1 // SPDX-License-Identifier: GPL-2.0-only
3 * Cadence MACB/GEM Ethernet Controller driver
5 * Copyright (C) 2004-2006 Atmel Corporation
8 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
10 #include <linux/clk-provider.h>
11 #include <linux/crc32.h>
12 #include <linux/module.h>
13 #include <linux/moduleparam.h>
14 #include <linux/kernel.h>
15 #include <linux/types.h>
16 #include <linux/circ_buf.h>
17 #include <linux/slab.h>
18 #include <linux/init.h>
20 #include <linux/gpio.h>
21 #include <linux/gpio/consumer.h>
22 #include <linux/interrupt.h>
23 #include <linux/netdevice.h>
24 #include <linux/etherdevice.h>
25 #include <linux/dma-mapping.h>
26 #include <linux/platform_device.h>
27 #include <linux/phylink.h>
29 #include <linux/of_device.h>
30 #include <linux/of_gpio.h>
31 #include <linux/of_mdio.h>
32 #include <linux/of_net.h>
34 #include <linux/udp.h>
35 #include <linux/tcp.h>
36 #include <linux/iopoll.h>
37 #include <linux/pm_runtime.h>
40 /* This structure is only used for MACB on SiFive FU540 devices */
41 struct sifive_fu540_macb_mgmt {
47 #define MACB_RX_BUFFER_SIZE 128
48 #define RX_BUFFER_MULTIPLE 64 /* bytes */
50 #define DEFAULT_RX_RING_SIZE 512 /* must be power of 2 */
51 #define MIN_RX_RING_SIZE 64
52 #define MAX_RX_RING_SIZE 8192
53 #define RX_RING_BYTES(bp) (macb_dma_desc_get_size(bp) \
56 #define DEFAULT_TX_RING_SIZE 512 /* must be power of 2 */
57 #define MIN_TX_RING_SIZE 64
58 #define MAX_TX_RING_SIZE 4096
59 #define TX_RING_BYTES(bp) (macb_dma_desc_get_size(bp) \
62 /* level of occupied TX descriptors under which we wake up TX process */
63 #define MACB_TX_WAKEUP_THRESH(bp) (3 * (bp)->tx_ring_size / 4)
65 #define MACB_RX_INT_FLAGS (MACB_BIT(RCOMP) | MACB_BIT(ISR_ROVR))
66 #define MACB_TX_ERR_FLAGS (MACB_BIT(ISR_TUND) \
69 #define MACB_TX_INT_FLAGS (MACB_TX_ERR_FLAGS | MACB_BIT(TCOMP) \
72 /* Max length of transmit frame must be a multiple of 8 bytes */
73 #define MACB_TX_LEN_ALIGN 8
74 #define MACB_MAX_TX_LEN ((unsigned int)((1 << MACB_TX_FRMLEN_SIZE) - 1) & ~((unsigned int)(MACB_TX_LEN_ALIGN - 1)))
75 /* Limit maximum TX length as per Cadence TSO errata. This is to avoid a
76 * false amba_error in TX path from the DMA assuming there is not enough
77 * space in the SRAM (16KB) even when there is.
79 #define GEM_MAX_TX_LEN (unsigned int)(0x3FC0)
81 #define GEM_MTU_MIN_SIZE ETH_MIN_MTU
82 #define MACB_NETIF_LSO NETIF_F_TSO
84 #define MACB_WOL_HAS_MAGIC_PACKET (0x1 << 0)
85 #define MACB_WOL_ENABLED (0x1 << 1)
87 #define HS_SPEED_10000M 4
88 #define MACB_SERDES_RATE_10G 1
90 /* Graceful stop timeouts in us. We should allow up to
91 * 1 frame time (10 Mbits/s, full-duplex, ignoring collisions)
93 #define MACB_HALT_TIMEOUT 1230
95 #define MACB_PM_TIMEOUT 100 /* ms */
97 #define MACB_MDIO_TIMEOUT 1000000 /* in usecs */
99 /* DMA buffer descriptor might be different size
100 * depends on hardware configuration:
102 * 1. dma address width 32 bits:
103 * word 1: 32 bit address of Data Buffer
106 * 2. dma address width 64 bits:
107 * word 1: 32 bit address of Data Buffer
109 * word 3: upper 32 bit address of Data Buffer
112 * 3. dma address width 32 bits with hardware timestamping:
113 * word 1: 32 bit address of Data Buffer
115 * word 3: timestamp word 1
116 * word 4: timestamp word 2
118 * 4. dma address width 64 bits with hardware timestamping:
119 * word 1: 32 bit address of Data Buffer
121 * word 3: upper 32 bit address of Data Buffer
123 * word 5: timestamp word 1
124 * word 6: timestamp word 2
126 static unsigned int macb_dma_desc_get_size(struct macb *bp)
129 unsigned int desc_size;
131 switch (bp->hw_dma_cap) {
133 desc_size = sizeof(struct macb_dma_desc)
134 + sizeof(struct macb_dma_desc_64);
137 desc_size = sizeof(struct macb_dma_desc)
138 + sizeof(struct macb_dma_desc_ptp);
140 case HW_DMA_CAP_64B_PTP:
141 desc_size = sizeof(struct macb_dma_desc)
142 + sizeof(struct macb_dma_desc_64)
143 + sizeof(struct macb_dma_desc_ptp);
146 desc_size = sizeof(struct macb_dma_desc);
150 return sizeof(struct macb_dma_desc);
153 static unsigned int macb_adj_dma_desc_idx(struct macb *bp, unsigned int desc_idx)
156 switch (bp->hw_dma_cap) {
161 case HW_DMA_CAP_64B_PTP:
171 #ifdef CONFIG_ARCH_DMA_ADDR_T_64BIT
172 static struct macb_dma_desc_64 *macb_64b_desc(struct macb *bp, struct macb_dma_desc *desc)
174 return (struct macb_dma_desc_64 *)((void *)desc
175 + sizeof(struct macb_dma_desc));
179 /* Ring buffer accessors */
180 static unsigned int macb_tx_ring_wrap(struct macb *bp, unsigned int index)
182 return index & (bp->tx_ring_size - 1);
185 static struct macb_dma_desc *macb_tx_desc(struct macb_queue *queue,
188 index = macb_tx_ring_wrap(queue->bp, index);
189 index = macb_adj_dma_desc_idx(queue->bp, index);
190 return &queue->tx_ring[index];
193 static struct macb_tx_skb *macb_tx_skb(struct macb_queue *queue,
196 return &queue->tx_skb[macb_tx_ring_wrap(queue->bp, index)];
199 static dma_addr_t macb_tx_dma(struct macb_queue *queue, unsigned int index)
203 offset = macb_tx_ring_wrap(queue->bp, index) *
204 macb_dma_desc_get_size(queue->bp);
206 return queue->tx_ring_dma + offset;
209 static unsigned int macb_rx_ring_wrap(struct macb *bp, unsigned int index)
211 return index & (bp->rx_ring_size - 1);
214 static struct macb_dma_desc *macb_rx_desc(struct macb_queue *queue, unsigned int index)
216 index = macb_rx_ring_wrap(queue->bp, index);
217 index = macb_adj_dma_desc_idx(queue->bp, index);
218 return &queue->rx_ring[index];
221 static void *macb_rx_buffer(struct macb_queue *queue, unsigned int index)
223 return queue->rx_buffers + queue->bp->rx_buffer_size *
224 macb_rx_ring_wrap(queue->bp, index);
228 static u32 hw_readl_native(struct macb *bp, int offset)
230 return __raw_readl(bp->regs + offset);
233 static void hw_writel_native(struct macb *bp, int offset, u32 value)
235 __raw_writel(value, bp->regs + offset);
238 static u32 hw_readl(struct macb *bp, int offset)
240 return readl_relaxed(bp->regs + offset);
243 static void hw_writel(struct macb *bp, int offset, u32 value)
245 writel_relaxed(value, bp->regs + offset);
248 /* Find the CPU endianness by using the loopback bit of NCR register. When the
249 * CPU is in big endian we need to program swapped mode for management
252 static bool hw_is_native_io(void __iomem *addr)
254 u32 value = MACB_BIT(LLB);
256 __raw_writel(value, addr + MACB_NCR);
257 value = __raw_readl(addr + MACB_NCR);
259 /* Write 0 back to disable everything */
260 __raw_writel(0, addr + MACB_NCR);
262 return value == MACB_BIT(LLB);
265 static bool hw_is_gem(void __iomem *addr, bool native_io)
270 id = __raw_readl(addr + MACB_MID);
272 id = readl_relaxed(addr + MACB_MID);
274 return MACB_BFEXT(IDNUM, id) >= 0x2;
277 static void macb_set_hwaddr(struct macb *bp)
282 bottom = cpu_to_le32(*((u32 *)bp->dev->dev_addr));
283 macb_or_gem_writel(bp, SA1B, bottom);
284 top = cpu_to_le16(*((u16 *)(bp->dev->dev_addr + 4)));
285 macb_or_gem_writel(bp, SA1T, top);
287 /* Clear unused address register sets */
288 macb_or_gem_writel(bp, SA2B, 0);
289 macb_or_gem_writel(bp, SA2T, 0);
290 macb_or_gem_writel(bp, SA3B, 0);
291 macb_or_gem_writel(bp, SA3T, 0);
292 macb_or_gem_writel(bp, SA4B, 0);
293 macb_or_gem_writel(bp, SA4T, 0);
296 static void macb_get_hwaddr(struct macb *bp)
303 /* Check all 4 address register for valid address */
304 for (i = 0; i < 4; i++) {
305 bottom = macb_or_gem_readl(bp, SA1B + i * 8);
306 top = macb_or_gem_readl(bp, SA1T + i * 8);
308 addr[0] = bottom & 0xff;
309 addr[1] = (bottom >> 8) & 0xff;
310 addr[2] = (bottom >> 16) & 0xff;
311 addr[3] = (bottom >> 24) & 0xff;
312 addr[4] = top & 0xff;
313 addr[5] = (top >> 8) & 0xff;
315 if (is_valid_ether_addr(addr)) {
316 memcpy(bp->dev->dev_addr, addr, sizeof(addr));
321 dev_info(&bp->pdev->dev, "invalid hw address, using random\n");
322 eth_hw_addr_random(bp->dev);
325 static int macb_mdio_wait_for_idle(struct macb *bp)
329 return readx_poll_timeout(MACB_READ_NSR, bp, val, val & MACB_BIT(IDLE),
330 1, MACB_MDIO_TIMEOUT);
333 static int macb_mdio_read(struct mii_bus *bus, int mii_id, int regnum)
335 struct macb *bp = bus->priv;
338 status = pm_runtime_get_sync(&bp->pdev->dev);
340 pm_runtime_put_noidle(&bp->pdev->dev);
344 status = macb_mdio_wait_for_idle(bp);
348 if (regnum & MII_ADDR_C45) {
349 macb_writel(bp, MAN, (MACB_BF(SOF, MACB_MAN_C45_SOF)
350 | MACB_BF(RW, MACB_MAN_C45_ADDR)
351 | MACB_BF(PHYA, mii_id)
352 | MACB_BF(REGA, (regnum >> 16) & 0x1F)
353 | MACB_BF(DATA, regnum & 0xFFFF)
354 | MACB_BF(CODE, MACB_MAN_C45_CODE)));
356 status = macb_mdio_wait_for_idle(bp);
360 macb_writel(bp, MAN, (MACB_BF(SOF, MACB_MAN_C45_SOF)
361 | MACB_BF(RW, MACB_MAN_C45_READ)
362 | MACB_BF(PHYA, mii_id)
363 | MACB_BF(REGA, (regnum >> 16) & 0x1F)
364 | MACB_BF(CODE, MACB_MAN_C45_CODE)));
366 macb_writel(bp, MAN, (MACB_BF(SOF, MACB_MAN_C22_SOF)
367 | MACB_BF(RW, MACB_MAN_C22_READ)
368 | MACB_BF(PHYA, mii_id)
369 | MACB_BF(REGA, regnum)
370 | MACB_BF(CODE, MACB_MAN_C22_CODE)));
373 status = macb_mdio_wait_for_idle(bp);
377 status = MACB_BFEXT(DATA, macb_readl(bp, MAN));
380 pm_runtime_mark_last_busy(&bp->pdev->dev);
381 pm_runtime_put_autosuspend(&bp->pdev->dev);
386 static int macb_mdio_write(struct mii_bus *bus, int mii_id, int regnum,
389 struct macb *bp = bus->priv;
392 status = pm_runtime_get_sync(&bp->pdev->dev);
394 pm_runtime_put_noidle(&bp->pdev->dev);
398 status = macb_mdio_wait_for_idle(bp);
400 goto mdio_write_exit;
402 if (regnum & MII_ADDR_C45) {
403 macb_writel(bp, MAN, (MACB_BF(SOF, MACB_MAN_C45_SOF)
404 | MACB_BF(RW, MACB_MAN_C45_ADDR)
405 | MACB_BF(PHYA, mii_id)
406 | MACB_BF(REGA, (regnum >> 16) & 0x1F)
407 | MACB_BF(DATA, regnum & 0xFFFF)
408 | MACB_BF(CODE, MACB_MAN_C45_CODE)));
410 status = macb_mdio_wait_for_idle(bp);
412 goto mdio_write_exit;
414 macb_writel(bp, MAN, (MACB_BF(SOF, MACB_MAN_C45_SOF)
415 | MACB_BF(RW, MACB_MAN_C45_WRITE)
416 | MACB_BF(PHYA, mii_id)
417 | MACB_BF(REGA, (regnum >> 16) & 0x1F)
418 | MACB_BF(CODE, MACB_MAN_C45_CODE)
419 | MACB_BF(DATA, value)));
421 macb_writel(bp, MAN, (MACB_BF(SOF, MACB_MAN_C22_SOF)
422 | MACB_BF(RW, MACB_MAN_C22_WRITE)
423 | MACB_BF(PHYA, mii_id)
424 | MACB_BF(REGA, regnum)
425 | MACB_BF(CODE, MACB_MAN_C22_CODE)
426 | MACB_BF(DATA, value)));
429 status = macb_mdio_wait_for_idle(bp);
431 goto mdio_write_exit;
434 pm_runtime_mark_last_busy(&bp->pdev->dev);
435 pm_runtime_put_autosuspend(&bp->pdev->dev);
440 static void macb_init_buffers(struct macb *bp)
442 struct macb_queue *queue;
445 for (q = 0, queue = bp->queues; q < bp->num_queues; ++q, ++queue) {
446 queue_writel(queue, RBQP, lower_32_bits(queue->rx_ring_dma));
447 #ifdef CONFIG_ARCH_DMA_ADDR_T_64BIT
448 if (bp->hw_dma_cap & HW_DMA_CAP_64B)
449 queue_writel(queue, RBQPH,
450 upper_32_bits(queue->rx_ring_dma));
452 queue_writel(queue, TBQP, lower_32_bits(queue->tx_ring_dma));
453 #ifdef CONFIG_ARCH_DMA_ADDR_T_64BIT
454 if (bp->hw_dma_cap & HW_DMA_CAP_64B)
455 queue_writel(queue, TBQPH,
456 upper_32_bits(queue->tx_ring_dma));
462 * macb_set_tx_clk() - Set a clock to a new frequency
463 * @bp: pointer to struct macb
464 * @speed: New frequency in Hz
466 static void macb_set_tx_clk(struct macb *bp, int speed)
468 long ferr, rate, rate_rounded;
470 if (!bp->tx_clk || (bp->caps & MACB_CAPS_CLK_HW_CHG))
473 /* In case of MII the PHY is the clock master */
474 if (bp->phy_interface == PHY_INTERFACE_MODE_MII)
491 rate_rounded = clk_round_rate(bp->tx_clk, rate);
492 if (rate_rounded < 0)
495 /* RGMII allows 50 ppm frequency error. Test and warn if this limit
498 ferr = abs(rate_rounded - rate);
499 ferr = DIV_ROUND_UP(ferr, rate / 100000);
502 "unable to generate target frequency: %ld Hz\n",
505 if (clk_set_rate(bp->tx_clk, rate_rounded))
506 netdev_err(bp->dev, "adjusting tx_clk failed.\n");
509 static void macb_validate(struct phylink_config *config,
510 unsigned long *supported,
511 struct phylink_link_state *state)
513 struct net_device *ndev = to_net_dev(config->dev);
514 __ETHTOOL_DECLARE_LINK_MODE_MASK(mask) = { 0, };
515 struct macb *bp = netdev_priv(ndev);
517 /* We only support MII, RMII, GMII, RGMII & SGMII. */
518 if (state->interface != PHY_INTERFACE_MODE_NA &&
519 state->interface != PHY_INTERFACE_MODE_MII &&
520 state->interface != PHY_INTERFACE_MODE_RMII &&
521 state->interface != PHY_INTERFACE_MODE_GMII &&
522 state->interface != PHY_INTERFACE_MODE_SGMII &&
523 state->interface != PHY_INTERFACE_MODE_10GBASER &&
524 !phy_interface_mode_is_rgmii(state->interface)) {
525 bitmap_zero(supported, __ETHTOOL_LINK_MODE_MASK_NBITS);
529 if (!macb_is_gem(bp) &&
530 (state->interface == PHY_INTERFACE_MODE_GMII ||
531 phy_interface_mode_is_rgmii(state->interface))) {
532 bitmap_zero(supported, __ETHTOOL_LINK_MODE_MASK_NBITS);
536 if (state->interface == PHY_INTERFACE_MODE_10GBASER &&
537 !(bp->caps & MACB_CAPS_HIGH_SPEED &&
538 bp->caps & MACB_CAPS_PCS)) {
539 bitmap_zero(supported, __ETHTOOL_LINK_MODE_MASK_NBITS);
543 phylink_set_port_modes(mask);
544 phylink_set(mask, Autoneg);
545 phylink_set(mask, Asym_Pause);
547 if (bp->caps & MACB_CAPS_GIGABIT_MODE_AVAILABLE &&
548 (state->interface == PHY_INTERFACE_MODE_NA ||
549 state->interface == PHY_INTERFACE_MODE_10GBASER)) {
550 phylink_set(mask, 10000baseCR_Full);
551 phylink_set(mask, 10000baseER_Full);
552 phylink_set(mask, 10000baseKR_Full);
553 phylink_set(mask, 10000baseLR_Full);
554 phylink_set(mask, 10000baseLRM_Full);
555 phylink_set(mask, 10000baseSR_Full);
556 phylink_set(mask, 10000baseT_Full);
557 if (state->interface != PHY_INTERFACE_MODE_NA)
561 phylink_set(mask, 10baseT_Half);
562 phylink_set(mask, 10baseT_Full);
563 phylink_set(mask, 100baseT_Half);
564 phylink_set(mask, 100baseT_Full);
566 if (bp->caps & MACB_CAPS_GIGABIT_MODE_AVAILABLE &&
567 (state->interface == PHY_INTERFACE_MODE_NA ||
568 state->interface == PHY_INTERFACE_MODE_GMII ||
569 state->interface == PHY_INTERFACE_MODE_SGMII ||
570 phy_interface_mode_is_rgmii(state->interface))) {
571 phylink_set(mask, 1000baseT_Full);
572 phylink_set(mask, 1000baseX_Full);
574 if (!(bp->caps & MACB_CAPS_NO_GIGABIT_HALF))
575 phylink_set(mask, 1000baseT_Half);
578 bitmap_and(supported, supported, mask, __ETHTOOL_LINK_MODE_MASK_NBITS);
579 bitmap_and(state->advertising, state->advertising, mask,
580 __ETHTOOL_LINK_MODE_MASK_NBITS);
583 static void macb_usx_pcs_link_up(struct phylink_pcs *pcs, unsigned int mode,
584 phy_interface_t interface, int speed,
587 struct macb *bp = container_of(pcs, struct macb, phylink_pcs);
590 config = gem_readl(bp, USX_CONTROL);
591 config = GEM_BFINS(SERDES_RATE, MACB_SERDES_RATE_10G, config);
592 config = GEM_BFINS(USX_CTRL_SPEED, HS_SPEED_10000M, config);
593 config &= ~(GEM_BIT(TX_SCR_BYPASS) | GEM_BIT(RX_SCR_BYPASS));
594 config |= GEM_BIT(TX_EN);
595 gem_writel(bp, USX_CONTROL, config);
598 static void macb_usx_pcs_get_state(struct phylink_pcs *pcs,
599 struct phylink_link_state *state)
601 struct macb *bp = container_of(pcs, struct macb, phylink_pcs);
604 state->speed = SPEED_10000;
606 state->an_complete = 1;
608 val = gem_readl(bp, USX_STATUS);
609 state->link = !!(val & GEM_BIT(USX_BLOCK_LOCK));
610 val = gem_readl(bp, NCFGR);
611 if (val & GEM_BIT(PAE))
612 state->pause = MLO_PAUSE_RX;
615 static int macb_usx_pcs_config(struct phylink_pcs *pcs,
617 phy_interface_t interface,
618 const unsigned long *advertising,
619 bool permit_pause_to_mac)
621 struct macb *bp = container_of(pcs, struct macb, phylink_pcs);
623 gem_writel(bp, USX_CONTROL, gem_readl(bp, USX_CONTROL) |
629 static void macb_pcs_get_state(struct phylink_pcs *pcs,
630 struct phylink_link_state *state)
635 static void macb_pcs_an_restart(struct phylink_pcs *pcs)
640 static int macb_pcs_config(struct phylink_pcs *pcs,
642 phy_interface_t interface,
643 const unsigned long *advertising,
644 bool permit_pause_to_mac)
649 static const struct phylink_pcs_ops macb_phylink_usx_pcs_ops = {
650 .pcs_get_state = macb_usx_pcs_get_state,
651 .pcs_config = macb_usx_pcs_config,
652 .pcs_link_up = macb_usx_pcs_link_up,
655 static const struct phylink_pcs_ops macb_phylink_pcs_ops = {
656 .pcs_get_state = macb_pcs_get_state,
657 .pcs_an_restart = macb_pcs_an_restart,
658 .pcs_config = macb_pcs_config,
661 static void macb_mac_config(struct phylink_config *config, unsigned int mode,
662 const struct phylink_link_state *state)
664 struct net_device *ndev = to_net_dev(config->dev);
665 struct macb *bp = netdev_priv(ndev);
670 spin_lock_irqsave(&bp->lock, flags);
672 old_ctrl = ctrl = macb_or_gem_readl(bp, NCFGR);
673 old_ncr = ncr = macb_or_gem_readl(bp, NCR);
675 if (bp->caps & MACB_CAPS_MACB_IS_EMAC) {
676 if (state->interface == PHY_INTERFACE_MODE_RMII)
677 ctrl |= MACB_BIT(RM9200_RMII);
678 } else if (macb_is_gem(bp)) {
679 ctrl &= ~(GEM_BIT(SGMIIEN) | GEM_BIT(PCSSEL));
680 ncr &= ~GEM_BIT(ENABLE_HS_MAC);
682 if (state->interface == PHY_INTERFACE_MODE_SGMII) {
683 ctrl |= GEM_BIT(SGMIIEN) | GEM_BIT(PCSSEL);
684 } else if (state->interface == PHY_INTERFACE_MODE_10GBASER) {
685 ctrl |= GEM_BIT(PCSSEL);
686 ncr |= GEM_BIT(ENABLE_HS_MAC);
690 /* Apply the new configuration, if any */
692 macb_or_gem_writel(bp, NCFGR, ctrl);
695 macb_or_gem_writel(bp, NCR, ncr);
697 spin_unlock_irqrestore(&bp->lock, flags);
700 static void macb_mac_link_down(struct phylink_config *config, unsigned int mode,
701 phy_interface_t interface)
703 struct net_device *ndev = to_net_dev(config->dev);
704 struct macb *bp = netdev_priv(ndev);
705 struct macb_queue *queue;
709 if (!(bp->caps & MACB_CAPS_MACB_IS_EMAC))
710 for (q = 0, queue = bp->queues; q < bp->num_queues; ++q, ++queue)
711 queue_writel(queue, IDR,
712 bp->rx_intr_mask | MACB_TX_INT_FLAGS | MACB_BIT(HRESP));
714 /* Disable Rx and Tx */
715 ctrl = macb_readl(bp, NCR) & ~(MACB_BIT(RE) | MACB_BIT(TE));
716 macb_writel(bp, NCR, ctrl);
718 netif_tx_stop_all_queues(ndev);
721 static void macb_mac_link_up(struct phylink_config *config,
722 struct phy_device *phy,
723 unsigned int mode, phy_interface_t interface,
724 int speed, int duplex,
725 bool tx_pause, bool rx_pause)
727 struct net_device *ndev = to_net_dev(config->dev);
728 struct macb *bp = netdev_priv(ndev);
729 struct macb_queue *queue;
734 spin_lock_irqsave(&bp->lock, flags);
736 ctrl = macb_or_gem_readl(bp, NCFGR);
738 ctrl &= ~(MACB_BIT(SPD) | MACB_BIT(FD));
740 if (speed == SPEED_100)
741 ctrl |= MACB_BIT(SPD);
744 ctrl |= MACB_BIT(FD);
746 if (!(bp->caps & MACB_CAPS_MACB_IS_EMAC)) {
747 ctrl &= ~MACB_BIT(PAE);
748 if (macb_is_gem(bp)) {
749 ctrl &= ~GEM_BIT(GBE);
751 if (speed == SPEED_1000)
752 ctrl |= GEM_BIT(GBE);
756 ctrl |= MACB_BIT(PAE);
758 macb_set_tx_clk(bp, speed);
760 /* Initialize rings & buffers as clearing MACB_BIT(TE) in link down
761 * cleared the pipeline and control registers.
763 bp->macbgem_ops.mog_init_rings(bp);
764 macb_init_buffers(bp);
766 for (q = 0, queue = bp->queues; q < bp->num_queues; ++q, ++queue)
767 queue_writel(queue, IER,
768 bp->rx_intr_mask | MACB_TX_INT_FLAGS | MACB_BIT(HRESP));
771 macb_or_gem_writel(bp, NCFGR, ctrl);
773 if (bp->phy_interface == PHY_INTERFACE_MODE_10GBASER)
774 gem_writel(bp, HS_MAC_CONFIG, GEM_BFINS(HS_MAC_SPEED, HS_SPEED_10000M,
775 gem_readl(bp, HS_MAC_CONFIG)));
777 spin_unlock_irqrestore(&bp->lock, flags);
779 /* Enable Rx and Tx */
780 macb_writel(bp, NCR, macb_readl(bp, NCR) | MACB_BIT(RE) | MACB_BIT(TE));
782 netif_tx_wake_all_queues(ndev);
785 static int macb_mac_prepare(struct phylink_config *config, unsigned int mode,
786 phy_interface_t interface)
788 struct net_device *ndev = to_net_dev(config->dev);
789 struct macb *bp = netdev_priv(ndev);
791 if (interface == PHY_INTERFACE_MODE_10GBASER)
792 bp->phylink_pcs.ops = &macb_phylink_usx_pcs_ops;
793 else if (interface == PHY_INTERFACE_MODE_SGMII)
794 bp->phylink_pcs.ops = &macb_phylink_pcs_ops;
796 bp->phylink_pcs.ops = NULL;
798 if (bp->phylink_pcs.ops)
799 phylink_set_pcs(bp->phylink, &bp->phylink_pcs);
804 static const struct phylink_mac_ops macb_phylink_ops = {
805 .validate = macb_validate,
806 .mac_prepare = macb_mac_prepare,
807 .mac_config = macb_mac_config,
808 .mac_link_down = macb_mac_link_down,
809 .mac_link_up = macb_mac_link_up,
812 static bool macb_phy_handle_exists(struct device_node *dn)
814 dn = of_parse_phandle(dn, "phy-handle", 0);
819 static int macb_phylink_connect(struct macb *bp)
821 struct device_node *dn = bp->pdev->dev.of_node;
822 struct net_device *dev = bp->dev;
823 struct phy_device *phydev;
827 ret = phylink_of_phy_connect(bp->phylink, dn, 0);
829 if (!dn || (ret && !macb_phy_handle_exists(dn))) {
830 phydev = phy_find_first(bp->mii_bus);
832 netdev_err(dev, "no PHY found\n");
836 /* attach the mac to the phy */
837 ret = phylink_connect_phy(bp->phylink, phydev);
841 netdev_err(dev, "Could not attach PHY (%d)\n", ret);
845 phylink_start(bp->phylink);
850 /* based on au1000_eth. c*/
851 static int macb_mii_probe(struct net_device *dev)
853 struct macb *bp = netdev_priv(dev);
855 bp->phylink_config.dev = &dev->dev;
856 bp->phylink_config.type = PHYLINK_NETDEV;
858 bp->phylink = phylink_create(&bp->phylink_config, bp->pdev->dev.fwnode,
859 bp->phy_interface, &macb_phylink_ops);
860 if (IS_ERR(bp->phylink)) {
861 netdev_err(dev, "Could not create a phylink instance (%ld)\n",
862 PTR_ERR(bp->phylink));
863 return PTR_ERR(bp->phylink);
869 static int macb_mdiobus_register(struct macb *bp)
871 struct device_node *child, *np = bp->pdev->dev.of_node;
873 if (of_phy_is_fixed_link(np))
874 return mdiobus_register(bp->mii_bus);
876 /* Only create the PHY from the device tree if at least one PHY is
877 * described. Otherwise scan the entire MDIO bus. We do this to support
878 * old device tree that did not follow the best practices and did not
879 * describe their network PHYs.
881 for_each_available_child_of_node(np, child)
882 if (of_mdiobus_child_is_phy(child)) {
883 /* The loop increments the child refcount,
884 * decrement it before returning.
888 return of_mdiobus_register(bp->mii_bus, np);
891 return mdiobus_register(bp->mii_bus);
894 static int macb_mii_init(struct macb *bp)
898 /* Enable management port */
899 macb_writel(bp, NCR, MACB_BIT(MPE));
901 bp->mii_bus = mdiobus_alloc();
907 bp->mii_bus->name = "MACB_mii_bus";
908 bp->mii_bus->read = &macb_mdio_read;
909 bp->mii_bus->write = &macb_mdio_write;
910 snprintf(bp->mii_bus->id, MII_BUS_ID_SIZE, "%s-%x",
911 bp->pdev->name, bp->pdev->id);
912 bp->mii_bus->priv = bp;
913 bp->mii_bus->parent = &bp->pdev->dev;
915 dev_set_drvdata(&bp->dev->dev, bp->mii_bus);
917 err = macb_mdiobus_register(bp);
919 goto err_out_free_mdiobus;
921 err = macb_mii_probe(bp->dev);
923 goto err_out_unregister_bus;
927 err_out_unregister_bus:
928 mdiobus_unregister(bp->mii_bus);
929 err_out_free_mdiobus:
930 mdiobus_free(bp->mii_bus);
935 static void macb_update_stats(struct macb *bp)
937 u32 *p = &bp->hw_stats.macb.rx_pause_frames;
938 u32 *end = &bp->hw_stats.macb.tx_pause_frames + 1;
939 int offset = MACB_PFR;
941 WARN_ON((unsigned long)(end - p - 1) != (MACB_TPF - MACB_PFR) / 4);
943 for (; p < end; p++, offset += 4)
944 *p += bp->macb_reg_readl(bp, offset);
947 static int macb_halt_tx(struct macb *bp)
949 unsigned long halt_time, timeout;
952 macb_writel(bp, NCR, macb_readl(bp, NCR) | MACB_BIT(THALT));
954 timeout = jiffies + usecs_to_jiffies(MACB_HALT_TIMEOUT);
957 status = macb_readl(bp, TSR);
958 if (!(status & MACB_BIT(TGO)))
962 } while (time_before(halt_time, timeout));
967 static void macb_tx_unmap(struct macb *bp, struct macb_tx_skb *tx_skb)
969 if (tx_skb->mapping) {
970 if (tx_skb->mapped_as_page)
971 dma_unmap_page(&bp->pdev->dev, tx_skb->mapping,
972 tx_skb->size, DMA_TO_DEVICE);
974 dma_unmap_single(&bp->pdev->dev, tx_skb->mapping,
975 tx_skb->size, DMA_TO_DEVICE);
980 dev_kfree_skb_any(tx_skb->skb);
985 static void macb_set_addr(struct macb *bp, struct macb_dma_desc *desc, dma_addr_t addr)
987 #ifdef CONFIG_ARCH_DMA_ADDR_T_64BIT
988 struct macb_dma_desc_64 *desc_64;
990 if (bp->hw_dma_cap & HW_DMA_CAP_64B) {
991 desc_64 = macb_64b_desc(bp, desc);
992 desc_64->addrh = upper_32_bits(addr);
993 /* The low bits of RX address contain the RX_USED bit, clearing
994 * of which allows packet RX. Make sure the high bits are also
995 * visible to HW at that point.
1000 desc->addr = lower_32_bits(addr);
1003 static dma_addr_t macb_get_addr(struct macb *bp, struct macb_dma_desc *desc)
1005 dma_addr_t addr = 0;
1006 #ifdef CONFIG_ARCH_DMA_ADDR_T_64BIT
1007 struct macb_dma_desc_64 *desc_64;
1009 if (bp->hw_dma_cap & HW_DMA_CAP_64B) {
1010 desc_64 = macb_64b_desc(bp, desc);
1011 addr = ((u64)(desc_64->addrh) << 32);
1014 addr |= MACB_BF(RX_WADDR, MACB_BFEXT(RX_WADDR, desc->addr));
1018 static void macb_tx_error_task(struct work_struct *work)
1020 struct macb_queue *queue = container_of(work, struct macb_queue,
1022 struct macb *bp = queue->bp;
1023 struct macb_tx_skb *tx_skb;
1024 struct macb_dma_desc *desc;
1025 struct sk_buff *skb;
1027 unsigned long flags;
1029 netdev_vdbg(bp->dev, "macb_tx_error_task: q = %u, t = %u, h = %u\n",
1030 (unsigned int)(queue - bp->queues),
1031 queue->tx_tail, queue->tx_head);
1033 /* Prevent the queue IRQ handlers from running: each of them may call
1034 * macb_tx_interrupt(), which in turn may call netif_wake_subqueue().
1035 * As explained below, we have to halt the transmission before updating
1036 * TBQP registers so we call netif_tx_stop_all_queues() to notify the
1037 * network engine about the macb/gem being halted.
1039 spin_lock_irqsave(&bp->lock, flags);
1041 /* Make sure nobody is trying to queue up new packets */
1042 netif_tx_stop_all_queues(bp->dev);
1044 /* Stop transmission now
1045 * (in case we have just queued new packets)
1046 * macb/gem must be halted to write TBQP register
1048 if (macb_halt_tx(bp))
1049 /* Just complain for now, reinitializing TX path can be good */
1050 netdev_err(bp->dev, "BUG: halt tx timed out\n");
1052 /* Treat frames in TX queue including the ones that caused the error.
1053 * Free transmit buffers in upper layer.
1055 for (tail = queue->tx_tail; tail != queue->tx_head; tail++) {
1058 desc = macb_tx_desc(queue, tail);
1060 tx_skb = macb_tx_skb(queue, tail);
1063 if (ctrl & MACB_BIT(TX_USED)) {
1064 /* skb is set for the last buffer of the frame */
1066 macb_tx_unmap(bp, tx_skb);
1068 tx_skb = macb_tx_skb(queue, tail);
1072 /* ctrl still refers to the first buffer descriptor
1073 * since it's the only one written back by the hardware
1075 if (!(ctrl & MACB_BIT(TX_BUF_EXHAUSTED))) {
1076 netdev_vdbg(bp->dev, "txerr skb %u (data %p) TX complete\n",
1077 macb_tx_ring_wrap(bp, tail),
1079 bp->dev->stats.tx_packets++;
1080 queue->stats.tx_packets++;
1081 bp->dev->stats.tx_bytes += skb->len;
1082 queue->stats.tx_bytes += skb->len;
1085 /* "Buffers exhausted mid-frame" errors may only happen
1086 * if the driver is buggy, so complain loudly about
1087 * those. Statistics are updated by hardware.
1089 if (ctrl & MACB_BIT(TX_BUF_EXHAUSTED))
1091 "BUG: TX buffers exhausted mid-frame\n");
1093 desc->ctrl = ctrl | MACB_BIT(TX_USED);
1096 macb_tx_unmap(bp, tx_skb);
1099 /* Set end of TX queue */
1100 desc = macb_tx_desc(queue, 0);
1101 macb_set_addr(bp, desc, 0);
1102 desc->ctrl = MACB_BIT(TX_USED);
1104 /* Make descriptor updates visible to hardware */
1107 /* Reinitialize the TX desc queue */
1108 queue_writel(queue, TBQP, lower_32_bits(queue->tx_ring_dma));
1109 #ifdef CONFIG_ARCH_DMA_ADDR_T_64BIT
1110 if (bp->hw_dma_cap & HW_DMA_CAP_64B)
1111 queue_writel(queue, TBQPH, upper_32_bits(queue->tx_ring_dma));
1113 /* Make TX ring reflect state of hardware */
1117 /* Housework before enabling TX IRQ */
1118 macb_writel(bp, TSR, macb_readl(bp, TSR));
1119 queue_writel(queue, IER, MACB_TX_INT_FLAGS);
1121 /* Now we are ready to start transmission again */
1122 netif_tx_start_all_queues(bp->dev);
1123 macb_writel(bp, NCR, macb_readl(bp, NCR) | MACB_BIT(TSTART));
1125 spin_unlock_irqrestore(&bp->lock, flags);
1128 static void macb_tx_interrupt(struct macb_queue *queue)
1133 struct macb *bp = queue->bp;
1134 u16 queue_index = queue - bp->queues;
1136 status = macb_readl(bp, TSR);
1137 macb_writel(bp, TSR, status);
1139 if (bp->caps & MACB_CAPS_ISR_CLEAR_ON_WRITE)
1140 queue_writel(queue, ISR, MACB_BIT(TCOMP));
1142 netdev_vdbg(bp->dev, "macb_tx_interrupt status = 0x%03lx\n",
1143 (unsigned long)status);
1145 head = queue->tx_head;
1146 for (tail = queue->tx_tail; tail != head; tail++) {
1147 struct macb_tx_skb *tx_skb;
1148 struct sk_buff *skb;
1149 struct macb_dma_desc *desc;
1152 desc = macb_tx_desc(queue, tail);
1154 /* Make hw descriptor updates visible to CPU */
1159 /* TX_USED bit is only set by hardware on the very first buffer
1160 * descriptor of the transmitted frame.
1162 if (!(ctrl & MACB_BIT(TX_USED)))
1165 /* Process all buffers of the current transmitted frame */
1167 tx_skb = macb_tx_skb(queue, tail);
1170 /* First, update TX stats if needed */
1172 if (unlikely(skb_shinfo(skb)->tx_flags &
1174 gem_ptp_do_txstamp(queue, skb, desc) == 0) {
1175 /* skb now belongs to timestamp buffer
1176 * and will be removed later
1180 netdev_vdbg(bp->dev, "skb %u (data %p) TX complete\n",
1181 macb_tx_ring_wrap(bp, tail),
1183 bp->dev->stats.tx_packets++;
1184 queue->stats.tx_packets++;
1185 bp->dev->stats.tx_bytes += skb->len;
1186 queue->stats.tx_bytes += skb->len;
1189 /* Now we can safely release resources */
1190 macb_tx_unmap(bp, tx_skb);
1192 /* skb is set only for the last buffer of the frame.
1193 * WARNING: at this point skb has been freed by
1201 queue->tx_tail = tail;
1202 if (__netif_subqueue_stopped(bp->dev, queue_index) &&
1203 CIRC_CNT(queue->tx_head, queue->tx_tail,
1204 bp->tx_ring_size) <= MACB_TX_WAKEUP_THRESH(bp))
1205 netif_wake_subqueue(bp->dev, queue_index);
1208 static void gem_rx_refill(struct macb_queue *queue)
1211 struct sk_buff *skb;
1213 struct macb *bp = queue->bp;
1214 struct macb_dma_desc *desc;
1216 while (CIRC_SPACE(queue->rx_prepared_head, queue->rx_tail,
1217 bp->rx_ring_size) > 0) {
1218 entry = macb_rx_ring_wrap(bp, queue->rx_prepared_head);
1220 /* Make hw descriptor updates visible to CPU */
1223 queue->rx_prepared_head++;
1224 desc = macb_rx_desc(queue, entry);
1226 if (!queue->rx_skbuff[entry]) {
1227 /* allocate sk_buff for this free entry in ring */
1228 skb = netdev_alloc_skb(bp->dev, bp->rx_buffer_size);
1229 if (unlikely(!skb)) {
1231 "Unable to allocate sk_buff\n");
1235 /* now fill corresponding descriptor entry */
1236 paddr = dma_map_single(&bp->pdev->dev, skb->data,
1239 if (dma_mapping_error(&bp->pdev->dev, paddr)) {
1244 queue->rx_skbuff[entry] = skb;
1246 if (entry == bp->rx_ring_size - 1)
1247 paddr |= MACB_BIT(RX_WRAP);
1249 /* Setting addr clears RX_USED and allows reception,
1250 * make sure ctrl is cleared first to avoid a race.
1253 macb_set_addr(bp, desc, paddr);
1255 /* properly align Ethernet header */
1256 skb_reserve(skb, NET_IP_ALIGN);
1260 desc->addr &= ~MACB_BIT(RX_USED);
1264 /* Make descriptor updates visible to hardware */
1267 netdev_vdbg(bp->dev, "rx ring: queue: %p, prepared head %d, tail %d\n",
1268 queue, queue->rx_prepared_head, queue->rx_tail);
1271 /* Mark DMA descriptors from begin up to and not including end as unused */
1272 static void discard_partial_frame(struct macb_queue *queue, unsigned int begin,
1277 for (frag = begin; frag != end; frag++) {
1278 struct macb_dma_desc *desc = macb_rx_desc(queue, frag);
1280 desc->addr &= ~MACB_BIT(RX_USED);
1283 /* Make descriptor updates visible to hardware */
1286 /* When this happens, the hardware stats registers for
1287 * whatever caused this is updated, so we don't have to record
1292 static int gem_rx(struct macb_queue *queue, struct napi_struct *napi,
1295 struct macb *bp = queue->bp;
1298 struct sk_buff *skb;
1299 struct macb_dma_desc *desc;
1302 while (count < budget) {
1307 entry = macb_rx_ring_wrap(bp, queue->rx_tail);
1308 desc = macb_rx_desc(queue, entry);
1310 /* Make hw descriptor updates visible to CPU */
1313 rxused = (desc->addr & MACB_BIT(RX_USED)) ? true : false;
1314 addr = macb_get_addr(bp, desc);
1319 /* Ensure ctrl is at least as up-to-date as rxused */
1327 if (!(ctrl & MACB_BIT(RX_SOF) && ctrl & MACB_BIT(RX_EOF))) {
1329 "not whole frame pointed by descriptor\n");
1330 bp->dev->stats.rx_dropped++;
1331 queue->stats.rx_dropped++;
1334 skb = queue->rx_skbuff[entry];
1335 if (unlikely(!skb)) {
1337 "inconsistent Rx descriptor chain\n");
1338 bp->dev->stats.rx_dropped++;
1339 queue->stats.rx_dropped++;
1342 /* now everything is ready for receiving packet */
1343 queue->rx_skbuff[entry] = NULL;
1344 len = ctrl & bp->rx_frm_len_mask;
1346 netdev_vdbg(bp->dev, "gem_rx %u (len %u)\n", entry, len);
1349 dma_unmap_single(&bp->pdev->dev, addr,
1350 bp->rx_buffer_size, DMA_FROM_DEVICE);
1352 skb->protocol = eth_type_trans(skb, bp->dev);
1353 skb_checksum_none_assert(skb);
1354 if (bp->dev->features & NETIF_F_RXCSUM &&
1355 !(bp->dev->flags & IFF_PROMISC) &&
1356 GEM_BFEXT(RX_CSUM, ctrl) & GEM_RX_CSUM_CHECKED_MASK)
1357 skb->ip_summed = CHECKSUM_UNNECESSARY;
1359 bp->dev->stats.rx_packets++;
1360 queue->stats.rx_packets++;
1361 bp->dev->stats.rx_bytes += skb->len;
1362 queue->stats.rx_bytes += skb->len;
1364 gem_ptp_do_rxstamp(bp, skb, desc);
1366 #if defined(DEBUG) && defined(VERBOSE_DEBUG)
1367 netdev_vdbg(bp->dev, "received skb of length %u, csum: %08x\n",
1368 skb->len, skb->csum);
1369 print_hex_dump(KERN_DEBUG, " mac: ", DUMP_PREFIX_ADDRESS, 16, 1,
1370 skb_mac_header(skb), 16, true);
1371 print_hex_dump(KERN_DEBUG, "data: ", DUMP_PREFIX_ADDRESS, 16, 1,
1372 skb->data, 32, true);
1375 napi_gro_receive(napi, skb);
1378 gem_rx_refill(queue);
1383 static int macb_rx_frame(struct macb_queue *queue, struct napi_struct *napi,
1384 unsigned int first_frag, unsigned int last_frag)
1388 unsigned int offset;
1389 struct sk_buff *skb;
1390 struct macb_dma_desc *desc;
1391 struct macb *bp = queue->bp;
1393 desc = macb_rx_desc(queue, last_frag);
1394 len = desc->ctrl & bp->rx_frm_len_mask;
1396 netdev_vdbg(bp->dev, "macb_rx_frame frags %u - %u (len %u)\n",
1397 macb_rx_ring_wrap(bp, first_frag),
1398 macb_rx_ring_wrap(bp, last_frag), len);
1400 /* The ethernet header starts NET_IP_ALIGN bytes into the
1401 * first buffer. Since the header is 14 bytes, this makes the
1402 * payload word-aligned.
1404 * Instead of calling skb_reserve(NET_IP_ALIGN), we just copy
1405 * the two padding bytes into the skb so that we avoid hitting
1406 * the slowpath in memcpy(), and pull them off afterwards.
1408 skb = netdev_alloc_skb(bp->dev, len + NET_IP_ALIGN);
1410 bp->dev->stats.rx_dropped++;
1411 for (frag = first_frag; ; frag++) {
1412 desc = macb_rx_desc(queue, frag);
1413 desc->addr &= ~MACB_BIT(RX_USED);
1414 if (frag == last_frag)
1418 /* Make descriptor updates visible to hardware */
1425 len += NET_IP_ALIGN;
1426 skb_checksum_none_assert(skb);
1429 for (frag = first_frag; ; frag++) {
1430 unsigned int frag_len = bp->rx_buffer_size;
1432 if (offset + frag_len > len) {
1433 if (unlikely(frag != last_frag)) {
1434 dev_kfree_skb_any(skb);
1437 frag_len = len - offset;
1439 skb_copy_to_linear_data_offset(skb, offset,
1440 macb_rx_buffer(queue, frag),
1442 offset += bp->rx_buffer_size;
1443 desc = macb_rx_desc(queue, frag);
1444 desc->addr &= ~MACB_BIT(RX_USED);
1446 if (frag == last_frag)
1450 /* Make descriptor updates visible to hardware */
1453 __skb_pull(skb, NET_IP_ALIGN);
1454 skb->protocol = eth_type_trans(skb, bp->dev);
1456 bp->dev->stats.rx_packets++;
1457 bp->dev->stats.rx_bytes += skb->len;
1458 netdev_vdbg(bp->dev, "received skb of length %u, csum: %08x\n",
1459 skb->len, skb->csum);
1460 napi_gro_receive(napi, skb);
1465 static inline void macb_init_rx_ring(struct macb_queue *queue)
1467 struct macb *bp = queue->bp;
1469 struct macb_dma_desc *desc = NULL;
1472 addr = queue->rx_buffers_dma;
1473 for (i = 0; i < bp->rx_ring_size; i++) {
1474 desc = macb_rx_desc(queue, i);
1475 macb_set_addr(bp, desc, addr);
1477 addr += bp->rx_buffer_size;
1479 desc->addr |= MACB_BIT(RX_WRAP);
1483 static int macb_rx(struct macb_queue *queue, struct napi_struct *napi,
1486 struct macb *bp = queue->bp;
1487 bool reset_rx_queue = false;
1490 int first_frag = -1;
1492 for (tail = queue->rx_tail; budget > 0; tail++) {
1493 struct macb_dma_desc *desc = macb_rx_desc(queue, tail);
1496 /* Make hw descriptor updates visible to CPU */
1499 if (!(desc->addr & MACB_BIT(RX_USED)))
1502 /* Ensure ctrl is at least as up-to-date as addr */
1507 if (ctrl & MACB_BIT(RX_SOF)) {
1508 if (first_frag != -1)
1509 discard_partial_frame(queue, first_frag, tail);
1513 if (ctrl & MACB_BIT(RX_EOF)) {
1516 if (unlikely(first_frag == -1)) {
1517 reset_rx_queue = true;
1521 dropped = macb_rx_frame(queue, napi, first_frag, tail);
1523 if (unlikely(dropped < 0)) {
1524 reset_rx_queue = true;
1534 if (unlikely(reset_rx_queue)) {
1535 unsigned long flags;
1538 netdev_err(bp->dev, "RX queue corruption: reset it\n");
1540 spin_lock_irqsave(&bp->lock, flags);
1542 ctrl = macb_readl(bp, NCR);
1543 macb_writel(bp, NCR, ctrl & ~MACB_BIT(RE));
1545 macb_init_rx_ring(queue);
1546 queue_writel(queue, RBQP, queue->rx_ring_dma);
1548 macb_writel(bp, NCR, ctrl | MACB_BIT(RE));
1550 spin_unlock_irqrestore(&bp->lock, flags);
1554 if (first_frag != -1)
1555 queue->rx_tail = first_frag;
1557 queue->rx_tail = tail;
1562 static int macb_poll(struct napi_struct *napi, int budget)
1564 struct macb_queue *queue = container_of(napi, struct macb_queue, napi);
1565 struct macb *bp = queue->bp;
1569 status = macb_readl(bp, RSR);
1570 macb_writel(bp, RSR, status);
1572 netdev_vdbg(bp->dev, "poll: status = %08lx, budget = %d\n",
1573 (unsigned long)status, budget);
1575 work_done = bp->macbgem_ops.mog_rx(queue, napi, budget);
1576 if (work_done < budget) {
1577 napi_complete_done(napi, work_done);
1579 /* Packets received while interrupts were disabled */
1580 status = macb_readl(bp, RSR);
1582 if (bp->caps & MACB_CAPS_ISR_CLEAR_ON_WRITE)
1583 queue_writel(queue, ISR, MACB_BIT(RCOMP));
1584 napi_reschedule(napi);
1586 queue_writel(queue, IER, bp->rx_intr_mask);
1590 /* TODO: Handle errors */
1595 static void macb_hresp_error_task(struct tasklet_struct *t)
1597 struct macb *bp = from_tasklet(bp, t, hresp_err_tasklet);
1598 struct net_device *dev = bp->dev;
1599 struct macb_queue *queue;
1603 for (q = 0, queue = bp->queues; q < bp->num_queues; ++q, ++queue) {
1604 queue_writel(queue, IDR, bp->rx_intr_mask |
1608 ctrl = macb_readl(bp, NCR);
1609 ctrl &= ~(MACB_BIT(RE) | MACB_BIT(TE));
1610 macb_writel(bp, NCR, ctrl);
1612 netif_tx_stop_all_queues(dev);
1613 netif_carrier_off(dev);
1615 bp->macbgem_ops.mog_init_rings(bp);
1617 /* Initialize TX and RX buffers */
1618 macb_init_buffers(bp);
1620 /* Enable interrupts */
1621 for (q = 0, queue = bp->queues; q < bp->num_queues; ++q, ++queue)
1622 queue_writel(queue, IER,
1627 ctrl |= MACB_BIT(RE) | MACB_BIT(TE);
1628 macb_writel(bp, NCR, ctrl);
1630 netif_carrier_on(dev);
1631 netif_tx_start_all_queues(dev);
1634 static void macb_tx_restart(struct macb_queue *queue)
1636 unsigned int head = queue->tx_head;
1637 unsigned int tail = queue->tx_tail;
1638 struct macb *bp = queue->bp;
1640 if (bp->caps & MACB_CAPS_ISR_CLEAR_ON_WRITE)
1641 queue_writel(queue, ISR, MACB_BIT(TXUBR));
1646 macb_writel(bp, NCR, macb_readl(bp, NCR) | MACB_BIT(TSTART));
1649 static irqreturn_t macb_wol_interrupt(int irq, void *dev_id)
1651 struct macb_queue *queue = dev_id;
1652 struct macb *bp = queue->bp;
1655 status = queue_readl(queue, ISR);
1657 if (unlikely(!status))
1660 spin_lock(&bp->lock);
1662 if (status & MACB_BIT(WOL)) {
1663 queue_writel(queue, IDR, MACB_BIT(WOL));
1664 macb_writel(bp, WOL, 0);
1665 netdev_vdbg(bp->dev, "MACB WoL: queue = %u, isr = 0x%08lx\n",
1666 (unsigned int)(queue - bp->queues),
1667 (unsigned long)status);
1668 if (bp->caps & MACB_CAPS_ISR_CLEAR_ON_WRITE)
1669 queue_writel(queue, ISR, MACB_BIT(WOL));
1670 pm_wakeup_event(&bp->pdev->dev, 0);
1673 spin_unlock(&bp->lock);
1678 static irqreturn_t gem_wol_interrupt(int irq, void *dev_id)
1680 struct macb_queue *queue = dev_id;
1681 struct macb *bp = queue->bp;
1684 status = queue_readl(queue, ISR);
1686 if (unlikely(!status))
1689 spin_lock(&bp->lock);
1691 if (status & GEM_BIT(WOL)) {
1692 queue_writel(queue, IDR, GEM_BIT(WOL));
1693 gem_writel(bp, WOL, 0);
1694 netdev_vdbg(bp->dev, "GEM WoL: queue = %u, isr = 0x%08lx\n",
1695 (unsigned int)(queue - bp->queues),
1696 (unsigned long)status);
1697 if (bp->caps & MACB_CAPS_ISR_CLEAR_ON_WRITE)
1698 queue_writel(queue, ISR, GEM_BIT(WOL));
1699 pm_wakeup_event(&bp->pdev->dev, 0);
1702 spin_unlock(&bp->lock);
1707 static irqreturn_t macb_interrupt(int irq, void *dev_id)
1709 struct macb_queue *queue = dev_id;
1710 struct macb *bp = queue->bp;
1711 struct net_device *dev = bp->dev;
1714 status = queue_readl(queue, ISR);
1716 if (unlikely(!status))
1719 spin_lock(&bp->lock);
1722 /* close possible race with dev_close */
1723 if (unlikely(!netif_running(dev))) {
1724 queue_writel(queue, IDR, -1);
1725 if (bp->caps & MACB_CAPS_ISR_CLEAR_ON_WRITE)
1726 queue_writel(queue, ISR, -1);
1730 netdev_vdbg(bp->dev, "queue = %u, isr = 0x%08lx\n",
1731 (unsigned int)(queue - bp->queues),
1732 (unsigned long)status);
1734 if (status & bp->rx_intr_mask) {
1735 /* There's no point taking any more interrupts
1736 * until we have processed the buffers. The
1737 * scheduling call may fail if the poll routine
1738 * is already scheduled, so disable interrupts
1741 queue_writel(queue, IDR, bp->rx_intr_mask);
1742 if (bp->caps & MACB_CAPS_ISR_CLEAR_ON_WRITE)
1743 queue_writel(queue, ISR, MACB_BIT(RCOMP));
1745 if (napi_schedule_prep(&queue->napi)) {
1746 netdev_vdbg(bp->dev, "scheduling RX softirq\n");
1747 __napi_schedule(&queue->napi);
1751 if (unlikely(status & (MACB_TX_ERR_FLAGS))) {
1752 queue_writel(queue, IDR, MACB_TX_INT_FLAGS);
1753 schedule_work(&queue->tx_error_task);
1755 if (bp->caps & MACB_CAPS_ISR_CLEAR_ON_WRITE)
1756 queue_writel(queue, ISR, MACB_TX_ERR_FLAGS);
1761 if (status & MACB_BIT(TCOMP))
1762 macb_tx_interrupt(queue);
1764 if (status & MACB_BIT(TXUBR))
1765 macb_tx_restart(queue);
1767 /* Link change detection isn't possible with RMII, so we'll
1768 * add that if/when we get our hands on a full-blown MII PHY.
1771 /* There is a hardware issue under heavy load where DMA can
1772 * stop, this causes endless "used buffer descriptor read"
1773 * interrupts but it can be cleared by re-enabling RX. See
1774 * the at91rm9200 manual, section 41.3.1 or the Zynq manual
1775 * section 16.7.4 for details. RXUBR is only enabled for
1776 * these two versions.
1778 if (status & MACB_BIT(RXUBR)) {
1779 ctrl = macb_readl(bp, NCR);
1780 macb_writel(bp, NCR, ctrl & ~MACB_BIT(RE));
1782 macb_writel(bp, NCR, ctrl | MACB_BIT(RE));
1784 if (bp->caps & MACB_CAPS_ISR_CLEAR_ON_WRITE)
1785 queue_writel(queue, ISR, MACB_BIT(RXUBR));
1788 if (status & MACB_BIT(ISR_ROVR)) {
1789 /* We missed at least one packet */
1790 if (macb_is_gem(bp))
1791 bp->hw_stats.gem.rx_overruns++;
1793 bp->hw_stats.macb.rx_overruns++;
1795 if (bp->caps & MACB_CAPS_ISR_CLEAR_ON_WRITE)
1796 queue_writel(queue, ISR, MACB_BIT(ISR_ROVR));
1799 if (status & MACB_BIT(HRESP)) {
1800 tasklet_schedule(&bp->hresp_err_tasklet);
1801 netdev_err(dev, "DMA bus error: HRESP not OK\n");
1803 if (bp->caps & MACB_CAPS_ISR_CLEAR_ON_WRITE)
1804 queue_writel(queue, ISR, MACB_BIT(HRESP));
1806 status = queue_readl(queue, ISR);
1809 spin_unlock(&bp->lock);
1814 #ifdef CONFIG_NET_POLL_CONTROLLER
1815 /* Polling receive - used by netconsole and other diagnostic tools
1816 * to allow network i/o with interrupts disabled.
1818 static void macb_poll_controller(struct net_device *dev)
1820 struct macb *bp = netdev_priv(dev);
1821 struct macb_queue *queue;
1822 unsigned long flags;
1825 local_irq_save(flags);
1826 for (q = 0, queue = bp->queues; q < bp->num_queues; ++q, ++queue)
1827 macb_interrupt(dev->irq, queue);
1828 local_irq_restore(flags);
1832 static unsigned int macb_tx_map(struct macb *bp,
1833 struct macb_queue *queue,
1834 struct sk_buff *skb,
1835 unsigned int hdrlen)
1838 unsigned int len, entry, i, tx_head = queue->tx_head;
1839 struct macb_tx_skb *tx_skb = NULL;
1840 struct macb_dma_desc *desc;
1841 unsigned int offset, size, count = 0;
1842 unsigned int f, nr_frags = skb_shinfo(skb)->nr_frags;
1843 unsigned int eof = 1, mss_mfs = 0;
1844 u32 ctrl, lso_ctrl = 0, seq_ctrl = 0;
1847 if (skb_shinfo(skb)->gso_size != 0) {
1848 if (ip_hdr(skb)->protocol == IPPROTO_UDP)
1850 lso_ctrl = MACB_LSO_UFO_ENABLE;
1853 lso_ctrl = MACB_LSO_TSO_ENABLE;
1856 /* First, map non-paged data */
1857 len = skb_headlen(skb);
1859 /* first buffer length */
1864 entry = macb_tx_ring_wrap(bp, tx_head);
1865 tx_skb = &queue->tx_skb[entry];
1867 mapping = dma_map_single(&bp->pdev->dev,
1869 size, DMA_TO_DEVICE);
1870 if (dma_mapping_error(&bp->pdev->dev, mapping))
1873 /* Save info to properly release resources */
1875 tx_skb->mapping = mapping;
1876 tx_skb->size = size;
1877 tx_skb->mapped_as_page = false;
1884 size = min(len, bp->max_tx_length);
1887 /* Then, map paged data from fragments */
1888 for (f = 0; f < nr_frags; f++) {
1889 const skb_frag_t *frag = &skb_shinfo(skb)->frags[f];
1891 len = skb_frag_size(frag);
1894 size = min(len, bp->max_tx_length);
1895 entry = macb_tx_ring_wrap(bp, tx_head);
1896 tx_skb = &queue->tx_skb[entry];
1898 mapping = skb_frag_dma_map(&bp->pdev->dev, frag,
1899 offset, size, DMA_TO_DEVICE);
1900 if (dma_mapping_error(&bp->pdev->dev, mapping))
1903 /* Save info to properly release resources */
1905 tx_skb->mapping = mapping;
1906 tx_skb->size = size;
1907 tx_skb->mapped_as_page = true;
1916 /* Should never happen */
1917 if (unlikely(!tx_skb)) {
1918 netdev_err(bp->dev, "BUG! empty skb!\n");
1922 /* This is the last buffer of the frame: save socket buffer */
1925 /* Update TX ring: update buffer descriptors in reverse order
1926 * to avoid race condition
1929 /* Set 'TX_USED' bit in buffer descriptor at tx_head position
1930 * to set the end of TX queue
1933 entry = macb_tx_ring_wrap(bp, i);
1934 ctrl = MACB_BIT(TX_USED);
1935 desc = macb_tx_desc(queue, entry);
1939 if (lso_ctrl == MACB_LSO_UFO_ENABLE)
1940 /* include header and FCS in value given to h/w */
1941 mss_mfs = skb_shinfo(skb)->gso_size +
1942 skb_transport_offset(skb) +
1945 mss_mfs = skb_shinfo(skb)->gso_size;
1946 /* TCP Sequence Number Source Select
1947 * can be set only for TSO
1955 entry = macb_tx_ring_wrap(bp, i);
1956 tx_skb = &queue->tx_skb[entry];
1957 desc = macb_tx_desc(queue, entry);
1959 ctrl = (u32)tx_skb->size;
1961 ctrl |= MACB_BIT(TX_LAST);
1964 if (unlikely(entry == (bp->tx_ring_size - 1)))
1965 ctrl |= MACB_BIT(TX_WRAP);
1967 /* First descriptor is header descriptor */
1968 if (i == queue->tx_head) {
1969 ctrl |= MACB_BF(TX_LSO, lso_ctrl);
1970 ctrl |= MACB_BF(TX_TCP_SEQ_SRC, seq_ctrl);
1971 if ((bp->dev->features & NETIF_F_HW_CSUM) &&
1972 skb->ip_summed != CHECKSUM_PARTIAL && !lso_ctrl)
1973 ctrl |= MACB_BIT(TX_NOCRC);
1975 /* Only set MSS/MFS on payload descriptors
1976 * (second or later descriptor)
1978 ctrl |= MACB_BF(MSS_MFS, mss_mfs);
1980 /* Set TX buffer descriptor */
1981 macb_set_addr(bp, desc, tx_skb->mapping);
1982 /* desc->addr must be visible to hardware before clearing
1983 * 'TX_USED' bit in desc->ctrl.
1987 } while (i != queue->tx_head);
1989 queue->tx_head = tx_head;
1994 netdev_err(bp->dev, "TX DMA map failed\n");
1996 for (i = queue->tx_head; i != tx_head; i++) {
1997 tx_skb = macb_tx_skb(queue, i);
1999 macb_tx_unmap(bp, tx_skb);
2005 static netdev_features_t macb_features_check(struct sk_buff *skb,
2006 struct net_device *dev,
2007 netdev_features_t features)
2009 unsigned int nr_frags, f;
2010 unsigned int hdrlen;
2012 /* Validate LSO compatibility */
2014 /* there is only one buffer or protocol is not UDP */
2015 if (!skb_is_nonlinear(skb) || (ip_hdr(skb)->protocol != IPPROTO_UDP))
2018 /* length of header */
2019 hdrlen = skb_transport_offset(skb);
2022 * When software supplies two or more payload buffers all payload buffers
2023 * apart from the last must be a multiple of 8 bytes in size.
2025 if (!IS_ALIGNED(skb_headlen(skb) - hdrlen, MACB_TX_LEN_ALIGN))
2026 return features & ~MACB_NETIF_LSO;
2028 nr_frags = skb_shinfo(skb)->nr_frags;
2029 /* No need to check last fragment */
2031 for (f = 0; f < nr_frags; f++) {
2032 const skb_frag_t *frag = &skb_shinfo(skb)->frags[f];
2034 if (!IS_ALIGNED(skb_frag_size(frag), MACB_TX_LEN_ALIGN))
2035 return features & ~MACB_NETIF_LSO;
2040 static inline int macb_clear_csum(struct sk_buff *skb)
2042 /* no change for packets without checksum offloading */
2043 if (skb->ip_summed != CHECKSUM_PARTIAL)
2046 /* make sure we can modify the header */
2047 if (unlikely(skb_cow_head(skb, 0)))
2050 /* initialize checksum field
2051 * This is required - at least for Zynq, which otherwise calculates
2052 * wrong UDP header checksums for UDP packets with UDP data len <=2
2054 *(__sum16 *)(skb_checksum_start(skb) + skb->csum_offset) = 0;
2058 static int macb_pad_and_fcs(struct sk_buff **skb, struct net_device *ndev)
2060 bool cloned = skb_cloned(*skb) || skb_header_cloned(*skb) ||
2061 skb_is_nonlinear(*skb);
2062 int padlen = ETH_ZLEN - (*skb)->len;
2063 int headroom = skb_headroom(*skb);
2064 int tailroom = skb_tailroom(*skb);
2065 struct sk_buff *nskb;
2068 if (!(ndev->features & NETIF_F_HW_CSUM) ||
2069 !((*skb)->ip_summed != CHECKSUM_PARTIAL) ||
2070 skb_shinfo(*skb)->gso_size) /* Not available for GSO */
2074 /* FCS could be appeded to tailroom. */
2075 if (tailroom >= ETH_FCS_LEN)
2077 /* FCS could be appeded by moving data to headroom. */
2078 else if (!cloned && headroom + tailroom >= ETH_FCS_LEN)
2080 /* No room for FCS, need to reallocate skb. */
2082 padlen = ETH_FCS_LEN;
2084 /* Add room for FCS. */
2085 padlen += ETH_FCS_LEN;
2088 if (!cloned && headroom + tailroom >= padlen) {
2089 (*skb)->data = memmove((*skb)->head, (*skb)->data, (*skb)->len);
2090 skb_set_tail_pointer(*skb, (*skb)->len);
2092 nskb = skb_copy_expand(*skb, 0, padlen, GFP_ATOMIC);
2096 dev_consume_skb_any(*skb);
2100 if (padlen > ETH_FCS_LEN)
2101 skb_put_zero(*skb, padlen - ETH_FCS_LEN);
2104 /* set FCS to packet */
2105 fcs = crc32_le(~0, (*skb)->data, (*skb)->len);
2108 skb_put_u8(*skb, fcs & 0xff);
2109 skb_put_u8(*skb, (fcs >> 8) & 0xff);
2110 skb_put_u8(*skb, (fcs >> 16) & 0xff);
2111 skb_put_u8(*skb, (fcs >> 24) & 0xff);
2116 static netdev_tx_t macb_start_xmit(struct sk_buff *skb, struct net_device *dev)
2118 u16 queue_index = skb_get_queue_mapping(skb);
2119 struct macb *bp = netdev_priv(dev);
2120 struct macb_queue *queue = &bp->queues[queue_index];
2121 unsigned long flags;
2122 unsigned int desc_cnt, nr_frags, frag_size, f;
2123 unsigned int hdrlen;
2125 netdev_tx_t ret = NETDEV_TX_OK;
2127 if (macb_clear_csum(skb)) {
2128 dev_kfree_skb_any(skb);
2132 if (macb_pad_and_fcs(&skb, dev)) {
2133 dev_kfree_skb_any(skb);
2137 is_lso = (skb_shinfo(skb)->gso_size != 0);
2140 /* length of headers */
2141 if (ip_hdr(skb)->protocol == IPPROTO_UDP)
2142 /* only queue eth + ip headers separately for UDP */
2143 hdrlen = skb_transport_offset(skb);
2145 hdrlen = skb_transport_offset(skb) + tcp_hdrlen(skb);
2146 if (skb_headlen(skb) < hdrlen) {
2147 netdev_err(bp->dev, "Error - LSO headers fragmented!!!\n");
2148 /* if this is required, would need to copy to single buffer */
2149 return NETDEV_TX_BUSY;
2152 hdrlen = min(skb_headlen(skb), bp->max_tx_length);
2154 #if defined(DEBUG) && defined(VERBOSE_DEBUG)
2155 netdev_vdbg(bp->dev,
2156 "start_xmit: queue %hu len %u head %p data %p tail %p end %p\n",
2157 queue_index, skb->len, skb->head, skb->data,
2158 skb_tail_pointer(skb), skb_end_pointer(skb));
2159 print_hex_dump(KERN_DEBUG, "data: ", DUMP_PREFIX_OFFSET, 16, 1,
2160 skb->data, 16, true);
2163 /* Count how many TX buffer descriptors are needed to send this
2164 * socket buffer: skb fragments of jumbo frames may need to be
2165 * split into many buffer descriptors.
2167 if (is_lso && (skb_headlen(skb) > hdrlen))
2168 /* extra header descriptor if also payload in first buffer */
2169 desc_cnt = DIV_ROUND_UP((skb_headlen(skb) - hdrlen), bp->max_tx_length) + 1;
2171 desc_cnt = DIV_ROUND_UP(skb_headlen(skb), bp->max_tx_length);
2172 nr_frags = skb_shinfo(skb)->nr_frags;
2173 for (f = 0; f < nr_frags; f++) {
2174 frag_size = skb_frag_size(&skb_shinfo(skb)->frags[f]);
2175 desc_cnt += DIV_ROUND_UP(frag_size, bp->max_tx_length);
2178 spin_lock_irqsave(&bp->lock, flags);
2180 /* This is a hard error, log it. */
2181 if (CIRC_SPACE(queue->tx_head, queue->tx_tail,
2182 bp->tx_ring_size) < desc_cnt) {
2183 netif_stop_subqueue(dev, queue_index);
2184 spin_unlock_irqrestore(&bp->lock, flags);
2185 netdev_dbg(bp->dev, "tx_head = %u, tx_tail = %u\n",
2186 queue->tx_head, queue->tx_tail);
2187 return NETDEV_TX_BUSY;
2190 /* Map socket buffer for DMA transfer */
2191 if (!macb_tx_map(bp, queue, skb, hdrlen)) {
2192 dev_kfree_skb_any(skb);
2196 /* Make newly initialized descriptor visible to hardware */
2198 skb_tx_timestamp(skb);
2200 macb_writel(bp, NCR, macb_readl(bp, NCR) | MACB_BIT(TSTART));
2202 if (CIRC_SPACE(queue->tx_head, queue->tx_tail, bp->tx_ring_size) < 1)
2203 netif_stop_subqueue(dev, queue_index);
2206 spin_unlock_irqrestore(&bp->lock, flags);
2211 static void macb_init_rx_buffer_size(struct macb *bp, size_t size)
2213 if (!macb_is_gem(bp)) {
2214 bp->rx_buffer_size = MACB_RX_BUFFER_SIZE;
2216 bp->rx_buffer_size = size;
2218 if (bp->rx_buffer_size % RX_BUFFER_MULTIPLE) {
2220 "RX buffer must be multiple of %d bytes, expanding\n",
2221 RX_BUFFER_MULTIPLE);
2222 bp->rx_buffer_size =
2223 roundup(bp->rx_buffer_size, RX_BUFFER_MULTIPLE);
2227 netdev_dbg(bp->dev, "mtu [%u] rx_buffer_size [%zu]\n",
2228 bp->dev->mtu, bp->rx_buffer_size);
2231 static void gem_free_rx_buffers(struct macb *bp)
2233 struct sk_buff *skb;
2234 struct macb_dma_desc *desc;
2235 struct macb_queue *queue;
2240 for (q = 0, queue = bp->queues; q < bp->num_queues; ++q, ++queue) {
2241 if (!queue->rx_skbuff)
2244 for (i = 0; i < bp->rx_ring_size; i++) {
2245 skb = queue->rx_skbuff[i];
2250 desc = macb_rx_desc(queue, i);
2251 addr = macb_get_addr(bp, desc);
2253 dma_unmap_single(&bp->pdev->dev, addr, bp->rx_buffer_size,
2255 dev_kfree_skb_any(skb);
2259 kfree(queue->rx_skbuff);
2260 queue->rx_skbuff = NULL;
2264 static void macb_free_rx_buffers(struct macb *bp)
2266 struct macb_queue *queue = &bp->queues[0];
2268 if (queue->rx_buffers) {
2269 dma_free_coherent(&bp->pdev->dev,
2270 bp->rx_ring_size * bp->rx_buffer_size,
2271 queue->rx_buffers, queue->rx_buffers_dma);
2272 queue->rx_buffers = NULL;
2276 static void macb_free_consistent(struct macb *bp)
2278 struct macb_queue *queue;
2282 bp->macbgem_ops.mog_free_rx_buffers(bp);
2284 for (q = 0, queue = bp->queues; q < bp->num_queues; ++q, ++queue) {
2285 kfree(queue->tx_skb);
2286 queue->tx_skb = NULL;
2287 if (queue->tx_ring) {
2288 size = TX_RING_BYTES(bp) + bp->tx_bd_rd_prefetch;
2289 dma_free_coherent(&bp->pdev->dev, size,
2290 queue->tx_ring, queue->tx_ring_dma);
2291 queue->tx_ring = NULL;
2293 if (queue->rx_ring) {
2294 size = RX_RING_BYTES(bp) + bp->rx_bd_rd_prefetch;
2295 dma_free_coherent(&bp->pdev->dev, size,
2296 queue->rx_ring, queue->rx_ring_dma);
2297 queue->rx_ring = NULL;
2302 static int gem_alloc_rx_buffers(struct macb *bp)
2304 struct macb_queue *queue;
2308 for (q = 0, queue = bp->queues; q < bp->num_queues; ++q, ++queue) {
2309 size = bp->rx_ring_size * sizeof(struct sk_buff *);
2310 queue->rx_skbuff = kzalloc(size, GFP_KERNEL);
2311 if (!queue->rx_skbuff)
2315 "Allocated %d RX struct sk_buff entries at %p\n",
2316 bp->rx_ring_size, queue->rx_skbuff);
2321 static int macb_alloc_rx_buffers(struct macb *bp)
2323 struct macb_queue *queue = &bp->queues[0];
2326 size = bp->rx_ring_size * bp->rx_buffer_size;
2327 queue->rx_buffers = dma_alloc_coherent(&bp->pdev->dev, size,
2328 &queue->rx_buffers_dma, GFP_KERNEL);
2329 if (!queue->rx_buffers)
2333 "Allocated RX buffers of %d bytes at %08lx (mapped %p)\n",
2334 size, (unsigned long)queue->rx_buffers_dma, queue->rx_buffers);
2338 static int macb_alloc_consistent(struct macb *bp)
2340 struct macb_queue *queue;
2344 for (q = 0, queue = bp->queues; q < bp->num_queues; ++q, ++queue) {
2345 size = TX_RING_BYTES(bp) + bp->tx_bd_rd_prefetch;
2346 queue->tx_ring = dma_alloc_coherent(&bp->pdev->dev, size,
2347 &queue->tx_ring_dma,
2349 if (!queue->tx_ring)
2352 "Allocated TX ring for queue %u of %d bytes at %08lx (mapped %p)\n",
2353 q, size, (unsigned long)queue->tx_ring_dma,
2356 size = bp->tx_ring_size * sizeof(struct macb_tx_skb);
2357 queue->tx_skb = kmalloc(size, GFP_KERNEL);
2361 size = RX_RING_BYTES(bp) + bp->rx_bd_rd_prefetch;
2362 queue->rx_ring = dma_alloc_coherent(&bp->pdev->dev, size,
2363 &queue->rx_ring_dma, GFP_KERNEL);
2364 if (!queue->rx_ring)
2367 "Allocated RX ring of %d bytes at %08lx (mapped %p)\n",
2368 size, (unsigned long)queue->rx_ring_dma, queue->rx_ring);
2370 if (bp->macbgem_ops.mog_alloc_rx_buffers(bp))
2376 macb_free_consistent(bp);
2380 static void gem_init_rings(struct macb *bp)
2382 struct macb_queue *queue;
2383 struct macb_dma_desc *desc = NULL;
2387 for (q = 0, queue = bp->queues; q < bp->num_queues; ++q, ++queue) {
2388 for (i = 0; i < bp->tx_ring_size; i++) {
2389 desc = macb_tx_desc(queue, i);
2390 macb_set_addr(bp, desc, 0);
2391 desc->ctrl = MACB_BIT(TX_USED);
2393 desc->ctrl |= MACB_BIT(TX_WRAP);
2398 queue->rx_prepared_head = 0;
2400 gem_rx_refill(queue);
2405 static void macb_init_rings(struct macb *bp)
2408 struct macb_dma_desc *desc = NULL;
2410 macb_init_rx_ring(&bp->queues[0]);
2412 for (i = 0; i < bp->tx_ring_size; i++) {
2413 desc = macb_tx_desc(&bp->queues[0], i);
2414 macb_set_addr(bp, desc, 0);
2415 desc->ctrl = MACB_BIT(TX_USED);
2417 bp->queues[0].tx_head = 0;
2418 bp->queues[0].tx_tail = 0;
2419 desc->ctrl |= MACB_BIT(TX_WRAP);
2422 static void macb_reset_hw(struct macb *bp)
2424 struct macb_queue *queue;
2426 u32 ctrl = macb_readl(bp, NCR);
2428 /* Disable RX and TX (XXX: Should we halt the transmission
2431 ctrl &= ~(MACB_BIT(RE) | MACB_BIT(TE));
2433 /* Clear the stats registers (XXX: Update stats first?) */
2434 ctrl |= MACB_BIT(CLRSTAT);
2436 macb_writel(bp, NCR, ctrl);
2438 /* Clear all status flags */
2439 macb_writel(bp, TSR, -1);
2440 macb_writel(bp, RSR, -1);
2442 /* Disable all interrupts */
2443 for (q = 0, queue = bp->queues; q < bp->num_queues; ++q, ++queue) {
2444 queue_writel(queue, IDR, -1);
2445 queue_readl(queue, ISR);
2446 if (bp->caps & MACB_CAPS_ISR_CLEAR_ON_WRITE)
2447 queue_writel(queue, ISR, -1);
2451 static u32 gem_mdc_clk_div(struct macb *bp)
2454 unsigned long pclk_hz = clk_get_rate(bp->pclk);
2456 if (pclk_hz <= 20000000)
2457 config = GEM_BF(CLK, GEM_CLK_DIV8);
2458 else if (pclk_hz <= 40000000)
2459 config = GEM_BF(CLK, GEM_CLK_DIV16);
2460 else if (pclk_hz <= 80000000)
2461 config = GEM_BF(CLK, GEM_CLK_DIV32);
2462 else if (pclk_hz <= 120000000)
2463 config = GEM_BF(CLK, GEM_CLK_DIV48);
2464 else if (pclk_hz <= 160000000)
2465 config = GEM_BF(CLK, GEM_CLK_DIV64);
2467 config = GEM_BF(CLK, GEM_CLK_DIV96);
2472 static u32 macb_mdc_clk_div(struct macb *bp)
2475 unsigned long pclk_hz;
2477 if (macb_is_gem(bp))
2478 return gem_mdc_clk_div(bp);
2480 pclk_hz = clk_get_rate(bp->pclk);
2481 if (pclk_hz <= 20000000)
2482 config = MACB_BF(CLK, MACB_CLK_DIV8);
2483 else if (pclk_hz <= 40000000)
2484 config = MACB_BF(CLK, MACB_CLK_DIV16);
2485 else if (pclk_hz <= 80000000)
2486 config = MACB_BF(CLK, MACB_CLK_DIV32);
2488 config = MACB_BF(CLK, MACB_CLK_DIV64);
2493 /* Get the DMA bus width field of the network configuration register that we
2494 * should program. We find the width from decoding the design configuration
2495 * register to find the maximum supported data bus width.
2497 static u32 macb_dbw(struct macb *bp)
2499 if (!macb_is_gem(bp))
2502 switch (GEM_BFEXT(DBWDEF, gem_readl(bp, DCFG1))) {
2504 return GEM_BF(DBW, GEM_DBW128);
2506 return GEM_BF(DBW, GEM_DBW64);
2509 return GEM_BF(DBW, GEM_DBW32);
2513 /* Configure the receive DMA engine
2514 * - use the correct receive buffer size
2515 * - set best burst length for DMA operations
2516 * (if not supported by FIFO, it will fallback to default)
2517 * - set both rx/tx packet buffers to full memory size
2518 * These are configurable parameters for GEM.
2520 static void macb_configure_dma(struct macb *bp)
2522 struct macb_queue *queue;
2527 buffer_size = bp->rx_buffer_size / RX_BUFFER_MULTIPLE;
2528 if (macb_is_gem(bp)) {
2529 dmacfg = gem_readl(bp, DMACFG) & ~GEM_BF(RXBS, -1L);
2530 for (q = 0, queue = bp->queues; q < bp->num_queues; ++q, ++queue) {
2532 queue_writel(queue, RBQS, buffer_size);
2534 dmacfg |= GEM_BF(RXBS, buffer_size);
2536 if (bp->dma_burst_length)
2537 dmacfg = GEM_BFINS(FBLDO, bp->dma_burst_length, dmacfg);
2538 dmacfg |= GEM_BIT(TXPBMS) | GEM_BF(RXBMS, -1L);
2539 dmacfg &= ~GEM_BIT(ENDIA_PKT);
2542 dmacfg &= ~GEM_BIT(ENDIA_DESC);
2544 dmacfg |= GEM_BIT(ENDIA_DESC); /* CPU in big endian */
2546 if (bp->dev->features & NETIF_F_HW_CSUM)
2547 dmacfg |= GEM_BIT(TXCOEN);
2549 dmacfg &= ~GEM_BIT(TXCOEN);
2551 dmacfg &= ~GEM_BIT(ADDR64);
2552 #ifdef CONFIG_ARCH_DMA_ADDR_T_64BIT
2553 if (bp->hw_dma_cap & HW_DMA_CAP_64B)
2554 dmacfg |= GEM_BIT(ADDR64);
2556 #ifdef CONFIG_MACB_USE_HWSTAMP
2557 if (bp->hw_dma_cap & HW_DMA_CAP_PTP)
2558 dmacfg |= GEM_BIT(RXEXT) | GEM_BIT(TXEXT);
2560 netdev_dbg(bp->dev, "Cadence configure DMA with 0x%08x\n",
2562 gem_writel(bp, DMACFG, dmacfg);
2566 static void macb_init_hw(struct macb *bp)
2571 macb_set_hwaddr(bp);
2573 config = macb_mdc_clk_div(bp);
2574 config |= MACB_BF(RBOF, NET_IP_ALIGN); /* Make eth data aligned */
2575 config |= MACB_BIT(DRFCS); /* Discard Rx FCS */
2576 if (bp->caps & MACB_CAPS_JUMBO)
2577 config |= MACB_BIT(JFRAME); /* Enable jumbo frames */
2579 config |= MACB_BIT(BIG); /* Receive oversized frames */
2580 if (bp->dev->flags & IFF_PROMISC)
2581 config |= MACB_BIT(CAF); /* Copy All Frames */
2582 else if (macb_is_gem(bp) && bp->dev->features & NETIF_F_RXCSUM)
2583 config |= GEM_BIT(RXCOEN);
2584 if (!(bp->dev->flags & IFF_BROADCAST))
2585 config |= MACB_BIT(NBC); /* No BroadCast */
2586 config |= macb_dbw(bp);
2587 macb_writel(bp, NCFGR, config);
2588 if ((bp->caps & MACB_CAPS_JUMBO) && bp->jumbo_max_len)
2589 gem_writel(bp, JML, bp->jumbo_max_len);
2590 bp->rx_frm_len_mask = MACB_RX_FRMLEN_MASK;
2591 if (bp->caps & MACB_CAPS_JUMBO)
2592 bp->rx_frm_len_mask = MACB_RX_JFRMLEN_MASK;
2594 macb_configure_dma(bp);
2597 /* The hash address register is 64 bits long and takes up two
2598 * locations in the memory map. The least significant bits are stored
2599 * in EMAC_HSL and the most significant bits in EMAC_HSH.
2601 * The unicast hash enable and the multicast hash enable bits in the
2602 * network configuration register enable the reception of hash matched
2603 * frames. The destination address is reduced to a 6 bit index into
2604 * the 64 bit hash register using the following hash function. The
2605 * hash function is an exclusive or of every sixth bit of the
2606 * destination address.
2608 * hi[5] = da[5] ^ da[11] ^ da[17] ^ da[23] ^ da[29] ^ da[35] ^ da[41] ^ da[47]
2609 * hi[4] = da[4] ^ da[10] ^ da[16] ^ da[22] ^ da[28] ^ da[34] ^ da[40] ^ da[46]
2610 * hi[3] = da[3] ^ da[09] ^ da[15] ^ da[21] ^ da[27] ^ da[33] ^ da[39] ^ da[45]
2611 * hi[2] = da[2] ^ da[08] ^ da[14] ^ da[20] ^ da[26] ^ da[32] ^ da[38] ^ da[44]
2612 * hi[1] = da[1] ^ da[07] ^ da[13] ^ da[19] ^ da[25] ^ da[31] ^ da[37] ^ da[43]
2613 * hi[0] = da[0] ^ da[06] ^ da[12] ^ da[18] ^ da[24] ^ da[30] ^ da[36] ^ da[42]
2615 * da[0] represents the least significant bit of the first byte
2616 * received, that is, the multicast/unicast indicator, and da[47]
2617 * represents the most significant bit of the last byte received. If
2618 * the hash index, hi[n], points to a bit that is set in the hash
2619 * register then the frame will be matched according to whether the
2620 * frame is multicast or unicast. A multicast match will be signalled
2621 * if the multicast hash enable bit is set, da[0] is 1 and the hash
2622 * index points to a bit set in the hash register. A unicast match
2623 * will be signalled if the unicast hash enable bit is set, da[0] is 0
2624 * and the hash index points to a bit set in the hash register. To
2625 * receive all multicast frames, the hash register should be set with
2626 * all ones and the multicast hash enable bit should be set in the
2627 * network configuration register.
2630 static inline int hash_bit_value(int bitnr, __u8 *addr)
2632 if (addr[bitnr / 8] & (1 << (bitnr % 8)))
2637 /* Return the hash index value for the specified address. */
2638 static int hash_get_index(__u8 *addr)
2643 for (j = 0; j < 6; j++) {
2644 for (i = 0, bitval = 0; i < 8; i++)
2645 bitval ^= hash_bit_value(i * 6 + j, addr);
2647 hash_index |= (bitval << j);
2653 /* Add multicast addresses to the internal multicast-hash table. */
2654 static void macb_sethashtable(struct net_device *dev)
2656 struct netdev_hw_addr *ha;
2657 unsigned long mc_filter[2];
2659 struct macb *bp = netdev_priv(dev);
2664 netdev_for_each_mc_addr(ha, dev) {
2665 bitnr = hash_get_index(ha->addr);
2666 mc_filter[bitnr >> 5] |= 1 << (bitnr & 31);
2669 macb_or_gem_writel(bp, HRB, mc_filter[0]);
2670 macb_or_gem_writel(bp, HRT, mc_filter[1]);
2673 /* Enable/Disable promiscuous and multicast modes. */
2674 static void macb_set_rx_mode(struct net_device *dev)
2677 struct macb *bp = netdev_priv(dev);
2679 cfg = macb_readl(bp, NCFGR);
2681 if (dev->flags & IFF_PROMISC) {
2682 /* Enable promiscuous mode */
2683 cfg |= MACB_BIT(CAF);
2685 /* Disable RX checksum offload */
2686 if (macb_is_gem(bp))
2687 cfg &= ~GEM_BIT(RXCOEN);
2689 /* Disable promiscuous mode */
2690 cfg &= ~MACB_BIT(CAF);
2692 /* Enable RX checksum offload only if requested */
2693 if (macb_is_gem(bp) && dev->features & NETIF_F_RXCSUM)
2694 cfg |= GEM_BIT(RXCOEN);
2697 if (dev->flags & IFF_ALLMULTI) {
2698 /* Enable all multicast mode */
2699 macb_or_gem_writel(bp, HRB, -1);
2700 macb_or_gem_writel(bp, HRT, -1);
2701 cfg |= MACB_BIT(NCFGR_MTI);
2702 } else if (!netdev_mc_empty(dev)) {
2703 /* Enable specific multicasts */
2704 macb_sethashtable(dev);
2705 cfg |= MACB_BIT(NCFGR_MTI);
2706 } else if (dev->flags & (~IFF_ALLMULTI)) {
2707 /* Disable all multicast mode */
2708 macb_or_gem_writel(bp, HRB, 0);
2709 macb_or_gem_writel(bp, HRT, 0);
2710 cfg &= ~MACB_BIT(NCFGR_MTI);
2713 macb_writel(bp, NCFGR, cfg);
2716 static int macb_open(struct net_device *dev)
2718 size_t bufsz = dev->mtu + ETH_HLEN + ETH_FCS_LEN + NET_IP_ALIGN;
2719 struct macb *bp = netdev_priv(dev);
2720 struct macb_queue *queue;
2724 netdev_dbg(bp->dev, "open\n");
2726 err = pm_runtime_get_sync(&bp->pdev->dev);
2730 /* RX buffers initialization */
2731 macb_init_rx_buffer_size(bp, bufsz);
2733 err = macb_alloc_consistent(bp);
2735 netdev_err(dev, "Unable to allocate DMA memory (error %d)\n",
2740 for (q = 0, queue = bp->queues; q < bp->num_queues; ++q, ++queue)
2741 napi_enable(&queue->napi);
2745 err = macb_phylink_connect(bp);
2749 netif_tx_start_all_queues(dev);
2752 bp->ptp_info->ptp_init(dev);
2758 for (q = 0, queue = bp->queues; q < bp->num_queues; ++q, ++queue)
2759 napi_disable(&queue->napi);
2760 macb_free_consistent(bp);
2762 pm_runtime_put_sync(&bp->pdev->dev);
2766 static int macb_close(struct net_device *dev)
2768 struct macb *bp = netdev_priv(dev);
2769 struct macb_queue *queue;
2770 unsigned long flags;
2773 netif_tx_stop_all_queues(dev);
2775 for (q = 0, queue = bp->queues; q < bp->num_queues; ++q, ++queue)
2776 napi_disable(&queue->napi);
2778 phylink_stop(bp->phylink);
2779 phylink_disconnect_phy(bp->phylink);
2781 spin_lock_irqsave(&bp->lock, flags);
2783 netif_carrier_off(dev);
2784 spin_unlock_irqrestore(&bp->lock, flags);
2786 macb_free_consistent(bp);
2789 bp->ptp_info->ptp_remove(dev);
2791 pm_runtime_put(&bp->pdev->dev);
2796 static int macb_change_mtu(struct net_device *dev, int new_mtu)
2798 if (netif_running(dev))
2806 static void gem_update_stats(struct macb *bp)
2808 struct macb_queue *queue;
2809 unsigned int i, q, idx;
2810 unsigned long *stat;
2812 u32 *p = &bp->hw_stats.gem.tx_octets_31_0;
2814 for (i = 0; i < GEM_STATS_LEN; ++i, ++p) {
2815 u32 offset = gem_statistics[i].offset;
2816 u64 val = bp->macb_reg_readl(bp, offset);
2818 bp->ethtool_stats[i] += val;
2821 if (offset == GEM_OCTTXL || offset == GEM_OCTRXL) {
2822 /* Add GEM_OCTTXH, GEM_OCTRXH */
2823 val = bp->macb_reg_readl(bp, offset + 4);
2824 bp->ethtool_stats[i] += ((u64)val) << 32;
2829 idx = GEM_STATS_LEN;
2830 for (q = 0, queue = bp->queues; q < bp->num_queues; ++q, ++queue)
2831 for (i = 0, stat = &queue->stats.first; i < QUEUE_STATS_LEN; ++i, ++stat)
2832 bp->ethtool_stats[idx++] = *stat;
2835 static struct net_device_stats *gem_get_stats(struct macb *bp)
2837 struct gem_stats *hwstat = &bp->hw_stats.gem;
2838 struct net_device_stats *nstat = &bp->dev->stats;
2840 gem_update_stats(bp);
2842 nstat->rx_errors = (hwstat->rx_frame_check_sequence_errors +
2843 hwstat->rx_alignment_errors +
2844 hwstat->rx_resource_errors +
2845 hwstat->rx_overruns +
2846 hwstat->rx_oversize_frames +
2847 hwstat->rx_jabbers +
2848 hwstat->rx_undersized_frames +
2849 hwstat->rx_length_field_frame_errors);
2850 nstat->tx_errors = (hwstat->tx_late_collisions +
2851 hwstat->tx_excessive_collisions +
2852 hwstat->tx_underrun +
2853 hwstat->tx_carrier_sense_errors);
2854 nstat->multicast = hwstat->rx_multicast_frames;
2855 nstat->collisions = (hwstat->tx_single_collision_frames +
2856 hwstat->tx_multiple_collision_frames +
2857 hwstat->tx_excessive_collisions);
2858 nstat->rx_length_errors = (hwstat->rx_oversize_frames +
2859 hwstat->rx_jabbers +
2860 hwstat->rx_undersized_frames +
2861 hwstat->rx_length_field_frame_errors);
2862 nstat->rx_over_errors = hwstat->rx_resource_errors;
2863 nstat->rx_crc_errors = hwstat->rx_frame_check_sequence_errors;
2864 nstat->rx_frame_errors = hwstat->rx_alignment_errors;
2865 nstat->rx_fifo_errors = hwstat->rx_overruns;
2866 nstat->tx_aborted_errors = hwstat->tx_excessive_collisions;
2867 nstat->tx_carrier_errors = hwstat->tx_carrier_sense_errors;
2868 nstat->tx_fifo_errors = hwstat->tx_underrun;
2873 static void gem_get_ethtool_stats(struct net_device *dev,
2874 struct ethtool_stats *stats, u64 *data)
2878 bp = netdev_priv(dev);
2879 gem_update_stats(bp);
2880 memcpy(data, &bp->ethtool_stats, sizeof(u64)
2881 * (GEM_STATS_LEN + QUEUE_STATS_LEN * MACB_MAX_QUEUES));
2884 static int gem_get_sset_count(struct net_device *dev, int sset)
2886 struct macb *bp = netdev_priv(dev);
2890 return GEM_STATS_LEN + bp->num_queues * QUEUE_STATS_LEN;
2896 static void gem_get_ethtool_strings(struct net_device *dev, u32 sset, u8 *p)
2898 char stat_string[ETH_GSTRING_LEN];
2899 struct macb *bp = netdev_priv(dev);
2900 struct macb_queue *queue;
2906 for (i = 0; i < GEM_STATS_LEN; i++, p += ETH_GSTRING_LEN)
2907 memcpy(p, gem_statistics[i].stat_string,
2910 for (q = 0, queue = bp->queues; q < bp->num_queues; ++q, ++queue) {
2911 for (i = 0; i < QUEUE_STATS_LEN; i++, p += ETH_GSTRING_LEN) {
2912 snprintf(stat_string, ETH_GSTRING_LEN, "q%d_%s",
2913 q, queue_statistics[i].stat_string);
2914 memcpy(p, stat_string, ETH_GSTRING_LEN);
2921 static struct net_device_stats *macb_get_stats(struct net_device *dev)
2923 struct macb *bp = netdev_priv(dev);
2924 struct net_device_stats *nstat = &bp->dev->stats;
2925 struct macb_stats *hwstat = &bp->hw_stats.macb;
2927 if (macb_is_gem(bp))
2928 return gem_get_stats(bp);
2930 /* read stats from hardware */
2931 macb_update_stats(bp);
2933 /* Convert HW stats into netdevice stats */
2934 nstat->rx_errors = (hwstat->rx_fcs_errors +
2935 hwstat->rx_align_errors +
2936 hwstat->rx_resource_errors +
2937 hwstat->rx_overruns +
2938 hwstat->rx_oversize_pkts +
2939 hwstat->rx_jabbers +
2940 hwstat->rx_undersize_pkts +
2941 hwstat->rx_length_mismatch);
2942 nstat->tx_errors = (hwstat->tx_late_cols +
2943 hwstat->tx_excessive_cols +
2944 hwstat->tx_underruns +
2945 hwstat->tx_carrier_errors +
2946 hwstat->sqe_test_errors);
2947 nstat->collisions = (hwstat->tx_single_cols +
2948 hwstat->tx_multiple_cols +
2949 hwstat->tx_excessive_cols);
2950 nstat->rx_length_errors = (hwstat->rx_oversize_pkts +
2951 hwstat->rx_jabbers +
2952 hwstat->rx_undersize_pkts +
2953 hwstat->rx_length_mismatch);
2954 nstat->rx_over_errors = hwstat->rx_resource_errors +
2955 hwstat->rx_overruns;
2956 nstat->rx_crc_errors = hwstat->rx_fcs_errors;
2957 nstat->rx_frame_errors = hwstat->rx_align_errors;
2958 nstat->rx_fifo_errors = hwstat->rx_overruns;
2959 /* XXX: What does "missed" mean? */
2960 nstat->tx_aborted_errors = hwstat->tx_excessive_cols;
2961 nstat->tx_carrier_errors = hwstat->tx_carrier_errors;
2962 nstat->tx_fifo_errors = hwstat->tx_underruns;
2963 /* Don't know about heartbeat or window errors... */
2968 static int macb_get_regs_len(struct net_device *netdev)
2970 return MACB_GREGS_NBR * sizeof(u32);
2973 static void macb_get_regs(struct net_device *dev, struct ethtool_regs *regs,
2976 struct macb *bp = netdev_priv(dev);
2977 unsigned int tail, head;
2980 regs->version = (macb_readl(bp, MID) & ((1 << MACB_REV_SIZE) - 1))
2981 | MACB_GREGS_VERSION;
2983 tail = macb_tx_ring_wrap(bp, bp->queues[0].tx_tail);
2984 head = macb_tx_ring_wrap(bp, bp->queues[0].tx_head);
2986 regs_buff[0] = macb_readl(bp, NCR);
2987 regs_buff[1] = macb_or_gem_readl(bp, NCFGR);
2988 regs_buff[2] = macb_readl(bp, NSR);
2989 regs_buff[3] = macb_readl(bp, TSR);
2990 regs_buff[4] = macb_readl(bp, RBQP);
2991 regs_buff[5] = macb_readl(bp, TBQP);
2992 regs_buff[6] = macb_readl(bp, RSR);
2993 regs_buff[7] = macb_readl(bp, IMR);
2995 regs_buff[8] = tail;
2996 regs_buff[9] = head;
2997 regs_buff[10] = macb_tx_dma(&bp->queues[0], tail);
2998 regs_buff[11] = macb_tx_dma(&bp->queues[0], head);
3000 if (!(bp->caps & MACB_CAPS_USRIO_DISABLED))
3001 regs_buff[12] = macb_or_gem_readl(bp, USRIO);
3002 if (macb_is_gem(bp))
3003 regs_buff[13] = gem_readl(bp, DMACFG);
3006 static void macb_get_wol(struct net_device *netdev, struct ethtool_wolinfo *wol)
3008 struct macb *bp = netdev_priv(netdev);
3010 if (bp->wol & MACB_WOL_HAS_MAGIC_PACKET) {
3011 phylink_ethtool_get_wol(bp->phylink, wol);
3012 wol->supported |= WAKE_MAGIC;
3014 if (bp->wol & MACB_WOL_ENABLED)
3015 wol->wolopts |= WAKE_MAGIC;
3019 static int macb_set_wol(struct net_device *netdev, struct ethtool_wolinfo *wol)
3021 struct macb *bp = netdev_priv(netdev);
3024 /* Pass the order to phylink layer */
3025 ret = phylink_ethtool_set_wol(bp->phylink, wol);
3026 /* Don't manage WoL on MAC if handled by the PHY
3027 * or if there's a failure in talking to the PHY
3029 if (!ret || ret != -EOPNOTSUPP)
3032 if (!(bp->wol & MACB_WOL_HAS_MAGIC_PACKET) ||
3033 (wol->wolopts & ~WAKE_MAGIC))
3036 if (wol->wolopts & WAKE_MAGIC)
3037 bp->wol |= MACB_WOL_ENABLED;
3039 bp->wol &= ~MACB_WOL_ENABLED;
3041 device_set_wakeup_enable(&bp->pdev->dev, bp->wol & MACB_WOL_ENABLED);
3046 static int macb_get_link_ksettings(struct net_device *netdev,
3047 struct ethtool_link_ksettings *kset)
3049 struct macb *bp = netdev_priv(netdev);
3051 return phylink_ethtool_ksettings_get(bp->phylink, kset);
3054 static int macb_set_link_ksettings(struct net_device *netdev,
3055 const struct ethtool_link_ksettings *kset)
3057 struct macb *bp = netdev_priv(netdev);
3059 return phylink_ethtool_ksettings_set(bp->phylink, kset);
3062 static void macb_get_ringparam(struct net_device *netdev,
3063 struct ethtool_ringparam *ring)
3065 struct macb *bp = netdev_priv(netdev);
3067 ring->rx_max_pending = MAX_RX_RING_SIZE;
3068 ring->tx_max_pending = MAX_TX_RING_SIZE;
3070 ring->rx_pending = bp->rx_ring_size;
3071 ring->tx_pending = bp->tx_ring_size;
3074 static int macb_set_ringparam(struct net_device *netdev,
3075 struct ethtool_ringparam *ring)
3077 struct macb *bp = netdev_priv(netdev);
3078 u32 new_rx_size, new_tx_size;
3079 unsigned int reset = 0;
3081 if ((ring->rx_mini_pending) || (ring->rx_jumbo_pending))
3084 new_rx_size = clamp_t(u32, ring->rx_pending,
3085 MIN_RX_RING_SIZE, MAX_RX_RING_SIZE);
3086 new_rx_size = roundup_pow_of_two(new_rx_size);
3088 new_tx_size = clamp_t(u32, ring->tx_pending,
3089 MIN_TX_RING_SIZE, MAX_TX_RING_SIZE);
3090 new_tx_size = roundup_pow_of_two(new_tx_size);
3092 if ((new_tx_size == bp->tx_ring_size) &&
3093 (new_rx_size == bp->rx_ring_size)) {
3098 if (netif_running(bp->dev)) {
3100 macb_close(bp->dev);
3103 bp->rx_ring_size = new_rx_size;
3104 bp->tx_ring_size = new_tx_size;
3112 #ifdef CONFIG_MACB_USE_HWSTAMP
3113 static unsigned int gem_get_tsu_rate(struct macb *bp)
3115 struct clk *tsu_clk;
3116 unsigned int tsu_rate;
3118 tsu_clk = devm_clk_get(&bp->pdev->dev, "tsu_clk");
3119 if (!IS_ERR(tsu_clk))
3120 tsu_rate = clk_get_rate(tsu_clk);
3121 /* try pclk instead */
3122 else if (!IS_ERR(bp->pclk)) {
3124 tsu_rate = clk_get_rate(tsu_clk);
3130 static s32 gem_get_ptp_max_adj(void)
3135 static int gem_get_ts_info(struct net_device *dev,
3136 struct ethtool_ts_info *info)
3138 struct macb *bp = netdev_priv(dev);
3140 if ((bp->hw_dma_cap & HW_DMA_CAP_PTP) == 0) {
3141 ethtool_op_get_ts_info(dev, info);
3145 info->so_timestamping =
3146 SOF_TIMESTAMPING_TX_SOFTWARE |
3147 SOF_TIMESTAMPING_RX_SOFTWARE |
3148 SOF_TIMESTAMPING_SOFTWARE |
3149 SOF_TIMESTAMPING_TX_HARDWARE |
3150 SOF_TIMESTAMPING_RX_HARDWARE |
3151 SOF_TIMESTAMPING_RAW_HARDWARE;
3153 (1 << HWTSTAMP_TX_ONESTEP_SYNC) |
3154 (1 << HWTSTAMP_TX_OFF) |
3155 (1 << HWTSTAMP_TX_ON);
3157 (1 << HWTSTAMP_FILTER_NONE) |
3158 (1 << HWTSTAMP_FILTER_ALL);
3160 info->phc_index = bp->ptp_clock ? ptp_clock_index(bp->ptp_clock) : -1;
3165 static struct macb_ptp_info gem_ptp_info = {
3166 .ptp_init = gem_ptp_init,
3167 .ptp_remove = gem_ptp_remove,
3168 .get_ptp_max_adj = gem_get_ptp_max_adj,
3169 .get_tsu_rate = gem_get_tsu_rate,
3170 .get_ts_info = gem_get_ts_info,
3171 .get_hwtst = gem_get_hwtst,
3172 .set_hwtst = gem_set_hwtst,
3176 static int macb_get_ts_info(struct net_device *netdev,
3177 struct ethtool_ts_info *info)
3179 struct macb *bp = netdev_priv(netdev);
3182 return bp->ptp_info->get_ts_info(netdev, info);
3184 return ethtool_op_get_ts_info(netdev, info);
3187 static void gem_enable_flow_filters(struct macb *bp, bool enable)
3189 struct net_device *netdev = bp->dev;
3190 struct ethtool_rx_fs_item *item;
3194 if (!(netdev->features & NETIF_F_NTUPLE))
3197 num_t2_scr = GEM_BFEXT(T2SCR, gem_readl(bp, DCFG8));
3199 list_for_each_entry(item, &bp->rx_fs_list.list, list) {
3200 struct ethtool_rx_flow_spec *fs = &item->fs;
3201 struct ethtool_tcpip4_spec *tp4sp_m;
3203 if (fs->location >= num_t2_scr)
3206 t2_scr = gem_readl_n(bp, SCRT2, fs->location);
3208 /* enable/disable screener regs for the flow entry */
3209 t2_scr = GEM_BFINS(ETHTEN, enable, t2_scr);
3211 /* only enable fields with no masking */
3212 tp4sp_m = &(fs->m_u.tcp_ip4_spec);
3214 if (enable && (tp4sp_m->ip4src == 0xFFFFFFFF))
3215 t2_scr = GEM_BFINS(CMPAEN, 1, t2_scr);
3217 t2_scr = GEM_BFINS(CMPAEN, 0, t2_scr);
3219 if (enable && (tp4sp_m->ip4dst == 0xFFFFFFFF))
3220 t2_scr = GEM_BFINS(CMPBEN, 1, t2_scr);
3222 t2_scr = GEM_BFINS(CMPBEN, 0, t2_scr);
3224 if (enable && ((tp4sp_m->psrc == 0xFFFF) || (tp4sp_m->pdst == 0xFFFF)))
3225 t2_scr = GEM_BFINS(CMPCEN, 1, t2_scr);
3227 t2_scr = GEM_BFINS(CMPCEN, 0, t2_scr);
3229 gem_writel_n(bp, SCRT2, fs->location, t2_scr);
3233 static void gem_prog_cmp_regs(struct macb *bp, struct ethtool_rx_flow_spec *fs)
3235 struct ethtool_tcpip4_spec *tp4sp_v, *tp4sp_m;
3236 uint16_t index = fs->location;
3242 tp4sp_v = &(fs->h_u.tcp_ip4_spec);
3243 tp4sp_m = &(fs->m_u.tcp_ip4_spec);
3245 /* ignore field if any masking set */
3246 if (tp4sp_m->ip4src == 0xFFFFFFFF) {
3247 /* 1st compare reg - IP source address */
3250 w0 = tp4sp_v->ip4src;
3251 w1 = GEM_BFINS(T2DISMSK, 1, w1); /* 32-bit compare */
3252 w1 = GEM_BFINS(T2CMPOFST, GEM_T2COMPOFST_ETYPE, w1);
3253 w1 = GEM_BFINS(T2OFST, ETYPE_SRCIP_OFFSET, w1);
3254 gem_writel_n(bp, T2CMPW0, T2CMP_OFST(GEM_IP4SRC_CMP(index)), w0);
3255 gem_writel_n(bp, T2CMPW1, T2CMP_OFST(GEM_IP4SRC_CMP(index)), w1);
3259 /* ignore field if any masking set */
3260 if (tp4sp_m->ip4dst == 0xFFFFFFFF) {
3261 /* 2nd compare reg - IP destination address */
3264 w0 = tp4sp_v->ip4dst;
3265 w1 = GEM_BFINS(T2DISMSK, 1, w1); /* 32-bit compare */
3266 w1 = GEM_BFINS(T2CMPOFST, GEM_T2COMPOFST_ETYPE, w1);
3267 w1 = GEM_BFINS(T2OFST, ETYPE_DSTIP_OFFSET, w1);
3268 gem_writel_n(bp, T2CMPW0, T2CMP_OFST(GEM_IP4DST_CMP(index)), w0);
3269 gem_writel_n(bp, T2CMPW1, T2CMP_OFST(GEM_IP4DST_CMP(index)), w1);
3273 /* ignore both port fields if masking set in both */
3274 if ((tp4sp_m->psrc == 0xFFFF) || (tp4sp_m->pdst == 0xFFFF)) {
3275 /* 3rd compare reg - source port, destination port */
3278 w1 = GEM_BFINS(T2CMPOFST, GEM_T2COMPOFST_IPHDR, w1);
3279 if (tp4sp_m->psrc == tp4sp_m->pdst) {
3280 w0 = GEM_BFINS(T2MASK, tp4sp_v->psrc, w0);
3281 w0 = GEM_BFINS(T2CMP, tp4sp_v->pdst, w0);
3282 w1 = GEM_BFINS(T2DISMSK, 1, w1); /* 32-bit compare */
3283 w1 = GEM_BFINS(T2OFST, IPHDR_SRCPORT_OFFSET, w1);
3285 /* only one port definition */
3286 w1 = GEM_BFINS(T2DISMSK, 0, w1); /* 16-bit compare */
3287 w0 = GEM_BFINS(T2MASK, 0xFFFF, w0);
3288 if (tp4sp_m->psrc == 0xFFFF) { /* src port */
3289 w0 = GEM_BFINS(T2CMP, tp4sp_v->psrc, w0);
3290 w1 = GEM_BFINS(T2OFST, IPHDR_SRCPORT_OFFSET, w1);
3291 } else { /* dst port */
3292 w0 = GEM_BFINS(T2CMP, tp4sp_v->pdst, w0);
3293 w1 = GEM_BFINS(T2OFST, IPHDR_DSTPORT_OFFSET, w1);
3296 gem_writel_n(bp, T2CMPW0, T2CMP_OFST(GEM_PORT_CMP(index)), w0);
3297 gem_writel_n(bp, T2CMPW1, T2CMP_OFST(GEM_PORT_CMP(index)), w1);
3302 t2_scr = GEM_BFINS(QUEUE, (fs->ring_cookie) & 0xFF, t2_scr);
3303 t2_scr = GEM_BFINS(ETHT2IDX, SCRT2_ETHT, t2_scr);
3305 t2_scr = GEM_BFINS(CMPA, GEM_IP4SRC_CMP(index), t2_scr);
3307 t2_scr = GEM_BFINS(CMPB, GEM_IP4DST_CMP(index), t2_scr);
3309 t2_scr = GEM_BFINS(CMPC, GEM_PORT_CMP(index), t2_scr);
3310 gem_writel_n(bp, SCRT2, index, t2_scr);
3313 static int gem_add_flow_filter(struct net_device *netdev,
3314 struct ethtool_rxnfc *cmd)
3316 struct macb *bp = netdev_priv(netdev);
3317 struct ethtool_rx_flow_spec *fs = &cmd->fs;
3318 struct ethtool_rx_fs_item *item, *newfs;
3319 unsigned long flags;
3323 newfs = kmalloc(sizeof(*newfs), GFP_KERNEL);
3326 memcpy(&newfs->fs, fs, sizeof(newfs->fs));
3329 "Adding flow filter entry,type=%u,queue=%u,loc=%u,src=%08X,dst=%08X,ps=%u,pd=%u\n",
3330 fs->flow_type, (int)fs->ring_cookie, fs->location,
3331 htonl(fs->h_u.tcp_ip4_spec.ip4src),
3332 htonl(fs->h_u.tcp_ip4_spec.ip4dst),
3333 htons(fs->h_u.tcp_ip4_spec.psrc), htons(fs->h_u.tcp_ip4_spec.pdst));
3335 spin_lock_irqsave(&bp->rx_fs_lock, flags);
3337 /* find correct place to add in list */
3338 list_for_each_entry(item, &bp->rx_fs_list.list, list) {
3339 if (item->fs.location > newfs->fs.location) {
3340 list_add_tail(&newfs->list, &item->list);
3343 } else if (item->fs.location == fs->location) {
3344 netdev_err(netdev, "Rule not added: location %d not free!\n",
3351 list_add_tail(&newfs->list, &bp->rx_fs_list.list);
3353 gem_prog_cmp_regs(bp, fs);
3354 bp->rx_fs_list.count++;
3355 /* enable filtering if NTUPLE on */
3356 gem_enable_flow_filters(bp, 1);
3358 spin_unlock_irqrestore(&bp->rx_fs_lock, flags);
3362 spin_unlock_irqrestore(&bp->rx_fs_lock, flags);
3367 static int gem_del_flow_filter(struct net_device *netdev,
3368 struct ethtool_rxnfc *cmd)
3370 struct macb *bp = netdev_priv(netdev);
3371 struct ethtool_rx_fs_item *item;
3372 struct ethtool_rx_flow_spec *fs;
3373 unsigned long flags;
3375 spin_lock_irqsave(&bp->rx_fs_lock, flags);
3377 list_for_each_entry(item, &bp->rx_fs_list.list, list) {
3378 if (item->fs.location == cmd->fs.location) {
3379 /* disable screener regs for the flow entry */
3382 "Deleting flow filter entry,type=%u,queue=%u,loc=%u,src=%08X,dst=%08X,ps=%u,pd=%u\n",
3383 fs->flow_type, (int)fs->ring_cookie, fs->location,
3384 htonl(fs->h_u.tcp_ip4_spec.ip4src),
3385 htonl(fs->h_u.tcp_ip4_spec.ip4dst),
3386 htons(fs->h_u.tcp_ip4_spec.psrc),
3387 htons(fs->h_u.tcp_ip4_spec.pdst));
3389 gem_writel_n(bp, SCRT2, fs->location, 0);
3391 list_del(&item->list);
3392 bp->rx_fs_list.count--;
3393 spin_unlock_irqrestore(&bp->rx_fs_lock, flags);
3399 spin_unlock_irqrestore(&bp->rx_fs_lock, flags);
3403 static int gem_get_flow_entry(struct net_device *netdev,
3404 struct ethtool_rxnfc *cmd)
3406 struct macb *bp = netdev_priv(netdev);
3407 struct ethtool_rx_fs_item *item;
3409 list_for_each_entry(item, &bp->rx_fs_list.list, list) {
3410 if (item->fs.location == cmd->fs.location) {
3411 memcpy(&cmd->fs, &item->fs, sizeof(cmd->fs));
3418 static int gem_get_all_flow_entries(struct net_device *netdev,
3419 struct ethtool_rxnfc *cmd, u32 *rule_locs)
3421 struct macb *bp = netdev_priv(netdev);
3422 struct ethtool_rx_fs_item *item;
3425 list_for_each_entry(item, &bp->rx_fs_list.list, list) {
3426 if (cnt == cmd->rule_cnt)
3428 rule_locs[cnt] = item->fs.location;
3431 cmd->data = bp->max_tuples;
3432 cmd->rule_cnt = cnt;
3437 static int gem_get_rxnfc(struct net_device *netdev, struct ethtool_rxnfc *cmd,
3440 struct macb *bp = netdev_priv(netdev);
3444 case ETHTOOL_GRXRINGS:
3445 cmd->data = bp->num_queues;
3447 case ETHTOOL_GRXCLSRLCNT:
3448 cmd->rule_cnt = bp->rx_fs_list.count;
3450 case ETHTOOL_GRXCLSRULE:
3451 ret = gem_get_flow_entry(netdev, cmd);
3453 case ETHTOOL_GRXCLSRLALL:
3454 ret = gem_get_all_flow_entries(netdev, cmd, rule_locs);
3458 "Command parameter %d is not supported\n", cmd->cmd);
3465 static int gem_set_rxnfc(struct net_device *netdev, struct ethtool_rxnfc *cmd)
3467 struct macb *bp = netdev_priv(netdev);
3471 case ETHTOOL_SRXCLSRLINS:
3472 if ((cmd->fs.location >= bp->max_tuples)
3473 || (cmd->fs.ring_cookie >= bp->num_queues)) {
3477 ret = gem_add_flow_filter(netdev, cmd);
3479 case ETHTOOL_SRXCLSRLDEL:
3480 ret = gem_del_flow_filter(netdev, cmd);
3484 "Command parameter %d is not supported\n", cmd->cmd);
3491 static const struct ethtool_ops macb_ethtool_ops = {
3492 .get_regs_len = macb_get_regs_len,
3493 .get_regs = macb_get_regs,
3494 .get_link = ethtool_op_get_link,
3495 .get_ts_info = ethtool_op_get_ts_info,
3496 .get_wol = macb_get_wol,
3497 .set_wol = macb_set_wol,
3498 .get_link_ksettings = macb_get_link_ksettings,
3499 .set_link_ksettings = macb_set_link_ksettings,
3500 .get_ringparam = macb_get_ringparam,
3501 .set_ringparam = macb_set_ringparam,
3504 static const struct ethtool_ops gem_ethtool_ops = {
3505 .get_regs_len = macb_get_regs_len,
3506 .get_regs = macb_get_regs,
3507 .get_wol = macb_get_wol,
3508 .set_wol = macb_set_wol,
3509 .get_link = ethtool_op_get_link,
3510 .get_ts_info = macb_get_ts_info,
3511 .get_ethtool_stats = gem_get_ethtool_stats,
3512 .get_strings = gem_get_ethtool_strings,
3513 .get_sset_count = gem_get_sset_count,
3514 .get_link_ksettings = macb_get_link_ksettings,
3515 .set_link_ksettings = macb_set_link_ksettings,
3516 .get_ringparam = macb_get_ringparam,
3517 .set_ringparam = macb_set_ringparam,
3518 .get_rxnfc = gem_get_rxnfc,
3519 .set_rxnfc = gem_set_rxnfc,
3522 static int macb_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
3524 struct macb *bp = netdev_priv(dev);
3526 if (!netif_running(dev))
3532 return bp->ptp_info->set_hwtst(dev, rq, cmd);
3534 return bp->ptp_info->get_hwtst(dev, rq);
3538 return phylink_mii_ioctl(bp->phylink, rq, cmd);
3541 static inline void macb_set_txcsum_feature(struct macb *bp,
3542 netdev_features_t features)
3546 if (!macb_is_gem(bp))
3549 val = gem_readl(bp, DMACFG);
3550 if (features & NETIF_F_HW_CSUM)
3551 val |= GEM_BIT(TXCOEN);
3553 val &= ~GEM_BIT(TXCOEN);
3555 gem_writel(bp, DMACFG, val);
3558 static inline void macb_set_rxcsum_feature(struct macb *bp,
3559 netdev_features_t features)
3561 struct net_device *netdev = bp->dev;
3564 if (!macb_is_gem(bp))
3567 val = gem_readl(bp, NCFGR);
3568 if ((features & NETIF_F_RXCSUM) && !(netdev->flags & IFF_PROMISC))
3569 val |= GEM_BIT(RXCOEN);
3571 val &= ~GEM_BIT(RXCOEN);
3573 gem_writel(bp, NCFGR, val);
3576 static inline void macb_set_rxflow_feature(struct macb *bp,
3577 netdev_features_t features)
3579 if (!macb_is_gem(bp))
3582 gem_enable_flow_filters(bp, !!(features & NETIF_F_NTUPLE));
3585 static int macb_set_features(struct net_device *netdev,
3586 netdev_features_t features)
3588 struct macb *bp = netdev_priv(netdev);
3589 netdev_features_t changed = features ^ netdev->features;
3591 /* TX checksum offload */
3592 if (changed & NETIF_F_HW_CSUM)
3593 macb_set_txcsum_feature(bp, features);
3595 /* RX checksum offload */
3596 if (changed & NETIF_F_RXCSUM)
3597 macb_set_rxcsum_feature(bp, features);
3599 /* RX Flow Filters */
3600 if (changed & NETIF_F_NTUPLE)
3601 macb_set_rxflow_feature(bp, features);
3606 static void macb_restore_features(struct macb *bp)
3608 struct net_device *netdev = bp->dev;
3609 netdev_features_t features = netdev->features;
3611 /* TX checksum offload */
3612 macb_set_txcsum_feature(bp, features);
3614 /* RX checksum offload */
3615 macb_set_rxcsum_feature(bp, features);
3617 /* RX Flow Filters */
3618 macb_set_rxflow_feature(bp, features);
3621 static const struct net_device_ops macb_netdev_ops = {
3622 .ndo_open = macb_open,
3623 .ndo_stop = macb_close,
3624 .ndo_start_xmit = macb_start_xmit,
3625 .ndo_set_rx_mode = macb_set_rx_mode,
3626 .ndo_get_stats = macb_get_stats,
3627 .ndo_do_ioctl = macb_ioctl,
3628 .ndo_validate_addr = eth_validate_addr,
3629 .ndo_change_mtu = macb_change_mtu,
3630 .ndo_set_mac_address = eth_mac_addr,
3631 #ifdef CONFIG_NET_POLL_CONTROLLER
3632 .ndo_poll_controller = macb_poll_controller,
3634 .ndo_set_features = macb_set_features,
3635 .ndo_features_check = macb_features_check,
3638 /* Configure peripheral capabilities according to device tree
3639 * and integration options used
3641 static void macb_configure_caps(struct macb *bp,
3642 const struct macb_config *dt_conf)
3647 bp->caps = dt_conf->caps;
3649 if (hw_is_gem(bp->regs, bp->native_io)) {
3650 bp->caps |= MACB_CAPS_MACB_IS_GEM;
3652 dcfg = gem_readl(bp, DCFG1);
3653 if (GEM_BFEXT(IRQCOR, dcfg) == 0)
3654 bp->caps |= MACB_CAPS_ISR_CLEAR_ON_WRITE;
3655 if (GEM_BFEXT(NO_PCS, dcfg) == 0)
3656 bp->caps |= MACB_CAPS_PCS;
3657 dcfg = gem_readl(bp, DCFG12);
3658 if (GEM_BFEXT(HIGH_SPEED, dcfg) == 1)
3659 bp->caps |= MACB_CAPS_HIGH_SPEED;
3660 dcfg = gem_readl(bp, DCFG2);
3661 if ((dcfg & (GEM_BIT(RX_PKT_BUFF) | GEM_BIT(TX_PKT_BUFF))) == 0)
3662 bp->caps |= MACB_CAPS_FIFO_MODE;
3663 #ifdef CONFIG_MACB_USE_HWSTAMP
3664 if (gem_has_ptp(bp)) {
3665 if (!GEM_BFEXT(TSU, gem_readl(bp, DCFG5)))
3666 dev_err(&bp->pdev->dev,
3667 "GEM doesn't support hardware ptp.\n");
3669 bp->hw_dma_cap |= HW_DMA_CAP_PTP;
3670 bp->ptp_info = &gem_ptp_info;
3676 dev_dbg(&bp->pdev->dev, "Cadence caps 0x%08x\n", bp->caps);
3679 static void macb_probe_queues(void __iomem *mem,
3681 unsigned int *queue_mask,
3682 unsigned int *num_queues)
3687 /* is it macb or gem ?
3689 * We need to read directly from the hardware here because
3690 * we are early in the probe process and don't have the
3691 * MACB_CAPS_MACB_IS_GEM flag positioned
3693 if (!hw_is_gem(mem, native_io))
3696 /* bit 0 is never set but queue 0 always exists */
3697 *queue_mask |= readl_relaxed(mem + GEM_DCFG6) & 0xff;
3698 *num_queues = hweight32(*queue_mask);
3701 static void macb_clks_disable(struct clk *pclk, struct clk *hclk, struct clk *tx_clk,
3702 struct clk *rx_clk, struct clk *tsu_clk)
3704 struct clk_bulk_data clks[] = {
3705 { .clk = tsu_clk, },
3712 clk_bulk_disable_unprepare(ARRAY_SIZE(clks), clks);
3715 static int macb_clk_init(struct platform_device *pdev, struct clk **pclk,
3716 struct clk **hclk, struct clk **tx_clk,
3717 struct clk **rx_clk, struct clk **tsu_clk)
3719 struct macb_platform_data *pdata;
3722 pdata = dev_get_platdata(&pdev->dev);
3724 *pclk = pdata->pclk;
3725 *hclk = pdata->hclk;
3727 *pclk = devm_clk_get(&pdev->dev, "pclk");
3728 *hclk = devm_clk_get(&pdev->dev, "hclk");
3731 if (IS_ERR_OR_NULL(*pclk)) {
3732 err = IS_ERR(*pclk) ? PTR_ERR(*pclk) : -ENODEV;
3733 dev_err(&pdev->dev, "failed to get macb_clk (%d)\n", err);
3737 if (IS_ERR_OR_NULL(*hclk)) {
3738 err = IS_ERR(*hclk) ? PTR_ERR(*hclk) : -ENODEV;
3739 dev_err(&pdev->dev, "failed to get hclk (%d)\n", err);
3743 *tx_clk = devm_clk_get_optional(&pdev->dev, "tx_clk");
3744 if (IS_ERR(*tx_clk))
3745 return PTR_ERR(*tx_clk);
3747 *rx_clk = devm_clk_get_optional(&pdev->dev, "rx_clk");
3748 if (IS_ERR(*rx_clk))
3749 return PTR_ERR(*rx_clk);
3751 *tsu_clk = devm_clk_get_optional(&pdev->dev, "tsu_clk");
3752 if (IS_ERR(*tsu_clk))
3753 return PTR_ERR(*tsu_clk);
3755 err = clk_prepare_enable(*pclk);
3757 dev_err(&pdev->dev, "failed to enable pclk (%d)\n", err);
3761 err = clk_prepare_enable(*hclk);
3763 dev_err(&pdev->dev, "failed to enable hclk (%d)\n", err);
3764 goto err_disable_pclk;
3767 err = clk_prepare_enable(*tx_clk);
3769 dev_err(&pdev->dev, "failed to enable tx_clk (%d)\n", err);
3770 goto err_disable_hclk;
3773 err = clk_prepare_enable(*rx_clk);
3775 dev_err(&pdev->dev, "failed to enable rx_clk (%d)\n", err);
3776 goto err_disable_txclk;
3779 err = clk_prepare_enable(*tsu_clk);
3781 dev_err(&pdev->dev, "failed to enable tsu_clk (%d)\n", err);
3782 goto err_disable_rxclk;
3788 clk_disable_unprepare(*rx_clk);
3791 clk_disable_unprepare(*tx_clk);
3794 clk_disable_unprepare(*hclk);
3797 clk_disable_unprepare(*pclk);
3802 static int macb_init(struct platform_device *pdev)
3804 struct net_device *dev = platform_get_drvdata(pdev);
3805 unsigned int hw_q, q;
3806 struct macb *bp = netdev_priv(dev);
3807 struct macb_queue *queue;
3811 bp->tx_ring_size = DEFAULT_TX_RING_SIZE;
3812 bp->rx_ring_size = DEFAULT_RX_RING_SIZE;
3814 /* set the queue register mapping once for all: queue0 has a special
3815 * register mapping but we don't want to test the queue index then
3816 * compute the corresponding register offset at run time.
3818 for (hw_q = 0, q = 0; hw_q < MACB_MAX_QUEUES; ++hw_q) {
3819 if (!(bp->queue_mask & (1 << hw_q)))
3822 queue = &bp->queues[q];
3824 netif_napi_add(dev, &queue->napi, macb_poll, NAPI_POLL_WEIGHT);
3826 queue->ISR = GEM_ISR(hw_q - 1);
3827 queue->IER = GEM_IER(hw_q - 1);
3828 queue->IDR = GEM_IDR(hw_q - 1);
3829 queue->IMR = GEM_IMR(hw_q - 1);
3830 queue->TBQP = GEM_TBQP(hw_q - 1);
3831 queue->RBQP = GEM_RBQP(hw_q - 1);
3832 queue->RBQS = GEM_RBQS(hw_q - 1);
3833 #ifdef CONFIG_ARCH_DMA_ADDR_T_64BIT
3834 if (bp->hw_dma_cap & HW_DMA_CAP_64B) {
3835 queue->TBQPH = GEM_TBQPH(hw_q - 1);
3836 queue->RBQPH = GEM_RBQPH(hw_q - 1);
3840 /* queue0 uses legacy registers */
3841 queue->ISR = MACB_ISR;
3842 queue->IER = MACB_IER;
3843 queue->IDR = MACB_IDR;
3844 queue->IMR = MACB_IMR;
3845 queue->TBQP = MACB_TBQP;
3846 queue->RBQP = MACB_RBQP;
3847 #ifdef CONFIG_ARCH_DMA_ADDR_T_64BIT
3848 if (bp->hw_dma_cap & HW_DMA_CAP_64B) {
3849 queue->TBQPH = MACB_TBQPH;
3850 queue->RBQPH = MACB_RBQPH;
3855 /* get irq: here we use the linux queue index, not the hardware
3856 * queue index. the queue irq definitions in the device tree
3857 * must remove the optional gaps that could exist in the
3858 * hardware queue mask.
3860 queue->irq = platform_get_irq(pdev, q);
3861 err = devm_request_irq(&pdev->dev, queue->irq, macb_interrupt,
3862 IRQF_SHARED, dev->name, queue);
3865 "Unable to request IRQ %d (error %d)\n",
3870 INIT_WORK(&queue->tx_error_task, macb_tx_error_task);
3874 dev->netdev_ops = &macb_netdev_ops;
3876 /* setup appropriated routines according to adapter type */
3877 if (macb_is_gem(bp)) {
3878 bp->max_tx_length = GEM_MAX_TX_LEN;
3879 bp->macbgem_ops.mog_alloc_rx_buffers = gem_alloc_rx_buffers;
3880 bp->macbgem_ops.mog_free_rx_buffers = gem_free_rx_buffers;
3881 bp->macbgem_ops.mog_init_rings = gem_init_rings;
3882 bp->macbgem_ops.mog_rx = gem_rx;
3883 dev->ethtool_ops = &gem_ethtool_ops;
3885 bp->max_tx_length = MACB_MAX_TX_LEN;
3886 bp->macbgem_ops.mog_alloc_rx_buffers = macb_alloc_rx_buffers;
3887 bp->macbgem_ops.mog_free_rx_buffers = macb_free_rx_buffers;
3888 bp->macbgem_ops.mog_init_rings = macb_init_rings;
3889 bp->macbgem_ops.mog_rx = macb_rx;
3890 dev->ethtool_ops = &macb_ethtool_ops;
3894 dev->hw_features = NETIF_F_SG;
3896 /* Check LSO capability */
3897 if (GEM_BFEXT(PBUF_LSO, gem_readl(bp, DCFG6)))
3898 dev->hw_features |= MACB_NETIF_LSO;
3900 /* Checksum offload is only available on gem with packet buffer */
3901 if (macb_is_gem(bp) && !(bp->caps & MACB_CAPS_FIFO_MODE))
3902 dev->hw_features |= NETIF_F_HW_CSUM | NETIF_F_RXCSUM;
3903 if (bp->caps & MACB_CAPS_SG_DISABLED)
3904 dev->hw_features &= ~NETIF_F_SG;
3905 dev->features = dev->hw_features;
3907 /* Check RX Flow Filters support.
3908 * Max Rx flows set by availability of screeners & compare regs:
3909 * each 4-tuple define requires 1 T2 screener reg + 3 compare regs
3911 reg = gem_readl(bp, DCFG8);
3912 bp->max_tuples = min((GEM_BFEXT(SCR2CMP, reg) / 3),
3913 GEM_BFEXT(T2SCR, reg));
3914 if (bp->max_tuples > 0) {
3915 /* also needs one ethtype match to check IPv4 */
3916 if (GEM_BFEXT(SCR2ETH, reg) > 0) {
3917 /* program this reg now */
3919 reg = GEM_BFINS(ETHTCMP, (uint16_t)ETH_P_IP, reg);
3920 gem_writel_n(bp, ETHT, SCRT2_ETHT, reg);
3921 /* Filtering is supported in hw but don't enable it in kernel now */
3922 dev->hw_features |= NETIF_F_NTUPLE;
3923 /* init Rx flow definitions */
3924 INIT_LIST_HEAD(&bp->rx_fs_list.list);
3925 bp->rx_fs_list.count = 0;
3926 spin_lock_init(&bp->rx_fs_lock);
3931 if (!(bp->caps & MACB_CAPS_USRIO_DISABLED)) {
3933 if (phy_interface_mode_is_rgmii(bp->phy_interface))
3934 val = bp->usrio->rgmii;
3935 else if (bp->phy_interface == PHY_INTERFACE_MODE_RMII &&
3936 (bp->caps & MACB_CAPS_USRIO_DEFAULT_IS_MII_GMII))
3937 val = bp->usrio->rmii;
3938 else if (!(bp->caps & MACB_CAPS_USRIO_DEFAULT_IS_MII_GMII))
3939 val = bp->usrio->mii;
3941 if (bp->caps & MACB_CAPS_USRIO_HAS_CLKEN)
3942 val |= bp->usrio->refclk;
3944 macb_or_gem_writel(bp, USRIO, val);
3947 /* Set MII management clock divider */
3948 val = macb_mdc_clk_div(bp);
3949 val |= macb_dbw(bp);
3950 if (bp->phy_interface == PHY_INTERFACE_MODE_SGMII)
3951 val |= GEM_BIT(SGMIIEN) | GEM_BIT(PCSSEL);
3952 macb_writel(bp, NCFGR, val);
3957 #if defined(CONFIG_OF)
3958 /* 1518 rounded up */
3959 #define AT91ETHER_MAX_RBUFF_SZ 0x600
3960 /* max number of receive buffers */
3961 #define AT91ETHER_MAX_RX_DESCR 9
3963 static struct sifive_fu540_macb_mgmt *mgmt;
3965 static int at91ether_alloc_coherent(struct macb *lp)
3967 struct macb_queue *q = &lp->queues[0];
3969 q->rx_ring = dma_alloc_coherent(&lp->pdev->dev,
3970 (AT91ETHER_MAX_RX_DESCR *
3971 macb_dma_desc_get_size(lp)),
3972 &q->rx_ring_dma, GFP_KERNEL);
3976 q->rx_buffers = dma_alloc_coherent(&lp->pdev->dev,
3977 AT91ETHER_MAX_RX_DESCR *
3978 AT91ETHER_MAX_RBUFF_SZ,
3979 &q->rx_buffers_dma, GFP_KERNEL);
3980 if (!q->rx_buffers) {
3981 dma_free_coherent(&lp->pdev->dev,
3982 AT91ETHER_MAX_RX_DESCR *
3983 macb_dma_desc_get_size(lp),
3984 q->rx_ring, q->rx_ring_dma);
3992 static void at91ether_free_coherent(struct macb *lp)
3994 struct macb_queue *q = &lp->queues[0];
3997 dma_free_coherent(&lp->pdev->dev,
3998 AT91ETHER_MAX_RX_DESCR *
3999 macb_dma_desc_get_size(lp),
4000 q->rx_ring, q->rx_ring_dma);
4004 if (q->rx_buffers) {
4005 dma_free_coherent(&lp->pdev->dev,
4006 AT91ETHER_MAX_RX_DESCR *
4007 AT91ETHER_MAX_RBUFF_SZ,
4008 q->rx_buffers, q->rx_buffers_dma);
4009 q->rx_buffers = NULL;
4013 /* Initialize and start the Receiver and Transmit subsystems */
4014 static int at91ether_start(struct macb *lp)
4016 struct macb_queue *q = &lp->queues[0];
4017 struct macb_dma_desc *desc;
4022 ret = at91ether_alloc_coherent(lp);
4026 addr = q->rx_buffers_dma;
4027 for (i = 0; i < AT91ETHER_MAX_RX_DESCR; i++) {
4028 desc = macb_rx_desc(q, i);
4029 macb_set_addr(lp, desc, addr);
4031 addr += AT91ETHER_MAX_RBUFF_SZ;
4034 /* Set the Wrap bit on the last descriptor */
4035 desc->addr |= MACB_BIT(RX_WRAP);
4037 /* Reset buffer index */
4040 /* Program address of descriptor list in Rx Buffer Queue register */
4041 macb_writel(lp, RBQP, q->rx_ring_dma);
4043 /* Enable Receive and Transmit */
4044 ctl = macb_readl(lp, NCR);
4045 macb_writel(lp, NCR, ctl | MACB_BIT(RE) | MACB_BIT(TE));
4047 /* Enable MAC interrupts */
4048 macb_writel(lp, IER, MACB_BIT(RCOMP) |
4050 MACB_BIT(ISR_TUND) |
4053 MACB_BIT(ISR_ROVR) |
4059 static void at91ether_stop(struct macb *lp)
4063 /* Disable MAC interrupts */
4064 macb_writel(lp, IDR, MACB_BIT(RCOMP) |
4066 MACB_BIT(ISR_TUND) |
4069 MACB_BIT(ISR_ROVR) |
4072 /* Disable Receiver and Transmitter */
4073 ctl = macb_readl(lp, NCR);
4074 macb_writel(lp, NCR, ctl & ~(MACB_BIT(TE) | MACB_BIT(RE)));
4076 /* Free resources. */
4077 at91ether_free_coherent(lp);
4080 /* Open the ethernet interface */
4081 static int at91ether_open(struct net_device *dev)
4083 struct macb *lp = netdev_priv(dev);
4087 ret = pm_runtime_get_sync(&lp->pdev->dev);
4089 pm_runtime_put_noidle(&lp->pdev->dev);
4093 /* Clear internal statistics */
4094 ctl = macb_readl(lp, NCR);
4095 macb_writel(lp, NCR, ctl | MACB_BIT(CLRSTAT));
4097 macb_set_hwaddr(lp);
4099 ret = at91ether_start(lp);
4103 ret = macb_phylink_connect(lp);
4107 netif_start_queue(dev);
4114 pm_runtime_put_sync(&lp->pdev->dev);
4118 /* Close the interface */
4119 static int at91ether_close(struct net_device *dev)
4121 struct macb *lp = netdev_priv(dev);
4123 netif_stop_queue(dev);
4125 phylink_stop(lp->phylink);
4126 phylink_disconnect_phy(lp->phylink);
4130 return pm_runtime_put(&lp->pdev->dev);
4133 /* Transmit packet */
4134 static netdev_tx_t at91ether_start_xmit(struct sk_buff *skb,
4135 struct net_device *dev)
4137 struct macb *lp = netdev_priv(dev);
4139 if (macb_readl(lp, TSR) & MACB_BIT(RM9200_BNQ)) {
4142 netif_stop_queue(dev);
4144 /* Store packet information (to free when Tx completed) */
4145 lp->rm9200_txq[desc].skb = skb;
4146 lp->rm9200_txq[desc].size = skb->len;
4147 lp->rm9200_txq[desc].mapping = dma_map_single(&lp->pdev->dev, skb->data,
4148 skb->len, DMA_TO_DEVICE);
4149 if (dma_mapping_error(&lp->pdev->dev, lp->rm9200_txq[desc].mapping)) {
4150 dev_kfree_skb_any(skb);
4151 dev->stats.tx_dropped++;
4152 netdev_err(dev, "%s: DMA mapping error\n", __func__);
4153 return NETDEV_TX_OK;
4156 /* Set address of the data in the Transmit Address register */
4157 macb_writel(lp, TAR, lp->rm9200_txq[desc].mapping);
4158 /* Set length of the packet in the Transmit Control register */
4159 macb_writel(lp, TCR, skb->len);
4162 netdev_err(dev, "%s called, but device is busy!\n", __func__);
4163 return NETDEV_TX_BUSY;
4166 return NETDEV_TX_OK;
4169 /* Extract received frame from buffer descriptors and sent to upper layers.
4170 * (Called from interrupt context)
4172 static void at91ether_rx(struct net_device *dev)
4174 struct macb *lp = netdev_priv(dev);
4175 struct macb_queue *q = &lp->queues[0];
4176 struct macb_dma_desc *desc;
4177 unsigned char *p_recv;
4178 struct sk_buff *skb;
4179 unsigned int pktlen;
4181 desc = macb_rx_desc(q, q->rx_tail);
4182 while (desc->addr & MACB_BIT(RX_USED)) {
4183 p_recv = q->rx_buffers + q->rx_tail * AT91ETHER_MAX_RBUFF_SZ;
4184 pktlen = MACB_BF(RX_FRMLEN, desc->ctrl);
4185 skb = netdev_alloc_skb(dev, pktlen + 2);
4187 skb_reserve(skb, 2);
4188 skb_put_data(skb, p_recv, pktlen);
4190 skb->protocol = eth_type_trans(skb, dev);
4191 dev->stats.rx_packets++;
4192 dev->stats.rx_bytes += pktlen;
4195 dev->stats.rx_dropped++;
4198 if (desc->ctrl & MACB_BIT(RX_MHASH_MATCH))
4199 dev->stats.multicast++;
4201 /* reset ownership bit */
4202 desc->addr &= ~MACB_BIT(RX_USED);
4204 /* wrap after last buffer */
4205 if (q->rx_tail == AT91ETHER_MAX_RX_DESCR - 1)
4210 desc = macb_rx_desc(q, q->rx_tail);
4214 /* MAC interrupt handler */
4215 static irqreturn_t at91ether_interrupt(int irq, void *dev_id)
4217 struct net_device *dev = dev_id;
4218 struct macb *lp = netdev_priv(dev);
4222 /* MAC Interrupt Status register indicates what interrupts are pending.
4223 * It is automatically cleared once read.
4225 intstatus = macb_readl(lp, ISR);
4227 /* Receive complete */
4228 if (intstatus & MACB_BIT(RCOMP))
4231 /* Transmit complete */
4232 if (intstatus & MACB_BIT(TCOMP)) {
4233 /* The TCOM bit is set even if the transmission failed */
4234 if (intstatus & (MACB_BIT(ISR_TUND) | MACB_BIT(ISR_RLE)))
4235 dev->stats.tx_errors++;
4238 if (lp->rm9200_txq[desc].skb) {
4239 dev_consume_skb_irq(lp->rm9200_txq[desc].skb);
4240 lp->rm9200_txq[desc].skb = NULL;
4241 dma_unmap_single(&lp->pdev->dev, lp->rm9200_txq[desc].mapping,
4242 lp->rm9200_txq[desc].size, DMA_TO_DEVICE);
4243 dev->stats.tx_packets++;
4244 dev->stats.tx_bytes += lp->rm9200_txq[desc].size;
4246 netif_wake_queue(dev);
4249 /* Work-around for EMAC Errata section 41.3.1 */
4250 if (intstatus & MACB_BIT(RXUBR)) {
4251 ctl = macb_readl(lp, NCR);
4252 macb_writel(lp, NCR, ctl & ~MACB_BIT(RE));
4254 macb_writel(lp, NCR, ctl | MACB_BIT(RE));
4257 if (intstatus & MACB_BIT(ISR_ROVR))
4258 netdev_err(dev, "ROVR error\n");
4263 #ifdef CONFIG_NET_POLL_CONTROLLER
4264 static void at91ether_poll_controller(struct net_device *dev)
4266 unsigned long flags;
4268 local_irq_save(flags);
4269 at91ether_interrupt(dev->irq, dev);
4270 local_irq_restore(flags);
4274 static const struct net_device_ops at91ether_netdev_ops = {
4275 .ndo_open = at91ether_open,
4276 .ndo_stop = at91ether_close,
4277 .ndo_start_xmit = at91ether_start_xmit,
4278 .ndo_get_stats = macb_get_stats,
4279 .ndo_set_rx_mode = macb_set_rx_mode,
4280 .ndo_set_mac_address = eth_mac_addr,
4281 .ndo_do_ioctl = macb_ioctl,
4282 .ndo_validate_addr = eth_validate_addr,
4283 #ifdef CONFIG_NET_POLL_CONTROLLER
4284 .ndo_poll_controller = at91ether_poll_controller,
4288 static int at91ether_clk_init(struct platform_device *pdev, struct clk **pclk,
4289 struct clk **hclk, struct clk **tx_clk,
4290 struct clk **rx_clk, struct clk **tsu_clk)
4299 *pclk = devm_clk_get(&pdev->dev, "ether_clk");
4301 return PTR_ERR(*pclk);
4303 err = clk_prepare_enable(*pclk);
4305 dev_err(&pdev->dev, "failed to enable pclk (%d)\n", err);
4312 static int at91ether_init(struct platform_device *pdev)
4314 struct net_device *dev = platform_get_drvdata(pdev);
4315 struct macb *bp = netdev_priv(dev);
4318 bp->queues[0].bp = bp;
4320 dev->netdev_ops = &at91ether_netdev_ops;
4321 dev->ethtool_ops = &macb_ethtool_ops;
4323 err = devm_request_irq(&pdev->dev, dev->irq, at91ether_interrupt,
4328 macb_writel(bp, NCR, 0);
4330 macb_writel(bp, NCFGR, MACB_BF(CLK, MACB_CLK_DIV32) | MACB_BIT(BIG));
4335 static unsigned long fu540_macb_tx_recalc_rate(struct clk_hw *hw,
4336 unsigned long parent_rate)
4341 static long fu540_macb_tx_round_rate(struct clk_hw *hw, unsigned long rate,
4342 unsigned long *parent_rate)
4344 if (WARN_ON(rate < 2500000))
4346 else if (rate == 2500000)
4348 else if (WARN_ON(rate < 13750000))
4350 else if (WARN_ON(rate < 25000000))
4352 else if (rate == 25000000)
4354 else if (WARN_ON(rate < 75000000))
4356 else if (WARN_ON(rate < 125000000))
4358 else if (rate == 125000000)
4361 WARN_ON(rate > 125000000);
4366 static int fu540_macb_tx_set_rate(struct clk_hw *hw, unsigned long rate,
4367 unsigned long parent_rate)
4369 rate = fu540_macb_tx_round_rate(hw, rate, &parent_rate);
4370 if (rate != 125000000)
4371 iowrite32(1, mgmt->reg);
4373 iowrite32(0, mgmt->reg);
4379 static const struct clk_ops fu540_c000_ops = {
4380 .recalc_rate = fu540_macb_tx_recalc_rate,
4381 .round_rate = fu540_macb_tx_round_rate,
4382 .set_rate = fu540_macb_tx_set_rate,
4385 static int fu540_c000_clk_init(struct platform_device *pdev, struct clk **pclk,
4386 struct clk **hclk, struct clk **tx_clk,
4387 struct clk **rx_clk, struct clk **tsu_clk)
4389 struct clk_init_data init;
4392 err = macb_clk_init(pdev, pclk, hclk, tx_clk, rx_clk, tsu_clk);
4396 mgmt = devm_kzalloc(&pdev->dev, sizeof(*mgmt), GFP_KERNEL);
4399 goto err_disable_clks;
4402 init.name = "sifive-gemgxl-mgmt";
4403 init.ops = &fu540_c000_ops;
4405 init.num_parents = 0;
4408 mgmt->hw.init = &init;
4410 *tx_clk = devm_clk_register(&pdev->dev, &mgmt->hw);
4411 if (IS_ERR(*tx_clk)) {
4412 err = PTR_ERR(*tx_clk);
4413 goto err_disable_clks;
4416 err = clk_prepare_enable(*tx_clk);
4418 dev_err(&pdev->dev, "failed to enable tx_clk (%u)\n", err);
4420 goto err_disable_clks;
4422 dev_info(&pdev->dev, "Registered clk switch '%s'\n", init.name);
4428 macb_clks_disable(*pclk, *hclk, *tx_clk, *rx_clk, *tsu_clk);
4433 static int fu540_c000_init(struct platform_device *pdev)
4435 mgmt->reg = devm_platform_ioremap_resource(pdev, 1);
4436 if (IS_ERR(mgmt->reg))
4437 return PTR_ERR(mgmt->reg);
4439 return macb_init(pdev);
4442 static const struct macb_usrio_config macb_default_usrio = {
4443 .mii = MACB_BIT(MII),
4444 .rmii = MACB_BIT(RMII),
4445 .rgmii = GEM_BIT(RGMII),
4446 .refclk = MACB_BIT(CLKEN),
4449 static const struct macb_usrio_config sama7g5_usrio = {
4457 static const struct macb_config fu540_c000_config = {
4458 .caps = MACB_CAPS_GIGABIT_MODE_AVAILABLE | MACB_CAPS_JUMBO |
4459 MACB_CAPS_GEM_HAS_PTP,
4460 .dma_burst_length = 16,
4461 .clk_init = fu540_c000_clk_init,
4462 .init = fu540_c000_init,
4463 .jumbo_max_len = 10240,
4464 .usrio = &macb_default_usrio,
4467 static const struct macb_config at91sam9260_config = {
4468 .caps = MACB_CAPS_USRIO_HAS_CLKEN | MACB_CAPS_USRIO_DEFAULT_IS_MII_GMII,
4469 .clk_init = macb_clk_init,
4471 .usrio = &macb_default_usrio,
4474 static const struct macb_config sama5d3macb_config = {
4475 .caps = MACB_CAPS_SG_DISABLED
4476 | MACB_CAPS_USRIO_HAS_CLKEN | MACB_CAPS_USRIO_DEFAULT_IS_MII_GMII,
4477 .clk_init = macb_clk_init,
4479 .usrio = &macb_default_usrio,
4482 static const struct macb_config pc302gem_config = {
4483 .caps = MACB_CAPS_SG_DISABLED | MACB_CAPS_GIGABIT_MODE_AVAILABLE,
4484 .dma_burst_length = 16,
4485 .clk_init = macb_clk_init,
4487 .usrio = &macb_default_usrio,
4490 static const struct macb_config sama5d2_config = {
4491 .caps = MACB_CAPS_USRIO_DEFAULT_IS_MII_GMII,
4492 .dma_burst_length = 16,
4493 .clk_init = macb_clk_init,
4495 .usrio = &macb_default_usrio,
4498 static const struct macb_config sama5d3_config = {
4499 .caps = MACB_CAPS_SG_DISABLED | MACB_CAPS_GIGABIT_MODE_AVAILABLE
4500 | MACB_CAPS_USRIO_DEFAULT_IS_MII_GMII | MACB_CAPS_JUMBO,
4501 .dma_burst_length = 16,
4502 .clk_init = macb_clk_init,
4504 .jumbo_max_len = 10240,
4505 .usrio = &macb_default_usrio,
4508 static const struct macb_config sama5d4_config = {
4509 .caps = MACB_CAPS_USRIO_DEFAULT_IS_MII_GMII,
4510 .dma_burst_length = 4,
4511 .clk_init = macb_clk_init,
4513 .usrio = &macb_default_usrio,
4516 static const struct macb_config emac_config = {
4517 .caps = MACB_CAPS_NEEDS_RSTONUBR | MACB_CAPS_MACB_IS_EMAC,
4518 .clk_init = at91ether_clk_init,
4519 .init = at91ether_init,
4520 .usrio = &macb_default_usrio,
4523 static const struct macb_config np4_config = {
4524 .caps = MACB_CAPS_USRIO_DISABLED,
4525 .clk_init = macb_clk_init,
4527 .usrio = &macb_default_usrio,
4530 static const struct macb_config zynqmp_config = {
4531 .caps = MACB_CAPS_GIGABIT_MODE_AVAILABLE |
4533 MACB_CAPS_GEM_HAS_PTP | MACB_CAPS_BD_RD_PREFETCH,
4534 .dma_burst_length = 16,
4535 .clk_init = macb_clk_init,
4537 .jumbo_max_len = 10240,
4538 .usrio = &macb_default_usrio,
4541 static const struct macb_config zynq_config = {
4542 .caps = MACB_CAPS_GIGABIT_MODE_AVAILABLE | MACB_CAPS_NO_GIGABIT_HALF |
4543 MACB_CAPS_NEEDS_RSTONUBR,
4544 .dma_burst_length = 16,
4545 .clk_init = macb_clk_init,
4547 .usrio = &macb_default_usrio,
4550 static const struct macb_config sama7g5_gem_config = {
4551 .caps = MACB_CAPS_GIGABIT_MODE_AVAILABLE | MACB_CAPS_CLK_HW_CHG,
4552 .dma_burst_length = 16,
4553 .clk_init = macb_clk_init,
4555 .usrio = &sama7g5_usrio,
4558 static const struct macb_config sama7g5_emac_config = {
4559 .caps = MACB_CAPS_USRIO_DEFAULT_IS_MII_GMII | MACB_CAPS_USRIO_HAS_CLKEN,
4560 .dma_burst_length = 16,
4561 .clk_init = macb_clk_init,
4563 .usrio = &sama7g5_usrio,
4566 static const struct of_device_id macb_dt_ids[] = {
4567 { .compatible = "cdns,at32ap7000-macb" },
4568 { .compatible = "cdns,at91sam9260-macb", .data = &at91sam9260_config },
4569 { .compatible = "cdns,macb" },
4570 { .compatible = "cdns,np4-macb", .data = &np4_config },
4571 { .compatible = "cdns,pc302-gem", .data = &pc302gem_config },
4572 { .compatible = "cdns,gem", .data = &pc302gem_config },
4573 { .compatible = "cdns,sam9x60-macb", .data = &at91sam9260_config },
4574 { .compatible = "atmel,sama5d2-gem", .data = &sama5d2_config },
4575 { .compatible = "atmel,sama5d3-gem", .data = &sama5d3_config },
4576 { .compatible = "atmel,sama5d3-macb", .data = &sama5d3macb_config },
4577 { .compatible = "atmel,sama5d4-gem", .data = &sama5d4_config },
4578 { .compatible = "cdns,at91rm9200-emac", .data = &emac_config },
4579 { .compatible = "cdns,emac", .data = &emac_config },
4580 { .compatible = "cdns,zynqmp-gem", .data = &zynqmp_config},
4581 { .compatible = "cdns,zynq-gem", .data = &zynq_config },
4582 { .compatible = "sifive,fu540-c000-gem", .data = &fu540_c000_config },
4583 { .compatible = "microchip,sama7g5-gem", .data = &sama7g5_gem_config },
4584 { .compatible = "microchip,sama7g5-emac", .data = &sama7g5_emac_config },
4587 MODULE_DEVICE_TABLE(of, macb_dt_ids);
4588 #endif /* CONFIG_OF */
4590 static const struct macb_config default_gem_config = {
4591 .caps = MACB_CAPS_GIGABIT_MODE_AVAILABLE |
4593 MACB_CAPS_GEM_HAS_PTP,
4594 .dma_burst_length = 16,
4595 .clk_init = macb_clk_init,
4597 .jumbo_max_len = 10240,
4600 static int macb_probe(struct platform_device *pdev)
4602 const struct macb_config *macb_config = &default_gem_config;
4603 int (*clk_init)(struct platform_device *, struct clk **,
4604 struct clk **, struct clk **, struct clk **,
4605 struct clk **) = macb_config->clk_init;
4606 int (*init)(struct platform_device *) = macb_config->init;
4607 struct device_node *np = pdev->dev.of_node;
4608 struct clk *pclk, *hclk = NULL, *tx_clk = NULL, *rx_clk = NULL;
4609 struct clk *tsu_clk = NULL;
4610 unsigned int queue_mask, num_queues;
4612 phy_interface_t interface;
4613 struct net_device *dev;
4614 struct resource *regs;
4620 regs = platform_get_resource(pdev, IORESOURCE_MEM, 0);
4621 mem = devm_ioremap_resource(&pdev->dev, regs);
4623 return PTR_ERR(mem);
4626 const struct of_device_id *match;
4628 match = of_match_node(macb_dt_ids, np);
4629 if (match && match->data) {
4630 macb_config = match->data;
4631 clk_init = macb_config->clk_init;
4632 init = macb_config->init;
4636 err = clk_init(pdev, &pclk, &hclk, &tx_clk, &rx_clk, &tsu_clk);
4640 pm_runtime_set_autosuspend_delay(&pdev->dev, MACB_PM_TIMEOUT);
4641 pm_runtime_use_autosuspend(&pdev->dev);
4642 pm_runtime_get_noresume(&pdev->dev);
4643 pm_runtime_set_active(&pdev->dev);
4644 pm_runtime_enable(&pdev->dev);
4645 native_io = hw_is_native_io(mem);
4647 macb_probe_queues(mem, native_io, &queue_mask, &num_queues);
4648 dev = alloc_etherdev_mq(sizeof(*bp), num_queues);
4651 goto err_disable_clocks;
4654 dev->base_addr = regs->start;
4656 SET_NETDEV_DEV(dev, &pdev->dev);
4658 bp = netdev_priv(dev);
4662 bp->native_io = native_io;
4664 bp->macb_reg_readl = hw_readl_native;
4665 bp->macb_reg_writel = hw_writel_native;
4667 bp->macb_reg_readl = hw_readl;
4668 bp->macb_reg_writel = hw_writel;
4670 bp->num_queues = num_queues;
4671 bp->queue_mask = queue_mask;
4673 bp->dma_burst_length = macb_config->dma_burst_length;
4676 bp->tx_clk = tx_clk;
4677 bp->rx_clk = rx_clk;
4678 bp->tsu_clk = tsu_clk;
4680 bp->jumbo_max_len = macb_config->jumbo_max_len;
4683 if (of_get_property(np, "magic-packet", NULL))
4684 bp->wol |= MACB_WOL_HAS_MAGIC_PACKET;
4685 device_set_wakeup_capable(&pdev->dev, bp->wol & MACB_WOL_HAS_MAGIC_PACKET);
4687 bp->usrio = macb_config->usrio;
4689 spin_lock_init(&bp->lock);
4691 /* setup capabilities */
4692 macb_configure_caps(bp, macb_config);
4694 #ifdef CONFIG_ARCH_DMA_ADDR_T_64BIT
4695 if (GEM_BFEXT(DAW64, gem_readl(bp, DCFG6))) {
4696 dma_set_mask(&pdev->dev, DMA_BIT_MASK(44));
4697 bp->hw_dma_cap |= HW_DMA_CAP_64B;
4700 platform_set_drvdata(pdev, dev);
4702 dev->irq = platform_get_irq(pdev, 0);
4705 goto err_out_free_netdev;
4708 /* MTU range: 68 - 1500 or 10240 */
4709 dev->min_mtu = GEM_MTU_MIN_SIZE;
4710 if (bp->caps & MACB_CAPS_JUMBO)
4711 dev->max_mtu = gem_readl(bp, JML) - ETH_HLEN - ETH_FCS_LEN;
4713 dev->max_mtu = ETH_DATA_LEN;
4715 if (bp->caps & MACB_CAPS_BD_RD_PREFETCH) {
4716 val = GEM_BFEXT(RXBD_RDBUFF, gem_readl(bp, DCFG10));
4718 bp->rx_bd_rd_prefetch = (2 << (val - 1)) *
4719 macb_dma_desc_get_size(bp);
4721 val = GEM_BFEXT(TXBD_RDBUFF, gem_readl(bp, DCFG10));
4723 bp->tx_bd_rd_prefetch = (2 << (val - 1)) *
4724 macb_dma_desc_get_size(bp);
4727 bp->rx_intr_mask = MACB_RX_INT_FLAGS;
4728 if (bp->caps & MACB_CAPS_NEEDS_RSTONUBR)
4729 bp->rx_intr_mask |= MACB_BIT(RXUBR);
4731 mac = of_get_mac_address(np);
4732 if (PTR_ERR(mac) == -EPROBE_DEFER) {
4733 err = -EPROBE_DEFER;
4734 goto err_out_free_netdev;
4735 } else if (!IS_ERR_OR_NULL(mac)) {
4736 ether_addr_copy(bp->dev->dev_addr, mac);
4738 macb_get_hwaddr(bp);
4741 err = of_get_phy_mode(np, &interface);
4743 /* not found in DT, MII by default */
4744 bp->phy_interface = PHY_INTERFACE_MODE_MII;
4746 bp->phy_interface = interface;
4748 /* IP specific init */
4751 goto err_out_free_netdev;
4753 err = macb_mii_init(bp);
4755 goto err_out_free_netdev;
4757 netif_carrier_off(dev);
4759 err = register_netdev(dev);
4761 dev_err(&pdev->dev, "Cannot register net device, aborting.\n");
4762 goto err_out_unregister_mdio;
4765 tasklet_setup(&bp->hresp_err_tasklet, macb_hresp_error_task);
4767 netdev_info(dev, "Cadence %s rev 0x%08x at 0x%08lx irq %d (%pM)\n",
4768 macb_is_gem(bp) ? "GEM" : "MACB", macb_readl(bp, MID),
4769 dev->base_addr, dev->irq, dev->dev_addr);
4771 pm_runtime_mark_last_busy(&bp->pdev->dev);
4772 pm_runtime_put_autosuspend(&bp->pdev->dev);
4776 err_out_unregister_mdio:
4777 mdiobus_unregister(bp->mii_bus);
4778 mdiobus_free(bp->mii_bus);
4780 err_out_free_netdev:
4784 macb_clks_disable(pclk, hclk, tx_clk, rx_clk, tsu_clk);
4785 pm_runtime_disable(&pdev->dev);
4786 pm_runtime_set_suspended(&pdev->dev);
4787 pm_runtime_dont_use_autosuspend(&pdev->dev);
4792 static int macb_remove(struct platform_device *pdev)
4794 struct net_device *dev;
4797 dev = platform_get_drvdata(pdev);
4800 bp = netdev_priv(dev);
4801 mdiobus_unregister(bp->mii_bus);
4802 mdiobus_free(bp->mii_bus);
4804 unregister_netdev(dev);
4805 tasklet_kill(&bp->hresp_err_tasklet);
4806 pm_runtime_disable(&pdev->dev);
4807 pm_runtime_dont_use_autosuspend(&pdev->dev);
4808 if (!pm_runtime_suspended(&pdev->dev)) {
4809 macb_clks_disable(bp->pclk, bp->hclk, bp->tx_clk,
4810 bp->rx_clk, bp->tsu_clk);
4811 pm_runtime_set_suspended(&pdev->dev);
4813 phylink_destroy(bp->phylink);
4820 static int __maybe_unused macb_suspend(struct device *dev)
4822 struct net_device *netdev = dev_get_drvdata(dev);
4823 struct macb *bp = netdev_priv(netdev);
4824 struct macb_queue *queue = bp->queues;
4825 unsigned long flags;
4829 if (!netif_running(netdev))
4832 if (bp->wol & MACB_WOL_ENABLED) {
4833 spin_lock_irqsave(&bp->lock, flags);
4834 /* Flush all status bits */
4835 macb_writel(bp, TSR, -1);
4836 macb_writel(bp, RSR, -1);
4837 for (q = 0, queue = bp->queues; q < bp->num_queues;
4839 /* Disable all interrupts */
4840 queue_writel(queue, IDR, -1);
4841 queue_readl(queue, ISR);
4842 if (bp->caps & MACB_CAPS_ISR_CLEAR_ON_WRITE)
4843 queue_writel(queue, ISR, -1);
4845 /* Change interrupt handler and
4846 * Enable WoL IRQ on queue 0
4848 devm_free_irq(dev, bp->queues[0].irq, bp->queues);
4849 if (macb_is_gem(bp)) {
4850 err = devm_request_irq(dev, bp->queues[0].irq, gem_wol_interrupt,
4851 IRQF_SHARED, netdev->name, bp->queues);
4854 "Unable to request IRQ %d (error %d)\n",
4855 bp->queues[0].irq, err);
4856 spin_unlock_irqrestore(&bp->lock, flags);
4859 queue_writel(bp->queues, IER, GEM_BIT(WOL));
4860 gem_writel(bp, WOL, MACB_BIT(MAG));
4862 err = devm_request_irq(dev, bp->queues[0].irq, macb_wol_interrupt,
4863 IRQF_SHARED, netdev->name, bp->queues);
4866 "Unable to request IRQ %d (error %d)\n",
4867 bp->queues[0].irq, err);
4868 spin_unlock_irqrestore(&bp->lock, flags);
4871 queue_writel(bp->queues, IER, MACB_BIT(WOL));
4872 macb_writel(bp, WOL, MACB_BIT(MAG));
4874 spin_unlock_irqrestore(&bp->lock, flags);
4876 enable_irq_wake(bp->queues[0].irq);
4879 netif_device_detach(netdev);
4880 for (q = 0, queue = bp->queues; q < bp->num_queues;
4882 napi_disable(&queue->napi);
4884 if (!(bp->wol & MACB_WOL_ENABLED)) {
4886 phylink_stop(bp->phylink);
4888 spin_lock_irqsave(&bp->lock, flags);
4890 spin_unlock_irqrestore(&bp->lock, flags);
4893 if (!(bp->caps & MACB_CAPS_USRIO_DISABLED))
4894 bp->pm_data.usrio = macb_or_gem_readl(bp, USRIO);
4896 if (netdev->hw_features & NETIF_F_NTUPLE)
4897 bp->pm_data.scrt2 = gem_readl_n(bp, ETHT, SCRT2_ETHT);
4900 bp->ptp_info->ptp_remove(netdev);
4901 if (!device_may_wakeup(dev))
4902 pm_runtime_force_suspend(dev);
4907 static int __maybe_unused macb_resume(struct device *dev)
4909 struct net_device *netdev = dev_get_drvdata(dev);
4910 struct macb *bp = netdev_priv(netdev);
4911 struct macb_queue *queue = bp->queues;
4912 unsigned long flags;
4916 if (!netif_running(netdev))
4919 if (!device_may_wakeup(dev))
4920 pm_runtime_force_resume(dev);
4922 if (bp->wol & MACB_WOL_ENABLED) {
4923 spin_lock_irqsave(&bp->lock, flags);
4925 if (macb_is_gem(bp)) {
4926 queue_writel(bp->queues, IDR, GEM_BIT(WOL));
4927 gem_writel(bp, WOL, 0);
4929 queue_writel(bp->queues, IDR, MACB_BIT(WOL));
4930 macb_writel(bp, WOL, 0);
4932 /* Clear ISR on queue 0 */
4933 queue_readl(bp->queues, ISR);
4934 if (bp->caps & MACB_CAPS_ISR_CLEAR_ON_WRITE)
4935 queue_writel(bp->queues, ISR, -1);
4936 /* Replace interrupt handler on queue 0 */
4937 devm_free_irq(dev, bp->queues[0].irq, bp->queues);
4938 err = devm_request_irq(dev, bp->queues[0].irq, macb_interrupt,
4939 IRQF_SHARED, netdev->name, bp->queues);
4942 "Unable to request IRQ %d (error %d)\n",
4943 bp->queues[0].irq, err);
4944 spin_unlock_irqrestore(&bp->lock, flags);
4947 spin_unlock_irqrestore(&bp->lock, flags);
4949 disable_irq_wake(bp->queues[0].irq);
4951 /* Now make sure we disable phy before moving
4952 * to common restore path
4955 phylink_stop(bp->phylink);
4959 for (q = 0, queue = bp->queues; q < bp->num_queues;
4961 napi_enable(&queue->napi);
4963 if (netdev->hw_features & NETIF_F_NTUPLE)
4964 gem_writel_n(bp, ETHT, SCRT2_ETHT, bp->pm_data.scrt2);
4966 if (!(bp->caps & MACB_CAPS_USRIO_DISABLED))
4967 macb_or_gem_writel(bp, USRIO, bp->pm_data.usrio);
4969 macb_writel(bp, NCR, MACB_BIT(MPE));
4971 macb_set_rx_mode(netdev);
4972 macb_restore_features(bp);
4974 phylink_start(bp->phylink);
4977 netif_device_attach(netdev);
4979 bp->ptp_info->ptp_init(netdev);
4984 static int __maybe_unused macb_runtime_suspend(struct device *dev)
4986 struct net_device *netdev = dev_get_drvdata(dev);
4987 struct macb *bp = netdev_priv(netdev);
4989 if (!(device_may_wakeup(dev)))
4990 macb_clks_disable(bp->pclk, bp->hclk, bp->tx_clk, bp->rx_clk, bp->tsu_clk);
4992 macb_clks_disable(NULL, NULL, NULL, NULL, bp->tsu_clk);
4997 static int __maybe_unused macb_runtime_resume(struct device *dev)
4999 struct net_device *netdev = dev_get_drvdata(dev);
5000 struct macb *bp = netdev_priv(netdev);
5002 if (!(device_may_wakeup(dev))) {
5003 clk_prepare_enable(bp->pclk);
5004 clk_prepare_enable(bp->hclk);
5005 clk_prepare_enable(bp->tx_clk);
5006 clk_prepare_enable(bp->rx_clk);
5008 clk_prepare_enable(bp->tsu_clk);
5013 static const struct dev_pm_ops macb_pm_ops = {
5014 SET_SYSTEM_SLEEP_PM_OPS(macb_suspend, macb_resume)
5015 SET_RUNTIME_PM_OPS(macb_runtime_suspend, macb_runtime_resume, NULL)
5018 static struct platform_driver macb_driver = {
5019 .probe = macb_probe,
5020 .remove = macb_remove,
5023 .of_match_table = of_match_ptr(macb_dt_ids),
5028 module_platform_driver(macb_driver);
5030 MODULE_LICENSE("GPL");
5031 MODULE_DESCRIPTION("Cadence MACB/GEM Ethernet driver");
5032 MODULE_AUTHOR("Haavard Skinnemoen (Atmel)");
5033 MODULE_ALIAS("platform:macb");