1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * Atmel MACB Ethernet Controller driver
5 * Copyright (C) 2004-2006 Atmel Corporation
10 #include <linux/clk.h>
11 #include <linux/phylink.h>
12 #include <linux/ptp_clock_kernel.h>
13 #include <linux/net_tstamp.h>
14 #include <linux/interrupt.h>
16 #if defined(CONFIG_ARCH_DMA_ADDR_T_64BIT) || defined(CONFIG_MACB_USE_HWSTAMP)
20 #define MACB_GREGS_NBR 16
21 #define MACB_GREGS_VERSION 2
22 #define MACB_MAX_QUEUES 8
24 /* MACB register offsets */
25 #define MACB_NCR 0x0000 /* Network Control */
26 #define MACB_NCFGR 0x0004 /* Network Config */
27 #define MACB_NSR 0x0008 /* Network Status */
28 #define MACB_TAR 0x000c /* AT91RM9200 only */
29 #define MACB_TCR 0x0010 /* AT91RM9200 only */
30 #define MACB_TSR 0x0014 /* Transmit Status */
31 #define MACB_RBQP 0x0018 /* RX Q Base Address */
32 #define MACB_TBQP 0x001c /* TX Q Base Address */
33 #define MACB_RSR 0x0020 /* Receive Status */
34 #define MACB_ISR 0x0024 /* Interrupt Status */
35 #define MACB_IER 0x0028 /* Interrupt Enable */
36 #define MACB_IDR 0x002c /* Interrupt Disable */
37 #define MACB_IMR 0x0030 /* Interrupt Mask */
38 #define MACB_MAN 0x0034 /* PHY Maintenance */
39 #define MACB_PTR 0x0038
40 #define MACB_PFR 0x003c
41 #define MACB_FTO 0x0040
42 #define MACB_SCF 0x0044
43 #define MACB_MCF 0x0048
44 #define MACB_FRO 0x004c
45 #define MACB_FCSE 0x0050
46 #define MACB_ALE 0x0054
47 #define MACB_DTF 0x0058
48 #define MACB_LCOL 0x005c
49 #define MACB_EXCOL 0x0060
50 #define MACB_TUND 0x0064
51 #define MACB_CSE 0x0068
52 #define MACB_RRE 0x006c
53 #define MACB_ROVR 0x0070
54 #define MACB_RSE 0x0074
55 #define MACB_ELE 0x0078
56 #define MACB_RJA 0x007c
57 #define MACB_USF 0x0080
58 #define MACB_STE 0x0084
59 #define MACB_RLE 0x0088
60 #define MACB_TPF 0x008c
61 #define MACB_HRB 0x0090
62 #define MACB_HRT 0x0094
63 #define MACB_SA1B 0x0098
64 #define MACB_SA1T 0x009c
65 #define MACB_SA2B 0x00a0
66 #define MACB_SA2T 0x00a4
67 #define MACB_SA3B 0x00a8
68 #define MACB_SA3T 0x00ac
69 #define MACB_SA4B 0x00b0
70 #define MACB_SA4T 0x00b4
71 #define MACB_TID 0x00b8
72 #define MACB_TPQ 0x00bc
73 #define MACB_USRIO 0x00c0
74 #define MACB_WOL 0x00c4
75 #define MACB_MID 0x00fc
76 #define MACB_TBQPH 0x04C8
77 #define MACB_RBQPH 0x04D4
79 /* GEM register offsets. */
80 #define GEM_NCFGR 0x0004 /* Network Config */
81 #define GEM_USRIO 0x000c /* User IO */
82 #define GEM_DMACFG 0x0010 /* DMA Configuration */
83 #define GEM_JML 0x0048 /* Jumbo Max Length */
84 #define GEM_HRB 0x0080 /* Hash Bottom */
85 #define GEM_HRT 0x0084 /* Hash Top */
86 #define GEM_SA1B 0x0088 /* Specific1 Bottom */
87 #define GEM_SA1T 0x008C /* Specific1 Top */
88 #define GEM_SA2B 0x0090 /* Specific2 Bottom */
89 #define GEM_SA2T 0x0094 /* Specific2 Top */
90 #define GEM_SA3B 0x0098 /* Specific3 Bottom */
91 #define GEM_SA3T 0x009C /* Specific3 Top */
92 #define GEM_SA4B 0x00A0 /* Specific4 Bottom */
93 #define GEM_SA4T 0x00A4 /* Specific4 Top */
94 #define GEM_WOL 0x00b8 /* Wake on LAN */
95 #define GEM_EFTSH 0x00e8 /* PTP Event Frame Transmitted Seconds Register 47:32 */
96 #define GEM_EFRSH 0x00ec /* PTP Event Frame Received Seconds Register 47:32 */
97 #define GEM_PEFTSH 0x00f0 /* PTP Peer Event Frame Transmitted Seconds Register 47:32 */
98 #define GEM_PEFRSH 0x00f4 /* PTP Peer Event Frame Received Seconds Register 47:32 */
99 #define GEM_OTX 0x0100 /* Octets transmitted */
100 #define GEM_OCTTXL 0x0100 /* Octets transmitted [31:0] */
101 #define GEM_OCTTXH 0x0104 /* Octets transmitted [47:32] */
102 #define GEM_TXCNT 0x0108 /* Frames Transmitted counter */
103 #define GEM_TXBCCNT 0x010c /* Broadcast Frames counter */
104 #define GEM_TXMCCNT 0x0110 /* Multicast Frames counter */
105 #define GEM_TXPAUSECNT 0x0114 /* Pause Frames Transmitted Counter */
106 #define GEM_TX64CNT 0x0118 /* 64 byte Frames TX counter */
107 #define GEM_TX65CNT 0x011c /* 65-127 byte Frames TX counter */
108 #define GEM_TX128CNT 0x0120 /* 128-255 byte Frames TX counter */
109 #define GEM_TX256CNT 0x0124 /* 256-511 byte Frames TX counter */
110 #define GEM_TX512CNT 0x0128 /* 512-1023 byte Frames TX counter */
111 #define GEM_TX1024CNT 0x012c /* 1024-1518 byte Frames TX counter */
112 #define GEM_TX1519CNT 0x0130 /* 1519+ byte Frames TX counter */
113 #define GEM_TXURUNCNT 0x0134 /* TX under run error counter */
114 #define GEM_SNGLCOLLCNT 0x0138 /* Single Collision Frame Counter */
115 #define GEM_MULTICOLLCNT 0x013c /* Multiple Collision Frame Counter */
116 #define GEM_EXCESSCOLLCNT 0x0140 /* Excessive Collision Frame Counter */
117 #define GEM_LATECOLLCNT 0x0144 /* Late Collision Frame Counter */
118 #define GEM_TXDEFERCNT 0x0148 /* Deferred Transmission Frame Counter */
119 #define GEM_TXCSENSECNT 0x014c /* Carrier Sense Error Counter */
120 #define GEM_ORX 0x0150 /* Octets received */
121 #define GEM_OCTRXL 0x0150 /* Octets received [31:0] */
122 #define GEM_OCTRXH 0x0154 /* Octets received [47:32] */
123 #define GEM_RXCNT 0x0158 /* Frames Received Counter */
124 #define GEM_RXBROADCNT 0x015c /* Broadcast Frames Received Counter */
125 #define GEM_RXMULTICNT 0x0160 /* Multicast Frames Received Counter */
126 #define GEM_RXPAUSECNT 0x0164 /* Pause Frames Received Counter */
127 #define GEM_RX64CNT 0x0168 /* 64 byte Frames RX Counter */
128 #define GEM_RX65CNT 0x016c /* 65-127 byte Frames RX Counter */
129 #define GEM_RX128CNT 0x0170 /* 128-255 byte Frames RX Counter */
130 #define GEM_RX256CNT 0x0174 /* 256-511 byte Frames RX Counter */
131 #define GEM_RX512CNT 0x0178 /* 512-1023 byte Frames RX Counter */
132 #define GEM_RX1024CNT 0x017c /* 1024-1518 byte Frames RX Counter */
133 #define GEM_RX1519CNT 0x0180 /* 1519+ byte Frames RX Counter */
134 #define GEM_RXUNDRCNT 0x0184 /* Undersize Frames Received Counter */
135 #define GEM_RXOVRCNT 0x0188 /* Oversize Frames Received Counter */
136 #define GEM_RXJABCNT 0x018c /* Jabbers Received Counter */
137 #define GEM_RXFCSCNT 0x0190 /* Frame Check Sequence Error Counter */
138 #define GEM_RXLENGTHCNT 0x0194 /* Length Field Error Counter */
139 #define GEM_RXSYMBCNT 0x0198 /* Symbol Error Counter */
140 #define GEM_RXALIGNCNT 0x019c /* Alignment Error Counter */
141 #define GEM_RXRESERRCNT 0x01a0 /* Receive Resource Error Counter */
142 #define GEM_RXORCNT 0x01a4 /* Receive Overrun Counter */
143 #define GEM_RXIPCCNT 0x01a8 /* IP header Checksum Error Counter */
144 #define GEM_RXTCPCCNT 0x01ac /* TCP Checksum Error Counter */
145 #define GEM_RXUDPCCNT 0x01b0 /* UDP Checksum Error Counter */
146 #define GEM_TISUBN 0x01bc /* 1588 Timer Increment Sub-ns */
147 #define GEM_TSH 0x01c0 /* 1588 Timer Seconds High */
148 #define GEM_TSL 0x01d0 /* 1588 Timer Seconds Low */
149 #define GEM_TN 0x01d4 /* 1588 Timer Nanoseconds */
150 #define GEM_TA 0x01d8 /* 1588 Timer Adjust */
151 #define GEM_TI 0x01dc /* 1588 Timer Increment */
152 #define GEM_EFTSL 0x01e0 /* PTP Event Frame Tx Seconds Low */
153 #define GEM_EFTN 0x01e4 /* PTP Event Frame Tx Nanoseconds */
154 #define GEM_EFRSL 0x01e8 /* PTP Event Frame Rx Seconds Low */
155 #define GEM_EFRN 0x01ec /* PTP Event Frame Rx Nanoseconds */
156 #define GEM_PEFTSL 0x01f0 /* PTP Peer Event Frame Tx Secs Low */
157 #define GEM_PEFTN 0x01f4 /* PTP Peer Event Frame Tx Ns */
158 #define GEM_PEFRSL 0x01f8 /* PTP Peer Event Frame Rx Sec Low */
159 #define GEM_PEFRN 0x01fc /* PTP Peer Event Frame Rx Ns */
160 #define GEM_DCFG1 0x0280 /* Design Config 1 */
161 #define GEM_DCFG2 0x0284 /* Design Config 2 */
162 #define GEM_DCFG3 0x0288 /* Design Config 3 */
163 #define GEM_DCFG4 0x028c /* Design Config 4 */
164 #define GEM_DCFG5 0x0290 /* Design Config 5 */
165 #define GEM_DCFG6 0x0294 /* Design Config 6 */
166 #define GEM_DCFG7 0x0298 /* Design Config 7 */
167 #define GEM_DCFG8 0x029C /* Design Config 8 */
168 #define GEM_DCFG10 0x02A4 /* Design Config 10 */
170 #define GEM_TXBDCTRL 0x04cc /* TX Buffer Descriptor control register */
171 #define GEM_RXBDCTRL 0x04d0 /* RX Buffer Descriptor control register */
173 /* Screener Type 2 match registers */
174 #define GEM_SCRT2 0x540
176 /* EtherType registers */
177 #define GEM_ETHT 0x06E0
179 /* Type 2 compare registers */
180 #define GEM_T2CMPW0 0x0700
181 #define GEM_T2CMPW1 0x0704
182 #define T2CMP_OFST(t2idx) (t2idx * 2)
184 /* type 2 compare registers
185 * each location requires 3 compare regs
187 #define GEM_IP4SRC_CMP(idx) (idx * 3)
188 #define GEM_IP4DST_CMP(idx) (idx * 3 + 1)
189 #define GEM_PORT_CMP(idx) (idx * 3 + 2)
191 /* Which screening type 2 EtherType register will be used (0 - 7) */
194 #define GEM_ISR(hw_q) (0x0400 + ((hw_q) << 2))
195 #define GEM_TBQP(hw_q) (0x0440 + ((hw_q) << 2))
196 #define GEM_TBQPH(hw_q) (0x04C8)
197 #define GEM_RBQP(hw_q) (0x0480 + ((hw_q) << 2))
198 #define GEM_RBQS(hw_q) (0x04A0 + ((hw_q) << 2))
199 #define GEM_RBQPH(hw_q) (0x04D4)
200 #define GEM_IER(hw_q) (0x0600 + ((hw_q) << 2))
201 #define GEM_IDR(hw_q) (0x0620 + ((hw_q) << 2))
202 #define GEM_IMR(hw_q) (0x0640 + ((hw_q) << 2))
204 /* Bitfields in NCR */
205 #define MACB_LB_OFFSET 0 /* reserved */
206 #define MACB_LB_SIZE 1
207 #define MACB_LLB_OFFSET 1 /* Loop back local */
208 #define MACB_LLB_SIZE 1
209 #define MACB_RE_OFFSET 2 /* Receive enable */
210 #define MACB_RE_SIZE 1
211 #define MACB_TE_OFFSET 3 /* Transmit enable */
212 #define MACB_TE_SIZE 1
213 #define MACB_MPE_OFFSET 4 /* Management port enable */
214 #define MACB_MPE_SIZE 1
215 #define MACB_CLRSTAT_OFFSET 5 /* Clear stats regs */
216 #define MACB_CLRSTAT_SIZE 1
217 #define MACB_INCSTAT_OFFSET 6 /* Incremental stats regs */
218 #define MACB_INCSTAT_SIZE 1
219 #define MACB_WESTAT_OFFSET 7 /* Write enable stats regs */
220 #define MACB_WESTAT_SIZE 1
221 #define MACB_BP_OFFSET 8 /* Back pressure */
222 #define MACB_BP_SIZE 1
223 #define MACB_TSTART_OFFSET 9 /* Start transmission */
224 #define MACB_TSTART_SIZE 1
225 #define MACB_THALT_OFFSET 10 /* Transmit halt */
226 #define MACB_THALT_SIZE 1
227 #define MACB_NCR_TPF_OFFSET 11 /* Transmit pause frame */
228 #define MACB_NCR_TPF_SIZE 1
229 #define MACB_TZQ_OFFSET 12 /* Transmit zero quantum pause frame */
230 #define MACB_TZQ_SIZE 1
231 #define MACB_SRTSM_OFFSET 15
232 #define MACB_OSSMODE_OFFSET 24 /* Enable One Step Synchro Mode */
233 #define MACB_OSSMODE_SIZE 1
235 /* Bitfields in NCFGR */
236 #define MACB_SPD_OFFSET 0 /* Speed */
237 #define MACB_SPD_SIZE 1
238 #define MACB_FD_OFFSET 1 /* Full duplex */
239 #define MACB_FD_SIZE 1
240 #define MACB_BIT_RATE_OFFSET 2 /* Discard non-VLAN frames */
241 #define MACB_BIT_RATE_SIZE 1
242 #define MACB_JFRAME_OFFSET 3 /* reserved */
243 #define MACB_JFRAME_SIZE 1
244 #define MACB_CAF_OFFSET 4 /* Copy all frames */
245 #define MACB_CAF_SIZE 1
246 #define MACB_NBC_OFFSET 5 /* No broadcast */
247 #define MACB_NBC_SIZE 1
248 #define MACB_NCFGR_MTI_OFFSET 6 /* Multicast hash enable */
249 #define MACB_NCFGR_MTI_SIZE 1
250 #define MACB_UNI_OFFSET 7 /* Unicast hash enable */
251 #define MACB_UNI_SIZE 1
252 #define MACB_BIG_OFFSET 8 /* Receive 1536 byte frames */
253 #define MACB_BIG_SIZE 1
254 #define MACB_EAE_OFFSET 9 /* External address match enable */
255 #define MACB_EAE_SIZE 1
256 #define MACB_CLK_OFFSET 10
257 #define MACB_CLK_SIZE 2
258 #define MACB_RTY_OFFSET 12 /* Retry test */
259 #define MACB_RTY_SIZE 1
260 #define MACB_PAE_OFFSET 13 /* Pause enable */
261 #define MACB_PAE_SIZE 1
262 #define MACB_RM9200_RMII_OFFSET 13 /* AT91RM9200 only */
263 #define MACB_RM9200_RMII_SIZE 1 /* AT91RM9200 only */
264 #define MACB_RBOF_OFFSET 14 /* Receive buffer offset */
265 #define MACB_RBOF_SIZE 2
266 #define MACB_RLCE_OFFSET 16 /* Length field error frame discard */
267 #define MACB_RLCE_SIZE 1
268 #define MACB_DRFCS_OFFSET 17 /* FCS remove */
269 #define MACB_DRFCS_SIZE 1
270 #define MACB_EFRHD_OFFSET 18
271 #define MACB_EFRHD_SIZE 1
272 #define MACB_IRXFCS_OFFSET 19
273 #define MACB_IRXFCS_SIZE 1
275 /* GEM specific NCFGR bitfields. */
276 #define GEM_GBE_OFFSET 10 /* Gigabit mode enable */
277 #define GEM_GBE_SIZE 1
278 #define GEM_PCSSEL_OFFSET 11
279 #define GEM_PCSSEL_SIZE 1
280 #define GEM_CLK_OFFSET 18 /* MDC clock division */
281 #define GEM_CLK_SIZE 3
282 #define GEM_DBW_OFFSET 21 /* Data bus width */
283 #define GEM_DBW_SIZE 2
284 #define GEM_RXCOEN_OFFSET 24
285 #define GEM_RXCOEN_SIZE 1
286 #define GEM_SGMIIEN_OFFSET 27
287 #define GEM_SGMIIEN_SIZE 1
290 /* Constants for data bus width. */
291 #define GEM_DBW32 0 /* 32 bit AMBA AHB data bus width */
292 #define GEM_DBW64 1 /* 64 bit AMBA AHB data bus width */
293 #define GEM_DBW128 2 /* 128 bit AMBA AHB data bus width */
295 /* Bitfields in DMACFG. */
296 #define GEM_FBLDO_OFFSET 0 /* fixed burst length for DMA */
297 #define GEM_FBLDO_SIZE 5
298 #define GEM_ENDIA_DESC_OFFSET 6 /* endian swap mode for management descriptor access */
299 #define GEM_ENDIA_DESC_SIZE 1
300 #define GEM_ENDIA_PKT_OFFSET 7 /* endian swap mode for packet data access */
301 #define GEM_ENDIA_PKT_SIZE 1
302 #define GEM_RXBMS_OFFSET 8 /* RX packet buffer memory size select */
303 #define GEM_RXBMS_SIZE 2
304 #define GEM_TXPBMS_OFFSET 10 /* TX packet buffer memory size select */
305 #define GEM_TXPBMS_SIZE 1
306 #define GEM_TXCOEN_OFFSET 11 /* TX IP/TCP/UDP checksum gen offload */
307 #define GEM_TXCOEN_SIZE 1
308 #define GEM_RXBS_OFFSET 16 /* DMA receive buffer size */
309 #define GEM_RXBS_SIZE 8
310 #define GEM_DDRP_OFFSET 24 /* disc_when_no_ahb */
311 #define GEM_DDRP_SIZE 1
312 #define GEM_RXEXT_OFFSET 28 /* RX extended Buffer Descriptor mode */
313 #define GEM_RXEXT_SIZE 1
314 #define GEM_TXEXT_OFFSET 29 /* TX extended Buffer Descriptor mode */
315 #define GEM_TXEXT_SIZE 1
316 #define GEM_ADDR64_OFFSET 30 /* Address bus width - 64b or 32b */
317 #define GEM_ADDR64_SIZE 1
320 /* Bitfields in NSR */
321 #define MACB_NSR_LINK_OFFSET 0 /* pcs_link_state */
322 #define MACB_NSR_LINK_SIZE 1
323 #define MACB_MDIO_OFFSET 1 /* status of the mdio_in pin */
324 #define MACB_MDIO_SIZE 1
325 #define MACB_IDLE_OFFSET 2 /* The PHY management logic is idle */
326 #define MACB_IDLE_SIZE 1
328 /* Bitfields in TSR */
329 #define MACB_UBR_OFFSET 0 /* Used bit read */
330 #define MACB_UBR_SIZE 1
331 #define MACB_COL_OFFSET 1 /* Collision occurred */
332 #define MACB_COL_SIZE 1
333 #define MACB_TSR_RLE_OFFSET 2 /* Retry limit exceeded */
334 #define MACB_TSR_RLE_SIZE 1
335 #define MACB_TGO_OFFSET 3 /* Transmit go */
336 #define MACB_TGO_SIZE 1
337 #define MACB_BEX_OFFSET 4 /* TX frame corruption due to AHB error */
338 #define MACB_BEX_SIZE 1
339 #define MACB_RM9200_BNQ_OFFSET 4 /* AT91RM9200 only */
340 #define MACB_RM9200_BNQ_SIZE 1 /* AT91RM9200 only */
341 #define MACB_COMP_OFFSET 5 /* Trnasmit complete */
342 #define MACB_COMP_SIZE 1
343 #define MACB_UND_OFFSET 6 /* Trnasmit under run */
344 #define MACB_UND_SIZE 1
346 /* Bitfields in RSR */
347 #define MACB_BNA_OFFSET 0 /* Buffer not available */
348 #define MACB_BNA_SIZE 1
349 #define MACB_REC_OFFSET 1 /* Frame received */
350 #define MACB_REC_SIZE 1
351 #define MACB_OVR_OFFSET 2 /* Receive overrun */
352 #define MACB_OVR_SIZE 1
354 /* Bitfields in ISR/IER/IDR/IMR */
355 #define MACB_MFD_OFFSET 0 /* Management frame sent */
356 #define MACB_MFD_SIZE 1
357 #define MACB_RCOMP_OFFSET 1 /* Receive complete */
358 #define MACB_RCOMP_SIZE 1
359 #define MACB_RXUBR_OFFSET 2 /* RX used bit read */
360 #define MACB_RXUBR_SIZE 1
361 #define MACB_TXUBR_OFFSET 3 /* TX used bit read */
362 #define MACB_TXUBR_SIZE 1
363 #define MACB_ISR_TUND_OFFSET 4 /* Enable TX buffer under run interrupt */
364 #define MACB_ISR_TUND_SIZE 1
365 #define MACB_ISR_RLE_OFFSET 5 /* EN retry exceeded/late coll interrupt */
366 #define MACB_ISR_RLE_SIZE 1
367 #define MACB_TXERR_OFFSET 6 /* EN TX frame corrupt from error interrupt */
368 #define MACB_TXERR_SIZE 1
369 #define MACB_RM9200_TBRE_OFFSET 6 /* EN may send new frame interrupt (RM9200) */
370 #define MACB_RM9200_TBRE_SIZE 1
371 #define MACB_TCOMP_OFFSET 7 /* Enable transmit complete interrupt */
372 #define MACB_TCOMP_SIZE 1
373 #define MACB_ISR_LINK_OFFSET 9 /* Enable link change interrupt */
374 #define MACB_ISR_LINK_SIZE 1
375 #define MACB_ISR_ROVR_OFFSET 10 /* Enable receive overrun interrupt */
376 #define MACB_ISR_ROVR_SIZE 1
377 #define MACB_HRESP_OFFSET 11 /* Enable hrsep not OK interrupt */
378 #define MACB_HRESP_SIZE 1
379 #define MACB_PFR_OFFSET 12 /* Enable pause frame w/ quantum interrupt */
380 #define MACB_PFR_SIZE 1
381 #define MACB_PTZ_OFFSET 13 /* Enable pause time zero interrupt */
382 #define MACB_PTZ_SIZE 1
383 #define MACB_WOL_OFFSET 14 /* Enable wake-on-lan interrupt */
384 #define MACB_WOL_SIZE 1
385 #define MACB_DRQFR_OFFSET 18 /* PTP Delay Request Frame Received */
386 #define MACB_DRQFR_SIZE 1
387 #define MACB_SFR_OFFSET 19 /* PTP Sync Frame Received */
388 #define MACB_SFR_SIZE 1
389 #define MACB_DRQFT_OFFSET 20 /* PTP Delay Request Frame Transmitted */
390 #define MACB_DRQFT_SIZE 1
391 #define MACB_SFT_OFFSET 21 /* PTP Sync Frame Transmitted */
392 #define MACB_SFT_SIZE 1
393 #define MACB_PDRQFR_OFFSET 22 /* PDelay Request Frame Received */
394 #define MACB_PDRQFR_SIZE 1
395 #define MACB_PDRSFR_OFFSET 23 /* PDelay Response Frame Received */
396 #define MACB_PDRSFR_SIZE 1
397 #define MACB_PDRQFT_OFFSET 24 /* PDelay Request Frame Transmitted */
398 #define MACB_PDRQFT_SIZE 1
399 #define MACB_PDRSFT_OFFSET 25 /* PDelay Response Frame Transmitted */
400 #define MACB_PDRSFT_SIZE 1
401 #define MACB_SRI_OFFSET 26 /* TSU Seconds Register Increment */
402 #define MACB_SRI_SIZE 1
403 #define GEM_WOL_OFFSET 28 /* Enable wake-on-lan interrupt */
404 #define GEM_WOL_SIZE 1
406 /* Timer increment fields */
407 #define MACB_TI_CNS_OFFSET 0
408 #define MACB_TI_CNS_SIZE 8
409 #define MACB_TI_ACNS_OFFSET 8
410 #define MACB_TI_ACNS_SIZE 8
411 #define MACB_TI_NIT_OFFSET 16
412 #define MACB_TI_NIT_SIZE 8
414 /* Bitfields in MAN */
415 #define MACB_DATA_OFFSET 0 /* data */
416 #define MACB_DATA_SIZE 16
417 #define MACB_CODE_OFFSET 16 /* Must be written to 10 */
418 #define MACB_CODE_SIZE 2
419 #define MACB_REGA_OFFSET 18 /* Register address */
420 #define MACB_REGA_SIZE 5
421 #define MACB_PHYA_OFFSET 23 /* PHY address */
422 #define MACB_PHYA_SIZE 5
423 #define MACB_RW_OFFSET 28 /* Operation. 10 is read. 01 is write. */
424 #define MACB_RW_SIZE 2
425 #define MACB_SOF_OFFSET 30 /* Must be written to 1 for Clause 22 */
426 #define MACB_SOF_SIZE 2
428 /* Bitfields in USRIO (AVR32) */
429 #define MACB_MII_OFFSET 0
430 #define MACB_MII_SIZE 1
431 #define MACB_EAM_OFFSET 1
432 #define MACB_EAM_SIZE 1
433 #define MACB_TX_PAUSE_OFFSET 2
434 #define MACB_TX_PAUSE_SIZE 1
435 #define MACB_TX_PAUSE_ZERO_OFFSET 3
436 #define MACB_TX_PAUSE_ZERO_SIZE 1
438 /* Bitfields in USRIO (AT91) */
439 #define MACB_RMII_OFFSET 0
440 #define MACB_RMII_SIZE 1
441 #define GEM_RGMII_OFFSET 0 /* GEM gigabit mode */
442 #define GEM_RGMII_SIZE 1
443 #define MACB_CLKEN_OFFSET 1
444 #define MACB_CLKEN_SIZE 1
446 /* Bitfields in WOL */
447 #define MACB_IP_OFFSET 0
448 #define MACB_IP_SIZE 16
449 #define MACB_MAG_OFFSET 16
450 #define MACB_MAG_SIZE 1
451 #define MACB_ARP_OFFSET 17
452 #define MACB_ARP_SIZE 1
453 #define MACB_SA1_OFFSET 18
454 #define MACB_SA1_SIZE 1
455 #define MACB_WOL_MTI_OFFSET 19
456 #define MACB_WOL_MTI_SIZE 1
458 /* Bitfields in MID */
459 #define MACB_IDNUM_OFFSET 16
460 #define MACB_IDNUM_SIZE 12
461 #define MACB_REV_OFFSET 0
462 #define MACB_REV_SIZE 16
464 /* Bitfields in DCFG1. */
465 #define GEM_IRQCOR_OFFSET 23
466 #define GEM_IRQCOR_SIZE 1
467 #define GEM_DBWDEF_OFFSET 25
468 #define GEM_DBWDEF_SIZE 3
470 /* Bitfields in DCFG2. */
471 #define GEM_RX_PKT_BUFF_OFFSET 20
472 #define GEM_RX_PKT_BUFF_SIZE 1
473 #define GEM_TX_PKT_BUFF_OFFSET 21
474 #define GEM_TX_PKT_BUFF_SIZE 1
477 /* Bitfields in DCFG5. */
478 #define GEM_TSU_OFFSET 8
479 #define GEM_TSU_SIZE 1
481 /* Bitfields in DCFG6. */
482 #define GEM_PBUF_LSO_OFFSET 27
483 #define GEM_PBUF_LSO_SIZE 1
484 #define GEM_DAW64_OFFSET 23
485 #define GEM_DAW64_SIZE 1
487 /* Bitfields in DCFG8. */
488 #define GEM_T1SCR_OFFSET 24
489 #define GEM_T1SCR_SIZE 8
490 #define GEM_T2SCR_OFFSET 16
491 #define GEM_T2SCR_SIZE 8
492 #define GEM_SCR2ETH_OFFSET 8
493 #define GEM_SCR2ETH_SIZE 8
494 #define GEM_SCR2CMP_OFFSET 0
495 #define GEM_SCR2CMP_SIZE 8
497 /* Bitfields in DCFG10 */
498 #define GEM_TXBD_RDBUFF_OFFSET 12
499 #define GEM_TXBD_RDBUFF_SIZE 4
500 #define GEM_RXBD_RDBUFF_OFFSET 8
501 #define GEM_RXBD_RDBUFF_SIZE 4
503 /* Bitfields in TISUBN */
504 #define GEM_SUBNSINCR_OFFSET 0
505 #define GEM_SUBNSINCRL_OFFSET 24
506 #define GEM_SUBNSINCRL_SIZE 8
507 #define GEM_SUBNSINCRH_OFFSET 0
508 #define GEM_SUBNSINCRH_SIZE 16
509 #define GEM_SUBNSINCR_SIZE 24
511 /* Bitfields in TI */
512 #define GEM_NSINCR_OFFSET 0
513 #define GEM_NSINCR_SIZE 8
515 /* Bitfields in TSH */
516 #define GEM_TSH_OFFSET 0 /* TSU timer value (s). MSB [47:32] of seconds timer count */
517 #define GEM_TSH_SIZE 16
519 /* Bitfields in TSL */
520 #define GEM_TSL_OFFSET 0 /* TSU timer value (s). LSB [31:0] of seconds timer count */
521 #define GEM_TSL_SIZE 32
523 /* Bitfields in TN */
524 #define GEM_TN_OFFSET 0 /* TSU timer value (ns) */
525 #define GEM_TN_SIZE 30
527 /* Bitfields in TXBDCTRL */
528 #define GEM_TXTSMODE_OFFSET 4 /* TX Descriptor Timestamp Insertion mode */
529 #define GEM_TXTSMODE_SIZE 2
531 /* Bitfields in RXBDCTRL */
532 #define GEM_RXTSMODE_OFFSET 4 /* RX Descriptor Timestamp Insertion mode */
533 #define GEM_RXTSMODE_SIZE 2
535 /* Bitfields in SCRT2 */
536 #define GEM_QUEUE_OFFSET 0 /* Queue Number */
537 #define GEM_QUEUE_SIZE 4
538 #define GEM_VLANPR_OFFSET 4 /* VLAN Priority */
539 #define GEM_VLANPR_SIZE 3
540 #define GEM_VLANEN_OFFSET 8 /* VLAN Enable */
541 #define GEM_VLANEN_SIZE 1
542 #define GEM_ETHT2IDX_OFFSET 9 /* Index to screener type 2 EtherType register */
543 #define GEM_ETHT2IDX_SIZE 3
544 #define GEM_ETHTEN_OFFSET 12 /* EtherType Enable */
545 #define GEM_ETHTEN_SIZE 1
546 #define GEM_CMPA_OFFSET 13 /* Compare A - Index to screener type 2 Compare register */
547 #define GEM_CMPA_SIZE 5
548 #define GEM_CMPAEN_OFFSET 18 /* Compare A Enable */
549 #define GEM_CMPAEN_SIZE 1
550 #define GEM_CMPB_OFFSET 19 /* Compare B - Index to screener type 2 Compare register */
551 #define GEM_CMPB_SIZE 5
552 #define GEM_CMPBEN_OFFSET 24 /* Compare B Enable */
553 #define GEM_CMPBEN_SIZE 1
554 #define GEM_CMPC_OFFSET 25 /* Compare C - Index to screener type 2 Compare register */
555 #define GEM_CMPC_SIZE 5
556 #define GEM_CMPCEN_OFFSET 30 /* Compare C Enable */
557 #define GEM_CMPCEN_SIZE 1
559 /* Bitfields in ETHT */
560 #define GEM_ETHTCMP_OFFSET 0 /* EtherType compare value */
561 #define GEM_ETHTCMP_SIZE 16
563 /* Bitfields in T2CMPW0 */
564 #define GEM_T2CMP_OFFSET 16 /* 0xFFFF0000 compare value */
565 #define GEM_T2CMP_SIZE 16
566 #define GEM_T2MASK_OFFSET 0 /* 0x0000FFFF compare value or mask */
567 #define GEM_T2MASK_SIZE 16
569 /* Bitfields in T2CMPW1 */
570 #define GEM_T2DISMSK_OFFSET 9 /* disable mask */
571 #define GEM_T2DISMSK_SIZE 1
572 #define GEM_T2CMPOFST_OFFSET 7 /* compare offset */
573 #define GEM_T2CMPOFST_SIZE 2
574 #define GEM_T2OFST_OFFSET 0 /* offset value */
575 #define GEM_T2OFST_SIZE 7
577 /* Offset for screener type 2 compare values (T2CMPOFST).
578 * Note the offset is applied after the specified point,
579 * e.g. GEM_T2COMPOFST_ETYPE denotes the EtherType field, so an offset
580 * of 12 bytes from this would be the source IP address in an IP header
582 #define GEM_T2COMPOFST_SOF 0
583 #define GEM_T2COMPOFST_ETYPE 1
584 #define GEM_T2COMPOFST_IPHDR 2
585 #define GEM_T2COMPOFST_TCPUDP 3
587 /* offset from EtherType to IP address */
588 #define ETYPE_SRCIP_OFFSET 12
589 #define ETYPE_DSTIP_OFFSET 16
591 /* offset from IP header to port */
592 #define IPHDR_SRCPORT_OFFSET 0
593 #define IPHDR_DSTPORT_OFFSET 2
595 /* Transmit DMA buffer descriptor Word 1 */
596 #define GEM_DMA_TXVALID_OFFSET 23 /* timestamp has been captured in the Buffer Descriptor */
597 #define GEM_DMA_TXVALID_SIZE 1
599 /* Receive DMA buffer descriptor Word 0 */
600 #define GEM_DMA_RXVALID_OFFSET 2 /* indicates a valid timestamp in the Buffer Descriptor */
601 #define GEM_DMA_RXVALID_SIZE 1
603 /* DMA buffer descriptor Word 2 (32 bit addressing) or Word 4 (64 bit addressing) */
604 #define GEM_DMA_SECL_OFFSET 30 /* Timestamp seconds[1:0] */
605 #define GEM_DMA_SECL_SIZE 2
606 #define GEM_DMA_NSEC_OFFSET 0 /* Timestamp nanosecs [29:0] */
607 #define GEM_DMA_NSEC_SIZE 30
609 /* DMA buffer descriptor Word 3 (32 bit addressing) or Word 5 (64 bit addressing) */
611 /* New hardware supports 12 bit precision of timestamp in DMA buffer descriptor.
612 * Old hardware supports only 6 bit precision but it is enough for PTP.
613 * Less accuracy is used always instead of checking hardware version.
615 #define GEM_DMA_SECH_OFFSET 0 /* Timestamp seconds[5:2] */
616 #define GEM_DMA_SECH_SIZE 4
617 #define GEM_DMA_SEC_WIDTH (GEM_DMA_SECH_SIZE + GEM_DMA_SECL_SIZE)
618 #define GEM_DMA_SEC_TOP (1 << GEM_DMA_SEC_WIDTH)
619 #define GEM_DMA_SEC_MASK (GEM_DMA_SEC_TOP - 1)
621 /* Bitfields in ADJ */
622 #define GEM_ADDSUB_OFFSET 31
623 #define GEM_ADDSUB_SIZE 1
624 /* Constants for CLK */
625 #define MACB_CLK_DIV8 0
626 #define MACB_CLK_DIV16 1
627 #define MACB_CLK_DIV32 2
628 #define MACB_CLK_DIV64 3
630 /* GEM specific constants for CLK. */
631 #define GEM_CLK_DIV8 0
632 #define GEM_CLK_DIV16 1
633 #define GEM_CLK_DIV32 2
634 #define GEM_CLK_DIV48 3
635 #define GEM_CLK_DIV64 4
636 #define GEM_CLK_DIV96 5
638 /* Constants for MAN register */
639 #define MACB_MAN_C22_SOF 1
640 #define MACB_MAN_C22_WRITE 1
641 #define MACB_MAN_C22_READ 2
642 #define MACB_MAN_C22_CODE 2
644 #define MACB_MAN_C45_SOF 0
645 #define MACB_MAN_C45_ADDR 0
646 #define MACB_MAN_C45_WRITE 1
647 #define MACB_MAN_C45_POST_READ_INCR 2
648 #define MACB_MAN_C45_READ 3
649 #define MACB_MAN_C45_CODE 2
651 /* Capability mask bits */
652 #define MACB_CAPS_ISR_CLEAR_ON_WRITE 0x00000001
653 #define MACB_CAPS_USRIO_HAS_CLKEN 0x00000002
654 #define MACB_CAPS_USRIO_DEFAULT_IS_MII_GMII 0x00000004
655 #define MACB_CAPS_NO_GIGABIT_HALF 0x00000008
656 #define MACB_CAPS_USRIO_DISABLED 0x00000010
657 #define MACB_CAPS_JUMBO 0x00000020
658 #define MACB_CAPS_GEM_HAS_PTP 0x00000040
659 #define MACB_CAPS_BD_RD_PREFETCH 0x00000080
660 #define MACB_CAPS_NEEDS_RSTONUBR 0x00000100
661 #define MACB_CAPS_MACB_IS_EMAC 0x08000000
662 #define MACB_CAPS_FIFO_MODE 0x10000000
663 #define MACB_CAPS_GIGABIT_MODE_AVAILABLE 0x20000000
664 #define MACB_CAPS_SG_DISABLED 0x40000000
665 #define MACB_CAPS_MACB_IS_GEM 0x80000000
668 #define MACB_LSO_UFO_ENABLE 0x01
669 #define MACB_LSO_TSO_ENABLE 0x02
671 /* Bit manipulation macros */
672 #define MACB_BIT(name) \
673 (1 << MACB_##name##_OFFSET)
674 #define MACB_BF(name,value) \
675 (((value) & ((1 << MACB_##name##_SIZE) - 1)) \
676 << MACB_##name##_OFFSET)
677 #define MACB_BFEXT(name,value)\
678 (((value) >> MACB_##name##_OFFSET) \
679 & ((1 << MACB_##name##_SIZE) - 1))
680 #define MACB_BFINS(name,value,old) \
681 (((old) & ~(((1 << MACB_##name##_SIZE) - 1) \
682 << MACB_##name##_OFFSET)) \
683 | MACB_BF(name,value))
685 #define GEM_BIT(name) \
686 (1 << GEM_##name##_OFFSET)
687 #define GEM_BF(name, value) \
688 (((value) & ((1 << GEM_##name##_SIZE) - 1)) \
689 << GEM_##name##_OFFSET)
690 #define GEM_BFEXT(name, value)\
691 (((value) >> GEM_##name##_OFFSET) \
692 & ((1 << GEM_##name##_SIZE) - 1))
693 #define GEM_BFINS(name, value, old) \
694 (((old) & ~(((1 << GEM_##name##_SIZE) - 1) \
695 << GEM_##name##_OFFSET)) \
696 | GEM_BF(name, value))
698 /* Register access macros */
699 #define macb_readl(port, reg) (port)->macb_reg_readl((port), MACB_##reg)
700 #define macb_writel(port, reg, value) (port)->macb_reg_writel((port), MACB_##reg, (value))
701 #define gem_readl(port, reg) (port)->macb_reg_readl((port), GEM_##reg)
702 #define gem_writel(port, reg, value) (port)->macb_reg_writel((port), GEM_##reg, (value))
703 #define queue_readl(queue, reg) (queue)->bp->macb_reg_readl((queue)->bp, (queue)->reg)
704 #define queue_writel(queue, reg, value) (queue)->bp->macb_reg_writel((queue)->bp, (queue)->reg, (value))
705 #define gem_readl_n(port, reg, idx) (port)->macb_reg_readl((port), GEM_##reg + idx * 4)
706 #define gem_writel_n(port, reg, idx, value) (port)->macb_reg_writel((port), GEM_##reg + idx * 4, (value))
708 #define PTP_TS_BUFFER_SIZE 128 /* must be power of 2 */
710 /* Conditional GEM/MACB macros. These perform the operation to the correct
711 * register dependent on whether the device is a GEM or a MACB. For registers
712 * and bitfields that are common across both devices, use macb_{read,write}l
713 * to avoid the cost of the conditional.
715 #define macb_or_gem_writel(__bp, __reg, __value) \
717 if (macb_is_gem((__bp))) \
718 gem_writel((__bp), __reg, __value); \
720 macb_writel((__bp), __reg, __value); \
723 #define macb_or_gem_readl(__bp, __reg) \
726 if (macb_is_gem((__bp))) \
727 __v = gem_readl((__bp), __reg); \
729 __v = macb_readl((__bp), __reg); \
733 #define MACB_READ_NSR(bp) macb_readl(bp, NSR)
735 /* struct macb_dma_desc - Hardware DMA descriptor
736 * @addr: DMA address of data buffer
737 * @ctrl: Control and status bits
739 struct macb_dma_desc {
745 #define HW_DMA_CAP_32B 0
746 #define HW_DMA_CAP_64B (1 << 0)
747 #define HW_DMA_CAP_PTP (1 << 1)
748 #define HW_DMA_CAP_64B_PTP (HW_DMA_CAP_64B | HW_DMA_CAP_PTP)
750 struct macb_dma_desc_64 {
755 struct macb_dma_desc_ptp {
762 struct macb_dma_desc_ptp desc_ptp;
766 /* DMA descriptor bitfields */
767 #define MACB_RX_USED_OFFSET 0
768 #define MACB_RX_USED_SIZE 1
769 #define MACB_RX_WRAP_OFFSET 1
770 #define MACB_RX_WRAP_SIZE 1
771 #define MACB_RX_WADDR_OFFSET 2
772 #define MACB_RX_WADDR_SIZE 30
774 #define MACB_RX_FRMLEN_OFFSET 0
775 #define MACB_RX_FRMLEN_SIZE 12
776 #define MACB_RX_OFFSET_OFFSET 12
777 #define MACB_RX_OFFSET_SIZE 2
778 #define MACB_RX_SOF_OFFSET 14
779 #define MACB_RX_SOF_SIZE 1
780 #define MACB_RX_EOF_OFFSET 15
781 #define MACB_RX_EOF_SIZE 1
782 #define MACB_RX_CFI_OFFSET 16
783 #define MACB_RX_CFI_SIZE 1
784 #define MACB_RX_VLAN_PRI_OFFSET 17
785 #define MACB_RX_VLAN_PRI_SIZE 3
786 #define MACB_RX_PRI_TAG_OFFSET 20
787 #define MACB_RX_PRI_TAG_SIZE 1
788 #define MACB_RX_VLAN_TAG_OFFSET 21
789 #define MACB_RX_VLAN_TAG_SIZE 1
790 #define MACB_RX_TYPEID_MATCH_OFFSET 22
791 #define MACB_RX_TYPEID_MATCH_SIZE 1
792 #define MACB_RX_SA4_MATCH_OFFSET 23
793 #define MACB_RX_SA4_MATCH_SIZE 1
794 #define MACB_RX_SA3_MATCH_OFFSET 24
795 #define MACB_RX_SA3_MATCH_SIZE 1
796 #define MACB_RX_SA2_MATCH_OFFSET 25
797 #define MACB_RX_SA2_MATCH_SIZE 1
798 #define MACB_RX_SA1_MATCH_OFFSET 26
799 #define MACB_RX_SA1_MATCH_SIZE 1
800 #define MACB_RX_EXT_MATCH_OFFSET 28
801 #define MACB_RX_EXT_MATCH_SIZE 1
802 #define MACB_RX_UHASH_MATCH_OFFSET 29
803 #define MACB_RX_UHASH_MATCH_SIZE 1
804 #define MACB_RX_MHASH_MATCH_OFFSET 30
805 #define MACB_RX_MHASH_MATCH_SIZE 1
806 #define MACB_RX_BROADCAST_OFFSET 31
807 #define MACB_RX_BROADCAST_SIZE 1
809 #define MACB_RX_FRMLEN_MASK 0xFFF
810 #define MACB_RX_JFRMLEN_MASK 0x3FFF
812 /* RX checksum offload disabled: bit 24 clear in NCFGR */
813 #define GEM_RX_TYPEID_MATCH_OFFSET 22
814 #define GEM_RX_TYPEID_MATCH_SIZE 2
816 /* RX checksum offload enabled: bit 24 set in NCFGR */
817 #define GEM_RX_CSUM_OFFSET 22
818 #define GEM_RX_CSUM_SIZE 2
820 #define MACB_TX_FRMLEN_OFFSET 0
821 #define MACB_TX_FRMLEN_SIZE 11
822 #define MACB_TX_LAST_OFFSET 15
823 #define MACB_TX_LAST_SIZE 1
824 #define MACB_TX_NOCRC_OFFSET 16
825 #define MACB_TX_NOCRC_SIZE 1
826 #define MACB_MSS_MFS_OFFSET 16
827 #define MACB_MSS_MFS_SIZE 14
828 #define MACB_TX_LSO_OFFSET 17
829 #define MACB_TX_LSO_SIZE 2
830 #define MACB_TX_TCP_SEQ_SRC_OFFSET 19
831 #define MACB_TX_TCP_SEQ_SRC_SIZE 1
832 #define MACB_TX_BUF_EXHAUSTED_OFFSET 27
833 #define MACB_TX_BUF_EXHAUSTED_SIZE 1
834 #define MACB_TX_UNDERRUN_OFFSET 28
835 #define MACB_TX_UNDERRUN_SIZE 1
836 #define MACB_TX_ERROR_OFFSET 29
837 #define MACB_TX_ERROR_SIZE 1
838 #define MACB_TX_WRAP_OFFSET 30
839 #define MACB_TX_WRAP_SIZE 1
840 #define MACB_TX_USED_OFFSET 31
841 #define MACB_TX_USED_SIZE 1
843 #define GEM_TX_FRMLEN_OFFSET 0
844 #define GEM_TX_FRMLEN_SIZE 14
846 /* Buffer descriptor constants */
847 #define GEM_RX_CSUM_NONE 0
848 #define GEM_RX_CSUM_IP_ONLY 1
849 #define GEM_RX_CSUM_IP_TCP 2
850 #define GEM_RX_CSUM_IP_UDP 3
852 /* limit RX checksum offload to TCP and UDP packets */
853 #define GEM_RX_CSUM_CHECKED_MASK 2
855 /* Scaled PPM fraction */
856 #define PPM_FRACTION 16
858 /* struct macb_tx_skb - data about an skb which is being transmitted
859 * @skb: skb currently being transmitted, only set for the last buffer
861 * @mapping: DMA address of the skb's fragment buffer
862 * @size: size of the DMA mapped buffer
863 * @mapped_as_page: true when buffer was mapped with skb_frag_dma_map(),
864 * false when buffer was mapped with dma_map_single()
873 /* Hardware-collected statistics. Used when updating the network
874 * device stats by a periodic timer.
880 u32 tx_multiple_cols;
886 u32 tx_excessive_cols;
888 u32 tx_carrier_errors;
889 u32 rx_resource_errors;
891 u32 rx_symbol_errors;
892 u32 rx_oversize_pkts;
894 u32 rx_undersize_pkts;
896 u32 rx_length_mismatch;
904 u32 tx_broadcast_frames;
905 u32 tx_multicast_frames;
907 u32 tx_64_byte_frames;
908 u32 tx_65_127_byte_frames;
909 u32 tx_128_255_byte_frames;
910 u32 tx_256_511_byte_frames;
911 u32 tx_512_1023_byte_frames;
912 u32 tx_1024_1518_byte_frames;
913 u32 tx_greater_than_1518_byte_frames;
915 u32 tx_single_collision_frames;
916 u32 tx_multiple_collision_frames;
917 u32 tx_excessive_collisions;
918 u32 tx_late_collisions;
919 u32 tx_deferred_frames;
920 u32 tx_carrier_sense_errors;
924 u32 rx_broadcast_frames;
925 u32 rx_multicast_frames;
927 u32 rx_64_byte_frames;
928 u32 rx_65_127_byte_frames;
929 u32 rx_128_255_byte_frames;
930 u32 rx_256_511_byte_frames;
931 u32 rx_512_1023_byte_frames;
932 u32 rx_1024_1518_byte_frames;
933 u32 rx_greater_than_1518_byte_frames;
934 u32 rx_undersized_frames;
935 u32 rx_oversize_frames;
937 u32 rx_frame_check_sequence_errors;
938 u32 rx_length_field_frame_errors;
939 u32 rx_symbol_errors;
940 u32 rx_alignment_errors;
941 u32 rx_resource_errors;
943 u32 rx_ip_header_checksum_errors;
944 u32 rx_tcp_checksum_errors;
945 u32 rx_udp_checksum_errors;
948 /* Describes the name and offset of an individual statistic register, as
949 * returned by `ethtool -S`. Also describes which net_device_stats statistics
950 * this register should contribute to.
952 struct gem_statistic {
953 char stat_string[ETH_GSTRING_LEN];
958 /* Bitfield defs for net_device_stat statistics */
959 #define GEM_NDS_RXERR_OFFSET 0
960 #define GEM_NDS_RXLENERR_OFFSET 1
961 #define GEM_NDS_RXOVERERR_OFFSET 2
962 #define GEM_NDS_RXCRCERR_OFFSET 3
963 #define GEM_NDS_RXFRAMEERR_OFFSET 4
964 #define GEM_NDS_RXFIFOERR_OFFSET 5
965 #define GEM_NDS_TXERR_OFFSET 6
966 #define GEM_NDS_TXABORTEDERR_OFFSET 7
967 #define GEM_NDS_TXCARRIERERR_OFFSET 8
968 #define GEM_NDS_TXFIFOERR_OFFSET 9
969 #define GEM_NDS_COLLISIONS_OFFSET 10
971 #define GEM_STAT_TITLE(name, title) GEM_STAT_TITLE_BITS(name, title, 0)
972 #define GEM_STAT_TITLE_BITS(name, title, bits) { \
973 .stat_string = title, \
974 .offset = GEM_##name, \
978 /* list of gem statistic registers. The names MUST match the
979 * corresponding GEM_* definitions.
981 static const struct gem_statistic gem_statistics[] = {
982 GEM_STAT_TITLE(OCTTXL, "tx_octets"), /* OCTTXH combined with OCTTXL */
983 GEM_STAT_TITLE(TXCNT, "tx_frames"),
984 GEM_STAT_TITLE(TXBCCNT, "tx_broadcast_frames"),
985 GEM_STAT_TITLE(TXMCCNT, "tx_multicast_frames"),
986 GEM_STAT_TITLE(TXPAUSECNT, "tx_pause_frames"),
987 GEM_STAT_TITLE(TX64CNT, "tx_64_byte_frames"),
988 GEM_STAT_TITLE(TX65CNT, "tx_65_127_byte_frames"),
989 GEM_STAT_TITLE(TX128CNT, "tx_128_255_byte_frames"),
990 GEM_STAT_TITLE(TX256CNT, "tx_256_511_byte_frames"),
991 GEM_STAT_TITLE(TX512CNT, "tx_512_1023_byte_frames"),
992 GEM_STAT_TITLE(TX1024CNT, "tx_1024_1518_byte_frames"),
993 GEM_STAT_TITLE(TX1519CNT, "tx_greater_than_1518_byte_frames"),
994 GEM_STAT_TITLE_BITS(TXURUNCNT, "tx_underrun",
995 GEM_BIT(NDS_TXERR)|GEM_BIT(NDS_TXFIFOERR)),
996 GEM_STAT_TITLE_BITS(SNGLCOLLCNT, "tx_single_collision_frames",
997 GEM_BIT(NDS_TXERR)|GEM_BIT(NDS_COLLISIONS)),
998 GEM_STAT_TITLE_BITS(MULTICOLLCNT, "tx_multiple_collision_frames",
999 GEM_BIT(NDS_TXERR)|GEM_BIT(NDS_COLLISIONS)),
1000 GEM_STAT_TITLE_BITS(EXCESSCOLLCNT, "tx_excessive_collisions",
1002 GEM_BIT(NDS_TXABORTEDERR)|
1003 GEM_BIT(NDS_COLLISIONS)),
1004 GEM_STAT_TITLE_BITS(LATECOLLCNT, "tx_late_collisions",
1005 GEM_BIT(NDS_TXERR)|GEM_BIT(NDS_COLLISIONS)),
1006 GEM_STAT_TITLE(TXDEFERCNT, "tx_deferred_frames"),
1007 GEM_STAT_TITLE_BITS(TXCSENSECNT, "tx_carrier_sense_errors",
1008 GEM_BIT(NDS_TXERR)|GEM_BIT(NDS_COLLISIONS)),
1009 GEM_STAT_TITLE(OCTRXL, "rx_octets"), /* OCTRXH combined with OCTRXL */
1010 GEM_STAT_TITLE(RXCNT, "rx_frames"),
1011 GEM_STAT_TITLE(RXBROADCNT, "rx_broadcast_frames"),
1012 GEM_STAT_TITLE(RXMULTICNT, "rx_multicast_frames"),
1013 GEM_STAT_TITLE(RXPAUSECNT, "rx_pause_frames"),
1014 GEM_STAT_TITLE(RX64CNT, "rx_64_byte_frames"),
1015 GEM_STAT_TITLE(RX65CNT, "rx_65_127_byte_frames"),
1016 GEM_STAT_TITLE(RX128CNT, "rx_128_255_byte_frames"),
1017 GEM_STAT_TITLE(RX256CNT, "rx_256_511_byte_frames"),
1018 GEM_STAT_TITLE(RX512CNT, "rx_512_1023_byte_frames"),
1019 GEM_STAT_TITLE(RX1024CNT, "rx_1024_1518_byte_frames"),
1020 GEM_STAT_TITLE(RX1519CNT, "rx_greater_than_1518_byte_frames"),
1021 GEM_STAT_TITLE_BITS(RXUNDRCNT, "rx_undersized_frames",
1022 GEM_BIT(NDS_RXERR)|GEM_BIT(NDS_RXLENERR)),
1023 GEM_STAT_TITLE_BITS(RXOVRCNT, "rx_oversize_frames",
1024 GEM_BIT(NDS_RXERR)|GEM_BIT(NDS_RXLENERR)),
1025 GEM_STAT_TITLE_BITS(RXJABCNT, "rx_jabbers",
1026 GEM_BIT(NDS_RXERR)|GEM_BIT(NDS_RXLENERR)),
1027 GEM_STAT_TITLE_BITS(RXFCSCNT, "rx_frame_check_sequence_errors",
1028 GEM_BIT(NDS_RXERR)|GEM_BIT(NDS_RXCRCERR)),
1029 GEM_STAT_TITLE_BITS(RXLENGTHCNT, "rx_length_field_frame_errors",
1030 GEM_BIT(NDS_RXERR)),
1031 GEM_STAT_TITLE_BITS(RXSYMBCNT, "rx_symbol_errors",
1032 GEM_BIT(NDS_RXERR)|GEM_BIT(NDS_RXFRAMEERR)),
1033 GEM_STAT_TITLE_BITS(RXALIGNCNT, "rx_alignment_errors",
1034 GEM_BIT(NDS_RXERR)|GEM_BIT(NDS_RXOVERERR)),
1035 GEM_STAT_TITLE_BITS(RXRESERRCNT, "rx_resource_errors",
1036 GEM_BIT(NDS_RXERR)|GEM_BIT(NDS_RXOVERERR)),
1037 GEM_STAT_TITLE_BITS(RXORCNT, "rx_overruns",
1038 GEM_BIT(NDS_RXERR)|GEM_BIT(NDS_RXFIFOERR)),
1039 GEM_STAT_TITLE_BITS(RXIPCCNT, "rx_ip_header_checksum_errors",
1040 GEM_BIT(NDS_RXERR)),
1041 GEM_STAT_TITLE_BITS(RXTCPCCNT, "rx_tcp_checksum_errors",
1042 GEM_BIT(NDS_RXERR)),
1043 GEM_STAT_TITLE_BITS(RXUDPCCNT, "rx_udp_checksum_errors",
1044 GEM_BIT(NDS_RXERR)),
1047 #define GEM_STATS_LEN ARRAY_SIZE(gem_statistics)
1049 #define QUEUE_STAT_TITLE(title) { \
1050 .stat_string = title, \
1053 /* per queue statistics, each should be unsigned long type */
1054 struct queue_stats {
1056 unsigned long first;
1057 unsigned long rx_packets;
1059 unsigned long rx_bytes;
1060 unsigned long rx_dropped;
1061 unsigned long tx_packets;
1062 unsigned long tx_bytes;
1063 unsigned long tx_dropped;
1066 static const struct gem_statistic queue_statistics[] = {
1067 QUEUE_STAT_TITLE("rx_packets"),
1068 QUEUE_STAT_TITLE("rx_bytes"),
1069 QUEUE_STAT_TITLE("rx_dropped"),
1070 QUEUE_STAT_TITLE("tx_packets"),
1071 QUEUE_STAT_TITLE("tx_bytes"),
1072 QUEUE_STAT_TITLE("tx_dropped"),
1075 #define QUEUE_STATS_LEN ARRAY_SIZE(queue_statistics)
1080 struct macb_or_gem_ops {
1081 int (*mog_alloc_rx_buffers)(struct macb *bp);
1082 void (*mog_free_rx_buffers)(struct macb *bp);
1083 void (*mog_init_rings)(struct macb *bp);
1084 int (*mog_rx)(struct macb_queue *queue, struct napi_struct *napi,
1088 /* MACB-PTP interface: adapt to platform needs. */
1089 struct macb_ptp_info {
1090 void (*ptp_init)(struct net_device *ndev);
1091 void (*ptp_remove)(struct net_device *ndev);
1092 s32 (*get_ptp_max_adj)(void);
1093 unsigned int (*get_tsu_rate)(struct macb *bp);
1094 int (*get_ts_info)(struct net_device *dev,
1095 struct ethtool_ts_info *info);
1096 int (*get_hwtst)(struct net_device *netdev,
1098 int (*set_hwtst)(struct net_device *netdev,
1099 struct ifreq *ifr, int cmd);
1102 struct macb_pm_data {
1107 struct macb_config {
1109 unsigned int dma_burst_length;
1110 int (*clk_init)(struct platform_device *pdev, struct clk **pclk,
1111 struct clk **hclk, struct clk **tx_clk,
1112 struct clk **rx_clk, struct clk **tsu_clk);
1113 int (*init)(struct platform_device *pdev);
1136 unsigned int tx_head, tx_tail;
1137 struct macb_dma_desc *tx_ring;
1138 struct macb_tx_skb *tx_skb;
1139 dma_addr_t tx_ring_dma;
1140 struct work_struct tx_error_task;
1142 dma_addr_t rx_ring_dma;
1143 dma_addr_t rx_buffers_dma;
1144 unsigned int rx_tail;
1145 unsigned int rx_prepared_head;
1146 struct macb_dma_desc *rx_ring;
1147 struct sk_buff **rx_skbuff;
1149 struct napi_struct napi;
1150 struct queue_stats stats;
1152 #ifdef CONFIG_MACB_USE_HWSTAMP
1153 struct work_struct tx_ts_task;
1154 unsigned int tx_ts_head, tx_ts_tail;
1155 struct gem_tx_ts tx_timestamps[PTP_TS_BUFFER_SIZE];
1159 struct ethtool_rx_fs_item {
1160 struct ethtool_rx_flow_spec fs;
1161 struct list_head list;
1164 struct ethtool_rx_fs_list {
1165 struct list_head list;
1173 /* hardware IO accessors */
1174 u32 (*macb_reg_readl)(struct macb *bp, int offset);
1175 void (*macb_reg_writel)(struct macb *bp, int offset, u32 value);
1177 size_t rx_buffer_size;
1179 unsigned int rx_ring_size;
1180 unsigned int tx_ring_size;
1182 unsigned int num_queues;
1183 unsigned int queue_mask;
1184 struct macb_queue queues[MACB_MAX_QUEUES];
1187 struct platform_device *pdev;
1192 struct clk *tsu_clk;
1193 struct net_device *dev;
1195 struct macb_stats macb;
1196 struct gem_stats gem;
1199 struct macb_or_gem_ops macbgem_ops;
1201 struct mii_bus *mii_bus;
1202 struct phylink *phylink;
1203 struct phylink_config phylink_config;
1206 unsigned int dma_burst_length;
1208 phy_interface_t phy_interface;
1210 /* AT91RM9200 transmit queue (1 on wire + 1 queued) */
1211 struct macb_tx_skb rm9200_txq[2];
1212 unsigned int rm9200_tx_tail;
1213 unsigned int rm9200_tx_len;
1214 unsigned int max_tx_length;
1216 u64 ethtool_stats[GEM_STATS_LEN + QUEUE_STATS_LEN * MACB_MAX_QUEUES];
1218 unsigned int rx_frm_len_mask;
1219 unsigned int jumbo_max_len;
1223 struct macb_ptp_info *ptp_info; /* macb-ptp interface */
1224 #ifdef MACB_EXT_DESC
1227 spinlock_t tsu_clk_lock; /* gem tsu clock locking */
1228 unsigned int tsu_rate;
1229 struct ptp_clock *ptp_clock;
1230 struct ptp_clock_info ptp_clock_info;
1231 struct tsu_incr tsu_incr;
1232 struct hwtstamp_config tstamp_config;
1234 /* RX queue filer rule set*/
1235 struct ethtool_rx_fs_list rx_fs_list;
1236 spinlock_t rx_fs_lock;
1237 unsigned int max_tuples;
1239 struct tasklet_struct hresp_err_tasklet;
1241 int rx_bd_rd_prefetch;
1242 int tx_bd_rd_prefetch;
1246 struct macb_pm_data pm_data;
1249 #ifdef CONFIG_MACB_USE_HWSTAMP
1250 #define GEM_TSEC_SIZE (GEM_TSH_SIZE + GEM_TSL_SIZE)
1251 #define TSU_SEC_MAX_VAL (((u64)1 << GEM_TSEC_SIZE) - 1)
1252 #define TSU_NSEC_MAX_VAL ((1 << GEM_TN_SIZE) - 1)
1254 enum macb_bd_control {
1256 TSTAMP_FRAME_PTP_EVENT_ONLY,
1257 TSTAMP_ALL_PTP_FRAMES,
1261 void gem_ptp_init(struct net_device *ndev);
1262 void gem_ptp_remove(struct net_device *ndev);
1263 int gem_ptp_txstamp(struct macb_queue *queue, struct sk_buff *skb, struct macb_dma_desc *des);
1264 void gem_ptp_rxstamp(struct macb *bp, struct sk_buff *skb, struct macb_dma_desc *desc);
1265 static inline int gem_ptp_do_txstamp(struct macb_queue *queue, struct sk_buff *skb, struct macb_dma_desc *desc)
1267 if (queue->bp->tstamp_config.tx_type == TSTAMP_DISABLED)
1270 return gem_ptp_txstamp(queue, skb, desc);
1273 static inline void gem_ptp_do_rxstamp(struct macb *bp, struct sk_buff *skb, struct macb_dma_desc *desc)
1275 if (bp->tstamp_config.rx_filter == TSTAMP_DISABLED)
1278 gem_ptp_rxstamp(bp, skb, desc);
1280 int gem_get_hwtst(struct net_device *dev, struct ifreq *rq);
1281 int gem_set_hwtst(struct net_device *dev, struct ifreq *ifr, int cmd);
1283 static inline void gem_ptp_init(struct net_device *ndev) { }
1284 static inline void gem_ptp_remove(struct net_device *ndev) { }
1286 static inline int gem_ptp_do_txstamp(struct macb_queue *queue, struct sk_buff *skb, struct macb_dma_desc *desc)
1291 static inline void gem_ptp_do_rxstamp(struct macb *bp, struct sk_buff *skb, struct macb_dma_desc *desc) { }
1294 static inline bool macb_is_gem(struct macb *bp)
1296 return !!(bp->caps & MACB_CAPS_MACB_IS_GEM);
1299 static inline bool gem_has_ptp(struct macb *bp)
1301 return !!(bp->caps & MACB_CAPS_GEM_HAS_PTP);
1305 * struct macb_platform_data - platform data for MACB Ethernet used for PCI registration
1306 * @pclk: platform clock
1309 struct macb_platform_data {
1314 #endif /* _MACB_H */
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