2 * tg3.c: Broadcom Tigon3 ethernet driver.
4 * Copyright (C) 2001, 2002, 2003, 2004 David S. Miller (davem@redhat.com)
5 * Copyright (C) 2001, 2002, 2003 Jeff Garzik (jgarzik@pobox.com)
6 * Copyright (C) 2004 Sun Microsystems Inc.
7 * Copyright (C) 2005-2016 Broadcom Corporation.
8 * Copyright (C) 2016-2017 Broadcom Limited.
9 * Copyright (C) 2018 Broadcom. All Rights Reserved. The term "Broadcom"
10 * refers to Broadcom Inc. and/or its subsidiaries.
13 * Derived from proprietary unpublished source code,
14 * Copyright (C) 2000-2016 Broadcom Corporation.
15 * Copyright (C) 2016-2017 Broadcom Ltd.
16 * Copyright (C) 2018 Broadcom. All Rights Reserved. The term "Broadcom"
17 * refers to Broadcom Inc. and/or its subsidiaries.
19 * Permission is hereby granted for the distribution of this firmware
20 * data in hexadecimal or equivalent format, provided this copyright
21 * notice is accompanying it.
25 #include <linux/module.h>
26 #include <linux/moduleparam.h>
27 #include <linux/stringify.h>
28 #include <linux/kernel.h>
29 #include <linux/sched/signal.h>
30 #include <linux/types.h>
31 #include <linux/compiler.h>
32 #include <linux/slab.h>
33 #include <linux/delay.h>
35 #include <linux/interrupt.h>
36 #include <linux/ioport.h>
37 #include <linux/pci.h>
38 #include <linux/netdevice.h>
39 #include <linux/etherdevice.h>
40 #include <linux/skbuff.h>
41 #include <linux/ethtool.h>
42 #include <linux/mdio.h>
43 #include <linux/mii.h>
44 #include <linux/phy.h>
45 #include <linux/brcmphy.h>
47 #include <linux/if_vlan.h>
49 #include <linux/tcp.h>
50 #include <linux/workqueue.h>
51 #include <linux/prefetch.h>
52 #include <linux/dma-mapping.h>
53 #include <linux/firmware.h>
54 #include <linux/ssb/ssb_driver_gige.h>
55 #include <linux/hwmon.h>
56 #include <linux/hwmon-sysfs.h>
58 #include <net/checksum.h>
62 #include <asm/byteorder.h>
63 #include <linux/uaccess.h>
65 #include <uapi/linux/net_tstamp.h>
66 #include <linux/ptp_clock_kernel.h>
69 #include <asm/idprom.h>
78 /* Functions & macros to verify TG3_FLAGS types */
80 static inline int _tg3_flag(enum TG3_FLAGS flag, unsigned long *bits)
82 return test_bit(flag, bits);
85 static inline void _tg3_flag_set(enum TG3_FLAGS flag, unsigned long *bits)
90 static inline void _tg3_flag_clear(enum TG3_FLAGS flag, unsigned long *bits)
92 clear_bit(flag, bits);
95 #define tg3_flag(tp, flag) \
96 _tg3_flag(TG3_FLAG_##flag, (tp)->tg3_flags)
97 #define tg3_flag_set(tp, flag) \
98 _tg3_flag_set(TG3_FLAG_##flag, (tp)->tg3_flags)
99 #define tg3_flag_clear(tp, flag) \
100 _tg3_flag_clear(TG3_FLAG_##flag, (tp)->tg3_flags)
102 #define DRV_MODULE_NAME "tg3"
103 #define TG3_MAJ_NUM 3
104 #define TG3_MIN_NUM 137
105 #define DRV_MODULE_VERSION \
106 __stringify(TG3_MAJ_NUM) "." __stringify(TG3_MIN_NUM)
107 #define DRV_MODULE_RELDATE "May 11, 2014"
109 #define RESET_KIND_SHUTDOWN 0
110 #define RESET_KIND_INIT 1
111 #define RESET_KIND_SUSPEND 2
113 #define TG3_DEF_RX_MODE 0
114 #define TG3_DEF_TX_MODE 0
115 #define TG3_DEF_MSG_ENABLE \
125 #define TG3_GRC_LCLCTL_PWRSW_DELAY 100
127 /* length of time before we decide the hardware is borked,
128 * and dev->tx_timeout() should be called to fix the problem
131 #define TG3_TX_TIMEOUT (5 * HZ)
133 /* hardware minimum and maximum for a single frame's data payload */
134 #define TG3_MIN_MTU ETH_ZLEN
135 #define TG3_MAX_MTU(tp) \
136 (tg3_flag(tp, JUMBO_CAPABLE) ? 9000 : 1500)
138 /* These numbers seem to be hard coded in the NIC firmware somehow.
139 * You can't change the ring sizes, but you can change where you place
140 * them in the NIC onboard memory.
142 #define TG3_RX_STD_RING_SIZE(tp) \
143 (tg3_flag(tp, LRG_PROD_RING_CAP) ? \
144 TG3_RX_STD_MAX_SIZE_5717 : TG3_RX_STD_MAX_SIZE_5700)
145 #define TG3_DEF_RX_RING_PENDING 200
146 #define TG3_RX_JMB_RING_SIZE(tp) \
147 (tg3_flag(tp, LRG_PROD_RING_CAP) ? \
148 TG3_RX_JMB_MAX_SIZE_5717 : TG3_RX_JMB_MAX_SIZE_5700)
149 #define TG3_DEF_RX_JUMBO_RING_PENDING 100
151 /* Do not place this n-ring entries value into the tp struct itself,
152 * we really want to expose these constants to GCC so that modulo et
153 * al. operations are done with shifts and masks instead of with
154 * hw multiply/modulo instructions. Another solution would be to
155 * replace things like '% foo' with '& (foo - 1)'.
158 #define TG3_TX_RING_SIZE 512
159 #define TG3_DEF_TX_RING_PENDING (TG3_TX_RING_SIZE - 1)
161 #define TG3_RX_STD_RING_BYTES(tp) \
162 (sizeof(struct tg3_rx_buffer_desc) * TG3_RX_STD_RING_SIZE(tp))
163 #define TG3_RX_JMB_RING_BYTES(tp) \
164 (sizeof(struct tg3_ext_rx_buffer_desc) * TG3_RX_JMB_RING_SIZE(tp))
165 #define TG3_RX_RCB_RING_BYTES(tp) \
166 (sizeof(struct tg3_rx_buffer_desc) * (tp->rx_ret_ring_mask + 1))
167 #define TG3_TX_RING_BYTES (sizeof(struct tg3_tx_buffer_desc) * \
169 #define NEXT_TX(N) (((N) + 1) & (TG3_TX_RING_SIZE - 1))
171 #define TG3_DMA_BYTE_ENAB 64
173 #define TG3_RX_STD_DMA_SZ 1536
174 #define TG3_RX_JMB_DMA_SZ 9046
176 #define TG3_RX_DMA_TO_MAP_SZ(x) ((x) + TG3_DMA_BYTE_ENAB)
178 #define TG3_RX_STD_MAP_SZ TG3_RX_DMA_TO_MAP_SZ(TG3_RX_STD_DMA_SZ)
179 #define TG3_RX_JMB_MAP_SZ TG3_RX_DMA_TO_MAP_SZ(TG3_RX_JMB_DMA_SZ)
181 #define TG3_RX_STD_BUFF_RING_SIZE(tp) \
182 (sizeof(struct ring_info) * TG3_RX_STD_RING_SIZE(tp))
184 #define TG3_RX_JMB_BUFF_RING_SIZE(tp) \
185 (sizeof(struct ring_info) * TG3_RX_JMB_RING_SIZE(tp))
187 /* Due to a hardware bug, the 5701 can only DMA to memory addresses
188 * that are at least dword aligned when used in PCIX mode. The driver
189 * works around this bug by double copying the packet. This workaround
190 * is built into the normal double copy length check for efficiency.
192 * However, the double copy is only necessary on those architectures
193 * where unaligned memory accesses are inefficient. For those architectures
194 * where unaligned memory accesses incur little penalty, we can reintegrate
195 * the 5701 in the normal rx path. Doing so saves a device structure
196 * dereference by hardcoding the double copy threshold in place.
198 #define TG3_RX_COPY_THRESHOLD 256
199 #if NET_IP_ALIGN == 0 || defined(CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS)
200 #define TG3_RX_COPY_THRESH(tp) TG3_RX_COPY_THRESHOLD
202 #define TG3_RX_COPY_THRESH(tp) ((tp)->rx_copy_thresh)
205 #if (NET_IP_ALIGN != 0)
206 #define TG3_RX_OFFSET(tp) ((tp)->rx_offset)
208 #define TG3_RX_OFFSET(tp) (NET_SKB_PAD)
211 /* minimum number of free TX descriptors required to wake up TX process */
212 #define TG3_TX_WAKEUP_THRESH(tnapi) ((tnapi)->tx_pending / 4)
213 #define TG3_TX_BD_DMA_MAX_2K 2048
214 #define TG3_TX_BD_DMA_MAX_4K 4096
216 #define TG3_RAW_IP_ALIGN 2
218 #define TG3_MAX_UCAST_ADDR(tp) (tg3_flag((tp), ENABLE_ASF) ? 2 : 3)
219 #define TG3_UCAST_ADDR_IDX(tp) (tg3_flag((tp), ENABLE_ASF) ? 2 : 1)
221 #define TG3_FW_UPDATE_TIMEOUT_SEC 5
222 #define TG3_FW_UPDATE_FREQ_SEC (TG3_FW_UPDATE_TIMEOUT_SEC / 2)
224 #define FIRMWARE_TG3 "tigon/tg3.bin"
225 #define FIRMWARE_TG357766 "tigon/tg357766.bin"
226 #define FIRMWARE_TG3TSO "tigon/tg3_tso.bin"
227 #define FIRMWARE_TG3TSO5 "tigon/tg3_tso5.bin"
229 static char version[] =
230 DRV_MODULE_NAME ".c:v" DRV_MODULE_VERSION " (" DRV_MODULE_RELDATE ")";
232 MODULE_AUTHOR("David S. Miller (davem@redhat.com) and Jeff Garzik (jgarzik@pobox.com)");
233 MODULE_DESCRIPTION("Broadcom Tigon3 ethernet driver");
234 MODULE_LICENSE("GPL");
235 MODULE_VERSION(DRV_MODULE_VERSION);
236 MODULE_FIRMWARE(FIRMWARE_TG3);
237 MODULE_FIRMWARE(FIRMWARE_TG3TSO);
238 MODULE_FIRMWARE(FIRMWARE_TG3TSO5);
240 static int tg3_debug = -1; /* -1 == use TG3_DEF_MSG_ENABLE as value */
241 module_param(tg3_debug, int, 0);
242 MODULE_PARM_DESC(tg3_debug, "Tigon3 bitmapped debugging message enable value");
244 #define TG3_DRV_DATA_FLAG_10_100_ONLY 0x0001
245 #define TG3_DRV_DATA_FLAG_5705_10_100 0x0002
247 static const struct pci_device_id tg3_pci_tbl[] = {
248 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5700)},
249 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5701)},
250 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702)},
251 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5703)},
252 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5704)},
253 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702FE)},
254 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705)},
255 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705_2)},
256 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705M)},
257 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705M_2)},
258 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702X)},
259 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5703X)},
260 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5704S)},
261 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702A3)},
262 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5703A3)},
263 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5782)},
264 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5788)},
265 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5789)},
266 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5901),
267 .driver_data = TG3_DRV_DATA_FLAG_10_100_ONLY |
268 TG3_DRV_DATA_FLAG_5705_10_100},
269 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5901_2),
270 .driver_data = TG3_DRV_DATA_FLAG_10_100_ONLY |
271 TG3_DRV_DATA_FLAG_5705_10_100},
272 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5704S_2)},
273 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705F),
274 .driver_data = TG3_DRV_DATA_FLAG_10_100_ONLY |
275 TG3_DRV_DATA_FLAG_5705_10_100},
276 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5721)},
277 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5722)},
278 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5750)},
279 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5751)},
280 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5751M)},
281 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5751F),
282 .driver_data = TG3_DRV_DATA_FLAG_10_100_ONLY},
283 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5752)},
284 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5752M)},
285 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5753)},
286 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5753M)},
287 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5753F),
288 .driver_data = TG3_DRV_DATA_FLAG_10_100_ONLY},
289 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5754)},
290 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5754M)},
291 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5755)},
292 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5755M)},
293 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5756)},
294 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5786)},
295 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5787)},
296 {PCI_DEVICE_SUB(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5787M,
297 PCI_VENDOR_ID_LENOVO,
298 TG3PCI_SUBDEVICE_ID_LENOVO_5787M),
299 .driver_data = TG3_DRV_DATA_FLAG_10_100_ONLY},
300 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5787M)},
301 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5787F),
302 .driver_data = TG3_DRV_DATA_FLAG_10_100_ONLY},
303 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5714)},
304 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5714S)},
305 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5715)},
306 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5715S)},
307 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5780)},
308 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5780S)},
309 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5781)},
310 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5906)},
311 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5906M)},
312 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5784)},
313 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5764)},
314 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5723)},
315 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5761)},
316 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5761E)},
317 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5761S)},
318 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5761SE)},
319 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5785_G)},
320 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5785_F)},
321 {PCI_DEVICE_SUB(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57780,
322 PCI_VENDOR_ID_AI, TG3PCI_SUBDEVICE_ID_ACER_57780_A),
323 .driver_data = TG3_DRV_DATA_FLAG_10_100_ONLY},
324 {PCI_DEVICE_SUB(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57780,
325 PCI_VENDOR_ID_AI, TG3PCI_SUBDEVICE_ID_ACER_57780_B),
326 .driver_data = TG3_DRV_DATA_FLAG_10_100_ONLY},
327 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57780)},
328 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57760)},
329 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57790),
330 .driver_data = TG3_DRV_DATA_FLAG_10_100_ONLY},
331 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57788)},
332 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5717)},
333 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5717_C)},
334 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5718)},
335 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57781)},
336 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57785)},
337 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57761)},
338 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57765)},
339 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57791),
340 .driver_data = TG3_DRV_DATA_FLAG_10_100_ONLY},
341 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57795),
342 .driver_data = TG3_DRV_DATA_FLAG_10_100_ONLY},
343 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5719)},
344 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5720)},
345 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57762)},
346 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57766)},
347 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5762)},
348 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5725)},
349 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5727)},
350 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57764)},
351 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57767)},
352 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57787)},
353 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57782)},
354 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57786)},
355 {PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, PCI_DEVICE_ID_SYSKONNECT_9DXX)},
356 {PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, PCI_DEVICE_ID_SYSKONNECT_9MXX)},
357 {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC1000)},
358 {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC1001)},
359 {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC1003)},
360 {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC9100)},
361 {PCI_DEVICE(PCI_VENDOR_ID_APPLE, PCI_DEVICE_ID_APPLE_TIGON3)},
362 {PCI_DEVICE(0x10cf, 0x11a2)}, /* Fujitsu 1000base-SX with BCM5703SKHB */
366 MODULE_DEVICE_TABLE(pci, tg3_pci_tbl);
368 static const struct {
369 const char string[ETH_GSTRING_LEN];
370 } ethtool_stats_keys[] = {
373 { "rx_ucast_packets" },
374 { "rx_mcast_packets" },
375 { "rx_bcast_packets" },
377 { "rx_align_errors" },
378 { "rx_xon_pause_rcvd" },
379 { "rx_xoff_pause_rcvd" },
380 { "rx_mac_ctrl_rcvd" },
381 { "rx_xoff_entered" },
382 { "rx_frame_too_long_errors" },
384 { "rx_undersize_packets" },
385 { "rx_in_length_errors" },
386 { "rx_out_length_errors" },
387 { "rx_64_or_less_octet_packets" },
388 { "rx_65_to_127_octet_packets" },
389 { "rx_128_to_255_octet_packets" },
390 { "rx_256_to_511_octet_packets" },
391 { "rx_512_to_1023_octet_packets" },
392 { "rx_1024_to_1522_octet_packets" },
393 { "rx_1523_to_2047_octet_packets" },
394 { "rx_2048_to_4095_octet_packets" },
395 { "rx_4096_to_8191_octet_packets" },
396 { "rx_8192_to_9022_octet_packets" },
403 { "tx_flow_control" },
405 { "tx_single_collisions" },
406 { "tx_mult_collisions" },
408 { "tx_excessive_collisions" },
409 { "tx_late_collisions" },
410 { "tx_collide_2times" },
411 { "tx_collide_3times" },
412 { "tx_collide_4times" },
413 { "tx_collide_5times" },
414 { "tx_collide_6times" },
415 { "tx_collide_7times" },
416 { "tx_collide_8times" },
417 { "tx_collide_9times" },
418 { "tx_collide_10times" },
419 { "tx_collide_11times" },
420 { "tx_collide_12times" },
421 { "tx_collide_13times" },
422 { "tx_collide_14times" },
423 { "tx_collide_15times" },
424 { "tx_ucast_packets" },
425 { "tx_mcast_packets" },
426 { "tx_bcast_packets" },
427 { "tx_carrier_sense_errors" },
431 { "dma_writeq_full" },
432 { "dma_write_prioq_full" },
436 { "rx_threshold_hit" },
438 { "dma_readq_full" },
439 { "dma_read_prioq_full" },
440 { "tx_comp_queue_full" },
442 { "ring_set_send_prod_index" },
443 { "ring_status_update" },
445 { "nic_avoided_irqs" },
446 { "nic_tx_threshold_hit" },
448 { "mbuf_lwm_thresh_hit" },
451 #define TG3_NUM_STATS ARRAY_SIZE(ethtool_stats_keys)
452 #define TG3_NVRAM_TEST 0
453 #define TG3_LINK_TEST 1
454 #define TG3_REGISTER_TEST 2
455 #define TG3_MEMORY_TEST 3
456 #define TG3_MAC_LOOPB_TEST 4
457 #define TG3_PHY_LOOPB_TEST 5
458 #define TG3_EXT_LOOPB_TEST 6
459 #define TG3_INTERRUPT_TEST 7
462 static const struct {
463 const char string[ETH_GSTRING_LEN];
464 } ethtool_test_keys[] = {
465 [TG3_NVRAM_TEST] = { "nvram test (online) " },
466 [TG3_LINK_TEST] = { "link test (online) " },
467 [TG3_REGISTER_TEST] = { "register test (offline)" },
468 [TG3_MEMORY_TEST] = { "memory test (offline)" },
469 [TG3_MAC_LOOPB_TEST] = { "mac loopback test (offline)" },
470 [TG3_PHY_LOOPB_TEST] = { "phy loopback test (offline)" },
471 [TG3_EXT_LOOPB_TEST] = { "ext loopback test (offline)" },
472 [TG3_INTERRUPT_TEST] = { "interrupt test (offline)" },
475 #define TG3_NUM_TEST ARRAY_SIZE(ethtool_test_keys)
478 static void tg3_write32(struct tg3 *tp, u32 off, u32 val)
480 writel(val, tp->regs + off);
483 static u32 tg3_read32(struct tg3 *tp, u32 off)
485 return readl(tp->regs + off);
488 static void tg3_ape_write32(struct tg3 *tp, u32 off, u32 val)
490 writel(val, tp->aperegs + off);
493 static u32 tg3_ape_read32(struct tg3 *tp, u32 off)
495 return readl(tp->aperegs + off);
498 static void tg3_write_indirect_reg32(struct tg3 *tp, u32 off, u32 val)
502 spin_lock_irqsave(&tp->indirect_lock, flags);
503 pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off);
504 pci_write_config_dword(tp->pdev, TG3PCI_REG_DATA, val);
505 spin_unlock_irqrestore(&tp->indirect_lock, flags);
508 static void tg3_write_flush_reg32(struct tg3 *tp, u32 off, u32 val)
510 writel(val, tp->regs + off);
511 readl(tp->regs + off);
514 static u32 tg3_read_indirect_reg32(struct tg3 *tp, u32 off)
519 spin_lock_irqsave(&tp->indirect_lock, flags);
520 pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off);
521 pci_read_config_dword(tp->pdev, TG3PCI_REG_DATA, &val);
522 spin_unlock_irqrestore(&tp->indirect_lock, flags);
526 static void tg3_write_indirect_mbox(struct tg3 *tp, u32 off, u32 val)
530 if (off == (MAILBOX_RCVRET_CON_IDX_0 + TG3_64BIT_REG_LOW)) {
531 pci_write_config_dword(tp->pdev, TG3PCI_RCV_RET_RING_CON_IDX +
532 TG3_64BIT_REG_LOW, val);
535 if (off == TG3_RX_STD_PROD_IDX_REG) {
536 pci_write_config_dword(tp->pdev, TG3PCI_STD_RING_PROD_IDX +
537 TG3_64BIT_REG_LOW, val);
541 spin_lock_irqsave(&tp->indirect_lock, flags);
542 pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off + 0x5600);
543 pci_write_config_dword(tp->pdev, TG3PCI_REG_DATA, val);
544 spin_unlock_irqrestore(&tp->indirect_lock, flags);
546 /* In indirect mode when disabling interrupts, we also need
547 * to clear the interrupt bit in the GRC local ctrl register.
549 if ((off == (MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW)) &&
551 pci_write_config_dword(tp->pdev, TG3PCI_MISC_LOCAL_CTRL,
552 tp->grc_local_ctrl|GRC_LCLCTRL_CLEARINT);
556 static u32 tg3_read_indirect_mbox(struct tg3 *tp, u32 off)
561 spin_lock_irqsave(&tp->indirect_lock, flags);
562 pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off + 0x5600);
563 pci_read_config_dword(tp->pdev, TG3PCI_REG_DATA, &val);
564 spin_unlock_irqrestore(&tp->indirect_lock, flags);
568 /* usec_wait specifies the wait time in usec when writing to certain registers
569 * where it is unsafe to read back the register without some delay.
570 * GRC_LOCAL_CTRL is one example if the GPIOs are toggled to switch power.
571 * TG3PCI_CLOCK_CTRL is another example if the clock frequencies are changed.
573 static void _tw32_flush(struct tg3 *tp, u32 off, u32 val, u32 usec_wait)
575 if (tg3_flag(tp, PCIX_TARGET_HWBUG) || tg3_flag(tp, ICH_WORKAROUND))
576 /* Non-posted methods */
577 tp->write32(tp, off, val);
580 tg3_write32(tp, off, val);
585 /* Wait again after the read for the posted method to guarantee that
586 * the wait time is met.
592 static inline void tw32_mailbox_flush(struct tg3 *tp, u32 off, u32 val)
594 tp->write32_mbox(tp, off, val);
595 if (tg3_flag(tp, FLUSH_POSTED_WRITES) ||
596 (!tg3_flag(tp, MBOX_WRITE_REORDER) &&
597 !tg3_flag(tp, ICH_WORKAROUND)))
598 tp->read32_mbox(tp, off);
601 static void tg3_write32_tx_mbox(struct tg3 *tp, u32 off, u32 val)
603 void __iomem *mbox = tp->regs + off;
605 if (tg3_flag(tp, TXD_MBOX_HWBUG))
607 if (tg3_flag(tp, MBOX_WRITE_REORDER) ||
608 tg3_flag(tp, FLUSH_POSTED_WRITES))
612 static u32 tg3_read32_mbox_5906(struct tg3 *tp, u32 off)
614 return readl(tp->regs + off + GRCMBOX_BASE);
617 static void tg3_write32_mbox_5906(struct tg3 *tp, u32 off, u32 val)
619 writel(val, tp->regs + off + GRCMBOX_BASE);
622 #define tw32_mailbox(reg, val) tp->write32_mbox(tp, reg, val)
623 #define tw32_mailbox_f(reg, val) tw32_mailbox_flush(tp, (reg), (val))
624 #define tw32_rx_mbox(reg, val) tp->write32_rx_mbox(tp, reg, val)
625 #define tw32_tx_mbox(reg, val) tp->write32_tx_mbox(tp, reg, val)
626 #define tr32_mailbox(reg) tp->read32_mbox(tp, reg)
628 #define tw32(reg, val) tp->write32(tp, reg, val)
629 #define tw32_f(reg, val) _tw32_flush(tp, (reg), (val), 0)
630 #define tw32_wait_f(reg, val, us) _tw32_flush(tp, (reg), (val), (us))
631 #define tr32(reg) tp->read32(tp, reg)
633 static void tg3_write_mem(struct tg3 *tp, u32 off, u32 val)
637 if (tg3_asic_rev(tp) == ASIC_REV_5906 &&
638 (off >= NIC_SRAM_STATS_BLK) && (off < NIC_SRAM_TX_BUFFER_DESC))
641 spin_lock_irqsave(&tp->indirect_lock, flags);
642 if (tg3_flag(tp, SRAM_USE_CONFIG)) {
643 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, off);
644 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_DATA, val);
646 /* Always leave this as zero. */
647 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, 0);
649 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, off);
650 tw32_f(TG3PCI_MEM_WIN_DATA, val);
652 /* Always leave this as zero. */
653 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, 0);
655 spin_unlock_irqrestore(&tp->indirect_lock, flags);
658 static void tg3_read_mem(struct tg3 *tp, u32 off, u32 *val)
662 if (tg3_asic_rev(tp) == ASIC_REV_5906 &&
663 (off >= NIC_SRAM_STATS_BLK) && (off < NIC_SRAM_TX_BUFFER_DESC)) {
668 spin_lock_irqsave(&tp->indirect_lock, flags);
669 if (tg3_flag(tp, SRAM_USE_CONFIG)) {
670 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, off);
671 pci_read_config_dword(tp->pdev, TG3PCI_MEM_WIN_DATA, val);
673 /* Always leave this as zero. */
674 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, 0);
676 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, off);
677 *val = tr32(TG3PCI_MEM_WIN_DATA);
679 /* Always leave this as zero. */
680 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, 0);
682 spin_unlock_irqrestore(&tp->indirect_lock, flags);
685 static void tg3_ape_lock_init(struct tg3 *tp)
690 if (tg3_asic_rev(tp) == ASIC_REV_5761)
691 regbase = TG3_APE_LOCK_GRANT;
693 regbase = TG3_APE_PER_LOCK_GRANT;
695 /* Make sure the driver hasn't any stale locks. */
696 for (i = TG3_APE_LOCK_PHY0; i <= TG3_APE_LOCK_GPIO; i++) {
698 case TG3_APE_LOCK_PHY0:
699 case TG3_APE_LOCK_PHY1:
700 case TG3_APE_LOCK_PHY2:
701 case TG3_APE_LOCK_PHY3:
702 bit = APE_LOCK_GRANT_DRIVER;
706 bit = APE_LOCK_GRANT_DRIVER;
708 bit = 1 << tp->pci_fn;
710 tg3_ape_write32(tp, regbase + 4 * i, bit);
715 static int tg3_ape_lock(struct tg3 *tp, int locknum)
719 u32 status, req, gnt, bit;
721 if (!tg3_flag(tp, ENABLE_APE))
725 case TG3_APE_LOCK_GPIO:
726 if (tg3_asic_rev(tp) == ASIC_REV_5761)
728 /* else: fall through */
729 case TG3_APE_LOCK_GRC:
730 case TG3_APE_LOCK_MEM:
732 bit = APE_LOCK_REQ_DRIVER;
734 bit = 1 << tp->pci_fn;
736 case TG3_APE_LOCK_PHY0:
737 case TG3_APE_LOCK_PHY1:
738 case TG3_APE_LOCK_PHY2:
739 case TG3_APE_LOCK_PHY3:
740 bit = APE_LOCK_REQ_DRIVER;
746 if (tg3_asic_rev(tp) == ASIC_REV_5761) {
747 req = TG3_APE_LOCK_REQ;
748 gnt = TG3_APE_LOCK_GRANT;
750 req = TG3_APE_PER_LOCK_REQ;
751 gnt = TG3_APE_PER_LOCK_GRANT;
756 tg3_ape_write32(tp, req + off, bit);
758 /* Wait for up to 1 millisecond to acquire lock. */
759 for (i = 0; i < 100; i++) {
760 status = tg3_ape_read32(tp, gnt + off);
763 if (pci_channel_offline(tp->pdev))
770 /* Revoke the lock request. */
771 tg3_ape_write32(tp, gnt + off, bit);
778 static void tg3_ape_unlock(struct tg3 *tp, int locknum)
782 if (!tg3_flag(tp, ENABLE_APE))
786 case TG3_APE_LOCK_GPIO:
787 if (tg3_asic_rev(tp) == ASIC_REV_5761)
789 /* else: fall through */
790 case TG3_APE_LOCK_GRC:
791 case TG3_APE_LOCK_MEM:
793 bit = APE_LOCK_GRANT_DRIVER;
795 bit = 1 << tp->pci_fn;
797 case TG3_APE_LOCK_PHY0:
798 case TG3_APE_LOCK_PHY1:
799 case TG3_APE_LOCK_PHY2:
800 case TG3_APE_LOCK_PHY3:
801 bit = APE_LOCK_GRANT_DRIVER;
807 if (tg3_asic_rev(tp) == ASIC_REV_5761)
808 gnt = TG3_APE_LOCK_GRANT;
810 gnt = TG3_APE_PER_LOCK_GRANT;
812 tg3_ape_write32(tp, gnt + 4 * locknum, bit);
815 static int tg3_ape_event_lock(struct tg3 *tp, u32 timeout_us)
820 if (tg3_ape_lock(tp, TG3_APE_LOCK_MEM))
823 apedata = tg3_ape_read32(tp, TG3_APE_EVENT_STATUS);
824 if (!(apedata & APE_EVENT_STATUS_EVENT_PENDING))
827 tg3_ape_unlock(tp, TG3_APE_LOCK_MEM);
830 timeout_us -= (timeout_us > 10) ? 10 : timeout_us;
833 return timeout_us ? 0 : -EBUSY;
836 #ifdef CONFIG_TIGON3_HWMON
837 static int tg3_ape_wait_for_event(struct tg3 *tp, u32 timeout_us)
841 for (i = 0; i < timeout_us / 10; i++) {
842 apedata = tg3_ape_read32(tp, TG3_APE_EVENT_STATUS);
844 if (!(apedata & APE_EVENT_STATUS_EVENT_PENDING))
850 return i == timeout_us / 10;
853 static int tg3_ape_scratchpad_read(struct tg3 *tp, u32 *data, u32 base_off,
857 u32 i, bufoff, msgoff, maxlen, apedata;
859 if (!tg3_flag(tp, APE_HAS_NCSI))
862 apedata = tg3_ape_read32(tp, TG3_APE_SEG_SIG);
863 if (apedata != APE_SEG_SIG_MAGIC)
866 apedata = tg3_ape_read32(tp, TG3_APE_FW_STATUS);
867 if (!(apedata & APE_FW_STATUS_READY))
870 bufoff = tg3_ape_read32(tp, TG3_APE_SEG_MSG_BUF_OFF) +
872 msgoff = bufoff + 2 * sizeof(u32);
873 maxlen = tg3_ape_read32(tp, TG3_APE_SEG_MSG_BUF_LEN);
878 /* Cap xfer sizes to scratchpad limits. */
879 length = (len > maxlen) ? maxlen : len;
882 apedata = tg3_ape_read32(tp, TG3_APE_FW_STATUS);
883 if (!(apedata & APE_FW_STATUS_READY))
886 /* Wait for up to 1 msec for APE to service previous event. */
887 err = tg3_ape_event_lock(tp, 1000);
891 apedata = APE_EVENT_STATUS_DRIVER_EVNT |
892 APE_EVENT_STATUS_SCRTCHPD_READ |
893 APE_EVENT_STATUS_EVENT_PENDING;
894 tg3_ape_write32(tp, TG3_APE_EVENT_STATUS, apedata);
896 tg3_ape_write32(tp, bufoff, base_off);
897 tg3_ape_write32(tp, bufoff + sizeof(u32), length);
899 tg3_ape_unlock(tp, TG3_APE_LOCK_MEM);
900 tg3_ape_write32(tp, TG3_APE_EVENT, APE_EVENT_1);
904 if (tg3_ape_wait_for_event(tp, 30000))
907 for (i = 0; length; i += 4, length -= 4) {
908 u32 val = tg3_ape_read32(tp, msgoff + i);
909 memcpy(data, &val, sizeof(u32));
918 static int tg3_ape_send_event(struct tg3 *tp, u32 event)
923 apedata = tg3_ape_read32(tp, TG3_APE_SEG_SIG);
924 if (apedata != APE_SEG_SIG_MAGIC)
927 apedata = tg3_ape_read32(tp, TG3_APE_FW_STATUS);
928 if (!(apedata & APE_FW_STATUS_READY))
931 /* Wait for up to 20 millisecond for APE to service previous event. */
932 err = tg3_ape_event_lock(tp, 20000);
936 tg3_ape_write32(tp, TG3_APE_EVENT_STATUS,
937 event | APE_EVENT_STATUS_EVENT_PENDING);
939 tg3_ape_unlock(tp, TG3_APE_LOCK_MEM);
940 tg3_ape_write32(tp, TG3_APE_EVENT, APE_EVENT_1);
945 static void tg3_ape_driver_state_change(struct tg3 *tp, int kind)
950 if (!tg3_flag(tp, ENABLE_APE))
954 case RESET_KIND_INIT:
955 tg3_ape_write32(tp, TG3_APE_HOST_HEARTBEAT_COUNT, tp->ape_hb++);
956 tg3_ape_write32(tp, TG3_APE_HOST_SEG_SIG,
957 APE_HOST_SEG_SIG_MAGIC);
958 tg3_ape_write32(tp, TG3_APE_HOST_SEG_LEN,
959 APE_HOST_SEG_LEN_MAGIC);
960 apedata = tg3_ape_read32(tp, TG3_APE_HOST_INIT_COUNT);
961 tg3_ape_write32(tp, TG3_APE_HOST_INIT_COUNT, ++apedata);
962 tg3_ape_write32(tp, TG3_APE_HOST_DRIVER_ID,
963 APE_HOST_DRIVER_ID_MAGIC(TG3_MAJ_NUM, TG3_MIN_NUM));
964 tg3_ape_write32(tp, TG3_APE_HOST_BEHAVIOR,
965 APE_HOST_BEHAV_NO_PHYLOCK);
966 tg3_ape_write32(tp, TG3_APE_HOST_DRVR_STATE,
967 TG3_APE_HOST_DRVR_STATE_START);
969 event = APE_EVENT_STATUS_STATE_START;
971 case RESET_KIND_SHUTDOWN:
972 if (device_may_wakeup(&tp->pdev->dev) &&
973 tg3_flag(tp, WOL_ENABLE)) {
974 tg3_ape_write32(tp, TG3_APE_HOST_WOL_SPEED,
975 TG3_APE_HOST_WOL_SPEED_AUTO);
976 apedata = TG3_APE_HOST_DRVR_STATE_WOL;
978 apedata = TG3_APE_HOST_DRVR_STATE_UNLOAD;
980 tg3_ape_write32(tp, TG3_APE_HOST_DRVR_STATE, apedata);
982 event = APE_EVENT_STATUS_STATE_UNLOAD;
988 event |= APE_EVENT_STATUS_DRIVER_EVNT | APE_EVENT_STATUS_STATE_CHNGE;
990 tg3_ape_send_event(tp, event);
993 static void tg3_send_ape_heartbeat(struct tg3 *tp,
994 unsigned long interval)
996 /* Check if hb interval has exceeded */
997 if (!tg3_flag(tp, ENABLE_APE) ||
998 time_before(jiffies, tp->ape_hb_jiffies + interval))
1001 tg3_ape_write32(tp, TG3_APE_HOST_HEARTBEAT_COUNT, tp->ape_hb++);
1002 tp->ape_hb_jiffies = jiffies;
1005 static void tg3_disable_ints(struct tg3 *tp)
1009 tw32(TG3PCI_MISC_HOST_CTRL,
1010 (tp->misc_host_ctrl | MISC_HOST_CTRL_MASK_PCI_INT));
1011 for (i = 0; i < tp->irq_max; i++)
1012 tw32_mailbox_f(tp->napi[i].int_mbox, 0x00000001);
1015 static void tg3_enable_ints(struct tg3 *tp)
1022 tw32(TG3PCI_MISC_HOST_CTRL,
1023 (tp->misc_host_ctrl & ~MISC_HOST_CTRL_MASK_PCI_INT));
1025 tp->coal_now = tp->coalesce_mode | HOSTCC_MODE_ENABLE;
1026 for (i = 0; i < tp->irq_cnt; i++) {
1027 struct tg3_napi *tnapi = &tp->napi[i];
1029 tw32_mailbox_f(tnapi->int_mbox, tnapi->last_tag << 24);
1030 if (tg3_flag(tp, 1SHOT_MSI))
1031 tw32_mailbox_f(tnapi->int_mbox, tnapi->last_tag << 24);
1033 tp->coal_now |= tnapi->coal_now;
1036 /* Force an initial interrupt */
1037 if (!tg3_flag(tp, TAGGED_STATUS) &&
1038 (tp->napi[0].hw_status->status & SD_STATUS_UPDATED))
1039 tw32(GRC_LOCAL_CTRL, tp->grc_local_ctrl | GRC_LCLCTRL_SETINT);
1041 tw32(HOSTCC_MODE, tp->coal_now);
1043 tp->coal_now &= ~(tp->napi[0].coal_now | tp->napi[1].coal_now);
1046 static inline unsigned int tg3_has_work(struct tg3_napi *tnapi)
1048 struct tg3 *tp = tnapi->tp;
1049 struct tg3_hw_status *sblk = tnapi->hw_status;
1050 unsigned int work_exists = 0;
1052 /* check for phy events */
1053 if (!(tg3_flag(tp, USE_LINKCHG_REG) || tg3_flag(tp, POLL_SERDES))) {
1054 if (sblk->status & SD_STATUS_LINK_CHG)
1058 /* check for TX work to do */
1059 if (sblk->idx[0].tx_consumer != tnapi->tx_cons)
1062 /* check for RX work to do */
1063 if (tnapi->rx_rcb_prod_idx &&
1064 *(tnapi->rx_rcb_prod_idx) != tnapi->rx_rcb_ptr)
1071 * similar to tg3_enable_ints, but it accurately determines whether there
1072 * is new work pending and can return without flushing the PIO write
1073 * which reenables interrupts
1075 static void tg3_int_reenable(struct tg3_napi *tnapi)
1077 struct tg3 *tp = tnapi->tp;
1079 tw32_mailbox(tnapi->int_mbox, tnapi->last_tag << 24);
1082 /* When doing tagged status, this work check is unnecessary.
1083 * The last_tag we write above tells the chip which piece of
1084 * work we've completed.
1086 if (!tg3_flag(tp, TAGGED_STATUS) && tg3_has_work(tnapi))
1087 tw32(HOSTCC_MODE, tp->coalesce_mode |
1088 HOSTCC_MODE_ENABLE | tnapi->coal_now);
1091 static void tg3_switch_clocks(struct tg3 *tp)
1094 u32 orig_clock_ctrl;
1096 if (tg3_flag(tp, CPMU_PRESENT) || tg3_flag(tp, 5780_CLASS))
1099 clock_ctrl = tr32(TG3PCI_CLOCK_CTRL);
1101 orig_clock_ctrl = clock_ctrl;
1102 clock_ctrl &= (CLOCK_CTRL_FORCE_CLKRUN |
1103 CLOCK_CTRL_CLKRUN_OENABLE |
1105 tp->pci_clock_ctrl = clock_ctrl;
1107 if (tg3_flag(tp, 5705_PLUS)) {
1108 if (orig_clock_ctrl & CLOCK_CTRL_625_CORE) {
1109 tw32_wait_f(TG3PCI_CLOCK_CTRL,
1110 clock_ctrl | CLOCK_CTRL_625_CORE, 40);
1112 } else if ((orig_clock_ctrl & CLOCK_CTRL_44MHZ_CORE) != 0) {
1113 tw32_wait_f(TG3PCI_CLOCK_CTRL,
1115 (CLOCK_CTRL_44MHZ_CORE | CLOCK_CTRL_ALTCLK),
1117 tw32_wait_f(TG3PCI_CLOCK_CTRL,
1118 clock_ctrl | (CLOCK_CTRL_ALTCLK),
1121 tw32_wait_f(TG3PCI_CLOCK_CTRL, clock_ctrl, 40);
1124 #define PHY_BUSY_LOOPS 5000
1126 static int __tg3_readphy(struct tg3 *tp, unsigned int phy_addr, int reg,
1133 if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
1135 (tp->mi_mode & ~MAC_MI_MODE_AUTO_POLL));
1139 tg3_ape_lock(tp, tp->phy_ape_lock);
1143 frame_val = ((phy_addr << MI_COM_PHY_ADDR_SHIFT) &
1144 MI_COM_PHY_ADDR_MASK);
1145 frame_val |= ((reg << MI_COM_REG_ADDR_SHIFT) &
1146 MI_COM_REG_ADDR_MASK);
1147 frame_val |= (MI_COM_CMD_READ | MI_COM_START);
1149 tw32_f(MAC_MI_COM, frame_val);
1151 loops = PHY_BUSY_LOOPS;
1152 while (loops != 0) {
1154 frame_val = tr32(MAC_MI_COM);
1156 if ((frame_val & MI_COM_BUSY) == 0) {
1158 frame_val = tr32(MAC_MI_COM);
1166 *val = frame_val & MI_COM_DATA_MASK;
1170 if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
1171 tw32_f(MAC_MI_MODE, tp->mi_mode);
1175 tg3_ape_unlock(tp, tp->phy_ape_lock);
1180 static int tg3_readphy(struct tg3 *tp, int reg, u32 *val)
1182 return __tg3_readphy(tp, tp->phy_addr, reg, val);
1185 static int __tg3_writephy(struct tg3 *tp, unsigned int phy_addr, int reg,
1192 if ((tp->phy_flags & TG3_PHYFLG_IS_FET) &&
1193 (reg == MII_CTRL1000 || reg == MII_TG3_AUX_CTRL))
1196 if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
1198 (tp->mi_mode & ~MAC_MI_MODE_AUTO_POLL));
1202 tg3_ape_lock(tp, tp->phy_ape_lock);
1204 frame_val = ((phy_addr << MI_COM_PHY_ADDR_SHIFT) &
1205 MI_COM_PHY_ADDR_MASK);
1206 frame_val |= ((reg << MI_COM_REG_ADDR_SHIFT) &
1207 MI_COM_REG_ADDR_MASK);
1208 frame_val |= (val & MI_COM_DATA_MASK);
1209 frame_val |= (MI_COM_CMD_WRITE | MI_COM_START);
1211 tw32_f(MAC_MI_COM, frame_val);
1213 loops = PHY_BUSY_LOOPS;
1214 while (loops != 0) {
1216 frame_val = tr32(MAC_MI_COM);
1217 if ((frame_val & MI_COM_BUSY) == 0) {
1219 frame_val = tr32(MAC_MI_COM);
1229 if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
1230 tw32_f(MAC_MI_MODE, tp->mi_mode);
1234 tg3_ape_unlock(tp, tp->phy_ape_lock);
1239 static int tg3_writephy(struct tg3 *tp, int reg, u32 val)
1241 return __tg3_writephy(tp, tp->phy_addr, reg, val);
1244 static int tg3_phy_cl45_write(struct tg3 *tp, u32 devad, u32 addr, u32 val)
1248 err = tg3_writephy(tp, MII_TG3_MMD_CTRL, devad);
1252 err = tg3_writephy(tp, MII_TG3_MMD_ADDRESS, addr);
1256 err = tg3_writephy(tp, MII_TG3_MMD_CTRL,
1257 MII_TG3_MMD_CTRL_DATA_NOINC | devad);
1261 err = tg3_writephy(tp, MII_TG3_MMD_ADDRESS, val);
1267 static int tg3_phy_cl45_read(struct tg3 *tp, u32 devad, u32 addr, u32 *val)
1271 err = tg3_writephy(tp, MII_TG3_MMD_CTRL, devad);
1275 err = tg3_writephy(tp, MII_TG3_MMD_ADDRESS, addr);
1279 err = tg3_writephy(tp, MII_TG3_MMD_CTRL,
1280 MII_TG3_MMD_CTRL_DATA_NOINC | devad);
1284 err = tg3_readphy(tp, MII_TG3_MMD_ADDRESS, val);
1290 static int tg3_phydsp_read(struct tg3 *tp, u32 reg, u32 *val)
1294 err = tg3_writephy(tp, MII_TG3_DSP_ADDRESS, reg);
1296 err = tg3_readphy(tp, MII_TG3_DSP_RW_PORT, val);
1301 static int tg3_phydsp_write(struct tg3 *tp, u32 reg, u32 val)
1305 err = tg3_writephy(tp, MII_TG3_DSP_ADDRESS, reg);
1307 err = tg3_writephy(tp, MII_TG3_DSP_RW_PORT, val);
1312 static int tg3_phy_auxctl_read(struct tg3 *tp, int reg, u32 *val)
1316 err = tg3_writephy(tp, MII_TG3_AUX_CTRL,
1317 (reg << MII_TG3_AUXCTL_MISC_RDSEL_SHIFT) |
1318 MII_TG3_AUXCTL_SHDWSEL_MISC);
1320 err = tg3_readphy(tp, MII_TG3_AUX_CTRL, val);
1325 static int tg3_phy_auxctl_write(struct tg3 *tp, int reg, u32 set)
1327 if (reg == MII_TG3_AUXCTL_SHDWSEL_MISC)
1328 set |= MII_TG3_AUXCTL_MISC_WREN;
1330 return tg3_writephy(tp, MII_TG3_AUX_CTRL, set | reg);
1333 static int tg3_phy_toggle_auxctl_smdsp(struct tg3 *tp, bool enable)
1338 err = tg3_phy_auxctl_read(tp, MII_TG3_AUXCTL_SHDWSEL_AUXCTL, &val);
1344 val |= MII_TG3_AUXCTL_ACTL_SMDSP_ENA;
1346 val &= ~MII_TG3_AUXCTL_ACTL_SMDSP_ENA;
1348 err = tg3_phy_auxctl_write((tp), MII_TG3_AUXCTL_SHDWSEL_AUXCTL,
1349 val | MII_TG3_AUXCTL_ACTL_TX_6DB);
1354 static int tg3_phy_shdw_write(struct tg3 *tp, int reg, u32 val)
1356 return tg3_writephy(tp, MII_TG3_MISC_SHDW,
1357 reg | val | MII_TG3_MISC_SHDW_WREN);
1360 static int tg3_bmcr_reset(struct tg3 *tp)
1365 /* OK, reset it, and poll the BMCR_RESET bit until it
1366 * clears or we time out.
1368 phy_control = BMCR_RESET;
1369 err = tg3_writephy(tp, MII_BMCR, phy_control);
1375 err = tg3_readphy(tp, MII_BMCR, &phy_control);
1379 if ((phy_control & BMCR_RESET) == 0) {
1391 static int tg3_mdio_read(struct mii_bus *bp, int mii_id, int reg)
1393 struct tg3 *tp = bp->priv;
1396 spin_lock_bh(&tp->lock);
1398 if (__tg3_readphy(tp, mii_id, reg, &val))
1401 spin_unlock_bh(&tp->lock);
1406 static int tg3_mdio_write(struct mii_bus *bp, int mii_id, int reg, u16 val)
1408 struct tg3 *tp = bp->priv;
1411 spin_lock_bh(&tp->lock);
1413 if (__tg3_writephy(tp, mii_id, reg, val))
1416 spin_unlock_bh(&tp->lock);
1421 static void tg3_mdio_config_5785(struct tg3 *tp)
1424 struct phy_device *phydev;
1426 phydev = mdiobus_get_phy(tp->mdio_bus, tp->phy_addr);
1427 switch (phydev->drv->phy_id & phydev->drv->phy_id_mask) {
1428 case PHY_ID_BCM50610:
1429 case PHY_ID_BCM50610M:
1430 val = MAC_PHYCFG2_50610_LED_MODES;
1432 case PHY_ID_BCMAC131:
1433 val = MAC_PHYCFG2_AC131_LED_MODES;
1435 case PHY_ID_RTL8211C:
1436 val = MAC_PHYCFG2_RTL8211C_LED_MODES;
1438 case PHY_ID_RTL8201E:
1439 val = MAC_PHYCFG2_RTL8201E_LED_MODES;
1445 if (phydev->interface != PHY_INTERFACE_MODE_RGMII) {
1446 tw32(MAC_PHYCFG2, val);
1448 val = tr32(MAC_PHYCFG1);
1449 val &= ~(MAC_PHYCFG1_RGMII_INT |
1450 MAC_PHYCFG1_RXCLK_TO_MASK | MAC_PHYCFG1_TXCLK_TO_MASK);
1451 val |= MAC_PHYCFG1_RXCLK_TIMEOUT | MAC_PHYCFG1_TXCLK_TIMEOUT;
1452 tw32(MAC_PHYCFG1, val);
1457 if (!tg3_flag(tp, RGMII_INBAND_DISABLE))
1458 val |= MAC_PHYCFG2_EMODE_MASK_MASK |
1459 MAC_PHYCFG2_FMODE_MASK_MASK |
1460 MAC_PHYCFG2_GMODE_MASK_MASK |
1461 MAC_PHYCFG2_ACT_MASK_MASK |
1462 MAC_PHYCFG2_QUAL_MASK_MASK |
1463 MAC_PHYCFG2_INBAND_ENABLE;
1465 tw32(MAC_PHYCFG2, val);
1467 val = tr32(MAC_PHYCFG1);
1468 val &= ~(MAC_PHYCFG1_RXCLK_TO_MASK | MAC_PHYCFG1_TXCLK_TO_MASK |
1469 MAC_PHYCFG1_RGMII_EXT_RX_DEC | MAC_PHYCFG1_RGMII_SND_STAT_EN);
1470 if (!tg3_flag(tp, RGMII_INBAND_DISABLE)) {
1471 if (tg3_flag(tp, RGMII_EXT_IBND_RX_EN))
1472 val |= MAC_PHYCFG1_RGMII_EXT_RX_DEC;
1473 if (tg3_flag(tp, RGMII_EXT_IBND_TX_EN))
1474 val |= MAC_PHYCFG1_RGMII_SND_STAT_EN;
1476 val |= MAC_PHYCFG1_RXCLK_TIMEOUT | MAC_PHYCFG1_TXCLK_TIMEOUT |
1477 MAC_PHYCFG1_RGMII_INT | MAC_PHYCFG1_TXC_DRV;
1478 tw32(MAC_PHYCFG1, val);
1480 val = tr32(MAC_EXT_RGMII_MODE);
1481 val &= ~(MAC_RGMII_MODE_RX_INT_B |
1482 MAC_RGMII_MODE_RX_QUALITY |
1483 MAC_RGMII_MODE_RX_ACTIVITY |
1484 MAC_RGMII_MODE_RX_ENG_DET |
1485 MAC_RGMII_MODE_TX_ENABLE |
1486 MAC_RGMII_MODE_TX_LOWPWR |
1487 MAC_RGMII_MODE_TX_RESET);
1488 if (!tg3_flag(tp, RGMII_INBAND_DISABLE)) {
1489 if (tg3_flag(tp, RGMII_EXT_IBND_RX_EN))
1490 val |= MAC_RGMII_MODE_RX_INT_B |
1491 MAC_RGMII_MODE_RX_QUALITY |
1492 MAC_RGMII_MODE_RX_ACTIVITY |
1493 MAC_RGMII_MODE_RX_ENG_DET;
1494 if (tg3_flag(tp, RGMII_EXT_IBND_TX_EN))
1495 val |= MAC_RGMII_MODE_TX_ENABLE |
1496 MAC_RGMII_MODE_TX_LOWPWR |
1497 MAC_RGMII_MODE_TX_RESET;
1499 tw32(MAC_EXT_RGMII_MODE, val);
1502 static void tg3_mdio_start(struct tg3 *tp)
1504 tp->mi_mode &= ~MAC_MI_MODE_AUTO_POLL;
1505 tw32_f(MAC_MI_MODE, tp->mi_mode);
1508 if (tg3_flag(tp, MDIOBUS_INITED) &&
1509 tg3_asic_rev(tp) == ASIC_REV_5785)
1510 tg3_mdio_config_5785(tp);
1513 static int tg3_mdio_init(struct tg3 *tp)
1517 struct phy_device *phydev;
1519 if (tg3_flag(tp, 5717_PLUS)) {
1522 tp->phy_addr = tp->pci_fn + 1;
1524 if (tg3_chip_rev_id(tp) != CHIPREV_ID_5717_A0)
1525 is_serdes = tr32(SG_DIG_STATUS) & SG_DIG_IS_SERDES;
1527 is_serdes = tr32(TG3_CPMU_PHY_STRAP) &
1528 TG3_CPMU_PHY_STRAP_IS_SERDES;
1531 } else if (tg3_flag(tp, IS_SSB_CORE) && tg3_flag(tp, ROBOSWITCH)) {
1534 addr = ssb_gige_get_phyaddr(tp->pdev);
1537 tp->phy_addr = addr;
1539 tp->phy_addr = TG3_PHY_MII_ADDR;
1543 if (!tg3_flag(tp, USE_PHYLIB) || tg3_flag(tp, MDIOBUS_INITED))
1546 tp->mdio_bus = mdiobus_alloc();
1547 if (tp->mdio_bus == NULL)
1550 tp->mdio_bus->name = "tg3 mdio bus";
1551 snprintf(tp->mdio_bus->id, MII_BUS_ID_SIZE, "%x",
1552 (tp->pdev->bus->number << 8) | tp->pdev->devfn);
1553 tp->mdio_bus->priv = tp;
1554 tp->mdio_bus->parent = &tp->pdev->dev;
1555 tp->mdio_bus->read = &tg3_mdio_read;
1556 tp->mdio_bus->write = &tg3_mdio_write;
1557 tp->mdio_bus->phy_mask = ~(1 << tp->phy_addr);
1559 /* The bus registration will look for all the PHYs on the mdio bus.
1560 * Unfortunately, it does not ensure the PHY is powered up before
1561 * accessing the PHY ID registers. A chip reset is the
1562 * quickest way to bring the device back to an operational state..
1564 if (tg3_readphy(tp, MII_BMCR, ®) || (reg & BMCR_PDOWN))
1567 i = mdiobus_register(tp->mdio_bus);
1569 dev_warn(&tp->pdev->dev, "mdiobus_reg failed (0x%x)\n", i);
1570 mdiobus_free(tp->mdio_bus);
1574 phydev = mdiobus_get_phy(tp->mdio_bus, tp->phy_addr);
1576 if (!phydev || !phydev->drv) {
1577 dev_warn(&tp->pdev->dev, "No PHY devices\n");
1578 mdiobus_unregister(tp->mdio_bus);
1579 mdiobus_free(tp->mdio_bus);
1583 switch (phydev->drv->phy_id & phydev->drv->phy_id_mask) {
1584 case PHY_ID_BCM57780:
1585 phydev->interface = PHY_INTERFACE_MODE_GMII;
1586 phydev->dev_flags |= PHY_BRCM_AUTO_PWRDWN_ENABLE;
1588 case PHY_ID_BCM50610:
1589 case PHY_ID_BCM50610M:
1590 phydev->dev_flags |= PHY_BRCM_CLEAR_RGMII_MODE |
1591 PHY_BRCM_RX_REFCLK_UNUSED |
1592 PHY_BRCM_DIS_TXCRXC_NOENRGY |
1593 PHY_BRCM_AUTO_PWRDWN_ENABLE;
1594 if (tg3_flag(tp, RGMII_INBAND_DISABLE))
1595 phydev->dev_flags |= PHY_BRCM_STD_IBND_DISABLE;
1596 if (tg3_flag(tp, RGMII_EXT_IBND_RX_EN))
1597 phydev->dev_flags |= PHY_BRCM_EXT_IBND_RX_ENABLE;
1598 if (tg3_flag(tp, RGMII_EXT_IBND_TX_EN))
1599 phydev->dev_flags |= PHY_BRCM_EXT_IBND_TX_ENABLE;
1601 case PHY_ID_RTL8211C:
1602 phydev->interface = PHY_INTERFACE_MODE_RGMII;
1604 case PHY_ID_RTL8201E:
1605 case PHY_ID_BCMAC131:
1606 phydev->interface = PHY_INTERFACE_MODE_MII;
1607 phydev->dev_flags |= PHY_BRCM_AUTO_PWRDWN_ENABLE;
1608 tp->phy_flags |= TG3_PHYFLG_IS_FET;
1612 tg3_flag_set(tp, MDIOBUS_INITED);
1614 if (tg3_asic_rev(tp) == ASIC_REV_5785)
1615 tg3_mdio_config_5785(tp);
1620 static void tg3_mdio_fini(struct tg3 *tp)
1622 if (tg3_flag(tp, MDIOBUS_INITED)) {
1623 tg3_flag_clear(tp, MDIOBUS_INITED);
1624 mdiobus_unregister(tp->mdio_bus);
1625 mdiobus_free(tp->mdio_bus);
1629 /* tp->lock is held. */
1630 static inline void tg3_generate_fw_event(struct tg3 *tp)
1634 val = tr32(GRC_RX_CPU_EVENT);
1635 val |= GRC_RX_CPU_DRIVER_EVENT;
1636 tw32_f(GRC_RX_CPU_EVENT, val);
1638 tp->last_event_jiffies = jiffies;
1641 #define TG3_FW_EVENT_TIMEOUT_USEC 2500
1643 /* tp->lock is held. */
1644 static void tg3_wait_for_event_ack(struct tg3 *tp)
1647 unsigned int delay_cnt;
1650 /* If enough time has passed, no wait is necessary. */
1651 time_remain = (long)(tp->last_event_jiffies + 1 +
1652 usecs_to_jiffies(TG3_FW_EVENT_TIMEOUT_USEC)) -
1654 if (time_remain < 0)
1657 /* Check if we can shorten the wait time. */
1658 delay_cnt = jiffies_to_usecs(time_remain);
1659 if (delay_cnt > TG3_FW_EVENT_TIMEOUT_USEC)
1660 delay_cnt = TG3_FW_EVENT_TIMEOUT_USEC;
1661 delay_cnt = (delay_cnt >> 3) + 1;
1663 for (i = 0; i < delay_cnt; i++) {
1664 if (!(tr32(GRC_RX_CPU_EVENT) & GRC_RX_CPU_DRIVER_EVENT))
1666 if (pci_channel_offline(tp->pdev))
1673 /* tp->lock is held. */
1674 static void tg3_phy_gather_ump_data(struct tg3 *tp, u32 *data)
1679 if (!tg3_readphy(tp, MII_BMCR, ®))
1681 if (!tg3_readphy(tp, MII_BMSR, ®))
1682 val |= (reg & 0xffff);
1686 if (!tg3_readphy(tp, MII_ADVERTISE, ®))
1688 if (!tg3_readphy(tp, MII_LPA, ®))
1689 val |= (reg & 0xffff);
1693 if (!(tp->phy_flags & TG3_PHYFLG_MII_SERDES)) {
1694 if (!tg3_readphy(tp, MII_CTRL1000, ®))
1696 if (!tg3_readphy(tp, MII_STAT1000, ®))
1697 val |= (reg & 0xffff);
1701 if (!tg3_readphy(tp, MII_PHYADDR, ®))
1708 /* tp->lock is held. */
1709 static void tg3_ump_link_report(struct tg3 *tp)
1713 if (!tg3_flag(tp, 5780_CLASS) || !tg3_flag(tp, ENABLE_ASF))
1716 tg3_phy_gather_ump_data(tp, data);
1718 tg3_wait_for_event_ack(tp);
1720 tg3_write_mem(tp, NIC_SRAM_FW_CMD_MBOX, FWCMD_NICDRV_LINK_UPDATE);
1721 tg3_write_mem(tp, NIC_SRAM_FW_CMD_LEN_MBOX, 14);
1722 tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX + 0x0, data[0]);
1723 tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX + 0x4, data[1]);
1724 tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX + 0x8, data[2]);
1725 tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX + 0xc, data[3]);
1727 tg3_generate_fw_event(tp);
1730 /* tp->lock is held. */
1731 static void tg3_stop_fw(struct tg3 *tp)
1733 if (tg3_flag(tp, ENABLE_ASF) && !tg3_flag(tp, ENABLE_APE)) {
1734 /* Wait for RX cpu to ACK the previous event. */
1735 tg3_wait_for_event_ack(tp);
1737 tg3_write_mem(tp, NIC_SRAM_FW_CMD_MBOX, FWCMD_NICDRV_PAUSE_FW);
1739 tg3_generate_fw_event(tp);
1741 /* Wait for RX cpu to ACK this event. */
1742 tg3_wait_for_event_ack(tp);
1746 /* tp->lock is held. */
1747 static void tg3_write_sig_pre_reset(struct tg3 *tp, int kind)
1749 tg3_write_mem(tp, NIC_SRAM_FIRMWARE_MBOX,
1750 NIC_SRAM_FIRMWARE_MBOX_MAGIC1);
1752 if (tg3_flag(tp, ASF_NEW_HANDSHAKE)) {
1754 case RESET_KIND_INIT:
1755 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
1759 case RESET_KIND_SHUTDOWN:
1760 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
1764 case RESET_KIND_SUSPEND:
1765 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
1775 /* tp->lock is held. */
1776 static void tg3_write_sig_post_reset(struct tg3 *tp, int kind)
1778 if (tg3_flag(tp, ASF_NEW_HANDSHAKE)) {
1780 case RESET_KIND_INIT:
1781 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
1782 DRV_STATE_START_DONE);
1785 case RESET_KIND_SHUTDOWN:
1786 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
1787 DRV_STATE_UNLOAD_DONE);
1796 /* tp->lock is held. */
1797 static void tg3_write_sig_legacy(struct tg3 *tp, int kind)
1799 if (tg3_flag(tp, ENABLE_ASF)) {
1801 case RESET_KIND_INIT:
1802 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
1806 case RESET_KIND_SHUTDOWN:
1807 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
1811 case RESET_KIND_SUSPEND:
1812 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
1822 static int tg3_poll_fw(struct tg3 *tp)
1827 if (tg3_flag(tp, NO_FWARE_REPORTED))
1830 if (tg3_flag(tp, IS_SSB_CORE)) {
1831 /* We don't use firmware. */
1835 if (tg3_asic_rev(tp) == ASIC_REV_5906) {
1836 /* Wait up to 20ms for init done. */
1837 for (i = 0; i < 200; i++) {
1838 if (tr32(VCPU_STATUS) & VCPU_STATUS_INIT_DONE)
1840 if (pci_channel_offline(tp->pdev))
1848 /* Wait for firmware initialization to complete. */
1849 for (i = 0; i < 100000; i++) {
1850 tg3_read_mem(tp, NIC_SRAM_FIRMWARE_MBOX, &val);
1851 if (val == ~NIC_SRAM_FIRMWARE_MBOX_MAGIC1)
1853 if (pci_channel_offline(tp->pdev)) {
1854 if (!tg3_flag(tp, NO_FWARE_REPORTED)) {
1855 tg3_flag_set(tp, NO_FWARE_REPORTED);
1856 netdev_info(tp->dev, "No firmware running\n");
1865 /* Chip might not be fitted with firmware. Some Sun onboard
1866 * parts are configured like that. So don't signal the timeout
1867 * of the above loop as an error, but do report the lack of
1868 * running firmware once.
1870 if (i >= 100000 && !tg3_flag(tp, NO_FWARE_REPORTED)) {
1871 tg3_flag_set(tp, NO_FWARE_REPORTED);
1873 netdev_info(tp->dev, "No firmware running\n");
1876 if (tg3_chip_rev_id(tp) == CHIPREV_ID_57765_A0) {
1877 /* The 57765 A0 needs a little more
1878 * time to do some important work.
1886 static void tg3_link_report(struct tg3 *tp)
1888 if (!netif_carrier_ok(tp->dev)) {
1889 netif_info(tp, link, tp->dev, "Link is down\n");
1890 tg3_ump_link_report(tp);
1891 } else if (netif_msg_link(tp)) {
1892 netdev_info(tp->dev, "Link is up at %d Mbps, %s duplex\n",
1893 (tp->link_config.active_speed == SPEED_1000 ?
1895 (tp->link_config.active_speed == SPEED_100 ?
1897 (tp->link_config.active_duplex == DUPLEX_FULL ?
1900 netdev_info(tp->dev, "Flow control is %s for TX and %s for RX\n",
1901 (tp->link_config.active_flowctrl & FLOW_CTRL_TX) ?
1903 (tp->link_config.active_flowctrl & FLOW_CTRL_RX) ?
1906 if (tp->phy_flags & TG3_PHYFLG_EEE_CAP)
1907 netdev_info(tp->dev, "EEE is %s\n",
1908 tp->setlpicnt ? "enabled" : "disabled");
1910 tg3_ump_link_report(tp);
1913 tp->link_up = netif_carrier_ok(tp->dev);
1916 static u32 tg3_decode_flowctrl_1000T(u32 adv)
1920 if (adv & ADVERTISE_PAUSE_CAP) {
1921 flowctrl |= FLOW_CTRL_RX;
1922 if (!(adv & ADVERTISE_PAUSE_ASYM))
1923 flowctrl |= FLOW_CTRL_TX;
1924 } else if (adv & ADVERTISE_PAUSE_ASYM)
1925 flowctrl |= FLOW_CTRL_TX;
1930 static u16 tg3_advert_flowctrl_1000X(u8 flow_ctrl)
1934 if ((flow_ctrl & FLOW_CTRL_TX) && (flow_ctrl & FLOW_CTRL_RX))
1935 miireg = ADVERTISE_1000XPAUSE;
1936 else if (flow_ctrl & FLOW_CTRL_TX)
1937 miireg = ADVERTISE_1000XPSE_ASYM;
1938 else if (flow_ctrl & FLOW_CTRL_RX)
1939 miireg = ADVERTISE_1000XPAUSE | ADVERTISE_1000XPSE_ASYM;
1946 static u32 tg3_decode_flowctrl_1000X(u32 adv)
1950 if (adv & ADVERTISE_1000XPAUSE) {
1951 flowctrl |= FLOW_CTRL_RX;
1952 if (!(adv & ADVERTISE_1000XPSE_ASYM))
1953 flowctrl |= FLOW_CTRL_TX;
1954 } else if (adv & ADVERTISE_1000XPSE_ASYM)
1955 flowctrl |= FLOW_CTRL_TX;
1960 static u8 tg3_resolve_flowctrl_1000X(u16 lcladv, u16 rmtadv)
1964 if (lcladv & rmtadv & ADVERTISE_1000XPAUSE) {
1965 cap = FLOW_CTRL_TX | FLOW_CTRL_RX;
1966 } else if (lcladv & rmtadv & ADVERTISE_1000XPSE_ASYM) {
1967 if (lcladv & ADVERTISE_1000XPAUSE)
1969 if (rmtadv & ADVERTISE_1000XPAUSE)
1976 static void tg3_setup_flow_control(struct tg3 *tp, u32 lcladv, u32 rmtadv)
1980 u32 old_rx_mode = tp->rx_mode;
1981 u32 old_tx_mode = tp->tx_mode;
1983 if (tg3_flag(tp, USE_PHYLIB))
1984 autoneg = mdiobus_get_phy(tp->mdio_bus, tp->phy_addr)->autoneg;
1986 autoneg = tp->link_config.autoneg;
1988 if (autoneg == AUTONEG_ENABLE && tg3_flag(tp, PAUSE_AUTONEG)) {
1989 if (tp->phy_flags & TG3_PHYFLG_ANY_SERDES)
1990 flowctrl = tg3_resolve_flowctrl_1000X(lcladv, rmtadv);
1992 flowctrl = mii_resolve_flowctrl_fdx(lcladv, rmtadv);
1994 flowctrl = tp->link_config.flowctrl;
1996 tp->link_config.active_flowctrl = flowctrl;
1998 if (flowctrl & FLOW_CTRL_RX)
1999 tp->rx_mode |= RX_MODE_FLOW_CTRL_ENABLE;
2001 tp->rx_mode &= ~RX_MODE_FLOW_CTRL_ENABLE;
2003 if (old_rx_mode != tp->rx_mode)
2004 tw32_f(MAC_RX_MODE, tp->rx_mode);
2006 if (flowctrl & FLOW_CTRL_TX)
2007 tp->tx_mode |= TX_MODE_FLOW_CTRL_ENABLE;
2009 tp->tx_mode &= ~TX_MODE_FLOW_CTRL_ENABLE;
2011 if (old_tx_mode != tp->tx_mode)
2012 tw32_f(MAC_TX_MODE, tp->tx_mode);
2015 static void tg3_adjust_link(struct net_device *dev)
2017 u8 oldflowctrl, linkmesg = 0;
2018 u32 mac_mode, lcl_adv, rmt_adv;
2019 struct tg3 *tp = netdev_priv(dev);
2020 struct phy_device *phydev = mdiobus_get_phy(tp->mdio_bus, tp->phy_addr);
2022 spin_lock_bh(&tp->lock);
2024 mac_mode = tp->mac_mode & ~(MAC_MODE_PORT_MODE_MASK |
2025 MAC_MODE_HALF_DUPLEX);
2027 oldflowctrl = tp->link_config.active_flowctrl;
2033 if (phydev->speed == SPEED_100 || phydev->speed == SPEED_10)
2034 mac_mode |= MAC_MODE_PORT_MODE_MII;
2035 else if (phydev->speed == SPEED_1000 ||
2036 tg3_asic_rev(tp) != ASIC_REV_5785)
2037 mac_mode |= MAC_MODE_PORT_MODE_GMII;
2039 mac_mode |= MAC_MODE_PORT_MODE_MII;
2041 if (phydev->duplex == DUPLEX_HALF)
2042 mac_mode |= MAC_MODE_HALF_DUPLEX;
2044 lcl_adv = mii_advertise_flowctrl(
2045 tp->link_config.flowctrl);
2048 rmt_adv = LPA_PAUSE_CAP;
2049 if (phydev->asym_pause)
2050 rmt_adv |= LPA_PAUSE_ASYM;
2053 tg3_setup_flow_control(tp, lcl_adv, rmt_adv);
2055 mac_mode |= MAC_MODE_PORT_MODE_GMII;
2057 if (mac_mode != tp->mac_mode) {
2058 tp->mac_mode = mac_mode;
2059 tw32_f(MAC_MODE, tp->mac_mode);
2063 if (tg3_asic_rev(tp) == ASIC_REV_5785) {
2064 if (phydev->speed == SPEED_10)
2066 MAC_MI_STAT_10MBPS_MODE |
2067 MAC_MI_STAT_LNKSTAT_ATTN_ENAB);
2069 tw32(MAC_MI_STAT, MAC_MI_STAT_LNKSTAT_ATTN_ENAB);
2072 if (phydev->speed == SPEED_1000 && phydev->duplex == DUPLEX_HALF)
2073 tw32(MAC_TX_LENGTHS,
2074 ((2 << TX_LENGTHS_IPG_CRS_SHIFT) |
2075 (6 << TX_LENGTHS_IPG_SHIFT) |
2076 (0xff << TX_LENGTHS_SLOT_TIME_SHIFT)));
2078 tw32(MAC_TX_LENGTHS,
2079 ((2 << TX_LENGTHS_IPG_CRS_SHIFT) |
2080 (6 << TX_LENGTHS_IPG_SHIFT) |
2081 (32 << TX_LENGTHS_SLOT_TIME_SHIFT)));
2083 if (phydev->link != tp->old_link ||
2084 phydev->speed != tp->link_config.active_speed ||
2085 phydev->duplex != tp->link_config.active_duplex ||
2086 oldflowctrl != tp->link_config.active_flowctrl)
2089 tp->old_link = phydev->link;
2090 tp->link_config.active_speed = phydev->speed;
2091 tp->link_config.active_duplex = phydev->duplex;
2093 spin_unlock_bh(&tp->lock);
2096 tg3_link_report(tp);
2099 static int tg3_phy_init(struct tg3 *tp)
2101 struct phy_device *phydev;
2103 if (tp->phy_flags & TG3_PHYFLG_IS_CONNECTED)
2106 /* Bring the PHY back to a known state. */
2109 phydev = mdiobus_get_phy(tp->mdio_bus, tp->phy_addr);
2111 /* Attach the MAC to the PHY. */
2112 phydev = phy_connect(tp->dev, phydev_name(phydev),
2113 tg3_adjust_link, phydev->interface);
2114 if (IS_ERR(phydev)) {
2115 dev_err(&tp->pdev->dev, "Could not attach to PHY\n");
2116 return PTR_ERR(phydev);
2119 /* Mask with MAC supported features. */
2120 switch (phydev->interface) {
2121 case PHY_INTERFACE_MODE_GMII:
2122 case PHY_INTERFACE_MODE_RGMII:
2123 if (!(tp->phy_flags & TG3_PHYFLG_10_100_ONLY)) {
2124 phydev->supported &= (PHY_GBIT_FEATURES |
2126 SUPPORTED_Asym_Pause);
2130 case PHY_INTERFACE_MODE_MII:
2131 phydev->supported &= (PHY_BASIC_FEATURES |
2133 SUPPORTED_Asym_Pause);
2136 phy_disconnect(mdiobus_get_phy(tp->mdio_bus, tp->phy_addr));
2140 tp->phy_flags |= TG3_PHYFLG_IS_CONNECTED;
2142 phydev->advertising = phydev->supported;
2144 phy_attached_info(phydev);
2149 static void tg3_phy_start(struct tg3 *tp)
2151 struct phy_device *phydev;
2153 if (!(tp->phy_flags & TG3_PHYFLG_IS_CONNECTED))
2156 phydev = mdiobus_get_phy(tp->mdio_bus, tp->phy_addr);
2158 if (tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER) {
2159 tp->phy_flags &= ~TG3_PHYFLG_IS_LOW_POWER;
2160 phydev->speed = tp->link_config.speed;
2161 phydev->duplex = tp->link_config.duplex;
2162 phydev->autoneg = tp->link_config.autoneg;
2163 phydev->advertising = tp->link_config.advertising;
2168 phy_start_aneg(phydev);
2171 static void tg3_phy_stop(struct tg3 *tp)
2173 if (!(tp->phy_flags & TG3_PHYFLG_IS_CONNECTED))
2176 phy_stop(mdiobus_get_phy(tp->mdio_bus, tp->phy_addr));
2179 static void tg3_phy_fini(struct tg3 *tp)
2181 if (tp->phy_flags & TG3_PHYFLG_IS_CONNECTED) {
2182 phy_disconnect(mdiobus_get_phy(tp->mdio_bus, tp->phy_addr));
2183 tp->phy_flags &= ~TG3_PHYFLG_IS_CONNECTED;
2187 static int tg3_phy_set_extloopbk(struct tg3 *tp)
2192 if (tp->phy_flags & TG3_PHYFLG_IS_FET)
2195 if ((tp->phy_id & TG3_PHY_ID_MASK) == TG3_PHY_ID_BCM5401) {
2196 /* Cannot do read-modify-write on 5401 */
2197 err = tg3_phy_auxctl_write(tp,
2198 MII_TG3_AUXCTL_SHDWSEL_AUXCTL,
2199 MII_TG3_AUXCTL_ACTL_EXTLOOPBK |
2204 err = tg3_phy_auxctl_read(tp,
2205 MII_TG3_AUXCTL_SHDWSEL_AUXCTL, &val);
2209 val |= MII_TG3_AUXCTL_ACTL_EXTLOOPBK;
2210 err = tg3_phy_auxctl_write(tp,
2211 MII_TG3_AUXCTL_SHDWSEL_AUXCTL, val);
2217 static void tg3_phy_fet_toggle_apd(struct tg3 *tp, bool enable)
2221 if (!tg3_readphy(tp, MII_TG3_FET_TEST, &phytest)) {
2224 tg3_writephy(tp, MII_TG3_FET_TEST,
2225 phytest | MII_TG3_FET_SHADOW_EN);
2226 if (!tg3_readphy(tp, MII_TG3_FET_SHDW_AUXSTAT2, &phy)) {
2228 phy |= MII_TG3_FET_SHDW_AUXSTAT2_APD;
2230 phy &= ~MII_TG3_FET_SHDW_AUXSTAT2_APD;
2231 tg3_writephy(tp, MII_TG3_FET_SHDW_AUXSTAT2, phy);
2233 tg3_writephy(tp, MII_TG3_FET_TEST, phytest);
2237 static void tg3_phy_toggle_apd(struct tg3 *tp, bool enable)
2241 if (!tg3_flag(tp, 5705_PLUS) ||
2242 (tg3_flag(tp, 5717_PLUS) &&
2243 (tp->phy_flags & TG3_PHYFLG_MII_SERDES)))
2246 if (tp->phy_flags & TG3_PHYFLG_IS_FET) {
2247 tg3_phy_fet_toggle_apd(tp, enable);
2251 reg = MII_TG3_MISC_SHDW_SCR5_LPED |
2252 MII_TG3_MISC_SHDW_SCR5_DLPTLM |
2253 MII_TG3_MISC_SHDW_SCR5_SDTL |
2254 MII_TG3_MISC_SHDW_SCR5_C125OE;
2255 if (tg3_asic_rev(tp) != ASIC_REV_5784 || !enable)
2256 reg |= MII_TG3_MISC_SHDW_SCR5_DLLAPD;
2258 tg3_phy_shdw_write(tp, MII_TG3_MISC_SHDW_SCR5_SEL, reg);
2261 reg = MII_TG3_MISC_SHDW_APD_WKTM_84MS;
2263 reg |= MII_TG3_MISC_SHDW_APD_ENABLE;
2265 tg3_phy_shdw_write(tp, MII_TG3_MISC_SHDW_APD_SEL, reg);
2268 static void tg3_phy_toggle_automdix(struct tg3 *tp, bool enable)
2272 if (!tg3_flag(tp, 5705_PLUS) ||
2273 (tp->phy_flags & TG3_PHYFLG_ANY_SERDES))
2276 if (tp->phy_flags & TG3_PHYFLG_IS_FET) {
2279 if (!tg3_readphy(tp, MII_TG3_FET_TEST, &ephy)) {
2280 u32 reg = MII_TG3_FET_SHDW_MISCCTRL;
2282 tg3_writephy(tp, MII_TG3_FET_TEST,
2283 ephy | MII_TG3_FET_SHADOW_EN);
2284 if (!tg3_readphy(tp, reg, &phy)) {
2286 phy |= MII_TG3_FET_SHDW_MISCCTRL_MDIX;
2288 phy &= ~MII_TG3_FET_SHDW_MISCCTRL_MDIX;
2289 tg3_writephy(tp, reg, phy);
2291 tg3_writephy(tp, MII_TG3_FET_TEST, ephy);
2296 ret = tg3_phy_auxctl_read(tp,
2297 MII_TG3_AUXCTL_SHDWSEL_MISC, &phy);
2300 phy |= MII_TG3_AUXCTL_MISC_FORCE_AMDIX;
2302 phy &= ~MII_TG3_AUXCTL_MISC_FORCE_AMDIX;
2303 tg3_phy_auxctl_write(tp,
2304 MII_TG3_AUXCTL_SHDWSEL_MISC, phy);
2309 static void tg3_phy_set_wirespeed(struct tg3 *tp)
2314 if (tp->phy_flags & TG3_PHYFLG_NO_ETH_WIRE_SPEED)
2317 ret = tg3_phy_auxctl_read(tp, MII_TG3_AUXCTL_SHDWSEL_MISC, &val);
2319 tg3_phy_auxctl_write(tp, MII_TG3_AUXCTL_SHDWSEL_MISC,
2320 val | MII_TG3_AUXCTL_MISC_WIRESPD_EN);
2323 static void tg3_phy_apply_otp(struct tg3 *tp)
2332 if (tg3_phy_toggle_auxctl_smdsp(tp, true))
2335 phy = ((otp & TG3_OTP_AGCTGT_MASK) >> TG3_OTP_AGCTGT_SHIFT);
2336 phy |= MII_TG3_DSP_TAP1_AGCTGT_DFLT;
2337 tg3_phydsp_write(tp, MII_TG3_DSP_TAP1, phy);
2339 phy = ((otp & TG3_OTP_HPFFLTR_MASK) >> TG3_OTP_HPFFLTR_SHIFT) |
2340 ((otp & TG3_OTP_HPFOVER_MASK) >> TG3_OTP_HPFOVER_SHIFT);
2341 tg3_phydsp_write(tp, MII_TG3_DSP_AADJ1CH0, phy);
2343 phy = ((otp & TG3_OTP_LPFDIS_MASK) >> TG3_OTP_LPFDIS_SHIFT);
2344 phy |= MII_TG3_DSP_AADJ1CH3_ADCCKADJ;
2345 tg3_phydsp_write(tp, MII_TG3_DSP_AADJ1CH3, phy);
2347 phy = ((otp & TG3_OTP_VDAC_MASK) >> TG3_OTP_VDAC_SHIFT);
2348 tg3_phydsp_write(tp, MII_TG3_DSP_EXP75, phy);
2350 phy = ((otp & TG3_OTP_10BTAMP_MASK) >> TG3_OTP_10BTAMP_SHIFT);
2351 tg3_phydsp_write(tp, MII_TG3_DSP_EXP96, phy);
2353 phy = ((otp & TG3_OTP_ROFF_MASK) >> TG3_OTP_ROFF_SHIFT) |
2354 ((otp & TG3_OTP_RCOFF_MASK) >> TG3_OTP_RCOFF_SHIFT);
2355 tg3_phydsp_write(tp, MII_TG3_DSP_EXP97, phy);
2357 tg3_phy_toggle_auxctl_smdsp(tp, false);
2360 static void tg3_eee_pull_config(struct tg3 *tp, struct ethtool_eee *eee)
2363 struct ethtool_eee *dest = &tp->eee;
2365 if (!(tp->phy_flags & TG3_PHYFLG_EEE_CAP))
2371 if (tg3_phy_cl45_read(tp, MDIO_MMD_AN, TG3_CL45_D7_EEERES_STAT, &val))
2374 /* Pull eee_active */
2375 if (val == TG3_CL45_D7_EEERES_STAT_LP_1000T ||
2376 val == TG3_CL45_D7_EEERES_STAT_LP_100TX) {
2377 dest->eee_active = 1;
2379 dest->eee_active = 0;
2381 /* Pull lp advertised settings */
2382 if (tg3_phy_cl45_read(tp, MDIO_MMD_AN, MDIO_AN_EEE_LPABLE, &val))
2384 dest->lp_advertised = mmd_eee_adv_to_ethtool_adv_t(val);
2386 /* Pull advertised and eee_enabled settings */
2387 if (tg3_phy_cl45_read(tp, MDIO_MMD_AN, MDIO_AN_EEE_ADV, &val))
2389 dest->eee_enabled = !!val;
2390 dest->advertised = mmd_eee_adv_to_ethtool_adv_t(val);
2392 /* Pull tx_lpi_enabled */
2393 val = tr32(TG3_CPMU_EEE_MODE);
2394 dest->tx_lpi_enabled = !!(val & TG3_CPMU_EEEMD_LPI_IN_TX);
2396 /* Pull lpi timer value */
2397 dest->tx_lpi_timer = tr32(TG3_CPMU_EEE_DBTMR1) & 0xffff;
2400 static void tg3_phy_eee_adjust(struct tg3 *tp, bool current_link_up)
2404 if (!(tp->phy_flags & TG3_PHYFLG_EEE_CAP))
2409 if (tp->link_config.autoneg == AUTONEG_ENABLE &&
2411 tp->link_config.active_duplex == DUPLEX_FULL &&
2412 (tp->link_config.active_speed == SPEED_100 ||
2413 tp->link_config.active_speed == SPEED_1000)) {
2416 if (tp->link_config.active_speed == SPEED_1000)
2417 eeectl = TG3_CPMU_EEE_CTRL_EXIT_16_5_US;
2419 eeectl = TG3_CPMU_EEE_CTRL_EXIT_36_US;
2421 tw32(TG3_CPMU_EEE_CTRL, eeectl);
2423 tg3_eee_pull_config(tp, NULL);
2424 if (tp->eee.eee_active)
2428 if (!tp->setlpicnt) {
2429 if (current_link_up &&
2430 !tg3_phy_toggle_auxctl_smdsp(tp, true)) {
2431 tg3_phydsp_write(tp, MII_TG3_DSP_TAP26, 0x0000);
2432 tg3_phy_toggle_auxctl_smdsp(tp, false);
2435 val = tr32(TG3_CPMU_EEE_MODE);
2436 tw32(TG3_CPMU_EEE_MODE, val & ~TG3_CPMU_EEEMD_LPI_ENABLE);
2440 static void tg3_phy_eee_enable(struct tg3 *tp)
2444 if (tp->link_config.active_speed == SPEED_1000 &&
2445 (tg3_asic_rev(tp) == ASIC_REV_5717 ||
2446 tg3_asic_rev(tp) == ASIC_REV_5719 ||
2447 tg3_flag(tp, 57765_CLASS)) &&
2448 !tg3_phy_toggle_auxctl_smdsp(tp, true)) {
2449 val = MII_TG3_DSP_TAP26_ALNOKO |
2450 MII_TG3_DSP_TAP26_RMRXSTO;
2451 tg3_phydsp_write(tp, MII_TG3_DSP_TAP26, val);
2452 tg3_phy_toggle_auxctl_smdsp(tp, false);
2455 val = tr32(TG3_CPMU_EEE_MODE);
2456 tw32(TG3_CPMU_EEE_MODE, val | TG3_CPMU_EEEMD_LPI_ENABLE);
2459 static int tg3_wait_macro_done(struct tg3 *tp)
2466 if (!tg3_readphy(tp, MII_TG3_DSP_CONTROL, &tmp32)) {
2467 if ((tmp32 & 0x1000) == 0)
2477 static int tg3_phy_write_and_check_testpat(struct tg3 *tp, int *resetp)
2479 static const u32 test_pat[4][6] = {
2480 { 0x00005555, 0x00000005, 0x00002aaa, 0x0000000a, 0x00003456, 0x00000003 },
2481 { 0x00002aaa, 0x0000000a, 0x00003333, 0x00000003, 0x0000789a, 0x00000005 },
2482 { 0x00005a5a, 0x00000005, 0x00002a6a, 0x0000000a, 0x00001bcd, 0x00000003 },
2483 { 0x00002a5a, 0x0000000a, 0x000033c3, 0x00000003, 0x00002ef1, 0x00000005 }
2487 for (chan = 0; chan < 4; chan++) {
2490 tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
2491 (chan * 0x2000) | 0x0200);
2492 tg3_writephy(tp, MII_TG3_DSP_CONTROL, 0x0002);
2494 for (i = 0; i < 6; i++)
2495 tg3_writephy(tp, MII_TG3_DSP_RW_PORT,
2498 tg3_writephy(tp, MII_TG3_DSP_CONTROL, 0x0202);
2499 if (tg3_wait_macro_done(tp)) {
2504 tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
2505 (chan * 0x2000) | 0x0200);
2506 tg3_writephy(tp, MII_TG3_DSP_CONTROL, 0x0082);
2507 if (tg3_wait_macro_done(tp)) {
2512 tg3_writephy(tp, MII_TG3_DSP_CONTROL, 0x0802);
2513 if (tg3_wait_macro_done(tp)) {
2518 for (i = 0; i < 6; i += 2) {
2521 if (tg3_readphy(tp, MII_TG3_DSP_RW_PORT, &low) ||
2522 tg3_readphy(tp, MII_TG3_DSP_RW_PORT, &high) ||
2523 tg3_wait_macro_done(tp)) {
2529 if (low != test_pat[chan][i] ||
2530 high != test_pat[chan][i+1]) {
2531 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x000b);
2532 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x4001);
2533 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x4005);
2543 static int tg3_phy_reset_chanpat(struct tg3 *tp)
2547 for (chan = 0; chan < 4; chan++) {
2550 tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
2551 (chan * 0x2000) | 0x0200);
2552 tg3_writephy(tp, MII_TG3_DSP_CONTROL, 0x0002);
2553 for (i = 0; i < 6; i++)
2554 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x000);
2555 tg3_writephy(tp, MII_TG3_DSP_CONTROL, 0x0202);
2556 if (tg3_wait_macro_done(tp))
2563 static int tg3_phy_reset_5703_4_5(struct tg3 *tp)
2565 u32 reg32, phy9_orig;
2566 int retries, do_phy_reset, err;
2572 err = tg3_bmcr_reset(tp);
2578 /* Disable transmitter and interrupt. */
2579 if (tg3_readphy(tp, MII_TG3_EXT_CTRL, ®32))
2583 tg3_writephy(tp, MII_TG3_EXT_CTRL, reg32);
2585 /* Set full-duplex, 1000 mbps. */
2586 tg3_writephy(tp, MII_BMCR,
2587 BMCR_FULLDPLX | BMCR_SPEED1000);
2589 /* Set to master mode. */
2590 if (tg3_readphy(tp, MII_CTRL1000, &phy9_orig))
2593 tg3_writephy(tp, MII_CTRL1000,
2594 CTL1000_AS_MASTER | CTL1000_ENABLE_MASTER);
2596 err = tg3_phy_toggle_auxctl_smdsp(tp, true);
2600 /* Block the PHY control access. */
2601 tg3_phydsp_write(tp, 0x8005, 0x0800);
2603 err = tg3_phy_write_and_check_testpat(tp, &do_phy_reset);
2606 } while (--retries);
2608 err = tg3_phy_reset_chanpat(tp);
2612 tg3_phydsp_write(tp, 0x8005, 0x0000);
2614 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8200);
2615 tg3_writephy(tp, MII_TG3_DSP_CONTROL, 0x0000);
2617 tg3_phy_toggle_auxctl_smdsp(tp, false);
2619 tg3_writephy(tp, MII_CTRL1000, phy9_orig);
2621 err = tg3_readphy(tp, MII_TG3_EXT_CTRL, ®32);
2626 tg3_writephy(tp, MII_TG3_EXT_CTRL, reg32);
2631 static void tg3_carrier_off(struct tg3 *tp)
2633 netif_carrier_off(tp->dev);
2634 tp->link_up = false;
2637 static void tg3_warn_mgmt_link_flap(struct tg3 *tp)
2639 if (tg3_flag(tp, ENABLE_ASF))
2640 netdev_warn(tp->dev,
2641 "Management side-band traffic will be interrupted during phy settings change\n");
2644 /* This will reset the tigon3 PHY if there is no valid
2645 * link unless the FORCE argument is non-zero.
2647 static int tg3_phy_reset(struct tg3 *tp)
2652 if (tg3_asic_rev(tp) == ASIC_REV_5906) {
2653 val = tr32(GRC_MISC_CFG);
2654 tw32_f(GRC_MISC_CFG, val & ~GRC_MISC_CFG_EPHY_IDDQ);
2657 err = tg3_readphy(tp, MII_BMSR, &val);
2658 err |= tg3_readphy(tp, MII_BMSR, &val);
2662 if (netif_running(tp->dev) && tp->link_up) {
2663 netif_carrier_off(tp->dev);
2664 tg3_link_report(tp);
2667 if (tg3_asic_rev(tp) == ASIC_REV_5703 ||
2668 tg3_asic_rev(tp) == ASIC_REV_5704 ||
2669 tg3_asic_rev(tp) == ASIC_REV_5705) {
2670 err = tg3_phy_reset_5703_4_5(tp);
2677 if (tg3_asic_rev(tp) == ASIC_REV_5784 &&
2678 tg3_chip_rev(tp) != CHIPREV_5784_AX) {
2679 cpmuctrl = tr32(TG3_CPMU_CTRL);
2680 if (cpmuctrl & CPMU_CTRL_GPHY_10MB_RXONLY)
2682 cpmuctrl & ~CPMU_CTRL_GPHY_10MB_RXONLY);
2685 err = tg3_bmcr_reset(tp);
2689 if (cpmuctrl & CPMU_CTRL_GPHY_10MB_RXONLY) {
2690 val = MII_TG3_DSP_EXP8_AEDW | MII_TG3_DSP_EXP8_REJ2MHz;
2691 tg3_phydsp_write(tp, MII_TG3_DSP_EXP8, val);
2693 tw32(TG3_CPMU_CTRL, cpmuctrl);
2696 if (tg3_chip_rev(tp) == CHIPREV_5784_AX ||
2697 tg3_chip_rev(tp) == CHIPREV_5761_AX) {
2698 val = tr32(TG3_CPMU_LSPD_1000MB_CLK);
2699 if ((val & CPMU_LSPD_1000MB_MACCLK_MASK) ==
2700 CPMU_LSPD_1000MB_MACCLK_12_5) {
2701 val &= ~CPMU_LSPD_1000MB_MACCLK_MASK;
2703 tw32_f(TG3_CPMU_LSPD_1000MB_CLK, val);
2707 if (tg3_flag(tp, 5717_PLUS) &&
2708 (tp->phy_flags & TG3_PHYFLG_MII_SERDES))
2711 tg3_phy_apply_otp(tp);
2713 if (tp->phy_flags & TG3_PHYFLG_ENABLE_APD)
2714 tg3_phy_toggle_apd(tp, true);
2716 tg3_phy_toggle_apd(tp, false);
2719 if ((tp->phy_flags & TG3_PHYFLG_ADC_BUG) &&
2720 !tg3_phy_toggle_auxctl_smdsp(tp, true)) {
2721 tg3_phydsp_write(tp, 0x201f, 0x2aaa);
2722 tg3_phydsp_write(tp, 0x000a, 0x0323);
2723 tg3_phy_toggle_auxctl_smdsp(tp, false);
2726 if (tp->phy_flags & TG3_PHYFLG_5704_A0_BUG) {
2727 tg3_writephy(tp, MII_TG3_MISC_SHDW, 0x8d68);
2728 tg3_writephy(tp, MII_TG3_MISC_SHDW, 0x8d68);
2731 if (tp->phy_flags & TG3_PHYFLG_BER_BUG) {
2732 if (!tg3_phy_toggle_auxctl_smdsp(tp, true)) {
2733 tg3_phydsp_write(tp, 0x000a, 0x310b);
2734 tg3_phydsp_write(tp, 0x201f, 0x9506);
2735 tg3_phydsp_write(tp, 0x401f, 0x14e2);
2736 tg3_phy_toggle_auxctl_smdsp(tp, false);
2738 } else if (tp->phy_flags & TG3_PHYFLG_JITTER_BUG) {
2739 if (!tg3_phy_toggle_auxctl_smdsp(tp, true)) {
2740 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x000a);
2741 if (tp->phy_flags & TG3_PHYFLG_ADJUST_TRIM) {
2742 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x110b);
2743 tg3_writephy(tp, MII_TG3_TEST1,
2744 MII_TG3_TEST1_TRIM_EN | 0x4);
2746 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x010b);
2748 tg3_phy_toggle_auxctl_smdsp(tp, false);
2752 /* Set Extended packet length bit (bit 14) on all chips that */
2753 /* support jumbo frames */
2754 if ((tp->phy_id & TG3_PHY_ID_MASK) == TG3_PHY_ID_BCM5401) {
2755 /* Cannot do read-modify-write on 5401 */
2756 tg3_phy_auxctl_write(tp, MII_TG3_AUXCTL_SHDWSEL_AUXCTL, 0x4c20);
2757 } else if (tg3_flag(tp, JUMBO_CAPABLE)) {
2758 /* Set bit 14 with read-modify-write to preserve other bits */
2759 err = tg3_phy_auxctl_read(tp,
2760 MII_TG3_AUXCTL_SHDWSEL_AUXCTL, &val);
2762 tg3_phy_auxctl_write(tp, MII_TG3_AUXCTL_SHDWSEL_AUXCTL,
2763 val | MII_TG3_AUXCTL_ACTL_EXTPKTLEN);
2766 /* Set phy register 0x10 bit 0 to high fifo elasticity to support
2767 * jumbo frames transmission.
2769 if (tg3_flag(tp, JUMBO_CAPABLE)) {
2770 if (!tg3_readphy(tp, MII_TG3_EXT_CTRL, &val))
2771 tg3_writephy(tp, MII_TG3_EXT_CTRL,
2772 val | MII_TG3_EXT_CTRL_FIFO_ELASTIC);
2775 if (tg3_asic_rev(tp) == ASIC_REV_5906) {
2776 /* adjust output voltage */
2777 tg3_writephy(tp, MII_TG3_FET_PTEST, 0x12);
2780 if (tg3_chip_rev_id(tp) == CHIPREV_ID_5762_A0)
2781 tg3_phydsp_write(tp, 0xffb, 0x4000);
2783 tg3_phy_toggle_automdix(tp, true);
2784 tg3_phy_set_wirespeed(tp);
2788 #define TG3_GPIO_MSG_DRVR_PRES 0x00000001
2789 #define TG3_GPIO_MSG_NEED_VAUX 0x00000002
2790 #define TG3_GPIO_MSG_MASK (TG3_GPIO_MSG_DRVR_PRES | \
2791 TG3_GPIO_MSG_NEED_VAUX)
2792 #define TG3_GPIO_MSG_ALL_DRVR_PRES_MASK \
2793 ((TG3_GPIO_MSG_DRVR_PRES << 0) | \
2794 (TG3_GPIO_MSG_DRVR_PRES << 4) | \
2795 (TG3_GPIO_MSG_DRVR_PRES << 8) | \
2796 (TG3_GPIO_MSG_DRVR_PRES << 12))
2798 #define TG3_GPIO_MSG_ALL_NEED_VAUX_MASK \
2799 ((TG3_GPIO_MSG_NEED_VAUX << 0) | \
2800 (TG3_GPIO_MSG_NEED_VAUX << 4) | \
2801 (TG3_GPIO_MSG_NEED_VAUX << 8) | \
2802 (TG3_GPIO_MSG_NEED_VAUX << 12))
2804 static inline u32 tg3_set_function_status(struct tg3 *tp, u32 newstat)
2808 if (tg3_asic_rev(tp) == ASIC_REV_5717 ||
2809 tg3_asic_rev(tp) == ASIC_REV_5719)
2810 status = tg3_ape_read32(tp, TG3_APE_GPIO_MSG);
2812 status = tr32(TG3_CPMU_DRV_STATUS);
2814 shift = TG3_APE_GPIO_MSG_SHIFT + 4 * tp->pci_fn;
2815 status &= ~(TG3_GPIO_MSG_MASK << shift);
2816 status |= (newstat << shift);
2818 if (tg3_asic_rev(tp) == ASIC_REV_5717 ||
2819 tg3_asic_rev(tp) == ASIC_REV_5719)
2820 tg3_ape_write32(tp, TG3_APE_GPIO_MSG, status);
2822 tw32(TG3_CPMU_DRV_STATUS, status);
2824 return status >> TG3_APE_GPIO_MSG_SHIFT;
2827 static inline int tg3_pwrsrc_switch_to_vmain(struct tg3 *tp)
2829 if (!tg3_flag(tp, IS_NIC))
2832 if (tg3_asic_rev(tp) == ASIC_REV_5717 ||
2833 tg3_asic_rev(tp) == ASIC_REV_5719 ||
2834 tg3_asic_rev(tp) == ASIC_REV_5720) {
2835 if (tg3_ape_lock(tp, TG3_APE_LOCK_GPIO))
2838 tg3_set_function_status(tp, TG3_GPIO_MSG_DRVR_PRES);
2840 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl,
2841 TG3_GRC_LCLCTL_PWRSW_DELAY);
2843 tg3_ape_unlock(tp, TG3_APE_LOCK_GPIO);
2845 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl,
2846 TG3_GRC_LCLCTL_PWRSW_DELAY);
2852 static void tg3_pwrsrc_die_with_vmain(struct tg3 *tp)
2856 if (!tg3_flag(tp, IS_NIC) ||
2857 tg3_asic_rev(tp) == ASIC_REV_5700 ||
2858 tg3_asic_rev(tp) == ASIC_REV_5701)
2861 grc_local_ctrl = tp->grc_local_ctrl | GRC_LCLCTRL_GPIO_OE1;
2863 tw32_wait_f(GRC_LOCAL_CTRL,
2864 grc_local_ctrl | GRC_LCLCTRL_GPIO_OUTPUT1,
2865 TG3_GRC_LCLCTL_PWRSW_DELAY);
2867 tw32_wait_f(GRC_LOCAL_CTRL,
2869 TG3_GRC_LCLCTL_PWRSW_DELAY);
2871 tw32_wait_f(GRC_LOCAL_CTRL,
2872 grc_local_ctrl | GRC_LCLCTRL_GPIO_OUTPUT1,
2873 TG3_GRC_LCLCTL_PWRSW_DELAY);
2876 static void tg3_pwrsrc_switch_to_vaux(struct tg3 *tp)
2878 if (!tg3_flag(tp, IS_NIC))
2881 if (tg3_asic_rev(tp) == ASIC_REV_5700 ||
2882 tg3_asic_rev(tp) == ASIC_REV_5701) {
2883 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2884 (GRC_LCLCTRL_GPIO_OE0 |
2885 GRC_LCLCTRL_GPIO_OE1 |
2886 GRC_LCLCTRL_GPIO_OE2 |
2887 GRC_LCLCTRL_GPIO_OUTPUT0 |
2888 GRC_LCLCTRL_GPIO_OUTPUT1),
2889 TG3_GRC_LCLCTL_PWRSW_DELAY);
2890 } else if (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5761 ||
2891 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5761S) {
2892 /* The 5761 non-e device swaps GPIO 0 and GPIO 2. */
2893 u32 grc_local_ctrl = GRC_LCLCTRL_GPIO_OE0 |
2894 GRC_LCLCTRL_GPIO_OE1 |
2895 GRC_LCLCTRL_GPIO_OE2 |
2896 GRC_LCLCTRL_GPIO_OUTPUT0 |
2897 GRC_LCLCTRL_GPIO_OUTPUT1 |
2899 tw32_wait_f(GRC_LOCAL_CTRL, grc_local_ctrl,
2900 TG3_GRC_LCLCTL_PWRSW_DELAY);
2902 grc_local_ctrl |= GRC_LCLCTRL_GPIO_OUTPUT2;
2903 tw32_wait_f(GRC_LOCAL_CTRL, grc_local_ctrl,
2904 TG3_GRC_LCLCTL_PWRSW_DELAY);
2906 grc_local_ctrl &= ~GRC_LCLCTRL_GPIO_OUTPUT0;
2907 tw32_wait_f(GRC_LOCAL_CTRL, grc_local_ctrl,
2908 TG3_GRC_LCLCTL_PWRSW_DELAY);
2911 u32 grc_local_ctrl = 0;
2913 /* Workaround to prevent overdrawing Amps. */
2914 if (tg3_asic_rev(tp) == ASIC_REV_5714) {
2915 grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE3;
2916 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2918 TG3_GRC_LCLCTL_PWRSW_DELAY);
2921 /* On 5753 and variants, GPIO2 cannot be used. */
2922 no_gpio2 = tp->nic_sram_data_cfg &
2923 NIC_SRAM_DATA_CFG_NO_GPIO2;
2925 grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE0 |
2926 GRC_LCLCTRL_GPIO_OE1 |
2927 GRC_LCLCTRL_GPIO_OE2 |
2928 GRC_LCLCTRL_GPIO_OUTPUT1 |
2929 GRC_LCLCTRL_GPIO_OUTPUT2;
2931 grc_local_ctrl &= ~(GRC_LCLCTRL_GPIO_OE2 |
2932 GRC_LCLCTRL_GPIO_OUTPUT2);
2934 tw32_wait_f(GRC_LOCAL_CTRL,
2935 tp->grc_local_ctrl | grc_local_ctrl,
2936 TG3_GRC_LCLCTL_PWRSW_DELAY);
2938 grc_local_ctrl |= GRC_LCLCTRL_GPIO_OUTPUT0;
2940 tw32_wait_f(GRC_LOCAL_CTRL,
2941 tp->grc_local_ctrl | grc_local_ctrl,
2942 TG3_GRC_LCLCTL_PWRSW_DELAY);
2945 grc_local_ctrl &= ~GRC_LCLCTRL_GPIO_OUTPUT2;
2946 tw32_wait_f(GRC_LOCAL_CTRL,
2947 tp->grc_local_ctrl | grc_local_ctrl,
2948 TG3_GRC_LCLCTL_PWRSW_DELAY);
2953 static void tg3_frob_aux_power_5717(struct tg3 *tp, bool wol_enable)
2957 /* Serialize power state transitions */
2958 if (tg3_ape_lock(tp, TG3_APE_LOCK_GPIO))
2961 if (tg3_flag(tp, ENABLE_ASF) || tg3_flag(tp, ENABLE_APE) || wol_enable)
2962 msg = TG3_GPIO_MSG_NEED_VAUX;
2964 msg = tg3_set_function_status(tp, msg);
2966 if (msg & TG3_GPIO_MSG_ALL_DRVR_PRES_MASK)
2969 if (msg & TG3_GPIO_MSG_ALL_NEED_VAUX_MASK)
2970 tg3_pwrsrc_switch_to_vaux(tp);
2972 tg3_pwrsrc_die_with_vmain(tp);
2975 tg3_ape_unlock(tp, TG3_APE_LOCK_GPIO);
2978 static void tg3_frob_aux_power(struct tg3 *tp, bool include_wol)
2980 bool need_vaux = false;
2982 /* The GPIOs do something completely different on 57765. */
2983 if (!tg3_flag(tp, IS_NIC) || tg3_flag(tp, 57765_CLASS))
2986 if (tg3_asic_rev(tp) == ASIC_REV_5717 ||
2987 tg3_asic_rev(tp) == ASIC_REV_5719 ||
2988 tg3_asic_rev(tp) == ASIC_REV_5720) {
2989 tg3_frob_aux_power_5717(tp, include_wol ?
2990 tg3_flag(tp, WOL_ENABLE) != 0 : 0);
2994 if (tp->pdev_peer && tp->pdev_peer != tp->pdev) {
2995 struct net_device *dev_peer;
2997 dev_peer = pci_get_drvdata(tp->pdev_peer);
2999 /* remove_one() may have been run on the peer. */
3001 struct tg3 *tp_peer = netdev_priv(dev_peer);
3003 if (tg3_flag(tp_peer, INIT_COMPLETE))
3006 if ((include_wol && tg3_flag(tp_peer, WOL_ENABLE)) ||
3007 tg3_flag(tp_peer, ENABLE_ASF))
3012 if ((include_wol && tg3_flag(tp, WOL_ENABLE)) ||
3013 tg3_flag(tp, ENABLE_ASF))
3017 tg3_pwrsrc_switch_to_vaux(tp);
3019 tg3_pwrsrc_die_with_vmain(tp);
3022 static int tg3_5700_link_polarity(struct tg3 *tp, u32 speed)
3024 if (tp->led_ctrl == LED_CTRL_MODE_PHY_2)
3026 else if ((tp->phy_id & TG3_PHY_ID_MASK) == TG3_PHY_ID_BCM5411) {
3027 if (speed != SPEED_10)
3029 } else if (speed == SPEED_10)
3035 static bool tg3_phy_power_bug(struct tg3 *tp)
3037 switch (tg3_asic_rev(tp)) {
3042 if (tp->phy_flags & TG3_PHYFLG_MII_SERDES)
3051 if ((tp->phy_flags & TG3_PHYFLG_PHY_SERDES) &&
3060 static bool tg3_phy_led_bug(struct tg3 *tp)
3062 switch (tg3_asic_rev(tp)) {
3065 if ((tp->phy_flags & TG3_PHYFLG_MII_SERDES) &&
3074 static void tg3_power_down_phy(struct tg3 *tp, bool do_low_power)
3078 if (tp->phy_flags & TG3_PHYFLG_KEEP_LINK_ON_PWRDN)
3081 if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES) {
3082 if (tg3_asic_rev(tp) == ASIC_REV_5704) {
3083 u32 sg_dig_ctrl = tr32(SG_DIG_CTRL);
3084 u32 serdes_cfg = tr32(MAC_SERDES_CFG);
3087 SG_DIG_USING_HW_AUTONEG | SG_DIG_SOFT_RESET;
3088 tw32(SG_DIG_CTRL, sg_dig_ctrl);
3089 tw32(MAC_SERDES_CFG, serdes_cfg | (1 << 15));
3094 if (tg3_asic_rev(tp) == ASIC_REV_5906) {
3096 val = tr32(GRC_MISC_CFG);
3097 tw32_f(GRC_MISC_CFG, val | GRC_MISC_CFG_EPHY_IDDQ);
3100 } else if (tp->phy_flags & TG3_PHYFLG_IS_FET) {
3102 if (!tg3_readphy(tp, MII_TG3_FET_TEST, &phytest)) {
3105 tg3_writephy(tp, MII_ADVERTISE, 0);
3106 tg3_writephy(tp, MII_BMCR,
3107 BMCR_ANENABLE | BMCR_ANRESTART);
3109 tg3_writephy(tp, MII_TG3_FET_TEST,
3110 phytest | MII_TG3_FET_SHADOW_EN);
3111 if (!tg3_readphy(tp, MII_TG3_FET_SHDW_AUXMODE4, &phy)) {
3112 phy |= MII_TG3_FET_SHDW_AUXMODE4_SBPD;
3114 MII_TG3_FET_SHDW_AUXMODE4,
3117 tg3_writephy(tp, MII_TG3_FET_TEST, phytest);
3120 } else if (do_low_power) {
3121 if (!tg3_phy_led_bug(tp))
3122 tg3_writephy(tp, MII_TG3_EXT_CTRL,
3123 MII_TG3_EXT_CTRL_FORCE_LED_OFF);
3125 val = MII_TG3_AUXCTL_PCTL_100TX_LPWR |
3126 MII_TG3_AUXCTL_PCTL_SPR_ISOLATE |
3127 MII_TG3_AUXCTL_PCTL_VREG_11V;
3128 tg3_phy_auxctl_write(tp, MII_TG3_AUXCTL_SHDWSEL_PWRCTL, val);
3131 /* The PHY should not be powered down on some chips because
3134 if (tg3_phy_power_bug(tp))
3137 if (tg3_chip_rev(tp) == CHIPREV_5784_AX ||
3138 tg3_chip_rev(tp) == CHIPREV_5761_AX) {
3139 val = tr32(TG3_CPMU_LSPD_1000MB_CLK);
3140 val &= ~CPMU_LSPD_1000MB_MACCLK_MASK;
3141 val |= CPMU_LSPD_1000MB_MACCLK_12_5;
3142 tw32_f(TG3_CPMU_LSPD_1000MB_CLK, val);
3145 tg3_writephy(tp, MII_BMCR, BMCR_PDOWN);
3148 /* tp->lock is held. */
3149 static int tg3_nvram_lock(struct tg3 *tp)
3151 if (tg3_flag(tp, NVRAM)) {
3154 if (tp->nvram_lock_cnt == 0) {
3155 tw32(NVRAM_SWARB, SWARB_REQ_SET1);
3156 for (i = 0; i < 8000; i++) {
3157 if (tr32(NVRAM_SWARB) & SWARB_GNT1)
3162 tw32(NVRAM_SWARB, SWARB_REQ_CLR1);
3166 tp->nvram_lock_cnt++;
3171 /* tp->lock is held. */
3172 static void tg3_nvram_unlock(struct tg3 *tp)
3174 if (tg3_flag(tp, NVRAM)) {
3175 if (tp->nvram_lock_cnt > 0)
3176 tp->nvram_lock_cnt--;
3177 if (tp->nvram_lock_cnt == 0)
3178 tw32_f(NVRAM_SWARB, SWARB_REQ_CLR1);
3182 /* tp->lock is held. */
3183 static void tg3_enable_nvram_access(struct tg3 *tp)
3185 if (tg3_flag(tp, 5750_PLUS) && !tg3_flag(tp, PROTECTED_NVRAM)) {
3186 u32 nvaccess = tr32(NVRAM_ACCESS);
3188 tw32(NVRAM_ACCESS, nvaccess | ACCESS_ENABLE);
3192 /* tp->lock is held. */
3193 static void tg3_disable_nvram_access(struct tg3 *tp)
3195 if (tg3_flag(tp, 5750_PLUS) && !tg3_flag(tp, PROTECTED_NVRAM)) {
3196 u32 nvaccess = tr32(NVRAM_ACCESS);
3198 tw32(NVRAM_ACCESS, nvaccess & ~ACCESS_ENABLE);
3202 static int tg3_nvram_read_using_eeprom(struct tg3 *tp,
3203 u32 offset, u32 *val)
3208 if (offset > EEPROM_ADDR_ADDR_MASK || (offset % 4) != 0)
3211 tmp = tr32(GRC_EEPROM_ADDR) & ~(EEPROM_ADDR_ADDR_MASK |
3212 EEPROM_ADDR_DEVID_MASK |
3214 tw32(GRC_EEPROM_ADDR,
3216 (0 << EEPROM_ADDR_DEVID_SHIFT) |
3217 ((offset << EEPROM_ADDR_ADDR_SHIFT) &
3218 EEPROM_ADDR_ADDR_MASK) |
3219 EEPROM_ADDR_READ | EEPROM_ADDR_START);
3221 for (i = 0; i < 1000; i++) {
3222 tmp = tr32(GRC_EEPROM_ADDR);
3224 if (tmp & EEPROM_ADDR_COMPLETE)
3228 if (!(tmp & EEPROM_ADDR_COMPLETE))
3231 tmp = tr32(GRC_EEPROM_DATA);
3234 * The data will always be opposite the native endian
3235 * format. Perform a blind byteswap to compensate.
3242 #define NVRAM_CMD_TIMEOUT 10000
3244 static int tg3_nvram_exec_cmd(struct tg3 *tp, u32 nvram_cmd)
3248 tw32(NVRAM_CMD, nvram_cmd);
3249 for (i = 0; i < NVRAM_CMD_TIMEOUT; i++) {
3250 usleep_range(10, 40);
3251 if (tr32(NVRAM_CMD) & NVRAM_CMD_DONE) {
3257 if (i == NVRAM_CMD_TIMEOUT)
3263 static u32 tg3_nvram_phys_addr(struct tg3 *tp, u32 addr)
3265 if (tg3_flag(tp, NVRAM) &&
3266 tg3_flag(tp, NVRAM_BUFFERED) &&
3267 tg3_flag(tp, FLASH) &&
3268 !tg3_flag(tp, NO_NVRAM_ADDR_TRANS) &&
3269 (tp->nvram_jedecnum == JEDEC_ATMEL))
3271 addr = ((addr / tp->nvram_pagesize) <<
3272 ATMEL_AT45DB0X1B_PAGE_POS) +
3273 (addr % tp->nvram_pagesize);
3278 static u32 tg3_nvram_logical_addr(struct tg3 *tp, u32 addr)
3280 if (tg3_flag(tp, NVRAM) &&
3281 tg3_flag(tp, NVRAM_BUFFERED) &&
3282 tg3_flag(tp, FLASH) &&
3283 !tg3_flag(tp, NO_NVRAM_ADDR_TRANS) &&
3284 (tp->nvram_jedecnum == JEDEC_ATMEL))
3286 addr = ((addr >> ATMEL_AT45DB0X1B_PAGE_POS) *
3287 tp->nvram_pagesize) +
3288 (addr & ((1 << ATMEL_AT45DB0X1B_PAGE_POS) - 1));
3293 /* NOTE: Data read in from NVRAM is byteswapped according to
3294 * the byteswapping settings for all other register accesses.
3295 * tg3 devices are BE devices, so on a BE machine, the data
3296 * returned will be exactly as it is seen in NVRAM. On a LE
3297 * machine, the 32-bit value will be byteswapped.
3299 static int tg3_nvram_read(struct tg3 *tp, u32 offset, u32 *val)
3303 if (!tg3_flag(tp, NVRAM))
3304 return tg3_nvram_read_using_eeprom(tp, offset, val);
3306 offset = tg3_nvram_phys_addr(tp, offset);
3308 if (offset > NVRAM_ADDR_MSK)
3311 ret = tg3_nvram_lock(tp);
3315 tg3_enable_nvram_access(tp);
3317 tw32(NVRAM_ADDR, offset);
3318 ret = tg3_nvram_exec_cmd(tp, NVRAM_CMD_RD | NVRAM_CMD_GO |
3319 NVRAM_CMD_FIRST | NVRAM_CMD_LAST | NVRAM_CMD_DONE);
3322 *val = tr32(NVRAM_RDDATA);
3324 tg3_disable_nvram_access(tp);
3326 tg3_nvram_unlock(tp);
3331 /* Ensures NVRAM data is in bytestream format. */
3332 static int tg3_nvram_read_be32(struct tg3 *tp, u32 offset, __be32 *val)
3335 int res = tg3_nvram_read(tp, offset, &v);
3337 *val = cpu_to_be32(v);
3341 static int tg3_nvram_write_block_using_eeprom(struct tg3 *tp,
3342 u32 offset, u32 len, u8 *buf)
3347 for (i = 0; i < len; i += 4) {
3353 memcpy(&data, buf + i, 4);
3356 * The SEEPROM interface expects the data to always be opposite
3357 * the native endian format. We accomplish this by reversing
3358 * all the operations that would have been performed on the
3359 * data from a call to tg3_nvram_read_be32().
3361 tw32(GRC_EEPROM_DATA, swab32(be32_to_cpu(data)));
3363 val = tr32(GRC_EEPROM_ADDR);
3364 tw32(GRC_EEPROM_ADDR, val | EEPROM_ADDR_COMPLETE);
3366 val &= ~(EEPROM_ADDR_ADDR_MASK | EEPROM_ADDR_DEVID_MASK |
3368 tw32(GRC_EEPROM_ADDR, val |
3369 (0 << EEPROM_ADDR_DEVID_SHIFT) |
3370 (addr & EEPROM_ADDR_ADDR_MASK) |
3374 for (j = 0; j < 1000; j++) {
3375 val = tr32(GRC_EEPROM_ADDR);
3377 if (val & EEPROM_ADDR_COMPLETE)
3381 if (!(val & EEPROM_ADDR_COMPLETE)) {
3390 /* offset and length are dword aligned */
3391 static int tg3_nvram_write_block_unbuffered(struct tg3 *tp, u32 offset, u32 len,
3395 u32 pagesize = tp->nvram_pagesize;
3396 u32 pagemask = pagesize - 1;
3400 tmp = kmalloc(pagesize, GFP_KERNEL);
3406 u32 phy_addr, page_off, size;
3408 phy_addr = offset & ~pagemask;
3410 for (j = 0; j < pagesize; j += 4) {
3411 ret = tg3_nvram_read_be32(tp, phy_addr + j,
3412 (__be32 *) (tmp + j));
3419 page_off = offset & pagemask;
3426 memcpy(tmp + page_off, buf, size);
3428 offset = offset + (pagesize - page_off);
3430 tg3_enable_nvram_access(tp);
3433 * Before we can erase the flash page, we need
3434 * to issue a special "write enable" command.
3436 nvram_cmd = NVRAM_CMD_WREN | NVRAM_CMD_GO | NVRAM_CMD_DONE;
3438 if (tg3_nvram_exec_cmd(tp, nvram_cmd))
3441 /* Erase the target page */
3442 tw32(NVRAM_ADDR, phy_addr);
3444 nvram_cmd = NVRAM_CMD_GO | NVRAM_CMD_DONE | NVRAM_CMD_WR |
3445 NVRAM_CMD_FIRST | NVRAM_CMD_LAST | NVRAM_CMD_ERASE;
3447 if (tg3_nvram_exec_cmd(tp, nvram_cmd))
3450 /* Issue another write enable to start the write. */
3451 nvram_cmd = NVRAM_CMD_WREN | NVRAM_CMD_GO | NVRAM_CMD_DONE;
3453 if (tg3_nvram_exec_cmd(tp, nvram_cmd))
3456 for (j = 0; j < pagesize; j += 4) {
3459 data = *((__be32 *) (tmp + j));
3461 tw32(NVRAM_WRDATA, be32_to_cpu(data));
3463 tw32(NVRAM_ADDR, phy_addr + j);
3465 nvram_cmd = NVRAM_CMD_GO | NVRAM_CMD_DONE |
3469 nvram_cmd |= NVRAM_CMD_FIRST;
3470 else if (j == (pagesize - 4))
3471 nvram_cmd |= NVRAM_CMD_LAST;
3473 ret = tg3_nvram_exec_cmd(tp, nvram_cmd);
3481 nvram_cmd = NVRAM_CMD_WRDI | NVRAM_CMD_GO | NVRAM_CMD_DONE;
3482 tg3_nvram_exec_cmd(tp, nvram_cmd);
3489 /* offset and length are dword aligned */
3490 static int tg3_nvram_write_block_buffered(struct tg3 *tp, u32 offset, u32 len,
3495 for (i = 0; i < len; i += 4, offset += 4) {
3496 u32 page_off, phy_addr, nvram_cmd;
3499 memcpy(&data, buf + i, 4);
3500 tw32(NVRAM_WRDATA, be32_to_cpu(data));
3502 page_off = offset % tp->nvram_pagesize;
3504 phy_addr = tg3_nvram_phys_addr(tp, offset);
3506 nvram_cmd = NVRAM_CMD_GO | NVRAM_CMD_DONE | NVRAM_CMD_WR;
3508 if (page_off == 0 || i == 0)
3509 nvram_cmd |= NVRAM_CMD_FIRST;
3510 if (page_off == (tp->nvram_pagesize - 4))
3511 nvram_cmd |= NVRAM_CMD_LAST;
3514 nvram_cmd |= NVRAM_CMD_LAST;
3516 if ((nvram_cmd & NVRAM_CMD_FIRST) ||
3517 !tg3_flag(tp, FLASH) ||
3518 !tg3_flag(tp, 57765_PLUS))
3519 tw32(NVRAM_ADDR, phy_addr);
3521 if (tg3_asic_rev(tp) != ASIC_REV_5752 &&
3522 !tg3_flag(tp, 5755_PLUS) &&
3523 (tp->nvram_jedecnum == JEDEC_ST) &&
3524 (nvram_cmd & NVRAM_CMD_FIRST)) {
3527 cmd = NVRAM_CMD_WREN | NVRAM_CMD_GO | NVRAM_CMD_DONE;
3528 ret = tg3_nvram_exec_cmd(tp, cmd);
3532 if (!tg3_flag(tp, FLASH)) {
3533 /* We always do complete word writes to eeprom. */
3534 nvram_cmd |= (NVRAM_CMD_FIRST | NVRAM_CMD_LAST);
3537 ret = tg3_nvram_exec_cmd(tp, nvram_cmd);
3544 /* offset and length are dword aligned */
3545 static int tg3_nvram_write_block(struct tg3 *tp, u32 offset, u32 len, u8 *buf)
3549 if (tg3_flag(tp, EEPROM_WRITE_PROT)) {
3550 tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl &
3551 ~GRC_LCLCTRL_GPIO_OUTPUT1);
3555 if (!tg3_flag(tp, NVRAM)) {
3556 ret = tg3_nvram_write_block_using_eeprom(tp, offset, len, buf);
3560 ret = tg3_nvram_lock(tp);
3564 tg3_enable_nvram_access(tp);
3565 if (tg3_flag(tp, 5750_PLUS) && !tg3_flag(tp, PROTECTED_NVRAM))
3566 tw32(NVRAM_WRITE1, 0x406);
3568 grc_mode = tr32(GRC_MODE);
3569 tw32(GRC_MODE, grc_mode | GRC_MODE_NVRAM_WR_ENABLE);
3571 if (tg3_flag(tp, NVRAM_BUFFERED) || !tg3_flag(tp, FLASH)) {
3572 ret = tg3_nvram_write_block_buffered(tp, offset, len,
3575 ret = tg3_nvram_write_block_unbuffered(tp, offset, len,
3579 grc_mode = tr32(GRC_MODE);
3580 tw32(GRC_MODE, grc_mode & ~GRC_MODE_NVRAM_WR_ENABLE);
3582 tg3_disable_nvram_access(tp);
3583 tg3_nvram_unlock(tp);
3586 if (tg3_flag(tp, EEPROM_WRITE_PROT)) {
3587 tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl);
3594 #define RX_CPU_SCRATCH_BASE 0x30000
3595 #define RX_CPU_SCRATCH_SIZE 0x04000
3596 #define TX_CPU_SCRATCH_BASE 0x34000
3597 #define TX_CPU_SCRATCH_SIZE 0x04000
3599 /* tp->lock is held. */
3600 static int tg3_pause_cpu(struct tg3 *tp, u32 cpu_base)
3603 const int iters = 10000;
3605 for (i = 0; i < iters; i++) {
3606 tw32(cpu_base + CPU_STATE, 0xffffffff);
3607 tw32(cpu_base + CPU_MODE, CPU_MODE_HALT);
3608 if (tr32(cpu_base + CPU_MODE) & CPU_MODE_HALT)
3610 if (pci_channel_offline(tp->pdev))
3614 return (i == iters) ? -EBUSY : 0;
3617 /* tp->lock is held. */
3618 static int tg3_rxcpu_pause(struct tg3 *tp)
3620 int rc = tg3_pause_cpu(tp, RX_CPU_BASE);
3622 tw32(RX_CPU_BASE + CPU_STATE, 0xffffffff);
3623 tw32_f(RX_CPU_BASE + CPU_MODE, CPU_MODE_HALT);
3629 /* tp->lock is held. */
3630 static int tg3_txcpu_pause(struct tg3 *tp)
3632 return tg3_pause_cpu(tp, TX_CPU_BASE);
3635 /* tp->lock is held. */
3636 static void tg3_resume_cpu(struct tg3 *tp, u32 cpu_base)
3638 tw32(cpu_base + CPU_STATE, 0xffffffff);
3639 tw32_f(cpu_base + CPU_MODE, 0x00000000);
3642 /* tp->lock is held. */
3643 static void tg3_rxcpu_resume(struct tg3 *tp)
3645 tg3_resume_cpu(tp, RX_CPU_BASE);
3648 /* tp->lock is held. */
3649 static int tg3_halt_cpu(struct tg3 *tp, u32 cpu_base)
3653 BUG_ON(cpu_base == TX_CPU_BASE && tg3_flag(tp, 5705_PLUS));
3655 if (tg3_asic_rev(tp) == ASIC_REV_5906) {
3656 u32 val = tr32(GRC_VCPU_EXT_CTRL);
3658 tw32(GRC_VCPU_EXT_CTRL, val | GRC_VCPU_EXT_CTRL_HALT_CPU);
3661 if (cpu_base == RX_CPU_BASE) {
3662 rc = tg3_rxcpu_pause(tp);
3665 * There is only an Rx CPU for the 5750 derivative in the
3668 if (tg3_flag(tp, IS_SSB_CORE))
3671 rc = tg3_txcpu_pause(tp);
3675 netdev_err(tp->dev, "%s timed out, %s CPU\n",
3676 __func__, cpu_base == RX_CPU_BASE ? "RX" : "TX");
3680 /* Clear firmware's nvram arbitration. */
3681 if (tg3_flag(tp, NVRAM))
3682 tw32(NVRAM_SWARB, SWARB_REQ_CLR0);
3686 static int tg3_fw_data_len(struct tg3 *tp,
3687 const struct tg3_firmware_hdr *fw_hdr)
3691 /* Non fragmented firmware have one firmware header followed by a
3692 * contiguous chunk of data to be written. The length field in that
3693 * header is not the length of data to be written but the complete
3694 * length of the bss. The data length is determined based on
3695 * tp->fw->size minus headers.
3697 * Fragmented firmware have a main header followed by multiple
3698 * fragments. Each fragment is identical to non fragmented firmware
3699 * with a firmware header followed by a contiguous chunk of data. In
3700 * the main header, the length field is unused and set to 0xffffffff.
3701 * In each fragment header the length is the entire size of that
3702 * fragment i.e. fragment data + header length. Data length is
3703 * therefore length field in the header minus TG3_FW_HDR_LEN.
3705 if (tp->fw_len == 0xffffffff)
3706 fw_len = be32_to_cpu(fw_hdr->len);
3708 fw_len = tp->fw->size;
3710 return (fw_len - TG3_FW_HDR_LEN) / sizeof(u32);
3713 /* tp->lock is held. */
3714 static int tg3_load_firmware_cpu(struct tg3 *tp, u32 cpu_base,
3715 u32 cpu_scratch_base, int cpu_scratch_size,
3716 const struct tg3_firmware_hdr *fw_hdr)
3719 void (*write_op)(struct tg3 *, u32, u32);
3720 int total_len = tp->fw->size;
3722 if (cpu_base == TX_CPU_BASE && tg3_flag(tp, 5705_PLUS)) {
3724 "%s: Trying to load TX cpu firmware which is 5705\n",
3729 if (tg3_flag(tp, 5705_PLUS) && tg3_asic_rev(tp) != ASIC_REV_57766)
3730 write_op = tg3_write_mem;
3732 write_op = tg3_write_indirect_reg32;
3734 if (tg3_asic_rev(tp) != ASIC_REV_57766) {
3735 /* It is possible that bootcode is still loading at this point.
3736 * Get the nvram lock first before halting the cpu.
3738 int lock_err = tg3_nvram_lock(tp);
3739 err = tg3_halt_cpu(tp, cpu_base);
3741 tg3_nvram_unlock(tp);
3745 for (i = 0; i < cpu_scratch_size; i += sizeof(u32))
3746 write_op(tp, cpu_scratch_base + i, 0);
3747 tw32(cpu_base + CPU_STATE, 0xffffffff);
3748 tw32(cpu_base + CPU_MODE,
3749 tr32(cpu_base + CPU_MODE) | CPU_MODE_HALT);
3751 /* Subtract additional main header for fragmented firmware and
3752 * advance to the first fragment
3754 total_len -= TG3_FW_HDR_LEN;
3759 u32 *fw_data = (u32 *)(fw_hdr + 1);
3760 for (i = 0; i < tg3_fw_data_len(tp, fw_hdr); i++)
3761 write_op(tp, cpu_scratch_base +
3762 (be32_to_cpu(fw_hdr->base_addr) & 0xffff) +
3764 be32_to_cpu(fw_data[i]));
3766 total_len -= be32_to_cpu(fw_hdr->len);
3768 /* Advance to next fragment */
3769 fw_hdr = (struct tg3_firmware_hdr *)
3770 ((void *)fw_hdr + be32_to_cpu(fw_hdr->len));
3771 } while (total_len > 0);
3779 /* tp->lock is held. */
3780 static int tg3_pause_cpu_and_set_pc(struct tg3 *tp, u32 cpu_base, u32 pc)
3783 const int iters = 5;
3785 tw32(cpu_base + CPU_STATE, 0xffffffff);
3786 tw32_f(cpu_base + CPU_PC, pc);
3788 for (i = 0; i < iters; i++) {
3789 if (tr32(cpu_base + CPU_PC) == pc)
3791 tw32(cpu_base + CPU_STATE, 0xffffffff);
3792 tw32(cpu_base + CPU_MODE, CPU_MODE_HALT);
3793 tw32_f(cpu_base + CPU_PC, pc);
3797 return (i == iters) ? -EBUSY : 0;
3800 /* tp->lock is held. */
3801 static int tg3_load_5701_a0_firmware_fix(struct tg3 *tp)
3803 const struct tg3_firmware_hdr *fw_hdr;
3806 fw_hdr = (struct tg3_firmware_hdr *)tp->fw->data;
3808 /* Firmware blob starts with version numbers, followed by
3809 start address and length. We are setting complete length.
3810 length = end_address_of_bss - start_address_of_text.
3811 Remainder is the blob to be loaded contiguously
3812 from start address. */
3814 err = tg3_load_firmware_cpu(tp, RX_CPU_BASE,
3815 RX_CPU_SCRATCH_BASE, RX_CPU_SCRATCH_SIZE,
3820 err = tg3_load_firmware_cpu(tp, TX_CPU_BASE,
3821 TX_CPU_SCRATCH_BASE, TX_CPU_SCRATCH_SIZE,
3826 /* Now startup only the RX cpu. */
3827 err = tg3_pause_cpu_and_set_pc(tp, RX_CPU_BASE,
3828 be32_to_cpu(fw_hdr->base_addr));
3830 netdev_err(tp->dev, "%s fails to set RX CPU PC, is %08x "
3831 "should be %08x\n", __func__,
3832 tr32(RX_CPU_BASE + CPU_PC),
3833 be32_to_cpu(fw_hdr->base_addr));
3837 tg3_rxcpu_resume(tp);
3842 static int tg3_validate_rxcpu_state(struct tg3 *tp)
3844 const int iters = 1000;
3848 /* Wait for boot code to complete initialization and enter service
3849 * loop. It is then safe to download service patches
3851 for (i = 0; i < iters; i++) {
3852 if (tr32(RX_CPU_HWBKPT) == TG3_SBROM_IN_SERVICE_LOOP)
3859 netdev_err(tp->dev, "Boot code not ready for service patches\n");
3863 val = tg3_read_indirect_reg32(tp, TG3_57766_FW_HANDSHAKE);
3865 netdev_warn(tp->dev,
3866 "Other patches exist. Not downloading EEE patch\n");
3873 /* tp->lock is held. */
3874 static void tg3_load_57766_firmware(struct tg3 *tp)
3876 struct tg3_firmware_hdr *fw_hdr;
3878 if (!tg3_flag(tp, NO_NVRAM))
3881 if (tg3_validate_rxcpu_state(tp))
3887 /* This firmware blob has a different format than older firmware
3888 * releases as given below. The main difference is we have fragmented
3889 * data to be written to non-contiguous locations.
3891 * In the beginning we have a firmware header identical to other
3892 * firmware which consists of version, base addr and length. The length
3893 * here is unused and set to 0xffffffff.
3895 * This is followed by a series of firmware fragments which are
3896 * individually identical to previous firmware. i.e. they have the
3897 * firmware header and followed by data for that fragment. The version
3898 * field of the individual fragment header is unused.
3901 fw_hdr = (struct tg3_firmware_hdr *)tp->fw->data;
3902 if (be32_to_cpu(fw_hdr->base_addr) != TG3_57766_FW_BASE_ADDR)
3905 if (tg3_rxcpu_pause(tp))
3908 /* tg3_load_firmware_cpu() will always succeed for the 57766 */
3909 tg3_load_firmware_cpu(tp, 0, TG3_57766_FW_BASE_ADDR, 0, fw_hdr);
3911 tg3_rxcpu_resume(tp);
3914 /* tp->lock is held. */
3915 static int tg3_load_tso_firmware(struct tg3 *tp)
3917 const struct tg3_firmware_hdr *fw_hdr;
3918 unsigned long cpu_base, cpu_scratch_base, cpu_scratch_size;
3921 if (!tg3_flag(tp, FW_TSO))
3924 fw_hdr = (struct tg3_firmware_hdr *)tp->fw->data;
3926 /* Firmware blob starts with version numbers, followed by
3927 start address and length. We are setting complete length.
3928 length = end_address_of_bss - start_address_of_text.
3929 Remainder is the blob to be loaded contiguously
3930 from start address. */
3932 cpu_scratch_size = tp->fw_len;
3934 if (tg3_asic_rev(tp) == ASIC_REV_5705) {
3935 cpu_base = RX_CPU_BASE;
3936 cpu_scratch_base = NIC_SRAM_MBUF_POOL_BASE5705;
3938 cpu_base = TX_CPU_BASE;
3939 cpu_scratch_base = TX_CPU_SCRATCH_BASE;
3940 cpu_scratch_size = TX_CPU_SCRATCH_SIZE;
3943 err = tg3_load_firmware_cpu(tp, cpu_base,
3944 cpu_scratch_base, cpu_scratch_size,
3949 /* Now startup the cpu. */
3950 err = tg3_pause_cpu_and_set_pc(tp, cpu_base,
3951 be32_to_cpu(fw_hdr->base_addr));
3954 "%s fails to set CPU PC, is %08x should be %08x\n",
3955 __func__, tr32(cpu_base + CPU_PC),
3956 be32_to_cpu(fw_hdr->base_addr));
3960 tg3_resume_cpu(tp, cpu_base);
3964 /* tp->lock is held. */
3965 static void __tg3_set_one_mac_addr(struct tg3 *tp, u8 *mac_addr, int index)
3967 u32 addr_high, addr_low;
3969 addr_high = ((mac_addr[0] << 8) | mac_addr[1]);
3970 addr_low = ((mac_addr[2] << 24) | (mac_addr[3] << 16) |
3971 (mac_addr[4] << 8) | mac_addr[5]);
3974 tw32(MAC_ADDR_0_HIGH + (index * 8), addr_high);
3975 tw32(MAC_ADDR_0_LOW + (index * 8), addr_low);
3978 tw32(MAC_EXTADDR_0_HIGH + (index * 8), addr_high);
3979 tw32(MAC_EXTADDR_0_LOW + (index * 8), addr_low);
3983 /* tp->lock is held. */
3984 static void __tg3_set_mac_addr(struct tg3 *tp, bool skip_mac_1)
3989 for (i = 0; i < 4; i++) {
3990 if (i == 1 && skip_mac_1)
3992 __tg3_set_one_mac_addr(tp, tp->dev->dev_addr, i);
3995 if (tg3_asic_rev(tp) == ASIC_REV_5703 ||
3996 tg3_asic_rev(tp) == ASIC_REV_5704) {
3997 for (i = 4; i < 16; i++)
3998 __tg3_set_one_mac_addr(tp, tp->dev->dev_addr, i);
4001 addr_high = (tp->dev->dev_addr[0] +
4002 tp->dev->dev_addr[1] +
4003 tp->dev->dev_addr[2] +
4004 tp->dev->dev_addr[3] +
4005 tp->dev->dev_addr[4] +
4006 tp->dev->dev_addr[5]) &
4007 TX_BACKOFF_SEED_MASK;
4008 tw32(MAC_TX_BACKOFF_SEED, addr_high);
4011 static void tg3_enable_register_access(struct tg3 *tp)
4014 * Make sure register accesses (indirect or otherwise) will function
4017 pci_write_config_dword(tp->pdev,
4018 TG3PCI_MISC_HOST_CTRL, tp->misc_host_ctrl);
4021 static int tg3_power_up(struct tg3 *tp)
4025 tg3_enable_register_access(tp);
4027 err = pci_set_power_state(tp->pdev, PCI_D0);
4029 /* Switch out of Vaux if it is a NIC */
4030 tg3_pwrsrc_switch_to_vmain(tp);
4032 netdev_err(tp->dev, "Transition to D0 failed\n");
4038 static int tg3_setup_phy(struct tg3 *, bool);
4040 static int tg3_power_down_prepare(struct tg3 *tp)
4043 bool device_should_wake, do_low_power;
4045 tg3_enable_register_access(tp);
4047 /* Restore the CLKREQ setting. */
4048 if (tg3_flag(tp, CLKREQ_BUG))
4049 pcie_capability_set_word(tp->pdev, PCI_EXP_LNKCTL,
4050 PCI_EXP_LNKCTL_CLKREQ_EN);
4052 misc_host_ctrl = tr32(TG3PCI_MISC_HOST_CTRL);
4053 tw32(TG3PCI_MISC_HOST_CTRL,
4054 misc_host_ctrl | MISC_HOST_CTRL_MASK_PCI_INT);
4056 device_should_wake = device_may_wakeup(&tp->pdev->dev) &&
4057 tg3_flag(tp, WOL_ENABLE);
4059 if (tg3_flag(tp, USE_PHYLIB)) {
4060 do_low_power = false;
4061 if ((tp->phy_flags & TG3_PHYFLG_IS_CONNECTED) &&
4062 !(tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER)) {
4063 struct phy_device *phydev;
4064 u32 phyid, advertising;
4066 phydev = mdiobus_get_phy(tp->mdio_bus, tp->phy_addr);
4068 tp->phy_flags |= TG3_PHYFLG_IS_LOW_POWER;
4070 tp->link_config.speed = phydev->speed;
4071 tp->link_config.duplex = phydev->duplex;
4072 tp->link_config.autoneg = phydev->autoneg;
4073 tp->link_config.advertising = phydev->advertising;
4075 advertising = ADVERTISED_TP |
4077 ADVERTISED_Autoneg |
4078 ADVERTISED_10baseT_Half;
4080 if (tg3_flag(tp, ENABLE_ASF) || device_should_wake) {
4081 if (tg3_flag(tp, WOL_SPEED_100MB))
4083 ADVERTISED_100baseT_Half |
4084 ADVERTISED_100baseT_Full |
4085 ADVERTISED_10baseT_Full;
4087 advertising |= ADVERTISED_10baseT_Full;
4090 phydev->advertising = advertising;
4092 phy_start_aneg(phydev);
4094 phyid = phydev->drv->phy_id & phydev->drv->phy_id_mask;
4095 if (phyid != PHY_ID_BCMAC131) {
4096 phyid &= PHY_BCM_OUI_MASK;
4097 if (phyid == PHY_BCM_OUI_1 ||
4098 phyid == PHY_BCM_OUI_2 ||
4099 phyid == PHY_BCM_OUI_3)
4100 do_low_power = true;
4104 do_low_power = true;
4106 if (!(tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER))
4107 tp->phy_flags |= TG3_PHYFLG_IS_LOW_POWER;
4109 if (!(tp->phy_flags & TG3_PHYFLG_ANY_SERDES))
4110 tg3_setup_phy(tp, false);
4113 if (tg3_asic_rev(tp) == ASIC_REV_5906) {
4116 val = tr32(GRC_VCPU_EXT_CTRL);
4117 tw32(GRC_VCPU_EXT_CTRL, val | GRC_VCPU_EXT_CTRL_DISABLE_WOL);
4118 } else if (!tg3_flag(tp, ENABLE_ASF)) {
4122 for (i = 0; i < 200; i++) {
4123 tg3_read_mem(tp, NIC_SRAM_FW_ASF_STATUS_MBOX, &val);
4124 if (val == ~NIC_SRAM_FIRMWARE_MBOX_MAGIC1)
4129 if (tg3_flag(tp, WOL_CAP))
4130 tg3_write_mem(tp, NIC_SRAM_WOL_MBOX, WOL_SIGNATURE |
4131 WOL_DRV_STATE_SHUTDOWN |
4135 if (device_should_wake) {
4138 if (!(tp->phy_flags & TG3_PHYFLG_PHY_SERDES)) {
4140 !(tp->phy_flags & TG3_PHYFLG_IS_FET)) {
4141 tg3_phy_auxctl_write(tp,
4142 MII_TG3_AUXCTL_SHDWSEL_PWRCTL,
4143 MII_TG3_AUXCTL_PCTL_WOL_EN |
4144 MII_TG3_AUXCTL_PCTL_100TX_LPWR |
4145 MII_TG3_AUXCTL_PCTL_CL_AB_TXDAC);
4149 if (tp->phy_flags & TG3_PHYFLG_MII_SERDES)
4150 mac_mode = MAC_MODE_PORT_MODE_GMII;
4151 else if (tp->phy_flags &
4152 TG3_PHYFLG_KEEP_LINK_ON_PWRDN) {
4153 if (tp->link_config.active_speed == SPEED_1000)
4154 mac_mode = MAC_MODE_PORT_MODE_GMII;
4156 mac_mode = MAC_MODE_PORT_MODE_MII;
4158 mac_mode = MAC_MODE_PORT_MODE_MII;
4160 mac_mode |= tp->mac_mode & MAC_MODE_LINK_POLARITY;
4161 if (tg3_asic_rev(tp) == ASIC_REV_5700) {
4162 u32 speed = tg3_flag(tp, WOL_SPEED_100MB) ?
4163 SPEED_100 : SPEED_10;
4164 if (tg3_5700_link_polarity(tp, speed))
4165 mac_mode |= MAC_MODE_LINK_POLARITY;
4167 mac_mode &= ~MAC_MODE_LINK_POLARITY;
4170 mac_mode = MAC_MODE_PORT_MODE_TBI;
4173 if (!tg3_flag(tp, 5750_PLUS))
4174 tw32(MAC_LED_CTRL, tp->led_ctrl);
4176 mac_mode |= MAC_MODE_MAGIC_PKT_ENABLE;
4177 if ((tg3_flag(tp, 5705_PLUS) && !tg3_flag(tp, 5780_CLASS)) &&
4178 (tg3_flag(tp, ENABLE_ASF) || tg3_flag(tp, ENABLE_APE)))
4179 mac_mode |= MAC_MODE_KEEP_FRAME_IN_WOL;
4181 if (tg3_flag(tp, ENABLE_APE))
4182 mac_mode |= MAC_MODE_APE_TX_EN |
4183 MAC_MODE_APE_RX_EN |
4184 MAC_MODE_TDE_ENABLE;
4186 tw32_f(MAC_MODE, mac_mode);
4189 tw32_f(MAC_RX_MODE, RX_MODE_ENABLE);
4193 if (!tg3_flag(tp, WOL_SPEED_100MB) &&
4194 (tg3_asic_rev(tp) == ASIC_REV_5700 ||
4195 tg3_asic_rev(tp) == ASIC_REV_5701)) {
4198 base_val = tp->pci_clock_ctrl;
4199 base_val |= (CLOCK_CTRL_RXCLK_DISABLE |
4200 CLOCK_CTRL_TXCLK_DISABLE);
4202 tw32_wait_f(TG3PCI_CLOCK_CTRL, base_val | CLOCK_CTRL_ALTCLK |
4203 CLOCK_CTRL_PWRDOWN_PLL133, 40);
4204 } else if (tg3_flag(tp, 5780_CLASS) ||
4205 tg3_flag(tp, CPMU_PRESENT) ||
4206 tg3_asic_rev(tp) == ASIC_REV_5906) {
4208 } else if (!(tg3_flag(tp, 5750_PLUS) && tg3_flag(tp, ENABLE_ASF))) {
4209 u32 newbits1, newbits2;
4211 if (tg3_asic_rev(tp) == ASIC_REV_5700 ||
4212 tg3_asic_rev(tp) == ASIC_REV_5701) {
4213 newbits1 = (CLOCK_CTRL_RXCLK_DISABLE |
4214 CLOCK_CTRL_TXCLK_DISABLE |
4216 newbits2 = newbits1 | CLOCK_CTRL_44MHZ_CORE;
4217 } else if (tg3_flag(tp, 5705_PLUS)) {
4218 newbits1 = CLOCK_CTRL_625_CORE;
4219 newbits2 = newbits1 | CLOCK_CTRL_ALTCLK;
4221 newbits1 = CLOCK_CTRL_ALTCLK;
4222 newbits2 = newbits1 | CLOCK_CTRL_44MHZ_CORE;
4225 tw32_wait_f(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl | newbits1,
4228 tw32_wait_f(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl | newbits2,
4231 if (!tg3_flag(tp, 5705_PLUS)) {
4234 if (tg3_asic_rev(tp) == ASIC_REV_5700 ||
4235 tg3_asic_rev(tp) == ASIC_REV_5701) {
4236 newbits3 = (CLOCK_CTRL_RXCLK_DISABLE |
4237 CLOCK_CTRL_TXCLK_DISABLE |
4238 CLOCK_CTRL_44MHZ_CORE);
4240 newbits3 = CLOCK_CTRL_44MHZ_CORE;
4243 tw32_wait_f(TG3PCI_CLOCK_CTRL,
4244 tp->pci_clock_ctrl | newbits3, 40);
4248 if (!(device_should_wake) && !tg3_flag(tp, ENABLE_ASF))
4249 tg3_power_down_phy(tp, do_low_power);
4251 tg3_frob_aux_power(tp, true);
4253 /* Workaround for unstable PLL clock */
4254 if ((!tg3_flag(tp, IS_SSB_CORE)) &&
4255 ((tg3_chip_rev(tp) == CHIPREV_5750_AX) ||
4256 (tg3_chip_rev(tp) == CHIPREV_5750_BX))) {
4257 u32 val = tr32(0x7d00);
4259 val &= ~((1 << 16) | (1 << 4) | (1 << 2) | (1 << 1) | 1);
4261 if (!tg3_flag(tp, ENABLE_ASF)) {
4264 err = tg3_nvram_lock(tp);
4265 tg3_halt_cpu(tp, RX_CPU_BASE);
4267 tg3_nvram_unlock(tp);
4271 tg3_write_sig_post_reset(tp, RESET_KIND_SHUTDOWN);
4273 tg3_ape_driver_state_change(tp, RESET_KIND_SHUTDOWN);
4278 static void tg3_power_down(struct tg3 *tp)
4280 pci_wake_from_d3(tp->pdev, tg3_flag(tp, WOL_ENABLE));
4281 pci_set_power_state(tp->pdev, PCI_D3hot);
4284 static void tg3_aux_stat_to_speed_duplex(struct tg3 *tp, u32 val, u16 *speed, u8 *duplex)
4286 switch (val & MII_TG3_AUX_STAT_SPDMASK) {
4287 case MII_TG3_AUX_STAT_10HALF:
4289 *duplex = DUPLEX_HALF;
4292 case MII_TG3_AUX_STAT_10FULL:
4294 *duplex = DUPLEX_FULL;
4297 case MII_TG3_AUX_STAT_100HALF:
4299 *duplex = DUPLEX_HALF;
4302 case MII_TG3_AUX_STAT_100FULL:
4304 *duplex = DUPLEX_FULL;
4307 case MII_TG3_AUX_STAT_1000HALF:
4308 *speed = SPEED_1000;
4309 *duplex = DUPLEX_HALF;
4312 case MII_TG3_AUX_STAT_1000FULL:
4313 *speed = SPEED_1000;
4314 *duplex = DUPLEX_FULL;
4318 if (tp->phy_flags & TG3_PHYFLG_IS_FET) {
4319 *speed = (val & MII_TG3_AUX_STAT_100) ? SPEED_100 :
4321 *duplex = (val & MII_TG3_AUX_STAT_FULL) ? DUPLEX_FULL :
4325 *speed = SPEED_UNKNOWN;
4326 *duplex = DUPLEX_UNKNOWN;
4331 static int tg3_phy_autoneg_cfg(struct tg3 *tp, u32 advertise, u32 flowctrl)
4336 new_adv = ADVERTISE_CSMA;
4337 new_adv |= ethtool_adv_to_mii_adv_t(advertise) & ADVERTISE_ALL;
4338 new_adv |= mii_advertise_flowctrl(flowctrl);
4340 err = tg3_writephy(tp, MII_ADVERTISE, new_adv);
4344 if (!(tp->phy_flags & TG3_PHYFLG_10_100_ONLY)) {
4345 new_adv = ethtool_adv_to_mii_ctrl1000_t(advertise);
4347 if (tg3_chip_rev_id(tp) == CHIPREV_ID_5701_A0 ||
4348 tg3_chip_rev_id(tp) == CHIPREV_ID_5701_B0)
4349 new_adv |= CTL1000_AS_MASTER | CTL1000_ENABLE_MASTER;
4351 err = tg3_writephy(tp, MII_CTRL1000, new_adv);
4356 if (!(tp->phy_flags & TG3_PHYFLG_EEE_CAP))
4359 tw32(TG3_CPMU_EEE_MODE,
4360 tr32(TG3_CPMU_EEE_MODE) & ~TG3_CPMU_EEEMD_LPI_ENABLE);
4362 err = tg3_phy_toggle_auxctl_smdsp(tp, true);
4367 /* Advertise 100-BaseTX EEE ability */
4368 if (advertise & ADVERTISED_100baseT_Full)
4369 val |= MDIO_AN_EEE_ADV_100TX;
4370 /* Advertise 1000-BaseT EEE ability */
4371 if (advertise & ADVERTISED_1000baseT_Full)
4372 val |= MDIO_AN_EEE_ADV_1000T;
4374 if (!tp->eee.eee_enabled) {
4376 tp->eee.advertised = 0;
4378 tp->eee.advertised = advertise &
4379 (ADVERTISED_100baseT_Full |
4380 ADVERTISED_1000baseT_Full);
4383 err = tg3_phy_cl45_write(tp, MDIO_MMD_AN, MDIO_AN_EEE_ADV, val);
4387 switch (tg3_asic_rev(tp)) {
4389 case ASIC_REV_57765:
4390 case ASIC_REV_57766:
4392 /* If we advertised any eee advertisements above... */
4394 val = MII_TG3_DSP_TAP26_ALNOKO |
4395 MII_TG3_DSP_TAP26_RMRXSTO |
4396 MII_TG3_DSP_TAP26_OPCSINPT;
4397 tg3_phydsp_write(tp, MII_TG3_DSP_TAP26, val);
4401 if (!tg3_phydsp_read(tp, MII_TG3_DSP_CH34TP2, &val))
4402 tg3_phydsp_write(tp, MII_TG3_DSP_CH34TP2, val |
4403 MII_TG3_DSP_CH34TP2_HIBW01);
4406 err2 = tg3_phy_toggle_auxctl_smdsp(tp, false);
4415 static void tg3_phy_copper_begin(struct tg3 *tp)
4417 if (tp->link_config.autoneg == AUTONEG_ENABLE ||
4418 (tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER)) {
4421 if ((tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER) &&
4422 !(tp->phy_flags & TG3_PHYFLG_KEEP_LINK_ON_PWRDN)) {
4423 adv = ADVERTISED_10baseT_Half |
4424 ADVERTISED_10baseT_Full;
4425 if (tg3_flag(tp, WOL_SPEED_100MB))
4426 adv |= ADVERTISED_100baseT_Half |
4427 ADVERTISED_100baseT_Full;
4428 if (tp->phy_flags & TG3_PHYFLG_1G_ON_VAUX_OK) {
4429 if (!(tp->phy_flags &
4430 TG3_PHYFLG_DISABLE_1G_HD_ADV))
4431 adv |= ADVERTISED_1000baseT_Half;
4432 adv |= ADVERTISED_1000baseT_Full;
4435 fc = FLOW_CTRL_TX | FLOW_CTRL_RX;
4437 adv = tp->link_config.advertising;
4438 if (tp->phy_flags & TG3_PHYFLG_10_100_ONLY)
4439 adv &= ~(ADVERTISED_1000baseT_Half |
4440 ADVERTISED_1000baseT_Full);
4442 fc = tp->link_config.flowctrl;
4445 tg3_phy_autoneg_cfg(tp, adv, fc);
4447 if ((tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER) &&
4448 (tp->phy_flags & TG3_PHYFLG_KEEP_LINK_ON_PWRDN)) {
4449 /* Normally during power down we want to autonegotiate
4450 * the lowest possible speed for WOL. However, to avoid
4451 * link flap, we leave it untouched.
4456 tg3_writephy(tp, MII_BMCR,
4457 BMCR_ANENABLE | BMCR_ANRESTART);
4460 u32 bmcr, orig_bmcr;
4462 tp->link_config.active_speed = tp->link_config.speed;
4463 tp->link_config.active_duplex = tp->link_config.duplex;
4465 if (tg3_asic_rev(tp) == ASIC_REV_5714) {
4466 /* With autoneg disabled, 5715 only links up when the
4467 * advertisement register has the configured speed
4470 tg3_writephy(tp, MII_ADVERTISE, ADVERTISE_ALL);
4474 switch (tp->link_config.speed) {
4480 bmcr |= BMCR_SPEED100;
4484 bmcr |= BMCR_SPEED1000;
4488 if (tp->link_config.duplex == DUPLEX_FULL)
4489 bmcr |= BMCR_FULLDPLX;
4491 if (!tg3_readphy(tp, MII_BMCR, &orig_bmcr) &&
4492 (bmcr != orig_bmcr)) {
4493 tg3_writephy(tp, MII_BMCR, BMCR_LOOPBACK);
4494 for (i = 0; i < 1500; i++) {
4498 if (tg3_readphy(tp, MII_BMSR, &tmp) ||
4499 tg3_readphy(tp, MII_BMSR, &tmp))
4501 if (!(tmp & BMSR_LSTATUS)) {
4506 tg3_writephy(tp, MII_BMCR, bmcr);
4512 static int tg3_phy_pull_config(struct tg3 *tp)
4517 err = tg3_readphy(tp, MII_BMCR, &val);
4521 if (!(val & BMCR_ANENABLE)) {
4522 tp->link_config.autoneg = AUTONEG_DISABLE;
4523 tp->link_config.advertising = 0;
4524 tg3_flag_clear(tp, PAUSE_AUTONEG);
4528 switch (val & (BMCR_SPEED1000 | BMCR_SPEED100)) {
4530 if (tp->phy_flags & TG3_PHYFLG_ANY_SERDES)
4533 tp->link_config.speed = SPEED_10;
4536 if (tp->phy_flags & TG3_PHYFLG_ANY_SERDES)
4539 tp->link_config.speed = SPEED_100;
4541 case BMCR_SPEED1000:
4542 if (!(tp->phy_flags & TG3_PHYFLG_10_100_ONLY)) {
4543 tp->link_config.speed = SPEED_1000;
4551 if (val & BMCR_FULLDPLX)
4552 tp->link_config.duplex = DUPLEX_FULL;
4554 tp->link_config.duplex = DUPLEX_HALF;
4556 tp->link_config.flowctrl = FLOW_CTRL_RX | FLOW_CTRL_TX;
4562 tp->link_config.autoneg = AUTONEG_ENABLE;
4563 tp->link_config.advertising = ADVERTISED_Autoneg;
4564 tg3_flag_set(tp, PAUSE_AUTONEG);
4566 if (!(tp->phy_flags & TG3_PHYFLG_ANY_SERDES)) {
4569 err = tg3_readphy(tp, MII_ADVERTISE, &val);
4573 adv = mii_adv_to_ethtool_adv_t(val & ADVERTISE_ALL);
4574 tp->link_config.advertising |= adv | ADVERTISED_TP;
4576 tp->link_config.flowctrl = tg3_decode_flowctrl_1000T(val);
4578 tp->link_config.advertising |= ADVERTISED_FIBRE;
4581 if (!(tp->phy_flags & TG3_PHYFLG_10_100_ONLY)) {
4584 if (!(tp->phy_flags & TG3_PHYFLG_ANY_SERDES)) {
4585 err = tg3_readphy(tp, MII_CTRL1000, &val);
4589 adv = mii_ctrl1000_to_ethtool_adv_t(val);
4591 err = tg3_readphy(tp, MII_ADVERTISE, &val);
4595 adv = tg3_decode_flowctrl_1000X(val);
4596 tp->link_config.flowctrl = adv;
4598 val &= (ADVERTISE_1000XHALF | ADVERTISE_1000XFULL);
4599 adv = mii_adv_to_ethtool_adv_x(val);
4602 tp->link_config.advertising |= adv;
4609 static int tg3_init_5401phy_dsp(struct tg3 *tp)
4613 /* Turn off tap power management. */
4614 /* Set Extended packet length bit */
4615 err = tg3_phy_auxctl_write(tp, MII_TG3_AUXCTL_SHDWSEL_AUXCTL, 0x4c20);
4617 err |= tg3_phydsp_write(tp, 0x0012, 0x1804);
4618 err |= tg3_phydsp_write(tp, 0x0013, 0x1204);
4619 err |= tg3_phydsp_write(tp, 0x8006, 0x0132);
4620 err |= tg3_phydsp_write(tp, 0x8006, 0x0232);
4621 err |= tg3_phydsp_write(tp, 0x201f, 0x0a20);
4628 static bool tg3_phy_eee_config_ok(struct tg3 *tp)
4630 struct ethtool_eee eee;
4632 if (!(tp->phy_flags & TG3_PHYFLG_EEE_CAP))
4635 tg3_eee_pull_config(tp, &eee);
4637 if (tp->eee.eee_enabled) {
4638 if (tp->eee.advertised != eee.advertised ||
4639 tp->eee.tx_lpi_timer != eee.tx_lpi_timer ||
4640 tp->eee.tx_lpi_enabled != eee.tx_lpi_enabled)
4643 /* EEE is disabled but we're advertising */
4651 static bool tg3_phy_copper_an_config_ok(struct tg3 *tp, u32 *lcladv)
4653 u32 advmsk, tgtadv, advertising;
4655 advertising = tp->link_config.advertising;
4656 tgtadv = ethtool_adv_to_mii_adv_t(advertising) & ADVERTISE_ALL;
4658 advmsk = ADVERTISE_ALL;
4659 if (tp->link_config.active_duplex == DUPLEX_FULL) {
4660 tgtadv |= mii_advertise_flowctrl(tp->link_config.flowctrl);
4661 advmsk |= ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM;
4664 if (tg3_readphy(tp, MII_ADVERTISE, lcladv))
4667 if ((*lcladv & advmsk) != tgtadv)
4670 if (!(tp->phy_flags & TG3_PHYFLG_10_100_ONLY)) {
4673 tgtadv = ethtool_adv_to_mii_ctrl1000_t(advertising);
4675 if (tg3_readphy(tp, MII_CTRL1000, &tg3_ctrl))
4679 (tg3_chip_rev_id(tp) == CHIPREV_ID_5701_A0 ||
4680 tg3_chip_rev_id(tp) == CHIPREV_ID_5701_B0)) {
4681 tgtadv |= CTL1000_AS_MASTER | CTL1000_ENABLE_MASTER;
4682 tg3_ctrl &= (ADVERTISE_1000HALF | ADVERTISE_1000FULL |
4683 CTL1000_AS_MASTER | CTL1000_ENABLE_MASTER);
4685 tg3_ctrl &= (ADVERTISE_1000HALF | ADVERTISE_1000FULL);
4688 if (tg3_ctrl != tgtadv)
4695 static bool tg3_phy_copper_fetch_rmtadv(struct tg3 *tp, u32 *rmtadv)
4699 if (!(tp->phy_flags & TG3_PHYFLG_10_100_ONLY)) {
4702 if (tg3_readphy(tp, MII_STAT1000, &val))
4705 lpeth = mii_stat1000_to_ethtool_lpa_t(val);
4708 if (tg3_readphy(tp, MII_LPA, rmtadv))
4711 lpeth |= mii_lpa_to_ethtool_lpa_t(*rmtadv);
4712 tp->link_config.rmt_adv = lpeth;
4717 static bool tg3_test_and_report_link_chg(struct tg3 *tp, bool curr_link_up)
4719 if (curr_link_up != tp->link_up) {
4721 netif_carrier_on(tp->dev);
4723 netif_carrier_off(tp->dev);
4724 if (tp->phy_flags & TG3_PHYFLG_MII_SERDES)
4725 tp->phy_flags &= ~TG3_PHYFLG_PARALLEL_DETECT;
4728 tg3_link_report(tp);
4735 static void tg3_clear_mac_status(struct tg3 *tp)
4740 MAC_STATUS_SYNC_CHANGED |
4741 MAC_STATUS_CFG_CHANGED |
4742 MAC_STATUS_MI_COMPLETION |
4743 MAC_STATUS_LNKSTATE_CHANGED);
4747 static void tg3_setup_eee(struct tg3 *tp)
4751 val = TG3_CPMU_EEE_LNKIDL_PCIE_NL0 |
4752 TG3_CPMU_EEE_LNKIDL_UART_IDL;
4753 if (tg3_chip_rev_id(tp) == CHIPREV_ID_57765_A0)
4754 val |= TG3_CPMU_EEE_LNKIDL_APE_TX_MT;
4756 tw32_f(TG3_CPMU_EEE_LNKIDL_CTRL, val);
4758 tw32_f(TG3_CPMU_EEE_CTRL,
4759 TG3_CPMU_EEE_CTRL_EXIT_20_1_US);
4761 val = TG3_CPMU_EEEMD_ERLY_L1_XIT_DET |
4762 (tp->eee.tx_lpi_enabled ? TG3_CPMU_EEEMD_LPI_IN_TX : 0) |
4763 TG3_CPMU_EEEMD_LPI_IN_RX |
4764 TG3_CPMU_EEEMD_EEE_ENABLE;
4766 if (tg3_asic_rev(tp) != ASIC_REV_5717)
4767 val |= TG3_CPMU_EEEMD_SND_IDX_DET_EN;
4769 if (tg3_flag(tp, ENABLE_APE))
4770 val |= TG3_CPMU_EEEMD_APE_TX_DET_EN;
4772 tw32_f(TG3_CPMU_EEE_MODE, tp->eee.eee_enabled ? val : 0);
4774 tw32_f(TG3_CPMU_EEE_DBTMR1,
4775 TG3_CPMU_DBTMR1_PCIEXIT_2047US |
4776 (tp->eee.tx_lpi_timer & 0xffff));
4778 tw32_f(TG3_CPMU_EEE_DBTMR2,
4779 TG3_CPMU_DBTMR2_APE_TX_2047US |
4780 TG3_CPMU_DBTMR2_TXIDXEQ_2047US);
4783 static int tg3_setup_copper_phy(struct tg3 *tp, bool force_reset)
4785 bool current_link_up;
4787 u32 lcl_adv, rmt_adv;
4792 tg3_clear_mac_status(tp);
4794 if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
4796 (tp->mi_mode & ~MAC_MI_MODE_AUTO_POLL));
4800 tg3_phy_auxctl_write(tp, MII_TG3_AUXCTL_SHDWSEL_PWRCTL, 0);
4802 /* Some third-party PHYs need to be reset on link going
4805 if ((tg3_asic_rev(tp) == ASIC_REV_5703 ||
4806 tg3_asic_rev(tp) == ASIC_REV_5704 ||
4807 tg3_asic_rev(tp) == ASIC_REV_5705) &&
4809 tg3_readphy(tp, MII_BMSR, &bmsr);
4810 if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
4811 !(bmsr & BMSR_LSTATUS))
4817 if ((tp->phy_id & TG3_PHY_ID_MASK) == TG3_PHY_ID_BCM5401) {
4818 tg3_readphy(tp, MII_BMSR, &bmsr);
4819 if (tg3_readphy(tp, MII_BMSR, &bmsr) ||
4820 !tg3_flag(tp, INIT_COMPLETE))
4823 if (!(bmsr & BMSR_LSTATUS)) {
4824 err = tg3_init_5401phy_dsp(tp);
4828 tg3_readphy(tp, MII_BMSR, &bmsr);
4829 for (i = 0; i < 1000; i++) {
4831 if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
4832 (bmsr & BMSR_LSTATUS)) {
4838 if ((tp->phy_id & TG3_PHY_ID_REV_MASK) ==
4839 TG3_PHY_REV_BCM5401_B0 &&
4840 !(bmsr & BMSR_LSTATUS) &&
4841 tp->link_config.active_speed == SPEED_1000) {
4842 err = tg3_phy_reset(tp);
4844 err = tg3_init_5401phy_dsp(tp);
4849 } else if (tg3_chip_rev_id(tp) == CHIPREV_ID_5701_A0 ||
4850 tg3_chip_rev_id(tp) == CHIPREV_ID_5701_B0) {
4851 /* 5701 {A0,B0} CRC bug workaround */
4852 tg3_writephy(tp, 0x15, 0x0a75);
4853 tg3_writephy(tp, MII_TG3_MISC_SHDW, 0x8c68);
4854 tg3_writephy(tp, MII_TG3_MISC_SHDW, 0x8d68);
4855 tg3_writephy(tp, MII_TG3_MISC_SHDW, 0x8c68);
4858 /* Clear pending interrupts... */
4859 tg3_readphy(tp, MII_TG3_ISTAT, &val);
4860 tg3_readphy(tp, MII_TG3_ISTAT, &val);
4862 if (tp->phy_flags & TG3_PHYFLG_USE_MI_INTERRUPT)
4863 tg3_writephy(tp, MII_TG3_IMASK, ~MII_TG3_INT_LINKCHG);
4864 else if (!(tp->phy_flags & TG3_PHYFLG_IS_FET))
4865 tg3_writephy(tp, MII_TG3_IMASK, ~0);
4867 if (tg3_asic_rev(tp) == ASIC_REV_5700 ||
4868 tg3_asic_rev(tp) == ASIC_REV_5701) {
4869 if (tp->led_ctrl == LED_CTRL_MODE_PHY_1)
4870 tg3_writephy(tp, MII_TG3_EXT_CTRL,
4871 MII_TG3_EXT_CTRL_LNK3_LED_MODE);
4873 tg3_writephy(tp, MII_TG3_EXT_CTRL, 0);
4876 current_link_up = false;
4877 current_speed = SPEED_UNKNOWN;
4878 current_duplex = DUPLEX_UNKNOWN;
4879 tp->phy_flags &= ~TG3_PHYFLG_MDIX_STATE;
4880 tp->link_config.rmt_adv = 0;
4882 if (tp->phy_flags & TG3_PHYFLG_CAPACITIVE_COUPLING) {
4883 err = tg3_phy_auxctl_read(tp,
4884 MII_TG3_AUXCTL_SHDWSEL_MISCTEST,
4886 if (!err && !(val & (1 << 10))) {
4887 tg3_phy_auxctl_write(tp,
4888 MII_TG3_AUXCTL_SHDWSEL_MISCTEST,
4895 for (i = 0; i < 100; i++) {
4896 tg3_readphy(tp, MII_BMSR, &bmsr);
4897 if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
4898 (bmsr & BMSR_LSTATUS))
4903 if (bmsr & BMSR_LSTATUS) {
4906 tg3_readphy(tp, MII_TG3_AUX_STAT, &aux_stat);
4907 for (i = 0; i < 2000; i++) {
4909 if (!tg3_readphy(tp, MII_TG3_AUX_STAT, &aux_stat) &&
4914 tg3_aux_stat_to_speed_duplex(tp, aux_stat,
4919 for (i = 0; i < 200; i++) {
4920 tg3_readphy(tp, MII_BMCR, &bmcr);
4921 if (tg3_readphy(tp, MII_BMCR, &bmcr))
4923 if (bmcr && bmcr != 0x7fff)
4931 tp->link_config.active_speed = current_speed;
4932 tp->link_config.active_duplex = current_duplex;
4934 if (tp->link_config.autoneg == AUTONEG_ENABLE) {
4935 bool eee_config_ok = tg3_phy_eee_config_ok(tp);
4937 if ((bmcr & BMCR_ANENABLE) &&
4939 tg3_phy_copper_an_config_ok(tp, &lcl_adv) &&
4940 tg3_phy_copper_fetch_rmtadv(tp, &rmt_adv))
4941 current_link_up = true;
4943 /* EEE settings changes take effect only after a phy
4944 * reset. If we have skipped a reset due to Link Flap
4945 * Avoidance being enabled, do it now.
4947 if (!eee_config_ok &&
4948 (tp->phy_flags & TG3_PHYFLG_KEEP_LINK_ON_PWRDN) &&
4954 if (!(bmcr & BMCR_ANENABLE) &&
4955 tp->link_config.speed == current_speed &&
4956 tp->link_config.duplex == current_duplex) {
4957 current_link_up = true;
4961 if (current_link_up &&
4962 tp->link_config.active_duplex == DUPLEX_FULL) {
4965 if (tp->phy_flags & TG3_PHYFLG_IS_FET) {
4966 reg = MII_TG3_FET_GEN_STAT;
4967 bit = MII_TG3_FET_GEN_STAT_MDIXSTAT;
4969 reg = MII_TG3_EXT_STAT;
4970 bit = MII_TG3_EXT_STAT_MDIX;
4973 if (!tg3_readphy(tp, reg, &val) && (val & bit))
4974 tp->phy_flags |= TG3_PHYFLG_MDIX_STATE;
4976 tg3_setup_flow_control(tp, lcl_adv, rmt_adv);
4981 if (!current_link_up || (tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER)) {
4982 tg3_phy_copper_begin(tp);
4984 if (tg3_flag(tp, ROBOSWITCH)) {
4985 current_link_up = true;
4986 /* FIXME: when BCM5325 switch is used use 100 MBit/s */
4987 current_speed = SPEED_1000;
4988 current_duplex = DUPLEX_FULL;
4989 tp->link_config.active_speed = current_speed;
4990 tp->link_config.active_duplex = current_duplex;
4993 tg3_readphy(tp, MII_BMSR, &bmsr);
4994 if ((!tg3_readphy(tp, MII_BMSR, &bmsr) && (bmsr & BMSR_LSTATUS)) ||
4995 (tp->mac_mode & MAC_MODE_PORT_INT_LPBACK))
4996 current_link_up = true;
4999 tp->mac_mode &= ~MAC_MODE_PORT_MODE_MASK;
5000 if (current_link_up) {
5001 if (tp->link_config.active_speed == SPEED_100 ||
5002 tp->link_config.active_speed == SPEED_10)
5003 tp->mac_mode |= MAC_MODE_PORT_MODE_MII;
5005 tp->mac_mode |= MAC_MODE_PORT_MODE_GMII;
5006 } else if (tp->phy_flags & TG3_PHYFLG_IS_FET)
5007 tp->mac_mode |= MAC_MODE_PORT_MODE_MII;
5009 tp->mac_mode |= MAC_MODE_PORT_MODE_GMII;
5011 /* In order for the 5750 core in BCM4785 chip to work properly
5012 * in RGMII mode, the Led Control Register must be set up.
5014 if (tg3_flag(tp, RGMII_MODE)) {
5015 u32 led_ctrl = tr32(MAC_LED_CTRL);
5016 led_ctrl &= ~(LED_CTRL_1000MBPS_ON | LED_CTRL_100MBPS_ON);
5018 if (tp->link_config.active_speed == SPEED_10)
5019 led_ctrl |= LED_CTRL_LNKLED_OVERRIDE;
5020 else if (tp->link_config.active_speed == SPEED_100)
5021 led_ctrl |= (LED_CTRL_LNKLED_OVERRIDE |
5022 LED_CTRL_100MBPS_ON);
5023 else if (tp->link_config.active_speed == SPEED_1000)
5024 led_ctrl |= (LED_CTRL_LNKLED_OVERRIDE |
5025 LED_CTRL_1000MBPS_ON);
5027 tw32(MAC_LED_CTRL, led_ctrl);
5031 tp->mac_mode &= ~MAC_MODE_HALF_DUPLEX;
5032 if (tp->link_config.active_duplex == DUPLEX_HALF)
5033 tp->mac_mode |= MAC_MODE_HALF_DUPLEX;
5035 if (tg3_asic_rev(tp) == ASIC_REV_5700) {
5036 if (current_link_up &&
5037 tg3_5700_link_polarity(tp, tp->link_config.active_speed))
5038 tp->mac_mode |= MAC_MODE_LINK_POLARITY;
5040 tp->mac_mode &= ~MAC_MODE_LINK_POLARITY;
5043 /* ??? Without this setting Netgear GA302T PHY does not
5044 * ??? send/receive packets...
5046 if ((tp->phy_id & TG3_PHY_ID_MASK) == TG3_PHY_ID_BCM5411 &&
5047 tg3_chip_rev_id(tp) == CHIPREV_ID_5700_ALTIMA) {
5048 tp->mi_mode |= MAC_MI_MODE_AUTO_POLL;
5049 tw32_f(MAC_MI_MODE, tp->mi_mode);
5053 tw32_f(MAC_MODE, tp->mac_mode);
5056 tg3_phy_eee_adjust(tp, current_link_up);
5058 if (tg3_flag(tp, USE_LINKCHG_REG)) {
5059 /* Polled via timer. */
5060 tw32_f(MAC_EVENT, 0);
5062 tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
5066 if (tg3_asic_rev(tp) == ASIC_REV_5700 &&
5068 tp->link_config.active_speed == SPEED_1000 &&
5069 (tg3_flag(tp, PCIX_MODE) || tg3_flag(tp, PCI_HIGH_SPEED))) {
5072 (MAC_STATUS_SYNC_CHANGED |
5073 MAC_STATUS_CFG_CHANGED));
5076 NIC_SRAM_FIRMWARE_MBOX,
5077 NIC_SRAM_FIRMWARE_MBOX_MAGIC2);
5080 /* Prevent send BD corruption. */
5081 if (tg3_flag(tp, CLKREQ_BUG)) {
5082 if (tp->link_config.active_speed == SPEED_100 ||
5083 tp->link_config.active_speed == SPEED_10)
5084 pcie_capability_clear_word(tp->pdev, PCI_EXP_LNKCTL,
5085 PCI_EXP_LNKCTL_CLKREQ_EN);
5087 pcie_capability_set_word(tp->pdev, PCI_EXP_LNKCTL,
5088 PCI_EXP_LNKCTL_CLKREQ_EN);
5091 tg3_test_and_report_link_chg(tp, current_link_up);
5096 struct tg3_fiber_aneginfo {
5098 #define ANEG_STATE_UNKNOWN 0
5099 #define ANEG_STATE_AN_ENABLE 1
5100 #define ANEG_STATE_RESTART_INIT 2
5101 #define ANEG_STATE_RESTART 3
5102 #define ANEG_STATE_DISABLE_LINK_OK 4
5103 #define ANEG_STATE_ABILITY_DETECT_INIT 5
5104 #define ANEG_STATE_ABILITY_DETECT 6
5105 #define ANEG_STATE_ACK_DETECT_INIT 7
5106 #define ANEG_STATE_ACK_DETECT 8
5107 #define ANEG_STATE_COMPLETE_ACK_INIT 9
5108 #define ANEG_STATE_COMPLETE_ACK 10
5109 #define ANEG_STATE_IDLE_DETECT_INIT 11
5110 #define ANEG_STATE_IDLE_DETECT 12
5111 #define ANEG_STATE_LINK_OK 13
5112 #define ANEG_STATE_NEXT_PAGE_WAIT_INIT 14
5113 #define ANEG_STATE_NEXT_PAGE_WAIT 15
5116 #define MR_AN_ENABLE 0x00000001
5117 #define MR_RESTART_AN 0x00000002
5118 #define MR_AN_COMPLETE 0x00000004
5119 #define MR_PAGE_RX 0x00000008
5120 #define MR_NP_LOADED 0x00000010
5121 #define MR_TOGGLE_TX 0x00000020
5122 #define MR_LP_ADV_FULL_DUPLEX 0x00000040
5123 #define MR_LP_ADV_HALF_DUPLEX 0x00000080
5124 #define MR_LP_ADV_SYM_PAUSE 0x00000100
5125 #define MR_LP_ADV_ASYM_PAUSE 0x00000200
5126 #define MR_LP_ADV_REMOTE_FAULT1 0x00000400
5127 #define MR_LP_ADV_REMOTE_FAULT2 0x00000800
5128 #define MR_LP_ADV_NEXT_PAGE 0x00001000
5129 #define MR_TOGGLE_RX 0x00002000
5130 #define MR_NP_RX 0x00004000
5132 #define MR_LINK_OK 0x80000000
5134 unsigned long link_time, cur_time;
5136 u32 ability_match_cfg;
5137 int ability_match_count;
5139 char ability_match, idle_match, ack_match;
5141 u32 txconfig, rxconfig;
5142 #define ANEG_CFG_NP 0x00000080
5143 #define ANEG_CFG_ACK 0x00000040
5144 #define ANEG_CFG_RF2 0x00000020
5145 #define ANEG_CFG_RF1 0x00000010
5146 #define ANEG_CFG_PS2 0x00000001
5147 #define ANEG_CFG_PS1 0x00008000
5148 #define ANEG_CFG_HD 0x00004000
5149 #define ANEG_CFG_FD 0x00002000
5150 #define ANEG_CFG_INVAL 0x00001f06
5155 #define ANEG_TIMER_ENAB 2
5156 #define ANEG_FAILED -1
5158 #define ANEG_STATE_SETTLE_TIME 10000
5160 static int tg3_fiber_aneg_smachine(struct tg3 *tp,
5161 struct tg3_fiber_aneginfo *ap)
5164 unsigned long delta;
5168 if (ap->state == ANEG_STATE_UNKNOWN) {
5172 ap->ability_match_cfg = 0;
5173 ap->ability_match_count = 0;
5174 ap->ability_match = 0;
5180 if (tr32(MAC_STATUS) & MAC_STATUS_RCVD_CFG) {
5181 rx_cfg_reg = tr32(MAC_RX_AUTO_NEG);
5183 if (rx_cfg_reg != ap->ability_match_cfg) {
5184 ap->ability_match_cfg = rx_cfg_reg;
5185 ap->ability_match = 0;
5186 ap->ability_match_count = 0;
5188 if (++ap->ability_match_count > 1) {
5189 ap->ability_match = 1;
5190 ap->ability_match_cfg = rx_cfg_reg;
5193 if (rx_cfg_reg & ANEG_CFG_ACK)
5201 ap->ability_match_cfg = 0;
5202 ap->ability_match_count = 0;
5203 ap->ability_match = 0;
5209 ap->rxconfig = rx_cfg_reg;
5212 switch (ap->state) {
5213 case ANEG_STATE_UNKNOWN:
5214 if (ap->flags & (MR_AN_ENABLE | MR_RESTART_AN))
5215 ap->state = ANEG_STATE_AN_ENABLE;
5218 case ANEG_STATE_AN_ENABLE:
5219 ap->flags &= ~(MR_AN_COMPLETE | MR_PAGE_RX);
5220 if (ap->flags & MR_AN_ENABLE) {
5223 ap->ability_match_cfg = 0;
5224 ap->ability_match_count = 0;
5225 ap->ability_match = 0;
5229 ap->state = ANEG_STATE_RESTART_INIT;
5231 ap->state = ANEG_STATE_DISABLE_LINK_OK;
5235 case ANEG_STATE_RESTART_INIT:
5236 ap->link_time = ap->cur_time;
5237 ap->flags &= ~(MR_NP_LOADED);
5239 tw32(MAC_TX_AUTO_NEG, 0);
5240 tp->mac_mode |= MAC_MODE_SEND_CONFIGS;
5241 tw32_f(MAC_MODE, tp->mac_mode);
5244 ret = ANEG_TIMER_ENAB;
5245 ap->state = ANEG_STATE_RESTART;
5248 case ANEG_STATE_RESTART:
5249 delta = ap->cur_time - ap->link_time;
5250 if (delta > ANEG_STATE_SETTLE_TIME)
5251 ap->state = ANEG_STATE_ABILITY_DETECT_INIT;
5253 ret = ANEG_TIMER_ENAB;
5256 case ANEG_STATE_DISABLE_LINK_OK:
5260 case ANEG_STATE_ABILITY_DETECT_INIT:
5261 ap->flags &= ~(MR_TOGGLE_TX);
5262 ap->txconfig = ANEG_CFG_FD;
5263 flowctrl = tg3_advert_flowctrl_1000X(tp->link_config.flowctrl);
5264 if (flowctrl & ADVERTISE_1000XPAUSE)
5265 ap->txconfig |= ANEG_CFG_PS1;
5266 if (flowctrl & ADVERTISE_1000XPSE_ASYM)
5267 ap->txconfig |= ANEG_CFG_PS2;
5268 tw32(MAC_TX_AUTO_NEG, ap->txconfig);
5269 tp->mac_mode |= MAC_MODE_SEND_CONFIGS;
5270 tw32_f(MAC_MODE, tp->mac_mode);
5273 ap->state = ANEG_STATE_ABILITY_DETECT;
5276 case ANEG_STATE_ABILITY_DETECT:
5277 if (ap->ability_match != 0 && ap->rxconfig != 0)
5278 ap->state = ANEG_STATE_ACK_DETECT_INIT;
5281 case ANEG_STATE_ACK_DETECT_INIT:
5282 ap->txconfig |= ANEG_CFG_ACK;
5283 tw32(MAC_TX_AUTO_NEG, ap->txconfig);
5284 tp->mac_mode |= MAC_MODE_SEND_CONFIGS;
5285 tw32_f(MAC_MODE, tp->mac_mode);
5288 ap->state = ANEG_STATE_ACK_DETECT;
5291 case ANEG_STATE_ACK_DETECT:
5292 if (ap->ack_match != 0) {
5293 if ((ap->rxconfig & ~ANEG_CFG_ACK) ==
5294 (ap->ability_match_cfg & ~ANEG_CFG_ACK)) {
5295 ap->state = ANEG_STATE_COMPLETE_ACK_INIT;
5297 ap->state = ANEG_STATE_AN_ENABLE;
5299 } else if (ap->ability_match != 0 &&
5300 ap->rxconfig == 0) {
5301 ap->state = ANEG_STATE_AN_ENABLE;
5305 case ANEG_STATE_COMPLETE_ACK_INIT:
5306 if (ap->rxconfig & ANEG_CFG_INVAL) {
5310 ap->flags &= ~(MR_LP_ADV_FULL_DUPLEX |
5311 MR_LP_ADV_HALF_DUPLEX |
5312 MR_LP_ADV_SYM_PAUSE |
5313 MR_LP_ADV_ASYM_PAUSE |
5314 MR_LP_ADV_REMOTE_FAULT1 |
5315 MR_LP_ADV_REMOTE_FAULT2 |
5316 MR_LP_ADV_NEXT_PAGE |
5319 if (ap->rxconfig & ANEG_CFG_FD)
5320 ap->flags |= MR_LP_ADV_FULL_DUPLEX;
5321 if (ap->rxconfig & ANEG_CFG_HD)
5322 ap->flags |= MR_LP_ADV_HALF_DUPLEX;
5323 if (ap->rxconfig & ANEG_CFG_PS1)
5324 ap->flags |= MR_LP_ADV_SYM_PAUSE;
5325 if (ap->rxconfig & ANEG_CFG_PS2)
5326 ap->flags |= MR_LP_ADV_ASYM_PAUSE;
5327 if (ap->rxconfig & ANEG_CFG_RF1)
5328 ap->flags |= MR_LP_ADV_REMOTE_FAULT1;
5329 if (ap->rxconfig & ANEG_CFG_RF2)
5330 ap->flags |= MR_LP_ADV_REMOTE_FAULT2;
5331 if (ap->rxconfig & ANEG_CFG_NP)
5332 ap->flags |= MR_LP_ADV_NEXT_PAGE;
5334 ap->link_time = ap->cur_time;
5336 ap->flags ^= (MR_TOGGLE_TX);
5337 if (ap->rxconfig & 0x0008)
5338 ap->flags |= MR_TOGGLE_RX;
5339 if (ap->rxconfig & ANEG_CFG_NP)
5340 ap->flags |= MR_NP_RX;
5341 ap->flags |= MR_PAGE_RX;
5343 ap->state = ANEG_STATE_COMPLETE_ACK;
5344 ret = ANEG_TIMER_ENAB;
5347 case ANEG_STATE_COMPLETE_ACK:
5348 if (ap->ability_match != 0 &&
5349 ap->rxconfig == 0) {
5350 ap->state = ANEG_STATE_AN_ENABLE;
5353 delta = ap->cur_time - ap->link_time;
5354 if (delta > ANEG_STATE_SETTLE_TIME) {
5355 if (!(ap->flags & (MR_LP_ADV_NEXT_PAGE))) {
5356 ap->state = ANEG_STATE_IDLE_DETECT_INIT;
5358 if ((ap->txconfig & ANEG_CFG_NP) == 0 &&
5359 !(ap->flags & MR_NP_RX)) {
5360 ap->state = ANEG_STATE_IDLE_DETECT_INIT;
5368 case ANEG_STATE_IDLE_DETECT_INIT:
5369 ap->link_time = ap->cur_time;
5370 tp->mac_mode &= ~MAC_MODE_SEND_CONFIGS;
5371 tw32_f(MAC_MODE, tp->mac_mode);
5374 ap->state = ANEG_STATE_IDLE_DETECT;
5375 ret = ANEG_TIMER_ENAB;
5378 case ANEG_STATE_IDLE_DETECT:
5379 if (ap->ability_match != 0 &&
5380 ap->rxconfig == 0) {
5381 ap->state = ANEG_STATE_AN_ENABLE;
5384 delta = ap->cur_time - ap->link_time;
5385 if (delta > ANEG_STATE_SETTLE_TIME) {
5386 /* XXX another gem from the Broadcom driver :( */
5387 ap->state = ANEG_STATE_LINK_OK;
5391 case ANEG_STATE_LINK_OK:
5392 ap->flags |= (MR_AN_COMPLETE | MR_LINK_OK);
5396 case ANEG_STATE_NEXT_PAGE_WAIT_INIT:
5397 /* ??? unimplemented */
5400 case ANEG_STATE_NEXT_PAGE_WAIT:
5401 /* ??? unimplemented */
5412 static int fiber_autoneg(struct tg3 *tp, u32 *txflags, u32 *rxflags)
5415 struct tg3_fiber_aneginfo aninfo;
5416 int status = ANEG_FAILED;
5420 tw32_f(MAC_TX_AUTO_NEG, 0);
5422 tmp = tp->mac_mode & ~MAC_MODE_PORT_MODE_MASK;
5423 tw32_f(MAC_MODE, tmp | MAC_MODE_PORT_MODE_GMII);
5426 tw32_f(MAC_MODE, tp->mac_mode | MAC_MODE_SEND_CONFIGS);
5429 memset(&aninfo, 0, sizeof(aninfo));
5430 aninfo.flags |= MR_AN_ENABLE;
5431 aninfo.state = ANEG_STATE_UNKNOWN;
5432 aninfo.cur_time = 0;
5434 while (++tick < 195000) {
5435 status = tg3_fiber_aneg_smachine(tp, &aninfo);
5436 if (status == ANEG_DONE || status == ANEG_FAILED)
5442 tp->mac_mode &= ~MAC_MODE_SEND_CONFIGS;
5443 tw32_f(MAC_MODE, tp->mac_mode);
5446 *txflags = aninfo.txconfig;
5447 *rxflags = aninfo.flags;
5449 if (status == ANEG_DONE &&
5450 (aninfo.flags & (MR_AN_COMPLETE | MR_LINK_OK |
5451 MR_LP_ADV_FULL_DUPLEX)))
5457 static void tg3_init_bcm8002(struct tg3 *tp)
5459 u32 mac_status = tr32(MAC_STATUS);
5462 /* Reset when initting first time or we have a link. */
5463 if (tg3_flag(tp, INIT_COMPLETE) &&
5464 !(mac_status & MAC_STATUS_PCS_SYNCED))
5467 /* Set PLL lock range. */
5468 tg3_writephy(tp, 0x16, 0x8007);
5471 tg3_writephy(tp, MII_BMCR, BMCR_RESET);
5473 /* Wait for reset to complete. */
5474 /* XXX schedule_timeout() ... */
5475 for (i = 0; i < 500; i++)
5478 /* Config mode; select PMA/Ch 1 regs. */
5479 tg3_writephy(tp, 0x10, 0x8411);
5481 /* Enable auto-lock and comdet, select txclk for tx. */
5482 tg3_writephy(tp, 0x11, 0x0a10);
5484 tg3_writephy(tp, 0x18, 0x00a0);
5485 tg3_writephy(tp, 0x16, 0x41ff);
5487 /* Assert and deassert POR. */
5488 tg3_writephy(tp, 0x13, 0x0400);
5490 tg3_writephy(tp, 0x13, 0x0000);
5492 tg3_writephy(tp, 0x11, 0x0a50);
5494 tg3_writephy(tp, 0x11, 0x0a10);
5496 /* Wait for signal to stabilize */
5497 /* XXX schedule_timeout() ... */
5498 for (i = 0; i < 15000; i++)
5501 /* Deselect the channel register so we can read the PHYID
5504 tg3_writephy(tp, 0x10, 0x8011);
5507 static bool tg3_setup_fiber_hw_autoneg(struct tg3 *tp, u32 mac_status)
5510 bool current_link_up;
5511 u32 sg_dig_ctrl, sg_dig_status;
5512 u32 serdes_cfg, expected_sg_dig_ctrl;
5513 int workaround, port_a;
5516 expected_sg_dig_ctrl = 0;
5519 current_link_up = false;
5521 if (tg3_chip_rev_id(tp) != CHIPREV_ID_5704_A0 &&
5522 tg3_chip_rev_id(tp) != CHIPREV_ID_5704_A1) {
5524 if (tr32(TG3PCI_DUAL_MAC_CTRL) & DUAL_MAC_CTRL_ID)
5527 /* preserve bits 0-11,13,14 for signal pre-emphasis */
5528 /* preserve bits 20-23 for voltage regulator */
5529 serdes_cfg = tr32(MAC_SERDES_CFG) & 0x00f06fff;
5532 sg_dig_ctrl = tr32(SG_DIG_CTRL);
5534 if (tp->link_config.autoneg != AUTONEG_ENABLE) {
5535 if (sg_dig_ctrl & SG_DIG_USING_HW_AUTONEG) {
5537 u32 val = serdes_cfg;
5543 tw32_f(MAC_SERDES_CFG, val);
5546 tw32_f(SG_DIG_CTRL, SG_DIG_COMMON_SETUP);
5548 if (mac_status & MAC_STATUS_PCS_SYNCED) {
5549 tg3_setup_flow_control(tp, 0, 0);
5550 current_link_up = true;
5555 /* Want auto-negotiation. */
5556 expected_sg_dig_ctrl = SG_DIG_USING_HW_AUTONEG | SG_DIG_COMMON_SETUP;
5558 flowctrl = tg3_advert_flowctrl_1000X(tp->link_config.flowctrl);
5559 if (flowctrl & ADVERTISE_1000XPAUSE)
5560 expected_sg_dig_ctrl |= SG_DIG_PAUSE_CAP;
5561 if (flowctrl & ADVERTISE_1000XPSE_ASYM)
5562 expected_sg_dig_ctrl |= SG_DIG_ASYM_PAUSE;
5564 if (sg_dig_ctrl != expected_sg_dig_ctrl) {
5565 if ((tp->phy_flags & TG3_PHYFLG_PARALLEL_DETECT) &&
5566 tp->serdes_counter &&
5567 ((mac_status & (MAC_STATUS_PCS_SYNCED |
5568 MAC_STATUS_RCVD_CFG)) ==
5569 MAC_STATUS_PCS_SYNCED)) {
5570 tp->serdes_counter--;
5571 current_link_up = true;
5576 tw32_f(MAC_SERDES_CFG, serdes_cfg | 0xc011000);
5577 tw32_f(SG_DIG_CTRL, expected_sg_dig_ctrl | SG_DIG_SOFT_RESET);
5579 tw32_f(SG_DIG_CTRL, expected_sg_dig_ctrl);
5581 tp->serdes_counter = SERDES_AN_TIMEOUT_5704S;
5582 tp->phy_flags &= ~TG3_PHYFLG_PARALLEL_DETECT;
5583 } else if (mac_status & (MAC_STATUS_PCS_SYNCED |
5584 MAC_STATUS_SIGNAL_DET)) {
5585 sg_dig_status = tr32(SG_DIG_STATUS);
5586 mac_status = tr32(MAC_STATUS);
5588 if ((sg_dig_status & SG_DIG_AUTONEG_COMPLETE) &&
5589 (mac_status & MAC_STATUS_PCS_SYNCED)) {
5590 u32 local_adv = 0, remote_adv = 0;
5592 if (sg_dig_ctrl & SG_DIG_PAUSE_CAP)
5593 local_adv |= ADVERTISE_1000XPAUSE;
5594 if (sg_dig_ctrl & SG_DIG_ASYM_PAUSE)
5595 local_adv |= ADVERTISE_1000XPSE_ASYM;
5597 if (sg_dig_status & SG_DIG_PARTNER_PAUSE_CAPABLE)
5598 remote_adv |= LPA_1000XPAUSE;
5599 if (sg_dig_status & SG_DIG_PARTNER_ASYM_PAUSE)
5600 remote_adv |= LPA_1000XPAUSE_ASYM;
5602 tp->link_config.rmt_adv =
5603 mii_adv_to_ethtool_adv_x(remote_adv);
5605 tg3_setup_flow_control(tp, local_adv, remote_adv);
5606 current_link_up = true;
5607 tp->serdes_counter = 0;
5608 tp->phy_flags &= ~TG3_PHYFLG_PARALLEL_DETECT;
5609 } else if (!(sg_dig_status & SG_DIG_AUTONEG_COMPLETE)) {
5610 if (tp->serdes_counter)
5611 tp->serdes_counter--;
5614 u32 val = serdes_cfg;
5621 tw32_f(MAC_SERDES_CFG, val);
5624 tw32_f(SG_DIG_CTRL, SG_DIG_COMMON_SETUP);
5627 /* Link parallel detection - link is up */
5628 /* only if we have PCS_SYNC and not */
5629 /* receiving config code words */
5630 mac_status = tr32(MAC_STATUS);
5631 if ((mac_status & MAC_STATUS_PCS_SYNCED) &&
5632 !(mac_status & MAC_STATUS_RCVD_CFG)) {
5633 tg3_setup_flow_control(tp, 0, 0);
5634 current_link_up = true;
5636 TG3_PHYFLG_PARALLEL_DETECT;
5637 tp->serdes_counter =
5638 SERDES_PARALLEL_DET_TIMEOUT;
5640 goto restart_autoneg;
5644 tp->serdes_counter = SERDES_AN_TIMEOUT_5704S;
5645 tp->phy_flags &= ~TG3_PHYFLG_PARALLEL_DETECT;
5649 return current_link_up;
5652 static bool tg3_setup_fiber_by_hand(struct tg3 *tp, u32 mac_status)
5654 bool current_link_up = false;
5656 if (!(mac_status & MAC_STATUS_PCS_SYNCED))
5659 if (tp->link_config.autoneg == AUTONEG_ENABLE) {
5660 u32 txflags, rxflags;
5663 if (fiber_autoneg(tp, &txflags, &rxflags)) {
5664 u32 local_adv = 0, remote_adv = 0;
5666 if (txflags & ANEG_CFG_PS1)
5667 local_adv |= ADVERTISE_1000XPAUSE;
5668 if (txflags & ANEG_CFG_PS2)
5669 local_adv |= ADVERTISE_1000XPSE_ASYM;
5671 if (rxflags & MR_LP_ADV_SYM_PAUSE)
5672 remote_adv |= LPA_1000XPAUSE;
5673 if (rxflags & MR_LP_ADV_ASYM_PAUSE)
5674 remote_adv |= LPA_1000XPAUSE_ASYM;
5676 tp->link_config.rmt_adv =
5677 mii_adv_to_ethtool_adv_x(remote_adv);
5679 tg3_setup_flow_control(tp, local_adv, remote_adv);
5681 current_link_up = true;
5683 for (i = 0; i < 30; i++) {
5686 (MAC_STATUS_SYNC_CHANGED |
5687 MAC_STATUS_CFG_CHANGED));
5689 if ((tr32(MAC_STATUS) &
5690 (MAC_STATUS_SYNC_CHANGED |
5691 MAC_STATUS_CFG_CHANGED)) == 0)
5695 mac_status = tr32(MAC_STATUS);
5696 if (!current_link_up &&
5697 (mac_status & MAC_STATUS_PCS_SYNCED) &&
5698 !(mac_status & MAC_STATUS_RCVD_CFG))
5699 current_link_up = true;
5701 tg3_setup_flow_control(tp, 0, 0);
5703 /* Forcing 1000FD link up. */
5704 current_link_up = true;
5706 tw32_f(MAC_MODE, (tp->mac_mode | MAC_MODE_SEND_CONFIGS));
5709 tw32_f(MAC_MODE, tp->mac_mode);
5714 return current_link_up;
5717 static int tg3_setup_fiber_phy(struct tg3 *tp, bool force_reset)
5720 u16 orig_active_speed;
5721 u8 orig_active_duplex;
5723 bool current_link_up;
5726 orig_pause_cfg = tp->link_config.active_flowctrl;
5727 orig_active_speed = tp->link_config.active_speed;
5728 orig_active_duplex = tp->link_config.active_duplex;
5730 if (!tg3_flag(tp, HW_AUTONEG) &&
5732 tg3_flag(tp, INIT_COMPLETE)) {
5733 mac_status = tr32(MAC_STATUS);
5734 mac_status &= (MAC_STATUS_PCS_SYNCED |
5735 MAC_STATUS_SIGNAL_DET |
5736 MAC_STATUS_CFG_CHANGED |
5737 MAC_STATUS_RCVD_CFG);
5738 if (mac_status == (MAC_STATUS_PCS_SYNCED |
5739 MAC_STATUS_SIGNAL_DET)) {
5740 tw32_f(MAC_STATUS, (MAC_STATUS_SYNC_CHANGED |
5741 MAC_STATUS_CFG_CHANGED));
5746 tw32_f(MAC_TX_AUTO_NEG, 0);
5748 tp->mac_mode &= ~(MAC_MODE_PORT_MODE_MASK | MAC_MODE_HALF_DUPLEX);
5749 tp->mac_mode |= MAC_MODE_PORT_MODE_TBI;
5750 tw32_f(MAC_MODE, tp->mac_mode);
5753 if (tp->phy_id == TG3_PHY_ID_BCM8002)
5754 tg3_init_bcm8002(tp);
5756 /* Enable link change event even when serdes polling. */
5757 tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
5760 current_link_up = false;
5761 tp->link_config.rmt_adv = 0;
5762 mac_status = tr32(MAC_STATUS);
5764 if (tg3_flag(tp, HW_AUTONEG))
5765 current_link_up = tg3_setup_fiber_hw_autoneg(tp, mac_status);
5767 current_link_up = tg3_setup_fiber_by_hand(tp, mac_status);
5769 tp->napi[0].hw_status->status =
5770 (SD_STATUS_UPDATED |
5771 (tp->napi[0].hw_status->status & ~SD_STATUS_LINK_CHG));
5773 for (i = 0; i < 100; i++) {
5774 tw32_f(MAC_STATUS, (MAC_STATUS_SYNC_CHANGED |
5775 MAC_STATUS_CFG_CHANGED));
5777 if ((tr32(MAC_STATUS) & (MAC_STATUS_SYNC_CHANGED |
5778 MAC_STATUS_CFG_CHANGED |
5779 MAC_STATUS_LNKSTATE_CHANGED)) == 0)
5783 mac_status = tr32(MAC_STATUS);
5784 if ((mac_status & MAC_STATUS_PCS_SYNCED) == 0) {
5785 current_link_up = false;
5786 if (tp->link_config.autoneg == AUTONEG_ENABLE &&
5787 tp->serdes_counter == 0) {
5788 tw32_f(MAC_MODE, (tp->mac_mode |
5789 MAC_MODE_SEND_CONFIGS));
5791 tw32_f(MAC_MODE, tp->mac_mode);
5795 if (current_link_up) {
5796 tp->link_config.active_speed = SPEED_1000;
5797 tp->link_config.active_duplex = DUPLEX_FULL;
5798 tw32(MAC_LED_CTRL, (tp->led_ctrl |
5799 LED_CTRL_LNKLED_OVERRIDE |
5800 LED_CTRL_1000MBPS_ON));
5802 tp->link_config.active_speed = SPEED_UNKNOWN;
5803 tp->link_config.active_duplex = DUPLEX_UNKNOWN;
5804 tw32(MAC_LED_CTRL, (tp->led_ctrl |
5805 LED_CTRL_LNKLED_OVERRIDE |
5806 LED_CTRL_TRAFFIC_OVERRIDE));
5809 if (!tg3_test_and_report_link_chg(tp, current_link_up)) {
5810 u32 now_pause_cfg = tp->link_config.active_flowctrl;
5811 if (orig_pause_cfg != now_pause_cfg ||
5812 orig_active_speed != tp->link_config.active_speed ||
5813 orig_active_duplex != tp->link_config.active_duplex)
5814 tg3_link_report(tp);
5820 static int tg3_setup_fiber_mii_phy(struct tg3 *tp, bool force_reset)
5824 u16 current_speed = SPEED_UNKNOWN;
5825 u8 current_duplex = DUPLEX_UNKNOWN;
5826 bool current_link_up = false;
5827 u32 local_adv, remote_adv, sgsr;
5829 if ((tg3_asic_rev(tp) == ASIC_REV_5719 ||
5830 tg3_asic_rev(tp) == ASIC_REV_5720) &&
5831 !tg3_readphy(tp, SERDES_TG3_1000X_STATUS, &sgsr) &&
5832 (sgsr & SERDES_TG3_SGMII_MODE)) {
5837 tp->mac_mode &= ~MAC_MODE_PORT_MODE_MASK;
5839 if (!(sgsr & SERDES_TG3_LINK_UP)) {
5840 tp->mac_mode |= MAC_MODE_PORT_MODE_GMII;
5842 current_link_up = true;
5843 if (sgsr & SERDES_TG3_SPEED_1000) {
5844 current_speed = SPEED_1000;
5845 tp->mac_mode |= MAC_MODE_PORT_MODE_GMII;
5846 } else if (sgsr & SERDES_TG3_SPEED_100) {
5847 current_speed = SPEED_100;
5848 tp->mac_mode |= MAC_MODE_PORT_MODE_MII;
5850 current_speed = SPEED_10;
5851 tp->mac_mode |= MAC_MODE_PORT_MODE_MII;
5854 if (sgsr & SERDES_TG3_FULL_DUPLEX)
5855 current_duplex = DUPLEX_FULL;
5857 current_duplex = DUPLEX_HALF;
5860 tw32_f(MAC_MODE, tp->mac_mode);
5863 tg3_clear_mac_status(tp);
5865 goto fiber_setup_done;
5868 tp->mac_mode |= MAC_MODE_PORT_MODE_GMII;
5869 tw32_f(MAC_MODE, tp->mac_mode);
5872 tg3_clear_mac_status(tp);
5877 tp->link_config.rmt_adv = 0;
5879 err |= tg3_readphy(tp, MII_BMSR, &bmsr);
5880 err |= tg3_readphy(tp, MII_BMSR, &bmsr);
5881 if (tg3_asic_rev(tp) == ASIC_REV_5714) {
5882 if (tr32(MAC_TX_STATUS) & TX_STATUS_LINK_UP)
5883 bmsr |= BMSR_LSTATUS;
5885 bmsr &= ~BMSR_LSTATUS;
5888 err |= tg3_readphy(tp, MII_BMCR, &bmcr);
5890 if ((tp->link_config.autoneg == AUTONEG_ENABLE) && !force_reset &&
5891 (tp->phy_flags & TG3_PHYFLG_PARALLEL_DETECT)) {
5892 /* do nothing, just check for link up at the end */
5893 } else if (tp->link_config.autoneg == AUTONEG_ENABLE) {
5896 err |= tg3_readphy(tp, MII_ADVERTISE, &adv);
5897 newadv = adv & ~(ADVERTISE_1000XFULL | ADVERTISE_1000XHALF |
5898 ADVERTISE_1000XPAUSE |
5899 ADVERTISE_1000XPSE_ASYM |
5902 newadv |= tg3_advert_flowctrl_1000X(tp->link_config.flowctrl);
5903 newadv |= ethtool_adv_to_mii_adv_x(tp->link_config.advertising);
5905 if ((newadv != adv) || !(bmcr & BMCR_ANENABLE)) {
5906 tg3_writephy(tp, MII_ADVERTISE, newadv);
5907 bmcr |= BMCR_ANENABLE | BMCR_ANRESTART;
5908 tg3_writephy(tp, MII_BMCR, bmcr);
5910 tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
5911 tp->serdes_counter = SERDES_AN_TIMEOUT_5714S;
5912 tp->phy_flags &= ~TG3_PHYFLG_PARALLEL_DETECT;
5919 bmcr &= ~BMCR_SPEED1000;
5920 new_bmcr = bmcr & ~(BMCR_ANENABLE | BMCR_FULLDPLX);
5922 if (tp->link_config.duplex == DUPLEX_FULL)
5923 new_bmcr |= BMCR_FULLDPLX;
5925 if (new_bmcr != bmcr) {
5926 /* BMCR_SPEED1000 is a reserved bit that needs
5927 * to be set on write.
5929 new_bmcr |= BMCR_SPEED1000;
5931 /* Force a linkdown */
5935 err |= tg3_readphy(tp, MII_ADVERTISE, &adv);
5936 adv &= ~(ADVERTISE_1000XFULL |
5937 ADVERTISE_1000XHALF |
5939 tg3_writephy(tp, MII_ADVERTISE, adv);
5940 tg3_writephy(tp, MII_BMCR, bmcr |
5944 tg3_carrier_off(tp);
5946 tg3_writephy(tp, MII_BMCR, new_bmcr);
5948 err |= tg3_readphy(tp, MII_BMSR, &bmsr);
5949 err |= tg3_readphy(tp, MII_BMSR, &bmsr);
5950 if (tg3_asic_rev(tp) == ASIC_REV_5714) {
5951 if (tr32(MAC_TX_STATUS) & TX_STATUS_LINK_UP)
5952 bmsr |= BMSR_LSTATUS;
5954 bmsr &= ~BMSR_LSTATUS;
5956 tp->phy_flags &= ~TG3_PHYFLG_PARALLEL_DETECT;
5960 if (bmsr & BMSR_LSTATUS) {
5961 current_speed = SPEED_1000;
5962 current_link_up = true;
5963 if (bmcr & BMCR_FULLDPLX)
5964 current_duplex = DUPLEX_FULL;
5966 current_duplex = DUPLEX_HALF;
5971 if (bmcr & BMCR_ANENABLE) {
5974 err |= tg3_readphy(tp, MII_ADVERTISE, &local_adv);
5975 err |= tg3_readphy(tp, MII_LPA, &remote_adv);
5976 common = local_adv & remote_adv;
5977 if (common & (ADVERTISE_1000XHALF |
5978 ADVERTISE_1000XFULL)) {
5979 if (common & ADVERTISE_1000XFULL)
5980 current_duplex = DUPLEX_FULL;
5982 current_duplex = DUPLEX_HALF;
5984 tp->link_config.rmt_adv =
5985 mii_adv_to_ethtool_adv_x(remote_adv);
5986 } else if (!tg3_flag(tp, 5780_CLASS)) {
5987 /* Link is up via parallel detect */
5989 current_link_up = false;
5995 if (current_link_up && current_duplex == DUPLEX_FULL)
5996 tg3_setup_flow_control(tp, local_adv, remote_adv);
5998 tp->mac_mode &= ~MAC_MODE_HALF_DUPLEX;
5999 if (tp->link_config.active_duplex == DUPLEX_HALF)
6000 tp->mac_mode |= MAC_MODE_HALF_DUPLEX;
6002 tw32_f(MAC_MODE, tp->mac_mode);
6005 tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
6007 tp->link_config.active_speed = current_speed;
6008 tp->link_config.active_duplex = current_duplex;
6010 tg3_test_and_report_link_chg(tp, current_link_up);
6014 static void tg3_serdes_parallel_detect(struct tg3 *tp)
6016 if (tp->serdes_counter) {
6017 /* Give autoneg time to complete. */
6018 tp->serdes_counter--;
6023 (tp->link_config.autoneg == AUTONEG_ENABLE)) {
6026 tg3_readphy(tp, MII_BMCR, &bmcr);
6027 if (bmcr & BMCR_ANENABLE) {
6030 /* Select shadow register 0x1f */
6031 tg3_writephy(tp, MII_TG3_MISC_SHDW, 0x7c00);
6032 tg3_readphy(tp, MII_TG3_MISC_SHDW, &phy1);
6034 /* Select expansion interrupt status register */
6035 tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
6036 MII_TG3_DSP_EXP1_INT_STAT);
6037 tg3_readphy(tp, MII_TG3_DSP_RW_PORT, &phy2);
6038 tg3_readphy(tp, MII_TG3_DSP_RW_PORT, &phy2);
6040 if ((phy1 & 0x10) && !(phy2 & 0x20)) {
6041 /* We have signal detect and not receiving
6042 * config code words, link is up by parallel
6046 bmcr &= ~BMCR_ANENABLE;
6047 bmcr |= BMCR_SPEED1000 | BMCR_FULLDPLX;
6048 tg3_writephy(tp, MII_BMCR, bmcr);
6049 tp->phy_flags |= TG3_PHYFLG_PARALLEL_DETECT;
6052 } else if (tp->link_up &&
6053 (tp->link_config.autoneg == AUTONEG_ENABLE) &&
6054 (tp->phy_flags & TG3_PHYFLG_PARALLEL_DETECT)) {
6057 /* Select expansion interrupt status register */
6058 tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
6059 MII_TG3_DSP_EXP1_INT_STAT);
6060 tg3_readphy(tp, MII_TG3_DSP_RW_PORT, &phy2);
6064 /* Config code words received, turn on autoneg. */
6065 tg3_readphy(tp, MII_BMCR, &bmcr);
6066 tg3_writephy(tp, MII_BMCR, bmcr | BMCR_ANENABLE);
6068 tp->phy_flags &= ~TG3_PHYFLG_PARALLEL_DETECT;
6074 static int tg3_setup_phy(struct tg3 *tp, bool force_reset)
6079 if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES)
6080 err = tg3_setup_fiber_phy(tp, force_reset);
6081 else if (tp->phy_flags & TG3_PHYFLG_MII_SERDES)
6082 err = tg3_setup_fiber_mii_phy(tp, force_reset);
6084 err = tg3_setup_copper_phy(tp, force_reset);
6086 if (tg3_chip_rev(tp) == CHIPREV_5784_AX) {
6089 val = tr32(TG3_CPMU_CLCK_STAT) & CPMU_CLCK_STAT_MAC_CLCK_MASK;
6090 if (val == CPMU_CLCK_STAT_MAC_CLCK_62_5)
6092 else if (val == CPMU_CLCK_STAT_MAC_CLCK_6_25)
6097 val = tr32(GRC_MISC_CFG) & ~GRC_MISC_CFG_PRESCALAR_MASK;
6098 val |= (scale << GRC_MISC_CFG_PRESCALAR_SHIFT);
6099 tw32(GRC_MISC_CFG, val);
6102 val = (2 << TX_LENGTHS_IPG_CRS_SHIFT) |
6103 (6 << TX_LENGTHS_IPG_SHIFT);
6104 if (tg3_asic_rev(tp) == ASIC_REV_5720 ||
6105 tg3_asic_rev(tp) == ASIC_REV_5762)
6106 val |= tr32(MAC_TX_LENGTHS) &
6107 (TX_LENGTHS_JMB_FRM_LEN_MSK |
6108 TX_LENGTHS_CNT_DWN_VAL_MSK);
6110 if (tp->link_config.active_speed == SPEED_1000 &&
6111 tp->link_config.active_duplex == DUPLEX_HALF)
6112 tw32(MAC_TX_LENGTHS, val |
6113 (0xff << TX_LENGTHS_SLOT_TIME_SHIFT));
6115 tw32(MAC_TX_LENGTHS, val |
6116 (32 << TX_LENGTHS_SLOT_TIME_SHIFT));
6118 if (!tg3_flag(tp, 5705_PLUS)) {
6120 tw32(HOSTCC_STAT_COAL_TICKS,
6121 tp->coal.stats_block_coalesce_usecs);
6123 tw32(HOSTCC_STAT_COAL_TICKS, 0);
6127 if (tg3_flag(tp, ASPM_WORKAROUND)) {
6128 val = tr32(PCIE_PWR_MGMT_THRESH);
6130 val = (val & ~PCIE_PWR_MGMT_L1_THRESH_MSK) |
6133 val |= PCIE_PWR_MGMT_L1_THRESH_MSK;
6134 tw32(PCIE_PWR_MGMT_THRESH, val);
6140 /* tp->lock must be held */
6141 static u64 tg3_refclk_read(struct tg3 *tp)
6143 u64 stamp = tr32(TG3_EAV_REF_CLCK_LSB);
6144 return stamp | (u64)tr32(TG3_EAV_REF_CLCK_MSB) << 32;
6147 /* tp->lock must be held */
6148 static void tg3_refclk_write(struct tg3 *tp, u64 newval)
6150 u32 clock_ctl = tr32(TG3_EAV_REF_CLCK_CTL);
6152 tw32(TG3_EAV_REF_CLCK_CTL, clock_ctl | TG3_EAV_REF_CLCK_CTL_STOP);
6153 tw32(TG3_EAV_REF_CLCK_LSB, newval & 0xffffffff);
6154 tw32(TG3_EAV_REF_CLCK_MSB, newval >> 32);
6155 tw32_f(TG3_EAV_REF_CLCK_CTL, clock_ctl | TG3_EAV_REF_CLCK_CTL_RESUME);
6158 static inline void tg3_full_lock(struct tg3 *tp, int irq_sync);
6159 static inline void tg3_full_unlock(struct tg3 *tp);
6160 static int tg3_get_ts_info(struct net_device *dev, struct ethtool_ts_info *info)
6162 struct tg3 *tp = netdev_priv(dev);
6164 info->so_timestamping = SOF_TIMESTAMPING_TX_SOFTWARE |
6165 SOF_TIMESTAMPING_RX_SOFTWARE |
6166 SOF_TIMESTAMPING_SOFTWARE;
6168 if (tg3_flag(tp, PTP_CAPABLE)) {
6169 info->so_timestamping |= SOF_TIMESTAMPING_TX_HARDWARE |
6170 SOF_TIMESTAMPING_RX_HARDWARE |
6171 SOF_TIMESTAMPING_RAW_HARDWARE;
6175 info->phc_index = ptp_clock_index(tp->ptp_clock);
6177 info->phc_index = -1;
6179 info->tx_types = (1 << HWTSTAMP_TX_OFF) | (1 << HWTSTAMP_TX_ON);
6181 info->rx_filters = (1 << HWTSTAMP_FILTER_NONE) |
6182 (1 << HWTSTAMP_FILTER_PTP_V1_L4_EVENT) |
6183 (1 << HWTSTAMP_FILTER_PTP_V2_L2_EVENT) |
6184 (1 << HWTSTAMP_FILTER_PTP_V2_L4_EVENT);
6188 static int tg3_ptp_adjfreq(struct ptp_clock_info *ptp, s32 ppb)
6190 struct tg3 *tp = container_of(ptp, struct tg3, ptp_info);
6191 bool neg_adj = false;
6199 /* Frequency adjustment is performed using hardware with a 24 bit
6200 * accumulator and a programmable correction value. On each clk, the
6201 * correction value gets added to the accumulator and when it
6202 * overflows, the time counter is incremented/decremented.
6204 * So conversion from ppb to correction value is
6205 * ppb * (1 << 24) / 1000000000
6207 correction = div_u64((u64)ppb * (1 << 24), 1000000000ULL) &
6208 TG3_EAV_REF_CLK_CORRECT_MASK;
6210 tg3_full_lock(tp, 0);
6213 tw32(TG3_EAV_REF_CLK_CORRECT_CTL,
6214 TG3_EAV_REF_CLK_CORRECT_EN |
6215 (neg_adj ? TG3_EAV_REF_CLK_CORRECT_NEG : 0) | correction);
6217 tw32(TG3_EAV_REF_CLK_CORRECT_CTL, 0);
6219 tg3_full_unlock(tp);
6224 static int tg3_ptp_adjtime(struct ptp_clock_info *ptp, s64 delta)
6226 struct tg3 *tp = container_of(ptp, struct tg3, ptp_info);
6228 tg3_full_lock(tp, 0);
6229 tp->ptp_adjust += delta;
6230 tg3_full_unlock(tp);
6235 static int tg3_ptp_gettime(struct ptp_clock_info *ptp, struct timespec64 *ts)
6238 struct tg3 *tp = container_of(ptp, struct tg3, ptp_info);
6240 tg3_full_lock(tp, 0);
6241 ns = tg3_refclk_read(tp);
6242 ns += tp->ptp_adjust;
6243 tg3_full_unlock(tp);
6245 *ts = ns_to_timespec64(ns);
6250 static int tg3_ptp_settime(struct ptp_clock_info *ptp,
6251 const struct timespec64 *ts)
6254 struct tg3 *tp = container_of(ptp, struct tg3, ptp_info);
6256 ns = timespec64_to_ns(ts);
6258 tg3_full_lock(tp, 0);
6259 tg3_refclk_write(tp, ns);
6261 tg3_full_unlock(tp);
6266 static int tg3_ptp_enable(struct ptp_clock_info *ptp,
6267 struct ptp_clock_request *rq, int on)
6269 struct tg3 *tp = container_of(ptp, struct tg3, ptp_info);
6274 case PTP_CLK_REQ_PEROUT:
6275 if (rq->perout.index != 0)
6278 tg3_full_lock(tp, 0);
6279 clock_ctl = tr32(TG3_EAV_REF_CLCK_CTL);
6280 clock_ctl &= ~TG3_EAV_CTL_TSYNC_GPIO_MASK;
6285 nsec = rq->perout.start.sec * 1000000000ULL +
6286 rq->perout.start.nsec;
6288 if (rq->perout.period.sec || rq->perout.period.nsec) {
6289 netdev_warn(tp->dev,
6290 "Device supports only a one-shot timesync output, period must be 0\n");
6295 if (nsec & (1ULL << 63)) {
6296 netdev_warn(tp->dev,
6297 "Start value (nsec) is over limit. Maximum size of start is only 63 bits\n");
6302 tw32(TG3_EAV_WATCHDOG0_LSB, (nsec & 0xffffffff));
6303 tw32(TG3_EAV_WATCHDOG0_MSB,
6304 TG3_EAV_WATCHDOG0_EN |
6305 ((nsec >> 32) & TG3_EAV_WATCHDOG_MSB_MASK));
6307 tw32(TG3_EAV_REF_CLCK_CTL,
6308 clock_ctl | TG3_EAV_CTL_TSYNC_WDOG0);
6310 tw32(TG3_EAV_WATCHDOG0_MSB, 0);
6311 tw32(TG3_EAV_REF_CLCK_CTL, clock_ctl);
6315 tg3_full_unlock(tp);
6325 static const struct ptp_clock_info tg3_ptp_caps = {
6326 .owner = THIS_MODULE,
6327 .name = "tg3 clock",
6328 .max_adj = 250000000,
6334 .adjfreq = tg3_ptp_adjfreq,
6335 .adjtime = tg3_ptp_adjtime,
6336 .gettime64 = tg3_ptp_gettime,
6337 .settime64 = tg3_ptp_settime,
6338 .enable = tg3_ptp_enable,
6341 static void tg3_hwclock_to_timestamp(struct tg3 *tp, u64 hwclock,
6342 struct skb_shared_hwtstamps *timestamp)
6344 memset(timestamp, 0, sizeof(struct skb_shared_hwtstamps));
6345 timestamp->hwtstamp = ns_to_ktime((hwclock & TG3_TSTAMP_MASK) +
6349 /* tp->lock must be held */
6350 static void tg3_ptp_init(struct tg3 *tp)
6352 if (!tg3_flag(tp, PTP_CAPABLE))
6355 /* Initialize the hardware clock to the system time. */
6356 tg3_refclk_write(tp, ktime_to_ns(ktime_get_real()));
6358 tp->ptp_info = tg3_ptp_caps;
6361 /* tp->lock must be held */
6362 static void tg3_ptp_resume(struct tg3 *tp)
6364 if (!tg3_flag(tp, PTP_CAPABLE))
6367 tg3_refclk_write(tp, ktime_to_ns(ktime_get_real()) + tp->ptp_adjust);
6371 static void tg3_ptp_fini(struct tg3 *tp)
6373 if (!tg3_flag(tp, PTP_CAPABLE) || !tp->ptp_clock)
6376 ptp_clock_unregister(tp->ptp_clock);
6377 tp->ptp_clock = NULL;
6381 static inline int tg3_irq_sync(struct tg3 *tp)
6383 return tp->irq_sync;
6386 static inline void tg3_rd32_loop(struct tg3 *tp, u32 *dst, u32 off, u32 len)
6390 dst = (u32 *)((u8 *)dst + off);
6391 for (i = 0; i < len; i += sizeof(u32))
6392 *dst++ = tr32(off + i);
6395 static void tg3_dump_legacy_regs(struct tg3 *tp, u32 *regs)
6397 tg3_rd32_loop(tp, regs, TG3PCI_VENDOR, 0xb0);
6398 tg3_rd32_loop(tp, regs, MAILBOX_INTERRUPT_0, 0x200);
6399 tg3_rd32_loop(tp, regs, MAC_MODE, 0x4f0);
6400 tg3_rd32_loop(tp, regs, SNDDATAI_MODE, 0xe0);
6401 tg3_rd32_loop(tp, regs, SNDDATAC_MODE, 0x04);
6402 tg3_rd32_loop(tp, regs, SNDBDS_MODE, 0x80);
6403 tg3_rd32_loop(tp, regs, SNDBDI_MODE, 0x48);
6404 tg3_rd32_loop(tp, regs, SNDBDC_MODE, 0x04);
6405 tg3_rd32_loop(tp, regs, RCVLPC_MODE, 0x20);
6406 tg3_rd32_loop(tp, regs, RCVLPC_SELLST_BASE, 0x15c);
6407 tg3_rd32_loop(tp, regs, RCVDBDI_MODE, 0x0c);
6408 tg3_rd32_loop(tp, regs, RCVDBDI_JUMBO_BD, 0x3c);
6409 tg3_rd32_loop(tp, regs, RCVDBDI_BD_PROD_IDX_0, 0x44);
6410 tg3_rd32_loop(tp, regs, RCVDCC_MODE, 0x04);
6411 tg3_rd32_loop(tp, regs, RCVBDI_MODE, 0x20);
6412 tg3_rd32_loop(tp, regs, RCVCC_MODE, 0x14);
6413 tg3_rd32_loop(tp, regs, RCVLSC_MODE, 0x08);
6414 tg3_rd32_loop(tp, regs, MBFREE_MODE, 0x08);
6415 tg3_rd32_loop(tp, regs, HOSTCC_MODE, 0x100);
6417 if (tg3_flag(tp, SUPPORT_MSIX))
6418 tg3_rd32_loop(tp, regs, HOSTCC_RXCOL_TICKS_VEC1, 0x180);
6420 tg3_rd32_loop(tp, regs, MEMARB_MODE, 0x10);
6421 tg3_rd32_loop(tp, regs, BUFMGR_MODE, 0x58);
6422 tg3_rd32_loop(tp, regs, RDMAC_MODE, 0x08);
6423 tg3_rd32_loop(tp, regs, WDMAC_MODE, 0x08);
6424 tg3_rd32_loop(tp, regs, RX_CPU_MODE, 0x04);
6425 tg3_rd32_loop(tp, regs, RX_CPU_STATE, 0x04);
6426 tg3_rd32_loop(tp, regs, RX_CPU_PGMCTR, 0x04);
6427 tg3_rd32_loop(tp, regs, RX_CPU_HWBKPT, 0x04);
6429 if (!tg3_flag(tp, 5705_PLUS)) {
6430 tg3_rd32_loop(tp, regs, TX_CPU_MODE, 0x04);
6431 tg3_rd32_loop(tp, regs, TX_CPU_STATE, 0x04);
6432 tg3_rd32_loop(tp, regs, TX_CPU_PGMCTR, 0x04);
6435 tg3_rd32_loop(tp, regs, GRCMBOX_INTERRUPT_0, 0x110);
6436 tg3_rd32_loop(tp, regs, FTQ_RESET, 0x120);
6437 tg3_rd32_loop(tp, regs, MSGINT_MODE, 0x0c);
6438 tg3_rd32_loop(tp, regs, DMAC_MODE, 0x04);
6439 tg3_rd32_loop(tp, regs, GRC_MODE, 0x4c);
6441 if (tg3_flag(tp, NVRAM))
6442 tg3_rd32_loop(tp, regs, NVRAM_CMD, 0x24);
6445 static void tg3_dump_state(struct tg3 *tp)
6450 regs = kzalloc(TG3_REG_BLK_SIZE, GFP_ATOMIC);
6454 if (tg3_flag(tp, PCI_EXPRESS)) {
6455 /* Read up to but not including private PCI registers */
6456 for (i = 0; i < TG3_PCIE_TLDLPL_PORT; i += sizeof(u32))
6457 regs[i / sizeof(u32)] = tr32(i);
6459 tg3_dump_legacy_regs(tp, regs);
6461 for (i = 0; i < TG3_REG_BLK_SIZE / sizeof(u32); i += 4) {
6462 if (!regs[i + 0] && !regs[i + 1] &&
6463 !regs[i + 2] && !regs[i + 3])
6466 netdev_err(tp->dev, "0x%08x: 0x%08x, 0x%08x, 0x%08x, 0x%08x\n",
6468 regs[i + 0], regs[i + 1], regs[i + 2], regs[i + 3]);
6473 for (i = 0; i < tp->irq_cnt; i++) {
6474 struct tg3_napi *tnapi = &tp->napi[i];
6476 /* SW status block */
6478 "%d: Host status block [%08x:%08x:(%04x:%04x:%04x):(%04x:%04x)]\n",
6480 tnapi->hw_status->status,
6481 tnapi->hw_status->status_tag,
6482 tnapi->hw_status->rx_jumbo_consumer,
6483 tnapi->hw_status->rx_consumer,
6484 tnapi->hw_status->rx_mini_consumer,
6485 tnapi->hw_status->idx[0].rx_producer,
6486 tnapi->hw_status->idx[0].tx_consumer);
6489 "%d: NAPI info [%08x:%08x:(%04x:%04x:%04x):%04x:(%04x:%04x:%04x:%04x)]\n",
6491 tnapi->last_tag, tnapi->last_irq_tag,
6492 tnapi->tx_prod, tnapi->tx_cons, tnapi->tx_pending,
6494 tnapi->prodring.rx_std_prod_idx,
6495 tnapi->prodring.rx_std_cons_idx,
6496 tnapi->prodring.rx_jmb_prod_idx,
6497 tnapi->prodring.rx_jmb_cons_idx);
6501 /* This is called whenever we suspect that the system chipset is re-
6502 * ordering the sequence of MMIO to the tx send mailbox. The symptom
6503 * is bogus tx completions. We try to recover by setting the
6504 * TG3_FLAG_MBOX_WRITE_REORDER flag and resetting the chip later
6507 static void tg3_tx_recover(struct tg3 *tp)
6509 BUG_ON(tg3_flag(tp, MBOX_WRITE_REORDER) ||
6510 tp->write32_tx_mbox == tg3_write_indirect_mbox);
6512 netdev_warn(tp->dev,
6513 "The system may be re-ordering memory-mapped I/O "
6514 "cycles to the network device, attempting to recover. "
6515 "Please report the problem to the driver maintainer "
6516 "and include system chipset information.\n");
6518 tg3_flag_set(tp, TX_RECOVERY_PENDING);
6521 static inline u32 tg3_tx_avail(struct tg3_napi *tnapi)
6523 /* Tell compiler to fetch tx indices from memory. */
6525 return tnapi->tx_pending -
6526 ((tnapi->tx_prod - tnapi->tx_cons) & (TG3_TX_RING_SIZE - 1));
6529 /* Tigon3 never reports partial packet sends. So we do not
6530 * need special logic to handle SKBs that have not had all
6531 * of their frags sent yet, like SunGEM does.
6533 static void tg3_tx(struct tg3_napi *tnapi)
6535 struct tg3 *tp = tnapi->tp;
6536 u32 hw_idx = tnapi->hw_status->idx[0].tx_consumer;
6537 u32 sw_idx = tnapi->tx_cons;
6538 struct netdev_queue *txq;
6539 int index = tnapi - tp->napi;
6540 unsigned int pkts_compl = 0, bytes_compl = 0;
6542 if (tg3_flag(tp, ENABLE_TSS))
6545 txq = netdev_get_tx_queue(tp->dev, index);
6547 while (sw_idx != hw_idx) {
6548 struct tg3_tx_ring_info *ri = &tnapi->tx_buffers[sw_idx];
6549 struct sk_buff *skb = ri->skb;
6552 if (unlikely(skb == NULL)) {
6557 if (tnapi->tx_ring[sw_idx].len_flags & TXD_FLAG_HWTSTAMP) {
6558 struct skb_shared_hwtstamps timestamp;
6559 u64 hwclock = tr32(TG3_TX_TSTAMP_LSB);
6560 hwclock |= (u64)tr32(TG3_TX_TSTAMP_MSB) << 32;
6562 tg3_hwclock_to_timestamp(tp, hwclock, ×tamp);
6564 skb_tstamp_tx(skb, ×tamp);
6567 pci_unmap_single(tp->pdev,
6568 dma_unmap_addr(ri, mapping),
6574 while (ri->fragmented) {
6575 ri->fragmented = false;
6576 sw_idx = NEXT_TX(sw_idx);
6577 ri = &tnapi->tx_buffers[sw_idx];
6580 sw_idx = NEXT_TX(sw_idx);
6582 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
6583 ri = &tnapi->tx_buffers[sw_idx];
6584 if (unlikely(ri->skb != NULL || sw_idx == hw_idx))
6587 pci_unmap_page(tp->pdev,
6588 dma_unmap_addr(ri, mapping),
6589 skb_frag_size(&skb_shinfo(skb)->frags[i]),
6592 while (ri->fragmented) {
6593 ri->fragmented = false;
6594 sw_idx = NEXT_TX(sw_idx);
6595 ri = &tnapi->tx_buffers[sw_idx];
6598 sw_idx = NEXT_TX(sw_idx);
6602 bytes_compl += skb->len;
6604 dev_consume_skb_any(skb);
6606 if (unlikely(tx_bug)) {
6612 netdev_tx_completed_queue(txq, pkts_compl, bytes_compl);
6614 tnapi->tx_cons = sw_idx;
6616 /* Need to make the tx_cons update visible to tg3_start_xmit()
6617 * before checking for netif_queue_stopped(). Without the
6618 * memory barrier, there is a small possibility that tg3_start_xmit()
6619 * will miss it and cause the queue to be stopped forever.
6623 if (unlikely(netif_tx_queue_stopped(txq) &&
6624 (tg3_tx_avail(tnapi) > TG3_TX_WAKEUP_THRESH(tnapi)))) {
6625 __netif_tx_lock(txq, smp_processor_id());
6626 if (netif_tx_queue_stopped(txq) &&
6627 (tg3_tx_avail(tnapi) > TG3_TX_WAKEUP_THRESH(tnapi)))
6628 netif_tx_wake_queue(txq);
6629 __netif_tx_unlock(txq);
6633 static void tg3_frag_free(bool is_frag, void *data)
6636 skb_free_frag(data);
6641 static void tg3_rx_data_free(struct tg3 *tp, struct ring_info *ri, u32 map_sz)
6643 unsigned int skb_size = SKB_DATA_ALIGN(map_sz + TG3_RX_OFFSET(tp)) +
6644 SKB_DATA_ALIGN(sizeof(struct skb_shared_info));
6649 pci_unmap_single(tp->pdev, dma_unmap_addr(ri, mapping),
6650 map_sz, PCI_DMA_FROMDEVICE);
6651 tg3_frag_free(skb_size <= PAGE_SIZE, ri->data);
6656 /* Returns size of skb allocated or < 0 on error.
6658 * We only need to fill in the address because the other members
6659 * of the RX descriptor are invariant, see tg3_init_rings.
6661 * Note the purposeful assymetry of cpu vs. chip accesses. For
6662 * posting buffers we only dirty the first cache line of the RX
6663 * descriptor (containing the address). Whereas for the RX status
6664 * buffers the cpu only reads the last cacheline of the RX descriptor
6665 * (to fetch the error flags, vlan tag, checksum, and opaque cookie).
6667 static int tg3_alloc_rx_data(struct tg3 *tp, struct tg3_rx_prodring_set *tpr,
6668 u32 opaque_key, u32 dest_idx_unmasked,
6669 unsigned int *frag_size)
6671 struct tg3_rx_buffer_desc *desc;
6672 struct ring_info *map;
6675 int skb_size, data_size, dest_idx;
6677 switch (opaque_key) {
6678 case RXD_OPAQUE_RING_STD:
6679 dest_idx = dest_idx_unmasked & tp->rx_std_ring_mask;
6680 desc = &tpr->rx_std[dest_idx];
6681 map = &tpr->rx_std_buffers[dest_idx];
6682 data_size = tp->rx_pkt_map_sz;
6685 case RXD_OPAQUE_RING_JUMBO:
6686 dest_idx = dest_idx_unmasked & tp->rx_jmb_ring_mask;
6687 desc = &tpr->rx_jmb[dest_idx].std;
6688 map = &tpr->rx_jmb_buffers[dest_idx];
6689 data_size = TG3_RX_JMB_MAP_SZ;
6696 /* Do not overwrite any of the map or rp information
6697 * until we are sure we can commit to a new buffer.
6699 * Callers depend upon this behavior and assume that
6700 * we leave everything unchanged if we fail.
6702 skb_size = SKB_DATA_ALIGN(data_size + TG3_RX_OFFSET(tp)) +
6703 SKB_DATA_ALIGN(sizeof(struct skb_shared_info));
6704 if (skb_size <= PAGE_SIZE) {
6705 data = netdev_alloc_frag(skb_size);
6706 *frag_size = skb_size;
6708 data = kmalloc(skb_size, GFP_ATOMIC);
6714 mapping = pci_map_single(tp->pdev,
6715 data + TG3_RX_OFFSET(tp),
6717 PCI_DMA_FROMDEVICE);
6718 if (unlikely(pci_dma_mapping_error(tp->pdev, mapping))) {
6719 tg3_frag_free(skb_size <= PAGE_SIZE, data);
6724 dma_unmap_addr_set(map, mapping, mapping);
6726 desc->addr_hi = ((u64)mapping >> 32);
6727 desc->addr_lo = ((u64)mapping & 0xffffffff);
6732 /* We only need to move over in the address because the other
6733 * members of the RX descriptor are invariant. See notes above
6734 * tg3_alloc_rx_data for full details.
6736 static void tg3_recycle_rx(struct tg3_napi *tnapi,
6737 struct tg3_rx_prodring_set *dpr,
6738 u32 opaque_key, int src_idx,
6739 u32 dest_idx_unmasked)
6741 struct tg3 *tp = tnapi->tp;
6742 struct tg3_rx_buffer_desc *src_desc, *dest_desc;
6743 struct ring_info *src_map, *dest_map;
6744 struct tg3_rx_prodring_set *spr = &tp->napi[0].prodring;
6747 switch (opaque_key) {
6748 case RXD_OPAQUE_RING_STD:
6749 dest_idx = dest_idx_unmasked & tp->rx_std_ring_mask;
6750 dest_desc = &dpr->rx_std[dest_idx];
6751 dest_map = &dpr->rx_std_buffers[dest_idx];
6752 src_desc = &spr->rx_std[src_idx];
6753 src_map = &spr->rx_std_buffers[src_idx];
6756 case RXD_OPAQUE_RING_JUMBO:
6757 dest_idx = dest_idx_unmasked & tp->rx_jmb_ring_mask;
6758 dest_desc = &dpr->rx_jmb[dest_idx].std;
6759 dest_map = &dpr->rx_jmb_buffers[dest_idx];
6760 src_desc = &spr->rx_jmb[src_idx].std;
6761 src_map = &spr->rx_jmb_buffers[src_idx];
6768 dest_map->data = src_map->data;
6769 dma_unmap_addr_set(dest_map, mapping,
6770 dma_unmap_addr(src_map, mapping));
6771 dest_desc->addr_hi = src_desc->addr_hi;
6772 dest_desc->addr_lo = src_desc->addr_lo;
6774 /* Ensure that the update to the skb happens after the physical
6775 * addresses have been transferred to the new BD location.
6779 src_map->data = NULL;
6782 /* The RX ring scheme is composed of multiple rings which post fresh
6783 * buffers to the chip, and one special ring the chip uses to report
6784 * status back to the host.
6786 * The special ring reports the status of received packets to the
6787 * host. The chip does not write into the original descriptor the
6788 * RX buffer was obtained from. The chip simply takes the original
6789 * descriptor as provided by the host, updates the status and length
6790 * field, then writes this into the next status ring entry.
6792 * Each ring the host uses to post buffers to the chip is described
6793 * by a TG3_BDINFO entry in the chips SRAM area. When a packet arrives,
6794 * it is first placed into the on-chip ram. When the packet's length
6795 * is known, it walks down the TG3_BDINFO entries to select the ring.
6796 * Each TG3_BDINFO specifies a MAXLEN field and the first TG3_BDINFO
6797 * which is within the range of the new packet's length is chosen.
6799 * The "separate ring for rx status" scheme may sound queer, but it makes
6800 * sense from a cache coherency perspective. If only the host writes
6801 * to the buffer post rings, and only the chip writes to the rx status
6802 * rings, then cache lines never move beyond shared-modified state.
6803 * If both the host and chip were to write into the same ring, cache line
6804 * eviction could occur since both entities want it in an exclusive state.
6806 static int tg3_rx(struct tg3_napi *tnapi, int budget)
6808 struct tg3 *tp = tnapi->tp;
6809 u32 work_mask, rx_std_posted = 0;
6810 u32 std_prod_idx, jmb_prod_idx;
6811 u32 sw_idx = tnapi->rx_rcb_ptr;
6814 struct tg3_rx_prodring_set *tpr = &tnapi->prodring;
6816 hw_idx = *(tnapi->rx_rcb_prod_idx);
6818 * We need to order the read of hw_idx and the read of
6819 * the opaque cookie.
6824 std_prod_idx = tpr->rx_std_prod_idx;
6825 jmb_prod_idx = tpr->rx_jmb_prod_idx;
6826 while (sw_idx != hw_idx && budget > 0) {
6827 struct ring_info *ri;
6828 struct tg3_rx_buffer_desc *desc = &tnapi->rx_rcb[sw_idx];
6830 struct sk_buff *skb;
6831 dma_addr_t dma_addr;
6832 u32 opaque_key, desc_idx, *post_ptr;
6836 desc_idx = desc->opaque & RXD_OPAQUE_INDEX_MASK;
6837 opaque_key = desc->opaque & RXD_OPAQUE_RING_MASK;
6838 if (opaque_key == RXD_OPAQUE_RING_STD) {
6839 ri = &tp->napi[0].prodring.rx_std_buffers[desc_idx];
6840 dma_addr = dma_unmap_addr(ri, mapping);
6842 post_ptr = &std_prod_idx;
6844 } else if (opaque_key == RXD_OPAQUE_RING_JUMBO) {
6845 ri = &tp->napi[0].prodring.rx_jmb_buffers[desc_idx];
6846 dma_addr = dma_unmap_addr(ri, mapping);
6848 post_ptr = &jmb_prod_idx;
6850 goto next_pkt_nopost;
6852 work_mask |= opaque_key;
6854 if (desc->err_vlan & RXD_ERR_MASK) {
6856 tg3_recycle_rx(tnapi, tpr, opaque_key,
6857 desc_idx, *post_ptr);
6859 /* Other statistics kept track of by card. */
6864 prefetch(data + TG3_RX_OFFSET(tp));
6865 len = ((desc->idx_len & RXD_LEN_MASK) >> RXD_LEN_SHIFT) -
6868 if ((desc->type_flags & RXD_FLAG_PTPSTAT_MASK) ==
6869 RXD_FLAG_PTPSTAT_PTPV1 ||
6870 (desc->type_flags & RXD_FLAG_PTPSTAT_MASK) ==
6871 RXD_FLAG_PTPSTAT_PTPV2) {
6872 tstamp = tr32(TG3_RX_TSTAMP_LSB);
6873 tstamp |= (u64)tr32(TG3_RX_TSTAMP_MSB) << 32;
6876 if (len > TG3_RX_COPY_THRESH(tp)) {
6878 unsigned int frag_size;
6880 skb_size = tg3_alloc_rx_data(tp, tpr, opaque_key,
6881 *post_ptr, &frag_size);
6885 pci_unmap_single(tp->pdev, dma_addr, skb_size,
6886 PCI_DMA_FROMDEVICE);
6888 /* Ensure that the update to the data happens
6889 * after the usage of the old DMA mapping.
6895 skb = build_skb(data, frag_size);
6897 tg3_frag_free(frag_size != 0, data);
6898 goto drop_it_no_recycle;
6900 skb_reserve(skb, TG3_RX_OFFSET(tp));
6902 tg3_recycle_rx(tnapi, tpr, opaque_key,
6903 desc_idx, *post_ptr);
6905 skb = netdev_alloc_skb(tp->dev,
6906 len + TG3_RAW_IP_ALIGN);
6908 goto drop_it_no_recycle;
6910 skb_reserve(skb, TG3_RAW_IP_ALIGN);
6911 pci_dma_sync_single_for_cpu(tp->pdev, dma_addr, len, PCI_DMA_FROMDEVICE);
6913 data + TG3_RX_OFFSET(tp),
6915 pci_dma_sync_single_for_device(tp->pdev, dma_addr, len, PCI_DMA_FROMDEVICE);
6920 tg3_hwclock_to_timestamp(tp, tstamp,
6921 skb_hwtstamps(skb));
6923 if ((tp->dev->features & NETIF_F_RXCSUM) &&
6924 (desc->type_flags & RXD_FLAG_TCPUDP_CSUM) &&
6925 (((desc->ip_tcp_csum & RXD_TCPCSUM_MASK)
6926 >> RXD_TCPCSUM_SHIFT) == 0xffff))
6927 skb->ip_summed = CHECKSUM_UNNECESSARY;
6929 skb_checksum_none_assert(skb);
6931 skb->protocol = eth_type_trans(skb, tp->dev);
6933 if (len > (tp->dev->mtu + ETH_HLEN) &&
6934 skb->protocol != htons(ETH_P_8021Q) &&
6935 skb->protocol != htons(ETH_P_8021AD)) {
6936 dev_kfree_skb_any(skb);
6937 goto drop_it_no_recycle;
6940 if (desc->type_flags & RXD_FLAG_VLAN &&
6941 !(tp->rx_mode & RX_MODE_KEEP_VLAN_TAG))
6942 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q),
6943 desc->err_vlan & RXD_VLAN_MASK);
6945 napi_gro_receive(&tnapi->napi, skb);
6953 if (unlikely(rx_std_posted >= tp->rx_std_max_post)) {
6954 tpr->rx_std_prod_idx = std_prod_idx &
6955 tp->rx_std_ring_mask;
6956 tw32_rx_mbox(TG3_RX_STD_PROD_IDX_REG,
6957 tpr->rx_std_prod_idx);
6958 work_mask &= ~RXD_OPAQUE_RING_STD;
6963 sw_idx &= tp->rx_ret_ring_mask;
6965 /* Refresh hw_idx to see if there is new work */
6966 if (sw_idx == hw_idx) {
6967 hw_idx = *(tnapi->rx_rcb_prod_idx);
6972 /* ACK the status ring. */
6973 tnapi->rx_rcb_ptr = sw_idx;
6974 tw32_rx_mbox(tnapi->consmbox, sw_idx);
6976 /* Refill RX ring(s). */
6977 if (!tg3_flag(tp, ENABLE_RSS)) {
6978 /* Sync BD data before updating mailbox */
6981 if (work_mask & RXD_OPAQUE_RING_STD) {
6982 tpr->rx_std_prod_idx = std_prod_idx &
6983 tp->rx_std_ring_mask;
6984 tw32_rx_mbox(TG3_RX_STD_PROD_IDX_REG,
6985 tpr->rx_std_prod_idx);
6987 if (work_mask & RXD_OPAQUE_RING_JUMBO) {
6988 tpr->rx_jmb_prod_idx = jmb_prod_idx &
6989 tp->rx_jmb_ring_mask;
6990 tw32_rx_mbox(TG3_RX_JMB_PROD_IDX_REG,
6991 tpr->rx_jmb_prod_idx);
6994 } else if (work_mask) {
6995 /* rx_std_buffers[] and rx_jmb_buffers[] entries must be
6996 * updated before the producer indices can be updated.
7000 tpr->rx_std_prod_idx = std_prod_idx & tp->rx_std_ring_mask;
7001 tpr->rx_jmb_prod_idx = jmb_prod_idx & tp->rx_jmb_ring_mask;
7003 if (tnapi != &tp->napi[1]) {
7004 tp->rx_refill = true;
7005 napi_schedule(&tp->napi[1].napi);
7012 static void tg3_poll_link(struct tg3 *tp)
7014 /* handle link change and other phy events */
7015 if (!(tg3_flag(tp, USE_LINKCHG_REG) || tg3_flag(tp, POLL_SERDES))) {
7016 struct tg3_hw_status *sblk = tp->napi[0].hw_status;
7018 if (sblk->status & SD_STATUS_LINK_CHG) {
7019 sblk->status = SD_STATUS_UPDATED |
7020 (sblk->status & ~SD_STATUS_LINK_CHG);
7021 spin_lock(&tp->lock);
7022 if (tg3_flag(tp, USE_PHYLIB)) {
7024 (MAC_STATUS_SYNC_CHANGED |
7025 MAC_STATUS_CFG_CHANGED |
7026 MAC_STATUS_MI_COMPLETION |
7027 MAC_STATUS_LNKSTATE_CHANGED));
7030 tg3_setup_phy(tp, false);
7031 spin_unlock(&tp->lock);
7036 static int tg3_rx_prodring_xfer(struct tg3 *tp,
7037 struct tg3_rx_prodring_set *dpr,
7038 struct tg3_rx_prodring_set *spr)
7040 u32 si, di, cpycnt, src_prod_idx;
7044 src_prod_idx = spr->rx_std_prod_idx;
7046 /* Make sure updates to the rx_std_buffers[] entries and the
7047 * standard producer index are seen in the correct order.
7051 if (spr->rx_std_cons_idx == src_prod_idx)
7054 if (spr->rx_std_cons_idx < src_prod_idx)
7055 cpycnt = src_prod_idx - spr->rx_std_cons_idx;
7057 cpycnt = tp->rx_std_ring_mask + 1 -
7058 spr->rx_std_cons_idx;
7060 cpycnt = min(cpycnt,
7061 tp->rx_std_ring_mask + 1 - dpr->rx_std_prod_idx);
7063 si = spr->rx_std_cons_idx;
7064 di = dpr->rx_std_prod_idx;
7066 for (i = di; i < di + cpycnt; i++) {
7067 if (dpr->rx_std_buffers[i].data) {
7077 /* Ensure that updates to the rx_std_buffers ring and the
7078 * shadowed hardware producer ring from tg3_recycle_skb() are
7079 * ordered correctly WRT the skb check above.
7083 memcpy(&dpr->rx_std_buffers[di],
7084 &spr->rx_std_buffers[si],
7085 cpycnt * sizeof(struct ring_info));
7087 for (i = 0; i < cpycnt; i++, di++, si++) {
7088 struct tg3_rx_buffer_desc *sbd, *dbd;
7089 sbd = &spr->rx_std[si];
7090 dbd = &dpr->rx_std[di];
7091 dbd->addr_hi = sbd->addr_hi;
7092 dbd->addr_lo = sbd->addr_lo;
7095 spr->rx_std_cons_idx = (spr->rx_std_cons_idx + cpycnt) &
7096 tp->rx_std_ring_mask;
7097 dpr->rx_std_prod_idx = (dpr->rx_std_prod_idx + cpycnt) &
7098 tp->rx_std_ring_mask;
7102 src_prod_idx = spr->rx_jmb_prod_idx;
7104 /* Make sure updates to the rx_jmb_buffers[] entries and
7105 * the jumbo producer index are seen in the correct order.
7109 if (spr->rx_jmb_cons_idx == src_prod_idx)
7112 if (spr->rx_jmb_cons_idx < src_prod_idx)
7113 cpycnt = src_prod_idx - spr->rx_jmb_cons_idx;
7115 cpycnt = tp->rx_jmb_ring_mask + 1 -
7116 spr->rx_jmb_cons_idx;
7118 cpycnt = min(cpycnt,
7119 tp->rx_jmb_ring_mask + 1 - dpr->rx_jmb_prod_idx);
7121 si = spr->rx_jmb_cons_idx;
7122 di = dpr->rx_jmb_prod_idx;
7124 for (i = di; i < di + cpycnt; i++) {
7125 if (dpr->rx_jmb_buffers[i].data) {
7135 /* Ensure that updates to the rx_jmb_buffers ring and the
7136 * shadowed hardware producer ring from tg3_recycle_skb() are
7137 * ordered correctly WRT the skb check above.
7141 memcpy(&dpr->rx_jmb_buffers[di],
7142 &spr->rx_jmb_buffers[si],
7143 cpycnt * sizeof(struct ring_info));
7145 for (i = 0; i < cpycnt; i++, di++, si++) {
7146 struct tg3_rx_buffer_desc *sbd, *dbd;
7147 sbd = &spr->rx_jmb[si].std;
7148 dbd = &dpr->rx_jmb[di].std;
7149 dbd->addr_hi = sbd->addr_hi;
7150 dbd->addr_lo = sbd->addr_lo;
7153 spr->rx_jmb_cons_idx = (spr->rx_jmb_cons_idx + cpycnt) &
7154 tp->rx_jmb_ring_mask;
7155 dpr->rx_jmb_prod_idx = (dpr->rx_jmb_prod_idx + cpycnt) &
7156 tp->rx_jmb_ring_mask;
7162 static int tg3_poll_work(struct tg3_napi *tnapi, int work_done, int budget)
7164 struct tg3 *tp = tnapi->tp;
7166 /* run TX completion thread */
7167 if (tnapi->hw_status->idx[0].tx_consumer != tnapi->tx_cons) {
7169 if (unlikely(tg3_flag(tp, TX_RECOVERY_PENDING)))
7173 if (!tnapi->rx_rcb_prod_idx)
7176 /* run RX thread, within the bounds set by NAPI.
7177 * All RX "locking" is done by ensuring outside
7178 * code synchronizes with tg3->napi.poll()
7180 if (*(tnapi->rx_rcb_prod_idx) != tnapi->rx_rcb_ptr)
7181 work_done += tg3_rx(tnapi, budget - work_done);
7183 if (tg3_flag(tp, ENABLE_RSS) && tnapi == &tp->napi[1]) {
7184 struct tg3_rx_prodring_set *dpr = &tp->napi[0].prodring;
7186 u32 std_prod_idx = dpr->rx_std_prod_idx;
7187 u32 jmb_prod_idx = dpr->rx_jmb_prod_idx;
7189 tp->rx_refill = false;
7190 for (i = 1; i <= tp->rxq_cnt; i++)
7191 err |= tg3_rx_prodring_xfer(tp, dpr,
7192 &tp->napi[i].prodring);
7196 if (std_prod_idx != dpr->rx_std_prod_idx)
7197 tw32_rx_mbox(TG3_RX_STD_PROD_IDX_REG,
7198 dpr->rx_std_prod_idx);
7200 if (jmb_prod_idx != dpr->rx_jmb_prod_idx)
7201 tw32_rx_mbox(TG3_RX_JMB_PROD_IDX_REG,
7202 dpr->rx_jmb_prod_idx);
7207 tw32_f(HOSTCC_MODE, tp->coal_now);
7213 static inline void tg3_reset_task_schedule(struct tg3 *tp)
7215 if (!test_and_set_bit(TG3_FLAG_RESET_TASK_PENDING, tp->tg3_flags))
7216 schedule_work(&tp->reset_task);
7219 static inline void tg3_reset_task_cancel(struct tg3 *tp)
7221 cancel_work_sync(&tp->reset_task);
7222 tg3_flag_clear(tp, RESET_TASK_PENDING);
7223 tg3_flag_clear(tp, TX_RECOVERY_PENDING);
7226 static int tg3_poll_msix(struct napi_struct *napi, int budget)
7228 struct tg3_napi *tnapi = container_of(napi, struct tg3_napi, napi);
7229 struct tg3 *tp = tnapi->tp;
7231 struct tg3_hw_status *sblk = tnapi->hw_status;
7234 work_done = tg3_poll_work(tnapi, work_done, budget);
7236 if (unlikely(tg3_flag(tp, TX_RECOVERY_PENDING)))
7239 if (unlikely(work_done >= budget))
7242 /* tp->last_tag is used in tg3_int_reenable() below
7243 * to tell the hw how much work has been processed,
7244 * so we must read it before checking for more work.
7246 tnapi->last_tag = sblk->status_tag;
7247 tnapi->last_irq_tag = tnapi->last_tag;
7250 /* check for RX/TX work to do */
7251 if (likely(sblk->idx[0].tx_consumer == tnapi->tx_cons &&
7252 *(tnapi->rx_rcb_prod_idx) == tnapi->rx_rcb_ptr)) {
7254 /* This test here is not race free, but will reduce
7255 * the number of interrupts by looping again.
7257 if (tnapi == &tp->napi[1] && tp->rx_refill)
7260 napi_complete_done(napi, work_done);
7261 /* Reenable interrupts. */
7262 tw32_mailbox(tnapi->int_mbox, tnapi->last_tag << 24);
7264 /* This test here is synchronized by napi_schedule()
7265 * and napi_complete() to close the race condition.
7267 if (unlikely(tnapi == &tp->napi[1] && tp->rx_refill)) {
7268 tw32(HOSTCC_MODE, tp->coalesce_mode |
7269 HOSTCC_MODE_ENABLE |
7277 tg3_send_ape_heartbeat(tp, TG3_APE_HB_INTERVAL << 1);
7281 /* work_done is guaranteed to be less than budget. */
7282 napi_complete(napi);
7283 tg3_reset_task_schedule(tp);
7287 static void tg3_process_error(struct tg3 *tp)
7290 bool real_error = false;
7292 if (tg3_flag(tp, ERROR_PROCESSED))
7295 /* Check Flow Attention register */
7296 val = tr32(HOSTCC_FLOW_ATTN);
7297 if (val & ~HOSTCC_FLOW_ATTN_MBUF_LWM) {
7298 netdev_err(tp->dev, "FLOW Attention error. Resetting chip.\n");
7302 if (tr32(MSGINT_STATUS) & ~MSGINT_STATUS_MSI_REQ) {
7303 netdev_err(tp->dev, "MSI Status error. Resetting chip.\n");
7307 if (tr32(RDMAC_STATUS) || tr32(WDMAC_STATUS)) {
7308 netdev_err(tp->dev, "DMA Status error. Resetting chip.\n");
7317 tg3_flag_set(tp, ERROR_PROCESSED);
7318 tg3_reset_task_schedule(tp);
7321 static int tg3_poll(struct napi_struct *napi, int budget)
7323 struct tg3_napi *tnapi = container_of(napi, struct tg3_napi, napi);
7324 struct tg3 *tp = tnapi->tp;
7326 struct tg3_hw_status *sblk = tnapi->hw_status;
7329 if (sblk->status & SD_STATUS_ERROR)
7330 tg3_process_error(tp);
7334 work_done = tg3_poll_work(tnapi, work_done, budget);
7336 if (unlikely(tg3_flag(tp, TX_RECOVERY_PENDING)))
7339 if (unlikely(work_done >= budget))
7342 if (tg3_flag(tp, TAGGED_STATUS)) {
7343 /* tp->last_tag is used in tg3_int_reenable() below
7344 * to tell the hw how much work has been processed,
7345 * so we must read it before checking for more work.
7347 tnapi->last_tag = sblk->status_tag;
7348 tnapi->last_irq_tag = tnapi->last_tag;
7351 sblk->status &= ~SD_STATUS_UPDATED;
7353 if (likely(!tg3_has_work(tnapi))) {
7354 napi_complete_done(napi, work_done);
7355 tg3_int_reenable(tnapi);
7360 tg3_send_ape_heartbeat(tp, TG3_APE_HB_INTERVAL << 1);
7364 /* work_done is guaranteed to be less than budget. */
7365 napi_complete(napi);
7366 tg3_reset_task_schedule(tp);
7370 static void tg3_napi_disable(struct tg3 *tp)
7374 for (i = tp->irq_cnt - 1; i >= 0; i--)
7375 napi_disable(&tp->napi[i].napi);
7378 static void tg3_napi_enable(struct tg3 *tp)
7382 for (i = 0; i < tp->irq_cnt; i++)
7383 napi_enable(&tp->napi[i].napi);
7386 static void tg3_napi_init(struct tg3 *tp)
7390 netif_napi_add(tp->dev, &tp->napi[0].napi, tg3_poll, 64);
7391 for (i = 1; i < tp->irq_cnt; i++)
7392 netif_napi_add(tp->dev, &tp->napi[i].napi, tg3_poll_msix, 64);
7395 static void tg3_napi_fini(struct tg3 *tp)
7399 for (i = 0; i < tp->irq_cnt; i++)
7400 netif_napi_del(&tp->napi[i].napi);
7403 static inline void tg3_netif_stop(struct tg3 *tp)
7405 netif_trans_update(tp->dev); /* prevent tx timeout */
7406 tg3_napi_disable(tp);
7407 netif_carrier_off(tp->dev);
7408 netif_tx_disable(tp->dev);
7411 /* tp->lock must be held */
7412 static inline void tg3_netif_start(struct tg3 *tp)
7416 /* NOTE: unconditional netif_tx_wake_all_queues is only
7417 * appropriate so long as all callers are assured to
7418 * have free tx slots (such as after tg3_init_hw)
7420 netif_tx_wake_all_queues(tp->dev);
7423 netif_carrier_on(tp->dev);
7425 tg3_napi_enable(tp);
7426 tp->napi[0].hw_status->status |= SD_STATUS_UPDATED;
7427 tg3_enable_ints(tp);
7430 static void tg3_irq_quiesce(struct tg3 *tp)
7431 __releases(tp->lock)
7432 __acquires(tp->lock)
7436 BUG_ON(tp->irq_sync);
7441 spin_unlock_bh(&tp->lock);
7443 for (i = 0; i < tp->irq_cnt; i++)
7444 synchronize_irq(tp->napi[i].irq_vec);
7446 spin_lock_bh(&tp->lock);
7449 /* Fully shutdown all tg3 driver activity elsewhere in the system.
7450 * If irq_sync is non-zero, then the IRQ handler must be synchronized
7451 * with as well. Most of the time, this is not necessary except when
7452 * shutting down the device.
7454 static inline void tg3_full_lock(struct tg3 *tp, int irq_sync)
7456 spin_lock_bh(&tp->lock);
7458 tg3_irq_quiesce(tp);
7461 static inline void tg3_full_unlock(struct tg3 *tp)
7463 spin_unlock_bh(&tp->lock);
7466 /* One-shot MSI handler - Chip automatically disables interrupt
7467 * after sending MSI so driver doesn't have to do it.
7469 static irqreturn_t tg3_msi_1shot(int irq, void *dev_id)
7471 struct tg3_napi *tnapi = dev_id;
7472 struct tg3 *tp = tnapi->tp;
7474 prefetch(tnapi->hw_status);
7476 prefetch(&tnapi->rx_rcb[tnapi->rx_rcb_ptr]);
7478 if (likely(!tg3_irq_sync(tp)))
7479 napi_schedule(&tnapi->napi);
7484 /* MSI ISR - No need to check for interrupt sharing and no need to
7485 * flush status block and interrupt mailbox. PCI ordering rules
7486 * guarantee that MSI will arrive after the status block.
7488 static irqreturn_t tg3_msi(int irq, void *dev_id)
7490 struct tg3_napi *tnapi = dev_id;
7491 struct tg3 *tp = tnapi->tp;
7493 prefetch(tnapi->hw_status);
7495 prefetch(&tnapi->rx_rcb[tnapi->rx_rcb_ptr]);
7497 * Writing any value to intr-mbox-0 clears PCI INTA# and
7498 * chip-internal interrupt pending events.
7499 * Writing non-zero to intr-mbox-0 additional tells the
7500 * NIC to stop sending us irqs, engaging "in-intr-handler"
7503 tw32_mailbox(tnapi->int_mbox, 0x00000001);
7504 if (likely(!tg3_irq_sync(tp)))
7505 napi_schedule(&tnapi->napi);
7507 return IRQ_RETVAL(1);
7510 static irqreturn_t tg3_interrupt(int irq, void *dev_id)
7512 struct tg3_napi *tnapi = dev_id;
7513 struct tg3 *tp = tnapi->tp;
7514 struct tg3_hw_status *sblk = tnapi->hw_status;
7515 unsigned int handled = 1;
7517 /* In INTx mode, it is possible for the interrupt to arrive at
7518 * the CPU before the status block posted prior to the interrupt.
7519 * Reading the PCI State register will confirm whether the
7520 * interrupt is ours and will flush the status block.
7522 if (unlikely(!(sblk->status & SD_STATUS_UPDATED))) {
7523 if (tg3_flag(tp, CHIP_RESETTING) ||
7524 (tr32(TG3PCI_PCISTATE) & PCISTATE_INT_NOT_ACTIVE)) {
7531 * Writing any value to intr-mbox-0 clears PCI INTA# and
7532 * chip-internal interrupt pending events.
7533 * Writing non-zero to intr-mbox-0 additional tells the
7534 * NIC to stop sending us irqs, engaging "in-intr-handler"
7537 * Flush the mailbox to de-assert the IRQ immediately to prevent
7538 * spurious interrupts. The flush impacts performance but
7539 * excessive spurious interrupts can be worse in some cases.
7541 tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, 0x00000001);
7542 if (tg3_irq_sync(tp))
7544 sblk->status &= ~SD_STATUS_UPDATED;
7545 if (likely(tg3_has_work(tnapi))) {
7546 prefetch(&tnapi->rx_rcb[tnapi->rx_rcb_ptr]);
7547 napi_schedule(&tnapi->napi);
7549 /* No work, shared interrupt perhaps? re-enable
7550 * interrupts, and flush that PCI write
7552 tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW,
7556 return IRQ_RETVAL(handled);
7559 static irqreturn_t tg3_interrupt_tagged(int irq, void *dev_id)
7561 struct tg3_napi *tnapi = dev_id;
7562 struct tg3 *tp = tnapi->tp;
7563 struct tg3_hw_status *sblk = tnapi->hw_status;
7564 unsigned int handled = 1;
7566 /* In INTx mode, it is possible for the interrupt to arrive at
7567 * the CPU before the status block posted prior to the interrupt.
7568 * Reading the PCI State register will confirm whether the
7569 * interrupt is ours and will flush the status block.
7571 if (unlikely(sblk->status_tag == tnapi->last_irq_tag)) {
7572 if (tg3_flag(tp, CHIP_RESETTING) ||
7573 (tr32(TG3PCI_PCISTATE) & PCISTATE_INT_NOT_ACTIVE)) {
7580 * writing any value to intr-mbox-0 clears PCI INTA# and
7581 * chip-internal interrupt pending events.
7582 * writing non-zero to intr-mbox-0 additional tells the
7583 * NIC to stop sending us irqs, engaging "in-intr-handler"
7586 * Flush the mailbox to de-assert the IRQ immediately to prevent
7587 * spurious interrupts. The flush impacts performance but
7588 * excessive spurious interrupts can be worse in some cases.
7590 tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, 0x00000001);
7593 * In a shared interrupt configuration, sometimes other devices'
7594 * interrupts will scream. We record the current status tag here
7595 * so that the above check can report that the screaming interrupts
7596 * are unhandled. Eventually they will be silenced.
7598 tnapi->last_irq_tag = sblk->status_tag;
7600 if (tg3_irq_sync(tp))
7603 prefetch(&tnapi->rx_rcb[tnapi->rx_rcb_ptr]);
7605 napi_schedule(&tnapi->napi);
7608 return IRQ_RETVAL(handled);
7611 /* ISR for interrupt test */
7612 static irqreturn_t tg3_test_isr(int irq, void *dev_id)
7614 struct tg3_napi *tnapi = dev_id;
7615 struct tg3 *tp = tnapi->tp;
7616 struct tg3_hw_status *sblk = tnapi->hw_status;
7618 if ((sblk->status & SD_STATUS_UPDATED) ||
7619 !(tr32(TG3PCI_PCISTATE) & PCISTATE_INT_NOT_ACTIVE)) {
7620 tg3_disable_ints(tp);
7621 return IRQ_RETVAL(1);
7623 return IRQ_RETVAL(0);
7626 #ifdef CONFIG_NET_POLL_CONTROLLER
7627 static void tg3_poll_controller(struct net_device *dev)
7630 struct tg3 *tp = netdev_priv(dev);
7632 if (tg3_irq_sync(tp))
7635 for (i = 0; i < tp->irq_cnt; i++)
7636 tg3_interrupt(tp->napi[i].irq_vec, &tp->napi[i]);
7640 static void tg3_tx_timeout(struct net_device *dev)
7642 struct tg3 *tp = netdev_priv(dev);
7644 if (netif_msg_tx_err(tp)) {
7645 netdev_err(dev, "transmit timed out, resetting\n");
7649 tg3_reset_task_schedule(tp);
7652 /* Test for DMA buffers crossing any 4GB boundaries: 4G, 8G, etc */
7653 static inline int tg3_4g_overflow_test(dma_addr_t mapping, int len)
7655 u32 base = (u32) mapping & 0xffffffff;
7657 return base + len + 8 < base;
7660 /* Test for TSO DMA buffers that cross into regions which are within MSS bytes
7661 * of any 4GB boundaries: 4G, 8G, etc
7663 static inline int tg3_4g_tso_overflow_test(struct tg3 *tp, dma_addr_t mapping,
7666 if (tg3_asic_rev(tp) == ASIC_REV_5762 && mss) {
7667 u32 base = (u32) mapping & 0xffffffff;
7669 return ((base + len + (mss & 0x3fff)) < base);
7674 /* Test for DMA addresses > 40-bit */
7675 static inline int tg3_40bit_overflow_test(struct tg3 *tp, dma_addr_t mapping,
7678 #if defined(CONFIG_HIGHMEM) && (BITS_PER_LONG == 64)
7679 if (tg3_flag(tp, 40BIT_DMA_BUG))
7680 return ((u64) mapping + len) > DMA_BIT_MASK(40);
7687 static inline void tg3_tx_set_bd(struct tg3_tx_buffer_desc *txbd,
7688 dma_addr_t mapping, u32 len, u32 flags,
7691 txbd->addr_hi = ((u64) mapping >> 32);
7692 txbd->addr_lo = ((u64) mapping & 0xffffffff);
7693 txbd->len_flags = (len << TXD_LEN_SHIFT) | (flags & 0x0000ffff);
7694 txbd->vlan_tag = (mss << TXD_MSS_SHIFT) | (vlan << TXD_VLAN_TAG_SHIFT);
7697 static bool tg3_tx_frag_set(struct tg3_napi *tnapi, u32 *entry, u32 *budget,
7698 dma_addr_t map, u32 len, u32 flags,
7701 struct tg3 *tp = tnapi->tp;
7704 if (tg3_flag(tp, SHORT_DMA_BUG) && len <= 8)
7707 if (tg3_4g_overflow_test(map, len))
7710 if (tg3_4g_tso_overflow_test(tp, map, len, mss))
7713 if (tg3_40bit_overflow_test(tp, map, len))
7716 if (tp->dma_limit) {
7717 u32 prvidx = *entry;
7718 u32 tmp_flag = flags & ~TXD_FLAG_END;
7719 while (len > tp->dma_limit && *budget) {
7720 u32 frag_len = tp->dma_limit;
7721 len -= tp->dma_limit;
7723 /* Avoid the 8byte DMA problem */
7725 len += tp->dma_limit / 2;
7726 frag_len = tp->dma_limit / 2;
7729 tnapi->tx_buffers[*entry].fragmented = true;
7731 tg3_tx_set_bd(&tnapi->tx_ring[*entry], map,
7732 frag_len, tmp_flag, mss, vlan);
7735 *entry = NEXT_TX(*entry);
7742 tg3_tx_set_bd(&tnapi->tx_ring[*entry], map,
7743 len, flags, mss, vlan);
7745 *entry = NEXT_TX(*entry);
7748 tnapi->tx_buffers[prvidx].fragmented = false;
7752 tg3_tx_set_bd(&tnapi->tx_ring[*entry], map,
7753 len, flags, mss, vlan);
7754 *entry = NEXT_TX(*entry);
7760 static void tg3_tx_skb_unmap(struct tg3_napi *tnapi, u32 entry, int last)
7763 struct sk_buff *skb;
7764 struct tg3_tx_ring_info *txb = &tnapi->tx_buffers[entry];
7769 pci_unmap_single(tnapi->tp->pdev,
7770 dma_unmap_addr(txb, mapping),
7774 while (txb->fragmented) {
7775 txb->fragmented = false;
7776 entry = NEXT_TX(entry);
7777 txb = &tnapi->tx_buffers[entry];
7780 for (i = 0; i <= last; i++) {
7781 const skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
7783 entry = NEXT_TX(entry);
7784 txb = &tnapi->tx_buffers[entry];
7786 pci_unmap_page(tnapi->tp->pdev,
7787 dma_unmap_addr(txb, mapping),
7788 skb_frag_size(frag), PCI_DMA_TODEVICE);
7790 while (txb->fragmented) {
7791 txb->fragmented = false;
7792 entry = NEXT_TX(entry);
7793 txb = &tnapi->tx_buffers[entry];
7798 /* Workaround 4GB and 40-bit hardware DMA bugs. */
7799 static int tigon3_dma_hwbug_workaround(struct tg3_napi *tnapi,
7800 struct sk_buff **pskb,
7801 u32 *entry, u32 *budget,
7802 u32 base_flags, u32 mss, u32 vlan)
7804 struct tg3 *tp = tnapi->tp;
7805 struct sk_buff *new_skb, *skb = *pskb;
7806 dma_addr_t new_addr = 0;
7809 if (tg3_asic_rev(tp) != ASIC_REV_5701)
7810 new_skb = skb_copy(skb, GFP_ATOMIC);
7812 int more_headroom = 4 - ((unsigned long)skb->data & 3);
7814 new_skb = skb_copy_expand(skb,
7815 skb_headroom(skb) + more_headroom,
7816 skb_tailroom(skb), GFP_ATOMIC);
7822 /* New SKB is guaranteed to be linear. */
7823 new_addr = pci_map_single(tp->pdev, new_skb->data, new_skb->len,
7825 /* Make sure the mapping succeeded */
7826 if (pci_dma_mapping_error(tp->pdev, new_addr)) {
7827 dev_kfree_skb_any(new_skb);
7830 u32 save_entry = *entry;
7832 base_flags |= TXD_FLAG_END;
7834 tnapi->tx_buffers[*entry].skb = new_skb;
7835 dma_unmap_addr_set(&tnapi->tx_buffers[*entry],
7838 if (tg3_tx_frag_set(tnapi, entry, budget, new_addr,
7839 new_skb->len, base_flags,
7841 tg3_tx_skb_unmap(tnapi, save_entry, -1);
7842 dev_kfree_skb_any(new_skb);
7848 dev_consume_skb_any(skb);
7853 static bool tg3_tso_bug_gso_check(struct tg3_napi *tnapi, struct sk_buff *skb)
7855 /* Check if we will never have enough descriptors,
7856 * as gso_segs can be more than current ring size
7858 return skb_shinfo(skb)->gso_segs < tnapi->tx_pending / 3;
7861 static netdev_tx_t tg3_start_xmit(struct sk_buff *, struct net_device *);
7863 /* Use GSO to workaround all TSO packets that meet HW bug conditions
7864 * indicated in tg3_tx_frag_set()
7866 static int tg3_tso_bug(struct tg3 *tp, struct tg3_napi *tnapi,
7867 struct netdev_queue *txq, struct sk_buff *skb)
7869 struct sk_buff *segs, *nskb;
7870 u32 frag_cnt_est = skb_shinfo(skb)->gso_segs * 3;
7872 /* Estimate the number of fragments in the worst case */
7873 if (unlikely(tg3_tx_avail(tnapi) <= frag_cnt_est)) {
7874 netif_tx_stop_queue(txq);
7876 /* netif_tx_stop_queue() must be done before checking
7877 * checking tx index in tg3_tx_avail() below, because in
7878 * tg3_tx(), we update tx index before checking for
7879 * netif_tx_queue_stopped().
7882 if (tg3_tx_avail(tnapi) <= frag_cnt_est)
7883 return NETDEV_TX_BUSY;
7885 netif_tx_wake_queue(txq);
7888 segs = skb_gso_segment(skb, tp->dev->features &
7889 ~(NETIF_F_TSO | NETIF_F_TSO6));
7890 if (IS_ERR(segs) || !segs)
7891 goto tg3_tso_bug_end;
7897 tg3_start_xmit(nskb, tp->dev);
7901 dev_consume_skb_any(skb);
7903 return NETDEV_TX_OK;
7906 /* hard_start_xmit for all devices */
7907 static netdev_tx_t tg3_start_xmit(struct sk_buff *skb, struct net_device *dev)
7909 struct tg3 *tp = netdev_priv(dev);
7910 u32 len, entry, base_flags, mss, vlan = 0;
7912 int i = -1, would_hit_hwbug;
7914 struct tg3_napi *tnapi;
7915 struct netdev_queue *txq;
7917 struct iphdr *iph = NULL;
7918 struct tcphdr *tcph = NULL;
7919 __sum16 tcp_csum = 0, ip_csum = 0;
7920 __be16 ip_tot_len = 0;
7922 txq = netdev_get_tx_queue(dev, skb_get_queue_mapping(skb));
7923 tnapi = &tp->napi[skb_get_queue_mapping(skb)];
7924 if (tg3_flag(tp, ENABLE_TSS))
7927 budget = tg3_tx_avail(tnapi);
7929 /* We are running in BH disabled context with netif_tx_lock
7930 * and TX reclaim runs via tp->napi.poll inside of a software
7931 * interrupt. Furthermore, IRQ processing runs lockless so we have
7932 * no IRQ context deadlocks to worry about either. Rejoice!
7934 if (unlikely(budget <= (skb_shinfo(skb)->nr_frags + 1))) {
7935 if (!netif_tx_queue_stopped(txq)) {
7936 netif_tx_stop_queue(txq);
7938 /* This is a hard error, log it. */
7940 "BUG! Tx Ring full when queue awake!\n");
7942 return NETDEV_TX_BUSY;
7945 entry = tnapi->tx_prod;
7948 mss = skb_shinfo(skb)->gso_size;
7950 u32 tcp_opt_len, hdr_len;
7952 if (skb_cow_head(skb, 0))
7956 tcp_opt_len = tcp_optlen(skb);
7958 hdr_len = skb_transport_offset(skb) + tcp_hdrlen(skb) - ETH_HLEN;
7960 /* HW/FW can not correctly segment packets that have been
7961 * vlan encapsulated.
7963 if (skb->protocol == htons(ETH_P_8021Q) ||
7964 skb->protocol == htons(ETH_P_8021AD)) {
7965 if (tg3_tso_bug_gso_check(tnapi, skb))
7966 return tg3_tso_bug(tp, tnapi, txq, skb);
7970 if (!skb_is_gso_v6(skb)) {
7971 if (unlikely((ETH_HLEN + hdr_len) > 80) &&
7972 tg3_flag(tp, TSO_BUG)) {
7973 if (tg3_tso_bug_gso_check(tnapi, skb))
7974 return tg3_tso_bug(tp, tnapi, txq, skb);
7977 ip_csum = iph->check;
7978 ip_tot_len = iph->tot_len;
7980 iph->tot_len = htons(mss + hdr_len);
7983 base_flags |= (TXD_FLAG_CPU_PRE_DMA |
7984 TXD_FLAG_CPU_POST_DMA);
7986 tcph = tcp_hdr(skb);
7987 tcp_csum = tcph->check;
7989 if (tg3_flag(tp, HW_TSO_1) ||
7990 tg3_flag(tp, HW_TSO_2) ||
7991 tg3_flag(tp, HW_TSO_3)) {
7993 base_flags &= ~TXD_FLAG_TCPUDP_CSUM;
7995 tcph->check = ~csum_tcpudp_magic(iph->saddr, iph->daddr,
7999 if (tg3_flag(tp, HW_TSO_3)) {
8000 mss |= (hdr_len & 0xc) << 12;
8002 base_flags |= 0x00000010;
8003 base_flags |= (hdr_len & 0x3e0) << 5;
8004 } else if (tg3_flag(tp, HW_TSO_2))
8005 mss |= hdr_len << 9;
8006 else if (tg3_flag(tp, HW_TSO_1) ||
8007 tg3_asic_rev(tp) == ASIC_REV_5705) {
8008 if (tcp_opt_len || iph->ihl > 5) {
8011 tsflags = (iph->ihl - 5) + (tcp_opt_len >> 2);
8012 mss |= (tsflags << 11);
8015 if (tcp_opt_len || iph->ihl > 5) {
8018 tsflags = (iph->ihl - 5) + (tcp_opt_len >> 2);
8019 base_flags |= tsflags << 12;
8022 } else if (skb->ip_summed == CHECKSUM_PARTIAL) {
8023 /* HW/FW can not correctly checksum packets that have been
8024 * vlan encapsulated.
8026 if (skb->protocol == htons(ETH_P_8021Q) ||
8027 skb->protocol == htons(ETH_P_8021AD)) {
8028 if (skb_checksum_help(skb))
8031 base_flags |= TXD_FLAG_TCPUDP_CSUM;
8035 if (tg3_flag(tp, USE_JUMBO_BDFLAG) &&
8036 !mss && skb->len > VLAN_ETH_FRAME_LEN)
8037 base_flags |= TXD_FLAG_JMB_PKT;
8039 if (skb_vlan_tag_present(skb)) {
8040 base_flags |= TXD_FLAG_VLAN;
8041 vlan = skb_vlan_tag_get(skb);
8044 if ((unlikely(skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP)) &&
8045 tg3_flag(tp, TX_TSTAMP_EN)) {
8046 skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS;
8047 base_flags |= TXD_FLAG_HWTSTAMP;
8050 len = skb_headlen(skb);
8052 mapping = pci_map_single(tp->pdev, skb->data, len, PCI_DMA_TODEVICE);
8053 if (pci_dma_mapping_error(tp->pdev, mapping))
8057 tnapi->tx_buffers[entry].skb = skb;
8058 dma_unmap_addr_set(&tnapi->tx_buffers[entry], mapping, mapping);
8060 would_hit_hwbug = 0;
8062 if (tg3_flag(tp, 5701_DMA_BUG))
8063 would_hit_hwbug = 1;
8065 if (tg3_tx_frag_set(tnapi, &entry, &budget, mapping, len, base_flags |
8066 ((skb_shinfo(skb)->nr_frags == 0) ? TXD_FLAG_END : 0),
8068 would_hit_hwbug = 1;
8069 } else if (skb_shinfo(skb)->nr_frags > 0) {
8072 if (!tg3_flag(tp, HW_TSO_1) &&
8073 !tg3_flag(tp, HW_TSO_2) &&
8074 !tg3_flag(tp, HW_TSO_3))
8077 /* Now loop through additional data
8078 * fragments, and queue them.
8080 last = skb_shinfo(skb)->nr_frags - 1;
8081 for (i = 0; i <= last; i++) {
8082 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
8084 len = skb_frag_size(frag);
8085 mapping = skb_frag_dma_map(&tp->pdev->dev, frag, 0,
8086 len, DMA_TO_DEVICE);
8088 tnapi->tx_buffers[entry].skb = NULL;
8089 dma_unmap_addr_set(&tnapi->tx_buffers[entry], mapping,
8091 if (dma_mapping_error(&tp->pdev->dev, mapping))
8095 tg3_tx_frag_set(tnapi, &entry, &budget, mapping,
8097 ((i == last) ? TXD_FLAG_END : 0),
8099 would_hit_hwbug = 1;
8105 if (would_hit_hwbug) {
8106 tg3_tx_skb_unmap(tnapi, tnapi->tx_prod, i);
8108 if (mss && tg3_tso_bug_gso_check(tnapi, skb)) {
8109 /* If it's a TSO packet, do GSO instead of
8110 * allocating and copying to a large linear SKB
8113 iph->check = ip_csum;
8114 iph->tot_len = ip_tot_len;
8116 tcph->check = tcp_csum;
8117 return tg3_tso_bug(tp, tnapi, txq, skb);
8120 /* If the workaround fails due to memory/mapping
8121 * failure, silently drop this packet.
8123 entry = tnapi->tx_prod;
8124 budget = tg3_tx_avail(tnapi);
8125 if (tigon3_dma_hwbug_workaround(tnapi, &skb, &entry, &budget,
8126 base_flags, mss, vlan))
8130 skb_tx_timestamp(skb);
8131 netdev_tx_sent_queue(txq, skb->len);
8133 /* Sync BD data before updating mailbox */
8136 tnapi->tx_prod = entry;
8137 if (unlikely(tg3_tx_avail(tnapi) <= (MAX_SKB_FRAGS + 1))) {
8138 netif_tx_stop_queue(txq);
8140 /* netif_tx_stop_queue() must be done before checking
8141 * checking tx index in tg3_tx_avail() below, because in
8142 * tg3_tx(), we update tx index before checking for
8143 * netif_tx_queue_stopped().
8146 if (tg3_tx_avail(tnapi) > TG3_TX_WAKEUP_THRESH(tnapi))
8147 netif_tx_wake_queue(txq);
8150 if (!skb->xmit_more || netif_xmit_stopped(txq)) {
8151 /* Packets are ready, update Tx producer idx on card. */
8152 tw32_tx_mbox(tnapi->prodmbox, entry);
8156 return NETDEV_TX_OK;
8159 tg3_tx_skb_unmap(tnapi, tnapi->tx_prod, --i);
8160 tnapi->tx_buffers[tnapi->tx_prod].skb = NULL;
8162 dev_kfree_skb_any(skb);
8165 return NETDEV_TX_OK;
8168 static void tg3_mac_loopback(struct tg3 *tp, bool enable)
8171 tp->mac_mode &= ~(MAC_MODE_HALF_DUPLEX |
8172 MAC_MODE_PORT_MODE_MASK);
8174 tp->mac_mode |= MAC_MODE_PORT_INT_LPBACK;
8176 if (!tg3_flag(tp, 5705_PLUS))
8177 tp->mac_mode |= MAC_MODE_LINK_POLARITY;
8179 if (tp->phy_flags & TG3_PHYFLG_10_100_ONLY)
8180 tp->mac_mode |= MAC_MODE_PORT_MODE_MII;
8182 tp->mac_mode |= MAC_MODE_PORT_MODE_GMII;
8184 tp->mac_mode &= ~MAC_MODE_PORT_INT_LPBACK;
8186 if (tg3_flag(tp, 5705_PLUS) ||
8187 (tp->phy_flags & TG3_PHYFLG_PHY_SERDES) ||
8188 tg3_asic_rev(tp) == ASIC_REV_5700)
8189 tp->mac_mode &= ~MAC_MODE_LINK_POLARITY;
8192 tw32(MAC_MODE, tp->mac_mode);
8196 static int tg3_phy_lpbk_set(struct tg3 *tp, u32 speed, bool extlpbk)
8198 u32 val, bmcr, mac_mode, ptest = 0;
8200 tg3_phy_toggle_apd(tp, false);
8201 tg3_phy_toggle_automdix(tp, false);
8203 if (extlpbk && tg3_phy_set_extloopbk(tp))
8206 bmcr = BMCR_FULLDPLX;
8211 bmcr |= BMCR_SPEED100;
8215 if (tp->phy_flags & TG3_PHYFLG_IS_FET) {
8217 bmcr |= BMCR_SPEED100;
8220 bmcr |= BMCR_SPEED1000;
8225 if (!(tp->phy_flags & TG3_PHYFLG_IS_FET)) {
8226 tg3_readphy(tp, MII_CTRL1000, &val);
8227 val |= CTL1000_AS_MASTER |
8228 CTL1000_ENABLE_MASTER;
8229 tg3_writephy(tp, MII_CTRL1000, val);
8231 ptest = MII_TG3_FET_PTEST_TRIM_SEL |
8232 MII_TG3_FET_PTEST_TRIM_2;
8233 tg3_writephy(tp, MII_TG3_FET_PTEST, ptest);
8236 bmcr |= BMCR_LOOPBACK;
8238 tg3_writephy(tp, MII_BMCR, bmcr);
8240 /* The write needs to be flushed for the FETs */
8241 if (tp->phy_flags & TG3_PHYFLG_IS_FET)
8242 tg3_readphy(tp, MII_BMCR, &bmcr);
8246 if ((tp->phy_flags & TG3_PHYFLG_IS_FET) &&
8247 tg3_asic_rev(tp) == ASIC_REV_5785) {
8248 tg3_writephy(tp, MII_TG3_FET_PTEST, ptest |
8249 MII_TG3_FET_PTEST_FRC_TX_LINK |
8250 MII_TG3_FET_PTEST_FRC_TX_LOCK);
8252 /* The write needs to be flushed for the AC131 */
8253 tg3_readphy(tp, MII_TG3_FET_PTEST, &val);
8256 /* Reset to prevent losing 1st rx packet intermittently */
8257 if ((tp->phy_flags & TG3_PHYFLG_MII_SERDES) &&
8258 tg3_flag(tp, 5780_CLASS)) {
8259 tw32_f(MAC_RX_MODE, RX_MODE_RESET);
8261 tw32_f(MAC_RX_MODE, tp->rx_mode);
8264 mac_mode = tp->mac_mode &
8265 ~(MAC_MODE_PORT_MODE_MASK | MAC_MODE_HALF_DUPLEX);
8266 if (speed == SPEED_1000)
8267 mac_mode |= MAC_MODE_PORT_MODE_GMII;
8269 mac_mode |= MAC_MODE_PORT_MODE_MII;
8271 if (tg3_asic_rev(tp) == ASIC_REV_5700) {
8272 u32 masked_phy_id = tp->phy_id & TG3_PHY_ID_MASK;
8274 if (masked_phy_id == TG3_PHY_ID_BCM5401)
8275 mac_mode &= ~MAC_MODE_LINK_POLARITY;
8276 else if (masked_phy_id == TG3_PHY_ID_BCM5411)
8277 mac_mode |= MAC_MODE_LINK_POLARITY;
8279 tg3_writephy(tp, MII_TG3_EXT_CTRL,
8280 MII_TG3_EXT_CTRL_LNK3_LED_MODE);
8283 tw32(MAC_MODE, mac_mode);
8289 static void tg3_set_loopback(struct net_device *dev, netdev_features_t features)
8291 struct tg3 *tp = netdev_priv(dev);
8293 if (features & NETIF_F_LOOPBACK) {
8294 if (tp->mac_mode & MAC_MODE_PORT_INT_LPBACK)
8297 spin_lock_bh(&tp->lock);
8298 tg3_mac_loopback(tp, true);
8299 netif_carrier_on(tp->dev);
8300 spin_unlock_bh(&tp->lock);
8301 netdev_info(dev, "Internal MAC loopback mode enabled.\n");
8303 if (!(tp->mac_mode & MAC_MODE_PORT_INT_LPBACK))
8306 spin_lock_bh(&tp->lock);
8307 tg3_mac_loopback(tp, false);
8308 /* Force link status check */
8309 tg3_setup_phy(tp, true);
8310 spin_unlock_bh(&tp->lock);
8311 netdev_info(dev, "Internal MAC loopback mode disabled.\n");
8315 static netdev_features_t tg3_fix_features(struct net_device *dev,
8316 netdev_features_t features)
8318 struct tg3 *tp = netdev_priv(dev);
8320 if (dev->mtu > ETH_DATA_LEN && tg3_flag(tp, 5780_CLASS))
8321 features &= ~NETIF_F_ALL_TSO;
8326 static int tg3_set_features(struct net_device *dev, netdev_features_t features)
8328 netdev_features_t changed = dev->features ^ features;
8330 if ((changed & NETIF_F_LOOPBACK) && netif_running(dev))
8331 tg3_set_loopback(dev, features);
8336 static void tg3_rx_prodring_free(struct tg3 *tp,
8337 struct tg3_rx_prodring_set *tpr)
8341 if (tpr != &tp->napi[0].prodring) {
8342 for (i = tpr->rx_std_cons_idx; i != tpr->rx_std_prod_idx;
8343 i = (i + 1) & tp->rx_std_ring_mask)
8344 tg3_rx_data_free(tp, &tpr->rx_std_buffers[i],
8347 if (tg3_flag(tp, JUMBO_CAPABLE)) {
8348 for (i = tpr->rx_jmb_cons_idx;
8349 i != tpr->rx_jmb_prod_idx;
8350 i = (i + 1) & tp->rx_jmb_ring_mask) {
8351 tg3_rx_data_free(tp, &tpr->rx_jmb_buffers[i],
8359 for (i = 0; i <= tp->rx_std_ring_mask; i++)
8360 tg3_rx_data_free(tp, &tpr->rx_std_buffers[i],
8363 if (tg3_flag(tp, JUMBO_CAPABLE) && !tg3_flag(tp, 5780_CLASS)) {
8364 for (i = 0; i <= tp->rx_jmb_ring_mask; i++)
8365 tg3_rx_data_free(tp, &tpr->rx_jmb_buffers[i],
8370 /* Initialize rx rings for packet processing.
8372 * The chip has been shut down and the driver detached from
8373 * the networking, so no interrupts or new tx packets will
8374 * end up in the driver. tp->{tx,}lock are held and thus
8377 static int tg3_rx_prodring_alloc(struct tg3 *tp,
8378 struct tg3_rx_prodring_set *tpr)
8380 u32 i, rx_pkt_dma_sz;
8382 tpr->rx_std_cons_idx = 0;
8383 tpr->rx_std_prod_idx = 0;
8384 tpr->rx_jmb_cons_idx = 0;
8385 tpr->rx_jmb_prod_idx = 0;
8387 if (tpr != &tp->napi[0].prodring) {
8388 memset(&tpr->rx_std_buffers[0], 0,
8389 TG3_RX_STD_BUFF_RING_SIZE(tp));
8390 if (tpr->rx_jmb_buffers)
8391 memset(&tpr->rx_jmb_buffers[0], 0,
8392 TG3_RX_JMB_BUFF_RING_SIZE(tp));
8396 /* Zero out all descriptors. */
8397 memset(tpr->rx_std, 0, TG3_RX_STD_RING_BYTES(tp));
8399 rx_pkt_dma_sz = TG3_RX_STD_DMA_SZ;
8400 if (tg3_flag(tp, 5780_CLASS) &&
8401 tp->dev->mtu > ETH_DATA_LEN)
8402 rx_pkt_dma_sz = TG3_RX_JMB_DMA_SZ;
8403 tp->rx_pkt_map_sz = TG3_RX_DMA_TO_MAP_SZ(rx_pkt_dma_sz);
8405 /* Initialize invariants of the rings, we only set this
8406 * stuff once. This works because the card does not
8407 * write into the rx buffer posting rings.
8409 for (i = 0; i <= tp->rx_std_ring_mask; i++) {
8410 struct tg3_rx_buffer_desc *rxd;
8412 rxd = &tpr->rx_std[i];
8413 rxd->idx_len = rx_pkt_dma_sz << RXD_LEN_SHIFT;
8414 rxd->type_flags = (RXD_FLAG_END << RXD_FLAGS_SHIFT);
8415 rxd->opaque = (RXD_OPAQUE_RING_STD |
8416 (i << RXD_OPAQUE_INDEX_SHIFT));
8419 /* Now allocate fresh SKBs for each rx ring. */
8420 for (i = 0; i < tp->rx_pending; i++) {
8421 unsigned int frag_size;
8423 if (tg3_alloc_rx_data(tp, tpr, RXD_OPAQUE_RING_STD, i,
8425 netdev_warn(tp->dev,
8426 "Using a smaller RX standard ring. Only "
8427 "%d out of %d buffers were allocated "
8428 "successfully\n", i, tp->rx_pending);
8436 if (!tg3_flag(tp, JUMBO_CAPABLE) || tg3_flag(tp, 5780_CLASS))
8439 memset(tpr->rx_jmb, 0, TG3_RX_JMB_RING_BYTES(tp));
8441 if (!tg3_flag(tp, JUMBO_RING_ENABLE))
8444 for (i = 0; i <= tp->rx_jmb_ring_mask; i++) {
8445 struct tg3_rx_buffer_desc *rxd;
8447 rxd = &tpr->rx_jmb[i].std;
8448 rxd->idx_len = TG3_RX_JMB_DMA_SZ << RXD_LEN_SHIFT;
8449 rxd->type_flags = (RXD_FLAG_END << RXD_FLAGS_SHIFT) |
8451 rxd->opaque = (RXD_OPAQUE_RING_JUMBO |
8452 (i << RXD_OPAQUE_INDEX_SHIFT));
8455 for (i = 0; i < tp->rx_jumbo_pending; i++) {
8456 unsigned int frag_size;
8458 if (tg3_alloc_rx_data(tp, tpr, RXD_OPAQUE_RING_JUMBO, i,
8460 netdev_warn(tp->dev,
8461 "Using a smaller RX jumbo ring. Only %d "
8462 "out of %d buffers were allocated "
8463 "successfully\n", i, tp->rx_jumbo_pending);
8466 tp->rx_jumbo_pending = i;
8475 tg3_rx_prodring_free(tp, tpr);
8479 static void tg3_rx_prodring_fini(struct tg3 *tp,
8480 struct tg3_rx_prodring_set *tpr)
8482 kfree(tpr->rx_std_buffers);
8483 tpr->rx_std_buffers = NULL;
8484 kfree(tpr->rx_jmb_buffers);
8485 tpr->rx_jmb_buffers = NULL;
8487 dma_free_coherent(&tp->pdev->dev, TG3_RX_STD_RING_BYTES(tp),
8488 tpr->rx_std, tpr->rx_std_mapping);
8492 dma_free_coherent(&tp->pdev->dev, TG3_RX_JMB_RING_BYTES(tp),
8493 tpr->rx_jmb, tpr->rx_jmb_mapping);
8498 static int tg3_rx_prodring_init(struct tg3 *tp,
8499 struct tg3_rx_prodring_set *tpr)
8501 tpr->rx_std_buffers = kzalloc(TG3_RX_STD_BUFF_RING_SIZE(tp),
8503 if (!tpr->rx_std_buffers)
8506 tpr->rx_std = dma_alloc_coherent(&tp->pdev->dev,
8507 TG3_RX_STD_RING_BYTES(tp),
8508 &tpr->rx_std_mapping,
8513 if (tg3_flag(tp, JUMBO_CAPABLE) && !tg3_flag(tp, 5780_CLASS)) {
8514 tpr->rx_jmb_buffers = kzalloc(TG3_RX_JMB_BUFF_RING_SIZE(tp),
8516 if (!tpr->rx_jmb_buffers)
8519 tpr->rx_jmb = dma_alloc_coherent(&tp->pdev->dev,
8520 TG3_RX_JMB_RING_BYTES(tp),
8521 &tpr->rx_jmb_mapping,
8530 tg3_rx_prodring_fini(tp, tpr);
8534 /* Free up pending packets in all rx/tx rings.
8536 * The chip has been shut down and the driver detached from
8537 * the networking, so no interrupts or new tx packets will
8538 * end up in the driver. tp->{tx,}lock is not held and we are not
8539 * in an interrupt context and thus may sleep.
8541 static void tg3_free_rings(struct tg3 *tp)
8545 for (j = 0; j < tp->irq_cnt; j++) {
8546 struct tg3_napi *tnapi = &tp->napi[j];
8548 tg3_rx_prodring_free(tp, &tnapi->prodring);
8550 if (!tnapi->tx_buffers)
8553 for (i = 0; i < TG3_TX_RING_SIZE; i++) {
8554 struct sk_buff *skb = tnapi->tx_buffers[i].skb;
8559 tg3_tx_skb_unmap(tnapi, i,
8560 skb_shinfo(skb)->nr_frags - 1);
8562 dev_consume_skb_any(skb);
8564 netdev_tx_reset_queue(netdev_get_tx_queue(tp->dev, j));
8568 /* Initialize tx/rx rings for packet processing.
8570 * The chip has been shut down and the driver detached from
8571 * the networking, so no interrupts or new tx packets will
8572 * end up in the driver. tp->{tx,}lock are held and thus
8575 static int tg3_init_rings(struct tg3 *tp)
8579 /* Free up all the SKBs. */
8582 for (i = 0; i < tp->irq_cnt; i++) {
8583 struct tg3_napi *tnapi = &tp->napi[i];
8585 tnapi->last_tag = 0;
8586 tnapi->last_irq_tag = 0;
8587 tnapi->hw_status->status = 0;
8588 tnapi->hw_status->status_tag = 0;
8589 memset(tnapi->hw_status, 0, TG3_HW_STATUS_SIZE);
8594 memset(tnapi->tx_ring, 0, TG3_TX_RING_BYTES);
8596 tnapi->rx_rcb_ptr = 0;
8598 memset(tnapi->rx_rcb, 0, TG3_RX_RCB_RING_BYTES(tp));
8600 if (tnapi->prodring.rx_std &&
8601 tg3_rx_prodring_alloc(tp, &tnapi->prodring)) {
8610 static void tg3_mem_tx_release(struct tg3 *tp)
8614 for (i = 0; i < tp->irq_max; i++) {
8615 struct tg3_napi *tnapi = &tp->napi[i];
8617 if (tnapi->tx_ring) {
8618 dma_free_coherent(&tp->pdev->dev, TG3_TX_RING_BYTES,
8619 tnapi->tx_ring, tnapi->tx_desc_mapping);
8620 tnapi->tx_ring = NULL;
8623 kfree(tnapi->tx_buffers);
8624 tnapi->tx_buffers = NULL;
8628 static int tg3_mem_tx_acquire(struct tg3 *tp)
8631 struct tg3_napi *tnapi = &tp->napi[0];
8633 /* If multivector TSS is enabled, vector 0 does not handle
8634 * tx interrupts. Don't allocate any resources for it.
8636 if (tg3_flag(tp, ENABLE_TSS))
8639 for (i = 0; i < tp->txq_cnt; i++, tnapi++) {
8640 tnapi->tx_buffers = kcalloc(TG3_TX_RING_SIZE,
8641 sizeof(struct tg3_tx_ring_info),
8643 if (!tnapi->tx_buffers)
8646 tnapi->tx_ring = dma_alloc_coherent(&tp->pdev->dev,
8648 &tnapi->tx_desc_mapping,
8650 if (!tnapi->tx_ring)
8657 tg3_mem_tx_release(tp);
8661 static void tg3_mem_rx_release(struct tg3 *tp)
8665 for (i = 0; i < tp->irq_max; i++) {
8666 struct tg3_napi *tnapi = &tp->napi[i];
8668 tg3_rx_prodring_fini(tp, &tnapi->prodring);
8673 dma_free_coherent(&tp->pdev->dev,
8674 TG3_RX_RCB_RING_BYTES(tp),
8676 tnapi->rx_rcb_mapping);
8677 tnapi->rx_rcb = NULL;
8681 static int tg3_mem_rx_acquire(struct tg3 *tp)
8683 unsigned int i, limit;
8685 limit = tp->rxq_cnt;
8687 /* If RSS is enabled, we need a (dummy) producer ring
8688 * set on vector zero. This is the true hw prodring.
8690 if (tg3_flag(tp, ENABLE_RSS))
8693 for (i = 0; i < limit; i++) {
8694 struct tg3_napi *tnapi = &tp->napi[i];
8696 if (tg3_rx_prodring_init(tp, &tnapi->prodring))
8699 /* If multivector RSS is enabled, vector 0
8700 * does not handle rx or tx interrupts.
8701 * Don't allocate any resources for it.
8703 if (!i && tg3_flag(tp, ENABLE_RSS))
8706 tnapi->rx_rcb = dma_zalloc_coherent(&tp->pdev->dev,
8707 TG3_RX_RCB_RING_BYTES(tp),
8708 &tnapi->rx_rcb_mapping,
8717 tg3_mem_rx_release(tp);
8722 * Must not be invoked with interrupt sources disabled and
8723 * the hardware shutdown down.
8725 static void tg3_free_consistent(struct tg3 *tp)
8729 for (i = 0; i < tp->irq_cnt; i++) {
8730 struct tg3_napi *tnapi = &tp->napi[i];
8732 if (tnapi->hw_status) {
8733 dma_free_coherent(&tp->pdev->dev, TG3_HW_STATUS_SIZE,
8735 tnapi->status_mapping);
8736 tnapi->hw_status = NULL;
8740 tg3_mem_rx_release(tp);
8741 tg3_mem_tx_release(tp);
8743 /* tp->hw_stats can be referenced safely:
8744 * 1. under rtnl_lock
8745 * 2. or under tp->lock if TG3_FLAG_INIT_COMPLETE is set.
8748 dma_free_coherent(&tp->pdev->dev, sizeof(struct tg3_hw_stats),
8749 tp->hw_stats, tp->stats_mapping);
8750 tp->hw_stats = NULL;
8755 * Must not be invoked with interrupt sources disabled and
8756 * the hardware shutdown down. Can sleep.
8758 static int tg3_alloc_consistent(struct tg3 *tp)
8762 tp->hw_stats = dma_zalloc_coherent(&tp->pdev->dev,
8763 sizeof(struct tg3_hw_stats),
8764 &tp->stats_mapping, GFP_KERNEL);
8768 for (i = 0; i < tp->irq_cnt; i++) {
8769 struct tg3_napi *tnapi = &tp->napi[i];
8770 struct tg3_hw_status *sblk;
8772 tnapi->hw_status = dma_zalloc_coherent(&tp->pdev->dev,
8774 &tnapi->status_mapping,
8776 if (!tnapi->hw_status)
8779 sblk = tnapi->hw_status;
8781 if (tg3_flag(tp, ENABLE_RSS)) {
8782 u16 *prodptr = NULL;
8785 * When RSS is enabled, the status block format changes
8786 * slightly. The "rx_jumbo_consumer", "reserved",
8787 * and "rx_mini_consumer" members get mapped to the
8788 * other three rx return ring producer indexes.
8792 prodptr = &sblk->idx[0].rx_producer;
8795 prodptr = &sblk->rx_jumbo_consumer;
8798 prodptr = &sblk->reserved;
8801 prodptr = &sblk->rx_mini_consumer;
8804 tnapi->rx_rcb_prod_idx = prodptr;
8806 tnapi->rx_rcb_prod_idx = &sblk->idx[0].rx_producer;
8810 if (tg3_mem_tx_acquire(tp) || tg3_mem_rx_acquire(tp))
8816 tg3_free_consistent(tp);
8820 #define MAX_WAIT_CNT 1000
8822 /* To stop a block, clear the enable bit and poll till it
8823 * clears. tp->lock is held.
8825 static int tg3_stop_block(struct tg3 *tp, unsigned long ofs, u32 enable_bit, bool silent)
8830 if (tg3_flag(tp, 5705_PLUS)) {
8837 /* We can't enable/disable these bits of the
8838 * 5705/5750, just say success.
8851 for (i = 0; i < MAX_WAIT_CNT; i++) {
8852 if (pci_channel_offline(tp->pdev)) {
8853 dev_err(&tp->pdev->dev,
8854 "tg3_stop_block device offline, "
8855 "ofs=%lx enable_bit=%x\n",
8862 if ((val & enable_bit) == 0)
8866 if (i == MAX_WAIT_CNT && !silent) {
8867 dev_err(&tp->pdev->dev,
8868 "tg3_stop_block timed out, ofs=%lx enable_bit=%x\n",
8876 /* tp->lock is held. */
8877 static int tg3_abort_hw(struct tg3 *tp, bool silent)
8881 tg3_disable_ints(tp);
8883 if (pci_channel_offline(tp->pdev)) {
8884 tp->rx_mode &= ~(RX_MODE_ENABLE | TX_MODE_ENABLE);
8885 tp->mac_mode &= ~MAC_MODE_TDE_ENABLE;
8890 tp->rx_mode &= ~RX_MODE_ENABLE;
8891 tw32_f(MAC_RX_MODE, tp->rx_mode);
8894 err = tg3_stop_block(tp, RCVBDI_MODE, RCVBDI_MODE_ENABLE, silent);
8895 err |= tg3_stop_block(tp, RCVLPC_MODE, RCVLPC_MODE_ENABLE, silent);
8896 err |= tg3_stop_block(tp, RCVLSC_MODE, RCVLSC_MODE_ENABLE, silent);
8897 err |= tg3_stop_block(tp, RCVDBDI_MODE, RCVDBDI_MODE_ENABLE, silent);
8898 err |= tg3_stop_block(tp, RCVDCC_MODE, RCVDCC_MODE_ENABLE, silent);
8899 err |= tg3_stop_block(tp, RCVCC_MODE, RCVCC_MODE_ENABLE, silent);
8901 err |= tg3_stop_block(tp, SNDBDS_MODE, SNDBDS_MODE_ENABLE, silent);
8902 err |= tg3_stop_block(tp, SNDBDI_MODE, SNDBDI_MODE_ENABLE, silent);
8903 err |= tg3_stop_block(tp, SNDDATAI_MODE, SNDDATAI_MODE_ENABLE, silent);
8904 err |= tg3_stop_block(tp, RDMAC_MODE, RDMAC_MODE_ENABLE, silent);
8905 err |= tg3_stop_block(tp, SNDDATAC_MODE, SNDDATAC_MODE_ENABLE, silent);
8906 err |= tg3_stop_block(tp, DMAC_MODE, DMAC_MODE_ENABLE, silent);
8907 err |= tg3_stop_block(tp, SNDBDC_MODE, SNDBDC_MODE_ENABLE, silent);
8909 tp->mac_mode &= ~MAC_MODE_TDE_ENABLE;
8910 tw32_f(MAC_MODE, tp->mac_mode);
8913 tp->tx_mode &= ~TX_MODE_ENABLE;
8914 tw32_f(MAC_TX_MODE, tp->tx_mode);
8916 for (i = 0; i < MAX_WAIT_CNT; i++) {
8918 if (!(tr32(MAC_TX_MODE) & TX_MODE_ENABLE))
8921 if (i >= MAX_WAIT_CNT) {
8922 dev_err(&tp->pdev->dev,
8923 "%s timed out, TX_MODE_ENABLE will not clear "
8924 "MAC_TX_MODE=%08x\n", __func__, tr32(MAC_TX_MODE));
8928 err |= tg3_stop_block(tp, HOSTCC_MODE, HOSTCC_MODE_ENABLE, silent);
8929 err |= tg3_stop_block(tp, WDMAC_MODE, WDMAC_MODE_ENABLE, silent);
8930 err |= tg3_stop_block(tp, MBFREE_MODE, MBFREE_MODE_ENABLE, silent);
8932 tw32(FTQ_RESET, 0xffffffff);
8933 tw32(FTQ_RESET, 0x00000000);
8935 err |= tg3_stop_block(tp, BUFMGR_MODE, BUFMGR_MODE_ENABLE, silent);
8936 err |= tg3_stop_block(tp, MEMARB_MODE, MEMARB_MODE_ENABLE, silent);
8939 for (i = 0; i < tp->irq_cnt; i++) {
8940 struct tg3_napi *tnapi = &tp->napi[i];
8941 if (tnapi->hw_status)
8942 memset(tnapi->hw_status, 0, TG3_HW_STATUS_SIZE);
8948 /* Save PCI command register before chip reset */
8949 static void tg3_save_pci_state(struct tg3 *tp)
8951 pci_read_config_word(tp->pdev, PCI_COMMAND, &tp->pci_cmd);
8954 /* Restore PCI state after chip reset */
8955 static void tg3_restore_pci_state(struct tg3 *tp)
8959 /* Re-enable indirect register accesses. */
8960 pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
8961 tp->misc_host_ctrl);
8963 /* Set MAX PCI retry to zero. */
8964 val = (PCISTATE_ROM_ENABLE | PCISTATE_ROM_RETRY_ENABLE);
8965 if (tg3_chip_rev_id(tp) == CHIPREV_ID_5704_A0 &&
8966 tg3_flag(tp, PCIX_MODE))
8967 val |= PCISTATE_RETRY_SAME_DMA;
8968 /* Allow reads and writes to the APE register and memory space. */
8969 if (tg3_flag(tp, ENABLE_APE))
8970 val |= PCISTATE_ALLOW_APE_CTLSPC_WR |
8971 PCISTATE_ALLOW_APE_SHMEM_WR |
8972 PCISTATE_ALLOW_APE_PSPACE_WR;
8973 pci_write_config_dword(tp->pdev, TG3PCI_PCISTATE, val);
8975 pci_write_config_word(tp->pdev, PCI_COMMAND, tp->pci_cmd);
8977 if (!tg3_flag(tp, PCI_EXPRESS)) {
8978 pci_write_config_byte(tp->pdev, PCI_CACHE_LINE_SIZE,
8979 tp->pci_cacheline_sz);
8980 pci_write_config_byte(tp->pdev, PCI_LATENCY_TIMER,
8984 /* Make sure PCI-X relaxed ordering bit is clear. */
8985 if (tg3_flag(tp, PCIX_MODE)) {
8988 pci_read_config_word(tp->pdev, tp->pcix_cap + PCI_X_CMD,
8990 pcix_cmd &= ~PCI_X_CMD_ERO;
8991 pci_write_config_word(tp->pdev, tp->pcix_cap + PCI_X_CMD,
8995 if (tg3_flag(tp, 5780_CLASS)) {
8997 /* Chip reset on 5780 will reset MSI enable bit,
8998 * so need to restore it.
9000 if (tg3_flag(tp, USING_MSI)) {
9003 pci_read_config_word(tp->pdev,
9004 tp->msi_cap + PCI_MSI_FLAGS,
9006 pci_write_config_word(tp->pdev,
9007 tp->msi_cap + PCI_MSI_FLAGS,
9008 ctrl | PCI_MSI_FLAGS_ENABLE);
9009 val = tr32(MSGINT_MODE);
9010 tw32(MSGINT_MODE, val | MSGINT_MODE_ENABLE);
9015 static void tg3_override_clk(struct tg3 *tp)
9019 switch (tg3_asic_rev(tp)) {
9021 val = tr32(TG3_CPMU_CLCK_ORIDE_ENABLE);
9022 tw32(TG3_CPMU_CLCK_ORIDE_ENABLE, val |
9023 TG3_CPMU_MAC_ORIDE_ENABLE);
9028 tw32(TG3_CPMU_CLCK_ORIDE, CPMU_CLCK_ORIDE_MAC_ORIDE_EN);
9036 static void tg3_restore_clk(struct tg3 *tp)
9040 switch (tg3_asic_rev(tp)) {
9042 val = tr32(TG3_CPMU_CLCK_ORIDE_ENABLE);
9043 tw32(TG3_CPMU_CLCK_ORIDE_ENABLE,
9044 val & ~TG3_CPMU_MAC_ORIDE_ENABLE);
9049 val = tr32(TG3_CPMU_CLCK_ORIDE);
9050 tw32(TG3_CPMU_CLCK_ORIDE, val & ~CPMU_CLCK_ORIDE_MAC_ORIDE_EN);
9058 /* tp->lock is held. */
9059 static int tg3_chip_reset(struct tg3 *tp)
9060 __releases(tp->lock)
9061 __acquires(tp->lock)
9064 void (*write_op)(struct tg3 *, u32, u32);
9067 if (!pci_device_is_present(tp->pdev))
9072 tg3_ape_lock(tp, TG3_APE_LOCK_GRC);
9074 /* No matching tg3_nvram_unlock() after this because
9075 * chip reset below will undo the nvram lock.
9077 tp->nvram_lock_cnt = 0;
9079 /* GRC_MISC_CFG core clock reset will clear the memory
9080 * enable bit in PCI register 4 and the MSI enable bit
9081 * on some chips, so we save relevant registers here.
9083 tg3_save_pci_state(tp);
9085 if (tg3_asic_rev(tp) == ASIC_REV_5752 ||
9086 tg3_flag(tp, 5755_PLUS))
9087 tw32(GRC_FASTBOOT_PC, 0);
9090 * We must avoid the readl() that normally takes place.
9091 * It locks machines, causes machine checks, and other
9092 * fun things. So, temporarily disable the 5701
9093 * hardware workaround, while we do the reset.
9095 write_op = tp->write32;
9096 if (write_op == tg3_write_flush_reg32)
9097 tp->write32 = tg3_write32;
9099 /* Prevent the irq handler from reading or writing PCI registers
9100 * during chip reset when the memory enable bit in the PCI command
9101 * register may be cleared. The chip does not generate interrupt
9102 * at this time, but the irq handler may still be called due to irq
9103 * sharing or irqpoll.
9105 tg3_flag_set(tp, CHIP_RESETTING);
9106 for (i = 0; i < tp->irq_cnt; i++) {
9107 struct tg3_napi *tnapi = &tp->napi[i];
9108 if (tnapi->hw_status) {
9109 tnapi->hw_status->status = 0;
9110 tnapi->hw_status->status_tag = 0;
9112 tnapi->last_tag = 0;
9113 tnapi->last_irq_tag = 0;
9117 tg3_full_unlock(tp);
9119 for (i = 0; i < tp->irq_cnt; i++)
9120 synchronize_irq(tp->napi[i].irq_vec);
9122 tg3_full_lock(tp, 0);
9124 if (tg3_asic_rev(tp) == ASIC_REV_57780) {
9125 val = tr32(TG3_PCIE_LNKCTL) & ~TG3_PCIE_LNKCTL_L1_PLL_PD_EN;
9126 tw32(TG3_PCIE_LNKCTL, val | TG3_PCIE_LNKCTL_L1_PLL_PD_DIS);
9130 val = GRC_MISC_CFG_CORECLK_RESET;
9132 if (tg3_flag(tp, PCI_EXPRESS)) {
9133 /* Force PCIe 1.0a mode */
9134 if (tg3_asic_rev(tp) != ASIC_REV_5785 &&
9135 !tg3_flag(tp, 57765_PLUS) &&
9136 tr32(TG3_PCIE_PHY_TSTCTL) ==
9137 (TG3_PCIE_PHY_TSTCTL_PCIE10 | TG3_PCIE_PHY_TSTCTL_PSCRAM))
9138 tw32(TG3_PCIE_PHY_TSTCTL, TG3_PCIE_PHY_TSTCTL_PSCRAM);
9140 if (tg3_chip_rev_id(tp) != CHIPREV_ID_5750_A0) {
9141 tw32(GRC_MISC_CFG, (1 << 29));
9146 if (tg3_asic_rev(tp) == ASIC_REV_5906) {
9147 tw32(VCPU_STATUS, tr32(VCPU_STATUS) | VCPU_STATUS_DRV_RESET);
9148 tw32(GRC_VCPU_EXT_CTRL,
9149 tr32(GRC_VCPU_EXT_CTRL) & ~GRC_VCPU_EXT_CTRL_HALT_CPU);
9152 /* Set the clock to the highest frequency to avoid timeouts. With link
9153 * aware mode, the clock speed could be slow and bootcode does not
9154 * complete within the expected time. Override the clock to allow the
9155 * bootcode to finish sooner and then restore it.
9157 tg3_override_clk(tp);
9159 /* Manage gphy power for all CPMU absent PCIe devices. */
9160 if (tg3_flag(tp, 5705_PLUS) && !tg3_flag(tp, CPMU_PRESENT))
9161 val |= GRC_MISC_CFG_KEEP_GPHY_POWER;
9163 tw32(GRC_MISC_CFG, val);
9165 /* restore 5701 hardware bug workaround write method */
9166 tp->write32 = write_op;
9168 /* Unfortunately, we have to delay before the PCI read back.
9169 * Some 575X chips even will not respond to a PCI cfg access
9170 * when the reset command is given to the chip.
9172 * How do these hardware designers expect things to work
9173 * properly if the PCI write is posted for a long period
9174 * of time? It is always necessary to have some method by
9175 * which a register read back can occur to push the write
9176 * out which does the reset.
9178 * For most tg3 variants the trick below was working.
9183 /* Flush PCI posted writes. The normal MMIO registers
9184 * are inaccessible at this time so this is the only
9185 * way to make this reliably (actually, this is no longer
9186 * the case, see above). I tried to use indirect
9187 * register read/write but this upset some 5701 variants.
9189 pci_read_config_dword(tp->pdev, PCI_COMMAND, &val);
9193 if (tg3_flag(tp, PCI_EXPRESS) && pci_is_pcie(tp->pdev)) {
9196 if (tg3_chip_rev_id(tp) == CHIPREV_ID_5750_A0) {
9200 /* Wait for link training to complete. */
9201 for (j = 0; j < 5000; j++)
9204 pci_read_config_dword(tp->pdev, 0xc4, &cfg_val);
9205 pci_write_config_dword(tp->pdev, 0xc4,
9206 cfg_val | (1 << 15));
9209 /* Clear the "no snoop" and "relaxed ordering" bits. */
9210 val16 = PCI_EXP_DEVCTL_RELAX_EN | PCI_EXP_DEVCTL_NOSNOOP_EN;
9212 * Older PCIe devices only support the 128 byte
9213 * MPS setting. Enforce the restriction.
9215 if (!tg3_flag(tp, CPMU_PRESENT))
9216 val16 |= PCI_EXP_DEVCTL_PAYLOAD;
9217 pcie_capability_clear_word(tp->pdev, PCI_EXP_DEVCTL, val16);
9219 /* Clear error status */
9220 pcie_capability_write_word(tp->pdev, PCI_EXP_DEVSTA,
9221 PCI_EXP_DEVSTA_CED |
9222 PCI_EXP_DEVSTA_NFED |
9223 PCI_EXP_DEVSTA_FED |
9224 PCI_EXP_DEVSTA_URD);
9227 tg3_restore_pci_state(tp);
9229 tg3_flag_clear(tp, CHIP_RESETTING);
9230 tg3_flag_clear(tp, ERROR_PROCESSED);
9233 if (tg3_flag(tp, 5780_CLASS))
9234 val = tr32(MEMARB_MODE);
9235 tw32(MEMARB_MODE, val | MEMARB_MODE_ENABLE);
9237 if (tg3_chip_rev_id(tp) == CHIPREV_ID_5750_A3) {
9239 tw32(0x5000, 0x400);
9242 if (tg3_flag(tp, IS_SSB_CORE)) {
9244 * BCM4785: In order to avoid repercussions from using
9245 * potentially defective internal ROM, stop the Rx RISC CPU,
9246 * which is not required.
9249 tg3_halt_cpu(tp, RX_CPU_BASE);
9252 err = tg3_poll_fw(tp);
9256 tw32(GRC_MODE, tp->grc_mode);
9258 if (tg3_chip_rev_id(tp) == CHIPREV_ID_5705_A0) {
9261 tw32(0xc4, val | (1 << 15));
9264 if ((tp->nic_sram_data_cfg & NIC_SRAM_DATA_CFG_MINI_PCI) != 0 &&
9265 tg3_asic_rev(tp) == ASIC_REV_5705) {
9266 tp->pci_clock_ctrl |= CLOCK_CTRL_CLKRUN_OENABLE;
9267 if (tg3_chip_rev_id(tp) == CHIPREV_ID_5705_A0)
9268 tp->pci_clock_ctrl |= CLOCK_CTRL_FORCE_CLKRUN;
9269 tw32(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl);
9272 if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES) {
9273 tp->mac_mode = MAC_MODE_PORT_MODE_TBI;
9275 } else if (tp->phy_flags & TG3_PHYFLG_MII_SERDES) {
9276 tp->mac_mode = MAC_MODE_PORT_MODE_GMII;
9281 tw32_f(MAC_MODE, val);
9284 tg3_ape_unlock(tp, TG3_APE_LOCK_GRC);
9288 if (tg3_flag(tp, PCI_EXPRESS) &&
9289 tg3_chip_rev_id(tp) != CHIPREV_ID_5750_A0 &&
9290 tg3_asic_rev(tp) != ASIC_REV_5785 &&
9291 !tg3_flag(tp, 57765_PLUS)) {
9294 tw32(0x7c00, val | (1 << 25));
9297 tg3_restore_clk(tp);
9299 /* Increase the core clock speed to fix tx timeout issue for 5762
9300 * with 100Mbps link speed.
9302 if (tg3_asic_rev(tp) == ASIC_REV_5762) {
9303 val = tr32(TG3_CPMU_CLCK_ORIDE_ENABLE);
9304 tw32(TG3_CPMU_CLCK_ORIDE_ENABLE, val |
9305 TG3_CPMU_MAC_ORIDE_ENABLE);
9308 /* Reprobe ASF enable state. */
9309 tg3_flag_clear(tp, ENABLE_ASF);
9310 tp->phy_flags &= ~(TG3_PHYFLG_1G_ON_VAUX_OK |
9311 TG3_PHYFLG_KEEP_LINK_ON_PWRDN);
9313 tg3_flag_clear(tp, ASF_NEW_HANDSHAKE);
9314 tg3_read_mem(tp, NIC_SRAM_DATA_SIG, &val);
9315 if (val == NIC_SRAM_DATA_SIG_MAGIC) {
9318 tg3_read_mem(tp, NIC_SRAM_DATA_CFG, &nic_cfg);
9319 if (nic_cfg & NIC_SRAM_DATA_CFG_ASF_ENABLE) {
9320 tg3_flag_set(tp, ENABLE_ASF);
9321 tp->last_event_jiffies = jiffies;
9322 if (tg3_flag(tp, 5750_PLUS))
9323 tg3_flag_set(tp, ASF_NEW_HANDSHAKE);
9325 tg3_read_mem(tp, NIC_SRAM_DATA_CFG_3, &nic_cfg);
9326 if (nic_cfg & NIC_SRAM_1G_ON_VAUX_OK)
9327 tp->phy_flags |= TG3_PHYFLG_1G_ON_VAUX_OK;
9328 if (nic_cfg & NIC_SRAM_LNK_FLAP_AVOID)
9329 tp->phy_flags |= TG3_PHYFLG_KEEP_LINK_ON_PWRDN;
9336 static void tg3_get_nstats(struct tg3 *, struct rtnl_link_stats64 *);
9337 static void tg3_get_estats(struct tg3 *, struct tg3_ethtool_stats *);
9338 static void __tg3_set_rx_mode(struct net_device *);
9340 /* tp->lock is held. */
9341 static int tg3_halt(struct tg3 *tp, int kind, bool silent)
9347 tg3_write_sig_pre_reset(tp, kind);
9349 tg3_abort_hw(tp, silent);
9350 err = tg3_chip_reset(tp);
9352 __tg3_set_mac_addr(tp, false);
9354 tg3_write_sig_legacy(tp, kind);
9355 tg3_write_sig_post_reset(tp, kind);
9358 /* Save the stats across chip resets... */
9359 tg3_get_nstats(tp, &tp->net_stats_prev);
9360 tg3_get_estats(tp, &tp->estats_prev);
9362 /* And make sure the next sample is new data */
9363 memset(tp->hw_stats, 0, sizeof(struct tg3_hw_stats));
9369 static int tg3_set_mac_addr(struct net_device *dev, void *p)
9371 struct tg3 *tp = netdev_priv(dev);
9372 struct sockaddr *addr = p;
9374 bool skip_mac_1 = false;
9376 if (!is_valid_ether_addr(addr->sa_data))
9377 return -EADDRNOTAVAIL;
9379 memcpy(dev->dev_addr, addr->sa_data, dev->addr_len);
9381 if (!netif_running(dev))
9384 if (tg3_flag(tp, ENABLE_ASF)) {
9385 u32 addr0_high, addr0_low, addr1_high, addr1_low;
9387 addr0_high = tr32(MAC_ADDR_0_HIGH);
9388 addr0_low = tr32(MAC_ADDR_0_LOW);
9389 addr1_high = tr32(MAC_ADDR_1_HIGH);
9390 addr1_low = tr32(MAC_ADDR_1_LOW);
9392 /* Skip MAC addr 1 if ASF is using it. */
9393 if ((addr0_high != addr1_high || addr0_low != addr1_low) &&
9394 !(addr1_high == 0 && addr1_low == 0))
9397 spin_lock_bh(&tp->lock);
9398 __tg3_set_mac_addr(tp, skip_mac_1);
9399 __tg3_set_rx_mode(dev);
9400 spin_unlock_bh(&tp->lock);
9405 /* tp->lock is held. */
9406 static void tg3_set_bdinfo(struct tg3 *tp, u32 bdinfo_addr,
9407 dma_addr_t mapping, u32 maxlen_flags,
9411 (bdinfo_addr + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_HIGH),
9412 ((u64) mapping >> 32));
9414 (bdinfo_addr + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_LOW),
9415 ((u64) mapping & 0xffffffff));
9417 (bdinfo_addr + TG3_BDINFO_MAXLEN_FLAGS),
9420 if (!tg3_flag(tp, 5705_PLUS))
9422 (bdinfo_addr + TG3_BDINFO_NIC_ADDR),
9427 static void tg3_coal_tx_init(struct tg3 *tp, struct ethtool_coalesce *ec)
9431 if (!tg3_flag(tp, ENABLE_TSS)) {
9432 tw32(HOSTCC_TXCOL_TICKS, ec->tx_coalesce_usecs);
9433 tw32(HOSTCC_TXMAX_FRAMES, ec->tx_max_coalesced_frames);
9434 tw32(HOSTCC_TXCOAL_MAXF_INT, ec->tx_max_coalesced_frames_irq);
9436 tw32(HOSTCC_TXCOL_TICKS, 0);
9437 tw32(HOSTCC_TXMAX_FRAMES, 0);
9438 tw32(HOSTCC_TXCOAL_MAXF_INT, 0);
9440 for (; i < tp->txq_cnt; i++) {
9443 reg = HOSTCC_TXCOL_TICKS_VEC1 + i * 0x18;
9444 tw32(reg, ec->tx_coalesce_usecs);
9445 reg = HOSTCC_TXMAX_FRAMES_VEC1 + i * 0x18;
9446 tw32(reg, ec->tx_max_coalesced_frames);
9447 reg = HOSTCC_TXCOAL_MAXF_INT_VEC1 + i * 0x18;
9448 tw32(reg, ec->tx_max_coalesced_frames_irq);
9452 for (; i < tp->irq_max - 1; i++) {
9453 tw32(HOSTCC_TXCOL_TICKS_VEC1 + i * 0x18, 0);
9454 tw32(HOSTCC_TXMAX_FRAMES_VEC1 + i * 0x18, 0);
9455 tw32(HOSTCC_TXCOAL_MAXF_INT_VEC1 + i * 0x18, 0);
9459 static void tg3_coal_rx_init(struct tg3 *tp, struct ethtool_coalesce *ec)
9462 u32 limit = tp->rxq_cnt;
9464 if (!tg3_flag(tp, ENABLE_RSS)) {
9465 tw32(HOSTCC_RXCOL_TICKS, ec->rx_coalesce_usecs);
9466 tw32(HOSTCC_RXMAX_FRAMES, ec->rx_max_coalesced_frames);
9467 tw32(HOSTCC_RXCOAL_MAXF_INT, ec->rx_max_coalesced_frames_irq);
9470 tw32(HOSTCC_RXCOL_TICKS, 0);
9471 tw32(HOSTCC_RXMAX_FRAMES, 0);
9472 tw32(HOSTCC_RXCOAL_MAXF_INT, 0);
9475 for (; i < limit; i++) {
9478 reg = HOSTCC_RXCOL_TICKS_VEC1 + i * 0x18;
9479 tw32(reg, ec->rx_coalesce_usecs);
9480 reg = HOSTCC_RXMAX_FRAMES_VEC1 + i * 0x18;
9481 tw32(reg, ec->rx_max_coalesced_frames);
9482 reg = HOSTCC_RXCOAL_MAXF_INT_VEC1 + i * 0x18;
9483 tw32(reg, ec->rx_max_coalesced_frames_irq);
9486 for (; i < tp->irq_max - 1; i++) {
9487 tw32(HOSTCC_RXCOL_TICKS_VEC1 + i * 0x18, 0);
9488 tw32(HOSTCC_RXMAX_FRAMES_VEC1 + i * 0x18, 0);
9489 tw32(HOSTCC_RXCOAL_MAXF_INT_VEC1 + i * 0x18, 0);
9493 static void __tg3_set_coalesce(struct tg3 *tp, struct ethtool_coalesce *ec)
9495 tg3_coal_tx_init(tp, ec);
9496 tg3_coal_rx_init(tp, ec);
9498 if (!tg3_flag(tp, 5705_PLUS)) {
9499 u32 val = ec->stats_block_coalesce_usecs;
9501 tw32(HOSTCC_RXCOAL_TICK_INT, ec->rx_coalesce_usecs_irq);
9502 tw32(HOSTCC_TXCOAL_TICK_INT, ec->tx_coalesce_usecs_irq);
9507 tw32(HOSTCC_STAT_COAL_TICKS, val);
9511 /* tp->lock is held. */
9512 static void tg3_tx_rcbs_disable(struct tg3 *tp)
9516 /* Disable all transmit rings but the first. */
9517 if (!tg3_flag(tp, 5705_PLUS))
9518 limit = NIC_SRAM_SEND_RCB + TG3_BDINFO_SIZE * 16;
9519 else if (tg3_flag(tp, 5717_PLUS))
9520 limit = NIC_SRAM_SEND_RCB + TG3_BDINFO_SIZE * 4;
9521 else if (tg3_flag(tp, 57765_CLASS) ||
9522 tg3_asic_rev(tp) == ASIC_REV_5762)
9523 limit = NIC_SRAM_SEND_RCB + TG3_BDINFO_SIZE * 2;
9525 limit = NIC_SRAM_SEND_RCB + TG3_BDINFO_SIZE;
9527 for (txrcb = NIC_SRAM_SEND_RCB + TG3_BDINFO_SIZE;
9528 txrcb < limit; txrcb += TG3_BDINFO_SIZE)
9529 tg3_write_mem(tp, txrcb + TG3_BDINFO_MAXLEN_FLAGS,
9530 BDINFO_FLAGS_DISABLED);
9533 /* tp->lock is held. */
9534 static void tg3_tx_rcbs_init(struct tg3 *tp)
9537 u32 txrcb = NIC_SRAM_SEND_RCB;
9539 if (tg3_flag(tp, ENABLE_TSS))
9542 for (; i < tp->irq_max; i++, txrcb += TG3_BDINFO_SIZE) {
9543 struct tg3_napi *tnapi = &tp->napi[i];
9545 if (!tnapi->tx_ring)
9548 tg3_set_bdinfo(tp, txrcb, tnapi->tx_desc_mapping,
9549 (TG3_TX_RING_SIZE << BDINFO_FLAGS_MAXLEN_SHIFT),
9550 NIC_SRAM_TX_BUFFER_DESC);
9554 /* tp->lock is held. */
9555 static void tg3_rx_ret_rcbs_disable(struct tg3 *tp)
9559 /* Disable all receive return rings but the first. */
9560 if (tg3_flag(tp, 5717_PLUS))
9561 limit = NIC_SRAM_RCV_RET_RCB + TG3_BDINFO_SIZE * 17;
9562 else if (!tg3_flag(tp, 5705_PLUS))
9563 limit = NIC_SRAM_RCV_RET_RCB + TG3_BDINFO_SIZE * 16;
9564 else if (tg3_asic_rev(tp) == ASIC_REV_5755 ||
9565 tg3_asic_rev(tp) == ASIC_REV_5762 ||
9566 tg3_flag(tp, 57765_CLASS))
9567 limit = NIC_SRAM_RCV_RET_RCB + TG3_BDINFO_SIZE * 4;
9569 limit = NIC_SRAM_RCV_RET_RCB + TG3_BDINFO_SIZE;
9571 for (rxrcb = NIC_SRAM_RCV_RET_RCB + TG3_BDINFO_SIZE;
9572 rxrcb < limit; rxrcb += TG3_BDINFO_SIZE)
9573 tg3_write_mem(tp, rxrcb + TG3_BDINFO_MAXLEN_FLAGS,
9574 BDINFO_FLAGS_DISABLED);
9577 /* tp->lock is held. */
9578 static void tg3_rx_ret_rcbs_init(struct tg3 *tp)
9581 u32 rxrcb = NIC_SRAM_RCV_RET_RCB;
9583 if (tg3_flag(tp, ENABLE_RSS))
9586 for (; i < tp->irq_max; i++, rxrcb += TG3_BDINFO_SIZE) {
9587 struct tg3_napi *tnapi = &tp->napi[i];
9592 tg3_set_bdinfo(tp, rxrcb, tnapi->rx_rcb_mapping,
9593 (tp->rx_ret_ring_mask + 1) <<
9594 BDINFO_FLAGS_MAXLEN_SHIFT, 0);
9598 /* tp->lock is held. */
9599 static void tg3_rings_reset(struct tg3 *tp)
9603 struct tg3_napi *tnapi = &tp->napi[0];
9605 tg3_tx_rcbs_disable(tp);
9607 tg3_rx_ret_rcbs_disable(tp);
9609 /* Disable interrupts */
9610 tw32_mailbox_f(tp->napi[0].int_mbox, 1);
9611 tp->napi[0].chk_msi_cnt = 0;
9612 tp->napi[0].last_rx_cons = 0;
9613 tp->napi[0].last_tx_cons = 0;
9615 /* Zero mailbox registers. */
9616 if (tg3_flag(tp, SUPPORT_MSIX)) {
9617 for (i = 1; i < tp->irq_max; i++) {
9618 tp->napi[i].tx_prod = 0;
9619 tp->napi[i].tx_cons = 0;
9620 if (tg3_flag(tp, ENABLE_TSS))
9621 tw32_mailbox(tp->napi[i].prodmbox, 0);
9622 tw32_rx_mbox(tp->napi[i].consmbox, 0);
9623 tw32_mailbox_f(tp->napi[i].int_mbox, 1);
9624 tp->napi[i].chk_msi_cnt = 0;
9625 tp->napi[i].last_rx_cons = 0;
9626 tp->napi[i].last_tx_cons = 0;
9628 if (!tg3_flag(tp, ENABLE_TSS))
9629 tw32_mailbox(tp->napi[0].prodmbox, 0);
9631 tp->napi[0].tx_prod = 0;
9632 tp->napi[0].tx_cons = 0;
9633 tw32_mailbox(tp->napi[0].prodmbox, 0);
9634 tw32_rx_mbox(tp->napi[0].consmbox, 0);
9637 /* Make sure the NIC-based send BD rings are disabled. */
9638 if (!tg3_flag(tp, 5705_PLUS)) {
9639 u32 mbox = MAILBOX_SNDNIC_PROD_IDX_0 + TG3_64BIT_REG_LOW;
9640 for (i = 0; i < 16; i++)
9641 tw32_tx_mbox(mbox + i * 8, 0);
9644 /* Clear status block in ram. */
9645 memset(tnapi->hw_status, 0, TG3_HW_STATUS_SIZE);
9647 /* Set status block DMA address */
9648 tw32(HOSTCC_STATUS_BLK_HOST_ADDR + TG3_64BIT_REG_HIGH,
9649 ((u64) tnapi->status_mapping >> 32));
9650 tw32(HOSTCC_STATUS_BLK_HOST_ADDR + TG3_64BIT_REG_LOW,
9651 ((u64) tnapi->status_mapping & 0xffffffff));
9653 stblk = HOSTCC_STATBLCK_RING1;
9655 for (i = 1, tnapi++; i < tp->irq_cnt; i++, tnapi++) {
9656 u64 mapping = (u64)tnapi->status_mapping;
9657 tw32(stblk + TG3_64BIT_REG_HIGH, mapping >> 32);
9658 tw32(stblk + TG3_64BIT_REG_LOW, mapping & 0xffffffff);
9661 /* Clear status block in ram. */
9662 memset(tnapi->hw_status, 0, TG3_HW_STATUS_SIZE);
9665 tg3_tx_rcbs_init(tp);
9666 tg3_rx_ret_rcbs_init(tp);
9669 static void tg3_setup_rxbd_thresholds(struct tg3 *tp)
9671 u32 val, bdcache_maxcnt, host_rep_thresh, nic_rep_thresh;
9673 if (!tg3_flag(tp, 5750_PLUS) ||
9674 tg3_flag(tp, 5780_CLASS) ||
9675 tg3_asic_rev(tp) == ASIC_REV_5750 ||
9676 tg3_asic_rev(tp) == ASIC_REV_5752 ||
9677 tg3_flag(tp, 57765_PLUS))
9678 bdcache_maxcnt = TG3_SRAM_RX_STD_BDCACHE_SIZE_5700;
9679 else if (tg3_asic_rev(tp) == ASIC_REV_5755 ||
9680 tg3_asic_rev(tp) == ASIC_REV_5787)
9681 bdcache_maxcnt = TG3_SRAM_RX_STD_BDCACHE_SIZE_5755;
9683 bdcache_maxcnt = TG3_SRAM_RX_STD_BDCACHE_SIZE_5906;
9685 nic_rep_thresh = min(bdcache_maxcnt / 2, tp->rx_std_max_post);
9686 host_rep_thresh = max_t(u32, tp->rx_pending / 8, 1);
9688 val = min(nic_rep_thresh, host_rep_thresh);
9689 tw32(RCVBDI_STD_THRESH, val);
9691 if (tg3_flag(tp, 57765_PLUS))
9692 tw32(STD_REPLENISH_LWM, bdcache_maxcnt);
9694 if (!tg3_flag(tp, JUMBO_CAPABLE) || tg3_flag(tp, 5780_CLASS))
9697 bdcache_maxcnt = TG3_SRAM_RX_JMB_BDCACHE_SIZE_5700;
9699 host_rep_thresh = max_t(u32, tp->rx_jumbo_pending / 8, 1);
9701 val = min(bdcache_maxcnt / 2, host_rep_thresh);
9702 tw32(RCVBDI_JUMBO_THRESH, val);
9704 if (tg3_flag(tp, 57765_PLUS))
9705 tw32(JMB_REPLENISH_LWM, bdcache_maxcnt);
9708 static inline u32 calc_crc(unsigned char *buf, int len)
9716 for (j = 0; j < len; j++) {
9719 for (k = 0; k < 8; k++) {
9732 static void tg3_set_multi(struct tg3 *tp, unsigned int accept_all)
9734 /* accept or reject all multicast frames */
9735 tw32(MAC_HASH_REG_0, accept_all ? 0xffffffff : 0);
9736 tw32(MAC_HASH_REG_1, accept_all ? 0xffffffff : 0);
9737 tw32(MAC_HASH_REG_2, accept_all ? 0xffffffff : 0);
9738 tw32(MAC_HASH_REG_3, accept_all ? 0xffffffff : 0);
9741 static void __tg3_set_rx_mode(struct net_device *dev)
9743 struct tg3 *tp = netdev_priv(dev);
9746 rx_mode = tp->rx_mode & ~(RX_MODE_PROMISC |
9747 RX_MODE_KEEP_VLAN_TAG);
9749 #if !defined(CONFIG_VLAN_8021Q) && !defined(CONFIG_VLAN_8021Q_MODULE)
9750 /* When ASF is in use, we always keep the RX_MODE_KEEP_VLAN_TAG
9753 if (!tg3_flag(tp, ENABLE_ASF))
9754 rx_mode |= RX_MODE_KEEP_VLAN_TAG;
9757 if (dev->flags & IFF_PROMISC) {
9758 /* Promiscuous mode. */
9759 rx_mode |= RX_MODE_PROMISC;
9760 } else if (dev->flags & IFF_ALLMULTI) {
9761 /* Accept all multicast. */
9762 tg3_set_multi(tp, 1);
9763 } else if (netdev_mc_empty(dev)) {
9764 /* Reject all multicast. */
9765 tg3_set_multi(tp, 0);
9767 /* Accept one or more multicast(s). */
9768 struct netdev_hw_addr *ha;
9769 u32 mc_filter[4] = { 0, };
9774 netdev_for_each_mc_addr(ha, dev) {
9775 crc = calc_crc(ha->addr, ETH_ALEN);
9777 regidx = (bit & 0x60) >> 5;
9779 mc_filter[regidx] |= (1 << bit);
9782 tw32(MAC_HASH_REG_0, mc_filter[0]);
9783 tw32(MAC_HASH_REG_1, mc_filter[1]);
9784 tw32(MAC_HASH_REG_2, mc_filter[2]);
9785 tw32(MAC_HASH_REG_3, mc_filter[3]);
9788 if (netdev_uc_count(dev) > TG3_MAX_UCAST_ADDR(tp)) {
9789 rx_mode |= RX_MODE_PROMISC;
9790 } else if (!(dev->flags & IFF_PROMISC)) {
9791 /* Add all entries into to the mac addr filter list */
9793 struct netdev_hw_addr *ha;
9795 netdev_for_each_uc_addr(ha, dev) {
9796 __tg3_set_one_mac_addr(tp, ha->addr,
9797 i + TG3_UCAST_ADDR_IDX(tp));
9802 if (rx_mode != tp->rx_mode) {
9803 tp->rx_mode = rx_mode;
9804 tw32_f(MAC_RX_MODE, rx_mode);
9809 static void tg3_rss_init_dflt_indir_tbl(struct tg3 *tp, u32 qcnt)
9813 for (i = 0; i < TG3_RSS_INDIR_TBL_SIZE; i++)
9814 tp->rss_ind_tbl[i] = ethtool_rxfh_indir_default(i, qcnt);
9817 static void tg3_rss_check_indir_tbl(struct tg3 *tp)
9821 if (!tg3_flag(tp, SUPPORT_MSIX))
9824 if (tp->rxq_cnt == 1) {
9825 memset(&tp->rss_ind_tbl[0], 0, sizeof(tp->rss_ind_tbl));
9829 /* Validate table against current IRQ count */
9830 for (i = 0; i < TG3_RSS_INDIR_TBL_SIZE; i++) {
9831 if (tp->rss_ind_tbl[i] >= tp->rxq_cnt)
9835 if (i != TG3_RSS_INDIR_TBL_SIZE)
9836 tg3_rss_init_dflt_indir_tbl(tp, tp->rxq_cnt);
9839 static void tg3_rss_write_indir_tbl(struct tg3 *tp)
9842 u32 reg = MAC_RSS_INDIR_TBL_0;
9844 while (i < TG3_RSS_INDIR_TBL_SIZE) {
9845 u32 val = tp->rss_ind_tbl[i];
9847 for (; i % 8; i++) {
9849 val |= tp->rss_ind_tbl[i];
9856 static inline u32 tg3_lso_rd_dma_workaround_bit(struct tg3 *tp)
9858 if (tg3_asic_rev(tp) == ASIC_REV_5719)
9859 return TG3_LSO_RD_DMA_TX_LENGTH_WA_5719;
9861 return TG3_LSO_RD_DMA_TX_LENGTH_WA_5720;
9864 /* tp->lock is held. */
9865 static int tg3_reset_hw(struct tg3 *tp, bool reset_phy)
9867 u32 val, rdmac_mode;
9869 struct tg3_rx_prodring_set *tpr = &tp->napi[0].prodring;
9871 tg3_disable_ints(tp);
9875 tg3_write_sig_pre_reset(tp, RESET_KIND_INIT);
9877 if (tg3_flag(tp, INIT_COMPLETE))
9878 tg3_abort_hw(tp, 1);
9880 if ((tp->phy_flags & TG3_PHYFLG_KEEP_LINK_ON_PWRDN) &&
9881 !(tp->phy_flags & TG3_PHYFLG_USER_CONFIGURED)) {
9882 tg3_phy_pull_config(tp);
9883 tg3_eee_pull_config(tp, NULL);
9884 tp->phy_flags |= TG3_PHYFLG_USER_CONFIGURED;
9887 /* Enable MAC control of LPI */
9888 if (tp->phy_flags & TG3_PHYFLG_EEE_CAP)
9894 err = tg3_chip_reset(tp);
9898 tg3_write_sig_legacy(tp, RESET_KIND_INIT);
9900 if (tg3_chip_rev(tp) == CHIPREV_5784_AX) {
9901 val = tr32(TG3_CPMU_CTRL);
9902 val &= ~(CPMU_CTRL_LINK_AWARE_MODE | CPMU_CTRL_LINK_IDLE_MODE);
9903 tw32(TG3_CPMU_CTRL, val);
9905 val = tr32(TG3_CPMU_LSPD_10MB_CLK);
9906 val &= ~CPMU_LSPD_10MB_MACCLK_MASK;
9907 val |= CPMU_LSPD_10MB_MACCLK_6_25;
9908 tw32(TG3_CPMU_LSPD_10MB_CLK, val);
9910 val = tr32(TG3_CPMU_LNK_AWARE_PWRMD);
9911 val &= ~CPMU_LNK_AWARE_MACCLK_MASK;
9912 val |= CPMU_LNK_AWARE_MACCLK_6_25;
9913 tw32(TG3_CPMU_LNK_AWARE_PWRMD, val);
9915 val = tr32(TG3_CPMU_HST_ACC);
9916 val &= ~CPMU_HST_ACC_MACCLK_MASK;
9917 val |= CPMU_HST_ACC_MACCLK_6_25;
9918 tw32(TG3_CPMU_HST_ACC, val);
9921 if (tg3_asic_rev(tp) == ASIC_REV_57780) {
9922 val = tr32(PCIE_PWR_MGMT_THRESH) & ~PCIE_PWR_MGMT_L1_THRESH_MSK;
9923 val |= PCIE_PWR_MGMT_EXT_ASPM_TMR_EN |
9924 PCIE_PWR_MGMT_L1_THRESH_4MS;
9925 tw32(PCIE_PWR_MGMT_THRESH, val);
9927 val = tr32(TG3_PCIE_EIDLE_DELAY) & ~TG3_PCIE_EIDLE_DELAY_MASK;
9928 tw32(TG3_PCIE_EIDLE_DELAY, val | TG3_PCIE_EIDLE_DELAY_13_CLKS);
9930 tw32(TG3_CORR_ERR_STAT, TG3_CORR_ERR_STAT_CLEAR);
9932 val = tr32(TG3_PCIE_LNKCTL) & ~TG3_PCIE_LNKCTL_L1_PLL_PD_EN;
9933 tw32(TG3_PCIE_LNKCTL, val | TG3_PCIE_LNKCTL_L1_PLL_PD_DIS);
9936 if (tg3_flag(tp, L1PLLPD_EN)) {
9937 u32 grc_mode = tr32(GRC_MODE);
9939 /* Access the lower 1K of PL PCIE block registers. */
9940 val = grc_mode & ~GRC_MODE_PCIE_PORT_MASK;
9941 tw32(GRC_MODE, val | GRC_MODE_PCIE_PL_SEL);
9943 val = tr32(TG3_PCIE_TLDLPL_PORT + TG3_PCIE_PL_LO_PHYCTL1);
9944 tw32(TG3_PCIE_TLDLPL_PORT + TG3_PCIE_PL_LO_PHYCTL1,
9945 val | TG3_PCIE_PL_LO_PHYCTL1_L1PLLPD_EN);
9947 tw32(GRC_MODE, grc_mode);
9950 if (tg3_flag(tp, 57765_CLASS)) {
9951 if (tg3_chip_rev_id(tp) == CHIPREV_ID_57765_A0) {
9952 u32 grc_mode = tr32(GRC_MODE);
9954 /* Access the lower 1K of PL PCIE block registers. */
9955 val = grc_mode & ~GRC_MODE_PCIE_PORT_MASK;
9956 tw32(GRC_MODE, val | GRC_MODE_PCIE_PL_SEL);
9958 val = tr32(TG3_PCIE_TLDLPL_PORT +
9959 TG3_PCIE_PL_LO_PHYCTL5);
9960 tw32(TG3_PCIE_TLDLPL_PORT + TG3_PCIE_PL_LO_PHYCTL5,
9961 val | TG3_PCIE_PL_LO_PHYCTL5_DIS_L2CLKREQ);
9963 tw32(GRC_MODE, grc_mode);
9966 if (tg3_chip_rev(tp) != CHIPREV_57765_AX) {
9969 /* Fix transmit hangs */
9970 val = tr32(TG3_CPMU_PADRNG_CTL);
9971 val |= TG3_CPMU_PADRNG_CTL_RDIV2;
9972 tw32(TG3_CPMU_PADRNG_CTL, val);
9974 grc_mode = tr32(GRC_MODE);
9976 /* Access the lower 1K of DL PCIE block registers. */
9977 val = grc_mode & ~GRC_MODE_PCIE_PORT_MASK;
9978 tw32(GRC_MODE, val | GRC_MODE_PCIE_DL_SEL);
9980 val = tr32(TG3_PCIE_TLDLPL_PORT +
9981 TG3_PCIE_DL_LO_FTSMAX);
9982 val &= ~TG3_PCIE_DL_LO_FTSMAX_MSK;
9983 tw32(TG3_PCIE_TLDLPL_PORT + TG3_PCIE_DL_LO_FTSMAX,
9984 val | TG3_PCIE_DL_LO_FTSMAX_VAL);
9986 tw32(GRC_MODE, grc_mode);
9989 val = tr32(TG3_CPMU_LSPD_10MB_CLK);
9990 val &= ~CPMU_LSPD_10MB_MACCLK_MASK;
9991 val |= CPMU_LSPD_10MB_MACCLK_6_25;
9992 tw32(TG3_CPMU_LSPD_10MB_CLK, val);
9995 /* This works around an issue with Athlon chipsets on
9996 * B3 tigon3 silicon. This bit has no effect on any
9997 * other revision. But do not set this on PCI Express
9998 * chips and don't even touch the clocks if the CPMU is present.
10000 if (!tg3_flag(tp, CPMU_PRESENT)) {
10001 if (!tg3_flag(tp, PCI_EXPRESS))
10002 tp->pci_clock_ctrl |= CLOCK_CTRL_DELAY_PCI_GRANT;
10003 tw32_f(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl);
10006 if (tg3_chip_rev_id(tp) == CHIPREV_ID_5704_A0 &&
10007 tg3_flag(tp, PCIX_MODE)) {
10008 val = tr32(TG3PCI_PCISTATE);
10009 val |= PCISTATE_RETRY_SAME_DMA;
10010 tw32(TG3PCI_PCISTATE, val);
10013 if (tg3_flag(tp, ENABLE_APE)) {
10014 /* Allow reads and writes to the
10015 * APE register and memory space.
10017 val = tr32(TG3PCI_PCISTATE);
10018 val |= PCISTATE_ALLOW_APE_CTLSPC_WR |
10019 PCISTATE_ALLOW_APE_SHMEM_WR |
10020 PCISTATE_ALLOW_APE_PSPACE_WR;
10021 tw32(TG3PCI_PCISTATE, val);
10024 if (tg3_chip_rev(tp) == CHIPREV_5704_BX) {
10025 /* Enable some hw fixes. */
10026 val = tr32(TG3PCI_MSI_DATA);
10027 val |= (1 << 26) | (1 << 28) | (1 << 29);
10028 tw32(TG3PCI_MSI_DATA, val);
10031 /* Descriptor ring init may make accesses to the
10032 * NIC SRAM area to setup the TX descriptors, so we
10033 * can only do this after the hardware has been
10034 * successfully reset.
10036 err = tg3_init_rings(tp);
10040 if (tg3_flag(tp, 57765_PLUS)) {
10041 val = tr32(TG3PCI_DMA_RW_CTRL) &
10042 ~DMA_RWCTRL_DIS_CACHE_ALIGNMENT;
10043 if (tg3_chip_rev_id(tp) == CHIPREV_ID_57765_A0)
10044 val &= ~DMA_RWCTRL_CRDRDR_RDMA_MRRS_MSK;
10045 if (!tg3_flag(tp, 57765_CLASS) &&
10046 tg3_asic_rev(tp) != ASIC_REV_5717 &&
10047 tg3_asic_rev(tp) != ASIC_REV_5762)
10048 val |= DMA_RWCTRL_TAGGED_STAT_WA;
10049 tw32(TG3PCI_DMA_RW_CTRL, val | tp->dma_rwctrl);
10050 } else if (tg3_asic_rev(tp) != ASIC_REV_5784 &&
10051 tg3_asic_rev(tp) != ASIC_REV_5761) {
10052 /* This value is determined during the probe time DMA
10053 * engine test, tg3_test_dma.
10055 tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
10058 tp->grc_mode &= ~(GRC_MODE_HOST_SENDBDS |
10059 GRC_MODE_4X_NIC_SEND_RINGS |
10060 GRC_MODE_NO_TX_PHDR_CSUM |
10061 GRC_MODE_NO_RX_PHDR_CSUM);
10062 tp->grc_mode |= GRC_MODE_HOST_SENDBDS;
10064 /* Pseudo-header checksum is done by hardware logic and not
10065 * the offload processers, so make the chip do the pseudo-
10066 * header checksums on receive. For transmit it is more
10067 * convenient to do the pseudo-header checksum in software
10068 * as Linux does that on transmit for us in all cases.
10070 tp->grc_mode |= GRC_MODE_NO_TX_PHDR_CSUM;
10072 val = GRC_MODE_IRQ_ON_MAC_ATTN | GRC_MODE_HOST_STACKUP;
10074 tw32(TG3_RX_PTP_CTL,
10075 tp->rxptpctl | TG3_RX_PTP_CTL_HWTS_INTERLOCK);
10077 if (tg3_flag(tp, PTP_CAPABLE))
10078 val |= GRC_MODE_TIME_SYNC_ENABLE;
10080 tw32(GRC_MODE, tp->grc_mode | val);
10082 /* On one of the AMD platform, MRRS is restricted to 4000 because of
10083 * south bridge limitation. As a workaround, Driver is setting MRRS
10084 * to 2048 instead of default 4096.
10086 if (tp->pdev->subsystem_vendor == PCI_VENDOR_ID_DELL &&
10087 tp->pdev->subsystem_device == TG3PCI_SUBDEVICE_ID_DELL_5762) {
10088 val = tr32(TG3PCI_DEV_STATUS_CTRL) & ~MAX_READ_REQ_MASK;
10089 tw32(TG3PCI_DEV_STATUS_CTRL, val | MAX_READ_REQ_SIZE_2048);
10092 /* Setup the timer prescalar register. Clock is always 66Mhz. */
10093 val = tr32(GRC_MISC_CFG);
10095 val |= (65 << GRC_MISC_CFG_PRESCALAR_SHIFT);
10096 tw32(GRC_MISC_CFG, val);
10098 /* Initialize MBUF/DESC pool. */
10099 if (tg3_flag(tp, 5750_PLUS)) {
10101 } else if (tg3_asic_rev(tp) != ASIC_REV_5705) {
10102 tw32(BUFMGR_MB_POOL_ADDR, NIC_SRAM_MBUF_POOL_BASE);
10103 if (tg3_asic_rev(tp) == ASIC_REV_5704)
10104 tw32(BUFMGR_MB_POOL_SIZE, NIC_SRAM_MBUF_POOL_SIZE64);
10106 tw32(BUFMGR_MB_POOL_SIZE, NIC_SRAM_MBUF_POOL_SIZE96);
10107 tw32(BUFMGR_DMA_DESC_POOL_ADDR, NIC_SRAM_DMA_DESC_POOL_BASE);
10108 tw32(BUFMGR_DMA_DESC_POOL_SIZE, NIC_SRAM_DMA_DESC_POOL_SIZE);
10109 } else if (tg3_flag(tp, TSO_CAPABLE)) {
10112 fw_len = tp->fw_len;
10113 fw_len = (fw_len + (0x80 - 1)) & ~(0x80 - 1);
10114 tw32(BUFMGR_MB_POOL_ADDR,
10115 NIC_SRAM_MBUF_POOL_BASE5705 + fw_len);
10116 tw32(BUFMGR_MB_POOL_SIZE,
10117 NIC_SRAM_MBUF_POOL_SIZE5705 - fw_len - 0xa00);
10120 if (tp->dev->mtu <= ETH_DATA_LEN) {
10121 tw32(BUFMGR_MB_RDMA_LOW_WATER,
10122 tp->bufmgr_config.mbuf_read_dma_low_water);
10123 tw32(BUFMGR_MB_MACRX_LOW_WATER,
10124 tp->bufmgr_config.mbuf_mac_rx_low_water);
10125 tw32(BUFMGR_MB_HIGH_WATER,
10126 tp->bufmgr_config.mbuf_high_water);
10128 tw32(BUFMGR_MB_RDMA_LOW_WATER,
10129 tp->bufmgr_config.mbuf_read_dma_low_water_jumbo);
10130 tw32(BUFMGR_MB_MACRX_LOW_WATER,
10131 tp->bufmgr_config.mbuf_mac_rx_low_water_jumbo);
10132 tw32(BUFMGR_MB_HIGH_WATER,
10133 tp->bufmgr_config.mbuf_high_water_jumbo);
10135 tw32(BUFMGR_DMA_LOW_WATER,
10136 tp->bufmgr_config.dma_low_water);
10137 tw32(BUFMGR_DMA_HIGH_WATER,
10138 tp->bufmgr_config.dma_high_water);
10140 val = BUFMGR_MODE_ENABLE | BUFMGR_MODE_ATTN_ENABLE;
10141 if (tg3_asic_rev(tp) == ASIC_REV_5719)
10142 val |= BUFMGR_MODE_NO_TX_UNDERRUN;
10143 if (tg3_asic_rev(tp) == ASIC_REV_5717 ||
10144 tg3_asic_rev(tp) == ASIC_REV_5762 ||
10145 tg3_chip_rev_id(tp) == CHIPREV_ID_5719_A0 ||
10146 tg3_chip_rev_id(tp) == CHIPREV_ID_5720_A0)
10147 val |= BUFMGR_MODE_MBLOW_ATTN_ENAB;
10148 tw32(BUFMGR_MODE, val);
10149 for (i = 0; i < 2000; i++) {
10150 if (tr32(BUFMGR_MODE) & BUFMGR_MODE_ENABLE)
10155 netdev_err(tp->dev, "%s cannot enable BUFMGR\n", __func__);
10159 if (tg3_chip_rev_id(tp) == CHIPREV_ID_5906_A1)
10160 tw32(ISO_PKT_TX, (tr32(ISO_PKT_TX) & ~0x3) | 0x2);
10162 tg3_setup_rxbd_thresholds(tp);
10164 /* Initialize TG3_BDINFO's at:
10165 * RCVDBDI_STD_BD: standard eth size rx ring
10166 * RCVDBDI_JUMBO_BD: jumbo frame rx ring
10167 * RCVDBDI_MINI_BD: small frame rx ring (??? does not work)
10170 * TG3_BDINFO_HOST_ADDR: high/low parts of DMA address of ring
10171 * TG3_BDINFO_MAXLEN_FLAGS: (rx max buffer size << 16) |
10172 * ring attribute flags
10173 * TG3_BDINFO_NIC_ADDR: location of descriptors in nic SRAM
10175 * Standard receive ring @ NIC_SRAM_RX_BUFFER_DESC, 512 entries.
10176 * Jumbo receive ring @ NIC_SRAM_RX_JUMBO_BUFFER_DESC, 256 entries.
10178 * The size of each ring is fixed in the firmware, but the location is
10181 tw32(RCVDBDI_STD_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_HIGH,
10182 ((u64) tpr->rx_std_mapping >> 32));
10183 tw32(RCVDBDI_STD_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_LOW,
10184 ((u64) tpr->rx_std_mapping & 0xffffffff));
10185 if (!tg3_flag(tp, 5717_PLUS))
10186 tw32(RCVDBDI_STD_BD + TG3_BDINFO_NIC_ADDR,
10187 NIC_SRAM_RX_BUFFER_DESC);
10189 /* Disable the mini ring */
10190 if (!tg3_flag(tp, 5705_PLUS))
10191 tw32(RCVDBDI_MINI_BD + TG3_BDINFO_MAXLEN_FLAGS,
10192 BDINFO_FLAGS_DISABLED);
10194 /* Program the jumbo buffer descriptor ring control
10195 * blocks on those devices that have them.
10197 if (tg3_chip_rev_id(tp) == CHIPREV_ID_5719_A0 ||
10198 (tg3_flag(tp, JUMBO_CAPABLE) && !tg3_flag(tp, 5780_CLASS))) {
10200 if (tg3_flag(tp, JUMBO_RING_ENABLE)) {
10201 tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_HIGH,
10202 ((u64) tpr->rx_jmb_mapping >> 32));
10203 tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_LOW,
10204 ((u64) tpr->rx_jmb_mapping & 0xffffffff));
10205 val = TG3_RX_JMB_RING_SIZE(tp) <<
10206 BDINFO_FLAGS_MAXLEN_SHIFT;
10207 tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_MAXLEN_FLAGS,
10208 val | BDINFO_FLAGS_USE_EXT_RECV);
10209 if (!tg3_flag(tp, USE_JUMBO_BDFLAG) ||
10210 tg3_flag(tp, 57765_CLASS) ||
10211 tg3_asic_rev(tp) == ASIC_REV_5762)
10212 tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_NIC_ADDR,
10213 NIC_SRAM_RX_JUMBO_BUFFER_DESC);
10215 tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_MAXLEN_FLAGS,
10216 BDINFO_FLAGS_DISABLED);
10219 if (tg3_flag(tp, 57765_PLUS)) {
10220 val = TG3_RX_STD_RING_SIZE(tp);
10221 val <<= BDINFO_FLAGS_MAXLEN_SHIFT;
10222 val |= (TG3_RX_STD_DMA_SZ << 2);
10224 val = TG3_RX_STD_DMA_SZ << BDINFO_FLAGS_MAXLEN_SHIFT;
10226 val = TG3_RX_STD_MAX_SIZE_5700 << BDINFO_FLAGS_MAXLEN_SHIFT;
10228 tw32(RCVDBDI_STD_BD + TG3_BDINFO_MAXLEN_FLAGS, val);
10230 tpr->rx_std_prod_idx = tp->rx_pending;
10231 tw32_rx_mbox(TG3_RX_STD_PROD_IDX_REG, tpr->rx_std_prod_idx);
10233 tpr->rx_jmb_prod_idx =
10234 tg3_flag(tp, JUMBO_RING_ENABLE) ? tp->rx_jumbo_pending : 0;
10235 tw32_rx_mbox(TG3_RX_JMB_PROD_IDX_REG, tpr->rx_jmb_prod_idx);
10237 tg3_rings_reset(tp);
10239 /* Initialize MAC address and backoff seed. */
10240 __tg3_set_mac_addr(tp, false);
10242 /* MTU + ethernet header + FCS + optional VLAN tag */
10243 tw32(MAC_RX_MTU_SIZE,
10244 tp->dev->mtu + ETH_HLEN + ETH_FCS_LEN + VLAN_HLEN);
10246 /* The slot time is changed by tg3_setup_phy if we
10247 * run at gigabit with half duplex.
10249 val = (2 << TX_LENGTHS_IPG_CRS_SHIFT) |
10250 (6 << TX_LENGTHS_IPG_SHIFT) |
10251 (32 << TX_LENGTHS_SLOT_TIME_SHIFT);
10253 if (tg3_asic_rev(tp) == ASIC_REV_5720 ||
10254 tg3_asic_rev(tp) == ASIC_REV_5762)
10255 val |= tr32(MAC_TX_LENGTHS) &
10256 (TX_LENGTHS_JMB_FRM_LEN_MSK |
10257 TX_LENGTHS_CNT_DWN_VAL_MSK);
10259 tw32(MAC_TX_LENGTHS, val);
10261 /* Receive rules. */
10262 tw32(MAC_RCV_RULE_CFG, RCV_RULE_CFG_DEFAULT_CLASS);
10263 tw32(RCVLPC_CONFIG, 0x0181);
10265 /* Calculate RDMAC_MODE setting early, we need it to determine
10266 * the RCVLPC_STATE_ENABLE mask.
10268 rdmac_mode = (RDMAC_MODE_ENABLE | RDMAC_MODE_TGTABORT_ENAB |
10269 RDMAC_MODE_MSTABORT_ENAB | RDMAC_MODE_PARITYERR_ENAB |
10270 RDMAC_MODE_ADDROFLOW_ENAB | RDMAC_MODE_FIFOOFLOW_ENAB |
10271 RDMAC_MODE_FIFOURUN_ENAB | RDMAC_MODE_FIFOOREAD_ENAB |
10272 RDMAC_MODE_LNGREAD_ENAB);
10274 if (tg3_asic_rev(tp) == ASIC_REV_5717)
10275 rdmac_mode |= RDMAC_MODE_MULT_DMA_RD_DIS;
10277 if (tg3_asic_rev(tp) == ASIC_REV_5784 ||
10278 tg3_asic_rev(tp) == ASIC_REV_5785 ||
10279 tg3_asic_rev(tp) == ASIC_REV_57780)
10280 rdmac_mode |= RDMAC_MODE_BD_SBD_CRPT_ENAB |
10281 RDMAC_MODE_MBUF_RBD_CRPT_ENAB |
10282 RDMAC_MODE_MBUF_SBD_CRPT_ENAB;
10284 if (tg3_asic_rev(tp) == ASIC_REV_5705 &&
10285 tg3_chip_rev_id(tp) != CHIPREV_ID_5705_A0) {
10286 if (tg3_flag(tp, TSO_CAPABLE) &&
10287 tg3_asic_rev(tp) == ASIC_REV_5705) {
10288 rdmac_mode |= RDMAC_MODE_FIFO_SIZE_128;
10289 } else if (!(tr32(TG3PCI_PCISTATE) & PCISTATE_BUS_SPEED_HIGH) &&
10290 !tg3_flag(tp, IS_5788)) {
10291 rdmac_mode |= RDMAC_MODE_FIFO_LONG_BURST;
10295 if (tg3_flag(tp, PCI_EXPRESS))
10296 rdmac_mode |= RDMAC_MODE_FIFO_LONG_BURST;
10298 if (tg3_asic_rev(tp) == ASIC_REV_57766) {
10300 if (tp->dev->mtu <= ETH_DATA_LEN) {
10301 rdmac_mode |= RDMAC_MODE_JMB_2K_MMRR;
10302 tp->dma_limit = TG3_TX_BD_DMA_MAX_2K;
10306 if (tg3_flag(tp, HW_TSO_1) ||
10307 tg3_flag(tp, HW_TSO_2) ||
10308 tg3_flag(tp, HW_TSO_3))
10309 rdmac_mode |= RDMAC_MODE_IPV4_LSO_EN;
10311 if (tg3_flag(tp, 57765_PLUS) ||
10312 tg3_asic_rev(tp) == ASIC_REV_5785 ||
10313 tg3_asic_rev(tp) == ASIC_REV_57780)
10314 rdmac_mode |= RDMAC_MODE_IPV6_LSO_EN;
10316 if (tg3_asic_rev(tp) == ASIC_REV_5720 ||
10317 tg3_asic_rev(tp) == ASIC_REV_5762)
10318 rdmac_mode |= tr32(RDMAC_MODE) & RDMAC_MODE_H2BNC_VLAN_DET;
10320 if (tg3_asic_rev(tp) == ASIC_REV_5761 ||
10321 tg3_asic_rev(tp) == ASIC_REV_5784 ||
10322 tg3_asic_rev(tp) == ASIC_REV_5785 ||
10323 tg3_asic_rev(tp) == ASIC_REV_57780 ||
10324 tg3_flag(tp, 57765_PLUS)) {
10327 if (tg3_asic_rev(tp) == ASIC_REV_5762)
10328 tgtreg = TG3_RDMA_RSRVCTRL_REG2;
10330 tgtreg = TG3_RDMA_RSRVCTRL_REG;
10332 val = tr32(tgtreg);
10333 if (tg3_chip_rev_id(tp) == CHIPREV_ID_5719_A0 ||
10334 tg3_asic_rev(tp) == ASIC_REV_5762) {
10335 val &= ~(TG3_RDMA_RSRVCTRL_TXMRGN_MASK |
10336 TG3_RDMA_RSRVCTRL_FIFO_LWM_MASK |
10337 TG3_RDMA_RSRVCTRL_FIFO_HWM_MASK);
10338 val |= TG3_RDMA_RSRVCTRL_TXMRGN_320B |
10339 TG3_RDMA_RSRVCTRL_FIFO_LWM_1_5K |
10340 TG3_RDMA_RSRVCTRL_FIFO_HWM_1_5K;
10342 tw32(tgtreg, val | TG3_RDMA_RSRVCTRL_FIFO_OFLW_FIX);
10345 if (tg3_asic_rev(tp) == ASIC_REV_5719 ||
10346 tg3_asic_rev(tp) == ASIC_REV_5720 ||
10347 tg3_asic_rev(tp) == ASIC_REV_5762) {
10350 if (tg3_asic_rev(tp) == ASIC_REV_5762)
10351 tgtreg = TG3_LSO_RD_DMA_CRPTEN_CTRL2;
10353 tgtreg = TG3_LSO_RD_DMA_CRPTEN_CTRL;
10355 val = tr32(tgtreg);
10357 TG3_LSO_RD_DMA_CRPTEN_CTRL_BLEN_BD_4K |
10358 TG3_LSO_RD_DMA_CRPTEN_CTRL_BLEN_LSO_4K);
10361 /* Receive/send statistics. */
10362 if (tg3_flag(tp, 5750_PLUS)) {
10363 val = tr32(RCVLPC_STATS_ENABLE);
10364 val &= ~RCVLPC_STATSENAB_DACK_FIX;
10365 tw32(RCVLPC_STATS_ENABLE, val);
10366 } else if ((rdmac_mode & RDMAC_MODE_FIFO_SIZE_128) &&
10367 tg3_flag(tp, TSO_CAPABLE)) {
10368 val = tr32(RCVLPC_STATS_ENABLE);
10369 val &= ~RCVLPC_STATSENAB_LNGBRST_RFIX;
10370 tw32(RCVLPC_STATS_ENABLE, val);
10372 tw32(RCVLPC_STATS_ENABLE, 0xffffff);
10374 tw32(RCVLPC_STATSCTRL, RCVLPC_STATSCTRL_ENABLE);
10375 tw32(SNDDATAI_STATSENAB, 0xffffff);
10376 tw32(SNDDATAI_STATSCTRL,
10377 (SNDDATAI_SCTRL_ENABLE |
10378 SNDDATAI_SCTRL_FASTUPD));
10380 /* Setup host coalescing engine. */
10381 tw32(HOSTCC_MODE, 0);
10382 for (i = 0; i < 2000; i++) {
10383 if (!(tr32(HOSTCC_MODE) & HOSTCC_MODE_ENABLE))
10388 __tg3_set_coalesce(tp, &tp->coal);
10390 if (!tg3_flag(tp, 5705_PLUS)) {
10391 /* Status/statistics block address. See tg3_timer,
10392 * the tg3_periodic_fetch_stats call there, and
10393 * tg3_get_stats to see how this works for 5705/5750 chips.
10395 tw32(HOSTCC_STATS_BLK_HOST_ADDR + TG3_64BIT_REG_HIGH,
10396 ((u64) tp->stats_mapping >> 32));
10397 tw32(HOSTCC_STATS_BLK_HOST_ADDR + TG3_64BIT_REG_LOW,
10398 ((u64) tp->stats_mapping & 0xffffffff));
10399 tw32(HOSTCC_STATS_BLK_NIC_ADDR, NIC_SRAM_STATS_BLK);
10401 tw32(HOSTCC_STATUS_BLK_NIC_ADDR, NIC_SRAM_STATUS_BLK);
10403 /* Clear statistics and status block memory areas */
10404 for (i = NIC_SRAM_STATS_BLK;
10405 i < NIC_SRAM_STATUS_BLK + TG3_HW_STATUS_SIZE;
10406 i += sizeof(u32)) {
10407 tg3_write_mem(tp, i, 0);
10412 tw32(HOSTCC_MODE, HOSTCC_MODE_ENABLE | tp->coalesce_mode);
10414 tw32(RCVCC_MODE, RCVCC_MODE_ENABLE | RCVCC_MODE_ATTN_ENABLE);
10415 tw32(RCVLPC_MODE, RCVLPC_MODE_ENABLE);
10416 if (!tg3_flag(tp, 5705_PLUS))
10417 tw32(RCVLSC_MODE, RCVLSC_MODE_ENABLE | RCVLSC_MODE_ATTN_ENABLE);
10419 if (tp->phy_flags & TG3_PHYFLG_MII_SERDES) {
10420 tp->phy_flags &= ~TG3_PHYFLG_PARALLEL_DETECT;
10421 /* reset to prevent losing 1st rx packet intermittently */
10422 tw32_f(MAC_RX_MODE, RX_MODE_RESET);
10426 tp->mac_mode |= MAC_MODE_TXSTAT_ENABLE | MAC_MODE_RXSTAT_ENABLE |
10427 MAC_MODE_TDE_ENABLE | MAC_MODE_RDE_ENABLE |
10428 MAC_MODE_FHDE_ENABLE;
10429 if (tg3_flag(tp, ENABLE_APE))
10430 tp->mac_mode |= MAC_MODE_APE_TX_EN | MAC_MODE_APE_RX_EN;
10431 if (!tg3_flag(tp, 5705_PLUS) &&
10432 !(tp->phy_flags & TG3_PHYFLG_PHY_SERDES) &&
10433 tg3_asic_rev(tp) != ASIC_REV_5700)
10434 tp->mac_mode |= MAC_MODE_LINK_POLARITY;
10435 tw32_f(MAC_MODE, tp->mac_mode | MAC_MODE_RXSTAT_CLEAR | MAC_MODE_TXSTAT_CLEAR);
10438 /* tp->grc_local_ctrl is partially set up during tg3_get_invariants().
10439 * If TG3_FLAG_IS_NIC is zero, we should read the
10440 * register to preserve the GPIO settings for LOMs. The GPIOs,
10441 * whether used as inputs or outputs, are set by boot code after
10444 if (!tg3_flag(tp, IS_NIC)) {
10447 gpio_mask = GRC_LCLCTRL_GPIO_OE0 | GRC_LCLCTRL_GPIO_OE1 |
10448 GRC_LCLCTRL_GPIO_OE2 | GRC_LCLCTRL_GPIO_OUTPUT0 |
10449 GRC_LCLCTRL_GPIO_OUTPUT1 | GRC_LCLCTRL_GPIO_OUTPUT2;
10451 if (tg3_asic_rev(tp) == ASIC_REV_5752)
10452 gpio_mask |= GRC_LCLCTRL_GPIO_OE3 |
10453 GRC_LCLCTRL_GPIO_OUTPUT3;
10455 if (tg3_asic_rev(tp) == ASIC_REV_5755)
10456 gpio_mask |= GRC_LCLCTRL_GPIO_UART_SEL;
10458 tp->grc_local_ctrl &= ~gpio_mask;
10459 tp->grc_local_ctrl |= tr32(GRC_LOCAL_CTRL) & gpio_mask;
10461 /* GPIO1 must be driven high for eeprom write protect */
10462 if (tg3_flag(tp, EEPROM_WRITE_PROT))
10463 tp->grc_local_ctrl |= (GRC_LCLCTRL_GPIO_OE1 |
10464 GRC_LCLCTRL_GPIO_OUTPUT1);
10466 tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl);
10469 if (tg3_flag(tp, USING_MSIX)) {
10470 val = tr32(MSGINT_MODE);
10471 val |= MSGINT_MODE_ENABLE;
10472 if (tp->irq_cnt > 1)
10473 val |= MSGINT_MODE_MULTIVEC_EN;
10474 if (!tg3_flag(tp, 1SHOT_MSI))
10475 val |= MSGINT_MODE_ONE_SHOT_DISABLE;
10476 tw32(MSGINT_MODE, val);
10479 if (!tg3_flag(tp, 5705_PLUS)) {
10480 tw32_f(DMAC_MODE, DMAC_MODE_ENABLE);
10484 val = (WDMAC_MODE_ENABLE | WDMAC_MODE_TGTABORT_ENAB |
10485 WDMAC_MODE_MSTABORT_ENAB | WDMAC_MODE_PARITYERR_ENAB |
10486 WDMAC_MODE_ADDROFLOW_ENAB | WDMAC_MODE_FIFOOFLOW_ENAB |
10487 WDMAC_MODE_FIFOURUN_ENAB | WDMAC_MODE_FIFOOREAD_ENAB |
10488 WDMAC_MODE_LNGREAD_ENAB);
10490 if (tg3_asic_rev(tp) == ASIC_REV_5705 &&
10491 tg3_chip_rev_id(tp) != CHIPREV_ID_5705_A0) {
10492 if (tg3_flag(tp, TSO_CAPABLE) &&
10493 (tg3_chip_rev_id(tp) == CHIPREV_ID_5705_A1 ||
10494 tg3_chip_rev_id(tp) == CHIPREV_ID_5705_A2)) {
10496 } else if (!(tr32(TG3PCI_PCISTATE) & PCISTATE_BUS_SPEED_HIGH) &&
10497 !tg3_flag(tp, IS_5788)) {
10498 val |= WDMAC_MODE_RX_ACCEL;
10502 /* Enable host coalescing bug fix */
10503 if (tg3_flag(tp, 5755_PLUS))
10504 val |= WDMAC_MODE_STATUS_TAG_FIX;
10506 if (tg3_asic_rev(tp) == ASIC_REV_5785)
10507 val |= WDMAC_MODE_BURST_ALL_DATA;
10509 tw32_f(WDMAC_MODE, val);
10512 if (tg3_flag(tp, PCIX_MODE)) {
10515 pci_read_config_word(tp->pdev, tp->pcix_cap + PCI_X_CMD,
10517 if (tg3_asic_rev(tp) == ASIC_REV_5703) {
10518 pcix_cmd &= ~PCI_X_CMD_MAX_READ;
10519 pcix_cmd |= PCI_X_CMD_READ_2K;
10520 } else if (tg3_asic_rev(tp) == ASIC_REV_5704) {
10521 pcix_cmd &= ~(PCI_X_CMD_MAX_SPLIT | PCI_X_CMD_MAX_READ);
10522 pcix_cmd |= PCI_X_CMD_READ_2K;
10524 pci_write_config_word(tp->pdev, tp->pcix_cap + PCI_X_CMD,
10528 tw32_f(RDMAC_MODE, rdmac_mode);
10531 if (tg3_asic_rev(tp) == ASIC_REV_5719 ||
10532 tg3_asic_rev(tp) == ASIC_REV_5720) {
10533 for (i = 0; i < TG3_NUM_RDMA_CHANNELS; i++) {
10534 if (tr32(TG3_RDMA_LENGTH + (i << 2)) > TG3_MAX_MTU(tp))
10537 if (i < TG3_NUM_RDMA_CHANNELS) {
10538 val = tr32(TG3_LSO_RD_DMA_CRPTEN_CTRL);
10539 val |= tg3_lso_rd_dma_workaround_bit(tp);
10540 tw32(TG3_LSO_RD_DMA_CRPTEN_CTRL, val);
10541 tg3_flag_set(tp, 5719_5720_RDMA_BUG);
10545 tw32(RCVDCC_MODE, RCVDCC_MODE_ENABLE | RCVDCC_MODE_ATTN_ENABLE);
10546 if (!tg3_flag(tp, 5705_PLUS))
10547 tw32(MBFREE_MODE, MBFREE_MODE_ENABLE);
10549 if (tg3_asic_rev(tp) == ASIC_REV_5761)
10550 tw32(SNDDATAC_MODE,
10551 SNDDATAC_MODE_ENABLE | SNDDATAC_MODE_CDELAY);
10553 tw32(SNDDATAC_MODE, SNDDATAC_MODE_ENABLE);
10555 tw32(SNDBDC_MODE, SNDBDC_MODE_ENABLE | SNDBDC_MODE_ATTN_ENABLE);
10556 tw32(RCVBDI_MODE, RCVBDI_MODE_ENABLE | RCVBDI_MODE_RCB_ATTN_ENAB);
10557 val = RCVDBDI_MODE_ENABLE | RCVDBDI_MODE_INV_RING_SZ;
10558 if (tg3_flag(tp, LRG_PROD_RING_CAP))
10559 val |= RCVDBDI_MODE_LRG_RING_SZ;
10560 tw32(RCVDBDI_MODE, val);
10561 tw32(SNDDATAI_MODE, SNDDATAI_MODE_ENABLE);
10562 if (tg3_flag(tp, HW_TSO_1) ||
10563 tg3_flag(tp, HW_TSO_2) ||
10564 tg3_flag(tp, HW_TSO_3))
10565 tw32(SNDDATAI_MODE, SNDDATAI_MODE_ENABLE | 0x8);
10566 val = SNDBDI_MODE_ENABLE | SNDBDI_MODE_ATTN_ENABLE;
10567 if (tg3_flag(tp, ENABLE_TSS))
10568 val |= SNDBDI_MODE_MULTI_TXQ_EN;
10569 tw32(SNDBDI_MODE, val);
10570 tw32(SNDBDS_MODE, SNDBDS_MODE_ENABLE | SNDBDS_MODE_ATTN_ENABLE);
10572 if (tg3_chip_rev_id(tp) == CHIPREV_ID_5701_A0) {
10573 err = tg3_load_5701_a0_firmware_fix(tp);
10578 if (tg3_asic_rev(tp) == ASIC_REV_57766) {
10579 /* Ignore any errors for the firmware download. If download
10580 * fails, the device will operate with EEE disabled
10582 tg3_load_57766_firmware(tp);
10585 if (tg3_flag(tp, TSO_CAPABLE)) {
10586 err = tg3_load_tso_firmware(tp);
10591 tp->tx_mode = TX_MODE_ENABLE;
10593 if (tg3_flag(tp, 5755_PLUS) ||
10594 tg3_asic_rev(tp) == ASIC_REV_5906)
10595 tp->tx_mode |= TX_MODE_MBUF_LOCKUP_FIX;
10597 if (tg3_asic_rev(tp) == ASIC_REV_5720 ||
10598 tg3_asic_rev(tp) == ASIC_REV_5762) {
10599 val = TX_MODE_JMB_FRM_LEN | TX_MODE_CNT_DN_MODE;
10600 tp->tx_mode &= ~val;
10601 tp->tx_mode |= tr32(MAC_TX_MODE) & val;
10604 tw32_f(MAC_TX_MODE, tp->tx_mode);
10607 if (tg3_flag(tp, ENABLE_RSS)) {
10610 tg3_rss_write_indir_tbl(tp);
10612 netdev_rss_key_fill(rss_key, 10 * sizeof(u32));
10614 for (i = 0; i < 10 ; i++)
10615 tw32(MAC_RSS_HASH_KEY_0 + i*4, rss_key[i]);
10618 tp->rx_mode = RX_MODE_ENABLE;
10619 if (tg3_flag(tp, 5755_PLUS))
10620 tp->rx_mode |= RX_MODE_IPV6_CSUM_ENABLE;
10622 if (tg3_asic_rev(tp) == ASIC_REV_5762)
10623 tp->rx_mode |= RX_MODE_IPV4_FRAG_FIX;
10625 if (tg3_flag(tp, ENABLE_RSS))
10626 tp->rx_mode |= RX_MODE_RSS_ENABLE |
10627 RX_MODE_RSS_ITBL_HASH_BITS_7 |
10628 RX_MODE_RSS_IPV6_HASH_EN |
10629 RX_MODE_RSS_TCP_IPV6_HASH_EN |
10630 RX_MODE_RSS_IPV4_HASH_EN |
10631 RX_MODE_RSS_TCP_IPV4_HASH_EN;
10633 tw32_f(MAC_RX_MODE, tp->rx_mode);
10636 tw32(MAC_LED_CTRL, tp->led_ctrl);
10638 tw32(MAC_MI_STAT, MAC_MI_STAT_LNKSTAT_ATTN_ENAB);
10639 if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES) {
10640 tw32_f(MAC_RX_MODE, RX_MODE_RESET);
10643 tw32_f(MAC_RX_MODE, tp->rx_mode);
10646 if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES) {
10647 if ((tg3_asic_rev(tp) == ASIC_REV_5704) &&
10648 !(tp->phy_flags & TG3_PHYFLG_SERDES_PREEMPHASIS)) {
10649 /* Set drive transmission level to 1.2V */
10650 /* only if the signal pre-emphasis bit is not set */
10651 val = tr32(MAC_SERDES_CFG);
10654 tw32(MAC_SERDES_CFG, val);
10656 if (tg3_chip_rev_id(tp) == CHIPREV_ID_5703_A1)
10657 tw32(MAC_SERDES_CFG, 0x616000);
10660 /* Prevent chip from dropping frames when flow control
10663 if (tg3_flag(tp, 57765_CLASS))
10667 tw32_f(MAC_LOW_WMARK_MAX_RX_FRAME, val);
10669 if (tg3_asic_rev(tp) == ASIC_REV_5704 &&
10670 (tp->phy_flags & TG3_PHYFLG_PHY_SERDES)) {
10671 /* Use hardware link auto-negotiation */
10672 tg3_flag_set(tp, HW_AUTONEG);
10675 if ((tp->phy_flags & TG3_PHYFLG_MII_SERDES) &&
10676 tg3_asic_rev(tp) == ASIC_REV_5714) {
10679 tmp = tr32(SERDES_RX_CTRL);
10680 tw32(SERDES_RX_CTRL, tmp | SERDES_RX_SIG_DETECT);
10681 tp->grc_local_ctrl &= ~GRC_LCLCTRL_USE_EXT_SIG_DETECT;
10682 tp->grc_local_ctrl |= GRC_LCLCTRL_USE_SIG_DETECT;
10683 tw32(GRC_LOCAL_CTRL, tp->grc_local_ctrl);
10686 if (!tg3_flag(tp, USE_PHYLIB)) {
10687 if (tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER)
10688 tp->phy_flags &= ~TG3_PHYFLG_IS_LOW_POWER;
10690 err = tg3_setup_phy(tp, false);
10694 if (!(tp->phy_flags & TG3_PHYFLG_PHY_SERDES) &&
10695 !(tp->phy_flags & TG3_PHYFLG_IS_FET)) {
10698 /* Clear CRC stats. */
10699 if (!tg3_readphy(tp, MII_TG3_TEST1, &tmp)) {
10700 tg3_writephy(tp, MII_TG3_TEST1,
10701 tmp | MII_TG3_TEST1_CRC_EN);
10702 tg3_readphy(tp, MII_TG3_RXR_COUNTERS, &tmp);
10707 __tg3_set_rx_mode(tp->dev);
10709 /* Initialize receive rules. */
10710 tw32(MAC_RCV_RULE_0, 0xc2000000 & RCV_RULE_DISABLE_MASK);
10711 tw32(MAC_RCV_VALUE_0, 0xffffffff & RCV_RULE_DISABLE_MASK);
10712 tw32(MAC_RCV_RULE_1, 0x86000004 & RCV_RULE_DISABLE_MASK);
10713 tw32(MAC_RCV_VALUE_1, 0xffffffff & RCV_RULE_DISABLE_MASK);
10715 if (tg3_flag(tp, 5705_PLUS) && !tg3_flag(tp, 5780_CLASS))
10719 if (tg3_flag(tp, ENABLE_ASF))
10723 tw32(MAC_RCV_RULE_15, 0); tw32(MAC_RCV_VALUE_15, 0);
10726 tw32(MAC_RCV_RULE_14, 0); tw32(MAC_RCV_VALUE_14, 0);
10729 tw32(MAC_RCV_RULE_13, 0); tw32(MAC_RCV_VALUE_13, 0);
10732 tw32(MAC_RCV_RULE_12, 0); tw32(MAC_RCV_VALUE_12, 0);
10735 tw32(MAC_RCV_RULE_11, 0); tw32(MAC_RCV_VALUE_11, 0);
10738 tw32(MAC_RCV_RULE_10, 0); tw32(MAC_RCV_VALUE_10, 0);
10741 tw32(MAC_RCV_RULE_9, 0); tw32(MAC_RCV_VALUE_9, 0);
10744 tw32(MAC_RCV_RULE_8, 0); tw32(MAC_RCV_VALUE_8, 0);
10747 tw32(MAC_RCV_RULE_7, 0); tw32(MAC_RCV_VALUE_7, 0);
10750 tw32(MAC_RCV_RULE_6, 0); tw32(MAC_RCV_VALUE_6, 0);
10753 tw32(MAC_RCV_RULE_5, 0); tw32(MAC_RCV_VALUE_5, 0);
10756 tw32(MAC_RCV_RULE_4, 0); tw32(MAC_RCV_VALUE_4, 0);
10759 /* tw32(MAC_RCV_RULE_3, 0); tw32(MAC_RCV_VALUE_3, 0); */
10761 /* tw32(MAC_RCV_RULE_2, 0); tw32(MAC_RCV_VALUE_2, 0); */
10769 if (tg3_flag(tp, ENABLE_APE))
10770 /* Write our heartbeat update interval to APE. */
10771 tg3_ape_write32(tp, TG3_APE_HOST_HEARTBEAT_INT_MS,
10772 APE_HOST_HEARTBEAT_INT_5SEC);
10774 tg3_write_sig_post_reset(tp, RESET_KIND_INIT);
10779 /* Called at device open time to get the chip ready for
10780 * packet processing. Invoked with tp->lock held.
10782 static int tg3_init_hw(struct tg3 *tp, bool reset_phy)
10784 /* Chip may have been just powered on. If so, the boot code may still
10785 * be running initialization. Wait for it to finish to avoid races in
10786 * accessing the hardware.
10788 tg3_enable_register_access(tp);
10791 tg3_switch_clocks(tp);
10793 tw32(TG3PCI_MEM_WIN_BASE_ADDR, 0);
10795 return tg3_reset_hw(tp, reset_phy);
10798 #ifdef CONFIG_TIGON3_HWMON
10799 static void tg3_sd_scan_scratchpad(struct tg3 *tp, struct tg3_ocir *ocir)
10803 for (i = 0; i < TG3_SD_NUM_RECS; i++, ocir++) {
10804 u32 off = i * TG3_OCIR_LEN, len = TG3_OCIR_LEN;
10806 tg3_ape_scratchpad_read(tp, (u32 *) ocir, off, len);
10809 if (ocir->signature != TG3_OCIR_SIG_MAGIC ||
10810 !(ocir->version_flags & TG3_OCIR_FLAG_ACTIVE))
10811 memset(ocir, 0, TG3_OCIR_LEN);
10815 /* sysfs attributes for hwmon */
10816 static ssize_t tg3_show_temp(struct device *dev,
10817 struct device_attribute *devattr, char *buf)
10819 struct sensor_device_attribute *attr = to_sensor_dev_attr(devattr);
10820 struct tg3 *tp = dev_get_drvdata(dev);
10823 spin_lock_bh(&tp->lock);
10824 tg3_ape_scratchpad_read(tp, &temperature, attr->index,
10825 sizeof(temperature));
10826 spin_unlock_bh(&tp->lock);
10827 return sprintf(buf, "%u\n", temperature * 1000);
10831 static SENSOR_DEVICE_ATTR(temp1_input, 0444, tg3_show_temp, NULL,
10832 TG3_TEMP_SENSOR_OFFSET);
10833 static SENSOR_DEVICE_ATTR(temp1_crit, 0444, tg3_show_temp, NULL,
10834 TG3_TEMP_CAUTION_OFFSET);
10835 static SENSOR_DEVICE_ATTR(temp1_max, 0444, tg3_show_temp, NULL,
10836 TG3_TEMP_MAX_OFFSET);
10838 static struct attribute *tg3_attrs[] = {
10839 &sensor_dev_attr_temp1_input.dev_attr.attr,
10840 &sensor_dev_attr_temp1_crit.dev_attr.attr,
10841 &sensor_dev_attr_temp1_max.dev_attr.attr,
10844 ATTRIBUTE_GROUPS(tg3);
10846 static void tg3_hwmon_close(struct tg3 *tp)
10848 if (tp->hwmon_dev) {
10849 hwmon_device_unregister(tp->hwmon_dev);
10850 tp->hwmon_dev = NULL;
10854 static void tg3_hwmon_open(struct tg3 *tp)
10858 struct pci_dev *pdev = tp->pdev;
10859 struct tg3_ocir ocirs[TG3_SD_NUM_RECS];
10861 tg3_sd_scan_scratchpad(tp, ocirs);
10863 for (i = 0; i < TG3_SD_NUM_RECS; i++) {
10864 if (!ocirs[i].src_data_length)
10867 size += ocirs[i].src_hdr_length;
10868 size += ocirs[i].src_data_length;
10874 tp->hwmon_dev = hwmon_device_register_with_groups(&pdev->dev, "tg3",
10876 if (IS_ERR(tp->hwmon_dev)) {
10877 tp->hwmon_dev = NULL;
10878 dev_err(&pdev->dev, "Cannot register hwmon device, aborting\n");
10882 static inline void tg3_hwmon_close(struct tg3 *tp) { }
10883 static inline void tg3_hwmon_open(struct tg3 *tp) { }
10884 #endif /* CONFIG_TIGON3_HWMON */
10887 #define TG3_STAT_ADD32(PSTAT, REG) \
10888 do { u32 __val = tr32(REG); \
10889 (PSTAT)->low += __val; \
10890 if ((PSTAT)->low < __val) \
10891 (PSTAT)->high += 1; \
10894 static void tg3_periodic_fetch_stats(struct tg3 *tp)
10896 struct tg3_hw_stats *sp = tp->hw_stats;
10901 TG3_STAT_ADD32(&sp->tx_octets, MAC_TX_STATS_OCTETS);
10902 TG3_STAT_ADD32(&sp->tx_collisions, MAC_TX_STATS_COLLISIONS);
10903 TG3_STAT_ADD32(&sp->tx_xon_sent, MAC_TX_STATS_XON_SENT);
10904 TG3_STAT_ADD32(&sp->tx_xoff_sent, MAC_TX_STATS_XOFF_SENT);
10905 TG3_STAT_ADD32(&sp->tx_mac_errors, MAC_TX_STATS_MAC_ERRORS);
10906 TG3_STAT_ADD32(&sp->tx_single_collisions, MAC_TX_STATS_SINGLE_COLLISIONS);
10907 TG3_STAT_ADD32(&sp->tx_mult_collisions, MAC_TX_STATS_MULT_COLLISIONS);
10908 TG3_STAT_ADD32(&sp->tx_deferred, MAC_TX_STATS_DEFERRED);
10909 TG3_STAT_ADD32(&sp->tx_excessive_collisions, MAC_TX_STATS_EXCESSIVE_COL);
10910 TG3_STAT_ADD32(&sp->tx_late_collisions, MAC_TX_STATS_LATE_COL);
10911 TG3_STAT_ADD32(&sp->tx_ucast_packets, MAC_TX_STATS_UCAST);
10912 TG3_STAT_ADD32(&sp->tx_mcast_packets, MAC_TX_STATS_MCAST);
10913 TG3_STAT_ADD32(&sp->tx_bcast_packets, MAC_TX_STATS_BCAST);
10914 if (unlikely(tg3_flag(tp, 5719_5720_RDMA_BUG) &&
10915 (sp->tx_ucast_packets.low + sp->tx_mcast_packets.low +
10916 sp->tx_bcast_packets.low) > TG3_NUM_RDMA_CHANNELS)) {
10919 val = tr32(TG3_LSO_RD_DMA_CRPTEN_CTRL);
10920 val &= ~tg3_lso_rd_dma_workaround_bit(tp);
10921 tw32(TG3_LSO_RD_DMA_CRPTEN_CTRL, val);
10922 tg3_flag_clear(tp, 5719_5720_RDMA_BUG);
10925 TG3_STAT_ADD32(&sp->rx_octets, MAC_RX_STATS_OCTETS);
10926 TG3_STAT_ADD32(&sp->rx_fragments, MAC_RX_STATS_FRAGMENTS);
10927 TG3_STAT_ADD32(&sp->rx_ucast_packets, MAC_RX_STATS_UCAST);
10928 TG3_STAT_ADD32(&sp->rx_mcast_packets, MAC_RX_STATS_MCAST);
10929 TG3_STAT_ADD32(&sp->rx_bcast_packets, MAC_RX_STATS_BCAST);
10930 TG3_STAT_ADD32(&sp->rx_fcs_errors, MAC_RX_STATS_FCS_ERRORS);
10931 TG3_STAT_ADD32(&sp->rx_align_errors, MAC_RX_STATS_ALIGN_ERRORS);
10932 TG3_STAT_ADD32(&sp->rx_xon_pause_rcvd, MAC_RX_STATS_XON_PAUSE_RECVD);
10933 TG3_STAT_ADD32(&sp->rx_xoff_pause_rcvd, MAC_RX_STATS_XOFF_PAUSE_RECVD);
10934 TG3_STAT_ADD32(&sp->rx_mac_ctrl_rcvd, MAC_RX_STATS_MAC_CTRL_RECVD);
10935 TG3_STAT_ADD32(&sp->rx_xoff_entered, MAC_RX_STATS_XOFF_ENTERED);
10936 TG3_STAT_ADD32(&sp->rx_frame_too_long_errors, MAC_RX_STATS_FRAME_TOO_LONG);
10937 TG3_STAT_ADD32(&sp->rx_jabbers, MAC_RX_STATS_JABBERS);
10938 TG3_STAT_ADD32(&sp->rx_undersize_packets, MAC_RX_STATS_UNDERSIZE);
10940 TG3_STAT_ADD32(&sp->rxbds_empty, RCVLPC_NO_RCV_BD_CNT);
10941 if (tg3_asic_rev(tp) != ASIC_REV_5717 &&
10942 tg3_asic_rev(tp) != ASIC_REV_5762 &&
10943 tg3_chip_rev_id(tp) != CHIPREV_ID_5719_A0 &&
10944 tg3_chip_rev_id(tp) != CHIPREV_ID_5720_A0) {
10945 TG3_STAT_ADD32(&sp->rx_discards, RCVLPC_IN_DISCARDS_CNT);
10947 u32 val = tr32(HOSTCC_FLOW_ATTN);
10948 val = (val & HOSTCC_FLOW_ATTN_MBUF_LWM) ? 1 : 0;
10950 tw32(HOSTCC_FLOW_ATTN, HOSTCC_FLOW_ATTN_MBUF_LWM);
10951 sp->rx_discards.low += val;
10952 if (sp->rx_discards.low < val)
10953 sp->rx_discards.high += 1;
10955 sp->mbuf_lwm_thresh_hit = sp->rx_discards;
10957 TG3_STAT_ADD32(&sp->rx_errors, RCVLPC_IN_ERRORS_CNT);
10960 static void tg3_chk_missed_msi(struct tg3 *tp)
10964 for (i = 0; i < tp->irq_cnt; i++) {
10965 struct tg3_napi *tnapi = &tp->napi[i];
10967 if (tg3_has_work(tnapi)) {
10968 if (tnapi->last_rx_cons == tnapi->rx_rcb_ptr &&
10969 tnapi->last_tx_cons == tnapi->tx_cons) {
10970 if (tnapi->chk_msi_cnt < 1) {
10971 tnapi->chk_msi_cnt++;
10977 tnapi->chk_msi_cnt = 0;
10978 tnapi->last_rx_cons = tnapi->rx_rcb_ptr;
10979 tnapi->last_tx_cons = tnapi->tx_cons;
10983 static void tg3_timer(struct timer_list *t)
10985 struct tg3 *tp = from_timer(tp, t, timer);
10987 spin_lock(&tp->lock);
10989 if (tp->irq_sync || tg3_flag(tp, RESET_TASK_PENDING)) {
10990 spin_unlock(&tp->lock);
10991 goto restart_timer;
10994 if (tg3_asic_rev(tp) == ASIC_REV_5717 ||
10995 tg3_flag(tp, 57765_CLASS))
10996 tg3_chk_missed_msi(tp);
10998 if (tg3_flag(tp, FLUSH_POSTED_WRITES)) {
10999 /* BCM4785: Flush posted writes from GbE to host memory. */
11003 if (!tg3_flag(tp, TAGGED_STATUS)) {
11004 /* All of this garbage is because when using non-tagged
11005 * IRQ status the mailbox/status_block protocol the chip
11006 * uses with the cpu is race prone.
11008 if (tp->napi[0].hw_status->status & SD_STATUS_UPDATED) {
11009 tw32(GRC_LOCAL_CTRL,
11010 tp->grc_local_ctrl | GRC_LCLCTRL_SETINT);
11012 tw32(HOSTCC_MODE, tp->coalesce_mode |
11013 HOSTCC_MODE_ENABLE | HOSTCC_MODE_NOW);
11016 if (!(tr32(WDMAC_MODE) & WDMAC_MODE_ENABLE)) {
11017 spin_unlock(&tp->lock);
11018 tg3_reset_task_schedule(tp);
11019 goto restart_timer;
11023 /* This part only runs once per second. */
11024 if (!--tp->timer_counter) {
11025 if (tg3_flag(tp, 5705_PLUS))
11026 tg3_periodic_fetch_stats(tp);
11028 if (tp->setlpicnt && !--tp->setlpicnt)
11029 tg3_phy_eee_enable(tp);
11031 if (tg3_flag(tp, USE_LINKCHG_REG)) {
11035 mac_stat = tr32(MAC_STATUS);
11038 if (tp->phy_flags & TG3_PHYFLG_USE_MI_INTERRUPT) {
11039 if (mac_stat & MAC_STATUS_MI_INTERRUPT)
11041 } else if (mac_stat & MAC_STATUS_LNKSTATE_CHANGED)
11045 tg3_setup_phy(tp, false);
11046 } else if (tg3_flag(tp, POLL_SERDES)) {
11047 u32 mac_stat = tr32(MAC_STATUS);
11048 int need_setup = 0;
11051 (mac_stat & MAC_STATUS_LNKSTATE_CHANGED)) {
11054 if (!tp->link_up &&
11055 (mac_stat & (MAC_STATUS_PCS_SYNCED |
11056 MAC_STATUS_SIGNAL_DET))) {
11060 if (!tp->serdes_counter) {
11063 ~MAC_MODE_PORT_MODE_MASK));
11065 tw32_f(MAC_MODE, tp->mac_mode);
11068 tg3_setup_phy(tp, false);
11070 } else if ((tp->phy_flags & TG3_PHYFLG_MII_SERDES) &&
11071 tg3_flag(tp, 5780_CLASS)) {
11072 tg3_serdes_parallel_detect(tp);
11073 } else if (tg3_flag(tp, POLL_CPMU_LINK)) {
11074 u32 cpmu = tr32(TG3_CPMU_STATUS);
11075 bool link_up = !((cpmu & TG3_CPMU_STATUS_LINK_MASK) ==
11076 TG3_CPMU_STATUS_LINK_MASK);
11078 if (link_up != tp->link_up)
11079 tg3_setup_phy(tp, false);
11082 tp->timer_counter = tp->timer_multiplier;
11085 /* Heartbeat is only sent once every 2 seconds.
11087 * The heartbeat is to tell the ASF firmware that the host
11088 * driver is still alive. In the event that the OS crashes,
11089 * ASF needs to reset the hardware to free up the FIFO space
11090 * that may be filled with rx packets destined for the host.
11091 * If the FIFO is full, ASF will no longer function properly.
11093 * Unintended resets have been reported on real time kernels
11094 * where the timer doesn't run on time. Netpoll will also have
11097 * The new FWCMD_NICDRV_ALIVE3 command tells the ASF firmware
11098 * to check the ring condition when the heartbeat is expiring
11099 * before doing the reset. This will prevent most unintended
11102 if (!--tp->asf_counter) {
11103 if (tg3_flag(tp, ENABLE_ASF) && !tg3_flag(tp, ENABLE_APE)) {
11104 tg3_wait_for_event_ack(tp);
11106 tg3_write_mem(tp, NIC_SRAM_FW_CMD_MBOX,
11107 FWCMD_NICDRV_ALIVE3);
11108 tg3_write_mem(tp, NIC_SRAM_FW_CMD_LEN_MBOX, 4);
11109 tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX,
11110 TG3_FW_UPDATE_TIMEOUT_SEC);
11112 tg3_generate_fw_event(tp);
11114 tp->asf_counter = tp->asf_multiplier;
11117 /* Update the APE heartbeat every 5 seconds.*/
11118 tg3_send_ape_heartbeat(tp, TG3_APE_HB_INTERVAL);
11120 spin_unlock(&tp->lock);
11123 tp->timer.expires = jiffies + tp->timer_offset;
11124 add_timer(&tp->timer);
11127 static void tg3_timer_init(struct tg3 *tp)
11129 if (tg3_flag(tp, TAGGED_STATUS) &&
11130 tg3_asic_rev(tp) != ASIC_REV_5717 &&
11131 !tg3_flag(tp, 57765_CLASS))
11132 tp->timer_offset = HZ;
11134 tp->timer_offset = HZ / 10;
11136 BUG_ON(tp->timer_offset > HZ);
11138 tp->timer_multiplier = (HZ / tp->timer_offset);
11139 tp->asf_multiplier = (HZ / tp->timer_offset) *
11140 TG3_FW_UPDATE_FREQ_SEC;
11142 timer_setup(&tp->timer, tg3_timer, 0);
11145 static void tg3_timer_start(struct tg3 *tp)
11147 tp->asf_counter = tp->asf_multiplier;
11148 tp->timer_counter = tp->timer_multiplier;
11150 tp->timer.expires = jiffies + tp->timer_offset;
11151 add_timer(&tp->timer);
11154 static void tg3_timer_stop(struct tg3 *tp)
11156 del_timer_sync(&tp->timer);
11159 /* Restart hardware after configuration changes, self-test, etc.
11160 * Invoked with tp->lock held.
11162 static int tg3_restart_hw(struct tg3 *tp, bool reset_phy)
11163 __releases(tp->lock)
11164 __acquires(tp->lock)
11168 err = tg3_init_hw(tp, reset_phy);
11170 netdev_err(tp->dev,
11171 "Failed to re-initialize device, aborting\n");
11172 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
11173 tg3_full_unlock(tp);
11174 tg3_timer_stop(tp);
11176 tg3_napi_enable(tp);
11177 dev_close(tp->dev);
11178 tg3_full_lock(tp, 0);
11183 static void tg3_reset_task(struct work_struct *work)
11185 struct tg3 *tp = container_of(work, struct tg3, reset_task);
11189 tg3_full_lock(tp, 0);
11191 if (!netif_running(tp->dev)) {
11192 tg3_flag_clear(tp, RESET_TASK_PENDING);
11193 tg3_full_unlock(tp);
11198 tg3_full_unlock(tp);
11202 tg3_netif_stop(tp);
11204 tg3_full_lock(tp, 1);
11206 if (tg3_flag(tp, TX_RECOVERY_PENDING)) {
11207 tp->write32_tx_mbox = tg3_write32_tx_mbox;
11208 tp->write32_rx_mbox = tg3_write_flush_reg32;
11209 tg3_flag_set(tp, MBOX_WRITE_REORDER);
11210 tg3_flag_clear(tp, TX_RECOVERY_PENDING);
11213 tg3_halt(tp, RESET_KIND_SHUTDOWN, 0);
11214 err = tg3_init_hw(tp, true);
11218 tg3_netif_start(tp);
11221 tg3_full_unlock(tp);
11226 tg3_flag_clear(tp, RESET_TASK_PENDING);
11230 static int tg3_request_irq(struct tg3 *tp, int irq_num)
11233 unsigned long flags;
11235 struct tg3_napi *tnapi = &tp->napi[irq_num];
11237 if (tp->irq_cnt == 1)
11238 name = tp->dev->name;
11240 name = &tnapi->irq_lbl[0];
11241 if (tnapi->tx_buffers && tnapi->rx_rcb)
11242 snprintf(name, IFNAMSIZ,
11243 "%s-txrx-%d", tp->dev->name, irq_num);
11244 else if (tnapi->tx_buffers)
11245 snprintf(name, IFNAMSIZ,
11246 "%s-tx-%d", tp->dev->name, irq_num);
11247 else if (tnapi->rx_rcb)
11248 snprintf(name, IFNAMSIZ,
11249 "%s-rx-%d", tp->dev->name, irq_num);
11251 snprintf(name, IFNAMSIZ,
11252 "%s-%d", tp->dev->name, irq_num);
11253 name[IFNAMSIZ-1] = 0;
11256 if (tg3_flag(tp, USING_MSI) || tg3_flag(tp, USING_MSIX)) {
11258 if (tg3_flag(tp, 1SHOT_MSI))
11259 fn = tg3_msi_1shot;
11262 fn = tg3_interrupt;
11263 if (tg3_flag(tp, TAGGED_STATUS))
11264 fn = tg3_interrupt_tagged;
11265 flags = IRQF_SHARED;
11268 return request_irq(tnapi->irq_vec, fn, flags, name, tnapi);
11271 static int tg3_test_interrupt(struct tg3 *tp)
11273 struct tg3_napi *tnapi = &tp->napi[0];
11274 struct net_device *dev = tp->dev;
11275 int err, i, intr_ok = 0;
11278 if (!netif_running(dev))
11281 tg3_disable_ints(tp);
11283 free_irq(tnapi->irq_vec, tnapi);
11286 * Turn off MSI one shot mode. Otherwise this test has no
11287 * observable way to know whether the interrupt was delivered.
11289 if (tg3_flag(tp, 57765_PLUS)) {
11290 val = tr32(MSGINT_MODE) | MSGINT_MODE_ONE_SHOT_DISABLE;
11291 tw32(MSGINT_MODE, val);
11294 err = request_irq(tnapi->irq_vec, tg3_test_isr,
11295 IRQF_SHARED, dev->name, tnapi);
11299 tnapi->hw_status->status &= ~SD_STATUS_UPDATED;
11300 tg3_enable_ints(tp);
11302 tw32_f(HOSTCC_MODE, tp->coalesce_mode | HOSTCC_MODE_ENABLE |
11305 for (i = 0; i < 5; i++) {
11306 u32 int_mbox, misc_host_ctrl;
11308 int_mbox = tr32_mailbox(tnapi->int_mbox);
11309 misc_host_ctrl = tr32(TG3PCI_MISC_HOST_CTRL);
11311 if ((int_mbox != 0) ||
11312 (misc_host_ctrl & MISC_HOST_CTRL_MASK_PCI_INT)) {
11317 if (tg3_flag(tp, 57765_PLUS) &&
11318 tnapi->hw_status->status_tag != tnapi->last_tag)
11319 tw32_mailbox_f(tnapi->int_mbox, tnapi->last_tag << 24);
11324 tg3_disable_ints(tp);
11326 free_irq(tnapi->irq_vec, tnapi);
11328 err = tg3_request_irq(tp, 0);
11334 /* Reenable MSI one shot mode. */
11335 if (tg3_flag(tp, 57765_PLUS) && tg3_flag(tp, 1SHOT_MSI)) {
11336 val = tr32(MSGINT_MODE) & ~MSGINT_MODE_ONE_SHOT_DISABLE;
11337 tw32(MSGINT_MODE, val);
11345 /* Returns 0 if MSI test succeeds or MSI test fails and INTx mode is
11346 * successfully restored
11348 static int tg3_test_msi(struct tg3 *tp)
11353 if (!tg3_flag(tp, USING_MSI))
11356 /* Turn off SERR reporting in case MSI terminates with Master
11359 pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd);
11360 pci_write_config_word(tp->pdev, PCI_COMMAND,
11361 pci_cmd & ~PCI_COMMAND_SERR);
11363 err = tg3_test_interrupt(tp);
11365 pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd);
11370 /* other failures */
11374 /* MSI test failed, go back to INTx mode */
11375 netdev_warn(tp->dev, "No interrupt was generated using MSI. Switching "
11376 "to INTx mode. Please report this failure to the PCI "
11377 "maintainer and include system chipset information\n");
11379 free_irq(tp->napi[0].irq_vec, &tp->napi[0]);
11381 pci_disable_msi(tp->pdev);
11383 tg3_flag_clear(tp, USING_MSI);
11384 tp->napi[0].irq_vec = tp->pdev->irq;
11386 err = tg3_request_irq(tp, 0);
11390 /* Need to reset the chip because the MSI cycle may have terminated
11391 * with Master Abort.
11393 tg3_full_lock(tp, 1);
11395 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
11396 err = tg3_init_hw(tp, true);
11398 tg3_full_unlock(tp);
11401 free_irq(tp->napi[0].irq_vec, &tp->napi[0]);
11406 static int tg3_request_firmware(struct tg3 *tp)
11408 const struct tg3_firmware_hdr *fw_hdr;
11410 if (request_firmware(&tp->fw, tp->fw_needed, &tp->pdev->dev)) {
11411 netdev_err(tp->dev, "Failed to load firmware \"%s\"\n",
11416 fw_hdr = (struct tg3_firmware_hdr *)tp->fw->data;
11418 /* Firmware blob starts with version numbers, followed by
11419 * start address and _full_ length including BSS sections
11420 * (which must be longer than the actual data, of course
11423 tp->fw_len = be32_to_cpu(fw_hdr->len); /* includes bss */
11424 if (tp->fw_len < (tp->fw->size - TG3_FW_HDR_LEN)) {
11425 netdev_err(tp->dev, "bogus length %d in \"%s\"\n",
11426 tp->fw_len, tp->fw_needed);
11427 release_firmware(tp->fw);
11432 /* We no longer need firmware; we have it. */
11433 tp->fw_needed = NULL;
11437 static u32 tg3_irq_count(struct tg3 *tp)
11439 u32 irq_cnt = max(tp->rxq_cnt, tp->txq_cnt);
11442 /* We want as many rx rings enabled as there are cpus.
11443 * In multiqueue MSI-X mode, the first MSI-X vector
11444 * only deals with link interrupts, etc, so we add
11445 * one to the number of vectors we are requesting.
11447 irq_cnt = min_t(unsigned, irq_cnt + 1, tp->irq_max);
11453 static bool tg3_enable_msix(struct tg3 *tp)
11456 struct msix_entry msix_ent[TG3_IRQ_MAX_VECS];
11458 tp->txq_cnt = tp->txq_req;
11459 tp->rxq_cnt = tp->rxq_req;
11461 tp->rxq_cnt = netif_get_num_default_rss_queues();
11462 if (tp->rxq_cnt > tp->rxq_max)
11463 tp->rxq_cnt = tp->rxq_max;
11465 /* Disable multiple TX rings by default. Simple round-robin hardware
11466 * scheduling of the TX rings can cause starvation of rings with
11467 * small packets when other rings have TSO or jumbo packets.
11472 tp->irq_cnt = tg3_irq_count(tp);
11474 for (i = 0; i < tp->irq_max; i++) {
11475 msix_ent[i].entry = i;
11476 msix_ent[i].vector = 0;
11479 rc = pci_enable_msix_range(tp->pdev, msix_ent, 1, tp->irq_cnt);
11482 } else if (rc < tp->irq_cnt) {
11483 netdev_notice(tp->dev, "Requested %d MSI-X vectors, received %d\n",
11486 tp->rxq_cnt = max(rc - 1, 1);
11488 tp->txq_cnt = min(tp->rxq_cnt, tp->txq_max);
11491 for (i = 0; i < tp->irq_max; i++)
11492 tp->napi[i].irq_vec = msix_ent[i].vector;
11494 if (netif_set_real_num_rx_queues(tp->dev, tp->rxq_cnt)) {
11495 pci_disable_msix(tp->pdev);
11499 if (tp->irq_cnt == 1)
11502 tg3_flag_set(tp, ENABLE_RSS);
11504 if (tp->txq_cnt > 1)
11505 tg3_flag_set(tp, ENABLE_TSS);
11507 netif_set_real_num_tx_queues(tp->dev, tp->txq_cnt);
11512 static void tg3_ints_init(struct tg3 *tp)
11514 if ((tg3_flag(tp, SUPPORT_MSI) || tg3_flag(tp, SUPPORT_MSIX)) &&
11515 !tg3_flag(tp, TAGGED_STATUS)) {
11516 /* All MSI supporting chips should support tagged
11517 * status. Assert that this is the case.
11519 netdev_warn(tp->dev,
11520 "MSI without TAGGED_STATUS? Not using MSI\n");
11524 if (tg3_flag(tp, SUPPORT_MSIX) && tg3_enable_msix(tp))
11525 tg3_flag_set(tp, USING_MSIX);
11526 else if (tg3_flag(tp, SUPPORT_MSI) && pci_enable_msi(tp->pdev) == 0)
11527 tg3_flag_set(tp, USING_MSI);
11529 if (tg3_flag(tp, USING_MSI) || tg3_flag(tp, USING_MSIX)) {
11530 u32 msi_mode = tr32(MSGINT_MODE);
11531 if (tg3_flag(tp, USING_MSIX) && tp->irq_cnt > 1)
11532 msi_mode |= MSGINT_MODE_MULTIVEC_EN;
11533 if (!tg3_flag(tp, 1SHOT_MSI))
11534 msi_mode |= MSGINT_MODE_ONE_SHOT_DISABLE;
11535 tw32(MSGINT_MODE, msi_mode | MSGINT_MODE_ENABLE);
11538 if (!tg3_flag(tp, USING_MSIX)) {
11540 tp->napi[0].irq_vec = tp->pdev->irq;
11543 if (tp->irq_cnt == 1) {
11546 netif_set_real_num_tx_queues(tp->dev, 1);
11547 netif_set_real_num_rx_queues(tp->dev, 1);
11551 static void tg3_ints_fini(struct tg3 *tp)
11553 if (tg3_flag(tp, USING_MSIX))
11554 pci_disable_msix(tp->pdev);
11555 else if (tg3_flag(tp, USING_MSI))
11556 pci_disable_msi(tp->pdev);
11557 tg3_flag_clear(tp, USING_MSI);
11558 tg3_flag_clear(tp, USING_MSIX);
11559 tg3_flag_clear(tp, ENABLE_RSS);
11560 tg3_flag_clear(tp, ENABLE_TSS);
11563 static int tg3_start(struct tg3 *tp, bool reset_phy, bool test_irq,
11566 struct net_device *dev = tp->dev;
11570 * Setup interrupts first so we know how
11571 * many NAPI resources to allocate
11575 tg3_rss_check_indir_tbl(tp);
11577 /* The placement of this call is tied
11578 * to the setup and use of Host TX descriptors.
11580 err = tg3_alloc_consistent(tp);
11582 goto out_ints_fini;
11586 tg3_napi_enable(tp);
11588 for (i = 0; i < tp->irq_cnt; i++) {
11589 err = tg3_request_irq(tp, i);
11591 for (i--; i >= 0; i--) {
11592 struct tg3_napi *tnapi = &tp->napi[i];
11594 free_irq(tnapi->irq_vec, tnapi);
11596 goto out_napi_fini;
11600 tg3_full_lock(tp, 0);
11603 tg3_ape_driver_state_change(tp, RESET_KIND_INIT);
11605 err = tg3_init_hw(tp, reset_phy);
11607 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
11608 tg3_free_rings(tp);
11611 tg3_full_unlock(tp);
11616 if (test_irq && tg3_flag(tp, USING_MSI)) {
11617 err = tg3_test_msi(tp);
11620 tg3_full_lock(tp, 0);
11621 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
11622 tg3_free_rings(tp);
11623 tg3_full_unlock(tp);
11625 goto out_napi_fini;
11628 if (!tg3_flag(tp, 57765_PLUS) && tg3_flag(tp, USING_MSI)) {
11629 u32 val = tr32(PCIE_TRANSACTION_CFG);
11631 tw32(PCIE_TRANSACTION_CFG,
11632 val | PCIE_TRANS_CFG_1SHOT_MSI);
11638 tg3_hwmon_open(tp);
11640 tg3_full_lock(tp, 0);
11642 tg3_timer_start(tp);
11643 tg3_flag_set(tp, INIT_COMPLETE);
11644 tg3_enable_ints(tp);
11646 tg3_ptp_resume(tp);
11648 tg3_full_unlock(tp);
11650 netif_tx_start_all_queues(dev);
11653 * Reset loopback feature if it was turned on while the device was down
11654 * make sure that it's installed properly now.
11656 if (dev->features & NETIF_F_LOOPBACK)
11657 tg3_set_loopback(dev, dev->features);
11662 for (i = tp->irq_cnt - 1; i >= 0; i--) {
11663 struct tg3_napi *tnapi = &tp->napi[i];
11664 free_irq(tnapi->irq_vec, tnapi);
11668 tg3_napi_disable(tp);
11670 tg3_free_consistent(tp);
11678 static void tg3_stop(struct tg3 *tp)
11682 tg3_reset_task_cancel(tp);
11683 tg3_netif_stop(tp);
11685 tg3_timer_stop(tp);
11687 tg3_hwmon_close(tp);
11691 tg3_full_lock(tp, 1);
11693 tg3_disable_ints(tp);
11695 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
11696 tg3_free_rings(tp);
11697 tg3_flag_clear(tp, INIT_COMPLETE);
11699 tg3_full_unlock(tp);
11701 for (i = tp->irq_cnt - 1; i >= 0; i--) {
11702 struct tg3_napi *tnapi = &tp->napi[i];
11703 free_irq(tnapi->irq_vec, tnapi);
11710 tg3_free_consistent(tp);
11713 static int tg3_open(struct net_device *dev)
11715 struct tg3 *tp = netdev_priv(dev);
11718 if (tp->pcierr_recovery) {
11719 netdev_err(dev, "Failed to open device. PCI error recovery "
11724 if (tp->fw_needed) {
11725 err = tg3_request_firmware(tp);
11726 if (tg3_asic_rev(tp) == ASIC_REV_57766) {
11728 netdev_warn(tp->dev, "EEE capability disabled\n");
11729 tp->phy_flags &= ~TG3_PHYFLG_EEE_CAP;
11730 } else if (!(tp->phy_flags & TG3_PHYFLG_EEE_CAP)) {
11731 netdev_warn(tp->dev, "EEE capability restored\n");
11732 tp->phy_flags |= TG3_PHYFLG_EEE_CAP;
11734 } else if (tg3_chip_rev_id(tp) == CHIPREV_ID_5701_A0) {
11738 netdev_warn(tp->dev, "TSO capability disabled\n");
11739 tg3_flag_clear(tp, TSO_CAPABLE);
11740 } else if (!tg3_flag(tp, TSO_CAPABLE)) {
11741 netdev_notice(tp->dev, "TSO capability restored\n");
11742 tg3_flag_set(tp, TSO_CAPABLE);
11746 tg3_carrier_off(tp);
11748 err = tg3_power_up(tp);
11752 tg3_full_lock(tp, 0);
11754 tg3_disable_ints(tp);
11755 tg3_flag_clear(tp, INIT_COMPLETE);
11757 tg3_full_unlock(tp);
11759 err = tg3_start(tp,
11760 !(tp->phy_flags & TG3_PHYFLG_KEEP_LINK_ON_PWRDN),
11763 tg3_frob_aux_power(tp, false);
11764 pci_set_power_state(tp->pdev, PCI_D3hot);
11770 static int tg3_close(struct net_device *dev)
11772 struct tg3 *tp = netdev_priv(dev);
11774 if (tp->pcierr_recovery) {
11775 netdev_err(dev, "Failed to close device. PCI error recovery "
11782 if (pci_device_is_present(tp->pdev)) {
11783 tg3_power_down_prepare(tp);
11785 tg3_carrier_off(tp);
11790 static inline u64 get_stat64(tg3_stat64_t *val)
11792 return ((u64)val->high << 32) | ((u64)val->low);
11795 static u64 tg3_calc_crc_errors(struct tg3 *tp)
11797 struct tg3_hw_stats *hw_stats = tp->hw_stats;
11799 if (!(tp->phy_flags & TG3_PHYFLG_PHY_SERDES) &&
11800 (tg3_asic_rev(tp) == ASIC_REV_5700 ||
11801 tg3_asic_rev(tp) == ASIC_REV_5701)) {
11804 if (!tg3_readphy(tp, MII_TG3_TEST1, &val)) {
11805 tg3_writephy(tp, MII_TG3_TEST1,
11806 val | MII_TG3_TEST1_CRC_EN);
11807 tg3_readphy(tp, MII_TG3_RXR_COUNTERS, &val);
11811 tp->phy_crc_errors += val;
11813 return tp->phy_crc_errors;
11816 return get_stat64(&hw_stats->rx_fcs_errors);
11819 #define ESTAT_ADD(member) \
11820 estats->member = old_estats->member + \
11821 get_stat64(&hw_stats->member)
11823 static void tg3_get_estats(struct tg3 *tp, struct tg3_ethtool_stats *estats)
11825 struct tg3_ethtool_stats *old_estats = &tp->estats_prev;
11826 struct tg3_hw_stats *hw_stats = tp->hw_stats;
11828 ESTAT_ADD(rx_octets);
11829 ESTAT_ADD(rx_fragments);
11830 ESTAT_ADD(rx_ucast_packets);
11831 ESTAT_ADD(rx_mcast_packets);
11832 ESTAT_ADD(rx_bcast_packets);
11833 ESTAT_ADD(rx_fcs_errors);
11834 ESTAT_ADD(rx_align_errors);
11835 ESTAT_ADD(rx_xon_pause_rcvd);
11836 ESTAT_ADD(rx_xoff_pause_rcvd);
11837 ESTAT_ADD(rx_mac_ctrl_rcvd);
11838 ESTAT_ADD(rx_xoff_entered);
11839 ESTAT_ADD(rx_frame_too_long_errors);
11840 ESTAT_ADD(rx_jabbers);
11841 ESTAT_ADD(rx_undersize_packets);
11842 ESTAT_ADD(rx_in_length_errors);
11843 ESTAT_ADD(rx_out_length_errors);
11844 ESTAT_ADD(rx_64_or_less_octet_packets);
11845 ESTAT_ADD(rx_65_to_127_octet_packets);
11846 ESTAT_ADD(rx_128_to_255_octet_packets);
11847 ESTAT_ADD(rx_256_to_511_octet_packets);
11848 ESTAT_ADD(rx_512_to_1023_octet_packets);
11849 ESTAT_ADD(rx_1024_to_1522_octet_packets);
11850 ESTAT_ADD(rx_1523_to_2047_octet_packets);
11851 ESTAT_ADD(rx_2048_to_4095_octet_packets);
11852 ESTAT_ADD(rx_4096_to_8191_octet_packets);
11853 ESTAT_ADD(rx_8192_to_9022_octet_packets);
11855 ESTAT_ADD(tx_octets);
11856 ESTAT_ADD(tx_collisions);
11857 ESTAT_ADD(tx_xon_sent);
11858 ESTAT_ADD(tx_xoff_sent);
11859 ESTAT_ADD(tx_flow_control);
11860 ESTAT_ADD(tx_mac_errors);
11861 ESTAT_ADD(tx_single_collisions);
11862 ESTAT_ADD(tx_mult_collisions);
11863 ESTAT_ADD(tx_deferred);
11864 ESTAT_ADD(tx_excessive_collisions);
11865 ESTAT_ADD(tx_late_collisions);
11866 ESTAT_ADD(tx_collide_2times);
11867 ESTAT_ADD(tx_collide_3times);
11868 ESTAT_ADD(tx_collide_4times);
11869 ESTAT_ADD(tx_collide_5times);
11870 ESTAT_ADD(tx_collide_6times);
11871 ESTAT_ADD(tx_collide_7times);
11872 ESTAT_ADD(tx_collide_8times);
11873 ESTAT_ADD(tx_collide_9times);
11874 ESTAT_ADD(tx_collide_10times);
11875 ESTAT_ADD(tx_collide_11times);
11876 ESTAT_ADD(tx_collide_12times);
11877 ESTAT_ADD(tx_collide_13times);
11878 ESTAT_ADD(tx_collide_14times);
11879 ESTAT_ADD(tx_collide_15times);
11880 ESTAT_ADD(tx_ucast_packets);
11881 ESTAT_ADD(tx_mcast_packets);
11882 ESTAT_ADD(tx_bcast_packets);
11883 ESTAT_ADD(tx_carrier_sense_errors);
11884 ESTAT_ADD(tx_discards);
11885 ESTAT_ADD(tx_errors);
11887 ESTAT_ADD(dma_writeq_full);
11888 ESTAT_ADD(dma_write_prioq_full);
11889 ESTAT_ADD(rxbds_empty);
11890 ESTAT_ADD(rx_discards);
11891 ESTAT_ADD(rx_errors);
11892 ESTAT_ADD(rx_threshold_hit);
11894 ESTAT_ADD(dma_readq_full);
11895 ESTAT_ADD(dma_read_prioq_full);
11896 ESTAT_ADD(tx_comp_queue_full);
11898 ESTAT_ADD(ring_set_send_prod_index);
11899 ESTAT_ADD(ring_status_update);
11900 ESTAT_ADD(nic_irqs);
11901 ESTAT_ADD(nic_avoided_irqs);
11902 ESTAT_ADD(nic_tx_threshold_hit);
11904 ESTAT_ADD(mbuf_lwm_thresh_hit);
11907 static void tg3_get_nstats(struct tg3 *tp, struct rtnl_link_stats64 *stats)
11909 struct rtnl_link_stats64 *old_stats = &tp->net_stats_prev;
11910 struct tg3_hw_stats *hw_stats = tp->hw_stats;
11912 stats->rx_packets = old_stats->rx_packets +
11913 get_stat64(&hw_stats->rx_ucast_packets) +
11914 get_stat64(&hw_stats->rx_mcast_packets) +
11915 get_stat64(&hw_stats->rx_bcast_packets);
11917 stats->tx_packets = old_stats->tx_packets +
11918 get_stat64(&hw_stats->tx_ucast_packets) +
11919 get_stat64(&hw_stats->tx_mcast_packets) +
11920 get_stat64(&hw_stats->tx_bcast_packets);
11922 stats->rx_bytes = old_stats->rx_bytes +
11923 get_stat64(&hw_stats->rx_octets);
11924 stats->tx_bytes = old_stats->tx_bytes +
11925 get_stat64(&hw_stats->tx_octets);
11927 stats->rx_errors = old_stats->rx_errors +
11928 get_stat64(&hw_stats->rx_errors);
11929 stats->tx_errors = old_stats->tx_errors +
11930 get_stat64(&hw_stats->tx_errors) +
11931 get_stat64(&hw_stats->tx_mac_errors) +
11932 get_stat64(&hw_stats->tx_carrier_sense_errors) +
11933 get_stat64(&hw_stats->tx_discards);
11935 stats->multicast = old_stats->multicast +
11936 get_stat64(&hw_stats->rx_mcast_packets);
11937 stats->collisions = old_stats->collisions +
11938 get_stat64(&hw_stats->tx_collisions);
11940 stats->rx_length_errors = old_stats->rx_length_errors +
11941 get_stat64(&hw_stats->rx_frame_too_long_errors) +
11942 get_stat64(&hw_stats->rx_undersize_packets);
11944 stats->rx_frame_errors = old_stats->rx_frame_errors +
11945 get_stat64(&hw_stats->rx_align_errors);
11946 stats->tx_aborted_errors = old_stats->tx_aborted_errors +
11947 get_stat64(&hw_stats->tx_discards);
11948 stats->tx_carrier_errors = old_stats->tx_carrier_errors +
11949 get_stat64(&hw_stats->tx_carrier_sense_errors);
11951 stats->rx_crc_errors = old_stats->rx_crc_errors +
11952 tg3_calc_crc_errors(tp);
11954 stats->rx_missed_errors = old_stats->rx_missed_errors +
11955 get_stat64(&hw_stats->rx_discards);
11957 stats->rx_dropped = tp->rx_dropped;
11958 stats->tx_dropped = tp->tx_dropped;
11961 static int tg3_get_regs_len(struct net_device *dev)
11963 return TG3_REG_BLK_SIZE;
11966 static void tg3_get_regs(struct net_device *dev,
11967 struct ethtool_regs *regs, void *_p)
11969 struct tg3 *tp = netdev_priv(dev);
11973 memset(_p, 0, TG3_REG_BLK_SIZE);
11975 if (tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER)
11978 tg3_full_lock(tp, 0);
11980 tg3_dump_legacy_regs(tp, (u32 *)_p);
11982 tg3_full_unlock(tp);
11985 static int tg3_get_eeprom_len(struct net_device *dev)
11987 struct tg3 *tp = netdev_priv(dev);
11989 return tp->nvram_size;
11992 static int tg3_get_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom, u8 *data)
11994 struct tg3 *tp = netdev_priv(dev);
11995 int ret, cpmu_restore = 0;
11997 u32 i, offset, len, b_offset, b_count, cpmu_val = 0;
12000 if (tg3_flag(tp, NO_NVRAM))
12003 offset = eeprom->offset;
12007 eeprom->magic = TG3_EEPROM_MAGIC;
12009 /* Override clock, link aware and link idle modes */
12010 if (tg3_flag(tp, CPMU_PRESENT)) {
12011 cpmu_val = tr32(TG3_CPMU_CTRL);
12012 if (cpmu_val & (CPMU_CTRL_LINK_AWARE_MODE |
12013 CPMU_CTRL_LINK_IDLE_MODE)) {
12014 tw32(TG3_CPMU_CTRL, cpmu_val &
12015 ~(CPMU_CTRL_LINK_AWARE_MODE |
12016 CPMU_CTRL_LINK_IDLE_MODE));
12020 tg3_override_clk(tp);
12023 /* adjustments to start on required 4 byte boundary */
12024 b_offset = offset & 3;
12025 b_count = 4 - b_offset;
12026 if (b_count > len) {
12027 /* i.e. offset=1 len=2 */
12030 ret = tg3_nvram_read_be32(tp, offset-b_offset, &val);
12033 memcpy(data, ((char *)&val) + b_offset, b_count);
12036 eeprom->len += b_count;
12039 /* read bytes up to the last 4 byte boundary */
12040 pd = &data[eeprom->len];
12041 for (i = 0; i < (len - (len & 3)); i += 4) {
12042 ret = tg3_nvram_read_be32(tp, offset + i, &val);
12049 memcpy(pd + i, &val, 4);
12050 if (need_resched()) {
12051 if (signal_pending(current)) {
12062 /* read last bytes not ending on 4 byte boundary */
12063 pd = &data[eeprom->len];
12065 b_offset = offset + len - b_count;
12066 ret = tg3_nvram_read_be32(tp, b_offset, &val);
12069 memcpy(pd, &val, b_count);
12070 eeprom->len += b_count;
12075 /* Restore clock, link aware and link idle modes */
12076 tg3_restore_clk(tp);
12078 tw32(TG3_CPMU_CTRL, cpmu_val);
12083 static int tg3_set_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom, u8 *data)
12085 struct tg3 *tp = netdev_priv(dev);
12087 u32 offset, len, b_offset, odd_len;
12089 __be32 start = 0, end;
12091 if (tg3_flag(tp, NO_NVRAM) ||
12092 eeprom->magic != TG3_EEPROM_MAGIC)
12095 offset = eeprom->offset;
12098 if ((b_offset = (offset & 3))) {
12099 /* adjustments to start on required 4 byte boundary */
12100 ret = tg3_nvram_read_be32(tp, offset-b_offset, &start);
12111 /* adjustments to end on required 4 byte boundary */
12113 len = (len + 3) & ~3;
12114 ret = tg3_nvram_read_be32(tp, offset+len-4, &end);
12120 if (b_offset || odd_len) {
12121 buf = kmalloc(len, GFP_KERNEL);
12125 memcpy(buf, &start, 4);
12127 memcpy(buf+len-4, &end, 4);
12128 memcpy(buf + b_offset, data, eeprom->len);
12131 ret = tg3_nvram_write_block(tp, offset, len, buf);
12139 static int tg3_get_link_ksettings(struct net_device *dev,
12140 struct ethtool_link_ksettings *cmd)
12142 struct tg3 *tp = netdev_priv(dev);
12143 u32 supported, advertising;
12145 if (tg3_flag(tp, USE_PHYLIB)) {
12146 struct phy_device *phydev;
12147 if (!(tp->phy_flags & TG3_PHYFLG_IS_CONNECTED))
12149 phydev = mdiobus_get_phy(tp->mdio_bus, tp->phy_addr);
12150 phy_ethtool_ksettings_get(phydev, cmd);
12155 supported = (SUPPORTED_Autoneg);
12157 if (!(tp->phy_flags & TG3_PHYFLG_10_100_ONLY))
12158 supported |= (SUPPORTED_1000baseT_Half |
12159 SUPPORTED_1000baseT_Full);
12161 if (!(tp->phy_flags & TG3_PHYFLG_ANY_SERDES)) {
12162 supported |= (SUPPORTED_100baseT_Half |
12163 SUPPORTED_100baseT_Full |
12164 SUPPORTED_10baseT_Half |
12165 SUPPORTED_10baseT_Full |
12167 cmd->base.port = PORT_TP;
12169 supported |= SUPPORTED_FIBRE;
12170 cmd->base.port = PORT_FIBRE;
12172 ethtool_convert_legacy_u32_to_link_mode(cmd->link_modes.supported,
12175 advertising = tp->link_config.advertising;
12176 if (tg3_flag(tp, PAUSE_AUTONEG)) {
12177 if (tp->link_config.flowctrl & FLOW_CTRL_RX) {
12178 if (tp->link_config.flowctrl & FLOW_CTRL_TX) {
12179 advertising |= ADVERTISED_Pause;
12181 advertising |= ADVERTISED_Pause |
12182 ADVERTISED_Asym_Pause;
12184 } else if (tp->link_config.flowctrl & FLOW_CTRL_TX) {
12185 advertising |= ADVERTISED_Asym_Pause;
12188 ethtool_convert_legacy_u32_to_link_mode(cmd->link_modes.advertising,
12191 if (netif_running(dev) && tp->link_up) {
12192 cmd->base.speed = tp->link_config.active_speed;
12193 cmd->base.duplex = tp->link_config.active_duplex;
12194 ethtool_convert_legacy_u32_to_link_mode(
12195 cmd->link_modes.lp_advertising,
12196 tp->link_config.rmt_adv);
12198 if (!(tp->phy_flags & TG3_PHYFLG_ANY_SERDES)) {
12199 if (tp->phy_flags & TG3_PHYFLG_MDIX_STATE)
12200 cmd->base.eth_tp_mdix = ETH_TP_MDI_X;
12202 cmd->base.eth_tp_mdix = ETH_TP_MDI;
12205 cmd->base.speed = SPEED_UNKNOWN;
12206 cmd->base.duplex = DUPLEX_UNKNOWN;
12207 cmd->base.eth_tp_mdix = ETH_TP_MDI_INVALID;
12209 cmd->base.phy_address = tp->phy_addr;
12210 cmd->base.autoneg = tp->link_config.autoneg;
12214 static int tg3_set_link_ksettings(struct net_device *dev,
12215 const struct ethtool_link_ksettings *cmd)
12217 struct tg3 *tp = netdev_priv(dev);
12218 u32 speed = cmd->base.speed;
12221 if (tg3_flag(tp, USE_PHYLIB)) {
12222 struct phy_device *phydev;
12223 if (!(tp->phy_flags & TG3_PHYFLG_IS_CONNECTED))
12225 phydev = mdiobus_get_phy(tp->mdio_bus, tp->phy_addr);
12226 return phy_ethtool_ksettings_set(phydev, cmd);
12229 if (cmd->base.autoneg != AUTONEG_ENABLE &&
12230 cmd->base.autoneg != AUTONEG_DISABLE)
12233 if (cmd->base.autoneg == AUTONEG_DISABLE &&
12234 cmd->base.duplex != DUPLEX_FULL &&
12235 cmd->base.duplex != DUPLEX_HALF)
12238 ethtool_convert_link_mode_to_legacy_u32(&advertising,
12239 cmd->link_modes.advertising);
12241 if (cmd->base.autoneg == AUTONEG_ENABLE) {
12242 u32 mask = ADVERTISED_Autoneg |
12244 ADVERTISED_Asym_Pause;
12246 if (!(tp->phy_flags & TG3_PHYFLG_10_100_ONLY))
12247 mask |= ADVERTISED_1000baseT_Half |
12248 ADVERTISED_1000baseT_Full;
12250 if (!(tp->phy_flags & TG3_PHYFLG_ANY_SERDES))
12251 mask |= ADVERTISED_100baseT_Half |
12252 ADVERTISED_100baseT_Full |
12253 ADVERTISED_10baseT_Half |
12254 ADVERTISED_10baseT_Full |
12257 mask |= ADVERTISED_FIBRE;
12259 if (advertising & ~mask)
12262 mask &= (ADVERTISED_1000baseT_Half |
12263 ADVERTISED_1000baseT_Full |
12264 ADVERTISED_100baseT_Half |
12265 ADVERTISED_100baseT_Full |
12266 ADVERTISED_10baseT_Half |
12267 ADVERTISED_10baseT_Full);
12269 advertising &= mask;
12271 if (tp->phy_flags & TG3_PHYFLG_ANY_SERDES) {
12272 if (speed != SPEED_1000)
12275 if (cmd->base.duplex != DUPLEX_FULL)
12278 if (speed != SPEED_100 &&
12284 tg3_full_lock(tp, 0);
12286 tp->link_config.autoneg = cmd->base.autoneg;
12287 if (cmd->base.autoneg == AUTONEG_ENABLE) {
12288 tp->link_config.advertising = (advertising |
12289 ADVERTISED_Autoneg);
12290 tp->link_config.speed = SPEED_UNKNOWN;
12291 tp->link_config.duplex = DUPLEX_UNKNOWN;
12293 tp->link_config.advertising = 0;
12294 tp->link_config.speed = speed;
12295 tp->link_config.duplex = cmd->base.duplex;
12298 tp->phy_flags |= TG3_PHYFLG_USER_CONFIGURED;
12300 tg3_warn_mgmt_link_flap(tp);
12302 if (netif_running(dev))
12303 tg3_setup_phy(tp, true);
12305 tg3_full_unlock(tp);
12310 static void tg3_get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *info)
12312 struct tg3 *tp = netdev_priv(dev);
12314 strlcpy(info->driver, DRV_MODULE_NAME, sizeof(info->driver));
12315 strlcpy(info->version, DRV_MODULE_VERSION, sizeof(info->version));
12316 strlcpy(info->fw_version, tp->fw_ver, sizeof(info->fw_version));
12317 strlcpy(info->bus_info, pci_name(tp->pdev), sizeof(info->bus_info));
12320 static void tg3_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
12322 struct tg3 *tp = netdev_priv(dev);
12324 if (tg3_flag(tp, WOL_CAP) && device_can_wakeup(&tp->pdev->dev))
12325 wol->supported = WAKE_MAGIC;
12327 wol->supported = 0;
12329 if (tg3_flag(tp, WOL_ENABLE) && device_can_wakeup(&tp->pdev->dev))
12330 wol->wolopts = WAKE_MAGIC;
12331 memset(&wol->sopass, 0, sizeof(wol->sopass));
12334 static int tg3_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
12336 struct tg3 *tp = netdev_priv(dev);
12337 struct device *dp = &tp->pdev->dev;
12339 if (wol->wolopts & ~WAKE_MAGIC)
12341 if ((wol->wolopts & WAKE_MAGIC) &&
12342 !(tg3_flag(tp, WOL_CAP) && device_can_wakeup(dp)))
12345 device_set_wakeup_enable(dp, wol->wolopts & WAKE_MAGIC);
12347 if (device_may_wakeup(dp))
12348 tg3_flag_set(tp, WOL_ENABLE);
12350 tg3_flag_clear(tp, WOL_ENABLE);
12355 static u32 tg3_get_msglevel(struct net_device *dev)
12357 struct tg3 *tp = netdev_priv(dev);
12358 return tp->msg_enable;
12361 static void tg3_set_msglevel(struct net_device *dev, u32 value)
12363 struct tg3 *tp = netdev_priv(dev);
12364 tp->msg_enable = value;
12367 static int tg3_nway_reset(struct net_device *dev)
12369 struct tg3 *tp = netdev_priv(dev);
12372 if (!netif_running(dev))
12375 if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES)
12378 tg3_warn_mgmt_link_flap(tp);
12380 if (tg3_flag(tp, USE_PHYLIB)) {
12381 if (!(tp->phy_flags & TG3_PHYFLG_IS_CONNECTED))
12383 r = phy_start_aneg(mdiobus_get_phy(tp->mdio_bus, tp->phy_addr));
12387 spin_lock_bh(&tp->lock);
12389 tg3_readphy(tp, MII_BMCR, &bmcr);
12390 if (!tg3_readphy(tp, MII_BMCR, &bmcr) &&
12391 ((bmcr & BMCR_ANENABLE) ||
12392 (tp->phy_flags & TG3_PHYFLG_PARALLEL_DETECT))) {
12393 tg3_writephy(tp, MII_BMCR, bmcr | BMCR_ANRESTART |
12397 spin_unlock_bh(&tp->lock);
12403 static void tg3_get_ringparam(struct net_device *dev, struct ethtool_ringparam *ering)
12405 struct tg3 *tp = netdev_priv(dev);
12407 ering->rx_max_pending = tp->rx_std_ring_mask;
12408 if (tg3_flag(tp, JUMBO_RING_ENABLE))
12409 ering->rx_jumbo_max_pending = tp->rx_jmb_ring_mask;
12411 ering->rx_jumbo_max_pending = 0;
12413 ering->tx_max_pending = TG3_TX_RING_SIZE - 1;
12415 ering->rx_pending = tp->rx_pending;
12416 if (tg3_flag(tp, JUMBO_RING_ENABLE))
12417 ering->rx_jumbo_pending = tp->rx_jumbo_pending;
12419 ering->rx_jumbo_pending = 0;
12421 ering->tx_pending = tp->napi[0].tx_pending;
12424 static int tg3_set_ringparam(struct net_device *dev, struct ethtool_ringparam *ering)
12426 struct tg3 *tp = netdev_priv(dev);
12427 int i, irq_sync = 0, err = 0;
12429 if ((ering->rx_pending > tp->rx_std_ring_mask) ||
12430 (ering->rx_jumbo_pending > tp->rx_jmb_ring_mask) ||
12431 (ering->tx_pending > TG3_TX_RING_SIZE - 1) ||
12432 (ering->tx_pending <= MAX_SKB_FRAGS) ||
12433 (tg3_flag(tp, TSO_BUG) &&
12434 (ering->tx_pending <= (MAX_SKB_FRAGS * 3))))
12437 if (netif_running(dev)) {
12439 tg3_netif_stop(tp);
12443 tg3_full_lock(tp, irq_sync);
12445 tp->rx_pending = ering->rx_pending;
12447 if (tg3_flag(tp, MAX_RXPEND_64) &&
12448 tp->rx_pending > 63)
12449 tp->rx_pending = 63;
12451 if (tg3_flag(tp, JUMBO_RING_ENABLE))
12452 tp->rx_jumbo_pending = ering->rx_jumbo_pending;
12454 for (i = 0; i < tp->irq_max; i++)
12455 tp->napi[i].tx_pending = ering->tx_pending;
12457 if (netif_running(dev)) {
12458 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
12459 err = tg3_restart_hw(tp, false);
12461 tg3_netif_start(tp);
12464 tg3_full_unlock(tp);
12466 if (irq_sync && !err)
12472 static void tg3_get_pauseparam(struct net_device *dev, struct ethtool_pauseparam *epause)
12474 struct tg3 *tp = netdev_priv(dev);
12476 epause->autoneg = !!tg3_flag(tp, PAUSE_AUTONEG);
12478 if (tp->link_config.flowctrl & FLOW_CTRL_RX)
12479 epause->rx_pause = 1;
12481 epause->rx_pause = 0;
12483 if (tp->link_config.flowctrl & FLOW_CTRL_TX)
12484 epause->tx_pause = 1;
12486 epause->tx_pause = 0;
12489 static int tg3_set_pauseparam(struct net_device *dev, struct ethtool_pauseparam *epause)
12491 struct tg3 *tp = netdev_priv(dev);
12494 if (tp->link_config.autoneg == AUTONEG_ENABLE)
12495 tg3_warn_mgmt_link_flap(tp);
12497 if (tg3_flag(tp, USE_PHYLIB)) {
12499 struct phy_device *phydev;
12501 phydev = mdiobus_get_phy(tp->mdio_bus, tp->phy_addr);
12503 if (!(phydev->supported & SUPPORTED_Pause) ||
12504 (!(phydev->supported & SUPPORTED_Asym_Pause) &&
12505 (epause->rx_pause != epause->tx_pause)))
12508 tp->link_config.flowctrl = 0;
12509 if (epause->rx_pause) {
12510 tp->link_config.flowctrl |= FLOW_CTRL_RX;
12512 if (epause->tx_pause) {
12513 tp->link_config.flowctrl |= FLOW_CTRL_TX;
12514 newadv = ADVERTISED_Pause;
12516 newadv = ADVERTISED_Pause |
12517 ADVERTISED_Asym_Pause;
12518 } else if (epause->tx_pause) {
12519 tp->link_config.flowctrl |= FLOW_CTRL_TX;
12520 newadv = ADVERTISED_Asym_Pause;
12524 if (epause->autoneg)
12525 tg3_flag_set(tp, PAUSE_AUTONEG);
12527 tg3_flag_clear(tp, PAUSE_AUTONEG);
12529 if (tp->phy_flags & TG3_PHYFLG_IS_CONNECTED) {
12530 u32 oldadv = phydev->advertising &
12531 (ADVERTISED_Pause | ADVERTISED_Asym_Pause);
12532 if (oldadv != newadv) {
12533 phydev->advertising &=
12534 ~(ADVERTISED_Pause |
12535 ADVERTISED_Asym_Pause);
12536 phydev->advertising |= newadv;
12537 if (phydev->autoneg) {
12539 * Always renegotiate the link to
12540 * inform our link partner of our
12541 * flow control settings, even if the
12542 * flow control is forced. Let
12543 * tg3_adjust_link() do the final
12544 * flow control setup.
12546 return phy_start_aneg(phydev);
12550 if (!epause->autoneg)
12551 tg3_setup_flow_control(tp, 0, 0);
12553 tp->link_config.advertising &=
12554 ~(ADVERTISED_Pause |
12555 ADVERTISED_Asym_Pause);
12556 tp->link_config.advertising |= newadv;
12561 if (netif_running(dev)) {
12562 tg3_netif_stop(tp);
12566 tg3_full_lock(tp, irq_sync);
12568 if (epause->autoneg)
12569 tg3_flag_set(tp, PAUSE_AUTONEG);
12571 tg3_flag_clear(tp, PAUSE_AUTONEG);
12572 if (epause->rx_pause)
12573 tp->link_config.flowctrl |= FLOW_CTRL_RX;
12575 tp->link_config.flowctrl &= ~FLOW_CTRL_RX;
12576 if (epause->tx_pause)
12577 tp->link_config.flowctrl |= FLOW_CTRL_TX;
12579 tp->link_config.flowctrl &= ~FLOW_CTRL_TX;
12581 if (netif_running(dev)) {
12582 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
12583 err = tg3_restart_hw(tp, false);
12585 tg3_netif_start(tp);
12588 tg3_full_unlock(tp);
12591 tp->phy_flags |= TG3_PHYFLG_USER_CONFIGURED;
12596 static int tg3_get_sset_count(struct net_device *dev, int sset)
12600 return TG3_NUM_TEST;
12602 return TG3_NUM_STATS;
12604 return -EOPNOTSUPP;
12608 static int tg3_get_rxnfc(struct net_device *dev, struct ethtool_rxnfc *info,
12609 u32 *rules __always_unused)
12611 struct tg3 *tp = netdev_priv(dev);
12613 if (!tg3_flag(tp, SUPPORT_MSIX))
12614 return -EOPNOTSUPP;
12616 switch (info->cmd) {
12617 case ETHTOOL_GRXRINGS:
12618 if (netif_running(tp->dev))
12619 info->data = tp->rxq_cnt;
12621 info->data = num_online_cpus();
12622 if (info->data > TG3_RSS_MAX_NUM_QS)
12623 info->data = TG3_RSS_MAX_NUM_QS;
12629 return -EOPNOTSUPP;
12633 static u32 tg3_get_rxfh_indir_size(struct net_device *dev)
12636 struct tg3 *tp = netdev_priv(dev);
12638 if (tg3_flag(tp, SUPPORT_MSIX))
12639 size = TG3_RSS_INDIR_TBL_SIZE;
12644 static int tg3_get_rxfh(struct net_device *dev, u32 *indir, u8 *key, u8 *hfunc)
12646 struct tg3 *tp = netdev_priv(dev);
12650 *hfunc = ETH_RSS_HASH_TOP;
12654 for (i = 0; i < TG3_RSS_INDIR_TBL_SIZE; i++)
12655 indir[i] = tp->rss_ind_tbl[i];
12660 static int tg3_set_rxfh(struct net_device *dev, const u32 *indir, const u8 *key,
12663 struct tg3 *tp = netdev_priv(dev);
12666 /* We require at least one supported parameter to be changed and no
12667 * change in any of the unsupported parameters
12670 (hfunc != ETH_RSS_HASH_NO_CHANGE && hfunc != ETH_RSS_HASH_TOP))
12671 return -EOPNOTSUPP;
12676 for (i = 0; i < TG3_RSS_INDIR_TBL_SIZE; i++)
12677 tp->rss_ind_tbl[i] = indir[i];
12679 if (!netif_running(dev) || !tg3_flag(tp, ENABLE_RSS))
12682 /* It is legal to write the indirection
12683 * table while the device is running.
12685 tg3_full_lock(tp, 0);
12686 tg3_rss_write_indir_tbl(tp);
12687 tg3_full_unlock(tp);
12692 static void tg3_get_channels(struct net_device *dev,
12693 struct ethtool_channels *channel)
12695 struct tg3 *tp = netdev_priv(dev);
12696 u32 deflt_qs = netif_get_num_default_rss_queues();
12698 channel->max_rx = tp->rxq_max;
12699 channel->max_tx = tp->txq_max;
12701 if (netif_running(dev)) {
12702 channel->rx_count = tp->rxq_cnt;
12703 channel->tx_count = tp->txq_cnt;
12706 channel->rx_count = tp->rxq_req;
12708 channel->rx_count = min(deflt_qs, tp->rxq_max);
12711 channel->tx_count = tp->txq_req;
12713 channel->tx_count = min(deflt_qs, tp->txq_max);
12717 static int tg3_set_channels(struct net_device *dev,
12718 struct ethtool_channels *channel)
12720 struct tg3 *tp = netdev_priv(dev);
12722 if (!tg3_flag(tp, SUPPORT_MSIX))
12723 return -EOPNOTSUPP;
12725 if (channel->rx_count > tp->rxq_max ||
12726 channel->tx_count > tp->txq_max)
12729 tp->rxq_req = channel->rx_count;
12730 tp->txq_req = channel->tx_count;
12732 if (!netif_running(dev))
12737 tg3_carrier_off(tp);
12739 tg3_start(tp, true, false, false);
12744 static void tg3_get_strings(struct net_device *dev, u32 stringset, u8 *buf)
12746 switch (stringset) {
12748 memcpy(buf, ðtool_stats_keys, sizeof(ethtool_stats_keys));
12751 memcpy(buf, ðtool_test_keys, sizeof(ethtool_test_keys));
12754 WARN_ON(1); /* we need a WARN() */
12759 static int tg3_set_phys_id(struct net_device *dev,
12760 enum ethtool_phys_id_state state)
12762 struct tg3 *tp = netdev_priv(dev);
12764 if (!netif_running(tp->dev))
12768 case ETHTOOL_ID_ACTIVE:
12769 return 1; /* cycle on/off once per second */
12771 case ETHTOOL_ID_ON:
12772 tw32(MAC_LED_CTRL, LED_CTRL_LNKLED_OVERRIDE |
12773 LED_CTRL_1000MBPS_ON |
12774 LED_CTRL_100MBPS_ON |
12775 LED_CTRL_10MBPS_ON |
12776 LED_CTRL_TRAFFIC_OVERRIDE |
12777 LED_CTRL_TRAFFIC_BLINK |
12778 LED_CTRL_TRAFFIC_LED);
12781 case ETHTOOL_ID_OFF:
12782 tw32(MAC_LED_CTRL, LED_CTRL_LNKLED_OVERRIDE |
12783 LED_CTRL_TRAFFIC_OVERRIDE);
12786 case ETHTOOL_ID_INACTIVE:
12787 tw32(MAC_LED_CTRL, tp->led_ctrl);
12794 static void tg3_get_ethtool_stats(struct net_device *dev,
12795 struct ethtool_stats *estats, u64 *tmp_stats)
12797 struct tg3 *tp = netdev_priv(dev);
12800 tg3_get_estats(tp, (struct tg3_ethtool_stats *)tmp_stats);
12802 memset(tmp_stats, 0, sizeof(struct tg3_ethtool_stats));
12805 static __be32 *tg3_vpd_readblock(struct tg3 *tp, u32 *vpdlen)
12809 u32 offset = 0, len = 0;
12812 if (tg3_flag(tp, NO_NVRAM) || tg3_nvram_read(tp, 0, &magic))
12815 if (magic == TG3_EEPROM_MAGIC) {
12816 for (offset = TG3_NVM_DIR_START;
12817 offset < TG3_NVM_DIR_END;
12818 offset += TG3_NVM_DIRENT_SIZE) {
12819 if (tg3_nvram_read(tp, offset, &val))
12822 if ((val >> TG3_NVM_DIRTYPE_SHIFT) ==
12823 TG3_NVM_DIRTYPE_EXTVPD)
12827 if (offset != TG3_NVM_DIR_END) {
12828 len = (val & TG3_NVM_DIRTYPE_LENMSK) * 4;
12829 if (tg3_nvram_read(tp, offset + 4, &offset))
12832 offset = tg3_nvram_logical_addr(tp, offset);
12836 if (!offset || !len) {
12837 offset = TG3_NVM_VPD_OFF;
12838 len = TG3_NVM_VPD_LEN;
12841 buf = kmalloc(len, GFP_KERNEL);
12845 if (magic == TG3_EEPROM_MAGIC) {
12846 for (i = 0; i < len; i += 4) {
12847 /* The data is in little-endian format in NVRAM.
12848 * Use the big-endian read routines to preserve
12849 * the byte order as it exists in NVRAM.
12851 if (tg3_nvram_read_be32(tp, offset + i, &buf[i/4]))
12857 unsigned int pos = 0;
12859 ptr = (u8 *)&buf[0];
12860 for (i = 0; pos < len && i < 3; i++, pos += cnt, ptr += cnt) {
12861 cnt = pci_read_vpd(tp->pdev, pos,
12863 if (cnt == -ETIMEDOUT || cnt == -EINTR)
12881 #define NVRAM_TEST_SIZE 0x100
12882 #define NVRAM_SELFBOOT_FORMAT1_0_SIZE 0x14
12883 #define NVRAM_SELFBOOT_FORMAT1_2_SIZE 0x18
12884 #define NVRAM_SELFBOOT_FORMAT1_3_SIZE 0x1c
12885 #define NVRAM_SELFBOOT_FORMAT1_4_SIZE 0x20
12886 #define NVRAM_SELFBOOT_FORMAT1_5_SIZE 0x24
12887 #define NVRAM_SELFBOOT_FORMAT1_6_SIZE 0x50
12888 #define NVRAM_SELFBOOT_HW_SIZE 0x20
12889 #define NVRAM_SELFBOOT_DATA_SIZE 0x1c
12891 static int tg3_test_nvram(struct tg3 *tp)
12893 u32 csum, magic, len;
12895 int i, j, k, err = 0, size;
12897 if (tg3_flag(tp, NO_NVRAM))
12900 if (tg3_nvram_read(tp, 0, &magic) != 0)
12903 if (magic == TG3_EEPROM_MAGIC)
12904 size = NVRAM_TEST_SIZE;
12905 else if ((magic & TG3_EEPROM_MAGIC_FW_MSK) == TG3_EEPROM_MAGIC_FW) {
12906 if ((magic & TG3_EEPROM_SB_FORMAT_MASK) ==
12907 TG3_EEPROM_SB_FORMAT_1) {
12908 switch (magic & TG3_EEPROM_SB_REVISION_MASK) {
12909 case TG3_EEPROM_SB_REVISION_0:
12910 size = NVRAM_SELFBOOT_FORMAT1_0_SIZE;
12912 case TG3_EEPROM_SB_REVISION_2:
12913 size = NVRAM_SELFBOOT_FORMAT1_2_SIZE;
12915 case TG3_EEPROM_SB_REVISION_3:
12916 size = NVRAM_SELFBOOT_FORMAT1_3_SIZE;
12918 case TG3_EEPROM_SB_REVISION_4:
12919 size = NVRAM_SELFBOOT_FORMAT1_4_SIZE;
12921 case TG3_EEPROM_SB_REVISION_5:
12922 size = NVRAM_SELFBOOT_FORMAT1_5_SIZE;
12924 case TG3_EEPROM_SB_REVISION_6:
12925 size = NVRAM_SELFBOOT_FORMAT1_6_SIZE;
12932 } else if ((magic & TG3_EEPROM_MAGIC_HW_MSK) == TG3_EEPROM_MAGIC_HW)
12933 size = NVRAM_SELFBOOT_HW_SIZE;
12937 buf = kmalloc(size, GFP_KERNEL);
12942 for (i = 0, j = 0; i < size; i += 4, j++) {
12943 err = tg3_nvram_read_be32(tp, i, &buf[j]);
12950 /* Selfboot format */
12951 magic = be32_to_cpu(buf[0]);
12952 if ((magic & TG3_EEPROM_MAGIC_FW_MSK) ==
12953 TG3_EEPROM_MAGIC_FW) {
12954 u8 *buf8 = (u8 *) buf, csum8 = 0;
12956 if ((magic & TG3_EEPROM_SB_REVISION_MASK) ==
12957 TG3_EEPROM_SB_REVISION_2) {
12958 /* For rev 2, the csum doesn't include the MBA. */
12959 for (i = 0; i < TG3_EEPROM_SB_F1R2_MBA_OFF; i++)
12961 for (i = TG3_EEPROM_SB_F1R2_MBA_OFF + 4; i < size; i++)
12964 for (i = 0; i < size; i++)
12977 if ((magic & TG3_EEPROM_MAGIC_HW_MSK) ==
12978 TG3_EEPROM_MAGIC_HW) {
12979 u8 data[NVRAM_SELFBOOT_DATA_SIZE];
12980 u8 parity[NVRAM_SELFBOOT_DATA_SIZE];
12981 u8 *buf8 = (u8 *) buf;
12983 /* Separate the parity bits and the data bytes. */
12984 for (i = 0, j = 0, k = 0; i < NVRAM_SELFBOOT_HW_SIZE; i++) {
12985 if ((i == 0) || (i == 8)) {
12989 for (l = 0, msk = 0x80; l < 7; l++, msk >>= 1)
12990 parity[k++] = buf8[i] & msk;
12992 } else if (i == 16) {
12996 for (l = 0, msk = 0x20; l < 6; l++, msk >>= 1)
12997 parity[k++] = buf8[i] & msk;
13000 for (l = 0, msk = 0x80; l < 8; l++, msk >>= 1)
13001 parity[k++] = buf8[i] & msk;
13004 data[j++] = buf8[i];
13008 for (i = 0; i < NVRAM_SELFBOOT_DATA_SIZE; i++) {
13009 u8 hw8 = hweight8(data[i]);
13011 if ((hw8 & 0x1) && parity[i])
13013 else if (!(hw8 & 0x1) && !parity[i])
13022 /* Bootstrap checksum at offset 0x10 */
13023 csum = calc_crc((unsigned char *) buf, 0x10);
13024 if (csum != le32_to_cpu(buf[0x10/4]))
13027 /* Manufacturing block starts at offset 0x74, checksum at 0xfc */
13028 csum = calc_crc((unsigned char *) &buf[0x74/4], 0x88);
13029 if (csum != le32_to_cpu(buf[0xfc/4]))
13034 buf = tg3_vpd_readblock(tp, &len);
13038 i = pci_vpd_find_tag((u8 *)buf, 0, len, PCI_VPD_LRDT_RO_DATA);
13040 j = pci_vpd_lrdt_size(&((u8 *)buf)[i]);
13044 if (i + PCI_VPD_LRDT_TAG_SIZE + j > len)
13047 i += PCI_VPD_LRDT_TAG_SIZE;
13048 j = pci_vpd_find_info_keyword((u8 *)buf, i, j,
13049 PCI_VPD_RO_KEYWORD_CHKSUM);
13053 j += PCI_VPD_INFO_FLD_HDR_SIZE;
13055 for (i = 0; i <= j; i++)
13056 csum8 += ((u8 *)buf)[i];
13070 #define TG3_SERDES_TIMEOUT_SEC 2
13071 #define TG3_COPPER_TIMEOUT_SEC 6
13073 static int tg3_test_link(struct tg3 *tp)
13077 if (!netif_running(tp->dev))
13080 if (tp->phy_flags & TG3_PHYFLG_ANY_SERDES)
13081 max = TG3_SERDES_TIMEOUT_SEC;
13083 max = TG3_COPPER_TIMEOUT_SEC;
13085 for (i = 0; i < max; i++) {
13089 if (msleep_interruptible(1000))
13096 /* Only test the commonly used registers */
13097 static int tg3_test_registers(struct tg3 *tp)
13099 int i, is_5705, is_5750;
13100 u32 offset, read_mask, write_mask, val, save_val, read_val;
13104 #define TG3_FL_5705 0x1
13105 #define TG3_FL_NOT_5705 0x2
13106 #define TG3_FL_NOT_5788 0x4
13107 #define TG3_FL_NOT_5750 0x8
13111 /* MAC Control Registers */
13112 { MAC_MODE, TG3_FL_NOT_5705,
13113 0x00000000, 0x00ef6f8c },
13114 { MAC_MODE, TG3_FL_5705,
13115 0x00000000, 0x01ef6b8c },
13116 { MAC_STATUS, TG3_FL_NOT_5705,
13117 0x03800107, 0x00000000 },
13118 { MAC_STATUS, TG3_FL_5705,
13119 0x03800100, 0x00000000 },
13120 { MAC_ADDR_0_HIGH, 0x0000,
13121 0x00000000, 0x0000ffff },
13122 { MAC_ADDR_0_LOW, 0x0000,
13123 0x00000000, 0xffffffff },
13124 { MAC_RX_MTU_SIZE, 0x0000,
13125 0x00000000, 0x0000ffff },
13126 { MAC_TX_MODE, 0x0000,
13127 0x00000000, 0x00000070 },
13128 { MAC_TX_LENGTHS, 0x0000,
13129 0x00000000, 0x00003fff },
13130 { MAC_RX_MODE, TG3_FL_NOT_5705,
13131 0x00000000, 0x000007fc },
13132 { MAC_RX_MODE, TG3_FL_5705,
13133 0x00000000, 0x000007dc },
13134 { MAC_HASH_REG_0, 0x0000,
13135 0x00000000, 0xffffffff },
13136 { MAC_HASH_REG_1, 0x0000,
13137 0x00000000, 0xffffffff },
13138 { MAC_HASH_REG_2, 0x0000,
13139 0x00000000, 0xffffffff },
13140 { MAC_HASH_REG_3, 0x0000,
13141 0x00000000, 0xffffffff },
13143 /* Receive Data and Receive BD Initiator Control Registers. */
13144 { RCVDBDI_JUMBO_BD+0, TG3_FL_NOT_5705,
13145 0x00000000, 0xffffffff },
13146 { RCVDBDI_JUMBO_BD+4, TG3_FL_NOT_5705,
13147 0x00000000, 0xffffffff },
13148 { RCVDBDI_JUMBO_BD+8, TG3_FL_NOT_5705,
13149 0x00000000, 0x00000003 },
13150 { RCVDBDI_JUMBO_BD+0xc, TG3_FL_NOT_5705,
13151 0x00000000, 0xffffffff },
13152 { RCVDBDI_STD_BD+0, 0x0000,
13153 0x00000000, 0xffffffff },
13154 { RCVDBDI_STD_BD+4, 0x0000,
13155 0x00000000, 0xffffffff },
13156 { RCVDBDI_STD_BD+8, 0x0000,
13157 0x00000000, 0xffff0002 },
13158 { RCVDBDI_STD_BD+0xc, 0x0000,
13159 0x00000000, 0xffffffff },
13161 /* Receive BD Initiator Control Registers. */
13162 { RCVBDI_STD_THRESH, TG3_FL_NOT_5705,
13163 0x00000000, 0xffffffff },
13164 { RCVBDI_STD_THRESH, TG3_FL_5705,
13165 0x00000000, 0x000003ff },
13166 { RCVBDI_JUMBO_THRESH, TG3_FL_NOT_5705,
13167 0x00000000, 0xffffffff },
13169 /* Host Coalescing Control Registers. */
13170 { HOSTCC_MODE, TG3_FL_NOT_5705,
13171 0x00000000, 0x00000004 },
13172 { HOSTCC_MODE, TG3_FL_5705,
13173 0x00000000, 0x000000f6 },
13174 { HOSTCC_RXCOL_TICKS, TG3_FL_NOT_5705,
13175 0x00000000, 0xffffffff },
13176 { HOSTCC_RXCOL_TICKS, TG3_FL_5705,
13177 0x00000000, 0x000003ff },
13178 { HOSTCC_TXCOL_TICKS, TG3_FL_NOT_5705,
13179 0x00000000, 0xffffffff },
13180 { HOSTCC_TXCOL_TICKS, TG3_FL_5705,
13181 0x00000000, 0x000003ff },
13182 { HOSTCC_RXMAX_FRAMES, TG3_FL_NOT_5705,
13183 0x00000000, 0xffffffff },
13184 { HOSTCC_RXMAX_FRAMES, TG3_FL_5705 | TG3_FL_NOT_5788,
13185 0x00000000, 0x000000ff },
13186 { HOSTCC_TXMAX_FRAMES, TG3_FL_NOT_5705,
13187 0x00000000, 0xffffffff },
13188 { HOSTCC_TXMAX_FRAMES, TG3_FL_5705 | TG3_FL_NOT_5788,
13189 0x00000000, 0x000000ff },
13190 { HOSTCC_RXCOAL_TICK_INT, TG3_FL_NOT_5705,
13191 0x00000000, 0xffffffff },
13192 { HOSTCC_TXCOAL_TICK_INT, TG3_FL_NOT_5705,
13193 0x00000000, 0xffffffff },
13194 { HOSTCC_RXCOAL_MAXF_INT, TG3_FL_NOT_5705,
13195 0x00000000, 0xffffffff },
13196 { HOSTCC_RXCOAL_MAXF_INT, TG3_FL_5705 | TG3_FL_NOT_5788,
13197 0x00000000, 0x000000ff },
13198 { HOSTCC_TXCOAL_MAXF_INT, TG3_FL_NOT_5705,
13199 0x00000000, 0xffffffff },
13200 { HOSTCC_TXCOAL_MAXF_INT, TG3_FL_5705 | TG3_FL_NOT_5788,
13201 0x00000000, 0x000000ff },
13202 { HOSTCC_STAT_COAL_TICKS, TG3_FL_NOT_5705,
13203 0x00000000, 0xffffffff },
13204 { HOSTCC_STATS_BLK_HOST_ADDR, TG3_FL_NOT_5705,
13205 0x00000000, 0xffffffff },
13206 { HOSTCC_STATS_BLK_HOST_ADDR+4, TG3_FL_NOT_5705,
13207 0x00000000, 0xffffffff },
13208 { HOSTCC_STATUS_BLK_HOST_ADDR, 0x0000,
13209 0x00000000, 0xffffffff },
13210 { HOSTCC_STATUS_BLK_HOST_ADDR+4, 0x0000,
13211 0x00000000, 0xffffffff },
13212 { HOSTCC_STATS_BLK_NIC_ADDR, 0x0000,
13213 0xffffffff, 0x00000000 },
13214 { HOSTCC_STATUS_BLK_NIC_ADDR, 0x0000,
13215 0xffffffff, 0x00000000 },
13217 /* Buffer Manager Control Registers. */
13218 { BUFMGR_MB_POOL_ADDR, TG3_FL_NOT_5750,
13219 0x00000000, 0x007fff80 },
13220 { BUFMGR_MB_POOL_SIZE, TG3_FL_NOT_5750,
13221 0x00000000, 0x007fffff },
13222 { BUFMGR_MB_RDMA_LOW_WATER, 0x0000,
13223 0x00000000, 0x0000003f },
13224 { BUFMGR_MB_MACRX_LOW_WATER, 0x0000,
13225 0x00000000, 0x000001ff },
13226 { BUFMGR_MB_HIGH_WATER, 0x0000,
13227 0x00000000, 0x000001ff },
13228 { BUFMGR_DMA_DESC_POOL_ADDR, TG3_FL_NOT_5705,
13229 0xffffffff, 0x00000000 },
13230 { BUFMGR_DMA_DESC_POOL_SIZE, TG3_FL_NOT_5705,
13231 0xffffffff, 0x00000000 },
13233 /* Mailbox Registers */
13234 { GRCMBOX_RCVSTD_PROD_IDX+4, 0x0000,
13235 0x00000000, 0x000001ff },
13236 { GRCMBOX_RCVJUMBO_PROD_IDX+4, TG3_FL_NOT_5705,
13237 0x00000000, 0x000001ff },
13238 { GRCMBOX_RCVRET_CON_IDX_0+4, 0x0000,
13239 0x00000000, 0x000007ff },
13240 { GRCMBOX_SNDHOST_PROD_IDX_0+4, 0x0000,
13241 0x00000000, 0x000001ff },
13243 { 0xffff, 0x0000, 0x00000000, 0x00000000 },
13246 is_5705 = is_5750 = 0;
13247 if (tg3_flag(tp, 5705_PLUS)) {
13249 if (tg3_flag(tp, 5750_PLUS))
13253 for (i = 0; reg_tbl[i].offset != 0xffff; i++) {
13254 if (is_5705 && (reg_tbl[i].flags & TG3_FL_NOT_5705))
13257 if (!is_5705 && (reg_tbl[i].flags & TG3_FL_5705))
13260 if (tg3_flag(tp, IS_5788) &&
13261 (reg_tbl[i].flags & TG3_FL_NOT_5788))
13264 if (is_5750 && (reg_tbl[i].flags & TG3_FL_NOT_5750))
13267 offset = (u32) reg_tbl[i].offset;
13268 read_mask = reg_tbl[i].read_mask;
13269 write_mask = reg_tbl[i].write_mask;
13271 /* Save the original register content */
13272 save_val = tr32(offset);
13274 /* Determine the read-only value. */
13275 read_val = save_val & read_mask;
13277 /* Write zero to the register, then make sure the read-only bits
13278 * are not changed and the read/write bits are all zeros.
13282 val = tr32(offset);
13284 /* Test the read-only and read/write bits. */
13285 if (((val & read_mask) != read_val) || (val & write_mask))
13288 /* Write ones to all the bits defined by RdMask and WrMask, then
13289 * make sure the read-only bits are not changed and the
13290 * read/write bits are all ones.
13292 tw32(offset, read_mask | write_mask);
13294 val = tr32(offset);
13296 /* Test the read-only bits. */
13297 if ((val & read_mask) != read_val)
13300 /* Test the read/write bits. */
13301 if ((val & write_mask) != write_mask)
13304 tw32(offset, save_val);
13310 if (netif_msg_hw(tp))
13311 netdev_err(tp->dev,
13312 "Register test failed at offset %x\n", offset);
13313 tw32(offset, save_val);
13317 static int tg3_do_mem_test(struct tg3 *tp, u32 offset, u32 len)
13319 static const u32 test_pattern[] = { 0x00000000, 0xffffffff, 0xaa55a55a };
13323 for (i = 0; i < ARRAY_SIZE(test_pattern); i++) {
13324 for (j = 0; j < len; j += 4) {
13327 tg3_write_mem(tp, offset + j, test_pattern[i]);
13328 tg3_read_mem(tp, offset + j, &val);
13329 if (val != test_pattern[i])
13336 static int tg3_test_memory(struct tg3 *tp)
13338 static struct mem_entry {
13341 } mem_tbl_570x[] = {
13342 { 0x00000000, 0x00b50},
13343 { 0x00002000, 0x1c000},
13344 { 0xffffffff, 0x00000}
13345 }, mem_tbl_5705[] = {
13346 { 0x00000100, 0x0000c},
13347 { 0x00000200, 0x00008},
13348 { 0x00004000, 0x00800},
13349 { 0x00006000, 0x01000},
13350 { 0x00008000, 0x02000},
13351 { 0x00010000, 0x0e000},
13352 { 0xffffffff, 0x00000}
13353 }, mem_tbl_5755[] = {
13354 { 0x00000200, 0x00008},
13355 { 0x00004000, 0x00800},
13356 { 0x00006000, 0x00800},
13357 { 0x00008000, 0x02000},
13358 { 0x00010000, 0x0c000},
13359 { 0xffffffff, 0x00000}
13360 }, mem_tbl_5906[] = {
13361 { 0x00000200, 0x00008},
13362 { 0x00004000, 0x00400},
13363 { 0x00006000, 0x00400},
13364 { 0x00008000, 0x01000},
13365 { 0x00010000, 0x01000},
13366 { 0xffffffff, 0x00000}
13367 }, mem_tbl_5717[] = {
13368 { 0x00000200, 0x00008},
13369 { 0x00010000, 0x0a000},
13370 { 0x00020000, 0x13c00},
13371 { 0xffffffff, 0x00000}
13372 }, mem_tbl_57765[] = {
13373 { 0x00000200, 0x00008},
13374 { 0x00004000, 0x00800},
13375 { 0x00006000, 0x09800},
13376 { 0x00010000, 0x0a000},
13377 { 0xffffffff, 0x00000}
13379 struct mem_entry *mem_tbl;
13383 if (tg3_flag(tp, 5717_PLUS))
13384 mem_tbl = mem_tbl_5717;
13385 else if (tg3_flag(tp, 57765_CLASS) ||
13386 tg3_asic_rev(tp) == ASIC_REV_5762)
13387 mem_tbl = mem_tbl_57765;
13388 else if (tg3_flag(tp, 5755_PLUS))
13389 mem_tbl = mem_tbl_5755;
13390 else if (tg3_asic_rev(tp) == ASIC_REV_5906)
13391 mem_tbl = mem_tbl_5906;
13392 else if (tg3_flag(tp, 5705_PLUS))
13393 mem_tbl = mem_tbl_5705;
13395 mem_tbl = mem_tbl_570x;
13397 for (i = 0; mem_tbl[i].offset != 0xffffffff; i++) {
13398 err = tg3_do_mem_test(tp, mem_tbl[i].offset, mem_tbl[i].len);
13406 #define TG3_TSO_MSS 500
13408 #define TG3_TSO_IP_HDR_LEN 20
13409 #define TG3_TSO_TCP_HDR_LEN 20
13410 #define TG3_TSO_TCP_OPT_LEN 12
13412 static const u8 tg3_tso_header[] = {
13414 0x45, 0x00, 0x00, 0x00,
13415 0x00, 0x00, 0x40, 0x00,
13416 0x40, 0x06, 0x00, 0x00,
13417 0x0a, 0x00, 0x00, 0x01,
13418 0x0a, 0x00, 0x00, 0x02,
13419 0x0d, 0x00, 0xe0, 0x00,
13420 0x00, 0x00, 0x01, 0x00,
13421 0x00, 0x00, 0x02, 0x00,
13422 0x80, 0x10, 0x10, 0x00,
13423 0x14, 0x09, 0x00, 0x00,
13424 0x01, 0x01, 0x08, 0x0a,
13425 0x11, 0x11, 0x11, 0x11,
13426 0x11, 0x11, 0x11, 0x11,
13429 static int tg3_run_loopback(struct tg3 *tp, u32 pktsz, bool tso_loopback)
13431 u32 rx_start_idx, rx_idx, tx_idx, opaque_key;
13432 u32 base_flags = 0, mss = 0, desc_idx, coal_now, data_off, val;
13434 struct sk_buff *skb;
13435 u8 *tx_data, *rx_data;
13437 int num_pkts, tx_len, rx_len, i, err;
13438 struct tg3_rx_buffer_desc *desc;
13439 struct tg3_napi *tnapi, *rnapi;
13440 struct tg3_rx_prodring_set *tpr = &tp->napi[0].prodring;
13442 tnapi = &tp->napi[0];
13443 rnapi = &tp->napi[0];
13444 if (tp->irq_cnt > 1) {
13445 if (tg3_flag(tp, ENABLE_RSS))
13446 rnapi = &tp->napi[1];
13447 if (tg3_flag(tp, ENABLE_TSS))
13448 tnapi = &tp->napi[1];
13450 coal_now = tnapi->coal_now | rnapi->coal_now;
13455 skb = netdev_alloc_skb(tp->dev, tx_len);
13459 tx_data = skb_put(skb, tx_len);
13460 memcpy(tx_data, tp->dev->dev_addr, ETH_ALEN);
13461 memset(tx_data + ETH_ALEN, 0x0, 8);
13463 tw32(MAC_RX_MTU_SIZE, tx_len + ETH_FCS_LEN);
13465 if (tso_loopback) {
13466 struct iphdr *iph = (struct iphdr *)&tx_data[ETH_HLEN];
13468 u32 hdr_len = TG3_TSO_IP_HDR_LEN + TG3_TSO_TCP_HDR_LEN +
13469 TG3_TSO_TCP_OPT_LEN;
13471 memcpy(tx_data + ETH_ALEN * 2, tg3_tso_header,
13472 sizeof(tg3_tso_header));
13475 val = tx_len - ETH_ALEN * 2 - sizeof(tg3_tso_header);
13476 num_pkts = DIV_ROUND_UP(val, TG3_TSO_MSS);
13478 /* Set the total length field in the IP header */
13479 iph->tot_len = htons((u16)(mss + hdr_len));
13481 base_flags = (TXD_FLAG_CPU_PRE_DMA |
13482 TXD_FLAG_CPU_POST_DMA);
13484 if (tg3_flag(tp, HW_TSO_1) ||
13485 tg3_flag(tp, HW_TSO_2) ||
13486 tg3_flag(tp, HW_TSO_3)) {
13488 val = ETH_HLEN + TG3_TSO_IP_HDR_LEN;
13489 th = (struct tcphdr *)&tx_data[val];
13492 base_flags |= TXD_FLAG_TCPUDP_CSUM;
13494 if (tg3_flag(tp, HW_TSO_3)) {
13495 mss |= (hdr_len & 0xc) << 12;
13496 if (hdr_len & 0x10)
13497 base_flags |= 0x00000010;
13498 base_flags |= (hdr_len & 0x3e0) << 5;
13499 } else if (tg3_flag(tp, HW_TSO_2))
13500 mss |= hdr_len << 9;
13501 else if (tg3_flag(tp, HW_TSO_1) ||
13502 tg3_asic_rev(tp) == ASIC_REV_5705) {
13503 mss |= (TG3_TSO_TCP_OPT_LEN << 9);
13505 base_flags |= (TG3_TSO_TCP_OPT_LEN << 10);
13508 data_off = ETH_ALEN * 2 + sizeof(tg3_tso_header);
13511 data_off = ETH_HLEN;
13513 if (tg3_flag(tp, USE_JUMBO_BDFLAG) &&
13514 tx_len > VLAN_ETH_FRAME_LEN)
13515 base_flags |= TXD_FLAG_JMB_PKT;
13518 for (i = data_off; i < tx_len; i++)
13519 tx_data[i] = (u8) (i & 0xff);
13521 map = pci_map_single(tp->pdev, skb->data, tx_len, PCI_DMA_TODEVICE);
13522 if (pci_dma_mapping_error(tp->pdev, map)) {
13523 dev_kfree_skb(skb);
13527 val = tnapi->tx_prod;
13528 tnapi->tx_buffers[val].skb = skb;
13529 dma_unmap_addr_set(&tnapi->tx_buffers[val], mapping, map);
13531 tw32_f(HOSTCC_MODE, tp->coalesce_mode | HOSTCC_MODE_ENABLE |
13536 rx_start_idx = rnapi->hw_status->idx[0].rx_producer;
13538 budget = tg3_tx_avail(tnapi);
13539 if (tg3_tx_frag_set(tnapi, &val, &budget, map, tx_len,
13540 base_flags | TXD_FLAG_END, mss, 0)) {
13541 tnapi->tx_buffers[val].skb = NULL;
13542 dev_kfree_skb(skb);
13548 /* Sync BD data before updating mailbox */
13551 tw32_tx_mbox(tnapi->prodmbox, tnapi->tx_prod);
13552 tr32_mailbox(tnapi->prodmbox);
13556 /* 350 usec to allow enough time on some 10/100 Mbps devices. */
13557 for (i = 0; i < 35; i++) {
13558 tw32_f(HOSTCC_MODE, tp->coalesce_mode | HOSTCC_MODE_ENABLE |
13563 tx_idx = tnapi->hw_status->idx[0].tx_consumer;
13564 rx_idx = rnapi->hw_status->idx[0].rx_producer;
13565 if ((tx_idx == tnapi->tx_prod) &&
13566 (rx_idx == (rx_start_idx + num_pkts)))
13570 tg3_tx_skb_unmap(tnapi, tnapi->tx_prod - 1, -1);
13571 dev_kfree_skb(skb);
13573 if (tx_idx != tnapi->tx_prod)
13576 if (rx_idx != rx_start_idx + num_pkts)
13580 while (rx_idx != rx_start_idx) {
13581 desc = &rnapi->rx_rcb[rx_start_idx++];
13582 desc_idx = desc->opaque & RXD_OPAQUE_INDEX_MASK;
13583 opaque_key = desc->opaque & RXD_OPAQUE_RING_MASK;
13585 if ((desc->err_vlan & RXD_ERR_MASK) != 0 &&
13586 (desc->err_vlan != RXD_ERR_ODD_NIBBLE_RCVD_MII))
13589 rx_len = ((desc->idx_len & RXD_LEN_MASK) >> RXD_LEN_SHIFT)
13592 if (!tso_loopback) {
13593 if (rx_len != tx_len)
13596 if (pktsz <= TG3_RX_STD_DMA_SZ - ETH_FCS_LEN) {
13597 if (opaque_key != RXD_OPAQUE_RING_STD)
13600 if (opaque_key != RXD_OPAQUE_RING_JUMBO)
13603 } else if ((desc->type_flags & RXD_FLAG_TCPUDP_CSUM) &&
13604 (desc->ip_tcp_csum & RXD_TCPCSUM_MASK)
13605 >> RXD_TCPCSUM_SHIFT != 0xffff) {
13609 if (opaque_key == RXD_OPAQUE_RING_STD) {
13610 rx_data = tpr->rx_std_buffers[desc_idx].data;
13611 map = dma_unmap_addr(&tpr->rx_std_buffers[desc_idx],
13613 } else if (opaque_key == RXD_OPAQUE_RING_JUMBO) {
13614 rx_data = tpr->rx_jmb_buffers[desc_idx].data;
13615 map = dma_unmap_addr(&tpr->rx_jmb_buffers[desc_idx],
13620 pci_dma_sync_single_for_cpu(tp->pdev, map, rx_len,
13621 PCI_DMA_FROMDEVICE);
13623 rx_data += TG3_RX_OFFSET(tp);
13624 for (i = data_off; i < rx_len; i++, val++) {
13625 if (*(rx_data + i) != (u8) (val & 0xff))
13632 /* tg3_free_rings will unmap and free the rx_data */
13637 #define TG3_STD_LOOPBACK_FAILED 1
13638 #define TG3_JMB_LOOPBACK_FAILED 2
13639 #define TG3_TSO_LOOPBACK_FAILED 4
13640 #define TG3_LOOPBACK_FAILED \
13641 (TG3_STD_LOOPBACK_FAILED | \
13642 TG3_JMB_LOOPBACK_FAILED | \
13643 TG3_TSO_LOOPBACK_FAILED)
13645 static int tg3_test_loopback(struct tg3 *tp, u64 *data, bool do_extlpbk)
13649 u32 jmb_pkt_sz = 9000;
13652 jmb_pkt_sz = tp->dma_limit - ETH_HLEN;
13654 eee_cap = tp->phy_flags & TG3_PHYFLG_EEE_CAP;
13655 tp->phy_flags &= ~TG3_PHYFLG_EEE_CAP;
13657 if (!netif_running(tp->dev)) {
13658 data[TG3_MAC_LOOPB_TEST] = TG3_LOOPBACK_FAILED;
13659 data[TG3_PHY_LOOPB_TEST] = TG3_LOOPBACK_FAILED;
13661 data[TG3_EXT_LOOPB_TEST] = TG3_LOOPBACK_FAILED;
13665 err = tg3_reset_hw(tp, true);
13667 data[TG3_MAC_LOOPB_TEST] = TG3_LOOPBACK_FAILED;
13668 data[TG3_PHY_LOOPB_TEST] = TG3_LOOPBACK_FAILED;
13670 data[TG3_EXT_LOOPB_TEST] = TG3_LOOPBACK_FAILED;
13674 if (tg3_flag(tp, ENABLE_RSS)) {
13677 /* Reroute all rx packets to the 1st queue */
13678 for (i = MAC_RSS_INDIR_TBL_0;
13679 i < MAC_RSS_INDIR_TBL_0 + TG3_RSS_INDIR_TBL_SIZE; i += 4)
13683 /* HW errata - mac loopback fails in some cases on 5780.
13684 * Normal traffic and PHY loopback are not affected by
13685 * errata. Also, the MAC loopback test is deprecated for
13686 * all newer ASIC revisions.
13688 if (tg3_asic_rev(tp) != ASIC_REV_5780 &&
13689 !tg3_flag(tp, CPMU_PRESENT)) {
13690 tg3_mac_loopback(tp, true);
13692 if (tg3_run_loopback(tp, ETH_FRAME_LEN, false))
13693 data[TG3_MAC_LOOPB_TEST] |= TG3_STD_LOOPBACK_FAILED;
13695 if (tg3_flag(tp, JUMBO_RING_ENABLE) &&
13696 tg3_run_loopback(tp, jmb_pkt_sz + ETH_HLEN, false))
13697 data[TG3_MAC_LOOPB_TEST] |= TG3_JMB_LOOPBACK_FAILED;
13699 tg3_mac_loopback(tp, false);
13702 if (!(tp->phy_flags & TG3_PHYFLG_PHY_SERDES) &&
13703 !tg3_flag(tp, USE_PHYLIB)) {
13706 tg3_phy_lpbk_set(tp, 0, false);
13708 /* Wait for link */
13709 for (i = 0; i < 100; i++) {
13710 if (tr32(MAC_TX_STATUS) & TX_STATUS_LINK_UP)
13715 if (tg3_run_loopback(tp, ETH_FRAME_LEN, false))
13716 data[TG3_PHY_LOOPB_TEST] |= TG3_STD_LOOPBACK_FAILED;
13717 if (tg3_flag(tp, TSO_CAPABLE) &&
13718 tg3_run_loopback(tp, ETH_FRAME_LEN, true))
13719 data[TG3_PHY_LOOPB_TEST] |= TG3_TSO_LOOPBACK_FAILED;
13720 if (tg3_flag(tp, JUMBO_RING_ENABLE) &&
13721 tg3_run_loopback(tp, jmb_pkt_sz + ETH_HLEN, false))
13722 data[TG3_PHY_LOOPB_TEST] |= TG3_JMB_LOOPBACK_FAILED;
13725 tg3_phy_lpbk_set(tp, 0, true);
13727 /* All link indications report up, but the hardware
13728 * isn't really ready for about 20 msec. Double it
13733 if (tg3_run_loopback(tp, ETH_FRAME_LEN, false))
13734 data[TG3_EXT_LOOPB_TEST] |=
13735 TG3_STD_LOOPBACK_FAILED;
13736 if (tg3_flag(tp, TSO_CAPABLE) &&
13737 tg3_run_loopback(tp, ETH_FRAME_LEN, true))
13738 data[TG3_EXT_LOOPB_TEST] |=
13739 TG3_TSO_LOOPBACK_FAILED;
13740 if (tg3_flag(tp, JUMBO_RING_ENABLE) &&
13741 tg3_run_loopback(tp, jmb_pkt_sz + ETH_HLEN, false))
13742 data[TG3_EXT_LOOPB_TEST] |=
13743 TG3_JMB_LOOPBACK_FAILED;
13746 /* Re-enable gphy autopowerdown. */
13747 if (tp->phy_flags & TG3_PHYFLG_ENABLE_APD)
13748 tg3_phy_toggle_apd(tp, true);
13751 err = (data[TG3_MAC_LOOPB_TEST] | data[TG3_PHY_LOOPB_TEST] |
13752 data[TG3_EXT_LOOPB_TEST]) ? -EIO : 0;
13755 tp->phy_flags |= eee_cap;
13760 static void tg3_self_test(struct net_device *dev, struct ethtool_test *etest,
13763 struct tg3 *tp = netdev_priv(dev);
13764 bool doextlpbk = etest->flags & ETH_TEST_FL_EXTERNAL_LB;
13766 if (tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER) {
13767 if (tg3_power_up(tp)) {
13768 etest->flags |= ETH_TEST_FL_FAILED;
13769 memset(data, 1, sizeof(u64) * TG3_NUM_TEST);
13772 tg3_ape_driver_state_change(tp, RESET_KIND_INIT);
13775 memset(data, 0, sizeof(u64) * TG3_NUM_TEST);
13777 if (tg3_test_nvram(tp) != 0) {
13778 etest->flags |= ETH_TEST_FL_FAILED;
13779 data[TG3_NVRAM_TEST] = 1;
13781 if (!doextlpbk && tg3_test_link(tp)) {
13782 etest->flags |= ETH_TEST_FL_FAILED;
13783 data[TG3_LINK_TEST] = 1;
13785 if (etest->flags & ETH_TEST_FL_OFFLINE) {
13786 int err, err2 = 0, irq_sync = 0;
13788 if (netif_running(dev)) {
13790 tg3_netif_stop(tp);
13794 tg3_full_lock(tp, irq_sync);
13795 tg3_halt(tp, RESET_KIND_SUSPEND, 1);
13796 err = tg3_nvram_lock(tp);
13797 tg3_halt_cpu(tp, RX_CPU_BASE);
13798 if (!tg3_flag(tp, 5705_PLUS))
13799 tg3_halt_cpu(tp, TX_CPU_BASE);
13801 tg3_nvram_unlock(tp);
13803 if (tp->phy_flags & TG3_PHYFLG_MII_SERDES)
13806 if (tg3_test_registers(tp) != 0) {
13807 etest->flags |= ETH_TEST_FL_FAILED;
13808 data[TG3_REGISTER_TEST] = 1;
13811 if (tg3_test_memory(tp) != 0) {
13812 etest->flags |= ETH_TEST_FL_FAILED;
13813 data[TG3_MEMORY_TEST] = 1;
13817 etest->flags |= ETH_TEST_FL_EXTERNAL_LB_DONE;
13819 if (tg3_test_loopback(tp, data, doextlpbk))
13820 etest->flags |= ETH_TEST_FL_FAILED;
13822 tg3_full_unlock(tp);
13824 if (tg3_test_interrupt(tp) != 0) {
13825 etest->flags |= ETH_TEST_FL_FAILED;
13826 data[TG3_INTERRUPT_TEST] = 1;
13829 tg3_full_lock(tp, 0);
13831 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
13832 if (netif_running(dev)) {
13833 tg3_flag_set(tp, INIT_COMPLETE);
13834 err2 = tg3_restart_hw(tp, true);
13836 tg3_netif_start(tp);
13839 tg3_full_unlock(tp);
13841 if (irq_sync && !err2)
13844 if (tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER)
13845 tg3_power_down_prepare(tp);
13849 static int tg3_hwtstamp_set(struct net_device *dev, struct ifreq *ifr)
13851 struct tg3 *tp = netdev_priv(dev);
13852 struct hwtstamp_config stmpconf;
13854 if (!tg3_flag(tp, PTP_CAPABLE))
13855 return -EOPNOTSUPP;
13857 if (copy_from_user(&stmpconf, ifr->ifr_data, sizeof(stmpconf)))
13860 if (stmpconf.flags)
13863 if (stmpconf.tx_type != HWTSTAMP_TX_ON &&
13864 stmpconf.tx_type != HWTSTAMP_TX_OFF)
13867 switch (stmpconf.rx_filter) {
13868 case HWTSTAMP_FILTER_NONE:
13871 case HWTSTAMP_FILTER_PTP_V1_L4_EVENT:
13872 tp->rxptpctl = TG3_RX_PTP_CTL_RX_PTP_V1_EN |
13873 TG3_RX_PTP_CTL_ALL_V1_EVENTS;
13875 case HWTSTAMP_FILTER_PTP_V1_L4_SYNC:
13876 tp->rxptpctl = TG3_RX_PTP_CTL_RX_PTP_V1_EN |
13877 TG3_RX_PTP_CTL_SYNC_EVNT;
13879 case HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ:
13880 tp->rxptpctl = TG3_RX_PTP_CTL_RX_PTP_V1_EN |
13881 TG3_RX_PTP_CTL_DELAY_REQ;
13883 case HWTSTAMP_FILTER_PTP_V2_EVENT:
13884 tp->rxptpctl = TG3_RX_PTP_CTL_RX_PTP_V2_EN |
13885 TG3_RX_PTP_CTL_ALL_V2_EVENTS;
13887 case HWTSTAMP_FILTER_PTP_V2_L2_EVENT:
13888 tp->rxptpctl = TG3_RX_PTP_CTL_RX_PTP_V2_L2_EN |
13889 TG3_RX_PTP_CTL_ALL_V2_EVENTS;
13891 case HWTSTAMP_FILTER_PTP_V2_L4_EVENT:
13892 tp->rxptpctl = TG3_RX_PTP_CTL_RX_PTP_V2_L4_EN |
13893 TG3_RX_PTP_CTL_ALL_V2_EVENTS;
13895 case HWTSTAMP_FILTER_PTP_V2_SYNC:
13896 tp->rxptpctl = TG3_RX_PTP_CTL_RX_PTP_V2_EN |
13897 TG3_RX_PTP_CTL_SYNC_EVNT;
13899 case HWTSTAMP_FILTER_PTP_V2_L2_SYNC:
13900 tp->rxptpctl = TG3_RX_PTP_CTL_RX_PTP_V2_L2_EN |
13901 TG3_RX_PTP_CTL_SYNC_EVNT;
13903 case HWTSTAMP_FILTER_PTP_V2_L4_SYNC:
13904 tp->rxptpctl = TG3_RX_PTP_CTL_RX_PTP_V2_L4_EN |
13905 TG3_RX_PTP_CTL_SYNC_EVNT;
13907 case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ:
13908 tp->rxptpctl = TG3_RX_PTP_CTL_RX_PTP_V2_EN |
13909 TG3_RX_PTP_CTL_DELAY_REQ;
13911 case HWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ:
13912 tp->rxptpctl = TG3_RX_PTP_CTL_RX_PTP_V2_L2_EN |
13913 TG3_RX_PTP_CTL_DELAY_REQ;
13915 case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ:
13916 tp->rxptpctl = TG3_RX_PTP_CTL_RX_PTP_V2_L4_EN |
13917 TG3_RX_PTP_CTL_DELAY_REQ;
13923 if (netif_running(dev) && tp->rxptpctl)
13924 tw32(TG3_RX_PTP_CTL,
13925 tp->rxptpctl | TG3_RX_PTP_CTL_HWTS_INTERLOCK);
13927 if (stmpconf.tx_type == HWTSTAMP_TX_ON)
13928 tg3_flag_set(tp, TX_TSTAMP_EN);
13930 tg3_flag_clear(tp, TX_TSTAMP_EN);
13932 return copy_to_user(ifr->ifr_data, &stmpconf, sizeof(stmpconf)) ?
13936 static int tg3_hwtstamp_get(struct net_device *dev, struct ifreq *ifr)
13938 struct tg3 *tp = netdev_priv(dev);
13939 struct hwtstamp_config stmpconf;
13941 if (!tg3_flag(tp, PTP_CAPABLE))
13942 return -EOPNOTSUPP;
13944 stmpconf.flags = 0;
13945 stmpconf.tx_type = (tg3_flag(tp, TX_TSTAMP_EN) ?
13946 HWTSTAMP_TX_ON : HWTSTAMP_TX_OFF);
13948 switch (tp->rxptpctl) {
13950 stmpconf.rx_filter = HWTSTAMP_FILTER_NONE;
13952 case TG3_RX_PTP_CTL_RX_PTP_V1_EN | TG3_RX_PTP_CTL_ALL_V1_EVENTS:
13953 stmpconf.rx_filter = HWTSTAMP_FILTER_PTP_V1_L4_EVENT;
13955 case TG3_RX_PTP_CTL_RX_PTP_V1_EN | TG3_RX_PTP_CTL_SYNC_EVNT:
13956 stmpconf.rx_filter = HWTSTAMP_FILTER_PTP_V1_L4_SYNC;
13958 case TG3_RX_PTP_CTL_RX_PTP_V1_EN | TG3_RX_PTP_CTL_DELAY_REQ:
13959 stmpconf.rx_filter = HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ;
13961 case TG3_RX_PTP_CTL_RX_PTP_V2_EN | TG3_RX_PTP_CTL_ALL_V2_EVENTS:
13962 stmpconf.rx_filter = HWTSTAMP_FILTER_PTP_V2_EVENT;
13964 case TG3_RX_PTP_CTL_RX_PTP_V2_L2_EN | TG3_RX_PTP_CTL_ALL_V2_EVENTS:
13965 stmpconf.rx_filter = HWTSTAMP_FILTER_PTP_V2_L2_EVENT;
13967 case TG3_RX_PTP_CTL_RX_PTP_V2_L4_EN | TG3_RX_PTP_CTL_ALL_V2_EVENTS:
13968 stmpconf.rx_filter = HWTSTAMP_FILTER_PTP_V2_L4_EVENT;
13970 case TG3_RX_PTP_CTL_RX_PTP_V2_EN | TG3_RX_PTP_CTL_SYNC_EVNT:
13971 stmpconf.rx_filter = HWTSTAMP_FILTER_PTP_V2_SYNC;
13973 case TG3_RX_PTP_CTL_RX_PTP_V2_L2_EN | TG3_RX_PTP_CTL_SYNC_EVNT:
13974 stmpconf.rx_filter = HWTSTAMP_FILTER_PTP_V2_L2_SYNC;
13976 case TG3_RX_PTP_CTL_RX_PTP_V2_L4_EN | TG3_RX_PTP_CTL_SYNC_EVNT:
13977 stmpconf.rx_filter = HWTSTAMP_FILTER_PTP_V2_L4_SYNC;
13979 case TG3_RX_PTP_CTL_RX_PTP_V2_EN | TG3_RX_PTP_CTL_DELAY_REQ:
13980 stmpconf.rx_filter = HWTSTAMP_FILTER_PTP_V2_DELAY_REQ;
13982 case TG3_RX_PTP_CTL_RX_PTP_V2_L2_EN | TG3_RX_PTP_CTL_DELAY_REQ:
13983 stmpconf.rx_filter = HWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ;
13985 case TG3_RX_PTP_CTL_RX_PTP_V2_L4_EN | TG3_RX_PTP_CTL_DELAY_REQ:
13986 stmpconf.rx_filter = HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ;
13993 return copy_to_user(ifr->ifr_data, &stmpconf, sizeof(stmpconf)) ?
13997 static int tg3_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
13999 struct mii_ioctl_data *data = if_mii(ifr);
14000 struct tg3 *tp = netdev_priv(dev);
14003 if (tg3_flag(tp, USE_PHYLIB)) {
14004 struct phy_device *phydev;
14005 if (!(tp->phy_flags & TG3_PHYFLG_IS_CONNECTED))
14007 phydev = mdiobus_get_phy(tp->mdio_bus, tp->phy_addr);
14008 return phy_mii_ioctl(phydev, ifr, cmd);
14013 data->phy_id = tp->phy_addr;
14016 case SIOCGMIIREG: {
14019 if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES)
14020 break; /* We have no PHY */
14022 if (!netif_running(dev))
14025 spin_lock_bh(&tp->lock);
14026 err = __tg3_readphy(tp, data->phy_id & 0x1f,
14027 data->reg_num & 0x1f, &mii_regval);
14028 spin_unlock_bh(&tp->lock);
14030 data->val_out = mii_regval;
14036 if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES)
14037 break; /* We have no PHY */
14039 if (!netif_running(dev))
14042 spin_lock_bh(&tp->lock);
14043 err = __tg3_writephy(tp, data->phy_id & 0x1f,
14044 data->reg_num & 0x1f, data->val_in);
14045 spin_unlock_bh(&tp->lock);
14049 case SIOCSHWTSTAMP:
14050 return tg3_hwtstamp_set(dev, ifr);
14052 case SIOCGHWTSTAMP:
14053 return tg3_hwtstamp_get(dev, ifr);
14059 return -EOPNOTSUPP;
14062 static int tg3_get_coalesce(struct net_device *dev, struct ethtool_coalesce *ec)
14064 struct tg3 *tp = netdev_priv(dev);
14066 memcpy(ec, &tp->coal, sizeof(*ec));
14070 static int tg3_set_coalesce(struct net_device *dev, struct ethtool_coalesce *ec)
14072 struct tg3 *tp = netdev_priv(dev);
14073 u32 max_rxcoal_tick_int = 0, max_txcoal_tick_int = 0;
14074 u32 max_stat_coal_ticks = 0, min_stat_coal_ticks = 0;
14076 if (!tg3_flag(tp, 5705_PLUS)) {
14077 max_rxcoal_tick_int = MAX_RXCOAL_TICK_INT;
14078 max_txcoal_tick_int = MAX_TXCOAL_TICK_INT;
14079 max_stat_coal_ticks = MAX_STAT_COAL_TICKS;
14080 min_stat_coal_ticks = MIN_STAT_COAL_TICKS;
14083 if ((ec->rx_coalesce_usecs > MAX_RXCOL_TICKS) ||
14084 (!ec->rx_coalesce_usecs) ||
14085 (ec->tx_coalesce_usecs > MAX_TXCOL_TICKS) ||
14086 (!ec->tx_coalesce_usecs) ||
14087 (ec->rx_max_coalesced_frames > MAX_RXMAX_FRAMES) ||
14088 (ec->tx_max_coalesced_frames > MAX_TXMAX_FRAMES) ||
14089 (ec->rx_coalesce_usecs_irq > max_rxcoal_tick_int) ||
14090 (ec->tx_coalesce_usecs_irq > max_txcoal_tick_int) ||
14091 (ec->rx_max_coalesced_frames_irq > MAX_RXCOAL_MAXF_INT) ||
14092 (ec->tx_max_coalesced_frames_irq > MAX_TXCOAL_MAXF_INT) ||
14093 (ec->stats_block_coalesce_usecs > max_stat_coal_ticks) ||
14094 (ec->stats_block_coalesce_usecs < min_stat_coal_ticks))
14097 /* Only copy relevant parameters, ignore all others. */
14098 tp->coal.rx_coalesce_usecs = ec->rx_coalesce_usecs;
14099 tp->coal.tx_coalesce_usecs = ec->tx_coalesce_usecs;
14100 tp->coal.rx_max_coalesced_frames = ec->rx_max_coalesced_frames;
14101 tp->coal.tx_max_coalesced_frames = ec->tx_max_coalesced_frames;
14102 tp->coal.rx_coalesce_usecs_irq = ec->rx_coalesce_usecs_irq;
14103 tp->coal.tx_coalesce_usecs_irq = ec->tx_coalesce_usecs_irq;
14104 tp->coal.rx_max_coalesced_frames_irq = ec->rx_max_coalesced_frames_irq;
14105 tp->coal.tx_max_coalesced_frames_irq = ec->tx_max_coalesced_frames_irq;
14106 tp->coal.stats_block_coalesce_usecs = ec->stats_block_coalesce_usecs;
14108 if (netif_running(dev)) {
14109 tg3_full_lock(tp, 0);
14110 __tg3_set_coalesce(tp, &tp->coal);
14111 tg3_full_unlock(tp);
14116 static int tg3_set_eee(struct net_device *dev, struct ethtool_eee *edata)
14118 struct tg3 *tp = netdev_priv(dev);
14120 if (!(tp->phy_flags & TG3_PHYFLG_EEE_CAP)) {
14121 netdev_warn(tp->dev, "Board does not support EEE!\n");
14122 return -EOPNOTSUPP;
14125 if (edata->advertised != tp->eee.advertised) {
14126 netdev_warn(tp->dev,
14127 "Direct manipulation of EEE advertisement is not supported\n");
14131 if (edata->tx_lpi_timer > TG3_CPMU_DBTMR1_LNKIDLE_MAX) {
14132 netdev_warn(tp->dev,
14133 "Maximal Tx Lpi timer supported is %#x(u)\n",
14134 TG3_CPMU_DBTMR1_LNKIDLE_MAX);
14140 tp->phy_flags |= TG3_PHYFLG_USER_CONFIGURED;
14141 tg3_warn_mgmt_link_flap(tp);
14143 if (netif_running(tp->dev)) {
14144 tg3_full_lock(tp, 0);
14147 tg3_full_unlock(tp);
14153 static int tg3_get_eee(struct net_device *dev, struct ethtool_eee *edata)
14155 struct tg3 *tp = netdev_priv(dev);
14157 if (!(tp->phy_flags & TG3_PHYFLG_EEE_CAP)) {
14158 netdev_warn(tp->dev,
14159 "Board does not support EEE!\n");
14160 return -EOPNOTSUPP;
14167 static const struct ethtool_ops tg3_ethtool_ops = {
14168 .get_drvinfo = tg3_get_drvinfo,
14169 .get_regs_len = tg3_get_regs_len,
14170 .get_regs = tg3_get_regs,
14171 .get_wol = tg3_get_wol,
14172 .set_wol = tg3_set_wol,
14173 .get_msglevel = tg3_get_msglevel,
14174 .set_msglevel = tg3_set_msglevel,
14175 .nway_reset = tg3_nway_reset,
14176 .get_link = ethtool_op_get_link,
14177 .get_eeprom_len = tg3_get_eeprom_len,
14178 .get_eeprom = tg3_get_eeprom,
14179 .set_eeprom = tg3_set_eeprom,
14180 .get_ringparam = tg3_get_ringparam,
14181 .set_ringparam = tg3_set_ringparam,
14182 .get_pauseparam = tg3_get_pauseparam,
14183 .set_pauseparam = tg3_set_pauseparam,
14184 .self_test = tg3_self_test,
14185 .get_strings = tg3_get_strings,
14186 .set_phys_id = tg3_set_phys_id,
14187 .get_ethtool_stats = tg3_get_ethtool_stats,
14188 .get_coalesce = tg3_get_coalesce,
14189 .set_coalesce = tg3_set_coalesce,
14190 .get_sset_count = tg3_get_sset_count,
14191 .get_rxnfc = tg3_get_rxnfc,
14192 .get_rxfh_indir_size = tg3_get_rxfh_indir_size,
14193 .get_rxfh = tg3_get_rxfh,
14194 .set_rxfh = tg3_set_rxfh,
14195 .get_channels = tg3_get_channels,
14196 .set_channels = tg3_set_channels,
14197 .get_ts_info = tg3_get_ts_info,
14198 .get_eee = tg3_get_eee,
14199 .set_eee = tg3_set_eee,
14200 .get_link_ksettings = tg3_get_link_ksettings,
14201 .set_link_ksettings = tg3_set_link_ksettings,
14204 static void tg3_get_stats64(struct net_device *dev,
14205 struct rtnl_link_stats64 *stats)
14207 struct tg3 *tp = netdev_priv(dev);
14209 spin_lock_bh(&tp->lock);
14210 if (!tp->hw_stats || !tg3_flag(tp, INIT_COMPLETE)) {
14211 *stats = tp->net_stats_prev;
14212 spin_unlock_bh(&tp->lock);
14216 tg3_get_nstats(tp, stats);
14217 spin_unlock_bh(&tp->lock);
14220 static void tg3_set_rx_mode(struct net_device *dev)
14222 struct tg3 *tp = netdev_priv(dev);
14224 if (!netif_running(dev))
14227 tg3_full_lock(tp, 0);
14228 __tg3_set_rx_mode(dev);
14229 tg3_full_unlock(tp);
14232 static inline void tg3_set_mtu(struct net_device *dev, struct tg3 *tp,
14235 dev->mtu = new_mtu;
14237 if (new_mtu > ETH_DATA_LEN) {
14238 if (tg3_flag(tp, 5780_CLASS)) {
14239 netdev_update_features(dev);
14240 tg3_flag_clear(tp, TSO_CAPABLE);
14242 tg3_flag_set(tp, JUMBO_RING_ENABLE);
14245 if (tg3_flag(tp, 5780_CLASS)) {
14246 tg3_flag_set(tp, TSO_CAPABLE);
14247 netdev_update_features(dev);
14249 tg3_flag_clear(tp, JUMBO_RING_ENABLE);
14253 static int tg3_change_mtu(struct net_device *dev, int new_mtu)
14255 struct tg3 *tp = netdev_priv(dev);
14257 bool reset_phy = false;
14259 if (!netif_running(dev)) {
14260 /* We'll just catch it later when the
14263 tg3_set_mtu(dev, tp, new_mtu);
14269 tg3_netif_stop(tp);
14271 tg3_set_mtu(dev, tp, new_mtu);
14273 tg3_full_lock(tp, 1);
14275 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
14277 /* Reset PHY, otherwise the read DMA engine will be in a mode that
14278 * breaks all requests to 256 bytes.
14280 if (tg3_asic_rev(tp) == ASIC_REV_57766 ||
14281 tg3_asic_rev(tp) == ASIC_REV_5717 ||
14282 tg3_asic_rev(tp) == ASIC_REV_5719 ||
14283 tg3_asic_rev(tp) == ASIC_REV_5720)
14286 err = tg3_restart_hw(tp, reset_phy);
14289 tg3_netif_start(tp);
14291 tg3_full_unlock(tp);
14299 static const struct net_device_ops tg3_netdev_ops = {
14300 .ndo_open = tg3_open,
14301 .ndo_stop = tg3_close,
14302 .ndo_start_xmit = tg3_start_xmit,
14303 .ndo_get_stats64 = tg3_get_stats64,
14304 .ndo_validate_addr = eth_validate_addr,
14305 .ndo_set_rx_mode = tg3_set_rx_mode,
14306 .ndo_set_mac_address = tg3_set_mac_addr,
14307 .ndo_do_ioctl = tg3_ioctl,
14308 .ndo_tx_timeout = tg3_tx_timeout,
14309 .ndo_change_mtu = tg3_change_mtu,
14310 .ndo_fix_features = tg3_fix_features,
14311 .ndo_set_features = tg3_set_features,
14312 #ifdef CONFIG_NET_POLL_CONTROLLER
14313 .ndo_poll_controller = tg3_poll_controller,
14317 static void tg3_get_eeprom_size(struct tg3 *tp)
14319 u32 cursize, val, magic;
14321 tp->nvram_size = EEPROM_CHIP_SIZE;
14323 if (tg3_nvram_read(tp, 0, &magic) != 0)
14326 if ((magic != TG3_EEPROM_MAGIC) &&
14327 ((magic & TG3_EEPROM_MAGIC_FW_MSK) != TG3_EEPROM_MAGIC_FW) &&
14328 ((magic & TG3_EEPROM_MAGIC_HW_MSK) != TG3_EEPROM_MAGIC_HW))
14332 * Size the chip by reading offsets at increasing powers of two.
14333 * When we encounter our validation signature, we know the addressing
14334 * has wrapped around, and thus have our chip size.
14338 while (cursize < tp->nvram_size) {
14339 if (tg3_nvram_read(tp, cursize, &val) != 0)
14348 tp->nvram_size = cursize;
14351 static void tg3_get_nvram_size(struct tg3 *tp)
14355 if (tg3_flag(tp, NO_NVRAM) || tg3_nvram_read(tp, 0, &val) != 0)
14358 /* Selfboot format */
14359 if (val != TG3_EEPROM_MAGIC) {
14360 tg3_get_eeprom_size(tp);
14364 if (tg3_nvram_read(tp, 0xf0, &val) == 0) {
14366 /* This is confusing. We want to operate on the
14367 * 16-bit value at offset 0xf2. The tg3_nvram_read()
14368 * call will read from NVRAM and byteswap the data
14369 * according to the byteswapping settings for all
14370 * other register accesses. This ensures the data we
14371 * want will always reside in the lower 16-bits.
14372 * However, the data in NVRAM is in LE format, which
14373 * means the data from the NVRAM read will always be
14374 * opposite the endianness of the CPU. The 16-bit
14375 * byteswap then brings the data to CPU endianness.
14377 tp->nvram_size = swab16((u16)(val & 0x0000ffff)) * 1024;
14381 tp->nvram_size = TG3_NVRAM_SIZE_512KB;
14384 static void tg3_get_nvram_info(struct tg3 *tp)
14388 nvcfg1 = tr32(NVRAM_CFG1);
14389 if (nvcfg1 & NVRAM_CFG1_FLASHIF_ENAB) {
14390 tg3_flag_set(tp, FLASH);
14392 nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
14393 tw32(NVRAM_CFG1, nvcfg1);
14396 if (tg3_asic_rev(tp) == ASIC_REV_5750 ||
14397 tg3_flag(tp, 5780_CLASS)) {
14398 switch (nvcfg1 & NVRAM_CFG1_VENDOR_MASK) {
14399 case FLASH_VENDOR_ATMEL_FLASH_BUFFERED:
14400 tp->nvram_jedecnum = JEDEC_ATMEL;
14401 tp->nvram_pagesize = ATMEL_AT45DB0X1B_PAGE_SIZE;
14402 tg3_flag_set(tp, NVRAM_BUFFERED);
14404 case FLASH_VENDOR_ATMEL_FLASH_UNBUFFERED:
14405 tp->nvram_jedecnum = JEDEC_ATMEL;
14406 tp->nvram_pagesize = ATMEL_AT25F512_PAGE_SIZE;
14408 case FLASH_VENDOR_ATMEL_EEPROM:
14409 tp->nvram_jedecnum = JEDEC_ATMEL;
14410 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
14411 tg3_flag_set(tp, NVRAM_BUFFERED);
14413 case FLASH_VENDOR_ST:
14414 tp->nvram_jedecnum = JEDEC_ST;
14415 tp->nvram_pagesize = ST_M45PEX0_PAGE_SIZE;
14416 tg3_flag_set(tp, NVRAM_BUFFERED);
14418 case FLASH_VENDOR_SAIFUN:
14419 tp->nvram_jedecnum = JEDEC_SAIFUN;
14420 tp->nvram_pagesize = SAIFUN_SA25F0XX_PAGE_SIZE;
14422 case FLASH_VENDOR_SST_SMALL:
14423 case FLASH_VENDOR_SST_LARGE:
14424 tp->nvram_jedecnum = JEDEC_SST;
14425 tp->nvram_pagesize = SST_25VF0X0_PAGE_SIZE;
14429 tp->nvram_jedecnum = JEDEC_ATMEL;
14430 tp->nvram_pagesize = ATMEL_AT45DB0X1B_PAGE_SIZE;
14431 tg3_flag_set(tp, NVRAM_BUFFERED);
14435 static void tg3_nvram_get_pagesize(struct tg3 *tp, u32 nvmcfg1)
14437 switch (nvmcfg1 & NVRAM_CFG1_5752PAGE_SIZE_MASK) {
14438 case FLASH_5752PAGE_SIZE_256:
14439 tp->nvram_pagesize = 256;
14441 case FLASH_5752PAGE_SIZE_512:
14442 tp->nvram_pagesize = 512;
14444 case FLASH_5752PAGE_SIZE_1K:
14445 tp->nvram_pagesize = 1024;
14447 case FLASH_5752PAGE_SIZE_2K:
14448 tp->nvram_pagesize = 2048;
14450 case FLASH_5752PAGE_SIZE_4K:
14451 tp->nvram_pagesize = 4096;
14453 case FLASH_5752PAGE_SIZE_264:
14454 tp->nvram_pagesize = 264;
14456 case FLASH_5752PAGE_SIZE_528:
14457 tp->nvram_pagesize = 528;
14462 static void tg3_get_5752_nvram_info(struct tg3 *tp)
14466 nvcfg1 = tr32(NVRAM_CFG1);
14468 /* NVRAM protection for TPM */
14469 if (nvcfg1 & (1 << 27))
14470 tg3_flag_set(tp, PROTECTED_NVRAM);
14472 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
14473 case FLASH_5752VENDOR_ATMEL_EEPROM_64KHZ:
14474 case FLASH_5752VENDOR_ATMEL_EEPROM_376KHZ:
14475 tp->nvram_jedecnum = JEDEC_ATMEL;
14476 tg3_flag_set(tp, NVRAM_BUFFERED);
14478 case FLASH_5752VENDOR_ATMEL_FLASH_BUFFERED:
14479 tp->nvram_jedecnum = JEDEC_ATMEL;
14480 tg3_flag_set(tp, NVRAM_BUFFERED);
14481 tg3_flag_set(tp, FLASH);
14483 case FLASH_5752VENDOR_ST_M45PE10:
14484 case FLASH_5752VENDOR_ST_M45PE20:
14485 case FLASH_5752VENDOR_ST_M45PE40:
14486 tp->nvram_jedecnum = JEDEC_ST;
14487 tg3_flag_set(tp, NVRAM_BUFFERED);
14488 tg3_flag_set(tp, FLASH);
14492 if (tg3_flag(tp, FLASH)) {
14493 tg3_nvram_get_pagesize(tp, nvcfg1);
14495 /* For eeprom, set pagesize to maximum eeprom size */
14496 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
14498 nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
14499 tw32(NVRAM_CFG1, nvcfg1);
14503 static void tg3_get_5755_nvram_info(struct tg3 *tp)
14505 u32 nvcfg1, protect = 0;
14507 nvcfg1 = tr32(NVRAM_CFG1);
14509 /* NVRAM protection for TPM */
14510 if (nvcfg1 & (1 << 27)) {
14511 tg3_flag_set(tp, PROTECTED_NVRAM);
14515 nvcfg1 &= NVRAM_CFG1_5752VENDOR_MASK;
14517 case FLASH_5755VENDOR_ATMEL_FLASH_1:
14518 case FLASH_5755VENDOR_ATMEL_FLASH_2:
14519 case FLASH_5755VENDOR_ATMEL_FLASH_3:
14520 case FLASH_5755VENDOR_ATMEL_FLASH_5:
14521 tp->nvram_jedecnum = JEDEC_ATMEL;
14522 tg3_flag_set(tp, NVRAM_BUFFERED);
14523 tg3_flag_set(tp, FLASH);
14524 tp->nvram_pagesize = 264;
14525 if (nvcfg1 == FLASH_5755VENDOR_ATMEL_FLASH_1 ||
14526 nvcfg1 == FLASH_5755VENDOR_ATMEL_FLASH_5)
14527 tp->nvram_size = (protect ? 0x3e200 :
14528 TG3_NVRAM_SIZE_512KB);
14529 else if (nvcfg1 == FLASH_5755VENDOR_ATMEL_FLASH_2)
14530 tp->nvram_size = (protect ? 0x1f200 :
14531 TG3_NVRAM_SIZE_256KB);
14533 tp->nvram_size = (protect ? 0x1f200 :
14534 TG3_NVRAM_SIZE_128KB);
14536 case FLASH_5752VENDOR_ST_M45PE10:
14537 case FLASH_5752VENDOR_ST_M45PE20:
14538 case FLASH_5752VENDOR_ST_M45PE40:
14539 tp->nvram_jedecnum = JEDEC_ST;
14540 tg3_flag_set(tp, NVRAM_BUFFERED);
14541 tg3_flag_set(tp, FLASH);
14542 tp->nvram_pagesize = 256;
14543 if (nvcfg1 == FLASH_5752VENDOR_ST_M45PE10)
14544 tp->nvram_size = (protect ?
14545 TG3_NVRAM_SIZE_64KB :
14546 TG3_NVRAM_SIZE_128KB);
14547 else if (nvcfg1 == FLASH_5752VENDOR_ST_M45PE20)
14548 tp->nvram_size = (protect ?
14549 TG3_NVRAM_SIZE_64KB :
14550 TG3_NVRAM_SIZE_256KB);
14552 tp->nvram_size = (protect ?
14553 TG3_NVRAM_SIZE_128KB :
14554 TG3_NVRAM_SIZE_512KB);
14559 static void tg3_get_5787_nvram_info(struct tg3 *tp)
14563 nvcfg1 = tr32(NVRAM_CFG1);
14565 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
14566 case FLASH_5787VENDOR_ATMEL_EEPROM_64KHZ:
14567 case FLASH_5787VENDOR_ATMEL_EEPROM_376KHZ:
14568 case FLASH_5787VENDOR_MICRO_EEPROM_64KHZ:
14569 case FLASH_5787VENDOR_MICRO_EEPROM_376KHZ:
14570 tp->nvram_jedecnum = JEDEC_ATMEL;
14571 tg3_flag_set(tp, NVRAM_BUFFERED);
14572 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
14574 nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
14575 tw32(NVRAM_CFG1, nvcfg1);
14577 case FLASH_5752VENDOR_ATMEL_FLASH_BUFFERED:
14578 case FLASH_5755VENDOR_ATMEL_FLASH_1:
14579 case FLASH_5755VENDOR_ATMEL_FLASH_2:
14580 case FLASH_5755VENDOR_ATMEL_FLASH_3:
14581 tp->nvram_jedecnum = JEDEC_ATMEL;
14582 tg3_flag_set(tp, NVRAM_BUFFERED);
14583 tg3_flag_set(tp, FLASH);
14584 tp->nvram_pagesize = 264;
14586 case FLASH_5752VENDOR_ST_M45PE10:
14587 case FLASH_5752VENDOR_ST_M45PE20:
14588 case FLASH_5752VENDOR_ST_M45PE40:
14589 tp->nvram_jedecnum = JEDEC_ST;
14590 tg3_flag_set(tp, NVRAM_BUFFERED);
14591 tg3_flag_set(tp, FLASH);
14592 tp->nvram_pagesize = 256;
14597 static void tg3_get_5761_nvram_info(struct tg3 *tp)
14599 u32 nvcfg1, protect = 0;
14601 nvcfg1 = tr32(NVRAM_CFG1);
14603 /* NVRAM protection for TPM */
14604 if (nvcfg1 & (1 << 27)) {
14605 tg3_flag_set(tp, PROTECTED_NVRAM);
14609 nvcfg1 &= NVRAM_CFG1_5752VENDOR_MASK;
14611 case FLASH_5761VENDOR_ATMEL_ADB021D:
14612 case FLASH_5761VENDOR_ATMEL_ADB041D:
14613 case FLASH_5761VENDOR_ATMEL_ADB081D:
14614 case FLASH_5761VENDOR_ATMEL_ADB161D:
14615 case FLASH_5761VENDOR_ATMEL_MDB021D:
14616 case FLASH_5761VENDOR_ATMEL_MDB041D:
14617 case FLASH_5761VENDOR_ATMEL_MDB081D:
14618 case FLASH_5761VENDOR_ATMEL_MDB161D:
14619 tp->nvram_jedecnum = JEDEC_ATMEL;
14620 tg3_flag_set(tp, NVRAM_BUFFERED);
14621 tg3_flag_set(tp, FLASH);
14622 tg3_flag_set(tp, NO_NVRAM_ADDR_TRANS);
14623 tp->nvram_pagesize = 256;
14625 case FLASH_5761VENDOR_ST_A_M45PE20:
14626 case FLASH_5761VENDOR_ST_A_M45PE40:
14627 case FLASH_5761VENDOR_ST_A_M45PE80:
14628 case FLASH_5761VENDOR_ST_A_M45PE16:
14629 case FLASH_5761VENDOR_ST_M_M45PE20:
14630 case FLASH_5761VENDOR_ST_M_M45PE40:
14631 case FLASH_5761VENDOR_ST_M_M45PE80:
14632 case FLASH_5761VENDOR_ST_M_M45PE16:
14633 tp->nvram_jedecnum = JEDEC_ST;
14634 tg3_flag_set(tp, NVRAM_BUFFERED);
14635 tg3_flag_set(tp, FLASH);
14636 tp->nvram_pagesize = 256;
14641 tp->nvram_size = tr32(NVRAM_ADDR_LOCKOUT);
14644 case FLASH_5761VENDOR_ATMEL_ADB161D:
14645 case FLASH_5761VENDOR_ATMEL_MDB161D:
14646 case FLASH_5761VENDOR_ST_A_M45PE16:
14647 case FLASH_5761VENDOR_ST_M_M45PE16:
14648 tp->nvram_size = TG3_NVRAM_SIZE_2MB;
14650 case FLASH_5761VENDOR_ATMEL_ADB081D:
14651 case FLASH_5761VENDOR_ATMEL_MDB081D:
14652 case FLASH_5761VENDOR_ST_A_M45PE80:
14653 case FLASH_5761VENDOR_ST_M_M45PE80:
14654 tp->nvram_size = TG3_NVRAM_SIZE_1MB;
14656 case FLASH_5761VENDOR_ATMEL_ADB041D:
14657 case FLASH_5761VENDOR_ATMEL_MDB041D:
14658 case FLASH_5761VENDOR_ST_A_M45PE40:
14659 case FLASH_5761VENDOR_ST_M_M45PE40:
14660 tp->nvram_size = TG3_NVRAM_SIZE_512KB;
14662 case FLASH_5761VENDOR_ATMEL_ADB021D:
14663 case FLASH_5761VENDOR_ATMEL_MDB021D:
14664 case FLASH_5761VENDOR_ST_A_M45PE20:
14665 case FLASH_5761VENDOR_ST_M_M45PE20:
14666 tp->nvram_size = TG3_NVRAM_SIZE_256KB;
14672 static void tg3_get_5906_nvram_info(struct tg3 *tp)
14674 tp->nvram_jedecnum = JEDEC_ATMEL;
14675 tg3_flag_set(tp, NVRAM_BUFFERED);
14676 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
14679 static void tg3_get_57780_nvram_info(struct tg3 *tp)
14683 nvcfg1 = tr32(NVRAM_CFG1);
14685 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
14686 case FLASH_5787VENDOR_ATMEL_EEPROM_376KHZ:
14687 case FLASH_5787VENDOR_MICRO_EEPROM_376KHZ:
14688 tp->nvram_jedecnum = JEDEC_ATMEL;
14689 tg3_flag_set(tp, NVRAM_BUFFERED);
14690 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
14692 nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
14693 tw32(NVRAM_CFG1, nvcfg1);
14695 case FLASH_5752VENDOR_ATMEL_FLASH_BUFFERED:
14696 case FLASH_57780VENDOR_ATMEL_AT45DB011D:
14697 case FLASH_57780VENDOR_ATMEL_AT45DB011B:
14698 case FLASH_57780VENDOR_ATMEL_AT45DB021D:
14699 case FLASH_57780VENDOR_ATMEL_AT45DB021B:
14700 case FLASH_57780VENDOR_ATMEL_AT45DB041D:
14701 case FLASH_57780VENDOR_ATMEL_AT45DB041B:
14702 tp->nvram_jedecnum = JEDEC_ATMEL;
14703 tg3_flag_set(tp, NVRAM_BUFFERED);
14704 tg3_flag_set(tp, FLASH);
14706 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
14707 case FLASH_5752VENDOR_ATMEL_FLASH_BUFFERED:
14708 case FLASH_57780VENDOR_ATMEL_AT45DB011D:
14709 case FLASH_57780VENDOR_ATMEL_AT45DB011B:
14710 tp->nvram_size = TG3_NVRAM_SIZE_128KB;
14712 case FLASH_57780VENDOR_ATMEL_AT45DB021D:
14713 case FLASH_57780VENDOR_ATMEL_AT45DB021B:
14714 tp->nvram_size = TG3_NVRAM_SIZE_256KB;
14716 case FLASH_57780VENDOR_ATMEL_AT45DB041D:
14717 case FLASH_57780VENDOR_ATMEL_AT45DB041B:
14718 tp->nvram_size = TG3_NVRAM_SIZE_512KB;
14722 case FLASH_5752VENDOR_ST_M45PE10:
14723 case FLASH_5752VENDOR_ST_M45PE20:
14724 case FLASH_5752VENDOR_ST_M45PE40:
14725 tp->nvram_jedecnum = JEDEC_ST;
14726 tg3_flag_set(tp, NVRAM_BUFFERED);
14727 tg3_flag_set(tp, FLASH);
14729 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
14730 case FLASH_5752VENDOR_ST_M45PE10:
14731 tp->nvram_size = TG3_NVRAM_SIZE_128KB;
14733 case FLASH_5752VENDOR_ST_M45PE20:
14734 tp->nvram_size = TG3_NVRAM_SIZE_256KB;
14736 case FLASH_5752VENDOR_ST_M45PE40:
14737 tp->nvram_size = TG3_NVRAM_SIZE_512KB;
14742 tg3_flag_set(tp, NO_NVRAM);
14746 tg3_nvram_get_pagesize(tp, nvcfg1);
14747 if (tp->nvram_pagesize != 264 && tp->nvram_pagesize != 528)
14748 tg3_flag_set(tp, NO_NVRAM_ADDR_TRANS);
14752 static void tg3_get_5717_nvram_info(struct tg3 *tp)
14756 nvcfg1 = tr32(NVRAM_CFG1);
14758 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
14759 case FLASH_5717VENDOR_ATMEL_EEPROM:
14760 case FLASH_5717VENDOR_MICRO_EEPROM:
14761 tp->nvram_jedecnum = JEDEC_ATMEL;
14762 tg3_flag_set(tp, NVRAM_BUFFERED);
14763 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
14765 nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
14766 tw32(NVRAM_CFG1, nvcfg1);
14768 case FLASH_5717VENDOR_ATMEL_MDB011D:
14769 case FLASH_5717VENDOR_ATMEL_ADB011B:
14770 case FLASH_5717VENDOR_ATMEL_ADB011D:
14771 case FLASH_5717VENDOR_ATMEL_MDB021D:
14772 case FLASH_5717VENDOR_ATMEL_ADB021B:
14773 case FLASH_5717VENDOR_ATMEL_ADB021D:
14774 case FLASH_5717VENDOR_ATMEL_45USPT:
14775 tp->nvram_jedecnum = JEDEC_ATMEL;
14776 tg3_flag_set(tp, NVRAM_BUFFERED);
14777 tg3_flag_set(tp, FLASH);
14779 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
14780 case FLASH_5717VENDOR_ATMEL_MDB021D:
14781 /* Detect size with tg3_nvram_get_size() */
14783 case FLASH_5717VENDOR_ATMEL_ADB021B:
14784 case FLASH_5717VENDOR_ATMEL_ADB021D:
14785 tp->nvram_size = TG3_NVRAM_SIZE_256KB;
14788 tp->nvram_size = TG3_NVRAM_SIZE_128KB;
14792 case FLASH_5717VENDOR_ST_M_M25PE10:
14793 case FLASH_5717VENDOR_ST_A_M25PE10:
14794 case FLASH_5717VENDOR_ST_M_M45PE10:
14795 case FLASH_5717VENDOR_ST_A_M45PE10:
14796 case FLASH_5717VENDOR_ST_M_M25PE20:
14797 case FLASH_5717VENDOR_ST_A_M25PE20:
14798 case FLASH_5717VENDOR_ST_M_M45PE20:
14799 case FLASH_5717VENDOR_ST_A_M45PE20:
14800 case FLASH_5717VENDOR_ST_25USPT:
14801 case FLASH_5717VENDOR_ST_45USPT:
14802 tp->nvram_jedecnum = JEDEC_ST;
14803 tg3_flag_set(tp, NVRAM_BUFFERED);
14804 tg3_flag_set(tp, FLASH);
14806 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
14807 case FLASH_5717VENDOR_ST_M_M25PE20:
14808 case FLASH_5717VENDOR_ST_M_M45PE20:
14809 /* Detect size with tg3_nvram_get_size() */
14811 case FLASH_5717VENDOR_ST_A_M25PE20:
14812 case FLASH_5717VENDOR_ST_A_M45PE20:
14813 tp->nvram_size = TG3_NVRAM_SIZE_256KB;
14816 tp->nvram_size = TG3_NVRAM_SIZE_128KB;
14821 tg3_flag_set(tp, NO_NVRAM);
14825 tg3_nvram_get_pagesize(tp, nvcfg1);
14826 if (tp->nvram_pagesize != 264 && tp->nvram_pagesize != 528)
14827 tg3_flag_set(tp, NO_NVRAM_ADDR_TRANS);
14830 static void tg3_get_5720_nvram_info(struct tg3 *tp)
14832 u32 nvcfg1, nvmpinstrp, nv_status;
14834 nvcfg1 = tr32(NVRAM_CFG1);
14835 nvmpinstrp = nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK;
14837 if (tg3_asic_rev(tp) == ASIC_REV_5762) {
14838 if (!(nvcfg1 & NVRAM_CFG1_5762VENDOR_MASK)) {
14839 tg3_flag_set(tp, NO_NVRAM);
14843 switch (nvmpinstrp) {
14844 case FLASH_5762_MX25L_100:
14845 case FLASH_5762_MX25L_200:
14846 case FLASH_5762_MX25L_400:
14847 case FLASH_5762_MX25L_800:
14848 case FLASH_5762_MX25L_160_320:
14849 tp->nvram_pagesize = 4096;
14850 tp->nvram_jedecnum = JEDEC_MACRONIX;
14851 tg3_flag_set(tp, NVRAM_BUFFERED);
14852 tg3_flag_set(tp, NO_NVRAM_ADDR_TRANS);
14853 tg3_flag_set(tp, FLASH);
14854 nv_status = tr32(NVRAM_AUTOSENSE_STATUS);
14856 (1 << (nv_status >> AUTOSENSE_DEVID &
14857 AUTOSENSE_DEVID_MASK)
14858 << AUTOSENSE_SIZE_IN_MB);
14861 case FLASH_5762_EEPROM_HD:
14862 nvmpinstrp = FLASH_5720_EEPROM_HD;
14864 case FLASH_5762_EEPROM_LD:
14865 nvmpinstrp = FLASH_5720_EEPROM_LD;
14867 case FLASH_5720VENDOR_M_ST_M45PE20:
14868 /* This pinstrap supports multiple sizes, so force it
14869 * to read the actual size from location 0xf0.
14871 nvmpinstrp = FLASH_5720VENDOR_ST_45USPT;
14876 switch (nvmpinstrp) {
14877 case FLASH_5720_EEPROM_HD:
14878 case FLASH_5720_EEPROM_LD:
14879 tp->nvram_jedecnum = JEDEC_ATMEL;
14880 tg3_flag_set(tp, NVRAM_BUFFERED);
14882 nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
14883 tw32(NVRAM_CFG1, nvcfg1);
14884 if (nvmpinstrp == FLASH_5720_EEPROM_HD)
14885 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
14887 tp->nvram_pagesize = ATMEL_AT24C02_CHIP_SIZE;
14889 case FLASH_5720VENDOR_M_ATMEL_DB011D:
14890 case FLASH_5720VENDOR_A_ATMEL_DB011B:
14891 case FLASH_5720VENDOR_A_ATMEL_DB011D:
14892 case FLASH_5720VENDOR_M_ATMEL_DB021D:
14893 case FLASH_5720VENDOR_A_ATMEL_DB021B:
14894 case FLASH_5720VENDOR_A_ATMEL_DB021D:
14895 case FLASH_5720VENDOR_M_ATMEL_DB041D:
14896 case FLASH_5720VENDOR_A_ATMEL_DB041B:
14897 case FLASH_5720VENDOR_A_ATMEL_DB041D:
14898 case FLASH_5720VENDOR_M_ATMEL_DB081D:
14899 case FLASH_5720VENDOR_A_ATMEL_DB081D:
14900 case FLASH_5720VENDOR_ATMEL_45USPT:
14901 tp->nvram_jedecnum = JEDEC_ATMEL;
14902 tg3_flag_set(tp, NVRAM_BUFFERED);
14903 tg3_flag_set(tp, FLASH);
14905 switch (nvmpinstrp) {
14906 case FLASH_5720VENDOR_M_ATMEL_DB021D:
14907 case FLASH_5720VENDOR_A_ATMEL_DB021B:
14908 case FLASH_5720VENDOR_A_ATMEL_DB021D:
14909 tp->nvram_size = TG3_NVRAM_SIZE_256KB;
14911 case FLASH_5720VENDOR_M_ATMEL_DB041D:
14912 case FLASH_5720VENDOR_A_ATMEL_DB041B:
14913 case FLASH_5720VENDOR_A_ATMEL_DB041D:
14914 tp->nvram_size = TG3_NVRAM_SIZE_512KB;
14916 case FLASH_5720VENDOR_M_ATMEL_DB081D:
14917 case FLASH_5720VENDOR_A_ATMEL_DB081D:
14918 tp->nvram_size = TG3_NVRAM_SIZE_1MB;
14921 if (tg3_asic_rev(tp) != ASIC_REV_5762)
14922 tp->nvram_size = TG3_NVRAM_SIZE_128KB;
14926 case FLASH_5720VENDOR_M_ST_M25PE10:
14927 case FLASH_5720VENDOR_M_ST_M45PE10:
14928 case FLASH_5720VENDOR_A_ST_M25PE10:
14929 case FLASH_5720VENDOR_A_ST_M45PE10:
14930 case FLASH_5720VENDOR_M_ST_M25PE20:
14931 case FLASH_5720VENDOR_M_ST_M45PE20:
14932 case FLASH_5720VENDOR_A_ST_M25PE20:
14933 case FLASH_5720VENDOR_A_ST_M45PE20:
14934 case FLASH_5720VENDOR_M_ST_M25PE40:
14935 case FLASH_5720VENDOR_M_ST_M45PE40:
14936 case FLASH_5720VENDOR_A_ST_M25PE40:
14937 case FLASH_5720VENDOR_A_ST_M45PE40:
14938 case FLASH_5720VENDOR_M_ST_M25PE80:
14939 case FLASH_5720VENDOR_M_ST_M45PE80:
14940 case FLASH_5720VENDOR_A_ST_M25PE80:
14941 case FLASH_5720VENDOR_A_ST_M45PE80:
14942 case FLASH_5720VENDOR_ST_25USPT:
14943 case FLASH_5720VENDOR_ST_45USPT:
14944 tp->nvram_jedecnum = JEDEC_ST;
14945 tg3_flag_set(tp, NVRAM_BUFFERED);
14946 tg3_flag_set(tp, FLASH);
14948 switch (nvmpinstrp) {
14949 case FLASH_5720VENDOR_M_ST_M25PE20:
14950 case FLASH_5720VENDOR_M_ST_M45PE20:
14951 case FLASH_5720VENDOR_A_ST_M25PE20:
14952 case FLASH_5720VENDOR_A_ST_M45PE20:
14953 tp->nvram_size = TG3_NVRAM_SIZE_256KB;
14955 case FLASH_5720VENDOR_M_ST_M25PE40:
14956 case FLASH_5720VENDOR_M_ST_M45PE40:
14957 case FLASH_5720VENDOR_A_ST_M25PE40:
14958 case FLASH_5720VENDOR_A_ST_M45PE40:
14959 tp->nvram_size = TG3_NVRAM_SIZE_512KB;
14961 case FLASH_5720VENDOR_M_ST_M25PE80:
14962 case FLASH_5720VENDOR_M_ST_M45PE80:
14963 case FLASH_5720VENDOR_A_ST_M25PE80:
14964 case FLASH_5720VENDOR_A_ST_M45PE80:
14965 tp->nvram_size = TG3_NVRAM_SIZE_1MB;
14968 if (tg3_asic_rev(tp) != ASIC_REV_5762)
14969 tp->nvram_size = TG3_NVRAM_SIZE_128KB;
14974 tg3_flag_set(tp, NO_NVRAM);
14978 tg3_nvram_get_pagesize(tp, nvcfg1);
14979 if (tp->nvram_pagesize != 264 && tp->nvram_pagesize != 528)
14980 tg3_flag_set(tp, NO_NVRAM_ADDR_TRANS);
14982 if (tg3_asic_rev(tp) == ASIC_REV_5762) {
14985 if (tg3_nvram_read(tp, 0, &val))
14988 if (val != TG3_EEPROM_MAGIC &&
14989 (val & TG3_EEPROM_MAGIC_FW_MSK) != TG3_EEPROM_MAGIC_FW)
14990 tg3_flag_set(tp, NO_NVRAM);
14994 /* Chips other than 5700/5701 use the NVRAM for fetching info. */
14995 static void tg3_nvram_init(struct tg3 *tp)
14997 if (tg3_flag(tp, IS_SSB_CORE)) {
14998 /* No NVRAM and EEPROM on the SSB Broadcom GigE core. */
14999 tg3_flag_clear(tp, NVRAM);
15000 tg3_flag_clear(tp, NVRAM_BUFFERED);
15001 tg3_flag_set(tp, NO_NVRAM);
15005 tw32_f(GRC_EEPROM_ADDR,
15006 (EEPROM_ADDR_FSM_RESET |
15007 (EEPROM_DEFAULT_CLOCK_PERIOD <<
15008 EEPROM_ADDR_CLKPERD_SHIFT)));
15012 /* Enable seeprom accesses. */
15013 tw32_f(GRC_LOCAL_CTRL,
15014 tr32(GRC_LOCAL_CTRL) | GRC_LCLCTRL_AUTO_SEEPROM);
15017 if (tg3_asic_rev(tp) != ASIC_REV_5700 &&
15018 tg3_asic_rev(tp) != ASIC_REV_5701) {
15019 tg3_flag_set(tp, NVRAM);
15021 if (tg3_nvram_lock(tp)) {
15022 netdev_warn(tp->dev,
15023 "Cannot get nvram lock, %s failed\n",
15027 tg3_enable_nvram_access(tp);
15029 tp->nvram_size = 0;
15031 if (tg3_asic_rev(tp) == ASIC_REV_5752)
15032 tg3_get_5752_nvram_info(tp);
15033 else if (tg3_asic_rev(tp) == ASIC_REV_5755)
15034 tg3_get_5755_nvram_info(tp);
15035 else if (tg3_asic_rev(tp) == ASIC_REV_5787 ||
15036 tg3_asic_rev(tp) == ASIC_REV_5784 ||
15037 tg3_asic_rev(tp) == ASIC_REV_5785)
15038 tg3_get_5787_nvram_info(tp);
15039 else if (tg3_asic_rev(tp) == ASIC_REV_5761)
15040 tg3_get_5761_nvram_info(tp);
15041 else if (tg3_asic_rev(tp) == ASIC_REV_5906)
15042 tg3_get_5906_nvram_info(tp);
15043 else if (tg3_asic_rev(tp) == ASIC_REV_57780 ||
15044 tg3_flag(tp, 57765_CLASS))
15045 tg3_get_57780_nvram_info(tp);
15046 else if (tg3_asic_rev(tp) == ASIC_REV_5717 ||
15047 tg3_asic_rev(tp) == ASIC_REV_5719)
15048 tg3_get_5717_nvram_info(tp);
15049 else if (tg3_asic_rev(tp) == ASIC_REV_5720 ||
15050 tg3_asic_rev(tp) == ASIC_REV_5762)
15051 tg3_get_5720_nvram_info(tp);
15053 tg3_get_nvram_info(tp);
15055 if (tp->nvram_size == 0)
15056 tg3_get_nvram_size(tp);
15058 tg3_disable_nvram_access(tp);
15059 tg3_nvram_unlock(tp);
15062 tg3_flag_clear(tp, NVRAM);
15063 tg3_flag_clear(tp, NVRAM_BUFFERED);
15065 tg3_get_eeprom_size(tp);
15069 struct subsys_tbl_ent {
15070 u16 subsys_vendor, subsys_devid;
15074 static struct subsys_tbl_ent subsys_id_to_phy_id[] = {
15075 /* Broadcom boards. */
15076 { TG3PCI_SUBVENDOR_ID_BROADCOM,
15077 TG3PCI_SUBDEVICE_ID_BROADCOM_95700A6, TG3_PHY_ID_BCM5401 },
15078 { TG3PCI_SUBVENDOR_ID_BROADCOM,
15079 TG3PCI_SUBDEVICE_ID_BROADCOM_95701A5, TG3_PHY_ID_BCM5701 },
15080 { TG3PCI_SUBVENDOR_ID_BROADCOM,
15081 TG3PCI_SUBDEVICE_ID_BROADCOM_95700T6, TG3_PHY_ID_BCM8002 },
15082 { TG3PCI_SUBVENDOR_ID_BROADCOM,
15083 TG3PCI_SUBDEVICE_ID_BROADCOM_95700A9, 0 },
15084 { TG3PCI_SUBVENDOR_ID_BROADCOM,
15085 TG3PCI_SUBDEVICE_ID_BROADCOM_95701T1, TG3_PHY_ID_BCM5701 },
15086 { TG3PCI_SUBVENDOR_ID_BROADCOM,
15087 TG3PCI_SUBDEVICE_ID_BROADCOM_95701T8, TG3_PHY_ID_BCM5701 },
15088 { TG3PCI_SUBVENDOR_ID_BROADCOM,
15089 TG3PCI_SUBDEVICE_ID_BROADCOM_95701A7, 0 },
15090 { TG3PCI_SUBVENDOR_ID_BROADCOM,
15091 TG3PCI_SUBDEVICE_ID_BROADCOM_95701A10, TG3_PHY_ID_BCM5701 },
15092 { TG3PCI_SUBVENDOR_ID_BROADCOM,
15093 TG3PCI_SUBDEVICE_ID_BROADCOM_95701A12, TG3_PHY_ID_BCM5701 },
15094 { TG3PCI_SUBVENDOR_ID_BROADCOM,
15095 TG3PCI_SUBDEVICE_ID_BROADCOM_95703AX1, TG3_PHY_ID_BCM5703 },
15096 { TG3PCI_SUBVENDOR_ID_BROADCOM,
15097 TG3PCI_SUBDEVICE_ID_BROADCOM_95703AX2, TG3_PHY_ID_BCM5703 },
15100 { TG3PCI_SUBVENDOR_ID_3COM,
15101 TG3PCI_SUBDEVICE_ID_3COM_3C996T, TG3_PHY_ID_BCM5401 },
15102 { TG3PCI_SUBVENDOR_ID_3COM,
15103 TG3PCI_SUBDEVICE_ID_3COM_3C996BT, TG3_PHY_ID_BCM5701 },
15104 { TG3PCI_SUBVENDOR_ID_3COM,
15105 TG3PCI_SUBDEVICE_ID_3COM_3C996SX, 0 },
15106 { TG3PCI_SUBVENDOR_ID_3COM,
15107 TG3PCI_SUBDEVICE_ID_3COM_3C1000T, TG3_PHY_ID_BCM5701 },
15108 { TG3PCI_SUBVENDOR_ID_3COM,
15109 TG3PCI_SUBDEVICE_ID_3COM_3C940BR01, TG3_PHY_ID_BCM5701 },
15112 { TG3PCI_SUBVENDOR_ID_DELL,
15113 TG3PCI_SUBDEVICE_ID_DELL_VIPER, TG3_PHY_ID_BCM5401 },
15114 { TG3PCI_SUBVENDOR_ID_DELL,
15115 TG3PCI_SUBDEVICE_ID_DELL_JAGUAR, TG3_PHY_ID_BCM5401 },
15116 { TG3PCI_SUBVENDOR_ID_DELL,
15117 TG3PCI_SUBDEVICE_ID_DELL_MERLOT, TG3_PHY_ID_BCM5411 },
15118 { TG3PCI_SUBVENDOR_ID_DELL,
15119 TG3PCI_SUBDEVICE_ID_DELL_SLIM_MERLOT, TG3_PHY_ID_BCM5411 },
15121 /* Compaq boards. */
15122 { TG3PCI_SUBVENDOR_ID_COMPAQ,
15123 TG3PCI_SUBDEVICE_ID_COMPAQ_BANSHEE, TG3_PHY_ID_BCM5701 },
15124 { TG3PCI_SUBVENDOR_ID_COMPAQ,
15125 TG3PCI_SUBDEVICE_ID_COMPAQ_BANSHEE_2, TG3_PHY_ID_BCM5701 },
15126 { TG3PCI_SUBVENDOR_ID_COMPAQ,
15127 TG3PCI_SUBDEVICE_ID_COMPAQ_CHANGELING, 0 },
15128 { TG3PCI_SUBVENDOR_ID_COMPAQ,
15129 TG3PCI_SUBDEVICE_ID_COMPAQ_NC7780, TG3_PHY_ID_BCM5701 },
15130 { TG3PCI_SUBVENDOR_ID_COMPAQ,
15131 TG3PCI_SUBDEVICE_ID_COMPAQ_NC7780_2, TG3_PHY_ID_BCM5701 },
15134 { TG3PCI_SUBVENDOR_ID_IBM,
15135 TG3PCI_SUBDEVICE_ID_IBM_5703SAX2, 0 }
15138 static struct subsys_tbl_ent *tg3_lookup_by_subsys(struct tg3 *tp)
15142 for (i = 0; i < ARRAY_SIZE(subsys_id_to_phy_id); i++) {
15143 if ((subsys_id_to_phy_id[i].subsys_vendor ==
15144 tp->pdev->subsystem_vendor) &&
15145 (subsys_id_to_phy_id[i].subsys_devid ==
15146 tp->pdev->subsystem_device))
15147 return &subsys_id_to_phy_id[i];
15152 static void tg3_get_eeprom_hw_cfg(struct tg3 *tp)
15156 tp->phy_id = TG3_PHY_ID_INVALID;
15157 tp->led_ctrl = LED_CTRL_MODE_PHY_1;
15159 /* Assume an onboard device and WOL capable by default. */
15160 tg3_flag_set(tp, EEPROM_WRITE_PROT);
15161 tg3_flag_set(tp, WOL_CAP);
15163 if (tg3_asic_rev(tp) == ASIC_REV_5906) {
15164 if (!(tr32(PCIE_TRANSACTION_CFG) & PCIE_TRANS_CFG_LOM)) {
15165 tg3_flag_clear(tp, EEPROM_WRITE_PROT);
15166 tg3_flag_set(tp, IS_NIC);
15168 val = tr32(VCPU_CFGSHDW);
15169 if (val & VCPU_CFGSHDW_ASPM_DBNC)
15170 tg3_flag_set(tp, ASPM_WORKAROUND);
15171 if ((val & VCPU_CFGSHDW_WOL_ENABLE) &&
15172 (val & VCPU_CFGSHDW_WOL_MAGPKT)) {
15173 tg3_flag_set(tp, WOL_ENABLE);
15174 device_set_wakeup_enable(&tp->pdev->dev, true);
15179 tg3_read_mem(tp, NIC_SRAM_DATA_SIG, &val);
15180 if (val == NIC_SRAM_DATA_SIG_MAGIC) {
15181 u32 nic_cfg, led_cfg;
15182 u32 cfg2 = 0, cfg4 = 0, cfg5 = 0;
15183 u32 nic_phy_id, ver, eeprom_phy_id;
15184 int eeprom_phy_serdes = 0;
15186 tg3_read_mem(tp, NIC_SRAM_DATA_CFG, &nic_cfg);
15187 tp->nic_sram_data_cfg = nic_cfg;
15189 tg3_read_mem(tp, NIC_SRAM_DATA_VER, &ver);
15190 ver >>= NIC_SRAM_DATA_VER_SHIFT;
15191 if (tg3_asic_rev(tp) != ASIC_REV_5700 &&
15192 tg3_asic_rev(tp) != ASIC_REV_5701 &&
15193 tg3_asic_rev(tp) != ASIC_REV_5703 &&
15194 (ver > 0) && (ver < 0x100))
15195 tg3_read_mem(tp, NIC_SRAM_DATA_CFG_2, &cfg2);
15197 if (tg3_asic_rev(tp) == ASIC_REV_5785)
15198 tg3_read_mem(tp, NIC_SRAM_DATA_CFG_4, &cfg4);
15200 if (tg3_asic_rev(tp) == ASIC_REV_5717 ||
15201 tg3_asic_rev(tp) == ASIC_REV_5719 ||
15202 tg3_asic_rev(tp) == ASIC_REV_5720)
15203 tg3_read_mem(tp, NIC_SRAM_DATA_CFG_5, &cfg5);
15205 if ((nic_cfg & NIC_SRAM_DATA_CFG_PHY_TYPE_MASK) ==
15206 NIC_SRAM_DATA_CFG_PHY_TYPE_FIBER)
15207 eeprom_phy_serdes = 1;
15209 tg3_read_mem(tp, NIC_SRAM_DATA_PHY_ID, &nic_phy_id);
15210 if (nic_phy_id != 0) {
15211 u32 id1 = nic_phy_id & NIC_SRAM_DATA_PHY_ID1_MASK;
15212 u32 id2 = nic_phy_id & NIC_SRAM_DATA_PHY_ID2_MASK;
15214 eeprom_phy_id = (id1 >> 16) << 10;
15215 eeprom_phy_id |= (id2 & 0xfc00) << 16;
15216 eeprom_phy_id |= (id2 & 0x03ff) << 0;
15220 tp->phy_id = eeprom_phy_id;
15221 if (eeprom_phy_serdes) {
15222 if (!tg3_flag(tp, 5705_PLUS))
15223 tp->phy_flags |= TG3_PHYFLG_PHY_SERDES;
15225 tp->phy_flags |= TG3_PHYFLG_MII_SERDES;
15228 if (tg3_flag(tp, 5750_PLUS))
15229 led_cfg = cfg2 & (NIC_SRAM_DATA_CFG_LED_MODE_MASK |
15230 SHASTA_EXT_LED_MODE_MASK);
15232 led_cfg = nic_cfg & NIC_SRAM_DATA_CFG_LED_MODE_MASK;
15236 case NIC_SRAM_DATA_CFG_LED_MODE_PHY_1:
15237 tp->led_ctrl = LED_CTRL_MODE_PHY_1;
15240 case NIC_SRAM_DATA_CFG_LED_MODE_PHY_2:
15241 tp->led_ctrl = LED_CTRL_MODE_PHY_2;
15244 case NIC_SRAM_DATA_CFG_LED_MODE_MAC:
15245 tp->led_ctrl = LED_CTRL_MODE_MAC;
15247 /* Default to PHY_1_MODE if 0 (MAC_MODE) is
15248 * read on some older 5700/5701 bootcode.
15250 if (tg3_asic_rev(tp) == ASIC_REV_5700 ||
15251 tg3_asic_rev(tp) == ASIC_REV_5701)
15252 tp->led_ctrl = LED_CTRL_MODE_PHY_1;
15256 case SHASTA_EXT_LED_SHARED:
15257 tp->led_ctrl = LED_CTRL_MODE_SHARED;
15258 if (tg3_chip_rev_id(tp) != CHIPREV_ID_5750_A0 &&
15259 tg3_chip_rev_id(tp) != CHIPREV_ID_5750_A1)
15260 tp->led_ctrl |= (LED_CTRL_MODE_PHY_1 |
15261 LED_CTRL_MODE_PHY_2);
15263 if (tg3_flag(tp, 5717_PLUS) ||
15264 tg3_asic_rev(tp) == ASIC_REV_5762)
15265 tp->led_ctrl |= LED_CTRL_BLINK_RATE_OVERRIDE |
15266 LED_CTRL_BLINK_RATE_MASK;
15270 case SHASTA_EXT_LED_MAC:
15271 tp->led_ctrl = LED_CTRL_MODE_SHASTA_MAC;
15274 case SHASTA_EXT_LED_COMBO:
15275 tp->led_ctrl = LED_CTRL_MODE_COMBO;
15276 if (tg3_chip_rev_id(tp) != CHIPREV_ID_5750_A0)
15277 tp->led_ctrl |= (LED_CTRL_MODE_PHY_1 |
15278 LED_CTRL_MODE_PHY_2);
15283 if ((tg3_asic_rev(tp) == ASIC_REV_5700 ||
15284 tg3_asic_rev(tp) == ASIC_REV_5701) &&
15285 tp->pdev->subsystem_vendor == PCI_VENDOR_ID_DELL)
15286 tp->led_ctrl = LED_CTRL_MODE_PHY_2;
15288 if (tg3_chip_rev(tp) == CHIPREV_5784_AX)
15289 tp->led_ctrl = LED_CTRL_MODE_PHY_1;
15291 if (nic_cfg & NIC_SRAM_DATA_CFG_EEPROM_WP) {
15292 tg3_flag_set(tp, EEPROM_WRITE_PROT);
15293 if ((tp->pdev->subsystem_vendor ==
15294 PCI_VENDOR_ID_ARIMA) &&
15295 (tp->pdev->subsystem_device == 0x205a ||
15296 tp->pdev->subsystem_device == 0x2063))
15297 tg3_flag_clear(tp, EEPROM_WRITE_PROT);
15299 tg3_flag_clear(tp, EEPROM_WRITE_PROT);
15300 tg3_flag_set(tp, IS_NIC);
15303 if (nic_cfg & NIC_SRAM_DATA_CFG_ASF_ENABLE) {
15304 tg3_flag_set(tp, ENABLE_ASF);
15305 if (tg3_flag(tp, 5750_PLUS))
15306 tg3_flag_set(tp, ASF_NEW_HANDSHAKE);
15309 if ((nic_cfg & NIC_SRAM_DATA_CFG_APE_ENABLE) &&
15310 tg3_flag(tp, 5750_PLUS))
15311 tg3_flag_set(tp, ENABLE_APE);
15313 if (tp->phy_flags & TG3_PHYFLG_ANY_SERDES &&
15314 !(nic_cfg & NIC_SRAM_DATA_CFG_FIBER_WOL))
15315 tg3_flag_clear(tp, WOL_CAP);
15317 if (tg3_flag(tp, WOL_CAP) &&
15318 (nic_cfg & NIC_SRAM_DATA_CFG_WOL_ENABLE)) {
15319 tg3_flag_set(tp, WOL_ENABLE);
15320 device_set_wakeup_enable(&tp->pdev->dev, true);
15323 if (cfg2 & (1 << 17))
15324 tp->phy_flags |= TG3_PHYFLG_CAPACITIVE_COUPLING;
15326 /* serdes signal pre-emphasis in register 0x590 set by */
15327 /* bootcode if bit 18 is set */
15328 if (cfg2 & (1 << 18))
15329 tp->phy_flags |= TG3_PHYFLG_SERDES_PREEMPHASIS;
15331 if ((tg3_flag(tp, 57765_PLUS) ||
15332 (tg3_asic_rev(tp) == ASIC_REV_5784 &&
15333 tg3_chip_rev(tp) != CHIPREV_5784_AX)) &&
15334 (cfg2 & NIC_SRAM_DATA_CFG_2_APD_EN))
15335 tp->phy_flags |= TG3_PHYFLG_ENABLE_APD;
15337 if (tg3_flag(tp, PCI_EXPRESS)) {
15340 tg3_read_mem(tp, NIC_SRAM_DATA_CFG_3, &cfg3);
15341 if (tg3_asic_rev(tp) != ASIC_REV_5785 &&
15342 !tg3_flag(tp, 57765_PLUS) &&
15343 (cfg3 & NIC_SRAM_ASPM_DEBOUNCE))
15344 tg3_flag_set(tp, ASPM_WORKAROUND);
15345 if (cfg3 & NIC_SRAM_LNK_FLAP_AVOID)
15346 tp->phy_flags |= TG3_PHYFLG_KEEP_LINK_ON_PWRDN;
15347 if (cfg3 & NIC_SRAM_1G_ON_VAUX_OK)
15348 tp->phy_flags |= TG3_PHYFLG_1G_ON_VAUX_OK;
15351 if (cfg4 & NIC_SRAM_RGMII_INBAND_DISABLE)
15352 tg3_flag_set(tp, RGMII_INBAND_DISABLE);
15353 if (cfg4 & NIC_SRAM_RGMII_EXT_IBND_RX_EN)
15354 tg3_flag_set(tp, RGMII_EXT_IBND_RX_EN);
15355 if (cfg4 & NIC_SRAM_RGMII_EXT_IBND_TX_EN)
15356 tg3_flag_set(tp, RGMII_EXT_IBND_TX_EN);
15358 if (cfg5 & NIC_SRAM_DISABLE_1G_HALF_ADV)
15359 tp->phy_flags |= TG3_PHYFLG_DISABLE_1G_HD_ADV;
15362 if (tg3_flag(tp, WOL_CAP))
15363 device_set_wakeup_enable(&tp->pdev->dev,
15364 tg3_flag(tp, WOL_ENABLE));
15366 device_set_wakeup_capable(&tp->pdev->dev, false);
15369 static int tg3_ape_otp_read(struct tg3 *tp, u32 offset, u32 *val)
15372 u32 val2, off = offset * 8;
15374 err = tg3_nvram_lock(tp);
15378 tg3_ape_write32(tp, TG3_APE_OTP_ADDR, off | APE_OTP_ADDR_CPU_ENABLE);
15379 tg3_ape_write32(tp, TG3_APE_OTP_CTRL, APE_OTP_CTRL_PROG_EN |
15380 APE_OTP_CTRL_CMD_RD | APE_OTP_CTRL_START);
15381 tg3_ape_read32(tp, TG3_APE_OTP_CTRL);
15384 for (i = 0; i < 100; i++) {
15385 val2 = tg3_ape_read32(tp, TG3_APE_OTP_STATUS);
15386 if (val2 & APE_OTP_STATUS_CMD_DONE) {
15387 *val = tg3_ape_read32(tp, TG3_APE_OTP_RD_DATA);
15393 tg3_ape_write32(tp, TG3_APE_OTP_CTRL, 0);
15395 tg3_nvram_unlock(tp);
15396 if (val2 & APE_OTP_STATUS_CMD_DONE)
15402 static int tg3_issue_otp_command(struct tg3 *tp, u32 cmd)
15407 tw32(OTP_CTRL, cmd | OTP_CTRL_OTP_CMD_START);
15408 tw32(OTP_CTRL, cmd);
15410 /* Wait for up to 1 ms for command to execute. */
15411 for (i = 0; i < 100; i++) {
15412 val = tr32(OTP_STATUS);
15413 if (val & OTP_STATUS_CMD_DONE)
15418 return (val & OTP_STATUS_CMD_DONE) ? 0 : -EBUSY;
15421 /* Read the gphy configuration from the OTP region of the chip. The gphy
15422 * configuration is a 32-bit value that straddles the alignment boundary.
15423 * We do two 32-bit reads and then shift and merge the results.
15425 static u32 tg3_read_otp_phycfg(struct tg3 *tp)
15427 u32 bhalf_otp, thalf_otp;
15429 tw32(OTP_MODE, OTP_MODE_OTP_THRU_GRC);
15431 if (tg3_issue_otp_command(tp, OTP_CTRL_OTP_CMD_INIT))
15434 tw32(OTP_ADDRESS, OTP_ADDRESS_MAGIC1);
15436 if (tg3_issue_otp_command(tp, OTP_CTRL_OTP_CMD_READ))
15439 thalf_otp = tr32(OTP_READ_DATA);
15441 tw32(OTP_ADDRESS, OTP_ADDRESS_MAGIC2);
15443 if (tg3_issue_otp_command(tp, OTP_CTRL_OTP_CMD_READ))
15446 bhalf_otp = tr32(OTP_READ_DATA);
15448 return ((thalf_otp & 0x0000ffff) << 16) | (bhalf_otp >> 16);
15451 static void tg3_phy_init_link_config(struct tg3 *tp)
15453 u32 adv = ADVERTISED_Autoneg;
15455 if (!(tp->phy_flags & TG3_PHYFLG_10_100_ONLY)) {
15456 if (!(tp->phy_flags & TG3_PHYFLG_DISABLE_1G_HD_ADV))
15457 adv |= ADVERTISED_1000baseT_Half;
15458 adv |= ADVERTISED_1000baseT_Full;
15461 if (!(tp->phy_flags & TG3_PHYFLG_ANY_SERDES))
15462 adv |= ADVERTISED_100baseT_Half |
15463 ADVERTISED_100baseT_Full |
15464 ADVERTISED_10baseT_Half |
15465 ADVERTISED_10baseT_Full |
15468 adv |= ADVERTISED_FIBRE;
15470 tp->link_config.advertising = adv;
15471 tp->link_config.speed = SPEED_UNKNOWN;
15472 tp->link_config.duplex = DUPLEX_UNKNOWN;
15473 tp->link_config.autoneg = AUTONEG_ENABLE;
15474 tp->link_config.active_speed = SPEED_UNKNOWN;
15475 tp->link_config.active_duplex = DUPLEX_UNKNOWN;
15480 static int tg3_phy_probe(struct tg3 *tp)
15482 u32 hw_phy_id_1, hw_phy_id_2;
15483 u32 hw_phy_id, hw_phy_id_masked;
15486 /* flow control autonegotiation is default behavior */
15487 tg3_flag_set(tp, PAUSE_AUTONEG);
15488 tp->link_config.flowctrl = FLOW_CTRL_TX | FLOW_CTRL_RX;
15490 if (tg3_flag(tp, ENABLE_APE)) {
15491 switch (tp->pci_fn) {
15493 tp->phy_ape_lock = TG3_APE_LOCK_PHY0;
15496 tp->phy_ape_lock = TG3_APE_LOCK_PHY1;
15499 tp->phy_ape_lock = TG3_APE_LOCK_PHY2;
15502 tp->phy_ape_lock = TG3_APE_LOCK_PHY3;
15507 if (!tg3_flag(tp, ENABLE_ASF) &&
15508 !(tp->phy_flags & TG3_PHYFLG_ANY_SERDES) &&
15509 !(tp->phy_flags & TG3_PHYFLG_10_100_ONLY))
15510 tp->phy_flags &= ~(TG3_PHYFLG_1G_ON_VAUX_OK |
15511 TG3_PHYFLG_KEEP_LINK_ON_PWRDN);
15513 if (tg3_flag(tp, USE_PHYLIB))
15514 return tg3_phy_init(tp);
15516 /* Reading the PHY ID register can conflict with ASF
15517 * firmware access to the PHY hardware.
15520 if (tg3_flag(tp, ENABLE_ASF) || tg3_flag(tp, ENABLE_APE)) {
15521 hw_phy_id = hw_phy_id_masked = TG3_PHY_ID_INVALID;
15523 /* Now read the physical PHY_ID from the chip and verify
15524 * that it is sane. If it doesn't look good, we fall back
15525 * to either the hard-coded table based PHY_ID and failing
15526 * that the value found in the eeprom area.
15528 err |= tg3_readphy(tp, MII_PHYSID1, &hw_phy_id_1);
15529 err |= tg3_readphy(tp, MII_PHYSID2, &hw_phy_id_2);
15531 hw_phy_id = (hw_phy_id_1 & 0xffff) << 10;
15532 hw_phy_id |= (hw_phy_id_2 & 0xfc00) << 16;
15533 hw_phy_id |= (hw_phy_id_2 & 0x03ff) << 0;
15535 hw_phy_id_masked = hw_phy_id & TG3_PHY_ID_MASK;
15538 if (!err && TG3_KNOWN_PHY_ID(hw_phy_id_masked)) {
15539 tp->phy_id = hw_phy_id;
15540 if (hw_phy_id_masked == TG3_PHY_ID_BCM8002)
15541 tp->phy_flags |= TG3_PHYFLG_PHY_SERDES;
15543 tp->phy_flags &= ~TG3_PHYFLG_PHY_SERDES;
15545 if (tp->phy_id != TG3_PHY_ID_INVALID) {
15546 /* Do nothing, phy ID already set up in
15547 * tg3_get_eeprom_hw_cfg().
15550 struct subsys_tbl_ent *p;
15552 /* No eeprom signature? Try the hardcoded
15553 * subsys device table.
15555 p = tg3_lookup_by_subsys(tp);
15557 tp->phy_id = p->phy_id;
15558 } else if (!tg3_flag(tp, IS_SSB_CORE)) {
15559 /* For now we saw the IDs 0xbc050cd0,
15560 * 0xbc050f80 and 0xbc050c30 on devices
15561 * connected to an BCM4785 and there are
15562 * probably more. Just assume that the phy is
15563 * supported when it is connected to a SSB core
15570 tp->phy_id == TG3_PHY_ID_BCM8002)
15571 tp->phy_flags |= TG3_PHYFLG_PHY_SERDES;
15575 if (!(tp->phy_flags & TG3_PHYFLG_ANY_SERDES) &&
15576 (tg3_asic_rev(tp) == ASIC_REV_5719 ||
15577 tg3_asic_rev(tp) == ASIC_REV_5720 ||
15578 tg3_asic_rev(tp) == ASIC_REV_57766 ||
15579 tg3_asic_rev(tp) == ASIC_REV_5762 ||
15580 (tg3_asic_rev(tp) == ASIC_REV_5717 &&
15581 tg3_chip_rev_id(tp) != CHIPREV_ID_5717_A0) ||
15582 (tg3_asic_rev(tp) == ASIC_REV_57765 &&
15583 tg3_chip_rev_id(tp) != CHIPREV_ID_57765_A0))) {
15584 tp->phy_flags |= TG3_PHYFLG_EEE_CAP;
15586 tp->eee.supported = SUPPORTED_100baseT_Full |
15587 SUPPORTED_1000baseT_Full;
15588 tp->eee.advertised = ADVERTISED_100baseT_Full |
15589 ADVERTISED_1000baseT_Full;
15590 tp->eee.eee_enabled = 1;
15591 tp->eee.tx_lpi_enabled = 1;
15592 tp->eee.tx_lpi_timer = TG3_CPMU_DBTMR1_LNKIDLE_2047US;
15595 tg3_phy_init_link_config(tp);
15597 if (!(tp->phy_flags & TG3_PHYFLG_KEEP_LINK_ON_PWRDN) &&
15598 !(tp->phy_flags & TG3_PHYFLG_ANY_SERDES) &&
15599 !tg3_flag(tp, ENABLE_APE) &&
15600 !tg3_flag(tp, ENABLE_ASF)) {
15603 tg3_readphy(tp, MII_BMSR, &bmsr);
15604 if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
15605 (bmsr & BMSR_LSTATUS))
15606 goto skip_phy_reset;
15608 err = tg3_phy_reset(tp);
15612 tg3_phy_set_wirespeed(tp);
15614 if (!tg3_phy_copper_an_config_ok(tp, &dummy)) {
15615 tg3_phy_autoneg_cfg(tp, tp->link_config.advertising,
15616 tp->link_config.flowctrl);
15618 tg3_writephy(tp, MII_BMCR,
15619 BMCR_ANENABLE | BMCR_ANRESTART);
15624 if ((tp->phy_id & TG3_PHY_ID_MASK) == TG3_PHY_ID_BCM5401) {
15625 err = tg3_init_5401phy_dsp(tp);
15629 err = tg3_init_5401phy_dsp(tp);
15635 static void tg3_read_vpd(struct tg3 *tp)
15638 unsigned int block_end, rosize, len;
15642 vpd_data = (u8 *)tg3_vpd_readblock(tp, &vpdlen);
15646 i = pci_vpd_find_tag(vpd_data, 0, vpdlen, PCI_VPD_LRDT_RO_DATA);
15648 goto out_not_found;
15650 rosize = pci_vpd_lrdt_size(&vpd_data[i]);
15651 block_end = i + PCI_VPD_LRDT_TAG_SIZE + rosize;
15652 i += PCI_VPD_LRDT_TAG_SIZE;
15654 if (block_end > vpdlen)
15655 goto out_not_found;
15657 j = pci_vpd_find_info_keyword(vpd_data, i, rosize,
15658 PCI_VPD_RO_KEYWORD_MFR_ID);
15660 len = pci_vpd_info_field_size(&vpd_data[j]);
15662 j += PCI_VPD_INFO_FLD_HDR_SIZE;
15663 if (j + len > block_end || len != 4 ||
15664 memcmp(&vpd_data[j], "1028", 4))
15667 j = pci_vpd_find_info_keyword(vpd_data, i, rosize,
15668 PCI_VPD_RO_KEYWORD_VENDOR0);
15672 len = pci_vpd_info_field_size(&vpd_data[j]);
15674 j += PCI_VPD_INFO_FLD_HDR_SIZE;
15675 if (j + len > block_end)
15678 if (len >= sizeof(tp->fw_ver))
15679 len = sizeof(tp->fw_ver) - 1;
15680 memset(tp->fw_ver, 0, sizeof(tp->fw_ver));
15681 snprintf(tp->fw_ver, sizeof(tp->fw_ver), "%.*s bc ", len,
15686 i = pci_vpd_find_info_keyword(vpd_data, i, rosize,
15687 PCI_VPD_RO_KEYWORD_PARTNO);
15689 goto out_not_found;
15691 len = pci_vpd_info_field_size(&vpd_data[i]);
15693 i += PCI_VPD_INFO_FLD_HDR_SIZE;
15694 if (len > TG3_BPN_SIZE ||
15695 (len + i) > vpdlen)
15696 goto out_not_found;
15698 memcpy(tp->board_part_number, &vpd_data[i], len);
15702 if (tp->board_part_number[0])
15706 if (tg3_asic_rev(tp) == ASIC_REV_5717) {
15707 if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_5717 ||
15708 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5717_C)
15709 strcpy(tp->board_part_number, "BCM5717");
15710 else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_5718)
15711 strcpy(tp->board_part_number, "BCM5718");
15714 } else if (tg3_asic_rev(tp) == ASIC_REV_57780) {
15715 if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57780)
15716 strcpy(tp->board_part_number, "BCM57780");
15717 else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57760)
15718 strcpy(tp->board_part_number, "BCM57760");
15719 else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57790)
15720 strcpy(tp->board_part_number, "BCM57790");
15721 else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57788)
15722 strcpy(tp->board_part_number, "BCM57788");
15725 } else if (tg3_asic_rev(tp) == ASIC_REV_57765) {
15726 if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57761)
15727 strcpy(tp->board_part_number, "BCM57761");
15728 else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57765)
15729 strcpy(tp->board_part_number, "BCM57765");
15730 else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57781)
15731 strcpy(tp->board_part_number, "BCM57781");
15732 else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57785)
15733 strcpy(tp->board_part_number, "BCM57785");
15734 else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57791)
15735 strcpy(tp->board_part_number, "BCM57791");
15736 else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57795)
15737 strcpy(tp->board_part_number, "BCM57795");
15740 } else if (tg3_asic_rev(tp) == ASIC_REV_57766) {
15741 if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57762)
15742 strcpy(tp->board_part_number, "BCM57762");
15743 else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57766)
15744 strcpy(tp->board_part_number, "BCM57766");
15745 else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57782)
15746 strcpy(tp->board_part_number, "BCM57782");
15747 else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57786)
15748 strcpy(tp->board_part_number, "BCM57786");
15751 } else if (tg3_asic_rev(tp) == ASIC_REV_5906) {
15752 strcpy(tp->board_part_number, "BCM95906");
15755 strcpy(tp->board_part_number, "none");
15759 static int tg3_fw_img_is_valid(struct tg3 *tp, u32 offset)
15763 if (tg3_nvram_read(tp, offset, &val) ||
15764 (val & 0xfc000000) != 0x0c000000 ||
15765 tg3_nvram_read(tp, offset + 4, &val) ||
15772 static void tg3_read_bc_ver(struct tg3 *tp)
15774 u32 val, offset, start, ver_offset;
15776 bool newver = false;
15778 if (tg3_nvram_read(tp, 0xc, &offset) ||
15779 tg3_nvram_read(tp, 0x4, &start))
15782 offset = tg3_nvram_logical_addr(tp, offset);
15784 if (tg3_nvram_read(tp, offset, &val))
15787 if ((val & 0xfc000000) == 0x0c000000) {
15788 if (tg3_nvram_read(tp, offset + 4, &val))
15795 dst_off = strlen(tp->fw_ver);
15798 if (TG3_VER_SIZE - dst_off < 16 ||
15799 tg3_nvram_read(tp, offset + 8, &ver_offset))
15802 offset = offset + ver_offset - start;
15803 for (i = 0; i < 16; i += 4) {
15805 if (tg3_nvram_read_be32(tp, offset + i, &v))
15808 memcpy(tp->fw_ver + dst_off + i, &v, sizeof(v));
15813 if (tg3_nvram_read(tp, TG3_NVM_PTREV_BCVER, &ver_offset))
15816 major = (ver_offset & TG3_NVM_BCVER_MAJMSK) >>
15817 TG3_NVM_BCVER_MAJSFT;
15818 minor = ver_offset & TG3_NVM_BCVER_MINMSK;
15819 snprintf(&tp->fw_ver[dst_off], TG3_VER_SIZE - dst_off,
15820 "v%d.%02d", major, minor);
15824 static void tg3_read_hwsb_ver(struct tg3 *tp)
15826 u32 val, major, minor;
15828 /* Use native endian representation */
15829 if (tg3_nvram_read(tp, TG3_NVM_HWSB_CFG1, &val))
15832 major = (val & TG3_NVM_HWSB_CFG1_MAJMSK) >>
15833 TG3_NVM_HWSB_CFG1_MAJSFT;
15834 minor = (val & TG3_NVM_HWSB_CFG1_MINMSK) >>
15835 TG3_NVM_HWSB_CFG1_MINSFT;
15837 snprintf(&tp->fw_ver[0], 32, "sb v%d.%02d", major, minor);
15840 static void tg3_read_sb_ver(struct tg3 *tp, u32 val)
15842 u32 offset, major, minor, build;
15844 strncat(tp->fw_ver, "sb", TG3_VER_SIZE - strlen(tp->fw_ver) - 1);
15846 if ((val & TG3_EEPROM_SB_FORMAT_MASK) != TG3_EEPROM_SB_FORMAT_1)
15849 switch (val & TG3_EEPROM_SB_REVISION_MASK) {
15850 case TG3_EEPROM_SB_REVISION_0:
15851 offset = TG3_EEPROM_SB_F1R0_EDH_OFF;
15853 case TG3_EEPROM_SB_REVISION_2:
15854 offset = TG3_EEPROM_SB_F1R2_EDH_OFF;
15856 case TG3_EEPROM_SB_REVISION_3:
15857 offset = TG3_EEPROM_SB_F1R3_EDH_OFF;
15859 case TG3_EEPROM_SB_REVISION_4:
15860 offset = TG3_EEPROM_SB_F1R4_EDH_OFF;
15862 case TG3_EEPROM_SB_REVISION_5:
15863 offset = TG3_EEPROM_SB_F1R5_EDH_OFF;
15865 case TG3_EEPROM_SB_REVISION_6:
15866 offset = TG3_EEPROM_SB_F1R6_EDH_OFF;
15872 if (tg3_nvram_read(tp, offset, &val))
15875 build = (val & TG3_EEPROM_SB_EDH_BLD_MASK) >>
15876 TG3_EEPROM_SB_EDH_BLD_SHFT;
15877 major = (val & TG3_EEPROM_SB_EDH_MAJ_MASK) >>
15878 TG3_EEPROM_SB_EDH_MAJ_SHFT;
15879 minor = val & TG3_EEPROM_SB_EDH_MIN_MASK;
15881 if (minor > 99 || build > 26)
15884 offset = strlen(tp->fw_ver);
15885 snprintf(&tp->fw_ver[offset], TG3_VER_SIZE - offset,
15886 " v%d.%02d", major, minor);
15889 offset = strlen(tp->fw_ver);
15890 if (offset < TG3_VER_SIZE - 1)
15891 tp->fw_ver[offset] = 'a' + build - 1;
15895 static void tg3_read_mgmtfw_ver(struct tg3 *tp)
15897 u32 val, offset, start;
15900 for (offset = TG3_NVM_DIR_START;
15901 offset < TG3_NVM_DIR_END;
15902 offset += TG3_NVM_DIRENT_SIZE) {
15903 if (tg3_nvram_read(tp, offset, &val))
15906 if ((val >> TG3_NVM_DIRTYPE_SHIFT) == TG3_NVM_DIRTYPE_ASFINI)
15910 if (offset == TG3_NVM_DIR_END)
15913 if (!tg3_flag(tp, 5705_PLUS))
15914 start = 0x08000000;
15915 else if (tg3_nvram_read(tp, offset - 4, &start))
15918 if (tg3_nvram_read(tp, offset + 4, &offset) ||
15919 !tg3_fw_img_is_valid(tp, offset) ||
15920 tg3_nvram_read(tp, offset + 8, &val))
15923 offset += val - start;
15925 vlen = strlen(tp->fw_ver);
15927 tp->fw_ver[vlen++] = ',';
15928 tp->fw_ver[vlen++] = ' ';
15930 for (i = 0; i < 4; i++) {
15932 if (tg3_nvram_read_be32(tp, offset, &v))
15935 offset += sizeof(v);
15937 if (vlen > TG3_VER_SIZE - sizeof(v)) {
15938 memcpy(&tp->fw_ver[vlen], &v, TG3_VER_SIZE - vlen);
15942 memcpy(&tp->fw_ver[vlen], &v, sizeof(v));
15947 static void tg3_probe_ncsi(struct tg3 *tp)
15951 apedata = tg3_ape_read32(tp, TG3_APE_SEG_SIG);
15952 if (apedata != APE_SEG_SIG_MAGIC)
15955 apedata = tg3_ape_read32(tp, TG3_APE_FW_STATUS);
15956 if (!(apedata & APE_FW_STATUS_READY))
15959 if (tg3_ape_read32(tp, TG3_APE_FW_FEATURES) & TG3_APE_FW_FEATURE_NCSI)
15960 tg3_flag_set(tp, APE_HAS_NCSI);
15963 static void tg3_read_dash_ver(struct tg3 *tp)
15969 apedata = tg3_ape_read32(tp, TG3_APE_FW_VERSION);
15971 if (tg3_flag(tp, APE_HAS_NCSI))
15973 else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_5725)
15978 vlen = strlen(tp->fw_ver);
15980 snprintf(&tp->fw_ver[vlen], TG3_VER_SIZE - vlen, " %s v%d.%d.%d.%d",
15982 (apedata & APE_FW_VERSION_MAJMSK) >> APE_FW_VERSION_MAJSFT,
15983 (apedata & APE_FW_VERSION_MINMSK) >> APE_FW_VERSION_MINSFT,
15984 (apedata & APE_FW_VERSION_REVMSK) >> APE_FW_VERSION_REVSFT,
15985 (apedata & APE_FW_VERSION_BLDMSK));
15988 static void tg3_read_otp_ver(struct tg3 *tp)
15992 if (tg3_asic_rev(tp) != ASIC_REV_5762)
15995 if (!tg3_ape_otp_read(tp, OTP_ADDRESS_MAGIC0, &val) &&
15996 !tg3_ape_otp_read(tp, OTP_ADDRESS_MAGIC0 + 4, &val2) &&
15997 TG3_OTP_MAGIC0_VALID(val)) {
15998 u64 val64 = (u64) val << 32 | val2;
16002 for (i = 0; i < 7; i++) {
16003 if ((val64 & 0xff) == 0)
16005 ver = val64 & 0xff;
16008 vlen = strlen(tp->fw_ver);
16009 snprintf(&tp->fw_ver[vlen], TG3_VER_SIZE - vlen, " .%02d", ver);
16013 static void tg3_read_fw_ver(struct tg3 *tp)
16016 bool vpd_vers = false;
16018 if (tp->fw_ver[0] != 0)
16021 if (tg3_flag(tp, NO_NVRAM)) {
16022 strcat(tp->fw_ver, "sb");
16023 tg3_read_otp_ver(tp);
16027 if (tg3_nvram_read(tp, 0, &val))
16030 if (val == TG3_EEPROM_MAGIC)
16031 tg3_read_bc_ver(tp);
16032 else if ((val & TG3_EEPROM_MAGIC_FW_MSK) == TG3_EEPROM_MAGIC_FW)
16033 tg3_read_sb_ver(tp, val);
16034 else if ((val & TG3_EEPROM_MAGIC_HW_MSK) == TG3_EEPROM_MAGIC_HW)
16035 tg3_read_hwsb_ver(tp);
16037 if (tg3_flag(tp, ENABLE_ASF)) {
16038 if (tg3_flag(tp, ENABLE_APE)) {
16039 tg3_probe_ncsi(tp);
16041 tg3_read_dash_ver(tp);
16042 } else if (!vpd_vers) {
16043 tg3_read_mgmtfw_ver(tp);
16047 tp->fw_ver[TG3_VER_SIZE - 1] = 0;
16050 static inline u32 tg3_rx_ret_ring_size(struct tg3 *tp)
16052 if (tg3_flag(tp, LRG_PROD_RING_CAP))
16053 return TG3_RX_RET_MAX_SIZE_5717;
16054 else if (tg3_flag(tp, JUMBO_CAPABLE) && !tg3_flag(tp, 5780_CLASS))
16055 return TG3_RX_RET_MAX_SIZE_5700;
16057 return TG3_RX_RET_MAX_SIZE_5705;
16060 static const struct pci_device_id tg3_write_reorder_chipsets[] = {
16061 { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_FE_GATE_700C) },
16062 { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8131_BRIDGE) },
16063 { PCI_DEVICE(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8385_0) },
16067 static struct pci_dev *tg3_find_peer(struct tg3 *tp)
16069 struct pci_dev *peer;
16070 unsigned int func, devnr = tp->pdev->devfn & ~7;
16072 for (func = 0; func < 8; func++) {
16073 peer = pci_get_slot(tp->pdev->bus, devnr | func);
16074 if (peer && peer != tp->pdev)
16078 /* 5704 can be configured in single-port mode, set peer to
16079 * tp->pdev in that case.
16087 * We don't need to keep the refcount elevated; there's no way
16088 * to remove one half of this device without removing the other
16095 static void tg3_detect_asic_rev(struct tg3 *tp, u32 misc_ctrl_reg)
16097 tp->pci_chip_rev_id = misc_ctrl_reg >> MISC_HOST_CTRL_CHIPREV_SHIFT;
16098 if (tg3_asic_rev(tp) == ASIC_REV_USE_PROD_ID_REG) {
16101 /* All devices that use the alternate
16102 * ASIC REV location have a CPMU.
16104 tg3_flag_set(tp, CPMU_PRESENT);
16106 if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_5717 ||
16107 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5717_C ||
16108 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5718 ||
16109 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5719 ||
16110 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5720 ||
16111 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57767 ||
16112 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57764 ||
16113 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5762 ||
16114 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5725 ||
16115 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5727 ||
16116 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57787)
16117 reg = TG3PCI_GEN2_PRODID_ASICREV;
16118 else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57781 ||
16119 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57785 ||
16120 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57761 ||
16121 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57765 ||
16122 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57791 ||
16123 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57795 ||
16124 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57762 ||
16125 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57766 ||
16126 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57782 ||
16127 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57786)
16128 reg = TG3PCI_GEN15_PRODID_ASICREV;
16130 reg = TG3PCI_PRODID_ASICREV;
16132 pci_read_config_dword(tp->pdev, reg, &tp->pci_chip_rev_id);
16135 /* Wrong chip ID in 5752 A0. This code can be removed later
16136 * as A0 is not in production.
16138 if (tg3_chip_rev_id(tp) == CHIPREV_ID_5752_A0_HW)
16139 tp->pci_chip_rev_id = CHIPREV_ID_5752_A0;
16141 if (tg3_chip_rev_id(tp) == CHIPREV_ID_5717_C0)
16142 tp->pci_chip_rev_id = CHIPREV_ID_5720_A0;
16144 if (tg3_asic_rev(tp) == ASIC_REV_5717 ||
16145 tg3_asic_rev(tp) == ASIC_REV_5719 ||
16146 tg3_asic_rev(tp) == ASIC_REV_5720)
16147 tg3_flag_set(tp, 5717_PLUS);
16149 if (tg3_asic_rev(tp) == ASIC_REV_57765 ||
16150 tg3_asic_rev(tp) == ASIC_REV_57766)
16151 tg3_flag_set(tp, 57765_CLASS);
16153 if (tg3_flag(tp, 57765_CLASS) || tg3_flag(tp, 5717_PLUS) ||
16154 tg3_asic_rev(tp) == ASIC_REV_5762)
16155 tg3_flag_set(tp, 57765_PLUS);
16157 /* Intentionally exclude ASIC_REV_5906 */
16158 if (tg3_asic_rev(tp) == ASIC_REV_5755 ||
16159 tg3_asic_rev(tp) == ASIC_REV_5787 ||
16160 tg3_asic_rev(tp) == ASIC_REV_5784 ||
16161 tg3_asic_rev(tp) == ASIC_REV_5761 ||
16162 tg3_asic_rev(tp) == ASIC_REV_5785 ||
16163 tg3_asic_rev(tp) == ASIC_REV_57780 ||
16164 tg3_flag(tp, 57765_PLUS))
16165 tg3_flag_set(tp, 5755_PLUS);
16167 if (tg3_asic_rev(tp) == ASIC_REV_5780 ||
16168 tg3_asic_rev(tp) == ASIC_REV_5714)
16169 tg3_flag_set(tp, 5780_CLASS);
16171 if (tg3_asic_rev(tp) == ASIC_REV_5750 ||
16172 tg3_asic_rev(tp) == ASIC_REV_5752 ||
16173 tg3_asic_rev(tp) == ASIC_REV_5906 ||
16174 tg3_flag(tp, 5755_PLUS) ||
16175 tg3_flag(tp, 5780_CLASS))
16176 tg3_flag_set(tp, 5750_PLUS);
16178 if (tg3_asic_rev(tp) == ASIC_REV_5705 ||
16179 tg3_flag(tp, 5750_PLUS))
16180 tg3_flag_set(tp, 5705_PLUS);
16183 static bool tg3_10_100_only_device(struct tg3 *tp,
16184 const struct pci_device_id *ent)
16186 u32 grc_misc_cfg = tr32(GRC_MISC_CFG) & GRC_MISC_CFG_BOARD_ID_MASK;
16188 if ((tg3_asic_rev(tp) == ASIC_REV_5703 &&
16189 (grc_misc_cfg == 0x8000 || grc_misc_cfg == 0x4000)) ||
16190 (tp->phy_flags & TG3_PHYFLG_IS_FET))
16193 if (ent->driver_data & TG3_DRV_DATA_FLAG_10_100_ONLY) {
16194 if (tg3_asic_rev(tp) == ASIC_REV_5705) {
16195 if (ent->driver_data & TG3_DRV_DATA_FLAG_5705_10_100)
16205 static int tg3_get_invariants(struct tg3 *tp, const struct pci_device_id *ent)
16208 u32 pci_state_reg, grc_misc_cfg;
16213 /* Force memory write invalidate off. If we leave it on,
16214 * then on 5700_BX chips we have to enable a workaround.
16215 * The workaround is to set the TG3PCI_DMA_RW_CTRL boundary
16216 * to match the cacheline size. The Broadcom driver have this
16217 * workaround but turns MWI off all the times so never uses
16218 * it. This seems to suggest that the workaround is insufficient.
16220 pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd);
16221 pci_cmd &= ~PCI_COMMAND_INVALIDATE;
16222 pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd);
16224 /* Important! -- Make sure register accesses are byteswapped
16225 * correctly. Also, for those chips that require it, make
16226 * sure that indirect register accesses are enabled before
16227 * the first operation.
16229 pci_read_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
16231 tp->misc_host_ctrl |= (misc_ctrl_reg &
16232 MISC_HOST_CTRL_CHIPREV);
16233 pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
16234 tp->misc_host_ctrl);
16236 tg3_detect_asic_rev(tp, misc_ctrl_reg);
16238 /* If we have 5702/03 A1 or A2 on certain ICH chipsets,
16239 * we need to disable memory and use config. cycles
16240 * only to access all registers. The 5702/03 chips
16241 * can mistakenly decode the special cycles from the
16242 * ICH chipsets as memory write cycles, causing corruption
16243 * of register and memory space. Only certain ICH bridges
16244 * will drive special cycles with non-zero data during the
16245 * address phase which can fall within the 5703's address
16246 * range. This is not an ICH bug as the PCI spec allows
16247 * non-zero address during special cycles. However, only
16248 * these ICH bridges are known to drive non-zero addresses
16249 * during special cycles.
16251 * Since special cycles do not cross PCI bridges, we only
16252 * enable this workaround if the 5703 is on the secondary
16253 * bus of these ICH bridges.
16255 if ((tg3_chip_rev_id(tp) == CHIPREV_ID_5703_A1) ||
16256 (tg3_chip_rev_id(tp) == CHIPREV_ID_5703_A2)) {
16257 static struct tg3_dev_id {
16261 } ich_chipsets[] = {
16262 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AA_8,
16264 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AB_8,
16266 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_11,
16268 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_6,
16272 struct tg3_dev_id *pci_id = &ich_chipsets[0];
16273 struct pci_dev *bridge = NULL;
16275 while (pci_id->vendor != 0) {
16276 bridge = pci_get_device(pci_id->vendor, pci_id->device,
16282 if (pci_id->rev != PCI_ANY_ID) {
16283 if (bridge->revision > pci_id->rev)
16286 if (bridge->subordinate &&
16287 (bridge->subordinate->number ==
16288 tp->pdev->bus->number)) {
16289 tg3_flag_set(tp, ICH_WORKAROUND);
16290 pci_dev_put(bridge);
16296 if (tg3_asic_rev(tp) == ASIC_REV_5701) {
16297 static struct tg3_dev_id {
16300 } bridge_chipsets[] = {
16301 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_0 },
16302 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_1 },
16305 struct tg3_dev_id *pci_id = &bridge_chipsets[0];
16306 struct pci_dev *bridge = NULL;
16308 while (pci_id->vendor != 0) {
16309 bridge = pci_get_device(pci_id->vendor,
16316 if (bridge->subordinate &&
16317 (bridge->subordinate->number <=
16318 tp->pdev->bus->number) &&
16319 (bridge->subordinate->busn_res.end >=
16320 tp->pdev->bus->number)) {
16321 tg3_flag_set(tp, 5701_DMA_BUG);
16322 pci_dev_put(bridge);
16328 /* The EPB bridge inside 5714, 5715, and 5780 cannot support
16329 * DMA addresses > 40-bit. This bridge may have other additional
16330 * 57xx devices behind it in some 4-port NIC designs for example.
16331 * Any tg3 device found behind the bridge will also need the 40-bit
16334 if (tg3_flag(tp, 5780_CLASS)) {
16335 tg3_flag_set(tp, 40BIT_DMA_BUG);
16336 tp->msi_cap = tp->pdev->msi_cap;
16338 struct pci_dev *bridge = NULL;
16341 bridge = pci_get_device(PCI_VENDOR_ID_SERVERWORKS,
16342 PCI_DEVICE_ID_SERVERWORKS_EPB,
16344 if (bridge && bridge->subordinate &&
16345 (bridge->subordinate->number <=
16346 tp->pdev->bus->number) &&
16347 (bridge->subordinate->busn_res.end >=
16348 tp->pdev->bus->number)) {
16349 tg3_flag_set(tp, 40BIT_DMA_BUG);
16350 pci_dev_put(bridge);
16356 if (tg3_asic_rev(tp) == ASIC_REV_5704 ||
16357 tg3_asic_rev(tp) == ASIC_REV_5714)
16358 tp->pdev_peer = tg3_find_peer(tp);
16360 /* Determine TSO capabilities */
16361 if (tg3_chip_rev_id(tp) == CHIPREV_ID_5719_A0)
16362 ; /* Do nothing. HW bug. */
16363 else if (tg3_flag(tp, 57765_PLUS))
16364 tg3_flag_set(tp, HW_TSO_3);
16365 else if (tg3_flag(tp, 5755_PLUS) ||
16366 tg3_asic_rev(tp) == ASIC_REV_5906)
16367 tg3_flag_set(tp, HW_TSO_2);
16368 else if (tg3_flag(tp, 5750_PLUS)) {
16369 tg3_flag_set(tp, HW_TSO_1);
16370 tg3_flag_set(tp, TSO_BUG);
16371 if (tg3_asic_rev(tp) == ASIC_REV_5750 &&
16372 tg3_chip_rev_id(tp) >= CHIPREV_ID_5750_C2)
16373 tg3_flag_clear(tp, TSO_BUG);
16374 } else if (tg3_asic_rev(tp) != ASIC_REV_5700 &&
16375 tg3_asic_rev(tp) != ASIC_REV_5701 &&
16376 tg3_chip_rev_id(tp) != CHIPREV_ID_5705_A0) {
16377 tg3_flag_set(tp, FW_TSO);
16378 tg3_flag_set(tp, TSO_BUG);
16379 if (tg3_asic_rev(tp) == ASIC_REV_5705)
16380 tp->fw_needed = FIRMWARE_TG3TSO5;
16382 tp->fw_needed = FIRMWARE_TG3TSO;
16385 /* Selectively allow TSO based on operating conditions */
16386 if (tg3_flag(tp, HW_TSO_1) ||
16387 tg3_flag(tp, HW_TSO_2) ||
16388 tg3_flag(tp, HW_TSO_3) ||
16389 tg3_flag(tp, FW_TSO)) {
16390 /* For firmware TSO, assume ASF is disabled.
16391 * We'll disable TSO later if we discover ASF
16392 * is enabled in tg3_get_eeprom_hw_cfg().
16394 tg3_flag_set(tp, TSO_CAPABLE);
16396 tg3_flag_clear(tp, TSO_CAPABLE);
16397 tg3_flag_clear(tp, TSO_BUG);
16398 tp->fw_needed = NULL;
16401 if (tg3_chip_rev_id(tp) == CHIPREV_ID_5701_A0)
16402 tp->fw_needed = FIRMWARE_TG3;
16404 if (tg3_asic_rev(tp) == ASIC_REV_57766)
16405 tp->fw_needed = FIRMWARE_TG357766;
16409 if (tg3_flag(tp, 5750_PLUS)) {
16410 tg3_flag_set(tp, SUPPORT_MSI);
16411 if (tg3_chip_rev(tp) == CHIPREV_5750_AX ||
16412 tg3_chip_rev(tp) == CHIPREV_5750_BX ||
16413 (tg3_asic_rev(tp) == ASIC_REV_5714 &&
16414 tg3_chip_rev_id(tp) <= CHIPREV_ID_5714_A2 &&
16415 tp->pdev_peer == tp->pdev))
16416 tg3_flag_clear(tp, SUPPORT_MSI);
16418 if (tg3_flag(tp, 5755_PLUS) ||
16419 tg3_asic_rev(tp) == ASIC_REV_5906) {
16420 tg3_flag_set(tp, 1SHOT_MSI);
16423 if (tg3_flag(tp, 57765_PLUS)) {
16424 tg3_flag_set(tp, SUPPORT_MSIX);
16425 tp->irq_max = TG3_IRQ_MAX_VECS;
16431 if (tp->irq_max > 1) {
16432 tp->rxq_max = TG3_RSS_MAX_NUM_QS;
16433 tg3_rss_init_dflt_indir_tbl(tp, TG3_RSS_MAX_NUM_QS);
16435 if (tg3_asic_rev(tp) == ASIC_REV_5719 ||
16436 tg3_asic_rev(tp) == ASIC_REV_5720)
16437 tp->txq_max = tp->irq_max - 1;
16440 if (tg3_flag(tp, 5755_PLUS) ||
16441 tg3_asic_rev(tp) == ASIC_REV_5906)
16442 tg3_flag_set(tp, SHORT_DMA_BUG);
16444 if (tg3_asic_rev(tp) == ASIC_REV_5719)
16445 tp->dma_limit = TG3_TX_BD_DMA_MAX_4K;
16447 if (tg3_asic_rev(tp) == ASIC_REV_5717 ||
16448 tg3_asic_rev(tp) == ASIC_REV_5719 ||
16449 tg3_asic_rev(tp) == ASIC_REV_5720 ||
16450 tg3_asic_rev(tp) == ASIC_REV_5762)
16451 tg3_flag_set(tp, LRG_PROD_RING_CAP);
16453 if (tg3_flag(tp, 57765_PLUS) &&
16454 tg3_chip_rev_id(tp) != CHIPREV_ID_5719_A0)
16455 tg3_flag_set(tp, USE_JUMBO_BDFLAG);
16457 if (!tg3_flag(tp, 5705_PLUS) ||
16458 tg3_flag(tp, 5780_CLASS) ||
16459 tg3_flag(tp, USE_JUMBO_BDFLAG))
16460 tg3_flag_set(tp, JUMBO_CAPABLE);
16462 pci_read_config_dword(tp->pdev, TG3PCI_PCISTATE,
16465 if (pci_is_pcie(tp->pdev)) {
16468 tg3_flag_set(tp, PCI_EXPRESS);
16470 pcie_capability_read_word(tp->pdev, PCI_EXP_LNKCTL, &lnkctl);
16471 if (lnkctl & PCI_EXP_LNKCTL_CLKREQ_EN) {
16472 if (tg3_asic_rev(tp) == ASIC_REV_5906) {
16473 tg3_flag_clear(tp, HW_TSO_2);
16474 tg3_flag_clear(tp, TSO_CAPABLE);
16476 if (tg3_asic_rev(tp) == ASIC_REV_5784 ||
16477 tg3_asic_rev(tp) == ASIC_REV_5761 ||
16478 tg3_chip_rev_id(tp) == CHIPREV_ID_57780_A0 ||
16479 tg3_chip_rev_id(tp) == CHIPREV_ID_57780_A1)
16480 tg3_flag_set(tp, CLKREQ_BUG);
16481 } else if (tg3_chip_rev_id(tp) == CHIPREV_ID_5717_A0) {
16482 tg3_flag_set(tp, L1PLLPD_EN);
16484 } else if (tg3_asic_rev(tp) == ASIC_REV_5785) {
16485 /* BCM5785 devices are effectively PCIe devices, and should
16486 * follow PCIe codepaths, but do not have a PCIe capabilities
16489 tg3_flag_set(tp, PCI_EXPRESS);
16490 } else if (!tg3_flag(tp, 5705_PLUS) ||
16491 tg3_flag(tp, 5780_CLASS)) {
16492 tp->pcix_cap = pci_find_capability(tp->pdev, PCI_CAP_ID_PCIX);
16493 if (!tp->pcix_cap) {
16494 dev_err(&tp->pdev->dev,
16495 "Cannot find PCI-X capability, aborting\n");
16499 if (!(pci_state_reg & PCISTATE_CONV_PCI_MODE))
16500 tg3_flag_set(tp, PCIX_MODE);
16503 /* If we have an AMD 762 or VIA K8T800 chipset, write
16504 * reordering to the mailbox registers done by the host
16505 * controller can cause major troubles. We read back from
16506 * every mailbox register write to force the writes to be
16507 * posted to the chip in order.
16509 if (pci_dev_present(tg3_write_reorder_chipsets) &&
16510 !tg3_flag(tp, PCI_EXPRESS))
16511 tg3_flag_set(tp, MBOX_WRITE_REORDER);
16513 pci_read_config_byte(tp->pdev, PCI_CACHE_LINE_SIZE,
16514 &tp->pci_cacheline_sz);
16515 pci_read_config_byte(tp->pdev, PCI_LATENCY_TIMER,
16516 &tp->pci_lat_timer);
16517 if (tg3_asic_rev(tp) == ASIC_REV_5703 &&
16518 tp->pci_lat_timer < 64) {
16519 tp->pci_lat_timer = 64;
16520 pci_write_config_byte(tp->pdev, PCI_LATENCY_TIMER,
16521 tp->pci_lat_timer);
16524 /* Important! -- It is critical that the PCI-X hw workaround
16525 * situation is decided before the first MMIO register access.
16527 if (tg3_chip_rev(tp) == CHIPREV_5700_BX) {
16528 /* 5700 BX chips need to have their TX producer index
16529 * mailboxes written twice to workaround a bug.
16531 tg3_flag_set(tp, TXD_MBOX_HWBUG);
16533 /* If we are in PCI-X mode, enable register write workaround.
16535 * The workaround is to use indirect register accesses
16536 * for all chip writes not to mailbox registers.
16538 if (tg3_flag(tp, PCIX_MODE)) {
16541 tg3_flag_set(tp, PCIX_TARGET_HWBUG);
16543 /* The chip can have it's power management PCI config
16544 * space registers clobbered due to this bug.
16545 * So explicitly force the chip into D0 here.
16547 pci_read_config_dword(tp->pdev,
16548 tp->pdev->pm_cap + PCI_PM_CTRL,
16550 pm_reg &= ~PCI_PM_CTRL_STATE_MASK;
16551 pm_reg |= PCI_PM_CTRL_PME_ENABLE | 0 /* D0 */;
16552 pci_write_config_dword(tp->pdev,
16553 tp->pdev->pm_cap + PCI_PM_CTRL,
16556 /* Also, force SERR#/PERR# in PCI command. */
16557 pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd);
16558 pci_cmd |= PCI_COMMAND_PARITY | PCI_COMMAND_SERR;
16559 pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd);
16563 if ((pci_state_reg & PCISTATE_BUS_SPEED_HIGH) != 0)
16564 tg3_flag_set(tp, PCI_HIGH_SPEED);
16565 if ((pci_state_reg & PCISTATE_BUS_32BIT) != 0)
16566 tg3_flag_set(tp, PCI_32BIT);
16568 /* Chip-specific fixup from Broadcom driver */
16569 if ((tg3_chip_rev_id(tp) == CHIPREV_ID_5704_A0) &&
16570 (!(pci_state_reg & PCISTATE_RETRY_SAME_DMA))) {
16571 pci_state_reg |= PCISTATE_RETRY_SAME_DMA;
16572 pci_write_config_dword(tp->pdev, TG3PCI_PCISTATE, pci_state_reg);
16575 /* Default fast path register access methods */
16576 tp->read32 = tg3_read32;
16577 tp->write32 = tg3_write32;
16578 tp->read32_mbox = tg3_read32;
16579 tp->write32_mbox = tg3_write32;
16580 tp->write32_tx_mbox = tg3_write32;
16581 tp->write32_rx_mbox = tg3_write32;
16583 /* Various workaround register access methods */
16584 if (tg3_flag(tp, PCIX_TARGET_HWBUG))
16585 tp->write32 = tg3_write_indirect_reg32;
16586 else if (tg3_asic_rev(tp) == ASIC_REV_5701 ||
16587 (tg3_flag(tp, PCI_EXPRESS) &&
16588 tg3_chip_rev_id(tp) == CHIPREV_ID_5750_A0)) {
16590 * Back to back register writes can cause problems on these
16591 * chips, the workaround is to read back all reg writes
16592 * except those to mailbox regs.
16594 * See tg3_write_indirect_reg32().
16596 tp->write32 = tg3_write_flush_reg32;
16599 if (tg3_flag(tp, TXD_MBOX_HWBUG) || tg3_flag(tp, MBOX_WRITE_REORDER)) {
16600 tp->write32_tx_mbox = tg3_write32_tx_mbox;
16601 if (tg3_flag(tp, MBOX_WRITE_REORDER))
16602 tp->write32_rx_mbox = tg3_write_flush_reg32;
16605 if (tg3_flag(tp, ICH_WORKAROUND)) {
16606 tp->read32 = tg3_read_indirect_reg32;
16607 tp->write32 = tg3_write_indirect_reg32;
16608 tp->read32_mbox = tg3_read_indirect_mbox;
16609 tp->write32_mbox = tg3_write_indirect_mbox;
16610 tp->write32_tx_mbox = tg3_write_indirect_mbox;
16611 tp->write32_rx_mbox = tg3_write_indirect_mbox;
16616 pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd);
16617 pci_cmd &= ~PCI_COMMAND_MEMORY;
16618 pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd);
16620 if (tg3_asic_rev(tp) == ASIC_REV_5906) {
16621 tp->read32_mbox = tg3_read32_mbox_5906;
16622 tp->write32_mbox = tg3_write32_mbox_5906;
16623 tp->write32_tx_mbox = tg3_write32_mbox_5906;
16624 tp->write32_rx_mbox = tg3_write32_mbox_5906;
16627 if (tp->write32 == tg3_write_indirect_reg32 ||
16628 (tg3_flag(tp, PCIX_MODE) &&
16629 (tg3_asic_rev(tp) == ASIC_REV_5700 ||
16630 tg3_asic_rev(tp) == ASIC_REV_5701)))
16631 tg3_flag_set(tp, SRAM_USE_CONFIG);
16633 /* The memory arbiter has to be enabled in order for SRAM accesses
16634 * to succeed. Normally on powerup the tg3 chip firmware will make
16635 * sure it is enabled, but other entities such as system netboot
16636 * code might disable it.
16638 val = tr32(MEMARB_MODE);
16639 tw32(MEMARB_MODE, val | MEMARB_MODE_ENABLE);
16641 tp->pci_fn = PCI_FUNC(tp->pdev->devfn) & 3;
16642 if (tg3_asic_rev(tp) == ASIC_REV_5704 ||
16643 tg3_flag(tp, 5780_CLASS)) {
16644 if (tg3_flag(tp, PCIX_MODE)) {
16645 pci_read_config_dword(tp->pdev,
16646 tp->pcix_cap + PCI_X_STATUS,
16648 tp->pci_fn = val & 0x7;
16650 } else if (tg3_asic_rev(tp) == ASIC_REV_5717 ||
16651 tg3_asic_rev(tp) == ASIC_REV_5719 ||
16652 tg3_asic_rev(tp) == ASIC_REV_5720) {
16653 tg3_read_mem(tp, NIC_SRAM_CPMU_STATUS, &val);
16654 if ((val & NIC_SRAM_CPMUSTAT_SIG_MSK) != NIC_SRAM_CPMUSTAT_SIG)
16655 val = tr32(TG3_CPMU_STATUS);
16657 if (tg3_asic_rev(tp) == ASIC_REV_5717)
16658 tp->pci_fn = (val & TG3_CPMU_STATUS_FMSK_5717) ? 1 : 0;
16660 tp->pci_fn = (val & TG3_CPMU_STATUS_FMSK_5719) >>
16661 TG3_CPMU_STATUS_FSHFT_5719;
16664 if (tg3_flag(tp, FLUSH_POSTED_WRITES)) {
16665 tp->write32_tx_mbox = tg3_write_flush_reg32;
16666 tp->write32_rx_mbox = tg3_write_flush_reg32;
16669 /* Get eeprom hw config before calling tg3_set_power_state().
16670 * In particular, the TG3_FLAG_IS_NIC flag must be
16671 * determined before calling tg3_set_power_state() so that
16672 * we know whether or not to switch out of Vaux power.
16673 * When the flag is set, it means that GPIO1 is used for eeprom
16674 * write protect and also implies that it is a LOM where GPIOs
16675 * are not used to switch power.
16677 tg3_get_eeprom_hw_cfg(tp);
16679 if (tg3_flag(tp, FW_TSO) && tg3_flag(tp, ENABLE_ASF)) {
16680 tg3_flag_clear(tp, TSO_CAPABLE);
16681 tg3_flag_clear(tp, TSO_BUG);
16682 tp->fw_needed = NULL;
16685 if (tg3_flag(tp, ENABLE_APE)) {
16686 /* Allow reads and writes to the
16687 * APE register and memory space.
16689 pci_state_reg |= PCISTATE_ALLOW_APE_CTLSPC_WR |
16690 PCISTATE_ALLOW_APE_SHMEM_WR |
16691 PCISTATE_ALLOW_APE_PSPACE_WR;
16692 pci_write_config_dword(tp->pdev, TG3PCI_PCISTATE,
16695 tg3_ape_lock_init(tp);
16696 tp->ape_hb_interval =
16697 msecs_to_jiffies(APE_HOST_HEARTBEAT_INT_5SEC);
16700 /* Set up tp->grc_local_ctrl before calling
16701 * tg3_pwrsrc_switch_to_vmain(). GPIO1 driven high
16702 * will bring 5700's external PHY out of reset.
16703 * It is also used as eeprom write protect on LOMs.
16705 tp->grc_local_ctrl = GRC_LCLCTRL_INT_ON_ATTN | GRC_LCLCTRL_AUTO_SEEPROM;
16706 if (tg3_asic_rev(tp) == ASIC_REV_5700 ||
16707 tg3_flag(tp, EEPROM_WRITE_PROT))
16708 tp->grc_local_ctrl |= (GRC_LCLCTRL_GPIO_OE1 |
16709 GRC_LCLCTRL_GPIO_OUTPUT1);
16710 /* Unused GPIO3 must be driven as output on 5752 because there
16711 * are no pull-up resistors on unused GPIO pins.
16713 else if (tg3_asic_rev(tp) == ASIC_REV_5752)
16714 tp->grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE3;
16716 if (tg3_asic_rev(tp) == ASIC_REV_5755 ||
16717 tg3_asic_rev(tp) == ASIC_REV_57780 ||
16718 tg3_flag(tp, 57765_CLASS))
16719 tp->grc_local_ctrl |= GRC_LCLCTRL_GPIO_UART_SEL;
16721 if (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5761 ||
16722 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5761S) {
16723 /* Turn off the debug UART. */
16724 tp->grc_local_ctrl |= GRC_LCLCTRL_GPIO_UART_SEL;
16725 if (tg3_flag(tp, IS_NIC))
16726 /* Keep VMain power. */
16727 tp->grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE0 |
16728 GRC_LCLCTRL_GPIO_OUTPUT0;
16731 if (tg3_asic_rev(tp) == ASIC_REV_5762)
16732 tp->grc_local_ctrl |=
16733 tr32(GRC_LOCAL_CTRL) & GRC_LCLCTRL_GPIO_UART_SEL;
16735 /* Switch out of Vaux if it is a NIC */
16736 tg3_pwrsrc_switch_to_vmain(tp);
16738 /* Derive initial jumbo mode from MTU assigned in
16739 * ether_setup() via the alloc_etherdev() call
16741 if (tp->dev->mtu > ETH_DATA_LEN && !tg3_flag(tp, 5780_CLASS))
16742 tg3_flag_set(tp, JUMBO_RING_ENABLE);
16744 /* Determine WakeOnLan speed to use. */
16745 if (tg3_asic_rev(tp) == ASIC_REV_5700 ||
16746 tg3_chip_rev_id(tp) == CHIPREV_ID_5701_A0 ||
16747 tg3_chip_rev_id(tp) == CHIPREV_ID_5701_B0 ||
16748 tg3_chip_rev_id(tp) == CHIPREV_ID_5701_B2) {
16749 tg3_flag_clear(tp, WOL_SPEED_100MB);
16751 tg3_flag_set(tp, WOL_SPEED_100MB);
16754 if (tg3_asic_rev(tp) == ASIC_REV_5906)
16755 tp->phy_flags |= TG3_PHYFLG_IS_FET;
16757 /* A few boards don't want Ethernet@WireSpeed phy feature */
16758 if (tg3_asic_rev(tp) == ASIC_REV_5700 ||
16759 (tg3_asic_rev(tp) == ASIC_REV_5705 &&
16760 (tg3_chip_rev_id(tp) != CHIPREV_ID_5705_A0) &&
16761 (tg3_chip_rev_id(tp) != CHIPREV_ID_5705_A1)) ||
16762 (tp->phy_flags & TG3_PHYFLG_IS_FET) ||
16763 (tp->phy_flags & TG3_PHYFLG_ANY_SERDES))
16764 tp->phy_flags |= TG3_PHYFLG_NO_ETH_WIRE_SPEED;
16766 if (tg3_chip_rev(tp) == CHIPREV_5703_AX ||
16767 tg3_chip_rev(tp) == CHIPREV_5704_AX)
16768 tp->phy_flags |= TG3_PHYFLG_ADC_BUG;
16769 if (tg3_chip_rev_id(tp) == CHIPREV_ID_5704_A0)
16770 tp->phy_flags |= TG3_PHYFLG_5704_A0_BUG;
16772 if (tg3_flag(tp, 5705_PLUS) &&
16773 !(tp->phy_flags & TG3_PHYFLG_IS_FET) &&
16774 tg3_asic_rev(tp) != ASIC_REV_5785 &&
16775 tg3_asic_rev(tp) != ASIC_REV_57780 &&
16776 !tg3_flag(tp, 57765_PLUS)) {
16777 if (tg3_asic_rev(tp) == ASIC_REV_5755 ||
16778 tg3_asic_rev(tp) == ASIC_REV_5787 ||
16779 tg3_asic_rev(tp) == ASIC_REV_5784 ||
16780 tg3_asic_rev(tp) == ASIC_REV_5761) {
16781 if (tp->pdev->device != PCI_DEVICE_ID_TIGON3_5756 &&
16782 tp->pdev->device != PCI_DEVICE_ID_TIGON3_5722)
16783 tp->phy_flags |= TG3_PHYFLG_JITTER_BUG;
16784 if (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5755M)
16785 tp->phy_flags |= TG3_PHYFLG_ADJUST_TRIM;
16787 tp->phy_flags |= TG3_PHYFLG_BER_BUG;
16790 if (tg3_asic_rev(tp) == ASIC_REV_5784 &&
16791 tg3_chip_rev(tp) != CHIPREV_5784_AX) {
16792 tp->phy_otp = tg3_read_otp_phycfg(tp);
16793 if (tp->phy_otp == 0)
16794 tp->phy_otp = TG3_OTP_DEFAULT;
16797 if (tg3_flag(tp, CPMU_PRESENT))
16798 tp->mi_mode = MAC_MI_MODE_500KHZ_CONST;
16800 tp->mi_mode = MAC_MI_MODE_BASE;
16802 tp->coalesce_mode = 0;
16803 if (tg3_chip_rev(tp) != CHIPREV_5700_AX &&
16804 tg3_chip_rev(tp) != CHIPREV_5700_BX)
16805 tp->coalesce_mode |= HOSTCC_MODE_32BYTE;
16807 /* Set these bits to enable statistics workaround. */
16808 if (tg3_asic_rev(tp) == ASIC_REV_5717 ||
16809 tg3_asic_rev(tp) == ASIC_REV_5762 ||
16810 tg3_chip_rev_id(tp) == CHIPREV_ID_5719_A0 ||
16811 tg3_chip_rev_id(tp) == CHIPREV_ID_5720_A0) {
16812 tp->coalesce_mode |= HOSTCC_MODE_ATTN;
16813 tp->grc_mode |= GRC_MODE_IRQ_ON_FLOW_ATTN;
16816 if (tg3_asic_rev(tp) == ASIC_REV_5785 ||
16817 tg3_asic_rev(tp) == ASIC_REV_57780)
16818 tg3_flag_set(tp, USE_PHYLIB);
16820 err = tg3_mdio_init(tp);
16824 /* Initialize data/descriptor byte/word swapping. */
16825 val = tr32(GRC_MODE);
16826 if (tg3_asic_rev(tp) == ASIC_REV_5720 ||
16827 tg3_asic_rev(tp) == ASIC_REV_5762)
16828 val &= (GRC_MODE_BYTE_SWAP_B2HRX_DATA |
16829 GRC_MODE_WORD_SWAP_B2HRX_DATA |
16830 GRC_MODE_B2HRX_ENABLE |
16831 GRC_MODE_HTX2B_ENABLE |
16832 GRC_MODE_HOST_STACKUP);
16834 val &= GRC_MODE_HOST_STACKUP;
16836 tw32(GRC_MODE, val | tp->grc_mode);
16838 tg3_switch_clocks(tp);
16840 /* Clear this out for sanity. */
16841 tw32(TG3PCI_MEM_WIN_BASE_ADDR, 0);
16843 /* Clear TG3PCI_REG_BASE_ADDR to prevent hangs. */
16844 tw32(TG3PCI_REG_BASE_ADDR, 0);
16846 pci_read_config_dword(tp->pdev, TG3PCI_PCISTATE,
16848 if ((pci_state_reg & PCISTATE_CONV_PCI_MODE) == 0 &&
16849 !tg3_flag(tp, PCIX_TARGET_HWBUG)) {
16850 if (tg3_chip_rev_id(tp) == CHIPREV_ID_5701_A0 ||
16851 tg3_chip_rev_id(tp) == CHIPREV_ID_5701_B0 ||
16852 tg3_chip_rev_id(tp) == CHIPREV_ID_5701_B2 ||
16853 tg3_chip_rev_id(tp) == CHIPREV_ID_5701_B5) {
16854 void __iomem *sram_base;
16856 /* Write some dummy words into the SRAM status block
16857 * area, see if it reads back correctly. If the return
16858 * value is bad, force enable the PCIX workaround.
16860 sram_base = tp->regs + NIC_SRAM_WIN_BASE + NIC_SRAM_STATS_BLK;
16862 writel(0x00000000, sram_base);
16863 writel(0x00000000, sram_base + 4);
16864 writel(0xffffffff, sram_base + 4);
16865 if (readl(sram_base) != 0x00000000)
16866 tg3_flag_set(tp, PCIX_TARGET_HWBUG);
16871 tg3_nvram_init(tp);
16873 /* If the device has an NVRAM, no need to load patch firmware */
16874 if (tg3_asic_rev(tp) == ASIC_REV_57766 &&
16875 !tg3_flag(tp, NO_NVRAM))
16876 tp->fw_needed = NULL;
16878 grc_misc_cfg = tr32(GRC_MISC_CFG);
16879 grc_misc_cfg &= GRC_MISC_CFG_BOARD_ID_MASK;
16881 if (tg3_asic_rev(tp) == ASIC_REV_5705 &&
16882 (grc_misc_cfg == GRC_MISC_CFG_BOARD_ID_5788 ||
16883 grc_misc_cfg == GRC_MISC_CFG_BOARD_ID_5788M))
16884 tg3_flag_set(tp, IS_5788);
16886 if (!tg3_flag(tp, IS_5788) &&
16887 tg3_asic_rev(tp) != ASIC_REV_5700)
16888 tg3_flag_set(tp, TAGGED_STATUS);
16889 if (tg3_flag(tp, TAGGED_STATUS)) {
16890 tp->coalesce_mode |= (HOSTCC_MODE_CLRTICK_RXBD |
16891 HOSTCC_MODE_CLRTICK_TXBD);
16893 tp->misc_host_ctrl |= MISC_HOST_CTRL_TAGGED_STATUS;
16894 pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
16895 tp->misc_host_ctrl);
16898 /* Preserve the APE MAC_MODE bits */
16899 if (tg3_flag(tp, ENABLE_APE))
16900 tp->mac_mode = MAC_MODE_APE_TX_EN | MAC_MODE_APE_RX_EN;
16904 if (tg3_10_100_only_device(tp, ent))
16905 tp->phy_flags |= TG3_PHYFLG_10_100_ONLY;
16907 err = tg3_phy_probe(tp);
16909 dev_err(&tp->pdev->dev, "phy probe failed, err %d\n", err);
16910 /* ... but do not return immediately ... */
16915 tg3_read_fw_ver(tp);
16917 if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES) {
16918 tp->phy_flags &= ~TG3_PHYFLG_USE_MI_INTERRUPT;
16920 if (tg3_asic_rev(tp) == ASIC_REV_5700)
16921 tp->phy_flags |= TG3_PHYFLG_USE_MI_INTERRUPT;
16923 tp->phy_flags &= ~TG3_PHYFLG_USE_MI_INTERRUPT;
16926 /* 5700 {AX,BX} chips have a broken status block link
16927 * change bit implementation, so we must use the
16928 * status register in those cases.
16930 if (tg3_asic_rev(tp) == ASIC_REV_5700)
16931 tg3_flag_set(tp, USE_LINKCHG_REG);
16933 tg3_flag_clear(tp, USE_LINKCHG_REG);
16935 /* The led_ctrl is set during tg3_phy_probe, here we might
16936 * have to force the link status polling mechanism based
16937 * upon subsystem IDs.
16939 if (tp->pdev->subsystem_vendor == PCI_VENDOR_ID_DELL &&
16940 tg3_asic_rev(tp) == ASIC_REV_5701 &&
16941 !(tp->phy_flags & TG3_PHYFLG_PHY_SERDES)) {
16942 tp->phy_flags |= TG3_PHYFLG_USE_MI_INTERRUPT;
16943 tg3_flag_set(tp, USE_LINKCHG_REG);
16946 /* For all SERDES we poll the MAC status register. */
16947 if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES)
16948 tg3_flag_set(tp, POLL_SERDES);
16950 tg3_flag_clear(tp, POLL_SERDES);
16952 if (tg3_flag(tp, ENABLE_APE) && tg3_flag(tp, ENABLE_ASF))
16953 tg3_flag_set(tp, POLL_CPMU_LINK);
16955 tp->rx_offset = NET_SKB_PAD + NET_IP_ALIGN;
16956 tp->rx_copy_thresh = TG3_RX_COPY_THRESHOLD;
16957 if (tg3_asic_rev(tp) == ASIC_REV_5701 &&
16958 tg3_flag(tp, PCIX_MODE)) {
16959 tp->rx_offset = NET_SKB_PAD;
16960 #ifndef CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS
16961 tp->rx_copy_thresh = ~(u16)0;
16965 tp->rx_std_ring_mask = TG3_RX_STD_RING_SIZE(tp) - 1;
16966 tp->rx_jmb_ring_mask = TG3_RX_JMB_RING_SIZE(tp) - 1;
16967 tp->rx_ret_ring_mask = tg3_rx_ret_ring_size(tp) - 1;
16969 tp->rx_std_max_post = tp->rx_std_ring_mask + 1;
16971 /* Increment the rx prod index on the rx std ring by at most
16972 * 8 for these chips to workaround hw errata.
16974 if (tg3_asic_rev(tp) == ASIC_REV_5750 ||
16975 tg3_asic_rev(tp) == ASIC_REV_5752 ||
16976 tg3_asic_rev(tp) == ASIC_REV_5755)
16977 tp->rx_std_max_post = 8;
16979 if (tg3_flag(tp, ASPM_WORKAROUND))
16980 tp->pwrmgmt_thresh = tr32(PCIE_PWR_MGMT_THRESH) &
16981 PCIE_PWR_MGMT_L1_THRESH_MSK;
16986 #ifdef CONFIG_SPARC
16987 static int tg3_get_macaddr_sparc(struct tg3 *tp)
16989 struct net_device *dev = tp->dev;
16990 struct pci_dev *pdev = tp->pdev;
16991 struct device_node *dp = pci_device_to_OF_node(pdev);
16992 const unsigned char *addr;
16995 addr = of_get_property(dp, "local-mac-address", &len);
16996 if (addr && len == ETH_ALEN) {
16997 memcpy(dev->dev_addr, addr, ETH_ALEN);
17003 static int tg3_get_default_macaddr_sparc(struct tg3 *tp)
17005 struct net_device *dev = tp->dev;
17007 memcpy(dev->dev_addr, idprom->id_ethaddr, ETH_ALEN);
17012 static int tg3_get_device_address(struct tg3 *tp)
17014 struct net_device *dev = tp->dev;
17015 u32 hi, lo, mac_offset;
17019 #ifdef CONFIG_SPARC
17020 if (!tg3_get_macaddr_sparc(tp))
17024 if (tg3_flag(tp, IS_SSB_CORE)) {
17025 err = ssb_gige_get_macaddr(tp->pdev, &dev->dev_addr[0]);
17026 if (!err && is_valid_ether_addr(&dev->dev_addr[0]))
17031 if (tg3_asic_rev(tp) == ASIC_REV_5704 ||
17032 tg3_flag(tp, 5780_CLASS)) {
17033 if (tr32(TG3PCI_DUAL_MAC_CTRL) & DUAL_MAC_CTRL_ID)
17035 if (tg3_nvram_lock(tp))
17036 tw32_f(NVRAM_CMD, NVRAM_CMD_RESET);
17038 tg3_nvram_unlock(tp);
17039 } else if (tg3_flag(tp, 5717_PLUS)) {
17040 if (tp->pci_fn & 1)
17042 if (tp->pci_fn > 1)
17043 mac_offset += 0x18c;
17044 } else if (tg3_asic_rev(tp) == ASIC_REV_5906)
17047 /* First try to get it from MAC address mailbox. */
17048 tg3_read_mem(tp, NIC_SRAM_MAC_ADDR_HIGH_MBOX, &hi);
17049 if ((hi >> 16) == 0x484b) {
17050 dev->dev_addr[0] = (hi >> 8) & 0xff;
17051 dev->dev_addr[1] = (hi >> 0) & 0xff;
17053 tg3_read_mem(tp, NIC_SRAM_MAC_ADDR_LOW_MBOX, &lo);
17054 dev->dev_addr[2] = (lo >> 24) & 0xff;
17055 dev->dev_addr[3] = (lo >> 16) & 0xff;
17056 dev->dev_addr[4] = (lo >> 8) & 0xff;
17057 dev->dev_addr[5] = (lo >> 0) & 0xff;
17059 /* Some old bootcode may report a 0 MAC address in SRAM */
17060 addr_ok = is_valid_ether_addr(&dev->dev_addr[0]);
17063 /* Next, try NVRAM. */
17064 if (!tg3_flag(tp, NO_NVRAM) &&
17065 !tg3_nvram_read_be32(tp, mac_offset + 0, &hi) &&
17066 !tg3_nvram_read_be32(tp, mac_offset + 4, &lo)) {
17067 memcpy(&dev->dev_addr[0], ((char *)&hi) + 2, 2);
17068 memcpy(&dev->dev_addr[2], (char *)&lo, sizeof(lo));
17070 /* Finally just fetch it out of the MAC control regs. */
17072 hi = tr32(MAC_ADDR_0_HIGH);
17073 lo = tr32(MAC_ADDR_0_LOW);
17075 dev->dev_addr[5] = lo & 0xff;
17076 dev->dev_addr[4] = (lo >> 8) & 0xff;
17077 dev->dev_addr[3] = (lo >> 16) & 0xff;
17078 dev->dev_addr[2] = (lo >> 24) & 0xff;
17079 dev->dev_addr[1] = hi & 0xff;
17080 dev->dev_addr[0] = (hi >> 8) & 0xff;
17084 if (!is_valid_ether_addr(&dev->dev_addr[0])) {
17085 #ifdef CONFIG_SPARC
17086 if (!tg3_get_default_macaddr_sparc(tp))
17094 #define BOUNDARY_SINGLE_CACHELINE 1
17095 #define BOUNDARY_MULTI_CACHELINE 2
17097 static u32 tg3_calc_dma_bndry(struct tg3 *tp, u32 val)
17099 int cacheline_size;
17103 pci_read_config_byte(tp->pdev, PCI_CACHE_LINE_SIZE, &byte);
17105 cacheline_size = 1024;
17107 cacheline_size = (int) byte * 4;
17109 /* On 5703 and later chips, the boundary bits have no
17112 if (tg3_asic_rev(tp) != ASIC_REV_5700 &&
17113 tg3_asic_rev(tp) != ASIC_REV_5701 &&
17114 !tg3_flag(tp, PCI_EXPRESS))
17117 #if defined(CONFIG_PPC64) || defined(CONFIG_IA64) || defined(CONFIG_PARISC)
17118 goal = BOUNDARY_MULTI_CACHELINE;
17120 #if defined(CONFIG_SPARC64) || defined(CONFIG_ALPHA)
17121 goal = BOUNDARY_SINGLE_CACHELINE;
17127 if (tg3_flag(tp, 57765_PLUS)) {
17128 val = goal ? 0 : DMA_RWCTRL_DIS_CACHE_ALIGNMENT;
17135 /* PCI controllers on most RISC systems tend to disconnect
17136 * when a device tries to burst across a cache-line boundary.
17137 * Therefore, letting tg3 do so just wastes PCI bandwidth.
17139 * Unfortunately, for PCI-E there are only limited
17140 * write-side controls for this, and thus for reads
17141 * we will still get the disconnects. We'll also waste
17142 * these PCI cycles for both read and write for chips
17143 * other than 5700 and 5701 which do not implement the
17146 if (tg3_flag(tp, PCIX_MODE) && !tg3_flag(tp, PCI_EXPRESS)) {
17147 switch (cacheline_size) {
17152 if (goal == BOUNDARY_SINGLE_CACHELINE) {
17153 val |= (DMA_RWCTRL_READ_BNDRY_128_PCIX |
17154 DMA_RWCTRL_WRITE_BNDRY_128_PCIX);
17156 val |= (DMA_RWCTRL_READ_BNDRY_384_PCIX |
17157 DMA_RWCTRL_WRITE_BNDRY_384_PCIX);
17162 val |= (DMA_RWCTRL_READ_BNDRY_256_PCIX |
17163 DMA_RWCTRL_WRITE_BNDRY_256_PCIX);
17167 val |= (DMA_RWCTRL_READ_BNDRY_384_PCIX |
17168 DMA_RWCTRL_WRITE_BNDRY_384_PCIX);
17171 } else if (tg3_flag(tp, PCI_EXPRESS)) {
17172 switch (cacheline_size) {
17176 if (goal == BOUNDARY_SINGLE_CACHELINE) {
17177 val &= ~DMA_RWCTRL_WRITE_BNDRY_DISAB_PCIE;
17178 val |= DMA_RWCTRL_WRITE_BNDRY_64_PCIE;
17184 val &= ~DMA_RWCTRL_WRITE_BNDRY_DISAB_PCIE;
17185 val |= DMA_RWCTRL_WRITE_BNDRY_128_PCIE;
17189 switch (cacheline_size) {
17191 if (goal == BOUNDARY_SINGLE_CACHELINE) {
17192 val |= (DMA_RWCTRL_READ_BNDRY_16 |
17193 DMA_RWCTRL_WRITE_BNDRY_16);
17198 if (goal == BOUNDARY_SINGLE_CACHELINE) {
17199 val |= (DMA_RWCTRL_READ_BNDRY_32 |
17200 DMA_RWCTRL_WRITE_BNDRY_32);
17205 if (goal == BOUNDARY_SINGLE_CACHELINE) {
17206 val |= (DMA_RWCTRL_READ_BNDRY_64 |
17207 DMA_RWCTRL_WRITE_BNDRY_64);
17212 if (goal == BOUNDARY_SINGLE_CACHELINE) {
17213 val |= (DMA_RWCTRL_READ_BNDRY_128 |
17214 DMA_RWCTRL_WRITE_BNDRY_128);
17219 val |= (DMA_RWCTRL_READ_BNDRY_256 |
17220 DMA_RWCTRL_WRITE_BNDRY_256);
17223 val |= (DMA_RWCTRL_READ_BNDRY_512 |
17224 DMA_RWCTRL_WRITE_BNDRY_512);
17228 val |= (DMA_RWCTRL_READ_BNDRY_1024 |
17229 DMA_RWCTRL_WRITE_BNDRY_1024);
17238 static int tg3_do_test_dma(struct tg3 *tp, u32 *buf, dma_addr_t buf_dma,
17239 int size, bool to_device)
17241 struct tg3_internal_buffer_desc test_desc;
17242 u32 sram_dma_descs;
17245 sram_dma_descs = NIC_SRAM_DMA_DESC_POOL_BASE;
17247 tw32(FTQ_RCVBD_COMP_FIFO_ENQDEQ, 0);
17248 tw32(FTQ_RCVDATA_COMP_FIFO_ENQDEQ, 0);
17249 tw32(RDMAC_STATUS, 0);
17250 tw32(WDMAC_STATUS, 0);
17252 tw32(BUFMGR_MODE, 0);
17253 tw32(FTQ_RESET, 0);
17255 test_desc.addr_hi = ((u64) buf_dma) >> 32;
17256 test_desc.addr_lo = buf_dma & 0xffffffff;
17257 test_desc.nic_mbuf = 0x00002100;
17258 test_desc.len = size;
17261 * HP ZX1 was seeing test failures for 5701 cards running at 33Mhz
17262 * the *second* time the tg3 driver was getting loaded after an
17265 * Broadcom tells me:
17266 * ...the DMA engine is connected to the GRC block and a DMA
17267 * reset may affect the GRC block in some unpredictable way...
17268 * The behavior of resets to individual blocks has not been tested.
17270 * Broadcom noted the GRC reset will also reset all sub-components.
17273 test_desc.cqid_sqid = (13 << 8) | 2;
17275 tw32_f(RDMAC_MODE, RDMAC_MODE_ENABLE);
17278 test_desc.cqid_sqid = (16 << 8) | 7;
17280 tw32_f(WDMAC_MODE, WDMAC_MODE_ENABLE);
17283 test_desc.flags = 0x00000005;
17285 for (i = 0; i < (sizeof(test_desc) / sizeof(u32)); i++) {
17288 val = *(((u32 *)&test_desc) + i);
17289 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR,
17290 sram_dma_descs + (i * sizeof(u32)));
17291 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_DATA, val);
17293 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, 0);
17296 tw32(FTQ_DMA_HIGH_READ_FIFO_ENQDEQ, sram_dma_descs);
17298 tw32(FTQ_DMA_HIGH_WRITE_FIFO_ENQDEQ, sram_dma_descs);
17301 for (i = 0; i < 40; i++) {
17305 val = tr32(FTQ_RCVBD_COMP_FIFO_ENQDEQ);
17307 val = tr32(FTQ_RCVDATA_COMP_FIFO_ENQDEQ);
17308 if ((val & 0xffff) == sram_dma_descs) {
17319 #define TEST_BUFFER_SIZE 0x2000
17321 static const struct pci_device_id tg3_dma_wait_state_chipsets[] = {
17322 { PCI_DEVICE(PCI_VENDOR_ID_APPLE, PCI_DEVICE_ID_APPLE_UNI_N_PCI15) },
17326 static int tg3_test_dma(struct tg3 *tp)
17328 dma_addr_t buf_dma;
17329 u32 *buf, saved_dma_rwctrl;
17332 buf = dma_alloc_coherent(&tp->pdev->dev, TEST_BUFFER_SIZE,
17333 &buf_dma, GFP_KERNEL);
17339 tp->dma_rwctrl = ((0x7 << DMA_RWCTRL_PCI_WRITE_CMD_SHIFT) |
17340 (0x6 << DMA_RWCTRL_PCI_READ_CMD_SHIFT));
17342 tp->dma_rwctrl = tg3_calc_dma_bndry(tp, tp->dma_rwctrl);
17344 if (tg3_flag(tp, 57765_PLUS))
17347 if (tg3_flag(tp, PCI_EXPRESS)) {
17348 /* DMA read watermark not used on PCIE */
17349 tp->dma_rwctrl |= 0x00180000;
17350 } else if (!tg3_flag(tp, PCIX_MODE)) {
17351 if (tg3_asic_rev(tp) == ASIC_REV_5705 ||
17352 tg3_asic_rev(tp) == ASIC_REV_5750)
17353 tp->dma_rwctrl |= 0x003f0000;
17355 tp->dma_rwctrl |= 0x003f000f;
17357 if (tg3_asic_rev(tp) == ASIC_REV_5703 ||
17358 tg3_asic_rev(tp) == ASIC_REV_5704) {
17359 u32 ccval = (tr32(TG3PCI_CLOCK_CTRL) & 0x1f);
17360 u32 read_water = 0x7;
17362 /* If the 5704 is behind the EPB bridge, we can
17363 * do the less restrictive ONE_DMA workaround for
17364 * better performance.
17366 if (tg3_flag(tp, 40BIT_DMA_BUG) &&
17367 tg3_asic_rev(tp) == ASIC_REV_5704)
17368 tp->dma_rwctrl |= 0x8000;
17369 else if (ccval == 0x6 || ccval == 0x7)
17370 tp->dma_rwctrl |= DMA_RWCTRL_ONE_DMA;
17372 if (tg3_asic_rev(tp) == ASIC_REV_5703)
17374 /* Set bit 23 to enable PCIX hw bug fix */
17376 (read_water << DMA_RWCTRL_READ_WATER_SHIFT) |
17377 (0x3 << DMA_RWCTRL_WRITE_WATER_SHIFT) |
17379 } else if (tg3_asic_rev(tp) == ASIC_REV_5780) {
17380 /* 5780 always in PCIX mode */
17381 tp->dma_rwctrl |= 0x00144000;
17382 } else if (tg3_asic_rev(tp) == ASIC_REV_5714) {
17383 /* 5714 always in PCIX mode */
17384 tp->dma_rwctrl |= 0x00148000;
17386 tp->dma_rwctrl |= 0x001b000f;
17389 if (tg3_flag(tp, ONE_DMA_AT_ONCE))
17390 tp->dma_rwctrl |= DMA_RWCTRL_ONE_DMA;
17392 if (tg3_asic_rev(tp) == ASIC_REV_5703 ||
17393 tg3_asic_rev(tp) == ASIC_REV_5704)
17394 tp->dma_rwctrl &= 0xfffffff0;
17396 if (tg3_asic_rev(tp) == ASIC_REV_5700 ||
17397 tg3_asic_rev(tp) == ASIC_REV_5701) {
17398 /* Remove this if it causes problems for some boards. */
17399 tp->dma_rwctrl |= DMA_RWCTRL_USE_MEM_READ_MULT;
17401 /* On 5700/5701 chips, we need to set this bit.
17402 * Otherwise the chip will issue cacheline transactions
17403 * to streamable DMA memory with not all the byte
17404 * enables turned on. This is an error on several
17405 * RISC PCI controllers, in particular sparc64.
17407 * On 5703/5704 chips, this bit has been reassigned
17408 * a different meaning. In particular, it is used
17409 * on those chips to enable a PCI-X workaround.
17411 tp->dma_rwctrl |= DMA_RWCTRL_ASSERT_ALL_BE;
17414 tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
17417 if (tg3_asic_rev(tp) != ASIC_REV_5700 &&
17418 tg3_asic_rev(tp) != ASIC_REV_5701)
17421 /* It is best to perform DMA test with maximum write burst size
17422 * to expose the 5700/5701 write DMA bug.
17424 saved_dma_rwctrl = tp->dma_rwctrl;
17425 tp->dma_rwctrl &= ~DMA_RWCTRL_WRITE_BNDRY_MASK;
17426 tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
17431 for (i = 0; i < TEST_BUFFER_SIZE / sizeof(u32); i++)
17434 /* Send the buffer to the chip. */
17435 ret = tg3_do_test_dma(tp, buf, buf_dma, TEST_BUFFER_SIZE, true);
17437 dev_err(&tp->pdev->dev,
17438 "%s: Buffer write failed. err = %d\n",
17443 /* Now read it back. */
17444 ret = tg3_do_test_dma(tp, buf, buf_dma, TEST_BUFFER_SIZE, false);
17446 dev_err(&tp->pdev->dev, "%s: Buffer read failed. "
17447 "err = %d\n", __func__, ret);
17452 for (i = 0; i < TEST_BUFFER_SIZE / sizeof(u32); i++) {
17456 if ((tp->dma_rwctrl & DMA_RWCTRL_WRITE_BNDRY_MASK) !=
17457 DMA_RWCTRL_WRITE_BNDRY_16) {
17458 tp->dma_rwctrl &= ~DMA_RWCTRL_WRITE_BNDRY_MASK;
17459 tp->dma_rwctrl |= DMA_RWCTRL_WRITE_BNDRY_16;
17460 tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
17463 dev_err(&tp->pdev->dev,
17464 "%s: Buffer corrupted on read back! "
17465 "(%d != %d)\n", __func__, p[i], i);
17471 if (i == (TEST_BUFFER_SIZE / sizeof(u32))) {
17477 if ((tp->dma_rwctrl & DMA_RWCTRL_WRITE_BNDRY_MASK) !=
17478 DMA_RWCTRL_WRITE_BNDRY_16) {
17479 /* DMA test passed without adjusting DMA boundary,
17480 * now look for chipsets that are known to expose the
17481 * DMA bug without failing the test.
17483 if (pci_dev_present(tg3_dma_wait_state_chipsets)) {
17484 tp->dma_rwctrl &= ~DMA_RWCTRL_WRITE_BNDRY_MASK;
17485 tp->dma_rwctrl |= DMA_RWCTRL_WRITE_BNDRY_16;
17487 /* Safe to use the calculated DMA boundary. */
17488 tp->dma_rwctrl = saved_dma_rwctrl;
17491 tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
17495 dma_free_coherent(&tp->pdev->dev, TEST_BUFFER_SIZE, buf, buf_dma);
17500 static void tg3_init_bufmgr_config(struct tg3 *tp)
17502 if (tg3_flag(tp, 57765_PLUS)) {
17503 tp->bufmgr_config.mbuf_read_dma_low_water =
17504 DEFAULT_MB_RDMA_LOW_WATER_5705;
17505 tp->bufmgr_config.mbuf_mac_rx_low_water =
17506 DEFAULT_MB_MACRX_LOW_WATER_57765;
17507 tp->bufmgr_config.mbuf_high_water =
17508 DEFAULT_MB_HIGH_WATER_57765;
17510 tp->bufmgr_config.mbuf_read_dma_low_water_jumbo =
17511 DEFAULT_MB_RDMA_LOW_WATER_5705;
17512 tp->bufmgr_config.mbuf_mac_rx_low_water_jumbo =
17513 DEFAULT_MB_MACRX_LOW_WATER_JUMBO_57765;
17514 tp->bufmgr_config.mbuf_high_water_jumbo =
17515 DEFAULT_MB_HIGH_WATER_JUMBO_57765;
17516 } else if (tg3_flag(tp, 5705_PLUS)) {
17517 tp->bufmgr_config.mbuf_read_dma_low_water =
17518 DEFAULT_MB_RDMA_LOW_WATER_5705;
17519 tp->bufmgr_config.mbuf_mac_rx_low_water =
17520 DEFAULT_MB_MACRX_LOW_WATER_5705;
17521 tp->bufmgr_config.mbuf_high_water =
17522 DEFAULT_MB_HIGH_WATER_5705;
17523 if (tg3_asic_rev(tp) == ASIC_REV_5906) {
17524 tp->bufmgr_config.mbuf_mac_rx_low_water =
17525 DEFAULT_MB_MACRX_LOW_WATER_5906;
17526 tp->bufmgr_config.mbuf_high_water =
17527 DEFAULT_MB_HIGH_WATER_5906;
17530 tp->bufmgr_config.mbuf_read_dma_low_water_jumbo =
17531 DEFAULT_MB_RDMA_LOW_WATER_JUMBO_5780;
17532 tp->bufmgr_config.mbuf_mac_rx_low_water_jumbo =
17533 DEFAULT_MB_MACRX_LOW_WATER_JUMBO_5780;
17534 tp->bufmgr_config.mbuf_high_water_jumbo =
17535 DEFAULT_MB_HIGH_WATER_JUMBO_5780;
17537 tp->bufmgr_config.mbuf_read_dma_low_water =
17538 DEFAULT_MB_RDMA_LOW_WATER;
17539 tp->bufmgr_config.mbuf_mac_rx_low_water =
17540 DEFAULT_MB_MACRX_LOW_WATER;
17541 tp->bufmgr_config.mbuf_high_water =
17542 DEFAULT_MB_HIGH_WATER;
17544 tp->bufmgr_config.mbuf_read_dma_low_water_jumbo =
17545 DEFAULT_MB_RDMA_LOW_WATER_JUMBO;
17546 tp->bufmgr_config.mbuf_mac_rx_low_water_jumbo =
17547 DEFAULT_MB_MACRX_LOW_WATER_JUMBO;
17548 tp->bufmgr_config.mbuf_high_water_jumbo =
17549 DEFAULT_MB_HIGH_WATER_JUMBO;
17552 tp->bufmgr_config.dma_low_water = DEFAULT_DMA_LOW_WATER;
17553 tp->bufmgr_config.dma_high_water = DEFAULT_DMA_HIGH_WATER;
17556 static char *tg3_phy_string(struct tg3 *tp)
17558 switch (tp->phy_id & TG3_PHY_ID_MASK) {
17559 case TG3_PHY_ID_BCM5400: return "5400";
17560 case TG3_PHY_ID_BCM5401: return "5401";
17561 case TG3_PHY_ID_BCM5411: return "5411";
17562 case TG3_PHY_ID_BCM5701: return "5701";
17563 case TG3_PHY_ID_BCM5703: return "5703";
17564 case TG3_PHY_ID_BCM5704: return "5704";
17565 case TG3_PHY_ID_BCM5705: return "5705";
17566 case TG3_PHY_ID_BCM5750: return "5750";
17567 case TG3_PHY_ID_BCM5752: return "5752";
17568 case TG3_PHY_ID_BCM5714: return "5714";
17569 case TG3_PHY_ID_BCM5780: return "5780";
17570 case TG3_PHY_ID_BCM5755: return "5755";
17571 case TG3_PHY_ID_BCM5787: return "5787";
17572 case TG3_PHY_ID_BCM5784: return "5784";
17573 case TG3_PHY_ID_BCM5756: return "5722/5756";
17574 case TG3_PHY_ID_BCM5906: return "5906";
17575 case TG3_PHY_ID_BCM5761: return "5761";
17576 case TG3_PHY_ID_BCM5718C: return "5718C";
17577 case TG3_PHY_ID_BCM5718S: return "5718S";
17578 case TG3_PHY_ID_BCM57765: return "57765";
17579 case TG3_PHY_ID_BCM5719C: return "5719C";
17580 case TG3_PHY_ID_BCM5720C: return "5720C";
17581 case TG3_PHY_ID_BCM5762: return "5762C";
17582 case TG3_PHY_ID_BCM8002: return "8002/serdes";
17583 case 0: return "serdes";
17584 default: return "unknown";
17588 static char *tg3_bus_string(struct tg3 *tp, char *str)
17590 if (tg3_flag(tp, PCI_EXPRESS)) {
17591 strcpy(str, "PCI Express");
17593 } else if (tg3_flag(tp, PCIX_MODE)) {
17594 u32 clock_ctrl = tr32(TG3PCI_CLOCK_CTRL) & 0x1f;
17596 strcpy(str, "PCIX:");
17598 if ((clock_ctrl == 7) ||
17599 ((tr32(GRC_MISC_CFG) & GRC_MISC_CFG_BOARD_ID_MASK) ==
17600 GRC_MISC_CFG_BOARD_ID_5704CIOBE))
17601 strcat(str, "133MHz");
17602 else if (clock_ctrl == 0)
17603 strcat(str, "33MHz");
17604 else if (clock_ctrl == 2)
17605 strcat(str, "50MHz");
17606 else if (clock_ctrl == 4)
17607 strcat(str, "66MHz");
17608 else if (clock_ctrl == 6)
17609 strcat(str, "100MHz");
17611 strcpy(str, "PCI:");
17612 if (tg3_flag(tp, PCI_HIGH_SPEED))
17613 strcat(str, "66MHz");
17615 strcat(str, "33MHz");
17617 if (tg3_flag(tp, PCI_32BIT))
17618 strcat(str, ":32-bit");
17620 strcat(str, ":64-bit");
17624 static void tg3_init_coal(struct tg3 *tp)
17626 struct ethtool_coalesce *ec = &tp->coal;
17628 memset(ec, 0, sizeof(*ec));
17629 ec->cmd = ETHTOOL_GCOALESCE;
17630 ec->rx_coalesce_usecs = LOW_RXCOL_TICKS;
17631 ec->tx_coalesce_usecs = LOW_TXCOL_TICKS;
17632 ec->rx_max_coalesced_frames = LOW_RXMAX_FRAMES;
17633 ec->tx_max_coalesced_frames = LOW_TXMAX_FRAMES;
17634 ec->rx_coalesce_usecs_irq = DEFAULT_RXCOAL_TICK_INT;
17635 ec->tx_coalesce_usecs_irq = DEFAULT_TXCOAL_TICK_INT;
17636 ec->rx_max_coalesced_frames_irq = DEFAULT_RXCOAL_MAXF_INT;
17637 ec->tx_max_coalesced_frames_irq = DEFAULT_TXCOAL_MAXF_INT;
17638 ec->stats_block_coalesce_usecs = DEFAULT_STAT_COAL_TICKS;
17640 if (tp->coalesce_mode & (HOSTCC_MODE_CLRTICK_RXBD |
17641 HOSTCC_MODE_CLRTICK_TXBD)) {
17642 ec->rx_coalesce_usecs = LOW_RXCOL_TICKS_CLRTCKS;
17643 ec->rx_coalesce_usecs_irq = DEFAULT_RXCOAL_TICK_INT_CLRTCKS;
17644 ec->tx_coalesce_usecs = LOW_TXCOL_TICKS_CLRTCKS;
17645 ec->tx_coalesce_usecs_irq = DEFAULT_TXCOAL_TICK_INT_CLRTCKS;
17648 if (tg3_flag(tp, 5705_PLUS)) {
17649 ec->rx_coalesce_usecs_irq = 0;
17650 ec->tx_coalesce_usecs_irq = 0;
17651 ec->stats_block_coalesce_usecs = 0;
17655 static int tg3_init_one(struct pci_dev *pdev,
17656 const struct pci_device_id *ent)
17658 struct net_device *dev;
17661 u32 sndmbx, rcvmbx, intmbx;
17663 u64 dma_mask, persist_dma_mask;
17664 netdev_features_t features = 0;
17666 printk_once(KERN_INFO "%s\n", version);
17668 err = pci_enable_device(pdev);
17670 dev_err(&pdev->dev, "Cannot enable PCI device, aborting\n");
17674 err = pci_request_regions(pdev, DRV_MODULE_NAME);
17676 dev_err(&pdev->dev, "Cannot obtain PCI resources, aborting\n");
17677 goto err_out_disable_pdev;
17680 pci_set_master(pdev);
17682 dev = alloc_etherdev_mq(sizeof(*tp), TG3_IRQ_MAX_VECS);
17685 goto err_out_free_res;
17688 SET_NETDEV_DEV(dev, &pdev->dev);
17690 tp = netdev_priv(dev);
17693 tp->rx_mode = TG3_DEF_RX_MODE;
17694 tp->tx_mode = TG3_DEF_TX_MODE;
17696 tp->pcierr_recovery = false;
17699 tp->msg_enable = tg3_debug;
17701 tp->msg_enable = TG3_DEF_MSG_ENABLE;
17703 if (pdev_is_ssb_gige_core(pdev)) {
17704 tg3_flag_set(tp, IS_SSB_CORE);
17705 if (ssb_gige_must_flush_posted_writes(pdev))
17706 tg3_flag_set(tp, FLUSH_POSTED_WRITES);
17707 if (ssb_gige_one_dma_at_once(pdev))
17708 tg3_flag_set(tp, ONE_DMA_AT_ONCE);
17709 if (ssb_gige_have_roboswitch(pdev)) {
17710 tg3_flag_set(tp, USE_PHYLIB);
17711 tg3_flag_set(tp, ROBOSWITCH);
17713 if (ssb_gige_is_rgmii(pdev))
17714 tg3_flag_set(tp, RGMII_MODE);
17717 /* The word/byte swap controls here control register access byte
17718 * swapping. DMA data byte swapping is controlled in the GRC_MODE
17721 tp->misc_host_ctrl =
17722 MISC_HOST_CTRL_MASK_PCI_INT |
17723 MISC_HOST_CTRL_WORD_SWAP |
17724 MISC_HOST_CTRL_INDIR_ACCESS |
17725 MISC_HOST_CTRL_PCISTATE_RW;
17727 /* The NONFRM (non-frame) byte/word swap controls take effect
17728 * on descriptor entries, anything which isn't packet data.
17730 * The StrongARM chips on the board (one for tx, one for rx)
17731 * are running in big-endian mode.
17733 tp->grc_mode = (GRC_MODE_WSWAP_DATA | GRC_MODE_BSWAP_DATA |
17734 GRC_MODE_WSWAP_NONFRM_DATA);
17735 #ifdef __BIG_ENDIAN
17736 tp->grc_mode |= GRC_MODE_BSWAP_NONFRM_DATA;
17738 spin_lock_init(&tp->lock);
17739 spin_lock_init(&tp->indirect_lock);
17740 INIT_WORK(&tp->reset_task, tg3_reset_task);
17742 tp->regs = pci_ioremap_bar(pdev, BAR_0);
17744 dev_err(&pdev->dev, "Cannot map device registers, aborting\n");
17746 goto err_out_free_dev;
17749 if (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5761 ||
17750 tp->pdev->device == PCI_DEVICE_ID_TIGON3_5761E ||
17751 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5761S ||
17752 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5761SE ||
17753 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5717 ||
17754 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5717_C ||
17755 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5718 ||
17756 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5719 ||
17757 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5720 ||
17758 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57767 ||
17759 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57764 ||
17760 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5762 ||
17761 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5725 ||
17762 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5727 ||
17763 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57787) {
17764 tg3_flag_set(tp, ENABLE_APE);
17765 tp->aperegs = pci_ioremap_bar(pdev, BAR_2);
17766 if (!tp->aperegs) {
17767 dev_err(&pdev->dev,
17768 "Cannot map APE registers, aborting\n");
17770 goto err_out_iounmap;
17774 tp->rx_pending = TG3_DEF_RX_RING_PENDING;
17775 tp->rx_jumbo_pending = TG3_DEF_RX_JUMBO_RING_PENDING;
17777 dev->ethtool_ops = &tg3_ethtool_ops;
17778 dev->watchdog_timeo = TG3_TX_TIMEOUT;
17779 dev->netdev_ops = &tg3_netdev_ops;
17780 dev->irq = pdev->irq;
17782 err = tg3_get_invariants(tp, ent);
17784 dev_err(&pdev->dev,
17785 "Problem fetching invariants of chip, aborting\n");
17786 goto err_out_apeunmap;
17789 /* The EPB bridge inside 5714, 5715, and 5780 and any
17790 * device behind the EPB cannot support DMA addresses > 40-bit.
17791 * On 64-bit systems with IOMMU, use 40-bit dma_mask.
17792 * On 64-bit systems without IOMMU, use 64-bit dma_mask and
17793 * do DMA address check in tg3_start_xmit().
17795 if (tg3_flag(tp, IS_5788))
17796 persist_dma_mask = dma_mask = DMA_BIT_MASK(32);
17797 else if (tg3_flag(tp, 40BIT_DMA_BUG)) {
17798 persist_dma_mask = dma_mask = DMA_BIT_MASK(40);
17799 #ifdef CONFIG_HIGHMEM
17800 dma_mask = DMA_BIT_MASK(64);
17803 persist_dma_mask = dma_mask = DMA_BIT_MASK(64);
17805 /* Configure DMA attributes. */
17806 if (dma_mask > DMA_BIT_MASK(32)) {
17807 err = pci_set_dma_mask(pdev, dma_mask);
17809 features |= NETIF_F_HIGHDMA;
17810 err = pci_set_consistent_dma_mask(pdev,
17813 dev_err(&pdev->dev, "Unable to obtain 64 bit "
17814 "DMA for consistent allocations\n");
17815 goto err_out_apeunmap;
17819 if (err || dma_mask == DMA_BIT_MASK(32)) {
17820 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
17822 dev_err(&pdev->dev,
17823 "No usable DMA configuration, aborting\n");
17824 goto err_out_apeunmap;
17828 tg3_init_bufmgr_config(tp);
17830 /* 5700 B0 chips do not support checksumming correctly due
17831 * to hardware bugs.
17833 if (tg3_chip_rev_id(tp) != CHIPREV_ID_5700_B0) {
17834 features |= NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_RXCSUM;
17836 if (tg3_flag(tp, 5755_PLUS))
17837 features |= NETIF_F_IPV6_CSUM;
17840 /* TSO is on by default on chips that support hardware TSO.
17841 * Firmware TSO on older chips gives lower performance, so it
17842 * is off by default, but can be enabled using ethtool.
17844 if ((tg3_flag(tp, HW_TSO_1) ||
17845 tg3_flag(tp, HW_TSO_2) ||
17846 tg3_flag(tp, HW_TSO_3)) &&
17847 (features & NETIF_F_IP_CSUM))
17848 features |= NETIF_F_TSO;
17849 if (tg3_flag(tp, HW_TSO_2) || tg3_flag(tp, HW_TSO_3)) {
17850 if (features & NETIF_F_IPV6_CSUM)
17851 features |= NETIF_F_TSO6;
17852 if (tg3_flag(tp, HW_TSO_3) ||
17853 tg3_asic_rev(tp) == ASIC_REV_5761 ||
17854 (tg3_asic_rev(tp) == ASIC_REV_5784 &&
17855 tg3_chip_rev(tp) != CHIPREV_5784_AX) ||
17856 tg3_asic_rev(tp) == ASIC_REV_5785 ||
17857 tg3_asic_rev(tp) == ASIC_REV_57780)
17858 features |= NETIF_F_TSO_ECN;
17861 dev->features |= features | NETIF_F_HW_VLAN_CTAG_TX |
17862 NETIF_F_HW_VLAN_CTAG_RX;
17863 dev->vlan_features |= features;
17866 * Add loopback capability only for a subset of devices that support
17867 * MAC-LOOPBACK. Eventually this need to be enhanced to allow INT-PHY
17868 * loopback for the remaining devices.
17870 if (tg3_asic_rev(tp) != ASIC_REV_5780 &&
17871 !tg3_flag(tp, CPMU_PRESENT))
17872 /* Add the loopback capability */
17873 features |= NETIF_F_LOOPBACK;
17875 dev->hw_features |= features;
17876 dev->priv_flags |= IFF_UNICAST_FLT;
17878 /* MTU range: 60 - 9000 or 1500, depending on hardware */
17879 dev->min_mtu = TG3_MIN_MTU;
17880 dev->max_mtu = TG3_MAX_MTU(tp);
17882 if (tg3_chip_rev_id(tp) == CHIPREV_ID_5705_A1 &&
17883 !tg3_flag(tp, TSO_CAPABLE) &&
17884 !(tr32(TG3PCI_PCISTATE) & PCISTATE_BUS_SPEED_HIGH)) {
17885 tg3_flag_set(tp, MAX_RXPEND_64);
17886 tp->rx_pending = 63;
17889 err = tg3_get_device_address(tp);
17891 dev_err(&pdev->dev,
17892 "Could not obtain valid ethernet address, aborting\n");
17893 goto err_out_apeunmap;
17896 intmbx = MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW;
17897 rcvmbx = MAILBOX_RCVRET_CON_IDX_0 + TG3_64BIT_REG_LOW;
17898 sndmbx = MAILBOX_SNDHOST_PROD_IDX_0 + TG3_64BIT_REG_LOW;
17899 for (i = 0; i < tp->irq_max; i++) {
17900 struct tg3_napi *tnapi = &tp->napi[i];
17903 tnapi->tx_pending = TG3_DEF_TX_RING_PENDING;
17905 tnapi->int_mbox = intmbx;
17911 tnapi->consmbox = rcvmbx;
17912 tnapi->prodmbox = sndmbx;
17915 tnapi->coal_now = HOSTCC_MODE_COAL_VEC1_NOW << (i - 1);
17917 tnapi->coal_now = HOSTCC_MODE_NOW;
17919 if (!tg3_flag(tp, SUPPORT_MSIX))
17923 * If we support MSIX, we'll be using RSS. If we're using
17924 * RSS, the first vector only handles link interrupts and the
17925 * remaining vectors handle rx and tx interrupts. Reuse the
17926 * mailbox values for the next iteration. The values we setup
17927 * above are still useful for the single vectored mode.
17941 * Reset chip in case UNDI or EFI driver did not shutdown
17942 * DMA self test will enable WDMAC and we'll see (spurious)
17943 * pending DMA on the PCI bus at that point.
17945 if ((tr32(HOSTCC_MODE) & HOSTCC_MODE_ENABLE) ||
17946 (tr32(WDMAC_MODE) & WDMAC_MODE_ENABLE)) {
17947 tg3_full_lock(tp, 0);
17948 tw32(MEMARB_MODE, MEMARB_MODE_ENABLE);
17949 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
17950 tg3_full_unlock(tp);
17953 err = tg3_test_dma(tp);
17955 dev_err(&pdev->dev, "DMA engine test failed, aborting\n");
17956 goto err_out_apeunmap;
17961 pci_set_drvdata(pdev, dev);
17963 if (tg3_asic_rev(tp) == ASIC_REV_5719 ||
17964 tg3_asic_rev(tp) == ASIC_REV_5720 ||
17965 tg3_asic_rev(tp) == ASIC_REV_5762)
17966 tg3_flag_set(tp, PTP_CAPABLE);
17968 tg3_timer_init(tp);
17970 tg3_carrier_off(tp);
17972 err = register_netdev(dev);
17974 dev_err(&pdev->dev, "Cannot register net device, aborting\n");
17975 goto err_out_apeunmap;
17978 if (tg3_flag(tp, PTP_CAPABLE)) {
17980 tp->ptp_clock = ptp_clock_register(&tp->ptp_info,
17982 if (IS_ERR(tp->ptp_clock))
17983 tp->ptp_clock = NULL;
17986 netdev_info(dev, "Tigon3 [partno(%s) rev %04x] (%s) MAC address %pM\n",
17987 tp->board_part_number,
17988 tg3_chip_rev_id(tp),
17989 tg3_bus_string(tp, str),
17992 if (!(tp->phy_flags & TG3_PHYFLG_IS_CONNECTED)) {
17995 if (tp->phy_flags & TG3_PHYFLG_10_100_ONLY)
17996 ethtype = "10/100Base-TX";
17997 else if (tp->phy_flags & TG3_PHYFLG_ANY_SERDES)
17998 ethtype = "1000Base-SX";
18000 ethtype = "10/100/1000Base-T";
18002 netdev_info(dev, "attached PHY is %s (%s Ethernet) "
18003 "(WireSpeed[%d], EEE[%d])\n",
18004 tg3_phy_string(tp), ethtype,
18005 (tp->phy_flags & TG3_PHYFLG_NO_ETH_WIRE_SPEED) == 0,
18006 (tp->phy_flags & TG3_PHYFLG_EEE_CAP) != 0);
18009 netdev_info(dev, "RXcsums[%d] LinkChgREG[%d] MIirq[%d] ASF[%d] TSOcap[%d]\n",
18010 (dev->features & NETIF_F_RXCSUM) != 0,
18011 tg3_flag(tp, USE_LINKCHG_REG) != 0,
18012 (tp->phy_flags & TG3_PHYFLG_USE_MI_INTERRUPT) != 0,
18013 tg3_flag(tp, ENABLE_ASF) != 0,
18014 tg3_flag(tp, TSO_CAPABLE) != 0);
18015 netdev_info(dev, "dma_rwctrl[%08x] dma_mask[%d-bit]\n",
18017 pdev->dma_mask == DMA_BIT_MASK(32) ? 32 :
18018 ((u64)pdev->dma_mask) == DMA_BIT_MASK(40) ? 40 : 64);
18020 pci_save_state(pdev);
18026 iounmap(tp->aperegs);
18027 tp->aperegs = NULL;
18040 pci_release_regions(pdev);
18042 err_out_disable_pdev:
18043 if (pci_is_enabled(pdev))
18044 pci_disable_device(pdev);
18048 static void tg3_remove_one(struct pci_dev *pdev)
18050 struct net_device *dev = pci_get_drvdata(pdev);
18053 struct tg3 *tp = netdev_priv(dev);
18057 release_firmware(tp->fw);
18059 tg3_reset_task_cancel(tp);
18061 if (tg3_flag(tp, USE_PHYLIB)) {
18066 unregister_netdev(dev);
18068 iounmap(tp->aperegs);
18069 tp->aperegs = NULL;
18076 pci_release_regions(pdev);
18077 pci_disable_device(pdev);
18081 #ifdef CONFIG_PM_SLEEP
18082 static int tg3_suspend(struct device *device)
18084 struct pci_dev *pdev = to_pci_dev(device);
18085 struct net_device *dev = pci_get_drvdata(pdev);
18086 struct tg3 *tp = netdev_priv(dev);
18091 if (!netif_running(dev))
18094 tg3_reset_task_cancel(tp);
18096 tg3_netif_stop(tp);
18098 tg3_timer_stop(tp);
18100 tg3_full_lock(tp, 1);
18101 tg3_disable_ints(tp);
18102 tg3_full_unlock(tp);
18104 netif_device_detach(dev);
18106 tg3_full_lock(tp, 0);
18107 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
18108 tg3_flag_clear(tp, INIT_COMPLETE);
18109 tg3_full_unlock(tp);
18111 err = tg3_power_down_prepare(tp);
18115 tg3_full_lock(tp, 0);
18117 tg3_flag_set(tp, INIT_COMPLETE);
18118 err2 = tg3_restart_hw(tp, true);
18122 tg3_timer_start(tp);
18124 netif_device_attach(dev);
18125 tg3_netif_start(tp);
18128 tg3_full_unlock(tp);
18139 static int tg3_resume(struct device *device)
18141 struct pci_dev *pdev = to_pci_dev(device);
18142 struct net_device *dev = pci_get_drvdata(pdev);
18143 struct tg3 *tp = netdev_priv(dev);
18148 if (!netif_running(dev))
18151 netif_device_attach(dev);
18153 tg3_full_lock(tp, 0);
18155 tg3_ape_driver_state_change(tp, RESET_KIND_INIT);
18157 tg3_flag_set(tp, INIT_COMPLETE);
18158 err = tg3_restart_hw(tp,
18159 !(tp->phy_flags & TG3_PHYFLG_KEEP_LINK_ON_PWRDN));
18163 tg3_timer_start(tp);
18165 tg3_netif_start(tp);
18168 tg3_full_unlock(tp);
18177 #endif /* CONFIG_PM_SLEEP */
18179 static SIMPLE_DEV_PM_OPS(tg3_pm_ops, tg3_suspend, tg3_resume);
18181 static void tg3_shutdown(struct pci_dev *pdev)
18183 struct net_device *dev = pci_get_drvdata(pdev);
18184 struct tg3 *tp = netdev_priv(dev);
18187 netif_device_detach(dev);
18189 if (netif_running(dev))
18192 if (system_state == SYSTEM_POWER_OFF)
18193 tg3_power_down(tp);
18199 * tg3_io_error_detected - called when PCI error is detected
18200 * @pdev: Pointer to PCI device
18201 * @state: The current pci connection state
18203 * This function is called after a PCI bus error affecting
18204 * this device has been detected.
18206 static pci_ers_result_t tg3_io_error_detected(struct pci_dev *pdev,
18207 pci_channel_state_t state)
18209 struct net_device *netdev = pci_get_drvdata(pdev);
18210 struct tg3 *tp = netdev_priv(netdev);
18211 pci_ers_result_t err = PCI_ERS_RESULT_NEED_RESET;
18213 netdev_info(netdev, "PCI I/O error detected\n");
18217 /* We probably don't have netdev yet */
18218 if (!netdev || !netif_running(netdev))
18221 /* We needn't recover from permanent error */
18222 if (state == pci_channel_io_frozen)
18223 tp->pcierr_recovery = true;
18227 tg3_netif_stop(tp);
18229 tg3_timer_stop(tp);
18231 /* Want to make sure that the reset task doesn't run */
18232 tg3_reset_task_cancel(tp);
18234 netif_device_detach(netdev);
18236 /* Clean up software state, even if MMIO is blocked */
18237 tg3_full_lock(tp, 0);
18238 tg3_halt(tp, RESET_KIND_SHUTDOWN, 0);
18239 tg3_full_unlock(tp);
18242 if (state == pci_channel_io_perm_failure) {
18244 tg3_napi_enable(tp);
18247 err = PCI_ERS_RESULT_DISCONNECT;
18249 pci_disable_device(pdev);
18258 * tg3_io_slot_reset - called after the pci bus has been reset.
18259 * @pdev: Pointer to PCI device
18261 * Restart the card from scratch, as if from a cold-boot.
18262 * At this point, the card has exprienced a hard reset,
18263 * followed by fixups by BIOS, and has its config space
18264 * set up identically to what it was at cold boot.
18266 static pci_ers_result_t tg3_io_slot_reset(struct pci_dev *pdev)
18268 struct net_device *netdev = pci_get_drvdata(pdev);
18269 struct tg3 *tp = netdev_priv(netdev);
18270 pci_ers_result_t rc = PCI_ERS_RESULT_DISCONNECT;
18275 if (pci_enable_device(pdev)) {
18276 dev_err(&pdev->dev,
18277 "Cannot re-enable PCI device after reset.\n");
18281 pci_set_master(pdev);
18282 pci_restore_state(pdev);
18283 pci_save_state(pdev);
18285 if (!netdev || !netif_running(netdev)) {
18286 rc = PCI_ERS_RESULT_RECOVERED;
18290 err = tg3_power_up(tp);
18294 rc = PCI_ERS_RESULT_RECOVERED;
18297 if (rc != PCI_ERS_RESULT_RECOVERED && netdev && netif_running(netdev)) {
18298 tg3_napi_enable(tp);
18307 * tg3_io_resume - called when traffic can start flowing again.
18308 * @pdev: Pointer to PCI device
18310 * This callback is called when the error recovery driver tells
18311 * us that its OK to resume normal operation.
18313 static void tg3_io_resume(struct pci_dev *pdev)
18315 struct net_device *netdev = pci_get_drvdata(pdev);
18316 struct tg3 *tp = netdev_priv(netdev);
18321 if (!netdev || !netif_running(netdev))
18324 tg3_full_lock(tp, 0);
18325 tg3_ape_driver_state_change(tp, RESET_KIND_INIT);
18326 tg3_flag_set(tp, INIT_COMPLETE);
18327 err = tg3_restart_hw(tp, true);
18329 tg3_full_unlock(tp);
18330 netdev_err(netdev, "Cannot restart hardware after reset.\n");
18334 netif_device_attach(netdev);
18336 tg3_timer_start(tp);
18338 tg3_netif_start(tp);
18340 tg3_full_unlock(tp);
18345 tp->pcierr_recovery = false;
18349 static const struct pci_error_handlers tg3_err_handler = {
18350 .error_detected = tg3_io_error_detected,
18351 .slot_reset = tg3_io_slot_reset,
18352 .resume = tg3_io_resume
18355 static struct pci_driver tg3_driver = {
18356 .name = DRV_MODULE_NAME,
18357 .id_table = tg3_pci_tbl,
18358 .probe = tg3_init_one,
18359 .remove = tg3_remove_one,
18360 .err_handler = &tg3_err_handler,
18361 .driver.pm = &tg3_pm_ops,
18362 .shutdown = tg3_shutdown,
18365 module_pci_driver(tg3_driver);