2 * tg3.c: Broadcom Tigon3 ethernet driver.
4 * Copyright (C) 2001, 2002, 2003, 2004 David S. Miller (davem@redhat.com)
5 * Copyright (C) 2001, 2002, 2003 Jeff Garzik (jgarzik@pobox.com)
6 * Copyright (C) 2004 Sun Microsystems Inc.
7 * Copyright (C) 2005-2013 Broadcom Corporation.
10 * Derived from proprietary unpublished source code,
11 * Copyright (C) 2000-2003 Broadcom Corporation.
13 * Permission is hereby granted for the distribution of this firmware
14 * data in hexadecimal or equivalent format, provided this copyright
15 * notice is accompanying it.
19 #include <linux/module.h>
20 #include <linux/moduleparam.h>
21 #include <linux/stringify.h>
22 #include <linux/kernel.h>
23 #include <linux/types.h>
24 #include <linux/compiler.h>
25 #include <linux/slab.h>
26 #include <linux/delay.h>
28 #include <linux/interrupt.h>
29 #include <linux/ioport.h>
30 #include <linux/pci.h>
31 #include <linux/netdevice.h>
32 #include <linux/etherdevice.h>
33 #include <linux/skbuff.h>
34 #include <linux/ethtool.h>
35 #include <linux/mdio.h>
36 #include <linux/mii.h>
37 #include <linux/phy.h>
38 #include <linux/brcmphy.h>
40 #include <linux/if_vlan.h>
42 #include <linux/tcp.h>
43 #include <linux/workqueue.h>
44 #include <linux/prefetch.h>
45 #include <linux/dma-mapping.h>
46 #include <linux/firmware.h>
47 #include <linux/ssb/ssb_driver_gige.h>
48 #include <linux/hwmon.h>
49 #include <linux/hwmon-sysfs.h>
51 #include <net/checksum.h>
55 #include <asm/byteorder.h>
56 #include <linux/uaccess.h>
58 #include <uapi/linux/net_tstamp.h>
59 #include <linux/ptp_clock_kernel.h>
62 #include <asm/idprom.h>
71 /* Functions & macros to verify TG3_FLAGS types */
73 static inline int _tg3_flag(enum TG3_FLAGS flag, unsigned long *bits)
75 return test_bit(flag, bits);
78 static inline void _tg3_flag_set(enum TG3_FLAGS flag, unsigned long *bits)
83 static inline void _tg3_flag_clear(enum TG3_FLAGS flag, unsigned long *bits)
85 clear_bit(flag, bits);
88 #define tg3_flag(tp, flag) \
89 _tg3_flag(TG3_FLAG_##flag, (tp)->tg3_flags)
90 #define tg3_flag_set(tp, flag) \
91 _tg3_flag_set(TG3_FLAG_##flag, (tp)->tg3_flags)
92 #define tg3_flag_clear(tp, flag) \
93 _tg3_flag_clear(TG3_FLAG_##flag, (tp)->tg3_flags)
95 #define DRV_MODULE_NAME "tg3"
97 #define TG3_MIN_NUM 136
98 #define DRV_MODULE_VERSION \
99 __stringify(TG3_MAJ_NUM) "." __stringify(TG3_MIN_NUM)
100 #define DRV_MODULE_RELDATE "Jan 03, 2014"
102 #define RESET_KIND_SHUTDOWN 0
103 #define RESET_KIND_INIT 1
104 #define RESET_KIND_SUSPEND 2
106 #define TG3_DEF_RX_MODE 0
107 #define TG3_DEF_TX_MODE 0
108 #define TG3_DEF_MSG_ENABLE \
118 #define TG3_GRC_LCLCTL_PWRSW_DELAY 100
120 /* length of time before we decide the hardware is borked,
121 * and dev->tx_timeout() should be called to fix the problem
124 #define TG3_TX_TIMEOUT (5 * HZ)
126 /* hardware minimum and maximum for a single frame's data payload */
127 #define TG3_MIN_MTU 60
128 #define TG3_MAX_MTU(tp) \
129 (tg3_flag(tp, JUMBO_CAPABLE) ? 9000 : 1500)
131 /* These numbers seem to be hard coded in the NIC firmware somehow.
132 * You can't change the ring sizes, but you can change where you place
133 * them in the NIC onboard memory.
135 #define TG3_RX_STD_RING_SIZE(tp) \
136 (tg3_flag(tp, LRG_PROD_RING_CAP) ? \
137 TG3_RX_STD_MAX_SIZE_5717 : TG3_RX_STD_MAX_SIZE_5700)
138 #define TG3_DEF_RX_RING_PENDING 200
139 #define TG3_RX_JMB_RING_SIZE(tp) \
140 (tg3_flag(tp, LRG_PROD_RING_CAP) ? \
141 TG3_RX_JMB_MAX_SIZE_5717 : TG3_RX_JMB_MAX_SIZE_5700)
142 #define TG3_DEF_RX_JUMBO_RING_PENDING 100
144 /* Do not place this n-ring entries value into the tp struct itself,
145 * we really want to expose these constants to GCC so that modulo et
146 * al. operations are done with shifts and masks instead of with
147 * hw multiply/modulo instructions. Another solution would be to
148 * replace things like '% foo' with '& (foo - 1)'.
151 #define TG3_TX_RING_SIZE 512
152 #define TG3_DEF_TX_RING_PENDING (TG3_TX_RING_SIZE - 1)
154 #define TG3_RX_STD_RING_BYTES(tp) \
155 (sizeof(struct tg3_rx_buffer_desc) * TG3_RX_STD_RING_SIZE(tp))
156 #define TG3_RX_JMB_RING_BYTES(tp) \
157 (sizeof(struct tg3_ext_rx_buffer_desc) * TG3_RX_JMB_RING_SIZE(tp))
158 #define TG3_RX_RCB_RING_BYTES(tp) \
159 (sizeof(struct tg3_rx_buffer_desc) * (tp->rx_ret_ring_mask + 1))
160 #define TG3_TX_RING_BYTES (sizeof(struct tg3_tx_buffer_desc) * \
162 #define NEXT_TX(N) (((N) + 1) & (TG3_TX_RING_SIZE - 1))
164 #define TG3_DMA_BYTE_ENAB 64
166 #define TG3_RX_STD_DMA_SZ 1536
167 #define TG3_RX_JMB_DMA_SZ 9046
169 #define TG3_RX_DMA_TO_MAP_SZ(x) ((x) + TG3_DMA_BYTE_ENAB)
171 #define TG3_RX_STD_MAP_SZ TG3_RX_DMA_TO_MAP_SZ(TG3_RX_STD_DMA_SZ)
172 #define TG3_RX_JMB_MAP_SZ TG3_RX_DMA_TO_MAP_SZ(TG3_RX_JMB_DMA_SZ)
174 #define TG3_RX_STD_BUFF_RING_SIZE(tp) \
175 (sizeof(struct ring_info) * TG3_RX_STD_RING_SIZE(tp))
177 #define TG3_RX_JMB_BUFF_RING_SIZE(tp) \
178 (sizeof(struct ring_info) * TG3_RX_JMB_RING_SIZE(tp))
180 /* Due to a hardware bug, the 5701 can only DMA to memory addresses
181 * that are at least dword aligned when used in PCIX mode. The driver
182 * works around this bug by double copying the packet. This workaround
183 * is built into the normal double copy length check for efficiency.
185 * However, the double copy is only necessary on those architectures
186 * where unaligned memory accesses are inefficient. For those architectures
187 * where unaligned memory accesses incur little penalty, we can reintegrate
188 * the 5701 in the normal rx path. Doing so saves a device structure
189 * dereference by hardcoding the double copy threshold in place.
191 #define TG3_RX_COPY_THRESHOLD 256
192 #if NET_IP_ALIGN == 0 || defined(CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS)
193 #define TG3_RX_COPY_THRESH(tp) TG3_RX_COPY_THRESHOLD
195 #define TG3_RX_COPY_THRESH(tp) ((tp)->rx_copy_thresh)
198 #if (NET_IP_ALIGN != 0)
199 #define TG3_RX_OFFSET(tp) ((tp)->rx_offset)
201 #define TG3_RX_OFFSET(tp) (NET_SKB_PAD)
204 /* minimum number of free TX descriptors required to wake up TX process */
205 #define TG3_TX_WAKEUP_THRESH(tnapi) ((tnapi)->tx_pending / 4)
206 #define TG3_TX_BD_DMA_MAX_2K 2048
207 #define TG3_TX_BD_DMA_MAX_4K 4096
209 #define TG3_RAW_IP_ALIGN 2
211 #define TG3_MAX_UCAST_ADDR(tp) (tg3_flag((tp), ENABLE_ASF) ? 2 : 3)
212 #define TG3_UCAST_ADDR_IDX(tp) (tg3_flag((tp), ENABLE_ASF) ? 2 : 1)
214 #define TG3_FW_UPDATE_TIMEOUT_SEC 5
215 #define TG3_FW_UPDATE_FREQ_SEC (TG3_FW_UPDATE_TIMEOUT_SEC / 2)
217 #define FIRMWARE_TG3 "tigon/tg3.bin"
218 #define FIRMWARE_TG357766 "tigon/tg357766.bin"
219 #define FIRMWARE_TG3TSO "tigon/tg3_tso.bin"
220 #define FIRMWARE_TG3TSO5 "tigon/tg3_tso5.bin"
222 static char version[] =
223 DRV_MODULE_NAME ".c:v" DRV_MODULE_VERSION " (" DRV_MODULE_RELDATE ")";
225 MODULE_AUTHOR("David S. Miller (davem@redhat.com) and Jeff Garzik (jgarzik@pobox.com)");
226 MODULE_DESCRIPTION("Broadcom Tigon3 ethernet driver");
227 MODULE_LICENSE("GPL");
228 MODULE_VERSION(DRV_MODULE_VERSION);
229 MODULE_FIRMWARE(FIRMWARE_TG3);
230 MODULE_FIRMWARE(FIRMWARE_TG3TSO);
231 MODULE_FIRMWARE(FIRMWARE_TG3TSO5);
233 static int tg3_debug = -1; /* -1 == use TG3_DEF_MSG_ENABLE as value */
234 module_param(tg3_debug, int, 0);
235 MODULE_PARM_DESC(tg3_debug, "Tigon3 bitmapped debugging message enable value");
237 #define TG3_DRV_DATA_FLAG_10_100_ONLY 0x0001
238 #define TG3_DRV_DATA_FLAG_5705_10_100 0x0002
240 static DEFINE_PCI_DEVICE_TABLE(tg3_pci_tbl) = {
241 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5700)},
242 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5701)},
243 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702)},
244 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5703)},
245 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5704)},
246 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702FE)},
247 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705)},
248 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705_2)},
249 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705M)},
250 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705M_2)},
251 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702X)},
252 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5703X)},
253 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5704S)},
254 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702A3)},
255 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5703A3)},
256 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5782)},
257 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5788)},
258 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5789)},
259 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5901),
260 .driver_data = TG3_DRV_DATA_FLAG_10_100_ONLY |
261 TG3_DRV_DATA_FLAG_5705_10_100},
262 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5901_2),
263 .driver_data = TG3_DRV_DATA_FLAG_10_100_ONLY |
264 TG3_DRV_DATA_FLAG_5705_10_100},
265 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5704S_2)},
266 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705F),
267 .driver_data = TG3_DRV_DATA_FLAG_10_100_ONLY |
268 TG3_DRV_DATA_FLAG_5705_10_100},
269 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5721)},
270 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5722)},
271 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5750)},
272 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5751)},
273 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5751M)},
274 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5751F),
275 .driver_data = TG3_DRV_DATA_FLAG_10_100_ONLY},
276 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5752)},
277 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5752M)},
278 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5753)},
279 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5753M)},
280 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5753F),
281 .driver_data = TG3_DRV_DATA_FLAG_10_100_ONLY},
282 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5754)},
283 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5754M)},
284 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5755)},
285 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5755M)},
286 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5756)},
287 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5786)},
288 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5787)},
289 {PCI_DEVICE_SUB(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5787M,
290 PCI_VENDOR_ID_LENOVO,
291 TG3PCI_SUBDEVICE_ID_LENOVO_5787M),
292 .driver_data = TG3_DRV_DATA_FLAG_10_100_ONLY},
293 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5787M)},
294 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5787F),
295 .driver_data = TG3_DRV_DATA_FLAG_10_100_ONLY},
296 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5714)},
297 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5714S)},
298 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5715)},
299 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5715S)},
300 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5780)},
301 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5780S)},
302 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5781)},
303 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5906)},
304 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5906M)},
305 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5784)},
306 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5764)},
307 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5723)},
308 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5761)},
309 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5761E)},
310 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5761S)},
311 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5761SE)},
312 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5785_G)},
313 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5785_F)},
314 {PCI_DEVICE_SUB(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57780,
315 PCI_VENDOR_ID_AI, TG3PCI_SUBDEVICE_ID_ACER_57780_A),
316 .driver_data = TG3_DRV_DATA_FLAG_10_100_ONLY},
317 {PCI_DEVICE_SUB(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57780,
318 PCI_VENDOR_ID_AI, TG3PCI_SUBDEVICE_ID_ACER_57780_B),
319 .driver_data = TG3_DRV_DATA_FLAG_10_100_ONLY},
320 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57780)},
321 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57760)},
322 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57790),
323 .driver_data = TG3_DRV_DATA_FLAG_10_100_ONLY},
324 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57788)},
325 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5717)},
326 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5717_C)},
327 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5718)},
328 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57781)},
329 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57785)},
330 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57761)},
331 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57765)},
332 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57791),
333 .driver_data = TG3_DRV_DATA_FLAG_10_100_ONLY},
334 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57795),
335 .driver_data = TG3_DRV_DATA_FLAG_10_100_ONLY},
336 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5719)},
337 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5720)},
338 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57762)},
339 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57766)},
340 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5762)},
341 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5725)},
342 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5727)},
343 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57764)},
344 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57767)},
345 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57787)},
346 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57782)},
347 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57786)},
348 {PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, PCI_DEVICE_ID_SYSKONNECT_9DXX)},
349 {PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, PCI_DEVICE_ID_SYSKONNECT_9MXX)},
350 {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC1000)},
351 {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC1001)},
352 {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC1003)},
353 {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC9100)},
354 {PCI_DEVICE(PCI_VENDOR_ID_APPLE, PCI_DEVICE_ID_APPLE_TIGON3)},
355 {PCI_DEVICE(0x10cf, 0x11a2)}, /* Fujitsu 1000base-SX with BCM5703SKHB */
359 MODULE_DEVICE_TABLE(pci, tg3_pci_tbl);
361 static const struct {
362 const char string[ETH_GSTRING_LEN];
363 } ethtool_stats_keys[] = {
366 { "rx_ucast_packets" },
367 { "rx_mcast_packets" },
368 { "rx_bcast_packets" },
370 { "rx_align_errors" },
371 { "rx_xon_pause_rcvd" },
372 { "rx_xoff_pause_rcvd" },
373 { "rx_mac_ctrl_rcvd" },
374 { "rx_xoff_entered" },
375 { "rx_frame_too_long_errors" },
377 { "rx_undersize_packets" },
378 { "rx_in_length_errors" },
379 { "rx_out_length_errors" },
380 { "rx_64_or_less_octet_packets" },
381 { "rx_65_to_127_octet_packets" },
382 { "rx_128_to_255_octet_packets" },
383 { "rx_256_to_511_octet_packets" },
384 { "rx_512_to_1023_octet_packets" },
385 { "rx_1024_to_1522_octet_packets" },
386 { "rx_1523_to_2047_octet_packets" },
387 { "rx_2048_to_4095_octet_packets" },
388 { "rx_4096_to_8191_octet_packets" },
389 { "rx_8192_to_9022_octet_packets" },
396 { "tx_flow_control" },
398 { "tx_single_collisions" },
399 { "tx_mult_collisions" },
401 { "tx_excessive_collisions" },
402 { "tx_late_collisions" },
403 { "tx_collide_2times" },
404 { "tx_collide_3times" },
405 { "tx_collide_4times" },
406 { "tx_collide_5times" },
407 { "tx_collide_6times" },
408 { "tx_collide_7times" },
409 { "tx_collide_8times" },
410 { "tx_collide_9times" },
411 { "tx_collide_10times" },
412 { "tx_collide_11times" },
413 { "tx_collide_12times" },
414 { "tx_collide_13times" },
415 { "tx_collide_14times" },
416 { "tx_collide_15times" },
417 { "tx_ucast_packets" },
418 { "tx_mcast_packets" },
419 { "tx_bcast_packets" },
420 { "tx_carrier_sense_errors" },
424 { "dma_writeq_full" },
425 { "dma_write_prioq_full" },
429 { "rx_threshold_hit" },
431 { "dma_readq_full" },
432 { "dma_read_prioq_full" },
433 { "tx_comp_queue_full" },
435 { "ring_set_send_prod_index" },
436 { "ring_status_update" },
438 { "nic_avoided_irqs" },
439 { "nic_tx_threshold_hit" },
441 { "mbuf_lwm_thresh_hit" },
444 #define TG3_NUM_STATS ARRAY_SIZE(ethtool_stats_keys)
445 #define TG3_NVRAM_TEST 0
446 #define TG3_LINK_TEST 1
447 #define TG3_REGISTER_TEST 2
448 #define TG3_MEMORY_TEST 3
449 #define TG3_MAC_LOOPB_TEST 4
450 #define TG3_PHY_LOOPB_TEST 5
451 #define TG3_EXT_LOOPB_TEST 6
452 #define TG3_INTERRUPT_TEST 7
455 static const struct {
456 const char string[ETH_GSTRING_LEN];
457 } ethtool_test_keys[] = {
458 [TG3_NVRAM_TEST] = { "nvram test (online) " },
459 [TG3_LINK_TEST] = { "link test (online) " },
460 [TG3_REGISTER_TEST] = { "register test (offline)" },
461 [TG3_MEMORY_TEST] = { "memory test (offline)" },
462 [TG3_MAC_LOOPB_TEST] = { "mac loopback test (offline)" },
463 [TG3_PHY_LOOPB_TEST] = { "phy loopback test (offline)" },
464 [TG3_EXT_LOOPB_TEST] = { "ext loopback test (offline)" },
465 [TG3_INTERRUPT_TEST] = { "interrupt test (offline)" },
468 #define TG3_NUM_TEST ARRAY_SIZE(ethtool_test_keys)
471 static void tg3_write32(struct tg3 *tp, u32 off, u32 val)
473 writel(val, tp->regs + off);
476 static u32 tg3_read32(struct tg3 *tp, u32 off)
478 return readl(tp->regs + off);
481 static void tg3_ape_write32(struct tg3 *tp, u32 off, u32 val)
483 writel(val, tp->aperegs + off);
486 static u32 tg3_ape_read32(struct tg3 *tp, u32 off)
488 return readl(tp->aperegs + off);
491 static void tg3_write_indirect_reg32(struct tg3 *tp, u32 off, u32 val)
495 spin_lock_irqsave(&tp->indirect_lock, flags);
496 pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off);
497 pci_write_config_dword(tp->pdev, TG3PCI_REG_DATA, val);
498 spin_unlock_irqrestore(&tp->indirect_lock, flags);
501 static void tg3_write_flush_reg32(struct tg3 *tp, u32 off, u32 val)
503 writel(val, tp->regs + off);
504 readl(tp->regs + off);
507 static u32 tg3_read_indirect_reg32(struct tg3 *tp, u32 off)
512 spin_lock_irqsave(&tp->indirect_lock, flags);
513 pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off);
514 pci_read_config_dword(tp->pdev, TG3PCI_REG_DATA, &val);
515 spin_unlock_irqrestore(&tp->indirect_lock, flags);
519 static void tg3_write_indirect_mbox(struct tg3 *tp, u32 off, u32 val)
523 if (off == (MAILBOX_RCVRET_CON_IDX_0 + TG3_64BIT_REG_LOW)) {
524 pci_write_config_dword(tp->pdev, TG3PCI_RCV_RET_RING_CON_IDX +
525 TG3_64BIT_REG_LOW, val);
528 if (off == TG3_RX_STD_PROD_IDX_REG) {
529 pci_write_config_dword(tp->pdev, TG3PCI_STD_RING_PROD_IDX +
530 TG3_64BIT_REG_LOW, val);
534 spin_lock_irqsave(&tp->indirect_lock, flags);
535 pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off + 0x5600);
536 pci_write_config_dword(tp->pdev, TG3PCI_REG_DATA, val);
537 spin_unlock_irqrestore(&tp->indirect_lock, flags);
539 /* In indirect mode when disabling interrupts, we also need
540 * to clear the interrupt bit in the GRC local ctrl register.
542 if ((off == (MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW)) &&
544 pci_write_config_dword(tp->pdev, TG3PCI_MISC_LOCAL_CTRL,
545 tp->grc_local_ctrl|GRC_LCLCTRL_CLEARINT);
549 static u32 tg3_read_indirect_mbox(struct tg3 *tp, u32 off)
554 spin_lock_irqsave(&tp->indirect_lock, flags);
555 pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off + 0x5600);
556 pci_read_config_dword(tp->pdev, TG3PCI_REG_DATA, &val);
557 spin_unlock_irqrestore(&tp->indirect_lock, flags);
561 /* usec_wait specifies the wait time in usec when writing to certain registers
562 * where it is unsafe to read back the register without some delay.
563 * GRC_LOCAL_CTRL is one example if the GPIOs are toggled to switch power.
564 * TG3PCI_CLOCK_CTRL is another example if the clock frequencies are changed.
566 static void _tw32_flush(struct tg3 *tp, u32 off, u32 val, u32 usec_wait)
568 if (tg3_flag(tp, PCIX_TARGET_HWBUG) || tg3_flag(tp, ICH_WORKAROUND))
569 /* Non-posted methods */
570 tp->write32(tp, off, val);
573 tg3_write32(tp, off, val);
578 /* Wait again after the read for the posted method to guarantee that
579 * the wait time is met.
585 static inline void tw32_mailbox_flush(struct tg3 *tp, u32 off, u32 val)
587 tp->write32_mbox(tp, off, val);
588 if (tg3_flag(tp, FLUSH_POSTED_WRITES) ||
589 (!tg3_flag(tp, MBOX_WRITE_REORDER) &&
590 !tg3_flag(tp, ICH_WORKAROUND)))
591 tp->read32_mbox(tp, off);
594 static void tg3_write32_tx_mbox(struct tg3 *tp, u32 off, u32 val)
596 void __iomem *mbox = tp->regs + off;
598 if (tg3_flag(tp, TXD_MBOX_HWBUG))
600 if (tg3_flag(tp, MBOX_WRITE_REORDER) ||
601 tg3_flag(tp, FLUSH_POSTED_WRITES))
605 static u32 tg3_read32_mbox_5906(struct tg3 *tp, u32 off)
607 return readl(tp->regs + off + GRCMBOX_BASE);
610 static void tg3_write32_mbox_5906(struct tg3 *tp, u32 off, u32 val)
612 writel(val, tp->regs + off + GRCMBOX_BASE);
615 #define tw32_mailbox(reg, val) tp->write32_mbox(tp, reg, val)
616 #define tw32_mailbox_f(reg, val) tw32_mailbox_flush(tp, (reg), (val))
617 #define tw32_rx_mbox(reg, val) tp->write32_rx_mbox(tp, reg, val)
618 #define tw32_tx_mbox(reg, val) tp->write32_tx_mbox(tp, reg, val)
619 #define tr32_mailbox(reg) tp->read32_mbox(tp, reg)
621 #define tw32(reg, val) tp->write32(tp, reg, val)
622 #define tw32_f(reg, val) _tw32_flush(tp, (reg), (val), 0)
623 #define tw32_wait_f(reg, val, us) _tw32_flush(tp, (reg), (val), (us))
624 #define tr32(reg) tp->read32(tp, reg)
626 static void tg3_write_mem(struct tg3 *tp, u32 off, u32 val)
630 if (tg3_asic_rev(tp) == ASIC_REV_5906 &&
631 (off >= NIC_SRAM_STATS_BLK) && (off < NIC_SRAM_TX_BUFFER_DESC))
634 spin_lock_irqsave(&tp->indirect_lock, flags);
635 if (tg3_flag(tp, SRAM_USE_CONFIG)) {
636 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, off);
637 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_DATA, val);
639 /* Always leave this as zero. */
640 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, 0);
642 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, off);
643 tw32_f(TG3PCI_MEM_WIN_DATA, val);
645 /* Always leave this as zero. */
646 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, 0);
648 spin_unlock_irqrestore(&tp->indirect_lock, flags);
651 static void tg3_read_mem(struct tg3 *tp, u32 off, u32 *val)
655 if (tg3_asic_rev(tp) == ASIC_REV_5906 &&
656 (off >= NIC_SRAM_STATS_BLK) && (off < NIC_SRAM_TX_BUFFER_DESC)) {
661 spin_lock_irqsave(&tp->indirect_lock, flags);
662 if (tg3_flag(tp, SRAM_USE_CONFIG)) {
663 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, off);
664 pci_read_config_dword(tp->pdev, TG3PCI_MEM_WIN_DATA, val);
666 /* Always leave this as zero. */
667 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, 0);
669 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, off);
670 *val = tr32(TG3PCI_MEM_WIN_DATA);
672 /* Always leave this as zero. */
673 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, 0);
675 spin_unlock_irqrestore(&tp->indirect_lock, flags);
678 static void tg3_ape_lock_init(struct tg3 *tp)
683 if (tg3_asic_rev(tp) == ASIC_REV_5761)
684 regbase = TG3_APE_LOCK_GRANT;
686 regbase = TG3_APE_PER_LOCK_GRANT;
688 /* Make sure the driver hasn't any stale locks. */
689 for (i = TG3_APE_LOCK_PHY0; i <= TG3_APE_LOCK_GPIO; i++) {
691 case TG3_APE_LOCK_PHY0:
692 case TG3_APE_LOCK_PHY1:
693 case TG3_APE_LOCK_PHY2:
694 case TG3_APE_LOCK_PHY3:
695 bit = APE_LOCK_GRANT_DRIVER;
699 bit = APE_LOCK_GRANT_DRIVER;
701 bit = 1 << tp->pci_fn;
703 tg3_ape_write32(tp, regbase + 4 * i, bit);
708 static int tg3_ape_lock(struct tg3 *tp, int locknum)
712 u32 status, req, gnt, bit;
714 if (!tg3_flag(tp, ENABLE_APE))
718 case TG3_APE_LOCK_GPIO:
719 if (tg3_asic_rev(tp) == ASIC_REV_5761)
721 case TG3_APE_LOCK_GRC:
722 case TG3_APE_LOCK_MEM:
724 bit = APE_LOCK_REQ_DRIVER;
726 bit = 1 << tp->pci_fn;
728 case TG3_APE_LOCK_PHY0:
729 case TG3_APE_LOCK_PHY1:
730 case TG3_APE_LOCK_PHY2:
731 case TG3_APE_LOCK_PHY3:
732 bit = APE_LOCK_REQ_DRIVER;
738 if (tg3_asic_rev(tp) == ASIC_REV_5761) {
739 req = TG3_APE_LOCK_REQ;
740 gnt = TG3_APE_LOCK_GRANT;
742 req = TG3_APE_PER_LOCK_REQ;
743 gnt = TG3_APE_PER_LOCK_GRANT;
748 tg3_ape_write32(tp, req + off, bit);
750 /* Wait for up to 1 millisecond to acquire lock. */
751 for (i = 0; i < 100; i++) {
752 status = tg3_ape_read32(tp, gnt + off);
755 if (pci_channel_offline(tp->pdev))
762 /* Revoke the lock request. */
763 tg3_ape_write32(tp, gnt + off, bit);
770 static void tg3_ape_unlock(struct tg3 *tp, int locknum)
774 if (!tg3_flag(tp, ENABLE_APE))
778 case TG3_APE_LOCK_GPIO:
779 if (tg3_asic_rev(tp) == ASIC_REV_5761)
781 case TG3_APE_LOCK_GRC:
782 case TG3_APE_LOCK_MEM:
784 bit = APE_LOCK_GRANT_DRIVER;
786 bit = 1 << tp->pci_fn;
788 case TG3_APE_LOCK_PHY0:
789 case TG3_APE_LOCK_PHY1:
790 case TG3_APE_LOCK_PHY2:
791 case TG3_APE_LOCK_PHY3:
792 bit = APE_LOCK_GRANT_DRIVER;
798 if (tg3_asic_rev(tp) == ASIC_REV_5761)
799 gnt = TG3_APE_LOCK_GRANT;
801 gnt = TG3_APE_PER_LOCK_GRANT;
803 tg3_ape_write32(tp, gnt + 4 * locknum, bit);
806 static int tg3_ape_event_lock(struct tg3 *tp, u32 timeout_us)
811 if (tg3_ape_lock(tp, TG3_APE_LOCK_MEM))
814 apedata = tg3_ape_read32(tp, TG3_APE_EVENT_STATUS);
815 if (!(apedata & APE_EVENT_STATUS_EVENT_PENDING))
818 tg3_ape_unlock(tp, TG3_APE_LOCK_MEM);
821 timeout_us -= (timeout_us > 10) ? 10 : timeout_us;
824 return timeout_us ? 0 : -EBUSY;
827 static int tg3_ape_wait_for_event(struct tg3 *tp, u32 timeout_us)
831 for (i = 0; i < timeout_us / 10; i++) {
832 apedata = tg3_ape_read32(tp, TG3_APE_EVENT_STATUS);
834 if (!(apedata & APE_EVENT_STATUS_EVENT_PENDING))
840 return i == timeout_us / 10;
843 static int tg3_ape_scratchpad_read(struct tg3 *tp, u32 *data, u32 base_off,
847 u32 i, bufoff, msgoff, maxlen, apedata;
849 if (!tg3_flag(tp, APE_HAS_NCSI))
852 apedata = tg3_ape_read32(tp, TG3_APE_SEG_SIG);
853 if (apedata != APE_SEG_SIG_MAGIC)
856 apedata = tg3_ape_read32(tp, TG3_APE_FW_STATUS);
857 if (!(apedata & APE_FW_STATUS_READY))
860 bufoff = tg3_ape_read32(tp, TG3_APE_SEG_MSG_BUF_OFF) +
862 msgoff = bufoff + 2 * sizeof(u32);
863 maxlen = tg3_ape_read32(tp, TG3_APE_SEG_MSG_BUF_LEN);
868 /* Cap xfer sizes to scratchpad limits. */
869 length = (len > maxlen) ? maxlen : len;
872 apedata = tg3_ape_read32(tp, TG3_APE_FW_STATUS);
873 if (!(apedata & APE_FW_STATUS_READY))
876 /* Wait for up to 1 msec for APE to service previous event. */
877 err = tg3_ape_event_lock(tp, 1000);
881 apedata = APE_EVENT_STATUS_DRIVER_EVNT |
882 APE_EVENT_STATUS_SCRTCHPD_READ |
883 APE_EVENT_STATUS_EVENT_PENDING;
884 tg3_ape_write32(tp, TG3_APE_EVENT_STATUS, apedata);
886 tg3_ape_write32(tp, bufoff, base_off);
887 tg3_ape_write32(tp, bufoff + sizeof(u32), length);
889 tg3_ape_unlock(tp, TG3_APE_LOCK_MEM);
890 tg3_ape_write32(tp, TG3_APE_EVENT, APE_EVENT_1);
894 if (tg3_ape_wait_for_event(tp, 30000))
897 for (i = 0; length; i += 4, length -= 4) {
898 u32 val = tg3_ape_read32(tp, msgoff + i);
899 memcpy(data, &val, sizeof(u32));
907 static int tg3_ape_send_event(struct tg3 *tp, u32 event)
912 apedata = tg3_ape_read32(tp, TG3_APE_SEG_SIG);
913 if (apedata != APE_SEG_SIG_MAGIC)
916 apedata = tg3_ape_read32(tp, TG3_APE_FW_STATUS);
917 if (!(apedata & APE_FW_STATUS_READY))
920 /* Wait for up to 1 millisecond for APE to service previous event. */
921 err = tg3_ape_event_lock(tp, 1000);
925 tg3_ape_write32(tp, TG3_APE_EVENT_STATUS,
926 event | APE_EVENT_STATUS_EVENT_PENDING);
928 tg3_ape_unlock(tp, TG3_APE_LOCK_MEM);
929 tg3_ape_write32(tp, TG3_APE_EVENT, APE_EVENT_1);
934 static void tg3_ape_driver_state_change(struct tg3 *tp, int kind)
939 if (!tg3_flag(tp, ENABLE_APE))
943 case RESET_KIND_INIT:
944 tg3_ape_write32(tp, TG3_APE_HOST_SEG_SIG,
945 APE_HOST_SEG_SIG_MAGIC);
946 tg3_ape_write32(tp, TG3_APE_HOST_SEG_LEN,
947 APE_HOST_SEG_LEN_MAGIC);
948 apedata = tg3_ape_read32(tp, TG3_APE_HOST_INIT_COUNT);
949 tg3_ape_write32(tp, TG3_APE_HOST_INIT_COUNT, ++apedata);
950 tg3_ape_write32(tp, TG3_APE_HOST_DRIVER_ID,
951 APE_HOST_DRIVER_ID_MAGIC(TG3_MAJ_NUM, TG3_MIN_NUM));
952 tg3_ape_write32(tp, TG3_APE_HOST_BEHAVIOR,
953 APE_HOST_BEHAV_NO_PHYLOCK);
954 tg3_ape_write32(tp, TG3_APE_HOST_DRVR_STATE,
955 TG3_APE_HOST_DRVR_STATE_START);
957 event = APE_EVENT_STATUS_STATE_START;
959 case RESET_KIND_SHUTDOWN:
960 /* With the interface we are currently using,
961 * APE does not track driver state. Wiping
962 * out the HOST SEGMENT SIGNATURE forces
963 * the APE to assume OS absent status.
965 tg3_ape_write32(tp, TG3_APE_HOST_SEG_SIG, 0x0);
967 if (device_may_wakeup(&tp->pdev->dev) &&
968 tg3_flag(tp, WOL_ENABLE)) {
969 tg3_ape_write32(tp, TG3_APE_HOST_WOL_SPEED,
970 TG3_APE_HOST_WOL_SPEED_AUTO);
971 apedata = TG3_APE_HOST_DRVR_STATE_WOL;
973 apedata = TG3_APE_HOST_DRVR_STATE_UNLOAD;
975 tg3_ape_write32(tp, TG3_APE_HOST_DRVR_STATE, apedata);
977 event = APE_EVENT_STATUS_STATE_UNLOAD;
983 event |= APE_EVENT_STATUS_DRIVER_EVNT | APE_EVENT_STATUS_STATE_CHNGE;
985 tg3_ape_send_event(tp, event);
988 static void tg3_disable_ints(struct tg3 *tp)
992 tw32(TG3PCI_MISC_HOST_CTRL,
993 (tp->misc_host_ctrl | MISC_HOST_CTRL_MASK_PCI_INT));
994 for (i = 0; i < tp->irq_max; i++)
995 tw32_mailbox_f(tp->napi[i].int_mbox, 0x00000001);
998 static void tg3_enable_ints(struct tg3 *tp)
1005 tw32(TG3PCI_MISC_HOST_CTRL,
1006 (tp->misc_host_ctrl & ~MISC_HOST_CTRL_MASK_PCI_INT));
1008 tp->coal_now = tp->coalesce_mode | HOSTCC_MODE_ENABLE;
1009 for (i = 0; i < tp->irq_cnt; i++) {
1010 struct tg3_napi *tnapi = &tp->napi[i];
1012 tw32_mailbox_f(tnapi->int_mbox, tnapi->last_tag << 24);
1013 if (tg3_flag(tp, 1SHOT_MSI))
1014 tw32_mailbox_f(tnapi->int_mbox, tnapi->last_tag << 24);
1016 tp->coal_now |= tnapi->coal_now;
1019 /* Force an initial interrupt */
1020 if (!tg3_flag(tp, TAGGED_STATUS) &&
1021 (tp->napi[0].hw_status->status & SD_STATUS_UPDATED))
1022 tw32(GRC_LOCAL_CTRL, tp->grc_local_ctrl | GRC_LCLCTRL_SETINT);
1024 tw32(HOSTCC_MODE, tp->coal_now);
1026 tp->coal_now &= ~(tp->napi[0].coal_now | tp->napi[1].coal_now);
1029 static inline unsigned int tg3_has_work(struct tg3_napi *tnapi)
1031 struct tg3 *tp = tnapi->tp;
1032 struct tg3_hw_status *sblk = tnapi->hw_status;
1033 unsigned int work_exists = 0;
1035 /* check for phy events */
1036 if (!(tg3_flag(tp, USE_LINKCHG_REG) || tg3_flag(tp, POLL_SERDES))) {
1037 if (sblk->status & SD_STATUS_LINK_CHG)
1041 /* check for TX work to do */
1042 if (sblk->idx[0].tx_consumer != tnapi->tx_cons)
1045 /* check for RX work to do */
1046 if (tnapi->rx_rcb_prod_idx &&
1047 *(tnapi->rx_rcb_prod_idx) != tnapi->rx_rcb_ptr)
1054 * similar to tg3_enable_ints, but it accurately determines whether there
1055 * is new work pending and can return without flushing the PIO write
1056 * which reenables interrupts
1058 static void tg3_int_reenable(struct tg3_napi *tnapi)
1060 struct tg3 *tp = tnapi->tp;
1062 tw32_mailbox(tnapi->int_mbox, tnapi->last_tag << 24);
1065 /* When doing tagged status, this work check is unnecessary.
1066 * The last_tag we write above tells the chip which piece of
1067 * work we've completed.
1069 if (!tg3_flag(tp, TAGGED_STATUS) && tg3_has_work(tnapi))
1070 tw32(HOSTCC_MODE, tp->coalesce_mode |
1071 HOSTCC_MODE_ENABLE | tnapi->coal_now);
1074 static void tg3_switch_clocks(struct tg3 *tp)
1077 u32 orig_clock_ctrl;
1079 if (tg3_flag(tp, CPMU_PRESENT) || tg3_flag(tp, 5780_CLASS))
1082 clock_ctrl = tr32(TG3PCI_CLOCK_CTRL);
1084 orig_clock_ctrl = clock_ctrl;
1085 clock_ctrl &= (CLOCK_CTRL_FORCE_CLKRUN |
1086 CLOCK_CTRL_CLKRUN_OENABLE |
1088 tp->pci_clock_ctrl = clock_ctrl;
1090 if (tg3_flag(tp, 5705_PLUS)) {
1091 if (orig_clock_ctrl & CLOCK_CTRL_625_CORE) {
1092 tw32_wait_f(TG3PCI_CLOCK_CTRL,
1093 clock_ctrl | CLOCK_CTRL_625_CORE, 40);
1095 } else if ((orig_clock_ctrl & CLOCK_CTRL_44MHZ_CORE) != 0) {
1096 tw32_wait_f(TG3PCI_CLOCK_CTRL,
1098 (CLOCK_CTRL_44MHZ_CORE | CLOCK_CTRL_ALTCLK),
1100 tw32_wait_f(TG3PCI_CLOCK_CTRL,
1101 clock_ctrl | (CLOCK_CTRL_ALTCLK),
1104 tw32_wait_f(TG3PCI_CLOCK_CTRL, clock_ctrl, 40);
1107 #define PHY_BUSY_LOOPS 5000
1109 static int __tg3_readphy(struct tg3 *tp, unsigned int phy_addr, int reg,
1116 if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
1118 (tp->mi_mode & ~MAC_MI_MODE_AUTO_POLL));
1122 tg3_ape_lock(tp, tp->phy_ape_lock);
1126 frame_val = ((phy_addr << MI_COM_PHY_ADDR_SHIFT) &
1127 MI_COM_PHY_ADDR_MASK);
1128 frame_val |= ((reg << MI_COM_REG_ADDR_SHIFT) &
1129 MI_COM_REG_ADDR_MASK);
1130 frame_val |= (MI_COM_CMD_READ | MI_COM_START);
1132 tw32_f(MAC_MI_COM, frame_val);
1134 loops = PHY_BUSY_LOOPS;
1135 while (loops != 0) {
1137 frame_val = tr32(MAC_MI_COM);
1139 if ((frame_val & MI_COM_BUSY) == 0) {
1141 frame_val = tr32(MAC_MI_COM);
1149 *val = frame_val & MI_COM_DATA_MASK;
1153 if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
1154 tw32_f(MAC_MI_MODE, tp->mi_mode);
1158 tg3_ape_unlock(tp, tp->phy_ape_lock);
1163 static int tg3_readphy(struct tg3 *tp, int reg, u32 *val)
1165 return __tg3_readphy(tp, tp->phy_addr, reg, val);
1168 static int __tg3_writephy(struct tg3 *tp, unsigned int phy_addr, int reg,
1175 if ((tp->phy_flags & TG3_PHYFLG_IS_FET) &&
1176 (reg == MII_CTRL1000 || reg == MII_TG3_AUX_CTRL))
1179 if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
1181 (tp->mi_mode & ~MAC_MI_MODE_AUTO_POLL));
1185 tg3_ape_lock(tp, tp->phy_ape_lock);
1187 frame_val = ((phy_addr << MI_COM_PHY_ADDR_SHIFT) &
1188 MI_COM_PHY_ADDR_MASK);
1189 frame_val |= ((reg << MI_COM_REG_ADDR_SHIFT) &
1190 MI_COM_REG_ADDR_MASK);
1191 frame_val |= (val & MI_COM_DATA_MASK);
1192 frame_val |= (MI_COM_CMD_WRITE | MI_COM_START);
1194 tw32_f(MAC_MI_COM, frame_val);
1196 loops = PHY_BUSY_LOOPS;
1197 while (loops != 0) {
1199 frame_val = tr32(MAC_MI_COM);
1200 if ((frame_val & MI_COM_BUSY) == 0) {
1202 frame_val = tr32(MAC_MI_COM);
1212 if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
1213 tw32_f(MAC_MI_MODE, tp->mi_mode);
1217 tg3_ape_unlock(tp, tp->phy_ape_lock);
1222 static int tg3_writephy(struct tg3 *tp, int reg, u32 val)
1224 return __tg3_writephy(tp, tp->phy_addr, reg, val);
1227 static int tg3_phy_cl45_write(struct tg3 *tp, u32 devad, u32 addr, u32 val)
1231 err = tg3_writephy(tp, MII_TG3_MMD_CTRL, devad);
1235 err = tg3_writephy(tp, MII_TG3_MMD_ADDRESS, addr);
1239 err = tg3_writephy(tp, MII_TG3_MMD_CTRL,
1240 MII_TG3_MMD_CTRL_DATA_NOINC | devad);
1244 err = tg3_writephy(tp, MII_TG3_MMD_ADDRESS, val);
1250 static int tg3_phy_cl45_read(struct tg3 *tp, u32 devad, u32 addr, u32 *val)
1254 err = tg3_writephy(tp, MII_TG3_MMD_CTRL, devad);
1258 err = tg3_writephy(tp, MII_TG3_MMD_ADDRESS, addr);
1262 err = tg3_writephy(tp, MII_TG3_MMD_CTRL,
1263 MII_TG3_MMD_CTRL_DATA_NOINC | devad);
1267 err = tg3_readphy(tp, MII_TG3_MMD_ADDRESS, val);
1273 static int tg3_phydsp_read(struct tg3 *tp, u32 reg, u32 *val)
1277 err = tg3_writephy(tp, MII_TG3_DSP_ADDRESS, reg);
1279 err = tg3_readphy(tp, MII_TG3_DSP_RW_PORT, val);
1284 static int tg3_phydsp_write(struct tg3 *tp, u32 reg, u32 val)
1288 err = tg3_writephy(tp, MII_TG3_DSP_ADDRESS, reg);
1290 err = tg3_writephy(tp, MII_TG3_DSP_RW_PORT, val);
1295 static int tg3_phy_auxctl_read(struct tg3 *tp, int reg, u32 *val)
1299 err = tg3_writephy(tp, MII_TG3_AUX_CTRL,
1300 (reg << MII_TG3_AUXCTL_MISC_RDSEL_SHIFT) |
1301 MII_TG3_AUXCTL_SHDWSEL_MISC);
1303 err = tg3_readphy(tp, MII_TG3_AUX_CTRL, val);
1308 static int tg3_phy_auxctl_write(struct tg3 *tp, int reg, u32 set)
1310 if (reg == MII_TG3_AUXCTL_SHDWSEL_MISC)
1311 set |= MII_TG3_AUXCTL_MISC_WREN;
1313 return tg3_writephy(tp, MII_TG3_AUX_CTRL, set | reg);
1316 static int tg3_phy_toggle_auxctl_smdsp(struct tg3 *tp, bool enable)
1321 err = tg3_phy_auxctl_read(tp, MII_TG3_AUXCTL_SHDWSEL_AUXCTL, &val);
1327 val |= MII_TG3_AUXCTL_ACTL_SMDSP_ENA;
1329 val &= ~MII_TG3_AUXCTL_ACTL_SMDSP_ENA;
1331 err = tg3_phy_auxctl_write((tp), MII_TG3_AUXCTL_SHDWSEL_AUXCTL,
1332 val | MII_TG3_AUXCTL_ACTL_TX_6DB);
1337 static int tg3_phy_shdw_write(struct tg3 *tp, int reg, u32 val)
1339 return tg3_writephy(tp, MII_TG3_MISC_SHDW,
1340 reg | val | MII_TG3_MISC_SHDW_WREN);
1343 static int tg3_bmcr_reset(struct tg3 *tp)
1348 /* OK, reset it, and poll the BMCR_RESET bit until it
1349 * clears or we time out.
1351 phy_control = BMCR_RESET;
1352 err = tg3_writephy(tp, MII_BMCR, phy_control);
1358 err = tg3_readphy(tp, MII_BMCR, &phy_control);
1362 if ((phy_control & BMCR_RESET) == 0) {
1374 static int tg3_mdio_read(struct mii_bus *bp, int mii_id, int reg)
1376 struct tg3 *tp = bp->priv;
1379 spin_lock_bh(&tp->lock);
1381 if (__tg3_readphy(tp, mii_id, reg, &val))
1384 spin_unlock_bh(&tp->lock);
1389 static int tg3_mdio_write(struct mii_bus *bp, int mii_id, int reg, u16 val)
1391 struct tg3 *tp = bp->priv;
1394 spin_lock_bh(&tp->lock);
1396 if (__tg3_writephy(tp, mii_id, reg, val))
1399 spin_unlock_bh(&tp->lock);
1404 static void tg3_mdio_config_5785(struct tg3 *tp)
1407 struct phy_device *phydev;
1409 phydev = tp->mdio_bus->phy_map[tp->phy_addr];
1410 switch (phydev->drv->phy_id & phydev->drv->phy_id_mask) {
1411 case PHY_ID_BCM50610:
1412 case PHY_ID_BCM50610M:
1413 val = MAC_PHYCFG2_50610_LED_MODES;
1415 case PHY_ID_BCMAC131:
1416 val = MAC_PHYCFG2_AC131_LED_MODES;
1418 case PHY_ID_RTL8211C:
1419 val = MAC_PHYCFG2_RTL8211C_LED_MODES;
1421 case PHY_ID_RTL8201E:
1422 val = MAC_PHYCFG2_RTL8201E_LED_MODES;
1428 if (phydev->interface != PHY_INTERFACE_MODE_RGMII) {
1429 tw32(MAC_PHYCFG2, val);
1431 val = tr32(MAC_PHYCFG1);
1432 val &= ~(MAC_PHYCFG1_RGMII_INT |
1433 MAC_PHYCFG1_RXCLK_TO_MASK | MAC_PHYCFG1_TXCLK_TO_MASK);
1434 val |= MAC_PHYCFG1_RXCLK_TIMEOUT | MAC_PHYCFG1_TXCLK_TIMEOUT;
1435 tw32(MAC_PHYCFG1, val);
1440 if (!tg3_flag(tp, RGMII_INBAND_DISABLE))
1441 val |= MAC_PHYCFG2_EMODE_MASK_MASK |
1442 MAC_PHYCFG2_FMODE_MASK_MASK |
1443 MAC_PHYCFG2_GMODE_MASK_MASK |
1444 MAC_PHYCFG2_ACT_MASK_MASK |
1445 MAC_PHYCFG2_QUAL_MASK_MASK |
1446 MAC_PHYCFG2_INBAND_ENABLE;
1448 tw32(MAC_PHYCFG2, val);
1450 val = tr32(MAC_PHYCFG1);
1451 val &= ~(MAC_PHYCFG1_RXCLK_TO_MASK | MAC_PHYCFG1_TXCLK_TO_MASK |
1452 MAC_PHYCFG1_RGMII_EXT_RX_DEC | MAC_PHYCFG1_RGMII_SND_STAT_EN);
1453 if (!tg3_flag(tp, RGMII_INBAND_DISABLE)) {
1454 if (tg3_flag(tp, RGMII_EXT_IBND_RX_EN))
1455 val |= MAC_PHYCFG1_RGMII_EXT_RX_DEC;
1456 if (tg3_flag(tp, RGMII_EXT_IBND_TX_EN))
1457 val |= MAC_PHYCFG1_RGMII_SND_STAT_EN;
1459 val |= MAC_PHYCFG1_RXCLK_TIMEOUT | MAC_PHYCFG1_TXCLK_TIMEOUT |
1460 MAC_PHYCFG1_RGMII_INT | MAC_PHYCFG1_TXC_DRV;
1461 tw32(MAC_PHYCFG1, val);
1463 val = tr32(MAC_EXT_RGMII_MODE);
1464 val &= ~(MAC_RGMII_MODE_RX_INT_B |
1465 MAC_RGMII_MODE_RX_QUALITY |
1466 MAC_RGMII_MODE_RX_ACTIVITY |
1467 MAC_RGMII_MODE_RX_ENG_DET |
1468 MAC_RGMII_MODE_TX_ENABLE |
1469 MAC_RGMII_MODE_TX_LOWPWR |
1470 MAC_RGMII_MODE_TX_RESET);
1471 if (!tg3_flag(tp, RGMII_INBAND_DISABLE)) {
1472 if (tg3_flag(tp, RGMII_EXT_IBND_RX_EN))
1473 val |= MAC_RGMII_MODE_RX_INT_B |
1474 MAC_RGMII_MODE_RX_QUALITY |
1475 MAC_RGMII_MODE_RX_ACTIVITY |
1476 MAC_RGMII_MODE_RX_ENG_DET;
1477 if (tg3_flag(tp, RGMII_EXT_IBND_TX_EN))
1478 val |= MAC_RGMII_MODE_TX_ENABLE |
1479 MAC_RGMII_MODE_TX_LOWPWR |
1480 MAC_RGMII_MODE_TX_RESET;
1482 tw32(MAC_EXT_RGMII_MODE, val);
1485 static void tg3_mdio_start(struct tg3 *tp)
1487 tp->mi_mode &= ~MAC_MI_MODE_AUTO_POLL;
1488 tw32_f(MAC_MI_MODE, tp->mi_mode);
1491 if (tg3_flag(tp, MDIOBUS_INITED) &&
1492 tg3_asic_rev(tp) == ASIC_REV_5785)
1493 tg3_mdio_config_5785(tp);
1496 static int tg3_mdio_init(struct tg3 *tp)
1500 struct phy_device *phydev;
1502 if (tg3_flag(tp, 5717_PLUS)) {
1505 tp->phy_addr = tp->pci_fn + 1;
1507 if (tg3_chip_rev_id(tp) != CHIPREV_ID_5717_A0)
1508 is_serdes = tr32(SG_DIG_STATUS) & SG_DIG_IS_SERDES;
1510 is_serdes = tr32(TG3_CPMU_PHY_STRAP) &
1511 TG3_CPMU_PHY_STRAP_IS_SERDES;
1514 } else if (tg3_flag(tp, IS_SSB_CORE) && tg3_flag(tp, ROBOSWITCH)) {
1517 addr = ssb_gige_get_phyaddr(tp->pdev);
1520 tp->phy_addr = addr;
1522 tp->phy_addr = TG3_PHY_MII_ADDR;
1526 if (!tg3_flag(tp, USE_PHYLIB) || tg3_flag(tp, MDIOBUS_INITED))
1529 tp->mdio_bus = mdiobus_alloc();
1530 if (tp->mdio_bus == NULL)
1533 tp->mdio_bus->name = "tg3 mdio bus";
1534 snprintf(tp->mdio_bus->id, MII_BUS_ID_SIZE, "%x",
1535 (tp->pdev->bus->number << 8) | tp->pdev->devfn);
1536 tp->mdio_bus->priv = tp;
1537 tp->mdio_bus->parent = &tp->pdev->dev;
1538 tp->mdio_bus->read = &tg3_mdio_read;
1539 tp->mdio_bus->write = &tg3_mdio_write;
1540 tp->mdio_bus->phy_mask = ~(1 << tp->phy_addr);
1541 tp->mdio_bus->irq = &tp->mdio_irq[0];
1543 for (i = 0; i < PHY_MAX_ADDR; i++)
1544 tp->mdio_bus->irq[i] = PHY_POLL;
1546 /* The bus registration will look for all the PHYs on the mdio bus.
1547 * Unfortunately, it does not ensure the PHY is powered up before
1548 * accessing the PHY ID registers. A chip reset is the
1549 * quickest way to bring the device back to an operational state..
1551 if (tg3_readphy(tp, MII_BMCR, ®) || (reg & BMCR_PDOWN))
1554 i = mdiobus_register(tp->mdio_bus);
1556 dev_warn(&tp->pdev->dev, "mdiobus_reg failed (0x%x)\n", i);
1557 mdiobus_free(tp->mdio_bus);
1561 phydev = tp->mdio_bus->phy_map[tp->phy_addr];
1563 if (!phydev || !phydev->drv) {
1564 dev_warn(&tp->pdev->dev, "No PHY devices\n");
1565 mdiobus_unregister(tp->mdio_bus);
1566 mdiobus_free(tp->mdio_bus);
1570 switch (phydev->drv->phy_id & phydev->drv->phy_id_mask) {
1571 case PHY_ID_BCM57780:
1572 phydev->interface = PHY_INTERFACE_MODE_GMII;
1573 phydev->dev_flags |= PHY_BRCM_AUTO_PWRDWN_ENABLE;
1575 case PHY_ID_BCM50610:
1576 case PHY_ID_BCM50610M:
1577 phydev->dev_flags |= PHY_BRCM_CLEAR_RGMII_MODE |
1578 PHY_BRCM_RX_REFCLK_UNUSED |
1579 PHY_BRCM_DIS_TXCRXC_NOENRGY |
1580 PHY_BRCM_AUTO_PWRDWN_ENABLE;
1581 if (tg3_flag(tp, RGMII_INBAND_DISABLE))
1582 phydev->dev_flags |= PHY_BRCM_STD_IBND_DISABLE;
1583 if (tg3_flag(tp, RGMII_EXT_IBND_RX_EN))
1584 phydev->dev_flags |= PHY_BRCM_EXT_IBND_RX_ENABLE;
1585 if (tg3_flag(tp, RGMII_EXT_IBND_TX_EN))
1586 phydev->dev_flags |= PHY_BRCM_EXT_IBND_TX_ENABLE;
1588 case PHY_ID_RTL8211C:
1589 phydev->interface = PHY_INTERFACE_MODE_RGMII;
1591 case PHY_ID_RTL8201E:
1592 case PHY_ID_BCMAC131:
1593 phydev->interface = PHY_INTERFACE_MODE_MII;
1594 phydev->dev_flags |= PHY_BRCM_AUTO_PWRDWN_ENABLE;
1595 tp->phy_flags |= TG3_PHYFLG_IS_FET;
1599 tg3_flag_set(tp, MDIOBUS_INITED);
1601 if (tg3_asic_rev(tp) == ASIC_REV_5785)
1602 tg3_mdio_config_5785(tp);
1607 static void tg3_mdio_fini(struct tg3 *tp)
1609 if (tg3_flag(tp, MDIOBUS_INITED)) {
1610 tg3_flag_clear(tp, MDIOBUS_INITED);
1611 mdiobus_unregister(tp->mdio_bus);
1612 mdiobus_free(tp->mdio_bus);
1616 /* tp->lock is held. */
1617 static inline void tg3_generate_fw_event(struct tg3 *tp)
1621 val = tr32(GRC_RX_CPU_EVENT);
1622 val |= GRC_RX_CPU_DRIVER_EVENT;
1623 tw32_f(GRC_RX_CPU_EVENT, val);
1625 tp->last_event_jiffies = jiffies;
1628 #define TG3_FW_EVENT_TIMEOUT_USEC 2500
1630 /* tp->lock is held. */
1631 static void tg3_wait_for_event_ack(struct tg3 *tp)
1634 unsigned int delay_cnt;
1637 /* If enough time has passed, no wait is necessary. */
1638 time_remain = (long)(tp->last_event_jiffies + 1 +
1639 usecs_to_jiffies(TG3_FW_EVENT_TIMEOUT_USEC)) -
1641 if (time_remain < 0)
1644 /* Check if we can shorten the wait time. */
1645 delay_cnt = jiffies_to_usecs(time_remain);
1646 if (delay_cnt > TG3_FW_EVENT_TIMEOUT_USEC)
1647 delay_cnt = TG3_FW_EVENT_TIMEOUT_USEC;
1648 delay_cnt = (delay_cnt >> 3) + 1;
1650 for (i = 0; i < delay_cnt; i++) {
1651 if (!(tr32(GRC_RX_CPU_EVENT) & GRC_RX_CPU_DRIVER_EVENT))
1653 if (pci_channel_offline(tp->pdev))
1660 /* tp->lock is held. */
1661 static void tg3_phy_gather_ump_data(struct tg3 *tp, u32 *data)
1666 if (!tg3_readphy(tp, MII_BMCR, ®))
1668 if (!tg3_readphy(tp, MII_BMSR, ®))
1669 val |= (reg & 0xffff);
1673 if (!tg3_readphy(tp, MII_ADVERTISE, ®))
1675 if (!tg3_readphy(tp, MII_LPA, ®))
1676 val |= (reg & 0xffff);
1680 if (!(tp->phy_flags & TG3_PHYFLG_MII_SERDES)) {
1681 if (!tg3_readphy(tp, MII_CTRL1000, ®))
1683 if (!tg3_readphy(tp, MII_STAT1000, ®))
1684 val |= (reg & 0xffff);
1688 if (!tg3_readphy(tp, MII_PHYADDR, ®))
1695 /* tp->lock is held. */
1696 static void tg3_ump_link_report(struct tg3 *tp)
1700 if (!tg3_flag(tp, 5780_CLASS) || !tg3_flag(tp, ENABLE_ASF))
1703 tg3_phy_gather_ump_data(tp, data);
1705 tg3_wait_for_event_ack(tp);
1707 tg3_write_mem(tp, NIC_SRAM_FW_CMD_MBOX, FWCMD_NICDRV_LINK_UPDATE);
1708 tg3_write_mem(tp, NIC_SRAM_FW_CMD_LEN_MBOX, 14);
1709 tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX + 0x0, data[0]);
1710 tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX + 0x4, data[1]);
1711 tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX + 0x8, data[2]);
1712 tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX + 0xc, data[3]);
1714 tg3_generate_fw_event(tp);
1717 /* tp->lock is held. */
1718 static void tg3_stop_fw(struct tg3 *tp)
1720 if (tg3_flag(tp, ENABLE_ASF) && !tg3_flag(tp, ENABLE_APE)) {
1721 /* Wait for RX cpu to ACK the previous event. */
1722 tg3_wait_for_event_ack(tp);
1724 tg3_write_mem(tp, NIC_SRAM_FW_CMD_MBOX, FWCMD_NICDRV_PAUSE_FW);
1726 tg3_generate_fw_event(tp);
1728 /* Wait for RX cpu to ACK this event. */
1729 tg3_wait_for_event_ack(tp);
1733 /* tp->lock is held. */
1734 static void tg3_write_sig_pre_reset(struct tg3 *tp, int kind)
1736 tg3_write_mem(tp, NIC_SRAM_FIRMWARE_MBOX,
1737 NIC_SRAM_FIRMWARE_MBOX_MAGIC1);
1739 if (tg3_flag(tp, ASF_NEW_HANDSHAKE)) {
1741 case RESET_KIND_INIT:
1742 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
1746 case RESET_KIND_SHUTDOWN:
1747 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
1751 case RESET_KIND_SUSPEND:
1752 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
1762 /* tp->lock is held. */
1763 static void tg3_write_sig_post_reset(struct tg3 *tp, int kind)
1765 if (tg3_flag(tp, ASF_NEW_HANDSHAKE)) {
1767 case RESET_KIND_INIT:
1768 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
1769 DRV_STATE_START_DONE);
1772 case RESET_KIND_SHUTDOWN:
1773 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
1774 DRV_STATE_UNLOAD_DONE);
1783 /* tp->lock is held. */
1784 static void tg3_write_sig_legacy(struct tg3 *tp, int kind)
1786 if (tg3_flag(tp, ENABLE_ASF)) {
1788 case RESET_KIND_INIT:
1789 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
1793 case RESET_KIND_SHUTDOWN:
1794 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
1798 case RESET_KIND_SUSPEND:
1799 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
1809 static int tg3_poll_fw(struct tg3 *tp)
1814 if (tg3_flag(tp, NO_FWARE_REPORTED))
1817 if (tg3_flag(tp, IS_SSB_CORE)) {
1818 /* We don't use firmware. */
1822 if (tg3_asic_rev(tp) == ASIC_REV_5906) {
1823 /* Wait up to 20ms for init done. */
1824 for (i = 0; i < 200; i++) {
1825 if (tr32(VCPU_STATUS) & VCPU_STATUS_INIT_DONE)
1827 if (pci_channel_offline(tp->pdev))
1835 /* Wait for firmware initialization to complete. */
1836 for (i = 0; i < 100000; i++) {
1837 tg3_read_mem(tp, NIC_SRAM_FIRMWARE_MBOX, &val);
1838 if (val == ~NIC_SRAM_FIRMWARE_MBOX_MAGIC1)
1840 if (pci_channel_offline(tp->pdev)) {
1841 if (!tg3_flag(tp, NO_FWARE_REPORTED)) {
1842 tg3_flag_set(tp, NO_FWARE_REPORTED);
1843 netdev_info(tp->dev, "No firmware running\n");
1852 /* Chip might not be fitted with firmware. Some Sun onboard
1853 * parts are configured like that. So don't signal the timeout
1854 * of the above loop as an error, but do report the lack of
1855 * running firmware once.
1857 if (i >= 100000 && !tg3_flag(tp, NO_FWARE_REPORTED)) {
1858 tg3_flag_set(tp, NO_FWARE_REPORTED);
1860 netdev_info(tp->dev, "No firmware running\n");
1863 if (tg3_chip_rev_id(tp) == CHIPREV_ID_57765_A0) {
1864 /* The 57765 A0 needs a little more
1865 * time to do some important work.
1873 static void tg3_link_report(struct tg3 *tp)
1875 if (!netif_carrier_ok(tp->dev)) {
1876 netif_info(tp, link, tp->dev, "Link is down\n");
1877 tg3_ump_link_report(tp);
1878 } else if (netif_msg_link(tp)) {
1879 netdev_info(tp->dev, "Link is up at %d Mbps, %s duplex\n",
1880 (tp->link_config.active_speed == SPEED_1000 ?
1882 (tp->link_config.active_speed == SPEED_100 ?
1884 (tp->link_config.active_duplex == DUPLEX_FULL ?
1887 netdev_info(tp->dev, "Flow control is %s for TX and %s for RX\n",
1888 (tp->link_config.active_flowctrl & FLOW_CTRL_TX) ?
1890 (tp->link_config.active_flowctrl & FLOW_CTRL_RX) ?
1893 if (tp->phy_flags & TG3_PHYFLG_EEE_CAP)
1894 netdev_info(tp->dev, "EEE is %s\n",
1895 tp->setlpicnt ? "enabled" : "disabled");
1897 tg3_ump_link_report(tp);
1900 tp->link_up = netif_carrier_ok(tp->dev);
1903 static u32 tg3_decode_flowctrl_1000T(u32 adv)
1907 if (adv & ADVERTISE_PAUSE_CAP) {
1908 flowctrl |= FLOW_CTRL_RX;
1909 if (!(adv & ADVERTISE_PAUSE_ASYM))
1910 flowctrl |= FLOW_CTRL_TX;
1911 } else if (adv & ADVERTISE_PAUSE_ASYM)
1912 flowctrl |= FLOW_CTRL_TX;
1917 static u16 tg3_advert_flowctrl_1000X(u8 flow_ctrl)
1921 if ((flow_ctrl & FLOW_CTRL_TX) && (flow_ctrl & FLOW_CTRL_RX))
1922 miireg = ADVERTISE_1000XPAUSE;
1923 else if (flow_ctrl & FLOW_CTRL_TX)
1924 miireg = ADVERTISE_1000XPSE_ASYM;
1925 else if (flow_ctrl & FLOW_CTRL_RX)
1926 miireg = ADVERTISE_1000XPAUSE | ADVERTISE_1000XPSE_ASYM;
1933 static u32 tg3_decode_flowctrl_1000X(u32 adv)
1937 if (adv & ADVERTISE_1000XPAUSE) {
1938 flowctrl |= FLOW_CTRL_RX;
1939 if (!(adv & ADVERTISE_1000XPSE_ASYM))
1940 flowctrl |= FLOW_CTRL_TX;
1941 } else if (adv & ADVERTISE_1000XPSE_ASYM)
1942 flowctrl |= FLOW_CTRL_TX;
1947 static u8 tg3_resolve_flowctrl_1000X(u16 lcladv, u16 rmtadv)
1951 if (lcladv & rmtadv & ADVERTISE_1000XPAUSE) {
1952 cap = FLOW_CTRL_TX | FLOW_CTRL_RX;
1953 } else if (lcladv & rmtadv & ADVERTISE_1000XPSE_ASYM) {
1954 if (lcladv & ADVERTISE_1000XPAUSE)
1956 if (rmtadv & ADVERTISE_1000XPAUSE)
1963 static void tg3_setup_flow_control(struct tg3 *tp, u32 lcladv, u32 rmtadv)
1967 u32 old_rx_mode = tp->rx_mode;
1968 u32 old_tx_mode = tp->tx_mode;
1970 if (tg3_flag(tp, USE_PHYLIB))
1971 autoneg = tp->mdio_bus->phy_map[tp->phy_addr]->autoneg;
1973 autoneg = tp->link_config.autoneg;
1975 if (autoneg == AUTONEG_ENABLE && tg3_flag(tp, PAUSE_AUTONEG)) {
1976 if (tp->phy_flags & TG3_PHYFLG_ANY_SERDES)
1977 flowctrl = tg3_resolve_flowctrl_1000X(lcladv, rmtadv);
1979 flowctrl = mii_resolve_flowctrl_fdx(lcladv, rmtadv);
1981 flowctrl = tp->link_config.flowctrl;
1983 tp->link_config.active_flowctrl = flowctrl;
1985 if (flowctrl & FLOW_CTRL_RX)
1986 tp->rx_mode |= RX_MODE_FLOW_CTRL_ENABLE;
1988 tp->rx_mode &= ~RX_MODE_FLOW_CTRL_ENABLE;
1990 if (old_rx_mode != tp->rx_mode)
1991 tw32_f(MAC_RX_MODE, tp->rx_mode);
1993 if (flowctrl & FLOW_CTRL_TX)
1994 tp->tx_mode |= TX_MODE_FLOW_CTRL_ENABLE;
1996 tp->tx_mode &= ~TX_MODE_FLOW_CTRL_ENABLE;
1998 if (old_tx_mode != tp->tx_mode)
1999 tw32_f(MAC_TX_MODE, tp->tx_mode);
2002 static void tg3_adjust_link(struct net_device *dev)
2004 u8 oldflowctrl, linkmesg = 0;
2005 u32 mac_mode, lcl_adv, rmt_adv;
2006 struct tg3 *tp = netdev_priv(dev);
2007 struct phy_device *phydev = tp->mdio_bus->phy_map[tp->phy_addr];
2009 spin_lock_bh(&tp->lock);
2011 mac_mode = tp->mac_mode & ~(MAC_MODE_PORT_MODE_MASK |
2012 MAC_MODE_HALF_DUPLEX);
2014 oldflowctrl = tp->link_config.active_flowctrl;
2020 if (phydev->speed == SPEED_100 || phydev->speed == SPEED_10)
2021 mac_mode |= MAC_MODE_PORT_MODE_MII;
2022 else if (phydev->speed == SPEED_1000 ||
2023 tg3_asic_rev(tp) != ASIC_REV_5785)
2024 mac_mode |= MAC_MODE_PORT_MODE_GMII;
2026 mac_mode |= MAC_MODE_PORT_MODE_MII;
2028 if (phydev->duplex == DUPLEX_HALF)
2029 mac_mode |= MAC_MODE_HALF_DUPLEX;
2031 lcl_adv = mii_advertise_flowctrl(
2032 tp->link_config.flowctrl);
2035 rmt_adv = LPA_PAUSE_CAP;
2036 if (phydev->asym_pause)
2037 rmt_adv |= LPA_PAUSE_ASYM;
2040 tg3_setup_flow_control(tp, lcl_adv, rmt_adv);
2042 mac_mode |= MAC_MODE_PORT_MODE_GMII;
2044 if (mac_mode != tp->mac_mode) {
2045 tp->mac_mode = mac_mode;
2046 tw32_f(MAC_MODE, tp->mac_mode);
2050 if (tg3_asic_rev(tp) == ASIC_REV_5785) {
2051 if (phydev->speed == SPEED_10)
2053 MAC_MI_STAT_10MBPS_MODE |
2054 MAC_MI_STAT_LNKSTAT_ATTN_ENAB);
2056 tw32(MAC_MI_STAT, MAC_MI_STAT_LNKSTAT_ATTN_ENAB);
2059 if (phydev->speed == SPEED_1000 && phydev->duplex == DUPLEX_HALF)
2060 tw32(MAC_TX_LENGTHS,
2061 ((2 << TX_LENGTHS_IPG_CRS_SHIFT) |
2062 (6 << TX_LENGTHS_IPG_SHIFT) |
2063 (0xff << TX_LENGTHS_SLOT_TIME_SHIFT)));
2065 tw32(MAC_TX_LENGTHS,
2066 ((2 << TX_LENGTHS_IPG_CRS_SHIFT) |
2067 (6 << TX_LENGTHS_IPG_SHIFT) |
2068 (32 << TX_LENGTHS_SLOT_TIME_SHIFT)));
2070 if (phydev->link != tp->old_link ||
2071 phydev->speed != tp->link_config.active_speed ||
2072 phydev->duplex != tp->link_config.active_duplex ||
2073 oldflowctrl != tp->link_config.active_flowctrl)
2076 tp->old_link = phydev->link;
2077 tp->link_config.active_speed = phydev->speed;
2078 tp->link_config.active_duplex = phydev->duplex;
2080 spin_unlock_bh(&tp->lock);
2083 tg3_link_report(tp);
2086 static int tg3_phy_init(struct tg3 *tp)
2088 struct phy_device *phydev;
2090 if (tp->phy_flags & TG3_PHYFLG_IS_CONNECTED)
2093 /* Bring the PHY back to a known state. */
2096 phydev = tp->mdio_bus->phy_map[tp->phy_addr];
2098 /* Attach the MAC to the PHY. */
2099 phydev = phy_connect(tp->dev, dev_name(&phydev->dev),
2100 tg3_adjust_link, phydev->interface);
2101 if (IS_ERR(phydev)) {
2102 dev_err(&tp->pdev->dev, "Could not attach to PHY\n");
2103 return PTR_ERR(phydev);
2106 /* Mask with MAC supported features. */
2107 switch (phydev->interface) {
2108 case PHY_INTERFACE_MODE_GMII:
2109 case PHY_INTERFACE_MODE_RGMII:
2110 if (!(tp->phy_flags & TG3_PHYFLG_10_100_ONLY)) {
2111 phydev->supported &= (PHY_GBIT_FEATURES |
2113 SUPPORTED_Asym_Pause);
2117 case PHY_INTERFACE_MODE_MII:
2118 phydev->supported &= (PHY_BASIC_FEATURES |
2120 SUPPORTED_Asym_Pause);
2123 phy_disconnect(tp->mdio_bus->phy_map[tp->phy_addr]);
2127 tp->phy_flags |= TG3_PHYFLG_IS_CONNECTED;
2129 phydev->advertising = phydev->supported;
2134 static void tg3_phy_start(struct tg3 *tp)
2136 struct phy_device *phydev;
2138 if (!(tp->phy_flags & TG3_PHYFLG_IS_CONNECTED))
2141 phydev = tp->mdio_bus->phy_map[tp->phy_addr];
2143 if (tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER) {
2144 tp->phy_flags &= ~TG3_PHYFLG_IS_LOW_POWER;
2145 phydev->speed = tp->link_config.speed;
2146 phydev->duplex = tp->link_config.duplex;
2147 phydev->autoneg = tp->link_config.autoneg;
2148 phydev->advertising = tp->link_config.advertising;
2153 phy_start_aneg(phydev);
2156 static void tg3_phy_stop(struct tg3 *tp)
2158 if (!(tp->phy_flags & TG3_PHYFLG_IS_CONNECTED))
2161 phy_stop(tp->mdio_bus->phy_map[tp->phy_addr]);
2164 static void tg3_phy_fini(struct tg3 *tp)
2166 if (tp->phy_flags & TG3_PHYFLG_IS_CONNECTED) {
2167 phy_disconnect(tp->mdio_bus->phy_map[tp->phy_addr]);
2168 tp->phy_flags &= ~TG3_PHYFLG_IS_CONNECTED;
2172 static int tg3_phy_set_extloopbk(struct tg3 *tp)
2177 if (tp->phy_flags & TG3_PHYFLG_IS_FET)
2180 if ((tp->phy_id & TG3_PHY_ID_MASK) == TG3_PHY_ID_BCM5401) {
2181 /* Cannot do read-modify-write on 5401 */
2182 err = tg3_phy_auxctl_write(tp,
2183 MII_TG3_AUXCTL_SHDWSEL_AUXCTL,
2184 MII_TG3_AUXCTL_ACTL_EXTLOOPBK |
2189 err = tg3_phy_auxctl_read(tp,
2190 MII_TG3_AUXCTL_SHDWSEL_AUXCTL, &val);
2194 val |= MII_TG3_AUXCTL_ACTL_EXTLOOPBK;
2195 err = tg3_phy_auxctl_write(tp,
2196 MII_TG3_AUXCTL_SHDWSEL_AUXCTL, val);
2202 static void tg3_phy_fet_toggle_apd(struct tg3 *tp, bool enable)
2206 if (!tg3_readphy(tp, MII_TG3_FET_TEST, &phytest)) {
2209 tg3_writephy(tp, MII_TG3_FET_TEST,
2210 phytest | MII_TG3_FET_SHADOW_EN);
2211 if (!tg3_readphy(tp, MII_TG3_FET_SHDW_AUXSTAT2, &phy)) {
2213 phy |= MII_TG3_FET_SHDW_AUXSTAT2_APD;
2215 phy &= ~MII_TG3_FET_SHDW_AUXSTAT2_APD;
2216 tg3_writephy(tp, MII_TG3_FET_SHDW_AUXSTAT2, phy);
2218 tg3_writephy(tp, MII_TG3_FET_TEST, phytest);
2222 static void tg3_phy_toggle_apd(struct tg3 *tp, bool enable)
2226 if (!tg3_flag(tp, 5705_PLUS) ||
2227 (tg3_flag(tp, 5717_PLUS) &&
2228 (tp->phy_flags & TG3_PHYFLG_MII_SERDES)))
2231 if (tp->phy_flags & TG3_PHYFLG_IS_FET) {
2232 tg3_phy_fet_toggle_apd(tp, enable);
2236 reg = MII_TG3_MISC_SHDW_SCR5_LPED |
2237 MII_TG3_MISC_SHDW_SCR5_DLPTLM |
2238 MII_TG3_MISC_SHDW_SCR5_SDTL |
2239 MII_TG3_MISC_SHDW_SCR5_C125OE;
2240 if (tg3_asic_rev(tp) != ASIC_REV_5784 || !enable)
2241 reg |= MII_TG3_MISC_SHDW_SCR5_DLLAPD;
2243 tg3_phy_shdw_write(tp, MII_TG3_MISC_SHDW_SCR5_SEL, reg);
2246 reg = MII_TG3_MISC_SHDW_APD_WKTM_84MS;
2248 reg |= MII_TG3_MISC_SHDW_APD_ENABLE;
2250 tg3_phy_shdw_write(tp, MII_TG3_MISC_SHDW_APD_SEL, reg);
2253 static void tg3_phy_toggle_automdix(struct tg3 *tp, bool enable)
2257 if (!tg3_flag(tp, 5705_PLUS) ||
2258 (tp->phy_flags & TG3_PHYFLG_ANY_SERDES))
2261 if (tp->phy_flags & TG3_PHYFLG_IS_FET) {
2264 if (!tg3_readphy(tp, MII_TG3_FET_TEST, &ephy)) {
2265 u32 reg = MII_TG3_FET_SHDW_MISCCTRL;
2267 tg3_writephy(tp, MII_TG3_FET_TEST,
2268 ephy | MII_TG3_FET_SHADOW_EN);
2269 if (!tg3_readphy(tp, reg, &phy)) {
2271 phy |= MII_TG3_FET_SHDW_MISCCTRL_MDIX;
2273 phy &= ~MII_TG3_FET_SHDW_MISCCTRL_MDIX;
2274 tg3_writephy(tp, reg, phy);
2276 tg3_writephy(tp, MII_TG3_FET_TEST, ephy);
2281 ret = tg3_phy_auxctl_read(tp,
2282 MII_TG3_AUXCTL_SHDWSEL_MISC, &phy);
2285 phy |= MII_TG3_AUXCTL_MISC_FORCE_AMDIX;
2287 phy &= ~MII_TG3_AUXCTL_MISC_FORCE_AMDIX;
2288 tg3_phy_auxctl_write(tp,
2289 MII_TG3_AUXCTL_SHDWSEL_MISC, phy);
2294 static void tg3_phy_set_wirespeed(struct tg3 *tp)
2299 if (tp->phy_flags & TG3_PHYFLG_NO_ETH_WIRE_SPEED)
2302 ret = tg3_phy_auxctl_read(tp, MII_TG3_AUXCTL_SHDWSEL_MISC, &val);
2304 tg3_phy_auxctl_write(tp, MII_TG3_AUXCTL_SHDWSEL_MISC,
2305 val | MII_TG3_AUXCTL_MISC_WIRESPD_EN);
2308 static void tg3_phy_apply_otp(struct tg3 *tp)
2317 if (tg3_phy_toggle_auxctl_smdsp(tp, true))
2320 phy = ((otp & TG3_OTP_AGCTGT_MASK) >> TG3_OTP_AGCTGT_SHIFT);
2321 phy |= MII_TG3_DSP_TAP1_AGCTGT_DFLT;
2322 tg3_phydsp_write(tp, MII_TG3_DSP_TAP1, phy);
2324 phy = ((otp & TG3_OTP_HPFFLTR_MASK) >> TG3_OTP_HPFFLTR_SHIFT) |
2325 ((otp & TG3_OTP_HPFOVER_MASK) >> TG3_OTP_HPFOVER_SHIFT);
2326 tg3_phydsp_write(tp, MII_TG3_DSP_AADJ1CH0, phy);
2328 phy = ((otp & TG3_OTP_LPFDIS_MASK) >> TG3_OTP_LPFDIS_SHIFT);
2329 phy |= MII_TG3_DSP_AADJ1CH3_ADCCKADJ;
2330 tg3_phydsp_write(tp, MII_TG3_DSP_AADJ1CH3, phy);
2332 phy = ((otp & TG3_OTP_VDAC_MASK) >> TG3_OTP_VDAC_SHIFT);
2333 tg3_phydsp_write(tp, MII_TG3_DSP_EXP75, phy);
2335 phy = ((otp & TG3_OTP_10BTAMP_MASK) >> TG3_OTP_10BTAMP_SHIFT);
2336 tg3_phydsp_write(tp, MII_TG3_DSP_EXP96, phy);
2338 phy = ((otp & TG3_OTP_ROFF_MASK) >> TG3_OTP_ROFF_SHIFT) |
2339 ((otp & TG3_OTP_RCOFF_MASK) >> TG3_OTP_RCOFF_SHIFT);
2340 tg3_phydsp_write(tp, MII_TG3_DSP_EXP97, phy);
2342 tg3_phy_toggle_auxctl_smdsp(tp, false);
2345 static void tg3_eee_pull_config(struct tg3 *tp, struct ethtool_eee *eee)
2348 struct ethtool_eee *dest = &tp->eee;
2350 if (!(tp->phy_flags & TG3_PHYFLG_EEE_CAP))
2356 if (tg3_phy_cl45_read(tp, MDIO_MMD_AN, TG3_CL45_D7_EEERES_STAT, &val))
2359 /* Pull eee_active */
2360 if (val == TG3_CL45_D7_EEERES_STAT_LP_1000T ||
2361 val == TG3_CL45_D7_EEERES_STAT_LP_100TX) {
2362 dest->eee_active = 1;
2364 dest->eee_active = 0;
2366 /* Pull lp advertised settings */
2367 if (tg3_phy_cl45_read(tp, MDIO_MMD_AN, MDIO_AN_EEE_LPABLE, &val))
2369 dest->lp_advertised = mmd_eee_adv_to_ethtool_adv_t(val);
2371 /* Pull advertised and eee_enabled settings */
2372 if (tg3_phy_cl45_read(tp, MDIO_MMD_AN, MDIO_AN_EEE_ADV, &val))
2374 dest->eee_enabled = !!val;
2375 dest->advertised = mmd_eee_adv_to_ethtool_adv_t(val);
2377 /* Pull tx_lpi_enabled */
2378 val = tr32(TG3_CPMU_EEE_MODE);
2379 dest->tx_lpi_enabled = !!(val & TG3_CPMU_EEEMD_LPI_IN_TX);
2381 /* Pull lpi timer value */
2382 dest->tx_lpi_timer = tr32(TG3_CPMU_EEE_DBTMR1) & 0xffff;
2385 static void tg3_phy_eee_adjust(struct tg3 *tp, bool current_link_up)
2389 if (!(tp->phy_flags & TG3_PHYFLG_EEE_CAP))
2394 if (tp->link_config.autoneg == AUTONEG_ENABLE &&
2396 tp->link_config.active_duplex == DUPLEX_FULL &&
2397 (tp->link_config.active_speed == SPEED_100 ||
2398 tp->link_config.active_speed == SPEED_1000)) {
2401 if (tp->link_config.active_speed == SPEED_1000)
2402 eeectl = TG3_CPMU_EEE_CTRL_EXIT_16_5_US;
2404 eeectl = TG3_CPMU_EEE_CTRL_EXIT_36_US;
2406 tw32(TG3_CPMU_EEE_CTRL, eeectl);
2408 tg3_eee_pull_config(tp, NULL);
2409 if (tp->eee.eee_active)
2413 if (!tp->setlpicnt) {
2414 if (current_link_up &&
2415 !tg3_phy_toggle_auxctl_smdsp(tp, true)) {
2416 tg3_phydsp_write(tp, MII_TG3_DSP_TAP26, 0x0000);
2417 tg3_phy_toggle_auxctl_smdsp(tp, false);
2420 val = tr32(TG3_CPMU_EEE_MODE);
2421 tw32(TG3_CPMU_EEE_MODE, val & ~TG3_CPMU_EEEMD_LPI_ENABLE);
2425 static void tg3_phy_eee_enable(struct tg3 *tp)
2429 if (tp->link_config.active_speed == SPEED_1000 &&
2430 (tg3_asic_rev(tp) == ASIC_REV_5717 ||
2431 tg3_asic_rev(tp) == ASIC_REV_5719 ||
2432 tg3_flag(tp, 57765_CLASS)) &&
2433 !tg3_phy_toggle_auxctl_smdsp(tp, true)) {
2434 val = MII_TG3_DSP_TAP26_ALNOKO |
2435 MII_TG3_DSP_TAP26_RMRXSTO;
2436 tg3_phydsp_write(tp, MII_TG3_DSP_TAP26, val);
2437 tg3_phy_toggle_auxctl_smdsp(tp, false);
2440 val = tr32(TG3_CPMU_EEE_MODE);
2441 tw32(TG3_CPMU_EEE_MODE, val | TG3_CPMU_EEEMD_LPI_ENABLE);
2444 static int tg3_wait_macro_done(struct tg3 *tp)
2451 if (!tg3_readphy(tp, MII_TG3_DSP_CONTROL, &tmp32)) {
2452 if ((tmp32 & 0x1000) == 0)
2462 static int tg3_phy_write_and_check_testpat(struct tg3 *tp, int *resetp)
2464 static const u32 test_pat[4][6] = {
2465 { 0x00005555, 0x00000005, 0x00002aaa, 0x0000000a, 0x00003456, 0x00000003 },
2466 { 0x00002aaa, 0x0000000a, 0x00003333, 0x00000003, 0x0000789a, 0x00000005 },
2467 { 0x00005a5a, 0x00000005, 0x00002a6a, 0x0000000a, 0x00001bcd, 0x00000003 },
2468 { 0x00002a5a, 0x0000000a, 0x000033c3, 0x00000003, 0x00002ef1, 0x00000005 }
2472 for (chan = 0; chan < 4; chan++) {
2475 tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
2476 (chan * 0x2000) | 0x0200);
2477 tg3_writephy(tp, MII_TG3_DSP_CONTROL, 0x0002);
2479 for (i = 0; i < 6; i++)
2480 tg3_writephy(tp, MII_TG3_DSP_RW_PORT,
2483 tg3_writephy(tp, MII_TG3_DSP_CONTROL, 0x0202);
2484 if (tg3_wait_macro_done(tp)) {
2489 tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
2490 (chan * 0x2000) | 0x0200);
2491 tg3_writephy(tp, MII_TG3_DSP_CONTROL, 0x0082);
2492 if (tg3_wait_macro_done(tp)) {
2497 tg3_writephy(tp, MII_TG3_DSP_CONTROL, 0x0802);
2498 if (tg3_wait_macro_done(tp)) {
2503 for (i = 0; i < 6; i += 2) {
2506 if (tg3_readphy(tp, MII_TG3_DSP_RW_PORT, &low) ||
2507 tg3_readphy(tp, MII_TG3_DSP_RW_PORT, &high) ||
2508 tg3_wait_macro_done(tp)) {
2514 if (low != test_pat[chan][i] ||
2515 high != test_pat[chan][i+1]) {
2516 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x000b);
2517 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x4001);
2518 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x4005);
2528 static int tg3_phy_reset_chanpat(struct tg3 *tp)
2532 for (chan = 0; chan < 4; chan++) {
2535 tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
2536 (chan * 0x2000) | 0x0200);
2537 tg3_writephy(tp, MII_TG3_DSP_CONTROL, 0x0002);
2538 for (i = 0; i < 6; i++)
2539 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x000);
2540 tg3_writephy(tp, MII_TG3_DSP_CONTROL, 0x0202);
2541 if (tg3_wait_macro_done(tp))
2548 static int tg3_phy_reset_5703_4_5(struct tg3 *tp)
2550 u32 reg32, phy9_orig;
2551 int retries, do_phy_reset, err;
2557 err = tg3_bmcr_reset(tp);
2563 /* Disable transmitter and interrupt. */
2564 if (tg3_readphy(tp, MII_TG3_EXT_CTRL, ®32))
2568 tg3_writephy(tp, MII_TG3_EXT_CTRL, reg32);
2570 /* Set full-duplex, 1000 mbps. */
2571 tg3_writephy(tp, MII_BMCR,
2572 BMCR_FULLDPLX | BMCR_SPEED1000);
2574 /* Set to master mode. */
2575 if (tg3_readphy(tp, MII_CTRL1000, &phy9_orig))
2578 tg3_writephy(tp, MII_CTRL1000,
2579 CTL1000_AS_MASTER | CTL1000_ENABLE_MASTER);
2581 err = tg3_phy_toggle_auxctl_smdsp(tp, true);
2585 /* Block the PHY control access. */
2586 tg3_phydsp_write(tp, 0x8005, 0x0800);
2588 err = tg3_phy_write_and_check_testpat(tp, &do_phy_reset);
2591 } while (--retries);
2593 err = tg3_phy_reset_chanpat(tp);
2597 tg3_phydsp_write(tp, 0x8005, 0x0000);
2599 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8200);
2600 tg3_writephy(tp, MII_TG3_DSP_CONTROL, 0x0000);
2602 tg3_phy_toggle_auxctl_smdsp(tp, false);
2604 tg3_writephy(tp, MII_CTRL1000, phy9_orig);
2606 err = tg3_readphy(tp, MII_TG3_EXT_CTRL, ®32);
2611 tg3_writephy(tp, MII_TG3_EXT_CTRL, reg32);
2616 static void tg3_carrier_off(struct tg3 *tp)
2618 netif_carrier_off(tp->dev);
2619 tp->link_up = false;
2622 static void tg3_warn_mgmt_link_flap(struct tg3 *tp)
2624 if (tg3_flag(tp, ENABLE_ASF))
2625 netdev_warn(tp->dev,
2626 "Management side-band traffic will be interrupted during phy settings change\n");
2629 /* This will reset the tigon3 PHY if there is no valid
2630 * link unless the FORCE argument is non-zero.
2632 static int tg3_phy_reset(struct tg3 *tp)
2637 if (tg3_asic_rev(tp) == ASIC_REV_5906) {
2638 val = tr32(GRC_MISC_CFG);
2639 tw32_f(GRC_MISC_CFG, val & ~GRC_MISC_CFG_EPHY_IDDQ);
2642 err = tg3_readphy(tp, MII_BMSR, &val);
2643 err |= tg3_readphy(tp, MII_BMSR, &val);
2647 if (netif_running(tp->dev) && tp->link_up) {
2648 netif_carrier_off(tp->dev);
2649 tg3_link_report(tp);
2652 if (tg3_asic_rev(tp) == ASIC_REV_5703 ||
2653 tg3_asic_rev(tp) == ASIC_REV_5704 ||
2654 tg3_asic_rev(tp) == ASIC_REV_5705) {
2655 err = tg3_phy_reset_5703_4_5(tp);
2662 if (tg3_asic_rev(tp) == ASIC_REV_5784 &&
2663 tg3_chip_rev(tp) != CHIPREV_5784_AX) {
2664 cpmuctrl = tr32(TG3_CPMU_CTRL);
2665 if (cpmuctrl & CPMU_CTRL_GPHY_10MB_RXONLY)
2667 cpmuctrl & ~CPMU_CTRL_GPHY_10MB_RXONLY);
2670 err = tg3_bmcr_reset(tp);
2674 if (cpmuctrl & CPMU_CTRL_GPHY_10MB_RXONLY) {
2675 val = MII_TG3_DSP_EXP8_AEDW | MII_TG3_DSP_EXP8_REJ2MHz;
2676 tg3_phydsp_write(tp, MII_TG3_DSP_EXP8, val);
2678 tw32(TG3_CPMU_CTRL, cpmuctrl);
2681 if (tg3_chip_rev(tp) == CHIPREV_5784_AX ||
2682 tg3_chip_rev(tp) == CHIPREV_5761_AX) {
2683 val = tr32(TG3_CPMU_LSPD_1000MB_CLK);
2684 if ((val & CPMU_LSPD_1000MB_MACCLK_MASK) ==
2685 CPMU_LSPD_1000MB_MACCLK_12_5) {
2686 val &= ~CPMU_LSPD_1000MB_MACCLK_MASK;
2688 tw32_f(TG3_CPMU_LSPD_1000MB_CLK, val);
2692 if (tg3_flag(tp, 5717_PLUS) &&
2693 (tp->phy_flags & TG3_PHYFLG_MII_SERDES))
2696 tg3_phy_apply_otp(tp);
2698 if (tp->phy_flags & TG3_PHYFLG_ENABLE_APD)
2699 tg3_phy_toggle_apd(tp, true);
2701 tg3_phy_toggle_apd(tp, false);
2704 if ((tp->phy_flags & TG3_PHYFLG_ADC_BUG) &&
2705 !tg3_phy_toggle_auxctl_smdsp(tp, true)) {
2706 tg3_phydsp_write(tp, 0x201f, 0x2aaa);
2707 tg3_phydsp_write(tp, 0x000a, 0x0323);
2708 tg3_phy_toggle_auxctl_smdsp(tp, false);
2711 if (tp->phy_flags & TG3_PHYFLG_5704_A0_BUG) {
2712 tg3_writephy(tp, MII_TG3_MISC_SHDW, 0x8d68);
2713 tg3_writephy(tp, MII_TG3_MISC_SHDW, 0x8d68);
2716 if (tp->phy_flags & TG3_PHYFLG_BER_BUG) {
2717 if (!tg3_phy_toggle_auxctl_smdsp(tp, true)) {
2718 tg3_phydsp_write(tp, 0x000a, 0x310b);
2719 tg3_phydsp_write(tp, 0x201f, 0x9506);
2720 tg3_phydsp_write(tp, 0x401f, 0x14e2);
2721 tg3_phy_toggle_auxctl_smdsp(tp, false);
2723 } else if (tp->phy_flags & TG3_PHYFLG_JITTER_BUG) {
2724 if (!tg3_phy_toggle_auxctl_smdsp(tp, true)) {
2725 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x000a);
2726 if (tp->phy_flags & TG3_PHYFLG_ADJUST_TRIM) {
2727 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x110b);
2728 tg3_writephy(tp, MII_TG3_TEST1,
2729 MII_TG3_TEST1_TRIM_EN | 0x4);
2731 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x010b);
2733 tg3_phy_toggle_auxctl_smdsp(tp, false);
2737 /* Set Extended packet length bit (bit 14) on all chips that */
2738 /* support jumbo frames */
2739 if ((tp->phy_id & TG3_PHY_ID_MASK) == TG3_PHY_ID_BCM5401) {
2740 /* Cannot do read-modify-write on 5401 */
2741 tg3_phy_auxctl_write(tp, MII_TG3_AUXCTL_SHDWSEL_AUXCTL, 0x4c20);
2742 } else if (tg3_flag(tp, JUMBO_CAPABLE)) {
2743 /* Set bit 14 with read-modify-write to preserve other bits */
2744 err = tg3_phy_auxctl_read(tp,
2745 MII_TG3_AUXCTL_SHDWSEL_AUXCTL, &val);
2747 tg3_phy_auxctl_write(tp, MII_TG3_AUXCTL_SHDWSEL_AUXCTL,
2748 val | MII_TG3_AUXCTL_ACTL_EXTPKTLEN);
2751 /* Set phy register 0x10 bit 0 to high fifo elasticity to support
2752 * jumbo frames transmission.
2754 if (tg3_flag(tp, JUMBO_CAPABLE)) {
2755 if (!tg3_readphy(tp, MII_TG3_EXT_CTRL, &val))
2756 tg3_writephy(tp, MII_TG3_EXT_CTRL,
2757 val | MII_TG3_EXT_CTRL_FIFO_ELASTIC);
2760 if (tg3_asic_rev(tp) == ASIC_REV_5906) {
2761 /* adjust output voltage */
2762 tg3_writephy(tp, MII_TG3_FET_PTEST, 0x12);
2765 if (tg3_chip_rev_id(tp) == CHIPREV_ID_5762_A0)
2766 tg3_phydsp_write(tp, 0xffb, 0x4000);
2768 tg3_phy_toggle_automdix(tp, true);
2769 tg3_phy_set_wirespeed(tp);
2773 #define TG3_GPIO_MSG_DRVR_PRES 0x00000001
2774 #define TG3_GPIO_MSG_NEED_VAUX 0x00000002
2775 #define TG3_GPIO_MSG_MASK (TG3_GPIO_MSG_DRVR_PRES | \
2776 TG3_GPIO_MSG_NEED_VAUX)
2777 #define TG3_GPIO_MSG_ALL_DRVR_PRES_MASK \
2778 ((TG3_GPIO_MSG_DRVR_PRES << 0) | \
2779 (TG3_GPIO_MSG_DRVR_PRES << 4) | \
2780 (TG3_GPIO_MSG_DRVR_PRES << 8) | \
2781 (TG3_GPIO_MSG_DRVR_PRES << 12))
2783 #define TG3_GPIO_MSG_ALL_NEED_VAUX_MASK \
2784 ((TG3_GPIO_MSG_NEED_VAUX << 0) | \
2785 (TG3_GPIO_MSG_NEED_VAUX << 4) | \
2786 (TG3_GPIO_MSG_NEED_VAUX << 8) | \
2787 (TG3_GPIO_MSG_NEED_VAUX << 12))
2789 static inline u32 tg3_set_function_status(struct tg3 *tp, u32 newstat)
2793 if (tg3_asic_rev(tp) == ASIC_REV_5717 ||
2794 tg3_asic_rev(tp) == ASIC_REV_5719)
2795 status = tg3_ape_read32(tp, TG3_APE_GPIO_MSG);
2797 status = tr32(TG3_CPMU_DRV_STATUS);
2799 shift = TG3_APE_GPIO_MSG_SHIFT + 4 * tp->pci_fn;
2800 status &= ~(TG3_GPIO_MSG_MASK << shift);
2801 status |= (newstat << shift);
2803 if (tg3_asic_rev(tp) == ASIC_REV_5717 ||
2804 tg3_asic_rev(tp) == ASIC_REV_5719)
2805 tg3_ape_write32(tp, TG3_APE_GPIO_MSG, status);
2807 tw32(TG3_CPMU_DRV_STATUS, status);
2809 return status >> TG3_APE_GPIO_MSG_SHIFT;
2812 static inline int tg3_pwrsrc_switch_to_vmain(struct tg3 *tp)
2814 if (!tg3_flag(tp, IS_NIC))
2817 if (tg3_asic_rev(tp) == ASIC_REV_5717 ||
2818 tg3_asic_rev(tp) == ASIC_REV_5719 ||
2819 tg3_asic_rev(tp) == ASIC_REV_5720) {
2820 if (tg3_ape_lock(tp, TG3_APE_LOCK_GPIO))
2823 tg3_set_function_status(tp, TG3_GPIO_MSG_DRVR_PRES);
2825 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl,
2826 TG3_GRC_LCLCTL_PWRSW_DELAY);
2828 tg3_ape_unlock(tp, TG3_APE_LOCK_GPIO);
2830 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl,
2831 TG3_GRC_LCLCTL_PWRSW_DELAY);
2837 static void tg3_pwrsrc_die_with_vmain(struct tg3 *tp)
2841 if (!tg3_flag(tp, IS_NIC) ||
2842 tg3_asic_rev(tp) == ASIC_REV_5700 ||
2843 tg3_asic_rev(tp) == ASIC_REV_5701)
2846 grc_local_ctrl = tp->grc_local_ctrl | GRC_LCLCTRL_GPIO_OE1;
2848 tw32_wait_f(GRC_LOCAL_CTRL,
2849 grc_local_ctrl | GRC_LCLCTRL_GPIO_OUTPUT1,
2850 TG3_GRC_LCLCTL_PWRSW_DELAY);
2852 tw32_wait_f(GRC_LOCAL_CTRL,
2854 TG3_GRC_LCLCTL_PWRSW_DELAY);
2856 tw32_wait_f(GRC_LOCAL_CTRL,
2857 grc_local_ctrl | GRC_LCLCTRL_GPIO_OUTPUT1,
2858 TG3_GRC_LCLCTL_PWRSW_DELAY);
2861 static void tg3_pwrsrc_switch_to_vaux(struct tg3 *tp)
2863 if (!tg3_flag(tp, IS_NIC))
2866 if (tg3_asic_rev(tp) == ASIC_REV_5700 ||
2867 tg3_asic_rev(tp) == ASIC_REV_5701) {
2868 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2869 (GRC_LCLCTRL_GPIO_OE0 |
2870 GRC_LCLCTRL_GPIO_OE1 |
2871 GRC_LCLCTRL_GPIO_OE2 |
2872 GRC_LCLCTRL_GPIO_OUTPUT0 |
2873 GRC_LCLCTRL_GPIO_OUTPUT1),
2874 TG3_GRC_LCLCTL_PWRSW_DELAY);
2875 } else if (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5761 ||
2876 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5761S) {
2877 /* The 5761 non-e device swaps GPIO 0 and GPIO 2. */
2878 u32 grc_local_ctrl = GRC_LCLCTRL_GPIO_OE0 |
2879 GRC_LCLCTRL_GPIO_OE1 |
2880 GRC_LCLCTRL_GPIO_OE2 |
2881 GRC_LCLCTRL_GPIO_OUTPUT0 |
2882 GRC_LCLCTRL_GPIO_OUTPUT1 |
2884 tw32_wait_f(GRC_LOCAL_CTRL, grc_local_ctrl,
2885 TG3_GRC_LCLCTL_PWRSW_DELAY);
2887 grc_local_ctrl |= GRC_LCLCTRL_GPIO_OUTPUT2;
2888 tw32_wait_f(GRC_LOCAL_CTRL, grc_local_ctrl,
2889 TG3_GRC_LCLCTL_PWRSW_DELAY);
2891 grc_local_ctrl &= ~GRC_LCLCTRL_GPIO_OUTPUT0;
2892 tw32_wait_f(GRC_LOCAL_CTRL, grc_local_ctrl,
2893 TG3_GRC_LCLCTL_PWRSW_DELAY);
2896 u32 grc_local_ctrl = 0;
2898 /* Workaround to prevent overdrawing Amps. */
2899 if (tg3_asic_rev(tp) == ASIC_REV_5714) {
2900 grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE3;
2901 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2903 TG3_GRC_LCLCTL_PWRSW_DELAY);
2906 /* On 5753 and variants, GPIO2 cannot be used. */
2907 no_gpio2 = tp->nic_sram_data_cfg &
2908 NIC_SRAM_DATA_CFG_NO_GPIO2;
2910 grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE0 |
2911 GRC_LCLCTRL_GPIO_OE1 |
2912 GRC_LCLCTRL_GPIO_OE2 |
2913 GRC_LCLCTRL_GPIO_OUTPUT1 |
2914 GRC_LCLCTRL_GPIO_OUTPUT2;
2916 grc_local_ctrl &= ~(GRC_LCLCTRL_GPIO_OE2 |
2917 GRC_LCLCTRL_GPIO_OUTPUT2);
2919 tw32_wait_f(GRC_LOCAL_CTRL,
2920 tp->grc_local_ctrl | grc_local_ctrl,
2921 TG3_GRC_LCLCTL_PWRSW_DELAY);
2923 grc_local_ctrl |= GRC_LCLCTRL_GPIO_OUTPUT0;
2925 tw32_wait_f(GRC_LOCAL_CTRL,
2926 tp->grc_local_ctrl | grc_local_ctrl,
2927 TG3_GRC_LCLCTL_PWRSW_DELAY);
2930 grc_local_ctrl &= ~GRC_LCLCTRL_GPIO_OUTPUT2;
2931 tw32_wait_f(GRC_LOCAL_CTRL,
2932 tp->grc_local_ctrl | grc_local_ctrl,
2933 TG3_GRC_LCLCTL_PWRSW_DELAY);
2938 static void tg3_frob_aux_power_5717(struct tg3 *tp, bool wol_enable)
2942 /* Serialize power state transitions */
2943 if (tg3_ape_lock(tp, TG3_APE_LOCK_GPIO))
2946 if (tg3_flag(tp, ENABLE_ASF) || tg3_flag(tp, ENABLE_APE) || wol_enable)
2947 msg = TG3_GPIO_MSG_NEED_VAUX;
2949 msg = tg3_set_function_status(tp, msg);
2951 if (msg & TG3_GPIO_MSG_ALL_DRVR_PRES_MASK)
2954 if (msg & TG3_GPIO_MSG_ALL_NEED_VAUX_MASK)
2955 tg3_pwrsrc_switch_to_vaux(tp);
2957 tg3_pwrsrc_die_with_vmain(tp);
2960 tg3_ape_unlock(tp, TG3_APE_LOCK_GPIO);
2963 static void tg3_frob_aux_power(struct tg3 *tp, bool include_wol)
2965 bool need_vaux = false;
2967 /* The GPIOs do something completely different on 57765. */
2968 if (!tg3_flag(tp, IS_NIC) || tg3_flag(tp, 57765_CLASS))
2971 if (tg3_asic_rev(tp) == ASIC_REV_5717 ||
2972 tg3_asic_rev(tp) == ASIC_REV_5719 ||
2973 tg3_asic_rev(tp) == ASIC_REV_5720) {
2974 tg3_frob_aux_power_5717(tp, include_wol ?
2975 tg3_flag(tp, WOL_ENABLE) != 0 : 0);
2979 if (tp->pdev_peer && tp->pdev_peer != tp->pdev) {
2980 struct net_device *dev_peer;
2982 dev_peer = pci_get_drvdata(tp->pdev_peer);
2984 /* remove_one() may have been run on the peer. */
2986 struct tg3 *tp_peer = netdev_priv(dev_peer);
2988 if (tg3_flag(tp_peer, INIT_COMPLETE))
2991 if ((include_wol && tg3_flag(tp_peer, WOL_ENABLE)) ||
2992 tg3_flag(tp_peer, ENABLE_ASF))
2997 if ((include_wol && tg3_flag(tp, WOL_ENABLE)) ||
2998 tg3_flag(tp, ENABLE_ASF))
3002 tg3_pwrsrc_switch_to_vaux(tp);
3004 tg3_pwrsrc_die_with_vmain(tp);
3007 static int tg3_5700_link_polarity(struct tg3 *tp, u32 speed)
3009 if (tp->led_ctrl == LED_CTRL_MODE_PHY_2)
3011 else if ((tp->phy_id & TG3_PHY_ID_MASK) == TG3_PHY_ID_BCM5411) {
3012 if (speed != SPEED_10)
3014 } else if (speed == SPEED_10)
3020 static bool tg3_phy_power_bug(struct tg3 *tp)
3022 switch (tg3_asic_rev(tp)) {
3027 if (tp->phy_flags & TG3_PHYFLG_MII_SERDES)
3036 if ((tp->phy_flags & TG3_PHYFLG_PHY_SERDES) &&
3045 static bool tg3_phy_led_bug(struct tg3 *tp)
3047 switch (tg3_asic_rev(tp)) {
3050 if ((tp->phy_flags & TG3_PHYFLG_MII_SERDES) &&
3059 static void tg3_power_down_phy(struct tg3 *tp, bool do_low_power)
3063 if (tp->phy_flags & TG3_PHYFLG_KEEP_LINK_ON_PWRDN)
3066 if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES) {
3067 if (tg3_asic_rev(tp) == ASIC_REV_5704) {
3068 u32 sg_dig_ctrl = tr32(SG_DIG_CTRL);
3069 u32 serdes_cfg = tr32(MAC_SERDES_CFG);
3072 SG_DIG_USING_HW_AUTONEG | SG_DIG_SOFT_RESET;
3073 tw32(SG_DIG_CTRL, sg_dig_ctrl);
3074 tw32(MAC_SERDES_CFG, serdes_cfg | (1 << 15));
3079 if (tg3_asic_rev(tp) == ASIC_REV_5906) {
3081 val = tr32(GRC_MISC_CFG);
3082 tw32_f(GRC_MISC_CFG, val | GRC_MISC_CFG_EPHY_IDDQ);
3085 } else if (tp->phy_flags & TG3_PHYFLG_IS_FET) {
3087 if (!tg3_readphy(tp, MII_TG3_FET_TEST, &phytest)) {
3090 tg3_writephy(tp, MII_ADVERTISE, 0);
3091 tg3_writephy(tp, MII_BMCR,
3092 BMCR_ANENABLE | BMCR_ANRESTART);
3094 tg3_writephy(tp, MII_TG3_FET_TEST,
3095 phytest | MII_TG3_FET_SHADOW_EN);
3096 if (!tg3_readphy(tp, MII_TG3_FET_SHDW_AUXMODE4, &phy)) {
3097 phy |= MII_TG3_FET_SHDW_AUXMODE4_SBPD;
3099 MII_TG3_FET_SHDW_AUXMODE4,
3102 tg3_writephy(tp, MII_TG3_FET_TEST, phytest);
3105 } else if (do_low_power) {
3106 if (!tg3_phy_led_bug(tp))
3107 tg3_writephy(tp, MII_TG3_EXT_CTRL,
3108 MII_TG3_EXT_CTRL_FORCE_LED_OFF);
3110 val = MII_TG3_AUXCTL_PCTL_100TX_LPWR |
3111 MII_TG3_AUXCTL_PCTL_SPR_ISOLATE |
3112 MII_TG3_AUXCTL_PCTL_VREG_11V;
3113 tg3_phy_auxctl_write(tp, MII_TG3_AUXCTL_SHDWSEL_PWRCTL, val);
3116 /* The PHY should not be powered down on some chips because
3119 if (tg3_phy_power_bug(tp))
3122 if (tg3_chip_rev(tp) == CHIPREV_5784_AX ||
3123 tg3_chip_rev(tp) == CHIPREV_5761_AX) {
3124 val = tr32(TG3_CPMU_LSPD_1000MB_CLK);
3125 val &= ~CPMU_LSPD_1000MB_MACCLK_MASK;
3126 val |= CPMU_LSPD_1000MB_MACCLK_12_5;
3127 tw32_f(TG3_CPMU_LSPD_1000MB_CLK, val);
3130 tg3_writephy(tp, MII_BMCR, BMCR_PDOWN);
3133 /* tp->lock is held. */
3134 static int tg3_nvram_lock(struct tg3 *tp)
3136 if (tg3_flag(tp, NVRAM)) {
3139 if (tp->nvram_lock_cnt == 0) {
3140 tw32(NVRAM_SWARB, SWARB_REQ_SET1);
3141 for (i = 0; i < 8000; i++) {
3142 if (tr32(NVRAM_SWARB) & SWARB_GNT1)
3147 tw32(NVRAM_SWARB, SWARB_REQ_CLR1);
3151 tp->nvram_lock_cnt++;
3156 /* tp->lock is held. */
3157 static void tg3_nvram_unlock(struct tg3 *tp)
3159 if (tg3_flag(tp, NVRAM)) {
3160 if (tp->nvram_lock_cnt > 0)
3161 tp->nvram_lock_cnt--;
3162 if (tp->nvram_lock_cnt == 0)
3163 tw32_f(NVRAM_SWARB, SWARB_REQ_CLR1);
3167 /* tp->lock is held. */
3168 static void tg3_enable_nvram_access(struct tg3 *tp)
3170 if (tg3_flag(tp, 5750_PLUS) && !tg3_flag(tp, PROTECTED_NVRAM)) {
3171 u32 nvaccess = tr32(NVRAM_ACCESS);
3173 tw32(NVRAM_ACCESS, nvaccess | ACCESS_ENABLE);
3177 /* tp->lock is held. */
3178 static void tg3_disable_nvram_access(struct tg3 *tp)
3180 if (tg3_flag(tp, 5750_PLUS) && !tg3_flag(tp, PROTECTED_NVRAM)) {
3181 u32 nvaccess = tr32(NVRAM_ACCESS);
3183 tw32(NVRAM_ACCESS, nvaccess & ~ACCESS_ENABLE);
3187 static int tg3_nvram_read_using_eeprom(struct tg3 *tp,
3188 u32 offset, u32 *val)
3193 if (offset > EEPROM_ADDR_ADDR_MASK || (offset % 4) != 0)
3196 tmp = tr32(GRC_EEPROM_ADDR) & ~(EEPROM_ADDR_ADDR_MASK |
3197 EEPROM_ADDR_DEVID_MASK |
3199 tw32(GRC_EEPROM_ADDR,
3201 (0 << EEPROM_ADDR_DEVID_SHIFT) |
3202 ((offset << EEPROM_ADDR_ADDR_SHIFT) &
3203 EEPROM_ADDR_ADDR_MASK) |
3204 EEPROM_ADDR_READ | EEPROM_ADDR_START);
3206 for (i = 0; i < 1000; i++) {
3207 tmp = tr32(GRC_EEPROM_ADDR);
3209 if (tmp & EEPROM_ADDR_COMPLETE)
3213 if (!(tmp & EEPROM_ADDR_COMPLETE))
3216 tmp = tr32(GRC_EEPROM_DATA);
3219 * The data will always be opposite the native endian
3220 * format. Perform a blind byteswap to compensate.
3227 #define NVRAM_CMD_TIMEOUT 10000
3229 static int tg3_nvram_exec_cmd(struct tg3 *tp, u32 nvram_cmd)
3233 tw32(NVRAM_CMD, nvram_cmd);
3234 for (i = 0; i < NVRAM_CMD_TIMEOUT; i++) {
3236 if (tr32(NVRAM_CMD) & NVRAM_CMD_DONE) {
3242 if (i == NVRAM_CMD_TIMEOUT)
3248 static u32 tg3_nvram_phys_addr(struct tg3 *tp, u32 addr)
3250 if (tg3_flag(tp, NVRAM) &&
3251 tg3_flag(tp, NVRAM_BUFFERED) &&
3252 tg3_flag(tp, FLASH) &&
3253 !tg3_flag(tp, NO_NVRAM_ADDR_TRANS) &&
3254 (tp->nvram_jedecnum == JEDEC_ATMEL))
3256 addr = ((addr / tp->nvram_pagesize) <<
3257 ATMEL_AT45DB0X1B_PAGE_POS) +
3258 (addr % tp->nvram_pagesize);
3263 static u32 tg3_nvram_logical_addr(struct tg3 *tp, u32 addr)
3265 if (tg3_flag(tp, NVRAM) &&
3266 tg3_flag(tp, NVRAM_BUFFERED) &&
3267 tg3_flag(tp, FLASH) &&
3268 !tg3_flag(tp, NO_NVRAM_ADDR_TRANS) &&
3269 (tp->nvram_jedecnum == JEDEC_ATMEL))
3271 addr = ((addr >> ATMEL_AT45DB0X1B_PAGE_POS) *
3272 tp->nvram_pagesize) +
3273 (addr & ((1 << ATMEL_AT45DB0X1B_PAGE_POS) - 1));
3278 /* NOTE: Data read in from NVRAM is byteswapped according to
3279 * the byteswapping settings for all other register accesses.
3280 * tg3 devices are BE devices, so on a BE machine, the data
3281 * returned will be exactly as it is seen in NVRAM. On a LE
3282 * machine, the 32-bit value will be byteswapped.
3284 static int tg3_nvram_read(struct tg3 *tp, u32 offset, u32 *val)
3288 if (!tg3_flag(tp, NVRAM))
3289 return tg3_nvram_read_using_eeprom(tp, offset, val);
3291 offset = tg3_nvram_phys_addr(tp, offset);
3293 if (offset > NVRAM_ADDR_MSK)
3296 ret = tg3_nvram_lock(tp);
3300 tg3_enable_nvram_access(tp);
3302 tw32(NVRAM_ADDR, offset);
3303 ret = tg3_nvram_exec_cmd(tp, NVRAM_CMD_RD | NVRAM_CMD_GO |
3304 NVRAM_CMD_FIRST | NVRAM_CMD_LAST | NVRAM_CMD_DONE);
3307 *val = tr32(NVRAM_RDDATA);
3309 tg3_disable_nvram_access(tp);
3311 tg3_nvram_unlock(tp);
3316 /* Ensures NVRAM data is in bytestream format. */
3317 static int tg3_nvram_read_be32(struct tg3 *tp, u32 offset, __be32 *val)
3320 int res = tg3_nvram_read(tp, offset, &v);
3322 *val = cpu_to_be32(v);
3326 static int tg3_nvram_write_block_using_eeprom(struct tg3 *tp,
3327 u32 offset, u32 len, u8 *buf)
3332 for (i = 0; i < len; i += 4) {
3338 memcpy(&data, buf + i, 4);
3341 * The SEEPROM interface expects the data to always be opposite
3342 * the native endian format. We accomplish this by reversing
3343 * all the operations that would have been performed on the
3344 * data from a call to tg3_nvram_read_be32().
3346 tw32(GRC_EEPROM_DATA, swab32(be32_to_cpu(data)));
3348 val = tr32(GRC_EEPROM_ADDR);
3349 tw32(GRC_EEPROM_ADDR, val | EEPROM_ADDR_COMPLETE);
3351 val &= ~(EEPROM_ADDR_ADDR_MASK | EEPROM_ADDR_DEVID_MASK |
3353 tw32(GRC_EEPROM_ADDR, val |
3354 (0 << EEPROM_ADDR_DEVID_SHIFT) |
3355 (addr & EEPROM_ADDR_ADDR_MASK) |
3359 for (j = 0; j < 1000; j++) {
3360 val = tr32(GRC_EEPROM_ADDR);
3362 if (val & EEPROM_ADDR_COMPLETE)
3366 if (!(val & EEPROM_ADDR_COMPLETE)) {
3375 /* offset and length are dword aligned */
3376 static int tg3_nvram_write_block_unbuffered(struct tg3 *tp, u32 offset, u32 len,
3380 u32 pagesize = tp->nvram_pagesize;
3381 u32 pagemask = pagesize - 1;
3385 tmp = kmalloc(pagesize, GFP_KERNEL);
3391 u32 phy_addr, page_off, size;
3393 phy_addr = offset & ~pagemask;
3395 for (j = 0; j < pagesize; j += 4) {
3396 ret = tg3_nvram_read_be32(tp, phy_addr + j,
3397 (__be32 *) (tmp + j));
3404 page_off = offset & pagemask;
3411 memcpy(tmp + page_off, buf, size);
3413 offset = offset + (pagesize - page_off);
3415 tg3_enable_nvram_access(tp);
3418 * Before we can erase the flash page, we need
3419 * to issue a special "write enable" command.
3421 nvram_cmd = NVRAM_CMD_WREN | NVRAM_CMD_GO | NVRAM_CMD_DONE;
3423 if (tg3_nvram_exec_cmd(tp, nvram_cmd))
3426 /* Erase the target page */
3427 tw32(NVRAM_ADDR, phy_addr);
3429 nvram_cmd = NVRAM_CMD_GO | NVRAM_CMD_DONE | NVRAM_CMD_WR |
3430 NVRAM_CMD_FIRST | NVRAM_CMD_LAST | NVRAM_CMD_ERASE;
3432 if (tg3_nvram_exec_cmd(tp, nvram_cmd))
3435 /* Issue another write enable to start the write. */
3436 nvram_cmd = NVRAM_CMD_WREN | NVRAM_CMD_GO | NVRAM_CMD_DONE;
3438 if (tg3_nvram_exec_cmd(tp, nvram_cmd))
3441 for (j = 0; j < pagesize; j += 4) {
3444 data = *((__be32 *) (tmp + j));
3446 tw32(NVRAM_WRDATA, be32_to_cpu(data));
3448 tw32(NVRAM_ADDR, phy_addr + j);
3450 nvram_cmd = NVRAM_CMD_GO | NVRAM_CMD_DONE |
3454 nvram_cmd |= NVRAM_CMD_FIRST;
3455 else if (j == (pagesize - 4))
3456 nvram_cmd |= NVRAM_CMD_LAST;
3458 ret = tg3_nvram_exec_cmd(tp, nvram_cmd);
3466 nvram_cmd = NVRAM_CMD_WRDI | NVRAM_CMD_GO | NVRAM_CMD_DONE;
3467 tg3_nvram_exec_cmd(tp, nvram_cmd);
3474 /* offset and length are dword aligned */
3475 static int tg3_nvram_write_block_buffered(struct tg3 *tp, u32 offset, u32 len,
3480 for (i = 0; i < len; i += 4, offset += 4) {
3481 u32 page_off, phy_addr, nvram_cmd;
3484 memcpy(&data, buf + i, 4);
3485 tw32(NVRAM_WRDATA, be32_to_cpu(data));
3487 page_off = offset % tp->nvram_pagesize;
3489 phy_addr = tg3_nvram_phys_addr(tp, offset);
3491 nvram_cmd = NVRAM_CMD_GO | NVRAM_CMD_DONE | NVRAM_CMD_WR;
3493 if (page_off == 0 || i == 0)
3494 nvram_cmd |= NVRAM_CMD_FIRST;
3495 if (page_off == (tp->nvram_pagesize - 4))
3496 nvram_cmd |= NVRAM_CMD_LAST;
3499 nvram_cmd |= NVRAM_CMD_LAST;
3501 if ((nvram_cmd & NVRAM_CMD_FIRST) ||
3502 !tg3_flag(tp, FLASH) ||
3503 !tg3_flag(tp, 57765_PLUS))
3504 tw32(NVRAM_ADDR, phy_addr);
3506 if (tg3_asic_rev(tp) != ASIC_REV_5752 &&
3507 !tg3_flag(tp, 5755_PLUS) &&
3508 (tp->nvram_jedecnum == JEDEC_ST) &&
3509 (nvram_cmd & NVRAM_CMD_FIRST)) {
3512 cmd = NVRAM_CMD_WREN | NVRAM_CMD_GO | NVRAM_CMD_DONE;
3513 ret = tg3_nvram_exec_cmd(tp, cmd);
3517 if (!tg3_flag(tp, FLASH)) {
3518 /* We always do complete word writes to eeprom. */
3519 nvram_cmd |= (NVRAM_CMD_FIRST | NVRAM_CMD_LAST);
3522 ret = tg3_nvram_exec_cmd(tp, nvram_cmd);
3529 /* offset and length are dword aligned */
3530 static int tg3_nvram_write_block(struct tg3 *tp, u32 offset, u32 len, u8 *buf)
3534 if (tg3_flag(tp, EEPROM_WRITE_PROT)) {
3535 tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl &
3536 ~GRC_LCLCTRL_GPIO_OUTPUT1);
3540 if (!tg3_flag(tp, NVRAM)) {
3541 ret = tg3_nvram_write_block_using_eeprom(tp, offset, len, buf);
3545 ret = tg3_nvram_lock(tp);
3549 tg3_enable_nvram_access(tp);
3550 if (tg3_flag(tp, 5750_PLUS) && !tg3_flag(tp, PROTECTED_NVRAM))
3551 tw32(NVRAM_WRITE1, 0x406);
3553 grc_mode = tr32(GRC_MODE);
3554 tw32(GRC_MODE, grc_mode | GRC_MODE_NVRAM_WR_ENABLE);
3556 if (tg3_flag(tp, NVRAM_BUFFERED) || !tg3_flag(tp, FLASH)) {
3557 ret = tg3_nvram_write_block_buffered(tp, offset, len,
3560 ret = tg3_nvram_write_block_unbuffered(tp, offset, len,
3564 grc_mode = tr32(GRC_MODE);
3565 tw32(GRC_MODE, grc_mode & ~GRC_MODE_NVRAM_WR_ENABLE);
3567 tg3_disable_nvram_access(tp);
3568 tg3_nvram_unlock(tp);
3571 if (tg3_flag(tp, EEPROM_WRITE_PROT)) {
3572 tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl);
3579 #define RX_CPU_SCRATCH_BASE 0x30000
3580 #define RX_CPU_SCRATCH_SIZE 0x04000
3581 #define TX_CPU_SCRATCH_BASE 0x34000
3582 #define TX_CPU_SCRATCH_SIZE 0x04000
3584 /* tp->lock is held. */
3585 static int tg3_pause_cpu(struct tg3 *tp, u32 cpu_base)
3588 const int iters = 10000;
3590 for (i = 0; i < iters; i++) {
3591 tw32(cpu_base + CPU_STATE, 0xffffffff);
3592 tw32(cpu_base + CPU_MODE, CPU_MODE_HALT);
3593 if (tr32(cpu_base + CPU_MODE) & CPU_MODE_HALT)
3595 if (pci_channel_offline(tp->pdev))
3599 return (i == iters) ? -EBUSY : 0;
3602 /* tp->lock is held. */
3603 static int tg3_rxcpu_pause(struct tg3 *tp)
3605 int rc = tg3_pause_cpu(tp, RX_CPU_BASE);
3607 tw32(RX_CPU_BASE + CPU_STATE, 0xffffffff);
3608 tw32_f(RX_CPU_BASE + CPU_MODE, CPU_MODE_HALT);
3614 /* tp->lock is held. */
3615 static int tg3_txcpu_pause(struct tg3 *tp)
3617 return tg3_pause_cpu(tp, TX_CPU_BASE);
3620 /* tp->lock is held. */
3621 static void tg3_resume_cpu(struct tg3 *tp, u32 cpu_base)
3623 tw32(cpu_base + CPU_STATE, 0xffffffff);
3624 tw32_f(cpu_base + CPU_MODE, 0x00000000);
3627 /* tp->lock is held. */
3628 static void tg3_rxcpu_resume(struct tg3 *tp)
3630 tg3_resume_cpu(tp, RX_CPU_BASE);
3633 /* tp->lock is held. */
3634 static int tg3_halt_cpu(struct tg3 *tp, u32 cpu_base)
3638 BUG_ON(cpu_base == TX_CPU_BASE && tg3_flag(tp, 5705_PLUS));
3640 if (tg3_asic_rev(tp) == ASIC_REV_5906) {
3641 u32 val = tr32(GRC_VCPU_EXT_CTRL);
3643 tw32(GRC_VCPU_EXT_CTRL, val | GRC_VCPU_EXT_CTRL_HALT_CPU);
3646 if (cpu_base == RX_CPU_BASE) {
3647 rc = tg3_rxcpu_pause(tp);
3650 * There is only an Rx CPU for the 5750 derivative in the
3653 if (tg3_flag(tp, IS_SSB_CORE))
3656 rc = tg3_txcpu_pause(tp);
3660 netdev_err(tp->dev, "%s timed out, %s CPU\n",
3661 __func__, cpu_base == RX_CPU_BASE ? "RX" : "TX");
3665 /* Clear firmware's nvram arbitration. */
3666 if (tg3_flag(tp, NVRAM))
3667 tw32(NVRAM_SWARB, SWARB_REQ_CLR0);
3671 static int tg3_fw_data_len(struct tg3 *tp,
3672 const struct tg3_firmware_hdr *fw_hdr)
3676 /* Non fragmented firmware have one firmware header followed by a
3677 * contiguous chunk of data to be written. The length field in that
3678 * header is not the length of data to be written but the complete
3679 * length of the bss. The data length is determined based on
3680 * tp->fw->size minus headers.
3682 * Fragmented firmware have a main header followed by multiple
3683 * fragments. Each fragment is identical to non fragmented firmware
3684 * with a firmware header followed by a contiguous chunk of data. In
3685 * the main header, the length field is unused and set to 0xffffffff.
3686 * In each fragment header the length is the entire size of that
3687 * fragment i.e. fragment data + header length. Data length is
3688 * therefore length field in the header minus TG3_FW_HDR_LEN.
3690 if (tp->fw_len == 0xffffffff)
3691 fw_len = be32_to_cpu(fw_hdr->len);
3693 fw_len = tp->fw->size;
3695 return (fw_len - TG3_FW_HDR_LEN) / sizeof(u32);
3698 /* tp->lock is held. */
3699 static int tg3_load_firmware_cpu(struct tg3 *tp, u32 cpu_base,
3700 u32 cpu_scratch_base, int cpu_scratch_size,
3701 const struct tg3_firmware_hdr *fw_hdr)
3704 void (*write_op)(struct tg3 *, u32, u32);
3705 int total_len = tp->fw->size;
3707 if (cpu_base == TX_CPU_BASE && tg3_flag(tp, 5705_PLUS)) {
3709 "%s: Trying to load TX cpu firmware which is 5705\n",
3714 if (tg3_flag(tp, 5705_PLUS) && tg3_asic_rev(tp) != ASIC_REV_57766)
3715 write_op = tg3_write_mem;
3717 write_op = tg3_write_indirect_reg32;
3719 if (tg3_asic_rev(tp) != ASIC_REV_57766) {
3720 /* It is possible that bootcode is still loading at this point.
3721 * Get the nvram lock first before halting the cpu.
3723 int lock_err = tg3_nvram_lock(tp);
3724 err = tg3_halt_cpu(tp, cpu_base);
3726 tg3_nvram_unlock(tp);
3730 for (i = 0; i < cpu_scratch_size; i += sizeof(u32))
3731 write_op(tp, cpu_scratch_base + i, 0);
3732 tw32(cpu_base + CPU_STATE, 0xffffffff);
3733 tw32(cpu_base + CPU_MODE,
3734 tr32(cpu_base + CPU_MODE) | CPU_MODE_HALT);
3736 /* Subtract additional main header for fragmented firmware and
3737 * advance to the first fragment
3739 total_len -= TG3_FW_HDR_LEN;
3744 u32 *fw_data = (u32 *)(fw_hdr + 1);
3745 for (i = 0; i < tg3_fw_data_len(tp, fw_hdr); i++)
3746 write_op(tp, cpu_scratch_base +
3747 (be32_to_cpu(fw_hdr->base_addr) & 0xffff) +
3749 be32_to_cpu(fw_data[i]));
3751 total_len -= be32_to_cpu(fw_hdr->len);
3753 /* Advance to next fragment */
3754 fw_hdr = (struct tg3_firmware_hdr *)
3755 ((void *)fw_hdr + be32_to_cpu(fw_hdr->len));
3756 } while (total_len > 0);
3764 /* tp->lock is held. */
3765 static int tg3_pause_cpu_and_set_pc(struct tg3 *tp, u32 cpu_base, u32 pc)
3768 const int iters = 5;
3770 tw32(cpu_base + CPU_STATE, 0xffffffff);
3771 tw32_f(cpu_base + CPU_PC, pc);
3773 for (i = 0; i < iters; i++) {
3774 if (tr32(cpu_base + CPU_PC) == pc)
3776 tw32(cpu_base + CPU_STATE, 0xffffffff);
3777 tw32(cpu_base + CPU_MODE, CPU_MODE_HALT);
3778 tw32_f(cpu_base + CPU_PC, pc);
3782 return (i == iters) ? -EBUSY : 0;
3785 /* tp->lock is held. */
3786 static int tg3_load_5701_a0_firmware_fix(struct tg3 *tp)
3788 const struct tg3_firmware_hdr *fw_hdr;
3791 fw_hdr = (struct tg3_firmware_hdr *)tp->fw->data;
3793 /* Firmware blob starts with version numbers, followed by
3794 start address and length. We are setting complete length.
3795 length = end_address_of_bss - start_address_of_text.
3796 Remainder is the blob to be loaded contiguously
3797 from start address. */
3799 err = tg3_load_firmware_cpu(tp, RX_CPU_BASE,
3800 RX_CPU_SCRATCH_BASE, RX_CPU_SCRATCH_SIZE,
3805 err = tg3_load_firmware_cpu(tp, TX_CPU_BASE,
3806 TX_CPU_SCRATCH_BASE, TX_CPU_SCRATCH_SIZE,
3811 /* Now startup only the RX cpu. */
3812 err = tg3_pause_cpu_and_set_pc(tp, RX_CPU_BASE,
3813 be32_to_cpu(fw_hdr->base_addr));
3815 netdev_err(tp->dev, "%s fails to set RX CPU PC, is %08x "
3816 "should be %08x\n", __func__,
3817 tr32(RX_CPU_BASE + CPU_PC),
3818 be32_to_cpu(fw_hdr->base_addr));
3822 tg3_rxcpu_resume(tp);
3827 static int tg3_validate_rxcpu_state(struct tg3 *tp)
3829 const int iters = 1000;
3833 /* Wait for boot code to complete initialization and enter service
3834 * loop. It is then safe to download service patches
3836 for (i = 0; i < iters; i++) {
3837 if (tr32(RX_CPU_HWBKPT) == TG3_SBROM_IN_SERVICE_LOOP)
3844 netdev_err(tp->dev, "Boot code not ready for service patches\n");
3848 val = tg3_read_indirect_reg32(tp, TG3_57766_FW_HANDSHAKE);
3850 netdev_warn(tp->dev,
3851 "Other patches exist. Not downloading EEE patch\n");
3858 /* tp->lock is held. */
3859 static void tg3_load_57766_firmware(struct tg3 *tp)
3861 struct tg3_firmware_hdr *fw_hdr;
3863 if (!tg3_flag(tp, NO_NVRAM))
3866 if (tg3_validate_rxcpu_state(tp))
3872 /* This firmware blob has a different format than older firmware
3873 * releases as given below. The main difference is we have fragmented
3874 * data to be written to non-contiguous locations.
3876 * In the beginning we have a firmware header identical to other
3877 * firmware which consists of version, base addr and length. The length
3878 * here is unused and set to 0xffffffff.
3880 * This is followed by a series of firmware fragments which are
3881 * individually identical to previous firmware. i.e. they have the
3882 * firmware header and followed by data for that fragment. The version
3883 * field of the individual fragment header is unused.
3886 fw_hdr = (struct tg3_firmware_hdr *)tp->fw->data;
3887 if (be32_to_cpu(fw_hdr->base_addr) != TG3_57766_FW_BASE_ADDR)
3890 if (tg3_rxcpu_pause(tp))
3893 /* tg3_load_firmware_cpu() will always succeed for the 57766 */
3894 tg3_load_firmware_cpu(tp, 0, TG3_57766_FW_BASE_ADDR, 0, fw_hdr);
3896 tg3_rxcpu_resume(tp);
3899 /* tp->lock is held. */
3900 static int tg3_load_tso_firmware(struct tg3 *tp)
3902 const struct tg3_firmware_hdr *fw_hdr;
3903 unsigned long cpu_base, cpu_scratch_base, cpu_scratch_size;
3906 if (!tg3_flag(tp, FW_TSO))
3909 fw_hdr = (struct tg3_firmware_hdr *)tp->fw->data;
3911 /* Firmware blob starts with version numbers, followed by
3912 start address and length. We are setting complete length.
3913 length = end_address_of_bss - start_address_of_text.
3914 Remainder is the blob to be loaded contiguously
3915 from start address. */
3917 cpu_scratch_size = tp->fw_len;
3919 if (tg3_asic_rev(tp) == ASIC_REV_5705) {
3920 cpu_base = RX_CPU_BASE;
3921 cpu_scratch_base = NIC_SRAM_MBUF_POOL_BASE5705;
3923 cpu_base = TX_CPU_BASE;
3924 cpu_scratch_base = TX_CPU_SCRATCH_BASE;
3925 cpu_scratch_size = TX_CPU_SCRATCH_SIZE;
3928 err = tg3_load_firmware_cpu(tp, cpu_base,
3929 cpu_scratch_base, cpu_scratch_size,
3934 /* Now startup the cpu. */
3935 err = tg3_pause_cpu_and_set_pc(tp, cpu_base,
3936 be32_to_cpu(fw_hdr->base_addr));
3939 "%s fails to set CPU PC, is %08x should be %08x\n",
3940 __func__, tr32(cpu_base + CPU_PC),
3941 be32_to_cpu(fw_hdr->base_addr));
3945 tg3_resume_cpu(tp, cpu_base);
3949 /* tp->lock is held. */
3950 static void __tg3_set_one_mac_addr(struct tg3 *tp, u8 *mac_addr, int index)
3952 u32 addr_high, addr_low;
3954 addr_high = ((mac_addr[0] << 8) | mac_addr[1]);
3955 addr_low = ((mac_addr[2] << 24) | (mac_addr[3] << 16) |
3956 (mac_addr[4] << 8) | mac_addr[5]);
3959 tw32(MAC_ADDR_0_HIGH + (index * 8), addr_high);
3960 tw32(MAC_ADDR_0_LOW + (index * 8), addr_low);
3963 tw32(MAC_EXTADDR_0_HIGH + (index * 8), addr_high);
3964 tw32(MAC_EXTADDR_0_LOW + (index * 8), addr_low);
3968 /* tp->lock is held. */
3969 static void __tg3_set_mac_addr(struct tg3 *tp, bool skip_mac_1)
3974 for (i = 0; i < 4; i++) {
3975 if (i == 1 && skip_mac_1)
3977 __tg3_set_one_mac_addr(tp, tp->dev->dev_addr, i);
3980 if (tg3_asic_rev(tp) == ASIC_REV_5703 ||
3981 tg3_asic_rev(tp) == ASIC_REV_5704) {
3982 for (i = 4; i < 16; i++)
3983 __tg3_set_one_mac_addr(tp, tp->dev->dev_addr, i);
3986 addr_high = (tp->dev->dev_addr[0] +
3987 tp->dev->dev_addr[1] +
3988 tp->dev->dev_addr[2] +
3989 tp->dev->dev_addr[3] +
3990 tp->dev->dev_addr[4] +
3991 tp->dev->dev_addr[5]) &
3992 TX_BACKOFF_SEED_MASK;
3993 tw32(MAC_TX_BACKOFF_SEED, addr_high);
3996 static void tg3_enable_register_access(struct tg3 *tp)
3999 * Make sure register accesses (indirect or otherwise) will function
4002 pci_write_config_dword(tp->pdev,
4003 TG3PCI_MISC_HOST_CTRL, tp->misc_host_ctrl);
4006 static int tg3_power_up(struct tg3 *tp)
4010 tg3_enable_register_access(tp);
4012 err = pci_set_power_state(tp->pdev, PCI_D0);
4014 /* Switch out of Vaux if it is a NIC */
4015 tg3_pwrsrc_switch_to_vmain(tp);
4017 netdev_err(tp->dev, "Transition to D0 failed\n");
4023 static int tg3_setup_phy(struct tg3 *, bool);
4025 static int tg3_power_down_prepare(struct tg3 *tp)
4028 bool device_should_wake, do_low_power;
4030 tg3_enable_register_access(tp);
4032 /* Restore the CLKREQ setting. */
4033 if (tg3_flag(tp, CLKREQ_BUG))
4034 pcie_capability_set_word(tp->pdev, PCI_EXP_LNKCTL,
4035 PCI_EXP_LNKCTL_CLKREQ_EN);
4037 misc_host_ctrl = tr32(TG3PCI_MISC_HOST_CTRL);
4038 tw32(TG3PCI_MISC_HOST_CTRL,
4039 misc_host_ctrl | MISC_HOST_CTRL_MASK_PCI_INT);
4041 device_should_wake = device_may_wakeup(&tp->pdev->dev) &&
4042 tg3_flag(tp, WOL_ENABLE);
4044 if (tg3_flag(tp, USE_PHYLIB)) {
4045 do_low_power = false;
4046 if ((tp->phy_flags & TG3_PHYFLG_IS_CONNECTED) &&
4047 !(tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER)) {
4048 struct phy_device *phydev;
4049 u32 phyid, advertising;
4051 phydev = tp->mdio_bus->phy_map[tp->phy_addr];
4053 tp->phy_flags |= TG3_PHYFLG_IS_LOW_POWER;
4055 tp->link_config.speed = phydev->speed;
4056 tp->link_config.duplex = phydev->duplex;
4057 tp->link_config.autoneg = phydev->autoneg;
4058 tp->link_config.advertising = phydev->advertising;
4060 advertising = ADVERTISED_TP |
4062 ADVERTISED_Autoneg |
4063 ADVERTISED_10baseT_Half;
4065 if (tg3_flag(tp, ENABLE_ASF) || device_should_wake) {
4066 if (tg3_flag(tp, WOL_SPEED_100MB))
4068 ADVERTISED_100baseT_Half |
4069 ADVERTISED_100baseT_Full |
4070 ADVERTISED_10baseT_Full;
4072 advertising |= ADVERTISED_10baseT_Full;
4075 phydev->advertising = advertising;
4077 phy_start_aneg(phydev);
4079 phyid = phydev->drv->phy_id & phydev->drv->phy_id_mask;
4080 if (phyid != PHY_ID_BCMAC131) {
4081 phyid &= PHY_BCM_OUI_MASK;
4082 if (phyid == PHY_BCM_OUI_1 ||
4083 phyid == PHY_BCM_OUI_2 ||
4084 phyid == PHY_BCM_OUI_3)
4085 do_low_power = true;
4089 do_low_power = true;
4091 if (!(tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER))
4092 tp->phy_flags |= TG3_PHYFLG_IS_LOW_POWER;
4094 if (!(tp->phy_flags & TG3_PHYFLG_ANY_SERDES))
4095 tg3_setup_phy(tp, false);
4098 if (tg3_asic_rev(tp) == ASIC_REV_5906) {
4101 val = tr32(GRC_VCPU_EXT_CTRL);
4102 tw32(GRC_VCPU_EXT_CTRL, val | GRC_VCPU_EXT_CTRL_DISABLE_WOL);
4103 } else if (!tg3_flag(tp, ENABLE_ASF)) {
4107 for (i = 0; i < 200; i++) {
4108 tg3_read_mem(tp, NIC_SRAM_FW_ASF_STATUS_MBOX, &val);
4109 if (val == ~NIC_SRAM_FIRMWARE_MBOX_MAGIC1)
4114 if (tg3_flag(tp, WOL_CAP))
4115 tg3_write_mem(tp, NIC_SRAM_WOL_MBOX, WOL_SIGNATURE |
4116 WOL_DRV_STATE_SHUTDOWN |
4120 if (device_should_wake) {
4123 if (!(tp->phy_flags & TG3_PHYFLG_PHY_SERDES)) {
4125 !(tp->phy_flags & TG3_PHYFLG_IS_FET)) {
4126 tg3_phy_auxctl_write(tp,
4127 MII_TG3_AUXCTL_SHDWSEL_PWRCTL,
4128 MII_TG3_AUXCTL_PCTL_WOL_EN |
4129 MII_TG3_AUXCTL_PCTL_100TX_LPWR |
4130 MII_TG3_AUXCTL_PCTL_CL_AB_TXDAC);
4134 if (tp->phy_flags & TG3_PHYFLG_MII_SERDES)
4135 mac_mode = MAC_MODE_PORT_MODE_GMII;
4136 else if (tp->phy_flags &
4137 TG3_PHYFLG_KEEP_LINK_ON_PWRDN) {
4138 if (tp->link_config.active_speed == SPEED_1000)
4139 mac_mode = MAC_MODE_PORT_MODE_GMII;
4141 mac_mode = MAC_MODE_PORT_MODE_MII;
4143 mac_mode = MAC_MODE_PORT_MODE_MII;
4145 mac_mode |= tp->mac_mode & MAC_MODE_LINK_POLARITY;
4146 if (tg3_asic_rev(tp) == ASIC_REV_5700) {
4147 u32 speed = tg3_flag(tp, WOL_SPEED_100MB) ?
4148 SPEED_100 : SPEED_10;
4149 if (tg3_5700_link_polarity(tp, speed))
4150 mac_mode |= MAC_MODE_LINK_POLARITY;
4152 mac_mode &= ~MAC_MODE_LINK_POLARITY;
4155 mac_mode = MAC_MODE_PORT_MODE_TBI;
4158 if (!tg3_flag(tp, 5750_PLUS))
4159 tw32(MAC_LED_CTRL, tp->led_ctrl);
4161 mac_mode |= MAC_MODE_MAGIC_PKT_ENABLE;
4162 if ((tg3_flag(tp, 5705_PLUS) && !tg3_flag(tp, 5780_CLASS)) &&
4163 (tg3_flag(tp, ENABLE_ASF) || tg3_flag(tp, ENABLE_APE)))
4164 mac_mode |= MAC_MODE_KEEP_FRAME_IN_WOL;
4166 if (tg3_flag(tp, ENABLE_APE))
4167 mac_mode |= MAC_MODE_APE_TX_EN |
4168 MAC_MODE_APE_RX_EN |
4169 MAC_MODE_TDE_ENABLE;
4171 tw32_f(MAC_MODE, mac_mode);
4174 tw32_f(MAC_RX_MODE, RX_MODE_ENABLE);
4178 if (!tg3_flag(tp, WOL_SPEED_100MB) &&
4179 (tg3_asic_rev(tp) == ASIC_REV_5700 ||
4180 tg3_asic_rev(tp) == ASIC_REV_5701)) {
4183 base_val = tp->pci_clock_ctrl;
4184 base_val |= (CLOCK_CTRL_RXCLK_DISABLE |
4185 CLOCK_CTRL_TXCLK_DISABLE);
4187 tw32_wait_f(TG3PCI_CLOCK_CTRL, base_val | CLOCK_CTRL_ALTCLK |
4188 CLOCK_CTRL_PWRDOWN_PLL133, 40);
4189 } else if (tg3_flag(tp, 5780_CLASS) ||
4190 tg3_flag(tp, CPMU_PRESENT) ||
4191 tg3_asic_rev(tp) == ASIC_REV_5906) {
4193 } else if (!(tg3_flag(tp, 5750_PLUS) && tg3_flag(tp, ENABLE_ASF))) {
4194 u32 newbits1, newbits2;
4196 if (tg3_asic_rev(tp) == ASIC_REV_5700 ||
4197 tg3_asic_rev(tp) == ASIC_REV_5701) {
4198 newbits1 = (CLOCK_CTRL_RXCLK_DISABLE |
4199 CLOCK_CTRL_TXCLK_DISABLE |
4201 newbits2 = newbits1 | CLOCK_CTRL_44MHZ_CORE;
4202 } else if (tg3_flag(tp, 5705_PLUS)) {
4203 newbits1 = CLOCK_CTRL_625_CORE;
4204 newbits2 = newbits1 | CLOCK_CTRL_ALTCLK;
4206 newbits1 = CLOCK_CTRL_ALTCLK;
4207 newbits2 = newbits1 | CLOCK_CTRL_44MHZ_CORE;
4210 tw32_wait_f(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl | newbits1,
4213 tw32_wait_f(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl | newbits2,
4216 if (!tg3_flag(tp, 5705_PLUS)) {
4219 if (tg3_asic_rev(tp) == ASIC_REV_5700 ||
4220 tg3_asic_rev(tp) == ASIC_REV_5701) {
4221 newbits3 = (CLOCK_CTRL_RXCLK_DISABLE |
4222 CLOCK_CTRL_TXCLK_DISABLE |
4223 CLOCK_CTRL_44MHZ_CORE);
4225 newbits3 = CLOCK_CTRL_44MHZ_CORE;
4228 tw32_wait_f(TG3PCI_CLOCK_CTRL,
4229 tp->pci_clock_ctrl | newbits3, 40);
4233 if (!(device_should_wake) && !tg3_flag(tp, ENABLE_ASF))
4234 tg3_power_down_phy(tp, do_low_power);
4236 tg3_frob_aux_power(tp, true);
4238 /* Workaround for unstable PLL clock */
4239 if ((!tg3_flag(tp, IS_SSB_CORE)) &&
4240 ((tg3_chip_rev(tp) == CHIPREV_5750_AX) ||
4241 (tg3_chip_rev(tp) == CHIPREV_5750_BX))) {
4242 u32 val = tr32(0x7d00);
4244 val &= ~((1 << 16) | (1 << 4) | (1 << 2) | (1 << 1) | 1);
4246 if (!tg3_flag(tp, ENABLE_ASF)) {
4249 err = tg3_nvram_lock(tp);
4250 tg3_halt_cpu(tp, RX_CPU_BASE);
4252 tg3_nvram_unlock(tp);
4256 tg3_write_sig_post_reset(tp, RESET_KIND_SHUTDOWN);
4258 tg3_ape_driver_state_change(tp, RESET_KIND_SHUTDOWN);
4263 static void tg3_power_down(struct tg3 *tp)
4265 pci_wake_from_d3(tp->pdev, tg3_flag(tp, WOL_ENABLE));
4266 pci_set_power_state(tp->pdev, PCI_D3hot);
4269 static void tg3_aux_stat_to_speed_duplex(struct tg3 *tp, u32 val, u16 *speed, u8 *duplex)
4271 switch (val & MII_TG3_AUX_STAT_SPDMASK) {
4272 case MII_TG3_AUX_STAT_10HALF:
4274 *duplex = DUPLEX_HALF;
4277 case MII_TG3_AUX_STAT_10FULL:
4279 *duplex = DUPLEX_FULL;
4282 case MII_TG3_AUX_STAT_100HALF:
4284 *duplex = DUPLEX_HALF;
4287 case MII_TG3_AUX_STAT_100FULL:
4289 *duplex = DUPLEX_FULL;
4292 case MII_TG3_AUX_STAT_1000HALF:
4293 *speed = SPEED_1000;
4294 *duplex = DUPLEX_HALF;
4297 case MII_TG3_AUX_STAT_1000FULL:
4298 *speed = SPEED_1000;
4299 *duplex = DUPLEX_FULL;
4303 if (tp->phy_flags & TG3_PHYFLG_IS_FET) {
4304 *speed = (val & MII_TG3_AUX_STAT_100) ? SPEED_100 :
4306 *duplex = (val & MII_TG3_AUX_STAT_FULL) ? DUPLEX_FULL :
4310 *speed = SPEED_UNKNOWN;
4311 *duplex = DUPLEX_UNKNOWN;
4316 static int tg3_phy_autoneg_cfg(struct tg3 *tp, u32 advertise, u32 flowctrl)
4321 new_adv = ADVERTISE_CSMA;
4322 new_adv |= ethtool_adv_to_mii_adv_t(advertise) & ADVERTISE_ALL;
4323 new_adv |= mii_advertise_flowctrl(flowctrl);
4325 err = tg3_writephy(tp, MII_ADVERTISE, new_adv);
4329 if (!(tp->phy_flags & TG3_PHYFLG_10_100_ONLY)) {
4330 new_adv = ethtool_adv_to_mii_ctrl1000_t(advertise);
4332 if (tg3_chip_rev_id(tp) == CHIPREV_ID_5701_A0 ||
4333 tg3_chip_rev_id(tp) == CHIPREV_ID_5701_B0)
4334 new_adv |= CTL1000_AS_MASTER | CTL1000_ENABLE_MASTER;
4336 err = tg3_writephy(tp, MII_CTRL1000, new_adv);
4341 if (!(tp->phy_flags & TG3_PHYFLG_EEE_CAP))
4344 tw32(TG3_CPMU_EEE_MODE,
4345 tr32(TG3_CPMU_EEE_MODE) & ~TG3_CPMU_EEEMD_LPI_ENABLE);
4347 err = tg3_phy_toggle_auxctl_smdsp(tp, true);
4352 /* Advertise 100-BaseTX EEE ability */
4353 if (advertise & ADVERTISED_100baseT_Full)
4354 val |= MDIO_AN_EEE_ADV_100TX;
4355 /* Advertise 1000-BaseT EEE ability */
4356 if (advertise & ADVERTISED_1000baseT_Full)
4357 val |= MDIO_AN_EEE_ADV_1000T;
4359 if (!tp->eee.eee_enabled) {
4361 tp->eee.advertised = 0;
4363 tp->eee.advertised = advertise &
4364 (ADVERTISED_100baseT_Full |
4365 ADVERTISED_1000baseT_Full);
4368 err = tg3_phy_cl45_write(tp, MDIO_MMD_AN, MDIO_AN_EEE_ADV, val);
4372 switch (tg3_asic_rev(tp)) {
4374 case ASIC_REV_57765:
4375 case ASIC_REV_57766:
4377 /* If we advertised any eee advertisements above... */
4379 val = MII_TG3_DSP_TAP26_ALNOKO |
4380 MII_TG3_DSP_TAP26_RMRXSTO |
4381 MII_TG3_DSP_TAP26_OPCSINPT;
4382 tg3_phydsp_write(tp, MII_TG3_DSP_TAP26, val);
4386 if (!tg3_phydsp_read(tp, MII_TG3_DSP_CH34TP2, &val))
4387 tg3_phydsp_write(tp, MII_TG3_DSP_CH34TP2, val |
4388 MII_TG3_DSP_CH34TP2_HIBW01);
4391 err2 = tg3_phy_toggle_auxctl_smdsp(tp, false);
4400 static void tg3_phy_copper_begin(struct tg3 *tp)
4402 if (tp->link_config.autoneg == AUTONEG_ENABLE ||
4403 (tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER)) {
4406 if ((tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER) &&
4407 !(tp->phy_flags & TG3_PHYFLG_KEEP_LINK_ON_PWRDN)) {
4408 adv = ADVERTISED_10baseT_Half |
4409 ADVERTISED_10baseT_Full;
4410 if (tg3_flag(tp, WOL_SPEED_100MB))
4411 adv |= ADVERTISED_100baseT_Half |
4412 ADVERTISED_100baseT_Full;
4413 if (tp->phy_flags & TG3_PHYFLG_1G_ON_VAUX_OK) {
4414 if (!(tp->phy_flags &
4415 TG3_PHYFLG_DISABLE_1G_HD_ADV))
4416 adv |= ADVERTISED_1000baseT_Half;
4417 adv |= ADVERTISED_1000baseT_Full;
4420 fc = FLOW_CTRL_TX | FLOW_CTRL_RX;
4422 adv = tp->link_config.advertising;
4423 if (tp->phy_flags & TG3_PHYFLG_10_100_ONLY)
4424 adv &= ~(ADVERTISED_1000baseT_Half |
4425 ADVERTISED_1000baseT_Full);
4427 fc = tp->link_config.flowctrl;
4430 tg3_phy_autoneg_cfg(tp, adv, fc);
4432 if ((tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER) &&
4433 (tp->phy_flags & TG3_PHYFLG_KEEP_LINK_ON_PWRDN)) {
4434 /* Normally during power down we want to autonegotiate
4435 * the lowest possible speed for WOL. However, to avoid
4436 * link flap, we leave it untouched.
4441 tg3_writephy(tp, MII_BMCR,
4442 BMCR_ANENABLE | BMCR_ANRESTART);
4445 u32 bmcr, orig_bmcr;
4447 tp->link_config.active_speed = tp->link_config.speed;
4448 tp->link_config.active_duplex = tp->link_config.duplex;
4450 if (tg3_asic_rev(tp) == ASIC_REV_5714) {
4451 /* With autoneg disabled, 5715 only links up when the
4452 * advertisement register has the configured speed
4455 tg3_writephy(tp, MII_ADVERTISE, ADVERTISE_ALL);
4459 switch (tp->link_config.speed) {
4465 bmcr |= BMCR_SPEED100;
4469 bmcr |= BMCR_SPEED1000;
4473 if (tp->link_config.duplex == DUPLEX_FULL)
4474 bmcr |= BMCR_FULLDPLX;
4476 if (!tg3_readphy(tp, MII_BMCR, &orig_bmcr) &&
4477 (bmcr != orig_bmcr)) {
4478 tg3_writephy(tp, MII_BMCR, BMCR_LOOPBACK);
4479 for (i = 0; i < 1500; i++) {
4483 if (tg3_readphy(tp, MII_BMSR, &tmp) ||
4484 tg3_readphy(tp, MII_BMSR, &tmp))
4486 if (!(tmp & BMSR_LSTATUS)) {
4491 tg3_writephy(tp, MII_BMCR, bmcr);
4497 static int tg3_phy_pull_config(struct tg3 *tp)
4502 err = tg3_readphy(tp, MII_BMCR, &val);
4506 if (!(val & BMCR_ANENABLE)) {
4507 tp->link_config.autoneg = AUTONEG_DISABLE;
4508 tp->link_config.advertising = 0;
4509 tg3_flag_clear(tp, PAUSE_AUTONEG);
4513 switch (val & (BMCR_SPEED1000 | BMCR_SPEED100)) {
4515 if (tp->phy_flags & TG3_PHYFLG_ANY_SERDES)
4518 tp->link_config.speed = SPEED_10;
4521 if (tp->phy_flags & TG3_PHYFLG_ANY_SERDES)
4524 tp->link_config.speed = SPEED_100;
4526 case BMCR_SPEED1000:
4527 if (!(tp->phy_flags & TG3_PHYFLG_10_100_ONLY)) {
4528 tp->link_config.speed = SPEED_1000;
4536 if (val & BMCR_FULLDPLX)
4537 tp->link_config.duplex = DUPLEX_FULL;
4539 tp->link_config.duplex = DUPLEX_HALF;
4541 tp->link_config.flowctrl = FLOW_CTRL_RX | FLOW_CTRL_TX;
4547 tp->link_config.autoneg = AUTONEG_ENABLE;
4548 tp->link_config.advertising = ADVERTISED_Autoneg;
4549 tg3_flag_set(tp, PAUSE_AUTONEG);
4551 if (!(tp->phy_flags & TG3_PHYFLG_ANY_SERDES)) {
4554 err = tg3_readphy(tp, MII_ADVERTISE, &val);
4558 adv = mii_adv_to_ethtool_adv_t(val & ADVERTISE_ALL);
4559 tp->link_config.advertising |= adv | ADVERTISED_TP;
4561 tp->link_config.flowctrl = tg3_decode_flowctrl_1000T(val);
4563 tp->link_config.advertising |= ADVERTISED_FIBRE;
4566 if (!(tp->phy_flags & TG3_PHYFLG_10_100_ONLY)) {
4569 if (!(tp->phy_flags & TG3_PHYFLG_ANY_SERDES)) {
4570 err = tg3_readphy(tp, MII_CTRL1000, &val);
4574 adv = mii_ctrl1000_to_ethtool_adv_t(val);
4576 err = tg3_readphy(tp, MII_ADVERTISE, &val);
4580 adv = tg3_decode_flowctrl_1000X(val);
4581 tp->link_config.flowctrl = adv;
4583 val &= (ADVERTISE_1000XHALF | ADVERTISE_1000XFULL);
4584 adv = mii_adv_to_ethtool_adv_x(val);
4587 tp->link_config.advertising |= adv;
4594 static int tg3_init_5401phy_dsp(struct tg3 *tp)
4598 /* Turn off tap power management. */
4599 /* Set Extended packet length bit */
4600 err = tg3_phy_auxctl_write(tp, MII_TG3_AUXCTL_SHDWSEL_AUXCTL, 0x4c20);
4602 err |= tg3_phydsp_write(tp, 0x0012, 0x1804);
4603 err |= tg3_phydsp_write(tp, 0x0013, 0x1204);
4604 err |= tg3_phydsp_write(tp, 0x8006, 0x0132);
4605 err |= tg3_phydsp_write(tp, 0x8006, 0x0232);
4606 err |= tg3_phydsp_write(tp, 0x201f, 0x0a20);
4613 static bool tg3_phy_eee_config_ok(struct tg3 *tp)
4615 struct ethtool_eee eee;
4617 if (!(tp->phy_flags & TG3_PHYFLG_EEE_CAP))
4620 tg3_eee_pull_config(tp, &eee);
4622 if (tp->eee.eee_enabled) {
4623 if (tp->eee.advertised != eee.advertised ||
4624 tp->eee.tx_lpi_timer != eee.tx_lpi_timer ||
4625 tp->eee.tx_lpi_enabled != eee.tx_lpi_enabled)
4628 /* EEE is disabled but we're advertising */
4636 static bool tg3_phy_copper_an_config_ok(struct tg3 *tp, u32 *lcladv)
4638 u32 advmsk, tgtadv, advertising;
4640 advertising = tp->link_config.advertising;
4641 tgtadv = ethtool_adv_to_mii_adv_t(advertising) & ADVERTISE_ALL;
4643 advmsk = ADVERTISE_ALL;
4644 if (tp->link_config.active_duplex == DUPLEX_FULL) {
4645 tgtadv |= mii_advertise_flowctrl(tp->link_config.flowctrl);
4646 advmsk |= ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM;
4649 if (tg3_readphy(tp, MII_ADVERTISE, lcladv))
4652 if ((*lcladv & advmsk) != tgtadv)
4655 if (!(tp->phy_flags & TG3_PHYFLG_10_100_ONLY)) {
4658 tgtadv = ethtool_adv_to_mii_ctrl1000_t(advertising);
4660 if (tg3_readphy(tp, MII_CTRL1000, &tg3_ctrl))
4664 (tg3_chip_rev_id(tp) == CHIPREV_ID_5701_A0 ||
4665 tg3_chip_rev_id(tp) == CHIPREV_ID_5701_B0)) {
4666 tgtadv |= CTL1000_AS_MASTER | CTL1000_ENABLE_MASTER;
4667 tg3_ctrl &= (ADVERTISE_1000HALF | ADVERTISE_1000FULL |
4668 CTL1000_AS_MASTER | CTL1000_ENABLE_MASTER);
4670 tg3_ctrl &= (ADVERTISE_1000HALF | ADVERTISE_1000FULL);
4673 if (tg3_ctrl != tgtadv)
4680 static bool tg3_phy_copper_fetch_rmtadv(struct tg3 *tp, u32 *rmtadv)
4684 if (!(tp->phy_flags & TG3_PHYFLG_10_100_ONLY)) {
4687 if (tg3_readphy(tp, MII_STAT1000, &val))
4690 lpeth = mii_stat1000_to_ethtool_lpa_t(val);
4693 if (tg3_readphy(tp, MII_LPA, rmtadv))
4696 lpeth |= mii_lpa_to_ethtool_lpa_t(*rmtadv);
4697 tp->link_config.rmt_adv = lpeth;
4702 static bool tg3_test_and_report_link_chg(struct tg3 *tp, bool curr_link_up)
4704 if (curr_link_up != tp->link_up) {
4706 netif_carrier_on(tp->dev);
4708 netif_carrier_off(tp->dev);
4709 if (tp->phy_flags & TG3_PHYFLG_MII_SERDES)
4710 tp->phy_flags &= ~TG3_PHYFLG_PARALLEL_DETECT;
4713 tg3_link_report(tp);
4720 static void tg3_clear_mac_status(struct tg3 *tp)
4725 MAC_STATUS_SYNC_CHANGED |
4726 MAC_STATUS_CFG_CHANGED |
4727 MAC_STATUS_MI_COMPLETION |
4728 MAC_STATUS_LNKSTATE_CHANGED);
4732 static void tg3_setup_eee(struct tg3 *tp)
4736 val = TG3_CPMU_EEE_LNKIDL_PCIE_NL0 |
4737 TG3_CPMU_EEE_LNKIDL_UART_IDL;
4738 if (tg3_chip_rev_id(tp) == CHIPREV_ID_57765_A0)
4739 val |= TG3_CPMU_EEE_LNKIDL_APE_TX_MT;
4741 tw32_f(TG3_CPMU_EEE_LNKIDL_CTRL, val);
4743 tw32_f(TG3_CPMU_EEE_CTRL,
4744 TG3_CPMU_EEE_CTRL_EXIT_20_1_US);
4746 val = TG3_CPMU_EEEMD_ERLY_L1_XIT_DET |
4747 (tp->eee.tx_lpi_enabled ? TG3_CPMU_EEEMD_LPI_IN_TX : 0) |
4748 TG3_CPMU_EEEMD_LPI_IN_RX |
4749 TG3_CPMU_EEEMD_EEE_ENABLE;
4751 if (tg3_asic_rev(tp) != ASIC_REV_5717)
4752 val |= TG3_CPMU_EEEMD_SND_IDX_DET_EN;
4754 if (tg3_flag(tp, ENABLE_APE))
4755 val |= TG3_CPMU_EEEMD_APE_TX_DET_EN;
4757 tw32_f(TG3_CPMU_EEE_MODE, tp->eee.eee_enabled ? val : 0);
4759 tw32_f(TG3_CPMU_EEE_DBTMR1,
4760 TG3_CPMU_DBTMR1_PCIEXIT_2047US |
4761 (tp->eee.tx_lpi_timer & 0xffff));
4763 tw32_f(TG3_CPMU_EEE_DBTMR2,
4764 TG3_CPMU_DBTMR2_APE_TX_2047US |
4765 TG3_CPMU_DBTMR2_TXIDXEQ_2047US);
4768 static int tg3_setup_copper_phy(struct tg3 *tp, bool force_reset)
4770 bool current_link_up;
4772 u32 lcl_adv, rmt_adv;
4777 tg3_clear_mac_status(tp);
4779 if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
4781 (tp->mi_mode & ~MAC_MI_MODE_AUTO_POLL));
4785 tg3_phy_auxctl_write(tp, MII_TG3_AUXCTL_SHDWSEL_PWRCTL, 0);
4787 /* Some third-party PHYs need to be reset on link going
4790 if ((tg3_asic_rev(tp) == ASIC_REV_5703 ||
4791 tg3_asic_rev(tp) == ASIC_REV_5704 ||
4792 tg3_asic_rev(tp) == ASIC_REV_5705) &&
4794 tg3_readphy(tp, MII_BMSR, &bmsr);
4795 if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
4796 !(bmsr & BMSR_LSTATUS))
4802 if ((tp->phy_id & TG3_PHY_ID_MASK) == TG3_PHY_ID_BCM5401) {
4803 tg3_readphy(tp, MII_BMSR, &bmsr);
4804 if (tg3_readphy(tp, MII_BMSR, &bmsr) ||
4805 !tg3_flag(tp, INIT_COMPLETE))
4808 if (!(bmsr & BMSR_LSTATUS)) {
4809 err = tg3_init_5401phy_dsp(tp);
4813 tg3_readphy(tp, MII_BMSR, &bmsr);
4814 for (i = 0; i < 1000; i++) {
4816 if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
4817 (bmsr & BMSR_LSTATUS)) {
4823 if ((tp->phy_id & TG3_PHY_ID_REV_MASK) ==
4824 TG3_PHY_REV_BCM5401_B0 &&
4825 !(bmsr & BMSR_LSTATUS) &&
4826 tp->link_config.active_speed == SPEED_1000) {
4827 err = tg3_phy_reset(tp);
4829 err = tg3_init_5401phy_dsp(tp);
4834 } else if (tg3_chip_rev_id(tp) == CHIPREV_ID_5701_A0 ||
4835 tg3_chip_rev_id(tp) == CHIPREV_ID_5701_B0) {
4836 /* 5701 {A0,B0} CRC bug workaround */
4837 tg3_writephy(tp, 0x15, 0x0a75);
4838 tg3_writephy(tp, MII_TG3_MISC_SHDW, 0x8c68);
4839 tg3_writephy(tp, MII_TG3_MISC_SHDW, 0x8d68);
4840 tg3_writephy(tp, MII_TG3_MISC_SHDW, 0x8c68);
4843 /* Clear pending interrupts... */
4844 tg3_readphy(tp, MII_TG3_ISTAT, &val);
4845 tg3_readphy(tp, MII_TG3_ISTAT, &val);
4847 if (tp->phy_flags & TG3_PHYFLG_USE_MI_INTERRUPT)
4848 tg3_writephy(tp, MII_TG3_IMASK, ~MII_TG3_INT_LINKCHG);
4849 else if (!(tp->phy_flags & TG3_PHYFLG_IS_FET))
4850 tg3_writephy(tp, MII_TG3_IMASK, ~0);
4852 if (tg3_asic_rev(tp) == ASIC_REV_5700 ||
4853 tg3_asic_rev(tp) == ASIC_REV_5701) {
4854 if (tp->led_ctrl == LED_CTRL_MODE_PHY_1)
4855 tg3_writephy(tp, MII_TG3_EXT_CTRL,
4856 MII_TG3_EXT_CTRL_LNK3_LED_MODE);
4858 tg3_writephy(tp, MII_TG3_EXT_CTRL, 0);
4861 current_link_up = false;
4862 current_speed = SPEED_UNKNOWN;
4863 current_duplex = DUPLEX_UNKNOWN;
4864 tp->phy_flags &= ~TG3_PHYFLG_MDIX_STATE;
4865 tp->link_config.rmt_adv = 0;
4867 if (tp->phy_flags & TG3_PHYFLG_CAPACITIVE_COUPLING) {
4868 err = tg3_phy_auxctl_read(tp,
4869 MII_TG3_AUXCTL_SHDWSEL_MISCTEST,
4871 if (!err && !(val & (1 << 10))) {
4872 tg3_phy_auxctl_write(tp,
4873 MII_TG3_AUXCTL_SHDWSEL_MISCTEST,
4880 for (i = 0; i < 100; i++) {
4881 tg3_readphy(tp, MII_BMSR, &bmsr);
4882 if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
4883 (bmsr & BMSR_LSTATUS))
4888 if (bmsr & BMSR_LSTATUS) {
4891 tg3_readphy(tp, MII_TG3_AUX_STAT, &aux_stat);
4892 for (i = 0; i < 2000; i++) {
4894 if (!tg3_readphy(tp, MII_TG3_AUX_STAT, &aux_stat) &&
4899 tg3_aux_stat_to_speed_duplex(tp, aux_stat,
4904 for (i = 0; i < 200; i++) {
4905 tg3_readphy(tp, MII_BMCR, &bmcr);
4906 if (tg3_readphy(tp, MII_BMCR, &bmcr))
4908 if (bmcr && bmcr != 0x7fff)
4916 tp->link_config.active_speed = current_speed;
4917 tp->link_config.active_duplex = current_duplex;
4919 if (tp->link_config.autoneg == AUTONEG_ENABLE) {
4920 bool eee_config_ok = tg3_phy_eee_config_ok(tp);
4922 if ((bmcr & BMCR_ANENABLE) &&
4924 tg3_phy_copper_an_config_ok(tp, &lcl_adv) &&
4925 tg3_phy_copper_fetch_rmtadv(tp, &rmt_adv))
4926 current_link_up = true;
4928 /* EEE settings changes take effect only after a phy
4929 * reset. If we have skipped a reset due to Link Flap
4930 * Avoidance being enabled, do it now.
4932 if (!eee_config_ok &&
4933 (tp->phy_flags & TG3_PHYFLG_KEEP_LINK_ON_PWRDN) &&
4939 if (!(bmcr & BMCR_ANENABLE) &&
4940 tp->link_config.speed == current_speed &&
4941 tp->link_config.duplex == current_duplex) {
4942 current_link_up = true;
4946 if (current_link_up &&
4947 tp->link_config.active_duplex == DUPLEX_FULL) {
4950 if (tp->phy_flags & TG3_PHYFLG_IS_FET) {
4951 reg = MII_TG3_FET_GEN_STAT;
4952 bit = MII_TG3_FET_GEN_STAT_MDIXSTAT;
4954 reg = MII_TG3_EXT_STAT;
4955 bit = MII_TG3_EXT_STAT_MDIX;
4958 if (!tg3_readphy(tp, reg, &val) && (val & bit))
4959 tp->phy_flags |= TG3_PHYFLG_MDIX_STATE;
4961 tg3_setup_flow_control(tp, lcl_adv, rmt_adv);
4966 if (!current_link_up || (tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER)) {
4967 tg3_phy_copper_begin(tp);
4969 if (tg3_flag(tp, ROBOSWITCH)) {
4970 current_link_up = true;
4971 /* FIXME: when BCM5325 switch is used use 100 MBit/s */
4972 current_speed = SPEED_1000;
4973 current_duplex = DUPLEX_FULL;
4974 tp->link_config.active_speed = current_speed;
4975 tp->link_config.active_duplex = current_duplex;
4978 tg3_readphy(tp, MII_BMSR, &bmsr);
4979 if ((!tg3_readphy(tp, MII_BMSR, &bmsr) && (bmsr & BMSR_LSTATUS)) ||
4980 (tp->mac_mode & MAC_MODE_PORT_INT_LPBACK))
4981 current_link_up = true;
4984 tp->mac_mode &= ~MAC_MODE_PORT_MODE_MASK;
4985 if (current_link_up) {
4986 if (tp->link_config.active_speed == SPEED_100 ||
4987 tp->link_config.active_speed == SPEED_10)
4988 tp->mac_mode |= MAC_MODE_PORT_MODE_MII;
4990 tp->mac_mode |= MAC_MODE_PORT_MODE_GMII;
4991 } else if (tp->phy_flags & TG3_PHYFLG_IS_FET)
4992 tp->mac_mode |= MAC_MODE_PORT_MODE_MII;
4994 tp->mac_mode |= MAC_MODE_PORT_MODE_GMII;
4996 /* In order for the 5750 core in BCM4785 chip to work properly
4997 * in RGMII mode, the Led Control Register must be set up.
4999 if (tg3_flag(tp, RGMII_MODE)) {
5000 u32 led_ctrl = tr32(MAC_LED_CTRL);
5001 led_ctrl &= ~(LED_CTRL_1000MBPS_ON | LED_CTRL_100MBPS_ON);
5003 if (tp->link_config.active_speed == SPEED_10)
5004 led_ctrl |= LED_CTRL_LNKLED_OVERRIDE;
5005 else if (tp->link_config.active_speed == SPEED_100)
5006 led_ctrl |= (LED_CTRL_LNKLED_OVERRIDE |
5007 LED_CTRL_100MBPS_ON);
5008 else if (tp->link_config.active_speed == SPEED_1000)
5009 led_ctrl |= (LED_CTRL_LNKLED_OVERRIDE |
5010 LED_CTRL_1000MBPS_ON);
5012 tw32(MAC_LED_CTRL, led_ctrl);
5016 tp->mac_mode &= ~MAC_MODE_HALF_DUPLEX;
5017 if (tp->link_config.active_duplex == DUPLEX_HALF)
5018 tp->mac_mode |= MAC_MODE_HALF_DUPLEX;
5020 if (tg3_asic_rev(tp) == ASIC_REV_5700) {
5021 if (current_link_up &&
5022 tg3_5700_link_polarity(tp, tp->link_config.active_speed))
5023 tp->mac_mode |= MAC_MODE_LINK_POLARITY;
5025 tp->mac_mode &= ~MAC_MODE_LINK_POLARITY;
5028 /* ??? Without this setting Netgear GA302T PHY does not
5029 * ??? send/receive packets...
5031 if ((tp->phy_id & TG3_PHY_ID_MASK) == TG3_PHY_ID_BCM5411 &&
5032 tg3_chip_rev_id(tp) == CHIPREV_ID_5700_ALTIMA) {
5033 tp->mi_mode |= MAC_MI_MODE_AUTO_POLL;
5034 tw32_f(MAC_MI_MODE, tp->mi_mode);
5038 tw32_f(MAC_MODE, tp->mac_mode);
5041 tg3_phy_eee_adjust(tp, current_link_up);
5043 if (tg3_flag(tp, USE_LINKCHG_REG)) {
5044 /* Polled via timer. */
5045 tw32_f(MAC_EVENT, 0);
5047 tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
5051 if (tg3_asic_rev(tp) == ASIC_REV_5700 &&
5053 tp->link_config.active_speed == SPEED_1000 &&
5054 (tg3_flag(tp, PCIX_MODE) || tg3_flag(tp, PCI_HIGH_SPEED))) {
5057 (MAC_STATUS_SYNC_CHANGED |
5058 MAC_STATUS_CFG_CHANGED));
5061 NIC_SRAM_FIRMWARE_MBOX,
5062 NIC_SRAM_FIRMWARE_MBOX_MAGIC2);
5065 /* Prevent send BD corruption. */
5066 if (tg3_flag(tp, CLKREQ_BUG)) {
5067 if (tp->link_config.active_speed == SPEED_100 ||
5068 tp->link_config.active_speed == SPEED_10)
5069 pcie_capability_clear_word(tp->pdev, PCI_EXP_LNKCTL,
5070 PCI_EXP_LNKCTL_CLKREQ_EN);
5072 pcie_capability_set_word(tp->pdev, PCI_EXP_LNKCTL,
5073 PCI_EXP_LNKCTL_CLKREQ_EN);
5076 tg3_test_and_report_link_chg(tp, current_link_up);
5081 struct tg3_fiber_aneginfo {
5083 #define ANEG_STATE_UNKNOWN 0
5084 #define ANEG_STATE_AN_ENABLE 1
5085 #define ANEG_STATE_RESTART_INIT 2
5086 #define ANEG_STATE_RESTART 3
5087 #define ANEG_STATE_DISABLE_LINK_OK 4
5088 #define ANEG_STATE_ABILITY_DETECT_INIT 5
5089 #define ANEG_STATE_ABILITY_DETECT 6
5090 #define ANEG_STATE_ACK_DETECT_INIT 7
5091 #define ANEG_STATE_ACK_DETECT 8
5092 #define ANEG_STATE_COMPLETE_ACK_INIT 9
5093 #define ANEG_STATE_COMPLETE_ACK 10
5094 #define ANEG_STATE_IDLE_DETECT_INIT 11
5095 #define ANEG_STATE_IDLE_DETECT 12
5096 #define ANEG_STATE_LINK_OK 13
5097 #define ANEG_STATE_NEXT_PAGE_WAIT_INIT 14
5098 #define ANEG_STATE_NEXT_PAGE_WAIT 15
5101 #define MR_AN_ENABLE 0x00000001
5102 #define MR_RESTART_AN 0x00000002
5103 #define MR_AN_COMPLETE 0x00000004
5104 #define MR_PAGE_RX 0x00000008
5105 #define MR_NP_LOADED 0x00000010
5106 #define MR_TOGGLE_TX 0x00000020
5107 #define MR_LP_ADV_FULL_DUPLEX 0x00000040
5108 #define MR_LP_ADV_HALF_DUPLEX 0x00000080
5109 #define MR_LP_ADV_SYM_PAUSE 0x00000100
5110 #define MR_LP_ADV_ASYM_PAUSE 0x00000200
5111 #define MR_LP_ADV_REMOTE_FAULT1 0x00000400
5112 #define MR_LP_ADV_REMOTE_FAULT2 0x00000800
5113 #define MR_LP_ADV_NEXT_PAGE 0x00001000
5114 #define MR_TOGGLE_RX 0x00002000
5115 #define MR_NP_RX 0x00004000
5117 #define MR_LINK_OK 0x80000000
5119 unsigned long link_time, cur_time;
5121 u32 ability_match_cfg;
5122 int ability_match_count;
5124 char ability_match, idle_match, ack_match;
5126 u32 txconfig, rxconfig;
5127 #define ANEG_CFG_NP 0x00000080
5128 #define ANEG_CFG_ACK 0x00000040
5129 #define ANEG_CFG_RF2 0x00000020
5130 #define ANEG_CFG_RF1 0x00000010
5131 #define ANEG_CFG_PS2 0x00000001
5132 #define ANEG_CFG_PS1 0x00008000
5133 #define ANEG_CFG_HD 0x00004000
5134 #define ANEG_CFG_FD 0x00002000
5135 #define ANEG_CFG_INVAL 0x00001f06
5140 #define ANEG_TIMER_ENAB 2
5141 #define ANEG_FAILED -1
5143 #define ANEG_STATE_SETTLE_TIME 10000
5145 static int tg3_fiber_aneg_smachine(struct tg3 *tp,
5146 struct tg3_fiber_aneginfo *ap)
5149 unsigned long delta;
5153 if (ap->state == ANEG_STATE_UNKNOWN) {
5157 ap->ability_match_cfg = 0;
5158 ap->ability_match_count = 0;
5159 ap->ability_match = 0;
5165 if (tr32(MAC_STATUS) & MAC_STATUS_RCVD_CFG) {
5166 rx_cfg_reg = tr32(MAC_RX_AUTO_NEG);
5168 if (rx_cfg_reg != ap->ability_match_cfg) {
5169 ap->ability_match_cfg = rx_cfg_reg;
5170 ap->ability_match = 0;
5171 ap->ability_match_count = 0;
5173 if (++ap->ability_match_count > 1) {
5174 ap->ability_match = 1;
5175 ap->ability_match_cfg = rx_cfg_reg;
5178 if (rx_cfg_reg & ANEG_CFG_ACK)
5186 ap->ability_match_cfg = 0;
5187 ap->ability_match_count = 0;
5188 ap->ability_match = 0;
5194 ap->rxconfig = rx_cfg_reg;
5197 switch (ap->state) {
5198 case ANEG_STATE_UNKNOWN:
5199 if (ap->flags & (MR_AN_ENABLE | MR_RESTART_AN))
5200 ap->state = ANEG_STATE_AN_ENABLE;
5203 case ANEG_STATE_AN_ENABLE:
5204 ap->flags &= ~(MR_AN_COMPLETE | MR_PAGE_RX);
5205 if (ap->flags & MR_AN_ENABLE) {
5208 ap->ability_match_cfg = 0;
5209 ap->ability_match_count = 0;
5210 ap->ability_match = 0;
5214 ap->state = ANEG_STATE_RESTART_INIT;
5216 ap->state = ANEG_STATE_DISABLE_LINK_OK;
5220 case ANEG_STATE_RESTART_INIT:
5221 ap->link_time = ap->cur_time;
5222 ap->flags &= ~(MR_NP_LOADED);
5224 tw32(MAC_TX_AUTO_NEG, 0);
5225 tp->mac_mode |= MAC_MODE_SEND_CONFIGS;
5226 tw32_f(MAC_MODE, tp->mac_mode);
5229 ret = ANEG_TIMER_ENAB;
5230 ap->state = ANEG_STATE_RESTART;
5233 case ANEG_STATE_RESTART:
5234 delta = ap->cur_time - ap->link_time;
5235 if (delta > ANEG_STATE_SETTLE_TIME)
5236 ap->state = ANEG_STATE_ABILITY_DETECT_INIT;
5238 ret = ANEG_TIMER_ENAB;
5241 case ANEG_STATE_DISABLE_LINK_OK:
5245 case ANEG_STATE_ABILITY_DETECT_INIT:
5246 ap->flags &= ~(MR_TOGGLE_TX);
5247 ap->txconfig = ANEG_CFG_FD;
5248 flowctrl = tg3_advert_flowctrl_1000X(tp->link_config.flowctrl);
5249 if (flowctrl & ADVERTISE_1000XPAUSE)
5250 ap->txconfig |= ANEG_CFG_PS1;
5251 if (flowctrl & ADVERTISE_1000XPSE_ASYM)
5252 ap->txconfig |= ANEG_CFG_PS2;
5253 tw32(MAC_TX_AUTO_NEG, ap->txconfig);
5254 tp->mac_mode |= MAC_MODE_SEND_CONFIGS;
5255 tw32_f(MAC_MODE, tp->mac_mode);
5258 ap->state = ANEG_STATE_ABILITY_DETECT;
5261 case ANEG_STATE_ABILITY_DETECT:
5262 if (ap->ability_match != 0 && ap->rxconfig != 0)
5263 ap->state = ANEG_STATE_ACK_DETECT_INIT;
5266 case ANEG_STATE_ACK_DETECT_INIT:
5267 ap->txconfig |= ANEG_CFG_ACK;
5268 tw32(MAC_TX_AUTO_NEG, ap->txconfig);
5269 tp->mac_mode |= MAC_MODE_SEND_CONFIGS;
5270 tw32_f(MAC_MODE, tp->mac_mode);
5273 ap->state = ANEG_STATE_ACK_DETECT;
5276 case ANEG_STATE_ACK_DETECT:
5277 if (ap->ack_match != 0) {
5278 if ((ap->rxconfig & ~ANEG_CFG_ACK) ==
5279 (ap->ability_match_cfg & ~ANEG_CFG_ACK)) {
5280 ap->state = ANEG_STATE_COMPLETE_ACK_INIT;
5282 ap->state = ANEG_STATE_AN_ENABLE;
5284 } else if (ap->ability_match != 0 &&
5285 ap->rxconfig == 0) {
5286 ap->state = ANEG_STATE_AN_ENABLE;
5290 case ANEG_STATE_COMPLETE_ACK_INIT:
5291 if (ap->rxconfig & ANEG_CFG_INVAL) {
5295 ap->flags &= ~(MR_LP_ADV_FULL_DUPLEX |
5296 MR_LP_ADV_HALF_DUPLEX |
5297 MR_LP_ADV_SYM_PAUSE |
5298 MR_LP_ADV_ASYM_PAUSE |
5299 MR_LP_ADV_REMOTE_FAULT1 |
5300 MR_LP_ADV_REMOTE_FAULT2 |
5301 MR_LP_ADV_NEXT_PAGE |
5304 if (ap->rxconfig & ANEG_CFG_FD)
5305 ap->flags |= MR_LP_ADV_FULL_DUPLEX;
5306 if (ap->rxconfig & ANEG_CFG_HD)
5307 ap->flags |= MR_LP_ADV_HALF_DUPLEX;
5308 if (ap->rxconfig & ANEG_CFG_PS1)
5309 ap->flags |= MR_LP_ADV_SYM_PAUSE;
5310 if (ap->rxconfig & ANEG_CFG_PS2)
5311 ap->flags |= MR_LP_ADV_ASYM_PAUSE;
5312 if (ap->rxconfig & ANEG_CFG_RF1)
5313 ap->flags |= MR_LP_ADV_REMOTE_FAULT1;
5314 if (ap->rxconfig & ANEG_CFG_RF2)
5315 ap->flags |= MR_LP_ADV_REMOTE_FAULT2;
5316 if (ap->rxconfig & ANEG_CFG_NP)
5317 ap->flags |= MR_LP_ADV_NEXT_PAGE;
5319 ap->link_time = ap->cur_time;
5321 ap->flags ^= (MR_TOGGLE_TX);
5322 if (ap->rxconfig & 0x0008)
5323 ap->flags |= MR_TOGGLE_RX;
5324 if (ap->rxconfig & ANEG_CFG_NP)
5325 ap->flags |= MR_NP_RX;
5326 ap->flags |= MR_PAGE_RX;
5328 ap->state = ANEG_STATE_COMPLETE_ACK;
5329 ret = ANEG_TIMER_ENAB;
5332 case ANEG_STATE_COMPLETE_ACK:
5333 if (ap->ability_match != 0 &&
5334 ap->rxconfig == 0) {
5335 ap->state = ANEG_STATE_AN_ENABLE;
5338 delta = ap->cur_time - ap->link_time;
5339 if (delta > ANEG_STATE_SETTLE_TIME) {
5340 if (!(ap->flags & (MR_LP_ADV_NEXT_PAGE))) {
5341 ap->state = ANEG_STATE_IDLE_DETECT_INIT;
5343 if ((ap->txconfig & ANEG_CFG_NP) == 0 &&
5344 !(ap->flags & MR_NP_RX)) {
5345 ap->state = ANEG_STATE_IDLE_DETECT_INIT;
5353 case ANEG_STATE_IDLE_DETECT_INIT:
5354 ap->link_time = ap->cur_time;
5355 tp->mac_mode &= ~MAC_MODE_SEND_CONFIGS;
5356 tw32_f(MAC_MODE, tp->mac_mode);
5359 ap->state = ANEG_STATE_IDLE_DETECT;
5360 ret = ANEG_TIMER_ENAB;
5363 case ANEG_STATE_IDLE_DETECT:
5364 if (ap->ability_match != 0 &&
5365 ap->rxconfig == 0) {
5366 ap->state = ANEG_STATE_AN_ENABLE;
5369 delta = ap->cur_time - ap->link_time;
5370 if (delta > ANEG_STATE_SETTLE_TIME) {
5371 /* XXX another gem from the Broadcom driver :( */
5372 ap->state = ANEG_STATE_LINK_OK;
5376 case ANEG_STATE_LINK_OK:
5377 ap->flags |= (MR_AN_COMPLETE | MR_LINK_OK);
5381 case ANEG_STATE_NEXT_PAGE_WAIT_INIT:
5382 /* ??? unimplemented */
5385 case ANEG_STATE_NEXT_PAGE_WAIT:
5386 /* ??? unimplemented */
5397 static int fiber_autoneg(struct tg3 *tp, u32 *txflags, u32 *rxflags)
5400 struct tg3_fiber_aneginfo aninfo;
5401 int status = ANEG_FAILED;
5405 tw32_f(MAC_TX_AUTO_NEG, 0);
5407 tmp = tp->mac_mode & ~MAC_MODE_PORT_MODE_MASK;
5408 tw32_f(MAC_MODE, tmp | MAC_MODE_PORT_MODE_GMII);
5411 tw32_f(MAC_MODE, tp->mac_mode | MAC_MODE_SEND_CONFIGS);
5414 memset(&aninfo, 0, sizeof(aninfo));
5415 aninfo.flags |= MR_AN_ENABLE;
5416 aninfo.state = ANEG_STATE_UNKNOWN;
5417 aninfo.cur_time = 0;
5419 while (++tick < 195000) {
5420 status = tg3_fiber_aneg_smachine(tp, &aninfo);
5421 if (status == ANEG_DONE || status == ANEG_FAILED)
5427 tp->mac_mode &= ~MAC_MODE_SEND_CONFIGS;
5428 tw32_f(MAC_MODE, tp->mac_mode);
5431 *txflags = aninfo.txconfig;
5432 *rxflags = aninfo.flags;
5434 if (status == ANEG_DONE &&
5435 (aninfo.flags & (MR_AN_COMPLETE | MR_LINK_OK |
5436 MR_LP_ADV_FULL_DUPLEX)))
5442 static void tg3_init_bcm8002(struct tg3 *tp)
5444 u32 mac_status = tr32(MAC_STATUS);
5447 /* Reset when initting first time or we have a link. */
5448 if (tg3_flag(tp, INIT_COMPLETE) &&
5449 !(mac_status & MAC_STATUS_PCS_SYNCED))
5452 /* Set PLL lock range. */
5453 tg3_writephy(tp, 0x16, 0x8007);
5456 tg3_writephy(tp, MII_BMCR, BMCR_RESET);
5458 /* Wait for reset to complete. */
5459 /* XXX schedule_timeout() ... */
5460 for (i = 0; i < 500; i++)
5463 /* Config mode; select PMA/Ch 1 regs. */
5464 tg3_writephy(tp, 0x10, 0x8411);
5466 /* Enable auto-lock and comdet, select txclk for tx. */
5467 tg3_writephy(tp, 0x11, 0x0a10);
5469 tg3_writephy(tp, 0x18, 0x00a0);
5470 tg3_writephy(tp, 0x16, 0x41ff);
5472 /* Assert and deassert POR. */
5473 tg3_writephy(tp, 0x13, 0x0400);
5475 tg3_writephy(tp, 0x13, 0x0000);
5477 tg3_writephy(tp, 0x11, 0x0a50);
5479 tg3_writephy(tp, 0x11, 0x0a10);
5481 /* Wait for signal to stabilize */
5482 /* XXX schedule_timeout() ... */
5483 for (i = 0; i < 15000; i++)
5486 /* Deselect the channel register so we can read the PHYID
5489 tg3_writephy(tp, 0x10, 0x8011);
5492 static bool tg3_setup_fiber_hw_autoneg(struct tg3 *tp, u32 mac_status)
5495 bool current_link_up;
5496 u32 sg_dig_ctrl, sg_dig_status;
5497 u32 serdes_cfg, expected_sg_dig_ctrl;
5498 int workaround, port_a;
5501 expected_sg_dig_ctrl = 0;
5504 current_link_up = false;
5506 if (tg3_chip_rev_id(tp) != CHIPREV_ID_5704_A0 &&
5507 tg3_chip_rev_id(tp) != CHIPREV_ID_5704_A1) {
5509 if (tr32(TG3PCI_DUAL_MAC_CTRL) & DUAL_MAC_CTRL_ID)
5512 /* preserve bits 0-11,13,14 for signal pre-emphasis */
5513 /* preserve bits 20-23 for voltage regulator */
5514 serdes_cfg = tr32(MAC_SERDES_CFG) & 0x00f06fff;
5517 sg_dig_ctrl = tr32(SG_DIG_CTRL);
5519 if (tp->link_config.autoneg != AUTONEG_ENABLE) {
5520 if (sg_dig_ctrl & SG_DIG_USING_HW_AUTONEG) {
5522 u32 val = serdes_cfg;
5528 tw32_f(MAC_SERDES_CFG, val);
5531 tw32_f(SG_DIG_CTRL, SG_DIG_COMMON_SETUP);
5533 if (mac_status & MAC_STATUS_PCS_SYNCED) {
5534 tg3_setup_flow_control(tp, 0, 0);
5535 current_link_up = true;
5540 /* Want auto-negotiation. */
5541 expected_sg_dig_ctrl = SG_DIG_USING_HW_AUTONEG | SG_DIG_COMMON_SETUP;
5543 flowctrl = tg3_advert_flowctrl_1000X(tp->link_config.flowctrl);
5544 if (flowctrl & ADVERTISE_1000XPAUSE)
5545 expected_sg_dig_ctrl |= SG_DIG_PAUSE_CAP;
5546 if (flowctrl & ADVERTISE_1000XPSE_ASYM)
5547 expected_sg_dig_ctrl |= SG_DIG_ASYM_PAUSE;
5549 if (sg_dig_ctrl != expected_sg_dig_ctrl) {
5550 if ((tp->phy_flags & TG3_PHYFLG_PARALLEL_DETECT) &&
5551 tp->serdes_counter &&
5552 ((mac_status & (MAC_STATUS_PCS_SYNCED |
5553 MAC_STATUS_RCVD_CFG)) ==
5554 MAC_STATUS_PCS_SYNCED)) {
5555 tp->serdes_counter--;
5556 current_link_up = true;
5561 tw32_f(MAC_SERDES_CFG, serdes_cfg | 0xc011000);
5562 tw32_f(SG_DIG_CTRL, expected_sg_dig_ctrl | SG_DIG_SOFT_RESET);
5564 tw32_f(SG_DIG_CTRL, expected_sg_dig_ctrl);
5566 tp->serdes_counter = SERDES_AN_TIMEOUT_5704S;
5567 tp->phy_flags &= ~TG3_PHYFLG_PARALLEL_DETECT;
5568 } else if (mac_status & (MAC_STATUS_PCS_SYNCED |
5569 MAC_STATUS_SIGNAL_DET)) {
5570 sg_dig_status = tr32(SG_DIG_STATUS);
5571 mac_status = tr32(MAC_STATUS);
5573 if ((sg_dig_status & SG_DIG_AUTONEG_COMPLETE) &&
5574 (mac_status & MAC_STATUS_PCS_SYNCED)) {
5575 u32 local_adv = 0, remote_adv = 0;
5577 if (sg_dig_ctrl & SG_DIG_PAUSE_CAP)
5578 local_adv |= ADVERTISE_1000XPAUSE;
5579 if (sg_dig_ctrl & SG_DIG_ASYM_PAUSE)
5580 local_adv |= ADVERTISE_1000XPSE_ASYM;
5582 if (sg_dig_status & SG_DIG_PARTNER_PAUSE_CAPABLE)
5583 remote_adv |= LPA_1000XPAUSE;
5584 if (sg_dig_status & SG_DIG_PARTNER_ASYM_PAUSE)
5585 remote_adv |= LPA_1000XPAUSE_ASYM;
5587 tp->link_config.rmt_adv =
5588 mii_adv_to_ethtool_adv_x(remote_adv);
5590 tg3_setup_flow_control(tp, local_adv, remote_adv);
5591 current_link_up = true;
5592 tp->serdes_counter = 0;
5593 tp->phy_flags &= ~TG3_PHYFLG_PARALLEL_DETECT;
5594 } else if (!(sg_dig_status & SG_DIG_AUTONEG_COMPLETE)) {
5595 if (tp->serdes_counter)
5596 tp->serdes_counter--;
5599 u32 val = serdes_cfg;
5606 tw32_f(MAC_SERDES_CFG, val);
5609 tw32_f(SG_DIG_CTRL, SG_DIG_COMMON_SETUP);
5612 /* Link parallel detection - link is up */
5613 /* only if we have PCS_SYNC and not */
5614 /* receiving config code words */
5615 mac_status = tr32(MAC_STATUS);
5616 if ((mac_status & MAC_STATUS_PCS_SYNCED) &&
5617 !(mac_status & MAC_STATUS_RCVD_CFG)) {
5618 tg3_setup_flow_control(tp, 0, 0);
5619 current_link_up = true;
5621 TG3_PHYFLG_PARALLEL_DETECT;
5622 tp->serdes_counter =
5623 SERDES_PARALLEL_DET_TIMEOUT;
5625 goto restart_autoneg;
5629 tp->serdes_counter = SERDES_AN_TIMEOUT_5704S;
5630 tp->phy_flags &= ~TG3_PHYFLG_PARALLEL_DETECT;
5634 return current_link_up;
5637 static bool tg3_setup_fiber_by_hand(struct tg3 *tp, u32 mac_status)
5639 bool current_link_up = false;
5641 if (!(mac_status & MAC_STATUS_PCS_SYNCED))
5644 if (tp->link_config.autoneg == AUTONEG_ENABLE) {
5645 u32 txflags, rxflags;
5648 if (fiber_autoneg(tp, &txflags, &rxflags)) {
5649 u32 local_adv = 0, remote_adv = 0;
5651 if (txflags & ANEG_CFG_PS1)
5652 local_adv |= ADVERTISE_1000XPAUSE;
5653 if (txflags & ANEG_CFG_PS2)
5654 local_adv |= ADVERTISE_1000XPSE_ASYM;
5656 if (rxflags & MR_LP_ADV_SYM_PAUSE)
5657 remote_adv |= LPA_1000XPAUSE;
5658 if (rxflags & MR_LP_ADV_ASYM_PAUSE)
5659 remote_adv |= LPA_1000XPAUSE_ASYM;
5661 tp->link_config.rmt_adv =
5662 mii_adv_to_ethtool_adv_x(remote_adv);
5664 tg3_setup_flow_control(tp, local_adv, remote_adv);
5666 current_link_up = true;
5668 for (i = 0; i < 30; i++) {
5671 (MAC_STATUS_SYNC_CHANGED |
5672 MAC_STATUS_CFG_CHANGED));
5674 if ((tr32(MAC_STATUS) &
5675 (MAC_STATUS_SYNC_CHANGED |
5676 MAC_STATUS_CFG_CHANGED)) == 0)
5680 mac_status = tr32(MAC_STATUS);
5681 if (!current_link_up &&
5682 (mac_status & MAC_STATUS_PCS_SYNCED) &&
5683 !(mac_status & MAC_STATUS_RCVD_CFG))
5684 current_link_up = true;
5686 tg3_setup_flow_control(tp, 0, 0);
5688 /* Forcing 1000FD link up. */
5689 current_link_up = true;
5691 tw32_f(MAC_MODE, (tp->mac_mode | MAC_MODE_SEND_CONFIGS));
5694 tw32_f(MAC_MODE, tp->mac_mode);
5699 return current_link_up;
5702 static int tg3_setup_fiber_phy(struct tg3 *tp, bool force_reset)
5705 u16 orig_active_speed;
5706 u8 orig_active_duplex;
5708 bool current_link_up;
5711 orig_pause_cfg = tp->link_config.active_flowctrl;
5712 orig_active_speed = tp->link_config.active_speed;
5713 orig_active_duplex = tp->link_config.active_duplex;
5715 if (!tg3_flag(tp, HW_AUTONEG) &&
5717 tg3_flag(tp, INIT_COMPLETE)) {
5718 mac_status = tr32(MAC_STATUS);
5719 mac_status &= (MAC_STATUS_PCS_SYNCED |
5720 MAC_STATUS_SIGNAL_DET |
5721 MAC_STATUS_CFG_CHANGED |
5722 MAC_STATUS_RCVD_CFG);
5723 if (mac_status == (MAC_STATUS_PCS_SYNCED |
5724 MAC_STATUS_SIGNAL_DET)) {
5725 tw32_f(MAC_STATUS, (MAC_STATUS_SYNC_CHANGED |
5726 MAC_STATUS_CFG_CHANGED));
5731 tw32_f(MAC_TX_AUTO_NEG, 0);
5733 tp->mac_mode &= ~(MAC_MODE_PORT_MODE_MASK | MAC_MODE_HALF_DUPLEX);
5734 tp->mac_mode |= MAC_MODE_PORT_MODE_TBI;
5735 tw32_f(MAC_MODE, tp->mac_mode);
5738 if (tp->phy_id == TG3_PHY_ID_BCM8002)
5739 tg3_init_bcm8002(tp);
5741 /* Enable link change event even when serdes polling. */
5742 tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
5745 current_link_up = false;
5746 tp->link_config.rmt_adv = 0;
5747 mac_status = tr32(MAC_STATUS);
5749 if (tg3_flag(tp, HW_AUTONEG))
5750 current_link_up = tg3_setup_fiber_hw_autoneg(tp, mac_status);
5752 current_link_up = tg3_setup_fiber_by_hand(tp, mac_status);
5754 tp->napi[0].hw_status->status =
5755 (SD_STATUS_UPDATED |
5756 (tp->napi[0].hw_status->status & ~SD_STATUS_LINK_CHG));
5758 for (i = 0; i < 100; i++) {
5759 tw32_f(MAC_STATUS, (MAC_STATUS_SYNC_CHANGED |
5760 MAC_STATUS_CFG_CHANGED));
5762 if ((tr32(MAC_STATUS) & (MAC_STATUS_SYNC_CHANGED |
5763 MAC_STATUS_CFG_CHANGED |
5764 MAC_STATUS_LNKSTATE_CHANGED)) == 0)
5768 mac_status = tr32(MAC_STATUS);
5769 if ((mac_status & MAC_STATUS_PCS_SYNCED) == 0) {
5770 current_link_up = false;
5771 if (tp->link_config.autoneg == AUTONEG_ENABLE &&
5772 tp->serdes_counter == 0) {
5773 tw32_f(MAC_MODE, (tp->mac_mode |
5774 MAC_MODE_SEND_CONFIGS));
5776 tw32_f(MAC_MODE, tp->mac_mode);
5780 if (current_link_up) {
5781 tp->link_config.active_speed = SPEED_1000;
5782 tp->link_config.active_duplex = DUPLEX_FULL;
5783 tw32(MAC_LED_CTRL, (tp->led_ctrl |
5784 LED_CTRL_LNKLED_OVERRIDE |
5785 LED_CTRL_1000MBPS_ON));
5787 tp->link_config.active_speed = SPEED_UNKNOWN;
5788 tp->link_config.active_duplex = DUPLEX_UNKNOWN;
5789 tw32(MAC_LED_CTRL, (tp->led_ctrl |
5790 LED_CTRL_LNKLED_OVERRIDE |
5791 LED_CTRL_TRAFFIC_OVERRIDE));
5794 if (!tg3_test_and_report_link_chg(tp, current_link_up)) {
5795 u32 now_pause_cfg = tp->link_config.active_flowctrl;
5796 if (orig_pause_cfg != now_pause_cfg ||
5797 orig_active_speed != tp->link_config.active_speed ||
5798 orig_active_duplex != tp->link_config.active_duplex)
5799 tg3_link_report(tp);
5805 static int tg3_setup_fiber_mii_phy(struct tg3 *tp, bool force_reset)
5809 u16 current_speed = SPEED_UNKNOWN;
5810 u8 current_duplex = DUPLEX_UNKNOWN;
5811 bool current_link_up = false;
5812 u32 local_adv, remote_adv, sgsr;
5814 if ((tg3_asic_rev(tp) == ASIC_REV_5719 ||
5815 tg3_asic_rev(tp) == ASIC_REV_5720) &&
5816 !tg3_readphy(tp, SERDES_TG3_1000X_STATUS, &sgsr) &&
5817 (sgsr & SERDES_TG3_SGMII_MODE)) {
5822 tp->mac_mode &= ~MAC_MODE_PORT_MODE_MASK;
5824 if (!(sgsr & SERDES_TG3_LINK_UP)) {
5825 tp->mac_mode |= MAC_MODE_PORT_MODE_GMII;
5827 current_link_up = true;
5828 if (sgsr & SERDES_TG3_SPEED_1000) {
5829 current_speed = SPEED_1000;
5830 tp->mac_mode |= MAC_MODE_PORT_MODE_GMII;
5831 } else if (sgsr & SERDES_TG3_SPEED_100) {
5832 current_speed = SPEED_100;
5833 tp->mac_mode |= MAC_MODE_PORT_MODE_MII;
5835 current_speed = SPEED_10;
5836 tp->mac_mode |= MAC_MODE_PORT_MODE_MII;
5839 if (sgsr & SERDES_TG3_FULL_DUPLEX)
5840 current_duplex = DUPLEX_FULL;
5842 current_duplex = DUPLEX_HALF;
5845 tw32_f(MAC_MODE, tp->mac_mode);
5848 tg3_clear_mac_status(tp);
5850 goto fiber_setup_done;
5853 tp->mac_mode |= MAC_MODE_PORT_MODE_GMII;
5854 tw32_f(MAC_MODE, tp->mac_mode);
5857 tg3_clear_mac_status(tp);
5862 tp->link_config.rmt_adv = 0;
5864 err |= tg3_readphy(tp, MII_BMSR, &bmsr);
5865 err |= tg3_readphy(tp, MII_BMSR, &bmsr);
5866 if (tg3_asic_rev(tp) == ASIC_REV_5714) {
5867 if (tr32(MAC_TX_STATUS) & TX_STATUS_LINK_UP)
5868 bmsr |= BMSR_LSTATUS;
5870 bmsr &= ~BMSR_LSTATUS;
5873 err |= tg3_readphy(tp, MII_BMCR, &bmcr);
5875 if ((tp->link_config.autoneg == AUTONEG_ENABLE) && !force_reset &&
5876 (tp->phy_flags & TG3_PHYFLG_PARALLEL_DETECT)) {
5877 /* do nothing, just check for link up at the end */
5878 } else if (tp->link_config.autoneg == AUTONEG_ENABLE) {
5881 err |= tg3_readphy(tp, MII_ADVERTISE, &adv);
5882 newadv = adv & ~(ADVERTISE_1000XFULL | ADVERTISE_1000XHALF |
5883 ADVERTISE_1000XPAUSE |
5884 ADVERTISE_1000XPSE_ASYM |
5887 newadv |= tg3_advert_flowctrl_1000X(tp->link_config.flowctrl);
5888 newadv |= ethtool_adv_to_mii_adv_x(tp->link_config.advertising);
5890 if ((newadv != adv) || !(bmcr & BMCR_ANENABLE)) {
5891 tg3_writephy(tp, MII_ADVERTISE, newadv);
5892 bmcr |= BMCR_ANENABLE | BMCR_ANRESTART;
5893 tg3_writephy(tp, MII_BMCR, bmcr);
5895 tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
5896 tp->serdes_counter = SERDES_AN_TIMEOUT_5714S;
5897 tp->phy_flags &= ~TG3_PHYFLG_PARALLEL_DETECT;
5904 bmcr &= ~BMCR_SPEED1000;
5905 new_bmcr = bmcr & ~(BMCR_ANENABLE | BMCR_FULLDPLX);
5907 if (tp->link_config.duplex == DUPLEX_FULL)
5908 new_bmcr |= BMCR_FULLDPLX;
5910 if (new_bmcr != bmcr) {
5911 /* BMCR_SPEED1000 is a reserved bit that needs
5912 * to be set on write.
5914 new_bmcr |= BMCR_SPEED1000;
5916 /* Force a linkdown */
5920 err |= tg3_readphy(tp, MII_ADVERTISE, &adv);
5921 adv &= ~(ADVERTISE_1000XFULL |
5922 ADVERTISE_1000XHALF |
5924 tg3_writephy(tp, MII_ADVERTISE, adv);
5925 tg3_writephy(tp, MII_BMCR, bmcr |
5929 tg3_carrier_off(tp);
5931 tg3_writephy(tp, MII_BMCR, new_bmcr);
5933 err |= tg3_readphy(tp, MII_BMSR, &bmsr);
5934 err |= tg3_readphy(tp, MII_BMSR, &bmsr);
5935 if (tg3_asic_rev(tp) == ASIC_REV_5714) {
5936 if (tr32(MAC_TX_STATUS) & TX_STATUS_LINK_UP)
5937 bmsr |= BMSR_LSTATUS;
5939 bmsr &= ~BMSR_LSTATUS;
5941 tp->phy_flags &= ~TG3_PHYFLG_PARALLEL_DETECT;
5945 if (bmsr & BMSR_LSTATUS) {
5946 current_speed = SPEED_1000;
5947 current_link_up = true;
5948 if (bmcr & BMCR_FULLDPLX)
5949 current_duplex = DUPLEX_FULL;
5951 current_duplex = DUPLEX_HALF;
5956 if (bmcr & BMCR_ANENABLE) {
5959 err |= tg3_readphy(tp, MII_ADVERTISE, &local_adv);
5960 err |= tg3_readphy(tp, MII_LPA, &remote_adv);
5961 common = local_adv & remote_adv;
5962 if (common & (ADVERTISE_1000XHALF |
5963 ADVERTISE_1000XFULL)) {
5964 if (common & ADVERTISE_1000XFULL)
5965 current_duplex = DUPLEX_FULL;
5967 current_duplex = DUPLEX_HALF;
5969 tp->link_config.rmt_adv =
5970 mii_adv_to_ethtool_adv_x(remote_adv);
5971 } else if (!tg3_flag(tp, 5780_CLASS)) {
5972 /* Link is up via parallel detect */
5974 current_link_up = false;
5980 if (current_link_up && current_duplex == DUPLEX_FULL)
5981 tg3_setup_flow_control(tp, local_adv, remote_adv);
5983 tp->mac_mode &= ~MAC_MODE_HALF_DUPLEX;
5984 if (tp->link_config.active_duplex == DUPLEX_HALF)
5985 tp->mac_mode |= MAC_MODE_HALF_DUPLEX;
5987 tw32_f(MAC_MODE, tp->mac_mode);
5990 tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
5992 tp->link_config.active_speed = current_speed;
5993 tp->link_config.active_duplex = current_duplex;
5995 tg3_test_and_report_link_chg(tp, current_link_up);
5999 static void tg3_serdes_parallel_detect(struct tg3 *tp)
6001 if (tp->serdes_counter) {
6002 /* Give autoneg time to complete. */
6003 tp->serdes_counter--;
6008 (tp->link_config.autoneg == AUTONEG_ENABLE)) {
6011 tg3_readphy(tp, MII_BMCR, &bmcr);
6012 if (bmcr & BMCR_ANENABLE) {
6015 /* Select shadow register 0x1f */
6016 tg3_writephy(tp, MII_TG3_MISC_SHDW, 0x7c00);
6017 tg3_readphy(tp, MII_TG3_MISC_SHDW, &phy1);
6019 /* Select expansion interrupt status register */
6020 tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
6021 MII_TG3_DSP_EXP1_INT_STAT);
6022 tg3_readphy(tp, MII_TG3_DSP_RW_PORT, &phy2);
6023 tg3_readphy(tp, MII_TG3_DSP_RW_PORT, &phy2);
6025 if ((phy1 & 0x10) && !(phy2 & 0x20)) {
6026 /* We have signal detect and not receiving
6027 * config code words, link is up by parallel
6031 bmcr &= ~BMCR_ANENABLE;
6032 bmcr |= BMCR_SPEED1000 | BMCR_FULLDPLX;
6033 tg3_writephy(tp, MII_BMCR, bmcr);
6034 tp->phy_flags |= TG3_PHYFLG_PARALLEL_DETECT;
6037 } else if (tp->link_up &&
6038 (tp->link_config.autoneg == AUTONEG_ENABLE) &&
6039 (tp->phy_flags & TG3_PHYFLG_PARALLEL_DETECT)) {
6042 /* Select expansion interrupt status register */
6043 tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
6044 MII_TG3_DSP_EXP1_INT_STAT);
6045 tg3_readphy(tp, MII_TG3_DSP_RW_PORT, &phy2);
6049 /* Config code words received, turn on autoneg. */
6050 tg3_readphy(tp, MII_BMCR, &bmcr);
6051 tg3_writephy(tp, MII_BMCR, bmcr | BMCR_ANENABLE);
6053 tp->phy_flags &= ~TG3_PHYFLG_PARALLEL_DETECT;
6059 static int tg3_setup_phy(struct tg3 *tp, bool force_reset)
6064 if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES)
6065 err = tg3_setup_fiber_phy(tp, force_reset);
6066 else if (tp->phy_flags & TG3_PHYFLG_MII_SERDES)
6067 err = tg3_setup_fiber_mii_phy(tp, force_reset);
6069 err = tg3_setup_copper_phy(tp, force_reset);
6071 if (tg3_chip_rev(tp) == CHIPREV_5784_AX) {
6074 val = tr32(TG3_CPMU_CLCK_STAT) & CPMU_CLCK_STAT_MAC_CLCK_MASK;
6075 if (val == CPMU_CLCK_STAT_MAC_CLCK_62_5)
6077 else if (val == CPMU_CLCK_STAT_MAC_CLCK_6_25)
6082 val = tr32(GRC_MISC_CFG) & ~GRC_MISC_CFG_PRESCALAR_MASK;
6083 val |= (scale << GRC_MISC_CFG_PRESCALAR_SHIFT);
6084 tw32(GRC_MISC_CFG, val);
6087 val = (2 << TX_LENGTHS_IPG_CRS_SHIFT) |
6088 (6 << TX_LENGTHS_IPG_SHIFT);
6089 if (tg3_asic_rev(tp) == ASIC_REV_5720 ||
6090 tg3_asic_rev(tp) == ASIC_REV_5762)
6091 val |= tr32(MAC_TX_LENGTHS) &
6092 (TX_LENGTHS_JMB_FRM_LEN_MSK |
6093 TX_LENGTHS_CNT_DWN_VAL_MSK);
6095 if (tp->link_config.active_speed == SPEED_1000 &&
6096 tp->link_config.active_duplex == DUPLEX_HALF)
6097 tw32(MAC_TX_LENGTHS, val |
6098 (0xff << TX_LENGTHS_SLOT_TIME_SHIFT));
6100 tw32(MAC_TX_LENGTHS, val |
6101 (32 << TX_LENGTHS_SLOT_TIME_SHIFT));
6103 if (!tg3_flag(tp, 5705_PLUS)) {
6105 tw32(HOSTCC_STAT_COAL_TICKS,
6106 tp->coal.stats_block_coalesce_usecs);
6108 tw32(HOSTCC_STAT_COAL_TICKS, 0);
6112 if (tg3_flag(tp, ASPM_WORKAROUND)) {
6113 val = tr32(PCIE_PWR_MGMT_THRESH);
6115 val = (val & ~PCIE_PWR_MGMT_L1_THRESH_MSK) |
6118 val |= PCIE_PWR_MGMT_L1_THRESH_MSK;
6119 tw32(PCIE_PWR_MGMT_THRESH, val);
6125 /* tp->lock must be held */
6126 static u64 tg3_refclk_read(struct tg3 *tp)
6128 u64 stamp = tr32(TG3_EAV_REF_CLCK_LSB);
6129 return stamp | (u64)tr32(TG3_EAV_REF_CLCK_MSB) << 32;
6132 /* tp->lock must be held */
6133 static void tg3_refclk_write(struct tg3 *tp, u64 newval)
6135 u32 clock_ctl = tr32(TG3_EAV_REF_CLCK_CTL);
6137 tw32(TG3_EAV_REF_CLCK_CTL, clock_ctl | TG3_EAV_REF_CLCK_CTL_STOP);
6138 tw32(TG3_EAV_REF_CLCK_LSB, newval & 0xffffffff);
6139 tw32(TG3_EAV_REF_CLCK_MSB, newval >> 32);
6140 tw32_f(TG3_EAV_REF_CLCK_CTL, clock_ctl | TG3_EAV_REF_CLCK_CTL_RESUME);
6143 static inline void tg3_full_lock(struct tg3 *tp, int irq_sync);
6144 static inline void tg3_full_unlock(struct tg3 *tp);
6145 static int tg3_get_ts_info(struct net_device *dev, struct ethtool_ts_info *info)
6147 struct tg3 *tp = netdev_priv(dev);
6149 info->so_timestamping = SOF_TIMESTAMPING_TX_SOFTWARE |
6150 SOF_TIMESTAMPING_RX_SOFTWARE |
6151 SOF_TIMESTAMPING_SOFTWARE;
6153 if (tg3_flag(tp, PTP_CAPABLE)) {
6154 info->so_timestamping |= SOF_TIMESTAMPING_TX_HARDWARE |
6155 SOF_TIMESTAMPING_RX_HARDWARE |
6156 SOF_TIMESTAMPING_RAW_HARDWARE;
6160 info->phc_index = ptp_clock_index(tp->ptp_clock);
6162 info->phc_index = -1;
6164 info->tx_types = (1 << HWTSTAMP_TX_OFF) | (1 << HWTSTAMP_TX_ON);
6166 info->rx_filters = (1 << HWTSTAMP_FILTER_NONE) |
6167 (1 << HWTSTAMP_FILTER_PTP_V1_L4_EVENT) |
6168 (1 << HWTSTAMP_FILTER_PTP_V2_L2_EVENT) |
6169 (1 << HWTSTAMP_FILTER_PTP_V2_L4_EVENT);
6173 static int tg3_ptp_adjfreq(struct ptp_clock_info *ptp, s32 ppb)
6175 struct tg3 *tp = container_of(ptp, struct tg3, ptp_info);
6176 bool neg_adj = false;
6184 /* Frequency adjustment is performed using hardware with a 24 bit
6185 * accumulator and a programmable correction value. On each clk, the
6186 * correction value gets added to the accumulator and when it
6187 * overflows, the time counter is incremented/decremented.
6189 * So conversion from ppb to correction value is
6190 * ppb * (1 << 24) / 1000000000
6192 correction = div_u64((u64)ppb * (1 << 24), 1000000000ULL) &
6193 TG3_EAV_REF_CLK_CORRECT_MASK;
6195 tg3_full_lock(tp, 0);
6198 tw32(TG3_EAV_REF_CLK_CORRECT_CTL,
6199 TG3_EAV_REF_CLK_CORRECT_EN |
6200 (neg_adj ? TG3_EAV_REF_CLK_CORRECT_NEG : 0) | correction);
6202 tw32(TG3_EAV_REF_CLK_CORRECT_CTL, 0);
6204 tg3_full_unlock(tp);
6209 static int tg3_ptp_adjtime(struct ptp_clock_info *ptp, s64 delta)
6211 struct tg3 *tp = container_of(ptp, struct tg3, ptp_info);
6213 tg3_full_lock(tp, 0);
6214 tp->ptp_adjust += delta;
6215 tg3_full_unlock(tp);
6220 static int tg3_ptp_gettime(struct ptp_clock_info *ptp, struct timespec *ts)
6224 struct tg3 *tp = container_of(ptp, struct tg3, ptp_info);
6226 tg3_full_lock(tp, 0);
6227 ns = tg3_refclk_read(tp);
6228 ns += tp->ptp_adjust;
6229 tg3_full_unlock(tp);
6231 ts->tv_sec = div_u64_rem(ns, 1000000000, &remainder);
6232 ts->tv_nsec = remainder;
6237 static int tg3_ptp_settime(struct ptp_clock_info *ptp,
6238 const struct timespec *ts)
6241 struct tg3 *tp = container_of(ptp, struct tg3, ptp_info);
6243 ns = timespec_to_ns(ts);
6245 tg3_full_lock(tp, 0);
6246 tg3_refclk_write(tp, ns);
6248 tg3_full_unlock(tp);
6253 static int tg3_ptp_enable(struct ptp_clock_info *ptp,
6254 struct ptp_clock_request *rq, int on)
6256 struct tg3 *tp = container_of(ptp, struct tg3, ptp_info);
6261 case PTP_CLK_REQ_PEROUT:
6262 if (rq->perout.index != 0)
6265 tg3_full_lock(tp, 0);
6266 clock_ctl = tr32(TG3_EAV_REF_CLCK_CTL);
6267 clock_ctl &= ~TG3_EAV_CTL_TSYNC_GPIO_MASK;
6272 nsec = rq->perout.start.sec * 1000000000ULL +
6273 rq->perout.start.nsec;
6275 if (rq->perout.period.sec || rq->perout.period.nsec) {
6276 netdev_warn(tp->dev,
6277 "Device supports only a one-shot timesync output, period must be 0\n");
6282 if (nsec & (1ULL << 63)) {
6283 netdev_warn(tp->dev,
6284 "Start value (nsec) is over limit. Maximum size of start is only 63 bits\n");
6289 tw32(TG3_EAV_WATCHDOG0_LSB, (nsec & 0xffffffff));
6290 tw32(TG3_EAV_WATCHDOG0_MSB,
6291 TG3_EAV_WATCHDOG0_EN |
6292 ((nsec >> 32) & TG3_EAV_WATCHDOG_MSB_MASK));
6294 tw32(TG3_EAV_REF_CLCK_CTL,
6295 clock_ctl | TG3_EAV_CTL_TSYNC_WDOG0);
6297 tw32(TG3_EAV_WATCHDOG0_MSB, 0);
6298 tw32(TG3_EAV_REF_CLCK_CTL, clock_ctl);
6302 tg3_full_unlock(tp);
6312 static const struct ptp_clock_info tg3_ptp_caps = {
6313 .owner = THIS_MODULE,
6314 .name = "tg3 clock",
6315 .max_adj = 250000000,
6321 .adjfreq = tg3_ptp_adjfreq,
6322 .adjtime = tg3_ptp_adjtime,
6323 .gettime = tg3_ptp_gettime,
6324 .settime = tg3_ptp_settime,
6325 .enable = tg3_ptp_enable,
6328 static void tg3_hwclock_to_timestamp(struct tg3 *tp, u64 hwclock,
6329 struct skb_shared_hwtstamps *timestamp)
6331 memset(timestamp, 0, sizeof(struct skb_shared_hwtstamps));
6332 timestamp->hwtstamp = ns_to_ktime((hwclock & TG3_TSTAMP_MASK) +
6336 /* tp->lock must be held */
6337 static void tg3_ptp_init(struct tg3 *tp)
6339 if (!tg3_flag(tp, PTP_CAPABLE))
6342 /* Initialize the hardware clock to the system time. */
6343 tg3_refclk_write(tp, ktime_to_ns(ktime_get_real()));
6345 tp->ptp_info = tg3_ptp_caps;
6348 /* tp->lock must be held */
6349 static void tg3_ptp_resume(struct tg3 *tp)
6351 if (!tg3_flag(tp, PTP_CAPABLE))
6354 tg3_refclk_write(tp, ktime_to_ns(ktime_get_real()) + tp->ptp_adjust);
6358 static void tg3_ptp_fini(struct tg3 *tp)
6360 if (!tg3_flag(tp, PTP_CAPABLE) || !tp->ptp_clock)
6363 ptp_clock_unregister(tp->ptp_clock);
6364 tp->ptp_clock = NULL;
6368 static inline int tg3_irq_sync(struct tg3 *tp)
6370 return tp->irq_sync;
6373 static inline void tg3_rd32_loop(struct tg3 *tp, u32 *dst, u32 off, u32 len)
6377 dst = (u32 *)((u8 *)dst + off);
6378 for (i = 0; i < len; i += sizeof(u32))
6379 *dst++ = tr32(off + i);
6382 static void tg3_dump_legacy_regs(struct tg3 *tp, u32 *regs)
6384 tg3_rd32_loop(tp, regs, TG3PCI_VENDOR, 0xb0);
6385 tg3_rd32_loop(tp, regs, MAILBOX_INTERRUPT_0, 0x200);
6386 tg3_rd32_loop(tp, regs, MAC_MODE, 0x4f0);
6387 tg3_rd32_loop(tp, regs, SNDDATAI_MODE, 0xe0);
6388 tg3_rd32_loop(tp, regs, SNDDATAC_MODE, 0x04);
6389 tg3_rd32_loop(tp, regs, SNDBDS_MODE, 0x80);
6390 tg3_rd32_loop(tp, regs, SNDBDI_MODE, 0x48);
6391 tg3_rd32_loop(tp, regs, SNDBDC_MODE, 0x04);
6392 tg3_rd32_loop(tp, regs, RCVLPC_MODE, 0x20);
6393 tg3_rd32_loop(tp, regs, RCVLPC_SELLST_BASE, 0x15c);
6394 tg3_rd32_loop(tp, regs, RCVDBDI_MODE, 0x0c);
6395 tg3_rd32_loop(tp, regs, RCVDBDI_JUMBO_BD, 0x3c);
6396 tg3_rd32_loop(tp, regs, RCVDBDI_BD_PROD_IDX_0, 0x44);
6397 tg3_rd32_loop(tp, regs, RCVDCC_MODE, 0x04);
6398 tg3_rd32_loop(tp, regs, RCVBDI_MODE, 0x20);
6399 tg3_rd32_loop(tp, regs, RCVCC_MODE, 0x14);
6400 tg3_rd32_loop(tp, regs, RCVLSC_MODE, 0x08);
6401 tg3_rd32_loop(tp, regs, MBFREE_MODE, 0x08);
6402 tg3_rd32_loop(tp, regs, HOSTCC_MODE, 0x100);
6404 if (tg3_flag(tp, SUPPORT_MSIX))
6405 tg3_rd32_loop(tp, regs, HOSTCC_RXCOL_TICKS_VEC1, 0x180);
6407 tg3_rd32_loop(tp, regs, MEMARB_MODE, 0x10);
6408 tg3_rd32_loop(tp, regs, BUFMGR_MODE, 0x58);
6409 tg3_rd32_loop(tp, regs, RDMAC_MODE, 0x08);
6410 tg3_rd32_loop(tp, regs, WDMAC_MODE, 0x08);
6411 tg3_rd32_loop(tp, regs, RX_CPU_MODE, 0x04);
6412 tg3_rd32_loop(tp, regs, RX_CPU_STATE, 0x04);
6413 tg3_rd32_loop(tp, regs, RX_CPU_PGMCTR, 0x04);
6414 tg3_rd32_loop(tp, regs, RX_CPU_HWBKPT, 0x04);
6416 if (!tg3_flag(tp, 5705_PLUS)) {
6417 tg3_rd32_loop(tp, regs, TX_CPU_MODE, 0x04);
6418 tg3_rd32_loop(tp, regs, TX_CPU_STATE, 0x04);
6419 tg3_rd32_loop(tp, regs, TX_CPU_PGMCTR, 0x04);
6422 tg3_rd32_loop(tp, regs, GRCMBOX_INTERRUPT_0, 0x110);
6423 tg3_rd32_loop(tp, regs, FTQ_RESET, 0x120);
6424 tg3_rd32_loop(tp, regs, MSGINT_MODE, 0x0c);
6425 tg3_rd32_loop(tp, regs, DMAC_MODE, 0x04);
6426 tg3_rd32_loop(tp, regs, GRC_MODE, 0x4c);
6428 if (tg3_flag(tp, NVRAM))
6429 tg3_rd32_loop(tp, regs, NVRAM_CMD, 0x24);
6432 static void tg3_dump_state(struct tg3 *tp)
6437 regs = kzalloc(TG3_REG_BLK_SIZE, GFP_ATOMIC);
6441 if (tg3_flag(tp, PCI_EXPRESS)) {
6442 /* Read up to but not including private PCI registers */
6443 for (i = 0; i < TG3_PCIE_TLDLPL_PORT; i += sizeof(u32))
6444 regs[i / sizeof(u32)] = tr32(i);
6446 tg3_dump_legacy_regs(tp, regs);
6448 for (i = 0; i < TG3_REG_BLK_SIZE / sizeof(u32); i += 4) {
6449 if (!regs[i + 0] && !regs[i + 1] &&
6450 !regs[i + 2] && !regs[i + 3])
6453 netdev_err(tp->dev, "0x%08x: 0x%08x, 0x%08x, 0x%08x, 0x%08x\n",
6455 regs[i + 0], regs[i + 1], regs[i + 2], regs[i + 3]);
6460 for (i = 0; i < tp->irq_cnt; i++) {
6461 struct tg3_napi *tnapi = &tp->napi[i];
6463 /* SW status block */
6465 "%d: Host status block [%08x:%08x:(%04x:%04x:%04x):(%04x:%04x)]\n",
6467 tnapi->hw_status->status,
6468 tnapi->hw_status->status_tag,
6469 tnapi->hw_status->rx_jumbo_consumer,
6470 tnapi->hw_status->rx_consumer,
6471 tnapi->hw_status->rx_mini_consumer,
6472 tnapi->hw_status->idx[0].rx_producer,
6473 tnapi->hw_status->idx[0].tx_consumer);
6476 "%d: NAPI info [%08x:%08x:(%04x:%04x:%04x):%04x:(%04x:%04x:%04x:%04x)]\n",
6478 tnapi->last_tag, tnapi->last_irq_tag,
6479 tnapi->tx_prod, tnapi->tx_cons, tnapi->tx_pending,
6481 tnapi->prodring.rx_std_prod_idx,
6482 tnapi->prodring.rx_std_cons_idx,
6483 tnapi->prodring.rx_jmb_prod_idx,
6484 tnapi->prodring.rx_jmb_cons_idx);
6488 /* This is called whenever we suspect that the system chipset is re-
6489 * ordering the sequence of MMIO to the tx send mailbox. The symptom
6490 * is bogus tx completions. We try to recover by setting the
6491 * TG3_FLAG_MBOX_WRITE_REORDER flag and resetting the chip later
6494 static void tg3_tx_recover(struct tg3 *tp)
6496 BUG_ON(tg3_flag(tp, MBOX_WRITE_REORDER) ||
6497 tp->write32_tx_mbox == tg3_write_indirect_mbox);
6499 netdev_warn(tp->dev,
6500 "The system may be re-ordering memory-mapped I/O "
6501 "cycles to the network device, attempting to recover. "
6502 "Please report the problem to the driver maintainer "
6503 "and include system chipset information.\n");
6505 tg3_flag_set(tp, TX_RECOVERY_PENDING);
6508 static inline u32 tg3_tx_avail(struct tg3_napi *tnapi)
6510 /* Tell compiler to fetch tx indices from memory. */
6512 return tnapi->tx_pending -
6513 ((tnapi->tx_prod - tnapi->tx_cons) & (TG3_TX_RING_SIZE - 1));
6516 /* Tigon3 never reports partial packet sends. So we do not
6517 * need special logic to handle SKBs that have not had all
6518 * of their frags sent yet, like SunGEM does.
6520 static void tg3_tx(struct tg3_napi *tnapi)
6522 struct tg3 *tp = tnapi->tp;
6523 u32 hw_idx = tnapi->hw_status->idx[0].tx_consumer;
6524 u32 sw_idx = tnapi->tx_cons;
6525 struct netdev_queue *txq;
6526 int index = tnapi - tp->napi;
6527 unsigned int pkts_compl = 0, bytes_compl = 0;
6529 if (tg3_flag(tp, ENABLE_TSS))
6532 txq = netdev_get_tx_queue(tp->dev, index);
6534 while (sw_idx != hw_idx) {
6535 struct tg3_tx_ring_info *ri = &tnapi->tx_buffers[sw_idx];
6536 struct sk_buff *skb = ri->skb;
6539 if (unlikely(skb == NULL)) {
6544 if (tnapi->tx_ring[sw_idx].len_flags & TXD_FLAG_HWTSTAMP) {
6545 struct skb_shared_hwtstamps timestamp;
6546 u64 hwclock = tr32(TG3_TX_TSTAMP_LSB);
6547 hwclock |= (u64)tr32(TG3_TX_TSTAMP_MSB) << 32;
6549 tg3_hwclock_to_timestamp(tp, hwclock, ×tamp);
6551 skb_tstamp_tx(skb, ×tamp);
6554 pci_unmap_single(tp->pdev,
6555 dma_unmap_addr(ri, mapping),
6561 while (ri->fragmented) {
6562 ri->fragmented = false;
6563 sw_idx = NEXT_TX(sw_idx);
6564 ri = &tnapi->tx_buffers[sw_idx];
6567 sw_idx = NEXT_TX(sw_idx);
6569 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
6570 ri = &tnapi->tx_buffers[sw_idx];
6571 if (unlikely(ri->skb != NULL || sw_idx == hw_idx))
6574 pci_unmap_page(tp->pdev,
6575 dma_unmap_addr(ri, mapping),
6576 skb_frag_size(&skb_shinfo(skb)->frags[i]),
6579 while (ri->fragmented) {
6580 ri->fragmented = false;
6581 sw_idx = NEXT_TX(sw_idx);
6582 ri = &tnapi->tx_buffers[sw_idx];
6585 sw_idx = NEXT_TX(sw_idx);
6589 bytes_compl += skb->len;
6591 dev_kfree_skb_any(skb);
6593 if (unlikely(tx_bug)) {
6599 netdev_tx_completed_queue(txq, pkts_compl, bytes_compl);
6601 tnapi->tx_cons = sw_idx;
6603 /* Need to make the tx_cons update visible to tg3_start_xmit()
6604 * before checking for netif_queue_stopped(). Without the
6605 * memory barrier, there is a small possibility that tg3_start_xmit()
6606 * will miss it and cause the queue to be stopped forever.
6610 if (unlikely(netif_tx_queue_stopped(txq) &&
6611 (tg3_tx_avail(tnapi) > TG3_TX_WAKEUP_THRESH(tnapi)))) {
6612 __netif_tx_lock(txq, smp_processor_id());
6613 if (netif_tx_queue_stopped(txq) &&
6614 (tg3_tx_avail(tnapi) > TG3_TX_WAKEUP_THRESH(tnapi)))
6615 netif_tx_wake_queue(txq);
6616 __netif_tx_unlock(txq);
6620 static void tg3_frag_free(bool is_frag, void *data)
6623 put_page(virt_to_head_page(data));
6628 static void tg3_rx_data_free(struct tg3 *tp, struct ring_info *ri, u32 map_sz)
6630 unsigned int skb_size = SKB_DATA_ALIGN(map_sz + TG3_RX_OFFSET(tp)) +
6631 SKB_DATA_ALIGN(sizeof(struct skb_shared_info));
6636 pci_unmap_single(tp->pdev, dma_unmap_addr(ri, mapping),
6637 map_sz, PCI_DMA_FROMDEVICE);
6638 tg3_frag_free(skb_size <= PAGE_SIZE, ri->data);
6643 /* Returns size of skb allocated or < 0 on error.
6645 * We only need to fill in the address because the other members
6646 * of the RX descriptor are invariant, see tg3_init_rings.
6648 * Note the purposeful assymetry of cpu vs. chip accesses. For
6649 * posting buffers we only dirty the first cache line of the RX
6650 * descriptor (containing the address). Whereas for the RX status
6651 * buffers the cpu only reads the last cacheline of the RX descriptor
6652 * (to fetch the error flags, vlan tag, checksum, and opaque cookie).
6654 static int tg3_alloc_rx_data(struct tg3 *tp, struct tg3_rx_prodring_set *tpr,
6655 u32 opaque_key, u32 dest_idx_unmasked,
6656 unsigned int *frag_size)
6658 struct tg3_rx_buffer_desc *desc;
6659 struct ring_info *map;
6662 int skb_size, data_size, dest_idx;
6664 switch (opaque_key) {
6665 case RXD_OPAQUE_RING_STD:
6666 dest_idx = dest_idx_unmasked & tp->rx_std_ring_mask;
6667 desc = &tpr->rx_std[dest_idx];
6668 map = &tpr->rx_std_buffers[dest_idx];
6669 data_size = tp->rx_pkt_map_sz;
6672 case RXD_OPAQUE_RING_JUMBO:
6673 dest_idx = dest_idx_unmasked & tp->rx_jmb_ring_mask;
6674 desc = &tpr->rx_jmb[dest_idx].std;
6675 map = &tpr->rx_jmb_buffers[dest_idx];
6676 data_size = TG3_RX_JMB_MAP_SZ;
6683 /* Do not overwrite any of the map or rp information
6684 * until we are sure we can commit to a new buffer.
6686 * Callers depend upon this behavior and assume that
6687 * we leave everything unchanged if we fail.
6689 skb_size = SKB_DATA_ALIGN(data_size + TG3_RX_OFFSET(tp)) +
6690 SKB_DATA_ALIGN(sizeof(struct skb_shared_info));
6691 if (skb_size <= PAGE_SIZE) {
6692 data = netdev_alloc_frag(skb_size);
6693 *frag_size = skb_size;
6695 data = kmalloc(skb_size, GFP_ATOMIC);
6701 mapping = pci_map_single(tp->pdev,
6702 data + TG3_RX_OFFSET(tp),
6704 PCI_DMA_FROMDEVICE);
6705 if (unlikely(pci_dma_mapping_error(tp->pdev, mapping))) {
6706 tg3_frag_free(skb_size <= PAGE_SIZE, data);
6711 dma_unmap_addr_set(map, mapping, mapping);
6713 desc->addr_hi = ((u64)mapping >> 32);
6714 desc->addr_lo = ((u64)mapping & 0xffffffff);
6719 /* We only need to move over in the address because the other
6720 * members of the RX descriptor are invariant. See notes above
6721 * tg3_alloc_rx_data for full details.
6723 static void tg3_recycle_rx(struct tg3_napi *tnapi,
6724 struct tg3_rx_prodring_set *dpr,
6725 u32 opaque_key, int src_idx,
6726 u32 dest_idx_unmasked)
6728 struct tg3 *tp = tnapi->tp;
6729 struct tg3_rx_buffer_desc *src_desc, *dest_desc;
6730 struct ring_info *src_map, *dest_map;
6731 struct tg3_rx_prodring_set *spr = &tp->napi[0].prodring;
6734 switch (opaque_key) {
6735 case RXD_OPAQUE_RING_STD:
6736 dest_idx = dest_idx_unmasked & tp->rx_std_ring_mask;
6737 dest_desc = &dpr->rx_std[dest_idx];
6738 dest_map = &dpr->rx_std_buffers[dest_idx];
6739 src_desc = &spr->rx_std[src_idx];
6740 src_map = &spr->rx_std_buffers[src_idx];
6743 case RXD_OPAQUE_RING_JUMBO:
6744 dest_idx = dest_idx_unmasked & tp->rx_jmb_ring_mask;
6745 dest_desc = &dpr->rx_jmb[dest_idx].std;
6746 dest_map = &dpr->rx_jmb_buffers[dest_idx];
6747 src_desc = &spr->rx_jmb[src_idx].std;
6748 src_map = &spr->rx_jmb_buffers[src_idx];
6755 dest_map->data = src_map->data;
6756 dma_unmap_addr_set(dest_map, mapping,
6757 dma_unmap_addr(src_map, mapping));
6758 dest_desc->addr_hi = src_desc->addr_hi;
6759 dest_desc->addr_lo = src_desc->addr_lo;
6761 /* Ensure that the update to the skb happens after the physical
6762 * addresses have been transferred to the new BD location.
6766 src_map->data = NULL;
6769 /* The RX ring scheme is composed of multiple rings which post fresh
6770 * buffers to the chip, and one special ring the chip uses to report
6771 * status back to the host.
6773 * The special ring reports the status of received packets to the
6774 * host. The chip does not write into the original descriptor the
6775 * RX buffer was obtained from. The chip simply takes the original
6776 * descriptor as provided by the host, updates the status and length
6777 * field, then writes this into the next status ring entry.
6779 * Each ring the host uses to post buffers to the chip is described
6780 * by a TG3_BDINFO entry in the chips SRAM area. When a packet arrives,
6781 * it is first placed into the on-chip ram. When the packet's length
6782 * is known, it walks down the TG3_BDINFO entries to select the ring.
6783 * Each TG3_BDINFO specifies a MAXLEN field and the first TG3_BDINFO
6784 * which is within the range of the new packet's length is chosen.
6786 * The "separate ring for rx status" scheme may sound queer, but it makes
6787 * sense from a cache coherency perspective. If only the host writes
6788 * to the buffer post rings, and only the chip writes to the rx status
6789 * rings, then cache lines never move beyond shared-modified state.
6790 * If both the host and chip were to write into the same ring, cache line
6791 * eviction could occur since both entities want it in an exclusive state.
6793 static int tg3_rx(struct tg3_napi *tnapi, int budget)
6795 struct tg3 *tp = tnapi->tp;
6796 u32 work_mask, rx_std_posted = 0;
6797 u32 std_prod_idx, jmb_prod_idx;
6798 u32 sw_idx = tnapi->rx_rcb_ptr;
6801 struct tg3_rx_prodring_set *tpr = &tnapi->prodring;
6803 hw_idx = *(tnapi->rx_rcb_prod_idx);
6805 * We need to order the read of hw_idx and the read of
6806 * the opaque cookie.
6811 std_prod_idx = tpr->rx_std_prod_idx;
6812 jmb_prod_idx = tpr->rx_jmb_prod_idx;
6813 while (sw_idx != hw_idx && budget > 0) {
6814 struct ring_info *ri;
6815 struct tg3_rx_buffer_desc *desc = &tnapi->rx_rcb[sw_idx];
6817 struct sk_buff *skb;
6818 dma_addr_t dma_addr;
6819 u32 opaque_key, desc_idx, *post_ptr;
6823 desc_idx = desc->opaque & RXD_OPAQUE_INDEX_MASK;
6824 opaque_key = desc->opaque & RXD_OPAQUE_RING_MASK;
6825 if (opaque_key == RXD_OPAQUE_RING_STD) {
6826 ri = &tp->napi[0].prodring.rx_std_buffers[desc_idx];
6827 dma_addr = dma_unmap_addr(ri, mapping);
6829 post_ptr = &std_prod_idx;
6831 } else if (opaque_key == RXD_OPAQUE_RING_JUMBO) {
6832 ri = &tp->napi[0].prodring.rx_jmb_buffers[desc_idx];
6833 dma_addr = dma_unmap_addr(ri, mapping);
6835 post_ptr = &jmb_prod_idx;
6837 goto next_pkt_nopost;
6839 work_mask |= opaque_key;
6841 if (desc->err_vlan & RXD_ERR_MASK) {
6843 tg3_recycle_rx(tnapi, tpr, opaque_key,
6844 desc_idx, *post_ptr);
6846 /* Other statistics kept track of by card. */
6851 prefetch(data + TG3_RX_OFFSET(tp));
6852 len = ((desc->idx_len & RXD_LEN_MASK) >> RXD_LEN_SHIFT) -
6855 if ((desc->type_flags & RXD_FLAG_PTPSTAT_MASK) ==
6856 RXD_FLAG_PTPSTAT_PTPV1 ||
6857 (desc->type_flags & RXD_FLAG_PTPSTAT_MASK) ==
6858 RXD_FLAG_PTPSTAT_PTPV2) {
6859 tstamp = tr32(TG3_RX_TSTAMP_LSB);
6860 tstamp |= (u64)tr32(TG3_RX_TSTAMP_MSB) << 32;
6863 if (len > TG3_RX_COPY_THRESH(tp)) {
6865 unsigned int frag_size;
6867 skb_size = tg3_alloc_rx_data(tp, tpr, opaque_key,
6868 *post_ptr, &frag_size);
6872 pci_unmap_single(tp->pdev, dma_addr, skb_size,
6873 PCI_DMA_FROMDEVICE);
6875 /* Ensure that the update to the data happens
6876 * after the usage of the old DMA mapping.
6882 skb = build_skb(data, frag_size);
6884 tg3_frag_free(frag_size != 0, data);
6885 goto drop_it_no_recycle;
6887 skb_reserve(skb, TG3_RX_OFFSET(tp));
6889 tg3_recycle_rx(tnapi, tpr, opaque_key,
6890 desc_idx, *post_ptr);
6892 skb = netdev_alloc_skb(tp->dev,
6893 len + TG3_RAW_IP_ALIGN);
6895 goto drop_it_no_recycle;
6897 skb_reserve(skb, TG3_RAW_IP_ALIGN);
6898 pci_dma_sync_single_for_cpu(tp->pdev, dma_addr, len, PCI_DMA_FROMDEVICE);
6900 data + TG3_RX_OFFSET(tp),
6902 pci_dma_sync_single_for_device(tp->pdev, dma_addr, len, PCI_DMA_FROMDEVICE);
6907 tg3_hwclock_to_timestamp(tp, tstamp,
6908 skb_hwtstamps(skb));
6910 if ((tp->dev->features & NETIF_F_RXCSUM) &&
6911 (desc->type_flags & RXD_FLAG_TCPUDP_CSUM) &&
6912 (((desc->ip_tcp_csum & RXD_TCPCSUM_MASK)
6913 >> RXD_TCPCSUM_SHIFT) == 0xffff))
6914 skb->ip_summed = CHECKSUM_UNNECESSARY;
6916 skb_checksum_none_assert(skb);
6918 skb->protocol = eth_type_trans(skb, tp->dev);
6920 if (len > (tp->dev->mtu + ETH_HLEN) &&
6921 skb->protocol != htons(ETH_P_8021Q)) {
6922 dev_kfree_skb_any(skb);
6923 goto drop_it_no_recycle;
6926 if (desc->type_flags & RXD_FLAG_VLAN &&
6927 !(tp->rx_mode & RX_MODE_KEEP_VLAN_TAG))
6928 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q),
6929 desc->err_vlan & RXD_VLAN_MASK);
6931 napi_gro_receive(&tnapi->napi, skb);
6939 if (unlikely(rx_std_posted >= tp->rx_std_max_post)) {
6940 tpr->rx_std_prod_idx = std_prod_idx &
6941 tp->rx_std_ring_mask;
6942 tw32_rx_mbox(TG3_RX_STD_PROD_IDX_REG,
6943 tpr->rx_std_prod_idx);
6944 work_mask &= ~RXD_OPAQUE_RING_STD;
6949 sw_idx &= tp->rx_ret_ring_mask;
6951 /* Refresh hw_idx to see if there is new work */
6952 if (sw_idx == hw_idx) {
6953 hw_idx = *(tnapi->rx_rcb_prod_idx);
6958 /* ACK the status ring. */
6959 tnapi->rx_rcb_ptr = sw_idx;
6960 tw32_rx_mbox(tnapi->consmbox, sw_idx);
6962 /* Refill RX ring(s). */
6963 if (!tg3_flag(tp, ENABLE_RSS)) {
6964 /* Sync BD data before updating mailbox */
6967 if (work_mask & RXD_OPAQUE_RING_STD) {
6968 tpr->rx_std_prod_idx = std_prod_idx &
6969 tp->rx_std_ring_mask;
6970 tw32_rx_mbox(TG3_RX_STD_PROD_IDX_REG,
6971 tpr->rx_std_prod_idx);
6973 if (work_mask & RXD_OPAQUE_RING_JUMBO) {
6974 tpr->rx_jmb_prod_idx = jmb_prod_idx &
6975 tp->rx_jmb_ring_mask;
6976 tw32_rx_mbox(TG3_RX_JMB_PROD_IDX_REG,
6977 tpr->rx_jmb_prod_idx);
6980 } else if (work_mask) {
6981 /* rx_std_buffers[] and rx_jmb_buffers[] entries must be
6982 * updated before the producer indices can be updated.
6986 tpr->rx_std_prod_idx = std_prod_idx & tp->rx_std_ring_mask;
6987 tpr->rx_jmb_prod_idx = jmb_prod_idx & tp->rx_jmb_ring_mask;
6989 if (tnapi != &tp->napi[1]) {
6990 tp->rx_refill = true;
6991 napi_schedule(&tp->napi[1].napi);
6998 static void tg3_poll_link(struct tg3 *tp)
7000 /* handle link change and other phy events */
7001 if (!(tg3_flag(tp, USE_LINKCHG_REG) || tg3_flag(tp, POLL_SERDES))) {
7002 struct tg3_hw_status *sblk = tp->napi[0].hw_status;
7004 if (sblk->status & SD_STATUS_LINK_CHG) {
7005 sblk->status = SD_STATUS_UPDATED |
7006 (sblk->status & ~SD_STATUS_LINK_CHG);
7007 spin_lock(&tp->lock);
7008 if (tg3_flag(tp, USE_PHYLIB)) {
7010 (MAC_STATUS_SYNC_CHANGED |
7011 MAC_STATUS_CFG_CHANGED |
7012 MAC_STATUS_MI_COMPLETION |
7013 MAC_STATUS_LNKSTATE_CHANGED));
7016 tg3_setup_phy(tp, false);
7017 spin_unlock(&tp->lock);
7022 static int tg3_rx_prodring_xfer(struct tg3 *tp,
7023 struct tg3_rx_prodring_set *dpr,
7024 struct tg3_rx_prodring_set *spr)
7026 u32 si, di, cpycnt, src_prod_idx;
7030 src_prod_idx = spr->rx_std_prod_idx;
7032 /* Make sure updates to the rx_std_buffers[] entries and the
7033 * standard producer index are seen in the correct order.
7037 if (spr->rx_std_cons_idx == src_prod_idx)
7040 if (spr->rx_std_cons_idx < src_prod_idx)
7041 cpycnt = src_prod_idx - spr->rx_std_cons_idx;
7043 cpycnt = tp->rx_std_ring_mask + 1 -
7044 spr->rx_std_cons_idx;
7046 cpycnt = min(cpycnt,
7047 tp->rx_std_ring_mask + 1 - dpr->rx_std_prod_idx);
7049 si = spr->rx_std_cons_idx;
7050 di = dpr->rx_std_prod_idx;
7052 for (i = di; i < di + cpycnt; i++) {
7053 if (dpr->rx_std_buffers[i].data) {
7063 /* Ensure that updates to the rx_std_buffers ring and the
7064 * shadowed hardware producer ring from tg3_recycle_skb() are
7065 * ordered correctly WRT the skb check above.
7069 memcpy(&dpr->rx_std_buffers[di],
7070 &spr->rx_std_buffers[si],
7071 cpycnt * sizeof(struct ring_info));
7073 for (i = 0; i < cpycnt; i++, di++, si++) {
7074 struct tg3_rx_buffer_desc *sbd, *dbd;
7075 sbd = &spr->rx_std[si];
7076 dbd = &dpr->rx_std[di];
7077 dbd->addr_hi = sbd->addr_hi;
7078 dbd->addr_lo = sbd->addr_lo;
7081 spr->rx_std_cons_idx = (spr->rx_std_cons_idx + cpycnt) &
7082 tp->rx_std_ring_mask;
7083 dpr->rx_std_prod_idx = (dpr->rx_std_prod_idx + cpycnt) &
7084 tp->rx_std_ring_mask;
7088 src_prod_idx = spr->rx_jmb_prod_idx;
7090 /* Make sure updates to the rx_jmb_buffers[] entries and
7091 * the jumbo producer index are seen in the correct order.
7095 if (spr->rx_jmb_cons_idx == src_prod_idx)
7098 if (spr->rx_jmb_cons_idx < src_prod_idx)
7099 cpycnt = src_prod_idx - spr->rx_jmb_cons_idx;
7101 cpycnt = tp->rx_jmb_ring_mask + 1 -
7102 spr->rx_jmb_cons_idx;
7104 cpycnt = min(cpycnt,
7105 tp->rx_jmb_ring_mask + 1 - dpr->rx_jmb_prod_idx);
7107 si = spr->rx_jmb_cons_idx;
7108 di = dpr->rx_jmb_prod_idx;
7110 for (i = di; i < di + cpycnt; i++) {
7111 if (dpr->rx_jmb_buffers[i].data) {
7121 /* Ensure that updates to the rx_jmb_buffers ring and the
7122 * shadowed hardware producer ring from tg3_recycle_skb() are
7123 * ordered correctly WRT the skb check above.
7127 memcpy(&dpr->rx_jmb_buffers[di],
7128 &spr->rx_jmb_buffers[si],
7129 cpycnt * sizeof(struct ring_info));
7131 for (i = 0; i < cpycnt; i++, di++, si++) {
7132 struct tg3_rx_buffer_desc *sbd, *dbd;
7133 sbd = &spr->rx_jmb[si].std;
7134 dbd = &dpr->rx_jmb[di].std;
7135 dbd->addr_hi = sbd->addr_hi;
7136 dbd->addr_lo = sbd->addr_lo;
7139 spr->rx_jmb_cons_idx = (spr->rx_jmb_cons_idx + cpycnt) &
7140 tp->rx_jmb_ring_mask;
7141 dpr->rx_jmb_prod_idx = (dpr->rx_jmb_prod_idx + cpycnt) &
7142 tp->rx_jmb_ring_mask;
7148 static int tg3_poll_work(struct tg3_napi *tnapi, int work_done, int budget)
7150 struct tg3 *tp = tnapi->tp;
7152 /* run TX completion thread */
7153 if (tnapi->hw_status->idx[0].tx_consumer != tnapi->tx_cons) {
7155 if (unlikely(tg3_flag(tp, TX_RECOVERY_PENDING)))
7159 if (!tnapi->rx_rcb_prod_idx)
7162 /* run RX thread, within the bounds set by NAPI.
7163 * All RX "locking" is done by ensuring outside
7164 * code synchronizes with tg3->napi.poll()
7166 if (*(tnapi->rx_rcb_prod_idx) != tnapi->rx_rcb_ptr)
7167 work_done += tg3_rx(tnapi, budget - work_done);
7169 if (tg3_flag(tp, ENABLE_RSS) && tnapi == &tp->napi[1]) {
7170 struct tg3_rx_prodring_set *dpr = &tp->napi[0].prodring;
7172 u32 std_prod_idx = dpr->rx_std_prod_idx;
7173 u32 jmb_prod_idx = dpr->rx_jmb_prod_idx;
7175 tp->rx_refill = false;
7176 for (i = 1; i <= tp->rxq_cnt; i++)
7177 err |= tg3_rx_prodring_xfer(tp, dpr,
7178 &tp->napi[i].prodring);
7182 if (std_prod_idx != dpr->rx_std_prod_idx)
7183 tw32_rx_mbox(TG3_RX_STD_PROD_IDX_REG,
7184 dpr->rx_std_prod_idx);
7186 if (jmb_prod_idx != dpr->rx_jmb_prod_idx)
7187 tw32_rx_mbox(TG3_RX_JMB_PROD_IDX_REG,
7188 dpr->rx_jmb_prod_idx);
7193 tw32_f(HOSTCC_MODE, tp->coal_now);
7199 static inline void tg3_reset_task_schedule(struct tg3 *tp)
7201 if (!test_and_set_bit(TG3_FLAG_RESET_TASK_PENDING, tp->tg3_flags))
7202 schedule_work(&tp->reset_task);
7205 static inline void tg3_reset_task_cancel(struct tg3 *tp)
7207 cancel_work_sync(&tp->reset_task);
7208 tg3_flag_clear(tp, RESET_TASK_PENDING);
7209 tg3_flag_clear(tp, TX_RECOVERY_PENDING);
7212 static int tg3_poll_msix(struct napi_struct *napi, int budget)
7214 struct tg3_napi *tnapi = container_of(napi, struct tg3_napi, napi);
7215 struct tg3 *tp = tnapi->tp;
7217 struct tg3_hw_status *sblk = tnapi->hw_status;
7220 work_done = tg3_poll_work(tnapi, work_done, budget);
7222 if (unlikely(tg3_flag(tp, TX_RECOVERY_PENDING)))
7225 if (unlikely(work_done >= budget))
7228 /* tp->last_tag is used in tg3_int_reenable() below
7229 * to tell the hw how much work has been processed,
7230 * so we must read it before checking for more work.
7232 tnapi->last_tag = sblk->status_tag;
7233 tnapi->last_irq_tag = tnapi->last_tag;
7236 /* check for RX/TX work to do */
7237 if (likely(sblk->idx[0].tx_consumer == tnapi->tx_cons &&
7238 *(tnapi->rx_rcb_prod_idx) == tnapi->rx_rcb_ptr)) {
7240 /* This test here is not race free, but will reduce
7241 * the number of interrupts by looping again.
7243 if (tnapi == &tp->napi[1] && tp->rx_refill)
7246 napi_complete(napi);
7247 /* Reenable interrupts. */
7248 tw32_mailbox(tnapi->int_mbox, tnapi->last_tag << 24);
7250 /* This test here is synchronized by napi_schedule()
7251 * and napi_complete() to close the race condition.
7253 if (unlikely(tnapi == &tp->napi[1] && tp->rx_refill)) {
7254 tw32(HOSTCC_MODE, tp->coalesce_mode |
7255 HOSTCC_MODE_ENABLE |
7266 /* work_done is guaranteed to be less than budget. */
7267 napi_complete(napi);
7268 tg3_reset_task_schedule(tp);
7272 static void tg3_process_error(struct tg3 *tp)
7275 bool real_error = false;
7277 if (tg3_flag(tp, ERROR_PROCESSED))
7280 /* Check Flow Attention register */
7281 val = tr32(HOSTCC_FLOW_ATTN);
7282 if (val & ~HOSTCC_FLOW_ATTN_MBUF_LWM) {
7283 netdev_err(tp->dev, "FLOW Attention error. Resetting chip.\n");
7287 if (tr32(MSGINT_STATUS) & ~MSGINT_STATUS_MSI_REQ) {
7288 netdev_err(tp->dev, "MSI Status error. Resetting chip.\n");
7292 if (tr32(RDMAC_STATUS) || tr32(WDMAC_STATUS)) {
7293 netdev_err(tp->dev, "DMA Status error. Resetting chip.\n");
7302 tg3_flag_set(tp, ERROR_PROCESSED);
7303 tg3_reset_task_schedule(tp);
7306 static int tg3_poll(struct napi_struct *napi, int budget)
7308 struct tg3_napi *tnapi = container_of(napi, struct tg3_napi, napi);
7309 struct tg3 *tp = tnapi->tp;
7311 struct tg3_hw_status *sblk = tnapi->hw_status;
7314 if (sblk->status & SD_STATUS_ERROR)
7315 tg3_process_error(tp);
7319 work_done = tg3_poll_work(tnapi, work_done, budget);
7321 if (unlikely(tg3_flag(tp, TX_RECOVERY_PENDING)))
7324 if (unlikely(work_done >= budget))
7327 if (tg3_flag(tp, TAGGED_STATUS)) {
7328 /* tp->last_tag is used in tg3_int_reenable() below
7329 * to tell the hw how much work has been processed,
7330 * so we must read it before checking for more work.
7332 tnapi->last_tag = sblk->status_tag;
7333 tnapi->last_irq_tag = tnapi->last_tag;
7336 sblk->status &= ~SD_STATUS_UPDATED;
7338 if (likely(!tg3_has_work(tnapi))) {
7339 napi_complete(napi);
7340 tg3_int_reenable(tnapi);
7348 /* work_done is guaranteed to be less than budget. */
7349 napi_complete(napi);
7350 tg3_reset_task_schedule(tp);
7354 static void tg3_napi_disable(struct tg3 *tp)
7358 for (i = tp->irq_cnt - 1; i >= 0; i--)
7359 napi_disable(&tp->napi[i].napi);
7362 static void tg3_napi_enable(struct tg3 *tp)
7366 for (i = 0; i < tp->irq_cnt; i++)
7367 napi_enable(&tp->napi[i].napi);
7370 static void tg3_napi_init(struct tg3 *tp)
7374 netif_napi_add(tp->dev, &tp->napi[0].napi, tg3_poll, 64);
7375 for (i = 1; i < tp->irq_cnt; i++)
7376 netif_napi_add(tp->dev, &tp->napi[i].napi, tg3_poll_msix, 64);
7379 static void tg3_napi_fini(struct tg3 *tp)
7383 for (i = 0; i < tp->irq_cnt; i++)
7384 netif_napi_del(&tp->napi[i].napi);
7387 static inline void tg3_netif_stop(struct tg3 *tp)
7389 tp->dev->trans_start = jiffies; /* prevent tx timeout */
7390 tg3_napi_disable(tp);
7391 netif_carrier_off(tp->dev);
7392 netif_tx_disable(tp->dev);
7395 /* tp->lock must be held */
7396 static inline void tg3_netif_start(struct tg3 *tp)
7400 /* NOTE: unconditional netif_tx_wake_all_queues is only
7401 * appropriate so long as all callers are assured to
7402 * have free tx slots (such as after tg3_init_hw)
7404 netif_tx_wake_all_queues(tp->dev);
7407 netif_carrier_on(tp->dev);
7409 tg3_napi_enable(tp);
7410 tp->napi[0].hw_status->status |= SD_STATUS_UPDATED;
7411 tg3_enable_ints(tp);
7414 static void tg3_irq_quiesce(struct tg3 *tp)
7418 BUG_ON(tp->irq_sync);
7423 for (i = 0; i < tp->irq_cnt; i++)
7424 synchronize_irq(tp->napi[i].irq_vec);
7427 /* Fully shutdown all tg3 driver activity elsewhere in the system.
7428 * If irq_sync is non-zero, then the IRQ handler must be synchronized
7429 * with as well. Most of the time, this is not necessary except when
7430 * shutting down the device.
7432 static inline void tg3_full_lock(struct tg3 *tp, int irq_sync)
7434 spin_lock_bh(&tp->lock);
7436 tg3_irq_quiesce(tp);
7439 static inline void tg3_full_unlock(struct tg3 *tp)
7441 spin_unlock_bh(&tp->lock);
7444 /* One-shot MSI handler - Chip automatically disables interrupt
7445 * after sending MSI so driver doesn't have to do it.
7447 static irqreturn_t tg3_msi_1shot(int irq, void *dev_id)
7449 struct tg3_napi *tnapi = dev_id;
7450 struct tg3 *tp = tnapi->tp;
7452 prefetch(tnapi->hw_status);
7454 prefetch(&tnapi->rx_rcb[tnapi->rx_rcb_ptr]);
7456 if (likely(!tg3_irq_sync(tp)))
7457 napi_schedule(&tnapi->napi);
7462 /* MSI ISR - No need to check for interrupt sharing and no need to
7463 * flush status block and interrupt mailbox. PCI ordering rules
7464 * guarantee that MSI will arrive after the status block.
7466 static irqreturn_t tg3_msi(int irq, void *dev_id)
7468 struct tg3_napi *tnapi = dev_id;
7469 struct tg3 *tp = tnapi->tp;
7471 prefetch(tnapi->hw_status);
7473 prefetch(&tnapi->rx_rcb[tnapi->rx_rcb_ptr]);
7475 * Writing any value to intr-mbox-0 clears PCI INTA# and
7476 * chip-internal interrupt pending events.
7477 * Writing non-zero to intr-mbox-0 additional tells the
7478 * NIC to stop sending us irqs, engaging "in-intr-handler"
7481 tw32_mailbox(tnapi->int_mbox, 0x00000001);
7482 if (likely(!tg3_irq_sync(tp)))
7483 napi_schedule(&tnapi->napi);
7485 return IRQ_RETVAL(1);
7488 static irqreturn_t tg3_interrupt(int irq, void *dev_id)
7490 struct tg3_napi *tnapi = dev_id;
7491 struct tg3 *tp = tnapi->tp;
7492 struct tg3_hw_status *sblk = tnapi->hw_status;
7493 unsigned int handled = 1;
7495 /* In INTx mode, it is possible for the interrupt to arrive at
7496 * the CPU before the status block posted prior to the interrupt.
7497 * Reading the PCI State register will confirm whether the
7498 * interrupt is ours and will flush the status block.
7500 if (unlikely(!(sblk->status & SD_STATUS_UPDATED))) {
7501 if (tg3_flag(tp, CHIP_RESETTING) ||
7502 (tr32(TG3PCI_PCISTATE) & PCISTATE_INT_NOT_ACTIVE)) {
7509 * Writing any value to intr-mbox-0 clears PCI INTA# and
7510 * chip-internal interrupt pending events.
7511 * Writing non-zero to intr-mbox-0 additional tells the
7512 * NIC to stop sending us irqs, engaging "in-intr-handler"
7515 * Flush the mailbox to de-assert the IRQ immediately to prevent
7516 * spurious interrupts. The flush impacts performance but
7517 * excessive spurious interrupts can be worse in some cases.
7519 tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, 0x00000001);
7520 if (tg3_irq_sync(tp))
7522 sblk->status &= ~SD_STATUS_UPDATED;
7523 if (likely(tg3_has_work(tnapi))) {
7524 prefetch(&tnapi->rx_rcb[tnapi->rx_rcb_ptr]);
7525 napi_schedule(&tnapi->napi);
7527 /* No work, shared interrupt perhaps? re-enable
7528 * interrupts, and flush that PCI write
7530 tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW,
7534 return IRQ_RETVAL(handled);
7537 static irqreturn_t tg3_interrupt_tagged(int irq, void *dev_id)
7539 struct tg3_napi *tnapi = dev_id;
7540 struct tg3 *tp = tnapi->tp;
7541 struct tg3_hw_status *sblk = tnapi->hw_status;
7542 unsigned int handled = 1;
7544 /* In INTx mode, it is possible for the interrupt to arrive at
7545 * the CPU before the status block posted prior to the interrupt.
7546 * Reading the PCI State register will confirm whether the
7547 * interrupt is ours and will flush the status block.
7549 if (unlikely(sblk->status_tag == tnapi->last_irq_tag)) {
7550 if (tg3_flag(tp, CHIP_RESETTING) ||
7551 (tr32(TG3PCI_PCISTATE) & PCISTATE_INT_NOT_ACTIVE)) {
7558 * writing any value to intr-mbox-0 clears PCI INTA# and
7559 * chip-internal interrupt pending events.
7560 * writing non-zero to intr-mbox-0 additional tells the
7561 * NIC to stop sending us irqs, engaging "in-intr-handler"
7564 * Flush the mailbox to de-assert the IRQ immediately to prevent
7565 * spurious interrupts. The flush impacts performance but
7566 * excessive spurious interrupts can be worse in some cases.
7568 tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, 0x00000001);
7571 * In a shared interrupt configuration, sometimes other devices'
7572 * interrupts will scream. We record the current status tag here
7573 * so that the above check can report that the screaming interrupts
7574 * are unhandled. Eventually they will be silenced.
7576 tnapi->last_irq_tag = sblk->status_tag;
7578 if (tg3_irq_sync(tp))
7581 prefetch(&tnapi->rx_rcb[tnapi->rx_rcb_ptr]);
7583 napi_schedule(&tnapi->napi);
7586 return IRQ_RETVAL(handled);
7589 /* ISR for interrupt test */
7590 static irqreturn_t tg3_test_isr(int irq, void *dev_id)
7592 struct tg3_napi *tnapi = dev_id;
7593 struct tg3 *tp = tnapi->tp;
7594 struct tg3_hw_status *sblk = tnapi->hw_status;
7596 if ((sblk->status & SD_STATUS_UPDATED) ||
7597 !(tr32(TG3PCI_PCISTATE) & PCISTATE_INT_NOT_ACTIVE)) {
7598 tg3_disable_ints(tp);
7599 return IRQ_RETVAL(1);
7601 return IRQ_RETVAL(0);
7604 #ifdef CONFIG_NET_POLL_CONTROLLER
7605 static void tg3_poll_controller(struct net_device *dev)
7608 struct tg3 *tp = netdev_priv(dev);
7610 if (tg3_irq_sync(tp))
7613 for (i = 0; i < tp->irq_cnt; i++)
7614 tg3_interrupt(tp->napi[i].irq_vec, &tp->napi[i]);
7618 static void tg3_tx_timeout(struct net_device *dev)
7620 struct tg3 *tp = netdev_priv(dev);
7622 if (netif_msg_tx_err(tp)) {
7623 netdev_err(dev, "transmit timed out, resetting\n");
7627 tg3_reset_task_schedule(tp);
7630 /* Test for DMA buffers crossing any 4GB boundaries: 4G, 8G, etc */
7631 static inline int tg3_4g_overflow_test(dma_addr_t mapping, int len)
7633 u32 base = (u32) mapping & 0xffffffff;
7635 return base + len + 8 < base;
7638 /* Test for TSO DMA buffers that cross into regions which are within MSS bytes
7639 * of any 4GB boundaries: 4G, 8G, etc
7641 static inline int tg3_4g_tso_overflow_test(struct tg3 *tp, dma_addr_t mapping,
7644 if (tg3_asic_rev(tp) == ASIC_REV_5762 && mss) {
7645 u32 base = (u32) mapping & 0xffffffff;
7647 return ((base + len + (mss & 0x3fff)) < base);
7652 /* Test for DMA addresses > 40-bit */
7653 static inline int tg3_40bit_overflow_test(struct tg3 *tp, dma_addr_t mapping,
7656 #if defined(CONFIG_HIGHMEM) && (BITS_PER_LONG == 64)
7657 if (tg3_flag(tp, 40BIT_DMA_BUG))
7658 return ((u64) mapping + len) > DMA_BIT_MASK(40);
7665 static inline void tg3_tx_set_bd(struct tg3_tx_buffer_desc *txbd,
7666 dma_addr_t mapping, u32 len, u32 flags,
7669 txbd->addr_hi = ((u64) mapping >> 32);
7670 txbd->addr_lo = ((u64) mapping & 0xffffffff);
7671 txbd->len_flags = (len << TXD_LEN_SHIFT) | (flags & 0x0000ffff);
7672 txbd->vlan_tag = (mss << TXD_MSS_SHIFT) | (vlan << TXD_VLAN_TAG_SHIFT);
7675 static bool tg3_tx_frag_set(struct tg3_napi *tnapi, u32 *entry, u32 *budget,
7676 dma_addr_t map, u32 len, u32 flags,
7679 struct tg3 *tp = tnapi->tp;
7682 if (tg3_flag(tp, SHORT_DMA_BUG) && len <= 8)
7685 if (tg3_4g_overflow_test(map, len))
7688 if (tg3_4g_tso_overflow_test(tp, map, len, mss))
7691 if (tg3_40bit_overflow_test(tp, map, len))
7694 if (tp->dma_limit) {
7695 u32 prvidx = *entry;
7696 u32 tmp_flag = flags & ~TXD_FLAG_END;
7697 while (len > tp->dma_limit && *budget) {
7698 u32 frag_len = tp->dma_limit;
7699 len -= tp->dma_limit;
7701 /* Avoid the 8byte DMA problem */
7703 len += tp->dma_limit / 2;
7704 frag_len = tp->dma_limit / 2;
7707 tnapi->tx_buffers[*entry].fragmented = true;
7709 tg3_tx_set_bd(&tnapi->tx_ring[*entry], map,
7710 frag_len, tmp_flag, mss, vlan);
7713 *entry = NEXT_TX(*entry);
7720 tg3_tx_set_bd(&tnapi->tx_ring[*entry], map,
7721 len, flags, mss, vlan);
7723 *entry = NEXT_TX(*entry);
7726 tnapi->tx_buffers[prvidx].fragmented = false;
7730 tg3_tx_set_bd(&tnapi->tx_ring[*entry], map,
7731 len, flags, mss, vlan);
7732 *entry = NEXT_TX(*entry);
7738 static void tg3_tx_skb_unmap(struct tg3_napi *tnapi, u32 entry, int last)
7741 struct sk_buff *skb;
7742 struct tg3_tx_ring_info *txb = &tnapi->tx_buffers[entry];
7747 pci_unmap_single(tnapi->tp->pdev,
7748 dma_unmap_addr(txb, mapping),
7752 while (txb->fragmented) {
7753 txb->fragmented = false;
7754 entry = NEXT_TX(entry);
7755 txb = &tnapi->tx_buffers[entry];
7758 for (i = 0; i <= last; i++) {
7759 const skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
7761 entry = NEXT_TX(entry);
7762 txb = &tnapi->tx_buffers[entry];
7764 pci_unmap_page(tnapi->tp->pdev,
7765 dma_unmap_addr(txb, mapping),
7766 skb_frag_size(frag), PCI_DMA_TODEVICE);
7768 while (txb->fragmented) {
7769 txb->fragmented = false;
7770 entry = NEXT_TX(entry);
7771 txb = &tnapi->tx_buffers[entry];
7776 /* Workaround 4GB and 40-bit hardware DMA bugs. */
7777 static int tigon3_dma_hwbug_workaround(struct tg3_napi *tnapi,
7778 struct sk_buff **pskb,
7779 u32 *entry, u32 *budget,
7780 u32 base_flags, u32 mss, u32 vlan)
7782 struct tg3 *tp = tnapi->tp;
7783 struct sk_buff *new_skb, *skb = *pskb;
7784 dma_addr_t new_addr = 0;
7787 if (tg3_asic_rev(tp) != ASIC_REV_5701)
7788 new_skb = skb_copy(skb, GFP_ATOMIC);
7790 int more_headroom = 4 - ((unsigned long)skb->data & 3);
7792 new_skb = skb_copy_expand(skb,
7793 skb_headroom(skb) + more_headroom,
7794 skb_tailroom(skb), GFP_ATOMIC);
7800 /* New SKB is guaranteed to be linear. */
7801 new_addr = pci_map_single(tp->pdev, new_skb->data, new_skb->len,
7803 /* Make sure the mapping succeeded */
7804 if (pci_dma_mapping_error(tp->pdev, new_addr)) {
7805 dev_kfree_skb_any(new_skb);
7808 u32 save_entry = *entry;
7810 base_flags |= TXD_FLAG_END;
7812 tnapi->tx_buffers[*entry].skb = new_skb;
7813 dma_unmap_addr_set(&tnapi->tx_buffers[*entry],
7816 if (tg3_tx_frag_set(tnapi, entry, budget, new_addr,
7817 new_skb->len, base_flags,
7819 tg3_tx_skb_unmap(tnapi, save_entry, -1);
7820 dev_kfree_skb_any(new_skb);
7826 dev_kfree_skb_any(skb);
7831 static netdev_tx_t tg3_start_xmit(struct sk_buff *, struct net_device *);
7833 /* Use GSO to workaround a rare TSO bug that may be triggered when the
7834 * TSO header is greater than 80 bytes.
7836 static int tg3_tso_bug(struct tg3 *tp, struct sk_buff *skb)
7838 struct sk_buff *segs, *nskb;
7839 u32 frag_cnt_est = skb_shinfo(skb)->gso_segs * 3;
7841 /* Estimate the number of fragments in the worst case */
7842 if (unlikely(tg3_tx_avail(&tp->napi[0]) <= frag_cnt_est)) {
7843 netif_stop_queue(tp->dev);
7845 /* netif_tx_stop_queue() must be done before checking
7846 * checking tx index in tg3_tx_avail() below, because in
7847 * tg3_tx(), we update tx index before checking for
7848 * netif_tx_queue_stopped().
7851 if (tg3_tx_avail(&tp->napi[0]) <= frag_cnt_est)
7852 return NETDEV_TX_BUSY;
7854 netif_wake_queue(tp->dev);
7857 segs = skb_gso_segment(skb, tp->dev->features & ~NETIF_F_TSO);
7859 goto tg3_tso_bug_end;
7865 tg3_start_xmit(nskb, tp->dev);
7869 dev_kfree_skb_any(skb);
7871 return NETDEV_TX_OK;
7874 /* hard_start_xmit for devices that have the 4G bug and/or 40-bit bug and
7875 * support TG3_FLAG_HW_TSO_1 or firmware TSO only.
7877 static netdev_tx_t tg3_start_xmit(struct sk_buff *skb, struct net_device *dev)
7879 struct tg3 *tp = netdev_priv(dev);
7880 u32 len, entry, base_flags, mss, vlan = 0;
7882 int i = -1, would_hit_hwbug;
7884 struct tg3_napi *tnapi;
7885 struct netdev_queue *txq;
7888 txq = netdev_get_tx_queue(dev, skb_get_queue_mapping(skb));
7889 tnapi = &tp->napi[skb_get_queue_mapping(skb)];
7890 if (tg3_flag(tp, ENABLE_TSS))
7893 budget = tg3_tx_avail(tnapi);
7895 /* We are running in BH disabled context with netif_tx_lock
7896 * and TX reclaim runs via tp->napi.poll inside of a software
7897 * interrupt. Furthermore, IRQ processing runs lockless so we have
7898 * no IRQ context deadlocks to worry about either. Rejoice!
7900 if (unlikely(budget <= (skb_shinfo(skb)->nr_frags + 1))) {
7901 if (!netif_tx_queue_stopped(txq)) {
7902 netif_tx_stop_queue(txq);
7904 /* This is a hard error, log it. */
7906 "BUG! Tx Ring full when queue awake!\n");
7908 return NETDEV_TX_BUSY;
7911 entry = tnapi->tx_prod;
7913 if (skb->ip_summed == CHECKSUM_PARTIAL)
7914 base_flags |= TXD_FLAG_TCPUDP_CSUM;
7916 mss = skb_shinfo(skb)->gso_size;
7919 u32 tcp_opt_len, hdr_len;
7921 if (skb_header_cloned(skb) &&
7922 pskb_expand_head(skb, 0, 0, GFP_ATOMIC))
7926 tcp_opt_len = tcp_optlen(skb);
7928 hdr_len = skb_transport_offset(skb) + tcp_hdrlen(skb) - ETH_HLEN;
7930 if (!skb_is_gso_v6(skb)) {
7932 iph->tot_len = htons(mss + hdr_len);
7935 if (unlikely((ETH_HLEN + hdr_len) > 80) &&
7936 tg3_flag(tp, TSO_BUG))
7937 return tg3_tso_bug(tp, skb);
7939 base_flags |= (TXD_FLAG_CPU_PRE_DMA |
7940 TXD_FLAG_CPU_POST_DMA);
7942 if (tg3_flag(tp, HW_TSO_1) ||
7943 tg3_flag(tp, HW_TSO_2) ||
7944 tg3_flag(tp, HW_TSO_3)) {
7945 tcp_hdr(skb)->check = 0;
7946 base_flags &= ~TXD_FLAG_TCPUDP_CSUM;
7948 tcp_hdr(skb)->check = ~csum_tcpudp_magic(iph->saddr,
7953 if (tg3_flag(tp, HW_TSO_3)) {
7954 mss |= (hdr_len & 0xc) << 12;
7956 base_flags |= 0x00000010;
7957 base_flags |= (hdr_len & 0x3e0) << 5;
7958 } else if (tg3_flag(tp, HW_TSO_2))
7959 mss |= hdr_len << 9;
7960 else if (tg3_flag(tp, HW_TSO_1) ||
7961 tg3_asic_rev(tp) == ASIC_REV_5705) {
7962 if (tcp_opt_len || iph->ihl > 5) {
7965 tsflags = (iph->ihl - 5) + (tcp_opt_len >> 2);
7966 mss |= (tsflags << 11);
7969 if (tcp_opt_len || iph->ihl > 5) {
7972 tsflags = (iph->ihl - 5) + (tcp_opt_len >> 2);
7973 base_flags |= tsflags << 12;
7978 if (tg3_flag(tp, USE_JUMBO_BDFLAG) &&
7979 !mss && skb->len > VLAN_ETH_FRAME_LEN)
7980 base_flags |= TXD_FLAG_JMB_PKT;
7982 if (vlan_tx_tag_present(skb)) {
7983 base_flags |= TXD_FLAG_VLAN;
7984 vlan = vlan_tx_tag_get(skb);
7987 if ((unlikely(skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP)) &&
7988 tg3_flag(tp, TX_TSTAMP_EN)) {
7989 skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS;
7990 base_flags |= TXD_FLAG_HWTSTAMP;
7993 len = skb_headlen(skb);
7995 mapping = pci_map_single(tp->pdev, skb->data, len, PCI_DMA_TODEVICE);
7996 if (pci_dma_mapping_error(tp->pdev, mapping))
8000 tnapi->tx_buffers[entry].skb = skb;
8001 dma_unmap_addr_set(&tnapi->tx_buffers[entry], mapping, mapping);
8003 would_hit_hwbug = 0;
8005 if (tg3_flag(tp, 5701_DMA_BUG))
8006 would_hit_hwbug = 1;
8008 if (tg3_tx_frag_set(tnapi, &entry, &budget, mapping, len, base_flags |
8009 ((skb_shinfo(skb)->nr_frags == 0) ? TXD_FLAG_END : 0),
8011 would_hit_hwbug = 1;
8012 } else if (skb_shinfo(skb)->nr_frags > 0) {
8015 if (!tg3_flag(tp, HW_TSO_1) &&
8016 !tg3_flag(tp, HW_TSO_2) &&
8017 !tg3_flag(tp, HW_TSO_3))
8020 /* Now loop through additional data
8021 * fragments, and queue them.
8023 last = skb_shinfo(skb)->nr_frags - 1;
8024 for (i = 0; i <= last; i++) {
8025 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
8027 len = skb_frag_size(frag);
8028 mapping = skb_frag_dma_map(&tp->pdev->dev, frag, 0,
8029 len, DMA_TO_DEVICE);
8031 tnapi->tx_buffers[entry].skb = NULL;
8032 dma_unmap_addr_set(&tnapi->tx_buffers[entry], mapping,
8034 if (dma_mapping_error(&tp->pdev->dev, mapping))
8038 tg3_tx_frag_set(tnapi, &entry, &budget, mapping,
8040 ((i == last) ? TXD_FLAG_END : 0),
8042 would_hit_hwbug = 1;
8048 if (would_hit_hwbug) {
8049 tg3_tx_skb_unmap(tnapi, tnapi->tx_prod, i);
8051 /* If the workaround fails due to memory/mapping
8052 * failure, silently drop this packet.
8054 entry = tnapi->tx_prod;
8055 budget = tg3_tx_avail(tnapi);
8056 if (tigon3_dma_hwbug_workaround(tnapi, &skb, &entry, &budget,
8057 base_flags, mss, vlan))
8061 skb_tx_timestamp(skb);
8062 netdev_tx_sent_queue(txq, skb->len);
8064 /* Sync BD data before updating mailbox */
8067 /* Packets are ready, update Tx producer idx local and on card. */
8068 tw32_tx_mbox(tnapi->prodmbox, entry);
8070 tnapi->tx_prod = entry;
8071 if (unlikely(tg3_tx_avail(tnapi) <= (MAX_SKB_FRAGS + 1))) {
8072 netif_tx_stop_queue(txq);
8074 /* netif_tx_stop_queue() must be done before checking
8075 * checking tx index in tg3_tx_avail() below, because in
8076 * tg3_tx(), we update tx index before checking for
8077 * netif_tx_queue_stopped().
8080 if (tg3_tx_avail(tnapi) > TG3_TX_WAKEUP_THRESH(tnapi))
8081 netif_tx_wake_queue(txq);
8085 return NETDEV_TX_OK;
8088 tg3_tx_skb_unmap(tnapi, tnapi->tx_prod, --i);
8089 tnapi->tx_buffers[tnapi->tx_prod].skb = NULL;
8091 dev_kfree_skb_any(skb);
8094 return NETDEV_TX_OK;
8097 static void tg3_mac_loopback(struct tg3 *tp, bool enable)
8100 tp->mac_mode &= ~(MAC_MODE_HALF_DUPLEX |
8101 MAC_MODE_PORT_MODE_MASK);
8103 tp->mac_mode |= MAC_MODE_PORT_INT_LPBACK;
8105 if (!tg3_flag(tp, 5705_PLUS))
8106 tp->mac_mode |= MAC_MODE_LINK_POLARITY;
8108 if (tp->phy_flags & TG3_PHYFLG_10_100_ONLY)
8109 tp->mac_mode |= MAC_MODE_PORT_MODE_MII;
8111 tp->mac_mode |= MAC_MODE_PORT_MODE_GMII;
8113 tp->mac_mode &= ~MAC_MODE_PORT_INT_LPBACK;
8115 if (tg3_flag(tp, 5705_PLUS) ||
8116 (tp->phy_flags & TG3_PHYFLG_PHY_SERDES) ||
8117 tg3_asic_rev(tp) == ASIC_REV_5700)
8118 tp->mac_mode &= ~MAC_MODE_LINK_POLARITY;
8121 tw32(MAC_MODE, tp->mac_mode);
8125 static int tg3_phy_lpbk_set(struct tg3 *tp, u32 speed, bool extlpbk)
8127 u32 val, bmcr, mac_mode, ptest = 0;
8129 tg3_phy_toggle_apd(tp, false);
8130 tg3_phy_toggle_automdix(tp, false);
8132 if (extlpbk && tg3_phy_set_extloopbk(tp))
8135 bmcr = BMCR_FULLDPLX;
8140 bmcr |= BMCR_SPEED100;
8144 if (tp->phy_flags & TG3_PHYFLG_IS_FET) {
8146 bmcr |= BMCR_SPEED100;
8149 bmcr |= BMCR_SPEED1000;
8154 if (!(tp->phy_flags & TG3_PHYFLG_IS_FET)) {
8155 tg3_readphy(tp, MII_CTRL1000, &val);
8156 val |= CTL1000_AS_MASTER |
8157 CTL1000_ENABLE_MASTER;
8158 tg3_writephy(tp, MII_CTRL1000, val);
8160 ptest = MII_TG3_FET_PTEST_TRIM_SEL |
8161 MII_TG3_FET_PTEST_TRIM_2;
8162 tg3_writephy(tp, MII_TG3_FET_PTEST, ptest);
8165 bmcr |= BMCR_LOOPBACK;
8167 tg3_writephy(tp, MII_BMCR, bmcr);
8169 /* The write needs to be flushed for the FETs */
8170 if (tp->phy_flags & TG3_PHYFLG_IS_FET)
8171 tg3_readphy(tp, MII_BMCR, &bmcr);
8175 if ((tp->phy_flags & TG3_PHYFLG_IS_FET) &&
8176 tg3_asic_rev(tp) == ASIC_REV_5785) {
8177 tg3_writephy(tp, MII_TG3_FET_PTEST, ptest |
8178 MII_TG3_FET_PTEST_FRC_TX_LINK |
8179 MII_TG3_FET_PTEST_FRC_TX_LOCK);
8181 /* The write needs to be flushed for the AC131 */
8182 tg3_readphy(tp, MII_TG3_FET_PTEST, &val);
8185 /* Reset to prevent losing 1st rx packet intermittently */
8186 if ((tp->phy_flags & TG3_PHYFLG_MII_SERDES) &&
8187 tg3_flag(tp, 5780_CLASS)) {
8188 tw32_f(MAC_RX_MODE, RX_MODE_RESET);
8190 tw32_f(MAC_RX_MODE, tp->rx_mode);
8193 mac_mode = tp->mac_mode &
8194 ~(MAC_MODE_PORT_MODE_MASK | MAC_MODE_HALF_DUPLEX);
8195 if (speed == SPEED_1000)
8196 mac_mode |= MAC_MODE_PORT_MODE_GMII;
8198 mac_mode |= MAC_MODE_PORT_MODE_MII;
8200 if (tg3_asic_rev(tp) == ASIC_REV_5700) {
8201 u32 masked_phy_id = tp->phy_id & TG3_PHY_ID_MASK;
8203 if (masked_phy_id == TG3_PHY_ID_BCM5401)
8204 mac_mode &= ~MAC_MODE_LINK_POLARITY;
8205 else if (masked_phy_id == TG3_PHY_ID_BCM5411)
8206 mac_mode |= MAC_MODE_LINK_POLARITY;
8208 tg3_writephy(tp, MII_TG3_EXT_CTRL,
8209 MII_TG3_EXT_CTRL_LNK3_LED_MODE);
8212 tw32(MAC_MODE, mac_mode);
8218 static void tg3_set_loopback(struct net_device *dev, netdev_features_t features)
8220 struct tg3 *tp = netdev_priv(dev);
8222 if (features & NETIF_F_LOOPBACK) {
8223 if (tp->mac_mode & MAC_MODE_PORT_INT_LPBACK)
8226 spin_lock_bh(&tp->lock);
8227 tg3_mac_loopback(tp, true);
8228 netif_carrier_on(tp->dev);
8229 spin_unlock_bh(&tp->lock);
8230 netdev_info(dev, "Internal MAC loopback mode enabled.\n");
8232 if (!(tp->mac_mode & MAC_MODE_PORT_INT_LPBACK))
8235 spin_lock_bh(&tp->lock);
8236 tg3_mac_loopback(tp, false);
8237 /* Force link status check */
8238 tg3_setup_phy(tp, true);
8239 spin_unlock_bh(&tp->lock);
8240 netdev_info(dev, "Internal MAC loopback mode disabled.\n");
8244 static netdev_features_t tg3_fix_features(struct net_device *dev,
8245 netdev_features_t features)
8247 struct tg3 *tp = netdev_priv(dev);
8249 if (dev->mtu > ETH_DATA_LEN && tg3_flag(tp, 5780_CLASS))
8250 features &= ~NETIF_F_ALL_TSO;
8255 static int tg3_set_features(struct net_device *dev, netdev_features_t features)
8257 netdev_features_t changed = dev->features ^ features;
8259 if ((changed & NETIF_F_LOOPBACK) && netif_running(dev))
8260 tg3_set_loopback(dev, features);
8265 static void tg3_rx_prodring_free(struct tg3 *tp,
8266 struct tg3_rx_prodring_set *tpr)
8270 if (tpr != &tp->napi[0].prodring) {
8271 for (i = tpr->rx_std_cons_idx; i != tpr->rx_std_prod_idx;
8272 i = (i + 1) & tp->rx_std_ring_mask)
8273 tg3_rx_data_free(tp, &tpr->rx_std_buffers[i],
8276 if (tg3_flag(tp, JUMBO_CAPABLE)) {
8277 for (i = tpr->rx_jmb_cons_idx;
8278 i != tpr->rx_jmb_prod_idx;
8279 i = (i + 1) & tp->rx_jmb_ring_mask) {
8280 tg3_rx_data_free(tp, &tpr->rx_jmb_buffers[i],
8288 for (i = 0; i <= tp->rx_std_ring_mask; i++)
8289 tg3_rx_data_free(tp, &tpr->rx_std_buffers[i],
8292 if (tg3_flag(tp, JUMBO_CAPABLE) && !tg3_flag(tp, 5780_CLASS)) {
8293 for (i = 0; i <= tp->rx_jmb_ring_mask; i++)
8294 tg3_rx_data_free(tp, &tpr->rx_jmb_buffers[i],
8299 /* Initialize rx rings for packet processing.
8301 * The chip has been shut down and the driver detached from
8302 * the networking, so no interrupts or new tx packets will
8303 * end up in the driver. tp->{tx,}lock are held and thus
8306 static int tg3_rx_prodring_alloc(struct tg3 *tp,
8307 struct tg3_rx_prodring_set *tpr)
8309 u32 i, rx_pkt_dma_sz;
8311 tpr->rx_std_cons_idx = 0;
8312 tpr->rx_std_prod_idx = 0;
8313 tpr->rx_jmb_cons_idx = 0;
8314 tpr->rx_jmb_prod_idx = 0;
8316 if (tpr != &tp->napi[0].prodring) {
8317 memset(&tpr->rx_std_buffers[0], 0,
8318 TG3_RX_STD_BUFF_RING_SIZE(tp));
8319 if (tpr->rx_jmb_buffers)
8320 memset(&tpr->rx_jmb_buffers[0], 0,
8321 TG3_RX_JMB_BUFF_RING_SIZE(tp));
8325 /* Zero out all descriptors. */
8326 memset(tpr->rx_std, 0, TG3_RX_STD_RING_BYTES(tp));
8328 rx_pkt_dma_sz = TG3_RX_STD_DMA_SZ;
8329 if (tg3_flag(tp, 5780_CLASS) &&
8330 tp->dev->mtu > ETH_DATA_LEN)
8331 rx_pkt_dma_sz = TG3_RX_JMB_DMA_SZ;
8332 tp->rx_pkt_map_sz = TG3_RX_DMA_TO_MAP_SZ(rx_pkt_dma_sz);
8334 /* Initialize invariants of the rings, we only set this
8335 * stuff once. This works because the card does not
8336 * write into the rx buffer posting rings.
8338 for (i = 0; i <= tp->rx_std_ring_mask; i++) {
8339 struct tg3_rx_buffer_desc *rxd;
8341 rxd = &tpr->rx_std[i];
8342 rxd->idx_len = rx_pkt_dma_sz << RXD_LEN_SHIFT;
8343 rxd->type_flags = (RXD_FLAG_END << RXD_FLAGS_SHIFT);
8344 rxd->opaque = (RXD_OPAQUE_RING_STD |
8345 (i << RXD_OPAQUE_INDEX_SHIFT));
8348 /* Now allocate fresh SKBs for each rx ring. */
8349 for (i = 0; i < tp->rx_pending; i++) {
8350 unsigned int frag_size;
8352 if (tg3_alloc_rx_data(tp, tpr, RXD_OPAQUE_RING_STD, i,
8354 netdev_warn(tp->dev,
8355 "Using a smaller RX standard ring. Only "
8356 "%d out of %d buffers were allocated "
8357 "successfully\n", i, tp->rx_pending);
8365 if (!tg3_flag(tp, JUMBO_CAPABLE) || tg3_flag(tp, 5780_CLASS))
8368 memset(tpr->rx_jmb, 0, TG3_RX_JMB_RING_BYTES(tp));
8370 if (!tg3_flag(tp, JUMBO_RING_ENABLE))
8373 for (i = 0; i <= tp->rx_jmb_ring_mask; i++) {
8374 struct tg3_rx_buffer_desc *rxd;
8376 rxd = &tpr->rx_jmb[i].std;
8377 rxd->idx_len = TG3_RX_JMB_DMA_SZ << RXD_LEN_SHIFT;
8378 rxd->type_flags = (RXD_FLAG_END << RXD_FLAGS_SHIFT) |
8380 rxd->opaque = (RXD_OPAQUE_RING_JUMBO |
8381 (i << RXD_OPAQUE_INDEX_SHIFT));
8384 for (i = 0; i < tp->rx_jumbo_pending; i++) {
8385 unsigned int frag_size;
8387 if (tg3_alloc_rx_data(tp, tpr, RXD_OPAQUE_RING_JUMBO, i,
8389 netdev_warn(tp->dev,
8390 "Using a smaller RX jumbo ring. Only %d "
8391 "out of %d buffers were allocated "
8392 "successfully\n", i, tp->rx_jumbo_pending);
8395 tp->rx_jumbo_pending = i;
8404 tg3_rx_prodring_free(tp, tpr);
8408 static void tg3_rx_prodring_fini(struct tg3 *tp,
8409 struct tg3_rx_prodring_set *tpr)
8411 kfree(tpr->rx_std_buffers);
8412 tpr->rx_std_buffers = NULL;
8413 kfree(tpr->rx_jmb_buffers);
8414 tpr->rx_jmb_buffers = NULL;
8416 dma_free_coherent(&tp->pdev->dev, TG3_RX_STD_RING_BYTES(tp),
8417 tpr->rx_std, tpr->rx_std_mapping);
8421 dma_free_coherent(&tp->pdev->dev, TG3_RX_JMB_RING_BYTES(tp),
8422 tpr->rx_jmb, tpr->rx_jmb_mapping);
8427 static int tg3_rx_prodring_init(struct tg3 *tp,
8428 struct tg3_rx_prodring_set *tpr)
8430 tpr->rx_std_buffers = kzalloc(TG3_RX_STD_BUFF_RING_SIZE(tp),
8432 if (!tpr->rx_std_buffers)
8435 tpr->rx_std = dma_alloc_coherent(&tp->pdev->dev,
8436 TG3_RX_STD_RING_BYTES(tp),
8437 &tpr->rx_std_mapping,
8442 if (tg3_flag(tp, JUMBO_CAPABLE) && !tg3_flag(tp, 5780_CLASS)) {
8443 tpr->rx_jmb_buffers = kzalloc(TG3_RX_JMB_BUFF_RING_SIZE(tp),
8445 if (!tpr->rx_jmb_buffers)
8448 tpr->rx_jmb = dma_alloc_coherent(&tp->pdev->dev,
8449 TG3_RX_JMB_RING_BYTES(tp),
8450 &tpr->rx_jmb_mapping,
8459 tg3_rx_prodring_fini(tp, tpr);
8463 /* Free up pending packets in all rx/tx rings.
8465 * The chip has been shut down and the driver detached from
8466 * the networking, so no interrupts or new tx packets will
8467 * end up in the driver. tp->{tx,}lock is not held and we are not
8468 * in an interrupt context and thus may sleep.
8470 static void tg3_free_rings(struct tg3 *tp)
8474 for (j = 0; j < tp->irq_cnt; j++) {
8475 struct tg3_napi *tnapi = &tp->napi[j];
8477 tg3_rx_prodring_free(tp, &tnapi->prodring);
8479 if (!tnapi->tx_buffers)
8482 for (i = 0; i < TG3_TX_RING_SIZE; i++) {
8483 struct sk_buff *skb = tnapi->tx_buffers[i].skb;
8488 tg3_tx_skb_unmap(tnapi, i,
8489 skb_shinfo(skb)->nr_frags - 1);
8491 dev_kfree_skb_any(skb);
8493 netdev_tx_reset_queue(netdev_get_tx_queue(tp->dev, j));
8497 /* Initialize tx/rx rings for packet processing.
8499 * The chip has been shut down and the driver detached from
8500 * the networking, so no interrupts or new tx packets will
8501 * end up in the driver. tp->{tx,}lock are held and thus
8504 static int tg3_init_rings(struct tg3 *tp)
8508 /* Free up all the SKBs. */
8511 for (i = 0; i < tp->irq_cnt; i++) {
8512 struct tg3_napi *tnapi = &tp->napi[i];
8514 tnapi->last_tag = 0;
8515 tnapi->last_irq_tag = 0;
8516 tnapi->hw_status->status = 0;
8517 tnapi->hw_status->status_tag = 0;
8518 memset(tnapi->hw_status, 0, TG3_HW_STATUS_SIZE);
8523 memset(tnapi->tx_ring, 0, TG3_TX_RING_BYTES);
8525 tnapi->rx_rcb_ptr = 0;
8527 memset(tnapi->rx_rcb, 0, TG3_RX_RCB_RING_BYTES(tp));
8529 if (tg3_rx_prodring_alloc(tp, &tnapi->prodring)) {
8538 static void tg3_mem_tx_release(struct tg3 *tp)
8542 for (i = 0; i < tp->irq_max; i++) {
8543 struct tg3_napi *tnapi = &tp->napi[i];
8545 if (tnapi->tx_ring) {
8546 dma_free_coherent(&tp->pdev->dev, TG3_TX_RING_BYTES,
8547 tnapi->tx_ring, tnapi->tx_desc_mapping);
8548 tnapi->tx_ring = NULL;
8551 kfree(tnapi->tx_buffers);
8552 tnapi->tx_buffers = NULL;
8556 static int tg3_mem_tx_acquire(struct tg3 *tp)
8559 struct tg3_napi *tnapi = &tp->napi[0];
8561 /* If multivector TSS is enabled, vector 0 does not handle
8562 * tx interrupts. Don't allocate any resources for it.
8564 if (tg3_flag(tp, ENABLE_TSS))
8567 for (i = 0; i < tp->txq_cnt; i++, tnapi++) {
8568 tnapi->tx_buffers = kzalloc(sizeof(struct tg3_tx_ring_info) *
8569 TG3_TX_RING_SIZE, GFP_KERNEL);
8570 if (!tnapi->tx_buffers)
8573 tnapi->tx_ring = dma_alloc_coherent(&tp->pdev->dev,
8575 &tnapi->tx_desc_mapping,
8577 if (!tnapi->tx_ring)
8584 tg3_mem_tx_release(tp);
8588 static void tg3_mem_rx_release(struct tg3 *tp)
8592 for (i = 0; i < tp->irq_max; i++) {
8593 struct tg3_napi *tnapi = &tp->napi[i];
8595 tg3_rx_prodring_fini(tp, &tnapi->prodring);
8600 dma_free_coherent(&tp->pdev->dev,
8601 TG3_RX_RCB_RING_BYTES(tp),
8603 tnapi->rx_rcb_mapping);
8604 tnapi->rx_rcb = NULL;
8608 static int tg3_mem_rx_acquire(struct tg3 *tp)
8610 unsigned int i, limit;
8612 limit = tp->rxq_cnt;
8614 /* If RSS is enabled, we need a (dummy) producer ring
8615 * set on vector zero. This is the true hw prodring.
8617 if (tg3_flag(tp, ENABLE_RSS))
8620 for (i = 0; i < limit; i++) {
8621 struct tg3_napi *tnapi = &tp->napi[i];
8623 if (tg3_rx_prodring_init(tp, &tnapi->prodring))
8626 /* If multivector RSS is enabled, vector 0
8627 * does not handle rx or tx interrupts.
8628 * Don't allocate any resources for it.
8630 if (!i && tg3_flag(tp, ENABLE_RSS))
8633 tnapi->rx_rcb = dma_zalloc_coherent(&tp->pdev->dev,
8634 TG3_RX_RCB_RING_BYTES(tp),
8635 &tnapi->rx_rcb_mapping,
8644 tg3_mem_rx_release(tp);
8649 * Must not be invoked with interrupt sources disabled and
8650 * the hardware shutdown down.
8652 static void tg3_free_consistent(struct tg3 *tp)
8656 for (i = 0; i < tp->irq_cnt; i++) {
8657 struct tg3_napi *tnapi = &tp->napi[i];
8659 if (tnapi->hw_status) {
8660 dma_free_coherent(&tp->pdev->dev, TG3_HW_STATUS_SIZE,
8662 tnapi->status_mapping);
8663 tnapi->hw_status = NULL;
8667 tg3_mem_rx_release(tp);
8668 tg3_mem_tx_release(tp);
8671 dma_free_coherent(&tp->pdev->dev, sizeof(struct tg3_hw_stats),
8672 tp->hw_stats, tp->stats_mapping);
8673 tp->hw_stats = NULL;
8678 * Must not be invoked with interrupt sources disabled and
8679 * the hardware shutdown down. Can sleep.
8681 static int tg3_alloc_consistent(struct tg3 *tp)
8685 tp->hw_stats = dma_zalloc_coherent(&tp->pdev->dev,
8686 sizeof(struct tg3_hw_stats),
8687 &tp->stats_mapping, GFP_KERNEL);
8691 for (i = 0; i < tp->irq_cnt; i++) {
8692 struct tg3_napi *tnapi = &tp->napi[i];
8693 struct tg3_hw_status *sblk;
8695 tnapi->hw_status = dma_zalloc_coherent(&tp->pdev->dev,
8697 &tnapi->status_mapping,
8699 if (!tnapi->hw_status)
8702 sblk = tnapi->hw_status;
8704 if (tg3_flag(tp, ENABLE_RSS)) {
8705 u16 *prodptr = NULL;
8708 * When RSS is enabled, the status block format changes
8709 * slightly. The "rx_jumbo_consumer", "reserved",
8710 * and "rx_mini_consumer" members get mapped to the
8711 * other three rx return ring producer indexes.
8715 prodptr = &sblk->idx[0].rx_producer;
8718 prodptr = &sblk->rx_jumbo_consumer;
8721 prodptr = &sblk->reserved;
8724 prodptr = &sblk->rx_mini_consumer;
8727 tnapi->rx_rcb_prod_idx = prodptr;
8729 tnapi->rx_rcb_prod_idx = &sblk->idx[0].rx_producer;
8733 if (tg3_mem_tx_acquire(tp) || tg3_mem_rx_acquire(tp))
8739 tg3_free_consistent(tp);
8743 #define MAX_WAIT_CNT 1000
8745 /* To stop a block, clear the enable bit and poll till it
8746 * clears. tp->lock is held.
8748 static int tg3_stop_block(struct tg3 *tp, unsigned long ofs, u32 enable_bit, bool silent)
8753 if (tg3_flag(tp, 5705_PLUS)) {
8760 /* We can't enable/disable these bits of the
8761 * 5705/5750, just say success.
8774 for (i = 0; i < MAX_WAIT_CNT; i++) {
8775 if (pci_channel_offline(tp->pdev)) {
8776 dev_err(&tp->pdev->dev,
8777 "tg3_stop_block device offline, "
8778 "ofs=%lx enable_bit=%x\n",
8785 if ((val & enable_bit) == 0)
8789 if (i == MAX_WAIT_CNT && !silent) {
8790 dev_err(&tp->pdev->dev,
8791 "tg3_stop_block timed out, ofs=%lx enable_bit=%x\n",
8799 /* tp->lock is held. */
8800 static int tg3_abort_hw(struct tg3 *tp, bool silent)
8804 tg3_disable_ints(tp);
8806 if (pci_channel_offline(tp->pdev)) {
8807 tp->rx_mode &= ~(RX_MODE_ENABLE | TX_MODE_ENABLE);
8808 tp->mac_mode &= ~MAC_MODE_TDE_ENABLE;
8813 tp->rx_mode &= ~RX_MODE_ENABLE;
8814 tw32_f(MAC_RX_MODE, tp->rx_mode);
8817 err = tg3_stop_block(tp, RCVBDI_MODE, RCVBDI_MODE_ENABLE, silent);
8818 err |= tg3_stop_block(tp, RCVLPC_MODE, RCVLPC_MODE_ENABLE, silent);
8819 err |= tg3_stop_block(tp, RCVLSC_MODE, RCVLSC_MODE_ENABLE, silent);
8820 err |= tg3_stop_block(tp, RCVDBDI_MODE, RCVDBDI_MODE_ENABLE, silent);
8821 err |= tg3_stop_block(tp, RCVDCC_MODE, RCVDCC_MODE_ENABLE, silent);
8822 err |= tg3_stop_block(tp, RCVCC_MODE, RCVCC_MODE_ENABLE, silent);
8824 err |= tg3_stop_block(tp, SNDBDS_MODE, SNDBDS_MODE_ENABLE, silent);
8825 err |= tg3_stop_block(tp, SNDBDI_MODE, SNDBDI_MODE_ENABLE, silent);
8826 err |= tg3_stop_block(tp, SNDDATAI_MODE, SNDDATAI_MODE_ENABLE, silent);
8827 err |= tg3_stop_block(tp, RDMAC_MODE, RDMAC_MODE_ENABLE, silent);
8828 err |= tg3_stop_block(tp, SNDDATAC_MODE, SNDDATAC_MODE_ENABLE, silent);
8829 err |= tg3_stop_block(tp, DMAC_MODE, DMAC_MODE_ENABLE, silent);
8830 err |= tg3_stop_block(tp, SNDBDC_MODE, SNDBDC_MODE_ENABLE, silent);
8832 tp->mac_mode &= ~MAC_MODE_TDE_ENABLE;
8833 tw32_f(MAC_MODE, tp->mac_mode);
8836 tp->tx_mode &= ~TX_MODE_ENABLE;
8837 tw32_f(MAC_TX_MODE, tp->tx_mode);
8839 for (i = 0; i < MAX_WAIT_CNT; i++) {
8841 if (!(tr32(MAC_TX_MODE) & TX_MODE_ENABLE))
8844 if (i >= MAX_WAIT_CNT) {
8845 dev_err(&tp->pdev->dev,
8846 "%s timed out, TX_MODE_ENABLE will not clear "
8847 "MAC_TX_MODE=%08x\n", __func__, tr32(MAC_TX_MODE));
8851 err |= tg3_stop_block(tp, HOSTCC_MODE, HOSTCC_MODE_ENABLE, silent);
8852 err |= tg3_stop_block(tp, WDMAC_MODE, WDMAC_MODE_ENABLE, silent);
8853 err |= tg3_stop_block(tp, MBFREE_MODE, MBFREE_MODE_ENABLE, silent);
8855 tw32(FTQ_RESET, 0xffffffff);
8856 tw32(FTQ_RESET, 0x00000000);
8858 err |= tg3_stop_block(tp, BUFMGR_MODE, BUFMGR_MODE_ENABLE, silent);
8859 err |= tg3_stop_block(tp, MEMARB_MODE, MEMARB_MODE_ENABLE, silent);
8862 for (i = 0; i < tp->irq_cnt; i++) {
8863 struct tg3_napi *tnapi = &tp->napi[i];
8864 if (tnapi->hw_status)
8865 memset(tnapi->hw_status, 0, TG3_HW_STATUS_SIZE);
8871 /* Save PCI command register before chip reset */
8872 static void tg3_save_pci_state(struct tg3 *tp)
8874 pci_read_config_word(tp->pdev, PCI_COMMAND, &tp->pci_cmd);
8877 /* Restore PCI state after chip reset */
8878 static void tg3_restore_pci_state(struct tg3 *tp)
8882 /* Re-enable indirect register accesses. */
8883 pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
8884 tp->misc_host_ctrl);
8886 /* Set MAX PCI retry to zero. */
8887 val = (PCISTATE_ROM_ENABLE | PCISTATE_ROM_RETRY_ENABLE);
8888 if (tg3_chip_rev_id(tp) == CHIPREV_ID_5704_A0 &&
8889 tg3_flag(tp, PCIX_MODE))
8890 val |= PCISTATE_RETRY_SAME_DMA;
8891 /* Allow reads and writes to the APE register and memory space. */
8892 if (tg3_flag(tp, ENABLE_APE))
8893 val |= PCISTATE_ALLOW_APE_CTLSPC_WR |
8894 PCISTATE_ALLOW_APE_SHMEM_WR |
8895 PCISTATE_ALLOW_APE_PSPACE_WR;
8896 pci_write_config_dword(tp->pdev, TG3PCI_PCISTATE, val);
8898 pci_write_config_word(tp->pdev, PCI_COMMAND, tp->pci_cmd);
8900 if (!tg3_flag(tp, PCI_EXPRESS)) {
8901 pci_write_config_byte(tp->pdev, PCI_CACHE_LINE_SIZE,
8902 tp->pci_cacheline_sz);
8903 pci_write_config_byte(tp->pdev, PCI_LATENCY_TIMER,
8907 /* Make sure PCI-X relaxed ordering bit is clear. */
8908 if (tg3_flag(tp, PCIX_MODE)) {
8911 pci_read_config_word(tp->pdev, tp->pcix_cap + PCI_X_CMD,
8913 pcix_cmd &= ~PCI_X_CMD_ERO;
8914 pci_write_config_word(tp->pdev, tp->pcix_cap + PCI_X_CMD,
8918 if (tg3_flag(tp, 5780_CLASS)) {
8920 /* Chip reset on 5780 will reset MSI enable bit,
8921 * so need to restore it.
8923 if (tg3_flag(tp, USING_MSI)) {
8926 pci_read_config_word(tp->pdev,
8927 tp->msi_cap + PCI_MSI_FLAGS,
8929 pci_write_config_word(tp->pdev,
8930 tp->msi_cap + PCI_MSI_FLAGS,
8931 ctrl | PCI_MSI_FLAGS_ENABLE);
8932 val = tr32(MSGINT_MODE);
8933 tw32(MSGINT_MODE, val | MSGINT_MODE_ENABLE);
8938 static void tg3_override_clk(struct tg3 *tp)
8942 switch (tg3_asic_rev(tp)) {
8944 val = tr32(TG3_CPMU_CLCK_ORIDE_ENABLE);
8945 tw32(TG3_CPMU_CLCK_ORIDE_ENABLE, val |
8946 TG3_CPMU_MAC_ORIDE_ENABLE);
8951 tw32(TG3_CPMU_CLCK_ORIDE, CPMU_CLCK_ORIDE_MAC_ORIDE_EN);
8959 static void tg3_restore_clk(struct tg3 *tp)
8963 switch (tg3_asic_rev(tp)) {
8965 val = tr32(TG3_CPMU_CLCK_ORIDE_ENABLE);
8966 tw32(TG3_CPMU_CLCK_ORIDE_ENABLE,
8967 val & ~TG3_CPMU_MAC_ORIDE_ENABLE);
8972 val = tr32(TG3_CPMU_CLCK_ORIDE);
8973 tw32(TG3_CPMU_CLCK_ORIDE, val & ~CPMU_CLCK_ORIDE_MAC_ORIDE_EN);
8981 /* tp->lock is held. */
8982 static int tg3_chip_reset(struct tg3 *tp)
8985 void (*write_op)(struct tg3 *, u32, u32);
8988 if (!pci_device_is_present(tp->pdev))
8993 tg3_ape_lock(tp, TG3_APE_LOCK_GRC);
8995 /* No matching tg3_nvram_unlock() after this because
8996 * chip reset below will undo the nvram lock.
8998 tp->nvram_lock_cnt = 0;
9000 /* GRC_MISC_CFG core clock reset will clear the memory
9001 * enable bit in PCI register 4 and the MSI enable bit
9002 * on some chips, so we save relevant registers here.
9004 tg3_save_pci_state(tp);
9006 if (tg3_asic_rev(tp) == ASIC_REV_5752 ||
9007 tg3_flag(tp, 5755_PLUS))
9008 tw32(GRC_FASTBOOT_PC, 0);
9011 * We must avoid the readl() that normally takes place.
9012 * It locks machines, causes machine checks, and other
9013 * fun things. So, temporarily disable the 5701
9014 * hardware workaround, while we do the reset.
9016 write_op = tp->write32;
9017 if (write_op == tg3_write_flush_reg32)
9018 tp->write32 = tg3_write32;
9020 /* Prevent the irq handler from reading or writing PCI registers
9021 * during chip reset when the memory enable bit in the PCI command
9022 * register may be cleared. The chip does not generate interrupt
9023 * at this time, but the irq handler may still be called due to irq
9024 * sharing or irqpoll.
9026 tg3_flag_set(tp, CHIP_RESETTING);
9027 for (i = 0; i < tp->irq_cnt; i++) {
9028 struct tg3_napi *tnapi = &tp->napi[i];
9029 if (tnapi->hw_status) {
9030 tnapi->hw_status->status = 0;
9031 tnapi->hw_status->status_tag = 0;
9033 tnapi->last_tag = 0;
9034 tnapi->last_irq_tag = 0;
9038 for (i = 0; i < tp->irq_cnt; i++)
9039 synchronize_irq(tp->napi[i].irq_vec);
9041 if (tg3_asic_rev(tp) == ASIC_REV_57780) {
9042 val = tr32(TG3_PCIE_LNKCTL) & ~TG3_PCIE_LNKCTL_L1_PLL_PD_EN;
9043 tw32(TG3_PCIE_LNKCTL, val | TG3_PCIE_LNKCTL_L1_PLL_PD_DIS);
9047 val = GRC_MISC_CFG_CORECLK_RESET;
9049 if (tg3_flag(tp, PCI_EXPRESS)) {
9050 /* Force PCIe 1.0a mode */
9051 if (tg3_asic_rev(tp) != ASIC_REV_5785 &&
9052 !tg3_flag(tp, 57765_PLUS) &&
9053 tr32(TG3_PCIE_PHY_TSTCTL) ==
9054 (TG3_PCIE_PHY_TSTCTL_PCIE10 | TG3_PCIE_PHY_TSTCTL_PSCRAM))
9055 tw32(TG3_PCIE_PHY_TSTCTL, TG3_PCIE_PHY_TSTCTL_PSCRAM);
9057 if (tg3_chip_rev_id(tp) != CHIPREV_ID_5750_A0) {
9058 tw32(GRC_MISC_CFG, (1 << 29));
9063 if (tg3_asic_rev(tp) == ASIC_REV_5906) {
9064 tw32(VCPU_STATUS, tr32(VCPU_STATUS) | VCPU_STATUS_DRV_RESET);
9065 tw32(GRC_VCPU_EXT_CTRL,
9066 tr32(GRC_VCPU_EXT_CTRL) & ~GRC_VCPU_EXT_CTRL_HALT_CPU);
9069 /* Set the clock to the highest frequency to avoid timeouts. With link
9070 * aware mode, the clock speed could be slow and bootcode does not
9071 * complete within the expected time. Override the clock to allow the
9072 * bootcode to finish sooner and then restore it.
9074 tg3_override_clk(tp);
9076 /* Manage gphy power for all CPMU absent PCIe devices. */
9077 if (tg3_flag(tp, 5705_PLUS) && !tg3_flag(tp, CPMU_PRESENT))
9078 val |= GRC_MISC_CFG_KEEP_GPHY_POWER;
9080 tw32(GRC_MISC_CFG, val);
9082 /* restore 5701 hardware bug workaround write method */
9083 tp->write32 = write_op;
9085 /* Unfortunately, we have to delay before the PCI read back.
9086 * Some 575X chips even will not respond to a PCI cfg access
9087 * when the reset command is given to the chip.
9089 * How do these hardware designers expect things to work
9090 * properly if the PCI write is posted for a long period
9091 * of time? It is always necessary to have some method by
9092 * which a register read back can occur to push the write
9093 * out which does the reset.
9095 * For most tg3 variants the trick below was working.
9100 /* Flush PCI posted writes. The normal MMIO registers
9101 * are inaccessible at this time so this is the only
9102 * way to make this reliably (actually, this is no longer
9103 * the case, see above). I tried to use indirect
9104 * register read/write but this upset some 5701 variants.
9106 pci_read_config_dword(tp->pdev, PCI_COMMAND, &val);
9110 if (tg3_flag(tp, PCI_EXPRESS) && pci_is_pcie(tp->pdev)) {
9113 if (tg3_chip_rev_id(tp) == CHIPREV_ID_5750_A0) {
9117 /* Wait for link training to complete. */
9118 for (j = 0; j < 5000; j++)
9121 pci_read_config_dword(tp->pdev, 0xc4, &cfg_val);
9122 pci_write_config_dword(tp->pdev, 0xc4,
9123 cfg_val | (1 << 15));
9126 /* Clear the "no snoop" and "relaxed ordering" bits. */
9127 val16 = PCI_EXP_DEVCTL_RELAX_EN | PCI_EXP_DEVCTL_NOSNOOP_EN;
9129 * Older PCIe devices only support the 128 byte
9130 * MPS setting. Enforce the restriction.
9132 if (!tg3_flag(tp, CPMU_PRESENT))
9133 val16 |= PCI_EXP_DEVCTL_PAYLOAD;
9134 pcie_capability_clear_word(tp->pdev, PCI_EXP_DEVCTL, val16);
9136 /* Clear error status */
9137 pcie_capability_write_word(tp->pdev, PCI_EXP_DEVSTA,
9138 PCI_EXP_DEVSTA_CED |
9139 PCI_EXP_DEVSTA_NFED |
9140 PCI_EXP_DEVSTA_FED |
9141 PCI_EXP_DEVSTA_URD);
9144 tg3_restore_pci_state(tp);
9146 tg3_flag_clear(tp, CHIP_RESETTING);
9147 tg3_flag_clear(tp, ERROR_PROCESSED);
9150 if (tg3_flag(tp, 5780_CLASS))
9151 val = tr32(MEMARB_MODE);
9152 tw32(MEMARB_MODE, val | MEMARB_MODE_ENABLE);
9154 if (tg3_chip_rev_id(tp) == CHIPREV_ID_5750_A3) {
9156 tw32(0x5000, 0x400);
9159 if (tg3_flag(tp, IS_SSB_CORE)) {
9161 * BCM4785: In order to avoid repercussions from using
9162 * potentially defective internal ROM, stop the Rx RISC CPU,
9163 * which is not required.
9166 tg3_halt_cpu(tp, RX_CPU_BASE);
9169 err = tg3_poll_fw(tp);
9173 tw32(GRC_MODE, tp->grc_mode);
9175 if (tg3_chip_rev_id(tp) == CHIPREV_ID_5705_A0) {
9178 tw32(0xc4, val | (1 << 15));
9181 if ((tp->nic_sram_data_cfg & NIC_SRAM_DATA_CFG_MINI_PCI) != 0 &&
9182 tg3_asic_rev(tp) == ASIC_REV_5705) {
9183 tp->pci_clock_ctrl |= CLOCK_CTRL_CLKRUN_OENABLE;
9184 if (tg3_chip_rev_id(tp) == CHIPREV_ID_5705_A0)
9185 tp->pci_clock_ctrl |= CLOCK_CTRL_FORCE_CLKRUN;
9186 tw32(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl);
9189 if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES) {
9190 tp->mac_mode = MAC_MODE_PORT_MODE_TBI;
9192 } else if (tp->phy_flags & TG3_PHYFLG_MII_SERDES) {
9193 tp->mac_mode = MAC_MODE_PORT_MODE_GMII;
9198 tw32_f(MAC_MODE, val);
9201 tg3_ape_unlock(tp, TG3_APE_LOCK_GRC);
9205 if (tg3_flag(tp, PCI_EXPRESS) &&
9206 tg3_chip_rev_id(tp) != CHIPREV_ID_5750_A0 &&
9207 tg3_asic_rev(tp) != ASIC_REV_5785 &&
9208 !tg3_flag(tp, 57765_PLUS)) {
9211 tw32(0x7c00, val | (1 << 25));
9214 tg3_restore_clk(tp);
9216 /* Reprobe ASF enable state. */
9217 tg3_flag_clear(tp, ENABLE_ASF);
9218 tp->phy_flags &= ~(TG3_PHYFLG_1G_ON_VAUX_OK |
9219 TG3_PHYFLG_KEEP_LINK_ON_PWRDN);
9221 tg3_flag_clear(tp, ASF_NEW_HANDSHAKE);
9222 tg3_read_mem(tp, NIC_SRAM_DATA_SIG, &val);
9223 if (val == NIC_SRAM_DATA_SIG_MAGIC) {
9226 tg3_read_mem(tp, NIC_SRAM_DATA_CFG, &nic_cfg);
9227 if (nic_cfg & NIC_SRAM_DATA_CFG_ASF_ENABLE) {
9228 tg3_flag_set(tp, ENABLE_ASF);
9229 tp->last_event_jiffies = jiffies;
9230 if (tg3_flag(tp, 5750_PLUS))
9231 tg3_flag_set(tp, ASF_NEW_HANDSHAKE);
9233 tg3_read_mem(tp, NIC_SRAM_DATA_CFG_3, &nic_cfg);
9234 if (nic_cfg & NIC_SRAM_1G_ON_VAUX_OK)
9235 tp->phy_flags |= TG3_PHYFLG_1G_ON_VAUX_OK;
9236 if (nic_cfg & NIC_SRAM_LNK_FLAP_AVOID)
9237 tp->phy_flags |= TG3_PHYFLG_KEEP_LINK_ON_PWRDN;
9244 static void tg3_get_nstats(struct tg3 *, struct rtnl_link_stats64 *);
9245 static void tg3_get_estats(struct tg3 *, struct tg3_ethtool_stats *);
9246 static void __tg3_set_rx_mode(struct net_device *);
9248 /* tp->lock is held. */
9249 static int tg3_halt(struct tg3 *tp, int kind, bool silent)
9255 tg3_write_sig_pre_reset(tp, kind);
9257 tg3_abort_hw(tp, silent);
9258 err = tg3_chip_reset(tp);
9260 __tg3_set_mac_addr(tp, false);
9262 tg3_write_sig_legacy(tp, kind);
9263 tg3_write_sig_post_reset(tp, kind);
9266 /* Save the stats across chip resets... */
9267 tg3_get_nstats(tp, &tp->net_stats_prev);
9268 tg3_get_estats(tp, &tp->estats_prev);
9270 /* And make sure the next sample is new data */
9271 memset(tp->hw_stats, 0, sizeof(struct tg3_hw_stats));
9277 static int tg3_set_mac_addr(struct net_device *dev, void *p)
9279 struct tg3 *tp = netdev_priv(dev);
9280 struct sockaddr *addr = p;
9282 bool skip_mac_1 = false;
9284 if (!is_valid_ether_addr(addr->sa_data))
9285 return -EADDRNOTAVAIL;
9287 memcpy(dev->dev_addr, addr->sa_data, dev->addr_len);
9289 if (!netif_running(dev))
9292 if (tg3_flag(tp, ENABLE_ASF)) {
9293 u32 addr0_high, addr0_low, addr1_high, addr1_low;
9295 addr0_high = tr32(MAC_ADDR_0_HIGH);
9296 addr0_low = tr32(MAC_ADDR_0_LOW);
9297 addr1_high = tr32(MAC_ADDR_1_HIGH);
9298 addr1_low = tr32(MAC_ADDR_1_LOW);
9300 /* Skip MAC addr 1 if ASF is using it. */
9301 if ((addr0_high != addr1_high || addr0_low != addr1_low) &&
9302 !(addr1_high == 0 && addr1_low == 0))
9305 spin_lock_bh(&tp->lock);
9306 __tg3_set_mac_addr(tp, skip_mac_1);
9307 __tg3_set_rx_mode(dev);
9308 spin_unlock_bh(&tp->lock);
9313 /* tp->lock is held. */
9314 static void tg3_set_bdinfo(struct tg3 *tp, u32 bdinfo_addr,
9315 dma_addr_t mapping, u32 maxlen_flags,
9319 (bdinfo_addr + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_HIGH),
9320 ((u64) mapping >> 32));
9322 (bdinfo_addr + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_LOW),
9323 ((u64) mapping & 0xffffffff));
9325 (bdinfo_addr + TG3_BDINFO_MAXLEN_FLAGS),
9328 if (!tg3_flag(tp, 5705_PLUS))
9330 (bdinfo_addr + TG3_BDINFO_NIC_ADDR),
9335 static void tg3_coal_tx_init(struct tg3 *tp, struct ethtool_coalesce *ec)
9339 if (!tg3_flag(tp, ENABLE_TSS)) {
9340 tw32(HOSTCC_TXCOL_TICKS, ec->tx_coalesce_usecs);
9341 tw32(HOSTCC_TXMAX_FRAMES, ec->tx_max_coalesced_frames);
9342 tw32(HOSTCC_TXCOAL_MAXF_INT, ec->tx_max_coalesced_frames_irq);
9344 tw32(HOSTCC_TXCOL_TICKS, 0);
9345 tw32(HOSTCC_TXMAX_FRAMES, 0);
9346 tw32(HOSTCC_TXCOAL_MAXF_INT, 0);
9348 for (; i < tp->txq_cnt; i++) {
9351 reg = HOSTCC_TXCOL_TICKS_VEC1 + i * 0x18;
9352 tw32(reg, ec->tx_coalesce_usecs);
9353 reg = HOSTCC_TXMAX_FRAMES_VEC1 + i * 0x18;
9354 tw32(reg, ec->tx_max_coalesced_frames);
9355 reg = HOSTCC_TXCOAL_MAXF_INT_VEC1 + i * 0x18;
9356 tw32(reg, ec->tx_max_coalesced_frames_irq);
9360 for (; i < tp->irq_max - 1; i++) {
9361 tw32(HOSTCC_TXCOL_TICKS_VEC1 + i * 0x18, 0);
9362 tw32(HOSTCC_TXMAX_FRAMES_VEC1 + i * 0x18, 0);
9363 tw32(HOSTCC_TXCOAL_MAXF_INT_VEC1 + i * 0x18, 0);
9367 static void tg3_coal_rx_init(struct tg3 *tp, struct ethtool_coalesce *ec)
9370 u32 limit = tp->rxq_cnt;
9372 if (!tg3_flag(tp, ENABLE_RSS)) {
9373 tw32(HOSTCC_RXCOL_TICKS, ec->rx_coalesce_usecs);
9374 tw32(HOSTCC_RXMAX_FRAMES, ec->rx_max_coalesced_frames);
9375 tw32(HOSTCC_RXCOAL_MAXF_INT, ec->rx_max_coalesced_frames_irq);
9378 tw32(HOSTCC_RXCOL_TICKS, 0);
9379 tw32(HOSTCC_RXMAX_FRAMES, 0);
9380 tw32(HOSTCC_RXCOAL_MAXF_INT, 0);
9383 for (; i < limit; i++) {
9386 reg = HOSTCC_RXCOL_TICKS_VEC1 + i * 0x18;
9387 tw32(reg, ec->rx_coalesce_usecs);
9388 reg = HOSTCC_RXMAX_FRAMES_VEC1 + i * 0x18;
9389 tw32(reg, ec->rx_max_coalesced_frames);
9390 reg = HOSTCC_RXCOAL_MAXF_INT_VEC1 + i * 0x18;
9391 tw32(reg, ec->rx_max_coalesced_frames_irq);
9394 for (; i < tp->irq_max - 1; i++) {
9395 tw32(HOSTCC_RXCOL_TICKS_VEC1 + i * 0x18, 0);
9396 tw32(HOSTCC_RXMAX_FRAMES_VEC1 + i * 0x18, 0);
9397 tw32(HOSTCC_RXCOAL_MAXF_INT_VEC1 + i * 0x18, 0);
9401 static void __tg3_set_coalesce(struct tg3 *tp, struct ethtool_coalesce *ec)
9403 tg3_coal_tx_init(tp, ec);
9404 tg3_coal_rx_init(tp, ec);
9406 if (!tg3_flag(tp, 5705_PLUS)) {
9407 u32 val = ec->stats_block_coalesce_usecs;
9409 tw32(HOSTCC_RXCOAL_TICK_INT, ec->rx_coalesce_usecs_irq);
9410 tw32(HOSTCC_TXCOAL_TICK_INT, ec->tx_coalesce_usecs_irq);
9415 tw32(HOSTCC_STAT_COAL_TICKS, val);
9419 /* tp->lock is held. */
9420 static void tg3_tx_rcbs_disable(struct tg3 *tp)
9424 /* Disable all transmit rings but the first. */
9425 if (!tg3_flag(tp, 5705_PLUS))
9426 limit = NIC_SRAM_SEND_RCB + TG3_BDINFO_SIZE * 16;
9427 else if (tg3_flag(tp, 5717_PLUS))
9428 limit = NIC_SRAM_SEND_RCB + TG3_BDINFO_SIZE * 4;
9429 else if (tg3_flag(tp, 57765_CLASS) ||
9430 tg3_asic_rev(tp) == ASIC_REV_5762)
9431 limit = NIC_SRAM_SEND_RCB + TG3_BDINFO_SIZE * 2;
9433 limit = NIC_SRAM_SEND_RCB + TG3_BDINFO_SIZE;
9435 for (txrcb = NIC_SRAM_SEND_RCB + TG3_BDINFO_SIZE;
9436 txrcb < limit; txrcb += TG3_BDINFO_SIZE)
9437 tg3_write_mem(tp, txrcb + TG3_BDINFO_MAXLEN_FLAGS,
9438 BDINFO_FLAGS_DISABLED);
9441 /* tp->lock is held. */
9442 static void tg3_tx_rcbs_init(struct tg3 *tp)
9445 u32 txrcb = NIC_SRAM_SEND_RCB;
9447 if (tg3_flag(tp, ENABLE_TSS))
9450 for (; i < tp->irq_max; i++, txrcb += TG3_BDINFO_SIZE) {
9451 struct tg3_napi *tnapi = &tp->napi[i];
9453 if (!tnapi->tx_ring)
9456 tg3_set_bdinfo(tp, txrcb, tnapi->tx_desc_mapping,
9457 (TG3_TX_RING_SIZE << BDINFO_FLAGS_MAXLEN_SHIFT),
9458 NIC_SRAM_TX_BUFFER_DESC);
9462 /* tp->lock is held. */
9463 static void tg3_rx_ret_rcbs_disable(struct tg3 *tp)
9467 /* Disable all receive return rings but the first. */
9468 if (tg3_flag(tp, 5717_PLUS))
9469 limit = NIC_SRAM_RCV_RET_RCB + TG3_BDINFO_SIZE * 17;
9470 else if (!tg3_flag(tp, 5705_PLUS))
9471 limit = NIC_SRAM_RCV_RET_RCB + TG3_BDINFO_SIZE * 16;
9472 else if (tg3_asic_rev(tp) == ASIC_REV_5755 ||
9473 tg3_asic_rev(tp) == ASIC_REV_5762 ||
9474 tg3_flag(tp, 57765_CLASS))
9475 limit = NIC_SRAM_RCV_RET_RCB + TG3_BDINFO_SIZE * 4;
9477 limit = NIC_SRAM_RCV_RET_RCB + TG3_BDINFO_SIZE;
9479 for (rxrcb = NIC_SRAM_RCV_RET_RCB + TG3_BDINFO_SIZE;
9480 rxrcb < limit; rxrcb += TG3_BDINFO_SIZE)
9481 tg3_write_mem(tp, rxrcb + TG3_BDINFO_MAXLEN_FLAGS,
9482 BDINFO_FLAGS_DISABLED);
9485 /* tp->lock is held. */
9486 static void tg3_rx_ret_rcbs_init(struct tg3 *tp)
9489 u32 rxrcb = NIC_SRAM_RCV_RET_RCB;
9491 if (tg3_flag(tp, ENABLE_RSS))
9494 for (; i < tp->irq_max; i++, rxrcb += TG3_BDINFO_SIZE) {
9495 struct tg3_napi *tnapi = &tp->napi[i];
9500 tg3_set_bdinfo(tp, rxrcb, tnapi->rx_rcb_mapping,
9501 (tp->rx_ret_ring_mask + 1) <<
9502 BDINFO_FLAGS_MAXLEN_SHIFT, 0);
9506 /* tp->lock is held. */
9507 static void tg3_rings_reset(struct tg3 *tp)
9511 struct tg3_napi *tnapi = &tp->napi[0];
9513 tg3_tx_rcbs_disable(tp);
9515 tg3_rx_ret_rcbs_disable(tp);
9517 /* Disable interrupts */
9518 tw32_mailbox_f(tp->napi[0].int_mbox, 1);
9519 tp->napi[0].chk_msi_cnt = 0;
9520 tp->napi[0].last_rx_cons = 0;
9521 tp->napi[0].last_tx_cons = 0;
9523 /* Zero mailbox registers. */
9524 if (tg3_flag(tp, SUPPORT_MSIX)) {
9525 for (i = 1; i < tp->irq_max; i++) {
9526 tp->napi[i].tx_prod = 0;
9527 tp->napi[i].tx_cons = 0;
9528 if (tg3_flag(tp, ENABLE_TSS))
9529 tw32_mailbox(tp->napi[i].prodmbox, 0);
9530 tw32_rx_mbox(tp->napi[i].consmbox, 0);
9531 tw32_mailbox_f(tp->napi[i].int_mbox, 1);
9532 tp->napi[i].chk_msi_cnt = 0;
9533 tp->napi[i].last_rx_cons = 0;
9534 tp->napi[i].last_tx_cons = 0;
9536 if (!tg3_flag(tp, ENABLE_TSS))
9537 tw32_mailbox(tp->napi[0].prodmbox, 0);
9539 tp->napi[0].tx_prod = 0;
9540 tp->napi[0].tx_cons = 0;
9541 tw32_mailbox(tp->napi[0].prodmbox, 0);
9542 tw32_rx_mbox(tp->napi[0].consmbox, 0);
9545 /* Make sure the NIC-based send BD rings are disabled. */
9546 if (!tg3_flag(tp, 5705_PLUS)) {
9547 u32 mbox = MAILBOX_SNDNIC_PROD_IDX_0 + TG3_64BIT_REG_LOW;
9548 for (i = 0; i < 16; i++)
9549 tw32_tx_mbox(mbox + i * 8, 0);
9552 /* Clear status block in ram. */
9553 memset(tnapi->hw_status, 0, TG3_HW_STATUS_SIZE);
9555 /* Set status block DMA address */
9556 tw32(HOSTCC_STATUS_BLK_HOST_ADDR + TG3_64BIT_REG_HIGH,
9557 ((u64) tnapi->status_mapping >> 32));
9558 tw32(HOSTCC_STATUS_BLK_HOST_ADDR + TG3_64BIT_REG_LOW,
9559 ((u64) tnapi->status_mapping & 0xffffffff));
9561 stblk = HOSTCC_STATBLCK_RING1;
9563 for (i = 1, tnapi++; i < tp->irq_cnt; i++, tnapi++) {
9564 u64 mapping = (u64)tnapi->status_mapping;
9565 tw32(stblk + TG3_64BIT_REG_HIGH, mapping >> 32);
9566 tw32(stblk + TG3_64BIT_REG_LOW, mapping & 0xffffffff);
9569 /* Clear status block in ram. */
9570 memset(tnapi->hw_status, 0, TG3_HW_STATUS_SIZE);
9573 tg3_tx_rcbs_init(tp);
9574 tg3_rx_ret_rcbs_init(tp);
9577 static void tg3_setup_rxbd_thresholds(struct tg3 *tp)
9579 u32 val, bdcache_maxcnt, host_rep_thresh, nic_rep_thresh;
9581 if (!tg3_flag(tp, 5750_PLUS) ||
9582 tg3_flag(tp, 5780_CLASS) ||
9583 tg3_asic_rev(tp) == ASIC_REV_5750 ||
9584 tg3_asic_rev(tp) == ASIC_REV_5752 ||
9585 tg3_flag(tp, 57765_PLUS))
9586 bdcache_maxcnt = TG3_SRAM_RX_STD_BDCACHE_SIZE_5700;
9587 else if (tg3_asic_rev(tp) == ASIC_REV_5755 ||
9588 tg3_asic_rev(tp) == ASIC_REV_5787)
9589 bdcache_maxcnt = TG3_SRAM_RX_STD_BDCACHE_SIZE_5755;
9591 bdcache_maxcnt = TG3_SRAM_RX_STD_BDCACHE_SIZE_5906;
9593 nic_rep_thresh = min(bdcache_maxcnt / 2, tp->rx_std_max_post);
9594 host_rep_thresh = max_t(u32, tp->rx_pending / 8, 1);
9596 val = min(nic_rep_thresh, host_rep_thresh);
9597 tw32(RCVBDI_STD_THRESH, val);
9599 if (tg3_flag(tp, 57765_PLUS))
9600 tw32(STD_REPLENISH_LWM, bdcache_maxcnt);
9602 if (!tg3_flag(tp, JUMBO_CAPABLE) || tg3_flag(tp, 5780_CLASS))
9605 bdcache_maxcnt = TG3_SRAM_RX_JMB_BDCACHE_SIZE_5700;
9607 host_rep_thresh = max_t(u32, tp->rx_jumbo_pending / 8, 1);
9609 val = min(bdcache_maxcnt / 2, host_rep_thresh);
9610 tw32(RCVBDI_JUMBO_THRESH, val);
9612 if (tg3_flag(tp, 57765_PLUS))
9613 tw32(JMB_REPLENISH_LWM, bdcache_maxcnt);
9616 static inline u32 calc_crc(unsigned char *buf, int len)
9624 for (j = 0; j < len; j++) {
9627 for (k = 0; k < 8; k++) {
9640 static void tg3_set_multi(struct tg3 *tp, unsigned int accept_all)
9642 /* accept or reject all multicast frames */
9643 tw32(MAC_HASH_REG_0, accept_all ? 0xffffffff : 0);
9644 tw32(MAC_HASH_REG_1, accept_all ? 0xffffffff : 0);
9645 tw32(MAC_HASH_REG_2, accept_all ? 0xffffffff : 0);
9646 tw32(MAC_HASH_REG_3, accept_all ? 0xffffffff : 0);
9649 static void __tg3_set_rx_mode(struct net_device *dev)
9651 struct tg3 *tp = netdev_priv(dev);
9654 rx_mode = tp->rx_mode & ~(RX_MODE_PROMISC |
9655 RX_MODE_KEEP_VLAN_TAG);
9657 #if !defined(CONFIG_VLAN_8021Q) && !defined(CONFIG_VLAN_8021Q_MODULE)
9658 /* When ASF is in use, we always keep the RX_MODE_KEEP_VLAN_TAG
9661 if (!tg3_flag(tp, ENABLE_ASF))
9662 rx_mode |= RX_MODE_KEEP_VLAN_TAG;
9665 if (dev->flags & IFF_PROMISC) {
9666 /* Promiscuous mode. */
9667 rx_mode |= RX_MODE_PROMISC;
9668 } else if (dev->flags & IFF_ALLMULTI) {
9669 /* Accept all multicast. */
9670 tg3_set_multi(tp, 1);
9671 } else if (netdev_mc_empty(dev)) {
9672 /* Reject all multicast. */
9673 tg3_set_multi(tp, 0);
9675 /* Accept one or more multicast(s). */
9676 struct netdev_hw_addr *ha;
9677 u32 mc_filter[4] = { 0, };
9682 netdev_for_each_mc_addr(ha, dev) {
9683 crc = calc_crc(ha->addr, ETH_ALEN);
9685 regidx = (bit & 0x60) >> 5;
9687 mc_filter[regidx] |= (1 << bit);
9690 tw32(MAC_HASH_REG_0, mc_filter[0]);
9691 tw32(MAC_HASH_REG_1, mc_filter[1]);
9692 tw32(MAC_HASH_REG_2, mc_filter[2]);
9693 tw32(MAC_HASH_REG_3, mc_filter[3]);
9696 if (netdev_uc_count(dev) > TG3_MAX_UCAST_ADDR(tp)) {
9697 rx_mode |= RX_MODE_PROMISC;
9698 } else if (!(dev->flags & IFF_PROMISC)) {
9699 /* Add all entries into to the mac addr filter list */
9701 struct netdev_hw_addr *ha;
9703 netdev_for_each_uc_addr(ha, dev) {
9704 __tg3_set_one_mac_addr(tp, ha->addr,
9705 i + TG3_UCAST_ADDR_IDX(tp));
9710 if (rx_mode != tp->rx_mode) {
9711 tp->rx_mode = rx_mode;
9712 tw32_f(MAC_RX_MODE, rx_mode);
9717 static void tg3_rss_init_dflt_indir_tbl(struct tg3 *tp, u32 qcnt)
9721 for (i = 0; i < TG3_RSS_INDIR_TBL_SIZE; i++)
9722 tp->rss_ind_tbl[i] = ethtool_rxfh_indir_default(i, qcnt);
9725 static void tg3_rss_check_indir_tbl(struct tg3 *tp)
9729 if (!tg3_flag(tp, SUPPORT_MSIX))
9732 if (tp->rxq_cnt == 1) {
9733 memset(&tp->rss_ind_tbl[0], 0, sizeof(tp->rss_ind_tbl));
9737 /* Validate table against current IRQ count */
9738 for (i = 0; i < TG3_RSS_INDIR_TBL_SIZE; i++) {
9739 if (tp->rss_ind_tbl[i] >= tp->rxq_cnt)
9743 if (i != TG3_RSS_INDIR_TBL_SIZE)
9744 tg3_rss_init_dflt_indir_tbl(tp, tp->rxq_cnt);
9747 static void tg3_rss_write_indir_tbl(struct tg3 *tp)
9750 u32 reg = MAC_RSS_INDIR_TBL_0;
9752 while (i < TG3_RSS_INDIR_TBL_SIZE) {
9753 u32 val = tp->rss_ind_tbl[i];
9755 for (; i % 8; i++) {
9757 val |= tp->rss_ind_tbl[i];
9764 static inline u32 tg3_lso_rd_dma_workaround_bit(struct tg3 *tp)
9766 if (tg3_asic_rev(tp) == ASIC_REV_5719)
9767 return TG3_LSO_RD_DMA_TX_LENGTH_WA_5719;
9769 return TG3_LSO_RD_DMA_TX_LENGTH_WA_5720;
9772 /* tp->lock is held. */
9773 static int tg3_reset_hw(struct tg3 *tp, bool reset_phy)
9775 u32 val, rdmac_mode;
9777 struct tg3_rx_prodring_set *tpr = &tp->napi[0].prodring;
9779 tg3_disable_ints(tp);
9783 tg3_write_sig_pre_reset(tp, RESET_KIND_INIT);
9785 if (tg3_flag(tp, INIT_COMPLETE))
9786 tg3_abort_hw(tp, 1);
9788 if ((tp->phy_flags & TG3_PHYFLG_KEEP_LINK_ON_PWRDN) &&
9789 !(tp->phy_flags & TG3_PHYFLG_USER_CONFIGURED)) {
9790 tg3_phy_pull_config(tp);
9791 tg3_eee_pull_config(tp, NULL);
9792 tp->phy_flags |= TG3_PHYFLG_USER_CONFIGURED;
9795 /* Enable MAC control of LPI */
9796 if (tp->phy_flags & TG3_PHYFLG_EEE_CAP)
9802 err = tg3_chip_reset(tp);
9806 tg3_write_sig_legacy(tp, RESET_KIND_INIT);
9808 if (tg3_chip_rev(tp) == CHIPREV_5784_AX) {
9809 val = tr32(TG3_CPMU_CTRL);
9810 val &= ~(CPMU_CTRL_LINK_AWARE_MODE | CPMU_CTRL_LINK_IDLE_MODE);
9811 tw32(TG3_CPMU_CTRL, val);
9813 val = tr32(TG3_CPMU_LSPD_10MB_CLK);
9814 val &= ~CPMU_LSPD_10MB_MACCLK_MASK;
9815 val |= CPMU_LSPD_10MB_MACCLK_6_25;
9816 tw32(TG3_CPMU_LSPD_10MB_CLK, val);
9818 val = tr32(TG3_CPMU_LNK_AWARE_PWRMD);
9819 val &= ~CPMU_LNK_AWARE_MACCLK_MASK;
9820 val |= CPMU_LNK_AWARE_MACCLK_6_25;
9821 tw32(TG3_CPMU_LNK_AWARE_PWRMD, val);
9823 val = tr32(TG3_CPMU_HST_ACC);
9824 val &= ~CPMU_HST_ACC_MACCLK_MASK;
9825 val |= CPMU_HST_ACC_MACCLK_6_25;
9826 tw32(TG3_CPMU_HST_ACC, val);
9829 if (tg3_asic_rev(tp) == ASIC_REV_57780) {
9830 val = tr32(PCIE_PWR_MGMT_THRESH) & ~PCIE_PWR_MGMT_L1_THRESH_MSK;
9831 val |= PCIE_PWR_MGMT_EXT_ASPM_TMR_EN |
9832 PCIE_PWR_MGMT_L1_THRESH_4MS;
9833 tw32(PCIE_PWR_MGMT_THRESH, val);
9835 val = tr32(TG3_PCIE_EIDLE_DELAY) & ~TG3_PCIE_EIDLE_DELAY_MASK;
9836 tw32(TG3_PCIE_EIDLE_DELAY, val | TG3_PCIE_EIDLE_DELAY_13_CLKS);
9838 tw32(TG3_CORR_ERR_STAT, TG3_CORR_ERR_STAT_CLEAR);
9840 val = tr32(TG3_PCIE_LNKCTL) & ~TG3_PCIE_LNKCTL_L1_PLL_PD_EN;
9841 tw32(TG3_PCIE_LNKCTL, val | TG3_PCIE_LNKCTL_L1_PLL_PD_DIS);
9844 if (tg3_flag(tp, L1PLLPD_EN)) {
9845 u32 grc_mode = tr32(GRC_MODE);
9847 /* Access the lower 1K of PL PCIE block registers. */
9848 val = grc_mode & ~GRC_MODE_PCIE_PORT_MASK;
9849 tw32(GRC_MODE, val | GRC_MODE_PCIE_PL_SEL);
9851 val = tr32(TG3_PCIE_TLDLPL_PORT + TG3_PCIE_PL_LO_PHYCTL1);
9852 tw32(TG3_PCIE_TLDLPL_PORT + TG3_PCIE_PL_LO_PHYCTL1,
9853 val | TG3_PCIE_PL_LO_PHYCTL1_L1PLLPD_EN);
9855 tw32(GRC_MODE, grc_mode);
9858 if (tg3_flag(tp, 57765_CLASS)) {
9859 if (tg3_chip_rev_id(tp) == CHIPREV_ID_57765_A0) {
9860 u32 grc_mode = tr32(GRC_MODE);
9862 /* Access the lower 1K of PL PCIE block registers. */
9863 val = grc_mode & ~GRC_MODE_PCIE_PORT_MASK;
9864 tw32(GRC_MODE, val | GRC_MODE_PCIE_PL_SEL);
9866 val = tr32(TG3_PCIE_TLDLPL_PORT +
9867 TG3_PCIE_PL_LO_PHYCTL5);
9868 tw32(TG3_PCIE_TLDLPL_PORT + TG3_PCIE_PL_LO_PHYCTL5,
9869 val | TG3_PCIE_PL_LO_PHYCTL5_DIS_L2CLKREQ);
9871 tw32(GRC_MODE, grc_mode);
9874 if (tg3_chip_rev(tp) != CHIPREV_57765_AX) {
9877 /* Fix transmit hangs */
9878 val = tr32(TG3_CPMU_PADRNG_CTL);
9879 val |= TG3_CPMU_PADRNG_CTL_RDIV2;
9880 tw32(TG3_CPMU_PADRNG_CTL, val);
9882 grc_mode = tr32(GRC_MODE);
9884 /* Access the lower 1K of DL PCIE block registers. */
9885 val = grc_mode & ~GRC_MODE_PCIE_PORT_MASK;
9886 tw32(GRC_MODE, val | GRC_MODE_PCIE_DL_SEL);
9888 val = tr32(TG3_PCIE_TLDLPL_PORT +
9889 TG3_PCIE_DL_LO_FTSMAX);
9890 val &= ~TG3_PCIE_DL_LO_FTSMAX_MSK;
9891 tw32(TG3_PCIE_TLDLPL_PORT + TG3_PCIE_DL_LO_FTSMAX,
9892 val | TG3_PCIE_DL_LO_FTSMAX_VAL);
9894 tw32(GRC_MODE, grc_mode);
9897 val = tr32(TG3_CPMU_LSPD_10MB_CLK);
9898 val &= ~CPMU_LSPD_10MB_MACCLK_MASK;
9899 val |= CPMU_LSPD_10MB_MACCLK_6_25;
9900 tw32(TG3_CPMU_LSPD_10MB_CLK, val);
9903 /* This works around an issue with Athlon chipsets on
9904 * B3 tigon3 silicon. This bit has no effect on any
9905 * other revision. But do not set this on PCI Express
9906 * chips and don't even touch the clocks if the CPMU is present.
9908 if (!tg3_flag(tp, CPMU_PRESENT)) {
9909 if (!tg3_flag(tp, PCI_EXPRESS))
9910 tp->pci_clock_ctrl |= CLOCK_CTRL_DELAY_PCI_GRANT;
9911 tw32_f(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl);
9914 if (tg3_chip_rev_id(tp) == CHIPREV_ID_5704_A0 &&
9915 tg3_flag(tp, PCIX_MODE)) {
9916 val = tr32(TG3PCI_PCISTATE);
9917 val |= PCISTATE_RETRY_SAME_DMA;
9918 tw32(TG3PCI_PCISTATE, val);
9921 if (tg3_flag(tp, ENABLE_APE)) {
9922 /* Allow reads and writes to the
9923 * APE register and memory space.
9925 val = tr32(TG3PCI_PCISTATE);
9926 val |= PCISTATE_ALLOW_APE_CTLSPC_WR |
9927 PCISTATE_ALLOW_APE_SHMEM_WR |
9928 PCISTATE_ALLOW_APE_PSPACE_WR;
9929 tw32(TG3PCI_PCISTATE, val);
9932 if (tg3_chip_rev(tp) == CHIPREV_5704_BX) {
9933 /* Enable some hw fixes. */
9934 val = tr32(TG3PCI_MSI_DATA);
9935 val |= (1 << 26) | (1 << 28) | (1 << 29);
9936 tw32(TG3PCI_MSI_DATA, val);
9939 /* Descriptor ring init may make accesses to the
9940 * NIC SRAM area to setup the TX descriptors, so we
9941 * can only do this after the hardware has been
9942 * successfully reset.
9944 err = tg3_init_rings(tp);
9948 if (tg3_flag(tp, 57765_PLUS)) {
9949 val = tr32(TG3PCI_DMA_RW_CTRL) &
9950 ~DMA_RWCTRL_DIS_CACHE_ALIGNMENT;
9951 if (tg3_chip_rev_id(tp) == CHIPREV_ID_57765_A0)
9952 val &= ~DMA_RWCTRL_CRDRDR_RDMA_MRRS_MSK;
9953 if (!tg3_flag(tp, 57765_CLASS) &&
9954 tg3_asic_rev(tp) != ASIC_REV_5717 &&
9955 tg3_asic_rev(tp) != ASIC_REV_5762)
9956 val |= DMA_RWCTRL_TAGGED_STAT_WA;
9957 tw32(TG3PCI_DMA_RW_CTRL, val | tp->dma_rwctrl);
9958 } else if (tg3_asic_rev(tp) != ASIC_REV_5784 &&
9959 tg3_asic_rev(tp) != ASIC_REV_5761) {
9960 /* This value is determined during the probe time DMA
9961 * engine test, tg3_test_dma.
9963 tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
9966 tp->grc_mode &= ~(GRC_MODE_HOST_SENDBDS |
9967 GRC_MODE_4X_NIC_SEND_RINGS |
9968 GRC_MODE_NO_TX_PHDR_CSUM |
9969 GRC_MODE_NO_RX_PHDR_CSUM);
9970 tp->grc_mode |= GRC_MODE_HOST_SENDBDS;
9972 /* Pseudo-header checksum is done by hardware logic and not
9973 * the offload processers, so make the chip do the pseudo-
9974 * header checksums on receive. For transmit it is more
9975 * convenient to do the pseudo-header checksum in software
9976 * as Linux does that on transmit for us in all cases.
9978 tp->grc_mode |= GRC_MODE_NO_TX_PHDR_CSUM;
9980 val = GRC_MODE_IRQ_ON_MAC_ATTN | GRC_MODE_HOST_STACKUP;
9982 tw32(TG3_RX_PTP_CTL,
9983 tp->rxptpctl | TG3_RX_PTP_CTL_HWTS_INTERLOCK);
9985 if (tg3_flag(tp, PTP_CAPABLE))
9986 val |= GRC_MODE_TIME_SYNC_ENABLE;
9988 tw32(GRC_MODE, tp->grc_mode | val);
9990 /* Setup the timer prescalar register. Clock is always 66Mhz. */
9991 val = tr32(GRC_MISC_CFG);
9993 val |= (65 << GRC_MISC_CFG_PRESCALAR_SHIFT);
9994 tw32(GRC_MISC_CFG, val);
9996 /* Initialize MBUF/DESC pool. */
9997 if (tg3_flag(tp, 5750_PLUS)) {
9999 } else if (tg3_asic_rev(tp) != ASIC_REV_5705) {
10000 tw32(BUFMGR_MB_POOL_ADDR, NIC_SRAM_MBUF_POOL_BASE);
10001 if (tg3_asic_rev(tp) == ASIC_REV_5704)
10002 tw32(BUFMGR_MB_POOL_SIZE, NIC_SRAM_MBUF_POOL_SIZE64);
10004 tw32(BUFMGR_MB_POOL_SIZE, NIC_SRAM_MBUF_POOL_SIZE96);
10005 tw32(BUFMGR_DMA_DESC_POOL_ADDR, NIC_SRAM_DMA_DESC_POOL_BASE);
10006 tw32(BUFMGR_DMA_DESC_POOL_SIZE, NIC_SRAM_DMA_DESC_POOL_SIZE);
10007 } else if (tg3_flag(tp, TSO_CAPABLE)) {
10010 fw_len = tp->fw_len;
10011 fw_len = (fw_len + (0x80 - 1)) & ~(0x80 - 1);
10012 tw32(BUFMGR_MB_POOL_ADDR,
10013 NIC_SRAM_MBUF_POOL_BASE5705 + fw_len);
10014 tw32(BUFMGR_MB_POOL_SIZE,
10015 NIC_SRAM_MBUF_POOL_SIZE5705 - fw_len - 0xa00);
10018 if (tp->dev->mtu <= ETH_DATA_LEN) {
10019 tw32(BUFMGR_MB_RDMA_LOW_WATER,
10020 tp->bufmgr_config.mbuf_read_dma_low_water);
10021 tw32(BUFMGR_MB_MACRX_LOW_WATER,
10022 tp->bufmgr_config.mbuf_mac_rx_low_water);
10023 tw32(BUFMGR_MB_HIGH_WATER,
10024 tp->bufmgr_config.mbuf_high_water);
10026 tw32(BUFMGR_MB_RDMA_LOW_WATER,
10027 tp->bufmgr_config.mbuf_read_dma_low_water_jumbo);
10028 tw32(BUFMGR_MB_MACRX_LOW_WATER,
10029 tp->bufmgr_config.mbuf_mac_rx_low_water_jumbo);
10030 tw32(BUFMGR_MB_HIGH_WATER,
10031 tp->bufmgr_config.mbuf_high_water_jumbo);
10033 tw32(BUFMGR_DMA_LOW_WATER,
10034 tp->bufmgr_config.dma_low_water);
10035 tw32(BUFMGR_DMA_HIGH_WATER,
10036 tp->bufmgr_config.dma_high_water);
10038 val = BUFMGR_MODE_ENABLE | BUFMGR_MODE_ATTN_ENABLE;
10039 if (tg3_asic_rev(tp) == ASIC_REV_5719)
10040 val |= BUFMGR_MODE_NO_TX_UNDERRUN;
10041 if (tg3_asic_rev(tp) == ASIC_REV_5717 ||
10042 tg3_asic_rev(tp) == ASIC_REV_5762 ||
10043 tg3_chip_rev_id(tp) == CHIPREV_ID_5719_A0 ||
10044 tg3_chip_rev_id(tp) == CHIPREV_ID_5720_A0)
10045 val |= BUFMGR_MODE_MBLOW_ATTN_ENAB;
10046 tw32(BUFMGR_MODE, val);
10047 for (i = 0; i < 2000; i++) {
10048 if (tr32(BUFMGR_MODE) & BUFMGR_MODE_ENABLE)
10053 netdev_err(tp->dev, "%s cannot enable BUFMGR\n", __func__);
10057 if (tg3_chip_rev_id(tp) == CHIPREV_ID_5906_A1)
10058 tw32(ISO_PKT_TX, (tr32(ISO_PKT_TX) & ~0x3) | 0x2);
10060 tg3_setup_rxbd_thresholds(tp);
10062 /* Initialize TG3_BDINFO's at:
10063 * RCVDBDI_STD_BD: standard eth size rx ring
10064 * RCVDBDI_JUMBO_BD: jumbo frame rx ring
10065 * RCVDBDI_MINI_BD: small frame rx ring (??? does not work)
10068 * TG3_BDINFO_HOST_ADDR: high/low parts of DMA address of ring
10069 * TG3_BDINFO_MAXLEN_FLAGS: (rx max buffer size << 16) |
10070 * ring attribute flags
10071 * TG3_BDINFO_NIC_ADDR: location of descriptors in nic SRAM
10073 * Standard receive ring @ NIC_SRAM_RX_BUFFER_DESC, 512 entries.
10074 * Jumbo receive ring @ NIC_SRAM_RX_JUMBO_BUFFER_DESC, 256 entries.
10076 * The size of each ring is fixed in the firmware, but the location is
10079 tw32(RCVDBDI_STD_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_HIGH,
10080 ((u64) tpr->rx_std_mapping >> 32));
10081 tw32(RCVDBDI_STD_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_LOW,
10082 ((u64) tpr->rx_std_mapping & 0xffffffff));
10083 if (!tg3_flag(tp, 5717_PLUS))
10084 tw32(RCVDBDI_STD_BD + TG3_BDINFO_NIC_ADDR,
10085 NIC_SRAM_RX_BUFFER_DESC);
10087 /* Disable the mini ring */
10088 if (!tg3_flag(tp, 5705_PLUS))
10089 tw32(RCVDBDI_MINI_BD + TG3_BDINFO_MAXLEN_FLAGS,
10090 BDINFO_FLAGS_DISABLED);
10092 /* Program the jumbo buffer descriptor ring control
10093 * blocks on those devices that have them.
10095 if (tg3_chip_rev_id(tp) == CHIPREV_ID_5719_A0 ||
10096 (tg3_flag(tp, JUMBO_CAPABLE) && !tg3_flag(tp, 5780_CLASS))) {
10098 if (tg3_flag(tp, JUMBO_RING_ENABLE)) {
10099 tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_HIGH,
10100 ((u64) tpr->rx_jmb_mapping >> 32));
10101 tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_LOW,
10102 ((u64) tpr->rx_jmb_mapping & 0xffffffff));
10103 val = TG3_RX_JMB_RING_SIZE(tp) <<
10104 BDINFO_FLAGS_MAXLEN_SHIFT;
10105 tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_MAXLEN_FLAGS,
10106 val | BDINFO_FLAGS_USE_EXT_RECV);
10107 if (!tg3_flag(tp, USE_JUMBO_BDFLAG) ||
10108 tg3_flag(tp, 57765_CLASS) ||
10109 tg3_asic_rev(tp) == ASIC_REV_5762)
10110 tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_NIC_ADDR,
10111 NIC_SRAM_RX_JUMBO_BUFFER_DESC);
10113 tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_MAXLEN_FLAGS,
10114 BDINFO_FLAGS_DISABLED);
10117 if (tg3_flag(tp, 57765_PLUS)) {
10118 val = TG3_RX_STD_RING_SIZE(tp);
10119 val <<= BDINFO_FLAGS_MAXLEN_SHIFT;
10120 val |= (TG3_RX_STD_DMA_SZ << 2);
10122 val = TG3_RX_STD_DMA_SZ << BDINFO_FLAGS_MAXLEN_SHIFT;
10124 val = TG3_RX_STD_MAX_SIZE_5700 << BDINFO_FLAGS_MAXLEN_SHIFT;
10126 tw32(RCVDBDI_STD_BD + TG3_BDINFO_MAXLEN_FLAGS, val);
10128 tpr->rx_std_prod_idx = tp->rx_pending;
10129 tw32_rx_mbox(TG3_RX_STD_PROD_IDX_REG, tpr->rx_std_prod_idx);
10131 tpr->rx_jmb_prod_idx =
10132 tg3_flag(tp, JUMBO_RING_ENABLE) ? tp->rx_jumbo_pending : 0;
10133 tw32_rx_mbox(TG3_RX_JMB_PROD_IDX_REG, tpr->rx_jmb_prod_idx);
10135 tg3_rings_reset(tp);
10137 /* Initialize MAC address and backoff seed. */
10138 __tg3_set_mac_addr(tp, false);
10140 /* MTU + ethernet header + FCS + optional VLAN tag */
10141 tw32(MAC_RX_MTU_SIZE,
10142 tp->dev->mtu + ETH_HLEN + ETH_FCS_LEN + VLAN_HLEN);
10144 /* The slot time is changed by tg3_setup_phy if we
10145 * run at gigabit with half duplex.
10147 val = (2 << TX_LENGTHS_IPG_CRS_SHIFT) |
10148 (6 << TX_LENGTHS_IPG_SHIFT) |
10149 (32 << TX_LENGTHS_SLOT_TIME_SHIFT);
10151 if (tg3_asic_rev(tp) == ASIC_REV_5720 ||
10152 tg3_asic_rev(tp) == ASIC_REV_5762)
10153 val |= tr32(MAC_TX_LENGTHS) &
10154 (TX_LENGTHS_JMB_FRM_LEN_MSK |
10155 TX_LENGTHS_CNT_DWN_VAL_MSK);
10157 tw32(MAC_TX_LENGTHS, val);
10159 /* Receive rules. */
10160 tw32(MAC_RCV_RULE_CFG, RCV_RULE_CFG_DEFAULT_CLASS);
10161 tw32(RCVLPC_CONFIG, 0x0181);
10163 /* Calculate RDMAC_MODE setting early, we need it to determine
10164 * the RCVLPC_STATE_ENABLE mask.
10166 rdmac_mode = (RDMAC_MODE_ENABLE | RDMAC_MODE_TGTABORT_ENAB |
10167 RDMAC_MODE_MSTABORT_ENAB | RDMAC_MODE_PARITYERR_ENAB |
10168 RDMAC_MODE_ADDROFLOW_ENAB | RDMAC_MODE_FIFOOFLOW_ENAB |
10169 RDMAC_MODE_FIFOURUN_ENAB | RDMAC_MODE_FIFOOREAD_ENAB |
10170 RDMAC_MODE_LNGREAD_ENAB);
10172 if (tg3_asic_rev(tp) == ASIC_REV_5717)
10173 rdmac_mode |= RDMAC_MODE_MULT_DMA_RD_DIS;
10175 if (tg3_asic_rev(tp) == ASIC_REV_5784 ||
10176 tg3_asic_rev(tp) == ASIC_REV_5785 ||
10177 tg3_asic_rev(tp) == ASIC_REV_57780)
10178 rdmac_mode |= RDMAC_MODE_BD_SBD_CRPT_ENAB |
10179 RDMAC_MODE_MBUF_RBD_CRPT_ENAB |
10180 RDMAC_MODE_MBUF_SBD_CRPT_ENAB;
10182 if (tg3_asic_rev(tp) == ASIC_REV_5705 &&
10183 tg3_chip_rev_id(tp) != CHIPREV_ID_5705_A0) {
10184 if (tg3_flag(tp, TSO_CAPABLE) &&
10185 tg3_asic_rev(tp) == ASIC_REV_5705) {
10186 rdmac_mode |= RDMAC_MODE_FIFO_SIZE_128;
10187 } else if (!(tr32(TG3PCI_PCISTATE) & PCISTATE_BUS_SPEED_HIGH) &&
10188 !tg3_flag(tp, IS_5788)) {
10189 rdmac_mode |= RDMAC_MODE_FIFO_LONG_BURST;
10193 if (tg3_flag(tp, PCI_EXPRESS))
10194 rdmac_mode |= RDMAC_MODE_FIFO_LONG_BURST;
10196 if (tg3_asic_rev(tp) == ASIC_REV_57766) {
10198 if (tp->dev->mtu <= ETH_DATA_LEN) {
10199 rdmac_mode |= RDMAC_MODE_JMB_2K_MMRR;
10200 tp->dma_limit = TG3_TX_BD_DMA_MAX_2K;
10204 if (tg3_flag(tp, HW_TSO_1) ||
10205 tg3_flag(tp, HW_TSO_2) ||
10206 tg3_flag(tp, HW_TSO_3))
10207 rdmac_mode |= RDMAC_MODE_IPV4_LSO_EN;
10209 if (tg3_flag(tp, 57765_PLUS) ||
10210 tg3_asic_rev(tp) == ASIC_REV_5785 ||
10211 tg3_asic_rev(tp) == ASIC_REV_57780)
10212 rdmac_mode |= RDMAC_MODE_IPV6_LSO_EN;
10214 if (tg3_asic_rev(tp) == ASIC_REV_5720 ||
10215 tg3_asic_rev(tp) == ASIC_REV_5762)
10216 rdmac_mode |= tr32(RDMAC_MODE) & RDMAC_MODE_H2BNC_VLAN_DET;
10218 if (tg3_asic_rev(tp) == ASIC_REV_5761 ||
10219 tg3_asic_rev(tp) == ASIC_REV_5784 ||
10220 tg3_asic_rev(tp) == ASIC_REV_5785 ||
10221 tg3_asic_rev(tp) == ASIC_REV_57780 ||
10222 tg3_flag(tp, 57765_PLUS)) {
10225 if (tg3_asic_rev(tp) == ASIC_REV_5762)
10226 tgtreg = TG3_RDMA_RSRVCTRL_REG2;
10228 tgtreg = TG3_RDMA_RSRVCTRL_REG;
10230 val = tr32(tgtreg);
10231 if (tg3_chip_rev_id(tp) == CHIPREV_ID_5719_A0 ||
10232 tg3_asic_rev(tp) == ASIC_REV_5762) {
10233 val &= ~(TG3_RDMA_RSRVCTRL_TXMRGN_MASK |
10234 TG3_RDMA_RSRVCTRL_FIFO_LWM_MASK |
10235 TG3_RDMA_RSRVCTRL_FIFO_HWM_MASK);
10236 val |= TG3_RDMA_RSRVCTRL_TXMRGN_320B |
10237 TG3_RDMA_RSRVCTRL_FIFO_LWM_1_5K |
10238 TG3_RDMA_RSRVCTRL_FIFO_HWM_1_5K;
10240 tw32(tgtreg, val | TG3_RDMA_RSRVCTRL_FIFO_OFLW_FIX);
10243 if (tg3_asic_rev(tp) == ASIC_REV_5719 ||
10244 tg3_asic_rev(tp) == ASIC_REV_5720 ||
10245 tg3_asic_rev(tp) == ASIC_REV_5762) {
10248 if (tg3_asic_rev(tp) == ASIC_REV_5762)
10249 tgtreg = TG3_LSO_RD_DMA_CRPTEN_CTRL2;
10251 tgtreg = TG3_LSO_RD_DMA_CRPTEN_CTRL;
10253 val = tr32(tgtreg);
10255 TG3_LSO_RD_DMA_CRPTEN_CTRL_BLEN_BD_4K |
10256 TG3_LSO_RD_DMA_CRPTEN_CTRL_BLEN_LSO_4K);
10259 /* Receive/send statistics. */
10260 if (tg3_flag(tp, 5750_PLUS)) {
10261 val = tr32(RCVLPC_STATS_ENABLE);
10262 val &= ~RCVLPC_STATSENAB_DACK_FIX;
10263 tw32(RCVLPC_STATS_ENABLE, val);
10264 } else if ((rdmac_mode & RDMAC_MODE_FIFO_SIZE_128) &&
10265 tg3_flag(tp, TSO_CAPABLE)) {
10266 val = tr32(RCVLPC_STATS_ENABLE);
10267 val &= ~RCVLPC_STATSENAB_LNGBRST_RFIX;
10268 tw32(RCVLPC_STATS_ENABLE, val);
10270 tw32(RCVLPC_STATS_ENABLE, 0xffffff);
10272 tw32(RCVLPC_STATSCTRL, RCVLPC_STATSCTRL_ENABLE);
10273 tw32(SNDDATAI_STATSENAB, 0xffffff);
10274 tw32(SNDDATAI_STATSCTRL,
10275 (SNDDATAI_SCTRL_ENABLE |
10276 SNDDATAI_SCTRL_FASTUPD));
10278 /* Setup host coalescing engine. */
10279 tw32(HOSTCC_MODE, 0);
10280 for (i = 0; i < 2000; i++) {
10281 if (!(tr32(HOSTCC_MODE) & HOSTCC_MODE_ENABLE))
10286 __tg3_set_coalesce(tp, &tp->coal);
10288 if (!tg3_flag(tp, 5705_PLUS)) {
10289 /* Status/statistics block address. See tg3_timer,
10290 * the tg3_periodic_fetch_stats call there, and
10291 * tg3_get_stats to see how this works for 5705/5750 chips.
10293 tw32(HOSTCC_STATS_BLK_HOST_ADDR + TG3_64BIT_REG_HIGH,
10294 ((u64) tp->stats_mapping >> 32));
10295 tw32(HOSTCC_STATS_BLK_HOST_ADDR + TG3_64BIT_REG_LOW,
10296 ((u64) tp->stats_mapping & 0xffffffff));
10297 tw32(HOSTCC_STATS_BLK_NIC_ADDR, NIC_SRAM_STATS_BLK);
10299 tw32(HOSTCC_STATUS_BLK_NIC_ADDR, NIC_SRAM_STATUS_BLK);
10301 /* Clear statistics and status block memory areas */
10302 for (i = NIC_SRAM_STATS_BLK;
10303 i < NIC_SRAM_STATUS_BLK + TG3_HW_STATUS_SIZE;
10304 i += sizeof(u32)) {
10305 tg3_write_mem(tp, i, 0);
10310 tw32(HOSTCC_MODE, HOSTCC_MODE_ENABLE | tp->coalesce_mode);
10312 tw32(RCVCC_MODE, RCVCC_MODE_ENABLE | RCVCC_MODE_ATTN_ENABLE);
10313 tw32(RCVLPC_MODE, RCVLPC_MODE_ENABLE);
10314 if (!tg3_flag(tp, 5705_PLUS))
10315 tw32(RCVLSC_MODE, RCVLSC_MODE_ENABLE | RCVLSC_MODE_ATTN_ENABLE);
10317 if (tp->phy_flags & TG3_PHYFLG_MII_SERDES) {
10318 tp->phy_flags &= ~TG3_PHYFLG_PARALLEL_DETECT;
10319 /* reset to prevent losing 1st rx packet intermittently */
10320 tw32_f(MAC_RX_MODE, RX_MODE_RESET);
10324 tp->mac_mode |= MAC_MODE_TXSTAT_ENABLE | MAC_MODE_RXSTAT_ENABLE |
10325 MAC_MODE_TDE_ENABLE | MAC_MODE_RDE_ENABLE |
10326 MAC_MODE_FHDE_ENABLE;
10327 if (tg3_flag(tp, ENABLE_APE))
10328 tp->mac_mode |= MAC_MODE_APE_TX_EN | MAC_MODE_APE_RX_EN;
10329 if (!tg3_flag(tp, 5705_PLUS) &&
10330 !(tp->phy_flags & TG3_PHYFLG_PHY_SERDES) &&
10331 tg3_asic_rev(tp) != ASIC_REV_5700)
10332 tp->mac_mode |= MAC_MODE_LINK_POLARITY;
10333 tw32_f(MAC_MODE, tp->mac_mode | MAC_MODE_RXSTAT_CLEAR | MAC_MODE_TXSTAT_CLEAR);
10336 /* tp->grc_local_ctrl is partially set up during tg3_get_invariants().
10337 * If TG3_FLAG_IS_NIC is zero, we should read the
10338 * register to preserve the GPIO settings for LOMs. The GPIOs,
10339 * whether used as inputs or outputs, are set by boot code after
10342 if (!tg3_flag(tp, IS_NIC)) {
10345 gpio_mask = GRC_LCLCTRL_GPIO_OE0 | GRC_LCLCTRL_GPIO_OE1 |
10346 GRC_LCLCTRL_GPIO_OE2 | GRC_LCLCTRL_GPIO_OUTPUT0 |
10347 GRC_LCLCTRL_GPIO_OUTPUT1 | GRC_LCLCTRL_GPIO_OUTPUT2;
10349 if (tg3_asic_rev(tp) == ASIC_REV_5752)
10350 gpio_mask |= GRC_LCLCTRL_GPIO_OE3 |
10351 GRC_LCLCTRL_GPIO_OUTPUT3;
10353 if (tg3_asic_rev(tp) == ASIC_REV_5755)
10354 gpio_mask |= GRC_LCLCTRL_GPIO_UART_SEL;
10356 tp->grc_local_ctrl &= ~gpio_mask;
10357 tp->grc_local_ctrl |= tr32(GRC_LOCAL_CTRL) & gpio_mask;
10359 /* GPIO1 must be driven high for eeprom write protect */
10360 if (tg3_flag(tp, EEPROM_WRITE_PROT))
10361 tp->grc_local_ctrl |= (GRC_LCLCTRL_GPIO_OE1 |
10362 GRC_LCLCTRL_GPIO_OUTPUT1);
10364 tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl);
10367 if (tg3_flag(tp, USING_MSIX)) {
10368 val = tr32(MSGINT_MODE);
10369 val |= MSGINT_MODE_ENABLE;
10370 if (tp->irq_cnt > 1)
10371 val |= MSGINT_MODE_MULTIVEC_EN;
10372 if (!tg3_flag(tp, 1SHOT_MSI))
10373 val |= MSGINT_MODE_ONE_SHOT_DISABLE;
10374 tw32(MSGINT_MODE, val);
10377 if (!tg3_flag(tp, 5705_PLUS)) {
10378 tw32_f(DMAC_MODE, DMAC_MODE_ENABLE);
10382 val = (WDMAC_MODE_ENABLE | WDMAC_MODE_TGTABORT_ENAB |
10383 WDMAC_MODE_MSTABORT_ENAB | WDMAC_MODE_PARITYERR_ENAB |
10384 WDMAC_MODE_ADDROFLOW_ENAB | WDMAC_MODE_FIFOOFLOW_ENAB |
10385 WDMAC_MODE_FIFOURUN_ENAB | WDMAC_MODE_FIFOOREAD_ENAB |
10386 WDMAC_MODE_LNGREAD_ENAB);
10388 if (tg3_asic_rev(tp) == ASIC_REV_5705 &&
10389 tg3_chip_rev_id(tp) != CHIPREV_ID_5705_A0) {
10390 if (tg3_flag(tp, TSO_CAPABLE) &&
10391 (tg3_chip_rev_id(tp) == CHIPREV_ID_5705_A1 ||
10392 tg3_chip_rev_id(tp) == CHIPREV_ID_5705_A2)) {
10394 } else if (!(tr32(TG3PCI_PCISTATE) & PCISTATE_BUS_SPEED_HIGH) &&
10395 !tg3_flag(tp, IS_5788)) {
10396 val |= WDMAC_MODE_RX_ACCEL;
10400 /* Enable host coalescing bug fix */
10401 if (tg3_flag(tp, 5755_PLUS))
10402 val |= WDMAC_MODE_STATUS_TAG_FIX;
10404 if (tg3_asic_rev(tp) == ASIC_REV_5785)
10405 val |= WDMAC_MODE_BURST_ALL_DATA;
10407 tw32_f(WDMAC_MODE, val);
10410 if (tg3_flag(tp, PCIX_MODE)) {
10413 pci_read_config_word(tp->pdev, tp->pcix_cap + PCI_X_CMD,
10415 if (tg3_asic_rev(tp) == ASIC_REV_5703) {
10416 pcix_cmd &= ~PCI_X_CMD_MAX_READ;
10417 pcix_cmd |= PCI_X_CMD_READ_2K;
10418 } else if (tg3_asic_rev(tp) == ASIC_REV_5704) {
10419 pcix_cmd &= ~(PCI_X_CMD_MAX_SPLIT | PCI_X_CMD_MAX_READ);
10420 pcix_cmd |= PCI_X_CMD_READ_2K;
10422 pci_write_config_word(tp->pdev, tp->pcix_cap + PCI_X_CMD,
10426 tw32_f(RDMAC_MODE, rdmac_mode);
10429 if (tg3_asic_rev(tp) == ASIC_REV_5719 ||
10430 tg3_asic_rev(tp) == ASIC_REV_5720) {
10431 for (i = 0; i < TG3_NUM_RDMA_CHANNELS; i++) {
10432 if (tr32(TG3_RDMA_LENGTH + (i << 2)) > TG3_MAX_MTU(tp))
10435 if (i < TG3_NUM_RDMA_CHANNELS) {
10436 val = tr32(TG3_LSO_RD_DMA_CRPTEN_CTRL);
10437 val |= tg3_lso_rd_dma_workaround_bit(tp);
10438 tw32(TG3_LSO_RD_DMA_CRPTEN_CTRL, val);
10439 tg3_flag_set(tp, 5719_5720_RDMA_BUG);
10443 tw32(RCVDCC_MODE, RCVDCC_MODE_ENABLE | RCVDCC_MODE_ATTN_ENABLE);
10444 if (!tg3_flag(tp, 5705_PLUS))
10445 tw32(MBFREE_MODE, MBFREE_MODE_ENABLE);
10447 if (tg3_asic_rev(tp) == ASIC_REV_5761)
10448 tw32(SNDDATAC_MODE,
10449 SNDDATAC_MODE_ENABLE | SNDDATAC_MODE_CDELAY);
10451 tw32(SNDDATAC_MODE, SNDDATAC_MODE_ENABLE);
10453 tw32(SNDBDC_MODE, SNDBDC_MODE_ENABLE | SNDBDC_MODE_ATTN_ENABLE);
10454 tw32(RCVBDI_MODE, RCVBDI_MODE_ENABLE | RCVBDI_MODE_RCB_ATTN_ENAB);
10455 val = RCVDBDI_MODE_ENABLE | RCVDBDI_MODE_INV_RING_SZ;
10456 if (tg3_flag(tp, LRG_PROD_RING_CAP))
10457 val |= RCVDBDI_MODE_LRG_RING_SZ;
10458 tw32(RCVDBDI_MODE, val);
10459 tw32(SNDDATAI_MODE, SNDDATAI_MODE_ENABLE);
10460 if (tg3_flag(tp, HW_TSO_1) ||
10461 tg3_flag(tp, HW_TSO_2) ||
10462 tg3_flag(tp, HW_TSO_3))
10463 tw32(SNDDATAI_MODE, SNDDATAI_MODE_ENABLE | 0x8);
10464 val = SNDBDI_MODE_ENABLE | SNDBDI_MODE_ATTN_ENABLE;
10465 if (tg3_flag(tp, ENABLE_TSS))
10466 val |= SNDBDI_MODE_MULTI_TXQ_EN;
10467 tw32(SNDBDI_MODE, val);
10468 tw32(SNDBDS_MODE, SNDBDS_MODE_ENABLE | SNDBDS_MODE_ATTN_ENABLE);
10470 if (tg3_chip_rev_id(tp) == CHIPREV_ID_5701_A0) {
10471 err = tg3_load_5701_a0_firmware_fix(tp);
10476 if (tg3_asic_rev(tp) == ASIC_REV_57766) {
10477 /* Ignore any errors for the firmware download. If download
10478 * fails, the device will operate with EEE disabled
10480 tg3_load_57766_firmware(tp);
10483 if (tg3_flag(tp, TSO_CAPABLE)) {
10484 err = tg3_load_tso_firmware(tp);
10489 tp->tx_mode = TX_MODE_ENABLE;
10491 if (tg3_flag(tp, 5755_PLUS) ||
10492 tg3_asic_rev(tp) == ASIC_REV_5906)
10493 tp->tx_mode |= TX_MODE_MBUF_LOCKUP_FIX;
10495 if (tg3_asic_rev(tp) == ASIC_REV_5720 ||
10496 tg3_asic_rev(tp) == ASIC_REV_5762) {
10497 val = TX_MODE_JMB_FRM_LEN | TX_MODE_CNT_DN_MODE;
10498 tp->tx_mode &= ~val;
10499 tp->tx_mode |= tr32(MAC_TX_MODE) & val;
10502 tw32_f(MAC_TX_MODE, tp->tx_mode);
10505 if (tg3_flag(tp, ENABLE_RSS)) {
10506 tg3_rss_write_indir_tbl(tp);
10508 /* Setup the "secret" hash key. */
10509 tw32(MAC_RSS_HASH_KEY_0, 0x5f865437);
10510 tw32(MAC_RSS_HASH_KEY_1, 0xe4ac62cc);
10511 tw32(MAC_RSS_HASH_KEY_2, 0x50103a45);
10512 tw32(MAC_RSS_HASH_KEY_3, 0x36621985);
10513 tw32(MAC_RSS_HASH_KEY_4, 0xbf14c0e8);
10514 tw32(MAC_RSS_HASH_KEY_5, 0x1bc27a1e);
10515 tw32(MAC_RSS_HASH_KEY_6, 0x84f4b556);
10516 tw32(MAC_RSS_HASH_KEY_7, 0x094ea6fe);
10517 tw32(MAC_RSS_HASH_KEY_8, 0x7dda01e7);
10518 tw32(MAC_RSS_HASH_KEY_9, 0xc04d7481);
10521 tp->rx_mode = RX_MODE_ENABLE;
10522 if (tg3_flag(tp, 5755_PLUS))
10523 tp->rx_mode |= RX_MODE_IPV6_CSUM_ENABLE;
10525 if (tg3_asic_rev(tp) == ASIC_REV_5762)
10526 tp->rx_mode |= RX_MODE_IPV4_FRAG_FIX;
10528 if (tg3_flag(tp, ENABLE_RSS))
10529 tp->rx_mode |= RX_MODE_RSS_ENABLE |
10530 RX_MODE_RSS_ITBL_HASH_BITS_7 |
10531 RX_MODE_RSS_IPV6_HASH_EN |
10532 RX_MODE_RSS_TCP_IPV6_HASH_EN |
10533 RX_MODE_RSS_IPV4_HASH_EN |
10534 RX_MODE_RSS_TCP_IPV4_HASH_EN;
10536 tw32_f(MAC_RX_MODE, tp->rx_mode);
10539 tw32(MAC_LED_CTRL, tp->led_ctrl);
10541 tw32(MAC_MI_STAT, MAC_MI_STAT_LNKSTAT_ATTN_ENAB);
10542 if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES) {
10543 tw32_f(MAC_RX_MODE, RX_MODE_RESET);
10546 tw32_f(MAC_RX_MODE, tp->rx_mode);
10549 if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES) {
10550 if ((tg3_asic_rev(tp) == ASIC_REV_5704) &&
10551 !(tp->phy_flags & TG3_PHYFLG_SERDES_PREEMPHASIS)) {
10552 /* Set drive transmission level to 1.2V */
10553 /* only if the signal pre-emphasis bit is not set */
10554 val = tr32(MAC_SERDES_CFG);
10557 tw32(MAC_SERDES_CFG, val);
10559 if (tg3_chip_rev_id(tp) == CHIPREV_ID_5703_A1)
10560 tw32(MAC_SERDES_CFG, 0x616000);
10563 /* Prevent chip from dropping frames when flow control
10566 if (tg3_flag(tp, 57765_CLASS))
10570 tw32_f(MAC_LOW_WMARK_MAX_RX_FRAME, val);
10572 if (tg3_asic_rev(tp) == ASIC_REV_5704 &&
10573 (tp->phy_flags & TG3_PHYFLG_PHY_SERDES)) {
10574 /* Use hardware link auto-negotiation */
10575 tg3_flag_set(tp, HW_AUTONEG);
10578 if ((tp->phy_flags & TG3_PHYFLG_MII_SERDES) &&
10579 tg3_asic_rev(tp) == ASIC_REV_5714) {
10582 tmp = tr32(SERDES_RX_CTRL);
10583 tw32(SERDES_RX_CTRL, tmp | SERDES_RX_SIG_DETECT);
10584 tp->grc_local_ctrl &= ~GRC_LCLCTRL_USE_EXT_SIG_DETECT;
10585 tp->grc_local_ctrl |= GRC_LCLCTRL_USE_SIG_DETECT;
10586 tw32(GRC_LOCAL_CTRL, tp->grc_local_ctrl);
10589 if (!tg3_flag(tp, USE_PHYLIB)) {
10590 if (tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER)
10591 tp->phy_flags &= ~TG3_PHYFLG_IS_LOW_POWER;
10593 err = tg3_setup_phy(tp, false);
10597 if (!(tp->phy_flags & TG3_PHYFLG_PHY_SERDES) &&
10598 !(tp->phy_flags & TG3_PHYFLG_IS_FET)) {
10601 /* Clear CRC stats. */
10602 if (!tg3_readphy(tp, MII_TG3_TEST1, &tmp)) {
10603 tg3_writephy(tp, MII_TG3_TEST1,
10604 tmp | MII_TG3_TEST1_CRC_EN);
10605 tg3_readphy(tp, MII_TG3_RXR_COUNTERS, &tmp);
10610 __tg3_set_rx_mode(tp->dev);
10612 /* Initialize receive rules. */
10613 tw32(MAC_RCV_RULE_0, 0xc2000000 & RCV_RULE_DISABLE_MASK);
10614 tw32(MAC_RCV_VALUE_0, 0xffffffff & RCV_RULE_DISABLE_MASK);
10615 tw32(MAC_RCV_RULE_1, 0x86000004 & RCV_RULE_DISABLE_MASK);
10616 tw32(MAC_RCV_VALUE_1, 0xffffffff & RCV_RULE_DISABLE_MASK);
10618 if (tg3_flag(tp, 5705_PLUS) && !tg3_flag(tp, 5780_CLASS))
10622 if (tg3_flag(tp, ENABLE_ASF))
10626 tw32(MAC_RCV_RULE_15, 0); tw32(MAC_RCV_VALUE_15, 0);
10628 tw32(MAC_RCV_RULE_14, 0); tw32(MAC_RCV_VALUE_14, 0);
10630 tw32(MAC_RCV_RULE_13, 0); tw32(MAC_RCV_VALUE_13, 0);
10632 tw32(MAC_RCV_RULE_12, 0); tw32(MAC_RCV_VALUE_12, 0);
10634 tw32(MAC_RCV_RULE_11, 0); tw32(MAC_RCV_VALUE_11, 0);
10636 tw32(MAC_RCV_RULE_10, 0); tw32(MAC_RCV_VALUE_10, 0);
10638 tw32(MAC_RCV_RULE_9, 0); tw32(MAC_RCV_VALUE_9, 0);
10640 tw32(MAC_RCV_RULE_8, 0); tw32(MAC_RCV_VALUE_8, 0);
10642 tw32(MAC_RCV_RULE_7, 0); tw32(MAC_RCV_VALUE_7, 0);
10644 tw32(MAC_RCV_RULE_6, 0); tw32(MAC_RCV_VALUE_6, 0);
10646 tw32(MAC_RCV_RULE_5, 0); tw32(MAC_RCV_VALUE_5, 0);
10648 tw32(MAC_RCV_RULE_4, 0); tw32(MAC_RCV_VALUE_4, 0);
10650 /* tw32(MAC_RCV_RULE_3, 0); tw32(MAC_RCV_VALUE_3, 0); */
10652 /* tw32(MAC_RCV_RULE_2, 0); tw32(MAC_RCV_VALUE_2, 0); */
10660 if (tg3_flag(tp, ENABLE_APE))
10661 /* Write our heartbeat update interval to APE. */
10662 tg3_ape_write32(tp, TG3_APE_HOST_HEARTBEAT_INT_MS,
10663 APE_HOST_HEARTBEAT_INT_DISABLE);
10665 tg3_write_sig_post_reset(tp, RESET_KIND_INIT);
10670 /* Called at device open time to get the chip ready for
10671 * packet processing. Invoked with tp->lock held.
10673 static int tg3_init_hw(struct tg3 *tp, bool reset_phy)
10675 /* Chip may have been just powered on. If so, the boot code may still
10676 * be running initialization. Wait for it to finish to avoid races in
10677 * accessing the hardware.
10679 tg3_enable_register_access(tp);
10682 tg3_switch_clocks(tp);
10684 tw32(TG3PCI_MEM_WIN_BASE_ADDR, 0);
10686 return tg3_reset_hw(tp, reset_phy);
10689 static void tg3_sd_scan_scratchpad(struct tg3 *tp, struct tg3_ocir *ocir)
10693 for (i = 0; i < TG3_SD_NUM_RECS; i++, ocir++) {
10694 u32 off = i * TG3_OCIR_LEN, len = TG3_OCIR_LEN;
10696 tg3_ape_scratchpad_read(tp, (u32 *) ocir, off, len);
10699 if (ocir->signature != TG3_OCIR_SIG_MAGIC ||
10700 !(ocir->version_flags & TG3_OCIR_FLAG_ACTIVE))
10701 memset(ocir, 0, TG3_OCIR_LEN);
10705 /* sysfs attributes for hwmon */
10706 static ssize_t tg3_show_temp(struct device *dev,
10707 struct device_attribute *devattr, char *buf)
10709 struct sensor_device_attribute *attr = to_sensor_dev_attr(devattr);
10710 struct tg3 *tp = dev_get_drvdata(dev);
10713 spin_lock_bh(&tp->lock);
10714 tg3_ape_scratchpad_read(tp, &temperature, attr->index,
10715 sizeof(temperature));
10716 spin_unlock_bh(&tp->lock);
10717 return sprintf(buf, "%u\n", temperature);
10721 static SENSOR_DEVICE_ATTR(temp1_input, S_IRUGO, tg3_show_temp, NULL,
10722 TG3_TEMP_SENSOR_OFFSET);
10723 static SENSOR_DEVICE_ATTR(temp1_crit, S_IRUGO, tg3_show_temp, NULL,
10724 TG3_TEMP_CAUTION_OFFSET);
10725 static SENSOR_DEVICE_ATTR(temp1_max, S_IRUGO, tg3_show_temp, NULL,
10726 TG3_TEMP_MAX_OFFSET);
10728 static struct attribute *tg3_attrs[] = {
10729 &sensor_dev_attr_temp1_input.dev_attr.attr,
10730 &sensor_dev_attr_temp1_crit.dev_attr.attr,
10731 &sensor_dev_attr_temp1_max.dev_attr.attr,
10734 ATTRIBUTE_GROUPS(tg3);
10736 static void tg3_hwmon_close(struct tg3 *tp)
10738 if (tp->hwmon_dev) {
10739 hwmon_device_unregister(tp->hwmon_dev);
10740 tp->hwmon_dev = NULL;
10744 static void tg3_hwmon_open(struct tg3 *tp)
10748 struct pci_dev *pdev = tp->pdev;
10749 struct tg3_ocir ocirs[TG3_SD_NUM_RECS];
10751 tg3_sd_scan_scratchpad(tp, ocirs);
10753 for (i = 0; i < TG3_SD_NUM_RECS; i++) {
10754 if (!ocirs[i].src_data_length)
10757 size += ocirs[i].src_hdr_length;
10758 size += ocirs[i].src_data_length;
10764 tp->hwmon_dev = hwmon_device_register_with_groups(&pdev->dev, "tg3",
10766 if (IS_ERR(tp->hwmon_dev)) {
10767 tp->hwmon_dev = NULL;
10768 dev_err(&pdev->dev, "Cannot register hwmon device, aborting\n");
10773 #define TG3_STAT_ADD32(PSTAT, REG) \
10774 do { u32 __val = tr32(REG); \
10775 (PSTAT)->low += __val; \
10776 if ((PSTAT)->low < __val) \
10777 (PSTAT)->high += 1; \
10780 static void tg3_periodic_fetch_stats(struct tg3 *tp)
10782 struct tg3_hw_stats *sp = tp->hw_stats;
10787 TG3_STAT_ADD32(&sp->tx_octets, MAC_TX_STATS_OCTETS);
10788 TG3_STAT_ADD32(&sp->tx_collisions, MAC_TX_STATS_COLLISIONS);
10789 TG3_STAT_ADD32(&sp->tx_xon_sent, MAC_TX_STATS_XON_SENT);
10790 TG3_STAT_ADD32(&sp->tx_xoff_sent, MAC_TX_STATS_XOFF_SENT);
10791 TG3_STAT_ADD32(&sp->tx_mac_errors, MAC_TX_STATS_MAC_ERRORS);
10792 TG3_STAT_ADD32(&sp->tx_single_collisions, MAC_TX_STATS_SINGLE_COLLISIONS);
10793 TG3_STAT_ADD32(&sp->tx_mult_collisions, MAC_TX_STATS_MULT_COLLISIONS);
10794 TG3_STAT_ADD32(&sp->tx_deferred, MAC_TX_STATS_DEFERRED);
10795 TG3_STAT_ADD32(&sp->tx_excessive_collisions, MAC_TX_STATS_EXCESSIVE_COL);
10796 TG3_STAT_ADD32(&sp->tx_late_collisions, MAC_TX_STATS_LATE_COL);
10797 TG3_STAT_ADD32(&sp->tx_ucast_packets, MAC_TX_STATS_UCAST);
10798 TG3_STAT_ADD32(&sp->tx_mcast_packets, MAC_TX_STATS_MCAST);
10799 TG3_STAT_ADD32(&sp->tx_bcast_packets, MAC_TX_STATS_BCAST);
10800 if (unlikely(tg3_flag(tp, 5719_5720_RDMA_BUG) &&
10801 (sp->tx_ucast_packets.low + sp->tx_mcast_packets.low +
10802 sp->tx_bcast_packets.low) > TG3_NUM_RDMA_CHANNELS)) {
10805 val = tr32(TG3_LSO_RD_DMA_CRPTEN_CTRL);
10806 val &= ~tg3_lso_rd_dma_workaround_bit(tp);
10807 tw32(TG3_LSO_RD_DMA_CRPTEN_CTRL, val);
10808 tg3_flag_clear(tp, 5719_5720_RDMA_BUG);
10811 TG3_STAT_ADD32(&sp->rx_octets, MAC_RX_STATS_OCTETS);
10812 TG3_STAT_ADD32(&sp->rx_fragments, MAC_RX_STATS_FRAGMENTS);
10813 TG3_STAT_ADD32(&sp->rx_ucast_packets, MAC_RX_STATS_UCAST);
10814 TG3_STAT_ADD32(&sp->rx_mcast_packets, MAC_RX_STATS_MCAST);
10815 TG3_STAT_ADD32(&sp->rx_bcast_packets, MAC_RX_STATS_BCAST);
10816 TG3_STAT_ADD32(&sp->rx_fcs_errors, MAC_RX_STATS_FCS_ERRORS);
10817 TG3_STAT_ADD32(&sp->rx_align_errors, MAC_RX_STATS_ALIGN_ERRORS);
10818 TG3_STAT_ADD32(&sp->rx_xon_pause_rcvd, MAC_RX_STATS_XON_PAUSE_RECVD);
10819 TG3_STAT_ADD32(&sp->rx_xoff_pause_rcvd, MAC_RX_STATS_XOFF_PAUSE_RECVD);
10820 TG3_STAT_ADD32(&sp->rx_mac_ctrl_rcvd, MAC_RX_STATS_MAC_CTRL_RECVD);
10821 TG3_STAT_ADD32(&sp->rx_xoff_entered, MAC_RX_STATS_XOFF_ENTERED);
10822 TG3_STAT_ADD32(&sp->rx_frame_too_long_errors, MAC_RX_STATS_FRAME_TOO_LONG);
10823 TG3_STAT_ADD32(&sp->rx_jabbers, MAC_RX_STATS_JABBERS);
10824 TG3_STAT_ADD32(&sp->rx_undersize_packets, MAC_RX_STATS_UNDERSIZE);
10826 TG3_STAT_ADD32(&sp->rxbds_empty, RCVLPC_NO_RCV_BD_CNT);
10827 if (tg3_asic_rev(tp) != ASIC_REV_5717 &&
10828 tg3_asic_rev(tp) != ASIC_REV_5762 &&
10829 tg3_chip_rev_id(tp) != CHIPREV_ID_5719_A0 &&
10830 tg3_chip_rev_id(tp) != CHIPREV_ID_5720_A0) {
10831 TG3_STAT_ADD32(&sp->rx_discards, RCVLPC_IN_DISCARDS_CNT);
10833 u32 val = tr32(HOSTCC_FLOW_ATTN);
10834 val = (val & HOSTCC_FLOW_ATTN_MBUF_LWM) ? 1 : 0;
10836 tw32(HOSTCC_FLOW_ATTN, HOSTCC_FLOW_ATTN_MBUF_LWM);
10837 sp->rx_discards.low += val;
10838 if (sp->rx_discards.low < val)
10839 sp->rx_discards.high += 1;
10841 sp->mbuf_lwm_thresh_hit = sp->rx_discards;
10843 TG3_STAT_ADD32(&sp->rx_errors, RCVLPC_IN_ERRORS_CNT);
10846 static void tg3_chk_missed_msi(struct tg3 *tp)
10850 for (i = 0; i < tp->irq_cnt; i++) {
10851 struct tg3_napi *tnapi = &tp->napi[i];
10853 if (tg3_has_work(tnapi)) {
10854 if (tnapi->last_rx_cons == tnapi->rx_rcb_ptr &&
10855 tnapi->last_tx_cons == tnapi->tx_cons) {
10856 if (tnapi->chk_msi_cnt < 1) {
10857 tnapi->chk_msi_cnt++;
10863 tnapi->chk_msi_cnt = 0;
10864 tnapi->last_rx_cons = tnapi->rx_rcb_ptr;
10865 tnapi->last_tx_cons = tnapi->tx_cons;
10869 static void tg3_timer(unsigned long __opaque)
10871 struct tg3 *tp = (struct tg3 *) __opaque;
10873 if (tp->irq_sync || tg3_flag(tp, RESET_TASK_PENDING))
10874 goto restart_timer;
10876 spin_lock(&tp->lock);
10878 if (tg3_asic_rev(tp) == ASIC_REV_5717 ||
10879 tg3_flag(tp, 57765_CLASS))
10880 tg3_chk_missed_msi(tp);
10882 if (tg3_flag(tp, FLUSH_POSTED_WRITES)) {
10883 /* BCM4785: Flush posted writes from GbE to host memory. */
10887 if (!tg3_flag(tp, TAGGED_STATUS)) {
10888 /* All of this garbage is because when using non-tagged
10889 * IRQ status the mailbox/status_block protocol the chip
10890 * uses with the cpu is race prone.
10892 if (tp->napi[0].hw_status->status & SD_STATUS_UPDATED) {
10893 tw32(GRC_LOCAL_CTRL,
10894 tp->grc_local_ctrl | GRC_LCLCTRL_SETINT);
10896 tw32(HOSTCC_MODE, tp->coalesce_mode |
10897 HOSTCC_MODE_ENABLE | HOSTCC_MODE_NOW);
10900 if (!(tr32(WDMAC_MODE) & WDMAC_MODE_ENABLE)) {
10901 spin_unlock(&tp->lock);
10902 tg3_reset_task_schedule(tp);
10903 goto restart_timer;
10907 /* This part only runs once per second. */
10908 if (!--tp->timer_counter) {
10909 if (tg3_flag(tp, 5705_PLUS))
10910 tg3_periodic_fetch_stats(tp);
10912 if (tp->setlpicnt && !--tp->setlpicnt)
10913 tg3_phy_eee_enable(tp);
10915 if (tg3_flag(tp, USE_LINKCHG_REG)) {
10919 mac_stat = tr32(MAC_STATUS);
10922 if (tp->phy_flags & TG3_PHYFLG_USE_MI_INTERRUPT) {
10923 if (mac_stat & MAC_STATUS_MI_INTERRUPT)
10925 } else if (mac_stat & MAC_STATUS_LNKSTATE_CHANGED)
10929 tg3_setup_phy(tp, false);
10930 } else if (tg3_flag(tp, POLL_SERDES)) {
10931 u32 mac_stat = tr32(MAC_STATUS);
10932 int need_setup = 0;
10935 (mac_stat & MAC_STATUS_LNKSTATE_CHANGED)) {
10938 if (!tp->link_up &&
10939 (mac_stat & (MAC_STATUS_PCS_SYNCED |
10940 MAC_STATUS_SIGNAL_DET))) {
10944 if (!tp->serdes_counter) {
10947 ~MAC_MODE_PORT_MODE_MASK));
10949 tw32_f(MAC_MODE, tp->mac_mode);
10952 tg3_setup_phy(tp, false);
10954 } else if ((tp->phy_flags & TG3_PHYFLG_MII_SERDES) &&
10955 tg3_flag(tp, 5780_CLASS)) {
10956 tg3_serdes_parallel_detect(tp);
10957 } else if (tg3_flag(tp, POLL_CPMU_LINK)) {
10958 u32 cpmu = tr32(TG3_CPMU_STATUS);
10959 bool link_up = !((cpmu & TG3_CPMU_STATUS_LINK_MASK) ==
10960 TG3_CPMU_STATUS_LINK_MASK);
10962 if (link_up != tp->link_up)
10963 tg3_setup_phy(tp, false);
10966 tp->timer_counter = tp->timer_multiplier;
10969 /* Heartbeat is only sent once every 2 seconds.
10971 * The heartbeat is to tell the ASF firmware that the host
10972 * driver is still alive. In the event that the OS crashes,
10973 * ASF needs to reset the hardware to free up the FIFO space
10974 * that may be filled with rx packets destined for the host.
10975 * If the FIFO is full, ASF will no longer function properly.
10977 * Unintended resets have been reported on real time kernels
10978 * where the timer doesn't run on time. Netpoll will also have
10981 * The new FWCMD_NICDRV_ALIVE3 command tells the ASF firmware
10982 * to check the ring condition when the heartbeat is expiring
10983 * before doing the reset. This will prevent most unintended
10986 if (!--tp->asf_counter) {
10987 if (tg3_flag(tp, ENABLE_ASF) && !tg3_flag(tp, ENABLE_APE)) {
10988 tg3_wait_for_event_ack(tp);
10990 tg3_write_mem(tp, NIC_SRAM_FW_CMD_MBOX,
10991 FWCMD_NICDRV_ALIVE3);
10992 tg3_write_mem(tp, NIC_SRAM_FW_CMD_LEN_MBOX, 4);
10993 tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX,
10994 TG3_FW_UPDATE_TIMEOUT_SEC);
10996 tg3_generate_fw_event(tp);
10998 tp->asf_counter = tp->asf_multiplier;
11001 spin_unlock(&tp->lock);
11004 tp->timer.expires = jiffies + tp->timer_offset;
11005 add_timer(&tp->timer);
11008 static void tg3_timer_init(struct tg3 *tp)
11010 if (tg3_flag(tp, TAGGED_STATUS) &&
11011 tg3_asic_rev(tp) != ASIC_REV_5717 &&
11012 !tg3_flag(tp, 57765_CLASS))
11013 tp->timer_offset = HZ;
11015 tp->timer_offset = HZ / 10;
11017 BUG_ON(tp->timer_offset > HZ);
11019 tp->timer_multiplier = (HZ / tp->timer_offset);
11020 tp->asf_multiplier = (HZ / tp->timer_offset) *
11021 TG3_FW_UPDATE_FREQ_SEC;
11023 init_timer(&tp->timer);
11024 tp->timer.data = (unsigned long) tp;
11025 tp->timer.function = tg3_timer;
11028 static void tg3_timer_start(struct tg3 *tp)
11030 tp->asf_counter = tp->asf_multiplier;
11031 tp->timer_counter = tp->timer_multiplier;
11033 tp->timer.expires = jiffies + tp->timer_offset;
11034 add_timer(&tp->timer);
11037 static void tg3_timer_stop(struct tg3 *tp)
11039 del_timer_sync(&tp->timer);
11042 /* Restart hardware after configuration changes, self-test, etc.
11043 * Invoked with tp->lock held.
11045 static int tg3_restart_hw(struct tg3 *tp, bool reset_phy)
11046 __releases(tp->lock)
11047 __acquires(tp->lock)
11051 err = tg3_init_hw(tp, reset_phy);
11053 netdev_err(tp->dev,
11054 "Failed to re-initialize device, aborting\n");
11055 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
11056 tg3_full_unlock(tp);
11057 tg3_timer_stop(tp);
11059 tg3_napi_enable(tp);
11060 dev_close(tp->dev);
11061 tg3_full_lock(tp, 0);
11066 static void tg3_reset_task(struct work_struct *work)
11068 struct tg3 *tp = container_of(work, struct tg3, reset_task);
11071 tg3_full_lock(tp, 0);
11073 if (!netif_running(tp->dev)) {
11074 tg3_flag_clear(tp, RESET_TASK_PENDING);
11075 tg3_full_unlock(tp);
11079 tg3_full_unlock(tp);
11083 tg3_netif_stop(tp);
11085 tg3_full_lock(tp, 1);
11087 if (tg3_flag(tp, TX_RECOVERY_PENDING)) {
11088 tp->write32_tx_mbox = tg3_write32_tx_mbox;
11089 tp->write32_rx_mbox = tg3_write_flush_reg32;
11090 tg3_flag_set(tp, MBOX_WRITE_REORDER);
11091 tg3_flag_clear(tp, TX_RECOVERY_PENDING);
11094 tg3_halt(tp, RESET_KIND_SHUTDOWN, 0);
11095 err = tg3_init_hw(tp, true);
11099 tg3_netif_start(tp);
11102 tg3_full_unlock(tp);
11107 tg3_flag_clear(tp, RESET_TASK_PENDING);
11110 static int tg3_request_irq(struct tg3 *tp, int irq_num)
11113 unsigned long flags;
11115 struct tg3_napi *tnapi = &tp->napi[irq_num];
11117 if (tp->irq_cnt == 1)
11118 name = tp->dev->name;
11120 name = &tnapi->irq_lbl[0];
11121 if (tnapi->tx_buffers && tnapi->rx_rcb)
11122 snprintf(name, IFNAMSIZ,
11123 "%s-txrx-%d", tp->dev->name, irq_num);
11124 else if (tnapi->tx_buffers)
11125 snprintf(name, IFNAMSIZ,
11126 "%s-tx-%d", tp->dev->name, irq_num);
11127 else if (tnapi->rx_rcb)
11128 snprintf(name, IFNAMSIZ,
11129 "%s-rx-%d", tp->dev->name, irq_num);
11131 snprintf(name, IFNAMSIZ,
11132 "%s-%d", tp->dev->name, irq_num);
11133 name[IFNAMSIZ-1] = 0;
11136 if (tg3_flag(tp, USING_MSI) || tg3_flag(tp, USING_MSIX)) {
11138 if (tg3_flag(tp, 1SHOT_MSI))
11139 fn = tg3_msi_1shot;
11142 fn = tg3_interrupt;
11143 if (tg3_flag(tp, TAGGED_STATUS))
11144 fn = tg3_interrupt_tagged;
11145 flags = IRQF_SHARED;
11148 return request_irq(tnapi->irq_vec, fn, flags, name, tnapi);
11151 static int tg3_test_interrupt(struct tg3 *tp)
11153 struct tg3_napi *tnapi = &tp->napi[0];
11154 struct net_device *dev = tp->dev;
11155 int err, i, intr_ok = 0;
11158 if (!netif_running(dev))
11161 tg3_disable_ints(tp);
11163 free_irq(tnapi->irq_vec, tnapi);
11166 * Turn off MSI one shot mode. Otherwise this test has no
11167 * observable way to know whether the interrupt was delivered.
11169 if (tg3_flag(tp, 57765_PLUS)) {
11170 val = tr32(MSGINT_MODE) | MSGINT_MODE_ONE_SHOT_DISABLE;
11171 tw32(MSGINT_MODE, val);
11174 err = request_irq(tnapi->irq_vec, tg3_test_isr,
11175 IRQF_SHARED, dev->name, tnapi);
11179 tnapi->hw_status->status &= ~SD_STATUS_UPDATED;
11180 tg3_enable_ints(tp);
11182 tw32_f(HOSTCC_MODE, tp->coalesce_mode | HOSTCC_MODE_ENABLE |
11185 for (i = 0; i < 5; i++) {
11186 u32 int_mbox, misc_host_ctrl;
11188 int_mbox = tr32_mailbox(tnapi->int_mbox);
11189 misc_host_ctrl = tr32(TG3PCI_MISC_HOST_CTRL);
11191 if ((int_mbox != 0) ||
11192 (misc_host_ctrl & MISC_HOST_CTRL_MASK_PCI_INT)) {
11197 if (tg3_flag(tp, 57765_PLUS) &&
11198 tnapi->hw_status->status_tag != tnapi->last_tag)
11199 tw32_mailbox_f(tnapi->int_mbox, tnapi->last_tag << 24);
11204 tg3_disable_ints(tp);
11206 free_irq(tnapi->irq_vec, tnapi);
11208 err = tg3_request_irq(tp, 0);
11214 /* Reenable MSI one shot mode. */
11215 if (tg3_flag(tp, 57765_PLUS) && tg3_flag(tp, 1SHOT_MSI)) {
11216 val = tr32(MSGINT_MODE) & ~MSGINT_MODE_ONE_SHOT_DISABLE;
11217 tw32(MSGINT_MODE, val);
11225 /* Returns 0 if MSI test succeeds or MSI test fails and INTx mode is
11226 * successfully restored
11228 static int tg3_test_msi(struct tg3 *tp)
11233 if (!tg3_flag(tp, USING_MSI))
11236 /* Turn off SERR reporting in case MSI terminates with Master
11239 pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd);
11240 pci_write_config_word(tp->pdev, PCI_COMMAND,
11241 pci_cmd & ~PCI_COMMAND_SERR);
11243 err = tg3_test_interrupt(tp);
11245 pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd);
11250 /* other failures */
11254 /* MSI test failed, go back to INTx mode */
11255 netdev_warn(tp->dev, "No interrupt was generated using MSI. Switching "
11256 "to INTx mode. Please report this failure to the PCI "
11257 "maintainer and include system chipset information\n");
11259 free_irq(tp->napi[0].irq_vec, &tp->napi[0]);
11261 pci_disable_msi(tp->pdev);
11263 tg3_flag_clear(tp, USING_MSI);
11264 tp->napi[0].irq_vec = tp->pdev->irq;
11266 err = tg3_request_irq(tp, 0);
11270 /* Need to reset the chip because the MSI cycle may have terminated
11271 * with Master Abort.
11273 tg3_full_lock(tp, 1);
11275 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
11276 err = tg3_init_hw(tp, true);
11278 tg3_full_unlock(tp);
11281 free_irq(tp->napi[0].irq_vec, &tp->napi[0]);
11286 static int tg3_request_firmware(struct tg3 *tp)
11288 const struct tg3_firmware_hdr *fw_hdr;
11290 if (request_firmware(&tp->fw, tp->fw_needed, &tp->pdev->dev)) {
11291 netdev_err(tp->dev, "Failed to load firmware \"%s\"\n",
11296 fw_hdr = (struct tg3_firmware_hdr *)tp->fw->data;
11298 /* Firmware blob starts with version numbers, followed by
11299 * start address and _full_ length including BSS sections
11300 * (which must be longer than the actual data, of course
11303 tp->fw_len = be32_to_cpu(fw_hdr->len); /* includes bss */
11304 if (tp->fw_len < (tp->fw->size - TG3_FW_HDR_LEN)) {
11305 netdev_err(tp->dev, "bogus length %d in \"%s\"\n",
11306 tp->fw_len, tp->fw_needed);
11307 release_firmware(tp->fw);
11312 /* We no longer need firmware; we have it. */
11313 tp->fw_needed = NULL;
11317 static u32 tg3_irq_count(struct tg3 *tp)
11319 u32 irq_cnt = max(tp->rxq_cnt, tp->txq_cnt);
11322 /* We want as many rx rings enabled as there are cpus.
11323 * In multiqueue MSI-X mode, the first MSI-X vector
11324 * only deals with link interrupts, etc, so we add
11325 * one to the number of vectors we are requesting.
11327 irq_cnt = min_t(unsigned, irq_cnt + 1, tp->irq_max);
11333 static bool tg3_enable_msix(struct tg3 *tp)
11336 struct msix_entry msix_ent[TG3_IRQ_MAX_VECS];
11338 tp->txq_cnt = tp->txq_req;
11339 tp->rxq_cnt = tp->rxq_req;
11341 tp->rxq_cnt = netif_get_num_default_rss_queues();
11342 if (tp->rxq_cnt > tp->rxq_max)
11343 tp->rxq_cnt = tp->rxq_max;
11345 /* Disable multiple TX rings by default. Simple round-robin hardware
11346 * scheduling of the TX rings can cause starvation of rings with
11347 * small packets when other rings have TSO or jumbo packets.
11352 tp->irq_cnt = tg3_irq_count(tp);
11354 for (i = 0; i < tp->irq_max; i++) {
11355 msix_ent[i].entry = i;
11356 msix_ent[i].vector = 0;
11359 rc = pci_enable_msix_range(tp->pdev, msix_ent, 1, tp->irq_cnt);
11362 } else if (rc < tp->irq_cnt) {
11363 netdev_notice(tp->dev, "Requested %d MSI-X vectors, received %d\n",
11366 tp->rxq_cnt = max(rc - 1, 1);
11368 tp->txq_cnt = min(tp->rxq_cnt, tp->txq_max);
11371 for (i = 0; i < tp->irq_max; i++)
11372 tp->napi[i].irq_vec = msix_ent[i].vector;
11374 if (netif_set_real_num_rx_queues(tp->dev, tp->rxq_cnt)) {
11375 pci_disable_msix(tp->pdev);
11379 if (tp->irq_cnt == 1)
11382 tg3_flag_set(tp, ENABLE_RSS);
11384 if (tp->txq_cnt > 1)
11385 tg3_flag_set(tp, ENABLE_TSS);
11387 netif_set_real_num_tx_queues(tp->dev, tp->txq_cnt);
11392 static void tg3_ints_init(struct tg3 *tp)
11394 if ((tg3_flag(tp, SUPPORT_MSI) || tg3_flag(tp, SUPPORT_MSIX)) &&
11395 !tg3_flag(tp, TAGGED_STATUS)) {
11396 /* All MSI supporting chips should support tagged
11397 * status. Assert that this is the case.
11399 netdev_warn(tp->dev,
11400 "MSI without TAGGED_STATUS? Not using MSI\n");
11404 if (tg3_flag(tp, SUPPORT_MSIX) && tg3_enable_msix(tp))
11405 tg3_flag_set(tp, USING_MSIX);
11406 else if (tg3_flag(tp, SUPPORT_MSI) && pci_enable_msi(tp->pdev) == 0)
11407 tg3_flag_set(tp, USING_MSI);
11409 if (tg3_flag(tp, USING_MSI) || tg3_flag(tp, USING_MSIX)) {
11410 u32 msi_mode = tr32(MSGINT_MODE);
11411 if (tg3_flag(tp, USING_MSIX) && tp->irq_cnt > 1)
11412 msi_mode |= MSGINT_MODE_MULTIVEC_EN;
11413 if (!tg3_flag(tp, 1SHOT_MSI))
11414 msi_mode |= MSGINT_MODE_ONE_SHOT_DISABLE;
11415 tw32(MSGINT_MODE, msi_mode | MSGINT_MODE_ENABLE);
11418 if (!tg3_flag(tp, USING_MSIX)) {
11420 tp->napi[0].irq_vec = tp->pdev->irq;
11423 if (tp->irq_cnt == 1) {
11426 netif_set_real_num_tx_queues(tp->dev, 1);
11427 netif_set_real_num_rx_queues(tp->dev, 1);
11431 static void tg3_ints_fini(struct tg3 *tp)
11433 if (tg3_flag(tp, USING_MSIX))
11434 pci_disable_msix(tp->pdev);
11435 else if (tg3_flag(tp, USING_MSI))
11436 pci_disable_msi(tp->pdev);
11437 tg3_flag_clear(tp, USING_MSI);
11438 tg3_flag_clear(tp, USING_MSIX);
11439 tg3_flag_clear(tp, ENABLE_RSS);
11440 tg3_flag_clear(tp, ENABLE_TSS);
11443 static int tg3_start(struct tg3 *tp, bool reset_phy, bool test_irq,
11446 struct net_device *dev = tp->dev;
11450 * Setup interrupts first so we know how
11451 * many NAPI resources to allocate
11455 tg3_rss_check_indir_tbl(tp);
11457 /* The placement of this call is tied
11458 * to the setup and use of Host TX descriptors.
11460 err = tg3_alloc_consistent(tp);
11462 goto out_ints_fini;
11466 tg3_napi_enable(tp);
11468 for (i = 0; i < tp->irq_cnt; i++) {
11469 struct tg3_napi *tnapi = &tp->napi[i];
11470 err = tg3_request_irq(tp, i);
11472 for (i--; i >= 0; i--) {
11473 tnapi = &tp->napi[i];
11474 free_irq(tnapi->irq_vec, tnapi);
11476 goto out_napi_fini;
11480 tg3_full_lock(tp, 0);
11483 tg3_ape_driver_state_change(tp, RESET_KIND_INIT);
11485 err = tg3_init_hw(tp, reset_phy);
11487 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
11488 tg3_free_rings(tp);
11491 tg3_full_unlock(tp);
11496 if (test_irq && tg3_flag(tp, USING_MSI)) {
11497 err = tg3_test_msi(tp);
11500 tg3_full_lock(tp, 0);
11501 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
11502 tg3_free_rings(tp);
11503 tg3_full_unlock(tp);
11505 goto out_napi_fini;
11508 if (!tg3_flag(tp, 57765_PLUS) && tg3_flag(tp, USING_MSI)) {
11509 u32 val = tr32(PCIE_TRANSACTION_CFG);
11511 tw32(PCIE_TRANSACTION_CFG,
11512 val | PCIE_TRANS_CFG_1SHOT_MSI);
11518 tg3_hwmon_open(tp);
11520 tg3_full_lock(tp, 0);
11522 tg3_timer_start(tp);
11523 tg3_flag_set(tp, INIT_COMPLETE);
11524 tg3_enable_ints(tp);
11529 tg3_ptp_resume(tp);
11532 tg3_full_unlock(tp);
11534 netif_tx_start_all_queues(dev);
11537 * Reset loopback feature if it was turned on while the device was down
11538 * make sure that it's installed properly now.
11540 if (dev->features & NETIF_F_LOOPBACK)
11541 tg3_set_loopback(dev, dev->features);
11546 for (i = tp->irq_cnt - 1; i >= 0; i--) {
11547 struct tg3_napi *tnapi = &tp->napi[i];
11548 free_irq(tnapi->irq_vec, tnapi);
11552 tg3_napi_disable(tp);
11554 tg3_free_consistent(tp);
11562 static void tg3_stop(struct tg3 *tp)
11566 tg3_reset_task_cancel(tp);
11567 tg3_netif_stop(tp);
11569 tg3_timer_stop(tp);
11571 tg3_hwmon_close(tp);
11575 tg3_full_lock(tp, 1);
11577 tg3_disable_ints(tp);
11579 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
11580 tg3_free_rings(tp);
11581 tg3_flag_clear(tp, INIT_COMPLETE);
11583 tg3_full_unlock(tp);
11585 for (i = tp->irq_cnt - 1; i >= 0; i--) {
11586 struct tg3_napi *tnapi = &tp->napi[i];
11587 free_irq(tnapi->irq_vec, tnapi);
11594 tg3_free_consistent(tp);
11597 static int tg3_open(struct net_device *dev)
11599 struct tg3 *tp = netdev_priv(dev);
11602 if (tp->fw_needed) {
11603 err = tg3_request_firmware(tp);
11604 if (tg3_asic_rev(tp) == ASIC_REV_57766) {
11606 netdev_warn(tp->dev, "EEE capability disabled\n");
11607 tp->phy_flags &= ~TG3_PHYFLG_EEE_CAP;
11608 } else if (!(tp->phy_flags & TG3_PHYFLG_EEE_CAP)) {
11609 netdev_warn(tp->dev, "EEE capability restored\n");
11610 tp->phy_flags |= TG3_PHYFLG_EEE_CAP;
11612 } else if (tg3_chip_rev_id(tp) == CHIPREV_ID_5701_A0) {
11616 netdev_warn(tp->dev, "TSO capability disabled\n");
11617 tg3_flag_clear(tp, TSO_CAPABLE);
11618 } else if (!tg3_flag(tp, TSO_CAPABLE)) {
11619 netdev_notice(tp->dev, "TSO capability restored\n");
11620 tg3_flag_set(tp, TSO_CAPABLE);
11624 tg3_carrier_off(tp);
11626 err = tg3_power_up(tp);
11630 tg3_full_lock(tp, 0);
11632 tg3_disable_ints(tp);
11633 tg3_flag_clear(tp, INIT_COMPLETE);
11635 tg3_full_unlock(tp);
11637 err = tg3_start(tp,
11638 !(tp->phy_flags & TG3_PHYFLG_KEEP_LINK_ON_PWRDN),
11641 tg3_frob_aux_power(tp, false);
11642 pci_set_power_state(tp->pdev, PCI_D3hot);
11645 if (tg3_flag(tp, PTP_CAPABLE)) {
11646 tp->ptp_clock = ptp_clock_register(&tp->ptp_info,
11648 if (IS_ERR(tp->ptp_clock))
11649 tp->ptp_clock = NULL;
11655 static int tg3_close(struct net_device *dev)
11657 struct tg3 *tp = netdev_priv(dev);
11663 /* Clear stats across close / open calls */
11664 memset(&tp->net_stats_prev, 0, sizeof(tp->net_stats_prev));
11665 memset(&tp->estats_prev, 0, sizeof(tp->estats_prev));
11667 if (pci_device_is_present(tp->pdev)) {
11668 tg3_power_down_prepare(tp);
11670 tg3_carrier_off(tp);
11675 static inline u64 get_stat64(tg3_stat64_t *val)
11677 return ((u64)val->high << 32) | ((u64)val->low);
11680 static u64 tg3_calc_crc_errors(struct tg3 *tp)
11682 struct tg3_hw_stats *hw_stats = tp->hw_stats;
11684 if (!(tp->phy_flags & TG3_PHYFLG_PHY_SERDES) &&
11685 (tg3_asic_rev(tp) == ASIC_REV_5700 ||
11686 tg3_asic_rev(tp) == ASIC_REV_5701)) {
11689 if (!tg3_readphy(tp, MII_TG3_TEST1, &val)) {
11690 tg3_writephy(tp, MII_TG3_TEST1,
11691 val | MII_TG3_TEST1_CRC_EN);
11692 tg3_readphy(tp, MII_TG3_RXR_COUNTERS, &val);
11696 tp->phy_crc_errors += val;
11698 return tp->phy_crc_errors;
11701 return get_stat64(&hw_stats->rx_fcs_errors);
11704 #define ESTAT_ADD(member) \
11705 estats->member = old_estats->member + \
11706 get_stat64(&hw_stats->member)
11708 static void tg3_get_estats(struct tg3 *tp, struct tg3_ethtool_stats *estats)
11710 struct tg3_ethtool_stats *old_estats = &tp->estats_prev;
11711 struct tg3_hw_stats *hw_stats = tp->hw_stats;
11713 ESTAT_ADD(rx_octets);
11714 ESTAT_ADD(rx_fragments);
11715 ESTAT_ADD(rx_ucast_packets);
11716 ESTAT_ADD(rx_mcast_packets);
11717 ESTAT_ADD(rx_bcast_packets);
11718 ESTAT_ADD(rx_fcs_errors);
11719 ESTAT_ADD(rx_align_errors);
11720 ESTAT_ADD(rx_xon_pause_rcvd);
11721 ESTAT_ADD(rx_xoff_pause_rcvd);
11722 ESTAT_ADD(rx_mac_ctrl_rcvd);
11723 ESTAT_ADD(rx_xoff_entered);
11724 ESTAT_ADD(rx_frame_too_long_errors);
11725 ESTAT_ADD(rx_jabbers);
11726 ESTAT_ADD(rx_undersize_packets);
11727 ESTAT_ADD(rx_in_length_errors);
11728 ESTAT_ADD(rx_out_length_errors);
11729 ESTAT_ADD(rx_64_or_less_octet_packets);
11730 ESTAT_ADD(rx_65_to_127_octet_packets);
11731 ESTAT_ADD(rx_128_to_255_octet_packets);
11732 ESTAT_ADD(rx_256_to_511_octet_packets);
11733 ESTAT_ADD(rx_512_to_1023_octet_packets);
11734 ESTAT_ADD(rx_1024_to_1522_octet_packets);
11735 ESTAT_ADD(rx_1523_to_2047_octet_packets);
11736 ESTAT_ADD(rx_2048_to_4095_octet_packets);
11737 ESTAT_ADD(rx_4096_to_8191_octet_packets);
11738 ESTAT_ADD(rx_8192_to_9022_octet_packets);
11740 ESTAT_ADD(tx_octets);
11741 ESTAT_ADD(tx_collisions);
11742 ESTAT_ADD(tx_xon_sent);
11743 ESTAT_ADD(tx_xoff_sent);
11744 ESTAT_ADD(tx_flow_control);
11745 ESTAT_ADD(tx_mac_errors);
11746 ESTAT_ADD(tx_single_collisions);
11747 ESTAT_ADD(tx_mult_collisions);
11748 ESTAT_ADD(tx_deferred);
11749 ESTAT_ADD(tx_excessive_collisions);
11750 ESTAT_ADD(tx_late_collisions);
11751 ESTAT_ADD(tx_collide_2times);
11752 ESTAT_ADD(tx_collide_3times);
11753 ESTAT_ADD(tx_collide_4times);
11754 ESTAT_ADD(tx_collide_5times);
11755 ESTAT_ADD(tx_collide_6times);
11756 ESTAT_ADD(tx_collide_7times);
11757 ESTAT_ADD(tx_collide_8times);
11758 ESTAT_ADD(tx_collide_9times);
11759 ESTAT_ADD(tx_collide_10times);
11760 ESTAT_ADD(tx_collide_11times);
11761 ESTAT_ADD(tx_collide_12times);
11762 ESTAT_ADD(tx_collide_13times);
11763 ESTAT_ADD(tx_collide_14times);
11764 ESTAT_ADD(tx_collide_15times);
11765 ESTAT_ADD(tx_ucast_packets);
11766 ESTAT_ADD(tx_mcast_packets);
11767 ESTAT_ADD(tx_bcast_packets);
11768 ESTAT_ADD(tx_carrier_sense_errors);
11769 ESTAT_ADD(tx_discards);
11770 ESTAT_ADD(tx_errors);
11772 ESTAT_ADD(dma_writeq_full);
11773 ESTAT_ADD(dma_write_prioq_full);
11774 ESTAT_ADD(rxbds_empty);
11775 ESTAT_ADD(rx_discards);
11776 ESTAT_ADD(rx_errors);
11777 ESTAT_ADD(rx_threshold_hit);
11779 ESTAT_ADD(dma_readq_full);
11780 ESTAT_ADD(dma_read_prioq_full);
11781 ESTAT_ADD(tx_comp_queue_full);
11783 ESTAT_ADD(ring_set_send_prod_index);
11784 ESTAT_ADD(ring_status_update);
11785 ESTAT_ADD(nic_irqs);
11786 ESTAT_ADD(nic_avoided_irqs);
11787 ESTAT_ADD(nic_tx_threshold_hit);
11789 ESTAT_ADD(mbuf_lwm_thresh_hit);
11792 static void tg3_get_nstats(struct tg3 *tp, struct rtnl_link_stats64 *stats)
11794 struct rtnl_link_stats64 *old_stats = &tp->net_stats_prev;
11795 struct tg3_hw_stats *hw_stats = tp->hw_stats;
11797 stats->rx_packets = old_stats->rx_packets +
11798 get_stat64(&hw_stats->rx_ucast_packets) +
11799 get_stat64(&hw_stats->rx_mcast_packets) +
11800 get_stat64(&hw_stats->rx_bcast_packets);
11802 stats->tx_packets = old_stats->tx_packets +
11803 get_stat64(&hw_stats->tx_ucast_packets) +
11804 get_stat64(&hw_stats->tx_mcast_packets) +
11805 get_stat64(&hw_stats->tx_bcast_packets);
11807 stats->rx_bytes = old_stats->rx_bytes +
11808 get_stat64(&hw_stats->rx_octets);
11809 stats->tx_bytes = old_stats->tx_bytes +
11810 get_stat64(&hw_stats->tx_octets);
11812 stats->rx_errors = old_stats->rx_errors +
11813 get_stat64(&hw_stats->rx_errors);
11814 stats->tx_errors = old_stats->tx_errors +
11815 get_stat64(&hw_stats->tx_errors) +
11816 get_stat64(&hw_stats->tx_mac_errors) +
11817 get_stat64(&hw_stats->tx_carrier_sense_errors) +
11818 get_stat64(&hw_stats->tx_discards);
11820 stats->multicast = old_stats->multicast +
11821 get_stat64(&hw_stats->rx_mcast_packets);
11822 stats->collisions = old_stats->collisions +
11823 get_stat64(&hw_stats->tx_collisions);
11825 stats->rx_length_errors = old_stats->rx_length_errors +
11826 get_stat64(&hw_stats->rx_frame_too_long_errors) +
11827 get_stat64(&hw_stats->rx_undersize_packets);
11829 stats->rx_frame_errors = old_stats->rx_frame_errors +
11830 get_stat64(&hw_stats->rx_align_errors);
11831 stats->tx_aborted_errors = old_stats->tx_aborted_errors +
11832 get_stat64(&hw_stats->tx_discards);
11833 stats->tx_carrier_errors = old_stats->tx_carrier_errors +
11834 get_stat64(&hw_stats->tx_carrier_sense_errors);
11836 stats->rx_crc_errors = old_stats->rx_crc_errors +
11837 tg3_calc_crc_errors(tp);
11839 stats->rx_missed_errors = old_stats->rx_missed_errors +
11840 get_stat64(&hw_stats->rx_discards);
11842 stats->rx_dropped = tp->rx_dropped;
11843 stats->tx_dropped = tp->tx_dropped;
11846 static int tg3_get_regs_len(struct net_device *dev)
11848 return TG3_REG_BLK_SIZE;
11851 static void tg3_get_regs(struct net_device *dev,
11852 struct ethtool_regs *regs, void *_p)
11854 struct tg3 *tp = netdev_priv(dev);
11858 memset(_p, 0, TG3_REG_BLK_SIZE);
11860 if (tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER)
11863 tg3_full_lock(tp, 0);
11865 tg3_dump_legacy_regs(tp, (u32 *)_p);
11867 tg3_full_unlock(tp);
11870 static int tg3_get_eeprom_len(struct net_device *dev)
11872 struct tg3 *tp = netdev_priv(dev);
11874 return tp->nvram_size;
11877 static int tg3_get_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom, u8 *data)
11879 struct tg3 *tp = netdev_priv(dev);
11882 u32 i, offset, len, b_offset, b_count;
11885 if (tg3_flag(tp, NO_NVRAM))
11888 offset = eeprom->offset;
11892 eeprom->magic = TG3_EEPROM_MAGIC;
11895 /* adjustments to start on required 4 byte boundary */
11896 b_offset = offset & 3;
11897 b_count = 4 - b_offset;
11898 if (b_count > len) {
11899 /* i.e. offset=1 len=2 */
11902 ret = tg3_nvram_read_be32(tp, offset-b_offset, &val);
11905 memcpy(data, ((char *)&val) + b_offset, b_count);
11908 eeprom->len += b_count;
11911 /* read bytes up to the last 4 byte boundary */
11912 pd = &data[eeprom->len];
11913 for (i = 0; i < (len - (len & 3)); i += 4) {
11914 ret = tg3_nvram_read_be32(tp, offset + i, &val);
11919 memcpy(pd + i, &val, 4);
11924 /* read last bytes not ending on 4 byte boundary */
11925 pd = &data[eeprom->len];
11927 b_offset = offset + len - b_count;
11928 ret = tg3_nvram_read_be32(tp, b_offset, &val);
11931 memcpy(pd, &val, b_count);
11932 eeprom->len += b_count;
11937 static int tg3_set_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom, u8 *data)
11939 struct tg3 *tp = netdev_priv(dev);
11941 u32 offset, len, b_offset, odd_len;
11945 if (tg3_flag(tp, NO_NVRAM) ||
11946 eeprom->magic != TG3_EEPROM_MAGIC)
11949 offset = eeprom->offset;
11952 if ((b_offset = (offset & 3))) {
11953 /* adjustments to start on required 4 byte boundary */
11954 ret = tg3_nvram_read_be32(tp, offset-b_offset, &start);
11965 /* adjustments to end on required 4 byte boundary */
11967 len = (len + 3) & ~3;
11968 ret = tg3_nvram_read_be32(tp, offset+len-4, &end);
11974 if (b_offset || odd_len) {
11975 buf = kmalloc(len, GFP_KERNEL);
11979 memcpy(buf, &start, 4);
11981 memcpy(buf+len-4, &end, 4);
11982 memcpy(buf + b_offset, data, eeprom->len);
11985 ret = tg3_nvram_write_block(tp, offset, len, buf);
11993 static int tg3_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
11995 struct tg3 *tp = netdev_priv(dev);
11997 if (tg3_flag(tp, USE_PHYLIB)) {
11998 struct phy_device *phydev;
11999 if (!(tp->phy_flags & TG3_PHYFLG_IS_CONNECTED))
12001 phydev = tp->mdio_bus->phy_map[tp->phy_addr];
12002 return phy_ethtool_gset(phydev, cmd);
12005 cmd->supported = (SUPPORTED_Autoneg);
12007 if (!(tp->phy_flags & TG3_PHYFLG_10_100_ONLY))
12008 cmd->supported |= (SUPPORTED_1000baseT_Half |
12009 SUPPORTED_1000baseT_Full);
12011 if (!(tp->phy_flags & TG3_PHYFLG_ANY_SERDES)) {
12012 cmd->supported |= (SUPPORTED_100baseT_Half |
12013 SUPPORTED_100baseT_Full |
12014 SUPPORTED_10baseT_Half |
12015 SUPPORTED_10baseT_Full |
12017 cmd->port = PORT_TP;
12019 cmd->supported |= SUPPORTED_FIBRE;
12020 cmd->port = PORT_FIBRE;
12023 cmd->advertising = tp->link_config.advertising;
12024 if (tg3_flag(tp, PAUSE_AUTONEG)) {
12025 if (tp->link_config.flowctrl & FLOW_CTRL_RX) {
12026 if (tp->link_config.flowctrl & FLOW_CTRL_TX) {
12027 cmd->advertising |= ADVERTISED_Pause;
12029 cmd->advertising |= ADVERTISED_Pause |
12030 ADVERTISED_Asym_Pause;
12032 } else if (tp->link_config.flowctrl & FLOW_CTRL_TX) {
12033 cmd->advertising |= ADVERTISED_Asym_Pause;
12036 if (netif_running(dev) && tp->link_up) {
12037 ethtool_cmd_speed_set(cmd, tp->link_config.active_speed);
12038 cmd->duplex = tp->link_config.active_duplex;
12039 cmd->lp_advertising = tp->link_config.rmt_adv;
12040 if (!(tp->phy_flags & TG3_PHYFLG_ANY_SERDES)) {
12041 if (tp->phy_flags & TG3_PHYFLG_MDIX_STATE)
12042 cmd->eth_tp_mdix = ETH_TP_MDI_X;
12044 cmd->eth_tp_mdix = ETH_TP_MDI;
12047 ethtool_cmd_speed_set(cmd, SPEED_UNKNOWN);
12048 cmd->duplex = DUPLEX_UNKNOWN;
12049 cmd->eth_tp_mdix = ETH_TP_MDI_INVALID;
12051 cmd->phy_address = tp->phy_addr;
12052 cmd->transceiver = XCVR_INTERNAL;
12053 cmd->autoneg = tp->link_config.autoneg;
12059 static int tg3_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
12061 struct tg3 *tp = netdev_priv(dev);
12062 u32 speed = ethtool_cmd_speed(cmd);
12064 if (tg3_flag(tp, USE_PHYLIB)) {
12065 struct phy_device *phydev;
12066 if (!(tp->phy_flags & TG3_PHYFLG_IS_CONNECTED))
12068 phydev = tp->mdio_bus->phy_map[tp->phy_addr];
12069 return phy_ethtool_sset(phydev, cmd);
12072 if (cmd->autoneg != AUTONEG_ENABLE &&
12073 cmd->autoneg != AUTONEG_DISABLE)
12076 if (cmd->autoneg == AUTONEG_DISABLE &&
12077 cmd->duplex != DUPLEX_FULL &&
12078 cmd->duplex != DUPLEX_HALF)
12081 if (cmd->autoneg == AUTONEG_ENABLE) {
12082 u32 mask = ADVERTISED_Autoneg |
12084 ADVERTISED_Asym_Pause;
12086 if (!(tp->phy_flags & TG3_PHYFLG_10_100_ONLY))
12087 mask |= ADVERTISED_1000baseT_Half |
12088 ADVERTISED_1000baseT_Full;
12090 if (!(tp->phy_flags & TG3_PHYFLG_ANY_SERDES))
12091 mask |= ADVERTISED_100baseT_Half |
12092 ADVERTISED_100baseT_Full |
12093 ADVERTISED_10baseT_Half |
12094 ADVERTISED_10baseT_Full |
12097 mask |= ADVERTISED_FIBRE;
12099 if (cmd->advertising & ~mask)
12102 mask &= (ADVERTISED_1000baseT_Half |
12103 ADVERTISED_1000baseT_Full |
12104 ADVERTISED_100baseT_Half |
12105 ADVERTISED_100baseT_Full |
12106 ADVERTISED_10baseT_Half |
12107 ADVERTISED_10baseT_Full);
12109 cmd->advertising &= mask;
12111 if (tp->phy_flags & TG3_PHYFLG_ANY_SERDES) {
12112 if (speed != SPEED_1000)
12115 if (cmd->duplex != DUPLEX_FULL)
12118 if (speed != SPEED_100 &&
12124 tg3_full_lock(tp, 0);
12126 tp->link_config.autoneg = cmd->autoneg;
12127 if (cmd->autoneg == AUTONEG_ENABLE) {
12128 tp->link_config.advertising = (cmd->advertising |
12129 ADVERTISED_Autoneg);
12130 tp->link_config.speed = SPEED_UNKNOWN;
12131 tp->link_config.duplex = DUPLEX_UNKNOWN;
12133 tp->link_config.advertising = 0;
12134 tp->link_config.speed = speed;
12135 tp->link_config.duplex = cmd->duplex;
12138 tp->phy_flags |= TG3_PHYFLG_USER_CONFIGURED;
12140 tg3_warn_mgmt_link_flap(tp);
12142 if (netif_running(dev))
12143 tg3_setup_phy(tp, true);
12145 tg3_full_unlock(tp);
12150 static void tg3_get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *info)
12152 struct tg3 *tp = netdev_priv(dev);
12154 strlcpy(info->driver, DRV_MODULE_NAME, sizeof(info->driver));
12155 strlcpy(info->version, DRV_MODULE_VERSION, sizeof(info->version));
12156 strlcpy(info->fw_version, tp->fw_ver, sizeof(info->fw_version));
12157 strlcpy(info->bus_info, pci_name(tp->pdev), sizeof(info->bus_info));
12160 static void tg3_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
12162 struct tg3 *tp = netdev_priv(dev);
12164 if (tg3_flag(tp, WOL_CAP) && device_can_wakeup(&tp->pdev->dev))
12165 wol->supported = WAKE_MAGIC;
12167 wol->supported = 0;
12169 if (tg3_flag(tp, WOL_ENABLE) && device_can_wakeup(&tp->pdev->dev))
12170 wol->wolopts = WAKE_MAGIC;
12171 memset(&wol->sopass, 0, sizeof(wol->sopass));
12174 static int tg3_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
12176 struct tg3 *tp = netdev_priv(dev);
12177 struct device *dp = &tp->pdev->dev;
12179 if (wol->wolopts & ~WAKE_MAGIC)
12181 if ((wol->wolopts & WAKE_MAGIC) &&
12182 !(tg3_flag(tp, WOL_CAP) && device_can_wakeup(dp)))
12185 device_set_wakeup_enable(dp, wol->wolopts & WAKE_MAGIC);
12187 if (device_may_wakeup(dp))
12188 tg3_flag_set(tp, WOL_ENABLE);
12190 tg3_flag_clear(tp, WOL_ENABLE);
12195 static u32 tg3_get_msglevel(struct net_device *dev)
12197 struct tg3 *tp = netdev_priv(dev);
12198 return tp->msg_enable;
12201 static void tg3_set_msglevel(struct net_device *dev, u32 value)
12203 struct tg3 *tp = netdev_priv(dev);
12204 tp->msg_enable = value;
12207 static int tg3_nway_reset(struct net_device *dev)
12209 struct tg3 *tp = netdev_priv(dev);
12212 if (!netif_running(dev))
12215 if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES)
12218 tg3_warn_mgmt_link_flap(tp);
12220 if (tg3_flag(tp, USE_PHYLIB)) {
12221 if (!(tp->phy_flags & TG3_PHYFLG_IS_CONNECTED))
12223 r = phy_start_aneg(tp->mdio_bus->phy_map[tp->phy_addr]);
12227 spin_lock_bh(&tp->lock);
12229 tg3_readphy(tp, MII_BMCR, &bmcr);
12230 if (!tg3_readphy(tp, MII_BMCR, &bmcr) &&
12231 ((bmcr & BMCR_ANENABLE) ||
12232 (tp->phy_flags & TG3_PHYFLG_PARALLEL_DETECT))) {
12233 tg3_writephy(tp, MII_BMCR, bmcr | BMCR_ANRESTART |
12237 spin_unlock_bh(&tp->lock);
12243 static void tg3_get_ringparam(struct net_device *dev, struct ethtool_ringparam *ering)
12245 struct tg3 *tp = netdev_priv(dev);
12247 ering->rx_max_pending = tp->rx_std_ring_mask;
12248 if (tg3_flag(tp, JUMBO_RING_ENABLE))
12249 ering->rx_jumbo_max_pending = tp->rx_jmb_ring_mask;
12251 ering->rx_jumbo_max_pending = 0;
12253 ering->tx_max_pending = TG3_TX_RING_SIZE - 1;
12255 ering->rx_pending = tp->rx_pending;
12256 if (tg3_flag(tp, JUMBO_RING_ENABLE))
12257 ering->rx_jumbo_pending = tp->rx_jumbo_pending;
12259 ering->rx_jumbo_pending = 0;
12261 ering->tx_pending = tp->napi[0].tx_pending;
12264 static int tg3_set_ringparam(struct net_device *dev, struct ethtool_ringparam *ering)
12266 struct tg3 *tp = netdev_priv(dev);
12267 int i, irq_sync = 0, err = 0;
12269 if ((ering->rx_pending > tp->rx_std_ring_mask) ||
12270 (ering->rx_jumbo_pending > tp->rx_jmb_ring_mask) ||
12271 (ering->tx_pending > TG3_TX_RING_SIZE - 1) ||
12272 (ering->tx_pending <= MAX_SKB_FRAGS) ||
12273 (tg3_flag(tp, TSO_BUG) &&
12274 (ering->tx_pending <= (MAX_SKB_FRAGS * 3))))
12277 if (netif_running(dev)) {
12279 tg3_netif_stop(tp);
12283 tg3_full_lock(tp, irq_sync);
12285 tp->rx_pending = ering->rx_pending;
12287 if (tg3_flag(tp, MAX_RXPEND_64) &&
12288 tp->rx_pending > 63)
12289 tp->rx_pending = 63;
12290 tp->rx_jumbo_pending = ering->rx_jumbo_pending;
12292 for (i = 0; i < tp->irq_max; i++)
12293 tp->napi[i].tx_pending = ering->tx_pending;
12295 if (netif_running(dev)) {
12296 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
12297 err = tg3_restart_hw(tp, false);
12299 tg3_netif_start(tp);
12302 tg3_full_unlock(tp);
12304 if (irq_sync && !err)
12310 static void tg3_get_pauseparam(struct net_device *dev, struct ethtool_pauseparam *epause)
12312 struct tg3 *tp = netdev_priv(dev);
12314 epause->autoneg = !!tg3_flag(tp, PAUSE_AUTONEG);
12316 if (tp->link_config.flowctrl & FLOW_CTRL_RX)
12317 epause->rx_pause = 1;
12319 epause->rx_pause = 0;
12321 if (tp->link_config.flowctrl & FLOW_CTRL_TX)
12322 epause->tx_pause = 1;
12324 epause->tx_pause = 0;
12327 static int tg3_set_pauseparam(struct net_device *dev, struct ethtool_pauseparam *epause)
12329 struct tg3 *tp = netdev_priv(dev);
12332 if (tp->link_config.autoneg == AUTONEG_ENABLE)
12333 tg3_warn_mgmt_link_flap(tp);
12335 if (tg3_flag(tp, USE_PHYLIB)) {
12337 struct phy_device *phydev;
12339 phydev = tp->mdio_bus->phy_map[tp->phy_addr];
12341 if (!(phydev->supported & SUPPORTED_Pause) ||
12342 (!(phydev->supported & SUPPORTED_Asym_Pause) &&
12343 (epause->rx_pause != epause->tx_pause)))
12346 tp->link_config.flowctrl = 0;
12347 if (epause->rx_pause) {
12348 tp->link_config.flowctrl |= FLOW_CTRL_RX;
12350 if (epause->tx_pause) {
12351 tp->link_config.flowctrl |= FLOW_CTRL_TX;
12352 newadv = ADVERTISED_Pause;
12354 newadv = ADVERTISED_Pause |
12355 ADVERTISED_Asym_Pause;
12356 } else if (epause->tx_pause) {
12357 tp->link_config.flowctrl |= FLOW_CTRL_TX;
12358 newadv = ADVERTISED_Asym_Pause;
12362 if (epause->autoneg)
12363 tg3_flag_set(tp, PAUSE_AUTONEG);
12365 tg3_flag_clear(tp, PAUSE_AUTONEG);
12367 if (tp->phy_flags & TG3_PHYFLG_IS_CONNECTED) {
12368 u32 oldadv = phydev->advertising &
12369 (ADVERTISED_Pause | ADVERTISED_Asym_Pause);
12370 if (oldadv != newadv) {
12371 phydev->advertising &=
12372 ~(ADVERTISED_Pause |
12373 ADVERTISED_Asym_Pause);
12374 phydev->advertising |= newadv;
12375 if (phydev->autoneg) {
12377 * Always renegotiate the link to
12378 * inform our link partner of our
12379 * flow control settings, even if the
12380 * flow control is forced. Let
12381 * tg3_adjust_link() do the final
12382 * flow control setup.
12384 return phy_start_aneg(phydev);
12388 if (!epause->autoneg)
12389 tg3_setup_flow_control(tp, 0, 0);
12391 tp->link_config.advertising &=
12392 ~(ADVERTISED_Pause |
12393 ADVERTISED_Asym_Pause);
12394 tp->link_config.advertising |= newadv;
12399 if (netif_running(dev)) {
12400 tg3_netif_stop(tp);
12404 tg3_full_lock(tp, irq_sync);
12406 if (epause->autoneg)
12407 tg3_flag_set(tp, PAUSE_AUTONEG);
12409 tg3_flag_clear(tp, PAUSE_AUTONEG);
12410 if (epause->rx_pause)
12411 tp->link_config.flowctrl |= FLOW_CTRL_RX;
12413 tp->link_config.flowctrl &= ~FLOW_CTRL_RX;
12414 if (epause->tx_pause)
12415 tp->link_config.flowctrl |= FLOW_CTRL_TX;
12417 tp->link_config.flowctrl &= ~FLOW_CTRL_TX;
12419 if (netif_running(dev)) {
12420 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
12421 err = tg3_restart_hw(tp, false);
12423 tg3_netif_start(tp);
12426 tg3_full_unlock(tp);
12429 tp->phy_flags |= TG3_PHYFLG_USER_CONFIGURED;
12434 static int tg3_get_sset_count(struct net_device *dev, int sset)
12438 return TG3_NUM_TEST;
12440 return TG3_NUM_STATS;
12442 return -EOPNOTSUPP;
12446 static int tg3_get_rxnfc(struct net_device *dev, struct ethtool_rxnfc *info,
12447 u32 *rules __always_unused)
12449 struct tg3 *tp = netdev_priv(dev);
12451 if (!tg3_flag(tp, SUPPORT_MSIX))
12452 return -EOPNOTSUPP;
12454 switch (info->cmd) {
12455 case ETHTOOL_GRXRINGS:
12456 if (netif_running(tp->dev))
12457 info->data = tp->rxq_cnt;
12459 info->data = num_online_cpus();
12460 if (info->data > TG3_RSS_MAX_NUM_QS)
12461 info->data = TG3_RSS_MAX_NUM_QS;
12464 /* The first interrupt vector only
12465 * handles link interrupts.
12471 return -EOPNOTSUPP;
12475 static u32 tg3_get_rxfh_indir_size(struct net_device *dev)
12478 struct tg3 *tp = netdev_priv(dev);
12480 if (tg3_flag(tp, SUPPORT_MSIX))
12481 size = TG3_RSS_INDIR_TBL_SIZE;
12486 static int tg3_get_rxfh_indir(struct net_device *dev, u32 *indir)
12488 struct tg3 *tp = netdev_priv(dev);
12491 for (i = 0; i < TG3_RSS_INDIR_TBL_SIZE; i++)
12492 indir[i] = tp->rss_ind_tbl[i];
12497 static int tg3_set_rxfh_indir(struct net_device *dev, const u32 *indir)
12499 struct tg3 *tp = netdev_priv(dev);
12502 for (i = 0; i < TG3_RSS_INDIR_TBL_SIZE; i++)
12503 tp->rss_ind_tbl[i] = indir[i];
12505 if (!netif_running(dev) || !tg3_flag(tp, ENABLE_RSS))
12508 /* It is legal to write the indirection
12509 * table while the device is running.
12511 tg3_full_lock(tp, 0);
12512 tg3_rss_write_indir_tbl(tp);
12513 tg3_full_unlock(tp);
12518 static void tg3_get_channels(struct net_device *dev,
12519 struct ethtool_channels *channel)
12521 struct tg3 *tp = netdev_priv(dev);
12522 u32 deflt_qs = netif_get_num_default_rss_queues();
12524 channel->max_rx = tp->rxq_max;
12525 channel->max_tx = tp->txq_max;
12527 if (netif_running(dev)) {
12528 channel->rx_count = tp->rxq_cnt;
12529 channel->tx_count = tp->txq_cnt;
12532 channel->rx_count = tp->rxq_req;
12534 channel->rx_count = min(deflt_qs, tp->rxq_max);
12537 channel->tx_count = tp->txq_req;
12539 channel->tx_count = min(deflt_qs, tp->txq_max);
12543 static int tg3_set_channels(struct net_device *dev,
12544 struct ethtool_channels *channel)
12546 struct tg3 *tp = netdev_priv(dev);
12548 if (!tg3_flag(tp, SUPPORT_MSIX))
12549 return -EOPNOTSUPP;
12551 if (channel->rx_count > tp->rxq_max ||
12552 channel->tx_count > tp->txq_max)
12555 tp->rxq_req = channel->rx_count;
12556 tp->txq_req = channel->tx_count;
12558 if (!netif_running(dev))
12563 tg3_carrier_off(tp);
12565 tg3_start(tp, true, false, false);
12570 static void tg3_get_strings(struct net_device *dev, u32 stringset, u8 *buf)
12572 switch (stringset) {
12574 memcpy(buf, ðtool_stats_keys, sizeof(ethtool_stats_keys));
12577 memcpy(buf, ðtool_test_keys, sizeof(ethtool_test_keys));
12580 WARN_ON(1); /* we need a WARN() */
12585 static int tg3_set_phys_id(struct net_device *dev,
12586 enum ethtool_phys_id_state state)
12588 struct tg3 *tp = netdev_priv(dev);
12590 if (!netif_running(tp->dev))
12594 case ETHTOOL_ID_ACTIVE:
12595 return 1; /* cycle on/off once per second */
12597 case ETHTOOL_ID_ON:
12598 tw32(MAC_LED_CTRL, LED_CTRL_LNKLED_OVERRIDE |
12599 LED_CTRL_1000MBPS_ON |
12600 LED_CTRL_100MBPS_ON |
12601 LED_CTRL_10MBPS_ON |
12602 LED_CTRL_TRAFFIC_OVERRIDE |
12603 LED_CTRL_TRAFFIC_BLINK |
12604 LED_CTRL_TRAFFIC_LED);
12607 case ETHTOOL_ID_OFF:
12608 tw32(MAC_LED_CTRL, LED_CTRL_LNKLED_OVERRIDE |
12609 LED_CTRL_TRAFFIC_OVERRIDE);
12612 case ETHTOOL_ID_INACTIVE:
12613 tw32(MAC_LED_CTRL, tp->led_ctrl);
12620 static void tg3_get_ethtool_stats(struct net_device *dev,
12621 struct ethtool_stats *estats, u64 *tmp_stats)
12623 struct tg3 *tp = netdev_priv(dev);
12626 tg3_get_estats(tp, (struct tg3_ethtool_stats *)tmp_stats);
12628 memset(tmp_stats, 0, sizeof(struct tg3_ethtool_stats));
12631 static __be32 *tg3_vpd_readblock(struct tg3 *tp, u32 *vpdlen)
12635 u32 offset = 0, len = 0;
12638 if (tg3_flag(tp, NO_NVRAM) || tg3_nvram_read(tp, 0, &magic))
12641 if (magic == TG3_EEPROM_MAGIC) {
12642 for (offset = TG3_NVM_DIR_START;
12643 offset < TG3_NVM_DIR_END;
12644 offset += TG3_NVM_DIRENT_SIZE) {
12645 if (tg3_nvram_read(tp, offset, &val))
12648 if ((val >> TG3_NVM_DIRTYPE_SHIFT) ==
12649 TG3_NVM_DIRTYPE_EXTVPD)
12653 if (offset != TG3_NVM_DIR_END) {
12654 len = (val & TG3_NVM_DIRTYPE_LENMSK) * 4;
12655 if (tg3_nvram_read(tp, offset + 4, &offset))
12658 offset = tg3_nvram_logical_addr(tp, offset);
12662 if (!offset || !len) {
12663 offset = TG3_NVM_VPD_OFF;
12664 len = TG3_NVM_VPD_LEN;
12667 buf = kmalloc(len, GFP_KERNEL);
12671 if (magic == TG3_EEPROM_MAGIC) {
12672 for (i = 0; i < len; i += 4) {
12673 /* The data is in little-endian format in NVRAM.
12674 * Use the big-endian read routines to preserve
12675 * the byte order as it exists in NVRAM.
12677 if (tg3_nvram_read_be32(tp, offset + i, &buf[i/4]))
12683 unsigned int pos = 0;
12685 ptr = (u8 *)&buf[0];
12686 for (i = 0; pos < len && i < 3; i++, pos += cnt, ptr += cnt) {
12687 cnt = pci_read_vpd(tp->pdev, pos,
12689 if (cnt == -ETIMEDOUT || cnt == -EINTR)
12707 #define NVRAM_TEST_SIZE 0x100
12708 #define NVRAM_SELFBOOT_FORMAT1_0_SIZE 0x14
12709 #define NVRAM_SELFBOOT_FORMAT1_2_SIZE 0x18
12710 #define NVRAM_SELFBOOT_FORMAT1_3_SIZE 0x1c
12711 #define NVRAM_SELFBOOT_FORMAT1_4_SIZE 0x20
12712 #define NVRAM_SELFBOOT_FORMAT1_5_SIZE 0x24
12713 #define NVRAM_SELFBOOT_FORMAT1_6_SIZE 0x50
12714 #define NVRAM_SELFBOOT_HW_SIZE 0x20
12715 #define NVRAM_SELFBOOT_DATA_SIZE 0x1c
12717 static int tg3_test_nvram(struct tg3 *tp)
12719 u32 csum, magic, len;
12721 int i, j, k, err = 0, size;
12723 if (tg3_flag(tp, NO_NVRAM))
12726 if (tg3_nvram_read(tp, 0, &magic) != 0)
12729 if (magic == TG3_EEPROM_MAGIC)
12730 size = NVRAM_TEST_SIZE;
12731 else if ((magic & TG3_EEPROM_MAGIC_FW_MSK) == TG3_EEPROM_MAGIC_FW) {
12732 if ((magic & TG3_EEPROM_SB_FORMAT_MASK) ==
12733 TG3_EEPROM_SB_FORMAT_1) {
12734 switch (magic & TG3_EEPROM_SB_REVISION_MASK) {
12735 case TG3_EEPROM_SB_REVISION_0:
12736 size = NVRAM_SELFBOOT_FORMAT1_0_SIZE;
12738 case TG3_EEPROM_SB_REVISION_2:
12739 size = NVRAM_SELFBOOT_FORMAT1_2_SIZE;
12741 case TG3_EEPROM_SB_REVISION_3:
12742 size = NVRAM_SELFBOOT_FORMAT1_3_SIZE;
12744 case TG3_EEPROM_SB_REVISION_4:
12745 size = NVRAM_SELFBOOT_FORMAT1_4_SIZE;
12747 case TG3_EEPROM_SB_REVISION_5:
12748 size = NVRAM_SELFBOOT_FORMAT1_5_SIZE;
12750 case TG3_EEPROM_SB_REVISION_6:
12751 size = NVRAM_SELFBOOT_FORMAT1_6_SIZE;
12758 } else if ((magic & TG3_EEPROM_MAGIC_HW_MSK) == TG3_EEPROM_MAGIC_HW)
12759 size = NVRAM_SELFBOOT_HW_SIZE;
12763 buf = kmalloc(size, GFP_KERNEL);
12768 for (i = 0, j = 0; i < size; i += 4, j++) {
12769 err = tg3_nvram_read_be32(tp, i, &buf[j]);
12776 /* Selfboot format */
12777 magic = be32_to_cpu(buf[0]);
12778 if ((magic & TG3_EEPROM_MAGIC_FW_MSK) ==
12779 TG3_EEPROM_MAGIC_FW) {
12780 u8 *buf8 = (u8 *) buf, csum8 = 0;
12782 if ((magic & TG3_EEPROM_SB_REVISION_MASK) ==
12783 TG3_EEPROM_SB_REVISION_2) {
12784 /* For rev 2, the csum doesn't include the MBA. */
12785 for (i = 0; i < TG3_EEPROM_SB_F1R2_MBA_OFF; i++)
12787 for (i = TG3_EEPROM_SB_F1R2_MBA_OFF + 4; i < size; i++)
12790 for (i = 0; i < size; i++)
12803 if ((magic & TG3_EEPROM_MAGIC_HW_MSK) ==
12804 TG3_EEPROM_MAGIC_HW) {
12805 u8 data[NVRAM_SELFBOOT_DATA_SIZE];
12806 u8 parity[NVRAM_SELFBOOT_DATA_SIZE];
12807 u8 *buf8 = (u8 *) buf;
12809 /* Separate the parity bits and the data bytes. */
12810 for (i = 0, j = 0, k = 0; i < NVRAM_SELFBOOT_HW_SIZE; i++) {
12811 if ((i == 0) || (i == 8)) {
12815 for (l = 0, msk = 0x80; l < 7; l++, msk >>= 1)
12816 parity[k++] = buf8[i] & msk;
12818 } else if (i == 16) {
12822 for (l = 0, msk = 0x20; l < 6; l++, msk >>= 1)
12823 parity[k++] = buf8[i] & msk;
12826 for (l = 0, msk = 0x80; l < 8; l++, msk >>= 1)
12827 parity[k++] = buf8[i] & msk;
12830 data[j++] = buf8[i];
12834 for (i = 0; i < NVRAM_SELFBOOT_DATA_SIZE; i++) {
12835 u8 hw8 = hweight8(data[i]);
12837 if ((hw8 & 0x1) && parity[i])
12839 else if (!(hw8 & 0x1) && !parity[i])
12848 /* Bootstrap checksum at offset 0x10 */
12849 csum = calc_crc((unsigned char *) buf, 0x10);
12850 if (csum != le32_to_cpu(buf[0x10/4]))
12853 /* Manufacturing block starts at offset 0x74, checksum at 0xfc */
12854 csum = calc_crc((unsigned char *) &buf[0x74/4], 0x88);
12855 if (csum != le32_to_cpu(buf[0xfc/4]))
12860 buf = tg3_vpd_readblock(tp, &len);
12864 i = pci_vpd_find_tag((u8 *)buf, 0, len, PCI_VPD_LRDT_RO_DATA);
12866 j = pci_vpd_lrdt_size(&((u8 *)buf)[i]);
12870 if (i + PCI_VPD_LRDT_TAG_SIZE + j > len)
12873 i += PCI_VPD_LRDT_TAG_SIZE;
12874 j = pci_vpd_find_info_keyword((u8 *)buf, i, j,
12875 PCI_VPD_RO_KEYWORD_CHKSUM);
12879 j += PCI_VPD_INFO_FLD_HDR_SIZE;
12881 for (i = 0; i <= j; i++)
12882 csum8 += ((u8 *)buf)[i];
12896 #define TG3_SERDES_TIMEOUT_SEC 2
12897 #define TG3_COPPER_TIMEOUT_SEC 6
12899 static int tg3_test_link(struct tg3 *tp)
12903 if (!netif_running(tp->dev))
12906 if (tp->phy_flags & TG3_PHYFLG_ANY_SERDES)
12907 max = TG3_SERDES_TIMEOUT_SEC;
12909 max = TG3_COPPER_TIMEOUT_SEC;
12911 for (i = 0; i < max; i++) {
12915 if (msleep_interruptible(1000))
12922 /* Only test the commonly used registers */
12923 static int tg3_test_registers(struct tg3 *tp)
12925 int i, is_5705, is_5750;
12926 u32 offset, read_mask, write_mask, val, save_val, read_val;
12930 #define TG3_FL_5705 0x1
12931 #define TG3_FL_NOT_5705 0x2
12932 #define TG3_FL_NOT_5788 0x4
12933 #define TG3_FL_NOT_5750 0x8
12937 /* MAC Control Registers */
12938 { MAC_MODE, TG3_FL_NOT_5705,
12939 0x00000000, 0x00ef6f8c },
12940 { MAC_MODE, TG3_FL_5705,
12941 0x00000000, 0x01ef6b8c },
12942 { MAC_STATUS, TG3_FL_NOT_5705,
12943 0x03800107, 0x00000000 },
12944 { MAC_STATUS, TG3_FL_5705,
12945 0x03800100, 0x00000000 },
12946 { MAC_ADDR_0_HIGH, 0x0000,
12947 0x00000000, 0x0000ffff },
12948 { MAC_ADDR_0_LOW, 0x0000,
12949 0x00000000, 0xffffffff },
12950 { MAC_RX_MTU_SIZE, 0x0000,
12951 0x00000000, 0x0000ffff },
12952 { MAC_TX_MODE, 0x0000,
12953 0x00000000, 0x00000070 },
12954 { MAC_TX_LENGTHS, 0x0000,
12955 0x00000000, 0x00003fff },
12956 { MAC_RX_MODE, TG3_FL_NOT_5705,
12957 0x00000000, 0x000007fc },
12958 { MAC_RX_MODE, TG3_FL_5705,
12959 0x00000000, 0x000007dc },
12960 { MAC_HASH_REG_0, 0x0000,
12961 0x00000000, 0xffffffff },
12962 { MAC_HASH_REG_1, 0x0000,
12963 0x00000000, 0xffffffff },
12964 { MAC_HASH_REG_2, 0x0000,
12965 0x00000000, 0xffffffff },
12966 { MAC_HASH_REG_3, 0x0000,
12967 0x00000000, 0xffffffff },
12969 /* Receive Data and Receive BD Initiator Control Registers. */
12970 { RCVDBDI_JUMBO_BD+0, TG3_FL_NOT_5705,
12971 0x00000000, 0xffffffff },
12972 { RCVDBDI_JUMBO_BD+4, TG3_FL_NOT_5705,
12973 0x00000000, 0xffffffff },
12974 { RCVDBDI_JUMBO_BD+8, TG3_FL_NOT_5705,
12975 0x00000000, 0x00000003 },
12976 { RCVDBDI_JUMBO_BD+0xc, TG3_FL_NOT_5705,
12977 0x00000000, 0xffffffff },
12978 { RCVDBDI_STD_BD+0, 0x0000,
12979 0x00000000, 0xffffffff },
12980 { RCVDBDI_STD_BD+4, 0x0000,
12981 0x00000000, 0xffffffff },
12982 { RCVDBDI_STD_BD+8, 0x0000,
12983 0x00000000, 0xffff0002 },
12984 { RCVDBDI_STD_BD+0xc, 0x0000,
12985 0x00000000, 0xffffffff },
12987 /* Receive BD Initiator Control Registers. */
12988 { RCVBDI_STD_THRESH, TG3_FL_NOT_5705,
12989 0x00000000, 0xffffffff },
12990 { RCVBDI_STD_THRESH, TG3_FL_5705,
12991 0x00000000, 0x000003ff },
12992 { RCVBDI_JUMBO_THRESH, TG3_FL_NOT_5705,
12993 0x00000000, 0xffffffff },
12995 /* Host Coalescing Control Registers. */
12996 { HOSTCC_MODE, TG3_FL_NOT_5705,
12997 0x00000000, 0x00000004 },
12998 { HOSTCC_MODE, TG3_FL_5705,
12999 0x00000000, 0x000000f6 },
13000 { HOSTCC_RXCOL_TICKS, TG3_FL_NOT_5705,
13001 0x00000000, 0xffffffff },
13002 { HOSTCC_RXCOL_TICKS, TG3_FL_5705,
13003 0x00000000, 0x000003ff },
13004 { HOSTCC_TXCOL_TICKS, TG3_FL_NOT_5705,
13005 0x00000000, 0xffffffff },
13006 { HOSTCC_TXCOL_TICKS, TG3_FL_5705,
13007 0x00000000, 0x000003ff },
13008 { HOSTCC_RXMAX_FRAMES, TG3_FL_NOT_5705,
13009 0x00000000, 0xffffffff },
13010 { HOSTCC_RXMAX_FRAMES, TG3_FL_5705 | TG3_FL_NOT_5788,
13011 0x00000000, 0x000000ff },
13012 { HOSTCC_TXMAX_FRAMES, TG3_FL_NOT_5705,
13013 0x00000000, 0xffffffff },
13014 { HOSTCC_TXMAX_FRAMES, TG3_FL_5705 | TG3_FL_NOT_5788,
13015 0x00000000, 0x000000ff },
13016 { HOSTCC_RXCOAL_TICK_INT, TG3_FL_NOT_5705,
13017 0x00000000, 0xffffffff },
13018 { HOSTCC_TXCOAL_TICK_INT, TG3_FL_NOT_5705,
13019 0x00000000, 0xffffffff },
13020 { HOSTCC_RXCOAL_MAXF_INT, TG3_FL_NOT_5705,
13021 0x00000000, 0xffffffff },
13022 { HOSTCC_RXCOAL_MAXF_INT, TG3_FL_5705 | TG3_FL_NOT_5788,
13023 0x00000000, 0x000000ff },
13024 { HOSTCC_TXCOAL_MAXF_INT, TG3_FL_NOT_5705,
13025 0x00000000, 0xffffffff },
13026 { HOSTCC_TXCOAL_MAXF_INT, TG3_FL_5705 | TG3_FL_NOT_5788,
13027 0x00000000, 0x000000ff },
13028 { HOSTCC_STAT_COAL_TICKS, TG3_FL_NOT_5705,
13029 0x00000000, 0xffffffff },
13030 { HOSTCC_STATS_BLK_HOST_ADDR, TG3_FL_NOT_5705,
13031 0x00000000, 0xffffffff },
13032 { HOSTCC_STATS_BLK_HOST_ADDR+4, TG3_FL_NOT_5705,
13033 0x00000000, 0xffffffff },
13034 { HOSTCC_STATUS_BLK_HOST_ADDR, 0x0000,
13035 0x00000000, 0xffffffff },
13036 { HOSTCC_STATUS_BLK_HOST_ADDR+4, 0x0000,
13037 0x00000000, 0xffffffff },
13038 { HOSTCC_STATS_BLK_NIC_ADDR, 0x0000,
13039 0xffffffff, 0x00000000 },
13040 { HOSTCC_STATUS_BLK_NIC_ADDR, 0x0000,
13041 0xffffffff, 0x00000000 },
13043 /* Buffer Manager Control Registers. */
13044 { BUFMGR_MB_POOL_ADDR, TG3_FL_NOT_5750,
13045 0x00000000, 0x007fff80 },
13046 { BUFMGR_MB_POOL_SIZE, TG3_FL_NOT_5750,
13047 0x00000000, 0x007fffff },
13048 { BUFMGR_MB_RDMA_LOW_WATER, 0x0000,
13049 0x00000000, 0x0000003f },
13050 { BUFMGR_MB_MACRX_LOW_WATER, 0x0000,
13051 0x00000000, 0x000001ff },
13052 { BUFMGR_MB_HIGH_WATER, 0x0000,
13053 0x00000000, 0x000001ff },
13054 { BUFMGR_DMA_DESC_POOL_ADDR, TG3_FL_NOT_5705,
13055 0xffffffff, 0x00000000 },
13056 { BUFMGR_DMA_DESC_POOL_SIZE, TG3_FL_NOT_5705,
13057 0xffffffff, 0x00000000 },
13059 /* Mailbox Registers */
13060 { GRCMBOX_RCVSTD_PROD_IDX+4, 0x0000,
13061 0x00000000, 0x000001ff },
13062 { GRCMBOX_RCVJUMBO_PROD_IDX+4, TG3_FL_NOT_5705,
13063 0x00000000, 0x000001ff },
13064 { GRCMBOX_RCVRET_CON_IDX_0+4, 0x0000,
13065 0x00000000, 0x000007ff },
13066 { GRCMBOX_SNDHOST_PROD_IDX_0+4, 0x0000,
13067 0x00000000, 0x000001ff },
13069 { 0xffff, 0x0000, 0x00000000, 0x00000000 },
13072 is_5705 = is_5750 = 0;
13073 if (tg3_flag(tp, 5705_PLUS)) {
13075 if (tg3_flag(tp, 5750_PLUS))
13079 for (i = 0; reg_tbl[i].offset != 0xffff; i++) {
13080 if (is_5705 && (reg_tbl[i].flags & TG3_FL_NOT_5705))
13083 if (!is_5705 && (reg_tbl[i].flags & TG3_FL_5705))
13086 if (tg3_flag(tp, IS_5788) &&
13087 (reg_tbl[i].flags & TG3_FL_NOT_5788))
13090 if (is_5750 && (reg_tbl[i].flags & TG3_FL_NOT_5750))
13093 offset = (u32) reg_tbl[i].offset;
13094 read_mask = reg_tbl[i].read_mask;
13095 write_mask = reg_tbl[i].write_mask;
13097 /* Save the original register content */
13098 save_val = tr32(offset);
13100 /* Determine the read-only value. */
13101 read_val = save_val & read_mask;
13103 /* Write zero to the register, then make sure the read-only bits
13104 * are not changed and the read/write bits are all zeros.
13108 val = tr32(offset);
13110 /* Test the read-only and read/write bits. */
13111 if (((val & read_mask) != read_val) || (val & write_mask))
13114 /* Write ones to all the bits defined by RdMask and WrMask, then
13115 * make sure the read-only bits are not changed and the
13116 * read/write bits are all ones.
13118 tw32(offset, read_mask | write_mask);
13120 val = tr32(offset);
13122 /* Test the read-only bits. */
13123 if ((val & read_mask) != read_val)
13126 /* Test the read/write bits. */
13127 if ((val & write_mask) != write_mask)
13130 tw32(offset, save_val);
13136 if (netif_msg_hw(tp))
13137 netdev_err(tp->dev,
13138 "Register test failed at offset %x\n", offset);
13139 tw32(offset, save_val);
13143 static int tg3_do_mem_test(struct tg3 *tp, u32 offset, u32 len)
13145 static const u32 test_pattern[] = { 0x00000000, 0xffffffff, 0xaa55a55a };
13149 for (i = 0; i < ARRAY_SIZE(test_pattern); i++) {
13150 for (j = 0; j < len; j += 4) {
13153 tg3_write_mem(tp, offset + j, test_pattern[i]);
13154 tg3_read_mem(tp, offset + j, &val);
13155 if (val != test_pattern[i])
13162 static int tg3_test_memory(struct tg3 *tp)
13164 static struct mem_entry {
13167 } mem_tbl_570x[] = {
13168 { 0x00000000, 0x00b50},
13169 { 0x00002000, 0x1c000},
13170 { 0xffffffff, 0x00000}
13171 }, mem_tbl_5705[] = {
13172 { 0x00000100, 0x0000c},
13173 { 0x00000200, 0x00008},
13174 { 0x00004000, 0x00800},
13175 { 0x00006000, 0x01000},
13176 { 0x00008000, 0x02000},
13177 { 0x00010000, 0x0e000},
13178 { 0xffffffff, 0x00000}
13179 }, mem_tbl_5755[] = {
13180 { 0x00000200, 0x00008},
13181 { 0x00004000, 0x00800},
13182 { 0x00006000, 0x00800},
13183 { 0x00008000, 0x02000},
13184 { 0x00010000, 0x0c000},
13185 { 0xffffffff, 0x00000}
13186 }, mem_tbl_5906[] = {
13187 { 0x00000200, 0x00008},
13188 { 0x00004000, 0x00400},
13189 { 0x00006000, 0x00400},
13190 { 0x00008000, 0x01000},
13191 { 0x00010000, 0x01000},
13192 { 0xffffffff, 0x00000}
13193 }, mem_tbl_5717[] = {
13194 { 0x00000200, 0x00008},
13195 { 0x00010000, 0x0a000},
13196 { 0x00020000, 0x13c00},
13197 { 0xffffffff, 0x00000}
13198 }, mem_tbl_57765[] = {
13199 { 0x00000200, 0x00008},
13200 { 0x00004000, 0x00800},
13201 { 0x00006000, 0x09800},
13202 { 0x00010000, 0x0a000},
13203 { 0xffffffff, 0x00000}
13205 struct mem_entry *mem_tbl;
13209 if (tg3_flag(tp, 5717_PLUS))
13210 mem_tbl = mem_tbl_5717;
13211 else if (tg3_flag(tp, 57765_CLASS) ||
13212 tg3_asic_rev(tp) == ASIC_REV_5762)
13213 mem_tbl = mem_tbl_57765;
13214 else if (tg3_flag(tp, 5755_PLUS))
13215 mem_tbl = mem_tbl_5755;
13216 else if (tg3_asic_rev(tp) == ASIC_REV_5906)
13217 mem_tbl = mem_tbl_5906;
13218 else if (tg3_flag(tp, 5705_PLUS))
13219 mem_tbl = mem_tbl_5705;
13221 mem_tbl = mem_tbl_570x;
13223 for (i = 0; mem_tbl[i].offset != 0xffffffff; i++) {
13224 err = tg3_do_mem_test(tp, mem_tbl[i].offset, mem_tbl[i].len);
13232 #define TG3_TSO_MSS 500
13234 #define TG3_TSO_IP_HDR_LEN 20
13235 #define TG3_TSO_TCP_HDR_LEN 20
13236 #define TG3_TSO_TCP_OPT_LEN 12
13238 static const u8 tg3_tso_header[] = {
13240 0x45, 0x00, 0x00, 0x00,
13241 0x00, 0x00, 0x40, 0x00,
13242 0x40, 0x06, 0x00, 0x00,
13243 0x0a, 0x00, 0x00, 0x01,
13244 0x0a, 0x00, 0x00, 0x02,
13245 0x0d, 0x00, 0xe0, 0x00,
13246 0x00, 0x00, 0x01, 0x00,
13247 0x00, 0x00, 0x02, 0x00,
13248 0x80, 0x10, 0x10, 0x00,
13249 0x14, 0x09, 0x00, 0x00,
13250 0x01, 0x01, 0x08, 0x0a,
13251 0x11, 0x11, 0x11, 0x11,
13252 0x11, 0x11, 0x11, 0x11,
13255 static int tg3_run_loopback(struct tg3 *tp, u32 pktsz, bool tso_loopback)
13257 u32 rx_start_idx, rx_idx, tx_idx, opaque_key;
13258 u32 base_flags = 0, mss = 0, desc_idx, coal_now, data_off, val;
13260 struct sk_buff *skb;
13261 u8 *tx_data, *rx_data;
13263 int num_pkts, tx_len, rx_len, i, err;
13264 struct tg3_rx_buffer_desc *desc;
13265 struct tg3_napi *tnapi, *rnapi;
13266 struct tg3_rx_prodring_set *tpr = &tp->napi[0].prodring;
13268 tnapi = &tp->napi[0];
13269 rnapi = &tp->napi[0];
13270 if (tp->irq_cnt > 1) {
13271 if (tg3_flag(tp, ENABLE_RSS))
13272 rnapi = &tp->napi[1];
13273 if (tg3_flag(tp, ENABLE_TSS))
13274 tnapi = &tp->napi[1];
13276 coal_now = tnapi->coal_now | rnapi->coal_now;
13281 skb = netdev_alloc_skb(tp->dev, tx_len);
13285 tx_data = skb_put(skb, tx_len);
13286 memcpy(tx_data, tp->dev->dev_addr, ETH_ALEN);
13287 memset(tx_data + ETH_ALEN, 0x0, 8);
13289 tw32(MAC_RX_MTU_SIZE, tx_len + ETH_FCS_LEN);
13291 if (tso_loopback) {
13292 struct iphdr *iph = (struct iphdr *)&tx_data[ETH_HLEN];
13294 u32 hdr_len = TG3_TSO_IP_HDR_LEN + TG3_TSO_TCP_HDR_LEN +
13295 TG3_TSO_TCP_OPT_LEN;
13297 memcpy(tx_data + ETH_ALEN * 2, tg3_tso_header,
13298 sizeof(tg3_tso_header));
13301 val = tx_len - ETH_ALEN * 2 - sizeof(tg3_tso_header);
13302 num_pkts = DIV_ROUND_UP(val, TG3_TSO_MSS);
13304 /* Set the total length field in the IP header */
13305 iph->tot_len = htons((u16)(mss + hdr_len));
13307 base_flags = (TXD_FLAG_CPU_PRE_DMA |
13308 TXD_FLAG_CPU_POST_DMA);
13310 if (tg3_flag(tp, HW_TSO_1) ||
13311 tg3_flag(tp, HW_TSO_2) ||
13312 tg3_flag(tp, HW_TSO_3)) {
13314 val = ETH_HLEN + TG3_TSO_IP_HDR_LEN;
13315 th = (struct tcphdr *)&tx_data[val];
13318 base_flags |= TXD_FLAG_TCPUDP_CSUM;
13320 if (tg3_flag(tp, HW_TSO_3)) {
13321 mss |= (hdr_len & 0xc) << 12;
13322 if (hdr_len & 0x10)
13323 base_flags |= 0x00000010;
13324 base_flags |= (hdr_len & 0x3e0) << 5;
13325 } else if (tg3_flag(tp, HW_TSO_2))
13326 mss |= hdr_len << 9;
13327 else if (tg3_flag(tp, HW_TSO_1) ||
13328 tg3_asic_rev(tp) == ASIC_REV_5705) {
13329 mss |= (TG3_TSO_TCP_OPT_LEN << 9);
13331 base_flags |= (TG3_TSO_TCP_OPT_LEN << 10);
13334 data_off = ETH_ALEN * 2 + sizeof(tg3_tso_header);
13337 data_off = ETH_HLEN;
13339 if (tg3_flag(tp, USE_JUMBO_BDFLAG) &&
13340 tx_len > VLAN_ETH_FRAME_LEN)
13341 base_flags |= TXD_FLAG_JMB_PKT;
13344 for (i = data_off; i < tx_len; i++)
13345 tx_data[i] = (u8) (i & 0xff);
13347 map = pci_map_single(tp->pdev, skb->data, tx_len, PCI_DMA_TODEVICE);
13348 if (pci_dma_mapping_error(tp->pdev, map)) {
13349 dev_kfree_skb(skb);
13353 val = tnapi->tx_prod;
13354 tnapi->tx_buffers[val].skb = skb;
13355 dma_unmap_addr_set(&tnapi->tx_buffers[val], mapping, map);
13357 tw32_f(HOSTCC_MODE, tp->coalesce_mode | HOSTCC_MODE_ENABLE |
13362 rx_start_idx = rnapi->hw_status->idx[0].rx_producer;
13364 budget = tg3_tx_avail(tnapi);
13365 if (tg3_tx_frag_set(tnapi, &val, &budget, map, tx_len,
13366 base_flags | TXD_FLAG_END, mss, 0)) {
13367 tnapi->tx_buffers[val].skb = NULL;
13368 dev_kfree_skb(skb);
13374 /* Sync BD data before updating mailbox */
13377 tw32_tx_mbox(tnapi->prodmbox, tnapi->tx_prod);
13378 tr32_mailbox(tnapi->prodmbox);
13382 /* 350 usec to allow enough time on some 10/100 Mbps devices. */
13383 for (i = 0; i < 35; i++) {
13384 tw32_f(HOSTCC_MODE, tp->coalesce_mode | HOSTCC_MODE_ENABLE |
13389 tx_idx = tnapi->hw_status->idx[0].tx_consumer;
13390 rx_idx = rnapi->hw_status->idx[0].rx_producer;
13391 if ((tx_idx == tnapi->tx_prod) &&
13392 (rx_idx == (rx_start_idx + num_pkts)))
13396 tg3_tx_skb_unmap(tnapi, tnapi->tx_prod - 1, -1);
13397 dev_kfree_skb(skb);
13399 if (tx_idx != tnapi->tx_prod)
13402 if (rx_idx != rx_start_idx + num_pkts)
13406 while (rx_idx != rx_start_idx) {
13407 desc = &rnapi->rx_rcb[rx_start_idx++];
13408 desc_idx = desc->opaque & RXD_OPAQUE_INDEX_MASK;
13409 opaque_key = desc->opaque & RXD_OPAQUE_RING_MASK;
13411 if ((desc->err_vlan & RXD_ERR_MASK) != 0 &&
13412 (desc->err_vlan != RXD_ERR_ODD_NIBBLE_RCVD_MII))
13415 rx_len = ((desc->idx_len & RXD_LEN_MASK) >> RXD_LEN_SHIFT)
13418 if (!tso_loopback) {
13419 if (rx_len != tx_len)
13422 if (pktsz <= TG3_RX_STD_DMA_SZ - ETH_FCS_LEN) {
13423 if (opaque_key != RXD_OPAQUE_RING_STD)
13426 if (opaque_key != RXD_OPAQUE_RING_JUMBO)
13429 } else if ((desc->type_flags & RXD_FLAG_TCPUDP_CSUM) &&
13430 (desc->ip_tcp_csum & RXD_TCPCSUM_MASK)
13431 >> RXD_TCPCSUM_SHIFT != 0xffff) {
13435 if (opaque_key == RXD_OPAQUE_RING_STD) {
13436 rx_data = tpr->rx_std_buffers[desc_idx].data;
13437 map = dma_unmap_addr(&tpr->rx_std_buffers[desc_idx],
13439 } else if (opaque_key == RXD_OPAQUE_RING_JUMBO) {
13440 rx_data = tpr->rx_jmb_buffers[desc_idx].data;
13441 map = dma_unmap_addr(&tpr->rx_jmb_buffers[desc_idx],
13446 pci_dma_sync_single_for_cpu(tp->pdev, map, rx_len,
13447 PCI_DMA_FROMDEVICE);
13449 rx_data += TG3_RX_OFFSET(tp);
13450 for (i = data_off; i < rx_len; i++, val++) {
13451 if (*(rx_data + i) != (u8) (val & 0xff))
13458 /* tg3_free_rings will unmap and free the rx_data */
13463 #define TG3_STD_LOOPBACK_FAILED 1
13464 #define TG3_JMB_LOOPBACK_FAILED 2
13465 #define TG3_TSO_LOOPBACK_FAILED 4
13466 #define TG3_LOOPBACK_FAILED \
13467 (TG3_STD_LOOPBACK_FAILED | \
13468 TG3_JMB_LOOPBACK_FAILED | \
13469 TG3_TSO_LOOPBACK_FAILED)
13471 static int tg3_test_loopback(struct tg3 *tp, u64 *data, bool do_extlpbk)
13475 u32 jmb_pkt_sz = 9000;
13478 jmb_pkt_sz = tp->dma_limit - ETH_HLEN;
13480 eee_cap = tp->phy_flags & TG3_PHYFLG_EEE_CAP;
13481 tp->phy_flags &= ~TG3_PHYFLG_EEE_CAP;
13483 if (!netif_running(tp->dev)) {
13484 data[TG3_MAC_LOOPB_TEST] = TG3_LOOPBACK_FAILED;
13485 data[TG3_PHY_LOOPB_TEST] = TG3_LOOPBACK_FAILED;
13487 data[TG3_EXT_LOOPB_TEST] = TG3_LOOPBACK_FAILED;
13491 err = tg3_reset_hw(tp, true);
13493 data[TG3_MAC_LOOPB_TEST] = TG3_LOOPBACK_FAILED;
13494 data[TG3_PHY_LOOPB_TEST] = TG3_LOOPBACK_FAILED;
13496 data[TG3_EXT_LOOPB_TEST] = TG3_LOOPBACK_FAILED;
13500 if (tg3_flag(tp, ENABLE_RSS)) {
13503 /* Reroute all rx packets to the 1st queue */
13504 for (i = MAC_RSS_INDIR_TBL_0;
13505 i < MAC_RSS_INDIR_TBL_0 + TG3_RSS_INDIR_TBL_SIZE; i += 4)
13509 /* HW errata - mac loopback fails in some cases on 5780.
13510 * Normal traffic and PHY loopback are not affected by
13511 * errata. Also, the MAC loopback test is deprecated for
13512 * all newer ASIC revisions.
13514 if (tg3_asic_rev(tp) != ASIC_REV_5780 &&
13515 !tg3_flag(tp, CPMU_PRESENT)) {
13516 tg3_mac_loopback(tp, true);
13518 if (tg3_run_loopback(tp, ETH_FRAME_LEN, false))
13519 data[TG3_MAC_LOOPB_TEST] |= TG3_STD_LOOPBACK_FAILED;
13521 if (tg3_flag(tp, JUMBO_RING_ENABLE) &&
13522 tg3_run_loopback(tp, jmb_pkt_sz + ETH_HLEN, false))
13523 data[TG3_MAC_LOOPB_TEST] |= TG3_JMB_LOOPBACK_FAILED;
13525 tg3_mac_loopback(tp, false);
13528 if (!(tp->phy_flags & TG3_PHYFLG_PHY_SERDES) &&
13529 !tg3_flag(tp, USE_PHYLIB)) {
13532 tg3_phy_lpbk_set(tp, 0, false);
13534 /* Wait for link */
13535 for (i = 0; i < 100; i++) {
13536 if (tr32(MAC_TX_STATUS) & TX_STATUS_LINK_UP)
13541 if (tg3_run_loopback(tp, ETH_FRAME_LEN, false))
13542 data[TG3_PHY_LOOPB_TEST] |= TG3_STD_LOOPBACK_FAILED;
13543 if (tg3_flag(tp, TSO_CAPABLE) &&
13544 tg3_run_loopback(tp, ETH_FRAME_LEN, true))
13545 data[TG3_PHY_LOOPB_TEST] |= TG3_TSO_LOOPBACK_FAILED;
13546 if (tg3_flag(tp, JUMBO_RING_ENABLE) &&
13547 tg3_run_loopback(tp, jmb_pkt_sz + ETH_HLEN, false))
13548 data[TG3_PHY_LOOPB_TEST] |= TG3_JMB_LOOPBACK_FAILED;
13551 tg3_phy_lpbk_set(tp, 0, true);
13553 /* All link indications report up, but the hardware
13554 * isn't really ready for about 20 msec. Double it
13559 if (tg3_run_loopback(tp, ETH_FRAME_LEN, false))
13560 data[TG3_EXT_LOOPB_TEST] |=
13561 TG3_STD_LOOPBACK_FAILED;
13562 if (tg3_flag(tp, TSO_CAPABLE) &&
13563 tg3_run_loopback(tp, ETH_FRAME_LEN, true))
13564 data[TG3_EXT_LOOPB_TEST] |=
13565 TG3_TSO_LOOPBACK_FAILED;
13566 if (tg3_flag(tp, JUMBO_RING_ENABLE) &&
13567 tg3_run_loopback(tp, jmb_pkt_sz + ETH_HLEN, false))
13568 data[TG3_EXT_LOOPB_TEST] |=
13569 TG3_JMB_LOOPBACK_FAILED;
13572 /* Re-enable gphy autopowerdown. */
13573 if (tp->phy_flags & TG3_PHYFLG_ENABLE_APD)
13574 tg3_phy_toggle_apd(tp, true);
13577 err = (data[TG3_MAC_LOOPB_TEST] | data[TG3_PHY_LOOPB_TEST] |
13578 data[TG3_EXT_LOOPB_TEST]) ? -EIO : 0;
13581 tp->phy_flags |= eee_cap;
13586 static void tg3_self_test(struct net_device *dev, struct ethtool_test *etest,
13589 struct tg3 *tp = netdev_priv(dev);
13590 bool doextlpbk = etest->flags & ETH_TEST_FL_EXTERNAL_LB;
13592 if (tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER) {
13593 if (tg3_power_up(tp)) {
13594 etest->flags |= ETH_TEST_FL_FAILED;
13595 memset(data, 1, sizeof(u64) * TG3_NUM_TEST);
13598 tg3_ape_driver_state_change(tp, RESET_KIND_INIT);
13601 memset(data, 0, sizeof(u64) * TG3_NUM_TEST);
13603 if (tg3_test_nvram(tp) != 0) {
13604 etest->flags |= ETH_TEST_FL_FAILED;
13605 data[TG3_NVRAM_TEST] = 1;
13607 if (!doextlpbk && tg3_test_link(tp)) {
13608 etest->flags |= ETH_TEST_FL_FAILED;
13609 data[TG3_LINK_TEST] = 1;
13611 if (etest->flags & ETH_TEST_FL_OFFLINE) {
13612 int err, err2 = 0, irq_sync = 0;
13614 if (netif_running(dev)) {
13616 tg3_netif_stop(tp);
13620 tg3_full_lock(tp, irq_sync);
13621 tg3_halt(tp, RESET_KIND_SUSPEND, 1);
13622 err = tg3_nvram_lock(tp);
13623 tg3_halt_cpu(tp, RX_CPU_BASE);
13624 if (!tg3_flag(tp, 5705_PLUS))
13625 tg3_halt_cpu(tp, TX_CPU_BASE);
13627 tg3_nvram_unlock(tp);
13629 if (tp->phy_flags & TG3_PHYFLG_MII_SERDES)
13632 if (tg3_test_registers(tp) != 0) {
13633 etest->flags |= ETH_TEST_FL_FAILED;
13634 data[TG3_REGISTER_TEST] = 1;
13637 if (tg3_test_memory(tp) != 0) {
13638 etest->flags |= ETH_TEST_FL_FAILED;
13639 data[TG3_MEMORY_TEST] = 1;
13643 etest->flags |= ETH_TEST_FL_EXTERNAL_LB_DONE;
13645 if (tg3_test_loopback(tp, data, doextlpbk))
13646 etest->flags |= ETH_TEST_FL_FAILED;
13648 tg3_full_unlock(tp);
13650 if (tg3_test_interrupt(tp) != 0) {
13651 etest->flags |= ETH_TEST_FL_FAILED;
13652 data[TG3_INTERRUPT_TEST] = 1;
13655 tg3_full_lock(tp, 0);
13657 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
13658 if (netif_running(dev)) {
13659 tg3_flag_set(tp, INIT_COMPLETE);
13660 err2 = tg3_restart_hw(tp, true);
13662 tg3_netif_start(tp);
13665 tg3_full_unlock(tp);
13667 if (irq_sync && !err2)
13670 if (tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER)
13671 tg3_power_down_prepare(tp);
13675 static int tg3_hwtstamp_set(struct net_device *dev, struct ifreq *ifr)
13677 struct tg3 *tp = netdev_priv(dev);
13678 struct hwtstamp_config stmpconf;
13680 if (!tg3_flag(tp, PTP_CAPABLE))
13681 return -EOPNOTSUPP;
13683 if (copy_from_user(&stmpconf, ifr->ifr_data, sizeof(stmpconf)))
13686 if (stmpconf.flags)
13689 if (stmpconf.tx_type != HWTSTAMP_TX_ON &&
13690 stmpconf.tx_type != HWTSTAMP_TX_OFF)
13693 switch (stmpconf.rx_filter) {
13694 case HWTSTAMP_FILTER_NONE:
13697 case HWTSTAMP_FILTER_PTP_V1_L4_EVENT:
13698 tp->rxptpctl = TG3_RX_PTP_CTL_RX_PTP_V1_EN |
13699 TG3_RX_PTP_CTL_ALL_V1_EVENTS;
13701 case HWTSTAMP_FILTER_PTP_V1_L4_SYNC:
13702 tp->rxptpctl = TG3_RX_PTP_CTL_RX_PTP_V1_EN |
13703 TG3_RX_PTP_CTL_SYNC_EVNT;
13705 case HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ:
13706 tp->rxptpctl = TG3_RX_PTP_CTL_RX_PTP_V1_EN |
13707 TG3_RX_PTP_CTL_DELAY_REQ;
13709 case HWTSTAMP_FILTER_PTP_V2_EVENT:
13710 tp->rxptpctl = TG3_RX_PTP_CTL_RX_PTP_V2_EN |
13711 TG3_RX_PTP_CTL_ALL_V2_EVENTS;
13713 case HWTSTAMP_FILTER_PTP_V2_L2_EVENT:
13714 tp->rxptpctl = TG3_RX_PTP_CTL_RX_PTP_V2_L2_EN |
13715 TG3_RX_PTP_CTL_ALL_V2_EVENTS;
13717 case HWTSTAMP_FILTER_PTP_V2_L4_EVENT:
13718 tp->rxptpctl = TG3_RX_PTP_CTL_RX_PTP_V2_L4_EN |
13719 TG3_RX_PTP_CTL_ALL_V2_EVENTS;
13721 case HWTSTAMP_FILTER_PTP_V2_SYNC:
13722 tp->rxptpctl = TG3_RX_PTP_CTL_RX_PTP_V2_EN |
13723 TG3_RX_PTP_CTL_SYNC_EVNT;
13725 case HWTSTAMP_FILTER_PTP_V2_L2_SYNC:
13726 tp->rxptpctl = TG3_RX_PTP_CTL_RX_PTP_V2_L2_EN |
13727 TG3_RX_PTP_CTL_SYNC_EVNT;
13729 case HWTSTAMP_FILTER_PTP_V2_L4_SYNC:
13730 tp->rxptpctl = TG3_RX_PTP_CTL_RX_PTP_V2_L4_EN |
13731 TG3_RX_PTP_CTL_SYNC_EVNT;
13733 case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ:
13734 tp->rxptpctl = TG3_RX_PTP_CTL_RX_PTP_V2_EN |
13735 TG3_RX_PTP_CTL_DELAY_REQ;
13737 case HWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ:
13738 tp->rxptpctl = TG3_RX_PTP_CTL_RX_PTP_V2_L2_EN |
13739 TG3_RX_PTP_CTL_DELAY_REQ;
13741 case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ:
13742 tp->rxptpctl = TG3_RX_PTP_CTL_RX_PTP_V2_L4_EN |
13743 TG3_RX_PTP_CTL_DELAY_REQ;
13749 if (netif_running(dev) && tp->rxptpctl)
13750 tw32(TG3_RX_PTP_CTL,
13751 tp->rxptpctl | TG3_RX_PTP_CTL_HWTS_INTERLOCK);
13753 if (stmpconf.tx_type == HWTSTAMP_TX_ON)
13754 tg3_flag_set(tp, TX_TSTAMP_EN);
13756 tg3_flag_clear(tp, TX_TSTAMP_EN);
13758 return copy_to_user(ifr->ifr_data, &stmpconf, sizeof(stmpconf)) ?
13762 static int tg3_hwtstamp_get(struct net_device *dev, struct ifreq *ifr)
13764 struct tg3 *tp = netdev_priv(dev);
13765 struct hwtstamp_config stmpconf;
13767 if (!tg3_flag(tp, PTP_CAPABLE))
13768 return -EOPNOTSUPP;
13770 stmpconf.flags = 0;
13771 stmpconf.tx_type = (tg3_flag(tp, TX_TSTAMP_EN) ?
13772 HWTSTAMP_TX_ON : HWTSTAMP_TX_OFF);
13774 switch (tp->rxptpctl) {
13776 stmpconf.rx_filter = HWTSTAMP_FILTER_NONE;
13778 case TG3_RX_PTP_CTL_RX_PTP_V1_EN | TG3_RX_PTP_CTL_ALL_V1_EVENTS:
13779 stmpconf.rx_filter = HWTSTAMP_FILTER_PTP_V1_L4_EVENT;
13781 case TG3_RX_PTP_CTL_RX_PTP_V1_EN | TG3_RX_PTP_CTL_SYNC_EVNT:
13782 stmpconf.rx_filter = HWTSTAMP_FILTER_PTP_V1_L4_SYNC;
13784 case TG3_RX_PTP_CTL_RX_PTP_V1_EN | TG3_RX_PTP_CTL_DELAY_REQ:
13785 stmpconf.rx_filter = HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ;
13787 case TG3_RX_PTP_CTL_RX_PTP_V2_EN | TG3_RX_PTP_CTL_ALL_V2_EVENTS:
13788 stmpconf.rx_filter = HWTSTAMP_FILTER_PTP_V2_EVENT;
13790 case TG3_RX_PTP_CTL_RX_PTP_V2_L2_EN | TG3_RX_PTP_CTL_ALL_V2_EVENTS:
13791 stmpconf.rx_filter = HWTSTAMP_FILTER_PTP_V2_L2_EVENT;
13793 case TG3_RX_PTP_CTL_RX_PTP_V2_L4_EN | TG3_RX_PTP_CTL_ALL_V2_EVENTS:
13794 stmpconf.rx_filter = HWTSTAMP_FILTER_PTP_V2_L4_EVENT;
13796 case TG3_RX_PTP_CTL_RX_PTP_V2_EN | TG3_RX_PTP_CTL_SYNC_EVNT:
13797 stmpconf.rx_filter = HWTSTAMP_FILTER_PTP_V2_SYNC;
13799 case TG3_RX_PTP_CTL_RX_PTP_V2_L2_EN | TG3_RX_PTP_CTL_SYNC_EVNT:
13800 stmpconf.rx_filter = HWTSTAMP_FILTER_PTP_V2_L2_SYNC;
13802 case TG3_RX_PTP_CTL_RX_PTP_V2_L4_EN | TG3_RX_PTP_CTL_SYNC_EVNT:
13803 stmpconf.rx_filter = HWTSTAMP_FILTER_PTP_V2_L4_SYNC;
13805 case TG3_RX_PTP_CTL_RX_PTP_V2_EN | TG3_RX_PTP_CTL_DELAY_REQ:
13806 stmpconf.rx_filter = HWTSTAMP_FILTER_PTP_V2_DELAY_REQ;
13808 case TG3_RX_PTP_CTL_RX_PTP_V2_L2_EN | TG3_RX_PTP_CTL_DELAY_REQ:
13809 stmpconf.rx_filter = HWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ;
13811 case TG3_RX_PTP_CTL_RX_PTP_V2_L4_EN | TG3_RX_PTP_CTL_DELAY_REQ:
13812 stmpconf.rx_filter = HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ;
13819 return copy_to_user(ifr->ifr_data, &stmpconf, sizeof(stmpconf)) ?
13823 static int tg3_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
13825 struct mii_ioctl_data *data = if_mii(ifr);
13826 struct tg3 *tp = netdev_priv(dev);
13829 if (tg3_flag(tp, USE_PHYLIB)) {
13830 struct phy_device *phydev;
13831 if (!(tp->phy_flags & TG3_PHYFLG_IS_CONNECTED))
13833 phydev = tp->mdio_bus->phy_map[tp->phy_addr];
13834 return phy_mii_ioctl(phydev, ifr, cmd);
13839 data->phy_id = tp->phy_addr;
13842 case SIOCGMIIREG: {
13845 if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES)
13846 break; /* We have no PHY */
13848 if (!netif_running(dev))
13851 spin_lock_bh(&tp->lock);
13852 err = __tg3_readphy(tp, data->phy_id & 0x1f,
13853 data->reg_num & 0x1f, &mii_regval);
13854 spin_unlock_bh(&tp->lock);
13856 data->val_out = mii_regval;
13862 if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES)
13863 break; /* We have no PHY */
13865 if (!netif_running(dev))
13868 spin_lock_bh(&tp->lock);
13869 err = __tg3_writephy(tp, data->phy_id & 0x1f,
13870 data->reg_num & 0x1f, data->val_in);
13871 spin_unlock_bh(&tp->lock);
13875 case SIOCSHWTSTAMP:
13876 return tg3_hwtstamp_set(dev, ifr);
13878 case SIOCGHWTSTAMP:
13879 return tg3_hwtstamp_get(dev, ifr);
13885 return -EOPNOTSUPP;
13888 static int tg3_get_coalesce(struct net_device *dev, struct ethtool_coalesce *ec)
13890 struct tg3 *tp = netdev_priv(dev);
13892 memcpy(ec, &tp->coal, sizeof(*ec));
13896 static int tg3_set_coalesce(struct net_device *dev, struct ethtool_coalesce *ec)
13898 struct tg3 *tp = netdev_priv(dev);
13899 u32 max_rxcoal_tick_int = 0, max_txcoal_tick_int = 0;
13900 u32 max_stat_coal_ticks = 0, min_stat_coal_ticks = 0;
13902 if (!tg3_flag(tp, 5705_PLUS)) {
13903 max_rxcoal_tick_int = MAX_RXCOAL_TICK_INT;
13904 max_txcoal_tick_int = MAX_TXCOAL_TICK_INT;
13905 max_stat_coal_ticks = MAX_STAT_COAL_TICKS;
13906 min_stat_coal_ticks = MIN_STAT_COAL_TICKS;
13909 if ((ec->rx_coalesce_usecs > MAX_RXCOL_TICKS) ||
13910 (ec->tx_coalesce_usecs > MAX_TXCOL_TICKS) ||
13911 (ec->rx_max_coalesced_frames > MAX_RXMAX_FRAMES) ||
13912 (ec->tx_max_coalesced_frames > MAX_TXMAX_FRAMES) ||
13913 (ec->rx_coalesce_usecs_irq > max_rxcoal_tick_int) ||
13914 (ec->tx_coalesce_usecs_irq > max_txcoal_tick_int) ||
13915 (ec->rx_max_coalesced_frames_irq > MAX_RXCOAL_MAXF_INT) ||
13916 (ec->tx_max_coalesced_frames_irq > MAX_TXCOAL_MAXF_INT) ||
13917 (ec->stats_block_coalesce_usecs > max_stat_coal_ticks) ||
13918 (ec->stats_block_coalesce_usecs < min_stat_coal_ticks))
13921 /* No rx interrupts will be generated if both are zero */
13922 if ((ec->rx_coalesce_usecs == 0) &&
13923 (ec->rx_max_coalesced_frames == 0))
13926 /* No tx interrupts will be generated if both are zero */
13927 if ((ec->tx_coalesce_usecs == 0) &&
13928 (ec->tx_max_coalesced_frames == 0))
13931 /* Only copy relevant parameters, ignore all others. */
13932 tp->coal.rx_coalesce_usecs = ec->rx_coalesce_usecs;
13933 tp->coal.tx_coalesce_usecs = ec->tx_coalesce_usecs;
13934 tp->coal.rx_max_coalesced_frames = ec->rx_max_coalesced_frames;
13935 tp->coal.tx_max_coalesced_frames = ec->tx_max_coalesced_frames;
13936 tp->coal.rx_coalesce_usecs_irq = ec->rx_coalesce_usecs_irq;
13937 tp->coal.tx_coalesce_usecs_irq = ec->tx_coalesce_usecs_irq;
13938 tp->coal.rx_max_coalesced_frames_irq = ec->rx_max_coalesced_frames_irq;
13939 tp->coal.tx_max_coalesced_frames_irq = ec->tx_max_coalesced_frames_irq;
13940 tp->coal.stats_block_coalesce_usecs = ec->stats_block_coalesce_usecs;
13942 if (netif_running(dev)) {
13943 tg3_full_lock(tp, 0);
13944 __tg3_set_coalesce(tp, &tp->coal);
13945 tg3_full_unlock(tp);
13950 static int tg3_set_eee(struct net_device *dev, struct ethtool_eee *edata)
13952 struct tg3 *tp = netdev_priv(dev);
13954 if (!(tp->phy_flags & TG3_PHYFLG_EEE_CAP)) {
13955 netdev_warn(tp->dev, "Board does not support EEE!\n");
13956 return -EOPNOTSUPP;
13959 if (edata->advertised != tp->eee.advertised) {
13960 netdev_warn(tp->dev,
13961 "Direct manipulation of EEE advertisement is not supported\n");
13965 if (edata->tx_lpi_timer > TG3_CPMU_DBTMR1_LNKIDLE_MAX) {
13966 netdev_warn(tp->dev,
13967 "Maximal Tx Lpi timer supported is %#x(u)\n",
13968 TG3_CPMU_DBTMR1_LNKIDLE_MAX);
13974 tp->phy_flags |= TG3_PHYFLG_USER_CONFIGURED;
13975 tg3_warn_mgmt_link_flap(tp);
13977 if (netif_running(tp->dev)) {
13978 tg3_full_lock(tp, 0);
13981 tg3_full_unlock(tp);
13987 static int tg3_get_eee(struct net_device *dev, struct ethtool_eee *edata)
13989 struct tg3 *tp = netdev_priv(dev);
13991 if (!(tp->phy_flags & TG3_PHYFLG_EEE_CAP)) {
13992 netdev_warn(tp->dev,
13993 "Board does not support EEE!\n");
13994 return -EOPNOTSUPP;
14001 static const struct ethtool_ops tg3_ethtool_ops = {
14002 .get_settings = tg3_get_settings,
14003 .set_settings = tg3_set_settings,
14004 .get_drvinfo = tg3_get_drvinfo,
14005 .get_regs_len = tg3_get_regs_len,
14006 .get_regs = tg3_get_regs,
14007 .get_wol = tg3_get_wol,
14008 .set_wol = tg3_set_wol,
14009 .get_msglevel = tg3_get_msglevel,
14010 .set_msglevel = tg3_set_msglevel,
14011 .nway_reset = tg3_nway_reset,
14012 .get_link = ethtool_op_get_link,
14013 .get_eeprom_len = tg3_get_eeprom_len,
14014 .get_eeprom = tg3_get_eeprom,
14015 .set_eeprom = tg3_set_eeprom,
14016 .get_ringparam = tg3_get_ringparam,
14017 .set_ringparam = tg3_set_ringparam,
14018 .get_pauseparam = tg3_get_pauseparam,
14019 .set_pauseparam = tg3_set_pauseparam,
14020 .self_test = tg3_self_test,
14021 .get_strings = tg3_get_strings,
14022 .set_phys_id = tg3_set_phys_id,
14023 .get_ethtool_stats = tg3_get_ethtool_stats,
14024 .get_coalesce = tg3_get_coalesce,
14025 .set_coalesce = tg3_set_coalesce,
14026 .get_sset_count = tg3_get_sset_count,
14027 .get_rxnfc = tg3_get_rxnfc,
14028 .get_rxfh_indir_size = tg3_get_rxfh_indir_size,
14029 .get_rxfh_indir = tg3_get_rxfh_indir,
14030 .set_rxfh_indir = tg3_set_rxfh_indir,
14031 .get_channels = tg3_get_channels,
14032 .set_channels = tg3_set_channels,
14033 .get_ts_info = tg3_get_ts_info,
14034 .get_eee = tg3_get_eee,
14035 .set_eee = tg3_set_eee,
14038 static struct rtnl_link_stats64 *tg3_get_stats64(struct net_device *dev,
14039 struct rtnl_link_stats64 *stats)
14041 struct tg3 *tp = netdev_priv(dev);
14043 spin_lock_bh(&tp->lock);
14044 if (!tp->hw_stats) {
14045 spin_unlock_bh(&tp->lock);
14046 return &tp->net_stats_prev;
14049 tg3_get_nstats(tp, stats);
14050 spin_unlock_bh(&tp->lock);
14055 static void tg3_set_rx_mode(struct net_device *dev)
14057 struct tg3 *tp = netdev_priv(dev);
14059 if (!netif_running(dev))
14062 tg3_full_lock(tp, 0);
14063 __tg3_set_rx_mode(dev);
14064 tg3_full_unlock(tp);
14067 static inline void tg3_set_mtu(struct net_device *dev, struct tg3 *tp,
14070 dev->mtu = new_mtu;
14072 if (new_mtu > ETH_DATA_LEN) {
14073 if (tg3_flag(tp, 5780_CLASS)) {
14074 netdev_update_features(dev);
14075 tg3_flag_clear(tp, TSO_CAPABLE);
14077 tg3_flag_set(tp, JUMBO_RING_ENABLE);
14080 if (tg3_flag(tp, 5780_CLASS)) {
14081 tg3_flag_set(tp, TSO_CAPABLE);
14082 netdev_update_features(dev);
14084 tg3_flag_clear(tp, JUMBO_RING_ENABLE);
14088 static int tg3_change_mtu(struct net_device *dev, int new_mtu)
14090 struct tg3 *tp = netdev_priv(dev);
14092 bool reset_phy = false;
14094 if (new_mtu < TG3_MIN_MTU || new_mtu > TG3_MAX_MTU(tp))
14097 if (!netif_running(dev)) {
14098 /* We'll just catch it later when the
14101 tg3_set_mtu(dev, tp, new_mtu);
14107 tg3_netif_stop(tp);
14109 tg3_set_mtu(dev, tp, new_mtu);
14111 tg3_full_lock(tp, 1);
14113 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
14115 /* Reset PHY, otherwise the read DMA engine will be in a mode that
14116 * breaks all requests to 256 bytes.
14118 if (tg3_asic_rev(tp) == ASIC_REV_57766)
14121 err = tg3_restart_hw(tp, reset_phy);
14124 tg3_netif_start(tp);
14126 tg3_full_unlock(tp);
14134 static const struct net_device_ops tg3_netdev_ops = {
14135 .ndo_open = tg3_open,
14136 .ndo_stop = tg3_close,
14137 .ndo_start_xmit = tg3_start_xmit,
14138 .ndo_get_stats64 = tg3_get_stats64,
14139 .ndo_validate_addr = eth_validate_addr,
14140 .ndo_set_rx_mode = tg3_set_rx_mode,
14141 .ndo_set_mac_address = tg3_set_mac_addr,
14142 .ndo_do_ioctl = tg3_ioctl,
14143 .ndo_tx_timeout = tg3_tx_timeout,
14144 .ndo_change_mtu = tg3_change_mtu,
14145 .ndo_fix_features = tg3_fix_features,
14146 .ndo_set_features = tg3_set_features,
14147 #ifdef CONFIG_NET_POLL_CONTROLLER
14148 .ndo_poll_controller = tg3_poll_controller,
14152 static void tg3_get_eeprom_size(struct tg3 *tp)
14154 u32 cursize, val, magic;
14156 tp->nvram_size = EEPROM_CHIP_SIZE;
14158 if (tg3_nvram_read(tp, 0, &magic) != 0)
14161 if ((magic != TG3_EEPROM_MAGIC) &&
14162 ((magic & TG3_EEPROM_MAGIC_FW_MSK) != TG3_EEPROM_MAGIC_FW) &&
14163 ((magic & TG3_EEPROM_MAGIC_HW_MSK) != TG3_EEPROM_MAGIC_HW))
14167 * Size the chip by reading offsets at increasing powers of two.
14168 * When we encounter our validation signature, we know the addressing
14169 * has wrapped around, and thus have our chip size.
14173 while (cursize < tp->nvram_size) {
14174 if (tg3_nvram_read(tp, cursize, &val) != 0)
14183 tp->nvram_size = cursize;
14186 static void tg3_get_nvram_size(struct tg3 *tp)
14190 if (tg3_flag(tp, NO_NVRAM) || tg3_nvram_read(tp, 0, &val) != 0)
14193 /* Selfboot format */
14194 if (val != TG3_EEPROM_MAGIC) {
14195 tg3_get_eeprom_size(tp);
14199 if (tg3_nvram_read(tp, 0xf0, &val) == 0) {
14201 /* This is confusing. We want to operate on the
14202 * 16-bit value at offset 0xf2. The tg3_nvram_read()
14203 * call will read from NVRAM and byteswap the data
14204 * according to the byteswapping settings for all
14205 * other register accesses. This ensures the data we
14206 * want will always reside in the lower 16-bits.
14207 * However, the data in NVRAM is in LE format, which
14208 * means the data from the NVRAM read will always be
14209 * opposite the endianness of the CPU. The 16-bit
14210 * byteswap then brings the data to CPU endianness.
14212 tp->nvram_size = swab16((u16)(val & 0x0000ffff)) * 1024;
14216 tp->nvram_size = TG3_NVRAM_SIZE_512KB;
14219 static void tg3_get_nvram_info(struct tg3 *tp)
14223 nvcfg1 = tr32(NVRAM_CFG1);
14224 if (nvcfg1 & NVRAM_CFG1_FLASHIF_ENAB) {
14225 tg3_flag_set(tp, FLASH);
14227 nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
14228 tw32(NVRAM_CFG1, nvcfg1);
14231 if (tg3_asic_rev(tp) == ASIC_REV_5750 ||
14232 tg3_flag(tp, 5780_CLASS)) {
14233 switch (nvcfg1 & NVRAM_CFG1_VENDOR_MASK) {
14234 case FLASH_VENDOR_ATMEL_FLASH_BUFFERED:
14235 tp->nvram_jedecnum = JEDEC_ATMEL;
14236 tp->nvram_pagesize = ATMEL_AT45DB0X1B_PAGE_SIZE;
14237 tg3_flag_set(tp, NVRAM_BUFFERED);
14239 case FLASH_VENDOR_ATMEL_FLASH_UNBUFFERED:
14240 tp->nvram_jedecnum = JEDEC_ATMEL;
14241 tp->nvram_pagesize = ATMEL_AT25F512_PAGE_SIZE;
14243 case FLASH_VENDOR_ATMEL_EEPROM:
14244 tp->nvram_jedecnum = JEDEC_ATMEL;
14245 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
14246 tg3_flag_set(tp, NVRAM_BUFFERED);
14248 case FLASH_VENDOR_ST:
14249 tp->nvram_jedecnum = JEDEC_ST;
14250 tp->nvram_pagesize = ST_M45PEX0_PAGE_SIZE;
14251 tg3_flag_set(tp, NVRAM_BUFFERED);
14253 case FLASH_VENDOR_SAIFUN:
14254 tp->nvram_jedecnum = JEDEC_SAIFUN;
14255 tp->nvram_pagesize = SAIFUN_SA25F0XX_PAGE_SIZE;
14257 case FLASH_VENDOR_SST_SMALL:
14258 case FLASH_VENDOR_SST_LARGE:
14259 tp->nvram_jedecnum = JEDEC_SST;
14260 tp->nvram_pagesize = SST_25VF0X0_PAGE_SIZE;
14264 tp->nvram_jedecnum = JEDEC_ATMEL;
14265 tp->nvram_pagesize = ATMEL_AT45DB0X1B_PAGE_SIZE;
14266 tg3_flag_set(tp, NVRAM_BUFFERED);
14270 static void tg3_nvram_get_pagesize(struct tg3 *tp, u32 nvmcfg1)
14272 switch (nvmcfg1 & NVRAM_CFG1_5752PAGE_SIZE_MASK) {
14273 case FLASH_5752PAGE_SIZE_256:
14274 tp->nvram_pagesize = 256;
14276 case FLASH_5752PAGE_SIZE_512:
14277 tp->nvram_pagesize = 512;
14279 case FLASH_5752PAGE_SIZE_1K:
14280 tp->nvram_pagesize = 1024;
14282 case FLASH_5752PAGE_SIZE_2K:
14283 tp->nvram_pagesize = 2048;
14285 case FLASH_5752PAGE_SIZE_4K:
14286 tp->nvram_pagesize = 4096;
14288 case FLASH_5752PAGE_SIZE_264:
14289 tp->nvram_pagesize = 264;
14291 case FLASH_5752PAGE_SIZE_528:
14292 tp->nvram_pagesize = 528;
14297 static void tg3_get_5752_nvram_info(struct tg3 *tp)
14301 nvcfg1 = tr32(NVRAM_CFG1);
14303 /* NVRAM protection for TPM */
14304 if (nvcfg1 & (1 << 27))
14305 tg3_flag_set(tp, PROTECTED_NVRAM);
14307 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
14308 case FLASH_5752VENDOR_ATMEL_EEPROM_64KHZ:
14309 case FLASH_5752VENDOR_ATMEL_EEPROM_376KHZ:
14310 tp->nvram_jedecnum = JEDEC_ATMEL;
14311 tg3_flag_set(tp, NVRAM_BUFFERED);
14313 case FLASH_5752VENDOR_ATMEL_FLASH_BUFFERED:
14314 tp->nvram_jedecnum = JEDEC_ATMEL;
14315 tg3_flag_set(tp, NVRAM_BUFFERED);
14316 tg3_flag_set(tp, FLASH);
14318 case FLASH_5752VENDOR_ST_M45PE10:
14319 case FLASH_5752VENDOR_ST_M45PE20:
14320 case FLASH_5752VENDOR_ST_M45PE40:
14321 tp->nvram_jedecnum = JEDEC_ST;
14322 tg3_flag_set(tp, NVRAM_BUFFERED);
14323 tg3_flag_set(tp, FLASH);
14327 if (tg3_flag(tp, FLASH)) {
14328 tg3_nvram_get_pagesize(tp, nvcfg1);
14330 /* For eeprom, set pagesize to maximum eeprom size */
14331 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
14333 nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
14334 tw32(NVRAM_CFG1, nvcfg1);
14338 static void tg3_get_5755_nvram_info(struct tg3 *tp)
14340 u32 nvcfg1, protect = 0;
14342 nvcfg1 = tr32(NVRAM_CFG1);
14344 /* NVRAM protection for TPM */
14345 if (nvcfg1 & (1 << 27)) {
14346 tg3_flag_set(tp, PROTECTED_NVRAM);
14350 nvcfg1 &= NVRAM_CFG1_5752VENDOR_MASK;
14352 case FLASH_5755VENDOR_ATMEL_FLASH_1:
14353 case FLASH_5755VENDOR_ATMEL_FLASH_2:
14354 case FLASH_5755VENDOR_ATMEL_FLASH_3:
14355 case FLASH_5755VENDOR_ATMEL_FLASH_5:
14356 tp->nvram_jedecnum = JEDEC_ATMEL;
14357 tg3_flag_set(tp, NVRAM_BUFFERED);
14358 tg3_flag_set(tp, FLASH);
14359 tp->nvram_pagesize = 264;
14360 if (nvcfg1 == FLASH_5755VENDOR_ATMEL_FLASH_1 ||
14361 nvcfg1 == FLASH_5755VENDOR_ATMEL_FLASH_5)
14362 tp->nvram_size = (protect ? 0x3e200 :
14363 TG3_NVRAM_SIZE_512KB);
14364 else if (nvcfg1 == FLASH_5755VENDOR_ATMEL_FLASH_2)
14365 tp->nvram_size = (protect ? 0x1f200 :
14366 TG3_NVRAM_SIZE_256KB);
14368 tp->nvram_size = (protect ? 0x1f200 :
14369 TG3_NVRAM_SIZE_128KB);
14371 case FLASH_5752VENDOR_ST_M45PE10:
14372 case FLASH_5752VENDOR_ST_M45PE20:
14373 case FLASH_5752VENDOR_ST_M45PE40:
14374 tp->nvram_jedecnum = JEDEC_ST;
14375 tg3_flag_set(tp, NVRAM_BUFFERED);
14376 tg3_flag_set(tp, FLASH);
14377 tp->nvram_pagesize = 256;
14378 if (nvcfg1 == FLASH_5752VENDOR_ST_M45PE10)
14379 tp->nvram_size = (protect ?
14380 TG3_NVRAM_SIZE_64KB :
14381 TG3_NVRAM_SIZE_128KB);
14382 else if (nvcfg1 == FLASH_5752VENDOR_ST_M45PE20)
14383 tp->nvram_size = (protect ?
14384 TG3_NVRAM_SIZE_64KB :
14385 TG3_NVRAM_SIZE_256KB);
14387 tp->nvram_size = (protect ?
14388 TG3_NVRAM_SIZE_128KB :
14389 TG3_NVRAM_SIZE_512KB);
14394 static void tg3_get_5787_nvram_info(struct tg3 *tp)
14398 nvcfg1 = tr32(NVRAM_CFG1);
14400 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
14401 case FLASH_5787VENDOR_ATMEL_EEPROM_64KHZ:
14402 case FLASH_5787VENDOR_ATMEL_EEPROM_376KHZ:
14403 case FLASH_5787VENDOR_MICRO_EEPROM_64KHZ:
14404 case FLASH_5787VENDOR_MICRO_EEPROM_376KHZ:
14405 tp->nvram_jedecnum = JEDEC_ATMEL;
14406 tg3_flag_set(tp, NVRAM_BUFFERED);
14407 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
14409 nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
14410 tw32(NVRAM_CFG1, nvcfg1);
14412 case FLASH_5752VENDOR_ATMEL_FLASH_BUFFERED:
14413 case FLASH_5755VENDOR_ATMEL_FLASH_1:
14414 case FLASH_5755VENDOR_ATMEL_FLASH_2:
14415 case FLASH_5755VENDOR_ATMEL_FLASH_3:
14416 tp->nvram_jedecnum = JEDEC_ATMEL;
14417 tg3_flag_set(tp, NVRAM_BUFFERED);
14418 tg3_flag_set(tp, FLASH);
14419 tp->nvram_pagesize = 264;
14421 case FLASH_5752VENDOR_ST_M45PE10:
14422 case FLASH_5752VENDOR_ST_M45PE20:
14423 case FLASH_5752VENDOR_ST_M45PE40:
14424 tp->nvram_jedecnum = JEDEC_ST;
14425 tg3_flag_set(tp, NVRAM_BUFFERED);
14426 tg3_flag_set(tp, FLASH);
14427 tp->nvram_pagesize = 256;
14432 static void tg3_get_5761_nvram_info(struct tg3 *tp)
14434 u32 nvcfg1, protect = 0;
14436 nvcfg1 = tr32(NVRAM_CFG1);
14438 /* NVRAM protection for TPM */
14439 if (nvcfg1 & (1 << 27)) {
14440 tg3_flag_set(tp, PROTECTED_NVRAM);
14444 nvcfg1 &= NVRAM_CFG1_5752VENDOR_MASK;
14446 case FLASH_5761VENDOR_ATMEL_ADB021D:
14447 case FLASH_5761VENDOR_ATMEL_ADB041D:
14448 case FLASH_5761VENDOR_ATMEL_ADB081D:
14449 case FLASH_5761VENDOR_ATMEL_ADB161D:
14450 case FLASH_5761VENDOR_ATMEL_MDB021D:
14451 case FLASH_5761VENDOR_ATMEL_MDB041D:
14452 case FLASH_5761VENDOR_ATMEL_MDB081D:
14453 case FLASH_5761VENDOR_ATMEL_MDB161D:
14454 tp->nvram_jedecnum = JEDEC_ATMEL;
14455 tg3_flag_set(tp, NVRAM_BUFFERED);
14456 tg3_flag_set(tp, FLASH);
14457 tg3_flag_set(tp, NO_NVRAM_ADDR_TRANS);
14458 tp->nvram_pagesize = 256;
14460 case FLASH_5761VENDOR_ST_A_M45PE20:
14461 case FLASH_5761VENDOR_ST_A_M45PE40:
14462 case FLASH_5761VENDOR_ST_A_M45PE80:
14463 case FLASH_5761VENDOR_ST_A_M45PE16:
14464 case FLASH_5761VENDOR_ST_M_M45PE20:
14465 case FLASH_5761VENDOR_ST_M_M45PE40:
14466 case FLASH_5761VENDOR_ST_M_M45PE80:
14467 case FLASH_5761VENDOR_ST_M_M45PE16:
14468 tp->nvram_jedecnum = JEDEC_ST;
14469 tg3_flag_set(tp, NVRAM_BUFFERED);
14470 tg3_flag_set(tp, FLASH);
14471 tp->nvram_pagesize = 256;
14476 tp->nvram_size = tr32(NVRAM_ADDR_LOCKOUT);
14479 case FLASH_5761VENDOR_ATMEL_ADB161D:
14480 case FLASH_5761VENDOR_ATMEL_MDB161D:
14481 case FLASH_5761VENDOR_ST_A_M45PE16:
14482 case FLASH_5761VENDOR_ST_M_M45PE16:
14483 tp->nvram_size = TG3_NVRAM_SIZE_2MB;
14485 case FLASH_5761VENDOR_ATMEL_ADB081D:
14486 case FLASH_5761VENDOR_ATMEL_MDB081D:
14487 case FLASH_5761VENDOR_ST_A_M45PE80:
14488 case FLASH_5761VENDOR_ST_M_M45PE80:
14489 tp->nvram_size = TG3_NVRAM_SIZE_1MB;
14491 case FLASH_5761VENDOR_ATMEL_ADB041D:
14492 case FLASH_5761VENDOR_ATMEL_MDB041D:
14493 case FLASH_5761VENDOR_ST_A_M45PE40:
14494 case FLASH_5761VENDOR_ST_M_M45PE40:
14495 tp->nvram_size = TG3_NVRAM_SIZE_512KB;
14497 case FLASH_5761VENDOR_ATMEL_ADB021D:
14498 case FLASH_5761VENDOR_ATMEL_MDB021D:
14499 case FLASH_5761VENDOR_ST_A_M45PE20:
14500 case FLASH_5761VENDOR_ST_M_M45PE20:
14501 tp->nvram_size = TG3_NVRAM_SIZE_256KB;
14507 static void tg3_get_5906_nvram_info(struct tg3 *tp)
14509 tp->nvram_jedecnum = JEDEC_ATMEL;
14510 tg3_flag_set(tp, NVRAM_BUFFERED);
14511 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
14514 static void tg3_get_57780_nvram_info(struct tg3 *tp)
14518 nvcfg1 = tr32(NVRAM_CFG1);
14520 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
14521 case FLASH_5787VENDOR_ATMEL_EEPROM_376KHZ:
14522 case FLASH_5787VENDOR_MICRO_EEPROM_376KHZ:
14523 tp->nvram_jedecnum = JEDEC_ATMEL;
14524 tg3_flag_set(tp, NVRAM_BUFFERED);
14525 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
14527 nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
14528 tw32(NVRAM_CFG1, nvcfg1);
14530 case FLASH_5752VENDOR_ATMEL_FLASH_BUFFERED:
14531 case FLASH_57780VENDOR_ATMEL_AT45DB011D:
14532 case FLASH_57780VENDOR_ATMEL_AT45DB011B:
14533 case FLASH_57780VENDOR_ATMEL_AT45DB021D:
14534 case FLASH_57780VENDOR_ATMEL_AT45DB021B:
14535 case FLASH_57780VENDOR_ATMEL_AT45DB041D:
14536 case FLASH_57780VENDOR_ATMEL_AT45DB041B:
14537 tp->nvram_jedecnum = JEDEC_ATMEL;
14538 tg3_flag_set(tp, NVRAM_BUFFERED);
14539 tg3_flag_set(tp, FLASH);
14541 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
14542 case FLASH_5752VENDOR_ATMEL_FLASH_BUFFERED:
14543 case FLASH_57780VENDOR_ATMEL_AT45DB011D:
14544 case FLASH_57780VENDOR_ATMEL_AT45DB011B:
14545 tp->nvram_size = TG3_NVRAM_SIZE_128KB;
14547 case FLASH_57780VENDOR_ATMEL_AT45DB021D:
14548 case FLASH_57780VENDOR_ATMEL_AT45DB021B:
14549 tp->nvram_size = TG3_NVRAM_SIZE_256KB;
14551 case FLASH_57780VENDOR_ATMEL_AT45DB041D:
14552 case FLASH_57780VENDOR_ATMEL_AT45DB041B:
14553 tp->nvram_size = TG3_NVRAM_SIZE_512KB;
14557 case FLASH_5752VENDOR_ST_M45PE10:
14558 case FLASH_5752VENDOR_ST_M45PE20:
14559 case FLASH_5752VENDOR_ST_M45PE40:
14560 tp->nvram_jedecnum = JEDEC_ST;
14561 tg3_flag_set(tp, NVRAM_BUFFERED);
14562 tg3_flag_set(tp, FLASH);
14564 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
14565 case FLASH_5752VENDOR_ST_M45PE10:
14566 tp->nvram_size = TG3_NVRAM_SIZE_128KB;
14568 case FLASH_5752VENDOR_ST_M45PE20:
14569 tp->nvram_size = TG3_NVRAM_SIZE_256KB;
14571 case FLASH_5752VENDOR_ST_M45PE40:
14572 tp->nvram_size = TG3_NVRAM_SIZE_512KB;
14577 tg3_flag_set(tp, NO_NVRAM);
14581 tg3_nvram_get_pagesize(tp, nvcfg1);
14582 if (tp->nvram_pagesize != 264 && tp->nvram_pagesize != 528)
14583 tg3_flag_set(tp, NO_NVRAM_ADDR_TRANS);
14587 static void tg3_get_5717_nvram_info(struct tg3 *tp)
14591 nvcfg1 = tr32(NVRAM_CFG1);
14593 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
14594 case FLASH_5717VENDOR_ATMEL_EEPROM:
14595 case FLASH_5717VENDOR_MICRO_EEPROM:
14596 tp->nvram_jedecnum = JEDEC_ATMEL;
14597 tg3_flag_set(tp, NVRAM_BUFFERED);
14598 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
14600 nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
14601 tw32(NVRAM_CFG1, nvcfg1);
14603 case FLASH_5717VENDOR_ATMEL_MDB011D:
14604 case FLASH_5717VENDOR_ATMEL_ADB011B:
14605 case FLASH_5717VENDOR_ATMEL_ADB011D:
14606 case FLASH_5717VENDOR_ATMEL_MDB021D:
14607 case FLASH_5717VENDOR_ATMEL_ADB021B:
14608 case FLASH_5717VENDOR_ATMEL_ADB021D:
14609 case FLASH_5717VENDOR_ATMEL_45USPT:
14610 tp->nvram_jedecnum = JEDEC_ATMEL;
14611 tg3_flag_set(tp, NVRAM_BUFFERED);
14612 tg3_flag_set(tp, FLASH);
14614 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
14615 case FLASH_5717VENDOR_ATMEL_MDB021D:
14616 /* Detect size with tg3_nvram_get_size() */
14618 case FLASH_5717VENDOR_ATMEL_ADB021B:
14619 case FLASH_5717VENDOR_ATMEL_ADB021D:
14620 tp->nvram_size = TG3_NVRAM_SIZE_256KB;
14623 tp->nvram_size = TG3_NVRAM_SIZE_128KB;
14627 case FLASH_5717VENDOR_ST_M_M25PE10:
14628 case FLASH_5717VENDOR_ST_A_M25PE10:
14629 case FLASH_5717VENDOR_ST_M_M45PE10:
14630 case FLASH_5717VENDOR_ST_A_M45PE10:
14631 case FLASH_5717VENDOR_ST_M_M25PE20:
14632 case FLASH_5717VENDOR_ST_A_M25PE20:
14633 case FLASH_5717VENDOR_ST_M_M45PE20:
14634 case FLASH_5717VENDOR_ST_A_M45PE20:
14635 case FLASH_5717VENDOR_ST_25USPT:
14636 case FLASH_5717VENDOR_ST_45USPT:
14637 tp->nvram_jedecnum = JEDEC_ST;
14638 tg3_flag_set(tp, NVRAM_BUFFERED);
14639 tg3_flag_set(tp, FLASH);
14641 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
14642 case FLASH_5717VENDOR_ST_M_M25PE20:
14643 case FLASH_5717VENDOR_ST_M_M45PE20:
14644 /* Detect size with tg3_nvram_get_size() */
14646 case FLASH_5717VENDOR_ST_A_M25PE20:
14647 case FLASH_5717VENDOR_ST_A_M45PE20:
14648 tp->nvram_size = TG3_NVRAM_SIZE_256KB;
14651 tp->nvram_size = TG3_NVRAM_SIZE_128KB;
14656 tg3_flag_set(tp, NO_NVRAM);
14660 tg3_nvram_get_pagesize(tp, nvcfg1);
14661 if (tp->nvram_pagesize != 264 && tp->nvram_pagesize != 528)
14662 tg3_flag_set(tp, NO_NVRAM_ADDR_TRANS);
14665 static void tg3_get_5720_nvram_info(struct tg3 *tp)
14667 u32 nvcfg1, nvmpinstrp;
14669 nvcfg1 = tr32(NVRAM_CFG1);
14670 nvmpinstrp = nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK;
14672 if (tg3_asic_rev(tp) == ASIC_REV_5762) {
14673 if (!(nvcfg1 & NVRAM_CFG1_5762VENDOR_MASK)) {
14674 tg3_flag_set(tp, NO_NVRAM);
14678 switch (nvmpinstrp) {
14679 case FLASH_5762_EEPROM_HD:
14680 nvmpinstrp = FLASH_5720_EEPROM_HD;
14682 case FLASH_5762_EEPROM_LD:
14683 nvmpinstrp = FLASH_5720_EEPROM_LD;
14685 case FLASH_5720VENDOR_M_ST_M45PE20:
14686 /* This pinstrap supports multiple sizes, so force it
14687 * to read the actual size from location 0xf0.
14689 nvmpinstrp = FLASH_5720VENDOR_ST_45USPT;
14694 switch (nvmpinstrp) {
14695 case FLASH_5720_EEPROM_HD:
14696 case FLASH_5720_EEPROM_LD:
14697 tp->nvram_jedecnum = JEDEC_ATMEL;
14698 tg3_flag_set(tp, NVRAM_BUFFERED);
14700 nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
14701 tw32(NVRAM_CFG1, nvcfg1);
14702 if (nvmpinstrp == FLASH_5720_EEPROM_HD)
14703 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
14705 tp->nvram_pagesize = ATMEL_AT24C02_CHIP_SIZE;
14707 case FLASH_5720VENDOR_M_ATMEL_DB011D:
14708 case FLASH_5720VENDOR_A_ATMEL_DB011B:
14709 case FLASH_5720VENDOR_A_ATMEL_DB011D:
14710 case FLASH_5720VENDOR_M_ATMEL_DB021D:
14711 case FLASH_5720VENDOR_A_ATMEL_DB021B:
14712 case FLASH_5720VENDOR_A_ATMEL_DB021D:
14713 case FLASH_5720VENDOR_M_ATMEL_DB041D:
14714 case FLASH_5720VENDOR_A_ATMEL_DB041B:
14715 case FLASH_5720VENDOR_A_ATMEL_DB041D:
14716 case FLASH_5720VENDOR_M_ATMEL_DB081D:
14717 case FLASH_5720VENDOR_A_ATMEL_DB081D:
14718 case FLASH_5720VENDOR_ATMEL_45USPT:
14719 tp->nvram_jedecnum = JEDEC_ATMEL;
14720 tg3_flag_set(tp, NVRAM_BUFFERED);
14721 tg3_flag_set(tp, FLASH);
14723 switch (nvmpinstrp) {
14724 case FLASH_5720VENDOR_M_ATMEL_DB021D:
14725 case FLASH_5720VENDOR_A_ATMEL_DB021B:
14726 case FLASH_5720VENDOR_A_ATMEL_DB021D:
14727 tp->nvram_size = TG3_NVRAM_SIZE_256KB;
14729 case FLASH_5720VENDOR_M_ATMEL_DB041D:
14730 case FLASH_5720VENDOR_A_ATMEL_DB041B:
14731 case FLASH_5720VENDOR_A_ATMEL_DB041D:
14732 tp->nvram_size = TG3_NVRAM_SIZE_512KB;
14734 case FLASH_5720VENDOR_M_ATMEL_DB081D:
14735 case FLASH_5720VENDOR_A_ATMEL_DB081D:
14736 tp->nvram_size = TG3_NVRAM_SIZE_1MB;
14739 if (tg3_asic_rev(tp) != ASIC_REV_5762)
14740 tp->nvram_size = TG3_NVRAM_SIZE_128KB;
14744 case FLASH_5720VENDOR_M_ST_M25PE10:
14745 case FLASH_5720VENDOR_M_ST_M45PE10:
14746 case FLASH_5720VENDOR_A_ST_M25PE10:
14747 case FLASH_5720VENDOR_A_ST_M45PE10:
14748 case FLASH_5720VENDOR_M_ST_M25PE20:
14749 case FLASH_5720VENDOR_M_ST_M45PE20:
14750 case FLASH_5720VENDOR_A_ST_M25PE20:
14751 case FLASH_5720VENDOR_A_ST_M45PE20:
14752 case FLASH_5720VENDOR_M_ST_M25PE40:
14753 case FLASH_5720VENDOR_M_ST_M45PE40:
14754 case FLASH_5720VENDOR_A_ST_M25PE40:
14755 case FLASH_5720VENDOR_A_ST_M45PE40:
14756 case FLASH_5720VENDOR_M_ST_M25PE80:
14757 case FLASH_5720VENDOR_M_ST_M45PE80:
14758 case FLASH_5720VENDOR_A_ST_M25PE80:
14759 case FLASH_5720VENDOR_A_ST_M45PE80:
14760 case FLASH_5720VENDOR_ST_25USPT:
14761 case FLASH_5720VENDOR_ST_45USPT:
14762 tp->nvram_jedecnum = JEDEC_ST;
14763 tg3_flag_set(tp, NVRAM_BUFFERED);
14764 tg3_flag_set(tp, FLASH);
14766 switch (nvmpinstrp) {
14767 case FLASH_5720VENDOR_M_ST_M25PE20:
14768 case FLASH_5720VENDOR_M_ST_M45PE20:
14769 case FLASH_5720VENDOR_A_ST_M25PE20:
14770 case FLASH_5720VENDOR_A_ST_M45PE20:
14771 tp->nvram_size = TG3_NVRAM_SIZE_256KB;
14773 case FLASH_5720VENDOR_M_ST_M25PE40:
14774 case FLASH_5720VENDOR_M_ST_M45PE40:
14775 case FLASH_5720VENDOR_A_ST_M25PE40:
14776 case FLASH_5720VENDOR_A_ST_M45PE40:
14777 tp->nvram_size = TG3_NVRAM_SIZE_512KB;
14779 case FLASH_5720VENDOR_M_ST_M25PE80:
14780 case FLASH_5720VENDOR_M_ST_M45PE80:
14781 case FLASH_5720VENDOR_A_ST_M25PE80:
14782 case FLASH_5720VENDOR_A_ST_M45PE80:
14783 tp->nvram_size = TG3_NVRAM_SIZE_1MB;
14786 if (tg3_asic_rev(tp) != ASIC_REV_5762)
14787 tp->nvram_size = TG3_NVRAM_SIZE_128KB;
14792 tg3_flag_set(tp, NO_NVRAM);
14796 tg3_nvram_get_pagesize(tp, nvcfg1);
14797 if (tp->nvram_pagesize != 264 && tp->nvram_pagesize != 528)
14798 tg3_flag_set(tp, NO_NVRAM_ADDR_TRANS);
14800 if (tg3_asic_rev(tp) == ASIC_REV_5762) {
14803 if (tg3_nvram_read(tp, 0, &val))
14806 if (val != TG3_EEPROM_MAGIC &&
14807 (val & TG3_EEPROM_MAGIC_FW_MSK) != TG3_EEPROM_MAGIC_FW)
14808 tg3_flag_set(tp, NO_NVRAM);
14812 /* Chips other than 5700/5701 use the NVRAM for fetching info. */
14813 static void tg3_nvram_init(struct tg3 *tp)
14815 if (tg3_flag(tp, IS_SSB_CORE)) {
14816 /* No NVRAM and EEPROM on the SSB Broadcom GigE core. */
14817 tg3_flag_clear(tp, NVRAM);
14818 tg3_flag_clear(tp, NVRAM_BUFFERED);
14819 tg3_flag_set(tp, NO_NVRAM);
14823 tw32_f(GRC_EEPROM_ADDR,
14824 (EEPROM_ADDR_FSM_RESET |
14825 (EEPROM_DEFAULT_CLOCK_PERIOD <<
14826 EEPROM_ADDR_CLKPERD_SHIFT)));
14830 /* Enable seeprom accesses. */
14831 tw32_f(GRC_LOCAL_CTRL,
14832 tr32(GRC_LOCAL_CTRL) | GRC_LCLCTRL_AUTO_SEEPROM);
14835 if (tg3_asic_rev(tp) != ASIC_REV_5700 &&
14836 tg3_asic_rev(tp) != ASIC_REV_5701) {
14837 tg3_flag_set(tp, NVRAM);
14839 if (tg3_nvram_lock(tp)) {
14840 netdev_warn(tp->dev,
14841 "Cannot get nvram lock, %s failed\n",
14845 tg3_enable_nvram_access(tp);
14847 tp->nvram_size = 0;
14849 if (tg3_asic_rev(tp) == ASIC_REV_5752)
14850 tg3_get_5752_nvram_info(tp);
14851 else if (tg3_asic_rev(tp) == ASIC_REV_5755)
14852 tg3_get_5755_nvram_info(tp);
14853 else if (tg3_asic_rev(tp) == ASIC_REV_5787 ||
14854 tg3_asic_rev(tp) == ASIC_REV_5784 ||
14855 tg3_asic_rev(tp) == ASIC_REV_5785)
14856 tg3_get_5787_nvram_info(tp);
14857 else if (tg3_asic_rev(tp) == ASIC_REV_5761)
14858 tg3_get_5761_nvram_info(tp);
14859 else if (tg3_asic_rev(tp) == ASIC_REV_5906)
14860 tg3_get_5906_nvram_info(tp);
14861 else if (tg3_asic_rev(tp) == ASIC_REV_57780 ||
14862 tg3_flag(tp, 57765_CLASS))
14863 tg3_get_57780_nvram_info(tp);
14864 else if (tg3_asic_rev(tp) == ASIC_REV_5717 ||
14865 tg3_asic_rev(tp) == ASIC_REV_5719)
14866 tg3_get_5717_nvram_info(tp);
14867 else if (tg3_asic_rev(tp) == ASIC_REV_5720 ||
14868 tg3_asic_rev(tp) == ASIC_REV_5762)
14869 tg3_get_5720_nvram_info(tp);
14871 tg3_get_nvram_info(tp);
14873 if (tp->nvram_size == 0)
14874 tg3_get_nvram_size(tp);
14876 tg3_disable_nvram_access(tp);
14877 tg3_nvram_unlock(tp);
14880 tg3_flag_clear(tp, NVRAM);
14881 tg3_flag_clear(tp, NVRAM_BUFFERED);
14883 tg3_get_eeprom_size(tp);
14887 struct subsys_tbl_ent {
14888 u16 subsys_vendor, subsys_devid;
14892 static struct subsys_tbl_ent subsys_id_to_phy_id[] = {
14893 /* Broadcom boards. */
14894 { TG3PCI_SUBVENDOR_ID_BROADCOM,
14895 TG3PCI_SUBDEVICE_ID_BROADCOM_95700A6, TG3_PHY_ID_BCM5401 },
14896 { TG3PCI_SUBVENDOR_ID_BROADCOM,
14897 TG3PCI_SUBDEVICE_ID_BROADCOM_95701A5, TG3_PHY_ID_BCM5701 },
14898 { TG3PCI_SUBVENDOR_ID_BROADCOM,
14899 TG3PCI_SUBDEVICE_ID_BROADCOM_95700T6, TG3_PHY_ID_BCM8002 },
14900 { TG3PCI_SUBVENDOR_ID_BROADCOM,
14901 TG3PCI_SUBDEVICE_ID_BROADCOM_95700A9, 0 },
14902 { TG3PCI_SUBVENDOR_ID_BROADCOM,
14903 TG3PCI_SUBDEVICE_ID_BROADCOM_95701T1, TG3_PHY_ID_BCM5701 },
14904 { TG3PCI_SUBVENDOR_ID_BROADCOM,
14905 TG3PCI_SUBDEVICE_ID_BROADCOM_95701T8, TG3_PHY_ID_BCM5701 },
14906 { TG3PCI_SUBVENDOR_ID_BROADCOM,
14907 TG3PCI_SUBDEVICE_ID_BROADCOM_95701A7, 0 },
14908 { TG3PCI_SUBVENDOR_ID_BROADCOM,
14909 TG3PCI_SUBDEVICE_ID_BROADCOM_95701A10, TG3_PHY_ID_BCM5701 },
14910 { TG3PCI_SUBVENDOR_ID_BROADCOM,
14911 TG3PCI_SUBDEVICE_ID_BROADCOM_95701A12, TG3_PHY_ID_BCM5701 },
14912 { TG3PCI_SUBVENDOR_ID_BROADCOM,
14913 TG3PCI_SUBDEVICE_ID_BROADCOM_95703AX1, TG3_PHY_ID_BCM5703 },
14914 { TG3PCI_SUBVENDOR_ID_BROADCOM,
14915 TG3PCI_SUBDEVICE_ID_BROADCOM_95703AX2, TG3_PHY_ID_BCM5703 },
14918 { TG3PCI_SUBVENDOR_ID_3COM,
14919 TG3PCI_SUBDEVICE_ID_3COM_3C996T, TG3_PHY_ID_BCM5401 },
14920 { TG3PCI_SUBVENDOR_ID_3COM,
14921 TG3PCI_SUBDEVICE_ID_3COM_3C996BT, TG3_PHY_ID_BCM5701 },
14922 { TG3PCI_SUBVENDOR_ID_3COM,
14923 TG3PCI_SUBDEVICE_ID_3COM_3C996SX, 0 },
14924 { TG3PCI_SUBVENDOR_ID_3COM,
14925 TG3PCI_SUBDEVICE_ID_3COM_3C1000T, TG3_PHY_ID_BCM5701 },
14926 { TG3PCI_SUBVENDOR_ID_3COM,
14927 TG3PCI_SUBDEVICE_ID_3COM_3C940BR01, TG3_PHY_ID_BCM5701 },
14930 { TG3PCI_SUBVENDOR_ID_DELL,
14931 TG3PCI_SUBDEVICE_ID_DELL_VIPER, TG3_PHY_ID_BCM5401 },
14932 { TG3PCI_SUBVENDOR_ID_DELL,
14933 TG3PCI_SUBDEVICE_ID_DELL_JAGUAR, TG3_PHY_ID_BCM5401 },
14934 { TG3PCI_SUBVENDOR_ID_DELL,
14935 TG3PCI_SUBDEVICE_ID_DELL_MERLOT, TG3_PHY_ID_BCM5411 },
14936 { TG3PCI_SUBVENDOR_ID_DELL,
14937 TG3PCI_SUBDEVICE_ID_DELL_SLIM_MERLOT, TG3_PHY_ID_BCM5411 },
14939 /* Compaq boards. */
14940 { TG3PCI_SUBVENDOR_ID_COMPAQ,
14941 TG3PCI_SUBDEVICE_ID_COMPAQ_BANSHEE, TG3_PHY_ID_BCM5701 },
14942 { TG3PCI_SUBVENDOR_ID_COMPAQ,
14943 TG3PCI_SUBDEVICE_ID_COMPAQ_BANSHEE_2, TG3_PHY_ID_BCM5701 },
14944 { TG3PCI_SUBVENDOR_ID_COMPAQ,
14945 TG3PCI_SUBDEVICE_ID_COMPAQ_CHANGELING, 0 },
14946 { TG3PCI_SUBVENDOR_ID_COMPAQ,
14947 TG3PCI_SUBDEVICE_ID_COMPAQ_NC7780, TG3_PHY_ID_BCM5701 },
14948 { TG3PCI_SUBVENDOR_ID_COMPAQ,
14949 TG3PCI_SUBDEVICE_ID_COMPAQ_NC7780_2, TG3_PHY_ID_BCM5701 },
14952 { TG3PCI_SUBVENDOR_ID_IBM,
14953 TG3PCI_SUBDEVICE_ID_IBM_5703SAX2, 0 }
14956 static struct subsys_tbl_ent *tg3_lookup_by_subsys(struct tg3 *tp)
14960 for (i = 0; i < ARRAY_SIZE(subsys_id_to_phy_id); i++) {
14961 if ((subsys_id_to_phy_id[i].subsys_vendor ==
14962 tp->pdev->subsystem_vendor) &&
14963 (subsys_id_to_phy_id[i].subsys_devid ==
14964 tp->pdev->subsystem_device))
14965 return &subsys_id_to_phy_id[i];
14970 static void tg3_get_eeprom_hw_cfg(struct tg3 *tp)
14974 tp->phy_id = TG3_PHY_ID_INVALID;
14975 tp->led_ctrl = LED_CTRL_MODE_PHY_1;
14977 /* Assume an onboard device and WOL capable by default. */
14978 tg3_flag_set(tp, EEPROM_WRITE_PROT);
14979 tg3_flag_set(tp, WOL_CAP);
14981 if (tg3_asic_rev(tp) == ASIC_REV_5906) {
14982 if (!(tr32(PCIE_TRANSACTION_CFG) & PCIE_TRANS_CFG_LOM)) {
14983 tg3_flag_clear(tp, EEPROM_WRITE_PROT);
14984 tg3_flag_set(tp, IS_NIC);
14986 val = tr32(VCPU_CFGSHDW);
14987 if (val & VCPU_CFGSHDW_ASPM_DBNC)
14988 tg3_flag_set(tp, ASPM_WORKAROUND);
14989 if ((val & VCPU_CFGSHDW_WOL_ENABLE) &&
14990 (val & VCPU_CFGSHDW_WOL_MAGPKT)) {
14991 tg3_flag_set(tp, WOL_ENABLE);
14992 device_set_wakeup_enable(&tp->pdev->dev, true);
14997 tg3_read_mem(tp, NIC_SRAM_DATA_SIG, &val);
14998 if (val == NIC_SRAM_DATA_SIG_MAGIC) {
14999 u32 nic_cfg, led_cfg;
15000 u32 cfg2 = 0, cfg4 = 0, cfg5 = 0;
15001 u32 nic_phy_id, ver, eeprom_phy_id;
15002 int eeprom_phy_serdes = 0;
15004 tg3_read_mem(tp, NIC_SRAM_DATA_CFG, &nic_cfg);
15005 tp->nic_sram_data_cfg = nic_cfg;
15007 tg3_read_mem(tp, NIC_SRAM_DATA_VER, &ver);
15008 ver >>= NIC_SRAM_DATA_VER_SHIFT;
15009 if (tg3_asic_rev(tp) != ASIC_REV_5700 &&
15010 tg3_asic_rev(tp) != ASIC_REV_5701 &&
15011 tg3_asic_rev(tp) != ASIC_REV_5703 &&
15012 (ver > 0) && (ver < 0x100))
15013 tg3_read_mem(tp, NIC_SRAM_DATA_CFG_2, &cfg2);
15015 if (tg3_asic_rev(tp) == ASIC_REV_5785)
15016 tg3_read_mem(tp, NIC_SRAM_DATA_CFG_4, &cfg4);
15018 if (tg3_asic_rev(tp) == ASIC_REV_5717 ||
15019 tg3_asic_rev(tp) == ASIC_REV_5719 ||
15020 tg3_asic_rev(tp) == ASIC_REV_5720)
15021 tg3_read_mem(tp, NIC_SRAM_DATA_CFG_5, &cfg5);
15023 if ((nic_cfg & NIC_SRAM_DATA_CFG_PHY_TYPE_MASK) ==
15024 NIC_SRAM_DATA_CFG_PHY_TYPE_FIBER)
15025 eeprom_phy_serdes = 1;
15027 tg3_read_mem(tp, NIC_SRAM_DATA_PHY_ID, &nic_phy_id);
15028 if (nic_phy_id != 0) {
15029 u32 id1 = nic_phy_id & NIC_SRAM_DATA_PHY_ID1_MASK;
15030 u32 id2 = nic_phy_id & NIC_SRAM_DATA_PHY_ID2_MASK;
15032 eeprom_phy_id = (id1 >> 16) << 10;
15033 eeprom_phy_id |= (id2 & 0xfc00) << 16;
15034 eeprom_phy_id |= (id2 & 0x03ff) << 0;
15038 tp->phy_id = eeprom_phy_id;
15039 if (eeprom_phy_serdes) {
15040 if (!tg3_flag(tp, 5705_PLUS))
15041 tp->phy_flags |= TG3_PHYFLG_PHY_SERDES;
15043 tp->phy_flags |= TG3_PHYFLG_MII_SERDES;
15046 if (tg3_flag(tp, 5750_PLUS))
15047 led_cfg = cfg2 & (NIC_SRAM_DATA_CFG_LED_MODE_MASK |
15048 SHASTA_EXT_LED_MODE_MASK);
15050 led_cfg = nic_cfg & NIC_SRAM_DATA_CFG_LED_MODE_MASK;
15054 case NIC_SRAM_DATA_CFG_LED_MODE_PHY_1:
15055 tp->led_ctrl = LED_CTRL_MODE_PHY_1;
15058 case NIC_SRAM_DATA_CFG_LED_MODE_PHY_2:
15059 tp->led_ctrl = LED_CTRL_MODE_PHY_2;
15062 case NIC_SRAM_DATA_CFG_LED_MODE_MAC:
15063 tp->led_ctrl = LED_CTRL_MODE_MAC;
15065 /* Default to PHY_1_MODE if 0 (MAC_MODE) is
15066 * read on some older 5700/5701 bootcode.
15068 if (tg3_asic_rev(tp) == ASIC_REV_5700 ||
15069 tg3_asic_rev(tp) == ASIC_REV_5701)
15070 tp->led_ctrl = LED_CTRL_MODE_PHY_1;
15074 case SHASTA_EXT_LED_SHARED:
15075 tp->led_ctrl = LED_CTRL_MODE_SHARED;
15076 if (tg3_chip_rev_id(tp) != CHIPREV_ID_5750_A0 &&
15077 tg3_chip_rev_id(tp) != CHIPREV_ID_5750_A1)
15078 tp->led_ctrl |= (LED_CTRL_MODE_PHY_1 |
15079 LED_CTRL_MODE_PHY_2);
15081 if (tg3_flag(tp, 5717_PLUS) ||
15082 tg3_asic_rev(tp) == ASIC_REV_5762)
15083 tp->led_ctrl |= LED_CTRL_BLINK_RATE_OVERRIDE |
15084 LED_CTRL_BLINK_RATE_MASK;
15088 case SHASTA_EXT_LED_MAC:
15089 tp->led_ctrl = LED_CTRL_MODE_SHASTA_MAC;
15092 case SHASTA_EXT_LED_COMBO:
15093 tp->led_ctrl = LED_CTRL_MODE_COMBO;
15094 if (tg3_chip_rev_id(tp) != CHIPREV_ID_5750_A0)
15095 tp->led_ctrl |= (LED_CTRL_MODE_PHY_1 |
15096 LED_CTRL_MODE_PHY_2);
15101 if ((tg3_asic_rev(tp) == ASIC_REV_5700 ||
15102 tg3_asic_rev(tp) == ASIC_REV_5701) &&
15103 tp->pdev->subsystem_vendor == PCI_VENDOR_ID_DELL)
15104 tp->led_ctrl = LED_CTRL_MODE_PHY_2;
15106 if (tg3_chip_rev(tp) == CHIPREV_5784_AX)
15107 tp->led_ctrl = LED_CTRL_MODE_PHY_1;
15109 if (nic_cfg & NIC_SRAM_DATA_CFG_EEPROM_WP) {
15110 tg3_flag_set(tp, EEPROM_WRITE_PROT);
15111 if ((tp->pdev->subsystem_vendor ==
15112 PCI_VENDOR_ID_ARIMA) &&
15113 (tp->pdev->subsystem_device == 0x205a ||
15114 tp->pdev->subsystem_device == 0x2063))
15115 tg3_flag_clear(tp, EEPROM_WRITE_PROT);
15117 tg3_flag_clear(tp, EEPROM_WRITE_PROT);
15118 tg3_flag_set(tp, IS_NIC);
15121 if (nic_cfg & NIC_SRAM_DATA_CFG_ASF_ENABLE) {
15122 tg3_flag_set(tp, ENABLE_ASF);
15123 if (tg3_flag(tp, 5750_PLUS))
15124 tg3_flag_set(tp, ASF_NEW_HANDSHAKE);
15127 if ((nic_cfg & NIC_SRAM_DATA_CFG_APE_ENABLE) &&
15128 tg3_flag(tp, 5750_PLUS))
15129 tg3_flag_set(tp, ENABLE_APE);
15131 if (tp->phy_flags & TG3_PHYFLG_ANY_SERDES &&
15132 !(nic_cfg & NIC_SRAM_DATA_CFG_FIBER_WOL))
15133 tg3_flag_clear(tp, WOL_CAP);
15135 if (tg3_flag(tp, WOL_CAP) &&
15136 (nic_cfg & NIC_SRAM_DATA_CFG_WOL_ENABLE)) {
15137 tg3_flag_set(tp, WOL_ENABLE);
15138 device_set_wakeup_enable(&tp->pdev->dev, true);
15141 if (cfg2 & (1 << 17))
15142 tp->phy_flags |= TG3_PHYFLG_CAPACITIVE_COUPLING;
15144 /* serdes signal pre-emphasis in register 0x590 set by */
15145 /* bootcode if bit 18 is set */
15146 if (cfg2 & (1 << 18))
15147 tp->phy_flags |= TG3_PHYFLG_SERDES_PREEMPHASIS;
15149 if ((tg3_flag(tp, 57765_PLUS) ||
15150 (tg3_asic_rev(tp) == ASIC_REV_5784 &&
15151 tg3_chip_rev(tp) != CHIPREV_5784_AX)) &&
15152 (cfg2 & NIC_SRAM_DATA_CFG_2_APD_EN))
15153 tp->phy_flags |= TG3_PHYFLG_ENABLE_APD;
15155 if (tg3_flag(tp, PCI_EXPRESS)) {
15158 tg3_read_mem(tp, NIC_SRAM_DATA_CFG_3, &cfg3);
15159 if (tg3_asic_rev(tp) != ASIC_REV_5785 &&
15160 !tg3_flag(tp, 57765_PLUS) &&
15161 (cfg3 & NIC_SRAM_ASPM_DEBOUNCE))
15162 tg3_flag_set(tp, ASPM_WORKAROUND);
15163 if (cfg3 & NIC_SRAM_LNK_FLAP_AVOID)
15164 tp->phy_flags |= TG3_PHYFLG_KEEP_LINK_ON_PWRDN;
15165 if (cfg3 & NIC_SRAM_1G_ON_VAUX_OK)
15166 tp->phy_flags |= TG3_PHYFLG_1G_ON_VAUX_OK;
15169 if (cfg4 & NIC_SRAM_RGMII_INBAND_DISABLE)
15170 tg3_flag_set(tp, RGMII_INBAND_DISABLE);
15171 if (cfg4 & NIC_SRAM_RGMII_EXT_IBND_RX_EN)
15172 tg3_flag_set(tp, RGMII_EXT_IBND_RX_EN);
15173 if (cfg4 & NIC_SRAM_RGMII_EXT_IBND_TX_EN)
15174 tg3_flag_set(tp, RGMII_EXT_IBND_TX_EN);
15176 if (cfg5 & NIC_SRAM_DISABLE_1G_HALF_ADV)
15177 tp->phy_flags |= TG3_PHYFLG_DISABLE_1G_HD_ADV;
15180 if (tg3_flag(tp, WOL_CAP))
15181 device_set_wakeup_enable(&tp->pdev->dev,
15182 tg3_flag(tp, WOL_ENABLE));
15184 device_set_wakeup_capable(&tp->pdev->dev, false);
15187 static int tg3_ape_otp_read(struct tg3 *tp, u32 offset, u32 *val)
15190 u32 val2, off = offset * 8;
15192 err = tg3_nvram_lock(tp);
15196 tg3_ape_write32(tp, TG3_APE_OTP_ADDR, off | APE_OTP_ADDR_CPU_ENABLE);
15197 tg3_ape_write32(tp, TG3_APE_OTP_CTRL, APE_OTP_CTRL_PROG_EN |
15198 APE_OTP_CTRL_CMD_RD | APE_OTP_CTRL_START);
15199 tg3_ape_read32(tp, TG3_APE_OTP_CTRL);
15202 for (i = 0; i < 100; i++) {
15203 val2 = tg3_ape_read32(tp, TG3_APE_OTP_STATUS);
15204 if (val2 & APE_OTP_STATUS_CMD_DONE) {
15205 *val = tg3_ape_read32(tp, TG3_APE_OTP_RD_DATA);
15211 tg3_ape_write32(tp, TG3_APE_OTP_CTRL, 0);
15213 tg3_nvram_unlock(tp);
15214 if (val2 & APE_OTP_STATUS_CMD_DONE)
15220 static int tg3_issue_otp_command(struct tg3 *tp, u32 cmd)
15225 tw32(OTP_CTRL, cmd | OTP_CTRL_OTP_CMD_START);
15226 tw32(OTP_CTRL, cmd);
15228 /* Wait for up to 1 ms for command to execute. */
15229 for (i = 0; i < 100; i++) {
15230 val = tr32(OTP_STATUS);
15231 if (val & OTP_STATUS_CMD_DONE)
15236 return (val & OTP_STATUS_CMD_DONE) ? 0 : -EBUSY;
15239 /* Read the gphy configuration from the OTP region of the chip. The gphy
15240 * configuration is a 32-bit value that straddles the alignment boundary.
15241 * We do two 32-bit reads and then shift and merge the results.
15243 static u32 tg3_read_otp_phycfg(struct tg3 *tp)
15245 u32 bhalf_otp, thalf_otp;
15247 tw32(OTP_MODE, OTP_MODE_OTP_THRU_GRC);
15249 if (tg3_issue_otp_command(tp, OTP_CTRL_OTP_CMD_INIT))
15252 tw32(OTP_ADDRESS, OTP_ADDRESS_MAGIC1);
15254 if (tg3_issue_otp_command(tp, OTP_CTRL_OTP_CMD_READ))
15257 thalf_otp = tr32(OTP_READ_DATA);
15259 tw32(OTP_ADDRESS, OTP_ADDRESS_MAGIC2);
15261 if (tg3_issue_otp_command(tp, OTP_CTRL_OTP_CMD_READ))
15264 bhalf_otp = tr32(OTP_READ_DATA);
15266 return ((thalf_otp & 0x0000ffff) << 16) | (bhalf_otp >> 16);
15269 static void tg3_phy_init_link_config(struct tg3 *tp)
15271 u32 adv = ADVERTISED_Autoneg;
15273 if (!(tp->phy_flags & TG3_PHYFLG_10_100_ONLY)) {
15274 if (!(tp->phy_flags & TG3_PHYFLG_DISABLE_1G_HD_ADV))
15275 adv |= ADVERTISED_1000baseT_Half;
15276 adv |= ADVERTISED_1000baseT_Full;
15279 if (!(tp->phy_flags & TG3_PHYFLG_ANY_SERDES))
15280 adv |= ADVERTISED_100baseT_Half |
15281 ADVERTISED_100baseT_Full |
15282 ADVERTISED_10baseT_Half |
15283 ADVERTISED_10baseT_Full |
15286 adv |= ADVERTISED_FIBRE;
15288 tp->link_config.advertising = adv;
15289 tp->link_config.speed = SPEED_UNKNOWN;
15290 tp->link_config.duplex = DUPLEX_UNKNOWN;
15291 tp->link_config.autoneg = AUTONEG_ENABLE;
15292 tp->link_config.active_speed = SPEED_UNKNOWN;
15293 tp->link_config.active_duplex = DUPLEX_UNKNOWN;
15298 static int tg3_phy_probe(struct tg3 *tp)
15300 u32 hw_phy_id_1, hw_phy_id_2;
15301 u32 hw_phy_id, hw_phy_id_masked;
15304 /* flow control autonegotiation is default behavior */
15305 tg3_flag_set(tp, PAUSE_AUTONEG);
15306 tp->link_config.flowctrl = FLOW_CTRL_TX | FLOW_CTRL_RX;
15308 if (tg3_flag(tp, ENABLE_APE)) {
15309 switch (tp->pci_fn) {
15311 tp->phy_ape_lock = TG3_APE_LOCK_PHY0;
15314 tp->phy_ape_lock = TG3_APE_LOCK_PHY1;
15317 tp->phy_ape_lock = TG3_APE_LOCK_PHY2;
15320 tp->phy_ape_lock = TG3_APE_LOCK_PHY3;
15325 if (!tg3_flag(tp, ENABLE_ASF) &&
15326 !(tp->phy_flags & TG3_PHYFLG_ANY_SERDES) &&
15327 !(tp->phy_flags & TG3_PHYFLG_10_100_ONLY))
15328 tp->phy_flags &= ~(TG3_PHYFLG_1G_ON_VAUX_OK |
15329 TG3_PHYFLG_KEEP_LINK_ON_PWRDN);
15331 if (tg3_flag(tp, USE_PHYLIB))
15332 return tg3_phy_init(tp);
15334 /* Reading the PHY ID register can conflict with ASF
15335 * firmware access to the PHY hardware.
15338 if (tg3_flag(tp, ENABLE_ASF) || tg3_flag(tp, ENABLE_APE)) {
15339 hw_phy_id = hw_phy_id_masked = TG3_PHY_ID_INVALID;
15341 /* Now read the physical PHY_ID from the chip and verify
15342 * that it is sane. If it doesn't look good, we fall back
15343 * to either the hard-coded table based PHY_ID and failing
15344 * that the value found in the eeprom area.
15346 err |= tg3_readphy(tp, MII_PHYSID1, &hw_phy_id_1);
15347 err |= tg3_readphy(tp, MII_PHYSID2, &hw_phy_id_2);
15349 hw_phy_id = (hw_phy_id_1 & 0xffff) << 10;
15350 hw_phy_id |= (hw_phy_id_2 & 0xfc00) << 16;
15351 hw_phy_id |= (hw_phy_id_2 & 0x03ff) << 0;
15353 hw_phy_id_masked = hw_phy_id & TG3_PHY_ID_MASK;
15356 if (!err && TG3_KNOWN_PHY_ID(hw_phy_id_masked)) {
15357 tp->phy_id = hw_phy_id;
15358 if (hw_phy_id_masked == TG3_PHY_ID_BCM8002)
15359 tp->phy_flags |= TG3_PHYFLG_PHY_SERDES;
15361 tp->phy_flags &= ~TG3_PHYFLG_PHY_SERDES;
15363 if (tp->phy_id != TG3_PHY_ID_INVALID) {
15364 /* Do nothing, phy ID already set up in
15365 * tg3_get_eeprom_hw_cfg().
15368 struct subsys_tbl_ent *p;
15370 /* No eeprom signature? Try the hardcoded
15371 * subsys device table.
15373 p = tg3_lookup_by_subsys(tp);
15375 tp->phy_id = p->phy_id;
15376 } else if (!tg3_flag(tp, IS_SSB_CORE)) {
15377 /* For now we saw the IDs 0xbc050cd0,
15378 * 0xbc050f80 and 0xbc050c30 on devices
15379 * connected to an BCM4785 and there are
15380 * probably more. Just assume that the phy is
15381 * supported when it is connected to a SSB core
15388 tp->phy_id == TG3_PHY_ID_BCM8002)
15389 tp->phy_flags |= TG3_PHYFLG_PHY_SERDES;
15393 if (!(tp->phy_flags & TG3_PHYFLG_ANY_SERDES) &&
15394 (tg3_asic_rev(tp) == ASIC_REV_5719 ||
15395 tg3_asic_rev(tp) == ASIC_REV_5720 ||
15396 tg3_asic_rev(tp) == ASIC_REV_57766 ||
15397 tg3_asic_rev(tp) == ASIC_REV_5762 ||
15398 (tg3_asic_rev(tp) == ASIC_REV_5717 &&
15399 tg3_chip_rev_id(tp) != CHIPREV_ID_5717_A0) ||
15400 (tg3_asic_rev(tp) == ASIC_REV_57765 &&
15401 tg3_chip_rev_id(tp) != CHIPREV_ID_57765_A0))) {
15402 tp->phy_flags |= TG3_PHYFLG_EEE_CAP;
15404 tp->eee.supported = SUPPORTED_100baseT_Full |
15405 SUPPORTED_1000baseT_Full;
15406 tp->eee.advertised = ADVERTISED_100baseT_Full |
15407 ADVERTISED_1000baseT_Full;
15408 tp->eee.eee_enabled = 1;
15409 tp->eee.tx_lpi_enabled = 1;
15410 tp->eee.tx_lpi_timer = TG3_CPMU_DBTMR1_LNKIDLE_2047US;
15413 tg3_phy_init_link_config(tp);
15415 if (!(tp->phy_flags & TG3_PHYFLG_KEEP_LINK_ON_PWRDN) &&
15416 !(tp->phy_flags & TG3_PHYFLG_ANY_SERDES) &&
15417 !tg3_flag(tp, ENABLE_APE) &&
15418 !tg3_flag(tp, ENABLE_ASF)) {
15421 tg3_readphy(tp, MII_BMSR, &bmsr);
15422 if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
15423 (bmsr & BMSR_LSTATUS))
15424 goto skip_phy_reset;
15426 err = tg3_phy_reset(tp);
15430 tg3_phy_set_wirespeed(tp);
15432 if (!tg3_phy_copper_an_config_ok(tp, &dummy)) {
15433 tg3_phy_autoneg_cfg(tp, tp->link_config.advertising,
15434 tp->link_config.flowctrl);
15436 tg3_writephy(tp, MII_BMCR,
15437 BMCR_ANENABLE | BMCR_ANRESTART);
15442 if ((tp->phy_id & TG3_PHY_ID_MASK) == TG3_PHY_ID_BCM5401) {
15443 err = tg3_init_5401phy_dsp(tp);
15447 err = tg3_init_5401phy_dsp(tp);
15453 static void tg3_read_vpd(struct tg3 *tp)
15456 unsigned int block_end, rosize, len;
15460 vpd_data = (u8 *)tg3_vpd_readblock(tp, &vpdlen);
15464 i = pci_vpd_find_tag(vpd_data, 0, vpdlen, PCI_VPD_LRDT_RO_DATA);
15466 goto out_not_found;
15468 rosize = pci_vpd_lrdt_size(&vpd_data[i]);
15469 block_end = i + PCI_VPD_LRDT_TAG_SIZE + rosize;
15470 i += PCI_VPD_LRDT_TAG_SIZE;
15472 if (block_end > vpdlen)
15473 goto out_not_found;
15475 j = pci_vpd_find_info_keyword(vpd_data, i, rosize,
15476 PCI_VPD_RO_KEYWORD_MFR_ID);
15478 len = pci_vpd_info_field_size(&vpd_data[j]);
15480 j += PCI_VPD_INFO_FLD_HDR_SIZE;
15481 if (j + len > block_end || len != 4 ||
15482 memcmp(&vpd_data[j], "1028", 4))
15485 j = pci_vpd_find_info_keyword(vpd_data, i, rosize,
15486 PCI_VPD_RO_KEYWORD_VENDOR0);
15490 len = pci_vpd_info_field_size(&vpd_data[j]);
15492 j += PCI_VPD_INFO_FLD_HDR_SIZE;
15493 if (j + len > block_end)
15496 if (len >= sizeof(tp->fw_ver))
15497 len = sizeof(tp->fw_ver) - 1;
15498 memset(tp->fw_ver, 0, sizeof(tp->fw_ver));
15499 snprintf(tp->fw_ver, sizeof(tp->fw_ver), "%.*s bc ", len,
15504 i = pci_vpd_find_info_keyword(vpd_data, i, rosize,
15505 PCI_VPD_RO_KEYWORD_PARTNO);
15507 goto out_not_found;
15509 len = pci_vpd_info_field_size(&vpd_data[i]);
15511 i += PCI_VPD_INFO_FLD_HDR_SIZE;
15512 if (len > TG3_BPN_SIZE ||
15513 (len + i) > vpdlen)
15514 goto out_not_found;
15516 memcpy(tp->board_part_number, &vpd_data[i], len);
15520 if (tp->board_part_number[0])
15524 if (tg3_asic_rev(tp) == ASIC_REV_5717) {
15525 if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_5717 ||
15526 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5717_C)
15527 strcpy(tp->board_part_number, "BCM5717");
15528 else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_5718)
15529 strcpy(tp->board_part_number, "BCM5718");
15532 } else if (tg3_asic_rev(tp) == ASIC_REV_57780) {
15533 if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57780)
15534 strcpy(tp->board_part_number, "BCM57780");
15535 else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57760)
15536 strcpy(tp->board_part_number, "BCM57760");
15537 else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57790)
15538 strcpy(tp->board_part_number, "BCM57790");
15539 else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57788)
15540 strcpy(tp->board_part_number, "BCM57788");
15543 } else if (tg3_asic_rev(tp) == ASIC_REV_57765) {
15544 if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57761)
15545 strcpy(tp->board_part_number, "BCM57761");
15546 else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57765)
15547 strcpy(tp->board_part_number, "BCM57765");
15548 else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57781)
15549 strcpy(tp->board_part_number, "BCM57781");
15550 else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57785)
15551 strcpy(tp->board_part_number, "BCM57785");
15552 else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57791)
15553 strcpy(tp->board_part_number, "BCM57791");
15554 else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57795)
15555 strcpy(tp->board_part_number, "BCM57795");
15558 } else if (tg3_asic_rev(tp) == ASIC_REV_57766) {
15559 if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57762)
15560 strcpy(tp->board_part_number, "BCM57762");
15561 else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57766)
15562 strcpy(tp->board_part_number, "BCM57766");
15563 else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57782)
15564 strcpy(tp->board_part_number, "BCM57782");
15565 else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57786)
15566 strcpy(tp->board_part_number, "BCM57786");
15569 } else if (tg3_asic_rev(tp) == ASIC_REV_5906) {
15570 strcpy(tp->board_part_number, "BCM95906");
15573 strcpy(tp->board_part_number, "none");
15577 static int tg3_fw_img_is_valid(struct tg3 *tp, u32 offset)
15581 if (tg3_nvram_read(tp, offset, &val) ||
15582 (val & 0xfc000000) != 0x0c000000 ||
15583 tg3_nvram_read(tp, offset + 4, &val) ||
15590 static void tg3_read_bc_ver(struct tg3 *tp)
15592 u32 val, offset, start, ver_offset;
15594 bool newver = false;
15596 if (tg3_nvram_read(tp, 0xc, &offset) ||
15597 tg3_nvram_read(tp, 0x4, &start))
15600 offset = tg3_nvram_logical_addr(tp, offset);
15602 if (tg3_nvram_read(tp, offset, &val))
15605 if ((val & 0xfc000000) == 0x0c000000) {
15606 if (tg3_nvram_read(tp, offset + 4, &val))
15613 dst_off = strlen(tp->fw_ver);
15616 if (TG3_VER_SIZE - dst_off < 16 ||
15617 tg3_nvram_read(tp, offset + 8, &ver_offset))
15620 offset = offset + ver_offset - start;
15621 for (i = 0; i < 16; i += 4) {
15623 if (tg3_nvram_read_be32(tp, offset + i, &v))
15626 memcpy(tp->fw_ver + dst_off + i, &v, sizeof(v));
15631 if (tg3_nvram_read(tp, TG3_NVM_PTREV_BCVER, &ver_offset))
15634 major = (ver_offset & TG3_NVM_BCVER_MAJMSK) >>
15635 TG3_NVM_BCVER_MAJSFT;
15636 minor = ver_offset & TG3_NVM_BCVER_MINMSK;
15637 snprintf(&tp->fw_ver[dst_off], TG3_VER_SIZE - dst_off,
15638 "v%d.%02d", major, minor);
15642 static void tg3_read_hwsb_ver(struct tg3 *tp)
15644 u32 val, major, minor;
15646 /* Use native endian representation */
15647 if (tg3_nvram_read(tp, TG3_NVM_HWSB_CFG1, &val))
15650 major = (val & TG3_NVM_HWSB_CFG1_MAJMSK) >>
15651 TG3_NVM_HWSB_CFG1_MAJSFT;
15652 minor = (val & TG3_NVM_HWSB_CFG1_MINMSK) >>
15653 TG3_NVM_HWSB_CFG1_MINSFT;
15655 snprintf(&tp->fw_ver[0], 32, "sb v%d.%02d", major, minor);
15658 static void tg3_read_sb_ver(struct tg3 *tp, u32 val)
15660 u32 offset, major, minor, build;
15662 strncat(tp->fw_ver, "sb", TG3_VER_SIZE - strlen(tp->fw_ver) - 1);
15664 if ((val & TG3_EEPROM_SB_FORMAT_MASK) != TG3_EEPROM_SB_FORMAT_1)
15667 switch (val & TG3_EEPROM_SB_REVISION_MASK) {
15668 case TG3_EEPROM_SB_REVISION_0:
15669 offset = TG3_EEPROM_SB_F1R0_EDH_OFF;
15671 case TG3_EEPROM_SB_REVISION_2:
15672 offset = TG3_EEPROM_SB_F1R2_EDH_OFF;
15674 case TG3_EEPROM_SB_REVISION_3:
15675 offset = TG3_EEPROM_SB_F1R3_EDH_OFF;
15677 case TG3_EEPROM_SB_REVISION_4:
15678 offset = TG3_EEPROM_SB_F1R4_EDH_OFF;
15680 case TG3_EEPROM_SB_REVISION_5:
15681 offset = TG3_EEPROM_SB_F1R5_EDH_OFF;
15683 case TG3_EEPROM_SB_REVISION_6:
15684 offset = TG3_EEPROM_SB_F1R6_EDH_OFF;
15690 if (tg3_nvram_read(tp, offset, &val))
15693 build = (val & TG3_EEPROM_SB_EDH_BLD_MASK) >>
15694 TG3_EEPROM_SB_EDH_BLD_SHFT;
15695 major = (val & TG3_EEPROM_SB_EDH_MAJ_MASK) >>
15696 TG3_EEPROM_SB_EDH_MAJ_SHFT;
15697 minor = val & TG3_EEPROM_SB_EDH_MIN_MASK;
15699 if (minor > 99 || build > 26)
15702 offset = strlen(tp->fw_ver);
15703 snprintf(&tp->fw_ver[offset], TG3_VER_SIZE - offset,
15704 " v%d.%02d", major, minor);
15707 offset = strlen(tp->fw_ver);
15708 if (offset < TG3_VER_SIZE - 1)
15709 tp->fw_ver[offset] = 'a' + build - 1;
15713 static void tg3_read_mgmtfw_ver(struct tg3 *tp)
15715 u32 val, offset, start;
15718 for (offset = TG3_NVM_DIR_START;
15719 offset < TG3_NVM_DIR_END;
15720 offset += TG3_NVM_DIRENT_SIZE) {
15721 if (tg3_nvram_read(tp, offset, &val))
15724 if ((val >> TG3_NVM_DIRTYPE_SHIFT) == TG3_NVM_DIRTYPE_ASFINI)
15728 if (offset == TG3_NVM_DIR_END)
15731 if (!tg3_flag(tp, 5705_PLUS))
15732 start = 0x08000000;
15733 else if (tg3_nvram_read(tp, offset - 4, &start))
15736 if (tg3_nvram_read(tp, offset + 4, &offset) ||
15737 !tg3_fw_img_is_valid(tp, offset) ||
15738 tg3_nvram_read(tp, offset + 8, &val))
15741 offset += val - start;
15743 vlen = strlen(tp->fw_ver);
15745 tp->fw_ver[vlen++] = ',';
15746 tp->fw_ver[vlen++] = ' ';
15748 for (i = 0; i < 4; i++) {
15750 if (tg3_nvram_read_be32(tp, offset, &v))
15753 offset += sizeof(v);
15755 if (vlen > TG3_VER_SIZE - sizeof(v)) {
15756 memcpy(&tp->fw_ver[vlen], &v, TG3_VER_SIZE - vlen);
15760 memcpy(&tp->fw_ver[vlen], &v, sizeof(v));
15765 static void tg3_probe_ncsi(struct tg3 *tp)
15769 apedata = tg3_ape_read32(tp, TG3_APE_SEG_SIG);
15770 if (apedata != APE_SEG_SIG_MAGIC)
15773 apedata = tg3_ape_read32(tp, TG3_APE_FW_STATUS);
15774 if (!(apedata & APE_FW_STATUS_READY))
15777 if (tg3_ape_read32(tp, TG3_APE_FW_FEATURES) & TG3_APE_FW_FEATURE_NCSI)
15778 tg3_flag_set(tp, APE_HAS_NCSI);
15781 static void tg3_read_dash_ver(struct tg3 *tp)
15787 apedata = tg3_ape_read32(tp, TG3_APE_FW_VERSION);
15789 if (tg3_flag(tp, APE_HAS_NCSI))
15791 else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_5725)
15796 vlen = strlen(tp->fw_ver);
15798 snprintf(&tp->fw_ver[vlen], TG3_VER_SIZE - vlen, " %s v%d.%d.%d.%d",
15800 (apedata & APE_FW_VERSION_MAJMSK) >> APE_FW_VERSION_MAJSFT,
15801 (apedata & APE_FW_VERSION_MINMSK) >> APE_FW_VERSION_MINSFT,
15802 (apedata & APE_FW_VERSION_REVMSK) >> APE_FW_VERSION_REVSFT,
15803 (apedata & APE_FW_VERSION_BLDMSK));
15806 static void tg3_read_otp_ver(struct tg3 *tp)
15810 if (tg3_asic_rev(tp) != ASIC_REV_5762)
15813 if (!tg3_ape_otp_read(tp, OTP_ADDRESS_MAGIC0, &val) &&
15814 !tg3_ape_otp_read(tp, OTP_ADDRESS_MAGIC0 + 4, &val2) &&
15815 TG3_OTP_MAGIC0_VALID(val)) {
15816 u64 val64 = (u64) val << 32 | val2;
15820 for (i = 0; i < 7; i++) {
15821 if ((val64 & 0xff) == 0)
15823 ver = val64 & 0xff;
15826 vlen = strlen(tp->fw_ver);
15827 snprintf(&tp->fw_ver[vlen], TG3_VER_SIZE - vlen, " .%02d", ver);
15831 static void tg3_read_fw_ver(struct tg3 *tp)
15834 bool vpd_vers = false;
15836 if (tp->fw_ver[0] != 0)
15839 if (tg3_flag(tp, NO_NVRAM)) {
15840 strcat(tp->fw_ver, "sb");
15841 tg3_read_otp_ver(tp);
15845 if (tg3_nvram_read(tp, 0, &val))
15848 if (val == TG3_EEPROM_MAGIC)
15849 tg3_read_bc_ver(tp);
15850 else if ((val & TG3_EEPROM_MAGIC_FW_MSK) == TG3_EEPROM_MAGIC_FW)
15851 tg3_read_sb_ver(tp, val);
15852 else if ((val & TG3_EEPROM_MAGIC_HW_MSK) == TG3_EEPROM_MAGIC_HW)
15853 tg3_read_hwsb_ver(tp);
15855 if (tg3_flag(tp, ENABLE_ASF)) {
15856 if (tg3_flag(tp, ENABLE_APE)) {
15857 tg3_probe_ncsi(tp);
15859 tg3_read_dash_ver(tp);
15860 } else if (!vpd_vers) {
15861 tg3_read_mgmtfw_ver(tp);
15865 tp->fw_ver[TG3_VER_SIZE - 1] = 0;
15868 static inline u32 tg3_rx_ret_ring_size(struct tg3 *tp)
15870 if (tg3_flag(tp, LRG_PROD_RING_CAP))
15871 return TG3_RX_RET_MAX_SIZE_5717;
15872 else if (tg3_flag(tp, JUMBO_CAPABLE) && !tg3_flag(tp, 5780_CLASS))
15873 return TG3_RX_RET_MAX_SIZE_5700;
15875 return TG3_RX_RET_MAX_SIZE_5705;
15878 static DEFINE_PCI_DEVICE_TABLE(tg3_write_reorder_chipsets) = {
15879 { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_FE_GATE_700C) },
15880 { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8131_BRIDGE) },
15881 { PCI_DEVICE(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8385_0) },
15885 static struct pci_dev *tg3_find_peer(struct tg3 *tp)
15887 struct pci_dev *peer;
15888 unsigned int func, devnr = tp->pdev->devfn & ~7;
15890 for (func = 0; func < 8; func++) {
15891 peer = pci_get_slot(tp->pdev->bus, devnr | func);
15892 if (peer && peer != tp->pdev)
15896 /* 5704 can be configured in single-port mode, set peer to
15897 * tp->pdev in that case.
15905 * We don't need to keep the refcount elevated; there's no way
15906 * to remove one half of this device without removing the other
15913 static void tg3_detect_asic_rev(struct tg3 *tp, u32 misc_ctrl_reg)
15915 tp->pci_chip_rev_id = misc_ctrl_reg >> MISC_HOST_CTRL_CHIPREV_SHIFT;
15916 if (tg3_asic_rev(tp) == ASIC_REV_USE_PROD_ID_REG) {
15919 /* All devices that use the alternate
15920 * ASIC REV location have a CPMU.
15922 tg3_flag_set(tp, CPMU_PRESENT);
15924 if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_5717 ||
15925 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5717_C ||
15926 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5718 ||
15927 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5719 ||
15928 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5720 ||
15929 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57767 ||
15930 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57764 ||
15931 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5762 ||
15932 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5725 ||
15933 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5727 ||
15934 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57787)
15935 reg = TG3PCI_GEN2_PRODID_ASICREV;
15936 else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57781 ||
15937 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57785 ||
15938 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57761 ||
15939 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57765 ||
15940 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57791 ||
15941 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57795 ||
15942 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57762 ||
15943 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57766 ||
15944 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57782 ||
15945 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57786)
15946 reg = TG3PCI_GEN15_PRODID_ASICREV;
15948 reg = TG3PCI_PRODID_ASICREV;
15950 pci_read_config_dword(tp->pdev, reg, &tp->pci_chip_rev_id);
15953 /* Wrong chip ID in 5752 A0. This code can be removed later
15954 * as A0 is not in production.
15956 if (tg3_chip_rev_id(tp) == CHIPREV_ID_5752_A0_HW)
15957 tp->pci_chip_rev_id = CHIPREV_ID_5752_A0;
15959 if (tg3_chip_rev_id(tp) == CHIPREV_ID_5717_C0)
15960 tp->pci_chip_rev_id = CHIPREV_ID_5720_A0;
15962 if (tg3_asic_rev(tp) == ASIC_REV_5717 ||
15963 tg3_asic_rev(tp) == ASIC_REV_5719 ||
15964 tg3_asic_rev(tp) == ASIC_REV_5720)
15965 tg3_flag_set(tp, 5717_PLUS);
15967 if (tg3_asic_rev(tp) == ASIC_REV_57765 ||
15968 tg3_asic_rev(tp) == ASIC_REV_57766)
15969 tg3_flag_set(tp, 57765_CLASS);
15971 if (tg3_flag(tp, 57765_CLASS) || tg3_flag(tp, 5717_PLUS) ||
15972 tg3_asic_rev(tp) == ASIC_REV_5762)
15973 tg3_flag_set(tp, 57765_PLUS);
15975 /* Intentionally exclude ASIC_REV_5906 */
15976 if (tg3_asic_rev(tp) == ASIC_REV_5755 ||
15977 tg3_asic_rev(tp) == ASIC_REV_5787 ||
15978 tg3_asic_rev(tp) == ASIC_REV_5784 ||
15979 tg3_asic_rev(tp) == ASIC_REV_5761 ||
15980 tg3_asic_rev(tp) == ASIC_REV_5785 ||
15981 tg3_asic_rev(tp) == ASIC_REV_57780 ||
15982 tg3_flag(tp, 57765_PLUS))
15983 tg3_flag_set(tp, 5755_PLUS);
15985 if (tg3_asic_rev(tp) == ASIC_REV_5780 ||
15986 tg3_asic_rev(tp) == ASIC_REV_5714)
15987 tg3_flag_set(tp, 5780_CLASS);
15989 if (tg3_asic_rev(tp) == ASIC_REV_5750 ||
15990 tg3_asic_rev(tp) == ASIC_REV_5752 ||
15991 tg3_asic_rev(tp) == ASIC_REV_5906 ||
15992 tg3_flag(tp, 5755_PLUS) ||
15993 tg3_flag(tp, 5780_CLASS))
15994 tg3_flag_set(tp, 5750_PLUS);
15996 if (tg3_asic_rev(tp) == ASIC_REV_5705 ||
15997 tg3_flag(tp, 5750_PLUS))
15998 tg3_flag_set(tp, 5705_PLUS);
16001 static bool tg3_10_100_only_device(struct tg3 *tp,
16002 const struct pci_device_id *ent)
16004 u32 grc_misc_cfg = tr32(GRC_MISC_CFG) & GRC_MISC_CFG_BOARD_ID_MASK;
16006 if ((tg3_asic_rev(tp) == ASIC_REV_5703 &&
16007 (grc_misc_cfg == 0x8000 || grc_misc_cfg == 0x4000)) ||
16008 (tp->phy_flags & TG3_PHYFLG_IS_FET))
16011 if (ent->driver_data & TG3_DRV_DATA_FLAG_10_100_ONLY) {
16012 if (tg3_asic_rev(tp) == ASIC_REV_5705) {
16013 if (ent->driver_data & TG3_DRV_DATA_FLAG_5705_10_100)
16023 static int tg3_get_invariants(struct tg3 *tp, const struct pci_device_id *ent)
16026 u32 pci_state_reg, grc_misc_cfg;
16031 /* Force memory write invalidate off. If we leave it on,
16032 * then on 5700_BX chips we have to enable a workaround.
16033 * The workaround is to set the TG3PCI_DMA_RW_CTRL boundary
16034 * to match the cacheline size. The Broadcom driver have this
16035 * workaround but turns MWI off all the times so never uses
16036 * it. This seems to suggest that the workaround is insufficient.
16038 pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd);
16039 pci_cmd &= ~PCI_COMMAND_INVALIDATE;
16040 pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd);
16042 /* Important! -- Make sure register accesses are byteswapped
16043 * correctly. Also, for those chips that require it, make
16044 * sure that indirect register accesses are enabled before
16045 * the first operation.
16047 pci_read_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
16049 tp->misc_host_ctrl |= (misc_ctrl_reg &
16050 MISC_HOST_CTRL_CHIPREV);
16051 pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
16052 tp->misc_host_ctrl);
16054 tg3_detect_asic_rev(tp, misc_ctrl_reg);
16056 /* If we have 5702/03 A1 or A2 on certain ICH chipsets,
16057 * we need to disable memory and use config. cycles
16058 * only to access all registers. The 5702/03 chips
16059 * can mistakenly decode the special cycles from the
16060 * ICH chipsets as memory write cycles, causing corruption
16061 * of register and memory space. Only certain ICH bridges
16062 * will drive special cycles with non-zero data during the
16063 * address phase which can fall within the 5703's address
16064 * range. This is not an ICH bug as the PCI spec allows
16065 * non-zero address during special cycles. However, only
16066 * these ICH bridges are known to drive non-zero addresses
16067 * during special cycles.
16069 * Since special cycles do not cross PCI bridges, we only
16070 * enable this workaround if the 5703 is on the secondary
16071 * bus of these ICH bridges.
16073 if ((tg3_chip_rev_id(tp) == CHIPREV_ID_5703_A1) ||
16074 (tg3_chip_rev_id(tp) == CHIPREV_ID_5703_A2)) {
16075 static struct tg3_dev_id {
16079 } ich_chipsets[] = {
16080 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AA_8,
16082 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AB_8,
16084 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_11,
16086 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_6,
16090 struct tg3_dev_id *pci_id = &ich_chipsets[0];
16091 struct pci_dev *bridge = NULL;
16093 while (pci_id->vendor != 0) {
16094 bridge = pci_get_device(pci_id->vendor, pci_id->device,
16100 if (pci_id->rev != PCI_ANY_ID) {
16101 if (bridge->revision > pci_id->rev)
16104 if (bridge->subordinate &&
16105 (bridge->subordinate->number ==
16106 tp->pdev->bus->number)) {
16107 tg3_flag_set(tp, ICH_WORKAROUND);
16108 pci_dev_put(bridge);
16114 if (tg3_asic_rev(tp) == ASIC_REV_5701) {
16115 static struct tg3_dev_id {
16118 } bridge_chipsets[] = {
16119 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_0 },
16120 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_1 },
16123 struct tg3_dev_id *pci_id = &bridge_chipsets[0];
16124 struct pci_dev *bridge = NULL;
16126 while (pci_id->vendor != 0) {
16127 bridge = pci_get_device(pci_id->vendor,
16134 if (bridge->subordinate &&
16135 (bridge->subordinate->number <=
16136 tp->pdev->bus->number) &&
16137 (bridge->subordinate->busn_res.end >=
16138 tp->pdev->bus->number)) {
16139 tg3_flag_set(tp, 5701_DMA_BUG);
16140 pci_dev_put(bridge);
16146 /* The EPB bridge inside 5714, 5715, and 5780 cannot support
16147 * DMA addresses > 40-bit. This bridge may have other additional
16148 * 57xx devices behind it in some 4-port NIC designs for example.
16149 * Any tg3 device found behind the bridge will also need the 40-bit
16152 if (tg3_flag(tp, 5780_CLASS)) {
16153 tg3_flag_set(tp, 40BIT_DMA_BUG);
16154 tp->msi_cap = tp->pdev->msi_cap;
16156 struct pci_dev *bridge = NULL;
16159 bridge = pci_get_device(PCI_VENDOR_ID_SERVERWORKS,
16160 PCI_DEVICE_ID_SERVERWORKS_EPB,
16162 if (bridge && bridge->subordinate &&
16163 (bridge->subordinate->number <=
16164 tp->pdev->bus->number) &&
16165 (bridge->subordinate->busn_res.end >=
16166 tp->pdev->bus->number)) {
16167 tg3_flag_set(tp, 40BIT_DMA_BUG);
16168 pci_dev_put(bridge);
16174 if (tg3_asic_rev(tp) == ASIC_REV_5704 ||
16175 tg3_asic_rev(tp) == ASIC_REV_5714)
16176 tp->pdev_peer = tg3_find_peer(tp);
16178 /* Determine TSO capabilities */
16179 if (tg3_chip_rev_id(tp) == CHIPREV_ID_5719_A0)
16180 ; /* Do nothing. HW bug. */
16181 else if (tg3_flag(tp, 57765_PLUS))
16182 tg3_flag_set(tp, HW_TSO_3);
16183 else if (tg3_flag(tp, 5755_PLUS) ||
16184 tg3_asic_rev(tp) == ASIC_REV_5906)
16185 tg3_flag_set(tp, HW_TSO_2);
16186 else if (tg3_flag(tp, 5750_PLUS)) {
16187 tg3_flag_set(tp, HW_TSO_1);
16188 tg3_flag_set(tp, TSO_BUG);
16189 if (tg3_asic_rev(tp) == ASIC_REV_5750 &&
16190 tg3_chip_rev_id(tp) >= CHIPREV_ID_5750_C2)
16191 tg3_flag_clear(tp, TSO_BUG);
16192 } else if (tg3_asic_rev(tp) != ASIC_REV_5700 &&
16193 tg3_asic_rev(tp) != ASIC_REV_5701 &&
16194 tg3_chip_rev_id(tp) != CHIPREV_ID_5705_A0) {
16195 tg3_flag_set(tp, FW_TSO);
16196 tg3_flag_set(tp, TSO_BUG);
16197 if (tg3_asic_rev(tp) == ASIC_REV_5705)
16198 tp->fw_needed = FIRMWARE_TG3TSO5;
16200 tp->fw_needed = FIRMWARE_TG3TSO;
16203 /* Selectively allow TSO based on operating conditions */
16204 if (tg3_flag(tp, HW_TSO_1) ||
16205 tg3_flag(tp, HW_TSO_2) ||
16206 tg3_flag(tp, HW_TSO_3) ||
16207 tg3_flag(tp, FW_TSO)) {
16208 /* For firmware TSO, assume ASF is disabled.
16209 * We'll disable TSO later if we discover ASF
16210 * is enabled in tg3_get_eeprom_hw_cfg().
16212 tg3_flag_set(tp, TSO_CAPABLE);
16214 tg3_flag_clear(tp, TSO_CAPABLE);
16215 tg3_flag_clear(tp, TSO_BUG);
16216 tp->fw_needed = NULL;
16219 if (tg3_chip_rev_id(tp) == CHIPREV_ID_5701_A0)
16220 tp->fw_needed = FIRMWARE_TG3;
16222 if (tg3_asic_rev(tp) == ASIC_REV_57766)
16223 tp->fw_needed = FIRMWARE_TG357766;
16227 if (tg3_flag(tp, 5750_PLUS)) {
16228 tg3_flag_set(tp, SUPPORT_MSI);
16229 if (tg3_chip_rev(tp) == CHIPREV_5750_AX ||
16230 tg3_chip_rev(tp) == CHIPREV_5750_BX ||
16231 (tg3_asic_rev(tp) == ASIC_REV_5714 &&
16232 tg3_chip_rev_id(tp) <= CHIPREV_ID_5714_A2 &&
16233 tp->pdev_peer == tp->pdev))
16234 tg3_flag_clear(tp, SUPPORT_MSI);
16236 if (tg3_flag(tp, 5755_PLUS) ||
16237 tg3_asic_rev(tp) == ASIC_REV_5906) {
16238 tg3_flag_set(tp, 1SHOT_MSI);
16241 if (tg3_flag(tp, 57765_PLUS)) {
16242 tg3_flag_set(tp, SUPPORT_MSIX);
16243 tp->irq_max = TG3_IRQ_MAX_VECS;
16249 if (tp->irq_max > 1) {
16250 tp->rxq_max = TG3_RSS_MAX_NUM_QS;
16251 tg3_rss_init_dflt_indir_tbl(tp, TG3_RSS_MAX_NUM_QS);
16253 if (tg3_asic_rev(tp) == ASIC_REV_5719 ||
16254 tg3_asic_rev(tp) == ASIC_REV_5720)
16255 tp->txq_max = tp->irq_max - 1;
16258 if (tg3_flag(tp, 5755_PLUS) ||
16259 tg3_asic_rev(tp) == ASIC_REV_5906)
16260 tg3_flag_set(tp, SHORT_DMA_BUG);
16262 if (tg3_asic_rev(tp) == ASIC_REV_5719)
16263 tp->dma_limit = TG3_TX_BD_DMA_MAX_4K;
16265 if (tg3_asic_rev(tp) == ASIC_REV_5717 ||
16266 tg3_asic_rev(tp) == ASIC_REV_5719 ||
16267 tg3_asic_rev(tp) == ASIC_REV_5720 ||
16268 tg3_asic_rev(tp) == ASIC_REV_5762)
16269 tg3_flag_set(tp, LRG_PROD_RING_CAP);
16271 if (tg3_flag(tp, 57765_PLUS) &&
16272 tg3_chip_rev_id(tp) != CHIPREV_ID_5719_A0)
16273 tg3_flag_set(tp, USE_JUMBO_BDFLAG);
16275 if (!tg3_flag(tp, 5705_PLUS) ||
16276 tg3_flag(tp, 5780_CLASS) ||
16277 tg3_flag(tp, USE_JUMBO_BDFLAG))
16278 tg3_flag_set(tp, JUMBO_CAPABLE);
16280 pci_read_config_dword(tp->pdev, TG3PCI_PCISTATE,
16283 if (pci_is_pcie(tp->pdev)) {
16286 tg3_flag_set(tp, PCI_EXPRESS);
16288 pcie_capability_read_word(tp->pdev, PCI_EXP_LNKCTL, &lnkctl);
16289 if (lnkctl & PCI_EXP_LNKCTL_CLKREQ_EN) {
16290 if (tg3_asic_rev(tp) == ASIC_REV_5906) {
16291 tg3_flag_clear(tp, HW_TSO_2);
16292 tg3_flag_clear(tp, TSO_CAPABLE);
16294 if (tg3_asic_rev(tp) == ASIC_REV_5784 ||
16295 tg3_asic_rev(tp) == ASIC_REV_5761 ||
16296 tg3_chip_rev_id(tp) == CHIPREV_ID_57780_A0 ||
16297 tg3_chip_rev_id(tp) == CHIPREV_ID_57780_A1)
16298 tg3_flag_set(tp, CLKREQ_BUG);
16299 } else if (tg3_chip_rev_id(tp) == CHIPREV_ID_5717_A0) {
16300 tg3_flag_set(tp, L1PLLPD_EN);
16302 } else if (tg3_asic_rev(tp) == ASIC_REV_5785) {
16303 /* BCM5785 devices are effectively PCIe devices, and should
16304 * follow PCIe codepaths, but do not have a PCIe capabilities
16307 tg3_flag_set(tp, PCI_EXPRESS);
16308 } else if (!tg3_flag(tp, 5705_PLUS) ||
16309 tg3_flag(tp, 5780_CLASS)) {
16310 tp->pcix_cap = pci_find_capability(tp->pdev, PCI_CAP_ID_PCIX);
16311 if (!tp->pcix_cap) {
16312 dev_err(&tp->pdev->dev,
16313 "Cannot find PCI-X capability, aborting\n");
16317 if (!(pci_state_reg & PCISTATE_CONV_PCI_MODE))
16318 tg3_flag_set(tp, PCIX_MODE);
16321 /* If we have an AMD 762 or VIA K8T800 chipset, write
16322 * reordering to the mailbox registers done by the host
16323 * controller can cause major troubles. We read back from
16324 * every mailbox register write to force the writes to be
16325 * posted to the chip in order.
16327 if (pci_dev_present(tg3_write_reorder_chipsets) &&
16328 !tg3_flag(tp, PCI_EXPRESS))
16329 tg3_flag_set(tp, MBOX_WRITE_REORDER);
16331 pci_read_config_byte(tp->pdev, PCI_CACHE_LINE_SIZE,
16332 &tp->pci_cacheline_sz);
16333 pci_read_config_byte(tp->pdev, PCI_LATENCY_TIMER,
16334 &tp->pci_lat_timer);
16335 if (tg3_asic_rev(tp) == ASIC_REV_5703 &&
16336 tp->pci_lat_timer < 64) {
16337 tp->pci_lat_timer = 64;
16338 pci_write_config_byte(tp->pdev, PCI_LATENCY_TIMER,
16339 tp->pci_lat_timer);
16342 /* Important! -- It is critical that the PCI-X hw workaround
16343 * situation is decided before the first MMIO register access.
16345 if (tg3_chip_rev(tp) == CHIPREV_5700_BX) {
16346 /* 5700 BX chips need to have their TX producer index
16347 * mailboxes written twice to workaround a bug.
16349 tg3_flag_set(tp, TXD_MBOX_HWBUG);
16351 /* If we are in PCI-X mode, enable register write workaround.
16353 * The workaround is to use indirect register accesses
16354 * for all chip writes not to mailbox registers.
16356 if (tg3_flag(tp, PCIX_MODE)) {
16359 tg3_flag_set(tp, PCIX_TARGET_HWBUG);
16361 /* The chip can have it's power management PCI config
16362 * space registers clobbered due to this bug.
16363 * So explicitly force the chip into D0 here.
16365 pci_read_config_dword(tp->pdev,
16366 tp->pdev->pm_cap + PCI_PM_CTRL,
16368 pm_reg &= ~PCI_PM_CTRL_STATE_MASK;
16369 pm_reg |= PCI_PM_CTRL_PME_ENABLE | 0 /* D0 */;
16370 pci_write_config_dword(tp->pdev,
16371 tp->pdev->pm_cap + PCI_PM_CTRL,
16374 /* Also, force SERR#/PERR# in PCI command. */
16375 pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd);
16376 pci_cmd |= PCI_COMMAND_PARITY | PCI_COMMAND_SERR;
16377 pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd);
16381 if ((pci_state_reg & PCISTATE_BUS_SPEED_HIGH) != 0)
16382 tg3_flag_set(tp, PCI_HIGH_SPEED);
16383 if ((pci_state_reg & PCISTATE_BUS_32BIT) != 0)
16384 tg3_flag_set(tp, PCI_32BIT);
16386 /* Chip-specific fixup from Broadcom driver */
16387 if ((tg3_chip_rev_id(tp) == CHIPREV_ID_5704_A0) &&
16388 (!(pci_state_reg & PCISTATE_RETRY_SAME_DMA))) {
16389 pci_state_reg |= PCISTATE_RETRY_SAME_DMA;
16390 pci_write_config_dword(tp->pdev, TG3PCI_PCISTATE, pci_state_reg);
16393 /* Default fast path register access methods */
16394 tp->read32 = tg3_read32;
16395 tp->write32 = tg3_write32;
16396 tp->read32_mbox = tg3_read32;
16397 tp->write32_mbox = tg3_write32;
16398 tp->write32_tx_mbox = tg3_write32;
16399 tp->write32_rx_mbox = tg3_write32;
16401 /* Various workaround register access methods */
16402 if (tg3_flag(tp, PCIX_TARGET_HWBUG))
16403 tp->write32 = tg3_write_indirect_reg32;
16404 else if (tg3_asic_rev(tp) == ASIC_REV_5701 ||
16405 (tg3_flag(tp, PCI_EXPRESS) &&
16406 tg3_chip_rev_id(tp) == CHIPREV_ID_5750_A0)) {
16408 * Back to back register writes can cause problems on these
16409 * chips, the workaround is to read back all reg writes
16410 * except those to mailbox regs.
16412 * See tg3_write_indirect_reg32().
16414 tp->write32 = tg3_write_flush_reg32;
16417 if (tg3_flag(tp, TXD_MBOX_HWBUG) || tg3_flag(tp, MBOX_WRITE_REORDER)) {
16418 tp->write32_tx_mbox = tg3_write32_tx_mbox;
16419 if (tg3_flag(tp, MBOX_WRITE_REORDER))
16420 tp->write32_rx_mbox = tg3_write_flush_reg32;
16423 if (tg3_flag(tp, ICH_WORKAROUND)) {
16424 tp->read32 = tg3_read_indirect_reg32;
16425 tp->write32 = tg3_write_indirect_reg32;
16426 tp->read32_mbox = tg3_read_indirect_mbox;
16427 tp->write32_mbox = tg3_write_indirect_mbox;
16428 tp->write32_tx_mbox = tg3_write_indirect_mbox;
16429 tp->write32_rx_mbox = tg3_write_indirect_mbox;
16434 pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd);
16435 pci_cmd &= ~PCI_COMMAND_MEMORY;
16436 pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd);
16438 if (tg3_asic_rev(tp) == ASIC_REV_5906) {
16439 tp->read32_mbox = tg3_read32_mbox_5906;
16440 tp->write32_mbox = tg3_write32_mbox_5906;
16441 tp->write32_tx_mbox = tg3_write32_mbox_5906;
16442 tp->write32_rx_mbox = tg3_write32_mbox_5906;
16445 if (tp->write32 == tg3_write_indirect_reg32 ||
16446 (tg3_flag(tp, PCIX_MODE) &&
16447 (tg3_asic_rev(tp) == ASIC_REV_5700 ||
16448 tg3_asic_rev(tp) == ASIC_REV_5701)))
16449 tg3_flag_set(tp, SRAM_USE_CONFIG);
16451 /* The memory arbiter has to be enabled in order for SRAM accesses
16452 * to succeed. Normally on powerup the tg3 chip firmware will make
16453 * sure it is enabled, but other entities such as system netboot
16454 * code might disable it.
16456 val = tr32(MEMARB_MODE);
16457 tw32(MEMARB_MODE, val | MEMARB_MODE_ENABLE);
16459 tp->pci_fn = PCI_FUNC(tp->pdev->devfn) & 3;
16460 if (tg3_asic_rev(tp) == ASIC_REV_5704 ||
16461 tg3_flag(tp, 5780_CLASS)) {
16462 if (tg3_flag(tp, PCIX_MODE)) {
16463 pci_read_config_dword(tp->pdev,
16464 tp->pcix_cap + PCI_X_STATUS,
16466 tp->pci_fn = val & 0x7;
16468 } else if (tg3_asic_rev(tp) == ASIC_REV_5717 ||
16469 tg3_asic_rev(tp) == ASIC_REV_5719 ||
16470 tg3_asic_rev(tp) == ASIC_REV_5720) {
16471 tg3_read_mem(tp, NIC_SRAM_CPMU_STATUS, &val);
16472 if ((val & NIC_SRAM_CPMUSTAT_SIG_MSK) != NIC_SRAM_CPMUSTAT_SIG)
16473 val = tr32(TG3_CPMU_STATUS);
16475 if (tg3_asic_rev(tp) == ASIC_REV_5717)
16476 tp->pci_fn = (val & TG3_CPMU_STATUS_FMSK_5717) ? 1 : 0;
16478 tp->pci_fn = (val & TG3_CPMU_STATUS_FMSK_5719) >>
16479 TG3_CPMU_STATUS_FSHFT_5719;
16482 if (tg3_flag(tp, FLUSH_POSTED_WRITES)) {
16483 tp->write32_tx_mbox = tg3_write_flush_reg32;
16484 tp->write32_rx_mbox = tg3_write_flush_reg32;
16487 /* Get eeprom hw config before calling tg3_set_power_state().
16488 * In particular, the TG3_FLAG_IS_NIC flag must be
16489 * determined before calling tg3_set_power_state() so that
16490 * we know whether or not to switch out of Vaux power.
16491 * When the flag is set, it means that GPIO1 is used for eeprom
16492 * write protect and also implies that it is a LOM where GPIOs
16493 * are not used to switch power.
16495 tg3_get_eeprom_hw_cfg(tp);
16497 if (tg3_flag(tp, FW_TSO) && tg3_flag(tp, ENABLE_ASF)) {
16498 tg3_flag_clear(tp, TSO_CAPABLE);
16499 tg3_flag_clear(tp, TSO_BUG);
16500 tp->fw_needed = NULL;
16503 if (tg3_flag(tp, ENABLE_APE)) {
16504 /* Allow reads and writes to the
16505 * APE register and memory space.
16507 pci_state_reg |= PCISTATE_ALLOW_APE_CTLSPC_WR |
16508 PCISTATE_ALLOW_APE_SHMEM_WR |
16509 PCISTATE_ALLOW_APE_PSPACE_WR;
16510 pci_write_config_dword(tp->pdev, TG3PCI_PCISTATE,
16513 tg3_ape_lock_init(tp);
16516 /* Set up tp->grc_local_ctrl before calling
16517 * tg3_pwrsrc_switch_to_vmain(). GPIO1 driven high
16518 * will bring 5700's external PHY out of reset.
16519 * It is also used as eeprom write protect on LOMs.
16521 tp->grc_local_ctrl = GRC_LCLCTRL_INT_ON_ATTN | GRC_LCLCTRL_AUTO_SEEPROM;
16522 if (tg3_asic_rev(tp) == ASIC_REV_5700 ||
16523 tg3_flag(tp, EEPROM_WRITE_PROT))
16524 tp->grc_local_ctrl |= (GRC_LCLCTRL_GPIO_OE1 |
16525 GRC_LCLCTRL_GPIO_OUTPUT1);
16526 /* Unused GPIO3 must be driven as output on 5752 because there
16527 * are no pull-up resistors on unused GPIO pins.
16529 else if (tg3_asic_rev(tp) == ASIC_REV_5752)
16530 tp->grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE3;
16532 if (tg3_asic_rev(tp) == ASIC_REV_5755 ||
16533 tg3_asic_rev(tp) == ASIC_REV_57780 ||
16534 tg3_flag(tp, 57765_CLASS))
16535 tp->grc_local_ctrl |= GRC_LCLCTRL_GPIO_UART_SEL;
16537 if (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5761 ||
16538 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5761S) {
16539 /* Turn off the debug UART. */
16540 tp->grc_local_ctrl |= GRC_LCLCTRL_GPIO_UART_SEL;
16541 if (tg3_flag(tp, IS_NIC))
16542 /* Keep VMain power. */
16543 tp->grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE0 |
16544 GRC_LCLCTRL_GPIO_OUTPUT0;
16547 if (tg3_asic_rev(tp) == ASIC_REV_5762)
16548 tp->grc_local_ctrl |=
16549 tr32(GRC_LOCAL_CTRL) & GRC_LCLCTRL_GPIO_UART_SEL;
16551 /* Switch out of Vaux if it is a NIC */
16552 tg3_pwrsrc_switch_to_vmain(tp);
16554 /* Derive initial jumbo mode from MTU assigned in
16555 * ether_setup() via the alloc_etherdev() call
16557 if (tp->dev->mtu > ETH_DATA_LEN && !tg3_flag(tp, 5780_CLASS))
16558 tg3_flag_set(tp, JUMBO_RING_ENABLE);
16560 /* Determine WakeOnLan speed to use. */
16561 if (tg3_asic_rev(tp) == ASIC_REV_5700 ||
16562 tg3_chip_rev_id(tp) == CHIPREV_ID_5701_A0 ||
16563 tg3_chip_rev_id(tp) == CHIPREV_ID_5701_B0 ||
16564 tg3_chip_rev_id(tp) == CHIPREV_ID_5701_B2) {
16565 tg3_flag_clear(tp, WOL_SPEED_100MB);
16567 tg3_flag_set(tp, WOL_SPEED_100MB);
16570 if (tg3_asic_rev(tp) == ASIC_REV_5906)
16571 tp->phy_flags |= TG3_PHYFLG_IS_FET;
16573 /* A few boards don't want Ethernet@WireSpeed phy feature */
16574 if (tg3_asic_rev(tp) == ASIC_REV_5700 ||
16575 (tg3_asic_rev(tp) == ASIC_REV_5705 &&
16576 (tg3_chip_rev_id(tp) != CHIPREV_ID_5705_A0) &&
16577 (tg3_chip_rev_id(tp) != CHIPREV_ID_5705_A1)) ||
16578 (tp->phy_flags & TG3_PHYFLG_IS_FET) ||
16579 (tp->phy_flags & TG3_PHYFLG_ANY_SERDES))
16580 tp->phy_flags |= TG3_PHYFLG_NO_ETH_WIRE_SPEED;
16582 if (tg3_chip_rev(tp) == CHIPREV_5703_AX ||
16583 tg3_chip_rev(tp) == CHIPREV_5704_AX)
16584 tp->phy_flags |= TG3_PHYFLG_ADC_BUG;
16585 if (tg3_chip_rev_id(tp) == CHIPREV_ID_5704_A0)
16586 tp->phy_flags |= TG3_PHYFLG_5704_A0_BUG;
16588 if (tg3_flag(tp, 5705_PLUS) &&
16589 !(tp->phy_flags & TG3_PHYFLG_IS_FET) &&
16590 tg3_asic_rev(tp) != ASIC_REV_5785 &&
16591 tg3_asic_rev(tp) != ASIC_REV_57780 &&
16592 !tg3_flag(tp, 57765_PLUS)) {
16593 if (tg3_asic_rev(tp) == ASIC_REV_5755 ||
16594 tg3_asic_rev(tp) == ASIC_REV_5787 ||
16595 tg3_asic_rev(tp) == ASIC_REV_5784 ||
16596 tg3_asic_rev(tp) == ASIC_REV_5761) {
16597 if (tp->pdev->device != PCI_DEVICE_ID_TIGON3_5756 &&
16598 tp->pdev->device != PCI_DEVICE_ID_TIGON3_5722)
16599 tp->phy_flags |= TG3_PHYFLG_JITTER_BUG;
16600 if (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5755M)
16601 tp->phy_flags |= TG3_PHYFLG_ADJUST_TRIM;
16603 tp->phy_flags |= TG3_PHYFLG_BER_BUG;
16606 if (tg3_asic_rev(tp) == ASIC_REV_5784 &&
16607 tg3_chip_rev(tp) != CHIPREV_5784_AX) {
16608 tp->phy_otp = tg3_read_otp_phycfg(tp);
16609 if (tp->phy_otp == 0)
16610 tp->phy_otp = TG3_OTP_DEFAULT;
16613 if (tg3_flag(tp, CPMU_PRESENT))
16614 tp->mi_mode = MAC_MI_MODE_500KHZ_CONST;
16616 tp->mi_mode = MAC_MI_MODE_BASE;
16618 tp->coalesce_mode = 0;
16619 if (tg3_chip_rev(tp) != CHIPREV_5700_AX &&
16620 tg3_chip_rev(tp) != CHIPREV_5700_BX)
16621 tp->coalesce_mode |= HOSTCC_MODE_32BYTE;
16623 /* Set these bits to enable statistics workaround. */
16624 if (tg3_asic_rev(tp) == ASIC_REV_5717 ||
16625 tg3_asic_rev(tp) == ASIC_REV_5762 ||
16626 tg3_chip_rev_id(tp) == CHIPREV_ID_5719_A0 ||
16627 tg3_chip_rev_id(tp) == CHIPREV_ID_5720_A0) {
16628 tp->coalesce_mode |= HOSTCC_MODE_ATTN;
16629 tp->grc_mode |= GRC_MODE_IRQ_ON_FLOW_ATTN;
16632 if (tg3_asic_rev(tp) == ASIC_REV_5785 ||
16633 tg3_asic_rev(tp) == ASIC_REV_57780)
16634 tg3_flag_set(tp, USE_PHYLIB);
16636 err = tg3_mdio_init(tp);
16640 /* Initialize data/descriptor byte/word swapping. */
16641 val = tr32(GRC_MODE);
16642 if (tg3_asic_rev(tp) == ASIC_REV_5720 ||
16643 tg3_asic_rev(tp) == ASIC_REV_5762)
16644 val &= (GRC_MODE_BYTE_SWAP_B2HRX_DATA |
16645 GRC_MODE_WORD_SWAP_B2HRX_DATA |
16646 GRC_MODE_B2HRX_ENABLE |
16647 GRC_MODE_HTX2B_ENABLE |
16648 GRC_MODE_HOST_STACKUP);
16650 val &= GRC_MODE_HOST_STACKUP;
16652 tw32(GRC_MODE, val | tp->grc_mode);
16654 tg3_switch_clocks(tp);
16656 /* Clear this out for sanity. */
16657 tw32(TG3PCI_MEM_WIN_BASE_ADDR, 0);
16659 /* Clear TG3PCI_REG_BASE_ADDR to prevent hangs. */
16660 tw32(TG3PCI_REG_BASE_ADDR, 0);
16662 pci_read_config_dword(tp->pdev, TG3PCI_PCISTATE,
16664 if ((pci_state_reg & PCISTATE_CONV_PCI_MODE) == 0 &&
16665 !tg3_flag(tp, PCIX_TARGET_HWBUG)) {
16666 if (tg3_chip_rev_id(tp) == CHIPREV_ID_5701_A0 ||
16667 tg3_chip_rev_id(tp) == CHIPREV_ID_5701_B0 ||
16668 tg3_chip_rev_id(tp) == CHIPREV_ID_5701_B2 ||
16669 tg3_chip_rev_id(tp) == CHIPREV_ID_5701_B5) {
16670 void __iomem *sram_base;
16672 /* Write some dummy words into the SRAM status block
16673 * area, see if it reads back correctly. If the return
16674 * value is bad, force enable the PCIX workaround.
16676 sram_base = tp->regs + NIC_SRAM_WIN_BASE + NIC_SRAM_STATS_BLK;
16678 writel(0x00000000, sram_base);
16679 writel(0x00000000, sram_base + 4);
16680 writel(0xffffffff, sram_base + 4);
16681 if (readl(sram_base) != 0x00000000)
16682 tg3_flag_set(tp, PCIX_TARGET_HWBUG);
16687 tg3_nvram_init(tp);
16689 /* If the device has an NVRAM, no need to load patch firmware */
16690 if (tg3_asic_rev(tp) == ASIC_REV_57766 &&
16691 !tg3_flag(tp, NO_NVRAM))
16692 tp->fw_needed = NULL;
16694 grc_misc_cfg = tr32(GRC_MISC_CFG);
16695 grc_misc_cfg &= GRC_MISC_CFG_BOARD_ID_MASK;
16697 if (tg3_asic_rev(tp) == ASIC_REV_5705 &&
16698 (grc_misc_cfg == GRC_MISC_CFG_BOARD_ID_5788 ||
16699 grc_misc_cfg == GRC_MISC_CFG_BOARD_ID_5788M))
16700 tg3_flag_set(tp, IS_5788);
16702 if (!tg3_flag(tp, IS_5788) &&
16703 tg3_asic_rev(tp) != ASIC_REV_5700)
16704 tg3_flag_set(tp, TAGGED_STATUS);
16705 if (tg3_flag(tp, TAGGED_STATUS)) {
16706 tp->coalesce_mode |= (HOSTCC_MODE_CLRTICK_RXBD |
16707 HOSTCC_MODE_CLRTICK_TXBD);
16709 tp->misc_host_ctrl |= MISC_HOST_CTRL_TAGGED_STATUS;
16710 pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
16711 tp->misc_host_ctrl);
16714 /* Preserve the APE MAC_MODE bits */
16715 if (tg3_flag(tp, ENABLE_APE))
16716 tp->mac_mode = MAC_MODE_APE_TX_EN | MAC_MODE_APE_RX_EN;
16720 if (tg3_10_100_only_device(tp, ent))
16721 tp->phy_flags |= TG3_PHYFLG_10_100_ONLY;
16723 err = tg3_phy_probe(tp);
16725 dev_err(&tp->pdev->dev, "phy probe failed, err %d\n", err);
16726 /* ... but do not return immediately ... */
16731 tg3_read_fw_ver(tp);
16733 if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES) {
16734 tp->phy_flags &= ~TG3_PHYFLG_USE_MI_INTERRUPT;
16736 if (tg3_asic_rev(tp) == ASIC_REV_5700)
16737 tp->phy_flags |= TG3_PHYFLG_USE_MI_INTERRUPT;
16739 tp->phy_flags &= ~TG3_PHYFLG_USE_MI_INTERRUPT;
16742 /* 5700 {AX,BX} chips have a broken status block link
16743 * change bit implementation, so we must use the
16744 * status register in those cases.
16746 if (tg3_asic_rev(tp) == ASIC_REV_5700)
16747 tg3_flag_set(tp, USE_LINKCHG_REG);
16749 tg3_flag_clear(tp, USE_LINKCHG_REG);
16751 /* The led_ctrl is set during tg3_phy_probe, here we might
16752 * have to force the link status polling mechanism based
16753 * upon subsystem IDs.
16755 if (tp->pdev->subsystem_vendor == PCI_VENDOR_ID_DELL &&
16756 tg3_asic_rev(tp) == ASIC_REV_5701 &&
16757 !(tp->phy_flags & TG3_PHYFLG_PHY_SERDES)) {
16758 tp->phy_flags |= TG3_PHYFLG_USE_MI_INTERRUPT;
16759 tg3_flag_set(tp, USE_LINKCHG_REG);
16762 /* For all SERDES we poll the MAC status register. */
16763 if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES)
16764 tg3_flag_set(tp, POLL_SERDES);
16766 tg3_flag_clear(tp, POLL_SERDES);
16768 if (tg3_flag(tp, ENABLE_APE) && tg3_flag(tp, ENABLE_ASF))
16769 tg3_flag_set(tp, POLL_CPMU_LINK);
16771 tp->rx_offset = NET_SKB_PAD + NET_IP_ALIGN;
16772 tp->rx_copy_thresh = TG3_RX_COPY_THRESHOLD;
16773 if (tg3_asic_rev(tp) == ASIC_REV_5701 &&
16774 tg3_flag(tp, PCIX_MODE)) {
16775 tp->rx_offset = NET_SKB_PAD;
16776 #ifndef CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS
16777 tp->rx_copy_thresh = ~(u16)0;
16781 tp->rx_std_ring_mask = TG3_RX_STD_RING_SIZE(tp) - 1;
16782 tp->rx_jmb_ring_mask = TG3_RX_JMB_RING_SIZE(tp) - 1;
16783 tp->rx_ret_ring_mask = tg3_rx_ret_ring_size(tp) - 1;
16785 tp->rx_std_max_post = tp->rx_std_ring_mask + 1;
16787 /* Increment the rx prod index on the rx std ring by at most
16788 * 8 for these chips to workaround hw errata.
16790 if (tg3_asic_rev(tp) == ASIC_REV_5750 ||
16791 tg3_asic_rev(tp) == ASIC_REV_5752 ||
16792 tg3_asic_rev(tp) == ASIC_REV_5755)
16793 tp->rx_std_max_post = 8;
16795 if (tg3_flag(tp, ASPM_WORKAROUND))
16796 tp->pwrmgmt_thresh = tr32(PCIE_PWR_MGMT_THRESH) &
16797 PCIE_PWR_MGMT_L1_THRESH_MSK;
16802 #ifdef CONFIG_SPARC
16803 static int tg3_get_macaddr_sparc(struct tg3 *tp)
16805 struct net_device *dev = tp->dev;
16806 struct pci_dev *pdev = tp->pdev;
16807 struct device_node *dp = pci_device_to_OF_node(pdev);
16808 const unsigned char *addr;
16811 addr = of_get_property(dp, "local-mac-address", &len);
16812 if (addr && len == ETH_ALEN) {
16813 memcpy(dev->dev_addr, addr, ETH_ALEN);
16819 static int tg3_get_default_macaddr_sparc(struct tg3 *tp)
16821 struct net_device *dev = tp->dev;
16823 memcpy(dev->dev_addr, idprom->id_ethaddr, ETH_ALEN);
16828 static int tg3_get_device_address(struct tg3 *tp)
16830 struct net_device *dev = tp->dev;
16831 u32 hi, lo, mac_offset;
16835 #ifdef CONFIG_SPARC
16836 if (!tg3_get_macaddr_sparc(tp))
16840 if (tg3_flag(tp, IS_SSB_CORE)) {
16841 err = ssb_gige_get_macaddr(tp->pdev, &dev->dev_addr[0]);
16842 if (!err && is_valid_ether_addr(&dev->dev_addr[0]))
16847 if (tg3_asic_rev(tp) == ASIC_REV_5704 ||
16848 tg3_flag(tp, 5780_CLASS)) {
16849 if (tr32(TG3PCI_DUAL_MAC_CTRL) & DUAL_MAC_CTRL_ID)
16851 if (tg3_nvram_lock(tp))
16852 tw32_f(NVRAM_CMD, NVRAM_CMD_RESET);
16854 tg3_nvram_unlock(tp);
16855 } else if (tg3_flag(tp, 5717_PLUS)) {
16856 if (tp->pci_fn & 1)
16858 if (tp->pci_fn > 1)
16859 mac_offset += 0x18c;
16860 } else if (tg3_asic_rev(tp) == ASIC_REV_5906)
16863 /* First try to get it from MAC address mailbox. */
16864 tg3_read_mem(tp, NIC_SRAM_MAC_ADDR_HIGH_MBOX, &hi);
16865 if ((hi >> 16) == 0x484b) {
16866 dev->dev_addr[0] = (hi >> 8) & 0xff;
16867 dev->dev_addr[1] = (hi >> 0) & 0xff;
16869 tg3_read_mem(tp, NIC_SRAM_MAC_ADDR_LOW_MBOX, &lo);
16870 dev->dev_addr[2] = (lo >> 24) & 0xff;
16871 dev->dev_addr[3] = (lo >> 16) & 0xff;
16872 dev->dev_addr[4] = (lo >> 8) & 0xff;
16873 dev->dev_addr[5] = (lo >> 0) & 0xff;
16875 /* Some old bootcode may report a 0 MAC address in SRAM */
16876 addr_ok = is_valid_ether_addr(&dev->dev_addr[0]);
16879 /* Next, try NVRAM. */
16880 if (!tg3_flag(tp, NO_NVRAM) &&
16881 !tg3_nvram_read_be32(tp, mac_offset + 0, &hi) &&
16882 !tg3_nvram_read_be32(tp, mac_offset + 4, &lo)) {
16883 memcpy(&dev->dev_addr[0], ((char *)&hi) + 2, 2);
16884 memcpy(&dev->dev_addr[2], (char *)&lo, sizeof(lo));
16886 /* Finally just fetch it out of the MAC control regs. */
16888 hi = tr32(MAC_ADDR_0_HIGH);
16889 lo = tr32(MAC_ADDR_0_LOW);
16891 dev->dev_addr[5] = lo & 0xff;
16892 dev->dev_addr[4] = (lo >> 8) & 0xff;
16893 dev->dev_addr[3] = (lo >> 16) & 0xff;
16894 dev->dev_addr[2] = (lo >> 24) & 0xff;
16895 dev->dev_addr[1] = hi & 0xff;
16896 dev->dev_addr[0] = (hi >> 8) & 0xff;
16900 if (!is_valid_ether_addr(&dev->dev_addr[0])) {
16901 #ifdef CONFIG_SPARC
16902 if (!tg3_get_default_macaddr_sparc(tp))
16910 #define BOUNDARY_SINGLE_CACHELINE 1
16911 #define BOUNDARY_MULTI_CACHELINE 2
16913 static u32 tg3_calc_dma_bndry(struct tg3 *tp, u32 val)
16915 int cacheline_size;
16919 pci_read_config_byte(tp->pdev, PCI_CACHE_LINE_SIZE, &byte);
16921 cacheline_size = 1024;
16923 cacheline_size = (int) byte * 4;
16925 /* On 5703 and later chips, the boundary bits have no
16928 if (tg3_asic_rev(tp) != ASIC_REV_5700 &&
16929 tg3_asic_rev(tp) != ASIC_REV_5701 &&
16930 !tg3_flag(tp, PCI_EXPRESS))
16933 #if defined(CONFIG_PPC64) || defined(CONFIG_IA64) || defined(CONFIG_PARISC)
16934 goal = BOUNDARY_MULTI_CACHELINE;
16936 #if defined(CONFIG_SPARC64) || defined(CONFIG_ALPHA)
16937 goal = BOUNDARY_SINGLE_CACHELINE;
16943 if (tg3_flag(tp, 57765_PLUS)) {
16944 val = goal ? 0 : DMA_RWCTRL_DIS_CACHE_ALIGNMENT;
16951 /* PCI controllers on most RISC systems tend to disconnect
16952 * when a device tries to burst across a cache-line boundary.
16953 * Therefore, letting tg3 do so just wastes PCI bandwidth.
16955 * Unfortunately, for PCI-E there are only limited
16956 * write-side controls for this, and thus for reads
16957 * we will still get the disconnects. We'll also waste
16958 * these PCI cycles for both read and write for chips
16959 * other than 5700 and 5701 which do not implement the
16962 if (tg3_flag(tp, PCIX_MODE) && !tg3_flag(tp, PCI_EXPRESS)) {
16963 switch (cacheline_size) {
16968 if (goal == BOUNDARY_SINGLE_CACHELINE) {
16969 val |= (DMA_RWCTRL_READ_BNDRY_128_PCIX |
16970 DMA_RWCTRL_WRITE_BNDRY_128_PCIX);
16972 val |= (DMA_RWCTRL_READ_BNDRY_384_PCIX |
16973 DMA_RWCTRL_WRITE_BNDRY_384_PCIX);
16978 val |= (DMA_RWCTRL_READ_BNDRY_256_PCIX |
16979 DMA_RWCTRL_WRITE_BNDRY_256_PCIX);
16983 val |= (DMA_RWCTRL_READ_BNDRY_384_PCIX |
16984 DMA_RWCTRL_WRITE_BNDRY_384_PCIX);
16987 } else if (tg3_flag(tp, PCI_EXPRESS)) {
16988 switch (cacheline_size) {
16992 if (goal == BOUNDARY_SINGLE_CACHELINE) {
16993 val &= ~DMA_RWCTRL_WRITE_BNDRY_DISAB_PCIE;
16994 val |= DMA_RWCTRL_WRITE_BNDRY_64_PCIE;
17000 val &= ~DMA_RWCTRL_WRITE_BNDRY_DISAB_PCIE;
17001 val |= DMA_RWCTRL_WRITE_BNDRY_128_PCIE;
17005 switch (cacheline_size) {
17007 if (goal == BOUNDARY_SINGLE_CACHELINE) {
17008 val |= (DMA_RWCTRL_READ_BNDRY_16 |
17009 DMA_RWCTRL_WRITE_BNDRY_16);
17014 if (goal == BOUNDARY_SINGLE_CACHELINE) {
17015 val |= (DMA_RWCTRL_READ_BNDRY_32 |
17016 DMA_RWCTRL_WRITE_BNDRY_32);
17021 if (goal == BOUNDARY_SINGLE_CACHELINE) {
17022 val |= (DMA_RWCTRL_READ_BNDRY_64 |
17023 DMA_RWCTRL_WRITE_BNDRY_64);
17028 if (goal == BOUNDARY_SINGLE_CACHELINE) {
17029 val |= (DMA_RWCTRL_READ_BNDRY_128 |
17030 DMA_RWCTRL_WRITE_BNDRY_128);
17035 val |= (DMA_RWCTRL_READ_BNDRY_256 |
17036 DMA_RWCTRL_WRITE_BNDRY_256);
17039 val |= (DMA_RWCTRL_READ_BNDRY_512 |
17040 DMA_RWCTRL_WRITE_BNDRY_512);
17044 val |= (DMA_RWCTRL_READ_BNDRY_1024 |
17045 DMA_RWCTRL_WRITE_BNDRY_1024);
17054 static int tg3_do_test_dma(struct tg3 *tp, u32 *buf, dma_addr_t buf_dma,
17055 int size, bool to_device)
17057 struct tg3_internal_buffer_desc test_desc;
17058 u32 sram_dma_descs;
17061 sram_dma_descs = NIC_SRAM_DMA_DESC_POOL_BASE;
17063 tw32(FTQ_RCVBD_COMP_FIFO_ENQDEQ, 0);
17064 tw32(FTQ_RCVDATA_COMP_FIFO_ENQDEQ, 0);
17065 tw32(RDMAC_STATUS, 0);
17066 tw32(WDMAC_STATUS, 0);
17068 tw32(BUFMGR_MODE, 0);
17069 tw32(FTQ_RESET, 0);
17071 test_desc.addr_hi = ((u64) buf_dma) >> 32;
17072 test_desc.addr_lo = buf_dma & 0xffffffff;
17073 test_desc.nic_mbuf = 0x00002100;
17074 test_desc.len = size;
17077 * HP ZX1 was seeing test failures for 5701 cards running at 33Mhz
17078 * the *second* time the tg3 driver was getting loaded after an
17081 * Broadcom tells me:
17082 * ...the DMA engine is connected to the GRC block and a DMA
17083 * reset may affect the GRC block in some unpredictable way...
17084 * The behavior of resets to individual blocks has not been tested.
17086 * Broadcom noted the GRC reset will also reset all sub-components.
17089 test_desc.cqid_sqid = (13 << 8) | 2;
17091 tw32_f(RDMAC_MODE, RDMAC_MODE_ENABLE);
17094 test_desc.cqid_sqid = (16 << 8) | 7;
17096 tw32_f(WDMAC_MODE, WDMAC_MODE_ENABLE);
17099 test_desc.flags = 0x00000005;
17101 for (i = 0; i < (sizeof(test_desc) / sizeof(u32)); i++) {
17104 val = *(((u32 *)&test_desc) + i);
17105 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR,
17106 sram_dma_descs + (i * sizeof(u32)));
17107 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_DATA, val);
17109 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, 0);
17112 tw32(FTQ_DMA_HIGH_READ_FIFO_ENQDEQ, sram_dma_descs);
17114 tw32(FTQ_DMA_HIGH_WRITE_FIFO_ENQDEQ, sram_dma_descs);
17117 for (i = 0; i < 40; i++) {
17121 val = tr32(FTQ_RCVBD_COMP_FIFO_ENQDEQ);
17123 val = tr32(FTQ_RCVDATA_COMP_FIFO_ENQDEQ);
17124 if ((val & 0xffff) == sram_dma_descs) {
17135 #define TEST_BUFFER_SIZE 0x2000
17137 static DEFINE_PCI_DEVICE_TABLE(tg3_dma_wait_state_chipsets) = {
17138 { PCI_DEVICE(PCI_VENDOR_ID_APPLE, PCI_DEVICE_ID_APPLE_UNI_N_PCI15) },
17142 static int tg3_test_dma(struct tg3 *tp)
17144 dma_addr_t buf_dma;
17145 u32 *buf, saved_dma_rwctrl;
17148 buf = dma_alloc_coherent(&tp->pdev->dev, TEST_BUFFER_SIZE,
17149 &buf_dma, GFP_KERNEL);
17155 tp->dma_rwctrl = ((0x7 << DMA_RWCTRL_PCI_WRITE_CMD_SHIFT) |
17156 (0x6 << DMA_RWCTRL_PCI_READ_CMD_SHIFT));
17158 tp->dma_rwctrl = tg3_calc_dma_bndry(tp, tp->dma_rwctrl);
17160 if (tg3_flag(tp, 57765_PLUS))
17163 if (tg3_flag(tp, PCI_EXPRESS)) {
17164 /* DMA read watermark not used on PCIE */
17165 tp->dma_rwctrl |= 0x00180000;
17166 } else if (!tg3_flag(tp, PCIX_MODE)) {
17167 if (tg3_asic_rev(tp) == ASIC_REV_5705 ||
17168 tg3_asic_rev(tp) == ASIC_REV_5750)
17169 tp->dma_rwctrl |= 0x003f0000;
17171 tp->dma_rwctrl |= 0x003f000f;
17173 if (tg3_asic_rev(tp) == ASIC_REV_5703 ||
17174 tg3_asic_rev(tp) == ASIC_REV_5704) {
17175 u32 ccval = (tr32(TG3PCI_CLOCK_CTRL) & 0x1f);
17176 u32 read_water = 0x7;
17178 /* If the 5704 is behind the EPB bridge, we can
17179 * do the less restrictive ONE_DMA workaround for
17180 * better performance.
17182 if (tg3_flag(tp, 40BIT_DMA_BUG) &&
17183 tg3_asic_rev(tp) == ASIC_REV_5704)
17184 tp->dma_rwctrl |= 0x8000;
17185 else if (ccval == 0x6 || ccval == 0x7)
17186 tp->dma_rwctrl |= DMA_RWCTRL_ONE_DMA;
17188 if (tg3_asic_rev(tp) == ASIC_REV_5703)
17190 /* Set bit 23 to enable PCIX hw bug fix */
17192 (read_water << DMA_RWCTRL_READ_WATER_SHIFT) |
17193 (0x3 << DMA_RWCTRL_WRITE_WATER_SHIFT) |
17195 } else if (tg3_asic_rev(tp) == ASIC_REV_5780) {
17196 /* 5780 always in PCIX mode */
17197 tp->dma_rwctrl |= 0x00144000;
17198 } else if (tg3_asic_rev(tp) == ASIC_REV_5714) {
17199 /* 5714 always in PCIX mode */
17200 tp->dma_rwctrl |= 0x00148000;
17202 tp->dma_rwctrl |= 0x001b000f;
17205 if (tg3_flag(tp, ONE_DMA_AT_ONCE))
17206 tp->dma_rwctrl |= DMA_RWCTRL_ONE_DMA;
17208 if (tg3_asic_rev(tp) == ASIC_REV_5703 ||
17209 tg3_asic_rev(tp) == ASIC_REV_5704)
17210 tp->dma_rwctrl &= 0xfffffff0;
17212 if (tg3_asic_rev(tp) == ASIC_REV_5700 ||
17213 tg3_asic_rev(tp) == ASIC_REV_5701) {
17214 /* Remove this if it causes problems for some boards. */
17215 tp->dma_rwctrl |= DMA_RWCTRL_USE_MEM_READ_MULT;
17217 /* On 5700/5701 chips, we need to set this bit.
17218 * Otherwise the chip will issue cacheline transactions
17219 * to streamable DMA memory with not all the byte
17220 * enables turned on. This is an error on several
17221 * RISC PCI controllers, in particular sparc64.
17223 * On 5703/5704 chips, this bit has been reassigned
17224 * a different meaning. In particular, it is used
17225 * on those chips to enable a PCI-X workaround.
17227 tp->dma_rwctrl |= DMA_RWCTRL_ASSERT_ALL_BE;
17230 tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
17233 if (tg3_asic_rev(tp) != ASIC_REV_5700 &&
17234 tg3_asic_rev(tp) != ASIC_REV_5701)
17237 /* It is best to perform DMA test with maximum write burst size
17238 * to expose the 5700/5701 write DMA bug.
17240 saved_dma_rwctrl = tp->dma_rwctrl;
17241 tp->dma_rwctrl &= ~DMA_RWCTRL_WRITE_BNDRY_MASK;
17242 tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
17247 for (i = 0; i < TEST_BUFFER_SIZE / sizeof(u32); i++)
17250 /* Send the buffer to the chip. */
17251 ret = tg3_do_test_dma(tp, buf, buf_dma, TEST_BUFFER_SIZE, true);
17253 dev_err(&tp->pdev->dev,
17254 "%s: Buffer write failed. err = %d\n",
17259 /* Now read it back. */
17260 ret = tg3_do_test_dma(tp, buf, buf_dma, TEST_BUFFER_SIZE, false);
17262 dev_err(&tp->pdev->dev, "%s: Buffer read failed. "
17263 "err = %d\n", __func__, ret);
17268 for (i = 0; i < TEST_BUFFER_SIZE / sizeof(u32); i++) {
17272 if ((tp->dma_rwctrl & DMA_RWCTRL_WRITE_BNDRY_MASK) !=
17273 DMA_RWCTRL_WRITE_BNDRY_16) {
17274 tp->dma_rwctrl &= ~DMA_RWCTRL_WRITE_BNDRY_MASK;
17275 tp->dma_rwctrl |= DMA_RWCTRL_WRITE_BNDRY_16;
17276 tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
17279 dev_err(&tp->pdev->dev,
17280 "%s: Buffer corrupted on read back! "
17281 "(%d != %d)\n", __func__, p[i], i);
17287 if (i == (TEST_BUFFER_SIZE / sizeof(u32))) {
17293 if ((tp->dma_rwctrl & DMA_RWCTRL_WRITE_BNDRY_MASK) !=
17294 DMA_RWCTRL_WRITE_BNDRY_16) {
17295 /* DMA test passed without adjusting DMA boundary,
17296 * now look for chipsets that are known to expose the
17297 * DMA bug without failing the test.
17299 if (pci_dev_present(tg3_dma_wait_state_chipsets)) {
17300 tp->dma_rwctrl &= ~DMA_RWCTRL_WRITE_BNDRY_MASK;
17301 tp->dma_rwctrl |= DMA_RWCTRL_WRITE_BNDRY_16;
17303 /* Safe to use the calculated DMA boundary. */
17304 tp->dma_rwctrl = saved_dma_rwctrl;
17307 tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
17311 dma_free_coherent(&tp->pdev->dev, TEST_BUFFER_SIZE, buf, buf_dma);
17316 static void tg3_init_bufmgr_config(struct tg3 *tp)
17318 if (tg3_flag(tp, 57765_PLUS)) {
17319 tp->bufmgr_config.mbuf_read_dma_low_water =
17320 DEFAULT_MB_RDMA_LOW_WATER_5705;
17321 tp->bufmgr_config.mbuf_mac_rx_low_water =
17322 DEFAULT_MB_MACRX_LOW_WATER_57765;
17323 tp->bufmgr_config.mbuf_high_water =
17324 DEFAULT_MB_HIGH_WATER_57765;
17326 tp->bufmgr_config.mbuf_read_dma_low_water_jumbo =
17327 DEFAULT_MB_RDMA_LOW_WATER_5705;
17328 tp->bufmgr_config.mbuf_mac_rx_low_water_jumbo =
17329 DEFAULT_MB_MACRX_LOW_WATER_JUMBO_57765;
17330 tp->bufmgr_config.mbuf_high_water_jumbo =
17331 DEFAULT_MB_HIGH_WATER_JUMBO_57765;
17332 } else if (tg3_flag(tp, 5705_PLUS)) {
17333 tp->bufmgr_config.mbuf_read_dma_low_water =
17334 DEFAULT_MB_RDMA_LOW_WATER_5705;
17335 tp->bufmgr_config.mbuf_mac_rx_low_water =
17336 DEFAULT_MB_MACRX_LOW_WATER_5705;
17337 tp->bufmgr_config.mbuf_high_water =
17338 DEFAULT_MB_HIGH_WATER_5705;
17339 if (tg3_asic_rev(tp) == ASIC_REV_5906) {
17340 tp->bufmgr_config.mbuf_mac_rx_low_water =
17341 DEFAULT_MB_MACRX_LOW_WATER_5906;
17342 tp->bufmgr_config.mbuf_high_water =
17343 DEFAULT_MB_HIGH_WATER_5906;
17346 tp->bufmgr_config.mbuf_read_dma_low_water_jumbo =
17347 DEFAULT_MB_RDMA_LOW_WATER_JUMBO_5780;
17348 tp->bufmgr_config.mbuf_mac_rx_low_water_jumbo =
17349 DEFAULT_MB_MACRX_LOW_WATER_JUMBO_5780;
17350 tp->bufmgr_config.mbuf_high_water_jumbo =
17351 DEFAULT_MB_HIGH_WATER_JUMBO_5780;
17353 tp->bufmgr_config.mbuf_read_dma_low_water =
17354 DEFAULT_MB_RDMA_LOW_WATER;
17355 tp->bufmgr_config.mbuf_mac_rx_low_water =
17356 DEFAULT_MB_MACRX_LOW_WATER;
17357 tp->bufmgr_config.mbuf_high_water =
17358 DEFAULT_MB_HIGH_WATER;
17360 tp->bufmgr_config.mbuf_read_dma_low_water_jumbo =
17361 DEFAULT_MB_RDMA_LOW_WATER_JUMBO;
17362 tp->bufmgr_config.mbuf_mac_rx_low_water_jumbo =
17363 DEFAULT_MB_MACRX_LOW_WATER_JUMBO;
17364 tp->bufmgr_config.mbuf_high_water_jumbo =
17365 DEFAULT_MB_HIGH_WATER_JUMBO;
17368 tp->bufmgr_config.dma_low_water = DEFAULT_DMA_LOW_WATER;
17369 tp->bufmgr_config.dma_high_water = DEFAULT_DMA_HIGH_WATER;
17372 static char *tg3_phy_string(struct tg3 *tp)
17374 switch (tp->phy_id & TG3_PHY_ID_MASK) {
17375 case TG3_PHY_ID_BCM5400: return "5400";
17376 case TG3_PHY_ID_BCM5401: return "5401";
17377 case TG3_PHY_ID_BCM5411: return "5411";
17378 case TG3_PHY_ID_BCM5701: return "5701";
17379 case TG3_PHY_ID_BCM5703: return "5703";
17380 case TG3_PHY_ID_BCM5704: return "5704";
17381 case TG3_PHY_ID_BCM5705: return "5705";
17382 case TG3_PHY_ID_BCM5750: return "5750";
17383 case TG3_PHY_ID_BCM5752: return "5752";
17384 case TG3_PHY_ID_BCM5714: return "5714";
17385 case TG3_PHY_ID_BCM5780: return "5780";
17386 case TG3_PHY_ID_BCM5755: return "5755";
17387 case TG3_PHY_ID_BCM5787: return "5787";
17388 case TG3_PHY_ID_BCM5784: return "5784";
17389 case TG3_PHY_ID_BCM5756: return "5722/5756";
17390 case TG3_PHY_ID_BCM5906: return "5906";
17391 case TG3_PHY_ID_BCM5761: return "5761";
17392 case TG3_PHY_ID_BCM5718C: return "5718C";
17393 case TG3_PHY_ID_BCM5718S: return "5718S";
17394 case TG3_PHY_ID_BCM57765: return "57765";
17395 case TG3_PHY_ID_BCM5719C: return "5719C";
17396 case TG3_PHY_ID_BCM5720C: return "5720C";
17397 case TG3_PHY_ID_BCM5762: return "5762C";
17398 case TG3_PHY_ID_BCM8002: return "8002/serdes";
17399 case 0: return "serdes";
17400 default: return "unknown";
17404 static char *tg3_bus_string(struct tg3 *tp, char *str)
17406 if (tg3_flag(tp, PCI_EXPRESS)) {
17407 strcpy(str, "PCI Express");
17409 } else if (tg3_flag(tp, PCIX_MODE)) {
17410 u32 clock_ctrl = tr32(TG3PCI_CLOCK_CTRL) & 0x1f;
17412 strcpy(str, "PCIX:");
17414 if ((clock_ctrl == 7) ||
17415 ((tr32(GRC_MISC_CFG) & GRC_MISC_CFG_BOARD_ID_MASK) ==
17416 GRC_MISC_CFG_BOARD_ID_5704CIOBE))
17417 strcat(str, "133MHz");
17418 else if (clock_ctrl == 0)
17419 strcat(str, "33MHz");
17420 else if (clock_ctrl == 2)
17421 strcat(str, "50MHz");
17422 else if (clock_ctrl == 4)
17423 strcat(str, "66MHz");
17424 else if (clock_ctrl == 6)
17425 strcat(str, "100MHz");
17427 strcpy(str, "PCI:");
17428 if (tg3_flag(tp, PCI_HIGH_SPEED))
17429 strcat(str, "66MHz");
17431 strcat(str, "33MHz");
17433 if (tg3_flag(tp, PCI_32BIT))
17434 strcat(str, ":32-bit");
17436 strcat(str, ":64-bit");
17440 static void tg3_init_coal(struct tg3 *tp)
17442 struct ethtool_coalesce *ec = &tp->coal;
17444 memset(ec, 0, sizeof(*ec));
17445 ec->cmd = ETHTOOL_GCOALESCE;
17446 ec->rx_coalesce_usecs = LOW_RXCOL_TICKS;
17447 ec->tx_coalesce_usecs = LOW_TXCOL_TICKS;
17448 ec->rx_max_coalesced_frames = LOW_RXMAX_FRAMES;
17449 ec->tx_max_coalesced_frames = LOW_TXMAX_FRAMES;
17450 ec->rx_coalesce_usecs_irq = DEFAULT_RXCOAL_TICK_INT;
17451 ec->tx_coalesce_usecs_irq = DEFAULT_TXCOAL_TICK_INT;
17452 ec->rx_max_coalesced_frames_irq = DEFAULT_RXCOAL_MAXF_INT;
17453 ec->tx_max_coalesced_frames_irq = DEFAULT_TXCOAL_MAXF_INT;
17454 ec->stats_block_coalesce_usecs = DEFAULT_STAT_COAL_TICKS;
17456 if (tp->coalesce_mode & (HOSTCC_MODE_CLRTICK_RXBD |
17457 HOSTCC_MODE_CLRTICK_TXBD)) {
17458 ec->rx_coalesce_usecs = LOW_RXCOL_TICKS_CLRTCKS;
17459 ec->rx_coalesce_usecs_irq = DEFAULT_RXCOAL_TICK_INT_CLRTCKS;
17460 ec->tx_coalesce_usecs = LOW_TXCOL_TICKS_CLRTCKS;
17461 ec->tx_coalesce_usecs_irq = DEFAULT_TXCOAL_TICK_INT_CLRTCKS;
17464 if (tg3_flag(tp, 5705_PLUS)) {
17465 ec->rx_coalesce_usecs_irq = 0;
17466 ec->tx_coalesce_usecs_irq = 0;
17467 ec->stats_block_coalesce_usecs = 0;
17471 static int tg3_init_one(struct pci_dev *pdev,
17472 const struct pci_device_id *ent)
17474 struct net_device *dev;
17477 u32 sndmbx, rcvmbx, intmbx;
17479 u64 dma_mask, persist_dma_mask;
17480 netdev_features_t features = 0;
17482 printk_once(KERN_INFO "%s\n", version);
17484 err = pci_enable_device(pdev);
17486 dev_err(&pdev->dev, "Cannot enable PCI device, aborting\n");
17490 err = pci_request_regions(pdev, DRV_MODULE_NAME);
17492 dev_err(&pdev->dev, "Cannot obtain PCI resources, aborting\n");
17493 goto err_out_disable_pdev;
17496 pci_set_master(pdev);
17498 dev = alloc_etherdev_mq(sizeof(*tp), TG3_IRQ_MAX_VECS);
17501 goto err_out_free_res;
17504 SET_NETDEV_DEV(dev, &pdev->dev);
17506 tp = netdev_priv(dev);
17509 tp->rx_mode = TG3_DEF_RX_MODE;
17510 tp->tx_mode = TG3_DEF_TX_MODE;
17514 tp->msg_enable = tg3_debug;
17516 tp->msg_enable = TG3_DEF_MSG_ENABLE;
17518 if (pdev_is_ssb_gige_core(pdev)) {
17519 tg3_flag_set(tp, IS_SSB_CORE);
17520 if (ssb_gige_must_flush_posted_writes(pdev))
17521 tg3_flag_set(tp, FLUSH_POSTED_WRITES);
17522 if (ssb_gige_one_dma_at_once(pdev))
17523 tg3_flag_set(tp, ONE_DMA_AT_ONCE);
17524 if (ssb_gige_have_roboswitch(pdev)) {
17525 tg3_flag_set(tp, USE_PHYLIB);
17526 tg3_flag_set(tp, ROBOSWITCH);
17528 if (ssb_gige_is_rgmii(pdev))
17529 tg3_flag_set(tp, RGMII_MODE);
17532 /* The word/byte swap controls here control register access byte
17533 * swapping. DMA data byte swapping is controlled in the GRC_MODE
17536 tp->misc_host_ctrl =
17537 MISC_HOST_CTRL_MASK_PCI_INT |
17538 MISC_HOST_CTRL_WORD_SWAP |
17539 MISC_HOST_CTRL_INDIR_ACCESS |
17540 MISC_HOST_CTRL_PCISTATE_RW;
17542 /* The NONFRM (non-frame) byte/word swap controls take effect
17543 * on descriptor entries, anything which isn't packet data.
17545 * The StrongARM chips on the board (one for tx, one for rx)
17546 * are running in big-endian mode.
17548 tp->grc_mode = (GRC_MODE_WSWAP_DATA | GRC_MODE_BSWAP_DATA |
17549 GRC_MODE_WSWAP_NONFRM_DATA);
17550 #ifdef __BIG_ENDIAN
17551 tp->grc_mode |= GRC_MODE_BSWAP_NONFRM_DATA;
17553 spin_lock_init(&tp->lock);
17554 spin_lock_init(&tp->indirect_lock);
17555 INIT_WORK(&tp->reset_task, tg3_reset_task);
17557 tp->regs = pci_ioremap_bar(pdev, BAR_0);
17559 dev_err(&pdev->dev, "Cannot map device registers, aborting\n");
17561 goto err_out_free_dev;
17564 if (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5761 ||
17565 tp->pdev->device == PCI_DEVICE_ID_TIGON3_5761E ||
17566 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5761S ||
17567 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5761SE ||
17568 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5717 ||
17569 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5717_C ||
17570 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5718 ||
17571 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5719 ||
17572 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5720 ||
17573 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57767 ||
17574 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57764 ||
17575 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5762 ||
17576 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5725 ||
17577 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5727 ||
17578 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57787) {
17579 tg3_flag_set(tp, ENABLE_APE);
17580 tp->aperegs = pci_ioremap_bar(pdev, BAR_2);
17581 if (!tp->aperegs) {
17582 dev_err(&pdev->dev,
17583 "Cannot map APE registers, aborting\n");
17585 goto err_out_iounmap;
17589 tp->rx_pending = TG3_DEF_RX_RING_PENDING;
17590 tp->rx_jumbo_pending = TG3_DEF_RX_JUMBO_RING_PENDING;
17592 dev->ethtool_ops = &tg3_ethtool_ops;
17593 dev->watchdog_timeo = TG3_TX_TIMEOUT;
17594 dev->netdev_ops = &tg3_netdev_ops;
17595 dev->irq = pdev->irq;
17597 err = tg3_get_invariants(tp, ent);
17599 dev_err(&pdev->dev,
17600 "Problem fetching invariants of chip, aborting\n");
17601 goto err_out_apeunmap;
17604 /* The EPB bridge inside 5714, 5715, and 5780 and any
17605 * device behind the EPB cannot support DMA addresses > 40-bit.
17606 * On 64-bit systems with IOMMU, use 40-bit dma_mask.
17607 * On 64-bit systems without IOMMU, use 64-bit dma_mask and
17608 * do DMA address check in tg3_start_xmit().
17610 if (tg3_flag(tp, IS_5788))
17611 persist_dma_mask = dma_mask = DMA_BIT_MASK(32);
17612 else if (tg3_flag(tp, 40BIT_DMA_BUG)) {
17613 persist_dma_mask = dma_mask = DMA_BIT_MASK(40);
17614 #ifdef CONFIG_HIGHMEM
17615 dma_mask = DMA_BIT_MASK(64);
17618 persist_dma_mask = dma_mask = DMA_BIT_MASK(64);
17620 /* Configure DMA attributes. */
17621 if (dma_mask > DMA_BIT_MASK(32)) {
17622 err = pci_set_dma_mask(pdev, dma_mask);
17624 features |= NETIF_F_HIGHDMA;
17625 err = pci_set_consistent_dma_mask(pdev,
17628 dev_err(&pdev->dev, "Unable to obtain 64 bit "
17629 "DMA for consistent allocations\n");
17630 goto err_out_apeunmap;
17634 if (err || dma_mask == DMA_BIT_MASK(32)) {
17635 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
17637 dev_err(&pdev->dev,
17638 "No usable DMA configuration, aborting\n");
17639 goto err_out_apeunmap;
17643 tg3_init_bufmgr_config(tp);
17645 features |= NETIF_F_HW_VLAN_CTAG_TX | NETIF_F_HW_VLAN_CTAG_RX;
17647 /* 5700 B0 chips do not support checksumming correctly due
17648 * to hardware bugs.
17650 if (tg3_chip_rev_id(tp) != CHIPREV_ID_5700_B0) {
17651 features |= NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_RXCSUM;
17653 if (tg3_flag(tp, 5755_PLUS))
17654 features |= NETIF_F_IPV6_CSUM;
17657 /* TSO is on by default on chips that support hardware TSO.
17658 * Firmware TSO on older chips gives lower performance, so it
17659 * is off by default, but can be enabled using ethtool.
17661 if ((tg3_flag(tp, HW_TSO_1) ||
17662 tg3_flag(tp, HW_TSO_2) ||
17663 tg3_flag(tp, HW_TSO_3)) &&
17664 (features & NETIF_F_IP_CSUM))
17665 features |= NETIF_F_TSO;
17666 if (tg3_flag(tp, HW_TSO_2) || tg3_flag(tp, HW_TSO_3)) {
17667 if (features & NETIF_F_IPV6_CSUM)
17668 features |= NETIF_F_TSO6;
17669 if (tg3_flag(tp, HW_TSO_3) ||
17670 tg3_asic_rev(tp) == ASIC_REV_5761 ||
17671 (tg3_asic_rev(tp) == ASIC_REV_5784 &&
17672 tg3_chip_rev(tp) != CHIPREV_5784_AX) ||
17673 tg3_asic_rev(tp) == ASIC_REV_5785 ||
17674 tg3_asic_rev(tp) == ASIC_REV_57780)
17675 features |= NETIF_F_TSO_ECN;
17678 dev->features |= features;
17679 dev->vlan_features |= features;
17682 * Add loopback capability only for a subset of devices that support
17683 * MAC-LOOPBACK. Eventually this need to be enhanced to allow INT-PHY
17684 * loopback for the remaining devices.
17686 if (tg3_asic_rev(tp) != ASIC_REV_5780 &&
17687 !tg3_flag(tp, CPMU_PRESENT))
17688 /* Add the loopback capability */
17689 features |= NETIF_F_LOOPBACK;
17691 dev->hw_features |= features;
17692 dev->priv_flags |= IFF_UNICAST_FLT;
17694 if (tg3_chip_rev_id(tp) == CHIPREV_ID_5705_A1 &&
17695 !tg3_flag(tp, TSO_CAPABLE) &&
17696 !(tr32(TG3PCI_PCISTATE) & PCISTATE_BUS_SPEED_HIGH)) {
17697 tg3_flag_set(tp, MAX_RXPEND_64);
17698 tp->rx_pending = 63;
17701 err = tg3_get_device_address(tp);
17703 dev_err(&pdev->dev,
17704 "Could not obtain valid ethernet address, aborting\n");
17705 goto err_out_apeunmap;
17709 * Reset chip in case UNDI or EFI driver did not shutdown
17710 * DMA self test will enable WDMAC and we'll see (spurious)
17711 * pending DMA on the PCI bus at that point.
17713 if ((tr32(HOSTCC_MODE) & HOSTCC_MODE_ENABLE) ||
17714 (tr32(WDMAC_MODE) & WDMAC_MODE_ENABLE)) {
17715 tw32(MEMARB_MODE, MEMARB_MODE_ENABLE);
17716 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
17719 err = tg3_test_dma(tp);
17721 dev_err(&pdev->dev, "DMA engine test failed, aborting\n");
17722 goto err_out_apeunmap;
17725 intmbx = MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW;
17726 rcvmbx = MAILBOX_RCVRET_CON_IDX_0 + TG3_64BIT_REG_LOW;
17727 sndmbx = MAILBOX_SNDHOST_PROD_IDX_0 + TG3_64BIT_REG_LOW;
17728 for (i = 0; i < tp->irq_max; i++) {
17729 struct tg3_napi *tnapi = &tp->napi[i];
17732 tnapi->tx_pending = TG3_DEF_TX_RING_PENDING;
17734 tnapi->int_mbox = intmbx;
17740 tnapi->consmbox = rcvmbx;
17741 tnapi->prodmbox = sndmbx;
17744 tnapi->coal_now = HOSTCC_MODE_COAL_VEC1_NOW << (i - 1);
17746 tnapi->coal_now = HOSTCC_MODE_NOW;
17748 if (!tg3_flag(tp, SUPPORT_MSIX))
17752 * If we support MSIX, we'll be using RSS. If we're using
17753 * RSS, the first vector only handles link interrupts and the
17754 * remaining vectors handle rx and tx interrupts. Reuse the
17755 * mailbox values for the next iteration. The values we setup
17756 * above are still useful for the single vectored mode.
17771 pci_set_drvdata(pdev, dev);
17773 if (tg3_asic_rev(tp) == ASIC_REV_5719 ||
17774 tg3_asic_rev(tp) == ASIC_REV_5720 ||
17775 tg3_asic_rev(tp) == ASIC_REV_5762)
17776 tg3_flag_set(tp, PTP_CAPABLE);
17778 tg3_timer_init(tp);
17780 tg3_carrier_off(tp);
17782 err = register_netdev(dev);
17784 dev_err(&pdev->dev, "Cannot register net device, aborting\n");
17785 goto err_out_apeunmap;
17788 netdev_info(dev, "Tigon3 [partno(%s) rev %04x] (%s) MAC address %pM\n",
17789 tp->board_part_number,
17790 tg3_chip_rev_id(tp),
17791 tg3_bus_string(tp, str),
17794 if (tp->phy_flags & TG3_PHYFLG_IS_CONNECTED) {
17795 struct phy_device *phydev;
17796 phydev = tp->mdio_bus->phy_map[tp->phy_addr];
17798 "attached PHY driver [%s] (mii_bus:phy_addr=%s)\n",
17799 phydev->drv->name, dev_name(&phydev->dev));
17803 if (tp->phy_flags & TG3_PHYFLG_10_100_ONLY)
17804 ethtype = "10/100Base-TX";
17805 else if (tp->phy_flags & TG3_PHYFLG_ANY_SERDES)
17806 ethtype = "1000Base-SX";
17808 ethtype = "10/100/1000Base-T";
17810 netdev_info(dev, "attached PHY is %s (%s Ethernet) "
17811 "(WireSpeed[%d], EEE[%d])\n",
17812 tg3_phy_string(tp), ethtype,
17813 (tp->phy_flags & TG3_PHYFLG_NO_ETH_WIRE_SPEED) == 0,
17814 (tp->phy_flags & TG3_PHYFLG_EEE_CAP) != 0);
17817 netdev_info(dev, "RXcsums[%d] LinkChgREG[%d] MIirq[%d] ASF[%d] TSOcap[%d]\n",
17818 (dev->features & NETIF_F_RXCSUM) != 0,
17819 tg3_flag(tp, USE_LINKCHG_REG) != 0,
17820 (tp->phy_flags & TG3_PHYFLG_USE_MI_INTERRUPT) != 0,
17821 tg3_flag(tp, ENABLE_ASF) != 0,
17822 tg3_flag(tp, TSO_CAPABLE) != 0);
17823 netdev_info(dev, "dma_rwctrl[%08x] dma_mask[%d-bit]\n",
17825 pdev->dma_mask == DMA_BIT_MASK(32) ? 32 :
17826 ((u64)pdev->dma_mask) == DMA_BIT_MASK(40) ? 40 : 64);
17828 pci_save_state(pdev);
17834 iounmap(tp->aperegs);
17835 tp->aperegs = NULL;
17848 pci_release_regions(pdev);
17850 err_out_disable_pdev:
17851 if (pci_is_enabled(pdev))
17852 pci_disable_device(pdev);
17856 static void tg3_remove_one(struct pci_dev *pdev)
17858 struct net_device *dev = pci_get_drvdata(pdev);
17861 struct tg3 *tp = netdev_priv(dev);
17863 release_firmware(tp->fw);
17865 tg3_reset_task_cancel(tp);
17867 if (tg3_flag(tp, USE_PHYLIB)) {
17872 unregister_netdev(dev);
17874 iounmap(tp->aperegs);
17875 tp->aperegs = NULL;
17882 pci_release_regions(pdev);
17883 pci_disable_device(pdev);
17887 #ifdef CONFIG_PM_SLEEP
17888 static int tg3_suspend(struct device *device)
17890 struct pci_dev *pdev = to_pci_dev(device);
17891 struct net_device *dev = pci_get_drvdata(pdev);
17892 struct tg3 *tp = netdev_priv(dev);
17897 if (!netif_running(dev))
17900 tg3_reset_task_cancel(tp);
17902 tg3_netif_stop(tp);
17904 tg3_timer_stop(tp);
17906 tg3_full_lock(tp, 1);
17907 tg3_disable_ints(tp);
17908 tg3_full_unlock(tp);
17910 netif_device_detach(dev);
17912 tg3_full_lock(tp, 0);
17913 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
17914 tg3_flag_clear(tp, INIT_COMPLETE);
17915 tg3_full_unlock(tp);
17917 err = tg3_power_down_prepare(tp);
17921 tg3_full_lock(tp, 0);
17923 tg3_flag_set(tp, INIT_COMPLETE);
17924 err2 = tg3_restart_hw(tp, true);
17928 tg3_timer_start(tp);
17930 netif_device_attach(dev);
17931 tg3_netif_start(tp);
17934 tg3_full_unlock(tp);
17945 static int tg3_resume(struct device *device)
17947 struct pci_dev *pdev = to_pci_dev(device);
17948 struct net_device *dev = pci_get_drvdata(pdev);
17949 struct tg3 *tp = netdev_priv(dev);
17954 if (!netif_running(dev))
17957 netif_device_attach(dev);
17959 tg3_full_lock(tp, 0);
17961 tg3_ape_driver_state_change(tp, RESET_KIND_INIT);
17963 tg3_flag_set(tp, INIT_COMPLETE);
17964 err = tg3_restart_hw(tp,
17965 !(tp->phy_flags & TG3_PHYFLG_KEEP_LINK_ON_PWRDN));
17969 tg3_timer_start(tp);
17971 tg3_netif_start(tp);
17974 tg3_full_unlock(tp);
17983 #endif /* CONFIG_PM_SLEEP */
17985 static SIMPLE_DEV_PM_OPS(tg3_pm_ops, tg3_suspend, tg3_resume);
17987 static void tg3_shutdown(struct pci_dev *pdev)
17989 struct net_device *dev = pci_get_drvdata(pdev);
17990 struct tg3 *tp = netdev_priv(dev);
17993 netif_device_detach(dev);
17995 if (netif_running(dev))
17998 if (system_state == SYSTEM_POWER_OFF)
17999 tg3_power_down(tp);
18005 * tg3_io_error_detected - called when PCI error is detected
18006 * @pdev: Pointer to PCI device
18007 * @state: The current pci connection state
18009 * This function is called after a PCI bus error affecting
18010 * this device has been detected.
18012 static pci_ers_result_t tg3_io_error_detected(struct pci_dev *pdev,
18013 pci_channel_state_t state)
18015 struct net_device *netdev = pci_get_drvdata(pdev);
18016 struct tg3 *tp = netdev_priv(netdev);
18017 pci_ers_result_t err = PCI_ERS_RESULT_NEED_RESET;
18019 netdev_info(netdev, "PCI I/O error detected\n");
18023 /* We probably don't have netdev yet */
18024 if (!netdev || !netif_running(netdev))
18029 tg3_netif_stop(tp);
18031 tg3_timer_stop(tp);
18033 /* Want to make sure that the reset task doesn't run */
18034 tg3_reset_task_cancel(tp);
18036 netif_device_detach(netdev);
18038 /* Clean up software state, even if MMIO is blocked */
18039 tg3_full_lock(tp, 0);
18040 tg3_halt(tp, RESET_KIND_SHUTDOWN, 0);
18041 tg3_full_unlock(tp);
18044 if (state == pci_channel_io_perm_failure) {
18046 tg3_napi_enable(tp);
18049 err = PCI_ERS_RESULT_DISCONNECT;
18051 pci_disable_device(pdev);
18060 * tg3_io_slot_reset - called after the pci bus has been reset.
18061 * @pdev: Pointer to PCI device
18063 * Restart the card from scratch, as if from a cold-boot.
18064 * At this point, the card has exprienced a hard reset,
18065 * followed by fixups by BIOS, and has its config space
18066 * set up identically to what it was at cold boot.
18068 static pci_ers_result_t tg3_io_slot_reset(struct pci_dev *pdev)
18070 struct net_device *netdev = pci_get_drvdata(pdev);
18071 struct tg3 *tp = netdev_priv(netdev);
18072 pci_ers_result_t rc = PCI_ERS_RESULT_DISCONNECT;
18077 if (pci_enable_device(pdev)) {
18078 dev_err(&pdev->dev,
18079 "Cannot re-enable PCI device after reset.\n");
18083 pci_set_master(pdev);
18084 pci_restore_state(pdev);
18085 pci_save_state(pdev);
18087 if (!netdev || !netif_running(netdev)) {
18088 rc = PCI_ERS_RESULT_RECOVERED;
18092 err = tg3_power_up(tp);
18096 rc = PCI_ERS_RESULT_RECOVERED;
18099 if (rc != PCI_ERS_RESULT_RECOVERED && netdev && netif_running(netdev)) {
18100 tg3_napi_enable(tp);
18109 * tg3_io_resume - called when traffic can start flowing again.
18110 * @pdev: Pointer to PCI device
18112 * This callback is called when the error recovery driver tells
18113 * us that its OK to resume normal operation.
18115 static void tg3_io_resume(struct pci_dev *pdev)
18117 struct net_device *netdev = pci_get_drvdata(pdev);
18118 struct tg3 *tp = netdev_priv(netdev);
18123 if (!netif_running(netdev))
18126 tg3_full_lock(tp, 0);
18127 tg3_ape_driver_state_change(tp, RESET_KIND_INIT);
18128 tg3_flag_set(tp, INIT_COMPLETE);
18129 err = tg3_restart_hw(tp, true);
18131 tg3_full_unlock(tp);
18132 netdev_err(netdev, "Cannot restart hardware after reset.\n");
18136 netif_device_attach(netdev);
18138 tg3_timer_start(tp);
18140 tg3_netif_start(tp);
18142 tg3_full_unlock(tp);
18150 static const struct pci_error_handlers tg3_err_handler = {
18151 .error_detected = tg3_io_error_detected,
18152 .slot_reset = tg3_io_slot_reset,
18153 .resume = tg3_io_resume
18156 static struct pci_driver tg3_driver = {
18157 .name = DRV_MODULE_NAME,
18158 .id_table = tg3_pci_tbl,
18159 .probe = tg3_init_one,
18160 .remove = tg3_remove_one,
18161 .err_handler = &tg3_err_handler,
18162 .driver.pm = &tg3_pm_ops,
18163 .shutdown = tg3_shutdown,
18166 module_pci_driver(tg3_driver);