1 // SPDX-License-Identifier: GPL-2.0-only
3 * Broadcom GENET MDIO routines
5 * Copyright (c) 2014-2017 Broadcom
8 #include <linux/acpi.h>
9 #include <linux/types.h>
10 #include <linux/delay.h>
11 #include <linux/wait.h>
12 #include <linux/mii.h>
13 #include <linux/ethtool.h>
14 #include <linux/bitops.h>
15 #include <linux/netdevice.h>
16 #include <linux/platform_device.h>
17 #include <linux/phy.h>
18 #include <linux/phy_fixed.h>
19 #include <linux/brcmphy.h>
21 #include <linux/of_net.h>
22 #include <linux/of_mdio.h>
23 #include <linux/platform_data/bcmgenet.h>
24 #include <linux/platform_data/mdio-bcm-unimac.h>
28 static void bcmgenet_mac_config(struct net_device *dev)
30 struct bcmgenet_priv *priv = netdev_priv(dev);
31 struct phy_device *phydev = dev->phydev;
32 u32 reg, cmd_bits = 0;
36 if (phydev->speed == SPEED_1000)
37 cmd_bits = CMD_SPEED_1000;
38 else if (phydev->speed == SPEED_100)
39 cmd_bits = CMD_SPEED_100;
41 cmd_bits = CMD_SPEED_10;
42 cmd_bits <<= CMD_SPEED_SHIFT;
45 if (phydev->duplex != DUPLEX_FULL) {
46 cmd_bits |= CMD_HD_EN |
47 CMD_RX_PAUSE_IGNORE | CMD_TX_PAUSE_IGNORE;
49 /* pause capability defaults to Symmetric */
50 if (priv->autoneg_pause) {
51 bool tx_pause = 0, rx_pause = 0;
54 phy_get_pause(phydev, &tx_pause, &rx_pause);
57 cmd_bits |= CMD_TX_PAUSE_IGNORE;
59 cmd_bits |= CMD_RX_PAUSE_IGNORE;
64 cmd_bits |= CMD_RX_PAUSE_IGNORE;
66 cmd_bits |= CMD_TX_PAUSE_IGNORE;
69 /* Program UMAC and RGMII block based on established
70 * link speed, duplex, and pause. The speed set in
71 * umac->cmd tell RGMII block which clock to use for
72 * transmit -- 25MHz(100Mbps) or 125MHz(1Gbps).
73 * Receive clock is provided by the PHY.
75 reg = bcmgenet_ext_readl(priv, EXT_RGMII_OOB_CTRL);
77 bcmgenet_ext_writel(priv, reg, EXT_RGMII_OOB_CTRL);
79 reg = bcmgenet_umac_readl(priv, UMAC_CMD);
80 reg &= ~((CMD_SPEED_MASK << CMD_SPEED_SHIFT) |
82 CMD_RX_PAUSE_IGNORE | CMD_TX_PAUSE_IGNORE);
84 if (reg & CMD_SW_RESET) {
86 bcmgenet_umac_writel(priv, reg, UMAC_CMD);
88 reg |= CMD_TX_EN | CMD_RX_EN;
90 bcmgenet_umac_writel(priv, reg, UMAC_CMD);
92 active = phy_init_eee(phydev, 0) >= 0;
93 bcmgenet_eee_enable_set(dev,
94 priv->eee.eee_enabled && active,
95 priv->eee.tx_lpi_enabled);
98 /* setup netdev link state when PHY link status change and
99 * update UMAC and RGMII block when link up
101 void bcmgenet_mii_setup(struct net_device *dev)
103 struct bcmgenet_priv *priv = netdev_priv(dev);
104 struct phy_device *phydev = dev->phydev;
108 bcmgenet_mac_config(dev);
110 reg = bcmgenet_ext_readl(priv, EXT_RGMII_OOB_CTRL);
112 bcmgenet_ext_writel(priv, reg, EXT_RGMII_OOB_CTRL);
115 phy_print_status(phydev);
119 static int bcmgenet_fixed_phy_link_update(struct net_device *dev,
120 struct fixed_phy_status *status)
122 struct bcmgenet_priv *priv;
125 if (dev && dev->phydev && status) {
126 priv = netdev_priv(dev);
127 reg = bcmgenet_umac_readl(priv, UMAC_MODE);
128 status->link = !!(reg & MODE_LINK_STATUS);
134 void bcmgenet_phy_pause_set(struct net_device *dev, bool rx, bool tx)
136 struct phy_device *phydev = dev->phydev;
138 linkmode_mod_bit(ETHTOOL_LINK_MODE_Pause_BIT, phydev->advertising, rx);
139 linkmode_mod_bit(ETHTOOL_LINK_MODE_Asym_Pause_BIT, phydev->advertising,
141 phy_start_aneg(phydev);
143 mutex_lock(&phydev->lock);
145 bcmgenet_mac_config(dev);
146 mutex_unlock(&phydev->lock);
149 void bcmgenet_phy_power_set(struct net_device *dev, bool enable)
151 struct bcmgenet_priv *priv = netdev_priv(dev);
154 /* EXT_GPHY_CTRL is only valid for GENETv4 and onward */
155 if (GENET_IS_V4(priv) || priv->ephy_16nm) {
156 reg = bcmgenet_ext_readl(priv, EXT_GPHY_CTRL);
158 reg &= ~EXT_CK25_DIS;
159 bcmgenet_ext_writel(priv, reg, EXT_GPHY_CTRL);
162 reg &= ~(EXT_CFG_IDDQ_BIAS | EXT_CFG_PWR_DOWN |
163 EXT_CFG_IDDQ_GLOBAL_PWR);
164 reg |= EXT_GPHY_RESET;
165 bcmgenet_ext_writel(priv, reg, EXT_GPHY_CTRL);
168 reg &= ~EXT_GPHY_RESET;
170 reg |= EXT_CFG_IDDQ_BIAS | EXT_CFG_PWR_DOWN |
171 EXT_GPHY_RESET | EXT_CFG_IDDQ_GLOBAL_PWR;
172 bcmgenet_ext_writel(priv, reg, EXT_GPHY_CTRL);
176 bcmgenet_ext_writel(priv, reg, EXT_GPHY_CTRL);
183 static void bcmgenet_moca_phy_setup(struct bcmgenet_priv *priv)
185 if (priv->hw_params->flags & GENET_HAS_MOCA_LINK_DET)
186 fixed_phy_set_link_update(priv->dev->phydev,
187 bcmgenet_fixed_phy_link_update);
190 int bcmgenet_mii_config(struct net_device *dev, bool init)
192 struct bcmgenet_priv *priv = netdev_priv(dev);
193 struct phy_device *phydev = dev->phydev;
194 struct device *kdev = &priv->pdev->dev;
195 const char *phy_name = NULL;
200 switch (priv->phy_interface) {
201 case PHY_INTERFACE_MODE_INTERNAL:
202 phy_name = "internal PHY";
204 case PHY_INTERFACE_MODE_MOCA:
205 /* Irrespective of the actually configured PHY speed (100 or
206 * 1000) GENETv4 only has an internal GPHY so we will just end
207 * up masking the Gigabit features from what we support, not
208 * switching to the EPHY
210 if (GENET_IS_V4(priv))
211 port_ctrl = PORT_MODE_INT_GPHY;
213 port_ctrl = PORT_MODE_INT_EPHY;
217 if (!GENET_IS_V5(priv))
218 port_ctrl |= LED_ACT_SOURCE_MAC;
219 bcmgenet_moca_phy_setup(priv);
223 case PHY_INTERFACE_MODE_MII:
224 phy_name = "external MII";
225 phy_set_max_speed(phydev, SPEED_100);
226 port_ctrl = PORT_MODE_EXT_EPHY;
229 case PHY_INTERFACE_MODE_REVMII:
230 phy_name = "external RvMII";
231 /* of_mdiobus_register took care of reading the 'max-speed'
232 * PHY property for us, effectively limiting the PHY supported
233 * capabilities, use that knowledge to also configure the
234 * Reverse MII interface correctly.
236 if (linkmode_test_bit(ETHTOOL_LINK_MODE_1000baseT_Full_BIT,
237 dev->phydev->supported))
238 port_ctrl = PORT_MODE_EXT_RVMII_50;
240 port_ctrl = PORT_MODE_EXT_RVMII_25;
243 case PHY_INTERFACE_MODE_RGMII:
244 /* RGMII_NO_ID: TXC transitions at the same time as TXD
245 * (requires PCB or receiver-side delay)
247 * ID is implicitly disabled for 100Mbps (RG)MII operation.
249 phy_name = "external RGMII (no delay)";
250 id_mode_dis = BIT(16);
251 port_ctrl = PORT_MODE_EXT_GPHY;
254 case PHY_INTERFACE_MODE_RGMII_TXID:
255 /* RGMII_TXID: Add 2ns delay on TXC (90 degree shift) */
256 phy_name = "external RGMII (TX delay)";
257 port_ctrl = PORT_MODE_EXT_GPHY;
260 case PHY_INTERFACE_MODE_RGMII_RXID:
261 phy_name = "external RGMII (RX delay)";
262 port_ctrl = PORT_MODE_EXT_GPHY;
265 dev_err(kdev, "unknown phy mode: %d\n", priv->phy_interface);
269 bcmgenet_sys_writel(priv, port_ctrl, SYS_PORT_CTRL);
271 priv->ext_phy = !priv->internal_phy &&
272 (priv->phy_interface != PHY_INTERFACE_MODE_MOCA);
274 /* This is an external PHY (xMII), so we need to enable the RGMII
275 * block for the interface to work, unconditionally clear the
276 * Out-of-band disable since we do not need it.
278 reg = bcmgenet_ext_readl(priv, EXT_RGMII_OOB_CTRL);
283 if (GENET_IS_V1(priv) || GENET_IS_V2(priv) || GENET_IS_V3(priv))
284 reg |= RGMII_MODE_EN_V123;
286 reg |= RGMII_MODE_EN;
288 bcmgenet_ext_writel(priv, reg, EXT_RGMII_OOB_CTRL);
291 dev_info(kdev, "configuring instance for %s\n", phy_name);
296 int bcmgenet_mii_probe(struct net_device *dev)
298 struct bcmgenet_priv *priv = netdev_priv(dev);
299 struct device *kdev = &priv->pdev->dev;
300 struct device_node *dn = kdev->of_node;
301 phy_interface_t phy_iface = priv->phy_interface;
302 struct phy_device *phydev;
303 u32 phy_flags = PHY_BRCM_AUTO_PWRDWN_ENABLE |
304 PHY_BRCM_DIS_TXCRXC_NOENRGY |
305 PHY_BRCM_IDDQ_SUSPEND;
308 /* Communicate the integrated PHY revision */
309 if (priv->internal_phy)
310 phy_flags = priv->gphy_rev;
312 /* This is an ugly quirk but we have not been correctly interpreting
313 * the phy_interface values and we have done that across different
314 * drivers, so at least we are consistent in our mistakes.
316 * When the Generic PHY driver is in use either the PHY has been
317 * strapped or programmed correctly by the boot loader so we should
318 * stick to our incorrect interpretation since we have validated it.
320 * Now when a dedicated PHY driver is in use, we need to reverse the
321 * meaning of the phy_interface_mode values to something that the PHY
322 * driver will interpret and act on such that we have two mistakes
323 * canceling themselves so to speak. We only do this for the two
324 * modes that GENET driver officially supports on Broadcom STB chips:
325 * PHY_INTERFACE_MODE_RGMII and PHY_INTERFACE_MODE_RGMII_TXID. Other
326 * modes are not *officially* supported with the boot loader and the
327 * scripted environment generating Device Tree blobs for those
330 * Note that internal PHY, MoCA and fixed-link configurations are not
331 * affected because they use different phy_interface_t values or the
332 * Generic PHY driver.
334 switch (priv->phy_interface) {
335 case PHY_INTERFACE_MODE_RGMII:
336 phy_iface = PHY_INTERFACE_MODE_RGMII_ID;
338 case PHY_INTERFACE_MODE_RGMII_TXID:
339 phy_iface = PHY_INTERFACE_MODE_RGMII_RXID;
346 phydev = of_phy_connect(dev, priv->phy_dn, bcmgenet_mii_setup,
347 phy_flags, phy_iface);
349 pr_err("could not attach to PHY\n");
353 if (has_acpi_companion(kdev)) {
354 char mdio_bus_id[MII_BUS_ID_SIZE];
355 struct mii_bus *unimacbus;
357 snprintf(mdio_bus_id, MII_BUS_ID_SIZE, "%s-%d",
358 UNIMAC_MDIO_DRV_NAME, priv->pdev->id);
360 unimacbus = mdio_find_bus(mdio_bus_id);
362 pr_err("Unable to find mii\n");
365 phydev = phy_find_first(unimacbus);
366 put_device(&unimacbus->dev);
368 pr_err("Unable to find PHY\n");
372 phydev = dev->phydev;
374 phydev->dev_flags = phy_flags;
376 ret = phy_connect_direct(dev, phydev, bcmgenet_mii_setup,
379 pr_err("could not attach to PHY\n");
384 /* Configure port multiplexer based on what the probed PHY device since
385 * reading the 'max-speed' property determines the maximum supported
386 * PHY speed which is needed for bcmgenet_mii_config() to configure
387 * things appropriately.
389 ret = bcmgenet_mii_config(dev, true);
391 phy_disconnect(dev->phydev);
395 /* The internal PHY has its link interrupts routed to the
396 * Ethernet MAC ISRs. On GENETv5 there is a hardware issue
397 * that prevents the signaling of link UP interrupts when
398 * the link operates at 10Mbps, so fallback to polling for
399 * those versions of GENET.
401 if (priv->internal_phy && !GENET_IS_V5(priv))
402 dev->phydev->irq = PHY_MAC_INTERRUPT;
404 /* Indicate that the MAC is responsible for PHY PM */
405 dev->phydev->mac_managed_pm = true;
410 static struct device_node *bcmgenet_mii_of_find_mdio(struct bcmgenet_priv *priv)
412 struct device_node *dn = priv->pdev->dev.of_node;
413 struct device *kdev = &priv->pdev->dev;
416 compat = kasprintf(GFP_KERNEL, "brcm,genet-mdio-v%d", priv->version);
420 priv->mdio_dn = of_get_compatible_child(dn, compat);
422 if (!priv->mdio_dn) {
423 dev_err(kdev, "unable to find MDIO bus node\n");
427 return priv->mdio_dn;
430 static void bcmgenet_mii_pdata_init(struct bcmgenet_priv *priv,
431 struct unimac_mdio_pdata *ppd)
433 struct device *kdev = &priv->pdev->dev;
434 struct bcmgenet_platform_data *pd = kdev->platform_data;
436 if (pd->phy_interface != PHY_INTERFACE_MODE_MOCA && pd->mdio_enabled) {
438 * Internal or external PHY with MDIO access
440 if (pd->phy_address >= 0 && pd->phy_address < PHY_MAX_ADDR)
441 ppd->phy_mask = 1 << pd->phy_address;
447 static int bcmgenet_mii_wait(void *wait_func_data)
449 struct bcmgenet_priv *priv = wait_func_data;
451 wait_event_timeout(priv->wq,
452 !(bcmgenet_umac_readl(priv, UMAC_MDIO_CMD)
458 static int bcmgenet_mii_register(struct bcmgenet_priv *priv)
460 struct platform_device *pdev = priv->pdev;
461 struct bcmgenet_platform_data *pdata = pdev->dev.platform_data;
462 struct device_node *dn = pdev->dev.of_node;
463 struct unimac_mdio_pdata ppd;
464 struct platform_device *ppdev;
465 struct resource *pres, res;
468 pres = platform_get_resource(pdev, IORESOURCE_MEM, 0);
470 dev_err(&pdev->dev, "Invalid resource\n");
473 memset(&res, 0, sizeof(res));
474 memset(&ppd, 0, sizeof(ppd));
476 ppd.wait_func = bcmgenet_mii_wait;
477 ppd.wait_func_data = priv;
478 ppd.bus_name = "bcmgenet MII bus";
479 /* Pass a reference to our "main" clock which is used for MDIO
484 /* Unimac MDIO bus controller starts at UniMAC offset + MDIO_CMD
485 * and is 2 * 32-bits word long, 8 bytes total.
487 res.start = pres->start + GENET_UMAC_OFF + UMAC_MDIO_CMD;
488 res.end = res.start + 8;
489 res.flags = IORESOURCE_MEM;
492 id = of_alias_get_id(dn, "eth");
496 ppdev = platform_device_alloc(UNIMAC_MDIO_DRV_NAME, id);
500 /* Retain this platform_device pointer for later cleanup */
501 priv->mii_pdev = ppdev;
502 ppdev->dev.parent = &pdev->dev;
504 ppdev->dev.of_node = bcmgenet_mii_of_find_mdio(priv);
506 bcmgenet_mii_pdata_init(priv, &ppd);
510 ret = platform_device_add_resources(ppdev, &res, 1);
514 ret = platform_device_add_data(ppdev, &ppd, sizeof(ppd));
518 ret = platform_device_add(ppdev);
524 platform_device_put(ppdev);
528 static int bcmgenet_phy_interface_init(struct bcmgenet_priv *priv)
530 struct device *kdev = &priv->pdev->dev;
531 int phy_mode = device_get_phy_mode(kdev);
534 dev_err(kdev, "invalid PHY mode property\n");
538 priv->phy_interface = phy_mode;
540 /* We need to specifically look up whether this PHY interface is
541 * internal or not *before* we even try to probe the PHY driver
542 * over MDIO as we may have shut down the internal PHY for power
545 if (priv->phy_interface == PHY_INTERFACE_MODE_INTERNAL)
546 priv->internal_phy = true;
551 static int bcmgenet_mii_of_init(struct bcmgenet_priv *priv)
553 struct device_node *dn = priv->pdev->dev.of_node;
554 struct phy_device *phydev;
557 /* Fetch the PHY phandle */
558 priv->phy_dn = of_parse_phandle(dn, "phy-handle", 0);
560 /* In the case of a fixed PHY, the DT node associated
561 * to the PHY is the Ethernet MAC DT node.
563 if (!priv->phy_dn && of_phy_is_fixed_link(dn)) {
564 ret = of_phy_register_fixed_link(dn);
568 priv->phy_dn = of_node_get(dn);
571 /* Get the link mode */
572 ret = bcmgenet_phy_interface_init(priv);
576 /* Make sure we initialize MoCA PHYs with a link down */
577 if (priv->phy_interface == PHY_INTERFACE_MODE_MOCA) {
578 phydev = of_phy_find_device(dn);
581 put_device(&phydev->mdio.dev);
588 static int bcmgenet_mii_pd_init(struct bcmgenet_priv *priv)
590 struct device *kdev = &priv->pdev->dev;
591 struct bcmgenet_platform_data *pd = kdev->platform_data;
592 char phy_name[MII_BUS_ID_SIZE + 3];
593 char mdio_bus_id[MII_BUS_ID_SIZE];
594 struct phy_device *phydev;
596 snprintf(mdio_bus_id, MII_BUS_ID_SIZE, "%s-%d",
597 UNIMAC_MDIO_DRV_NAME, priv->pdev->id);
599 if (pd->phy_interface != PHY_INTERFACE_MODE_MOCA && pd->mdio_enabled) {
600 snprintf(phy_name, MII_BUS_ID_SIZE, PHY_ID_FMT,
601 mdio_bus_id, pd->phy_address);
604 * Internal or external PHY with MDIO access
606 phydev = phy_attach(priv->dev, phy_name, pd->phy_interface);
607 if (IS_ERR(phydev)) {
608 dev_err(kdev, "failed to register PHY device\n");
609 return PTR_ERR(phydev);
613 * MoCA port or no MDIO access.
614 * Use fixed PHY to represent the link layer.
616 struct fixed_phy_status fphy_status = {
618 .speed = pd->phy_speed,
619 .duplex = pd->phy_duplex,
624 phydev = fixed_phy_register(PHY_POLL, &fphy_status, NULL);
625 if (IS_ERR(phydev)) {
626 dev_err(kdev, "failed to register fixed PHY device\n");
627 return PTR_ERR(phydev);
630 /* Make sure we initialize MoCA PHYs with a link down */
635 priv->phy_interface = pd->phy_interface;
640 static int bcmgenet_mii_bus_init(struct bcmgenet_priv *priv)
642 struct device *kdev = &priv->pdev->dev;
643 struct device_node *dn = kdev->of_node;
646 return bcmgenet_mii_of_init(priv);
647 else if (has_acpi_companion(kdev))
648 return bcmgenet_phy_interface_init(priv);
650 return bcmgenet_mii_pd_init(priv);
653 int bcmgenet_mii_init(struct net_device *dev)
655 struct bcmgenet_priv *priv = netdev_priv(dev);
658 ret = bcmgenet_mii_register(priv);
662 ret = bcmgenet_mii_bus_init(priv);
669 bcmgenet_mii_exit(dev);
673 void bcmgenet_mii_exit(struct net_device *dev)
675 struct bcmgenet_priv *priv = netdev_priv(dev);
676 struct device_node *dn = priv->pdev->dev.of_node;
678 if (of_phy_is_fixed_link(dn))
679 of_phy_deregister_fixed_link(dn);
680 of_node_put(priv->phy_dn);
681 platform_device_unregister(priv->mii_pdev);