1 /* Broadcom NetXtreme-C/E network driver.
3 * Copyright (c) 2014-2016 Broadcom Corporation
4 * Copyright (c) 2016-2017 Broadcom Limited
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation.
11 #include <linux/ctype.h>
12 #include <linux/stringify.h>
13 #include <linux/ethtool.h>
14 #include <linux/linkmode.h>
15 #include <linux/interrupt.h>
16 #include <linux/pci.h>
17 #include <linux/etherdevice.h>
18 #include <linux/crc32.h>
19 #include <linux/firmware.h>
20 #include <linux/utsname.h>
21 #include <linux/time.h>
25 #include "bnxt_ethtool.h"
26 #include "bnxt_nvm_defs.h" /* NVRAM content constant and structure defs */
27 #include "bnxt_fw_hdr.h" /* Firmware hdr constant and structure defs */
28 #include "bnxt_coredump.h"
29 #define FLASH_NVRAM_TIMEOUT ((HWRM_CMD_TIMEOUT) * 100)
30 #define FLASH_PACKAGE_TIMEOUT ((HWRM_CMD_TIMEOUT) * 200)
31 #define INSTALL_PACKAGE_TIMEOUT ((HWRM_CMD_TIMEOUT) * 200)
33 static u32 bnxt_get_msglevel(struct net_device *dev)
35 struct bnxt *bp = netdev_priv(dev);
37 return bp->msg_enable;
40 static void bnxt_set_msglevel(struct net_device *dev, u32 value)
42 struct bnxt *bp = netdev_priv(dev);
44 bp->msg_enable = value;
47 static int bnxt_get_coalesce(struct net_device *dev,
48 struct ethtool_coalesce *coal)
50 struct bnxt *bp = netdev_priv(dev);
51 struct bnxt_coal *hw_coal;
54 memset(coal, 0, sizeof(*coal));
56 coal->use_adaptive_rx_coalesce = bp->flags & BNXT_FLAG_DIM;
58 hw_coal = &bp->rx_coal;
59 mult = hw_coal->bufs_per_record;
60 coal->rx_coalesce_usecs = hw_coal->coal_ticks;
61 coal->rx_max_coalesced_frames = hw_coal->coal_bufs / mult;
62 coal->rx_coalesce_usecs_irq = hw_coal->coal_ticks_irq;
63 coal->rx_max_coalesced_frames_irq = hw_coal->coal_bufs_irq / mult;
65 hw_coal = &bp->tx_coal;
66 mult = hw_coal->bufs_per_record;
67 coal->tx_coalesce_usecs = hw_coal->coal_ticks;
68 coal->tx_max_coalesced_frames = hw_coal->coal_bufs / mult;
69 coal->tx_coalesce_usecs_irq = hw_coal->coal_ticks_irq;
70 coal->tx_max_coalesced_frames_irq = hw_coal->coal_bufs_irq / mult;
72 coal->stats_block_coalesce_usecs = bp->stats_coal_ticks;
77 static int bnxt_set_coalesce(struct net_device *dev,
78 struct ethtool_coalesce *coal)
80 struct bnxt *bp = netdev_priv(dev);
81 bool update_stats = false;
82 struct bnxt_coal *hw_coal;
86 if (coal->use_adaptive_rx_coalesce) {
87 bp->flags |= BNXT_FLAG_DIM;
89 if (bp->flags & BNXT_FLAG_DIM) {
90 bp->flags &= ~(BNXT_FLAG_DIM);
95 hw_coal = &bp->rx_coal;
96 mult = hw_coal->bufs_per_record;
97 hw_coal->coal_ticks = coal->rx_coalesce_usecs;
98 hw_coal->coal_bufs = coal->rx_max_coalesced_frames * mult;
99 hw_coal->coal_ticks_irq = coal->rx_coalesce_usecs_irq;
100 hw_coal->coal_bufs_irq = coal->rx_max_coalesced_frames_irq * mult;
102 hw_coal = &bp->tx_coal;
103 mult = hw_coal->bufs_per_record;
104 hw_coal->coal_ticks = coal->tx_coalesce_usecs;
105 hw_coal->coal_bufs = coal->tx_max_coalesced_frames * mult;
106 hw_coal->coal_ticks_irq = coal->tx_coalesce_usecs_irq;
107 hw_coal->coal_bufs_irq = coal->tx_max_coalesced_frames_irq * mult;
109 if (bp->stats_coal_ticks != coal->stats_block_coalesce_usecs) {
110 u32 stats_ticks = coal->stats_block_coalesce_usecs;
112 /* Allow 0, which means disable. */
114 stats_ticks = clamp_t(u32, stats_ticks,
115 BNXT_MIN_STATS_COAL_TICKS,
116 BNXT_MAX_STATS_COAL_TICKS);
117 stats_ticks = rounddown(stats_ticks, BNXT_MIN_STATS_COAL_TICKS);
118 bp->stats_coal_ticks = stats_ticks;
119 if (bp->stats_coal_ticks)
120 bp->current_interval =
121 bp->stats_coal_ticks * HZ / 1000000;
123 bp->current_interval = BNXT_TIMER_INTERVAL;
128 if (netif_running(dev)) {
130 rc = bnxt_close_nic(bp, true, false);
132 rc = bnxt_open_nic(bp, true, false);
134 rc = bnxt_hwrm_set_coal(bp);
141 static const char * const bnxt_ring_rx_stats_str[] = {
152 static const char * const bnxt_ring_tx_stats_str[] = {
163 static const char * const bnxt_ring_tpa_stats_str[] = {
170 static const char * const bnxt_ring_tpa2_stats_str[] = {
171 "rx_tpa_eligible_pkt",
172 "rx_tpa_eligible_bytes",
179 static const char * const bnxt_rx_sw_stats_str[] = {
185 static const char * const bnxt_cmn_sw_stats_str[] = {
189 #define BNXT_RX_STATS_ENTRY(counter) \
190 { BNXT_RX_STATS_OFFSET(counter), __stringify(counter) }
192 #define BNXT_TX_STATS_ENTRY(counter) \
193 { BNXT_TX_STATS_OFFSET(counter), __stringify(counter) }
195 #define BNXT_RX_STATS_EXT_ENTRY(counter) \
196 { BNXT_RX_STATS_EXT_OFFSET(counter), __stringify(counter) }
198 #define BNXT_TX_STATS_EXT_ENTRY(counter) \
199 { BNXT_TX_STATS_EXT_OFFSET(counter), __stringify(counter) }
201 #define BNXT_RX_STATS_EXT_PFC_ENTRY(n) \
202 BNXT_RX_STATS_EXT_ENTRY(pfc_pri##n##_rx_duration_us), \
203 BNXT_RX_STATS_EXT_ENTRY(pfc_pri##n##_rx_transitions)
205 #define BNXT_TX_STATS_EXT_PFC_ENTRY(n) \
206 BNXT_TX_STATS_EXT_ENTRY(pfc_pri##n##_tx_duration_us), \
207 BNXT_TX_STATS_EXT_ENTRY(pfc_pri##n##_tx_transitions)
209 #define BNXT_RX_STATS_EXT_PFC_ENTRIES \
210 BNXT_RX_STATS_EXT_PFC_ENTRY(0), \
211 BNXT_RX_STATS_EXT_PFC_ENTRY(1), \
212 BNXT_RX_STATS_EXT_PFC_ENTRY(2), \
213 BNXT_RX_STATS_EXT_PFC_ENTRY(3), \
214 BNXT_RX_STATS_EXT_PFC_ENTRY(4), \
215 BNXT_RX_STATS_EXT_PFC_ENTRY(5), \
216 BNXT_RX_STATS_EXT_PFC_ENTRY(6), \
217 BNXT_RX_STATS_EXT_PFC_ENTRY(7)
219 #define BNXT_TX_STATS_EXT_PFC_ENTRIES \
220 BNXT_TX_STATS_EXT_PFC_ENTRY(0), \
221 BNXT_TX_STATS_EXT_PFC_ENTRY(1), \
222 BNXT_TX_STATS_EXT_PFC_ENTRY(2), \
223 BNXT_TX_STATS_EXT_PFC_ENTRY(3), \
224 BNXT_TX_STATS_EXT_PFC_ENTRY(4), \
225 BNXT_TX_STATS_EXT_PFC_ENTRY(5), \
226 BNXT_TX_STATS_EXT_PFC_ENTRY(6), \
227 BNXT_TX_STATS_EXT_PFC_ENTRY(7)
229 #define BNXT_RX_STATS_EXT_COS_ENTRY(n) \
230 BNXT_RX_STATS_EXT_ENTRY(rx_bytes_cos##n), \
231 BNXT_RX_STATS_EXT_ENTRY(rx_packets_cos##n)
233 #define BNXT_TX_STATS_EXT_COS_ENTRY(n) \
234 BNXT_TX_STATS_EXT_ENTRY(tx_bytes_cos##n), \
235 BNXT_TX_STATS_EXT_ENTRY(tx_packets_cos##n)
237 #define BNXT_RX_STATS_EXT_COS_ENTRIES \
238 BNXT_RX_STATS_EXT_COS_ENTRY(0), \
239 BNXT_RX_STATS_EXT_COS_ENTRY(1), \
240 BNXT_RX_STATS_EXT_COS_ENTRY(2), \
241 BNXT_RX_STATS_EXT_COS_ENTRY(3), \
242 BNXT_RX_STATS_EXT_COS_ENTRY(4), \
243 BNXT_RX_STATS_EXT_COS_ENTRY(5), \
244 BNXT_RX_STATS_EXT_COS_ENTRY(6), \
245 BNXT_RX_STATS_EXT_COS_ENTRY(7) \
247 #define BNXT_TX_STATS_EXT_COS_ENTRIES \
248 BNXT_TX_STATS_EXT_COS_ENTRY(0), \
249 BNXT_TX_STATS_EXT_COS_ENTRY(1), \
250 BNXT_TX_STATS_EXT_COS_ENTRY(2), \
251 BNXT_TX_STATS_EXT_COS_ENTRY(3), \
252 BNXT_TX_STATS_EXT_COS_ENTRY(4), \
253 BNXT_TX_STATS_EXT_COS_ENTRY(5), \
254 BNXT_TX_STATS_EXT_COS_ENTRY(6), \
255 BNXT_TX_STATS_EXT_COS_ENTRY(7) \
257 #define BNXT_RX_STATS_EXT_DISCARD_COS_ENTRY(n) \
258 BNXT_RX_STATS_EXT_ENTRY(rx_discard_bytes_cos##n), \
259 BNXT_RX_STATS_EXT_ENTRY(rx_discard_packets_cos##n)
261 #define BNXT_RX_STATS_EXT_DISCARD_COS_ENTRIES \
262 BNXT_RX_STATS_EXT_DISCARD_COS_ENTRY(0), \
263 BNXT_RX_STATS_EXT_DISCARD_COS_ENTRY(1), \
264 BNXT_RX_STATS_EXT_DISCARD_COS_ENTRY(2), \
265 BNXT_RX_STATS_EXT_DISCARD_COS_ENTRY(3), \
266 BNXT_RX_STATS_EXT_DISCARD_COS_ENTRY(4), \
267 BNXT_RX_STATS_EXT_DISCARD_COS_ENTRY(5), \
268 BNXT_RX_STATS_EXT_DISCARD_COS_ENTRY(6), \
269 BNXT_RX_STATS_EXT_DISCARD_COS_ENTRY(7)
271 #define BNXT_RX_STATS_PRI_ENTRY(counter, n) \
272 { BNXT_RX_STATS_EXT_OFFSET(counter##_cos0), \
273 __stringify(counter##_pri##n) }
275 #define BNXT_TX_STATS_PRI_ENTRY(counter, n) \
276 { BNXT_TX_STATS_EXT_OFFSET(counter##_cos0), \
277 __stringify(counter##_pri##n) }
279 #define BNXT_RX_STATS_PRI_ENTRIES(counter) \
280 BNXT_RX_STATS_PRI_ENTRY(counter, 0), \
281 BNXT_RX_STATS_PRI_ENTRY(counter, 1), \
282 BNXT_RX_STATS_PRI_ENTRY(counter, 2), \
283 BNXT_RX_STATS_PRI_ENTRY(counter, 3), \
284 BNXT_RX_STATS_PRI_ENTRY(counter, 4), \
285 BNXT_RX_STATS_PRI_ENTRY(counter, 5), \
286 BNXT_RX_STATS_PRI_ENTRY(counter, 6), \
287 BNXT_RX_STATS_PRI_ENTRY(counter, 7)
289 #define BNXT_TX_STATS_PRI_ENTRIES(counter) \
290 BNXT_TX_STATS_PRI_ENTRY(counter, 0), \
291 BNXT_TX_STATS_PRI_ENTRY(counter, 1), \
292 BNXT_TX_STATS_PRI_ENTRY(counter, 2), \
293 BNXT_TX_STATS_PRI_ENTRY(counter, 3), \
294 BNXT_TX_STATS_PRI_ENTRY(counter, 4), \
295 BNXT_TX_STATS_PRI_ENTRY(counter, 5), \
296 BNXT_TX_STATS_PRI_ENTRY(counter, 6), \
297 BNXT_TX_STATS_PRI_ENTRY(counter, 7)
306 char string[ETH_GSTRING_LEN];
307 } bnxt_sw_func_stats[] = {
308 {0, "rx_total_discard_pkts"},
309 {0, "tx_total_discard_pkts"},
312 #define NUM_RING_RX_SW_STATS ARRAY_SIZE(bnxt_rx_sw_stats_str)
313 #define NUM_RING_CMN_SW_STATS ARRAY_SIZE(bnxt_cmn_sw_stats_str)
314 #define NUM_RING_RX_HW_STATS ARRAY_SIZE(bnxt_ring_rx_stats_str)
315 #define NUM_RING_TX_HW_STATS ARRAY_SIZE(bnxt_ring_tx_stats_str)
317 static const struct {
319 char string[ETH_GSTRING_LEN];
320 } bnxt_port_stats_arr[] = {
321 BNXT_RX_STATS_ENTRY(rx_64b_frames),
322 BNXT_RX_STATS_ENTRY(rx_65b_127b_frames),
323 BNXT_RX_STATS_ENTRY(rx_128b_255b_frames),
324 BNXT_RX_STATS_ENTRY(rx_256b_511b_frames),
325 BNXT_RX_STATS_ENTRY(rx_512b_1023b_frames),
326 BNXT_RX_STATS_ENTRY(rx_1024b_1518b_frames),
327 BNXT_RX_STATS_ENTRY(rx_good_vlan_frames),
328 BNXT_RX_STATS_ENTRY(rx_1519b_2047b_frames),
329 BNXT_RX_STATS_ENTRY(rx_2048b_4095b_frames),
330 BNXT_RX_STATS_ENTRY(rx_4096b_9216b_frames),
331 BNXT_RX_STATS_ENTRY(rx_9217b_16383b_frames),
332 BNXT_RX_STATS_ENTRY(rx_total_frames),
333 BNXT_RX_STATS_ENTRY(rx_ucast_frames),
334 BNXT_RX_STATS_ENTRY(rx_mcast_frames),
335 BNXT_RX_STATS_ENTRY(rx_bcast_frames),
336 BNXT_RX_STATS_ENTRY(rx_fcs_err_frames),
337 BNXT_RX_STATS_ENTRY(rx_ctrl_frames),
338 BNXT_RX_STATS_ENTRY(rx_pause_frames),
339 BNXT_RX_STATS_ENTRY(rx_pfc_frames),
340 BNXT_RX_STATS_ENTRY(rx_align_err_frames),
341 BNXT_RX_STATS_ENTRY(rx_ovrsz_frames),
342 BNXT_RX_STATS_ENTRY(rx_jbr_frames),
343 BNXT_RX_STATS_ENTRY(rx_mtu_err_frames),
344 BNXT_RX_STATS_ENTRY(rx_tagged_frames),
345 BNXT_RX_STATS_ENTRY(rx_double_tagged_frames),
346 BNXT_RX_STATS_ENTRY(rx_good_frames),
347 BNXT_RX_STATS_ENTRY(rx_pfc_ena_frames_pri0),
348 BNXT_RX_STATS_ENTRY(rx_pfc_ena_frames_pri1),
349 BNXT_RX_STATS_ENTRY(rx_pfc_ena_frames_pri2),
350 BNXT_RX_STATS_ENTRY(rx_pfc_ena_frames_pri3),
351 BNXT_RX_STATS_ENTRY(rx_pfc_ena_frames_pri4),
352 BNXT_RX_STATS_ENTRY(rx_pfc_ena_frames_pri5),
353 BNXT_RX_STATS_ENTRY(rx_pfc_ena_frames_pri6),
354 BNXT_RX_STATS_ENTRY(rx_pfc_ena_frames_pri7),
355 BNXT_RX_STATS_ENTRY(rx_undrsz_frames),
356 BNXT_RX_STATS_ENTRY(rx_eee_lpi_events),
357 BNXT_RX_STATS_ENTRY(rx_eee_lpi_duration),
358 BNXT_RX_STATS_ENTRY(rx_bytes),
359 BNXT_RX_STATS_ENTRY(rx_runt_bytes),
360 BNXT_RX_STATS_ENTRY(rx_runt_frames),
361 BNXT_RX_STATS_ENTRY(rx_stat_discard),
362 BNXT_RX_STATS_ENTRY(rx_stat_err),
364 BNXT_TX_STATS_ENTRY(tx_64b_frames),
365 BNXT_TX_STATS_ENTRY(tx_65b_127b_frames),
366 BNXT_TX_STATS_ENTRY(tx_128b_255b_frames),
367 BNXT_TX_STATS_ENTRY(tx_256b_511b_frames),
368 BNXT_TX_STATS_ENTRY(tx_512b_1023b_frames),
369 BNXT_TX_STATS_ENTRY(tx_1024b_1518b_frames),
370 BNXT_TX_STATS_ENTRY(tx_good_vlan_frames),
371 BNXT_TX_STATS_ENTRY(tx_1519b_2047b_frames),
372 BNXT_TX_STATS_ENTRY(tx_2048b_4095b_frames),
373 BNXT_TX_STATS_ENTRY(tx_4096b_9216b_frames),
374 BNXT_TX_STATS_ENTRY(tx_9217b_16383b_frames),
375 BNXT_TX_STATS_ENTRY(tx_good_frames),
376 BNXT_TX_STATS_ENTRY(tx_total_frames),
377 BNXT_TX_STATS_ENTRY(tx_ucast_frames),
378 BNXT_TX_STATS_ENTRY(tx_mcast_frames),
379 BNXT_TX_STATS_ENTRY(tx_bcast_frames),
380 BNXT_TX_STATS_ENTRY(tx_pause_frames),
381 BNXT_TX_STATS_ENTRY(tx_pfc_frames),
382 BNXT_TX_STATS_ENTRY(tx_jabber_frames),
383 BNXT_TX_STATS_ENTRY(tx_fcs_err_frames),
384 BNXT_TX_STATS_ENTRY(tx_err),
385 BNXT_TX_STATS_ENTRY(tx_fifo_underruns),
386 BNXT_TX_STATS_ENTRY(tx_pfc_ena_frames_pri0),
387 BNXT_TX_STATS_ENTRY(tx_pfc_ena_frames_pri1),
388 BNXT_TX_STATS_ENTRY(tx_pfc_ena_frames_pri2),
389 BNXT_TX_STATS_ENTRY(tx_pfc_ena_frames_pri3),
390 BNXT_TX_STATS_ENTRY(tx_pfc_ena_frames_pri4),
391 BNXT_TX_STATS_ENTRY(tx_pfc_ena_frames_pri5),
392 BNXT_TX_STATS_ENTRY(tx_pfc_ena_frames_pri6),
393 BNXT_TX_STATS_ENTRY(tx_pfc_ena_frames_pri7),
394 BNXT_TX_STATS_ENTRY(tx_eee_lpi_events),
395 BNXT_TX_STATS_ENTRY(tx_eee_lpi_duration),
396 BNXT_TX_STATS_ENTRY(tx_total_collisions),
397 BNXT_TX_STATS_ENTRY(tx_bytes),
398 BNXT_TX_STATS_ENTRY(tx_xthol_frames),
399 BNXT_TX_STATS_ENTRY(tx_stat_discard),
400 BNXT_TX_STATS_ENTRY(tx_stat_error),
403 static const struct {
405 char string[ETH_GSTRING_LEN];
406 } bnxt_port_stats_ext_arr[] = {
407 BNXT_RX_STATS_EXT_ENTRY(link_down_events),
408 BNXT_RX_STATS_EXT_ENTRY(continuous_pause_events),
409 BNXT_RX_STATS_EXT_ENTRY(resume_pause_events),
410 BNXT_RX_STATS_EXT_ENTRY(continuous_roce_pause_events),
411 BNXT_RX_STATS_EXT_ENTRY(resume_roce_pause_events),
412 BNXT_RX_STATS_EXT_COS_ENTRIES,
413 BNXT_RX_STATS_EXT_PFC_ENTRIES,
414 BNXT_RX_STATS_EXT_ENTRY(rx_bits),
415 BNXT_RX_STATS_EXT_ENTRY(rx_buffer_passed_threshold),
416 BNXT_RX_STATS_EXT_ENTRY(rx_pcs_symbol_err),
417 BNXT_RX_STATS_EXT_ENTRY(rx_corrected_bits),
418 BNXT_RX_STATS_EXT_DISCARD_COS_ENTRIES,
421 static const struct {
423 char string[ETH_GSTRING_LEN];
424 } bnxt_tx_port_stats_ext_arr[] = {
425 BNXT_TX_STATS_EXT_COS_ENTRIES,
426 BNXT_TX_STATS_EXT_PFC_ENTRIES,
429 static const struct {
431 char string[ETH_GSTRING_LEN];
432 } bnxt_rx_bytes_pri_arr[] = {
433 BNXT_RX_STATS_PRI_ENTRIES(rx_bytes),
436 static const struct {
438 char string[ETH_GSTRING_LEN];
439 } bnxt_rx_pkts_pri_arr[] = {
440 BNXT_RX_STATS_PRI_ENTRIES(rx_packets),
443 static const struct {
445 char string[ETH_GSTRING_LEN];
446 } bnxt_tx_bytes_pri_arr[] = {
447 BNXT_TX_STATS_PRI_ENTRIES(tx_bytes),
450 static const struct {
452 char string[ETH_GSTRING_LEN];
453 } bnxt_tx_pkts_pri_arr[] = {
454 BNXT_TX_STATS_PRI_ENTRIES(tx_packets),
457 #define BNXT_NUM_SW_FUNC_STATS ARRAY_SIZE(bnxt_sw_func_stats)
458 #define BNXT_NUM_PORT_STATS ARRAY_SIZE(bnxt_port_stats_arr)
459 #define BNXT_NUM_STATS_PRI \
460 (ARRAY_SIZE(bnxt_rx_bytes_pri_arr) + \
461 ARRAY_SIZE(bnxt_rx_pkts_pri_arr) + \
462 ARRAY_SIZE(bnxt_tx_bytes_pri_arr) + \
463 ARRAY_SIZE(bnxt_tx_pkts_pri_arr))
465 static int bnxt_get_num_tpa_ring_stats(struct bnxt *bp)
467 if (BNXT_SUPPORTS_TPA(bp)) {
468 if (bp->max_tpa_v2) {
469 if (BNXT_CHIP_P5_THOR(bp))
470 return BNXT_NUM_TPA_RING_STATS_P5;
471 return BNXT_NUM_TPA_RING_STATS_P5_SR2;
473 return BNXT_NUM_TPA_RING_STATS;
478 static int bnxt_get_num_ring_stats(struct bnxt *bp)
482 rx = NUM_RING_RX_HW_STATS + NUM_RING_RX_SW_STATS +
483 bnxt_get_num_tpa_ring_stats(bp);
484 tx = NUM_RING_TX_HW_STATS;
485 cmn = NUM_RING_CMN_SW_STATS;
486 return rx * bp->rx_nr_rings + tx * bp->tx_nr_rings +
487 cmn * bp->cp_nr_rings;
490 static int bnxt_get_num_stats(struct bnxt *bp)
492 int num_stats = bnxt_get_num_ring_stats(bp);
494 num_stats += BNXT_NUM_SW_FUNC_STATS;
496 if (bp->flags & BNXT_FLAG_PORT_STATS)
497 num_stats += BNXT_NUM_PORT_STATS;
499 if (bp->flags & BNXT_FLAG_PORT_STATS_EXT) {
500 num_stats += bp->fw_rx_stats_ext_size +
501 bp->fw_tx_stats_ext_size;
502 if (bp->pri2cos_valid)
503 num_stats += BNXT_NUM_STATS_PRI;
509 static int bnxt_get_sset_count(struct net_device *dev, int sset)
511 struct bnxt *bp = netdev_priv(dev);
515 return bnxt_get_num_stats(bp);
519 return bp->num_tests;
525 static bool is_rx_ring(struct bnxt *bp, int ring_num)
527 return ring_num < bp->rx_nr_rings;
530 static bool is_tx_ring(struct bnxt *bp, int ring_num)
534 if (!(bp->flags & BNXT_FLAG_SHARED_RINGS))
535 tx_base = bp->rx_nr_rings;
537 if (ring_num >= tx_base && ring_num < (tx_base + bp->tx_nr_rings))
542 static void bnxt_get_ethtool_stats(struct net_device *dev,
543 struct ethtool_stats *stats, u64 *buf)
546 struct bnxt *bp = netdev_priv(dev);
550 j += bnxt_get_num_ring_stats(bp) + BNXT_NUM_SW_FUNC_STATS;
551 goto skip_ring_stats;
554 for (i = 0; i < BNXT_NUM_SW_FUNC_STATS; i++)
555 bnxt_sw_func_stats[i].counter = 0;
557 tpa_stats = bnxt_get_num_tpa_ring_stats(bp);
558 for (i = 0; i < bp->cp_nr_rings; i++) {
559 struct bnxt_napi *bnapi = bp->bnapi[i];
560 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
561 u64 *sw_stats = cpr->stats.sw_stats;
565 if (is_rx_ring(bp, i)) {
566 for (k = 0; k < NUM_RING_RX_HW_STATS; j++, k++)
567 buf[j] = sw_stats[k];
569 if (is_tx_ring(bp, i)) {
570 k = NUM_RING_RX_HW_STATS;
571 for (; k < NUM_RING_RX_HW_STATS + NUM_RING_TX_HW_STATS;
573 buf[j] = sw_stats[k];
575 if (!tpa_stats || !is_rx_ring(bp, i))
576 goto skip_tpa_ring_stats;
578 k = NUM_RING_RX_HW_STATS + NUM_RING_TX_HW_STATS;
579 for (; k < NUM_RING_RX_HW_STATS + NUM_RING_TX_HW_STATS +
581 buf[j] = sw_stats[k];
584 sw = (u64 *)&cpr->sw_stats.rx;
585 if (is_rx_ring(bp, i)) {
586 for (k = 0; k < NUM_RING_RX_SW_STATS; j++, k++)
590 sw = (u64 *)&cpr->sw_stats.cmn;
591 for (k = 0; k < NUM_RING_CMN_SW_STATS; j++, k++)
594 bnxt_sw_func_stats[RX_TOTAL_DISCARDS].counter +=
595 BNXT_GET_RING_STATS64(sw_stats, rx_discard_pkts);
596 bnxt_sw_func_stats[TX_TOTAL_DISCARDS].counter +=
597 BNXT_GET_RING_STATS64(sw_stats, tx_discard_pkts);
600 for (i = 0; i < BNXT_NUM_SW_FUNC_STATS; i++, j++)
601 buf[j] = bnxt_sw_func_stats[i].counter;
604 if (bp->flags & BNXT_FLAG_PORT_STATS) {
605 u64 *port_stats = bp->port_stats.sw_stats;
607 for (i = 0; i < BNXT_NUM_PORT_STATS; i++, j++)
608 buf[j] = *(port_stats + bnxt_port_stats_arr[i].offset);
610 if (bp->flags & BNXT_FLAG_PORT_STATS_EXT) {
611 u64 *rx_port_stats_ext = bp->rx_port_stats_ext.sw_stats;
612 u64 *tx_port_stats_ext = bp->tx_port_stats_ext.sw_stats;
614 for (i = 0; i < bp->fw_rx_stats_ext_size; i++, j++) {
615 buf[j] = *(rx_port_stats_ext +
616 bnxt_port_stats_ext_arr[i].offset);
618 for (i = 0; i < bp->fw_tx_stats_ext_size; i++, j++) {
619 buf[j] = *(tx_port_stats_ext +
620 bnxt_tx_port_stats_ext_arr[i].offset);
622 if (bp->pri2cos_valid) {
623 for (i = 0; i < 8; i++, j++) {
624 long n = bnxt_rx_bytes_pri_arr[i].base_off +
627 buf[j] = *(rx_port_stats_ext + n);
629 for (i = 0; i < 8; i++, j++) {
630 long n = bnxt_rx_pkts_pri_arr[i].base_off +
633 buf[j] = *(rx_port_stats_ext + n);
635 for (i = 0; i < 8; i++, j++) {
636 long n = bnxt_tx_bytes_pri_arr[i].base_off +
639 buf[j] = *(tx_port_stats_ext + n);
641 for (i = 0; i < 8; i++, j++) {
642 long n = bnxt_tx_pkts_pri_arr[i].base_off +
645 buf[j] = *(tx_port_stats_ext + n);
651 static void bnxt_get_strings(struct net_device *dev, u32 stringset, u8 *buf)
653 struct bnxt *bp = netdev_priv(dev);
654 static const char * const *str;
659 for (i = 0; i < bp->cp_nr_rings; i++) {
660 if (is_rx_ring(bp, i)) {
661 num_str = NUM_RING_RX_HW_STATS;
662 for (j = 0; j < num_str; j++) {
663 sprintf(buf, "[%d]: %s", i,
664 bnxt_ring_rx_stats_str[j]);
665 buf += ETH_GSTRING_LEN;
668 if (is_tx_ring(bp, i)) {
669 num_str = NUM_RING_TX_HW_STATS;
670 for (j = 0; j < num_str; j++) {
671 sprintf(buf, "[%d]: %s", i,
672 bnxt_ring_tx_stats_str[j]);
673 buf += ETH_GSTRING_LEN;
676 num_str = bnxt_get_num_tpa_ring_stats(bp);
677 if (!num_str || !is_rx_ring(bp, i))
681 str = bnxt_ring_tpa2_stats_str;
683 str = bnxt_ring_tpa_stats_str;
685 for (j = 0; j < num_str; j++) {
686 sprintf(buf, "[%d]: %s", i, str[j]);
687 buf += ETH_GSTRING_LEN;
690 if (is_rx_ring(bp, i)) {
691 num_str = NUM_RING_RX_SW_STATS;
692 for (j = 0; j < num_str; j++) {
693 sprintf(buf, "[%d]: %s", i,
694 bnxt_rx_sw_stats_str[j]);
695 buf += ETH_GSTRING_LEN;
698 num_str = NUM_RING_CMN_SW_STATS;
699 for (j = 0; j < num_str; j++) {
700 sprintf(buf, "[%d]: %s", i,
701 bnxt_cmn_sw_stats_str[j]);
702 buf += ETH_GSTRING_LEN;
705 for (i = 0; i < BNXT_NUM_SW_FUNC_STATS; i++) {
706 strcpy(buf, bnxt_sw_func_stats[i].string);
707 buf += ETH_GSTRING_LEN;
710 if (bp->flags & BNXT_FLAG_PORT_STATS) {
711 for (i = 0; i < BNXT_NUM_PORT_STATS; i++) {
712 strcpy(buf, bnxt_port_stats_arr[i].string);
713 buf += ETH_GSTRING_LEN;
716 if (bp->flags & BNXT_FLAG_PORT_STATS_EXT) {
717 for (i = 0; i < bp->fw_rx_stats_ext_size; i++) {
718 strcpy(buf, bnxt_port_stats_ext_arr[i].string);
719 buf += ETH_GSTRING_LEN;
721 for (i = 0; i < bp->fw_tx_stats_ext_size; i++) {
723 bnxt_tx_port_stats_ext_arr[i].string);
724 buf += ETH_GSTRING_LEN;
726 if (bp->pri2cos_valid) {
727 for (i = 0; i < 8; i++) {
729 bnxt_rx_bytes_pri_arr[i].string);
730 buf += ETH_GSTRING_LEN;
732 for (i = 0; i < 8; i++) {
734 bnxt_rx_pkts_pri_arr[i].string);
735 buf += ETH_GSTRING_LEN;
737 for (i = 0; i < 8; i++) {
739 bnxt_tx_bytes_pri_arr[i].string);
740 buf += ETH_GSTRING_LEN;
742 for (i = 0; i < 8; i++) {
744 bnxt_tx_pkts_pri_arr[i].string);
745 buf += ETH_GSTRING_LEN;
752 memcpy(buf, bp->test_info->string,
753 bp->num_tests * ETH_GSTRING_LEN);
756 netdev_err(bp->dev, "bnxt_get_strings invalid request %x\n",
762 static void bnxt_get_ringparam(struct net_device *dev,
763 struct ethtool_ringparam *ering)
765 struct bnxt *bp = netdev_priv(dev);
767 ering->rx_max_pending = BNXT_MAX_RX_DESC_CNT;
768 ering->rx_jumbo_max_pending = BNXT_MAX_RX_JUM_DESC_CNT;
769 ering->tx_max_pending = BNXT_MAX_TX_DESC_CNT;
771 ering->rx_pending = bp->rx_ring_size;
772 ering->rx_jumbo_pending = bp->rx_agg_ring_size;
773 ering->tx_pending = bp->tx_ring_size;
776 static int bnxt_set_ringparam(struct net_device *dev,
777 struct ethtool_ringparam *ering)
779 struct bnxt *bp = netdev_priv(dev);
781 if ((ering->rx_pending > BNXT_MAX_RX_DESC_CNT) ||
782 (ering->tx_pending > BNXT_MAX_TX_DESC_CNT) ||
783 (ering->tx_pending <= MAX_SKB_FRAGS))
786 if (netif_running(dev))
787 bnxt_close_nic(bp, false, false);
789 bp->rx_ring_size = ering->rx_pending;
790 bp->tx_ring_size = ering->tx_pending;
791 bnxt_set_ring_params(bp);
793 if (netif_running(dev))
794 return bnxt_open_nic(bp, false, false);
799 static void bnxt_get_channels(struct net_device *dev,
800 struct ethtool_channels *channel)
802 struct bnxt *bp = netdev_priv(dev);
803 struct bnxt_hw_resc *hw_resc = &bp->hw_resc;
804 int max_rx_rings, max_tx_rings, tcs;
805 int max_tx_sch_inputs, tx_grps;
807 /* Get the most up-to-date max_tx_sch_inputs. */
808 if (netif_running(dev) && BNXT_NEW_RM(bp))
809 bnxt_hwrm_func_resc_qcaps(bp, false);
810 max_tx_sch_inputs = hw_resc->max_tx_sch_inputs;
812 bnxt_get_max_rings(bp, &max_rx_rings, &max_tx_rings, true);
813 if (max_tx_sch_inputs)
814 max_tx_rings = min_t(int, max_tx_rings, max_tx_sch_inputs);
816 tcs = netdev_get_num_tc(dev);
817 tx_grps = max(tcs, 1);
818 if (bp->tx_nr_rings_xdp)
820 max_tx_rings /= tx_grps;
821 channel->max_combined = min_t(int, max_rx_rings, max_tx_rings);
823 if (bnxt_get_max_rings(bp, &max_rx_rings, &max_tx_rings, false)) {
827 if (max_tx_sch_inputs)
828 max_tx_rings = min_t(int, max_tx_rings, max_tx_sch_inputs);
833 channel->max_rx = max_rx_rings;
834 channel->max_tx = max_tx_rings;
835 channel->max_other = 0;
836 if (bp->flags & BNXT_FLAG_SHARED_RINGS) {
837 channel->combined_count = bp->rx_nr_rings;
838 if (BNXT_CHIP_TYPE_NITRO_A0(bp))
839 channel->combined_count--;
841 if (!BNXT_CHIP_TYPE_NITRO_A0(bp)) {
842 channel->rx_count = bp->rx_nr_rings;
843 channel->tx_count = bp->tx_nr_rings_per_tc;
848 static int bnxt_set_channels(struct net_device *dev,
849 struct ethtool_channels *channel)
851 struct bnxt *bp = netdev_priv(dev);
852 int req_tx_rings, req_rx_rings, tcs;
857 if (channel->other_count)
860 if (!channel->combined_count &&
861 (!channel->rx_count || !channel->tx_count))
864 if (channel->combined_count &&
865 (channel->rx_count || channel->tx_count))
868 if (BNXT_CHIP_TYPE_NITRO_A0(bp) && (channel->rx_count ||
872 if (channel->combined_count)
875 tcs = netdev_get_num_tc(dev);
877 req_tx_rings = sh ? channel->combined_count : channel->tx_count;
878 req_rx_rings = sh ? channel->combined_count : channel->rx_count;
879 if (bp->tx_nr_rings_xdp) {
881 netdev_err(dev, "Only combined mode supported when XDP is enabled.\n");
884 tx_xdp = req_rx_rings;
886 rc = bnxt_check_rings(bp, req_tx_rings, req_rx_rings, sh, tcs, tx_xdp);
888 netdev_warn(dev, "Unable to allocate the requested rings\n");
892 if (bnxt_get_nr_rss_ctxs(bp, req_rx_rings) !=
893 bnxt_get_nr_rss_ctxs(bp, bp->rx_nr_rings) &&
894 (dev->priv_flags & IFF_RXFH_CONFIGURED)) {
895 netdev_warn(dev, "RSS table size change required, RSS table entries must be default to proceed\n");
899 if (netif_running(dev)) {
901 /* TODO CHIMP_FW: Send message to all VF's
905 rc = bnxt_close_nic(bp, true, false);
907 netdev_err(bp->dev, "Set channel failure rc :%x\n",
914 bp->flags |= BNXT_FLAG_SHARED_RINGS;
915 bp->rx_nr_rings = channel->combined_count;
916 bp->tx_nr_rings_per_tc = channel->combined_count;
918 bp->flags &= ~BNXT_FLAG_SHARED_RINGS;
919 bp->rx_nr_rings = channel->rx_count;
920 bp->tx_nr_rings_per_tc = channel->tx_count;
922 bp->tx_nr_rings_xdp = tx_xdp;
923 bp->tx_nr_rings = bp->tx_nr_rings_per_tc + tx_xdp;
925 bp->tx_nr_rings = bp->tx_nr_rings_per_tc * tcs + tx_xdp;
927 bp->cp_nr_rings = sh ? max_t(int, bp->tx_nr_rings, bp->rx_nr_rings) :
928 bp->tx_nr_rings + bp->rx_nr_rings;
930 /* After changing number of rx channels, update NTUPLE feature. */
931 netdev_update_features(dev);
932 if (netif_running(dev)) {
933 rc = bnxt_open_nic(bp, true, false);
934 if ((!rc) && BNXT_PF(bp)) {
935 /* TODO CHIMP_FW: Send message to all VF's
940 rc = bnxt_reserve_rings(bp, true);
946 #ifdef CONFIG_RFS_ACCEL
947 static int bnxt_grxclsrlall(struct bnxt *bp, struct ethtool_rxnfc *cmd,
952 cmd->data = bp->ntp_fltr_count;
953 for (i = 0; i < BNXT_NTP_FLTR_HASH_SIZE; i++) {
954 struct hlist_head *head;
955 struct bnxt_ntuple_filter *fltr;
957 head = &bp->ntp_fltr_hash_tbl[i];
959 hlist_for_each_entry_rcu(fltr, head, hash) {
960 if (j == cmd->rule_cnt)
962 rule_locs[j++] = fltr->sw_id;
965 if (j == cmd->rule_cnt)
972 static int bnxt_grxclsrule(struct bnxt *bp, struct ethtool_rxnfc *cmd)
974 struct ethtool_rx_flow_spec *fs =
975 (struct ethtool_rx_flow_spec *)&cmd->fs;
976 struct bnxt_ntuple_filter *fltr;
977 struct flow_keys *fkeys;
980 if (fs->location >= BNXT_NTP_FLTR_MAX_FLTR)
983 for (i = 0; i < BNXT_NTP_FLTR_HASH_SIZE; i++) {
984 struct hlist_head *head;
986 head = &bp->ntp_fltr_hash_tbl[i];
988 hlist_for_each_entry_rcu(fltr, head, hash) {
989 if (fltr->sw_id == fs->location)
997 fkeys = &fltr->fkeys;
998 if (fkeys->basic.n_proto == htons(ETH_P_IP)) {
999 if (fkeys->basic.ip_proto == IPPROTO_TCP)
1000 fs->flow_type = TCP_V4_FLOW;
1001 else if (fkeys->basic.ip_proto == IPPROTO_UDP)
1002 fs->flow_type = UDP_V4_FLOW;
1006 fs->h_u.tcp_ip4_spec.ip4src = fkeys->addrs.v4addrs.src;
1007 fs->m_u.tcp_ip4_spec.ip4src = cpu_to_be32(~0);
1009 fs->h_u.tcp_ip4_spec.ip4dst = fkeys->addrs.v4addrs.dst;
1010 fs->m_u.tcp_ip4_spec.ip4dst = cpu_to_be32(~0);
1012 fs->h_u.tcp_ip4_spec.psrc = fkeys->ports.src;
1013 fs->m_u.tcp_ip4_spec.psrc = cpu_to_be16(~0);
1015 fs->h_u.tcp_ip4_spec.pdst = fkeys->ports.dst;
1016 fs->m_u.tcp_ip4_spec.pdst = cpu_to_be16(~0);
1020 if (fkeys->basic.ip_proto == IPPROTO_TCP)
1021 fs->flow_type = TCP_V6_FLOW;
1022 else if (fkeys->basic.ip_proto == IPPROTO_UDP)
1023 fs->flow_type = UDP_V6_FLOW;
1027 *(struct in6_addr *)&fs->h_u.tcp_ip6_spec.ip6src[0] =
1028 fkeys->addrs.v6addrs.src;
1029 *(struct in6_addr *)&fs->h_u.tcp_ip6_spec.ip6dst[0] =
1030 fkeys->addrs.v6addrs.dst;
1031 for (i = 0; i < 4; i++) {
1032 fs->m_u.tcp_ip6_spec.ip6src[i] = cpu_to_be32(~0);
1033 fs->m_u.tcp_ip6_spec.ip6dst[i] = cpu_to_be32(~0);
1035 fs->h_u.tcp_ip6_spec.psrc = fkeys->ports.src;
1036 fs->m_u.tcp_ip6_spec.psrc = cpu_to_be16(~0);
1038 fs->h_u.tcp_ip6_spec.pdst = fkeys->ports.dst;
1039 fs->m_u.tcp_ip6_spec.pdst = cpu_to_be16(~0);
1042 fs->ring_cookie = fltr->rxq;
1052 static u64 get_ethtool_ipv4_rss(struct bnxt *bp)
1054 if (bp->rss_hash_cfg & VNIC_RSS_CFG_REQ_HASH_TYPE_IPV4)
1055 return RXH_IP_SRC | RXH_IP_DST;
1059 static u64 get_ethtool_ipv6_rss(struct bnxt *bp)
1061 if (bp->rss_hash_cfg & VNIC_RSS_CFG_REQ_HASH_TYPE_IPV6)
1062 return RXH_IP_SRC | RXH_IP_DST;
1066 static int bnxt_grxfh(struct bnxt *bp, struct ethtool_rxnfc *cmd)
1069 switch (cmd->flow_type) {
1071 if (bp->rss_hash_cfg & VNIC_RSS_CFG_REQ_HASH_TYPE_TCP_IPV4)
1072 cmd->data |= RXH_IP_SRC | RXH_IP_DST |
1073 RXH_L4_B_0_1 | RXH_L4_B_2_3;
1074 cmd->data |= get_ethtool_ipv4_rss(bp);
1077 if (bp->rss_hash_cfg & VNIC_RSS_CFG_REQ_HASH_TYPE_UDP_IPV4)
1078 cmd->data |= RXH_IP_SRC | RXH_IP_DST |
1079 RXH_L4_B_0_1 | RXH_L4_B_2_3;
1082 case AH_ESP_V4_FLOW:
1086 cmd->data |= get_ethtool_ipv4_rss(bp);
1090 if (bp->rss_hash_cfg & VNIC_RSS_CFG_REQ_HASH_TYPE_TCP_IPV6)
1091 cmd->data |= RXH_IP_SRC | RXH_IP_DST |
1092 RXH_L4_B_0_1 | RXH_L4_B_2_3;
1093 cmd->data |= get_ethtool_ipv6_rss(bp);
1096 if (bp->rss_hash_cfg & VNIC_RSS_CFG_REQ_HASH_TYPE_UDP_IPV6)
1097 cmd->data |= RXH_IP_SRC | RXH_IP_DST |
1098 RXH_L4_B_0_1 | RXH_L4_B_2_3;
1101 case AH_ESP_V6_FLOW:
1105 cmd->data |= get_ethtool_ipv6_rss(bp);
1111 #define RXH_4TUPLE (RXH_IP_SRC | RXH_IP_DST | RXH_L4_B_0_1 | RXH_L4_B_2_3)
1112 #define RXH_2TUPLE (RXH_IP_SRC | RXH_IP_DST)
1114 static int bnxt_srxfh(struct bnxt *bp, struct ethtool_rxnfc *cmd)
1116 u32 rss_hash_cfg = bp->rss_hash_cfg;
1119 if (cmd->data == RXH_4TUPLE)
1121 else if (cmd->data == RXH_2TUPLE)
1123 else if (!cmd->data)
1128 if (cmd->flow_type == TCP_V4_FLOW) {
1129 rss_hash_cfg &= ~VNIC_RSS_CFG_REQ_HASH_TYPE_TCP_IPV4;
1131 rss_hash_cfg |= VNIC_RSS_CFG_REQ_HASH_TYPE_TCP_IPV4;
1132 } else if (cmd->flow_type == UDP_V4_FLOW) {
1133 if (tuple == 4 && !(bp->flags & BNXT_FLAG_UDP_RSS_CAP))
1135 rss_hash_cfg &= ~VNIC_RSS_CFG_REQ_HASH_TYPE_UDP_IPV4;
1137 rss_hash_cfg |= VNIC_RSS_CFG_REQ_HASH_TYPE_UDP_IPV4;
1138 } else if (cmd->flow_type == TCP_V6_FLOW) {
1139 rss_hash_cfg &= ~VNIC_RSS_CFG_REQ_HASH_TYPE_TCP_IPV6;
1141 rss_hash_cfg |= VNIC_RSS_CFG_REQ_HASH_TYPE_TCP_IPV6;
1142 } else if (cmd->flow_type == UDP_V6_FLOW) {
1143 if (tuple == 4 && !(bp->flags & BNXT_FLAG_UDP_RSS_CAP))
1145 rss_hash_cfg &= ~VNIC_RSS_CFG_REQ_HASH_TYPE_UDP_IPV6;
1147 rss_hash_cfg |= VNIC_RSS_CFG_REQ_HASH_TYPE_UDP_IPV6;
1148 } else if (tuple == 4) {
1152 switch (cmd->flow_type) {
1156 case AH_ESP_V4_FLOW:
1161 rss_hash_cfg |= VNIC_RSS_CFG_REQ_HASH_TYPE_IPV4;
1163 rss_hash_cfg &= ~VNIC_RSS_CFG_REQ_HASH_TYPE_IPV4;
1169 case AH_ESP_V6_FLOW:
1174 rss_hash_cfg |= VNIC_RSS_CFG_REQ_HASH_TYPE_IPV6;
1176 rss_hash_cfg &= ~VNIC_RSS_CFG_REQ_HASH_TYPE_IPV6;
1180 if (bp->rss_hash_cfg == rss_hash_cfg)
1183 bp->rss_hash_cfg = rss_hash_cfg;
1184 if (netif_running(bp->dev)) {
1185 bnxt_close_nic(bp, false, false);
1186 rc = bnxt_open_nic(bp, false, false);
1191 static int bnxt_get_rxnfc(struct net_device *dev, struct ethtool_rxnfc *cmd,
1194 struct bnxt *bp = netdev_priv(dev);
1198 #ifdef CONFIG_RFS_ACCEL
1199 case ETHTOOL_GRXRINGS:
1200 cmd->data = bp->rx_nr_rings;
1203 case ETHTOOL_GRXCLSRLCNT:
1204 cmd->rule_cnt = bp->ntp_fltr_count;
1205 cmd->data = BNXT_NTP_FLTR_MAX_FLTR;
1208 case ETHTOOL_GRXCLSRLALL:
1209 rc = bnxt_grxclsrlall(bp, cmd, (u32 *)rule_locs);
1212 case ETHTOOL_GRXCLSRULE:
1213 rc = bnxt_grxclsrule(bp, cmd);
1218 rc = bnxt_grxfh(bp, cmd);
1229 static int bnxt_set_rxnfc(struct net_device *dev, struct ethtool_rxnfc *cmd)
1231 struct bnxt *bp = netdev_priv(dev);
1236 rc = bnxt_srxfh(bp, cmd);
1246 u32 bnxt_get_rxfh_indir_size(struct net_device *dev)
1248 struct bnxt *bp = netdev_priv(dev);
1250 if (bp->flags & BNXT_FLAG_CHIP_P5)
1251 return ALIGN(bp->rx_nr_rings, BNXT_RSS_TABLE_ENTRIES_P5);
1252 return HW_HASH_INDEX_SIZE;
1255 static u32 bnxt_get_rxfh_key_size(struct net_device *dev)
1257 return HW_HASH_KEY_SIZE;
1260 static int bnxt_get_rxfh(struct net_device *dev, u32 *indir, u8 *key,
1263 struct bnxt *bp = netdev_priv(dev);
1264 struct bnxt_vnic_info *vnic;
1268 *hfunc = ETH_RSS_HASH_TOP;
1273 vnic = &bp->vnic_info[0];
1274 if (indir && bp->rss_indir_tbl) {
1275 tbl_size = bnxt_get_rxfh_indir_size(dev);
1276 for (i = 0; i < tbl_size; i++)
1277 indir[i] = bp->rss_indir_tbl[i];
1280 if (key && vnic->rss_hash_key)
1281 memcpy(key, vnic->rss_hash_key, HW_HASH_KEY_SIZE);
1286 static int bnxt_set_rxfh(struct net_device *dev, const u32 *indir,
1287 const u8 *key, const u8 hfunc)
1289 struct bnxt *bp = netdev_priv(dev);
1292 if (hfunc && hfunc != ETH_RSS_HASH_TOP)
1299 u32 i, pad, tbl_size = bnxt_get_rxfh_indir_size(dev);
1301 for (i = 0; i < tbl_size; i++)
1302 bp->rss_indir_tbl[i] = indir[i];
1303 pad = bp->rss_indir_tbl_entries - tbl_size;
1305 memset(&bp->rss_indir_tbl[i], 0, pad * sizeof(u16));
1308 if (netif_running(bp->dev)) {
1309 bnxt_close_nic(bp, false, false);
1310 rc = bnxt_open_nic(bp, false, false);
1315 static void bnxt_get_drvinfo(struct net_device *dev,
1316 struct ethtool_drvinfo *info)
1318 struct bnxt *bp = netdev_priv(dev);
1320 strlcpy(info->driver, DRV_MODULE_NAME, sizeof(info->driver));
1321 strlcpy(info->fw_version, bp->fw_ver_str, sizeof(info->fw_version));
1322 strlcpy(info->bus_info, pci_name(bp->pdev), sizeof(info->bus_info));
1323 info->n_stats = bnxt_get_num_stats(bp);
1324 info->testinfo_len = bp->num_tests;
1325 /* TODO CHIMP_FW: eeprom dump details */
1326 info->eedump_len = 0;
1327 /* TODO CHIMP FW: reg dump details */
1328 info->regdump_len = 0;
1331 static int bnxt_get_regs_len(struct net_device *dev)
1333 struct bnxt *bp = netdev_priv(dev);
1339 reg_len = BNXT_PXP_REG_LEN;
1341 if (bp->fw_cap & BNXT_FW_CAP_PCIE_STATS_SUPPORTED)
1342 reg_len += sizeof(struct pcie_ctx_hw_stats);
1347 static void bnxt_get_regs(struct net_device *dev, struct ethtool_regs *regs,
1350 struct pcie_ctx_hw_stats *hw_pcie_stats;
1351 struct hwrm_pcie_qstats_input req = {0};
1352 struct bnxt *bp = netdev_priv(dev);
1353 dma_addr_t hw_pcie_stats_addr;
1357 bnxt_dbg_hwrm_rd_reg(bp, 0, BNXT_PXP_REG_LEN / 4, _p);
1359 if (!(bp->fw_cap & BNXT_FW_CAP_PCIE_STATS_SUPPORTED))
1362 hw_pcie_stats = dma_alloc_coherent(&bp->pdev->dev,
1363 sizeof(*hw_pcie_stats),
1364 &hw_pcie_stats_addr, GFP_KERNEL);
1369 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_PCIE_QSTATS, -1, -1);
1370 req.pcie_stat_size = cpu_to_le16(sizeof(*hw_pcie_stats));
1371 req.pcie_stat_host_addr = cpu_to_le64(hw_pcie_stats_addr);
1372 mutex_lock(&bp->hwrm_cmd_lock);
1373 rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
1375 __le64 *src = (__le64 *)hw_pcie_stats;
1376 u64 *dst = (u64 *)(_p + BNXT_PXP_REG_LEN);
1379 for (i = 0; i < sizeof(*hw_pcie_stats) / sizeof(__le64); i++)
1380 dst[i] = le64_to_cpu(src[i]);
1382 mutex_unlock(&bp->hwrm_cmd_lock);
1383 dma_free_coherent(&bp->pdev->dev, sizeof(*hw_pcie_stats), hw_pcie_stats,
1384 hw_pcie_stats_addr);
1387 static void bnxt_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
1389 struct bnxt *bp = netdev_priv(dev);
1393 memset(&wol->sopass, 0, sizeof(wol->sopass));
1394 if (bp->flags & BNXT_FLAG_WOL_CAP) {
1395 wol->supported = WAKE_MAGIC;
1397 wol->wolopts = WAKE_MAGIC;
1401 static int bnxt_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
1403 struct bnxt *bp = netdev_priv(dev);
1405 if (wol->wolopts & ~WAKE_MAGIC)
1408 if (wol->wolopts & WAKE_MAGIC) {
1409 if (!(bp->flags & BNXT_FLAG_WOL_CAP))
1412 if (bnxt_hwrm_alloc_wol_fltr(bp))
1418 if (bnxt_hwrm_free_wol_fltr(bp))
1426 u32 _bnxt_fw_to_ethtool_adv_spds(u16 fw_speeds, u8 fw_pause)
1430 /* TODO: support 25GB, 40GB, 50GB with different cable type */
1431 /* set the advertised speeds */
1432 if (fw_speeds & BNXT_LINK_SPEED_MSK_100MB)
1433 speed_mask |= ADVERTISED_100baseT_Full;
1434 if (fw_speeds & BNXT_LINK_SPEED_MSK_1GB)
1435 speed_mask |= ADVERTISED_1000baseT_Full;
1436 if (fw_speeds & BNXT_LINK_SPEED_MSK_2_5GB)
1437 speed_mask |= ADVERTISED_2500baseX_Full;
1438 if (fw_speeds & BNXT_LINK_SPEED_MSK_10GB)
1439 speed_mask |= ADVERTISED_10000baseT_Full;
1440 if (fw_speeds & BNXT_LINK_SPEED_MSK_40GB)
1441 speed_mask |= ADVERTISED_40000baseCR4_Full;
1443 if ((fw_pause & BNXT_LINK_PAUSE_BOTH) == BNXT_LINK_PAUSE_BOTH)
1444 speed_mask |= ADVERTISED_Pause;
1445 else if (fw_pause & BNXT_LINK_PAUSE_TX)
1446 speed_mask |= ADVERTISED_Asym_Pause;
1447 else if (fw_pause & BNXT_LINK_PAUSE_RX)
1448 speed_mask |= ADVERTISED_Pause | ADVERTISED_Asym_Pause;
1453 #define BNXT_FW_TO_ETHTOOL_SPDS(fw_speeds, fw_pause, lk_ksettings, name)\
1455 if ((fw_speeds) & BNXT_LINK_SPEED_MSK_100MB) \
1456 ethtool_link_ksettings_add_link_mode(lk_ksettings, name,\
1458 if ((fw_speeds) & BNXT_LINK_SPEED_MSK_1GB) \
1459 ethtool_link_ksettings_add_link_mode(lk_ksettings, name,\
1461 if ((fw_speeds) & BNXT_LINK_SPEED_MSK_10GB) \
1462 ethtool_link_ksettings_add_link_mode(lk_ksettings, name,\
1464 if ((fw_speeds) & BNXT_LINK_SPEED_MSK_25GB) \
1465 ethtool_link_ksettings_add_link_mode(lk_ksettings, name,\
1466 25000baseCR_Full); \
1467 if ((fw_speeds) & BNXT_LINK_SPEED_MSK_40GB) \
1468 ethtool_link_ksettings_add_link_mode(lk_ksettings, name,\
1469 40000baseCR4_Full);\
1470 if ((fw_speeds) & BNXT_LINK_SPEED_MSK_50GB) \
1471 ethtool_link_ksettings_add_link_mode(lk_ksettings, name,\
1472 50000baseCR2_Full);\
1473 if ((fw_speeds) & BNXT_LINK_SPEED_MSK_100GB) \
1474 ethtool_link_ksettings_add_link_mode(lk_ksettings, name,\
1475 100000baseCR4_Full);\
1476 if ((fw_pause) & BNXT_LINK_PAUSE_RX) { \
1477 ethtool_link_ksettings_add_link_mode(lk_ksettings, name,\
1479 if (!((fw_pause) & BNXT_LINK_PAUSE_TX)) \
1480 ethtool_link_ksettings_add_link_mode( \
1481 lk_ksettings, name, Asym_Pause);\
1482 } else if ((fw_pause) & BNXT_LINK_PAUSE_TX) { \
1483 ethtool_link_ksettings_add_link_mode(lk_ksettings, name,\
1488 #define BNXT_ETHTOOL_TO_FW_SPDS(fw_speeds, lk_ksettings, name) \
1490 if (ethtool_link_ksettings_test_link_mode(lk_ksettings, name, \
1492 ethtool_link_ksettings_test_link_mode(lk_ksettings, name, \
1494 (fw_speeds) |= BNXT_LINK_SPEED_MSK_100MB; \
1495 if (ethtool_link_ksettings_test_link_mode(lk_ksettings, name, \
1496 1000baseT_Full) || \
1497 ethtool_link_ksettings_test_link_mode(lk_ksettings, name, \
1499 (fw_speeds) |= BNXT_LINK_SPEED_MSK_1GB; \
1500 if (ethtool_link_ksettings_test_link_mode(lk_ksettings, name, \
1502 (fw_speeds) |= BNXT_LINK_SPEED_MSK_10GB; \
1503 if (ethtool_link_ksettings_test_link_mode(lk_ksettings, name, \
1504 25000baseCR_Full)) \
1505 (fw_speeds) |= BNXT_LINK_SPEED_MSK_25GB; \
1506 if (ethtool_link_ksettings_test_link_mode(lk_ksettings, name, \
1507 40000baseCR4_Full)) \
1508 (fw_speeds) |= BNXT_LINK_SPEED_MSK_40GB; \
1509 if (ethtool_link_ksettings_test_link_mode(lk_ksettings, name, \
1510 50000baseCR2_Full)) \
1511 (fw_speeds) |= BNXT_LINK_SPEED_MSK_50GB; \
1512 if (ethtool_link_ksettings_test_link_mode(lk_ksettings, name, \
1513 100000baseCR4_Full)) \
1514 (fw_speeds) |= BNXT_LINK_SPEED_MSK_100GB; \
1517 #define BNXT_FW_TO_ETHTOOL_PAM4_SPDS(fw_speeds, lk_ksettings, name) \
1519 if ((fw_speeds) & BNXT_LINK_PAM4_SPEED_MSK_50GB) \
1520 ethtool_link_ksettings_add_link_mode(lk_ksettings, name,\
1521 50000baseCR_Full); \
1522 if ((fw_speeds) & BNXT_LINK_PAM4_SPEED_MSK_100GB) \
1523 ethtool_link_ksettings_add_link_mode(lk_ksettings, name,\
1524 100000baseCR2_Full);\
1525 if ((fw_speeds) & BNXT_LINK_PAM4_SPEED_MSK_200GB) \
1526 ethtool_link_ksettings_add_link_mode(lk_ksettings, name,\
1527 200000baseCR4_Full);\
1530 #define BNXT_ETHTOOL_TO_FW_PAM4_SPDS(fw_speeds, lk_ksettings, name) \
1532 if (ethtool_link_ksettings_test_link_mode(lk_ksettings, name, \
1533 50000baseCR_Full)) \
1534 (fw_speeds) |= BNXT_LINK_PAM4_SPEED_MSK_50GB; \
1535 if (ethtool_link_ksettings_test_link_mode(lk_ksettings, name, \
1536 100000baseCR2_Full)) \
1537 (fw_speeds) |= BNXT_LINK_PAM4_SPEED_MSK_100GB; \
1538 if (ethtool_link_ksettings_test_link_mode(lk_ksettings, name, \
1539 200000baseCR4_Full)) \
1540 (fw_speeds) |= BNXT_LINK_PAM4_SPEED_MSK_200GB; \
1543 static void bnxt_fw_to_ethtool_advertised_fec(struct bnxt_link_info *link_info,
1544 struct ethtool_link_ksettings *lk_ksettings)
1546 u16 fec_cfg = link_info->fec_cfg;
1548 if ((fec_cfg & BNXT_FEC_NONE) || !(fec_cfg & BNXT_FEC_AUTONEG)) {
1549 linkmode_set_bit(ETHTOOL_LINK_MODE_FEC_NONE_BIT,
1550 lk_ksettings->link_modes.advertising);
1553 if (fec_cfg & BNXT_FEC_ENC_BASE_R)
1554 linkmode_set_bit(ETHTOOL_LINK_MODE_FEC_BASER_BIT,
1555 lk_ksettings->link_modes.advertising);
1556 if (fec_cfg & BNXT_FEC_ENC_RS)
1557 linkmode_set_bit(ETHTOOL_LINK_MODE_FEC_RS_BIT,
1558 lk_ksettings->link_modes.advertising);
1559 if (fec_cfg & BNXT_FEC_ENC_LLRS)
1560 linkmode_set_bit(ETHTOOL_LINK_MODE_FEC_LLRS_BIT,
1561 lk_ksettings->link_modes.advertising);
1564 static void bnxt_fw_to_ethtool_advertised_spds(struct bnxt_link_info *link_info,
1565 struct ethtool_link_ksettings *lk_ksettings)
1567 u16 fw_speeds = link_info->advertising;
1570 if (link_info->autoneg & BNXT_AUTONEG_FLOW_CTRL)
1571 fw_pause = link_info->auto_pause_setting;
1573 BNXT_FW_TO_ETHTOOL_SPDS(fw_speeds, fw_pause, lk_ksettings, advertising);
1574 fw_speeds = link_info->advertising_pam4;
1575 BNXT_FW_TO_ETHTOOL_PAM4_SPDS(fw_speeds, lk_ksettings, advertising);
1576 bnxt_fw_to_ethtool_advertised_fec(link_info, lk_ksettings);
1579 static void bnxt_fw_to_ethtool_lp_adv(struct bnxt_link_info *link_info,
1580 struct ethtool_link_ksettings *lk_ksettings)
1582 u16 fw_speeds = link_info->lp_auto_link_speeds;
1585 if (link_info->autoneg & BNXT_AUTONEG_FLOW_CTRL)
1586 fw_pause = link_info->lp_pause;
1588 BNXT_FW_TO_ETHTOOL_SPDS(fw_speeds, fw_pause, lk_ksettings,
1590 fw_speeds = link_info->lp_auto_pam4_link_speeds;
1591 BNXT_FW_TO_ETHTOOL_PAM4_SPDS(fw_speeds, lk_ksettings, lp_advertising);
1594 static void bnxt_fw_to_ethtool_support_fec(struct bnxt_link_info *link_info,
1595 struct ethtool_link_ksettings *lk_ksettings)
1597 u16 fec_cfg = link_info->fec_cfg;
1599 if (fec_cfg & BNXT_FEC_NONE) {
1600 linkmode_set_bit(ETHTOOL_LINK_MODE_FEC_NONE_BIT,
1601 lk_ksettings->link_modes.supported);
1604 if (fec_cfg & BNXT_FEC_ENC_BASE_R_CAP)
1605 linkmode_set_bit(ETHTOOL_LINK_MODE_FEC_BASER_BIT,
1606 lk_ksettings->link_modes.supported);
1607 if (fec_cfg & BNXT_FEC_ENC_RS_CAP)
1608 linkmode_set_bit(ETHTOOL_LINK_MODE_FEC_RS_BIT,
1609 lk_ksettings->link_modes.supported);
1610 if (fec_cfg & BNXT_FEC_ENC_LLRS_CAP)
1611 linkmode_set_bit(ETHTOOL_LINK_MODE_FEC_LLRS_BIT,
1612 lk_ksettings->link_modes.supported);
1615 static void bnxt_fw_to_ethtool_support_spds(struct bnxt_link_info *link_info,
1616 struct ethtool_link_ksettings *lk_ksettings)
1618 u16 fw_speeds = link_info->support_speeds;
1620 BNXT_FW_TO_ETHTOOL_SPDS(fw_speeds, 0, lk_ksettings, supported);
1621 fw_speeds = link_info->support_pam4_speeds;
1622 BNXT_FW_TO_ETHTOOL_PAM4_SPDS(fw_speeds, lk_ksettings, supported);
1624 ethtool_link_ksettings_add_link_mode(lk_ksettings, supported, Pause);
1625 ethtool_link_ksettings_add_link_mode(lk_ksettings, supported,
1628 if (link_info->support_auto_speeds ||
1629 link_info->support_pam4_auto_speeds)
1630 ethtool_link_ksettings_add_link_mode(lk_ksettings, supported,
1632 bnxt_fw_to_ethtool_support_fec(link_info, lk_ksettings);
1635 u32 bnxt_fw_to_ethtool_speed(u16 fw_link_speed)
1637 switch (fw_link_speed) {
1638 case BNXT_LINK_SPEED_100MB:
1640 case BNXT_LINK_SPEED_1GB:
1642 case BNXT_LINK_SPEED_2_5GB:
1644 case BNXT_LINK_SPEED_10GB:
1646 case BNXT_LINK_SPEED_20GB:
1648 case BNXT_LINK_SPEED_25GB:
1650 case BNXT_LINK_SPEED_40GB:
1652 case BNXT_LINK_SPEED_50GB:
1654 case BNXT_LINK_SPEED_100GB:
1655 return SPEED_100000;
1657 return SPEED_UNKNOWN;
1661 static int bnxt_get_link_ksettings(struct net_device *dev,
1662 struct ethtool_link_ksettings *lk_ksettings)
1664 struct bnxt *bp = netdev_priv(dev);
1665 struct bnxt_link_info *link_info = &bp->link_info;
1666 struct ethtool_link_settings *base = &lk_ksettings->base;
1669 ethtool_link_ksettings_zero_link_mode(lk_ksettings, supported);
1670 mutex_lock(&bp->link_lock);
1671 bnxt_fw_to_ethtool_support_spds(link_info, lk_ksettings);
1673 ethtool_link_ksettings_zero_link_mode(lk_ksettings, advertising);
1674 if (link_info->autoneg) {
1675 bnxt_fw_to_ethtool_advertised_spds(link_info, lk_ksettings);
1676 ethtool_link_ksettings_add_link_mode(lk_ksettings,
1677 advertising, Autoneg);
1678 base->autoneg = AUTONEG_ENABLE;
1679 base->duplex = DUPLEX_UNKNOWN;
1680 if (link_info->phy_link_status == BNXT_LINK_LINK) {
1681 bnxt_fw_to_ethtool_lp_adv(link_info, lk_ksettings);
1682 if (link_info->duplex & BNXT_LINK_DUPLEX_FULL)
1683 base->duplex = DUPLEX_FULL;
1685 base->duplex = DUPLEX_HALF;
1687 ethtool_speed = bnxt_fw_to_ethtool_speed(link_info->link_speed);
1689 base->autoneg = AUTONEG_DISABLE;
1691 bnxt_fw_to_ethtool_speed(link_info->req_link_speed);
1692 base->duplex = DUPLEX_HALF;
1693 if (link_info->req_duplex == BNXT_LINK_DUPLEX_FULL)
1694 base->duplex = DUPLEX_FULL;
1696 base->speed = ethtool_speed;
1698 base->port = PORT_NONE;
1699 if (link_info->media_type == PORT_PHY_QCFG_RESP_MEDIA_TYPE_TP) {
1700 base->port = PORT_TP;
1701 ethtool_link_ksettings_add_link_mode(lk_ksettings, supported,
1703 ethtool_link_ksettings_add_link_mode(lk_ksettings, advertising,
1706 ethtool_link_ksettings_add_link_mode(lk_ksettings, supported,
1708 ethtool_link_ksettings_add_link_mode(lk_ksettings, advertising,
1711 if (link_info->media_type == PORT_PHY_QCFG_RESP_MEDIA_TYPE_DAC)
1712 base->port = PORT_DA;
1713 else if (link_info->media_type ==
1714 PORT_PHY_QCFG_RESP_MEDIA_TYPE_FIBRE)
1715 base->port = PORT_FIBRE;
1717 base->phy_address = link_info->phy_addr;
1718 mutex_unlock(&bp->link_lock);
1723 static int bnxt_force_link_speed(struct net_device *dev, u32 ethtool_speed)
1725 struct bnxt *bp = netdev_priv(dev);
1726 struct bnxt_link_info *link_info = &bp->link_info;
1727 u16 support_pam4_spds = link_info->support_pam4_speeds;
1728 u16 support_spds = link_info->support_speeds;
1729 u8 sig_mode = BNXT_SIG_MODE_NRZ;
1732 switch (ethtool_speed) {
1734 if (support_spds & BNXT_LINK_SPEED_MSK_100MB)
1735 fw_speed = PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_100MB;
1738 if (support_spds & BNXT_LINK_SPEED_MSK_1GB)
1739 fw_speed = PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_1GB;
1742 if (support_spds & BNXT_LINK_SPEED_MSK_2_5GB)
1743 fw_speed = PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_2_5GB;
1746 if (support_spds & BNXT_LINK_SPEED_MSK_10GB)
1747 fw_speed = PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_10GB;
1750 if (support_spds & BNXT_LINK_SPEED_MSK_20GB)
1751 fw_speed = PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_20GB;
1754 if (support_spds & BNXT_LINK_SPEED_MSK_25GB)
1755 fw_speed = PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_25GB;
1758 if (support_spds & BNXT_LINK_SPEED_MSK_40GB)
1759 fw_speed = PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_40GB;
1762 if (support_spds & BNXT_LINK_SPEED_MSK_50GB) {
1763 fw_speed = PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_50GB;
1764 } else if (support_pam4_spds & BNXT_LINK_PAM4_SPEED_MSK_50GB) {
1765 fw_speed = PORT_PHY_CFG_REQ_FORCE_PAM4_LINK_SPEED_50GB;
1766 sig_mode = BNXT_SIG_MODE_PAM4;
1770 if (support_spds & BNXT_LINK_SPEED_MSK_100GB) {
1771 fw_speed = PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_100GB;
1772 } else if (support_pam4_spds & BNXT_LINK_PAM4_SPEED_MSK_100GB) {
1773 fw_speed = PORT_PHY_CFG_REQ_FORCE_PAM4_LINK_SPEED_100GB;
1774 sig_mode = BNXT_SIG_MODE_PAM4;
1778 if (support_pam4_spds & BNXT_LINK_PAM4_SPEED_MSK_200GB) {
1779 fw_speed = PORT_PHY_CFG_REQ_FORCE_PAM4_LINK_SPEED_200GB;
1780 sig_mode = BNXT_SIG_MODE_PAM4;
1786 netdev_err(dev, "unsupported speed!\n");
1790 if (link_info->req_link_speed == fw_speed &&
1791 link_info->req_signal_mode == sig_mode &&
1792 link_info->autoneg == 0)
1795 link_info->req_link_speed = fw_speed;
1796 link_info->req_signal_mode = sig_mode;
1797 link_info->req_duplex = BNXT_LINK_DUPLEX_FULL;
1798 link_info->autoneg = 0;
1799 link_info->advertising = 0;
1800 link_info->advertising_pam4 = 0;
1805 u16 bnxt_get_fw_auto_link_speeds(u32 advertising)
1807 u16 fw_speed_mask = 0;
1809 /* only support autoneg at speed 100, 1000, and 10000 */
1810 if (advertising & (ADVERTISED_100baseT_Full |
1811 ADVERTISED_100baseT_Half)) {
1812 fw_speed_mask |= BNXT_LINK_SPEED_MSK_100MB;
1814 if (advertising & (ADVERTISED_1000baseT_Full |
1815 ADVERTISED_1000baseT_Half)) {
1816 fw_speed_mask |= BNXT_LINK_SPEED_MSK_1GB;
1818 if (advertising & ADVERTISED_10000baseT_Full)
1819 fw_speed_mask |= BNXT_LINK_SPEED_MSK_10GB;
1821 if (advertising & ADVERTISED_40000baseCR4_Full)
1822 fw_speed_mask |= BNXT_LINK_SPEED_MSK_40GB;
1824 return fw_speed_mask;
1827 static int bnxt_set_link_ksettings(struct net_device *dev,
1828 const struct ethtool_link_ksettings *lk_ksettings)
1830 struct bnxt *bp = netdev_priv(dev);
1831 struct bnxt_link_info *link_info = &bp->link_info;
1832 const struct ethtool_link_settings *base = &lk_ksettings->base;
1833 bool set_pause = false;
1837 if (!BNXT_PHY_CFG_ABLE(bp))
1840 mutex_lock(&bp->link_lock);
1841 if (base->autoneg == AUTONEG_ENABLE) {
1842 link_info->advertising = 0;
1843 link_info->advertising_pam4 = 0;
1844 BNXT_ETHTOOL_TO_FW_SPDS(link_info->advertising, lk_ksettings,
1846 BNXT_ETHTOOL_TO_FW_PAM4_SPDS(link_info->advertising_pam4,
1847 lk_ksettings, advertising);
1848 link_info->autoneg |= BNXT_AUTONEG_SPEED;
1849 if (!link_info->advertising && !link_info->advertising_pam4) {
1850 link_info->advertising = link_info->support_auto_speeds;
1851 link_info->advertising_pam4 =
1852 link_info->support_pam4_auto_speeds;
1854 /* any change to autoneg will cause link change, therefore the
1855 * driver should put back the original pause setting in autoneg
1859 u8 phy_type = link_info->phy_type;
1861 if (phy_type == PORT_PHY_QCFG_RESP_PHY_TYPE_BASET ||
1862 phy_type == PORT_PHY_QCFG_RESP_PHY_TYPE_BASETE ||
1863 link_info->media_type == PORT_PHY_QCFG_RESP_MEDIA_TYPE_TP) {
1864 netdev_err(dev, "10GBase-T devices must autoneg\n");
1866 goto set_setting_exit;
1868 if (base->duplex == DUPLEX_HALF) {
1869 netdev_err(dev, "HALF DUPLEX is not supported!\n");
1871 goto set_setting_exit;
1873 speed = base->speed;
1874 rc = bnxt_force_link_speed(dev, speed);
1876 if (rc == -EALREADY)
1878 goto set_setting_exit;
1882 if (netif_running(dev))
1883 rc = bnxt_hwrm_set_link_setting(bp, set_pause, false);
1886 mutex_unlock(&bp->link_lock);
1890 static int bnxt_get_fecparam(struct net_device *dev,
1891 struct ethtool_fecparam *fec)
1893 struct bnxt *bp = netdev_priv(dev);
1894 struct bnxt_link_info *link_info;
1898 link_info = &bp->link_info;
1899 fec_cfg = link_info->fec_cfg;
1900 active_fec = link_info->active_fec_sig_mode &
1901 PORT_PHY_QCFG_RESP_ACTIVE_FEC_MASK;
1902 if (fec_cfg & BNXT_FEC_NONE) {
1903 fec->fec = ETHTOOL_FEC_NONE;
1904 fec->active_fec = ETHTOOL_FEC_NONE;
1907 if (fec_cfg & BNXT_FEC_AUTONEG)
1908 fec->fec |= ETHTOOL_FEC_AUTO;
1909 if (fec_cfg & BNXT_FEC_ENC_BASE_R)
1910 fec->fec |= ETHTOOL_FEC_BASER;
1911 if (fec_cfg & BNXT_FEC_ENC_RS)
1912 fec->fec |= ETHTOOL_FEC_RS;
1913 if (fec_cfg & BNXT_FEC_ENC_LLRS)
1914 fec->fec |= ETHTOOL_FEC_LLRS;
1916 switch (active_fec) {
1917 case PORT_PHY_QCFG_RESP_ACTIVE_FEC_FEC_CLAUSE74_ACTIVE:
1918 fec->active_fec |= ETHTOOL_FEC_BASER;
1920 case PORT_PHY_QCFG_RESP_ACTIVE_FEC_FEC_CLAUSE91_ACTIVE:
1921 case PORT_PHY_QCFG_RESP_ACTIVE_FEC_FEC_RS544_1XN_ACTIVE:
1922 case PORT_PHY_QCFG_RESP_ACTIVE_FEC_FEC_RS544_IEEE_ACTIVE:
1923 fec->active_fec |= ETHTOOL_FEC_RS;
1925 case PORT_PHY_QCFG_RESP_ACTIVE_FEC_FEC_RS272_1XN_ACTIVE:
1926 case PORT_PHY_QCFG_RESP_ACTIVE_FEC_FEC_RS272_IEEE_ACTIVE:
1927 fec->active_fec |= ETHTOOL_FEC_LLRS;
1933 static u32 bnxt_ethtool_forced_fec_to_fw(struct bnxt_link_info *link_info,
1936 u32 fw_fec = PORT_PHY_CFG_REQ_FLAGS_FEC_AUTONEG_DISABLE;
1938 if (fec & ETHTOOL_FEC_BASER)
1939 fw_fec |= BNXT_FEC_BASE_R_ON(link_info);
1940 else if (fec & ETHTOOL_FEC_RS)
1941 fw_fec |= BNXT_FEC_RS_ON(link_info);
1942 else if (fec & ETHTOOL_FEC_LLRS)
1943 fw_fec |= BNXT_FEC_LLRS_ON;
1947 static int bnxt_set_fecparam(struct net_device *dev,
1948 struct ethtool_fecparam *fecparam)
1950 struct hwrm_port_phy_cfg_input req = {0};
1951 struct bnxt *bp = netdev_priv(dev);
1952 struct bnxt_link_info *link_info;
1953 u32 new_cfg, fec = fecparam->fec;
1957 link_info = &bp->link_info;
1958 fec_cfg = link_info->fec_cfg;
1959 if (fec_cfg & BNXT_FEC_NONE)
1962 if (fec & ETHTOOL_FEC_OFF) {
1963 new_cfg = PORT_PHY_CFG_REQ_FLAGS_FEC_AUTONEG_DISABLE |
1964 BNXT_FEC_ALL_OFF(link_info);
1967 if (((fec & ETHTOOL_FEC_AUTO) && !(fec_cfg & BNXT_FEC_AUTONEG_CAP)) ||
1968 ((fec & ETHTOOL_FEC_RS) && !(fec_cfg & BNXT_FEC_ENC_RS_CAP)) ||
1969 ((fec & ETHTOOL_FEC_LLRS) && !(fec_cfg & BNXT_FEC_ENC_LLRS_CAP)) ||
1970 ((fec & ETHTOOL_FEC_BASER) && !(fec_cfg & BNXT_FEC_ENC_BASE_R_CAP)))
1973 if (fec & ETHTOOL_FEC_AUTO) {
1974 if (!link_info->autoneg)
1976 new_cfg = PORT_PHY_CFG_REQ_FLAGS_FEC_AUTONEG_ENABLE;
1978 new_cfg = bnxt_ethtool_forced_fec_to_fw(link_info, fec);
1982 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_PORT_PHY_CFG, -1, -1);
1983 req.flags = cpu_to_le32(new_cfg | PORT_PHY_CFG_REQ_FLAGS_RESET_PHY);
1984 rc = hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
1985 /* update current settings */
1987 mutex_lock(&bp->link_lock);
1988 bnxt_update_link(bp, false);
1989 mutex_unlock(&bp->link_lock);
1994 static void bnxt_get_pauseparam(struct net_device *dev,
1995 struct ethtool_pauseparam *epause)
1997 struct bnxt *bp = netdev_priv(dev);
1998 struct bnxt_link_info *link_info = &bp->link_info;
2002 epause->autoneg = !!(link_info->autoneg & BNXT_AUTONEG_FLOW_CTRL);
2003 epause->rx_pause = !!(link_info->req_flow_ctrl & BNXT_LINK_PAUSE_RX);
2004 epause->tx_pause = !!(link_info->req_flow_ctrl & BNXT_LINK_PAUSE_TX);
2007 static void bnxt_get_pause_stats(struct net_device *dev,
2008 struct ethtool_pause_stats *epstat)
2010 struct bnxt *bp = netdev_priv(dev);
2013 if (BNXT_VF(bp) || !(bp->flags & BNXT_FLAG_PORT_STATS))
2016 rx = bp->port_stats.sw_stats;
2017 tx = bp->port_stats.sw_stats + BNXT_TX_PORT_STATS_BYTE_OFFSET / 8;
2019 epstat->rx_pause_frames = BNXT_GET_RX_PORT_STATS64(rx, rx_pause_frames);
2020 epstat->tx_pause_frames = BNXT_GET_TX_PORT_STATS64(tx, tx_pause_frames);
2023 static int bnxt_set_pauseparam(struct net_device *dev,
2024 struct ethtool_pauseparam *epause)
2027 struct bnxt *bp = netdev_priv(dev);
2028 struct bnxt_link_info *link_info = &bp->link_info;
2030 if (!BNXT_PHY_CFG_ABLE(bp))
2033 mutex_lock(&bp->link_lock);
2034 if (epause->autoneg) {
2035 if (!(link_info->autoneg & BNXT_AUTONEG_SPEED)) {
2040 link_info->autoneg |= BNXT_AUTONEG_FLOW_CTRL;
2041 if (bp->hwrm_spec_code >= 0x10201)
2042 link_info->req_flow_ctrl =
2043 PORT_PHY_CFG_REQ_AUTO_PAUSE_AUTONEG_PAUSE;
2045 /* when transition from auto pause to force pause,
2046 * force a link change
2048 if (link_info->autoneg & BNXT_AUTONEG_FLOW_CTRL)
2049 link_info->force_link_chng = true;
2050 link_info->autoneg &= ~BNXT_AUTONEG_FLOW_CTRL;
2051 link_info->req_flow_ctrl = 0;
2053 if (epause->rx_pause)
2054 link_info->req_flow_ctrl |= BNXT_LINK_PAUSE_RX;
2056 if (epause->tx_pause)
2057 link_info->req_flow_ctrl |= BNXT_LINK_PAUSE_TX;
2059 if (netif_running(dev))
2060 rc = bnxt_hwrm_set_pause(bp);
2063 mutex_unlock(&bp->link_lock);
2067 static u32 bnxt_get_link(struct net_device *dev)
2069 struct bnxt *bp = netdev_priv(dev);
2071 /* TODO: handle MF, VF, driver close case */
2072 return bp->link_info.link_up;
2075 int bnxt_hwrm_nvm_get_dev_info(struct bnxt *bp,
2076 struct hwrm_nvm_get_dev_info_output *nvm_dev_info)
2078 struct hwrm_nvm_get_dev_info_output *resp = bp->hwrm_cmd_resp_addr;
2079 struct hwrm_nvm_get_dev_info_input req = {0};
2082 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_NVM_GET_DEV_INFO, -1, -1);
2083 mutex_lock(&bp->hwrm_cmd_lock);
2084 rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
2086 memcpy(nvm_dev_info, resp, sizeof(*resp));
2087 mutex_unlock(&bp->hwrm_cmd_lock);
2091 static void bnxt_print_admin_err(struct bnxt *bp)
2093 netdev_info(bp->dev, "PF does not have admin privileges to flash or reset the device\n");
2096 static int bnxt_find_nvram_item(struct net_device *dev, u16 type, u16 ordinal,
2097 u16 ext, u16 *index, u32 *item_length,
2100 static int bnxt_flash_nvram(struct net_device *dev,
2108 struct bnxt *bp = netdev_priv(dev);
2110 struct hwrm_nvm_write_input req = {0};
2111 dma_addr_t dma_handle;
2114 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_NVM_WRITE, -1, -1);
2116 req.dir_type = cpu_to_le16(dir_type);
2117 req.dir_ordinal = cpu_to_le16(dir_ordinal);
2118 req.dir_ext = cpu_to_le16(dir_ext);
2119 req.dir_attr = cpu_to_le16(dir_attr);
2120 req.dir_data_length = cpu_to_le32(data_len);
2122 kmem = dma_alloc_coherent(&bp->pdev->dev, data_len, &dma_handle,
2125 netdev_err(dev, "dma_alloc_coherent failure, length = %u\n",
2126 (unsigned)data_len);
2129 memcpy(kmem, data, data_len);
2130 req.host_src_addr = cpu_to_le64(dma_handle);
2132 rc = hwrm_send_message(bp, &req, sizeof(req), FLASH_NVRAM_TIMEOUT);
2133 dma_free_coherent(&bp->pdev->dev, data_len, kmem, dma_handle);
2136 bnxt_print_admin_err(bp);
2140 static int bnxt_hwrm_firmware_reset(struct net_device *dev, u8 proc_type,
2141 u8 self_reset, u8 flags)
2143 struct hwrm_fw_reset_input req = {0};
2144 struct bnxt *bp = netdev_priv(dev);
2147 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_FW_RESET, -1, -1);
2149 req.embedded_proc_type = proc_type;
2150 req.selfrst_status = self_reset;
2153 if (proc_type == FW_RESET_REQ_EMBEDDED_PROC_TYPE_AP) {
2154 rc = hwrm_send_message_silent(bp, &req, sizeof(req),
2157 rc = hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
2159 bnxt_print_admin_err(bp);
2164 static int bnxt_firmware_reset(struct net_device *dev,
2165 enum bnxt_nvm_directory_type dir_type)
2167 u8 self_reset = FW_RESET_REQ_SELFRST_STATUS_SELFRSTNONE;
2168 u8 proc_type, flags = 0;
2170 /* TODO: Address self-reset of APE/KONG/BONO/TANG or ungraceful reset */
2171 /* (e.g. when firmware isn't already running) */
2173 case BNX_DIR_TYPE_CHIMP_PATCH:
2174 case BNX_DIR_TYPE_BOOTCODE:
2175 case BNX_DIR_TYPE_BOOTCODE_2:
2176 proc_type = FW_RESET_REQ_EMBEDDED_PROC_TYPE_BOOT;
2177 /* Self-reset ChiMP upon next PCIe reset: */
2178 self_reset = FW_RESET_REQ_SELFRST_STATUS_SELFRSTPCIERST;
2180 case BNX_DIR_TYPE_APE_FW:
2181 case BNX_DIR_TYPE_APE_PATCH:
2182 proc_type = FW_RESET_REQ_EMBEDDED_PROC_TYPE_MGMT;
2183 /* Self-reset APE upon next PCIe reset: */
2184 self_reset = FW_RESET_REQ_SELFRST_STATUS_SELFRSTPCIERST;
2186 case BNX_DIR_TYPE_KONG_FW:
2187 case BNX_DIR_TYPE_KONG_PATCH:
2188 proc_type = FW_RESET_REQ_EMBEDDED_PROC_TYPE_NETCTRL;
2190 case BNX_DIR_TYPE_BONO_FW:
2191 case BNX_DIR_TYPE_BONO_PATCH:
2192 proc_type = FW_RESET_REQ_EMBEDDED_PROC_TYPE_ROCE;
2198 return bnxt_hwrm_firmware_reset(dev, proc_type, self_reset, flags);
2201 static int bnxt_firmware_reset_chip(struct net_device *dev)
2203 struct bnxt *bp = netdev_priv(dev);
2206 if (bp->fw_cap & BNXT_FW_CAP_HOT_RESET)
2207 flags = FW_RESET_REQ_FLAGS_RESET_GRACEFUL;
2209 return bnxt_hwrm_firmware_reset(dev,
2210 FW_RESET_REQ_EMBEDDED_PROC_TYPE_CHIP,
2211 FW_RESET_REQ_SELFRST_STATUS_SELFRSTASAP,
2215 static int bnxt_firmware_reset_ap(struct net_device *dev)
2217 return bnxt_hwrm_firmware_reset(dev, FW_RESET_REQ_EMBEDDED_PROC_TYPE_AP,
2218 FW_RESET_REQ_SELFRST_STATUS_SELFRSTNONE,
2222 static int bnxt_flash_firmware(struct net_device *dev,
2231 struct bnxt_fw_header *header = (struct bnxt_fw_header *)fw_data;
2234 case BNX_DIR_TYPE_BOOTCODE:
2235 case BNX_DIR_TYPE_BOOTCODE_2:
2236 code_type = CODE_BOOT;
2238 case BNX_DIR_TYPE_CHIMP_PATCH:
2239 code_type = CODE_CHIMP_PATCH;
2241 case BNX_DIR_TYPE_APE_FW:
2242 code_type = CODE_MCTP_PASSTHRU;
2244 case BNX_DIR_TYPE_APE_PATCH:
2245 code_type = CODE_APE_PATCH;
2247 case BNX_DIR_TYPE_KONG_FW:
2248 code_type = CODE_KONG_FW;
2250 case BNX_DIR_TYPE_KONG_PATCH:
2251 code_type = CODE_KONG_PATCH;
2253 case BNX_DIR_TYPE_BONO_FW:
2254 code_type = CODE_BONO_FW;
2256 case BNX_DIR_TYPE_BONO_PATCH:
2257 code_type = CODE_BONO_PATCH;
2260 netdev_err(dev, "Unsupported directory entry type: %u\n",
2264 if (fw_size < sizeof(struct bnxt_fw_header)) {
2265 netdev_err(dev, "Invalid firmware file size: %u\n",
2266 (unsigned int)fw_size);
2269 if (header->signature != cpu_to_le32(BNXT_FIRMWARE_BIN_SIGNATURE)) {
2270 netdev_err(dev, "Invalid firmware signature: %08X\n",
2271 le32_to_cpu(header->signature));
2274 if (header->code_type != code_type) {
2275 netdev_err(dev, "Expected firmware type: %d, read: %d\n",
2276 code_type, header->code_type);
2279 if (header->device != DEVICE_CUMULUS_FAMILY) {
2280 netdev_err(dev, "Expected firmware device family %d, read: %d\n",
2281 DEVICE_CUMULUS_FAMILY, header->device);
2284 /* Confirm the CRC32 checksum of the file: */
2285 stored_crc = le32_to_cpu(*(__le32 *)(fw_data + fw_size -
2286 sizeof(stored_crc)));
2287 calculated_crc = ~crc32(~0, fw_data, fw_size - sizeof(stored_crc));
2288 if (calculated_crc != stored_crc) {
2289 netdev_err(dev, "Firmware file CRC32 checksum (%08lX) does not match calculated checksum (%08lX)\n",
2290 (unsigned long)stored_crc,
2291 (unsigned long)calculated_crc);
2294 rc = bnxt_flash_nvram(dev, dir_type, BNX_DIR_ORDINAL_FIRST,
2295 0, 0, fw_data, fw_size);
2296 if (rc == 0) /* Firmware update successful */
2297 rc = bnxt_firmware_reset(dev, dir_type);
2302 static int bnxt_flash_microcode(struct net_device *dev,
2307 struct bnxt_ucode_trailer *trailer;
2312 if (fw_size < sizeof(struct bnxt_ucode_trailer)) {
2313 netdev_err(dev, "Invalid microcode file size: %u\n",
2314 (unsigned int)fw_size);
2317 trailer = (struct bnxt_ucode_trailer *)(fw_data + (fw_size -
2319 if (trailer->sig != cpu_to_le32(BNXT_UCODE_TRAILER_SIGNATURE)) {
2320 netdev_err(dev, "Invalid microcode trailer signature: %08X\n",
2321 le32_to_cpu(trailer->sig));
2324 if (le16_to_cpu(trailer->dir_type) != dir_type) {
2325 netdev_err(dev, "Expected microcode type: %d, read: %d\n",
2326 dir_type, le16_to_cpu(trailer->dir_type));
2329 if (le16_to_cpu(trailer->trailer_length) <
2330 sizeof(struct bnxt_ucode_trailer)) {
2331 netdev_err(dev, "Invalid microcode trailer length: %d\n",
2332 le16_to_cpu(trailer->trailer_length));
2336 /* Confirm the CRC32 checksum of the file: */
2337 stored_crc = le32_to_cpu(*(__le32 *)(fw_data + fw_size -
2338 sizeof(stored_crc)));
2339 calculated_crc = ~crc32(~0, fw_data, fw_size - sizeof(stored_crc));
2340 if (calculated_crc != stored_crc) {
2342 "CRC32 (%08lX) does not match calculated: %08lX\n",
2343 (unsigned long)stored_crc,
2344 (unsigned long)calculated_crc);
2347 rc = bnxt_flash_nvram(dev, dir_type, BNX_DIR_ORDINAL_FIRST,
2348 0, 0, fw_data, fw_size);
2353 static bool bnxt_dir_type_is_ape_bin_format(u16 dir_type)
2356 case BNX_DIR_TYPE_CHIMP_PATCH:
2357 case BNX_DIR_TYPE_BOOTCODE:
2358 case BNX_DIR_TYPE_BOOTCODE_2:
2359 case BNX_DIR_TYPE_APE_FW:
2360 case BNX_DIR_TYPE_APE_PATCH:
2361 case BNX_DIR_TYPE_KONG_FW:
2362 case BNX_DIR_TYPE_KONG_PATCH:
2363 case BNX_DIR_TYPE_BONO_FW:
2364 case BNX_DIR_TYPE_BONO_PATCH:
2371 static bool bnxt_dir_type_is_other_exec_format(u16 dir_type)
2374 case BNX_DIR_TYPE_AVS:
2375 case BNX_DIR_TYPE_EXP_ROM_MBA:
2376 case BNX_DIR_TYPE_PCIE:
2377 case BNX_DIR_TYPE_TSCF_UCODE:
2378 case BNX_DIR_TYPE_EXT_PHY:
2379 case BNX_DIR_TYPE_CCM:
2380 case BNX_DIR_TYPE_ISCSI_BOOT:
2381 case BNX_DIR_TYPE_ISCSI_BOOT_IPV6:
2382 case BNX_DIR_TYPE_ISCSI_BOOT_IPV4N6:
2389 static bool bnxt_dir_type_is_executable(u16 dir_type)
2391 return bnxt_dir_type_is_ape_bin_format(dir_type) ||
2392 bnxt_dir_type_is_other_exec_format(dir_type);
2395 static int bnxt_flash_firmware_from_file(struct net_device *dev,
2397 const char *filename)
2399 const struct firmware *fw;
2402 rc = request_firmware(&fw, filename, &dev->dev);
2404 netdev_err(dev, "Error %d requesting firmware file: %s\n",
2408 if (bnxt_dir_type_is_ape_bin_format(dir_type))
2409 rc = bnxt_flash_firmware(dev, dir_type, fw->data, fw->size);
2410 else if (bnxt_dir_type_is_other_exec_format(dir_type))
2411 rc = bnxt_flash_microcode(dev, dir_type, fw->data, fw->size);
2413 rc = bnxt_flash_nvram(dev, dir_type, BNX_DIR_ORDINAL_FIRST,
2414 0, 0, fw->data, fw->size);
2415 release_firmware(fw);
2419 int bnxt_flash_package_from_file(struct net_device *dev, const char *filename,
2422 struct bnxt *bp = netdev_priv(dev);
2423 struct hwrm_nvm_install_update_output *resp = bp->hwrm_cmd_resp_addr;
2424 struct hwrm_nvm_install_update_input install = {0};
2425 const struct firmware *fw;
2430 bnxt_hwrm_fw_set_time(bp);
2432 rc = bnxt_find_nvram_item(dev, BNX_DIR_TYPE_UPDATE,
2433 BNX_DIR_ORDINAL_FIRST, BNX_DIR_EXT_NONE,
2434 &index, &item_len, NULL);
2436 netdev_err(dev, "PKG update area not created in nvram\n");
2440 rc = request_firmware(&fw, filename, &dev->dev);
2442 netdev_err(dev, "PKG error %d requesting file: %s\n",
2447 if (fw->size > item_len) {
2448 netdev_err(dev, "PKG insufficient update area in nvram: %lu\n",
2449 (unsigned long)fw->size);
2452 dma_addr_t dma_handle;
2454 struct hwrm_nvm_modify_input modify = {0};
2456 bnxt_hwrm_cmd_hdr_init(bp, &modify, HWRM_NVM_MODIFY, -1, -1);
2458 modify.dir_idx = cpu_to_le16(index);
2459 modify.len = cpu_to_le32(fw->size);
2461 kmem = dma_alloc_coherent(&bp->pdev->dev, fw->size,
2462 &dma_handle, GFP_KERNEL);
2465 "dma_alloc_coherent failure, length = %u\n",
2466 (unsigned int)fw->size);
2469 memcpy(kmem, fw->data, fw->size);
2470 modify.host_src_addr = cpu_to_le64(dma_handle);
2472 rc = hwrm_send_message(bp, &modify, sizeof(modify),
2473 FLASH_PACKAGE_TIMEOUT);
2474 dma_free_coherent(&bp->pdev->dev, fw->size, kmem,
2478 release_firmware(fw);
2482 if ((install_type & 0xffff) == 0)
2483 install_type >>= 16;
2484 bnxt_hwrm_cmd_hdr_init(bp, &install, HWRM_NVM_INSTALL_UPDATE, -1, -1);
2485 install.install_type = cpu_to_le32(install_type);
2487 mutex_lock(&bp->hwrm_cmd_lock);
2488 rc = _hwrm_send_message(bp, &install, sizeof(install),
2489 INSTALL_PACKAGE_TIMEOUT);
2491 u8 error_code = ((struct hwrm_err_output *)resp)->cmd_err;
2493 if (resp->error_code && error_code ==
2494 NVM_INSTALL_UPDATE_CMD_ERR_CODE_FRAG_ERR) {
2495 install.flags |= cpu_to_le16(
2496 NVM_INSTALL_UPDATE_REQ_FLAGS_ALLOWED_TO_DEFRAG);
2497 rc = _hwrm_send_message(bp, &install, sizeof(install),
2498 INSTALL_PACKAGE_TIMEOUT);
2501 goto flash_pkg_exit;
2505 netdev_err(dev, "PKG install error = %d, problem_item = %d\n",
2506 (s8)resp->result, (int)resp->problem_item);
2510 mutex_unlock(&bp->hwrm_cmd_lock);
2513 bnxt_print_admin_err(bp);
2517 static int bnxt_flash_device(struct net_device *dev,
2518 struct ethtool_flash *flash)
2520 if (!BNXT_PF((struct bnxt *)netdev_priv(dev))) {
2521 netdev_err(dev, "flashdev not supported from a virtual function\n");
2525 if (flash->region == ETHTOOL_FLASH_ALL_REGIONS ||
2526 flash->region > 0xffff)
2527 return bnxt_flash_package_from_file(dev, flash->data,
2530 return bnxt_flash_firmware_from_file(dev, flash->region, flash->data);
2533 static int nvm_get_dir_info(struct net_device *dev, u32 *entries, u32 *length)
2535 struct bnxt *bp = netdev_priv(dev);
2537 struct hwrm_nvm_get_dir_info_input req = {0};
2538 struct hwrm_nvm_get_dir_info_output *output = bp->hwrm_cmd_resp_addr;
2540 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_NVM_GET_DIR_INFO, -1, -1);
2542 mutex_lock(&bp->hwrm_cmd_lock);
2543 rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
2545 *entries = le32_to_cpu(output->entries);
2546 *length = le32_to_cpu(output->entry_length);
2548 mutex_unlock(&bp->hwrm_cmd_lock);
2552 static int bnxt_get_eeprom_len(struct net_device *dev)
2554 struct bnxt *bp = netdev_priv(dev);
2559 /* The -1 return value allows the entire 32-bit range of offsets to be
2560 * passed via the ethtool command-line utility.
2565 static int bnxt_get_nvram_directory(struct net_device *dev, u32 len, u8 *data)
2567 struct bnxt *bp = netdev_priv(dev);
2573 dma_addr_t dma_handle;
2574 struct hwrm_nvm_get_dir_entries_input req = {0};
2576 rc = nvm_get_dir_info(dev, &dir_entries, &entry_length);
2580 if (!dir_entries || !entry_length)
2583 /* Insert 2 bytes of directory info (count and size of entries) */
2587 *data++ = dir_entries;
2588 *data++ = entry_length;
2590 memset(data, 0xff, len);
2592 buflen = dir_entries * entry_length;
2593 buf = dma_alloc_coherent(&bp->pdev->dev, buflen, &dma_handle,
2596 netdev_err(dev, "dma_alloc_coherent failure, length = %u\n",
2600 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_NVM_GET_DIR_ENTRIES, -1, -1);
2601 req.host_dest_addr = cpu_to_le64(dma_handle);
2602 rc = hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
2604 memcpy(data, buf, len > buflen ? buflen : len);
2605 dma_free_coherent(&bp->pdev->dev, buflen, buf, dma_handle);
2609 static int bnxt_get_nvram_item(struct net_device *dev, u32 index, u32 offset,
2610 u32 length, u8 *data)
2612 struct bnxt *bp = netdev_priv(dev);
2615 dma_addr_t dma_handle;
2616 struct hwrm_nvm_read_input req = {0};
2621 buf = dma_alloc_coherent(&bp->pdev->dev, length, &dma_handle,
2624 netdev_err(dev, "dma_alloc_coherent failure, length = %u\n",
2628 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_NVM_READ, -1, -1);
2629 req.host_dest_addr = cpu_to_le64(dma_handle);
2630 req.dir_idx = cpu_to_le16(index);
2631 req.offset = cpu_to_le32(offset);
2632 req.len = cpu_to_le32(length);
2634 rc = hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
2636 memcpy(data, buf, length);
2637 dma_free_coherent(&bp->pdev->dev, length, buf, dma_handle);
2641 static int bnxt_find_nvram_item(struct net_device *dev, u16 type, u16 ordinal,
2642 u16 ext, u16 *index, u32 *item_length,
2645 struct bnxt *bp = netdev_priv(dev);
2647 struct hwrm_nvm_find_dir_entry_input req = {0};
2648 struct hwrm_nvm_find_dir_entry_output *output = bp->hwrm_cmd_resp_addr;
2650 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_NVM_FIND_DIR_ENTRY, -1, -1);
2653 req.dir_type = cpu_to_le16(type);
2654 req.dir_ordinal = cpu_to_le16(ordinal);
2655 req.dir_ext = cpu_to_le16(ext);
2656 req.opt_ordinal = NVM_FIND_DIR_ENTRY_REQ_OPT_ORDINAL_EQ;
2657 mutex_lock(&bp->hwrm_cmd_lock);
2658 rc = _hwrm_send_message_silent(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
2661 *index = le16_to_cpu(output->dir_idx);
2663 *item_length = le32_to_cpu(output->dir_item_length);
2665 *data_length = le32_to_cpu(output->dir_data_length);
2667 mutex_unlock(&bp->hwrm_cmd_lock);
2671 static char *bnxt_parse_pkglog(int desired_field, u8 *data, size_t datalen)
2673 char *retval = NULL;
2680 /* null-terminate the log data (removing last '\n'): */
2681 data[datalen - 1] = 0;
2682 for (p = data; *p != 0; p++) {
2685 while (*p != 0 && *p != '\n') {
2687 while (*p != 0 && *p != '\t' && *p != '\n')
2689 if (field == desired_field)
2704 static void bnxt_get_pkgver(struct net_device *dev)
2706 struct bnxt *bp = netdev_priv(dev);
2713 if (bnxt_find_nvram_item(dev, BNX_DIR_TYPE_PKG_LOG,
2714 BNX_DIR_ORDINAL_FIRST, BNX_DIR_EXT_NONE,
2715 &index, NULL, &pkglen) != 0)
2718 pkgbuf = kzalloc(pkglen, GFP_KERNEL);
2720 dev_err(&bp->pdev->dev, "Unable to allocate memory for pkg version, length = %u\n",
2725 if (bnxt_get_nvram_item(dev, index, 0, pkglen, pkgbuf))
2728 pkgver = bnxt_parse_pkglog(BNX_PKG_LOG_FIELD_IDX_PKG_VERSION, pkgbuf,
2730 if (pkgver && *pkgver != 0 && isdigit(*pkgver)) {
2731 len = strlen(bp->fw_ver_str);
2732 snprintf(bp->fw_ver_str + len, FW_VER_STR_LEN - len - 1,
2739 static int bnxt_get_eeprom(struct net_device *dev,
2740 struct ethtool_eeprom *eeprom,
2746 if (eeprom->offset == 0) /* special offset value to get directory */
2747 return bnxt_get_nvram_directory(dev, eeprom->len, data);
2749 index = eeprom->offset >> 24;
2750 offset = eeprom->offset & 0xffffff;
2753 netdev_err(dev, "unsupported index value: %d\n", index);
2757 return bnxt_get_nvram_item(dev, index - 1, offset, eeprom->len, data);
2760 static int bnxt_erase_nvram_directory(struct net_device *dev, u8 index)
2762 struct bnxt *bp = netdev_priv(dev);
2763 struct hwrm_nvm_erase_dir_entry_input req = {0};
2765 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_NVM_ERASE_DIR_ENTRY, -1, -1);
2766 req.dir_idx = cpu_to_le16(index);
2767 return hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
2770 static int bnxt_set_eeprom(struct net_device *dev,
2771 struct ethtool_eeprom *eeprom,
2774 struct bnxt *bp = netdev_priv(dev);
2776 u16 type, ext, ordinal, attr;
2779 netdev_err(dev, "NVM write not supported from a virtual function\n");
2783 type = eeprom->magic >> 16;
2785 if (type == 0xffff) { /* special value for directory operations */
2786 index = eeprom->magic & 0xff;
2787 dir_op = eeprom->magic >> 8;
2791 case 0x0e: /* erase */
2792 if (eeprom->offset != ~eeprom->magic)
2794 return bnxt_erase_nvram_directory(dev, index - 1);
2800 /* Create or re-write an NVM item: */
2801 if (bnxt_dir_type_is_executable(type))
2803 ext = eeprom->magic & 0xffff;
2804 ordinal = eeprom->offset >> 16;
2805 attr = eeprom->offset & 0xffff;
2807 return bnxt_flash_nvram(dev, type, ordinal, ext, attr, data,
2811 static int bnxt_set_eee(struct net_device *dev, struct ethtool_eee *edata)
2813 struct bnxt *bp = netdev_priv(dev);
2814 struct ethtool_eee *eee = &bp->eee;
2815 struct bnxt_link_info *link_info = &bp->link_info;
2819 if (!BNXT_PHY_CFG_ABLE(bp))
2822 if (!(bp->flags & BNXT_FLAG_EEE_CAP))
2825 mutex_lock(&bp->link_lock);
2826 advertising = _bnxt_fw_to_ethtool_adv_spds(link_info->advertising, 0);
2827 if (!edata->eee_enabled)
2830 if (!(link_info->autoneg & BNXT_AUTONEG_SPEED)) {
2831 netdev_warn(dev, "EEE requires autoneg\n");
2835 if (edata->tx_lpi_enabled) {
2836 if (bp->lpi_tmr_hi && (edata->tx_lpi_timer > bp->lpi_tmr_hi ||
2837 edata->tx_lpi_timer < bp->lpi_tmr_lo)) {
2838 netdev_warn(dev, "Valid LPI timer range is %d and %d microsecs\n",
2839 bp->lpi_tmr_lo, bp->lpi_tmr_hi);
2842 } else if (!bp->lpi_tmr_hi) {
2843 edata->tx_lpi_timer = eee->tx_lpi_timer;
2846 if (!edata->advertised) {
2847 edata->advertised = advertising & eee->supported;
2848 } else if (edata->advertised & ~advertising) {
2849 netdev_warn(dev, "EEE advertised %x must be a subset of autoneg advertised speeds %x\n",
2850 edata->advertised, advertising);
2855 eee->advertised = edata->advertised;
2856 eee->tx_lpi_enabled = edata->tx_lpi_enabled;
2857 eee->tx_lpi_timer = edata->tx_lpi_timer;
2859 eee->eee_enabled = edata->eee_enabled;
2861 if (netif_running(dev))
2862 rc = bnxt_hwrm_set_link_setting(bp, false, true);
2865 mutex_unlock(&bp->link_lock);
2869 static int bnxt_get_eee(struct net_device *dev, struct ethtool_eee *edata)
2871 struct bnxt *bp = netdev_priv(dev);
2873 if (!(bp->flags & BNXT_FLAG_EEE_CAP))
2877 if (!bp->eee.eee_enabled) {
2878 /* Preserve tx_lpi_timer so that the last value will be used
2879 * by default when it is re-enabled.
2881 edata->advertised = 0;
2882 edata->tx_lpi_enabled = 0;
2885 if (!bp->eee.eee_active)
2886 edata->lp_advertised = 0;
2891 static int bnxt_read_sfp_module_eeprom_info(struct bnxt *bp, u16 i2c_addr,
2892 u16 page_number, u16 start_addr,
2893 u16 data_length, u8 *buf)
2895 struct hwrm_port_phy_i2c_read_input req = {0};
2896 struct hwrm_port_phy_i2c_read_output *output = bp->hwrm_cmd_resp_addr;
2897 int rc, byte_offset = 0;
2899 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_PORT_PHY_I2C_READ, -1, -1);
2900 req.i2c_slave_addr = i2c_addr;
2901 req.page_number = cpu_to_le16(page_number);
2902 req.port_id = cpu_to_le16(bp->pf.port_id);
2906 xfer_size = min_t(u16, data_length, BNXT_MAX_PHY_I2C_RESP_SIZE);
2907 data_length -= xfer_size;
2908 req.page_offset = cpu_to_le16(start_addr + byte_offset);
2909 req.data_length = xfer_size;
2910 req.enables = cpu_to_le32(start_addr + byte_offset ?
2911 PORT_PHY_I2C_READ_REQ_ENABLES_PAGE_OFFSET : 0);
2912 mutex_lock(&bp->hwrm_cmd_lock);
2913 rc = _hwrm_send_message(bp, &req, sizeof(req),
2916 memcpy(buf + byte_offset, output->data, xfer_size);
2917 mutex_unlock(&bp->hwrm_cmd_lock);
2918 byte_offset += xfer_size;
2919 } while (!rc && data_length > 0);
2924 static int bnxt_get_module_info(struct net_device *dev,
2925 struct ethtool_modinfo *modinfo)
2927 u8 data[SFF_DIAG_SUPPORT_OFFSET + 1];
2928 struct bnxt *bp = netdev_priv(dev);
2931 /* No point in going further if phy status indicates
2932 * module is not inserted or if it is powered down or
2933 * if it is of type 10GBase-T
2935 if (bp->link_info.module_status >
2936 PORT_PHY_QCFG_RESP_MODULE_STATUS_WARNINGMSG)
2939 /* This feature is not supported in older firmware versions */
2940 if (bp->hwrm_spec_code < 0x10202)
2943 rc = bnxt_read_sfp_module_eeprom_info(bp, I2C_DEV_ADDR_A0, 0, 0,
2944 SFF_DIAG_SUPPORT_OFFSET + 1,
2947 u8 module_id = data[0];
2948 u8 diag_supported = data[SFF_DIAG_SUPPORT_OFFSET];
2950 switch (module_id) {
2951 case SFF_MODULE_ID_SFP:
2952 modinfo->type = ETH_MODULE_SFF_8472;
2953 modinfo->eeprom_len = ETH_MODULE_SFF_8472_LEN;
2954 if (!diag_supported)
2955 modinfo->eeprom_len = ETH_MODULE_SFF_8436_LEN;
2957 case SFF_MODULE_ID_QSFP:
2958 case SFF_MODULE_ID_QSFP_PLUS:
2959 modinfo->type = ETH_MODULE_SFF_8436;
2960 modinfo->eeprom_len = ETH_MODULE_SFF_8436_LEN;
2962 case SFF_MODULE_ID_QSFP28:
2963 modinfo->type = ETH_MODULE_SFF_8636;
2964 modinfo->eeprom_len = ETH_MODULE_SFF_8636_LEN;
2974 static int bnxt_get_module_eeprom(struct net_device *dev,
2975 struct ethtool_eeprom *eeprom,
2978 struct bnxt *bp = netdev_priv(dev);
2979 u16 start = eeprom->offset, length = eeprom->len;
2982 memset(data, 0, eeprom->len);
2984 /* Read A0 portion of the EEPROM */
2985 if (start < ETH_MODULE_SFF_8436_LEN) {
2986 if (start + eeprom->len > ETH_MODULE_SFF_8436_LEN)
2987 length = ETH_MODULE_SFF_8436_LEN - start;
2988 rc = bnxt_read_sfp_module_eeprom_info(bp, I2C_DEV_ADDR_A0, 0,
2989 start, length, data);
2994 length = eeprom->len - length;
2997 /* Read A2 portion of the EEPROM */
2999 start -= ETH_MODULE_SFF_8436_LEN;
3000 rc = bnxt_read_sfp_module_eeprom_info(bp, I2C_DEV_ADDR_A2, 1,
3001 start, length, data);
3006 static int bnxt_nway_reset(struct net_device *dev)
3010 struct bnxt *bp = netdev_priv(dev);
3011 struct bnxt_link_info *link_info = &bp->link_info;
3013 if (!BNXT_PHY_CFG_ABLE(bp))
3016 if (!(link_info->autoneg & BNXT_AUTONEG_SPEED))
3019 if (netif_running(dev))
3020 rc = bnxt_hwrm_set_link_setting(bp, true, false);
3025 static int bnxt_set_phys_id(struct net_device *dev,
3026 enum ethtool_phys_id_state state)
3028 struct hwrm_port_led_cfg_input req = {0};
3029 struct bnxt *bp = netdev_priv(dev);
3030 struct bnxt_pf_info *pf = &bp->pf;
3031 struct bnxt_led_cfg *led_cfg;
3036 if (!bp->num_leds || BNXT_VF(bp))
3039 if (state == ETHTOOL_ID_ACTIVE) {
3040 led_state = PORT_LED_CFG_REQ_LED0_STATE_BLINKALT;
3041 duration = cpu_to_le16(500);
3042 } else if (state == ETHTOOL_ID_INACTIVE) {
3043 led_state = PORT_LED_CFG_REQ_LED1_STATE_DEFAULT;
3044 duration = cpu_to_le16(0);
3048 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_PORT_LED_CFG, -1, -1);
3049 req.port_id = cpu_to_le16(pf->port_id);
3050 req.num_leds = bp->num_leds;
3051 led_cfg = (struct bnxt_led_cfg *)&req.led0_id;
3052 for (i = 0; i < bp->num_leds; i++, led_cfg++) {
3053 req.enables |= BNXT_LED_DFLT_ENABLES(i);
3054 led_cfg->led_id = bp->leds[i].led_id;
3055 led_cfg->led_state = led_state;
3056 led_cfg->led_blink_on = duration;
3057 led_cfg->led_blink_off = duration;
3058 led_cfg->led_group_id = bp->leds[i].led_group_id;
3060 return hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
3063 static int bnxt_hwrm_selftest_irq(struct bnxt *bp, u16 cmpl_ring)
3065 struct hwrm_selftest_irq_input req = {0};
3067 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_SELFTEST_IRQ, cmpl_ring, -1);
3068 return hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
3071 static int bnxt_test_irq(struct bnxt *bp)
3075 for (i = 0; i < bp->cp_nr_rings; i++) {
3076 u16 cmpl_ring = bp->grp_info[i].cp_fw_ring_id;
3079 rc = bnxt_hwrm_selftest_irq(bp, cmpl_ring);
3086 static int bnxt_hwrm_mac_loopback(struct bnxt *bp, bool enable)
3088 struct hwrm_port_mac_cfg_input req = {0};
3090 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_PORT_MAC_CFG, -1, -1);
3092 req.enables = cpu_to_le32(PORT_MAC_CFG_REQ_ENABLES_LPBK);
3094 req.lpbk = PORT_MAC_CFG_REQ_LPBK_LOCAL;
3096 req.lpbk = PORT_MAC_CFG_REQ_LPBK_NONE;
3097 return hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
3100 static int bnxt_query_force_speeds(struct bnxt *bp, u16 *force_speeds)
3102 struct hwrm_port_phy_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
3103 struct hwrm_port_phy_qcaps_input req = {0};
3106 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_PORT_PHY_QCAPS, -1, -1);
3107 mutex_lock(&bp->hwrm_cmd_lock);
3108 rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
3110 *force_speeds = le16_to_cpu(resp->supported_speeds_force_mode);
3112 mutex_unlock(&bp->hwrm_cmd_lock);
3116 static int bnxt_disable_an_for_lpbk(struct bnxt *bp,
3117 struct hwrm_port_phy_cfg_input *req)
3119 struct bnxt_link_info *link_info = &bp->link_info;
3124 if (!link_info->autoneg ||
3125 (bp->test_info->flags & BNXT_TEST_FL_AN_PHY_LPBK))
3128 rc = bnxt_query_force_speeds(bp, &fw_advertising);
3132 fw_speed = PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_1GB;
3133 if (bp->link_info.link_up)
3134 fw_speed = bp->link_info.link_speed;
3135 else if (fw_advertising & BNXT_LINK_SPEED_MSK_10GB)
3136 fw_speed = PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_10GB;
3137 else if (fw_advertising & BNXT_LINK_SPEED_MSK_25GB)
3138 fw_speed = PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_25GB;
3139 else if (fw_advertising & BNXT_LINK_SPEED_MSK_40GB)
3140 fw_speed = PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_40GB;
3141 else if (fw_advertising & BNXT_LINK_SPEED_MSK_50GB)
3142 fw_speed = PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_50GB;
3144 req->force_link_speed = cpu_to_le16(fw_speed);
3145 req->flags |= cpu_to_le32(PORT_PHY_CFG_REQ_FLAGS_FORCE |
3146 PORT_PHY_CFG_REQ_FLAGS_RESET_PHY);
3147 rc = hwrm_send_message(bp, req, sizeof(*req), HWRM_CMD_TIMEOUT);
3149 req->force_link_speed = cpu_to_le16(0);
3153 static int bnxt_hwrm_phy_loopback(struct bnxt *bp, bool enable, bool ext)
3155 struct hwrm_port_phy_cfg_input req = {0};
3157 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_PORT_PHY_CFG, -1, -1);
3160 bnxt_disable_an_for_lpbk(bp, &req);
3162 req.lpbk = PORT_PHY_CFG_REQ_LPBK_EXTERNAL;
3164 req.lpbk = PORT_PHY_CFG_REQ_LPBK_LOCAL;
3166 req.lpbk = PORT_PHY_CFG_REQ_LPBK_NONE;
3168 req.enables = cpu_to_le32(PORT_PHY_CFG_REQ_ENABLES_LPBK);
3169 return hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
3172 static int bnxt_rx_loopback(struct bnxt *bp, struct bnxt_cp_ring_info *cpr,
3173 u32 raw_cons, int pkt_size)
3175 struct bnxt_napi *bnapi = cpr->bnapi;
3176 struct bnxt_rx_ring_info *rxr;
3177 struct bnxt_sw_rx_bd *rx_buf;
3178 struct rx_cmp *rxcmp;
3184 rxr = bnapi->rx_ring;
3185 cp_cons = RING_CMP(raw_cons);
3186 rxcmp = (struct rx_cmp *)
3187 &cpr->cp_desc_ring[CP_RING(cp_cons)][CP_IDX(cp_cons)];
3188 cons = rxcmp->rx_cmp_opaque;
3189 rx_buf = &rxr->rx_buf_ring[cons];
3190 data = rx_buf->data_ptr;
3191 len = le32_to_cpu(rxcmp->rx_cmp_len_flags_type) >> RX_CMP_LEN_SHIFT;
3192 if (len != pkt_size)
3195 if (!ether_addr_equal(data + i, bnapi->bp->dev->dev_addr))
3198 for ( ; i < pkt_size; i++) {
3199 if (data[i] != (u8)(i & 0xff))
3205 static int bnxt_poll_loopback(struct bnxt *bp, struct bnxt_cp_ring_info *cpr,
3208 struct tx_cmp *txcmp;
3214 raw_cons = cpr->cp_raw_cons;
3215 for (i = 0; i < 200; i++) {
3216 cons = RING_CMP(raw_cons);
3217 txcmp = &cpr->cp_desc_ring[CP_RING(cons)][CP_IDX(cons)];
3219 if (!TX_CMP_VALID(txcmp, raw_cons)) {
3224 /* The valid test of the entry must be done first before
3225 * reading any further.
3228 if (TX_CMP_TYPE(txcmp) == CMP_TYPE_RX_L2_CMP) {
3229 rc = bnxt_rx_loopback(bp, cpr, raw_cons, pkt_size);
3230 raw_cons = NEXT_RAW_CMP(raw_cons);
3231 raw_cons = NEXT_RAW_CMP(raw_cons);
3234 raw_cons = NEXT_RAW_CMP(raw_cons);
3236 cpr->cp_raw_cons = raw_cons;
3240 static int bnxt_run_loopback(struct bnxt *bp)
3242 struct bnxt_tx_ring_info *txr = &bp->tx_ring[0];
3243 struct bnxt_rx_ring_info *rxr = &bp->rx_ring[0];
3244 struct bnxt_cp_ring_info *cpr;
3245 int pkt_size, i = 0;
3246 struct sk_buff *skb;
3251 cpr = &rxr->bnapi->cp_ring;
3252 if (bp->flags & BNXT_FLAG_CHIP_P5)
3253 cpr = cpr->cp_ring_arr[BNXT_RX_HDL];
3254 pkt_size = min(bp->dev->mtu + ETH_HLEN, bp->rx_copy_thresh);
3255 skb = netdev_alloc_skb(bp->dev, pkt_size);
3258 data = skb_put(skb, pkt_size);
3259 eth_broadcast_addr(data);
3261 ether_addr_copy(&data[i], bp->dev->dev_addr);
3263 for ( ; i < pkt_size; i++)
3264 data[i] = (u8)(i & 0xff);
3266 map = dma_map_single(&bp->pdev->dev, skb->data, pkt_size,
3268 if (dma_mapping_error(&bp->pdev->dev, map)) {
3272 bnxt_xmit_bd(bp, txr, map, pkt_size);
3274 /* Sync BD data before updating doorbell */
3277 bnxt_db_write(bp, &txr->tx_db, txr->tx_prod);
3278 rc = bnxt_poll_loopback(bp, cpr, pkt_size);
3280 dma_unmap_single(&bp->pdev->dev, map, pkt_size, PCI_DMA_TODEVICE);
3285 static int bnxt_run_fw_tests(struct bnxt *bp, u8 test_mask, u8 *test_results)
3287 struct hwrm_selftest_exec_output *resp = bp->hwrm_cmd_resp_addr;
3288 struct hwrm_selftest_exec_input req = {0};
3291 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_SELFTEST_EXEC, -1, -1);
3292 mutex_lock(&bp->hwrm_cmd_lock);
3293 resp->test_success = 0;
3294 req.flags = test_mask;
3295 rc = _hwrm_send_message(bp, &req, sizeof(req), bp->test_info->timeout);
3296 *test_results = resp->test_success;
3297 mutex_unlock(&bp->hwrm_cmd_lock);
3301 #define BNXT_DRV_TESTS 4
3302 #define BNXT_MACLPBK_TEST_IDX (bp->num_tests - BNXT_DRV_TESTS)
3303 #define BNXT_PHYLPBK_TEST_IDX (BNXT_MACLPBK_TEST_IDX + 1)
3304 #define BNXT_EXTLPBK_TEST_IDX (BNXT_MACLPBK_TEST_IDX + 2)
3305 #define BNXT_IRQ_TEST_IDX (BNXT_MACLPBK_TEST_IDX + 3)
3307 static void bnxt_self_test(struct net_device *dev, struct ethtool_test *etest,
3310 struct bnxt *bp = netdev_priv(dev);
3311 bool do_ext_lpbk = false;
3312 bool offline = false;
3313 u8 test_results = 0;
3317 if (!bp->num_tests || !BNXT_PF(bp))
3319 memset(buf, 0, sizeof(u64) * bp->num_tests);
3320 if (!netif_running(dev)) {
3321 etest->flags |= ETH_TEST_FL_FAILED;
3325 if ((etest->flags & ETH_TEST_FL_EXTERNAL_LB) &&
3326 (bp->test_info->flags & BNXT_TEST_FL_EXT_LPBK))
3329 if (etest->flags & ETH_TEST_FL_OFFLINE) {
3330 if (bp->pf.active_vfs || !BNXT_SINGLE_PF(bp)) {
3331 etest->flags |= ETH_TEST_FL_FAILED;
3332 netdev_warn(dev, "Offline tests cannot be run with active VFs or on shared PF\n");
3338 for (i = 0; i < bp->num_tests - BNXT_DRV_TESTS; i++) {
3339 u8 bit_val = 1 << i;
3341 if (!(bp->test_info->offline_mask & bit_val))
3342 test_mask |= bit_val;
3344 test_mask |= bit_val;
3347 bnxt_run_fw_tests(bp, test_mask, &test_results);
3349 rc = bnxt_close_nic(bp, false, false);
3352 bnxt_run_fw_tests(bp, test_mask, &test_results);
3354 buf[BNXT_MACLPBK_TEST_IDX] = 1;
3355 bnxt_hwrm_mac_loopback(bp, true);
3357 rc = bnxt_half_open_nic(bp);
3359 bnxt_hwrm_mac_loopback(bp, false);
3360 etest->flags |= ETH_TEST_FL_FAILED;
3363 if (bnxt_run_loopback(bp))
3364 etest->flags |= ETH_TEST_FL_FAILED;
3366 buf[BNXT_MACLPBK_TEST_IDX] = 0;
3368 bnxt_hwrm_mac_loopback(bp, false);
3369 bnxt_hwrm_phy_loopback(bp, true, false);
3371 if (bnxt_run_loopback(bp)) {
3372 buf[BNXT_PHYLPBK_TEST_IDX] = 1;
3373 etest->flags |= ETH_TEST_FL_FAILED;
3376 etest->flags |= ETH_TEST_FL_EXTERNAL_LB_DONE;
3377 bnxt_hwrm_phy_loopback(bp, true, true);
3379 if (bnxt_run_loopback(bp)) {
3380 buf[BNXT_EXTLPBK_TEST_IDX] = 1;
3381 etest->flags |= ETH_TEST_FL_FAILED;
3384 bnxt_hwrm_phy_loopback(bp, false, false);
3385 bnxt_half_close_nic(bp);
3386 rc = bnxt_open_nic(bp, false, true);
3388 if (rc || bnxt_test_irq(bp)) {
3389 buf[BNXT_IRQ_TEST_IDX] = 1;
3390 etest->flags |= ETH_TEST_FL_FAILED;
3392 for (i = 0; i < bp->num_tests - BNXT_DRV_TESTS; i++) {
3393 u8 bit_val = 1 << i;
3395 if ((test_mask & bit_val) && !(test_results & bit_val)) {
3397 etest->flags |= ETH_TEST_FL_FAILED;
3402 static int bnxt_reset(struct net_device *dev, u32 *flags)
3404 struct bnxt *bp = netdev_priv(dev);
3405 bool reload = false;
3412 netdev_err(dev, "Reset is not supported from a VF\n");
3416 if (pci_vfs_assigned(bp->pdev) &&
3417 !(bp->fw_cap & BNXT_FW_CAP_HOT_RESET)) {
3419 "Reset not allowed when VFs are assigned to VMs\n");
3423 if ((req & BNXT_FW_RESET_CHIP) == BNXT_FW_RESET_CHIP) {
3424 /* This feature is not supported in older firmware versions */
3425 if (bp->hwrm_spec_code >= 0x10803) {
3426 if (!bnxt_firmware_reset_chip(dev)) {
3427 netdev_info(dev, "Firmware reset request successful.\n");
3428 if (!(bp->fw_cap & BNXT_FW_CAP_HOT_RESET))
3430 *flags &= ~BNXT_FW_RESET_CHIP;
3432 } else if (req == BNXT_FW_RESET_CHIP) {
3433 return -EOPNOTSUPP; /* only request, fail hard */
3437 if (req & BNXT_FW_RESET_AP) {
3438 /* This feature is not supported in older firmware versions */
3439 if (bp->hwrm_spec_code >= 0x10803) {
3440 if (!bnxt_firmware_reset_ap(dev)) {
3441 netdev_info(dev, "Reset application processor successful.\n");
3443 *flags &= ~BNXT_FW_RESET_AP;
3445 } else if (req == BNXT_FW_RESET_AP) {
3446 return -EOPNOTSUPP; /* only request, fail hard */
3451 netdev_info(dev, "Reload driver to complete reset\n");
3456 static int bnxt_hwrm_dbg_dma_data(struct bnxt *bp, void *msg, int msg_len,
3457 struct bnxt_hwrm_dbg_dma_info *info)
3459 struct hwrm_dbg_cmn_output *cmn_resp = bp->hwrm_cmd_resp_addr;
3460 struct hwrm_dbg_cmn_input *cmn_req = msg;
3461 __le16 *seq_ptr = msg + info->seq_off;
3462 u16 seq = 0, len, segs_off;
3463 void *resp = cmn_resp;
3464 dma_addr_t dma_handle;
3468 dma_buf = dma_alloc_coherent(&bp->pdev->dev, info->dma_len, &dma_handle,
3473 segs_off = offsetof(struct hwrm_dbg_coredump_list_output,
3475 cmn_req->host_dest_addr = cpu_to_le64(dma_handle);
3476 cmn_req->host_buf_len = cpu_to_le32(info->dma_len);
3477 mutex_lock(&bp->hwrm_cmd_lock);
3479 *seq_ptr = cpu_to_le16(seq);
3480 rc = _hwrm_send_message(bp, msg, msg_len,
3481 HWRM_COREDUMP_TIMEOUT);
3485 len = le16_to_cpu(*((__le16 *)(resp + info->data_len_off)));
3487 cmn_req->req_type == cpu_to_le16(HWRM_DBG_COREDUMP_LIST)) {
3488 info->segs = le16_to_cpu(*((__le16 *)(resp +
3495 info->dest_buf_size = info->segs *
3496 sizeof(struct coredump_segment_record);
3497 info->dest_buf = kmalloc(info->dest_buf_size,
3499 if (!info->dest_buf) {
3505 if (info->dest_buf) {
3506 if ((info->seg_start + off + len) <=
3507 BNXT_COREDUMP_BUF_LEN(info->buf_len)) {
3508 memcpy(info->dest_buf + off, dma_buf, len);
3515 if (cmn_req->req_type ==
3516 cpu_to_le16(HWRM_DBG_COREDUMP_RETRIEVE))
3517 info->dest_buf_size += len;
3519 if (!(cmn_resp->flags & HWRM_DBG_CMN_FLAGS_MORE))
3525 mutex_unlock(&bp->hwrm_cmd_lock);
3526 dma_free_coherent(&bp->pdev->dev, info->dma_len, dma_buf, dma_handle);
3530 static int bnxt_hwrm_dbg_coredump_list(struct bnxt *bp,
3531 struct bnxt_coredump *coredump)
3533 struct hwrm_dbg_coredump_list_input req = {0};
3534 struct bnxt_hwrm_dbg_dma_info info = {NULL};
3537 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_DBG_COREDUMP_LIST, -1, -1);
3539 info.dma_len = COREDUMP_LIST_BUF_LEN;
3540 info.seq_off = offsetof(struct hwrm_dbg_coredump_list_input, seq_no);
3541 info.data_len_off = offsetof(struct hwrm_dbg_coredump_list_output,
3544 rc = bnxt_hwrm_dbg_dma_data(bp, &req, sizeof(req), &info);
3546 coredump->data = info.dest_buf;
3547 coredump->data_size = info.dest_buf_size;
3548 coredump->total_segs = info.segs;
3553 static int bnxt_hwrm_dbg_coredump_initiate(struct bnxt *bp, u16 component_id,
3556 struct hwrm_dbg_coredump_initiate_input req = {0};
3558 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_DBG_COREDUMP_INITIATE, -1, -1);
3559 req.component_id = cpu_to_le16(component_id);
3560 req.segment_id = cpu_to_le16(segment_id);
3562 return hwrm_send_message(bp, &req, sizeof(req), HWRM_COREDUMP_TIMEOUT);
3565 static int bnxt_hwrm_dbg_coredump_retrieve(struct bnxt *bp, u16 component_id,
3566 u16 segment_id, u32 *seg_len,
3567 void *buf, u32 buf_len, u32 offset)
3569 struct hwrm_dbg_coredump_retrieve_input req = {0};
3570 struct bnxt_hwrm_dbg_dma_info info = {NULL};
3573 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_DBG_COREDUMP_RETRIEVE, -1, -1);
3574 req.component_id = cpu_to_le16(component_id);
3575 req.segment_id = cpu_to_le16(segment_id);
3577 info.dma_len = COREDUMP_RETRIEVE_BUF_LEN;
3578 info.seq_off = offsetof(struct hwrm_dbg_coredump_retrieve_input,
3580 info.data_len_off = offsetof(struct hwrm_dbg_coredump_retrieve_output,
3583 info.dest_buf = buf + offset;
3584 info.buf_len = buf_len;
3585 info.seg_start = offset;
3588 rc = bnxt_hwrm_dbg_dma_data(bp, &req, sizeof(req), &info);
3590 *seg_len = info.dest_buf_size;
3596 bnxt_fill_coredump_seg_hdr(struct bnxt *bp,
3597 struct bnxt_coredump_segment_hdr *seg_hdr,
3598 struct coredump_segment_record *seg_rec, u32 seg_len,
3599 int status, u32 duration, u32 instance)
3601 memset(seg_hdr, 0, sizeof(*seg_hdr));
3602 memcpy(seg_hdr->signature, "sEgM", 4);
3604 seg_hdr->component_id = (__force __le32)seg_rec->component_id;
3605 seg_hdr->segment_id = (__force __le32)seg_rec->segment_id;
3606 seg_hdr->low_version = seg_rec->version_low;
3607 seg_hdr->high_version = seg_rec->version_hi;
3609 /* For hwrm_ver_get response Component id = 2
3610 * and Segment id = 0
3612 seg_hdr->component_id = cpu_to_le32(2);
3613 seg_hdr->segment_id = 0;
3615 seg_hdr->function_id = cpu_to_le16(bp->pdev->devfn);
3616 seg_hdr->length = cpu_to_le32(seg_len);
3617 seg_hdr->status = cpu_to_le32(status);
3618 seg_hdr->duration = cpu_to_le32(duration);
3619 seg_hdr->data_offset = cpu_to_le32(sizeof(*seg_hdr));
3620 seg_hdr->instance = cpu_to_le32(instance);
3624 bnxt_fill_coredump_record(struct bnxt *bp, struct bnxt_coredump_record *record,
3625 time64_t start, s16 start_utc, u16 total_segs,
3628 time64_t end = ktime_get_real_seconds();
3629 u32 os_ver_major = 0, os_ver_minor = 0;
3632 time64_to_tm(start, 0, &tm);
3633 memset(record, 0, sizeof(*record));
3634 memcpy(record->signature, "cOrE", 4);
3636 record->low_version = 0;
3637 record->high_version = 1;
3638 record->asic_state = 0;
3639 strlcpy(record->system_name, utsname()->nodename,
3640 sizeof(record->system_name));
3641 record->year = cpu_to_le16(tm.tm_year + 1900);
3642 record->month = cpu_to_le16(tm.tm_mon + 1);
3643 record->day = cpu_to_le16(tm.tm_mday);
3644 record->hour = cpu_to_le16(tm.tm_hour);
3645 record->minute = cpu_to_le16(tm.tm_min);
3646 record->second = cpu_to_le16(tm.tm_sec);
3647 record->utc_bias = cpu_to_le16(start_utc);
3648 strcpy(record->commandline, "ethtool -w");
3649 record->total_segments = cpu_to_le32(total_segs);
3651 sscanf(utsname()->release, "%u.%u", &os_ver_major, &os_ver_minor);
3652 record->os_ver_major = cpu_to_le32(os_ver_major);
3653 record->os_ver_minor = cpu_to_le32(os_ver_minor);
3655 strlcpy(record->os_name, utsname()->sysname, 32);
3656 time64_to_tm(end, 0, &tm);
3657 record->end_year = cpu_to_le16(tm.tm_year + 1900);
3658 record->end_month = cpu_to_le16(tm.tm_mon + 1);
3659 record->end_day = cpu_to_le16(tm.tm_mday);
3660 record->end_hour = cpu_to_le16(tm.tm_hour);
3661 record->end_minute = cpu_to_le16(tm.tm_min);
3662 record->end_second = cpu_to_le16(tm.tm_sec);
3663 record->end_utc_bias = cpu_to_le16(sys_tz.tz_minuteswest * 60);
3664 record->asic_id1 = cpu_to_le32(bp->chip_num << 16 |
3665 bp->ver_resp.chip_rev << 8 |
3666 bp->ver_resp.chip_metal);
3667 record->asic_id2 = 0;
3668 record->coredump_status = cpu_to_le32(status);
3669 record->ioctl_low_version = 0;
3670 record->ioctl_high_version = 0;
3673 static int bnxt_get_coredump(struct bnxt *bp, void *buf, u32 *dump_len)
3675 u32 ver_get_resp_len = sizeof(struct hwrm_ver_get_output);
3676 u32 offset = 0, seg_hdr_len, seg_record_len, buf_len = 0;
3677 struct coredump_segment_record *seg_record = NULL;
3678 struct bnxt_coredump_segment_hdr seg_hdr;
3679 struct bnxt_coredump coredump = {NULL};
3680 time64_t start_time;
3685 buf_len = *dump_len;
3687 start_time = ktime_get_real_seconds();
3688 start_utc = sys_tz.tz_minuteswest * 60;
3689 seg_hdr_len = sizeof(seg_hdr);
3691 /* First segment should be hwrm_ver_get response */
3692 *dump_len = seg_hdr_len + ver_get_resp_len;
3694 bnxt_fill_coredump_seg_hdr(bp, &seg_hdr, NULL, ver_get_resp_len,
3696 memcpy(buf + offset, &seg_hdr, seg_hdr_len);
3697 offset += seg_hdr_len;
3698 memcpy(buf + offset, &bp->ver_resp, ver_get_resp_len);
3699 offset += ver_get_resp_len;
3702 rc = bnxt_hwrm_dbg_coredump_list(bp, &coredump);
3704 netdev_err(bp->dev, "Failed to get coredump segment list\n");
3708 *dump_len += seg_hdr_len * coredump.total_segs;
3710 seg_record = (struct coredump_segment_record *)coredump.data;
3711 seg_record_len = sizeof(*seg_record);
3713 for (i = 0; i < coredump.total_segs; i++) {
3714 u16 comp_id = le16_to_cpu(seg_record->component_id);
3715 u16 seg_id = le16_to_cpu(seg_record->segment_id);
3716 u32 duration = 0, seg_len = 0;
3717 unsigned long start, end;
3719 if (buf && ((offset + seg_hdr_len) >
3720 BNXT_COREDUMP_BUF_LEN(buf_len))) {
3727 rc = bnxt_hwrm_dbg_coredump_initiate(bp, comp_id, seg_id);
3730 "Failed to initiate coredump for seg = %d\n",
3731 seg_record->segment_id);
3735 /* Write segment data into the buffer */
3736 rc = bnxt_hwrm_dbg_coredump_retrieve(bp, comp_id, seg_id,
3737 &seg_len, buf, buf_len,
3738 offset + seg_hdr_len);
3739 if (rc && rc == -ENOBUFS)
3743 "Failed to retrieve coredump for seg = %d\n",
3744 seg_record->segment_id);
3748 duration = jiffies_to_msecs(end - start);
3749 bnxt_fill_coredump_seg_hdr(bp, &seg_hdr, seg_record, seg_len,
3753 /* Write segment header into the buffer */
3754 memcpy(buf + offset, &seg_hdr, seg_hdr_len);
3755 offset += seg_hdr_len + seg_len;
3758 *dump_len += seg_len;
3760 (struct coredump_segment_record *)((u8 *)seg_record +
3766 bnxt_fill_coredump_record(bp, buf + offset, start_time,
3767 start_utc, coredump.total_segs + 1,
3769 kfree(coredump.data);
3770 *dump_len += sizeof(struct bnxt_coredump_record);
3772 netdev_err(bp->dev, "Firmware returned large coredump buffer\n");
3776 static int bnxt_set_dump(struct net_device *dev, struct ethtool_dump *dump)
3778 struct bnxt *bp = netdev_priv(dev);
3780 if (dump->flag > BNXT_DUMP_CRASH) {
3781 netdev_info(dev, "Supports only Live(0) and Crash(1) dumps.\n");
3785 if (!IS_ENABLED(CONFIG_TEE_BNXT_FW) && dump->flag == BNXT_DUMP_CRASH) {
3786 netdev_info(dev, "Cannot collect crash dump as TEE_BNXT_FW config option is not enabled.\n");
3790 bp->dump_flag = dump->flag;
3794 static int bnxt_get_dump_flag(struct net_device *dev, struct ethtool_dump *dump)
3796 struct bnxt *bp = netdev_priv(dev);
3798 if (bp->hwrm_spec_code < 0x10801)
3801 dump->version = bp->ver_resp.hwrm_fw_maj_8b << 24 |
3802 bp->ver_resp.hwrm_fw_min_8b << 16 |
3803 bp->ver_resp.hwrm_fw_bld_8b << 8 |
3804 bp->ver_resp.hwrm_fw_rsvd_8b;
3806 dump->flag = bp->dump_flag;
3807 if (bp->dump_flag == BNXT_DUMP_CRASH)
3808 dump->len = BNXT_CRASH_DUMP_LEN;
3810 bnxt_get_coredump(bp, NULL, &dump->len);
3814 static int bnxt_get_dump_data(struct net_device *dev, struct ethtool_dump *dump,
3817 struct bnxt *bp = netdev_priv(dev);
3819 if (bp->hwrm_spec_code < 0x10801)
3822 memset(buf, 0, dump->len);
3824 dump->flag = bp->dump_flag;
3825 if (dump->flag == BNXT_DUMP_CRASH) {
3826 #ifdef CONFIG_TEE_BNXT_FW
3827 return tee_bnxt_copy_coredump(buf, 0, dump->len);
3830 return bnxt_get_coredump(bp, buf, &dump->len);
3836 void bnxt_ethtool_init(struct bnxt *bp)
3838 struct hwrm_selftest_qlist_output *resp = bp->hwrm_cmd_resp_addr;
3839 struct hwrm_selftest_qlist_input req = {0};
3840 struct bnxt_test_info *test_info;
3841 struct net_device *dev = bp->dev;
3844 if (!(bp->fw_cap & BNXT_FW_CAP_PKG_VER))
3845 bnxt_get_pkgver(dev);
3848 if (bp->hwrm_spec_code < 0x10704 || !BNXT_PF(bp))
3851 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_SELFTEST_QLIST, -1, -1);
3852 mutex_lock(&bp->hwrm_cmd_lock);
3853 rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
3855 goto ethtool_init_exit;
3857 test_info = bp->test_info;
3859 test_info = kzalloc(sizeof(*bp->test_info), GFP_KERNEL);
3861 goto ethtool_init_exit;
3863 bp->test_info = test_info;
3864 bp->num_tests = resp->num_tests + BNXT_DRV_TESTS;
3865 if (bp->num_tests > BNXT_MAX_TEST)
3866 bp->num_tests = BNXT_MAX_TEST;
3868 test_info->offline_mask = resp->offline_tests;
3869 test_info->timeout = le16_to_cpu(resp->test_timeout);
3870 if (!test_info->timeout)
3871 test_info->timeout = HWRM_CMD_TIMEOUT;
3872 for (i = 0; i < bp->num_tests; i++) {
3873 char *str = test_info->string[i];
3874 char *fw_str = resp->test0_name + i * 32;
3876 if (i == BNXT_MACLPBK_TEST_IDX) {
3877 strcpy(str, "Mac loopback test (offline)");
3878 } else if (i == BNXT_PHYLPBK_TEST_IDX) {
3879 strcpy(str, "Phy loopback test (offline)");
3880 } else if (i == BNXT_EXTLPBK_TEST_IDX) {
3881 strcpy(str, "Ext loopback test (offline)");
3882 } else if (i == BNXT_IRQ_TEST_IDX) {
3883 strcpy(str, "Interrupt_test (offline)");
3885 strlcpy(str, fw_str, ETH_GSTRING_LEN);
3886 strncat(str, " test", ETH_GSTRING_LEN - strlen(str));
3887 if (test_info->offline_mask & (1 << i))
3888 strncat(str, " (offline)",
3889 ETH_GSTRING_LEN - strlen(str));
3891 strncat(str, " (online)",
3892 ETH_GSTRING_LEN - strlen(str));
3897 mutex_unlock(&bp->hwrm_cmd_lock);
3900 void bnxt_ethtool_free(struct bnxt *bp)
3902 kfree(bp->test_info);
3903 bp->test_info = NULL;
3906 const struct ethtool_ops bnxt_ethtool_ops = {
3907 .supported_coalesce_params = ETHTOOL_COALESCE_USECS |
3908 ETHTOOL_COALESCE_MAX_FRAMES |
3909 ETHTOOL_COALESCE_USECS_IRQ |
3910 ETHTOOL_COALESCE_MAX_FRAMES_IRQ |
3911 ETHTOOL_COALESCE_STATS_BLOCK_USECS |
3912 ETHTOOL_COALESCE_USE_ADAPTIVE_RX,
3913 .get_link_ksettings = bnxt_get_link_ksettings,
3914 .set_link_ksettings = bnxt_set_link_ksettings,
3915 .get_fecparam = bnxt_get_fecparam,
3916 .set_fecparam = bnxt_set_fecparam,
3917 .get_pause_stats = bnxt_get_pause_stats,
3918 .get_pauseparam = bnxt_get_pauseparam,
3919 .set_pauseparam = bnxt_set_pauseparam,
3920 .get_drvinfo = bnxt_get_drvinfo,
3921 .get_regs_len = bnxt_get_regs_len,
3922 .get_regs = bnxt_get_regs,
3923 .get_wol = bnxt_get_wol,
3924 .set_wol = bnxt_set_wol,
3925 .get_coalesce = bnxt_get_coalesce,
3926 .set_coalesce = bnxt_set_coalesce,
3927 .get_msglevel = bnxt_get_msglevel,
3928 .set_msglevel = bnxt_set_msglevel,
3929 .get_sset_count = bnxt_get_sset_count,
3930 .get_strings = bnxt_get_strings,
3931 .get_ethtool_stats = bnxt_get_ethtool_stats,
3932 .set_ringparam = bnxt_set_ringparam,
3933 .get_ringparam = bnxt_get_ringparam,
3934 .get_channels = bnxt_get_channels,
3935 .set_channels = bnxt_set_channels,
3936 .get_rxnfc = bnxt_get_rxnfc,
3937 .set_rxnfc = bnxt_set_rxnfc,
3938 .get_rxfh_indir_size = bnxt_get_rxfh_indir_size,
3939 .get_rxfh_key_size = bnxt_get_rxfh_key_size,
3940 .get_rxfh = bnxt_get_rxfh,
3941 .set_rxfh = bnxt_set_rxfh,
3942 .flash_device = bnxt_flash_device,
3943 .get_eeprom_len = bnxt_get_eeprom_len,
3944 .get_eeprom = bnxt_get_eeprom,
3945 .set_eeprom = bnxt_set_eeprom,
3946 .get_link = bnxt_get_link,
3947 .get_eee = bnxt_get_eee,
3948 .set_eee = bnxt_set_eee,
3949 .get_module_info = bnxt_get_module_info,
3950 .get_module_eeprom = bnxt_get_module_eeprom,
3951 .nway_reset = bnxt_nway_reset,
3952 .set_phys_id = bnxt_set_phys_id,
3953 .self_test = bnxt_self_test,
3954 .reset = bnxt_reset,
3955 .set_dump = bnxt_set_dump,
3956 .get_dump_flag = bnxt_get_dump_flag,
3957 .get_dump_data = bnxt_get_dump_data,