1 /* Broadcom NetXtreme-C/E network driver.
3 * Copyright (c) 2014-2016 Broadcom Corporation
4 * Copyright (c) 2016-2018 Broadcom Limited
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation.
14 #define DRV_MODULE_NAME "bnxt_en"
15 #define DRV_MODULE_VERSION "1.10.0"
18 #define DRV_VER_MIN 10
21 #include <linux/interrupt.h>
22 #include <linux/rhashtable.h>
23 #include <linux/crash_dump.h>
24 #include <net/devlink.h>
25 #include <net/dst_metadata.h>
27 #include <linux/dim.h>
32 __le32 tx_bd_len_flags_type;
33 #define TX_BD_TYPE (0x3f << 0)
34 #define TX_BD_TYPE_SHORT_TX_BD (0x00 << 0)
35 #define TX_BD_TYPE_LONG_TX_BD (0x10 << 0)
36 #define TX_BD_FLAGS_PACKET_END (1 << 6)
37 #define TX_BD_FLAGS_NO_CMPL (1 << 7)
38 #define TX_BD_FLAGS_BD_CNT (0x1f << 8)
39 #define TX_BD_FLAGS_BD_CNT_SHIFT 8
40 #define TX_BD_FLAGS_LHINT (3 << 13)
41 #define TX_BD_FLAGS_LHINT_SHIFT 13
42 #define TX_BD_FLAGS_LHINT_512_AND_SMALLER (0 << 13)
43 #define TX_BD_FLAGS_LHINT_512_TO_1023 (1 << 13)
44 #define TX_BD_FLAGS_LHINT_1024_TO_2047 (2 << 13)
45 #define TX_BD_FLAGS_LHINT_2048_AND_LARGER (3 << 13)
46 #define TX_BD_FLAGS_COAL_NOW (1 << 15)
47 #define TX_BD_LEN (0xffff << 16)
48 #define TX_BD_LEN_SHIFT 16
55 __le32 tx_bd_hsize_lflags;
56 #define TX_BD_FLAGS_TCP_UDP_CHKSUM (1 << 0)
57 #define TX_BD_FLAGS_IP_CKSUM (1 << 1)
58 #define TX_BD_FLAGS_NO_CRC (1 << 2)
59 #define TX_BD_FLAGS_STAMP (1 << 3)
60 #define TX_BD_FLAGS_T_IP_CHKSUM (1 << 4)
61 #define TX_BD_FLAGS_LSO (1 << 5)
62 #define TX_BD_FLAGS_IPID_FMT (1 << 6)
63 #define TX_BD_FLAGS_T_IPID (1 << 7)
64 #define TX_BD_HSIZE (0xff << 16)
65 #define TX_BD_HSIZE_SHIFT 16
68 __le32 tx_bd_cfa_action;
69 #define TX_BD_CFA_ACTION (0xffff << 16)
70 #define TX_BD_CFA_ACTION_SHIFT 16
72 __le32 tx_bd_cfa_meta;
73 #define TX_BD_CFA_META_MASK 0xfffffff
74 #define TX_BD_CFA_META_VID_MASK 0xfff
75 #define TX_BD_CFA_META_PRI_MASK (0xf << 12)
76 #define TX_BD_CFA_META_PRI_SHIFT 12
77 #define TX_BD_CFA_META_TPID_MASK (3 << 16)
78 #define TX_BD_CFA_META_TPID_SHIFT 16
79 #define TX_BD_CFA_META_KEY (0xf << 28)
80 #define TX_BD_CFA_META_KEY_SHIFT 28
81 #define TX_BD_CFA_META_KEY_VLAN (1 << 28)
85 __le32 rx_bd_len_flags_type;
86 #define RX_BD_TYPE (0x3f << 0)
87 #define RX_BD_TYPE_RX_PACKET_BD 0x4
88 #define RX_BD_TYPE_RX_BUFFER_BD 0x5
89 #define RX_BD_TYPE_RX_AGG_BD 0x6
90 #define RX_BD_TYPE_16B_BD_SIZE (0 << 4)
91 #define RX_BD_TYPE_32B_BD_SIZE (1 << 4)
92 #define RX_BD_TYPE_48B_BD_SIZE (2 << 4)
93 #define RX_BD_TYPE_64B_BD_SIZE (3 << 4)
94 #define RX_BD_FLAGS_SOP (1 << 6)
95 #define RX_BD_FLAGS_EOP (1 << 7)
96 #define RX_BD_FLAGS_BUFFERS (3 << 8)
97 #define RX_BD_FLAGS_1_BUFFER_PACKET (0 << 8)
98 #define RX_BD_FLAGS_2_BUFFER_PACKET (1 << 8)
99 #define RX_BD_FLAGS_3_BUFFER_PACKET (2 << 8)
100 #define RX_BD_FLAGS_4_BUFFER_PACKET (3 << 8)
101 #define RX_BD_LEN (0xffff << 16)
102 #define RX_BD_LEN_SHIFT 16
109 __le32 tx_cmp_flags_type;
110 #define CMP_TYPE (0x3f << 0)
111 #define CMP_TYPE_TX_L2_CMP 0
112 #define CMP_TYPE_RX_L2_CMP 17
113 #define CMP_TYPE_RX_AGG_CMP 18
114 #define CMP_TYPE_RX_L2_TPA_START_CMP 19
115 #define CMP_TYPE_RX_L2_TPA_END_CMP 21
116 #define CMP_TYPE_RX_TPA_AGG_CMP 22
117 #define CMP_TYPE_STATUS_CMP 32
118 #define CMP_TYPE_REMOTE_DRIVER_REQ 34
119 #define CMP_TYPE_REMOTE_DRIVER_RESP 36
120 #define CMP_TYPE_ERROR_STATUS 48
121 #define CMPL_BASE_TYPE_STAT_EJECT 0x1aUL
122 #define CMPL_BASE_TYPE_HWRM_DONE 0x20UL
123 #define CMPL_BASE_TYPE_HWRM_FWD_REQ 0x22UL
124 #define CMPL_BASE_TYPE_HWRM_FWD_RESP 0x24UL
125 #define CMPL_BASE_TYPE_HWRM_ASYNC_EVENT 0x2eUL
127 #define TX_CMP_FLAGS_ERROR (1 << 6)
128 #define TX_CMP_FLAGS_PUSH (1 << 7)
131 __le32 tx_cmp_errors_v;
132 #define TX_CMP_V (1 << 0)
133 #define TX_CMP_ERRORS_BUFFER_ERROR (7 << 1)
134 #define TX_CMP_ERRORS_BUFFER_ERROR_NO_ERROR 0
135 #define TX_CMP_ERRORS_BUFFER_ERROR_BAD_FORMAT 2
136 #define TX_CMP_ERRORS_BUFFER_ERROR_INVALID_STAG 4
137 #define TX_CMP_ERRORS_BUFFER_ERROR_STAG_BOUNDS 5
138 #define TX_CMP_ERRORS_ZERO_LENGTH_PKT (1 << 4)
139 #define TX_CMP_ERRORS_EXCESSIVE_BD_LEN (1 << 5)
140 #define TX_CMP_ERRORS_DMA_ERROR (1 << 6)
141 #define TX_CMP_ERRORS_HINT_TOO_SHORT (1 << 7)
143 __le32 tx_cmp_unsed_3;
147 __le32 rx_cmp_len_flags_type;
148 #define RX_CMP_CMP_TYPE (0x3f << 0)
149 #define RX_CMP_FLAGS_ERROR (1 << 6)
150 #define RX_CMP_FLAGS_PLACEMENT (7 << 7)
151 #define RX_CMP_FLAGS_RSS_VALID (1 << 10)
152 #define RX_CMP_FLAGS_UNUSED (1 << 11)
153 #define RX_CMP_FLAGS_ITYPES_SHIFT 12
154 #define RX_CMP_FLAGS_ITYPE_UNKNOWN (0 << 12)
155 #define RX_CMP_FLAGS_ITYPE_IP (1 << 12)
156 #define RX_CMP_FLAGS_ITYPE_TCP (2 << 12)
157 #define RX_CMP_FLAGS_ITYPE_UDP (3 << 12)
158 #define RX_CMP_FLAGS_ITYPE_FCOE (4 << 12)
159 #define RX_CMP_FLAGS_ITYPE_ROCE (5 << 12)
160 #define RX_CMP_FLAGS_ITYPE_PTP_WO_TS (8 << 12)
161 #define RX_CMP_FLAGS_ITYPE_PTP_W_TS (9 << 12)
162 #define RX_CMP_LEN (0xffff << 16)
163 #define RX_CMP_LEN_SHIFT 16
166 __le32 rx_cmp_misc_v1;
167 #define RX_CMP_V1 (1 << 0)
168 #define RX_CMP_AGG_BUFS (0x1f << 1)
169 #define RX_CMP_AGG_BUFS_SHIFT 1
170 #define RX_CMP_RSS_HASH_TYPE (0x7f << 9)
171 #define RX_CMP_RSS_HASH_TYPE_SHIFT 9
172 #define RX_CMP_PAYLOAD_OFFSET (0xff << 16)
173 #define RX_CMP_PAYLOAD_OFFSET_SHIFT 16
175 __le32 rx_cmp_rss_hash;
178 #define RX_CMP_HASH_VALID(rxcmp) \
179 ((rxcmp)->rx_cmp_len_flags_type & cpu_to_le32(RX_CMP_FLAGS_RSS_VALID))
181 #define RSS_PROFILE_ID_MASK 0x1f
183 #define RX_CMP_HASH_TYPE(rxcmp) \
184 (((le32_to_cpu((rxcmp)->rx_cmp_misc_v1) & RX_CMP_RSS_HASH_TYPE) >>\
185 RX_CMP_RSS_HASH_TYPE_SHIFT) & RSS_PROFILE_ID_MASK)
188 __le32 rx_cmp_flags2;
189 #define RX_CMP_FLAGS2_IP_CS_CALC 0x1
190 #define RX_CMP_FLAGS2_L4_CS_CALC (0x1 << 1)
191 #define RX_CMP_FLAGS2_T_IP_CS_CALC (0x1 << 2)
192 #define RX_CMP_FLAGS2_T_L4_CS_CALC (0x1 << 3)
193 #define RX_CMP_FLAGS2_META_FORMAT_VLAN (0x1 << 4)
194 __le32 rx_cmp_meta_data;
195 #define RX_CMP_FLAGS2_METADATA_TCI_MASK 0xffff
196 #define RX_CMP_FLAGS2_METADATA_VID_MASK 0xfff
197 #define RX_CMP_FLAGS2_METADATA_TPID_MASK 0xffff0000
198 #define RX_CMP_FLAGS2_METADATA_TPID_SFT 16
199 __le32 rx_cmp_cfa_code_errors_v2;
200 #define RX_CMP_V (1 << 0)
201 #define RX_CMPL_ERRORS_MASK (0x7fff << 1)
202 #define RX_CMPL_ERRORS_SFT 1
203 #define RX_CMPL_ERRORS_BUFFER_ERROR_MASK (0x7 << 1)
204 #define RX_CMPL_ERRORS_BUFFER_ERROR_NO_BUFFER (0x0 << 1)
205 #define RX_CMPL_ERRORS_BUFFER_ERROR_DID_NOT_FIT (0x1 << 1)
206 #define RX_CMPL_ERRORS_BUFFER_ERROR_NOT_ON_CHIP (0x2 << 1)
207 #define RX_CMPL_ERRORS_BUFFER_ERROR_BAD_FORMAT (0x3 << 1)
208 #define RX_CMPL_ERRORS_IP_CS_ERROR (0x1 << 4)
209 #define RX_CMPL_ERRORS_L4_CS_ERROR (0x1 << 5)
210 #define RX_CMPL_ERRORS_T_IP_CS_ERROR (0x1 << 6)
211 #define RX_CMPL_ERRORS_T_L4_CS_ERROR (0x1 << 7)
212 #define RX_CMPL_ERRORS_CRC_ERROR (0x1 << 8)
213 #define RX_CMPL_ERRORS_T_PKT_ERROR_MASK (0x7 << 9)
214 #define RX_CMPL_ERRORS_T_PKT_ERROR_NO_ERROR (0x0 << 9)
215 #define RX_CMPL_ERRORS_T_PKT_ERROR_T_L3_BAD_VERSION (0x1 << 9)
216 #define RX_CMPL_ERRORS_T_PKT_ERROR_T_L3_BAD_HDR_LEN (0x2 << 9)
217 #define RX_CMPL_ERRORS_T_PKT_ERROR_TUNNEL_TOTAL_ERROR (0x3 << 9)
218 #define RX_CMPL_ERRORS_T_PKT_ERROR_T_IP_TOTAL_ERROR (0x4 << 9)
219 #define RX_CMPL_ERRORS_T_PKT_ERROR_T_UDP_TOTAL_ERROR (0x5 << 9)
220 #define RX_CMPL_ERRORS_T_PKT_ERROR_T_L3_BAD_TTL (0x6 << 9)
221 #define RX_CMPL_ERRORS_PKT_ERROR_MASK (0xf << 12)
222 #define RX_CMPL_ERRORS_PKT_ERROR_NO_ERROR (0x0 << 12)
223 #define RX_CMPL_ERRORS_PKT_ERROR_L3_BAD_VERSION (0x1 << 12)
224 #define RX_CMPL_ERRORS_PKT_ERROR_L3_BAD_HDR_LEN (0x2 << 12)
225 #define RX_CMPL_ERRORS_PKT_ERROR_L3_BAD_TTL (0x3 << 12)
226 #define RX_CMPL_ERRORS_PKT_ERROR_IP_TOTAL_ERROR (0x4 << 12)
227 #define RX_CMPL_ERRORS_PKT_ERROR_UDP_TOTAL_ERROR (0x5 << 12)
228 #define RX_CMPL_ERRORS_PKT_ERROR_L4_BAD_HDR_LEN (0x6 << 12)
229 #define RX_CMPL_ERRORS_PKT_ERROR_L4_BAD_HDR_LEN_TOO_SMALL (0x7 << 12)
230 #define RX_CMPL_ERRORS_PKT_ERROR_L4_BAD_OPT_LEN (0x8 << 12)
232 #define RX_CMPL_CFA_CODE_MASK (0xffff << 16)
233 #define RX_CMPL_CFA_CODE_SFT 16
235 __le32 rx_cmp_unused3;
238 #define RX_CMP_L2_ERRORS \
239 cpu_to_le32(RX_CMPL_ERRORS_BUFFER_ERROR_MASK | RX_CMPL_ERRORS_CRC_ERROR)
241 #define RX_CMP_L4_CS_BITS \
242 (cpu_to_le32(RX_CMP_FLAGS2_L4_CS_CALC | RX_CMP_FLAGS2_T_L4_CS_CALC))
244 #define RX_CMP_L4_CS_ERR_BITS \
245 (cpu_to_le32(RX_CMPL_ERRORS_L4_CS_ERROR | RX_CMPL_ERRORS_T_L4_CS_ERROR))
247 #define RX_CMP_L4_CS_OK(rxcmp1) \
248 (((rxcmp1)->rx_cmp_flags2 & RX_CMP_L4_CS_BITS) && \
249 !((rxcmp1)->rx_cmp_cfa_code_errors_v2 & RX_CMP_L4_CS_ERR_BITS))
251 #define RX_CMP_ENCAP(rxcmp1) \
252 ((le32_to_cpu((rxcmp1)->rx_cmp_flags2) & \
253 RX_CMP_FLAGS2_T_L4_CS_CALC) >> 3)
255 #define RX_CMP_CFA_CODE(rxcmpl1) \
256 ((le32_to_cpu((rxcmpl1)->rx_cmp_cfa_code_errors_v2) & \
257 RX_CMPL_CFA_CODE_MASK) >> RX_CMPL_CFA_CODE_SFT)
260 __le32 rx_agg_cmp_len_flags_type;
261 #define RX_AGG_CMP_TYPE (0x3f << 0)
262 #define RX_AGG_CMP_LEN (0xffff << 16)
263 #define RX_AGG_CMP_LEN_SHIFT 16
264 u32 rx_agg_cmp_opaque;
266 #define RX_AGG_CMP_V (1 << 0)
267 #define RX_AGG_CMP_AGG_ID (0xffff << 16)
268 #define RX_AGG_CMP_AGG_ID_SHIFT 16
269 __le32 rx_agg_cmp_unused;
272 #define TPA_AGG_AGG_ID(rx_agg) \
273 ((le32_to_cpu((rx_agg)->rx_agg_cmp_v) & \
274 RX_AGG_CMP_AGG_ID) >> RX_AGG_CMP_AGG_ID_SHIFT)
276 struct rx_tpa_start_cmp {
277 __le32 rx_tpa_start_cmp_len_flags_type;
278 #define RX_TPA_START_CMP_TYPE (0x3f << 0)
279 #define RX_TPA_START_CMP_FLAGS (0x3ff << 6)
280 #define RX_TPA_START_CMP_FLAGS_SHIFT 6
281 #define RX_TPA_START_CMP_FLAGS_ERROR (0x1 << 6)
282 #define RX_TPA_START_CMP_FLAGS_PLACEMENT (0x7 << 7)
283 #define RX_TPA_START_CMP_FLAGS_PLACEMENT_SHIFT 7
284 #define RX_TPA_START_CMP_FLAGS_PLACEMENT_JUMBO (0x1 << 7)
285 #define RX_TPA_START_CMP_FLAGS_PLACEMENT_HDS (0x2 << 7)
286 #define RX_TPA_START_CMP_FLAGS_PLACEMENT_GRO_JUMBO (0x5 << 7)
287 #define RX_TPA_START_CMP_FLAGS_PLACEMENT_GRO_HDS (0x6 << 7)
288 #define RX_TPA_START_CMP_FLAGS_RSS_VALID (0x1 << 10)
289 #define RX_TPA_START_CMP_FLAGS_TIMESTAMP (0x1 << 11)
290 #define RX_TPA_START_CMP_FLAGS_ITYPES (0xf << 12)
291 #define RX_TPA_START_CMP_FLAGS_ITYPES_SHIFT 12
292 #define RX_TPA_START_CMP_FLAGS_ITYPE_TCP (0x2 << 12)
293 #define RX_TPA_START_CMP_LEN (0xffff << 16)
294 #define RX_TPA_START_CMP_LEN_SHIFT 16
296 u32 rx_tpa_start_cmp_opaque;
297 __le32 rx_tpa_start_cmp_misc_v1;
298 #define RX_TPA_START_CMP_V1 (0x1 << 0)
299 #define RX_TPA_START_CMP_RSS_HASH_TYPE (0x7f << 9)
300 #define RX_TPA_START_CMP_RSS_HASH_TYPE_SHIFT 9
301 #define RX_TPA_START_CMP_AGG_ID (0x7f << 25)
302 #define RX_TPA_START_CMP_AGG_ID_SHIFT 25
303 #define RX_TPA_START_CMP_AGG_ID_P5 (0xffff << 16)
304 #define RX_TPA_START_CMP_AGG_ID_SHIFT_P5 16
306 __le32 rx_tpa_start_cmp_rss_hash;
309 #define TPA_START_HASH_VALID(rx_tpa_start) \
310 ((rx_tpa_start)->rx_tpa_start_cmp_len_flags_type & \
311 cpu_to_le32(RX_TPA_START_CMP_FLAGS_RSS_VALID))
313 #define TPA_START_HASH_TYPE(rx_tpa_start) \
314 (((le32_to_cpu((rx_tpa_start)->rx_tpa_start_cmp_misc_v1) & \
315 RX_TPA_START_CMP_RSS_HASH_TYPE) >> \
316 RX_TPA_START_CMP_RSS_HASH_TYPE_SHIFT) & RSS_PROFILE_ID_MASK)
318 #define TPA_START_AGG_ID(rx_tpa_start) \
319 ((le32_to_cpu((rx_tpa_start)->rx_tpa_start_cmp_misc_v1) & \
320 RX_TPA_START_CMP_AGG_ID) >> RX_TPA_START_CMP_AGG_ID_SHIFT)
322 #define TPA_START_AGG_ID_P5(rx_tpa_start) \
323 ((le32_to_cpu((rx_tpa_start)->rx_tpa_start_cmp_misc_v1) & \
324 RX_TPA_START_CMP_AGG_ID_P5) >> RX_TPA_START_CMP_AGG_ID_SHIFT_P5)
326 #define TPA_START_ERROR(rx_tpa_start) \
327 ((rx_tpa_start)->rx_tpa_start_cmp_len_flags_type & \
328 cpu_to_le32(RX_TPA_START_CMP_FLAGS_ERROR))
330 struct rx_tpa_start_cmp_ext {
331 __le32 rx_tpa_start_cmp_flags2;
332 #define RX_TPA_START_CMP_FLAGS2_IP_CS_CALC (0x1 << 0)
333 #define RX_TPA_START_CMP_FLAGS2_L4_CS_CALC (0x1 << 1)
334 #define RX_TPA_START_CMP_FLAGS2_T_IP_CS_CALC (0x1 << 2)
335 #define RX_TPA_START_CMP_FLAGS2_T_L4_CS_CALC (0x1 << 3)
336 #define RX_TPA_START_CMP_FLAGS2_IP_TYPE (0x1 << 8)
337 #define RX_TPA_START_CMP_FLAGS2_CSUM_CMPL_VALID (0x1 << 9)
338 #define RX_TPA_START_CMP_FLAGS2_EXT_META_FORMAT (0x3 << 10)
339 #define RX_TPA_START_CMP_FLAGS2_EXT_META_FORMAT_SHIFT 10
340 #define RX_TPA_START_CMP_FLAGS2_CSUM_CMPL (0xffff << 16)
341 #define RX_TPA_START_CMP_FLAGS2_CSUM_CMPL_SHIFT 16
343 __le32 rx_tpa_start_cmp_metadata;
344 __le32 rx_tpa_start_cmp_cfa_code_v2;
345 #define RX_TPA_START_CMP_V2 (0x1 << 0)
346 #define RX_TPA_START_CMP_ERRORS_BUFFER_ERROR_MASK (0x7 << 1)
347 #define RX_TPA_START_CMP_ERRORS_BUFFER_ERROR_SHIFT 1
348 #define RX_TPA_START_CMP_ERRORS_BUFFER_ERROR_NO_BUFFER (0x0 << 1)
349 #define RX_TPA_START_CMP_ERRORS_BUFFER_ERROR_BAD_FORMAT (0x3 << 1)
350 #define RX_TPA_START_CMP_ERRORS_BUFFER_ERROR_FLUSH (0x5 << 1)
351 #define RX_TPA_START_CMP_CFA_CODE (0xffff << 16)
352 #define RX_TPA_START_CMPL_CFA_CODE_SHIFT 16
353 __le32 rx_tpa_start_cmp_hdr_info;
356 #define TPA_START_CFA_CODE(rx_tpa_start) \
357 ((le32_to_cpu((rx_tpa_start)->rx_tpa_start_cmp_cfa_code_v2) & \
358 RX_TPA_START_CMP_CFA_CODE) >> RX_TPA_START_CMPL_CFA_CODE_SHIFT)
360 #define TPA_START_IS_IPV6(rx_tpa_start) \
361 (!!((rx_tpa_start)->rx_tpa_start_cmp_flags2 & \
362 cpu_to_le32(RX_TPA_START_CMP_FLAGS2_IP_TYPE)))
364 #define TPA_START_ERROR_CODE(rx_tpa_start) \
365 ((le32_to_cpu((rx_tpa_start)->rx_tpa_start_cmp_cfa_code_v2) & \
366 RX_TPA_START_CMP_ERRORS_BUFFER_ERROR_MASK) >> \
367 RX_TPA_START_CMP_ERRORS_BUFFER_ERROR_SHIFT)
369 struct rx_tpa_end_cmp {
370 __le32 rx_tpa_end_cmp_len_flags_type;
371 #define RX_TPA_END_CMP_TYPE (0x3f << 0)
372 #define RX_TPA_END_CMP_FLAGS (0x3ff << 6)
373 #define RX_TPA_END_CMP_FLAGS_SHIFT 6
374 #define RX_TPA_END_CMP_FLAGS_PLACEMENT (0x7 << 7)
375 #define RX_TPA_END_CMP_FLAGS_PLACEMENT_SHIFT 7
376 #define RX_TPA_END_CMP_FLAGS_PLACEMENT_JUMBO (0x1 << 7)
377 #define RX_TPA_END_CMP_FLAGS_PLACEMENT_HDS (0x2 << 7)
378 #define RX_TPA_END_CMP_FLAGS_PLACEMENT_GRO_JUMBO (0x5 << 7)
379 #define RX_TPA_END_CMP_FLAGS_PLACEMENT_GRO_HDS (0x6 << 7)
380 #define RX_TPA_END_CMP_FLAGS_RSS_VALID (0x1 << 10)
381 #define RX_TPA_END_CMP_FLAGS_ITYPES (0xf << 12)
382 #define RX_TPA_END_CMP_FLAGS_ITYPES_SHIFT 12
383 #define RX_TPA_END_CMP_FLAGS_ITYPE_TCP (0x2 << 12)
384 #define RX_TPA_END_CMP_LEN (0xffff << 16)
385 #define RX_TPA_END_CMP_LEN_SHIFT 16
387 u32 rx_tpa_end_cmp_opaque;
388 __le32 rx_tpa_end_cmp_misc_v1;
389 #define RX_TPA_END_CMP_V1 (0x1 << 0)
390 #define RX_TPA_END_CMP_AGG_BUFS (0x3f << 1)
391 #define RX_TPA_END_CMP_AGG_BUFS_SHIFT 1
392 #define RX_TPA_END_CMP_TPA_SEGS (0xff << 8)
393 #define RX_TPA_END_CMP_TPA_SEGS_SHIFT 8
394 #define RX_TPA_END_CMP_PAYLOAD_OFFSET (0xff << 16)
395 #define RX_TPA_END_CMP_PAYLOAD_OFFSET_SHIFT 16
396 #define RX_TPA_END_CMP_AGG_ID (0x7f << 25)
397 #define RX_TPA_END_CMP_AGG_ID_SHIFT 25
398 #define RX_TPA_END_CMP_AGG_ID_P5 (0xffff << 16)
399 #define RX_TPA_END_CMP_AGG_ID_SHIFT_P5 16
401 __le32 rx_tpa_end_cmp_tsdelta;
402 #define RX_TPA_END_GRO_TS (0x1 << 31)
405 #define TPA_END_AGG_ID(rx_tpa_end) \
406 ((le32_to_cpu((rx_tpa_end)->rx_tpa_end_cmp_misc_v1) & \
407 RX_TPA_END_CMP_AGG_ID) >> RX_TPA_END_CMP_AGG_ID_SHIFT)
409 #define TPA_END_AGG_ID_P5(rx_tpa_end) \
410 ((le32_to_cpu((rx_tpa_end)->rx_tpa_end_cmp_misc_v1) & \
411 RX_TPA_END_CMP_AGG_ID_P5) >> RX_TPA_END_CMP_AGG_ID_SHIFT_P5)
413 #define TPA_END_PAYLOAD_OFF(rx_tpa_end) \
414 ((le32_to_cpu((rx_tpa_end)->rx_tpa_end_cmp_misc_v1) & \
415 RX_TPA_END_CMP_PAYLOAD_OFFSET) >> RX_TPA_END_CMP_PAYLOAD_OFFSET_SHIFT)
417 #define TPA_END_AGG_BUFS(rx_tpa_end) \
418 ((le32_to_cpu((rx_tpa_end)->rx_tpa_end_cmp_misc_v1) & \
419 RX_TPA_END_CMP_AGG_BUFS) >> RX_TPA_END_CMP_AGG_BUFS_SHIFT)
421 #define TPA_END_TPA_SEGS(rx_tpa_end) \
422 ((le32_to_cpu((rx_tpa_end)->rx_tpa_end_cmp_misc_v1) & \
423 RX_TPA_END_CMP_TPA_SEGS) >> RX_TPA_END_CMP_TPA_SEGS_SHIFT)
425 #define RX_TPA_END_CMP_FLAGS_PLACEMENT_ANY_GRO \
426 cpu_to_le32(RX_TPA_END_CMP_FLAGS_PLACEMENT_GRO_JUMBO & \
427 RX_TPA_END_CMP_FLAGS_PLACEMENT_GRO_HDS)
429 #define TPA_END_GRO(rx_tpa_end) \
430 ((rx_tpa_end)->rx_tpa_end_cmp_len_flags_type & \
431 RX_TPA_END_CMP_FLAGS_PLACEMENT_ANY_GRO)
433 #define TPA_END_GRO_TS(rx_tpa_end) \
434 (!!((rx_tpa_end)->rx_tpa_end_cmp_tsdelta & \
435 cpu_to_le32(RX_TPA_END_GRO_TS)))
437 struct rx_tpa_end_cmp_ext {
438 __le32 rx_tpa_end_cmp_dup_acks;
439 #define RX_TPA_END_CMP_TPA_DUP_ACKS (0xf << 0)
440 #define RX_TPA_END_CMP_PAYLOAD_OFFSET_P5 (0xff << 16)
441 #define RX_TPA_END_CMP_PAYLOAD_OFFSET_SHIFT_P5 16
442 #define RX_TPA_END_CMP_AGG_BUFS_P5 (0xff << 24)
443 #define RX_TPA_END_CMP_AGG_BUFS_SHIFT_P5 24
445 __le32 rx_tpa_end_cmp_seg_len;
446 #define RX_TPA_END_CMP_TPA_SEG_LEN (0xffff << 0)
448 __le32 rx_tpa_end_cmp_errors_v2;
449 #define RX_TPA_END_CMP_V2 (0x1 << 0)
450 #define RX_TPA_END_CMP_ERRORS (0x3 << 1)
451 #define RX_TPA_END_CMP_ERRORS_P5 (0x7 << 1)
452 #define RX_TPA_END_CMPL_ERRORS_SHIFT 1
453 #define RX_TPA_END_CMP_ERRORS_BUFFER_ERROR_NO_BUFFER (0x0 << 1)
454 #define RX_TPA_END_CMP_ERRORS_BUFFER_ERROR_NOT_ON_CHIP (0x2 << 1)
455 #define RX_TPA_END_CMP_ERRORS_BUFFER_ERROR_BAD_FORMAT (0x3 << 1)
456 #define RX_TPA_END_CMP_ERRORS_BUFFER_ERROR_RSV_ERROR (0x4 << 1)
457 #define RX_TPA_END_CMP_ERRORS_BUFFER_ERROR_FLUSH (0x5 << 1)
459 u32 rx_tpa_end_cmp_start_opaque;
462 #define TPA_END_ERRORS(rx_tpa_end_ext) \
463 ((rx_tpa_end_ext)->rx_tpa_end_cmp_errors_v2 & \
464 cpu_to_le32(RX_TPA_END_CMP_ERRORS))
466 #define TPA_END_PAYLOAD_OFF_P5(rx_tpa_end_ext) \
467 ((le32_to_cpu((rx_tpa_end_ext)->rx_tpa_end_cmp_dup_acks) & \
468 RX_TPA_END_CMP_PAYLOAD_OFFSET_P5) >> \
469 RX_TPA_END_CMP_PAYLOAD_OFFSET_SHIFT_P5)
471 #define TPA_END_AGG_BUFS_P5(rx_tpa_end_ext) \
472 ((le32_to_cpu((rx_tpa_end_ext)->rx_tpa_end_cmp_dup_acks) & \
473 RX_TPA_END_CMP_AGG_BUFS_P5) >> RX_TPA_END_CMP_AGG_BUFS_SHIFT_P5)
475 #define EVENT_DATA1_RECOVERY_MASTER_FUNC(data1) \
477 ASYNC_EVENT_CMPL_ERROR_RECOVERY_EVENT_DATA1_FLAGS_MASTER_FUNC)
479 #define EVENT_DATA1_RECOVERY_ENABLED(data1) \
481 ASYNC_EVENT_CMPL_ERROR_RECOVERY_EVENT_DATA1_FLAGS_RECOVERY_ENABLED)
485 #define NQ_CN_TYPE_MASK 0x3fUL
486 #define NQ_CN_TYPE_SFT 0
487 #define NQ_CN_TYPE_CQ_NOTIFICATION 0x30UL
488 #define NQ_CN_TYPE_LAST NQ_CN_TYPE_CQ_NOTIFICATION
490 __le32 cq_handle_low;
492 #define NQ_CN_V 0x1UL
493 __le32 cq_handle_high;
496 #define DB_IDX_MASK 0xffffff
497 #define DB_IDX_VALID (0x1 << 26)
498 #define DB_IRQ_DIS (0x1 << 27)
499 #define DB_KEY_TX (0x0 << 28)
500 #define DB_KEY_RX (0x1 << 28)
501 #define DB_KEY_CP (0x2 << 28)
502 #define DB_KEY_ST (0x3 << 28)
503 #define DB_KEY_TX_PUSH (0x4 << 28)
504 #define DB_LONG_TX_PUSH (0x2 << 24)
506 #define BNXT_MIN_ROCE_CP_RINGS 2
507 #define BNXT_MIN_ROCE_STAT_CTXS 1
509 /* 64-bit doorbell */
510 #define DBR_INDEX_MASK 0x0000000000ffffffULL
511 #define DBR_XID_MASK 0x000fffff00000000ULL
512 #define DBR_XID_SFT 32
513 #define DBR_PATH_L2 (0x1ULL << 56)
514 #define DBR_TYPE_SQ (0x0ULL << 60)
515 #define DBR_TYPE_RQ (0x1ULL << 60)
516 #define DBR_TYPE_SRQ (0x2ULL << 60)
517 #define DBR_TYPE_SRQ_ARM (0x3ULL << 60)
518 #define DBR_TYPE_CQ (0x4ULL << 60)
519 #define DBR_TYPE_CQ_ARMSE (0x5ULL << 60)
520 #define DBR_TYPE_CQ_ARMALL (0x6ULL << 60)
521 #define DBR_TYPE_CQ_ARMENA (0x7ULL << 60)
522 #define DBR_TYPE_SRQ_ARMENA (0x8ULL << 60)
523 #define DBR_TYPE_CQ_CUTOFF_ACK (0x9ULL << 60)
524 #define DBR_TYPE_NQ (0xaULL << 60)
525 #define DBR_TYPE_NQ_ARM (0xbULL << 60)
526 #define DBR_TYPE_NULL (0xfULL << 60)
528 #define INVALID_HW_RING_ID ((u16)-1)
530 /* The hardware supports certain page sizes. Use the supported page sizes
531 * to allocate the rings.
533 #if (PAGE_SHIFT < 12)
534 #define BNXT_PAGE_SHIFT 12
535 #elif (PAGE_SHIFT <= 13)
536 #define BNXT_PAGE_SHIFT PAGE_SHIFT
537 #elif (PAGE_SHIFT < 16)
538 #define BNXT_PAGE_SHIFT 13
540 #define BNXT_PAGE_SHIFT 16
543 #define BNXT_PAGE_SIZE (1 << BNXT_PAGE_SHIFT)
545 /* The RXBD length is 16-bit so we can only support page sizes < 64K */
546 #if (PAGE_SHIFT > 15)
547 #define BNXT_RX_PAGE_SHIFT 15
549 #define BNXT_RX_PAGE_SHIFT PAGE_SHIFT
552 #define BNXT_RX_PAGE_SIZE (1 << BNXT_RX_PAGE_SHIFT)
554 #define BNXT_MAX_MTU 9500
555 #define BNXT_MAX_PAGE_MODE_MTU \
556 ((unsigned int)PAGE_SIZE - VLAN_ETH_HLEN - NET_IP_ALIGN - \
559 #define BNXT_MIN_PKT_SIZE 52
561 #define BNXT_DEFAULT_RX_RING_SIZE 511
562 #define BNXT_DEFAULT_TX_RING_SIZE 511
565 #define MAX_TPA_P5 256
566 #define MAX_TPA_P5_MASK (MAX_TPA_P5 - 1)
567 #define MAX_TPA_SEGS_P5 0x3f
569 #if (BNXT_PAGE_SHIFT == 16)
570 #define MAX_RX_PAGES 1
571 #define MAX_RX_AGG_PAGES 4
572 #define MAX_TX_PAGES 1
573 #define MAX_CP_PAGES 8
575 #define MAX_RX_PAGES 8
576 #define MAX_RX_AGG_PAGES 32
577 #define MAX_TX_PAGES 8
578 #define MAX_CP_PAGES 64
581 #define RX_DESC_CNT (BNXT_PAGE_SIZE / sizeof(struct rx_bd))
582 #define TX_DESC_CNT (BNXT_PAGE_SIZE / sizeof(struct tx_bd))
583 #define CP_DESC_CNT (BNXT_PAGE_SIZE / sizeof(struct tx_cmp))
585 #define SW_RXBD_RING_SIZE (sizeof(struct bnxt_sw_rx_bd) * RX_DESC_CNT)
586 #define HW_RXBD_RING_SIZE (sizeof(struct rx_bd) * RX_DESC_CNT)
588 #define SW_RXBD_AGG_RING_SIZE (sizeof(struct bnxt_sw_rx_agg_bd) * RX_DESC_CNT)
590 #define SW_TXBD_RING_SIZE (sizeof(struct bnxt_sw_tx_bd) * TX_DESC_CNT)
591 #define HW_TXBD_RING_SIZE (sizeof(struct tx_bd) * TX_DESC_CNT)
593 #define HW_CMPD_RING_SIZE (sizeof(struct tx_cmp) * CP_DESC_CNT)
595 #define BNXT_MAX_RX_DESC_CNT (RX_DESC_CNT * MAX_RX_PAGES - 1)
596 #define BNXT_MAX_RX_JUM_DESC_CNT (RX_DESC_CNT * MAX_RX_AGG_PAGES - 1)
597 #define BNXT_MAX_TX_DESC_CNT (TX_DESC_CNT * MAX_TX_PAGES - 1)
599 #define RX_RING(x) (((x) & ~(RX_DESC_CNT - 1)) >> (BNXT_PAGE_SHIFT - 4))
600 #define RX_IDX(x) ((x) & (RX_DESC_CNT - 1))
602 #define TX_RING(x) (((x) & ~(TX_DESC_CNT - 1)) >> (BNXT_PAGE_SHIFT - 4))
603 #define TX_IDX(x) ((x) & (TX_DESC_CNT - 1))
605 #define CP_RING(x) (((x) & ~(CP_DESC_CNT - 1)) >> (BNXT_PAGE_SHIFT - 4))
606 #define CP_IDX(x) ((x) & (CP_DESC_CNT - 1))
608 #define TX_CMP_VALID(txcmp, raw_cons) \
609 (!!((txcmp)->tx_cmp_errors_v & cpu_to_le32(TX_CMP_V)) == \
610 !((raw_cons) & bp->cp_bit))
612 #define RX_CMP_VALID(rxcmp1, raw_cons) \
613 (!!((rxcmp1)->rx_cmp_cfa_code_errors_v2 & cpu_to_le32(RX_CMP_V)) ==\
614 !((raw_cons) & bp->cp_bit))
616 #define RX_AGG_CMP_VALID(agg, raw_cons) \
617 (!!((agg)->rx_agg_cmp_v & cpu_to_le32(RX_AGG_CMP_V)) == \
618 !((raw_cons) & bp->cp_bit))
620 #define NQ_CMP_VALID(nqcmp, raw_cons) \
621 (!!((nqcmp)->v & cpu_to_le32(NQ_CN_V)) == !((raw_cons) & bp->cp_bit))
623 #define TX_CMP_TYPE(txcmp) \
624 (le32_to_cpu((txcmp)->tx_cmp_flags_type) & CMP_TYPE)
626 #define RX_CMP_TYPE(rxcmp) \
627 (le32_to_cpu((rxcmp)->rx_cmp_len_flags_type) & RX_CMP_CMP_TYPE)
629 #define NEXT_RX(idx) (((idx) + 1) & bp->rx_ring_mask)
631 #define NEXT_RX_AGG(idx) (((idx) + 1) & bp->rx_agg_ring_mask)
633 #define NEXT_TX(idx) (((idx) + 1) & bp->tx_ring_mask)
635 #define ADV_RAW_CMP(idx, n) ((idx) + (n))
636 #define NEXT_RAW_CMP(idx) ADV_RAW_CMP(idx, 1)
637 #define RING_CMP(idx) ((idx) & bp->cp_ring_mask)
638 #define NEXT_CMP(idx) RING_CMP(ADV_RAW_CMP(idx, 1))
640 #define BNXT_HWRM_MAX_REQ_LEN (bp->hwrm_max_req_len)
641 #define BNXT_HWRM_SHORT_REQ_LEN sizeof(struct hwrm_short_input)
642 #define DFLT_HWRM_CMD_TIMEOUT 500
643 #define HWRM_CMD_TIMEOUT (bp->hwrm_cmd_timeout)
644 #define HWRM_RESET_TIMEOUT ((HWRM_CMD_TIMEOUT) * 4)
645 #define HWRM_RESP_ERR_CODE_MASK 0xffff
646 #define HWRM_RESP_LEN_OFFSET 4
647 #define HWRM_RESP_LEN_MASK 0xffff0000
648 #define HWRM_RESP_LEN_SFT 16
649 #define HWRM_RESP_VALID_MASK 0xff000000
650 #define BNXT_HWRM_REQ_MAX_SIZE 128
651 #define BNXT_HWRM_REQS_PER_PAGE (BNXT_PAGE_SIZE / \
652 BNXT_HWRM_REQ_MAX_SIZE)
653 #define HWRM_SHORT_MIN_TIMEOUT 3
654 #define HWRM_SHORT_MAX_TIMEOUT 10
655 #define HWRM_SHORT_TIMEOUT_COUNTER 5
657 #define HWRM_MIN_TIMEOUT 25
658 #define HWRM_MAX_TIMEOUT 40
660 #define HWRM_TOTAL_TIMEOUT(n) (((n) <= HWRM_SHORT_TIMEOUT_COUNTER) ? \
661 ((n) * HWRM_SHORT_MIN_TIMEOUT) : \
662 (HWRM_SHORT_TIMEOUT_COUNTER * HWRM_SHORT_MIN_TIMEOUT + \
663 ((n) - HWRM_SHORT_TIMEOUT_COUNTER) * HWRM_MIN_TIMEOUT))
665 #define HWRM_VALID_BIT_DELAY_USEC 150
667 #define BNXT_HWRM_CHNL_CHIMP 0
668 #define BNXT_HWRM_CHNL_KONG 1
670 #define BNXT_RX_EVENT 1
671 #define BNXT_AGG_EVENT 2
672 #define BNXT_TX_EVENT 4
673 #define BNXT_REDIRECT_EVENT 8
675 struct bnxt_sw_tx_bd {
678 struct xdp_frame *xdpf;
680 DEFINE_DMA_UNMAP_ADDR(mapping);
681 DEFINE_DMA_UNMAP_LEN(len);
686 unsigned short nr_frags;
691 struct bnxt_sw_rx_bd {
697 struct bnxt_sw_rx_agg_bd {
703 struct bnxt_ring_mem_info {
707 #define BNXT_RMEM_VALID_PTE_FLAG 1
708 #define BNXT_RMEM_RING_PTE_FLAG 2
709 #define BNXT_RMEM_USE_FULL_PAGE_FLAG 4
717 dma_addr_t pg_tbl_map;
723 struct bnxt_ring_struct {
724 struct bnxt_ring_mem_info ring_mem;
726 u16 fw_ring_id; /* Ring id filled by Chimp FW */
729 u16 map_idx; /* Used by cmpl rings */
737 __le32 tx_bd_len_flags_type;
739 struct tx_bd_ext txbd2;
742 struct tx_push_buffer {
743 struct tx_push_bd push_bd;
747 struct bnxt_db_info {
748 void __iomem *doorbell;
755 struct bnxt_tx_ring_info {
756 struct bnxt_napi *bnapi;
760 struct bnxt_db_info tx_db;
762 struct tx_bd *tx_desc_ring[MAX_TX_PAGES];
763 struct bnxt_sw_tx_bd *tx_buf_ring;
765 dma_addr_t tx_desc_mapping[MAX_TX_PAGES];
767 struct tx_push_buffer *tx_push;
768 dma_addr_t tx_push_mapping;
771 #define BNXT_DEV_STATE_CLOSING 0x1
774 struct bnxt_ring_struct tx_ring_struct;
777 #define BNXT_LEGACY_COAL_CMPL_PARAMS \
778 (RING_AGGINT_QCAPS_RESP_CMPL_PARAMS_INT_LAT_TMR_MIN | \
779 RING_AGGINT_QCAPS_RESP_CMPL_PARAMS_INT_LAT_TMR_MAX | \
780 RING_AGGINT_QCAPS_RESP_CMPL_PARAMS_TIMER_RESET | \
781 RING_AGGINT_QCAPS_RESP_CMPL_PARAMS_RING_IDLE | \
782 RING_AGGINT_QCAPS_RESP_CMPL_PARAMS_NUM_CMPL_DMA_AGGR | \
783 RING_AGGINT_QCAPS_RESP_CMPL_PARAMS_NUM_CMPL_DMA_AGGR_DURING_INT | \
784 RING_AGGINT_QCAPS_RESP_CMPL_PARAMS_CMPL_AGGR_DMA_TMR | \
785 RING_AGGINT_QCAPS_RESP_CMPL_PARAMS_CMPL_AGGR_DMA_TMR_DURING_INT | \
786 RING_AGGINT_QCAPS_RESP_CMPL_PARAMS_NUM_CMPL_AGGR_INT)
788 #define BNXT_COAL_CMPL_ENABLES \
789 (RING_CMPL_RING_CFG_AGGINT_PARAMS_REQ_ENABLES_NUM_CMPL_DMA_AGGR | \
790 RING_CMPL_RING_CFG_AGGINT_PARAMS_REQ_ENABLES_CMPL_AGGR_DMA_TMR | \
791 RING_CMPL_RING_CFG_AGGINT_PARAMS_REQ_ENABLES_INT_LAT_TMR_MAX | \
792 RING_CMPL_RING_CFG_AGGINT_PARAMS_REQ_ENABLES_NUM_CMPL_AGGR_INT)
794 #define BNXT_COAL_CMPL_MIN_TMR_ENABLE \
795 RING_CMPL_RING_CFG_AGGINT_PARAMS_REQ_ENABLES_INT_LAT_TMR_MIN
797 #define BNXT_COAL_CMPL_AGGR_TMR_DURING_INT_ENABLE \
798 RING_CMPL_RING_CFG_AGGINT_PARAMS_REQ_ENABLES_NUM_CMPL_DMA_AGGR_DURING_INT
800 struct bnxt_coal_cap {
803 u16 num_cmpl_dma_aggr_max;
804 u16 num_cmpl_dma_aggr_during_int_max;
805 u16 cmpl_aggr_dma_tmr_max;
806 u16 cmpl_aggr_dma_tmr_during_int_max;
807 u16 int_lat_tmr_min_max;
808 u16 int_lat_tmr_max_max;
809 u16 num_cmpl_aggr_int_max;
818 /* RING_IDLE enabled when coal ticks < idle_thresh */
824 struct bnxt_tpa_info {
829 unsigned short gso_type;
832 enum pkt_hash_types hash_type;
836 #define BNXT_TPA_L4_SIZE(hdr_info) \
837 (((hdr_info) & 0xf8000000) ? ((hdr_info) >> 27) : 32)
839 #define BNXT_TPA_INNER_L3_OFF(hdr_info) \
840 (((hdr_info) >> 18) & 0x1ff)
842 #define BNXT_TPA_INNER_L2_OFF(hdr_info) \
843 (((hdr_info) >> 9) & 0x1ff)
845 #define BNXT_TPA_OUTER_L3_OFF(hdr_info) \
848 u16 cfa_code; /* cfa_code in TPA start compl */
850 struct rx_agg_cmp *agg_arr;
853 #define BNXT_AGG_IDX_BMAP_SIZE (MAX_TPA_P5 / BITS_PER_LONG)
855 struct bnxt_tpa_idx_map {
856 u16 agg_id_tbl[1024];
857 unsigned long agg_idx_bmap[BNXT_AGG_IDX_BMAP_SIZE];
860 struct bnxt_rx_ring_info {
861 struct bnxt_napi *bnapi;
866 struct bnxt_db_info rx_db;
867 struct bnxt_db_info rx_agg_db;
869 struct bpf_prog *xdp_prog;
871 struct rx_bd *rx_desc_ring[MAX_RX_PAGES];
872 struct bnxt_sw_rx_bd *rx_buf_ring;
874 struct rx_bd *rx_agg_desc_ring[MAX_RX_AGG_PAGES];
875 struct bnxt_sw_rx_agg_bd *rx_agg_ring;
877 unsigned long *rx_agg_bmap;
878 u16 rx_agg_bmap_size;
880 struct page *rx_page;
881 unsigned int rx_page_offset;
883 dma_addr_t rx_desc_mapping[MAX_RX_PAGES];
884 dma_addr_t rx_agg_desc_mapping[MAX_RX_AGG_PAGES];
886 struct bnxt_tpa_info *rx_tpa;
887 struct bnxt_tpa_idx_map *rx_tpa_idx_map;
889 struct bnxt_ring_struct rx_ring_struct;
890 struct bnxt_ring_struct rx_agg_ring_struct;
891 struct xdp_rxq_info xdp_rxq;
892 struct page_pool *page_pool;
895 struct bnxt_cp_ring_info {
896 struct bnxt_napi *bnapi;
898 struct bnxt_db_info cp_db;
903 u32 last_cp_raw_cons;
905 struct bnxt_coal rx_ring_coal;
913 struct tx_cmp *cp_desc_ring[MAX_CP_PAGES];
914 struct nqe_cn *nq_desc_ring[MAX_CP_PAGES];
917 dma_addr_t cp_desc_mapping[MAX_CP_PAGES];
919 struct ctx_hw_stats *hw_stats;
920 dma_addr_t hw_stats_map;
922 u64 rx_l4_csum_errors;
925 struct bnxt_ring_struct cp_ring_struct;
927 struct bnxt_cp_ring_info *cp_ring_arr[2];
928 #define BNXT_RX_HDL 0
929 #define BNXT_TX_HDL 1
933 struct napi_struct napi;
937 struct bnxt_cp_ring_info cp_ring;
938 struct bnxt_rx_ring_info *rx_ring;
939 struct bnxt_tx_ring_info *tx_ring;
941 void (*tx_int)(struct bnxt *, struct bnxt_napi *,
947 #define BNXT_NAPI_FLAG_XDP 0x1
953 irq_handler_t handler;
957 char name[IFNAMSIZ + 2];
958 cpumask_var_t cpu_mask;
961 #define HWRM_RING_ALLOC_TX 0x1
962 #define HWRM_RING_ALLOC_RX 0x2
963 #define HWRM_RING_ALLOC_AGG 0x4
964 #define HWRM_RING_ALLOC_CMPL 0x8
965 #define HWRM_RING_ALLOC_NQ 0x10
967 #define INVALID_STATS_CTX_ID -1
969 struct bnxt_ring_grp_info {
977 struct bnxt_vnic_info {
978 u16 fw_vnic_id; /* returned by Chimp during alloc */
979 #define BNXT_MAX_CTX_PER_VNIC 8
980 u16 fw_rss_cos_lb_ctx[BNXT_MAX_CTX_PER_VNIC];
982 #define BNXT_MAX_UC_ADDRS 4
983 __le64 fw_l2_filter_id[BNXT_MAX_UC_ADDRS];
984 /* index 0 always dev_addr */
989 dma_addr_t rss_table_dma_addr;
991 dma_addr_t rss_hash_key_dma_addr;
998 dma_addr_t mc_list_mapping;
999 #define BNXT_MAX_MC_ADDRS 16
1002 #define BNXT_VNIC_RSS_FLAG 1
1003 #define BNXT_VNIC_RFS_FLAG 2
1004 #define BNXT_VNIC_MCAST_FLAG 4
1005 #define BNXT_VNIC_UCAST_FLAG 8
1006 #define BNXT_VNIC_RFS_NEW_RSS_FLAG 0x10
1009 struct bnxt_hw_resc {
1010 u16 min_rsscos_ctxs;
1011 u16 max_rsscos_ctxs;
1018 u16 max_tx_sch_inputs;
1022 u16 min_hw_ring_grps;
1023 u16 max_hw_ring_grps;
1024 u16 resv_hw_ring_grps;
1038 #if defined(CONFIG_BNXT_SRIOV)
1039 struct bnxt_vf_info {
1041 u8 mac_addr[ETH_ALEN]; /* PF assigned MAC Address */
1042 u8 vf_mac_addr[ETH_ALEN]; /* VF assigned MAC address, only
1046 u16 func_qcfg_flags;
1048 #define BNXT_VF_QOS 0x1
1049 #define BNXT_VF_SPOOFCHK 0x2
1050 #define BNXT_VF_LINK_FORCED 0x4
1051 #define BNXT_VF_LINK_UP 0x8
1052 #define BNXT_VF_TRUST 0x10
1053 u32 func_flags; /* func cfg flags */
1056 void *hwrm_cmd_req_addr;
1057 dma_addr_t hwrm_cmd_req_dma_addr;
1061 struct bnxt_pf_info {
1062 #define BNXT_FIRST_PF_FID 1
1063 #define BNXT_FIRST_VF_FID 128
1066 u8 mac_addr[ETH_ALEN];
1070 u32 max_encap_records;
1071 u32 max_decap_records;
1072 u32 max_tx_em_flows;
1073 u32 max_tx_wm_flows;
1074 u32 max_rx_em_flows;
1075 u32 max_rx_wm_flows;
1076 unsigned long *vf_event_bmap;
1077 u16 hwrm_cmd_req_pages;
1078 u8 vf_resv_strategy;
1079 #define BNXT_VF_RESV_STRATEGY_MAXIMAL 0
1080 #define BNXT_VF_RESV_STRATEGY_MINIMAL 1
1081 #define BNXT_VF_RESV_STRATEGY_MINIMAL_STATIC 2
1082 void *hwrm_cmd_req_addr[4];
1083 dma_addr_t hwrm_cmd_req_dma_addr[4];
1084 struct bnxt_vf_info *vf;
1087 struct bnxt_ntuple_filter {
1088 struct hlist_node hash;
1089 u8 dst_mac_addr[ETH_ALEN];
1090 u8 src_mac_addr[ETH_ALEN];
1091 struct flow_keys fkeys;
1097 unsigned long state;
1098 #define BNXT_FLTR_VALID 0
1099 #define BNXT_FLTR_UPDATE 1
1102 struct bnxt_link_info {
1108 #define BNXT_LINK_NO_LINK PORT_PHY_QCFG_RESP_LINK_NO_LINK
1109 #define BNXT_LINK_SIGNAL PORT_PHY_QCFG_RESP_LINK_SIGNAL
1110 #define BNXT_LINK_LINK PORT_PHY_QCFG_RESP_LINK_LINK
1115 #define BNXT_LINK_DUPLEX_HALF PORT_PHY_QCFG_RESP_DUPLEX_STATE_HALF
1116 #define BNXT_LINK_DUPLEX_FULL PORT_PHY_QCFG_RESP_DUPLEX_STATE_FULL
1118 #define BNXT_LINK_PAUSE_TX PORT_PHY_QCFG_RESP_PAUSE_TX
1119 #define BNXT_LINK_PAUSE_RX PORT_PHY_QCFG_RESP_PAUSE_RX
1120 #define BNXT_LINK_PAUSE_BOTH (PORT_PHY_QCFG_RESP_PAUSE_RX | \
1121 PORT_PHY_QCFG_RESP_PAUSE_TX)
1123 u8 auto_pause_setting;
1124 u8 force_pause_setting;
1127 #define BNXT_AUTO_MODE(mode) ((mode) > BNXT_LINK_AUTO_NONE && \
1128 (mode) <= BNXT_LINK_AUTO_MSK)
1129 #define BNXT_LINK_AUTO_NONE PORT_PHY_QCFG_RESP_AUTO_MODE_NONE
1130 #define BNXT_LINK_AUTO_ALLSPDS PORT_PHY_QCFG_RESP_AUTO_MODE_ALL_SPEEDS
1131 #define BNXT_LINK_AUTO_ONESPD PORT_PHY_QCFG_RESP_AUTO_MODE_ONE_SPEED
1132 #define BNXT_LINK_AUTO_ONEORBELOW PORT_PHY_QCFG_RESP_AUTO_MODE_ONE_OR_BELOW
1133 #define BNXT_LINK_AUTO_MSK PORT_PHY_QCFG_RESP_AUTO_MODE_SPEED_MASK
1134 #define PHY_VER_LEN 3
1135 u8 phy_ver[PHY_VER_LEN];
1137 #define BNXT_LINK_SPEED_100MB PORT_PHY_QCFG_RESP_LINK_SPEED_100MB
1138 #define BNXT_LINK_SPEED_1GB PORT_PHY_QCFG_RESP_LINK_SPEED_1GB
1139 #define BNXT_LINK_SPEED_2GB PORT_PHY_QCFG_RESP_LINK_SPEED_2GB
1140 #define BNXT_LINK_SPEED_2_5GB PORT_PHY_QCFG_RESP_LINK_SPEED_2_5GB
1141 #define BNXT_LINK_SPEED_10GB PORT_PHY_QCFG_RESP_LINK_SPEED_10GB
1142 #define BNXT_LINK_SPEED_20GB PORT_PHY_QCFG_RESP_LINK_SPEED_20GB
1143 #define BNXT_LINK_SPEED_25GB PORT_PHY_QCFG_RESP_LINK_SPEED_25GB
1144 #define BNXT_LINK_SPEED_40GB PORT_PHY_QCFG_RESP_LINK_SPEED_40GB
1145 #define BNXT_LINK_SPEED_50GB PORT_PHY_QCFG_RESP_LINK_SPEED_50GB
1146 #define BNXT_LINK_SPEED_100GB PORT_PHY_QCFG_RESP_LINK_SPEED_100GB
1148 u16 auto_link_speeds; /* fw adv setting */
1149 #define BNXT_LINK_SPEED_MSK_100MB PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_100MB
1150 #define BNXT_LINK_SPEED_MSK_1GB PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_1GB
1151 #define BNXT_LINK_SPEED_MSK_2GB PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_2GB
1152 #define BNXT_LINK_SPEED_MSK_10GB PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_10GB
1153 #define BNXT_LINK_SPEED_MSK_2_5GB PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_2_5GB
1154 #define BNXT_LINK_SPEED_MSK_20GB PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_20GB
1155 #define BNXT_LINK_SPEED_MSK_25GB PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_25GB
1156 #define BNXT_LINK_SPEED_MSK_40GB PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_40GB
1157 #define BNXT_LINK_SPEED_MSK_50GB PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_50GB
1158 #define BNXT_LINK_SPEED_MSK_100GB PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_100GB
1159 u16 support_auto_speeds;
1160 u16 lp_auto_link_speeds;
1161 u16 force_link_speed;
1165 #define BNXT_FEC_AUTONEG PORT_PHY_QCFG_RESP_FEC_CFG_FEC_AUTONEG_ENABLED
1166 #define BNXT_FEC_ENC_BASE_R PORT_PHY_QCFG_RESP_FEC_CFG_FEC_CLAUSE74_ENABLED
1167 #define BNXT_FEC_ENC_RS PORT_PHY_QCFG_RESP_FEC_CFG_FEC_CLAUSE91_ENABLED
1169 /* copy of requested setting from ethtool cmd */
1171 #define BNXT_AUTONEG_SPEED 1
1172 #define BNXT_AUTONEG_FLOW_CTRL 2
1176 u16 advertising; /* user adv setting */
1177 bool force_link_chng;
1180 unsigned long phy_retry_expires;
1182 /* a copy of phy_qcfg output used to report link
1185 struct hwrm_port_phy_qcfg_output phy_qcfg_resp;
1188 #define BNXT_MAX_QUEUE 8
1190 struct bnxt_queue_info {
1195 #define BNXT_MAX_LED 4
1197 struct bnxt_led_info {
1202 __le16 led_state_caps;
1203 #define BNXT_LED_ALT_BLINK_CAP(x) ((x) & \
1204 cpu_to_le16(PORT_LED_QCAPS_RESP_LED0_STATE_CAPS_BLINK_ALT_SUPPORTED))
1206 __le16 led_color_caps;
1209 #define BNXT_MAX_TEST 8
1211 struct bnxt_test_info {
1214 #define BNXT_TEST_FL_EXT_LPBK 0x1
1216 char string[BNXT_MAX_TEST][ETH_GSTRING_LEN];
1219 #define BNXT_GRCPF_REG_CHIMP_COMM 0x0
1220 #define BNXT_GRCPF_REG_CHIMP_COMM_TRIGGER 0x100
1221 #define BNXT_GRCPF_REG_WINDOW_BASE_OUT 0x400
1222 #define BNXT_CAG_REG_LEGACY_INT_STATUS 0x4014
1223 #define BNXT_CAG_REG_BASE 0x300000
1225 #define BNXT_GRCPF_REG_KONG_COMM 0xA00
1226 #define BNXT_GRCPF_REG_KONG_COMM_TRIGGER 0xB00
1228 #define BNXT_GRC_BASE_MASK 0xfffff000
1229 #define BNXT_GRC_OFFSET_MASK 0x00000ffc
1231 struct bnxt_tc_flow_stats {
1236 struct bnxt_tc_info {
1239 /* hash table to store TC offloaded flows */
1240 struct rhashtable flow_table;
1241 struct rhashtable_params flow_ht_params;
1243 /* hash table to store L2 keys of TC flows */
1244 struct rhashtable l2_table;
1245 struct rhashtable_params l2_ht_params;
1246 /* hash table to store L2 keys for TC tunnel decap */
1247 struct rhashtable decap_l2_table;
1248 struct rhashtable_params decap_l2_ht_params;
1249 /* hash table to store tunnel decap entries */
1250 struct rhashtable decap_table;
1251 struct rhashtable_params decap_ht_params;
1252 /* hash table to store tunnel encap entries */
1253 struct rhashtable encap_table;
1254 struct rhashtable_params encap_ht_params;
1256 /* lock to atomically add/del an l2 node when a flow is
1261 /* Fields used for batching stats query */
1262 struct rhashtable_iter iter;
1263 #define BNXT_FLOW_STATS_BATCH_MAX 10
1264 struct bnxt_tc_stats_batch {
1266 struct bnxt_tc_flow_stats hw_stats;
1267 } stats_batch[BNXT_FLOW_STATS_BATCH_MAX];
1269 /* Stat counter mask (width) */
1274 struct bnxt_vf_rep_stats {
1280 struct bnxt_vf_rep {
1282 struct net_device *dev;
1283 struct metadata_dst *dst;
1288 struct bnxt_vf_rep_stats rx_stats;
1289 struct bnxt_vf_rep_stats tx_stats;
1292 #define PTU_PTE_VALID 0x1UL
1293 #define PTU_PTE_LAST 0x2UL
1294 #define PTU_PTE_NEXT_TO_LAST 0x4UL
1296 #define MAX_CTX_PAGES (BNXT_PAGE_SIZE / 8)
1297 #define MAX_CTX_TOTAL_PAGES (MAX_CTX_PAGES * MAX_CTX_PAGES)
1299 struct bnxt_ctx_pg_info {
1302 void *ctx_pg_arr[MAX_CTX_PAGES];
1303 dma_addr_t ctx_dma_arr[MAX_CTX_PAGES];
1304 struct bnxt_ring_mem_info ring_mem;
1305 struct bnxt_ctx_pg_info **ctx_pg_tbl;
1308 struct bnxt_ctx_mem_info {
1310 u16 qp_min_qp1_entries;
1311 u16 qp_max_l2_entries;
1313 u16 srq_max_l2_entries;
1314 u32 srq_max_entries;
1316 u16 cq_max_l2_entries;
1319 u16 vnic_max_vnic_entries;
1320 u16 vnic_max_ring_table_entries;
1321 u16 vnic_entry_size;
1322 u32 stat_max_entries;
1323 u16 stat_entry_size;
1325 u32 tqm_min_entries_per_ring;
1326 u32 tqm_max_entries_per_ring;
1327 u32 mrav_max_entries;
1328 u16 mrav_entry_size;
1330 u32 tim_max_entries;
1331 u16 mrav_num_entries_units;
1332 u8 tqm_entries_multiple;
1335 #define BNXT_CTX_FLAG_INITED 0x01
1337 struct bnxt_ctx_pg_info qp_mem;
1338 struct bnxt_ctx_pg_info srq_mem;
1339 struct bnxt_ctx_pg_info cq_mem;
1340 struct bnxt_ctx_pg_info vnic_mem;
1341 struct bnxt_ctx_pg_info stat_mem;
1342 struct bnxt_ctx_pg_info mrav_mem;
1343 struct bnxt_ctx_pg_info tim_mem;
1344 struct bnxt_ctx_pg_info *tqm_mem[9];
1347 struct bnxt_fw_health {
1350 u32 master_func_wait_dsecs;
1351 u32 normal_func_wait_dsecs;
1352 u32 post_reset_wait_dsecs;
1353 u32 post_reset_max_wait_dsecs;
1356 #define BNXT_FW_HEALTH_REG 0
1357 #define BNXT_FW_HEARTBEAT_REG 1
1358 #define BNXT_FW_RESET_CNT_REG 2
1359 #define BNXT_FW_RESET_INPROG_REG 3
1360 u32 fw_reset_inprog_reg_mask;
1361 u32 last_fw_heartbeat;
1362 u32 last_fw_reset_cnt;
1367 u8 fw_reset_seq_cnt;
1368 u32 fw_reset_seq_regs[16];
1369 u32 fw_reset_seq_vals[16];
1370 u32 fw_reset_seq_delay_msec[16];
1371 struct devlink_health_reporter *fw_reporter;
1374 #define BNXT_FW_HEALTH_REG_TYPE_MASK 3
1375 #define BNXT_FW_HEALTH_REG_TYPE_CFG 0
1376 #define BNXT_FW_HEALTH_REG_TYPE_GRC 1
1377 #define BNXT_FW_HEALTH_REG_TYPE_BAR0 2
1378 #define BNXT_FW_HEALTH_REG_TYPE_BAR1 3
1380 #define BNXT_FW_HEALTH_REG_TYPE(reg) ((reg) & BNXT_FW_HEALTH_REG_TYPE_MASK)
1381 #define BNXT_FW_HEALTH_REG_OFF(reg) ((reg) & ~BNXT_FW_HEALTH_REG_TYPE_MASK)
1383 #define BNXT_FW_HEALTH_WIN_BASE 0x3000
1384 #define BNXT_FW_HEALTH_WIN_MAP_OFF 8
1386 #define BNXT_FW_STATUS_HEALTHY 0x8000
1395 #define CHIP_NUM_57301 0x16c8
1396 #define CHIP_NUM_57302 0x16c9
1397 #define CHIP_NUM_57304 0x16ca
1398 #define CHIP_NUM_58700 0x16cd
1399 #define CHIP_NUM_57402 0x16d0
1400 #define CHIP_NUM_57404 0x16d1
1401 #define CHIP_NUM_57406 0x16d2
1402 #define CHIP_NUM_57407 0x16d5
1404 #define CHIP_NUM_57311 0x16ce
1405 #define CHIP_NUM_57312 0x16cf
1406 #define CHIP_NUM_57314 0x16df
1407 #define CHIP_NUM_57317 0x16e0
1408 #define CHIP_NUM_57412 0x16d6
1409 #define CHIP_NUM_57414 0x16d7
1410 #define CHIP_NUM_57416 0x16d8
1411 #define CHIP_NUM_57417 0x16d9
1412 #define CHIP_NUM_57412L 0x16da
1413 #define CHIP_NUM_57414L 0x16db
1415 #define CHIP_NUM_5745X 0xd730
1417 #define CHIP_NUM_57508 0x1750
1418 #define CHIP_NUM_57504 0x1751
1419 #define CHIP_NUM_57502 0x1752
1421 #define CHIP_NUM_58802 0xd802
1422 #define CHIP_NUM_58804 0xd804
1423 #define CHIP_NUM_58808 0xd808
1425 #define BNXT_CHIP_NUM_5730X(chip_num) \
1426 ((chip_num) >= CHIP_NUM_57301 && \
1427 (chip_num) <= CHIP_NUM_57304)
1429 #define BNXT_CHIP_NUM_5740X(chip_num) \
1430 (((chip_num) >= CHIP_NUM_57402 && \
1431 (chip_num) <= CHIP_NUM_57406) || \
1432 (chip_num) == CHIP_NUM_57407)
1434 #define BNXT_CHIP_NUM_5731X(chip_num) \
1435 ((chip_num) == CHIP_NUM_57311 || \
1436 (chip_num) == CHIP_NUM_57312 || \
1437 (chip_num) == CHIP_NUM_57314 || \
1438 (chip_num) == CHIP_NUM_57317)
1440 #define BNXT_CHIP_NUM_5741X(chip_num) \
1441 ((chip_num) >= CHIP_NUM_57412 && \
1442 (chip_num) <= CHIP_NUM_57414L)
1444 #define BNXT_CHIP_NUM_58700(chip_num) \
1445 ((chip_num) == CHIP_NUM_58700)
1447 #define BNXT_CHIP_NUM_5745X(chip_num) \
1448 ((chip_num) == CHIP_NUM_5745X)
1450 #define BNXT_CHIP_NUM_57X0X(chip_num) \
1451 (BNXT_CHIP_NUM_5730X(chip_num) || BNXT_CHIP_NUM_5740X(chip_num))
1453 #define BNXT_CHIP_NUM_57X1X(chip_num) \
1454 (BNXT_CHIP_NUM_5731X(chip_num) || BNXT_CHIP_NUM_5741X(chip_num))
1456 #define BNXT_CHIP_NUM_588XX(chip_num) \
1457 ((chip_num) == CHIP_NUM_58802 || \
1458 (chip_num) == CHIP_NUM_58804 || \
1459 (chip_num) == CHIP_NUM_58808)
1461 struct net_device *dev;
1462 struct pci_dev *pdev;
1467 #define BNXT_FLAG_CHIP_P5 0x1
1468 #define BNXT_FLAG_VF 0x2
1469 #define BNXT_FLAG_LRO 0x4
1471 #define BNXT_FLAG_GRO 0x8
1473 /* Cannot support hardware GRO if CONFIG_INET is not set */
1474 #define BNXT_FLAG_GRO 0x0
1476 #define BNXT_FLAG_TPA (BNXT_FLAG_LRO | BNXT_FLAG_GRO)
1477 #define BNXT_FLAG_JUMBO 0x10
1478 #define BNXT_FLAG_STRIP_VLAN 0x20
1479 #define BNXT_FLAG_AGG_RINGS (BNXT_FLAG_JUMBO | BNXT_FLAG_GRO | \
1481 #define BNXT_FLAG_USING_MSIX 0x40
1482 #define BNXT_FLAG_MSIX_CAP 0x80
1483 #define BNXT_FLAG_RFS 0x100
1484 #define BNXT_FLAG_SHARED_RINGS 0x200
1485 #define BNXT_FLAG_PORT_STATS 0x400
1486 #define BNXT_FLAG_UDP_RSS_CAP 0x800
1487 #define BNXT_FLAG_EEE_CAP 0x1000
1488 #define BNXT_FLAG_NEW_RSS_CAP 0x2000
1489 #define BNXT_FLAG_WOL_CAP 0x4000
1490 #define BNXT_FLAG_ROCEV1_CAP 0x8000
1491 #define BNXT_FLAG_ROCEV2_CAP 0x10000
1492 #define BNXT_FLAG_ROCE_CAP (BNXT_FLAG_ROCEV1_CAP | \
1493 BNXT_FLAG_ROCEV2_CAP)
1494 #define BNXT_FLAG_NO_AGG_RINGS 0x20000
1495 #define BNXT_FLAG_RX_PAGE_MODE 0x40000
1496 #define BNXT_FLAG_MULTI_HOST 0x100000
1497 #define BNXT_FLAG_DOUBLE_DB 0x400000
1498 #define BNXT_FLAG_CHIP_NITRO_A0 0x1000000
1499 #define BNXT_FLAG_DIM 0x2000000
1500 #define BNXT_FLAG_ROCE_MIRROR_CAP 0x4000000
1501 #define BNXT_FLAG_PORT_STATS_EXT 0x10000000
1502 #define BNXT_FLAG_PCIE_STATS 0x40000000
1504 #define BNXT_FLAG_ALL_CONFIG_FEATS (BNXT_FLAG_TPA | \
1506 BNXT_FLAG_STRIP_VLAN)
1508 #define BNXT_PF(bp) (!((bp)->flags & BNXT_FLAG_VF))
1509 #define BNXT_VF(bp) ((bp)->flags & BNXT_FLAG_VF)
1510 #define BNXT_NPAR(bp) ((bp)->port_partition_type)
1511 #define BNXT_MH(bp) ((bp)->flags & BNXT_FLAG_MULTI_HOST)
1512 #define BNXT_SINGLE_PF(bp) (BNXT_PF(bp) && !BNXT_NPAR(bp) && !BNXT_MH(bp))
1513 #define BNXT_CHIP_TYPE_NITRO_A0(bp) ((bp)->flags & BNXT_FLAG_CHIP_NITRO_A0)
1514 #define BNXT_RX_PAGE_MODE(bp) ((bp)->flags & BNXT_FLAG_RX_PAGE_MODE)
1515 #define BNXT_SUPPORTS_TPA(bp) (!BNXT_CHIP_TYPE_NITRO_A0(bp) && \
1516 (!((bp)->flags & BNXT_FLAG_CHIP_P5) || \
1517 (bp)->max_tpa_v2) && !is_kdump_kernel())
1519 /* Chip class phase 5 */
1520 #define BNXT_CHIP_P5(bp) \
1521 ((bp)->chip_num == CHIP_NUM_57508 || \
1522 (bp)->chip_num == CHIP_NUM_57504 || \
1523 (bp)->chip_num == CHIP_NUM_57502)
1525 /* Chip class phase 4.x */
1526 #define BNXT_CHIP_P4(bp) \
1527 (BNXT_CHIP_NUM_57X1X((bp)->chip_num) || \
1528 BNXT_CHIP_NUM_5745X((bp)->chip_num) || \
1529 BNXT_CHIP_NUM_588XX((bp)->chip_num) || \
1530 (BNXT_CHIP_NUM_58700((bp)->chip_num) && \
1531 !BNXT_CHIP_TYPE_NITRO_A0(bp)))
1533 #define BNXT_CHIP_P4_PLUS(bp) \
1534 (BNXT_CHIP_P4(bp) || BNXT_CHIP_P5(bp))
1536 struct bnxt_en_dev *edev;
1537 struct bnxt_en_dev * (*ulp_probe)(struct net_device *);
1539 struct bnxt_napi **bnapi;
1541 struct bnxt_rx_ring_info *rx_ring;
1542 struct bnxt_tx_ring_info *tx_ring;
1545 struct sk_buff * (*gro_func)(struct bnxt_tpa_info *, int, int,
1548 struct sk_buff * (*rx_skb_func)(struct bnxt *,
1549 struct bnxt_rx_ring_info *,
1550 u16, void *, u8 *, dma_addr_t,
1556 u32 rx_buf_use_size; /* useable size */
1559 enum dma_data_direction rx_dir;
1561 u32 rx_agg_ring_size;
1564 u32 rx_agg_ring_mask;
1566 int rx_agg_nr_pages;
1574 int tx_nr_rings_per_tc;
1575 int tx_nr_rings_xdp;
1587 /* grp_info indexed by completion ring index */
1588 struct bnxt_ring_grp_info *grp_info;
1589 struct bnxt_vnic_info *vnic_info;
1595 u8 max_lltc; /* lossless TCs */
1596 struct bnxt_queue_info q_info[BNXT_MAX_QUEUE];
1597 u8 tc_to_qidx[BNXT_MAX_QUEUE];
1598 u8 q_ids[BNXT_MAX_QUEUE];
1601 unsigned int current_interval;
1602 #define BNXT_TIMER_INTERVAL HZ
1604 struct timer_list timer;
1606 unsigned long state;
1607 #define BNXT_STATE_OPEN 0
1608 #define BNXT_STATE_IN_SP_TASK 1
1609 #define BNXT_STATE_READ_STATS 2
1610 #define BNXT_STATE_FW_RESET_DET 3
1611 #define BNXT_STATE_IN_FW_RESET 4
1612 #define BNXT_STATE_ABORT_ERR 5
1614 struct bnxt_irq *irq_tbl;
1616 u8 mac_addr[ETH_ALEN];
1618 #ifdef CONFIG_BNXT_DCB
1619 struct ieee_pfc *ieee_pfc;
1620 struct ieee_ets *ieee_ets;
1624 #endif /* CONFIG_BNXT_DCB */
1629 #define BNXT_FW_CAP_SHORT_CMD 0x00000001
1630 #define BNXT_FW_CAP_LLDP_AGENT 0x00000002
1631 #define BNXT_FW_CAP_DCBX_AGENT 0x00000004
1632 #define BNXT_FW_CAP_NEW_RM 0x00000008
1633 #define BNXT_FW_CAP_IF_CHANGE 0x00000010
1634 #define BNXT_FW_CAP_KONG_MB_CHNL 0x00000080
1635 #define BNXT_FW_CAP_OVS_64BIT_HANDLE 0x00000400
1636 #define BNXT_FW_CAP_TRUSTED_VF 0x00000800
1637 #define BNXT_FW_CAP_ERROR_RECOVERY 0x00002000
1638 #define BNXT_FW_CAP_PKG_VER 0x00004000
1639 #define BNXT_FW_CAP_CFA_ADV_FLOW 0x00008000
1640 #define BNXT_FW_CAP_CFA_RFS_RING_TBL_IDX 0x00010000
1641 #define BNXT_FW_CAP_PCIE_STATS_SUPPORTED 0x00020000
1642 #define BNXT_FW_CAP_EXT_STATS_SUPPORTED 0x00040000
1644 #define BNXT_NEW_RM(bp) ((bp)->fw_cap & BNXT_FW_CAP_NEW_RM)
1647 u16 hwrm_cmd_kong_seq;
1648 u16 hwrm_intr_seq_id;
1649 void *hwrm_short_cmd_req_addr;
1650 dma_addr_t hwrm_short_cmd_req_dma_addr;
1651 void *hwrm_cmd_resp_addr;
1652 dma_addr_t hwrm_cmd_resp_dma_addr;
1653 void *hwrm_cmd_kong_resp_addr;
1654 dma_addr_t hwrm_cmd_kong_resp_dma_addr;
1656 struct rtnl_link_stats64 net_stats_prev;
1657 struct rx_port_stats *hw_rx_port_stats;
1658 struct tx_port_stats *hw_tx_port_stats;
1659 struct rx_port_stats_ext *hw_rx_port_stats_ext;
1660 struct tx_port_stats_ext *hw_tx_port_stats_ext;
1661 struct pcie_ctx_hw_stats *hw_pcie_stats;
1662 dma_addr_t hw_rx_port_stats_map;
1663 dma_addr_t hw_tx_port_stats_map;
1664 dma_addr_t hw_rx_port_stats_ext_map;
1665 dma_addr_t hw_tx_port_stats_ext_map;
1666 dma_addr_t hw_pcie_stats_map;
1667 int hw_port_stats_size;
1668 u16 fw_rx_stats_ext_size;
1669 u16 fw_tx_stats_ext_size;
1670 u16 hw_ring_stats_size;
1674 u16 hwrm_max_req_len;
1675 u16 hwrm_max_ext_req_len;
1676 int hwrm_cmd_timeout;
1677 struct mutex hwrm_cmd_lock; /* serialize hwrm messages */
1678 struct hwrm_ver_get_output ver_resp;
1679 #define FW_VER_STR_LEN 32
1680 #define BC_HWRM_STR_LEN 21
1681 #define PHY_VER_STR_LEN (FW_VER_STR_LEN - BC_HWRM_STR_LEN)
1682 char fw_ver_str[FW_VER_STR_LEN];
1685 __le16 vxlan_fw_dst_port_id;
1688 __le16 nge_fw_dst_port_id;
1689 u8 port_partition_type;
1693 struct bnxt_coal_cap coal_cap;
1694 struct bnxt_coal rx_coal;
1695 struct bnxt_coal tx_coal;
1697 u32 stats_coal_ticks;
1698 #define BNXT_DEF_STATS_COAL_TICKS 1000000
1699 #define BNXT_MIN_STATS_COAL_TICKS 250000
1700 #define BNXT_MAX_STATS_COAL_TICKS 1000000
1702 struct work_struct sp_task;
1703 unsigned long sp_event;
1704 #define BNXT_RX_MASK_SP_EVENT 0
1705 #define BNXT_RX_NTP_FLTR_SP_EVENT 1
1706 #define BNXT_LINK_CHNG_SP_EVENT 2
1707 #define BNXT_HWRM_EXEC_FWD_REQ_SP_EVENT 3
1708 #define BNXT_VXLAN_ADD_PORT_SP_EVENT 4
1709 #define BNXT_VXLAN_DEL_PORT_SP_EVENT 5
1710 #define BNXT_RESET_TASK_SP_EVENT 6
1711 #define BNXT_RST_RING_SP_EVENT 7
1712 #define BNXT_HWRM_PF_UNLOAD_SP_EVENT 8
1713 #define BNXT_PERIODIC_STATS_SP_EVENT 9
1714 #define BNXT_HWRM_PORT_MODULE_SP_EVENT 10
1715 #define BNXT_RESET_TASK_SILENT_SP_EVENT 11
1716 #define BNXT_GENEVE_ADD_PORT_SP_EVENT 12
1717 #define BNXT_GENEVE_DEL_PORT_SP_EVENT 13
1718 #define BNXT_LINK_SPEED_CHNG_SP_EVENT 14
1719 #define BNXT_FLOW_STATS_SP_EVENT 15
1720 #define BNXT_UPDATE_PHY_SP_EVENT 16
1721 #define BNXT_RING_COAL_NOW_SP_EVENT 17
1722 #define BNXT_FW_RESET_NOTIFY_SP_EVENT 18
1724 u16 fw_reset_min_dsecs;
1725 #define BNXT_DFLT_FW_RST_MIN_DSECS 20
1726 u16 fw_reset_max_dsecs;
1727 #define BNXT_DFLT_FW_RST_MAX_DSECS 60
1728 unsigned long fw_reset_timestamp;
1730 struct bnxt_fw_health *fw_health;
1732 struct bnxt_hw_resc hw_resc;
1733 struct bnxt_pf_info pf;
1734 struct bnxt_ctx_mem_info *ctx;
1735 #ifdef CONFIG_BNXT_SRIOV
1737 struct bnxt_vf_info vf;
1738 wait_queue_head_t sriov_cfg_wait;
1740 #define BNXT_SRIOV_CFG_WAIT_TMO msecs_to_jiffies(10000)
1742 /* lock to protect VF-rep creation/cleanup via
1743 * multiple paths such as ->sriov_configure() and
1744 * devlink ->eswitch_mode_set()
1746 struct mutex sriov_lock;
1749 #if BITS_PER_LONG == 32
1750 /* ensure atomic 64-bit doorbell writes on 32-bit systems. */
1754 #define BNXT_NTP_FLTR_MAX_FLTR 4096
1755 #define BNXT_NTP_FLTR_HASH_SIZE 512
1756 #define BNXT_NTP_FLTR_HASH_MASK (BNXT_NTP_FLTR_HASH_SIZE - 1)
1757 struct hlist_head ntp_fltr_hash_tbl[BNXT_NTP_FLTR_HASH_SIZE];
1758 spinlock_t ntp_fltr_lock; /* for hash table add, del */
1760 unsigned long *ntp_fltr_bmap;
1763 /* To protect link related settings during link changes and
1764 * ethtool settings changes.
1766 struct mutex link_lock;
1767 struct bnxt_link_info link_info;
1768 struct ethtool_eee eee;
1773 struct bnxt_test_info *test_info;
1779 struct bnxt_led_info leds[BNXT_MAX_LED];
1781 struct bpf_prog *xdp_prog;
1783 /* devlink interface and vf-rep structs */
1785 struct devlink_port dl_port;
1786 enum devlink_eswitch_mode eswitch_mode;
1787 struct bnxt_vf_rep **vf_reps; /* array of vf-rep ptrs */
1788 u16 *cfa_code_map; /* cfa_code -> vf_idx map */
1790 struct bnxt_tc_info *tc_info;
1791 struct dentry *debugfs_pdev;
1792 struct device *hwmon_dev;
1795 #define BNXT_RX_STATS_OFFSET(counter) \
1796 (offsetof(struct rx_port_stats, counter) / 8)
1798 #define BNXT_TX_STATS_OFFSET(counter) \
1799 ((offsetof(struct tx_port_stats, counter) + \
1800 sizeof(struct rx_port_stats) + 512) / 8)
1802 #define BNXT_RX_STATS_EXT_OFFSET(counter) \
1803 (offsetof(struct rx_port_stats_ext, counter) / 8)
1805 #define BNXT_TX_STATS_EXT_OFFSET(counter) \
1806 (offsetof(struct tx_port_stats_ext, counter) / 8)
1808 #define BNXT_PCIE_STATS_OFFSET(counter) \
1809 (offsetof(struct pcie_ctx_hw_stats, counter) / 8)
1811 #define I2C_DEV_ADDR_A0 0xa0
1812 #define I2C_DEV_ADDR_A2 0xa2
1813 #define SFF_DIAG_SUPPORT_OFFSET 0x5c
1814 #define SFF_MODULE_ID_SFP 0x3
1815 #define SFF_MODULE_ID_QSFP 0xc
1816 #define SFF_MODULE_ID_QSFP_PLUS 0xd
1817 #define SFF_MODULE_ID_QSFP28 0x11
1818 #define BNXT_MAX_PHY_I2C_RESP_SIZE 64
1820 static inline u32 bnxt_tx_avail(struct bnxt *bp, struct bnxt_tx_ring_info *txr)
1822 /* Tell compiler to fetch tx indices from memory. */
1825 return bp->tx_ring_size -
1826 ((txr->tx_prod - txr->tx_cons) & bp->tx_ring_mask);
1829 #if BITS_PER_LONG == 32
1830 #define writeq(val64, db) \
1832 spin_lock(&bp->db_lock); \
1833 writel((val64) & 0xffffffff, db); \
1834 writel((val64) >> 32, (db) + 4); \
1835 spin_unlock(&bp->db_lock); \
1838 #define writeq_relaxed writeq
1841 /* For TX and RX ring doorbells with no ordering guarantee*/
1842 static inline void bnxt_db_write_relaxed(struct bnxt *bp,
1843 struct bnxt_db_info *db, u32 idx)
1845 if (bp->flags & BNXT_FLAG_CHIP_P5) {
1846 writeq_relaxed(db->db_key64 | idx, db->doorbell);
1848 u32 db_val = db->db_key32 | idx;
1850 writel_relaxed(db_val, db->doorbell);
1851 if (bp->flags & BNXT_FLAG_DOUBLE_DB)
1852 writel_relaxed(db_val, db->doorbell);
1856 /* For TX and RX ring doorbells */
1857 static inline void bnxt_db_write(struct bnxt *bp, struct bnxt_db_info *db,
1860 if (bp->flags & BNXT_FLAG_CHIP_P5) {
1861 writeq(db->db_key64 | idx, db->doorbell);
1863 u32 db_val = db->db_key32 | idx;
1865 writel(db_val, db->doorbell);
1866 if (bp->flags & BNXT_FLAG_DOUBLE_DB)
1867 writel(db_val, db->doorbell);
1871 static inline bool bnxt_cfa_hwrm_message(u16 req_type)
1874 case HWRM_CFA_ENCAP_RECORD_ALLOC:
1875 case HWRM_CFA_ENCAP_RECORD_FREE:
1876 case HWRM_CFA_DECAP_FILTER_ALLOC:
1877 case HWRM_CFA_DECAP_FILTER_FREE:
1878 case HWRM_CFA_NTUPLE_FILTER_ALLOC:
1879 case HWRM_CFA_NTUPLE_FILTER_FREE:
1880 case HWRM_CFA_NTUPLE_FILTER_CFG:
1881 case HWRM_CFA_EM_FLOW_ALLOC:
1882 case HWRM_CFA_EM_FLOW_FREE:
1883 case HWRM_CFA_EM_FLOW_CFG:
1884 case HWRM_CFA_FLOW_ALLOC:
1885 case HWRM_CFA_FLOW_FREE:
1886 case HWRM_CFA_FLOW_INFO:
1887 case HWRM_CFA_FLOW_FLUSH:
1888 case HWRM_CFA_FLOW_STATS:
1889 case HWRM_CFA_METER_PROFILE_ALLOC:
1890 case HWRM_CFA_METER_PROFILE_FREE:
1891 case HWRM_CFA_METER_PROFILE_CFG:
1892 case HWRM_CFA_METER_INSTANCE_ALLOC:
1893 case HWRM_CFA_METER_INSTANCE_FREE:
1900 static inline bool bnxt_kong_hwrm_message(struct bnxt *bp, struct input *req)
1902 return (bp->fw_cap & BNXT_FW_CAP_KONG_MB_CHNL &&
1903 bnxt_cfa_hwrm_message(le16_to_cpu(req->req_type)));
1906 static inline bool bnxt_hwrm_kong_chnl(struct bnxt *bp, struct input *req)
1908 return (bp->fw_cap & BNXT_FW_CAP_KONG_MB_CHNL &&
1909 req->resp_addr == cpu_to_le64(bp->hwrm_cmd_kong_resp_dma_addr));
1912 static inline void *bnxt_get_hwrm_resp_addr(struct bnxt *bp, void *req)
1914 if (bnxt_hwrm_kong_chnl(bp, (struct input *)req))
1915 return bp->hwrm_cmd_kong_resp_addr;
1917 return bp->hwrm_cmd_resp_addr;
1920 static inline u16 bnxt_get_hwrm_seq_id(struct bnxt *bp, u16 dst)
1924 if (dst == BNXT_HWRM_CHNL_CHIMP)
1925 seq_id = bp->hwrm_cmd_seq++;
1927 seq_id = bp->hwrm_cmd_kong_seq++;
1931 extern const u16 bnxt_lhint_arr[];
1933 int bnxt_alloc_rx_data(struct bnxt *bp, struct bnxt_rx_ring_info *rxr,
1934 u16 prod, gfp_t gfp);
1935 void bnxt_reuse_rx_data(struct bnxt_rx_ring_info *rxr, u16 cons, void *data);
1936 u32 bnxt_fw_health_readl(struct bnxt *bp, int reg_idx);
1937 void bnxt_set_tpa_flags(struct bnxt *bp);
1938 void bnxt_set_ring_params(struct bnxt *);
1939 int bnxt_set_rx_skb_mode(struct bnxt *bp, bool page_mode);
1940 void bnxt_hwrm_cmd_hdr_init(struct bnxt *, void *, u16, u16, u16);
1941 int _hwrm_send_message(struct bnxt *, void *, u32, int);
1942 int _hwrm_send_message_silent(struct bnxt *bp, void *msg, u32 len, int timeout);
1943 int hwrm_send_message(struct bnxt *, void *, u32, int);
1944 int hwrm_send_message_silent(struct bnxt *, void *, u32, int);
1945 int bnxt_hwrm_func_rgtr_async_events(struct bnxt *bp, unsigned long *bmap,
1947 int bnxt_hwrm_vnic_cfg(struct bnxt *bp, u16 vnic_id);
1948 int __bnxt_hwrm_get_tx_rings(struct bnxt *bp, u16 fid, int *tx_rings);
1949 int bnxt_nq_rings_in_use(struct bnxt *bp);
1950 int bnxt_hwrm_set_coal(struct bnxt *);
1951 unsigned int bnxt_get_max_func_stat_ctxs(struct bnxt *bp);
1952 unsigned int bnxt_get_avail_stat_ctxs_for_en(struct bnxt *bp);
1953 unsigned int bnxt_get_max_func_cp_rings(struct bnxt *bp);
1954 unsigned int bnxt_get_avail_cp_rings_for_en(struct bnxt *bp);
1955 int bnxt_get_avail_msix(struct bnxt *bp, int num);
1956 int bnxt_reserve_rings(struct bnxt *bp, bool irq_re_init);
1957 void bnxt_tx_disable(struct bnxt *bp);
1958 void bnxt_tx_enable(struct bnxt *bp);
1959 int bnxt_hwrm_set_pause(struct bnxt *);
1960 int bnxt_hwrm_set_link_setting(struct bnxt *, bool, bool);
1961 int bnxt_hwrm_alloc_wol_fltr(struct bnxt *bp);
1962 int bnxt_hwrm_free_wol_fltr(struct bnxt *bp);
1963 int bnxt_hwrm_func_resc_qcaps(struct bnxt *bp, bool all);
1964 int bnxt_hwrm_fw_set_time(struct bnxt *);
1965 int bnxt_open_nic(struct bnxt *, bool, bool);
1966 int bnxt_half_open_nic(struct bnxt *bp);
1967 void bnxt_half_close_nic(struct bnxt *bp);
1968 int bnxt_close_nic(struct bnxt *, bool, bool);
1969 int bnxt_check_rings(struct bnxt *bp, int tx, int rx, bool sh, int tcs,
1971 int bnxt_setup_mq_tc(struct net_device *dev, u8 tc);
1972 int bnxt_get_max_rings(struct bnxt *, int *, int *, bool);
1973 int bnxt_restore_pf_fw_resources(struct bnxt *bp);
1974 int bnxt_get_port_parent_id(struct net_device *dev,
1975 struct netdev_phys_item_id *ppid);
1976 void bnxt_dim_work(struct work_struct *work);
1977 int bnxt_hwrm_set_ring_coal(struct bnxt *bp, struct bnxt_napi *bnapi);