1 /* Broadcom NetXtreme-C/E network driver.
3 * Copyright (c) 2014-2016 Broadcom Corporation
4 * Copyright (c) 2016-2018 Broadcom Limited
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation.
14 #define DRV_MODULE_NAME "bnxt_en"
16 /* DO NOT CHANGE DRV_VER_* defines
20 #define DRV_VER_MIN 10
23 #include <linux/ethtool.h>
24 #include <linux/interrupt.h>
25 #include <linux/rhashtable.h>
26 #include <linux/crash_dump.h>
27 #include <linux/auxiliary_bus.h>
28 #include <net/devlink.h>
29 #include <net/dst_metadata.h>
31 #include <linux/dim.h>
32 #include <linux/io-64-nonatomic-lo-hi.h>
33 #ifdef CONFIG_TEE_BNXT_FW
34 #include <linux/firmware/broadcom/tee_bnxt_fw.h>
37 extern struct list_head bnxt_block_cb_list;
42 __le32 tx_bd_len_flags_type;
43 #define TX_BD_TYPE (0x3f << 0)
44 #define TX_BD_TYPE_SHORT_TX_BD (0x00 << 0)
45 #define TX_BD_TYPE_LONG_TX_BD (0x10 << 0)
46 #define TX_BD_FLAGS_PACKET_END (1 << 6)
47 #define TX_BD_FLAGS_NO_CMPL (1 << 7)
48 #define TX_BD_FLAGS_BD_CNT (0x1f << 8)
49 #define TX_BD_FLAGS_BD_CNT_SHIFT 8
50 #define TX_BD_FLAGS_LHINT (3 << 13)
51 #define TX_BD_FLAGS_LHINT_SHIFT 13
52 #define TX_BD_FLAGS_LHINT_512_AND_SMALLER (0 << 13)
53 #define TX_BD_FLAGS_LHINT_512_TO_1023 (1 << 13)
54 #define TX_BD_FLAGS_LHINT_1024_TO_2047 (2 << 13)
55 #define TX_BD_FLAGS_LHINT_2048_AND_LARGER (3 << 13)
56 #define TX_BD_FLAGS_COAL_NOW (1 << 15)
57 #define TX_BD_LEN (0xffff << 16)
58 #define TX_BD_LEN_SHIFT 16
65 __le32 tx_bd_hsize_lflags;
66 #define TX_BD_FLAGS_TCP_UDP_CHKSUM (1 << 0)
67 #define TX_BD_FLAGS_IP_CKSUM (1 << 1)
68 #define TX_BD_FLAGS_NO_CRC (1 << 2)
69 #define TX_BD_FLAGS_STAMP (1 << 3)
70 #define TX_BD_FLAGS_T_IP_CHKSUM (1 << 4)
71 #define TX_BD_FLAGS_LSO (1 << 5)
72 #define TX_BD_FLAGS_IPID_FMT (1 << 6)
73 #define TX_BD_FLAGS_T_IPID (1 << 7)
74 #define TX_BD_HSIZE (0xff << 16)
75 #define TX_BD_HSIZE_SHIFT 16
78 __le32 tx_bd_cfa_action;
79 #define TX_BD_CFA_ACTION (0xffff << 16)
80 #define TX_BD_CFA_ACTION_SHIFT 16
82 __le32 tx_bd_cfa_meta;
83 #define TX_BD_CFA_META_MASK 0xfffffff
84 #define TX_BD_CFA_META_VID_MASK 0xfff
85 #define TX_BD_CFA_META_PRI_MASK (0xf << 12)
86 #define TX_BD_CFA_META_PRI_SHIFT 12
87 #define TX_BD_CFA_META_TPID_MASK (3 << 16)
88 #define TX_BD_CFA_META_TPID_SHIFT 16
89 #define TX_BD_CFA_META_KEY (0xf << 28)
90 #define TX_BD_CFA_META_KEY_SHIFT 28
91 #define TX_BD_CFA_META_KEY_VLAN (1 << 28)
94 #define BNXT_TX_PTP_IS_SET(lflags) ((lflags) & cpu_to_le32(TX_BD_FLAGS_STAMP))
97 __le32 rx_bd_len_flags_type;
98 #define RX_BD_TYPE (0x3f << 0)
99 #define RX_BD_TYPE_RX_PACKET_BD 0x4
100 #define RX_BD_TYPE_RX_BUFFER_BD 0x5
101 #define RX_BD_TYPE_RX_AGG_BD 0x6
102 #define RX_BD_TYPE_16B_BD_SIZE (0 << 4)
103 #define RX_BD_TYPE_32B_BD_SIZE (1 << 4)
104 #define RX_BD_TYPE_48B_BD_SIZE (2 << 4)
105 #define RX_BD_TYPE_64B_BD_SIZE (3 << 4)
106 #define RX_BD_FLAGS_SOP (1 << 6)
107 #define RX_BD_FLAGS_EOP (1 << 7)
108 #define RX_BD_FLAGS_BUFFERS (3 << 8)
109 #define RX_BD_FLAGS_1_BUFFER_PACKET (0 << 8)
110 #define RX_BD_FLAGS_2_BUFFER_PACKET (1 << 8)
111 #define RX_BD_FLAGS_3_BUFFER_PACKET (2 << 8)
112 #define RX_BD_FLAGS_4_BUFFER_PACKET (3 << 8)
113 #define RX_BD_LEN (0xffff << 16)
114 #define RX_BD_LEN_SHIFT 16
121 __le32 tx_cmp_flags_type;
122 #define CMP_TYPE (0x3f << 0)
123 #define CMP_TYPE_TX_L2_CMP 0
124 #define CMP_TYPE_RX_L2_CMP 17
125 #define CMP_TYPE_RX_AGG_CMP 18
126 #define CMP_TYPE_RX_L2_TPA_START_CMP 19
127 #define CMP_TYPE_RX_L2_TPA_END_CMP 21
128 #define CMP_TYPE_RX_TPA_AGG_CMP 22
129 #define CMP_TYPE_STATUS_CMP 32
130 #define CMP_TYPE_REMOTE_DRIVER_REQ 34
131 #define CMP_TYPE_REMOTE_DRIVER_RESP 36
132 #define CMP_TYPE_ERROR_STATUS 48
133 #define CMPL_BASE_TYPE_STAT_EJECT 0x1aUL
134 #define CMPL_BASE_TYPE_HWRM_DONE 0x20UL
135 #define CMPL_BASE_TYPE_HWRM_FWD_REQ 0x22UL
136 #define CMPL_BASE_TYPE_HWRM_FWD_RESP 0x24UL
137 #define CMPL_BASE_TYPE_HWRM_ASYNC_EVENT 0x2eUL
139 #define TX_CMP_FLAGS_ERROR (1 << 6)
140 #define TX_CMP_FLAGS_PUSH (1 << 7)
143 __le32 tx_cmp_errors_v;
144 #define TX_CMP_V (1 << 0)
145 #define TX_CMP_ERRORS_BUFFER_ERROR (7 << 1)
146 #define TX_CMP_ERRORS_BUFFER_ERROR_NO_ERROR 0
147 #define TX_CMP_ERRORS_BUFFER_ERROR_BAD_FORMAT 2
148 #define TX_CMP_ERRORS_BUFFER_ERROR_INVALID_STAG 4
149 #define TX_CMP_ERRORS_BUFFER_ERROR_STAG_BOUNDS 5
150 #define TX_CMP_ERRORS_ZERO_LENGTH_PKT (1 << 4)
151 #define TX_CMP_ERRORS_EXCESSIVE_BD_LEN (1 << 5)
152 #define TX_CMP_ERRORS_DMA_ERROR (1 << 6)
153 #define TX_CMP_ERRORS_HINT_TOO_SHORT (1 << 7)
155 __le32 tx_cmp_unsed_3;
159 __le32 rx_cmp_len_flags_type;
160 #define RX_CMP_CMP_TYPE (0x3f << 0)
161 #define RX_CMP_FLAGS_ERROR (1 << 6)
162 #define RX_CMP_FLAGS_PLACEMENT (7 << 7)
163 #define RX_CMP_FLAGS_RSS_VALID (1 << 10)
164 #define RX_CMP_FLAGS_UNUSED (1 << 11)
165 #define RX_CMP_FLAGS_ITYPES_SHIFT 12
166 #define RX_CMP_FLAGS_ITYPES_MASK 0xf000
167 #define RX_CMP_FLAGS_ITYPE_UNKNOWN (0 << 12)
168 #define RX_CMP_FLAGS_ITYPE_IP (1 << 12)
169 #define RX_CMP_FLAGS_ITYPE_TCP (2 << 12)
170 #define RX_CMP_FLAGS_ITYPE_UDP (3 << 12)
171 #define RX_CMP_FLAGS_ITYPE_FCOE (4 << 12)
172 #define RX_CMP_FLAGS_ITYPE_ROCE (5 << 12)
173 #define RX_CMP_FLAGS_ITYPE_PTP_WO_TS (8 << 12)
174 #define RX_CMP_FLAGS_ITYPE_PTP_W_TS (9 << 12)
175 #define RX_CMP_LEN (0xffff << 16)
176 #define RX_CMP_LEN_SHIFT 16
179 __le32 rx_cmp_misc_v1;
180 #define RX_CMP_V1 (1 << 0)
181 #define RX_CMP_AGG_BUFS (0x1f << 1)
182 #define RX_CMP_AGG_BUFS_SHIFT 1
183 #define RX_CMP_RSS_HASH_TYPE (0x7f << 9)
184 #define RX_CMP_RSS_HASH_TYPE_SHIFT 9
185 #define RX_CMP_PAYLOAD_OFFSET (0xff << 16)
186 #define RX_CMP_PAYLOAD_OFFSET_SHIFT 16
188 __le32 rx_cmp_rss_hash;
191 #define RX_CMP_HASH_VALID(rxcmp) \
192 ((rxcmp)->rx_cmp_len_flags_type & cpu_to_le32(RX_CMP_FLAGS_RSS_VALID))
194 #define RSS_PROFILE_ID_MASK 0x1f
196 #define RX_CMP_HASH_TYPE(rxcmp) \
197 (((le32_to_cpu((rxcmp)->rx_cmp_misc_v1) & RX_CMP_RSS_HASH_TYPE) >>\
198 RX_CMP_RSS_HASH_TYPE_SHIFT) & RSS_PROFILE_ID_MASK)
201 __le32 rx_cmp_flags2;
202 #define RX_CMP_FLAGS2_IP_CS_CALC 0x1
203 #define RX_CMP_FLAGS2_L4_CS_CALC (0x1 << 1)
204 #define RX_CMP_FLAGS2_T_IP_CS_CALC (0x1 << 2)
205 #define RX_CMP_FLAGS2_T_L4_CS_CALC (0x1 << 3)
206 #define RX_CMP_FLAGS2_META_FORMAT_VLAN (0x1 << 4)
207 __le32 rx_cmp_meta_data;
208 #define RX_CMP_FLAGS2_METADATA_TCI_MASK 0xffff
209 #define RX_CMP_FLAGS2_METADATA_VID_MASK 0xfff
210 #define RX_CMP_FLAGS2_METADATA_TPID_MASK 0xffff0000
211 #define RX_CMP_FLAGS2_METADATA_TPID_SFT 16
212 __le32 rx_cmp_cfa_code_errors_v2;
213 #define RX_CMP_V (1 << 0)
214 #define RX_CMPL_ERRORS_MASK (0x7fff << 1)
215 #define RX_CMPL_ERRORS_SFT 1
216 #define RX_CMPL_ERRORS_BUFFER_ERROR_MASK (0x7 << 1)
217 #define RX_CMPL_ERRORS_BUFFER_ERROR_NO_BUFFER (0x0 << 1)
218 #define RX_CMPL_ERRORS_BUFFER_ERROR_DID_NOT_FIT (0x1 << 1)
219 #define RX_CMPL_ERRORS_BUFFER_ERROR_NOT_ON_CHIP (0x2 << 1)
220 #define RX_CMPL_ERRORS_BUFFER_ERROR_BAD_FORMAT (0x3 << 1)
221 #define RX_CMPL_ERRORS_IP_CS_ERROR (0x1 << 4)
222 #define RX_CMPL_ERRORS_L4_CS_ERROR (0x1 << 5)
223 #define RX_CMPL_ERRORS_T_IP_CS_ERROR (0x1 << 6)
224 #define RX_CMPL_ERRORS_T_L4_CS_ERROR (0x1 << 7)
225 #define RX_CMPL_ERRORS_CRC_ERROR (0x1 << 8)
226 #define RX_CMPL_ERRORS_T_PKT_ERROR_MASK (0x7 << 9)
227 #define RX_CMPL_ERRORS_T_PKT_ERROR_NO_ERROR (0x0 << 9)
228 #define RX_CMPL_ERRORS_T_PKT_ERROR_T_L3_BAD_VERSION (0x1 << 9)
229 #define RX_CMPL_ERRORS_T_PKT_ERROR_T_L3_BAD_HDR_LEN (0x2 << 9)
230 #define RX_CMPL_ERRORS_T_PKT_ERROR_TUNNEL_TOTAL_ERROR (0x3 << 9)
231 #define RX_CMPL_ERRORS_T_PKT_ERROR_T_IP_TOTAL_ERROR (0x4 << 9)
232 #define RX_CMPL_ERRORS_T_PKT_ERROR_T_UDP_TOTAL_ERROR (0x5 << 9)
233 #define RX_CMPL_ERRORS_T_PKT_ERROR_T_L3_BAD_TTL (0x6 << 9)
234 #define RX_CMPL_ERRORS_PKT_ERROR_MASK (0xf << 12)
235 #define RX_CMPL_ERRORS_PKT_ERROR_NO_ERROR (0x0 << 12)
236 #define RX_CMPL_ERRORS_PKT_ERROR_L3_BAD_VERSION (0x1 << 12)
237 #define RX_CMPL_ERRORS_PKT_ERROR_L3_BAD_HDR_LEN (0x2 << 12)
238 #define RX_CMPL_ERRORS_PKT_ERROR_L3_BAD_TTL (0x3 << 12)
239 #define RX_CMPL_ERRORS_PKT_ERROR_IP_TOTAL_ERROR (0x4 << 12)
240 #define RX_CMPL_ERRORS_PKT_ERROR_UDP_TOTAL_ERROR (0x5 << 12)
241 #define RX_CMPL_ERRORS_PKT_ERROR_L4_BAD_HDR_LEN (0x6 << 12)
242 #define RX_CMPL_ERRORS_PKT_ERROR_L4_BAD_HDR_LEN_TOO_SMALL (0x7 << 12)
243 #define RX_CMPL_ERRORS_PKT_ERROR_L4_BAD_OPT_LEN (0x8 << 12)
245 #define RX_CMPL_CFA_CODE_MASK (0xffff << 16)
246 #define RX_CMPL_CFA_CODE_SFT 16
248 __le32 rx_cmp_timestamp;
251 #define RX_CMP_L2_ERRORS \
252 cpu_to_le32(RX_CMPL_ERRORS_BUFFER_ERROR_MASK | RX_CMPL_ERRORS_CRC_ERROR)
254 #define RX_CMP_L4_CS_BITS \
255 (cpu_to_le32(RX_CMP_FLAGS2_L4_CS_CALC | RX_CMP_FLAGS2_T_L4_CS_CALC))
257 #define RX_CMP_L4_CS_ERR_BITS \
258 (cpu_to_le32(RX_CMPL_ERRORS_L4_CS_ERROR | RX_CMPL_ERRORS_T_L4_CS_ERROR))
260 #define RX_CMP_L4_CS_OK(rxcmp1) \
261 (((rxcmp1)->rx_cmp_flags2 & RX_CMP_L4_CS_BITS) && \
262 !((rxcmp1)->rx_cmp_cfa_code_errors_v2 & RX_CMP_L4_CS_ERR_BITS))
264 #define RX_CMP_ENCAP(rxcmp1) \
265 ((le32_to_cpu((rxcmp1)->rx_cmp_flags2) & \
266 RX_CMP_FLAGS2_T_L4_CS_CALC) >> 3)
268 #define RX_CMP_CFA_CODE(rxcmpl1) \
269 ((le32_to_cpu((rxcmpl1)->rx_cmp_cfa_code_errors_v2) & \
270 RX_CMPL_CFA_CODE_MASK) >> RX_CMPL_CFA_CODE_SFT)
273 __le32 rx_agg_cmp_len_flags_type;
274 #define RX_AGG_CMP_TYPE (0x3f << 0)
275 #define RX_AGG_CMP_LEN (0xffff << 16)
276 #define RX_AGG_CMP_LEN_SHIFT 16
277 u32 rx_agg_cmp_opaque;
279 #define RX_AGG_CMP_V (1 << 0)
280 #define RX_AGG_CMP_AGG_ID (0xffff << 16)
281 #define RX_AGG_CMP_AGG_ID_SHIFT 16
282 __le32 rx_agg_cmp_unused;
285 #define TPA_AGG_AGG_ID(rx_agg) \
286 ((le32_to_cpu((rx_agg)->rx_agg_cmp_v) & \
287 RX_AGG_CMP_AGG_ID) >> RX_AGG_CMP_AGG_ID_SHIFT)
289 struct rx_tpa_start_cmp {
290 __le32 rx_tpa_start_cmp_len_flags_type;
291 #define RX_TPA_START_CMP_TYPE (0x3f << 0)
292 #define RX_TPA_START_CMP_FLAGS (0x3ff << 6)
293 #define RX_TPA_START_CMP_FLAGS_SHIFT 6
294 #define RX_TPA_START_CMP_FLAGS_ERROR (0x1 << 6)
295 #define RX_TPA_START_CMP_FLAGS_PLACEMENT (0x7 << 7)
296 #define RX_TPA_START_CMP_FLAGS_PLACEMENT_SHIFT 7
297 #define RX_TPA_START_CMP_FLAGS_PLACEMENT_JUMBO (0x1 << 7)
298 #define RX_TPA_START_CMP_FLAGS_PLACEMENT_HDS (0x2 << 7)
299 #define RX_TPA_START_CMP_FLAGS_PLACEMENT_GRO_JUMBO (0x5 << 7)
300 #define RX_TPA_START_CMP_FLAGS_PLACEMENT_GRO_HDS (0x6 << 7)
301 #define RX_TPA_START_CMP_FLAGS_RSS_VALID (0x1 << 10)
302 #define RX_TPA_START_CMP_FLAGS_TIMESTAMP (0x1 << 11)
303 #define RX_TPA_START_CMP_FLAGS_ITYPES (0xf << 12)
304 #define RX_TPA_START_CMP_FLAGS_ITYPES_SHIFT 12
305 #define RX_TPA_START_CMP_FLAGS_ITYPE_TCP (0x2 << 12)
306 #define RX_TPA_START_CMP_LEN (0xffff << 16)
307 #define RX_TPA_START_CMP_LEN_SHIFT 16
309 u32 rx_tpa_start_cmp_opaque;
310 __le32 rx_tpa_start_cmp_misc_v1;
311 #define RX_TPA_START_CMP_V1 (0x1 << 0)
312 #define RX_TPA_START_CMP_RSS_HASH_TYPE (0x7f << 9)
313 #define RX_TPA_START_CMP_RSS_HASH_TYPE_SHIFT 9
314 #define RX_TPA_START_CMP_AGG_ID (0x7f << 25)
315 #define RX_TPA_START_CMP_AGG_ID_SHIFT 25
316 #define RX_TPA_START_CMP_AGG_ID_P5 (0xffff << 16)
317 #define RX_TPA_START_CMP_AGG_ID_SHIFT_P5 16
319 __le32 rx_tpa_start_cmp_rss_hash;
322 #define TPA_START_HASH_VALID(rx_tpa_start) \
323 ((rx_tpa_start)->rx_tpa_start_cmp_len_flags_type & \
324 cpu_to_le32(RX_TPA_START_CMP_FLAGS_RSS_VALID))
326 #define TPA_START_HASH_TYPE(rx_tpa_start) \
327 (((le32_to_cpu((rx_tpa_start)->rx_tpa_start_cmp_misc_v1) & \
328 RX_TPA_START_CMP_RSS_HASH_TYPE) >> \
329 RX_TPA_START_CMP_RSS_HASH_TYPE_SHIFT) & RSS_PROFILE_ID_MASK)
331 #define TPA_START_AGG_ID(rx_tpa_start) \
332 ((le32_to_cpu((rx_tpa_start)->rx_tpa_start_cmp_misc_v1) & \
333 RX_TPA_START_CMP_AGG_ID) >> RX_TPA_START_CMP_AGG_ID_SHIFT)
335 #define TPA_START_AGG_ID_P5(rx_tpa_start) \
336 ((le32_to_cpu((rx_tpa_start)->rx_tpa_start_cmp_misc_v1) & \
337 RX_TPA_START_CMP_AGG_ID_P5) >> RX_TPA_START_CMP_AGG_ID_SHIFT_P5)
339 #define TPA_START_ERROR(rx_tpa_start) \
340 ((rx_tpa_start)->rx_tpa_start_cmp_len_flags_type & \
341 cpu_to_le32(RX_TPA_START_CMP_FLAGS_ERROR))
343 struct rx_tpa_start_cmp_ext {
344 __le32 rx_tpa_start_cmp_flags2;
345 #define RX_TPA_START_CMP_FLAGS2_IP_CS_CALC (0x1 << 0)
346 #define RX_TPA_START_CMP_FLAGS2_L4_CS_CALC (0x1 << 1)
347 #define RX_TPA_START_CMP_FLAGS2_T_IP_CS_CALC (0x1 << 2)
348 #define RX_TPA_START_CMP_FLAGS2_T_L4_CS_CALC (0x1 << 3)
349 #define RX_TPA_START_CMP_FLAGS2_IP_TYPE (0x1 << 8)
350 #define RX_TPA_START_CMP_FLAGS2_CSUM_CMPL_VALID (0x1 << 9)
351 #define RX_TPA_START_CMP_FLAGS2_EXT_META_FORMAT (0x3 << 10)
352 #define RX_TPA_START_CMP_FLAGS2_EXT_META_FORMAT_SHIFT 10
353 #define RX_TPA_START_CMP_FLAGS2_CSUM_CMPL (0xffff << 16)
354 #define RX_TPA_START_CMP_FLAGS2_CSUM_CMPL_SHIFT 16
356 __le32 rx_tpa_start_cmp_metadata;
357 __le32 rx_tpa_start_cmp_cfa_code_v2;
358 #define RX_TPA_START_CMP_V2 (0x1 << 0)
359 #define RX_TPA_START_CMP_ERRORS_BUFFER_ERROR_MASK (0x7 << 1)
360 #define RX_TPA_START_CMP_ERRORS_BUFFER_ERROR_SHIFT 1
361 #define RX_TPA_START_CMP_ERRORS_BUFFER_ERROR_NO_BUFFER (0x0 << 1)
362 #define RX_TPA_START_CMP_ERRORS_BUFFER_ERROR_BAD_FORMAT (0x3 << 1)
363 #define RX_TPA_START_CMP_ERRORS_BUFFER_ERROR_FLUSH (0x5 << 1)
364 #define RX_TPA_START_CMP_CFA_CODE (0xffff << 16)
365 #define RX_TPA_START_CMPL_CFA_CODE_SHIFT 16
366 __le32 rx_tpa_start_cmp_hdr_info;
369 #define TPA_START_CFA_CODE(rx_tpa_start) \
370 ((le32_to_cpu((rx_tpa_start)->rx_tpa_start_cmp_cfa_code_v2) & \
371 RX_TPA_START_CMP_CFA_CODE) >> RX_TPA_START_CMPL_CFA_CODE_SHIFT)
373 #define TPA_START_IS_IPV6(rx_tpa_start) \
374 (!!((rx_tpa_start)->rx_tpa_start_cmp_flags2 & \
375 cpu_to_le32(RX_TPA_START_CMP_FLAGS2_IP_TYPE)))
377 #define TPA_START_ERROR_CODE(rx_tpa_start) \
378 ((le32_to_cpu((rx_tpa_start)->rx_tpa_start_cmp_cfa_code_v2) & \
379 RX_TPA_START_CMP_ERRORS_BUFFER_ERROR_MASK) >> \
380 RX_TPA_START_CMP_ERRORS_BUFFER_ERROR_SHIFT)
382 struct rx_tpa_end_cmp {
383 __le32 rx_tpa_end_cmp_len_flags_type;
384 #define RX_TPA_END_CMP_TYPE (0x3f << 0)
385 #define RX_TPA_END_CMP_FLAGS (0x3ff << 6)
386 #define RX_TPA_END_CMP_FLAGS_SHIFT 6
387 #define RX_TPA_END_CMP_FLAGS_PLACEMENT (0x7 << 7)
388 #define RX_TPA_END_CMP_FLAGS_PLACEMENT_SHIFT 7
389 #define RX_TPA_END_CMP_FLAGS_PLACEMENT_JUMBO (0x1 << 7)
390 #define RX_TPA_END_CMP_FLAGS_PLACEMENT_HDS (0x2 << 7)
391 #define RX_TPA_END_CMP_FLAGS_PLACEMENT_GRO_JUMBO (0x5 << 7)
392 #define RX_TPA_END_CMP_FLAGS_PLACEMENT_GRO_HDS (0x6 << 7)
393 #define RX_TPA_END_CMP_FLAGS_RSS_VALID (0x1 << 10)
394 #define RX_TPA_END_CMP_FLAGS_ITYPES (0xf << 12)
395 #define RX_TPA_END_CMP_FLAGS_ITYPES_SHIFT 12
396 #define RX_TPA_END_CMP_FLAGS_ITYPE_TCP (0x2 << 12)
397 #define RX_TPA_END_CMP_LEN (0xffff << 16)
398 #define RX_TPA_END_CMP_LEN_SHIFT 16
400 u32 rx_tpa_end_cmp_opaque;
401 __le32 rx_tpa_end_cmp_misc_v1;
402 #define RX_TPA_END_CMP_V1 (0x1 << 0)
403 #define RX_TPA_END_CMP_AGG_BUFS (0x3f << 1)
404 #define RX_TPA_END_CMP_AGG_BUFS_SHIFT 1
405 #define RX_TPA_END_CMP_TPA_SEGS (0xff << 8)
406 #define RX_TPA_END_CMP_TPA_SEGS_SHIFT 8
407 #define RX_TPA_END_CMP_PAYLOAD_OFFSET (0xff << 16)
408 #define RX_TPA_END_CMP_PAYLOAD_OFFSET_SHIFT 16
409 #define RX_TPA_END_CMP_AGG_ID (0x7f << 25)
410 #define RX_TPA_END_CMP_AGG_ID_SHIFT 25
411 #define RX_TPA_END_CMP_AGG_ID_P5 (0xffff << 16)
412 #define RX_TPA_END_CMP_AGG_ID_SHIFT_P5 16
414 __le32 rx_tpa_end_cmp_tsdelta;
415 #define RX_TPA_END_GRO_TS (0x1 << 31)
418 #define TPA_END_AGG_ID(rx_tpa_end) \
419 ((le32_to_cpu((rx_tpa_end)->rx_tpa_end_cmp_misc_v1) & \
420 RX_TPA_END_CMP_AGG_ID) >> RX_TPA_END_CMP_AGG_ID_SHIFT)
422 #define TPA_END_AGG_ID_P5(rx_tpa_end) \
423 ((le32_to_cpu((rx_tpa_end)->rx_tpa_end_cmp_misc_v1) & \
424 RX_TPA_END_CMP_AGG_ID_P5) >> RX_TPA_END_CMP_AGG_ID_SHIFT_P5)
426 #define TPA_END_PAYLOAD_OFF(rx_tpa_end) \
427 ((le32_to_cpu((rx_tpa_end)->rx_tpa_end_cmp_misc_v1) & \
428 RX_TPA_END_CMP_PAYLOAD_OFFSET) >> RX_TPA_END_CMP_PAYLOAD_OFFSET_SHIFT)
430 #define TPA_END_AGG_BUFS(rx_tpa_end) \
431 ((le32_to_cpu((rx_tpa_end)->rx_tpa_end_cmp_misc_v1) & \
432 RX_TPA_END_CMP_AGG_BUFS) >> RX_TPA_END_CMP_AGG_BUFS_SHIFT)
434 #define TPA_END_TPA_SEGS(rx_tpa_end) \
435 ((le32_to_cpu((rx_tpa_end)->rx_tpa_end_cmp_misc_v1) & \
436 RX_TPA_END_CMP_TPA_SEGS) >> RX_TPA_END_CMP_TPA_SEGS_SHIFT)
438 #define RX_TPA_END_CMP_FLAGS_PLACEMENT_ANY_GRO \
439 cpu_to_le32(RX_TPA_END_CMP_FLAGS_PLACEMENT_GRO_JUMBO & \
440 RX_TPA_END_CMP_FLAGS_PLACEMENT_GRO_HDS)
442 #define TPA_END_GRO(rx_tpa_end) \
443 ((rx_tpa_end)->rx_tpa_end_cmp_len_flags_type & \
444 RX_TPA_END_CMP_FLAGS_PLACEMENT_ANY_GRO)
446 #define TPA_END_GRO_TS(rx_tpa_end) \
447 (!!((rx_tpa_end)->rx_tpa_end_cmp_tsdelta & \
448 cpu_to_le32(RX_TPA_END_GRO_TS)))
450 struct rx_tpa_end_cmp_ext {
451 __le32 rx_tpa_end_cmp_dup_acks;
452 #define RX_TPA_END_CMP_TPA_DUP_ACKS (0xf << 0)
453 #define RX_TPA_END_CMP_PAYLOAD_OFFSET_P5 (0xff << 16)
454 #define RX_TPA_END_CMP_PAYLOAD_OFFSET_SHIFT_P5 16
455 #define RX_TPA_END_CMP_AGG_BUFS_P5 (0xff << 24)
456 #define RX_TPA_END_CMP_AGG_BUFS_SHIFT_P5 24
458 __le32 rx_tpa_end_cmp_seg_len;
459 #define RX_TPA_END_CMP_TPA_SEG_LEN (0xffff << 0)
461 __le32 rx_tpa_end_cmp_errors_v2;
462 #define RX_TPA_END_CMP_V2 (0x1 << 0)
463 #define RX_TPA_END_CMP_ERRORS (0x3 << 1)
464 #define RX_TPA_END_CMP_ERRORS_P5 (0x7 << 1)
465 #define RX_TPA_END_CMPL_ERRORS_SHIFT 1
466 #define RX_TPA_END_CMP_ERRORS_BUFFER_ERROR_NO_BUFFER (0x0 << 1)
467 #define RX_TPA_END_CMP_ERRORS_BUFFER_ERROR_NOT_ON_CHIP (0x2 << 1)
468 #define RX_TPA_END_CMP_ERRORS_BUFFER_ERROR_BAD_FORMAT (0x3 << 1)
469 #define RX_TPA_END_CMP_ERRORS_BUFFER_ERROR_RSV_ERROR (0x4 << 1)
470 #define RX_TPA_END_CMP_ERRORS_BUFFER_ERROR_FLUSH (0x5 << 1)
472 u32 rx_tpa_end_cmp_start_opaque;
475 #define TPA_END_ERRORS(rx_tpa_end_ext) \
476 ((rx_tpa_end_ext)->rx_tpa_end_cmp_errors_v2 & \
477 cpu_to_le32(RX_TPA_END_CMP_ERRORS))
479 #define TPA_END_PAYLOAD_OFF_P5(rx_tpa_end_ext) \
480 ((le32_to_cpu((rx_tpa_end_ext)->rx_tpa_end_cmp_dup_acks) & \
481 RX_TPA_END_CMP_PAYLOAD_OFFSET_P5) >> \
482 RX_TPA_END_CMP_PAYLOAD_OFFSET_SHIFT_P5)
484 #define TPA_END_AGG_BUFS_P5(rx_tpa_end_ext) \
485 ((le32_to_cpu((rx_tpa_end_ext)->rx_tpa_end_cmp_dup_acks) & \
486 RX_TPA_END_CMP_AGG_BUFS_P5) >> RX_TPA_END_CMP_AGG_BUFS_SHIFT_P5)
488 #define EVENT_DATA1_RESET_NOTIFY_FATAL(data1) \
490 ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_REASON_CODE_MASK) ==\
491 ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_REASON_CODE_FW_EXCEPTION_FATAL)
493 #define EVENT_DATA1_RESET_NOTIFY_FW_ACTIVATION(data1) \
495 ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_REASON_CODE_MASK) ==\
496 ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_REASON_CODE_FW_ACTIVATION)
498 #define EVENT_DATA2_RESET_NOTIFY_FW_STATUS_CODE(data2) \
500 ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA2_FW_STATUS_CODE_MASK)
502 #define EVENT_DATA1_RECOVERY_MASTER_FUNC(data1) \
504 ASYNC_EVENT_CMPL_ERROR_RECOVERY_EVENT_DATA1_FLAGS_MASTER_FUNC)
506 #define EVENT_DATA1_RECOVERY_ENABLED(data1) \
508 ASYNC_EVENT_CMPL_ERROR_RECOVERY_EVENT_DATA1_FLAGS_RECOVERY_ENABLED)
510 #define BNXT_EVENT_ERROR_REPORT_TYPE(data1) \
512 ASYNC_EVENT_CMPL_ERROR_REPORT_BASE_EVENT_DATA1_ERROR_TYPE_MASK) >>\
513 ASYNC_EVENT_CMPL_ERROR_REPORT_BASE_EVENT_DATA1_ERROR_TYPE_SFT)
515 #define BNXT_EVENT_INVALID_SIGNAL_DATA(data2) \
517 ASYNC_EVENT_CMPL_ERROR_REPORT_INVALID_SIGNAL_EVENT_DATA2_PIN_ID_MASK) >>\
518 ASYNC_EVENT_CMPL_ERROR_REPORT_INVALID_SIGNAL_EVENT_DATA2_PIN_ID_SFT)
522 #define NQ_CN_TYPE_MASK 0x3fUL
523 #define NQ_CN_TYPE_SFT 0
524 #define NQ_CN_TYPE_CQ_NOTIFICATION 0x30UL
525 #define NQ_CN_TYPE_LAST NQ_CN_TYPE_CQ_NOTIFICATION
527 __le32 cq_handle_low;
529 #define NQ_CN_V 0x1UL
530 __le32 cq_handle_high;
533 #define DB_IDX_MASK 0xffffff
534 #define DB_IDX_VALID (0x1 << 26)
535 #define DB_IRQ_DIS (0x1 << 27)
536 #define DB_KEY_TX (0x0 << 28)
537 #define DB_KEY_RX (0x1 << 28)
538 #define DB_KEY_CP (0x2 << 28)
539 #define DB_KEY_ST (0x3 << 28)
540 #define DB_KEY_TX_PUSH (0x4 << 28)
541 #define DB_LONG_TX_PUSH (0x2 << 24)
543 #define BNXT_MIN_ROCE_CP_RINGS 2
544 #define BNXT_MIN_ROCE_STAT_CTXS 1
546 /* 64-bit doorbell */
547 #define DBR_INDEX_MASK 0x0000000000ffffffULL
548 #define DBR_XID_MASK 0x000fffff00000000ULL
549 #define DBR_XID_SFT 32
550 #define DBR_PATH_L2 (0x1ULL << 56)
551 #define DBR_TYPE_SQ (0x0ULL << 60)
552 #define DBR_TYPE_RQ (0x1ULL << 60)
553 #define DBR_TYPE_SRQ (0x2ULL << 60)
554 #define DBR_TYPE_SRQ_ARM (0x3ULL << 60)
555 #define DBR_TYPE_CQ (0x4ULL << 60)
556 #define DBR_TYPE_CQ_ARMSE (0x5ULL << 60)
557 #define DBR_TYPE_CQ_ARMALL (0x6ULL << 60)
558 #define DBR_TYPE_CQ_ARMENA (0x7ULL << 60)
559 #define DBR_TYPE_SRQ_ARMENA (0x8ULL << 60)
560 #define DBR_TYPE_CQ_CUTOFF_ACK (0x9ULL << 60)
561 #define DBR_TYPE_NQ (0xaULL << 60)
562 #define DBR_TYPE_NQ_ARM (0xbULL << 60)
563 #define DBR_TYPE_NULL (0xfULL << 60)
565 #define DB_PF_OFFSET_P5 0x10000
566 #define DB_VF_OFFSET_P5 0x4000
568 #define INVALID_HW_RING_ID ((u16)-1)
570 /* The hardware supports certain page sizes. Use the supported page sizes
571 * to allocate the rings.
573 #if (PAGE_SHIFT < 12)
574 #define BNXT_PAGE_SHIFT 12
575 #elif (PAGE_SHIFT <= 13)
576 #define BNXT_PAGE_SHIFT PAGE_SHIFT
577 #elif (PAGE_SHIFT < 16)
578 #define BNXT_PAGE_SHIFT 13
580 #define BNXT_PAGE_SHIFT 16
583 #define BNXT_PAGE_SIZE (1 << BNXT_PAGE_SHIFT)
585 /* The RXBD length is 16-bit so we can only support page sizes < 64K */
586 #if (PAGE_SHIFT > 15)
587 #define BNXT_RX_PAGE_SHIFT 15
589 #define BNXT_RX_PAGE_SHIFT PAGE_SHIFT
592 #define BNXT_RX_PAGE_SIZE (1 << BNXT_RX_PAGE_SHIFT)
594 #define BNXT_MAX_MTU 9500
596 /* First RX buffer page in XDP multi-buf mode
598 * +-------------------------------------------------------------------------+
599 * | XDP_PACKET_HEADROOM | bp->rx_buf_use_size | skb_shared_info|
600 * | (bp->rx_dma_offset) | | |
601 * +-------------------------------------------------------------------------+
603 #define BNXT_MAX_PAGE_MODE_MTU_SBUF \
604 ((unsigned int)PAGE_SIZE - VLAN_ETH_HLEN - NET_IP_ALIGN - \
606 #define BNXT_MAX_PAGE_MODE_MTU \
607 (BNXT_MAX_PAGE_MODE_MTU_SBUF - \
608 SKB_DATA_ALIGN((unsigned int)sizeof(struct skb_shared_info)))
610 #define BNXT_MIN_PKT_SIZE 52
612 #define BNXT_DEFAULT_RX_RING_SIZE 511
613 #define BNXT_DEFAULT_TX_RING_SIZE 511
616 #define MAX_TPA_P5 256
617 #define MAX_TPA_P5_MASK (MAX_TPA_P5 - 1)
618 #define MAX_TPA_SEGS_P5 0x3f
620 #if (BNXT_PAGE_SHIFT == 16)
621 #define MAX_RX_PAGES_AGG_ENA 1
622 #define MAX_RX_PAGES 4
623 #define MAX_RX_AGG_PAGES 4
624 #define MAX_TX_PAGES 1
625 #define MAX_CP_PAGES 16
627 #define MAX_RX_PAGES_AGG_ENA 8
628 #define MAX_RX_PAGES 32
629 #define MAX_RX_AGG_PAGES 32
630 #define MAX_TX_PAGES 8
631 #define MAX_CP_PAGES 128
634 #define RX_DESC_CNT (BNXT_PAGE_SIZE / sizeof(struct rx_bd))
635 #define TX_DESC_CNT (BNXT_PAGE_SIZE / sizeof(struct tx_bd))
636 #define CP_DESC_CNT (BNXT_PAGE_SIZE / sizeof(struct tx_cmp))
638 #define SW_RXBD_RING_SIZE (sizeof(struct bnxt_sw_rx_bd) * RX_DESC_CNT)
639 #define HW_RXBD_RING_SIZE (sizeof(struct rx_bd) * RX_DESC_CNT)
641 #define SW_RXBD_AGG_RING_SIZE (sizeof(struct bnxt_sw_rx_agg_bd) * RX_DESC_CNT)
643 #define SW_TXBD_RING_SIZE (sizeof(struct bnxt_sw_tx_bd) * TX_DESC_CNT)
644 #define HW_TXBD_RING_SIZE (sizeof(struct tx_bd) * TX_DESC_CNT)
646 #define HW_CMPD_RING_SIZE (sizeof(struct tx_cmp) * CP_DESC_CNT)
648 #define BNXT_MAX_RX_DESC_CNT (RX_DESC_CNT * MAX_RX_PAGES - 1)
649 #define BNXT_MAX_RX_DESC_CNT_JUM_ENA (RX_DESC_CNT * MAX_RX_PAGES_AGG_ENA - 1)
650 #define BNXT_MAX_RX_JUM_DESC_CNT (RX_DESC_CNT * MAX_RX_AGG_PAGES - 1)
651 #define BNXT_MAX_TX_DESC_CNT (TX_DESC_CNT * MAX_TX_PAGES - 1)
653 /* Minimum TX BDs for a TX packet with MAX_SKB_FRAGS + 1. We need one extra
654 * BD because the first TX BD is always a long BD.
656 #define BNXT_MIN_TX_DESC_CNT (MAX_SKB_FRAGS + 2)
658 #define RX_RING(x) (((x) & ~(RX_DESC_CNT - 1)) >> (BNXT_PAGE_SHIFT - 4))
659 #define RX_IDX(x) ((x) & (RX_DESC_CNT - 1))
661 #define TX_RING(x) (((x) & ~(TX_DESC_CNT - 1)) >> (BNXT_PAGE_SHIFT - 4))
662 #define TX_IDX(x) ((x) & (TX_DESC_CNT - 1))
664 #define CP_RING(x) (((x) & ~(CP_DESC_CNT - 1)) >> (BNXT_PAGE_SHIFT - 4))
665 #define CP_IDX(x) ((x) & (CP_DESC_CNT - 1))
667 #define TX_CMP_VALID(txcmp, raw_cons) \
668 (!!((txcmp)->tx_cmp_errors_v & cpu_to_le32(TX_CMP_V)) == \
669 !((raw_cons) & bp->cp_bit))
671 #define RX_CMP_VALID(rxcmp1, raw_cons) \
672 (!!((rxcmp1)->rx_cmp_cfa_code_errors_v2 & cpu_to_le32(RX_CMP_V)) ==\
673 !((raw_cons) & bp->cp_bit))
675 #define RX_AGG_CMP_VALID(agg, raw_cons) \
676 (!!((agg)->rx_agg_cmp_v & cpu_to_le32(RX_AGG_CMP_V)) == \
677 !((raw_cons) & bp->cp_bit))
679 #define NQ_CMP_VALID(nqcmp, raw_cons) \
680 (!!((nqcmp)->v & cpu_to_le32(NQ_CN_V)) == !((raw_cons) & bp->cp_bit))
682 #define TX_CMP_TYPE(txcmp) \
683 (le32_to_cpu((txcmp)->tx_cmp_flags_type) & CMP_TYPE)
685 #define RX_CMP_TYPE(rxcmp) \
686 (le32_to_cpu((rxcmp)->rx_cmp_len_flags_type) & RX_CMP_CMP_TYPE)
688 #define NEXT_RX(idx) (((idx) + 1) & bp->rx_ring_mask)
690 #define NEXT_RX_AGG(idx) (((idx) + 1) & bp->rx_agg_ring_mask)
692 #define NEXT_TX(idx) (((idx) + 1) & bp->tx_ring_mask)
694 #define ADV_RAW_CMP(idx, n) ((idx) + (n))
695 #define NEXT_RAW_CMP(idx) ADV_RAW_CMP(idx, 1)
696 #define RING_CMP(idx) ((idx) & bp->cp_ring_mask)
697 #define NEXT_CMP(idx) RING_CMP(ADV_RAW_CMP(idx, 1))
699 #define DFLT_HWRM_CMD_TIMEOUT 500
701 #define BNXT_RX_EVENT 1
702 #define BNXT_AGG_EVENT 2
703 #define BNXT_TX_EVENT 4
704 #define BNXT_REDIRECT_EVENT 8
706 struct bnxt_sw_tx_bd {
709 struct xdp_frame *xdpf;
711 DEFINE_DMA_UNMAP_ADDR(mapping);
712 DEFINE_DMA_UNMAP_LEN(len);
717 unsigned short nr_frags;
721 struct bnxt_sw_rx_bd {
727 struct bnxt_sw_rx_agg_bd {
733 struct bnxt_mem_init {
736 #define BNXT_MEM_INVALID_OFFSET 0xffff
740 struct bnxt_ring_mem_info {
744 #define BNXT_RMEM_VALID_PTE_FLAG 1
745 #define BNXT_RMEM_RING_PTE_FLAG 2
746 #define BNXT_RMEM_USE_FULL_PAGE_FLAG 4
749 struct bnxt_mem_init *mem_init;
755 dma_addr_t pg_tbl_map;
761 struct bnxt_ring_struct {
762 struct bnxt_ring_mem_info ring_mem;
764 u16 fw_ring_id; /* Ring id filled by Chimp FW */
767 u16 map_idx; /* Used by cmpl rings */
775 __le32 tx_bd_len_flags_type;
777 struct tx_bd_ext txbd2;
780 struct tx_push_buffer {
781 struct tx_push_bd push_bd;
785 struct bnxt_db_info {
786 void __iomem *doorbell;
793 struct bnxt_tx_ring_info {
794 struct bnxt_napi *bnapi;
799 struct bnxt_db_info tx_db;
801 struct tx_bd *tx_desc_ring[MAX_TX_PAGES];
802 struct bnxt_sw_tx_bd *tx_buf_ring;
804 dma_addr_t tx_desc_mapping[MAX_TX_PAGES];
806 struct tx_push_buffer *tx_push;
807 dma_addr_t tx_push_mapping;
810 #define BNXT_DEV_STATE_CLOSING 0x1
813 struct bnxt_ring_struct tx_ring_struct;
814 /* Synchronize simultaneous xdp_xmit on same ring */
815 spinlock_t xdp_tx_lock;
818 #define BNXT_LEGACY_COAL_CMPL_PARAMS \
819 (RING_AGGINT_QCAPS_RESP_CMPL_PARAMS_INT_LAT_TMR_MIN | \
820 RING_AGGINT_QCAPS_RESP_CMPL_PARAMS_INT_LAT_TMR_MAX | \
821 RING_AGGINT_QCAPS_RESP_CMPL_PARAMS_TIMER_RESET | \
822 RING_AGGINT_QCAPS_RESP_CMPL_PARAMS_RING_IDLE | \
823 RING_AGGINT_QCAPS_RESP_CMPL_PARAMS_NUM_CMPL_DMA_AGGR | \
824 RING_AGGINT_QCAPS_RESP_CMPL_PARAMS_NUM_CMPL_DMA_AGGR_DURING_INT | \
825 RING_AGGINT_QCAPS_RESP_CMPL_PARAMS_CMPL_AGGR_DMA_TMR | \
826 RING_AGGINT_QCAPS_RESP_CMPL_PARAMS_CMPL_AGGR_DMA_TMR_DURING_INT | \
827 RING_AGGINT_QCAPS_RESP_CMPL_PARAMS_NUM_CMPL_AGGR_INT)
829 #define BNXT_COAL_CMPL_ENABLES \
830 (RING_CMPL_RING_CFG_AGGINT_PARAMS_REQ_ENABLES_NUM_CMPL_DMA_AGGR | \
831 RING_CMPL_RING_CFG_AGGINT_PARAMS_REQ_ENABLES_CMPL_AGGR_DMA_TMR | \
832 RING_CMPL_RING_CFG_AGGINT_PARAMS_REQ_ENABLES_INT_LAT_TMR_MAX | \
833 RING_CMPL_RING_CFG_AGGINT_PARAMS_REQ_ENABLES_NUM_CMPL_AGGR_INT)
835 #define BNXT_COAL_CMPL_MIN_TMR_ENABLE \
836 RING_CMPL_RING_CFG_AGGINT_PARAMS_REQ_ENABLES_INT_LAT_TMR_MIN
838 #define BNXT_COAL_CMPL_AGGR_TMR_DURING_INT_ENABLE \
839 RING_CMPL_RING_CFG_AGGINT_PARAMS_REQ_ENABLES_NUM_CMPL_DMA_AGGR_DURING_INT
841 struct bnxt_coal_cap {
844 u16 num_cmpl_dma_aggr_max;
845 u16 num_cmpl_dma_aggr_during_int_max;
846 u16 cmpl_aggr_dma_tmr_max;
847 u16 cmpl_aggr_dma_tmr_during_int_max;
848 u16 int_lat_tmr_min_max;
849 u16 int_lat_tmr_max_max;
850 u16 num_cmpl_aggr_int_max;
859 /* RING_IDLE enabled when coal ticks < idle_thresh */
866 struct bnxt_tpa_info {
871 unsigned short gso_type;
874 enum pkt_hash_types hash_type;
878 #define BNXT_TPA_L4_SIZE(hdr_info) \
879 (((hdr_info) & 0xf8000000) ? ((hdr_info) >> 27) : 32)
881 #define BNXT_TPA_INNER_L3_OFF(hdr_info) \
882 (((hdr_info) >> 18) & 0x1ff)
884 #define BNXT_TPA_INNER_L2_OFF(hdr_info) \
885 (((hdr_info) >> 9) & 0x1ff)
887 #define BNXT_TPA_OUTER_L3_OFF(hdr_info) \
890 u16 cfa_code; /* cfa_code in TPA start compl */
892 struct rx_agg_cmp *agg_arr;
895 #define BNXT_AGG_IDX_BMAP_SIZE (MAX_TPA_P5 / BITS_PER_LONG)
897 struct bnxt_tpa_idx_map {
898 u16 agg_id_tbl[1024];
899 unsigned long agg_idx_bmap[BNXT_AGG_IDX_BMAP_SIZE];
902 struct bnxt_rx_ring_info {
903 struct bnxt_napi *bnapi;
908 struct bnxt_db_info rx_db;
909 struct bnxt_db_info rx_agg_db;
911 struct bpf_prog *xdp_prog;
913 struct rx_bd *rx_desc_ring[MAX_RX_PAGES];
914 struct bnxt_sw_rx_bd *rx_buf_ring;
916 struct rx_bd *rx_agg_desc_ring[MAX_RX_AGG_PAGES];
917 struct bnxt_sw_rx_agg_bd *rx_agg_ring;
919 unsigned long *rx_agg_bmap;
920 u16 rx_agg_bmap_size;
922 dma_addr_t rx_desc_mapping[MAX_RX_PAGES];
923 dma_addr_t rx_agg_desc_mapping[MAX_RX_AGG_PAGES];
925 struct bnxt_tpa_info *rx_tpa;
926 struct bnxt_tpa_idx_map *rx_tpa_idx_map;
928 struct bnxt_ring_struct rx_ring_struct;
929 struct bnxt_ring_struct rx_agg_ring_struct;
930 struct xdp_rxq_info xdp_rxq;
931 struct page_pool *page_pool;
934 struct bnxt_rx_sw_stats {
935 u64 rx_l4_csum_errors;
939 u64 rx_netpoll_discards;
942 struct bnxt_cmn_sw_stats {
946 struct bnxt_sw_stats {
947 struct bnxt_rx_sw_stats rx;
948 struct bnxt_cmn_sw_stats cmn;
951 struct bnxt_total_ring_err_stats {
952 u64 rx_total_l4_csum_errors;
954 u64 rx_total_buf_errors;
955 u64 rx_total_oom_discards;
956 u64 rx_total_netpoll_discards;
957 u64 rx_total_ring_discards;
958 u64 tx_total_ring_discards;
959 u64 total_missed_irqs;
962 struct bnxt_stats_mem {
966 dma_addr_t hw_stats_map;
970 struct bnxt_cp_ring_info {
971 struct bnxt_napi *bnapi;
973 struct bnxt_db_info cp_db;
978 u32 last_cp_raw_cons;
980 struct bnxt_coal rx_ring_coal;
988 struct tx_cmp **cp_desc_ring;
989 struct nqe_cn **nq_desc_ring;
992 dma_addr_t *cp_desc_mapping;
994 struct bnxt_stats_mem stats;
997 struct bnxt_sw_stats sw_stats;
999 struct bnxt_ring_struct cp_ring_struct;
1001 struct bnxt_cp_ring_info *cp_ring_arr[2];
1002 #define BNXT_RX_HDL 0
1003 #define BNXT_TX_HDL 1
1007 struct napi_struct napi;
1011 struct bnxt_cp_ring_info cp_ring;
1012 struct bnxt_rx_ring_info *rx_ring;
1013 struct bnxt_tx_ring_info *tx_ring;
1015 void (*tx_int)(struct bnxt *, struct bnxt_napi *,
1022 #define BNXT_NAPI_FLAG_XDP 0x1
1028 irq_handler_t handler;
1029 unsigned int vector;
1032 char name[IFNAMSIZ + 2];
1033 cpumask_var_t cpu_mask;
1036 #define HWRM_RING_ALLOC_TX 0x1
1037 #define HWRM_RING_ALLOC_RX 0x2
1038 #define HWRM_RING_ALLOC_AGG 0x4
1039 #define HWRM_RING_ALLOC_CMPL 0x8
1040 #define HWRM_RING_ALLOC_NQ 0x10
1042 #define INVALID_STATS_CTX_ID -1
1044 struct bnxt_ring_grp_info {
1052 struct bnxt_vnic_info {
1053 u16 fw_vnic_id; /* returned by Chimp during alloc */
1054 #define BNXT_MAX_CTX_PER_VNIC 8
1055 u16 fw_rss_cos_lb_ctx[BNXT_MAX_CTX_PER_VNIC];
1057 #define BNXT_MAX_UC_ADDRS 4
1058 __le64 fw_l2_filter_id[BNXT_MAX_UC_ADDRS];
1059 /* index 0 always dev_addr */
1060 u16 uc_filter_count;
1064 dma_addr_t rss_table_dma_addr;
1066 dma_addr_t rss_hash_key_dma_addr;
1069 #define BNXT_RSS_TABLE_ENTRIES_P5 64
1070 #define BNXT_RSS_TABLE_SIZE_P5 (BNXT_RSS_TABLE_ENTRIES_P5 * 4)
1071 #define BNXT_RSS_TABLE_MAX_TBL_P5 8
1072 #define BNXT_MAX_RSS_TABLE_SIZE_P5 \
1073 (BNXT_RSS_TABLE_SIZE_P5 * BNXT_RSS_TABLE_MAX_TBL_P5)
1074 #define BNXT_MAX_RSS_TABLE_ENTRIES_P5 \
1075 (BNXT_RSS_TABLE_ENTRIES_P5 * BNXT_RSS_TABLE_MAX_TBL_P5)
1082 dma_addr_t mc_list_mapping;
1083 #define BNXT_MAX_MC_ADDRS 16
1086 #define BNXT_VNIC_RSS_FLAG 1
1087 #define BNXT_VNIC_RFS_FLAG 2
1088 #define BNXT_VNIC_MCAST_FLAG 4
1089 #define BNXT_VNIC_UCAST_FLAG 8
1090 #define BNXT_VNIC_RFS_NEW_RSS_FLAG 0x10
1093 struct bnxt_hw_resc {
1094 u16 min_rsscos_ctxs;
1095 u16 max_rsscos_ctxs;
1102 u16 max_tx_sch_inputs;
1106 u16 min_hw_ring_grps;
1107 u16 max_hw_ring_grps;
1108 u16 resv_hw_ring_grps;
1122 #if defined(CONFIG_BNXT_SRIOV)
1123 struct bnxt_vf_info {
1125 u8 mac_addr[ETH_ALEN]; /* PF assigned MAC Address */
1126 u8 vf_mac_addr[ETH_ALEN]; /* VF assigned MAC address, only
1130 u16 func_qcfg_flags;
1132 #define BNXT_VF_QOS 0x1
1133 #define BNXT_VF_SPOOFCHK 0x2
1134 #define BNXT_VF_LINK_FORCED 0x4
1135 #define BNXT_VF_LINK_UP 0x8
1136 #define BNXT_VF_TRUST 0x10
1139 void *hwrm_cmd_req_addr;
1140 dma_addr_t hwrm_cmd_req_dma_addr;
1144 struct bnxt_pf_info {
1145 #define BNXT_FIRST_PF_FID 1
1146 #define BNXT_FIRST_VF_FID 128
1149 u8 mac_addr[ETH_ALEN];
1154 u32 max_encap_records;
1155 u32 max_decap_records;
1156 u32 max_tx_em_flows;
1157 u32 max_tx_wm_flows;
1158 u32 max_rx_em_flows;
1159 u32 max_rx_wm_flows;
1160 unsigned long *vf_event_bmap;
1161 u16 hwrm_cmd_req_pages;
1162 u8 vf_resv_strategy;
1163 #define BNXT_VF_RESV_STRATEGY_MAXIMAL 0
1164 #define BNXT_VF_RESV_STRATEGY_MINIMAL 1
1165 #define BNXT_VF_RESV_STRATEGY_MINIMAL_STATIC 2
1166 void *hwrm_cmd_req_addr[4];
1167 dma_addr_t hwrm_cmd_req_dma_addr[4];
1168 struct bnxt_vf_info *vf;
1171 struct bnxt_ntuple_filter {
1172 struct hlist_node hash;
1173 u8 dst_mac_addr[ETH_ALEN];
1174 u8 src_mac_addr[ETH_ALEN];
1175 struct flow_keys fkeys;
1181 unsigned long state;
1182 #define BNXT_FLTR_VALID 0
1183 #define BNXT_FLTR_UPDATE 1
1186 struct bnxt_link_info {
1192 #define BNXT_LINK_NO_LINK PORT_PHY_QCFG_RESP_LINK_NO_LINK
1193 #define BNXT_LINK_SIGNAL PORT_PHY_QCFG_RESP_LINK_SIGNAL
1194 #define BNXT_LINK_LINK PORT_PHY_QCFG_RESP_LINK_LINK
1197 #define BNXT_PHY_STATE_ENABLED 0
1198 #define BNXT_PHY_STATE_DISABLED 1
1201 #define BNXT_LINK_STATE_UNKNOWN 0
1202 #define BNXT_LINK_STATE_DOWN 1
1203 #define BNXT_LINK_STATE_UP 2
1204 #define BNXT_LINK_IS_UP(bp) ((bp)->link_info.link_state == BNXT_LINK_STATE_UP)
1206 #define BNXT_LINK_DUPLEX_HALF PORT_PHY_QCFG_RESP_DUPLEX_STATE_HALF
1207 #define BNXT_LINK_DUPLEX_FULL PORT_PHY_QCFG_RESP_DUPLEX_STATE_FULL
1209 #define BNXT_LINK_PAUSE_TX PORT_PHY_QCFG_RESP_PAUSE_TX
1210 #define BNXT_LINK_PAUSE_RX PORT_PHY_QCFG_RESP_PAUSE_RX
1211 #define BNXT_LINK_PAUSE_BOTH (PORT_PHY_QCFG_RESP_PAUSE_RX | \
1212 PORT_PHY_QCFG_RESP_PAUSE_TX)
1214 u8 auto_pause_setting;
1215 u8 force_pause_setting;
1218 #define BNXT_AUTO_MODE(mode) ((mode) > BNXT_LINK_AUTO_NONE && \
1219 (mode) <= BNXT_LINK_AUTO_MSK)
1220 #define BNXT_LINK_AUTO_NONE PORT_PHY_QCFG_RESP_AUTO_MODE_NONE
1221 #define BNXT_LINK_AUTO_ALLSPDS PORT_PHY_QCFG_RESP_AUTO_MODE_ALL_SPEEDS
1222 #define BNXT_LINK_AUTO_ONESPD PORT_PHY_QCFG_RESP_AUTO_MODE_ONE_SPEED
1223 #define BNXT_LINK_AUTO_ONEORBELOW PORT_PHY_QCFG_RESP_AUTO_MODE_ONE_OR_BELOW
1224 #define BNXT_LINK_AUTO_MSK PORT_PHY_QCFG_RESP_AUTO_MODE_SPEED_MASK
1225 #define PHY_VER_LEN 3
1226 u8 phy_ver[PHY_VER_LEN];
1228 #define BNXT_LINK_SPEED_100MB PORT_PHY_QCFG_RESP_LINK_SPEED_100MB
1229 #define BNXT_LINK_SPEED_1GB PORT_PHY_QCFG_RESP_LINK_SPEED_1GB
1230 #define BNXT_LINK_SPEED_2GB PORT_PHY_QCFG_RESP_LINK_SPEED_2GB
1231 #define BNXT_LINK_SPEED_2_5GB PORT_PHY_QCFG_RESP_LINK_SPEED_2_5GB
1232 #define BNXT_LINK_SPEED_10GB PORT_PHY_QCFG_RESP_LINK_SPEED_10GB
1233 #define BNXT_LINK_SPEED_20GB PORT_PHY_QCFG_RESP_LINK_SPEED_20GB
1234 #define BNXT_LINK_SPEED_25GB PORT_PHY_QCFG_RESP_LINK_SPEED_25GB
1235 #define BNXT_LINK_SPEED_40GB PORT_PHY_QCFG_RESP_LINK_SPEED_40GB
1236 #define BNXT_LINK_SPEED_50GB PORT_PHY_QCFG_RESP_LINK_SPEED_50GB
1237 #define BNXT_LINK_SPEED_100GB PORT_PHY_QCFG_RESP_LINK_SPEED_100GB
1238 #define BNXT_LINK_SPEED_200GB PORT_PHY_QCFG_RESP_LINK_SPEED_200GB
1240 u16 support_pam4_speeds;
1241 u16 auto_link_speeds; /* fw adv setting */
1242 #define BNXT_LINK_SPEED_MSK_100MB PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_100MB
1243 #define BNXT_LINK_SPEED_MSK_1GB PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_1GB
1244 #define BNXT_LINK_SPEED_MSK_2GB PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_2GB
1245 #define BNXT_LINK_SPEED_MSK_10GB PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_10GB
1246 #define BNXT_LINK_SPEED_MSK_2_5GB PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_2_5GB
1247 #define BNXT_LINK_SPEED_MSK_20GB PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_20GB
1248 #define BNXT_LINK_SPEED_MSK_25GB PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_25GB
1249 #define BNXT_LINK_SPEED_MSK_40GB PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_40GB
1250 #define BNXT_LINK_SPEED_MSK_50GB PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_50GB
1251 #define BNXT_LINK_SPEED_MSK_100GB PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_100GB
1252 u16 auto_pam4_link_speeds;
1253 #define BNXT_LINK_PAM4_SPEED_MSK_50GB PORT_PHY_QCFG_RESP_SUPPORT_PAM4_SPEEDS_50G
1254 #define BNXT_LINK_PAM4_SPEED_MSK_100GB PORT_PHY_QCFG_RESP_SUPPORT_PAM4_SPEEDS_100G
1255 #define BNXT_LINK_PAM4_SPEED_MSK_200GB PORT_PHY_QCFG_RESP_SUPPORT_PAM4_SPEEDS_200G
1256 u16 support_auto_speeds;
1257 u16 support_pam4_auto_speeds;
1258 u16 lp_auto_link_speeds;
1259 u16 lp_auto_pam4_link_speeds;
1260 u16 force_link_speed;
1261 u16 force_pam4_link_speed;
1264 u8 active_fec_sig_mode;
1266 #define BNXT_FEC_NONE PORT_PHY_QCFG_RESP_FEC_CFG_FEC_NONE_SUPPORTED
1267 #define BNXT_FEC_AUTONEG_CAP PORT_PHY_QCFG_RESP_FEC_CFG_FEC_AUTONEG_SUPPORTED
1268 #define BNXT_FEC_AUTONEG PORT_PHY_QCFG_RESP_FEC_CFG_FEC_AUTONEG_ENABLED
1269 #define BNXT_FEC_ENC_BASE_R_CAP \
1270 PORT_PHY_QCFG_RESP_FEC_CFG_FEC_CLAUSE74_SUPPORTED
1271 #define BNXT_FEC_ENC_BASE_R PORT_PHY_QCFG_RESP_FEC_CFG_FEC_CLAUSE74_ENABLED
1272 #define BNXT_FEC_ENC_RS_CAP \
1273 PORT_PHY_QCFG_RESP_FEC_CFG_FEC_CLAUSE91_SUPPORTED
1274 #define BNXT_FEC_ENC_LLRS_CAP \
1275 (PORT_PHY_QCFG_RESP_FEC_CFG_FEC_RS272_1XN_SUPPORTED | \
1276 PORT_PHY_QCFG_RESP_FEC_CFG_FEC_RS272_IEEE_SUPPORTED)
1277 #define BNXT_FEC_ENC_RS \
1278 (PORT_PHY_QCFG_RESP_FEC_CFG_FEC_CLAUSE91_ENABLED | \
1279 PORT_PHY_QCFG_RESP_FEC_CFG_FEC_RS544_1XN_ENABLED | \
1280 PORT_PHY_QCFG_RESP_FEC_CFG_FEC_RS544_IEEE_ENABLED)
1281 #define BNXT_FEC_ENC_LLRS \
1282 (PORT_PHY_QCFG_RESP_FEC_CFG_FEC_RS272_1XN_ENABLED | \
1283 PORT_PHY_QCFG_RESP_FEC_CFG_FEC_RS272_IEEE_ENABLED)
1285 /* copy of requested setting from ethtool cmd */
1287 #define BNXT_AUTONEG_SPEED 1
1288 #define BNXT_AUTONEG_FLOW_CTRL 2
1290 #define BNXT_SIG_MODE_NRZ PORT_PHY_QCFG_RESP_SIGNAL_MODE_NRZ
1291 #define BNXT_SIG_MODE_PAM4 PORT_PHY_QCFG_RESP_SIGNAL_MODE_PAM4
1295 u16 advertising; /* user adv setting */
1296 u16 advertising_pam4;
1297 bool force_link_chng;
1300 unsigned long phy_retry_expires;
1302 /* a copy of phy_qcfg output used to report link
1305 struct hwrm_port_phy_qcfg_output phy_qcfg_resp;
1308 #define BNXT_FEC_RS544_ON \
1309 (PORT_PHY_CFG_REQ_FLAGS_FEC_RS544_1XN_ENABLE | \
1310 PORT_PHY_CFG_REQ_FLAGS_FEC_RS544_IEEE_ENABLE)
1312 #define BNXT_FEC_RS544_OFF \
1313 (PORT_PHY_CFG_REQ_FLAGS_FEC_RS544_1XN_DISABLE | \
1314 PORT_PHY_CFG_REQ_FLAGS_FEC_RS544_IEEE_DISABLE)
1316 #define BNXT_FEC_RS272_ON \
1317 (PORT_PHY_CFG_REQ_FLAGS_FEC_RS272_1XN_ENABLE | \
1318 PORT_PHY_CFG_REQ_FLAGS_FEC_RS272_IEEE_ENABLE)
1320 #define BNXT_FEC_RS272_OFF \
1321 (PORT_PHY_CFG_REQ_FLAGS_FEC_RS272_1XN_DISABLE | \
1322 PORT_PHY_CFG_REQ_FLAGS_FEC_RS272_IEEE_DISABLE)
1324 #define BNXT_PAM4_SUPPORTED(link_info) \
1325 ((link_info)->support_pam4_speeds)
1327 #define BNXT_FEC_RS_ON(link_info) \
1328 (PORT_PHY_CFG_REQ_FLAGS_FEC_CLAUSE91_ENABLE | \
1329 PORT_PHY_CFG_REQ_FLAGS_FEC_CLAUSE74_DISABLE | \
1330 (BNXT_PAM4_SUPPORTED(link_info) ? \
1331 (BNXT_FEC_RS544_ON | BNXT_FEC_RS272_OFF) : 0))
1333 #define BNXT_FEC_LLRS_ON \
1334 (PORT_PHY_CFG_REQ_FLAGS_FEC_CLAUSE91_ENABLE | \
1335 PORT_PHY_CFG_REQ_FLAGS_FEC_CLAUSE74_DISABLE | \
1336 BNXT_FEC_RS272_ON | BNXT_FEC_RS544_OFF)
1338 #define BNXT_FEC_RS_OFF(link_info) \
1339 (PORT_PHY_CFG_REQ_FLAGS_FEC_CLAUSE91_DISABLE | \
1340 (BNXT_PAM4_SUPPORTED(link_info) ? \
1341 (BNXT_FEC_RS544_OFF | BNXT_FEC_RS272_OFF) : 0))
1343 #define BNXT_FEC_BASE_R_ON(link_info) \
1344 (PORT_PHY_CFG_REQ_FLAGS_FEC_CLAUSE74_ENABLE | \
1345 BNXT_FEC_RS_OFF(link_info))
1347 #define BNXT_FEC_ALL_OFF(link_info) \
1348 (PORT_PHY_CFG_REQ_FLAGS_FEC_CLAUSE74_DISABLE | \
1349 BNXT_FEC_RS_OFF(link_info))
1351 #define BNXT_MAX_QUEUE 8
1353 struct bnxt_queue_info {
1358 #define BNXT_MAX_LED 4
1360 struct bnxt_led_info {
1365 __le16 led_state_caps;
1366 #define BNXT_LED_ALT_BLINK_CAP(x) ((x) & \
1367 cpu_to_le16(PORT_LED_QCAPS_RESP_LED0_STATE_CAPS_BLINK_ALT_SUPPORTED))
1369 __le16 led_color_caps;
1372 #define BNXT_MAX_TEST 8
1374 struct bnxt_test_info {
1377 char string[BNXT_MAX_TEST][ETH_GSTRING_LEN];
1380 #define CHIMP_REG_VIEW_ADDR \
1381 ((bp->flags & BNXT_FLAG_CHIP_P5) ? 0x80000000 : 0xb1000000)
1383 #define BNXT_GRCPF_REG_CHIMP_COMM 0x0
1384 #define BNXT_GRCPF_REG_CHIMP_COMM_TRIGGER 0x100
1385 #define BNXT_GRCPF_REG_WINDOW_BASE_OUT 0x400
1386 #define BNXT_CAG_REG_LEGACY_INT_STATUS 0x4014
1387 #define BNXT_CAG_REG_BASE 0x300000
1389 #define BNXT_GRC_REG_STATUS_P5 0x520
1391 #define BNXT_GRCPF_REG_KONG_COMM 0xA00
1392 #define BNXT_GRCPF_REG_KONG_COMM_TRIGGER 0xB00
1394 #define BNXT_GRC_REG_CHIP_NUM 0x48
1395 #define BNXT_GRC_REG_BASE 0x260000
1397 #define BNXT_TS_REG_TIMESYNC_TS0_LOWER 0x640180c
1398 #define BNXT_TS_REG_TIMESYNC_TS0_UPPER 0x6401810
1400 #define BNXT_GRC_BASE_MASK 0xfffff000
1401 #define BNXT_GRC_OFFSET_MASK 0x00000ffc
1403 struct bnxt_tc_flow_stats {
1408 #ifdef CONFIG_BNXT_FLOWER_OFFLOAD
1409 struct bnxt_flower_indr_block_cb_priv {
1410 struct net_device *tunnel_netdev;
1412 struct list_head list;
1416 struct bnxt_tc_info {
1419 /* hash table to store TC offloaded flows */
1420 struct rhashtable flow_table;
1421 struct rhashtable_params flow_ht_params;
1423 /* hash table to store L2 keys of TC flows */
1424 struct rhashtable l2_table;
1425 struct rhashtable_params l2_ht_params;
1426 /* hash table to store L2 keys for TC tunnel decap */
1427 struct rhashtable decap_l2_table;
1428 struct rhashtable_params decap_l2_ht_params;
1429 /* hash table to store tunnel decap entries */
1430 struct rhashtable decap_table;
1431 struct rhashtable_params decap_ht_params;
1432 /* hash table to store tunnel encap entries */
1433 struct rhashtable encap_table;
1434 struct rhashtable_params encap_ht_params;
1436 /* lock to atomically add/del an l2 node when a flow is
1441 /* Fields used for batching stats query */
1442 struct rhashtable_iter iter;
1443 #define BNXT_FLOW_STATS_BATCH_MAX 10
1444 struct bnxt_tc_stats_batch {
1446 struct bnxt_tc_flow_stats hw_stats;
1447 } stats_batch[BNXT_FLOW_STATS_BATCH_MAX];
1449 /* Stat counter mask (width) */
1454 struct bnxt_vf_rep_stats {
1460 struct bnxt_vf_rep {
1462 struct net_device *dev;
1463 struct metadata_dst *dst;
1468 struct bnxt_vf_rep_stats rx_stats;
1469 struct bnxt_vf_rep_stats tx_stats;
1472 #define PTU_PTE_VALID 0x1UL
1473 #define PTU_PTE_LAST 0x2UL
1474 #define PTU_PTE_NEXT_TO_LAST 0x4UL
1476 #define MAX_CTX_PAGES (BNXT_PAGE_SIZE / 8)
1477 #define MAX_CTX_TOTAL_PAGES (MAX_CTX_PAGES * MAX_CTX_PAGES)
1479 struct bnxt_ctx_pg_info {
1482 void *ctx_pg_arr[MAX_CTX_PAGES];
1483 dma_addr_t ctx_dma_arr[MAX_CTX_PAGES];
1484 struct bnxt_ring_mem_info ring_mem;
1485 struct bnxt_ctx_pg_info **ctx_pg_tbl;
1488 #define BNXT_MAX_TQM_SP_RINGS 1
1489 #define BNXT_MAX_TQM_FP_RINGS 8
1490 #define BNXT_MAX_TQM_RINGS \
1491 (BNXT_MAX_TQM_SP_RINGS + BNXT_MAX_TQM_FP_RINGS)
1493 #define BNXT_BACKING_STORE_CFG_LEGACY_LEN 256
1495 #define BNXT_SET_CTX_PAGE_ATTR(attr) \
1497 if (BNXT_PAGE_SIZE == 0x2000) \
1498 attr = FUNC_BACKING_STORE_CFG_REQ_SRQ_PG_SIZE_PG_8K; \
1499 else if (BNXT_PAGE_SIZE == 0x10000) \
1500 attr = FUNC_BACKING_STORE_CFG_REQ_QPC_PG_SIZE_PG_64K; \
1502 attr = FUNC_BACKING_STORE_CFG_REQ_QPC_PG_SIZE_PG_4K; \
1505 struct bnxt_ctx_mem_info {
1507 u16 qp_min_qp1_entries;
1508 u16 qp_max_l2_entries;
1510 u16 srq_max_l2_entries;
1511 u32 srq_max_entries;
1513 u16 cq_max_l2_entries;
1516 u16 vnic_max_vnic_entries;
1517 u16 vnic_max_ring_table_entries;
1518 u16 vnic_entry_size;
1519 u32 stat_max_entries;
1520 u16 stat_entry_size;
1522 u32 tqm_min_entries_per_ring;
1523 u32 tqm_max_entries_per_ring;
1524 u32 mrav_max_entries;
1525 u16 mrav_entry_size;
1527 u32 tim_max_entries;
1528 u16 mrav_num_entries_units;
1529 u8 tqm_entries_multiple;
1530 u8 tqm_fp_rings_count;
1533 #define BNXT_CTX_FLAG_INITED 0x01
1535 struct bnxt_ctx_pg_info qp_mem;
1536 struct bnxt_ctx_pg_info srq_mem;
1537 struct bnxt_ctx_pg_info cq_mem;
1538 struct bnxt_ctx_pg_info vnic_mem;
1539 struct bnxt_ctx_pg_info stat_mem;
1540 struct bnxt_ctx_pg_info mrav_mem;
1541 struct bnxt_ctx_pg_info tim_mem;
1542 struct bnxt_ctx_pg_info *tqm_mem[BNXT_MAX_TQM_RINGS];
1544 #define BNXT_CTX_MEM_INIT_QP 0
1545 #define BNXT_CTX_MEM_INIT_SRQ 1
1546 #define BNXT_CTX_MEM_INIT_CQ 2
1547 #define BNXT_CTX_MEM_INIT_VNIC 3
1548 #define BNXT_CTX_MEM_INIT_STAT 4
1549 #define BNXT_CTX_MEM_INIT_MRAV 5
1550 #define BNXT_CTX_MEM_INIT_MAX 6
1551 struct bnxt_mem_init mem_init[BNXT_CTX_MEM_INIT_MAX];
1554 enum bnxt_health_severity {
1555 SEVERITY_NORMAL = 0,
1557 SEVERITY_RECOVERABLE,
1561 enum bnxt_health_remedy {
1562 REMEDY_DEVLINK_RECOVER,
1563 REMEDY_POWER_CYCLE_DEVICE,
1564 REMEDY_POWER_CYCLE_HOST,
1569 struct bnxt_fw_health {
1572 u32 master_func_wait_dsecs;
1573 u32 normal_func_wait_dsecs;
1574 u32 post_reset_wait_dsecs;
1575 u32 post_reset_max_wait_dsecs;
1578 #define BNXT_FW_HEALTH_REG 0
1579 #define BNXT_FW_HEARTBEAT_REG 1
1580 #define BNXT_FW_RESET_CNT_REG 2
1581 #define BNXT_FW_RESET_INPROG_REG 3
1582 u32 fw_reset_inprog_reg_mask;
1583 u32 last_fw_heartbeat;
1584 u32 last_fw_reset_cnt;
1587 u8 status_reliable:1;
1588 u8 resets_reliable:1;
1591 u8 fw_reset_seq_cnt;
1592 u32 fw_reset_seq_regs[16];
1593 u32 fw_reset_seq_vals[16];
1594 u32 fw_reset_seq_delay_msec[16];
1597 struct devlink_health_reporter *fw_reporter;
1598 /* Protects severity and remedy */
1600 enum bnxt_health_severity severity;
1601 enum bnxt_health_remedy remedy;
1609 #define BNXT_FW_HEALTH_REG_TYPE_MASK 3
1610 #define BNXT_FW_HEALTH_REG_TYPE_CFG 0
1611 #define BNXT_FW_HEALTH_REG_TYPE_GRC 1
1612 #define BNXT_FW_HEALTH_REG_TYPE_BAR0 2
1613 #define BNXT_FW_HEALTH_REG_TYPE_BAR1 3
1615 #define BNXT_FW_HEALTH_REG_TYPE(reg) ((reg) & BNXT_FW_HEALTH_REG_TYPE_MASK)
1616 #define BNXT_FW_HEALTH_REG_OFF(reg) ((reg) & ~BNXT_FW_HEALTH_REG_TYPE_MASK)
1618 #define BNXT_FW_HEALTH_WIN_BASE 0x3000
1619 #define BNXT_FW_HEALTH_WIN_MAP_OFF 8
1621 #define BNXT_FW_HEALTH_WIN_OFF(reg) (BNXT_FW_HEALTH_WIN_BASE + \
1622 ((reg) & BNXT_GRC_OFFSET_MASK))
1624 #define BNXT_FW_STATUS_HEALTH_MSK 0xffff
1625 #define BNXT_FW_STATUS_HEALTHY 0x8000
1626 #define BNXT_FW_STATUS_SHUTDOWN 0x100000
1627 #define BNXT_FW_STATUS_RECOVERING 0x400000
1629 #define BNXT_FW_IS_HEALTHY(sts) (((sts) & BNXT_FW_STATUS_HEALTH_MSK) ==\
1630 BNXT_FW_STATUS_HEALTHY)
1632 #define BNXT_FW_IS_BOOTING(sts) (((sts) & BNXT_FW_STATUS_HEALTH_MSK) < \
1633 BNXT_FW_STATUS_HEALTHY)
1635 #define BNXT_FW_IS_ERR(sts) (((sts) & BNXT_FW_STATUS_HEALTH_MSK) > \
1636 BNXT_FW_STATUS_HEALTHY)
1638 #define BNXT_FW_IS_RECOVERING(sts) (BNXT_FW_IS_ERR(sts) && \
1639 ((sts) & BNXT_FW_STATUS_RECOVERING))
1641 #define BNXT_FW_RETRY 5
1642 #define BNXT_FW_IF_RETRY 10
1643 #define BNXT_FW_SLOT_RESET_RETRY 4
1645 struct bnxt_aux_priv {
1646 struct auxiliary_device aux_dev;
1647 struct bnxt_en_dev *edev;
1696 NETXTREME_E_P5_VF_HV,
1706 #define CHIP_NUM_57301 0x16c8
1707 #define CHIP_NUM_57302 0x16c9
1708 #define CHIP_NUM_57304 0x16ca
1709 #define CHIP_NUM_58700 0x16cd
1710 #define CHIP_NUM_57402 0x16d0
1711 #define CHIP_NUM_57404 0x16d1
1712 #define CHIP_NUM_57406 0x16d2
1713 #define CHIP_NUM_57407 0x16d5
1715 #define CHIP_NUM_57311 0x16ce
1716 #define CHIP_NUM_57312 0x16cf
1717 #define CHIP_NUM_57314 0x16df
1718 #define CHIP_NUM_57317 0x16e0
1719 #define CHIP_NUM_57412 0x16d6
1720 #define CHIP_NUM_57414 0x16d7
1721 #define CHIP_NUM_57416 0x16d8
1722 #define CHIP_NUM_57417 0x16d9
1723 #define CHIP_NUM_57412L 0x16da
1724 #define CHIP_NUM_57414L 0x16db
1726 #define CHIP_NUM_5745X 0xd730
1727 #define CHIP_NUM_57452 0xc452
1728 #define CHIP_NUM_57454 0xc454
1730 #define CHIP_NUM_57508 0x1750
1731 #define CHIP_NUM_57504 0x1751
1732 #define CHIP_NUM_57502 0x1752
1734 #define CHIP_NUM_58802 0xd802
1735 #define CHIP_NUM_58804 0xd804
1736 #define CHIP_NUM_58808 0xd808
1740 #define CHIP_NUM_58818 0xd818
1742 #define BNXT_CHIP_NUM_5730X(chip_num) \
1743 ((chip_num) >= CHIP_NUM_57301 && \
1744 (chip_num) <= CHIP_NUM_57304)
1746 #define BNXT_CHIP_NUM_5740X(chip_num) \
1747 (((chip_num) >= CHIP_NUM_57402 && \
1748 (chip_num) <= CHIP_NUM_57406) || \
1749 (chip_num) == CHIP_NUM_57407)
1751 #define BNXT_CHIP_NUM_5731X(chip_num) \
1752 ((chip_num) == CHIP_NUM_57311 || \
1753 (chip_num) == CHIP_NUM_57312 || \
1754 (chip_num) == CHIP_NUM_57314 || \
1755 (chip_num) == CHIP_NUM_57317)
1757 #define BNXT_CHIP_NUM_5741X(chip_num) \
1758 ((chip_num) >= CHIP_NUM_57412 && \
1759 (chip_num) <= CHIP_NUM_57414L)
1761 #define BNXT_CHIP_NUM_58700(chip_num) \
1762 ((chip_num) == CHIP_NUM_58700)
1764 #define BNXT_CHIP_NUM_5745X(chip_num) \
1765 ((chip_num) == CHIP_NUM_5745X || \
1766 (chip_num) == CHIP_NUM_57452 || \
1767 (chip_num) == CHIP_NUM_57454)
1770 #define BNXT_CHIP_NUM_57X0X(chip_num) \
1771 (BNXT_CHIP_NUM_5730X(chip_num) || BNXT_CHIP_NUM_5740X(chip_num))
1773 #define BNXT_CHIP_NUM_57X1X(chip_num) \
1774 (BNXT_CHIP_NUM_5731X(chip_num) || BNXT_CHIP_NUM_5741X(chip_num))
1776 #define BNXT_CHIP_NUM_588XX(chip_num) \
1777 ((chip_num) == CHIP_NUM_58802 || \
1778 (chip_num) == CHIP_NUM_58804 || \
1779 (chip_num) == CHIP_NUM_58808)
1781 #define BNXT_VPD_FLD_LEN 32
1782 char board_partno[BNXT_VPD_FLD_LEN];
1783 char board_serialno[BNXT_VPD_FLD_LEN];
1785 struct net_device *dev;
1786 struct pci_dev *pdev;
1791 #define BNXT_FLAG_CHIP_P5 0x1
1792 #define BNXT_FLAG_VF 0x2
1793 #define BNXT_FLAG_LRO 0x4
1795 #define BNXT_FLAG_GRO 0x8
1797 /* Cannot support hardware GRO if CONFIG_INET is not set */
1798 #define BNXT_FLAG_GRO 0x0
1800 #define BNXT_FLAG_TPA (BNXT_FLAG_LRO | BNXT_FLAG_GRO)
1801 #define BNXT_FLAG_JUMBO 0x10
1802 #define BNXT_FLAG_STRIP_VLAN 0x20
1803 #define BNXT_FLAG_AGG_RINGS (BNXT_FLAG_JUMBO | BNXT_FLAG_GRO | \
1805 #define BNXT_FLAG_USING_MSIX 0x40
1806 #define BNXT_FLAG_MSIX_CAP 0x80
1807 #define BNXT_FLAG_RFS 0x100
1808 #define BNXT_FLAG_SHARED_RINGS 0x200
1809 #define BNXT_FLAG_PORT_STATS 0x400
1810 #define BNXT_FLAG_UDP_RSS_CAP 0x800
1811 #define BNXT_FLAG_NEW_RSS_CAP 0x2000
1812 #define BNXT_FLAG_WOL_CAP 0x4000
1813 #define BNXT_FLAG_ROCEV1_CAP 0x8000
1814 #define BNXT_FLAG_ROCEV2_CAP 0x10000
1815 #define BNXT_FLAG_ROCE_CAP (BNXT_FLAG_ROCEV1_CAP | \
1816 BNXT_FLAG_ROCEV2_CAP)
1817 #define BNXT_FLAG_NO_AGG_RINGS 0x20000
1818 #define BNXT_FLAG_RX_PAGE_MODE 0x40000
1819 #define BNXT_FLAG_CHIP_SR2 0x80000
1820 #define BNXT_FLAG_MULTI_HOST 0x100000
1821 #define BNXT_FLAG_DSN_VALID 0x200000
1822 #define BNXT_FLAG_DOUBLE_DB 0x400000
1823 #define BNXT_FLAG_CHIP_NITRO_A0 0x1000000
1824 #define BNXT_FLAG_DIM 0x2000000
1825 #define BNXT_FLAG_ROCE_MIRROR_CAP 0x4000000
1826 #define BNXT_FLAG_PORT_STATS_EXT 0x10000000
1828 #define BNXT_FLAG_ALL_CONFIG_FEATS (BNXT_FLAG_TPA | \
1830 BNXT_FLAG_STRIP_VLAN)
1832 #define BNXT_PF(bp) (!((bp)->flags & BNXT_FLAG_VF))
1833 #define BNXT_VF(bp) ((bp)->flags & BNXT_FLAG_VF)
1834 #define BNXT_NPAR(bp) ((bp)->port_partition_type)
1835 #define BNXT_MH(bp) ((bp)->flags & BNXT_FLAG_MULTI_HOST)
1836 #define BNXT_SINGLE_PF(bp) (BNXT_PF(bp) && !BNXT_NPAR(bp) && !BNXT_MH(bp))
1837 #define BNXT_SH_PORT_CFG_OK(bp) (BNXT_PF(bp) && \
1838 ((bp)->phy_flags & BNXT_PHY_FL_SHARED_PORT_CFG))
1839 #define BNXT_PHY_CFG_ABLE(bp) ((BNXT_SINGLE_PF(bp) || \
1840 BNXT_SH_PORT_CFG_OK(bp)) && \
1841 (bp)->link_info.phy_state == BNXT_PHY_STATE_ENABLED)
1842 #define BNXT_CHIP_TYPE_NITRO_A0(bp) ((bp)->flags & BNXT_FLAG_CHIP_NITRO_A0)
1843 #define BNXT_RX_PAGE_MODE(bp) ((bp)->flags & BNXT_FLAG_RX_PAGE_MODE)
1844 #define BNXT_SUPPORTS_TPA(bp) (!BNXT_CHIP_TYPE_NITRO_A0(bp) && \
1845 (!((bp)->flags & BNXT_FLAG_CHIP_P5) || \
1846 (bp)->max_tpa_v2) && !is_kdump_kernel())
1847 #define BNXT_RX_JUMBO_MODE(bp) ((bp)->flags & BNXT_FLAG_JUMBO)
1849 #define BNXT_CHIP_SR2(bp) \
1850 ((bp)->chip_num == CHIP_NUM_58818)
1852 #define BNXT_CHIP_P5_THOR(bp) \
1853 ((bp)->chip_num == CHIP_NUM_57508 || \
1854 (bp)->chip_num == CHIP_NUM_57504 || \
1855 (bp)->chip_num == CHIP_NUM_57502)
1857 /* Chip class phase 5 */
1858 #define BNXT_CHIP_P5(bp) \
1859 (BNXT_CHIP_P5_THOR(bp) || BNXT_CHIP_SR2(bp))
1861 /* Chip class phase 4.x */
1862 #define BNXT_CHIP_P4(bp) \
1863 (BNXT_CHIP_NUM_57X1X((bp)->chip_num) || \
1864 BNXT_CHIP_NUM_5745X((bp)->chip_num) || \
1865 BNXT_CHIP_NUM_588XX((bp)->chip_num) || \
1866 (BNXT_CHIP_NUM_58700((bp)->chip_num) && \
1867 !BNXT_CHIP_TYPE_NITRO_A0(bp)))
1869 #define BNXT_CHIP_P4_PLUS(bp) \
1870 (BNXT_CHIP_P4(bp) || BNXT_CHIP_P5(bp))
1872 struct bnxt_aux_priv *aux_priv;
1873 struct bnxt_en_dev *edev;
1875 struct bnxt_napi **bnapi;
1877 struct bnxt_rx_ring_info *rx_ring;
1878 struct bnxt_tx_ring_info *tx_ring;
1881 struct sk_buff * (*gro_func)(struct bnxt_tpa_info *, int, int,
1884 struct sk_buff * (*rx_skb_func)(struct bnxt *,
1885 struct bnxt_rx_ring_info *,
1886 u16, void *, u8 *, dma_addr_t,
1892 u32 rx_buf_use_size; /* useable size */
1895 enum dma_data_direction rx_dir;
1897 u32 rx_agg_ring_size;
1900 u32 rx_agg_ring_mask;
1902 int rx_agg_nr_pages;
1910 int tx_nr_rings_per_tc;
1911 int tx_nr_rings_xdp;
1923 /* grp_info indexed by completion ring index */
1924 struct bnxt_ring_grp_info *grp_info;
1925 struct bnxt_vnic_info *vnic_info;
1928 u16 rss_indir_tbl_entries;
1934 u8 max_lltc; /* lossless TCs */
1935 struct bnxt_queue_info q_info[BNXT_MAX_QUEUE];
1936 u8 tc_to_qidx[BNXT_MAX_QUEUE];
1937 u8 q_ids[BNXT_MAX_QUEUE];
1940 unsigned int current_interval;
1941 #define BNXT_TIMER_INTERVAL HZ
1943 struct timer_list timer;
1945 unsigned long state;
1946 #define BNXT_STATE_OPEN 0
1947 #define BNXT_STATE_IN_SP_TASK 1
1948 #define BNXT_STATE_READ_STATS 2
1949 #define BNXT_STATE_FW_RESET_DET 3
1950 #define BNXT_STATE_IN_FW_RESET 4
1951 #define BNXT_STATE_ABORT_ERR 5
1952 #define BNXT_STATE_FW_FATAL_COND 6
1953 #define BNXT_STATE_DRV_REGISTERED 7
1954 #define BNXT_STATE_PCI_CHANNEL_IO_FROZEN 8
1955 #define BNXT_STATE_NAPI_DISABLED 9
1956 #define BNXT_STATE_L2_FILTER_RETRY 10
1957 #define BNXT_STATE_FW_ACTIVATE 11
1958 #define BNXT_STATE_RECOVER 12
1959 #define BNXT_STATE_FW_NON_FATAL_COND 13
1960 #define BNXT_STATE_FW_ACTIVATE_RESET 14
1961 #define BNXT_STATE_HALF_OPEN 15 /* For offline ethtool tests */
1963 #define BNXT_NO_FW_ACCESS(bp) \
1964 (test_bit(BNXT_STATE_FW_FATAL_COND, &(bp)->state) || \
1965 pci_channel_offline((bp)->pdev))
1967 struct bnxt_irq *irq_tbl;
1969 u8 mac_addr[ETH_ALEN];
1971 #ifdef CONFIG_BNXT_DCB
1972 struct ieee_pfc *ieee_pfc;
1973 struct ieee_ets *ieee_ets;
1977 #endif /* CONFIG_BNXT_DCB */
1982 #define BNXT_FW_CAP_SHORT_CMD BIT_ULL(0)
1983 #define BNXT_FW_CAP_LLDP_AGENT BIT_ULL(1)
1984 #define BNXT_FW_CAP_DCBX_AGENT BIT_ULL(2)
1985 #define BNXT_FW_CAP_NEW_RM BIT_ULL(3)
1986 #define BNXT_FW_CAP_IF_CHANGE BIT_ULL(4)
1987 #define BNXT_FW_CAP_KONG_MB_CHNL BIT_ULL(7)
1988 #define BNXT_FW_CAP_OVS_64BIT_HANDLE BIT_ULL(10)
1989 #define BNXT_FW_CAP_TRUSTED_VF BIT_ULL(11)
1990 #define BNXT_FW_CAP_ERROR_RECOVERY BIT_ULL(13)
1991 #define BNXT_FW_CAP_PKG_VER BIT_ULL(14)
1992 #define BNXT_FW_CAP_CFA_ADV_FLOW BIT_ULL(15)
1993 #define BNXT_FW_CAP_CFA_RFS_RING_TBL_IDX_V2 BIT_ULL(16)
1994 #define BNXT_FW_CAP_PCIE_STATS_SUPPORTED BIT_ULL(17)
1995 #define BNXT_FW_CAP_EXT_STATS_SUPPORTED BIT_ULL(18)
1996 #define BNXT_FW_CAP_RSS_HASH_TYPE_DELTA BIT_ULL(19)
1997 #define BNXT_FW_CAP_ERR_RECOVER_RELOAD BIT_ULL(20)
1998 #define BNXT_FW_CAP_HOT_RESET BIT_ULL(21)
1999 #define BNXT_FW_CAP_PTP_RTC BIT_ULL(22)
2000 #define BNXT_FW_CAP_RX_ALL_PKT_TS BIT_ULL(23)
2001 #define BNXT_FW_CAP_VLAN_RX_STRIP BIT_ULL(24)
2002 #define BNXT_FW_CAP_VLAN_TX_INSERT BIT_ULL(25)
2003 #define BNXT_FW_CAP_EXT_HW_STATS_SUPPORTED BIT_ULL(26)
2004 #define BNXT_FW_CAP_LIVEPATCH BIT_ULL(27)
2005 #define BNXT_FW_CAP_PTP_PPS BIT_ULL(28)
2006 #define BNXT_FW_CAP_HOT_RESET_IF BIT_ULL(29)
2007 #define BNXT_FW_CAP_RING_MONITOR BIT_ULL(30)
2008 #define BNXT_FW_CAP_DBG_QCAPS BIT_ULL(31)
2009 #define BNXT_FW_CAP_PTP BIT_ULL(32)
2013 #define BNXT_NEW_RM(bp) ((bp)->fw_cap & BNXT_FW_CAP_NEW_RM)
2014 #define BNXT_PTP_USE_RTC(bp) (!BNXT_MH(bp) && \
2015 ((bp)->fw_cap & BNXT_FW_CAP_PTP_RTC))
2018 u16 hwrm_cmd_kong_seq;
2019 struct dma_pool *hwrm_dma_pool;
2020 struct hlist_head hwrm_pending_list;
2022 struct rtnl_link_stats64 net_stats_prev;
2023 struct bnxt_stats_mem port_stats;
2024 struct bnxt_stats_mem rx_port_stats_ext;
2025 struct bnxt_stats_mem tx_port_stats_ext;
2026 u16 fw_rx_stats_ext_size;
2027 u16 fw_tx_stats_ext_size;
2028 u16 hw_ring_stats_size;
2032 struct bnxt_total_ring_err_stats ring_err_stats_prev;
2034 u16 hwrm_max_req_len;
2035 u16 hwrm_max_ext_req_len;
2036 unsigned int hwrm_cmd_timeout;
2037 unsigned int hwrm_cmd_max_timeout;
2038 struct mutex hwrm_cmd_lock; /* serialize hwrm messages */
2039 struct hwrm_ver_get_output ver_resp;
2040 #define FW_VER_STR_LEN 32
2041 #define BC_HWRM_STR_LEN 21
2042 #define PHY_VER_STR_LEN (FW_VER_STR_LEN - BC_HWRM_STR_LEN)
2043 char fw_ver_str[FW_VER_STR_LEN];
2044 char hwrm_ver_supp[FW_VER_STR_LEN];
2045 char nvm_cfg_ver[FW_VER_STR_LEN];
2047 #define BNXT_FW_VER_CODE(maj, min, bld, rsv) \
2048 ((u64)(maj) << 48 | (u64)(min) << 32 | (u64)(bld) << 16 | (rsv))
2049 #define BNXT_FW_MAJ(bp) ((bp)->fw_ver_code >> 48)
2051 u16 vxlan_fw_dst_port_id;
2052 u16 nge_fw_dst_port_id;
2055 u8 port_partition_type;
2059 struct bnxt_coal_cap coal_cap;
2060 struct bnxt_coal rx_coal;
2061 struct bnxt_coal tx_coal;
2063 u32 stats_coal_ticks;
2064 #define BNXT_DEF_STATS_COAL_TICKS 1000000
2065 #define BNXT_MIN_STATS_COAL_TICKS 250000
2066 #define BNXT_MAX_STATS_COAL_TICKS 1000000
2068 struct work_struct sp_task;
2069 unsigned long sp_event;
2070 #define BNXT_RX_MASK_SP_EVENT 0
2071 #define BNXT_RX_NTP_FLTR_SP_EVENT 1
2072 #define BNXT_LINK_CHNG_SP_EVENT 2
2073 #define BNXT_HWRM_EXEC_FWD_REQ_SP_EVENT 3
2074 #define BNXT_RESET_TASK_SP_EVENT 6
2075 #define BNXT_RST_RING_SP_EVENT 7
2076 #define BNXT_HWRM_PF_UNLOAD_SP_EVENT 8
2077 #define BNXT_PERIODIC_STATS_SP_EVENT 9
2078 #define BNXT_HWRM_PORT_MODULE_SP_EVENT 10
2079 #define BNXT_RESET_TASK_SILENT_SP_EVENT 11
2080 #define BNXT_LINK_SPEED_CHNG_SP_EVENT 14
2081 #define BNXT_FLOW_STATS_SP_EVENT 15
2082 #define BNXT_UPDATE_PHY_SP_EVENT 16
2083 #define BNXT_RING_COAL_NOW_SP_EVENT 17
2084 #define BNXT_FW_RESET_NOTIFY_SP_EVENT 18
2085 #define BNXT_FW_EXCEPTION_SP_EVENT 19
2086 #define BNXT_LINK_CFG_CHANGE_SP_EVENT 21
2087 #define BNXT_FW_ECHO_REQUEST_SP_EVENT 23
2089 struct delayed_work fw_reset_task;
2091 #define BNXT_FW_RESET_STATE_POLL_VF 1
2092 #define BNXT_FW_RESET_STATE_RESET_FW 2
2093 #define BNXT_FW_RESET_STATE_ENABLE_DEV 3
2094 #define BNXT_FW_RESET_STATE_POLL_FW 4
2095 #define BNXT_FW_RESET_STATE_OPENING 5
2096 #define BNXT_FW_RESET_STATE_POLL_FW_DOWN 6
2098 u16 fw_reset_min_dsecs;
2099 #define BNXT_DFLT_FW_RST_MIN_DSECS 20
2100 u16 fw_reset_max_dsecs;
2101 #define BNXT_DFLT_FW_RST_MAX_DSECS 60
2102 unsigned long fw_reset_timestamp;
2104 struct bnxt_fw_health *fw_health;
2106 struct bnxt_hw_resc hw_resc;
2107 struct bnxt_pf_info pf;
2108 struct bnxt_ctx_mem_info *ctx;
2109 #ifdef CONFIG_BNXT_SRIOV
2111 struct bnxt_vf_info vf;
2112 wait_queue_head_t sriov_cfg_wait;
2114 #define BNXT_SRIOV_CFG_WAIT_TMO msecs_to_jiffies(10000)
2117 #if BITS_PER_LONG == 32
2118 /* ensure atomic 64-bit doorbell writes on 32-bit systems. */
2123 #define BNXT_NTP_FLTR_MAX_FLTR 4096
2124 #define BNXT_NTP_FLTR_HASH_SIZE 512
2125 #define BNXT_NTP_FLTR_HASH_MASK (BNXT_NTP_FLTR_HASH_SIZE - 1)
2126 struct hlist_head ntp_fltr_hash_tbl[BNXT_NTP_FLTR_HASH_SIZE];
2127 spinlock_t ntp_fltr_lock; /* for hash table add, del */
2129 unsigned long *ntp_fltr_bmap;
2132 /* To protect link related settings during link changes and
2133 * ethtool settings changes.
2135 struct mutex link_lock;
2136 struct bnxt_link_info link_info;
2137 struct ethtool_eee eee;
2141 /* copied from flags and flags2 in hwrm_port_phy_qcaps_output */
2143 #define BNXT_PHY_FL_EEE_CAP PORT_PHY_QCAPS_RESP_FLAGS_EEE_SUPPORTED
2144 #define BNXT_PHY_FL_EXT_LPBK PORT_PHY_QCAPS_RESP_FLAGS_EXTERNAL_LPBK_SUPPORTED
2145 #define BNXT_PHY_FL_AN_PHY_LPBK PORT_PHY_QCAPS_RESP_FLAGS_AUTONEG_LPBK_SUPPORTED
2146 #define BNXT_PHY_FL_SHARED_PORT_CFG PORT_PHY_QCAPS_RESP_FLAGS_SHARED_PHY_CFG_SUPPORTED
2147 #define BNXT_PHY_FL_PORT_STATS_NO_RESET PORT_PHY_QCAPS_RESP_FLAGS_CUMULATIVE_COUNTERS_ON_RESET
2148 #define BNXT_PHY_FL_NO_PHY_LPBK PORT_PHY_QCAPS_RESP_FLAGS_LOCAL_LPBK_NOT_SUPPORTED
2149 #define BNXT_PHY_FL_FW_MANAGED_LKDN PORT_PHY_QCAPS_RESP_FLAGS_FW_MANAGED_LINK_DOWN
2150 #define BNXT_PHY_FL_NO_FCS PORT_PHY_QCAPS_RESP_FLAGS_NO_FCS
2151 #define BNXT_PHY_FL_NO_PAUSE (PORT_PHY_QCAPS_RESP_FLAGS2_PAUSE_UNSUPPORTED << 8)
2152 #define BNXT_PHY_FL_NO_PFC (PORT_PHY_QCAPS_RESP_FLAGS2_PFC_UNSUPPORTED << 8)
2153 #define BNXT_PHY_FL_BANK_SEL (PORT_PHY_QCAPS_RESP_FLAGS2_BANK_ADDR_SUPPORTED << 8)
2156 struct bnxt_test_info *test_info;
2162 struct bnxt_led_info leds[BNXT_MAX_LED];
2164 #define BNXT_DUMP_LIVE 0
2165 #define BNXT_DUMP_CRASH 1
2167 struct bpf_prog *xdp_prog;
2169 struct bnxt_ptp_cfg *ptp_cfg;
2170 u8 ptp_all_rx_tstamp;
2172 /* devlink interface and vf-rep structs */
2174 struct devlink_port dl_port;
2175 enum devlink_eswitch_mode eswitch_mode;
2176 struct bnxt_vf_rep **vf_reps; /* array of vf-rep ptrs */
2177 u16 *cfa_code_map; /* cfa_code -> vf_idx map */
2179 struct bnxt_tc_info *tc_info;
2180 struct list_head tc_indr_block_list;
2181 struct dentry *debugfs_pdev;
2182 struct device *hwmon_dev;
2183 enum board_idx board_idx;
2186 #define BNXT_NUM_RX_RING_STATS 8
2187 #define BNXT_NUM_TX_RING_STATS 8
2188 #define BNXT_NUM_TPA_RING_STATS 4
2189 #define BNXT_NUM_TPA_RING_STATS_P5 5
2190 #define BNXT_NUM_TPA_RING_STATS_P5_SR2 6
2192 #define BNXT_RING_STATS_SIZE_P5 \
2193 ((BNXT_NUM_RX_RING_STATS + BNXT_NUM_TX_RING_STATS + \
2194 BNXT_NUM_TPA_RING_STATS_P5) * 8)
2196 #define BNXT_RING_STATS_SIZE_P5_SR2 \
2197 ((BNXT_NUM_RX_RING_STATS + BNXT_NUM_TX_RING_STATS + \
2198 BNXT_NUM_TPA_RING_STATS_P5_SR2) * 8)
2200 #define BNXT_GET_RING_STATS64(sw, counter) \
2201 (*((sw) + offsetof(struct ctx_hw_stats, counter) / 8))
2203 #define BNXT_GET_RX_PORT_STATS64(sw, counter) \
2204 (*((sw) + offsetof(struct rx_port_stats, counter) / 8))
2206 #define BNXT_GET_TX_PORT_STATS64(sw, counter) \
2207 (*((sw) + offsetof(struct tx_port_stats, counter) / 8))
2209 #define BNXT_PORT_STATS_SIZE \
2210 (sizeof(struct rx_port_stats) + sizeof(struct tx_port_stats) + 1024)
2212 #define BNXT_TX_PORT_STATS_BYTE_OFFSET \
2213 (sizeof(struct rx_port_stats) + 512)
2215 #define BNXT_RX_STATS_OFFSET(counter) \
2216 (offsetof(struct rx_port_stats, counter) / 8)
2218 #define BNXT_TX_STATS_OFFSET(counter) \
2219 ((offsetof(struct tx_port_stats, counter) + \
2220 BNXT_TX_PORT_STATS_BYTE_OFFSET) / 8)
2222 #define BNXT_RX_STATS_EXT_OFFSET(counter) \
2223 (offsetof(struct rx_port_stats_ext, counter) / 8)
2225 #define BNXT_RX_STATS_EXT_NUM_LEGACY \
2226 BNXT_RX_STATS_EXT_OFFSET(rx_fec_corrected_blocks)
2228 #define BNXT_TX_STATS_EXT_OFFSET(counter) \
2229 (offsetof(struct tx_port_stats_ext, counter) / 8)
2231 #define BNXT_HW_FEATURE_VLAN_ALL_RX \
2232 (NETIF_F_HW_VLAN_CTAG_RX | NETIF_F_HW_VLAN_STAG_RX)
2233 #define BNXT_HW_FEATURE_VLAN_ALL_TX \
2234 (NETIF_F_HW_VLAN_CTAG_TX | NETIF_F_HW_VLAN_STAG_TX)
2236 #define I2C_DEV_ADDR_A0 0xa0
2237 #define I2C_DEV_ADDR_A2 0xa2
2238 #define SFF_DIAG_SUPPORT_OFFSET 0x5c
2239 #define SFF_MODULE_ID_SFP 0x3
2240 #define SFF_MODULE_ID_QSFP 0xc
2241 #define SFF_MODULE_ID_QSFP_PLUS 0xd
2242 #define SFF_MODULE_ID_QSFP28 0x11
2243 #define BNXT_MAX_PHY_I2C_RESP_SIZE 64
2245 static inline u32 bnxt_tx_avail(struct bnxt *bp,
2246 const struct bnxt_tx_ring_info *txr)
2248 u32 used = READ_ONCE(txr->tx_prod) - READ_ONCE(txr->tx_cons);
2250 return bp->tx_ring_size - (used & bp->tx_ring_mask);
2253 static inline void bnxt_writeq(struct bnxt *bp, u64 val,
2254 volatile void __iomem *addr)
2256 #if BITS_PER_LONG == 32
2257 spin_lock(&bp->db_lock);
2258 lo_hi_writeq(val, addr);
2259 spin_unlock(&bp->db_lock);
2265 static inline void bnxt_writeq_relaxed(struct bnxt *bp, u64 val,
2266 volatile void __iomem *addr)
2268 #if BITS_PER_LONG == 32
2269 spin_lock(&bp->db_lock);
2270 lo_hi_writeq_relaxed(val, addr);
2271 spin_unlock(&bp->db_lock);
2273 writeq_relaxed(val, addr);
2277 /* For TX and RX ring doorbells with no ordering guarantee*/
2278 static inline void bnxt_db_write_relaxed(struct bnxt *bp,
2279 struct bnxt_db_info *db, u32 idx)
2281 if (bp->flags & BNXT_FLAG_CHIP_P5) {
2282 bnxt_writeq_relaxed(bp, db->db_key64 | idx, db->doorbell);
2284 u32 db_val = db->db_key32 | idx;
2286 writel_relaxed(db_val, db->doorbell);
2287 if (bp->flags & BNXT_FLAG_DOUBLE_DB)
2288 writel_relaxed(db_val, db->doorbell);
2292 /* For TX and RX ring doorbells */
2293 static inline void bnxt_db_write(struct bnxt *bp, struct bnxt_db_info *db,
2296 if (bp->flags & BNXT_FLAG_CHIP_P5) {
2297 bnxt_writeq(bp, db->db_key64 | idx, db->doorbell);
2299 u32 db_val = db->db_key32 | idx;
2301 writel(db_val, db->doorbell);
2302 if (bp->flags & BNXT_FLAG_DOUBLE_DB)
2303 writel(db_val, db->doorbell);
2307 /* Must hold rtnl_lock */
2308 static inline bool bnxt_sriov_cfg(struct bnxt *bp)
2310 #if defined(CONFIG_BNXT_SRIOV)
2311 return BNXT_PF(bp) && (bp->pf.active_vfs || bp->sriov_cfg);
2317 extern const u16 bnxt_lhint_arr[];
2319 int bnxt_alloc_rx_data(struct bnxt *bp, struct bnxt_rx_ring_info *rxr,
2320 u16 prod, gfp_t gfp);
2321 void bnxt_reuse_rx_data(struct bnxt_rx_ring_info *rxr, u16 cons, void *data);
2322 u32 bnxt_fw_health_readl(struct bnxt *bp, int reg_idx);
2323 void bnxt_set_tpa_flags(struct bnxt *bp);
2324 void bnxt_set_ring_params(struct bnxt *);
2325 int bnxt_set_rx_skb_mode(struct bnxt *bp, bool page_mode);
2326 int bnxt_hwrm_func_drv_rgtr(struct bnxt *bp, unsigned long *bmap,
2327 int bmap_size, bool async_only);
2328 int bnxt_hwrm_func_drv_unrgtr(struct bnxt *bp);
2329 int bnxt_get_nr_rss_ctxs(struct bnxt *bp, int rx_rings);
2330 int bnxt_hwrm_vnic_cfg(struct bnxt *bp, u16 vnic_id);
2331 int __bnxt_hwrm_get_tx_rings(struct bnxt *bp, u16 fid, int *tx_rings);
2332 int bnxt_nq_rings_in_use(struct bnxt *bp);
2333 int bnxt_hwrm_set_coal(struct bnxt *);
2334 void bnxt_free_ctx_mem(struct bnxt *bp);
2335 unsigned int bnxt_get_max_func_stat_ctxs(struct bnxt *bp);
2336 unsigned int bnxt_get_avail_stat_ctxs_for_en(struct bnxt *bp);
2337 unsigned int bnxt_get_max_func_cp_rings(struct bnxt *bp);
2338 unsigned int bnxt_get_avail_cp_rings_for_en(struct bnxt *bp);
2339 int bnxt_get_avail_msix(struct bnxt *bp, int num);
2340 int bnxt_reserve_rings(struct bnxt *bp, bool irq_re_init);
2341 void bnxt_tx_disable(struct bnxt *bp);
2342 void bnxt_tx_enable(struct bnxt *bp);
2343 void bnxt_sched_reset_txr(struct bnxt *bp, struct bnxt_tx_ring_info *txr,
2345 void bnxt_report_link(struct bnxt *bp);
2346 int bnxt_update_link(struct bnxt *bp, bool chng_link_state);
2347 int bnxt_hwrm_set_pause(struct bnxt *);
2348 int bnxt_hwrm_set_link_setting(struct bnxt *, bool, bool);
2349 int bnxt_cancel_reservations(struct bnxt *bp, bool fw_reset);
2350 int bnxt_hwrm_alloc_wol_fltr(struct bnxt *bp);
2351 int bnxt_hwrm_free_wol_fltr(struct bnxt *bp);
2352 int bnxt_hwrm_func_resc_qcaps(struct bnxt *bp, bool all);
2353 int bnxt_hwrm_func_qcaps(struct bnxt *bp);
2354 int bnxt_hwrm_fw_set_time(struct bnxt *);
2355 int bnxt_open_nic(struct bnxt *, bool, bool);
2356 int bnxt_half_open_nic(struct bnxt *bp);
2357 void bnxt_half_close_nic(struct bnxt *bp);
2358 void bnxt_reenable_sriov(struct bnxt *bp);
2359 int bnxt_close_nic(struct bnxt *, bool, bool);
2360 void bnxt_get_ring_err_stats(struct bnxt *bp,
2361 struct bnxt_total_ring_err_stats *stats);
2362 int bnxt_dbg_hwrm_rd_reg(struct bnxt *bp, u32 reg_off, u16 num_words,
2364 void bnxt_fw_exception(struct bnxt *bp);
2365 void bnxt_fw_reset(struct bnxt *bp);
2366 int bnxt_check_rings(struct bnxt *bp, int tx, int rx, bool sh, int tcs,
2368 int bnxt_fw_init_one(struct bnxt *bp);
2369 bool bnxt_hwrm_reset_permitted(struct bnxt *bp);
2370 int bnxt_setup_mq_tc(struct net_device *dev, u8 tc);
2371 int bnxt_get_max_rings(struct bnxt *, int *, int *, bool);
2372 int bnxt_restore_pf_fw_resources(struct bnxt *bp);
2373 int bnxt_get_port_parent_id(struct net_device *dev,
2374 struct netdev_phys_item_id *ppid);
2375 void bnxt_dim_work(struct work_struct *work);
2376 int bnxt_hwrm_set_ring_coal(struct bnxt *bp, struct bnxt_napi *bnapi);
2377 void bnxt_print_device_info(struct bnxt *bp);