1 /* bnx2x_sp.h: Broadcom Everest network driver.
3 * Copyright (c) 2011-2013 Broadcom Corporation
5 * Unless you and Broadcom execute a separate written software license
6 * agreement governing use of this software, this software is licensed to you
7 * under the terms of the GNU General Public License version 2, available
8 * at http://www.gnu.org/licenses/old-licenses/gpl-2.0.html (the "GPL").
10 * Notwithstanding the above, under no circumstances may you combine this
11 * software in any way with any other Broadcom software provided under a
12 * license other than the GPL, without Broadcom's express prior written
15 * Maintained by: Ariel Elior <ariel.elior@qlogic.com>
16 * Written by: Vladislav Zolotarov
19 #ifndef BNX2X_SP_VERBS
20 #define BNX2X_SP_VERBS
25 /* Bits representing general command's configuration */
29 /* Wait until all pending commands complete */
31 /* Don't send a ramrod, only update a registry */
33 /* Configure HW according to the current object state */
35 /* Execute the next command now */
37 /* Don't add a new command and continue execution of postponed
38 * commands. If not set a new command will be added to the
39 * pending commands list.
42 /* If there is another pending ramrod, wait until it finishes and
43 * re-try to submit this one. This flag can be set only in sleepable
44 * context, and should not be set from the context that completes the
45 * ramrods as deadlock will occur.
56 /* Public slow path states */
58 BNX2X_FILTER_MAC_PENDING,
59 BNX2X_FILTER_VLAN_PENDING,
60 BNX2X_FILTER_VLAN_MAC_PENDING,
61 BNX2X_FILTER_RX_MODE_PENDING,
62 BNX2X_FILTER_RX_MODE_SCHED,
63 BNX2X_FILTER_ISCSI_ETH_START_SCHED,
64 BNX2X_FILTER_ISCSI_ETH_STOP_SCHED,
65 BNX2X_FILTER_FCOE_ETH_START_SCHED,
66 BNX2X_FILTER_FCOE_ETH_STOP_SCHED,
67 BNX2X_FILTER_MCAST_PENDING,
68 BNX2X_FILTER_MCAST_SCHED,
69 BNX2X_FILTER_RSS_CONF_PENDING,
70 BNX2X_AFEX_FCOE_Q_UPDATE_PENDING,
71 BNX2X_AFEX_PENDING_VIFSET_MCP_ACK
74 struct bnx2x_raw_obj {
81 /* Ramrod data buffer params */
83 dma_addr_t rdata_mapping;
85 /* Ramrod state params */
86 int state; /* "ramrod is pending" state bit */
87 unsigned long *pstate; /* pointer to state buffer */
89 bnx2x_obj_type obj_type;
91 int (*wait_comp)(struct bnx2x *bp,
92 struct bnx2x_raw_obj *o);
94 bool (*check_pending)(struct bnx2x_raw_obj *o);
95 void (*clear_pending)(struct bnx2x_raw_obj *o);
96 void (*set_pending)(struct bnx2x_raw_obj *o);
99 /************************* VLAN-MAC commands related parameters ***************/
100 struct bnx2x_mac_ramrod_data {
105 struct bnx2x_vlan_ramrod_data {
109 struct bnx2x_vlan_mac_ramrod_data {
115 union bnx2x_classification_ramrod_data {
116 struct bnx2x_mac_ramrod_data mac;
117 struct bnx2x_vlan_ramrod_data vlan;
118 struct bnx2x_vlan_mac_ramrod_data vlan_mac;
121 /* VLAN_MAC commands */
122 enum bnx2x_vlan_mac_cmd {
128 struct bnx2x_vlan_mac_data {
129 /* Requested command: BNX2X_VLAN_MAC_XX */
130 enum bnx2x_vlan_mac_cmd cmd;
131 /* used to contain the data related vlan_mac_flags bits from
134 unsigned long vlan_mac_flags;
136 /* Needed for MOVE command */
137 struct bnx2x_vlan_mac_obj *target_obj;
139 union bnx2x_classification_ramrod_data u;
142 /*************************** Exe Queue obj ************************************/
143 union bnx2x_exe_queue_cmd_data {
144 struct bnx2x_vlan_mac_data vlan_mac;
151 struct bnx2x_exeq_elem {
152 struct list_head link;
154 /* Length of this element in the exe_chunk. */
157 union bnx2x_exe_queue_cmd_data cmd_data;
160 union bnx2x_qable_obj;
162 union bnx2x_exeq_comp_elem {
163 union event_ring_elem *elem;
166 struct bnx2x_exe_queue_obj;
168 typedef int (*exe_q_validate)(struct bnx2x *bp,
169 union bnx2x_qable_obj *o,
170 struct bnx2x_exeq_elem *elem);
172 typedef int (*exe_q_remove)(struct bnx2x *bp,
173 union bnx2x_qable_obj *o,
174 struct bnx2x_exeq_elem *elem);
176 /* Return positive if entry was optimized, 0 - if not, negative
177 * in case of an error.
179 typedef int (*exe_q_optimize)(struct bnx2x *bp,
180 union bnx2x_qable_obj *o,
181 struct bnx2x_exeq_elem *elem);
182 typedef int (*exe_q_execute)(struct bnx2x *bp,
183 union bnx2x_qable_obj *o,
184 struct list_head *exe_chunk,
185 unsigned long *ramrod_flags);
186 typedef struct bnx2x_exeq_elem *
187 (*exe_q_get)(struct bnx2x_exe_queue_obj *o,
188 struct bnx2x_exeq_elem *elem);
190 struct bnx2x_exe_queue_obj {
191 /* Commands pending for an execution. */
192 struct list_head exe_queue;
194 /* Commands pending for an completion. */
195 struct list_head pending_comp;
199 /* Maximum length of commands' list for one execution */
202 union bnx2x_qable_obj *owner;
204 /****** Virtual functions ******/
206 * Called before commands execution for commands that are really
207 * going to be executed (after 'optimize').
209 * Must run under exe_queue->lock
211 exe_q_validate validate;
214 * Called before removing pending commands, cleaning allocated
215 * resources (e.g., credits from validate)
220 * This will try to cancel the current pending commands list
221 * considering the new command.
223 * Returns the number of optimized commands or a negative error code
225 * Must run under exe_queue->lock
227 exe_q_optimize optimize;
230 * Run the next commands chunk (owner specific).
232 exe_q_execute execute;
235 * Return the exe_queue element containing the specific command
236 * if any. Otherwise return NULL.
240 /***************** Classification verbs: Set/Del MAC/VLAN/VLAN-MAC ************/
242 * Element in the VLAN_MAC registry list having all currently configured
245 struct bnx2x_vlan_mac_registry_elem {
246 struct list_head link;
248 /* Used to store the cam offset used for the mac/vlan/vlan-mac.
249 * Relevant for 57710 and 57711 only. VLANs and MACs share the
250 * same CAM for these chips.
254 /* Needed for DEL and RESTORE flows */
255 unsigned long vlan_mac_flags;
257 union bnx2x_classification_ramrod_data u;
260 /* Bits representing VLAN_MAC commands specific flags */
266 BNX2X_DONT_CONSUME_CAM_CREDIT,
267 BNX2X_DONT_CONSUME_CAM_CREDIT_DEST,
269 /* When looking for matching filters, some flags are not interesting */
270 #define BNX2X_VLAN_MAC_CMP_MASK (1 << BNX2X_UC_LIST_MAC | \
271 1 << BNX2X_ETH_MAC | \
272 1 << BNX2X_ISCSI_ETH_MAC | \
273 1 << BNX2X_NETQ_ETH_MAC)
274 #define BNX2X_VLAN_MAC_CMP_FLAGS(flags) \
275 ((flags) & BNX2X_VLAN_MAC_CMP_MASK)
277 struct bnx2x_vlan_mac_ramrod_params {
278 /* Object to run the command from */
279 struct bnx2x_vlan_mac_obj *vlan_mac_obj;
281 /* General command flags: COMP_WAIT, etc. */
282 unsigned long ramrod_flags;
284 /* Command specific configuration request */
285 struct bnx2x_vlan_mac_data user_req;
288 struct bnx2x_vlan_mac_obj {
289 struct bnx2x_raw_obj raw;
291 /* Bookkeeping list: will prevent the addition of already existing
294 struct list_head head;
295 /* Implement a simple reader/writer lock on the head list.
296 * all these fields should only be accessed under the exe_queue lock
298 u8 head_reader; /* Num. of readers accessing head list */
299 bool head_exe_request; /* Pending execution request. */
300 unsigned long saved_ramrod_flags; /* Ramrods of pending execution */
302 /* TODO: Add it's initialization in the init functions */
303 struct bnx2x_exe_queue_obj exe_queue;
305 /* MACs credit pool */
306 struct bnx2x_credit_pool_obj *macs_pool;
308 /* VLANs credit pool */
309 struct bnx2x_credit_pool_obj *vlans_pool;
311 /* RAMROD command to be used */
314 /* copy first n elements onto preallocated buffer
316 * @param n number of elements to get
317 * @param buf buffer preallocated by caller into which elements
318 * will be copied. Note elements are 4-byte aligned
319 * so buffer size must be able to accommodate the
322 * @return number of copied bytes
324 int (*get_n_elements)(struct bnx2x *bp,
325 struct bnx2x_vlan_mac_obj *o, int n, u8 *base,
329 * Checks if ADD-ramrod with the given params may be performed.
331 * @return zero if the element may be added
334 int (*check_add)(struct bnx2x *bp,
335 struct bnx2x_vlan_mac_obj *o,
336 union bnx2x_classification_ramrod_data *data);
339 * Checks if DEL-ramrod with the given params may be performed.
341 * @return true if the element may be deleted
343 struct bnx2x_vlan_mac_registry_elem *
344 (*check_del)(struct bnx2x *bp,
345 struct bnx2x_vlan_mac_obj *o,
346 union bnx2x_classification_ramrod_data *data);
349 * Checks if DEL-ramrod with the given params may be performed.
351 * @return true if the element may be deleted
353 bool (*check_move)(struct bnx2x *bp,
354 struct bnx2x_vlan_mac_obj *src_o,
355 struct bnx2x_vlan_mac_obj *dst_o,
356 union bnx2x_classification_ramrod_data *data);
359 * Update the relevant credit object(s) (consume/return
362 bool (*get_credit)(struct bnx2x_vlan_mac_obj *o);
363 bool (*put_credit)(struct bnx2x_vlan_mac_obj *o);
364 bool (*get_cam_offset)(struct bnx2x_vlan_mac_obj *o, int *offset);
365 bool (*put_cam_offset)(struct bnx2x_vlan_mac_obj *o, int offset);
368 * Configures one rule in the ramrod data buffer.
370 void (*set_one_rule)(struct bnx2x *bp,
371 struct bnx2x_vlan_mac_obj *o,
372 struct bnx2x_exeq_elem *elem, int rule_idx,
376 * Delete all configured elements having the given
377 * vlan_mac_flags specification. Assumes no pending for
378 * execution commands. Will schedule all all currently
379 * configured MACs/VLANs/VLAN-MACs matching the vlan_mac_flags
380 * specification for deletion and will use the given
381 * ramrod_flags for the last DEL operation.
385 * @param ramrod_flags RAMROD_XX flags
387 * @return 0 if the last operation has completed successfully
388 * and there are no more elements left, positive value
389 * if there are pending for completion commands,
390 * negative value in case of failure.
392 int (*delete_all)(struct bnx2x *bp,
393 struct bnx2x_vlan_mac_obj *o,
394 unsigned long *vlan_mac_flags,
395 unsigned long *ramrod_flags);
398 * Reconfigures the next MAC/VLAN/VLAN-MAC element from the previously
399 * configured elements list.
402 * @param p Command parameters (RAMROD_COMP_WAIT bit in
403 * ramrod_flags is only taken into an account)
404 * @param ppos a pointer to the cookie that should be given back in the
405 * next call to make function handle the next element. If
406 * *ppos is set to NULL it will restart the iterator.
407 * If returned *ppos == NULL this means that the last
408 * element has been handled.
412 int (*restore)(struct bnx2x *bp,
413 struct bnx2x_vlan_mac_ramrod_params *p,
414 struct bnx2x_vlan_mac_registry_elem **ppos);
417 * Should be called on a completion arrival.
421 * @param cqe Completion element we are handling
422 * @param ramrod_flags if RAMROD_CONT is set the next bulk of
423 * pending commands will be executed.
424 * RAMROD_DRV_CLR_ONLY and RAMROD_RESTORE
425 * may also be set if needed.
427 * @return 0 if there are neither pending nor waiting for
428 * completion commands. Positive value if there are
429 * pending for execution or for completion commands.
430 * Negative value in case of an error (including an
433 int (*complete)(struct bnx2x *bp, struct bnx2x_vlan_mac_obj *o,
434 union event_ring_elem *cqe,
435 unsigned long *ramrod_flags);
438 * Wait for completion of all commands. Don't schedule new ones,
439 * just wait. It assumes that the completion code will schedule
442 int (*wait)(struct bnx2x *bp, struct bnx2x_vlan_mac_obj *o);
446 BNX2X_LLH_CAM_ISCSI_ETH_LINE = 0,
447 BNX2X_LLH_CAM_ETH_LINE,
448 BNX2X_LLH_CAM_MAX_PF_LINE = NIG_REG_LLH1_FUNC_MEM_SIZE / 2
451 /** RX_MODE verbs:DROP_ALL/ACCEPT_ALL/ACCEPT_ALL_MULTI/ACCEPT_ALL_VLAN/NORMAL */
453 /* RX_MODE ramrod special flags: set in rx_mode_flags field in
454 * a bnx2x_rx_mode_ramrod_params.
457 BNX2X_RX_MODE_FCOE_ETH,
458 BNX2X_RX_MODE_ISCSI_ETH,
462 BNX2X_ACCEPT_UNICAST,
463 BNX2X_ACCEPT_MULTICAST,
464 BNX2X_ACCEPT_ALL_UNICAST,
465 BNX2X_ACCEPT_ALL_MULTICAST,
466 BNX2X_ACCEPT_BROADCAST,
467 BNX2X_ACCEPT_UNMATCHED,
468 BNX2X_ACCEPT_ANY_VLAN
471 struct bnx2x_rx_mode_ramrod_params {
472 struct bnx2x_rx_mode_obj *rx_mode_obj;
473 unsigned long *pstate;
478 unsigned long ramrod_flags;
479 unsigned long rx_mode_flags;
481 /* rdata is either a pointer to eth_filter_rules_ramrod_data(e2) or to
482 * a tstorm_eth_mac_filter_config (e1x).
485 dma_addr_t rdata_mapping;
487 /* Rx mode settings */
488 unsigned long rx_accept_flags;
490 /* internal switching settings */
491 unsigned long tx_accept_flags;
494 struct bnx2x_rx_mode_obj {
495 int (*config_rx_mode)(struct bnx2x *bp,
496 struct bnx2x_rx_mode_ramrod_params *p);
498 int (*wait_comp)(struct bnx2x *bp,
499 struct bnx2x_rx_mode_ramrod_params *p);
502 /********************** Set multicast group ***********************************/
504 struct bnx2x_mcast_list_elem {
505 struct list_head link;
509 union bnx2x_mcast_config_data {
511 u8 bin; /* used in a RESTORE flow */
514 struct bnx2x_mcast_ramrod_params {
515 struct bnx2x_mcast_obj *mcast_obj;
517 /* Relevant options are RAMROD_COMP_WAIT and RAMROD_DRV_CLR_ONLY */
518 unsigned long ramrod_flags;
520 struct list_head mcast_list; /* list of struct bnx2x_mcast_list_elem */
522 * - rename it to macs_num.
523 * - Add a new command type for handling pending commands
524 * (remove "zero semantics").
526 * Length of mcast_list. If zero and ADD_CONT command - post
532 enum bnx2x_mcast_cmd {
534 BNX2X_MCAST_CMD_CONT,
536 BNX2X_MCAST_CMD_RESTORE,
539 struct bnx2x_mcast_obj {
540 struct bnx2x_raw_obj raw;
544 #define BNX2X_MCAST_BINS_NUM 256
545 #define BNX2X_MCAST_VEC_SZ (BNX2X_MCAST_BINS_NUM / 64)
546 u64 vec[BNX2X_MCAST_VEC_SZ];
548 /** Number of BINs to clear. Should be updated
549 * immediately when a command arrives in order to
550 * properly create DEL commands.
556 struct list_head macs;
561 /* Pending commands */
562 struct list_head pending_cmds_head;
564 /* A state that is set in raw.pstate, when there are pending commands */
567 /* Maximal number of mcast MACs configured in one command */
570 /* Total number of currently pending MACs to configure: both
571 * in the pending commands list and in the current command.
573 int total_pending_num;
578 * @param cmd command to execute (BNX2X_MCAST_CMD_X, see above)
580 int (*config_mcast)(struct bnx2x *bp,
581 struct bnx2x_mcast_ramrod_params *p,
582 enum bnx2x_mcast_cmd cmd);
585 * Fills the ramrod data during the RESTORE flow.
589 * @param start_idx Registry index to start from
590 * @param rdata_idx Index in the ramrod data to start from
592 * @return -1 if we handled the whole registry or index of the last
593 * handled registry element.
595 int (*hdl_restore)(struct bnx2x *bp, struct bnx2x_mcast_obj *o,
596 int start_bin, int *rdata_idx);
598 int (*enqueue_cmd)(struct bnx2x *bp, struct bnx2x_mcast_obj *o,
599 struct bnx2x_mcast_ramrod_params *p,
600 enum bnx2x_mcast_cmd cmd);
602 void (*set_one_rule)(struct bnx2x *bp,
603 struct bnx2x_mcast_obj *o, int idx,
604 union bnx2x_mcast_config_data *cfg_data,
605 enum bnx2x_mcast_cmd cmd);
607 /** Checks if there are more mcast MACs to be set or a previous
608 * command is still pending.
610 bool (*check_pending)(struct bnx2x_mcast_obj *o);
613 * Set/Clear/Check SCHEDULED state of the object
615 void (*set_sched)(struct bnx2x_mcast_obj *o);
616 void (*clear_sched)(struct bnx2x_mcast_obj *o);
617 bool (*check_sched)(struct bnx2x_mcast_obj *o);
619 /* Wait until all pending commands complete */
620 int (*wait_comp)(struct bnx2x *bp, struct bnx2x_mcast_obj *o);
623 * Handle the internal object counters needed for proper
624 * commands handling. Checks that the provided parameters are
627 int (*validate)(struct bnx2x *bp,
628 struct bnx2x_mcast_ramrod_params *p,
629 enum bnx2x_mcast_cmd cmd);
632 * Restore the values of internal counters in case of a failure.
634 void (*revert)(struct bnx2x *bp,
635 struct bnx2x_mcast_ramrod_params *p,
638 int (*get_registry_size)(struct bnx2x_mcast_obj *o);
639 void (*set_registry_size)(struct bnx2x_mcast_obj *o, int n);
642 /*************************** Credit handling **********************************/
643 struct bnx2x_credit_pool_obj {
645 /* Current amount of credit in the pool */
648 /* Maximum allowed credit. put() will check against it. */
651 /* Allocate a pool table statically.
653 * Currently the maximum allowed size is MAX_MAC_CREDIT_E2(272)
655 * The set bit in the table will mean that the entry is available.
657 #define BNX2X_POOL_VEC_SIZE (MAX_MAC_CREDIT_E2 / 64)
658 u64 pool_mirror[BNX2X_POOL_VEC_SIZE];
660 /* Base pool offset (initialized differently */
661 int base_pool_offset;
664 * Get the next free pool entry.
666 * @return true if there was a free entry in the pool
668 bool (*get_entry)(struct bnx2x_credit_pool_obj *o, int *entry);
671 * Return the entry back to the pool.
673 * @return true if entry is legal and has been successfully
674 * returned to the pool.
676 bool (*put_entry)(struct bnx2x_credit_pool_obj *o, int entry);
679 * Get the requested amount of credit from the pool.
681 * @param cnt Amount of requested credit
682 * @return true if the operation is successful
684 bool (*get)(struct bnx2x_credit_pool_obj *o, int cnt);
687 * Returns the credit to the pool.
689 * @param cnt Amount of credit to return
690 * @return true if the operation is successful
692 bool (*put)(struct bnx2x_credit_pool_obj *o, int cnt);
695 * Reads the current amount of credit.
697 int (*check)(struct bnx2x_credit_pool_obj *o);
700 /*************************** RSS configuration ********************************/
702 /* RSS_MODE bits are mutually exclusive */
703 BNX2X_RSS_MODE_DISABLED,
704 BNX2X_RSS_MODE_REGULAR,
706 BNX2X_RSS_SET_SRCH, /* Setup searcher, E1x specific flag */
714 BNX2X_RSS_GRE_INNER_HDRS,
717 struct bnx2x_config_rss_params {
718 struct bnx2x_rss_config_obj *rss_obj;
720 /* may have RAMROD_COMP_WAIT set only */
721 unsigned long ramrod_flags;
723 /* BNX2X_RSS_X bits */
724 unsigned long rss_flags;
726 /* Number hash bits to take into an account */
729 /* Indirection table */
730 u8 ind_table[T_ETH_INDIRECTION_TABLE_SIZE];
732 /* RSS hash values */
735 /* valid only iff BNX2X_RSS_UPDATE_TOE is set */
739 struct bnx2x_rss_config_obj {
740 struct bnx2x_raw_obj raw;
742 /* RSS engine to use */
745 /* Last configured indirection table */
746 u8 ind_table[T_ETH_INDIRECTION_TABLE_SIZE];
748 /* flags for enabling 4-tupple hash on UDP */
752 int (*config_rss)(struct bnx2x *bp,
753 struct bnx2x_config_rss_params *p);
756 /*********************** Queue state update ***********************************/
758 /* UPDATE command options */
760 BNX2X_Q_UPDATE_IN_VLAN_REM,
761 BNX2X_Q_UPDATE_IN_VLAN_REM_CHNG,
762 BNX2X_Q_UPDATE_OUT_VLAN_REM,
763 BNX2X_Q_UPDATE_OUT_VLAN_REM_CHNG,
764 BNX2X_Q_UPDATE_ANTI_SPOOF,
765 BNX2X_Q_UPDATE_ANTI_SPOOF_CHNG,
766 BNX2X_Q_UPDATE_ACTIVATE,
767 BNX2X_Q_UPDATE_ACTIVATE_CHNG,
768 BNX2X_Q_UPDATE_DEF_VLAN_EN,
769 BNX2X_Q_UPDATE_DEF_VLAN_EN_CHNG,
770 BNX2X_Q_UPDATE_SILENT_VLAN_REM_CHNG,
771 BNX2X_Q_UPDATE_SILENT_VLAN_REM,
772 BNX2X_Q_UPDATE_TX_SWITCHING_CHNG,
773 BNX2X_Q_UPDATE_TX_SWITCHING,
774 BNX2X_Q_UPDATE_PTP_PKTS_CHNG,
775 BNX2X_Q_UPDATE_PTP_PKTS,
778 /* Allowed Queue states */
781 BNX2X_Q_STATE_INITIALIZED,
782 BNX2X_Q_STATE_ACTIVE,
783 BNX2X_Q_STATE_MULTI_COS,
784 BNX2X_Q_STATE_MCOS_TERMINATED,
785 BNX2X_Q_STATE_INACTIVE,
786 BNX2X_Q_STATE_STOPPED,
787 BNX2X_Q_STATE_TERMINATED,
792 /* Allowed Queue states */
793 enum bnx2x_q_logical_state {
794 BNX2X_Q_LOGICAL_STATE_ACTIVE,
795 BNX2X_Q_LOGICAL_STATE_STOPPED,
798 /* Allowed commands */
799 enum bnx2x_queue_cmd {
802 BNX2X_Q_CMD_SETUP_TX_ONLY,
803 BNX2X_Q_CMD_DEACTIVATE,
804 BNX2X_Q_CMD_ACTIVATE,
806 BNX2X_Q_CMD_UPDATE_TPA,
809 BNX2X_Q_CMD_TERMINATE,
814 /* queue SETUP + INIT flags */
817 BNX2X_Q_FLG_TPA_IPV6,
820 BNX2X_Q_FLG_ZERO_STATS,
829 BNX2X_Q_FLG_LEADING_RSS,
831 BNX2X_Q_FLG_DEF_VLAN,
832 BNX2X_Q_FLG_TX_SWITCH,
834 BNX2X_Q_FLG_ANTI_SPOOF,
835 BNX2X_Q_FLG_SILENT_VLAN_REM,
836 BNX2X_Q_FLG_FORCE_DEFAULT_PRI,
837 BNX2X_Q_FLG_REFUSE_OUTBAND_VLAN,
838 BNX2X_Q_FLG_PCSUM_ON_PKT,
839 BNX2X_Q_FLG_TUN_INC_INNER_IP_ID
842 /* Queue type options: queue type may be a combination of below. */
844 /** TODO: Consider moving both these flags into the init()
851 #define BNX2X_PRIMARY_CID_INDEX 0
852 #define BNX2X_MULTI_TX_COS_E1X 3 /* QM only */
853 #define BNX2X_MULTI_TX_COS_E2_E3A0 2
854 #define BNX2X_MULTI_TX_COS_E3B0 3
855 #define BNX2X_MULTI_TX_COS 3 /* Maximum possible */
857 #define MAC_PAD (ALIGN(ETH_ALEN, sizeof(u32)) - ETH_ALEN)
858 /* DMAE channel to be used by FW for timesync workaroun. A driver that sends
859 * timesync-related ramrods must not use this DMAE command ID.
861 #define FW_DMAE_CMD_ID 6
863 struct bnx2x_queue_init_params {
878 /* CID context in the host memory */
879 struct eth_context *cxts[BNX2X_MULTI_TX_COS];
881 /* maximum number of cos supported by hardware */
885 struct bnx2x_queue_terminate_params {
886 /* index within the tx_only cids of this queue object */
890 struct bnx2x_queue_cfc_del_params {
891 /* index within the tx_only cids of this queue object */
895 struct bnx2x_queue_update_params {
896 unsigned long update_flags; /* BNX2X_Q_UPDATE_XX bits */
898 u16 silent_removal_value;
899 u16 silent_removal_mask;
900 /* index within the tx_only cids of this queue object */
904 struct bnx2x_queue_update_tpa_params {
910 u8 complete_on_both_clients;
918 u16 sge_pause_thr_low;
919 u16 sge_pause_thr_high;
922 struct rxq_pause_params {
927 u16 sge_th_lo; /* valid iff BNX2X_Q_FLG_TPA */
928 u16 sge_th_hi; /* valid iff BNX2X_Q_FLG_TPA */
933 struct bnx2x_general_setup_params {
934 /* valid iff BNX2X_Q_FLG_STATS */
942 struct bnx2x_rxq_setup_params {
947 dma_addr_t rcq_np_map;
954 /* valid iff BNX2X_Q_FLG_TPA */
961 /* valid iff BNX2X_Q_FLG_MCAST */
968 /* valid iff BXN2X_Q_FLG_SILENT_VLAN_REM */
969 u16 silent_removal_value;
970 u16 silent_removal_mask;
973 struct bnx2x_txq_setup_params {
979 u8 cos; /* valid iff BNX2X_Q_FLG_COS */
981 /* equals to the leading rss client id, used for TX classification*/
982 u8 tss_leading_cl_id;
984 /* valid iff BNX2X_Q_FLG_DEF_VLAN */
988 struct bnx2x_queue_setup_params {
989 struct bnx2x_general_setup_params gen_params;
990 struct bnx2x_txq_setup_params txq_params;
991 struct bnx2x_rxq_setup_params rxq_params;
992 struct rxq_pause_params pause_params;
996 struct bnx2x_queue_setup_tx_only_params {
997 struct bnx2x_general_setup_params gen_params;
998 struct bnx2x_txq_setup_params txq_params;
1000 /* index within the tx_only cids of this queue object */
1004 struct bnx2x_queue_state_params {
1005 struct bnx2x_queue_sp_obj *q_obj;
1007 /* Current command */
1008 enum bnx2x_queue_cmd cmd;
1010 /* may have RAMROD_COMP_WAIT set only */
1011 unsigned long ramrod_flags;
1013 /* Params according to the current command */
1015 struct bnx2x_queue_update_params update;
1016 struct bnx2x_queue_update_tpa_params update_tpa;
1017 struct bnx2x_queue_setup_params setup;
1018 struct bnx2x_queue_init_params init;
1019 struct bnx2x_queue_setup_tx_only_params tx_only;
1020 struct bnx2x_queue_terminate_params terminate;
1021 struct bnx2x_queue_cfc_del_params cfc_del;
1025 struct bnx2x_viflist_params {
1027 u8 func_bit_map_res;
1030 struct bnx2x_queue_sp_obj {
1031 u32 cids[BNX2X_MULTI_TX_COS];
1035 /* number of traffic classes supported by queue.
1036 * The primary connection of the queue supports the first traffic
1037 * class. Any further traffic class is supported by a tx-only
1040 * Therefore max_cos is also a number of valid entries in the cids
1044 u8 num_tx_only, next_tx_only;
1046 enum bnx2x_q_state state, next_state;
1048 /* bits from enum bnx2x_q_type */
1051 /* BNX2X_Q_CMD_XX bits. This object implements "one
1052 * pending" paradigm but for debug and tracing purposes it's
1053 * more convenient to have different bits for different
1056 unsigned long pending;
1058 /* Buffer to use as a ramrod data and its mapping */
1060 dma_addr_t rdata_mapping;
1063 * Performs one state change according to the given parameters.
1065 * @return 0 in case of success and negative value otherwise.
1067 int (*send_cmd)(struct bnx2x *bp,
1068 struct bnx2x_queue_state_params *params);
1071 * Sets the pending bit according to the requested transition.
1073 int (*set_pending)(struct bnx2x_queue_sp_obj *o,
1074 struct bnx2x_queue_state_params *params);
1077 * Checks that the requested state transition is legal.
1079 int (*check_transition)(struct bnx2x *bp,
1080 struct bnx2x_queue_sp_obj *o,
1081 struct bnx2x_queue_state_params *params);
1084 * Completes the pending command.
1086 int (*complete_cmd)(struct bnx2x *bp,
1087 struct bnx2x_queue_sp_obj *o,
1088 enum bnx2x_queue_cmd);
1090 int (*wait_comp)(struct bnx2x *bp,
1091 struct bnx2x_queue_sp_obj *o,
1092 enum bnx2x_queue_cmd cmd);
1095 /********************** Function state update *********************************/
1097 /* UPDATE command options */
1099 BNX2X_F_UPDATE_TX_SWITCH_SUSPEND_CHNG,
1100 BNX2X_F_UPDATE_TX_SWITCH_SUSPEND,
1101 BNX2X_F_UPDATE_TUNNEL_CFG_CHNG,
1102 BNX2X_F_UPDATE_TUNNEL_CLSS_EN,
1103 BNX2X_F_UPDATE_TUNNEL_INNER_GRE_RSS_EN,
1106 /* Allowed Function states */
1107 enum bnx2x_func_state {
1108 BNX2X_F_STATE_RESET,
1109 BNX2X_F_STATE_INITIALIZED,
1110 BNX2X_F_STATE_STARTED,
1111 BNX2X_F_STATE_TX_STOPPED,
1115 /* Allowed Function commands */
1116 enum bnx2x_func_cmd {
1117 BNX2X_F_CMD_HW_INIT,
1120 BNX2X_F_CMD_HW_RESET,
1121 BNX2X_F_CMD_AFEX_UPDATE,
1122 BNX2X_F_CMD_AFEX_VIFLISTS,
1123 BNX2X_F_CMD_TX_STOP,
1124 BNX2X_F_CMD_TX_START,
1125 BNX2X_F_CMD_SWITCH_UPDATE,
1126 BNX2X_F_CMD_SET_TIMESYNC,
1130 struct bnx2x_func_hw_init_params {
1131 /* A load phase returned by MCP.
1134 * FW_MSG_CODE_DRV_LOAD_COMMON_CHIP
1135 * FW_MSG_CODE_DRV_LOAD_COMMON
1136 * FW_MSG_CODE_DRV_LOAD_PORT
1137 * FW_MSG_CODE_DRV_LOAD_FUNCTION
1142 struct bnx2x_func_hw_reset_params {
1143 /* A load phase returned by MCP.
1146 * FW_MSG_CODE_DRV_LOAD_COMMON_CHIP
1147 * FW_MSG_CODE_DRV_LOAD_COMMON
1148 * FW_MSG_CODE_DRV_LOAD_PORT
1149 * FW_MSG_CODE_DRV_LOAD_FUNCTION
1154 struct bnx2x_func_start_params {
1155 /* Multi Function mode:
1157 * - Switch Dependent
1158 * - Switch Independent
1162 /* Switch Dependent mode outer VLAN tag */
1165 /* Function cos mode */
1166 u8 network_cos_mode;
1168 /* TUNN_MODE_NONE/TUNN_MODE_VXLAN/TUNN_MODE_GRE */
1171 /* tunneling classification enablement */
1174 /* NVGRE_TUNNEL/L2GRE_TUNNEL/IPGRE_TUNNEL */
1177 /* Enables Inner GRE RSS on the function, depends on the client RSS
1180 u8 inner_gre_rss_en;
1183 struct bnx2x_func_switch_update_params {
1184 unsigned long changes; /* BNX2X_F_UPDATE_XX bits */
1189 struct bnx2x_func_afex_update_params {
1191 u16 afex_default_vlan;
1192 u8 allowed_priorities;
1195 struct bnx2x_func_afex_viflists_params {
1198 u8 afex_vif_list_command;
1202 struct bnx2x_func_tx_start_params {
1203 struct priority_cos traffic_type_to_priority_cos[MAX_TRAFFIC_TYPES];
1206 u8 dont_add_pri_0_en;
1209 struct bnx2x_func_set_timesync_params {
1210 /* Reset, set or keep the current drift value */
1211 u8 drift_adjust_cmd;
1213 /* Dec, inc or keep the current offset */
1216 /* Drift value direction */
1217 u8 add_sub_drift_adjust_value;
1219 /* Drift, period and offset values to be used according to the commands
1222 u8 drift_adjust_value;
1223 u32 drift_adjust_period;
1227 struct bnx2x_func_state_params {
1228 struct bnx2x_func_sp_obj *f_obj;
1230 /* Current command */
1231 enum bnx2x_func_cmd cmd;
1233 /* may have RAMROD_COMP_WAIT set only */
1234 unsigned long ramrod_flags;
1236 /* Params according to the current command */
1238 struct bnx2x_func_hw_init_params hw_init;
1239 struct bnx2x_func_hw_reset_params hw_reset;
1240 struct bnx2x_func_start_params start;
1241 struct bnx2x_func_switch_update_params switch_update;
1242 struct bnx2x_func_afex_update_params afex_update;
1243 struct bnx2x_func_afex_viflists_params afex_viflists;
1244 struct bnx2x_func_tx_start_params tx_start;
1245 struct bnx2x_func_set_timesync_params set_timesync;
1249 struct bnx2x_func_sp_drv_ops {
1250 /* Init tool + runtime initialization:
1252 * - Common (per Path)
1256 int (*init_hw_cmn_chip)(struct bnx2x *bp);
1257 int (*init_hw_cmn)(struct bnx2x *bp);
1258 int (*init_hw_port)(struct bnx2x *bp);
1259 int (*init_hw_func)(struct bnx2x *bp);
1261 /* Reset Function HW: Common, Port, Function phases. */
1262 void (*reset_hw_cmn)(struct bnx2x *bp);
1263 void (*reset_hw_port)(struct bnx2x *bp);
1264 void (*reset_hw_func)(struct bnx2x *bp);
1266 /* Init/Free GUNZIP resources */
1267 int (*gunzip_init)(struct bnx2x *bp);
1268 void (*gunzip_end)(struct bnx2x *bp);
1270 /* Prepare/Release FW resources */
1271 int (*init_fw)(struct bnx2x *bp);
1272 void (*release_fw)(struct bnx2x *bp);
1275 struct bnx2x_func_sp_obj {
1276 enum bnx2x_func_state state, next_state;
1278 /* BNX2X_FUNC_CMD_XX bits. This object implements "one
1279 * pending" paradigm but for debug and tracing purposes it's
1280 * more convenient to have different bits for different
1283 unsigned long pending;
1285 /* Buffer to use as a ramrod data and its mapping */
1287 dma_addr_t rdata_mapping;
1289 /* Buffer to use as a afex ramrod data and its mapping.
1290 * This can't be same rdata as above because afex ramrod requests
1291 * can arrive to the object in parallel to other ramrod requests.
1294 dma_addr_t afex_rdata_mapping;
1296 /* this mutex validates that when pending flag is taken, the next
1297 * ramrod to be sent will be the one set the pending bit
1299 struct mutex one_pending_mutex;
1301 /* Driver interface */
1302 struct bnx2x_func_sp_drv_ops *drv;
1305 * Performs one state change according to the given parameters.
1307 * @return 0 in case of success and negative value otherwise.
1309 int (*send_cmd)(struct bnx2x *bp,
1310 struct bnx2x_func_state_params *params);
1313 * Checks that the requested state transition is legal.
1315 int (*check_transition)(struct bnx2x *bp,
1316 struct bnx2x_func_sp_obj *o,
1317 struct bnx2x_func_state_params *params);
1320 * Completes the pending command.
1322 int (*complete_cmd)(struct bnx2x *bp,
1323 struct bnx2x_func_sp_obj *o,
1324 enum bnx2x_func_cmd cmd);
1326 int (*wait_comp)(struct bnx2x *bp, struct bnx2x_func_sp_obj *o,
1327 enum bnx2x_func_cmd cmd);
1330 /********************** Interfaces ********************************************/
1331 /* Queueable objects set */
1332 union bnx2x_qable_obj {
1333 struct bnx2x_vlan_mac_obj vlan_mac;
1335 /************** Function state update *********/
1336 void bnx2x_init_func_obj(struct bnx2x *bp,
1337 struct bnx2x_func_sp_obj *obj,
1338 void *rdata, dma_addr_t rdata_mapping,
1339 void *afex_rdata, dma_addr_t afex_rdata_mapping,
1340 struct bnx2x_func_sp_drv_ops *drv_iface);
1342 int bnx2x_func_state_change(struct bnx2x *bp,
1343 struct bnx2x_func_state_params *params);
1345 enum bnx2x_func_state bnx2x_func_get_state(struct bnx2x *bp,
1346 struct bnx2x_func_sp_obj *o);
1347 /******************* Queue State **************/
1348 void bnx2x_init_queue_obj(struct bnx2x *bp,
1349 struct bnx2x_queue_sp_obj *obj, u8 cl_id, u32 *cids,
1350 u8 cid_cnt, u8 func_id, void *rdata,
1351 dma_addr_t rdata_mapping, unsigned long type);
1353 int bnx2x_queue_state_change(struct bnx2x *bp,
1354 struct bnx2x_queue_state_params *params);
1356 int bnx2x_get_q_logical_state(struct bnx2x *bp,
1357 struct bnx2x_queue_sp_obj *obj);
1359 /********************* VLAN-MAC ****************/
1360 void bnx2x_init_mac_obj(struct bnx2x *bp,
1361 struct bnx2x_vlan_mac_obj *mac_obj,
1362 u8 cl_id, u32 cid, u8 func_id, void *rdata,
1363 dma_addr_t rdata_mapping, int state,
1364 unsigned long *pstate, bnx2x_obj_type type,
1365 struct bnx2x_credit_pool_obj *macs_pool);
1367 void bnx2x_init_vlan_obj(struct bnx2x *bp,
1368 struct bnx2x_vlan_mac_obj *vlan_obj,
1369 u8 cl_id, u32 cid, u8 func_id, void *rdata,
1370 dma_addr_t rdata_mapping, int state,
1371 unsigned long *pstate, bnx2x_obj_type type,
1372 struct bnx2x_credit_pool_obj *vlans_pool);
1374 int bnx2x_vlan_mac_h_read_lock(struct bnx2x *bp,
1375 struct bnx2x_vlan_mac_obj *o);
1376 void bnx2x_vlan_mac_h_read_unlock(struct bnx2x *bp,
1377 struct bnx2x_vlan_mac_obj *o);
1378 int bnx2x_vlan_mac_h_write_lock(struct bnx2x *bp,
1379 struct bnx2x_vlan_mac_obj *o);
1380 int bnx2x_config_vlan_mac(struct bnx2x *bp,
1381 struct bnx2x_vlan_mac_ramrod_params *p);
1383 int bnx2x_vlan_mac_move(struct bnx2x *bp,
1384 struct bnx2x_vlan_mac_ramrod_params *p,
1385 struct bnx2x_vlan_mac_obj *dest_o);
1387 /********************* RX MODE ****************/
1389 void bnx2x_init_rx_mode_obj(struct bnx2x *bp,
1390 struct bnx2x_rx_mode_obj *o);
1393 * bnx2x_config_rx_mode - Send and RX_MODE ramrod according to the provided parameters.
1395 * @p: Command parameters
1397 * Return: 0 - if operation was successful and there is no pending completions,
1398 * positive number - if there are pending completions,
1399 * negative - if there were errors
1401 int bnx2x_config_rx_mode(struct bnx2x *bp,
1402 struct bnx2x_rx_mode_ramrod_params *p);
1404 /****************** MULTICASTS ****************/
1406 void bnx2x_init_mcast_obj(struct bnx2x *bp,
1407 struct bnx2x_mcast_obj *mcast_obj,
1408 u8 mcast_cl_id, u32 mcast_cid, u8 func_id,
1409 u8 engine_id, void *rdata, dma_addr_t rdata_mapping,
1410 int state, unsigned long *pstate,
1411 bnx2x_obj_type type);
1414 * bnx2x_config_mcast - Configure multicast MACs list.
1416 * @cmd: command to execute: BNX2X_MCAST_CMD_X
1418 * May configure a new list
1419 * provided in p->mcast_list (BNX2X_MCAST_CMD_ADD), clean up
1420 * (BNX2X_MCAST_CMD_DEL) or restore (BNX2X_MCAST_CMD_RESTORE) a current
1421 * configuration, continue to execute the pending commands
1422 * (BNX2X_MCAST_CMD_CONT).
1424 * If previous command is still pending or if number of MACs to
1425 * configure is more that maximum number of MACs in one command,
1426 * the current command will be enqueued to the tail of the
1427 * pending commands list.
1429 * Return: 0 is operation was successful and there are no pending completions,
1430 * negative if there were errors, positive if there are pending
1433 int bnx2x_config_mcast(struct bnx2x *bp,
1434 struct bnx2x_mcast_ramrod_params *p,
1435 enum bnx2x_mcast_cmd cmd);
1437 /****************** CREDIT POOL ****************/
1438 void bnx2x_init_mac_credit_pool(struct bnx2x *bp,
1439 struct bnx2x_credit_pool_obj *p, u8 func_id,
1441 void bnx2x_init_vlan_credit_pool(struct bnx2x *bp,
1442 struct bnx2x_credit_pool_obj *p, u8 func_id,
1445 /****************** RSS CONFIGURATION ****************/
1446 void bnx2x_init_rss_config_obj(struct bnx2x *bp,
1447 struct bnx2x_rss_config_obj *rss_obj,
1448 u8 cl_id, u32 cid, u8 func_id, u8 engine_id,
1449 void *rdata, dma_addr_t rdata_mapping,
1450 int state, unsigned long *pstate,
1451 bnx2x_obj_type type);
1454 * bnx2x_config_rss - Updates RSS configuration according to provided parameters
1456 * Return: 0 in case of success
1458 int bnx2x_config_rss(struct bnx2x *bp,
1459 struct bnx2x_config_rss_params *p);
1462 * bnx2x_get_rss_ind_table - Return the current ind_table configuration.
1464 * @ind_table: buffer to fill with the current indirection
1465 * table content. Should be at least
1466 * T_ETH_INDIRECTION_TABLE_SIZE bytes long.
1468 void bnx2x_get_rss_ind_table(struct bnx2x_rss_config_obj *rss_obj,
1471 #endif /* BNX2X_SP_VERBS */