drivers/net/ethernet/broadcom/bnx2x/bnx2x_sp.c

   1 /* bnx2x_sp.c: Qlogic Everest network driver.
   2  *
   3  * Copyright 2011-2013 Broadcom Corporation
   4  * Copyright (c) 2014 QLogic Corporation
   5  * All rights reserved
   6  *
   7  * Unless you and Qlogic execute a separate written software license
   8  * agreement governing use of this software, this software is licensed to you
   9  * under the terms of the GNU General Public License version 2, available
  10  * at http://www.gnu.org/licenses/gpl-2.0.html (the "GPL").
  11  *
  12  * Notwithstanding the above, under no circumstances may you combine this
  13  * software in any way with any other Qlogic software provided under a
  14  * license other than the GPL, without Qlogic's express prior written
  15  * consent.
  16  *
  17  * Maintained by: Ariel Elior <ariel.elior@qlogic.com>
  18  * Written by: Vladislav Zolotarov
  19  *
  20  */
  21
  22 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
  23
  24 #include <linux/module.h>
  25 #include <linux/crc32.h>
  26 #include <linux/netdevice.h>
  27 #include <linux/etherdevice.h>
  28 #include <linux/crc32c.h>
  29 #include "bnx2x.h"
  30 #include "bnx2x_cmn.h"
  31 #include "bnx2x_sp.h"
  32
  33 #define BNX2X_MAX_EMUL_MULTI            16
  34
  35 /**** Exe Queue interfaces ****/
  36
  37 /**
  38  * bnx2x_exe_queue_init - init the Exe Queue object
  39  *
  40  * @o:          pointer to the object
  41  * @exe_len:    length
  42  * @owner:      pointer to the owner
  43  * @validate:   validate function pointer
  44  * @optimize:   optimize function pointer
  45  * @exec:       execute function pointer
  46  * @get:        get function pointer
  47  */
  48 static inline void bnx2x_exe_queue_init(struct bnx2x *bp,
  49                                         struct bnx2x_exe_queue_obj *o,
  50                                         int exe_len,
  51                                         union bnx2x_qable_obj *owner,
  52                                         exe_q_validate validate,
  53                                         exe_q_remove remove,
  54                                         exe_q_optimize optimize,
  55                                         exe_q_execute exec,
  56                                         exe_q_get get)
  57 {
  58         memset(o, 0, sizeof(*o));
  59
  60         INIT_LIST_HEAD(&o->exe_queue);
  61         INIT_LIST_HEAD(&o->pending_comp);
  62
  63         spin_lock_init(&o->lock);
  64
  65         o->exe_chunk_len = exe_len;
  66         o->owner         = owner;
  67
  68         /* Owner specific callbacks */
  69         o->validate      = validate;
  70         o->remove        = remove;
  71         o->optimize      = optimize;
  72         o->execute       = exec;
  73         o->get           = get;
  74
  75         DP(BNX2X_MSG_SP, "Setup the execution queue with the chunk length of %d\n",
  76            exe_len);
  77 }
  78
  79 static inline void bnx2x_exe_queue_free_elem(struct bnx2x *bp,
  80                                              struct bnx2x_exeq_elem *elem)
  81 {
  82         DP(BNX2X_MSG_SP, "Deleting an exe_queue element\n");
  83         kfree(elem);
  84 }
  85
  86 static inline int bnx2x_exe_queue_length(struct bnx2x_exe_queue_obj *o)
  87 {
  88         struct bnx2x_exeq_elem *elem;
  89         int cnt = 0;
  90
  91         spin_lock_bh(&o->lock);
  92
  93         list_for_each_entry(elem, &o->exe_queue, link)
  94                 cnt++;
  95
  96         spin_unlock_bh(&o->lock);
  97
  98         return cnt;
  99 }
 100
 101 /**
 102  * bnx2x_exe_queue_add - add a new element to the execution queue
 103  *
 104  * @bp:         driver handle
 105  * @o:          queue
 106  * @cmd:        new command to add
 107  * @restore:    true - do not optimize the command
 108  *
 109  * If the element is optimized or is illegal, frees it.
 110  */
 111 static inline int bnx2x_exe_queue_add(struct bnx2x *bp,
 112                                       struct bnx2x_exe_queue_obj *o,
 113                                       struct bnx2x_exeq_elem *elem,
 114                                       bool restore)
 115 {
 116         int rc;
 117
 118         spin_lock_bh(&o->lock);
 119
 120         if (!restore) {
 121                 /* Try to cancel this element queue */
 122                 rc = o->optimize(bp, o->owner, elem);
 123                 if (rc)
 124                         goto free_and_exit;
 125
 126                 /* Check if this request is ok */
 127                 rc = o->validate(bp, o->owner, elem);
 128                 if (rc) {
 129                         DP(BNX2X_MSG_SP, "Preamble failed: %d\n", rc);
 130                         goto free_and_exit;
 131                 }
 132         }
 133
 134         /* If so, add it to the execution queue */
 135         list_add_tail(&elem->link, &o->exe_queue);
 136
 137         spin_unlock_bh(&o->lock);
 138
 139         return 0;
 140
 141 free_and_exit:
 142         bnx2x_exe_queue_free_elem(bp, elem);
 143
 144         spin_unlock_bh(&o->lock);
 145
 146         return rc;
 147 }
 148
 149 static inline void __bnx2x_exe_queue_reset_pending(
 150         struct bnx2x *bp,
 151         struct bnx2x_exe_queue_obj *o)
 152 {
 153         struct bnx2x_exeq_elem *elem;
 154
 155         while (!list_empty(&o->pending_comp)) {
 156                 elem = list_first_entry(&o->pending_comp,
 157                                         struct bnx2x_exeq_elem, link);
 158
 159                 list_del(&elem->link);
 160                 bnx2x_exe_queue_free_elem(bp, elem);
 161         }
 162 }
 163
 164 /**
 165  * bnx2x_exe_queue_step - execute one execution chunk atomically
 166  *
 167  * @bp:                 driver handle
 168  * @o:                  queue
 169  * @ramrod_flags:       flags
 170  *
 171  * (Should be called while holding the exe_queue->lock).
 172  */
 173 static inline int bnx2x_exe_queue_step(struct bnx2x *bp,
 174                                        struct bnx2x_exe_queue_obj *o,
 175                                        unsigned long *ramrod_flags)
 176 {
 177         struct bnx2x_exeq_elem *elem, spacer;
 178         int cur_len = 0, rc;
 179
 180         memset(&spacer, 0, sizeof(spacer));
 181
 182         /* Next step should not be performed until the current is finished,
 183          * unless a DRV_CLEAR_ONLY bit is set. In this case we just want to
 184          * properly clear object internals without sending any command to the FW
 185          * which also implies there won't be any completion to clear the
 186          * 'pending' list.
 187          */
 188         if (!list_empty(&o->pending_comp)) {
 189                 if (test_bit(RAMROD_DRV_CLR_ONLY, ramrod_flags)) {
 190                         DP(BNX2X_MSG_SP, "RAMROD_DRV_CLR_ONLY requested: resetting a pending_comp list\n");
 191                         __bnx2x_exe_queue_reset_pending(bp, o);
 192                 } else {
 193                         return 1;
 194                 }
 195         }
 196
 197         /* Run through the pending commands list and create a next
 198          * execution chunk.
 199          */
 200         while (!list_empty(&o->exe_queue)) {
 201                 elem = list_first_entry(&o->exe_queue, struct bnx2x_exeq_elem,
 202                                         link);
 203                 WARN_ON(!elem->cmd_len);
 204
 205                 if (cur_len + elem->cmd_len <= o->exe_chunk_len) {
 206                         cur_len += elem->cmd_len;
 207                         /* Prevent from both lists being empty when moving an
 208                          * element. This will allow the call of
 209                          * bnx2x_exe_queue_empty() without locking.
 210                          */
 211                         list_add_tail(&spacer.link, &o->pending_comp);
 212                         mb();
 213                         list_move_tail(&elem->link, &o->pending_comp);
 214                         list_del(&spacer.link);
 215                 } else
 216                         break;
 217         }
 218
 219         /* Sanity check */
 220         if (!cur_len)
 221                 return 0;
 222
 223         rc = o->execute(bp, o->owner, &o->pending_comp, ramrod_flags);
 224         if (rc < 0)
 225                 /* In case of an error return the commands back to the queue
 226                  * and reset the pending_comp.
 227                  */
 228                 list_splice_init(&o->pending_comp, &o->exe_queue);
 229         else if (!rc)
 230                 /* If zero is returned, means there are no outstanding pending
 231                  * completions and we may dismiss the pending list.
 232                  */
 233                 __bnx2x_exe_queue_reset_pending(bp, o);
 234
 235         return rc;
 236 }
 237
 238 static inline bool bnx2x_exe_queue_empty(struct bnx2x_exe_queue_obj *o)
 239 {
 240         bool empty = list_empty(&o->exe_queue);
 241
 242         /* Don't reorder!!! */
 243         mb();
 244
 245         return empty && list_empty(&o->pending_comp);
 246 }
 247
 248 static inline struct bnx2x_exeq_elem *bnx2x_exe_queue_alloc_elem(
 249         struct bnx2x *bp)
 250 {
 251         DP(BNX2X_MSG_SP, "Allocating a new exe_queue element\n");
 252         return kzalloc(sizeof(struct bnx2x_exeq_elem), GFP_ATOMIC);
 253 }
 254
 255 /************************ raw_obj functions ***********************************/
 256 static bool bnx2x_raw_check_pending(struct bnx2x_raw_obj *o)
 257 {
 258         return !!test_bit(o->state, o->pstate);
 259 }
 260
 261 static void bnx2x_raw_clear_pending(struct bnx2x_raw_obj *o)
 262 {
 263         smp_mb__before_atomic();
 264         clear_bit(o->state, o->pstate);
 265         smp_mb__after_atomic();
 266 }
 267
 268 static void bnx2x_raw_set_pending(struct bnx2x_raw_obj *o)
 269 {
 270         smp_mb__before_atomic();
 271         set_bit(o->state, o->pstate);
 272         smp_mb__after_atomic();
 273 }
 274
 275 /**
 276  * bnx2x_state_wait - wait until the given bit(state) is cleared
 277  *
 278  * @bp:         device handle
 279  * @state:      state which is to be cleared
 280  * @state_p:    state buffer
 281  *
 282  */
 283 static inline int bnx2x_state_wait(struct bnx2x *bp, int state,
 284                                    unsigned long *pstate)
 285 {
 286         /* can take a while if any port is running */
 287         int cnt = 5000;
 288
 289         if (CHIP_REV_IS_EMUL(bp))
 290                 cnt *= 20;
 291
 292         DP(BNX2X_MSG_SP, "waiting for state to become %d\n", state);
 293
 294         might_sleep();
 295         while (cnt--) {
 296                 if (!test_bit(state, pstate)) {
 297 #ifdef BNX2X_STOP_ON_ERROR
 298                         DP(BNX2X_MSG_SP, "exit  (cnt %d)\n", 5000 - cnt);
 299 #endif
 300                         return 0;
 301                 }
 302
 303                 usleep_range(1000, 2000);
 304
 305                 if (bp->panic)
 306                         return -EIO;
 307         }
 308
 309         /* timeout! */
 310         BNX2X_ERR("timeout waiting for state %d\n", state);
 311 #ifdef BNX2X_STOP_ON_ERROR
 312         bnx2x_panic();
 313 #endif
 314
 315         return -EBUSY;
 316 }
 317
 318 static int bnx2x_raw_wait(struct bnx2x *bp, struct bnx2x_raw_obj *raw)
 319 {
 320         return bnx2x_state_wait(bp, raw->state, raw->pstate);
 321 }
 322
 323 /***************** Classification verbs: Set/Del MAC/VLAN/VLAN-MAC ************/
 324 /* credit handling callbacks */
 325 static bool bnx2x_get_cam_offset_mac(struct bnx2x_vlan_mac_obj *o, int *offset)
 326 {
 327         struct bnx2x_credit_pool_obj *mp = o->macs_pool;
 328
 329         WARN_ON(!mp);
 330
 331         return mp->get_entry(mp, offset);
 332 }
 333
 334 static bool bnx2x_get_credit_mac(struct bnx2x_vlan_mac_obj *o)
 335 {
 336         struct bnx2x_credit_pool_obj *mp = o->macs_pool;
 337
 338         WARN_ON(!mp);
 339
 340         return mp->get(mp, 1);
 341 }
 342
 343 static bool bnx2x_get_cam_offset_vlan(struct bnx2x_vlan_mac_obj *o, int *offset)
 344 {
 345         struct bnx2x_credit_pool_obj *vp = o->vlans_pool;
 346
 347         WARN_ON(!vp);
 348
 349         return vp->get_entry(vp, offset);
 350 }
 351
 352 static bool bnx2x_get_credit_vlan(struct bnx2x_vlan_mac_obj *o)
 353 {
 354         struct bnx2x_credit_pool_obj *vp = o->vlans_pool;
 355
 356         WARN_ON(!vp);
 357
 358         return vp->get(vp, 1);
 359 }
 360 static bool bnx2x_put_cam_offset_mac(struct bnx2x_vlan_mac_obj *o, int offset)
 361 {
 362         struct bnx2x_credit_pool_obj *mp = o->macs_pool;
 363
 364         return mp->put_entry(mp, offset);
 365 }
 366
 367 static bool bnx2x_put_credit_mac(struct bnx2x_vlan_mac_obj *o)
 368 {
 369         struct bnx2x_credit_pool_obj *mp = o->macs_pool;
 370
 371         return mp->put(mp, 1);
 372 }
 373
 374 static bool bnx2x_put_cam_offset_vlan(struct bnx2x_vlan_mac_obj *o, int offset)
 375 {
 376         struct bnx2x_credit_pool_obj *vp = o->vlans_pool;
 377
 378         return vp->put_entry(vp, offset);
 379 }
 380
 381 static bool bnx2x_put_credit_vlan(struct bnx2x_vlan_mac_obj *o)
 382 {
 383         struct bnx2x_credit_pool_obj *vp = o->vlans_pool;
 384
 385         return vp->put(vp, 1);
 386 }
 387
 388 /**
 389  * __bnx2x_vlan_mac_h_write_trylock - try getting the vlan mac writer lock
 390  *
 391  * @bp:         device handle
 392  * @o:          vlan_mac object
 393  *
 394  * @details: Non-blocking implementation; should be called under execution
 395  *           queue lock.
 396  */
 397 static int __bnx2x_vlan_mac_h_write_trylock(struct bnx2x *bp,
 398                                             struct bnx2x_vlan_mac_obj *o)
 399 {
 400         if (o->head_reader) {
 401                 DP(BNX2X_MSG_SP, "vlan_mac_lock writer - There are readers; Busy\n");
 402                 return -EBUSY;
 403         }
 404
 405         DP(BNX2X_MSG_SP, "vlan_mac_lock writer - Taken\n");
 406         return 0;
 407 }
 408
 409 /**
 410  * __bnx2x_vlan_mac_h_exec_pending - execute step instead of a previous step
 411  *
 412  * @bp:         device handle
 413  * @o:          vlan_mac object
 414  *
 415  * @details Should be called under execution queue lock; notice it might release
 416  *          and reclaim it during its run.
 417  */
 418 static void __bnx2x_vlan_mac_h_exec_pending(struct bnx2x *bp,
 419                                             struct bnx2x_vlan_mac_obj *o)
 420 {
 421         int rc;
 422         unsigned long ramrod_flags = o->saved_ramrod_flags;
 423
 424         DP(BNX2X_MSG_SP, "vlan_mac_lock execute pending command with ramrod flags %lu\n",
 425            ramrod_flags);
 426         o->head_exe_request = false;
 427         o->saved_ramrod_flags = 0;
 428         rc = bnx2x_exe_queue_step(bp, &o->exe_queue, &ramrod_flags);
 429         if ((rc != 0) && (rc != 1)) {
 430                 BNX2X_ERR("execution of pending commands failed with rc %d\n",
 431                           rc);
 432 #ifdef BNX2X_STOP_ON_ERROR
 433                 bnx2x_panic();
 434 #endif
 435         }
 436 }
 437
 438 /**
 439  * __bnx2x_vlan_mac_h_pend - Pend an execution step which couldn't run
 440  *
 441  * @bp:                 device handle
 442  * @o:                  vlan_mac object
 443  * @ramrod_flags:       ramrod flags of missed execution
 444  *
 445  * @details Should be called under execution queue lock.
 446  */
 447 static void __bnx2x_vlan_mac_h_pend(struct bnx2x *bp,
 448                                     struct bnx2x_vlan_mac_obj *o,
 449                                     unsigned long ramrod_flags)
 450 {
 451         o->head_exe_request = true;
 452         o->saved_ramrod_flags = ramrod_flags;
 453         DP(BNX2X_MSG_SP, "Placing pending execution with ramrod flags %lu\n",
 454            ramrod_flags);
 455 }
 456
 457 /**
 458  * __bnx2x_vlan_mac_h_write_unlock - unlock the vlan mac head list writer lock
 459  *
 460  * @bp:                 device handle
 461  * @o:                  vlan_mac object
 462  *
 463  * @details Should be called under execution queue lock. Notice if a pending
 464  *          execution exists, it would perform it - possibly releasing and
 465  *          reclaiming the execution queue lock.
 466  */
 467 static void __bnx2x_vlan_mac_h_write_unlock(struct bnx2x *bp,
 468                                             struct bnx2x_vlan_mac_obj *o)
 469 {
 470         /* It's possible a new pending execution was added since this writer
 471          * executed. If so, execute again. [Ad infinitum]
 472          */
 473         while (o->head_exe_request) {
 474                 DP(BNX2X_MSG_SP, "vlan_mac_lock - writer release encountered a pending request\n");
 475                 __bnx2x_vlan_mac_h_exec_pending(bp, o);
 476         }
 477 }
 478
 479
 480 /**
 481  * __bnx2x_vlan_mac_h_read_lock - lock the vlan mac head list reader lock
 482  *
 483  * @bp:                 device handle
 484  * @o:                  vlan_mac object
 485  *
 486  * @details Should be called under the execution queue lock. May sleep. May
 487  *          release and reclaim execution queue lock during its run.
 488  */
 489 static int __bnx2x_vlan_mac_h_read_lock(struct bnx2x *bp,
 490                                         struct bnx2x_vlan_mac_obj *o)
 491 {
 492         /* If we got here, we're holding lock --> no WRITER exists */
 493         o->head_reader++;
 494         DP(BNX2X_MSG_SP, "vlan_mac_lock - locked reader - number %d\n",
 495            o->head_reader);
 496
 497         return 0;
 498 }
 499
 500 /**
 501  * bnx2x_vlan_mac_h_read_lock - lock the vlan mac head list reader lock
 502  *
 503  * @bp:                 device handle
 504  * @o:                  vlan_mac object
 505  *
 506  * @details May sleep. Claims and releases execution queue lock during its run.
 507  */
 508 int bnx2x_vlan_mac_h_read_lock(struct bnx2x *bp,
 509                                struct bnx2x_vlan_mac_obj *o)
 510 {
 511         int rc;
 512
 513         spin_lock_bh(&o->exe_queue.lock);
 514         rc = __bnx2x_vlan_mac_h_read_lock(bp, o);
 515         spin_unlock_bh(&o->exe_queue.lock);
 516
 517         return rc;
 518 }
 519
 520 /**
 521  * __bnx2x_vlan_mac_h_read_unlock - unlock the vlan mac head list reader lock
 522  *
 523  * @bp:                 device handle
 524  * @o:                  vlan_mac object
 525  *
 526  * @details Should be called under execution queue lock. Notice if a pending
 527  *          execution exists, it would be performed if this was the last
 528  *          reader. possibly releasing and reclaiming the execution queue lock.
 529  */
 530 static void __bnx2x_vlan_mac_h_read_unlock(struct bnx2x *bp,
 531                                           struct bnx2x_vlan_mac_obj *o)
 532 {
 533         if (!o->head_reader) {
 534                 BNX2X_ERR("Need to release vlan mac reader lock, but lock isn't taken\n");
 535 #ifdef BNX2X_STOP_ON_ERROR
 536                 bnx2x_panic();
 537 #endif
 538         } else {
 539                 o->head_reader--;
 540                 DP(BNX2X_MSG_SP, "vlan_mac_lock - decreased readers to %d\n",
 541                    o->head_reader);
 542         }
 543
 544         /* It's possible a new pending execution was added, and that this reader
 545          * was last - if so we need to execute the command.
 546          */
 547         if (!o->head_reader && o->head_exe_request) {
 548                 DP(BNX2X_MSG_SP, "vlan_mac_lock - reader release encountered a pending request\n");
 549
 550                 /* Writer release will do the trick */
 551                 __bnx2x_vlan_mac_h_write_unlock(bp, o);
 552         }
 553 }
 554
 555 /**
 556  * bnx2x_vlan_mac_h_read_unlock - unlock the vlan mac head list reader lock
 557  *
 558  * @bp:                 device handle
 559  * @o:                  vlan_mac object
 560  *
 561  * @details Notice if a pending execution exists, it would be performed if this
 562  *          was the last reader. Claims and releases the execution queue lock
 563  *          during its run.
 564  */
 565 void bnx2x_vlan_mac_h_read_unlock(struct bnx2x *bp,
 566                                   struct bnx2x_vlan_mac_obj *o)
 567 {
 568         spin_lock_bh(&o->exe_queue.lock);
 569         __bnx2x_vlan_mac_h_read_unlock(bp, o);
 570         spin_unlock_bh(&o->exe_queue.lock);
 571 }
 572
 573 static int bnx2x_get_n_elements(struct bnx2x *bp, struct bnx2x_vlan_mac_obj *o,
 574                                 int n, u8 *base, u8 stride, u8 size)
 575 {
 576         struct bnx2x_vlan_mac_registry_elem *pos;
 577         u8 *next = base;
 578         int counter = 0;
 579         int read_lock;
 580
 581         DP(BNX2X_MSG_SP, "get_n_elements - taking vlan_mac_lock (reader)\n");
 582         read_lock = bnx2x_vlan_mac_h_read_lock(bp, o);
 583         if (read_lock != 0)
 584                 BNX2X_ERR("get_n_elements failed to get vlan mac reader lock; Access without lock\n");
 585
 586         /* traverse list */
 587         list_for_each_entry(pos, &o->head, link) {
 588                 if (counter < n) {
 589                         memcpy(next, &pos->u, size);
 590                         counter++;
 591                         DP(BNX2X_MSG_SP, "copied element number %d to address %p element was:\n",
 592                            counter, next);
 593                         next += stride + size;
 594                 }
 595         }
 596
 597         if (read_lock == 0) {
 598                 DP(BNX2X_MSG_SP, "get_n_elements - releasing vlan_mac_lock (reader)\n");
 599                 bnx2x_vlan_mac_h_read_unlock(bp, o);
 600         }
 601
 602         return counter * ETH_ALEN;
 603 }
 604
 605 /* check_add() callbacks */
 606 static int bnx2x_check_mac_add(struct bnx2x *bp,
 607                                struct bnx2x_vlan_mac_obj *o,
 608                                union bnx2x_classification_ramrod_data *data)
 609 {
 610         struct bnx2x_vlan_mac_registry_elem *pos;
 611
 612         DP(BNX2X_MSG_SP, "Checking MAC %pM for ADD command\n", data->mac.mac);
 613
 614         if (!is_valid_ether_addr(data->mac.mac))
 615                 return -EINVAL;
 616
 617         /* Check if a requested MAC already exists */
 618         list_for_each_entry(pos, &o->head, link)
 619                 if (ether_addr_equal(data->mac.mac, pos->u.mac.mac) &&
 620                     (data->mac.is_inner_mac == pos->u.mac.is_inner_mac))
 621                         return -EEXIST;
 622
 623         return 0;
 624 }
 625
 626 static int bnx2x_check_vlan_add(struct bnx2x *bp,
 627                                 struct bnx2x_vlan_mac_obj *o,
 628                                 union bnx2x_classification_ramrod_data *data)
 629 {
 630         struct bnx2x_vlan_mac_registry_elem *pos;
 631
 632         DP(BNX2X_MSG_SP, "Checking VLAN %d for ADD command\n", data->vlan.vlan);
 633
 634         list_for_each_entry(pos, &o->head, link)
 635                 if (data->vlan.vlan == pos->u.vlan.vlan)
 636                         return -EEXIST;
 637
 638         return 0;
 639 }
 640
 641 /* check_del() callbacks */
 642 static struct bnx2x_vlan_mac_registry_elem *
 643         bnx2x_check_mac_del(struct bnx2x *bp,
 644                             struct bnx2x_vlan_mac_obj *o,
 645                             union bnx2x_classification_ramrod_data *data)
 646 {
 647         struct bnx2x_vlan_mac_registry_elem *pos;
 648
 649         DP(BNX2X_MSG_SP, "Checking MAC %pM for DEL command\n", data->mac.mac);
 650
 651         list_for_each_entry(pos, &o->head, link)
 652                 if (ether_addr_equal(data->mac.mac, pos->u.mac.mac) &&
 653                     (data->mac.is_inner_mac == pos->u.mac.is_inner_mac))
 654                         return pos;
 655
 656         return NULL;
 657 }
 658
 659 static struct bnx2x_vlan_mac_registry_elem *
 660         bnx2x_check_vlan_del(struct bnx2x *bp,
 661                              struct bnx2x_vlan_mac_obj *o,
 662                              union bnx2x_classification_ramrod_data *data)
 663 {
 664         struct bnx2x_vlan_mac_registry_elem *pos;
 665
 666         DP(BNX2X_MSG_SP, "Checking VLAN %d for DEL command\n", data->vlan.vlan);
 667
 668         list_for_each_entry(pos, &o->head, link)
 669                 if (data->vlan.vlan == pos->u.vlan.vlan)
 670                         return pos;
 671
 672         return NULL;
 673 }
 674
 675 /* check_move() callback */
 676 static bool bnx2x_check_move(struct bnx2x *bp,
 677                              struct bnx2x_vlan_mac_obj *src_o,
 678                              struct bnx2x_vlan_mac_obj *dst_o,
 679                              union bnx2x_classification_ramrod_data *data)
 680 {
 681         struct bnx2x_vlan_mac_registry_elem *pos;
 682         int rc;
 683
 684         /* Check if we can delete the requested configuration from the first
 685          * object.
 686          */
 687         pos = src_o->check_del(bp, src_o, data);
 688
 689         /*  check if configuration can be added */
 690         rc = dst_o->check_add(bp, dst_o, data);
 691
 692         /* If this classification can not be added (is already set)
 693          * or can't be deleted - return an error.
 694          */
 695         if (rc || !pos)
 696                 return false;
 697
 698         return true;
 699 }
 700
 701 static bool bnx2x_check_move_always_err(
 702         struct bnx2x *bp,
 703         struct bnx2x_vlan_mac_obj *src_o,
 704         struct bnx2x_vlan_mac_obj *dst_o,
 705         union bnx2x_classification_ramrod_data *data)
 706 {
 707         return false;
 708 }
 709
 710 static inline u8 bnx2x_vlan_mac_get_rx_tx_flag(struct bnx2x_vlan_mac_obj *o)
 711 {
 712         struct bnx2x_raw_obj *raw = &o->raw;
 713         u8 rx_tx_flag = 0;
 714
 715         if ((raw->obj_type == BNX2X_OBJ_TYPE_TX) ||
 716             (raw->obj_type == BNX2X_OBJ_TYPE_RX_TX))
 717                 rx_tx_flag |= ETH_CLASSIFY_CMD_HEADER_TX_CMD;
 718
 719         if ((raw->obj_type == BNX2X_OBJ_TYPE_RX) ||
 720             (raw->obj_type == BNX2X_OBJ_TYPE_RX_TX))
 721                 rx_tx_flag |= ETH_CLASSIFY_CMD_HEADER_RX_CMD;
 722
 723         return rx_tx_flag;
 724 }
 725
 726 static void bnx2x_set_mac_in_nig(struct bnx2x *bp,
 727                                  bool add, unsigned char *dev_addr, int index)
 728 {
 729         u32 wb_data[2];
 730         u32 reg_offset = BP_PORT(bp) ? NIG_REG_LLH1_FUNC_MEM :
 731                          NIG_REG_LLH0_FUNC_MEM;
 732
 733         if (!IS_MF_SI(bp) && !IS_MF_AFEX(bp))
 734                 return;
 735
 736         if (index > BNX2X_LLH_CAM_MAX_PF_LINE)
 737                 return;
 738
 739         DP(BNX2X_MSG_SP, "Going to %s LLH configuration at entry %d\n",
 740                          (add ? "ADD" : "DELETE"), index);
 741
 742         if (add) {
 743                 /* LLH_FUNC_MEM is a u64 WB register */
 744                 reg_offset += 8*index;
 745
 746                 wb_data[0] = ((dev_addr[2] << 24) | (dev_addr[3] << 16) |
 747                               (dev_addr[4] <<  8) |  dev_addr[5]);
 748                 wb_data[1] = ((dev_addr[0] <<  8) |  dev_addr[1]);
 749
 750                 REG_WR_DMAE(bp, reg_offset, wb_data, 2);
 751         }
 752
 753         REG_WR(bp, (BP_PORT(bp) ? NIG_REG_LLH1_FUNC_MEM_ENABLE :
 754                                   NIG_REG_LLH0_FUNC_MEM_ENABLE) + 4*index, add);
 755 }
 756
 757 /**
 758  * bnx2x_vlan_mac_set_cmd_hdr_e2 - set a header in a single classify ramrod
 759  *
 760  * @bp:         device handle
 761  * @o:          queue for which we want to configure this rule
 762  * @add:        if true the command is an ADD command, DEL otherwise
 763  * @opcode:     CLASSIFY_RULE_OPCODE_XXX
 764  * @hdr:        pointer to a header to setup
 765  *
 766  */
 767 static inline void bnx2x_vlan_mac_set_cmd_hdr_e2(struct bnx2x *bp,
 768         struct bnx2x_vlan_mac_obj *o, bool add, int opcode,
 769         struct eth_classify_cmd_header *hdr)
 770 {
 771         struct bnx2x_raw_obj *raw = &o->raw;
 772
 773         hdr->client_id = raw->cl_id;
 774         hdr->func_id = raw->func_id;
 775
 776         /* Rx or/and Tx (internal switching) configuration ? */
 777         hdr->cmd_general_data |=
 778                 bnx2x_vlan_mac_get_rx_tx_flag(o);
 779
 780         if (add)
 781                 hdr->cmd_general_data |= ETH_CLASSIFY_CMD_HEADER_IS_ADD;
 782
 783         hdr->cmd_general_data |=
 784                 (opcode << ETH_CLASSIFY_CMD_HEADER_OPCODE_SHIFT);
 785 }
 786
 787 /**
 788  * bnx2x_vlan_mac_set_rdata_hdr_e2 - set the classify ramrod data header
 789  *
 790  * @cid:        connection id
 791  * @type:       BNX2X_FILTER_XXX_PENDING
 792  * @hdr:        pointer to header to setup
 793  * @rule_cnt:
 794  *
 795  * currently we always configure one rule and echo field to contain a CID and an
 796  * opcode type.
 797  */
 798 static inline void bnx2x_vlan_mac_set_rdata_hdr_e2(u32 cid, int type,
 799                                 struct eth_classify_header *hdr, int rule_cnt)
 800 {
 801         hdr->echo = cpu_to_le32((cid & BNX2X_SWCID_MASK) |
 802                                 (type << BNX2X_SWCID_SHIFT));
 803         hdr->rule_cnt = (u8)rule_cnt;
 804 }
 805
 806 /* hw_config() callbacks */
 807 static void bnx2x_set_one_mac_e2(struct bnx2x *bp,
 808                                  struct bnx2x_vlan_mac_obj *o,
 809                                  struct bnx2x_exeq_elem *elem, int rule_idx,
 810                                  int cam_offset)
 811 {
 812         struct bnx2x_raw_obj *raw = &o->raw;
 813         struct eth_classify_rules_ramrod_data *data =
 814                 (struct eth_classify_rules_ramrod_data *)(raw->rdata);
 815         int rule_cnt = rule_idx + 1, cmd = elem->cmd_data.vlan_mac.cmd;
 816         union eth_classify_rule_cmd *rule_entry = &data->rules[rule_idx];
 817         bool add = (cmd == BNX2X_VLAN_MAC_ADD) ? true : false;
 818         unsigned long *vlan_mac_flags = &elem->cmd_data.vlan_mac.vlan_mac_flags;
 819         u8 *mac = elem->cmd_data.vlan_mac.u.mac.mac;
 820
 821         /* Set LLH CAM entry: currently only iSCSI and ETH macs are
 822          * relevant. In addition, current implementation is tuned for a
 823          * single ETH MAC.
 824          *
 825          * When multiple unicast ETH MACs PF configuration in switch
 826          * independent mode is required (NetQ, multiple netdev MACs,
 827          * etc.), consider better utilisation of 8 per function MAC
 828          * entries in the LLH register. There is also
 829          * NIG_REG_P[01]_LLH_FUNC_MEM2 registers that complete the
 830          * total number of CAM entries to 16.
 831          *
 832          * Currently we won't configure NIG for MACs other than a primary ETH
 833          * MAC and iSCSI L2 MAC.
 834          *
 835          * If this MAC is moving from one Queue to another, no need to change
 836          * NIG configuration.
 837          */
 838         if (cmd != BNX2X_VLAN_MAC_MOVE) {
 839                 if (test_bit(BNX2X_ISCSI_ETH_MAC, vlan_mac_flags))
 840                         bnx2x_set_mac_in_nig(bp, add, mac,
 841                                              BNX2X_LLH_CAM_ISCSI_ETH_LINE);
 842                 else if (test_bit(BNX2X_ETH_MAC, vlan_mac_flags))
 843                         bnx2x_set_mac_in_nig(bp, add, mac,
 844                                              BNX2X_LLH_CAM_ETH_LINE);
 845         }
 846
 847         /* Reset the ramrod data buffer for the first rule */
 848         if (rule_idx == 0)
 849                 memset(data, 0, sizeof(*data));
 850
 851         /* Setup a command header */
 852         bnx2x_vlan_mac_set_cmd_hdr_e2(bp, o, add, CLASSIFY_RULE_OPCODE_MAC,
 853                                       &rule_entry->mac.header);
 854
 855         DP(BNX2X_MSG_SP, "About to %s MAC %pM for Queue %d\n",
 856            (add ? "add" : "delete"), mac, raw->cl_id);
 857
 858         /* Set a MAC itself */
 859         bnx2x_set_fw_mac_addr(&rule_entry->mac.mac_msb,
 860                               &rule_entry->mac.mac_mid,
 861                               &rule_entry->mac.mac_lsb, mac);
 862         rule_entry->mac.inner_mac =
 863                 cpu_to_le16(elem->cmd_data.vlan_mac.u.mac.is_inner_mac);
 864
 865         /* MOVE: Add a rule that will add this MAC to the target Queue */
 866         if (cmd == BNX2X_VLAN_MAC_MOVE) {
 867                 rule_entry++;
 868                 rule_cnt++;
 869
 870                 /* Setup ramrod data */
 871                 bnx2x_vlan_mac_set_cmd_hdr_e2(bp,
 872                                         elem->cmd_data.vlan_mac.target_obj,
 873                                               true, CLASSIFY_RULE_OPCODE_MAC,
 874                                               &rule_entry->mac.header);
 875
 876                 /* Set a MAC itself */
 877                 bnx2x_set_fw_mac_addr(&rule_entry->mac.mac_msb,
 878                                       &rule_entry->mac.mac_mid,
 879                                       &rule_entry->mac.mac_lsb, mac);
 880                 rule_entry->mac.inner_mac =
 881                         cpu_to_le16(elem->cmd_data.vlan_mac.
 882                                                 u.mac.is_inner_mac);
 883         }
 884
 885         /* Set the ramrod data header */
 886         /* TODO: take this to the higher level in order to prevent multiple
 887                  writing */
 888         bnx2x_vlan_mac_set_rdata_hdr_e2(raw->cid, raw->state, &data->header,
 889                                         rule_cnt);
 890 }
 891
 892 /**
 893  * bnx2x_vlan_mac_set_rdata_hdr_e1x - set a header in a single classify ramrod
 894  *
 895  * @bp:         device handle
 896  * @o:          queue
 897  * @type:
 898  * @cam_offset: offset in cam memory
 899  * @hdr:        pointer to a header to setup
 900  *
 901  * E1/E1H
 902  */
 903 static inline void bnx2x_vlan_mac_set_rdata_hdr_e1x(struct bnx2x *bp,
 904         struct bnx2x_vlan_mac_obj *o, int type, int cam_offset,
 905         struct mac_configuration_hdr *hdr)
 906 {
 907         struct bnx2x_raw_obj *r = &o->raw;
 908
 909         hdr->length = 1;
 910         hdr->offset = (u8)cam_offset;
 911         hdr->client_id = cpu_to_le16(0xff);
 912         hdr->echo = cpu_to_le32((r->cid & BNX2X_SWCID_MASK) |
 913                                 (type << BNX2X_SWCID_SHIFT));
 914 }
 915
 916 static inline void bnx2x_vlan_mac_set_cfg_entry_e1x(struct bnx2x *bp,
 917         struct bnx2x_vlan_mac_obj *o, bool add, int opcode, u8 *mac,
 918         u16 vlan_id, struct mac_configuration_entry *cfg_entry)
 919 {
 920         struct bnx2x_raw_obj *r = &o->raw;
 921         u32 cl_bit_vec = (1 << r->cl_id);
 922
 923         cfg_entry->clients_bit_vector = cpu_to_le32(cl_bit_vec);
 924         cfg_entry->pf_id = r->func_id;
 925         cfg_entry->vlan_id = cpu_to_le16(vlan_id);
 926
 927         if (add) {
 928                 SET_FLAG(cfg_entry->flags, MAC_CONFIGURATION_ENTRY_ACTION_TYPE,
 929                          T_ETH_MAC_COMMAND_SET);
 930                 SET_FLAG(cfg_entry->flags,
 931                          MAC_CONFIGURATION_ENTRY_VLAN_FILTERING_MODE, opcode);
 932
 933                 /* Set a MAC in a ramrod data */
 934                 bnx2x_set_fw_mac_addr(&cfg_entry->msb_mac_addr,
 935                                       &cfg_entry->middle_mac_addr,
 936                                       &cfg_entry->lsb_mac_addr, mac);
 937         } else
 938                 SET_FLAG(cfg_entry->flags, MAC_CONFIGURATION_ENTRY_ACTION_TYPE,
 939                          T_ETH_MAC_COMMAND_INVALIDATE);
 940 }
 941
 942 static inline void bnx2x_vlan_mac_set_rdata_e1x(struct bnx2x *bp,
 943         struct bnx2x_vlan_mac_obj *o, int type, int cam_offset, bool add,
 944         u8 *mac, u16 vlan_id, int opcode, struct mac_configuration_cmd *config)
 945 {
 946         struct mac_configuration_entry *cfg_entry = &config->config_table[0];
 947         struct bnx2x_raw_obj *raw = &o->raw;
 948
 949         bnx2x_vlan_mac_set_rdata_hdr_e1x(bp, o, type, cam_offset,
 950                                          &config->hdr);
 951         bnx2x_vlan_mac_set_cfg_entry_e1x(bp, o, add, opcode, mac, vlan_id,
 952                                          cfg_entry);
 953
 954         DP(BNX2X_MSG_SP, "%s MAC %pM CLID %d CAM offset %d\n",
 955                          (add ? "setting" : "clearing"),
 956                          mac, raw->cl_id, cam_offset);
 957 }
 958
 959 /**
 960  * bnx2x_set_one_mac_e1x - fill a single MAC rule ramrod data
 961  *
 962  * @bp:         device handle
 963  * @o:          bnx2x_vlan_mac_obj
 964  * @elem:       bnx2x_exeq_elem
 965  * @rule_idx:   rule_idx
 966  * @cam_offset: cam_offset
 967  */
 968 static void bnx2x_set_one_mac_e1x(struct bnx2x *bp,
 969                                   struct bnx2x_vlan_mac_obj *o,
 970                                   struct bnx2x_exeq_elem *elem, int rule_idx,
 971                                   int cam_offset)
 972 {
 973         struct bnx2x_raw_obj *raw = &o->raw;
 974         struct mac_configuration_cmd *config =
 975                 (struct mac_configuration_cmd *)(raw->rdata);
 976         /* 57710 and 57711 do not support MOVE command,
 977          * so it's either ADD or DEL
 978          */
 979         bool add = (elem->cmd_data.vlan_mac.cmd == BNX2X_VLAN_MAC_ADD) ?
 980                 true : false;
 981
 982         /* Reset the ramrod data buffer */
 983         memset(config, 0, sizeof(*config));
 984
 985         bnx2x_vlan_mac_set_rdata_e1x(bp, o, raw->state,
 986                                      cam_offset, add,
 987                                      elem->cmd_data.vlan_mac.u.mac.mac, 0,
 988                                      ETH_VLAN_FILTER_ANY_VLAN, config);
 989 }
 990
 991 static void bnx2x_set_one_vlan_e2(struct bnx2x *bp,
 992                                   struct bnx2x_vlan_mac_obj *o,
 993                                   struct bnx2x_exeq_elem *elem, int rule_idx,
 994                                   int cam_offset)
 995 {
 996         struct bnx2x_raw_obj *raw = &o->raw;
 997         struct eth_classify_rules_ramrod_data *data =
 998                 (struct eth_classify_rules_ramrod_data *)(raw->rdata);
 999         int rule_cnt = rule_idx + 1;
1000         union eth_classify_rule_cmd *rule_entry = &data->rules[rule_idx];
1001         enum bnx2x_vlan_mac_cmd cmd = elem->cmd_data.vlan_mac.cmd;
1002         bool add = (cmd == BNX2X_VLAN_MAC_ADD) ? true : false;
1003         u16 vlan = elem->cmd_data.vlan_mac.u.vlan.vlan;
1004
1005         /* Reset the ramrod data buffer for the first rule */
1006         if (rule_idx == 0)
1007                 memset(data, 0, sizeof(*data));
1008
1009         /* Set a rule header */
1010         bnx2x_vlan_mac_set_cmd_hdr_e2(bp, o, add, CLASSIFY_RULE_OPCODE_VLAN,
1011                                       &rule_entry->vlan.header);
1012
1013         DP(BNX2X_MSG_SP, "About to %s VLAN %d\n", (add ? "add" : "delete"),
1014                          vlan);
1015
1016         /* Set a VLAN itself */
1017         rule_entry->vlan.vlan = cpu_to_le16(vlan);
1018
1019         /* MOVE: Add a rule that will add this MAC to the target Queue */
1020         if (cmd == BNX2X_VLAN_MAC_MOVE) {
1021                 rule_entry++;
1022                 rule_cnt++;
1023
1024                 /* Setup ramrod data */
1025                 bnx2x_vlan_mac_set_cmd_hdr_e2(bp,
1026                                         elem->cmd_data.vlan_mac.target_obj,
1027                                               true, CLASSIFY_RULE_OPCODE_VLAN,
1028                                               &rule_entry->vlan.header);
1029
1030                 /* Set a VLAN itself */
1031                 rule_entry->vlan.vlan = cpu_to_le16(vlan);
1032         }
1033
1034         /* Set the ramrod data header */
1035         /* TODO: take this to the higher level in order to prevent multiple
1036                  writing */
1037         bnx2x_vlan_mac_set_rdata_hdr_e2(raw->cid, raw->state, &data->header,
1038                                         rule_cnt);
1039 }
1040
1041 /**
1042  * bnx2x_vlan_mac_restore - reconfigure next MAC/VLAN/VLAN-MAC element
1043  *
1044  * @bp:         device handle
1045  * @p:          command parameters
1046  * @ppos:       pointer to the cookie
1047  *
1048  * reconfigure next MAC/VLAN/VLAN-MAC element from the
1049  * previously configured elements list.
1050  *
1051  * from command parameters only RAMROD_COMP_WAIT bit in ramrod_flags is taken
1052  * into an account
1053  *
1054  * pointer to the cookie  - that should be given back in the next call to make
1055  * function handle the next element. If *ppos is set to NULL it will restart the
1056  * iterator. If returned *ppos == NULL this means that the last element has been
1057  * handled.
1058  *
1059  */
1060 static int bnx2x_vlan_mac_restore(struct bnx2x *bp,
1061                            struct bnx2x_vlan_mac_ramrod_params *p,
1062                            struct bnx2x_vlan_mac_registry_elem **ppos)
1063 {
1064         struct bnx2x_vlan_mac_registry_elem *pos;
1065         struct bnx2x_vlan_mac_obj *o = p->vlan_mac_obj;
1066
1067         /* If list is empty - there is nothing to do here */
1068         if (list_empty(&o->head)) {
1069                 *ppos = NULL;
1070                 return 0;
1071         }
1072
1073         /* make a step... */
1074         if (*ppos == NULL)
1075                 *ppos = list_first_entry(&o->head,
1076                                          struct bnx2x_vlan_mac_registry_elem,
1077                                          link);
1078         else
1079                 *ppos = list_next_entry(*ppos, link);
1080
1081         pos = *ppos;
1082
1083         /* If it's the last step - return NULL */
1084         if (list_is_last(&pos->link, &o->head))
1085                 *ppos = NULL;
1086
1087         /* Prepare a 'user_req' */
1088         memcpy(&p->user_req.u, &pos->u, sizeof(pos->u));
1089
1090         /* Set the command */
1091         p->user_req.cmd = BNX2X_VLAN_MAC_ADD;
1092
1093         /* Set vlan_mac_flags */
1094         p->user_req.vlan_mac_flags = pos->vlan_mac_flags;
1095
1096         /* Set a restore bit */
1097         __set_bit(RAMROD_RESTORE, &p->ramrod_flags);
1098
1099         return bnx2x_config_vlan_mac(bp, p);
1100 }
1101
1102 /* bnx2x_exeq_get_mac/bnx2x_exeq_get_vlan/bnx2x_exeq_get_vlan_mac return a
1103  * pointer to an element with a specific criteria and NULL if such an element
1104  * hasn't been found.
1105  */
1106 static struct bnx2x_exeq_elem *bnx2x_exeq_get_mac(
1107         struct bnx2x_exe_queue_obj *o,
1108         struct bnx2x_exeq_elem *elem)
1109 {
1110         struct bnx2x_exeq_elem *pos;
1111         struct bnx2x_mac_ramrod_data *data = &elem->cmd_data.vlan_mac.u.mac;
1112
1113         /* Check pending for execution commands */
1114         list_for_each_entry(pos, &o->exe_queue, link)
1115                 if (!memcmp(&pos->cmd_data.vlan_mac.u.mac, data,
1116                               sizeof(*data)) &&
1117                     (pos->cmd_data.vlan_mac.cmd == elem->cmd_data.vlan_mac.cmd))
1118                         return pos;
1119
1120         return NULL;
1121 }
1122
1123 static struct bnx2x_exeq_elem *bnx2x_exeq_get_vlan(
1124         struct bnx2x_exe_queue_obj *o,
1125         struct bnx2x_exeq_elem *elem)
1126 {
1127         struct bnx2x_exeq_elem *pos;
1128         struct bnx2x_vlan_ramrod_data *data = &elem->cmd_data.vlan_mac.u.vlan;
1129
1130         /* Check pending for execution commands */
1131         list_for_each_entry(pos, &o->exe_queue, link)
1132                 if (!memcmp(&pos->cmd_data.vlan_mac.u.vlan, data,
1133                               sizeof(*data)) &&
1134                     (pos->cmd_data.vlan_mac.cmd == elem->cmd_data.vlan_mac.cmd))
1135                         return pos;
1136
1137         return NULL;
1138 }
1139
1140 /**
1141  * bnx2x_validate_vlan_mac_add - check if an ADD command can be executed
1142  *
1143  * @bp:         device handle
1144  * @qo:         bnx2x_qable_obj
1145  * @elem:       bnx2x_exeq_elem
1146  *
1147  * Checks that the requested configuration can be added. If yes and if
1148  * requested, consume CAM credit.
1149  *
1150  * The 'validate' is run after the 'optimize'.
1151  *
1152  */
1153 static inline int bnx2x_validate_vlan_mac_add(struct bnx2x *bp,
1154                                               union bnx2x_qable_obj *qo,
1155                                               struct bnx2x_exeq_elem *elem)
1156 {
1157         struct bnx2x_vlan_mac_obj *o = &qo->vlan_mac;
1158         struct bnx2x_exe_queue_obj *exeq = &o->exe_queue;
1159         int rc;
1160
1161         /* Check the registry */
1162         rc = o->check_add(bp, o, &elem->cmd_data.vlan_mac.u);
1163         if (rc) {
1164                 DP(BNX2X_MSG_SP, "ADD command is not allowed considering current registry state.\n");
1165                 return rc;
1166         }
1167
1168         /* Check if there is a pending ADD command for this
1169          * MAC/VLAN/VLAN-MAC. Return an error if there is.
1170          */
1171         if (exeq->get(exeq, elem)) {
1172                 DP(BNX2X_MSG_SP, "There is a pending ADD command already\n");
1173                 return -EEXIST;
1174         }
1175
1176         /* TODO: Check the pending MOVE from other objects where this
1177          * object is a destination object.
1178          */
1179
1180         /* Consume the credit if not requested not to */
1181         if (!(test_bit(BNX2X_DONT_CONSUME_CAM_CREDIT,
1182                        &elem->cmd_data.vlan_mac.vlan_mac_flags) ||
1183             o->get_credit(o)))
1184                 return -EINVAL;
1185
1186         return 0;
1187 }
1188
1189 /**
1190  * bnx2x_validate_vlan_mac_del - check if the DEL command can be executed
1191  *
1192  * @bp:         device handle
1193  * @qo:         quable object to check
1194  * @elem:       element that needs to be deleted
1195  *
1196  * Checks that the requested configuration can be deleted. If yes and if
1197  * requested, returns a CAM credit.
1198  *
1199  * The 'validate' is run after the 'optimize'.
1200  */
1201 static inline int bnx2x_validate_vlan_mac_del(struct bnx2x *bp,
1202                                               union bnx2x_qable_obj *qo,
1203                                               struct bnx2x_exeq_elem *elem)
1204 {
1205         struct bnx2x_vlan_mac_obj *o = &qo->vlan_mac;
1206         struct bnx2x_vlan_mac_registry_elem *pos;
1207         struct bnx2x_exe_queue_obj *exeq = &o->exe_queue;
1208         struct bnx2x_exeq_elem query_elem;
1209
1210         /* If this classification can not be deleted (doesn't exist)
1211          * - return a BNX2X_EXIST.
1212          */
1213         pos = o->check_del(bp, o, &elem->cmd_data.vlan_mac.u);
1214         if (!pos) {
1215                 DP(BNX2X_MSG_SP, "DEL command is not allowed considering current registry state\n");
1216                 return -EEXIST;
1217         }
1218
1219         /* Check if there are pending DEL or MOVE commands for this
1220          * MAC/VLAN/VLAN-MAC. Return an error if so.
1221          */
1222         memcpy(&query_elem, elem, sizeof(query_elem));
1223
1224         /* Check for MOVE commands */
1225         query_elem.cmd_data.vlan_mac.cmd = BNX2X_VLAN_MAC_MOVE;
1226         if (exeq->get(exeq, &query_elem)) {
1227                 BNX2X_ERR("There is a pending MOVE command already\n");
1228                 return -EINVAL;
1229         }
1230
1231         /* Check for DEL commands */
1232         if (exeq->get(exeq, elem)) {
1233                 DP(BNX2X_MSG_SP, "There is a pending DEL command already\n");
1234                 return -EEXIST;
1235         }
1236
1237         /* Return the credit to the credit pool if not requested not to */
1238         if (!(test_bit(BNX2X_DONT_CONSUME_CAM_CREDIT,
1239                        &elem->cmd_data.vlan_mac.vlan_mac_flags) ||
1240             o->put_credit(o))) {
1241                 BNX2X_ERR("Failed to return a credit\n");
1242                 return -EINVAL;
1243         }
1244
1245         return 0;
1246 }
1247
1248 /**
1249  * bnx2x_validate_vlan_mac_move - check if the MOVE command can be executed
1250  *
1251  * @bp:         device handle
1252  * @qo:         quable object to check (source)
1253  * @elem:       element that needs to be moved
1254  *
1255  * Checks that the requested configuration can be moved. If yes and if
1256  * requested, returns a CAM credit.
1257  *
1258  * The 'validate' is run after the 'optimize'.
1259  */
1260 static inline int bnx2x_validate_vlan_mac_move(struct bnx2x *bp,
1261                                                union bnx2x_qable_obj *qo,
1262                                                struct bnx2x_exeq_elem *elem)
1263 {
1264         struct bnx2x_vlan_mac_obj *src_o = &qo->vlan_mac;
1265         struct bnx2x_vlan_mac_obj *dest_o = elem->cmd_data.vlan_mac.target_obj;
1266         struct bnx2x_exeq_elem query_elem;
1267         struct bnx2x_exe_queue_obj *src_exeq = &src_o->exe_queue;
1268         struct bnx2x_exe_queue_obj *dest_exeq = &dest_o->exe_queue;
1269
1270         /* Check if we can perform this operation based on the current registry
1271          * state.
1272          */
1273         if (!src_o->check_move(bp, src_o, dest_o,
1274                                &elem->cmd_data.vlan_mac.u)) {
1275                 DP(BNX2X_MSG_SP, "MOVE command is not allowed considering current registry state\n");
1276                 return -EINVAL;
1277         }
1278
1279         /* Check if there is an already pending DEL or MOVE command for the
1280          * source object or ADD command for a destination object. Return an
1281          * error if so.
1282          */
1283         memcpy(&query_elem, elem, sizeof(query_elem));
1284
1285         /* Check DEL on source */
1286         query_elem.cmd_data.vlan_mac.cmd = BNX2X_VLAN_MAC_DEL;
1287         if (src_exeq->get(src_exeq, &query_elem)) {
1288                 BNX2X_ERR("There is a pending DEL command on the source queue already\n");
1289                 return -EINVAL;
1290         }
1291
1292         /* Check MOVE on source */
1293         if (src_exeq->get(src_exeq, elem)) {
1294                 DP(BNX2X_MSG_SP, "There is a pending MOVE command already\n");
1295                 return -EEXIST;
1296         }
1297
1298         /* Check ADD on destination */
1299         query_elem.cmd_data.vlan_mac.cmd = BNX2X_VLAN_MAC_ADD;
1300         if (dest_exeq->get(dest_exeq, &query_elem)) {
1301                 BNX2X_ERR("There is a pending ADD command on the destination queue already\n");
1302                 return -EINVAL;
1303         }
1304
1305         /* Consume the credit if not requested not to */
1306         if (!(test_bit(BNX2X_DONT_CONSUME_CAM_CREDIT_DEST,
1307                        &elem->cmd_data.vlan_mac.vlan_mac_flags) ||
1308             dest_o->get_credit(dest_o)))
1309                 return -EINVAL;
1310
1311         if (!(test_bit(BNX2X_DONT_CONSUME_CAM_CREDIT,
1312                        &elem->cmd_data.vlan_mac.vlan_mac_flags) ||
1313             src_o->put_credit(src_o))) {
1314                 /* return the credit taken from dest... */
1315                 dest_o->put_credit(dest_o);
1316                 return -EINVAL;
1317         }
1318
1319         return 0;
1320 }
1321
1322 static int bnx2x_validate_vlan_mac(struct bnx2x *bp,
1323                                    union bnx2x_qable_obj *qo,
1324                                    struct bnx2x_exeq_elem *elem)
1325 {
1326         switch (elem->cmd_data.vlan_mac.cmd) {
1327         case BNX2X_VLAN_MAC_ADD:
1328                 return bnx2x_validate_vlan_mac_add(bp, qo, elem);
1329         case BNX2X_VLAN_MAC_DEL:
1330                 return bnx2x_validate_vlan_mac_del(bp, qo, elem);
1331         case BNX2X_VLAN_MAC_MOVE:
1332                 return bnx2x_validate_vlan_mac_move(bp, qo, elem);
1333         default:
1334                 return -EINVAL;
1335         }
1336 }
1337
1338 static int bnx2x_remove_vlan_mac(struct bnx2x *bp,
1339                                   union bnx2x_qable_obj *qo,
1340                                   struct bnx2x_exeq_elem *elem)
1341 {
1342         int rc = 0;
1343
1344         /* If consumption wasn't required, nothing to do */
1345         if (test_bit(BNX2X_DONT_CONSUME_CAM_CREDIT,
1346                      &elem->cmd_data.vlan_mac.vlan_mac_flags))
1347                 return 0;
1348
1349         switch (elem->cmd_data.vlan_mac.cmd) {
1350         case BNX2X_VLAN_MAC_ADD:
1351         case BNX2X_VLAN_MAC_MOVE:
1352                 rc = qo->vlan_mac.put_credit(&qo->vlan_mac);
1353                 break;
1354         case BNX2X_VLAN_MAC_DEL:
1355                 rc = qo->vlan_mac.get_credit(&qo->vlan_mac);
1356                 break;
1357         default:
1358                 return -EINVAL;
1359         }
1360
1361         if (rc != true)
1362                 return -EINVAL;
1363
1364         return 0;
1365 }
1366
1367 /**
1368  * bnx2x_wait_vlan_mac - passively wait for 5 seconds until all work completes.
1369  *
1370  * @bp:         device handle
1371  * @o:          bnx2x_vlan_mac_obj
1372  *
1373  */
1374 static int bnx2x_wait_vlan_mac(struct bnx2x *bp,
1375                                struct bnx2x_vlan_mac_obj *o)
1376 {
1377         int cnt = 5000, rc;
1378         struct bnx2x_exe_queue_obj *exeq = &o->exe_queue;
1379         struct bnx2x_raw_obj *raw = &o->raw;
1380
1381         while (cnt--) {
1382                 /* Wait for the current command to complete */
1383                 rc = raw->wait_comp(bp, raw);
1384                 if (rc)
1385                         return rc;
1386
1387                 /* Wait until there are no pending commands */
1388                 if (!bnx2x_exe_queue_empty(exeq))
1389                         usleep_range(1000, 2000);
1390                 else
1391                         return 0;
1392         }
1393
1394         return -EBUSY;
1395 }
1396
1397 static int __bnx2x_vlan_mac_execute_step(struct bnx2x *bp,
1398                                          struct bnx2x_vlan_mac_obj *o,
1399                                          unsigned long *ramrod_flags)
1400 {
1401         int rc = 0;
1402
1403         spin_lock_bh(&o->exe_queue.lock);
1404
1405         DP(BNX2X_MSG_SP, "vlan_mac_execute_step - trying to take writer lock\n");
1406         rc = __bnx2x_vlan_mac_h_write_trylock(bp, o);
1407
1408         if (rc != 0) {
1409                 __bnx2x_vlan_mac_h_pend(bp, o, *ramrod_flags);
1410
1411                 /* Calling function should not diffrentiate between this case
1412                  * and the case in which there is already a pending ramrod
1413                  */
1414                 rc = 1;
1415         } else {
1416                 rc = bnx2x_exe_queue_step(bp, &o->exe_queue, ramrod_flags);
1417         }
1418         spin_unlock_bh(&o->exe_queue.lock);
1419
1420         return rc;
1421 }
1422
1423 /**
1424  * bnx2x_complete_vlan_mac - complete one VLAN-MAC ramrod
1425  *
1426  * @bp:         device handle
1427  * @o:          bnx2x_vlan_mac_obj
1428  * @cqe:
1429  * @cont:       if true schedule next execution chunk
1430  *
1431  */
1432 static int bnx2x_complete_vlan_mac(struct bnx2x *bp,
1433                                    struct bnx2x_vlan_mac_obj *o,
1434                                    union event_ring_elem *cqe,
1435                                    unsigned long *ramrod_flags)
1436 {
1437         struct bnx2x_raw_obj *r = &o->raw;
1438         int rc;
1439
1440         /* Clearing the pending list & raw state should be made
1441          * atomically (as execution flow assumes they represent the same).
1442          */
1443         spin_lock_bh(&o->exe_queue.lock);
1444
1445         /* Reset pending list */
1446         __bnx2x_exe_queue_reset_pending(bp, &o->exe_queue);
1447
1448         /* Clear pending */
1449         r->clear_pending(r);
1450
1451         spin_unlock_bh(&o->exe_queue.lock);
1452
1453         /* If ramrod failed this is most likely a SW bug */
1454         if (cqe->message.error)
1455                 return -EINVAL;
1456
1457         /* Run the next bulk of pending commands if requested */
1458         if (test_bit(RAMROD_CONT, ramrod_flags)) {
1459                 rc = __bnx2x_vlan_mac_execute_step(bp, o, ramrod_flags);
1460
1461                 if (rc < 0)
1462                         return rc;
1463         }
1464
1465         /* If there is more work to do return PENDING */
1466         if (!bnx2x_exe_queue_empty(&o->exe_queue))
1467                 return 1;
1468
1469         return 0;
1470 }
1471
1472 /**
1473  * bnx2x_optimize_vlan_mac - optimize ADD and DEL commands.
1474  *
1475  * @bp:         device handle
1476  * @o:          bnx2x_qable_obj
1477  * @elem:       bnx2x_exeq_elem
1478  */
1479 static int bnx2x_optimize_vlan_mac(struct bnx2x *bp,
1480                                    union bnx2x_qable_obj *qo,
1481                                    struct bnx2x_exeq_elem *elem)
1482 {
1483         struct bnx2x_exeq_elem query, *pos;
1484         struct bnx2x_vlan_mac_obj *o = &qo->vlan_mac;
1485         struct bnx2x_exe_queue_obj *exeq = &o->exe_queue;
1486
1487         memcpy(&query, elem, sizeof(query));
1488
1489         switch (elem->cmd_data.vlan_mac.cmd) {
1490         case BNX2X_VLAN_MAC_ADD:
1491                 query.cmd_data.vlan_mac.cmd = BNX2X_VLAN_MAC_DEL;
1492                 break;
1493         case BNX2X_VLAN_MAC_DEL:
1494                 query.cmd_data.vlan_mac.cmd = BNX2X_VLAN_MAC_ADD;
1495                 break;
1496         default:
1497                 /* Don't handle anything other than ADD or DEL */
1498                 return 0;
1499         }
1500
1501         /* If we found the appropriate element - delete it */
1502         pos = exeq->get(exeq, &query);
1503         if (pos) {
1504
1505                 /* Return the credit of the optimized command */
1506                 if (!test_bit(BNX2X_DONT_CONSUME_CAM_CREDIT,
1507                               &pos->cmd_data.vlan_mac.vlan_mac_flags)) {
1508                         if ((query.cmd_data.vlan_mac.cmd ==
1509                              BNX2X_VLAN_MAC_ADD) && !o->put_credit(o)) {
1510                                 BNX2X_ERR("Failed to return the credit for the optimized ADD command\n");
1511                                 return -EINVAL;
1512                         } else if (!o->get_credit(o)) { /* VLAN_MAC_DEL */
1513                                 BNX2X_ERR("Failed to recover the credit from the optimized DEL command\n");
1514                                 return -EINVAL;
1515                         }
1516                 }
1517
1518                 DP(BNX2X_MSG_SP, "Optimizing %s command\n",
1519                            (elem->cmd_data.vlan_mac.cmd == BNX2X_VLAN_MAC_ADD) ?
1520                            "ADD" : "DEL");
1521
1522                 list_del(&pos->link);
1523                 bnx2x_exe_queue_free_elem(bp, pos);
1524                 return 1;
1525         }
1526
1527         return 0;
1528 }
1529
1530 /**
1531  * bnx2x_vlan_mac_get_registry_elem - prepare a registry element
1532  *
1533  * @bp:   device handle
1534  * @o:
1535  * @elem:
1536  * @restore:
1537  * @re:
1538  *
1539  * prepare a registry element according to the current command request.
1540  */
1541 static inline int bnx2x_vlan_mac_get_registry_elem(
1542         struct bnx2x *bp,
1543         struct bnx2x_vlan_mac_obj *o,
1544         struct bnx2x_exeq_elem *elem,
1545         bool restore,
1546         struct bnx2x_vlan_mac_registry_elem **re)
1547 {
1548         enum bnx2x_vlan_mac_cmd cmd = elem->cmd_data.vlan_mac.cmd;
1549         struct bnx2x_vlan_mac_registry_elem *reg_elem;
1550
1551         /* Allocate a new registry element if needed. */
1552         if (!restore &&
1553             ((cmd == BNX2X_VLAN_MAC_ADD) || (cmd == BNX2X_VLAN_MAC_MOVE))) {
1554                 reg_elem = kzalloc(sizeof(*reg_elem), GFP_ATOMIC);
1555                 if (!reg_elem)
1556                         return -ENOMEM;
1557
1558                 /* Get a new CAM offset */
1559                 if (!o->get_cam_offset(o, &reg_elem->cam_offset)) {
1560                         /* This shall never happen, because we have checked the
1561                          * CAM availability in the 'validate'.
1562                          */
1563                         WARN_ON(1);
1564                         kfree(reg_elem);
1565                         return -EINVAL;
1566                 }
1567
1568                 DP(BNX2X_MSG_SP, "Got cam offset %d\n", reg_elem->cam_offset);
1569
1570                 /* Set a VLAN-MAC data */
1571                 memcpy(&reg_elem->u, &elem->cmd_data.vlan_mac.u,
1572                           sizeof(reg_elem->u));
1573
1574                 /* Copy the flags (needed for DEL and RESTORE flows) */
1575                 reg_elem->vlan_mac_flags =
1576                         elem->cmd_data.vlan_mac.vlan_mac_flags;
1577         } else /* DEL, RESTORE */
1578                 reg_elem = o->check_del(bp, o, &elem->cmd_data.vlan_mac.u);
1579
1580         *re = reg_elem;
1581         return 0;
1582 }
1583
1584 /**
1585  * bnx2x_execute_vlan_mac - execute vlan mac command
1586  *
1587  * @bp:                 device handle
1588  * @qo:
1589  * @exe_chunk:
1590  * @ramrod_flags:
1591  *
1592  * go and send a ramrod!
1593  */
1594 static int bnx2x_execute_vlan_mac(struct bnx2x *bp,
1595                                   union bnx2x_qable_obj *qo,
1596                                   struct list_head *exe_chunk,
1597                                   unsigned long *ramrod_flags)
1598 {
1599         struct bnx2x_exeq_elem *elem;
1600         struct bnx2x_vlan_mac_obj *o = &qo->vlan_mac, *cam_obj;
1601         struct bnx2x_raw_obj *r = &o->raw;
1602         int rc, idx = 0;
1603         bool restore = test_bit(RAMROD_RESTORE, ramrod_flags);
1604         bool drv_only = test_bit(RAMROD_DRV_CLR_ONLY, ramrod_flags);
1605         struct bnx2x_vlan_mac_registry_elem *reg_elem;
1606         enum bnx2x_vlan_mac_cmd cmd;
1607
1608         /* If DRIVER_ONLY execution is requested, cleanup a registry
1609          * and exit. Otherwise send a ramrod to FW.
1610          */
1611         if (!drv_only) {
1612                 WARN_ON(r->check_pending(r));
1613
1614                 /* Set pending */
1615                 r->set_pending(r);
1616
1617                 /* Fill the ramrod data */
1618                 list_for_each_entry(elem, exe_chunk, link) {
1619                         cmd = elem->cmd_data.vlan_mac.cmd;
1620                         /* We will add to the target object in MOVE command, so
1621                          * change the object for a CAM search.
1622                          */
1623                         if (cmd == BNX2X_VLAN_MAC_MOVE)
1624                                 cam_obj = elem->cmd_data.vlan_mac.target_obj;
1625                         else
1626                                 cam_obj = o;
1627
1628                         rc = bnx2x_vlan_mac_get_registry_elem(bp, cam_obj,
1629                                                               elem, restore,
1630                                                               &reg_elem);
1631                         if (rc)
1632                                 goto error_exit;
1633
1634                         WARN_ON(!reg_elem);
1635
1636                         /* Push a new entry into the registry */
1637                         if (!restore &&
1638                             ((cmd == BNX2X_VLAN_MAC_ADD) ||
1639                             (cmd == BNX2X_VLAN_MAC_MOVE)))
1640                                 list_add(&reg_elem->link, &cam_obj->head);
1641
1642                         /* Configure a single command in a ramrod data buffer */
1643                         o->set_one_rule(bp, o, elem, idx,
1644                                         reg_elem->cam_offset);
1645
1646                         /* MOVE command consumes 2 entries in the ramrod data */
1647                         if (cmd == BNX2X_VLAN_MAC_MOVE)
1648                                 idx += 2;
1649                         else
1650                                 idx++;
1651                 }
1652
1653                 /* No need for an explicit memory barrier here as long we would
1654                  * need to ensure the ordering of writing to the SPQ element
1655                  * and updating of the SPQ producer which involves a memory
1656                  * read and we will have to put a full memory barrier there
1657                  * (inside bnx2x_sp_post()).
1658                  */
1659
1660                 rc = bnx2x_sp_post(bp, o->ramrod_cmd, r->cid,
1661                                    U64_HI(r->rdata_mapping),
1662                                    U64_LO(r->rdata_mapping),
1663                                    ETH_CONNECTION_TYPE);
1664                 if (rc)
1665                         goto error_exit;
1666         }
1667
1668         /* Now, when we are done with the ramrod - clean up the registry */
1669         list_for_each_entry(elem, exe_chunk, link) {
1670                 cmd = elem->cmd_data.vlan_mac.cmd;
1671                 if ((cmd == BNX2X_VLAN_MAC_DEL) ||
1672                     (cmd == BNX2X_VLAN_MAC_MOVE)) {
1673                         reg_elem = o->check_del(bp, o,
1674                                                 &elem->cmd_data.vlan_mac.u);
1675
1676                         WARN_ON(!reg_elem);
1677
1678                         o->put_cam_offset(o, reg_elem->cam_offset);
1679                         list_del(&reg_elem->link);
1680                         kfree(reg_elem);
1681                 }
1682         }
1683
1684         if (!drv_only)
1685                 return 1;
1686         else
1687                 return 0;
1688
1689 error_exit:
1690         r->clear_pending(r);
1691
1692         /* Cleanup a registry in case of a failure */
1693         list_for_each_entry(elem, exe_chunk, link) {
1694                 cmd = elem->cmd_data.vlan_mac.cmd;
1695
1696                 if (cmd == BNX2X_VLAN_MAC_MOVE)
1697                         cam_obj = elem->cmd_data.vlan_mac.target_obj;
1698                 else
1699                         cam_obj = o;
1700
1701                 /* Delete all newly added above entries */
1702                 if (!restore &&
1703                     ((cmd == BNX2X_VLAN_MAC_ADD) ||
1704                     (cmd == BNX2X_VLAN_MAC_MOVE))) {
1705                         reg_elem = o->check_del(bp, cam_obj,
1706                                                 &elem->cmd_data.vlan_mac.u);
1707                         if (reg_elem) {
1708                                 list_del(&reg_elem->link);
1709                                 kfree(reg_elem);
1710                         }
1711                 }
1712         }
1713
1714         return rc;
1715 }
1716
1717 static inline int bnx2x_vlan_mac_push_new_cmd(
1718         struct bnx2x *bp,
1719         struct bnx2x_vlan_mac_ramrod_params *p)
1720 {
1721         struct bnx2x_exeq_elem *elem;
1722         struct bnx2x_vlan_mac_obj *o = p->vlan_mac_obj;
1723         bool restore = test_bit(RAMROD_RESTORE, &p->ramrod_flags);
1724
1725         /* Allocate the execution queue element */
1726         elem = bnx2x_exe_queue_alloc_elem(bp);
1727         if (!elem)
1728                 return -ENOMEM;
1729
1730         /* Set the command 'length' */
1731         switch (p->user_req.cmd) {
1732         case BNX2X_VLAN_MAC_MOVE:
1733                 elem->cmd_len = 2;
1734                 break;
1735         default:
1736                 elem->cmd_len = 1;
1737         }
1738
1739         /* Fill the object specific info */
1740         memcpy(&elem->cmd_data.vlan_mac, &p->user_req, sizeof(p->user_req));
1741
1742         /* Try to add a new command to the pending list */
1743         return bnx2x_exe_queue_add(bp, &o->exe_queue, elem, restore);
1744 }
1745
1746 /**
1747  * bnx2x_config_vlan_mac - configure VLAN/MAC/VLAN_MAC filtering rules.
1748  *
1749  * @bp:   device handle
1750  * @p:
1751  *
1752  */
1753 int bnx2x_config_vlan_mac(struct bnx2x *bp,
1754                            struct bnx2x_vlan_mac_ramrod_params *p)
1755 {
1756         int rc = 0;
1757         struct bnx2x_vlan_mac_obj *o = p->vlan_mac_obj;
1758         unsigned long *ramrod_flags = &p->ramrod_flags;
1759         bool cont = test_bit(RAMROD_CONT, ramrod_flags);
1760         struct bnx2x_raw_obj *raw = &o->raw;
1761
1762         /*
1763          * Add new elements to the execution list for commands that require it.
1764          */
1765         if (!cont) {
1766                 rc = bnx2x_vlan_mac_push_new_cmd(bp, p);
1767                 if (rc)
1768                         return rc;
1769         }
1770
1771         /* If nothing will be executed further in this iteration we want to
1772          * return PENDING if there are pending commands
1773          */
1774         if (!bnx2x_exe_queue_empty(&o->exe_queue))
1775                 rc = 1;
1776
1777         if (test_bit(RAMROD_DRV_CLR_ONLY, ramrod_flags))  {
1778                 DP(BNX2X_MSG_SP, "RAMROD_DRV_CLR_ONLY requested: clearing a pending bit.\n");
1779                 raw->clear_pending(raw);
1780         }
1781
1782         /* Execute commands if required */
1783         if (cont || test_bit(RAMROD_EXEC, ramrod_flags) ||
1784             test_bit(RAMROD_COMP_WAIT, ramrod_flags)) {
1785                 rc = __bnx2x_vlan_mac_execute_step(bp, p->vlan_mac_obj,
1786                                                    &p->ramrod_flags);
1787                 if (rc < 0)
1788                         return rc;
1789         }
1790
1791         /* RAMROD_COMP_WAIT is a superset of RAMROD_EXEC. If it was set
1792          * then user want to wait until the last command is done.
1793          */
1794         if (test_bit(RAMROD_COMP_WAIT, &p->ramrod_flags)) {
1795                 /* Wait maximum for the current exe_queue length iterations plus
1796                  * one (for the current pending command).
1797                  */
1798                 int max_iterations = bnx2x_exe_queue_length(&o->exe_queue) + 1;
1799
1800                 while (!bnx2x_exe_queue_empty(&o->exe_queue) &&
1801                        max_iterations--) {
1802
1803                         /* Wait for the current command to complete */
1804                         rc = raw->wait_comp(bp, raw);
1805                         if (rc)
1806                                 return rc;
1807
1808                         /* Make a next step */
1809                         rc = __bnx2x_vlan_mac_execute_step(bp,
1810                                                            p->vlan_mac_obj,
1811                                                            &p->ramrod_flags);
1812                         if (rc < 0)
1813                                 return rc;
1814                 }
1815
1816                 return 0;
1817         }
1818
1819         return rc;
1820 }
1821
1822 /**
1823  * bnx2x_vlan_mac_del_all - delete elements with given vlan_mac_flags spec
1824  *
1825  * @bp:                 device handle
1826  * @o:
1827  * @vlan_mac_flags:
1828  * @ramrod_flags:       execution flags to be used for this deletion
1829  *
1830  * if the last operation has completed successfully and there are no
1831  * more elements left, positive value if the last operation has completed
1832  * successfully and there are more previously configured elements, negative
1833  * value is current operation has failed.
1834  */
1835 static int bnx2x_vlan_mac_del_all(struct bnx2x *bp,
1836                                   struct bnx2x_vlan_mac_obj *o,
1837                                   unsigned long *vlan_mac_flags,
1838                                   unsigned long *ramrod_flags)
1839 {
1840         struct bnx2x_vlan_mac_registry_elem *pos = NULL;
1841         struct bnx2x_vlan_mac_ramrod_params p;
1842         struct bnx2x_exe_queue_obj *exeq = &o->exe_queue;
1843         struct bnx2x_exeq_elem *exeq_pos, *exeq_pos_n;
1844         unsigned long flags;
1845         int read_lock;
1846         int rc = 0;
1847
1848         /* Clear pending commands first */
1849
1850         spin_lock_bh(&exeq->lock);
1851
1852         list_for_each_entry_safe(exeq_pos, exeq_pos_n, &exeq->exe_queue, link) {
1853                 flags = exeq_pos->cmd_data.vlan_mac.vlan_mac_flags;
1854                 if (BNX2X_VLAN_MAC_CMP_FLAGS(flags) ==
1855                     BNX2X_VLAN_MAC_CMP_FLAGS(*vlan_mac_flags)) {
1856                         rc = exeq->remove(bp, exeq->owner, exeq_pos);
1857                         if (rc) {
1858                                 BNX2X_ERR("Failed to remove command\n");
1859                                 spin_unlock_bh(&exeq->lock);
1860                                 return rc;
1861                         }
1862                         list_del(&exeq_pos->link);
1863                         bnx2x_exe_queue_free_elem(bp, exeq_pos);
1864                 }
1865         }
1866
1867         spin_unlock_bh(&exeq->lock);
1868
1869         /* Prepare a command request */
1870         memset(&p, 0, sizeof(p));
1871         p.vlan_mac_obj = o;
1872         p.ramrod_flags = *ramrod_flags;
1873         p.user_req.cmd = BNX2X_VLAN_MAC_DEL;
1874
1875         /* Add all but the last VLAN-MAC to the execution queue without actually
1876          * execution anything.
1877          */
1878         __clear_bit(RAMROD_COMP_WAIT, &p.ramrod_flags);
1879         __clear_bit(RAMROD_EXEC, &p.ramrod_flags);
1880         __clear_bit(RAMROD_CONT, &p.ramrod_flags);
1881
1882         DP(BNX2X_MSG_SP, "vlan_mac_del_all -- taking vlan_mac_lock (reader)\n");
1883         read_lock = bnx2x_vlan_mac_h_read_lock(bp, o);
1884         if (read_lock != 0)
1885                 return read_lock;
1886
1887         list_for_each_entry(pos, &o->head, link) {
1888                 flags = pos->vlan_mac_flags;
1889                 if (BNX2X_VLAN_MAC_CMP_FLAGS(flags) ==
1890                     BNX2X_VLAN_MAC_CMP_FLAGS(*vlan_mac_flags)) {
1891                         p.user_req.vlan_mac_flags = pos->vlan_mac_flags;
1892                         memcpy(&p.user_req.u, &pos->u, sizeof(pos->u));
1893                         rc = bnx2x_config_vlan_mac(bp, &p);
1894                         if (rc < 0) {
1895                                 BNX2X_ERR("Failed to add a new DEL command\n");
1896                                 bnx2x_vlan_mac_h_read_unlock(bp, o);
1897                                 return rc;
1898                         }
1899                 }
1900         }
1901
1902         DP(BNX2X_MSG_SP, "vlan_mac_del_all -- releasing vlan_mac_lock (reader)\n");
1903         bnx2x_vlan_mac_h_read_unlock(bp, o);
1904
1905         p.ramrod_flags = *ramrod_flags;
1906         __set_bit(RAMROD_CONT, &p.ramrod_flags);
1907
1908         return bnx2x_config_vlan_mac(bp, &p);
1909 }
1910
1911 static inline void bnx2x_init_raw_obj(struct bnx2x_raw_obj *raw, u8 cl_id,
1912         u32 cid, u8 func_id, void *rdata, dma_addr_t rdata_mapping, int state,
1913         unsigned long *pstate, bnx2x_obj_type type)
1914 {
1915         raw->func_id = func_id;
1916         raw->cid = cid;
1917         raw->cl_id = cl_id;
1918         raw->rdata = rdata;
1919         raw->rdata_mapping = rdata_mapping;
1920         raw->state = state;
1921         raw->pstate = pstate;
1922         raw->obj_type = type;
1923         raw->check_pending = bnx2x_raw_check_pending;
1924         raw->clear_pending = bnx2x_raw_clear_pending;
1925         raw->set_pending = bnx2x_raw_set_pending;
1926         raw->wait_comp = bnx2x_raw_wait;
1927 }
1928
1929 static inline void bnx2x_init_vlan_mac_common(struct bnx2x_vlan_mac_obj *o,
1930         u8 cl_id, u32 cid, u8 func_id, void *rdata, dma_addr_t rdata_mapping,
1931         int state, unsigned long *pstate, bnx2x_obj_type type,
1932         struct bnx2x_credit_pool_obj *macs_pool,
1933         struct bnx2x_credit_pool_obj *vlans_pool)
1934 {
1935         INIT_LIST_HEAD(&o->head);
1936         o->head_reader = 0;
1937         o->head_exe_request = false;
1938         o->saved_ramrod_flags = 0;
1939
1940         o->macs_pool = macs_pool;
1941         o->vlans_pool = vlans_pool;
1942
1943         o->delete_all = bnx2x_vlan_mac_del_all;
1944         o->restore = bnx2x_vlan_mac_restore;
1945         o->complete = bnx2x_complete_vlan_mac;
1946         o->wait = bnx2x_wait_vlan_mac;
1947
1948         bnx2x_init_raw_obj(&o->raw, cl_id, cid, func_id, rdata, rdata_mapping,
1949                            state, pstate, type);
1950 }
1951
1952 void bnx2x_init_mac_obj(struct bnx2x *bp,
1953                         struct bnx2x_vlan_mac_obj *mac_obj,
1954                         u8 cl_id, u32 cid, u8 func_id, void *rdata,
1955                         dma_addr_t rdata_mapping, int state,
1956                         unsigned long *pstate, bnx2x_obj_type type,
1957                         struct bnx2x_credit_pool_obj *macs_pool)
1958 {
1959         union bnx2x_qable_obj *qable_obj = (union bnx2x_qable_obj *)mac_obj;
1960
1961         bnx2x_init_vlan_mac_common(mac_obj, cl_id, cid, func_id, rdata,
1962                                    rdata_mapping, state, pstate, type,
1963                                    macs_pool, NULL);
1964
1965         /* CAM credit pool handling */
1966         mac_obj->get_credit = bnx2x_get_credit_mac;
1967         mac_obj->put_credit = bnx2x_put_credit_mac;
1968         mac_obj->get_cam_offset = bnx2x_get_cam_offset_mac;
1969         mac_obj->put_cam_offset = bnx2x_put_cam_offset_mac;
1970
1971         if (CHIP_IS_E1x(bp)) {
1972                 mac_obj->set_one_rule      = bnx2x_set_one_mac_e1x;
1973                 mac_obj->check_del         = bnx2x_check_mac_del;
1974                 mac_obj->check_add         = bnx2x_check_mac_add;
1975                 mac_obj->check_move        = bnx2x_check_move_always_err;
1976                 mac_obj->ramrod_cmd        = RAMROD_CMD_ID_ETH_SET_MAC;
1977
1978                 /* Exe Queue */
1979                 bnx2x_exe_queue_init(bp,
1980                                      &mac_obj->exe_queue, 1, qable_obj,
1981                                      bnx2x_validate_vlan_mac,
1982                                      bnx2x_remove_vlan_mac,
1983                                      bnx2x_optimize_vlan_mac,
1984                                      bnx2x_execute_vlan_mac,
1985                                      bnx2x_exeq_get_mac);
1986         } else {
1987                 mac_obj->set_one_rule      = bnx2x_set_one_mac_e2;
1988                 mac_obj->check_del         = bnx2x_check_mac_del;
1989                 mac_obj->check_add         = bnx2x_check_mac_add;
1990                 mac_obj->check_move        = bnx2x_check_move;
1991                 mac_obj->ramrod_cmd        =
1992                         RAMROD_CMD_ID_ETH_CLASSIFICATION_RULES;
1993                 mac_obj->get_n_elements    = bnx2x_get_n_elements;
1994
1995                 /* Exe Queue */
1996                 bnx2x_exe_queue_init(bp,
1997                                      &mac_obj->exe_queue, CLASSIFY_RULES_COUNT,
1998                                      qable_obj, bnx2x_validate_vlan_mac,
1999                                      bnx2x_remove_vlan_mac,
2000                                      bnx2x_optimize_vlan_mac,
2001                                      bnx2x_execute_vlan_mac,
2002                                      bnx2x_exeq_get_mac);
2003         }
2004 }
2005
2006 void bnx2x_init_vlan_obj(struct bnx2x *bp,
2007                          struct bnx2x_vlan_mac_obj *vlan_obj,
2008                          u8 cl_id, u32 cid, u8 func_id, void *rdata,
2009                          dma_addr_t rdata_mapping, int state,
2010                          unsigned long *pstate, bnx2x_obj_type type,
2011                          struct bnx2x_credit_pool_obj *vlans_pool)
2012 {
2013         union bnx2x_qable_obj *qable_obj = (union bnx2x_qable_obj *)vlan_obj;
2014
2015         bnx2x_init_vlan_mac_common(vlan_obj, cl_id, cid, func_id, rdata,
2016                                    rdata_mapping, state, pstate, type, NULL,
2017                                    vlans_pool);
2018
2019         vlan_obj->get_credit = bnx2x_get_credit_vlan;
2020         vlan_obj->put_credit = bnx2x_put_credit_vlan;
2021         vlan_obj->get_cam_offset = bnx2x_get_cam_offset_vlan;
2022         vlan_obj->put_cam_offset = bnx2x_put_cam_offset_vlan;
2023
2024         if (CHIP_IS_E1x(bp)) {
2025                 BNX2X_ERR("Do not support chips others than E2 and newer\n");
2026                 BUG();
2027         } else {
2028                 vlan_obj->set_one_rule      = bnx2x_set_one_vlan_e2;
2029                 vlan_obj->check_del         = bnx2x_check_vlan_del;
2030                 vlan_obj->check_add         = bnx2x_check_vlan_add;
2031                 vlan_obj->check_move        = bnx2x_check_move;
2032                 vlan_obj->ramrod_cmd        =
2033                         RAMROD_CMD_ID_ETH_CLASSIFICATION_RULES;
2034                 vlan_obj->get_n_elements    = bnx2x_get_n_elements;
2035
2036                 /* Exe Queue */
2037                 bnx2x_exe_queue_init(bp,
2038                                      &vlan_obj->exe_queue, CLASSIFY_RULES_COUNT,
2039                                      qable_obj, bnx2x_validate_vlan_mac,
2040                                      bnx2x_remove_vlan_mac,
2041                                      bnx2x_optimize_vlan_mac,
2042                                      bnx2x_execute_vlan_mac,
2043                                      bnx2x_exeq_get_vlan);
2044         }
2045 }
2046
2047 /* RX_MODE verbs: DROP_ALL/ACCEPT_ALL/ACCEPT_ALL_MULTI/ACCEPT_ALL_VLAN/NORMAL */
2048 static inline void __storm_memset_mac_filters(struct bnx2x *bp,
2049                         struct tstorm_eth_mac_filter_config *mac_filters,
2050                         u16 pf_id)
2051 {
2052         size_t size = sizeof(struct tstorm_eth_mac_filter_config);
2053
2054         u32 addr = BAR_TSTRORM_INTMEM +
2055                         TSTORM_MAC_FILTER_CONFIG_OFFSET(pf_id);
2056
2057         __storm_memset_struct(bp, addr, size, (u32 *)mac_filters);
2058 }
2059
2060 static int bnx2x_set_rx_mode_e1x(struct bnx2x *bp,
2061                                  struct bnx2x_rx_mode_ramrod_params *p)
2062 {
2063         /* update the bp MAC filter structure */
2064         u32 mask = (1 << p->cl_id);
2065
2066         struct tstorm_eth_mac_filter_config *mac_filters =
2067                 (struct tstorm_eth_mac_filter_config *)p->rdata;
2068
2069         /* initial setting is drop-all */
2070         u8 drop_all_ucast = 1, drop_all_mcast = 1;
2071         u8 accp_all_ucast = 0, accp_all_bcast = 0, accp_all_mcast = 0;
2072         u8 unmatched_unicast = 0;
2073
2074     /* In e1x there we only take into account rx accept flag since tx switching
2075      * isn't enabled. */
2076         if (test_bit(BNX2X_ACCEPT_UNICAST, &p->rx_accept_flags))
2077                 /* accept matched ucast */
2078                 drop_all_ucast = 0;
2079
2080         if (test_bit(BNX2X_ACCEPT_MULTICAST, &p->rx_accept_flags))
2081                 /* accept matched mcast */
2082                 drop_all_mcast = 0;
2083
2084         if (test_bit(BNX2X_ACCEPT_ALL_UNICAST, &p->rx_accept_flags)) {
2085                 /* accept all mcast */
2086                 drop_all_ucast = 0;
2087                 accp_all_ucast = 1;
2088         }
2089         if (test_bit(BNX2X_ACCEPT_ALL_MULTICAST, &p->rx_accept_flags)) {
2090                 /* accept all mcast */
2091                 drop_all_mcast = 0;
2092                 accp_all_mcast = 1;
2093         }
2094         if (test_bit(BNX2X_ACCEPT_BROADCAST, &p->rx_accept_flags))
2095                 /* accept (all) bcast */
2096                 accp_all_bcast = 1;
2097         if (test_bit(BNX2X_ACCEPT_UNMATCHED, &p->rx_accept_flags))
2098                 /* accept unmatched unicasts */
2099                 unmatched_unicast = 1;
2100
2101         mac_filters->ucast_drop_all = drop_all_ucast ?
2102                 mac_filters->ucast_drop_all | mask :
2103                 mac_filters->ucast_drop_all & ~mask;
2104
2105         mac_filters->mcast_drop_all = drop_all_mcast ?
2106                 mac_filters->mcast_drop_all | mask :
2107                 mac_filters->mcast_drop_all & ~mask;
2108
2109         mac_filters->ucast_accept_all = accp_all_ucast ?
2110                 mac_filters->ucast_accept_all | mask :
2111                 mac_filters->ucast_accept_all & ~mask;
2112
2113         mac_filters->mcast_accept_all = accp_all_mcast ?
2114                 mac_filters->mcast_accept_all | mask :
2115                 mac_filters->mcast_accept_all & ~mask;
2116
2117         mac_filters->bcast_accept_all = accp_all_bcast ?
2118                 mac_filters->bcast_accept_all | mask :
2119                 mac_filters->bcast_accept_all & ~mask;
2120
2121         mac_filters->unmatched_unicast = unmatched_unicast ?
2122                 mac_filters->unmatched_unicast | mask :
2123                 mac_filters->unmatched_unicast & ~mask;
2124
2125         DP(BNX2X_MSG_SP, "drop_ucast 0x%x\ndrop_mcast 0x%x\n accp_ucast 0x%x\n"
2126                          "accp_mcast 0x%x\naccp_bcast 0x%x\n",
2127            mac_filters->ucast_drop_all, mac_filters->mcast_drop_all,
2128            mac_filters->ucast_accept_all, mac_filters->mcast_accept_all,
2129            mac_filters->bcast_accept_all);
2130
2131         /* write the MAC filter structure*/
2132         __storm_memset_mac_filters(bp, mac_filters, p->func_id);
2133
2134         /* The operation is completed */
2135         clear_bit(p->state, p->pstate);
2136         smp_mb__after_atomic();
2137
2138         return 0;
2139 }
2140
2141 /* Setup ramrod data */
2142 static inline void bnx2x_rx_mode_set_rdata_hdr_e2(u32 cid,
2143                                 struct eth_classify_header *hdr,
2144                                 u8 rule_cnt)
2145 {
2146         hdr->echo = cpu_to_le32(cid);
2147         hdr->rule_cnt = rule_cnt;
2148 }
2149
2150 static inline void bnx2x_rx_mode_set_cmd_state_e2(struct bnx2x *bp,
2151                                 unsigned long *accept_flags,
2152                                 struct eth_filter_rules_cmd *cmd,
2153                                 bool clear_accept_all)
2154 {
2155         u16 state;
2156
2157         /* start with 'drop-all' */
2158         state = ETH_FILTER_RULES_CMD_UCAST_DROP_ALL |
2159                 ETH_FILTER_RULES_CMD_MCAST_DROP_ALL;
2160
2161         if (test_bit(BNX2X_ACCEPT_UNICAST, accept_flags))
2162                 state &= ~ETH_FILTER_RULES_CMD_UCAST_DROP_ALL;
2163
2164         if (test_bit(BNX2X_ACCEPT_MULTICAST, accept_flags))
2165                 state &= ~ETH_FILTER_RULES_CMD_MCAST_DROP_ALL;
2166
2167         if (test_bit(BNX2X_ACCEPT_ALL_UNICAST, accept_flags)) {
2168                 state &= ~ETH_FILTER_RULES_CMD_UCAST_DROP_ALL;
2169                 state |= ETH_FILTER_RULES_CMD_UCAST_ACCEPT_ALL;
2170         }
2171
2172         if (test_bit(BNX2X_ACCEPT_ALL_MULTICAST, accept_flags)) {
2173                 state |= ETH_FILTER_RULES_CMD_MCAST_ACCEPT_ALL;
2174                 state &= ~ETH_FILTER_RULES_CMD_MCAST_DROP_ALL;
2175         }
2176
2177         if (test_bit(BNX2X_ACCEPT_BROADCAST, accept_flags))
2178                 state |= ETH_FILTER_RULES_CMD_BCAST_ACCEPT_ALL;
2179
2180         if (test_bit(BNX2X_ACCEPT_UNMATCHED, accept_flags)) {
2181                 state &= ~ETH_FILTER_RULES_CMD_UCAST_DROP_ALL;
2182                 state |= ETH_FILTER_RULES_CMD_UCAST_ACCEPT_UNMATCHED;
2183         }
2184
2185         if (test_bit(BNX2X_ACCEPT_ANY_VLAN, accept_flags))
2186                 state |= ETH_FILTER_RULES_CMD_ACCEPT_ANY_VLAN;
2187
2188         /* Clear ACCEPT_ALL_XXX flags for FCoE L2 Queue */
2189         if (clear_accept_all) {
2190                 state &= ~ETH_FILTER_RULES_CMD_MCAST_ACCEPT_ALL;
2191                 state &= ~ETH_FILTER_RULES_CMD_BCAST_ACCEPT_ALL;
2192                 state &= ~ETH_FILTER_RULES_CMD_UCAST_ACCEPT_ALL;
2193                 state &= ~ETH_FILTER_RULES_CMD_UCAST_ACCEPT_UNMATCHED;
2194         }
2195
2196         cmd->state = cpu_to_le16(state);
2197 }
2198
2199 static int bnx2x_set_rx_mode_e2(struct bnx2x *bp,
2200                                 struct bnx2x_rx_mode_ramrod_params *p)
2201 {
2202         struct eth_filter_rules_ramrod_data *data = p->rdata;
2203         int rc;
2204         u8 rule_idx = 0;
2205
2206         /* Reset the ramrod data buffer */
2207         memset(data, 0, sizeof(*data));
2208
2209         /* Setup ramrod data */
2210
2211         /* Tx (internal switching) */
2212         if (test_bit(RAMROD_TX, &p->ramrod_flags)) {
2213                 data->rules[rule_idx].client_id = p->cl_id;
2214                 data->rules[rule_idx].func_id = p->func_id;
2215
2216                 data->rules[rule_idx].cmd_general_data =
2217                         ETH_FILTER_RULES_CMD_TX_CMD;
2218
2219                 bnx2x_rx_mode_set_cmd_state_e2(bp, &p->tx_accept_flags,
2220                                                &(data->rules[rule_idx++]),
2221                                                false);
2222         }
2223
2224         /* Rx */
2225         if (test_bit(RAMROD_RX, &p->ramrod_flags)) {
2226                 data->rules[rule_idx].client_id = p->cl_id;
2227                 data->rules[rule_idx].func_id = p->func_id;
2228
2229                 data->rules[rule_idx].cmd_general_data =
2230                         ETH_FILTER_RULES_CMD_RX_CMD;
2231
2232                 bnx2x_rx_mode_set_cmd_state_e2(bp, &p->rx_accept_flags,
2233                                                &(data->rules[rule_idx++]),
2234                                                false);
2235         }
2236
2237         /* If FCoE Queue configuration has been requested configure the Rx and
2238          * internal switching modes for this queue in separate rules.
2239          *
2240          * FCoE queue shell never be set to ACCEPT_ALL packets of any sort:
2241          * MCAST_ALL, UCAST_ALL, BCAST_ALL and UNMATCHED.
2242          */
2243         if (test_bit(BNX2X_RX_MODE_FCOE_ETH, &p->rx_mode_flags)) {
2244                 /*  Tx (internal switching) */
2245                 if (test_bit(RAMROD_TX, &p->ramrod_flags)) {
2246                         data->rules[rule_idx].client_id = bnx2x_fcoe(bp, cl_id);
2247                         data->rules[rule_idx].func_id = p->func_id;
2248
2249                         data->rules[rule_idx].cmd_general_data =
2250                                                 ETH_FILTER_RULES_CMD_TX_CMD;
2251
2252                         bnx2x_rx_mode_set_cmd_state_e2(bp, &p->tx_accept_flags,
2253                                                        &(data->rules[rule_idx]),
2254                                                        true);
2255                         rule_idx++;
2256                 }
2257
2258                 /* Rx */
2259                 if (test_bit(RAMROD_RX, &p->ramrod_flags)) {
2260                         data->rules[rule_idx].client_id = bnx2x_fcoe(bp, cl_id);
2261                         data->rules[rule_idx].func_id = p->func_id;
2262
2263                         data->rules[rule_idx].cmd_general_data =
2264                                                 ETH_FILTER_RULES_CMD_RX_CMD;
2265
2266                         bnx2x_rx_mode_set_cmd_state_e2(bp, &p->rx_accept_flags,
2267                                                        &(data->rules[rule_idx]),
2268                                                        true);
2269                         rule_idx++;
2270                 }
2271         }
2272
2273         /* Set the ramrod header (most importantly - number of rules to
2274          * configure).
2275          */
2276         bnx2x_rx_mode_set_rdata_hdr_e2(p->cid, &data->header, rule_idx);
2277
2278         DP(BNX2X_MSG_SP, "About to configure %d rules, rx_accept_flags 0x%lx, tx_accept_flags 0x%lx\n",
2279                          data->header.rule_cnt, p->rx_accept_flags,
2280                          p->tx_accept_flags);
2281
2282         /* No need for an explicit memory barrier here as long as we
2283          * ensure the ordering of writing to the SPQ element
2284          * and updating of the SPQ producer which involves a memory
2285          * read. If the memory read is removed we will have to put a
2286          * full memory barrier there (inside bnx2x_sp_post()).
2287          */
2288
2289         /* Send a ramrod */
2290         rc = bnx2x_sp_post(bp, RAMROD_CMD_ID_ETH_FILTER_RULES, p->cid,
2291                            U64_HI(p->rdata_mapping),
2292                            U64_LO(p->rdata_mapping),
2293                            ETH_CONNECTION_TYPE);
2294         if (rc)
2295                 return rc;
2296
2297         /* Ramrod completion is pending */
2298         return 1;
2299 }
2300
2301 static int bnx2x_wait_rx_mode_comp_e2(struct bnx2x *bp,
2302                                       struct bnx2x_rx_mode_ramrod_params *p)
2303 {
2304         return bnx2x_state_wait(bp, p->state, p->pstate);
2305 }
2306
2307 static int bnx2x_empty_rx_mode_wait(struct bnx2x *bp,
2308                                     struct bnx2x_rx_mode_ramrod_params *p)
2309 {
2310         /* Do nothing */
2311         return 0;
2312 }
2313
2314 int bnx2x_config_rx_mode(struct bnx2x *bp,
2315                          struct bnx2x_rx_mode_ramrod_params *p)
2316 {
2317         int rc;
2318
2319         /* Configure the new classification in the chip */
2320         rc = p->rx_mode_obj->config_rx_mode(bp, p);
2321         if (rc < 0)
2322                 return rc;
2323
2324         /* Wait for a ramrod completion if was requested */
2325         if (test_bit(RAMROD_COMP_WAIT, &p->ramrod_flags)) {
2326                 rc = p->rx_mode_obj->wait_comp(bp, p);
2327                 if (rc)
2328                         return rc;
2329         }
2330
2331         return rc;
2332 }
2333
2334 void bnx2x_init_rx_mode_obj(struct bnx2x *bp,
2335                             struct bnx2x_rx_mode_obj *o)
2336 {
2337         if (CHIP_IS_E1x(bp)) {
2338                 o->wait_comp      = bnx2x_empty_rx_mode_wait;
2339                 o->config_rx_mode = bnx2x_set_rx_mode_e1x;
2340         } else {
2341                 o->wait_comp      = bnx2x_wait_rx_mode_comp_e2;
2342                 o->config_rx_mode = bnx2x_set_rx_mode_e2;
2343         }
2344 }
2345
2346 /********************* Multicast verbs: SET, CLEAR ****************************/
2347 static inline u8 bnx2x_mcast_bin_from_mac(u8 *mac)
2348 {
2349         return (crc32c_le(0, mac, ETH_ALEN) >> 24) & 0xff;
2350 }
2351
2352 struct bnx2x_mcast_mac_elem {
2353         struct list_head link;
2354         u8 mac[ETH_ALEN];
2355         u8 pad[2]; /* For a natural alignment of the following buffer */
2356 };
2357
2358 struct bnx2x_pending_mcast_cmd {
2359         struct list_head link;
2360         int type; /* BNX2X_MCAST_CMD_X */
2361         union {
2362                 struct list_head macs_head;
2363                 u32 macs_num; /* Needed for DEL command */
2364                 int next_bin; /* Needed for RESTORE flow with aprox match */
2365         } data;
2366
2367         bool done; /* set to true, when the command has been handled,
2368                     * practically used in 57712 handling only, where one pending
2369                     * command may be handled in a few operations. As long as for
2370                     * other chips every operation handling is completed in a
2371                     * single ramrod, there is no need to utilize this field.
2372                     */
2373 };
2374
2375 static int bnx2x_mcast_wait(struct bnx2x *bp,
2376                             struct bnx2x_mcast_obj *o)
2377 {
2378         if (bnx2x_state_wait(bp, o->sched_state, o->raw.pstate) ||
2379                         o->raw.wait_comp(bp, &o->raw))
2380                 return -EBUSY;
2381
2382         return 0;
2383 }
2384
2385 static int bnx2x_mcast_enqueue_cmd(struct bnx2x *bp,
2386                                    struct bnx2x_mcast_obj *o,
2387                                    struct bnx2x_mcast_ramrod_params *p,
2388                                    enum bnx2x_mcast_cmd cmd)
2389 {
2390         int total_sz;
2391         struct bnx2x_pending_mcast_cmd *new_cmd;
2392         struct bnx2x_mcast_mac_elem *cur_mac = NULL;
2393         struct bnx2x_mcast_list_elem *pos;
2394         int macs_list_len = ((cmd == BNX2X_MCAST_CMD_ADD) ?
2395                              p->mcast_list_len : 0);
2396
2397         /* If the command is empty ("handle pending commands only"), break */
2398         if (!p->mcast_list_len)
2399                 return 0;
2400
2401         total_sz = sizeof(*new_cmd) +
2402                 macs_list_len * sizeof(struct bnx2x_mcast_mac_elem);
2403
2404         /* Add mcast is called under spin_lock, thus calling with GFP_ATOMIC */
2405         new_cmd = kzalloc(total_sz, GFP_ATOMIC);
2406
2407         if (!new_cmd)
2408                 return -ENOMEM;
2409
2410         DP(BNX2X_MSG_SP, "About to enqueue a new %d command. macs_list_len=%d\n",
2411            cmd, macs_list_len);
2412
2413         INIT_LIST_HEAD(&new_cmd->data.macs_head);
2414
2415         new_cmd->type = cmd;
2416         new_cmd->done = false;
2417
2418         switch (cmd) {
2419         case BNX2X_MCAST_CMD_ADD:
2420                 cur_mac = (struct bnx2x_mcast_mac_elem *)
2421                           ((u8 *)new_cmd + sizeof(*new_cmd));
2422
2423                 /* Push the MACs of the current command into the pending command
2424                  * MACs list: FIFO
2425                  */
2426                 list_for_each_entry(pos, &p->mcast_list, link) {
2427                         memcpy(cur_mac->mac, pos->mac, ETH_ALEN);
2428                         list_add_tail(&cur_mac->link, &new_cmd->data.macs_head);
2429                         cur_mac++;
2430                 }
2431
2432                 break;
2433
2434         case BNX2X_MCAST_CMD_DEL:
2435                 new_cmd->data.macs_num = p->mcast_list_len;
2436                 break;
2437
2438         case BNX2X_MCAST_CMD_RESTORE:
2439                 new_cmd->data.next_bin = 0;
2440                 break;
2441
2442         default:
2443                 kfree(new_cmd);
2444                 BNX2X_ERR("Unknown command: %d\n", cmd);
2445                 return -EINVAL;
2446         }
2447
2448         /* Push the new pending command to the tail of the pending list: FIFO */
2449         list_add_tail(&new_cmd->link, &o->pending_cmds_head);
2450
2451         o->set_sched(o);
2452
2453         return 1;
2454 }
2455
2456 /**
2457  * bnx2x_mcast_get_next_bin - get the next set bin (index)
2458  *
2459  * @o:
2460  * @last:       index to start looking from (including)
2461  *
2462  * returns the next found (set) bin or a negative value if none is found.
2463  */
2464 static inline int bnx2x_mcast_get_next_bin(struct bnx2x_mcast_obj *o, int last)
2465 {
2466         int i, j, inner_start = last % BIT_VEC64_ELEM_SZ;
2467
2468         for (i = last / BIT_VEC64_ELEM_SZ; i < BNX2X_MCAST_VEC_SZ; i++) {
2469                 if (o->registry.aprox_match.vec[i])
2470                         for (j = inner_start; j < BIT_VEC64_ELEM_SZ; j++) {
2471                                 int cur_bit = j + BIT_VEC64_ELEM_SZ * i;
2472                                 if (BIT_VEC64_TEST_BIT(o->registry.aprox_match.
2473                                                        vec, cur_bit)) {
2474                                         return cur_bit;
2475                                 }
2476                         }
2477                 inner_start = 0;
2478         }
2479
2480         /* None found */
2481         return -1;
2482 }
2483
2484 /**
2485  * bnx2x_mcast_clear_first_bin - find the first set bin and clear it
2486  *
2487  * @o:
2488  *
2489  * returns the index of the found bin or -1 if none is found
2490  */
2491 static inline int bnx2x_mcast_clear_first_bin(struct bnx2x_mcast_obj *o)
2492 {
2493         int cur_bit = bnx2x_mcast_get_next_bin(o, 0);
2494
2495         if (cur_bit >= 0)
2496                 BIT_VEC64_CLEAR_BIT(o->registry.aprox_match.vec, cur_bit);
2497
2498         return cur_bit;
2499 }
2500
2501 static inline u8 bnx2x_mcast_get_rx_tx_flag(struct bnx2x_mcast_obj *o)
2502 {
2503         struct bnx2x_raw_obj *raw = &o->raw;
2504         u8 rx_tx_flag = 0;
2505
2506         if ((raw->obj_type == BNX2X_OBJ_TYPE_TX) ||
2507             (raw->obj_type == BNX2X_OBJ_TYPE_RX_TX))
2508                 rx_tx_flag |= ETH_MULTICAST_RULES_CMD_TX_CMD;
2509
2510         if ((raw->obj_type == BNX2X_OBJ_TYPE_RX) ||
2511             (raw->obj_type == BNX2X_OBJ_TYPE_RX_TX))
2512                 rx_tx_flag |= ETH_MULTICAST_RULES_CMD_RX_CMD;
2513
2514         return rx_tx_flag;
2515 }
2516
2517 static void bnx2x_mcast_set_one_rule_e2(struct bnx2x *bp,
2518                                         struct bnx2x_mcast_obj *o, int idx,
2519                                         union bnx2x_mcast_config_data *cfg_data,
2520                                         enum bnx2x_mcast_cmd cmd)
2521 {
2522         struct bnx2x_raw_obj *r = &o->raw;
2523         struct eth_multicast_rules_ramrod_data *data =
2524                 (struct eth_multicast_rules_ramrod_data *)(r->rdata);
2525         u8 func_id = r->func_id;
2526         u8 rx_tx_add_flag = bnx2x_mcast_get_rx_tx_flag(o);
2527         int bin;
2528
2529         if ((cmd == BNX2X_MCAST_CMD_ADD) || (cmd == BNX2X_MCAST_CMD_RESTORE))
2530                 rx_tx_add_flag |= ETH_MULTICAST_RULES_CMD_IS_ADD;
2531
2532         data->rules[idx].cmd_general_data |= rx_tx_add_flag;
2533
2534         /* Get a bin and update a bins' vector */
2535         switch (cmd) {
2536         case BNX2X_MCAST_CMD_ADD:
2537                 bin = bnx2x_mcast_bin_from_mac(cfg_data->mac);
2538                 BIT_VEC64_SET_BIT(o->registry.aprox_match.vec, bin);
2539                 break;
2540
2541         case BNX2X_MCAST_CMD_DEL:
2542                 /* If there were no more bins to clear
2543                  * (bnx2x_mcast_clear_first_bin() returns -1) then we would
2544                  * clear any (0xff) bin.
2545                  * See bnx2x_mcast_validate_e2() for explanation when it may
2546                  * happen.
2547                  */
2548                 bin = bnx2x_mcast_clear_first_bin(o);
2549                 break;
2550
2551         case BNX2X_MCAST_CMD_RESTORE:
2552                 bin = cfg_data->bin;
2553                 break;
2554
2555         default:
2556                 BNX2X_ERR("Unknown command: %d\n", cmd);
2557                 return;
2558         }
2559
2560         DP(BNX2X_MSG_SP, "%s bin %d\n",
2561                          ((rx_tx_add_flag & ETH_MULTICAST_RULES_CMD_IS_ADD) ?
2562                          "Setting"  : "Clearing"), bin);
2563
2564         data->rules[idx].bin_id    = (u8)bin;
2565         data->rules[idx].func_id   = func_id;
2566         data->rules[idx].engine_id = o->engine_id;
2567 }
2568
2569 /**
2570  * bnx2x_mcast_handle_restore_cmd_e2 - restore configuration from the registry
2571  *
2572  * @bp:         device handle
2573  * @o:
2574  * @start_bin:  index in the registry to start from (including)
2575  * @rdata_idx:  index in the ramrod data to start from
2576  *
2577  * returns last handled bin index or -1 if all bins have been handled
2578  */
2579 static inline int bnx2x_mcast_handle_restore_cmd_e2(
2580         struct bnx2x *bp, struct bnx2x_mcast_obj *o , int start_bin,
2581         int *rdata_idx)
2582 {
2583         int cur_bin, cnt = *rdata_idx;
2584         union bnx2x_mcast_config_data cfg_data = {NULL};
2585
2586         /* go through the registry and configure the bins from it */
2587         for (cur_bin = bnx2x_mcast_get_next_bin(o, start_bin); cur_bin >= 0;
2588             cur_bin = bnx2x_mcast_get_next_bin(o, cur_bin + 1)) {
2589
2590                 cfg_data.bin = (u8)cur_bin;
2591                 o->set_one_rule(bp, o, cnt, &cfg_data,
2592                                 BNX2X_MCAST_CMD_RESTORE);
2593
2594                 cnt++;
2595
2596                 DP(BNX2X_MSG_SP, "About to configure a bin %d\n", cur_bin);
2597
2598                 /* Break if we reached the maximum number
2599                  * of rules.
2600                  */
2601                 if (cnt >= o->max_cmd_len)
2602                         break;
2603         }
2604
2605         *rdata_idx = cnt;
2606
2607         return cur_bin;
2608 }
2609
2610 static inline void bnx2x_mcast_hdl_pending_add_e2(struct bnx2x *bp,
2611         struct bnx2x_mcast_obj *o, struct bnx2x_pending_mcast_cmd *cmd_pos,
2612         int *line_idx)
2613 {
2614         struct bnx2x_mcast_mac_elem *pmac_pos, *pmac_pos_n;
2615         int cnt = *line_idx;
2616         union bnx2x_mcast_config_data cfg_data = {NULL};
2617
2618         list_for_each_entry_safe(pmac_pos, pmac_pos_n, &cmd_pos->data.macs_head,
2619                                  link) {
2620
2621                 cfg_data.mac = &pmac_pos->mac[0];
2622                 o->set_one_rule(bp, o, cnt, &cfg_data, cmd_pos->type);
2623
2624                 cnt++;
2625
2626                 DP(BNX2X_MSG_SP, "About to configure %pM mcast MAC\n",
2627                    pmac_pos->mac);
2628
2629                 list_del(&pmac_pos->link);
2630
2631                 /* Break if we reached the maximum number
2632                  * of rules.
2633                  */
2634                 if (cnt >= o->max_cmd_len)
2635                         break;
2636         }
2637
2638         *line_idx = cnt;
2639
2640         /* if no more MACs to configure - we are done */
2641         if (list_empty(&cmd_pos->data.macs_head))
2642                 cmd_pos->done = true;
2643 }
2644
2645 static inline void bnx2x_mcast_hdl_pending_del_e2(struct bnx2x *bp,
2646         struct bnx2x_mcast_obj *o, struct bnx2x_pending_mcast_cmd *cmd_pos,
2647         int *line_idx)
2648 {
2649         int cnt = *line_idx;
2650
2651         while (cmd_pos->data.macs_num) {
2652                 o->set_one_rule(bp, o, cnt, NULL, cmd_pos->type);
2653
2654                 cnt++;
2655
2656                 cmd_pos->data.macs_num--;
2657
2658                   DP(BNX2X_MSG_SP, "Deleting MAC. %d left,cnt is %d\n",
2659                                    cmd_pos->data.macs_num, cnt);
2660
2661                 /* Break if we reached the maximum
2662                  * number of rules.
2663                  */
2664                 if (cnt >= o->max_cmd_len)
2665                         break;
2666         }
2667
2668         *line_idx = cnt;
2669
2670         /* If we cleared all bins - we are done */
2671         if (!cmd_pos->data.macs_num)
2672                 cmd_pos->done = true;
2673 }
2674
2675 static inline void bnx2x_mcast_hdl_pending_restore_e2(struct bnx2x *bp,
2676         struct bnx2x_mcast_obj *o, struct bnx2x_pending_mcast_cmd *cmd_pos,
2677         int *line_idx)
2678 {
2679         cmd_pos->data.next_bin = o->hdl_restore(bp, o, cmd_pos->data.next_bin,
2680                                                 line_idx);
2681
2682         if (cmd_pos->data.next_bin < 0)
2683                 /* If o->set_restore returned -1 we are done */
2684                 cmd_pos->done = true;
2685         else
2686                 /* Start from the next bin next time */
2687                 cmd_pos->data.next_bin++;
2688 }
2689
2690 static inline int bnx2x_mcast_handle_pending_cmds_e2(struct bnx2x *bp,
2691                                 struct bnx2x_mcast_ramrod_params *p)
2692 {
2693         struct bnx2x_pending_mcast_cmd *cmd_pos, *cmd_pos_n;
2694         int cnt = 0;
2695         struct bnx2x_mcast_obj *o = p->mcast_obj;
2696
2697         list_for_each_entry_safe(cmd_pos, cmd_pos_n, &o->pending_cmds_head,
2698                                  link) {
2699                 switch (cmd_pos->type) {
2700                 case BNX2X_MCAST_CMD_ADD:
2701                         bnx2x_mcast_hdl_pending_add_e2(bp, o, cmd_pos, &cnt);
2702                         break;
2703
2704                 case BNX2X_MCAST_CMD_DEL:
2705                         bnx2x_mcast_hdl_pending_del_e2(bp, o, cmd_pos, &cnt);
2706                         break;
2707
2708                 case BNX2X_MCAST_CMD_RESTORE:
2709                         bnx2x_mcast_hdl_pending_restore_e2(bp, o, cmd_pos,
2710                                                            &cnt);
2711                         break;
2712
2713                 default:
2714                         BNX2X_ERR("Unknown command: %d\n", cmd_pos->type);
2715                         return -EINVAL;
2716                 }
2717
2718                 /* If the command has been completed - remove it from the list
2719                  * and free the memory
2720                  */
2721                 if (cmd_pos->done) {
2722                         list_del(&cmd_pos->link);
2723                         kfree(cmd_pos);
2724                 }
2725
2726                 /* Break if we reached the maximum number of rules */
2727                 if (cnt >= o->max_cmd_len)
2728                         break;
2729         }
2730
2731         return cnt;
2732 }
2733
2734 static inline void bnx2x_mcast_hdl_add(struct bnx2x *bp,
2735         struct bnx2x_mcast_obj *o, struct bnx2x_mcast_ramrod_params *p,
2736         int *line_idx)
2737 {
2738         struct bnx2x_mcast_list_elem *mlist_pos;
2739         union bnx2x_mcast_config_data cfg_data = {NULL};
2740         int cnt = *line_idx;
2741
2742         list_for_each_entry(mlist_pos, &p->mcast_list, link) {
2743                 cfg_data.mac = mlist_pos->mac;
2744                 o->set_one_rule(bp, o, cnt, &cfg_data, BNX2X_MCAST_CMD_ADD);
2745
2746                 cnt++;
2747
2748                 DP(BNX2X_MSG_SP, "About to configure %pM mcast MAC\n",
2749                    mlist_pos->mac);
2750         }
2751
2752         *line_idx = cnt;
2753 }
2754
2755 static inline void bnx2x_mcast_hdl_del(struct bnx2x *bp,
2756         struct bnx2x_mcast_obj *o, struct bnx2x_mcast_ramrod_params *p,
2757         int *line_idx)
2758 {
2759         int cnt = *line_idx, i;
2760
2761         for (i = 0; i < p->mcast_list_len; i++) {
2762                 o->set_one_rule(bp, o, cnt, NULL, BNX2X_MCAST_CMD_DEL);
2763
2764                 cnt++;
2765
2766                 DP(BNX2X_MSG_SP, "Deleting MAC. %d left\n",
2767                                  p->mcast_list_len - i - 1);
2768         }
2769
2770         *line_idx = cnt;
2771 }
2772
2773 /**
2774  * bnx2x_mcast_handle_current_cmd -
2775  *
2776  * @bp:         device handle
2777  * @p:
2778  * @cmd:
2779  * @start_cnt:  first line in the ramrod data that may be used
2780  *
2781  * This function is called iff there is enough place for the current command in
2782  * the ramrod data.
2783  * Returns number of lines filled in the ramrod data in total.
2784  */
2785 static inline int bnx2x_mcast_handle_current_cmd(struct bnx2x *bp,
2786                         struct bnx2x_mcast_ramrod_params *p,
2787                         enum bnx2x_mcast_cmd cmd,
2788                         int start_cnt)
2789 {
2790         struct bnx2x_mcast_obj *o = p->mcast_obj;
2791         int cnt = start_cnt;
2792
2793         DP(BNX2X_MSG_SP, "p->mcast_list_len=%d\n", p->mcast_list_len);
2794
2795         switch (cmd) {
2796         case BNX2X_MCAST_CMD_ADD:
2797                 bnx2x_mcast_hdl_add(bp, o, p, &cnt);
2798                 break;
2799
2800         case BNX2X_MCAST_CMD_DEL:
2801                 bnx2x_mcast_hdl_del(bp, o, p, &cnt);
2802                 break;
2803
2804         case BNX2X_MCAST_CMD_RESTORE:
2805                 o->hdl_restore(bp, o, 0, &cnt);
2806                 break;
2807
2808         default:
2809                 BNX2X_ERR("Unknown command: %d\n", cmd);
2810                 return -EINVAL;
2811         }
2812
2813         /* The current command has been handled */
2814         p->mcast_list_len = 0;
2815
2816         return cnt;
2817 }
2818
2819 static int bnx2x_mcast_validate_e2(struct bnx2x *bp,
2820                                    struct bnx2x_mcast_ramrod_params *p,
2821                                    enum bnx2x_mcast_cmd cmd)
2822 {
2823         struct bnx2x_mcast_obj *o = p->mcast_obj;
2824         int reg_sz = o->get_registry_size(o);
2825
2826         switch (cmd) {
2827         /* DEL command deletes all currently configured MACs */
2828         case BNX2X_MCAST_CMD_DEL:
2829                 o->set_registry_size(o, 0);
2830                 /* Don't break */
2831
2832         /* RESTORE command will restore the entire multicast configuration */
2833         case BNX2X_MCAST_CMD_RESTORE:
2834                 /* Here we set the approximate amount of work to do, which in
2835                  * fact may be only less as some MACs in postponed ADD
2836                  * command(s) scheduled before this command may fall into
2837                  * the same bin and the actual number of bins set in the
2838                  * registry would be less than we estimated here. See
2839                  * bnx2x_mcast_set_one_rule_e2() for further details.
2840                  */
2841                 p->mcast_list_len = reg_sz;
2842                 break;
2843
2844         case BNX2X_MCAST_CMD_ADD:
2845         case BNX2X_MCAST_CMD_CONT:
2846                 /* Here we assume that all new MACs will fall into new bins.
2847                  * However we will correct the real registry size after we
2848                  * handle all pending commands.
2849                  */
2850                 o->set_registry_size(o, reg_sz + p->mcast_list_len);
2851                 break;
2852
2853         default:
2854                 BNX2X_ERR("Unknown command: %d\n", cmd);
2855                 return -EINVAL;
2856         }
2857
2858         /* Increase the total number of MACs pending to be configured */
2859         o->total_pending_num += p->mcast_list_len;
2860
2861         return 0;
2862 }
2863
2864 static void bnx2x_mcast_revert_e2(struct bnx2x *bp,
2865                                       struct bnx2x_mcast_ramrod_params *p,
2866                                       int old_num_bins)
2867 {
2868         struct bnx2x_mcast_obj *o = p->mcast_obj;
2869
2870         o->set_registry_size(o, old_num_bins);
2871         o->total_pending_num -= p->mcast_list_len;
2872 }
2873
2874 /**
2875  * bnx2x_mcast_set_rdata_hdr_e2 - sets a header values
2876  *
2877  * @bp:         device handle
2878  * @p:
2879  * @len:        number of rules to handle
2880  */
2881 static inline void bnx2x_mcast_set_rdata_hdr_e2(struct bnx2x *bp,
2882                                         struct bnx2x_mcast_ramrod_params *p,
2883                                         u8 len)
2884 {
2885         struct bnx2x_raw_obj *r = &p->mcast_obj->raw;
2886         struct eth_multicast_rules_ramrod_data *data =
2887                 (struct eth_multicast_rules_ramrod_data *)(r->rdata);
2888
2889         data->header.echo = cpu_to_le32((r->cid & BNX2X_SWCID_MASK) |
2890                                         (BNX2X_FILTER_MCAST_PENDING <<
2891                                          BNX2X_SWCID_SHIFT));
2892         data->header.rule_cnt = len;
2893 }
2894
2895 /**
2896  * bnx2x_mcast_refresh_registry_e2 - recalculate the actual number of set bins
2897  *
2898  * @bp:         device handle
2899  * @o:
2900  *
2901  * Recalculate the actual number of set bins in the registry using Brian
2902  * Kernighan's algorithm: it's execution complexity is as a number of set bins.
2903  *
2904  * returns 0 for the compliance with bnx2x_mcast_refresh_registry_e1().
2905  */
2906 static inline int bnx2x_mcast_refresh_registry_e2(struct bnx2x *bp,
2907                                                   struct bnx2x_mcast_obj *o)
2908 {
2909         int i, cnt = 0;
2910         u64 elem;
2911
2912         for (i = 0; i < BNX2X_MCAST_VEC_SZ; i++) {
2913                 elem = o->registry.aprox_match.vec[i];
2914                 for (; elem; cnt++)
2915                         elem &= elem - 1;
2916         }
2917
2918         o->set_registry_size(o, cnt);
2919
2920         return 0;
2921 }
2922
2923 static int bnx2x_mcast_setup_e2(struct bnx2x *bp,
2924                                 struct bnx2x_mcast_ramrod_params *p,
2925                                 enum bnx2x_mcast_cmd cmd)
2926 {
2927         struct bnx2x_raw_obj *raw = &p->mcast_obj->raw;
2928         struct bnx2x_mcast_obj *o = p->mcast_obj;
2929         struct eth_multicast_rules_ramrod_data *data =
2930                 (struct eth_multicast_rules_ramrod_data *)(raw->rdata);
2931         int cnt = 0, rc;
2932
2933         /* Reset the ramrod data buffer */
2934         memset(data, 0, sizeof(*data));
2935
2936         cnt = bnx2x_mcast_handle_pending_cmds_e2(bp, p);
2937
2938         /* If there are no more pending commands - clear SCHEDULED state */
2939         if (list_empty(&o->pending_cmds_head))
2940                 o->clear_sched(o);
2941
2942         /* The below may be true iff there was enough room in ramrod
2943          * data for all pending commands and for the current
2944          * command. Otherwise the current command would have been added
2945          * to the pending commands and p->mcast_list_len would have been
2946          * zeroed.
2947          */
2948         if (p->mcast_list_len > 0)
2949                 cnt = bnx2x_mcast_handle_current_cmd(bp, p, cmd, cnt);
2950
2951         /* We've pulled out some MACs - update the total number of
2952          * outstanding.
2953          */
2954         o->total_pending_num -= cnt;
2955
2956         /* send a ramrod */
2957         WARN_ON(o->total_pending_num < 0);
2958         WARN_ON(cnt > o->max_cmd_len);
2959
2960         bnx2x_mcast_set_rdata_hdr_e2(bp, p, (u8)cnt);
2961
2962         /* Update a registry size if there are no more pending operations.
2963          *
2964          * We don't want to change the value of the registry size if there are
2965          * pending operations because we want it to always be equal to the
2966          * exact or the approximate number (see bnx2x_mcast_validate_e2()) of
2967          * set bins after the last requested operation in order to properly
2968          * evaluate the size of the next DEL/RESTORE operation.
2969          *
2970          * Note that we update the registry itself during command(s) handling
2971          * - see bnx2x_mcast_set_one_rule_e2(). That's because for 57712 we
2972          * aggregate multiple commands (ADD/DEL/RESTORE) into one ramrod but
2973          * with a limited amount of update commands (per MAC/bin) and we don't
2974          * know in this scope what the actual state of bins configuration is
2975          * going to be after this ramrod.
2976          */
2977         if (!o->total_pending_num)
2978                 bnx2x_mcast_refresh_registry_e2(bp, o);
2979
2980         /* If CLEAR_ONLY was requested - don't send a ramrod and clear
2981          * RAMROD_PENDING status immediately.
2982          */
2983         if (test_bit(RAMROD_DRV_CLR_ONLY, &p->ramrod_flags)) {
2984                 raw->clear_pending(raw);
2985                 return 0;
2986         } else {
2987                 /* No need for an explicit memory barrier here as long as we
2988                  * ensure the ordering of writing to the SPQ element
2989                  * and updating of the SPQ producer which involves a memory
2990                  * read. If the memory read is removed we will have to put a
2991                  * full memory barrier there (inside bnx2x_sp_post()).
2992                  */
2993
2994                 /* Send a ramrod */
2995                 rc = bnx2x_sp_post(bp, RAMROD_CMD_ID_ETH_MULTICAST_RULES,
2996                                    raw->cid, U64_HI(raw->rdata_mapping),
2997                                    U64_LO(raw->rdata_mapping),
2998                                    ETH_CONNECTION_TYPE);
2999                 if (rc)
3000                         return rc;
3001
3002                 /* Ramrod completion is pending */
3003                 return 1;
3004         }
3005 }
3006
3007 static int bnx2x_mcast_validate_e1h(struct bnx2x *bp,
3008                                     struct bnx2x_mcast_ramrod_params *p,
3009                                     enum bnx2x_mcast_cmd cmd)
3010 {
3011         /* Mark, that there is a work to do */
3012         if ((cmd == BNX2X_MCAST_CMD_DEL) || (cmd == BNX2X_MCAST_CMD_RESTORE))
3013                 p->mcast_list_len = 1;
3014
3015         return 0;
3016 }
3017
3018 static void bnx2x_mcast_revert_e1h(struct bnx2x *bp,
3019                                        struct bnx2x_mcast_ramrod_params *p,
3020                                        int old_num_bins)
3021 {
3022         /* Do nothing */
3023 }
3024
3025 #define BNX2X_57711_SET_MC_FILTER(filter, bit) \
3026 do { \
3027         (filter)[(bit) >> 5] |= (1 << ((bit) & 0x1f)); \
3028 } while (0)
3029
3030 static inline void bnx2x_mcast_hdl_add_e1h(struct bnx2x *bp,
3031                                            struct bnx2x_mcast_obj *o,
3032                                            struct bnx2x_mcast_ramrod_params *p,
3033                                            u32 *mc_filter)
3034 {
3035         struct bnx2x_mcast_list_elem *mlist_pos;
3036         int bit;
3037
3038         list_for_each_entry(mlist_pos, &p->mcast_list, link) {
3039                 bit = bnx2x_mcast_bin_from_mac(mlist_pos->mac);
3040                 BNX2X_57711_SET_MC_FILTER(mc_filter, bit);
3041
3042                 DP(BNX2X_MSG_SP, "About to configure %pM mcast MAC, bin %d\n",
3043                    mlist_pos->mac, bit);
3044
3045                 /* bookkeeping... */
3046                 BIT_VEC64_SET_BIT(o->registry.aprox_match.vec,
3047                                   bit);
3048         }
3049 }
3050
3051 static inline void bnx2x_mcast_hdl_restore_e1h(struct bnx2x *bp,
3052         struct bnx2x_mcast_obj *o, struct bnx2x_mcast_ramrod_params *p,
3053         u32 *mc_filter)
3054 {
3055         int bit;
3056
3057         for (bit = bnx2x_mcast_get_next_bin(o, 0);
3058              bit >= 0;
3059              bit = bnx2x_mcast_get_next_bin(o, bit + 1)) {
3060                 BNX2X_57711_SET_MC_FILTER(mc_filter, bit);
3061                 DP(BNX2X_MSG_SP, "About to set bin %d\n", bit);
3062         }
3063 }
3064
3065 /* On 57711 we write the multicast MACs' approximate match
3066  * table by directly into the TSTORM's internal RAM. So we don't
3067  * really need to handle any tricks to make it work.
3068  */
3069 static int bnx2x_mcast_setup_e1h(struct bnx2x *bp,
3070                                  struct bnx2x_mcast_ramrod_params *p,
3071                                  enum bnx2x_mcast_cmd cmd)
3072 {
3073         int i;
3074         struct bnx2x_mcast_obj *o = p->mcast_obj;
3075         struct bnx2x_raw_obj *r = &o->raw;
3076
3077         /* If CLEAR_ONLY has been requested - clear the registry
3078          * and clear a pending bit.
3079          */
3080         if (!test_bit(RAMROD_DRV_CLR_ONLY, &p->ramrod_flags)) {
3081                 u32 mc_filter[MC_HASH_SIZE] = {0};
3082
3083                 /* Set the multicast filter bits before writing it into
3084                  * the internal memory.
3085                  */
3086                 switch (cmd) {
3087                 case BNX2X_MCAST_CMD_ADD:
3088                         bnx2x_mcast_hdl_add_e1h(bp, o, p, mc_filter);
3089                         break;
3090
3091                 case BNX2X_MCAST_CMD_DEL:
3092                         DP(BNX2X_MSG_SP,
3093                            "Invalidating multicast MACs configuration\n");
3094
3095                         /* clear the registry */
3096                         memset(o->registry.aprox_match.vec, 0,
3097                                sizeof(o->registry.aprox_match.vec));
3098                         break;
3099
3100                 case BNX2X_MCAST_CMD_RESTORE:
3101                         bnx2x_mcast_hdl_restore_e1h(bp, o, p, mc_filter);
3102                         break;
3103
3104                 default:
3105                         BNX2X_ERR("Unknown command: %d\n", cmd);
3106                         return -EINVAL;
3107                 }
3108
3109                 /* Set the mcast filter in the internal memory */
3110                 for (i = 0; i < MC_HASH_SIZE; i++)
3111                         REG_WR(bp, MC_HASH_OFFSET(bp, i), mc_filter[i]);
3112         } else
3113                 /* clear the registry */
3114                 memset(o->registry.aprox_match.vec, 0,
3115                        sizeof(o->registry.aprox_match.vec));
3116
3117         /* We are done */
3118         r->clear_pending(r);
3119
3120         return 0;
3121 }
3122
3123 static int bnx2x_mcast_validate_e1(struct bnx2x *bp,
3124                                    struct bnx2x_mcast_ramrod_params *p,
3125                                    enum bnx2x_mcast_cmd cmd)
3126 {
3127         struct bnx2x_mcast_obj *o = p->mcast_obj;
3128         int reg_sz = o->get_registry_size(o);
3129
3130         switch (cmd) {
3131         /* DEL command deletes all currently configured MACs */
3132         case BNX2X_MCAST_CMD_DEL:
3133                 o->set_registry_size(o, 0);
3134                 /* Don't break */
3135
3136         /* RESTORE command will restore the entire multicast configuration */
3137         case BNX2X_MCAST_CMD_RESTORE:
3138                 p->mcast_list_len = reg_sz;
3139                   DP(BNX2X_MSG_SP, "Command %d, p->mcast_list_len=%d\n",
3140                                    cmd, p->mcast_list_len);
3141                 break;
3142
3143         case BNX2X_MCAST_CMD_ADD:
3144         case BNX2X_MCAST_CMD_CONT:
3145                 /* Multicast MACs on 57710 are configured as unicast MACs and
3146                  * there is only a limited number of CAM entries for that
3147                  * matter.
3148                  */
3149                 if (p->mcast_list_len > o->max_cmd_len) {
3150                         BNX2X_ERR("Can't configure more than %d multicast MACs on 57710\n",
3151                                   o->max_cmd_len);
3152                         return -EINVAL;
3153                 }
3154                 /* Every configured MAC should be cleared if DEL command is
3155                  * called. Only the last ADD command is relevant as long as
3156                  * every ADD commands overrides the previous configuration.
3157                  */
3158                 DP(BNX2X_MSG_SP, "p->mcast_list_len=%d\n", p->mcast_list_len);
3159                 if (p->mcast_list_len > 0)
3160                         o->set_registry_size(o, p->mcast_list_len);
3161
3162                 break;
3163
3164         default:
3165                 BNX2X_ERR("Unknown command: %d\n", cmd);
3166                 return -EINVAL;
3167         }
3168
3169         /* We want to ensure that commands are executed one by one for 57710.
3170          * Therefore each none-empty command will consume o->max_cmd_len.
3171          */
3172         if (p->mcast_list_len)
3173                 o->total_pending_num += o->max_cmd_len;
3174
3175         return 0;
3176 }
3177
3178 static void bnx2x_mcast_revert_e1(struct bnx2x *bp,
3179                                       struct bnx2x_mcast_ramrod_params *p,
3180                                       int old_num_macs)
3181 {
3182         struct bnx2x_mcast_obj *o = p->mcast_obj;
3183
3184         o->set_registry_size(o, old_num_macs);
3185
3186         /* If current command hasn't been handled yet and we are
3187          * here means that it's meant to be dropped and we have to
3188          * update the number of outstanding MACs accordingly.
3189          */
3190         if (p->mcast_list_len)
3191                 o->total_pending_num -= o->max_cmd_len;
3192 }
3193
3194 static void bnx2x_mcast_set_one_rule_e1(struct bnx2x *bp,
3195                                         struct bnx2x_mcast_obj *o, int idx,
3196                                         union bnx2x_mcast_config_data *cfg_data,
3197                                         enum bnx2x_mcast_cmd cmd)
3198 {
3199         struct bnx2x_raw_obj *r = &o->raw;
3200         struct mac_configuration_cmd *data =
3201                 (struct mac_configuration_cmd *)(r->rdata);
3202
3203         /* copy mac */
3204         if ((cmd == BNX2X_MCAST_CMD_ADD) || (cmd == BNX2X_MCAST_CMD_RESTORE)) {
3205                 bnx2x_set_fw_mac_addr(&data->config_table[idx].msb_mac_addr,
3206                                       &data->config_table[idx].middle_mac_addr,
3207                                       &data->config_table[idx].lsb_mac_addr,
3208                                       cfg_data->mac);
3209
3210                 data->config_table[idx].vlan_id = 0;
3211                 data->config_table[idx].pf_id = r->func_id;
3212                 data->config_table[idx].clients_bit_vector =
3213                         cpu_to_le32(1 << r->cl_id);
3214
3215                 SET_FLAG(data->config_table[idx].flags,
3216                          MAC_CONFIGURATION_ENTRY_ACTION_TYPE,
3217                          T_ETH_MAC_COMMAND_SET);
3218         }
3219 }
3220
3221 /**
3222  * bnx2x_mcast_set_rdata_hdr_e1  - set header values in mac_configuration_cmd
3223  *
3224  * @bp:         device handle
3225  * @p:
3226  * @len:        number of rules to handle
3227  */
3228 static inline void bnx2x_mcast_set_rdata_hdr_e1(struct bnx2x *bp,
3229                                         struct bnx2x_mcast_ramrod_params *p,
3230                                         u8 len)
3231 {
3232         struct bnx2x_raw_obj *r = &p->mcast_obj->raw;
3233         struct mac_configuration_cmd *data =
3234                 (struct mac_configuration_cmd *)(r->rdata);
3235
3236         u8 offset = (CHIP_REV_IS_SLOW(bp) ?
3237                      BNX2X_MAX_EMUL_MULTI*(1 + r->func_id) :
3238                      BNX2X_MAX_MULTICAST*(1 + r->func_id));
3239
3240         data->hdr.offset = offset;
3241         data->hdr.client_id = cpu_to_le16(0xff);
3242         data->hdr.echo = cpu_to_le32((r->cid & BNX2X_SWCID_MASK) |
3243                                      (BNX2X_FILTER_MCAST_PENDING <<
3244                                       BNX2X_SWCID_SHIFT));
3245         data->hdr.length = len;
3246 }
3247
3248 /**
3249  * bnx2x_mcast_handle_restore_cmd_e1 - restore command for 57710
3250  *
3251  * @bp:         device handle
3252  * @o:
3253  * @start_idx:  index in the registry to start from
3254  * @rdata_idx:  index in the ramrod data to start from
3255  *
3256  * restore command for 57710 is like all other commands - always a stand alone
3257  * command - start_idx and rdata_idx will always be 0. This function will always
3258  * succeed.
3259  * returns -1 to comply with 57712 variant.
3260  */
3261 static inline int bnx2x_mcast_handle_restore_cmd_e1(
3262         struct bnx2x *bp, struct bnx2x_mcast_obj *o , int start_idx,
3263         int *rdata_idx)
3264 {
3265         struct bnx2x_mcast_mac_elem *elem;
3266         int i = 0;
3267         union bnx2x_mcast_config_data cfg_data = {NULL};
3268
3269         /* go through the registry and configure the MACs from it. */
3270         list_for_each_entry(elem, &o->registry.exact_match.macs, link) {
3271                 cfg_data.mac = &elem->mac[0];
3272                 o->set_one_rule(bp, o, i, &cfg_data, BNX2X_MCAST_CMD_RESTORE);
3273
3274                 i++;
3275
3276                   DP(BNX2X_MSG_SP, "About to configure %pM mcast MAC\n",
3277                      cfg_data.mac);
3278         }
3279
3280         *rdata_idx = i;
3281
3282         return -1;
3283 }
3284
3285 static inline int bnx2x_mcast_handle_pending_cmds_e1(
3286         struct bnx2x *bp, struct bnx2x_mcast_ramrod_params *p)
3287 {
3288         struct bnx2x_pending_mcast_cmd *cmd_pos;
3289         struct bnx2x_mcast_mac_elem *pmac_pos;
3290         struct bnx2x_mcast_obj *o = p->mcast_obj;
3291         union bnx2x_mcast_config_data cfg_data = {NULL};
3292         int cnt = 0;
3293
3294         /* If nothing to be done - return */
3295         if (list_empty(&o->pending_cmds_head))
3296                 return 0;
3297
3298         /* Handle the first command */
3299         cmd_pos = list_first_entry(&o->pending_cmds_head,
3300                                    struct bnx2x_pending_mcast_cmd, link);
3301
3302         switch (cmd_pos->type) {
3303         case BNX2X_MCAST_CMD_ADD:
3304                 list_for_each_entry(pmac_pos, &cmd_pos->data.macs_head, link) {
3305                         cfg_data.mac = &pmac_pos->mac[0];
3306                         o->set_one_rule(bp, o, cnt, &cfg_data, cmd_pos->type);
3307
3308                         cnt++;
3309
3310                         DP(BNX2X_MSG_SP, "About to configure %pM mcast MAC\n",
3311                            pmac_pos->mac);
3312                 }
3313                 break;
3314
3315         case BNX2X_MCAST_CMD_DEL:
3316                 cnt = cmd_pos->data.macs_num;
3317                 DP(BNX2X_MSG_SP, "About to delete %d multicast MACs\n", cnt);
3318                 break;
3319
3320         case BNX2X_MCAST_CMD_RESTORE:
3321                 o->hdl_restore(bp, o, 0, &cnt);
3322                 break;
3323
3324         default:
3325                 BNX2X_ERR("Unknown command: %d\n", cmd_pos->type);
3326                 return -EINVAL;
3327         }
3328
3329         list_del(&cmd_pos->link);
3330         kfree(cmd_pos);
3331
3332         return cnt;
3333 }
3334
3335 /**
3336  * bnx2x_get_fw_mac_addr - revert the bnx2x_set_fw_mac_addr().
3337  *
3338  * @fw_hi:
3339  * @fw_mid:
3340  * @fw_lo:
3341  * @mac:
3342  */
3343 static inline void bnx2x_get_fw_mac_addr(__le16 *fw_hi, __le16 *fw_mid,
3344                                          __le16 *fw_lo, u8 *mac)
3345 {
3346         mac[1] = ((u8 *)fw_hi)[0];
3347         mac[0] = ((u8 *)fw_hi)[1];
3348         mac[3] = ((u8 *)fw_mid)[0];
3349         mac[2] = ((u8 *)fw_mid)[1];
3350         mac[5] = ((u8 *)fw_lo)[0];
3351         mac[4] = ((u8 *)fw_lo)[1];
3352 }
3353
3354 /**
3355  * bnx2x_mcast_refresh_registry_e1 -
3356  *
3357  * @bp:         device handle
3358  * @cnt:
3359  *
3360  * Check the ramrod data first entry flag to see if it's a DELETE or ADD command
3361  * and update the registry correspondingly: if ADD - allocate a memory and add
3362  * the entries to the registry (list), if DELETE - clear the registry and free
3363  * the memory.
3364  */
3365 static inline int bnx2x_mcast_refresh_registry_e1(struct bnx2x *bp,
3366                                                   struct bnx2x_mcast_obj *o)
3367 {
3368         struct bnx2x_raw_obj *raw = &o->raw;
3369         struct bnx2x_mcast_mac_elem *elem;
3370         struct mac_configuration_cmd *data =
3371                         (struct mac_configuration_cmd *)(raw->rdata);
3372
3373         /* If first entry contains a SET bit - the command was ADD,
3374          * otherwise - DEL_ALL
3375          */
3376         if (GET_FLAG(data->config_table[0].flags,
3377                         MAC_CONFIGURATION_ENTRY_ACTION_TYPE)) {
3378                 int i, len = data->hdr.length;
3379
3380                 /* Break if it was a RESTORE command */
3381                 if (!list_empty(&o->registry.exact_match.macs))
3382                         return 0;
3383
3384                 elem = kcalloc(len, sizeof(*elem), GFP_ATOMIC);
3385                 if (!elem) {
3386                         BNX2X_ERR("Failed to allocate registry memory\n");
3387                         return -ENOMEM;
3388                 }
3389
3390                 for (i = 0; i < len; i++, elem++) {
3391                         bnx2x_get_fw_mac_addr(
3392                                 &data->config_table[i].msb_mac_addr,
3393                                 &data->config_table[i].middle_mac_addr,
3394                                 &data->config_table[i].lsb_mac_addr,
3395                                 elem->mac);
3396                         DP(BNX2X_MSG_SP, "Adding registry entry for [%pM]\n",
3397                            elem->mac);
3398                         list_add_tail(&elem->link,
3399                                       &o->registry.exact_match.macs);
3400                 }
3401         } else {
3402                 elem = list_first_entry(&o->registry.exact_match.macs,
3403                                         struct bnx2x_mcast_mac_elem, link);
3404                 DP(BNX2X_MSG_SP, "Deleting a registry\n");
3405                 kfree(elem);
3406                 INIT_LIST_HEAD(&o->registry.exact_match.macs);
3407         }
3408
3409         return 0;
3410 }
3411
3412 static int bnx2x_mcast_setup_e1(struct bnx2x *bp,
3413                                 struct bnx2x_mcast_ramrod_params *p,
3414                                 enum bnx2x_mcast_cmd cmd)
3415 {
3416         struct bnx2x_mcast_obj *o = p->mcast_obj;
3417         struct bnx2x_raw_obj *raw = &o->raw;
3418         struct mac_configuration_cmd *data =
3419                 (struct mac_configuration_cmd *)(raw->rdata);
3420         int cnt = 0, i, rc;
3421
3422         /* Reset the ramrod data buffer */
3423         memset(data, 0, sizeof(*data));
3424
3425         /* First set all entries as invalid */
3426         for (i = 0; i < o->max_cmd_len ; i++)
3427                 SET_FLAG(data->config_table[i].flags,
3428                          MAC_CONFIGURATION_ENTRY_ACTION_TYPE,
3429                          T_ETH_MAC_COMMAND_INVALIDATE);
3430
3431         /* Handle pending commands first */
3432         cnt = bnx2x_mcast_handle_pending_cmds_e1(bp, p);
3433
3434         /* If there are no more pending commands - clear SCHEDULED state */
3435         if (list_empty(&o->pending_cmds_head))
3436                 o->clear_sched(o);
3437
3438         /* The below may be true iff there were no pending commands */
3439         if (!cnt)
3440                 cnt = bnx2x_mcast_handle_current_cmd(bp, p, cmd, 0);
3441
3442         /* For 57710 every command has o->max_cmd_len length to ensure that
3443          * commands are done one at a time.
3444          */
3445         o->total_pending_num -= o->max_cmd_len;
3446
3447         /* send a ramrod */
3448
3449         WARN_ON(cnt > o->max_cmd_len);
3450
3451         /* Set ramrod header (in particular, a number of entries to update) */
3452         bnx2x_mcast_set_rdata_hdr_e1(bp, p, (u8)cnt);
3453
3454         /* update a registry: we need the registry contents to be always up
3455          * to date in order to be able to execute a RESTORE opcode. Here
3456          * we use the fact that for 57710 we sent one command at a time
3457          * hence we may take the registry update out of the command handling
3458          * and do it in a simpler way here.
3459          */
3460         rc = bnx2x_mcast_refresh_registry_e1(bp, o);
3461         if (rc)
3462                 return rc;
3463
3464         /* If CLEAR_ONLY was requested - don't send a ramrod and clear
3465          * RAMROD_PENDING status immediately.
3466          */
3467         if (test_bit(RAMROD_DRV_CLR_ONLY, &p->ramrod_flags)) {
3468                 raw->clear_pending(raw);
3469                 return 0;
3470         } else {
3471                 /* No need for an explicit memory barrier here as long as we
3472                  * ensure the ordering of writing to the SPQ element
3473                  * and updating of the SPQ producer which involves a memory
3474                  * read. If the memory read is removed we will have to put a
3475                  * full memory barrier there (inside bnx2x_sp_post()).
3476                  */
3477
3478                 /* Send a ramrod */
3479                 rc = bnx2x_sp_post(bp, RAMROD_CMD_ID_ETH_SET_MAC, raw->cid,
3480                                    U64_HI(raw->rdata_mapping),
3481                                    U64_LO(raw->rdata_mapping),
3482                                    ETH_CONNECTION_TYPE);
3483                 if (rc)
3484                         return rc;
3485
3486                 /* Ramrod completion is pending */
3487                 return 1;
3488         }
3489 }
3490
3491 static int bnx2x_mcast_get_registry_size_exact(struct bnx2x_mcast_obj *o)
3492 {
3493         return o->registry.exact_match.num_macs_set;
3494 }
3495
3496 static int bnx2x_mcast_get_registry_size_aprox(struct bnx2x_mcast_obj *o)
3497 {
3498         return o->registry.aprox_match.num_bins_set;
3499 }
3500
3501 static void bnx2x_mcast_set_registry_size_exact(struct bnx2x_mcast_obj *o,
3502                                                 int n)
3503 {
3504         o->registry.exact_match.num_macs_set = n;
3505 }
3506
3507 static void bnx2x_mcast_set_registry_size_aprox(struct bnx2x_mcast_obj *o,
3508                                                 int n)
3509 {
3510         o->registry.aprox_match.num_bins_set = n;
3511 }
3512
3513 int bnx2x_config_mcast(struct bnx2x *bp,
3514                        struct bnx2x_mcast_ramrod_params *p,
3515                        enum bnx2x_mcast_cmd cmd)
3516 {
3517         struct bnx2x_mcast_obj *o = p->mcast_obj;
3518         struct bnx2x_raw_obj *r = &o->raw;
3519         int rc = 0, old_reg_size;
3520
3521         /* This is needed to recover number of currently configured mcast macs
3522          * in case of failure.
3523          */
3524         old_reg_size = o->get_registry_size(o);
3525
3526         /* Do some calculations and checks */
3527         rc = o->validate(bp, p, cmd);
3528         if (rc)
3529                 return rc;
3530
3531         /* Return if there is no work to do */
3532         if ((!p->mcast_list_len) && (!o->check_sched(o)))
3533                 return 0;
3534
3535         DP(BNX2X_MSG_SP, "o->total_pending_num=%d p->mcast_list_len=%d o->max_cmd_len=%d\n",
3536            o->total_pending_num, p->mcast_list_len, o->max_cmd_len);
3537
3538         /* Enqueue the current command to the pending list if we can't complete
3539          * it in the current iteration
3540          */
3541         if (r->check_pending(r) ||
3542             ((o->max_cmd_len > 0) && (o->total_pending_num > o->max_cmd_len))) {
3543                 rc = o->enqueue_cmd(bp, p->mcast_obj, p, cmd);
3544                 if (rc < 0)
3545                         goto error_exit1;
3546
3547                 /* As long as the current command is in a command list we
3548                  * don't need to handle it separately.
3549                  */
3550                 p->mcast_list_len = 0;
3551         }
3552
3553         if (!r->check_pending(r)) {
3554
3555                 /* Set 'pending' state */
3556                 r->set_pending(r);
3557
3558                 /* Configure the new classification in the chip */
3559                 rc = o->config_mcast(bp, p, cmd);
3560                 if (rc < 0)
3561                         goto error_exit2;
3562
3563                 /* Wait for a ramrod completion if was requested */
3564                 if (test_bit(RAMROD_COMP_WAIT, &p->ramrod_flags))
3565                         rc = o->wait_comp(bp, o);
3566         }
3567
3568         return rc;
3569
3570 error_exit2:
3571         r->clear_pending(r);
3572
3573 error_exit1:
3574         o->revert(bp, p, old_reg_size);
3575
3576         return rc;
3577 }
3578
3579 static void bnx2x_mcast_clear_sched(struct bnx2x_mcast_obj *o)
3580 {
3581         smp_mb__before_atomic();
3582         clear_bit(o->sched_state, o->raw.pstate);
3583         smp_mb__after_atomic();
3584 }
3585
3586 static void bnx2x_mcast_set_sched(struct bnx2x_mcast_obj *o)
3587 {
3588         smp_mb__before_atomic();
3589         set_bit(o->sched_state, o->raw.pstate);
3590         smp_mb__after_atomic();
3591 }
3592
3593 static bool bnx2x_mcast_check_sched(struct bnx2x_mcast_obj *o)
3594 {
3595         return !!test_bit(o->sched_state, o->raw.pstate);
3596 }
3597
3598 static bool bnx2x_mcast_check_pending(struct bnx2x_mcast_obj *o)
3599 {
3600         return o->raw.check_pending(&o->raw) || o->check_sched(o);
3601 }
3602
3603 void bnx2x_init_mcast_obj(struct bnx2x *bp,
3604                           struct bnx2x_mcast_obj *mcast_obj,
3605                           u8 mcast_cl_id, u32 mcast_cid, u8 func_id,
3606                           u8 engine_id, void *rdata, dma_addr_t rdata_mapping,
3607                           int state, unsigned long *pstate, bnx2x_obj_type type)
3608 {
3609         memset(mcast_obj, 0, sizeof(*mcast_obj));
3610
3611         bnx2x_init_raw_obj(&mcast_obj->raw, mcast_cl_id, mcast_cid, func_id,
3612                            rdata, rdata_mapping, state, pstate, type);
3613
3614         mcast_obj->engine_id = engine_id;
3615
3616         INIT_LIST_HEAD(&mcast_obj->pending_cmds_head);
3617
3618         mcast_obj->sched_state = BNX2X_FILTER_MCAST_SCHED;
3619         mcast_obj->check_sched = bnx2x_mcast_check_sched;
3620         mcast_obj->set_sched = bnx2x_mcast_set_sched;
3621         mcast_obj->clear_sched = bnx2x_mcast_clear_sched;
3622
3623         if (CHIP_IS_E1(bp)) {
3624                 mcast_obj->config_mcast      = bnx2x_mcast_setup_e1;
3625                 mcast_obj->enqueue_cmd       = bnx2x_mcast_enqueue_cmd;
3626                 mcast_obj->hdl_restore       =
3627                         bnx2x_mcast_handle_restore_cmd_e1;
3628                 mcast_obj->check_pending     = bnx2x_mcast_check_pending;
3629
3630                 if (CHIP_REV_IS_SLOW(bp))
3631                         mcast_obj->max_cmd_len = BNX2X_MAX_EMUL_MULTI;
3632                 else
3633                         mcast_obj->max_cmd_len = BNX2X_MAX_MULTICAST;
3634
3635                 mcast_obj->wait_comp         = bnx2x_mcast_wait;
3636                 mcast_obj->set_one_rule      = bnx2x_mcast_set_one_rule_e1;
3637                 mcast_obj->validate          = bnx2x_mcast_validate_e1;
3638                 mcast_obj->revert            = bnx2x_mcast_revert_e1;
3639                 mcast_obj->get_registry_size =
3640                         bnx2x_mcast_get_registry_size_exact;
3641                 mcast_obj->set_registry_size =
3642                         bnx2x_mcast_set_registry_size_exact;
3643
3644                 /* 57710 is the only chip that uses the exact match for mcast
3645                  * at the moment.
3646                  */
3647                 INIT_LIST_HEAD(&mcast_obj->registry.exact_match.macs);
3648
3649         } else if (CHIP_IS_E1H(bp)) {
3650                 mcast_obj->config_mcast  = bnx2x_mcast_setup_e1h;
3651                 mcast_obj->enqueue_cmd   = NULL;
3652                 mcast_obj->hdl_restore   = NULL;
3653                 mcast_obj->check_pending = bnx2x_mcast_check_pending;
3654
3655                 /* 57711 doesn't send a ramrod, so it has unlimited credit
3656                  * for one command.
3657                  */
3658                 mcast_obj->max_cmd_len       = -1;
3659                 mcast_obj->wait_comp         = bnx2x_mcast_wait;
3660                 mcast_obj->set_one_rule      = NULL;
3661                 mcast_obj->validate          = bnx2x_mcast_validate_e1h;
3662                 mcast_obj->revert            = bnx2x_mcast_revert_e1h;
3663                 mcast_obj->get_registry_size =
3664                         bnx2x_mcast_get_registry_size_aprox;
3665                 mcast_obj->set_registry_size =
3666                         bnx2x_mcast_set_registry_size_aprox;
3667         } else {
3668                 mcast_obj->config_mcast      = bnx2x_mcast_setup_e2;
3669                 mcast_obj->enqueue_cmd       = bnx2x_mcast_enqueue_cmd;
3670                 mcast_obj->hdl_restore       =
3671                         bnx2x_mcast_handle_restore_cmd_e2;
3672                 mcast_obj->check_pending     = bnx2x_mcast_check_pending;
3673                 /* TODO: There should be a proper HSI define for this number!!!
3674                  */
3675                 mcast_obj->max_cmd_len       = 16;
3676                 mcast_obj->wait_comp         = bnx2x_mcast_wait;
3677                 mcast_obj->set_one_rule      = bnx2x_mcast_set_one_rule_e2;
3678                 mcast_obj->validate          = bnx2x_mcast_validate_e2;
3679                 mcast_obj->revert            = bnx2x_mcast_revert_e2;
3680                 mcast_obj->get_registry_size =
3681                         bnx2x_mcast_get_registry_size_aprox;
3682                 mcast_obj->set_registry_size =
3683                         bnx2x_mcast_set_registry_size_aprox;
3684         }
3685 }
3686
3687 /*************************** Credit handling **********************************/
3688
3689 /**
3690  * atomic_add_ifless - add if the result is less than a given value.
3691  *
3692  * @v:  pointer of type atomic_t
3693  * @a:  the amount to add to v...
3694  * @u:  ...if (v + a) is less than u.
3695  *
3696  * returns true if (v + a) was less than u, and false otherwise.
3697  *
3698  */
3699 static inline bool __atomic_add_ifless(atomic_t *v, int a, int u)
3700 {
3701         int c, old;
3702
3703         c = atomic_read(v);
3704         for (;;) {
3705                 if (unlikely(c + a >= u))
3706                         return false;
3707
3708                 old = atomic_cmpxchg((v), c, c + a);
3709                 if (likely(old == c))
3710                         break;
3711                 c = old;
3712         }
3713
3714         return true;
3715 }
3716
3717 /**
3718  * atomic_dec_ifmoe - dec if the result is more or equal than a given value.
3719  *
3720  * @v:  pointer of type atomic_t
3721  * @a:  the amount to dec from v...
3722  * @u:  ...if (v - a) is more or equal than u.
3723  *
3724  * returns true if (v - a) was more or equal than u, and false
3725  * otherwise.
3726  */
3727 static inline bool __atomic_dec_ifmoe(atomic_t *v, int a, int u)
3728 {
3729         int c, old;
3730
3731         c = atomic_read(v);
3732         for (;;) {
3733                 if (unlikely(c - a < u))
3734                         return false;
3735
3736                 old = atomic_cmpxchg((v), c, c - a);
3737                 if (likely(old == c))
3738                         break;
3739                 c = old;
3740         }
3741
3742         return true;
3743 }
3744
3745 static bool bnx2x_credit_pool_get(struct bnx2x_credit_pool_obj *o, int cnt)
3746 {
3747         bool rc;
3748
3749         smp_mb();
3750         rc = __atomic_dec_ifmoe(&o->credit, cnt, 0);
3751         smp_mb();
3752
3753         return rc;
3754 }
3755
3756 static bool bnx2x_credit_pool_put(struct bnx2x_credit_pool_obj *o, int cnt)
3757 {
3758         bool rc;
3759
3760         smp_mb();
3761
3762         /* Don't let to refill if credit + cnt > pool_sz */
3763         rc = __atomic_add_ifless(&o->credit, cnt, o->pool_sz + 1);
3764
3765         smp_mb();
3766
3767         return rc;
3768 }
3769
3770 static int bnx2x_credit_pool_check(struct bnx2x_credit_pool_obj *o)
3771 {
3772         int cur_credit;
3773
3774         smp_mb();
3775         cur_credit = atomic_read(&o->credit);
3776
3777         return cur_credit;
3778 }
3779
3780 static bool bnx2x_credit_pool_always_true(struct bnx2x_credit_pool_obj *o,
3781                                           int cnt)
3782 {
3783         return true;
3784 }
3785
3786 static bool bnx2x_credit_pool_get_entry(
3787         struct bnx2x_credit_pool_obj *o,
3788         int *offset)
3789 {
3790         int idx, vec, i;
3791
3792         *offset = -1;
3793
3794         /* Find "internal cam-offset" then add to base for this object... */
3795         for (vec = 0; vec < BNX2X_POOL_VEC_SIZE; vec++) {
3796
3797                 /* Skip the current vector if there are no free entries in it */
3798                 if (!o->pool_mirror[vec])
3799                         continue;
3800
3801                 /* If we've got here we are going to find a free entry */
3802                 for (idx = vec * BIT_VEC64_ELEM_SZ, i = 0;
3803                       i < BIT_VEC64_ELEM_SZ; idx++, i++)
3804
3805                         if (BIT_VEC64_TEST_BIT(o->pool_mirror, idx)) {
3806                                 /* Got one!! */
3807                                 BIT_VEC64_CLEAR_BIT(o->pool_mirror, idx);
3808                                 *offset = o->base_pool_offset + idx;
3809                                 return true;
3810                         }
3811         }
3812
3813         return false;
3814 }
3815
3816 static bool bnx2x_credit_pool_put_entry(
3817         struct bnx2x_credit_pool_obj *o,
3818         int offset)
3819 {
3820         if (offset < o->base_pool_offset)
3821                 return false;
3822
3823         offset -= o->base_pool_offset;
3824
3825         if (offset >= o->pool_sz)
3826                 return false;
3827
3828         /* Return the entry to the pool */
3829         BIT_VEC64_SET_BIT(o->pool_mirror, offset);
3830
3831         return true;
3832 }
3833
3834 static bool bnx2x_credit_pool_put_entry_always_true(
3835         struct bnx2x_credit_pool_obj *o,
3836         int offset)
3837 {
3838         return true;
3839 }
3840
3841 static bool bnx2x_credit_pool_get_entry_always_true(
3842         struct bnx2x_credit_pool_obj *o,
3843         int *offset)
3844 {
3845         *offset = -1;
3846         return true;
3847 }
3848 /**
3849  * bnx2x_init_credit_pool - initialize credit pool internals.
3850  *
3851  * @p:
3852  * @base:       Base entry in the CAM to use.
3853  * @credit:     pool size.
3854  *
3855  * If base is negative no CAM entries handling will be performed.
3856  * If credit is negative pool operations will always succeed (unlimited pool).
3857  *
3858  */
3859 static inline void bnx2x_init_credit_pool(struct bnx2x_credit_pool_obj *p,
3860                                           int base, int credit)
3861 {
3862         /* Zero the object first */
3863         memset(p, 0, sizeof(*p));
3864
3865         /* Set the table to all 1s */
3866         memset(&p->pool_mirror, 0xff, sizeof(p->pool_mirror));
3867
3868         /* Init a pool as full */
3869         atomic_set(&p->credit, credit);
3870
3871         /* The total poll size */
3872         p->pool_sz = credit;
3873
3874         p->base_pool_offset = base;
3875
3876         /* Commit the change */
3877         smp_mb();
3878
3879         p->check = bnx2x_credit_pool_check;
3880
3881         /* if pool credit is negative - disable the checks */
3882         if (credit >= 0) {
3883                 p->put      = bnx2x_credit_pool_put;
3884                 p->get      = bnx2x_credit_pool_get;
3885                 p->put_entry = bnx2x_credit_pool_put_entry;
3886                 p->get_entry = bnx2x_credit_pool_get_entry;
3887         } else {
3888                 p->put      = bnx2x_credit_pool_always_true;
3889                 p->get      = bnx2x_credit_pool_always_true;
3890                 p->put_entry = bnx2x_credit_pool_put_entry_always_true;
3891                 p->get_entry = bnx2x_credit_pool_get_entry_always_true;
3892         }
3893
3894         /* If base is negative - disable entries handling */
3895         if (base < 0) {
3896                 p->put_entry = bnx2x_credit_pool_put_entry_always_true;
3897                 p->get_entry = bnx2x_credit_pool_get_entry_always_true;
3898         }
3899 }
3900
3901 void bnx2x_init_mac_credit_pool(struct bnx2x *bp,
3902                                 struct bnx2x_credit_pool_obj *p, u8 func_id,
3903                                 u8 func_num)
3904 {
3905 /* TODO: this will be defined in consts as well... */
3906 #define BNX2X_CAM_SIZE_EMUL 5
3907
3908         int cam_sz;
3909
3910         if (CHIP_IS_E1(bp)) {
3911                 /* In E1, Multicast is saved in cam... */
3912                 if (!CHIP_REV_IS_SLOW(bp))
3913                         cam_sz = (MAX_MAC_CREDIT_E1 / 2) - BNX2X_MAX_MULTICAST;
3914                 else
3915                         cam_sz = BNX2X_CAM_SIZE_EMUL - BNX2X_MAX_EMUL_MULTI;
3916
3917                 bnx2x_init_credit_pool(p, func_id * cam_sz, cam_sz);
3918
3919         } else if (CHIP_IS_E1H(bp)) {
3920                 /* CAM credit is equaly divided between all active functions
3921                  * on the PORT!.
3922                  */
3923                 if ((func_num > 0)) {
3924                         if (!CHIP_REV_IS_SLOW(bp))
3925                                 cam_sz = (MAX_MAC_CREDIT_E1H / (2*func_num));
3926                         else
3927                                 cam_sz = BNX2X_CAM_SIZE_EMUL;
3928                         bnx2x_init_credit_pool(p, func_id * cam_sz, cam_sz);
3929                 } else {
3930                         /* this should never happen! Block MAC operations. */
3931                         bnx2x_init_credit_pool(p, 0, 0);
3932                 }
3933
3934         } else {
3935
3936                 /* CAM credit is equaly divided between all active functions
3937                  * on the PATH.
3938                  */
3939                 if ((func_num > 0)) {
3940                         if (!CHIP_REV_IS_SLOW(bp))
3941                                 cam_sz = (MAX_MAC_CREDIT_E2 / func_num);
3942                         else
3943                                 cam_sz = BNX2X_CAM_SIZE_EMUL;
3944
3945                         /* No need for CAM entries handling for 57712 and
3946                          * newer.
3947                          */
3948                         bnx2x_init_credit_pool(p, -1, cam_sz);
3949                 } else {
3950                         /* this should never happen! Block MAC operations. */
3951                         bnx2x_init_credit_pool(p, 0, 0);
3952                 }
3953         }
3954 }
3955
3956 void bnx2x_init_vlan_credit_pool(struct bnx2x *bp,
3957                                  struct bnx2x_credit_pool_obj *p,
3958                                  u8 func_id,
3959                                  u8 func_num)
3960 {
3961         if (CHIP_IS_E1x(bp)) {
3962                 /* There is no VLAN credit in HW on 57710 and 57711 only
3963                  * MAC / MAC-VLAN can be set
3964                  */
3965                 bnx2x_init_credit_pool(p, 0, -1);
3966         } else {
3967                 /* CAM credit is equally divided between all active functions
3968                  * on the PATH.
3969                  */
3970                 if (func_num > 0) {
3971                         int credit = MAX_VLAN_CREDIT_E2 / func_num;
3972                         bnx2x_init_credit_pool(p, func_id * credit, credit);
3973                 } else
3974                         /* this should never happen! Block VLAN operations. */
3975                         bnx2x_init_credit_pool(p, 0, 0);
3976         }
3977 }
3978
3979 /****************** RSS Configuration ******************/
3980 /**
3981  * bnx2x_debug_print_ind_table - prints the indirection table configuration.
3982  *
3983  * @bp:         driver handle
3984  * @p:          pointer to rss configuration
3985  *
3986  * Prints it when NETIF_MSG_IFUP debug level is configured.
3987  */
3988 static inline void bnx2x_debug_print_ind_table(struct bnx2x *bp,
3989                                         struct bnx2x_config_rss_params *p)
3990 {
3991         int i;
3992
3993         DP(BNX2X_MSG_SP, "Setting indirection table to:\n");
3994         DP(BNX2X_MSG_SP, "0x0000: ");
3995         for (i = 0; i < T_ETH_INDIRECTION_TABLE_SIZE; i++) {
3996                 DP_CONT(BNX2X_MSG_SP, "0x%02x ", p->ind_table[i]);
3997
3998                 /* Print 4 bytes in a line */
3999                 if ((i + 1 < T_ETH_INDIRECTION_TABLE_SIZE) &&
4000                     (((i + 1) & 0x3) == 0)) {
4001                         DP_CONT(BNX2X_MSG_SP, "\n");
4002                         DP(BNX2X_MSG_SP, "0x%04x: ", i + 1);
4003                 }
4004         }
4005
4006         DP_CONT(BNX2X_MSG_SP, "\n");
4007 }
4008
4009 /**
4010  * bnx2x_setup_rss - configure RSS
4011  *
4012  * @bp:         device handle
4013  * @p:          rss configuration
4014  *
4015  * sends on UPDATE ramrod for that matter.
4016  */
4017 static int bnx2x_setup_rss(struct bnx2x *bp,
4018                            struct bnx2x_config_rss_params *p)
4019 {
4020         struct bnx2x_rss_config_obj *o = p->rss_obj;
4021         struct bnx2x_raw_obj *r = &o->raw;
4022         struct eth_rss_update_ramrod_data *data =
4023                 (struct eth_rss_update_ramrod_data *)(r->rdata);
4024         u16 caps = 0;
4025         u8 rss_mode = 0;
4026         int rc;
4027
4028         memset(data, 0, sizeof(*data));
4029
4030         DP(BNX2X_MSG_SP, "Configuring RSS\n");
4031
4032         /* Set an echo field */
4033         data->echo = cpu_to_le32((r->cid & BNX2X_SWCID_MASK) |
4034                                  (r->state << BNX2X_SWCID_SHIFT));
4035
4036         /* RSS mode */
4037         if (test_bit(BNX2X_RSS_MODE_DISABLED, &p->rss_flags))
4038                 rss_mode = ETH_RSS_MODE_DISABLED;
4039         else if (test_bit(BNX2X_RSS_MODE_REGULAR, &p->rss_flags))
4040                 rss_mode = ETH_RSS_MODE_REGULAR;
4041
4042         data->rss_mode = rss_mode;
4043
4044         DP(BNX2X_MSG_SP, "rss_mode=%d\n", rss_mode);
4045
4046         /* RSS capabilities */
4047         if (test_bit(BNX2X_RSS_IPV4, &p->rss_flags))
4048                 caps |= ETH_RSS_UPDATE_RAMROD_DATA_IPV4_CAPABILITY;
4049
4050         if (test_bit(BNX2X_RSS_IPV4_TCP, &p->rss_flags))
4051                 caps |= ETH_RSS_UPDATE_RAMROD_DATA_IPV4_TCP_CAPABILITY;
4052
4053         if (test_bit(BNX2X_RSS_IPV4_UDP, &p->rss_flags))
4054                 caps |= ETH_RSS_UPDATE_RAMROD_DATA_IPV4_UDP_CAPABILITY;
4055
4056         if (test_bit(BNX2X_RSS_IPV6, &p->rss_flags))
4057                 caps |= ETH_RSS_UPDATE_RAMROD_DATA_IPV6_CAPABILITY;
4058
4059         if (test_bit(BNX2X_RSS_IPV6_TCP, &p->rss_flags))
4060                 caps |= ETH_RSS_UPDATE_RAMROD_DATA_IPV6_TCP_CAPABILITY;
4061
4062         if (test_bit(BNX2X_RSS_IPV6_UDP, &p->rss_flags))
4063                 caps |= ETH_RSS_UPDATE_RAMROD_DATA_IPV6_UDP_CAPABILITY;
4064
4065         if (test_bit(BNX2X_RSS_IPV4_VXLAN, &p->rss_flags))
4066                 caps |= ETH_RSS_UPDATE_RAMROD_DATA_IPV4_VXLAN_CAPABILITY;
4067
4068         if (test_bit(BNX2X_RSS_IPV6_VXLAN, &p->rss_flags))
4069                 caps |= ETH_RSS_UPDATE_RAMROD_DATA_IPV6_VXLAN_CAPABILITY;
4070
4071         if (test_bit(BNX2X_RSS_TUNN_INNER_HDRS, &p->rss_flags))
4072                 caps |= ETH_RSS_UPDATE_RAMROD_DATA_TUNN_INNER_HDRS_CAPABILITY;
4073
4074         /* RSS keys */
4075         if (test_bit(BNX2X_RSS_SET_SRCH, &p->rss_flags)) {
4076                 memcpy(&data->rss_key[0], &p->rss_key[0],
4077                        sizeof(data->rss_key));
4078                 caps |= ETH_RSS_UPDATE_RAMROD_DATA_UPDATE_RSS_KEY;
4079         }
4080
4081         data->capabilities = cpu_to_le16(caps);
4082
4083         /* Hashing mask */
4084         data->rss_result_mask = p->rss_result_mask;
4085
4086         /* RSS engine ID */
4087         data->rss_engine_id = o->engine_id;
4088
4089         DP(BNX2X_MSG_SP, "rss_engine_id=%d\n", data->rss_engine_id);
4090
4091         /* Indirection table */
4092         memcpy(data->indirection_table, p->ind_table,
4093                   T_ETH_INDIRECTION_TABLE_SIZE);
4094
4095         /* Remember the last configuration */
4096         memcpy(o->ind_table, p->ind_table, T_ETH_INDIRECTION_TABLE_SIZE);
4097
4098         /* Print the indirection table */
4099         if (netif_msg_ifup(bp))
4100                 bnx2x_debug_print_ind_table(bp, p);
4101
4102         /* No need for an explicit memory barrier here as long as we
4103          * ensure the ordering of writing to the SPQ element
4104          * and updating of the SPQ producer which involves a memory
4105          * read. If the memory read is removed we will have to put a
4106          * full memory barrier there (inside bnx2x_sp_post()).
4107          */
4108
4109         /* Send a ramrod */
4110         rc = bnx2x_sp_post(bp, RAMROD_CMD_ID_ETH_RSS_UPDATE, r->cid,
4111                            U64_HI(r->rdata_mapping),
4112                            U64_LO(r->rdata_mapping),
4113                            ETH_CONNECTION_TYPE);
4114
4115         if (rc < 0)
4116                 return rc;
4117
4118         return 1;
4119 }
4120
4121 void bnx2x_get_rss_ind_table(struct bnx2x_rss_config_obj *rss_obj,
4122                              u8 *ind_table)
4123 {
4124         memcpy(ind_table, rss_obj->ind_table, sizeof(rss_obj->ind_table));
4125 }
4126
4127 int bnx2x_config_rss(struct bnx2x *bp,
4128                      struct bnx2x_config_rss_params *p)
4129 {
4130         int rc;
4131         struct bnx2x_rss_config_obj *o = p->rss_obj;
4132         struct bnx2x_raw_obj *r = &o->raw;
4133
4134         /* Do nothing if only driver cleanup was requested */
4135         if (test_bit(RAMROD_DRV_CLR_ONLY, &p->ramrod_flags)) {
4136                 DP(BNX2X_MSG_SP, "Not configuring RSS ramrod_flags=%lx\n",
4137                    p->ramrod_flags);
4138                 return 0;
4139         }
4140
4141         r->set_pending(r);
4142
4143         rc = o->config_rss(bp, p);
4144         if (rc < 0) {
4145                 r->clear_pending(r);
4146                 return rc;
4147         }
4148
4149         if (test_bit(RAMROD_COMP_WAIT, &p->ramrod_flags))
4150                 rc = r->wait_comp(bp, r);
4151
4152         return rc;
4153 }
4154
4155 void bnx2x_init_rss_config_obj(struct bnx2x *bp,
4156                                struct bnx2x_rss_config_obj *rss_obj,
4157                                u8 cl_id, u32 cid, u8 func_id, u8 engine_id,
4158                                void *rdata, dma_addr_t rdata_mapping,
4159                                int state, unsigned long *pstate,
4160                                bnx2x_obj_type type)
4161 {
4162         bnx2x_init_raw_obj(&rss_obj->raw, cl_id, cid, func_id, rdata,
4163                            rdata_mapping, state, pstate, type);
4164
4165         rss_obj->engine_id  = engine_id;
4166         rss_obj->config_rss = bnx2x_setup_rss;
4167 }
4168
4169 /********************** Queue state object ***********************************/
4170
4171 /**
4172  * bnx2x_queue_state_change - perform Queue state change transition
4173  *
4174  * @bp:         device handle
4175  * @params:     parameters to perform the transition
4176  *
4177  * returns 0 in case of successfully completed transition, negative error
4178  * code in case of failure, positive (EBUSY) value if there is a completion
4179  * to that is still pending (possible only if RAMROD_COMP_WAIT is
4180  * not set in params->ramrod_flags for asynchronous commands).
4181  *
4182  */
4183 int bnx2x_queue_state_change(struct bnx2x *bp,
4184                              struct bnx2x_queue_state_params *params)
4185 {
4186         struct bnx2x_queue_sp_obj *o = params->q_obj;
4187         int rc, pending_bit;
4188         unsigned long *pending = &o->pending;
4189
4190         /* Check that the requested transition is legal */
4191         rc = o->check_transition(bp, o, params);
4192         if (rc) {
4193                 BNX2X_ERR("check transition returned an error. rc %d\n", rc);
4194                 return -EINVAL;
4195         }
4196
4197         /* Set "pending" bit */
4198         DP(BNX2X_MSG_SP, "pending bit was=%lx\n", o->pending);
4199         pending_bit = o->set_pending(o, params);
4200         DP(BNX2X_MSG_SP, "pending bit now=%lx\n", o->pending);
4201
4202         /* Don't send a command if only driver cleanup was requested */
4203         if (test_bit(RAMROD_DRV_CLR_ONLY, &params->ramrod_flags))
4204                 o->complete_cmd(bp, o, pending_bit);
4205         else {
4206                 /* Send a ramrod */
4207                 rc = o->send_cmd(bp, params);
4208                 if (rc) {
4209                         o->next_state = BNX2X_Q_STATE_MAX;
4210                         clear_bit(pending_bit, pending);
4211                         smp_mb__after_atomic();
4212                         return rc;
4213                 }
4214
4215                 if (test_bit(RAMROD_COMP_WAIT, &params->ramrod_flags)) {
4216                         rc = o->wait_comp(bp, o, pending_bit);
4217                         if (rc)
4218                                 return rc;
4219
4220                         return 0;
4221                 }
4222         }
4223
4224         return !!test_bit(pending_bit, pending);
4225 }
4226
4227 static int bnx2x_queue_set_pending(struct bnx2x_queue_sp_obj *obj,
4228                                    struct bnx2x_queue_state_params *params)
4229 {
4230         enum bnx2x_queue_cmd cmd = params->cmd, bit;
4231
4232         /* ACTIVATE and DEACTIVATE commands are implemented on top of
4233          * UPDATE command.
4234          */
4235         if ((cmd == BNX2X_Q_CMD_ACTIVATE) ||
4236             (cmd == BNX2X_Q_CMD_DEACTIVATE))
4237                 bit = BNX2X_Q_CMD_UPDATE;
4238         else
4239                 bit = cmd;
4240
4241         set_bit(bit, &obj->pending);
4242         return bit;
4243 }
4244
4245 static int bnx2x_queue_wait_comp(struct bnx2x *bp,
4246                                  struct bnx2x_queue_sp_obj *o,
4247                                  enum bnx2x_queue_cmd cmd)
4248 {
4249         return bnx2x_state_wait(bp, cmd, &o->pending);
4250 }
4251
4252 /**
4253  * bnx2x_queue_comp_cmd - complete the state change command.
4254  *
4255  * @bp:         device handle
4256  * @o:
4257  * @cmd:
4258  *
4259  * Checks that the arrived completion is expected.
4260  */
4261 static int bnx2x_queue_comp_cmd(struct bnx2x *bp,
4262                                 struct bnx2x_queue_sp_obj *o,
4263                                 enum bnx2x_queue_cmd cmd)
4264 {
4265         unsigned long cur_pending = o->pending;
4266
4267         if (!test_and_clear_bit(cmd, &cur_pending)) {
4268                 BNX2X_ERR("Bad MC reply %d for queue %d in state %d pending 0x%lx, next_state %d\n",
4269                           cmd, o->cids[BNX2X_PRIMARY_CID_INDEX],
4270                           o->state, cur_pending, o->next_state);
4271                 return -EINVAL;
4272         }
4273
4274         if (o->next_tx_only >= o->max_cos)
4275                 /* >= because tx only must always be smaller than cos since the
4276                  * primary connection supports COS 0
4277                  */
4278                 BNX2X_ERR("illegal value for next tx_only: %d. max cos was %d",
4279                            o->next_tx_only, o->max_cos);
4280
4281         DP(BNX2X_MSG_SP,
4282            "Completing command %d for queue %d, setting state to %d\n",
4283            cmd, o->cids[BNX2X_PRIMARY_CID_INDEX], o->next_state);
4284
4285         if (o->next_tx_only)  /* print num tx-only if any exist */
4286                 DP(BNX2X_MSG_SP, "primary cid %d: num tx-only cons %d\n",
4287                    o->cids[BNX2X_PRIMARY_CID_INDEX], o->next_tx_only);
4288
4289         o->state = o->next_state;
4290         o->num_tx_only = o->next_tx_only;
4291         o->next_state = BNX2X_Q_STATE_MAX;
4292
4293         /* It's important that o->state and o->next_state are
4294          * updated before o->pending.
4295          */
4296         wmb();
4297
4298         clear_bit(cmd, &o->pending);
4299         smp_mb__after_atomic();
4300
4301         return 0;
4302 }
4303
4304 static void bnx2x_q_fill_setup_data_e2(struct bnx2x *bp,
4305                                 struct bnx2x_queue_state_params *cmd_params,
4306                                 struct client_init_ramrod_data *data)
4307 {
4308         struct bnx2x_queue_setup_params *params = &cmd_params->params.setup;
4309
4310         /* Rx data */
4311
4312         /* IPv6 TPA supported for E2 and above only */
4313         data->rx.tpa_en |= test_bit(BNX2X_Q_FLG_TPA_IPV6, &params->flags) *
4314                                 CLIENT_INIT_RX_DATA_TPA_EN_IPV6;
4315 }
4316
4317 static void bnx2x_q_fill_init_general_data(struct bnx2x *bp,
4318                                 struct bnx2x_queue_sp_obj *o,
4319                                 struct bnx2x_general_setup_params *params,
4320                                 struct client_init_general_data *gen_data,
4321                                 unsigned long *flags)
4322 {
4323         gen_data->client_id = o->cl_id;
4324
4325         if (test_bit(BNX2X_Q_FLG_STATS, flags)) {
4326                 gen_data->statistics_counter_id =
4327                                         params->stat_id;
4328                 gen_data->statistics_en_flg = 1;
4329                 gen_data->statistics_zero_flg =
4330                         test_bit(BNX2X_Q_FLG_ZERO_STATS, flags);
4331         } else
4332                 gen_data->statistics_counter_id =
4333                                         DISABLE_STATISTIC_COUNTER_ID_VALUE;
4334
4335         gen_data->is_fcoe_flg = test_bit(BNX2X_Q_FLG_FCOE, flags);
4336         gen_data->activate_flg = test_bit(BNX2X_Q_FLG_ACTIVE, flags);
4337         gen_data->sp_client_id = params->spcl_id;
4338         gen_data->mtu = cpu_to_le16(params->mtu);
4339         gen_data->func_id = o->func_id;
4340
4341         gen_data->cos = params->cos;
4342
4343         gen_data->traffic_type =
4344                 test_bit(BNX2X_Q_FLG_FCOE, flags) ?
4345                 LLFC_TRAFFIC_TYPE_FCOE : LLFC_TRAFFIC_TYPE_NW;
4346
4347         gen_data->fp_hsi_ver = params->fp_hsi;
4348
4349         DP(BNX2X_MSG_SP, "flags: active %d, cos %d, stats en %d\n",
4350            gen_data->activate_flg, gen_data->cos, gen_data->statistics_en_flg);
4351 }
4352
4353 static void bnx2x_q_fill_init_tx_data(struct bnx2x_queue_sp_obj *o,
4354                                 struct bnx2x_txq_setup_params *params,
4355                                 struct client_init_tx_data *tx_data,
4356                                 unsigned long *flags)
4357 {
4358         tx_data->enforce_security_flg =
4359                 test_bit(BNX2X_Q_FLG_TX_SEC, flags);
4360         tx_data->default_vlan =
4361                 cpu_to_le16(params->default_vlan);
4362         tx_data->default_vlan_flg =
4363                 test_bit(BNX2X_Q_FLG_DEF_VLAN, flags);
4364         tx_data->tx_switching_flg =
4365                 test_bit(BNX2X_Q_FLG_TX_SWITCH, flags);
4366         tx_data->anti_spoofing_flg =
4367                 test_bit(BNX2X_Q_FLG_ANTI_SPOOF, flags);
4368         tx_data->force_default_pri_flg =
4369                 test_bit(BNX2X_Q_FLG_FORCE_DEFAULT_PRI, flags);
4370         tx_data->refuse_outband_vlan_flg =
4371                 test_bit(BNX2X_Q_FLG_REFUSE_OUTBAND_VLAN, flags);
4372         tx_data->tunnel_lso_inc_ip_id =
4373                 test_bit(BNX2X_Q_FLG_TUN_INC_INNER_IP_ID, flags);
4374         tx_data->tunnel_non_lso_pcsum_location =
4375                 test_bit(BNX2X_Q_FLG_PCSUM_ON_PKT, flags) ? CSUM_ON_PKT :
4376                                                             CSUM_ON_BD;
4377
4378         tx_data->tx_status_block_id = params->fw_sb_id;
4379         tx_data->tx_sb_index_number = params->sb_cq_index;
4380         tx_data->tss_leading_client_id = params->tss_leading_cl_id;
4381
4382         tx_data->tx_bd_page_base.lo =
4383                 cpu_to_le32(U64_LO(params->dscr_map));
4384         tx_data->tx_bd_page_base.hi =
4385                 cpu_to_le32(U64_HI(params->dscr_map));
4386
4387         /* Don't configure any Tx switching mode during queue SETUP */
4388         tx_data->state = 0;
4389 }
4390
4391 static void bnx2x_q_fill_init_pause_data(struct bnx2x_queue_sp_obj *o,
4392                                 struct rxq_pause_params *params,
4393                                 struct client_init_rx_data *rx_data)
4394 {
4395         /* flow control data */
4396         rx_data->cqe_pause_thr_low = cpu_to_le16(params->rcq_th_lo);
4397         rx_data->cqe_pause_thr_high = cpu_to_le16(params->rcq_th_hi);
4398         rx_data->bd_pause_thr_low = cpu_to_le16(params->bd_th_lo);
4399         rx_data->bd_pause_thr_high = cpu_to_le16(params->bd_th_hi);
4400         rx_data->sge_pause_thr_low = cpu_to_le16(params->sge_th_lo);
4401         rx_data->sge_pause_thr_high = cpu_to_le16(params->sge_th_hi);
4402         rx_data->rx_cos_mask = cpu_to_le16(params->pri_map);
4403 }
4404
4405 static void bnx2x_q_fill_init_rx_data(struct bnx2x_queue_sp_obj *o,
4406                                 struct bnx2x_rxq_setup_params *params,
4407                                 struct client_init_rx_data *rx_data,
4408                                 unsigned long *flags)
4409 {
4410         rx_data->tpa_en = test_bit(BNX2X_Q_FLG_TPA, flags) *
4411                                 CLIENT_INIT_RX_DATA_TPA_EN_IPV4;
4412         rx_data->tpa_en |= test_bit(BNX2X_Q_FLG_TPA_GRO, flags) *
4413                                 CLIENT_INIT_RX_DATA_TPA_MODE;
4414         rx_data->vmqueue_mode_en_flg = 0;
4415
4416         rx_data->cache_line_alignment_log_size =
4417                 params->cache_line_log;
4418         rx_data->enable_dynamic_hc =
4419                 test_bit(BNX2X_Q_FLG_DHC, flags);
4420         rx_data->max_sges_for_packet = params->max_sges_pkt;
4421         rx_data->client_qzone_id = params->cl_qzone_id;
4422         rx_data->max_agg_size = cpu_to_le16(params->tpa_agg_sz);
4423
4424         /* Always start in DROP_ALL mode */
4425         rx_data->state = cpu_to_le16(CLIENT_INIT_RX_DATA_UCAST_DROP_ALL |
4426                                      CLIENT_INIT_RX_DATA_MCAST_DROP_ALL);
4427
4428         /* We don't set drop flags */
4429         rx_data->drop_ip_cs_err_flg = 0;
4430         rx_data->drop_tcp_cs_err_flg = 0;
4431         rx_data->drop_ttl0_flg = 0;
4432         rx_data->drop_udp_cs_err_flg = 0;
4433         rx_data->inner_vlan_removal_enable_flg =
4434                 test_bit(BNX2X_Q_FLG_VLAN, flags);
4435         rx_data->outer_vlan_removal_enable_flg =
4436                 test_bit(BNX2X_Q_FLG_OV, flags);
4437         rx_data->status_block_id = params->fw_sb_id;
4438         rx_data->rx_sb_index_number = params->sb_cq_index;
4439         rx_data->max_tpa_queues = params->max_tpa_queues;
4440         rx_data->max_bytes_on_bd = cpu_to_le16(params->buf_sz);
4441         rx_data->sge_buff_size = cpu_to_le16(params->sge_buf_sz);
4442         rx_data->bd_page_base.lo =
4443                 cpu_to_le32(U64_LO(params->dscr_map));
4444         rx_data->bd_page_base.hi =
4445                 cpu_to_le32(U64_HI(params->dscr_map));
4446         rx_data->sge_page_base.lo =
4447                 cpu_to_le32(U64_LO(params->sge_map));
4448         rx_data->sge_page_base.hi =
4449                 cpu_to_le32(U64_HI(params->sge_map));
4450         rx_data->cqe_page_base.lo =
4451                 cpu_to_le32(U64_LO(params->rcq_map));
4452         rx_data->cqe_page_base.hi =
4453                 cpu_to_le32(U64_HI(params->rcq_map));
4454         rx_data->is_leading_rss = test_bit(BNX2X_Q_FLG_LEADING_RSS, flags);
4455
4456         if (test_bit(BNX2X_Q_FLG_MCAST, flags)) {
4457                 rx_data->approx_mcast_engine_id = params->mcast_engine_id;
4458                 rx_data->is_approx_mcast = 1;
4459         }
4460
4461         rx_data->rss_engine_id = params->rss_engine_id;
4462
4463         /* silent vlan removal */
4464         rx_data->silent_vlan_removal_flg =
4465                 test_bit(BNX2X_Q_FLG_SILENT_VLAN_REM, flags);
4466         rx_data->silent_vlan_value =
4467                 cpu_to_le16(params->silent_removal_value);
4468         rx_data->silent_vlan_mask =
4469                 cpu_to_le16(params->silent_removal_mask);
4470 }
4471
4472 /* initialize the general, tx and rx parts of a queue object */
4473 static void bnx2x_q_fill_setup_data_cmn(struct bnx2x *bp,
4474                                 struct bnx2x_queue_state_params *cmd_params,
4475                                 struct client_init_ramrod_data *data)
4476 {
4477         bnx2x_q_fill_init_general_data(bp, cmd_params->q_obj,
4478                                        &cmd_params->params.setup.gen_params,
4479                                        &data->general,
4480                                        &cmd_params->params.setup.flags);
4481
4482         bnx2x_q_fill_init_tx_data(cmd_params->q_obj,
4483                                   &cmd_params->params.setup.txq_params,
4484                                   &data->tx,
4485                                   &cmd_params->params.setup.flags);
4486
4487         bnx2x_q_fill_init_rx_data(cmd_params->q_obj,
4488                                   &cmd_params->params.setup.rxq_params,
4489                                   &data->rx,
4490                                   &cmd_params->params.setup.flags);
4491
4492         bnx2x_q_fill_init_pause_data(cmd_params->q_obj,
4493                                      &cmd_params->params.setup.pause_params,
4494                                      &data->rx);
4495 }
4496
4497 /* initialize the general and tx parts of a tx-only queue object */
4498 static void bnx2x_q_fill_setup_tx_only(struct bnx2x *bp,
4499                                 struct bnx2x_queue_state_params *cmd_params,
4500                                 struct tx_queue_init_ramrod_data *data)
4501 {
4502         bnx2x_q_fill_init_general_data(bp, cmd_params->q_obj,
4503                                        &cmd_params->params.tx_only.gen_params,
4504                                        &data->general,
4505                                        &cmd_params->params.tx_only.flags);
4506
4507         bnx2x_q_fill_init_tx_data(cmd_params->q_obj,
4508                                   &cmd_params->params.tx_only.txq_params,
4509                                   &data->tx,
4510                                   &cmd_params->params.tx_only.flags);
4511
4512         DP(BNX2X_MSG_SP, "cid %d, tx bd page lo %x hi %x",
4513                          cmd_params->q_obj->cids[0],
4514                          data->tx.tx_bd_page_base.lo,
4515                          data->tx.tx_bd_page_base.hi);
4516 }
4517
4518 /**
4519  * bnx2x_q_init - init HW/FW queue
4520  *
4521  * @bp:         device handle
4522  * @params:
4523  *
4524  * HW/FW initial Queue configuration:
4525  *      - HC: Rx and Tx
4526  *      - CDU context validation
4527  *
4528  */
4529 static inline int bnx2x_q_init(struct bnx2x *bp,
4530                                struct bnx2x_queue_state_params *params)
4531 {
4532         struct bnx2x_queue_sp_obj *o = params->q_obj;
4533         struct bnx2x_queue_init_params *init = &params->params.init;
4534         u16 hc_usec;
4535         u8 cos;
4536
4537         /* Tx HC configuration */
4538         if (test_bit(BNX2X_Q_TYPE_HAS_TX, &o->type) &&
4539             test_bit(BNX2X_Q_FLG_HC, &init->tx.flags)) {
4540                 hc_usec = init->tx.hc_rate ? 1000000 / init->tx.hc_rate : 0;
4541
4542                 bnx2x_update_coalesce_sb_index(bp, init->tx.fw_sb_id,
4543                         init->tx.sb_cq_index,
4544                         !test_bit(BNX2X_Q_FLG_HC_EN, &init->tx.flags),
4545                         hc_usec);
4546         }
4547
4548         /* Rx HC configuration */
4549         if (test_bit(BNX2X_Q_TYPE_HAS_RX, &o->type) &&
4550             test_bit(BNX2X_Q_FLG_HC, &init->rx.flags)) {
4551                 hc_usec = init->rx.hc_rate ? 1000000 / init->rx.hc_rate : 0;
4552
4553                 bnx2x_update_coalesce_sb_index(bp, init->rx.fw_sb_id,
4554                         init->rx.sb_cq_index,
4555                         !test_bit(BNX2X_Q_FLG_HC_EN, &init->rx.flags),
4556                         hc_usec);
4557         }
4558
4559         /* Set CDU context validation values */
4560         for (cos = 0; cos < o->max_cos; cos++) {
4561                 DP(BNX2X_MSG_SP, "setting context validation. cid %d, cos %d\n",
4562                                  o->cids[cos], cos);
4563                 DP(BNX2X_MSG_SP, "context pointer %p\n", init->cxts[cos]);
4564                 bnx2x_set_ctx_validation(bp, init->cxts[cos], o->cids[cos]);
4565         }
4566
4567         /* As no ramrod is sent, complete the command immediately  */
4568         o->complete_cmd(bp, o, BNX2X_Q_CMD_INIT);
4569
4570         mmiowb();
4571         smp_mb();
4572
4573         return 0;
4574 }
4575
4576 static inline int bnx2x_q_send_setup_e1x(struct bnx2x *bp,
4577                                         struct bnx2x_queue_state_params *params)
4578 {
4579         struct bnx2x_queue_sp_obj *o = params->q_obj;
4580         struct client_init_ramrod_data *rdata =
4581                 (struct client_init_ramrod_data *)o->rdata;
4582         dma_addr_t data_mapping = o->rdata_mapping;
4583         int ramrod = RAMROD_CMD_ID_ETH_CLIENT_SETUP;
4584
4585         /* Clear the ramrod data */
4586         memset(rdata, 0, sizeof(*rdata));
4587
4588         /* Fill the ramrod data */
4589         bnx2x_q_fill_setup_data_cmn(bp, params, rdata);
4590
4591         /* No need for an explicit memory barrier here as long as we
4592          * ensure the ordering of writing to the SPQ element
4593          * and updating of the SPQ producer which involves a memory
4594          * read. If the memory read is removed we will have to put a
4595          * full memory barrier there (inside bnx2x_sp_post()).
4596          */
4597         return bnx2x_sp_post(bp, ramrod, o->cids[BNX2X_PRIMARY_CID_INDEX],
4598                              U64_HI(data_mapping),
4599                              U64_LO(data_mapping), ETH_CONNECTION_TYPE);
4600 }
4601
4602 static inline int bnx2x_q_send_setup_e2(struct bnx2x *bp,
4603                                         struct bnx2x_queue_state_params *params)
4604 {
4605         struct bnx2x_queue_sp_obj *o = params->q_obj;
4606         struct client_init_ramrod_data *rdata =
4607                 (struct client_init_ramrod_data *)o->rdata;
4608         dma_addr_t data_mapping = o->rdata_mapping;
4609         int ramrod = RAMROD_CMD_ID_ETH_CLIENT_SETUP;
4610
4611         /* Clear the ramrod data */
4612         memset(rdata, 0, sizeof(*rdata));
4613
4614         /* Fill the ramrod data */
4615         bnx2x_q_fill_setup_data_cmn(bp, params, rdata);
4616         bnx2x_q_fill_setup_data_e2(bp, params, rdata);
4617
4618         /* No need for an explicit memory barrier here as long as we
4619          * ensure the ordering of writing to the SPQ element
4620          * and updating of the SPQ producer which involves a memory
4621          * read. If the memory read is removed we will have to put a
4622          * full memory barrier there (inside bnx2x_sp_post()).
4623          */
4624         return bnx2x_sp_post(bp, ramrod, o->cids[BNX2X_PRIMARY_CID_INDEX],
4625                              U64_HI(data_mapping),
4626                              U64_LO(data_mapping), ETH_CONNECTION_TYPE);
4627 }
4628
4629 static inline int bnx2x_q_send_setup_tx_only(struct bnx2x *bp,
4630                                   struct bnx2x_queue_state_params *params)
4631 {
4632         struct bnx2x_queue_sp_obj *o = params->q_obj;
4633         struct tx_queue_init_ramrod_data *rdata =
4634                 (struct tx_queue_init_ramrod_data *)o->rdata;
4635         dma_addr_t data_mapping = o->rdata_mapping;
4636         int ramrod = RAMROD_CMD_ID_ETH_TX_QUEUE_SETUP;
4637         struct bnx2x_queue_setup_tx_only_params *tx_only_params =
4638                 &params->params.tx_only;
4639         u8 cid_index = tx_only_params->cid_index;
4640
4641         if (cid_index >= o->max_cos) {
4642                 BNX2X_ERR("queue[%d]: cid_index (%d) is out of range\n",
4643                           o->cl_id, cid_index);
4644                 return -EINVAL;
4645         }
4646
4647         DP(BNX2X_MSG_SP, "parameters received: cos: %d sp-id: %d\n",
4648                          tx_only_params->gen_params.cos,
4649                          tx_only_params->gen_params.spcl_id);
4650
4651         /* Clear the ramrod data */
4652         memset(rdata, 0, sizeof(*rdata));
4653
4654         /* Fill the ramrod data */
4655         bnx2x_q_fill_setup_tx_only(bp, params, rdata);
4656
4657         DP(BNX2X_MSG_SP, "sending tx-only ramrod: cid %d, client-id %d, sp-client id %d, cos %d\n",
4658                          o->cids[cid_index], rdata->general.client_id,
4659                          rdata->general.sp_client_id, rdata->general.cos);
4660
4661         /* No need for an explicit memory barrier here as long as we
4662          * ensure the ordering of writing to the SPQ element
4663          * and updating of the SPQ producer which involves a memory
4664          * read. If the memory read is removed we will have to put a
4665          * full memory barrier there (inside bnx2x_sp_post()).
4666          */
4667         return bnx2x_sp_post(bp, ramrod, o->cids[cid_index],
4668                              U64_HI(data_mapping),
4669                              U64_LO(data_mapping), ETH_CONNECTION_TYPE);
4670 }
4671
4672 static void bnx2x_q_fill_update_data(struct bnx2x *bp,
4673                                      struct bnx2x_queue_sp_obj *obj,
4674                                      struct bnx2x_queue_update_params *params,
4675                                      struct client_update_ramrod_data *data)
4676 {
4677         /* Client ID of the client to update */
4678         data->client_id = obj->cl_id;
4679
4680         /* Function ID of the client to update */
4681         data->func_id = obj->func_id;
4682
4683         /* Default VLAN value */
4684         data->default_vlan = cpu_to_le16(params->def_vlan);
4685
4686         /* Inner VLAN stripping */
4687         data->inner_vlan_removal_enable_flg =
4688                 test_bit(BNX2X_Q_UPDATE_IN_VLAN_REM, &params->update_flags);
4689         data->inner_vlan_removal_change_flg =
4690                 test_bit(BNX2X_Q_UPDATE_IN_VLAN_REM_CHNG,
4691                          &params->update_flags);
4692
4693         /* Outer VLAN stripping */
4694         data->outer_vlan_removal_enable_flg =
4695                 test_bit(BNX2X_Q_UPDATE_OUT_VLAN_REM, &params->update_flags);
4696         data->outer_vlan_removal_change_flg =
4697                 test_bit(BNX2X_Q_UPDATE_OUT_VLAN_REM_CHNG,
4698                          &params->update_flags);
4699
4700         /* Drop packets that have source MAC that doesn't belong to this
4701          * Queue.
4702          */
4703         data->anti_spoofing_enable_flg =
4704                 test_bit(BNX2X_Q_UPDATE_ANTI_SPOOF, &params->update_flags);
4705         data->anti_spoofing_change_flg =
4706                 test_bit(BNX2X_Q_UPDATE_ANTI_SPOOF_CHNG, &params->update_flags);
4707
4708         /* Activate/Deactivate */
4709         data->activate_flg =
4710                 test_bit(BNX2X_Q_UPDATE_ACTIVATE, &params->update_flags);
4711         data->activate_change_flg =
4712                 test_bit(BNX2X_Q_UPDATE_ACTIVATE_CHNG, &params->update_flags);
4713
4714         /* Enable default VLAN */
4715         data->default_vlan_enable_flg =
4716                 test_bit(BNX2X_Q_UPDATE_DEF_VLAN_EN, &params->update_flags);
4717         data->default_vlan_change_flg =
4718                 test_bit(BNX2X_Q_UPDATE_DEF_VLAN_EN_CHNG,
4719                          &params->update_flags);
4720
4721         /* silent vlan removal */
4722         data->silent_vlan_change_flg =
4723                 test_bit(BNX2X_Q_UPDATE_SILENT_VLAN_REM_CHNG,
4724                          &params->update_flags);
4725         data->silent_vlan_removal_flg =
4726                 test_bit(BNX2X_Q_UPDATE_SILENT_VLAN_REM, &params->update_flags);
4727         data->silent_vlan_value = cpu_to_le16(params->silent_removal_value);
4728         data->silent_vlan_mask = cpu_to_le16(params->silent_removal_mask);
4729
4730         /* tx switching */
4731         data->tx_switching_flg =
4732                 test_bit(BNX2X_Q_UPDATE_TX_SWITCHING, &params->update_flags);
4733         data->tx_switching_change_flg =
4734                 test_bit(BNX2X_Q_UPDATE_TX_SWITCHING_CHNG,
4735                          &params->update_flags);
4736
4737         /* PTP */
4738         data->handle_ptp_pkts_flg =
4739                 test_bit(BNX2X_Q_UPDATE_PTP_PKTS, &params->update_flags);
4740         data->handle_ptp_pkts_change_flg =
4741                 test_bit(BNX2X_Q_UPDATE_PTP_PKTS_CHNG, &params->update_flags);
4742 }
4743
4744 static inline int bnx2x_q_send_update(struct bnx2x *bp,
4745                                       struct bnx2x_queue_state_params *params)
4746 {
4747         struct bnx2x_queue_sp_obj *o = params->q_obj;
4748         struct client_update_ramrod_data *rdata =
4749                 (struct client_update_ramrod_data *)o->rdata;
4750         dma_addr_t data_mapping = o->rdata_mapping;
4751         struct bnx2x_queue_update_params *update_params =
4752                 &params->params.update;
4753         u8 cid_index = update_params->cid_index;
4754
4755         if (cid_index >= o->max_cos) {
4756                 BNX2X_ERR("queue[%d]: cid_index (%d) is out of range\n",
4757                           o->cl_id, cid_index);
4758                 return -EINVAL;
4759         }
4760
4761         /* Clear the ramrod data */
4762         memset(rdata, 0, sizeof(*rdata));
4763
4764         /* Fill the ramrod data */
4765         bnx2x_q_fill_update_data(bp, o, update_params, rdata);
4766
4767         /* No need for an explicit memory barrier here as long as we
4768          * ensure the ordering of writing to the SPQ element
4769          * and updating of the SPQ producer which involves a memory
4770          * read. If the memory read is removed we will have to put a
4771          * full memory barrier there (inside bnx2x_sp_post()).
4772          */
4773         return bnx2x_sp_post(bp, RAMROD_CMD_ID_ETH_CLIENT_UPDATE,
4774                              o->cids[cid_index], U64_HI(data_mapping),
4775                              U64_LO(data_mapping), ETH_CONNECTION_TYPE);
4776 }
4777
4778 /**
4779  * bnx2x_q_send_deactivate - send DEACTIVATE command
4780  *
4781  * @bp:         device handle
4782  * @params:
4783  *
4784  * implemented using the UPDATE command.
4785  */
4786 static inline int bnx2x_q_send_deactivate(struct bnx2x *bp,
4787                                         struct bnx2x_queue_state_params *params)
4788 {
4789         struct bnx2x_queue_update_params *update = &params->params.update;
4790
4791         memset(update, 0, sizeof(*update));
4792
4793         __set_bit(BNX2X_Q_UPDATE_ACTIVATE_CHNG, &update->update_flags);
4794
4795         return bnx2x_q_send_update(bp, params);
4796 }
4797
4798 /**
4799  * bnx2x_q_send_activate - send ACTIVATE command
4800  *
4801  * @bp:         device handle
4802  * @params:
4803  *
4804  * implemented using the UPDATE command.
4805  */
4806 static inline int bnx2x_q_send_activate(struct bnx2x *bp,
4807                                         struct bnx2x_queue_state_params *params)
4808 {
4809         struct bnx2x_queue_update_params *update = &params->params.update;
4810
4811         memset(update, 0, sizeof(*update));
4812
4813         __set_bit(BNX2X_Q_UPDATE_ACTIVATE, &update->update_flags);
4814         __set_bit(BNX2X_Q_UPDATE_ACTIVATE_CHNG, &update->update_flags);
4815
4816         return bnx2x_q_send_update(bp, params);
4817 }
4818
4819 static void bnx2x_q_fill_update_tpa_data(struct bnx2x *bp,
4820                                 struct bnx2x_queue_sp_obj *obj,
4821                                 struct bnx2x_queue_update_tpa_params *params,
4822                                 struct tpa_update_ramrod_data *data)
4823 {
4824         data->client_id = obj->cl_id;
4825         data->complete_on_both_clients = params->complete_on_both_clients;
4826         data->dont_verify_rings_pause_thr_flg =
4827                 params->dont_verify_thr;
4828         data->max_agg_size = cpu_to_le16(params->max_agg_sz);
4829         data->max_sges_for_packet = params->max_sges_pkt;
4830         data->max_tpa_queues = params->max_tpa_queues;
4831         data->sge_buff_size = cpu_to_le16(params->sge_buff_sz);
4832         data->sge_page_base_hi = cpu_to_le32(U64_HI(params->sge_map));
4833         data->sge_page_base_lo = cpu_to_le32(U64_LO(params->sge_map));
4834         data->sge_pause_thr_high = cpu_to_le16(params->sge_pause_thr_high);
4835         data->sge_pause_thr_low = cpu_to_le16(params->sge_pause_thr_low);
4836         data->tpa_mode = params->tpa_mode;
4837         data->update_ipv4 = params->update_ipv4;
4838         data->update_ipv6 = params->update_ipv6;
4839 }
4840
4841 static inline int bnx2x_q_send_update_tpa(struct bnx2x *bp,
4842                                         struct bnx2x_queue_state_params *params)
4843 {
4844         struct bnx2x_queue_sp_obj *o = params->q_obj;
4845         struct tpa_update_ramrod_data *rdata =
4846                 (struct tpa_update_ramrod_data *)o->rdata;
4847         dma_addr_t data_mapping = o->rdata_mapping;
4848         struct bnx2x_queue_update_tpa_params *update_tpa_params =
4849                 &params->params.update_tpa;
4850         u16 type;
4851
4852         /* Clear the ramrod data */
4853         memset(rdata, 0, sizeof(*rdata));
4854
4855         /* Fill the ramrod data */
4856         bnx2x_q_fill_update_tpa_data(bp, o, update_tpa_params, rdata);
4857
4858         /* Add the function id inside the type, so that sp post function
4859          * doesn't automatically add the PF func-id, this is required
4860          * for operations done by PFs on behalf of their VFs
4861          */
4862         type = ETH_CONNECTION_TYPE |
4863                 ((o->func_id) << SPE_HDR_FUNCTION_ID_SHIFT);
4864
4865         /* No need for an explicit memory barrier here as long as we
4866          * ensure the ordering of writing to the SPQ element
4867          * and updating of the SPQ producer which involves a memory
4868          * read. If the memory read is removed we will have to put a
4869          * full memory barrier there (inside bnx2x_sp_post()).
4870          */
4871         return bnx2x_sp_post(bp, RAMROD_CMD_ID_ETH_TPA_UPDATE,
4872                              o->cids[BNX2X_PRIMARY_CID_INDEX],
4873                              U64_HI(data_mapping),
4874                              U64_LO(data_mapping), type);
4875 }
4876
4877 static inline int bnx2x_q_send_halt(struct bnx2x *bp,
4878                                     struct bnx2x_queue_state_params *params)
4879 {
4880         struct bnx2x_queue_sp_obj *o = params->q_obj;
4881
4882         return bnx2x_sp_post(bp, RAMROD_CMD_ID_ETH_HALT,
4883                              o->cids[BNX2X_PRIMARY_CID_INDEX], 0, o->cl_id,
4884                              ETH_CONNECTION_TYPE);
4885 }
4886
4887 static inline int bnx2x_q_send_cfc_del(struct bnx2x *bp,
4888                                        struct bnx2x_queue_state_params *params)
4889 {
4890         struct bnx2x_queue_sp_obj *o = params->q_obj;
4891         u8 cid_idx = params->params.cfc_del.cid_index;
4892
4893         if (cid_idx >= o->max_cos) {
4894                 BNX2X_ERR("queue[%d]: cid_index (%d) is out of range\n",
4895                           o->cl_id, cid_idx);
4896                 return -EINVAL;
4897         }
4898
4899         return bnx2x_sp_post(bp, RAMROD_CMD_ID_COMMON_CFC_DEL,
4900                              o->cids[cid_idx], 0, 0, NONE_CONNECTION_TYPE);
4901 }
4902
4903 static inline int bnx2x_q_send_terminate(struct bnx2x *bp,
4904                                         struct bnx2x_queue_state_params *params)
4905 {
4906         struct bnx2x_queue_sp_obj *o = params->q_obj;
4907         u8 cid_index = params->params.terminate.cid_index;
4908
4909         if (cid_index >= o->max_cos) {
4910                 BNX2X_ERR("queue[%d]: cid_index (%d) is out of range\n",
4911                           o->cl_id, cid_index);
4912                 return -EINVAL;
4913         }
4914
4915         return bnx2x_sp_post(bp, RAMROD_CMD_ID_ETH_TERMINATE,
4916                              o->cids[cid_index], 0, 0, ETH_CONNECTION_TYPE);
4917 }
4918
4919 static inline int bnx2x_q_send_empty(struct bnx2x *bp,
4920                                      struct bnx2x_queue_state_params *params)
4921 {
4922         struct bnx2x_queue_sp_obj *o = params->q_obj;
4923
4924         return bnx2x_sp_post(bp, RAMROD_CMD_ID_ETH_EMPTY,
4925                              o->cids[BNX2X_PRIMARY_CID_INDEX], 0, 0,
4926                              ETH_CONNECTION_TYPE);
4927 }
4928
4929 static inline int bnx2x_queue_send_cmd_cmn(struct bnx2x *bp,
4930                                         struct bnx2x_queue_state_params *params)
4931 {
4932         switch (params->cmd) {
4933         case BNX2X_Q_CMD_INIT:
4934                 return bnx2x_q_init(bp, params);
4935         case BNX2X_Q_CMD_SETUP_TX_ONLY:
4936                 return bnx2x_q_send_setup_tx_only(bp, params);
4937         case BNX2X_Q_CMD_DEACTIVATE:
4938                 return bnx2x_q_send_deactivate(bp, params);
4939         case BNX2X_Q_CMD_ACTIVATE:
4940                 return bnx2x_q_send_activate(bp, params);
4941         case BNX2X_Q_CMD_UPDATE:
4942                 return bnx2x_q_send_update(bp, params);
4943         case BNX2X_Q_CMD_UPDATE_TPA:
4944                 return bnx2x_q_send_update_tpa(bp, params);
4945         case BNX2X_Q_CMD_HALT:
4946                 return bnx2x_q_send_halt(bp, params);
4947         case BNX2X_Q_CMD_CFC_DEL:
4948                 return bnx2x_q_send_cfc_del(bp, params);
4949         case BNX2X_Q_CMD_TERMINATE:
4950                 return bnx2x_q_send_terminate(bp, params);
4951         case BNX2X_Q_CMD_EMPTY:
4952                 return bnx2x_q_send_empty(bp, params);
4953         default:
4954                 BNX2X_ERR("Unknown command: %d\n", params->cmd);
4955                 return -EINVAL;
4956         }
4957 }
4958
4959 static int bnx2x_queue_send_cmd_e1x(struct bnx2x *bp,
4960                                     struct bnx2x_queue_state_params *params)
4961 {
4962         switch (params->cmd) {
4963         case BNX2X_Q_CMD_SETUP:
4964                 return bnx2x_q_send_setup_e1x(bp, params);
4965         case BNX2X_Q_CMD_INIT:
4966         case BNX2X_Q_CMD_SETUP_TX_ONLY:
4967         case BNX2X_Q_CMD_DEACTIVATE:
4968         case BNX2X_Q_CMD_ACTIVATE:
4969         case BNX2X_Q_CMD_UPDATE:
4970         case BNX2X_Q_CMD_UPDATE_TPA:
4971         case BNX2X_Q_CMD_HALT:
4972         case BNX2X_Q_CMD_CFC_DEL:
4973         case BNX2X_Q_CMD_TERMINATE:
4974         case BNX2X_Q_CMD_EMPTY:
4975                 return bnx2x_queue_send_cmd_cmn(bp, params);
4976         default:
4977                 BNX2X_ERR("Unknown command: %d\n", params->cmd);
4978                 return -EINVAL;
4979         }
4980 }
4981
4982 static int bnx2x_queue_send_cmd_e2(struct bnx2x *bp,
4983                                    struct bnx2x_queue_state_params *params)
4984 {
4985         switch (params->cmd) {
4986         case BNX2X_Q_CMD_SETUP:
4987                 return bnx2x_q_send_setup_e2(bp, params);
4988         case BNX2X_Q_CMD_INIT:
4989         case BNX2X_Q_CMD_SETUP_TX_ONLY:
4990         case BNX2X_Q_CMD_DEACTIVATE:
4991         case BNX2X_Q_CMD_ACTIVATE:
4992         case BNX2X_Q_CMD_UPDATE:
4993         case BNX2X_Q_CMD_UPDATE_TPA:
4994         case BNX2X_Q_CMD_HALT:
4995         case BNX2X_Q_CMD_CFC_DEL:
4996         case BNX2X_Q_CMD_TERMINATE:
4997         case BNX2X_Q_CMD_EMPTY:
4998                 return bnx2x_queue_send_cmd_cmn(bp, params);
4999         default:
5000                 BNX2X_ERR("Unknown command: %d\n", params->cmd);
5001                 return -EINVAL;
5002         }
5003 }
5004
5005 /**
5006  * bnx2x_queue_chk_transition - check state machine of a regular Queue
5007  *
5008  * @bp:         device handle
5009  * @o:
5010  * @params:
5011  *
5012  * (not Forwarding)
5013  * It both checks if the requested command is legal in a current
5014  * state and, if it's legal, sets a `next_state' in the object
5015  * that will be used in the completion flow to set the `state'
5016  * of the object.
5017  *
5018  * returns 0 if a requested command is a legal transition,
5019  *         -EINVAL otherwise.
5020  */
5021 static int bnx2x_queue_chk_transition(struct bnx2x *bp,
5022                                       struct bnx2x_queue_sp_obj *o,
5023                                       struct bnx2x_queue_state_params *params)
5024 {
5025         enum bnx2x_q_state state = o->state, next_state = BNX2X_Q_STATE_MAX;
5026         enum bnx2x_queue_cmd cmd = params->cmd;
5027         struct bnx2x_queue_update_params *update_params =
5028                  &params->params.update;
5029         u8 next_tx_only = o->num_tx_only;
5030
5031         /* Forget all pending for completion commands if a driver only state
5032          * transition has been requested.
5033          */
5034         if (test_bit(RAMROD_DRV_CLR_ONLY, &params->ramrod_flags)) {
5035                 o->pending = 0;
5036                 o->next_state = BNX2X_Q_STATE_MAX;
5037         }
5038
5039         /* Don't allow a next state transition if we are in the middle of
5040          * the previous one.
5041          */
5042         if (o->pending) {
5043                 BNX2X_ERR("Blocking transition since pending was %lx\n",
5044                           o->pending);
5045                 return -EBUSY;
5046         }
5047
5048         switch (state) {
5049         case BNX2X_Q_STATE_RESET:
5050                 if (cmd == BNX2X_Q_CMD_INIT)
5051                         next_state = BNX2X_Q_STATE_INITIALIZED;
5052
5053                 break;
5054         case BNX2X_Q_STATE_INITIALIZED:
5055                 if (cmd == BNX2X_Q_CMD_SETUP) {
5056                         if (test_bit(BNX2X_Q_FLG_ACTIVE,
5057                                      &params->params.setup.flags))
5058                                 next_state = BNX2X_Q_STATE_ACTIVE;
5059                         else
5060                                 next_state = BNX2X_Q_STATE_INACTIVE;
5061                 }
5062
5063                 break;
5064         case BNX2X_Q_STATE_ACTIVE:
5065                 if (cmd == BNX2X_Q_CMD_DEACTIVATE)
5066                         next_state = BNX2X_Q_STATE_INACTIVE;
5067
5068                 else if ((cmd == BNX2X_Q_CMD_EMPTY) ||
5069                          (cmd == BNX2X_Q_CMD_UPDATE_TPA))
5070                         next_state = BNX2X_Q_STATE_ACTIVE;
5071
5072                 else if (cmd == BNX2X_Q_CMD_SETUP_TX_ONLY) {
5073                         next_state = BNX2X_Q_STATE_MULTI_COS;
5074                         next_tx_only = 1;
5075                 }
5076
5077                 else if (cmd == BNX2X_Q_CMD_HALT)
5078                         next_state = BNX2X_Q_STATE_STOPPED;
5079
5080                 else if (cmd == BNX2X_Q_CMD_UPDATE) {
5081                         /* If "active" state change is requested, update the
5082                          *  state accordingly.
5083                          */
5084                         if (test_bit(BNX2X_Q_UPDATE_ACTIVATE_CHNG,
5085                                      &update_params->update_flags) &&
5086                             !test_bit(BNX2X_Q_UPDATE_ACTIVATE,
5087                                       &update_params->update_flags))
5088                                 next_state = BNX2X_Q_STATE_INACTIVE;
5089                         else
5090                                 next_state = BNX2X_Q_STATE_ACTIVE;
5091                 }
5092
5093                 break;
5094         case BNX2X_Q_STATE_MULTI_COS:
5095                 if (cmd == BNX2X_Q_CMD_TERMINATE)
5096                         next_state = BNX2X_Q_STATE_MCOS_TERMINATED;
5097
5098                 else if (cmd == BNX2X_Q_CMD_SETUP_TX_ONLY) {
5099                         next_state = BNX2X_Q_STATE_MULTI_COS;
5100                         next_tx_only = o->num_tx_only + 1;
5101                 }
5102
5103                 else if ((cmd == BNX2X_Q_CMD_EMPTY) ||
5104                          (cmd == BNX2X_Q_CMD_UPDATE_TPA))
5105                         next_state = BNX2X_Q_STATE_MULTI_COS;
5106
5107                 else if (cmd == BNX2X_Q_CMD_UPDATE) {
5108                         /* If "active" state change is requested, update the
5109                          *  state accordingly.
5110                          */
5111                         if (test_bit(BNX2X_Q_UPDATE_ACTIVATE_CHNG,
5112                                      &update_params->update_flags) &&
5113                             !test_bit(BNX2X_Q_UPDATE_ACTIVATE,
5114                                       &update_params->update_flags))
5115                                 next_state = BNX2X_Q_STATE_INACTIVE;
5116                         else
5117                                 next_state = BNX2X_Q_STATE_MULTI_COS;
5118                 }
5119
5120                 break;
5121         case BNX2X_Q_STATE_MCOS_TERMINATED:
5122                 if (cmd == BNX2X_Q_CMD_CFC_DEL) {
5123                         next_tx_only = o->num_tx_only - 1;
5124                         if (next_tx_only == 0)
5125                                 next_state = BNX2X_Q_STATE_ACTIVE;
5126                         else
5127                                 next_state = BNX2X_Q_STATE_MULTI_COS;
5128                 }
5129
5130                 break;
5131         case BNX2X_Q_STATE_INACTIVE:
5132                 if (cmd == BNX2X_Q_CMD_ACTIVATE)
5133                         next_state = BNX2X_Q_STATE_ACTIVE;
5134
5135                 else if ((cmd == BNX2X_Q_CMD_EMPTY) ||
5136                          (cmd == BNX2X_Q_CMD_UPDATE_TPA))
5137                         next_state = BNX2X_Q_STATE_INACTIVE;
5138
5139                 else if (cmd == BNX2X_Q_CMD_HALT)
5140                         next_state = BNX2X_Q_STATE_STOPPED;
5141
5142                 else if (cmd == BNX2X_Q_CMD_UPDATE) {
5143                         /* If "active" state change is requested, update the
5144                          * state accordingly.
5145                          */
5146                         if (test_bit(BNX2X_Q_UPDATE_ACTIVATE_CHNG,
5147                                      &update_params->update_flags) &&
5148                             test_bit(BNX2X_Q_UPDATE_ACTIVATE,
5149                                      &update_params->update_flags)){
5150                                 if (o->num_tx_only == 0)
5151                                         next_state = BNX2X_Q_STATE_ACTIVE;
5152                                 else /* tx only queues exist for this queue */
5153                                         next_state = BNX2X_Q_STATE_MULTI_COS;
5154                         } else
5155                                 next_state = BNX2X_Q_STATE_INACTIVE;
5156                 }
5157
5158                 break;
5159         case BNX2X_Q_STATE_STOPPED:
5160                 if (cmd == BNX2X_Q_CMD_TERMINATE)
5161                         next_state = BNX2X_Q_STATE_TERMINATED;
5162
5163                 break;
5164         case BNX2X_Q_STATE_TERMINATED:
5165                 if (cmd == BNX2X_Q_CMD_CFC_DEL)
5166                         next_state = BNX2X_Q_STATE_RESET;
5167
5168                 break;
5169         default:
5170                 BNX2X_ERR("Illegal state: %d\n", state);
5171         }
5172
5173         /* Transition is assured */
5174         if (next_state != BNX2X_Q_STATE_MAX) {
5175                 DP(BNX2X_MSG_SP, "Good state transition: %d(%d)->%d\n",
5176                                  state, cmd, next_state);
5177                 o->next_state = next_state;
5178                 o->next_tx_only = next_tx_only;
5179                 return 0;
5180         }
5181
5182         DP(BNX2X_MSG_SP, "Bad state transition request: %d %d\n", state, cmd);
5183
5184         return -EINVAL;
5185 }
5186
5187 void bnx2x_init_queue_obj(struct bnx2x *bp,
5188                           struct bnx2x_queue_sp_obj *obj,
5189                           u8 cl_id, u32 *cids, u8 cid_cnt, u8 func_id,
5190                           void *rdata,
5191                           dma_addr_t rdata_mapping, unsigned long type)
5192 {
5193         memset(obj, 0, sizeof(*obj));
5194
5195         /* We support only BNX2X_MULTI_TX_COS Tx CoS at the moment */
5196         BUG_ON(BNX2X_MULTI_TX_COS < cid_cnt);
5197
5198         memcpy(obj->cids, cids, sizeof(obj->cids[0]) * cid_cnt);
5199         obj->max_cos = cid_cnt;
5200         obj->cl_id = cl_id;
5201         obj->func_id = func_id;
5202         obj->rdata = rdata;
5203         obj->rdata_mapping = rdata_mapping;
5204         obj->type = type;
5205         obj->next_state = BNX2X_Q_STATE_MAX;
5206
5207         if (CHIP_IS_E1x(bp))
5208                 obj->send_cmd = bnx2x_queue_send_cmd_e1x;
5209         else
5210                 obj->send_cmd = bnx2x_queue_send_cmd_e2;
5211
5212         obj->check_transition = bnx2x_queue_chk_transition;
5213
5214         obj->complete_cmd = bnx2x_queue_comp_cmd;
5215         obj->wait_comp = bnx2x_queue_wait_comp;
5216         obj->set_pending = bnx2x_queue_set_pending;
5217 }
5218
5219 /* return a queue object's logical state*/
5220 int bnx2x_get_q_logical_state(struct bnx2x *bp,
5221                                struct bnx2x_queue_sp_obj *obj)
5222 {
5223         switch (obj->state) {
5224         case BNX2X_Q_STATE_ACTIVE:
5225         case BNX2X_Q_STATE_MULTI_COS:
5226                 return BNX2X_Q_LOGICAL_STATE_ACTIVE;
5227         case BNX2X_Q_STATE_RESET:
5228         case BNX2X_Q_STATE_INITIALIZED:
5229         case BNX2X_Q_STATE_MCOS_TERMINATED:
5230         case BNX2X_Q_STATE_INACTIVE:
5231         case BNX2X_Q_STATE_STOPPED:
5232         case BNX2X_Q_STATE_TERMINATED:
5233         case BNX2X_Q_STATE_FLRED:
5234                 return BNX2X_Q_LOGICAL_STATE_STOPPED;
5235         default:
5236                 return -EINVAL;
5237         }
5238 }
5239
5240 /********************** Function state object *********************************/
5241 enum bnx2x_func_state bnx2x_func_get_state(struct bnx2x *bp,
5242                                            struct bnx2x_func_sp_obj *o)
5243 {
5244         /* in the middle of transaction - return INVALID state */
5245         if (o->pending)
5246                 return BNX2X_F_STATE_MAX;
5247
5248         /* unsure the order of reading of o->pending and o->state
5249          * o->pending should be read first
5250          */
5251         rmb();
5252
5253         return o->state;
5254 }
5255
5256 static int bnx2x_func_wait_comp(struct bnx2x *bp,
5257                                 struct bnx2x_func_sp_obj *o,
5258                                 enum bnx2x_func_cmd cmd)
5259 {
5260         return bnx2x_state_wait(bp, cmd, &o->pending);
5261 }
5262
5263 /**
5264  * bnx2x_func_state_change_comp - complete the state machine transition
5265  *
5266  * @bp:         device handle
5267  * @o:
5268  * @cmd:
5269  *
5270  * Called on state change transition. Completes the state
5271  * machine transition only - no HW interaction.
5272  */
5273 static inline int bnx2x_func_state_change_comp(struct bnx2x *bp,
5274                                                struct bnx2x_func_sp_obj *o,
5275                                                enum bnx2x_func_cmd cmd)
5276 {
5277         unsigned long cur_pending = o->pending;
5278
5279         if (!test_and_clear_bit(cmd, &cur_pending)) {
5280                 BNX2X_ERR("Bad MC reply %d for func %d in state %d pending 0x%lx, next_state %d\n",
5281                           cmd, BP_FUNC(bp), o->state,
5282                           cur_pending, o->next_state);
5283                 return -EINVAL;
5284         }
5285
5286         DP(BNX2X_MSG_SP,
5287            "Completing command %d for func %d, setting state to %d\n",
5288            cmd, BP_FUNC(bp), o->next_state);
5289
5290         o->state = o->next_state;
5291         o->next_state = BNX2X_F_STATE_MAX;
5292
5293         /* It's important that o->state and o->next_state are
5294          * updated before o->pending.
5295          */
5296         wmb();
5297
5298         clear_bit(cmd, &o->pending);
5299         smp_mb__after_atomic();
5300
5301         return 0;
5302 }
5303
5304 /**
5305  * bnx2x_func_comp_cmd - complete the state change command
5306  *
5307  * @bp:         device handle
5308  * @o:
5309  * @cmd:
5310  *
5311  * Checks that the arrived completion is expected.
5312  */
5313 static int bnx2x_func_comp_cmd(struct bnx2x *bp,
5314                                struct bnx2x_func_sp_obj *o,
5315                                enum bnx2x_func_cmd cmd)
5316 {
5317         /* Complete the state machine part first, check if it's a
5318          * legal completion.
5319          */
5320         int rc = bnx2x_func_state_change_comp(bp, o, cmd);
5321         return rc;
5322 }
5323
5324 /**
5325  * bnx2x_func_chk_transition - perform function state machine transition
5326  *
5327  * @bp:         device handle
5328  * @o:
5329  * @params:
5330  *
5331  * It both checks if the requested command is legal in a current
5332  * state and, if it's legal, sets a `next_state' in the object
5333  * that will be used in the completion flow to set the `state'
5334  * of the object.
5335  *
5336  * returns 0 if a requested command is a legal transition,
5337  *         -EINVAL otherwise.
5338  */
5339 static int bnx2x_func_chk_transition(struct bnx2x *bp,
5340                                      struct bnx2x_func_sp_obj *o,
5341                                      struct bnx2x_func_state_params *params)
5342 {
5343         enum bnx2x_func_state state = o->state, next_state = BNX2X_F_STATE_MAX;
5344         enum bnx2x_func_cmd cmd = params->cmd;
5345
5346         /* Forget all pending for completion commands if a driver only state
5347          * transition has been requested.
5348          */
5349         if (test_bit(RAMROD_DRV_CLR_ONLY, &params->ramrod_flags)) {
5350                 o->pending = 0;
5351                 o->next_state = BNX2X_F_STATE_MAX;
5352         }
5353
5354         /* Don't allow a next state transition if we are in the middle of
5355          * the previous one.
5356          */
5357         if (o->pending)
5358                 return -EBUSY;
5359
5360         switch (state) {
5361         case BNX2X_F_STATE_RESET:
5362                 if (cmd == BNX2X_F_CMD_HW_INIT)
5363                         next_state = BNX2X_F_STATE_INITIALIZED;
5364
5365                 break;
5366         case BNX2X_F_STATE_INITIALIZED:
5367                 if (cmd == BNX2X_F_CMD_START)
5368                         next_state = BNX2X_F_STATE_STARTED;
5369
5370                 else if (cmd == BNX2X_F_CMD_HW_RESET)
5371                         next_state = BNX2X_F_STATE_RESET;
5372
5373                 break;
5374         case BNX2X_F_STATE_STARTED:
5375                 if (cmd == BNX2X_F_CMD_STOP)
5376                         next_state = BNX2X_F_STATE_INITIALIZED;
5377                 /* afex ramrods can be sent only in started mode, and only
5378                  * if not pending for function_stop ramrod completion
5379                  * for these events - next state remained STARTED.
5380                  */
5381                 else if ((cmd == BNX2X_F_CMD_AFEX_UPDATE) &&
5382                          (!test_bit(BNX2X_F_CMD_STOP, &o->pending)))
5383                         next_state = BNX2X_F_STATE_STARTED;
5384
5385                 else if ((cmd == BNX2X_F_CMD_AFEX_VIFLISTS) &&
5386                          (!test_bit(BNX2X_F_CMD_STOP, &o->pending)))
5387                         next_state = BNX2X_F_STATE_STARTED;
5388
5389                 /* Switch_update ramrod can be sent in either started or
5390                  * tx_stopped state, and it doesn't change the state.
5391                  */
5392                 else if ((cmd == BNX2X_F_CMD_SWITCH_UPDATE) &&
5393                          (!test_bit(BNX2X_F_CMD_STOP, &o->pending)))
5394                         next_state = BNX2X_F_STATE_STARTED;
5395
5396                 else if ((cmd == BNX2X_F_CMD_SET_TIMESYNC) &&
5397                          (!test_bit(BNX2X_F_CMD_STOP, &o->pending)))
5398                         next_state = BNX2X_F_STATE_STARTED;
5399
5400                 else if (cmd == BNX2X_F_CMD_TX_STOP)
5401                         next_state = BNX2X_F_STATE_TX_STOPPED;
5402
5403                 break;
5404         case BNX2X_F_STATE_TX_STOPPED:
5405                 if ((cmd == BNX2X_F_CMD_SWITCH_UPDATE) &&
5406                     (!test_bit(BNX2X_F_CMD_STOP, &o->pending)))
5407                         next_state = BNX2X_F_STATE_TX_STOPPED;
5408
5409                 else if ((cmd == BNX2X_F_CMD_SET_TIMESYNC) &&
5410                          (!test_bit(BNX2X_F_CMD_STOP, &o->pending)))
5411                         next_state = BNX2X_F_STATE_TX_STOPPED;
5412
5413                 else if (cmd == BNX2X_F_CMD_TX_START)
5414                         next_state = BNX2X_F_STATE_STARTED;
5415
5416                 break;
5417         default:
5418                 BNX2X_ERR("Unknown state: %d\n", state);
5419         }
5420
5421         /* Transition is assured */
5422         if (next_state != BNX2X_F_STATE_MAX) {
5423                 DP(BNX2X_MSG_SP, "Good function state transition: %d(%d)->%d\n",
5424                                  state, cmd, next_state);
5425                 o->next_state = next_state;
5426                 return 0;
5427         }
5428
5429         DP(BNX2X_MSG_SP, "Bad function state transition request: %d %d\n",
5430                          state, cmd);
5431
5432         return -EINVAL;
5433 }
5434
5435 /**
5436  * bnx2x_func_init_func - performs HW init at function stage
5437  *
5438  * @bp:         device handle
5439  * @drv:
5440  *
5441  * Init HW when the current phase is
5442  * FW_MSG_CODE_DRV_LOAD_FUNCTION: initialize only FUNCTION-only
5443  * HW blocks.
5444  */
5445 static inline int bnx2x_func_init_func(struct bnx2x *bp,
5446                                        const struct bnx2x_func_sp_drv_ops *drv)
5447 {
5448         return drv->init_hw_func(bp);
5449 }
5450
5451 /**
5452  * bnx2x_func_init_port - performs HW init at port stage
5453  *
5454  * @bp:         device handle
5455  * @drv:
5456  *
5457  * Init HW when the current phase is
5458  * FW_MSG_CODE_DRV_LOAD_PORT: initialize PORT-only and
5459  * FUNCTION-only HW blocks.
5460  *
5461  */
5462 static inline int bnx2x_func_init_port(struct bnx2x *bp,
5463                                        const struct bnx2x_func_sp_drv_ops *drv)
5464 {
5465         int rc = drv->init_hw_port(bp);
5466         if (rc)
5467                 return rc;
5468
5469         return bnx2x_func_init_func(bp, drv);
5470 }
5471
5472 /**
5473  * bnx2x_func_init_cmn_chip - performs HW init at chip-common stage
5474  *
5475  * @bp:         device handle
5476  * @drv:
5477  *
5478  * Init HW when the current phase is
5479  * FW_MSG_CODE_DRV_LOAD_COMMON_CHIP: initialize COMMON_CHIP,
5480  * PORT-only and FUNCTION-only HW blocks.
5481  */
5482 static inline int bnx2x_func_init_cmn_chip(struct bnx2x *bp,
5483                                         const struct bnx2x_func_sp_drv_ops *drv)
5484 {
5485         int rc = drv->init_hw_cmn_chip(bp);
5486         if (rc)
5487                 return rc;
5488
5489         return bnx2x_func_init_port(bp, drv);
5490 }
5491
5492 /**
5493  * bnx2x_func_init_cmn - performs HW init at common stage
5494  *
5495  * @bp:         device handle
5496  * @drv:
5497  *
5498  * Init HW when the current phase is
5499  * FW_MSG_CODE_DRV_LOAD_COMMON_CHIP: initialize COMMON,
5500  * PORT-only and FUNCTION-only HW blocks.
5501  */
5502 static inline int bnx2x_func_init_cmn(struct bnx2x *bp,
5503                                       const struct bnx2x_func_sp_drv_ops *drv)
5504 {
5505         int rc = drv->init_hw_cmn(bp);
5506         if (rc)
5507                 return rc;
5508
5509         return bnx2x_func_init_port(bp, drv);
5510 }
5511
5512 static int bnx2x_func_hw_init(struct bnx2x *bp,
5513                               struct bnx2x_func_state_params *params)
5514 {
5515         u32 load_code = params->params.hw_init.load_phase;
5516         struct bnx2x_func_sp_obj *o = params->f_obj;
5517         const struct bnx2x_func_sp_drv_ops *drv = o->drv;
5518         int rc = 0;
5519
5520         DP(BNX2X_MSG_SP, "function %d  load_code %x\n",
5521                          BP_ABS_FUNC(bp), load_code);
5522
5523         /* Prepare buffers for unzipping the FW */
5524         rc = drv->gunzip_init(bp);
5525         if (rc)
5526                 return rc;
5527
5528         /* Prepare FW */
5529         rc = drv->init_fw(bp);
5530         if (rc) {
5531                 BNX2X_ERR("Error loading firmware\n");
5532                 goto init_err;
5533         }
5534
5535         /* Handle the beginning of COMMON_XXX pases separately... */
5536         switch (load_code) {
5537         case FW_MSG_CODE_DRV_LOAD_COMMON_CHIP:
5538                 rc = bnx2x_func_init_cmn_chip(bp, drv);
5539                 if (rc)
5540                         goto init_err;
5541
5542                 break;
5543         case FW_MSG_CODE_DRV_LOAD_COMMON:
5544                 rc = bnx2x_func_init_cmn(bp, drv);
5545                 if (rc)
5546                         goto init_err;
5547
5548                 break;
5549         case FW_MSG_CODE_DRV_LOAD_PORT:
5550                 rc = bnx2x_func_init_port(bp, drv);
5551                 if (rc)
5552                         goto init_err;
5553
5554                 break;
5555         case FW_MSG_CODE_DRV_LOAD_FUNCTION:
5556                 rc = bnx2x_func_init_func(bp, drv);
5557                 if (rc)
5558                         goto init_err;
5559
5560                 break;
5561         default:
5562                 BNX2X_ERR("Unknown load_code (0x%x) from MCP\n", load_code);
5563                 rc = -EINVAL;
5564         }
5565
5566 init_err:
5567         drv->gunzip_end(bp);
5568
5569         /* In case of success, complete the command immediately: no ramrods
5570          * have been sent.
5571          */
5572         if (!rc)
5573                 o->complete_cmd(bp, o, BNX2X_F_CMD_HW_INIT);
5574
5575         return rc;
5576 }
5577
5578 /**
5579  * bnx2x_func_reset_func - reset HW at function stage
5580  *
5581  * @bp:         device handle
5582  * @drv:
5583  *
5584  * Reset HW at FW_MSG_CODE_DRV_UNLOAD_FUNCTION stage: reset only
5585  * FUNCTION-only HW blocks.
5586  */
5587 static inline void bnx2x_func_reset_func(struct bnx2x *bp,
5588                                         const struct bnx2x_func_sp_drv_ops *drv)
5589 {
5590         drv->reset_hw_func(bp);
5591 }
5592
5593 /**
5594  * bnx2x_func_reset_port - reset HW at port stage
5595  *
5596  * @bp:         device handle
5597  * @drv:
5598  *
5599  * Reset HW at FW_MSG_CODE_DRV_UNLOAD_PORT stage: reset
5600  * FUNCTION-only and PORT-only HW blocks.
5601  *
5602  *                 !!!IMPORTANT!!!
5603  *
5604  * It's important to call reset_port before reset_func() as the last thing
5605  * reset_func does is pf_disable() thus disabling PGLUE_B, which
5606  * makes impossible any DMAE transactions.
5607  */
5608 static inline void bnx2x_func_reset_port(struct bnx2x *bp,
5609                                         const struct bnx2x_func_sp_drv_ops *drv)
5610 {
5611         drv->reset_hw_port(bp);
5612         bnx2x_func_reset_func(bp, drv);
5613 }
5614
5615 /**
5616  * bnx2x_func_reset_cmn - reset HW at common stage
5617  *
5618  * @bp:         device handle
5619  * @drv:
5620  *
5621  * Reset HW at FW_MSG_CODE_DRV_UNLOAD_COMMON and
5622  * FW_MSG_CODE_DRV_UNLOAD_COMMON_CHIP stages: reset COMMON,
5623  * COMMON_CHIP, FUNCTION-only and PORT-only HW blocks.
5624  */
5625 static inline void bnx2x_func_reset_cmn(struct bnx2x *bp,
5626                                         const struct bnx2x_func_sp_drv_ops *drv)
5627 {
5628         bnx2x_func_reset_port(bp, drv);
5629         drv->reset_hw_cmn(bp);
5630 }
5631
5632 static inline int bnx2x_func_hw_reset(struct bnx2x *bp,
5633                                       struct bnx2x_func_state_params *params)
5634 {
5635         u32 reset_phase = params->params.hw_reset.reset_phase;
5636         struct bnx2x_func_sp_obj *o = params->f_obj;
5637         const struct bnx2x_func_sp_drv_ops *drv = o->drv;
5638
5639         DP(BNX2X_MSG_SP, "function %d  reset_phase %x\n", BP_ABS_FUNC(bp),
5640                          reset_phase);
5641
5642         switch (reset_phase) {
5643         case FW_MSG_CODE_DRV_UNLOAD_COMMON:
5644                 bnx2x_func_reset_cmn(bp, drv);
5645                 break;
5646         case FW_MSG_CODE_DRV_UNLOAD_PORT:
5647                 bnx2x_func_reset_port(bp, drv);
5648                 break;
5649         case FW_MSG_CODE_DRV_UNLOAD_FUNCTION:
5650                 bnx2x_func_reset_func(bp, drv);
5651                 break;
5652         default:
5653                 BNX2X_ERR("Unknown reset_phase (0x%x) from MCP\n",
5654                            reset_phase);
5655                 break;
5656         }
5657
5658         /* Complete the command immediately: no ramrods have been sent. */
5659         o->complete_cmd(bp, o, BNX2X_F_CMD_HW_RESET);
5660
5661         return 0;
5662 }
5663
5664 static inline int bnx2x_func_send_start(struct bnx2x *bp,
5665                                         struct bnx2x_func_state_params *params)
5666 {
5667         struct bnx2x_func_sp_obj *o = params->f_obj;
5668         struct function_start_data *rdata =
5669                 (struct function_start_data *)o->rdata;
5670         dma_addr_t data_mapping = o->rdata_mapping;
5671         struct bnx2x_func_start_params *start_params = &params->params.start;
5672
5673         memset(rdata, 0, sizeof(*rdata));
5674
5675         /* Fill the ramrod data with provided parameters */
5676         rdata->function_mode    = (u8)start_params->mf_mode;
5677         rdata->sd_vlan_tag      = cpu_to_le16(start_params->sd_vlan_tag);
5678         rdata->path_id          = BP_PATH(bp);
5679         rdata->network_cos_mode = start_params->network_cos_mode;
5680
5681         rdata->vxlan_dst_port   = cpu_to_le16(start_params->vxlan_dst_port);
5682         rdata->geneve_dst_port  = cpu_to_le16(start_params->geneve_dst_port);
5683         rdata->inner_clss_l2gre = start_params->inner_clss_l2gre;
5684         rdata->inner_clss_l2geneve = start_params->inner_clss_l2geneve;
5685         rdata->inner_clss_vxlan = start_params->inner_clss_vxlan;
5686         rdata->inner_rss        = start_params->inner_rss;
5687
5688         rdata->sd_accept_mf_clss_fail = start_params->class_fail;
5689         if (start_params->class_fail_ethtype) {
5690                 rdata->sd_accept_mf_clss_fail_match_ethtype = 1;
5691                 rdata->sd_accept_mf_clss_fail_ethtype =
5692                         cpu_to_le16(start_params->class_fail_ethtype);
5693         }
5694
5695         rdata->sd_vlan_force_pri_flg = start_params->sd_vlan_force_pri;
5696         rdata->sd_vlan_force_pri_val = start_params->sd_vlan_force_pri_val;
5697         if (start_params->sd_vlan_eth_type)
5698                 rdata->sd_vlan_eth_type =
5699                         cpu_to_le16(start_params->sd_vlan_eth_type);
5700         else
5701                 rdata->sd_vlan_eth_type =
5702                         cpu_to_le16(0x8100);
5703
5704         rdata->no_added_tags = start_params->no_added_tags;
5705
5706         rdata->c2s_pri_tt_valid = start_params->c2s_pri_valid;
5707         if (rdata->c2s_pri_tt_valid) {
5708                 memcpy(rdata->c2s_pri_trans_table.val,
5709                        start_params->c2s_pri,
5710                        MAX_VLAN_PRIORITIES);
5711                 rdata->c2s_pri_default = start_params->c2s_pri_default;
5712         }
5713         /* No need for an explicit memory barrier here as long we would
5714          * need to ensure the ordering of writing to the SPQ element
5715          * and updating of the SPQ producer which involves a memory
5716          * read and we will have to put a full memory barrier there
5717          * (inside bnx2x_sp_post()).
5718          */
5719
5720         return bnx2x_sp_post(bp, RAMROD_CMD_ID_COMMON_FUNCTION_START, 0,
5721                              U64_HI(data_mapping),
5722                              U64_LO(data_mapping), NONE_CONNECTION_TYPE);
5723 }
5724
5725 static inline int bnx2x_func_send_switch_update(struct bnx2x *bp,
5726                                         struct bnx2x_func_state_params *params)
5727 {
5728         struct bnx2x_func_sp_obj *o = params->f_obj;
5729         struct function_update_data *rdata =
5730                 (struct function_update_data *)o->rdata;
5731         dma_addr_t data_mapping = o->rdata_mapping;
5732         struct bnx2x_func_switch_update_params *switch_update_params =
5733                 &params->params.switch_update;
5734
5735         memset(rdata, 0, sizeof(*rdata));
5736
5737         /* Fill the ramrod data with provided parameters */
5738         if (test_bit(BNX2X_F_UPDATE_TX_SWITCH_SUSPEND_CHNG,
5739                      &switch_update_params->changes)) {
5740                 rdata->tx_switch_suspend_change_flg = 1;
5741                 rdata->tx_switch_suspend =
5742                         test_bit(BNX2X_F_UPDATE_TX_SWITCH_SUSPEND,
5743                                  &switch_update_params->changes);
5744         }
5745
5746         if (test_bit(BNX2X_F_UPDATE_SD_VLAN_TAG_CHNG,
5747                      &switch_update_params->changes)) {
5748                 rdata->sd_vlan_tag_change_flg = 1;
5749                 rdata->sd_vlan_tag =
5750                         cpu_to_le16(switch_update_params->vlan);
5751         }
5752
5753         if (test_bit(BNX2X_F_UPDATE_SD_VLAN_ETH_TYPE_CHNG,
5754                      &switch_update_params->changes)) {
5755                 rdata->sd_vlan_eth_type_change_flg = 1;
5756                 rdata->sd_vlan_eth_type =
5757                         cpu_to_le16(switch_update_params->vlan_eth_type);
5758         }
5759
5760         if (test_bit(BNX2X_F_UPDATE_VLAN_FORCE_PRIO_CHNG,
5761                      &switch_update_params->changes)) {
5762                 rdata->sd_vlan_force_pri_change_flg = 1;
5763                 if (test_bit(BNX2X_F_UPDATE_VLAN_FORCE_PRIO_FLAG,
5764                              &switch_update_params->changes))
5765                         rdata->sd_vlan_force_pri_flg = 1;
5766                 rdata->sd_vlan_force_pri_flg =
5767                         switch_update_params->vlan_force_prio;
5768         }
5769
5770         if (test_bit(BNX2X_F_UPDATE_TUNNEL_CFG_CHNG,
5771                      &switch_update_params->changes)) {
5772                 rdata->update_tunn_cfg_flg = 1;
5773                 if (test_bit(BNX2X_F_UPDATE_TUNNEL_INNER_CLSS_L2GRE,
5774                              &switch_update_params->changes))
5775                         rdata->inner_clss_l2gre = 1;
5776                 if (test_bit(BNX2X_F_UPDATE_TUNNEL_INNER_CLSS_VXLAN,
5777                              &switch_update_params->changes))
5778                         rdata->inner_clss_vxlan = 1;
5779                 if (test_bit(BNX2X_F_UPDATE_TUNNEL_INNER_CLSS_L2GENEVE,
5780                              &switch_update_params->changes))
5781                         rdata->inner_clss_l2geneve = 1;
5782                 if (test_bit(BNX2X_F_UPDATE_TUNNEL_INNER_RSS,
5783                              &switch_update_params->changes))
5784                         rdata->inner_rss = 1;
5785                 rdata->vxlan_dst_port =
5786                         cpu_to_le16(switch_update_params->vxlan_dst_port);
5787                 rdata->geneve_dst_port =
5788                         cpu_to_le16(switch_update_params->geneve_dst_port);
5789         }
5790
5791         rdata->echo = SWITCH_UPDATE;
5792
5793         /* No need for an explicit memory barrier here as long as we
5794          * ensure the ordering of writing to the SPQ element
5795          * and updating of the SPQ producer which involves a memory
5796          * read. If the memory read is removed we will have to put a
5797          * full memory barrier there (inside bnx2x_sp_post()).
5798          */
5799         return bnx2x_sp_post(bp, RAMROD_CMD_ID_COMMON_FUNCTION_UPDATE, 0,
5800                              U64_HI(data_mapping),
5801                              U64_LO(data_mapping), NONE_CONNECTION_TYPE);
5802 }
5803
5804 static inline int bnx2x_func_send_afex_update(struct bnx2x *bp,
5805                                          struct bnx2x_func_state_params *params)
5806 {
5807         struct bnx2x_func_sp_obj *o = params->f_obj;
5808         struct function_update_data *rdata =
5809                 (struct function_update_data *)o->afex_rdata;
5810         dma_addr_t data_mapping = o->afex_rdata_mapping;
5811         struct bnx2x_func_afex_update_params *afex_update_params =
5812                 &params->params.afex_update;
5813
5814         memset(rdata, 0, sizeof(*rdata));
5815
5816         /* Fill the ramrod data with provided parameters */
5817         rdata->vif_id_change_flg = 1;
5818         rdata->vif_id = cpu_to_le16(afex_update_params->vif_id);
5819         rdata->afex_default_vlan_change_flg = 1;
5820         rdata->afex_default_vlan =
5821                 cpu_to_le16(afex_update_params->afex_default_vlan);
5822         rdata->allowed_priorities_change_flg = 1;
5823         rdata->allowed_priorities = afex_update_params->allowed_priorities;
5824         rdata->echo = AFEX_UPDATE;
5825
5826         /* No need for an explicit memory barrier here as long as we
5827          * ensure the ordering of writing to the SPQ element
5828          * and updating of the SPQ producer which involves a memory
5829          * read. If the memory read is removed we will have to put a
5830          * full memory barrier there (inside bnx2x_sp_post()).
5831          */
5832         DP(BNX2X_MSG_SP,
5833            "afex: sending func_update vif_id 0x%x dvlan 0x%x prio 0x%x\n",
5834            rdata->vif_id,
5835            rdata->afex_default_vlan, rdata->allowed_priorities);
5836
5837         return bnx2x_sp_post(bp, RAMROD_CMD_ID_COMMON_FUNCTION_UPDATE, 0,
5838                              U64_HI(data_mapping),
5839                              U64_LO(data_mapping), NONE_CONNECTION_TYPE);
5840 }
5841
5842 static
5843 inline int bnx2x_func_send_afex_viflists(struct bnx2x *bp,
5844                                          struct bnx2x_func_state_params *params)
5845 {
5846         struct bnx2x_func_sp_obj *o = params->f_obj;
5847         struct afex_vif_list_ramrod_data *rdata =
5848                 (struct afex_vif_list_ramrod_data *)o->afex_rdata;
5849         struct bnx2x_func_afex_viflists_params *afex_vif_params =
5850                 &params->params.afex_viflists;
5851         u64 *p_rdata = (u64 *)rdata;
5852
5853         memset(rdata, 0, sizeof(*rdata));
5854
5855         /* Fill the ramrod data with provided parameters */
5856         rdata->vif_list_index = cpu_to_le16(afex_vif_params->vif_list_index);
5857         rdata->func_bit_map          = afex_vif_params->func_bit_map;
5858         rdata->afex_vif_list_command = afex_vif_params->afex_vif_list_command;
5859         rdata->func_to_clear         = afex_vif_params->func_to_clear;
5860
5861         /* send in echo type of sub command */
5862         rdata->echo = afex_vif_params->afex_vif_list_command;
5863
5864         /*  No need for an explicit memory barrier here as long we would
5865          *  need to ensure the ordering of writing to the SPQ element
5866          *  and updating of the SPQ producer which involves a memory
5867          *  read and we will have to put a full memory barrier there
5868          *  (inside bnx2x_sp_post()).
5869          */
5870
5871         DP(BNX2X_MSG_SP, "afex: ramrod lists, cmd 0x%x index 0x%x func_bit_map 0x%x func_to_clr 0x%x\n",
5872            rdata->afex_vif_list_command, rdata->vif_list_index,
5873            rdata->func_bit_map, rdata->func_to_clear);
5874
5875         /* this ramrod sends data directly and not through DMA mapping */
5876         return bnx2x_sp_post(bp, RAMROD_CMD_ID_COMMON_AFEX_VIF_LISTS, 0,
5877                              U64_HI(*p_rdata), U64_LO(*p_rdata),
5878                              NONE_CONNECTION_TYPE);
5879 }
5880
5881 static inline int bnx2x_func_send_stop(struct bnx2x *bp,
5882                                        struct bnx2x_func_state_params *params)
5883 {
5884         return bnx2x_sp_post(bp, RAMROD_CMD_ID_COMMON_FUNCTION_STOP, 0, 0, 0,
5885                              NONE_CONNECTION_TYPE);
5886 }
5887
5888 static inline int bnx2x_func_send_tx_stop(struct bnx2x *bp,
5889                                        struct bnx2x_func_state_params *params)
5890 {
5891         return bnx2x_sp_post(bp, RAMROD_CMD_ID_COMMON_STOP_TRAFFIC, 0, 0, 0,
5892                              NONE_CONNECTION_TYPE);
5893 }
5894 static inline int bnx2x_func_send_tx_start(struct bnx2x *bp,
5895                                        struct bnx2x_func_state_params *params)
5896 {
5897         struct bnx2x_func_sp_obj *o = params->f_obj;
5898         struct flow_control_configuration *rdata =
5899                 (struct flow_control_configuration *)o->rdata;
5900         dma_addr_t data_mapping = o->rdata_mapping;
5901         struct bnx2x_func_tx_start_params *tx_start_params =
5902                 &params->params.tx_start;
5903         int i;
5904
5905         memset(rdata, 0, sizeof(*rdata));
5906
5907         rdata->dcb_enabled = tx_start_params->dcb_enabled;
5908         rdata->dcb_version = tx_start_params->dcb_version;
5909         rdata->dont_add_pri_0_en = tx_start_params->dont_add_pri_0_en;
5910
5911         for (i = 0; i < ARRAY_SIZE(rdata->traffic_type_to_priority_cos); i++)
5912                 rdata->traffic_type_to_priority_cos[i] =
5913                         tx_start_params->traffic_type_to_priority_cos[i];
5914
5915         for (i = 0; i < MAX_TRAFFIC_TYPES; i++)
5916                 rdata->dcb_outer_pri[i] = tx_start_params->dcb_outer_pri[i];
5917         /* No need for an explicit memory barrier here as long as we
5918          * ensure the ordering of writing to the SPQ element
5919          * and updating of the SPQ producer which involves a memory
5920          * read. If the memory read is removed we will have to put a
5921          * full memory barrier there (inside bnx2x_sp_post()).
5922          */
5923         return bnx2x_sp_post(bp, RAMROD_CMD_ID_COMMON_START_TRAFFIC, 0,
5924                              U64_HI(data_mapping),
5925                              U64_LO(data_mapping), NONE_CONNECTION_TYPE);
5926 }
5927
5928 static inline
5929 int bnx2x_func_send_set_timesync(struct bnx2x *bp,
5930                                  struct bnx2x_func_state_params *params)
5931 {
5932         struct bnx2x_func_sp_obj *o = params->f_obj;
5933         struct set_timesync_ramrod_data *rdata =
5934                 (struct set_timesync_ramrod_data *)o->rdata;
5935         dma_addr_t data_mapping = o->rdata_mapping;
5936         struct bnx2x_func_set_timesync_params *set_timesync_params =
5937                 &params->params.set_timesync;
5938
5939         memset(rdata, 0, sizeof(*rdata));
5940
5941         /* Fill the ramrod data with provided parameters */
5942         rdata->drift_adjust_cmd = set_timesync_params->drift_adjust_cmd;
5943         rdata->offset_cmd = set_timesync_params->offset_cmd;
5944         rdata->add_sub_drift_adjust_value =
5945                 set_timesync_params->add_sub_drift_adjust_value;
5946         rdata->drift_adjust_value = set_timesync_params->drift_adjust_value;
5947         rdata->drift_adjust_period = set_timesync_params->drift_adjust_period;
5948         rdata->offset_delta.lo =
5949                 cpu_to_le32(U64_LO(set_timesync_params->offset_delta));
5950         rdata->offset_delta.hi =
5951                 cpu_to_le32(U64_HI(set_timesync_params->offset_delta));
5952
5953         DP(BNX2X_MSG_SP, "Set timesync command params: drift_cmd = %d, offset_cmd = %d, add_sub_drift = %d, drift_val = %d, drift_period = %d, offset_lo = %d, offset_hi = %d\n",
5954            rdata->drift_adjust_cmd, rdata->offset_cmd,
5955            rdata->add_sub_drift_adjust_value, rdata->drift_adjust_value,
5956            rdata->drift_adjust_period, rdata->offset_delta.lo,
5957            rdata->offset_delta.hi);
5958
5959         return bnx2x_sp_post(bp, RAMROD_CMD_ID_COMMON_SET_TIMESYNC, 0,
5960                              U64_HI(data_mapping),
5961                              U64_LO(data_mapping), NONE_CONNECTION_TYPE);
5962 }
5963
5964 static int bnx2x_func_send_cmd(struct bnx2x *bp,
5965                                struct bnx2x_func_state_params *params)
5966 {
5967         switch (params->cmd) {
5968         case BNX2X_F_CMD_HW_INIT:
5969                 return bnx2x_func_hw_init(bp, params);
5970         case BNX2X_F_CMD_START:
5971                 return bnx2x_func_send_start(bp, params);
5972         case BNX2X_F_CMD_STOP:
5973                 return bnx2x_func_send_stop(bp, params);
5974         case BNX2X_F_CMD_HW_RESET:
5975                 return bnx2x_func_hw_reset(bp, params);
5976         case BNX2X_F_CMD_AFEX_UPDATE:
5977                 return bnx2x_func_send_afex_update(bp, params);
5978         case BNX2X_F_CMD_AFEX_VIFLISTS:
5979                 return bnx2x_func_send_afex_viflists(bp, params);
5980         case BNX2X_F_CMD_TX_STOP:
5981                 return bnx2x_func_send_tx_stop(bp, params);
5982         case BNX2X_F_CMD_TX_START:
5983                 return bnx2x_func_send_tx_start(bp, params);
5984         case BNX2X_F_CMD_SWITCH_UPDATE:
5985                 return bnx2x_func_send_switch_update(bp, params);
5986         case BNX2X_F_CMD_SET_TIMESYNC:
5987                 return bnx2x_func_send_set_timesync(bp, params);
5988         default:
5989                 BNX2X_ERR("Unknown command: %d\n", params->cmd);
5990                 return -EINVAL;
5991         }
5992 }
5993
5994 void bnx2x_init_func_obj(struct bnx2x *bp,
5995                          struct bnx2x_func_sp_obj *obj,
5996                          void *rdata, dma_addr_t rdata_mapping,
5997                          void *afex_rdata, dma_addr_t afex_rdata_mapping,
5998                          struct bnx2x_func_sp_drv_ops *drv_iface)
5999 {
6000         memset(obj, 0, sizeof(*obj));
6001
6002         mutex_init(&obj->one_pending_mutex);
6003
6004         obj->rdata = rdata;
6005         obj->rdata_mapping = rdata_mapping;
6006         obj->afex_rdata = afex_rdata;
6007         obj->afex_rdata_mapping = afex_rdata_mapping;
6008         obj->send_cmd = bnx2x_func_send_cmd;
6009         obj->check_transition = bnx2x_func_chk_transition;
6010         obj->complete_cmd = bnx2x_func_comp_cmd;
6011         obj->wait_comp = bnx2x_func_wait_comp;
6012
6013         obj->drv = drv_iface;
6014 }
6015
6016 /**
6017  * bnx2x_func_state_change - perform Function state change transition
6018  *
6019  * @bp:         device handle
6020  * @params:     parameters to perform the transaction
6021  *
6022  * returns 0 in case of successfully completed transition,
6023  *         negative error code in case of failure, positive
6024  *         (EBUSY) value if there is a completion to that is
6025  *         still pending (possible only if RAMROD_COMP_WAIT is
6026  *         not set in params->ramrod_flags for asynchronous
6027  *         commands).
6028  */
6029 int bnx2x_func_state_change(struct bnx2x *bp,
6030                             struct bnx2x_func_state_params *params)
6031 {
6032         struct bnx2x_func_sp_obj *o = params->f_obj;
6033         int rc, cnt = 300;
6034         enum bnx2x_func_cmd cmd = params->cmd;
6035         unsigned long *pending = &o->pending;
6036
6037         mutex_lock(&o->one_pending_mutex);
6038
6039         /* Check that the requested transition is legal */
6040         rc = o->check_transition(bp, o, params);
6041         if ((rc == -EBUSY) &&
6042             (test_bit(RAMROD_RETRY, &params->ramrod_flags))) {
6043                 while ((rc == -EBUSY) && (--cnt > 0)) {
6044                         mutex_unlock(&o->one_pending_mutex);
6045                         msleep(10);
6046                         mutex_lock(&o->one_pending_mutex);
6047                         rc = o->check_transition(bp, o, params);
6048                 }
6049                 if (rc == -EBUSY) {
6050                         mutex_unlock(&o->one_pending_mutex);
6051                         BNX2X_ERR("timeout waiting for previous ramrod completion\n");
6052                         return rc;
6053                 }
6054         } else if (rc) {
6055                 mutex_unlock(&o->one_pending_mutex);
6056                 return rc;
6057         }
6058
6059         /* Set "pending" bit */
6060         set_bit(cmd, pending);
6061
6062         /* Don't send a command if only driver cleanup was requested */
6063         if (test_bit(RAMROD_DRV_CLR_ONLY, &params->ramrod_flags)) {
6064                 bnx2x_func_state_change_comp(bp, o, cmd);
6065                 mutex_unlock(&o->one_pending_mutex);
6066         } else {
6067                 /* Send a ramrod */
6068                 rc = o->send_cmd(bp, params);
6069
6070                 mutex_unlock(&o->one_pending_mutex);
6071
6072                 if (rc) {
6073                         o->next_state = BNX2X_F_STATE_MAX;
6074                         clear_bit(cmd, pending);
6075                         smp_mb__after_atomic();
6076                         return rc;
6077                 }
6078
6079                 if (test_bit(RAMROD_COMP_WAIT, &params->ramrod_flags)) {
6080                         rc = o->wait_comp(bp, o, cmd);
6081                         if (rc)
6082                                 return rc;
6083
6084                         return 0;
6085                 }
6086         }
6087
6088         return !!test_bit(cmd, pending);
6089 }