1 /* bnx2x_main.c: QLogic Everest network driver.
3 * Copyright (c) 2007-2013 Broadcom Corporation
4 * Copyright (c) 2014 QLogic Corporation
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation.
11 * Maintained by: Ariel Elior <ariel.elior@qlogic.com>
12 * Written by: Eliezer Tamir
13 * Based on code from Michael Chan's bnx2 driver
14 * UDP CSUM errata workaround by Arik Gendelman
15 * Slowpath and fastpath rework by Vladislav Zolotarov
16 * Statistics and Link management by Yitchak Gertner
20 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
22 #include <linux/module.h>
23 #include <linux/moduleparam.h>
24 #include <linux/kernel.h>
25 #include <linux/device.h> /* for dev_info() */
26 #include <linux/timer.h>
27 #include <linux/errno.h>
28 #include <linux/ioport.h>
29 #include <linux/slab.h>
30 #include <linux/interrupt.h>
31 #include <linux/pci.h>
32 #include <linux/aer.h>
33 #include <linux/init.h>
34 #include <linux/netdevice.h>
35 #include <linux/etherdevice.h>
36 #include <linux/skbuff.h>
37 #include <linux/dma-mapping.h>
38 #include <linux/bitops.h>
39 #include <linux/irq.h>
40 #include <linux/delay.h>
41 #include <asm/byteorder.h>
42 #include <linux/time.h>
43 #include <linux/ethtool.h>
44 #include <linux/mii.h>
45 #include <linux/if_vlan.h>
46 #include <linux/crash_dump.h>
50 #include <net/vxlan.h>
51 #include <net/checksum.h>
52 #include <net/ip6_checksum.h>
53 #include <linux/workqueue.h>
54 #include <linux/crc32.h>
55 #include <linux/crc32c.h>
56 #include <linux/prefetch.h>
57 #include <linux/zlib.h>
59 #include <linux/semaphore.h>
60 #include <linux/stringify.h>
61 #include <linux/vmalloc.h>
64 #include "bnx2x_init.h"
65 #include "bnx2x_init_ops.h"
66 #include "bnx2x_cmn.h"
67 #include "bnx2x_vfpf.h"
68 #include "bnx2x_dcb.h"
70 #include <linux/firmware.h>
71 #include "bnx2x_fw_file_hdr.h"
73 #define FW_FILE_VERSION \
74 __stringify(BCM_5710_FW_MAJOR_VERSION) "." \
75 __stringify(BCM_5710_FW_MINOR_VERSION) "." \
76 __stringify(BCM_5710_FW_REVISION_VERSION) "." \
77 __stringify(BCM_5710_FW_ENGINEERING_VERSION)
78 #define FW_FILE_NAME_E1 "bnx2x/bnx2x-e1-" FW_FILE_VERSION ".fw"
79 #define FW_FILE_NAME_E1H "bnx2x/bnx2x-e1h-" FW_FILE_VERSION ".fw"
80 #define FW_FILE_NAME_E2 "bnx2x/bnx2x-e2-" FW_FILE_VERSION ".fw"
82 /* Time in jiffies before concluding the transmitter is hung */
83 #define TX_TIMEOUT (5*HZ)
85 static char version[] =
86 "QLogic 5771x/578xx 10/20-Gigabit Ethernet Driver "
87 DRV_MODULE_NAME " " DRV_MODULE_VERSION " (" DRV_MODULE_RELDATE ")\n";
89 MODULE_AUTHOR("Eliezer Tamir");
90 MODULE_DESCRIPTION("QLogic "
91 "BCM57710/57711/57711E/"
92 "57712/57712_MF/57800/57800_MF/57810/57810_MF/"
93 "57840/57840_MF Driver");
94 MODULE_LICENSE("GPL");
95 MODULE_VERSION(DRV_MODULE_VERSION);
96 MODULE_FIRMWARE(FW_FILE_NAME_E1);
97 MODULE_FIRMWARE(FW_FILE_NAME_E1H);
98 MODULE_FIRMWARE(FW_FILE_NAME_E2);
100 int bnx2x_num_queues;
101 module_param_named(num_queues, bnx2x_num_queues, int, S_IRUGO);
102 MODULE_PARM_DESC(num_queues,
103 " Set number of queues (default is as a number of CPUs)");
105 static int disable_tpa;
106 module_param(disable_tpa, int, S_IRUGO);
107 MODULE_PARM_DESC(disable_tpa, " Disable the TPA (LRO) feature");
110 module_param(int_mode, int, S_IRUGO);
111 MODULE_PARM_DESC(int_mode, " Force interrupt mode other than MSI-X "
114 static int dropless_fc;
115 module_param(dropless_fc, int, S_IRUGO);
116 MODULE_PARM_DESC(dropless_fc, " Pause on exhausted host ring");
118 static int mrrs = -1;
119 module_param(mrrs, int, S_IRUGO);
120 MODULE_PARM_DESC(mrrs, " Force Max Read Req Size (0..3) (for debug)");
123 module_param(debug, int, S_IRUGO);
124 MODULE_PARM_DESC(debug, " Default debug msglevel");
126 static struct workqueue_struct *bnx2x_wq;
127 struct workqueue_struct *bnx2x_iov_wq;
129 struct bnx2x_mac_vals {
140 enum bnx2x_board_type {
164 /* indexed by board_type, above */
168 [BCM57710] = { "QLogic BCM57710 10 Gigabit PCIe [Everest]" },
169 [BCM57711] = { "QLogic BCM57711 10 Gigabit PCIe" },
170 [BCM57711E] = { "QLogic BCM57711E 10 Gigabit PCIe" },
171 [BCM57712] = { "QLogic BCM57712 10 Gigabit Ethernet" },
172 [BCM57712_MF] = { "QLogic BCM57712 10 Gigabit Ethernet Multi Function" },
173 [BCM57712_VF] = { "QLogic BCM57712 10 Gigabit Ethernet Virtual Function" },
174 [BCM57800] = { "QLogic BCM57800 10 Gigabit Ethernet" },
175 [BCM57800_MF] = { "QLogic BCM57800 10 Gigabit Ethernet Multi Function" },
176 [BCM57800_VF] = { "QLogic BCM57800 10 Gigabit Ethernet Virtual Function" },
177 [BCM57810] = { "QLogic BCM57810 10 Gigabit Ethernet" },
178 [BCM57810_MF] = { "QLogic BCM57810 10 Gigabit Ethernet Multi Function" },
179 [BCM57810_VF] = { "QLogic BCM57810 10 Gigabit Ethernet Virtual Function" },
180 [BCM57840_4_10] = { "QLogic BCM57840 10 Gigabit Ethernet" },
181 [BCM57840_2_20] = { "QLogic BCM57840 20 Gigabit Ethernet" },
182 [BCM57840_MF] = { "QLogic BCM57840 10/20 Gigabit Ethernet Multi Function" },
183 [BCM57840_VF] = { "QLogic BCM57840 10/20 Gigabit Ethernet Virtual Function" },
184 [BCM57811] = { "QLogic BCM57811 10 Gigabit Ethernet" },
185 [BCM57811_MF] = { "QLogic BCM57811 10 Gigabit Ethernet Multi Function" },
186 [BCM57840_O] = { "QLogic BCM57840 10/20 Gigabit Ethernet" },
187 [BCM57840_MFO] = { "QLogic BCM57840 10/20 Gigabit Ethernet Multi Function" },
188 [BCM57811_VF] = { "QLogic BCM57840 10/20 Gigabit Ethernet Virtual Function" }
191 #ifndef PCI_DEVICE_ID_NX2_57710
192 #define PCI_DEVICE_ID_NX2_57710 CHIP_NUM_57710
194 #ifndef PCI_DEVICE_ID_NX2_57711
195 #define PCI_DEVICE_ID_NX2_57711 CHIP_NUM_57711
197 #ifndef PCI_DEVICE_ID_NX2_57711E
198 #define PCI_DEVICE_ID_NX2_57711E CHIP_NUM_57711E
200 #ifndef PCI_DEVICE_ID_NX2_57712
201 #define PCI_DEVICE_ID_NX2_57712 CHIP_NUM_57712
203 #ifndef PCI_DEVICE_ID_NX2_57712_MF
204 #define PCI_DEVICE_ID_NX2_57712_MF CHIP_NUM_57712_MF
206 #ifndef PCI_DEVICE_ID_NX2_57712_VF
207 #define PCI_DEVICE_ID_NX2_57712_VF CHIP_NUM_57712_VF
209 #ifndef PCI_DEVICE_ID_NX2_57800
210 #define PCI_DEVICE_ID_NX2_57800 CHIP_NUM_57800
212 #ifndef PCI_DEVICE_ID_NX2_57800_MF
213 #define PCI_DEVICE_ID_NX2_57800_MF CHIP_NUM_57800_MF
215 #ifndef PCI_DEVICE_ID_NX2_57800_VF
216 #define PCI_DEVICE_ID_NX2_57800_VF CHIP_NUM_57800_VF
218 #ifndef PCI_DEVICE_ID_NX2_57810
219 #define PCI_DEVICE_ID_NX2_57810 CHIP_NUM_57810
221 #ifndef PCI_DEVICE_ID_NX2_57810_MF
222 #define PCI_DEVICE_ID_NX2_57810_MF CHIP_NUM_57810_MF
224 #ifndef PCI_DEVICE_ID_NX2_57840_O
225 #define PCI_DEVICE_ID_NX2_57840_O CHIP_NUM_57840_OBSOLETE
227 #ifndef PCI_DEVICE_ID_NX2_57810_VF
228 #define PCI_DEVICE_ID_NX2_57810_VF CHIP_NUM_57810_VF
230 #ifndef PCI_DEVICE_ID_NX2_57840_4_10
231 #define PCI_DEVICE_ID_NX2_57840_4_10 CHIP_NUM_57840_4_10
233 #ifndef PCI_DEVICE_ID_NX2_57840_2_20
234 #define PCI_DEVICE_ID_NX2_57840_2_20 CHIP_NUM_57840_2_20
236 #ifndef PCI_DEVICE_ID_NX2_57840_MFO
237 #define PCI_DEVICE_ID_NX2_57840_MFO CHIP_NUM_57840_MF_OBSOLETE
239 #ifndef PCI_DEVICE_ID_NX2_57840_MF
240 #define PCI_DEVICE_ID_NX2_57840_MF CHIP_NUM_57840_MF
242 #ifndef PCI_DEVICE_ID_NX2_57840_VF
243 #define PCI_DEVICE_ID_NX2_57840_VF CHIP_NUM_57840_VF
245 #ifndef PCI_DEVICE_ID_NX2_57811
246 #define PCI_DEVICE_ID_NX2_57811 CHIP_NUM_57811
248 #ifndef PCI_DEVICE_ID_NX2_57811_MF
249 #define PCI_DEVICE_ID_NX2_57811_MF CHIP_NUM_57811_MF
251 #ifndef PCI_DEVICE_ID_NX2_57811_VF
252 #define PCI_DEVICE_ID_NX2_57811_VF CHIP_NUM_57811_VF
255 static const struct pci_device_id bnx2x_pci_tbl[] = {
256 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57710), BCM57710 },
257 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57711), BCM57711 },
258 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57711E), BCM57711E },
259 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57712), BCM57712 },
260 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57712_MF), BCM57712_MF },
261 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57712_VF), BCM57712_VF },
262 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57800), BCM57800 },
263 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57800_MF), BCM57800_MF },
264 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57800_VF), BCM57800_VF },
265 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57810), BCM57810 },
266 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57810_MF), BCM57810_MF },
267 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57840_O), BCM57840_O },
268 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57840_4_10), BCM57840_4_10 },
269 { PCI_VDEVICE(QLOGIC, PCI_DEVICE_ID_NX2_57840_4_10), BCM57840_4_10 },
270 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57840_2_20), BCM57840_2_20 },
271 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57810_VF), BCM57810_VF },
272 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57840_MFO), BCM57840_MFO },
273 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57840_MF), BCM57840_MF },
274 { PCI_VDEVICE(QLOGIC, PCI_DEVICE_ID_NX2_57840_MF), BCM57840_MF },
275 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57840_VF), BCM57840_VF },
276 { PCI_VDEVICE(QLOGIC, PCI_DEVICE_ID_NX2_57840_VF), BCM57840_VF },
277 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57811), BCM57811 },
278 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57811_MF), BCM57811_MF },
279 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57811_VF), BCM57811_VF },
283 MODULE_DEVICE_TABLE(pci, bnx2x_pci_tbl);
285 /* Global resources for unloading a previously loaded device */
286 #define BNX2X_PREV_WAIT_NEEDED 1
287 static DEFINE_SEMAPHORE(bnx2x_prev_sem);
288 static LIST_HEAD(bnx2x_prev_list);
290 /* Forward declaration */
291 static struct cnic_eth_dev *bnx2x_cnic_probe(struct net_device *dev);
292 static u32 bnx2x_rx_ustorm_prods_offset(struct bnx2x_fastpath *fp);
293 static int bnx2x_set_storm_rx_mode(struct bnx2x *bp);
295 /****************************************************************************
296 * General service functions
297 ****************************************************************************/
299 static int bnx2x_hwtstamp_ioctl(struct bnx2x *bp, struct ifreq *ifr);
301 static void __storm_memset_dma_mapping(struct bnx2x *bp,
302 u32 addr, dma_addr_t mapping)
304 REG_WR(bp, addr, U64_LO(mapping));
305 REG_WR(bp, addr + 4, U64_HI(mapping));
308 static void storm_memset_spq_addr(struct bnx2x *bp,
309 dma_addr_t mapping, u16 abs_fid)
311 u32 addr = XSEM_REG_FAST_MEMORY +
312 XSTORM_SPQ_PAGE_BASE_OFFSET(abs_fid);
314 __storm_memset_dma_mapping(bp, addr, mapping);
317 static void storm_memset_vf_to_pf(struct bnx2x *bp, u16 abs_fid,
320 REG_WR8(bp, BAR_XSTRORM_INTMEM + XSTORM_VF_TO_PF_OFFSET(abs_fid),
322 REG_WR8(bp, BAR_CSTRORM_INTMEM + CSTORM_VF_TO_PF_OFFSET(abs_fid),
324 REG_WR8(bp, BAR_TSTRORM_INTMEM + TSTORM_VF_TO_PF_OFFSET(abs_fid),
326 REG_WR8(bp, BAR_USTRORM_INTMEM + USTORM_VF_TO_PF_OFFSET(abs_fid),
330 static void storm_memset_func_en(struct bnx2x *bp, u16 abs_fid,
333 REG_WR8(bp, BAR_XSTRORM_INTMEM + XSTORM_FUNC_EN_OFFSET(abs_fid),
335 REG_WR8(bp, BAR_CSTRORM_INTMEM + CSTORM_FUNC_EN_OFFSET(abs_fid),
337 REG_WR8(bp, BAR_TSTRORM_INTMEM + TSTORM_FUNC_EN_OFFSET(abs_fid),
339 REG_WR8(bp, BAR_USTRORM_INTMEM + USTORM_FUNC_EN_OFFSET(abs_fid),
343 static void storm_memset_eq_data(struct bnx2x *bp,
344 struct event_ring_data *eq_data,
347 size_t size = sizeof(struct event_ring_data);
349 u32 addr = BAR_CSTRORM_INTMEM + CSTORM_EVENT_RING_DATA_OFFSET(pfid);
351 __storm_memset_struct(bp, addr, size, (u32 *)eq_data);
354 static void storm_memset_eq_prod(struct bnx2x *bp, u16 eq_prod,
357 u32 addr = BAR_CSTRORM_INTMEM + CSTORM_EVENT_RING_PROD_OFFSET(pfid);
358 REG_WR16(bp, addr, eq_prod);
362 * locking is done by mcp
364 static void bnx2x_reg_wr_ind(struct bnx2x *bp, u32 addr, u32 val)
366 pci_write_config_dword(bp->pdev, PCICFG_GRC_ADDRESS, addr);
367 pci_write_config_dword(bp->pdev, PCICFG_GRC_DATA, val);
368 pci_write_config_dword(bp->pdev, PCICFG_GRC_ADDRESS,
369 PCICFG_VENDOR_ID_OFFSET);
372 static u32 bnx2x_reg_rd_ind(struct bnx2x *bp, u32 addr)
376 pci_write_config_dword(bp->pdev, PCICFG_GRC_ADDRESS, addr);
377 pci_read_config_dword(bp->pdev, PCICFG_GRC_DATA, &val);
378 pci_write_config_dword(bp->pdev, PCICFG_GRC_ADDRESS,
379 PCICFG_VENDOR_ID_OFFSET);
384 #define DMAE_DP_SRC_GRC "grc src_addr [%08x]"
385 #define DMAE_DP_SRC_PCI "pci src_addr [%x:%08x]"
386 #define DMAE_DP_DST_GRC "grc dst_addr [%08x]"
387 #define DMAE_DP_DST_PCI "pci dst_addr [%x:%08x]"
388 #define DMAE_DP_DST_NONE "dst_addr [none]"
390 static void bnx2x_dp_dmae(struct bnx2x *bp,
391 struct dmae_command *dmae, int msglvl)
393 u32 src_type = dmae->opcode & DMAE_COMMAND_SRC;
396 switch (dmae->opcode & DMAE_COMMAND_DST) {
397 case DMAE_CMD_DST_PCI:
398 if (src_type == DMAE_CMD_SRC_PCI)
399 DP(msglvl, "DMAE: opcode 0x%08x\n"
400 "src [%x:%08x], len [%d*4], dst [%x:%08x]\n"
401 "comp_addr [%x:%08x], comp_val 0x%08x\n",
402 dmae->opcode, dmae->src_addr_hi, dmae->src_addr_lo,
403 dmae->len, dmae->dst_addr_hi, dmae->dst_addr_lo,
404 dmae->comp_addr_hi, dmae->comp_addr_lo,
407 DP(msglvl, "DMAE: opcode 0x%08x\n"
408 "src [%08x], len [%d*4], dst [%x:%08x]\n"
409 "comp_addr [%x:%08x], comp_val 0x%08x\n",
410 dmae->opcode, dmae->src_addr_lo >> 2,
411 dmae->len, dmae->dst_addr_hi, dmae->dst_addr_lo,
412 dmae->comp_addr_hi, dmae->comp_addr_lo,
415 case DMAE_CMD_DST_GRC:
416 if (src_type == DMAE_CMD_SRC_PCI)
417 DP(msglvl, "DMAE: opcode 0x%08x\n"
418 "src [%x:%08x], len [%d*4], dst_addr [%08x]\n"
419 "comp_addr [%x:%08x], comp_val 0x%08x\n",
420 dmae->opcode, dmae->src_addr_hi, dmae->src_addr_lo,
421 dmae->len, dmae->dst_addr_lo >> 2,
422 dmae->comp_addr_hi, dmae->comp_addr_lo,
425 DP(msglvl, "DMAE: opcode 0x%08x\n"
426 "src [%08x], len [%d*4], dst [%08x]\n"
427 "comp_addr [%x:%08x], comp_val 0x%08x\n",
428 dmae->opcode, dmae->src_addr_lo >> 2,
429 dmae->len, dmae->dst_addr_lo >> 2,
430 dmae->comp_addr_hi, dmae->comp_addr_lo,
434 if (src_type == DMAE_CMD_SRC_PCI)
435 DP(msglvl, "DMAE: opcode 0x%08x\n"
436 "src_addr [%x:%08x] len [%d * 4] dst_addr [none]\n"
437 "comp_addr [%x:%08x] comp_val 0x%08x\n",
438 dmae->opcode, dmae->src_addr_hi, dmae->src_addr_lo,
439 dmae->len, dmae->comp_addr_hi, dmae->comp_addr_lo,
442 DP(msglvl, "DMAE: opcode 0x%08x\n"
443 "src_addr [%08x] len [%d * 4] dst_addr [none]\n"
444 "comp_addr [%x:%08x] comp_val 0x%08x\n",
445 dmae->opcode, dmae->src_addr_lo >> 2,
446 dmae->len, dmae->comp_addr_hi, dmae->comp_addr_lo,
451 for (i = 0; i < (sizeof(struct dmae_command)/4); i++)
452 DP(msglvl, "DMAE RAW [%02d]: 0x%08x\n",
453 i, *(((u32 *)dmae) + i));
456 /* copy command into DMAE command memory and set DMAE command go */
457 void bnx2x_post_dmae(struct bnx2x *bp, struct dmae_command *dmae, int idx)
462 cmd_offset = (DMAE_REG_CMD_MEM + sizeof(struct dmae_command) * idx);
463 for (i = 0; i < (sizeof(struct dmae_command)/4); i++) {
464 REG_WR(bp, cmd_offset + i*4, *(((u32 *)dmae) + i));
466 REG_WR(bp, dmae_reg_go_c[idx], 1);
469 u32 bnx2x_dmae_opcode_add_comp(u32 opcode, u8 comp_type)
471 return opcode | ((comp_type << DMAE_COMMAND_C_DST_SHIFT) |
475 u32 bnx2x_dmae_opcode_clr_src_reset(u32 opcode)
477 return opcode & ~DMAE_CMD_SRC_RESET;
480 u32 bnx2x_dmae_opcode(struct bnx2x *bp, u8 src_type, u8 dst_type,
481 bool with_comp, u8 comp_type)
485 opcode |= ((src_type << DMAE_COMMAND_SRC_SHIFT) |
486 (dst_type << DMAE_COMMAND_DST_SHIFT));
488 opcode |= (DMAE_CMD_SRC_RESET | DMAE_CMD_DST_RESET);
490 opcode |= (BP_PORT(bp) ? DMAE_CMD_PORT_1 : DMAE_CMD_PORT_0);
491 opcode |= ((BP_VN(bp) << DMAE_CMD_E1HVN_SHIFT) |
492 (BP_VN(bp) << DMAE_COMMAND_DST_VN_SHIFT));
493 opcode |= (DMAE_COM_SET_ERR << DMAE_COMMAND_ERR_POLICY_SHIFT);
496 opcode |= DMAE_CMD_ENDIANITY_B_DW_SWAP;
498 opcode |= DMAE_CMD_ENDIANITY_DW_SWAP;
501 opcode = bnx2x_dmae_opcode_add_comp(opcode, comp_type);
505 void bnx2x_prep_dmae_with_comp(struct bnx2x *bp,
506 struct dmae_command *dmae,
507 u8 src_type, u8 dst_type)
509 memset(dmae, 0, sizeof(struct dmae_command));
512 dmae->opcode = bnx2x_dmae_opcode(bp, src_type, dst_type,
513 true, DMAE_COMP_PCI);
515 /* fill in the completion parameters */
516 dmae->comp_addr_lo = U64_LO(bnx2x_sp_mapping(bp, wb_comp));
517 dmae->comp_addr_hi = U64_HI(bnx2x_sp_mapping(bp, wb_comp));
518 dmae->comp_val = DMAE_COMP_VAL;
521 /* issue a dmae command over the init-channel and wait for completion */
522 int bnx2x_issue_dmae_with_comp(struct bnx2x *bp, struct dmae_command *dmae,
525 int cnt = CHIP_REV_IS_SLOW(bp) ? (400000) : 4000;
528 bnx2x_dp_dmae(bp, dmae, BNX2X_MSG_DMAE);
530 /* Lock the dmae channel. Disable BHs to prevent a dead-lock
531 * as long as this code is called both from syscall context and
532 * from ndo_set_rx_mode() flow that may be called from BH.
535 spin_lock_bh(&bp->dmae_lock);
537 /* reset completion */
540 /* post the command on the channel used for initializations */
541 bnx2x_post_dmae(bp, dmae, INIT_DMAE_C(bp));
543 /* wait for completion */
545 while ((*comp & ~DMAE_PCI_ERR_FLAG) != DMAE_COMP_VAL) {
548 (bp->recovery_state != BNX2X_RECOVERY_DONE &&
549 bp->recovery_state != BNX2X_RECOVERY_NIC_LOADING)) {
550 BNX2X_ERR("DMAE timeout!\n");
557 if (*comp & DMAE_PCI_ERR_FLAG) {
558 BNX2X_ERR("DMAE PCI error!\n");
564 spin_unlock_bh(&bp->dmae_lock);
569 void bnx2x_write_dmae(struct bnx2x *bp, dma_addr_t dma_addr, u32 dst_addr,
573 struct dmae_command dmae;
575 if (!bp->dmae_ready) {
576 u32 *data = bnx2x_sp(bp, wb_data[0]);
579 bnx2x_init_ind_wr(bp, dst_addr, data, len32);
581 bnx2x_init_str_wr(bp, dst_addr, data, len32);
585 /* set opcode and fixed command fields */
586 bnx2x_prep_dmae_with_comp(bp, &dmae, DMAE_SRC_PCI, DMAE_DST_GRC);
588 /* fill in addresses and len */
589 dmae.src_addr_lo = U64_LO(dma_addr);
590 dmae.src_addr_hi = U64_HI(dma_addr);
591 dmae.dst_addr_lo = dst_addr >> 2;
592 dmae.dst_addr_hi = 0;
595 /* issue the command and wait for completion */
596 rc = bnx2x_issue_dmae_with_comp(bp, &dmae, bnx2x_sp(bp, wb_comp));
598 BNX2X_ERR("DMAE returned failure %d\n", rc);
599 #ifdef BNX2X_STOP_ON_ERROR
605 void bnx2x_read_dmae(struct bnx2x *bp, u32 src_addr, u32 len32)
608 struct dmae_command dmae;
610 if (!bp->dmae_ready) {
611 u32 *data = bnx2x_sp(bp, wb_data[0]);
615 for (i = 0; i < len32; i++)
616 data[i] = bnx2x_reg_rd_ind(bp, src_addr + i*4);
618 for (i = 0; i < len32; i++)
619 data[i] = REG_RD(bp, src_addr + i*4);
624 /* set opcode and fixed command fields */
625 bnx2x_prep_dmae_with_comp(bp, &dmae, DMAE_SRC_GRC, DMAE_DST_PCI);
627 /* fill in addresses and len */
628 dmae.src_addr_lo = src_addr >> 2;
629 dmae.src_addr_hi = 0;
630 dmae.dst_addr_lo = U64_LO(bnx2x_sp_mapping(bp, wb_data));
631 dmae.dst_addr_hi = U64_HI(bnx2x_sp_mapping(bp, wb_data));
634 /* issue the command and wait for completion */
635 rc = bnx2x_issue_dmae_with_comp(bp, &dmae, bnx2x_sp(bp, wb_comp));
637 BNX2X_ERR("DMAE returned failure %d\n", rc);
638 #ifdef BNX2X_STOP_ON_ERROR
644 static void bnx2x_write_dmae_phys_len(struct bnx2x *bp, dma_addr_t phys_addr,
647 int dmae_wr_max = DMAE_LEN32_WR_MAX(bp);
650 while (len > dmae_wr_max) {
651 bnx2x_write_dmae(bp, phys_addr + offset,
652 addr + offset, dmae_wr_max);
653 offset += dmae_wr_max * 4;
657 bnx2x_write_dmae(bp, phys_addr + offset, addr + offset, len);
669 #define REGS_IN_ENTRY 4
671 static inline int bnx2x_get_assert_list_entry(struct bnx2x *bp,
677 return XSTORM_ASSERT_LIST_OFFSET(entry);
679 return TSTORM_ASSERT_LIST_OFFSET(entry);
681 return CSTORM_ASSERT_LIST_OFFSET(entry);
683 return USTORM_ASSERT_LIST_OFFSET(entry);
686 BNX2X_ERR("unknown storm\n");
691 static int bnx2x_mc_assert(struct bnx2x *bp)
696 u32 regs[REGS_IN_ENTRY];
697 u32 bar_storm_intmem[STORMS_NUM] = {
703 u32 storm_assert_list_index[STORMS_NUM] = {
704 XSTORM_ASSERT_LIST_INDEX_OFFSET,
705 TSTORM_ASSERT_LIST_INDEX_OFFSET,
706 CSTORM_ASSERT_LIST_INDEX_OFFSET,
707 USTORM_ASSERT_LIST_INDEX_OFFSET
709 char *storms_string[STORMS_NUM] = {
716 for (storm = XSTORM; storm < MAX_STORMS; storm++) {
717 last_idx = REG_RD8(bp, bar_storm_intmem[storm] +
718 storm_assert_list_index[storm]);
720 BNX2X_ERR("%s_ASSERT_LIST_INDEX 0x%x\n",
721 storms_string[storm], last_idx);
723 /* print the asserts */
724 for (i = 0; i < STROM_ASSERT_ARRAY_SIZE; i++) {
725 /* read a single assert entry */
726 for (j = 0; j < REGS_IN_ENTRY; j++)
727 regs[j] = REG_RD(bp, bar_storm_intmem[storm] +
728 bnx2x_get_assert_list_entry(bp,
733 /* log entry if it contains a valid assert */
734 if (regs[0] != COMMON_ASM_INVALID_ASSERT_OPCODE) {
735 BNX2X_ERR("%s_ASSERT_INDEX 0x%x = 0x%08x 0x%08x 0x%08x 0x%08x\n",
736 storms_string[storm], i, regs[3],
737 regs[2], regs[1], regs[0]);
745 BNX2X_ERR("Chip Revision: %s, FW Version: %d_%d_%d\n",
746 CHIP_IS_E1(bp) ? "everest1" :
747 CHIP_IS_E1H(bp) ? "everest1h" :
748 CHIP_IS_E2(bp) ? "everest2" : "everest3",
749 BCM_5710_FW_MAJOR_VERSION,
750 BCM_5710_FW_MINOR_VERSION,
751 BCM_5710_FW_REVISION_VERSION);
756 #define MCPR_TRACE_BUFFER_SIZE (0x800)
757 #define SCRATCH_BUFFER_SIZE(bp) \
758 (CHIP_IS_E1(bp) ? 0x10000 : (CHIP_IS_E1H(bp) ? 0x20000 : 0x28000))
760 void bnx2x_fw_dump_lvl(struct bnx2x *bp, const char *lvl)
766 u32 trace_shmem_base;
768 BNX2X_ERR("NO MCP - can not dump\n");
771 netdev_printk(lvl, bp->dev, "bc %d.%d.%d\n",
772 (bp->common.bc_ver & 0xff0000) >> 16,
773 (bp->common.bc_ver & 0xff00) >> 8,
774 (bp->common.bc_ver & 0xff));
776 val = REG_RD(bp, MCP_REG_MCPR_CPU_PROGRAM_COUNTER);
777 if (val == REG_RD(bp, MCP_REG_MCPR_CPU_PROGRAM_COUNTER))
778 BNX2X_ERR("%s" "MCP PC at 0x%x\n", lvl, val);
780 if (BP_PATH(bp) == 0)
781 trace_shmem_base = bp->common.shmem_base;
783 trace_shmem_base = SHMEM2_RD(bp, other_shmem_base_addr);
786 if (trace_shmem_base < MCPR_SCRATCH_BASE(bp) + MCPR_TRACE_BUFFER_SIZE ||
787 trace_shmem_base >= MCPR_SCRATCH_BASE(bp) +
788 SCRATCH_BUFFER_SIZE(bp)) {
789 BNX2X_ERR("Unable to dump trace buffer (mark %x)\n",
794 addr = trace_shmem_base - MCPR_TRACE_BUFFER_SIZE;
796 /* validate TRCB signature */
797 mark = REG_RD(bp, addr);
798 if (mark != MFW_TRACE_SIGNATURE) {
799 BNX2X_ERR("Trace buffer signature is missing.");
803 /* read cyclic buffer pointer */
805 mark = REG_RD(bp, addr);
806 mark = MCPR_SCRATCH_BASE(bp) + ((mark + 0x3) & ~0x3) - 0x08000000;
807 if (mark >= trace_shmem_base || mark < addr + 4) {
808 BNX2X_ERR("Mark doesn't fall inside Trace Buffer\n");
811 printk("%s" "begin fw dump (mark 0x%x)\n", lvl, mark);
815 /* dump buffer after the mark */
816 for (offset = mark; offset < trace_shmem_base; offset += 0x8*4) {
817 for (word = 0; word < 8; word++)
818 data[word] = htonl(REG_RD(bp, offset + 4*word));
820 pr_cont("%s", (char *)data);
823 /* dump buffer before the mark */
824 for (offset = addr + 4; offset <= mark; offset += 0x8*4) {
825 for (word = 0; word < 8; word++)
826 data[word] = htonl(REG_RD(bp, offset + 4*word));
828 pr_cont("%s", (char *)data);
830 printk("%s" "end of fw dump\n", lvl);
833 static void bnx2x_fw_dump(struct bnx2x *bp)
835 bnx2x_fw_dump_lvl(bp, KERN_ERR);
838 static void bnx2x_hc_int_disable(struct bnx2x *bp)
840 int port = BP_PORT(bp);
841 u32 addr = port ? HC_REG_CONFIG_1 : HC_REG_CONFIG_0;
842 u32 val = REG_RD(bp, addr);
844 /* in E1 we must use only PCI configuration space to disable
845 * MSI/MSIX capability
846 * It's forbidden to disable IGU_PF_CONF_MSI_MSIX_EN in HC block
848 if (CHIP_IS_E1(bp)) {
849 /* Since IGU_PF_CONF_MSI_MSIX_EN still always on
850 * Use mask register to prevent from HC sending interrupts
851 * after we exit the function
853 REG_WR(bp, HC_REG_INT_MASK + port*4, 0);
855 val &= ~(HC_CONFIG_0_REG_SINGLE_ISR_EN_0 |
856 HC_CONFIG_0_REG_INT_LINE_EN_0 |
857 HC_CONFIG_0_REG_ATTN_BIT_EN_0);
859 val &= ~(HC_CONFIG_0_REG_SINGLE_ISR_EN_0 |
860 HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0 |
861 HC_CONFIG_0_REG_INT_LINE_EN_0 |
862 HC_CONFIG_0_REG_ATTN_BIT_EN_0);
865 "write %x to HC %d (addr 0x%x)\n",
868 /* flush all outstanding writes */
871 REG_WR(bp, addr, val);
872 if (REG_RD(bp, addr) != val)
873 BNX2X_ERR("BUG! Proper val not read from IGU!\n");
876 static void bnx2x_igu_int_disable(struct bnx2x *bp)
878 u32 val = REG_RD(bp, IGU_REG_PF_CONFIGURATION);
880 val &= ~(IGU_PF_CONF_MSI_MSIX_EN |
881 IGU_PF_CONF_INT_LINE_EN |
882 IGU_PF_CONF_ATTN_BIT_EN);
884 DP(NETIF_MSG_IFDOWN, "write %x to IGU\n", val);
886 /* flush all outstanding writes */
889 REG_WR(bp, IGU_REG_PF_CONFIGURATION, val);
890 if (REG_RD(bp, IGU_REG_PF_CONFIGURATION) != val)
891 BNX2X_ERR("BUG! Proper val not read from IGU!\n");
894 static void bnx2x_int_disable(struct bnx2x *bp)
896 if (bp->common.int_block == INT_BLOCK_HC)
897 bnx2x_hc_int_disable(bp);
899 bnx2x_igu_int_disable(bp);
902 void bnx2x_panic_dump(struct bnx2x *bp, bool disable_int)
906 struct hc_sp_status_block_data sp_sb_data;
907 int func = BP_FUNC(bp);
908 #ifdef BNX2X_STOP_ON_ERROR
909 u16 start = 0, end = 0;
912 if (IS_PF(bp) && disable_int)
913 bnx2x_int_disable(bp);
915 bp->stats_state = STATS_STATE_DISABLED;
916 bp->eth_stats.unrecoverable_error++;
917 DP(BNX2X_MSG_STATS, "stats_state - DISABLED\n");
919 BNX2X_ERR("begin crash dump -----------------\n");
924 struct host_sp_status_block *def_sb = bp->def_status_blk;
925 int data_size, cstorm_offset;
927 BNX2X_ERR("def_idx(0x%x) def_att_idx(0x%x) attn_state(0x%x) spq_prod_idx(0x%x) next_stats_cnt(0x%x)\n",
928 bp->def_idx, bp->def_att_idx, bp->attn_state,
929 bp->spq_prod_idx, bp->stats_counter);
930 BNX2X_ERR("DSB: attn bits(0x%x) ack(0x%x) id(0x%x) idx(0x%x)\n",
931 def_sb->atten_status_block.attn_bits,
932 def_sb->atten_status_block.attn_bits_ack,
933 def_sb->atten_status_block.status_block_id,
934 def_sb->atten_status_block.attn_bits_index);
936 for (i = 0; i < HC_SP_SB_MAX_INDICES; i++)
938 def_sb->sp_sb.index_values[i],
939 (i == HC_SP_SB_MAX_INDICES - 1) ? ") " : " ");
941 data_size = sizeof(struct hc_sp_status_block_data) /
943 cstorm_offset = CSTORM_SP_STATUS_BLOCK_DATA_OFFSET(func);
944 for (i = 0; i < data_size; i++)
945 *((u32 *)&sp_sb_data + i) =
946 REG_RD(bp, BAR_CSTRORM_INTMEM + cstorm_offset +
949 pr_cont("igu_sb_id(0x%x) igu_seg_id(0x%x) pf_id(0x%x) vnic_id(0x%x) vf_id(0x%x) vf_valid (0x%x) state(0x%x)\n",
950 sp_sb_data.igu_sb_id,
951 sp_sb_data.igu_seg_id,
952 sp_sb_data.p_func.pf_id,
953 sp_sb_data.p_func.vnic_id,
954 sp_sb_data.p_func.vf_id,
955 sp_sb_data.p_func.vf_valid,
959 for_each_eth_queue(bp, i) {
960 struct bnx2x_fastpath *fp = &bp->fp[i];
962 struct hc_status_block_data_e2 sb_data_e2;
963 struct hc_status_block_data_e1x sb_data_e1x;
964 struct hc_status_block_sm *hc_sm_p =
966 sb_data_e1x.common.state_machine :
967 sb_data_e2.common.state_machine;
968 struct hc_index_data *hc_index_p =
970 sb_data_e1x.index_data :
971 sb_data_e2.index_data;
974 struct bnx2x_fp_txdata txdata;
983 BNX2X_ERR("fp%d: rx_bd_prod(0x%x) rx_bd_cons(0x%x) rx_comp_prod(0x%x) rx_comp_cons(0x%x) *rx_cons_sb(0x%x)\n",
984 i, fp->rx_bd_prod, fp->rx_bd_cons,
986 fp->rx_comp_cons, le16_to_cpu(*fp->rx_cons_sb));
987 BNX2X_ERR(" rx_sge_prod(0x%x) last_max_sge(0x%x) fp_hc_idx(0x%x)\n",
988 fp->rx_sge_prod, fp->last_max_sge,
989 le16_to_cpu(fp->fp_hc_idx));
992 for_each_cos_in_tx_queue(fp, cos)
994 if (!fp->txdata_ptr[cos])
997 txdata = *fp->txdata_ptr[cos];
999 if (!txdata.tx_cons_sb)
1002 BNX2X_ERR("fp%d: tx_pkt_prod(0x%x) tx_pkt_cons(0x%x) tx_bd_prod(0x%x) tx_bd_cons(0x%x) *tx_cons_sb(0x%x)\n",
1003 i, txdata.tx_pkt_prod,
1004 txdata.tx_pkt_cons, txdata.tx_bd_prod,
1006 le16_to_cpu(*txdata.tx_cons_sb));
1009 loop = CHIP_IS_E1x(bp) ?
1010 HC_SB_MAX_INDICES_E1X : HC_SB_MAX_INDICES_E2;
1017 BNX2X_ERR(" run indexes (");
1018 for (j = 0; j < HC_SB_MAX_SM; j++)
1020 fp->sb_running_index[j],
1021 (j == HC_SB_MAX_SM - 1) ? ")" : " ");
1023 BNX2X_ERR(" indexes (");
1024 for (j = 0; j < loop; j++)
1026 fp->sb_index_values[j],
1027 (j == loop - 1) ? ")" : " ");
1029 /* VF cannot access FW refelection for status block */
1034 data_size = CHIP_IS_E1x(bp) ?
1035 sizeof(struct hc_status_block_data_e1x) :
1036 sizeof(struct hc_status_block_data_e2);
1037 data_size /= sizeof(u32);
1038 sb_data_p = CHIP_IS_E1x(bp) ?
1039 (u32 *)&sb_data_e1x :
1041 /* copy sb data in here */
1042 for (j = 0; j < data_size; j++)
1043 *(sb_data_p + j) = REG_RD(bp, BAR_CSTRORM_INTMEM +
1044 CSTORM_STATUS_BLOCK_DATA_OFFSET(fp->fw_sb_id) +
1047 if (!CHIP_IS_E1x(bp)) {
1048 pr_cont("pf_id(0x%x) vf_id(0x%x) vf_valid(0x%x) vnic_id(0x%x) same_igu_sb_1b(0x%x) state(0x%x)\n",
1049 sb_data_e2.common.p_func.pf_id,
1050 sb_data_e2.common.p_func.vf_id,
1051 sb_data_e2.common.p_func.vf_valid,
1052 sb_data_e2.common.p_func.vnic_id,
1053 sb_data_e2.common.same_igu_sb_1b,
1054 sb_data_e2.common.state);
1056 pr_cont("pf_id(0x%x) vf_id(0x%x) vf_valid(0x%x) vnic_id(0x%x) same_igu_sb_1b(0x%x) state(0x%x)\n",
1057 sb_data_e1x.common.p_func.pf_id,
1058 sb_data_e1x.common.p_func.vf_id,
1059 sb_data_e1x.common.p_func.vf_valid,
1060 sb_data_e1x.common.p_func.vnic_id,
1061 sb_data_e1x.common.same_igu_sb_1b,
1062 sb_data_e1x.common.state);
1066 for (j = 0; j < HC_SB_MAX_SM; j++) {
1067 pr_cont("SM[%d] __flags (0x%x) igu_sb_id (0x%x) igu_seg_id(0x%x) time_to_expire (0x%x) timer_value(0x%x)\n",
1068 j, hc_sm_p[j].__flags,
1069 hc_sm_p[j].igu_sb_id,
1070 hc_sm_p[j].igu_seg_id,
1071 hc_sm_p[j].time_to_expire,
1072 hc_sm_p[j].timer_value);
1076 for (j = 0; j < loop; j++) {
1077 pr_cont("INDEX[%d] flags (0x%x) timeout (0x%x)\n", j,
1078 hc_index_p[j].flags,
1079 hc_index_p[j].timeout);
1083 #ifdef BNX2X_STOP_ON_ERROR
1086 BNX2X_ERR("eq cons %x prod %x\n", bp->eq_cons, bp->eq_prod);
1087 for (i = 0; i < NUM_EQ_DESC; i++) {
1088 u32 *data = (u32 *)&bp->eq_ring[i].message.data;
1090 BNX2X_ERR("event queue [%d]: header: opcode %d, error %d\n",
1091 i, bp->eq_ring[i].message.opcode,
1092 bp->eq_ring[i].message.error);
1093 BNX2X_ERR("data: %x %x %x\n",
1094 data[0], data[1], data[2]);
1100 for_each_valid_rx_queue(bp, i) {
1101 struct bnx2x_fastpath *fp = &bp->fp[i];
1106 if (!fp->rx_cons_sb)
1109 start = RX_BD(le16_to_cpu(*fp->rx_cons_sb) - 10);
1110 end = RX_BD(le16_to_cpu(*fp->rx_cons_sb) + 503);
1111 for (j = start; j != end; j = RX_BD(j + 1)) {
1112 u32 *rx_bd = (u32 *)&fp->rx_desc_ring[j];
1113 struct sw_rx_bd *sw_bd = &fp->rx_buf_ring[j];
1115 BNX2X_ERR("fp%d: rx_bd[%x]=[%x:%x] sw_bd=[%p]\n",
1116 i, j, rx_bd[1], rx_bd[0], sw_bd->data);
1119 start = RX_SGE(fp->rx_sge_prod);
1120 end = RX_SGE(fp->last_max_sge);
1121 for (j = start; j != end; j = RX_SGE(j + 1)) {
1122 u32 *rx_sge = (u32 *)&fp->rx_sge_ring[j];
1123 struct sw_rx_page *sw_page = &fp->rx_page_ring[j];
1125 BNX2X_ERR("fp%d: rx_sge[%x]=[%x:%x] sw_page=[%p]\n",
1126 i, j, rx_sge[1], rx_sge[0], sw_page->page);
1129 start = RCQ_BD(fp->rx_comp_cons - 10);
1130 end = RCQ_BD(fp->rx_comp_cons + 503);
1131 for (j = start; j != end; j = RCQ_BD(j + 1)) {
1132 u32 *cqe = (u32 *)&fp->rx_comp_ring[j];
1134 BNX2X_ERR("fp%d: cqe[%x]=[%x:%x:%x:%x]\n",
1135 i, j, cqe[0], cqe[1], cqe[2], cqe[3]);
1140 for_each_valid_tx_queue(bp, i) {
1141 struct bnx2x_fastpath *fp = &bp->fp[i];
1146 for_each_cos_in_tx_queue(fp, cos) {
1147 struct bnx2x_fp_txdata *txdata = fp->txdata_ptr[cos];
1149 if (!fp->txdata_ptr[cos])
1152 if (!txdata->tx_cons_sb)
1155 start = TX_BD(le16_to_cpu(*txdata->tx_cons_sb) - 10);
1156 end = TX_BD(le16_to_cpu(*txdata->tx_cons_sb) + 245);
1157 for (j = start; j != end; j = TX_BD(j + 1)) {
1158 struct sw_tx_bd *sw_bd =
1159 &txdata->tx_buf_ring[j];
1161 BNX2X_ERR("fp%d: txdata %d, packet[%x]=[%p,%x]\n",
1162 i, cos, j, sw_bd->skb,
1166 start = TX_BD(txdata->tx_bd_cons - 10);
1167 end = TX_BD(txdata->tx_bd_cons + 254);
1168 for (j = start; j != end; j = TX_BD(j + 1)) {
1169 u32 *tx_bd = (u32 *)&txdata->tx_desc_ring[j];
1171 BNX2X_ERR("fp%d: txdata %d, tx_bd[%x]=[%x:%x:%x:%x]\n",
1172 i, cos, j, tx_bd[0], tx_bd[1],
1173 tx_bd[2], tx_bd[3]);
1180 bnx2x_mc_assert(bp);
1182 BNX2X_ERR("end crash dump -----------------\n");
1186 * FLR Support for E2
1188 * bnx2x_pf_flr_clnup() is called during nic_load in the per function HW
1191 #define FLR_WAIT_USEC 10000 /* 10 milliseconds */
1192 #define FLR_WAIT_INTERVAL 50 /* usec */
1193 #define FLR_POLL_CNT (FLR_WAIT_USEC/FLR_WAIT_INTERVAL) /* 200 */
1195 struct pbf_pN_buf_regs {
1202 struct pbf_pN_cmd_regs {
1208 static void bnx2x_pbf_pN_buf_flushed(struct bnx2x *bp,
1209 struct pbf_pN_buf_regs *regs,
1212 u32 init_crd, crd, crd_start, crd_freed, crd_freed_start;
1213 u32 cur_cnt = poll_count;
1215 crd_freed = crd_freed_start = REG_RD(bp, regs->crd_freed);
1216 crd = crd_start = REG_RD(bp, regs->crd);
1217 init_crd = REG_RD(bp, regs->init_crd);
1219 DP(BNX2X_MSG_SP, "INIT CREDIT[%d] : %x\n", regs->pN, init_crd);
1220 DP(BNX2X_MSG_SP, "CREDIT[%d] : s:%x\n", regs->pN, crd);
1221 DP(BNX2X_MSG_SP, "CREDIT_FREED[%d]: s:%x\n", regs->pN, crd_freed);
1223 while ((crd != init_crd) && ((u32)SUB_S32(crd_freed, crd_freed_start) <
1224 (init_crd - crd_start))) {
1226 udelay(FLR_WAIT_INTERVAL);
1227 crd = REG_RD(bp, regs->crd);
1228 crd_freed = REG_RD(bp, regs->crd_freed);
1230 DP(BNX2X_MSG_SP, "PBF tx buffer[%d] timed out\n",
1232 DP(BNX2X_MSG_SP, "CREDIT[%d] : c:%x\n",
1234 DP(BNX2X_MSG_SP, "CREDIT_FREED[%d]: c:%x\n",
1235 regs->pN, crd_freed);
1239 DP(BNX2X_MSG_SP, "Waited %d*%d usec for PBF tx buffer[%d]\n",
1240 poll_count-cur_cnt, FLR_WAIT_INTERVAL, regs->pN);
1243 static void bnx2x_pbf_pN_cmd_flushed(struct bnx2x *bp,
1244 struct pbf_pN_cmd_regs *regs,
1247 u32 occup, to_free, freed, freed_start;
1248 u32 cur_cnt = poll_count;
1250 occup = to_free = REG_RD(bp, regs->lines_occup);
1251 freed = freed_start = REG_RD(bp, regs->lines_freed);
1253 DP(BNX2X_MSG_SP, "OCCUPANCY[%d] : s:%x\n", regs->pN, occup);
1254 DP(BNX2X_MSG_SP, "LINES_FREED[%d] : s:%x\n", regs->pN, freed);
1256 while (occup && ((u32)SUB_S32(freed, freed_start) < to_free)) {
1258 udelay(FLR_WAIT_INTERVAL);
1259 occup = REG_RD(bp, regs->lines_occup);
1260 freed = REG_RD(bp, regs->lines_freed);
1262 DP(BNX2X_MSG_SP, "PBF cmd queue[%d] timed out\n",
1264 DP(BNX2X_MSG_SP, "OCCUPANCY[%d] : s:%x\n",
1266 DP(BNX2X_MSG_SP, "LINES_FREED[%d] : s:%x\n",
1271 DP(BNX2X_MSG_SP, "Waited %d*%d usec for PBF cmd queue[%d]\n",
1272 poll_count-cur_cnt, FLR_WAIT_INTERVAL, regs->pN);
1275 static u32 bnx2x_flr_clnup_reg_poll(struct bnx2x *bp, u32 reg,
1276 u32 expected, u32 poll_count)
1278 u32 cur_cnt = poll_count;
1281 while ((val = REG_RD(bp, reg)) != expected && cur_cnt--)
1282 udelay(FLR_WAIT_INTERVAL);
1287 int bnx2x_flr_clnup_poll_hw_counter(struct bnx2x *bp, u32 reg,
1288 char *msg, u32 poll_cnt)
1290 u32 val = bnx2x_flr_clnup_reg_poll(bp, reg, 0, poll_cnt);
1292 BNX2X_ERR("%s usage count=%d\n", msg, val);
1298 /* Common routines with VF FLR cleanup */
1299 u32 bnx2x_flr_clnup_poll_count(struct bnx2x *bp)
1301 /* adjust polling timeout */
1302 if (CHIP_REV_IS_EMUL(bp))
1303 return FLR_POLL_CNT * 2000;
1305 if (CHIP_REV_IS_FPGA(bp))
1306 return FLR_POLL_CNT * 120;
1308 return FLR_POLL_CNT;
1311 void bnx2x_tx_hw_flushed(struct bnx2x *bp, u32 poll_count)
1313 struct pbf_pN_cmd_regs cmd_regs[] = {
1314 {0, (CHIP_IS_E3B0(bp)) ?
1315 PBF_REG_TQ_OCCUPANCY_Q0 :
1316 PBF_REG_P0_TQ_OCCUPANCY,
1317 (CHIP_IS_E3B0(bp)) ?
1318 PBF_REG_TQ_LINES_FREED_CNT_Q0 :
1319 PBF_REG_P0_TQ_LINES_FREED_CNT},
1320 {1, (CHIP_IS_E3B0(bp)) ?
1321 PBF_REG_TQ_OCCUPANCY_Q1 :
1322 PBF_REG_P1_TQ_OCCUPANCY,
1323 (CHIP_IS_E3B0(bp)) ?
1324 PBF_REG_TQ_LINES_FREED_CNT_Q1 :
1325 PBF_REG_P1_TQ_LINES_FREED_CNT},
1326 {4, (CHIP_IS_E3B0(bp)) ?
1327 PBF_REG_TQ_OCCUPANCY_LB_Q :
1328 PBF_REG_P4_TQ_OCCUPANCY,
1329 (CHIP_IS_E3B0(bp)) ?
1330 PBF_REG_TQ_LINES_FREED_CNT_LB_Q :
1331 PBF_REG_P4_TQ_LINES_FREED_CNT}
1334 struct pbf_pN_buf_regs buf_regs[] = {
1335 {0, (CHIP_IS_E3B0(bp)) ?
1336 PBF_REG_INIT_CRD_Q0 :
1337 PBF_REG_P0_INIT_CRD ,
1338 (CHIP_IS_E3B0(bp)) ?
1341 (CHIP_IS_E3B0(bp)) ?
1342 PBF_REG_INTERNAL_CRD_FREED_CNT_Q0 :
1343 PBF_REG_P0_INTERNAL_CRD_FREED_CNT},
1344 {1, (CHIP_IS_E3B0(bp)) ?
1345 PBF_REG_INIT_CRD_Q1 :
1346 PBF_REG_P1_INIT_CRD,
1347 (CHIP_IS_E3B0(bp)) ?
1350 (CHIP_IS_E3B0(bp)) ?
1351 PBF_REG_INTERNAL_CRD_FREED_CNT_Q1 :
1352 PBF_REG_P1_INTERNAL_CRD_FREED_CNT},
1353 {4, (CHIP_IS_E3B0(bp)) ?
1354 PBF_REG_INIT_CRD_LB_Q :
1355 PBF_REG_P4_INIT_CRD,
1356 (CHIP_IS_E3B0(bp)) ?
1357 PBF_REG_CREDIT_LB_Q :
1359 (CHIP_IS_E3B0(bp)) ?
1360 PBF_REG_INTERNAL_CRD_FREED_CNT_LB_Q :
1361 PBF_REG_P4_INTERNAL_CRD_FREED_CNT},
1366 /* Verify the command queues are flushed P0, P1, P4 */
1367 for (i = 0; i < ARRAY_SIZE(cmd_regs); i++)
1368 bnx2x_pbf_pN_cmd_flushed(bp, &cmd_regs[i], poll_count);
1370 /* Verify the transmission buffers are flushed P0, P1, P4 */
1371 for (i = 0; i < ARRAY_SIZE(buf_regs); i++)
1372 bnx2x_pbf_pN_buf_flushed(bp, &buf_regs[i], poll_count);
1375 #define OP_GEN_PARAM(param) \
1376 (((param) << SDM_OP_GEN_COMP_PARAM_SHIFT) & SDM_OP_GEN_COMP_PARAM)
1378 #define OP_GEN_TYPE(type) \
1379 (((type) << SDM_OP_GEN_COMP_TYPE_SHIFT) & SDM_OP_GEN_COMP_TYPE)
1381 #define OP_GEN_AGG_VECT(index) \
1382 (((index) << SDM_OP_GEN_AGG_VECT_IDX_SHIFT) & SDM_OP_GEN_AGG_VECT_IDX)
1384 int bnx2x_send_final_clnup(struct bnx2x *bp, u8 clnup_func, u32 poll_cnt)
1386 u32 op_gen_command = 0;
1387 u32 comp_addr = BAR_CSTRORM_INTMEM +
1388 CSTORM_FINAL_CLEANUP_COMPLETE_OFFSET(clnup_func);
1391 if (REG_RD(bp, comp_addr)) {
1392 BNX2X_ERR("Cleanup complete was not 0 before sending\n");
1396 op_gen_command |= OP_GEN_PARAM(XSTORM_AGG_INT_FINAL_CLEANUP_INDEX);
1397 op_gen_command |= OP_GEN_TYPE(XSTORM_AGG_INT_FINAL_CLEANUP_COMP_TYPE);
1398 op_gen_command |= OP_GEN_AGG_VECT(clnup_func);
1399 op_gen_command |= 1 << SDM_OP_GEN_AGG_VECT_IDX_VALID_SHIFT;
1401 DP(BNX2X_MSG_SP, "sending FW Final cleanup\n");
1402 REG_WR(bp, XSDM_REG_OPERATION_GEN, op_gen_command);
1404 if (bnx2x_flr_clnup_reg_poll(bp, comp_addr, 1, poll_cnt) != 1) {
1405 BNX2X_ERR("FW final cleanup did not succeed\n");
1406 DP(BNX2X_MSG_SP, "At timeout completion address contained %x\n",
1407 (REG_RD(bp, comp_addr)));
1411 /* Zero completion for next FLR */
1412 REG_WR(bp, comp_addr, 0);
1417 u8 bnx2x_is_pcie_pending(struct pci_dev *dev)
1421 pcie_capability_read_word(dev, PCI_EXP_DEVSTA, &status);
1422 return status & PCI_EXP_DEVSTA_TRPND;
1425 /* PF FLR specific routines
1427 static int bnx2x_poll_hw_usage_counters(struct bnx2x *bp, u32 poll_cnt)
1429 /* wait for CFC PF usage-counter to zero (includes all the VFs) */
1430 if (bnx2x_flr_clnup_poll_hw_counter(bp,
1431 CFC_REG_NUM_LCIDS_INSIDE_PF,
1432 "CFC PF usage counter timed out",
1436 /* Wait for DQ PF usage-counter to zero (until DQ cleanup) */
1437 if (bnx2x_flr_clnup_poll_hw_counter(bp,
1438 DORQ_REG_PF_USAGE_CNT,
1439 "DQ PF usage counter timed out",
1443 /* Wait for QM PF usage-counter to zero (until DQ cleanup) */
1444 if (bnx2x_flr_clnup_poll_hw_counter(bp,
1445 QM_REG_PF_USG_CNT_0 + 4*BP_FUNC(bp),
1446 "QM PF usage counter timed out",
1450 /* Wait for Timer PF usage-counters to zero (until DQ cleanup) */
1451 if (bnx2x_flr_clnup_poll_hw_counter(bp,
1452 TM_REG_LIN0_VNIC_UC + 4*BP_PORT(bp),
1453 "Timers VNIC usage counter timed out",
1456 if (bnx2x_flr_clnup_poll_hw_counter(bp,
1457 TM_REG_LIN0_NUM_SCANS + 4*BP_PORT(bp),
1458 "Timers NUM_SCANS usage counter timed out",
1462 /* Wait DMAE PF usage counter to zero */
1463 if (bnx2x_flr_clnup_poll_hw_counter(bp,
1464 dmae_reg_go_c[INIT_DMAE_C(bp)],
1465 "DMAE command register timed out",
1472 static void bnx2x_hw_enable_status(struct bnx2x *bp)
1476 val = REG_RD(bp, CFC_REG_WEAK_ENABLE_PF);
1477 DP(BNX2X_MSG_SP, "CFC_REG_WEAK_ENABLE_PF is 0x%x\n", val);
1479 val = REG_RD(bp, PBF_REG_DISABLE_PF);
1480 DP(BNX2X_MSG_SP, "PBF_REG_DISABLE_PF is 0x%x\n", val);
1482 val = REG_RD(bp, IGU_REG_PCI_PF_MSI_EN);
1483 DP(BNX2X_MSG_SP, "IGU_REG_PCI_PF_MSI_EN is 0x%x\n", val);
1485 val = REG_RD(bp, IGU_REG_PCI_PF_MSIX_EN);
1486 DP(BNX2X_MSG_SP, "IGU_REG_PCI_PF_MSIX_EN is 0x%x\n", val);
1488 val = REG_RD(bp, IGU_REG_PCI_PF_MSIX_FUNC_MASK);
1489 DP(BNX2X_MSG_SP, "IGU_REG_PCI_PF_MSIX_FUNC_MASK is 0x%x\n", val);
1491 val = REG_RD(bp, PGLUE_B_REG_SHADOW_BME_PF_7_0_CLR);
1492 DP(BNX2X_MSG_SP, "PGLUE_B_REG_SHADOW_BME_PF_7_0_CLR is 0x%x\n", val);
1494 val = REG_RD(bp, PGLUE_B_REG_FLR_REQUEST_PF_7_0_CLR);
1495 DP(BNX2X_MSG_SP, "PGLUE_B_REG_FLR_REQUEST_PF_7_0_CLR is 0x%x\n", val);
1497 val = REG_RD(bp, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER);
1498 DP(BNX2X_MSG_SP, "PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER is 0x%x\n",
1502 static int bnx2x_pf_flr_clnup(struct bnx2x *bp)
1504 u32 poll_cnt = bnx2x_flr_clnup_poll_count(bp);
1506 DP(BNX2X_MSG_SP, "Cleanup after FLR PF[%d]\n", BP_ABS_FUNC(bp));
1508 /* Re-enable PF target read access */
1509 REG_WR(bp, PGLUE_B_REG_INTERNAL_PFID_ENABLE_TARGET_READ, 1);
1511 /* Poll HW usage counters */
1512 DP(BNX2X_MSG_SP, "Polling usage counters\n");
1513 if (bnx2x_poll_hw_usage_counters(bp, poll_cnt))
1516 /* Zero the igu 'trailing edge' and 'leading edge' */
1518 /* Send the FW cleanup command */
1519 if (bnx2x_send_final_clnup(bp, (u8)BP_FUNC(bp), poll_cnt))
1524 /* Verify TX hw is flushed */
1525 bnx2x_tx_hw_flushed(bp, poll_cnt);
1527 /* Wait 100ms (not adjusted according to platform) */
1530 /* Verify no pending pci transactions */
1531 if (bnx2x_is_pcie_pending(bp->pdev))
1532 BNX2X_ERR("PCIE Transactions still pending\n");
1535 bnx2x_hw_enable_status(bp);
1538 * Master enable - Due to WB DMAE writes performed before this
1539 * register is re-initialized as part of the regular function init
1541 REG_WR(bp, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, 1);
1546 static void bnx2x_hc_int_enable(struct bnx2x *bp)
1548 int port = BP_PORT(bp);
1549 u32 addr = port ? HC_REG_CONFIG_1 : HC_REG_CONFIG_0;
1550 u32 val = REG_RD(bp, addr);
1551 bool msix = (bp->flags & USING_MSIX_FLAG) ? true : false;
1552 bool single_msix = (bp->flags & USING_SINGLE_MSIX_FLAG) ? true : false;
1553 bool msi = (bp->flags & USING_MSI_FLAG) ? true : false;
1556 val &= ~(HC_CONFIG_0_REG_SINGLE_ISR_EN_0 |
1557 HC_CONFIG_0_REG_INT_LINE_EN_0);
1558 val |= (HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0 |
1559 HC_CONFIG_0_REG_ATTN_BIT_EN_0);
1561 val |= HC_CONFIG_0_REG_SINGLE_ISR_EN_0;
1563 val &= ~HC_CONFIG_0_REG_INT_LINE_EN_0;
1564 val |= (HC_CONFIG_0_REG_SINGLE_ISR_EN_0 |
1565 HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0 |
1566 HC_CONFIG_0_REG_ATTN_BIT_EN_0);
1568 val |= (HC_CONFIG_0_REG_SINGLE_ISR_EN_0 |
1569 HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0 |
1570 HC_CONFIG_0_REG_INT_LINE_EN_0 |
1571 HC_CONFIG_0_REG_ATTN_BIT_EN_0);
1573 if (!CHIP_IS_E1(bp)) {
1575 "write %x to HC %d (addr 0x%x)\n", val, port, addr);
1577 REG_WR(bp, addr, val);
1579 val &= ~HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0;
1584 REG_WR(bp, HC_REG_INT_MASK + port*4, 0x1FFFF);
1587 "write %x to HC %d (addr 0x%x) mode %s\n", val, port, addr,
1588 (msix ? "MSI-X" : (msi ? "MSI" : "INTx")));
1590 REG_WR(bp, addr, val);
1592 * Ensure that HC_CONFIG is written before leading/trailing edge config
1597 if (!CHIP_IS_E1(bp)) {
1598 /* init leading/trailing edge */
1600 val = (0xee0f | (1 << (BP_VN(bp) + 4)));
1602 /* enable nig and gpio3 attention */
1607 REG_WR(bp, HC_REG_TRAILING_EDGE_0 + port*8, val);
1608 REG_WR(bp, HC_REG_LEADING_EDGE_0 + port*8, val);
1611 /* Make sure that interrupts are indeed enabled from here on */
1615 static void bnx2x_igu_int_enable(struct bnx2x *bp)
1618 bool msix = (bp->flags & USING_MSIX_FLAG) ? true : false;
1619 bool single_msix = (bp->flags & USING_SINGLE_MSIX_FLAG) ? true : false;
1620 bool msi = (bp->flags & USING_MSI_FLAG) ? true : false;
1622 val = REG_RD(bp, IGU_REG_PF_CONFIGURATION);
1625 val &= ~(IGU_PF_CONF_INT_LINE_EN |
1626 IGU_PF_CONF_SINGLE_ISR_EN);
1627 val |= (IGU_PF_CONF_MSI_MSIX_EN |
1628 IGU_PF_CONF_ATTN_BIT_EN);
1631 val |= IGU_PF_CONF_SINGLE_ISR_EN;
1633 val &= ~IGU_PF_CONF_INT_LINE_EN;
1634 val |= (IGU_PF_CONF_MSI_MSIX_EN |
1635 IGU_PF_CONF_ATTN_BIT_EN |
1636 IGU_PF_CONF_SINGLE_ISR_EN);
1638 val &= ~IGU_PF_CONF_MSI_MSIX_EN;
1639 val |= (IGU_PF_CONF_INT_LINE_EN |
1640 IGU_PF_CONF_ATTN_BIT_EN |
1641 IGU_PF_CONF_SINGLE_ISR_EN);
1644 /* Clean previous status - need to configure igu prior to ack*/
1645 if ((!msix) || single_msix) {
1646 REG_WR(bp, IGU_REG_PF_CONFIGURATION, val);
1650 val |= IGU_PF_CONF_FUNC_EN;
1652 DP(NETIF_MSG_IFUP, "write 0x%x to IGU mode %s\n",
1653 val, (msix ? "MSI-X" : (msi ? "MSI" : "INTx")));
1655 REG_WR(bp, IGU_REG_PF_CONFIGURATION, val);
1657 if (val & IGU_PF_CONF_INT_LINE_EN)
1658 pci_intx(bp->pdev, true);
1662 /* init leading/trailing edge */
1664 val = (0xee0f | (1 << (BP_VN(bp) + 4)));
1666 /* enable nig and gpio3 attention */
1671 REG_WR(bp, IGU_REG_TRAILING_EDGE_LATCH, val);
1672 REG_WR(bp, IGU_REG_LEADING_EDGE_LATCH, val);
1674 /* Make sure that interrupts are indeed enabled from here on */
1678 void bnx2x_int_enable(struct bnx2x *bp)
1680 if (bp->common.int_block == INT_BLOCK_HC)
1681 bnx2x_hc_int_enable(bp);
1683 bnx2x_igu_int_enable(bp);
1686 void bnx2x_int_disable_sync(struct bnx2x *bp, int disable_hw)
1688 int msix = (bp->flags & USING_MSIX_FLAG) ? 1 : 0;
1692 /* prevent the HW from sending interrupts */
1693 bnx2x_int_disable(bp);
1695 /* make sure all ISRs are done */
1697 synchronize_irq(bp->msix_table[0].vector);
1699 if (CNIC_SUPPORT(bp))
1701 for_each_eth_queue(bp, i)
1702 synchronize_irq(bp->msix_table[offset++].vector);
1704 synchronize_irq(bp->pdev->irq);
1706 /* make sure sp_task is not running */
1707 cancel_delayed_work(&bp->sp_task);
1708 cancel_delayed_work(&bp->period_task);
1709 flush_workqueue(bnx2x_wq);
1715 * General service functions
1718 /* Return true if succeeded to acquire the lock */
1719 static bool bnx2x_trylock_hw_lock(struct bnx2x *bp, u32 resource)
1722 u32 resource_bit = (1 << resource);
1723 int func = BP_FUNC(bp);
1724 u32 hw_lock_control_reg;
1726 DP(NETIF_MSG_HW | NETIF_MSG_IFUP,
1727 "Trying to take a lock on resource %d\n", resource);
1729 /* Validating that the resource is within range */
1730 if (resource > HW_LOCK_MAX_RESOURCE_VALUE) {
1731 DP(NETIF_MSG_HW | NETIF_MSG_IFUP,
1732 "resource(0x%x) > HW_LOCK_MAX_RESOURCE_VALUE(0x%x)\n",
1733 resource, HW_LOCK_MAX_RESOURCE_VALUE);
1738 hw_lock_control_reg = (MISC_REG_DRIVER_CONTROL_1 + func*8);
1740 hw_lock_control_reg =
1741 (MISC_REG_DRIVER_CONTROL_7 + (func - 6)*8);
1743 /* Try to acquire the lock */
1744 REG_WR(bp, hw_lock_control_reg + 4, resource_bit);
1745 lock_status = REG_RD(bp, hw_lock_control_reg);
1746 if (lock_status & resource_bit)
1749 DP(NETIF_MSG_HW | NETIF_MSG_IFUP,
1750 "Failed to get a lock on resource %d\n", resource);
1755 * bnx2x_get_leader_lock_resource - get the recovery leader resource id
1757 * @bp: driver handle
1759 * Returns the recovery leader resource id according to the engine this function
1760 * belongs to. Currently only only 2 engines is supported.
1762 static int bnx2x_get_leader_lock_resource(struct bnx2x *bp)
1765 return HW_LOCK_RESOURCE_RECOVERY_LEADER_1;
1767 return HW_LOCK_RESOURCE_RECOVERY_LEADER_0;
1771 * bnx2x_trylock_leader_lock- try to acquire a leader lock.
1773 * @bp: driver handle
1775 * Tries to acquire a leader lock for current engine.
1777 static bool bnx2x_trylock_leader_lock(struct bnx2x *bp)
1779 return bnx2x_trylock_hw_lock(bp, bnx2x_get_leader_lock_resource(bp));
1782 static void bnx2x_cnic_cfc_comp(struct bnx2x *bp, int cid, u8 err);
1784 /* schedule the sp task and mark that interrupt occurred (runs from ISR) */
1785 static int bnx2x_schedule_sp_task(struct bnx2x *bp)
1787 /* Set the interrupt occurred bit for the sp-task to recognize it
1788 * must ack the interrupt and transition according to the IGU
1791 atomic_set(&bp->interrupt_occurred, 1);
1793 /* The sp_task must execute only after this bit
1794 * is set, otherwise we will get out of sync and miss all
1795 * further interrupts. Hence, the barrier.
1799 /* schedule sp_task to workqueue */
1800 return queue_delayed_work(bnx2x_wq, &bp->sp_task, 0);
1803 void bnx2x_sp_event(struct bnx2x_fastpath *fp, union eth_rx_cqe *rr_cqe)
1805 struct bnx2x *bp = fp->bp;
1806 int cid = SW_CID(rr_cqe->ramrod_cqe.conn_and_cmd_data);
1807 int command = CQE_CMD(rr_cqe->ramrod_cqe.conn_and_cmd_data);
1808 enum bnx2x_queue_cmd drv_cmd = BNX2X_Q_CMD_MAX;
1809 struct bnx2x_queue_sp_obj *q_obj = &bnx2x_sp_obj(bp, fp).q_obj;
1812 "fp %d cid %d got ramrod #%d state is %x type is %d\n",
1813 fp->index, cid, command, bp->state,
1814 rr_cqe->ramrod_cqe.ramrod_type);
1816 /* If cid is within VF range, replace the slowpath object with the
1817 * one corresponding to this VF
1819 if (cid >= BNX2X_FIRST_VF_CID &&
1820 cid < BNX2X_FIRST_VF_CID + BNX2X_VF_CIDS)
1821 bnx2x_iov_set_queue_sp_obj(bp, cid, &q_obj);
1824 case (RAMROD_CMD_ID_ETH_CLIENT_UPDATE):
1825 DP(BNX2X_MSG_SP, "got UPDATE ramrod. CID %d\n", cid);
1826 drv_cmd = BNX2X_Q_CMD_UPDATE;
1829 case (RAMROD_CMD_ID_ETH_CLIENT_SETUP):
1830 DP(BNX2X_MSG_SP, "got MULTI[%d] setup ramrod\n", cid);
1831 drv_cmd = BNX2X_Q_CMD_SETUP;
1834 case (RAMROD_CMD_ID_ETH_TX_QUEUE_SETUP):
1835 DP(BNX2X_MSG_SP, "got MULTI[%d] tx-only setup ramrod\n", cid);
1836 drv_cmd = BNX2X_Q_CMD_SETUP_TX_ONLY;
1839 case (RAMROD_CMD_ID_ETH_HALT):
1840 DP(BNX2X_MSG_SP, "got MULTI[%d] halt ramrod\n", cid);
1841 drv_cmd = BNX2X_Q_CMD_HALT;
1844 case (RAMROD_CMD_ID_ETH_TERMINATE):
1845 DP(BNX2X_MSG_SP, "got MULTI[%d] terminate ramrod\n", cid);
1846 drv_cmd = BNX2X_Q_CMD_TERMINATE;
1849 case (RAMROD_CMD_ID_ETH_EMPTY):
1850 DP(BNX2X_MSG_SP, "got MULTI[%d] empty ramrod\n", cid);
1851 drv_cmd = BNX2X_Q_CMD_EMPTY;
1854 case (RAMROD_CMD_ID_ETH_TPA_UPDATE):
1855 DP(BNX2X_MSG_SP, "got tpa update ramrod CID=%d\n", cid);
1856 drv_cmd = BNX2X_Q_CMD_UPDATE_TPA;
1860 BNX2X_ERR("unexpected MC reply (%d) on fp[%d]\n",
1861 command, fp->index);
1865 if ((drv_cmd != BNX2X_Q_CMD_MAX) &&
1866 q_obj->complete_cmd(bp, q_obj, drv_cmd))
1867 /* q_obj->complete_cmd() failure means that this was
1868 * an unexpected completion.
1870 * In this case we don't want to increase the bp->spq_left
1871 * because apparently we haven't sent this command the first
1874 #ifdef BNX2X_STOP_ON_ERROR
1880 smp_mb__before_atomic();
1881 atomic_inc(&bp->cq_spq_left);
1882 /* push the change in bp->spq_left and towards the memory */
1883 smp_mb__after_atomic();
1885 DP(BNX2X_MSG_SP, "bp->cq_spq_left %x\n", atomic_read(&bp->cq_spq_left));
1887 if ((drv_cmd == BNX2X_Q_CMD_UPDATE) && (IS_FCOE_FP(fp)) &&
1888 (!!test_bit(BNX2X_AFEX_FCOE_Q_UPDATE_PENDING, &bp->sp_state))) {
1889 /* if Q update ramrod is completed for last Q in AFEX vif set
1890 * flow, then ACK MCP at the end
1892 * mark pending ACK to MCP bit.
1893 * prevent case that both bits are cleared.
1894 * At the end of load/unload driver checks that
1895 * sp_state is cleared, and this order prevents
1898 smp_mb__before_atomic();
1899 set_bit(BNX2X_AFEX_PENDING_VIFSET_MCP_ACK, &bp->sp_state);
1901 clear_bit(BNX2X_AFEX_FCOE_Q_UPDATE_PENDING, &bp->sp_state);
1902 smp_mb__after_atomic();
1904 /* schedule the sp task as mcp ack is required */
1905 bnx2x_schedule_sp_task(bp);
1911 irqreturn_t bnx2x_interrupt(int irq, void *dev_instance)
1913 struct bnx2x *bp = netdev_priv(dev_instance);
1914 u16 status = bnx2x_ack_int(bp);
1919 /* Return here if interrupt is shared and it's not for us */
1920 if (unlikely(status == 0)) {
1921 DP(NETIF_MSG_INTR, "not our interrupt!\n");
1924 DP(NETIF_MSG_INTR, "got an interrupt status 0x%x\n", status);
1926 #ifdef BNX2X_STOP_ON_ERROR
1927 if (unlikely(bp->panic))
1931 for_each_eth_queue(bp, i) {
1932 struct bnx2x_fastpath *fp = &bp->fp[i];
1934 mask = 0x2 << (fp->index + CNIC_SUPPORT(bp));
1935 if (status & mask) {
1936 /* Handle Rx or Tx according to SB id */
1937 for_each_cos_in_tx_queue(fp, cos)
1938 prefetch(fp->txdata_ptr[cos]->tx_cons_sb);
1939 prefetch(&fp->sb_running_index[SM_RX_ID]);
1940 napi_schedule_irqoff(&bnx2x_fp(bp, fp->index, napi));
1945 if (CNIC_SUPPORT(bp)) {
1947 if (status & (mask | 0x1)) {
1948 struct cnic_ops *c_ops = NULL;
1951 c_ops = rcu_dereference(bp->cnic_ops);
1952 if (c_ops && (bp->cnic_eth_dev.drv_state &
1953 CNIC_DRV_STATE_HANDLES_IRQ))
1954 c_ops->cnic_handler(bp->cnic_data, NULL);
1961 if (unlikely(status & 0x1)) {
1963 /* schedule sp task to perform default status block work, ack
1964 * attentions and enable interrupts.
1966 bnx2x_schedule_sp_task(bp);
1973 if (unlikely(status))
1974 DP(NETIF_MSG_INTR, "got an unknown interrupt! (status 0x%x)\n",
1983 * General service functions
1986 int bnx2x_acquire_hw_lock(struct bnx2x *bp, u32 resource)
1989 u32 resource_bit = (1 << resource);
1990 int func = BP_FUNC(bp);
1991 u32 hw_lock_control_reg;
1994 /* Validating that the resource is within range */
1995 if (resource > HW_LOCK_MAX_RESOURCE_VALUE) {
1996 BNX2X_ERR("resource(0x%x) > HW_LOCK_MAX_RESOURCE_VALUE(0x%x)\n",
1997 resource, HW_LOCK_MAX_RESOURCE_VALUE);
2002 hw_lock_control_reg = (MISC_REG_DRIVER_CONTROL_1 + func*8);
2004 hw_lock_control_reg =
2005 (MISC_REG_DRIVER_CONTROL_7 + (func - 6)*8);
2008 /* Validating that the resource is not already taken */
2009 lock_status = REG_RD(bp, hw_lock_control_reg);
2010 if (lock_status & resource_bit) {
2011 BNX2X_ERR("lock_status 0x%x resource_bit 0x%x\n",
2012 lock_status, resource_bit);
2016 /* Try for 5 second every 5ms */
2017 for (cnt = 0; cnt < 1000; cnt++) {
2018 /* Try to acquire the lock */
2019 REG_WR(bp, hw_lock_control_reg + 4, resource_bit);
2020 lock_status = REG_RD(bp, hw_lock_control_reg);
2021 if (lock_status & resource_bit)
2024 usleep_range(5000, 10000);
2026 BNX2X_ERR("Timeout\n");
2030 int bnx2x_release_leader_lock(struct bnx2x *bp)
2032 return bnx2x_release_hw_lock(bp, bnx2x_get_leader_lock_resource(bp));
2035 int bnx2x_release_hw_lock(struct bnx2x *bp, u32 resource)
2038 u32 resource_bit = (1 << resource);
2039 int func = BP_FUNC(bp);
2040 u32 hw_lock_control_reg;
2042 /* Validating that the resource is within range */
2043 if (resource > HW_LOCK_MAX_RESOURCE_VALUE) {
2044 BNX2X_ERR("resource(0x%x) > HW_LOCK_MAX_RESOURCE_VALUE(0x%x)\n",
2045 resource, HW_LOCK_MAX_RESOURCE_VALUE);
2050 hw_lock_control_reg = (MISC_REG_DRIVER_CONTROL_1 + func*8);
2052 hw_lock_control_reg =
2053 (MISC_REG_DRIVER_CONTROL_7 + (func - 6)*8);
2056 /* Validating that the resource is currently taken */
2057 lock_status = REG_RD(bp, hw_lock_control_reg);
2058 if (!(lock_status & resource_bit)) {
2059 BNX2X_ERR("lock_status 0x%x resource_bit 0x%x. Unlock was called but lock wasn't taken!\n",
2060 lock_status, resource_bit);
2064 REG_WR(bp, hw_lock_control_reg, resource_bit);
2068 int bnx2x_get_gpio(struct bnx2x *bp, int gpio_num, u8 port)
2070 /* The GPIO should be swapped if swap register is set and active */
2071 int gpio_port = (REG_RD(bp, NIG_REG_PORT_SWAP) &&
2072 REG_RD(bp, NIG_REG_STRAP_OVERRIDE)) ^ port;
2073 int gpio_shift = gpio_num +
2074 (gpio_port ? MISC_REGISTERS_GPIO_PORT_SHIFT : 0);
2075 u32 gpio_mask = (1 << gpio_shift);
2079 if (gpio_num > MISC_REGISTERS_GPIO_3) {
2080 BNX2X_ERR("Invalid GPIO %d\n", gpio_num);
2084 /* read GPIO value */
2085 gpio_reg = REG_RD(bp, MISC_REG_GPIO);
2087 /* get the requested pin value */
2088 if ((gpio_reg & gpio_mask) == gpio_mask)
2096 int bnx2x_set_gpio(struct bnx2x *bp, int gpio_num, u32 mode, u8 port)
2098 /* The GPIO should be swapped if swap register is set and active */
2099 int gpio_port = (REG_RD(bp, NIG_REG_PORT_SWAP) &&
2100 REG_RD(bp, NIG_REG_STRAP_OVERRIDE)) ^ port;
2101 int gpio_shift = gpio_num +
2102 (gpio_port ? MISC_REGISTERS_GPIO_PORT_SHIFT : 0);
2103 u32 gpio_mask = (1 << gpio_shift);
2106 if (gpio_num > MISC_REGISTERS_GPIO_3) {
2107 BNX2X_ERR("Invalid GPIO %d\n", gpio_num);
2111 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_GPIO);
2112 /* read GPIO and mask except the float bits */
2113 gpio_reg = (REG_RD(bp, MISC_REG_GPIO) & MISC_REGISTERS_GPIO_FLOAT);
2116 case MISC_REGISTERS_GPIO_OUTPUT_LOW:
2118 "Set GPIO %d (shift %d) -> output low\n",
2119 gpio_num, gpio_shift);
2120 /* clear FLOAT and set CLR */
2121 gpio_reg &= ~(gpio_mask << MISC_REGISTERS_GPIO_FLOAT_POS);
2122 gpio_reg |= (gpio_mask << MISC_REGISTERS_GPIO_CLR_POS);
2125 case MISC_REGISTERS_GPIO_OUTPUT_HIGH:
2127 "Set GPIO %d (shift %d) -> output high\n",
2128 gpio_num, gpio_shift);
2129 /* clear FLOAT and set SET */
2130 gpio_reg &= ~(gpio_mask << MISC_REGISTERS_GPIO_FLOAT_POS);
2131 gpio_reg |= (gpio_mask << MISC_REGISTERS_GPIO_SET_POS);
2134 case MISC_REGISTERS_GPIO_INPUT_HI_Z:
2136 "Set GPIO %d (shift %d) -> input\n",
2137 gpio_num, gpio_shift);
2139 gpio_reg |= (gpio_mask << MISC_REGISTERS_GPIO_FLOAT_POS);
2146 REG_WR(bp, MISC_REG_GPIO, gpio_reg);
2147 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_GPIO);
2152 int bnx2x_set_mult_gpio(struct bnx2x *bp, u8 pins, u32 mode)
2157 /* Any port swapping should be handled by caller. */
2159 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_GPIO);
2160 /* read GPIO and mask except the float bits */
2161 gpio_reg = REG_RD(bp, MISC_REG_GPIO);
2162 gpio_reg &= ~(pins << MISC_REGISTERS_GPIO_FLOAT_POS);
2163 gpio_reg &= ~(pins << MISC_REGISTERS_GPIO_CLR_POS);
2164 gpio_reg &= ~(pins << MISC_REGISTERS_GPIO_SET_POS);
2167 case MISC_REGISTERS_GPIO_OUTPUT_LOW:
2168 DP(NETIF_MSG_LINK, "Set GPIO 0x%x -> output low\n", pins);
2170 gpio_reg |= (pins << MISC_REGISTERS_GPIO_CLR_POS);
2173 case MISC_REGISTERS_GPIO_OUTPUT_HIGH:
2174 DP(NETIF_MSG_LINK, "Set GPIO 0x%x -> output high\n", pins);
2176 gpio_reg |= (pins << MISC_REGISTERS_GPIO_SET_POS);
2179 case MISC_REGISTERS_GPIO_INPUT_HI_Z:
2180 DP(NETIF_MSG_LINK, "Set GPIO 0x%x -> input\n", pins);
2182 gpio_reg |= (pins << MISC_REGISTERS_GPIO_FLOAT_POS);
2186 BNX2X_ERR("Invalid GPIO mode assignment %d\n", mode);
2192 REG_WR(bp, MISC_REG_GPIO, gpio_reg);
2194 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_GPIO);
2199 int bnx2x_set_gpio_int(struct bnx2x *bp, int gpio_num, u32 mode, u8 port)
2201 /* The GPIO should be swapped if swap register is set and active */
2202 int gpio_port = (REG_RD(bp, NIG_REG_PORT_SWAP) &&
2203 REG_RD(bp, NIG_REG_STRAP_OVERRIDE)) ^ port;
2204 int gpio_shift = gpio_num +
2205 (gpio_port ? MISC_REGISTERS_GPIO_PORT_SHIFT : 0);
2206 u32 gpio_mask = (1 << gpio_shift);
2209 if (gpio_num > MISC_REGISTERS_GPIO_3) {
2210 BNX2X_ERR("Invalid GPIO %d\n", gpio_num);
2214 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_GPIO);
2216 gpio_reg = REG_RD(bp, MISC_REG_GPIO_INT);
2219 case MISC_REGISTERS_GPIO_INT_OUTPUT_CLR:
2221 "Clear GPIO INT %d (shift %d) -> output low\n",
2222 gpio_num, gpio_shift);
2223 /* clear SET and set CLR */
2224 gpio_reg &= ~(gpio_mask << MISC_REGISTERS_GPIO_INT_SET_POS);
2225 gpio_reg |= (gpio_mask << MISC_REGISTERS_GPIO_INT_CLR_POS);
2228 case MISC_REGISTERS_GPIO_INT_OUTPUT_SET:
2230 "Set GPIO INT %d (shift %d) -> output high\n",
2231 gpio_num, gpio_shift);
2232 /* clear CLR and set SET */
2233 gpio_reg &= ~(gpio_mask << MISC_REGISTERS_GPIO_INT_CLR_POS);
2234 gpio_reg |= (gpio_mask << MISC_REGISTERS_GPIO_INT_SET_POS);
2241 REG_WR(bp, MISC_REG_GPIO_INT, gpio_reg);
2242 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_GPIO);
2247 static int bnx2x_set_spio(struct bnx2x *bp, int spio, u32 mode)
2251 /* Only 2 SPIOs are configurable */
2252 if ((spio != MISC_SPIO_SPIO4) && (spio != MISC_SPIO_SPIO5)) {
2253 BNX2X_ERR("Invalid SPIO 0x%x\n", spio);
2257 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_SPIO);
2258 /* read SPIO and mask except the float bits */
2259 spio_reg = (REG_RD(bp, MISC_REG_SPIO) & MISC_SPIO_FLOAT);
2262 case MISC_SPIO_OUTPUT_LOW:
2263 DP(NETIF_MSG_HW, "Set SPIO 0x%x -> output low\n", spio);
2264 /* clear FLOAT and set CLR */
2265 spio_reg &= ~(spio << MISC_SPIO_FLOAT_POS);
2266 spio_reg |= (spio << MISC_SPIO_CLR_POS);
2269 case MISC_SPIO_OUTPUT_HIGH:
2270 DP(NETIF_MSG_HW, "Set SPIO 0x%x -> output high\n", spio);
2271 /* clear FLOAT and set SET */
2272 spio_reg &= ~(spio << MISC_SPIO_FLOAT_POS);
2273 spio_reg |= (spio << MISC_SPIO_SET_POS);
2276 case MISC_SPIO_INPUT_HI_Z:
2277 DP(NETIF_MSG_HW, "Set SPIO 0x%x -> input\n", spio);
2279 spio_reg |= (spio << MISC_SPIO_FLOAT_POS);
2286 REG_WR(bp, MISC_REG_SPIO, spio_reg);
2287 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_SPIO);
2292 void bnx2x_calc_fc_adv(struct bnx2x *bp)
2294 u8 cfg_idx = bnx2x_get_link_cfg_idx(bp);
2296 bp->port.advertising[cfg_idx] &= ~(ADVERTISED_Asym_Pause |
2298 switch (bp->link_vars.ieee_fc &
2299 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_MASK) {
2300 case MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH:
2301 bp->port.advertising[cfg_idx] |= (ADVERTISED_Asym_Pause |
2305 case MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC:
2306 bp->port.advertising[cfg_idx] |= ADVERTISED_Asym_Pause;
2314 static void bnx2x_set_requested_fc(struct bnx2x *bp)
2316 /* Initialize link parameters structure variables
2317 * It is recommended to turn off RX FC for jumbo frames
2318 * for better performance
2320 if (CHIP_IS_E1x(bp) && (bp->dev->mtu > 5000))
2321 bp->link_params.req_fc_auto_adv = BNX2X_FLOW_CTRL_TX;
2323 bp->link_params.req_fc_auto_adv = BNX2X_FLOW_CTRL_BOTH;
2326 static void bnx2x_init_dropless_fc(struct bnx2x *bp)
2328 u32 pause_enabled = 0;
2330 if (!CHIP_IS_E1(bp) && bp->dropless_fc && bp->link_vars.link_up) {
2331 if (bp->link_vars.flow_ctrl & BNX2X_FLOW_CTRL_TX)
2334 REG_WR(bp, BAR_USTRORM_INTMEM +
2335 USTORM_ETH_PAUSE_ENABLED_OFFSET(BP_PORT(bp)),
2339 DP(NETIF_MSG_IFUP | NETIF_MSG_LINK, "dropless_fc is %s\n",
2340 pause_enabled ? "enabled" : "disabled");
2343 int bnx2x_initial_phy_init(struct bnx2x *bp, int load_mode)
2345 int rc, cfx_idx = bnx2x_get_link_cfg_idx(bp);
2346 u16 req_line_speed = bp->link_params.req_line_speed[cfx_idx];
2348 if (!BP_NOMCP(bp)) {
2349 bnx2x_set_requested_fc(bp);
2350 bnx2x_acquire_phy_lock(bp);
2352 if (load_mode == LOAD_DIAG) {
2353 struct link_params *lp = &bp->link_params;
2354 lp->loopback_mode = LOOPBACK_XGXS;
2355 /* Prefer doing PHY loopback at highest speed */
2356 if (lp->req_line_speed[cfx_idx] < SPEED_20000) {
2357 if (lp->speed_cap_mask[cfx_idx] &
2358 PORT_HW_CFG_SPEED_CAPABILITY_D0_20G)
2359 lp->req_line_speed[cfx_idx] =
2361 else if (lp->speed_cap_mask[cfx_idx] &
2362 PORT_HW_CFG_SPEED_CAPABILITY_D0_10G)
2363 lp->req_line_speed[cfx_idx] =
2366 lp->req_line_speed[cfx_idx] =
2371 if (load_mode == LOAD_LOOPBACK_EXT) {
2372 struct link_params *lp = &bp->link_params;
2373 lp->loopback_mode = LOOPBACK_EXT;
2376 rc = bnx2x_phy_init(&bp->link_params, &bp->link_vars);
2378 bnx2x_release_phy_lock(bp);
2380 bnx2x_init_dropless_fc(bp);
2382 bnx2x_calc_fc_adv(bp);
2384 if (bp->link_vars.link_up) {
2385 bnx2x_stats_handle(bp, STATS_EVENT_LINK_UP);
2386 bnx2x_link_report(bp);
2388 queue_delayed_work(bnx2x_wq, &bp->period_task, 0);
2389 bp->link_params.req_line_speed[cfx_idx] = req_line_speed;
2392 BNX2X_ERR("Bootcode is missing - can not initialize link\n");
2396 void bnx2x_link_set(struct bnx2x *bp)
2398 if (!BP_NOMCP(bp)) {
2399 bnx2x_acquire_phy_lock(bp);
2400 bnx2x_phy_init(&bp->link_params, &bp->link_vars);
2401 bnx2x_release_phy_lock(bp);
2403 bnx2x_init_dropless_fc(bp);
2405 bnx2x_calc_fc_adv(bp);
2407 BNX2X_ERR("Bootcode is missing - can not set link\n");
2410 static void bnx2x__link_reset(struct bnx2x *bp)
2412 if (!BP_NOMCP(bp)) {
2413 bnx2x_acquire_phy_lock(bp);
2414 bnx2x_lfa_reset(&bp->link_params, &bp->link_vars);
2415 bnx2x_release_phy_lock(bp);
2417 BNX2X_ERR("Bootcode is missing - can not reset link\n");
2420 void bnx2x_force_link_reset(struct bnx2x *bp)
2422 bnx2x_acquire_phy_lock(bp);
2423 bnx2x_link_reset(&bp->link_params, &bp->link_vars, 1);
2424 bnx2x_release_phy_lock(bp);
2427 u8 bnx2x_link_test(struct bnx2x *bp, u8 is_serdes)
2431 if (!BP_NOMCP(bp)) {
2432 bnx2x_acquire_phy_lock(bp);
2433 rc = bnx2x_test_link(&bp->link_params, &bp->link_vars,
2435 bnx2x_release_phy_lock(bp);
2437 BNX2X_ERR("Bootcode is missing - can not test link\n");
2442 /* Calculates the sum of vn_min_rates.
2443 It's needed for further normalizing of the min_rates.
2445 sum of vn_min_rates.
2447 0 - if all the min_rates are 0.
2448 In the later case fairness algorithm should be deactivated.
2449 If not all min_rates are zero then those that are zeroes will be set to 1.
2451 static void bnx2x_calc_vn_min(struct bnx2x *bp,
2452 struct cmng_init_input *input)
2457 for (vn = VN_0; vn < BP_MAX_VN_NUM(bp); vn++) {
2458 u32 vn_cfg = bp->mf_config[vn];
2459 u32 vn_min_rate = ((vn_cfg & FUNC_MF_CFG_MIN_BW_MASK) >>
2460 FUNC_MF_CFG_MIN_BW_SHIFT) * 100;
2462 /* Skip hidden vns */
2463 if (vn_cfg & FUNC_MF_CFG_FUNC_HIDE)
2465 /* If min rate is zero - set it to 1 */
2466 else if (!vn_min_rate)
2467 vn_min_rate = DEF_MIN_RATE;
2471 input->vnic_min_rate[vn] = vn_min_rate;
2474 /* if ETS or all min rates are zeros - disable fairness */
2475 if (BNX2X_IS_ETS_ENABLED(bp)) {
2476 input->flags.cmng_enables &=
2477 ~CMNG_FLAGS_PER_PORT_FAIRNESS_VN;
2478 DP(NETIF_MSG_IFUP, "Fairness will be disabled due to ETS\n");
2479 } else if (all_zero) {
2480 input->flags.cmng_enables &=
2481 ~CMNG_FLAGS_PER_PORT_FAIRNESS_VN;
2483 "All MIN values are zeroes fairness will be disabled\n");
2485 input->flags.cmng_enables |=
2486 CMNG_FLAGS_PER_PORT_FAIRNESS_VN;
2489 static void bnx2x_calc_vn_max(struct bnx2x *bp, int vn,
2490 struct cmng_init_input *input)
2493 u32 vn_cfg = bp->mf_config[vn];
2495 if (vn_cfg & FUNC_MF_CFG_FUNC_HIDE)
2498 u32 maxCfg = bnx2x_extract_max_cfg(bp, vn_cfg);
2500 if (IS_MF_PERCENT_BW(bp)) {
2501 /* maxCfg in percents of linkspeed */
2502 vn_max_rate = (bp->link_vars.line_speed * maxCfg) / 100;
2503 } else /* SD modes */
2504 /* maxCfg is absolute in 100Mb units */
2505 vn_max_rate = maxCfg * 100;
2508 DP(NETIF_MSG_IFUP, "vn %d: vn_max_rate %d\n", vn, vn_max_rate);
2510 input->vnic_max_rate[vn] = vn_max_rate;
2513 static int bnx2x_get_cmng_fns_mode(struct bnx2x *bp)
2515 if (CHIP_REV_IS_SLOW(bp))
2516 return CMNG_FNS_NONE;
2518 return CMNG_FNS_MINMAX;
2520 return CMNG_FNS_NONE;
2523 void bnx2x_read_mf_cfg(struct bnx2x *bp)
2525 int vn, n = (CHIP_MODE_IS_4_PORT(bp) ? 2 : 1);
2528 return; /* what should be the default value in this case */
2530 /* For 2 port configuration the absolute function number formula
2532 * abs_func = 2 * vn + BP_PORT + BP_PATH
2534 * and there are 4 functions per port
2536 * For 4 port configuration it is
2537 * abs_func = 4 * vn + 2 * BP_PORT + BP_PATH
2539 * and there are 2 functions per port
2541 for (vn = VN_0; vn < BP_MAX_VN_NUM(bp); vn++) {
2542 int /*abs*/func = n * (2 * vn + BP_PORT(bp)) + BP_PATH(bp);
2544 if (func >= E1H_FUNC_MAX)
2548 MF_CFG_RD(bp, func_mf_config[func].config);
2550 if (bp->mf_config[BP_VN(bp)] & FUNC_MF_CFG_FUNC_DISABLED) {
2551 DP(NETIF_MSG_IFUP, "mf_cfg function disabled\n");
2552 bp->flags |= MF_FUNC_DIS;
2554 DP(NETIF_MSG_IFUP, "mf_cfg function enabled\n");
2555 bp->flags &= ~MF_FUNC_DIS;
2559 static void bnx2x_cmng_fns_init(struct bnx2x *bp, u8 read_cfg, u8 cmng_type)
2561 struct cmng_init_input input;
2562 memset(&input, 0, sizeof(struct cmng_init_input));
2564 input.port_rate = bp->link_vars.line_speed;
2566 if (cmng_type == CMNG_FNS_MINMAX && input.port_rate) {
2569 /* read mf conf from shmem */
2571 bnx2x_read_mf_cfg(bp);
2573 /* vn_weight_sum and enable fairness if not 0 */
2574 bnx2x_calc_vn_min(bp, &input);
2576 /* calculate and set min-max rate for each vn */
2578 for (vn = VN_0; vn < BP_MAX_VN_NUM(bp); vn++)
2579 bnx2x_calc_vn_max(bp, vn, &input);
2581 /* always enable rate shaping and fairness */
2582 input.flags.cmng_enables |=
2583 CMNG_FLAGS_PER_PORT_RATE_SHAPING_VN;
2585 bnx2x_init_cmng(&input, &bp->cmng);
2589 /* rate shaping and fairness are disabled */
2591 "rate shaping and fairness are disabled\n");
2594 static void storm_memset_cmng(struct bnx2x *bp,
2595 struct cmng_init *cmng,
2599 size_t size = sizeof(struct cmng_struct_per_port);
2601 u32 addr = BAR_XSTRORM_INTMEM +
2602 XSTORM_CMNG_PER_PORT_VARS_OFFSET(port);
2604 __storm_memset_struct(bp, addr, size, (u32 *)&cmng->port);
2606 for (vn = VN_0; vn < BP_MAX_VN_NUM(bp); vn++) {
2607 int func = func_by_vn(bp, vn);
2609 addr = BAR_XSTRORM_INTMEM +
2610 XSTORM_RATE_SHAPING_PER_VN_VARS_OFFSET(func);
2611 size = sizeof(struct rate_shaping_vars_per_vn);
2612 __storm_memset_struct(bp, addr, size,
2613 (u32 *)&cmng->vnic.vnic_max_rate[vn]);
2615 addr = BAR_XSTRORM_INTMEM +
2616 XSTORM_FAIRNESS_PER_VN_VARS_OFFSET(func);
2617 size = sizeof(struct fairness_vars_per_vn);
2618 __storm_memset_struct(bp, addr, size,
2619 (u32 *)&cmng->vnic.vnic_min_rate[vn]);
2623 /* init cmng mode in HW according to local configuration */
2624 void bnx2x_set_local_cmng(struct bnx2x *bp)
2626 int cmng_fns = bnx2x_get_cmng_fns_mode(bp);
2628 if (cmng_fns != CMNG_FNS_NONE) {
2629 bnx2x_cmng_fns_init(bp, false, cmng_fns);
2630 storm_memset_cmng(bp, &bp->cmng, BP_PORT(bp));
2632 /* rate shaping and fairness are disabled */
2634 "single function mode without fairness\n");
2638 /* This function is called upon link interrupt */
2639 static void bnx2x_link_attn(struct bnx2x *bp)
2641 /* Make sure that we are synced with the current statistics */
2642 bnx2x_stats_handle(bp, STATS_EVENT_STOP);
2644 bnx2x_link_update(&bp->link_params, &bp->link_vars);
2646 bnx2x_init_dropless_fc(bp);
2648 if (bp->link_vars.link_up) {
2650 if (bp->link_vars.mac_type != MAC_TYPE_EMAC) {
2651 struct host_port_stats *pstats;
2653 pstats = bnx2x_sp(bp, port_stats);
2654 /* reset old mac stats */
2655 memset(&(pstats->mac_stx[0]), 0,
2656 sizeof(struct mac_stx));
2658 if (bp->state == BNX2X_STATE_OPEN)
2659 bnx2x_stats_handle(bp, STATS_EVENT_LINK_UP);
2662 if (bp->link_vars.link_up && bp->link_vars.line_speed)
2663 bnx2x_set_local_cmng(bp);
2665 __bnx2x_link_report(bp);
2668 bnx2x_link_sync_notify(bp);
2671 void bnx2x__link_status_update(struct bnx2x *bp)
2673 if (bp->state != BNX2X_STATE_OPEN)
2676 /* read updated dcb configuration */
2678 bnx2x_dcbx_pmf_update(bp);
2679 bnx2x_link_status_update(&bp->link_params, &bp->link_vars);
2680 if (bp->link_vars.link_up)
2681 bnx2x_stats_handle(bp, STATS_EVENT_LINK_UP);
2683 bnx2x_stats_handle(bp, STATS_EVENT_STOP);
2684 /* indicate link status */
2685 bnx2x_link_report(bp);
2688 bp->port.supported[0] |= (SUPPORTED_10baseT_Half |
2689 SUPPORTED_10baseT_Full |
2690 SUPPORTED_100baseT_Half |
2691 SUPPORTED_100baseT_Full |
2692 SUPPORTED_1000baseT_Full |
2693 SUPPORTED_2500baseX_Full |
2694 SUPPORTED_10000baseT_Full |
2699 SUPPORTED_Asym_Pause);
2700 bp->port.advertising[0] = bp->port.supported[0];
2702 bp->link_params.bp = bp;
2703 bp->link_params.port = BP_PORT(bp);
2704 bp->link_params.req_duplex[0] = DUPLEX_FULL;
2705 bp->link_params.req_flow_ctrl[0] = BNX2X_FLOW_CTRL_NONE;
2706 bp->link_params.req_line_speed[0] = SPEED_10000;
2707 bp->link_params.speed_cap_mask[0] = 0x7f0000;
2708 bp->link_params.switch_cfg = SWITCH_CFG_10G;
2709 bp->link_vars.mac_type = MAC_TYPE_BMAC;
2710 bp->link_vars.line_speed = SPEED_10000;
2711 bp->link_vars.link_status =
2712 (LINK_STATUS_LINK_UP |
2713 LINK_STATUS_SPEED_AND_DUPLEX_10GTFD);
2714 bp->link_vars.link_up = 1;
2715 bp->link_vars.duplex = DUPLEX_FULL;
2716 bp->link_vars.flow_ctrl = BNX2X_FLOW_CTRL_NONE;
2717 __bnx2x_link_report(bp);
2719 bnx2x_sample_bulletin(bp);
2721 /* if bulletin board did not have an update for link status
2722 * __bnx2x_link_report will report current status
2723 * but it will NOT duplicate report in case of already reported
2724 * during sampling bulletin board.
2726 bnx2x_stats_handle(bp, STATS_EVENT_LINK_UP);
2730 static int bnx2x_afex_func_update(struct bnx2x *bp, u16 vifid,
2731 u16 vlan_val, u8 allowed_prio)
2733 struct bnx2x_func_state_params func_params = {NULL};
2734 struct bnx2x_func_afex_update_params *f_update_params =
2735 &func_params.params.afex_update;
2737 func_params.f_obj = &bp->func_obj;
2738 func_params.cmd = BNX2X_F_CMD_AFEX_UPDATE;
2740 /* no need to wait for RAMROD completion, so don't
2741 * set RAMROD_COMP_WAIT flag
2744 f_update_params->vif_id = vifid;
2745 f_update_params->afex_default_vlan = vlan_val;
2746 f_update_params->allowed_priorities = allowed_prio;
2748 /* if ramrod can not be sent, response to MCP immediately */
2749 if (bnx2x_func_state_change(bp, &func_params) < 0)
2750 bnx2x_fw_command(bp, DRV_MSG_CODE_AFEX_VIFSET_ACK, 0);
2755 static int bnx2x_afex_handle_vif_list_cmd(struct bnx2x *bp, u8 cmd_type,
2756 u16 vif_index, u8 func_bit_map)
2758 struct bnx2x_func_state_params func_params = {NULL};
2759 struct bnx2x_func_afex_viflists_params *update_params =
2760 &func_params.params.afex_viflists;
2764 /* validate only LIST_SET and LIST_GET are received from switch */
2765 if ((cmd_type != VIF_LIST_RULE_GET) && (cmd_type != VIF_LIST_RULE_SET))
2766 BNX2X_ERR("BUG! afex_handle_vif_list_cmd invalid type 0x%x\n",
2769 func_params.f_obj = &bp->func_obj;
2770 func_params.cmd = BNX2X_F_CMD_AFEX_VIFLISTS;
2772 /* set parameters according to cmd_type */
2773 update_params->afex_vif_list_command = cmd_type;
2774 update_params->vif_list_index = vif_index;
2775 update_params->func_bit_map =
2776 (cmd_type == VIF_LIST_RULE_GET) ? 0 : func_bit_map;
2777 update_params->func_to_clear = 0;
2779 (cmd_type == VIF_LIST_RULE_GET) ?
2780 DRV_MSG_CODE_AFEX_LISTGET_ACK :
2781 DRV_MSG_CODE_AFEX_LISTSET_ACK;
2783 /* if ramrod can not be sent, respond to MCP immediately for
2784 * SET and GET requests (other are not triggered from MCP)
2786 rc = bnx2x_func_state_change(bp, &func_params);
2788 bnx2x_fw_command(bp, drv_msg_code, 0);
2793 static void bnx2x_handle_afex_cmd(struct bnx2x *bp, u32 cmd)
2795 struct afex_stats afex_stats;
2796 u32 func = BP_ABS_FUNC(bp);
2803 u32 addr_to_write, vifid, addrs, stats_type, i;
2805 if (cmd & DRV_STATUS_AFEX_LISTGET_REQ) {
2806 vifid = SHMEM2_RD(bp, afex_param1_to_driver[BP_FW_MB_IDX(bp)]);
2808 "afex: got MCP req LISTGET_REQ for vifid 0x%x\n", vifid);
2809 bnx2x_afex_handle_vif_list_cmd(bp, VIF_LIST_RULE_GET, vifid, 0);
2812 if (cmd & DRV_STATUS_AFEX_LISTSET_REQ) {
2813 vifid = SHMEM2_RD(bp, afex_param1_to_driver[BP_FW_MB_IDX(bp)]);
2814 addrs = SHMEM2_RD(bp, afex_param2_to_driver[BP_FW_MB_IDX(bp)]);
2816 "afex: got MCP req LISTSET_REQ for vifid 0x%x addrs 0x%x\n",
2818 bnx2x_afex_handle_vif_list_cmd(bp, VIF_LIST_RULE_SET, vifid,
2822 if (cmd & DRV_STATUS_AFEX_STATSGET_REQ) {
2823 addr_to_write = SHMEM2_RD(bp,
2824 afex_scratchpad_addr_to_write[BP_FW_MB_IDX(bp)]);
2825 stats_type = SHMEM2_RD(bp,
2826 afex_param1_to_driver[BP_FW_MB_IDX(bp)]);
2829 "afex: got MCP req STATSGET_REQ, write to addr 0x%x\n",
2832 bnx2x_afex_collect_stats(bp, (void *)&afex_stats, stats_type);
2834 /* write response to scratchpad, for MCP */
2835 for (i = 0; i < (sizeof(struct afex_stats)/sizeof(u32)); i++)
2836 REG_WR(bp, addr_to_write + i*sizeof(u32),
2837 *(((u32 *)(&afex_stats))+i));
2839 /* send ack message to MCP */
2840 bnx2x_fw_command(bp, DRV_MSG_CODE_AFEX_STATSGET_ACK, 0);
2843 if (cmd & DRV_STATUS_AFEX_VIFSET_REQ) {
2844 mf_config = MF_CFG_RD(bp, func_mf_config[func].config);
2845 bp->mf_config[BP_VN(bp)] = mf_config;
2847 "afex: got MCP req VIFSET_REQ, mf_config 0x%x\n",
2850 /* if VIF_SET is "enabled" */
2851 if (!(mf_config & FUNC_MF_CFG_FUNC_DISABLED)) {
2852 /* set rate limit directly to internal RAM */
2853 struct cmng_init_input cmng_input;
2854 struct rate_shaping_vars_per_vn m_rs_vn;
2855 size_t size = sizeof(struct rate_shaping_vars_per_vn);
2856 u32 addr = BAR_XSTRORM_INTMEM +
2857 XSTORM_RATE_SHAPING_PER_VN_VARS_OFFSET(BP_FUNC(bp));
2859 bp->mf_config[BP_VN(bp)] = mf_config;
2861 bnx2x_calc_vn_max(bp, BP_VN(bp), &cmng_input);
2862 m_rs_vn.vn_counter.rate =
2863 cmng_input.vnic_max_rate[BP_VN(bp)];
2864 m_rs_vn.vn_counter.quota =
2865 (m_rs_vn.vn_counter.rate *
2866 RS_PERIODIC_TIMEOUT_USEC) / 8;
2868 __storm_memset_struct(bp, addr, size, (u32 *)&m_rs_vn);
2870 /* read relevant values from mf_cfg struct in shmem */
2872 (MF_CFG_RD(bp, func_mf_config[func].e1hov_tag) &
2873 FUNC_MF_CFG_E1HOV_TAG_MASK) >>
2874 FUNC_MF_CFG_E1HOV_TAG_SHIFT;
2876 (MF_CFG_RD(bp, func_mf_config[func].e1hov_tag) &
2877 FUNC_MF_CFG_AFEX_VLAN_MASK) >>
2878 FUNC_MF_CFG_AFEX_VLAN_SHIFT;
2879 vlan_prio = (mf_config &
2880 FUNC_MF_CFG_TRANSMIT_PRIORITY_MASK) >>
2881 FUNC_MF_CFG_TRANSMIT_PRIORITY_SHIFT;
2882 vlan_val |= (vlan_prio << VLAN_PRIO_SHIFT);
2885 func_mf_config[func].afex_config) &
2886 FUNC_MF_CFG_AFEX_VLAN_MODE_MASK) >>
2887 FUNC_MF_CFG_AFEX_VLAN_MODE_SHIFT;
2890 func_mf_config[func].afex_config) &
2891 FUNC_MF_CFG_AFEX_COS_FILTER_MASK) >>
2892 FUNC_MF_CFG_AFEX_COS_FILTER_SHIFT;
2894 /* send ramrod to FW, return in case of failure */
2895 if (bnx2x_afex_func_update(bp, vif_id, vlan_val,
2899 bp->afex_def_vlan_tag = vlan_val;
2900 bp->afex_vlan_mode = vlan_mode;
2902 /* notify link down because BP->flags is disabled */
2903 bnx2x_link_report(bp);
2905 /* send INVALID VIF ramrod to FW */
2906 bnx2x_afex_func_update(bp, 0xFFFF, 0, 0);
2908 /* Reset the default afex VLAN */
2909 bp->afex_def_vlan_tag = -1;
2914 static void bnx2x_handle_update_svid_cmd(struct bnx2x *bp)
2916 struct bnx2x_func_switch_update_params *switch_update_params;
2917 struct bnx2x_func_state_params func_params;
2919 memset(&func_params, 0, sizeof(struct bnx2x_func_state_params));
2920 switch_update_params = &func_params.params.switch_update;
2921 func_params.f_obj = &bp->func_obj;
2922 func_params.cmd = BNX2X_F_CMD_SWITCH_UPDATE;
2924 if (IS_MF_UFP(bp) || IS_MF_BD(bp)) {
2925 int func = BP_ABS_FUNC(bp);
2928 /* Re-learn the S-tag from shmem */
2929 val = MF_CFG_RD(bp, func_mf_config[func].e1hov_tag) &
2930 FUNC_MF_CFG_E1HOV_TAG_MASK;
2931 if (val != FUNC_MF_CFG_E1HOV_TAG_DEFAULT) {
2934 BNX2X_ERR("Got an SVID event, but no tag is configured in shmem\n");
2938 /* Configure new S-tag in LLH */
2939 REG_WR(bp, NIG_REG_LLH0_FUNC_VLAN_ID + BP_PORT(bp) * 8,
2942 /* Send Ramrod to update FW of change */
2943 __set_bit(BNX2X_F_UPDATE_SD_VLAN_TAG_CHNG,
2944 &switch_update_params->changes);
2945 switch_update_params->vlan = bp->mf_ov;
2947 if (bnx2x_func_state_change(bp, &func_params) < 0) {
2948 BNX2X_ERR("Failed to configure FW of S-tag Change to %02x\n",
2952 DP(BNX2X_MSG_MCP, "Configured S-tag %02x\n",
2959 bnx2x_fw_command(bp, DRV_MSG_CODE_OEM_UPDATE_SVID_OK, 0);
2962 bnx2x_fw_command(bp, DRV_MSG_CODE_OEM_UPDATE_SVID_FAILURE, 0);
2965 static void bnx2x_pmf_update(struct bnx2x *bp)
2967 int port = BP_PORT(bp);
2971 DP(BNX2X_MSG_MCP, "pmf %d\n", bp->port.pmf);
2974 * We need the mb() to ensure the ordering between the writing to
2975 * bp->port.pmf here and reading it from the bnx2x_periodic_task().
2979 /* queue a periodic task */
2980 queue_delayed_work(bnx2x_wq, &bp->period_task, 0);
2982 bnx2x_dcbx_pmf_update(bp);
2984 /* enable nig attention */
2985 val = (0xff0f | (1 << (BP_VN(bp) + 4)));
2986 if (bp->common.int_block == INT_BLOCK_HC) {
2987 REG_WR(bp, HC_REG_TRAILING_EDGE_0 + port*8, val);
2988 REG_WR(bp, HC_REG_LEADING_EDGE_0 + port*8, val);
2989 } else if (!CHIP_IS_E1x(bp)) {
2990 REG_WR(bp, IGU_REG_TRAILING_EDGE_LATCH, val);
2991 REG_WR(bp, IGU_REG_LEADING_EDGE_LATCH, val);
2994 bnx2x_stats_handle(bp, STATS_EVENT_PMF);
3002 * General service functions
3005 /* send the MCP a request, block until there is a reply */
3006 u32 bnx2x_fw_command(struct bnx2x *bp, u32 command, u32 param)
3008 int mb_idx = BP_FW_MB_IDX(bp);
3012 u8 delay = CHIP_REV_IS_SLOW(bp) ? 100 : 10;
3014 mutex_lock(&bp->fw_mb_mutex);
3016 SHMEM_WR(bp, func_mb[mb_idx].drv_mb_param, param);
3017 SHMEM_WR(bp, func_mb[mb_idx].drv_mb_header, (command | seq));
3019 DP(BNX2X_MSG_MCP, "wrote command (%x) to FW MB param 0x%08x\n",
3020 (command | seq), param);
3023 /* let the FW do it's magic ... */
3026 rc = SHMEM_RD(bp, func_mb[mb_idx].fw_mb_header);
3028 /* Give the FW up to 5 second (500*10ms) */
3029 } while ((seq != (rc & FW_MSG_SEQ_NUMBER_MASK)) && (cnt++ < 500));
3031 DP(BNX2X_MSG_MCP, "[after %d ms] read (%x) seq is (%x) from FW MB\n",
3032 cnt*delay, rc, seq);
3034 /* is this a reply to our command? */
3035 if (seq == (rc & FW_MSG_SEQ_NUMBER_MASK))
3036 rc &= FW_MSG_CODE_MASK;
3039 BNX2X_ERR("FW failed to respond!\n");
3043 mutex_unlock(&bp->fw_mb_mutex);
3048 static void storm_memset_func_cfg(struct bnx2x *bp,
3049 struct tstorm_eth_function_common_config *tcfg,
3052 size_t size = sizeof(struct tstorm_eth_function_common_config);
3054 u32 addr = BAR_TSTRORM_INTMEM +
3055 TSTORM_FUNCTION_COMMON_CONFIG_OFFSET(abs_fid);
3057 __storm_memset_struct(bp, addr, size, (u32 *)tcfg);
3060 void bnx2x_func_init(struct bnx2x *bp, struct bnx2x_func_init_params *p)
3062 if (CHIP_IS_E1x(bp)) {
3063 struct tstorm_eth_function_common_config tcfg = {0};
3065 storm_memset_func_cfg(bp, &tcfg, p->func_id);
3068 /* Enable the function in the FW */
3069 storm_memset_vf_to_pf(bp, p->func_id, p->pf_id);
3070 storm_memset_func_en(bp, p->func_id, 1);
3073 if (p->spq_active) {
3074 storm_memset_spq_addr(bp, p->spq_map, p->func_id);
3075 REG_WR(bp, XSEM_REG_FAST_MEMORY +
3076 XSTORM_SPQ_PROD_OFFSET(p->func_id), p->spq_prod);
3081 * bnx2x_get_common_flags - Return common flags
3085 * @zero_stats TRUE if statistics zeroing is needed
3087 * Return the flags that are common for the Tx-only and not normal connections.
3089 static unsigned long bnx2x_get_common_flags(struct bnx2x *bp,
3090 struct bnx2x_fastpath *fp,
3093 unsigned long flags = 0;
3095 /* PF driver will always initialize the Queue to an ACTIVE state */
3096 __set_bit(BNX2X_Q_FLG_ACTIVE, &flags);
3098 /* tx only connections collect statistics (on the same index as the
3099 * parent connection). The statistics are zeroed when the parent
3100 * connection is initialized.
3103 __set_bit(BNX2X_Q_FLG_STATS, &flags);
3105 __set_bit(BNX2X_Q_FLG_ZERO_STATS, &flags);
3107 if (bp->flags & TX_SWITCHING)
3108 __set_bit(BNX2X_Q_FLG_TX_SWITCH, &flags);
3110 __set_bit(BNX2X_Q_FLG_PCSUM_ON_PKT, &flags);
3111 __set_bit(BNX2X_Q_FLG_TUN_INC_INNER_IP_ID, &flags);
3113 #ifdef BNX2X_STOP_ON_ERROR
3114 __set_bit(BNX2X_Q_FLG_TX_SEC, &flags);
3120 static unsigned long bnx2x_get_q_flags(struct bnx2x *bp,
3121 struct bnx2x_fastpath *fp,
3124 unsigned long flags = 0;
3126 /* calculate other queue flags */
3128 __set_bit(BNX2X_Q_FLG_OV, &flags);
3130 if (IS_FCOE_FP(fp)) {
3131 __set_bit(BNX2X_Q_FLG_FCOE, &flags);
3132 /* For FCoE - force usage of default priority (for afex) */
3133 __set_bit(BNX2X_Q_FLG_FORCE_DEFAULT_PRI, &flags);
3136 if (fp->mode != TPA_MODE_DISABLED) {
3137 __set_bit(BNX2X_Q_FLG_TPA, &flags);
3138 __set_bit(BNX2X_Q_FLG_TPA_IPV6, &flags);
3139 if (fp->mode == TPA_MODE_GRO)
3140 __set_bit(BNX2X_Q_FLG_TPA_GRO, &flags);
3144 __set_bit(BNX2X_Q_FLG_LEADING_RSS, &flags);
3145 __set_bit(BNX2X_Q_FLG_MCAST, &flags);
3148 /* Always set HW VLAN stripping */
3149 __set_bit(BNX2X_Q_FLG_VLAN, &flags);
3151 /* configure silent vlan removal */
3153 __set_bit(BNX2X_Q_FLG_SILENT_VLAN_REM, &flags);
3155 return flags | bnx2x_get_common_flags(bp, fp, true);
3158 static void bnx2x_pf_q_prep_general(struct bnx2x *bp,
3159 struct bnx2x_fastpath *fp, struct bnx2x_general_setup_params *gen_init,
3162 gen_init->stat_id = bnx2x_stats_id(fp);
3163 gen_init->spcl_id = fp->cl_id;
3165 /* Always use mini-jumbo MTU for FCoE L2 ring */
3167 gen_init->mtu = BNX2X_FCOE_MINI_JUMBO_MTU;
3169 gen_init->mtu = bp->dev->mtu;
3171 gen_init->cos = cos;
3173 gen_init->fp_hsi = ETH_FP_HSI_VERSION;
3176 static void bnx2x_pf_rx_q_prep(struct bnx2x *bp,
3177 struct bnx2x_fastpath *fp, struct rxq_pause_params *pause,
3178 struct bnx2x_rxq_setup_params *rxq_init)
3182 u16 tpa_agg_size = 0;
3184 if (fp->mode != TPA_MODE_DISABLED) {
3185 pause->sge_th_lo = SGE_TH_LO(bp);
3186 pause->sge_th_hi = SGE_TH_HI(bp);
3188 /* validate SGE ring has enough to cross high threshold */
3189 WARN_ON(bp->dropless_fc &&
3190 pause->sge_th_hi + FW_PREFETCH_CNT >
3191 MAX_RX_SGE_CNT * NUM_RX_SGE_PAGES);
3193 tpa_agg_size = TPA_AGG_SIZE;
3194 max_sge = SGE_PAGE_ALIGN(bp->dev->mtu) >>
3196 max_sge = ((max_sge + PAGES_PER_SGE - 1) &
3197 (~(PAGES_PER_SGE-1))) >> PAGES_PER_SGE_SHIFT;
3198 sge_sz = (u16)min_t(u32, SGE_PAGES, 0xffff);
3201 /* pause - not for e1 */
3202 if (!CHIP_IS_E1(bp)) {
3203 pause->bd_th_lo = BD_TH_LO(bp);
3204 pause->bd_th_hi = BD_TH_HI(bp);
3206 pause->rcq_th_lo = RCQ_TH_LO(bp);
3207 pause->rcq_th_hi = RCQ_TH_HI(bp);
3209 * validate that rings have enough entries to cross
3212 WARN_ON(bp->dropless_fc &&
3213 pause->bd_th_hi + FW_PREFETCH_CNT >
3215 WARN_ON(bp->dropless_fc &&
3216 pause->rcq_th_hi + FW_PREFETCH_CNT >
3217 NUM_RCQ_RINGS * MAX_RCQ_DESC_CNT);
3223 rxq_init->dscr_map = fp->rx_desc_mapping;
3224 rxq_init->sge_map = fp->rx_sge_mapping;
3225 rxq_init->rcq_map = fp->rx_comp_mapping;
3226 rxq_init->rcq_np_map = fp->rx_comp_mapping + BCM_PAGE_SIZE;
3228 /* This should be a maximum number of data bytes that may be
3229 * placed on the BD (not including paddings).
3231 rxq_init->buf_sz = fp->rx_buf_size - BNX2X_FW_RX_ALIGN_START -
3232 BNX2X_FW_RX_ALIGN_END - IP_HEADER_ALIGNMENT_PADDING;
3234 rxq_init->cl_qzone_id = fp->cl_qzone_id;
3235 rxq_init->tpa_agg_sz = tpa_agg_size;
3236 rxq_init->sge_buf_sz = sge_sz;
3237 rxq_init->max_sges_pkt = max_sge;
3238 rxq_init->rss_engine_id = BP_FUNC(bp);
3239 rxq_init->mcast_engine_id = BP_FUNC(bp);
3241 /* Maximum number or simultaneous TPA aggregation for this Queue.
3243 * For PF Clients it should be the maximum available number.
3244 * VF driver(s) may want to define it to a smaller value.
3246 rxq_init->max_tpa_queues = MAX_AGG_QS(bp);
3248 rxq_init->cache_line_log = BNX2X_RX_ALIGN_SHIFT;
3249 rxq_init->fw_sb_id = fp->fw_sb_id;
3252 rxq_init->sb_cq_index = HC_SP_INDEX_ETH_FCOE_RX_CQ_CONS;
3254 rxq_init->sb_cq_index = HC_INDEX_ETH_RX_CQ_CONS;
3255 /* configure silent vlan removal
3256 * if multi function mode is afex, then mask default vlan
3258 if (IS_MF_AFEX(bp)) {
3259 rxq_init->silent_removal_value = bp->afex_def_vlan_tag;
3260 rxq_init->silent_removal_mask = VLAN_VID_MASK;
3264 static void bnx2x_pf_tx_q_prep(struct bnx2x *bp,
3265 struct bnx2x_fastpath *fp, struct bnx2x_txq_setup_params *txq_init,
3268 txq_init->dscr_map = fp->txdata_ptr[cos]->tx_desc_mapping;
3269 txq_init->sb_cq_index = HC_INDEX_ETH_FIRST_TX_CQ_CONS + cos;
3270 txq_init->traffic_type = LLFC_TRAFFIC_TYPE_NW;
3271 txq_init->fw_sb_id = fp->fw_sb_id;
3274 * set the tss leading client id for TX classification ==
3275 * leading RSS client id
3277 txq_init->tss_leading_cl_id = bnx2x_fp(bp, 0, cl_id);
3279 if (IS_FCOE_FP(fp)) {
3280 txq_init->sb_cq_index = HC_SP_INDEX_ETH_FCOE_TX_CQ_CONS;
3281 txq_init->traffic_type = LLFC_TRAFFIC_TYPE_FCOE;
3285 static void bnx2x_pf_init(struct bnx2x *bp)
3287 struct bnx2x_func_init_params func_init = {0};
3288 struct event_ring_data eq_data = { {0} };
3290 if (!CHIP_IS_E1x(bp)) {
3291 /* reset IGU PF statistics: MSIX + ATTN */
3293 REG_WR(bp, IGU_REG_STATISTIC_NUM_MESSAGE_SENT +
3294 BNX2X_IGU_STAS_MSG_VF_CNT*4 +
3295 (CHIP_MODE_IS_4_PORT(bp) ?
3296 BP_FUNC(bp) : BP_VN(bp))*4, 0);
3298 REG_WR(bp, IGU_REG_STATISTIC_NUM_MESSAGE_SENT +
3299 BNX2X_IGU_STAS_MSG_VF_CNT*4 +
3300 BNX2X_IGU_STAS_MSG_PF_CNT*4 +
3301 (CHIP_MODE_IS_4_PORT(bp) ?
3302 BP_FUNC(bp) : BP_VN(bp))*4, 0);
3305 func_init.spq_active = true;
3306 func_init.pf_id = BP_FUNC(bp);
3307 func_init.func_id = BP_FUNC(bp);
3308 func_init.spq_map = bp->spq_mapping;
3309 func_init.spq_prod = bp->spq_prod_idx;
3311 bnx2x_func_init(bp, &func_init);
3313 memset(&(bp->cmng), 0, sizeof(struct cmng_struct_per_port));
3316 * Congestion management values depend on the link rate
3317 * There is no active link so initial link rate is set to 10 Gbps.
3318 * When the link comes up The congestion management values are
3319 * re-calculated according to the actual link rate.
3321 bp->link_vars.line_speed = SPEED_10000;
3322 bnx2x_cmng_fns_init(bp, true, bnx2x_get_cmng_fns_mode(bp));
3324 /* Only the PMF sets the HW */
3326 storm_memset_cmng(bp, &bp->cmng, BP_PORT(bp));
3328 /* init Event Queue - PCI bus guarantees correct endianity*/
3329 eq_data.base_addr.hi = U64_HI(bp->eq_mapping);
3330 eq_data.base_addr.lo = U64_LO(bp->eq_mapping);
3331 eq_data.producer = bp->eq_prod;
3332 eq_data.index_id = HC_SP_INDEX_EQ_CONS;
3333 eq_data.sb_id = DEF_SB_ID;
3334 storm_memset_eq_data(bp, &eq_data, BP_FUNC(bp));
3337 static void bnx2x_e1h_disable(struct bnx2x *bp)
3339 int port = BP_PORT(bp);
3341 bnx2x_tx_disable(bp);
3343 REG_WR(bp, NIG_REG_LLH0_FUNC_EN + port*8, 0);
3346 static void bnx2x_e1h_enable(struct bnx2x *bp)
3348 int port = BP_PORT(bp);
3350 if (!(IS_MF_UFP(bp) && BNX2X_IS_MF_SD_PROTOCOL_FCOE(bp)))
3351 REG_WR(bp, NIG_REG_LLH0_FUNC_EN + port * 8, 1);
3353 /* Tx queue should be only re-enabled */
3354 netif_tx_wake_all_queues(bp->dev);
3357 * Should not call netif_carrier_on since it will be called if the link
3358 * is up when checking for link state
3362 #define DRV_INFO_ETH_STAT_NUM_MACS_REQUIRED 3
3364 static void bnx2x_drv_info_ether_stat(struct bnx2x *bp)
3366 struct eth_stats_info *ether_stat =
3367 &bp->slowpath->drv_info_to_mcp.ether_stat;
3368 struct bnx2x_vlan_mac_obj *mac_obj =
3369 &bp->sp_objs->mac_obj;
3372 strlcpy(ether_stat->version, DRV_MODULE_VERSION,
3373 ETH_STAT_INFO_VERSION_LEN);
3375 /* get DRV_INFO_ETH_STAT_NUM_MACS_REQUIRED macs, placing them in the
3376 * mac_local field in ether_stat struct. The base address is offset by 2
3377 * bytes to account for the field being 8 bytes but a mac address is
3378 * only 6 bytes. Likewise, the stride for the get_n_elements function is
3379 * 2 bytes to compensate from the 6 bytes of a mac to the 8 bytes
3380 * allocated by the ether_stat struct, so the macs will land in their
3383 for (i = 0; i < DRV_INFO_ETH_STAT_NUM_MACS_REQUIRED; i++)
3384 memset(ether_stat->mac_local + i, 0,
3385 sizeof(ether_stat->mac_local[0]));
3386 mac_obj->get_n_elements(bp, &bp->sp_objs[0].mac_obj,
3387 DRV_INFO_ETH_STAT_NUM_MACS_REQUIRED,
3388 ether_stat->mac_local + MAC_PAD, MAC_PAD,
3390 ether_stat->mtu_size = bp->dev->mtu;
3391 if (bp->dev->features & NETIF_F_RXCSUM)
3392 ether_stat->feature_flags |= FEATURE_ETH_CHKSUM_OFFLOAD_MASK;
3393 if (bp->dev->features & NETIF_F_TSO)
3394 ether_stat->feature_flags |= FEATURE_ETH_LSO_MASK;
3395 ether_stat->feature_flags |= bp->common.boot_mode;
3397 ether_stat->promiscuous_mode = (bp->dev->flags & IFF_PROMISC) ? 1 : 0;
3399 ether_stat->txq_size = bp->tx_ring_size;
3400 ether_stat->rxq_size = bp->rx_ring_size;
3402 #ifdef CONFIG_BNX2X_SRIOV
3403 ether_stat->vf_cnt = IS_SRIOV(bp) ? bp->vfdb->sriov.nr_virtfn : 0;
3407 static void bnx2x_drv_info_fcoe_stat(struct bnx2x *bp)
3409 struct bnx2x_dcbx_app_params *app = &bp->dcbx_port_params.app;
3410 struct fcoe_stats_info *fcoe_stat =
3411 &bp->slowpath->drv_info_to_mcp.fcoe_stat;
3413 if (!CNIC_LOADED(bp))
3416 memcpy(fcoe_stat->mac_local + MAC_PAD, bp->fip_mac, ETH_ALEN);
3418 fcoe_stat->qos_priority =
3419 app->traffic_type_priority[LLFC_TRAFFIC_TYPE_FCOE];
3421 /* insert FCoE stats from ramrod response */
3423 struct tstorm_per_queue_stats *fcoe_q_tstorm_stats =
3424 &bp->fw_stats_data->queue_stats[FCOE_IDX(bp)].
3425 tstorm_queue_statistics;
3427 struct xstorm_per_queue_stats *fcoe_q_xstorm_stats =
3428 &bp->fw_stats_data->queue_stats[FCOE_IDX(bp)].
3429 xstorm_queue_statistics;
3431 struct fcoe_statistics_params *fw_fcoe_stat =
3432 &bp->fw_stats_data->fcoe;
3434 ADD_64_LE(fcoe_stat->rx_bytes_hi, LE32_0,
3435 fcoe_stat->rx_bytes_lo,
3436 fw_fcoe_stat->rx_stat0.fcoe_rx_byte_cnt);
3438 ADD_64_LE(fcoe_stat->rx_bytes_hi,
3439 fcoe_q_tstorm_stats->rcv_ucast_bytes.hi,
3440 fcoe_stat->rx_bytes_lo,
3441 fcoe_q_tstorm_stats->rcv_ucast_bytes.lo);
3443 ADD_64_LE(fcoe_stat->rx_bytes_hi,
3444 fcoe_q_tstorm_stats->rcv_bcast_bytes.hi,
3445 fcoe_stat->rx_bytes_lo,
3446 fcoe_q_tstorm_stats->rcv_bcast_bytes.lo);
3448 ADD_64_LE(fcoe_stat->rx_bytes_hi,
3449 fcoe_q_tstorm_stats->rcv_mcast_bytes.hi,
3450 fcoe_stat->rx_bytes_lo,
3451 fcoe_q_tstorm_stats->rcv_mcast_bytes.lo);
3453 ADD_64_LE(fcoe_stat->rx_frames_hi, LE32_0,
3454 fcoe_stat->rx_frames_lo,
3455 fw_fcoe_stat->rx_stat0.fcoe_rx_pkt_cnt);
3457 ADD_64_LE(fcoe_stat->rx_frames_hi, LE32_0,
3458 fcoe_stat->rx_frames_lo,
3459 fcoe_q_tstorm_stats->rcv_ucast_pkts);
3461 ADD_64_LE(fcoe_stat->rx_frames_hi, LE32_0,
3462 fcoe_stat->rx_frames_lo,
3463 fcoe_q_tstorm_stats->rcv_bcast_pkts);
3465 ADD_64_LE(fcoe_stat->rx_frames_hi, LE32_0,
3466 fcoe_stat->rx_frames_lo,
3467 fcoe_q_tstorm_stats->rcv_mcast_pkts);
3469 ADD_64_LE(fcoe_stat->tx_bytes_hi, LE32_0,
3470 fcoe_stat->tx_bytes_lo,
3471 fw_fcoe_stat->tx_stat.fcoe_tx_byte_cnt);
3473 ADD_64_LE(fcoe_stat->tx_bytes_hi,
3474 fcoe_q_xstorm_stats->ucast_bytes_sent.hi,
3475 fcoe_stat->tx_bytes_lo,
3476 fcoe_q_xstorm_stats->ucast_bytes_sent.lo);
3478 ADD_64_LE(fcoe_stat->tx_bytes_hi,
3479 fcoe_q_xstorm_stats->bcast_bytes_sent.hi,
3480 fcoe_stat->tx_bytes_lo,
3481 fcoe_q_xstorm_stats->bcast_bytes_sent.lo);
3483 ADD_64_LE(fcoe_stat->tx_bytes_hi,
3484 fcoe_q_xstorm_stats->mcast_bytes_sent.hi,
3485 fcoe_stat->tx_bytes_lo,
3486 fcoe_q_xstorm_stats->mcast_bytes_sent.lo);
3488 ADD_64_LE(fcoe_stat->tx_frames_hi, LE32_0,
3489 fcoe_stat->tx_frames_lo,
3490 fw_fcoe_stat->tx_stat.fcoe_tx_pkt_cnt);
3492 ADD_64_LE(fcoe_stat->tx_frames_hi, LE32_0,
3493 fcoe_stat->tx_frames_lo,
3494 fcoe_q_xstorm_stats->ucast_pkts_sent);
3496 ADD_64_LE(fcoe_stat->tx_frames_hi, LE32_0,
3497 fcoe_stat->tx_frames_lo,
3498 fcoe_q_xstorm_stats->bcast_pkts_sent);
3500 ADD_64_LE(fcoe_stat->tx_frames_hi, LE32_0,
3501 fcoe_stat->tx_frames_lo,
3502 fcoe_q_xstorm_stats->mcast_pkts_sent);
3505 /* ask L5 driver to add data to the struct */
3506 bnx2x_cnic_notify(bp, CNIC_CTL_FCOE_STATS_GET_CMD);
3509 static void bnx2x_drv_info_iscsi_stat(struct bnx2x *bp)
3511 struct bnx2x_dcbx_app_params *app = &bp->dcbx_port_params.app;
3512 struct iscsi_stats_info *iscsi_stat =
3513 &bp->slowpath->drv_info_to_mcp.iscsi_stat;
3515 if (!CNIC_LOADED(bp))
3518 memcpy(iscsi_stat->mac_local + MAC_PAD, bp->cnic_eth_dev.iscsi_mac,
3521 iscsi_stat->qos_priority =
3522 app->traffic_type_priority[LLFC_TRAFFIC_TYPE_ISCSI];
3524 /* ask L5 driver to add data to the struct */
3525 bnx2x_cnic_notify(bp, CNIC_CTL_ISCSI_STATS_GET_CMD);
3528 /* called due to MCP event (on pmf):
3529 * reread new bandwidth configuration
3531 * notify others function about the change
3533 static void bnx2x_config_mf_bw(struct bnx2x *bp)
3535 if (bp->link_vars.link_up) {
3536 bnx2x_cmng_fns_init(bp, true, CMNG_FNS_MINMAX);
3537 bnx2x_link_sync_notify(bp);
3539 storm_memset_cmng(bp, &bp->cmng, BP_PORT(bp));
3542 static void bnx2x_set_mf_bw(struct bnx2x *bp)
3544 bnx2x_config_mf_bw(bp);
3545 bnx2x_fw_command(bp, DRV_MSG_CODE_SET_MF_BW_ACK, 0);
3548 static void bnx2x_handle_eee_event(struct bnx2x *bp)
3550 DP(BNX2X_MSG_MCP, "EEE - LLDP event\n");
3551 bnx2x_fw_command(bp, DRV_MSG_CODE_EEE_RESULTS_ACK, 0);
3554 #define BNX2X_UPDATE_DRV_INFO_IND_LENGTH (20)
3555 #define BNX2X_UPDATE_DRV_INFO_IND_COUNT (25)
3557 static void bnx2x_handle_drv_info_req(struct bnx2x *bp)
3559 enum drv_info_opcode op_code;
3560 u32 drv_info_ctl = SHMEM2_RD(bp, drv_info_control);
3561 bool release = false;
3564 /* if drv_info version supported by MFW doesn't match - send NACK */
3565 if ((drv_info_ctl & DRV_INFO_CONTROL_VER_MASK) != DRV_INFO_CUR_VER) {
3566 bnx2x_fw_command(bp, DRV_MSG_CODE_DRV_INFO_NACK, 0);
3570 op_code = (drv_info_ctl & DRV_INFO_CONTROL_OP_CODE_MASK) >>
3571 DRV_INFO_CONTROL_OP_CODE_SHIFT;
3573 /* Must prevent other flows from accessing drv_info_to_mcp */
3574 mutex_lock(&bp->drv_info_mutex);
3576 memset(&bp->slowpath->drv_info_to_mcp, 0,
3577 sizeof(union drv_info_to_mcp));
3580 case ETH_STATS_OPCODE:
3581 bnx2x_drv_info_ether_stat(bp);
3583 case FCOE_STATS_OPCODE:
3584 bnx2x_drv_info_fcoe_stat(bp);
3586 case ISCSI_STATS_OPCODE:
3587 bnx2x_drv_info_iscsi_stat(bp);
3590 /* if op code isn't supported - send NACK */
3591 bnx2x_fw_command(bp, DRV_MSG_CODE_DRV_INFO_NACK, 0);
3595 /* if we got drv_info attn from MFW then these fields are defined in
3598 SHMEM2_WR(bp, drv_info_host_addr_lo,
3599 U64_LO(bnx2x_sp_mapping(bp, drv_info_to_mcp)));
3600 SHMEM2_WR(bp, drv_info_host_addr_hi,
3601 U64_HI(bnx2x_sp_mapping(bp, drv_info_to_mcp)));
3603 bnx2x_fw_command(bp, DRV_MSG_CODE_DRV_INFO_ACK, 0);
3605 /* Since possible management wants both this and get_driver_version
3606 * need to wait until management notifies us it finished utilizing
3609 if (!SHMEM2_HAS(bp, mfw_drv_indication)) {
3610 DP(BNX2X_MSG_MCP, "Management does not support indication\n");
3611 } else if (!bp->drv_info_mng_owner) {
3612 u32 bit = MFW_DRV_IND_READ_DONE_OFFSET((BP_ABS_FUNC(bp) >> 1));
3614 for (wait = 0; wait < BNX2X_UPDATE_DRV_INFO_IND_COUNT; wait++) {
3615 u32 indication = SHMEM2_RD(bp, mfw_drv_indication);
3617 /* Management is done; need to clear indication */
3618 if (indication & bit) {
3619 SHMEM2_WR(bp, mfw_drv_indication,
3625 msleep(BNX2X_UPDATE_DRV_INFO_IND_LENGTH);
3629 DP(BNX2X_MSG_MCP, "Management did not release indication\n");
3630 bp->drv_info_mng_owner = true;
3634 mutex_unlock(&bp->drv_info_mutex);
3637 static u32 bnx2x_update_mng_version_utility(u8 *version, bool bnx2x_format)
3643 i = sscanf(version, "1.%c%hhd.%hhd.%hhd",
3644 &vals[0], &vals[1], &vals[2], &vals[3]);
3648 i = sscanf(version, "%hhd.%hhd.%hhd.%hhd",
3649 &vals[0], &vals[1], &vals[2], &vals[3]);
3655 return (vals[0] << 24) | (vals[1] << 16) | (vals[2] << 8) | vals[3];
3658 void bnx2x_update_mng_version(struct bnx2x *bp)
3660 u32 iscsiver = DRV_VER_NOT_LOADED;
3661 u32 fcoever = DRV_VER_NOT_LOADED;
3662 u32 ethver = DRV_VER_NOT_LOADED;
3663 int idx = BP_FW_MB_IDX(bp);
3666 if (!SHMEM2_HAS(bp, func_os_drv_ver))
3669 mutex_lock(&bp->drv_info_mutex);
3670 /* Must not proceed when `bnx2x_handle_drv_info_req' is feasible */
3671 if (bp->drv_info_mng_owner)
3674 if (bp->state != BNX2X_STATE_OPEN)
3677 /* Parse ethernet driver version */
3678 ethver = bnx2x_update_mng_version_utility(DRV_MODULE_VERSION, true);
3679 if (!CNIC_LOADED(bp))
3682 /* Try getting storage driver version via cnic */
3683 memset(&bp->slowpath->drv_info_to_mcp, 0,
3684 sizeof(union drv_info_to_mcp));
3685 bnx2x_drv_info_iscsi_stat(bp);
3686 version = bp->slowpath->drv_info_to_mcp.iscsi_stat.version;
3687 iscsiver = bnx2x_update_mng_version_utility(version, false);
3689 memset(&bp->slowpath->drv_info_to_mcp, 0,
3690 sizeof(union drv_info_to_mcp));
3691 bnx2x_drv_info_fcoe_stat(bp);
3692 version = bp->slowpath->drv_info_to_mcp.fcoe_stat.version;
3693 fcoever = bnx2x_update_mng_version_utility(version, false);
3696 SHMEM2_WR(bp, func_os_drv_ver[idx].versions[DRV_PERS_ETHERNET], ethver);
3697 SHMEM2_WR(bp, func_os_drv_ver[idx].versions[DRV_PERS_ISCSI], iscsiver);
3698 SHMEM2_WR(bp, func_os_drv_ver[idx].versions[DRV_PERS_FCOE], fcoever);
3700 mutex_unlock(&bp->drv_info_mutex);
3702 DP(BNX2X_MSG_MCP, "Setting driver version: ETH [%08x] iSCSI [%08x] FCoE [%08x]\n",
3703 ethver, iscsiver, fcoever);
3706 void bnx2x_update_mfw_dump(struct bnx2x *bp)
3708 struct timeval epoc;
3712 if (!SHMEM2_HAS(bp, drv_info))
3715 /* Update Driver load time */
3716 do_gettimeofday(&epoc);
3717 SHMEM2_WR(bp, drv_info.epoc, epoc.tv_sec);
3719 drv_ver = bnx2x_update_mng_version_utility(DRV_MODULE_VERSION, true);
3720 SHMEM2_WR(bp, drv_info.drv_ver, drv_ver);
3722 SHMEM2_WR(bp, drv_info.fw_ver, REG_RD(bp, XSEM_REG_PRAM));
3724 /* Check & notify On-Chip dump. */
3725 valid_dump = SHMEM2_RD(bp, drv_info.valid_dump);
3727 if (valid_dump & FIRST_DUMP_VALID)
3728 DP(NETIF_MSG_IFUP, "A valid On-Chip MFW dump found on 1st partition\n");
3730 if (valid_dump & SECOND_DUMP_VALID)
3731 DP(NETIF_MSG_IFUP, "A valid On-Chip MFW dump found on 2nd partition\n");
3734 static void bnx2x_oem_event(struct bnx2x *bp, u32 event)
3736 u32 cmd_ok, cmd_fail;
3739 if (event & DRV_STATUS_DCC_EVENT_MASK &&
3740 event & DRV_STATUS_OEM_EVENT_MASK) {
3741 BNX2X_ERR("Received simultaneous events %08x\n", event);
3745 if (event & DRV_STATUS_DCC_EVENT_MASK) {
3746 cmd_fail = DRV_MSG_CODE_DCC_FAILURE;
3747 cmd_ok = DRV_MSG_CODE_DCC_OK;
3748 } else /* if (event & DRV_STATUS_OEM_EVENT_MASK) */ {
3749 cmd_fail = DRV_MSG_CODE_OEM_FAILURE;
3750 cmd_ok = DRV_MSG_CODE_OEM_OK;
3753 DP(BNX2X_MSG_MCP, "oem_event 0x%x\n", event);
3755 if (event & (DRV_STATUS_DCC_DISABLE_ENABLE_PF |
3756 DRV_STATUS_OEM_DISABLE_ENABLE_PF)) {
3757 /* This is the only place besides the function initialization
3758 * where the bp->flags can change so it is done without any
3761 if (bp->mf_config[BP_VN(bp)] & FUNC_MF_CFG_FUNC_DISABLED) {
3762 DP(BNX2X_MSG_MCP, "mf_cfg function disabled\n");
3763 bp->flags |= MF_FUNC_DIS;
3765 bnx2x_e1h_disable(bp);
3767 DP(BNX2X_MSG_MCP, "mf_cfg function enabled\n");
3768 bp->flags &= ~MF_FUNC_DIS;
3770 bnx2x_e1h_enable(bp);
3772 event &= ~(DRV_STATUS_DCC_DISABLE_ENABLE_PF |
3773 DRV_STATUS_OEM_DISABLE_ENABLE_PF);
3776 if (event & (DRV_STATUS_DCC_BANDWIDTH_ALLOCATION |
3777 DRV_STATUS_OEM_BANDWIDTH_ALLOCATION)) {
3778 bnx2x_config_mf_bw(bp);
3779 event &= ~(DRV_STATUS_DCC_BANDWIDTH_ALLOCATION |
3780 DRV_STATUS_OEM_BANDWIDTH_ALLOCATION);
3783 /* Report results to MCP */
3785 bnx2x_fw_command(bp, cmd_fail, 0);
3787 bnx2x_fw_command(bp, cmd_ok, 0);
3790 /* must be called under the spq lock */
3791 static struct eth_spe *bnx2x_sp_get_next(struct bnx2x *bp)
3793 struct eth_spe *next_spe = bp->spq_prod_bd;
3795 if (bp->spq_prod_bd == bp->spq_last_bd) {
3796 bp->spq_prod_bd = bp->spq;
3797 bp->spq_prod_idx = 0;
3798 DP(BNX2X_MSG_SP, "end of spq\n");
3806 /* must be called under the spq lock */
3807 static void bnx2x_sp_prod_update(struct bnx2x *bp)
3809 int func = BP_FUNC(bp);
3812 * Make sure that BD data is updated before writing the producer:
3813 * BD data is written to the memory, the producer is read from the
3814 * memory, thus we need a full memory barrier to ensure the ordering.
3818 REG_WR16(bp, BAR_XSTRORM_INTMEM + XSTORM_SPQ_PROD_OFFSET(func),
3824 * bnx2x_is_contextless_ramrod - check if the current command ends on EQ
3826 * @cmd: command to check
3827 * @cmd_type: command type
3829 static bool bnx2x_is_contextless_ramrod(int cmd, int cmd_type)
3831 if ((cmd_type == NONE_CONNECTION_TYPE) ||
3832 (cmd == RAMROD_CMD_ID_ETH_FORWARD_SETUP) ||
3833 (cmd == RAMROD_CMD_ID_ETH_CLASSIFICATION_RULES) ||
3834 (cmd == RAMROD_CMD_ID_ETH_FILTER_RULES) ||
3835 (cmd == RAMROD_CMD_ID_ETH_MULTICAST_RULES) ||
3836 (cmd == RAMROD_CMD_ID_ETH_SET_MAC) ||
3837 (cmd == RAMROD_CMD_ID_ETH_RSS_UPDATE))
3844 * bnx2x_sp_post - place a single command on an SP ring
3846 * @bp: driver handle
3847 * @command: command to place (e.g. SETUP, FILTER_RULES, etc.)
3848 * @cid: SW CID the command is related to
3849 * @data_hi: command private data address (high 32 bits)
3850 * @data_lo: command private data address (low 32 bits)
3851 * @cmd_type: command type (e.g. NONE, ETH)
3853 * SP data is handled as if it's always an address pair, thus data fields are
3854 * not swapped to little endian in upper functions. Instead this function swaps
3855 * data as if it's two u32 fields.
3857 int bnx2x_sp_post(struct bnx2x *bp, int command, int cid,
3858 u32 data_hi, u32 data_lo, int cmd_type)
3860 struct eth_spe *spe;
3862 bool common = bnx2x_is_contextless_ramrod(command, cmd_type);
3864 #ifdef BNX2X_STOP_ON_ERROR
3865 if (unlikely(bp->panic)) {
3866 BNX2X_ERR("Can't post SP when there is panic\n");
3871 spin_lock_bh(&bp->spq_lock);
3874 if (!atomic_read(&bp->eq_spq_left)) {
3875 BNX2X_ERR("BUG! EQ ring full!\n");
3876 spin_unlock_bh(&bp->spq_lock);
3880 } else if (!atomic_read(&bp->cq_spq_left)) {
3881 BNX2X_ERR("BUG! SPQ ring full!\n");
3882 spin_unlock_bh(&bp->spq_lock);
3887 spe = bnx2x_sp_get_next(bp);
3889 /* CID needs port number to be encoded int it */
3890 spe->hdr.conn_and_cmd_data =
3891 cpu_to_le32((command << SPE_HDR_CMD_ID_SHIFT) |
3894 /* In some cases, type may already contain the func-id
3895 * mainly in SRIOV related use cases, so we add it here only
3896 * if it's not already set.
3898 if (!(cmd_type & SPE_HDR_FUNCTION_ID)) {
3899 type = (cmd_type << SPE_HDR_CONN_TYPE_SHIFT) &
3901 type |= ((BP_FUNC(bp) << SPE_HDR_FUNCTION_ID_SHIFT) &
3902 SPE_HDR_FUNCTION_ID);
3907 spe->hdr.type = cpu_to_le16(type);
3909 spe->data.update_data_addr.hi = cpu_to_le32(data_hi);
3910 spe->data.update_data_addr.lo = cpu_to_le32(data_lo);
3913 * It's ok if the actual decrement is issued towards the memory
3914 * somewhere between the spin_lock and spin_unlock. Thus no
3915 * more explicit memory barrier is needed.
3918 atomic_dec(&bp->eq_spq_left);
3920 atomic_dec(&bp->cq_spq_left);
3923 "SPQE[%x] (%x:%x) (cmd, common?) (%d,%d) hw_cid %x data (%x:%x) type(0x%x) left (CQ, EQ) (%x,%x)\n",
3924 bp->spq_prod_idx, (u32)U64_HI(bp->spq_mapping),
3925 (u32)(U64_LO(bp->spq_mapping) +
3926 (void *)bp->spq_prod_bd - (void *)bp->spq), command, common,
3927 HW_CID(bp, cid), data_hi, data_lo, type,
3928 atomic_read(&bp->cq_spq_left), atomic_read(&bp->eq_spq_left));
3930 bnx2x_sp_prod_update(bp);
3931 spin_unlock_bh(&bp->spq_lock);
3935 /* acquire split MCP access lock register */
3936 static int bnx2x_acquire_alr(struct bnx2x *bp)
3942 for (j = 0; j < 1000; j++) {
3943 REG_WR(bp, MCP_REG_MCPR_ACCESS_LOCK, MCPR_ACCESS_LOCK_LOCK);
3944 val = REG_RD(bp, MCP_REG_MCPR_ACCESS_LOCK);
3945 if (val & MCPR_ACCESS_LOCK_LOCK)
3948 usleep_range(5000, 10000);
3950 if (!(val & MCPR_ACCESS_LOCK_LOCK)) {
3951 BNX2X_ERR("Cannot acquire MCP access lock register\n");
3958 /* release split MCP access lock register */
3959 static void bnx2x_release_alr(struct bnx2x *bp)
3961 REG_WR(bp, MCP_REG_MCPR_ACCESS_LOCK, 0);
3964 #define BNX2X_DEF_SB_ATT_IDX 0x0001
3965 #define BNX2X_DEF_SB_IDX 0x0002
3967 static u16 bnx2x_update_dsb_idx(struct bnx2x *bp)
3969 struct host_sp_status_block *def_sb = bp->def_status_blk;
3972 barrier(); /* status block is written to by the chip */
3973 if (bp->def_att_idx != def_sb->atten_status_block.attn_bits_index) {
3974 bp->def_att_idx = def_sb->atten_status_block.attn_bits_index;
3975 rc |= BNX2X_DEF_SB_ATT_IDX;
3978 if (bp->def_idx != def_sb->sp_sb.running_index) {
3979 bp->def_idx = def_sb->sp_sb.running_index;
3980 rc |= BNX2X_DEF_SB_IDX;
3983 /* Do not reorder: indices reading should complete before handling */
3989 * slow path service functions
3992 static void bnx2x_attn_int_asserted(struct bnx2x *bp, u32 asserted)
3994 int port = BP_PORT(bp);
3995 u32 aeu_addr = port ? MISC_REG_AEU_MASK_ATTN_FUNC_1 :
3996 MISC_REG_AEU_MASK_ATTN_FUNC_0;
3997 u32 nig_int_mask_addr = port ? NIG_REG_MASK_INTERRUPT_PORT1 :
3998 NIG_REG_MASK_INTERRUPT_PORT0;
4003 if (bp->attn_state & asserted)
4004 BNX2X_ERR("IGU ERROR\n");
4006 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_PORT0_ATT_MASK + port);
4007 aeu_mask = REG_RD(bp, aeu_addr);
4009 DP(NETIF_MSG_HW, "aeu_mask %x newly asserted %x\n",
4010 aeu_mask, asserted);
4011 aeu_mask &= ~(asserted & 0x3ff);
4012 DP(NETIF_MSG_HW, "new mask %x\n", aeu_mask);
4014 REG_WR(bp, aeu_addr, aeu_mask);
4015 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_PORT0_ATT_MASK + port);
4017 DP(NETIF_MSG_HW, "attn_state %x\n", bp->attn_state);
4018 bp->attn_state |= asserted;
4019 DP(NETIF_MSG_HW, "new state %x\n", bp->attn_state);
4021 if (asserted & ATTN_HARD_WIRED_MASK) {
4022 if (asserted & ATTN_NIG_FOR_FUNC) {
4024 bnx2x_acquire_phy_lock(bp);
4026 /* save nig interrupt mask */
4027 nig_mask = REG_RD(bp, nig_int_mask_addr);
4029 /* If nig_mask is not set, no need to call the update
4033 REG_WR(bp, nig_int_mask_addr, 0);
4035 bnx2x_link_attn(bp);
4038 /* handle unicore attn? */
4040 if (asserted & ATTN_SW_TIMER_4_FUNC)
4041 DP(NETIF_MSG_HW, "ATTN_SW_TIMER_4_FUNC!\n");
4043 if (asserted & GPIO_2_FUNC)
4044 DP(NETIF_MSG_HW, "GPIO_2_FUNC!\n");
4046 if (asserted & GPIO_3_FUNC)
4047 DP(NETIF_MSG_HW, "GPIO_3_FUNC!\n");
4049 if (asserted & GPIO_4_FUNC)
4050 DP(NETIF_MSG_HW, "GPIO_4_FUNC!\n");
4053 if (asserted & ATTN_GENERAL_ATTN_1) {
4054 DP(NETIF_MSG_HW, "ATTN_GENERAL_ATTN_1!\n");
4055 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_1, 0x0);
4057 if (asserted & ATTN_GENERAL_ATTN_2) {
4058 DP(NETIF_MSG_HW, "ATTN_GENERAL_ATTN_2!\n");
4059 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_2, 0x0);
4061 if (asserted & ATTN_GENERAL_ATTN_3) {
4062 DP(NETIF_MSG_HW, "ATTN_GENERAL_ATTN_3!\n");
4063 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_3, 0x0);
4066 if (asserted & ATTN_GENERAL_ATTN_4) {
4067 DP(NETIF_MSG_HW, "ATTN_GENERAL_ATTN_4!\n");
4068 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_4, 0x0);
4070 if (asserted & ATTN_GENERAL_ATTN_5) {
4071 DP(NETIF_MSG_HW, "ATTN_GENERAL_ATTN_5!\n");
4072 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_5, 0x0);
4074 if (asserted & ATTN_GENERAL_ATTN_6) {
4075 DP(NETIF_MSG_HW, "ATTN_GENERAL_ATTN_6!\n");
4076 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_6, 0x0);
4080 } /* if hardwired */
4082 if (bp->common.int_block == INT_BLOCK_HC)
4083 reg_addr = (HC_REG_COMMAND_REG + port*32 +
4084 COMMAND_REG_ATTN_BITS_SET);
4086 reg_addr = (BAR_IGU_INTMEM + IGU_CMD_ATTN_BIT_SET_UPPER*8);
4088 DP(NETIF_MSG_HW, "about to mask 0x%08x at %s addr 0x%x\n", asserted,
4089 (bp->common.int_block == INT_BLOCK_HC) ? "HC" : "IGU", reg_addr);
4090 REG_WR(bp, reg_addr, asserted);
4092 /* now set back the mask */
4093 if (asserted & ATTN_NIG_FOR_FUNC) {
4094 /* Verify that IGU ack through BAR was written before restoring
4095 * NIG mask. This loop should exit after 2-3 iterations max.
4097 if (bp->common.int_block != INT_BLOCK_HC) {
4098 u32 cnt = 0, igu_acked;
4100 igu_acked = REG_RD(bp,
4101 IGU_REG_ATTENTION_ACK_BITS);
4102 } while (((igu_acked & ATTN_NIG_FOR_FUNC) == 0) &&
4103 (++cnt < MAX_IGU_ATTN_ACK_TO));
4106 "Failed to verify IGU ack on time\n");
4109 REG_WR(bp, nig_int_mask_addr, nig_mask);
4110 bnx2x_release_phy_lock(bp);
4114 static void bnx2x_fan_failure(struct bnx2x *bp)
4116 int port = BP_PORT(bp);
4118 /* mark the failure */
4121 dev_info.port_hw_config[port].external_phy_config);
4123 ext_phy_config &= ~PORT_HW_CFG_XGXS_EXT_PHY_TYPE_MASK;
4124 ext_phy_config |= PORT_HW_CFG_XGXS_EXT_PHY_TYPE_FAILURE;
4125 SHMEM_WR(bp, dev_info.port_hw_config[port].external_phy_config,
4128 /* log the failure */
4129 netdev_err(bp->dev, "Fan Failure on Network Controller has caused the driver to shutdown the card to prevent permanent damage.\n"
4130 "Please contact OEM Support for assistance\n");
4132 /* Schedule device reset (unload)
4133 * This is due to some boards consuming sufficient power when driver is
4134 * up to overheat if fan fails.
4136 bnx2x_schedule_sp_rtnl(bp, BNX2X_SP_RTNL_FAN_FAILURE, 0);
4139 static void bnx2x_attn_int_deasserted0(struct bnx2x *bp, u32 attn)
4141 int port = BP_PORT(bp);
4145 reg_offset = (port ? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_0 :
4146 MISC_REG_AEU_ENABLE1_FUNC_0_OUT_0);
4148 if (attn & AEU_INPUTS_ATTN_BITS_SPIO5) {
4150 val = REG_RD(bp, reg_offset);
4151 val &= ~AEU_INPUTS_ATTN_BITS_SPIO5;
4152 REG_WR(bp, reg_offset, val);
4154 BNX2X_ERR("SPIO5 hw attention\n");
4156 /* Fan failure attention */
4157 bnx2x_hw_reset_phy(&bp->link_params);
4158 bnx2x_fan_failure(bp);
4161 if ((attn & bp->link_vars.aeu_int_mask) && bp->port.pmf) {
4162 bnx2x_acquire_phy_lock(bp);
4163 bnx2x_handle_module_detect_int(&bp->link_params);
4164 bnx2x_release_phy_lock(bp);
4167 if (attn & HW_INTERRUT_ASSERT_SET_0) {
4169 val = REG_RD(bp, reg_offset);
4170 val &= ~(attn & HW_INTERRUT_ASSERT_SET_0);
4171 REG_WR(bp, reg_offset, val);
4173 BNX2X_ERR("FATAL HW block attention set0 0x%x\n",
4174 (u32)(attn & HW_INTERRUT_ASSERT_SET_0));
4179 static void bnx2x_attn_int_deasserted1(struct bnx2x *bp, u32 attn)
4183 if (attn & AEU_INPUTS_ATTN_BITS_DOORBELLQ_HW_INTERRUPT) {
4185 val = REG_RD(bp, DORQ_REG_DORQ_INT_STS_CLR);
4186 BNX2X_ERR("DB hw attention 0x%x\n", val);
4187 /* DORQ discard attention */
4189 BNX2X_ERR("FATAL error from DORQ\n");
4192 if (attn & HW_INTERRUT_ASSERT_SET_1) {
4194 int port = BP_PORT(bp);
4197 reg_offset = (port ? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_1 :
4198 MISC_REG_AEU_ENABLE1_FUNC_0_OUT_1);
4200 val = REG_RD(bp, reg_offset);
4201 val &= ~(attn & HW_INTERRUT_ASSERT_SET_1);
4202 REG_WR(bp, reg_offset, val);
4204 BNX2X_ERR("FATAL HW block attention set1 0x%x\n",
4205 (u32)(attn & HW_INTERRUT_ASSERT_SET_1));
4210 static void bnx2x_attn_int_deasserted2(struct bnx2x *bp, u32 attn)
4214 if (attn & AEU_INPUTS_ATTN_BITS_CFC_HW_INTERRUPT) {
4216 val = REG_RD(bp, CFC_REG_CFC_INT_STS_CLR);
4217 BNX2X_ERR("CFC hw attention 0x%x\n", val);
4218 /* CFC error attention */
4220 BNX2X_ERR("FATAL error from CFC\n");
4223 if (attn & AEU_INPUTS_ATTN_BITS_PXP_HW_INTERRUPT) {
4224 val = REG_RD(bp, PXP_REG_PXP_INT_STS_CLR_0);
4225 BNX2X_ERR("PXP hw attention-0 0x%x\n", val);
4226 /* RQ_USDMDP_FIFO_OVERFLOW */
4228 BNX2X_ERR("FATAL error from PXP\n");
4230 if (!CHIP_IS_E1x(bp)) {
4231 val = REG_RD(bp, PXP_REG_PXP_INT_STS_CLR_1);
4232 BNX2X_ERR("PXP hw attention-1 0x%x\n", val);
4236 if (attn & HW_INTERRUT_ASSERT_SET_2) {
4238 int port = BP_PORT(bp);
4241 reg_offset = (port ? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_2 :
4242 MISC_REG_AEU_ENABLE1_FUNC_0_OUT_2);
4244 val = REG_RD(bp, reg_offset);
4245 val &= ~(attn & HW_INTERRUT_ASSERT_SET_2);
4246 REG_WR(bp, reg_offset, val);
4248 BNX2X_ERR("FATAL HW block attention set2 0x%x\n",
4249 (u32)(attn & HW_INTERRUT_ASSERT_SET_2));
4254 static void bnx2x_attn_int_deasserted3(struct bnx2x *bp, u32 attn)
4258 if (attn & EVEREST_GEN_ATTN_IN_USE_MASK) {
4260 if (attn & BNX2X_PMF_LINK_ASSERT) {
4261 int func = BP_FUNC(bp);
4263 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_12 + func*4, 0);
4264 bnx2x_read_mf_cfg(bp);
4265 bp->mf_config[BP_VN(bp)] = MF_CFG_RD(bp,
4266 func_mf_config[BP_ABS_FUNC(bp)].config);
4268 func_mb[BP_FW_MB_IDX(bp)].drv_status);
4270 if (val & (DRV_STATUS_DCC_EVENT_MASK |
4271 DRV_STATUS_OEM_EVENT_MASK))
4273 (val & (DRV_STATUS_DCC_EVENT_MASK |
4274 DRV_STATUS_OEM_EVENT_MASK)));
4276 if (val & DRV_STATUS_SET_MF_BW)
4277 bnx2x_set_mf_bw(bp);
4279 if (val & DRV_STATUS_DRV_INFO_REQ)
4280 bnx2x_handle_drv_info_req(bp);
4282 if (val & DRV_STATUS_VF_DISABLED)
4283 bnx2x_schedule_iov_task(bp,
4284 BNX2X_IOV_HANDLE_FLR);
4286 if ((bp->port.pmf == 0) && (val & DRV_STATUS_PMF))
4287 bnx2x_pmf_update(bp);
4290 (val & DRV_STATUS_DCBX_NEGOTIATION_RESULTS) &&
4291 bp->dcbx_enabled > 0)
4292 /* start dcbx state machine */
4293 bnx2x_dcbx_set_params(bp,
4294 BNX2X_DCBX_STATE_NEG_RECEIVED);
4295 if (val & DRV_STATUS_AFEX_EVENT_MASK)
4296 bnx2x_handle_afex_cmd(bp,
4297 val & DRV_STATUS_AFEX_EVENT_MASK);
4298 if (val & DRV_STATUS_EEE_NEGOTIATION_RESULTS)
4299 bnx2x_handle_eee_event(bp);
4301 if (val & DRV_STATUS_OEM_UPDATE_SVID)
4302 bnx2x_handle_update_svid_cmd(bp);
4304 if (bp->link_vars.periodic_flags &
4305 PERIODIC_FLAGS_LINK_EVENT) {
4306 /* sync with link */
4307 bnx2x_acquire_phy_lock(bp);
4308 bp->link_vars.periodic_flags &=
4309 ~PERIODIC_FLAGS_LINK_EVENT;
4310 bnx2x_release_phy_lock(bp);
4312 bnx2x_link_sync_notify(bp);
4313 bnx2x_link_report(bp);
4315 /* Always call it here: bnx2x_link_report() will
4316 * prevent the link indication duplication.
4318 bnx2x__link_status_update(bp);
4319 } else if (attn & BNX2X_MC_ASSERT_BITS) {
4321 BNX2X_ERR("MC assert!\n");
4322 bnx2x_mc_assert(bp);
4323 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_10, 0);
4324 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_9, 0);
4325 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_8, 0);
4326 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_7, 0);
4329 } else if (attn & BNX2X_MCP_ASSERT) {
4331 BNX2X_ERR("MCP assert!\n");
4332 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_11, 0);
4336 BNX2X_ERR("Unknown HW assert! (attn 0x%x)\n", attn);
4339 if (attn & EVEREST_LATCHED_ATTN_IN_USE_MASK) {
4340 BNX2X_ERR("LATCHED attention 0x%08x (masked)\n", attn);
4341 if (attn & BNX2X_GRC_TIMEOUT) {
4342 val = CHIP_IS_E1(bp) ? 0 :
4343 REG_RD(bp, MISC_REG_GRC_TIMEOUT_ATTN);
4344 BNX2X_ERR("GRC time-out 0x%08x\n", val);
4346 if (attn & BNX2X_GRC_RSV) {
4347 val = CHIP_IS_E1(bp) ? 0 :
4348 REG_RD(bp, MISC_REG_GRC_RSV_ATTN);
4349 BNX2X_ERR("GRC reserved 0x%08x\n", val);
4351 REG_WR(bp, MISC_REG_AEU_CLR_LATCH_SIGNAL, 0x7ff);
4357 * 0-7 - Engine0 load counter.
4358 * 8-15 - Engine1 load counter.
4359 * 16 - Engine0 RESET_IN_PROGRESS bit.
4360 * 17 - Engine1 RESET_IN_PROGRESS bit.
4361 * 18 - Engine0 ONE_IS_LOADED. Set when there is at least one active function
4363 * 19 - Engine1 ONE_IS_LOADED.
4364 * 20 - Chip reset flow bit. When set none-leader must wait for both engines
4365 * leader to complete (check for both RESET_IN_PROGRESS bits and not for
4366 * just the one belonging to its engine).
4369 #define BNX2X_RECOVERY_GLOB_REG MISC_REG_GENERIC_POR_1
4371 #define BNX2X_PATH0_LOAD_CNT_MASK 0x000000ff
4372 #define BNX2X_PATH0_LOAD_CNT_SHIFT 0
4373 #define BNX2X_PATH1_LOAD_CNT_MASK 0x0000ff00
4374 #define BNX2X_PATH1_LOAD_CNT_SHIFT 8
4375 #define BNX2X_PATH0_RST_IN_PROG_BIT 0x00010000
4376 #define BNX2X_PATH1_RST_IN_PROG_BIT 0x00020000
4377 #define BNX2X_GLOBAL_RESET_BIT 0x00040000
4380 * Set the GLOBAL_RESET bit.
4382 * Should be run under rtnl lock
4384 void bnx2x_set_reset_global(struct bnx2x *bp)
4387 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG);
4388 val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG);
4389 REG_WR(bp, BNX2X_RECOVERY_GLOB_REG, val | BNX2X_GLOBAL_RESET_BIT);
4390 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG);
4394 * Clear the GLOBAL_RESET bit.
4396 * Should be run under rtnl lock
4398 static void bnx2x_clear_reset_global(struct bnx2x *bp)
4401 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG);
4402 val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG);
4403 REG_WR(bp, BNX2X_RECOVERY_GLOB_REG, val & (~BNX2X_GLOBAL_RESET_BIT));
4404 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG);
4408 * Checks the GLOBAL_RESET bit.
4410 * should be run under rtnl lock
4412 static bool bnx2x_reset_is_global(struct bnx2x *bp)
4414 u32 val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG);
4416 DP(NETIF_MSG_HW, "GEN_REG_VAL=0x%08x\n", val);
4417 return (val & BNX2X_GLOBAL_RESET_BIT) ? true : false;
4421 * Clear RESET_IN_PROGRESS bit for the current engine.
4423 * Should be run under rtnl lock
4425 static void bnx2x_set_reset_done(struct bnx2x *bp)
4428 u32 bit = BP_PATH(bp) ?
4429 BNX2X_PATH1_RST_IN_PROG_BIT : BNX2X_PATH0_RST_IN_PROG_BIT;
4430 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG);
4431 val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG);
4435 REG_WR(bp, BNX2X_RECOVERY_GLOB_REG, val);
4437 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG);
4441 * Set RESET_IN_PROGRESS for the current engine.
4443 * should be run under rtnl lock
4445 void bnx2x_set_reset_in_progress(struct bnx2x *bp)
4448 u32 bit = BP_PATH(bp) ?
4449 BNX2X_PATH1_RST_IN_PROG_BIT : BNX2X_PATH0_RST_IN_PROG_BIT;
4450 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG);
4451 val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG);
4455 REG_WR(bp, BNX2X_RECOVERY_GLOB_REG, val);
4456 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG);
4460 * Checks the RESET_IN_PROGRESS bit for the given engine.
4461 * should be run under rtnl lock
4463 bool bnx2x_reset_is_done(struct bnx2x *bp, int engine)
4465 u32 val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG);
4467 BNX2X_PATH1_RST_IN_PROG_BIT : BNX2X_PATH0_RST_IN_PROG_BIT;
4469 /* return false if bit is set */
4470 return (val & bit) ? false : true;
4474 * set pf load for the current pf.
4476 * should be run under rtnl lock
4478 void bnx2x_set_pf_load(struct bnx2x *bp)
4481 u32 mask = BP_PATH(bp) ? BNX2X_PATH1_LOAD_CNT_MASK :
4482 BNX2X_PATH0_LOAD_CNT_MASK;
4483 u32 shift = BP_PATH(bp) ? BNX2X_PATH1_LOAD_CNT_SHIFT :
4484 BNX2X_PATH0_LOAD_CNT_SHIFT;
4486 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG);
4487 val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG);
4489 DP(NETIF_MSG_IFUP, "Old GEN_REG_VAL=0x%08x\n", val);
4491 /* get the current counter value */
4492 val1 = (val & mask) >> shift;
4494 /* set bit of that PF */
4495 val1 |= (1 << bp->pf_num);
4497 /* clear the old value */
4500 /* set the new one */
4501 val |= ((val1 << shift) & mask);
4503 REG_WR(bp, BNX2X_RECOVERY_GLOB_REG, val);
4504 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG);
4508 * bnx2x_clear_pf_load - clear pf load mark
4510 * @bp: driver handle
4512 * Should be run under rtnl lock.
4513 * Decrements the load counter for the current engine. Returns
4514 * whether other functions are still loaded
4516 bool bnx2x_clear_pf_load(struct bnx2x *bp)
4519 u32 mask = BP_PATH(bp) ? BNX2X_PATH1_LOAD_CNT_MASK :
4520 BNX2X_PATH0_LOAD_CNT_MASK;
4521 u32 shift = BP_PATH(bp) ? BNX2X_PATH1_LOAD_CNT_SHIFT :
4522 BNX2X_PATH0_LOAD_CNT_SHIFT;
4524 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG);
4525 val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG);
4526 DP(NETIF_MSG_IFDOWN, "Old GEN_REG_VAL=0x%08x\n", val);
4528 /* get the current counter value */
4529 val1 = (val & mask) >> shift;
4531 /* clear bit of that PF */
4532 val1 &= ~(1 << bp->pf_num);
4534 /* clear the old value */
4537 /* set the new one */
4538 val |= ((val1 << shift) & mask);
4540 REG_WR(bp, BNX2X_RECOVERY_GLOB_REG, val);
4541 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG);
4546 * Read the load status for the current engine.
4548 * should be run under rtnl lock
4550 static bool bnx2x_get_load_status(struct bnx2x *bp, int engine)
4552 u32 mask = (engine ? BNX2X_PATH1_LOAD_CNT_MASK :
4553 BNX2X_PATH0_LOAD_CNT_MASK);
4554 u32 shift = (engine ? BNX2X_PATH1_LOAD_CNT_SHIFT :
4555 BNX2X_PATH0_LOAD_CNT_SHIFT);
4556 u32 val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG);
4558 DP(NETIF_MSG_HW | NETIF_MSG_IFUP, "GLOB_REG=0x%08x\n", val);
4560 val = (val & mask) >> shift;
4562 DP(NETIF_MSG_HW | NETIF_MSG_IFUP, "load mask for engine %d = 0x%x\n",
4568 static void _print_parity(struct bnx2x *bp, u32 reg)
4570 pr_cont(" [0x%08x] ", REG_RD(bp, reg));
4573 static void _print_next_block(int idx, const char *blk)
4575 pr_cont("%s%s", idx ? ", " : "", blk);
4578 static bool bnx2x_check_blocks_with_parity0(struct bnx2x *bp, u32 sig,
4579 int *par_num, bool print)
4587 for (i = 0; sig; i++) {
4588 cur_bit = (0x1UL << i);
4589 if (sig & cur_bit) {
4590 res |= true; /* Each bit is real error! */
4594 case AEU_INPUTS_ATTN_BITS_BRB_PARITY_ERROR:
4595 _print_next_block((*par_num)++, "BRB");
4597 BRB1_REG_BRB1_PRTY_STS);
4599 case AEU_INPUTS_ATTN_BITS_PARSER_PARITY_ERROR:
4600 _print_next_block((*par_num)++,
4602 _print_parity(bp, PRS_REG_PRS_PRTY_STS);
4604 case AEU_INPUTS_ATTN_BITS_TSDM_PARITY_ERROR:
4605 _print_next_block((*par_num)++, "TSDM");
4607 TSDM_REG_TSDM_PRTY_STS);
4609 case AEU_INPUTS_ATTN_BITS_SEARCHER_PARITY_ERROR:
4610 _print_next_block((*par_num)++,
4612 _print_parity(bp, SRC_REG_SRC_PRTY_STS);
4614 case AEU_INPUTS_ATTN_BITS_TCM_PARITY_ERROR:
4615 _print_next_block((*par_num)++, "TCM");
4616 _print_parity(bp, TCM_REG_TCM_PRTY_STS);
4618 case AEU_INPUTS_ATTN_BITS_TSEMI_PARITY_ERROR:
4619 _print_next_block((*par_num)++,
4622 TSEM_REG_TSEM_PRTY_STS_0);
4624 TSEM_REG_TSEM_PRTY_STS_1);
4626 case AEU_INPUTS_ATTN_BITS_PBCLIENT_PARITY_ERROR:
4627 _print_next_block((*par_num)++, "XPB");
4628 _print_parity(bp, GRCBASE_XPB +
4629 PB_REG_PB_PRTY_STS);
4642 static bool bnx2x_check_blocks_with_parity1(struct bnx2x *bp, u32 sig,
4643 int *par_num, bool *global,
4652 for (i = 0; sig; i++) {
4653 cur_bit = (0x1UL << i);
4654 if (sig & cur_bit) {
4655 res |= true; /* Each bit is real error! */
4657 case AEU_INPUTS_ATTN_BITS_PBF_PARITY_ERROR:
4659 _print_next_block((*par_num)++, "PBF");
4660 _print_parity(bp, PBF_REG_PBF_PRTY_STS);
4663 case AEU_INPUTS_ATTN_BITS_QM_PARITY_ERROR:
4665 _print_next_block((*par_num)++, "QM");
4666 _print_parity(bp, QM_REG_QM_PRTY_STS);
4669 case AEU_INPUTS_ATTN_BITS_TIMERS_PARITY_ERROR:
4671 _print_next_block((*par_num)++, "TM");
4672 _print_parity(bp, TM_REG_TM_PRTY_STS);
4675 case AEU_INPUTS_ATTN_BITS_XSDM_PARITY_ERROR:
4677 _print_next_block((*par_num)++, "XSDM");
4679 XSDM_REG_XSDM_PRTY_STS);
4682 case AEU_INPUTS_ATTN_BITS_XCM_PARITY_ERROR:
4684 _print_next_block((*par_num)++, "XCM");
4685 _print_parity(bp, XCM_REG_XCM_PRTY_STS);
4688 case AEU_INPUTS_ATTN_BITS_XSEMI_PARITY_ERROR:
4690 _print_next_block((*par_num)++,
4693 XSEM_REG_XSEM_PRTY_STS_0);
4695 XSEM_REG_XSEM_PRTY_STS_1);
4698 case AEU_INPUTS_ATTN_BITS_DOORBELLQ_PARITY_ERROR:
4700 _print_next_block((*par_num)++,
4703 DORQ_REG_DORQ_PRTY_STS);
4706 case AEU_INPUTS_ATTN_BITS_NIG_PARITY_ERROR:
4708 _print_next_block((*par_num)++, "NIG");
4709 if (CHIP_IS_E1x(bp)) {
4711 NIG_REG_NIG_PRTY_STS);
4714 NIG_REG_NIG_PRTY_STS_0);
4716 NIG_REG_NIG_PRTY_STS_1);
4720 case AEU_INPUTS_ATTN_BITS_VAUX_PCI_CORE_PARITY_ERROR:
4722 _print_next_block((*par_num)++,
4726 case AEU_INPUTS_ATTN_BITS_DEBUG_PARITY_ERROR:
4728 _print_next_block((*par_num)++,
4730 _print_parity(bp, DBG_REG_DBG_PRTY_STS);
4733 case AEU_INPUTS_ATTN_BITS_USDM_PARITY_ERROR:
4735 _print_next_block((*par_num)++, "USDM");
4737 USDM_REG_USDM_PRTY_STS);
4740 case AEU_INPUTS_ATTN_BITS_UCM_PARITY_ERROR:
4742 _print_next_block((*par_num)++, "UCM");
4743 _print_parity(bp, UCM_REG_UCM_PRTY_STS);
4746 case AEU_INPUTS_ATTN_BITS_USEMI_PARITY_ERROR:
4748 _print_next_block((*par_num)++,
4751 USEM_REG_USEM_PRTY_STS_0);
4753 USEM_REG_USEM_PRTY_STS_1);
4756 case AEU_INPUTS_ATTN_BITS_UPB_PARITY_ERROR:
4758 _print_next_block((*par_num)++, "UPB");
4759 _print_parity(bp, GRCBASE_UPB +
4760 PB_REG_PB_PRTY_STS);
4763 case AEU_INPUTS_ATTN_BITS_CSDM_PARITY_ERROR:
4765 _print_next_block((*par_num)++, "CSDM");
4767 CSDM_REG_CSDM_PRTY_STS);
4770 case AEU_INPUTS_ATTN_BITS_CCM_PARITY_ERROR:
4772 _print_next_block((*par_num)++, "CCM");
4773 _print_parity(bp, CCM_REG_CCM_PRTY_STS);
4786 static bool bnx2x_check_blocks_with_parity2(struct bnx2x *bp, u32 sig,
4787 int *par_num, bool print)
4795 for (i = 0; sig; i++) {
4796 cur_bit = (0x1UL << i);
4797 if (sig & cur_bit) {
4798 res = true; /* Each bit is real error! */
4801 case AEU_INPUTS_ATTN_BITS_CSEMI_PARITY_ERROR:
4802 _print_next_block((*par_num)++,
4805 CSEM_REG_CSEM_PRTY_STS_0);
4807 CSEM_REG_CSEM_PRTY_STS_1);
4809 case AEU_INPUTS_ATTN_BITS_PXP_PARITY_ERROR:
4810 _print_next_block((*par_num)++, "PXP");
4811 _print_parity(bp, PXP_REG_PXP_PRTY_STS);
4813 PXP2_REG_PXP2_PRTY_STS_0);
4815 PXP2_REG_PXP2_PRTY_STS_1);
4817 case AEU_IN_ATTN_BITS_PXPPCICLOCKCLIENT_PARITY_ERROR:
4818 _print_next_block((*par_num)++,
4819 "PXPPCICLOCKCLIENT");
4821 case AEU_INPUTS_ATTN_BITS_CFC_PARITY_ERROR:
4822 _print_next_block((*par_num)++, "CFC");
4824 CFC_REG_CFC_PRTY_STS);
4826 case AEU_INPUTS_ATTN_BITS_CDU_PARITY_ERROR:
4827 _print_next_block((*par_num)++, "CDU");
4828 _print_parity(bp, CDU_REG_CDU_PRTY_STS);
4830 case AEU_INPUTS_ATTN_BITS_DMAE_PARITY_ERROR:
4831 _print_next_block((*par_num)++, "DMAE");
4833 DMAE_REG_DMAE_PRTY_STS);
4835 case AEU_INPUTS_ATTN_BITS_IGU_PARITY_ERROR:
4836 _print_next_block((*par_num)++, "IGU");
4837 if (CHIP_IS_E1x(bp))
4839 HC_REG_HC_PRTY_STS);
4842 IGU_REG_IGU_PRTY_STS);
4844 case AEU_INPUTS_ATTN_BITS_MISC_PARITY_ERROR:
4845 _print_next_block((*par_num)++, "MISC");
4847 MISC_REG_MISC_PRTY_STS);
4860 static bool bnx2x_check_blocks_with_parity3(struct bnx2x *bp, u32 sig,
4861 int *par_num, bool *global,
4868 for (i = 0; sig; i++) {
4869 cur_bit = (0x1UL << i);
4870 if (sig & cur_bit) {
4872 case AEU_INPUTS_ATTN_BITS_MCP_LATCHED_ROM_PARITY:
4874 _print_next_block((*par_num)++,
4879 case AEU_INPUTS_ATTN_BITS_MCP_LATCHED_UMP_RX_PARITY:
4881 _print_next_block((*par_num)++,
4886 case AEU_INPUTS_ATTN_BITS_MCP_LATCHED_UMP_TX_PARITY:
4888 _print_next_block((*par_num)++,
4893 case AEU_INPUTS_ATTN_BITS_MCP_LATCHED_SCPAD_PARITY:
4895 /* clear latched SCPAD PATIRY from MCP */
4896 REG_WR(bp, MISC_REG_AEU_CLR_LATCH_SIGNAL,
4909 static bool bnx2x_check_blocks_with_parity4(struct bnx2x *bp, u32 sig,
4910 int *par_num, bool print)
4918 for (i = 0; sig; i++) {
4919 cur_bit = (0x1UL << i);
4920 if (sig & cur_bit) {
4921 res = true; /* Each bit is real error! */
4924 case AEU_INPUTS_ATTN_BITS_PGLUE_PARITY_ERROR:
4925 _print_next_block((*par_num)++,
4928 PGLUE_B_REG_PGLUE_B_PRTY_STS);
4930 case AEU_INPUTS_ATTN_BITS_ATC_PARITY_ERROR:
4931 _print_next_block((*par_num)++, "ATC");
4933 ATC_REG_ATC_PRTY_STS);
4945 static bool bnx2x_parity_attn(struct bnx2x *bp, bool *global, bool print,
4950 if ((sig[0] & HW_PRTY_ASSERT_SET_0) ||
4951 (sig[1] & HW_PRTY_ASSERT_SET_1) ||
4952 (sig[2] & HW_PRTY_ASSERT_SET_2) ||
4953 (sig[3] & HW_PRTY_ASSERT_SET_3) ||
4954 (sig[4] & HW_PRTY_ASSERT_SET_4)) {
4957 DP(NETIF_MSG_HW, "Was parity error: HW block parity attention:\n"
4958 "[0]:0x%08x [1]:0x%08x [2]:0x%08x [3]:0x%08x [4]:0x%08x\n",
4959 sig[0] & HW_PRTY_ASSERT_SET_0,
4960 sig[1] & HW_PRTY_ASSERT_SET_1,
4961 sig[2] & HW_PRTY_ASSERT_SET_2,
4962 sig[3] & HW_PRTY_ASSERT_SET_3,
4963 sig[4] & HW_PRTY_ASSERT_SET_4);
4965 if (((sig[0] & HW_PRTY_ASSERT_SET_0) ||
4966 (sig[1] & HW_PRTY_ASSERT_SET_1) ||
4967 (sig[2] & HW_PRTY_ASSERT_SET_2) ||
4968 (sig[4] & HW_PRTY_ASSERT_SET_4)) ||
4969 (sig[3] & HW_PRTY_ASSERT_SET_3_WITHOUT_SCPAD)) {
4971 "Parity errors detected in blocks: ");
4976 res |= bnx2x_check_blocks_with_parity0(bp,
4977 sig[0] & HW_PRTY_ASSERT_SET_0, &par_num, print);
4978 res |= bnx2x_check_blocks_with_parity1(bp,
4979 sig[1] & HW_PRTY_ASSERT_SET_1, &par_num, global, print);
4980 res |= bnx2x_check_blocks_with_parity2(bp,
4981 sig[2] & HW_PRTY_ASSERT_SET_2, &par_num, print);
4982 res |= bnx2x_check_blocks_with_parity3(bp,
4983 sig[3] & HW_PRTY_ASSERT_SET_3, &par_num, global, print);
4984 res |= bnx2x_check_blocks_with_parity4(bp,
4985 sig[4] & HW_PRTY_ASSERT_SET_4, &par_num, print);
4995 * bnx2x_chk_parity_attn - checks for parity attentions.
4997 * @bp: driver handle
4998 * @global: true if there was a global attention
4999 * @print: show parity attention in syslog
5001 bool bnx2x_chk_parity_attn(struct bnx2x *bp, bool *global, bool print)
5003 struct attn_route attn = { {0} };
5004 int port = BP_PORT(bp);
5006 attn.sig[0] = REG_RD(bp,
5007 MISC_REG_AEU_AFTER_INVERT_1_FUNC_0 +
5009 attn.sig[1] = REG_RD(bp,
5010 MISC_REG_AEU_AFTER_INVERT_2_FUNC_0 +
5012 attn.sig[2] = REG_RD(bp,
5013 MISC_REG_AEU_AFTER_INVERT_3_FUNC_0 +
5015 attn.sig[3] = REG_RD(bp,
5016 MISC_REG_AEU_AFTER_INVERT_4_FUNC_0 +
5018 /* Since MCP attentions can't be disabled inside the block, we need to
5019 * read AEU registers to see whether they're currently disabled
5021 attn.sig[3] &= ((REG_RD(bp,
5022 !port ? MISC_REG_AEU_ENABLE4_FUNC_0_OUT_0
5023 : MISC_REG_AEU_ENABLE4_FUNC_1_OUT_0) &
5024 MISC_AEU_ENABLE_MCP_PRTY_BITS) |
5025 ~MISC_AEU_ENABLE_MCP_PRTY_BITS);
5027 if (!CHIP_IS_E1x(bp))
5028 attn.sig[4] = REG_RD(bp,
5029 MISC_REG_AEU_AFTER_INVERT_5_FUNC_0 +
5032 return bnx2x_parity_attn(bp, global, print, attn.sig);
5035 static void bnx2x_attn_int_deasserted4(struct bnx2x *bp, u32 attn)
5038 if (attn & AEU_INPUTS_ATTN_BITS_PGLUE_HW_INTERRUPT) {
5040 val = REG_RD(bp, PGLUE_B_REG_PGLUE_B_INT_STS_CLR);
5041 BNX2X_ERR("PGLUE hw attention 0x%x\n", val);
5042 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_ADDRESS_ERROR)
5043 BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_ADDRESS_ERROR\n");
5044 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_INCORRECT_RCV_BEHAVIOR)
5045 BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_INCORRECT_RCV_BEHAVIOR\n");
5046 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_WAS_ERROR_ATTN)
5047 BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_WAS_ERROR_ATTN\n");
5048 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_VF_LENGTH_VIOLATION_ATTN)
5049 BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_VF_LENGTH_VIOLATION_ATTN\n");
5051 PGLUE_B_PGLUE_B_INT_STS_REG_VF_GRC_SPACE_VIOLATION_ATTN)
5052 BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_VF_GRC_SPACE_VIOLATION_ATTN\n");
5054 PGLUE_B_PGLUE_B_INT_STS_REG_VF_MSIX_BAR_VIOLATION_ATTN)
5055 BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_VF_MSIX_BAR_VIOLATION_ATTN\n");
5056 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_TCPL_ERROR_ATTN)
5057 BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_TCPL_ERROR_ATTN\n");
5058 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_TCPL_IN_TWO_RCBS_ATTN)
5059 BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_TCPL_IN_TWO_RCBS_ATTN\n");
5060 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_CSSNOOP_FIFO_OVERFLOW)
5061 BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_CSSNOOP_FIFO_OVERFLOW\n");
5063 if (attn & AEU_INPUTS_ATTN_BITS_ATC_HW_INTERRUPT) {
5064 val = REG_RD(bp, ATC_REG_ATC_INT_STS_CLR);
5065 BNX2X_ERR("ATC hw attention 0x%x\n", val);
5066 if (val & ATC_ATC_INT_STS_REG_ADDRESS_ERROR)
5067 BNX2X_ERR("ATC_ATC_INT_STS_REG_ADDRESS_ERROR\n");
5068 if (val & ATC_ATC_INT_STS_REG_ATC_TCPL_TO_NOT_PEND)
5069 BNX2X_ERR("ATC_ATC_INT_STS_REG_ATC_TCPL_TO_NOT_PEND\n");
5070 if (val & ATC_ATC_INT_STS_REG_ATC_GPA_MULTIPLE_HITS)
5071 BNX2X_ERR("ATC_ATC_INT_STS_REG_ATC_GPA_MULTIPLE_HITS\n");
5072 if (val & ATC_ATC_INT_STS_REG_ATC_RCPL_TO_EMPTY_CNT)
5073 BNX2X_ERR("ATC_ATC_INT_STS_REG_ATC_RCPL_TO_EMPTY_CNT\n");
5074 if (val & ATC_ATC_INT_STS_REG_ATC_TCPL_ERROR)
5075 BNX2X_ERR("ATC_ATC_INT_STS_REG_ATC_TCPL_ERROR\n");
5076 if (val & ATC_ATC_INT_STS_REG_ATC_IREQ_LESS_THAN_STU)
5077 BNX2X_ERR("ATC_ATC_INT_STS_REG_ATC_IREQ_LESS_THAN_STU\n");
5080 if (attn & (AEU_INPUTS_ATTN_BITS_PGLUE_PARITY_ERROR |
5081 AEU_INPUTS_ATTN_BITS_ATC_PARITY_ERROR)) {
5082 BNX2X_ERR("FATAL parity attention set4 0x%x\n",
5083 (u32)(attn & (AEU_INPUTS_ATTN_BITS_PGLUE_PARITY_ERROR |
5084 AEU_INPUTS_ATTN_BITS_ATC_PARITY_ERROR)));
5088 static void bnx2x_attn_int_deasserted(struct bnx2x *bp, u32 deasserted)
5090 struct attn_route attn, *group_mask;
5091 int port = BP_PORT(bp);
5096 bool global = false;
5098 /* need to take HW lock because MCP or other port might also
5099 try to handle this event */
5100 bnx2x_acquire_alr(bp);
5102 if (bnx2x_chk_parity_attn(bp, &global, true)) {
5103 #ifndef BNX2X_STOP_ON_ERROR
5104 bp->recovery_state = BNX2X_RECOVERY_INIT;
5105 schedule_delayed_work(&bp->sp_rtnl_task, 0);
5106 /* Disable HW interrupts */
5107 bnx2x_int_disable(bp);
5108 /* In case of parity errors don't handle attentions so that
5109 * other function would "see" parity errors.
5114 bnx2x_release_alr(bp);
5118 attn.sig[0] = REG_RD(bp, MISC_REG_AEU_AFTER_INVERT_1_FUNC_0 + port*4);
5119 attn.sig[1] = REG_RD(bp, MISC_REG_AEU_AFTER_INVERT_2_FUNC_0 + port*4);
5120 attn.sig[2] = REG_RD(bp, MISC_REG_AEU_AFTER_INVERT_3_FUNC_0 + port*4);
5121 attn.sig[3] = REG_RD(bp, MISC_REG_AEU_AFTER_INVERT_4_FUNC_0 + port*4);
5122 if (!CHIP_IS_E1x(bp))
5124 REG_RD(bp, MISC_REG_AEU_AFTER_INVERT_5_FUNC_0 + port*4);
5128 DP(NETIF_MSG_HW, "attn: %08x %08x %08x %08x %08x\n",
5129 attn.sig[0], attn.sig[1], attn.sig[2], attn.sig[3], attn.sig[4]);
5131 for (index = 0; index < MAX_DYNAMIC_ATTN_GRPS; index++) {
5132 if (deasserted & (1 << index)) {
5133 group_mask = &bp->attn_group[index];
5135 DP(NETIF_MSG_HW, "group[%d]: %08x %08x %08x %08x %08x\n",
5137 group_mask->sig[0], group_mask->sig[1],
5138 group_mask->sig[2], group_mask->sig[3],
5139 group_mask->sig[4]);
5141 bnx2x_attn_int_deasserted4(bp,
5142 attn.sig[4] & group_mask->sig[4]);
5143 bnx2x_attn_int_deasserted3(bp,
5144 attn.sig[3] & group_mask->sig[3]);
5145 bnx2x_attn_int_deasserted1(bp,
5146 attn.sig[1] & group_mask->sig[1]);
5147 bnx2x_attn_int_deasserted2(bp,
5148 attn.sig[2] & group_mask->sig[2]);
5149 bnx2x_attn_int_deasserted0(bp,
5150 attn.sig[0] & group_mask->sig[0]);
5154 bnx2x_release_alr(bp);
5156 if (bp->common.int_block == INT_BLOCK_HC)
5157 reg_addr = (HC_REG_COMMAND_REG + port*32 +
5158 COMMAND_REG_ATTN_BITS_CLR);
5160 reg_addr = (BAR_IGU_INTMEM + IGU_CMD_ATTN_BIT_CLR_UPPER*8);
5163 DP(NETIF_MSG_HW, "about to mask 0x%08x at %s addr 0x%x\n", val,
5164 (bp->common.int_block == INT_BLOCK_HC) ? "HC" : "IGU", reg_addr);
5165 REG_WR(bp, reg_addr, val);
5167 if (~bp->attn_state & deasserted)
5168 BNX2X_ERR("IGU ERROR\n");
5170 reg_addr = port ? MISC_REG_AEU_MASK_ATTN_FUNC_1 :
5171 MISC_REG_AEU_MASK_ATTN_FUNC_0;
5173 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_PORT0_ATT_MASK + port);
5174 aeu_mask = REG_RD(bp, reg_addr);
5176 DP(NETIF_MSG_HW, "aeu_mask %x newly deasserted %x\n",
5177 aeu_mask, deasserted);
5178 aeu_mask |= (deasserted & 0x3ff);
5179 DP(NETIF_MSG_HW, "new mask %x\n", aeu_mask);
5181 REG_WR(bp, reg_addr, aeu_mask);
5182 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_PORT0_ATT_MASK + port);
5184 DP(NETIF_MSG_HW, "attn_state %x\n", bp->attn_state);
5185 bp->attn_state &= ~deasserted;
5186 DP(NETIF_MSG_HW, "new state %x\n", bp->attn_state);
5189 static void bnx2x_attn_int(struct bnx2x *bp)
5191 /* read local copy of bits */
5192 u32 attn_bits = le32_to_cpu(bp->def_status_blk->atten_status_block.
5194 u32 attn_ack = le32_to_cpu(bp->def_status_blk->atten_status_block.
5196 u32 attn_state = bp->attn_state;
5198 /* look for changed bits */
5199 u32 asserted = attn_bits & ~attn_ack & ~attn_state;
5200 u32 deasserted = ~attn_bits & attn_ack & attn_state;
5203 "attn_bits %x attn_ack %x asserted %x deasserted %x\n",
5204 attn_bits, attn_ack, asserted, deasserted);
5206 if (~(attn_bits ^ attn_ack) & (attn_bits ^ attn_state))
5207 BNX2X_ERR("BAD attention state\n");
5209 /* handle bits that were raised */
5211 bnx2x_attn_int_asserted(bp, asserted);
5214 bnx2x_attn_int_deasserted(bp, deasserted);
5217 void bnx2x_igu_ack_sb(struct bnx2x *bp, u8 igu_sb_id, u8 segment,
5218 u16 index, u8 op, u8 update)
5220 u32 igu_addr = bp->igu_base_addr;
5221 igu_addr += (IGU_CMD_INT_ACK_BASE + igu_sb_id)*8;
5222 bnx2x_igu_ack_sb_gen(bp, igu_sb_id, segment, index, op, update,
5226 static void bnx2x_update_eq_prod(struct bnx2x *bp, u16 prod)
5228 /* No memory barriers */
5229 storm_memset_eq_prod(bp, prod, BP_FUNC(bp));
5230 mmiowb(); /* keep prod updates ordered */
5233 static int bnx2x_cnic_handle_cfc_del(struct bnx2x *bp, u32 cid,
5234 union event_ring_elem *elem)
5236 u8 err = elem->message.error;
5238 if (!bp->cnic_eth_dev.starting_cid ||
5239 (cid < bp->cnic_eth_dev.starting_cid &&
5240 cid != bp->cnic_eth_dev.iscsi_l2_cid))
5243 DP(BNX2X_MSG_SP, "got delete ramrod for CNIC CID %d\n", cid);
5245 if (unlikely(err)) {
5247 BNX2X_ERR("got delete ramrod for CNIC CID %d with error!\n",
5249 bnx2x_panic_dump(bp, false);
5251 bnx2x_cnic_cfc_comp(bp, cid, err);
5255 static void bnx2x_handle_mcast_eqe(struct bnx2x *bp)
5257 struct bnx2x_mcast_ramrod_params rparam;
5260 memset(&rparam, 0, sizeof(rparam));
5262 rparam.mcast_obj = &bp->mcast_obj;
5264 netif_addr_lock_bh(bp->dev);
5266 /* Clear pending state for the last command */
5267 bp->mcast_obj.raw.clear_pending(&bp->mcast_obj.raw);
5269 /* If there are pending mcast commands - send them */
5270 if (bp->mcast_obj.check_pending(&bp->mcast_obj)) {
5271 rc = bnx2x_config_mcast(bp, &rparam, BNX2X_MCAST_CMD_CONT);
5273 BNX2X_ERR("Failed to send pending mcast commands: %d\n",
5277 netif_addr_unlock_bh(bp->dev);
5280 static void bnx2x_handle_classification_eqe(struct bnx2x *bp,
5281 union event_ring_elem *elem)
5283 unsigned long ramrod_flags = 0;
5285 u32 cid = elem->message.data.eth_event.echo & BNX2X_SWCID_MASK;
5286 struct bnx2x_vlan_mac_obj *vlan_mac_obj;
5288 /* Always push next commands out, don't wait here */
5289 __set_bit(RAMROD_CONT, &ramrod_flags);
5291 switch (le32_to_cpu((__force __le32)elem->message.data.eth_event.echo)
5292 >> BNX2X_SWCID_SHIFT) {
5293 case BNX2X_FILTER_MAC_PENDING:
5294 DP(BNX2X_MSG_SP, "Got SETUP_MAC completions\n");
5295 if (CNIC_LOADED(bp) && (cid == BNX2X_ISCSI_ETH_CID(bp)))
5296 vlan_mac_obj = &bp->iscsi_l2_mac_obj;
5298 vlan_mac_obj = &bp->sp_objs[cid].mac_obj;
5301 case BNX2X_FILTER_VLAN_PENDING:
5302 DP(BNX2X_MSG_SP, "Got SETUP_VLAN completions\n");
5303 vlan_mac_obj = &bp->sp_objs[cid].vlan_obj;
5305 case BNX2X_FILTER_MCAST_PENDING:
5306 DP(BNX2X_MSG_SP, "Got SETUP_MCAST completions\n");
5307 /* This is only relevant for 57710 where multicast MACs are
5308 * configured as unicast MACs using the same ramrod.
5310 bnx2x_handle_mcast_eqe(bp);
5313 BNX2X_ERR("Unsupported classification command: %d\n",
5314 elem->message.data.eth_event.echo);
5318 rc = vlan_mac_obj->complete(bp, vlan_mac_obj, elem, &ramrod_flags);
5321 BNX2X_ERR("Failed to schedule new commands: %d\n", rc);
5323 DP(BNX2X_MSG_SP, "Scheduled next pending commands...\n");
5326 static void bnx2x_set_iscsi_eth_rx_mode(struct bnx2x *bp, bool start);
5328 static void bnx2x_handle_rx_mode_eqe(struct bnx2x *bp)
5330 netif_addr_lock_bh(bp->dev);
5332 clear_bit(BNX2X_FILTER_RX_MODE_PENDING, &bp->sp_state);
5334 /* Send rx_mode command again if was requested */
5335 if (test_and_clear_bit(BNX2X_FILTER_RX_MODE_SCHED, &bp->sp_state))
5336 bnx2x_set_storm_rx_mode(bp);
5337 else if (test_and_clear_bit(BNX2X_FILTER_ISCSI_ETH_START_SCHED,
5339 bnx2x_set_iscsi_eth_rx_mode(bp, true);
5340 else if (test_and_clear_bit(BNX2X_FILTER_ISCSI_ETH_STOP_SCHED,
5342 bnx2x_set_iscsi_eth_rx_mode(bp, false);
5344 netif_addr_unlock_bh(bp->dev);
5347 static void bnx2x_after_afex_vif_lists(struct bnx2x *bp,
5348 union event_ring_elem *elem)
5350 if (elem->message.data.vif_list_event.echo == VIF_LIST_RULE_GET) {
5352 "afex: ramrod completed VIF LIST_GET, addrs 0x%x\n",
5353 elem->message.data.vif_list_event.func_bit_map);
5354 bnx2x_fw_command(bp, DRV_MSG_CODE_AFEX_LISTGET_ACK,
5355 elem->message.data.vif_list_event.func_bit_map);
5356 } else if (elem->message.data.vif_list_event.echo ==
5357 VIF_LIST_RULE_SET) {
5358 DP(BNX2X_MSG_SP, "afex: ramrod completed VIF LIST_SET\n");
5359 bnx2x_fw_command(bp, DRV_MSG_CODE_AFEX_LISTSET_ACK, 0);
5363 /* called with rtnl_lock */
5364 static void bnx2x_after_function_update(struct bnx2x *bp)
5367 struct bnx2x_fastpath *fp;
5368 struct bnx2x_queue_state_params queue_params = {NULL};
5369 struct bnx2x_queue_update_params *q_update_params =
5370 &queue_params.params.update;
5372 /* Send Q update command with afex vlan removal values for all Qs */
5373 queue_params.cmd = BNX2X_Q_CMD_UPDATE;
5375 /* set silent vlan removal values according to vlan mode */
5376 __set_bit(BNX2X_Q_UPDATE_SILENT_VLAN_REM_CHNG,
5377 &q_update_params->update_flags);
5378 __set_bit(BNX2X_Q_UPDATE_SILENT_VLAN_REM,
5379 &q_update_params->update_flags);
5380 __set_bit(RAMROD_COMP_WAIT, &queue_params.ramrod_flags);
5382 /* in access mode mark mask and value are 0 to strip all vlans */
5383 if (bp->afex_vlan_mode == FUNC_MF_CFG_AFEX_VLAN_ACCESS_MODE) {
5384 q_update_params->silent_removal_value = 0;
5385 q_update_params->silent_removal_mask = 0;
5387 q_update_params->silent_removal_value =
5388 (bp->afex_def_vlan_tag & VLAN_VID_MASK);
5389 q_update_params->silent_removal_mask = VLAN_VID_MASK;
5392 for_each_eth_queue(bp, q) {
5393 /* Set the appropriate Queue object */
5395 queue_params.q_obj = &bnx2x_sp_obj(bp, fp).q_obj;
5397 /* send the ramrod */
5398 rc = bnx2x_queue_state_change(bp, &queue_params);
5400 BNX2X_ERR("Failed to config silent vlan rem for Q %d\n",
5404 if (!NO_FCOE(bp) && CNIC_ENABLED(bp)) {
5405 fp = &bp->fp[FCOE_IDX(bp)];
5406 queue_params.q_obj = &bnx2x_sp_obj(bp, fp).q_obj;
5408 /* clear pending completion bit */
5409 __clear_bit(RAMROD_COMP_WAIT, &queue_params.ramrod_flags);
5411 /* mark latest Q bit */
5412 smp_mb__before_atomic();
5413 set_bit(BNX2X_AFEX_FCOE_Q_UPDATE_PENDING, &bp->sp_state);
5414 smp_mb__after_atomic();
5416 /* send Q update ramrod for FCoE Q */
5417 rc = bnx2x_queue_state_change(bp, &queue_params);
5419 BNX2X_ERR("Failed to config silent vlan rem for Q %d\n",
5422 /* If no FCoE ring - ACK MCP now */
5423 bnx2x_link_report(bp);
5424 bnx2x_fw_command(bp, DRV_MSG_CODE_AFEX_VIFSET_ACK, 0);
5428 static struct bnx2x_queue_sp_obj *bnx2x_cid_to_q_obj(
5429 struct bnx2x *bp, u32 cid)
5431 DP(BNX2X_MSG_SP, "retrieving fp from cid %d\n", cid);
5433 if (CNIC_LOADED(bp) && (cid == BNX2X_FCOE_ETH_CID(bp)))
5434 return &bnx2x_fcoe_sp_obj(bp, q_obj);
5436 return &bp->sp_objs[CID_TO_FP(cid, bp)].q_obj;
5439 static void bnx2x_eq_int(struct bnx2x *bp)
5441 u16 hw_cons, sw_cons, sw_prod;
5442 union event_ring_elem *elem;
5446 int rc, spqe_cnt = 0;
5447 struct bnx2x_queue_sp_obj *q_obj;
5448 struct bnx2x_func_sp_obj *f_obj = &bp->func_obj;
5449 struct bnx2x_raw_obj *rss_raw = &bp->rss_conf_obj.raw;
5451 hw_cons = le16_to_cpu(*bp->eq_cons_sb);
5453 /* The hw_cos range is 1-255, 257 - the sw_cons range is 0-254, 256.
5454 * when we get the next-page we need to adjust so the loop
5455 * condition below will be met. The next element is the size of a
5456 * regular element and hence incrementing by 1
5458 if ((hw_cons & EQ_DESC_MAX_PAGE) == EQ_DESC_MAX_PAGE)
5461 /* This function may never run in parallel with itself for a
5462 * specific bp, thus there is no need in "paired" read memory
5465 sw_cons = bp->eq_cons;
5466 sw_prod = bp->eq_prod;
5468 DP(BNX2X_MSG_SP, "EQ: hw_cons %u sw_cons %u bp->eq_spq_left %x\n",
5469 hw_cons, sw_cons, atomic_read(&bp->eq_spq_left));
5471 for (; sw_cons != hw_cons;
5472 sw_prod = NEXT_EQ_IDX(sw_prod), sw_cons = NEXT_EQ_IDX(sw_cons)) {
5474 elem = &bp->eq_ring[EQ_DESC(sw_cons)];
5476 rc = bnx2x_iov_eq_sp_event(bp, elem);
5478 DP(BNX2X_MSG_IOV, "bnx2x_iov_eq_sp_event returned %d\n",
5483 /* elem CID originates from FW; actually LE */
5484 cid = SW_CID((__force __le32)
5485 elem->message.data.cfc_del_event.cid);
5486 opcode = elem->message.opcode;
5488 /* handle eq element */
5490 case EVENT_RING_OPCODE_VF_PF_CHANNEL:
5491 bnx2x_vf_mbx_schedule(bp,
5492 &elem->message.data.vf_pf_event);
5495 case EVENT_RING_OPCODE_STAT_QUERY:
5496 DP_AND((BNX2X_MSG_SP | BNX2X_MSG_STATS),
5497 "got statistics comp event %d\n",
5499 /* nothing to do with stats comp */
5502 case EVENT_RING_OPCODE_CFC_DEL:
5503 /* handle according to cid range */
5505 * we may want to verify here that the bp state is
5509 "got delete ramrod for MULTI[%d]\n", cid);
5511 if (CNIC_LOADED(bp) &&
5512 !bnx2x_cnic_handle_cfc_del(bp, cid, elem))
5515 q_obj = bnx2x_cid_to_q_obj(bp, cid);
5517 if (q_obj->complete_cmd(bp, q_obj, BNX2X_Q_CMD_CFC_DEL))
5522 case EVENT_RING_OPCODE_STOP_TRAFFIC:
5523 DP(BNX2X_MSG_SP | BNX2X_MSG_DCB, "got STOP TRAFFIC\n");
5524 bnx2x_dcbx_set_params(bp, BNX2X_DCBX_STATE_TX_PAUSED);
5525 if (f_obj->complete_cmd(bp, f_obj,
5526 BNX2X_F_CMD_TX_STOP))
5530 case EVENT_RING_OPCODE_START_TRAFFIC:
5531 DP(BNX2X_MSG_SP | BNX2X_MSG_DCB, "got START TRAFFIC\n");
5532 bnx2x_dcbx_set_params(bp, BNX2X_DCBX_STATE_TX_RELEASED);
5533 if (f_obj->complete_cmd(bp, f_obj,
5534 BNX2X_F_CMD_TX_START))
5538 case EVENT_RING_OPCODE_FUNCTION_UPDATE:
5539 echo = elem->message.data.function_update_event.echo;
5540 if (echo == SWITCH_UPDATE) {
5541 DP(BNX2X_MSG_SP | NETIF_MSG_IFUP,
5542 "got FUNC_SWITCH_UPDATE ramrod\n");
5543 if (f_obj->complete_cmd(
5544 bp, f_obj, BNX2X_F_CMD_SWITCH_UPDATE))
5548 int cmd = BNX2X_SP_RTNL_AFEX_F_UPDATE;
5550 DP(BNX2X_MSG_SP | BNX2X_MSG_MCP,
5551 "AFEX: ramrod completed FUNCTION_UPDATE\n");
5552 f_obj->complete_cmd(bp, f_obj,
5553 BNX2X_F_CMD_AFEX_UPDATE);
5555 /* We will perform the Queues update from
5556 * sp_rtnl task as all Queue SP operations
5557 * should run under rtnl_lock.
5559 bnx2x_schedule_sp_rtnl(bp, cmd, 0);
5564 case EVENT_RING_OPCODE_AFEX_VIF_LISTS:
5565 f_obj->complete_cmd(bp, f_obj,
5566 BNX2X_F_CMD_AFEX_VIFLISTS);
5567 bnx2x_after_afex_vif_lists(bp, elem);
5569 case EVENT_RING_OPCODE_FUNCTION_START:
5570 DP(BNX2X_MSG_SP | NETIF_MSG_IFUP,
5571 "got FUNC_START ramrod\n");
5572 if (f_obj->complete_cmd(bp, f_obj, BNX2X_F_CMD_START))
5577 case EVENT_RING_OPCODE_FUNCTION_STOP:
5578 DP(BNX2X_MSG_SP | NETIF_MSG_IFUP,
5579 "got FUNC_STOP ramrod\n");
5580 if (f_obj->complete_cmd(bp, f_obj, BNX2X_F_CMD_STOP))
5585 case EVENT_RING_OPCODE_SET_TIMESYNC:
5586 DP(BNX2X_MSG_SP | BNX2X_MSG_PTP,
5587 "got set_timesync ramrod completion\n");
5588 if (f_obj->complete_cmd(bp, f_obj,
5589 BNX2X_F_CMD_SET_TIMESYNC))
5594 switch (opcode | bp->state) {
5595 case (EVENT_RING_OPCODE_RSS_UPDATE_RULES |
5597 case (EVENT_RING_OPCODE_RSS_UPDATE_RULES |
5598 BNX2X_STATE_OPENING_WAIT4_PORT):
5599 case (EVENT_RING_OPCODE_RSS_UPDATE_RULES |
5600 BNX2X_STATE_CLOSING_WAIT4_HALT):
5601 cid = elem->message.data.eth_event.echo &
5603 DP(BNX2X_MSG_SP, "got RSS_UPDATE ramrod. CID %d\n",
5605 rss_raw->clear_pending(rss_raw);
5608 case (EVENT_RING_OPCODE_SET_MAC | BNX2X_STATE_OPEN):
5609 case (EVENT_RING_OPCODE_SET_MAC | BNX2X_STATE_DIAG):
5610 case (EVENT_RING_OPCODE_SET_MAC |
5611 BNX2X_STATE_CLOSING_WAIT4_HALT):
5612 case (EVENT_RING_OPCODE_CLASSIFICATION_RULES |
5614 case (EVENT_RING_OPCODE_CLASSIFICATION_RULES |
5616 case (EVENT_RING_OPCODE_CLASSIFICATION_RULES |
5617 BNX2X_STATE_CLOSING_WAIT4_HALT):
5618 DP(BNX2X_MSG_SP, "got (un)set vlan/mac ramrod\n");
5619 bnx2x_handle_classification_eqe(bp, elem);
5622 case (EVENT_RING_OPCODE_MULTICAST_RULES |
5624 case (EVENT_RING_OPCODE_MULTICAST_RULES |
5626 case (EVENT_RING_OPCODE_MULTICAST_RULES |
5627 BNX2X_STATE_CLOSING_WAIT4_HALT):
5628 DP(BNX2X_MSG_SP, "got mcast ramrod\n");
5629 bnx2x_handle_mcast_eqe(bp);
5632 case (EVENT_RING_OPCODE_FILTERS_RULES |
5634 case (EVENT_RING_OPCODE_FILTERS_RULES |
5636 case (EVENT_RING_OPCODE_FILTERS_RULES |
5637 BNX2X_STATE_CLOSING_WAIT4_HALT):
5638 DP(BNX2X_MSG_SP, "got rx_mode ramrod\n");
5639 bnx2x_handle_rx_mode_eqe(bp);
5642 /* unknown event log error and continue */
5643 BNX2X_ERR("Unknown EQ event %d, bp->state 0x%x\n",
5644 elem->message.opcode, bp->state);
5650 smp_mb__before_atomic();
5651 atomic_add(spqe_cnt, &bp->eq_spq_left);
5653 bp->eq_cons = sw_cons;
5654 bp->eq_prod = sw_prod;
5655 /* Make sure that above mem writes were issued towards the memory */
5658 /* update producer */
5659 bnx2x_update_eq_prod(bp, bp->eq_prod);
5662 static void bnx2x_sp_task(struct work_struct *work)
5664 struct bnx2x *bp = container_of(work, struct bnx2x, sp_task.work);
5666 DP(BNX2X_MSG_SP, "sp task invoked\n");
5668 /* make sure the atomic interrupt_occurred has been written */
5670 if (atomic_read(&bp->interrupt_occurred)) {
5672 /* what work needs to be performed? */
5673 u16 status = bnx2x_update_dsb_idx(bp);
5675 DP(BNX2X_MSG_SP, "status %x\n", status);
5676 DP(BNX2X_MSG_SP, "setting interrupt_occurred to 0\n");
5677 atomic_set(&bp->interrupt_occurred, 0);
5680 if (status & BNX2X_DEF_SB_ATT_IDX) {
5682 status &= ~BNX2X_DEF_SB_ATT_IDX;
5685 /* SP events: STAT_QUERY and others */
5686 if (status & BNX2X_DEF_SB_IDX) {
5687 struct bnx2x_fastpath *fp = bnx2x_fcoe_fp(bp);
5689 if (FCOE_INIT(bp) &&
5690 (bnx2x_has_rx_work(fp) || bnx2x_has_tx_work(fp))) {
5691 /* Prevent local bottom-halves from running as
5692 * we are going to change the local NAPI list.
5695 napi_schedule(&bnx2x_fcoe(bp, napi));
5699 /* Handle EQ completions */
5701 bnx2x_ack_sb(bp, bp->igu_dsb_id, USTORM_ID,
5702 le16_to_cpu(bp->def_idx), IGU_INT_NOP, 1);
5704 status &= ~BNX2X_DEF_SB_IDX;
5707 /* if status is non zero then perhaps something went wrong */
5708 if (unlikely(status))
5710 "got an unknown interrupt! (status 0x%x)\n", status);
5712 /* ack status block only if something was actually handled */
5713 bnx2x_ack_sb(bp, bp->igu_dsb_id, ATTENTION_ID,
5714 le16_to_cpu(bp->def_att_idx), IGU_INT_ENABLE, 1);
5717 /* afex - poll to check if VIFSET_ACK should be sent to MFW */
5718 if (test_and_clear_bit(BNX2X_AFEX_PENDING_VIFSET_MCP_ACK,
5720 bnx2x_link_report(bp);
5721 bnx2x_fw_command(bp, DRV_MSG_CODE_AFEX_VIFSET_ACK, 0);
5725 irqreturn_t bnx2x_msix_sp_int(int irq, void *dev_instance)
5727 struct net_device *dev = dev_instance;
5728 struct bnx2x *bp = netdev_priv(dev);
5730 bnx2x_ack_sb(bp, bp->igu_dsb_id, USTORM_ID, 0,
5731 IGU_INT_DISABLE, 0);
5733 #ifdef BNX2X_STOP_ON_ERROR
5734 if (unlikely(bp->panic))
5738 if (CNIC_LOADED(bp)) {
5739 struct cnic_ops *c_ops;
5742 c_ops = rcu_dereference(bp->cnic_ops);
5744 c_ops->cnic_handler(bp->cnic_data, NULL);
5748 /* schedule sp task to perform default status block work, ack
5749 * attentions and enable interrupts.
5751 bnx2x_schedule_sp_task(bp);
5756 /* end of slow path */
5758 void bnx2x_drv_pulse(struct bnx2x *bp)
5760 SHMEM_WR(bp, func_mb[BP_FW_MB_IDX(bp)].drv_pulse_mb,
5761 bp->fw_drv_pulse_wr_seq);
5764 static void bnx2x_timer(unsigned long data)
5766 struct bnx2x *bp = (struct bnx2x *) data;
5768 if (!netif_running(bp->dev))
5773 int mb_idx = BP_FW_MB_IDX(bp);
5777 ++bp->fw_drv_pulse_wr_seq;
5778 bp->fw_drv_pulse_wr_seq &= DRV_PULSE_SEQ_MASK;
5779 drv_pulse = bp->fw_drv_pulse_wr_seq;
5780 bnx2x_drv_pulse(bp);
5782 mcp_pulse = (SHMEM_RD(bp, func_mb[mb_idx].mcp_pulse_mb) &
5783 MCP_PULSE_SEQ_MASK);
5784 /* The delta between driver pulse and mcp response
5785 * should not get too big. If the MFW is more than 5 pulses
5786 * behind, we should worry about it enough to generate an error
5789 if (((drv_pulse - mcp_pulse) & MCP_PULSE_SEQ_MASK) > 5)
5790 BNX2X_ERR("MFW seems hanged: drv_pulse (0x%x) != mcp_pulse (0x%x)\n",
5791 drv_pulse, mcp_pulse);
5794 if (bp->state == BNX2X_STATE_OPEN)
5795 bnx2x_stats_handle(bp, STATS_EVENT_UPDATE);
5797 /* sample pf vf bulletin board for new posts from pf */
5799 bnx2x_timer_sriov(bp);
5801 mod_timer(&bp->timer, jiffies + bp->current_interval);
5804 /* end of Statistics */
5809 * nic init service functions
5812 static void bnx2x_fill(struct bnx2x *bp, u32 addr, int fill, u32 len)
5815 if (!(len%4) && !(addr%4))
5816 for (i = 0; i < len; i += 4)
5817 REG_WR(bp, addr + i, fill);
5819 for (i = 0; i < len; i++)
5820 REG_WR8(bp, addr + i, fill);
5823 /* helper: writes FP SP data to FW - data_size in dwords */
5824 static void bnx2x_wr_fp_sb_data(struct bnx2x *bp,
5830 for (index = 0; index < data_size; index++)
5831 REG_WR(bp, BAR_CSTRORM_INTMEM +
5832 CSTORM_STATUS_BLOCK_DATA_OFFSET(fw_sb_id) +
5834 *(sb_data_p + index));
5837 static void bnx2x_zero_fp_sb(struct bnx2x *bp, int fw_sb_id)
5841 struct hc_status_block_data_e2 sb_data_e2;
5842 struct hc_status_block_data_e1x sb_data_e1x;
5844 /* disable the function first */
5845 if (!CHIP_IS_E1x(bp)) {
5846 memset(&sb_data_e2, 0, sizeof(struct hc_status_block_data_e2));
5847 sb_data_e2.common.state = SB_DISABLED;
5848 sb_data_e2.common.p_func.vf_valid = false;
5849 sb_data_p = (u32 *)&sb_data_e2;
5850 data_size = sizeof(struct hc_status_block_data_e2)/sizeof(u32);
5852 memset(&sb_data_e1x, 0,
5853 sizeof(struct hc_status_block_data_e1x));
5854 sb_data_e1x.common.state = SB_DISABLED;
5855 sb_data_e1x.common.p_func.vf_valid = false;
5856 sb_data_p = (u32 *)&sb_data_e1x;
5857 data_size = sizeof(struct hc_status_block_data_e1x)/sizeof(u32);
5859 bnx2x_wr_fp_sb_data(bp, fw_sb_id, sb_data_p, data_size);
5861 bnx2x_fill(bp, BAR_CSTRORM_INTMEM +
5862 CSTORM_STATUS_BLOCK_OFFSET(fw_sb_id), 0,
5863 CSTORM_STATUS_BLOCK_SIZE);
5864 bnx2x_fill(bp, BAR_CSTRORM_INTMEM +
5865 CSTORM_SYNC_BLOCK_OFFSET(fw_sb_id), 0,
5866 CSTORM_SYNC_BLOCK_SIZE);
5869 /* helper: writes SP SB data to FW */
5870 static void bnx2x_wr_sp_sb_data(struct bnx2x *bp,
5871 struct hc_sp_status_block_data *sp_sb_data)
5873 int func = BP_FUNC(bp);
5875 for (i = 0; i < sizeof(struct hc_sp_status_block_data)/sizeof(u32); i++)
5876 REG_WR(bp, BAR_CSTRORM_INTMEM +
5877 CSTORM_SP_STATUS_BLOCK_DATA_OFFSET(func) +
5879 *((u32 *)sp_sb_data + i));
5882 static void bnx2x_zero_sp_sb(struct bnx2x *bp)
5884 int func = BP_FUNC(bp);
5885 struct hc_sp_status_block_data sp_sb_data;
5886 memset(&sp_sb_data, 0, sizeof(struct hc_sp_status_block_data));
5888 sp_sb_data.state = SB_DISABLED;
5889 sp_sb_data.p_func.vf_valid = false;
5891 bnx2x_wr_sp_sb_data(bp, &sp_sb_data);
5893 bnx2x_fill(bp, BAR_CSTRORM_INTMEM +
5894 CSTORM_SP_STATUS_BLOCK_OFFSET(func), 0,
5895 CSTORM_SP_STATUS_BLOCK_SIZE);
5896 bnx2x_fill(bp, BAR_CSTRORM_INTMEM +
5897 CSTORM_SP_SYNC_BLOCK_OFFSET(func), 0,
5898 CSTORM_SP_SYNC_BLOCK_SIZE);
5901 static void bnx2x_setup_ndsb_state_machine(struct hc_status_block_sm *hc_sm,
5902 int igu_sb_id, int igu_seg_id)
5904 hc_sm->igu_sb_id = igu_sb_id;
5905 hc_sm->igu_seg_id = igu_seg_id;
5906 hc_sm->timer_value = 0xFF;
5907 hc_sm->time_to_expire = 0xFFFFFFFF;
5910 /* allocates state machine ids. */
5911 static void bnx2x_map_sb_state_machines(struct hc_index_data *index_data)
5913 /* zero out state machine indices */
5915 index_data[HC_INDEX_ETH_RX_CQ_CONS].flags &= ~HC_INDEX_DATA_SM_ID;
5918 index_data[HC_INDEX_OOO_TX_CQ_CONS].flags &= ~HC_INDEX_DATA_SM_ID;
5919 index_data[HC_INDEX_ETH_TX_CQ_CONS_COS0].flags &= ~HC_INDEX_DATA_SM_ID;
5920 index_data[HC_INDEX_ETH_TX_CQ_CONS_COS1].flags &= ~HC_INDEX_DATA_SM_ID;
5921 index_data[HC_INDEX_ETH_TX_CQ_CONS_COS2].flags &= ~HC_INDEX_DATA_SM_ID;
5925 index_data[HC_INDEX_ETH_RX_CQ_CONS].flags |=
5926 SM_RX_ID << HC_INDEX_DATA_SM_ID_SHIFT;
5929 index_data[HC_INDEX_OOO_TX_CQ_CONS].flags |=
5930 SM_TX_ID << HC_INDEX_DATA_SM_ID_SHIFT;
5931 index_data[HC_INDEX_ETH_TX_CQ_CONS_COS0].flags |=
5932 SM_TX_ID << HC_INDEX_DATA_SM_ID_SHIFT;
5933 index_data[HC_INDEX_ETH_TX_CQ_CONS_COS1].flags |=
5934 SM_TX_ID << HC_INDEX_DATA_SM_ID_SHIFT;
5935 index_data[HC_INDEX_ETH_TX_CQ_CONS_COS2].flags |=
5936 SM_TX_ID << HC_INDEX_DATA_SM_ID_SHIFT;
5939 void bnx2x_init_sb(struct bnx2x *bp, dma_addr_t mapping, int vfid,
5940 u8 vf_valid, int fw_sb_id, int igu_sb_id)
5944 struct hc_status_block_data_e2 sb_data_e2;
5945 struct hc_status_block_data_e1x sb_data_e1x;
5946 struct hc_status_block_sm *hc_sm_p;
5950 if (CHIP_INT_MODE_IS_BC(bp))
5951 igu_seg_id = HC_SEG_ACCESS_NORM;
5953 igu_seg_id = IGU_SEG_ACCESS_NORM;
5955 bnx2x_zero_fp_sb(bp, fw_sb_id);
5957 if (!CHIP_IS_E1x(bp)) {
5958 memset(&sb_data_e2, 0, sizeof(struct hc_status_block_data_e2));
5959 sb_data_e2.common.state = SB_ENABLED;
5960 sb_data_e2.common.p_func.pf_id = BP_FUNC(bp);
5961 sb_data_e2.common.p_func.vf_id = vfid;
5962 sb_data_e2.common.p_func.vf_valid = vf_valid;
5963 sb_data_e2.common.p_func.vnic_id = BP_VN(bp);
5964 sb_data_e2.common.same_igu_sb_1b = true;
5965 sb_data_e2.common.host_sb_addr.hi = U64_HI(mapping);
5966 sb_data_e2.common.host_sb_addr.lo = U64_LO(mapping);
5967 hc_sm_p = sb_data_e2.common.state_machine;
5968 sb_data_p = (u32 *)&sb_data_e2;
5969 data_size = sizeof(struct hc_status_block_data_e2)/sizeof(u32);
5970 bnx2x_map_sb_state_machines(sb_data_e2.index_data);
5972 memset(&sb_data_e1x, 0,
5973 sizeof(struct hc_status_block_data_e1x));
5974 sb_data_e1x.common.state = SB_ENABLED;
5975 sb_data_e1x.common.p_func.pf_id = BP_FUNC(bp);
5976 sb_data_e1x.common.p_func.vf_id = 0xff;
5977 sb_data_e1x.common.p_func.vf_valid = false;
5978 sb_data_e1x.common.p_func.vnic_id = BP_VN(bp);
5979 sb_data_e1x.common.same_igu_sb_1b = true;
5980 sb_data_e1x.common.host_sb_addr.hi = U64_HI(mapping);
5981 sb_data_e1x.common.host_sb_addr.lo = U64_LO(mapping);
5982 hc_sm_p = sb_data_e1x.common.state_machine;
5983 sb_data_p = (u32 *)&sb_data_e1x;
5984 data_size = sizeof(struct hc_status_block_data_e1x)/sizeof(u32);
5985 bnx2x_map_sb_state_machines(sb_data_e1x.index_data);
5988 bnx2x_setup_ndsb_state_machine(&hc_sm_p[SM_RX_ID],
5989 igu_sb_id, igu_seg_id);
5990 bnx2x_setup_ndsb_state_machine(&hc_sm_p[SM_TX_ID],
5991 igu_sb_id, igu_seg_id);
5993 DP(NETIF_MSG_IFUP, "Init FW SB %d\n", fw_sb_id);
5995 /* write indices to HW - PCI guarantees endianity of regpairs */
5996 bnx2x_wr_fp_sb_data(bp, fw_sb_id, sb_data_p, data_size);
5999 static void bnx2x_update_coalesce_sb(struct bnx2x *bp, u8 fw_sb_id,
6000 u16 tx_usec, u16 rx_usec)
6002 bnx2x_update_coalesce_sb_index(bp, fw_sb_id, HC_INDEX_ETH_RX_CQ_CONS,
6004 bnx2x_update_coalesce_sb_index(bp, fw_sb_id,
6005 HC_INDEX_ETH_TX_CQ_CONS_COS0, false,
6007 bnx2x_update_coalesce_sb_index(bp, fw_sb_id,
6008 HC_INDEX_ETH_TX_CQ_CONS_COS1, false,
6010 bnx2x_update_coalesce_sb_index(bp, fw_sb_id,
6011 HC_INDEX_ETH_TX_CQ_CONS_COS2, false,
6015 static void bnx2x_init_def_sb(struct bnx2x *bp)
6017 struct host_sp_status_block *def_sb = bp->def_status_blk;
6018 dma_addr_t mapping = bp->def_status_blk_mapping;
6019 int igu_sp_sb_index;
6021 int port = BP_PORT(bp);
6022 int func = BP_FUNC(bp);
6023 int reg_offset, reg_offset_en5;
6026 struct hc_sp_status_block_data sp_sb_data;
6027 memset(&sp_sb_data, 0, sizeof(struct hc_sp_status_block_data));
6029 if (CHIP_INT_MODE_IS_BC(bp)) {
6030 igu_sp_sb_index = DEF_SB_IGU_ID;
6031 igu_seg_id = HC_SEG_ACCESS_DEF;
6033 igu_sp_sb_index = bp->igu_dsb_id;
6034 igu_seg_id = IGU_SEG_ACCESS_DEF;
6038 section = ((u64)mapping) + offsetof(struct host_sp_status_block,
6039 atten_status_block);
6040 def_sb->atten_status_block.status_block_id = igu_sp_sb_index;
6044 reg_offset = (port ? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_0 :
6045 MISC_REG_AEU_ENABLE1_FUNC_0_OUT_0);
6046 reg_offset_en5 = (port ? MISC_REG_AEU_ENABLE5_FUNC_1_OUT_0 :
6047 MISC_REG_AEU_ENABLE5_FUNC_0_OUT_0);
6048 for (index = 0; index < MAX_DYNAMIC_ATTN_GRPS; index++) {
6050 /* take care of sig[0]..sig[4] */
6051 for (sindex = 0; sindex < 4; sindex++)
6052 bp->attn_group[index].sig[sindex] =
6053 REG_RD(bp, reg_offset + sindex*0x4 + 0x10*index);
6055 if (!CHIP_IS_E1x(bp))
6057 * enable5 is separate from the rest of the registers,
6058 * and therefore the address skip is 4
6059 * and not 16 between the different groups
6061 bp->attn_group[index].sig[4] = REG_RD(bp,
6062 reg_offset_en5 + 0x4*index);
6064 bp->attn_group[index].sig[4] = 0;
6067 if (bp->common.int_block == INT_BLOCK_HC) {
6068 reg_offset = (port ? HC_REG_ATTN_MSG1_ADDR_L :
6069 HC_REG_ATTN_MSG0_ADDR_L);
6071 REG_WR(bp, reg_offset, U64_LO(section));
6072 REG_WR(bp, reg_offset + 4, U64_HI(section));
6073 } else if (!CHIP_IS_E1x(bp)) {
6074 REG_WR(bp, IGU_REG_ATTN_MSG_ADDR_L, U64_LO(section));
6075 REG_WR(bp, IGU_REG_ATTN_MSG_ADDR_H, U64_HI(section));
6078 section = ((u64)mapping) + offsetof(struct host_sp_status_block,
6081 bnx2x_zero_sp_sb(bp);
6083 /* PCI guarantees endianity of regpairs */
6084 sp_sb_data.state = SB_ENABLED;
6085 sp_sb_data.host_sb_addr.lo = U64_LO(section);
6086 sp_sb_data.host_sb_addr.hi = U64_HI(section);
6087 sp_sb_data.igu_sb_id = igu_sp_sb_index;
6088 sp_sb_data.igu_seg_id = igu_seg_id;
6089 sp_sb_data.p_func.pf_id = func;
6090 sp_sb_data.p_func.vnic_id = BP_VN(bp);
6091 sp_sb_data.p_func.vf_id = 0xff;
6093 bnx2x_wr_sp_sb_data(bp, &sp_sb_data);
6095 bnx2x_ack_sb(bp, bp->igu_dsb_id, USTORM_ID, 0, IGU_INT_ENABLE, 0);
6098 void bnx2x_update_coalesce(struct bnx2x *bp)
6102 for_each_eth_queue(bp, i)
6103 bnx2x_update_coalesce_sb(bp, bp->fp[i].fw_sb_id,
6104 bp->tx_ticks, bp->rx_ticks);
6107 static void bnx2x_init_sp_ring(struct bnx2x *bp)
6109 spin_lock_init(&bp->spq_lock);
6110 atomic_set(&bp->cq_spq_left, MAX_SPQ_PENDING);
6112 bp->spq_prod_idx = 0;
6113 bp->dsb_sp_prod = BNX2X_SP_DSB_INDEX;
6114 bp->spq_prod_bd = bp->spq;
6115 bp->spq_last_bd = bp->spq_prod_bd + MAX_SP_DESC_CNT;
6118 static void bnx2x_init_eq_ring(struct bnx2x *bp)
6121 for (i = 1; i <= NUM_EQ_PAGES; i++) {
6122 union event_ring_elem *elem =
6123 &bp->eq_ring[EQ_DESC_CNT_PAGE * i - 1];
6125 elem->next_page.addr.hi =
6126 cpu_to_le32(U64_HI(bp->eq_mapping +
6127 BCM_PAGE_SIZE * (i % NUM_EQ_PAGES)));
6128 elem->next_page.addr.lo =
6129 cpu_to_le32(U64_LO(bp->eq_mapping +
6130 BCM_PAGE_SIZE*(i % NUM_EQ_PAGES)));
6133 bp->eq_prod = NUM_EQ_DESC;
6134 bp->eq_cons_sb = BNX2X_EQ_INDEX;
6135 /* we want a warning message before it gets wrought... */
6136 atomic_set(&bp->eq_spq_left,
6137 min_t(int, MAX_SP_DESC_CNT - MAX_SPQ_PENDING, NUM_EQ_DESC) - 1);
6140 /* called with netif_addr_lock_bh() */
6141 static int bnx2x_set_q_rx_mode(struct bnx2x *bp, u8 cl_id,
6142 unsigned long rx_mode_flags,
6143 unsigned long rx_accept_flags,
6144 unsigned long tx_accept_flags,
6145 unsigned long ramrod_flags)
6147 struct bnx2x_rx_mode_ramrod_params ramrod_param;
6150 memset(&ramrod_param, 0, sizeof(ramrod_param));
6152 /* Prepare ramrod parameters */
6153 ramrod_param.cid = 0;
6154 ramrod_param.cl_id = cl_id;
6155 ramrod_param.rx_mode_obj = &bp->rx_mode_obj;
6156 ramrod_param.func_id = BP_FUNC(bp);
6158 ramrod_param.pstate = &bp->sp_state;
6159 ramrod_param.state = BNX2X_FILTER_RX_MODE_PENDING;
6161 ramrod_param.rdata = bnx2x_sp(bp, rx_mode_rdata);
6162 ramrod_param.rdata_mapping = bnx2x_sp_mapping(bp, rx_mode_rdata);
6164 set_bit(BNX2X_FILTER_RX_MODE_PENDING, &bp->sp_state);
6166 ramrod_param.ramrod_flags = ramrod_flags;
6167 ramrod_param.rx_mode_flags = rx_mode_flags;
6169 ramrod_param.rx_accept_flags = rx_accept_flags;
6170 ramrod_param.tx_accept_flags = tx_accept_flags;
6172 rc = bnx2x_config_rx_mode(bp, &ramrod_param);
6174 BNX2X_ERR("Set rx_mode %d failed\n", bp->rx_mode);
6181 static int bnx2x_fill_accept_flags(struct bnx2x *bp, u32 rx_mode,
6182 unsigned long *rx_accept_flags,
6183 unsigned long *tx_accept_flags)
6185 /* Clear the flags first */
6186 *rx_accept_flags = 0;
6187 *tx_accept_flags = 0;
6190 case BNX2X_RX_MODE_NONE:
6192 * 'drop all' supersedes any accept flags that may have been
6193 * passed to the function.
6196 case BNX2X_RX_MODE_NORMAL:
6197 __set_bit(BNX2X_ACCEPT_UNICAST, rx_accept_flags);
6198 __set_bit(BNX2X_ACCEPT_MULTICAST, rx_accept_flags);
6199 __set_bit(BNX2X_ACCEPT_BROADCAST, rx_accept_flags);
6201 /* internal switching mode */
6202 __set_bit(BNX2X_ACCEPT_UNICAST, tx_accept_flags);
6203 __set_bit(BNX2X_ACCEPT_MULTICAST, tx_accept_flags);
6204 __set_bit(BNX2X_ACCEPT_BROADCAST, tx_accept_flags);
6206 if (bp->accept_any_vlan) {
6207 __set_bit(BNX2X_ACCEPT_ANY_VLAN, rx_accept_flags);
6208 __set_bit(BNX2X_ACCEPT_ANY_VLAN, tx_accept_flags);
6212 case BNX2X_RX_MODE_ALLMULTI:
6213 __set_bit(BNX2X_ACCEPT_UNICAST, rx_accept_flags);
6214 __set_bit(BNX2X_ACCEPT_ALL_MULTICAST, rx_accept_flags);
6215 __set_bit(BNX2X_ACCEPT_BROADCAST, rx_accept_flags);
6217 /* internal switching mode */
6218 __set_bit(BNX2X_ACCEPT_UNICAST, tx_accept_flags);
6219 __set_bit(BNX2X_ACCEPT_ALL_MULTICAST, tx_accept_flags);
6220 __set_bit(BNX2X_ACCEPT_BROADCAST, tx_accept_flags);
6222 if (bp->accept_any_vlan) {
6223 __set_bit(BNX2X_ACCEPT_ANY_VLAN, rx_accept_flags);
6224 __set_bit(BNX2X_ACCEPT_ANY_VLAN, tx_accept_flags);
6228 case BNX2X_RX_MODE_PROMISC:
6229 /* According to definition of SI mode, iface in promisc mode
6230 * should receive matched and unmatched (in resolution of port)
6233 __set_bit(BNX2X_ACCEPT_UNMATCHED, rx_accept_flags);
6234 __set_bit(BNX2X_ACCEPT_UNICAST, rx_accept_flags);
6235 __set_bit(BNX2X_ACCEPT_ALL_MULTICAST, rx_accept_flags);
6236 __set_bit(BNX2X_ACCEPT_BROADCAST, rx_accept_flags);
6238 /* internal switching mode */
6239 __set_bit(BNX2X_ACCEPT_ALL_MULTICAST, tx_accept_flags);
6240 __set_bit(BNX2X_ACCEPT_BROADCAST, tx_accept_flags);
6243 __set_bit(BNX2X_ACCEPT_ALL_UNICAST, tx_accept_flags);
6245 __set_bit(BNX2X_ACCEPT_UNICAST, tx_accept_flags);
6247 __set_bit(BNX2X_ACCEPT_ANY_VLAN, rx_accept_flags);
6248 __set_bit(BNX2X_ACCEPT_ANY_VLAN, tx_accept_flags);
6252 BNX2X_ERR("Unknown rx_mode: %d\n", rx_mode);
6259 /* called with netif_addr_lock_bh() */
6260 static int bnx2x_set_storm_rx_mode(struct bnx2x *bp)
6262 unsigned long rx_mode_flags = 0, ramrod_flags = 0;
6263 unsigned long rx_accept_flags = 0, tx_accept_flags = 0;
6267 /* Configure rx_mode of FCoE Queue */
6268 __set_bit(BNX2X_RX_MODE_FCOE_ETH, &rx_mode_flags);
6270 rc = bnx2x_fill_accept_flags(bp, bp->rx_mode, &rx_accept_flags,
6275 __set_bit(RAMROD_RX, &ramrod_flags);
6276 __set_bit(RAMROD_TX, &ramrod_flags);
6278 return bnx2x_set_q_rx_mode(bp, bp->fp->cl_id, rx_mode_flags,
6279 rx_accept_flags, tx_accept_flags,
6283 static void bnx2x_init_internal_common(struct bnx2x *bp)
6287 /* Zero this manually as its initialization is
6288 currently missing in the initTool */
6289 for (i = 0; i < (USTORM_AGG_DATA_SIZE >> 2); i++)
6290 REG_WR(bp, BAR_USTRORM_INTMEM +
6291 USTORM_AGG_DATA_OFFSET + i * 4, 0);
6292 if (!CHIP_IS_E1x(bp)) {
6293 REG_WR8(bp, BAR_CSTRORM_INTMEM + CSTORM_IGU_MODE_OFFSET,
6294 CHIP_INT_MODE_IS_BC(bp) ?
6295 HC_IGU_BC_MODE : HC_IGU_NBC_MODE);
6299 static void bnx2x_init_internal(struct bnx2x *bp, u32 load_code)
6301 switch (load_code) {
6302 case FW_MSG_CODE_DRV_LOAD_COMMON:
6303 case FW_MSG_CODE_DRV_LOAD_COMMON_CHIP:
6304 bnx2x_init_internal_common(bp);
6307 case FW_MSG_CODE_DRV_LOAD_PORT:
6311 case FW_MSG_CODE_DRV_LOAD_FUNCTION:
6312 /* internal memory per function is
6313 initialized inside bnx2x_pf_init */
6317 BNX2X_ERR("Unknown load_code (0x%x) from MCP\n", load_code);
6322 static inline u8 bnx2x_fp_igu_sb_id(struct bnx2x_fastpath *fp)
6324 return fp->bp->igu_base_sb + fp->index + CNIC_SUPPORT(fp->bp);
6327 static inline u8 bnx2x_fp_fw_sb_id(struct bnx2x_fastpath *fp)
6329 return fp->bp->base_fw_ndsb + fp->index + CNIC_SUPPORT(fp->bp);
6332 static u8 bnx2x_fp_cl_id(struct bnx2x_fastpath *fp)
6334 if (CHIP_IS_E1x(fp->bp))
6335 return BP_L_ID(fp->bp) + fp->index;
6336 else /* We want Client ID to be the same as IGU SB ID for 57712 */
6337 return bnx2x_fp_igu_sb_id(fp);
6340 static void bnx2x_init_eth_fp(struct bnx2x *bp, int fp_idx)
6342 struct bnx2x_fastpath *fp = &bp->fp[fp_idx];
6344 unsigned long q_type = 0;
6345 u32 cids[BNX2X_MULTI_TX_COS] = { 0 };
6346 fp->rx_queue = fp_idx;
6348 fp->cl_id = bnx2x_fp_cl_id(fp);
6349 fp->fw_sb_id = bnx2x_fp_fw_sb_id(fp);
6350 fp->igu_sb_id = bnx2x_fp_igu_sb_id(fp);
6351 /* qZone id equals to FW (per path) client id */
6352 fp->cl_qzone_id = bnx2x_fp_qzone_id(fp);
6355 fp->ustorm_rx_prods_offset = bnx2x_rx_ustorm_prods_offset(fp);
6357 /* Setup SB indices */
6358 fp->rx_cons_sb = BNX2X_RX_SB_INDEX;
6360 /* Configure Queue State object */
6361 __set_bit(BNX2X_Q_TYPE_HAS_RX, &q_type);
6362 __set_bit(BNX2X_Q_TYPE_HAS_TX, &q_type);
6364 BUG_ON(fp->max_cos > BNX2X_MULTI_TX_COS);
6367 for_each_cos_in_tx_queue(fp, cos) {
6368 bnx2x_init_txdata(bp, fp->txdata_ptr[cos],
6369 CID_COS_TO_TX_ONLY_CID(fp->cid, cos, bp),
6370 FP_COS_TO_TXQ(fp, cos, bp),
6371 BNX2X_TX_SB_INDEX_BASE + cos, fp);
6372 cids[cos] = fp->txdata_ptr[cos]->cid;
6375 /* nothing more for vf to do here */
6379 bnx2x_init_sb(bp, fp->status_blk_mapping, BNX2X_VF_ID_INVALID, false,
6380 fp->fw_sb_id, fp->igu_sb_id);
6381 bnx2x_update_fpsb_idx(fp);
6382 bnx2x_init_queue_obj(bp, &bnx2x_sp_obj(bp, fp).q_obj, fp->cl_id, cids,
6383 fp->max_cos, BP_FUNC(bp), bnx2x_sp(bp, q_rdata),
6384 bnx2x_sp_mapping(bp, q_rdata), q_type);
6387 * Configure classification DBs: Always enable Tx switching
6389 bnx2x_init_vlan_mac_fp_objs(fp, BNX2X_OBJ_TYPE_RX_TX);
6392 "queue[%d]: bnx2x_init_sb(%p,%p) cl_id %d fw_sb %d igu_sb %d\n",
6393 fp_idx, bp, fp->status_blk.e2_sb, fp->cl_id, fp->fw_sb_id,
6397 static void bnx2x_init_tx_ring_one(struct bnx2x_fp_txdata *txdata)
6401 for (i = 1; i <= NUM_TX_RINGS; i++) {
6402 struct eth_tx_next_bd *tx_next_bd =
6403 &txdata->tx_desc_ring[TX_DESC_CNT * i - 1].next_bd;
6405 tx_next_bd->addr_hi =
6406 cpu_to_le32(U64_HI(txdata->tx_desc_mapping +
6407 BCM_PAGE_SIZE*(i % NUM_TX_RINGS)));
6408 tx_next_bd->addr_lo =
6409 cpu_to_le32(U64_LO(txdata->tx_desc_mapping +
6410 BCM_PAGE_SIZE*(i % NUM_TX_RINGS)));
6413 *txdata->tx_cons_sb = cpu_to_le16(0);
6415 SET_FLAG(txdata->tx_db.data.header.header, DOORBELL_HDR_DB_TYPE, 1);
6416 txdata->tx_db.data.zero_fill1 = 0;
6417 txdata->tx_db.data.prod = 0;
6419 txdata->tx_pkt_prod = 0;
6420 txdata->tx_pkt_cons = 0;
6421 txdata->tx_bd_prod = 0;
6422 txdata->tx_bd_cons = 0;
6426 static void bnx2x_init_tx_rings_cnic(struct bnx2x *bp)
6430 for_each_tx_queue_cnic(bp, i)
6431 bnx2x_init_tx_ring_one(bp->fp[i].txdata_ptr[0]);
6434 static void bnx2x_init_tx_rings(struct bnx2x *bp)
6439 for_each_eth_queue(bp, i)
6440 for_each_cos_in_tx_queue(&bp->fp[i], cos)
6441 bnx2x_init_tx_ring_one(bp->fp[i].txdata_ptr[cos]);
6444 static void bnx2x_init_fcoe_fp(struct bnx2x *bp)
6446 struct bnx2x_fastpath *fp = bnx2x_fcoe_fp(bp);
6447 unsigned long q_type = 0;
6449 bnx2x_fcoe(bp, rx_queue) = BNX2X_NUM_ETH_QUEUES(bp);
6450 bnx2x_fcoe(bp, cl_id) = bnx2x_cnic_eth_cl_id(bp,
6451 BNX2X_FCOE_ETH_CL_ID_IDX);
6452 bnx2x_fcoe(bp, cid) = BNX2X_FCOE_ETH_CID(bp);
6453 bnx2x_fcoe(bp, fw_sb_id) = DEF_SB_ID;
6454 bnx2x_fcoe(bp, igu_sb_id) = bp->igu_dsb_id;
6455 bnx2x_fcoe(bp, rx_cons_sb) = BNX2X_FCOE_L2_RX_INDEX;
6456 bnx2x_init_txdata(bp, bnx2x_fcoe(bp, txdata_ptr[0]),
6457 fp->cid, FCOE_TXQ_IDX(bp), BNX2X_FCOE_L2_TX_INDEX,
6460 DP(NETIF_MSG_IFUP, "created fcoe tx data (fp index %d)\n", fp->index);
6462 /* qZone id equals to FW (per path) client id */
6463 bnx2x_fcoe(bp, cl_qzone_id) = bnx2x_fp_qzone_id(fp);
6465 bnx2x_fcoe(bp, ustorm_rx_prods_offset) =
6466 bnx2x_rx_ustorm_prods_offset(fp);
6468 /* Configure Queue State object */
6469 __set_bit(BNX2X_Q_TYPE_HAS_RX, &q_type);
6470 __set_bit(BNX2X_Q_TYPE_HAS_TX, &q_type);
6472 /* No multi-CoS for FCoE L2 client */
6473 BUG_ON(fp->max_cos != 1);
6475 bnx2x_init_queue_obj(bp, &bnx2x_sp_obj(bp, fp).q_obj, fp->cl_id,
6476 &fp->cid, 1, BP_FUNC(bp), bnx2x_sp(bp, q_rdata),
6477 bnx2x_sp_mapping(bp, q_rdata), q_type);
6480 "queue[%d]: bnx2x_init_sb(%p,%p) cl_id %d fw_sb %d igu_sb %d\n",
6481 fp->index, bp, fp->status_blk.e2_sb, fp->cl_id, fp->fw_sb_id,
6485 void bnx2x_nic_init_cnic(struct bnx2x *bp)
6488 bnx2x_init_fcoe_fp(bp);
6490 bnx2x_init_sb(bp, bp->cnic_sb_mapping,
6491 BNX2X_VF_ID_INVALID, false,
6492 bnx2x_cnic_fw_sb_id(bp), bnx2x_cnic_igu_sb_id(bp));
6494 /* ensure status block indices were read */
6496 bnx2x_init_rx_rings_cnic(bp);
6497 bnx2x_init_tx_rings_cnic(bp);
6504 void bnx2x_pre_irq_nic_init(struct bnx2x *bp)
6508 /* Setup NIC internals and enable interrupts */
6509 for_each_eth_queue(bp, i)
6510 bnx2x_init_eth_fp(bp, i);
6512 /* ensure status block indices were read */
6514 bnx2x_init_rx_rings(bp);
6515 bnx2x_init_tx_rings(bp);
6518 /* Initialize MOD_ABS interrupts */
6519 bnx2x_init_mod_abs_int(bp, &bp->link_vars, bp->common.chip_id,
6520 bp->common.shmem_base,
6521 bp->common.shmem2_base, BP_PORT(bp));
6523 /* initialize the default status block and sp ring */
6524 bnx2x_init_def_sb(bp);
6525 bnx2x_update_dsb_idx(bp);
6526 bnx2x_init_sp_ring(bp);
6528 bnx2x_memset_stats(bp);
6532 void bnx2x_post_irq_nic_init(struct bnx2x *bp, u32 load_code)
6534 bnx2x_init_eq_ring(bp);
6535 bnx2x_init_internal(bp, load_code);
6537 bnx2x_stats_init(bp);
6539 /* flush all before enabling interrupts */
6543 bnx2x_int_enable(bp);
6545 /* Check for SPIO5 */
6546 bnx2x_attn_int_deasserted0(bp,
6547 REG_RD(bp, MISC_REG_AEU_AFTER_INVERT_1_FUNC_0 + BP_PORT(bp)*4) &
6548 AEU_INPUTS_ATTN_BITS_SPIO5);
6551 /* gzip service functions */
6552 static int bnx2x_gunzip_init(struct bnx2x *bp)
6554 bp->gunzip_buf = dma_alloc_coherent(&bp->pdev->dev, FW_BUF_SIZE,
6555 &bp->gunzip_mapping, GFP_KERNEL);
6556 if (bp->gunzip_buf == NULL)
6559 bp->strm = kmalloc(sizeof(*bp->strm), GFP_KERNEL);
6560 if (bp->strm == NULL)
6563 bp->strm->workspace = vmalloc(zlib_inflate_workspacesize());
6564 if (bp->strm->workspace == NULL)
6574 dma_free_coherent(&bp->pdev->dev, FW_BUF_SIZE, bp->gunzip_buf,
6575 bp->gunzip_mapping);
6576 bp->gunzip_buf = NULL;
6579 BNX2X_ERR("Cannot allocate firmware buffer for un-compression\n");
6583 static void bnx2x_gunzip_end(struct bnx2x *bp)
6586 vfree(bp->strm->workspace);
6591 if (bp->gunzip_buf) {
6592 dma_free_coherent(&bp->pdev->dev, FW_BUF_SIZE, bp->gunzip_buf,
6593 bp->gunzip_mapping);
6594 bp->gunzip_buf = NULL;
6598 static int bnx2x_gunzip(struct bnx2x *bp, const u8 *zbuf, int len)
6602 /* check gzip header */
6603 if ((zbuf[0] != 0x1f) || (zbuf[1] != 0x8b) || (zbuf[2] != Z_DEFLATED)) {
6604 BNX2X_ERR("Bad gzip header\n");
6612 if (zbuf[3] & FNAME)
6613 while ((zbuf[n++] != 0) && (n < len));
6615 bp->strm->next_in = (typeof(bp->strm->next_in))zbuf + n;
6616 bp->strm->avail_in = len - n;
6617 bp->strm->next_out = bp->gunzip_buf;
6618 bp->strm->avail_out = FW_BUF_SIZE;
6620 rc = zlib_inflateInit2(bp->strm, -MAX_WBITS);
6624 rc = zlib_inflate(bp->strm, Z_FINISH);
6625 if ((rc != Z_OK) && (rc != Z_STREAM_END))
6626 netdev_err(bp->dev, "Firmware decompression error: %s\n",
6629 bp->gunzip_outlen = (FW_BUF_SIZE - bp->strm->avail_out);
6630 if (bp->gunzip_outlen & 0x3)
6632 "Firmware decompression error: gunzip_outlen (%d) not aligned\n",
6634 bp->gunzip_outlen >>= 2;
6636 zlib_inflateEnd(bp->strm);
6638 if (rc == Z_STREAM_END)
6644 /* nic load/unload */
6647 * General service functions
6650 /* send a NIG loopback debug packet */
6651 static void bnx2x_lb_pckt(struct bnx2x *bp)
6655 /* Ethernet source and destination addresses */
6656 wb_write[0] = 0x55555555;
6657 wb_write[1] = 0x55555555;
6658 wb_write[2] = 0x20; /* SOP */
6659 REG_WR_DMAE(bp, NIG_REG_DEBUG_PACKET_LB, wb_write, 3);
6661 /* NON-IP protocol */
6662 wb_write[0] = 0x09000000;
6663 wb_write[1] = 0x55555555;
6664 wb_write[2] = 0x10; /* EOP, eop_bvalid = 0 */
6665 REG_WR_DMAE(bp, NIG_REG_DEBUG_PACKET_LB, wb_write, 3);
6668 /* some of the internal memories
6669 * are not directly readable from the driver
6670 * to test them we send debug packets
6672 static int bnx2x_int_mem_test(struct bnx2x *bp)
6678 if (CHIP_REV_IS_FPGA(bp))
6680 else if (CHIP_REV_IS_EMUL(bp))
6685 /* Disable inputs of parser neighbor blocks */
6686 REG_WR(bp, TSDM_REG_ENABLE_IN1, 0x0);
6687 REG_WR(bp, TCM_REG_PRS_IFEN, 0x0);
6688 REG_WR(bp, CFC_REG_DEBUG0, 0x1);
6689 REG_WR(bp, NIG_REG_PRS_REQ_IN_EN, 0x0);
6691 /* Write 0 to parser credits for CFC search request */
6692 REG_WR(bp, PRS_REG_CFC_SEARCH_INITIAL_CREDIT, 0x0);
6694 /* send Ethernet packet */
6697 /* TODO do i reset NIG statistic? */
6698 /* Wait until NIG register shows 1 packet of size 0x10 */
6699 count = 1000 * factor;
6702 bnx2x_read_dmae(bp, NIG_REG_STAT2_BRB_OCTET, 2);
6703 val = *bnx2x_sp(bp, wb_data[0]);
6707 usleep_range(10000, 20000);
6711 BNX2X_ERR("NIG timeout val = 0x%x\n", val);
6715 /* Wait until PRS register shows 1 packet */
6716 count = 1000 * factor;
6718 val = REG_RD(bp, PRS_REG_NUM_OF_PACKETS);
6722 usleep_range(10000, 20000);
6726 BNX2X_ERR("PRS timeout val = 0x%x\n", val);
6730 /* Reset and init BRB, PRS */
6731 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_CLEAR, 0x03);
6733 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_SET, 0x03);
6735 bnx2x_init_block(bp, BLOCK_BRB1, PHASE_COMMON);
6736 bnx2x_init_block(bp, BLOCK_PRS, PHASE_COMMON);
6738 DP(NETIF_MSG_HW, "part2\n");
6740 /* Disable inputs of parser neighbor blocks */
6741 REG_WR(bp, TSDM_REG_ENABLE_IN1, 0x0);
6742 REG_WR(bp, TCM_REG_PRS_IFEN, 0x0);
6743 REG_WR(bp, CFC_REG_DEBUG0, 0x1);
6744 REG_WR(bp, NIG_REG_PRS_REQ_IN_EN, 0x0);
6746 /* Write 0 to parser credits for CFC search request */
6747 REG_WR(bp, PRS_REG_CFC_SEARCH_INITIAL_CREDIT, 0x0);
6749 /* send 10 Ethernet packets */
6750 for (i = 0; i < 10; i++)
6753 /* Wait until NIG register shows 10 + 1
6754 packets of size 11*0x10 = 0xb0 */
6755 count = 1000 * factor;
6758 bnx2x_read_dmae(bp, NIG_REG_STAT2_BRB_OCTET, 2);
6759 val = *bnx2x_sp(bp, wb_data[0]);
6763 usleep_range(10000, 20000);
6767 BNX2X_ERR("NIG timeout val = 0x%x\n", val);
6771 /* Wait until PRS register shows 2 packets */
6772 val = REG_RD(bp, PRS_REG_NUM_OF_PACKETS);
6774 BNX2X_ERR("PRS timeout val = 0x%x\n", val);
6776 /* Write 1 to parser credits for CFC search request */
6777 REG_WR(bp, PRS_REG_CFC_SEARCH_INITIAL_CREDIT, 0x1);
6779 /* Wait until PRS register shows 3 packets */
6780 msleep(10 * factor);
6781 /* Wait until NIG register shows 1 packet of size 0x10 */
6782 val = REG_RD(bp, PRS_REG_NUM_OF_PACKETS);
6784 BNX2X_ERR("PRS timeout val = 0x%x\n", val);
6786 /* clear NIG EOP FIFO */
6787 for (i = 0; i < 11; i++)
6788 REG_RD(bp, NIG_REG_INGRESS_EOP_LB_FIFO);
6789 val = REG_RD(bp, NIG_REG_INGRESS_EOP_LB_EMPTY);
6791 BNX2X_ERR("clear of NIG failed\n");
6795 /* Reset and init BRB, PRS, NIG */
6796 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_CLEAR, 0x03);
6798 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_SET, 0x03);
6800 bnx2x_init_block(bp, BLOCK_BRB1, PHASE_COMMON);
6801 bnx2x_init_block(bp, BLOCK_PRS, PHASE_COMMON);
6802 if (!CNIC_SUPPORT(bp))
6804 REG_WR(bp, PRS_REG_NIC_MODE, 1);
6806 /* Enable inputs of parser neighbor blocks */
6807 REG_WR(bp, TSDM_REG_ENABLE_IN1, 0x7fffffff);
6808 REG_WR(bp, TCM_REG_PRS_IFEN, 0x1);
6809 REG_WR(bp, CFC_REG_DEBUG0, 0x0);
6810 REG_WR(bp, NIG_REG_PRS_REQ_IN_EN, 0x1);
6812 DP(NETIF_MSG_HW, "done\n");
6817 static void bnx2x_enable_blocks_attention(struct bnx2x *bp)
6821 REG_WR(bp, PXP_REG_PXP_INT_MASK_0, 0);
6822 if (!CHIP_IS_E1x(bp))
6823 REG_WR(bp, PXP_REG_PXP_INT_MASK_1, 0x40);
6825 REG_WR(bp, PXP_REG_PXP_INT_MASK_1, 0);
6826 REG_WR(bp, DORQ_REG_DORQ_INT_MASK, 0);
6827 REG_WR(bp, CFC_REG_CFC_INT_MASK, 0);
6829 * mask read length error interrupts in brb for parser
6830 * (parsing unit and 'checksum and crc' unit)
6831 * these errors are legal (PU reads fixed length and CAC can cause
6832 * read length error on truncated packets)
6834 REG_WR(bp, BRB1_REG_BRB1_INT_MASK, 0xFC00);
6835 REG_WR(bp, QM_REG_QM_INT_MASK, 0);
6836 REG_WR(bp, TM_REG_TM_INT_MASK, 0);
6837 REG_WR(bp, XSDM_REG_XSDM_INT_MASK_0, 0);
6838 REG_WR(bp, XSDM_REG_XSDM_INT_MASK_1, 0);
6839 REG_WR(bp, XCM_REG_XCM_INT_MASK, 0);
6840 /* REG_WR(bp, XSEM_REG_XSEM_INT_MASK_0, 0); */
6841 /* REG_WR(bp, XSEM_REG_XSEM_INT_MASK_1, 0); */
6842 REG_WR(bp, USDM_REG_USDM_INT_MASK_0, 0);
6843 REG_WR(bp, USDM_REG_USDM_INT_MASK_1, 0);
6844 REG_WR(bp, UCM_REG_UCM_INT_MASK, 0);
6845 /* REG_WR(bp, USEM_REG_USEM_INT_MASK_0, 0); */
6846 /* REG_WR(bp, USEM_REG_USEM_INT_MASK_1, 0); */
6847 REG_WR(bp, GRCBASE_UPB + PB_REG_PB_INT_MASK, 0);
6848 REG_WR(bp, CSDM_REG_CSDM_INT_MASK_0, 0);
6849 REG_WR(bp, CSDM_REG_CSDM_INT_MASK_1, 0);
6850 REG_WR(bp, CCM_REG_CCM_INT_MASK, 0);
6851 /* REG_WR(bp, CSEM_REG_CSEM_INT_MASK_0, 0); */
6852 /* REG_WR(bp, CSEM_REG_CSEM_INT_MASK_1, 0); */
6854 val = PXP2_PXP2_INT_MASK_0_REG_PGL_CPL_AFT |
6855 PXP2_PXP2_INT_MASK_0_REG_PGL_CPL_OF |
6856 PXP2_PXP2_INT_MASK_0_REG_PGL_PCIE_ATTN;
6857 if (!CHIP_IS_E1x(bp))
6858 val |= PXP2_PXP2_INT_MASK_0_REG_PGL_READ_BLOCKED |
6859 PXP2_PXP2_INT_MASK_0_REG_PGL_WRITE_BLOCKED;
6860 REG_WR(bp, PXP2_REG_PXP2_INT_MASK_0, val);
6862 REG_WR(bp, TSDM_REG_TSDM_INT_MASK_0, 0);
6863 REG_WR(bp, TSDM_REG_TSDM_INT_MASK_1, 0);
6864 REG_WR(bp, TCM_REG_TCM_INT_MASK, 0);
6865 /* REG_WR(bp, TSEM_REG_TSEM_INT_MASK_0, 0); */
6867 if (!CHIP_IS_E1x(bp))
6868 /* enable VFC attentions: bits 11 and 12, bits 31:13 reserved */
6869 REG_WR(bp, TSEM_REG_TSEM_INT_MASK_1, 0x07ff);
6871 REG_WR(bp, CDU_REG_CDU_INT_MASK, 0);
6872 REG_WR(bp, DMAE_REG_DMAE_INT_MASK, 0);
6873 /* REG_WR(bp, MISC_REG_MISC_INT_MASK, 0); */
6874 REG_WR(bp, PBF_REG_PBF_INT_MASK, 0x18); /* bit 3,4 masked */
6877 static void bnx2x_reset_common(struct bnx2x *bp)
6882 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_CLEAR,
6885 if (CHIP_IS_E3(bp)) {
6886 val |= MISC_REGISTERS_RESET_REG_2_MSTAT0;
6887 val |= MISC_REGISTERS_RESET_REG_2_MSTAT1;
6890 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR, val);
6893 static void bnx2x_setup_dmae(struct bnx2x *bp)
6896 spin_lock_init(&bp->dmae_lock);
6899 static void bnx2x_init_pxp(struct bnx2x *bp)
6902 int r_order, w_order;
6904 pcie_capability_read_word(bp->pdev, PCI_EXP_DEVCTL, &devctl);
6905 DP(NETIF_MSG_HW, "read 0x%x from devctl\n", devctl);
6906 w_order = ((devctl & PCI_EXP_DEVCTL_PAYLOAD) >> 5);
6908 r_order = ((devctl & PCI_EXP_DEVCTL_READRQ) >> 12);
6910 DP(NETIF_MSG_HW, "force read order to %d\n", bp->mrrs);
6914 bnx2x_init_pxp_arb(bp, r_order, w_order);
6917 static void bnx2x_setup_fan_failure_detection(struct bnx2x *bp)
6927 val = SHMEM_RD(bp, dev_info.shared_hw_config.config2) &
6928 SHARED_HW_CFG_FAN_FAILURE_MASK;
6930 if (val == SHARED_HW_CFG_FAN_FAILURE_ENABLED)
6934 * The fan failure mechanism is usually related to the PHY type since
6935 * the power consumption of the board is affected by the PHY. Currently,
6936 * fan is required for most designs with SFX7101, BCM8727 and BCM8481.
6938 else if (val == SHARED_HW_CFG_FAN_FAILURE_PHY_TYPE)
6939 for (port = PORT_0; port < PORT_MAX; port++) {
6941 bnx2x_fan_failure_det_req(
6943 bp->common.shmem_base,
6944 bp->common.shmem2_base,
6948 DP(NETIF_MSG_HW, "fan detection setting: %d\n", is_required);
6950 if (is_required == 0)
6953 /* Fan failure is indicated by SPIO 5 */
6954 bnx2x_set_spio(bp, MISC_SPIO_SPIO5, MISC_SPIO_INPUT_HI_Z);
6956 /* set to active low mode */
6957 val = REG_RD(bp, MISC_REG_SPIO_INT);
6958 val |= (MISC_SPIO_SPIO5 << MISC_SPIO_INT_OLD_SET_POS);
6959 REG_WR(bp, MISC_REG_SPIO_INT, val);
6961 /* enable interrupt to signal the IGU */
6962 val = REG_RD(bp, MISC_REG_SPIO_EVENT_EN);
6963 val |= MISC_SPIO_SPIO5;
6964 REG_WR(bp, MISC_REG_SPIO_EVENT_EN, val);
6967 void bnx2x_pf_disable(struct bnx2x *bp)
6969 u32 val = REG_RD(bp, IGU_REG_PF_CONFIGURATION);
6970 val &= ~IGU_PF_CONF_FUNC_EN;
6972 REG_WR(bp, IGU_REG_PF_CONFIGURATION, val);
6973 REG_WR(bp, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, 0);
6974 REG_WR(bp, CFC_REG_WEAK_ENABLE_PF, 0);
6977 static void bnx2x__common_init_phy(struct bnx2x *bp)
6979 u32 shmem_base[2], shmem2_base[2];
6980 /* Avoid common init in case MFW supports LFA */
6981 if (SHMEM2_RD(bp, size) >
6982 (u32)offsetof(struct shmem2_region, lfa_host_addr[BP_PORT(bp)]))
6984 shmem_base[0] = bp->common.shmem_base;
6985 shmem2_base[0] = bp->common.shmem2_base;
6986 if (!CHIP_IS_E1x(bp)) {
6988 SHMEM2_RD(bp, other_shmem_base_addr);
6990 SHMEM2_RD(bp, other_shmem2_base_addr);
6992 bnx2x_acquire_phy_lock(bp);
6993 bnx2x_common_init_phy(bp, shmem_base, shmem2_base,
6994 bp->common.chip_id);
6995 bnx2x_release_phy_lock(bp);
6998 static void bnx2x_config_endianity(struct bnx2x *bp, u32 val)
7000 REG_WR(bp, PXP2_REG_RQ_QM_ENDIAN_M, val);
7001 REG_WR(bp, PXP2_REG_RQ_TM_ENDIAN_M, val);
7002 REG_WR(bp, PXP2_REG_RQ_SRC_ENDIAN_M, val);
7003 REG_WR(bp, PXP2_REG_RQ_CDU_ENDIAN_M, val);
7004 REG_WR(bp, PXP2_REG_RQ_DBG_ENDIAN_M, val);
7006 /* make sure this value is 0 */
7007 REG_WR(bp, PXP2_REG_RQ_HC_ENDIAN_M, 0);
7009 REG_WR(bp, PXP2_REG_RD_QM_SWAP_MODE, val);
7010 REG_WR(bp, PXP2_REG_RD_TM_SWAP_MODE, val);
7011 REG_WR(bp, PXP2_REG_RD_SRC_SWAP_MODE, val);
7012 REG_WR(bp, PXP2_REG_RD_CDURD_SWAP_MODE, val);
7015 static void bnx2x_set_endianity(struct bnx2x *bp)
7018 bnx2x_config_endianity(bp, 1);
7020 bnx2x_config_endianity(bp, 0);
7024 static void bnx2x_reset_endianity(struct bnx2x *bp)
7026 bnx2x_config_endianity(bp, 0);
7030 * bnx2x_init_hw_common - initialize the HW at the COMMON phase.
7032 * @bp: driver handle
7034 static int bnx2x_init_hw_common(struct bnx2x *bp)
7038 DP(NETIF_MSG_HW, "starting common init func %d\n", BP_ABS_FUNC(bp));
7041 * take the RESET lock to protect undi_unload flow from accessing
7042 * registers while we're resetting the chip
7044 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_RESET);
7046 bnx2x_reset_common(bp);
7047 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_SET, 0xffffffff);
7050 if (CHIP_IS_E3(bp)) {
7051 val |= MISC_REGISTERS_RESET_REG_2_MSTAT0;
7052 val |= MISC_REGISTERS_RESET_REG_2_MSTAT1;
7054 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_SET, val);
7056 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_RESET);
7058 bnx2x_init_block(bp, BLOCK_MISC, PHASE_COMMON);
7060 if (!CHIP_IS_E1x(bp)) {
7064 * 4-port mode or 2-port mode we need to turn of master-enable
7065 * for everyone, after that, turn it back on for self.
7066 * so, we disregard multi-function or not, and always disable
7067 * for all functions on the given path, this means 0,2,4,6 for
7068 * path 0 and 1,3,5,7 for path 1
7070 for (abs_func_id = BP_PATH(bp);
7071 abs_func_id < E2_FUNC_MAX*2; abs_func_id += 2) {
7072 if (abs_func_id == BP_ABS_FUNC(bp)) {
7074 PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER,
7079 bnx2x_pretend_func(bp, abs_func_id);
7080 /* clear pf enable */
7081 bnx2x_pf_disable(bp);
7082 bnx2x_pretend_func(bp, BP_ABS_FUNC(bp));
7086 bnx2x_init_block(bp, BLOCK_PXP, PHASE_COMMON);
7087 if (CHIP_IS_E1(bp)) {
7088 /* enable HW interrupt from PXP on USDM overflow
7089 bit 16 on INT_MASK_0 */
7090 REG_WR(bp, PXP_REG_PXP_INT_MASK_0, 0);
7093 bnx2x_init_block(bp, BLOCK_PXP2, PHASE_COMMON);
7095 bnx2x_set_endianity(bp);
7096 bnx2x_ilt_init_page_size(bp, INITOP_SET);
7098 if (CHIP_REV_IS_FPGA(bp) && CHIP_IS_E1H(bp))
7099 REG_WR(bp, PXP2_REG_PGL_TAGS_LIMIT, 0x1);
7101 /* let the HW do it's magic ... */
7103 /* finish PXP init */
7104 val = REG_RD(bp, PXP2_REG_RQ_CFG_DONE);
7106 BNX2X_ERR("PXP2 CFG failed\n");
7109 val = REG_RD(bp, PXP2_REG_RD_INIT_DONE);
7111 BNX2X_ERR("PXP2 RD_INIT failed\n");
7115 /* Timers bug workaround E2 only. We need to set the entire ILT to
7116 * have entries with value "0" and valid bit on.
7117 * This needs to be done by the first PF that is loaded in a path
7118 * (i.e. common phase)
7120 if (!CHIP_IS_E1x(bp)) {
7121 /* In E2 there is a bug in the timers block that can cause function 6 / 7
7122 * (i.e. vnic3) to start even if it is marked as "scan-off".
7123 * This occurs when a different function (func2,3) is being marked
7124 * as "scan-off". Real-life scenario for example: if a driver is being
7125 * load-unloaded while func6,7 are down. This will cause the timer to access
7126 * the ilt, translate to a logical address and send a request to read/write.
7127 * Since the ilt for the function that is down is not valid, this will cause
7128 * a translation error which is unrecoverable.
7129 * The Workaround is intended to make sure that when this happens nothing fatal
7130 * will occur. The workaround:
7131 * 1. First PF driver which loads on a path will:
7132 * a. After taking the chip out of reset, by using pretend,
7133 * it will write "0" to the following registers of
7135 * REG_WR(pdev, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, 0);
7136 * REG_WR(pdev, CFC_REG_WEAK_ENABLE_PF,0);
7137 * REG_WR(pdev, CFC_REG_STRONG_ENABLE_PF,0);
7138 * And for itself it will write '1' to
7139 * PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER to enable
7140 * dmae-operations (writing to pram for example.)
7141 * note: can be done for only function 6,7 but cleaner this
7143 * b. Write zero+valid to the entire ILT.
7144 * c. Init the first_timers_ilt_entry, last_timers_ilt_entry of
7145 * VNIC3 (of that port). The range allocated will be the
7146 * entire ILT. This is needed to prevent ILT range error.
7147 * 2. Any PF driver load flow:
7148 * a. ILT update with the physical addresses of the allocated
7150 * b. Wait 20msec. - note that this timeout is needed to make
7151 * sure there are no requests in one of the PXP internal
7152 * queues with "old" ILT addresses.
7153 * c. PF enable in the PGLC.
7154 * d. Clear the was_error of the PF in the PGLC. (could have
7155 * occurred while driver was down)
7156 * e. PF enable in the CFC (WEAK + STRONG)
7157 * f. Timers scan enable
7158 * 3. PF driver unload flow:
7159 * a. Clear the Timers scan_en.
7160 * b. Polling for scan_on=0 for that PF.
7161 * c. Clear the PF enable bit in the PXP.
7162 * d. Clear the PF enable in the CFC (WEAK + STRONG)
7163 * e. Write zero+valid to all ILT entries (The valid bit must
7165 * f. If this is VNIC 3 of a port then also init
7166 * first_timers_ilt_entry to zero and last_timers_ilt_entry
7167 * to the last entry in the ILT.
7170 * Currently the PF error in the PGLC is non recoverable.
7171 * In the future the there will be a recovery routine for this error.
7172 * Currently attention is masked.
7173 * Having an MCP lock on the load/unload process does not guarantee that
7174 * there is no Timer disable during Func6/7 enable. This is because the
7175 * Timers scan is currently being cleared by the MCP on FLR.
7176 * Step 2.d can be done only for PF6/7 and the driver can also check if
7177 * there is error before clearing it. But the flow above is simpler and
7179 * All ILT entries are written by zero+valid and not just PF6/7
7180 * ILT entries since in the future the ILT entries allocation for
7181 * PF-s might be dynamic.
7183 struct ilt_client_info ilt_cli;
7184 struct bnx2x_ilt ilt;
7185 memset(&ilt_cli, 0, sizeof(struct ilt_client_info));
7186 memset(&ilt, 0, sizeof(struct bnx2x_ilt));
7188 /* initialize dummy TM client */
7190 ilt_cli.end = ILT_NUM_PAGE_ENTRIES - 1;
7191 ilt_cli.client_num = ILT_CLIENT_TM;
7193 /* Step 1: set zeroes to all ilt page entries with valid bit on
7194 * Step 2: set the timers first/last ilt entry to point
7195 * to the entire range to prevent ILT range error for 3rd/4th
7196 * vnic (this code assumes existence of the vnic)
7198 * both steps performed by call to bnx2x_ilt_client_init_op()
7199 * with dummy TM client
7201 * we must use pretend since PXP2_REG_RQ_##blk##_FIRST_ILT
7202 * and his brother are split registers
7204 bnx2x_pretend_func(bp, (BP_PATH(bp) + 6));
7205 bnx2x_ilt_client_init_op_ilt(bp, &ilt, &ilt_cli, INITOP_CLEAR);
7206 bnx2x_pretend_func(bp, BP_ABS_FUNC(bp));
7208 REG_WR(bp, PXP2_REG_RQ_DRAM_ALIGN, BNX2X_PXP_DRAM_ALIGN);
7209 REG_WR(bp, PXP2_REG_RQ_DRAM_ALIGN_RD, BNX2X_PXP_DRAM_ALIGN);
7210 REG_WR(bp, PXP2_REG_RQ_DRAM_ALIGN_SEL, 1);
7213 REG_WR(bp, PXP2_REG_RQ_DISABLE_INPUTS, 0);
7214 REG_WR(bp, PXP2_REG_RD_DISABLE_INPUTS, 0);
7216 if (!CHIP_IS_E1x(bp)) {
7217 int factor = CHIP_REV_IS_EMUL(bp) ? 1000 :
7218 (CHIP_REV_IS_FPGA(bp) ? 400 : 0);
7219 bnx2x_init_block(bp, BLOCK_PGLUE_B, PHASE_COMMON);
7221 bnx2x_init_block(bp, BLOCK_ATC, PHASE_COMMON);
7223 /* let the HW do it's magic ... */
7226 val = REG_RD(bp, ATC_REG_ATC_INIT_DONE);
7227 } while (factor-- && (val != 1));
7230 BNX2X_ERR("ATC_INIT failed\n");
7235 bnx2x_init_block(bp, BLOCK_DMAE, PHASE_COMMON);
7237 bnx2x_iov_init_dmae(bp);
7239 /* clean the DMAE memory */
7241 bnx2x_init_fill(bp, TSEM_REG_PRAM, 0, 8, 1);
7243 bnx2x_init_block(bp, BLOCK_TCM, PHASE_COMMON);
7245 bnx2x_init_block(bp, BLOCK_UCM, PHASE_COMMON);
7247 bnx2x_init_block(bp, BLOCK_CCM, PHASE_COMMON);
7249 bnx2x_init_block(bp, BLOCK_XCM, PHASE_COMMON);
7251 bnx2x_read_dmae(bp, XSEM_REG_PASSIVE_BUFFER, 3);
7252 bnx2x_read_dmae(bp, CSEM_REG_PASSIVE_BUFFER, 3);
7253 bnx2x_read_dmae(bp, TSEM_REG_PASSIVE_BUFFER, 3);
7254 bnx2x_read_dmae(bp, USEM_REG_PASSIVE_BUFFER, 3);
7256 bnx2x_init_block(bp, BLOCK_QM, PHASE_COMMON);
7258 /* QM queues pointers table */
7259 bnx2x_qm_init_ptr_table(bp, bp->qm_cid_count, INITOP_SET);
7261 /* soft reset pulse */
7262 REG_WR(bp, QM_REG_SOFT_RESET, 1);
7263 REG_WR(bp, QM_REG_SOFT_RESET, 0);
7265 if (CNIC_SUPPORT(bp))
7266 bnx2x_init_block(bp, BLOCK_TM, PHASE_COMMON);
7268 bnx2x_init_block(bp, BLOCK_DORQ, PHASE_COMMON);
7270 if (!CHIP_REV_IS_SLOW(bp))
7271 /* enable hw interrupt from doorbell Q */
7272 REG_WR(bp, DORQ_REG_DORQ_INT_MASK, 0);
7274 bnx2x_init_block(bp, BLOCK_BRB1, PHASE_COMMON);
7276 bnx2x_init_block(bp, BLOCK_PRS, PHASE_COMMON);
7277 REG_WR(bp, PRS_REG_A_PRSU_20, 0xf);
7279 if (!CHIP_IS_E1(bp))
7280 REG_WR(bp, PRS_REG_E1HOV_MODE, bp->path_has_ovlan);
7282 if (!CHIP_IS_E1x(bp) && !CHIP_IS_E3B0(bp)) {
7283 if (IS_MF_AFEX(bp)) {
7284 /* configure that VNTag and VLAN headers must be
7285 * received in afex mode
7287 REG_WR(bp, PRS_REG_HDRS_AFTER_BASIC, 0xE);
7288 REG_WR(bp, PRS_REG_MUST_HAVE_HDRS, 0xA);
7289 REG_WR(bp, PRS_REG_HDRS_AFTER_TAG_0, 0x6);
7290 REG_WR(bp, PRS_REG_TAG_ETHERTYPE_0, 0x8926);
7291 REG_WR(bp, PRS_REG_TAG_LEN_0, 0x4);
7293 /* Bit-map indicating which L2 hdrs may appear
7294 * after the basic Ethernet header
7296 REG_WR(bp, PRS_REG_HDRS_AFTER_BASIC,
7297 bp->path_has_ovlan ? 7 : 6);
7301 bnx2x_init_block(bp, BLOCK_TSDM, PHASE_COMMON);
7302 bnx2x_init_block(bp, BLOCK_CSDM, PHASE_COMMON);
7303 bnx2x_init_block(bp, BLOCK_USDM, PHASE_COMMON);
7304 bnx2x_init_block(bp, BLOCK_XSDM, PHASE_COMMON);
7306 if (!CHIP_IS_E1x(bp)) {
7307 /* reset VFC memories */
7308 REG_WR(bp, TSEM_REG_FAST_MEMORY + VFC_REG_MEMORIES_RST,
7309 VFC_MEMORIES_RST_REG_CAM_RST |
7310 VFC_MEMORIES_RST_REG_RAM_RST);
7311 REG_WR(bp, XSEM_REG_FAST_MEMORY + VFC_REG_MEMORIES_RST,
7312 VFC_MEMORIES_RST_REG_CAM_RST |
7313 VFC_MEMORIES_RST_REG_RAM_RST);
7318 bnx2x_init_block(bp, BLOCK_TSEM, PHASE_COMMON);
7319 bnx2x_init_block(bp, BLOCK_USEM, PHASE_COMMON);
7320 bnx2x_init_block(bp, BLOCK_CSEM, PHASE_COMMON);
7321 bnx2x_init_block(bp, BLOCK_XSEM, PHASE_COMMON);
7324 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_CLEAR,
7326 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_SET,
7329 bnx2x_init_block(bp, BLOCK_UPB, PHASE_COMMON);
7330 bnx2x_init_block(bp, BLOCK_XPB, PHASE_COMMON);
7331 bnx2x_init_block(bp, BLOCK_PBF, PHASE_COMMON);
7333 if (!CHIP_IS_E1x(bp)) {
7334 if (IS_MF_AFEX(bp)) {
7335 /* configure that VNTag and VLAN headers must be
7338 REG_WR(bp, PBF_REG_HDRS_AFTER_BASIC, 0xE);
7339 REG_WR(bp, PBF_REG_MUST_HAVE_HDRS, 0xA);
7340 REG_WR(bp, PBF_REG_HDRS_AFTER_TAG_0, 0x6);
7341 REG_WR(bp, PBF_REG_TAG_ETHERTYPE_0, 0x8926);
7342 REG_WR(bp, PBF_REG_TAG_LEN_0, 0x4);
7344 REG_WR(bp, PBF_REG_HDRS_AFTER_BASIC,
7345 bp->path_has_ovlan ? 7 : 6);
7349 REG_WR(bp, SRC_REG_SOFT_RST, 1);
7351 bnx2x_init_block(bp, BLOCK_SRC, PHASE_COMMON);
7353 if (CNIC_SUPPORT(bp)) {
7354 REG_WR(bp, SRC_REG_KEYSEARCH_0, 0x63285672);
7355 REG_WR(bp, SRC_REG_KEYSEARCH_1, 0x24b8f2cc);
7356 REG_WR(bp, SRC_REG_KEYSEARCH_2, 0x223aef9b);
7357 REG_WR(bp, SRC_REG_KEYSEARCH_3, 0x26001e3a);
7358 REG_WR(bp, SRC_REG_KEYSEARCH_4, 0x7ae91116);
7359 REG_WR(bp, SRC_REG_KEYSEARCH_5, 0x5ce5230b);
7360 REG_WR(bp, SRC_REG_KEYSEARCH_6, 0x298d8adf);
7361 REG_WR(bp, SRC_REG_KEYSEARCH_7, 0x6eb0ff09);
7362 REG_WR(bp, SRC_REG_KEYSEARCH_8, 0x1830f82f);
7363 REG_WR(bp, SRC_REG_KEYSEARCH_9, 0x01e46be7);
7365 REG_WR(bp, SRC_REG_SOFT_RST, 0);
7367 if (sizeof(union cdu_context) != 1024)
7368 /* we currently assume that a context is 1024 bytes */
7369 dev_alert(&bp->pdev->dev,
7370 "please adjust the size of cdu_context(%ld)\n",
7371 (long)sizeof(union cdu_context));
7373 bnx2x_init_block(bp, BLOCK_CDU, PHASE_COMMON);
7374 val = (4 << 24) + (0 << 12) + 1024;
7375 REG_WR(bp, CDU_REG_CDU_GLOBAL_PARAMS, val);
7377 bnx2x_init_block(bp, BLOCK_CFC, PHASE_COMMON);
7378 REG_WR(bp, CFC_REG_INIT_REG, 0x7FF);
7379 /* enable context validation interrupt from CFC */
7380 REG_WR(bp, CFC_REG_CFC_INT_MASK, 0);
7382 /* set the thresholds to prevent CFC/CDU race */
7383 REG_WR(bp, CFC_REG_DEBUG0, 0x20020000);
7385 bnx2x_init_block(bp, BLOCK_HC, PHASE_COMMON);
7387 if (!CHIP_IS_E1x(bp) && BP_NOMCP(bp))
7388 REG_WR(bp, IGU_REG_RESET_MEMORIES, 0x36);
7390 bnx2x_init_block(bp, BLOCK_IGU, PHASE_COMMON);
7391 bnx2x_init_block(bp, BLOCK_MISC_AEU, PHASE_COMMON);
7393 /* Reset PCIE errors for debug */
7394 REG_WR(bp, 0x2814, 0xffffffff);
7395 REG_WR(bp, 0x3820, 0xffffffff);
7397 if (!CHIP_IS_E1x(bp)) {
7398 REG_WR(bp, PCICFG_OFFSET + PXPCS_TL_CONTROL_5,
7399 (PXPCS_TL_CONTROL_5_ERR_UNSPPORT1 |
7400 PXPCS_TL_CONTROL_5_ERR_UNSPPORT));
7401 REG_WR(bp, PCICFG_OFFSET + PXPCS_TL_FUNC345_STAT,
7402 (PXPCS_TL_FUNC345_STAT_ERR_UNSPPORT4 |
7403 PXPCS_TL_FUNC345_STAT_ERR_UNSPPORT3 |
7404 PXPCS_TL_FUNC345_STAT_ERR_UNSPPORT2));
7405 REG_WR(bp, PCICFG_OFFSET + PXPCS_TL_FUNC678_STAT,
7406 (PXPCS_TL_FUNC678_STAT_ERR_UNSPPORT7 |
7407 PXPCS_TL_FUNC678_STAT_ERR_UNSPPORT6 |
7408 PXPCS_TL_FUNC678_STAT_ERR_UNSPPORT5));
7411 bnx2x_init_block(bp, BLOCK_NIG, PHASE_COMMON);
7412 if (!CHIP_IS_E1(bp)) {
7413 /* in E3 this done in per-port section */
7414 if (!CHIP_IS_E3(bp))
7415 REG_WR(bp, NIG_REG_LLH_MF_MODE, IS_MF(bp));
7417 if (CHIP_IS_E1H(bp))
7418 /* not applicable for E2 (and above ...) */
7419 REG_WR(bp, NIG_REG_LLH_E1HOV_MODE, IS_MF_SD(bp));
7421 if (CHIP_REV_IS_SLOW(bp))
7424 /* finish CFC init */
7425 val = reg_poll(bp, CFC_REG_LL_INIT_DONE, 1, 100, 10);
7427 BNX2X_ERR("CFC LL_INIT failed\n");
7430 val = reg_poll(bp, CFC_REG_AC_INIT_DONE, 1, 100, 10);
7432 BNX2X_ERR("CFC AC_INIT failed\n");
7435 val = reg_poll(bp, CFC_REG_CAM_INIT_DONE, 1, 100, 10);
7437 BNX2X_ERR("CFC CAM_INIT failed\n");
7440 REG_WR(bp, CFC_REG_DEBUG0, 0);
7442 if (CHIP_IS_E1(bp)) {
7443 /* read NIG statistic
7444 to see if this is our first up since powerup */
7445 bnx2x_read_dmae(bp, NIG_REG_STAT2_BRB_OCTET, 2);
7446 val = *bnx2x_sp(bp, wb_data[0]);
7448 /* do internal memory self test */
7449 if ((val == 0) && bnx2x_int_mem_test(bp)) {
7450 BNX2X_ERR("internal mem self test failed\n");
7455 bnx2x_setup_fan_failure_detection(bp);
7457 /* clear PXP2 attentions */
7458 REG_RD(bp, PXP2_REG_PXP2_INT_STS_CLR_0);
7460 bnx2x_enable_blocks_attention(bp);
7461 bnx2x_enable_blocks_parity(bp);
7463 if (!BP_NOMCP(bp)) {
7464 if (CHIP_IS_E1x(bp))
7465 bnx2x__common_init_phy(bp);
7467 BNX2X_ERR("Bootcode is missing - can not initialize link\n");
7469 if (SHMEM2_HAS(bp, netproc_fw_ver))
7470 SHMEM2_WR(bp, netproc_fw_ver, REG_RD(bp, XSEM_REG_PRAM));
7476 * bnx2x_init_hw_common_chip - init HW at the COMMON_CHIP phase.
7478 * @bp: driver handle
7480 static int bnx2x_init_hw_common_chip(struct bnx2x *bp)
7482 int rc = bnx2x_init_hw_common(bp);
7487 /* In E2 2-PORT mode, same ext phy is used for the two paths */
7489 bnx2x__common_init_phy(bp);
7494 static int bnx2x_init_hw_port(struct bnx2x *bp)
7496 int port = BP_PORT(bp);
7497 int init_phase = port ? PHASE_PORT1 : PHASE_PORT0;
7501 DP(NETIF_MSG_HW, "starting port init port %d\n", port);
7503 REG_WR(bp, NIG_REG_MASK_INTERRUPT_PORT0 + port*4, 0);
7505 bnx2x_init_block(bp, BLOCK_MISC, init_phase);
7506 bnx2x_init_block(bp, BLOCK_PXP, init_phase);
7507 bnx2x_init_block(bp, BLOCK_PXP2, init_phase);
7509 /* Timers bug workaround: disables the pf_master bit in pglue at
7510 * common phase, we need to enable it here before any dmae access are
7511 * attempted. Therefore we manually added the enable-master to the
7512 * port phase (it also happens in the function phase)
7514 if (!CHIP_IS_E1x(bp))
7515 REG_WR(bp, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, 1);
7517 bnx2x_init_block(bp, BLOCK_ATC, init_phase);
7518 bnx2x_init_block(bp, BLOCK_DMAE, init_phase);
7519 bnx2x_init_block(bp, BLOCK_PGLUE_B, init_phase);
7520 bnx2x_init_block(bp, BLOCK_QM, init_phase);
7522 bnx2x_init_block(bp, BLOCK_TCM, init_phase);
7523 bnx2x_init_block(bp, BLOCK_UCM, init_phase);
7524 bnx2x_init_block(bp, BLOCK_CCM, init_phase);
7525 bnx2x_init_block(bp, BLOCK_XCM, init_phase);
7527 /* QM cid (connection) count */
7528 bnx2x_qm_init_cid_count(bp, bp->qm_cid_count, INITOP_SET);
7530 if (CNIC_SUPPORT(bp)) {
7531 bnx2x_init_block(bp, BLOCK_TM, init_phase);
7532 REG_WR(bp, TM_REG_LIN0_SCAN_TIME + port*4, 20);
7533 REG_WR(bp, TM_REG_LIN0_MAX_ACTIVE_CID + port*4, 31);
7536 bnx2x_init_block(bp, BLOCK_DORQ, init_phase);
7538 bnx2x_init_block(bp, BLOCK_BRB1, init_phase);
7540 if (CHIP_IS_E1(bp) || CHIP_IS_E1H(bp)) {
7543 low = ((bp->flags & ONE_PORT_FLAG) ? 160 : 246);
7544 else if (bp->dev->mtu > 4096) {
7545 if (bp->flags & ONE_PORT_FLAG)
7549 /* (24*1024 + val*4)/256 */
7550 low = 96 + (val/64) +
7551 ((val % 64) ? 1 : 0);
7554 low = ((bp->flags & ONE_PORT_FLAG) ? 80 : 160);
7555 high = low + 56; /* 14*1024/256 */
7556 REG_WR(bp, BRB1_REG_PAUSE_LOW_THRESHOLD_0 + port*4, low);
7557 REG_WR(bp, BRB1_REG_PAUSE_HIGH_THRESHOLD_0 + port*4, high);
7560 if (CHIP_MODE_IS_4_PORT(bp))
7561 REG_WR(bp, (BP_PORT(bp) ?
7562 BRB1_REG_MAC_GUARANTIED_1 :
7563 BRB1_REG_MAC_GUARANTIED_0), 40);
7565 bnx2x_init_block(bp, BLOCK_PRS, init_phase);
7566 if (CHIP_IS_E3B0(bp)) {
7567 if (IS_MF_AFEX(bp)) {
7568 /* configure headers for AFEX mode */
7569 REG_WR(bp, BP_PORT(bp) ?
7570 PRS_REG_HDRS_AFTER_BASIC_PORT_1 :
7571 PRS_REG_HDRS_AFTER_BASIC_PORT_0, 0xE);
7572 REG_WR(bp, BP_PORT(bp) ?
7573 PRS_REG_HDRS_AFTER_TAG_0_PORT_1 :
7574 PRS_REG_HDRS_AFTER_TAG_0_PORT_0, 0x6);
7575 REG_WR(bp, BP_PORT(bp) ?
7576 PRS_REG_MUST_HAVE_HDRS_PORT_1 :
7577 PRS_REG_MUST_HAVE_HDRS_PORT_0, 0xA);
7579 /* Ovlan exists only if we are in multi-function +
7580 * switch-dependent mode, in switch-independent there
7581 * is no ovlan headers
7583 REG_WR(bp, BP_PORT(bp) ?
7584 PRS_REG_HDRS_AFTER_BASIC_PORT_1 :
7585 PRS_REG_HDRS_AFTER_BASIC_PORT_0,
7586 (bp->path_has_ovlan ? 7 : 6));
7590 bnx2x_init_block(bp, BLOCK_TSDM, init_phase);
7591 bnx2x_init_block(bp, BLOCK_CSDM, init_phase);
7592 bnx2x_init_block(bp, BLOCK_USDM, init_phase);
7593 bnx2x_init_block(bp, BLOCK_XSDM, init_phase);
7595 bnx2x_init_block(bp, BLOCK_TSEM, init_phase);
7596 bnx2x_init_block(bp, BLOCK_USEM, init_phase);
7597 bnx2x_init_block(bp, BLOCK_CSEM, init_phase);
7598 bnx2x_init_block(bp, BLOCK_XSEM, init_phase);
7600 bnx2x_init_block(bp, BLOCK_UPB, init_phase);
7601 bnx2x_init_block(bp, BLOCK_XPB, init_phase);
7603 bnx2x_init_block(bp, BLOCK_PBF, init_phase);
7605 if (CHIP_IS_E1x(bp)) {
7606 /* configure PBF to work without PAUSE mtu 9000 */
7607 REG_WR(bp, PBF_REG_P0_PAUSE_ENABLE + port*4, 0);
7609 /* update threshold */
7610 REG_WR(bp, PBF_REG_P0_ARB_THRSH + port*4, (9040/16));
7611 /* update init credit */
7612 REG_WR(bp, PBF_REG_P0_INIT_CRD + port*4, (9040/16) + 553 - 22);
7615 REG_WR(bp, PBF_REG_INIT_P0 + port*4, 1);
7617 REG_WR(bp, PBF_REG_INIT_P0 + port*4, 0);
7620 if (CNIC_SUPPORT(bp))
7621 bnx2x_init_block(bp, BLOCK_SRC, init_phase);
7623 bnx2x_init_block(bp, BLOCK_CDU, init_phase);
7624 bnx2x_init_block(bp, BLOCK_CFC, init_phase);
7626 if (CHIP_IS_E1(bp)) {
7627 REG_WR(bp, HC_REG_LEADING_EDGE_0 + port*8, 0);
7628 REG_WR(bp, HC_REG_TRAILING_EDGE_0 + port*8, 0);
7630 bnx2x_init_block(bp, BLOCK_HC, init_phase);
7632 bnx2x_init_block(bp, BLOCK_IGU, init_phase);
7634 bnx2x_init_block(bp, BLOCK_MISC_AEU, init_phase);
7635 /* init aeu_mask_attn_func_0/1:
7636 * - SF mode: bits 3-7 are masked. Only bits 0-2 are in use
7637 * - MF mode: bit 3 is masked. Bits 0-2 are in use as in SF
7638 * bits 4-7 are used for "per vn group attention" */
7639 val = IS_MF(bp) ? 0xF7 : 0x7;
7640 /* Enable DCBX attention for all but E1 */
7641 val |= CHIP_IS_E1(bp) ? 0 : 0x10;
7642 REG_WR(bp, MISC_REG_AEU_MASK_ATTN_FUNC_0 + port*4, val);
7644 /* SCPAD_PARITY should NOT trigger close the gates */
7645 reg = port ? MISC_REG_AEU_ENABLE4_NIG_1 : MISC_REG_AEU_ENABLE4_NIG_0;
7648 ~AEU_INPUTS_ATTN_BITS_MCP_LATCHED_SCPAD_PARITY);
7650 reg = port ? MISC_REG_AEU_ENABLE4_PXP_1 : MISC_REG_AEU_ENABLE4_PXP_0;
7653 ~AEU_INPUTS_ATTN_BITS_MCP_LATCHED_SCPAD_PARITY);
7655 bnx2x_init_block(bp, BLOCK_NIG, init_phase);
7657 if (!CHIP_IS_E1x(bp)) {
7658 /* Bit-map indicating which L2 hdrs may appear after the
7659 * basic Ethernet header
7662 REG_WR(bp, BP_PORT(bp) ?
7663 NIG_REG_P1_HDRS_AFTER_BASIC :
7664 NIG_REG_P0_HDRS_AFTER_BASIC, 0xE);
7666 REG_WR(bp, BP_PORT(bp) ?
7667 NIG_REG_P1_HDRS_AFTER_BASIC :
7668 NIG_REG_P0_HDRS_AFTER_BASIC,
7669 IS_MF_SD(bp) ? 7 : 6);
7672 REG_WR(bp, BP_PORT(bp) ?
7673 NIG_REG_LLH1_MF_MODE :
7674 NIG_REG_LLH_MF_MODE, IS_MF(bp));
7676 if (!CHIP_IS_E3(bp))
7677 REG_WR(bp, NIG_REG_XGXS_SERDES0_MODE_SEL + port*4, 1);
7679 if (!CHIP_IS_E1(bp)) {
7680 /* 0x2 disable mf_ov, 0x1 enable */
7681 REG_WR(bp, NIG_REG_LLH0_BRB1_DRV_MASK_MF + port*4,
7682 (IS_MF_SD(bp) ? 0x1 : 0x2));
7684 if (!CHIP_IS_E1x(bp)) {
7686 switch (bp->mf_mode) {
7687 case MULTI_FUNCTION_SD:
7690 case MULTI_FUNCTION_SI:
7691 case MULTI_FUNCTION_AFEX:
7696 REG_WR(bp, (BP_PORT(bp) ? NIG_REG_LLH1_CLS_TYPE :
7697 NIG_REG_LLH0_CLS_TYPE), val);
7700 REG_WR(bp, NIG_REG_LLFC_ENABLE_0 + port*4, 0);
7701 REG_WR(bp, NIG_REG_LLFC_OUT_EN_0 + port*4, 0);
7702 REG_WR(bp, NIG_REG_PAUSE_ENABLE_0 + port*4, 1);
7706 /* If SPIO5 is set to generate interrupts, enable it for this port */
7707 val = REG_RD(bp, MISC_REG_SPIO_EVENT_EN);
7708 if (val & MISC_SPIO_SPIO5) {
7709 u32 reg_addr = (port ? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_0 :
7710 MISC_REG_AEU_ENABLE1_FUNC_0_OUT_0);
7711 val = REG_RD(bp, reg_addr);
7712 val |= AEU_INPUTS_ATTN_BITS_SPIO5;
7713 REG_WR(bp, reg_addr, val);
7719 static void bnx2x_ilt_wr(struct bnx2x *bp, u32 index, dma_addr_t addr)
7725 reg = PXP2_REG_RQ_ONCHIP_AT + index*8;
7727 reg = PXP2_REG_RQ_ONCHIP_AT_B0 + index*8;
7729 wb_write[0] = ONCHIP_ADDR1(addr);
7730 wb_write[1] = ONCHIP_ADDR2(addr);
7731 REG_WR_DMAE(bp, reg, wb_write, 2);
7734 void bnx2x_igu_clear_sb_gen(struct bnx2x *bp, u8 func, u8 idu_sb_id, bool is_pf)
7736 u32 data, ctl, cnt = 100;
7737 u32 igu_addr_data = IGU_REG_COMMAND_REG_32LSB_DATA;
7738 u32 igu_addr_ctl = IGU_REG_COMMAND_REG_CTRL;
7739 u32 igu_addr_ack = IGU_REG_CSTORM_TYPE_0_SB_CLEANUP + (idu_sb_id/32)*4;
7740 u32 sb_bit = 1 << (idu_sb_id%32);
7741 u32 func_encode = func | (is_pf ? 1 : 0) << IGU_FID_ENCODE_IS_PF_SHIFT;
7742 u32 addr_encode = IGU_CMD_E2_PROD_UPD_BASE + idu_sb_id;
7744 /* Not supported in BC mode */
7745 if (CHIP_INT_MODE_IS_BC(bp))
7748 data = (IGU_USE_REGISTER_cstorm_type_0_sb_cleanup
7749 << IGU_REGULAR_CLEANUP_TYPE_SHIFT) |
7750 IGU_REGULAR_CLEANUP_SET |
7751 IGU_REGULAR_BCLEANUP;
7753 ctl = addr_encode << IGU_CTRL_REG_ADDRESS_SHIFT |
7754 func_encode << IGU_CTRL_REG_FID_SHIFT |
7755 IGU_CTRL_CMD_TYPE_WR << IGU_CTRL_REG_TYPE_SHIFT;
7757 DP(NETIF_MSG_HW, "write 0x%08x to IGU(via GRC) addr 0x%x\n",
7758 data, igu_addr_data);
7759 REG_WR(bp, igu_addr_data, data);
7762 DP(NETIF_MSG_HW, "write 0x%08x to IGU(via GRC) addr 0x%x\n",
7764 REG_WR(bp, igu_addr_ctl, ctl);
7768 /* wait for clean up to finish */
7769 while (!(REG_RD(bp, igu_addr_ack) & sb_bit) && --cnt)
7772 if (!(REG_RD(bp, igu_addr_ack) & sb_bit)) {
7774 "Unable to finish IGU cleanup: idu_sb_id %d offset %d bit %d (cnt %d)\n",
7775 idu_sb_id, idu_sb_id/32, idu_sb_id%32, cnt);
7779 static void bnx2x_igu_clear_sb(struct bnx2x *bp, u8 idu_sb_id)
7781 bnx2x_igu_clear_sb_gen(bp, BP_FUNC(bp), idu_sb_id, true /*PF*/);
7784 static void bnx2x_clear_func_ilt(struct bnx2x *bp, u32 func)
7786 u32 i, base = FUNC_ILT_BASE(func);
7787 for (i = base; i < base + ILT_PER_FUNC; i++)
7788 bnx2x_ilt_wr(bp, i, 0);
7791 static void bnx2x_init_searcher(struct bnx2x *bp)
7793 int port = BP_PORT(bp);
7794 bnx2x_src_init_t2(bp, bp->t2, bp->t2_mapping, SRC_CONN_NUM);
7795 /* T1 hash bits value determines the T1 number of entries */
7796 REG_WR(bp, SRC_REG_NUMBER_HASH_BITS0 + port*4, SRC_HASH_BITS);
7799 static inline int bnx2x_func_switch_update(struct bnx2x *bp, int suspend)
7802 struct bnx2x_func_state_params func_params = {NULL};
7803 struct bnx2x_func_switch_update_params *switch_update_params =
7804 &func_params.params.switch_update;
7806 /* Prepare parameters for function state transitions */
7807 __set_bit(RAMROD_COMP_WAIT, &func_params.ramrod_flags);
7808 __set_bit(RAMROD_RETRY, &func_params.ramrod_flags);
7810 func_params.f_obj = &bp->func_obj;
7811 func_params.cmd = BNX2X_F_CMD_SWITCH_UPDATE;
7813 /* Function parameters */
7814 __set_bit(BNX2X_F_UPDATE_TX_SWITCH_SUSPEND_CHNG,
7815 &switch_update_params->changes);
7817 __set_bit(BNX2X_F_UPDATE_TX_SWITCH_SUSPEND,
7818 &switch_update_params->changes);
7820 rc = bnx2x_func_state_change(bp, &func_params);
7825 static int bnx2x_reset_nic_mode(struct bnx2x *bp)
7827 int rc, i, port = BP_PORT(bp);
7828 int vlan_en = 0, mac_en[NUM_MACS];
7830 /* Close input from network */
7831 if (bp->mf_mode == SINGLE_FUNCTION) {
7832 bnx2x_set_rx_filter(&bp->link_params, 0);
7834 vlan_en = REG_RD(bp, port ? NIG_REG_LLH1_FUNC_EN :
7835 NIG_REG_LLH0_FUNC_EN);
7836 REG_WR(bp, port ? NIG_REG_LLH1_FUNC_EN :
7837 NIG_REG_LLH0_FUNC_EN, 0);
7838 for (i = 0; i < NUM_MACS; i++) {
7839 mac_en[i] = REG_RD(bp, port ?
7840 (NIG_REG_LLH1_FUNC_MEM_ENABLE +
7842 (NIG_REG_LLH0_FUNC_MEM_ENABLE +
7844 REG_WR(bp, port ? (NIG_REG_LLH1_FUNC_MEM_ENABLE +
7846 (NIG_REG_LLH0_FUNC_MEM_ENABLE + 4 * i), 0);
7850 /* Close BMC to host */
7851 REG_WR(bp, port ? NIG_REG_P0_TX_MNG_HOST_ENABLE :
7852 NIG_REG_P1_TX_MNG_HOST_ENABLE, 0);
7854 /* Suspend Tx switching to the PF. Completion of this ramrod
7855 * further guarantees that all the packets of that PF / child
7856 * VFs in BRB were processed by the Parser, so it is safe to
7857 * change the NIC_MODE register.
7859 rc = bnx2x_func_switch_update(bp, 1);
7861 BNX2X_ERR("Can't suspend tx-switching!\n");
7865 /* Change NIC_MODE register */
7866 REG_WR(bp, PRS_REG_NIC_MODE, 0);
7868 /* Open input from network */
7869 if (bp->mf_mode == SINGLE_FUNCTION) {
7870 bnx2x_set_rx_filter(&bp->link_params, 1);
7872 REG_WR(bp, port ? NIG_REG_LLH1_FUNC_EN :
7873 NIG_REG_LLH0_FUNC_EN, vlan_en);
7874 for (i = 0; i < NUM_MACS; i++) {
7875 REG_WR(bp, port ? (NIG_REG_LLH1_FUNC_MEM_ENABLE +
7877 (NIG_REG_LLH0_FUNC_MEM_ENABLE + 4 * i),
7882 /* Enable BMC to host */
7883 REG_WR(bp, port ? NIG_REG_P0_TX_MNG_HOST_ENABLE :
7884 NIG_REG_P1_TX_MNG_HOST_ENABLE, 1);
7886 /* Resume Tx switching to the PF */
7887 rc = bnx2x_func_switch_update(bp, 0);
7889 BNX2X_ERR("Can't resume tx-switching!\n");
7893 DP(NETIF_MSG_IFUP, "NIC MODE disabled\n");
7897 int bnx2x_init_hw_func_cnic(struct bnx2x *bp)
7901 bnx2x_ilt_init_op_cnic(bp, INITOP_SET);
7903 if (CONFIGURE_NIC_MODE(bp)) {
7904 /* Configure searcher as part of function hw init */
7905 bnx2x_init_searcher(bp);
7907 /* Reset NIC mode */
7908 rc = bnx2x_reset_nic_mode(bp);
7910 BNX2X_ERR("Can't change NIC mode!\n");
7917 /* previous driver DMAE transaction may have occurred when pre-boot stage ended
7918 * and boot began, or when kdump kernel was loaded. Either case would invalidate
7919 * the addresses of the transaction, resulting in was-error bit set in the pci
7920 * causing all hw-to-host pcie transactions to timeout. If this happened we want
7921 * to clear the interrupt which detected this from the pglueb and the was done
7924 static void bnx2x_clean_pglue_errors(struct bnx2x *bp)
7926 if (!CHIP_IS_E1x(bp))
7927 REG_WR(bp, PGLUE_B_REG_WAS_ERROR_PF_7_0_CLR,
7928 1 << BP_ABS_FUNC(bp));
7931 static int bnx2x_init_hw_func(struct bnx2x *bp)
7933 int port = BP_PORT(bp);
7934 int func = BP_FUNC(bp);
7935 int init_phase = PHASE_PF0 + func;
7936 struct bnx2x_ilt *ilt = BP_ILT(bp);
7939 u32 main_mem_base, main_mem_size, main_mem_prty_clr;
7940 int i, main_mem_width, rc;
7942 DP(NETIF_MSG_HW, "starting func init func %d\n", func);
7944 /* FLR cleanup - hmmm */
7945 if (!CHIP_IS_E1x(bp)) {
7946 rc = bnx2x_pf_flr_clnup(bp);
7953 /* set MSI reconfigure capability */
7954 if (bp->common.int_block == INT_BLOCK_HC) {
7955 addr = (port ? HC_REG_CONFIG_1 : HC_REG_CONFIG_0);
7956 val = REG_RD(bp, addr);
7957 val |= HC_CONFIG_0_REG_MSI_ATTN_EN_0;
7958 REG_WR(bp, addr, val);
7961 bnx2x_init_block(bp, BLOCK_PXP, init_phase);
7962 bnx2x_init_block(bp, BLOCK_PXP2, init_phase);
7965 cdu_ilt_start = ilt->clients[ILT_CLIENT_CDU].start;
7968 cdu_ilt_start += BNX2X_FIRST_VF_CID/ILT_PAGE_CIDS;
7969 cdu_ilt_start = bnx2x_iov_init_ilt(bp, cdu_ilt_start);
7971 /* since BNX2X_FIRST_VF_CID > 0 the PF L2 cids precedes
7972 * those of the VFs, so start line should be reset
7974 cdu_ilt_start = ilt->clients[ILT_CLIENT_CDU].start;
7975 for (i = 0; i < L2_ILT_LINES(bp); i++) {
7976 ilt->lines[cdu_ilt_start + i].page = bp->context[i].vcxt;
7977 ilt->lines[cdu_ilt_start + i].page_mapping =
7978 bp->context[i].cxt_mapping;
7979 ilt->lines[cdu_ilt_start + i].size = bp->context[i].size;
7982 bnx2x_ilt_init_op(bp, INITOP_SET);
7984 if (!CONFIGURE_NIC_MODE(bp)) {
7985 bnx2x_init_searcher(bp);
7986 REG_WR(bp, PRS_REG_NIC_MODE, 0);
7987 DP(NETIF_MSG_IFUP, "NIC MODE disabled\n");
7990 REG_WR(bp, PRS_REG_NIC_MODE, 1);
7991 DP(NETIF_MSG_IFUP, "NIC MODE configured\n");
7994 if (!CHIP_IS_E1x(bp)) {
7995 u32 pf_conf = IGU_PF_CONF_FUNC_EN;
7997 /* Turn on a single ISR mode in IGU if driver is going to use
8000 if (!(bp->flags & USING_MSIX_FLAG))
8001 pf_conf |= IGU_PF_CONF_SINGLE_ISR_EN;
8003 * Timers workaround bug: function init part.
8004 * Need to wait 20msec after initializing ILT,
8005 * needed to make sure there are no requests in
8006 * one of the PXP internal queues with "old" ILT addresses
8010 * Master enable - Due to WB DMAE writes performed before this
8011 * register is re-initialized as part of the regular function
8014 REG_WR(bp, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, 1);
8015 /* Enable the function in IGU */
8016 REG_WR(bp, IGU_REG_PF_CONFIGURATION, pf_conf);
8021 bnx2x_init_block(bp, BLOCK_PGLUE_B, init_phase);
8023 bnx2x_clean_pglue_errors(bp);
8025 bnx2x_init_block(bp, BLOCK_ATC, init_phase);
8026 bnx2x_init_block(bp, BLOCK_DMAE, init_phase);
8027 bnx2x_init_block(bp, BLOCK_NIG, init_phase);
8028 bnx2x_init_block(bp, BLOCK_SRC, init_phase);
8029 bnx2x_init_block(bp, BLOCK_MISC, init_phase);
8030 bnx2x_init_block(bp, BLOCK_TCM, init_phase);
8031 bnx2x_init_block(bp, BLOCK_UCM, init_phase);
8032 bnx2x_init_block(bp, BLOCK_CCM, init_phase);
8033 bnx2x_init_block(bp, BLOCK_XCM, init_phase);
8034 bnx2x_init_block(bp, BLOCK_TSEM, init_phase);
8035 bnx2x_init_block(bp, BLOCK_USEM, init_phase);
8036 bnx2x_init_block(bp, BLOCK_CSEM, init_phase);
8037 bnx2x_init_block(bp, BLOCK_XSEM, init_phase);
8039 if (!CHIP_IS_E1x(bp))
8040 REG_WR(bp, QM_REG_PF_EN, 1);
8042 if (!CHIP_IS_E1x(bp)) {
8043 REG_WR(bp, TSEM_REG_VFPF_ERR_NUM, BNX2X_MAX_NUM_OF_VFS + func);
8044 REG_WR(bp, USEM_REG_VFPF_ERR_NUM, BNX2X_MAX_NUM_OF_VFS + func);
8045 REG_WR(bp, CSEM_REG_VFPF_ERR_NUM, BNX2X_MAX_NUM_OF_VFS + func);
8046 REG_WR(bp, XSEM_REG_VFPF_ERR_NUM, BNX2X_MAX_NUM_OF_VFS + func);
8048 bnx2x_init_block(bp, BLOCK_QM, init_phase);
8050 bnx2x_init_block(bp, BLOCK_TM, init_phase);
8051 bnx2x_init_block(bp, BLOCK_DORQ, init_phase);
8052 REG_WR(bp, DORQ_REG_MODE_ACT, 1); /* no dpm */
8054 bnx2x_iov_init_dq(bp);
8056 bnx2x_init_block(bp, BLOCK_BRB1, init_phase);
8057 bnx2x_init_block(bp, BLOCK_PRS, init_phase);
8058 bnx2x_init_block(bp, BLOCK_TSDM, init_phase);
8059 bnx2x_init_block(bp, BLOCK_CSDM, init_phase);
8060 bnx2x_init_block(bp, BLOCK_USDM, init_phase);
8061 bnx2x_init_block(bp, BLOCK_XSDM, init_phase);
8062 bnx2x_init_block(bp, BLOCK_UPB, init_phase);
8063 bnx2x_init_block(bp, BLOCK_XPB, init_phase);
8064 bnx2x_init_block(bp, BLOCK_PBF, init_phase);
8065 if (!CHIP_IS_E1x(bp))
8066 REG_WR(bp, PBF_REG_DISABLE_PF, 0);
8068 bnx2x_init_block(bp, BLOCK_CDU, init_phase);
8070 bnx2x_init_block(bp, BLOCK_CFC, init_phase);
8072 if (!CHIP_IS_E1x(bp))
8073 REG_WR(bp, CFC_REG_WEAK_ENABLE_PF, 1);
8076 if (!(IS_MF_UFP(bp) && BNX2X_IS_MF_SD_PROTOCOL_FCOE(bp))) {
8077 REG_WR(bp, NIG_REG_LLH0_FUNC_EN + port * 8, 1);
8078 REG_WR(bp, NIG_REG_LLH0_FUNC_VLAN_ID + port * 8,
8083 bnx2x_init_block(bp, BLOCK_MISC_AEU, init_phase);
8085 /* HC init per function */
8086 if (bp->common.int_block == INT_BLOCK_HC) {
8087 if (CHIP_IS_E1H(bp)) {
8088 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_12 + func*4, 0);
8090 REG_WR(bp, HC_REG_LEADING_EDGE_0 + port*8, 0);
8091 REG_WR(bp, HC_REG_TRAILING_EDGE_0 + port*8, 0);
8093 bnx2x_init_block(bp, BLOCK_HC, init_phase);
8096 int num_segs, sb_idx, prod_offset;
8098 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_12 + func*4, 0);
8100 if (!CHIP_IS_E1x(bp)) {
8101 REG_WR(bp, IGU_REG_LEADING_EDGE_LATCH, 0);
8102 REG_WR(bp, IGU_REG_TRAILING_EDGE_LATCH, 0);
8105 bnx2x_init_block(bp, BLOCK_IGU, init_phase);
8107 if (!CHIP_IS_E1x(bp)) {
8111 * E2 mode: address 0-135 match to the mapping memory;
8112 * 136 - PF0 default prod; 137 - PF1 default prod;
8113 * 138 - PF2 default prod; 139 - PF3 default prod;
8114 * 140 - PF0 attn prod; 141 - PF1 attn prod;
8115 * 142 - PF2 attn prod; 143 - PF3 attn prod;
8118 * E1.5 mode - In backward compatible mode;
8119 * for non default SB; each even line in the memory
8120 * holds the U producer and each odd line hold
8121 * the C producer. The first 128 producers are for
8122 * NDSB (PF0 - 0-31; PF1 - 32-63 and so on). The last 20
8123 * producers are for the DSB for each PF.
8124 * Each PF has five segments: (the order inside each
8125 * segment is PF0; PF1; PF2; PF3) - 128-131 U prods;
8126 * 132-135 C prods; 136-139 X prods; 140-143 T prods;
8127 * 144-147 attn prods;
8129 /* non-default-status-blocks */
8130 num_segs = CHIP_INT_MODE_IS_BC(bp) ?
8131 IGU_BC_NDSB_NUM_SEGS : IGU_NORM_NDSB_NUM_SEGS;
8132 for (sb_idx = 0; sb_idx < bp->igu_sb_cnt; sb_idx++) {
8133 prod_offset = (bp->igu_base_sb + sb_idx) *
8136 for (i = 0; i < num_segs; i++) {
8137 addr = IGU_REG_PROD_CONS_MEMORY +
8138 (prod_offset + i) * 4;
8139 REG_WR(bp, addr, 0);
8141 /* send consumer update with value 0 */
8142 bnx2x_ack_sb(bp, bp->igu_base_sb + sb_idx,
8143 USTORM_ID, 0, IGU_INT_NOP, 1);
8144 bnx2x_igu_clear_sb(bp,
8145 bp->igu_base_sb + sb_idx);
8148 /* default-status-blocks */
8149 num_segs = CHIP_INT_MODE_IS_BC(bp) ?
8150 IGU_BC_DSB_NUM_SEGS : IGU_NORM_DSB_NUM_SEGS;
8152 if (CHIP_MODE_IS_4_PORT(bp))
8153 dsb_idx = BP_FUNC(bp);
8155 dsb_idx = BP_VN(bp);
8157 prod_offset = (CHIP_INT_MODE_IS_BC(bp) ?
8158 IGU_BC_BASE_DSB_PROD + dsb_idx :
8159 IGU_NORM_BASE_DSB_PROD + dsb_idx);
8162 * igu prods come in chunks of E1HVN_MAX (4) -
8163 * does not matters what is the current chip mode
8165 for (i = 0; i < (num_segs * E1HVN_MAX);
8167 addr = IGU_REG_PROD_CONS_MEMORY +
8168 (prod_offset + i)*4;
8169 REG_WR(bp, addr, 0);
8171 /* send consumer update with 0 */
8172 if (CHIP_INT_MODE_IS_BC(bp)) {
8173 bnx2x_ack_sb(bp, bp->igu_dsb_id,
8174 USTORM_ID, 0, IGU_INT_NOP, 1);
8175 bnx2x_ack_sb(bp, bp->igu_dsb_id,
8176 CSTORM_ID, 0, IGU_INT_NOP, 1);
8177 bnx2x_ack_sb(bp, bp->igu_dsb_id,
8178 XSTORM_ID, 0, IGU_INT_NOP, 1);
8179 bnx2x_ack_sb(bp, bp->igu_dsb_id,
8180 TSTORM_ID, 0, IGU_INT_NOP, 1);
8181 bnx2x_ack_sb(bp, bp->igu_dsb_id,
8182 ATTENTION_ID, 0, IGU_INT_NOP, 1);
8184 bnx2x_ack_sb(bp, bp->igu_dsb_id,
8185 USTORM_ID, 0, IGU_INT_NOP, 1);
8186 bnx2x_ack_sb(bp, bp->igu_dsb_id,
8187 ATTENTION_ID, 0, IGU_INT_NOP, 1);
8189 bnx2x_igu_clear_sb(bp, bp->igu_dsb_id);
8191 /* !!! These should become driver const once
8192 rf-tool supports split-68 const */
8193 REG_WR(bp, IGU_REG_SB_INT_BEFORE_MASK_LSB, 0);
8194 REG_WR(bp, IGU_REG_SB_INT_BEFORE_MASK_MSB, 0);
8195 REG_WR(bp, IGU_REG_SB_MASK_LSB, 0);
8196 REG_WR(bp, IGU_REG_SB_MASK_MSB, 0);
8197 REG_WR(bp, IGU_REG_PBA_STATUS_LSB, 0);
8198 REG_WR(bp, IGU_REG_PBA_STATUS_MSB, 0);
8202 /* Reset PCIE errors for debug */
8203 REG_WR(bp, 0x2114, 0xffffffff);
8204 REG_WR(bp, 0x2120, 0xffffffff);
8206 if (CHIP_IS_E1x(bp)) {
8207 main_mem_size = HC_REG_MAIN_MEMORY_SIZE / 2; /*dwords*/
8208 main_mem_base = HC_REG_MAIN_MEMORY +
8209 BP_PORT(bp) * (main_mem_size * 4);
8210 main_mem_prty_clr = HC_REG_HC_PRTY_STS_CLR;
8213 val = REG_RD(bp, main_mem_prty_clr);
8216 "Hmmm... Parity errors in HC block during function init (0x%x)!\n",
8219 /* Clear "false" parity errors in MSI-X table */
8220 for (i = main_mem_base;
8221 i < main_mem_base + main_mem_size * 4;
8222 i += main_mem_width) {
8223 bnx2x_read_dmae(bp, i, main_mem_width / 4);
8224 bnx2x_write_dmae(bp, bnx2x_sp_mapping(bp, wb_data),
8225 i, main_mem_width / 4);
8227 /* Clear HC parity attention */
8228 REG_RD(bp, main_mem_prty_clr);
8231 #ifdef BNX2X_STOP_ON_ERROR
8232 /* Enable STORMs SP logging */
8233 REG_WR8(bp, BAR_USTRORM_INTMEM +
8234 USTORM_RECORD_SLOW_PATH_OFFSET(BP_FUNC(bp)), 1);
8235 REG_WR8(bp, BAR_TSTRORM_INTMEM +
8236 TSTORM_RECORD_SLOW_PATH_OFFSET(BP_FUNC(bp)), 1);
8237 REG_WR8(bp, BAR_CSTRORM_INTMEM +
8238 CSTORM_RECORD_SLOW_PATH_OFFSET(BP_FUNC(bp)), 1);
8239 REG_WR8(bp, BAR_XSTRORM_INTMEM +
8240 XSTORM_RECORD_SLOW_PATH_OFFSET(BP_FUNC(bp)), 1);
8243 bnx2x_phy_probe(&bp->link_params);
8248 void bnx2x_free_mem_cnic(struct bnx2x *bp)
8250 bnx2x_ilt_mem_op_cnic(bp, ILT_MEMOP_FREE);
8252 if (!CHIP_IS_E1x(bp))
8253 BNX2X_PCI_FREE(bp->cnic_sb.e2_sb, bp->cnic_sb_mapping,
8254 sizeof(struct host_hc_status_block_e2));
8256 BNX2X_PCI_FREE(bp->cnic_sb.e1x_sb, bp->cnic_sb_mapping,
8257 sizeof(struct host_hc_status_block_e1x));
8259 BNX2X_PCI_FREE(bp->t2, bp->t2_mapping, SRC_T2_SZ);
8262 void bnx2x_free_mem(struct bnx2x *bp)
8266 BNX2X_PCI_FREE(bp->fw_stats, bp->fw_stats_mapping,
8267 bp->fw_stats_data_sz + bp->fw_stats_req_sz);
8272 BNX2X_PCI_FREE(bp->def_status_blk, bp->def_status_blk_mapping,
8273 sizeof(struct host_sp_status_block));
8275 BNX2X_PCI_FREE(bp->slowpath, bp->slowpath_mapping,
8276 sizeof(struct bnx2x_slowpath));
8278 for (i = 0; i < L2_ILT_LINES(bp); i++)
8279 BNX2X_PCI_FREE(bp->context[i].vcxt, bp->context[i].cxt_mapping,
8280 bp->context[i].size);
8281 bnx2x_ilt_mem_op(bp, ILT_MEMOP_FREE);
8283 BNX2X_FREE(bp->ilt->lines);
8285 BNX2X_PCI_FREE(bp->spq, bp->spq_mapping, BCM_PAGE_SIZE);
8287 BNX2X_PCI_FREE(bp->eq_ring, bp->eq_mapping,
8288 BCM_PAGE_SIZE * NUM_EQ_PAGES);
8290 BNX2X_PCI_FREE(bp->t2, bp->t2_mapping, SRC_T2_SZ);
8292 bnx2x_iov_free_mem(bp);
8295 int bnx2x_alloc_mem_cnic(struct bnx2x *bp)
8297 if (!CHIP_IS_E1x(bp)) {
8298 /* size = the status block + ramrod buffers */
8299 bp->cnic_sb.e2_sb = BNX2X_PCI_ALLOC(&bp->cnic_sb_mapping,
8300 sizeof(struct host_hc_status_block_e2));
8301 if (!bp->cnic_sb.e2_sb)
8304 bp->cnic_sb.e1x_sb = BNX2X_PCI_ALLOC(&bp->cnic_sb_mapping,
8305 sizeof(struct host_hc_status_block_e1x));
8306 if (!bp->cnic_sb.e1x_sb)
8310 if (CONFIGURE_NIC_MODE(bp) && !bp->t2) {
8311 /* allocate searcher T2 table, as it wasn't allocated before */
8312 bp->t2 = BNX2X_PCI_ALLOC(&bp->t2_mapping, SRC_T2_SZ);
8317 /* write address to which L5 should insert its values */
8318 bp->cnic_eth_dev.addr_drv_info_to_mcp =
8319 &bp->slowpath->drv_info_to_mcp;
8321 if (bnx2x_ilt_mem_op_cnic(bp, ILT_MEMOP_ALLOC))
8327 bnx2x_free_mem_cnic(bp);
8328 BNX2X_ERR("Can't allocate memory\n");
8332 int bnx2x_alloc_mem(struct bnx2x *bp)
8334 int i, allocated, context_size;
8336 if (!CONFIGURE_NIC_MODE(bp) && !bp->t2) {
8337 /* allocate searcher T2 table */
8338 bp->t2 = BNX2X_PCI_ALLOC(&bp->t2_mapping, SRC_T2_SZ);
8343 bp->def_status_blk = BNX2X_PCI_ALLOC(&bp->def_status_blk_mapping,
8344 sizeof(struct host_sp_status_block));
8345 if (!bp->def_status_blk)
8348 bp->slowpath = BNX2X_PCI_ALLOC(&bp->slowpath_mapping,
8349 sizeof(struct bnx2x_slowpath));
8353 /* Allocate memory for CDU context:
8354 * This memory is allocated separately and not in the generic ILT
8355 * functions because CDU differs in few aspects:
8356 * 1. There are multiple entities allocating memory for context -
8357 * 'regular' driver, CNIC and SRIOV driver. Each separately controls
8358 * its own ILT lines.
8359 * 2. Since CDU page-size is not a single 4KB page (which is the case
8360 * for the other ILT clients), to be efficient we want to support
8361 * allocation of sub-page-size in the last entry.
8362 * 3. Context pointers are used by the driver to pass to FW / update
8363 * the context (for the other ILT clients the pointers are used just to
8364 * free the memory during unload).
8366 context_size = sizeof(union cdu_context) * BNX2X_L2_CID_COUNT(bp);
8368 for (i = 0, allocated = 0; allocated < context_size; i++) {
8369 bp->context[i].size = min(CDU_ILT_PAGE_SZ,
8370 (context_size - allocated));
8371 bp->context[i].vcxt = BNX2X_PCI_ALLOC(&bp->context[i].cxt_mapping,
8372 bp->context[i].size);
8373 if (!bp->context[i].vcxt)
8375 allocated += bp->context[i].size;
8377 bp->ilt->lines = kcalloc(ILT_MAX_LINES, sizeof(struct ilt_line),
8379 if (!bp->ilt->lines)
8382 if (bnx2x_ilt_mem_op(bp, ILT_MEMOP_ALLOC))
8385 if (bnx2x_iov_alloc_mem(bp))
8388 /* Slow path ring */
8389 bp->spq = BNX2X_PCI_ALLOC(&bp->spq_mapping, BCM_PAGE_SIZE);
8394 bp->eq_ring = BNX2X_PCI_ALLOC(&bp->eq_mapping,
8395 BCM_PAGE_SIZE * NUM_EQ_PAGES);
8403 BNX2X_ERR("Can't allocate memory\n");
8408 * Init service functions
8411 int bnx2x_set_mac_one(struct bnx2x *bp, u8 *mac,
8412 struct bnx2x_vlan_mac_obj *obj, bool set,
8413 int mac_type, unsigned long *ramrod_flags)
8416 struct bnx2x_vlan_mac_ramrod_params ramrod_param;
8418 memset(&ramrod_param, 0, sizeof(ramrod_param));
8420 /* Fill general parameters */
8421 ramrod_param.vlan_mac_obj = obj;
8422 ramrod_param.ramrod_flags = *ramrod_flags;
8424 /* Fill a user request section if needed */
8425 if (!test_bit(RAMROD_CONT, ramrod_flags)) {
8426 memcpy(ramrod_param.user_req.u.mac.mac, mac, ETH_ALEN);
8428 __set_bit(mac_type, &ramrod_param.user_req.vlan_mac_flags);
8430 /* Set the command: ADD or DEL */
8432 ramrod_param.user_req.cmd = BNX2X_VLAN_MAC_ADD;
8434 ramrod_param.user_req.cmd = BNX2X_VLAN_MAC_DEL;
8437 rc = bnx2x_config_vlan_mac(bp, &ramrod_param);
8439 if (rc == -EEXIST) {
8440 DP(BNX2X_MSG_SP, "Failed to schedule ADD operations: %d\n", rc);
8441 /* do not treat adding same MAC as error */
8444 BNX2X_ERR("%s MAC failed\n", (set ? "Set" : "Del"));
8449 int bnx2x_set_vlan_one(struct bnx2x *bp, u16 vlan,
8450 struct bnx2x_vlan_mac_obj *obj, bool set,
8451 unsigned long *ramrod_flags)
8454 struct bnx2x_vlan_mac_ramrod_params ramrod_param;
8456 memset(&ramrod_param, 0, sizeof(ramrod_param));
8458 /* Fill general parameters */
8459 ramrod_param.vlan_mac_obj = obj;
8460 ramrod_param.ramrod_flags = *ramrod_flags;
8462 /* Fill a user request section if needed */
8463 if (!test_bit(RAMROD_CONT, ramrod_flags)) {
8464 ramrod_param.user_req.u.vlan.vlan = vlan;
8465 /* Set the command: ADD or DEL */
8467 ramrod_param.user_req.cmd = BNX2X_VLAN_MAC_ADD;
8469 ramrod_param.user_req.cmd = BNX2X_VLAN_MAC_DEL;
8472 rc = bnx2x_config_vlan_mac(bp, &ramrod_param);
8474 if (rc == -EEXIST) {
8475 /* Do not treat adding same vlan as error. */
8476 DP(BNX2X_MSG_SP, "Failed to schedule ADD operations: %d\n", rc);
8478 } else if (rc < 0) {
8479 BNX2X_ERR("%s VLAN failed\n", (set ? "Set" : "Del"));
8485 int bnx2x_del_all_macs(struct bnx2x *bp,
8486 struct bnx2x_vlan_mac_obj *mac_obj,
8487 int mac_type, bool wait_for_comp)
8490 unsigned long ramrod_flags = 0, vlan_mac_flags = 0;
8492 /* Wait for completion of requested */
8494 __set_bit(RAMROD_COMP_WAIT, &ramrod_flags);
8496 /* Set the mac type of addresses we want to clear */
8497 __set_bit(mac_type, &vlan_mac_flags);
8499 rc = mac_obj->delete_all(bp, mac_obj, &vlan_mac_flags, &ramrod_flags);
8501 BNX2X_ERR("Failed to delete MACs: %d\n", rc);
8506 int bnx2x_set_eth_mac(struct bnx2x *bp, bool set)
8509 unsigned long ramrod_flags = 0;
8511 DP(NETIF_MSG_IFUP, "Adding Eth MAC\n");
8512 __set_bit(RAMROD_COMP_WAIT, &ramrod_flags);
8513 return bnx2x_set_mac_one(bp, bp->dev->dev_addr,
8514 &bp->sp_objs->mac_obj, set,
8515 BNX2X_ETH_MAC, &ramrod_flags);
8517 return bnx2x_vfpf_config_mac(bp, bp->dev->dev_addr,
8518 bp->fp->index, set);
8522 int bnx2x_setup_leading(struct bnx2x *bp)
8525 return bnx2x_setup_queue(bp, &bp->fp[0], true);
8527 return bnx2x_vfpf_setup_q(bp, &bp->fp[0], true);
8531 * bnx2x_set_int_mode - configure interrupt mode
8533 * @bp: driver handle
8535 * In case of MSI-X it will also try to enable MSI-X.
8537 int bnx2x_set_int_mode(struct bnx2x *bp)
8541 if (IS_VF(bp) && int_mode != BNX2X_INT_MODE_MSIX) {
8542 BNX2X_ERR("VF not loaded since interrupt mode not msix\n");
8547 case BNX2X_INT_MODE_MSIX:
8548 /* attempt to enable msix */
8549 rc = bnx2x_enable_msix(bp);
8555 /* vfs use only msix */
8556 if (rc && IS_VF(bp))
8559 /* failed to enable multiple MSI-X */
8560 BNX2X_DEV_INFO("Failed to enable multiple MSI-X (%d), set number of queues to %d\n",
8562 1 + bp->num_cnic_queues);
8564 /* falling through... */
8565 case BNX2X_INT_MODE_MSI:
8566 bnx2x_enable_msi(bp);
8568 /* falling through... */
8569 case BNX2X_INT_MODE_INTX:
8570 bp->num_ethernet_queues = 1;
8571 bp->num_queues = bp->num_ethernet_queues + bp->num_cnic_queues;
8572 BNX2X_DEV_INFO("set number of queues to 1\n");
8575 BNX2X_DEV_INFO("unknown value in int_mode module parameter\n");
8581 /* must be called prior to any HW initializations */
8582 static inline u16 bnx2x_cid_ilt_lines(struct bnx2x *bp)
8585 return (BNX2X_FIRST_VF_CID + BNX2X_VF_CIDS)/ILT_PAGE_CIDS;
8586 return L2_ILT_LINES(bp);
8589 void bnx2x_ilt_set_info(struct bnx2x *bp)
8591 struct ilt_client_info *ilt_client;
8592 struct bnx2x_ilt *ilt = BP_ILT(bp);
8595 ilt->start_line = FUNC_ILT_BASE(BP_FUNC(bp));
8596 DP(BNX2X_MSG_SP, "ilt starts at line %d\n", ilt->start_line);
8599 ilt_client = &ilt->clients[ILT_CLIENT_CDU];
8600 ilt_client->client_num = ILT_CLIENT_CDU;
8601 ilt_client->page_size = CDU_ILT_PAGE_SZ;
8602 ilt_client->flags = ILT_CLIENT_SKIP_MEM;
8603 ilt_client->start = line;
8604 line += bnx2x_cid_ilt_lines(bp);
8606 if (CNIC_SUPPORT(bp))
8607 line += CNIC_ILT_LINES;
8608 ilt_client->end = line - 1;
8610 DP(NETIF_MSG_IFUP, "ilt client[CDU]: start %d, end %d, psz 0x%x, flags 0x%x, hw psz %d\n",
8613 ilt_client->page_size,
8615 ilog2(ilt_client->page_size >> 12));
8618 if (QM_INIT(bp->qm_cid_count)) {
8619 ilt_client = &ilt->clients[ILT_CLIENT_QM];
8620 ilt_client->client_num = ILT_CLIENT_QM;
8621 ilt_client->page_size = QM_ILT_PAGE_SZ;
8622 ilt_client->flags = 0;
8623 ilt_client->start = line;
8625 /* 4 bytes for each cid */
8626 line += DIV_ROUND_UP(bp->qm_cid_count * QM_QUEUES_PER_FUNC * 4,
8629 ilt_client->end = line - 1;
8632 "ilt client[QM]: start %d, end %d, psz 0x%x, flags 0x%x, hw psz %d\n",
8635 ilt_client->page_size,
8637 ilog2(ilt_client->page_size >> 12));
8640 if (CNIC_SUPPORT(bp)) {
8642 ilt_client = &ilt->clients[ILT_CLIENT_SRC];
8643 ilt_client->client_num = ILT_CLIENT_SRC;
8644 ilt_client->page_size = SRC_ILT_PAGE_SZ;
8645 ilt_client->flags = 0;
8646 ilt_client->start = line;
8647 line += SRC_ILT_LINES;
8648 ilt_client->end = line - 1;
8651 "ilt client[SRC]: start %d, end %d, psz 0x%x, flags 0x%x, hw psz %d\n",
8654 ilt_client->page_size,
8656 ilog2(ilt_client->page_size >> 12));
8659 ilt_client = &ilt->clients[ILT_CLIENT_TM];
8660 ilt_client->client_num = ILT_CLIENT_TM;
8661 ilt_client->page_size = TM_ILT_PAGE_SZ;
8662 ilt_client->flags = 0;
8663 ilt_client->start = line;
8664 line += TM_ILT_LINES;
8665 ilt_client->end = line - 1;
8668 "ilt client[TM]: start %d, end %d, psz 0x%x, flags 0x%x, hw psz %d\n",
8671 ilt_client->page_size,
8673 ilog2(ilt_client->page_size >> 12));
8676 BUG_ON(line > ILT_MAX_LINES);
8680 * bnx2x_pf_q_prep_init - prepare INIT transition parameters
8682 * @bp: driver handle
8683 * @fp: pointer to fastpath
8684 * @init_params: pointer to parameters structure
8686 * parameters configured:
8687 * - HC configuration
8688 * - Queue's CDU context
8690 static void bnx2x_pf_q_prep_init(struct bnx2x *bp,
8691 struct bnx2x_fastpath *fp, struct bnx2x_queue_init_params *init_params)
8694 int cxt_index, cxt_offset;
8696 /* FCoE Queue uses Default SB, thus has no HC capabilities */
8697 if (!IS_FCOE_FP(fp)) {
8698 __set_bit(BNX2X_Q_FLG_HC, &init_params->rx.flags);
8699 __set_bit(BNX2X_Q_FLG_HC, &init_params->tx.flags);
8701 /* If HC is supported, enable host coalescing in the transition
8704 __set_bit(BNX2X_Q_FLG_HC_EN, &init_params->rx.flags);
8705 __set_bit(BNX2X_Q_FLG_HC_EN, &init_params->tx.flags);
8708 init_params->rx.hc_rate = bp->rx_ticks ?
8709 (1000000 / bp->rx_ticks) : 0;
8710 init_params->tx.hc_rate = bp->tx_ticks ?
8711 (1000000 / bp->tx_ticks) : 0;
8714 init_params->rx.fw_sb_id = init_params->tx.fw_sb_id =
8718 * CQ index among the SB indices: FCoE clients uses the default
8719 * SB, therefore it's different.
8721 init_params->rx.sb_cq_index = HC_INDEX_ETH_RX_CQ_CONS;
8722 init_params->tx.sb_cq_index = HC_INDEX_ETH_FIRST_TX_CQ_CONS;
8725 /* set maximum number of COSs supported by this queue */
8726 init_params->max_cos = fp->max_cos;
8728 DP(NETIF_MSG_IFUP, "fp: %d setting queue params max cos to: %d\n",
8729 fp->index, init_params->max_cos);
8731 /* set the context pointers queue object */
8732 for (cos = FIRST_TX_COS_INDEX; cos < init_params->max_cos; cos++) {
8733 cxt_index = fp->txdata_ptr[cos]->cid / ILT_PAGE_CIDS;
8734 cxt_offset = fp->txdata_ptr[cos]->cid - (cxt_index *
8736 init_params->cxts[cos] =
8737 &bp->context[cxt_index].vcxt[cxt_offset].eth;
8741 static int bnx2x_setup_tx_only(struct bnx2x *bp, struct bnx2x_fastpath *fp,
8742 struct bnx2x_queue_state_params *q_params,
8743 struct bnx2x_queue_setup_tx_only_params *tx_only_params,
8744 int tx_index, bool leading)
8746 memset(tx_only_params, 0, sizeof(*tx_only_params));
8748 /* Set the command */
8749 q_params->cmd = BNX2X_Q_CMD_SETUP_TX_ONLY;
8751 /* Set tx-only QUEUE flags: don't zero statistics */
8752 tx_only_params->flags = bnx2x_get_common_flags(bp, fp, false);
8754 /* choose the index of the cid to send the slow path on */
8755 tx_only_params->cid_index = tx_index;
8757 /* Set general TX_ONLY_SETUP parameters */
8758 bnx2x_pf_q_prep_general(bp, fp, &tx_only_params->gen_params, tx_index);
8760 /* Set Tx TX_ONLY_SETUP parameters */
8761 bnx2x_pf_tx_q_prep(bp, fp, &tx_only_params->txq_params, tx_index);
8764 "preparing to send tx-only ramrod for connection: cos %d, primary cid %d, cid %d, client id %d, sp-client id %d, flags %lx\n",
8765 tx_index, q_params->q_obj->cids[FIRST_TX_COS_INDEX],
8766 q_params->q_obj->cids[tx_index], q_params->q_obj->cl_id,
8767 tx_only_params->gen_params.spcl_id, tx_only_params->flags);
8769 /* send the ramrod */
8770 return bnx2x_queue_state_change(bp, q_params);
8774 * bnx2x_setup_queue - setup queue
8776 * @bp: driver handle
8777 * @fp: pointer to fastpath
8778 * @leading: is leading
8780 * This function performs 2 steps in a Queue state machine
8781 * actually: 1) RESET->INIT 2) INIT->SETUP
8784 int bnx2x_setup_queue(struct bnx2x *bp, struct bnx2x_fastpath *fp,
8787 struct bnx2x_queue_state_params q_params = {NULL};
8788 struct bnx2x_queue_setup_params *setup_params =
8789 &q_params.params.setup;
8790 struct bnx2x_queue_setup_tx_only_params *tx_only_params =
8791 &q_params.params.tx_only;
8795 DP(NETIF_MSG_IFUP, "setting up queue %d\n", fp->index);
8797 /* reset IGU state skip FCoE L2 queue */
8798 if (!IS_FCOE_FP(fp))
8799 bnx2x_ack_sb(bp, fp->igu_sb_id, USTORM_ID, 0,
8802 q_params.q_obj = &bnx2x_sp_obj(bp, fp).q_obj;
8803 /* We want to wait for completion in this context */
8804 __set_bit(RAMROD_COMP_WAIT, &q_params.ramrod_flags);
8806 /* Prepare the INIT parameters */
8807 bnx2x_pf_q_prep_init(bp, fp, &q_params.params.init);
8809 /* Set the command */
8810 q_params.cmd = BNX2X_Q_CMD_INIT;
8812 /* Change the state to INIT */
8813 rc = bnx2x_queue_state_change(bp, &q_params);
8815 BNX2X_ERR("Queue(%d) INIT failed\n", fp->index);
8819 DP(NETIF_MSG_IFUP, "init complete\n");
8821 /* Now move the Queue to the SETUP state... */
8822 memset(setup_params, 0, sizeof(*setup_params));
8824 /* Set QUEUE flags */
8825 setup_params->flags = bnx2x_get_q_flags(bp, fp, leading);
8827 /* Set general SETUP parameters */
8828 bnx2x_pf_q_prep_general(bp, fp, &setup_params->gen_params,
8829 FIRST_TX_COS_INDEX);
8831 bnx2x_pf_rx_q_prep(bp, fp, &setup_params->pause_params,
8832 &setup_params->rxq_params);
8834 bnx2x_pf_tx_q_prep(bp, fp, &setup_params->txq_params,
8835 FIRST_TX_COS_INDEX);
8837 /* Set the command */
8838 q_params.cmd = BNX2X_Q_CMD_SETUP;
8841 bp->fcoe_init = true;
8843 /* Change the state to SETUP */
8844 rc = bnx2x_queue_state_change(bp, &q_params);
8846 BNX2X_ERR("Queue(%d) SETUP failed\n", fp->index);
8850 /* loop through the relevant tx-only indices */
8851 for (tx_index = FIRST_TX_ONLY_COS_INDEX;
8852 tx_index < fp->max_cos;
8855 /* prepare and send tx-only ramrod*/
8856 rc = bnx2x_setup_tx_only(bp, fp, &q_params,
8857 tx_only_params, tx_index, leading);
8859 BNX2X_ERR("Queue(%d.%d) TX_ONLY_SETUP failed\n",
8860 fp->index, tx_index);
8868 static int bnx2x_stop_queue(struct bnx2x *bp, int index)
8870 struct bnx2x_fastpath *fp = &bp->fp[index];
8871 struct bnx2x_fp_txdata *txdata;
8872 struct bnx2x_queue_state_params q_params = {NULL};
8875 DP(NETIF_MSG_IFDOWN, "stopping queue %d cid %d\n", index, fp->cid);
8877 q_params.q_obj = &bnx2x_sp_obj(bp, fp).q_obj;
8878 /* We want to wait for completion in this context */
8879 __set_bit(RAMROD_COMP_WAIT, &q_params.ramrod_flags);
8881 /* close tx-only connections */
8882 for (tx_index = FIRST_TX_ONLY_COS_INDEX;
8883 tx_index < fp->max_cos;
8886 /* ascertain this is a normal queue*/
8887 txdata = fp->txdata_ptr[tx_index];
8889 DP(NETIF_MSG_IFDOWN, "stopping tx-only queue %d\n",
8892 /* send halt terminate on tx-only connection */
8893 q_params.cmd = BNX2X_Q_CMD_TERMINATE;
8894 memset(&q_params.params.terminate, 0,
8895 sizeof(q_params.params.terminate));
8896 q_params.params.terminate.cid_index = tx_index;
8898 rc = bnx2x_queue_state_change(bp, &q_params);
8902 /* send halt terminate on tx-only connection */
8903 q_params.cmd = BNX2X_Q_CMD_CFC_DEL;
8904 memset(&q_params.params.cfc_del, 0,
8905 sizeof(q_params.params.cfc_del));
8906 q_params.params.cfc_del.cid_index = tx_index;
8907 rc = bnx2x_queue_state_change(bp, &q_params);
8911 /* Stop the primary connection: */
8912 /* ...halt the connection */
8913 q_params.cmd = BNX2X_Q_CMD_HALT;
8914 rc = bnx2x_queue_state_change(bp, &q_params);
8918 /* ...terminate the connection */
8919 q_params.cmd = BNX2X_Q_CMD_TERMINATE;
8920 memset(&q_params.params.terminate, 0,
8921 sizeof(q_params.params.terminate));
8922 q_params.params.terminate.cid_index = FIRST_TX_COS_INDEX;
8923 rc = bnx2x_queue_state_change(bp, &q_params);
8926 /* ...delete cfc entry */
8927 q_params.cmd = BNX2X_Q_CMD_CFC_DEL;
8928 memset(&q_params.params.cfc_del, 0,
8929 sizeof(q_params.params.cfc_del));
8930 q_params.params.cfc_del.cid_index = FIRST_TX_COS_INDEX;
8931 return bnx2x_queue_state_change(bp, &q_params);
8934 static void bnx2x_reset_func(struct bnx2x *bp)
8936 int port = BP_PORT(bp);
8937 int func = BP_FUNC(bp);
8940 /* Disable the function in the FW */
8941 REG_WR8(bp, BAR_XSTRORM_INTMEM + XSTORM_FUNC_EN_OFFSET(func), 0);
8942 REG_WR8(bp, BAR_CSTRORM_INTMEM + CSTORM_FUNC_EN_OFFSET(func), 0);
8943 REG_WR8(bp, BAR_TSTRORM_INTMEM + TSTORM_FUNC_EN_OFFSET(func), 0);
8944 REG_WR8(bp, BAR_USTRORM_INTMEM + USTORM_FUNC_EN_OFFSET(func), 0);
8947 for_each_eth_queue(bp, i) {
8948 struct bnx2x_fastpath *fp = &bp->fp[i];
8949 REG_WR8(bp, BAR_CSTRORM_INTMEM +
8950 CSTORM_STATUS_BLOCK_DATA_STATE_OFFSET(fp->fw_sb_id),
8954 if (CNIC_LOADED(bp))
8956 REG_WR8(bp, BAR_CSTRORM_INTMEM +
8957 CSTORM_STATUS_BLOCK_DATA_STATE_OFFSET
8958 (bnx2x_cnic_fw_sb_id(bp)), SB_DISABLED);
8961 REG_WR8(bp, BAR_CSTRORM_INTMEM +
8962 CSTORM_SP_STATUS_BLOCK_DATA_STATE_OFFSET(func),
8965 for (i = 0; i < XSTORM_SPQ_DATA_SIZE / 4; i++)
8966 REG_WR(bp, BAR_XSTRORM_INTMEM + XSTORM_SPQ_DATA_OFFSET(func),
8970 if (bp->common.int_block == INT_BLOCK_HC) {
8971 REG_WR(bp, HC_REG_LEADING_EDGE_0 + port*8, 0);
8972 REG_WR(bp, HC_REG_TRAILING_EDGE_0 + port*8, 0);
8974 REG_WR(bp, IGU_REG_LEADING_EDGE_LATCH, 0);
8975 REG_WR(bp, IGU_REG_TRAILING_EDGE_LATCH, 0);
8978 if (CNIC_LOADED(bp)) {
8979 /* Disable Timer scan */
8980 REG_WR(bp, TM_REG_EN_LINEAR0_TIMER + port*4, 0);
8982 * Wait for at least 10ms and up to 2 second for the timers
8985 for (i = 0; i < 200; i++) {
8986 usleep_range(10000, 20000);
8987 if (!REG_RD(bp, TM_REG_LIN0_SCAN_ON + port*4))
8992 bnx2x_clear_func_ilt(bp, func);
8994 /* Timers workaround bug for E2: if this is vnic-3,
8995 * we need to set the entire ilt range for this timers.
8997 if (!CHIP_IS_E1x(bp) && BP_VN(bp) == 3) {
8998 struct ilt_client_info ilt_cli;
8999 /* use dummy TM client */
9000 memset(&ilt_cli, 0, sizeof(struct ilt_client_info));
9002 ilt_cli.end = ILT_NUM_PAGE_ENTRIES - 1;
9003 ilt_cli.client_num = ILT_CLIENT_TM;
9005 bnx2x_ilt_boundry_init_op(bp, &ilt_cli, 0, INITOP_CLEAR);
9008 /* this assumes that reset_port() called before reset_func()*/
9009 if (!CHIP_IS_E1x(bp))
9010 bnx2x_pf_disable(bp);
9015 static void bnx2x_reset_port(struct bnx2x *bp)
9017 int port = BP_PORT(bp);
9020 /* Reset physical Link */
9021 bnx2x__link_reset(bp);
9023 REG_WR(bp, NIG_REG_MASK_INTERRUPT_PORT0 + port*4, 0);
9025 /* Do not rcv packets to BRB */
9026 REG_WR(bp, NIG_REG_LLH0_BRB1_DRV_MASK + port*4, 0x0);
9027 /* Do not direct rcv packets that are not for MCP to the BRB */
9028 REG_WR(bp, (port ? NIG_REG_LLH1_BRB1_NOT_MCP :
9029 NIG_REG_LLH0_BRB1_NOT_MCP), 0x0);
9032 REG_WR(bp, MISC_REG_AEU_MASK_ATTN_FUNC_0 + port*4, 0);
9035 /* Check for BRB port occupancy */
9036 val = REG_RD(bp, BRB1_REG_PORT_NUM_OCC_BLOCKS_0 + port*4);
9038 DP(NETIF_MSG_IFDOWN,
9039 "BRB1 is not empty %d blocks are occupied\n", val);
9041 /* TODO: Close Doorbell port? */
9044 static int bnx2x_reset_hw(struct bnx2x *bp, u32 load_code)
9046 struct bnx2x_func_state_params func_params = {NULL};
9048 /* Prepare parameters for function state transitions */
9049 __set_bit(RAMROD_COMP_WAIT, &func_params.ramrod_flags);
9051 func_params.f_obj = &bp->func_obj;
9052 func_params.cmd = BNX2X_F_CMD_HW_RESET;
9054 func_params.params.hw_init.load_phase = load_code;
9056 return bnx2x_func_state_change(bp, &func_params);
9059 static int bnx2x_func_stop(struct bnx2x *bp)
9061 struct bnx2x_func_state_params func_params = {NULL};
9064 /* Prepare parameters for function state transitions */
9065 __set_bit(RAMROD_COMP_WAIT, &func_params.ramrod_flags);
9066 func_params.f_obj = &bp->func_obj;
9067 func_params.cmd = BNX2X_F_CMD_STOP;
9070 * Try to stop the function the 'good way'. If fails (in case
9071 * of a parity error during bnx2x_chip_cleanup()) and we are
9072 * not in a debug mode, perform a state transaction in order to
9073 * enable further HW_RESET transaction.
9075 rc = bnx2x_func_state_change(bp, &func_params);
9077 #ifdef BNX2X_STOP_ON_ERROR
9080 BNX2X_ERR("FUNC_STOP ramrod failed. Running a dry transaction\n");
9081 __set_bit(RAMROD_DRV_CLR_ONLY, &func_params.ramrod_flags);
9082 return bnx2x_func_state_change(bp, &func_params);
9090 * bnx2x_send_unload_req - request unload mode from the MCP.
9092 * @bp: driver handle
9093 * @unload_mode: requested function's unload mode
9095 * Return unload mode returned by the MCP: COMMON, PORT or FUNC.
9097 u32 bnx2x_send_unload_req(struct bnx2x *bp, int unload_mode)
9100 int port = BP_PORT(bp);
9102 /* Select the UNLOAD request mode */
9103 if (unload_mode == UNLOAD_NORMAL)
9104 reset_code = DRV_MSG_CODE_UNLOAD_REQ_WOL_DIS;
9106 else if (bp->flags & NO_WOL_FLAG)
9107 reset_code = DRV_MSG_CODE_UNLOAD_REQ_WOL_MCP;
9110 u32 emac_base = port ? GRCBASE_EMAC1 : GRCBASE_EMAC0;
9111 u8 *mac_addr = bp->dev->dev_addr;
9112 struct pci_dev *pdev = bp->pdev;
9116 /* The mac address is written to entries 1-4 to
9117 * preserve entry 0 which is used by the PMF
9119 u8 entry = (BP_VN(bp) + 1)*8;
9121 val = (mac_addr[0] << 8) | mac_addr[1];
9122 EMAC_WR(bp, EMAC_REG_EMAC_MAC_MATCH + entry, val);
9124 val = (mac_addr[2] << 24) | (mac_addr[3] << 16) |
9125 (mac_addr[4] << 8) | mac_addr[5];
9126 EMAC_WR(bp, EMAC_REG_EMAC_MAC_MATCH + entry + 4, val);
9128 /* Enable the PME and clear the status */
9129 pci_read_config_word(pdev, pdev->pm_cap + PCI_PM_CTRL, &pmc);
9130 pmc |= PCI_PM_CTRL_PME_ENABLE | PCI_PM_CTRL_PME_STATUS;
9131 pci_write_config_word(pdev, pdev->pm_cap + PCI_PM_CTRL, pmc);
9133 reset_code = DRV_MSG_CODE_UNLOAD_REQ_WOL_EN;
9136 reset_code = DRV_MSG_CODE_UNLOAD_REQ_WOL_DIS;
9138 /* Send the request to the MCP */
9140 reset_code = bnx2x_fw_command(bp, reset_code, 0);
9142 int path = BP_PATH(bp);
9144 DP(NETIF_MSG_IFDOWN, "NO MCP - load counts[%d] %d, %d, %d\n",
9145 path, bnx2x_load_count[path][0], bnx2x_load_count[path][1],
9146 bnx2x_load_count[path][2]);
9147 bnx2x_load_count[path][0]--;
9148 bnx2x_load_count[path][1 + port]--;
9149 DP(NETIF_MSG_IFDOWN, "NO MCP - new load counts[%d] %d, %d, %d\n",
9150 path, bnx2x_load_count[path][0], bnx2x_load_count[path][1],
9151 bnx2x_load_count[path][2]);
9152 if (bnx2x_load_count[path][0] == 0)
9153 reset_code = FW_MSG_CODE_DRV_UNLOAD_COMMON;
9154 else if (bnx2x_load_count[path][1 + port] == 0)
9155 reset_code = FW_MSG_CODE_DRV_UNLOAD_PORT;
9157 reset_code = FW_MSG_CODE_DRV_UNLOAD_FUNCTION;
9164 * bnx2x_send_unload_done - send UNLOAD_DONE command to the MCP.
9166 * @bp: driver handle
9167 * @keep_link: true iff link should be kept up
9169 void bnx2x_send_unload_done(struct bnx2x *bp, bool keep_link)
9171 u32 reset_param = keep_link ? DRV_MSG_CODE_UNLOAD_SKIP_LINK_RESET : 0;
9173 /* Report UNLOAD_DONE to MCP */
9175 bnx2x_fw_command(bp, DRV_MSG_CODE_UNLOAD_DONE, reset_param);
9178 static int bnx2x_func_wait_started(struct bnx2x *bp)
9181 int msix = (bp->flags & USING_MSIX_FLAG) ? 1 : 0;
9187 * (assumption: No Attention from MCP at this stage)
9188 * PMF probably in the middle of TX disable/enable transaction
9189 * 1. Sync IRS for default SB
9190 * 2. Sync SP queue - this guarantees us that attention handling started
9191 * 3. Wait, that TX disable/enable transaction completes
9193 * 1+2 guarantee that if DCBx attention was scheduled it already changed
9194 * pending bit of transaction from STARTED-->TX_STOPPED, if we already
9195 * received completion for the transaction the state is TX_STOPPED.
9196 * State will return to STARTED after completion of TX_STOPPED-->STARTED
9200 /* make sure default SB ISR is done */
9202 synchronize_irq(bp->msix_table[0].vector);
9204 synchronize_irq(bp->pdev->irq);
9206 flush_workqueue(bnx2x_wq);
9207 flush_workqueue(bnx2x_iov_wq);
9209 while (bnx2x_func_get_state(bp, &bp->func_obj) !=
9210 BNX2X_F_STATE_STARTED && tout--)
9213 if (bnx2x_func_get_state(bp, &bp->func_obj) !=
9214 BNX2X_F_STATE_STARTED) {
9215 #ifdef BNX2X_STOP_ON_ERROR
9216 BNX2X_ERR("Wrong function state\n");
9220 * Failed to complete the transaction in a "good way"
9221 * Force both transactions with CLR bit
9223 struct bnx2x_func_state_params func_params = {NULL};
9225 DP(NETIF_MSG_IFDOWN,
9226 "Hmmm... Unexpected function state! Forcing STARTED-->TX_STOPPED-->STARTED\n");
9228 func_params.f_obj = &bp->func_obj;
9229 __set_bit(RAMROD_DRV_CLR_ONLY,
9230 &func_params.ramrod_flags);
9232 /* STARTED-->TX_ST0PPED */
9233 func_params.cmd = BNX2X_F_CMD_TX_STOP;
9234 bnx2x_func_state_change(bp, &func_params);
9236 /* TX_ST0PPED-->STARTED */
9237 func_params.cmd = BNX2X_F_CMD_TX_START;
9238 return bnx2x_func_state_change(bp, &func_params);
9245 static void bnx2x_disable_ptp(struct bnx2x *bp)
9247 int port = BP_PORT(bp);
9249 /* Disable sending PTP packets to host */
9250 REG_WR(bp, port ? NIG_REG_P1_LLH_PTP_TO_HOST :
9251 NIG_REG_P0_LLH_PTP_TO_HOST, 0x0);
9253 /* Reset PTP event detection rules */
9254 REG_WR(bp, port ? NIG_REG_P1_LLH_PTP_PARAM_MASK :
9255 NIG_REG_P0_LLH_PTP_PARAM_MASK, 0x7FF);
9256 REG_WR(bp, port ? NIG_REG_P1_LLH_PTP_RULE_MASK :
9257 NIG_REG_P0_LLH_PTP_RULE_MASK, 0x3FFF);
9258 REG_WR(bp, port ? NIG_REG_P1_TLLH_PTP_PARAM_MASK :
9259 NIG_REG_P0_TLLH_PTP_PARAM_MASK, 0x7FF);
9260 REG_WR(bp, port ? NIG_REG_P1_TLLH_PTP_RULE_MASK :
9261 NIG_REG_P0_TLLH_PTP_RULE_MASK, 0x3FFF);
9263 /* Disable the PTP feature */
9264 REG_WR(bp, port ? NIG_REG_P1_PTP_EN :
9265 NIG_REG_P0_PTP_EN, 0x0);
9268 /* Called during unload, to stop PTP-related stuff */
9269 static void bnx2x_stop_ptp(struct bnx2x *bp)
9271 /* Cancel PTP work queue. Should be done after the Tx queues are
9272 * drained to prevent additional scheduling.
9274 cancel_work_sync(&bp->ptp_task);
9276 if (bp->ptp_tx_skb) {
9277 dev_kfree_skb_any(bp->ptp_tx_skb);
9278 bp->ptp_tx_skb = NULL;
9281 /* Disable PTP in HW */
9282 bnx2x_disable_ptp(bp);
9284 DP(BNX2X_MSG_PTP, "PTP stop ended successfully\n");
9287 void bnx2x_chip_cleanup(struct bnx2x *bp, int unload_mode, bool keep_link)
9289 int port = BP_PORT(bp);
9292 struct bnx2x_mcast_ramrod_params rparam = {NULL};
9295 /* Wait until tx fastpath tasks complete */
9296 for_each_tx_queue(bp, i) {
9297 struct bnx2x_fastpath *fp = &bp->fp[i];
9299 for_each_cos_in_tx_queue(fp, cos)
9300 rc = bnx2x_clean_tx_queue(bp, fp->txdata_ptr[cos]);
9301 #ifdef BNX2X_STOP_ON_ERROR
9307 /* Give HW time to discard old tx messages */
9308 usleep_range(1000, 2000);
9310 /* Clean all ETH MACs */
9311 rc = bnx2x_del_all_macs(bp, &bp->sp_objs[0].mac_obj, BNX2X_ETH_MAC,
9314 BNX2X_ERR("Failed to delete all ETH macs: %d\n", rc);
9316 /* Clean up UC list */
9317 rc = bnx2x_del_all_macs(bp, &bp->sp_objs[0].mac_obj, BNX2X_UC_LIST_MAC,
9320 BNX2X_ERR("Failed to schedule DEL commands for UC MACs list: %d\n",
9324 if (!CHIP_IS_E1(bp))
9325 REG_WR(bp, NIG_REG_LLH0_FUNC_EN + port*8, 0);
9327 /* Set "drop all" (stop Rx).
9328 * We need to take a netif_addr_lock() here in order to prevent
9329 * a race between the completion code and this code.
9331 netif_addr_lock_bh(bp->dev);
9332 /* Schedule the rx_mode command */
9333 if (test_bit(BNX2X_FILTER_RX_MODE_PENDING, &bp->sp_state))
9334 set_bit(BNX2X_FILTER_RX_MODE_SCHED, &bp->sp_state);
9336 bnx2x_set_storm_rx_mode(bp);
9338 /* Cleanup multicast configuration */
9339 rparam.mcast_obj = &bp->mcast_obj;
9340 rc = bnx2x_config_mcast(bp, &rparam, BNX2X_MCAST_CMD_DEL);
9342 BNX2X_ERR("Failed to send DEL multicast command: %d\n", rc);
9344 netif_addr_unlock_bh(bp->dev);
9346 bnx2x_iov_chip_cleanup(bp);
9349 * Send the UNLOAD_REQUEST to the MCP. This will return if
9350 * this function should perform FUNC, PORT or COMMON HW
9353 reset_code = bnx2x_send_unload_req(bp, unload_mode);
9356 * (assumption: No Attention from MCP at this stage)
9357 * PMF probably in the middle of TX disable/enable transaction
9359 rc = bnx2x_func_wait_started(bp);
9361 BNX2X_ERR("bnx2x_func_wait_started failed\n");
9362 #ifdef BNX2X_STOP_ON_ERROR
9367 /* Close multi and leading connections
9368 * Completions for ramrods are collected in a synchronous way
9370 for_each_eth_queue(bp, i)
9371 if (bnx2x_stop_queue(bp, i))
9372 #ifdef BNX2X_STOP_ON_ERROR
9378 if (CNIC_LOADED(bp)) {
9379 for_each_cnic_queue(bp, i)
9380 if (bnx2x_stop_queue(bp, i))
9381 #ifdef BNX2X_STOP_ON_ERROR
9388 /* If SP settings didn't get completed so far - something
9389 * very wrong has happen.
9391 if (!bnx2x_wait_sp_comp(bp, ~0x0UL))
9392 BNX2X_ERR("Hmmm... Common slow path ramrods got stuck!\n");
9394 #ifndef BNX2X_STOP_ON_ERROR
9397 rc = bnx2x_func_stop(bp);
9399 BNX2X_ERR("Function stop failed!\n");
9400 #ifdef BNX2X_STOP_ON_ERROR
9405 /* stop_ptp should be after the Tx queues are drained to prevent
9406 * scheduling to the cancelled PTP work queue. It should also be after
9407 * function stop ramrod is sent, since as part of this ramrod FW access
9410 if (bp->flags & PTP_SUPPORTED)
9413 /* Disable HW interrupts, NAPI */
9414 bnx2x_netif_stop(bp, 1);
9415 /* Delete all NAPI objects */
9416 bnx2x_del_all_napi(bp);
9417 if (CNIC_LOADED(bp))
9418 bnx2x_del_all_napi_cnic(bp);
9423 /* Reset the chip */
9424 rc = bnx2x_reset_hw(bp, reset_code);
9426 BNX2X_ERR("HW_RESET failed\n");
9428 /* Report UNLOAD_DONE to MCP */
9429 bnx2x_send_unload_done(bp, keep_link);
9432 void bnx2x_disable_close_the_gate(struct bnx2x *bp)
9436 DP(NETIF_MSG_IFDOWN, "Disabling \"close the gates\"\n");
9438 if (CHIP_IS_E1(bp)) {
9439 int port = BP_PORT(bp);
9440 u32 addr = port ? MISC_REG_AEU_MASK_ATTN_FUNC_1 :
9441 MISC_REG_AEU_MASK_ATTN_FUNC_0;
9443 val = REG_RD(bp, addr);
9445 REG_WR(bp, addr, val);
9447 val = REG_RD(bp, MISC_REG_AEU_GENERAL_MASK);
9448 val &= ~(MISC_AEU_GENERAL_MASK_REG_AEU_PXP_CLOSE_MASK |
9449 MISC_AEU_GENERAL_MASK_REG_AEU_NIG_CLOSE_MASK);
9450 REG_WR(bp, MISC_REG_AEU_GENERAL_MASK, val);
9454 /* Close gates #2, #3 and #4: */
9455 static void bnx2x_set_234_gates(struct bnx2x *bp, bool close)
9459 /* Gates #2 and #4a are closed/opened for "not E1" only */
9460 if (!CHIP_IS_E1(bp)) {
9462 REG_WR(bp, PXP_REG_HST_DISCARD_DOORBELLS, !!close);
9464 REG_WR(bp, PXP_REG_HST_DISCARD_INTERNAL_WRITES, !!close);
9468 if (CHIP_IS_E1x(bp)) {
9469 /* Prevent interrupts from HC on both ports */
9470 val = REG_RD(bp, HC_REG_CONFIG_1);
9471 REG_WR(bp, HC_REG_CONFIG_1,
9472 (!close) ? (val | HC_CONFIG_1_REG_BLOCK_DISABLE_1) :
9473 (val & ~(u32)HC_CONFIG_1_REG_BLOCK_DISABLE_1));
9475 val = REG_RD(bp, HC_REG_CONFIG_0);
9476 REG_WR(bp, HC_REG_CONFIG_0,
9477 (!close) ? (val | HC_CONFIG_0_REG_BLOCK_DISABLE_0) :
9478 (val & ~(u32)HC_CONFIG_0_REG_BLOCK_DISABLE_0));
9480 /* Prevent incoming interrupts in IGU */
9481 val = REG_RD(bp, IGU_REG_BLOCK_CONFIGURATION);
9483 REG_WR(bp, IGU_REG_BLOCK_CONFIGURATION,
9485 (val | IGU_BLOCK_CONFIGURATION_REG_BLOCK_ENABLE) :
9486 (val & ~(u32)IGU_BLOCK_CONFIGURATION_REG_BLOCK_ENABLE));
9489 DP(NETIF_MSG_HW | NETIF_MSG_IFUP, "%s gates #2, #3 and #4\n",
9490 close ? "closing" : "opening");
9494 #define SHARED_MF_CLP_MAGIC 0x80000000 /* `magic' bit */
9496 static void bnx2x_clp_reset_prep(struct bnx2x *bp, u32 *magic_val)
9498 /* Do some magic... */
9499 u32 val = MF_CFG_RD(bp, shared_mf_config.clp_mb);
9500 *magic_val = val & SHARED_MF_CLP_MAGIC;
9501 MF_CFG_WR(bp, shared_mf_config.clp_mb, val | SHARED_MF_CLP_MAGIC);
9505 * bnx2x_clp_reset_done - restore the value of the `magic' bit.
9507 * @bp: driver handle
9508 * @magic_val: old value of the `magic' bit.
9510 static void bnx2x_clp_reset_done(struct bnx2x *bp, u32 magic_val)
9512 /* Restore the `magic' bit value... */
9513 u32 val = MF_CFG_RD(bp, shared_mf_config.clp_mb);
9514 MF_CFG_WR(bp, shared_mf_config.clp_mb,
9515 (val & (~SHARED_MF_CLP_MAGIC)) | magic_val);
9519 * bnx2x_reset_mcp_prep - prepare for MCP reset.
9521 * @bp: driver handle
9522 * @magic_val: old value of 'magic' bit.
9524 * Takes care of CLP configurations.
9526 static void bnx2x_reset_mcp_prep(struct bnx2x *bp, u32 *magic_val)
9529 u32 validity_offset;
9531 DP(NETIF_MSG_HW | NETIF_MSG_IFUP, "Starting\n");
9533 /* Set `magic' bit in order to save MF config */
9534 if (!CHIP_IS_E1(bp))
9535 bnx2x_clp_reset_prep(bp, magic_val);
9537 /* Get shmem offset */
9538 shmem = REG_RD(bp, MISC_REG_SHARED_MEM_ADDR);
9540 offsetof(struct shmem_region, validity_map[BP_PORT(bp)]);
9542 /* Clear validity map flags */
9544 REG_WR(bp, shmem + validity_offset, 0);
9547 #define MCP_TIMEOUT 5000 /* 5 seconds (in ms) */
9548 #define MCP_ONE_TIMEOUT 100 /* 100 ms */
9551 * bnx2x_mcp_wait_one - wait for MCP_ONE_TIMEOUT
9553 * @bp: driver handle
9555 static void bnx2x_mcp_wait_one(struct bnx2x *bp)
9557 /* special handling for emulation and FPGA,
9558 wait 10 times longer */
9559 if (CHIP_REV_IS_SLOW(bp))
9560 msleep(MCP_ONE_TIMEOUT*10);
9562 msleep(MCP_ONE_TIMEOUT);
9566 * initializes bp->common.shmem_base and waits for validity signature to appear
9568 static int bnx2x_init_shmem(struct bnx2x *bp)
9574 bp->common.shmem_base = REG_RD(bp, MISC_REG_SHARED_MEM_ADDR);
9575 if (bp->common.shmem_base) {
9576 val = SHMEM_RD(bp, validity_map[BP_PORT(bp)]);
9577 if (val & SHR_MEM_VALIDITY_MB)
9581 bnx2x_mcp_wait_one(bp);
9583 } while (cnt++ < (MCP_TIMEOUT / MCP_ONE_TIMEOUT));
9585 BNX2X_ERR("BAD MCP validity signature\n");
9590 static int bnx2x_reset_mcp_comp(struct bnx2x *bp, u32 magic_val)
9592 int rc = bnx2x_init_shmem(bp);
9594 /* Restore the `magic' bit value */
9595 if (!CHIP_IS_E1(bp))
9596 bnx2x_clp_reset_done(bp, magic_val);
9601 static void bnx2x_pxp_prep(struct bnx2x *bp)
9603 if (!CHIP_IS_E1(bp)) {
9604 REG_WR(bp, PXP2_REG_RD_START_INIT, 0);
9605 REG_WR(bp, PXP2_REG_RQ_RBC_DONE, 0);
9611 * Reset the whole chip except for:
9613 * - PCI Glue, PSWHST, PXP/PXP2 RF (all controlled by
9616 * - MISC (including AEU)
9620 static void bnx2x_process_kill_chip_reset(struct bnx2x *bp, bool global)
9622 u32 not_reset_mask1, reset_mask1, not_reset_mask2, reset_mask2;
9623 u32 global_bits2, stay_reset2;
9626 * Bits that have to be set in reset_mask2 if we want to reset 'global'
9627 * (per chip) blocks.
9630 MISC_REGISTERS_RESET_REG_2_RST_MCP_N_RESET_CMN_CPU |
9631 MISC_REGISTERS_RESET_REG_2_RST_MCP_N_RESET_CMN_CORE;
9633 /* Don't reset the following blocks.
9634 * Important: per port blocks (such as EMAC, BMAC, UMAC) can't be
9635 * reset, as in 4 port device they might still be owned
9636 * by the MCP (there is only one leader per path).
9639 MISC_REGISTERS_RESET_REG_1_RST_HC |
9640 MISC_REGISTERS_RESET_REG_1_RST_PXPV |
9641 MISC_REGISTERS_RESET_REG_1_RST_PXP;
9644 MISC_REGISTERS_RESET_REG_2_RST_PCI_MDIO |
9645 MISC_REGISTERS_RESET_REG_2_RST_EMAC0_HARD_CORE |
9646 MISC_REGISTERS_RESET_REG_2_RST_EMAC1_HARD_CORE |
9647 MISC_REGISTERS_RESET_REG_2_RST_MISC_CORE |
9648 MISC_REGISTERS_RESET_REG_2_RST_RBCN |
9649 MISC_REGISTERS_RESET_REG_2_RST_GRC |
9650 MISC_REGISTERS_RESET_REG_2_RST_MCP_N_RESET_REG_HARD_CORE |
9651 MISC_REGISTERS_RESET_REG_2_RST_MCP_N_HARD_CORE_RST_B |
9652 MISC_REGISTERS_RESET_REG_2_RST_ATC |
9653 MISC_REGISTERS_RESET_REG_2_PGLC |
9654 MISC_REGISTERS_RESET_REG_2_RST_BMAC0 |
9655 MISC_REGISTERS_RESET_REG_2_RST_BMAC1 |
9656 MISC_REGISTERS_RESET_REG_2_RST_EMAC0 |
9657 MISC_REGISTERS_RESET_REG_2_RST_EMAC1 |
9658 MISC_REGISTERS_RESET_REG_2_UMAC0 |
9659 MISC_REGISTERS_RESET_REG_2_UMAC1;
9662 * Keep the following blocks in reset:
9663 * - all xxMACs are handled by the bnx2x_link code.
9666 MISC_REGISTERS_RESET_REG_2_XMAC |
9667 MISC_REGISTERS_RESET_REG_2_XMAC_SOFT;
9669 /* Full reset masks according to the chip */
9670 reset_mask1 = 0xffffffff;
9673 reset_mask2 = 0xffff;
9674 else if (CHIP_IS_E1H(bp))
9675 reset_mask2 = 0x1ffff;
9676 else if (CHIP_IS_E2(bp))
9677 reset_mask2 = 0xfffff;
9678 else /* CHIP_IS_E3 */
9679 reset_mask2 = 0x3ffffff;
9681 /* Don't reset global blocks unless we need to */
9683 reset_mask2 &= ~global_bits2;
9686 * In case of attention in the QM, we need to reset PXP
9687 * (MISC_REGISTERS_RESET_REG_2_RST_PXP_RQ_RD_WR) before QM
9688 * because otherwise QM reset would release 'close the gates' shortly
9689 * before resetting the PXP, then the PSWRQ would send a write
9690 * request to PGLUE. Then when PXP is reset, PGLUE would try to
9691 * read the payload data from PSWWR, but PSWWR would not
9692 * respond. The write queue in PGLUE would stuck, dmae commands
9693 * would not return. Therefore it's important to reset the second
9694 * reset register (containing the
9695 * MISC_REGISTERS_RESET_REG_2_RST_PXP_RQ_RD_WR bit) before the
9696 * first one (containing the MISC_REGISTERS_RESET_REG_1_RST_QM
9699 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR,
9700 reset_mask2 & (~not_reset_mask2));
9702 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_CLEAR,
9703 reset_mask1 & (~not_reset_mask1));
9708 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_SET,
9709 reset_mask2 & (~stay_reset2));
9714 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_SET, reset_mask1);
9719 * bnx2x_er_poll_igu_vq - poll for pending writes bit.
9720 * It should get cleared in no more than 1s.
9722 * @bp: driver handle
9724 * It should get cleared in no more than 1s. Returns 0 if
9725 * pending writes bit gets cleared.
9727 static int bnx2x_er_poll_igu_vq(struct bnx2x *bp)
9733 pend_bits = REG_RD(bp, IGU_REG_PENDING_BITS_STATUS);
9738 usleep_range(1000, 2000);
9739 } while (cnt-- > 0);
9742 BNX2X_ERR("Still pending IGU requests pend_bits=%x!\n",
9750 static int bnx2x_process_kill(struct bnx2x *bp, bool global)
9754 u32 sr_cnt, blk_cnt, port_is_idle_0, port_is_idle_1, pgl_exp_rom2;
9757 /* Empty the Tetris buffer, wait for 1s */
9759 sr_cnt = REG_RD(bp, PXP2_REG_RD_SR_CNT);
9760 blk_cnt = REG_RD(bp, PXP2_REG_RD_BLK_CNT);
9761 port_is_idle_0 = REG_RD(bp, PXP2_REG_RD_PORT_IS_IDLE_0);
9762 port_is_idle_1 = REG_RD(bp, PXP2_REG_RD_PORT_IS_IDLE_1);
9763 pgl_exp_rom2 = REG_RD(bp, PXP2_REG_PGL_EXP_ROM2);
9765 tags_63_32 = REG_RD(bp, PGLUE_B_REG_TAGS_63_32);
9767 if ((sr_cnt == 0x7e) && (blk_cnt == 0xa0) &&
9768 ((port_is_idle_0 & 0x1) == 0x1) &&
9769 ((port_is_idle_1 & 0x1) == 0x1) &&
9770 (pgl_exp_rom2 == 0xffffffff) &&
9771 (!CHIP_IS_E3(bp) || (tags_63_32 == 0xffffffff)))
9773 usleep_range(1000, 2000);
9774 } while (cnt-- > 0);
9777 BNX2X_ERR("Tetris buffer didn't get empty or there are still outstanding read requests after 1s!\n");
9778 BNX2X_ERR("sr_cnt=0x%08x, blk_cnt=0x%08x, port_is_idle_0=0x%08x, port_is_idle_1=0x%08x, pgl_exp_rom2=0x%08x\n",
9779 sr_cnt, blk_cnt, port_is_idle_0, port_is_idle_1,
9786 /* Close gates #2, #3 and #4 */
9787 bnx2x_set_234_gates(bp, true);
9789 /* Poll for IGU VQs for 57712 and newer chips */
9790 if (!CHIP_IS_E1x(bp) && bnx2x_er_poll_igu_vq(bp))
9793 /* TBD: Indicate that "process kill" is in progress to MCP */
9795 /* Clear "unprepared" bit */
9796 REG_WR(bp, MISC_REG_UNPREPARED, 0);
9799 /* Make sure all is written to the chip before the reset */
9802 /* Wait for 1ms to empty GLUE and PCI-E core queues,
9803 * PSWHST, GRC and PSWRD Tetris buffer.
9805 usleep_range(1000, 2000);
9807 /* Prepare to chip reset: */
9810 bnx2x_reset_mcp_prep(bp, &val);
9816 /* reset the chip */
9817 bnx2x_process_kill_chip_reset(bp, global);
9820 /* clear errors in PGB */
9821 if (!CHIP_IS_E1x(bp))
9822 REG_WR(bp, PGLUE_B_REG_LATCHED_ERRORS_CLR, 0x7f);
9824 /* Recover after reset: */
9826 if (global && bnx2x_reset_mcp_comp(bp, val))
9829 /* TBD: Add resetting the NO_MCP mode DB here */
9831 /* Open the gates #2, #3 and #4 */
9832 bnx2x_set_234_gates(bp, false);
9834 /* TBD: IGU/AEU preparation bring back the AEU/IGU to a
9835 * reset state, re-enable attentions. */
9840 static int bnx2x_leader_reset(struct bnx2x *bp)
9843 bool global = bnx2x_reset_is_global(bp);
9846 /* if not going to reset MCP - load "fake" driver to reset HW while
9847 * driver is owner of the HW
9849 if (!global && !BP_NOMCP(bp)) {
9850 load_code = bnx2x_fw_command(bp, DRV_MSG_CODE_LOAD_REQ,
9851 DRV_MSG_CODE_LOAD_REQ_WITH_LFA);
9853 BNX2X_ERR("MCP response failure, aborting\n");
9855 goto exit_leader_reset;
9857 if ((load_code != FW_MSG_CODE_DRV_LOAD_COMMON_CHIP) &&
9858 (load_code != FW_MSG_CODE_DRV_LOAD_COMMON)) {
9859 BNX2X_ERR("MCP unexpected resp, aborting\n");
9861 goto exit_leader_reset2;
9863 load_code = bnx2x_fw_command(bp, DRV_MSG_CODE_LOAD_DONE, 0);
9865 BNX2X_ERR("MCP response failure, aborting\n");
9867 goto exit_leader_reset2;
9871 /* Try to recover after the failure */
9872 if (bnx2x_process_kill(bp, global)) {
9873 BNX2X_ERR("Something bad had happen on engine %d! Aii!\n",
9876 goto exit_leader_reset2;
9880 * Clear RESET_IN_PROGRES and RESET_GLOBAL bits and update the driver
9883 bnx2x_set_reset_done(bp);
9885 bnx2x_clear_reset_global(bp);
9888 /* unload "fake driver" if it was loaded */
9889 if (!global && !BP_NOMCP(bp)) {
9890 bnx2x_fw_command(bp, DRV_MSG_CODE_UNLOAD_REQ_WOL_MCP, 0);
9891 bnx2x_fw_command(bp, DRV_MSG_CODE_UNLOAD_DONE, 0);
9895 bnx2x_release_leader_lock(bp);
9900 static void bnx2x_recovery_failed(struct bnx2x *bp)
9902 netdev_err(bp->dev, "Recovery has failed. Power cycle is needed.\n");
9904 /* Disconnect this device */
9905 netif_device_detach(bp->dev);
9908 * Block ifup for all function on this engine until "process kill"
9911 bnx2x_set_reset_in_progress(bp);
9913 /* Shut down the power */
9914 bnx2x_set_power_state(bp, PCI_D3hot);
9916 bp->recovery_state = BNX2X_RECOVERY_FAILED;
9922 * Assumption: runs under rtnl lock. This together with the fact
9923 * that it's called only from bnx2x_sp_rtnl() ensure that it
9924 * will never be called when netif_running(bp->dev) is false.
9926 static void bnx2x_parity_recover(struct bnx2x *bp)
9928 bool global = false;
9929 u32 error_recovered, error_unrecovered;
9932 DP(NETIF_MSG_HW, "Handling parity\n");
9934 switch (bp->recovery_state) {
9935 case BNX2X_RECOVERY_INIT:
9936 DP(NETIF_MSG_HW, "State is BNX2X_RECOVERY_INIT\n");
9937 is_parity = bnx2x_chk_parity_attn(bp, &global, false);
9938 WARN_ON(!is_parity);
9940 /* Try to get a LEADER_LOCK HW lock */
9941 if (bnx2x_trylock_leader_lock(bp)) {
9942 bnx2x_set_reset_in_progress(bp);
9944 * Check if there is a global attention and if
9945 * there was a global attention, set the global
9950 bnx2x_set_reset_global(bp);
9955 /* Stop the driver */
9956 /* If interface has been removed - break */
9957 if (bnx2x_nic_unload(bp, UNLOAD_RECOVERY, false))
9960 bp->recovery_state = BNX2X_RECOVERY_WAIT;
9962 /* Ensure "is_leader", MCP command sequence and
9963 * "recovery_state" update values are seen on other
9969 case BNX2X_RECOVERY_WAIT:
9970 DP(NETIF_MSG_HW, "State is BNX2X_RECOVERY_WAIT\n");
9971 if (bp->is_leader) {
9972 int other_engine = BP_PATH(bp) ? 0 : 1;
9973 bool other_load_status =
9974 bnx2x_get_load_status(bp, other_engine);
9976 bnx2x_get_load_status(bp, BP_PATH(bp));
9977 global = bnx2x_reset_is_global(bp);
9980 * In case of a parity in a global block, let
9981 * the first leader that performs a
9982 * leader_reset() reset the global blocks in
9983 * order to clear global attentions. Otherwise
9984 * the gates will remain closed for that
9988 (global && other_load_status)) {
9989 /* Wait until all other functions get
9992 schedule_delayed_work(&bp->sp_rtnl_task,
9996 /* If all other functions got down -
9997 * try to bring the chip back to
9998 * normal. In any case it's an exit
9999 * point for a leader.
10001 if (bnx2x_leader_reset(bp)) {
10002 bnx2x_recovery_failed(bp);
10006 /* If we are here, means that the
10007 * leader has succeeded and doesn't
10008 * want to be a leader any more. Try
10009 * to continue as a none-leader.
10013 } else { /* non-leader */
10014 if (!bnx2x_reset_is_done(bp, BP_PATH(bp))) {
10015 /* Try to get a LEADER_LOCK HW lock as
10016 * long as a former leader may have
10017 * been unloaded by the user or
10018 * released a leadership by another
10021 if (bnx2x_trylock_leader_lock(bp)) {
10022 /* I'm a leader now! Restart a
10029 schedule_delayed_work(&bp->sp_rtnl_task,
10035 * If there was a global attention, wait
10036 * for it to be cleared.
10038 if (bnx2x_reset_is_global(bp)) {
10039 schedule_delayed_work(
10046 bp->eth_stats.recoverable_error;
10047 error_unrecovered =
10048 bp->eth_stats.unrecoverable_error;
10049 bp->recovery_state =
10050 BNX2X_RECOVERY_NIC_LOADING;
10051 if (bnx2x_nic_load(bp, LOAD_NORMAL)) {
10052 error_unrecovered++;
10053 netdev_err(bp->dev,
10054 "Recovery failed. Power cycle needed\n");
10055 /* Disconnect this device */
10056 netif_device_detach(bp->dev);
10057 /* Shut down the power */
10058 bnx2x_set_power_state(
10062 bp->recovery_state =
10063 BNX2X_RECOVERY_DONE;
10067 bp->eth_stats.recoverable_error =
10069 bp->eth_stats.unrecoverable_error =
10081 #ifdef CONFIG_BNX2X_VXLAN
10082 static int bnx2x_vxlan_port_update(struct bnx2x *bp, u16 port)
10084 struct bnx2x_func_switch_update_params *switch_update_params;
10085 struct bnx2x_func_state_params func_params = {NULL};
10088 switch_update_params = &func_params.params.switch_update;
10090 /* Prepare parameters for function state transitions */
10091 __set_bit(RAMROD_COMP_WAIT, &func_params.ramrod_flags);
10092 __set_bit(RAMROD_RETRY, &func_params.ramrod_flags);
10094 func_params.f_obj = &bp->func_obj;
10095 func_params.cmd = BNX2X_F_CMD_SWITCH_UPDATE;
10097 /* Function parameters */
10098 __set_bit(BNX2X_F_UPDATE_TUNNEL_CFG_CHNG,
10099 &switch_update_params->changes);
10100 switch_update_params->vxlan_dst_port = port;
10101 rc = bnx2x_func_state_change(bp, &func_params);
10103 BNX2X_ERR("failed to change vxlan dst port to %d (rc = 0x%x)\n",
10108 static void __bnx2x_add_vxlan_port(struct bnx2x *bp, u16 port)
10110 if (!netif_running(bp->dev))
10113 if (bp->vxlan_dst_port || !IS_PF(bp)) {
10114 DP(BNX2X_MSG_SP, "Vxlan destination port limit reached\n");
10118 bp->vxlan_dst_port = port;
10119 bnx2x_schedule_sp_rtnl(bp, BNX2X_SP_RTNL_ADD_VXLAN_PORT, 0);
10122 static void bnx2x_add_vxlan_port(struct net_device *netdev,
10123 sa_family_t sa_family, __be16 port)
10125 struct bnx2x *bp = netdev_priv(netdev);
10126 u16 t_port = ntohs(port);
10128 __bnx2x_add_vxlan_port(bp, t_port);
10131 static void __bnx2x_del_vxlan_port(struct bnx2x *bp, u16 port)
10133 if (!bp->vxlan_dst_port || bp->vxlan_dst_port != port || !IS_PF(bp)) {
10134 DP(BNX2X_MSG_SP, "Invalid vxlan port\n");
10138 if (netif_running(bp->dev)) {
10139 bnx2x_schedule_sp_rtnl(bp, BNX2X_SP_RTNL_DEL_VXLAN_PORT, 0);
10141 bp->vxlan_dst_port = 0;
10142 netdev_info(bp->dev, "Deleted vxlan dest port %d", port);
10146 static void bnx2x_del_vxlan_port(struct net_device *netdev,
10147 sa_family_t sa_family, __be16 port)
10149 struct bnx2x *bp = netdev_priv(netdev);
10150 u16 t_port = ntohs(port);
10152 __bnx2x_del_vxlan_port(bp, t_port);
10156 static int bnx2x_close(struct net_device *dev);
10158 /* bnx2x_nic_unload() flushes the bnx2x_wq, thus reset task is
10159 * scheduled on a general queue in order to prevent a dead lock.
10161 static void bnx2x_sp_rtnl_task(struct work_struct *work)
10163 struct bnx2x *bp = container_of(work, struct bnx2x, sp_rtnl_task.work);
10164 #ifdef CONFIG_BNX2X_VXLAN
10170 if (!netif_running(bp->dev)) {
10175 if (unlikely(bp->recovery_state != BNX2X_RECOVERY_DONE)) {
10176 #ifdef BNX2X_STOP_ON_ERROR
10177 BNX2X_ERR("recovery flow called but STOP_ON_ERROR defined so reset not done to allow debug dump,\n"
10178 "you will need to reboot when done\n");
10179 goto sp_rtnl_not_reset;
10182 * Clear all pending SP commands as we are going to reset the
10185 bp->sp_rtnl_state = 0;
10188 bnx2x_parity_recover(bp);
10194 if (test_and_clear_bit(BNX2X_SP_RTNL_TX_TIMEOUT, &bp->sp_rtnl_state)) {
10195 #ifdef BNX2X_STOP_ON_ERROR
10196 BNX2X_ERR("recovery flow called but STOP_ON_ERROR defined so reset not done to allow debug dump,\n"
10197 "you will need to reboot when done\n");
10198 goto sp_rtnl_not_reset;
10202 * Clear all pending SP commands as we are going to reset the
10205 bp->sp_rtnl_state = 0;
10208 bnx2x_nic_unload(bp, UNLOAD_NORMAL, true);
10209 bnx2x_nic_load(bp, LOAD_NORMAL);
10214 #ifdef BNX2X_STOP_ON_ERROR
10217 if (test_and_clear_bit(BNX2X_SP_RTNL_SETUP_TC, &bp->sp_rtnl_state))
10218 bnx2x_setup_tc(bp->dev, bp->dcbx_port_params.ets.num_of_cos);
10219 if (test_and_clear_bit(BNX2X_SP_RTNL_AFEX_F_UPDATE, &bp->sp_rtnl_state))
10220 bnx2x_after_function_update(bp);
10222 * in case of fan failure we need to reset id if the "stop on error"
10223 * debug flag is set, since we trying to prevent permanent overheating
10226 if (test_and_clear_bit(BNX2X_SP_RTNL_FAN_FAILURE, &bp->sp_rtnl_state)) {
10227 DP(NETIF_MSG_HW, "fan failure detected. Unloading driver\n");
10228 netif_device_detach(bp->dev);
10229 bnx2x_close(bp->dev);
10234 if (test_and_clear_bit(BNX2X_SP_RTNL_VFPF_MCAST, &bp->sp_rtnl_state)) {
10236 "sending set mcast vf pf channel message from rtnl sp-task\n");
10237 bnx2x_vfpf_set_mcast(bp->dev);
10239 if (test_and_clear_bit(BNX2X_SP_RTNL_VFPF_CHANNEL_DOWN,
10240 &bp->sp_rtnl_state)){
10241 if (!test_bit(__LINK_STATE_NOCARRIER, &bp->dev->state)) {
10242 bnx2x_tx_disable(bp);
10243 BNX2X_ERR("PF indicated channel is not servicable anymore. This means this VF device is no longer operational\n");
10247 if (test_and_clear_bit(BNX2X_SP_RTNL_RX_MODE, &bp->sp_rtnl_state)) {
10248 DP(BNX2X_MSG_SP, "Handling Rx Mode setting\n");
10249 bnx2x_set_rx_mode_inner(bp);
10252 if (test_and_clear_bit(BNX2X_SP_RTNL_HYPERVISOR_VLAN,
10253 &bp->sp_rtnl_state))
10254 bnx2x_pf_set_vfs_vlan(bp);
10256 if (test_and_clear_bit(BNX2X_SP_RTNL_TX_STOP, &bp->sp_rtnl_state)) {
10257 bnx2x_dcbx_stop_hw_tx(bp);
10258 bnx2x_dcbx_resume_hw_tx(bp);
10261 if (test_and_clear_bit(BNX2X_SP_RTNL_GET_DRV_VERSION,
10262 &bp->sp_rtnl_state))
10263 bnx2x_update_mng_version(bp);
10265 #ifdef CONFIG_BNX2X_VXLAN
10266 port = bp->vxlan_dst_port;
10267 if (test_and_clear_bit(BNX2X_SP_RTNL_ADD_VXLAN_PORT,
10268 &bp->sp_rtnl_state)) {
10269 if (!bnx2x_vxlan_port_update(bp, port))
10270 netdev_info(bp->dev, "Added vxlan dest port %d", port);
10272 bp->vxlan_dst_port = 0;
10275 if (test_and_clear_bit(BNX2X_SP_RTNL_DEL_VXLAN_PORT,
10276 &bp->sp_rtnl_state)) {
10277 if (!bnx2x_vxlan_port_update(bp, 0)) {
10278 netdev_info(bp->dev,
10279 "Deleted vxlan dest port %d", port);
10280 bp->vxlan_dst_port = 0;
10281 vxlan_get_rx_port(bp->dev);
10286 /* work which needs rtnl lock not-taken (as it takes the lock itself and
10287 * can be called from other contexts as well)
10291 /* enable SR-IOV if applicable */
10292 if (IS_SRIOV(bp) && test_and_clear_bit(BNX2X_SP_RTNL_ENABLE_SRIOV,
10293 &bp->sp_rtnl_state)) {
10294 bnx2x_disable_sriov(bp);
10295 bnx2x_enable_sriov(bp);
10299 static void bnx2x_period_task(struct work_struct *work)
10301 struct bnx2x *bp = container_of(work, struct bnx2x, period_task.work);
10303 if (!netif_running(bp->dev))
10304 goto period_task_exit;
10306 if (CHIP_REV_IS_SLOW(bp)) {
10307 BNX2X_ERR("period task called on emulation, ignoring\n");
10308 goto period_task_exit;
10311 bnx2x_acquire_phy_lock(bp);
10313 * The barrier is needed to ensure the ordering between the writing to
10314 * the bp->port.pmf in the bnx2x_nic_load() or bnx2x_pmf_update() and
10315 * the reading here.
10318 if (bp->port.pmf) {
10319 bnx2x_period_func(&bp->link_params, &bp->link_vars);
10321 /* Re-queue task in 1 sec */
10322 queue_delayed_work(bnx2x_wq, &bp->period_task, 1*HZ);
10325 bnx2x_release_phy_lock(bp);
10331 * Init service functions
10334 static u32 bnx2x_get_pretend_reg(struct bnx2x *bp)
10336 u32 base = PXP2_REG_PGL_PRETEND_FUNC_F0;
10337 u32 stride = PXP2_REG_PGL_PRETEND_FUNC_F1 - base;
10338 return base + (BP_ABS_FUNC(bp)) * stride;
10341 static bool bnx2x_prev_unload_close_umac(struct bnx2x *bp,
10342 u8 port, u32 reset_reg,
10343 struct bnx2x_mac_vals *vals)
10345 u32 mask = MISC_REGISTERS_RESET_REG_2_UMAC0 << port;
10348 if (!(mask & reset_reg))
10351 BNX2X_DEV_INFO("Disable umac Rx %02x\n", port);
10352 base_addr = port ? GRCBASE_UMAC1 : GRCBASE_UMAC0;
10353 vals->umac_addr[port] = base_addr + UMAC_REG_COMMAND_CONFIG;
10354 vals->umac_val[port] = REG_RD(bp, vals->umac_addr[port]);
10355 REG_WR(bp, vals->umac_addr[port], 0);
10360 static void bnx2x_prev_unload_close_mac(struct bnx2x *bp,
10361 struct bnx2x_mac_vals *vals)
10363 u32 val, base_addr, offset, mask, reset_reg;
10364 bool mac_stopped = false;
10365 u8 port = BP_PORT(bp);
10367 /* reset addresses as they also mark which values were changed */
10368 memset(vals, 0, sizeof(*vals));
10370 reset_reg = REG_RD(bp, MISC_REG_RESET_REG_2);
10372 if (!CHIP_IS_E3(bp)) {
10373 val = REG_RD(bp, NIG_REG_BMAC0_REGS_OUT_EN + port * 4);
10374 mask = MISC_REGISTERS_RESET_REG_2_RST_BMAC0 << port;
10375 if ((mask & reset_reg) && val) {
10377 BNX2X_DEV_INFO("Disable bmac Rx\n");
10378 base_addr = BP_PORT(bp) ? NIG_REG_INGRESS_BMAC1_MEM
10379 : NIG_REG_INGRESS_BMAC0_MEM;
10380 offset = CHIP_IS_E2(bp) ? BIGMAC2_REGISTER_BMAC_CONTROL
10381 : BIGMAC_REGISTER_BMAC_CONTROL;
10384 * use rd/wr since we cannot use dmae. This is safe
10385 * since MCP won't access the bus due to the request
10386 * to unload, and no function on the path can be
10387 * loaded at this time.
10389 wb_data[0] = REG_RD(bp, base_addr + offset);
10390 wb_data[1] = REG_RD(bp, base_addr + offset + 0x4);
10391 vals->bmac_addr = base_addr + offset;
10392 vals->bmac_val[0] = wb_data[0];
10393 vals->bmac_val[1] = wb_data[1];
10394 wb_data[0] &= ~BMAC_CONTROL_RX_ENABLE;
10395 REG_WR(bp, vals->bmac_addr, wb_data[0]);
10396 REG_WR(bp, vals->bmac_addr + 0x4, wb_data[1]);
10398 BNX2X_DEV_INFO("Disable emac Rx\n");
10399 vals->emac_addr = NIG_REG_NIG_EMAC0_EN + BP_PORT(bp)*4;
10400 vals->emac_val = REG_RD(bp, vals->emac_addr);
10401 REG_WR(bp, vals->emac_addr, 0);
10402 mac_stopped = true;
10404 if (reset_reg & MISC_REGISTERS_RESET_REG_2_XMAC) {
10405 BNX2X_DEV_INFO("Disable xmac Rx\n");
10406 base_addr = BP_PORT(bp) ? GRCBASE_XMAC1 : GRCBASE_XMAC0;
10407 val = REG_RD(bp, base_addr + XMAC_REG_PFC_CTRL_HI);
10408 REG_WR(bp, base_addr + XMAC_REG_PFC_CTRL_HI,
10410 REG_WR(bp, base_addr + XMAC_REG_PFC_CTRL_HI,
10412 vals->xmac_addr = base_addr + XMAC_REG_CTRL;
10413 vals->xmac_val = REG_RD(bp, vals->xmac_addr);
10414 REG_WR(bp, vals->xmac_addr, 0);
10415 mac_stopped = true;
10418 mac_stopped |= bnx2x_prev_unload_close_umac(bp, 0,
10420 mac_stopped |= bnx2x_prev_unload_close_umac(bp, 1,
10428 #define BNX2X_PREV_UNDI_PROD_ADDR(p) (BAR_TSTRORM_INTMEM + 0x1508 + ((p) << 4))
10429 #define BNX2X_PREV_UNDI_PROD_ADDR_H(f) (BAR_TSTRORM_INTMEM + \
10430 0x1848 + ((f) << 4))
10431 #define BNX2X_PREV_UNDI_RCQ(val) ((val) & 0xffff)
10432 #define BNX2X_PREV_UNDI_BD(val) ((val) >> 16 & 0xffff)
10433 #define BNX2X_PREV_UNDI_PROD(rcq, bd) ((bd) << 16 | (rcq))
10435 #define BCM_5710_UNDI_FW_MF_MAJOR (0x07)
10436 #define BCM_5710_UNDI_FW_MF_MINOR (0x08)
10437 #define BCM_5710_UNDI_FW_MF_VERS (0x05)
10439 static bool bnx2x_prev_is_after_undi(struct bnx2x *bp)
10441 /* UNDI marks its presence in DORQ -
10442 * it initializes CID offset for normal bell to 0x7
10444 if (!(REG_RD(bp, MISC_REG_RESET_REG_1) &
10445 MISC_REGISTERS_RESET_REG_1_RST_DORQ))
10448 if (REG_RD(bp, DORQ_REG_NORM_CID_OFST) == 0x7) {
10449 BNX2X_DEV_INFO("UNDI previously loaded\n");
10456 static void bnx2x_prev_unload_undi_inc(struct bnx2x *bp, u8 inc)
10461 if (BP_FUNC(bp) < 2)
10462 addr = BNX2X_PREV_UNDI_PROD_ADDR(BP_PORT(bp));
10464 addr = BNX2X_PREV_UNDI_PROD_ADDR_H(BP_FUNC(bp) - 2);
10466 tmp_reg = REG_RD(bp, addr);
10467 rcq = BNX2X_PREV_UNDI_RCQ(tmp_reg) + inc;
10468 bd = BNX2X_PREV_UNDI_BD(tmp_reg) + inc;
10470 tmp_reg = BNX2X_PREV_UNDI_PROD(rcq, bd);
10471 REG_WR(bp, addr, tmp_reg);
10473 BNX2X_DEV_INFO("UNDI producer [%d/%d][%08x] rings bd -> 0x%04x, rcq -> 0x%04x\n",
10474 BP_PORT(bp), BP_FUNC(bp), addr, bd, rcq);
10477 static int bnx2x_prev_mcp_done(struct bnx2x *bp)
10479 u32 rc = bnx2x_fw_command(bp, DRV_MSG_CODE_UNLOAD_DONE,
10480 DRV_MSG_CODE_UNLOAD_SKIP_LINK_RESET);
10482 BNX2X_ERR("MCP response failure, aborting\n");
10489 static struct bnx2x_prev_path_list *
10490 bnx2x_prev_path_get_entry(struct bnx2x *bp)
10492 struct bnx2x_prev_path_list *tmp_list;
10494 list_for_each_entry(tmp_list, &bnx2x_prev_list, list)
10495 if (PCI_SLOT(bp->pdev->devfn) == tmp_list->slot &&
10496 bp->pdev->bus->number == tmp_list->bus &&
10497 BP_PATH(bp) == tmp_list->path)
10503 static int bnx2x_prev_path_mark_eeh(struct bnx2x *bp)
10505 struct bnx2x_prev_path_list *tmp_list;
10508 rc = down_interruptible(&bnx2x_prev_sem);
10510 BNX2X_ERR("Received %d when tried to take lock\n", rc);
10514 tmp_list = bnx2x_prev_path_get_entry(bp);
10519 BNX2X_ERR("path %d: Entry does not exist for eeh; Flow occurs before initial insmod is over ?\n",
10523 up(&bnx2x_prev_sem);
10528 static bool bnx2x_prev_is_path_marked(struct bnx2x *bp)
10530 struct bnx2x_prev_path_list *tmp_list;
10533 if (down_trylock(&bnx2x_prev_sem))
10536 tmp_list = bnx2x_prev_path_get_entry(bp);
10538 if (tmp_list->aer) {
10539 DP(NETIF_MSG_HW, "Path %d was marked by AER\n",
10543 BNX2X_DEV_INFO("Path %d was already cleaned from previous drivers\n",
10548 up(&bnx2x_prev_sem);
10553 bool bnx2x_port_after_undi(struct bnx2x *bp)
10555 struct bnx2x_prev_path_list *entry;
10558 down(&bnx2x_prev_sem);
10560 entry = bnx2x_prev_path_get_entry(bp);
10561 val = !!(entry && (entry->undi & (1 << BP_PORT(bp))));
10563 up(&bnx2x_prev_sem);
10568 static int bnx2x_prev_mark_path(struct bnx2x *bp, bool after_undi)
10570 struct bnx2x_prev_path_list *tmp_list;
10573 rc = down_interruptible(&bnx2x_prev_sem);
10575 BNX2X_ERR("Received %d when tried to take lock\n", rc);
10579 /* Check whether the entry for this path already exists */
10580 tmp_list = bnx2x_prev_path_get_entry(bp);
10582 if (!tmp_list->aer) {
10583 BNX2X_ERR("Re-Marking the path.\n");
10585 DP(NETIF_MSG_HW, "Removing AER indication from path %d\n",
10589 up(&bnx2x_prev_sem);
10592 up(&bnx2x_prev_sem);
10594 /* Create an entry for this path and add it */
10595 tmp_list = kmalloc(sizeof(struct bnx2x_prev_path_list), GFP_KERNEL);
10597 BNX2X_ERR("Failed to allocate 'bnx2x_prev_path_list'\n");
10601 tmp_list->bus = bp->pdev->bus->number;
10602 tmp_list->slot = PCI_SLOT(bp->pdev->devfn);
10603 tmp_list->path = BP_PATH(bp);
10605 tmp_list->undi = after_undi ? (1 << BP_PORT(bp)) : 0;
10607 rc = down_interruptible(&bnx2x_prev_sem);
10609 BNX2X_ERR("Received %d when tried to take lock\n", rc);
10612 DP(NETIF_MSG_HW, "Marked path [%d] - finished previous unload\n",
10614 list_add(&tmp_list->list, &bnx2x_prev_list);
10615 up(&bnx2x_prev_sem);
10621 static int bnx2x_do_flr(struct bnx2x *bp)
10623 struct pci_dev *dev = bp->pdev;
10625 if (CHIP_IS_E1x(bp)) {
10626 BNX2X_DEV_INFO("FLR not supported in E1/E1H\n");
10630 /* only bootcode REQ_BC_VER_4_INITIATE_FLR and onwards support flr */
10631 if (bp->common.bc_ver < REQ_BC_VER_4_INITIATE_FLR) {
10632 BNX2X_ERR("FLR not supported by BC_VER: 0x%x\n",
10633 bp->common.bc_ver);
10637 if (!pci_wait_for_pending_transaction(dev))
10638 dev_err(&dev->dev, "transaction is not cleared; proceeding with reset anyway\n");
10640 BNX2X_DEV_INFO("Initiating FLR\n");
10641 bnx2x_fw_command(bp, DRV_MSG_CODE_INITIATE_FLR, 0);
10646 static int bnx2x_prev_unload_uncommon(struct bnx2x *bp)
10650 BNX2X_DEV_INFO("Uncommon unload Flow\n");
10652 /* Test if previous unload process was already finished for this path */
10653 if (bnx2x_prev_is_path_marked(bp))
10654 return bnx2x_prev_mcp_done(bp);
10656 BNX2X_DEV_INFO("Path is unmarked\n");
10658 /* Cannot proceed with FLR if UNDI is loaded, since FW does not match */
10659 if (bnx2x_prev_is_after_undi(bp))
10662 /* If function has FLR capabilities, and existing FW version matches
10663 * the one required, then FLR will be sufficient to clean any residue
10664 * left by previous driver
10666 rc = bnx2x_compare_fw_ver(bp, FW_MSG_CODE_DRV_LOAD_FUNCTION, false);
10669 /* fw version is good */
10670 BNX2X_DEV_INFO("FW version matches our own. Attempting FLR\n");
10671 rc = bnx2x_do_flr(bp);
10675 /* FLR was performed */
10676 BNX2X_DEV_INFO("FLR successful\n");
10680 BNX2X_DEV_INFO("Could not FLR\n");
10683 /* Close the MCP request, return failure*/
10684 rc = bnx2x_prev_mcp_done(bp);
10686 rc = BNX2X_PREV_WAIT_NEEDED;
10691 static int bnx2x_prev_unload_common(struct bnx2x *bp)
10693 u32 reset_reg, tmp_reg = 0, rc;
10694 bool prev_undi = false;
10695 struct bnx2x_mac_vals mac_vals;
10697 /* It is possible a previous function received 'common' answer,
10698 * but hasn't loaded yet, therefore creating a scenario of
10699 * multiple functions receiving 'common' on the same path.
10701 BNX2X_DEV_INFO("Common unload Flow\n");
10703 memset(&mac_vals, 0, sizeof(mac_vals));
10705 if (bnx2x_prev_is_path_marked(bp))
10706 return bnx2x_prev_mcp_done(bp);
10708 reset_reg = REG_RD(bp, MISC_REG_RESET_REG_1);
10710 /* Reset should be performed after BRB is emptied */
10711 if (reset_reg & MISC_REGISTERS_RESET_REG_1_RST_BRB1) {
10712 u32 timer_count = 1000;
10714 /* Close the MAC Rx to prevent BRB from filling up */
10715 bnx2x_prev_unload_close_mac(bp, &mac_vals);
10717 /* close LLH filters for both ports towards the BRB */
10718 bnx2x_set_rx_filter(&bp->link_params, 0);
10719 bp->link_params.port ^= 1;
10720 bnx2x_set_rx_filter(&bp->link_params, 0);
10721 bp->link_params.port ^= 1;
10723 /* Check if the UNDI driver was previously loaded */
10724 if (bnx2x_prev_is_after_undi(bp)) {
10726 /* clear the UNDI indication */
10727 REG_WR(bp, DORQ_REG_NORM_CID_OFST, 0);
10728 /* clear possible idle check errors */
10729 REG_RD(bp, NIG_REG_NIG_INT_STS_CLR_0);
10731 if (!CHIP_IS_E1x(bp))
10732 /* block FW from writing to host */
10733 REG_WR(bp, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, 0);
10735 /* wait until BRB is empty */
10736 tmp_reg = REG_RD(bp, BRB1_REG_NUM_OF_FULL_BLOCKS);
10737 while (timer_count) {
10738 u32 prev_brb = tmp_reg;
10740 tmp_reg = REG_RD(bp, BRB1_REG_NUM_OF_FULL_BLOCKS);
10744 BNX2X_DEV_INFO("BRB still has 0x%08x\n", tmp_reg);
10746 /* reset timer as long as BRB actually gets emptied */
10747 if (prev_brb > tmp_reg)
10748 timer_count = 1000;
10752 /* If UNDI resides in memory, manually increment it */
10754 bnx2x_prev_unload_undi_inc(bp, 1);
10760 BNX2X_ERR("Failed to empty BRB, hope for the best\n");
10763 /* No packets are in the pipeline, path is ready for reset */
10764 bnx2x_reset_common(bp);
10766 if (mac_vals.xmac_addr)
10767 REG_WR(bp, mac_vals.xmac_addr, mac_vals.xmac_val);
10768 if (mac_vals.umac_addr[0])
10769 REG_WR(bp, mac_vals.umac_addr[0], mac_vals.umac_val[0]);
10770 if (mac_vals.umac_addr[1])
10771 REG_WR(bp, mac_vals.umac_addr[1], mac_vals.umac_val[1]);
10772 if (mac_vals.emac_addr)
10773 REG_WR(bp, mac_vals.emac_addr, mac_vals.emac_val);
10774 if (mac_vals.bmac_addr) {
10775 REG_WR(bp, mac_vals.bmac_addr, mac_vals.bmac_val[0]);
10776 REG_WR(bp, mac_vals.bmac_addr + 4, mac_vals.bmac_val[1]);
10779 rc = bnx2x_prev_mark_path(bp, prev_undi);
10781 bnx2x_prev_mcp_done(bp);
10785 return bnx2x_prev_mcp_done(bp);
10788 static int bnx2x_prev_unload(struct bnx2x *bp)
10790 int time_counter = 10;
10791 u32 rc, fw, hw_lock_reg, hw_lock_val;
10792 BNX2X_DEV_INFO("Entering Previous Unload Flow\n");
10794 /* clear hw from errors which may have resulted from an interrupted
10795 * dmae transaction.
10797 bnx2x_clean_pglue_errors(bp);
10799 /* Release previously held locks */
10800 hw_lock_reg = (BP_FUNC(bp) <= 5) ?
10801 (MISC_REG_DRIVER_CONTROL_1 + BP_FUNC(bp) * 8) :
10802 (MISC_REG_DRIVER_CONTROL_7 + (BP_FUNC(bp) - 6) * 8);
10804 hw_lock_val = REG_RD(bp, hw_lock_reg);
10806 if (hw_lock_val & HW_LOCK_RESOURCE_NVRAM) {
10807 BNX2X_DEV_INFO("Release Previously held NVRAM lock\n");
10808 REG_WR(bp, MCP_REG_MCPR_NVM_SW_ARB,
10809 (MCPR_NVM_SW_ARB_ARB_REQ_CLR1 << BP_PORT(bp)));
10812 BNX2X_DEV_INFO("Release Previously held hw lock\n");
10813 REG_WR(bp, hw_lock_reg, 0xffffffff);
10815 BNX2X_DEV_INFO("No need to release hw/nvram locks\n");
10817 if (MCPR_ACCESS_LOCK_LOCK & REG_RD(bp, MCP_REG_MCPR_ACCESS_LOCK)) {
10818 BNX2X_DEV_INFO("Release previously held alr\n");
10819 bnx2x_release_alr(bp);
10824 /* Lock MCP using an unload request */
10825 fw = bnx2x_fw_command(bp, DRV_MSG_CODE_UNLOAD_REQ_WOL_DIS, 0);
10827 BNX2X_ERR("MCP response failure, aborting\n");
10832 rc = down_interruptible(&bnx2x_prev_sem);
10834 BNX2X_ERR("Cannot check for AER; Received %d when tried to take lock\n",
10837 /* If Path is marked by EEH, ignore unload status */
10838 aer = !!(bnx2x_prev_path_get_entry(bp) &&
10839 bnx2x_prev_path_get_entry(bp)->aer);
10840 up(&bnx2x_prev_sem);
10843 if (fw == FW_MSG_CODE_DRV_UNLOAD_COMMON || aer) {
10844 rc = bnx2x_prev_unload_common(bp);
10848 /* non-common reply from MCP might require looping */
10849 rc = bnx2x_prev_unload_uncommon(bp);
10850 if (rc != BNX2X_PREV_WAIT_NEEDED)
10854 } while (--time_counter);
10856 if (!time_counter || rc) {
10857 BNX2X_DEV_INFO("Unloading previous driver did not occur, Possibly due to MF UNDI\n");
10858 rc = -EPROBE_DEFER;
10861 /* Mark function if its port was used to boot from SAN */
10862 if (bnx2x_port_after_undi(bp))
10863 bp->link_params.feature_config_flags |=
10864 FEATURE_CONFIG_BOOT_FROM_SAN;
10866 BNX2X_DEV_INFO("Finished Previous Unload Flow [%d]\n", rc);
10871 static void bnx2x_get_common_hwinfo(struct bnx2x *bp)
10873 u32 val, val2, val3, val4, id, boot_mode;
10876 /* Get the chip revision id and number. */
10877 /* chip num:16-31, rev:12-15, metal:4-11, bond_id:0-3 */
10878 val = REG_RD(bp, MISC_REG_CHIP_NUM);
10879 id = ((val & 0xffff) << 16);
10880 val = REG_RD(bp, MISC_REG_CHIP_REV);
10881 id |= ((val & 0xf) << 12);
10883 /* Metal is read from PCI regs, but we can't access >=0x400 from
10884 * the configuration space (so we need to reg_rd)
10886 val = REG_RD(bp, PCICFG_OFFSET + PCI_ID_VAL3);
10887 id |= (((val >> 24) & 0xf) << 4);
10888 val = REG_RD(bp, MISC_REG_BOND_ID);
10890 bp->common.chip_id = id;
10892 /* force 57811 according to MISC register */
10893 if (REG_RD(bp, MISC_REG_CHIP_TYPE) & MISC_REG_CHIP_TYPE_57811_MASK) {
10894 if (CHIP_IS_57810(bp))
10895 bp->common.chip_id = (CHIP_NUM_57811 << 16) |
10896 (bp->common.chip_id & 0x0000FFFF);
10897 else if (CHIP_IS_57810_MF(bp))
10898 bp->common.chip_id = (CHIP_NUM_57811_MF << 16) |
10899 (bp->common.chip_id & 0x0000FFFF);
10900 bp->common.chip_id |= 0x1;
10903 /* Set doorbell size */
10904 bp->db_size = (1 << BNX2X_DB_SHIFT);
10906 if (!CHIP_IS_E1x(bp)) {
10907 val = REG_RD(bp, MISC_REG_PORT4MODE_EN_OVWR);
10908 if ((val & 1) == 0)
10909 val = REG_RD(bp, MISC_REG_PORT4MODE_EN);
10911 val = (val >> 1) & 1;
10912 BNX2X_DEV_INFO("chip is in %s\n", val ? "4_PORT_MODE" :
10914 bp->common.chip_port_mode = val ? CHIP_4_PORT_MODE :
10917 if (CHIP_MODE_IS_4_PORT(bp))
10918 bp->pfid = (bp->pf_num >> 1); /* 0..3 */
10920 bp->pfid = (bp->pf_num & 0x6); /* 0, 2, 4, 6 */
10922 bp->common.chip_port_mode = CHIP_PORT_MODE_NONE; /* N/A */
10923 bp->pfid = bp->pf_num; /* 0..7 */
10926 BNX2X_DEV_INFO("pf_id: %x", bp->pfid);
10928 bp->link_params.chip_id = bp->common.chip_id;
10929 BNX2X_DEV_INFO("chip ID is 0x%x\n", id);
10931 val = (REG_RD(bp, 0x2874) & 0x55);
10932 if ((bp->common.chip_id & 0x1) ||
10933 (CHIP_IS_E1(bp) && val) || (CHIP_IS_E1H(bp) && (val == 0x55))) {
10934 bp->flags |= ONE_PORT_FLAG;
10935 BNX2X_DEV_INFO("single port device\n");
10938 val = REG_RD(bp, MCP_REG_MCPR_NVM_CFG4);
10939 bp->common.flash_size = (BNX2X_NVRAM_1MB_SIZE <<
10940 (val & MCPR_NVM_CFG4_FLASH_SIZE));
10941 BNX2X_DEV_INFO("flash_size 0x%x (%d)\n",
10942 bp->common.flash_size, bp->common.flash_size);
10944 bnx2x_init_shmem(bp);
10946 bp->common.shmem2_base = REG_RD(bp, (BP_PATH(bp) ?
10947 MISC_REG_GENERIC_CR_1 :
10948 MISC_REG_GENERIC_CR_0));
10950 bp->link_params.shmem_base = bp->common.shmem_base;
10951 bp->link_params.shmem2_base = bp->common.shmem2_base;
10952 if (SHMEM2_RD(bp, size) >
10953 (u32)offsetof(struct shmem2_region, lfa_host_addr[BP_PORT(bp)]))
10954 bp->link_params.lfa_base =
10955 REG_RD(bp, bp->common.shmem2_base +
10956 (u32)offsetof(struct shmem2_region,
10957 lfa_host_addr[BP_PORT(bp)]));
10959 bp->link_params.lfa_base = 0;
10960 BNX2X_DEV_INFO("shmem offset 0x%x shmem2 offset 0x%x\n",
10961 bp->common.shmem_base, bp->common.shmem2_base);
10963 if (!bp->common.shmem_base) {
10964 BNX2X_DEV_INFO("MCP not active\n");
10965 bp->flags |= NO_MCP_FLAG;
10969 bp->common.hw_config = SHMEM_RD(bp, dev_info.shared_hw_config.config);
10970 BNX2X_DEV_INFO("hw_config 0x%08x\n", bp->common.hw_config);
10972 bp->link_params.hw_led_mode = ((bp->common.hw_config &
10973 SHARED_HW_CFG_LED_MODE_MASK) >>
10974 SHARED_HW_CFG_LED_MODE_SHIFT);
10976 bp->link_params.feature_config_flags = 0;
10977 val = SHMEM_RD(bp, dev_info.shared_feature_config.config);
10978 if (val & SHARED_FEAT_CFG_OVERRIDE_PREEMPHASIS_CFG_ENABLED)
10979 bp->link_params.feature_config_flags |=
10980 FEATURE_CONFIG_OVERRIDE_PREEMPHASIS_ENABLED;
10982 bp->link_params.feature_config_flags &=
10983 ~FEATURE_CONFIG_OVERRIDE_PREEMPHASIS_ENABLED;
10985 val = SHMEM_RD(bp, dev_info.bc_rev) >> 8;
10986 bp->common.bc_ver = val;
10987 BNX2X_DEV_INFO("bc_ver %X\n", val);
10988 if (val < BNX2X_BC_VER) {
10989 /* for now only warn
10990 * later we might need to enforce this */
10991 BNX2X_ERR("This driver needs bc_ver %X but found %X, please upgrade BC\n",
10992 BNX2X_BC_VER, val);
10994 bp->link_params.feature_config_flags |=
10995 (val >= REQ_BC_VER_4_VRFY_FIRST_PHY_OPT_MDL) ?
10996 FEATURE_CONFIG_BC_SUPPORTS_OPT_MDL_VRFY : 0;
10998 bp->link_params.feature_config_flags |=
10999 (val >= REQ_BC_VER_4_VRFY_SPECIFIC_PHY_OPT_MDL) ?
11000 FEATURE_CONFIG_BC_SUPPORTS_DUAL_PHY_OPT_MDL_VRFY : 0;
11001 bp->link_params.feature_config_flags |=
11002 (val >= REQ_BC_VER_4_VRFY_AFEX_SUPPORTED) ?
11003 FEATURE_CONFIG_BC_SUPPORTS_AFEX : 0;
11004 bp->link_params.feature_config_flags |=
11005 (val >= REQ_BC_VER_4_SFP_TX_DISABLE_SUPPORTED) ?
11006 FEATURE_CONFIG_BC_SUPPORTS_SFP_TX_DISABLED : 0;
11008 bp->link_params.feature_config_flags |=
11009 (val >= REQ_BC_VER_4_MT_SUPPORTED) ?
11010 FEATURE_CONFIG_MT_SUPPORT : 0;
11012 bp->flags |= (val >= REQ_BC_VER_4_PFC_STATS_SUPPORTED) ?
11013 BC_SUPPORTS_PFC_STATS : 0;
11015 bp->flags |= (val >= REQ_BC_VER_4_FCOE_FEATURES) ?
11016 BC_SUPPORTS_FCOE_FEATURES : 0;
11018 bp->flags |= (val >= REQ_BC_VER_4_DCBX_ADMIN_MSG_NON_PMF) ?
11019 BC_SUPPORTS_DCBX_MSG_NON_PMF : 0;
11021 bp->flags |= (val >= REQ_BC_VER_4_RMMOD_CMD) ?
11022 BC_SUPPORTS_RMMOD_CMD : 0;
11024 boot_mode = SHMEM_RD(bp,
11025 dev_info.port_feature_config[BP_PORT(bp)].mba_config) &
11026 PORT_FEATURE_MBA_BOOT_AGENT_TYPE_MASK;
11027 switch (boot_mode) {
11028 case PORT_FEATURE_MBA_BOOT_AGENT_TYPE_PXE:
11029 bp->common.boot_mode = FEATURE_ETH_BOOTMODE_PXE;
11031 case PORT_FEATURE_MBA_BOOT_AGENT_TYPE_ISCSIB:
11032 bp->common.boot_mode = FEATURE_ETH_BOOTMODE_ISCSI;
11034 case PORT_FEATURE_MBA_BOOT_AGENT_TYPE_FCOE_BOOT:
11035 bp->common.boot_mode = FEATURE_ETH_BOOTMODE_FCOE;
11037 case PORT_FEATURE_MBA_BOOT_AGENT_TYPE_NONE:
11038 bp->common.boot_mode = FEATURE_ETH_BOOTMODE_NONE;
11042 pci_read_config_word(bp->pdev, bp->pdev->pm_cap + PCI_PM_PMC, &pmc);
11043 bp->flags |= (pmc & PCI_PM_CAP_PME_D3cold) ? 0 : NO_WOL_FLAG;
11045 BNX2X_DEV_INFO("%sWoL capable\n",
11046 (bp->flags & NO_WOL_FLAG) ? "not " : "");
11048 val = SHMEM_RD(bp, dev_info.shared_hw_config.part_num);
11049 val2 = SHMEM_RD(bp, dev_info.shared_hw_config.part_num[4]);
11050 val3 = SHMEM_RD(bp, dev_info.shared_hw_config.part_num[8]);
11051 val4 = SHMEM_RD(bp, dev_info.shared_hw_config.part_num[12]);
11053 dev_info(&bp->pdev->dev, "part number %X-%X-%X-%X\n",
11054 val, val2, val3, val4);
11057 #define IGU_FID(val) GET_FIELD((val), IGU_REG_MAPPING_MEMORY_FID)
11058 #define IGU_VEC(val) GET_FIELD((val), IGU_REG_MAPPING_MEMORY_VECTOR)
11060 static int bnx2x_get_igu_cam_info(struct bnx2x *bp)
11062 int pfid = BP_FUNC(bp);
11065 u8 fid, igu_sb_cnt = 0;
11067 bp->igu_base_sb = 0xff;
11068 if (CHIP_INT_MODE_IS_BC(bp)) {
11069 int vn = BP_VN(bp);
11070 igu_sb_cnt = bp->igu_sb_cnt;
11071 bp->igu_base_sb = (CHIP_MODE_IS_4_PORT(bp) ? pfid : vn) *
11074 bp->igu_dsb_id = E1HVN_MAX * FP_SB_MAX_E1x +
11075 (CHIP_MODE_IS_4_PORT(bp) ? pfid : vn);
11080 /* IGU in normal mode - read CAM */
11081 for (igu_sb_id = 0; igu_sb_id < IGU_REG_MAPPING_MEMORY_SIZE;
11083 val = REG_RD(bp, IGU_REG_MAPPING_MEMORY + igu_sb_id * 4);
11084 if (!(val & IGU_REG_MAPPING_MEMORY_VALID))
11086 fid = IGU_FID(val);
11087 if ((fid & IGU_FID_ENCODE_IS_PF)) {
11088 if ((fid & IGU_FID_PF_NUM_MASK) != pfid)
11090 if (IGU_VEC(val) == 0)
11091 /* default status block */
11092 bp->igu_dsb_id = igu_sb_id;
11094 if (bp->igu_base_sb == 0xff)
11095 bp->igu_base_sb = igu_sb_id;
11101 #ifdef CONFIG_PCI_MSI
11102 /* Due to new PF resource allocation by MFW T7.4 and above, it's
11103 * optional that number of CAM entries will not be equal to the value
11104 * advertised in PCI.
11105 * Driver should use the minimal value of both as the actual status
11108 bp->igu_sb_cnt = min_t(int, bp->igu_sb_cnt, igu_sb_cnt);
11111 if (igu_sb_cnt == 0) {
11112 BNX2X_ERR("CAM configuration error\n");
11119 static void bnx2x_link_settings_supported(struct bnx2x *bp, u32 switch_cfg)
11121 int cfg_size = 0, idx, port = BP_PORT(bp);
11123 /* Aggregation of supported attributes of all external phys */
11124 bp->port.supported[0] = 0;
11125 bp->port.supported[1] = 0;
11126 switch (bp->link_params.num_phys) {
11128 bp->port.supported[0] = bp->link_params.phy[INT_PHY].supported;
11132 bp->port.supported[0] = bp->link_params.phy[EXT_PHY1].supported;
11136 if (bp->link_params.multi_phy_config &
11137 PORT_HW_CFG_PHY_SWAPPED_ENABLED) {
11138 bp->port.supported[1] =
11139 bp->link_params.phy[EXT_PHY1].supported;
11140 bp->port.supported[0] =
11141 bp->link_params.phy[EXT_PHY2].supported;
11143 bp->port.supported[0] =
11144 bp->link_params.phy[EXT_PHY1].supported;
11145 bp->port.supported[1] =
11146 bp->link_params.phy[EXT_PHY2].supported;
11152 if (!(bp->port.supported[0] || bp->port.supported[1])) {
11153 BNX2X_ERR("NVRAM config error. BAD phy config. PHY1 config 0x%x, PHY2 config 0x%x\n",
11155 dev_info.port_hw_config[port].external_phy_config),
11157 dev_info.port_hw_config[port].external_phy_config2));
11161 if (CHIP_IS_E3(bp))
11162 bp->port.phy_addr = REG_RD(bp, MISC_REG_WC0_CTRL_PHY_ADDR);
11164 switch (switch_cfg) {
11165 case SWITCH_CFG_1G:
11166 bp->port.phy_addr = REG_RD(
11167 bp, NIG_REG_SERDES0_CTRL_PHY_ADDR + port*0x10);
11169 case SWITCH_CFG_10G:
11170 bp->port.phy_addr = REG_RD(
11171 bp, NIG_REG_XGXS0_CTRL_PHY_ADDR + port*0x18);
11174 BNX2X_ERR("BAD switch_cfg link_config 0x%x\n",
11175 bp->port.link_config[0]);
11179 BNX2X_DEV_INFO("phy_addr 0x%x\n", bp->port.phy_addr);
11180 /* mask what we support according to speed_cap_mask per configuration */
11181 for (idx = 0; idx < cfg_size; idx++) {
11182 if (!(bp->link_params.speed_cap_mask[idx] &
11183 PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_HALF))
11184 bp->port.supported[idx] &= ~SUPPORTED_10baseT_Half;
11186 if (!(bp->link_params.speed_cap_mask[idx] &
11187 PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_FULL))
11188 bp->port.supported[idx] &= ~SUPPORTED_10baseT_Full;
11190 if (!(bp->link_params.speed_cap_mask[idx] &
11191 PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_HALF))
11192 bp->port.supported[idx] &= ~SUPPORTED_100baseT_Half;
11194 if (!(bp->link_params.speed_cap_mask[idx] &
11195 PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_FULL))
11196 bp->port.supported[idx] &= ~SUPPORTED_100baseT_Full;
11198 if (!(bp->link_params.speed_cap_mask[idx] &
11199 PORT_HW_CFG_SPEED_CAPABILITY_D0_1G))
11200 bp->port.supported[idx] &= ~(SUPPORTED_1000baseT_Half |
11201 SUPPORTED_1000baseT_Full);
11203 if (!(bp->link_params.speed_cap_mask[idx] &
11204 PORT_HW_CFG_SPEED_CAPABILITY_D0_2_5G))
11205 bp->port.supported[idx] &= ~SUPPORTED_2500baseX_Full;
11207 if (!(bp->link_params.speed_cap_mask[idx] &
11208 PORT_HW_CFG_SPEED_CAPABILITY_D0_10G))
11209 bp->port.supported[idx] &= ~SUPPORTED_10000baseT_Full;
11211 if (!(bp->link_params.speed_cap_mask[idx] &
11212 PORT_HW_CFG_SPEED_CAPABILITY_D0_20G))
11213 bp->port.supported[idx] &= ~SUPPORTED_20000baseKR2_Full;
11216 BNX2X_DEV_INFO("supported 0x%x 0x%x\n", bp->port.supported[0],
11217 bp->port.supported[1]);
11220 static void bnx2x_link_settings_requested(struct bnx2x *bp)
11222 u32 link_config, idx, cfg_size = 0;
11223 bp->port.advertising[0] = 0;
11224 bp->port.advertising[1] = 0;
11225 switch (bp->link_params.num_phys) {
11234 for (idx = 0; idx < cfg_size; idx++) {
11235 bp->link_params.req_duplex[idx] = DUPLEX_FULL;
11236 link_config = bp->port.link_config[idx];
11237 switch (link_config & PORT_FEATURE_LINK_SPEED_MASK) {
11238 case PORT_FEATURE_LINK_SPEED_AUTO:
11239 if (bp->port.supported[idx] & SUPPORTED_Autoneg) {
11240 bp->link_params.req_line_speed[idx] =
11242 bp->port.advertising[idx] |=
11243 bp->port.supported[idx];
11244 if (bp->link_params.phy[EXT_PHY1].type ==
11245 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84833)
11246 bp->port.advertising[idx] |=
11247 (SUPPORTED_100baseT_Half |
11248 SUPPORTED_100baseT_Full);
11250 /* force 10G, no AN */
11251 bp->link_params.req_line_speed[idx] =
11253 bp->port.advertising[idx] |=
11254 (ADVERTISED_10000baseT_Full |
11260 case PORT_FEATURE_LINK_SPEED_10M_FULL:
11261 if (bp->port.supported[idx] & SUPPORTED_10baseT_Full) {
11262 bp->link_params.req_line_speed[idx] =
11264 bp->port.advertising[idx] |=
11265 (ADVERTISED_10baseT_Full |
11268 BNX2X_ERR("NVRAM config error. Invalid link_config 0x%x speed_cap_mask 0x%x\n",
11270 bp->link_params.speed_cap_mask[idx]);
11275 case PORT_FEATURE_LINK_SPEED_10M_HALF:
11276 if (bp->port.supported[idx] & SUPPORTED_10baseT_Half) {
11277 bp->link_params.req_line_speed[idx] =
11279 bp->link_params.req_duplex[idx] =
11281 bp->port.advertising[idx] |=
11282 (ADVERTISED_10baseT_Half |
11285 BNX2X_ERR("NVRAM config error. Invalid link_config 0x%x speed_cap_mask 0x%x\n",
11287 bp->link_params.speed_cap_mask[idx]);
11292 case PORT_FEATURE_LINK_SPEED_100M_FULL:
11293 if (bp->port.supported[idx] &
11294 SUPPORTED_100baseT_Full) {
11295 bp->link_params.req_line_speed[idx] =
11297 bp->port.advertising[idx] |=
11298 (ADVERTISED_100baseT_Full |
11301 BNX2X_ERR("NVRAM config error. Invalid link_config 0x%x speed_cap_mask 0x%x\n",
11303 bp->link_params.speed_cap_mask[idx]);
11308 case PORT_FEATURE_LINK_SPEED_100M_HALF:
11309 if (bp->port.supported[idx] &
11310 SUPPORTED_100baseT_Half) {
11311 bp->link_params.req_line_speed[idx] =
11313 bp->link_params.req_duplex[idx] =
11315 bp->port.advertising[idx] |=
11316 (ADVERTISED_100baseT_Half |
11319 BNX2X_ERR("NVRAM config error. Invalid link_config 0x%x speed_cap_mask 0x%x\n",
11321 bp->link_params.speed_cap_mask[idx]);
11326 case PORT_FEATURE_LINK_SPEED_1G:
11327 if (bp->port.supported[idx] &
11328 SUPPORTED_1000baseT_Full) {
11329 bp->link_params.req_line_speed[idx] =
11331 bp->port.advertising[idx] |=
11332 (ADVERTISED_1000baseT_Full |
11334 } else if (bp->port.supported[idx] &
11335 SUPPORTED_1000baseKX_Full) {
11336 bp->link_params.req_line_speed[idx] =
11338 bp->port.advertising[idx] |=
11339 ADVERTISED_1000baseKX_Full;
11341 BNX2X_ERR("NVRAM config error. Invalid link_config 0x%x speed_cap_mask 0x%x\n",
11343 bp->link_params.speed_cap_mask[idx]);
11348 case PORT_FEATURE_LINK_SPEED_2_5G:
11349 if (bp->port.supported[idx] &
11350 SUPPORTED_2500baseX_Full) {
11351 bp->link_params.req_line_speed[idx] =
11353 bp->port.advertising[idx] |=
11354 (ADVERTISED_2500baseX_Full |
11357 BNX2X_ERR("NVRAM config error. Invalid link_config 0x%x speed_cap_mask 0x%x\n",
11359 bp->link_params.speed_cap_mask[idx]);
11364 case PORT_FEATURE_LINK_SPEED_10G_CX4:
11365 if (bp->port.supported[idx] &
11366 SUPPORTED_10000baseT_Full) {
11367 bp->link_params.req_line_speed[idx] =
11369 bp->port.advertising[idx] |=
11370 (ADVERTISED_10000baseT_Full |
11372 } else if (bp->port.supported[idx] &
11373 SUPPORTED_10000baseKR_Full) {
11374 bp->link_params.req_line_speed[idx] =
11376 bp->port.advertising[idx] |=
11377 (ADVERTISED_10000baseKR_Full |
11380 BNX2X_ERR("NVRAM config error. Invalid link_config 0x%x speed_cap_mask 0x%x\n",
11382 bp->link_params.speed_cap_mask[idx]);
11386 case PORT_FEATURE_LINK_SPEED_20G:
11387 bp->link_params.req_line_speed[idx] = SPEED_20000;
11391 BNX2X_ERR("NVRAM config error. BAD link speed link_config 0x%x\n",
11393 bp->link_params.req_line_speed[idx] =
11395 bp->port.advertising[idx] =
11396 bp->port.supported[idx];
11400 bp->link_params.req_flow_ctrl[idx] = (link_config &
11401 PORT_FEATURE_FLOW_CONTROL_MASK);
11402 if (bp->link_params.req_flow_ctrl[idx] ==
11403 BNX2X_FLOW_CTRL_AUTO) {
11404 if (!(bp->port.supported[idx] & SUPPORTED_Autoneg))
11405 bp->link_params.req_flow_ctrl[idx] =
11406 BNX2X_FLOW_CTRL_NONE;
11408 bnx2x_set_requested_fc(bp);
11411 BNX2X_DEV_INFO("req_line_speed %d req_duplex %d req_flow_ctrl 0x%x advertising 0x%x\n",
11412 bp->link_params.req_line_speed[idx],
11413 bp->link_params.req_duplex[idx],
11414 bp->link_params.req_flow_ctrl[idx],
11415 bp->port.advertising[idx]);
11419 static void bnx2x_set_mac_buf(u8 *mac_buf, u32 mac_lo, u16 mac_hi)
11421 __be16 mac_hi_be = cpu_to_be16(mac_hi);
11422 __be32 mac_lo_be = cpu_to_be32(mac_lo);
11423 memcpy(mac_buf, &mac_hi_be, sizeof(mac_hi_be));
11424 memcpy(mac_buf + sizeof(mac_hi_be), &mac_lo_be, sizeof(mac_lo_be));
11427 static void bnx2x_get_port_hwinfo(struct bnx2x *bp)
11429 int port = BP_PORT(bp);
11431 u32 ext_phy_type, ext_phy_config, eee_mode;
11433 bp->link_params.bp = bp;
11434 bp->link_params.port = port;
11436 bp->link_params.lane_config =
11437 SHMEM_RD(bp, dev_info.port_hw_config[port].lane_config);
11439 bp->link_params.speed_cap_mask[0] =
11441 dev_info.port_hw_config[port].speed_capability_mask) &
11442 PORT_HW_CFG_SPEED_CAPABILITY_D0_MASK;
11443 bp->link_params.speed_cap_mask[1] =
11445 dev_info.port_hw_config[port].speed_capability_mask2) &
11446 PORT_HW_CFG_SPEED_CAPABILITY_D0_MASK;
11447 bp->port.link_config[0] =
11448 SHMEM_RD(bp, dev_info.port_feature_config[port].link_config);
11450 bp->port.link_config[1] =
11451 SHMEM_RD(bp, dev_info.port_feature_config[port].link_config2);
11453 bp->link_params.multi_phy_config =
11454 SHMEM_RD(bp, dev_info.port_hw_config[port].multi_phy_config);
11455 /* If the device is capable of WoL, set the default state according
11458 config = SHMEM_RD(bp, dev_info.port_feature_config[port].config);
11459 bp->wol = (!(bp->flags & NO_WOL_FLAG) &&
11460 (config & PORT_FEATURE_WOL_ENABLED));
11462 if ((config & PORT_FEAT_CFG_STORAGE_PERSONALITY_MASK) ==
11463 PORT_FEAT_CFG_STORAGE_PERSONALITY_FCOE && !IS_MF(bp))
11464 bp->flags |= NO_ISCSI_FLAG;
11465 if ((config & PORT_FEAT_CFG_STORAGE_PERSONALITY_MASK) ==
11466 PORT_FEAT_CFG_STORAGE_PERSONALITY_ISCSI && !(IS_MF(bp)))
11467 bp->flags |= NO_FCOE_FLAG;
11469 BNX2X_DEV_INFO("lane_config 0x%08x speed_cap_mask0 0x%08x link_config0 0x%08x\n",
11470 bp->link_params.lane_config,
11471 bp->link_params.speed_cap_mask[0],
11472 bp->port.link_config[0]);
11474 bp->link_params.switch_cfg = (bp->port.link_config[0] &
11475 PORT_FEATURE_CONNECTED_SWITCH_MASK);
11476 bnx2x_phy_probe(&bp->link_params);
11477 bnx2x_link_settings_supported(bp, bp->link_params.switch_cfg);
11479 bnx2x_link_settings_requested(bp);
11482 * If connected directly, work with the internal PHY, otherwise, work
11483 * with the external PHY
11487 dev_info.port_hw_config[port].external_phy_config);
11488 ext_phy_type = XGXS_EXT_PHY_TYPE(ext_phy_config);
11489 if (ext_phy_type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT)
11490 bp->mdio.prtad = bp->port.phy_addr;
11492 else if ((ext_phy_type != PORT_HW_CFG_XGXS_EXT_PHY_TYPE_FAILURE) &&
11493 (ext_phy_type != PORT_HW_CFG_XGXS_EXT_PHY_TYPE_NOT_CONN))
11495 XGXS_EXT_PHY_ADDR(ext_phy_config);
11497 /* Configure link feature according to nvram value */
11498 eee_mode = (((SHMEM_RD(bp, dev_info.
11499 port_feature_config[port].eee_power_mode)) &
11500 PORT_FEAT_CFG_EEE_POWER_MODE_MASK) >>
11501 PORT_FEAT_CFG_EEE_POWER_MODE_SHIFT);
11502 if (eee_mode != PORT_FEAT_CFG_EEE_POWER_MODE_DISABLED) {
11503 bp->link_params.eee_mode = EEE_MODE_ADV_LPI |
11504 EEE_MODE_ENABLE_LPI |
11505 EEE_MODE_OUTPUT_TIME;
11507 bp->link_params.eee_mode = 0;
11511 void bnx2x_get_iscsi_info(struct bnx2x *bp)
11513 u32 no_flags = NO_ISCSI_FLAG;
11514 int port = BP_PORT(bp);
11515 u32 max_iscsi_conn = FW_ENCODE_32BIT_PATTERN ^ SHMEM_RD(bp,
11516 drv_lic_key[port].max_iscsi_conn);
11518 if (!CNIC_SUPPORT(bp)) {
11519 bp->flags |= no_flags;
11523 /* Get the number of maximum allowed iSCSI connections */
11524 bp->cnic_eth_dev.max_iscsi_conn =
11525 (max_iscsi_conn & BNX2X_MAX_ISCSI_INIT_CONN_MASK) >>
11526 BNX2X_MAX_ISCSI_INIT_CONN_SHIFT;
11528 BNX2X_DEV_INFO("max_iscsi_conn 0x%x\n",
11529 bp->cnic_eth_dev.max_iscsi_conn);
11532 * If maximum allowed number of connections is zero -
11533 * disable the feature.
11535 if (!bp->cnic_eth_dev.max_iscsi_conn)
11536 bp->flags |= no_flags;
11539 static void bnx2x_get_ext_wwn_info(struct bnx2x *bp, int func)
11542 bp->cnic_eth_dev.fcoe_wwn_port_name_hi =
11543 MF_CFG_RD(bp, func_ext_config[func].fcoe_wwn_port_name_upper);
11544 bp->cnic_eth_dev.fcoe_wwn_port_name_lo =
11545 MF_CFG_RD(bp, func_ext_config[func].fcoe_wwn_port_name_lower);
11548 bp->cnic_eth_dev.fcoe_wwn_node_name_hi =
11549 MF_CFG_RD(bp, func_ext_config[func].fcoe_wwn_node_name_upper);
11550 bp->cnic_eth_dev.fcoe_wwn_node_name_lo =
11551 MF_CFG_RD(bp, func_ext_config[func].fcoe_wwn_node_name_lower);
11554 static int bnx2x_shared_fcoe_funcs(struct bnx2x *bp)
11561 /* iterate over absolute function ids for this path: */
11562 for (fid = BP_PATH(bp); fid < E2_FUNC_MAX * 2; fid += 2) {
11563 if (IS_MF_SD(bp)) {
11564 u32 cfg = MF_CFG_RD(bp,
11565 func_mf_config[fid].config);
11567 if (!(cfg & FUNC_MF_CFG_FUNC_HIDE) &&
11568 ((cfg & FUNC_MF_CFG_PROTOCOL_MASK) ==
11569 FUNC_MF_CFG_PROTOCOL_FCOE))
11572 u32 cfg = MF_CFG_RD(bp,
11573 func_ext_config[fid].
11576 if ((cfg & MACP_FUNC_CFG_FLAGS_ENABLED) &&
11577 (cfg & MACP_FUNC_CFG_FLAGS_FCOE_OFFLOAD))
11582 int port, port_cnt = CHIP_MODE_IS_4_PORT(bp) ? 2 : 1;
11584 for (port = 0; port < port_cnt; port++) {
11585 u32 lic = SHMEM_RD(bp,
11586 drv_lic_key[port].max_fcoe_conn) ^
11587 FW_ENCODE_32BIT_PATTERN;
11596 static void bnx2x_get_fcoe_info(struct bnx2x *bp)
11598 int port = BP_PORT(bp);
11599 int func = BP_ABS_FUNC(bp);
11600 u32 max_fcoe_conn = FW_ENCODE_32BIT_PATTERN ^ SHMEM_RD(bp,
11601 drv_lic_key[port].max_fcoe_conn);
11602 u8 num_fcoe_func = bnx2x_shared_fcoe_funcs(bp);
11604 if (!CNIC_SUPPORT(bp)) {
11605 bp->flags |= NO_FCOE_FLAG;
11609 /* Get the number of maximum allowed FCoE connections */
11610 bp->cnic_eth_dev.max_fcoe_conn =
11611 (max_fcoe_conn & BNX2X_MAX_FCOE_INIT_CONN_MASK) >>
11612 BNX2X_MAX_FCOE_INIT_CONN_SHIFT;
11614 /* Calculate the number of maximum allowed FCoE tasks */
11615 bp->cnic_eth_dev.max_fcoe_exchanges = MAX_NUM_FCOE_TASKS_PER_ENGINE;
11617 /* check if FCoE resources must be shared between different functions */
11619 bp->cnic_eth_dev.max_fcoe_exchanges /= num_fcoe_func;
11621 /* Read the WWN: */
11624 bp->cnic_eth_dev.fcoe_wwn_port_name_hi =
11626 dev_info.port_hw_config[port].
11627 fcoe_wwn_port_name_upper);
11628 bp->cnic_eth_dev.fcoe_wwn_port_name_lo =
11630 dev_info.port_hw_config[port].
11631 fcoe_wwn_port_name_lower);
11634 bp->cnic_eth_dev.fcoe_wwn_node_name_hi =
11636 dev_info.port_hw_config[port].
11637 fcoe_wwn_node_name_upper);
11638 bp->cnic_eth_dev.fcoe_wwn_node_name_lo =
11640 dev_info.port_hw_config[port].
11641 fcoe_wwn_node_name_lower);
11642 } else if (!IS_MF_SD(bp)) {
11643 /* Read the WWN info only if the FCoE feature is enabled for
11646 if (BNX2X_HAS_MF_EXT_PROTOCOL_FCOE(bp))
11647 bnx2x_get_ext_wwn_info(bp, func);
11649 if (BNX2X_IS_MF_SD_PROTOCOL_FCOE(bp) && !CHIP_IS_E1x(bp))
11650 bnx2x_get_ext_wwn_info(bp, func);
11653 BNX2X_DEV_INFO("max_fcoe_conn 0x%x\n", bp->cnic_eth_dev.max_fcoe_conn);
11656 * If maximum allowed number of connections is zero -
11657 * disable the feature.
11659 if (!bp->cnic_eth_dev.max_fcoe_conn)
11660 bp->flags |= NO_FCOE_FLAG;
11663 static void bnx2x_get_cnic_info(struct bnx2x *bp)
11666 * iSCSI may be dynamically disabled but reading
11667 * info here we will decrease memory usage by driver
11668 * if the feature is disabled for good
11670 bnx2x_get_iscsi_info(bp);
11671 bnx2x_get_fcoe_info(bp);
11674 static void bnx2x_get_cnic_mac_hwinfo(struct bnx2x *bp)
11677 int func = BP_ABS_FUNC(bp);
11678 int port = BP_PORT(bp);
11679 u8 *iscsi_mac = bp->cnic_eth_dev.iscsi_mac;
11680 u8 *fip_mac = bp->fip_mac;
11683 /* iSCSI and FCoE NPAR MACs: if there is no either iSCSI or
11684 * FCoE MAC then the appropriate feature should be disabled.
11685 * In non SD mode features configuration comes from struct
11688 if (!IS_MF_SD(bp)) {
11689 u32 cfg = MF_CFG_RD(bp, func_ext_config[func].func_cfg);
11690 if (cfg & MACP_FUNC_CFG_FLAGS_ISCSI_OFFLOAD) {
11691 val2 = MF_CFG_RD(bp, func_ext_config[func].
11692 iscsi_mac_addr_upper);
11693 val = MF_CFG_RD(bp, func_ext_config[func].
11694 iscsi_mac_addr_lower);
11695 bnx2x_set_mac_buf(iscsi_mac, val, val2);
11697 ("Read iSCSI MAC: %pM\n", iscsi_mac);
11699 bp->flags |= NO_ISCSI_OOO_FLAG | NO_ISCSI_FLAG;
11702 if (cfg & MACP_FUNC_CFG_FLAGS_FCOE_OFFLOAD) {
11703 val2 = MF_CFG_RD(bp, func_ext_config[func].
11704 fcoe_mac_addr_upper);
11705 val = MF_CFG_RD(bp, func_ext_config[func].
11706 fcoe_mac_addr_lower);
11707 bnx2x_set_mac_buf(fip_mac, val, val2);
11709 ("Read FCoE L2 MAC: %pM\n", fip_mac);
11711 bp->flags |= NO_FCOE_FLAG;
11714 bp->mf_ext_config = cfg;
11716 } else { /* SD MODE */
11717 if (BNX2X_IS_MF_SD_PROTOCOL_ISCSI(bp)) {
11718 /* use primary mac as iscsi mac */
11719 memcpy(iscsi_mac, bp->dev->dev_addr, ETH_ALEN);
11721 BNX2X_DEV_INFO("SD ISCSI MODE\n");
11723 ("Read iSCSI MAC: %pM\n", iscsi_mac);
11724 } else if (BNX2X_IS_MF_SD_PROTOCOL_FCOE(bp)) {
11725 /* use primary mac as fip mac */
11726 memcpy(fip_mac, bp->dev->dev_addr, ETH_ALEN);
11727 BNX2X_DEV_INFO("SD FCoE MODE\n");
11729 ("Read FIP MAC: %pM\n", fip_mac);
11733 /* If this is a storage-only interface, use SAN mac as
11734 * primary MAC. Notice that for SD this is already the case,
11735 * as the SAN mac was copied from the primary MAC.
11737 if (IS_MF_FCOE_AFEX(bp))
11738 memcpy(bp->dev->dev_addr, fip_mac, ETH_ALEN);
11740 val2 = SHMEM_RD(bp, dev_info.port_hw_config[port].
11742 val = SHMEM_RD(bp, dev_info.port_hw_config[port].
11744 bnx2x_set_mac_buf(iscsi_mac, val, val2);
11746 val2 = SHMEM_RD(bp, dev_info.port_hw_config[port].
11747 fcoe_fip_mac_upper);
11748 val = SHMEM_RD(bp, dev_info.port_hw_config[port].
11749 fcoe_fip_mac_lower);
11750 bnx2x_set_mac_buf(fip_mac, val, val2);
11753 /* Disable iSCSI OOO if MAC configuration is invalid. */
11754 if (!is_valid_ether_addr(iscsi_mac)) {
11755 bp->flags |= NO_ISCSI_OOO_FLAG | NO_ISCSI_FLAG;
11756 eth_zero_addr(iscsi_mac);
11759 /* Disable FCoE if MAC configuration is invalid. */
11760 if (!is_valid_ether_addr(fip_mac)) {
11761 bp->flags |= NO_FCOE_FLAG;
11762 eth_zero_addr(bp->fip_mac);
11766 static void bnx2x_get_mac_hwinfo(struct bnx2x *bp)
11769 int func = BP_ABS_FUNC(bp);
11770 int port = BP_PORT(bp);
11772 /* Zero primary MAC configuration */
11773 eth_zero_addr(bp->dev->dev_addr);
11775 if (BP_NOMCP(bp)) {
11776 BNX2X_ERROR("warning: random MAC workaround active\n");
11777 eth_hw_addr_random(bp->dev);
11778 } else if (IS_MF(bp)) {
11779 val2 = MF_CFG_RD(bp, func_mf_config[func].mac_upper);
11780 val = MF_CFG_RD(bp, func_mf_config[func].mac_lower);
11781 if ((val2 != FUNC_MF_CFG_UPPERMAC_DEFAULT) &&
11782 (val != FUNC_MF_CFG_LOWERMAC_DEFAULT))
11783 bnx2x_set_mac_buf(bp->dev->dev_addr, val, val2);
11785 if (CNIC_SUPPORT(bp))
11786 bnx2x_get_cnic_mac_hwinfo(bp);
11788 /* in SF read MACs from port configuration */
11789 val2 = SHMEM_RD(bp, dev_info.port_hw_config[port].mac_upper);
11790 val = SHMEM_RD(bp, dev_info.port_hw_config[port].mac_lower);
11791 bnx2x_set_mac_buf(bp->dev->dev_addr, val, val2);
11793 if (CNIC_SUPPORT(bp))
11794 bnx2x_get_cnic_mac_hwinfo(bp);
11797 if (!BP_NOMCP(bp)) {
11798 /* Read physical port identifier from shmem */
11799 val2 = SHMEM_RD(bp, dev_info.port_hw_config[port].mac_upper);
11800 val = SHMEM_RD(bp, dev_info.port_hw_config[port].mac_lower);
11801 bnx2x_set_mac_buf(bp->phys_port_id, val, val2);
11802 bp->flags |= HAS_PHYS_PORT_ID;
11805 memcpy(bp->link_params.mac_addr, bp->dev->dev_addr, ETH_ALEN);
11807 if (!is_valid_ether_addr(bp->dev->dev_addr))
11808 dev_err(&bp->pdev->dev,
11809 "bad Ethernet MAC address configuration: %pM\n"
11810 "change it manually before bringing up the appropriate network interface\n",
11811 bp->dev->dev_addr);
11814 static bool bnx2x_get_dropless_info(struct bnx2x *bp)
11822 if (IS_MF(bp) && !CHIP_IS_E1x(bp)) {
11823 /* Take function: tmp = func */
11824 tmp = BP_ABS_FUNC(bp);
11825 cfg = MF_CFG_RD(bp, func_ext_config[tmp].func_cfg);
11826 cfg = !!(cfg & MACP_FUNC_CFG_PAUSE_ON_HOST_RING);
11828 /* Take port: tmp = port */
11831 dev_info.port_hw_config[tmp].generic_features);
11832 cfg = !!(cfg & PORT_HW_CFG_PAUSE_ON_HOST_RING_ENABLED);
11837 static void validate_set_si_mode(struct bnx2x *bp)
11839 u8 func = BP_ABS_FUNC(bp);
11842 val = MF_CFG_RD(bp, func_mf_config[func].mac_upper);
11844 /* check for legal mac (upper bytes) */
11845 if (val != 0xffff) {
11846 bp->mf_mode = MULTI_FUNCTION_SI;
11847 bp->mf_config[BP_VN(bp)] =
11848 MF_CFG_RD(bp, func_mf_config[func].config);
11850 BNX2X_DEV_INFO("illegal MAC address for SI\n");
11853 static int bnx2x_get_hwinfo(struct bnx2x *bp)
11855 int /*abs*/func = BP_ABS_FUNC(bp);
11857 u32 val = 0, val2 = 0;
11860 /* Validate that chip access is feasible */
11861 if (REG_RD(bp, MISC_REG_CHIP_NUM) == 0xffffffff) {
11862 dev_err(&bp->pdev->dev,
11863 "Chip read returns all Fs. Preventing probe from continuing\n");
11867 bnx2x_get_common_hwinfo(bp);
11870 * initialize IGU parameters
11872 if (CHIP_IS_E1x(bp)) {
11873 bp->common.int_block = INT_BLOCK_HC;
11875 bp->igu_dsb_id = DEF_SB_IGU_ID;
11876 bp->igu_base_sb = 0;
11878 bp->common.int_block = INT_BLOCK_IGU;
11880 /* do not allow device reset during IGU info processing */
11881 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_RESET);
11883 val = REG_RD(bp, IGU_REG_BLOCK_CONFIGURATION);
11885 if (val & IGU_BLOCK_CONFIGURATION_REG_BACKWARD_COMP_EN) {
11888 BNX2X_DEV_INFO("FORCING Normal Mode\n");
11890 val &= ~(IGU_BLOCK_CONFIGURATION_REG_BACKWARD_COMP_EN);
11891 REG_WR(bp, IGU_REG_BLOCK_CONFIGURATION, val);
11892 REG_WR(bp, IGU_REG_RESET_MEMORIES, 0x7f);
11894 while (tout && REG_RD(bp, IGU_REG_RESET_MEMORIES)) {
11896 usleep_range(1000, 2000);
11899 if (REG_RD(bp, IGU_REG_RESET_MEMORIES)) {
11900 dev_err(&bp->pdev->dev,
11901 "FORCING Normal Mode failed!!!\n");
11902 bnx2x_release_hw_lock(bp,
11903 HW_LOCK_RESOURCE_RESET);
11908 if (val & IGU_BLOCK_CONFIGURATION_REG_BACKWARD_COMP_EN) {
11909 BNX2X_DEV_INFO("IGU Backward Compatible Mode\n");
11910 bp->common.int_block |= INT_BLOCK_MODE_BW_COMP;
11912 BNX2X_DEV_INFO("IGU Normal Mode\n");
11914 rc = bnx2x_get_igu_cam_info(bp);
11915 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_RESET);
11921 * set base FW non-default (fast path) status block id, this value is
11922 * used to initialize the fw_sb_id saved on the fp/queue structure to
11923 * determine the id used by the FW.
11925 if (CHIP_IS_E1x(bp))
11926 bp->base_fw_ndsb = BP_PORT(bp) * FP_SB_MAX_E1x + BP_L_ID(bp);
11928 * 57712 - we currently use one FW SB per IGU SB (Rx and Tx of
11929 * the same queue are indicated on the same IGU SB). So we prefer
11930 * FW and IGU SBs to be the same value.
11932 bp->base_fw_ndsb = bp->igu_base_sb;
11934 BNX2X_DEV_INFO("igu_dsb_id %d igu_base_sb %d igu_sb_cnt %d\n"
11935 "base_fw_ndsb %d\n", bp->igu_dsb_id, bp->igu_base_sb,
11936 bp->igu_sb_cnt, bp->base_fw_ndsb);
11939 * Initialize MF configuration
11944 bp->mf_sub_mode = 0;
11946 mfw_vn = BP_FW_MB_IDX(bp);
11948 if (!CHIP_IS_E1(bp) && !BP_NOMCP(bp)) {
11949 BNX2X_DEV_INFO("shmem2base 0x%x, size %d, mfcfg offset %d\n",
11950 bp->common.shmem2_base, SHMEM2_RD(bp, size),
11951 (u32)offsetof(struct shmem2_region, mf_cfg_addr));
11953 if (SHMEM2_HAS(bp, mf_cfg_addr))
11954 bp->common.mf_cfg_base = SHMEM2_RD(bp, mf_cfg_addr);
11956 bp->common.mf_cfg_base = bp->common.shmem_base +
11957 offsetof(struct shmem_region, func_mb) +
11958 E1H_FUNC_MAX * sizeof(struct drv_func_mb);
11960 * get mf configuration:
11961 * 1. Existence of MF configuration
11962 * 2. MAC address must be legal (check only upper bytes)
11963 * for Switch-Independent mode;
11964 * OVLAN must be legal for Switch-Dependent mode
11965 * 3. SF_MODE configures specific MF mode
11967 if (bp->common.mf_cfg_base != SHMEM_MF_CFG_ADDR_NONE) {
11968 /* get mf configuration */
11970 dev_info.shared_feature_config.config);
11971 val &= SHARED_FEAT_CFG_FORCE_SF_MODE_MASK;
11974 case SHARED_FEAT_CFG_FORCE_SF_MODE_SWITCH_INDEPT:
11975 validate_set_si_mode(bp);
11977 case SHARED_FEAT_CFG_FORCE_SF_MODE_AFEX_MODE:
11978 if ((!CHIP_IS_E1x(bp)) &&
11979 (MF_CFG_RD(bp, func_mf_config[func].
11980 mac_upper) != 0xffff) &&
11982 afex_driver_support))) {
11983 bp->mf_mode = MULTI_FUNCTION_AFEX;
11984 bp->mf_config[vn] = MF_CFG_RD(bp,
11985 func_mf_config[func].config);
11987 BNX2X_DEV_INFO("can not configure afex mode\n");
11990 case SHARED_FEAT_CFG_FORCE_SF_MODE_MF_ALLOWED:
11991 /* get OV configuration */
11992 val = MF_CFG_RD(bp,
11993 func_mf_config[FUNC_0].e1hov_tag);
11994 val &= FUNC_MF_CFG_E1HOV_TAG_MASK;
11996 if (val != FUNC_MF_CFG_E1HOV_TAG_DEFAULT) {
11997 bp->mf_mode = MULTI_FUNCTION_SD;
11998 bp->mf_config[vn] = MF_CFG_RD(bp,
11999 func_mf_config[func].config);
12001 BNX2X_DEV_INFO("illegal OV for SD\n");
12003 case SHARED_FEAT_CFG_FORCE_SF_MODE_BD_MODE:
12004 bp->mf_mode = MULTI_FUNCTION_SD;
12005 bp->mf_sub_mode = SUB_MF_MODE_BD;
12006 bp->mf_config[vn] =
12008 func_mf_config[func].config);
12010 if (SHMEM2_HAS(bp, mtu_size)) {
12011 int mtu_idx = BP_FW_MB_IDX(bp);
12015 mtu = SHMEM2_RD(bp, mtu_size[mtu_idx]);
12016 mtu_size = (u16)mtu;
12017 DP(NETIF_MSG_IFUP, "Read MTU size %04x [%08x]\n",
12020 /* if valid: update device mtu */
12021 if (((mtu_size + ETH_HLEN) >=
12022 ETH_MIN_PACKET_SIZE) &&
12024 ETH_MAX_JUMBO_PACKET_SIZE))
12025 bp->dev->mtu = mtu_size;
12028 case SHARED_FEAT_CFG_FORCE_SF_MODE_UFP_MODE:
12029 bp->mf_mode = MULTI_FUNCTION_SD;
12030 bp->mf_sub_mode = SUB_MF_MODE_UFP;
12031 bp->mf_config[vn] =
12033 func_mf_config[func].config);
12035 case SHARED_FEAT_CFG_FORCE_SF_MODE_FORCED_SF:
12036 bp->mf_config[vn] = 0;
12038 case SHARED_FEAT_CFG_FORCE_SF_MODE_EXTENDED_MODE:
12039 val2 = SHMEM_RD(bp,
12040 dev_info.shared_hw_config.config_3);
12041 val2 &= SHARED_HW_CFG_EXTENDED_MF_MODE_MASK;
12043 case SHARED_HW_CFG_EXTENDED_MF_MODE_NPAR1_DOT_5:
12044 validate_set_si_mode(bp);
12046 SUB_MF_MODE_NPAR1_DOT_5;
12049 /* Unknown configuration */
12050 bp->mf_config[vn] = 0;
12051 BNX2X_DEV_INFO("unknown extended MF mode 0x%x\n",
12056 /* Unknown configuration: reset mf_config */
12057 bp->mf_config[vn] = 0;
12058 BNX2X_DEV_INFO("unknown MF mode 0x%x\n", val);
12062 BNX2X_DEV_INFO("%s function mode\n",
12063 IS_MF(bp) ? "multi" : "single");
12065 switch (bp->mf_mode) {
12066 case MULTI_FUNCTION_SD:
12067 val = MF_CFG_RD(bp, func_mf_config[func].e1hov_tag) &
12068 FUNC_MF_CFG_E1HOV_TAG_MASK;
12069 if (val != FUNC_MF_CFG_E1HOV_TAG_DEFAULT) {
12071 bp->path_has_ovlan = true;
12073 BNX2X_DEV_INFO("MF OV for func %d is %d (0x%04x)\n",
12074 func, bp->mf_ov, bp->mf_ov);
12075 } else if ((bp->mf_sub_mode == SUB_MF_MODE_UFP) ||
12076 (bp->mf_sub_mode == SUB_MF_MODE_BD)) {
12077 dev_err(&bp->pdev->dev,
12078 "Unexpected - no valid MF OV for func %d in UFP/BD mode\n",
12080 bp->path_has_ovlan = true;
12082 dev_err(&bp->pdev->dev,
12083 "No valid MF OV for func %d, aborting\n",
12088 case MULTI_FUNCTION_AFEX:
12089 BNX2X_DEV_INFO("func %d is in MF afex mode\n", func);
12091 case MULTI_FUNCTION_SI:
12092 BNX2X_DEV_INFO("func %d is in MF switch-independent mode\n",
12097 dev_err(&bp->pdev->dev,
12098 "VN %d is in a single function mode, aborting\n",
12105 /* check if other port on the path needs ovlan:
12106 * Since MF configuration is shared between ports
12107 * Possible mixed modes are only
12108 * {SF, SI} {SF, SD} {SD, SF} {SI, SF}
12110 if (CHIP_MODE_IS_4_PORT(bp) &&
12111 !bp->path_has_ovlan &&
12113 bp->common.mf_cfg_base != SHMEM_MF_CFG_ADDR_NONE) {
12114 u8 other_port = !BP_PORT(bp);
12115 u8 other_func = BP_PATH(bp) + 2*other_port;
12116 val = MF_CFG_RD(bp,
12117 func_mf_config[other_func].e1hov_tag);
12118 if (val != FUNC_MF_CFG_E1HOV_TAG_DEFAULT)
12119 bp->path_has_ovlan = true;
12123 /* adjust igu_sb_cnt to MF for E1H */
12124 if (CHIP_IS_E1H(bp) && IS_MF(bp))
12125 bp->igu_sb_cnt = min_t(u8, bp->igu_sb_cnt, E1H_MAX_MF_SB_COUNT);
12128 bnx2x_get_port_hwinfo(bp);
12130 /* Get MAC addresses */
12131 bnx2x_get_mac_hwinfo(bp);
12133 bnx2x_get_cnic_info(bp);
12138 static void bnx2x_read_fwinfo(struct bnx2x *bp)
12140 int cnt, i, block_end, rodi;
12141 char vpd_start[BNX2X_VPD_LEN+1];
12142 char str_id_reg[VENDOR_ID_LEN+1];
12143 char str_id_cap[VENDOR_ID_LEN+1];
12145 char *vpd_extended_data = NULL;
12148 cnt = pci_read_vpd(bp->pdev, 0, BNX2X_VPD_LEN, vpd_start);
12149 memset(bp->fw_ver, 0, sizeof(bp->fw_ver));
12151 if (cnt < BNX2X_VPD_LEN)
12152 goto out_not_found;
12154 /* VPD RO tag should be first tag after identifier string, hence
12155 * we should be able to find it in first BNX2X_VPD_LEN chars
12157 i = pci_vpd_find_tag(vpd_start, 0, BNX2X_VPD_LEN,
12158 PCI_VPD_LRDT_RO_DATA);
12160 goto out_not_found;
12162 block_end = i + PCI_VPD_LRDT_TAG_SIZE +
12163 pci_vpd_lrdt_size(&vpd_start[i]);
12165 i += PCI_VPD_LRDT_TAG_SIZE;
12167 if (block_end > BNX2X_VPD_LEN) {
12168 vpd_extended_data = kmalloc(block_end, GFP_KERNEL);
12169 if (vpd_extended_data == NULL)
12170 goto out_not_found;
12172 /* read rest of vpd image into vpd_extended_data */
12173 memcpy(vpd_extended_data, vpd_start, BNX2X_VPD_LEN);
12174 cnt = pci_read_vpd(bp->pdev, BNX2X_VPD_LEN,
12175 block_end - BNX2X_VPD_LEN,
12176 vpd_extended_data + BNX2X_VPD_LEN);
12177 if (cnt < (block_end - BNX2X_VPD_LEN))
12178 goto out_not_found;
12179 vpd_data = vpd_extended_data;
12181 vpd_data = vpd_start;
12183 /* now vpd_data holds full vpd content in both cases */
12185 rodi = pci_vpd_find_info_keyword(vpd_data, i, block_end,
12186 PCI_VPD_RO_KEYWORD_MFR_ID);
12188 goto out_not_found;
12190 len = pci_vpd_info_field_size(&vpd_data[rodi]);
12192 if (len != VENDOR_ID_LEN)
12193 goto out_not_found;
12195 rodi += PCI_VPD_INFO_FLD_HDR_SIZE;
12197 /* vendor specific info */
12198 snprintf(str_id_reg, VENDOR_ID_LEN + 1, "%04x", PCI_VENDOR_ID_DELL);
12199 snprintf(str_id_cap, VENDOR_ID_LEN + 1, "%04X", PCI_VENDOR_ID_DELL);
12200 if (!strncmp(str_id_reg, &vpd_data[rodi], VENDOR_ID_LEN) ||
12201 !strncmp(str_id_cap, &vpd_data[rodi], VENDOR_ID_LEN)) {
12203 rodi = pci_vpd_find_info_keyword(vpd_data, i, block_end,
12204 PCI_VPD_RO_KEYWORD_VENDOR0);
12206 len = pci_vpd_info_field_size(&vpd_data[rodi]);
12208 rodi += PCI_VPD_INFO_FLD_HDR_SIZE;
12210 if (len < 32 && (len + rodi) <= BNX2X_VPD_LEN) {
12211 memcpy(bp->fw_ver, &vpd_data[rodi], len);
12212 bp->fw_ver[len] = ' ';
12215 kfree(vpd_extended_data);
12219 kfree(vpd_extended_data);
12223 static void bnx2x_set_modes_bitmap(struct bnx2x *bp)
12227 if (CHIP_REV_IS_FPGA(bp))
12228 SET_FLAGS(flags, MODE_FPGA);
12229 else if (CHIP_REV_IS_EMUL(bp))
12230 SET_FLAGS(flags, MODE_EMUL);
12232 SET_FLAGS(flags, MODE_ASIC);
12234 if (CHIP_MODE_IS_4_PORT(bp))
12235 SET_FLAGS(flags, MODE_PORT4);
12237 SET_FLAGS(flags, MODE_PORT2);
12239 if (CHIP_IS_E2(bp))
12240 SET_FLAGS(flags, MODE_E2);
12241 else if (CHIP_IS_E3(bp)) {
12242 SET_FLAGS(flags, MODE_E3);
12243 if (CHIP_REV(bp) == CHIP_REV_Ax)
12244 SET_FLAGS(flags, MODE_E3_A0);
12245 else /*if (CHIP_REV(bp) == CHIP_REV_Bx)*/
12246 SET_FLAGS(flags, MODE_E3_B0 | MODE_COS3);
12250 SET_FLAGS(flags, MODE_MF);
12251 switch (bp->mf_mode) {
12252 case MULTI_FUNCTION_SD:
12253 SET_FLAGS(flags, MODE_MF_SD);
12255 case MULTI_FUNCTION_SI:
12256 SET_FLAGS(flags, MODE_MF_SI);
12258 case MULTI_FUNCTION_AFEX:
12259 SET_FLAGS(flags, MODE_MF_AFEX);
12263 SET_FLAGS(flags, MODE_SF);
12265 #if defined(__LITTLE_ENDIAN)
12266 SET_FLAGS(flags, MODE_LITTLE_ENDIAN);
12267 #else /*(__BIG_ENDIAN)*/
12268 SET_FLAGS(flags, MODE_BIG_ENDIAN);
12270 INIT_MODE_FLAGS(bp) = flags;
12273 static int bnx2x_init_bp(struct bnx2x *bp)
12278 mutex_init(&bp->port.phy_mutex);
12279 mutex_init(&bp->fw_mb_mutex);
12280 mutex_init(&bp->drv_info_mutex);
12281 sema_init(&bp->stats_lock, 1);
12282 bp->drv_info_mng_owner = false;
12283 INIT_LIST_HEAD(&bp->vlan_reg);
12285 INIT_DELAYED_WORK(&bp->sp_task, bnx2x_sp_task);
12286 INIT_DELAYED_WORK(&bp->sp_rtnl_task, bnx2x_sp_rtnl_task);
12287 INIT_DELAYED_WORK(&bp->period_task, bnx2x_period_task);
12288 INIT_DELAYED_WORK(&bp->iov_task, bnx2x_iov_task);
12290 rc = bnx2x_get_hwinfo(bp);
12294 eth_zero_addr(bp->dev->dev_addr);
12297 bnx2x_set_modes_bitmap(bp);
12299 rc = bnx2x_alloc_mem_bp(bp);
12303 bnx2x_read_fwinfo(bp);
12305 func = BP_FUNC(bp);
12307 /* need to reset chip if undi was active */
12308 if (IS_PF(bp) && !BP_NOMCP(bp)) {
12311 SHMEM_RD(bp, func_mb[BP_FW_MB_IDX(bp)].drv_mb_header) &
12312 DRV_MSG_SEQ_NUMBER_MASK;
12313 BNX2X_DEV_INFO("fw_seq 0x%08x\n", bp->fw_seq);
12315 rc = bnx2x_prev_unload(bp);
12317 bnx2x_free_mem_bp(bp);
12322 if (CHIP_REV_IS_FPGA(bp))
12323 dev_err(&bp->pdev->dev, "FPGA detected\n");
12325 if (BP_NOMCP(bp) && (func == 0))
12326 dev_err(&bp->pdev->dev, "MCP disabled, must load devices in order!\n");
12328 bp->disable_tpa = disable_tpa;
12329 bp->disable_tpa |= !!IS_MF_STORAGE_ONLY(bp);
12330 /* Reduce memory usage in kdump environment by disabling TPA */
12331 bp->disable_tpa |= is_kdump_kernel();
12333 /* Set TPA flags */
12334 if (bp->disable_tpa) {
12335 bp->dev->hw_features &= ~NETIF_F_LRO;
12336 bp->dev->features &= ~NETIF_F_LRO;
12339 if (CHIP_IS_E1(bp))
12340 bp->dropless_fc = 0;
12342 bp->dropless_fc = dropless_fc | bnx2x_get_dropless_info(bp);
12346 bp->tx_ring_size = IS_MF_STORAGE_ONLY(bp) ? 0 : MAX_TX_AVAIL;
12348 bp->rx_ring_size = MAX_RX_AVAIL;
12350 /* make sure that the numbers are in the right granularity */
12351 bp->tx_ticks = (50 / BNX2X_BTR) * BNX2X_BTR;
12352 bp->rx_ticks = (25 / BNX2X_BTR) * BNX2X_BTR;
12354 bp->current_interval = CHIP_REV_IS_SLOW(bp) ? 5*HZ : HZ;
12356 init_timer(&bp->timer);
12357 bp->timer.expires = jiffies + bp->current_interval;
12358 bp->timer.data = (unsigned long) bp;
12359 bp->timer.function = bnx2x_timer;
12361 if (SHMEM2_HAS(bp, dcbx_lldp_params_offset) &&
12362 SHMEM2_HAS(bp, dcbx_lldp_dcbx_stat_offset) &&
12363 SHMEM2_RD(bp, dcbx_lldp_params_offset) &&
12364 SHMEM2_RD(bp, dcbx_lldp_dcbx_stat_offset)) {
12365 bnx2x_dcbx_set_state(bp, true, BNX2X_DCBX_ENABLED_ON_NEG_ON);
12366 bnx2x_dcbx_init_params(bp);
12368 bnx2x_dcbx_set_state(bp, false, BNX2X_DCBX_ENABLED_OFF);
12371 if (CHIP_IS_E1x(bp))
12372 bp->cnic_base_cl_id = FP_SB_MAX_E1x;
12374 bp->cnic_base_cl_id = FP_SB_MAX_E2;
12376 /* multiple tx priority */
12379 else if (CHIP_IS_E1x(bp))
12380 bp->max_cos = BNX2X_MULTI_TX_COS_E1X;
12381 else if (CHIP_IS_E2(bp) || CHIP_IS_E3A0(bp))
12382 bp->max_cos = BNX2X_MULTI_TX_COS_E2_E3A0;
12383 else if (CHIP_IS_E3B0(bp))
12384 bp->max_cos = BNX2X_MULTI_TX_COS_E3B0;
12386 BNX2X_ERR("unknown chip %x revision %x\n",
12387 CHIP_NUM(bp), CHIP_REV(bp));
12388 BNX2X_DEV_INFO("set bp->max_cos to %d\n", bp->max_cos);
12390 /* We need at least one default status block for slow-path events,
12391 * second status block for the L2 queue, and a third status block for
12392 * CNIC if supported.
12395 bp->min_msix_vec_cnt = 1;
12396 else if (CNIC_SUPPORT(bp))
12397 bp->min_msix_vec_cnt = 3;
12398 else /* PF w/o cnic */
12399 bp->min_msix_vec_cnt = 2;
12400 BNX2X_DEV_INFO("bp->min_msix_vec_cnt %d", bp->min_msix_vec_cnt);
12402 bp->dump_preset_idx = 1;
12404 if (CHIP_IS_E3B0(bp))
12405 bp->flags |= PTP_SUPPORTED;
12410 /****************************************************************************
12411 * General service functions
12412 ****************************************************************************/
12415 * net_device service functions
12418 /* called with rtnl_lock */
12419 static int bnx2x_open(struct net_device *dev)
12421 struct bnx2x *bp = netdev_priv(dev);
12424 bp->stats_init = true;
12426 netif_carrier_off(dev);
12428 bnx2x_set_power_state(bp, PCI_D0);
12430 /* If parity had happen during the unload, then attentions
12431 * and/or RECOVERY_IN_PROGRES may still be set. In this case we
12432 * want the first function loaded on the current engine to
12433 * complete the recovery.
12434 * Parity recovery is only relevant for PF driver.
12437 int other_engine = BP_PATH(bp) ? 0 : 1;
12438 bool other_load_status, load_status;
12439 bool global = false;
12441 other_load_status = bnx2x_get_load_status(bp, other_engine);
12442 load_status = bnx2x_get_load_status(bp, BP_PATH(bp));
12443 if (!bnx2x_reset_is_done(bp, BP_PATH(bp)) ||
12444 bnx2x_chk_parity_attn(bp, &global, true)) {
12446 /* If there are attentions and they are in a
12447 * global blocks, set the GLOBAL_RESET bit
12448 * regardless whether it will be this function
12449 * that will complete the recovery or not.
12452 bnx2x_set_reset_global(bp);
12454 /* Only the first function on the current
12455 * engine should try to recover in open. In case
12456 * of attentions in global blocks only the first
12457 * in the chip should try to recover.
12459 if ((!load_status &&
12460 (!global || !other_load_status)) &&
12461 bnx2x_trylock_leader_lock(bp) &&
12462 !bnx2x_leader_reset(bp)) {
12463 netdev_info(bp->dev,
12464 "Recovered in open\n");
12468 /* recovery has failed... */
12469 bnx2x_set_power_state(bp, PCI_D3hot);
12470 bp->recovery_state = BNX2X_RECOVERY_FAILED;
12472 BNX2X_ERR("Recovery flow hasn't been properly completed yet. Try again later.\n"
12473 "If you still see this message after a few retries then power cycle is required.\n");
12480 bp->recovery_state = BNX2X_RECOVERY_DONE;
12481 rc = bnx2x_nic_load(bp, LOAD_OPEN);
12485 #ifdef CONFIG_BNX2X_VXLAN
12487 vxlan_get_rx_port(dev);
12493 /* called with rtnl_lock */
12494 static int bnx2x_close(struct net_device *dev)
12496 struct bnx2x *bp = netdev_priv(dev);
12498 /* Unload the driver, release IRQs */
12499 bnx2x_nic_unload(bp, UNLOAD_CLOSE, false);
12504 static int bnx2x_init_mcast_macs_list(struct bnx2x *bp,
12505 struct bnx2x_mcast_ramrod_params *p)
12507 int mc_count = netdev_mc_count(bp->dev);
12508 struct bnx2x_mcast_list_elem *mc_mac =
12509 kcalloc(mc_count, sizeof(*mc_mac), GFP_ATOMIC);
12510 struct netdev_hw_addr *ha;
12515 INIT_LIST_HEAD(&p->mcast_list);
12517 netdev_for_each_mc_addr(ha, bp->dev) {
12518 mc_mac->mac = bnx2x_mc_addr(ha);
12519 list_add_tail(&mc_mac->link, &p->mcast_list);
12523 p->mcast_list_len = mc_count;
12528 static void bnx2x_free_mcast_macs_list(
12529 struct bnx2x_mcast_ramrod_params *p)
12531 struct bnx2x_mcast_list_elem *mc_mac =
12532 list_first_entry(&p->mcast_list, struct bnx2x_mcast_list_elem,
12540 * bnx2x_set_uc_list - configure a new unicast MACs list.
12542 * @bp: driver handle
12544 * We will use zero (0) as a MAC type for these MACs.
12546 static int bnx2x_set_uc_list(struct bnx2x *bp)
12549 struct net_device *dev = bp->dev;
12550 struct netdev_hw_addr *ha;
12551 struct bnx2x_vlan_mac_obj *mac_obj = &bp->sp_objs->mac_obj;
12552 unsigned long ramrod_flags = 0;
12554 /* First schedule a cleanup up of old configuration */
12555 rc = bnx2x_del_all_macs(bp, mac_obj, BNX2X_UC_LIST_MAC, false);
12557 BNX2X_ERR("Failed to schedule DELETE operations: %d\n", rc);
12561 netdev_for_each_uc_addr(ha, dev) {
12562 rc = bnx2x_set_mac_one(bp, bnx2x_uc_addr(ha), mac_obj, true,
12563 BNX2X_UC_LIST_MAC, &ramrod_flags);
12564 if (rc == -EEXIST) {
12566 "Failed to schedule ADD operations: %d\n", rc);
12567 /* do not treat adding same MAC as error */
12570 } else if (rc < 0) {
12572 BNX2X_ERR("Failed to schedule ADD operations: %d\n",
12578 /* Execute the pending commands */
12579 __set_bit(RAMROD_CONT, &ramrod_flags);
12580 return bnx2x_set_mac_one(bp, NULL, mac_obj, false /* don't care */,
12581 BNX2X_UC_LIST_MAC, &ramrod_flags);
12584 static int bnx2x_set_mc_list(struct bnx2x *bp)
12586 struct net_device *dev = bp->dev;
12587 struct bnx2x_mcast_ramrod_params rparam = {NULL};
12590 rparam.mcast_obj = &bp->mcast_obj;
12592 /* first, clear all configured multicast MACs */
12593 rc = bnx2x_config_mcast(bp, &rparam, BNX2X_MCAST_CMD_DEL);
12595 BNX2X_ERR("Failed to clear multicast configuration: %d\n", rc);
12599 /* then, configure a new MACs list */
12600 if (netdev_mc_count(dev)) {
12601 rc = bnx2x_init_mcast_macs_list(bp, &rparam);
12603 BNX2X_ERR("Failed to create multicast MACs list: %d\n",
12608 /* Now add the new MACs */
12609 rc = bnx2x_config_mcast(bp, &rparam,
12610 BNX2X_MCAST_CMD_ADD);
12612 BNX2X_ERR("Failed to set a new multicast configuration: %d\n",
12615 bnx2x_free_mcast_macs_list(&rparam);
12621 /* If bp->state is OPEN, should be called with netif_addr_lock_bh() */
12622 static void bnx2x_set_rx_mode(struct net_device *dev)
12624 struct bnx2x *bp = netdev_priv(dev);
12626 if (bp->state != BNX2X_STATE_OPEN) {
12627 DP(NETIF_MSG_IFUP, "state is %x, returning\n", bp->state);
12630 /* Schedule an SP task to handle rest of change */
12631 bnx2x_schedule_sp_rtnl(bp, BNX2X_SP_RTNL_RX_MODE,
12636 void bnx2x_set_rx_mode_inner(struct bnx2x *bp)
12638 u32 rx_mode = BNX2X_RX_MODE_NORMAL;
12640 DP(NETIF_MSG_IFUP, "dev->flags = %x\n", bp->dev->flags);
12642 netif_addr_lock_bh(bp->dev);
12644 if (bp->dev->flags & IFF_PROMISC) {
12645 rx_mode = BNX2X_RX_MODE_PROMISC;
12646 } else if ((bp->dev->flags & IFF_ALLMULTI) ||
12647 ((netdev_mc_count(bp->dev) > BNX2X_MAX_MULTICAST) &&
12649 rx_mode = BNX2X_RX_MODE_ALLMULTI;
12652 /* some multicasts */
12653 if (bnx2x_set_mc_list(bp) < 0)
12654 rx_mode = BNX2X_RX_MODE_ALLMULTI;
12656 /* release bh lock, as bnx2x_set_uc_list might sleep */
12657 netif_addr_unlock_bh(bp->dev);
12658 if (bnx2x_set_uc_list(bp) < 0)
12659 rx_mode = BNX2X_RX_MODE_PROMISC;
12660 netif_addr_lock_bh(bp->dev);
12662 /* configuring mcast to a vf involves sleeping (when we
12663 * wait for the pf's response).
12665 bnx2x_schedule_sp_rtnl(bp,
12666 BNX2X_SP_RTNL_VFPF_MCAST, 0);
12670 bp->rx_mode = rx_mode;
12671 /* handle ISCSI SD mode */
12672 if (IS_MF_ISCSI_ONLY(bp))
12673 bp->rx_mode = BNX2X_RX_MODE_NONE;
12675 /* Schedule the rx_mode command */
12676 if (test_bit(BNX2X_FILTER_RX_MODE_PENDING, &bp->sp_state)) {
12677 set_bit(BNX2X_FILTER_RX_MODE_SCHED, &bp->sp_state);
12678 netif_addr_unlock_bh(bp->dev);
12683 bnx2x_set_storm_rx_mode(bp);
12684 netif_addr_unlock_bh(bp->dev);
12686 /* VF will need to request the PF to make this change, and so
12687 * the VF needs to release the bottom-half lock prior to the
12688 * request (as it will likely require sleep on the VF side)
12690 netif_addr_unlock_bh(bp->dev);
12691 bnx2x_vfpf_storm_rx_mode(bp);
12695 /* called with rtnl_lock */
12696 static int bnx2x_mdio_read(struct net_device *netdev, int prtad,
12697 int devad, u16 addr)
12699 struct bnx2x *bp = netdev_priv(netdev);
12703 DP(NETIF_MSG_LINK, "mdio_read: prtad 0x%x, devad 0x%x, addr 0x%x\n",
12704 prtad, devad, addr);
12706 /* The HW expects different devad if CL22 is used */
12707 devad = (devad == MDIO_DEVAD_NONE) ? DEFAULT_PHY_DEV_ADDR : devad;
12709 bnx2x_acquire_phy_lock(bp);
12710 rc = bnx2x_phy_read(&bp->link_params, prtad, devad, addr, &value);
12711 bnx2x_release_phy_lock(bp);
12712 DP(NETIF_MSG_LINK, "mdio_read_val 0x%x rc = 0x%x\n", value, rc);
12719 /* called with rtnl_lock */
12720 static int bnx2x_mdio_write(struct net_device *netdev, int prtad, int devad,
12721 u16 addr, u16 value)
12723 struct bnx2x *bp = netdev_priv(netdev);
12727 "mdio_write: prtad 0x%x, devad 0x%x, addr 0x%x, value 0x%x\n",
12728 prtad, devad, addr, value);
12730 /* The HW expects different devad if CL22 is used */
12731 devad = (devad == MDIO_DEVAD_NONE) ? DEFAULT_PHY_DEV_ADDR : devad;
12733 bnx2x_acquire_phy_lock(bp);
12734 rc = bnx2x_phy_write(&bp->link_params, prtad, devad, addr, value);
12735 bnx2x_release_phy_lock(bp);
12739 /* called with rtnl_lock */
12740 static int bnx2x_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
12742 struct bnx2x *bp = netdev_priv(dev);
12743 struct mii_ioctl_data *mdio = if_mii(ifr);
12745 if (!netif_running(dev))
12749 case SIOCSHWTSTAMP:
12750 return bnx2x_hwtstamp_ioctl(bp, ifr);
12752 DP(NETIF_MSG_LINK, "ioctl: phy id 0x%x, reg 0x%x, val_in 0x%x\n",
12753 mdio->phy_id, mdio->reg_num, mdio->val_in);
12754 return mdio_mii_ioctl(&bp->mdio, mdio, cmd);
12758 #ifdef CONFIG_NET_POLL_CONTROLLER
12759 static void poll_bnx2x(struct net_device *dev)
12761 struct bnx2x *bp = netdev_priv(dev);
12764 for_each_eth_queue(bp, i) {
12765 struct bnx2x_fastpath *fp = &bp->fp[i];
12766 napi_schedule(&bnx2x_fp(bp, fp->index, napi));
12771 static int bnx2x_validate_addr(struct net_device *dev)
12773 struct bnx2x *bp = netdev_priv(dev);
12775 /* query the bulletin board for mac address configured by the PF */
12777 bnx2x_sample_bulletin(bp);
12779 if (!is_valid_ether_addr(dev->dev_addr)) {
12780 BNX2X_ERR("Non-valid Ethernet address\n");
12781 return -EADDRNOTAVAIL;
12786 static int bnx2x_get_phys_port_id(struct net_device *netdev,
12787 struct netdev_phys_item_id *ppid)
12789 struct bnx2x *bp = netdev_priv(netdev);
12791 if (!(bp->flags & HAS_PHYS_PORT_ID))
12792 return -EOPNOTSUPP;
12794 ppid->id_len = sizeof(bp->phys_port_id);
12795 memcpy(ppid->id, bp->phys_port_id, ppid->id_len);
12800 static netdev_features_t bnx2x_features_check(struct sk_buff *skb,
12801 struct net_device *dev,
12802 netdev_features_t features)
12804 features = vlan_features_check(skb, features);
12805 return vxlan_features_check(skb, features);
12808 static int __bnx2x_vlan_configure_vid(struct bnx2x *bp, u16 vid, bool add)
12813 unsigned long ramrod_flags = 0;
12815 __set_bit(RAMROD_COMP_WAIT, &ramrod_flags);
12816 rc = bnx2x_set_vlan_one(bp, vid, &bp->sp_objs->vlan_obj,
12817 add, &ramrod_flags);
12819 rc = bnx2x_vfpf_update_vlan(bp, vid, bp->fp->index, add);
12825 int bnx2x_vlan_reconfigure_vid(struct bnx2x *bp)
12827 struct bnx2x_vlan_entry *vlan;
12830 if (!bp->vlan_cnt) {
12831 DP(NETIF_MSG_IFUP, "No need to re-configure vlan filters\n");
12835 list_for_each_entry(vlan, &bp->vlan_reg, link) {
12836 /* Prepare for cleanup in case of errors */
12845 DP(NETIF_MSG_IFUP, "Re-configuring vlan 0x%04x\n", vlan->vid);
12847 rc = __bnx2x_vlan_configure_vid(bp, vlan->vid, true);
12849 BNX2X_ERR("Unable to configure VLAN %d\n", vlan->vid);
12859 static int bnx2x_vlan_rx_add_vid(struct net_device *dev, __be16 proto, u16 vid)
12861 struct bnx2x *bp = netdev_priv(dev);
12862 struct bnx2x_vlan_entry *vlan;
12866 if (!netif_running(bp->dev)) {
12868 "Ignoring VLAN configuration the interface is down\n");
12872 DP(NETIF_MSG_IFUP, "Adding VLAN %d\n", vid);
12874 vlan = kmalloc(sizeof(*vlan), GFP_KERNEL);
12879 if (bp->vlan_cnt > bp->vlan_credit && !bp->accept_any_vlan) {
12880 DP(NETIF_MSG_IFUP, "Accept all VLAN raised\n");
12881 bp->accept_any_vlan = true;
12883 bnx2x_set_rx_mode_inner(bp);
12885 bnx2x_vfpf_storm_rx_mode(bp);
12886 } else if (bp->vlan_cnt <= bp->vlan_credit) {
12887 rc = __bnx2x_vlan_configure_vid(bp, vid, true);
12895 list_add(&vlan->link, &bp->vlan_reg);
12901 DP(NETIF_MSG_IFUP, "Adding VLAN result %d\n", rc);
12906 static int bnx2x_vlan_rx_kill_vid(struct net_device *dev, __be16 proto, u16 vid)
12908 struct bnx2x *bp = netdev_priv(dev);
12909 struct bnx2x_vlan_entry *vlan;
12912 if (!netif_running(bp->dev)) {
12914 "Ignoring VLAN configuration the interface is down\n");
12918 DP(NETIF_MSG_IFUP, "Removing VLAN %d\n", vid);
12920 if (!bp->vlan_cnt) {
12921 BNX2X_ERR("Unable to kill VLAN %d\n", vid);
12925 list_for_each_entry(vlan, &bp->vlan_reg, link)
12926 if (vlan->vid == vid)
12929 if (vlan->vid != vid) {
12930 BNX2X_ERR("Unable to kill VLAN %d - not found\n", vid);
12935 rc = __bnx2x_vlan_configure_vid(bp, vid, false);
12937 list_del(&vlan->link);
12942 if (bp->vlan_cnt <= bp->vlan_credit && bp->accept_any_vlan) {
12943 /* Configure all non-configured entries */
12944 list_for_each_entry(vlan, &bp->vlan_reg, link) {
12948 rc = __bnx2x_vlan_configure_vid(bp, vlan->vid, true);
12950 BNX2X_ERR("Unable to config VLAN %d\n",
12954 DP(NETIF_MSG_IFUP, "HW configured for VLAN %d\n",
12958 DP(NETIF_MSG_IFUP, "Accept all VLAN Removed\n");
12959 bp->accept_any_vlan = false;
12961 bnx2x_set_rx_mode_inner(bp);
12963 bnx2x_vfpf_storm_rx_mode(bp);
12966 DP(NETIF_MSG_IFUP, "Removing VLAN result %d\n", rc);
12971 static const struct net_device_ops bnx2x_netdev_ops = {
12972 .ndo_open = bnx2x_open,
12973 .ndo_stop = bnx2x_close,
12974 .ndo_start_xmit = bnx2x_start_xmit,
12975 .ndo_select_queue = bnx2x_select_queue,
12976 .ndo_set_rx_mode = bnx2x_set_rx_mode,
12977 .ndo_set_mac_address = bnx2x_change_mac_addr,
12978 .ndo_validate_addr = bnx2x_validate_addr,
12979 .ndo_do_ioctl = bnx2x_ioctl,
12980 .ndo_change_mtu = bnx2x_change_mtu,
12981 .ndo_fix_features = bnx2x_fix_features,
12982 .ndo_set_features = bnx2x_set_features,
12983 .ndo_tx_timeout = bnx2x_tx_timeout,
12984 .ndo_vlan_rx_add_vid = bnx2x_vlan_rx_add_vid,
12985 .ndo_vlan_rx_kill_vid = bnx2x_vlan_rx_kill_vid,
12986 #ifdef CONFIG_NET_POLL_CONTROLLER
12987 .ndo_poll_controller = poll_bnx2x,
12989 .ndo_setup_tc = bnx2x_setup_tc,
12990 #ifdef CONFIG_BNX2X_SRIOV
12991 .ndo_set_vf_mac = bnx2x_set_vf_mac,
12992 .ndo_set_vf_vlan = bnx2x_set_vf_vlan,
12993 .ndo_get_vf_config = bnx2x_get_vf_config,
12995 #ifdef NETDEV_FCOE_WWNN
12996 .ndo_fcoe_get_wwn = bnx2x_fcoe_get_wwn,
12999 #ifdef CONFIG_NET_RX_BUSY_POLL
13000 .ndo_busy_poll = bnx2x_low_latency_recv,
13002 .ndo_get_phys_port_id = bnx2x_get_phys_port_id,
13003 .ndo_set_vf_link_state = bnx2x_set_vf_link_state,
13004 .ndo_features_check = bnx2x_features_check,
13005 #ifdef CONFIG_BNX2X_VXLAN
13006 .ndo_add_vxlan_port = bnx2x_add_vxlan_port,
13007 .ndo_del_vxlan_port = bnx2x_del_vxlan_port,
13011 static int bnx2x_set_coherency_mask(struct bnx2x *bp)
13013 struct device *dev = &bp->pdev->dev;
13015 if (dma_set_mask_and_coherent(dev, DMA_BIT_MASK(64)) != 0 &&
13016 dma_set_mask_and_coherent(dev, DMA_BIT_MASK(32)) != 0) {
13017 dev_err(dev, "System does not support DMA, aborting\n");
13024 static void bnx2x_disable_pcie_error_reporting(struct bnx2x *bp)
13026 if (bp->flags & AER_ENABLED) {
13027 pci_disable_pcie_error_reporting(bp->pdev);
13028 bp->flags &= ~AER_ENABLED;
13032 static int bnx2x_init_dev(struct bnx2x *bp, struct pci_dev *pdev,
13033 struct net_device *dev, unsigned long board_type)
13037 bool chip_is_e1x = (board_type == BCM57710 ||
13038 board_type == BCM57711 ||
13039 board_type == BCM57711E);
13041 SET_NETDEV_DEV(dev, &pdev->dev);
13046 rc = pci_enable_device(pdev);
13048 dev_err(&bp->pdev->dev,
13049 "Cannot enable PCI device, aborting\n");
13053 if (!(pci_resource_flags(pdev, 0) & IORESOURCE_MEM)) {
13054 dev_err(&bp->pdev->dev,
13055 "Cannot find PCI device base address, aborting\n");
13057 goto err_out_disable;
13060 if (IS_PF(bp) && !(pci_resource_flags(pdev, 2) & IORESOURCE_MEM)) {
13061 dev_err(&bp->pdev->dev, "Cannot find second PCI device base address, aborting\n");
13063 goto err_out_disable;
13066 pci_read_config_dword(pdev, PCICFG_REVISION_ID_OFFSET, &pci_cfg_dword);
13067 if ((pci_cfg_dword & PCICFG_REVESION_ID_MASK) ==
13068 PCICFG_REVESION_ID_ERROR_VAL) {
13069 pr_err("PCI device error, probably due to fan failure, aborting\n");
13071 goto err_out_disable;
13074 if (atomic_read(&pdev->enable_cnt) == 1) {
13075 rc = pci_request_regions(pdev, DRV_MODULE_NAME);
13077 dev_err(&bp->pdev->dev,
13078 "Cannot obtain PCI resources, aborting\n");
13079 goto err_out_disable;
13082 pci_set_master(pdev);
13083 pci_save_state(pdev);
13087 if (!pdev->pm_cap) {
13088 dev_err(&bp->pdev->dev,
13089 "Cannot find power management capability, aborting\n");
13091 goto err_out_release;
13095 if (!pci_is_pcie(pdev)) {
13096 dev_err(&bp->pdev->dev, "Not PCI Express, aborting\n");
13098 goto err_out_release;
13101 rc = bnx2x_set_coherency_mask(bp);
13103 goto err_out_release;
13105 dev->mem_start = pci_resource_start(pdev, 0);
13106 dev->base_addr = dev->mem_start;
13107 dev->mem_end = pci_resource_end(pdev, 0);
13109 dev->irq = pdev->irq;
13111 bp->regview = pci_ioremap_bar(pdev, 0);
13112 if (!bp->regview) {
13113 dev_err(&bp->pdev->dev,
13114 "Cannot map register space, aborting\n");
13116 goto err_out_release;
13119 /* In E1/E1H use pci device function given by kernel.
13120 * In E2/E3 read physical function from ME register since these chips
13121 * support Physical Device Assignment where kernel BDF maybe arbitrary
13122 * (depending on hypervisor).
13125 bp->pf_num = PCI_FUNC(pdev->devfn);
13128 pci_read_config_dword(bp->pdev,
13129 PCICFG_ME_REGISTER, &pci_cfg_dword);
13130 bp->pf_num = (u8)((pci_cfg_dword & ME_REG_ABS_PF_NUM) >>
13131 ME_REG_ABS_PF_NUM_SHIFT);
13133 BNX2X_DEV_INFO("me reg PF num: %d\n", bp->pf_num);
13135 /* clean indirect addresses */
13136 pci_write_config_dword(bp->pdev, PCICFG_GRC_ADDRESS,
13137 PCICFG_VENDOR_ID_OFFSET);
13139 /* Set PCIe reset type to fundamental for EEH recovery */
13140 pdev->needs_freset = 1;
13142 /* AER (Advanced Error reporting) configuration */
13143 rc = pci_enable_pcie_error_reporting(pdev);
13145 bp->flags |= AER_ENABLED;
13147 BNX2X_DEV_INFO("Failed To configure PCIe AER [%d]\n", rc);
13150 * Clean the following indirect addresses for all functions since it
13151 * is not used by the driver.
13154 REG_WR(bp, PXP2_REG_PGL_ADDR_88_F0, 0);
13155 REG_WR(bp, PXP2_REG_PGL_ADDR_8C_F0, 0);
13156 REG_WR(bp, PXP2_REG_PGL_ADDR_90_F0, 0);
13157 REG_WR(bp, PXP2_REG_PGL_ADDR_94_F0, 0);
13160 REG_WR(bp, PXP2_REG_PGL_ADDR_88_F1, 0);
13161 REG_WR(bp, PXP2_REG_PGL_ADDR_8C_F1, 0);
13162 REG_WR(bp, PXP2_REG_PGL_ADDR_90_F1, 0);
13163 REG_WR(bp, PXP2_REG_PGL_ADDR_94_F1, 0);
13166 /* Enable internal target-read (in case we are probed after PF
13167 * FLR). Must be done prior to any BAR read access. Only for
13172 PGLUE_B_REG_INTERNAL_PFID_ENABLE_TARGET_READ, 1);
13175 dev->watchdog_timeo = TX_TIMEOUT;
13177 dev->netdev_ops = &bnx2x_netdev_ops;
13178 bnx2x_set_ethtool_ops(bp, dev);
13180 dev->priv_flags |= IFF_UNICAST_FLT;
13182 dev->hw_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM |
13183 NETIF_F_TSO | NETIF_F_TSO_ECN | NETIF_F_TSO6 |
13184 NETIF_F_RXCSUM | NETIF_F_LRO | NETIF_F_GRO |
13185 NETIF_F_RXHASH | NETIF_F_HW_VLAN_CTAG_TX;
13186 if (!chip_is_e1x) {
13187 dev->hw_features |= NETIF_F_GSO_GRE | NETIF_F_GSO_UDP_TUNNEL |
13188 NETIF_F_GSO_IPIP | NETIF_F_GSO_SIT;
13189 dev->hw_enc_features =
13190 NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM | NETIF_F_SG |
13191 NETIF_F_TSO | NETIF_F_TSO_ECN | NETIF_F_TSO6 |
13194 NETIF_F_GSO_GRE | NETIF_F_GSO_UDP_TUNNEL;
13197 dev->vlan_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM |
13198 NETIF_F_TSO | NETIF_F_TSO_ECN | NETIF_F_TSO6 | NETIF_F_HIGHDMA;
13200 /* VF with OLD Hypervisor or old PF do not support filtering */
13202 if (CHIP_IS_E1x(bp))
13203 bp->accept_any_vlan = true;
13205 dev->hw_features |= NETIF_F_HW_VLAN_CTAG_FILTER;
13206 #ifdef CONFIG_BNX2X_SRIOV
13207 } else if (bp->acquire_resp.pfdev_info.pf_cap & PFVF_CAP_VLAN_FILTER) {
13208 dev->hw_features |= NETIF_F_HW_VLAN_CTAG_FILTER;
13212 dev->features |= dev->hw_features | NETIF_F_HW_VLAN_CTAG_RX;
13213 dev->features |= NETIF_F_HIGHDMA;
13215 /* Add Loopback capability to the device */
13216 dev->hw_features |= NETIF_F_LOOPBACK;
13219 dev->dcbnl_ops = &bnx2x_dcbnl_ops;
13222 /* get_port_hwinfo() will set prtad and mmds properly */
13223 bp->mdio.prtad = MDIO_PRTAD_NONE;
13225 bp->mdio.mode_support = MDIO_SUPPORTS_C45 | MDIO_EMULATE_C22;
13226 bp->mdio.dev = dev;
13227 bp->mdio.mdio_read = bnx2x_mdio_read;
13228 bp->mdio.mdio_write = bnx2x_mdio_write;
13233 if (atomic_read(&pdev->enable_cnt) == 1)
13234 pci_release_regions(pdev);
13237 pci_disable_device(pdev);
13243 static int bnx2x_check_firmware(struct bnx2x *bp)
13245 const struct firmware *firmware = bp->firmware;
13246 struct bnx2x_fw_file_hdr *fw_hdr;
13247 struct bnx2x_fw_file_section *sections;
13248 u32 offset, len, num_ops;
13249 __be16 *ops_offsets;
13253 if (firmware->size < sizeof(struct bnx2x_fw_file_hdr)) {
13254 BNX2X_ERR("Wrong FW size\n");
13258 fw_hdr = (struct bnx2x_fw_file_hdr *)firmware->data;
13259 sections = (struct bnx2x_fw_file_section *)fw_hdr;
13261 /* Make sure none of the offsets and sizes make us read beyond
13262 * the end of the firmware data */
13263 for (i = 0; i < sizeof(*fw_hdr) / sizeof(*sections); i++) {
13264 offset = be32_to_cpu(sections[i].offset);
13265 len = be32_to_cpu(sections[i].len);
13266 if (offset + len > firmware->size) {
13267 BNX2X_ERR("Section %d length is out of bounds\n", i);
13272 /* Likewise for the init_ops offsets */
13273 offset = be32_to_cpu(fw_hdr->init_ops_offsets.offset);
13274 ops_offsets = (__force __be16 *)(firmware->data + offset);
13275 num_ops = be32_to_cpu(fw_hdr->init_ops.len) / sizeof(struct raw_op);
13277 for (i = 0; i < be32_to_cpu(fw_hdr->init_ops_offsets.len) / 2; i++) {
13278 if (be16_to_cpu(ops_offsets[i]) > num_ops) {
13279 BNX2X_ERR("Section offset %d is out of bounds\n", i);
13284 /* Check FW version */
13285 offset = be32_to_cpu(fw_hdr->fw_version.offset);
13286 fw_ver = firmware->data + offset;
13287 if ((fw_ver[0] != BCM_5710_FW_MAJOR_VERSION) ||
13288 (fw_ver[1] != BCM_5710_FW_MINOR_VERSION) ||
13289 (fw_ver[2] != BCM_5710_FW_REVISION_VERSION) ||
13290 (fw_ver[3] != BCM_5710_FW_ENGINEERING_VERSION)) {
13291 BNX2X_ERR("Bad FW version:%d.%d.%d.%d. Should be %d.%d.%d.%d\n",
13292 fw_ver[0], fw_ver[1], fw_ver[2], fw_ver[3],
13293 BCM_5710_FW_MAJOR_VERSION,
13294 BCM_5710_FW_MINOR_VERSION,
13295 BCM_5710_FW_REVISION_VERSION,
13296 BCM_5710_FW_ENGINEERING_VERSION);
13303 static void be32_to_cpu_n(const u8 *_source, u8 *_target, u32 n)
13305 const __be32 *source = (const __be32 *)_source;
13306 u32 *target = (u32 *)_target;
13309 for (i = 0; i < n/4; i++)
13310 target[i] = be32_to_cpu(source[i]);
13314 Ops array is stored in the following format:
13315 {op(8bit), offset(24bit, big endian), data(32bit, big endian)}
13317 static void bnx2x_prep_ops(const u8 *_source, u8 *_target, u32 n)
13319 const __be32 *source = (const __be32 *)_source;
13320 struct raw_op *target = (struct raw_op *)_target;
13323 for (i = 0, j = 0; i < n/8; i++, j += 2) {
13324 tmp = be32_to_cpu(source[j]);
13325 target[i].op = (tmp >> 24) & 0xff;
13326 target[i].offset = tmp & 0xffffff;
13327 target[i].raw_data = be32_to_cpu(source[j + 1]);
13331 /* IRO array is stored in the following format:
13332 * {base(24bit), m1(16bit), m2(16bit), m3(16bit), size(16bit) }
13334 static void bnx2x_prep_iro(const u8 *_source, u8 *_target, u32 n)
13336 const __be32 *source = (const __be32 *)_source;
13337 struct iro *target = (struct iro *)_target;
13340 for (i = 0, j = 0; i < n/sizeof(struct iro); i++) {
13341 target[i].base = be32_to_cpu(source[j]);
13343 tmp = be32_to_cpu(source[j]);
13344 target[i].m1 = (tmp >> 16) & 0xffff;
13345 target[i].m2 = tmp & 0xffff;
13347 tmp = be32_to_cpu(source[j]);
13348 target[i].m3 = (tmp >> 16) & 0xffff;
13349 target[i].size = tmp & 0xffff;
13354 static void be16_to_cpu_n(const u8 *_source, u8 *_target, u32 n)
13356 const __be16 *source = (const __be16 *)_source;
13357 u16 *target = (u16 *)_target;
13360 for (i = 0; i < n/2; i++)
13361 target[i] = be16_to_cpu(source[i]);
13364 #define BNX2X_ALLOC_AND_SET(arr, lbl, func) \
13366 u32 len = be32_to_cpu(fw_hdr->arr.len); \
13367 bp->arr = kmalloc(len, GFP_KERNEL); \
13370 func(bp->firmware->data + be32_to_cpu(fw_hdr->arr.offset), \
13371 (u8 *)bp->arr, len); \
13374 static int bnx2x_init_firmware(struct bnx2x *bp)
13376 const char *fw_file_name;
13377 struct bnx2x_fw_file_hdr *fw_hdr;
13383 if (CHIP_IS_E1(bp))
13384 fw_file_name = FW_FILE_NAME_E1;
13385 else if (CHIP_IS_E1H(bp))
13386 fw_file_name = FW_FILE_NAME_E1H;
13387 else if (!CHIP_IS_E1x(bp))
13388 fw_file_name = FW_FILE_NAME_E2;
13390 BNX2X_ERR("Unsupported chip revision\n");
13393 BNX2X_DEV_INFO("Loading %s\n", fw_file_name);
13395 rc = request_firmware(&bp->firmware, fw_file_name, &bp->pdev->dev);
13397 BNX2X_ERR("Can't load firmware file %s\n",
13399 goto request_firmware_exit;
13402 rc = bnx2x_check_firmware(bp);
13404 BNX2X_ERR("Corrupt firmware file %s\n", fw_file_name);
13405 goto request_firmware_exit;
13408 fw_hdr = (struct bnx2x_fw_file_hdr *)bp->firmware->data;
13410 /* Initialize the pointers to the init arrays */
13412 BNX2X_ALLOC_AND_SET(init_data, request_firmware_exit, be32_to_cpu_n);
13415 BNX2X_ALLOC_AND_SET(init_ops, init_ops_alloc_err, bnx2x_prep_ops);
13418 BNX2X_ALLOC_AND_SET(init_ops_offsets, init_offsets_alloc_err,
13421 /* STORMs firmware */
13422 INIT_TSEM_INT_TABLE_DATA(bp) = bp->firmware->data +
13423 be32_to_cpu(fw_hdr->tsem_int_table_data.offset);
13424 INIT_TSEM_PRAM_DATA(bp) = bp->firmware->data +
13425 be32_to_cpu(fw_hdr->tsem_pram_data.offset);
13426 INIT_USEM_INT_TABLE_DATA(bp) = bp->firmware->data +
13427 be32_to_cpu(fw_hdr->usem_int_table_data.offset);
13428 INIT_USEM_PRAM_DATA(bp) = bp->firmware->data +
13429 be32_to_cpu(fw_hdr->usem_pram_data.offset);
13430 INIT_XSEM_INT_TABLE_DATA(bp) = bp->firmware->data +
13431 be32_to_cpu(fw_hdr->xsem_int_table_data.offset);
13432 INIT_XSEM_PRAM_DATA(bp) = bp->firmware->data +
13433 be32_to_cpu(fw_hdr->xsem_pram_data.offset);
13434 INIT_CSEM_INT_TABLE_DATA(bp) = bp->firmware->data +
13435 be32_to_cpu(fw_hdr->csem_int_table_data.offset);
13436 INIT_CSEM_PRAM_DATA(bp) = bp->firmware->data +
13437 be32_to_cpu(fw_hdr->csem_pram_data.offset);
13439 BNX2X_ALLOC_AND_SET(iro_arr, iro_alloc_err, bnx2x_prep_iro);
13444 kfree(bp->init_ops_offsets);
13445 init_offsets_alloc_err:
13446 kfree(bp->init_ops);
13447 init_ops_alloc_err:
13448 kfree(bp->init_data);
13449 request_firmware_exit:
13450 release_firmware(bp->firmware);
13451 bp->firmware = NULL;
13456 static void bnx2x_release_firmware(struct bnx2x *bp)
13458 kfree(bp->init_ops_offsets);
13459 kfree(bp->init_ops);
13460 kfree(bp->init_data);
13461 release_firmware(bp->firmware);
13462 bp->firmware = NULL;
13465 static struct bnx2x_func_sp_drv_ops bnx2x_func_sp_drv = {
13466 .init_hw_cmn_chip = bnx2x_init_hw_common_chip,
13467 .init_hw_cmn = bnx2x_init_hw_common,
13468 .init_hw_port = bnx2x_init_hw_port,
13469 .init_hw_func = bnx2x_init_hw_func,
13471 .reset_hw_cmn = bnx2x_reset_common,
13472 .reset_hw_port = bnx2x_reset_port,
13473 .reset_hw_func = bnx2x_reset_func,
13475 .gunzip_init = bnx2x_gunzip_init,
13476 .gunzip_end = bnx2x_gunzip_end,
13478 .init_fw = bnx2x_init_firmware,
13479 .release_fw = bnx2x_release_firmware,
13482 void bnx2x__init_func_obj(struct bnx2x *bp)
13484 /* Prepare DMAE related driver resources */
13485 bnx2x_setup_dmae(bp);
13487 bnx2x_init_func_obj(bp, &bp->func_obj,
13488 bnx2x_sp(bp, func_rdata),
13489 bnx2x_sp_mapping(bp, func_rdata),
13490 bnx2x_sp(bp, func_afex_rdata),
13491 bnx2x_sp_mapping(bp, func_afex_rdata),
13492 &bnx2x_func_sp_drv);
13495 /* must be called after sriov-enable */
13496 static int bnx2x_set_qm_cid_count(struct bnx2x *bp)
13498 int cid_count = BNX2X_L2_MAX_CID(bp);
13501 cid_count += BNX2X_VF_CIDS;
13503 if (CNIC_SUPPORT(bp))
13504 cid_count += CNIC_CID_MAX;
13506 return roundup(cid_count, QM_CID_ROUND);
13510 * bnx2x_get_num_none_def_sbs - return the number of none default SBs
13515 static int bnx2x_get_num_non_def_sbs(struct pci_dev *pdev, int cnic_cnt)
13521 * If MSI-X is not supported - return number of SBs needed to support
13522 * one fast path queue: one FP queue + SB for CNIC
13524 if (!pdev->msix_cap) {
13525 dev_info(&pdev->dev, "no msix capability found\n");
13526 return 1 + cnic_cnt;
13528 dev_info(&pdev->dev, "msix capability found\n");
13531 * The value in the PCI configuration space is the index of the last
13532 * entry, namely one less than the actual size of the table, which is
13533 * exactly what we want to return from this function: number of all SBs
13534 * without the default SB.
13535 * For VFs there is no default SB, then we return (index+1).
13537 pci_read_config_word(pdev, pdev->msix_cap + PCI_MSIX_FLAGS, &control);
13539 index = control & PCI_MSIX_FLAGS_QSIZE;
13544 static int set_max_cos_est(int chip_id)
13550 return BNX2X_MULTI_TX_COS_E1X;
13553 return BNX2X_MULTI_TX_COS_E2_E3A0;
13558 case BCM57840_4_10:
13559 case BCM57840_2_20:
13565 return BNX2X_MULTI_TX_COS_E3B0;
13573 pr_err("Unknown board_type (%d), aborting\n", chip_id);
13578 static int set_is_vf(int chip_id)
13592 /* nig_tsgen registers relative address */
13593 #define tsgen_ctrl 0x0
13594 #define tsgen_freecount 0x10
13595 #define tsgen_synctime_t0 0x20
13596 #define tsgen_offset_t0 0x28
13597 #define tsgen_drift_t0 0x30
13598 #define tsgen_synctime_t1 0x58
13599 #define tsgen_offset_t1 0x60
13600 #define tsgen_drift_t1 0x68
13602 /* FW workaround for setting drift */
13603 static int bnx2x_send_update_drift_ramrod(struct bnx2x *bp, int drift_dir,
13604 int best_val, int best_period)
13606 struct bnx2x_func_state_params func_params = {NULL};
13607 struct bnx2x_func_set_timesync_params *set_timesync_params =
13608 &func_params.params.set_timesync;
13610 /* Prepare parameters for function state transitions */
13611 __set_bit(RAMROD_COMP_WAIT, &func_params.ramrod_flags);
13612 __set_bit(RAMROD_RETRY, &func_params.ramrod_flags);
13614 func_params.f_obj = &bp->func_obj;
13615 func_params.cmd = BNX2X_F_CMD_SET_TIMESYNC;
13617 /* Function parameters */
13618 set_timesync_params->drift_adjust_cmd = TS_DRIFT_ADJUST_SET;
13619 set_timesync_params->offset_cmd = TS_OFFSET_KEEP;
13620 set_timesync_params->add_sub_drift_adjust_value =
13621 drift_dir ? TS_ADD_VALUE : TS_SUB_VALUE;
13622 set_timesync_params->drift_adjust_value = best_val;
13623 set_timesync_params->drift_adjust_period = best_period;
13625 return bnx2x_func_state_change(bp, &func_params);
13628 static int bnx2x_ptp_adjfreq(struct ptp_clock_info *ptp, s32 ppb)
13630 struct bnx2x *bp = container_of(ptp, struct bnx2x, ptp_clock_info);
13633 int val, period, period1, period2, dif, dif1, dif2;
13634 int best_dif = BNX2X_MAX_PHC_DRIFT, best_period = 0, best_val = 0;
13636 DP(BNX2X_MSG_PTP, "PTP adjfreq called, ppb = %d\n", ppb);
13638 if (!netif_running(bp->dev)) {
13640 "PTP adjfreq called while the interface is down\n");
13651 best_period = 0x1FFFFFF;
13652 } else if (ppb >= BNX2X_MAX_PHC_DRIFT) {
13656 /* Changed not to allow val = 8, 16, 24 as these values
13657 * are not supported in workaround.
13659 for (val = 0; val <= 31; val++) {
13660 if ((val & 0x7) == 0)
13662 period1 = val * 1000000 / ppb;
13663 period2 = period1 + 1;
13665 dif1 = ppb - (val * 1000000 / period1);
13667 dif1 = BNX2X_MAX_PHC_DRIFT;
13670 dif2 = ppb - (val * 1000000 / period2);
13673 dif = (dif1 < dif2) ? dif1 : dif2;
13674 period = (dif1 < dif2) ? period1 : period2;
13675 if (dif < best_dif) {
13678 best_period = period;
13683 rc = bnx2x_send_update_drift_ramrod(bp, drift_dir, best_val,
13686 BNX2X_ERR("Failed to set drift\n");
13690 DP(BNX2X_MSG_PTP, "Configured val = %d, period = %d\n", best_val,
13696 static int bnx2x_ptp_adjtime(struct ptp_clock_info *ptp, s64 delta)
13698 struct bnx2x *bp = container_of(ptp, struct bnx2x, ptp_clock_info);
13700 DP(BNX2X_MSG_PTP, "PTP adjtime called, delta = %llx\n", delta);
13702 timecounter_adjtime(&bp->timecounter, delta);
13707 static int bnx2x_ptp_gettime(struct ptp_clock_info *ptp, struct timespec64 *ts)
13709 struct bnx2x *bp = container_of(ptp, struct bnx2x, ptp_clock_info);
13712 ns = timecounter_read(&bp->timecounter);
13714 DP(BNX2X_MSG_PTP, "PTP gettime called, ns = %llu\n", ns);
13716 *ts = ns_to_timespec64(ns);
13721 static int bnx2x_ptp_settime(struct ptp_clock_info *ptp,
13722 const struct timespec64 *ts)
13724 struct bnx2x *bp = container_of(ptp, struct bnx2x, ptp_clock_info);
13727 ns = timespec64_to_ns(ts);
13729 DP(BNX2X_MSG_PTP, "PTP settime called, ns = %llu\n", ns);
13731 /* Re-init the timecounter */
13732 timecounter_init(&bp->timecounter, &bp->cyclecounter, ns);
13737 /* Enable (or disable) ancillary features of the phc subsystem */
13738 static int bnx2x_ptp_enable(struct ptp_clock_info *ptp,
13739 struct ptp_clock_request *rq, int on)
13741 struct bnx2x *bp = container_of(ptp, struct bnx2x, ptp_clock_info);
13743 BNX2X_ERR("PHC ancillary features are not supported\n");
13747 static void bnx2x_register_phc(struct bnx2x *bp)
13749 /* Fill the ptp_clock_info struct and register PTP clock*/
13750 bp->ptp_clock_info.owner = THIS_MODULE;
13751 snprintf(bp->ptp_clock_info.name, 16, "%s", bp->dev->name);
13752 bp->ptp_clock_info.max_adj = BNX2X_MAX_PHC_DRIFT; /* In PPB */
13753 bp->ptp_clock_info.n_alarm = 0;
13754 bp->ptp_clock_info.n_ext_ts = 0;
13755 bp->ptp_clock_info.n_per_out = 0;
13756 bp->ptp_clock_info.pps = 0;
13757 bp->ptp_clock_info.adjfreq = bnx2x_ptp_adjfreq;
13758 bp->ptp_clock_info.adjtime = bnx2x_ptp_adjtime;
13759 bp->ptp_clock_info.gettime64 = bnx2x_ptp_gettime;
13760 bp->ptp_clock_info.settime64 = bnx2x_ptp_settime;
13761 bp->ptp_clock_info.enable = bnx2x_ptp_enable;
13763 bp->ptp_clock = ptp_clock_register(&bp->ptp_clock_info, &bp->pdev->dev);
13764 if (IS_ERR(bp->ptp_clock)) {
13765 bp->ptp_clock = NULL;
13766 BNX2X_ERR("PTP clock registeration failed\n");
13770 static int bnx2x_init_one(struct pci_dev *pdev,
13771 const struct pci_device_id *ent)
13773 struct net_device *dev = NULL;
13775 enum pcie_link_width pcie_width;
13776 enum pci_bus_speed pcie_speed;
13777 int rc, max_non_def_sbs;
13778 int rx_count, tx_count, rss_count, doorbell_size;
13783 /* Management FW 'remembers' living interfaces. Allow it some time
13784 * to forget previously living interfaces, allowing a proper re-load.
13786 if (is_kdump_kernel()) {
13787 ktime_t now = ktime_get_boottime();
13788 ktime_t fw_ready_time = ktime_set(5, 0);
13790 if (ktime_before(now, fw_ready_time))
13791 msleep(ktime_ms_delta(fw_ready_time, now));
13794 /* An estimated maximum supported CoS number according to the chip
13796 * We will try to roughly estimate the maximum number of CoSes this chip
13797 * may support in order to minimize the memory allocated for Tx
13798 * netdev_queue's. This number will be accurately calculated during the
13799 * initialization of bp->max_cos based on the chip versions AND chip
13800 * revision in the bnx2x_init_bp().
13802 max_cos_est = set_max_cos_est(ent->driver_data);
13803 if (max_cos_est < 0)
13804 return max_cos_est;
13805 is_vf = set_is_vf(ent->driver_data);
13806 cnic_cnt = is_vf ? 0 : 1;
13808 max_non_def_sbs = bnx2x_get_num_non_def_sbs(pdev, cnic_cnt);
13810 /* add another SB for VF as it has no default SB */
13811 max_non_def_sbs += is_vf ? 1 : 0;
13813 /* Maximum number of RSS queues: one IGU SB goes to CNIC */
13814 rss_count = max_non_def_sbs - cnic_cnt;
13819 /* Maximum number of netdev Rx queues: RSS + FCoE L2 */
13820 rx_count = rss_count + cnic_cnt;
13822 /* Maximum number of netdev Tx queues:
13823 * Maximum TSS queues * Maximum supported number of CoS + FCoE L2
13825 tx_count = rss_count * max_cos_est + cnic_cnt;
13827 /* dev zeroed in init_etherdev */
13828 dev = alloc_etherdev_mqs(sizeof(*bp), tx_count, rx_count);
13832 bp = netdev_priv(dev);
13836 bp->flags |= IS_VF_FLAG;
13838 bp->igu_sb_cnt = max_non_def_sbs;
13839 bp->igu_base_addr = IS_VF(bp) ? PXP_VF_ADDR_IGU_START : BAR_IGU_INTMEM;
13840 bp->msg_enable = debug;
13841 bp->cnic_support = cnic_cnt;
13842 bp->cnic_probe = bnx2x_cnic_probe;
13844 pci_set_drvdata(pdev, dev);
13846 rc = bnx2x_init_dev(bp, pdev, dev, ent->driver_data);
13852 BNX2X_DEV_INFO("This is a %s function\n",
13853 IS_PF(bp) ? "physical" : "virtual");
13854 BNX2X_DEV_INFO("Cnic support is %s\n", CNIC_SUPPORT(bp) ? "on" : "off");
13855 BNX2X_DEV_INFO("Max num of status blocks %d\n", max_non_def_sbs);
13856 BNX2X_DEV_INFO("Allocated netdev with %d tx and %d rx queues\n",
13857 tx_count, rx_count);
13859 rc = bnx2x_init_bp(bp);
13861 goto init_one_exit;
13863 /* Map doorbells here as we need the real value of bp->max_cos which
13864 * is initialized in bnx2x_init_bp() to determine the number of
13868 bp->doorbells = bnx2x_vf_doorbells(bp);
13869 rc = bnx2x_vf_pci_alloc(bp);
13871 goto init_one_exit;
13873 doorbell_size = BNX2X_L2_MAX_CID(bp) * (1 << BNX2X_DB_SHIFT);
13874 if (doorbell_size > pci_resource_len(pdev, 2)) {
13875 dev_err(&bp->pdev->dev,
13876 "Cannot map doorbells, bar size too small, aborting\n");
13878 goto init_one_exit;
13880 bp->doorbells = ioremap_nocache(pci_resource_start(pdev, 2),
13883 if (!bp->doorbells) {
13884 dev_err(&bp->pdev->dev,
13885 "Cannot map doorbell space, aborting\n");
13887 goto init_one_exit;
13891 rc = bnx2x_vfpf_acquire(bp, tx_count, rx_count);
13893 goto init_one_exit;
13896 /* Enable SRIOV if capability found in configuration space */
13897 rc = bnx2x_iov_init_one(bp, int_mode, BNX2X_MAX_NUM_OF_VFS);
13899 goto init_one_exit;
13901 /* calc qm_cid_count */
13902 bp->qm_cid_count = bnx2x_set_qm_cid_count(bp);
13903 BNX2X_DEV_INFO("qm_cid_count %d\n", bp->qm_cid_count);
13905 /* disable FCOE L2 queue for E1x*/
13906 if (CHIP_IS_E1x(bp))
13907 bp->flags |= NO_FCOE_FLAG;
13909 /* Set bp->num_queues for MSI-X mode*/
13910 bnx2x_set_num_queues(bp);
13912 /* Configure interrupt mode: try to enable MSI-X/MSI if
13915 rc = bnx2x_set_int_mode(bp);
13917 dev_err(&pdev->dev, "Cannot set interrupts\n");
13918 goto init_one_exit;
13920 BNX2X_DEV_INFO("set interrupts successfully\n");
13922 /* register the net device */
13923 rc = register_netdev(dev);
13925 dev_err(&pdev->dev, "Cannot register net device\n");
13926 goto init_one_exit;
13928 BNX2X_DEV_INFO("device name after netdev register %s\n", dev->name);
13930 if (!NO_FCOE(bp)) {
13931 /* Add storage MAC address */
13933 dev_addr_add(bp->dev, bp->fip_mac, NETDEV_HW_ADDR_T_SAN);
13936 if (pcie_get_minimum_link(bp->pdev, &pcie_speed, &pcie_width) ||
13937 pcie_speed == PCI_SPEED_UNKNOWN ||
13938 pcie_width == PCIE_LNK_WIDTH_UNKNOWN)
13939 BNX2X_DEV_INFO("Failed to determine PCI Express Bandwidth\n");
13942 "%s (%c%d) PCI-E x%d %s found at mem %lx, IRQ %d, node addr %pM\n",
13943 board_info[ent->driver_data].name,
13944 (CHIP_REV(bp) >> 12) + 'A', (CHIP_METAL(bp) >> 4),
13946 pcie_speed == PCIE_SPEED_2_5GT ? "2.5GHz" :
13947 pcie_speed == PCIE_SPEED_5_0GT ? "5.0GHz" :
13948 pcie_speed == PCIE_SPEED_8_0GT ? "8.0GHz" :
13950 dev->base_addr, bp->pdev->irq, dev->dev_addr);
13952 bnx2x_register_phc(bp);
13954 if (!IS_MF_SD_STORAGE_PERSONALITY_ONLY(bp))
13955 bnx2x_set_os_driver_state(bp, OS_DRIVER_STATE_DISABLED);
13960 bnx2x_disable_pcie_error_reporting(bp);
13963 iounmap(bp->regview);
13965 if (IS_PF(bp) && bp->doorbells)
13966 iounmap(bp->doorbells);
13970 if (atomic_read(&pdev->enable_cnt) == 1)
13971 pci_release_regions(pdev);
13973 pci_disable_device(pdev);
13978 static void __bnx2x_remove(struct pci_dev *pdev,
13979 struct net_device *dev,
13981 bool remove_netdev)
13983 if (bp->ptp_clock) {
13984 ptp_clock_unregister(bp->ptp_clock);
13985 bp->ptp_clock = NULL;
13988 /* Delete storage MAC address */
13989 if (!NO_FCOE(bp)) {
13991 dev_addr_del(bp->dev, bp->fip_mac, NETDEV_HW_ADDR_T_SAN);
13996 /* Delete app tlvs from dcbnl */
13997 bnx2x_dcbnl_update_applist(bp, true);
14002 (bp->flags & BC_SUPPORTS_RMMOD_CMD))
14003 bnx2x_fw_command(bp, DRV_MSG_CODE_RMMOD, 0);
14005 /* Close the interface - either directly or implicitly */
14006 if (remove_netdev) {
14007 unregister_netdev(dev);
14014 bnx2x_iov_remove_one(bp);
14016 /* Power on: we can't let PCI layer write to us while we are in D3 */
14018 bnx2x_set_power_state(bp, PCI_D0);
14019 bnx2x_set_os_driver_state(bp, OS_DRIVER_STATE_NOT_LOADED);
14021 /* Set endianity registers to reset values in case next driver
14022 * boots in different endianty environment.
14024 bnx2x_reset_endianity(bp);
14027 /* Disable MSI/MSI-X */
14028 bnx2x_disable_msi(bp);
14032 bnx2x_set_power_state(bp, PCI_D3hot);
14034 /* Make sure RESET task is not scheduled before continuing */
14035 cancel_delayed_work_sync(&bp->sp_rtnl_task);
14037 /* send message via vfpf channel to release the resources of this vf */
14039 bnx2x_vfpf_release(bp);
14041 /* Assumes no further PCIe PM changes will occur */
14042 if (system_state == SYSTEM_POWER_OFF) {
14043 pci_wake_from_d3(pdev, bp->wol);
14044 pci_set_power_state(pdev, PCI_D3hot);
14047 bnx2x_disable_pcie_error_reporting(bp);
14048 if (remove_netdev) {
14050 iounmap(bp->regview);
14052 /* For vfs, doorbells are part of the regview and were unmapped
14053 * along with it. FW is only loaded by PF.
14057 iounmap(bp->doorbells);
14059 bnx2x_release_firmware(bp);
14061 bnx2x_vf_pci_dealloc(bp);
14063 bnx2x_free_mem_bp(bp);
14067 if (atomic_read(&pdev->enable_cnt) == 1)
14068 pci_release_regions(pdev);
14070 pci_disable_device(pdev);
14074 static void bnx2x_remove_one(struct pci_dev *pdev)
14076 struct net_device *dev = pci_get_drvdata(pdev);
14080 dev_err(&pdev->dev, "BAD net device from bnx2x_init_one\n");
14083 bp = netdev_priv(dev);
14085 __bnx2x_remove(pdev, dev, bp, true);
14088 static int bnx2x_eeh_nic_unload(struct bnx2x *bp)
14090 bp->state = BNX2X_STATE_CLOSING_WAIT4_HALT;
14092 bp->rx_mode = BNX2X_RX_MODE_NONE;
14094 if (CNIC_LOADED(bp))
14095 bnx2x_cnic_notify(bp, CNIC_CTL_STOP_CMD);
14098 bnx2x_tx_disable(bp);
14099 /* Delete all NAPI objects */
14100 bnx2x_del_all_napi(bp);
14101 if (CNIC_LOADED(bp))
14102 bnx2x_del_all_napi_cnic(bp);
14103 netdev_reset_tc(bp->dev);
14105 del_timer_sync(&bp->timer);
14106 cancel_delayed_work_sync(&bp->sp_task);
14107 cancel_delayed_work_sync(&bp->period_task);
14109 if (!down_timeout(&bp->stats_lock, HZ / 10)) {
14110 bp->stats_state = STATS_STATE_DISABLED;
14111 up(&bp->stats_lock);
14114 bnx2x_save_statistics(bp);
14116 netif_carrier_off(bp->dev);
14122 * bnx2x_io_error_detected - called when PCI error is detected
14123 * @pdev: Pointer to PCI device
14124 * @state: The current pci connection state
14126 * This function is called after a PCI bus error affecting
14127 * this device has been detected.
14129 static pci_ers_result_t bnx2x_io_error_detected(struct pci_dev *pdev,
14130 pci_channel_state_t state)
14132 struct net_device *dev = pci_get_drvdata(pdev);
14133 struct bnx2x *bp = netdev_priv(dev);
14137 BNX2X_ERR("IO error detected\n");
14139 netif_device_detach(dev);
14141 if (state == pci_channel_io_perm_failure) {
14143 return PCI_ERS_RESULT_DISCONNECT;
14146 if (netif_running(dev))
14147 bnx2x_eeh_nic_unload(bp);
14149 bnx2x_prev_path_mark_eeh(bp);
14151 pci_disable_device(pdev);
14155 /* Request a slot reset */
14156 return PCI_ERS_RESULT_NEED_RESET;
14160 * bnx2x_io_slot_reset - called after the PCI bus has been reset
14161 * @pdev: Pointer to PCI device
14163 * Restart the card from scratch, as if from a cold-boot.
14165 static pci_ers_result_t bnx2x_io_slot_reset(struct pci_dev *pdev)
14167 struct net_device *dev = pci_get_drvdata(pdev);
14168 struct bnx2x *bp = netdev_priv(dev);
14172 BNX2X_ERR("IO slot reset initializing...\n");
14173 if (pci_enable_device(pdev)) {
14174 dev_err(&pdev->dev,
14175 "Cannot re-enable PCI device after reset\n");
14177 return PCI_ERS_RESULT_DISCONNECT;
14180 pci_set_master(pdev);
14181 pci_restore_state(pdev);
14182 pci_save_state(pdev);
14184 if (netif_running(dev))
14185 bnx2x_set_power_state(bp, PCI_D0);
14187 if (netif_running(dev)) {
14188 BNX2X_ERR("IO slot reset --> driver unload\n");
14190 /* MCP should have been reset; Need to wait for validity */
14191 bnx2x_init_shmem(bp);
14193 if (IS_PF(bp) && SHMEM2_HAS(bp, drv_capabilities_flag)) {
14197 drv_capabilities_flag[BP_FW_MB_IDX(bp)]);
14198 SHMEM2_WR(bp, drv_capabilities_flag[BP_FW_MB_IDX(bp)],
14199 v & ~DRV_FLAGS_CAPABILITIES_LOADED_L2);
14201 bnx2x_drain_tx_queues(bp);
14202 bnx2x_send_unload_req(bp, UNLOAD_RECOVERY);
14203 bnx2x_netif_stop(bp, 1);
14204 bnx2x_free_irq(bp);
14206 /* Report UNLOAD_DONE to MCP */
14207 bnx2x_send_unload_done(bp, true);
14212 bnx2x_prev_unload(bp);
14214 /* We should have reseted the engine, so It's fair to
14215 * assume the FW will no longer write to the bnx2x driver.
14217 bnx2x_squeeze_objects(bp);
14218 bnx2x_free_skbs(bp);
14219 for_each_rx_queue(bp, i)
14220 bnx2x_free_rx_sge_range(bp, bp->fp + i, NUM_RX_SGE);
14221 bnx2x_free_fp_mem(bp);
14222 bnx2x_free_mem(bp);
14224 bp->state = BNX2X_STATE_CLOSED;
14229 /* If AER, perform cleanup of the PCIe registers */
14230 if (bp->flags & AER_ENABLED) {
14231 if (pci_cleanup_aer_uncorrect_error_status(pdev))
14232 BNX2X_ERR("pci_cleanup_aer_uncorrect_error_status failed\n");
14234 DP(NETIF_MSG_HW, "pci_cleanup_aer_uncorrect_error_status succeeded\n");
14237 return PCI_ERS_RESULT_RECOVERED;
14241 * bnx2x_io_resume - called when traffic can start flowing again
14242 * @pdev: Pointer to PCI device
14244 * This callback is called when the error recovery driver tells us that
14245 * its OK to resume normal operation.
14247 static void bnx2x_io_resume(struct pci_dev *pdev)
14249 struct net_device *dev = pci_get_drvdata(pdev);
14250 struct bnx2x *bp = netdev_priv(dev);
14252 if (bp->recovery_state != BNX2X_RECOVERY_DONE) {
14253 netdev_err(bp->dev, "Handling parity error recovery. Try again later\n");
14259 bp->fw_seq = SHMEM_RD(bp, func_mb[BP_FW_MB_IDX(bp)].drv_mb_header) &
14260 DRV_MSG_SEQ_NUMBER_MASK;
14262 if (netif_running(dev))
14263 bnx2x_nic_load(bp, LOAD_NORMAL);
14265 netif_device_attach(dev);
14270 static const struct pci_error_handlers bnx2x_err_handler = {
14271 .error_detected = bnx2x_io_error_detected,
14272 .slot_reset = bnx2x_io_slot_reset,
14273 .resume = bnx2x_io_resume,
14276 static void bnx2x_shutdown(struct pci_dev *pdev)
14278 struct net_device *dev = pci_get_drvdata(pdev);
14284 bp = netdev_priv(dev);
14289 netif_device_detach(dev);
14292 /* Don't remove the netdevice, as there are scenarios which will cause
14293 * the kernel to hang, e.g., when trying to remove bnx2i while the
14294 * rootfs is mounted from SAN.
14296 __bnx2x_remove(pdev, dev, bp, false);
14299 static struct pci_driver bnx2x_pci_driver = {
14300 .name = DRV_MODULE_NAME,
14301 .id_table = bnx2x_pci_tbl,
14302 .probe = bnx2x_init_one,
14303 .remove = bnx2x_remove_one,
14304 .suspend = bnx2x_suspend,
14305 .resume = bnx2x_resume,
14306 .err_handler = &bnx2x_err_handler,
14307 #ifdef CONFIG_BNX2X_SRIOV
14308 .sriov_configure = bnx2x_sriov_configure,
14310 .shutdown = bnx2x_shutdown,
14313 static int __init bnx2x_init(void)
14317 pr_info("%s", version);
14319 bnx2x_wq = create_singlethread_workqueue("bnx2x");
14320 if (bnx2x_wq == NULL) {
14321 pr_err("Cannot create workqueue\n");
14324 bnx2x_iov_wq = create_singlethread_workqueue("bnx2x_iov");
14325 if (!bnx2x_iov_wq) {
14326 pr_err("Cannot create iov workqueue\n");
14327 destroy_workqueue(bnx2x_wq);
14331 ret = pci_register_driver(&bnx2x_pci_driver);
14333 pr_err("Cannot register driver\n");
14334 destroy_workqueue(bnx2x_wq);
14335 destroy_workqueue(bnx2x_iov_wq);
14340 static void __exit bnx2x_cleanup(void)
14342 struct list_head *pos, *q;
14344 pci_unregister_driver(&bnx2x_pci_driver);
14346 destroy_workqueue(bnx2x_wq);
14347 destroy_workqueue(bnx2x_iov_wq);
14349 /* Free globally allocated resources */
14350 list_for_each_safe(pos, q, &bnx2x_prev_list) {
14351 struct bnx2x_prev_path_list *tmp =
14352 list_entry(pos, struct bnx2x_prev_path_list, list);
14358 void bnx2x_notify_link_changed(struct bnx2x *bp)
14360 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_12 + BP_FUNC(bp)*sizeof(u32), 1);
14363 module_init(bnx2x_init);
14364 module_exit(bnx2x_cleanup);
14367 * bnx2x_set_iscsi_eth_mac_addr - set iSCSI MAC(s).
14369 * @bp: driver handle
14370 * @set: set or clear the CAM entry
14372 * This function will wait until the ramrod completion returns.
14373 * Return 0 if success, -ENODEV if ramrod doesn't return.
14375 static int bnx2x_set_iscsi_eth_mac_addr(struct bnx2x *bp)
14377 unsigned long ramrod_flags = 0;
14379 __set_bit(RAMROD_COMP_WAIT, &ramrod_flags);
14380 return bnx2x_set_mac_one(bp, bp->cnic_eth_dev.iscsi_mac,
14381 &bp->iscsi_l2_mac_obj, true,
14382 BNX2X_ISCSI_ETH_MAC, &ramrod_flags);
14385 /* count denotes the number of new completions we have seen */
14386 static void bnx2x_cnic_sp_post(struct bnx2x *bp, int count)
14388 struct eth_spe *spe;
14389 int cxt_index, cxt_offset;
14391 #ifdef BNX2X_STOP_ON_ERROR
14392 if (unlikely(bp->panic))
14396 spin_lock_bh(&bp->spq_lock);
14397 BUG_ON(bp->cnic_spq_pending < count);
14398 bp->cnic_spq_pending -= count;
14400 for (; bp->cnic_kwq_pending; bp->cnic_kwq_pending--) {
14401 u16 type = (le16_to_cpu(bp->cnic_kwq_cons->hdr.type)
14402 & SPE_HDR_CONN_TYPE) >>
14403 SPE_HDR_CONN_TYPE_SHIFT;
14404 u8 cmd = (le32_to_cpu(bp->cnic_kwq_cons->hdr.conn_and_cmd_data)
14405 >> SPE_HDR_CMD_ID_SHIFT) & 0xff;
14407 /* Set validation for iSCSI L2 client before sending SETUP
14410 if (type == ETH_CONNECTION_TYPE) {
14411 if (cmd == RAMROD_CMD_ID_ETH_CLIENT_SETUP) {
14412 cxt_index = BNX2X_ISCSI_ETH_CID(bp) /
14414 cxt_offset = BNX2X_ISCSI_ETH_CID(bp) -
14415 (cxt_index * ILT_PAGE_CIDS);
14416 bnx2x_set_ctx_validation(bp,
14417 &bp->context[cxt_index].
14418 vcxt[cxt_offset].eth,
14419 BNX2X_ISCSI_ETH_CID(bp));
14424 * There may be not more than 8 L2, not more than 8 L5 SPEs
14425 * and in the air. We also check that number of outstanding
14426 * COMMON ramrods is not more than the EQ and SPQ can
14429 if (type == ETH_CONNECTION_TYPE) {
14430 if (!atomic_read(&bp->cq_spq_left))
14433 atomic_dec(&bp->cq_spq_left);
14434 } else if (type == NONE_CONNECTION_TYPE) {
14435 if (!atomic_read(&bp->eq_spq_left))
14438 atomic_dec(&bp->eq_spq_left);
14439 } else if ((type == ISCSI_CONNECTION_TYPE) ||
14440 (type == FCOE_CONNECTION_TYPE)) {
14441 if (bp->cnic_spq_pending >=
14442 bp->cnic_eth_dev.max_kwqe_pending)
14445 bp->cnic_spq_pending++;
14447 BNX2X_ERR("Unknown SPE type: %d\n", type);
14452 spe = bnx2x_sp_get_next(bp);
14453 *spe = *bp->cnic_kwq_cons;
14455 DP(BNX2X_MSG_SP, "pending on SPQ %d, on KWQ %d count %d\n",
14456 bp->cnic_spq_pending, bp->cnic_kwq_pending, count);
14458 if (bp->cnic_kwq_cons == bp->cnic_kwq_last)
14459 bp->cnic_kwq_cons = bp->cnic_kwq;
14461 bp->cnic_kwq_cons++;
14463 bnx2x_sp_prod_update(bp);
14464 spin_unlock_bh(&bp->spq_lock);
14467 static int bnx2x_cnic_sp_queue(struct net_device *dev,
14468 struct kwqe_16 *kwqes[], u32 count)
14470 struct bnx2x *bp = netdev_priv(dev);
14473 #ifdef BNX2X_STOP_ON_ERROR
14474 if (unlikely(bp->panic)) {
14475 BNX2X_ERR("Can't post to SP queue while panic\n");
14480 if ((bp->recovery_state != BNX2X_RECOVERY_DONE) &&
14481 (bp->recovery_state != BNX2X_RECOVERY_NIC_LOADING)) {
14482 BNX2X_ERR("Handling parity error recovery. Try again later\n");
14486 spin_lock_bh(&bp->spq_lock);
14488 for (i = 0; i < count; i++) {
14489 struct eth_spe *spe = (struct eth_spe *)kwqes[i];
14491 if (bp->cnic_kwq_pending == MAX_SP_DESC_CNT)
14494 *bp->cnic_kwq_prod = *spe;
14496 bp->cnic_kwq_pending++;
14498 DP(BNX2X_MSG_SP, "L5 SPQE %x %x %x:%x pos %d\n",
14499 spe->hdr.conn_and_cmd_data, spe->hdr.type,
14500 spe->data.update_data_addr.hi,
14501 spe->data.update_data_addr.lo,
14502 bp->cnic_kwq_pending);
14504 if (bp->cnic_kwq_prod == bp->cnic_kwq_last)
14505 bp->cnic_kwq_prod = bp->cnic_kwq;
14507 bp->cnic_kwq_prod++;
14510 spin_unlock_bh(&bp->spq_lock);
14512 if (bp->cnic_spq_pending < bp->cnic_eth_dev.max_kwqe_pending)
14513 bnx2x_cnic_sp_post(bp, 0);
14518 static int bnx2x_cnic_ctl_send(struct bnx2x *bp, struct cnic_ctl_info *ctl)
14520 struct cnic_ops *c_ops;
14523 mutex_lock(&bp->cnic_mutex);
14524 c_ops = rcu_dereference_protected(bp->cnic_ops,
14525 lockdep_is_held(&bp->cnic_mutex));
14527 rc = c_ops->cnic_ctl(bp->cnic_data, ctl);
14528 mutex_unlock(&bp->cnic_mutex);
14533 static int bnx2x_cnic_ctl_send_bh(struct bnx2x *bp, struct cnic_ctl_info *ctl)
14535 struct cnic_ops *c_ops;
14539 c_ops = rcu_dereference(bp->cnic_ops);
14541 rc = c_ops->cnic_ctl(bp->cnic_data, ctl);
14548 * for commands that have no data
14550 int bnx2x_cnic_notify(struct bnx2x *bp, int cmd)
14552 struct cnic_ctl_info ctl = {0};
14556 return bnx2x_cnic_ctl_send(bp, &ctl);
14559 static void bnx2x_cnic_cfc_comp(struct bnx2x *bp, int cid, u8 err)
14561 struct cnic_ctl_info ctl = {0};
14563 /* first we tell CNIC and only then we count this as a completion */
14564 ctl.cmd = CNIC_CTL_COMPLETION_CMD;
14565 ctl.data.comp.cid = cid;
14566 ctl.data.comp.error = err;
14568 bnx2x_cnic_ctl_send_bh(bp, &ctl);
14569 bnx2x_cnic_sp_post(bp, 0);
14572 /* Called with netif_addr_lock_bh() taken.
14573 * Sets an rx_mode config for an iSCSI ETH client.
14575 * Completion should be checked outside.
14577 static void bnx2x_set_iscsi_eth_rx_mode(struct bnx2x *bp, bool start)
14579 unsigned long accept_flags = 0, ramrod_flags = 0;
14580 u8 cl_id = bnx2x_cnic_eth_cl_id(bp, BNX2X_ISCSI_ETH_CL_ID_IDX);
14581 int sched_state = BNX2X_FILTER_ISCSI_ETH_STOP_SCHED;
14584 /* Start accepting on iSCSI L2 ring. Accept all multicasts
14585 * because it's the only way for UIO Queue to accept
14586 * multicasts (in non-promiscuous mode only one Queue per
14587 * function will receive multicast packets (leading in our
14590 __set_bit(BNX2X_ACCEPT_UNICAST, &accept_flags);
14591 __set_bit(BNX2X_ACCEPT_ALL_MULTICAST, &accept_flags);
14592 __set_bit(BNX2X_ACCEPT_BROADCAST, &accept_flags);
14593 __set_bit(BNX2X_ACCEPT_ANY_VLAN, &accept_flags);
14595 /* Clear STOP_PENDING bit if START is requested */
14596 clear_bit(BNX2X_FILTER_ISCSI_ETH_STOP_SCHED, &bp->sp_state);
14598 sched_state = BNX2X_FILTER_ISCSI_ETH_START_SCHED;
14600 /* Clear START_PENDING bit if STOP is requested */
14601 clear_bit(BNX2X_FILTER_ISCSI_ETH_START_SCHED, &bp->sp_state);
14603 if (test_bit(BNX2X_FILTER_RX_MODE_PENDING, &bp->sp_state))
14604 set_bit(sched_state, &bp->sp_state);
14606 __set_bit(RAMROD_RX, &ramrod_flags);
14607 bnx2x_set_q_rx_mode(bp, cl_id, 0, accept_flags, 0,
14612 static int bnx2x_drv_ctl(struct net_device *dev, struct drv_ctl_info *ctl)
14614 struct bnx2x *bp = netdev_priv(dev);
14617 switch (ctl->cmd) {
14618 case DRV_CTL_CTXTBL_WR_CMD: {
14619 u32 index = ctl->data.io.offset;
14620 dma_addr_t addr = ctl->data.io.dma_addr;
14622 bnx2x_ilt_wr(bp, index, addr);
14626 case DRV_CTL_RET_L5_SPQ_CREDIT_CMD: {
14627 int count = ctl->data.credit.credit_count;
14629 bnx2x_cnic_sp_post(bp, count);
14633 /* rtnl_lock is held. */
14634 case DRV_CTL_START_L2_CMD: {
14635 struct cnic_eth_dev *cp = &bp->cnic_eth_dev;
14636 unsigned long sp_bits = 0;
14638 /* Configure the iSCSI classification object */
14639 bnx2x_init_mac_obj(bp, &bp->iscsi_l2_mac_obj,
14640 cp->iscsi_l2_client_id,
14641 cp->iscsi_l2_cid, BP_FUNC(bp),
14642 bnx2x_sp(bp, mac_rdata),
14643 bnx2x_sp_mapping(bp, mac_rdata),
14644 BNX2X_FILTER_MAC_PENDING,
14645 &bp->sp_state, BNX2X_OBJ_TYPE_RX,
14648 /* Set iSCSI MAC address */
14649 rc = bnx2x_set_iscsi_eth_mac_addr(bp);
14656 /* Start accepting on iSCSI L2 ring */
14658 netif_addr_lock_bh(dev);
14659 bnx2x_set_iscsi_eth_rx_mode(bp, true);
14660 netif_addr_unlock_bh(dev);
14662 /* bits to wait on */
14663 __set_bit(BNX2X_FILTER_RX_MODE_PENDING, &sp_bits);
14664 __set_bit(BNX2X_FILTER_ISCSI_ETH_START_SCHED, &sp_bits);
14666 if (!bnx2x_wait_sp_comp(bp, sp_bits))
14667 BNX2X_ERR("rx_mode completion timed out!\n");
14672 /* rtnl_lock is held. */
14673 case DRV_CTL_STOP_L2_CMD: {
14674 unsigned long sp_bits = 0;
14676 /* Stop accepting on iSCSI L2 ring */
14677 netif_addr_lock_bh(dev);
14678 bnx2x_set_iscsi_eth_rx_mode(bp, false);
14679 netif_addr_unlock_bh(dev);
14681 /* bits to wait on */
14682 __set_bit(BNX2X_FILTER_RX_MODE_PENDING, &sp_bits);
14683 __set_bit(BNX2X_FILTER_ISCSI_ETH_STOP_SCHED, &sp_bits);
14685 if (!bnx2x_wait_sp_comp(bp, sp_bits))
14686 BNX2X_ERR("rx_mode completion timed out!\n");
14691 /* Unset iSCSI L2 MAC */
14692 rc = bnx2x_del_all_macs(bp, &bp->iscsi_l2_mac_obj,
14693 BNX2X_ISCSI_ETH_MAC, true);
14696 case DRV_CTL_RET_L2_SPQ_CREDIT_CMD: {
14697 int count = ctl->data.credit.credit_count;
14699 smp_mb__before_atomic();
14700 atomic_add(count, &bp->cq_spq_left);
14701 smp_mb__after_atomic();
14704 case DRV_CTL_ULP_REGISTER_CMD: {
14705 int ulp_type = ctl->data.register_data.ulp_type;
14707 if (CHIP_IS_E3(bp)) {
14708 int idx = BP_FW_MB_IDX(bp);
14709 u32 cap = SHMEM2_RD(bp, drv_capabilities_flag[idx]);
14710 int path = BP_PATH(bp);
14711 int port = BP_PORT(bp);
14713 u32 scratch_offset;
14716 /* first write capability to shmem2 */
14717 if (ulp_type == CNIC_ULP_ISCSI)
14718 cap |= DRV_FLAGS_CAPABILITIES_LOADED_ISCSI;
14719 else if (ulp_type == CNIC_ULP_FCOE)
14720 cap |= DRV_FLAGS_CAPABILITIES_LOADED_FCOE;
14721 SHMEM2_WR(bp, drv_capabilities_flag[idx], cap);
14723 if ((ulp_type != CNIC_ULP_FCOE) ||
14724 (!SHMEM2_HAS(bp, ncsi_oem_data_addr)) ||
14725 (!(bp->flags & BC_SUPPORTS_FCOE_FEATURES)))
14728 /* if reached here - should write fcoe capabilities */
14729 scratch_offset = SHMEM2_RD(bp, ncsi_oem_data_addr);
14730 if (!scratch_offset)
14732 scratch_offset += offsetof(struct glob_ncsi_oem_data,
14733 fcoe_features[path][port]);
14734 host_addr = (u32 *) &(ctl->data.register_data.
14736 for (i = 0; i < sizeof(struct fcoe_capabilities);
14738 REG_WR(bp, scratch_offset + i,
14739 *(host_addr + i/4));
14741 bnx2x_schedule_sp_rtnl(bp, BNX2X_SP_RTNL_GET_DRV_VERSION, 0);
14745 case DRV_CTL_ULP_UNREGISTER_CMD: {
14746 int ulp_type = ctl->data.ulp_type;
14748 if (CHIP_IS_E3(bp)) {
14749 int idx = BP_FW_MB_IDX(bp);
14752 cap = SHMEM2_RD(bp, drv_capabilities_flag[idx]);
14753 if (ulp_type == CNIC_ULP_ISCSI)
14754 cap &= ~DRV_FLAGS_CAPABILITIES_LOADED_ISCSI;
14755 else if (ulp_type == CNIC_ULP_FCOE)
14756 cap &= ~DRV_FLAGS_CAPABILITIES_LOADED_FCOE;
14757 SHMEM2_WR(bp, drv_capabilities_flag[idx], cap);
14759 bnx2x_schedule_sp_rtnl(bp, BNX2X_SP_RTNL_GET_DRV_VERSION, 0);
14764 BNX2X_ERR("unknown command %x\n", ctl->cmd);
14768 /* For storage-only interfaces, change driver state */
14769 if (IS_MF_SD_STORAGE_PERSONALITY_ONLY(bp)) {
14770 switch (ctl->drv_state) {
14774 bnx2x_set_os_driver_state(bp,
14775 OS_DRIVER_STATE_ACTIVE);
14778 bnx2x_set_os_driver_state(bp,
14779 OS_DRIVER_STATE_DISABLED);
14782 bnx2x_set_os_driver_state(bp,
14783 OS_DRIVER_STATE_NOT_LOADED);
14786 BNX2X_ERR("Unknown cnic driver state: %d\n", ctl->drv_state);
14793 static int bnx2x_get_fc_npiv(struct net_device *dev,
14794 struct cnic_fc_npiv_tbl *cnic_tbl)
14796 struct bnx2x *bp = netdev_priv(dev);
14797 struct bdn_fc_npiv_tbl *tbl = NULL;
14798 u32 offset, entries;
14802 if (!SHMEM2_HAS(bp, fc_npiv_nvram_tbl_addr[0]))
14805 DP(BNX2X_MSG_MCP, "About to read the FC-NPIV table\n");
14807 tbl = kmalloc(sizeof(*tbl), GFP_KERNEL);
14809 BNX2X_ERR("Failed to allocate fc_npiv table\n");
14813 offset = SHMEM2_RD(bp, fc_npiv_nvram_tbl_addr[BP_PORT(bp)]);
14814 DP(BNX2X_MSG_MCP, "Offset of FC-NPIV in NVRAM: %08x\n", offset);
14816 /* Read the table contents from nvram */
14817 if (bnx2x_nvram_read(bp, offset, (u8 *)tbl, sizeof(*tbl))) {
14818 BNX2X_ERR("Failed to read FC-NPIV table\n");
14822 /* Since bnx2x_nvram_read() returns data in be32, we need to convert
14823 * the number of entries back to cpu endianness.
14825 entries = tbl->fc_npiv_cfg.num_of_npiv;
14826 entries = (__force u32)be32_to_cpu((__force __be32)entries);
14827 tbl->fc_npiv_cfg.num_of_npiv = entries;
14829 if (!tbl->fc_npiv_cfg.num_of_npiv) {
14831 "No FC-NPIV table [valid, simply not present]\n");
14833 } else if (tbl->fc_npiv_cfg.num_of_npiv > MAX_NUMBER_NPIV) {
14834 BNX2X_ERR("FC-NPIV table with bad length 0x%08x\n",
14835 tbl->fc_npiv_cfg.num_of_npiv);
14838 DP(BNX2X_MSG_MCP, "Read 0x%08x entries from NVRAM\n",
14839 tbl->fc_npiv_cfg.num_of_npiv);
14842 /* Copy the data into cnic-provided struct */
14843 cnic_tbl->count = tbl->fc_npiv_cfg.num_of_npiv;
14844 for (i = 0; i < cnic_tbl->count; i++) {
14845 memcpy(cnic_tbl->wwpn[i], tbl->settings[i].npiv_wwpn, 8);
14846 memcpy(cnic_tbl->wwnn[i], tbl->settings[i].npiv_wwnn, 8);
14855 void bnx2x_setup_cnic_irq_info(struct bnx2x *bp)
14857 struct cnic_eth_dev *cp = &bp->cnic_eth_dev;
14859 if (bp->flags & USING_MSIX_FLAG) {
14860 cp->drv_state |= CNIC_DRV_STATE_USING_MSIX;
14861 cp->irq_arr[0].irq_flags |= CNIC_IRQ_FL_MSIX;
14862 cp->irq_arr[0].vector = bp->msix_table[1].vector;
14864 cp->drv_state &= ~CNIC_DRV_STATE_USING_MSIX;
14865 cp->irq_arr[0].irq_flags &= ~CNIC_IRQ_FL_MSIX;
14867 if (!CHIP_IS_E1x(bp))
14868 cp->irq_arr[0].status_blk = (void *)bp->cnic_sb.e2_sb;
14870 cp->irq_arr[0].status_blk = (void *)bp->cnic_sb.e1x_sb;
14872 cp->irq_arr[0].status_blk_num = bnx2x_cnic_fw_sb_id(bp);
14873 cp->irq_arr[0].status_blk_num2 = bnx2x_cnic_igu_sb_id(bp);
14874 cp->irq_arr[1].status_blk = bp->def_status_blk;
14875 cp->irq_arr[1].status_blk_num = DEF_SB_ID;
14876 cp->irq_arr[1].status_blk_num2 = DEF_SB_IGU_ID;
14881 void bnx2x_setup_cnic_info(struct bnx2x *bp)
14883 struct cnic_eth_dev *cp = &bp->cnic_eth_dev;
14885 cp->ctx_tbl_offset = FUNC_ILT_BASE(BP_FUNC(bp)) +
14886 bnx2x_cid_ilt_lines(bp);
14887 cp->starting_cid = bnx2x_cid_ilt_lines(bp) * ILT_PAGE_CIDS;
14888 cp->fcoe_init_cid = BNX2X_FCOE_ETH_CID(bp);
14889 cp->iscsi_l2_cid = BNX2X_ISCSI_ETH_CID(bp);
14891 DP(NETIF_MSG_IFUP, "BNX2X_1st_NON_L2_ETH_CID(bp) %x, cp->starting_cid %x, cp->fcoe_init_cid %x, cp->iscsi_l2_cid %x\n",
14892 BNX2X_1st_NON_L2_ETH_CID(bp), cp->starting_cid, cp->fcoe_init_cid,
14895 if (NO_ISCSI_OOO(bp))
14896 cp->drv_state |= CNIC_DRV_STATE_NO_ISCSI_OOO;
14899 static int bnx2x_register_cnic(struct net_device *dev, struct cnic_ops *ops,
14902 struct bnx2x *bp = netdev_priv(dev);
14903 struct cnic_eth_dev *cp = &bp->cnic_eth_dev;
14906 DP(NETIF_MSG_IFUP, "Register_cnic called\n");
14909 BNX2X_ERR("NULL ops received\n");
14913 if (!CNIC_SUPPORT(bp)) {
14914 BNX2X_ERR("Can't register CNIC when not supported\n");
14915 return -EOPNOTSUPP;
14918 if (!CNIC_LOADED(bp)) {
14919 rc = bnx2x_load_cnic(bp);
14921 BNX2X_ERR("CNIC-related load failed\n");
14926 bp->cnic_enabled = true;
14928 bp->cnic_kwq = kzalloc(PAGE_SIZE, GFP_KERNEL);
14932 bp->cnic_kwq_cons = bp->cnic_kwq;
14933 bp->cnic_kwq_prod = bp->cnic_kwq;
14934 bp->cnic_kwq_last = bp->cnic_kwq + MAX_SP_DESC_CNT;
14936 bp->cnic_spq_pending = 0;
14937 bp->cnic_kwq_pending = 0;
14939 bp->cnic_data = data;
14942 cp->drv_state |= CNIC_DRV_STATE_REGD;
14943 cp->iro_arr = bp->iro_arr;
14945 bnx2x_setup_cnic_irq_info(bp);
14947 rcu_assign_pointer(bp->cnic_ops, ops);
14949 /* Schedule driver to read CNIC driver versions */
14950 bnx2x_schedule_sp_rtnl(bp, BNX2X_SP_RTNL_GET_DRV_VERSION, 0);
14955 static int bnx2x_unregister_cnic(struct net_device *dev)
14957 struct bnx2x *bp = netdev_priv(dev);
14958 struct cnic_eth_dev *cp = &bp->cnic_eth_dev;
14960 mutex_lock(&bp->cnic_mutex);
14962 RCU_INIT_POINTER(bp->cnic_ops, NULL);
14963 mutex_unlock(&bp->cnic_mutex);
14965 bp->cnic_enabled = false;
14966 kfree(bp->cnic_kwq);
14967 bp->cnic_kwq = NULL;
14972 static struct cnic_eth_dev *bnx2x_cnic_probe(struct net_device *dev)
14974 struct bnx2x *bp = netdev_priv(dev);
14975 struct cnic_eth_dev *cp = &bp->cnic_eth_dev;
14977 /* If both iSCSI and FCoE are disabled - return NULL in
14978 * order to indicate CNIC that it should not try to work
14979 * with this device.
14981 if (NO_ISCSI(bp) && NO_FCOE(bp))
14984 cp->drv_owner = THIS_MODULE;
14985 cp->chip_id = CHIP_ID(bp);
14986 cp->pdev = bp->pdev;
14987 cp->io_base = bp->regview;
14988 cp->io_base2 = bp->doorbells;
14989 cp->max_kwqe_pending = 8;
14990 cp->ctx_blk_size = CDU_ILT_PAGE_SZ;
14991 cp->ctx_tbl_offset = FUNC_ILT_BASE(BP_FUNC(bp)) +
14992 bnx2x_cid_ilt_lines(bp);
14993 cp->ctx_tbl_len = CNIC_ILT_LINES;
14994 cp->starting_cid = bnx2x_cid_ilt_lines(bp) * ILT_PAGE_CIDS;
14995 cp->drv_submit_kwqes_16 = bnx2x_cnic_sp_queue;
14996 cp->drv_ctl = bnx2x_drv_ctl;
14997 cp->drv_get_fc_npiv_tbl = bnx2x_get_fc_npiv;
14998 cp->drv_register_cnic = bnx2x_register_cnic;
14999 cp->drv_unregister_cnic = bnx2x_unregister_cnic;
15000 cp->fcoe_init_cid = BNX2X_FCOE_ETH_CID(bp);
15001 cp->iscsi_l2_client_id =
15002 bnx2x_cnic_eth_cl_id(bp, BNX2X_ISCSI_ETH_CL_ID_IDX);
15003 cp->iscsi_l2_cid = BNX2X_ISCSI_ETH_CID(bp);
15005 if (NO_ISCSI_OOO(bp))
15006 cp->drv_state |= CNIC_DRV_STATE_NO_ISCSI_OOO;
15009 cp->drv_state |= CNIC_DRV_STATE_NO_ISCSI;
15012 cp->drv_state |= CNIC_DRV_STATE_NO_FCOE;
15015 "page_size %d, tbl_offset %d, tbl_lines %d, starting cid %d\n",
15017 cp->ctx_tbl_offset,
15023 static u32 bnx2x_rx_ustorm_prods_offset(struct bnx2x_fastpath *fp)
15025 struct bnx2x *bp = fp->bp;
15026 u32 offset = BAR_USTRORM_INTMEM;
15029 return bnx2x_vf_ustorm_prods_offset(bp, fp);
15030 else if (!CHIP_IS_E1x(bp))
15031 offset += USTORM_RX_PRODS_E2_OFFSET(fp->cl_qzone_id);
15033 offset += USTORM_RX_PRODS_E1X_OFFSET(BP_PORT(bp), fp->cl_id);
15038 /* called only on E1H or E2.
15039 * When pretending to be PF, the pretend value is the function number 0...7
15040 * When pretending to be VF, the pretend val is the PF-num:VF-valid:ABS-VFID
15043 int bnx2x_pretend_func(struct bnx2x *bp, u16 pretend_func_val)
15047 if (CHIP_IS_E1H(bp) && pretend_func_val >= E1H_FUNC_MAX)
15050 /* get my own pretend register */
15051 pretend_reg = bnx2x_get_pretend_reg(bp);
15052 REG_WR(bp, pretend_reg, pretend_func_val);
15053 REG_RD(bp, pretend_reg);
15057 static void bnx2x_ptp_task(struct work_struct *work)
15059 struct bnx2x *bp = container_of(work, struct bnx2x, ptp_task);
15060 int port = BP_PORT(bp);
15063 struct skb_shared_hwtstamps shhwtstamps;
15065 /* Read Tx timestamp registers */
15066 val_seq = REG_RD(bp, port ? NIG_REG_P1_TLLH_PTP_BUF_SEQID :
15067 NIG_REG_P0_TLLH_PTP_BUF_SEQID);
15068 if (val_seq & 0x10000) {
15069 /* There is a valid timestamp value */
15070 timestamp = REG_RD(bp, port ? NIG_REG_P1_TLLH_PTP_BUF_TS_MSB :
15071 NIG_REG_P0_TLLH_PTP_BUF_TS_MSB);
15073 timestamp |= REG_RD(bp, port ? NIG_REG_P1_TLLH_PTP_BUF_TS_LSB :
15074 NIG_REG_P0_TLLH_PTP_BUF_TS_LSB);
15075 /* Reset timestamp register to allow new timestamp */
15076 REG_WR(bp, port ? NIG_REG_P1_TLLH_PTP_BUF_SEQID :
15077 NIG_REG_P0_TLLH_PTP_BUF_SEQID, 0x10000);
15078 ns = timecounter_cyc2time(&bp->timecounter, timestamp);
15080 memset(&shhwtstamps, 0, sizeof(shhwtstamps));
15081 shhwtstamps.hwtstamp = ns_to_ktime(ns);
15082 skb_tstamp_tx(bp->ptp_tx_skb, &shhwtstamps);
15083 dev_kfree_skb_any(bp->ptp_tx_skb);
15084 bp->ptp_tx_skb = NULL;
15086 DP(BNX2X_MSG_PTP, "Tx timestamp, timestamp cycles = %llu, ns = %llu\n",
15089 DP(BNX2X_MSG_PTP, "There is no valid Tx timestamp yet\n");
15090 /* Reschedule to keep checking for a valid timestamp value */
15091 schedule_work(&bp->ptp_task);
15095 void bnx2x_set_rx_ts(struct bnx2x *bp, struct sk_buff *skb)
15097 int port = BP_PORT(bp);
15100 timestamp = REG_RD(bp, port ? NIG_REG_P1_LLH_PTP_HOST_BUF_TS_MSB :
15101 NIG_REG_P0_LLH_PTP_HOST_BUF_TS_MSB);
15103 timestamp |= REG_RD(bp, port ? NIG_REG_P1_LLH_PTP_HOST_BUF_TS_LSB :
15104 NIG_REG_P0_LLH_PTP_HOST_BUF_TS_LSB);
15106 /* Reset timestamp register to allow new timestamp */
15107 REG_WR(bp, port ? NIG_REG_P1_LLH_PTP_HOST_BUF_SEQID :
15108 NIG_REG_P0_LLH_PTP_HOST_BUF_SEQID, 0x10000);
15110 ns = timecounter_cyc2time(&bp->timecounter, timestamp);
15112 skb_hwtstamps(skb)->hwtstamp = ns_to_ktime(ns);
15114 DP(BNX2X_MSG_PTP, "Rx timestamp, timestamp cycles = %llu, ns = %llu\n",
15119 static cycle_t bnx2x_cyclecounter_read(const struct cyclecounter *cc)
15121 struct bnx2x *bp = container_of(cc, struct bnx2x, cyclecounter);
15122 int port = BP_PORT(bp);
15126 REG_RD_DMAE(bp, port ? NIG_REG_TIMESYNC_GEN_REG + tsgen_synctime_t1 :
15127 NIG_REG_TIMESYNC_GEN_REG + tsgen_synctime_t0, wb_data, 2);
15128 phc_cycles = wb_data[1];
15129 phc_cycles = (phc_cycles << 32) + wb_data[0];
15131 DP(BNX2X_MSG_PTP, "PHC read cycles = %llu\n", phc_cycles);
15136 static void bnx2x_init_cyclecounter(struct bnx2x *bp)
15138 memset(&bp->cyclecounter, 0, sizeof(bp->cyclecounter));
15139 bp->cyclecounter.read = bnx2x_cyclecounter_read;
15140 bp->cyclecounter.mask = CYCLECOUNTER_MASK(64);
15141 bp->cyclecounter.shift = 1;
15142 bp->cyclecounter.mult = 1;
15145 static int bnx2x_send_reset_timesync_ramrod(struct bnx2x *bp)
15147 struct bnx2x_func_state_params func_params = {NULL};
15148 struct bnx2x_func_set_timesync_params *set_timesync_params =
15149 &func_params.params.set_timesync;
15151 /* Prepare parameters for function state transitions */
15152 __set_bit(RAMROD_COMP_WAIT, &func_params.ramrod_flags);
15153 __set_bit(RAMROD_RETRY, &func_params.ramrod_flags);
15155 func_params.f_obj = &bp->func_obj;
15156 func_params.cmd = BNX2X_F_CMD_SET_TIMESYNC;
15158 /* Function parameters */
15159 set_timesync_params->drift_adjust_cmd = TS_DRIFT_ADJUST_RESET;
15160 set_timesync_params->offset_cmd = TS_OFFSET_KEEP;
15162 return bnx2x_func_state_change(bp, &func_params);
15165 static int bnx2x_enable_ptp_packets(struct bnx2x *bp)
15167 struct bnx2x_queue_state_params q_params;
15170 /* send queue update ramrod to enable PTP packets */
15171 memset(&q_params, 0, sizeof(q_params));
15172 __set_bit(RAMROD_COMP_WAIT, &q_params.ramrod_flags);
15173 q_params.cmd = BNX2X_Q_CMD_UPDATE;
15174 __set_bit(BNX2X_Q_UPDATE_PTP_PKTS_CHNG,
15175 &q_params.params.update.update_flags);
15176 __set_bit(BNX2X_Q_UPDATE_PTP_PKTS,
15177 &q_params.params.update.update_flags);
15179 /* send the ramrod on all the queues of the PF */
15180 for_each_eth_queue(bp, i) {
15181 struct bnx2x_fastpath *fp = &bp->fp[i];
15183 /* Set the appropriate Queue object */
15184 q_params.q_obj = &bnx2x_sp_obj(bp, fp).q_obj;
15186 /* Update the Queue state */
15187 rc = bnx2x_queue_state_change(bp, &q_params);
15189 BNX2X_ERR("Failed to enable PTP packets\n");
15197 int bnx2x_configure_ptp_filters(struct bnx2x *bp)
15199 int port = BP_PORT(bp);
15202 if (!bp->hwtstamp_ioctl_called)
15205 switch (bp->tx_type) {
15206 case HWTSTAMP_TX_ON:
15207 bp->flags |= TX_TIMESTAMPING_EN;
15208 REG_WR(bp, port ? NIG_REG_P1_TLLH_PTP_PARAM_MASK :
15209 NIG_REG_P0_TLLH_PTP_PARAM_MASK, 0x6AA);
15210 REG_WR(bp, port ? NIG_REG_P1_TLLH_PTP_RULE_MASK :
15211 NIG_REG_P0_TLLH_PTP_RULE_MASK, 0x3EEE);
15213 case HWTSTAMP_TX_ONESTEP_SYNC:
15214 BNX2X_ERR("One-step timestamping is not supported\n");
15218 switch (bp->rx_filter) {
15219 case HWTSTAMP_FILTER_NONE:
15221 case HWTSTAMP_FILTER_ALL:
15222 case HWTSTAMP_FILTER_SOME:
15223 bp->rx_filter = HWTSTAMP_FILTER_NONE;
15225 case HWTSTAMP_FILTER_PTP_V1_L4_EVENT:
15226 case HWTSTAMP_FILTER_PTP_V1_L4_SYNC:
15227 case HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ:
15228 bp->rx_filter = HWTSTAMP_FILTER_PTP_V1_L4_EVENT;
15229 /* Initialize PTP detection for UDP/IPv4 events */
15230 REG_WR(bp, port ? NIG_REG_P1_LLH_PTP_PARAM_MASK :
15231 NIG_REG_P0_LLH_PTP_PARAM_MASK, 0x7EE);
15232 REG_WR(bp, port ? NIG_REG_P1_LLH_PTP_RULE_MASK :
15233 NIG_REG_P0_LLH_PTP_RULE_MASK, 0x3FFE);
15235 case HWTSTAMP_FILTER_PTP_V2_L4_EVENT:
15236 case HWTSTAMP_FILTER_PTP_V2_L4_SYNC:
15237 case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ:
15238 bp->rx_filter = HWTSTAMP_FILTER_PTP_V2_L4_EVENT;
15239 /* Initialize PTP detection for UDP/IPv4 or UDP/IPv6 events */
15240 REG_WR(bp, port ? NIG_REG_P1_LLH_PTP_PARAM_MASK :
15241 NIG_REG_P0_LLH_PTP_PARAM_MASK, 0x7EA);
15242 REG_WR(bp, port ? NIG_REG_P1_LLH_PTP_RULE_MASK :
15243 NIG_REG_P0_LLH_PTP_RULE_MASK, 0x3FEE);
15245 case HWTSTAMP_FILTER_PTP_V2_L2_EVENT:
15246 case HWTSTAMP_FILTER_PTP_V2_L2_SYNC:
15247 case HWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ:
15248 bp->rx_filter = HWTSTAMP_FILTER_PTP_V2_L2_EVENT;
15249 /* Initialize PTP detection L2 events */
15250 REG_WR(bp, port ? NIG_REG_P1_LLH_PTP_PARAM_MASK :
15251 NIG_REG_P0_LLH_PTP_PARAM_MASK, 0x6BF);
15252 REG_WR(bp, port ? NIG_REG_P1_LLH_PTP_RULE_MASK :
15253 NIG_REG_P0_LLH_PTP_RULE_MASK, 0x3EFF);
15256 case HWTSTAMP_FILTER_PTP_V2_EVENT:
15257 case HWTSTAMP_FILTER_PTP_V2_SYNC:
15258 case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ:
15259 bp->rx_filter = HWTSTAMP_FILTER_PTP_V2_EVENT;
15260 /* Initialize PTP detection L2, UDP/IPv4 or UDP/IPv6 events */
15261 REG_WR(bp, port ? NIG_REG_P1_LLH_PTP_PARAM_MASK :
15262 NIG_REG_P0_LLH_PTP_PARAM_MASK, 0x6AA);
15263 REG_WR(bp, port ? NIG_REG_P1_LLH_PTP_RULE_MASK :
15264 NIG_REG_P0_LLH_PTP_RULE_MASK, 0x3EEE);
15268 /* Indicate to FW that this PF expects recorded PTP packets */
15269 rc = bnx2x_enable_ptp_packets(bp);
15273 /* Enable sending PTP packets to host */
15274 REG_WR(bp, port ? NIG_REG_P1_LLH_PTP_TO_HOST :
15275 NIG_REG_P0_LLH_PTP_TO_HOST, 0x1);
15280 static int bnx2x_hwtstamp_ioctl(struct bnx2x *bp, struct ifreq *ifr)
15282 struct hwtstamp_config config;
15285 DP(BNX2X_MSG_PTP, "HWTSTAMP IOCTL called\n");
15287 if (copy_from_user(&config, ifr->ifr_data, sizeof(config)))
15290 DP(BNX2X_MSG_PTP, "Requested tx_type: %d, requested rx_filters = %d\n",
15291 config.tx_type, config.rx_filter);
15293 if (config.flags) {
15294 BNX2X_ERR("config.flags is reserved for future use\n");
15298 bp->hwtstamp_ioctl_called = 1;
15299 bp->tx_type = config.tx_type;
15300 bp->rx_filter = config.rx_filter;
15302 rc = bnx2x_configure_ptp_filters(bp);
15306 config.rx_filter = bp->rx_filter;
15308 return copy_to_user(ifr->ifr_data, &config, sizeof(config)) ?
15312 /* Configures HW for PTP */
15313 static int bnx2x_configure_ptp(struct bnx2x *bp)
15315 int rc, port = BP_PORT(bp);
15318 /* Reset PTP event detection rules - will be configured in the IOCTL */
15319 REG_WR(bp, port ? NIG_REG_P1_LLH_PTP_PARAM_MASK :
15320 NIG_REG_P0_LLH_PTP_PARAM_MASK, 0x7FF);
15321 REG_WR(bp, port ? NIG_REG_P1_LLH_PTP_RULE_MASK :
15322 NIG_REG_P0_LLH_PTP_RULE_MASK, 0x3FFF);
15323 REG_WR(bp, port ? NIG_REG_P1_TLLH_PTP_PARAM_MASK :
15324 NIG_REG_P0_TLLH_PTP_PARAM_MASK, 0x7FF);
15325 REG_WR(bp, port ? NIG_REG_P1_TLLH_PTP_RULE_MASK :
15326 NIG_REG_P0_TLLH_PTP_RULE_MASK, 0x3FFF);
15328 /* Disable PTP packets to host - will be configured in the IOCTL*/
15329 REG_WR(bp, port ? NIG_REG_P1_LLH_PTP_TO_HOST :
15330 NIG_REG_P0_LLH_PTP_TO_HOST, 0x0);
15332 /* Enable the PTP feature */
15333 REG_WR(bp, port ? NIG_REG_P1_PTP_EN :
15334 NIG_REG_P0_PTP_EN, 0x3F);
15336 /* Enable the free-running counter */
15339 REG_WR_DMAE(bp, NIG_REG_TIMESYNC_GEN_REG + tsgen_ctrl, wb_data, 2);
15341 /* Reset drift register (offset register is not reset) */
15342 rc = bnx2x_send_reset_timesync_ramrod(bp);
15344 BNX2X_ERR("Failed to reset PHC drift register\n");
15348 /* Reset possibly old timestamps */
15349 REG_WR(bp, port ? NIG_REG_P1_LLH_PTP_HOST_BUF_SEQID :
15350 NIG_REG_P0_LLH_PTP_HOST_BUF_SEQID, 0x10000);
15351 REG_WR(bp, port ? NIG_REG_P1_TLLH_PTP_BUF_SEQID :
15352 NIG_REG_P0_TLLH_PTP_BUF_SEQID, 0x10000);
15357 /* Called during load, to initialize PTP-related stuff */
15358 void bnx2x_init_ptp(struct bnx2x *bp)
15362 /* Configure PTP in HW */
15363 rc = bnx2x_configure_ptp(bp);
15365 BNX2X_ERR("Stopping PTP initialization\n");
15369 /* Init work queue for Tx timestamping */
15370 INIT_WORK(&bp->ptp_task, bnx2x_ptp_task);
15372 /* Init cyclecounter and timecounter. This is done only in the first
15373 * load. If done in every load, PTP application will fail when doing
15374 * unload / load (e.g. MTU change) while it is running.
15376 if (!bp->timecounter_init_done) {
15377 bnx2x_init_cyclecounter(bp);
15378 timecounter_init(&bp->timecounter, &bp->cyclecounter,
15379 ktime_to_ns(ktime_get_real()));
15380 bp->timecounter_init_done = 1;
15383 DP(BNX2X_MSG_PTP, "PTP initialization ended successfully\n");