1 /* bnx2x_main.c: Broadcom Everest network driver.
3 * Copyright (c) 2007-2013 Broadcom Corporation
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation.
9 * Maintained by: Ariel Elior <ariel.elior@qlogic.com>
10 * Written by: Eliezer Tamir
11 * Based on code from Michael Chan's bnx2 driver
12 * UDP CSUM errata workaround by Arik Gendelman
13 * Slowpath and fastpath rework by Vladislav Zolotarov
14 * Statistics and Link management by Yitchak Gertner
18 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
20 #include <linux/module.h>
21 #include <linux/moduleparam.h>
22 #include <linux/kernel.h>
23 #include <linux/device.h> /* for dev_info() */
24 #include <linux/timer.h>
25 #include <linux/errno.h>
26 #include <linux/ioport.h>
27 #include <linux/slab.h>
28 #include <linux/interrupt.h>
29 #include <linux/pci.h>
30 #include <linux/aer.h>
31 #include <linux/init.h>
32 #include <linux/netdevice.h>
33 #include <linux/etherdevice.h>
34 #include <linux/skbuff.h>
35 #include <linux/dma-mapping.h>
36 #include <linux/bitops.h>
37 #include <linux/irq.h>
38 #include <linux/delay.h>
39 #include <asm/byteorder.h>
40 #include <linux/time.h>
41 #include <linux/ethtool.h>
42 #include <linux/mii.h>
43 #include <linux/if_vlan.h>
44 #include <linux/crash_dump.h>
48 #include <net/vxlan.h>
49 #include <net/checksum.h>
50 #include <net/ip6_checksum.h>
51 #include <linux/workqueue.h>
52 #include <linux/crc32.h>
53 #include <linux/crc32c.h>
54 #include <linux/prefetch.h>
55 #include <linux/zlib.h>
57 #include <linux/semaphore.h>
58 #include <linux/stringify.h>
59 #include <linux/vmalloc.h>
62 #include "bnx2x_init.h"
63 #include "bnx2x_init_ops.h"
64 #include "bnx2x_cmn.h"
65 #include "bnx2x_vfpf.h"
66 #include "bnx2x_dcb.h"
68 #include <linux/firmware.h>
69 #include "bnx2x_fw_file_hdr.h"
71 #define FW_FILE_VERSION \
72 __stringify(BCM_5710_FW_MAJOR_VERSION) "." \
73 __stringify(BCM_5710_FW_MINOR_VERSION) "." \
74 __stringify(BCM_5710_FW_REVISION_VERSION) "." \
75 __stringify(BCM_5710_FW_ENGINEERING_VERSION)
76 #define FW_FILE_NAME_E1 "bnx2x/bnx2x-e1-" FW_FILE_VERSION ".fw"
77 #define FW_FILE_NAME_E1H "bnx2x/bnx2x-e1h-" FW_FILE_VERSION ".fw"
78 #define FW_FILE_NAME_E2 "bnx2x/bnx2x-e2-" FW_FILE_VERSION ".fw"
80 /* Time in jiffies before concluding the transmitter is hung */
81 #define TX_TIMEOUT (5*HZ)
83 static char version[] =
84 "Broadcom NetXtreme II 5771x/578xx 10/20-Gigabit Ethernet Driver "
85 DRV_MODULE_NAME " " DRV_MODULE_VERSION " (" DRV_MODULE_RELDATE ")\n";
87 MODULE_AUTHOR("Eliezer Tamir");
88 MODULE_DESCRIPTION("Broadcom NetXtreme II "
89 "BCM57710/57711/57711E/"
90 "57712/57712_MF/57800/57800_MF/57810/57810_MF/"
91 "57840/57840_MF Driver");
92 MODULE_LICENSE("GPL");
93 MODULE_VERSION(DRV_MODULE_VERSION);
94 MODULE_FIRMWARE(FW_FILE_NAME_E1);
95 MODULE_FIRMWARE(FW_FILE_NAME_E1H);
96 MODULE_FIRMWARE(FW_FILE_NAME_E2);
99 module_param_named(num_queues, bnx2x_num_queues, int, S_IRUGO);
100 MODULE_PARM_DESC(num_queues,
101 " Set number of queues (default is as a number of CPUs)");
103 static int disable_tpa;
104 module_param(disable_tpa, int, S_IRUGO);
105 MODULE_PARM_DESC(disable_tpa, " Disable the TPA (LRO) feature");
108 module_param(int_mode, int, S_IRUGO);
109 MODULE_PARM_DESC(int_mode, " Force interrupt mode other than MSI-X "
112 static int dropless_fc;
113 module_param(dropless_fc, int, S_IRUGO);
114 MODULE_PARM_DESC(dropless_fc, " Pause on exhausted host ring");
116 static int mrrs = -1;
117 module_param(mrrs, int, S_IRUGO);
118 MODULE_PARM_DESC(mrrs, " Force Max Read Req Size (0..3) (for debug)");
121 module_param(debug, int, S_IRUGO);
122 MODULE_PARM_DESC(debug, " Default debug msglevel");
124 static struct workqueue_struct *bnx2x_wq;
125 struct workqueue_struct *bnx2x_iov_wq;
127 struct bnx2x_mac_vals {
138 enum bnx2x_board_type {
162 /* indexed by board_type, above */
166 [BCM57710] = { "Broadcom NetXtreme II BCM57710 10 Gigabit PCIe [Everest]" },
167 [BCM57711] = { "Broadcom NetXtreme II BCM57711 10 Gigabit PCIe" },
168 [BCM57711E] = { "Broadcom NetXtreme II BCM57711E 10 Gigabit PCIe" },
169 [BCM57712] = { "Broadcom NetXtreme II BCM57712 10 Gigabit Ethernet" },
170 [BCM57712_MF] = { "Broadcom NetXtreme II BCM57712 10 Gigabit Ethernet Multi Function" },
171 [BCM57712_VF] = { "Broadcom NetXtreme II BCM57712 10 Gigabit Ethernet Virtual Function" },
172 [BCM57800] = { "Broadcom NetXtreme II BCM57800 10 Gigabit Ethernet" },
173 [BCM57800_MF] = { "Broadcom NetXtreme II BCM57800 10 Gigabit Ethernet Multi Function" },
174 [BCM57800_VF] = { "Broadcom NetXtreme II BCM57800 10 Gigabit Ethernet Virtual Function" },
175 [BCM57810] = { "Broadcom NetXtreme II BCM57810 10 Gigabit Ethernet" },
176 [BCM57810_MF] = { "Broadcom NetXtreme II BCM57810 10 Gigabit Ethernet Multi Function" },
177 [BCM57810_VF] = { "Broadcom NetXtreme II BCM57810 10 Gigabit Ethernet Virtual Function" },
178 [BCM57840_4_10] = { "Broadcom NetXtreme II BCM57840 10 Gigabit Ethernet" },
179 [BCM57840_2_20] = { "Broadcom NetXtreme II BCM57840 20 Gigabit Ethernet" },
180 [BCM57840_MF] = { "Broadcom NetXtreme II BCM57840 10/20 Gigabit Ethernet Multi Function" },
181 [BCM57840_VF] = { "Broadcom NetXtreme II BCM57840 10/20 Gigabit Ethernet Virtual Function" },
182 [BCM57811] = { "Broadcom NetXtreme II BCM57811 10 Gigabit Ethernet" },
183 [BCM57811_MF] = { "Broadcom NetXtreme II BCM57811 10 Gigabit Ethernet Multi Function" },
184 [BCM57840_O] = { "Broadcom NetXtreme II BCM57840 10/20 Gigabit Ethernet" },
185 [BCM57840_MFO] = { "Broadcom NetXtreme II BCM57840 10/20 Gigabit Ethernet Multi Function" },
186 [BCM57811_VF] = { "Broadcom NetXtreme II BCM57840 10/20 Gigabit Ethernet Virtual Function" }
189 #ifndef PCI_DEVICE_ID_NX2_57710
190 #define PCI_DEVICE_ID_NX2_57710 CHIP_NUM_57710
192 #ifndef PCI_DEVICE_ID_NX2_57711
193 #define PCI_DEVICE_ID_NX2_57711 CHIP_NUM_57711
195 #ifndef PCI_DEVICE_ID_NX2_57711E
196 #define PCI_DEVICE_ID_NX2_57711E CHIP_NUM_57711E
198 #ifndef PCI_DEVICE_ID_NX2_57712
199 #define PCI_DEVICE_ID_NX2_57712 CHIP_NUM_57712
201 #ifndef PCI_DEVICE_ID_NX2_57712_MF
202 #define PCI_DEVICE_ID_NX2_57712_MF CHIP_NUM_57712_MF
204 #ifndef PCI_DEVICE_ID_NX2_57712_VF
205 #define PCI_DEVICE_ID_NX2_57712_VF CHIP_NUM_57712_VF
207 #ifndef PCI_DEVICE_ID_NX2_57800
208 #define PCI_DEVICE_ID_NX2_57800 CHIP_NUM_57800
210 #ifndef PCI_DEVICE_ID_NX2_57800_MF
211 #define PCI_DEVICE_ID_NX2_57800_MF CHIP_NUM_57800_MF
213 #ifndef PCI_DEVICE_ID_NX2_57800_VF
214 #define PCI_DEVICE_ID_NX2_57800_VF CHIP_NUM_57800_VF
216 #ifndef PCI_DEVICE_ID_NX2_57810
217 #define PCI_DEVICE_ID_NX2_57810 CHIP_NUM_57810
219 #ifndef PCI_DEVICE_ID_NX2_57810_MF
220 #define PCI_DEVICE_ID_NX2_57810_MF CHIP_NUM_57810_MF
222 #ifndef PCI_DEVICE_ID_NX2_57840_O
223 #define PCI_DEVICE_ID_NX2_57840_O CHIP_NUM_57840_OBSOLETE
225 #ifndef PCI_DEVICE_ID_NX2_57810_VF
226 #define PCI_DEVICE_ID_NX2_57810_VF CHIP_NUM_57810_VF
228 #ifndef PCI_DEVICE_ID_NX2_57840_4_10
229 #define PCI_DEVICE_ID_NX2_57840_4_10 CHIP_NUM_57840_4_10
231 #ifndef PCI_DEVICE_ID_NX2_57840_2_20
232 #define PCI_DEVICE_ID_NX2_57840_2_20 CHIP_NUM_57840_2_20
234 #ifndef PCI_DEVICE_ID_NX2_57840_MFO
235 #define PCI_DEVICE_ID_NX2_57840_MFO CHIP_NUM_57840_MF_OBSOLETE
237 #ifndef PCI_DEVICE_ID_NX2_57840_MF
238 #define PCI_DEVICE_ID_NX2_57840_MF CHIP_NUM_57840_MF
240 #ifndef PCI_DEVICE_ID_NX2_57840_VF
241 #define PCI_DEVICE_ID_NX2_57840_VF CHIP_NUM_57840_VF
243 #ifndef PCI_DEVICE_ID_NX2_57811
244 #define PCI_DEVICE_ID_NX2_57811 CHIP_NUM_57811
246 #ifndef PCI_DEVICE_ID_NX2_57811_MF
247 #define PCI_DEVICE_ID_NX2_57811_MF CHIP_NUM_57811_MF
249 #ifndef PCI_DEVICE_ID_NX2_57811_VF
250 #define PCI_DEVICE_ID_NX2_57811_VF CHIP_NUM_57811_VF
253 static const struct pci_device_id bnx2x_pci_tbl[] = {
254 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57710), BCM57710 },
255 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57711), BCM57711 },
256 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57711E), BCM57711E },
257 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57712), BCM57712 },
258 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57712_MF), BCM57712_MF },
259 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57712_VF), BCM57712_VF },
260 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57800), BCM57800 },
261 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57800_MF), BCM57800_MF },
262 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57800_VF), BCM57800_VF },
263 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57810), BCM57810 },
264 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57810_MF), BCM57810_MF },
265 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57840_O), BCM57840_O },
266 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57840_4_10), BCM57840_4_10 },
267 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57840_2_20), BCM57840_2_20 },
268 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57810_VF), BCM57810_VF },
269 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57840_MFO), BCM57840_MFO },
270 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57840_MF), BCM57840_MF },
271 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57840_VF), BCM57840_VF },
272 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57811), BCM57811 },
273 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57811_MF), BCM57811_MF },
274 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57811_VF), BCM57811_VF },
278 MODULE_DEVICE_TABLE(pci, bnx2x_pci_tbl);
280 /* Global resources for unloading a previously loaded device */
281 #define BNX2X_PREV_WAIT_NEEDED 1
282 static DEFINE_SEMAPHORE(bnx2x_prev_sem);
283 static LIST_HEAD(bnx2x_prev_list);
285 /* Forward declaration */
286 static struct cnic_eth_dev *bnx2x_cnic_probe(struct net_device *dev);
287 static u32 bnx2x_rx_ustorm_prods_offset(struct bnx2x_fastpath *fp);
288 static int bnx2x_set_storm_rx_mode(struct bnx2x *bp);
290 /****************************************************************************
291 * General service functions
292 ****************************************************************************/
294 static int bnx2x_hwtstamp_ioctl(struct bnx2x *bp, struct ifreq *ifr);
296 static void __storm_memset_dma_mapping(struct bnx2x *bp,
297 u32 addr, dma_addr_t mapping)
299 REG_WR(bp, addr, U64_LO(mapping));
300 REG_WR(bp, addr + 4, U64_HI(mapping));
303 static void storm_memset_spq_addr(struct bnx2x *bp,
304 dma_addr_t mapping, u16 abs_fid)
306 u32 addr = XSEM_REG_FAST_MEMORY +
307 XSTORM_SPQ_PAGE_BASE_OFFSET(abs_fid);
309 __storm_memset_dma_mapping(bp, addr, mapping);
312 static void storm_memset_vf_to_pf(struct bnx2x *bp, u16 abs_fid,
315 REG_WR8(bp, BAR_XSTRORM_INTMEM + XSTORM_VF_TO_PF_OFFSET(abs_fid),
317 REG_WR8(bp, BAR_CSTRORM_INTMEM + CSTORM_VF_TO_PF_OFFSET(abs_fid),
319 REG_WR8(bp, BAR_TSTRORM_INTMEM + TSTORM_VF_TO_PF_OFFSET(abs_fid),
321 REG_WR8(bp, BAR_USTRORM_INTMEM + USTORM_VF_TO_PF_OFFSET(abs_fid),
325 static void storm_memset_func_en(struct bnx2x *bp, u16 abs_fid,
328 REG_WR8(bp, BAR_XSTRORM_INTMEM + XSTORM_FUNC_EN_OFFSET(abs_fid),
330 REG_WR8(bp, BAR_CSTRORM_INTMEM + CSTORM_FUNC_EN_OFFSET(abs_fid),
332 REG_WR8(bp, BAR_TSTRORM_INTMEM + TSTORM_FUNC_EN_OFFSET(abs_fid),
334 REG_WR8(bp, BAR_USTRORM_INTMEM + USTORM_FUNC_EN_OFFSET(abs_fid),
338 static void storm_memset_eq_data(struct bnx2x *bp,
339 struct event_ring_data *eq_data,
342 size_t size = sizeof(struct event_ring_data);
344 u32 addr = BAR_CSTRORM_INTMEM + CSTORM_EVENT_RING_DATA_OFFSET(pfid);
346 __storm_memset_struct(bp, addr, size, (u32 *)eq_data);
349 static void storm_memset_eq_prod(struct bnx2x *bp, u16 eq_prod,
352 u32 addr = BAR_CSTRORM_INTMEM + CSTORM_EVENT_RING_PROD_OFFSET(pfid);
353 REG_WR16(bp, addr, eq_prod);
357 * locking is done by mcp
359 static void bnx2x_reg_wr_ind(struct bnx2x *bp, u32 addr, u32 val)
361 pci_write_config_dword(bp->pdev, PCICFG_GRC_ADDRESS, addr);
362 pci_write_config_dword(bp->pdev, PCICFG_GRC_DATA, val);
363 pci_write_config_dword(bp->pdev, PCICFG_GRC_ADDRESS,
364 PCICFG_VENDOR_ID_OFFSET);
367 static u32 bnx2x_reg_rd_ind(struct bnx2x *bp, u32 addr)
371 pci_write_config_dword(bp->pdev, PCICFG_GRC_ADDRESS, addr);
372 pci_read_config_dword(bp->pdev, PCICFG_GRC_DATA, &val);
373 pci_write_config_dword(bp->pdev, PCICFG_GRC_ADDRESS,
374 PCICFG_VENDOR_ID_OFFSET);
379 #define DMAE_DP_SRC_GRC "grc src_addr [%08x]"
380 #define DMAE_DP_SRC_PCI "pci src_addr [%x:%08x]"
381 #define DMAE_DP_DST_GRC "grc dst_addr [%08x]"
382 #define DMAE_DP_DST_PCI "pci dst_addr [%x:%08x]"
383 #define DMAE_DP_DST_NONE "dst_addr [none]"
385 static void bnx2x_dp_dmae(struct bnx2x *bp,
386 struct dmae_command *dmae, int msglvl)
388 u32 src_type = dmae->opcode & DMAE_COMMAND_SRC;
391 switch (dmae->opcode & DMAE_COMMAND_DST) {
392 case DMAE_CMD_DST_PCI:
393 if (src_type == DMAE_CMD_SRC_PCI)
394 DP(msglvl, "DMAE: opcode 0x%08x\n"
395 "src [%x:%08x], len [%d*4], dst [%x:%08x]\n"
396 "comp_addr [%x:%08x], comp_val 0x%08x\n",
397 dmae->opcode, dmae->src_addr_hi, dmae->src_addr_lo,
398 dmae->len, dmae->dst_addr_hi, dmae->dst_addr_lo,
399 dmae->comp_addr_hi, dmae->comp_addr_lo,
402 DP(msglvl, "DMAE: opcode 0x%08x\n"
403 "src [%08x], len [%d*4], dst [%x:%08x]\n"
404 "comp_addr [%x:%08x], comp_val 0x%08x\n",
405 dmae->opcode, dmae->src_addr_lo >> 2,
406 dmae->len, dmae->dst_addr_hi, dmae->dst_addr_lo,
407 dmae->comp_addr_hi, dmae->comp_addr_lo,
410 case DMAE_CMD_DST_GRC:
411 if (src_type == DMAE_CMD_SRC_PCI)
412 DP(msglvl, "DMAE: opcode 0x%08x\n"
413 "src [%x:%08x], len [%d*4], dst_addr [%08x]\n"
414 "comp_addr [%x:%08x], comp_val 0x%08x\n",
415 dmae->opcode, dmae->src_addr_hi, dmae->src_addr_lo,
416 dmae->len, dmae->dst_addr_lo >> 2,
417 dmae->comp_addr_hi, dmae->comp_addr_lo,
420 DP(msglvl, "DMAE: opcode 0x%08x\n"
421 "src [%08x], len [%d*4], dst [%08x]\n"
422 "comp_addr [%x:%08x], comp_val 0x%08x\n",
423 dmae->opcode, dmae->src_addr_lo >> 2,
424 dmae->len, dmae->dst_addr_lo >> 2,
425 dmae->comp_addr_hi, dmae->comp_addr_lo,
429 if (src_type == DMAE_CMD_SRC_PCI)
430 DP(msglvl, "DMAE: opcode 0x%08x\n"
431 "src_addr [%x:%08x] len [%d * 4] dst_addr [none]\n"
432 "comp_addr [%x:%08x] comp_val 0x%08x\n",
433 dmae->opcode, dmae->src_addr_hi, dmae->src_addr_lo,
434 dmae->len, dmae->comp_addr_hi, dmae->comp_addr_lo,
437 DP(msglvl, "DMAE: opcode 0x%08x\n"
438 "src_addr [%08x] len [%d * 4] dst_addr [none]\n"
439 "comp_addr [%x:%08x] comp_val 0x%08x\n",
440 dmae->opcode, dmae->src_addr_lo >> 2,
441 dmae->len, dmae->comp_addr_hi, dmae->comp_addr_lo,
446 for (i = 0; i < (sizeof(struct dmae_command)/4); i++)
447 DP(msglvl, "DMAE RAW [%02d]: 0x%08x\n",
448 i, *(((u32 *)dmae) + i));
451 /* copy command into DMAE command memory and set DMAE command go */
452 void bnx2x_post_dmae(struct bnx2x *bp, struct dmae_command *dmae, int idx)
457 cmd_offset = (DMAE_REG_CMD_MEM + sizeof(struct dmae_command) * idx);
458 for (i = 0; i < (sizeof(struct dmae_command)/4); i++) {
459 REG_WR(bp, cmd_offset + i*4, *(((u32 *)dmae) + i));
461 REG_WR(bp, dmae_reg_go_c[idx], 1);
464 u32 bnx2x_dmae_opcode_add_comp(u32 opcode, u8 comp_type)
466 return opcode | ((comp_type << DMAE_COMMAND_C_DST_SHIFT) |
470 u32 bnx2x_dmae_opcode_clr_src_reset(u32 opcode)
472 return opcode & ~DMAE_CMD_SRC_RESET;
475 u32 bnx2x_dmae_opcode(struct bnx2x *bp, u8 src_type, u8 dst_type,
476 bool with_comp, u8 comp_type)
480 opcode |= ((src_type << DMAE_COMMAND_SRC_SHIFT) |
481 (dst_type << DMAE_COMMAND_DST_SHIFT));
483 opcode |= (DMAE_CMD_SRC_RESET | DMAE_CMD_DST_RESET);
485 opcode |= (BP_PORT(bp) ? DMAE_CMD_PORT_1 : DMAE_CMD_PORT_0);
486 opcode |= ((BP_VN(bp) << DMAE_CMD_E1HVN_SHIFT) |
487 (BP_VN(bp) << DMAE_COMMAND_DST_VN_SHIFT));
488 opcode |= (DMAE_COM_SET_ERR << DMAE_COMMAND_ERR_POLICY_SHIFT);
491 opcode |= DMAE_CMD_ENDIANITY_B_DW_SWAP;
493 opcode |= DMAE_CMD_ENDIANITY_DW_SWAP;
496 opcode = bnx2x_dmae_opcode_add_comp(opcode, comp_type);
500 void bnx2x_prep_dmae_with_comp(struct bnx2x *bp,
501 struct dmae_command *dmae,
502 u8 src_type, u8 dst_type)
504 memset(dmae, 0, sizeof(struct dmae_command));
507 dmae->opcode = bnx2x_dmae_opcode(bp, src_type, dst_type,
508 true, DMAE_COMP_PCI);
510 /* fill in the completion parameters */
511 dmae->comp_addr_lo = U64_LO(bnx2x_sp_mapping(bp, wb_comp));
512 dmae->comp_addr_hi = U64_HI(bnx2x_sp_mapping(bp, wb_comp));
513 dmae->comp_val = DMAE_COMP_VAL;
516 /* issue a dmae command over the init-channel and wait for completion */
517 int bnx2x_issue_dmae_with_comp(struct bnx2x *bp, struct dmae_command *dmae,
520 int cnt = CHIP_REV_IS_SLOW(bp) ? (400000) : 4000;
523 bnx2x_dp_dmae(bp, dmae, BNX2X_MSG_DMAE);
525 /* Lock the dmae channel. Disable BHs to prevent a dead-lock
526 * as long as this code is called both from syscall context and
527 * from ndo_set_rx_mode() flow that may be called from BH.
530 spin_lock_bh(&bp->dmae_lock);
532 /* reset completion */
535 /* post the command on the channel used for initializations */
536 bnx2x_post_dmae(bp, dmae, INIT_DMAE_C(bp));
538 /* wait for completion */
540 while ((*comp & ~DMAE_PCI_ERR_FLAG) != DMAE_COMP_VAL) {
543 (bp->recovery_state != BNX2X_RECOVERY_DONE &&
544 bp->recovery_state != BNX2X_RECOVERY_NIC_LOADING)) {
545 BNX2X_ERR("DMAE timeout!\n");
552 if (*comp & DMAE_PCI_ERR_FLAG) {
553 BNX2X_ERR("DMAE PCI error!\n");
559 spin_unlock_bh(&bp->dmae_lock);
564 void bnx2x_write_dmae(struct bnx2x *bp, dma_addr_t dma_addr, u32 dst_addr,
568 struct dmae_command dmae;
570 if (!bp->dmae_ready) {
571 u32 *data = bnx2x_sp(bp, wb_data[0]);
574 bnx2x_init_ind_wr(bp, dst_addr, data, len32);
576 bnx2x_init_str_wr(bp, dst_addr, data, len32);
580 /* set opcode and fixed command fields */
581 bnx2x_prep_dmae_with_comp(bp, &dmae, DMAE_SRC_PCI, DMAE_DST_GRC);
583 /* fill in addresses and len */
584 dmae.src_addr_lo = U64_LO(dma_addr);
585 dmae.src_addr_hi = U64_HI(dma_addr);
586 dmae.dst_addr_lo = dst_addr >> 2;
587 dmae.dst_addr_hi = 0;
590 /* issue the command and wait for completion */
591 rc = bnx2x_issue_dmae_with_comp(bp, &dmae, bnx2x_sp(bp, wb_comp));
593 BNX2X_ERR("DMAE returned failure %d\n", rc);
594 #ifdef BNX2X_STOP_ON_ERROR
600 void bnx2x_read_dmae(struct bnx2x *bp, u32 src_addr, u32 len32)
603 struct dmae_command dmae;
605 if (!bp->dmae_ready) {
606 u32 *data = bnx2x_sp(bp, wb_data[0]);
610 for (i = 0; i < len32; i++)
611 data[i] = bnx2x_reg_rd_ind(bp, src_addr + i*4);
613 for (i = 0; i < len32; i++)
614 data[i] = REG_RD(bp, src_addr + i*4);
619 /* set opcode and fixed command fields */
620 bnx2x_prep_dmae_with_comp(bp, &dmae, DMAE_SRC_GRC, DMAE_DST_PCI);
622 /* fill in addresses and len */
623 dmae.src_addr_lo = src_addr >> 2;
624 dmae.src_addr_hi = 0;
625 dmae.dst_addr_lo = U64_LO(bnx2x_sp_mapping(bp, wb_data));
626 dmae.dst_addr_hi = U64_HI(bnx2x_sp_mapping(bp, wb_data));
629 /* issue the command and wait for completion */
630 rc = bnx2x_issue_dmae_with_comp(bp, &dmae, bnx2x_sp(bp, wb_comp));
632 BNX2X_ERR("DMAE returned failure %d\n", rc);
633 #ifdef BNX2X_STOP_ON_ERROR
639 static void bnx2x_write_dmae_phys_len(struct bnx2x *bp, dma_addr_t phys_addr,
642 int dmae_wr_max = DMAE_LEN32_WR_MAX(bp);
645 while (len > dmae_wr_max) {
646 bnx2x_write_dmae(bp, phys_addr + offset,
647 addr + offset, dmae_wr_max);
648 offset += dmae_wr_max * 4;
652 bnx2x_write_dmae(bp, phys_addr + offset, addr + offset, len);
664 #define REGS_IN_ENTRY 4
666 static inline int bnx2x_get_assert_list_entry(struct bnx2x *bp,
672 return XSTORM_ASSERT_LIST_OFFSET(entry);
674 return TSTORM_ASSERT_LIST_OFFSET(entry);
676 return CSTORM_ASSERT_LIST_OFFSET(entry);
678 return USTORM_ASSERT_LIST_OFFSET(entry);
681 BNX2X_ERR("unknown storm\n");
686 static int bnx2x_mc_assert(struct bnx2x *bp)
691 u32 regs[REGS_IN_ENTRY];
692 u32 bar_storm_intmem[STORMS_NUM] = {
698 u32 storm_assert_list_index[STORMS_NUM] = {
699 XSTORM_ASSERT_LIST_INDEX_OFFSET,
700 TSTORM_ASSERT_LIST_INDEX_OFFSET,
701 CSTORM_ASSERT_LIST_INDEX_OFFSET,
702 USTORM_ASSERT_LIST_INDEX_OFFSET
704 char *storms_string[STORMS_NUM] = {
711 for (storm = XSTORM; storm < MAX_STORMS; storm++) {
712 last_idx = REG_RD8(bp, bar_storm_intmem[storm] +
713 storm_assert_list_index[storm]);
715 BNX2X_ERR("%s_ASSERT_LIST_INDEX 0x%x\n",
716 storms_string[storm], last_idx);
718 /* print the asserts */
719 for (i = 0; i < STROM_ASSERT_ARRAY_SIZE; i++) {
720 /* read a single assert entry */
721 for (j = 0; j < REGS_IN_ENTRY; j++)
722 regs[j] = REG_RD(bp, bar_storm_intmem[storm] +
723 bnx2x_get_assert_list_entry(bp,
728 /* log entry if it contains a valid assert */
729 if (regs[0] != COMMON_ASM_INVALID_ASSERT_OPCODE) {
730 BNX2X_ERR("%s_ASSERT_INDEX 0x%x = 0x%08x 0x%08x 0x%08x 0x%08x\n",
731 storms_string[storm], i, regs[3],
732 regs[2], regs[1], regs[0]);
740 BNX2X_ERR("Chip Revision: %s, FW Version: %d_%d_%d\n",
741 CHIP_IS_E1(bp) ? "everest1" :
742 CHIP_IS_E1H(bp) ? "everest1h" :
743 CHIP_IS_E2(bp) ? "everest2" : "everest3",
744 BCM_5710_FW_MAJOR_VERSION,
745 BCM_5710_FW_MINOR_VERSION,
746 BCM_5710_FW_REVISION_VERSION);
751 #define MCPR_TRACE_BUFFER_SIZE (0x800)
752 #define SCRATCH_BUFFER_SIZE(bp) \
753 (CHIP_IS_E1(bp) ? 0x10000 : (CHIP_IS_E1H(bp) ? 0x20000 : 0x28000))
755 void bnx2x_fw_dump_lvl(struct bnx2x *bp, const char *lvl)
761 u32 trace_shmem_base;
763 BNX2X_ERR("NO MCP - can not dump\n");
766 netdev_printk(lvl, bp->dev, "bc %d.%d.%d\n",
767 (bp->common.bc_ver & 0xff0000) >> 16,
768 (bp->common.bc_ver & 0xff00) >> 8,
769 (bp->common.bc_ver & 0xff));
771 val = REG_RD(bp, MCP_REG_MCPR_CPU_PROGRAM_COUNTER);
772 if (val == REG_RD(bp, MCP_REG_MCPR_CPU_PROGRAM_COUNTER))
773 BNX2X_ERR("%s" "MCP PC at 0x%x\n", lvl, val);
775 if (BP_PATH(bp) == 0)
776 trace_shmem_base = bp->common.shmem_base;
778 trace_shmem_base = SHMEM2_RD(bp, other_shmem_base_addr);
781 if (trace_shmem_base < MCPR_SCRATCH_BASE(bp) + MCPR_TRACE_BUFFER_SIZE ||
782 trace_shmem_base >= MCPR_SCRATCH_BASE(bp) +
783 SCRATCH_BUFFER_SIZE(bp)) {
784 BNX2X_ERR("Unable to dump trace buffer (mark %x)\n",
789 addr = trace_shmem_base - MCPR_TRACE_BUFFER_SIZE;
791 /* validate TRCB signature */
792 mark = REG_RD(bp, addr);
793 if (mark != MFW_TRACE_SIGNATURE) {
794 BNX2X_ERR("Trace buffer signature is missing.");
798 /* read cyclic buffer pointer */
800 mark = REG_RD(bp, addr);
801 mark = MCPR_SCRATCH_BASE(bp) + ((mark + 0x3) & ~0x3) - 0x08000000;
802 if (mark >= trace_shmem_base || mark < addr + 4) {
803 BNX2X_ERR("Mark doesn't fall inside Trace Buffer\n");
806 printk("%s" "begin fw dump (mark 0x%x)\n", lvl, mark);
810 /* dump buffer after the mark */
811 for (offset = mark; offset < trace_shmem_base; offset += 0x8*4) {
812 for (word = 0; word < 8; word++)
813 data[word] = htonl(REG_RD(bp, offset + 4*word));
815 pr_cont("%s", (char *)data);
818 /* dump buffer before the mark */
819 for (offset = addr + 4; offset <= mark; offset += 0x8*4) {
820 for (word = 0; word < 8; word++)
821 data[word] = htonl(REG_RD(bp, offset + 4*word));
823 pr_cont("%s", (char *)data);
825 printk("%s" "end of fw dump\n", lvl);
828 static void bnx2x_fw_dump(struct bnx2x *bp)
830 bnx2x_fw_dump_lvl(bp, KERN_ERR);
833 static void bnx2x_hc_int_disable(struct bnx2x *bp)
835 int port = BP_PORT(bp);
836 u32 addr = port ? HC_REG_CONFIG_1 : HC_REG_CONFIG_0;
837 u32 val = REG_RD(bp, addr);
839 /* in E1 we must use only PCI configuration space to disable
840 * MSI/MSIX capability
841 * It's forbidden to disable IGU_PF_CONF_MSI_MSIX_EN in HC block
843 if (CHIP_IS_E1(bp)) {
844 /* Since IGU_PF_CONF_MSI_MSIX_EN still always on
845 * Use mask register to prevent from HC sending interrupts
846 * after we exit the function
848 REG_WR(bp, HC_REG_INT_MASK + port*4, 0);
850 val &= ~(HC_CONFIG_0_REG_SINGLE_ISR_EN_0 |
851 HC_CONFIG_0_REG_INT_LINE_EN_0 |
852 HC_CONFIG_0_REG_ATTN_BIT_EN_0);
854 val &= ~(HC_CONFIG_0_REG_SINGLE_ISR_EN_0 |
855 HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0 |
856 HC_CONFIG_0_REG_INT_LINE_EN_0 |
857 HC_CONFIG_0_REG_ATTN_BIT_EN_0);
860 "write %x to HC %d (addr 0x%x)\n",
863 /* flush all outstanding writes */
866 REG_WR(bp, addr, val);
867 if (REG_RD(bp, addr) != val)
868 BNX2X_ERR("BUG! Proper val not read from IGU!\n");
871 static void bnx2x_igu_int_disable(struct bnx2x *bp)
873 u32 val = REG_RD(bp, IGU_REG_PF_CONFIGURATION);
875 val &= ~(IGU_PF_CONF_MSI_MSIX_EN |
876 IGU_PF_CONF_INT_LINE_EN |
877 IGU_PF_CONF_ATTN_BIT_EN);
879 DP(NETIF_MSG_IFDOWN, "write %x to IGU\n", val);
881 /* flush all outstanding writes */
884 REG_WR(bp, IGU_REG_PF_CONFIGURATION, val);
885 if (REG_RD(bp, IGU_REG_PF_CONFIGURATION) != val)
886 BNX2X_ERR("BUG! Proper val not read from IGU!\n");
889 static void bnx2x_int_disable(struct bnx2x *bp)
891 if (bp->common.int_block == INT_BLOCK_HC)
892 bnx2x_hc_int_disable(bp);
894 bnx2x_igu_int_disable(bp);
897 void bnx2x_panic_dump(struct bnx2x *bp, bool disable_int)
901 struct hc_sp_status_block_data sp_sb_data;
902 int func = BP_FUNC(bp);
903 #ifdef BNX2X_STOP_ON_ERROR
904 u16 start = 0, end = 0;
907 if (IS_PF(bp) && disable_int)
908 bnx2x_int_disable(bp);
910 bp->stats_state = STATS_STATE_DISABLED;
911 bp->eth_stats.unrecoverable_error++;
912 DP(BNX2X_MSG_STATS, "stats_state - DISABLED\n");
914 BNX2X_ERR("begin crash dump -----------------\n");
919 struct host_sp_status_block *def_sb = bp->def_status_blk;
920 int data_size, cstorm_offset;
922 BNX2X_ERR("def_idx(0x%x) def_att_idx(0x%x) attn_state(0x%x) spq_prod_idx(0x%x) next_stats_cnt(0x%x)\n",
923 bp->def_idx, bp->def_att_idx, bp->attn_state,
924 bp->spq_prod_idx, bp->stats_counter);
925 BNX2X_ERR("DSB: attn bits(0x%x) ack(0x%x) id(0x%x) idx(0x%x)\n",
926 def_sb->atten_status_block.attn_bits,
927 def_sb->atten_status_block.attn_bits_ack,
928 def_sb->atten_status_block.status_block_id,
929 def_sb->atten_status_block.attn_bits_index);
931 for (i = 0; i < HC_SP_SB_MAX_INDICES; i++)
933 def_sb->sp_sb.index_values[i],
934 (i == HC_SP_SB_MAX_INDICES - 1) ? ") " : " ");
936 data_size = sizeof(struct hc_sp_status_block_data) /
938 cstorm_offset = CSTORM_SP_STATUS_BLOCK_DATA_OFFSET(func);
939 for (i = 0; i < data_size; i++)
940 *((u32 *)&sp_sb_data + i) =
941 REG_RD(bp, BAR_CSTRORM_INTMEM + cstorm_offset +
944 pr_cont("igu_sb_id(0x%x) igu_seg_id(0x%x) pf_id(0x%x) vnic_id(0x%x) vf_id(0x%x) vf_valid (0x%x) state(0x%x)\n",
945 sp_sb_data.igu_sb_id,
946 sp_sb_data.igu_seg_id,
947 sp_sb_data.p_func.pf_id,
948 sp_sb_data.p_func.vnic_id,
949 sp_sb_data.p_func.vf_id,
950 sp_sb_data.p_func.vf_valid,
954 for_each_eth_queue(bp, i) {
955 struct bnx2x_fastpath *fp = &bp->fp[i];
957 struct hc_status_block_data_e2 sb_data_e2;
958 struct hc_status_block_data_e1x sb_data_e1x;
959 struct hc_status_block_sm *hc_sm_p =
961 sb_data_e1x.common.state_machine :
962 sb_data_e2.common.state_machine;
963 struct hc_index_data *hc_index_p =
965 sb_data_e1x.index_data :
966 sb_data_e2.index_data;
969 struct bnx2x_fp_txdata txdata;
978 BNX2X_ERR("fp%d: rx_bd_prod(0x%x) rx_bd_cons(0x%x) rx_comp_prod(0x%x) rx_comp_cons(0x%x) *rx_cons_sb(0x%x)\n",
979 i, fp->rx_bd_prod, fp->rx_bd_cons,
981 fp->rx_comp_cons, le16_to_cpu(*fp->rx_cons_sb));
982 BNX2X_ERR(" rx_sge_prod(0x%x) last_max_sge(0x%x) fp_hc_idx(0x%x)\n",
983 fp->rx_sge_prod, fp->last_max_sge,
984 le16_to_cpu(fp->fp_hc_idx));
987 for_each_cos_in_tx_queue(fp, cos)
989 if (!fp->txdata_ptr[cos])
992 txdata = *fp->txdata_ptr[cos];
994 if (!txdata.tx_cons_sb)
997 BNX2X_ERR("fp%d: tx_pkt_prod(0x%x) tx_pkt_cons(0x%x) tx_bd_prod(0x%x) tx_bd_cons(0x%x) *tx_cons_sb(0x%x)\n",
998 i, txdata.tx_pkt_prod,
999 txdata.tx_pkt_cons, txdata.tx_bd_prod,
1001 le16_to_cpu(*txdata.tx_cons_sb));
1004 loop = CHIP_IS_E1x(bp) ?
1005 HC_SB_MAX_INDICES_E1X : HC_SB_MAX_INDICES_E2;
1012 BNX2X_ERR(" run indexes (");
1013 for (j = 0; j < HC_SB_MAX_SM; j++)
1015 fp->sb_running_index[j],
1016 (j == HC_SB_MAX_SM - 1) ? ")" : " ");
1018 BNX2X_ERR(" indexes (");
1019 for (j = 0; j < loop; j++)
1021 fp->sb_index_values[j],
1022 (j == loop - 1) ? ")" : " ");
1024 /* VF cannot access FW refelection for status block */
1029 data_size = CHIP_IS_E1x(bp) ?
1030 sizeof(struct hc_status_block_data_e1x) :
1031 sizeof(struct hc_status_block_data_e2);
1032 data_size /= sizeof(u32);
1033 sb_data_p = CHIP_IS_E1x(bp) ?
1034 (u32 *)&sb_data_e1x :
1036 /* copy sb data in here */
1037 for (j = 0; j < data_size; j++)
1038 *(sb_data_p + j) = REG_RD(bp, BAR_CSTRORM_INTMEM +
1039 CSTORM_STATUS_BLOCK_DATA_OFFSET(fp->fw_sb_id) +
1042 if (!CHIP_IS_E1x(bp)) {
1043 pr_cont("pf_id(0x%x) vf_id(0x%x) vf_valid(0x%x) vnic_id(0x%x) same_igu_sb_1b(0x%x) state(0x%x)\n",
1044 sb_data_e2.common.p_func.pf_id,
1045 sb_data_e2.common.p_func.vf_id,
1046 sb_data_e2.common.p_func.vf_valid,
1047 sb_data_e2.common.p_func.vnic_id,
1048 sb_data_e2.common.same_igu_sb_1b,
1049 sb_data_e2.common.state);
1051 pr_cont("pf_id(0x%x) vf_id(0x%x) vf_valid(0x%x) vnic_id(0x%x) same_igu_sb_1b(0x%x) state(0x%x)\n",
1052 sb_data_e1x.common.p_func.pf_id,
1053 sb_data_e1x.common.p_func.vf_id,
1054 sb_data_e1x.common.p_func.vf_valid,
1055 sb_data_e1x.common.p_func.vnic_id,
1056 sb_data_e1x.common.same_igu_sb_1b,
1057 sb_data_e1x.common.state);
1061 for (j = 0; j < HC_SB_MAX_SM; j++) {
1062 pr_cont("SM[%d] __flags (0x%x) igu_sb_id (0x%x) igu_seg_id(0x%x) time_to_expire (0x%x) timer_value(0x%x)\n",
1063 j, hc_sm_p[j].__flags,
1064 hc_sm_p[j].igu_sb_id,
1065 hc_sm_p[j].igu_seg_id,
1066 hc_sm_p[j].time_to_expire,
1067 hc_sm_p[j].timer_value);
1071 for (j = 0; j < loop; j++) {
1072 pr_cont("INDEX[%d] flags (0x%x) timeout (0x%x)\n", j,
1073 hc_index_p[j].flags,
1074 hc_index_p[j].timeout);
1078 #ifdef BNX2X_STOP_ON_ERROR
1081 BNX2X_ERR("eq cons %x prod %x\n", bp->eq_cons, bp->eq_prod);
1082 for (i = 0; i < NUM_EQ_DESC; i++) {
1083 u32 *data = (u32 *)&bp->eq_ring[i].message.data;
1085 BNX2X_ERR("event queue [%d]: header: opcode %d, error %d\n",
1086 i, bp->eq_ring[i].message.opcode,
1087 bp->eq_ring[i].message.error);
1088 BNX2X_ERR("data: %x %x %x\n",
1089 data[0], data[1], data[2]);
1095 for_each_valid_rx_queue(bp, i) {
1096 struct bnx2x_fastpath *fp = &bp->fp[i];
1101 if (!fp->rx_cons_sb)
1104 start = RX_BD(le16_to_cpu(*fp->rx_cons_sb) - 10);
1105 end = RX_BD(le16_to_cpu(*fp->rx_cons_sb) + 503);
1106 for (j = start; j != end; j = RX_BD(j + 1)) {
1107 u32 *rx_bd = (u32 *)&fp->rx_desc_ring[j];
1108 struct sw_rx_bd *sw_bd = &fp->rx_buf_ring[j];
1110 BNX2X_ERR("fp%d: rx_bd[%x]=[%x:%x] sw_bd=[%p]\n",
1111 i, j, rx_bd[1], rx_bd[0], sw_bd->data);
1114 start = RX_SGE(fp->rx_sge_prod);
1115 end = RX_SGE(fp->last_max_sge);
1116 for (j = start; j != end; j = RX_SGE(j + 1)) {
1117 u32 *rx_sge = (u32 *)&fp->rx_sge_ring[j];
1118 struct sw_rx_page *sw_page = &fp->rx_page_ring[j];
1120 BNX2X_ERR("fp%d: rx_sge[%x]=[%x:%x] sw_page=[%p]\n",
1121 i, j, rx_sge[1], rx_sge[0], sw_page->page);
1124 start = RCQ_BD(fp->rx_comp_cons - 10);
1125 end = RCQ_BD(fp->rx_comp_cons + 503);
1126 for (j = start; j != end; j = RCQ_BD(j + 1)) {
1127 u32 *cqe = (u32 *)&fp->rx_comp_ring[j];
1129 BNX2X_ERR("fp%d: cqe[%x]=[%x:%x:%x:%x]\n",
1130 i, j, cqe[0], cqe[1], cqe[2], cqe[3]);
1135 for_each_valid_tx_queue(bp, i) {
1136 struct bnx2x_fastpath *fp = &bp->fp[i];
1141 for_each_cos_in_tx_queue(fp, cos) {
1142 struct bnx2x_fp_txdata *txdata = fp->txdata_ptr[cos];
1144 if (!fp->txdata_ptr[cos])
1147 if (!txdata->tx_cons_sb)
1150 start = TX_BD(le16_to_cpu(*txdata->tx_cons_sb) - 10);
1151 end = TX_BD(le16_to_cpu(*txdata->tx_cons_sb) + 245);
1152 for (j = start; j != end; j = TX_BD(j + 1)) {
1153 struct sw_tx_bd *sw_bd =
1154 &txdata->tx_buf_ring[j];
1156 BNX2X_ERR("fp%d: txdata %d, packet[%x]=[%p,%x]\n",
1157 i, cos, j, sw_bd->skb,
1161 start = TX_BD(txdata->tx_bd_cons - 10);
1162 end = TX_BD(txdata->tx_bd_cons + 254);
1163 for (j = start; j != end; j = TX_BD(j + 1)) {
1164 u32 *tx_bd = (u32 *)&txdata->tx_desc_ring[j];
1166 BNX2X_ERR("fp%d: txdata %d, tx_bd[%x]=[%x:%x:%x:%x]\n",
1167 i, cos, j, tx_bd[0], tx_bd[1],
1168 tx_bd[2], tx_bd[3]);
1175 bnx2x_mc_assert(bp);
1177 BNX2X_ERR("end crash dump -----------------\n");
1181 * FLR Support for E2
1183 * bnx2x_pf_flr_clnup() is called during nic_load in the per function HW
1186 #define FLR_WAIT_USEC 10000 /* 10 milliseconds */
1187 #define FLR_WAIT_INTERVAL 50 /* usec */
1188 #define FLR_POLL_CNT (FLR_WAIT_USEC/FLR_WAIT_INTERVAL) /* 200 */
1190 struct pbf_pN_buf_regs {
1197 struct pbf_pN_cmd_regs {
1203 static void bnx2x_pbf_pN_buf_flushed(struct bnx2x *bp,
1204 struct pbf_pN_buf_regs *regs,
1207 u32 init_crd, crd, crd_start, crd_freed, crd_freed_start;
1208 u32 cur_cnt = poll_count;
1210 crd_freed = crd_freed_start = REG_RD(bp, regs->crd_freed);
1211 crd = crd_start = REG_RD(bp, regs->crd);
1212 init_crd = REG_RD(bp, regs->init_crd);
1214 DP(BNX2X_MSG_SP, "INIT CREDIT[%d] : %x\n", regs->pN, init_crd);
1215 DP(BNX2X_MSG_SP, "CREDIT[%d] : s:%x\n", regs->pN, crd);
1216 DP(BNX2X_MSG_SP, "CREDIT_FREED[%d]: s:%x\n", regs->pN, crd_freed);
1218 while ((crd != init_crd) && ((u32)SUB_S32(crd_freed, crd_freed_start) <
1219 (init_crd - crd_start))) {
1221 udelay(FLR_WAIT_INTERVAL);
1222 crd = REG_RD(bp, regs->crd);
1223 crd_freed = REG_RD(bp, regs->crd_freed);
1225 DP(BNX2X_MSG_SP, "PBF tx buffer[%d] timed out\n",
1227 DP(BNX2X_MSG_SP, "CREDIT[%d] : c:%x\n",
1229 DP(BNX2X_MSG_SP, "CREDIT_FREED[%d]: c:%x\n",
1230 regs->pN, crd_freed);
1234 DP(BNX2X_MSG_SP, "Waited %d*%d usec for PBF tx buffer[%d]\n",
1235 poll_count-cur_cnt, FLR_WAIT_INTERVAL, regs->pN);
1238 static void bnx2x_pbf_pN_cmd_flushed(struct bnx2x *bp,
1239 struct pbf_pN_cmd_regs *regs,
1242 u32 occup, to_free, freed, freed_start;
1243 u32 cur_cnt = poll_count;
1245 occup = to_free = REG_RD(bp, regs->lines_occup);
1246 freed = freed_start = REG_RD(bp, regs->lines_freed);
1248 DP(BNX2X_MSG_SP, "OCCUPANCY[%d] : s:%x\n", regs->pN, occup);
1249 DP(BNX2X_MSG_SP, "LINES_FREED[%d] : s:%x\n", regs->pN, freed);
1251 while (occup && ((u32)SUB_S32(freed, freed_start) < to_free)) {
1253 udelay(FLR_WAIT_INTERVAL);
1254 occup = REG_RD(bp, regs->lines_occup);
1255 freed = REG_RD(bp, regs->lines_freed);
1257 DP(BNX2X_MSG_SP, "PBF cmd queue[%d] timed out\n",
1259 DP(BNX2X_MSG_SP, "OCCUPANCY[%d] : s:%x\n",
1261 DP(BNX2X_MSG_SP, "LINES_FREED[%d] : s:%x\n",
1266 DP(BNX2X_MSG_SP, "Waited %d*%d usec for PBF cmd queue[%d]\n",
1267 poll_count-cur_cnt, FLR_WAIT_INTERVAL, regs->pN);
1270 static u32 bnx2x_flr_clnup_reg_poll(struct bnx2x *bp, u32 reg,
1271 u32 expected, u32 poll_count)
1273 u32 cur_cnt = poll_count;
1276 while ((val = REG_RD(bp, reg)) != expected && cur_cnt--)
1277 udelay(FLR_WAIT_INTERVAL);
1282 int bnx2x_flr_clnup_poll_hw_counter(struct bnx2x *bp, u32 reg,
1283 char *msg, u32 poll_cnt)
1285 u32 val = bnx2x_flr_clnup_reg_poll(bp, reg, 0, poll_cnt);
1287 BNX2X_ERR("%s usage count=%d\n", msg, val);
1293 /* Common routines with VF FLR cleanup */
1294 u32 bnx2x_flr_clnup_poll_count(struct bnx2x *bp)
1296 /* adjust polling timeout */
1297 if (CHIP_REV_IS_EMUL(bp))
1298 return FLR_POLL_CNT * 2000;
1300 if (CHIP_REV_IS_FPGA(bp))
1301 return FLR_POLL_CNT * 120;
1303 return FLR_POLL_CNT;
1306 void bnx2x_tx_hw_flushed(struct bnx2x *bp, u32 poll_count)
1308 struct pbf_pN_cmd_regs cmd_regs[] = {
1309 {0, (CHIP_IS_E3B0(bp)) ?
1310 PBF_REG_TQ_OCCUPANCY_Q0 :
1311 PBF_REG_P0_TQ_OCCUPANCY,
1312 (CHIP_IS_E3B0(bp)) ?
1313 PBF_REG_TQ_LINES_FREED_CNT_Q0 :
1314 PBF_REG_P0_TQ_LINES_FREED_CNT},
1315 {1, (CHIP_IS_E3B0(bp)) ?
1316 PBF_REG_TQ_OCCUPANCY_Q1 :
1317 PBF_REG_P1_TQ_OCCUPANCY,
1318 (CHIP_IS_E3B0(bp)) ?
1319 PBF_REG_TQ_LINES_FREED_CNT_Q1 :
1320 PBF_REG_P1_TQ_LINES_FREED_CNT},
1321 {4, (CHIP_IS_E3B0(bp)) ?
1322 PBF_REG_TQ_OCCUPANCY_LB_Q :
1323 PBF_REG_P4_TQ_OCCUPANCY,
1324 (CHIP_IS_E3B0(bp)) ?
1325 PBF_REG_TQ_LINES_FREED_CNT_LB_Q :
1326 PBF_REG_P4_TQ_LINES_FREED_CNT}
1329 struct pbf_pN_buf_regs buf_regs[] = {
1330 {0, (CHIP_IS_E3B0(bp)) ?
1331 PBF_REG_INIT_CRD_Q0 :
1332 PBF_REG_P0_INIT_CRD ,
1333 (CHIP_IS_E3B0(bp)) ?
1336 (CHIP_IS_E3B0(bp)) ?
1337 PBF_REG_INTERNAL_CRD_FREED_CNT_Q0 :
1338 PBF_REG_P0_INTERNAL_CRD_FREED_CNT},
1339 {1, (CHIP_IS_E3B0(bp)) ?
1340 PBF_REG_INIT_CRD_Q1 :
1341 PBF_REG_P1_INIT_CRD,
1342 (CHIP_IS_E3B0(bp)) ?
1345 (CHIP_IS_E3B0(bp)) ?
1346 PBF_REG_INTERNAL_CRD_FREED_CNT_Q1 :
1347 PBF_REG_P1_INTERNAL_CRD_FREED_CNT},
1348 {4, (CHIP_IS_E3B0(bp)) ?
1349 PBF_REG_INIT_CRD_LB_Q :
1350 PBF_REG_P4_INIT_CRD,
1351 (CHIP_IS_E3B0(bp)) ?
1352 PBF_REG_CREDIT_LB_Q :
1354 (CHIP_IS_E3B0(bp)) ?
1355 PBF_REG_INTERNAL_CRD_FREED_CNT_LB_Q :
1356 PBF_REG_P4_INTERNAL_CRD_FREED_CNT},
1361 /* Verify the command queues are flushed P0, P1, P4 */
1362 for (i = 0; i < ARRAY_SIZE(cmd_regs); i++)
1363 bnx2x_pbf_pN_cmd_flushed(bp, &cmd_regs[i], poll_count);
1365 /* Verify the transmission buffers are flushed P0, P1, P4 */
1366 for (i = 0; i < ARRAY_SIZE(buf_regs); i++)
1367 bnx2x_pbf_pN_buf_flushed(bp, &buf_regs[i], poll_count);
1370 #define OP_GEN_PARAM(param) \
1371 (((param) << SDM_OP_GEN_COMP_PARAM_SHIFT) & SDM_OP_GEN_COMP_PARAM)
1373 #define OP_GEN_TYPE(type) \
1374 (((type) << SDM_OP_GEN_COMP_TYPE_SHIFT) & SDM_OP_GEN_COMP_TYPE)
1376 #define OP_GEN_AGG_VECT(index) \
1377 (((index) << SDM_OP_GEN_AGG_VECT_IDX_SHIFT) & SDM_OP_GEN_AGG_VECT_IDX)
1379 int bnx2x_send_final_clnup(struct bnx2x *bp, u8 clnup_func, u32 poll_cnt)
1381 u32 op_gen_command = 0;
1382 u32 comp_addr = BAR_CSTRORM_INTMEM +
1383 CSTORM_FINAL_CLEANUP_COMPLETE_OFFSET(clnup_func);
1386 if (REG_RD(bp, comp_addr)) {
1387 BNX2X_ERR("Cleanup complete was not 0 before sending\n");
1391 op_gen_command |= OP_GEN_PARAM(XSTORM_AGG_INT_FINAL_CLEANUP_INDEX);
1392 op_gen_command |= OP_GEN_TYPE(XSTORM_AGG_INT_FINAL_CLEANUP_COMP_TYPE);
1393 op_gen_command |= OP_GEN_AGG_VECT(clnup_func);
1394 op_gen_command |= 1 << SDM_OP_GEN_AGG_VECT_IDX_VALID_SHIFT;
1396 DP(BNX2X_MSG_SP, "sending FW Final cleanup\n");
1397 REG_WR(bp, XSDM_REG_OPERATION_GEN, op_gen_command);
1399 if (bnx2x_flr_clnup_reg_poll(bp, comp_addr, 1, poll_cnt) != 1) {
1400 BNX2X_ERR("FW final cleanup did not succeed\n");
1401 DP(BNX2X_MSG_SP, "At timeout completion address contained %x\n",
1402 (REG_RD(bp, comp_addr)));
1406 /* Zero completion for next FLR */
1407 REG_WR(bp, comp_addr, 0);
1412 u8 bnx2x_is_pcie_pending(struct pci_dev *dev)
1416 pcie_capability_read_word(dev, PCI_EXP_DEVSTA, &status);
1417 return status & PCI_EXP_DEVSTA_TRPND;
1420 /* PF FLR specific routines
1422 static int bnx2x_poll_hw_usage_counters(struct bnx2x *bp, u32 poll_cnt)
1424 /* wait for CFC PF usage-counter to zero (includes all the VFs) */
1425 if (bnx2x_flr_clnup_poll_hw_counter(bp,
1426 CFC_REG_NUM_LCIDS_INSIDE_PF,
1427 "CFC PF usage counter timed out",
1431 /* Wait for DQ PF usage-counter to zero (until DQ cleanup) */
1432 if (bnx2x_flr_clnup_poll_hw_counter(bp,
1433 DORQ_REG_PF_USAGE_CNT,
1434 "DQ PF usage counter timed out",
1438 /* Wait for QM PF usage-counter to zero (until DQ cleanup) */
1439 if (bnx2x_flr_clnup_poll_hw_counter(bp,
1440 QM_REG_PF_USG_CNT_0 + 4*BP_FUNC(bp),
1441 "QM PF usage counter timed out",
1445 /* Wait for Timer PF usage-counters to zero (until DQ cleanup) */
1446 if (bnx2x_flr_clnup_poll_hw_counter(bp,
1447 TM_REG_LIN0_VNIC_UC + 4*BP_PORT(bp),
1448 "Timers VNIC usage counter timed out",
1451 if (bnx2x_flr_clnup_poll_hw_counter(bp,
1452 TM_REG_LIN0_NUM_SCANS + 4*BP_PORT(bp),
1453 "Timers NUM_SCANS usage counter timed out",
1457 /* Wait DMAE PF usage counter to zero */
1458 if (bnx2x_flr_clnup_poll_hw_counter(bp,
1459 dmae_reg_go_c[INIT_DMAE_C(bp)],
1460 "DMAE command register timed out",
1467 static void bnx2x_hw_enable_status(struct bnx2x *bp)
1471 val = REG_RD(bp, CFC_REG_WEAK_ENABLE_PF);
1472 DP(BNX2X_MSG_SP, "CFC_REG_WEAK_ENABLE_PF is 0x%x\n", val);
1474 val = REG_RD(bp, PBF_REG_DISABLE_PF);
1475 DP(BNX2X_MSG_SP, "PBF_REG_DISABLE_PF is 0x%x\n", val);
1477 val = REG_RD(bp, IGU_REG_PCI_PF_MSI_EN);
1478 DP(BNX2X_MSG_SP, "IGU_REG_PCI_PF_MSI_EN is 0x%x\n", val);
1480 val = REG_RD(bp, IGU_REG_PCI_PF_MSIX_EN);
1481 DP(BNX2X_MSG_SP, "IGU_REG_PCI_PF_MSIX_EN is 0x%x\n", val);
1483 val = REG_RD(bp, IGU_REG_PCI_PF_MSIX_FUNC_MASK);
1484 DP(BNX2X_MSG_SP, "IGU_REG_PCI_PF_MSIX_FUNC_MASK is 0x%x\n", val);
1486 val = REG_RD(bp, PGLUE_B_REG_SHADOW_BME_PF_7_0_CLR);
1487 DP(BNX2X_MSG_SP, "PGLUE_B_REG_SHADOW_BME_PF_7_0_CLR is 0x%x\n", val);
1489 val = REG_RD(bp, PGLUE_B_REG_FLR_REQUEST_PF_7_0_CLR);
1490 DP(BNX2X_MSG_SP, "PGLUE_B_REG_FLR_REQUEST_PF_7_0_CLR is 0x%x\n", val);
1492 val = REG_RD(bp, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER);
1493 DP(BNX2X_MSG_SP, "PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER is 0x%x\n",
1497 static int bnx2x_pf_flr_clnup(struct bnx2x *bp)
1499 u32 poll_cnt = bnx2x_flr_clnup_poll_count(bp);
1501 DP(BNX2X_MSG_SP, "Cleanup after FLR PF[%d]\n", BP_ABS_FUNC(bp));
1503 /* Re-enable PF target read access */
1504 REG_WR(bp, PGLUE_B_REG_INTERNAL_PFID_ENABLE_TARGET_READ, 1);
1506 /* Poll HW usage counters */
1507 DP(BNX2X_MSG_SP, "Polling usage counters\n");
1508 if (bnx2x_poll_hw_usage_counters(bp, poll_cnt))
1511 /* Zero the igu 'trailing edge' and 'leading edge' */
1513 /* Send the FW cleanup command */
1514 if (bnx2x_send_final_clnup(bp, (u8)BP_FUNC(bp), poll_cnt))
1519 /* Verify TX hw is flushed */
1520 bnx2x_tx_hw_flushed(bp, poll_cnt);
1522 /* Wait 100ms (not adjusted according to platform) */
1525 /* Verify no pending pci transactions */
1526 if (bnx2x_is_pcie_pending(bp->pdev))
1527 BNX2X_ERR("PCIE Transactions still pending\n");
1530 bnx2x_hw_enable_status(bp);
1533 * Master enable - Due to WB DMAE writes performed before this
1534 * register is re-initialized as part of the regular function init
1536 REG_WR(bp, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, 1);
1541 static void bnx2x_hc_int_enable(struct bnx2x *bp)
1543 int port = BP_PORT(bp);
1544 u32 addr = port ? HC_REG_CONFIG_1 : HC_REG_CONFIG_0;
1545 u32 val = REG_RD(bp, addr);
1546 bool msix = (bp->flags & USING_MSIX_FLAG) ? true : false;
1547 bool single_msix = (bp->flags & USING_SINGLE_MSIX_FLAG) ? true : false;
1548 bool msi = (bp->flags & USING_MSI_FLAG) ? true : false;
1551 val &= ~(HC_CONFIG_0_REG_SINGLE_ISR_EN_0 |
1552 HC_CONFIG_0_REG_INT_LINE_EN_0);
1553 val |= (HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0 |
1554 HC_CONFIG_0_REG_ATTN_BIT_EN_0);
1556 val |= HC_CONFIG_0_REG_SINGLE_ISR_EN_0;
1558 val &= ~HC_CONFIG_0_REG_INT_LINE_EN_0;
1559 val |= (HC_CONFIG_0_REG_SINGLE_ISR_EN_0 |
1560 HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0 |
1561 HC_CONFIG_0_REG_ATTN_BIT_EN_0);
1563 val |= (HC_CONFIG_0_REG_SINGLE_ISR_EN_0 |
1564 HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0 |
1565 HC_CONFIG_0_REG_INT_LINE_EN_0 |
1566 HC_CONFIG_0_REG_ATTN_BIT_EN_0);
1568 if (!CHIP_IS_E1(bp)) {
1570 "write %x to HC %d (addr 0x%x)\n", val, port, addr);
1572 REG_WR(bp, addr, val);
1574 val &= ~HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0;
1579 REG_WR(bp, HC_REG_INT_MASK + port*4, 0x1FFFF);
1582 "write %x to HC %d (addr 0x%x) mode %s\n", val, port, addr,
1583 (msix ? "MSI-X" : (msi ? "MSI" : "INTx")));
1585 REG_WR(bp, addr, val);
1587 * Ensure that HC_CONFIG is written before leading/trailing edge config
1592 if (!CHIP_IS_E1(bp)) {
1593 /* init leading/trailing edge */
1595 val = (0xee0f | (1 << (BP_VN(bp) + 4)));
1597 /* enable nig and gpio3 attention */
1602 REG_WR(bp, HC_REG_TRAILING_EDGE_0 + port*8, val);
1603 REG_WR(bp, HC_REG_LEADING_EDGE_0 + port*8, val);
1606 /* Make sure that interrupts are indeed enabled from here on */
1610 static void bnx2x_igu_int_enable(struct bnx2x *bp)
1613 bool msix = (bp->flags & USING_MSIX_FLAG) ? true : false;
1614 bool single_msix = (bp->flags & USING_SINGLE_MSIX_FLAG) ? true : false;
1615 bool msi = (bp->flags & USING_MSI_FLAG) ? true : false;
1617 val = REG_RD(bp, IGU_REG_PF_CONFIGURATION);
1620 val &= ~(IGU_PF_CONF_INT_LINE_EN |
1621 IGU_PF_CONF_SINGLE_ISR_EN);
1622 val |= (IGU_PF_CONF_MSI_MSIX_EN |
1623 IGU_PF_CONF_ATTN_BIT_EN);
1626 val |= IGU_PF_CONF_SINGLE_ISR_EN;
1628 val &= ~IGU_PF_CONF_INT_LINE_EN;
1629 val |= (IGU_PF_CONF_MSI_MSIX_EN |
1630 IGU_PF_CONF_ATTN_BIT_EN |
1631 IGU_PF_CONF_SINGLE_ISR_EN);
1633 val &= ~IGU_PF_CONF_MSI_MSIX_EN;
1634 val |= (IGU_PF_CONF_INT_LINE_EN |
1635 IGU_PF_CONF_ATTN_BIT_EN |
1636 IGU_PF_CONF_SINGLE_ISR_EN);
1639 /* Clean previous status - need to configure igu prior to ack*/
1640 if ((!msix) || single_msix) {
1641 REG_WR(bp, IGU_REG_PF_CONFIGURATION, val);
1645 val |= IGU_PF_CONF_FUNC_EN;
1647 DP(NETIF_MSG_IFUP, "write 0x%x to IGU mode %s\n",
1648 val, (msix ? "MSI-X" : (msi ? "MSI" : "INTx")));
1650 REG_WR(bp, IGU_REG_PF_CONFIGURATION, val);
1652 if (val & IGU_PF_CONF_INT_LINE_EN)
1653 pci_intx(bp->pdev, true);
1657 /* init leading/trailing edge */
1659 val = (0xee0f | (1 << (BP_VN(bp) + 4)));
1661 /* enable nig and gpio3 attention */
1666 REG_WR(bp, IGU_REG_TRAILING_EDGE_LATCH, val);
1667 REG_WR(bp, IGU_REG_LEADING_EDGE_LATCH, val);
1669 /* Make sure that interrupts are indeed enabled from here on */
1673 void bnx2x_int_enable(struct bnx2x *bp)
1675 if (bp->common.int_block == INT_BLOCK_HC)
1676 bnx2x_hc_int_enable(bp);
1678 bnx2x_igu_int_enable(bp);
1681 void bnx2x_int_disable_sync(struct bnx2x *bp, int disable_hw)
1683 int msix = (bp->flags & USING_MSIX_FLAG) ? 1 : 0;
1687 /* prevent the HW from sending interrupts */
1688 bnx2x_int_disable(bp);
1690 /* make sure all ISRs are done */
1692 synchronize_irq(bp->msix_table[0].vector);
1694 if (CNIC_SUPPORT(bp))
1696 for_each_eth_queue(bp, i)
1697 synchronize_irq(bp->msix_table[offset++].vector);
1699 synchronize_irq(bp->pdev->irq);
1701 /* make sure sp_task is not running */
1702 cancel_delayed_work(&bp->sp_task);
1703 cancel_delayed_work(&bp->period_task);
1704 flush_workqueue(bnx2x_wq);
1710 * General service functions
1713 /* Return true if succeeded to acquire the lock */
1714 static bool bnx2x_trylock_hw_lock(struct bnx2x *bp, u32 resource)
1717 u32 resource_bit = (1 << resource);
1718 int func = BP_FUNC(bp);
1719 u32 hw_lock_control_reg;
1721 DP(NETIF_MSG_HW | NETIF_MSG_IFUP,
1722 "Trying to take a lock on resource %d\n", resource);
1724 /* Validating that the resource is within range */
1725 if (resource > HW_LOCK_MAX_RESOURCE_VALUE) {
1726 DP(NETIF_MSG_HW | NETIF_MSG_IFUP,
1727 "resource(0x%x) > HW_LOCK_MAX_RESOURCE_VALUE(0x%x)\n",
1728 resource, HW_LOCK_MAX_RESOURCE_VALUE);
1733 hw_lock_control_reg = (MISC_REG_DRIVER_CONTROL_1 + func*8);
1735 hw_lock_control_reg =
1736 (MISC_REG_DRIVER_CONTROL_7 + (func - 6)*8);
1738 /* Try to acquire the lock */
1739 REG_WR(bp, hw_lock_control_reg + 4, resource_bit);
1740 lock_status = REG_RD(bp, hw_lock_control_reg);
1741 if (lock_status & resource_bit)
1744 DP(NETIF_MSG_HW | NETIF_MSG_IFUP,
1745 "Failed to get a lock on resource %d\n", resource);
1750 * bnx2x_get_leader_lock_resource - get the recovery leader resource id
1752 * @bp: driver handle
1754 * Returns the recovery leader resource id according to the engine this function
1755 * belongs to. Currently only only 2 engines is supported.
1757 static int bnx2x_get_leader_lock_resource(struct bnx2x *bp)
1760 return HW_LOCK_RESOURCE_RECOVERY_LEADER_1;
1762 return HW_LOCK_RESOURCE_RECOVERY_LEADER_0;
1766 * bnx2x_trylock_leader_lock- try to acquire a leader lock.
1768 * @bp: driver handle
1770 * Tries to acquire a leader lock for current engine.
1772 static bool bnx2x_trylock_leader_lock(struct bnx2x *bp)
1774 return bnx2x_trylock_hw_lock(bp, bnx2x_get_leader_lock_resource(bp));
1777 static void bnx2x_cnic_cfc_comp(struct bnx2x *bp, int cid, u8 err);
1779 /* schedule the sp task and mark that interrupt occurred (runs from ISR) */
1780 static int bnx2x_schedule_sp_task(struct bnx2x *bp)
1782 /* Set the interrupt occurred bit for the sp-task to recognize it
1783 * must ack the interrupt and transition according to the IGU
1786 atomic_set(&bp->interrupt_occurred, 1);
1788 /* The sp_task must execute only after this bit
1789 * is set, otherwise we will get out of sync and miss all
1790 * further interrupts. Hence, the barrier.
1794 /* schedule sp_task to workqueue */
1795 return queue_delayed_work(bnx2x_wq, &bp->sp_task, 0);
1798 void bnx2x_sp_event(struct bnx2x_fastpath *fp, union eth_rx_cqe *rr_cqe)
1800 struct bnx2x *bp = fp->bp;
1801 int cid = SW_CID(rr_cqe->ramrod_cqe.conn_and_cmd_data);
1802 int command = CQE_CMD(rr_cqe->ramrod_cqe.conn_and_cmd_data);
1803 enum bnx2x_queue_cmd drv_cmd = BNX2X_Q_CMD_MAX;
1804 struct bnx2x_queue_sp_obj *q_obj = &bnx2x_sp_obj(bp, fp).q_obj;
1807 "fp %d cid %d got ramrod #%d state is %x type is %d\n",
1808 fp->index, cid, command, bp->state,
1809 rr_cqe->ramrod_cqe.ramrod_type);
1811 /* If cid is within VF range, replace the slowpath object with the
1812 * one corresponding to this VF
1814 if (cid >= BNX2X_FIRST_VF_CID &&
1815 cid < BNX2X_FIRST_VF_CID + BNX2X_VF_CIDS)
1816 bnx2x_iov_set_queue_sp_obj(bp, cid, &q_obj);
1819 case (RAMROD_CMD_ID_ETH_CLIENT_UPDATE):
1820 DP(BNX2X_MSG_SP, "got UPDATE ramrod. CID %d\n", cid);
1821 drv_cmd = BNX2X_Q_CMD_UPDATE;
1824 case (RAMROD_CMD_ID_ETH_CLIENT_SETUP):
1825 DP(BNX2X_MSG_SP, "got MULTI[%d] setup ramrod\n", cid);
1826 drv_cmd = BNX2X_Q_CMD_SETUP;
1829 case (RAMROD_CMD_ID_ETH_TX_QUEUE_SETUP):
1830 DP(BNX2X_MSG_SP, "got MULTI[%d] tx-only setup ramrod\n", cid);
1831 drv_cmd = BNX2X_Q_CMD_SETUP_TX_ONLY;
1834 case (RAMROD_CMD_ID_ETH_HALT):
1835 DP(BNX2X_MSG_SP, "got MULTI[%d] halt ramrod\n", cid);
1836 drv_cmd = BNX2X_Q_CMD_HALT;
1839 case (RAMROD_CMD_ID_ETH_TERMINATE):
1840 DP(BNX2X_MSG_SP, "got MULTI[%d] terminate ramrod\n", cid);
1841 drv_cmd = BNX2X_Q_CMD_TERMINATE;
1844 case (RAMROD_CMD_ID_ETH_EMPTY):
1845 DP(BNX2X_MSG_SP, "got MULTI[%d] empty ramrod\n", cid);
1846 drv_cmd = BNX2X_Q_CMD_EMPTY;
1849 case (RAMROD_CMD_ID_ETH_TPA_UPDATE):
1850 DP(BNX2X_MSG_SP, "got tpa update ramrod CID=%d\n", cid);
1851 drv_cmd = BNX2X_Q_CMD_UPDATE_TPA;
1855 BNX2X_ERR("unexpected MC reply (%d) on fp[%d]\n",
1856 command, fp->index);
1860 if ((drv_cmd != BNX2X_Q_CMD_MAX) &&
1861 q_obj->complete_cmd(bp, q_obj, drv_cmd))
1862 /* q_obj->complete_cmd() failure means that this was
1863 * an unexpected completion.
1865 * In this case we don't want to increase the bp->spq_left
1866 * because apparently we haven't sent this command the first
1869 #ifdef BNX2X_STOP_ON_ERROR
1875 smp_mb__before_atomic();
1876 atomic_inc(&bp->cq_spq_left);
1877 /* push the change in bp->spq_left and towards the memory */
1878 smp_mb__after_atomic();
1880 DP(BNX2X_MSG_SP, "bp->cq_spq_left %x\n", atomic_read(&bp->cq_spq_left));
1882 if ((drv_cmd == BNX2X_Q_CMD_UPDATE) && (IS_FCOE_FP(fp)) &&
1883 (!!test_bit(BNX2X_AFEX_FCOE_Q_UPDATE_PENDING, &bp->sp_state))) {
1884 /* if Q update ramrod is completed for last Q in AFEX vif set
1885 * flow, then ACK MCP at the end
1887 * mark pending ACK to MCP bit.
1888 * prevent case that both bits are cleared.
1889 * At the end of load/unload driver checks that
1890 * sp_state is cleared, and this order prevents
1893 smp_mb__before_atomic();
1894 set_bit(BNX2X_AFEX_PENDING_VIFSET_MCP_ACK, &bp->sp_state);
1896 clear_bit(BNX2X_AFEX_FCOE_Q_UPDATE_PENDING, &bp->sp_state);
1897 smp_mb__after_atomic();
1899 /* schedule the sp task as mcp ack is required */
1900 bnx2x_schedule_sp_task(bp);
1906 irqreturn_t bnx2x_interrupt(int irq, void *dev_instance)
1908 struct bnx2x *bp = netdev_priv(dev_instance);
1909 u16 status = bnx2x_ack_int(bp);
1914 /* Return here if interrupt is shared and it's not for us */
1915 if (unlikely(status == 0)) {
1916 DP(NETIF_MSG_INTR, "not our interrupt!\n");
1919 DP(NETIF_MSG_INTR, "got an interrupt status 0x%x\n", status);
1921 #ifdef BNX2X_STOP_ON_ERROR
1922 if (unlikely(bp->panic))
1926 for_each_eth_queue(bp, i) {
1927 struct bnx2x_fastpath *fp = &bp->fp[i];
1929 mask = 0x2 << (fp->index + CNIC_SUPPORT(bp));
1930 if (status & mask) {
1931 /* Handle Rx or Tx according to SB id */
1932 for_each_cos_in_tx_queue(fp, cos)
1933 prefetch(fp->txdata_ptr[cos]->tx_cons_sb);
1934 prefetch(&fp->sb_running_index[SM_RX_ID]);
1935 napi_schedule_irqoff(&bnx2x_fp(bp, fp->index, napi));
1940 if (CNIC_SUPPORT(bp)) {
1942 if (status & (mask | 0x1)) {
1943 struct cnic_ops *c_ops = NULL;
1946 c_ops = rcu_dereference(bp->cnic_ops);
1947 if (c_ops && (bp->cnic_eth_dev.drv_state &
1948 CNIC_DRV_STATE_HANDLES_IRQ))
1949 c_ops->cnic_handler(bp->cnic_data, NULL);
1956 if (unlikely(status & 0x1)) {
1958 /* schedule sp task to perform default status block work, ack
1959 * attentions and enable interrupts.
1961 bnx2x_schedule_sp_task(bp);
1968 if (unlikely(status))
1969 DP(NETIF_MSG_INTR, "got an unknown interrupt! (status 0x%x)\n",
1978 * General service functions
1981 int bnx2x_acquire_hw_lock(struct bnx2x *bp, u32 resource)
1984 u32 resource_bit = (1 << resource);
1985 int func = BP_FUNC(bp);
1986 u32 hw_lock_control_reg;
1989 /* Validating that the resource is within range */
1990 if (resource > HW_LOCK_MAX_RESOURCE_VALUE) {
1991 BNX2X_ERR("resource(0x%x) > HW_LOCK_MAX_RESOURCE_VALUE(0x%x)\n",
1992 resource, HW_LOCK_MAX_RESOURCE_VALUE);
1997 hw_lock_control_reg = (MISC_REG_DRIVER_CONTROL_1 + func*8);
1999 hw_lock_control_reg =
2000 (MISC_REG_DRIVER_CONTROL_7 + (func - 6)*8);
2003 /* Validating that the resource is not already taken */
2004 lock_status = REG_RD(bp, hw_lock_control_reg);
2005 if (lock_status & resource_bit) {
2006 BNX2X_ERR("lock_status 0x%x resource_bit 0x%x\n",
2007 lock_status, resource_bit);
2011 /* Try for 5 second every 5ms */
2012 for (cnt = 0; cnt < 1000; cnt++) {
2013 /* Try to acquire the lock */
2014 REG_WR(bp, hw_lock_control_reg + 4, resource_bit);
2015 lock_status = REG_RD(bp, hw_lock_control_reg);
2016 if (lock_status & resource_bit)
2019 usleep_range(5000, 10000);
2021 BNX2X_ERR("Timeout\n");
2025 int bnx2x_release_leader_lock(struct bnx2x *bp)
2027 return bnx2x_release_hw_lock(bp, bnx2x_get_leader_lock_resource(bp));
2030 int bnx2x_release_hw_lock(struct bnx2x *bp, u32 resource)
2033 u32 resource_bit = (1 << resource);
2034 int func = BP_FUNC(bp);
2035 u32 hw_lock_control_reg;
2037 /* Validating that the resource is within range */
2038 if (resource > HW_LOCK_MAX_RESOURCE_VALUE) {
2039 BNX2X_ERR("resource(0x%x) > HW_LOCK_MAX_RESOURCE_VALUE(0x%x)\n",
2040 resource, HW_LOCK_MAX_RESOURCE_VALUE);
2045 hw_lock_control_reg = (MISC_REG_DRIVER_CONTROL_1 + func*8);
2047 hw_lock_control_reg =
2048 (MISC_REG_DRIVER_CONTROL_7 + (func - 6)*8);
2051 /* Validating that the resource is currently taken */
2052 lock_status = REG_RD(bp, hw_lock_control_reg);
2053 if (!(lock_status & resource_bit)) {
2054 BNX2X_ERR("lock_status 0x%x resource_bit 0x%x. Unlock was called but lock wasn't taken!\n",
2055 lock_status, resource_bit);
2059 REG_WR(bp, hw_lock_control_reg, resource_bit);
2063 int bnx2x_get_gpio(struct bnx2x *bp, int gpio_num, u8 port)
2065 /* The GPIO should be swapped if swap register is set and active */
2066 int gpio_port = (REG_RD(bp, NIG_REG_PORT_SWAP) &&
2067 REG_RD(bp, NIG_REG_STRAP_OVERRIDE)) ^ port;
2068 int gpio_shift = gpio_num +
2069 (gpio_port ? MISC_REGISTERS_GPIO_PORT_SHIFT : 0);
2070 u32 gpio_mask = (1 << gpio_shift);
2074 if (gpio_num > MISC_REGISTERS_GPIO_3) {
2075 BNX2X_ERR("Invalid GPIO %d\n", gpio_num);
2079 /* read GPIO value */
2080 gpio_reg = REG_RD(bp, MISC_REG_GPIO);
2082 /* get the requested pin value */
2083 if ((gpio_reg & gpio_mask) == gpio_mask)
2091 int bnx2x_set_gpio(struct bnx2x *bp, int gpio_num, u32 mode, u8 port)
2093 /* The GPIO should be swapped if swap register is set and active */
2094 int gpio_port = (REG_RD(bp, NIG_REG_PORT_SWAP) &&
2095 REG_RD(bp, NIG_REG_STRAP_OVERRIDE)) ^ port;
2096 int gpio_shift = gpio_num +
2097 (gpio_port ? MISC_REGISTERS_GPIO_PORT_SHIFT : 0);
2098 u32 gpio_mask = (1 << gpio_shift);
2101 if (gpio_num > MISC_REGISTERS_GPIO_3) {
2102 BNX2X_ERR("Invalid GPIO %d\n", gpio_num);
2106 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_GPIO);
2107 /* read GPIO and mask except the float bits */
2108 gpio_reg = (REG_RD(bp, MISC_REG_GPIO) & MISC_REGISTERS_GPIO_FLOAT);
2111 case MISC_REGISTERS_GPIO_OUTPUT_LOW:
2113 "Set GPIO %d (shift %d) -> output low\n",
2114 gpio_num, gpio_shift);
2115 /* clear FLOAT and set CLR */
2116 gpio_reg &= ~(gpio_mask << MISC_REGISTERS_GPIO_FLOAT_POS);
2117 gpio_reg |= (gpio_mask << MISC_REGISTERS_GPIO_CLR_POS);
2120 case MISC_REGISTERS_GPIO_OUTPUT_HIGH:
2122 "Set GPIO %d (shift %d) -> output high\n",
2123 gpio_num, gpio_shift);
2124 /* clear FLOAT and set SET */
2125 gpio_reg &= ~(gpio_mask << MISC_REGISTERS_GPIO_FLOAT_POS);
2126 gpio_reg |= (gpio_mask << MISC_REGISTERS_GPIO_SET_POS);
2129 case MISC_REGISTERS_GPIO_INPUT_HI_Z:
2131 "Set GPIO %d (shift %d) -> input\n",
2132 gpio_num, gpio_shift);
2134 gpio_reg |= (gpio_mask << MISC_REGISTERS_GPIO_FLOAT_POS);
2141 REG_WR(bp, MISC_REG_GPIO, gpio_reg);
2142 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_GPIO);
2147 int bnx2x_set_mult_gpio(struct bnx2x *bp, u8 pins, u32 mode)
2152 /* Any port swapping should be handled by caller. */
2154 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_GPIO);
2155 /* read GPIO and mask except the float bits */
2156 gpio_reg = REG_RD(bp, MISC_REG_GPIO);
2157 gpio_reg &= ~(pins << MISC_REGISTERS_GPIO_FLOAT_POS);
2158 gpio_reg &= ~(pins << MISC_REGISTERS_GPIO_CLR_POS);
2159 gpio_reg &= ~(pins << MISC_REGISTERS_GPIO_SET_POS);
2162 case MISC_REGISTERS_GPIO_OUTPUT_LOW:
2163 DP(NETIF_MSG_LINK, "Set GPIO 0x%x -> output low\n", pins);
2165 gpio_reg |= (pins << MISC_REGISTERS_GPIO_CLR_POS);
2168 case MISC_REGISTERS_GPIO_OUTPUT_HIGH:
2169 DP(NETIF_MSG_LINK, "Set GPIO 0x%x -> output high\n", pins);
2171 gpio_reg |= (pins << MISC_REGISTERS_GPIO_SET_POS);
2174 case MISC_REGISTERS_GPIO_INPUT_HI_Z:
2175 DP(NETIF_MSG_LINK, "Set GPIO 0x%x -> input\n", pins);
2177 gpio_reg |= (pins << MISC_REGISTERS_GPIO_FLOAT_POS);
2181 BNX2X_ERR("Invalid GPIO mode assignment %d\n", mode);
2187 REG_WR(bp, MISC_REG_GPIO, gpio_reg);
2189 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_GPIO);
2194 int bnx2x_set_gpio_int(struct bnx2x *bp, int gpio_num, u32 mode, u8 port)
2196 /* The GPIO should be swapped if swap register is set and active */
2197 int gpio_port = (REG_RD(bp, NIG_REG_PORT_SWAP) &&
2198 REG_RD(bp, NIG_REG_STRAP_OVERRIDE)) ^ port;
2199 int gpio_shift = gpio_num +
2200 (gpio_port ? MISC_REGISTERS_GPIO_PORT_SHIFT : 0);
2201 u32 gpio_mask = (1 << gpio_shift);
2204 if (gpio_num > MISC_REGISTERS_GPIO_3) {
2205 BNX2X_ERR("Invalid GPIO %d\n", gpio_num);
2209 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_GPIO);
2211 gpio_reg = REG_RD(bp, MISC_REG_GPIO_INT);
2214 case MISC_REGISTERS_GPIO_INT_OUTPUT_CLR:
2216 "Clear GPIO INT %d (shift %d) -> output low\n",
2217 gpio_num, gpio_shift);
2218 /* clear SET and set CLR */
2219 gpio_reg &= ~(gpio_mask << MISC_REGISTERS_GPIO_INT_SET_POS);
2220 gpio_reg |= (gpio_mask << MISC_REGISTERS_GPIO_INT_CLR_POS);
2223 case MISC_REGISTERS_GPIO_INT_OUTPUT_SET:
2225 "Set GPIO INT %d (shift %d) -> output high\n",
2226 gpio_num, gpio_shift);
2227 /* clear CLR and set SET */
2228 gpio_reg &= ~(gpio_mask << MISC_REGISTERS_GPIO_INT_CLR_POS);
2229 gpio_reg |= (gpio_mask << MISC_REGISTERS_GPIO_INT_SET_POS);
2236 REG_WR(bp, MISC_REG_GPIO_INT, gpio_reg);
2237 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_GPIO);
2242 static int bnx2x_set_spio(struct bnx2x *bp, int spio, u32 mode)
2246 /* Only 2 SPIOs are configurable */
2247 if ((spio != MISC_SPIO_SPIO4) && (spio != MISC_SPIO_SPIO5)) {
2248 BNX2X_ERR("Invalid SPIO 0x%x\n", spio);
2252 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_SPIO);
2253 /* read SPIO and mask except the float bits */
2254 spio_reg = (REG_RD(bp, MISC_REG_SPIO) & MISC_SPIO_FLOAT);
2257 case MISC_SPIO_OUTPUT_LOW:
2258 DP(NETIF_MSG_HW, "Set SPIO 0x%x -> output low\n", spio);
2259 /* clear FLOAT and set CLR */
2260 spio_reg &= ~(spio << MISC_SPIO_FLOAT_POS);
2261 spio_reg |= (spio << MISC_SPIO_CLR_POS);
2264 case MISC_SPIO_OUTPUT_HIGH:
2265 DP(NETIF_MSG_HW, "Set SPIO 0x%x -> output high\n", spio);
2266 /* clear FLOAT and set SET */
2267 spio_reg &= ~(spio << MISC_SPIO_FLOAT_POS);
2268 spio_reg |= (spio << MISC_SPIO_SET_POS);
2271 case MISC_SPIO_INPUT_HI_Z:
2272 DP(NETIF_MSG_HW, "Set SPIO 0x%x -> input\n", spio);
2274 spio_reg |= (spio << MISC_SPIO_FLOAT_POS);
2281 REG_WR(bp, MISC_REG_SPIO, spio_reg);
2282 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_SPIO);
2287 void bnx2x_calc_fc_adv(struct bnx2x *bp)
2289 u8 cfg_idx = bnx2x_get_link_cfg_idx(bp);
2291 bp->port.advertising[cfg_idx] &= ~(ADVERTISED_Asym_Pause |
2293 switch (bp->link_vars.ieee_fc &
2294 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_MASK) {
2295 case MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH:
2296 bp->port.advertising[cfg_idx] |= (ADVERTISED_Asym_Pause |
2300 case MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC:
2301 bp->port.advertising[cfg_idx] |= ADVERTISED_Asym_Pause;
2309 static void bnx2x_set_requested_fc(struct bnx2x *bp)
2311 /* Initialize link parameters structure variables
2312 * It is recommended to turn off RX FC for jumbo frames
2313 * for better performance
2315 if (CHIP_IS_E1x(bp) && (bp->dev->mtu > 5000))
2316 bp->link_params.req_fc_auto_adv = BNX2X_FLOW_CTRL_TX;
2318 bp->link_params.req_fc_auto_adv = BNX2X_FLOW_CTRL_BOTH;
2321 static void bnx2x_init_dropless_fc(struct bnx2x *bp)
2323 u32 pause_enabled = 0;
2325 if (!CHIP_IS_E1(bp) && bp->dropless_fc && bp->link_vars.link_up) {
2326 if (bp->link_vars.flow_ctrl & BNX2X_FLOW_CTRL_TX)
2329 REG_WR(bp, BAR_USTRORM_INTMEM +
2330 USTORM_ETH_PAUSE_ENABLED_OFFSET(BP_PORT(bp)),
2334 DP(NETIF_MSG_IFUP | NETIF_MSG_LINK, "dropless_fc is %s\n",
2335 pause_enabled ? "enabled" : "disabled");
2338 int bnx2x_initial_phy_init(struct bnx2x *bp, int load_mode)
2340 int rc, cfx_idx = bnx2x_get_link_cfg_idx(bp);
2341 u16 req_line_speed = bp->link_params.req_line_speed[cfx_idx];
2343 if (!BP_NOMCP(bp)) {
2344 bnx2x_set_requested_fc(bp);
2345 bnx2x_acquire_phy_lock(bp);
2347 if (load_mode == LOAD_DIAG) {
2348 struct link_params *lp = &bp->link_params;
2349 lp->loopback_mode = LOOPBACK_XGXS;
2350 /* do PHY loopback at 10G speed, if possible */
2351 if (lp->req_line_speed[cfx_idx] < SPEED_10000) {
2352 if (lp->speed_cap_mask[cfx_idx] &
2353 PORT_HW_CFG_SPEED_CAPABILITY_D0_10G)
2354 lp->req_line_speed[cfx_idx] =
2357 lp->req_line_speed[cfx_idx] =
2362 if (load_mode == LOAD_LOOPBACK_EXT) {
2363 struct link_params *lp = &bp->link_params;
2364 lp->loopback_mode = LOOPBACK_EXT;
2367 rc = bnx2x_phy_init(&bp->link_params, &bp->link_vars);
2369 bnx2x_release_phy_lock(bp);
2371 bnx2x_init_dropless_fc(bp);
2373 bnx2x_calc_fc_adv(bp);
2375 if (bp->link_vars.link_up) {
2376 bnx2x_stats_handle(bp, STATS_EVENT_LINK_UP);
2377 bnx2x_link_report(bp);
2379 queue_delayed_work(bnx2x_wq, &bp->period_task, 0);
2380 bp->link_params.req_line_speed[cfx_idx] = req_line_speed;
2383 BNX2X_ERR("Bootcode is missing - can not initialize link\n");
2387 void bnx2x_link_set(struct bnx2x *bp)
2389 if (!BP_NOMCP(bp)) {
2390 bnx2x_acquire_phy_lock(bp);
2391 bnx2x_phy_init(&bp->link_params, &bp->link_vars);
2392 bnx2x_release_phy_lock(bp);
2394 bnx2x_init_dropless_fc(bp);
2396 bnx2x_calc_fc_adv(bp);
2398 BNX2X_ERR("Bootcode is missing - can not set link\n");
2401 static void bnx2x__link_reset(struct bnx2x *bp)
2403 if (!BP_NOMCP(bp)) {
2404 bnx2x_acquire_phy_lock(bp);
2405 bnx2x_lfa_reset(&bp->link_params, &bp->link_vars);
2406 bnx2x_release_phy_lock(bp);
2408 BNX2X_ERR("Bootcode is missing - can not reset link\n");
2411 void bnx2x_force_link_reset(struct bnx2x *bp)
2413 bnx2x_acquire_phy_lock(bp);
2414 bnx2x_link_reset(&bp->link_params, &bp->link_vars, 1);
2415 bnx2x_release_phy_lock(bp);
2418 u8 bnx2x_link_test(struct bnx2x *bp, u8 is_serdes)
2422 if (!BP_NOMCP(bp)) {
2423 bnx2x_acquire_phy_lock(bp);
2424 rc = bnx2x_test_link(&bp->link_params, &bp->link_vars,
2426 bnx2x_release_phy_lock(bp);
2428 BNX2X_ERR("Bootcode is missing - can not test link\n");
2433 /* Calculates the sum of vn_min_rates.
2434 It's needed for further normalizing of the min_rates.
2436 sum of vn_min_rates.
2438 0 - if all the min_rates are 0.
2439 In the later case fairness algorithm should be deactivated.
2440 If not all min_rates are zero then those that are zeroes will be set to 1.
2442 static void bnx2x_calc_vn_min(struct bnx2x *bp,
2443 struct cmng_init_input *input)
2448 for (vn = VN_0; vn < BP_MAX_VN_NUM(bp); vn++) {
2449 u32 vn_cfg = bp->mf_config[vn];
2450 u32 vn_min_rate = ((vn_cfg & FUNC_MF_CFG_MIN_BW_MASK) >>
2451 FUNC_MF_CFG_MIN_BW_SHIFT) * 100;
2453 /* Skip hidden vns */
2454 if (vn_cfg & FUNC_MF_CFG_FUNC_HIDE)
2456 /* If min rate is zero - set it to 1 */
2457 else if (!vn_min_rate)
2458 vn_min_rate = DEF_MIN_RATE;
2462 input->vnic_min_rate[vn] = vn_min_rate;
2465 /* if ETS or all min rates are zeros - disable fairness */
2466 if (BNX2X_IS_ETS_ENABLED(bp)) {
2467 input->flags.cmng_enables &=
2468 ~CMNG_FLAGS_PER_PORT_FAIRNESS_VN;
2469 DP(NETIF_MSG_IFUP, "Fairness will be disabled due to ETS\n");
2470 } else if (all_zero) {
2471 input->flags.cmng_enables &=
2472 ~CMNG_FLAGS_PER_PORT_FAIRNESS_VN;
2474 "All MIN values are zeroes fairness will be disabled\n");
2476 input->flags.cmng_enables |=
2477 CMNG_FLAGS_PER_PORT_FAIRNESS_VN;
2480 static void bnx2x_calc_vn_max(struct bnx2x *bp, int vn,
2481 struct cmng_init_input *input)
2484 u32 vn_cfg = bp->mf_config[vn];
2486 if (vn_cfg & FUNC_MF_CFG_FUNC_HIDE)
2489 u32 maxCfg = bnx2x_extract_max_cfg(bp, vn_cfg);
2492 /* maxCfg in percents of linkspeed */
2493 vn_max_rate = (bp->link_vars.line_speed * maxCfg) / 100;
2494 } else /* SD modes */
2495 /* maxCfg is absolute in 100Mb units */
2496 vn_max_rate = maxCfg * 100;
2499 DP(NETIF_MSG_IFUP, "vn %d: vn_max_rate %d\n", vn, vn_max_rate);
2501 input->vnic_max_rate[vn] = vn_max_rate;
2504 static int bnx2x_get_cmng_fns_mode(struct bnx2x *bp)
2506 if (CHIP_REV_IS_SLOW(bp))
2507 return CMNG_FNS_NONE;
2509 return CMNG_FNS_MINMAX;
2511 return CMNG_FNS_NONE;
2514 void bnx2x_read_mf_cfg(struct bnx2x *bp)
2516 int vn, n = (CHIP_MODE_IS_4_PORT(bp) ? 2 : 1);
2519 return; /* what should be the default value in this case */
2521 /* For 2 port configuration the absolute function number formula
2523 * abs_func = 2 * vn + BP_PORT + BP_PATH
2525 * and there are 4 functions per port
2527 * For 4 port configuration it is
2528 * abs_func = 4 * vn + 2 * BP_PORT + BP_PATH
2530 * and there are 2 functions per port
2532 for (vn = VN_0; vn < BP_MAX_VN_NUM(bp); vn++) {
2533 int /*abs*/func = n * (2 * vn + BP_PORT(bp)) + BP_PATH(bp);
2535 if (func >= E1H_FUNC_MAX)
2539 MF_CFG_RD(bp, func_mf_config[func].config);
2541 if (bp->mf_config[BP_VN(bp)] & FUNC_MF_CFG_FUNC_DISABLED) {
2542 DP(NETIF_MSG_IFUP, "mf_cfg function disabled\n");
2543 bp->flags |= MF_FUNC_DIS;
2545 DP(NETIF_MSG_IFUP, "mf_cfg function enabled\n");
2546 bp->flags &= ~MF_FUNC_DIS;
2550 static void bnx2x_cmng_fns_init(struct bnx2x *bp, u8 read_cfg, u8 cmng_type)
2552 struct cmng_init_input input;
2553 memset(&input, 0, sizeof(struct cmng_init_input));
2555 input.port_rate = bp->link_vars.line_speed;
2557 if (cmng_type == CMNG_FNS_MINMAX && input.port_rate) {
2560 /* read mf conf from shmem */
2562 bnx2x_read_mf_cfg(bp);
2564 /* vn_weight_sum and enable fairness if not 0 */
2565 bnx2x_calc_vn_min(bp, &input);
2567 /* calculate and set min-max rate for each vn */
2569 for (vn = VN_0; vn < BP_MAX_VN_NUM(bp); vn++)
2570 bnx2x_calc_vn_max(bp, vn, &input);
2572 /* always enable rate shaping and fairness */
2573 input.flags.cmng_enables |=
2574 CMNG_FLAGS_PER_PORT_RATE_SHAPING_VN;
2576 bnx2x_init_cmng(&input, &bp->cmng);
2580 /* rate shaping and fairness are disabled */
2582 "rate shaping and fairness are disabled\n");
2585 static void storm_memset_cmng(struct bnx2x *bp,
2586 struct cmng_init *cmng,
2590 size_t size = sizeof(struct cmng_struct_per_port);
2592 u32 addr = BAR_XSTRORM_INTMEM +
2593 XSTORM_CMNG_PER_PORT_VARS_OFFSET(port);
2595 __storm_memset_struct(bp, addr, size, (u32 *)&cmng->port);
2597 for (vn = VN_0; vn < BP_MAX_VN_NUM(bp); vn++) {
2598 int func = func_by_vn(bp, vn);
2600 addr = BAR_XSTRORM_INTMEM +
2601 XSTORM_RATE_SHAPING_PER_VN_VARS_OFFSET(func);
2602 size = sizeof(struct rate_shaping_vars_per_vn);
2603 __storm_memset_struct(bp, addr, size,
2604 (u32 *)&cmng->vnic.vnic_max_rate[vn]);
2606 addr = BAR_XSTRORM_INTMEM +
2607 XSTORM_FAIRNESS_PER_VN_VARS_OFFSET(func);
2608 size = sizeof(struct fairness_vars_per_vn);
2609 __storm_memset_struct(bp, addr, size,
2610 (u32 *)&cmng->vnic.vnic_min_rate[vn]);
2614 /* init cmng mode in HW according to local configuration */
2615 void bnx2x_set_local_cmng(struct bnx2x *bp)
2617 int cmng_fns = bnx2x_get_cmng_fns_mode(bp);
2619 if (cmng_fns != CMNG_FNS_NONE) {
2620 bnx2x_cmng_fns_init(bp, false, cmng_fns);
2621 storm_memset_cmng(bp, &bp->cmng, BP_PORT(bp));
2623 /* rate shaping and fairness are disabled */
2625 "single function mode without fairness\n");
2629 /* This function is called upon link interrupt */
2630 static void bnx2x_link_attn(struct bnx2x *bp)
2632 /* Make sure that we are synced with the current statistics */
2633 bnx2x_stats_handle(bp, STATS_EVENT_STOP);
2635 bnx2x_link_update(&bp->link_params, &bp->link_vars);
2637 bnx2x_init_dropless_fc(bp);
2639 if (bp->link_vars.link_up) {
2641 if (bp->link_vars.mac_type != MAC_TYPE_EMAC) {
2642 struct host_port_stats *pstats;
2644 pstats = bnx2x_sp(bp, port_stats);
2645 /* reset old mac stats */
2646 memset(&(pstats->mac_stx[0]), 0,
2647 sizeof(struct mac_stx));
2649 if (bp->state == BNX2X_STATE_OPEN)
2650 bnx2x_stats_handle(bp, STATS_EVENT_LINK_UP);
2653 if (bp->link_vars.link_up && bp->link_vars.line_speed)
2654 bnx2x_set_local_cmng(bp);
2656 __bnx2x_link_report(bp);
2659 bnx2x_link_sync_notify(bp);
2662 void bnx2x__link_status_update(struct bnx2x *bp)
2664 if (bp->state != BNX2X_STATE_OPEN)
2667 /* read updated dcb configuration */
2669 bnx2x_dcbx_pmf_update(bp);
2670 bnx2x_link_status_update(&bp->link_params, &bp->link_vars);
2671 if (bp->link_vars.link_up)
2672 bnx2x_stats_handle(bp, STATS_EVENT_LINK_UP);
2674 bnx2x_stats_handle(bp, STATS_EVENT_STOP);
2675 /* indicate link status */
2676 bnx2x_link_report(bp);
2679 bp->port.supported[0] |= (SUPPORTED_10baseT_Half |
2680 SUPPORTED_10baseT_Full |
2681 SUPPORTED_100baseT_Half |
2682 SUPPORTED_100baseT_Full |
2683 SUPPORTED_1000baseT_Full |
2684 SUPPORTED_2500baseX_Full |
2685 SUPPORTED_10000baseT_Full |
2690 SUPPORTED_Asym_Pause);
2691 bp->port.advertising[0] = bp->port.supported[0];
2693 bp->link_params.bp = bp;
2694 bp->link_params.port = BP_PORT(bp);
2695 bp->link_params.req_duplex[0] = DUPLEX_FULL;
2696 bp->link_params.req_flow_ctrl[0] = BNX2X_FLOW_CTRL_NONE;
2697 bp->link_params.req_line_speed[0] = SPEED_10000;
2698 bp->link_params.speed_cap_mask[0] = 0x7f0000;
2699 bp->link_params.switch_cfg = SWITCH_CFG_10G;
2700 bp->link_vars.mac_type = MAC_TYPE_BMAC;
2701 bp->link_vars.line_speed = SPEED_10000;
2702 bp->link_vars.link_status =
2703 (LINK_STATUS_LINK_UP |
2704 LINK_STATUS_SPEED_AND_DUPLEX_10GTFD);
2705 bp->link_vars.link_up = 1;
2706 bp->link_vars.duplex = DUPLEX_FULL;
2707 bp->link_vars.flow_ctrl = BNX2X_FLOW_CTRL_NONE;
2708 __bnx2x_link_report(bp);
2710 bnx2x_sample_bulletin(bp);
2712 /* if bulletin board did not have an update for link status
2713 * __bnx2x_link_report will report current status
2714 * but it will NOT duplicate report in case of already reported
2715 * during sampling bulletin board.
2717 bnx2x_stats_handle(bp, STATS_EVENT_LINK_UP);
2721 static int bnx2x_afex_func_update(struct bnx2x *bp, u16 vifid,
2722 u16 vlan_val, u8 allowed_prio)
2724 struct bnx2x_func_state_params func_params = {NULL};
2725 struct bnx2x_func_afex_update_params *f_update_params =
2726 &func_params.params.afex_update;
2728 func_params.f_obj = &bp->func_obj;
2729 func_params.cmd = BNX2X_F_CMD_AFEX_UPDATE;
2731 /* no need to wait for RAMROD completion, so don't
2732 * set RAMROD_COMP_WAIT flag
2735 f_update_params->vif_id = vifid;
2736 f_update_params->afex_default_vlan = vlan_val;
2737 f_update_params->allowed_priorities = allowed_prio;
2739 /* if ramrod can not be sent, response to MCP immediately */
2740 if (bnx2x_func_state_change(bp, &func_params) < 0)
2741 bnx2x_fw_command(bp, DRV_MSG_CODE_AFEX_VIFSET_ACK, 0);
2746 static int bnx2x_afex_handle_vif_list_cmd(struct bnx2x *bp, u8 cmd_type,
2747 u16 vif_index, u8 func_bit_map)
2749 struct bnx2x_func_state_params func_params = {NULL};
2750 struct bnx2x_func_afex_viflists_params *update_params =
2751 &func_params.params.afex_viflists;
2755 /* validate only LIST_SET and LIST_GET are received from switch */
2756 if ((cmd_type != VIF_LIST_RULE_GET) && (cmd_type != VIF_LIST_RULE_SET))
2757 BNX2X_ERR("BUG! afex_handle_vif_list_cmd invalid type 0x%x\n",
2760 func_params.f_obj = &bp->func_obj;
2761 func_params.cmd = BNX2X_F_CMD_AFEX_VIFLISTS;
2763 /* set parameters according to cmd_type */
2764 update_params->afex_vif_list_command = cmd_type;
2765 update_params->vif_list_index = vif_index;
2766 update_params->func_bit_map =
2767 (cmd_type == VIF_LIST_RULE_GET) ? 0 : func_bit_map;
2768 update_params->func_to_clear = 0;
2770 (cmd_type == VIF_LIST_RULE_GET) ?
2771 DRV_MSG_CODE_AFEX_LISTGET_ACK :
2772 DRV_MSG_CODE_AFEX_LISTSET_ACK;
2774 /* if ramrod can not be sent, respond to MCP immediately for
2775 * SET and GET requests (other are not triggered from MCP)
2777 rc = bnx2x_func_state_change(bp, &func_params);
2779 bnx2x_fw_command(bp, drv_msg_code, 0);
2784 static void bnx2x_handle_afex_cmd(struct bnx2x *bp, u32 cmd)
2786 struct afex_stats afex_stats;
2787 u32 func = BP_ABS_FUNC(bp);
2794 u32 addr_to_write, vifid, addrs, stats_type, i;
2796 if (cmd & DRV_STATUS_AFEX_LISTGET_REQ) {
2797 vifid = SHMEM2_RD(bp, afex_param1_to_driver[BP_FW_MB_IDX(bp)]);
2799 "afex: got MCP req LISTGET_REQ for vifid 0x%x\n", vifid);
2800 bnx2x_afex_handle_vif_list_cmd(bp, VIF_LIST_RULE_GET, vifid, 0);
2803 if (cmd & DRV_STATUS_AFEX_LISTSET_REQ) {
2804 vifid = SHMEM2_RD(bp, afex_param1_to_driver[BP_FW_MB_IDX(bp)]);
2805 addrs = SHMEM2_RD(bp, afex_param2_to_driver[BP_FW_MB_IDX(bp)]);
2807 "afex: got MCP req LISTSET_REQ for vifid 0x%x addrs 0x%x\n",
2809 bnx2x_afex_handle_vif_list_cmd(bp, VIF_LIST_RULE_SET, vifid,
2813 if (cmd & DRV_STATUS_AFEX_STATSGET_REQ) {
2814 addr_to_write = SHMEM2_RD(bp,
2815 afex_scratchpad_addr_to_write[BP_FW_MB_IDX(bp)]);
2816 stats_type = SHMEM2_RD(bp,
2817 afex_param1_to_driver[BP_FW_MB_IDX(bp)]);
2820 "afex: got MCP req STATSGET_REQ, write to addr 0x%x\n",
2823 bnx2x_afex_collect_stats(bp, (void *)&afex_stats, stats_type);
2825 /* write response to scratchpad, for MCP */
2826 for (i = 0; i < (sizeof(struct afex_stats)/sizeof(u32)); i++)
2827 REG_WR(bp, addr_to_write + i*sizeof(u32),
2828 *(((u32 *)(&afex_stats))+i));
2830 /* send ack message to MCP */
2831 bnx2x_fw_command(bp, DRV_MSG_CODE_AFEX_STATSGET_ACK, 0);
2834 if (cmd & DRV_STATUS_AFEX_VIFSET_REQ) {
2835 mf_config = MF_CFG_RD(bp, func_mf_config[func].config);
2836 bp->mf_config[BP_VN(bp)] = mf_config;
2838 "afex: got MCP req VIFSET_REQ, mf_config 0x%x\n",
2841 /* if VIF_SET is "enabled" */
2842 if (!(mf_config & FUNC_MF_CFG_FUNC_DISABLED)) {
2843 /* set rate limit directly to internal RAM */
2844 struct cmng_init_input cmng_input;
2845 struct rate_shaping_vars_per_vn m_rs_vn;
2846 size_t size = sizeof(struct rate_shaping_vars_per_vn);
2847 u32 addr = BAR_XSTRORM_INTMEM +
2848 XSTORM_RATE_SHAPING_PER_VN_VARS_OFFSET(BP_FUNC(bp));
2850 bp->mf_config[BP_VN(bp)] = mf_config;
2852 bnx2x_calc_vn_max(bp, BP_VN(bp), &cmng_input);
2853 m_rs_vn.vn_counter.rate =
2854 cmng_input.vnic_max_rate[BP_VN(bp)];
2855 m_rs_vn.vn_counter.quota =
2856 (m_rs_vn.vn_counter.rate *
2857 RS_PERIODIC_TIMEOUT_USEC) / 8;
2859 __storm_memset_struct(bp, addr, size, (u32 *)&m_rs_vn);
2861 /* read relevant values from mf_cfg struct in shmem */
2863 (MF_CFG_RD(bp, func_mf_config[func].e1hov_tag) &
2864 FUNC_MF_CFG_E1HOV_TAG_MASK) >>
2865 FUNC_MF_CFG_E1HOV_TAG_SHIFT;
2867 (MF_CFG_RD(bp, func_mf_config[func].e1hov_tag) &
2868 FUNC_MF_CFG_AFEX_VLAN_MASK) >>
2869 FUNC_MF_CFG_AFEX_VLAN_SHIFT;
2870 vlan_prio = (mf_config &
2871 FUNC_MF_CFG_TRANSMIT_PRIORITY_MASK) >>
2872 FUNC_MF_CFG_TRANSMIT_PRIORITY_SHIFT;
2873 vlan_val |= (vlan_prio << VLAN_PRIO_SHIFT);
2876 func_mf_config[func].afex_config) &
2877 FUNC_MF_CFG_AFEX_VLAN_MODE_MASK) >>
2878 FUNC_MF_CFG_AFEX_VLAN_MODE_SHIFT;
2881 func_mf_config[func].afex_config) &
2882 FUNC_MF_CFG_AFEX_COS_FILTER_MASK) >>
2883 FUNC_MF_CFG_AFEX_COS_FILTER_SHIFT;
2885 /* send ramrod to FW, return in case of failure */
2886 if (bnx2x_afex_func_update(bp, vif_id, vlan_val,
2890 bp->afex_def_vlan_tag = vlan_val;
2891 bp->afex_vlan_mode = vlan_mode;
2893 /* notify link down because BP->flags is disabled */
2894 bnx2x_link_report(bp);
2896 /* send INVALID VIF ramrod to FW */
2897 bnx2x_afex_func_update(bp, 0xFFFF, 0, 0);
2899 /* Reset the default afex VLAN */
2900 bp->afex_def_vlan_tag = -1;
2905 static void bnx2x_handle_update_svid_cmd(struct bnx2x *bp)
2907 struct bnx2x_func_switch_update_params *switch_update_params;
2908 struct bnx2x_func_state_params func_params;
2910 memset(&func_params, 0, sizeof(struct bnx2x_func_state_params));
2911 switch_update_params = &func_params.params.switch_update;
2912 func_params.f_obj = &bp->func_obj;
2913 func_params.cmd = BNX2X_F_CMD_SWITCH_UPDATE;
2915 if (IS_MF_UFP(bp)) {
2916 int func = BP_ABS_FUNC(bp);
2919 /* Re-learn the S-tag from shmem */
2920 val = MF_CFG_RD(bp, func_mf_config[func].e1hov_tag) &
2921 FUNC_MF_CFG_E1HOV_TAG_MASK;
2922 if (val != FUNC_MF_CFG_E1HOV_TAG_DEFAULT) {
2925 BNX2X_ERR("Got an SVID event, but no tag is configured in shmem\n");
2929 /* Configure new S-tag in LLH */
2930 REG_WR(bp, NIG_REG_LLH0_FUNC_VLAN_ID + BP_PORT(bp) * 8,
2933 /* Send Ramrod to update FW of change */
2934 __set_bit(BNX2X_F_UPDATE_SD_VLAN_TAG_CHNG,
2935 &switch_update_params->changes);
2936 switch_update_params->vlan = bp->mf_ov;
2938 if (bnx2x_func_state_change(bp, &func_params) < 0) {
2939 BNX2X_ERR("Failed to configure FW of S-tag Change to %02x\n",
2944 DP(BNX2X_MSG_MCP, "Configured S-tag %02x\n", bp->mf_ov);
2946 bnx2x_fw_command(bp, DRV_MSG_CODE_OEM_UPDATE_SVID_OK, 0);
2951 /* not supported by SW yet */
2953 bnx2x_fw_command(bp, DRV_MSG_CODE_OEM_UPDATE_SVID_FAILURE, 0);
2956 static void bnx2x_pmf_update(struct bnx2x *bp)
2958 int port = BP_PORT(bp);
2962 DP(BNX2X_MSG_MCP, "pmf %d\n", bp->port.pmf);
2965 * We need the mb() to ensure the ordering between the writing to
2966 * bp->port.pmf here and reading it from the bnx2x_periodic_task().
2970 /* queue a periodic task */
2971 queue_delayed_work(bnx2x_wq, &bp->period_task, 0);
2973 bnx2x_dcbx_pmf_update(bp);
2975 /* enable nig attention */
2976 val = (0xff0f | (1 << (BP_VN(bp) + 4)));
2977 if (bp->common.int_block == INT_BLOCK_HC) {
2978 REG_WR(bp, HC_REG_TRAILING_EDGE_0 + port*8, val);
2979 REG_WR(bp, HC_REG_LEADING_EDGE_0 + port*8, val);
2980 } else if (!CHIP_IS_E1x(bp)) {
2981 REG_WR(bp, IGU_REG_TRAILING_EDGE_LATCH, val);
2982 REG_WR(bp, IGU_REG_LEADING_EDGE_LATCH, val);
2985 bnx2x_stats_handle(bp, STATS_EVENT_PMF);
2993 * General service functions
2996 /* send the MCP a request, block until there is a reply */
2997 u32 bnx2x_fw_command(struct bnx2x *bp, u32 command, u32 param)
2999 int mb_idx = BP_FW_MB_IDX(bp);
3003 u8 delay = CHIP_REV_IS_SLOW(bp) ? 100 : 10;
3005 mutex_lock(&bp->fw_mb_mutex);
3007 SHMEM_WR(bp, func_mb[mb_idx].drv_mb_param, param);
3008 SHMEM_WR(bp, func_mb[mb_idx].drv_mb_header, (command | seq));
3010 DP(BNX2X_MSG_MCP, "wrote command (%x) to FW MB param 0x%08x\n",
3011 (command | seq), param);
3014 /* let the FW do it's magic ... */
3017 rc = SHMEM_RD(bp, func_mb[mb_idx].fw_mb_header);
3019 /* Give the FW up to 5 second (500*10ms) */
3020 } while ((seq != (rc & FW_MSG_SEQ_NUMBER_MASK)) && (cnt++ < 500));
3022 DP(BNX2X_MSG_MCP, "[after %d ms] read (%x) seq is (%x) from FW MB\n",
3023 cnt*delay, rc, seq);
3025 /* is this a reply to our command? */
3026 if (seq == (rc & FW_MSG_SEQ_NUMBER_MASK))
3027 rc &= FW_MSG_CODE_MASK;
3030 BNX2X_ERR("FW failed to respond!\n");
3034 mutex_unlock(&bp->fw_mb_mutex);
3039 static void storm_memset_func_cfg(struct bnx2x *bp,
3040 struct tstorm_eth_function_common_config *tcfg,
3043 size_t size = sizeof(struct tstorm_eth_function_common_config);
3045 u32 addr = BAR_TSTRORM_INTMEM +
3046 TSTORM_FUNCTION_COMMON_CONFIG_OFFSET(abs_fid);
3048 __storm_memset_struct(bp, addr, size, (u32 *)tcfg);
3051 void bnx2x_func_init(struct bnx2x *bp, struct bnx2x_func_init_params *p)
3053 if (CHIP_IS_E1x(bp)) {
3054 struct tstorm_eth_function_common_config tcfg = {0};
3056 storm_memset_func_cfg(bp, &tcfg, p->func_id);
3059 /* Enable the function in the FW */
3060 storm_memset_vf_to_pf(bp, p->func_id, p->pf_id);
3061 storm_memset_func_en(bp, p->func_id, 1);
3064 if (p->func_flgs & FUNC_FLG_SPQ) {
3065 storm_memset_spq_addr(bp, p->spq_map, p->func_id);
3066 REG_WR(bp, XSEM_REG_FAST_MEMORY +
3067 XSTORM_SPQ_PROD_OFFSET(p->func_id), p->spq_prod);
3072 * bnx2x_get_common_flags - Return common flags
3076 * @zero_stats TRUE if statistics zeroing is needed
3078 * Return the flags that are common for the Tx-only and not normal connections.
3080 static unsigned long bnx2x_get_common_flags(struct bnx2x *bp,
3081 struct bnx2x_fastpath *fp,
3084 unsigned long flags = 0;
3086 /* PF driver will always initialize the Queue to an ACTIVE state */
3087 __set_bit(BNX2X_Q_FLG_ACTIVE, &flags);
3089 /* tx only connections collect statistics (on the same index as the
3090 * parent connection). The statistics are zeroed when the parent
3091 * connection is initialized.
3094 __set_bit(BNX2X_Q_FLG_STATS, &flags);
3096 __set_bit(BNX2X_Q_FLG_ZERO_STATS, &flags);
3098 if (bp->flags & TX_SWITCHING)
3099 __set_bit(BNX2X_Q_FLG_TX_SWITCH, &flags);
3101 __set_bit(BNX2X_Q_FLG_PCSUM_ON_PKT, &flags);
3102 __set_bit(BNX2X_Q_FLG_TUN_INC_INNER_IP_ID, &flags);
3104 #ifdef BNX2X_STOP_ON_ERROR
3105 __set_bit(BNX2X_Q_FLG_TX_SEC, &flags);
3111 static unsigned long bnx2x_get_q_flags(struct bnx2x *bp,
3112 struct bnx2x_fastpath *fp,
3115 unsigned long flags = 0;
3117 /* calculate other queue flags */
3119 __set_bit(BNX2X_Q_FLG_OV, &flags);
3121 if (IS_FCOE_FP(fp)) {
3122 __set_bit(BNX2X_Q_FLG_FCOE, &flags);
3123 /* For FCoE - force usage of default priority (for afex) */
3124 __set_bit(BNX2X_Q_FLG_FORCE_DEFAULT_PRI, &flags);
3127 if (fp->mode != TPA_MODE_DISABLED) {
3128 __set_bit(BNX2X_Q_FLG_TPA, &flags);
3129 __set_bit(BNX2X_Q_FLG_TPA_IPV6, &flags);
3130 if (fp->mode == TPA_MODE_GRO)
3131 __set_bit(BNX2X_Q_FLG_TPA_GRO, &flags);
3135 __set_bit(BNX2X_Q_FLG_LEADING_RSS, &flags);
3136 __set_bit(BNX2X_Q_FLG_MCAST, &flags);
3139 /* Always set HW VLAN stripping */
3140 __set_bit(BNX2X_Q_FLG_VLAN, &flags);
3142 /* configure silent vlan removal */
3144 __set_bit(BNX2X_Q_FLG_SILENT_VLAN_REM, &flags);
3146 return flags | bnx2x_get_common_flags(bp, fp, true);
3149 static void bnx2x_pf_q_prep_general(struct bnx2x *bp,
3150 struct bnx2x_fastpath *fp, struct bnx2x_general_setup_params *gen_init,
3153 gen_init->stat_id = bnx2x_stats_id(fp);
3154 gen_init->spcl_id = fp->cl_id;
3156 /* Always use mini-jumbo MTU for FCoE L2 ring */
3158 gen_init->mtu = BNX2X_FCOE_MINI_JUMBO_MTU;
3160 gen_init->mtu = bp->dev->mtu;
3162 gen_init->cos = cos;
3164 gen_init->fp_hsi = ETH_FP_HSI_VERSION;
3167 static void bnx2x_pf_rx_q_prep(struct bnx2x *bp,
3168 struct bnx2x_fastpath *fp, struct rxq_pause_params *pause,
3169 struct bnx2x_rxq_setup_params *rxq_init)
3173 u16 tpa_agg_size = 0;
3175 if (fp->mode != TPA_MODE_DISABLED) {
3176 pause->sge_th_lo = SGE_TH_LO(bp);
3177 pause->sge_th_hi = SGE_TH_HI(bp);
3179 /* validate SGE ring has enough to cross high threshold */
3180 WARN_ON(bp->dropless_fc &&
3181 pause->sge_th_hi + FW_PREFETCH_CNT >
3182 MAX_RX_SGE_CNT * NUM_RX_SGE_PAGES);
3184 tpa_agg_size = TPA_AGG_SIZE;
3185 max_sge = SGE_PAGE_ALIGN(bp->dev->mtu) >>
3187 max_sge = ((max_sge + PAGES_PER_SGE - 1) &
3188 (~(PAGES_PER_SGE-1))) >> PAGES_PER_SGE_SHIFT;
3189 sge_sz = (u16)min_t(u32, SGE_PAGES, 0xffff);
3192 /* pause - not for e1 */
3193 if (!CHIP_IS_E1(bp)) {
3194 pause->bd_th_lo = BD_TH_LO(bp);
3195 pause->bd_th_hi = BD_TH_HI(bp);
3197 pause->rcq_th_lo = RCQ_TH_LO(bp);
3198 pause->rcq_th_hi = RCQ_TH_HI(bp);
3200 * validate that rings have enough entries to cross
3203 WARN_ON(bp->dropless_fc &&
3204 pause->bd_th_hi + FW_PREFETCH_CNT >
3206 WARN_ON(bp->dropless_fc &&
3207 pause->rcq_th_hi + FW_PREFETCH_CNT >
3208 NUM_RCQ_RINGS * MAX_RCQ_DESC_CNT);
3214 rxq_init->dscr_map = fp->rx_desc_mapping;
3215 rxq_init->sge_map = fp->rx_sge_mapping;
3216 rxq_init->rcq_map = fp->rx_comp_mapping;
3217 rxq_init->rcq_np_map = fp->rx_comp_mapping + BCM_PAGE_SIZE;
3219 /* This should be a maximum number of data bytes that may be
3220 * placed on the BD (not including paddings).
3222 rxq_init->buf_sz = fp->rx_buf_size - BNX2X_FW_RX_ALIGN_START -
3223 BNX2X_FW_RX_ALIGN_END - IP_HEADER_ALIGNMENT_PADDING;
3225 rxq_init->cl_qzone_id = fp->cl_qzone_id;
3226 rxq_init->tpa_agg_sz = tpa_agg_size;
3227 rxq_init->sge_buf_sz = sge_sz;
3228 rxq_init->max_sges_pkt = max_sge;
3229 rxq_init->rss_engine_id = BP_FUNC(bp);
3230 rxq_init->mcast_engine_id = BP_FUNC(bp);
3232 /* Maximum number or simultaneous TPA aggregation for this Queue.
3234 * For PF Clients it should be the maximum available number.
3235 * VF driver(s) may want to define it to a smaller value.
3237 rxq_init->max_tpa_queues = MAX_AGG_QS(bp);
3239 rxq_init->cache_line_log = BNX2X_RX_ALIGN_SHIFT;
3240 rxq_init->fw_sb_id = fp->fw_sb_id;
3243 rxq_init->sb_cq_index = HC_SP_INDEX_ETH_FCOE_RX_CQ_CONS;
3245 rxq_init->sb_cq_index = HC_INDEX_ETH_RX_CQ_CONS;
3246 /* configure silent vlan removal
3247 * if multi function mode is afex, then mask default vlan
3249 if (IS_MF_AFEX(bp)) {
3250 rxq_init->silent_removal_value = bp->afex_def_vlan_tag;
3251 rxq_init->silent_removal_mask = VLAN_VID_MASK;
3255 static void bnx2x_pf_tx_q_prep(struct bnx2x *bp,
3256 struct bnx2x_fastpath *fp, struct bnx2x_txq_setup_params *txq_init,
3259 txq_init->dscr_map = fp->txdata_ptr[cos]->tx_desc_mapping;
3260 txq_init->sb_cq_index = HC_INDEX_ETH_FIRST_TX_CQ_CONS + cos;
3261 txq_init->traffic_type = LLFC_TRAFFIC_TYPE_NW;
3262 txq_init->fw_sb_id = fp->fw_sb_id;
3265 * set the tss leading client id for TX classification ==
3266 * leading RSS client id
3268 txq_init->tss_leading_cl_id = bnx2x_fp(bp, 0, cl_id);
3270 if (IS_FCOE_FP(fp)) {
3271 txq_init->sb_cq_index = HC_SP_INDEX_ETH_FCOE_TX_CQ_CONS;
3272 txq_init->traffic_type = LLFC_TRAFFIC_TYPE_FCOE;
3276 static void bnx2x_pf_init(struct bnx2x *bp)
3278 struct bnx2x_func_init_params func_init = {0};
3279 struct event_ring_data eq_data = { {0} };
3282 if (!CHIP_IS_E1x(bp)) {
3283 /* reset IGU PF statistics: MSIX + ATTN */
3285 REG_WR(bp, IGU_REG_STATISTIC_NUM_MESSAGE_SENT +
3286 BNX2X_IGU_STAS_MSG_VF_CNT*4 +
3287 (CHIP_MODE_IS_4_PORT(bp) ?
3288 BP_FUNC(bp) : BP_VN(bp))*4, 0);
3290 REG_WR(bp, IGU_REG_STATISTIC_NUM_MESSAGE_SENT +
3291 BNX2X_IGU_STAS_MSG_VF_CNT*4 +
3292 BNX2X_IGU_STAS_MSG_PF_CNT*4 +
3293 (CHIP_MODE_IS_4_PORT(bp) ?
3294 BP_FUNC(bp) : BP_VN(bp))*4, 0);
3297 /* function setup flags */
3298 flags = (FUNC_FLG_STATS | FUNC_FLG_LEADING | FUNC_FLG_SPQ);
3300 /* This flag is relevant for E1x only.
3301 * E2 doesn't have a TPA configuration in a function level.
3303 flags |= (bp->dev->features & NETIF_F_LRO) ? FUNC_FLG_TPA : 0;
3305 func_init.func_flgs = flags;
3306 func_init.pf_id = BP_FUNC(bp);
3307 func_init.func_id = BP_FUNC(bp);
3308 func_init.spq_map = bp->spq_mapping;
3309 func_init.spq_prod = bp->spq_prod_idx;
3311 bnx2x_func_init(bp, &func_init);
3313 memset(&(bp->cmng), 0, sizeof(struct cmng_struct_per_port));
3316 * Congestion management values depend on the link rate
3317 * There is no active link so initial link rate is set to 10 Gbps.
3318 * When the link comes up The congestion management values are
3319 * re-calculated according to the actual link rate.
3321 bp->link_vars.line_speed = SPEED_10000;
3322 bnx2x_cmng_fns_init(bp, true, bnx2x_get_cmng_fns_mode(bp));
3324 /* Only the PMF sets the HW */
3326 storm_memset_cmng(bp, &bp->cmng, BP_PORT(bp));
3328 /* init Event Queue - PCI bus guarantees correct endianity*/
3329 eq_data.base_addr.hi = U64_HI(bp->eq_mapping);
3330 eq_data.base_addr.lo = U64_LO(bp->eq_mapping);
3331 eq_data.producer = bp->eq_prod;
3332 eq_data.index_id = HC_SP_INDEX_EQ_CONS;
3333 eq_data.sb_id = DEF_SB_ID;
3334 storm_memset_eq_data(bp, &eq_data, BP_FUNC(bp));
3337 static void bnx2x_e1h_disable(struct bnx2x *bp)
3339 int port = BP_PORT(bp);
3341 bnx2x_tx_disable(bp);
3343 REG_WR(bp, NIG_REG_LLH0_FUNC_EN + port*8, 0);
3346 static void bnx2x_e1h_enable(struct bnx2x *bp)
3348 int port = BP_PORT(bp);
3350 if (!(IS_MF_UFP(bp) && BNX2X_IS_MF_SD_PROTOCOL_FCOE(bp)))
3351 REG_WR(bp, NIG_REG_LLH0_FUNC_EN + port * 8, 1);
3353 /* Tx queue should be only re-enabled */
3354 netif_tx_wake_all_queues(bp->dev);
3357 * Should not call netif_carrier_on since it will be called if the link
3358 * is up when checking for link state
3362 #define DRV_INFO_ETH_STAT_NUM_MACS_REQUIRED 3
3364 static void bnx2x_drv_info_ether_stat(struct bnx2x *bp)
3366 struct eth_stats_info *ether_stat =
3367 &bp->slowpath->drv_info_to_mcp.ether_stat;
3368 struct bnx2x_vlan_mac_obj *mac_obj =
3369 &bp->sp_objs->mac_obj;
3372 strlcpy(ether_stat->version, DRV_MODULE_VERSION,
3373 ETH_STAT_INFO_VERSION_LEN);
3375 /* get DRV_INFO_ETH_STAT_NUM_MACS_REQUIRED macs, placing them in the
3376 * mac_local field in ether_stat struct. The base address is offset by 2
3377 * bytes to account for the field being 8 bytes but a mac address is
3378 * only 6 bytes. Likewise, the stride for the get_n_elements function is
3379 * 2 bytes to compensate from the 6 bytes of a mac to the 8 bytes
3380 * allocated by the ether_stat struct, so the macs will land in their
3383 for (i = 0; i < DRV_INFO_ETH_STAT_NUM_MACS_REQUIRED; i++)
3384 memset(ether_stat->mac_local + i, 0,
3385 sizeof(ether_stat->mac_local[0]));
3386 mac_obj->get_n_elements(bp, &bp->sp_objs[0].mac_obj,
3387 DRV_INFO_ETH_STAT_NUM_MACS_REQUIRED,
3388 ether_stat->mac_local + MAC_PAD, MAC_PAD,
3390 ether_stat->mtu_size = bp->dev->mtu;
3391 if (bp->dev->features & NETIF_F_RXCSUM)
3392 ether_stat->feature_flags |= FEATURE_ETH_CHKSUM_OFFLOAD_MASK;
3393 if (bp->dev->features & NETIF_F_TSO)
3394 ether_stat->feature_flags |= FEATURE_ETH_LSO_MASK;
3395 ether_stat->feature_flags |= bp->common.boot_mode;
3397 ether_stat->promiscuous_mode = (bp->dev->flags & IFF_PROMISC) ? 1 : 0;
3399 ether_stat->txq_size = bp->tx_ring_size;
3400 ether_stat->rxq_size = bp->rx_ring_size;
3402 #ifdef CONFIG_BNX2X_SRIOV
3403 ether_stat->vf_cnt = IS_SRIOV(bp) ? bp->vfdb->sriov.nr_virtfn : 0;
3407 static void bnx2x_drv_info_fcoe_stat(struct bnx2x *bp)
3409 struct bnx2x_dcbx_app_params *app = &bp->dcbx_port_params.app;
3410 struct fcoe_stats_info *fcoe_stat =
3411 &bp->slowpath->drv_info_to_mcp.fcoe_stat;
3413 if (!CNIC_LOADED(bp))
3416 memcpy(fcoe_stat->mac_local + MAC_PAD, bp->fip_mac, ETH_ALEN);
3418 fcoe_stat->qos_priority =
3419 app->traffic_type_priority[LLFC_TRAFFIC_TYPE_FCOE];
3421 /* insert FCoE stats from ramrod response */
3423 struct tstorm_per_queue_stats *fcoe_q_tstorm_stats =
3424 &bp->fw_stats_data->queue_stats[FCOE_IDX(bp)].
3425 tstorm_queue_statistics;
3427 struct xstorm_per_queue_stats *fcoe_q_xstorm_stats =
3428 &bp->fw_stats_data->queue_stats[FCOE_IDX(bp)].
3429 xstorm_queue_statistics;
3431 struct fcoe_statistics_params *fw_fcoe_stat =
3432 &bp->fw_stats_data->fcoe;
3434 ADD_64_LE(fcoe_stat->rx_bytes_hi, LE32_0,
3435 fcoe_stat->rx_bytes_lo,
3436 fw_fcoe_stat->rx_stat0.fcoe_rx_byte_cnt);
3438 ADD_64_LE(fcoe_stat->rx_bytes_hi,
3439 fcoe_q_tstorm_stats->rcv_ucast_bytes.hi,
3440 fcoe_stat->rx_bytes_lo,
3441 fcoe_q_tstorm_stats->rcv_ucast_bytes.lo);
3443 ADD_64_LE(fcoe_stat->rx_bytes_hi,
3444 fcoe_q_tstorm_stats->rcv_bcast_bytes.hi,
3445 fcoe_stat->rx_bytes_lo,
3446 fcoe_q_tstorm_stats->rcv_bcast_bytes.lo);
3448 ADD_64_LE(fcoe_stat->rx_bytes_hi,
3449 fcoe_q_tstorm_stats->rcv_mcast_bytes.hi,
3450 fcoe_stat->rx_bytes_lo,
3451 fcoe_q_tstorm_stats->rcv_mcast_bytes.lo);
3453 ADD_64_LE(fcoe_stat->rx_frames_hi, LE32_0,
3454 fcoe_stat->rx_frames_lo,
3455 fw_fcoe_stat->rx_stat0.fcoe_rx_pkt_cnt);
3457 ADD_64_LE(fcoe_stat->rx_frames_hi, LE32_0,
3458 fcoe_stat->rx_frames_lo,
3459 fcoe_q_tstorm_stats->rcv_ucast_pkts);
3461 ADD_64_LE(fcoe_stat->rx_frames_hi, LE32_0,
3462 fcoe_stat->rx_frames_lo,
3463 fcoe_q_tstorm_stats->rcv_bcast_pkts);
3465 ADD_64_LE(fcoe_stat->rx_frames_hi, LE32_0,
3466 fcoe_stat->rx_frames_lo,
3467 fcoe_q_tstorm_stats->rcv_mcast_pkts);
3469 ADD_64_LE(fcoe_stat->tx_bytes_hi, LE32_0,
3470 fcoe_stat->tx_bytes_lo,
3471 fw_fcoe_stat->tx_stat.fcoe_tx_byte_cnt);
3473 ADD_64_LE(fcoe_stat->tx_bytes_hi,
3474 fcoe_q_xstorm_stats->ucast_bytes_sent.hi,
3475 fcoe_stat->tx_bytes_lo,
3476 fcoe_q_xstorm_stats->ucast_bytes_sent.lo);
3478 ADD_64_LE(fcoe_stat->tx_bytes_hi,
3479 fcoe_q_xstorm_stats->bcast_bytes_sent.hi,
3480 fcoe_stat->tx_bytes_lo,
3481 fcoe_q_xstorm_stats->bcast_bytes_sent.lo);
3483 ADD_64_LE(fcoe_stat->tx_bytes_hi,
3484 fcoe_q_xstorm_stats->mcast_bytes_sent.hi,
3485 fcoe_stat->tx_bytes_lo,
3486 fcoe_q_xstorm_stats->mcast_bytes_sent.lo);
3488 ADD_64_LE(fcoe_stat->tx_frames_hi, LE32_0,
3489 fcoe_stat->tx_frames_lo,
3490 fw_fcoe_stat->tx_stat.fcoe_tx_pkt_cnt);
3492 ADD_64_LE(fcoe_stat->tx_frames_hi, LE32_0,
3493 fcoe_stat->tx_frames_lo,
3494 fcoe_q_xstorm_stats->ucast_pkts_sent);
3496 ADD_64_LE(fcoe_stat->tx_frames_hi, LE32_0,
3497 fcoe_stat->tx_frames_lo,
3498 fcoe_q_xstorm_stats->bcast_pkts_sent);
3500 ADD_64_LE(fcoe_stat->tx_frames_hi, LE32_0,
3501 fcoe_stat->tx_frames_lo,
3502 fcoe_q_xstorm_stats->mcast_pkts_sent);
3505 /* ask L5 driver to add data to the struct */
3506 bnx2x_cnic_notify(bp, CNIC_CTL_FCOE_STATS_GET_CMD);
3509 static void bnx2x_drv_info_iscsi_stat(struct bnx2x *bp)
3511 struct bnx2x_dcbx_app_params *app = &bp->dcbx_port_params.app;
3512 struct iscsi_stats_info *iscsi_stat =
3513 &bp->slowpath->drv_info_to_mcp.iscsi_stat;
3515 if (!CNIC_LOADED(bp))
3518 memcpy(iscsi_stat->mac_local + MAC_PAD, bp->cnic_eth_dev.iscsi_mac,
3521 iscsi_stat->qos_priority =
3522 app->traffic_type_priority[LLFC_TRAFFIC_TYPE_ISCSI];
3524 /* ask L5 driver to add data to the struct */
3525 bnx2x_cnic_notify(bp, CNIC_CTL_ISCSI_STATS_GET_CMD);
3528 /* called due to MCP event (on pmf):
3529 * reread new bandwidth configuration
3531 * notify others function about the change
3533 static void bnx2x_config_mf_bw(struct bnx2x *bp)
3535 if (bp->link_vars.link_up) {
3536 bnx2x_cmng_fns_init(bp, true, CMNG_FNS_MINMAX);
3537 bnx2x_link_sync_notify(bp);
3539 storm_memset_cmng(bp, &bp->cmng, BP_PORT(bp));
3542 static void bnx2x_set_mf_bw(struct bnx2x *bp)
3544 bnx2x_config_mf_bw(bp);
3545 bnx2x_fw_command(bp, DRV_MSG_CODE_SET_MF_BW_ACK, 0);
3548 static void bnx2x_handle_eee_event(struct bnx2x *bp)
3550 DP(BNX2X_MSG_MCP, "EEE - LLDP event\n");
3551 bnx2x_fw_command(bp, DRV_MSG_CODE_EEE_RESULTS_ACK, 0);
3554 #define BNX2X_UPDATE_DRV_INFO_IND_LENGTH (20)
3555 #define BNX2X_UPDATE_DRV_INFO_IND_COUNT (25)
3557 static void bnx2x_handle_drv_info_req(struct bnx2x *bp)
3559 enum drv_info_opcode op_code;
3560 u32 drv_info_ctl = SHMEM2_RD(bp, drv_info_control);
3561 bool release = false;
3564 /* if drv_info version supported by MFW doesn't match - send NACK */
3565 if ((drv_info_ctl & DRV_INFO_CONTROL_VER_MASK) != DRV_INFO_CUR_VER) {
3566 bnx2x_fw_command(bp, DRV_MSG_CODE_DRV_INFO_NACK, 0);
3570 op_code = (drv_info_ctl & DRV_INFO_CONTROL_OP_CODE_MASK) >>
3571 DRV_INFO_CONTROL_OP_CODE_SHIFT;
3573 /* Must prevent other flows from accessing drv_info_to_mcp */
3574 mutex_lock(&bp->drv_info_mutex);
3576 memset(&bp->slowpath->drv_info_to_mcp, 0,
3577 sizeof(union drv_info_to_mcp));
3580 case ETH_STATS_OPCODE:
3581 bnx2x_drv_info_ether_stat(bp);
3583 case FCOE_STATS_OPCODE:
3584 bnx2x_drv_info_fcoe_stat(bp);
3586 case ISCSI_STATS_OPCODE:
3587 bnx2x_drv_info_iscsi_stat(bp);
3590 /* if op code isn't supported - send NACK */
3591 bnx2x_fw_command(bp, DRV_MSG_CODE_DRV_INFO_NACK, 0);
3595 /* if we got drv_info attn from MFW then these fields are defined in
3598 SHMEM2_WR(bp, drv_info_host_addr_lo,
3599 U64_LO(bnx2x_sp_mapping(bp, drv_info_to_mcp)));
3600 SHMEM2_WR(bp, drv_info_host_addr_hi,
3601 U64_HI(bnx2x_sp_mapping(bp, drv_info_to_mcp)));
3603 bnx2x_fw_command(bp, DRV_MSG_CODE_DRV_INFO_ACK, 0);
3605 /* Since possible management wants both this and get_driver_version
3606 * need to wait until management notifies us it finished utilizing
3609 if (!SHMEM2_HAS(bp, mfw_drv_indication)) {
3610 DP(BNX2X_MSG_MCP, "Management does not support indication\n");
3611 } else if (!bp->drv_info_mng_owner) {
3612 u32 bit = MFW_DRV_IND_READ_DONE_OFFSET((BP_ABS_FUNC(bp) >> 1));
3614 for (wait = 0; wait < BNX2X_UPDATE_DRV_INFO_IND_COUNT; wait++) {
3615 u32 indication = SHMEM2_RD(bp, mfw_drv_indication);
3617 /* Management is done; need to clear indication */
3618 if (indication & bit) {
3619 SHMEM2_WR(bp, mfw_drv_indication,
3625 msleep(BNX2X_UPDATE_DRV_INFO_IND_LENGTH);
3629 DP(BNX2X_MSG_MCP, "Management did not release indication\n");
3630 bp->drv_info_mng_owner = true;
3634 mutex_unlock(&bp->drv_info_mutex);
3637 static u32 bnx2x_update_mng_version_utility(u8 *version, bool bnx2x_format)
3643 i = sscanf(version, "1.%c%hhd.%hhd.%hhd",
3644 &vals[0], &vals[1], &vals[2], &vals[3]);
3648 i = sscanf(version, "%hhd.%hhd.%hhd.%hhd",
3649 &vals[0], &vals[1], &vals[2], &vals[3]);
3655 return (vals[0] << 24) | (vals[1] << 16) | (vals[2] << 8) | vals[3];
3658 void bnx2x_update_mng_version(struct bnx2x *bp)
3660 u32 iscsiver = DRV_VER_NOT_LOADED;
3661 u32 fcoever = DRV_VER_NOT_LOADED;
3662 u32 ethver = DRV_VER_NOT_LOADED;
3663 int idx = BP_FW_MB_IDX(bp);
3666 if (!SHMEM2_HAS(bp, func_os_drv_ver))
3669 mutex_lock(&bp->drv_info_mutex);
3670 /* Must not proceed when `bnx2x_handle_drv_info_req' is feasible */
3671 if (bp->drv_info_mng_owner)
3674 if (bp->state != BNX2X_STATE_OPEN)
3677 /* Parse ethernet driver version */
3678 ethver = bnx2x_update_mng_version_utility(DRV_MODULE_VERSION, true);
3679 if (!CNIC_LOADED(bp))
3682 /* Try getting storage driver version via cnic */
3683 memset(&bp->slowpath->drv_info_to_mcp, 0,
3684 sizeof(union drv_info_to_mcp));
3685 bnx2x_drv_info_iscsi_stat(bp);
3686 version = bp->slowpath->drv_info_to_mcp.iscsi_stat.version;
3687 iscsiver = bnx2x_update_mng_version_utility(version, false);
3689 memset(&bp->slowpath->drv_info_to_mcp, 0,
3690 sizeof(union drv_info_to_mcp));
3691 bnx2x_drv_info_fcoe_stat(bp);
3692 version = bp->slowpath->drv_info_to_mcp.fcoe_stat.version;
3693 fcoever = bnx2x_update_mng_version_utility(version, false);
3696 SHMEM2_WR(bp, func_os_drv_ver[idx].versions[DRV_PERS_ETHERNET], ethver);
3697 SHMEM2_WR(bp, func_os_drv_ver[idx].versions[DRV_PERS_ISCSI], iscsiver);
3698 SHMEM2_WR(bp, func_os_drv_ver[idx].versions[DRV_PERS_FCOE], fcoever);
3700 mutex_unlock(&bp->drv_info_mutex);
3702 DP(BNX2X_MSG_MCP, "Setting driver version: ETH [%08x] iSCSI [%08x] FCoE [%08x]\n",
3703 ethver, iscsiver, fcoever);
3706 static void bnx2x_oem_event(struct bnx2x *bp, u32 event)
3708 u32 cmd_ok, cmd_fail;
3711 if (event & DRV_STATUS_DCC_EVENT_MASK &&
3712 event & DRV_STATUS_OEM_EVENT_MASK) {
3713 BNX2X_ERR("Received simultaneous events %08x\n", event);
3717 if (event & DRV_STATUS_DCC_EVENT_MASK) {
3718 cmd_fail = DRV_MSG_CODE_DCC_FAILURE;
3719 cmd_ok = DRV_MSG_CODE_DCC_OK;
3720 } else /* if (event & DRV_STATUS_OEM_EVENT_MASK) */ {
3721 cmd_fail = DRV_MSG_CODE_OEM_FAILURE;
3722 cmd_ok = DRV_MSG_CODE_OEM_OK;
3725 DP(BNX2X_MSG_MCP, "oem_event 0x%x\n", event);
3727 if (event & (DRV_STATUS_DCC_DISABLE_ENABLE_PF |
3728 DRV_STATUS_OEM_DISABLE_ENABLE_PF)) {
3729 /* This is the only place besides the function initialization
3730 * where the bp->flags can change so it is done without any
3733 if (bp->mf_config[BP_VN(bp)] & FUNC_MF_CFG_FUNC_DISABLED) {
3734 DP(BNX2X_MSG_MCP, "mf_cfg function disabled\n");
3735 bp->flags |= MF_FUNC_DIS;
3737 bnx2x_e1h_disable(bp);
3739 DP(BNX2X_MSG_MCP, "mf_cfg function enabled\n");
3740 bp->flags &= ~MF_FUNC_DIS;
3742 bnx2x_e1h_enable(bp);
3744 event &= ~(DRV_STATUS_DCC_DISABLE_ENABLE_PF |
3745 DRV_STATUS_OEM_DISABLE_ENABLE_PF);
3748 if (event & (DRV_STATUS_DCC_BANDWIDTH_ALLOCATION |
3749 DRV_STATUS_OEM_BANDWIDTH_ALLOCATION)) {
3750 bnx2x_config_mf_bw(bp);
3751 event &= ~(DRV_STATUS_DCC_BANDWIDTH_ALLOCATION |
3752 DRV_STATUS_OEM_BANDWIDTH_ALLOCATION);
3755 /* Report results to MCP */
3757 bnx2x_fw_command(bp, cmd_fail, 0);
3759 bnx2x_fw_command(bp, cmd_ok, 0);
3762 /* must be called under the spq lock */
3763 static struct eth_spe *bnx2x_sp_get_next(struct bnx2x *bp)
3765 struct eth_spe *next_spe = bp->spq_prod_bd;
3767 if (bp->spq_prod_bd == bp->spq_last_bd) {
3768 bp->spq_prod_bd = bp->spq;
3769 bp->spq_prod_idx = 0;
3770 DP(BNX2X_MSG_SP, "end of spq\n");
3778 /* must be called under the spq lock */
3779 static void bnx2x_sp_prod_update(struct bnx2x *bp)
3781 int func = BP_FUNC(bp);
3784 * Make sure that BD data is updated before writing the producer:
3785 * BD data is written to the memory, the producer is read from the
3786 * memory, thus we need a full memory barrier to ensure the ordering.
3790 REG_WR16(bp, BAR_XSTRORM_INTMEM + XSTORM_SPQ_PROD_OFFSET(func),
3796 * bnx2x_is_contextless_ramrod - check if the current command ends on EQ
3798 * @cmd: command to check
3799 * @cmd_type: command type
3801 static bool bnx2x_is_contextless_ramrod(int cmd, int cmd_type)
3803 if ((cmd_type == NONE_CONNECTION_TYPE) ||
3804 (cmd == RAMROD_CMD_ID_ETH_FORWARD_SETUP) ||
3805 (cmd == RAMROD_CMD_ID_ETH_CLASSIFICATION_RULES) ||
3806 (cmd == RAMROD_CMD_ID_ETH_FILTER_RULES) ||
3807 (cmd == RAMROD_CMD_ID_ETH_MULTICAST_RULES) ||
3808 (cmd == RAMROD_CMD_ID_ETH_SET_MAC) ||
3809 (cmd == RAMROD_CMD_ID_ETH_RSS_UPDATE))
3816 * bnx2x_sp_post - place a single command on an SP ring
3818 * @bp: driver handle
3819 * @command: command to place (e.g. SETUP, FILTER_RULES, etc.)
3820 * @cid: SW CID the command is related to
3821 * @data_hi: command private data address (high 32 bits)
3822 * @data_lo: command private data address (low 32 bits)
3823 * @cmd_type: command type (e.g. NONE, ETH)
3825 * SP data is handled as if it's always an address pair, thus data fields are
3826 * not swapped to little endian in upper functions. Instead this function swaps
3827 * data as if it's two u32 fields.
3829 int bnx2x_sp_post(struct bnx2x *bp, int command, int cid,
3830 u32 data_hi, u32 data_lo, int cmd_type)
3832 struct eth_spe *spe;
3834 bool common = bnx2x_is_contextless_ramrod(command, cmd_type);
3836 #ifdef BNX2X_STOP_ON_ERROR
3837 if (unlikely(bp->panic)) {
3838 BNX2X_ERR("Can't post SP when there is panic\n");
3843 spin_lock_bh(&bp->spq_lock);
3846 if (!atomic_read(&bp->eq_spq_left)) {
3847 BNX2X_ERR("BUG! EQ ring full!\n");
3848 spin_unlock_bh(&bp->spq_lock);
3852 } else if (!atomic_read(&bp->cq_spq_left)) {
3853 BNX2X_ERR("BUG! SPQ ring full!\n");
3854 spin_unlock_bh(&bp->spq_lock);
3859 spe = bnx2x_sp_get_next(bp);
3861 /* CID needs port number to be encoded int it */
3862 spe->hdr.conn_and_cmd_data =
3863 cpu_to_le32((command << SPE_HDR_CMD_ID_SHIFT) |
3866 /* In some cases, type may already contain the func-id
3867 * mainly in SRIOV related use cases, so we add it here only
3868 * if it's not already set.
3870 if (!(cmd_type & SPE_HDR_FUNCTION_ID)) {
3871 type = (cmd_type << SPE_HDR_CONN_TYPE_SHIFT) &
3873 type |= ((BP_FUNC(bp) << SPE_HDR_FUNCTION_ID_SHIFT) &
3874 SPE_HDR_FUNCTION_ID);
3879 spe->hdr.type = cpu_to_le16(type);
3881 spe->data.update_data_addr.hi = cpu_to_le32(data_hi);
3882 spe->data.update_data_addr.lo = cpu_to_le32(data_lo);
3885 * It's ok if the actual decrement is issued towards the memory
3886 * somewhere between the spin_lock and spin_unlock. Thus no
3887 * more explicit memory barrier is needed.
3890 atomic_dec(&bp->eq_spq_left);
3892 atomic_dec(&bp->cq_spq_left);
3895 "SPQE[%x] (%x:%x) (cmd, common?) (%d,%d) hw_cid %x data (%x:%x) type(0x%x) left (CQ, EQ) (%x,%x)\n",
3896 bp->spq_prod_idx, (u32)U64_HI(bp->spq_mapping),
3897 (u32)(U64_LO(bp->spq_mapping) +
3898 (void *)bp->spq_prod_bd - (void *)bp->spq), command, common,
3899 HW_CID(bp, cid), data_hi, data_lo, type,
3900 atomic_read(&bp->cq_spq_left), atomic_read(&bp->eq_spq_left));
3902 bnx2x_sp_prod_update(bp);
3903 spin_unlock_bh(&bp->spq_lock);
3907 /* acquire split MCP access lock register */
3908 static int bnx2x_acquire_alr(struct bnx2x *bp)
3914 for (j = 0; j < 1000; j++) {
3915 REG_WR(bp, MCP_REG_MCPR_ACCESS_LOCK, MCPR_ACCESS_LOCK_LOCK);
3916 val = REG_RD(bp, MCP_REG_MCPR_ACCESS_LOCK);
3917 if (val & MCPR_ACCESS_LOCK_LOCK)
3920 usleep_range(5000, 10000);
3922 if (!(val & MCPR_ACCESS_LOCK_LOCK)) {
3923 BNX2X_ERR("Cannot acquire MCP access lock register\n");
3930 /* release split MCP access lock register */
3931 static void bnx2x_release_alr(struct bnx2x *bp)
3933 REG_WR(bp, MCP_REG_MCPR_ACCESS_LOCK, 0);
3936 #define BNX2X_DEF_SB_ATT_IDX 0x0001
3937 #define BNX2X_DEF_SB_IDX 0x0002
3939 static u16 bnx2x_update_dsb_idx(struct bnx2x *bp)
3941 struct host_sp_status_block *def_sb = bp->def_status_blk;
3944 barrier(); /* status block is written to by the chip */
3945 if (bp->def_att_idx != def_sb->atten_status_block.attn_bits_index) {
3946 bp->def_att_idx = def_sb->atten_status_block.attn_bits_index;
3947 rc |= BNX2X_DEF_SB_ATT_IDX;
3950 if (bp->def_idx != def_sb->sp_sb.running_index) {
3951 bp->def_idx = def_sb->sp_sb.running_index;
3952 rc |= BNX2X_DEF_SB_IDX;
3955 /* Do not reorder: indices reading should complete before handling */
3961 * slow path service functions
3964 static void bnx2x_attn_int_asserted(struct bnx2x *bp, u32 asserted)
3966 int port = BP_PORT(bp);
3967 u32 aeu_addr = port ? MISC_REG_AEU_MASK_ATTN_FUNC_1 :
3968 MISC_REG_AEU_MASK_ATTN_FUNC_0;
3969 u32 nig_int_mask_addr = port ? NIG_REG_MASK_INTERRUPT_PORT1 :
3970 NIG_REG_MASK_INTERRUPT_PORT0;
3975 if (bp->attn_state & asserted)
3976 BNX2X_ERR("IGU ERROR\n");
3978 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_PORT0_ATT_MASK + port);
3979 aeu_mask = REG_RD(bp, aeu_addr);
3981 DP(NETIF_MSG_HW, "aeu_mask %x newly asserted %x\n",
3982 aeu_mask, asserted);
3983 aeu_mask &= ~(asserted & 0x3ff);
3984 DP(NETIF_MSG_HW, "new mask %x\n", aeu_mask);
3986 REG_WR(bp, aeu_addr, aeu_mask);
3987 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_PORT0_ATT_MASK + port);
3989 DP(NETIF_MSG_HW, "attn_state %x\n", bp->attn_state);
3990 bp->attn_state |= asserted;
3991 DP(NETIF_MSG_HW, "new state %x\n", bp->attn_state);
3993 if (asserted & ATTN_HARD_WIRED_MASK) {
3994 if (asserted & ATTN_NIG_FOR_FUNC) {
3996 bnx2x_acquire_phy_lock(bp);
3998 /* save nig interrupt mask */
3999 nig_mask = REG_RD(bp, nig_int_mask_addr);
4001 /* If nig_mask is not set, no need to call the update
4005 REG_WR(bp, nig_int_mask_addr, 0);
4007 bnx2x_link_attn(bp);
4010 /* handle unicore attn? */
4012 if (asserted & ATTN_SW_TIMER_4_FUNC)
4013 DP(NETIF_MSG_HW, "ATTN_SW_TIMER_4_FUNC!\n");
4015 if (asserted & GPIO_2_FUNC)
4016 DP(NETIF_MSG_HW, "GPIO_2_FUNC!\n");
4018 if (asserted & GPIO_3_FUNC)
4019 DP(NETIF_MSG_HW, "GPIO_3_FUNC!\n");
4021 if (asserted & GPIO_4_FUNC)
4022 DP(NETIF_MSG_HW, "GPIO_4_FUNC!\n");
4025 if (asserted & ATTN_GENERAL_ATTN_1) {
4026 DP(NETIF_MSG_HW, "ATTN_GENERAL_ATTN_1!\n");
4027 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_1, 0x0);
4029 if (asserted & ATTN_GENERAL_ATTN_2) {
4030 DP(NETIF_MSG_HW, "ATTN_GENERAL_ATTN_2!\n");
4031 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_2, 0x0);
4033 if (asserted & ATTN_GENERAL_ATTN_3) {
4034 DP(NETIF_MSG_HW, "ATTN_GENERAL_ATTN_3!\n");
4035 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_3, 0x0);
4038 if (asserted & ATTN_GENERAL_ATTN_4) {
4039 DP(NETIF_MSG_HW, "ATTN_GENERAL_ATTN_4!\n");
4040 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_4, 0x0);
4042 if (asserted & ATTN_GENERAL_ATTN_5) {
4043 DP(NETIF_MSG_HW, "ATTN_GENERAL_ATTN_5!\n");
4044 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_5, 0x0);
4046 if (asserted & ATTN_GENERAL_ATTN_6) {
4047 DP(NETIF_MSG_HW, "ATTN_GENERAL_ATTN_6!\n");
4048 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_6, 0x0);
4052 } /* if hardwired */
4054 if (bp->common.int_block == INT_BLOCK_HC)
4055 reg_addr = (HC_REG_COMMAND_REG + port*32 +
4056 COMMAND_REG_ATTN_BITS_SET);
4058 reg_addr = (BAR_IGU_INTMEM + IGU_CMD_ATTN_BIT_SET_UPPER*8);
4060 DP(NETIF_MSG_HW, "about to mask 0x%08x at %s addr 0x%x\n", asserted,
4061 (bp->common.int_block == INT_BLOCK_HC) ? "HC" : "IGU", reg_addr);
4062 REG_WR(bp, reg_addr, asserted);
4064 /* now set back the mask */
4065 if (asserted & ATTN_NIG_FOR_FUNC) {
4066 /* Verify that IGU ack through BAR was written before restoring
4067 * NIG mask. This loop should exit after 2-3 iterations max.
4069 if (bp->common.int_block != INT_BLOCK_HC) {
4070 u32 cnt = 0, igu_acked;
4072 igu_acked = REG_RD(bp,
4073 IGU_REG_ATTENTION_ACK_BITS);
4074 } while (((igu_acked & ATTN_NIG_FOR_FUNC) == 0) &&
4075 (++cnt < MAX_IGU_ATTN_ACK_TO));
4078 "Failed to verify IGU ack on time\n");
4081 REG_WR(bp, nig_int_mask_addr, nig_mask);
4082 bnx2x_release_phy_lock(bp);
4086 static void bnx2x_fan_failure(struct bnx2x *bp)
4088 int port = BP_PORT(bp);
4090 /* mark the failure */
4093 dev_info.port_hw_config[port].external_phy_config);
4095 ext_phy_config &= ~PORT_HW_CFG_XGXS_EXT_PHY_TYPE_MASK;
4096 ext_phy_config |= PORT_HW_CFG_XGXS_EXT_PHY_TYPE_FAILURE;
4097 SHMEM_WR(bp, dev_info.port_hw_config[port].external_phy_config,
4100 /* log the failure */
4101 netdev_err(bp->dev, "Fan Failure on Network Controller has caused the driver to shutdown the card to prevent permanent damage.\n"
4102 "Please contact OEM Support for assistance\n");
4104 /* Schedule device reset (unload)
4105 * This is due to some boards consuming sufficient power when driver is
4106 * up to overheat if fan fails.
4108 bnx2x_schedule_sp_rtnl(bp, BNX2X_SP_RTNL_FAN_FAILURE, 0);
4111 static void bnx2x_attn_int_deasserted0(struct bnx2x *bp, u32 attn)
4113 int port = BP_PORT(bp);
4117 reg_offset = (port ? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_0 :
4118 MISC_REG_AEU_ENABLE1_FUNC_0_OUT_0);
4120 if (attn & AEU_INPUTS_ATTN_BITS_SPIO5) {
4122 val = REG_RD(bp, reg_offset);
4123 val &= ~AEU_INPUTS_ATTN_BITS_SPIO5;
4124 REG_WR(bp, reg_offset, val);
4126 BNX2X_ERR("SPIO5 hw attention\n");
4128 /* Fan failure attention */
4129 bnx2x_hw_reset_phy(&bp->link_params);
4130 bnx2x_fan_failure(bp);
4133 if ((attn & bp->link_vars.aeu_int_mask) && bp->port.pmf) {
4134 bnx2x_acquire_phy_lock(bp);
4135 bnx2x_handle_module_detect_int(&bp->link_params);
4136 bnx2x_release_phy_lock(bp);
4139 if (attn & HW_INTERRUT_ASSERT_SET_0) {
4141 val = REG_RD(bp, reg_offset);
4142 val &= ~(attn & HW_INTERRUT_ASSERT_SET_0);
4143 REG_WR(bp, reg_offset, val);
4145 BNX2X_ERR("FATAL HW block attention set0 0x%x\n",
4146 (u32)(attn & HW_INTERRUT_ASSERT_SET_0));
4151 static void bnx2x_attn_int_deasserted1(struct bnx2x *bp, u32 attn)
4155 if (attn & AEU_INPUTS_ATTN_BITS_DOORBELLQ_HW_INTERRUPT) {
4157 val = REG_RD(bp, DORQ_REG_DORQ_INT_STS_CLR);
4158 BNX2X_ERR("DB hw attention 0x%x\n", val);
4159 /* DORQ discard attention */
4161 BNX2X_ERR("FATAL error from DORQ\n");
4164 if (attn & HW_INTERRUT_ASSERT_SET_1) {
4166 int port = BP_PORT(bp);
4169 reg_offset = (port ? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_1 :
4170 MISC_REG_AEU_ENABLE1_FUNC_0_OUT_1);
4172 val = REG_RD(bp, reg_offset);
4173 val &= ~(attn & HW_INTERRUT_ASSERT_SET_1);
4174 REG_WR(bp, reg_offset, val);
4176 BNX2X_ERR("FATAL HW block attention set1 0x%x\n",
4177 (u32)(attn & HW_INTERRUT_ASSERT_SET_1));
4182 static void bnx2x_attn_int_deasserted2(struct bnx2x *bp, u32 attn)
4186 if (attn & AEU_INPUTS_ATTN_BITS_CFC_HW_INTERRUPT) {
4188 val = REG_RD(bp, CFC_REG_CFC_INT_STS_CLR);
4189 BNX2X_ERR("CFC hw attention 0x%x\n", val);
4190 /* CFC error attention */
4192 BNX2X_ERR("FATAL error from CFC\n");
4195 if (attn & AEU_INPUTS_ATTN_BITS_PXP_HW_INTERRUPT) {
4196 val = REG_RD(bp, PXP_REG_PXP_INT_STS_CLR_0);
4197 BNX2X_ERR("PXP hw attention-0 0x%x\n", val);
4198 /* RQ_USDMDP_FIFO_OVERFLOW */
4200 BNX2X_ERR("FATAL error from PXP\n");
4202 if (!CHIP_IS_E1x(bp)) {
4203 val = REG_RD(bp, PXP_REG_PXP_INT_STS_CLR_1);
4204 BNX2X_ERR("PXP hw attention-1 0x%x\n", val);
4208 if (attn & HW_INTERRUT_ASSERT_SET_2) {
4210 int port = BP_PORT(bp);
4213 reg_offset = (port ? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_2 :
4214 MISC_REG_AEU_ENABLE1_FUNC_0_OUT_2);
4216 val = REG_RD(bp, reg_offset);
4217 val &= ~(attn & HW_INTERRUT_ASSERT_SET_2);
4218 REG_WR(bp, reg_offset, val);
4220 BNX2X_ERR("FATAL HW block attention set2 0x%x\n",
4221 (u32)(attn & HW_INTERRUT_ASSERT_SET_2));
4226 static void bnx2x_attn_int_deasserted3(struct bnx2x *bp, u32 attn)
4230 if (attn & EVEREST_GEN_ATTN_IN_USE_MASK) {
4232 if (attn & BNX2X_PMF_LINK_ASSERT) {
4233 int func = BP_FUNC(bp);
4235 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_12 + func*4, 0);
4236 bnx2x_read_mf_cfg(bp);
4237 bp->mf_config[BP_VN(bp)] = MF_CFG_RD(bp,
4238 func_mf_config[BP_ABS_FUNC(bp)].config);
4240 func_mb[BP_FW_MB_IDX(bp)].drv_status);
4242 if (val & (DRV_STATUS_DCC_EVENT_MASK |
4243 DRV_STATUS_OEM_EVENT_MASK))
4245 (val & (DRV_STATUS_DCC_EVENT_MASK |
4246 DRV_STATUS_OEM_EVENT_MASK)));
4248 if (val & DRV_STATUS_SET_MF_BW)
4249 bnx2x_set_mf_bw(bp);
4251 if (val & DRV_STATUS_DRV_INFO_REQ)
4252 bnx2x_handle_drv_info_req(bp);
4254 if (val & DRV_STATUS_VF_DISABLED)
4255 bnx2x_schedule_iov_task(bp,
4256 BNX2X_IOV_HANDLE_FLR);
4258 if ((bp->port.pmf == 0) && (val & DRV_STATUS_PMF))
4259 bnx2x_pmf_update(bp);
4262 (val & DRV_STATUS_DCBX_NEGOTIATION_RESULTS) &&
4263 bp->dcbx_enabled > 0)
4264 /* start dcbx state machine */
4265 bnx2x_dcbx_set_params(bp,
4266 BNX2X_DCBX_STATE_NEG_RECEIVED);
4267 if (val & DRV_STATUS_AFEX_EVENT_MASK)
4268 bnx2x_handle_afex_cmd(bp,
4269 val & DRV_STATUS_AFEX_EVENT_MASK);
4270 if (val & DRV_STATUS_EEE_NEGOTIATION_RESULTS)
4271 bnx2x_handle_eee_event(bp);
4273 if (val & DRV_STATUS_OEM_UPDATE_SVID)
4274 bnx2x_handle_update_svid_cmd(bp);
4276 if (bp->link_vars.periodic_flags &
4277 PERIODIC_FLAGS_LINK_EVENT) {
4278 /* sync with link */
4279 bnx2x_acquire_phy_lock(bp);
4280 bp->link_vars.periodic_flags &=
4281 ~PERIODIC_FLAGS_LINK_EVENT;
4282 bnx2x_release_phy_lock(bp);
4284 bnx2x_link_sync_notify(bp);
4285 bnx2x_link_report(bp);
4287 /* Always call it here: bnx2x_link_report() will
4288 * prevent the link indication duplication.
4290 bnx2x__link_status_update(bp);
4291 } else if (attn & BNX2X_MC_ASSERT_BITS) {
4293 BNX2X_ERR("MC assert!\n");
4294 bnx2x_mc_assert(bp);
4295 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_10, 0);
4296 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_9, 0);
4297 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_8, 0);
4298 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_7, 0);
4301 } else if (attn & BNX2X_MCP_ASSERT) {
4303 BNX2X_ERR("MCP assert!\n");
4304 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_11, 0);
4308 BNX2X_ERR("Unknown HW assert! (attn 0x%x)\n", attn);
4311 if (attn & EVEREST_LATCHED_ATTN_IN_USE_MASK) {
4312 BNX2X_ERR("LATCHED attention 0x%08x (masked)\n", attn);
4313 if (attn & BNX2X_GRC_TIMEOUT) {
4314 val = CHIP_IS_E1(bp) ? 0 :
4315 REG_RD(bp, MISC_REG_GRC_TIMEOUT_ATTN);
4316 BNX2X_ERR("GRC time-out 0x%08x\n", val);
4318 if (attn & BNX2X_GRC_RSV) {
4319 val = CHIP_IS_E1(bp) ? 0 :
4320 REG_RD(bp, MISC_REG_GRC_RSV_ATTN);
4321 BNX2X_ERR("GRC reserved 0x%08x\n", val);
4323 REG_WR(bp, MISC_REG_AEU_CLR_LATCH_SIGNAL, 0x7ff);
4329 * 0-7 - Engine0 load counter.
4330 * 8-15 - Engine1 load counter.
4331 * 16 - Engine0 RESET_IN_PROGRESS bit.
4332 * 17 - Engine1 RESET_IN_PROGRESS bit.
4333 * 18 - Engine0 ONE_IS_LOADED. Set when there is at least one active function
4335 * 19 - Engine1 ONE_IS_LOADED.
4336 * 20 - Chip reset flow bit. When set none-leader must wait for both engines
4337 * leader to complete (check for both RESET_IN_PROGRESS bits and not for
4338 * just the one belonging to its engine).
4341 #define BNX2X_RECOVERY_GLOB_REG MISC_REG_GENERIC_POR_1
4343 #define BNX2X_PATH0_LOAD_CNT_MASK 0x000000ff
4344 #define BNX2X_PATH0_LOAD_CNT_SHIFT 0
4345 #define BNX2X_PATH1_LOAD_CNT_MASK 0x0000ff00
4346 #define BNX2X_PATH1_LOAD_CNT_SHIFT 8
4347 #define BNX2X_PATH0_RST_IN_PROG_BIT 0x00010000
4348 #define BNX2X_PATH1_RST_IN_PROG_BIT 0x00020000
4349 #define BNX2X_GLOBAL_RESET_BIT 0x00040000
4352 * Set the GLOBAL_RESET bit.
4354 * Should be run under rtnl lock
4356 void bnx2x_set_reset_global(struct bnx2x *bp)
4359 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG);
4360 val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG);
4361 REG_WR(bp, BNX2X_RECOVERY_GLOB_REG, val | BNX2X_GLOBAL_RESET_BIT);
4362 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG);
4366 * Clear the GLOBAL_RESET bit.
4368 * Should be run under rtnl lock
4370 static void bnx2x_clear_reset_global(struct bnx2x *bp)
4373 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG);
4374 val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG);
4375 REG_WR(bp, BNX2X_RECOVERY_GLOB_REG, val & (~BNX2X_GLOBAL_RESET_BIT));
4376 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG);
4380 * Checks the GLOBAL_RESET bit.
4382 * should be run under rtnl lock
4384 static bool bnx2x_reset_is_global(struct bnx2x *bp)
4386 u32 val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG);
4388 DP(NETIF_MSG_HW, "GEN_REG_VAL=0x%08x\n", val);
4389 return (val & BNX2X_GLOBAL_RESET_BIT) ? true : false;
4393 * Clear RESET_IN_PROGRESS bit for the current engine.
4395 * Should be run under rtnl lock
4397 static void bnx2x_set_reset_done(struct bnx2x *bp)
4400 u32 bit = BP_PATH(bp) ?
4401 BNX2X_PATH1_RST_IN_PROG_BIT : BNX2X_PATH0_RST_IN_PROG_BIT;
4402 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG);
4403 val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG);
4407 REG_WR(bp, BNX2X_RECOVERY_GLOB_REG, val);
4409 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG);
4413 * Set RESET_IN_PROGRESS for the current engine.
4415 * should be run under rtnl lock
4417 void bnx2x_set_reset_in_progress(struct bnx2x *bp)
4420 u32 bit = BP_PATH(bp) ?
4421 BNX2X_PATH1_RST_IN_PROG_BIT : BNX2X_PATH0_RST_IN_PROG_BIT;
4422 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG);
4423 val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG);
4427 REG_WR(bp, BNX2X_RECOVERY_GLOB_REG, val);
4428 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG);
4432 * Checks the RESET_IN_PROGRESS bit for the given engine.
4433 * should be run under rtnl lock
4435 bool bnx2x_reset_is_done(struct bnx2x *bp, int engine)
4437 u32 val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG);
4439 BNX2X_PATH1_RST_IN_PROG_BIT : BNX2X_PATH0_RST_IN_PROG_BIT;
4441 /* return false if bit is set */
4442 return (val & bit) ? false : true;
4446 * set pf load for the current pf.
4448 * should be run under rtnl lock
4450 void bnx2x_set_pf_load(struct bnx2x *bp)
4453 u32 mask = BP_PATH(bp) ? BNX2X_PATH1_LOAD_CNT_MASK :
4454 BNX2X_PATH0_LOAD_CNT_MASK;
4455 u32 shift = BP_PATH(bp) ? BNX2X_PATH1_LOAD_CNT_SHIFT :
4456 BNX2X_PATH0_LOAD_CNT_SHIFT;
4458 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG);
4459 val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG);
4461 DP(NETIF_MSG_IFUP, "Old GEN_REG_VAL=0x%08x\n", val);
4463 /* get the current counter value */
4464 val1 = (val & mask) >> shift;
4466 /* set bit of that PF */
4467 val1 |= (1 << bp->pf_num);
4469 /* clear the old value */
4472 /* set the new one */
4473 val |= ((val1 << shift) & mask);
4475 REG_WR(bp, BNX2X_RECOVERY_GLOB_REG, val);
4476 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG);
4480 * bnx2x_clear_pf_load - clear pf load mark
4482 * @bp: driver handle
4484 * Should be run under rtnl lock.
4485 * Decrements the load counter for the current engine. Returns
4486 * whether other functions are still loaded
4488 bool bnx2x_clear_pf_load(struct bnx2x *bp)
4491 u32 mask = BP_PATH(bp) ? BNX2X_PATH1_LOAD_CNT_MASK :
4492 BNX2X_PATH0_LOAD_CNT_MASK;
4493 u32 shift = BP_PATH(bp) ? BNX2X_PATH1_LOAD_CNT_SHIFT :
4494 BNX2X_PATH0_LOAD_CNT_SHIFT;
4496 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG);
4497 val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG);
4498 DP(NETIF_MSG_IFDOWN, "Old GEN_REG_VAL=0x%08x\n", val);
4500 /* get the current counter value */
4501 val1 = (val & mask) >> shift;
4503 /* clear bit of that PF */
4504 val1 &= ~(1 << bp->pf_num);
4506 /* clear the old value */
4509 /* set the new one */
4510 val |= ((val1 << shift) & mask);
4512 REG_WR(bp, BNX2X_RECOVERY_GLOB_REG, val);
4513 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG);
4518 * Read the load status for the current engine.
4520 * should be run under rtnl lock
4522 static bool bnx2x_get_load_status(struct bnx2x *bp, int engine)
4524 u32 mask = (engine ? BNX2X_PATH1_LOAD_CNT_MASK :
4525 BNX2X_PATH0_LOAD_CNT_MASK);
4526 u32 shift = (engine ? BNX2X_PATH1_LOAD_CNT_SHIFT :
4527 BNX2X_PATH0_LOAD_CNT_SHIFT);
4528 u32 val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG);
4530 DP(NETIF_MSG_HW | NETIF_MSG_IFUP, "GLOB_REG=0x%08x\n", val);
4532 val = (val & mask) >> shift;
4534 DP(NETIF_MSG_HW | NETIF_MSG_IFUP, "load mask for engine %d = 0x%x\n",
4540 static void _print_parity(struct bnx2x *bp, u32 reg)
4542 pr_cont(" [0x%08x] ", REG_RD(bp, reg));
4545 static void _print_next_block(int idx, const char *blk)
4547 pr_cont("%s%s", idx ? ", " : "", blk);
4550 static bool bnx2x_check_blocks_with_parity0(struct bnx2x *bp, u32 sig,
4551 int *par_num, bool print)
4559 for (i = 0; sig; i++) {
4560 cur_bit = (0x1UL << i);
4561 if (sig & cur_bit) {
4562 res |= true; /* Each bit is real error! */
4566 case AEU_INPUTS_ATTN_BITS_BRB_PARITY_ERROR:
4567 _print_next_block((*par_num)++, "BRB");
4569 BRB1_REG_BRB1_PRTY_STS);
4571 case AEU_INPUTS_ATTN_BITS_PARSER_PARITY_ERROR:
4572 _print_next_block((*par_num)++,
4574 _print_parity(bp, PRS_REG_PRS_PRTY_STS);
4576 case AEU_INPUTS_ATTN_BITS_TSDM_PARITY_ERROR:
4577 _print_next_block((*par_num)++, "TSDM");
4579 TSDM_REG_TSDM_PRTY_STS);
4581 case AEU_INPUTS_ATTN_BITS_SEARCHER_PARITY_ERROR:
4582 _print_next_block((*par_num)++,
4584 _print_parity(bp, SRC_REG_SRC_PRTY_STS);
4586 case AEU_INPUTS_ATTN_BITS_TCM_PARITY_ERROR:
4587 _print_next_block((*par_num)++, "TCM");
4588 _print_parity(bp, TCM_REG_TCM_PRTY_STS);
4590 case AEU_INPUTS_ATTN_BITS_TSEMI_PARITY_ERROR:
4591 _print_next_block((*par_num)++,
4594 TSEM_REG_TSEM_PRTY_STS_0);
4596 TSEM_REG_TSEM_PRTY_STS_1);
4598 case AEU_INPUTS_ATTN_BITS_PBCLIENT_PARITY_ERROR:
4599 _print_next_block((*par_num)++, "XPB");
4600 _print_parity(bp, GRCBASE_XPB +
4601 PB_REG_PB_PRTY_STS);
4614 static bool bnx2x_check_blocks_with_parity1(struct bnx2x *bp, u32 sig,
4615 int *par_num, bool *global,
4624 for (i = 0; sig; i++) {
4625 cur_bit = (0x1UL << i);
4626 if (sig & cur_bit) {
4627 res |= true; /* Each bit is real error! */
4629 case AEU_INPUTS_ATTN_BITS_PBF_PARITY_ERROR:
4631 _print_next_block((*par_num)++, "PBF");
4632 _print_parity(bp, PBF_REG_PBF_PRTY_STS);
4635 case AEU_INPUTS_ATTN_BITS_QM_PARITY_ERROR:
4637 _print_next_block((*par_num)++, "QM");
4638 _print_parity(bp, QM_REG_QM_PRTY_STS);
4641 case AEU_INPUTS_ATTN_BITS_TIMERS_PARITY_ERROR:
4643 _print_next_block((*par_num)++, "TM");
4644 _print_parity(bp, TM_REG_TM_PRTY_STS);
4647 case AEU_INPUTS_ATTN_BITS_XSDM_PARITY_ERROR:
4649 _print_next_block((*par_num)++, "XSDM");
4651 XSDM_REG_XSDM_PRTY_STS);
4654 case AEU_INPUTS_ATTN_BITS_XCM_PARITY_ERROR:
4656 _print_next_block((*par_num)++, "XCM");
4657 _print_parity(bp, XCM_REG_XCM_PRTY_STS);
4660 case AEU_INPUTS_ATTN_BITS_XSEMI_PARITY_ERROR:
4662 _print_next_block((*par_num)++,
4665 XSEM_REG_XSEM_PRTY_STS_0);
4667 XSEM_REG_XSEM_PRTY_STS_1);
4670 case AEU_INPUTS_ATTN_BITS_DOORBELLQ_PARITY_ERROR:
4672 _print_next_block((*par_num)++,
4675 DORQ_REG_DORQ_PRTY_STS);
4678 case AEU_INPUTS_ATTN_BITS_NIG_PARITY_ERROR:
4680 _print_next_block((*par_num)++, "NIG");
4681 if (CHIP_IS_E1x(bp)) {
4683 NIG_REG_NIG_PRTY_STS);
4686 NIG_REG_NIG_PRTY_STS_0);
4688 NIG_REG_NIG_PRTY_STS_1);
4692 case AEU_INPUTS_ATTN_BITS_VAUX_PCI_CORE_PARITY_ERROR:
4694 _print_next_block((*par_num)++,
4698 case AEU_INPUTS_ATTN_BITS_DEBUG_PARITY_ERROR:
4700 _print_next_block((*par_num)++,
4702 _print_parity(bp, DBG_REG_DBG_PRTY_STS);
4705 case AEU_INPUTS_ATTN_BITS_USDM_PARITY_ERROR:
4707 _print_next_block((*par_num)++, "USDM");
4709 USDM_REG_USDM_PRTY_STS);
4712 case AEU_INPUTS_ATTN_BITS_UCM_PARITY_ERROR:
4714 _print_next_block((*par_num)++, "UCM");
4715 _print_parity(bp, UCM_REG_UCM_PRTY_STS);
4718 case AEU_INPUTS_ATTN_BITS_USEMI_PARITY_ERROR:
4720 _print_next_block((*par_num)++,
4723 USEM_REG_USEM_PRTY_STS_0);
4725 USEM_REG_USEM_PRTY_STS_1);
4728 case AEU_INPUTS_ATTN_BITS_UPB_PARITY_ERROR:
4730 _print_next_block((*par_num)++, "UPB");
4731 _print_parity(bp, GRCBASE_UPB +
4732 PB_REG_PB_PRTY_STS);
4735 case AEU_INPUTS_ATTN_BITS_CSDM_PARITY_ERROR:
4737 _print_next_block((*par_num)++, "CSDM");
4739 CSDM_REG_CSDM_PRTY_STS);
4742 case AEU_INPUTS_ATTN_BITS_CCM_PARITY_ERROR:
4744 _print_next_block((*par_num)++, "CCM");
4745 _print_parity(bp, CCM_REG_CCM_PRTY_STS);
4758 static bool bnx2x_check_blocks_with_parity2(struct bnx2x *bp, u32 sig,
4759 int *par_num, bool print)
4767 for (i = 0; sig; i++) {
4768 cur_bit = (0x1UL << i);
4769 if (sig & cur_bit) {
4770 res = true; /* Each bit is real error! */
4773 case AEU_INPUTS_ATTN_BITS_CSEMI_PARITY_ERROR:
4774 _print_next_block((*par_num)++,
4777 CSEM_REG_CSEM_PRTY_STS_0);
4779 CSEM_REG_CSEM_PRTY_STS_1);
4781 case AEU_INPUTS_ATTN_BITS_PXP_PARITY_ERROR:
4782 _print_next_block((*par_num)++, "PXP");
4783 _print_parity(bp, PXP_REG_PXP_PRTY_STS);
4785 PXP2_REG_PXP2_PRTY_STS_0);
4787 PXP2_REG_PXP2_PRTY_STS_1);
4789 case AEU_IN_ATTN_BITS_PXPPCICLOCKCLIENT_PARITY_ERROR:
4790 _print_next_block((*par_num)++,
4791 "PXPPCICLOCKCLIENT");
4793 case AEU_INPUTS_ATTN_BITS_CFC_PARITY_ERROR:
4794 _print_next_block((*par_num)++, "CFC");
4796 CFC_REG_CFC_PRTY_STS);
4798 case AEU_INPUTS_ATTN_BITS_CDU_PARITY_ERROR:
4799 _print_next_block((*par_num)++, "CDU");
4800 _print_parity(bp, CDU_REG_CDU_PRTY_STS);
4802 case AEU_INPUTS_ATTN_BITS_DMAE_PARITY_ERROR:
4803 _print_next_block((*par_num)++, "DMAE");
4805 DMAE_REG_DMAE_PRTY_STS);
4807 case AEU_INPUTS_ATTN_BITS_IGU_PARITY_ERROR:
4808 _print_next_block((*par_num)++, "IGU");
4809 if (CHIP_IS_E1x(bp))
4811 HC_REG_HC_PRTY_STS);
4814 IGU_REG_IGU_PRTY_STS);
4816 case AEU_INPUTS_ATTN_BITS_MISC_PARITY_ERROR:
4817 _print_next_block((*par_num)++, "MISC");
4819 MISC_REG_MISC_PRTY_STS);
4832 static bool bnx2x_check_blocks_with_parity3(struct bnx2x *bp, u32 sig,
4833 int *par_num, bool *global,
4840 for (i = 0; sig; i++) {
4841 cur_bit = (0x1UL << i);
4842 if (sig & cur_bit) {
4844 case AEU_INPUTS_ATTN_BITS_MCP_LATCHED_ROM_PARITY:
4846 _print_next_block((*par_num)++,
4851 case AEU_INPUTS_ATTN_BITS_MCP_LATCHED_UMP_RX_PARITY:
4853 _print_next_block((*par_num)++,
4858 case AEU_INPUTS_ATTN_BITS_MCP_LATCHED_UMP_TX_PARITY:
4860 _print_next_block((*par_num)++,
4865 case AEU_INPUTS_ATTN_BITS_MCP_LATCHED_SCPAD_PARITY:
4867 _print_next_block((*par_num)++,
4869 /* clear latched SCPAD PATIRY from MCP */
4870 REG_WR(bp, MISC_REG_AEU_CLR_LATCH_SIGNAL,
4883 static bool bnx2x_check_blocks_with_parity4(struct bnx2x *bp, u32 sig,
4884 int *par_num, bool print)
4892 for (i = 0; sig; i++) {
4893 cur_bit = (0x1UL << i);
4894 if (sig & cur_bit) {
4895 res = true; /* Each bit is real error! */
4898 case AEU_INPUTS_ATTN_BITS_PGLUE_PARITY_ERROR:
4899 _print_next_block((*par_num)++,
4902 PGLUE_B_REG_PGLUE_B_PRTY_STS);
4904 case AEU_INPUTS_ATTN_BITS_ATC_PARITY_ERROR:
4905 _print_next_block((*par_num)++, "ATC");
4907 ATC_REG_ATC_PRTY_STS);
4919 static bool bnx2x_parity_attn(struct bnx2x *bp, bool *global, bool print,
4924 if ((sig[0] & HW_PRTY_ASSERT_SET_0) ||
4925 (sig[1] & HW_PRTY_ASSERT_SET_1) ||
4926 (sig[2] & HW_PRTY_ASSERT_SET_2) ||
4927 (sig[3] & HW_PRTY_ASSERT_SET_3) ||
4928 (sig[4] & HW_PRTY_ASSERT_SET_4)) {
4930 DP(NETIF_MSG_HW, "Was parity error: HW block parity attention:\n"
4931 "[0]:0x%08x [1]:0x%08x [2]:0x%08x [3]:0x%08x [4]:0x%08x\n",
4932 sig[0] & HW_PRTY_ASSERT_SET_0,
4933 sig[1] & HW_PRTY_ASSERT_SET_1,
4934 sig[2] & HW_PRTY_ASSERT_SET_2,
4935 sig[3] & HW_PRTY_ASSERT_SET_3,
4936 sig[4] & HW_PRTY_ASSERT_SET_4);
4939 "Parity errors detected in blocks: ");
4940 res |= bnx2x_check_blocks_with_parity0(bp,
4941 sig[0] & HW_PRTY_ASSERT_SET_0, &par_num, print);
4942 res |= bnx2x_check_blocks_with_parity1(bp,
4943 sig[1] & HW_PRTY_ASSERT_SET_1, &par_num, global, print);
4944 res |= bnx2x_check_blocks_with_parity2(bp,
4945 sig[2] & HW_PRTY_ASSERT_SET_2, &par_num, print);
4946 res |= bnx2x_check_blocks_with_parity3(bp,
4947 sig[3] & HW_PRTY_ASSERT_SET_3, &par_num, global, print);
4948 res |= bnx2x_check_blocks_with_parity4(bp,
4949 sig[4] & HW_PRTY_ASSERT_SET_4, &par_num, print);
4959 * bnx2x_chk_parity_attn - checks for parity attentions.
4961 * @bp: driver handle
4962 * @global: true if there was a global attention
4963 * @print: show parity attention in syslog
4965 bool bnx2x_chk_parity_attn(struct bnx2x *bp, bool *global, bool print)
4967 struct attn_route attn = { {0} };
4968 int port = BP_PORT(bp);
4970 attn.sig[0] = REG_RD(bp,
4971 MISC_REG_AEU_AFTER_INVERT_1_FUNC_0 +
4973 attn.sig[1] = REG_RD(bp,
4974 MISC_REG_AEU_AFTER_INVERT_2_FUNC_0 +
4976 attn.sig[2] = REG_RD(bp,
4977 MISC_REG_AEU_AFTER_INVERT_3_FUNC_0 +
4979 attn.sig[3] = REG_RD(bp,
4980 MISC_REG_AEU_AFTER_INVERT_4_FUNC_0 +
4982 /* Since MCP attentions can't be disabled inside the block, we need to
4983 * read AEU registers to see whether they're currently disabled
4985 attn.sig[3] &= ((REG_RD(bp,
4986 !port ? MISC_REG_AEU_ENABLE4_FUNC_0_OUT_0
4987 : MISC_REG_AEU_ENABLE4_FUNC_1_OUT_0) &
4988 MISC_AEU_ENABLE_MCP_PRTY_BITS) |
4989 ~MISC_AEU_ENABLE_MCP_PRTY_BITS);
4991 if (!CHIP_IS_E1x(bp))
4992 attn.sig[4] = REG_RD(bp,
4993 MISC_REG_AEU_AFTER_INVERT_5_FUNC_0 +
4996 return bnx2x_parity_attn(bp, global, print, attn.sig);
4999 static void bnx2x_attn_int_deasserted4(struct bnx2x *bp, u32 attn)
5002 if (attn & AEU_INPUTS_ATTN_BITS_PGLUE_HW_INTERRUPT) {
5004 val = REG_RD(bp, PGLUE_B_REG_PGLUE_B_INT_STS_CLR);
5005 BNX2X_ERR("PGLUE hw attention 0x%x\n", val);
5006 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_ADDRESS_ERROR)
5007 BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_ADDRESS_ERROR\n");
5008 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_INCORRECT_RCV_BEHAVIOR)
5009 BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_INCORRECT_RCV_BEHAVIOR\n");
5010 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_WAS_ERROR_ATTN)
5011 BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_WAS_ERROR_ATTN\n");
5012 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_VF_LENGTH_VIOLATION_ATTN)
5013 BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_VF_LENGTH_VIOLATION_ATTN\n");
5015 PGLUE_B_PGLUE_B_INT_STS_REG_VF_GRC_SPACE_VIOLATION_ATTN)
5016 BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_VF_GRC_SPACE_VIOLATION_ATTN\n");
5018 PGLUE_B_PGLUE_B_INT_STS_REG_VF_MSIX_BAR_VIOLATION_ATTN)
5019 BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_VF_MSIX_BAR_VIOLATION_ATTN\n");
5020 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_TCPL_ERROR_ATTN)
5021 BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_TCPL_ERROR_ATTN\n");
5022 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_TCPL_IN_TWO_RCBS_ATTN)
5023 BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_TCPL_IN_TWO_RCBS_ATTN\n");
5024 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_CSSNOOP_FIFO_OVERFLOW)
5025 BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_CSSNOOP_FIFO_OVERFLOW\n");
5027 if (attn & AEU_INPUTS_ATTN_BITS_ATC_HW_INTERRUPT) {
5028 val = REG_RD(bp, ATC_REG_ATC_INT_STS_CLR);
5029 BNX2X_ERR("ATC hw attention 0x%x\n", val);
5030 if (val & ATC_ATC_INT_STS_REG_ADDRESS_ERROR)
5031 BNX2X_ERR("ATC_ATC_INT_STS_REG_ADDRESS_ERROR\n");
5032 if (val & ATC_ATC_INT_STS_REG_ATC_TCPL_TO_NOT_PEND)
5033 BNX2X_ERR("ATC_ATC_INT_STS_REG_ATC_TCPL_TO_NOT_PEND\n");
5034 if (val & ATC_ATC_INT_STS_REG_ATC_GPA_MULTIPLE_HITS)
5035 BNX2X_ERR("ATC_ATC_INT_STS_REG_ATC_GPA_MULTIPLE_HITS\n");
5036 if (val & ATC_ATC_INT_STS_REG_ATC_RCPL_TO_EMPTY_CNT)
5037 BNX2X_ERR("ATC_ATC_INT_STS_REG_ATC_RCPL_TO_EMPTY_CNT\n");
5038 if (val & ATC_ATC_INT_STS_REG_ATC_TCPL_ERROR)
5039 BNX2X_ERR("ATC_ATC_INT_STS_REG_ATC_TCPL_ERROR\n");
5040 if (val & ATC_ATC_INT_STS_REG_ATC_IREQ_LESS_THAN_STU)
5041 BNX2X_ERR("ATC_ATC_INT_STS_REG_ATC_IREQ_LESS_THAN_STU\n");
5044 if (attn & (AEU_INPUTS_ATTN_BITS_PGLUE_PARITY_ERROR |
5045 AEU_INPUTS_ATTN_BITS_ATC_PARITY_ERROR)) {
5046 BNX2X_ERR("FATAL parity attention set4 0x%x\n",
5047 (u32)(attn & (AEU_INPUTS_ATTN_BITS_PGLUE_PARITY_ERROR |
5048 AEU_INPUTS_ATTN_BITS_ATC_PARITY_ERROR)));
5052 static void bnx2x_attn_int_deasserted(struct bnx2x *bp, u32 deasserted)
5054 struct attn_route attn, *group_mask;
5055 int port = BP_PORT(bp);
5060 bool global = false;
5062 /* need to take HW lock because MCP or other port might also
5063 try to handle this event */
5064 bnx2x_acquire_alr(bp);
5066 if (bnx2x_chk_parity_attn(bp, &global, true)) {
5067 #ifndef BNX2X_STOP_ON_ERROR
5068 bp->recovery_state = BNX2X_RECOVERY_INIT;
5069 schedule_delayed_work(&bp->sp_rtnl_task, 0);
5070 /* Disable HW interrupts */
5071 bnx2x_int_disable(bp);
5072 /* In case of parity errors don't handle attentions so that
5073 * other function would "see" parity errors.
5078 bnx2x_release_alr(bp);
5082 attn.sig[0] = REG_RD(bp, MISC_REG_AEU_AFTER_INVERT_1_FUNC_0 + port*4);
5083 attn.sig[1] = REG_RD(bp, MISC_REG_AEU_AFTER_INVERT_2_FUNC_0 + port*4);
5084 attn.sig[2] = REG_RD(bp, MISC_REG_AEU_AFTER_INVERT_3_FUNC_0 + port*4);
5085 attn.sig[3] = REG_RD(bp, MISC_REG_AEU_AFTER_INVERT_4_FUNC_0 + port*4);
5086 if (!CHIP_IS_E1x(bp))
5088 REG_RD(bp, MISC_REG_AEU_AFTER_INVERT_5_FUNC_0 + port*4);
5092 DP(NETIF_MSG_HW, "attn: %08x %08x %08x %08x %08x\n",
5093 attn.sig[0], attn.sig[1], attn.sig[2], attn.sig[3], attn.sig[4]);
5095 for (index = 0; index < MAX_DYNAMIC_ATTN_GRPS; index++) {
5096 if (deasserted & (1 << index)) {
5097 group_mask = &bp->attn_group[index];
5099 DP(NETIF_MSG_HW, "group[%d]: %08x %08x %08x %08x %08x\n",
5101 group_mask->sig[0], group_mask->sig[1],
5102 group_mask->sig[2], group_mask->sig[3],
5103 group_mask->sig[4]);
5105 bnx2x_attn_int_deasserted4(bp,
5106 attn.sig[4] & group_mask->sig[4]);
5107 bnx2x_attn_int_deasserted3(bp,
5108 attn.sig[3] & group_mask->sig[3]);
5109 bnx2x_attn_int_deasserted1(bp,
5110 attn.sig[1] & group_mask->sig[1]);
5111 bnx2x_attn_int_deasserted2(bp,
5112 attn.sig[2] & group_mask->sig[2]);
5113 bnx2x_attn_int_deasserted0(bp,
5114 attn.sig[0] & group_mask->sig[0]);
5118 bnx2x_release_alr(bp);
5120 if (bp->common.int_block == INT_BLOCK_HC)
5121 reg_addr = (HC_REG_COMMAND_REG + port*32 +
5122 COMMAND_REG_ATTN_BITS_CLR);
5124 reg_addr = (BAR_IGU_INTMEM + IGU_CMD_ATTN_BIT_CLR_UPPER*8);
5127 DP(NETIF_MSG_HW, "about to mask 0x%08x at %s addr 0x%x\n", val,
5128 (bp->common.int_block == INT_BLOCK_HC) ? "HC" : "IGU", reg_addr);
5129 REG_WR(bp, reg_addr, val);
5131 if (~bp->attn_state & deasserted)
5132 BNX2X_ERR("IGU ERROR\n");
5134 reg_addr = port ? MISC_REG_AEU_MASK_ATTN_FUNC_1 :
5135 MISC_REG_AEU_MASK_ATTN_FUNC_0;
5137 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_PORT0_ATT_MASK + port);
5138 aeu_mask = REG_RD(bp, reg_addr);
5140 DP(NETIF_MSG_HW, "aeu_mask %x newly deasserted %x\n",
5141 aeu_mask, deasserted);
5142 aeu_mask |= (deasserted & 0x3ff);
5143 DP(NETIF_MSG_HW, "new mask %x\n", aeu_mask);
5145 REG_WR(bp, reg_addr, aeu_mask);
5146 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_PORT0_ATT_MASK + port);
5148 DP(NETIF_MSG_HW, "attn_state %x\n", bp->attn_state);
5149 bp->attn_state &= ~deasserted;
5150 DP(NETIF_MSG_HW, "new state %x\n", bp->attn_state);
5153 static void bnx2x_attn_int(struct bnx2x *bp)
5155 /* read local copy of bits */
5156 u32 attn_bits = le32_to_cpu(bp->def_status_blk->atten_status_block.
5158 u32 attn_ack = le32_to_cpu(bp->def_status_blk->atten_status_block.
5160 u32 attn_state = bp->attn_state;
5162 /* look for changed bits */
5163 u32 asserted = attn_bits & ~attn_ack & ~attn_state;
5164 u32 deasserted = ~attn_bits & attn_ack & attn_state;
5167 "attn_bits %x attn_ack %x asserted %x deasserted %x\n",
5168 attn_bits, attn_ack, asserted, deasserted);
5170 if (~(attn_bits ^ attn_ack) & (attn_bits ^ attn_state))
5171 BNX2X_ERR("BAD attention state\n");
5173 /* handle bits that were raised */
5175 bnx2x_attn_int_asserted(bp, asserted);
5178 bnx2x_attn_int_deasserted(bp, deasserted);
5181 void bnx2x_igu_ack_sb(struct bnx2x *bp, u8 igu_sb_id, u8 segment,
5182 u16 index, u8 op, u8 update)
5184 u32 igu_addr = bp->igu_base_addr;
5185 igu_addr += (IGU_CMD_INT_ACK_BASE + igu_sb_id)*8;
5186 bnx2x_igu_ack_sb_gen(bp, igu_sb_id, segment, index, op, update,
5190 static void bnx2x_update_eq_prod(struct bnx2x *bp, u16 prod)
5192 /* No memory barriers */
5193 storm_memset_eq_prod(bp, prod, BP_FUNC(bp));
5194 mmiowb(); /* keep prod updates ordered */
5197 static int bnx2x_cnic_handle_cfc_del(struct bnx2x *bp, u32 cid,
5198 union event_ring_elem *elem)
5200 u8 err = elem->message.error;
5202 if (!bp->cnic_eth_dev.starting_cid ||
5203 (cid < bp->cnic_eth_dev.starting_cid &&
5204 cid != bp->cnic_eth_dev.iscsi_l2_cid))
5207 DP(BNX2X_MSG_SP, "got delete ramrod for CNIC CID %d\n", cid);
5209 if (unlikely(err)) {
5211 BNX2X_ERR("got delete ramrod for CNIC CID %d with error!\n",
5213 bnx2x_panic_dump(bp, false);
5215 bnx2x_cnic_cfc_comp(bp, cid, err);
5219 static void bnx2x_handle_mcast_eqe(struct bnx2x *bp)
5221 struct bnx2x_mcast_ramrod_params rparam;
5224 memset(&rparam, 0, sizeof(rparam));
5226 rparam.mcast_obj = &bp->mcast_obj;
5228 netif_addr_lock_bh(bp->dev);
5230 /* Clear pending state for the last command */
5231 bp->mcast_obj.raw.clear_pending(&bp->mcast_obj.raw);
5233 /* If there are pending mcast commands - send them */
5234 if (bp->mcast_obj.check_pending(&bp->mcast_obj)) {
5235 rc = bnx2x_config_mcast(bp, &rparam, BNX2X_MCAST_CMD_CONT);
5237 BNX2X_ERR("Failed to send pending mcast commands: %d\n",
5241 netif_addr_unlock_bh(bp->dev);
5244 static void bnx2x_handle_classification_eqe(struct bnx2x *bp,
5245 union event_ring_elem *elem)
5247 unsigned long ramrod_flags = 0;
5249 u32 cid = elem->message.data.eth_event.echo & BNX2X_SWCID_MASK;
5250 struct bnx2x_vlan_mac_obj *vlan_mac_obj;
5252 /* Always push next commands out, don't wait here */
5253 __set_bit(RAMROD_CONT, &ramrod_flags);
5255 switch (le32_to_cpu((__force __le32)elem->message.data.eth_event.echo)
5256 >> BNX2X_SWCID_SHIFT) {
5257 case BNX2X_FILTER_MAC_PENDING:
5258 DP(BNX2X_MSG_SP, "Got SETUP_MAC completions\n");
5259 if (CNIC_LOADED(bp) && (cid == BNX2X_ISCSI_ETH_CID(bp)))
5260 vlan_mac_obj = &bp->iscsi_l2_mac_obj;
5262 vlan_mac_obj = &bp->sp_objs[cid].mac_obj;
5265 case BNX2X_FILTER_MCAST_PENDING:
5266 DP(BNX2X_MSG_SP, "Got SETUP_MCAST completions\n");
5267 /* This is only relevant for 57710 where multicast MACs are
5268 * configured as unicast MACs using the same ramrod.
5270 bnx2x_handle_mcast_eqe(bp);
5273 BNX2X_ERR("Unsupported classification command: %d\n",
5274 elem->message.data.eth_event.echo);
5278 rc = vlan_mac_obj->complete(bp, vlan_mac_obj, elem, &ramrod_flags);
5281 BNX2X_ERR("Failed to schedule new commands: %d\n", rc);
5283 DP(BNX2X_MSG_SP, "Scheduled next pending commands...\n");
5286 static void bnx2x_set_iscsi_eth_rx_mode(struct bnx2x *bp, bool start);
5288 static void bnx2x_handle_rx_mode_eqe(struct bnx2x *bp)
5290 netif_addr_lock_bh(bp->dev);
5292 clear_bit(BNX2X_FILTER_RX_MODE_PENDING, &bp->sp_state);
5294 /* Send rx_mode command again if was requested */
5295 if (test_and_clear_bit(BNX2X_FILTER_RX_MODE_SCHED, &bp->sp_state))
5296 bnx2x_set_storm_rx_mode(bp);
5297 else if (test_and_clear_bit(BNX2X_FILTER_ISCSI_ETH_START_SCHED,
5299 bnx2x_set_iscsi_eth_rx_mode(bp, true);
5300 else if (test_and_clear_bit(BNX2X_FILTER_ISCSI_ETH_STOP_SCHED,
5302 bnx2x_set_iscsi_eth_rx_mode(bp, false);
5304 netif_addr_unlock_bh(bp->dev);
5307 static void bnx2x_after_afex_vif_lists(struct bnx2x *bp,
5308 union event_ring_elem *elem)
5310 if (elem->message.data.vif_list_event.echo == VIF_LIST_RULE_GET) {
5312 "afex: ramrod completed VIF LIST_GET, addrs 0x%x\n",
5313 elem->message.data.vif_list_event.func_bit_map);
5314 bnx2x_fw_command(bp, DRV_MSG_CODE_AFEX_LISTGET_ACK,
5315 elem->message.data.vif_list_event.func_bit_map);
5316 } else if (elem->message.data.vif_list_event.echo ==
5317 VIF_LIST_RULE_SET) {
5318 DP(BNX2X_MSG_SP, "afex: ramrod completed VIF LIST_SET\n");
5319 bnx2x_fw_command(bp, DRV_MSG_CODE_AFEX_LISTSET_ACK, 0);
5323 /* called with rtnl_lock */
5324 static void bnx2x_after_function_update(struct bnx2x *bp)
5327 struct bnx2x_fastpath *fp;
5328 struct bnx2x_queue_state_params queue_params = {NULL};
5329 struct bnx2x_queue_update_params *q_update_params =
5330 &queue_params.params.update;
5332 /* Send Q update command with afex vlan removal values for all Qs */
5333 queue_params.cmd = BNX2X_Q_CMD_UPDATE;
5335 /* set silent vlan removal values according to vlan mode */
5336 __set_bit(BNX2X_Q_UPDATE_SILENT_VLAN_REM_CHNG,
5337 &q_update_params->update_flags);
5338 __set_bit(BNX2X_Q_UPDATE_SILENT_VLAN_REM,
5339 &q_update_params->update_flags);
5340 __set_bit(RAMROD_COMP_WAIT, &queue_params.ramrod_flags);
5342 /* in access mode mark mask and value are 0 to strip all vlans */
5343 if (bp->afex_vlan_mode == FUNC_MF_CFG_AFEX_VLAN_ACCESS_MODE) {
5344 q_update_params->silent_removal_value = 0;
5345 q_update_params->silent_removal_mask = 0;
5347 q_update_params->silent_removal_value =
5348 (bp->afex_def_vlan_tag & VLAN_VID_MASK);
5349 q_update_params->silent_removal_mask = VLAN_VID_MASK;
5352 for_each_eth_queue(bp, q) {
5353 /* Set the appropriate Queue object */
5355 queue_params.q_obj = &bnx2x_sp_obj(bp, fp).q_obj;
5357 /* send the ramrod */
5358 rc = bnx2x_queue_state_change(bp, &queue_params);
5360 BNX2X_ERR("Failed to config silent vlan rem for Q %d\n",
5364 if (!NO_FCOE(bp) && CNIC_ENABLED(bp)) {
5365 fp = &bp->fp[FCOE_IDX(bp)];
5366 queue_params.q_obj = &bnx2x_sp_obj(bp, fp).q_obj;
5368 /* clear pending completion bit */
5369 __clear_bit(RAMROD_COMP_WAIT, &queue_params.ramrod_flags);
5371 /* mark latest Q bit */
5372 smp_mb__before_atomic();
5373 set_bit(BNX2X_AFEX_FCOE_Q_UPDATE_PENDING, &bp->sp_state);
5374 smp_mb__after_atomic();
5376 /* send Q update ramrod for FCoE Q */
5377 rc = bnx2x_queue_state_change(bp, &queue_params);
5379 BNX2X_ERR("Failed to config silent vlan rem for Q %d\n",
5382 /* If no FCoE ring - ACK MCP now */
5383 bnx2x_link_report(bp);
5384 bnx2x_fw_command(bp, DRV_MSG_CODE_AFEX_VIFSET_ACK, 0);
5388 static struct bnx2x_queue_sp_obj *bnx2x_cid_to_q_obj(
5389 struct bnx2x *bp, u32 cid)
5391 DP(BNX2X_MSG_SP, "retrieving fp from cid %d\n", cid);
5393 if (CNIC_LOADED(bp) && (cid == BNX2X_FCOE_ETH_CID(bp)))
5394 return &bnx2x_fcoe_sp_obj(bp, q_obj);
5396 return &bp->sp_objs[CID_TO_FP(cid, bp)].q_obj;
5399 static void bnx2x_eq_int(struct bnx2x *bp)
5401 u16 hw_cons, sw_cons, sw_prod;
5402 union event_ring_elem *elem;
5406 int rc, spqe_cnt = 0;
5407 struct bnx2x_queue_sp_obj *q_obj;
5408 struct bnx2x_func_sp_obj *f_obj = &bp->func_obj;
5409 struct bnx2x_raw_obj *rss_raw = &bp->rss_conf_obj.raw;
5411 hw_cons = le16_to_cpu(*bp->eq_cons_sb);
5413 /* The hw_cos range is 1-255, 257 - the sw_cons range is 0-254, 256.
5414 * when we get the next-page we need to adjust so the loop
5415 * condition below will be met. The next element is the size of a
5416 * regular element and hence incrementing by 1
5418 if ((hw_cons & EQ_DESC_MAX_PAGE) == EQ_DESC_MAX_PAGE)
5421 /* This function may never run in parallel with itself for a
5422 * specific bp, thus there is no need in "paired" read memory
5425 sw_cons = bp->eq_cons;
5426 sw_prod = bp->eq_prod;
5428 DP(BNX2X_MSG_SP, "EQ: hw_cons %u sw_cons %u bp->eq_spq_left %x\n",
5429 hw_cons, sw_cons, atomic_read(&bp->eq_spq_left));
5431 for (; sw_cons != hw_cons;
5432 sw_prod = NEXT_EQ_IDX(sw_prod), sw_cons = NEXT_EQ_IDX(sw_cons)) {
5434 elem = &bp->eq_ring[EQ_DESC(sw_cons)];
5436 rc = bnx2x_iov_eq_sp_event(bp, elem);
5438 DP(BNX2X_MSG_IOV, "bnx2x_iov_eq_sp_event returned %d\n",
5443 /* elem CID originates from FW; actually LE */
5444 cid = SW_CID((__force __le32)
5445 elem->message.data.cfc_del_event.cid);
5446 opcode = elem->message.opcode;
5448 /* handle eq element */
5450 case EVENT_RING_OPCODE_VF_PF_CHANNEL:
5451 bnx2x_vf_mbx_schedule(bp,
5452 &elem->message.data.vf_pf_event);
5455 case EVENT_RING_OPCODE_STAT_QUERY:
5456 DP_AND((BNX2X_MSG_SP | BNX2X_MSG_STATS),
5457 "got statistics comp event %d\n",
5459 /* nothing to do with stats comp */
5462 case EVENT_RING_OPCODE_CFC_DEL:
5463 /* handle according to cid range */
5465 * we may want to verify here that the bp state is
5469 "got delete ramrod for MULTI[%d]\n", cid);
5471 if (CNIC_LOADED(bp) &&
5472 !bnx2x_cnic_handle_cfc_del(bp, cid, elem))
5475 q_obj = bnx2x_cid_to_q_obj(bp, cid);
5477 if (q_obj->complete_cmd(bp, q_obj, BNX2X_Q_CMD_CFC_DEL))
5482 case EVENT_RING_OPCODE_STOP_TRAFFIC:
5483 DP(BNX2X_MSG_SP | BNX2X_MSG_DCB, "got STOP TRAFFIC\n");
5484 bnx2x_dcbx_set_params(bp, BNX2X_DCBX_STATE_TX_PAUSED);
5485 if (f_obj->complete_cmd(bp, f_obj,
5486 BNX2X_F_CMD_TX_STOP))
5490 case EVENT_RING_OPCODE_START_TRAFFIC:
5491 DP(BNX2X_MSG_SP | BNX2X_MSG_DCB, "got START TRAFFIC\n");
5492 bnx2x_dcbx_set_params(bp, BNX2X_DCBX_STATE_TX_RELEASED);
5493 if (f_obj->complete_cmd(bp, f_obj,
5494 BNX2X_F_CMD_TX_START))
5498 case EVENT_RING_OPCODE_FUNCTION_UPDATE:
5499 echo = elem->message.data.function_update_event.echo;
5500 if (echo == SWITCH_UPDATE) {
5501 DP(BNX2X_MSG_SP | NETIF_MSG_IFUP,
5502 "got FUNC_SWITCH_UPDATE ramrod\n");
5503 if (f_obj->complete_cmd(
5504 bp, f_obj, BNX2X_F_CMD_SWITCH_UPDATE))
5508 int cmd = BNX2X_SP_RTNL_AFEX_F_UPDATE;
5510 DP(BNX2X_MSG_SP | BNX2X_MSG_MCP,
5511 "AFEX: ramrod completed FUNCTION_UPDATE\n");
5512 f_obj->complete_cmd(bp, f_obj,
5513 BNX2X_F_CMD_AFEX_UPDATE);
5515 /* We will perform the Queues update from
5516 * sp_rtnl task as all Queue SP operations
5517 * should run under rtnl_lock.
5519 bnx2x_schedule_sp_rtnl(bp, cmd, 0);
5524 case EVENT_RING_OPCODE_AFEX_VIF_LISTS:
5525 f_obj->complete_cmd(bp, f_obj,
5526 BNX2X_F_CMD_AFEX_VIFLISTS);
5527 bnx2x_after_afex_vif_lists(bp, elem);
5529 case EVENT_RING_OPCODE_FUNCTION_START:
5530 DP(BNX2X_MSG_SP | NETIF_MSG_IFUP,
5531 "got FUNC_START ramrod\n");
5532 if (f_obj->complete_cmd(bp, f_obj, BNX2X_F_CMD_START))
5537 case EVENT_RING_OPCODE_FUNCTION_STOP:
5538 DP(BNX2X_MSG_SP | NETIF_MSG_IFUP,
5539 "got FUNC_STOP ramrod\n");
5540 if (f_obj->complete_cmd(bp, f_obj, BNX2X_F_CMD_STOP))
5545 case EVENT_RING_OPCODE_SET_TIMESYNC:
5546 DP(BNX2X_MSG_SP | BNX2X_MSG_PTP,
5547 "got set_timesync ramrod completion\n");
5548 if (f_obj->complete_cmd(bp, f_obj,
5549 BNX2X_F_CMD_SET_TIMESYNC))
5554 switch (opcode | bp->state) {
5555 case (EVENT_RING_OPCODE_RSS_UPDATE_RULES |
5557 case (EVENT_RING_OPCODE_RSS_UPDATE_RULES |
5558 BNX2X_STATE_OPENING_WAIT4_PORT):
5559 cid = elem->message.data.eth_event.echo &
5561 DP(BNX2X_MSG_SP, "got RSS_UPDATE ramrod. CID %d\n",
5563 rss_raw->clear_pending(rss_raw);
5566 case (EVENT_RING_OPCODE_SET_MAC | BNX2X_STATE_OPEN):
5567 case (EVENT_RING_OPCODE_SET_MAC | BNX2X_STATE_DIAG):
5568 case (EVENT_RING_OPCODE_SET_MAC |
5569 BNX2X_STATE_CLOSING_WAIT4_HALT):
5570 case (EVENT_RING_OPCODE_CLASSIFICATION_RULES |
5572 case (EVENT_RING_OPCODE_CLASSIFICATION_RULES |
5574 case (EVENT_RING_OPCODE_CLASSIFICATION_RULES |
5575 BNX2X_STATE_CLOSING_WAIT4_HALT):
5576 DP(BNX2X_MSG_SP, "got (un)set mac ramrod\n");
5577 bnx2x_handle_classification_eqe(bp, elem);
5580 case (EVENT_RING_OPCODE_MULTICAST_RULES |
5582 case (EVENT_RING_OPCODE_MULTICAST_RULES |
5584 case (EVENT_RING_OPCODE_MULTICAST_RULES |
5585 BNX2X_STATE_CLOSING_WAIT4_HALT):
5586 DP(BNX2X_MSG_SP, "got mcast ramrod\n");
5587 bnx2x_handle_mcast_eqe(bp);
5590 case (EVENT_RING_OPCODE_FILTERS_RULES |
5592 case (EVENT_RING_OPCODE_FILTERS_RULES |
5594 case (EVENT_RING_OPCODE_FILTERS_RULES |
5595 BNX2X_STATE_CLOSING_WAIT4_HALT):
5596 DP(BNX2X_MSG_SP, "got rx_mode ramrod\n");
5597 bnx2x_handle_rx_mode_eqe(bp);
5600 /* unknown event log error and continue */
5601 BNX2X_ERR("Unknown EQ event %d, bp->state 0x%x\n",
5602 elem->message.opcode, bp->state);
5608 smp_mb__before_atomic();
5609 atomic_add(spqe_cnt, &bp->eq_spq_left);
5611 bp->eq_cons = sw_cons;
5612 bp->eq_prod = sw_prod;
5613 /* Make sure that above mem writes were issued towards the memory */
5616 /* update producer */
5617 bnx2x_update_eq_prod(bp, bp->eq_prod);
5620 static void bnx2x_sp_task(struct work_struct *work)
5622 struct bnx2x *bp = container_of(work, struct bnx2x, sp_task.work);
5624 DP(BNX2X_MSG_SP, "sp task invoked\n");
5626 /* make sure the atomic interrupt_occurred has been written */
5628 if (atomic_read(&bp->interrupt_occurred)) {
5630 /* what work needs to be performed? */
5631 u16 status = bnx2x_update_dsb_idx(bp);
5633 DP(BNX2X_MSG_SP, "status %x\n", status);
5634 DP(BNX2X_MSG_SP, "setting interrupt_occurred to 0\n");
5635 atomic_set(&bp->interrupt_occurred, 0);
5638 if (status & BNX2X_DEF_SB_ATT_IDX) {
5640 status &= ~BNX2X_DEF_SB_ATT_IDX;
5643 /* SP events: STAT_QUERY and others */
5644 if (status & BNX2X_DEF_SB_IDX) {
5645 struct bnx2x_fastpath *fp = bnx2x_fcoe_fp(bp);
5647 if (FCOE_INIT(bp) &&
5648 (bnx2x_has_rx_work(fp) || bnx2x_has_tx_work(fp))) {
5649 /* Prevent local bottom-halves from running as
5650 * we are going to change the local NAPI list.
5653 napi_schedule(&bnx2x_fcoe(bp, napi));
5657 /* Handle EQ completions */
5659 bnx2x_ack_sb(bp, bp->igu_dsb_id, USTORM_ID,
5660 le16_to_cpu(bp->def_idx), IGU_INT_NOP, 1);
5662 status &= ~BNX2X_DEF_SB_IDX;
5665 /* if status is non zero then perhaps something went wrong */
5666 if (unlikely(status))
5668 "got an unknown interrupt! (status 0x%x)\n", status);
5670 /* ack status block only if something was actually handled */
5671 bnx2x_ack_sb(bp, bp->igu_dsb_id, ATTENTION_ID,
5672 le16_to_cpu(bp->def_att_idx), IGU_INT_ENABLE, 1);
5675 /* afex - poll to check if VIFSET_ACK should be sent to MFW */
5676 if (test_and_clear_bit(BNX2X_AFEX_PENDING_VIFSET_MCP_ACK,
5678 bnx2x_link_report(bp);
5679 bnx2x_fw_command(bp, DRV_MSG_CODE_AFEX_VIFSET_ACK, 0);
5683 irqreturn_t bnx2x_msix_sp_int(int irq, void *dev_instance)
5685 struct net_device *dev = dev_instance;
5686 struct bnx2x *bp = netdev_priv(dev);
5688 bnx2x_ack_sb(bp, bp->igu_dsb_id, USTORM_ID, 0,
5689 IGU_INT_DISABLE, 0);
5691 #ifdef BNX2X_STOP_ON_ERROR
5692 if (unlikely(bp->panic))
5696 if (CNIC_LOADED(bp)) {
5697 struct cnic_ops *c_ops;
5700 c_ops = rcu_dereference(bp->cnic_ops);
5702 c_ops->cnic_handler(bp->cnic_data, NULL);
5706 /* schedule sp task to perform default status block work, ack
5707 * attentions and enable interrupts.
5709 bnx2x_schedule_sp_task(bp);
5714 /* end of slow path */
5716 void bnx2x_drv_pulse(struct bnx2x *bp)
5718 SHMEM_WR(bp, func_mb[BP_FW_MB_IDX(bp)].drv_pulse_mb,
5719 bp->fw_drv_pulse_wr_seq);
5722 static void bnx2x_timer(unsigned long data)
5724 struct bnx2x *bp = (struct bnx2x *) data;
5726 if (!netif_running(bp->dev))
5731 int mb_idx = BP_FW_MB_IDX(bp);
5735 ++bp->fw_drv_pulse_wr_seq;
5736 bp->fw_drv_pulse_wr_seq &= DRV_PULSE_SEQ_MASK;
5737 drv_pulse = bp->fw_drv_pulse_wr_seq;
5738 bnx2x_drv_pulse(bp);
5740 mcp_pulse = (SHMEM_RD(bp, func_mb[mb_idx].mcp_pulse_mb) &
5741 MCP_PULSE_SEQ_MASK);
5742 /* The delta between driver pulse and mcp response
5743 * should not get too big. If the MFW is more than 5 pulses
5744 * behind, we should worry about it enough to generate an error
5747 if (((drv_pulse - mcp_pulse) & MCP_PULSE_SEQ_MASK) > 5)
5748 BNX2X_ERR("MFW seems hanged: drv_pulse (0x%x) != mcp_pulse (0x%x)\n",
5749 drv_pulse, mcp_pulse);
5752 if (bp->state == BNX2X_STATE_OPEN)
5753 bnx2x_stats_handle(bp, STATS_EVENT_UPDATE);
5755 /* sample pf vf bulletin board for new posts from pf */
5757 bnx2x_timer_sriov(bp);
5759 mod_timer(&bp->timer, jiffies + bp->current_interval);
5762 /* end of Statistics */
5767 * nic init service functions
5770 static void bnx2x_fill(struct bnx2x *bp, u32 addr, int fill, u32 len)
5773 if (!(len%4) && !(addr%4))
5774 for (i = 0; i < len; i += 4)
5775 REG_WR(bp, addr + i, fill);
5777 for (i = 0; i < len; i++)
5778 REG_WR8(bp, addr + i, fill);
5781 /* helper: writes FP SP data to FW - data_size in dwords */
5782 static void bnx2x_wr_fp_sb_data(struct bnx2x *bp,
5788 for (index = 0; index < data_size; index++)
5789 REG_WR(bp, BAR_CSTRORM_INTMEM +
5790 CSTORM_STATUS_BLOCK_DATA_OFFSET(fw_sb_id) +
5792 *(sb_data_p + index));
5795 static void bnx2x_zero_fp_sb(struct bnx2x *bp, int fw_sb_id)
5799 struct hc_status_block_data_e2 sb_data_e2;
5800 struct hc_status_block_data_e1x sb_data_e1x;
5802 /* disable the function first */
5803 if (!CHIP_IS_E1x(bp)) {
5804 memset(&sb_data_e2, 0, sizeof(struct hc_status_block_data_e2));
5805 sb_data_e2.common.state = SB_DISABLED;
5806 sb_data_e2.common.p_func.vf_valid = false;
5807 sb_data_p = (u32 *)&sb_data_e2;
5808 data_size = sizeof(struct hc_status_block_data_e2)/sizeof(u32);
5810 memset(&sb_data_e1x, 0,
5811 sizeof(struct hc_status_block_data_e1x));
5812 sb_data_e1x.common.state = SB_DISABLED;
5813 sb_data_e1x.common.p_func.vf_valid = false;
5814 sb_data_p = (u32 *)&sb_data_e1x;
5815 data_size = sizeof(struct hc_status_block_data_e1x)/sizeof(u32);
5817 bnx2x_wr_fp_sb_data(bp, fw_sb_id, sb_data_p, data_size);
5819 bnx2x_fill(bp, BAR_CSTRORM_INTMEM +
5820 CSTORM_STATUS_BLOCK_OFFSET(fw_sb_id), 0,
5821 CSTORM_STATUS_BLOCK_SIZE);
5822 bnx2x_fill(bp, BAR_CSTRORM_INTMEM +
5823 CSTORM_SYNC_BLOCK_OFFSET(fw_sb_id), 0,
5824 CSTORM_SYNC_BLOCK_SIZE);
5827 /* helper: writes SP SB data to FW */
5828 static void bnx2x_wr_sp_sb_data(struct bnx2x *bp,
5829 struct hc_sp_status_block_data *sp_sb_data)
5831 int func = BP_FUNC(bp);
5833 for (i = 0; i < sizeof(struct hc_sp_status_block_data)/sizeof(u32); i++)
5834 REG_WR(bp, BAR_CSTRORM_INTMEM +
5835 CSTORM_SP_STATUS_BLOCK_DATA_OFFSET(func) +
5837 *((u32 *)sp_sb_data + i));
5840 static void bnx2x_zero_sp_sb(struct bnx2x *bp)
5842 int func = BP_FUNC(bp);
5843 struct hc_sp_status_block_data sp_sb_data;
5844 memset(&sp_sb_data, 0, sizeof(struct hc_sp_status_block_data));
5846 sp_sb_data.state = SB_DISABLED;
5847 sp_sb_data.p_func.vf_valid = false;
5849 bnx2x_wr_sp_sb_data(bp, &sp_sb_data);
5851 bnx2x_fill(bp, BAR_CSTRORM_INTMEM +
5852 CSTORM_SP_STATUS_BLOCK_OFFSET(func), 0,
5853 CSTORM_SP_STATUS_BLOCK_SIZE);
5854 bnx2x_fill(bp, BAR_CSTRORM_INTMEM +
5855 CSTORM_SP_SYNC_BLOCK_OFFSET(func), 0,
5856 CSTORM_SP_SYNC_BLOCK_SIZE);
5859 static void bnx2x_setup_ndsb_state_machine(struct hc_status_block_sm *hc_sm,
5860 int igu_sb_id, int igu_seg_id)
5862 hc_sm->igu_sb_id = igu_sb_id;
5863 hc_sm->igu_seg_id = igu_seg_id;
5864 hc_sm->timer_value = 0xFF;
5865 hc_sm->time_to_expire = 0xFFFFFFFF;
5868 /* allocates state machine ids. */
5869 static void bnx2x_map_sb_state_machines(struct hc_index_data *index_data)
5871 /* zero out state machine indices */
5873 index_data[HC_INDEX_ETH_RX_CQ_CONS].flags &= ~HC_INDEX_DATA_SM_ID;
5876 index_data[HC_INDEX_OOO_TX_CQ_CONS].flags &= ~HC_INDEX_DATA_SM_ID;
5877 index_data[HC_INDEX_ETH_TX_CQ_CONS_COS0].flags &= ~HC_INDEX_DATA_SM_ID;
5878 index_data[HC_INDEX_ETH_TX_CQ_CONS_COS1].flags &= ~HC_INDEX_DATA_SM_ID;
5879 index_data[HC_INDEX_ETH_TX_CQ_CONS_COS2].flags &= ~HC_INDEX_DATA_SM_ID;
5883 index_data[HC_INDEX_ETH_RX_CQ_CONS].flags |=
5884 SM_RX_ID << HC_INDEX_DATA_SM_ID_SHIFT;
5887 index_data[HC_INDEX_OOO_TX_CQ_CONS].flags |=
5888 SM_TX_ID << HC_INDEX_DATA_SM_ID_SHIFT;
5889 index_data[HC_INDEX_ETH_TX_CQ_CONS_COS0].flags |=
5890 SM_TX_ID << HC_INDEX_DATA_SM_ID_SHIFT;
5891 index_data[HC_INDEX_ETH_TX_CQ_CONS_COS1].flags |=
5892 SM_TX_ID << HC_INDEX_DATA_SM_ID_SHIFT;
5893 index_data[HC_INDEX_ETH_TX_CQ_CONS_COS2].flags |=
5894 SM_TX_ID << HC_INDEX_DATA_SM_ID_SHIFT;
5897 void bnx2x_init_sb(struct bnx2x *bp, dma_addr_t mapping, int vfid,
5898 u8 vf_valid, int fw_sb_id, int igu_sb_id)
5902 struct hc_status_block_data_e2 sb_data_e2;
5903 struct hc_status_block_data_e1x sb_data_e1x;
5904 struct hc_status_block_sm *hc_sm_p;
5908 if (CHIP_INT_MODE_IS_BC(bp))
5909 igu_seg_id = HC_SEG_ACCESS_NORM;
5911 igu_seg_id = IGU_SEG_ACCESS_NORM;
5913 bnx2x_zero_fp_sb(bp, fw_sb_id);
5915 if (!CHIP_IS_E1x(bp)) {
5916 memset(&sb_data_e2, 0, sizeof(struct hc_status_block_data_e2));
5917 sb_data_e2.common.state = SB_ENABLED;
5918 sb_data_e2.common.p_func.pf_id = BP_FUNC(bp);
5919 sb_data_e2.common.p_func.vf_id = vfid;
5920 sb_data_e2.common.p_func.vf_valid = vf_valid;
5921 sb_data_e2.common.p_func.vnic_id = BP_VN(bp);
5922 sb_data_e2.common.same_igu_sb_1b = true;
5923 sb_data_e2.common.host_sb_addr.hi = U64_HI(mapping);
5924 sb_data_e2.common.host_sb_addr.lo = U64_LO(mapping);
5925 hc_sm_p = sb_data_e2.common.state_machine;
5926 sb_data_p = (u32 *)&sb_data_e2;
5927 data_size = sizeof(struct hc_status_block_data_e2)/sizeof(u32);
5928 bnx2x_map_sb_state_machines(sb_data_e2.index_data);
5930 memset(&sb_data_e1x, 0,
5931 sizeof(struct hc_status_block_data_e1x));
5932 sb_data_e1x.common.state = SB_ENABLED;
5933 sb_data_e1x.common.p_func.pf_id = BP_FUNC(bp);
5934 sb_data_e1x.common.p_func.vf_id = 0xff;
5935 sb_data_e1x.common.p_func.vf_valid = false;
5936 sb_data_e1x.common.p_func.vnic_id = BP_VN(bp);
5937 sb_data_e1x.common.same_igu_sb_1b = true;
5938 sb_data_e1x.common.host_sb_addr.hi = U64_HI(mapping);
5939 sb_data_e1x.common.host_sb_addr.lo = U64_LO(mapping);
5940 hc_sm_p = sb_data_e1x.common.state_machine;
5941 sb_data_p = (u32 *)&sb_data_e1x;
5942 data_size = sizeof(struct hc_status_block_data_e1x)/sizeof(u32);
5943 bnx2x_map_sb_state_machines(sb_data_e1x.index_data);
5946 bnx2x_setup_ndsb_state_machine(&hc_sm_p[SM_RX_ID],
5947 igu_sb_id, igu_seg_id);
5948 bnx2x_setup_ndsb_state_machine(&hc_sm_p[SM_TX_ID],
5949 igu_sb_id, igu_seg_id);
5951 DP(NETIF_MSG_IFUP, "Init FW SB %d\n", fw_sb_id);
5953 /* write indices to HW - PCI guarantees endianity of regpairs */
5954 bnx2x_wr_fp_sb_data(bp, fw_sb_id, sb_data_p, data_size);
5957 static void bnx2x_update_coalesce_sb(struct bnx2x *bp, u8 fw_sb_id,
5958 u16 tx_usec, u16 rx_usec)
5960 bnx2x_update_coalesce_sb_index(bp, fw_sb_id, HC_INDEX_ETH_RX_CQ_CONS,
5962 bnx2x_update_coalesce_sb_index(bp, fw_sb_id,
5963 HC_INDEX_ETH_TX_CQ_CONS_COS0, false,
5965 bnx2x_update_coalesce_sb_index(bp, fw_sb_id,
5966 HC_INDEX_ETH_TX_CQ_CONS_COS1, false,
5968 bnx2x_update_coalesce_sb_index(bp, fw_sb_id,
5969 HC_INDEX_ETH_TX_CQ_CONS_COS2, false,
5973 static void bnx2x_init_def_sb(struct bnx2x *bp)
5975 struct host_sp_status_block *def_sb = bp->def_status_blk;
5976 dma_addr_t mapping = bp->def_status_blk_mapping;
5977 int igu_sp_sb_index;
5979 int port = BP_PORT(bp);
5980 int func = BP_FUNC(bp);
5981 int reg_offset, reg_offset_en5;
5984 struct hc_sp_status_block_data sp_sb_data;
5985 memset(&sp_sb_data, 0, sizeof(struct hc_sp_status_block_data));
5987 if (CHIP_INT_MODE_IS_BC(bp)) {
5988 igu_sp_sb_index = DEF_SB_IGU_ID;
5989 igu_seg_id = HC_SEG_ACCESS_DEF;
5991 igu_sp_sb_index = bp->igu_dsb_id;
5992 igu_seg_id = IGU_SEG_ACCESS_DEF;
5996 section = ((u64)mapping) + offsetof(struct host_sp_status_block,
5997 atten_status_block);
5998 def_sb->atten_status_block.status_block_id = igu_sp_sb_index;
6002 reg_offset = (port ? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_0 :
6003 MISC_REG_AEU_ENABLE1_FUNC_0_OUT_0);
6004 reg_offset_en5 = (port ? MISC_REG_AEU_ENABLE5_FUNC_1_OUT_0 :
6005 MISC_REG_AEU_ENABLE5_FUNC_0_OUT_0);
6006 for (index = 0; index < MAX_DYNAMIC_ATTN_GRPS; index++) {
6008 /* take care of sig[0]..sig[4] */
6009 for (sindex = 0; sindex < 4; sindex++)
6010 bp->attn_group[index].sig[sindex] =
6011 REG_RD(bp, reg_offset + sindex*0x4 + 0x10*index);
6013 if (!CHIP_IS_E1x(bp))
6015 * enable5 is separate from the rest of the registers,
6016 * and therefore the address skip is 4
6017 * and not 16 between the different groups
6019 bp->attn_group[index].sig[4] = REG_RD(bp,
6020 reg_offset_en5 + 0x4*index);
6022 bp->attn_group[index].sig[4] = 0;
6025 if (bp->common.int_block == INT_BLOCK_HC) {
6026 reg_offset = (port ? HC_REG_ATTN_MSG1_ADDR_L :
6027 HC_REG_ATTN_MSG0_ADDR_L);
6029 REG_WR(bp, reg_offset, U64_LO(section));
6030 REG_WR(bp, reg_offset + 4, U64_HI(section));
6031 } else if (!CHIP_IS_E1x(bp)) {
6032 REG_WR(bp, IGU_REG_ATTN_MSG_ADDR_L, U64_LO(section));
6033 REG_WR(bp, IGU_REG_ATTN_MSG_ADDR_H, U64_HI(section));
6036 section = ((u64)mapping) + offsetof(struct host_sp_status_block,
6039 bnx2x_zero_sp_sb(bp);
6041 /* PCI guarantees endianity of regpairs */
6042 sp_sb_data.state = SB_ENABLED;
6043 sp_sb_data.host_sb_addr.lo = U64_LO(section);
6044 sp_sb_data.host_sb_addr.hi = U64_HI(section);
6045 sp_sb_data.igu_sb_id = igu_sp_sb_index;
6046 sp_sb_data.igu_seg_id = igu_seg_id;
6047 sp_sb_data.p_func.pf_id = func;
6048 sp_sb_data.p_func.vnic_id = BP_VN(bp);
6049 sp_sb_data.p_func.vf_id = 0xff;
6051 bnx2x_wr_sp_sb_data(bp, &sp_sb_data);
6053 bnx2x_ack_sb(bp, bp->igu_dsb_id, USTORM_ID, 0, IGU_INT_ENABLE, 0);
6056 void bnx2x_update_coalesce(struct bnx2x *bp)
6060 for_each_eth_queue(bp, i)
6061 bnx2x_update_coalesce_sb(bp, bp->fp[i].fw_sb_id,
6062 bp->tx_ticks, bp->rx_ticks);
6065 static void bnx2x_init_sp_ring(struct bnx2x *bp)
6067 spin_lock_init(&bp->spq_lock);
6068 atomic_set(&bp->cq_spq_left, MAX_SPQ_PENDING);
6070 bp->spq_prod_idx = 0;
6071 bp->dsb_sp_prod = BNX2X_SP_DSB_INDEX;
6072 bp->spq_prod_bd = bp->spq;
6073 bp->spq_last_bd = bp->spq_prod_bd + MAX_SP_DESC_CNT;
6076 static void bnx2x_init_eq_ring(struct bnx2x *bp)
6079 for (i = 1; i <= NUM_EQ_PAGES; i++) {
6080 union event_ring_elem *elem =
6081 &bp->eq_ring[EQ_DESC_CNT_PAGE * i - 1];
6083 elem->next_page.addr.hi =
6084 cpu_to_le32(U64_HI(bp->eq_mapping +
6085 BCM_PAGE_SIZE * (i % NUM_EQ_PAGES)));
6086 elem->next_page.addr.lo =
6087 cpu_to_le32(U64_LO(bp->eq_mapping +
6088 BCM_PAGE_SIZE*(i % NUM_EQ_PAGES)));
6091 bp->eq_prod = NUM_EQ_DESC;
6092 bp->eq_cons_sb = BNX2X_EQ_INDEX;
6093 /* we want a warning message before it gets wrought... */
6094 atomic_set(&bp->eq_spq_left,
6095 min_t(int, MAX_SP_DESC_CNT - MAX_SPQ_PENDING, NUM_EQ_DESC) - 1);
6098 /* called with netif_addr_lock_bh() */
6099 static int bnx2x_set_q_rx_mode(struct bnx2x *bp, u8 cl_id,
6100 unsigned long rx_mode_flags,
6101 unsigned long rx_accept_flags,
6102 unsigned long tx_accept_flags,
6103 unsigned long ramrod_flags)
6105 struct bnx2x_rx_mode_ramrod_params ramrod_param;
6108 memset(&ramrod_param, 0, sizeof(ramrod_param));
6110 /* Prepare ramrod parameters */
6111 ramrod_param.cid = 0;
6112 ramrod_param.cl_id = cl_id;
6113 ramrod_param.rx_mode_obj = &bp->rx_mode_obj;
6114 ramrod_param.func_id = BP_FUNC(bp);
6116 ramrod_param.pstate = &bp->sp_state;
6117 ramrod_param.state = BNX2X_FILTER_RX_MODE_PENDING;
6119 ramrod_param.rdata = bnx2x_sp(bp, rx_mode_rdata);
6120 ramrod_param.rdata_mapping = bnx2x_sp_mapping(bp, rx_mode_rdata);
6122 set_bit(BNX2X_FILTER_RX_MODE_PENDING, &bp->sp_state);
6124 ramrod_param.ramrod_flags = ramrod_flags;
6125 ramrod_param.rx_mode_flags = rx_mode_flags;
6127 ramrod_param.rx_accept_flags = rx_accept_flags;
6128 ramrod_param.tx_accept_flags = tx_accept_flags;
6130 rc = bnx2x_config_rx_mode(bp, &ramrod_param);
6132 BNX2X_ERR("Set rx_mode %d failed\n", bp->rx_mode);
6139 static int bnx2x_fill_accept_flags(struct bnx2x *bp, u32 rx_mode,
6140 unsigned long *rx_accept_flags,
6141 unsigned long *tx_accept_flags)
6143 /* Clear the flags first */
6144 *rx_accept_flags = 0;
6145 *tx_accept_flags = 0;
6148 case BNX2X_RX_MODE_NONE:
6150 * 'drop all' supersedes any accept flags that may have been
6151 * passed to the function.
6154 case BNX2X_RX_MODE_NORMAL:
6155 __set_bit(BNX2X_ACCEPT_UNICAST, rx_accept_flags);
6156 __set_bit(BNX2X_ACCEPT_MULTICAST, rx_accept_flags);
6157 __set_bit(BNX2X_ACCEPT_BROADCAST, rx_accept_flags);
6159 /* internal switching mode */
6160 __set_bit(BNX2X_ACCEPT_UNICAST, tx_accept_flags);
6161 __set_bit(BNX2X_ACCEPT_MULTICAST, tx_accept_flags);
6162 __set_bit(BNX2X_ACCEPT_BROADCAST, tx_accept_flags);
6165 case BNX2X_RX_MODE_ALLMULTI:
6166 __set_bit(BNX2X_ACCEPT_UNICAST, rx_accept_flags);
6167 __set_bit(BNX2X_ACCEPT_ALL_MULTICAST, rx_accept_flags);
6168 __set_bit(BNX2X_ACCEPT_BROADCAST, rx_accept_flags);
6170 /* internal switching mode */
6171 __set_bit(BNX2X_ACCEPT_UNICAST, tx_accept_flags);
6172 __set_bit(BNX2X_ACCEPT_ALL_MULTICAST, tx_accept_flags);
6173 __set_bit(BNX2X_ACCEPT_BROADCAST, tx_accept_flags);
6176 case BNX2X_RX_MODE_PROMISC:
6177 /* According to definition of SI mode, iface in promisc mode
6178 * should receive matched and unmatched (in resolution of port)
6181 __set_bit(BNX2X_ACCEPT_UNMATCHED, rx_accept_flags);
6182 __set_bit(BNX2X_ACCEPT_UNICAST, rx_accept_flags);
6183 __set_bit(BNX2X_ACCEPT_ALL_MULTICAST, rx_accept_flags);
6184 __set_bit(BNX2X_ACCEPT_BROADCAST, rx_accept_flags);
6186 /* internal switching mode */
6187 __set_bit(BNX2X_ACCEPT_ALL_MULTICAST, tx_accept_flags);
6188 __set_bit(BNX2X_ACCEPT_BROADCAST, tx_accept_flags);
6191 __set_bit(BNX2X_ACCEPT_ALL_UNICAST, tx_accept_flags);
6193 __set_bit(BNX2X_ACCEPT_UNICAST, tx_accept_flags);
6197 BNX2X_ERR("Unknown rx_mode: %d\n", rx_mode);
6201 /* Set ACCEPT_ANY_VLAN as we do not enable filtering by VLAN */
6202 if (rx_mode != BNX2X_RX_MODE_NONE) {
6203 __set_bit(BNX2X_ACCEPT_ANY_VLAN, rx_accept_flags);
6204 __set_bit(BNX2X_ACCEPT_ANY_VLAN, tx_accept_flags);
6210 /* called with netif_addr_lock_bh() */
6211 static int bnx2x_set_storm_rx_mode(struct bnx2x *bp)
6213 unsigned long rx_mode_flags = 0, ramrod_flags = 0;
6214 unsigned long rx_accept_flags = 0, tx_accept_flags = 0;
6218 /* Configure rx_mode of FCoE Queue */
6219 __set_bit(BNX2X_RX_MODE_FCOE_ETH, &rx_mode_flags);
6221 rc = bnx2x_fill_accept_flags(bp, bp->rx_mode, &rx_accept_flags,
6226 __set_bit(RAMROD_RX, &ramrod_flags);
6227 __set_bit(RAMROD_TX, &ramrod_flags);
6229 return bnx2x_set_q_rx_mode(bp, bp->fp->cl_id, rx_mode_flags,
6230 rx_accept_flags, tx_accept_flags,
6234 static void bnx2x_init_internal_common(struct bnx2x *bp)
6238 /* Zero this manually as its initialization is
6239 currently missing in the initTool */
6240 for (i = 0; i < (USTORM_AGG_DATA_SIZE >> 2); i++)
6241 REG_WR(bp, BAR_USTRORM_INTMEM +
6242 USTORM_AGG_DATA_OFFSET + i * 4, 0);
6243 if (!CHIP_IS_E1x(bp)) {
6244 REG_WR8(bp, BAR_CSTRORM_INTMEM + CSTORM_IGU_MODE_OFFSET,
6245 CHIP_INT_MODE_IS_BC(bp) ?
6246 HC_IGU_BC_MODE : HC_IGU_NBC_MODE);
6250 static void bnx2x_init_internal(struct bnx2x *bp, u32 load_code)
6252 switch (load_code) {
6253 case FW_MSG_CODE_DRV_LOAD_COMMON:
6254 case FW_MSG_CODE_DRV_LOAD_COMMON_CHIP:
6255 bnx2x_init_internal_common(bp);
6258 case FW_MSG_CODE_DRV_LOAD_PORT:
6262 case FW_MSG_CODE_DRV_LOAD_FUNCTION:
6263 /* internal memory per function is
6264 initialized inside bnx2x_pf_init */
6268 BNX2X_ERR("Unknown load_code (0x%x) from MCP\n", load_code);
6273 static inline u8 bnx2x_fp_igu_sb_id(struct bnx2x_fastpath *fp)
6275 return fp->bp->igu_base_sb + fp->index + CNIC_SUPPORT(fp->bp);
6278 static inline u8 bnx2x_fp_fw_sb_id(struct bnx2x_fastpath *fp)
6280 return fp->bp->base_fw_ndsb + fp->index + CNIC_SUPPORT(fp->bp);
6283 static u8 bnx2x_fp_cl_id(struct bnx2x_fastpath *fp)
6285 if (CHIP_IS_E1x(fp->bp))
6286 return BP_L_ID(fp->bp) + fp->index;
6287 else /* We want Client ID to be the same as IGU SB ID for 57712 */
6288 return bnx2x_fp_igu_sb_id(fp);
6291 static void bnx2x_init_eth_fp(struct bnx2x *bp, int fp_idx)
6293 struct bnx2x_fastpath *fp = &bp->fp[fp_idx];
6295 unsigned long q_type = 0;
6296 u32 cids[BNX2X_MULTI_TX_COS] = { 0 };
6297 fp->rx_queue = fp_idx;
6299 fp->cl_id = bnx2x_fp_cl_id(fp);
6300 fp->fw_sb_id = bnx2x_fp_fw_sb_id(fp);
6301 fp->igu_sb_id = bnx2x_fp_igu_sb_id(fp);
6302 /* qZone id equals to FW (per path) client id */
6303 fp->cl_qzone_id = bnx2x_fp_qzone_id(fp);
6306 fp->ustorm_rx_prods_offset = bnx2x_rx_ustorm_prods_offset(fp);
6308 /* Setup SB indices */
6309 fp->rx_cons_sb = BNX2X_RX_SB_INDEX;
6311 /* Configure Queue State object */
6312 __set_bit(BNX2X_Q_TYPE_HAS_RX, &q_type);
6313 __set_bit(BNX2X_Q_TYPE_HAS_TX, &q_type);
6315 BUG_ON(fp->max_cos > BNX2X_MULTI_TX_COS);
6318 for_each_cos_in_tx_queue(fp, cos) {
6319 bnx2x_init_txdata(bp, fp->txdata_ptr[cos],
6320 CID_COS_TO_TX_ONLY_CID(fp->cid, cos, bp),
6321 FP_COS_TO_TXQ(fp, cos, bp),
6322 BNX2X_TX_SB_INDEX_BASE + cos, fp);
6323 cids[cos] = fp->txdata_ptr[cos]->cid;
6326 /* nothing more for vf to do here */
6330 bnx2x_init_sb(bp, fp->status_blk_mapping, BNX2X_VF_ID_INVALID, false,
6331 fp->fw_sb_id, fp->igu_sb_id);
6332 bnx2x_update_fpsb_idx(fp);
6333 bnx2x_init_queue_obj(bp, &bnx2x_sp_obj(bp, fp).q_obj, fp->cl_id, cids,
6334 fp->max_cos, BP_FUNC(bp), bnx2x_sp(bp, q_rdata),
6335 bnx2x_sp_mapping(bp, q_rdata), q_type);
6338 * Configure classification DBs: Always enable Tx switching
6340 bnx2x_init_vlan_mac_fp_objs(fp, BNX2X_OBJ_TYPE_RX_TX);
6343 "queue[%d]: bnx2x_init_sb(%p,%p) cl_id %d fw_sb %d igu_sb %d\n",
6344 fp_idx, bp, fp->status_blk.e2_sb, fp->cl_id, fp->fw_sb_id,
6348 static void bnx2x_init_tx_ring_one(struct bnx2x_fp_txdata *txdata)
6352 for (i = 1; i <= NUM_TX_RINGS; i++) {
6353 struct eth_tx_next_bd *tx_next_bd =
6354 &txdata->tx_desc_ring[TX_DESC_CNT * i - 1].next_bd;
6356 tx_next_bd->addr_hi =
6357 cpu_to_le32(U64_HI(txdata->tx_desc_mapping +
6358 BCM_PAGE_SIZE*(i % NUM_TX_RINGS)));
6359 tx_next_bd->addr_lo =
6360 cpu_to_le32(U64_LO(txdata->tx_desc_mapping +
6361 BCM_PAGE_SIZE*(i % NUM_TX_RINGS)));
6364 *txdata->tx_cons_sb = cpu_to_le16(0);
6366 SET_FLAG(txdata->tx_db.data.header.header, DOORBELL_HDR_DB_TYPE, 1);
6367 txdata->tx_db.data.zero_fill1 = 0;
6368 txdata->tx_db.data.prod = 0;
6370 txdata->tx_pkt_prod = 0;
6371 txdata->tx_pkt_cons = 0;
6372 txdata->tx_bd_prod = 0;
6373 txdata->tx_bd_cons = 0;
6377 static void bnx2x_init_tx_rings_cnic(struct bnx2x *bp)
6381 for_each_tx_queue_cnic(bp, i)
6382 bnx2x_init_tx_ring_one(bp->fp[i].txdata_ptr[0]);
6385 static void bnx2x_init_tx_rings(struct bnx2x *bp)
6390 for_each_eth_queue(bp, i)
6391 for_each_cos_in_tx_queue(&bp->fp[i], cos)
6392 bnx2x_init_tx_ring_one(bp->fp[i].txdata_ptr[cos]);
6395 static void bnx2x_init_fcoe_fp(struct bnx2x *bp)
6397 struct bnx2x_fastpath *fp = bnx2x_fcoe_fp(bp);
6398 unsigned long q_type = 0;
6400 bnx2x_fcoe(bp, rx_queue) = BNX2X_NUM_ETH_QUEUES(bp);
6401 bnx2x_fcoe(bp, cl_id) = bnx2x_cnic_eth_cl_id(bp,
6402 BNX2X_FCOE_ETH_CL_ID_IDX);
6403 bnx2x_fcoe(bp, cid) = BNX2X_FCOE_ETH_CID(bp);
6404 bnx2x_fcoe(bp, fw_sb_id) = DEF_SB_ID;
6405 bnx2x_fcoe(bp, igu_sb_id) = bp->igu_dsb_id;
6406 bnx2x_fcoe(bp, rx_cons_sb) = BNX2X_FCOE_L2_RX_INDEX;
6407 bnx2x_init_txdata(bp, bnx2x_fcoe(bp, txdata_ptr[0]),
6408 fp->cid, FCOE_TXQ_IDX(bp), BNX2X_FCOE_L2_TX_INDEX,
6411 DP(NETIF_MSG_IFUP, "created fcoe tx data (fp index %d)\n", fp->index);
6413 /* qZone id equals to FW (per path) client id */
6414 bnx2x_fcoe(bp, cl_qzone_id) = bnx2x_fp_qzone_id(fp);
6416 bnx2x_fcoe(bp, ustorm_rx_prods_offset) =
6417 bnx2x_rx_ustorm_prods_offset(fp);
6419 /* Configure Queue State object */
6420 __set_bit(BNX2X_Q_TYPE_HAS_RX, &q_type);
6421 __set_bit(BNX2X_Q_TYPE_HAS_TX, &q_type);
6423 /* No multi-CoS for FCoE L2 client */
6424 BUG_ON(fp->max_cos != 1);
6426 bnx2x_init_queue_obj(bp, &bnx2x_sp_obj(bp, fp).q_obj, fp->cl_id,
6427 &fp->cid, 1, BP_FUNC(bp), bnx2x_sp(bp, q_rdata),
6428 bnx2x_sp_mapping(bp, q_rdata), q_type);
6431 "queue[%d]: bnx2x_init_sb(%p,%p) cl_id %d fw_sb %d igu_sb %d\n",
6432 fp->index, bp, fp->status_blk.e2_sb, fp->cl_id, fp->fw_sb_id,
6436 void bnx2x_nic_init_cnic(struct bnx2x *bp)
6439 bnx2x_init_fcoe_fp(bp);
6441 bnx2x_init_sb(bp, bp->cnic_sb_mapping,
6442 BNX2X_VF_ID_INVALID, false,
6443 bnx2x_cnic_fw_sb_id(bp), bnx2x_cnic_igu_sb_id(bp));
6445 /* ensure status block indices were read */
6447 bnx2x_init_rx_rings_cnic(bp);
6448 bnx2x_init_tx_rings_cnic(bp);
6455 void bnx2x_pre_irq_nic_init(struct bnx2x *bp)
6459 /* Setup NIC internals and enable interrupts */
6460 for_each_eth_queue(bp, i)
6461 bnx2x_init_eth_fp(bp, i);
6463 /* ensure status block indices were read */
6465 bnx2x_init_rx_rings(bp);
6466 bnx2x_init_tx_rings(bp);
6469 /* Initialize MOD_ABS interrupts */
6470 bnx2x_init_mod_abs_int(bp, &bp->link_vars, bp->common.chip_id,
6471 bp->common.shmem_base,
6472 bp->common.shmem2_base, BP_PORT(bp));
6474 /* initialize the default status block and sp ring */
6475 bnx2x_init_def_sb(bp);
6476 bnx2x_update_dsb_idx(bp);
6477 bnx2x_init_sp_ring(bp);
6479 bnx2x_memset_stats(bp);
6483 void bnx2x_post_irq_nic_init(struct bnx2x *bp, u32 load_code)
6485 bnx2x_init_eq_ring(bp);
6486 bnx2x_init_internal(bp, load_code);
6488 bnx2x_stats_init(bp);
6490 /* flush all before enabling interrupts */
6494 bnx2x_int_enable(bp);
6496 /* Check for SPIO5 */
6497 bnx2x_attn_int_deasserted0(bp,
6498 REG_RD(bp, MISC_REG_AEU_AFTER_INVERT_1_FUNC_0 + BP_PORT(bp)*4) &
6499 AEU_INPUTS_ATTN_BITS_SPIO5);
6502 /* gzip service functions */
6503 static int bnx2x_gunzip_init(struct bnx2x *bp)
6505 bp->gunzip_buf = dma_alloc_coherent(&bp->pdev->dev, FW_BUF_SIZE,
6506 &bp->gunzip_mapping, GFP_KERNEL);
6507 if (bp->gunzip_buf == NULL)
6510 bp->strm = kmalloc(sizeof(*bp->strm), GFP_KERNEL);
6511 if (bp->strm == NULL)
6514 bp->strm->workspace = vmalloc(zlib_inflate_workspacesize());
6515 if (bp->strm->workspace == NULL)
6525 dma_free_coherent(&bp->pdev->dev, FW_BUF_SIZE, bp->gunzip_buf,
6526 bp->gunzip_mapping);
6527 bp->gunzip_buf = NULL;
6530 BNX2X_ERR("Cannot allocate firmware buffer for un-compression\n");
6534 static void bnx2x_gunzip_end(struct bnx2x *bp)
6537 vfree(bp->strm->workspace);
6542 if (bp->gunzip_buf) {
6543 dma_free_coherent(&bp->pdev->dev, FW_BUF_SIZE, bp->gunzip_buf,
6544 bp->gunzip_mapping);
6545 bp->gunzip_buf = NULL;
6549 static int bnx2x_gunzip(struct bnx2x *bp, const u8 *zbuf, int len)
6553 /* check gzip header */
6554 if ((zbuf[0] != 0x1f) || (zbuf[1] != 0x8b) || (zbuf[2] != Z_DEFLATED)) {
6555 BNX2X_ERR("Bad gzip header\n");
6563 if (zbuf[3] & FNAME)
6564 while ((zbuf[n++] != 0) && (n < len));
6566 bp->strm->next_in = (typeof(bp->strm->next_in))zbuf + n;
6567 bp->strm->avail_in = len - n;
6568 bp->strm->next_out = bp->gunzip_buf;
6569 bp->strm->avail_out = FW_BUF_SIZE;
6571 rc = zlib_inflateInit2(bp->strm, -MAX_WBITS);
6575 rc = zlib_inflate(bp->strm, Z_FINISH);
6576 if ((rc != Z_OK) && (rc != Z_STREAM_END))
6577 netdev_err(bp->dev, "Firmware decompression error: %s\n",
6580 bp->gunzip_outlen = (FW_BUF_SIZE - bp->strm->avail_out);
6581 if (bp->gunzip_outlen & 0x3)
6583 "Firmware decompression error: gunzip_outlen (%d) not aligned\n",
6585 bp->gunzip_outlen >>= 2;
6587 zlib_inflateEnd(bp->strm);
6589 if (rc == Z_STREAM_END)
6595 /* nic load/unload */
6598 * General service functions
6601 /* send a NIG loopback debug packet */
6602 static void bnx2x_lb_pckt(struct bnx2x *bp)
6606 /* Ethernet source and destination addresses */
6607 wb_write[0] = 0x55555555;
6608 wb_write[1] = 0x55555555;
6609 wb_write[2] = 0x20; /* SOP */
6610 REG_WR_DMAE(bp, NIG_REG_DEBUG_PACKET_LB, wb_write, 3);
6612 /* NON-IP protocol */
6613 wb_write[0] = 0x09000000;
6614 wb_write[1] = 0x55555555;
6615 wb_write[2] = 0x10; /* EOP, eop_bvalid = 0 */
6616 REG_WR_DMAE(bp, NIG_REG_DEBUG_PACKET_LB, wb_write, 3);
6619 /* some of the internal memories
6620 * are not directly readable from the driver
6621 * to test them we send debug packets
6623 static int bnx2x_int_mem_test(struct bnx2x *bp)
6629 if (CHIP_REV_IS_FPGA(bp))
6631 else if (CHIP_REV_IS_EMUL(bp))
6636 /* Disable inputs of parser neighbor blocks */
6637 REG_WR(bp, TSDM_REG_ENABLE_IN1, 0x0);
6638 REG_WR(bp, TCM_REG_PRS_IFEN, 0x0);
6639 REG_WR(bp, CFC_REG_DEBUG0, 0x1);
6640 REG_WR(bp, NIG_REG_PRS_REQ_IN_EN, 0x0);
6642 /* Write 0 to parser credits for CFC search request */
6643 REG_WR(bp, PRS_REG_CFC_SEARCH_INITIAL_CREDIT, 0x0);
6645 /* send Ethernet packet */
6648 /* TODO do i reset NIG statistic? */
6649 /* Wait until NIG register shows 1 packet of size 0x10 */
6650 count = 1000 * factor;
6653 bnx2x_read_dmae(bp, NIG_REG_STAT2_BRB_OCTET, 2);
6654 val = *bnx2x_sp(bp, wb_data[0]);
6658 usleep_range(10000, 20000);
6662 BNX2X_ERR("NIG timeout val = 0x%x\n", val);
6666 /* Wait until PRS register shows 1 packet */
6667 count = 1000 * factor;
6669 val = REG_RD(bp, PRS_REG_NUM_OF_PACKETS);
6673 usleep_range(10000, 20000);
6677 BNX2X_ERR("PRS timeout val = 0x%x\n", val);
6681 /* Reset and init BRB, PRS */
6682 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_CLEAR, 0x03);
6684 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_SET, 0x03);
6686 bnx2x_init_block(bp, BLOCK_BRB1, PHASE_COMMON);
6687 bnx2x_init_block(bp, BLOCK_PRS, PHASE_COMMON);
6689 DP(NETIF_MSG_HW, "part2\n");
6691 /* Disable inputs of parser neighbor blocks */
6692 REG_WR(bp, TSDM_REG_ENABLE_IN1, 0x0);
6693 REG_WR(bp, TCM_REG_PRS_IFEN, 0x0);
6694 REG_WR(bp, CFC_REG_DEBUG0, 0x1);
6695 REG_WR(bp, NIG_REG_PRS_REQ_IN_EN, 0x0);
6697 /* Write 0 to parser credits for CFC search request */
6698 REG_WR(bp, PRS_REG_CFC_SEARCH_INITIAL_CREDIT, 0x0);
6700 /* send 10 Ethernet packets */
6701 for (i = 0; i < 10; i++)
6704 /* Wait until NIG register shows 10 + 1
6705 packets of size 11*0x10 = 0xb0 */
6706 count = 1000 * factor;
6709 bnx2x_read_dmae(bp, NIG_REG_STAT2_BRB_OCTET, 2);
6710 val = *bnx2x_sp(bp, wb_data[0]);
6714 usleep_range(10000, 20000);
6718 BNX2X_ERR("NIG timeout val = 0x%x\n", val);
6722 /* Wait until PRS register shows 2 packets */
6723 val = REG_RD(bp, PRS_REG_NUM_OF_PACKETS);
6725 BNX2X_ERR("PRS timeout val = 0x%x\n", val);
6727 /* Write 1 to parser credits for CFC search request */
6728 REG_WR(bp, PRS_REG_CFC_SEARCH_INITIAL_CREDIT, 0x1);
6730 /* Wait until PRS register shows 3 packets */
6731 msleep(10 * factor);
6732 /* Wait until NIG register shows 1 packet of size 0x10 */
6733 val = REG_RD(bp, PRS_REG_NUM_OF_PACKETS);
6735 BNX2X_ERR("PRS timeout val = 0x%x\n", val);
6737 /* clear NIG EOP FIFO */
6738 for (i = 0; i < 11; i++)
6739 REG_RD(bp, NIG_REG_INGRESS_EOP_LB_FIFO);
6740 val = REG_RD(bp, NIG_REG_INGRESS_EOP_LB_EMPTY);
6742 BNX2X_ERR("clear of NIG failed\n");
6746 /* Reset and init BRB, PRS, NIG */
6747 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_CLEAR, 0x03);
6749 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_SET, 0x03);
6751 bnx2x_init_block(bp, BLOCK_BRB1, PHASE_COMMON);
6752 bnx2x_init_block(bp, BLOCK_PRS, PHASE_COMMON);
6753 if (!CNIC_SUPPORT(bp))
6755 REG_WR(bp, PRS_REG_NIC_MODE, 1);
6757 /* Enable inputs of parser neighbor blocks */
6758 REG_WR(bp, TSDM_REG_ENABLE_IN1, 0x7fffffff);
6759 REG_WR(bp, TCM_REG_PRS_IFEN, 0x1);
6760 REG_WR(bp, CFC_REG_DEBUG0, 0x0);
6761 REG_WR(bp, NIG_REG_PRS_REQ_IN_EN, 0x1);
6763 DP(NETIF_MSG_HW, "done\n");
6768 static void bnx2x_enable_blocks_attention(struct bnx2x *bp)
6772 REG_WR(bp, PXP_REG_PXP_INT_MASK_0, 0);
6773 if (!CHIP_IS_E1x(bp))
6774 REG_WR(bp, PXP_REG_PXP_INT_MASK_1, 0x40);
6776 REG_WR(bp, PXP_REG_PXP_INT_MASK_1, 0);
6777 REG_WR(bp, DORQ_REG_DORQ_INT_MASK, 0);
6778 REG_WR(bp, CFC_REG_CFC_INT_MASK, 0);
6780 * mask read length error interrupts in brb for parser
6781 * (parsing unit and 'checksum and crc' unit)
6782 * these errors are legal (PU reads fixed length and CAC can cause
6783 * read length error on truncated packets)
6785 REG_WR(bp, BRB1_REG_BRB1_INT_MASK, 0xFC00);
6786 REG_WR(bp, QM_REG_QM_INT_MASK, 0);
6787 REG_WR(bp, TM_REG_TM_INT_MASK, 0);
6788 REG_WR(bp, XSDM_REG_XSDM_INT_MASK_0, 0);
6789 REG_WR(bp, XSDM_REG_XSDM_INT_MASK_1, 0);
6790 REG_WR(bp, XCM_REG_XCM_INT_MASK, 0);
6791 /* REG_WR(bp, XSEM_REG_XSEM_INT_MASK_0, 0); */
6792 /* REG_WR(bp, XSEM_REG_XSEM_INT_MASK_1, 0); */
6793 REG_WR(bp, USDM_REG_USDM_INT_MASK_0, 0);
6794 REG_WR(bp, USDM_REG_USDM_INT_MASK_1, 0);
6795 REG_WR(bp, UCM_REG_UCM_INT_MASK, 0);
6796 /* REG_WR(bp, USEM_REG_USEM_INT_MASK_0, 0); */
6797 /* REG_WR(bp, USEM_REG_USEM_INT_MASK_1, 0); */
6798 REG_WR(bp, GRCBASE_UPB + PB_REG_PB_INT_MASK, 0);
6799 REG_WR(bp, CSDM_REG_CSDM_INT_MASK_0, 0);
6800 REG_WR(bp, CSDM_REG_CSDM_INT_MASK_1, 0);
6801 REG_WR(bp, CCM_REG_CCM_INT_MASK, 0);
6802 /* REG_WR(bp, CSEM_REG_CSEM_INT_MASK_0, 0); */
6803 /* REG_WR(bp, CSEM_REG_CSEM_INT_MASK_1, 0); */
6805 val = PXP2_PXP2_INT_MASK_0_REG_PGL_CPL_AFT |
6806 PXP2_PXP2_INT_MASK_0_REG_PGL_CPL_OF |
6807 PXP2_PXP2_INT_MASK_0_REG_PGL_PCIE_ATTN;
6808 if (!CHIP_IS_E1x(bp))
6809 val |= PXP2_PXP2_INT_MASK_0_REG_PGL_READ_BLOCKED |
6810 PXP2_PXP2_INT_MASK_0_REG_PGL_WRITE_BLOCKED;
6811 REG_WR(bp, PXP2_REG_PXP2_INT_MASK_0, val);
6813 REG_WR(bp, TSDM_REG_TSDM_INT_MASK_0, 0);
6814 REG_WR(bp, TSDM_REG_TSDM_INT_MASK_1, 0);
6815 REG_WR(bp, TCM_REG_TCM_INT_MASK, 0);
6816 /* REG_WR(bp, TSEM_REG_TSEM_INT_MASK_0, 0); */
6818 if (!CHIP_IS_E1x(bp))
6819 /* enable VFC attentions: bits 11 and 12, bits 31:13 reserved */
6820 REG_WR(bp, TSEM_REG_TSEM_INT_MASK_1, 0x07ff);
6822 REG_WR(bp, CDU_REG_CDU_INT_MASK, 0);
6823 REG_WR(bp, DMAE_REG_DMAE_INT_MASK, 0);
6824 /* REG_WR(bp, MISC_REG_MISC_INT_MASK, 0); */
6825 REG_WR(bp, PBF_REG_PBF_INT_MASK, 0x18); /* bit 3,4 masked */
6828 static void bnx2x_reset_common(struct bnx2x *bp)
6833 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_CLEAR,
6836 if (CHIP_IS_E3(bp)) {
6837 val |= MISC_REGISTERS_RESET_REG_2_MSTAT0;
6838 val |= MISC_REGISTERS_RESET_REG_2_MSTAT1;
6841 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR, val);
6844 static void bnx2x_setup_dmae(struct bnx2x *bp)
6847 spin_lock_init(&bp->dmae_lock);
6850 static void bnx2x_init_pxp(struct bnx2x *bp)
6853 int r_order, w_order;
6855 pcie_capability_read_word(bp->pdev, PCI_EXP_DEVCTL, &devctl);
6856 DP(NETIF_MSG_HW, "read 0x%x from devctl\n", devctl);
6857 w_order = ((devctl & PCI_EXP_DEVCTL_PAYLOAD) >> 5);
6859 r_order = ((devctl & PCI_EXP_DEVCTL_READRQ) >> 12);
6861 DP(NETIF_MSG_HW, "force read order to %d\n", bp->mrrs);
6865 bnx2x_init_pxp_arb(bp, r_order, w_order);
6868 static void bnx2x_setup_fan_failure_detection(struct bnx2x *bp)
6878 val = SHMEM_RD(bp, dev_info.shared_hw_config.config2) &
6879 SHARED_HW_CFG_FAN_FAILURE_MASK;
6881 if (val == SHARED_HW_CFG_FAN_FAILURE_ENABLED)
6885 * The fan failure mechanism is usually related to the PHY type since
6886 * the power consumption of the board is affected by the PHY. Currently,
6887 * fan is required for most designs with SFX7101, BCM8727 and BCM8481.
6889 else if (val == SHARED_HW_CFG_FAN_FAILURE_PHY_TYPE)
6890 for (port = PORT_0; port < PORT_MAX; port++) {
6892 bnx2x_fan_failure_det_req(
6894 bp->common.shmem_base,
6895 bp->common.shmem2_base,
6899 DP(NETIF_MSG_HW, "fan detection setting: %d\n", is_required);
6901 if (is_required == 0)
6904 /* Fan failure is indicated by SPIO 5 */
6905 bnx2x_set_spio(bp, MISC_SPIO_SPIO5, MISC_SPIO_INPUT_HI_Z);
6907 /* set to active low mode */
6908 val = REG_RD(bp, MISC_REG_SPIO_INT);
6909 val |= (MISC_SPIO_SPIO5 << MISC_SPIO_INT_OLD_SET_POS);
6910 REG_WR(bp, MISC_REG_SPIO_INT, val);
6912 /* enable interrupt to signal the IGU */
6913 val = REG_RD(bp, MISC_REG_SPIO_EVENT_EN);
6914 val |= MISC_SPIO_SPIO5;
6915 REG_WR(bp, MISC_REG_SPIO_EVENT_EN, val);
6918 void bnx2x_pf_disable(struct bnx2x *bp)
6920 u32 val = REG_RD(bp, IGU_REG_PF_CONFIGURATION);
6921 val &= ~IGU_PF_CONF_FUNC_EN;
6923 REG_WR(bp, IGU_REG_PF_CONFIGURATION, val);
6924 REG_WR(bp, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, 0);
6925 REG_WR(bp, CFC_REG_WEAK_ENABLE_PF, 0);
6928 static void bnx2x__common_init_phy(struct bnx2x *bp)
6930 u32 shmem_base[2], shmem2_base[2];
6931 /* Avoid common init in case MFW supports LFA */
6932 if (SHMEM2_RD(bp, size) >
6933 (u32)offsetof(struct shmem2_region, lfa_host_addr[BP_PORT(bp)]))
6935 shmem_base[0] = bp->common.shmem_base;
6936 shmem2_base[0] = bp->common.shmem2_base;
6937 if (!CHIP_IS_E1x(bp)) {
6939 SHMEM2_RD(bp, other_shmem_base_addr);
6941 SHMEM2_RD(bp, other_shmem2_base_addr);
6943 bnx2x_acquire_phy_lock(bp);
6944 bnx2x_common_init_phy(bp, shmem_base, shmem2_base,
6945 bp->common.chip_id);
6946 bnx2x_release_phy_lock(bp);
6949 static void bnx2x_config_endianity(struct bnx2x *bp, u32 val)
6951 REG_WR(bp, PXP2_REG_RQ_QM_ENDIAN_M, val);
6952 REG_WR(bp, PXP2_REG_RQ_TM_ENDIAN_M, val);
6953 REG_WR(bp, PXP2_REG_RQ_SRC_ENDIAN_M, val);
6954 REG_WR(bp, PXP2_REG_RQ_CDU_ENDIAN_M, val);
6955 REG_WR(bp, PXP2_REG_RQ_DBG_ENDIAN_M, val);
6957 /* make sure this value is 0 */
6958 REG_WR(bp, PXP2_REG_RQ_HC_ENDIAN_M, 0);
6960 REG_WR(bp, PXP2_REG_RD_QM_SWAP_MODE, val);
6961 REG_WR(bp, PXP2_REG_RD_TM_SWAP_MODE, val);
6962 REG_WR(bp, PXP2_REG_RD_SRC_SWAP_MODE, val);
6963 REG_WR(bp, PXP2_REG_RD_CDURD_SWAP_MODE, val);
6966 static void bnx2x_set_endianity(struct bnx2x *bp)
6969 bnx2x_config_endianity(bp, 1);
6971 bnx2x_config_endianity(bp, 0);
6975 static void bnx2x_reset_endianity(struct bnx2x *bp)
6977 bnx2x_config_endianity(bp, 0);
6981 * bnx2x_init_hw_common - initialize the HW at the COMMON phase.
6983 * @bp: driver handle
6985 static int bnx2x_init_hw_common(struct bnx2x *bp)
6989 DP(NETIF_MSG_HW, "starting common init func %d\n", BP_ABS_FUNC(bp));
6992 * take the RESET lock to protect undi_unload flow from accessing
6993 * registers while we're resetting the chip
6995 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_RESET);
6997 bnx2x_reset_common(bp);
6998 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_SET, 0xffffffff);
7001 if (CHIP_IS_E3(bp)) {
7002 val |= MISC_REGISTERS_RESET_REG_2_MSTAT0;
7003 val |= MISC_REGISTERS_RESET_REG_2_MSTAT1;
7005 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_SET, val);
7007 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_RESET);
7009 bnx2x_init_block(bp, BLOCK_MISC, PHASE_COMMON);
7011 if (!CHIP_IS_E1x(bp)) {
7015 * 4-port mode or 2-port mode we need to turn of master-enable
7016 * for everyone, after that, turn it back on for self.
7017 * so, we disregard multi-function or not, and always disable
7018 * for all functions on the given path, this means 0,2,4,6 for
7019 * path 0 and 1,3,5,7 for path 1
7021 for (abs_func_id = BP_PATH(bp);
7022 abs_func_id < E2_FUNC_MAX*2; abs_func_id += 2) {
7023 if (abs_func_id == BP_ABS_FUNC(bp)) {
7025 PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER,
7030 bnx2x_pretend_func(bp, abs_func_id);
7031 /* clear pf enable */
7032 bnx2x_pf_disable(bp);
7033 bnx2x_pretend_func(bp, BP_ABS_FUNC(bp));
7037 bnx2x_init_block(bp, BLOCK_PXP, PHASE_COMMON);
7038 if (CHIP_IS_E1(bp)) {
7039 /* enable HW interrupt from PXP on USDM overflow
7040 bit 16 on INT_MASK_0 */
7041 REG_WR(bp, PXP_REG_PXP_INT_MASK_0, 0);
7044 bnx2x_init_block(bp, BLOCK_PXP2, PHASE_COMMON);
7046 bnx2x_set_endianity(bp);
7047 bnx2x_ilt_init_page_size(bp, INITOP_SET);
7049 if (CHIP_REV_IS_FPGA(bp) && CHIP_IS_E1H(bp))
7050 REG_WR(bp, PXP2_REG_PGL_TAGS_LIMIT, 0x1);
7052 /* let the HW do it's magic ... */
7054 /* finish PXP init */
7055 val = REG_RD(bp, PXP2_REG_RQ_CFG_DONE);
7057 BNX2X_ERR("PXP2 CFG failed\n");
7060 val = REG_RD(bp, PXP2_REG_RD_INIT_DONE);
7062 BNX2X_ERR("PXP2 RD_INIT failed\n");
7066 /* Timers bug workaround E2 only. We need to set the entire ILT to
7067 * have entries with value "0" and valid bit on.
7068 * This needs to be done by the first PF that is loaded in a path
7069 * (i.e. common phase)
7071 if (!CHIP_IS_E1x(bp)) {
7072 /* In E2 there is a bug in the timers block that can cause function 6 / 7
7073 * (i.e. vnic3) to start even if it is marked as "scan-off".
7074 * This occurs when a different function (func2,3) is being marked
7075 * as "scan-off". Real-life scenario for example: if a driver is being
7076 * load-unloaded while func6,7 are down. This will cause the timer to access
7077 * the ilt, translate to a logical address and send a request to read/write.
7078 * Since the ilt for the function that is down is not valid, this will cause
7079 * a translation error which is unrecoverable.
7080 * The Workaround is intended to make sure that when this happens nothing fatal
7081 * will occur. The workaround:
7082 * 1. First PF driver which loads on a path will:
7083 * a. After taking the chip out of reset, by using pretend,
7084 * it will write "0" to the following registers of
7086 * REG_WR(pdev, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, 0);
7087 * REG_WR(pdev, CFC_REG_WEAK_ENABLE_PF,0);
7088 * REG_WR(pdev, CFC_REG_STRONG_ENABLE_PF,0);
7089 * And for itself it will write '1' to
7090 * PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER to enable
7091 * dmae-operations (writing to pram for example.)
7092 * note: can be done for only function 6,7 but cleaner this
7094 * b. Write zero+valid to the entire ILT.
7095 * c. Init the first_timers_ilt_entry, last_timers_ilt_entry of
7096 * VNIC3 (of that port). The range allocated will be the
7097 * entire ILT. This is needed to prevent ILT range error.
7098 * 2. Any PF driver load flow:
7099 * a. ILT update with the physical addresses of the allocated
7101 * b. Wait 20msec. - note that this timeout is needed to make
7102 * sure there are no requests in one of the PXP internal
7103 * queues with "old" ILT addresses.
7104 * c. PF enable in the PGLC.
7105 * d. Clear the was_error of the PF in the PGLC. (could have
7106 * occurred while driver was down)
7107 * e. PF enable in the CFC (WEAK + STRONG)
7108 * f. Timers scan enable
7109 * 3. PF driver unload flow:
7110 * a. Clear the Timers scan_en.
7111 * b. Polling for scan_on=0 for that PF.
7112 * c. Clear the PF enable bit in the PXP.
7113 * d. Clear the PF enable in the CFC (WEAK + STRONG)
7114 * e. Write zero+valid to all ILT entries (The valid bit must
7116 * f. If this is VNIC 3 of a port then also init
7117 * first_timers_ilt_entry to zero and last_timers_ilt_entry
7118 * to the last entry in the ILT.
7121 * Currently the PF error in the PGLC is non recoverable.
7122 * In the future the there will be a recovery routine for this error.
7123 * Currently attention is masked.
7124 * Having an MCP lock on the load/unload process does not guarantee that
7125 * there is no Timer disable during Func6/7 enable. This is because the
7126 * Timers scan is currently being cleared by the MCP on FLR.
7127 * Step 2.d can be done only for PF6/7 and the driver can also check if
7128 * there is error before clearing it. But the flow above is simpler and
7130 * All ILT entries are written by zero+valid and not just PF6/7
7131 * ILT entries since in the future the ILT entries allocation for
7132 * PF-s might be dynamic.
7134 struct ilt_client_info ilt_cli;
7135 struct bnx2x_ilt ilt;
7136 memset(&ilt_cli, 0, sizeof(struct ilt_client_info));
7137 memset(&ilt, 0, sizeof(struct bnx2x_ilt));
7139 /* initialize dummy TM client */
7141 ilt_cli.end = ILT_NUM_PAGE_ENTRIES - 1;
7142 ilt_cli.client_num = ILT_CLIENT_TM;
7144 /* Step 1: set zeroes to all ilt page entries with valid bit on
7145 * Step 2: set the timers first/last ilt entry to point
7146 * to the entire range to prevent ILT range error for 3rd/4th
7147 * vnic (this code assumes existence of the vnic)
7149 * both steps performed by call to bnx2x_ilt_client_init_op()
7150 * with dummy TM client
7152 * we must use pretend since PXP2_REG_RQ_##blk##_FIRST_ILT
7153 * and his brother are split registers
7155 bnx2x_pretend_func(bp, (BP_PATH(bp) + 6));
7156 bnx2x_ilt_client_init_op_ilt(bp, &ilt, &ilt_cli, INITOP_CLEAR);
7157 bnx2x_pretend_func(bp, BP_ABS_FUNC(bp));
7159 REG_WR(bp, PXP2_REG_RQ_DRAM_ALIGN, BNX2X_PXP_DRAM_ALIGN);
7160 REG_WR(bp, PXP2_REG_RQ_DRAM_ALIGN_RD, BNX2X_PXP_DRAM_ALIGN);
7161 REG_WR(bp, PXP2_REG_RQ_DRAM_ALIGN_SEL, 1);
7164 REG_WR(bp, PXP2_REG_RQ_DISABLE_INPUTS, 0);
7165 REG_WR(bp, PXP2_REG_RD_DISABLE_INPUTS, 0);
7167 if (!CHIP_IS_E1x(bp)) {
7168 int factor = CHIP_REV_IS_EMUL(bp) ? 1000 :
7169 (CHIP_REV_IS_FPGA(bp) ? 400 : 0);
7170 bnx2x_init_block(bp, BLOCK_PGLUE_B, PHASE_COMMON);
7172 bnx2x_init_block(bp, BLOCK_ATC, PHASE_COMMON);
7174 /* let the HW do it's magic ... */
7177 val = REG_RD(bp, ATC_REG_ATC_INIT_DONE);
7178 } while (factor-- && (val != 1));
7181 BNX2X_ERR("ATC_INIT failed\n");
7186 bnx2x_init_block(bp, BLOCK_DMAE, PHASE_COMMON);
7188 bnx2x_iov_init_dmae(bp);
7190 /* clean the DMAE memory */
7192 bnx2x_init_fill(bp, TSEM_REG_PRAM, 0, 8, 1);
7194 bnx2x_init_block(bp, BLOCK_TCM, PHASE_COMMON);
7196 bnx2x_init_block(bp, BLOCK_UCM, PHASE_COMMON);
7198 bnx2x_init_block(bp, BLOCK_CCM, PHASE_COMMON);
7200 bnx2x_init_block(bp, BLOCK_XCM, PHASE_COMMON);
7202 bnx2x_read_dmae(bp, XSEM_REG_PASSIVE_BUFFER, 3);
7203 bnx2x_read_dmae(bp, CSEM_REG_PASSIVE_BUFFER, 3);
7204 bnx2x_read_dmae(bp, TSEM_REG_PASSIVE_BUFFER, 3);
7205 bnx2x_read_dmae(bp, USEM_REG_PASSIVE_BUFFER, 3);
7207 bnx2x_init_block(bp, BLOCK_QM, PHASE_COMMON);
7209 /* QM queues pointers table */
7210 bnx2x_qm_init_ptr_table(bp, bp->qm_cid_count, INITOP_SET);
7212 /* soft reset pulse */
7213 REG_WR(bp, QM_REG_SOFT_RESET, 1);
7214 REG_WR(bp, QM_REG_SOFT_RESET, 0);
7216 if (CNIC_SUPPORT(bp))
7217 bnx2x_init_block(bp, BLOCK_TM, PHASE_COMMON);
7219 bnx2x_init_block(bp, BLOCK_DORQ, PHASE_COMMON);
7221 if (!CHIP_REV_IS_SLOW(bp))
7222 /* enable hw interrupt from doorbell Q */
7223 REG_WR(bp, DORQ_REG_DORQ_INT_MASK, 0);
7225 bnx2x_init_block(bp, BLOCK_BRB1, PHASE_COMMON);
7227 bnx2x_init_block(bp, BLOCK_PRS, PHASE_COMMON);
7228 REG_WR(bp, PRS_REG_A_PRSU_20, 0xf);
7230 if (!CHIP_IS_E1(bp))
7231 REG_WR(bp, PRS_REG_E1HOV_MODE, bp->path_has_ovlan);
7233 if (!CHIP_IS_E1x(bp) && !CHIP_IS_E3B0(bp)) {
7234 if (IS_MF_AFEX(bp)) {
7235 /* configure that VNTag and VLAN headers must be
7236 * received in afex mode
7238 REG_WR(bp, PRS_REG_HDRS_AFTER_BASIC, 0xE);
7239 REG_WR(bp, PRS_REG_MUST_HAVE_HDRS, 0xA);
7240 REG_WR(bp, PRS_REG_HDRS_AFTER_TAG_0, 0x6);
7241 REG_WR(bp, PRS_REG_TAG_ETHERTYPE_0, 0x8926);
7242 REG_WR(bp, PRS_REG_TAG_LEN_0, 0x4);
7244 /* Bit-map indicating which L2 hdrs may appear
7245 * after the basic Ethernet header
7247 REG_WR(bp, PRS_REG_HDRS_AFTER_BASIC,
7248 bp->path_has_ovlan ? 7 : 6);
7252 bnx2x_init_block(bp, BLOCK_TSDM, PHASE_COMMON);
7253 bnx2x_init_block(bp, BLOCK_CSDM, PHASE_COMMON);
7254 bnx2x_init_block(bp, BLOCK_USDM, PHASE_COMMON);
7255 bnx2x_init_block(bp, BLOCK_XSDM, PHASE_COMMON);
7257 if (!CHIP_IS_E1x(bp)) {
7258 /* reset VFC memories */
7259 REG_WR(bp, TSEM_REG_FAST_MEMORY + VFC_REG_MEMORIES_RST,
7260 VFC_MEMORIES_RST_REG_CAM_RST |
7261 VFC_MEMORIES_RST_REG_RAM_RST);
7262 REG_WR(bp, XSEM_REG_FAST_MEMORY + VFC_REG_MEMORIES_RST,
7263 VFC_MEMORIES_RST_REG_CAM_RST |
7264 VFC_MEMORIES_RST_REG_RAM_RST);
7269 bnx2x_init_block(bp, BLOCK_TSEM, PHASE_COMMON);
7270 bnx2x_init_block(bp, BLOCK_USEM, PHASE_COMMON);
7271 bnx2x_init_block(bp, BLOCK_CSEM, PHASE_COMMON);
7272 bnx2x_init_block(bp, BLOCK_XSEM, PHASE_COMMON);
7275 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_CLEAR,
7277 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_SET,
7280 bnx2x_init_block(bp, BLOCK_UPB, PHASE_COMMON);
7281 bnx2x_init_block(bp, BLOCK_XPB, PHASE_COMMON);
7282 bnx2x_init_block(bp, BLOCK_PBF, PHASE_COMMON);
7284 if (!CHIP_IS_E1x(bp)) {
7285 if (IS_MF_AFEX(bp)) {
7286 /* configure that VNTag and VLAN headers must be
7289 REG_WR(bp, PBF_REG_HDRS_AFTER_BASIC, 0xE);
7290 REG_WR(bp, PBF_REG_MUST_HAVE_HDRS, 0xA);
7291 REG_WR(bp, PBF_REG_HDRS_AFTER_TAG_0, 0x6);
7292 REG_WR(bp, PBF_REG_TAG_ETHERTYPE_0, 0x8926);
7293 REG_WR(bp, PBF_REG_TAG_LEN_0, 0x4);
7295 REG_WR(bp, PBF_REG_HDRS_AFTER_BASIC,
7296 bp->path_has_ovlan ? 7 : 6);
7300 REG_WR(bp, SRC_REG_SOFT_RST, 1);
7302 bnx2x_init_block(bp, BLOCK_SRC, PHASE_COMMON);
7304 if (CNIC_SUPPORT(bp)) {
7305 REG_WR(bp, SRC_REG_KEYSEARCH_0, 0x63285672);
7306 REG_WR(bp, SRC_REG_KEYSEARCH_1, 0x24b8f2cc);
7307 REG_WR(bp, SRC_REG_KEYSEARCH_2, 0x223aef9b);
7308 REG_WR(bp, SRC_REG_KEYSEARCH_3, 0x26001e3a);
7309 REG_WR(bp, SRC_REG_KEYSEARCH_4, 0x7ae91116);
7310 REG_WR(bp, SRC_REG_KEYSEARCH_5, 0x5ce5230b);
7311 REG_WR(bp, SRC_REG_KEYSEARCH_6, 0x298d8adf);
7312 REG_WR(bp, SRC_REG_KEYSEARCH_7, 0x6eb0ff09);
7313 REG_WR(bp, SRC_REG_KEYSEARCH_8, 0x1830f82f);
7314 REG_WR(bp, SRC_REG_KEYSEARCH_9, 0x01e46be7);
7316 REG_WR(bp, SRC_REG_SOFT_RST, 0);
7318 if (sizeof(union cdu_context) != 1024)
7319 /* we currently assume that a context is 1024 bytes */
7320 dev_alert(&bp->pdev->dev,
7321 "please adjust the size of cdu_context(%ld)\n",
7322 (long)sizeof(union cdu_context));
7324 bnx2x_init_block(bp, BLOCK_CDU, PHASE_COMMON);
7325 val = (4 << 24) + (0 << 12) + 1024;
7326 REG_WR(bp, CDU_REG_CDU_GLOBAL_PARAMS, val);
7328 bnx2x_init_block(bp, BLOCK_CFC, PHASE_COMMON);
7329 REG_WR(bp, CFC_REG_INIT_REG, 0x7FF);
7330 /* enable context validation interrupt from CFC */
7331 REG_WR(bp, CFC_REG_CFC_INT_MASK, 0);
7333 /* set the thresholds to prevent CFC/CDU race */
7334 REG_WR(bp, CFC_REG_DEBUG0, 0x20020000);
7336 bnx2x_init_block(bp, BLOCK_HC, PHASE_COMMON);
7338 if (!CHIP_IS_E1x(bp) && BP_NOMCP(bp))
7339 REG_WR(bp, IGU_REG_RESET_MEMORIES, 0x36);
7341 bnx2x_init_block(bp, BLOCK_IGU, PHASE_COMMON);
7342 bnx2x_init_block(bp, BLOCK_MISC_AEU, PHASE_COMMON);
7344 /* Reset PCIE errors for debug */
7345 REG_WR(bp, 0x2814, 0xffffffff);
7346 REG_WR(bp, 0x3820, 0xffffffff);
7348 if (!CHIP_IS_E1x(bp)) {
7349 REG_WR(bp, PCICFG_OFFSET + PXPCS_TL_CONTROL_5,
7350 (PXPCS_TL_CONTROL_5_ERR_UNSPPORT1 |
7351 PXPCS_TL_CONTROL_5_ERR_UNSPPORT));
7352 REG_WR(bp, PCICFG_OFFSET + PXPCS_TL_FUNC345_STAT,
7353 (PXPCS_TL_FUNC345_STAT_ERR_UNSPPORT4 |
7354 PXPCS_TL_FUNC345_STAT_ERR_UNSPPORT3 |
7355 PXPCS_TL_FUNC345_STAT_ERR_UNSPPORT2));
7356 REG_WR(bp, PCICFG_OFFSET + PXPCS_TL_FUNC678_STAT,
7357 (PXPCS_TL_FUNC678_STAT_ERR_UNSPPORT7 |
7358 PXPCS_TL_FUNC678_STAT_ERR_UNSPPORT6 |
7359 PXPCS_TL_FUNC678_STAT_ERR_UNSPPORT5));
7362 bnx2x_init_block(bp, BLOCK_NIG, PHASE_COMMON);
7363 if (!CHIP_IS_E1(bp)) {
7364 /* in E3 this done in per-port section */
7365 if (!CHIP_IS_E3(bp))
7366 REG_WR(bp, NIG_REG_LLH_MF_MODE, IS_MF(bp));
7368 if (CHIP_IS_E1H(bp))
7369 /* not applicable for E2 (and above ...) */
7370 REG_WR(bp, NIG_REG_LLH_E1HOV_MODE, IS_MF_SD(bp));
7372 if (CHIP_REV_IS_SLOW(bp))
7375 /* finish CFC init */
7376 val = reg_poll(bp, CFC_REG_LL_INIT_DONE, 1, 100, 10);
7378 BNX2X_ERR("CFC LL_INIT failed\n");
7381 val = reg_poll(bp, CFC_REG_AC_INIT_DONE, 1, 100, 10);
7383 BNX2X_ERR("CFC AC_INIT failed\n");
7386 val = reg_poll(bp, CFC_REG_CAM_INIT_DONE, 1, 100, 10);
7388 BNX2X_ERR("CFC CAM_INIT failed\n");
7391 REG_WR(bp, CFC_REG_DEBUG0, 0);
7393 if (CHIP_IS_E1(bp)) {
7394 /* read NIG statistic
7395 to see if this is our first up since powerup */
7396 bnx2x_read_dmae(bp, NIG_REG_STAT2_BRB_OCTET, 2);
7397 val = *bnx2x_sp(bp, wb_data[0]);
7399 /* do internal memory self test */
7400 if ((val == 0) && bnx2x_int_mem_test(bp)) {
7401 BNX2X_ERR("internal mem self test failed\n");
7406 bnx2x_setup_fan_failure_detection(bp);
7408 /* clear PXP2 attentions */
7409 REG_RD(bp, PXP2_REG_PXP2_INT_STS_CLR_0);
7411 bnx2x_enable_blocks_attention(bp);
7412 bnx2x_enable_blocks_parity(bp);
7414 if (!BP_NOMCP(bp)) {
7415 if (CHIP_IS_E1x(bp))
7416 bnx2x__common_init_phy(bp);
7418 BNX2X_ERR("Bootcode is missing - can not initialize link\n");
7424 * bnx2x_init_hw_common_chip - init HW at the COMMON_CHIP phase.
7426 * @bp: driver handle
7428 static int bnx2x_init_hw_common_chip(struct bnx2x *bp)
7430 int rc = bnx2x_init_hw_common(bp);
7435 /* In E2 2-PORT mode, same ext phy is used for the two paths */
7437 bnx2x__common_init_phy(bp);
7442 static int bnx2x_init_hw_port(struct bnx2x *bp)
7444 int port = BP_PORT(bp);
7445 int init_phase = port ? PHASE_PORT1 : PHASE_PORT0;
7449 DP(NETIF_MSG_HW, "starting port init port %d\n", port);
7451 REG_WR(bp, NIG_REG_MASK_INTERRUPT_PORT0 + port*4, 0);
7453 bnx2x_init_block(bp, BLOCK_MISC, init_phase);
7454 bnx2x_init_block(bp, BLOCK_PXP, init_phase);
7455 bnx2x_init_block(bp, BLOCK_PXP2, init_phase);
7457 /* Timers bug workaround: disables the pf_master bit in pglue at
7458 * common phase, we need to enable it here before any dmae access are
7459 * attempted. Therefore we manually added the enable-master to the
7460 * port phase (it also happens in the function phase)
7462 if (!CHIP_IS_E1x(bp))
7463 REG_WR(bp, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, 1);
7465 bnx2x_init_block(bp, BLOCK_ATC, init_phase);
7466 bnx2x_init_block(bp, BLOCK_DMAE, init_phase);
7467 bnx2x_init_block(bp, BLOCK_PGLUE_B, init_phase);
7468 bnx2x_init_block(bp, BLOCK_QM, init_phase);
7470 bnx2x_init_block(bp, BLOCK_TCM, init_phase);
7471 bnx2x_init_block(bp, BLOCK_UCM, init_phase);
7472 bnx2x_init_block(bp, BLOCK_CCM, init_phase);
7473 bnx2x_init_block(bp, BLOCK_XCM, init_phase);
7475 /* QM cid (connection) count */
7476 bnx2x_qm_init_cid_count(bp, bp->qm_cid_count, INITOP_SET);
7478 if (CNIC_SUPPORT(bp)) {
7479 bnx2x_init_block(bp, BLOCK_TM, init_phase);
7480 REG_WR(bp, TM_REG_LIN0_SCAN_TIME + port*4, 20);
7481 REG_WR(bp, TM_REG_LIN0_MAX_ACTIVE_CID + port*4, 31);
7484 bnx2x_init_block(bp, BLOCK_DORQ, init_phase);
7486 bnx2x_init_block(bp, BLOCK_BRB1, init_phase);
7488 if (CHIP_IS_E1(bp) || CHIP_IS_E1H(bp)) {
7491 low = ((bp->flags & ONE_PORT_FLAG) ? 160 : 246);
7492 else if (bp->dev->mtu > 4096) {
7493 if (bp->flags & ONE_PORT_FLAG)
7497 /* (24*1024 + val*4)/256 */
7498 low = 96 + (val/64) +
7499 ((val % 64) ? 1 : 0);
7502 low = ((bp->flags & ONE_PORT_FLAG) ? 80 : 160);
7503 high = low + 56; /* 14*1024/256 */
7504 REG_WR(bp, BRB1_REG_PAUSE_LOW_THRESHOLD_0 + port*4, low);
7505 REG_WR(bp, BRB1_REG_PAUSE_HIGH_THRESHOLD_0 + port*4, high);
7508 if (CHIP_MODE_IS_4_PORT(bp))
7509 REG_WR(bp, (BP_PORT(bp) ?
7510 BRB1_REG_MAC_GUARANTIED_1 :
7511 BRB1_REG_MAC_GUARANTIED_0), 40);
7513 bnx2x_init_block(bp, BLOCK_PRS, init_phase);
7514 if (CHIP_IS_E3B0(bp)) {
7515 if (IS_MF_AFEX(bp)) {
7516 /* configure headers for AFEX mode */
7517 REG_WR(bp, BP_PORT(bp) ?
7518 PRS_REG_HDRS_AFTER_BASIC_PORT_1 :
7519 PRS_REG_HDRS_AFTER_BASIC_PORT_0, 0xE);
7520 REG_WR(bp, BP_PORT(bp) ?
7521 PRS_REG_HDRS_AFTER_TAG_0_PORT_1 :
7522 PRS_REG_HDRS_AFTER_TAG_0_PORT_0, 0x6);
7523 REG_WR(bp, BP_PORT(bp) ?
7524 PRS_REG_MUST_HAVE_HDRS_PORT_1 :
7525 PRS_REG_MUST_HAVE_HDRS_PORT_0, 0xA);
7527 /* Ovlan exists only if we are in multi-function +
7528 * switch-dependent mode, in switch-independent there
7529 * is no ovlan headers
7531 REG_WR(bp, BP_PORT(bp) ?
7532 PRS_REG_HDRS_AFTER_BASIC_PORT_1 :
7533 PRS_REG_HDRS_AFTER_BASIC_PORT_0,
7534 (bp->path_has_ovlan ? 7 : 6));
7538 bnx2x_init_block(bp, BLOCK_TSDM, init_phase);
7539 bnx2x_init_block(bp, BLOCK_CSDM, init_phase);
7540 bnx2x_init_block(bp, BLOCK_USDM, init_phase);
7541 bnx2x_init_block(bp, BLOCK_XSDM, init_phase);
7543 bnx2x_init_block(bp, BLOCK_TSEM, init_phase);
7544 bnx2x_init_block(bp, BLOCK_USEM, init_phase);
7545 bnx2x_init_block(bp, BLOCK_CSEM, init_phase);
7546 bnx2x_init_block(bp, BLOCK_XSEM, init_phase);
7548 bnx2x_init_block(bp, BLOCK_UPB, init_phase);
7549 bnx2x_init_block(bp, BLOCK_XPB, init_phase);
7551 bnx2x_init_block(bp, BLOCK_PBF, init_phase);
7553 if (CHIP_IS_E1x(bp)) {
7554 /* configure PBF to work without PAUSE mtu 9000 */
7555 REG_WR(bp, PBF_REG_P0_PAUSE_ENABLE + port*4, 0);
7557 /* update threshold */
7558 REG_WR(bp, PBF_REG_P0_ARB_THRSH + port*4, (9040/16));
7559 /* update init credit */
7560 REG_WR(bp, PBF_REG_P0_INIT_CRD + port*4, (9040/16) + 553 - 22);
7563 REG_WR(bp, PBF_REG_INIT_P0 + port*4, 1);
7565 REG_WR(bp, PBF_REG_INIT_P0 + port*4, 0);
7568 if (CNIC_SUPPORT(bp))
7569 bnx2x_init_block(bp, BLOCK_SRC, init_phase);
7571 bnx2x_init_block(bp, BLOCK_CDU, init_phase);
7572 bnx2x_init_block(bp, BLOCK_CFC, init_phase);
7574 if (CHIP_IS_E1(bp)) {
7575 REG_WR(bp, HC_REG_LEADING_EDGE_0 + port*8, 0);
7576 REG_WR(bp, HC_REG_TRAILING_EDGE_0 + port*8, 0);
7578 bnx2x_init_block(bp, BLOCK_HC, init_phase);
7580 bnx2x_init_block(bp, BLOCK_IGU, init_phase);
7582 bnx2x_init_block(bp, BLOCK_MISC_AEU, init_phase);
7583 /* init aeu_mask_attn_func_0/1:
7584 * - SF mode: bits 3-7 are masked. Only bits 0-2 are in use
7585 * - MF mode: bit 3 is masked. Bits 0-2 are in use as in SF
7586 * bits 4-7 are used for "per vn group attention" */
7587 val = IS_MF(bp) ? 0xF7 : 0x7;
7588 /* Enable DCBX attention for all but E1 */
7589 val |= CHIP_IS_E1(bp) ? 0 : 0x10;
7590 REG_WR(bp, MISC_REG_AEU_MASK_ATTN_FUNC_0 + port*4, val);
7592 /* SCPAD_PARITY should NOT trigger close the gates */
7593 reg = port ? MISC_REG_AEU_ENABLE4_NIG_1 : MISC_REG_AEU_ENABLE4_NIG_0;
7596 ~AEU_INPUTS_ATTN_BITS_MCP_LATCHED_SCPAD_PARITY);
7598 reg = port ? MISC_REG_AEU_ENABLE4_PXP_1 : MISC_REG_AEU_ENABLE4_PXP_0;
7601 ~AEU_INPUTS_ATTN_BITS_MCP_LATCHED_SCPAD_PARITY);
7603 bnx2x_init_block(bp, BLOCK_NIG, init_phase);
7605 if (!CHIP_IS_E1x(bp)) {
7606 /* Bit-map indicating which L2 hdrs may appear after the
7607 * basic Ethernet header
7610 REG_WR(bp, BP_PORT(bp) ?
7611 NIG_REG_P1_HDRS_AFTER_BASIC :
7612 NIG_REG_P0_HDRS_AFTER_BASIC, 0xE);
7614 REG_WR(bp, BP_PORT(bp) ?
7615 NIG_REG_P1_HDRS_AFTER_BASIC :
7616 NIG_REG_P0_HDRS_AFTER_BASIC,
7617 IS_MF_SD(bp) ? 7 : 6);
7620 REG_WR(bp, BP_PORT(bp) ?
7621 NIG_REG_LLH1_MF_MODE :
7622 NIG_REG_LLH_MF_MODE, IS_MF(bp));
7624 if (!CHIP_IS_E3(bp))
7625 REG_WR(bp, NIG_REG_XGXS_SERDES0_MODE_SEL + port*4, 1);
7627 if (!CHIP_IS_E1(bp)) {
7628 /* 0x2 disable mf_ov, 0x1 enable */
7629 REG_WR(bp, NIG_REG_LLH0_BRB1_DRV_MASK_MF + port*4,
7630 (IS_MF_SD(bp) ? 0x1 : 0x2));
7632 if (!CHIP_IS_E1x(bp)) {
7634 switch (bp->mf_mode) {
7635 case MULTI_FUNCTION_SD:
7638 case MULTI_FUNCTION_SI:
7639 case MULTI_FUNCTION_AFEX:
7644 REG_WR(bp, (BP_PORT(bp) ? NIG_REG_LLH1_CLS_TYPE :
7645 NIG_REG_LLH0_CLS_TYPE), val);
7648 REG_WR(bp, NIG_REG_LLFC_ENABLE_0 + port*4, 0);
7649 REG_WR(bp, NIG_REG_LLFC_OUT_EN_0 + port*4, 0);
7650 REG_WR(bp, NIG_REG_PAUSE_ENABLE_0 + port*4, 1);
7654 /* If SPIO5 is set to generate interrupts, enable it for this port */
7655 val = REG_RD(bp, MISC_REG_SPIO_EVENT_EN);
7656 if (val & MISC_SPIO_SPIO5) {
7657 u32 reg_addr = (port ? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_0 :
7658 MISC_REG_AEU_ENABLE1_FUNC_0_OUT_0);
7659 val = REG_RD(bp, reg_addr);
7660 val |= AEU_INPUTS_ATTN_BITS_SPIO5;
7661 REG_WR(bp, reg_addr, val);
7667 static void bnx2x_ilt_wr(struct bnx2x *bp, u32 index, dma_addr_t addr)
7673 reg = PXP2_REG_RQ_ONCHIP_AT + index*8;
7675 reg = PXP2_REG_RQ_ONCHIP_AT_B0 + index*8;
7677 wb_write[0] = ONCHIP_ADDR1(addr);
7678 wb_write[1] = ONCHIP_ADDR2(addr);
7679 REG_WR_DMAE(bp, reg, wb_write, 2);
7682 void bnx2x_igu_clear_sb_gen(struct bnx2x *bp, u8 func, u8 idu_sb_id, bool is_pf)
7684 u32 data, ctl, cnt = 100;
7685 u32 igu_addr_data = IGU_REG_COMMAND_REG_32LSB_DATA;
7686 u32 igu_addr_ctl = IGU_REG_COMMAND_REG_CTRL;
7687 u32 igu_addr_ack = IGU_REG_CSTORM_TYPE_0_SB_CLEANUP + (idu_sb_id/32)*4;
7688 u32 sb_bit = 1 << (idu_sb_id%32);
7689 u32 func_encode = func | (is_pf ? 1 : 0) << IGU_FID_ENCODE_IS_PF_SHIFT;
7690 u32 addr_encode = IGU_CMD_E2_PROD_UPD_BASE + idu_sb_id;
7692 /* Not supported in BC mode */
7693 if (CHIP_INT_MODE_IS_BC(bp))
7696 data = (IGU_USE_REGISTER_cstorm_type_0_sb_cleanup
7697 << IGU_REGULAR_CLEANUP_TYPE_SHIFT) |
7698 IGU_REGULAR_CLEANUP_SET |
7699 IGU_REGULAR_BCLEANUP;
7701 ctl = addr_encode << IGU_CTRL_REG_ADDRESS_SHIFT |
7702 func_encode << IGU_CTRL_REG_FID_SHIFT |
7703 IGU_CTRL_CMD_TYPE_WR << IGU_CTRL_REG_TYPE_SHIFT;
7705 DP(NETIF_MSG_HW, "write 0x%08x to IGU(via GRC) addr 0x%x\n",
7706 data, igu_addr_data);
7707 REG_WR(bp, igu_addr_data, data);
7710 DP(NETIF_MSG_HW, "write 0x%08x to IGU(via GRC) addr 0x%x\n",
7712 REG_WR(bp, igu_addr_ctl, ctl);
7716 /* wait for clean up to finish */
7717 while (!(REG_RD(bp, igu_addr_ack) & sb_bit) && --cnt)
7720 if (!(REG_RD(bp, igu_addr_ack) & sb_bit)) {
7722 "Unable to finish IGU cleanup: idu_sb_id %d offset %d bit %d (cnt %d)\n",
7723 idu_sb_id, idu_sb_id/32, idu_sb_id%32, cnt);
7727 static void bnx2x_igu_clear_sb(struct bnx2x *bp, u8 idu_sb_id)
7729 bnx2x_igu_clear_sb_gen(bp, BP_FUNC(bp), idu_sb_id, true /*PF*/);
7732 static void bnx2x_clear_func_ilt(struct bnx2x *bp, u32 func)
7734 u32 i, base = FUNC_ILT_BASE(func);
7735 for (i = base; i < base + ILT_PER_FUNC; i++)
7736 bnx2x_ilt_wr(bp, i, 0);
7739 static void bnx2x_init_searcher(struct bnx2x *bp)
7741 int port = BP_PORT(bp);
7742 bnx2x_src_init_t2(bp, bp->t2, bp->t2_mapping, SRC_CONN_NUM);
7743 /* T1 hash bits value determines the T1 number of entries */
7744 REG_WR(bp, SRC_REG_NUMBER_HASH_BITS0 + port*4, SRC_HASH_BITS);
7747 static inline int bnx2x_func_switch_update(struct bnx2x *bp, int suspend)
7750 struct bnx2x_func_state_params func_params = {NULL};
7751 struct bnx2x_func_switch_update_params *switch_update_params =
7752 &func_params.params.switch_update;
7754 /* Prepare parameters for function state transitions */
7755 __set_bit(RAMROD_COMP_WAIT, &func_params.ramrod_flags);
7756 __set_bit(RAMROD_RETRY, &func_params.ramrod_flags);
7758 func_params.f_obj = &bp->func_obj;
7759 func_params.cmd = BNX2X_F_CMD_SWITCH_UPDATE;
7761 /* Function parameters */
7762 __set_bit(BNX2X_F_UPDATE_TX_SWITCH_SUSPEND_CHNG,
7763 &switch_update_params->changes);
7765 __set_bit(BNX2X_F_UPDATE_TX_SWITCH_SUSPEND,
7766 &switch_update_params->changes);
7768 rc = bnx2x_func_state_change(bp, &func_params);
7773 static int bnx2x_reset_nic_mode(struct bnx2x *bp)
7775 int rc, i, port = BP_PORT(bp);
7776 int vlan_en = 0, mac_en[NUM_MACS];
7778 /* Close input from network */
7779 if (bp->mf_mode == SINGLE_FUNCTION) {
7780 bnx2x_set_rx_filter(&bp->link_params, 0);
7782 vlan_en = REG_RD(bp, port ? NIG_REG_LLH1_FUNC_EN :
7783 NIG_REG_LLH0_FUNC_EN);
7784 REG_WR(bp, port ? NIG_REG_LLH1_FUNC_EN :
7785 NIG_REG_LLH0_FUNC_EN, 0);
7786 for (i = 0; i < NUM_MACS; i++) {
7787 mac_en[i] = REG_RD(bp, port ?
7788 (NIG_REG_LLH1_FUNC_MEM_ENABLE +
7790 (NIG_REG_LLH0_FUNC_MEM_ENABLE +
7792 REG_WR(bp, port ? (NIG_REG_LLH1_FUNC_MEM_ENABLE +
7794 (NIG_REG_LLH0_FUNC_MEM_ENABLE + 4 * i), 0);
7798 /* Close BMC to host */
7799 REG_WR(bp, port ? NIG_REG_P0_TX_MNG_HOST_ENABLE :
7800 NIG_REG_P1_TX_MNG_HOST_ENABLE, 0);
7802 /* Suspend Tx switching to the PF. Completion of this ramrod
7803 * further guarantees that all the packets of that PF / child
7804 * VFs in BRB were processed by the Parser, so it is safe to
7805 * change the NIC_MODE register.
7807 rc = bnx2x_func_switch_update(bp, 1);
7809 BNX2X_ERR("Can't suspend tx-switching!\n");
7813 /* Change NIC_MODE register */
7814 REG_WR(bp, PRS_REG_NIC_MODE, 0);
7816 /* Open input from network */
7817 if (bp->mf_mode == SINGLE_FUNCTION) {
7818 bnx2x_set_rx_filter(&bp->link_params, 1);
7820 REG_WR(bp, port ? NIG_REG_LLH1_FUNC_EN :
7821 NIG_REG_LLH0_FUNC_EN, vlan_en);
7822 for (i = 0; i < NUM_MACS; i++) {
7823 REG_WR(bp, port ? (NIG_REG_LLH1_FUNC_MEM_ENABLE +
7825 (NIG_REG_LLH0_FUNC_MEM_ENABLE + 4 * i),
7830 /* Enable BMC to host */
7831 REG_WR(bp, port ? NIG_REG_P0_TX_MNG_HOST_ENABLE :
7832 NIG_REG_P1_TX_MNG_HOST_ENABLE, 1);
7834 /* Resume Tx switching to the PF */
7835 rc = bnx2x_func_switch_update(bp, 0);
7837 BNX2X_ERR("Can't resume tx-switching!\n");
7841 DP(NETIF_MSG_IFUP, "NIC MODE disabled\n");
7845 int bnx2x_init_hw_func_cnic(struct bnx2x *bp)
7849 bnx2x_ilt_init_op_cnic(bp, INITOP_SET);
7851 if (CONFIGURE_NIC_MODE(bp)) {
7852 /* Configure searcher as part of function hw init */
7853 bnx2x_init_searcher(bp);
7855 /* Reset NIC mode */
7856 rc = bnx2x_reset_nic_mode(bp);
7858 BNX2X_ERR("Can't change NIC mode!\n");
7865 /* previous driver DMAE transaction may have occurred when pre-boot stage ended
7866 * and boot began, or when kdump kernel was loaded. Either case would invalidate
7867 * the addresses of the transaction, resulting in was-error bit set in the pci
7868 * causing all hw-to-host pcie transactions to timeout. If this happened we want
7869 * to clear the interrupt which detected this from the pglueb and the was done
7872 static void bnx2x_clean_pglue_errors(struct bnx2x *bp)
7874 if (!CHIP_IS_E1x(bp))
7875 REG_WR(bp, PGLUE_B_REG_WAS_ERROR_PF_7_0_CLR,
7876 1 << BP_ABS_FUNC(bp));
7879 static int bnx2x_init_hw_func(struct bnx2x *bp)
7881 int port = BP_PORT(bp);
7882 int func = BP_FUNC(bp);
7883 int init_phase = PHASE_PF0 + func;
7884 struct bnx2x_ilt *ilt = BP_ILT(bp);
7887 u32 main_mem_base, main_mem_size, main_mem_prty_clr;
7888 int i, main_mem_width, rc;
7890 DP(NETIF_MSG_HW, "starting func init func %d\n", func);
7892 /* FLR cleanup - hmmm */
7893 if (!CHIP_IS_E1x(bp)) {
7894 rc = bnx2x_pf_flr_clnup(bp);
7901 /* set MSI reconfigure capability */
7902 if (bp->common.int_block == INT_BLOCK_HC) {
7903 addr = (port ? HC_REG_CONFIG_1 : HC_REG_CONFIG_0);
7904 val = REG_RD(bp, addr);
7905 val |= HC_CONFIG_0_REG_MSI_ATTN_EN_0;
7906 REG_WR(bp, addr, val);
7909 bnx2x_init_block(bp, BLOCK_PXP, init_phase);
7910 bnx2x_init_block(bp, BLOCK_PXP2, init_phase);
7913 cdu_ilt_start = ilt->clients[ILT_CLIENT_CDU].start;
7916 cdu_ilt_start += BNX2X_FIRST_VF_CID/ILT_PAGE_CIDS;
7917 cdu_ilt_start = bnx2x_iov_init_ilt(bp, cdu_ilt_start);
7919 /* since BNX2X_FIRST_VF_CID > 0 the PF L2 cids precedes
7920 * those of the VFs, so start line should be reset
7922 cdu_ilt_start = ilt->clients[ILT_CLIENT_CDU].start;
7923 for (i = 0; i < L2_ILT_LINES(bp); i++) {
7924 ilt->lines[cdu_ilt_start + i].page = bp->context[i].vcxt;
7925 ilt->lines[cdu_ilt_start + i].page_mapping =
7926 bp->context[i].cxt_mapping;
7927 ilt->lines[cdu_ilt_start + i].size = bp->context[i].size;
7930 bnx2x_ilt_init_op(bp, INITOP_SET);
7932 if (!CONFIGURE_NIC_MODE(bp)) {
7933 bnx2x_init_searcher(bp);
7934 REG_WR(bp, PRS_REG_NIC_MODE, 0);
7935 DP(NETIF_MSG_IFUP, "NIC MODE disabled\n");
7938 REG_WR(bp, PRS_REG_NIC_MODE, 1);
7939 DP(NETIF_MSG_IFUP, "NIC MODE configured\n");
7942 if (!CHIP_IS_E1x(bp)) {
7943 u32 pf_conf = IGU_PF_CONF_FUNC_EN;
7945 /* Turn on a single ISR mode in IGU if driver is going to use
7948 if (!(bp->flags & USING_MSIX_FLAG))
7949 pf_conf |= IGU_PF_CONF_SINGLE_ISR_EN;
7951 * Timers workaround bug: function init part.
7952 * Need to wait 20msec after initializing ILT,
7953 * needed to make sure there are no requests in
7954 * one of the PXP internal queues with "old" ILT addresses
7958 * Master enable - Due to WB DMAE writes performed before this
7959 * register is re-initialized as part of the regular function
7962 REG_WR(bp, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, 1);
7963 /* Enable the function in IGU */
7964 REG_WR(bp, IGU_REG_PF_CONFIGURATION, pf_conf);
7969 bnx2x_init_block(bp, BLOCK_PGLUE_B, init_phase);
7971 bnx2x_clean_pglue_errors(bp);
7973 bnx2x_init_block(bp, BLOCK_ATC, init_phase);
7974 bnx2x_init_block(bp, BLOCK_DMAE, init_phase);
7975 bnx2x_init_block(bp, BLOCK_NIG, init_phase);
7976 bnx2x_init_block(bp, BLOCK_SRC, init_phase);
7977 bnx2x_init_block(bp, BLOCK_MISC, init_phase);
7978 bnx2x_init_block(bp, BLOCK_TCM, init_phase);
7979 bnx2x_init_block(bp, BLOCK_UCM, init_phase);
7980 bnx2x_init_block(bp, BLOCK_CCM, init_phase);
7981 bnx2x_init_block(bp, BLOCK_XCM, init_phase);
7982 bnx2x_init_block(bp, BLOCK_TSEM, init_phase);
7983 bnx2x_init_block(bp, BLOCK_USEM, init_phase);
7984 bnx2x_init_block(bp, BLOCK_CSEM, init_phase);
7985 bnx2x_init_block(bp, BLOCK_XSEM, init_phase);
7987 if (!CHIP_IS_E1x(bp))
7988 REG_WR(bp, QM_REG_PF_EN, 1);
7990 if (!CHIP_IS_E1x(bp)) {
7991 REG_WR(bp, TSEM_REG_VFPF_ERR_NUM, BNX2X_MAX_NUM_OF_VFS + func);
7992 REG_WR(bp, USEM_REG_VFPF_ERR_NUM, BNX2X_MAX_NUM_OF_VFS + func);
7993 REG_WR(bp, CSEM_REG_VFPF_ERR_NUM, BNX2X_MAX_NUM_OF_VFS + func);
7994 REG_WR(bp, XSEM_REG_VFPF_ERR_NUM, BNX2X_MAX_NUM_OF_VFS + func);
7996 bnx2x_init_block(bp, BLOCK_QM, init_phase);
7998 bnx2x_init_block(bp, BLOCK_TM, init_phase);
7999 bnx2x_init_block(bp, BLOCK_DORQ, init_phase);
8000 REG_WR(bp, DORQ_REG_MODE_ACT, 1); /* no dpm */
8002 bnx2x_iov_init_dq(bp);
8004 bnx2x_init_block(bp, BLOCK_BRB1, init_phase);
8005 bnx2x_init_block(bp, BLOCK_PRS, init_phase);
8006 bnx2x_init_block(bp, BLOCK_TSDM, init_phase);
8007 bnx2x_init_block(bp, BLOCK_CSDM, init_phase);
8008 bnx2x_init_block(bp, BLOCK_USDM, init_phase);
8009 bnx2x_init_block(bp, BLOCK_XSDM, init_phase);
8010 bnx2x_init_block(bp, BLOCK_UPB, init_phase);
8011 bnx2x_init_block(bp, BLOCK_XPB, init_phase);
8012 bnx2x_init_block(bp, BLOCK_PBF, init_phase);
8013 if (!CHIP_IS_E1x(bp))
8014 REG_WR(bp, PBF_REG_DISABLE_PF, 0);
8016 bnx2x_init_block(bp, BLOCK_CDU, init_phase);
8018 bnx2x_init_block(bp, BLOCK_CFC, init_phase);
8020 if (!CHIP_IS_E1x(bp))
8021 REG_WR(bp, CFC_REG_WEAK_ENABLE_PF, 1);
8024 if (!(IS_MF_UFP(bp) && BNX2X_IS_MF_SD_PROTOCOL_FCOE(bp))) {
8025 REG_WR(bp, NIG_REG_LLH0_FUNC_EN + port * 8, 1);
8026 REG_WR(bp, NIG_REG_LLH0_FUNC_VLAN_ID + port * 8,
8031 bnx2x_init_block(bp, BLOCK_MISC_AEU, init_phase);
8033 /* HC init per function */
8034 if (bp->common.int_block == INT_BLOCK_HC) {
8035 if (CHIP_IS_E1H(bp)) {
8036 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_12 + func*4, 0);
8038 REG_WR(bp, HC_REG_LEADING_EDGE_0 + port*8, 0);
8039 REG_WR(bp, HC_REG_TRAILING_EDGE_0 + port*8, 0);
8041 bnx2x_init_block(bp, BLOCK_HC, init_phase);
8044 int num_segs, sb_idx, prod_offset;
8046 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_12 + func*4, 0);
8048 if (!CHIP_IS_E1x(bp)) {
8049 REG_WR(bp, IGU_REG_LEADING_EDGE_LATCH, 0);
8050 REG_WR(bp, IGU_REG_TRAILING_EDGE_LATCH, 0);
8053 bnx2x_init_block(bp, BLOCK_IGU, init_phase);
8055 if (!CHIP_IS_E1x(bp)) {
8059 * E2 mode: address 0-135 match to the mapping memory;
8060 * 136 - PF0 default prod; 137 - PF1 default prod;
8061 * 138 - PF2 default prod; 139 - PF3 default prod;
8062 * 140 - PF0 attn prod; 141 - PF1 attn prod;
8063 * 142 - PF2 attn prod; 143 - PF3 attn prod;
8066 * E1.5 mode - In backward compatible mode;
8067 * for non default SB; each even line in the memory
8068 * holds the U producer and each odd line hold
8069 * the C producer. The first 128 producers are for
8070 * NDSB (PF0 - 0-31; PF1 - 32-63 and so on). The last 20
8071 * producers are for the DSB for each PF.
8072 * Each PF has five segments: (the order inside each
8073 * segment is PF0; PF1; PF2; PF3) - 128-131 U prods;
8074 * 132-135 C prods; 136-139 X prods; 140-143 T prods;
8075 * 144-147 attn prods;
8077 /* non-default-status-blocks */
8078 num_segs = CHIP_INT_MODE_IS_BC(bp) ?
8079 IGU_BC_NDSB_NUM_SEGS : IGU_NORM_NDSB_NUM_SEGS;
8080 for (sb_idx = 0; sb_idx < bp->igu_sb_cnt; sb_idx++) {
8081 prod_offset = (bp->igu_base_sb + sb_idx) *
8084 for (i = 0; i < num_segs; i++) {
8085 addr = IGU_REG_PROD_CONS_MEMORY +
8086 (prod_offset + i) * 4;
8087 REG_WR(bp, addr, 0);
8089 /* send consumer update with value 0 */
8090 bnx2x_ack_sb(bp, bp->igu_base_sb + sb_idx,
8091 USTORM_ID, 0, IGU_INT_NOP, 1);
8092 bnx2x_igu_clear_sb(bp,
8093 bp->igu_base_sb + sb_idx);
8096 /* default-status-blocks */
8097 num_segs = CHIP_INT_MODE_IS_BC(bp) ?
8098 IGU_BC_DSB_NUM_SEGS : IGU_NORM_DSB_NUM_SEGS;
8100 if (CHIP_MODE_IS_4_PORT(bp))
8101 dsb_idx = BP_FUNC(bp);
8103 dsb_idx = BP_VN(bp);
8105 prod_offset = (CHIP_INT_MODE_IS_BC(bp) ?
8106 IGU_BC_BASE_DSB_PROD + dsb_idx :
8107 IGU_NORM_BASE_DSB_PROD + dsb_idx);
8110 * igu prods come in chunks of E1HVN_MAX (4) -
8111 * does not matters what is the current chip mode
8113 for (i = 0; i < (num_segs * E1HVN_MAX);
8115 addr = IGU_REG_PROD_CONS_MEMORY +
8116 (prod_offset + i)*4;
8117 REG_WR(bp, addr, 0);
8119 /* send consumer update with 0 */
8120 if (CHIP_INT_MODE_IS_BC(bp)) {
8121 bnx2x_ack_sb(bp, bp->igu_dsb_id,
8122 USTORM_ID, 0, IGU_INT_NOP, 1);
8123 bnx2x_ack_sb(bp, bp->igu_dsb_id,
8124 CSTORM_ID, 0, IGU_INT_NOP, 1);
8125 bnx2x_ack_sb(bp, bp->igu_dsb_id,
8126 XSTORM_ID, 0, IGU_INT_NOP, 1);
8127 bnx2x_ack_sb(bp, bp->igu_dsb_id,
8128 TSTORM_ID, 0, IGU_INT_NOP, 1);
8129 bnx2x_ack_sb(bp, bp->igu_dsb_id,
8130 ATTENTION_ID, 0, IGU_INT_NOP, 1);
8132 bnx2x_ack_sb(bp, bp->igu_dsb_id,
8133 USTORM_ID, 0, IGU_INT_NOP, 1);
8134 bnx2x_ack_sb(bp, bp->igu_dsb_id,
8135 ATTENTION_ID, 0, IGU_INT_NOP, 1);
8137 bnx2x_igu_clear_sb(bp, bp->igu_dsb_id);
8139 /* !!! These should become driver const once
8140 rf-tool supports split-68 const */
8141 REG_WR(bp, IGU_REG_SB_INT_BEFORE_MASK_LSB, 0);
8142 REG_WR(bp, IGU_REG_SB_INT_BEFORE_MASK_MSB, 0);
8143 REG_WR(bp, IGU_REG_SB_MASK_LSB, 0);
8144 REG_WR(bp, IGU_REG_SB_MASK_MSB, 0);
8145 REG_WR(bp, IGU_REG_PBA_STATUS_LSB, 0);
8146 REG_WR(bp, IGU_REG_PBA_STATUS_MSB, 0);
8150 /* Reset PCIE errors for debug */
8151 REG_WR(bp, 0x2114, 0xffffffff);
8152 REG_WR(bp, 0x2120, 0xffffffff);
8154 if (CHIP_IS_E1x(bp)) {
8155 main_mem_size = HC_REG_MAIN_MEMORY_SIZE / 2; /*dwords*/
8156 main_mem_base = HC_REG_MAIN_MEMORY +
8157 BP_PORT(bp) * (main_mem_size * 4);
8158 main_mem_prty_clr = HC_REG_HC_PRTY_STS_CLR;
8161 val = REG_RD(bp, main_mem_prty_clr);
8164 "Hmmm... Parity errors in HC block during function init (0x%x)!\n",
8167 /* Clear "false" parity errors in MSI-X table */
8168 for (i = main_mem_base;
8169 i < main_mem_base + main_mem_size * 4;
8170 i += main_mem_width) {
8171 bnx2x_read_dmae(bp, i, main_mem_width / 4);
8172 bnx2x_write_dmae(bp, bnx2x_sp_mapping(bp, wb_data),
8173 i, main_mem_width / 4);
8175 /* Clear HC parity attention */
8176 REG_RD(bp, main_mem_prty_clr);
8179 #ifdef BNX2X_STOP_ON_ERROR
8180 /* Enable STORMs SP logging */
8181 REG_WR8(bp, BAR_USTRORM_INTMEM +
8182 USTORM_RECORD_SLOW_PATH_OFFSET(BP_FUNC(bp)), 1);
8183 REG_WR8(bp, BAR_TSTRORM_INTMEM +
8184 TSTORM_RECORD_SLOW_PATH_OFFSET(BP_FUNC(bp)), 1);
8185 REG_WR8(bp, BAR_CSTRORM_INTMEM +
8186 CSTORM_RECORD_SLOW_PATH_OFFSET(BP_FUNC(bp)), 1);
8187 REG_WR8(bp, BAR_XSTRORM_INTMEM +
8188 XSTORM_RECORD_SLOW_PATH_OFFSET(BP_FUNC(bp)), 1);
8191 bnx2x_phy_probe(&bp->link_params);
8196 void bnx2x_free_mem_cnic(struct bnx2x *bp)
8198 bnx2x_ilt_mem_op_cnic(bp, ILT_MEMOP_FREE);
8200 if (!CHIP_IS_E1x(bp))
8201 BNX2X_PCI_FREE(bp->cnic_sb.e2_sb, bp->cnic_sb_mapping,
8202 sizeof(struct host_hc_status_block_e2));
8204 BNX2X_PCI_FREE(bp->cnic_sb.e1x_sb, bp->cnic_sb_mapping,
8205 sizeof(struct host_hc_status_block_e1x));
8207 BNX2X_PCI_FREE(bp->t2, bp->t2_mapping, SRC_T2_SZ);
8210 void bnx2x_free_mem(struct bnx2x *bp)
8214 BNX2X_PCI_FREE(bp->fw_stats, bp->fw_stats_mapping,
8215 bp->fw_stats_data_sz + bp->fw_stats_req_sz);
8220 BNX2X_PCI_FREE(bp->def_status_blk, bp->def_status_blk_mapping,
8221 sizeof(struct host_sp_status_block));
8223 BNX2X_PCI_FREE(bp->slowpath, bp->slowpath_mapping,
8224 sizeof(struct bnx2x_slowpath));
8226 for (i = 0; i < L2_ILT_LINES(bp); i++)
8227 BNX2X_PCI_FREE(bp->context[i].vcxt, bp->context[i].cxt_mapping,
8228 bp->context[i].size);
8229 bnx2x_ilt_mem_op(bp, ILT_MEMOP_FREE);
8231 BNX2X_FREE(bp->ilt->lines);
8233 BNX2X_PCI_FREE(bp->spq, bp->spq_mapping, BCM_PAGE_SIZE);
8235 BNX2X_PCI_FREE(bp->eq_ring, bp->eq_mapping,
8236 BCM_PAGE_SIZE * NUM_EQ_PAGES);
8238 BNX2X_PCI_FREE(bp->t2, bp->t2_mapping, SRC_T2_SZ);
8240 bnx2x_iov_free_mem(bp);
8243 int bnx2x_alloc_mem_cnic(struct bnx2x *bp)
8245 if (!CHIP_IS_E1x(bp)) {
8246 /* size = the status block + ramrod buffers */
8247 bp->cnic_sb.e2_sb = BNX2X_PCI_ALLOC(&bp->cnic_sb_mapping,
8248 sizeof(struct host_hc_status_block_e2));
8249 if (!bp->cnic_sb.e2_sb)
8252 bp->cnic_sb.e1x_sb = BNX2X_PCI_ALLOC(&bp->cnic_sb_mapping,
8253 sizeof(struct host_hc_status_block_e1x));
8254 if (!bp->cnic_sb.e1x_sb)
8258 if (CONFIGURE_NIC_MODE(bp) && !bp->t2) {
8259 /* allocate searcher T2 table, as it wasn't allocated before */
8260 bp->t2 = BNX2X_PCI_ALLOC(&bp->t2_mapping, SRC_T2_SZ);
8265 /* write address to which L5 should insert its values */
8266 bp->cnic_eth_dev.addr_drv_info_to_mcp =
8267 &bp->slowpath->drv_info_to_mcp;
8269 if (bnx2x_ilt_mem_op_cnic(bp, ILT_MEMOP_ALLOC))
8275 bnx2x_free_mem_cnic(bp);
8276 BNX2X_ERR("Can't allocate memory\n");
8280 int bnx2x_alloc_mem(struct bnx2x *bp)
8282 int i, allocated, context_size;
8284 if (!CONFIGURE_NIC_MODE(bp) && !bp->t2) {
8285 /* allocate searcher T2 table */
8286 bp->t2 = BNX2X_PCI_ALLOC(&bp->t2_mapping, SRC_T2_SZ);
8291 bp->def_status_blk = BNX2X_PCI_ALLOC(&bp->def_status_blk_mapping,
8292 sizeof(struct host_sp_status_block));
8293 if (!bp->def_status_blk)
8296 bp->slowpath = BNX2X_PCI_ALLOC(&bp->slowpath_mapping,
8297 sizeof(struct bnx2x_slowpath));
8301 /* Allocate memory for CDU context:
8302 * This memory is allocated separately and not in the generic ILT
8303 * functions because CDU differs in few aspects:
8304 * 1. There are multiple entities allocating memory for context -
8305 * 'regular' driver, CNIC and SRIOV driver. Each separately controls
8306 * its own ILT lines.
8307 * 2. Since CDU page-size is not a single 4KB page (which is the case
8308 * for the other ILT clients), to be efficient we want to support
8309 * allocation of sub-page-size in the last entry.
8310 * 3. Context pointers are used by the driver to pass to FW / update
8311 * the context (for the other ILT clients the pointers are used just to
8312 * free the memory during unload).
8314 context_size = sizeof(union cdu_context) * BNX2X_L2_CID_COUNT(bp);
8316 for (i = 0, allocated = 0; allocated < context_size; i++) {
8317 bp->context[i].size = min(CDU_ILT_PAGE_SZ,
8318 (context_size - allocated));
8319 bp->context[i].vcxt = BNX2X_PCI_ALLOC(&bp->context[i].cxt_mapping,
8320 bp->context[i].size);
8321 if (!bp->context[i].vcxt)
8323 allocated += bp->context[i].size;
8325 bp->ilt->lines = kcalloc(ILT_MAX_LINES, sizeof(struct ilt_line),
8327 if (!bp->ilt->lines)
8330 if (bnx2x_ilt_mem_op(bp, ILT_MEMOP_ALLOC))
8333 if (bnx2x_iov_alloc_mem(bp))
8336 /* Slow path ring */
8337 bp->spq = BNX2X_PCI_ALLOC(&bp->spq_mapping, BCM_PAGE_SIZE);
8342 bp->eq_ring = BNX2X_PCI_ALLOC(&bp->eq_mapping,
8343 BCM_PAGE_SIZE * NUM_EQ_PAGES);
8351 BNX2X_ERR("Can't allocate memory\n");
8356 * Init service functions
8359 int bnx2x_set_mac_one(struct bnx2x *bp, u8 *mac,
8360 struct bnx2x_vlan_mac_obj *obj, bool set,
8361 int mac_type, unsigned long *ramrod_flags)
8364 struct bnx2x_vlan_mac_ramrod_params ramrod_param;
8366 memset(&ramrod_param, 0, sizeof(ramrod_param));
8368 /* Fill general parameters */
8369 ramrod_param.vlan_mac_obj = obj;
8370 ramrod_param.ramrod_flags = *ramrod_flags;
8372 /* Fill a user request section if needed */
8373 if (!test_bit(RAMROD_CONT, ramrod_flags)) {
8374 memcpy(ramrod_param.user_req.u.mac.mac, mac, ETH_ALEN);
8376 __set_bit(mac_type, &ramrod_param.user_req.vlan_mac_flags);
8378 /* Set the command: ADD or DEL */
8380 ramrod_param.user_req.cmd = BNX2X_VLAN_MAC_ADD;
8382 ramrod_param.user_req.cmd = BNX2X_VLAN_MAC_DEL;
8385 rc = bnx2x_config_vlan_mac(bp, &ramrod_param);
8387 if (rc == -EEXIST) {
8388 DP(BNX2X_MSG_SP, "Failed to schedule ADD operations: %d\n", rc);
8389 /* do not treat adding same MAC as error */
8392 BNX2X_ERR("%s MAC failed\n", (set ? "Set" : "Del"));
8397 int bnx2x_del_all_macs(struct bnx2x *bp,
8398 struct bnx2x_vlan_mac_obj *mac_obj,
8399 int mac_type, bool wait_for_comp)
8402 unsigned long ramrod_flags = 0, vlan_mac_flags = 0;
8404 /* Wait for completion of requested */
8406 __set_bit(RAMROD_COMP_WAIT, &ramrod_flags);
8408 /* Set the mac type of addresses we want to clear */
8409 __set_bit(mac_type, &vlan_mac_flags);
8411 rc = mac_obj->delete_all(bp, mac_obj, &vlan_mac_flags, &ramrod_flags);
8413 BNX2X_ERR("Failed to delete MACs: %d\n", rc);
8418 int bnx2x_set_eth_mac(struct bnx2x *bp, bool set)
8421 unsigned long ramrod_flags = 0;
8423 DP(NETIF_MSG_IFUP, "Adding Eth MAC\n");
8424 __set_bit(RAMROD_COMP_WAIT, &ramrod_flags);
8425 return bnx2x_set_mac_one(bp, bp->dev->dev_addr,
8426 &bp->sp_objs->mac_obj, set,
8427 BNX2X_ETH_MAC, &ramrod_flags);
8429 return bnx2x_vfpf_config_mac(bp, bp->dev->dev_addr,
8430 bp->fp->index, true);
8434 int bnx2x_setup_leading(struct bnx2x *bp)
8437 return bnx2x_setup_queue(bp, &bp->fp[0], true);
8439 return bnx2x_vfpf_setup_q(bp, &bp->fp[0], true);
8443 * bnx2x_set_int_mode - configure interrupt mode
8445 * @bp: driver handle
8447 * In case of MSI-X it will also try to enable MSI-X.
8449 int bnx2x_set_int_mode(struct bnx2x *bp)
8453 if (IS_VF(bp) && int_mode != BNX2X_INT_MODE_MSIX) {
8454 BNX2X_ERR("VF not loaded since interrupt mode not msix\n");
8459 case BNX2X_INT_MODE_MSIX:
8460 /* attempt to enable msix */
8461 rc = bnx2x_enable_msix(bp);
8467 /* vfs use only msix */
8468 if (rc && IS_VF(bp))
8471 /* failed to enable multiple MSI-X */
8472 BNX2X_DEV_INFO("Failed to enable multiple MSI-X (%d), set number of queues to %d\n",
8474 1 + bp->num_cnic_queues);
8476 /* falling through... */
8477 case BNX2X_INT_MODE_MSI:
8478 bnx2x_enable_msi(bp);
8480 /* falling through... */
8481 case BNX2X_INT_MODE_INTX:
8482 bp->num_ethernet_queues = 1;
8483 bp->num_queues = bp->num_ethernet_queues + bp->num_cnic_queues;
8484 BNX2X_DEV_INFO("set number of queues to 1\n");
8487 BNX2X_DEV_INFO("unknown value in int_mode module parameter\n");
8493 /* must be called prior to any HW initializations */
8494 static inline u16 bnx2x_cid_ilt_lines(struct bnx2x *bp)
8497 return (BNX2X_FIRST_VF_CID + BNX2X_VF_CIDS)/ILT_PAGE_CIDS;
8498 return L2_ILT_LINES(bp);
8501 void bnx2x_ilt_set_info(struct bnx2x *bp)
8503 struct ilt_client_info *ilt_client;
8504 struct bnx2x_ilt *ilt = BP_ILT(bp);
8507 ilt->start_line = FUNC_ILT_BASE(BP_FUNC(bp));
8508 DP(BNX2X_MSG_SP, "ilt starts at line %d\n", ilt->start_line);
8511 ilt_client = &ilt->clients[ILT_CLIENT_CDU];
8512 ilt_client->client_num = ILT_CLIENT_CDU;
8513 ilt_client->page_size = CDU_ILT_PAGE_SZ;
8514 ilt_client->flags = ILT_CLIENT_SKIP_MEM;
8515 ilt_client->start = line;
8516 line += bnx2x_cid_ilt_lines(bp);
8518 if (CNIC_SUPPORT(bp))
8519 line += CNIC_ILT_LINES;
8520 ilt_client->end = line - 1;
8522 DP(NETIF_MSG_IFUP, "ilt client[CDU]: start %d, end %d, psz 0x%x, flags 0x%x, hw psz %d\n",
8525 ilt_client->page_size,
8527 ilog2(ilt_client->page_size >> 12));
8530 if (QM_INIT(bp->qm_cid_count)) {
8531 ilt_client = &ilt->clients[ILT_CLIENT_QM];
8532 ilt_client->client_num = ILT_CLIENT_QM;
8533 ilt_client->page_size = QM_ILT_PAGE_SZ;
8534 ilt_client->flags = 0;
8535 ilt_client->start = line;
8537 /* 4 bytes for each cid */
8538 line += DIV_ROUND_UP(bp->qm_cid_count * QM_QUEUES_PER_FUNC * 4,
8541 ilt_client->end = line - 1;
8544 "ilt client[QM]: start %d, end %d, psz 0x%x, flags 0x%x, hw psz %d\n",
8547 ilt_client->page_size,
8549 ilog2(ilt_client->page_size >> 12));
8552 if (CNIC_SUPPORT(bp)) {
8554 ilt_client = &ilt->clients[ILT_CLIENT_SRC];
8555 ilt_client->client_num = ILT_CLIENT_SRC;
8556 ilt_client->page_size = SRC_ILT_PAGE_SZ;
8557 ilt_client->flags = 0;
8558 ilt_client->start = line;
8559 line += SRC_ILT_LINES;
8560 ilt_client->end = line - 1;
8563 "ilt client[SRC]: start %d, end %d, psz 0x%x, flags 0x%x, hw psz %d\n",
8566 ilt_client->page_size,
8568 ilog2(ilt_client->page_size >> 12));
8571 ilt_client = &ilt->clients[ILT_CLIENT_TM];
8572 ilt_client->client_num = ILT_CLIENT_TM;
8573 ilt_client->page_size = TM_ILT_PAGE_SZ;
8574 ilt_client->flags = 0;
8575 ilt_client->start = line;
8576 line += TM_ILT_LINES;
8577 ilt_client->end = line - 1;
8580 "ilt client[TM]: start %d, end %d, psz 0x%x, flags 0x%x, hw psz %d\n",
8583 ilt_client->page_size,
8585 ilog2(ilt_client->page_size >> 12));
8588 BUG_ON(line > ILT_MAX_LINES);
8592 * bnx2x_pf_q_prep_init - prepare INIT transition parameters
8594 * @bp: driver handle
8595 * @fp: pointer to fastpath
8596 * @init_params: pointer to parameters structure
8598 * parameters configured:
8599 * - HC configuration
8600 * - Queue's CDU context
8602 static void bnx2x_pf_q_prep_init(struct bnx2x *bp,
8603 struct bnx2x_fastpath *fp, struct bnx2x_queue_init_params *init_params)
8606 int cxt_index, cxt_offset;
8608 /* FCoE Queue uses Default SB, thus has no HC capabilities */
8609 if (!IS_FCOE_FP(fp)) {
8610 __set_bit(BNX2X_Q_FLG_HC, &init_params->rx.flags);
8611 __set_bit(BNX2X_Q_FLG_HC, &init_params->tx.flags);
8613 /* If HC is supported, enable host coalescing in the transition
8616 __set_bit(BNX2X_Q_FLG_HC_EN, &init_params->rx.flags);
8617 __set_bit(BNX2X_Q_FLG_HC_EN, &init_params->tx.flags);
8620 init_params->rx.hc_rate = bp->rx_ticks ?
8621 (1000000 / bp->rx_ticks) : 0;
8622 init_params->tx.hc_rate = bp->tx_ticks ?
8623 (1000000 / bp->tx_ticks) : 0;
8626 init_params->rx.fw_sb_id = init_params->tx.fw_sb_id =
8630 * CQ index among the SB indices: FCoE clients uses the default
8631 * SB, therefore it's different.
8633 init_params->rx.sb_cq_index = HC_INDEX_ETH_RX_CQ_CONS;
8634 init_params->tx.sb_cq_index = HC_INDEX_ETH_FIRST_TX_CQ_CONS;
8637 /* set maximum number of COSs supported by this queue */
8638 init_params->max_cos = fp->max_cos;
8640 DP(NETIF_MSG_IFUP, "fp: %d setting queue params max cos to: %d\n",
8641 fp->index, init_params->max_cos);
8643 /* set the context pointers queue object */
8644 for (cos = FIRST_TX_COS_INDEX; cos < init_params->max_cos; cos++) {
8645 cxt_index = fp->txdata_ptr[cos]->cid / ILT_PAGE_CIDS;
8646 cxt_offset = fp->txdata_ptr[cos]->cid - (cxt_index *
8648 init_params->cxts[cos] =
8649 &bp->context[cxt_index].vcxt[cxt_offset].eth;
8653 static int bnx2x_setup_tx_only(struct bnx2x *bp, struct bnx2x_fastpath *fp,
8654 struct bnx2x_queue_state_params *q_params,
8655 struct bnx2x_queue_setup_tx_only_params *tx_only_params,
8656 int tx_index, bool leading)
8658 memset(tx_only_params, 0, sizeof(*tx_only_params));
8660 /* Set the command */
8661 q_params->cmd = BNX2X_Q_CMD_SETUP_TX_ONLY;
8663 /* Set tx-only QUEUE flags: don't zero statistics */
8664 tx_only_params->flags = bnx2x_get_common_flags(bp, fp, false);
8666 /* choose the index of the cid to send the slow path on */
8667 tx_only_params->cid_index = tx_index;
8669 /* Set general TX_ONLY_SETUP parameters */
8670 bnx2x_pf_q_prep_general(bp, fp, &tx_only_params->gen_params, tx_index);
8672 /* Set Tx TX_ONLY_SETUP parameters */
8673 bnx2x_pf_tx_q_prep(bp, fp, &tx_only_params->txq_params, tx_index);
8676 "preparing to send tx-only ramrod for connection: cos %d, primary cid %d, cid %d, client id %d, sp-client id %d, flags %lx\n",
8677 tx_index, q_params->q_obj->cids[FIRST_TX_COS_INDEX],
8678 q_params->q_obj->cids[tx_index], q_params->q_obj->cl_id,
8679 tx_only_params->gen_params.spcl_id, tx_only_params->flags);
8681 /* send the ramrod */
8682 return bnx2x_queue_state_change(bp, q_params);
8686 * bnx2x_setup_queue - setup queue
8688 * @bp: driver handle
8689 * @fp: pointer to fastpath
8690 * @leading: is leading
8692 * This function performs 2 steps in a Queue state machine
8693 * actually: 1) RESET->INIT 2) INIT->SETUP
8696 int bnx2x_setup_queue(struct bnx2x *bp, struct bnx2x_fastpath *fp,
8699 struct bnx2x_queue_state_params q_params = {NULL};
8700 struct bnx2x_queue_setup_params *setup_params =
8701 &q_params.params.setup;
8702 struct bnx2x_queue_setup_tx_only_params *tx_only_params =
8703 &q_params.params.tx_only;
8707 DP(NETIF_MSG_IFUP, "setting up queue %d\n", fp->index);
8709 /* reset IGU state skip FCoE L2 queue */
8710 if (!IS_FCOE_FP(fp))
8711 bnx2x_ack_sb(bp, fp->igu_sb_id, USTORM_ID, 0,
8714 q_params.q_obj = &bnx2x_sp_obj(bp, fp).q_obj;
8715 /* We want to wait for completion in this context */
8716 __set_bit(RAMROD_COMP_WAIT, &q_params.ramrod_flags);
8718 /* Prepare the INIT parameters */
8719 bnx2x_pf_q_prep_init(bp, fp, &q_params.params.init);
8721 /* Set the command */
8722 q_params.cmd = BNX2X_Q_CMD_INIT;
8724 /* Change the state to INIT */
8725 rc = bnx2x_queue_state_change(bp, &q_params);
8727 BNX2X_ERR("Queue(%d) INIT failed\n", fp->index);
8731 DP(NETIF_MSG_IFUP, "init complete\n");
8733 /* Now move the Queue to the SETUP state... */
8734 memset(setup_params, 0, sizeof(*setup_params));
8736 /* Set QUEUE flags */
8737 setup_params->flags = bnx2x_get_q_flags(bp, fp, leading);
8739 /* Set general SETUP parameters */
8740 bnx2x_pf_q_prep_general(bp, fp, &setup_params->gen_params,
8741 FIRST_TX_COS_INDEX);
8743 bnx2x_pf_rx_q_prep(bp, fp, &setup_params->pause_params,
8744 &setup_params->rxq_params);
8746 bnx2x_pf_tx_q_prep(bp, fp, &setup_params->txq_params,
8747 FIRST_TX_COS_INDEX);
8749 /* Set the command */
8750 q_params.cmd = BNX2X_Q_CMD_SETUP;
8753 bp->fcoe_init = true;
8755 /* Change the state to SETUP */
8756 rc = bnx2x_queue_state_change(bp, &q_params);
8758 BNX2X_ERR("Queue(%d) SETUP failed\n", fp->index);
8762 /* loop through the relevant tx-only indices */
8763 for (tx_index = FIRST_TX_ONLY_COS_INDEX;
8764 tx_index < fp->max_cos;
8767 /* prepare and send tx-only ramrod*/
8768 rc = bnx2x_setup_tx_only(bp, fp, &q_params,
8769 tx_only_params, tx_index, leading);
8771 BNX2X_ERR("Queue(%d.%d) TX_ONLY_SETUP failed\n",
8772 fp->index, tx_index);
8780 static int bnx2x_stop_queue(struct bnx2x *bp, int index)
8782 struct bnx2x_fastpath *fp = &bp->fp[index];
8783 struct bnx2x_fp_txdata *txdata;
8784 struct bnx2x_queue_state_params q_params = {NULL};
8787 DP(NETIF_MSG_IFDOWN, "stopping queue %d cid %d\n", index, fp->cid);
8789 q_params.q_obj = &bnx2x_sp_obj(bp, fp).q_obj;
8790 /* We want to wait for completion in this context */
8791 __set_bit(RAMROD_COMP_WAIT, &q_params.ramrod_flags);
8793 /* close tx-only connections */
8794 for (tx_index = FIRST_TX_ONLY_COS_INDEX;
8795 tx_index < fp->max_cos;
8798 /* ascertain this is a normal queue*/
8799 txdata = fp->txdata_ptr[tx_index];
8801 DP(NETIF_MSG_IFDOWN, "stopping tx-only queue %d\n",
8804 /* send halt terminate on tx-only connection */
8805 q_params.cmd = BNX2X_Q_CMD_TERMINATE;
8806 memset(&q_params.params.terminate, 0,
8807 sizeof(q_params.params.terminate));
8808 q_params.params.terminate.cid_index = tx_index;
8810 rc = bnx2x_queue_state_change(bp, &q_params);
8814 /* send halt terminate on tx-only connection */
8815 q_params.cmd = BNX2X_Q_CMD_CFC_DEL;
8816 memset(&q_params.params.cfc_del, 0,
8817 sizeof(q_params.params.cfc_del));
8818 q_params.params.cfc_del.cid_index = tx_index;
8819 rc = bnx2x_queue_state_change(bp, &q_params);
8823 /* Stop the primary connection: */
8824 /* ...halt the connection */
8825 q_params.cmd = BNX2X_Q_CMD_HALT;
8826 rc = bnx2x_queue_state_change(bp, &q_params);
8830 /* ...terminate the connection */
8831 q_params.cmd = BNX2X_Q_CMD_TERMINATE;
8832 memset(&q_params.params.terminate, 0,
8833 sizeof(q_params.params.terminate));
8834 q_params.params.terminate.cid_index = FIRST_TX_COS_INDEX;
8835 rc = bnx2x_queue_state_change(bp, &q_params);
8838 /* ...delete cfc entry */
8839 q_params.cmd = BNX2X_Q_CMD_CFC_DEL;
8840 memset(&q_params.params.cfc_del, 0,
8841 sizeof(q_params.params.cfc_del));
8842 q_params.params.cfc_del.cid_index = FIRST_TX_COS_INDEX;
8843 return bnx2x_queue_state_change(bp, &q_params);
8846 static void bnx2x_reset_func(struct bnx2x *bp)
8848 int port = BP_PORT(bp);
8849 int func = BP_FUNC(bp);
8852 /* Disable the function in the FW */
8853 REG_WR8(bp, BAR_XSTRORM_INTMEM + XSTORM_FUNC_EN_OFFSET(func), 0);
8854 REG_WR8(bp, BAR_CSTRORM_INTMEM + CSTORM_FUNC_EN_OFFSET(func), 0);
8855 REG_WR8(bp, BAR_TSTRORM_INTMEM + TSTORM_FUNC_EN_OFFSET(func), 0);
8856 REG_WR8(bp, BAR_USTRORM_INTMEM + USTORM_FUNC_EN_OFFSET(func), 0);
8859 for_each_eth_queue(bp, i) {
8860 struct bnx2x_fastpath *fp = &bp->fp[i];
8861 REG_WR8(bp, BAR_CSTRORM_INTMEM +
8862 CSTORM_STATUS_BLOCK_DATA_STATE_OFFSET(fp->fw_sb_id),
8866 if (CNIC_LOADED(bp))
8868 REG_WR8(bp, BAR_CSTRORM_INTMEM +
8869 CSTORM_STATUS_BLOCK_DATA_STATE_OFFSET
8870 (bnx2x_cnic_fw_sb_id(bp)), SB_DISABLED);
8873 REG_WR8(bp, BAR_CSTRORM_INTMEM +
8874 CSTORM_SP_STATUS_BLOCK_DATA_STATE_OFFSET(func),
8877 for (i = 0; i < XSTORM_SPQ_DATA_SIZE / 4; i++)
8878 REG_WR(bp, BAR_XSTRORM_INTMEM + XSTORM_SPQ_DATA_OFFSET(func),
8882 if (bp->common.int_block == INT_BLOCK_HC) {
8883 REG_WR(bp, HC_REG_LEADING_EDGE_0 + port*8, 0);
8884 REG_WR(bp, HC_REG_TRAILING_EDGE_0 + port*8, 0);
8886 REG_WR(bp, IGU_REG_LEADING_EDGE_LATCH, 0);
8887 REG_WR(bp, IGU_REG_TRAILING_EDGE_LATCH, 0);
8890 if (CNIC_LOADED(bp)) {
8891 /* Disable Timer scan */
8892 REG_WR(bp, TM_REG_EN_LINEAR0_TIMER + port*4, 0);
8894 * Wait for at least 10ms and up to 2 second for the timers
8897 for (i = 0; i < 200; i++) {
8898 usleep_range(10000, 20000);
8899 if (!REG_RD(bp, TM_REG_LIN0_SCAN_ON + port*4))
8904 bnx2x_clear_func_ilt(bp, func);
8906 /* Timers workaround bug for E2: if this is vnic-3,
8907 * we need to set the entire ilt range for this timers.
8909 if (!CHIP_IS_E1x(bp) && BP_VN(bp) == 3) {
8910 struct ilt_client_info ilt_cli;
8911 /* use dummy TM client */
8912 memset(&ilt_cli, 0, sizeof(struct ilt_client_info));
8914 ilt_cli.end = ILT_NUM_PAGE_ENTRIES - 1;
8915 ilt_cli.client_num = ILT_CLIENT_TM;
8917 bnx2x_ilt_boundry_init_op(bp, &ilt_cli, 0, INITOP_CLEAR);
8920 /* this assumes that reset_port() called before reset_func()*/
8921 if (!CHIP_IS_E1x(bp))
8922 bnx2x_pf_disable(bp);
8927 static void bnx2x_reset_port(struct bnx2x *bp)
8929 int port = BP_PORT(bp);
8932 /* Reset physical Link */
8933 bnx2x__link_reset(bp);
8935 REG_WR(bp, NIG_REG_MASK_INTERRUPT_PORT0 + port*4, 0);
8937 /* Do not rcv packets to BRB */
8938 REG_WR(bp, NIG_REG_LLH0_BRB1_DRV_MASK + port*4, 0x0);
8939 /* Do not direct rcv packets that are not for MCP to the BRB */
8940 REG_WR(bp, (port ? NIG_REG_LLH1_BRB1_NOT_MCP :
8941 NIG_REG_LLH0_BRB1_NOT_MCP), 0x0);
8944 REG_WR(bp, MISC_REG_AEU_MASK_ATTN_FUNC_0 + port*4, 0);
8947 /* Check for BRB port occupancy */
8948 val = REG_RD(bp, BRB1_REG_PORT_NUM_OCC_BLOCKS_0 + port*4);
8950 DP(NETIF_MSG_IFDOWN,
8951 "BRB1 is not empty %d blocks are occupied\n", val);
8953 /* TODO: Close Doorbell port? */
8956 static int bnx2x_reset_hw(struct bnx2x *bp, u32 load_code)
8958 struct bnx2x_func_state_params func_params = {NULL};
8960 /* Prepare parameters for function state transitions */
8961 __set_bit(RAMROD_COMP_WAIT, &func_params.ramrod_flags);
8963 func_params.f_obj = &bp->func_obj;
8964 func_params.cmd = BNX2X_F_CMD_HW_RESET;
8966 func_params.params.hw_init.load_phase = load_code;
8968 return bnx2x_func_state_change(bp, &func_params);
8971 static int bnx2x_func_stop(struct bnx2x *bp)
8973 struct bnx2x_func_state_params func_params = {NULL};
8976 /* Prepare parameters for function state transitions */
8977 __set_bit(RAMROD_COMP_WAIT, &func_params.ramrod_flags);
8978 func_params.f_obj = &bp->func_obj;
8979 func_params.cmd = BNX2X_F_CMD_STOP;
8982 * Try to stop the function the 'good way'. If fails (in case
8983 * of a parity error during bnx2x_chip_cleanup()) and we are
8984 * not in a debug mode, perform a state transaction in order to
8985 * enable further HW_RESET transaction.
8987 rc = bnx2x_func_state_change(bp, &func_params);
8989 #ifdef BNX2X_STOP_ON_ERROR
8992 BNX2X_ERR("FUNC_STOP ramrod failed. Running a dry transaction\n");
8993 __set_bit(RAMROD_DRV_CLR_ONLY, &func_params.ramrod_flags);
8994 return bnx2x_func_state_change(bp, &func_params);
9002 * bnx2x_send_unload_req - request unload mode from the MCP.
9004 * @bp: driver handle
9005 * @unload_mode: requested function's unload mode
9007 * Return unload mode returned by the MCP: COMMON, PORT or FUNC.
9009 u32 bnx2x_send_unload_req(struct bnx2x *bp, int unload_mode)
9012 int port = BP_PORT(bp);
9014 /* Select the UNLOAD request mode */
9015 if (unload_mode == UNLOAD_NORMAL)
9016 reset_code = DRV_MSG_CODE_UNLOAD_REQ_WOL_DIS;
9018 else if (bp->flags & NO_WOL_FLAG)
9019 reset_code = DRV_MSG_CODE_UNLOAD_REQ_WOL_MCP;
9022 u32 emac_base = port ? GRCBASE_EMAC1 : GRCBASE_EMAC0;
9023 u8 *mac_addr = bp->dev->dev_addr;
9024 struct pci_dev *pdev = bp->pdev;
9028 /* The mac address is written to entries 1-4 to
9029 * preserve entry 0 which is used by the PMF
9031 u8 entry = (BP_VN(bp) + 1)*8;
9033 val = (mac_addr[0] << 8) | mac_addr[1];
9034 EMAC_WR(bp, EMAC_REG_EMAC_MAC_MATCH + entry, val);
9036 val = (mac_addr[2] << 24) | (mac_addr[3] << 16) |
9037 (mac_addr[4] << 8) | mac_addr[5];
9038 EMAC_WR(bp, EMAC_REG_EMAC_MAC_MATCH + entry + 4, val);
9040 /* Enable the PME and clear the status */
9041 pci_read_config_word(pdev, pdev->pm_cap + PCI_PM_CTRL, &pmc);
9042 pmc |= PCI_PM_CTRL_PME_ENABLE | PCI_PM_CTRL_PME_STATUS;
9043 pci_write_config_word(pdev, pdev->pm_cap + PCI_PM_CTRL, pmc);
9045 reset_code = DRV_MSG_CODE_UNLOAD_REQ_WOL_EN;
9048 reset_code = DRV_MSG_CODE_UNLOAD_REQ_WOL_DIS;
9050 /* Send the request to the MCP */
9052 reset_code = bnx2x_fw_command(bp, reset_code, 0);
9054 int path = BP_PATH(bp);
9056 DP(NETIF_MSG_IFDOWN, "NO MCP - load counts[%d] %d, %d, %d\n",
9057 path, bnx2x_load_count[path][0], bnx2x_load_count[path][1],
9058 bnx2x_load_count[path][2]);
9059 bnx2x_load_count[path][0]--;
9060 bnx2x_load_count[path][1 + port]--;
9061 DP(NETIF_MSG_IFDOWN, "NO MCP - new load counts[%d] %d, %d, %d\n",
9062 path, bnx2x_load_count[path][0], bnx2x_load_count[path][1],
9063 bnx2x_load_count[path][2]);
9064 if (bnx2x_load_count[path][0] == 0)
9065 reset_code = FW_MSG_CODE_DRV_UNLOAD_COMMON;
9066 else if (bnx2x_load_count[path][1 + port] == 0)
9067 reset_code = FW_MSG_CODE_DRV_UNLOAD_PORT;
9069 reset_code = FW_MSG_CODE_DRV_UNLOAD_FUNCTION;
9076 * bnx2x_send_unload_done - send UNLOAD_DONE command to the MCP.
9078 * @bp: driver handle
9079 * @keep_link: true iff link should be kept up
9081 void bnx2x_send_unload_done(struct bnx2x *bp, bool keep_link)
9083 u32 reset_param = keep_link ? DRV_MSG_CODE_UNLOAD_SKIP_LINK_RESET : 0;
9085 /* Report UNLOAD_DONE to MCP */
9087 bnx2x_fw_command(bp, DRV_MSG_CODE_UNLOAD_DONE, reset_param);
9090 static int bnx2x_func_wait_started(struct bnx2x *bp)
9093 int msix = (bp->flags & USING_MSIX_FLAG) ? 1 : 0;
9099 * (assumption: No Attention from MCP at this stage)
9100 * PMF probably in the middle of TX disable/enable transaction
9101 * 1. Sync IRS for default SB
9102 * 2. Sync SP queue - this guarantees us that attention handling started
9103 * 3. Wait, that TX disable/enable transaction completes
9105 * 1+2 guarantee that if DCBx attention was scheduled it already changed
9106 * pending bit of transaction from STARTED-->TX_STOPPED, if we already
9107 * received completion for the transaction the state is TX_STOPPED.
9108 * State will return to STARTED after completion of TX_STOPPED-->STARTED
9112 /* make sure default SB ISR is done */
9114 synchronize_irq(bp->msix_table[0].vector);
9116 synchronize_irq(bp->pdev->irq);
9118 flush_workqueue(bnx2x_wq);
9119 flush_workqueue(bnx2x_iov_wq);
9121 while (bnx2x_func_get_state(bp, &bp->func_obj) !=
9122 BNX2X_F_STATE_STARTED && tout--)
9125 if (bnx2x_func_get_state(bp, &bp->func_obj) !=
9126 BNX2X_F_STATE_STARTED) {
9127 #ifdef BNX2X_STOP_ON_ERROR
9128 BNX2X_ERR("Wrong function state\n");
9132 * Failed to complete the transaction in a "good way"
9133 * Force both transactions with CLR bit
9135 struct bnx2x_func_state_params func_params = {NULL};
9137 DP(NETIF_MSG_IFDOWN,
9138 "Hmmm... Unexpected function state! Forcing STARTED-->TX_STOPPED-->STARTED\n");
9140 func_params.f_obj = &bp->func_obj;
9141 __set_bit(RAMROD_DRV_CLR_ONLY,
9142 &func_params.ramrod_flags);
9144 /* STARTED-->TX_ST0PPED */
9145 func_params.cmd = BNX2X_F_CMD_TX_STOP;
9146 bnx2x_func_state_change(bp, &func_params);
9148 /* TX_ST0PPED-->STARTED */
9149 func_params.cmd = BNX2X_F_CMD_TX_START;
9150 return bnx2x_func_state_change(bp, &func_params);
9157 static void bnx2x_disable_ptp(struct bnx2x *bp)
9159 int port = BP_PORT(bp);
9161 /* Disable sending PTP packets to host */
9162 REG_WR(bp, port ? NIG_REG_P1_LLH_PTP_TO_HOST :
9163 NIG_REG_P0_LLH_PTP_TO_HOST, 0x0);
9165 /* Reset PTP event detection rules */
9166 REG_WR(bp, port ? NIG_REG_P1_LLH_PTP_PARAM_MASK :
9167 NIG_REG_P0_LLH_PTP_PARAM_MASK, 0x7FF);
9168 REG_WR(bp, port ? NIG_REG_P1_LLH_PTP_RULE_MASK :
9169 NIG_REG_P0_LLH_PTP_RULE_MASK, 0x3FFF);
9170 REG_WR(bp, port ? NIG_REG_P1_TLLH_PTP_PARAM_MASK :
9171 NIG_REG_P0_TLLH_PTP_PARAM_MASK, 0x7FF);
9172 REG_WR(bp, port ? NIG_REG_P1_TLLH_PTP_RULE_MASK :
9173 NIG_REG_P0_TLLH_PTP_RULE_MASK, 0x3FFF);
9175 /* Disable the PTP feature */
9176 REG_WR(bp, port ? NIG_REG_P1_PTP_EN :
9177 NIG_REG_P0_PTP_EN, 0x0);
9180 /* Called during unload, to stop PTP-related stuff */
9181 static void bnx2x_stop_ptp(struct bnx2x *bp)
9183 /* Cancel PTP work queue. Should be done after the Tx queues are
9184 * drained to prevent additional scheduling.
9186 cancel_work_sync(&bp->ptp_task);
9188 if (bp->ptp_tx_skb) {
9189 dev_kfree_skb_any(bp->ptp_tx_skb);
9190 bp->ptp_tx_skb = NULL;
9193 /* Disable PTP in HW */
9194 bnx2x_disable_ptp(bp);
9196 DP(BNX2X_MSG_PTP, "PTP stop ended successfully\n");
9199 void bnx2x_chip_cleanup(struct bnx2x *bp, int unload_mode, bool keep_link)
9201 int port = BP_PORT(bp);
9204 struct bnx2x_mcast_ramrod_params rparam = {NULL};
9207 /* Wait until tx fastpath tasks complete */
9208 for_each_tx_queue(bp, i) {
9209 struct bnx2x_fastpath *fp = &bp->fp[i];
9211 for_each_cos_in_tx_queue(fp, cos)
9212 rc = bnx2x_clean_tx_queue(bp, fp->txdata_ptr[cos]);
9213 #ifdef BNX2X_STOP_ON_ERROR
9219 /* Give HW time to discard old tx messages */
9220 usleep_range(1000, 2000);
9222 /* Clean all ETH MACs */
9223 rc = bnx2x_del_all_macs(bp, &bp->sp_objs[0].mac_obj, BNX2X_ETH_MAC,
9226 BNX2X_ERR("Failed to delete all ETH macs: %d\n", rc);
9228 /* Clean up UC list */
9229 rc = bnx2x_del_all_macs(bp, &bp->sp_objs[0].mac_obj, BNX2X_UC_LIST_MAC,
9232 BNX2X_ERR("Failed to schedule DEL commands for UC MACs list: %d\n",
9236 if (!CHIP_IS_E1(bp))
9237 REG_WR(bp, NIG_REG_LLH0_FUNC_EN + port*8, 0);
9239 /* Set "drop all" (stop Rx).
9240 * We need to take a netif_addr_lock() here in order to prevent
9241 * a race between the completion code and this code.
9243 netif_addr_lock_bh(bp->dev);
9244 /* Schedule the rx_mode command */
9245 if (test_bit(BNX2X_FILTER_RX_MODE_PENDING, &bp->sp_state))
9246 set_bit(BNX2X_FILTER_RX_MODE_SCHED, &bp->sp_state);
9248 bnx2x_set_storm_rx_mode(bp);
9250 /* Cleanup multicast configuration */
9251 rparam.mcast_obj = &bp->mcast_obj;
9252 rc = bnx2x_config_mcast(bp, &rparam, BNX2X_MCAST_CMD_DEL);
9254 BNX2X_ERR("Failed to send DEL multicast command: %d\n", rc);
9256 netif_addr_unlock_bh(bp->dev);
9258 bnx2x_iov_chip_cleanup(bp);
9261 * Send the UNLOAD_REQUEST to the MCP. This will return if
9262 * this function should perform FUNC, PORT or COMMON HW
9265 reset_code = bnx2x_send_unload_req(bp, unload_mode);
9268 * (assumption: No Attention from MCP at this stage)
9269 * PMF probably in the middle of TX disable/enable transaction
9271 rc = bnx2x_func_wait_started(bp);
9273 BNX2X_ERR("bnx2x_func_wait_started failed\n");
9274 #ifdef BNX2X_STOP_ON_ERROR
9279 /* Close multi and leading connections
9280 * Completions for ramrods are collected in a synchronous way
9282 for_each_eth_queue(bp, i)
9283 if (bnx2x_stop_queue(bp, i))
9284 #ifdef BNX2X_STOP_ON_ERROR
9290 if (CNIC_LOADED(bp)) {
9291 for_each_cnic_queue(bp, i)
9292 if (bnx2x_stop_queue(bp, i))
9293 #ifdef BNX2X_STOP_ON_ERROR
9300 /* If SP settings didn't get completed so far - something
9301 * very wrong has happen.
9303 if (!bnx2x_wait_sp_comp(bp, ~0x0UL))
9304 BNX2X_ERR("Hmmm... Common slow path ramrods got stuck!\n");
9306 #ifndef BNX2X_STOP_ON_ERROR
9309 rc = bnx2x_func_stop(bp);
9311 BNX2X_ERR("Function stop failed!\n");
9312 #ifdef BNX2X_STOP_ON_ERROR
9317 /* stop_ptp should be after the Tx queues are drained to prevent
9318 * scheduling to the cancelled PTP work queue. It should also be after
9319 * function stop ramrod is sent, since as part of this ramrod FW access
9324 /* Disable HW interrupts, NAPI */
9325 bnx2x_netif_stop(bp, 1);
9326 /* Delete all NAPI objects */
9327 bnx2x_del_all_napi(bp);
9328 if (CNIC_LOADED(bp))
9329 bnx2x_del_all_napi_cnic(bp);
9334 /* Reset the chip */
9335 rc = bnx2x_reset_hw(bp, reset_code);
9337 BNX2X_ERR("HW_RESET failed\n");
9339 /* Report UNLOAD_DONE to MCP */
9340 bnx2x_send_unload_done(bp, keep_link);
9343 void bnx2x_disable_close_the_gate(struct bnx2x *bp)
9347 DP(NETIF_MSG_IFDOWN, "Disabling \"close the gates\"\n");
9349 if (CHIP_IS_E1(bp)) {
9350 int port = BP_PORT(bp);
9351 u32 addr = port ? MISC_REG_AEU_MASK_ATTN_FUNC_1 :
9352 MISC_REG_AEU_MASK_ATTN_FUNC_0;
9354 val = REG_RD(bp, addr);
9356 REG_WR(bp, addr, val);
9358 val = REG_RD(bp, MISC_REG_AEU_GENERAL_MASK);
9359 val &= ~(MISC_AEU_GENERAL_MASK_REG_AEU_PXP_CLOSE_MASK |
9360 MISC_AEU_GENERAL_MASK_REG_AEU_NIG_CLOSE_MASK);
9361 REG_WR(bp, MISC_REG_AEU_GENERAL_MASK, val);
9365 /* Close gates #2, #3 and #4: */
9366 static void bnx2x_set_234_gates(struct bnx2x *bp, bool close)
9370 /* Gates #2 and #4a are closed/opened for "not E1" only */
9371 if (!CHIP_IS_E1(bp)) {
9373 REG_WR(bp, PXP_REG_HST_DISCARD_DOORBELLS, !!close);
9375 REG_WR(bp, PXP_REG_HST_DISCARD_INTERNAL_WRITES, !!close);
9379 if (CHIP_IS_E1x(bp)) {
9380 /* Prevent interrupts from HC on both ports */
9381 val = REG_RD(bp, HC_REG_CONFIG_1);
9382 REG_WR(bp, HC_REG_CONFIG_1,
9383 (!close) ? (val | HC_CONFIG_1_REG_BLOCK_DISABLE_1) :
9384 (val & ~(u32)HC_CONFIG_1_REG_BLOCK_DISABLE_1));
9386 val = REG_RD(bp, HC_REG_CONFIG_0);
9387 REG_WR(bp, HC_REG_CONFIG_0,
9388 (!close) ? (val | HC_CONFIG_0_REG_BLOCK_DISABLE_0) :
9389 (val & ~(u32)HC_CONFIG_0_REG_BLOCK_DISABLE_0));
9391 /* Prevent incoming interrupts in IGU */
9392 val = REG_RD(bp, IGU_REG_BLOCK_CONFIGURATION);
9394 REG_WR(bp, IGU_REG_BLOCK_CONFIGURATION,
9396 (val | IGU_BLOCK_CONFIGURATION_REG_BLOCK_ENABLE) :
9397 (val & ~(u32)IGU_BLOCK_CONFIGURATION_REG_BLOCK_ENABLE));
9400 DP(NETIF_MSG_HW | NETIF_MSG_IFUP, "%s gates #2, #3 and #4\n",
9401 close ? "closing" : "opening");
9405 #define SHARED_MF_CLP_MAGIC 0x80000000 /* `magic' bit */
9407 static void bnx2x_clp_reset_prep(struct bnx2x *bp, u32 *magic_val)
9409 /* Do some magic... */
9410 u32 val = MF_CFG_RD(bp, shared_mf_config.clp_mb);
9411 *magic_val = val & SHARED_MF_CLP_MAGIC;
9412 MF_CFG_WR(bp, shared_mf_config.clp_mb, val | SHARED_MF_CLP_MAGIC);
9416 * bnx2x_clp_reset_done - restore the value of the `magic' bit.
9418 * @bp: driver handle
9419 * @magic_val: old value of the `magic' bit.
9421 static void bnx2x_clp_reset_done(struct bnx2x *bp, u32 magic_val)
9423 /* Restore the `magic' bit value... */
9424 u32 val = MF_CFG_RD(bp, shared_mf_config.clp_mb);
9425 MF_CFG_WR(bp, shared_mf_config.clp_mb,
9426 (val & (~SHARED_MF_CLP_MAGIC)) | magic_val);
9430 * bnx2x_reset_mcp_prep - prepare for MCP reset.
9432 * @bp: driver handle
9433 * @magic_val: old value of 'magic' bit.
9435 * Takes care of CLP configurations.
9437 static void bnx2x_reset_mcp_prep(struct bnx2x *bp, u32 *magic_val)
9440 u32 validity_offset;
9442 DP(NETIF_MSG_HW | NETIF_MSG_IFUP, "Starting\n");
9444 /* Set `magic' bit in order to save MF config */
9445 if (!CHIP_IS_E1(bp))
9446 bnx2x_clp_reset_prep(bp, magic_val);
9448 /* Get shmem offset */
9449 shmem = REG_RD(bp, MISC_REG_SHARED_MEM_ADDR);
9451 offsetof(struct shmem_region, validity_map[BP_PORT(bp)]);
9453 /* Clear validity map flags */
9455 REG_WR(bp, shmem + validity_offset, 0);
9458 #define MCP_TIMEOUT 5000 /* 5 seconds (in ms) */
9459 #define MCP_ONE_TIMEOUT 100 /* 100 ms */
9462 * bnx2x_mcp_wait_one - wait for MCP_ONE_TIMEOUT
9464 * @bp: driver handle
9466 static void bnx2x_mcp_wait_one(struct bnx2x *bp)
9468 /* special handling for emulation and FPGA,
9469 wait 10 times longer */
9470 if (CHIP_REV_IS_SLOW(bp))
9471 msleep(MCP_ONE_TIMEOUT*10);
9473 msleep(MCP_ONE_TIMEOUT);
9477 * initializes bp->common.shmem_base and waits for validity signature to appear
9479 static int bnx2x_init_shmem(struct bnx2x *bp)
9485 bp->common.shmem_base = REG_RD(bp, MISC_REG_SHARED_MEM_ADDR);
9486 if (bp->common.shmem_base) {
9487 val = SHMEM_RD(bp, validity_map[BP_PORT(bp)]);
9488 if (val & SHR_MEM_VALIDITY_MB)
9492 bnx2x_mcp_wait_one(bp);
9494 } while (cnt++ < (MCP_TIMEOUT / MCP_ONE_TIMEOUT));
9496 BNX2X_ERR("BAD MCP validity signature\n");
9501 static int bnx2x_reset_mcp_comp(struct bnx2x *bp, u32 magic_val)
9503 int rc = bnx2x_init_shmem(bp);
9505 /* Restore the `magic' bit value */
9506 if (!CHIP_IS_E1(bp))
9507 bnx2x_clp_reset_done(bp, magic_val);
9512 static void bnx2x_pxp_prep(struct bnx2x *bp)
9514 if (!CHIP_IS_E1(bp)) {
9515 REG_WR(bp, PXP2_REG_RD_START_INIT, 0);
9516 REG_WR(bp, PXP2_REG_RQ_RBC_DONE, 0);
9522 * Reset the whole chip except for:
9524 * - PCI Glue, PSWHST, PXP/PXP2 RF (all controlled by
9527 * - MISC (including AEU)
9531 static void bnx2x_process_kill_chip_reset(struct bnx2x *bp, bool global)
9533 u32 not_reset_mask1, reset_mask1, not_reset_mask2, reset_mask2;
9534 u32 global_bits2, stay_reset2;
9537 * Bits that have to be set in reset_mask2 if we want to reset 'global'
9538 * (per chip) blocks.
9541 MISC_REGISTERS_RESET_REG_2_RST_MCP_N_RESET_CMN_CPU |
9542 MISC_REGISTERS_RESET_REG_2_RST_MCP_N_RESET_CMN_CORE;
9544 /* Don't reset the following blocks.
9545 * Important: per port blocks (such as EMAC, BMAC, UMAC) can't be
9546 * reset, as in 4 port device they might still be owned
9547 * by the MCP (there is only one leader per path).
9550 MISC_REGISTERS_RESET_REG_1_RST_HC |
9551 MISC_REGISTERS_RESET_REG_1_RST_PXPV |
9552 MISC_REGISTERS_RESET_REG_1_RST_PXP;
9555 MISC_REGISTERS_RESET_REG_2_RST_PCI_MDIO |
9556 MISC_REGISTERS_RESET_REG_2_RST_EMAC0_HARD_CORE |
9557 MISC_REGISTERS_RESET_REG_2_RST_EMAC1_HARD_CORE |
9558 MISC_REGISTERS_RESET_REG_2_RST_MISC_CORE |
9559 MISC_REGISTERS_RESET_REG_2_RST_RBCN |
9560 MISC_REGISTERS_RESET_REG_2_RST_GRC |
9561 MISC_REGISTERS_RESET_REG_2_RST_MCP_N_RESET_REG_HARD_CORE |
9562 MISC_REGISTERS_RESET_REG_2_RST_MCP_N_HARD_CORE_RST_B |
9563 MISC_REGISTERS_RESET_REG_2_RST_ATC |
9564 MISC_REGISTERS_RESET_REG_2_PGLC |
9565 MISC_REGISTERS_RESET_REG_2_RST_BMAC0 |
9566 MISC_REGISTERS_RESET_REG_2_RST_BMAC1 |
9567 MISC_REGISTERS_RESET_REG_2_RST_EMAC0 |
9568 MISC_REGISTERS_RESET_REG_2_RST_EMAC1 |
9569 MISC_REGISTERS_RESET_REG_2_UMAC0 |
9570 MISC_REGISTERS_RESET_REG_2_UMAC1;
9573 * Keep the following blocks in reset:
9574 * - all xxMACs are handled by the bnx2x_link code.
9577 MISC_REGISTERS_RESET_REG_2_XMAC |
9578 MISC_REGISTERS_RESET_REG_2_XMAC_SOFT;
9580 /* Full reset masks according to the chip */
9581 reset_mask1 = 0xffffffff;
9584 reset_mask2 = 0xffff;
9585 else if (CHIP_IS_E1H(bp))
9586 reset_mask2 = 0x1ffff;
9587 else if (CHIP_IS_E2(bp))
9588 reset_mask2 = 0xfffff;
9589 else /* CHIP_IS_E3 */
9590 reset_mask2 = 0x3ffffff;
9592 /* Don't reset global blocks unless we need to */
9594 reset_mask2 &= ~global_bits2;
9597 * In case of attention in the QM, we need to reset PXP
9598 * (MISC_REGISTERS_RESET_REG_2_RST_PXP_RQ_RD_WR) before QM
9599 * because otherwise QM reset would release 'close the gates' shortly
9600 * before resetting the PXP, then the PSWRQ would send a write
9601 * request to PGLUE. Then when PXP is reset, PGLUE would try to
9602 * read the payload data from PSWWR, but PSWWR would not
9603 * respond. The write queue in PGLUE would stuck, dmae commands
9604 * would not return. Therefore it's important to reset the second
9605 * reset register (containing the
9606 * MISC_REGISTERS_RESET_REG_2_RST_PXP_RQ_RD_WR bit) before the
9607 * first one (containing the MISC_REGISTERS_RESET_REG_1_RST_QM
9610 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR,
9611 reset_mask2 & (~not_reset_mask2));
9613 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_CLEAR,
9614 reset_mask1 & (~not_reset_mask1));
9619 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_SET,
9620 reset_mask2 & (~stay_reset2));
9625 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_SET, reset_mask1);
9630 * bnx2x_er_poll_igu_vq - poll for pending writes bit.
9631 * It should get cleared in no more than 1s.
9633 * @bp: driver handle
9635 * It should get cleared in no more than 1s. Returns 0 if
9636 * pending writes bit gets cleared.
9638 static int bnx2x_er_poll_igu_vq(struct bnx2x *bp)
9644 pend_bits = REG_RD(bp, IGU_REG_PENDING_BITS_STATUS);
9649 usleep_range(1000, 2000);
9650 } while (cnt-- > 0);
9653 BNX2X_ERR("Still pending IGU requests pend_bits=%x!\n",
9661 static int bnx2x_process_kill(struct bnx2x *bp, bool global)
9665 u32 sr_cnt, blk_cnt, port_is_idle_0, port_is_idle_1, pgl_exp_rom2;
9668 /* Empty the Tetris buffer, wait for 1s */
9670 sr_cnt = REG_RD(bp, PXP2_REG_RD_SR_CNT);
9671 blk_cnt = REG_RD(bp, PXP2_REG_RD_BLK_CNT);
9672 port_is_idle_0 = REG_RD(bp, PXP2_REG_RD_PORT_IS_IDLE_0);
9673 port_is_idle_1 = REG_RD(bp, PXP2_REG_RD_PORT_IS_IDLE_1);
9674 pgl_exp_rom2 = REG_RD(bp, PXP2_REG_PGL_EXP_ROM2);
9676 tags_63_32 = REG_RD(bp, PGLUE_B_REG_TAGS_63_32);
9678 if ((sr_cnt == 0x7e) && (blk_cnt == 0xa0) &&
9679 ((port_is_idle_0 & 0x1) == 0x1) &&
9680 ((port_is_idle_1 & 0x1) == 0x1) &&
9681 (pgl_exp_rom2 == 0xffffffff) &&
9682 (!CHIP_IS_E3(bp) || (tags_63_32 == 0xffffffff)))
9684 usleep_range(1000, 2000);
9685 } while (cnt-- > 0);
9688 BNX2X_ERR("Tetris buffer didn't get empty or there are still outstanding read requests after 1s!\n");
9689 BNX2X_ERR("sr_cnt=0x%08x, blk_cnt=0x%08x, port_is_idle_0=0x%08x, port_is_idle_1=0x%08x, pgl_exp_rom2=0x%08x\n",
9690 sr_cnt, blk_cnt, port_is_idle_0, port_is_idle_1,
9697 /* Close gates #2, #3 and #4 */
9698 bnx2x_set_234_gates(bp, true);
9700 /* Poll for IGU VQs for 57712 and newer chips */
9701 if (!CHIP_IS_E1x(bp) && bnx2x_er_poll_igu_vq(bp))
9704 /* TBD: Indicate that "process kill" is in progress to MCP */
9706 /* Clear "unprepared" bit */
9707 REG_WR(bp, MISC_REG_UNPREPARED, 0);
9710 /* Make sure all is written to the chip before the reset */
9713 /* Wait for 1ms to empty GLUE and PCI-E core queues,
9714 * PSWHST, GRC and PSWRD Tetris buffer.
9716 usleep_range(1000, 2000);
9718 /* Prepare to chip reset: */
9721 bnx2x_reset_mcp_prep(bp, &val);
9727 /* reset the chip */
9728 bnx2x_process_kill_chip_reset(bp, global);
9731 /* clear errors in PGB */
9732 if (!CHIP_IS_E1x(bp))
9733 REG_WR(bp, PGLUE_B_REG_LATCHED_ERRORS_CLR, 0x7f);
9735 /* Recover after reset: */
9737 if (global && bnx2x_reset_mcp_comp(bp, val))
9740 /* TBD: Add resetting the NO_MCP mode DB here */
9742 /* Open the gates #2, #3 and #4 */
9743 bnx2x_set_234_gates(bp, false);
9745 /* TBD: IGU/AEU preparation bring back the AEU/IGU to a
9746 * reset state, re-enable attentions. */
9751 static int bnx2x_leader_reset(struct bnx2x *bp)
9754 bool global = bnx2x_reset_is_global(bp);
9757 /* if not going to reset MCP - load "fake" driver to reset HW while
9758 * driver is owner of the HW
9760 if (!global && !BP_NOMCP(bp)) {
9761 load_code = bnx2x_fw_command(bp, DRV_MSG_CODE_LOAD_REQ,
9762 DRV_MSG_CODE_LOAD_REQ_WITH_LFA);
9764 BNX2X_ERR("MCP response failure, aborting\n");
9766 goto exit_leader_reset;
9768 if ((load_code != FW_MSG_CODE_DRV_LOAD_COMMON_CHIP) &&
9769 (load_code != FW_MSG_CODE_DRV_LOAD_COMMON)) {
9770 BNX2X_ERR("MCP unexpected resp, aborting\n");
9772 goto exit_leader_reset2;
9774 load_code = bnx2x_fw_command(bp, DRV_MSG_CODE_LOAD_DONE, 0);
9776 BNX2X_ERR("MCP response failure, aborting\n");
9778 goto exit_leader_reset2;
9782 /* Try to recover after the failure */
9783 if (bnx2x_process_kill(bp, global)) {
9784 BNX2X_ERR("Something bad had happen on engine %d! Aii!\n",
9787 goto exit_leader_reset2;
9791 * Clear RESET_IN_PROGRES and RESET_GLOBAL bits and update the driver
9794 bnx2x_set_reset_done(bp);
9796 bnx2x_clear_reset_global(bp);
9799 /* unload "fake driver" if it was loaded */
9800 if (!global && !BP_NOMCP(bp)) {
9801 bnx2x_fw_command(bp, DRV_MSG_CODE_UNLOAD_REQ_WOL_MCP, 0);
9802 bnx2x_fw_command(bp, DRV_MSG_CODE_UNLOAD_DONE, 0);
9806 bnx2x_release_leader_lock(bp);
9811 static void bnx2x_recovery_failed(struct bnx2x *bp)
9813 netdev_err(bp->dev, "Recovery has failed. Power cycle is needed.\n");
9815 /* Disconnect this device */
9816 netif_device_detach(bp->dev);
9819 * Block ifup for all function on this engine until "process kill"
9822 bnx2x_set_reset_in_progress(bp);
9824 /* Shut down the power */
9825 bnx2x_set_power_state(bp, PCI_D3hot);
9827 bp->recovery_state = BNX2X_RECOVERY_FAILED;
9833 * Assumption: runs under rtnl lock. This together with the fact
9834 * that it's called only from bnx2x_sp_rtnl() ensure that it
9835 * will never be called when netif_running(bp->dev) is false.
9837 static void bnx2x_parity_recover(struct bnx2x *bp)
9839 bool global = false;
9840 u32 error_recovered, error_unrecovered;
9843 DP(NETIF_MSG_HW, "Handling parity\n");
9845 switch (bp->recovery_state) {
9846 case BNX2X_RECOVERY_INIT:
9847 DP(NETIF_MSG_HW, "State is BNX2X_RECOVERY_INIT\n");
9848 is_parity = bnx2x_chk_parity_attn(bp, &global, false);
9849 WARN_ON(!is_parity);
9851 /* Try to get a LEADER_LOCK HW lock */
9852 if (bnx2x_trylock_leader_lock(bp)) {
9853 bnx2x_set_reset_in_progress(bp);
9855 * Check if there is a global attention and if
9856 * there was a global attention, set the global
9861 bnx2x_set_reset_global(bp);
9866 /* Stop the driver */
9867 /* If interface has been removed - break */
9868 if (bnx2x_nic_unload(bp, UNLOAD_RECOVERY, false))
9871 bp->recovery_state = BNX2X_RECOVERY_WAIT;
9873 /* Ensure "is_leader", MCP command sequence and
9874 * "recovery_state" update values are seen on other
9880 case BNX2X_RECOVERY_WAIT:
9881 DP(NETIF_MSG_HW, "State is BNX2X_RECOVERY_WAIT\n");
9882 if (bp->is_leader) {
9883 int other_engine = BP_PATH(bp) ? 0 : 1;
9884 bool other_load_status =
9885 bnx2x_get_load_status(bp, other_engine);
9887 bnx2x_get_load_status(bp, BP_PATH(bp));
9888 global = bnx2x_reset_is_global(bp);
9891 * In case of a parity in a global block, let
9892 * the first leader that performs a
9893 * leader_reset() reset the global blocks in
9894 * order to clear global attentions. Otherwise
9895 * the gates will remain closed for that
9899 (global && other_load_status)) {
9900 /* Wait until all other functions get
9903 schedule_delayed_work(&bp->sp_rtnl_task,
9907 /* If all other functions got down -
9908 * try to bring the chip back to
9909 * normal. In any case it's an exit
9910 * point for a leader.
9912 if (bnx2x_leader_reset(bp)) {
9913 bnx2x_recovery_failed(bp);
9917 /* If we are here, means that the
9918 * leader has succeeded and doesn't
9919 * want to be a leader any more. Try
9920 * to continue as a none-leader.
9924 } else { /* non-leader */
9925 if (!bnx2x_reset_is_done(bp, BP_PATH(bp))) {
9926 /* Try to get a LEADER_LOCK HW lock as
9927 * long as a former leader may have
9928 * been unloaded by the user or
9929 * released a leadership by another
9932 if (bnx2x_trylock_leader_lock(bp)) {
9933 /* I'm a leader now! Restart a
9940 schedule_delayed_work(&bp->sp_rtnl_task,
9946 * If there was a global attention, wait
9947 * for it to be cleared.
9949 if (bnx2x_reset_is_global(bp)) {
9950 schedule_delayed_work(
9957 bp->eth_stats.recoverable_error;
9959 bp->eth_stats.unrecoverable_error;
9960 bp->recovery_state =
9961 BNX2X_RECOVERY_NIC_LOADING;
9962 if (bnx2x_nic_load(bp, LOAD_NORMAL)) {
9963 error_unrecovered++;
9965 "Recovery failed. Power cycle needed\n");
9966 /* Disconnect this device */
9967 netif_device_detach(bp->dev);
9968 /* Shut down the power */
9969 bnx2x_set_power_state(
9973 bp->recovery_state =
9974 BNX2X_RECOVERY_DONE;
9978 bp->eth_stats.recoverable_error =
9980 bp->eth_stats.unrecoverable_error =
9992 static int bnx2x_close(struct net_device *dev);
9994 /* bnx2x_nic_unload() flushes the bnx2x_wq, thus reset task is
9995 * scheduled on a general queue in order to prevent a dead lock.
9997 static void bnx2x_sp_rtnl_task(struct work_struct *work)
9999 struct bnx2x *bp = container_of(work, struct bnx2x, sp_rtnl_task.work);
10003 if (!netif_running(bp->dev)) {
10008 if (unlikely(bp->recovery_state != BNX2X_RECOVERY_DONE)) {
10009 #ifdef BNX2X_STOP_ON_ERROR
10010 BNX2X_ERR("recovery flow called but STOP_ON_ERROR defined so reset not done to allow debug dump,\n"
10011 "you will need to reboot when done\n");
10012 goto sp_rtnl_not_reset;
10015 * Clear all pending SP commands as we are going to reset the
10018 bp->sp_rtnl_state = 0;
10021 bnx2x_parity_recover(bp);
10027 if (test_and_clear_bit(BNX2X_SP_RTNL_TX_TIMEOUT, &bp->sp_rtnl_state)) {
10028 #ifdef BNX2X_STOP_ON_ERROR
10029 BNX2X_ERR("recovery flow called but STOP_ON_ERROR defined so reset not done to allow debug dump,\n"
10030 "you will need to reboot when done\n");
10031 goto sp_rtnl_not_reset;
10035 * Clear all pending SP commands as we are going to reset the
10038 bp->sp_rtnl_state = 0;
10041 bnx2x_nic_unload(bp, UNLOAD_NORMAL, true);
10042 bnx2x_nic_load(bp, LOAD_NORMAL);
10047 #ifdef BNX2X_STOP_ON_ERROR
10050 if (test_and_clear_bit(BNX2X_SP_RTNL_SETUP_TC, &bp->sp_rtnl_state))
10051 bnx2x_setup_tc(bp->dev, bp->dcbx_port_params.ets.num_of_cos);
10052 if (test_and_clear_bit(BNX2X_SP_RTNL_AFEX_F_UPDATE, &bp->sp_rtnl_state))
10053 bnx2x_after_function_update(bp);
10055 * in case of fan failure we need to reset id if the "stop on error"
10056 * debug flag is set, since we trying to prevent permanent overheating
10059 if (test_and_clear_bit(BNX2X_SP_RTNL_FAN_FAILURE, &bp->sp_rtnl_state)) {
10060 DP(NETIF_MSG_HW, "fan failure detected. Unloading driver\n");
10061 netif_device_detach(bp->dev);
10062 bnx2x_close(bp->dev);
10067 if (test_and_clear_bit(BNX2X_SP_RTNL_VFPF_MCAST, &bp->sp_rtnl_state)) {
10069 "sending set mcast vf pf channel message from rtnl sp-task\n");
10070 bnx2x_vfpf_set_mcast(bp->dev);
10072 if (test_and_clear_bit(BNX2X_SP_RTNL_VFPF_CHANNEL_DOWN,
10073 &bp->sp_rtnl_state)){
10074 if (!test_bit(__LINK_STATE_NOCARRIER, &bp->dev->state)) {
10075 bnx2x_tx_disable(bp);
10076 BNX2X_ERR("PF indicated channel is not servicable anymore. This means this VF device is no longer operational\n");
10080 if (test_and_clear_bit(BNX2X_SP_RTNL_RX_MODE, &bp->sp_rtnl_state)) {
10081 DP(BNX2X_MSG_SP, "Handling Rx Mode setting\n");
10082 bnx2x_set_rx_mode_inner(bp);
10085 if (test_and_clear_bit(BNX2X_SP_RTNL_HYPERVISOR_VLAN,
10086 &bp->sp_rtnl_state))
10087 bnx2x_pf_set_vfs_vlan(bp);
10089 if (test_and_clear_bit(BNX2X_SP_RTNL_TX_STOP, &bp->sp_rtnl_state)) {
10090 bnx2x_dcbx_stop_hw_tx(bp);
10091 bnx2x_dcbx_resume_hw_tx(bp);
10094 if (test_and_clear_bit(BNX2X_SP_RTNL_GET_DRV_VERSION,
10095 &bp->sp_rtnl_state))
10096 bnx2x_update_mng_version(bp);
10098 /* work which needs rtnl lock not-taken (as it takes the lock itself and
10099 * can be called from other contexts as well)
10103 /* enable SR-IOV if applicable */
10104 if (IS_SRIOV(bp) && test_and_clear_bit(BNX2X_SP_RTNL_ENABLE_SRIOV,
10105 &bp->sp_rtnl_state)) {
10106 bnx2x_disable_sriov(bp);
10107 bnx2x_enable_sriov(bp);
10111 static void bnx2x_period_task(struct work_struct *work)
10113 struct bnx2x *bp = container_of(work, struct bnx2x, period_task.work);
10115 if (!netif_running(bp->dev))
10116 goto period_task_exit;
10118 if (CHIP_REV_IS_SLOW(bp)) {
10119 BNX2X_ERR("period task called on emulation, ignoring\n");
10120 goto period_task_exit;
10123 bnx2x_acquire_phy_lock(bp);
10125 * The barrier is needed to ensure the ordering between the writing to
10126 * the bp->port.pmf in the bnx2x_nic_load() or bnx2x_pmf_update() and
10127 * the reading here.
10130 if (bp->port.pmf) {
10131 bnx2x_period_func(&bp->link_params, &bp->link_vars);
10133 /* Re-queue task in 1 sec */
10134 queue_delayed_work(bnx2x_wq, &bp->period_task, 1*HZ);
10137 bnx2x_release_phy_lock(bp);
10143 * Init service functions
10146 static u32 bnx2x_get_pretend_reg(struct bnx2x *bp)
10148 u32 base = PXP2_REG_PGL_PRETEND_FUNC_F0;
10149 u32 stride = PXP2_REG_PGL_PRETEND_FUNC_F1 - base;
10150 return base + (BP_ABS_FUNC(bp)) * stride;
10153 static bool bnx2x_prev_unload_close_umac(struct bnx2x *bp,
10154 u8 port, u32 reset_reg,
10155 struct bnx2x_mac_vals *vals)
10157 u32 mask = MISC_REGISTERS_RESET_REG_2_UMAC0 << port;
10160 if (!(mask & reset_reg))
10163 BNX2X_DEV_INFO("Disable umac Rx %02x\n", port);
10164 base_addr = port ? GRCBASE_UMAC1 : GRCBASE_UMAC0;
10165 vals->umac_addr[port] = base_addr + UMAC_REG_COMMAND_CONFIG;
10166 vals->umac_val[port] = REG_RD(bp, vals->umac_addr[port]);
10167 REG_WR(bp, vals->umac_addr[port], 0);
10172 static void bnx2x_prev_unload_close_mac(struct bnx2x *bp,
10173 struct bnx2x_mac_vals *vals)
10175 u32 val, base_addr, offset, mask, reset_reg;
10176 bool mac_stopped = false;
10177 u8 port = BP_PORT(bp);
10179 /* reset addresses as they also mark which values were changed */
10180 memset(vals, 0, sizeof(*vals));
10182 reset_reg = REG_RD(bp, MISC_REG_RESET_REG_2);
10184 if (!CHIP_IS_E3(bp)) {
10185 val = REG_RD(bp, NIG_REG_BMAC0_REGS_OUT_EN + port * 4);
10186 mask = MISC_REGISTERS_RESET_REG_2_RST_BMAC0 << port;
10187 if ((mask & reset_reg) && val) {
10189 BNX2X_DEV_INFO("Disable bmac Rx\n");
10190 base_addr = BP_PORT(bp) ? NIG_REG_INGRESS_BMAC1_MEM
10191 : NIG_REG_INGRESS_BMAC0_MEM;
10192 offset = CHIP_IS_E2(bp) ? BIGMAC2_REGISTER_BMAC_CONTROL
10193 : BIGMAC_REGISTER_BMAC_CONTROL;
10196 * use rd/wr since we cannot use dmae. This is safe
10197 * since MCP won't access the bus due to the request
10198 * to unload, and no function on the path can be
10199 * loaded at this time.
10201 wb_data[0] = REG_RD(bp, base_addr + offset);
10202 wb_data[1] = REG_RD(bp, base_addr + offset + 0x4);
10203 vals->bmac_addr = base_addr + offset;
10204 vals->bmac_val[0] = wb_data[0];
10205 vals->bmac_val[1] = wb_data[1];
10206 wb_data[0] &= ~BMAC_CONTROL_RX_ENABLE;
10207 REG_WR(bp, vals->bmac_addr, wb_data[0]);
10208 REG_WR(bp, vals->bmac_addr + 0x4, wb_data[1]);
10210 BNX2X_DEV_INFO("Disable emac Rx\n");
10211 vals->emac_addr = NIG_REG_NIG_EMAC0_EN + BP_PORT(bp)*4;
10212 vals->emac_val = REG_RD(bp, vals->emac_addr);
10213 REG_WR(bp, vals->emac_addr, 0);
10214 mac_stopped = true;
10216 if (reset_reg & MISC_REGISTERS_RESET_REG_2_XMAC) {
10217 BNX2X_DEV_INFO("Disable xmac Rx\n");
10218 base_addr = BP_PORT(bp) ? GRCBASE_XMAC1 : GRCBASE_XMAC0;
10219 val = REG_RD(bp, base_addr + XMAC_REG_PFC_CTRL_HI);
10220 REG_WR(bp, base_addr + XMAC_REG_PFC_CTRL_HI,
10222 REG_WR(bp, base_addr + XMAC_REG_PFC_CTRL_HI,
10224 vals->xmac_addr = base_addr + XMAC_REG_CTRL;
10225 vals->xmac_val = REG_RD(bp, vals->xmac_addr);
10226 REG_WR(bp, vals->xmac_addr, 0);
10227 mac_stopped = true;
10230 mac_stopped |= bnx2x_prev_unload_close_umac(bp, 0,
10232 mac_stopped |= bnx2x_prev_unload_close_umac(bp, 1,
10240 #define BNX2X_PREV_UNDI_PROD_ADDR(p) (BAR_TSTRORM_INTMEM + 0x1508 + ((p) << 4))
10241 #define BNX2X_PREV_UNDI_PROD_ADDR_H(f) (BAR_TSTRORM_INTMEM + \
10242 0x1848 + ((f) << 4))
10243 #define BNX2X_PREV_UNDI_RCQ(val) ((val) & 0xffff)
10244 #define BNX2X_PREV_UNDI_BD(val) ((val) >> 16 & 0xffff)
10245 #define BNX2X_PREV_UNDI_PROD(rcq, bd) ((bd) << 16 | (rcq))
10247 #define BCM_5710_UNDI_FW_MF_MAJOR (0x07)
10248 #define BCM_5710_UNDI_FW_MF_MINOR (0x08)
10249 #define BCM_5710_UNDI_FW_MF_VERS (0x05)
10251 static bool bnx2x_prev_is_after_undi(struct bnx2x *bp)
10253 /* UNDI marks its presence in DORQ -
10254 * it initializes CID offset for normal bell to 0x7
10256 if (!(REG_RD(bp, MISC_REG_RESET_REG_1) &
10257 MISC_REGISTERS_RESET_REG_1_RST_DORQ))
10260 if (REG_RD(bp, DORQ_REG_NORM_CID_OFST) == 0x7) {
10261 BNX2X_DEV_INFO("UNDI previously loaded\n");
10268 static void bnx2x_prev_unload_undi_inc(struct bnx2x *bp, u8 inc)
10273 if (BP_FUNC(bp) < 2)
10274 addr = BNX2X_PREV_UNDI_PROD_ADDR(BP_PORT(bp));
10276 addr = BNX2X_PREV_UNDI_PROD_ADDR_H(BP_FUNC(bp) - 2);
10278 tmp_reg = REG_RD(bp, addr);
10279 rcq = BNX2X_PREV_UNDI_RCQ(tmp_reg) + inc;
10280 bd = BNX2X_PREV_UNDI_BD(tmp_reg) + inc;
10282 tmp_reg = BNX2X_PREV_UNDI_PROD(rcq, bd);
10283 REG_WR(bp, addr, tmp_reg);
10285 BNX2X_DEV_INFO("UNDI producer [%d/%d][%08x] rings bd -> 0x%04x, rcq -> 0x%04x\n",
10286 BP_PORT(bp), BP_FUNC(bp), addr, bd, rcq);
10289 static int bnx2x_prev_mcp_done(struct bnx2x *bp)
10291 u32 rc = bnx2x_fw_command(bp, DRV_MSG_CODE_UNLOAD_DONE,
10292 DRV_MSG_CODE_UNLOAD_SKIP_LINK_RESET);
10294 BNX2X_ERR("MCP response failure, aborting\n");
10301 static struct bnx2x_prev_path_list *
10302 bnx2x_prev_path_get_entry(struct bnx2x *bp)
10304 struct bnx2x_prev_path_list *tmp_list;
10306 list_for_each_entry(tmp_list, &bnx2x_prev_list, list)
10307 if (PCI_SLOT(bp->pdev->devfn) == tmp_list->slot &&
10308 bp->pdev->bus->number == tmp_list->bus &&
10309 BP_PATH(bp) == tmp_list->path)
10315 static int bnx2x_prev_path_mark_eeh(struct bnx2x *bp)
10317 struct bnx2x_prev_path_list *tmp_list;
10320 rc = down_interruptible(&bnx2x_prev_sem);
10322 BNX2X_ERR("Received %d when tried to take lock\n", rc);
10326 tmp_list = bnx2x_prev_path_get_entry(bp);
10331 BNX2X_ERR("path %d: Entry does not exist for eeh; Flow occurs before initial insmod is over ?\n",
10335 up(&bnx2x_prev_sem);
10340 static bool bnx2x_prev_is_path_marked(struct bnx2x *bp)
10342 struct bnx2x_prev_path_list *tmp_list;
10345 if (down_trylock(&bnx2x_prev_sem))
10348 tmp_list = bnx2x_prev_path_get_entry(bp);
10350 if (tmp_list->aer) {
10351 DP(NETIF_MSG_HW, "Path %d was marked by AER\n",
10355 BNX2X_DEV_INFO("Path %d was already cleaned from previous drivers\n",
10360 up(&bnx2x_prev_sem);
10365 bool bnx2x_port_after_undi(struct bnx2x *bp)
10367 struct bnx2x_prev_path_list *entry;
10370 down(&bnx2x_prev_sem);
10372 entry = bnx2x_prev_path_get_entry(bp);
10373 val = !!(entry && (entry->undi & (1 << BP_PORT(bp))));
10375 up(&bnx2x_prev_sem);
10380 static int bnx2x_prev_mark_path(struct bnx2x *bp, bool after_undi)
10382 struct bnx2x_prev_path_list *tmp_list;
10385 rc = down_interruptible(&bnx2x_prev_sem);
10387 BNX2X_ERR("Received %d when tried to take lock\n", rc);
10391 /* Check whether the entry for this path already exists */
10392 tmp_list = bnx2x_prev_path_get_entry(bp);
10394 if (!tmp_list->aer) {
10395 BNX2X_ERR("Re-Marking the path.\n");
10397 DP(NETIF_MSG_HW, "Removing AER indication from path %d\n",
10401 up(&bnx2x_prev_sem);
10404 up(&bnx2x_prev_sem);
10406 /* Create an entry for this path and add it */
10407 tmp_list = kmalloc(sizeof(struct bnx2x_prev_path_list), GFP_KERNEL);
10409 BNX2X_ERR("Failed to allocate 'bnx2x_prev_path_list'\n");
10413 tmp_list->bus = bp->pdev->bus->number;
10414 tmp_list->slot = PCI_SLOT(bp->pdev->devfn);
10415 tmp_list->path = BP_PATH(bp);
10417 tmp_list->undi = after_undi ? (1 << BP_PORT(bp)) : 0;
10419 rc = down_interruptible(&bnx2x_prev_sem);
10421 BNX2X_ERR("Received %d when tried to take lock\n", rc);
10424 DP(NETIF_MSG_HW, "Marked path [%d] - finished previous unload\n",
10426 list_add(&tmp_list->list, &bnx2x_prev_list);
10427 up(&bnx2x_prev_sem);
10433 static int bnx2x_do_flr(struct bnx2x *bp)
10435 struct pci_dev *dev = bp->pdev;
10437 if (CHIP_IS_E1x(bp)) {
10438 BNX2X_DEV_INFO("FLR not supported in E1/E1H\n");
10442 /* only bootcode REQ_BC_VER_4_INITIATE_FLR and onwards support flr */
10443 if (bp->common.bc_ver < REQ_BC_VER_4_INITIATE_FLR) {
10444 BNX2X_ERR("FLR not supported by BC_VER: 0x%x\n",
10445 bp->common.bc_ver);
10449 if (!pci_wait_for_pending_transaction(dev))
10450 dev_err(&dev->dev, "transaction is not cleared; proceeding with reset anyway\n");
10452 BNX2X_DEV_INFO("Initiating FLR\n");
10453 bnx2x_fw_command(bp, DRV_MSG_CODE_INITIATE_FLR, 0);
10458 static int bnx2x_prev_unload_uncommon(struct bnx2x *bp)
10462 BNX2X_DEV_INFO("Uncommon unload Flow\n");
10464 /* Test if previous unload process was already finished for this path */
10465 if (bnx2x_prev_is_path_marked(bp))
10466 return bnx2x_prev_mcp_done(bp);
10468 BNX2X_DEV_INFO("Path is unmarked\n");
10470 /* Cannot proceed with FLR if UNDI is loaded, since FW does not match */
10471 if (bnx2x_prev_is_after_undi(bp))
10474 /* If function has FLR capabilities, and existing FW version matches
10475 * the one required, then FLR will be sufficient to clean any residue
10476 * left by previous driver
10478 rc = bnx2x_compare_fw_ver(bp, FW_MSG_CODE_DRV_LOAD_FUNCTION, false);
10481 /* fw version is good */
10482 BNX2X_DEV_INFO("FW version matches our own. Attempting FLR\n");
10483 rc = bnx2x_do_flr(bp);
10487 /* FLR was performed */
10488 BNX2X_DEV_INFO("FLR successful\n");
10492 BNX2X_DEV_INFO("Could not FLR\n");
10495 /* Close the MCP request, return failure*/
10496 rc = bnx2x_prev_mcp_done(bp);
10498 rc = BNX2X_PREV_WAIT_NEEDED;
10503 static int bnx2x_prev_unload_common(struct bnx2x *bp)
10505 u32 reset_reg, tmp_reg = 0, rc;
10506 bool prev_undi = false;
10507 struct bnx2x_mac_vals mac_vals;
10509 /* It is possible a previous function received 'common' answer,
10510 * but hasn't loaded yet, therefore creating a scenario of
10511 * multiple functions receiving 'common' on the same path.
10513 BNX2X_DEV_INFO("Common unload Flow\n");
10515 memset(&mac_vals, 0, sizeof(mac_vals));
10517 if (bnx2x_prev_is_path_marked(bp))
10518 return bnx2x_prev_mcp_done(bp);
10520 reset_reg = REG_RD(bp, MISC_REG_RESET_REG_1);
10522 /* Reset should be performed after BRB is emptied */
10523 if (reset_reg & MISC_REGISTERS_RESET_REG_1_RST_BRB1) {
10524 u32 timer_count = 1000;
10526 /* Close the MAC Rx to prevent BRB from filling up */
10527 bnx2x_prev_unload_close_mac(bp, &mac_vals);
10529 /* close LLH filters for both ports towards the BRB */
10530 bnx2x_set_rx_filter(&bp->link_params, 0);
10531 bp->link_params.port ^= 1;
10532 bnx2x_set_rx_filter(&bp->link_params, 0);
10533 bp->link_params.port ^= 1;
10535 /* Check if the UNDI driver was previously loaded */
10536 if (bnx2x_prev_is_after_undi(bp)) {
10538 /* clear the UNDI indication */
10539 REG_WR(bp, DORQ_REG_NORM_CID_OFST, 0);
10540 /* clear possible idle check errors */
10541 REG_RD(bp, NIG_REG_NIG_INT_STS_CLR_0);
10543 if (!CHIP_IS_E1x(bp))
10544 /* block FW from writing to host */
10545 REG_WR(bp, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, 0);
10547 /* wait until BRB is empty */
10548 tmp_reg = REG_RD(bp, BRB1_REG_NUM_OF_FULL_BLOCKS);
10549 while (timer_count) {
10550 u32 prev_brb = tmp_reg;
10552 tmp_reg = REG_RD(bp, BRB1_REG_NUM_OF_FULL_BLOCKS);
10556 BNX2X_DEV_INFO("BRB still has 0x%08x\n", tmp_reg);
10558 /* reset timer as long as BRB actually gets emptied */
10559 if (prev_brb > tmp_reg)
10560 timer_count = 1000;
10564 /* If UNDI resides in memory, manually increment it */
10566 bnx2x_prev_unload_undi_inc(bp, 1);
10572 BNX2X_ERR("Failed to empty BRB, hope for the best\n");
10575 /* No packets are in the pipeline, path is ready for reset */
10576 bnx2x_reset_common(bp);
10578 if (mac_vals.xmac_addr)
10579 REG_WR(bp, mac_vals.xmac_addr, mac_vals.xmac_val);
10580 if (mac_vals.umac_addr[0])
10581 REG_WR(bp, mac_vals.umac_addr[0], mac_vals.umac_val[0]);
10582 if (mac_vals.umac_addr[1])
10583 REG_WR(bp, mac_vals.umac_addr[1], mac_vals.umac_val[1]);
10584 if (mac_vals.emac_addr)
10585 REG_WR(bp, mac_vals.emac_addr, mac_vals.emac_val);
10586 if (mac_vals.bmac_addr) {
10587 REG_WR(bp, mac_vals.bmac_addr, mac_vals.bmac_val[0]);
10588 REG_WR(bp, mac_vals.bmac_addr + 4, mac_vals.bmac_val[1]);
10591 rc = bnx2x_prev_mark_path(bp, prev_undi);
10593 bnx2x_prev_mcp_done(bp);
10597 return bnx2x_prev_mcp_done(bp);
10600 static int bnx2x_prev_unload(struct bnx2x *bp)
10602 int time_counter = 10;
10603 u32 rc, fw, hw_lock_reg, hw_lock_val;
10604 BNX2X_DEV_INFO("Entering Previous Unload Flow\n");
10606 /* clear hw from errors which may have resulted from an interrupted
10607 * dmae transaction.
10609 bnx2x_clean_pglue_errors(bp);
10611 /* Release previously held locks */
10612 hw_lock_reg = (BP_FUNC(bp) <= 5) ?
10613 (MISC_REG_DRIVER_CONTROL_1 + BP_FUNC(bp) * 8) :
10614 (MISC_REG_DRIVER_CONTROL_7 + (BP_FUNC(bp) - 6) * 8);
10616 hw_lock_val = REG_RD(bp, hw_lock_reg);
10618 if (hw_lock_val & HW_LOCK_RESOURCE_NVRAM) {
10619 BNX2X_DEV_INFO("Release Previously held NVRAM lock\n");
10620 REG_WR(bp, MCP_REG_MCPR_NVM_SW_ARB,
10621 (MCPR_NVM_SW_ARB_ARB_REQ_CLR1 << BP_PORT(bp)));
10624 BNX2X_DEV_INFO("Release Previously held hw lock\n");
10625 REG_WR(bp, hw_lock_reg, 0xffffffff);
10627 BNX2X_DEV_INFO("No need to release hw/nvram locks\n");
10629 if (MCPR_ACCESS_LOCK_LOCK & REG_RD(bp, MCP_REG_MCPR_ACCESS_LOCK)) {
10630 BNX2X_DEV_INFO("Release previously held alr\n");
10631 bnx2x_release_alr(bp);
10636 /* Lock MCP using an unload request */
10637 fw = bnx2x_fw_command(bp, DRV_MSG_CODE_UNLOAD_REQ_WOL_DIS, 0);
10639 BNX2X_ERR("MCP response failure, aborting\n");
10644 rc = down_interruptible(&bnx2x_prev_sem);
10646 BNX2X_ERR("Cannot check for AER; Received %d when tried to take lock\n",
10649 /* If Path is marked by EEH, ignore unload status */
10650 aer = !!(bnx2x_prev_path_get_entry(bp) &&
10651 bnx2x_prev_path_get_entry(bp)->aer);
10652 up(&bnx2x_prev_sem);
10655 if (fw == FW_MSG_CODE_DRV_UNLOAD_COMMON || aer) {
10656 rc = bnx2x_prev_unload_common(bp);
10660 /* non-common reply from MCP might require looping */
10661 rc = bnx2x_prev_unload_uncommon(bp);
10662 if (rc != BNX2X_PREV_WAIT_NEEDED)
10666 } while (--time_counter);
10668 if (!time_counter || rc) {
10669 BNX2X_DEV_INFO("Unloading previous driver did not occur, Possibly due to MF UNDI\n");
10670 rc = -EPROBE_DEFER;
10673 /* Mark function if its port was used to boot from SAN */
10674 if (bnx2x_port_after_undi(bp))
10675 bp->link_params.feature_config_flags |=
10676 FEATURE_CONFIG_BOOT_FROM_SAN;
10678 BNX2X_DEV_INFO("Finished Previous Unload Flow [%d]\n", rc);
10683 static void bnx2x_get_common_hwinfo(struct bnx2x *bp)
10685 u32 val, val2, val3, val4, id, boot_mode;
10688 /* Get the chip revision id and number. */
10689 /* chip num:16-31, rev:12-15, metal:4-11, bond_id:0-3 */
10690 val = REG_RD(bp, MISC_REG_CHIP_NUM);
10691 id = ((val & 0xffff) << 16);
10692 val = REG_RD(bp, MISC_REG_CHIP_REV);
10693 id |= ((val & 0xf) << 12);
10695 /* Metal is read from PCI regs, but we can't access >=0x400 from
10696 * the configuration space (so we need to reg_rd)
10698 val = REG_RD(bp, PCICFG_OFFSET + PCI_ID_VAL3);
10699 id |= (((val >> 24) & 0xf) << 4);
10700 val = REG_RD(bp, MISC_REG_BOND_ID);
10702 bp->common.chip_id = id;
10704 /* force 57811 according to MISC register */
10705 if (REG_RD(bp, MISC_REG_CHIP_TYPE) & MISC_REG_CHIP_TYPE_57811_MASK) {
10706 if (CHIP_IS_57810(bp))
10707 bp->common.chip_id = (CHIP_NUM_57811 << 16) |
10708 (bp->common.chip_id & 0x0000FFFF);
10709 else if (CHIP_IS_57810_MF(bp))
10710 bp->common.chip_id = (CHIP_NUM_57811_MF << 16) |
10711 (bp->common.chip_id & 0x0000FFFF);
10712 bp->common.chip_id |= 0x1;
10715 /* Set doorbell size */
10716 bp->db_size = (1 << BNX2X_DB_SHIFT);
10718 if (!CHIP_IS_E1x(bp)) {
10719 val = REG_RD(bp, MISC_REG_PORT4MODE_EN_OVWR);
10720 if ((val & 1) == 0)
10721 val = REG_RD(bp, MISC_REG_PORT4MODE_EN);
10723 val = (val >> 1) & 1;
10724 BNX2X_DEV_INFO("chip is in %s\n", val ? "4_PORT_MODE" :
10726 bp->common.chip_port_mode = val ? CHIP_4_PORT_MODE :
10729 if (CHIP_MODE_IS_4_PORT(bp))
10730 bp->pfid = (bp->pf_num >> 1); /* 0..3 */
10732 bp->pfid = (bp->pf_num & 0x6); /* 0, 2, 4, 6 */
10734 bp->common.chip_port_mode = CHIP_PORT_MODE_NONE; /* N/A */
10735 bp->pfid = bp->pf_num; /* 0..7 */
10738 BNX2X_DEV_INFO("pf_id: %x", bp->pfid);
10740 bp->link_params.chip_id = bp->common.chip_id;
10741 BNX2X_DEV_INFO("chip ID is 0x%x\n", id);
10743 val = (REG_RD(bp, 0x2874) & 0x55);
10744 if ((bp->common.chip_id & 0x1) ||
10745 (CHIP_IS_E1(bp) && val) || (CHIP_IS_E1H(bp) && (val == 0x55))) {
10746 bp->flags |= ONE_PORT_FLAG;
10747 BNX2X_DEV_INFO("single port device\n");
10750 val = REG_RD(bp, MCP_REG_MCPR_NVM_CFG4);
10751 bp->common.flash_size = (BNX2X_NVRAM_1MB_SIZE <<
10752 (val & MCPR_NVM_CFG4_FLASH_SIZE));
10753 BNX2X_DEV_INFO("flash_size 0x%x (%d)\n",
10754 bp->common.flash_size, bp->common.flash_size);
10756 bnx2x_init_shmem(bp);
10758 bp->common.shmem2_base = REG_RD(bp, (BP_PATH(bp) ?
10759 MISC_REG_GENERIC_CR_1 :
10760 MISC_REG_GENERIC_CR_0));
10762 bp->link_params.shmem_base = bp->common.shmem_base;
10763 bp->link_params.shmem2_base = bp->common.shmem2_base;
10764 if (SHMEM2_RD(bp, size) >
10765 (u32)offsetof(struct shmem2_region, lfa_host_addr[BP_PORT(bp)]))
10766 bp->link_params.lfa_base =
10767 REG_RD(bp, bp->common.shmem2_base +
10768 (u32)offsetof(struct shmem2_region,
10769 lfa_host_addr[BP_PORT(bp)]));
10771 bp->link_params.lfa_base = 0;
10772 BNX2X_DEV_INFO("shmem offset 0x%x shmem2 offset 0x%x\n",
10773 bp->common.shmem_base, bp->common.shmem2_base);
10775 if (!bp->common.shmem_base) {
10776 BNX2X_DEV_INFO("MCP not active\n");
10777 bp->flags |= NO_MCP_FLAG;
10781 bp->common.hw_config = SHMEM_RD(bp, dev_info.shared_hw_config.config);
10782 BNX2X_DEV_INFO("hw_config 0x%08x\n", bp->common.hw_config);
10784 bp->link_params.hw_led_mode = ((bp->common.hw_config &
10785 SHARED_HW_CFG_LED_MODE_MASK) >>
10786 SHARED_HW_CFG_LED_MODE_SHIFT);
10788 bp->link_params.feature_config_flags = 0;
10789 val = SHMEM_RD(bp, dev_info.shared_feature_config.config);
10790 if (val & SHARED_FEAT_CFG_OVERRIDE_PREEMPHASIS_CFG_ENABLED)
10791 bp->link_params.feature_config_flags |=
10792 FEATURE_CONFIG_OVERRIDE_PREEMPHASIS_ENABLED;
10794 bp->link_params.feature_config_flags &=
10795 ~FEATURE_CONFIG_OVERRIDE_PREEMPHASIS_ENABLED;
10797 val = SHMEM_RD(bp, dev_info.bc_rev) >> 8;
10798 bp->common.bc_ver = val;
10799 BNX2X_DEV_INFO("bc_ver %X\n", val);
10800 if (val < BNX2X_BC_VER) {
10801 /* for now only warn
10802 * later we might need to enforce this */
10803 BNX2X_ERR("This driver needs bc_ver %X but found %X, please upgrade BC\n",
10804 BNX2X_BC_VER, val);
10806 bp->link_params.feature_config_flags |=
10807 (val >= REQ_BC_VER_4_VRFY_FIRST_PHY_OPT_MDL) ?
10808 FEATURE_CONFIG_BC_SUPPORTS_OPT_MDL_VRFY : 0;
10810 bp->link_params.feature_config_flags |=
10811 (val >= REQ_BC_VER_4_VRFY_SPECIFIC_PHY_OPT_MDL) ?
10812 FEATURE_CONFIG_BC_SUPPORTS_DUAL_PHY_OPT_MDL_VRFY : 0;
10813 bp->link_params.feature_config_flags |=
10814 (val >= REQ_BC_VER_4_VRFY_AFEX_SUPPORTED) ?
10815 FEATURE_CONFIG_BC_SUPPORTS_AFEX : 0;
10816 bp->link_params.feature_config_flags |=
10817 (val >= REQ_BC_VER_4_SFP_TX_DISABLE_SUPPORTED) ?
10818 FEATURE_CONFIG_BC_SUPPORTS_SFP_TX_DISABLED : 0;
10820 bp->link_params.feature_config_flags |=
10821 (val >= REQ_BC_VER_4_MT_SUPPORTED) ?
10822 FEATURE_CONFIG_MT_SUPPORT : 0;
10824 bp->flags |= (val >= REQ_BC_VER_4_PFC_STATS_SUPPORTED) ?
10825 BC_SUPPORTS_PFC_STATS : 0;
10827 bp->flags |= (val >= REQ_BC_VER_4_FCOE_FEATURES) ?
10828 BC_SUPPORTS_FCOE_FEATURES : 0;
10830 bp->flags |= (val >= REQ_BC_VER_4_DCBX_ADMIN_MSG_NON_PMF) ?
10831 BC_SUPPORTS_DCBX_MSG_NON_PMF : 0;
10833 bp->flags |= (val >= REQ_BC_VER_4_RMMOD_CMD) ?
10834 BC_SUPPORTS_RMMOD_CMD : 0;
10836 boot_mode = SHMEM_RD(bp,
10837 dev_info.port_feature_config[BP_PORT(bp)].mba_config) &
10838 PORT_FEATURE_MBA_BOOT_AGENT_TYPE_MASK;
10839 switch (boot_mode) {
10840 case PORT_FEATURE_MBA_BOOT_AGENT_TYPE_PXE:
10841 bp->common.boot_mode = FEATURE_ETH_BOOTMODE_PXE;
10843 case PORT_FEATURE_MBA_BOOT_AGENT_TYPE_ISCSIB:
10844 bp->common.boot_mode = FEATURE_ETH_BOOTMODE_ISCSI;
10846 case PORT_FEATURE_MBA_BOOT_AGENT_TYPE_FCOE_BOOT:
10847 bp->common.boot_mode = FEATURE_ETH_BOOTMODE_FCOE;
10849 case PORT_FEATURE_MBA_BOOT_AGENT_TYPE_NONE:
10850 bp->common.boot_mode = FEATURE_ETH_BOOTMODE_NONE;
10854 pci_read_config_word(bp->pdev, bp->pdev->pm_cap + PCI_PM_PMC, &pmc);
10855 bp->flags |= (pmc & PCI_PM_CAP_PME_D3cold) ? 0 : NO_WOL_FLAG;
10857 BNX2X_DEV_INFO("%sWoL capable\n",
10858 (bp->flags & NO_WOL_FLAG) ? "not " : "");
10860 val = SHMEM_RD(bp, dev_info.shared_hw_config.part_num);
10861 val2 = SHMEM_RD(bp, dev_info.shared_hw_config.part_num[4]);
10862 val3 = SHMEM_RD(bp, dev_info.shared_hw_config.part_num[8]);
10863 val4 = SHMEM_RD(bp, dev_info.shared_hw_config.part_num[12]);
10865 dev_info(&bp->pdev->dev, "part number %X-%X-%X-%X\n",
10866 val, val2, val3, val4);
10869 #define IGU_FID(val) GET_FIELD((val), IGU_REG_MAPPING_MEMORY_FID)
10870 #define IGU_VEC(val) GET_FIELD((val), IGU_REG_MAPPING_MEMORY_VECTOR)
10872 static int bnx2x_get_igu_cam_info(struct bnx2x *bp)
10874 int pfid = BP_FUNC(bp);
10877 u8 fid, igu_sb_cnt = 0;
10879 bp->igu_base_sb = 0xff;
10880 if (CHIP_INT_MODE_IS_BC(bp)) {
10881 int vn = BP_VN(bp);
10882 igu_sb_cnt = bp->igu_sb_cnt;
10883 bp->igu_base_sb = (CHIP_MODE_IS_4_PORT(bp) ? pfid : vn) *
10886 bp->igu_dsb_id = E1HVN_MAX * FP_SB_MAX_E1x +
10887 (CHIP_MODE_IS_4_PORT(bp) ? pfid : vn);
10892 /* IGU in normal mode - read CAM */
10893 for (igu_sb_id = 0; igu_sb_id < IGU_REG_MAPPING_MEMORY_SIZE;
10895 val = REG_RD(bp, IGU_REG_MAPPING_MEMORY + igu_sb_id * 4);
10896 if (!(val & IGU_REG_MAPPING_MEMORY_VALID))
10898 fid = IGU_FID(val);
10899 if ((fid & IGU_FID_ENCODE_IS_PF)) {
10900 if ((fid & IGU_FID_PF_NUM_MASK) != pfid)
10902 if (IGU_VEC(val) == 0)
10903 /* default status block */
10904 bp->igu_dsb_id = igu_sb_id;
10906 if (bp->igu_base_sb == 0xff)
10907 bp->igu_base_sb = igu_sb_id;
10913 #ifdef CONFIG_PCI_MSI
10914 /* Due to new PF resource allocation by MFW T7.4 and above, it's
10915 * optional that number of CAM entries will not be equal to the value
10916 * advertised in PCI.
10917 * Driver should use the minimal value of both as the actual status
10920 bp->igu_sb_cnt = min_t(int, bp->igu_sb_cnt, igu_sb_cnt);
10923 if (igu_sb_cnt == 0) {
10924 BNX2X_ERR("CAM configuration error\n");
10931 static void bnx2x_link_settings_supported(struct bnx2x *bp, u32 switch_cfg)
10933 int cfg_size = 0, idx, port = BP_PORT(bp);
10935 /* Aggregation of supported attributes of all external phys */
10936 bp->port.supported[0] = 0;
10937 bp->port.supported[1] = 0;
10938 switch (bp->link_params.num_phys) {
10940 bp->port.supported[0] = bp->link_params.phy[INT_PHY].supported;
10944 bp->port.supported[0] = bp->link_params.phy[EXT_PHY1].supported;
10948 if (bp->link_params.multi_phy_config &
10949 PORT_HW_CFG_PHY_SWAPPED_ENABLED) {
10950 bp->port.supported[1] =
10951 bp->link_params.phy[EXT_PHY1].supported;
10952 bp->port.supported[0] =
10953 bp->link_params.phy[EXT_PHY2].supported;
10955 bp->port.supported[0] =
10956 bp->link_params.phy[EXT_PHY1].supported;
10957 bp->port.supported[1] =
10958 bp->link_params.phy[EXT_PHY2].supported;
10964 if (!(bp->port.supported[0] || bp->port.supported[1])) {
10965 BNX2X_ERR("NVRAM config error. BAD phy config. PHY1 config 0x%x, PHY2 config 0x%x\n",
10967 dev_info.port_hw_config[port].external_phy_config),
10969 dev_info.port_hw_config[port].external_phy_config2));
10973 if (CHIP_IS_E3(bp))
10974 bp->port.phy_addr = REG_RD(bp, MISC_REG_WC0_CTRL_PHY_ADDR);
10976 switch (switch_cfg) {
10977 case SWITCH_CFG_1G:
10978 bp->port.phy_addr = REG_RD(
10979 bp, NIG_REG_SERDES0_CTRL_PHY_ADDR + port*0x10);
10981 case SWITCH_CFG_10G:
10982 bp->port.phy_addr = REG_RD(
10983 bp, NIG_REG_XGXS0_CTRL_PHY_ADDR + port*0x18);
10986 BNX2X_ERR("BAD switch_cfg link_config 0x%x\n",
10987 bp->port.link_config[0]);
10991 BNX2X_DEV_INFO("phy_addr 0x%x\n", bp->port.phy_addr);
10992 /* mask what we support according to speed_cap_mask per configuration */
10993 for (idx = 0; idx < cfg_size; idx++) {
10994 if (!(bp->link_params.speed_cap_mask[idx] &
10995 PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_HALF))
10996 bp->port.supported[idx] &= ~SUPPORTED_10baseT_Half;
10998 if (!(bp->link_params.speed_cap_mask[idx] &
10999 PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_FULL))
11000 bp->port.supported[idx] &= ~SUPPORTED_10baseT_Full;
11002 if (!(bp->link_params.speed_cap_mask[idx] &
11003 PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_HALF))
11004 bp->port.supported[idx] &= ~SUPPORTED_100baseT_Half;
11006 if (!(bp->link_params.speed_cap_mask[idx] &
11007 PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_FULL))
11008 bp->port.supported[idx] &= ~SUPPORTED_100baseT_Full;
11010 if (!(bp->link_params.speed_cap_mask[idx] &
11011 PORT_HW_CFG_SPEED_CAPABILITY_D0_1G))
11012 bp->port.supported[idx] &= ~(SUPPORTED_1000baseT_Half |
11013 SUPPORTED_1000baseT_Full);
11015 if (!(bp->link_params.speed_cap_mask[idx] &
11016 PORT_HW_CFG_SPEED_CAPABILITY_D0_2_5G))
11017 bp->port.supported[idx] &= ~SUPPORTED_2500baseX_Full;
11019 if (!(bp->link_params.speed_cap_mask[idx] &
11020 PORT_HW_CFG_SPEED_CAPABILITY_D0_10G))
11021 bp->port.supported[idx] &= ~SUPPORTED_10000baseT_Full;
11023 if (!(bp->link_params.speed_cap_mask[idx] &
11024 PORT_HW_CFG_SPEED_CAPABILITY_D0_20G))
11025 bp->port.supported[idx] &= ~SUPPORTED_20000baseKR2_Full;
11028 BNX2X_DEV_INFO("supported 0x%x 0x%x\n", bp->port.supported[0],
11029 bp->port.supported[1]);
11032 static void bnx2x_link_settings_requested(struct bnx2x *bp)
11034 u32 link_config, idx, cfg_size = 0;
11035 bp->port.advertising[0] = 0;
11036 bp->port.advertising[1] = 0;
11037 switch (bp->link_params.num_phys) {
11046 for (idx = 0; idx < cfg_size; idx++) {
11047 bp->link_params.req_duplex[idx] = DUPLEX_FULL;
11048 link_config = bp->port.link_config[idx];
11049 switch (link_config & PORT_FEATURE_LINK_SPEED_MASK) {
11050 case PORT_FEATURE_LINK_SPEED_AUTO:
11051 if (bp->port.supported[idx] & SUPPORTED_Autoneg) {
11052 bp->link_params.req_line_speed[idx] =
11054 bp->port.advertising[idx] |=
11055 bp->port.supported[idx];
11056 if (bp->link_params.phy[EXT_PHY1].type ==
11057 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84833)
11058 bp->port.advertising[idx] |=
11059 (SUPPORTED_100baseT_Half |
11060 SUPPORTED_100baseT_Full);
11062 /* force 10G, no AN */
11063 bp->link_params.req_line_speed[idx] =
11065 bp->port.advertising[idx] |=
11066 (ADVERTISED_10000baseT_Full |
11072 case PORT_FEATURE_LINK_SPEED_10M_FULL:
11073 if (bp->port.supported[idx] & SUPPORTED_10baseT_Full) {
11074 bp->link_params.req_line_speed[idx] =
11076 bp->port.advertising[idx] |=
11077 (ADVERTISED_10baseT_Full |
11080 BNX2X_ERR("NVRAM config error. Invalid link_config 0x%x speed_cap_mask 0x%x\n",
11082 bp->link_params.speed_cap_mask[idx]);
11087 case PORT_FEATURE_LINK_SPEED_10M_HALF:
11088 if (bp->port.supported[idx] & SUPPORTED_10baseT_Half) {
11089 bp->link_params.req_line_speed[idx] =
11091 bp->link_params.req_duplex[idx] =
11093 bp->port.advertising[idx] |=
11094 (ADVERTISED_10baseT_Half |
11097 BNX2X_ERR("NVRAM config error. Invalid link_config 0x%x speed_cap_mask 0x%x\n",
11099 bp->link_params.speed_cap_mask[idx]);
11104 case PORT_FEATURE_LINK_SPEED_100M_FULL:
11105 if (bp->port.supported[idx] &
11106 SUPPORTED_100baseT_Full) {
11107 bp->link_params.req_line_speed[idx] =
11109 bp->port.advertising[idx] |=
11110 (ADVERTISED_100baseT_Full |
11113 BNX2X_ERR("NVRAM config error. Invalid link_config 0x%x speed_cap_mask 0x%x\n",
11115 bp->link_params.speed_cap_mask[idx]);
11120 case PORT_FEATURE_LINK_SPEED_100M_HALF:
11121 if (bp->port.supported[idx] &
11122 SUPPORTED_100baseT_Half) {
11123 bp->link_params.req_line_speed[idx] =
11125 bp->link_params.req_duplex[idx] =
11127 bp->port.advertising[idx] |=
11128 (ADVERTISED_100baseT_Half |
11131 BNX2X_ERR("NVRAM config error. Invalid link_config 0x%x speed_cap_mask 0x%x\n",
11133 bp->link_params.speed_cap_mask[idx]);
11138 case PORT_FEATURE_LINK_SPEED_1G:
11139 if (bp->port.supported[idx] &
11140 SUPPORTED_1000baseT_Full) {
11141 bp->link_params.req_line_speed[idx] =
11143 bp->port.advertising[idx] |=
11144 (ADVERTISED_1000baseT_Full |
11147 BNX2X_ERR("NVRAM config error. Invalid link_config 0x%x speed_cap_mask 0x%x\n",
11149 bp->link_params.speed_cap_mask[idx]);
11154 case PORT_FEATURE_LINK_SPEED_2_5G:
11155 if (bp->port.supported[idx] &
11156 SUPPORTED_2500baseX_Full) {
11157 bp->link_params.req_line_speed[idx] =
11159 bp->port.advertising[idx] |=
11160 (ADVERTISED_2500baseX_Full |
11163 BNX2X_ERR("NVRAM config error. Invalid link_config 0x%x speed_cap_mask 0x%x\n",
11165 bp->link_params.speed_cap_mask[idx]);
11170 case PORT_FEATURE_LINK_SPEED_10G_CX4:
11171 if (bp->port.supported[idx] &
11172 SUPPORTED_10000baseT_Full) {
11173 bp->link_params.req_line_speed[idx] =
11175 bp->port.advertising[idx] |=
11176 (ADVERTISED_10000baseT_Full |
11179 BNX2X_ERR("NVRAM config error. Invalid link_config 0x%x speed_cap_mask 0x%x\n",
11181 bp->link_params.speed_cap_mask[idx]);
11185 case PORT_FEATURE_LINK_SPEED_20G:
11186 bp->link_params.req_line_speed[idx] = SPEED_20000;
11190 BNX2X_ERR("NVRAM config error. BAD link speed link_config 0x%x\n",
11192 bp->link_params.req_line_speed[idx] =
11194 bp->port.advertising[idx] =
11195 bp->port.supported[idx];
11199 bp->link_params.req_flow_ctrl[idx] = (link_config &
11200 PORT_FEATURE_FLOW_CONTROL_MASK);
11201 if (bp->link_params.req_flow_ctrl[idx] ==
11202 BNX2X_FLOW_CTRL_AUTO) {
11203 if (!(bp->port.supported[idx] & SUPPORTED_Autoneg))
11204 bp->link_params.req_flow_ctrl[idx] =
11205 BNX2X_FLOW_CTRL_NONE;
11207 bnx2x_set_requested_fc(bp);
11210 BNX2X_DEV_INFO("req_line_speed %d req_duplex %d req_flow_ctrl 0x%x advertising 0x%x\n",
11211 bp->link_params.req_line_speed[idx],
11212 bp->link_params.req_duplex[idx],
11213 bp->link_params.req_flow_ctrl[idx],
11214 bp->port.advertising[idx]);
11218 static void bnx2x_set_mac_buf(u8 *mac_buf, u32 mac_lo, u16 mac_hi)
11220 __be16 mac_hi_be = cpu_to_be16(mac_hi);
11221 __be32 mac_lo_be = cpu_to_be32(mac_lo);
11222 memcpy(mac_buf, &mac_hi_be, sizeof(mac_hi_be));
11223 memcpy(mac_buf + sizeof(mac_hi_be), &mac_lo_be, sizeof(mac_lo_be));
11226 static void bnx2x_get_port_hwinfo(struct bnx2x *bp)
11228 int port = BP_PORT(bp);
11230 u32 ext_phy_type, ext_phy_config, eee_mode;
11232 bp->link_params.bp = bp;
11233 bp->link_params.port = port;
11235 bp->link_params.lane_config =
11236 SHMEM_RD(bp, dev_info.port_hw_config[port].lane_config);
11238 bp->link_params.speed_cap_mask[0] =
11240 dev_info.port_hw_config[port].speed_capability_mask) &
11241 PORT_HW_CFG_SPEED_CAPABILITY_D0_MASK;
11242 bp->link_params.speed_cap_mask[1] =
11244 dev_info.port_hw_config[port].speed_capability_mask2) &
11245 PORT_HW_CFG_SPEED_CAPABILITY_D0_MASK;
11246 bp->port.link_config[0] =
11247 SHMEM_RD(bp, dev_info.port_feature_config[port].link_config);
11249 bp->port.link_config[1] =
11250 SHMEM_RD(bp, dev_info.port_feature_config[port].link_config2);
11252 bp->link_params.multi_phy_config =
11253 SHMEM_RD(bp, dev_info.port_hw_config[port].multi_phy_config);
11254 /* If the device is capable of WoL, set the default state according
11257 config = SHMEM_RD(bp, dev_info.port_feature_config[port].config);
11258 bp->wol = (!(bp->flags & NO_WOL_FLAG) &&
11259 (config & PORT_FEATURE_WOL_ENABLED));
11261 if ((config & PORT_FEAT_CFG_STORAGE_PERSONALITY_MASK) ==
11262 PORT_FEAT_CFG_STORAGE_PERSONALITY_FCOE && !IS_MF(bp))
11263 bp->flags |= NO_ISCSI_FLAG;
11264 if ((config & PORT_FEAT_CFG_STORAGE_PERSONALITY_MASK) ==
11265 PORT_FEAT_CFG_STORAGE_PERSONALITY_ISCSI && !(IS_MF(bp)))
11266 bp->flags |= NO_FCOE_FLAG;
11268 BNX2X_DEV_INFO("lane_config 0x%08x speed_cap_mask0 0x%08x link_config0 0x%08x\n",
11269 bp->link_params.lane_config,
11270 bp->link_params.speed_cap_mask[0],
11271 bp->port.link_config[0]);
11273 bp->link_params.switch_cfg = (bp->port.link_config[0] &
11274 PORT_FEATURE_CONNECTED_SWITCH_MASK);
11275 bnx2x_phy_probe(&bp->link_params);
11276 bnx2x_link_settings_supported(bp, bp->link_params.switch_cfg);
11278 bnx2x_link_settings_requested(bp);
11281 * If connected directly, work with the internal PHY, otherwise, work
11282 * with the external PHY
11286 dev_info.port_hw_config[port].external_phy_config);
11287 ext_phy_type = XGXS_EXT_PHY_TYPE(ext_phy_config);
11288 if (ext_phy_type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT)
11289 bp->mdio.prtad = bp->port.phy_addr;
11291 else if ((ext_phy_type != PORT_HW_CFG_XGXS_EXT_PHY_TYPE_FAILURE) &&
11292 (ext_phy_type != PORT_HW_CFG_XGXS_EXT_PHY_TYPE_NOT_CONN))
11294 XGXS_EXT_PHY_ADDR(ext_phy_config);
11296 /* Configure link feature according to nvram value */
11297 eee_mode = (((SHMEM_RD(bp, dev_info.
11298 port_feature_config[port].eee_power_mode)) &
11299 PORT_FEAT_CFG_EEE_POWER_MODE_MASK) >>
11300 PORT_FEAT_CFG_EEE_POWER_MODE_SHIFT);
11301 if (eee_mode != PORT_FEAT_CFG_EEE_POWER_MODE_DISABLED) {
11302 bp->link_params.eee_mode = EEE_MODE_ADV_LPI |
11303 EEE_MODE_ENABLE_LPI |
11304 EEE_MODE_OUTPUT_TIME;
11306 bp->link_params.eee_mode = 0;
11310 void bnx2x_get_iscsi_info(struct bnx2x *bp)
11312 u32 no_flags = NO_ISCSI_FLAG;
11313 int port = BP_PORT(bp);
11314 u32 max_iscsi_conn = FW_ENCODE_32BIT_PATTERN ^ SHMEM_RD(bp,
11315 drv_lic_key[port].max_iscsi_conn);
11317 if (!CNIC_SUPPORT(bp)) {
11318 bp->flags |= no_flags;
11322 /* Get the number of maximum allowed iSCSI connections */
11323 bp->cnic_eth_dev.max_iscsi_conn =
11324 (max_iscsi_conn & BNX2X_MAX_ISCSI_INIT_CONN_MASK) >>
11325 BNX2X_MAX_ISCSI_INIT_CONN_SHIFT;
11327 BNX2X_DEV_INFO("max_iscsi_conn 0x%x\n",
11328 bp->cnic_eth_dev.max_iscsi_conn);
11331 * If maximum allowed number of connections is zero -
11332 * disable the feature.
11334 if (!bp->cnic_eth_dev.max_iscsi_conn)
11335 bp->flags |= no_flags;
11338 static void bnx2x_get_ext_wwn_info(struct bnx2x *bp, int func)
11341 bp->cnic_eth_dev.fcoe_wwn_port_name_hi =
11342 MF_CFG_RD(bp, func_ext_config[func].fcoe_wwn_port_name_upper);
11343 bp->cnic_eth_dev.fcoe_wwn_port_name_lo =
11344 MF_CFG_RD(bp, func_ext_config[func].fcoe_wwn_port_name_lower);
11347 bp->cnic_eth_dev.fcoe_wwn_node_name_hi =
11348 MF_CFG_RD(bp, func_ext_config[func].fcoe_wwn_node_name_upper);
11349 bp->cnic_eth_dev.fcoe_wwn_node_name_lo =
11350 MF_CFG_RD(bp, func_ext_config[func].fcoe_wwn_node_name_lower);
11353 static int bnx2x_shared_fcoe_funcs(struct bnx2x *bp)
11360 /* iterate over absolute function ids for this path: */
11361 for (fid = BP_PATH(bp); fid < E2_FUNC_MAX * 2; fid += 2) {
11362 if (IS_MF_SD(bp)) {
11363 u32 cfg = MF_CFG_RD(bp,
11364 func_mf_config[fid].config);
11366 if (!(cfg & FUNC_MF_CFG_FUNC_HIDE) &&
11367 ((cfg & FUNC_MF_CFG_PROTOCOL_MASK) ==
11368 FUNC_MF_CFG_PROTOCOL_FCOE))
11371 u32 cfg = MF_CFG_RD(bp,
11372 func_ext_config[fid].
11375 if ((cfg & MACP_FUNC_CFG_FLAGS_ENABLED) &&
11376 (cfg & MACP_FUNC_CFG_FLAGS_FCOE_OFFLOAD))
11381 int port, port_cnt = CHIP_MODE_IS_4_PORT(bp) ? 2 : 1;
11383 for (port = 0; port < port_cnt; port++) {
11384 u32 lic = SHMEM_RD(bp,
11385 drv_lic_key[port].max_fcoe_conn) ^
11386 FW_ENCODE_32BIT_PATTERN;
11395 static void bnx2x_get_fcoe_info(struct bnx2x *bp)
11397 int port = BP_PORT(bp);
11398 int func = BP_ABS_FUNC(bp);
11399 u32 max_fcoe_conn = FW_ENCODE_32BIT_PATTERN ^ SHMEM_RD(bp,
11400 drv_lic_key[port].max_fcoe_conn);
11401 u8 num_fcoe_func = bnx2x_shared_fcoe_funcs(bp);
11403 if (!CNIC_SUPPORT(bp)) {
11404 bp->flags |= NO_FCOE_FLAG;
11408 /* Get the number of maximum allowed FCoE connections */
11409 bp->cnic_eth_dev.max_fcoe_conn =
11410 (max_fcoe_conn & BNX2X_MAX_FCOE_INIT_CONN_MASK) >>
11411 BNX2X_MAX_FCOE_INIT_CONN_SHIFT;
11413 /* Calculate the number of maximum allowed FCoE tasks */
11414 bp->cnic_eth_dev.max_fcoe_exchanges = MAX_NUM_FCOE_TASKS_PER_ENGINE;
11416 /* check if FCoE resources must be shared between different functions */
11418 bp->cnic_eth_dev.max_fcoe_exchanges /= num_fcoe_func;
11420 /* Read the WWN: */
11423 bp->cnic_eth_dev.fcoe_wwn_port_name_hi =
11425 dev_info.port_hw_config[port].
11426 fcoe_wwn_port_name_upper);
11427 bp->cnic_eth_dev.fcoe_wwn_port_name_lo =
11429 dev_info.port_hw_config[port].
11430 fcoe_wwn_port_name_lower);
11433 bp->cnic_eth_dev.fcoe_wwn_node_name_hi =
11435 dev_info.port_hw_config[port].
11436 fcoe_wwn_node_name_upper);
11437 bp->cnic_eth_dev.fcoe_wwn_node_name_lo =
11439 dev_info.port_hw_config[port].
11440 fcoe_wwn_node_name_lower);
11441 } else if (!IS_MF_SD(bp)) {
11442 /* Read the WWN info only if the FCoE feature is enabled for
11445 if (BNX2X_HAS_MF_EXT_PROTOCOL_FCOE(bp))
11446 bnx2x_get_ext_wwn_info(bp, func);
11448 if (BNX2X_IS_MF_SD_PROTOCOL_FCOE(bp) && !CHIP_IS_E1x(bp))
11449 bnx2x_get_ext_wwn_info(bp, func);
11452 BNX2X_DEV_INFO("max_fcoe_conn 0x%x\n", bp->cnic_eth_dev.max_fcoe_conn);
11455 * If maximum allowed number of connections is zero -
11456 * disable the feature.
11458 if (!bp->cnic_eth_dev.max_fcoe_conn)
11459 bp->flags |= NO_FCOE_FLAG;
11462 static void bnx2x_get_cnic_info(struct bnx2x *bp)
11465 * iSCSI may be dynamically disabled but reading
11466 * info here we will decrease memory usage by driver
11467 * if the feature is disabled for good
11469 bnx2x_get_iscsi_info(bp);
11470 bnx2x_get_fcoe_info(bp);
11473 static void bnx2x_get_cnic_mac_hwinfo(struct bnx2x *bp)
11476 int func = BP_ABS_FUNC(bp);
11477 int port = BP_PORT(bp);
11478 u8 *iscsi_mac = bp->cnic_eth_dev.iscsi_mac;
11479 u8 *fip_mac = bp->fip_mac;
11482 /* iSCSI and FCoE NPAR MACs: if there is no either iSCSI or
11483 * FCoE MAC then the appropriate feature should be disabled.
11484 * In non SD mode features configuration comes from struct
11487 if (!IS_MF_SD(bp)) {
11488 u32 cfg = MF_CFG_RD(bp, func_ext_config[func].func_cfg);
11489 if (cfg & MACP_FUNC_CFG_FLAGS_ISCSI_OFFLOAD) {
11490 val2 = MF_CFG_RD(bp, func_ext_config[func].
11491 iscsi_mac_addr_upper);
11492 val = MF_CFG_RD(bp, func_ext_config[func].
11493 iscsi_mac_addr_lower);
11494 bnx2x_set_mac_buf(iscsi_mac, val, val2);
11496 ("Read iSCSI MAC: %pM\n", iscsi_mac);
11498 bp->flags |= NO_ISCSI_OOO_FLAG | NO_ISCSI_FLAG;
11501 if (cfg & MACP_FUNC_CFG_FLAGS_FCOE_OFFLOAD) {
11502 val2 = MF_CFG_RD(bp, func_ext_config[func].
11503 fcoe_mac_addr_upper);
11504 val = MF_CFG_RD(bp, func_ext_config[func].
11505 fcoe_mac_addr_lower);
11506 bnx2x_set_mac_buf(fip_mac, val, val2);
11508 ("Read FCoE L2 MAC: %pM\n", fip_mac);
11510 bp->flags |= NO_FCOE_FLAG;
11513 bp->mf_ext_config = cfg;
11515 } else { /* SD MODE */
11516 if (BNX2X_IS_MF_SD_PROTOCOL_ISCSI(bp)) {
11517 /* use primary mac as iscsi mac */
11518 memcpy(iscsi_mac, bp->dev->dev_addr, ETH_ALEN);
11520 BNX2X_DEV_INFO("SD ISCSI MODE\n");
11522 ("Read iSCSI MAC: %pM\n", iscsi_mac);
11523 } else if (BNX2X_IS_MF_SD_PROTOCOL_FCOE(bp)) {
11524 /* use primary mac as fip mac */
11525 memcpy(fip_mac, bp->dev->dev_addr, ETH_ALEN);
11526 BNX2X_DEV_INFO("SD FCoE MODE\n");
11528 ("Read FIP MAC: %pM\n", fip_mac);
11532 /* If this is a storage-only interface, use SAN mac as
11533 * primary MAC. Notice that for SD this is already the case,
11534 * as the SAN mac was copied from the primary MAC.
11536 if (IS_MF_FCOE_AFEX(bp))
11537 memcpy(bp->dev->dev_addr, fip_mac, ETH_ALEN);
11539 val2 = SHMEM_RD(bp, dev_info.port_hw_config[port].
11541 val = SHMEM_RD(bp, dev_info.port_hw_config[port].
11543 bnx2x_set_mac_buf(iscsi_mac, val, val2);
11545 val2 = SHMEM_RD(bp, dev_info.port_hw_config[port].
11546 fcoe_fip_mac_upper);
11547 val = SHMEM_RD(bp, dev_info.port_hw_config[port].
11548 fcoe_fip_mac_lower);
11549 bnx2x_set_mac_buf(fip_mac, val, val2);
11552 /* Disable iSCSI OOO if MAC configuration is invalid. */
11553 if (!is_valid_ether_addr(iscsi_mac)) {
11554 bp->flags |= NO_ISCSI_OOO_FLAG | NO_ISCSI_FLAG;
11555 eth_zero_addr(iscsi_mac);
11558 /* Disable FCoE if MAC configuration is invalid. */
11559 if (!is_valid_ether_addr(fip_mac)) {
11560 bp->flags |= NO_FCOE_FLAG;
11561 eth_zero_addr(bp->fip_mac);
11565 static void bnx2x_get_mac_hwinfo(struct bnx2x *bp)
11568 int func = BP_ABS_FUNC(bp);
11569 int port = BP_PORT(bp);
11571 /* Zero primary MAC configuration */
11572 eth_zero_addr(bp->dev->dev_addr);
11574 if (BP_NOMCP(bp)) {
11575 BNX2X_ERROR("warning: random MAC workaround active\n");
11576 eth_hw_addr_random(bp->dev);
11577 } else if (IS_MF(bp)) {
11578 val2 = MF_CFG_RD(bp, func_mf_config[func].mac_upper);
11579 val = MF_CFG_RD(bp, func_mf_config[func].mac_lower);
11580 if ((val2 != FUNC_MF_CFG_UPPERMAC_DEFAULT) &&
11581 (val != FUNC_MF_CFG_LOWERMAC_DEFAULT))
11582 bnx2x_set_mac_buf(bp->dev->dev_addr, val, val2);
11584 if (CNIC_SUPPORT(bp))
11585 bnx2x_get_cnic_mac_hwinfo(bp);
11587 /* in SF read MACs from port configuration */
11588 val2 = SHMEM_RD(bp, dev_info.port_hw_config[port].mac_upper);
11589 val = SHMEM_RD(bp, dev_info.port_hw_config[port].mac_lower);
11590 bnx2x_set_mac_buf(bp->dev->dev_addr, val, val2);
11592 if (CNIC_SUPPORT(bp))
11593 bnx2x_get_cnic_mac_hwinfo(bp);
11596 if (!BP_NOMCP(bp)) {
11597 /* Read physical port identifier from shmem */
11598 val2 = SHMEM_RD(bp, dev_info.port_hw_config[port].mac_upper);
11599 val = SHMEM_RD(bp, dev_info.port_hw_config[port].mac_lower);
11600 bnx2x_set_mac_buf(bp->phys_port_id, val, val2);
11601 bp->flags |= HAS_PHYS_PORT_ID;
11604 memcpy(bp->link_params.mac_addr, bp->dev->dev_addr, ETH_ALEN);
11606 if (!is_valid_ether_addr(bp->dev->dev_addr))
11607 dev_err(&bp->pdev->dev,
11608 "bad Ethernet MAC address configuration: %pM\n"
11609 "change it manually before bringing up the appropriate network interface\n",
11610 bp->dev->dev_addr);
11613 static bool bnx2x_get_dropless_info(struct bnx2x *bp)
11621 if (IS_MF(bp) && !CHIP_IS_E1x(bp)) {
11622 /* Take function: tmp = func */
11623 tmp = BP_ABS_FUNC(bp);
11624 cfg = MF_CFG_RD(bp, func_ext_config[tmp].func_cfg);
11625 cfg = !!(cfg & MACP_FUNC_CFG_PAUSE_ON_HOST_RING);
11627 /* Take port: tmp = port */
11630 dev_info.port_hw_config[tmp].generic_features);
11631 cfg = !!(cfg & PORT_HW_CFG_PAUSE_ON_HOST_RING_ENABLED);
11636 static void validate_set_si_mode(struct bnx2x *bp)
11638 u8 func = BP_ABS_FUNC(bp);
11641 val = MF_CFG_RD(bp, func_mf_config[func].mac_upper);
11643 /* check for legal mac (upper bytes) */
11644 if (val != 0xffff) {
11645 bp->mf_mode = MULTI_FUNCTION_SI;
11646 bp->mf_config[BP_VN(bp)] =
11647 MF_CFG_RD(bp, func_mf_config[func].config);
11649 BNX2X_DEV_INFO("illegal MAC address for SI\n");
11652 static int bnx2x_get_hwinfo(struct bnx2x *bp)
11654 int /*abs*/func = BP_ABS_FUNC(bp);
11656 u32 val = 0, val2 = 0;
11659 /* Validate that chip access is feasible */
11660 if (REG_RD(bp, MISC_REG_CHIP_NUM) == 0xffffffff) {
11661 dev_err(&bp->pdev->dev,
11662 "Chip read returns all Fs. Preventing probe from continuing\n");
11666 bnx2x_get_common_hwinfo(bp);
11669 * initialize IGU parameters
11671 if (CHIP_IS_E1x(bp)) {
11672 bp->common.int_block = INT_BLOCK_HC;
11674 bp->igu_dsb_id = DEF_SB_IGU_ID;
11675 bp->igu_base_sb = 0;
11677 bp->common.int_block = INT_BLOCK_IGU;
11679 /* do not allow device reset during IGU info processing */
11680 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_RESET);
11682 val = REG_RD(bp, IGU_REG_BLOCK_CONFIGURATION);
11684 if (val & IGU_BLOCK_CONFIGURATION_REG_BACKWARD_COMP_EN) {
11687 BNX2X_DEV_INFO("FORCING Normal Mode\n");
11689 val &= ~(IGU_BLOCK_CONFIGURATION_REG_BACKWARD_COMP_EN);
11690 REG_WR(bp, IGU_REG_BLOCK_CONFIGURATION, val);
11691 REG_WR(bp, IGU_REG_RESET_MEMORIES, 0x7f);
11693 while (tout && REG_RD(bp, IGU_REG_RESET_MEMORIES)) {
11695 usleep_range(1000, 2000);
11698 if (REG_RD(bp, IGU_REG_RESET_MEMORIES)) {
11699 dev_err(&bp->pdev->dev,
11700 "FORCING Normal Mode failed!!!\n");
11701 bnx2x_release_hw_lock(bp,
11702 HW_LOCK_RESOURCE_RESET);
11707 if (val & IGU_BLOCK_CONFIGURATION_REG_BACKWARD_COMP_EN) {
11708 BNX2X_DEV_INFO("IGU Backward Compatible Mode\n");
11709 bp->common.int_block |= INT_BLOCK_MODE_BW_COMP;
11711 BNX2X_DEV_INFO("IGU Normal Mode\n");
11713 rc = bnx2x_get_igu_cam_info(bp);
11714 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_RESET);
11720 * set base FW non-default (fast path) status block id, this value is
11721 * used to initialize the fw_sb_id saved on the fp/queue structure to
11722 * determine the id used by the FW.
11724 if (CHIP_IS_E1x(bp))
11725 bp->base_fw_ndsb = BP_PORT(bp) * FP_SB_MAX_E1x + BP_L_ID(bp);
11727 * 57712 - we currently use one FW SB per IGU SB (Rx and Tx of
11728 * the same queue are indicated on the same IGU SB). So we prefer
11729 * FW and IGU SBs to be the same value.
11731 bp->base_fw_ndsb = bp->igu_base_sb;
11733 BNX2X_DEV_INFO("igu_dsb_id %d igu_base_sb %d igu_sb_cnt %d\n"
11734 "base_fw_ndsb %d\n", bp->igu_dsb_id, bp->igu_base_sb,
11735 bp->igu_sb_cnt, bp->base_fw_ndsb);
11738 * Initialize MF configuration
11743 bp->mf_sub_mode = 0;
11746 if (!CHIP_IS_E1(bp) && !BP_NOMCP(bp)) {
11747 BNX2X_DEV_INFO("shmem2base 0x%x, size %d, mfcfg offset %d\n",
11748 bp->common.shmem2_base, SHMEM2_RD(bp, size),
11749 (u32)offsetof(struct shmem2_region, mf_cfg_addr));
11751 if (SHMEM2_HAS(bp, mf_cfg_addr))
11752 bp->common.mf_cfg_base = SHMEM2_RD(bp, mf_cfg_addr);
11754 bp->common.mf_cfg_base = bp->common.shmem_base +
11755 offsetof(struct shmem_region, func_mb) +
11756 E1H_FUNC_MAX * sizeof(struct drv_func_mb);
11758 * get mf configuration:
11759 * 1. Existence of MF configuration
11760 * 2. MAC address must be legal (check only upper bytes)
11761 * for Switch-Independent mode;
11762 * OVLAN must be legal for Switch-Dependent mode
11763 * 3. SF_MODE configures specific MF mode
11765 if (bp->common.mf_cfg_base != SHMEM_MF_CFG_ADDR_NONE) {
11766 /* get mf configuration */
11768 dev_info.shared_feature_config.config);
11769 val &= SHARED_FEAT_CFG_FORCE_SF_MODE_MASK;
11772 case SHARED_FEAT_CFG_FORCE_SF_MODE_SWITCH_INDEPT:
11773 validate_set_si_mode(bp);
11775 case SHARED_FEAT_CFG_FORCE_SF_MODE_AFEX_MODE:
11776 if ((!CHIP_IS_E1x(bp)) &&
11777 (MF_CFG_RD(bp, func_mf_config[func].
11778 mac_upper) != 0xffff) &&
11780 afex_driver_support))) {
11781 bp->mf_mode = MULTI_FUNCTION_AFEX;
11782 bp->mf_config[vn] = MF_CFG_RD(bp,
11783 func_mf_config[func].config);
11785 BNX2X_DEV_INFO("can not configure afex mode\n");
11788 case SHARED_FEAT_CFG_FORCE_SF_MODE_MF_ALLOWED:
11789 /* get OV configuration */
11790 val = MF_CFG_RD(bp,
11791 func_mf_config[FUNC_0].e1hov_tag);
11792 val &= FUNC_MF_CFG_E1HOV_TAG_MASK;
11794 if (val != FUNC_MF_CFG_E1HOV_TAG_DEFAULT) {
11795 bp->mf_mode = MULTI_FUNCTION_SD;
11796 bp->mf_config[vn] = MF_CFG_RD(bp,
11797 func_mf_config[func].config);
11799 BNX2X_DEV_INFO("illegal OV for SD\n");
11801 case SHARED_FEAT_CFG_FORCE_SF_MODE_UFP_MODE:
11802 bp->mf_mode = MULTI_FUNCTION_SD;
11803 bp->mf_sub_mode = SUB_MF_MODE_UFP;
11804 bp->mf_config[vn] =
11806 func_mf_config[func].config);
11808 case SHARED_FEAT_CFG_FORCE_SF_MODE_FORCED_SF:
11809 bp->mf_config[vn] = 0;
11811 case SHARED_FEAT_CFG_FORCE_SF_MODE_EXTENDED_MODE:
11812 val2 = SHMEM_RD(bp,
11813 dev_info.shared_hw_config.config_3);
11814 val2 &= SHARED_HW_CFG_EXTENDED_MF_MODE_MASK;
11816 case SHARED_HW_CFG_EXTENDED_MF_MODE_NPAR1_DOT_5:
11817 validate_set_si_mode(bp);
11819 SUB_MF_MODE_NPAR1_DOT_5;
11822 /* Unknown configuration */
11823 bp->mf_config[vn] = 0;
11824 BNX2X_DEV_INFO("unknown extended MF mode 0x%x\n",
11829 /* Unknown configuration: reset mf_config */
11830 bp->mf_config[vn] = 0;
11831 BNX2X_DEV_INFO("unknown MF mode 0x%x\n", val);
11835 BNX2X_DEV_INFO("%s function mode\n",
11836 IS_MF(bp) ? "multi" : "single");
11838 switch (bp->mf_mode) {
11839 case MULTI_FUNCTION_SD:
11840 val = MF_CFG_RD(bp, func_mf_config[func].e1hov_tag) &
11841 FUNC_MF_CFG_E1HOV_TAG_MASK;
11842 if (val != FUNC_MF_CFG_E1HOV_TAG_DEFAULT) {
11844 bp->path_has_ovlan = true;
11846 BNX2X_DEV_INFO("MF OV for func %d is %d (0x%04x)\n",
11847 func, bp->mf_ov, bp->mf_ov);
11848 } else if (bp->mf_sub_mode == SUB_MF_MODE_UFP) {
11849 dev_err(&bp->pdev->dev,
11850 "Unexpected - no valid MF OV for func %d in UFP mode\n",
11852 bp->path_has_ovlan = true;
11854 dev_err(&bp->pdev->dev,
11855 "No valid MF OV for func %d, aborting\n",
11860 case MULTI_FUNCTION_AFEX:
11861 BNX2X_DEV_INFO("func %d is in MF afex mode\n", func);
11863 case MULTI_FUNCTION_SI:
11864 BNX2X_DEV_INFO("func %d is in MF switch-independent mode\n",
11869 dev_err(&bp->pdev->dev,
11870 "VN %d is in a single function mode, aborting\n",
11877 /* check if other port on the path needs ovlan:
11878 * Since MF configuration is shared between ports
11879 * Possible mixed modes are only
11880 * {SF, SI} {SF, SD} {SD, SF} {SI, SF}
11882 if (CHIP_MODE_IS_4_PORT(bp) &&
11883 !bp->path_has_ovlan &&
11885 bp->common.mf_cfg_base != SHMEM_MF_CFG_ADDR_NONE) {
11886 u8 other_port = !BP_PORT(bp);
11887 u8 other_func = BP_PATH(bp) + 2*other_port;
11888 val = MF_CFG_RD(bp,
11889 func_mf_config[other_func].e1hov_tag);
11890 if (val != FUNC_MF_CFG_E1HOV_TAG_DEFAULT)
11891 bp->path_has_ovlan = true;
11895 /* adjust igu_sb_cnt to MF for E1H */
11896 if (CHIP_IS_E1H(bp) && IS_MF(bp))
11897 bp->igu_sb_cnt = min_t(u8, bp->igu_sb_cnt, E1H_MAX_MF_SB_COUNT);
11900 bnx2x_get_port_hwinfo(bp);
11902 /* Get MAC addresses */
11903 bnx2x_get_mac_hwinfo(bp);
11905 bnx2x_get_cnic_info(bp);
11910 static void bnx2x_read_fwinfo(struct bnx2x *bp)
11912 int cnt, i, block_end, rodi;
11913 char vpd_start[BNX2X_VPD_LEN+1];
11914 char str_id_reg[VENDOR_ID_LEN+1];
11915 char str_id_cap[VENDOR_ID_LEN+1];
11917 char *vpd_extended_data = NULL;
11920 cnt = pci_read_vpd(bp->pdev, 0, BNX2X_VPD_LEN, vpd_start);
11921 memset(bp->fw_ver, 0, sizeof(bp->fw_ver));
11923 if (cnt < BNX2X_VPD_LEN)
11924 goto out_not_found;
11926 /* VPD RO tag should be first tag after identifier string, hence
11927 * we should be able to find it in first BNX2X_VPD_LEN chars
11929 i = pci_vpd_find_tag(vpd_start, 0, BNX2X_VPD_LEN,
11930 PCI_VPD_LRDT_RO_DATA);
11932 goto out_not_found;
11934 block_end = i + PCI_VPD_LRDT_TAG_SIZE +
11935 pci_vpd_lrdt_size(&vpd_start[i]);
11937 i += PCI_VPD_LRDT_TAG_SIZE;
11939 if (block_end > BNX2X_VPD_LEN) {
11940 vpd_extended_data = kmalloc(block_end, GFP_KERNEL);
11941 if (vpd_extended_data == NULL)
11942 goto out_not_found;
11944 /* read rest of vpd image into vpd_extended_data */
11945 memcpy(vpd_extended_data, vpd_start, BNX2X_VPD_LEN);
11946 cnt = pci_read_vpd(bp->pdev, BNX2X_VPD_LEN,
11947 block_end - BNX2X_VPD_LEN,
11948 vpd_extended_data + BNX2X_VPD_LEN);
11949 if (cnt < (block_end - BNX2X_VPD_LEN))
11950 goto out_not_found;
11951 vpd_data = vpd_extended_data;
11953 vpd_data = vpd_start;
11955 /* now vpd_data holds full vpd content in both cases */
11957 rodi = pci_vpd_find_info_keyword(vpd_data, i, block_end,
11958 PCI_VPD_RO_KEYWORD_MFR_ID);
11960 goto out_not_found;
11962 len = pci_vpd_info_field_size(&vpd_data[rodi]);
11964 if (len != VENDOR_ID_LEN)
11965 goto out_not_found;
11967 rodi += PCI_VPD_INFO_FLD_HDR_SIZE;
11969 /* vendor specific info */
11970 snprintf(str_id_reg, VENDOR_ID_LEN + 1, "%04x", PCI_VENDOR_ID_DELL);
11971 snprintf(str_id_cap, VENDOR_ID_LEN + 1, "%04X", PCI_VENDOR_ID_DELL);
11972 if (!strncmp(str_id_reg, &vpd_data[rodi], VENDOR_ID_LEN) ||
11973 !strncmp(str_id_cap, &vpd_data[rodi], VENDOR_ID_LEN)) {
11975 rodi = pci_vpd_find_info_keyword(vpd_data, i, block_end,
11976 PCI_VPD_RO_KEYWORD_VENDOR0);
11978 len = pci_vpd_info_field_size(&vpd_data[rodi]);
11980 rodi += PCI_VPD_INFO_FLD_HDR_SIZE;
11982 if (len < 32 && (len + rodi) <= BNX2X_VPD_LEN) {
11983 memcpy(bp->fw_ver, &vpd_data[rodi], len);
11984 bp->fw_ver[len] = ' ';
11987 kfree(vpd_extended_data);
11991 kfree(vpd_extended_data);
11995 static void bnx2x_set_modes_bitmap(struct bnx2x *bp)
11999 if (CHIP_REV_IS_FPGA(bp))
12000 SET_FLAGS(flags, MODE_FPGA);
12001 else if (CHIP_REV_IS_EMUL(bp))
12002 SET_FLAGS(flags, MODE_EMUL);
12004 SET_FLAGS(flags, MODE_ASIC);
12006 if (CHIP_MODE_IS_4_PORT(bp))
12007 SET_FLAGS(flags, MODE_PORT4);
12009 SET_FLAGS(flags, MODE_PORT2);
12011 if (CHIP_IS_E2(bp))
12012 SET_FLAGS(flags, MODE_E2);
12013 else if (CHIP_IS_E3(bp)) {
12014 SET_FLAGS(flags, MODE_E3);
12015 if (CHIP_REV(bp) == CHIP_REV_Ax)
12016 SET_FLAGS(flags, MODE_E3_A0);
12017 else /*if (CHIP_REV(bp) == CHIP_REV_Bx)*/
12018 SET_FLAGS(flags, MODE_E3_B0 | MODE_COS3);
12022 SET_FLAGS(flags, MODE_MF);
12023 switch (bp->mf_mode) {
12024 case MULTI_FUNCTION_SD:
12025 SET_FLAGS(flags, MODE_MF_SD);
12027 case MULTI_FUNCTION_SI:
12028 SET_FLAGS(flags, MODE_MF_SI);
12030 case MULTI_FUNCTION_AFEX:
12031 SET_FLAGS(flags, MODE_MF_AFEX);
12035 SET_FLAGS(flags, MODE_SF);
12037 #if defined(__LITTLE_ENDIAN)
12038 SET_FLAGS(flags, MODE_LITTLE_ENDIAN);
12039 #else /*(__BIG_ENDIAN)*/
12040 SET_FLAGS(flags, MODE_BIG_ENDIAN);
12042 INIT_MODE_FLAGS(bp) = flags;
12045 static int bnx2x_init_bp(struct bnx2x *bp)
12050 mutex_init(&bp->port.phy_mutex);
12051 mutex_init(&bp->fw_mb_mutex);
12052 mutex_init(&bp->drv_info_mutex);
12053 sema_init(&bp->stats_lock, 1);
12054 bp->drv_info_mng_owner = false;
12056 INIT_DELAYED_WORK(&bp->sp_task, bnx2x_sp_task);
12057 INIT_DELAYED_WORK(&bp->sp_rtnl_task, bnx2x_sp_rtnl_task);
12058 INIT_DELAYED_WORK(&bp->period_task, bnx2x_period_task);
12059 INIT_DELAYED_WORK(&bp->iov_task, bnx2x_iov_task);
12061 rc = bnx2x_get_hwinfo(bp);
12065 eth_zero_addr(bp->dev->dev_addr);
12068 bnx2x_set_modes_bitmap(bp);
12070 rc = bnx2x_alloc_mem_bp(bp);
12074 bnx2x_read_fwinfo(bp);
12076 func = BP_FUNC(bp);
12078 /* need to reset chip if undi was active */
12079 if (IS_PF(bp) && !BP_NOMCP(bp)) {
12082 SHMEM_RD(bp, func_mb[BP_FW_MB_IDX(bp)].drv_mb_header) &
12083 DRV_MSG_SEQ_NUMBER_MASK;
12084 BNX2X_DEV_INFO("fw_seq 0x%08x\n", bp->fw_seq);
12086 rc = bnx2x_prev_unload(bp);
12088 bnx2x_free_mem_bp(bp);
12093 if (CHIP_REV_IS_FPGA(bp))
12094 dev_err(&bp->pdev->dev, "FPGA detected\n");
12096 if (BP_NOMCP(bp) && (func == 0))
12097 dev_err(&bp->pdev->dev, "MCP disabled, must load devices in order!\n");
12099 bp->disable_tpa = disable_tpa;
12100 bp->disable_tpa |= !!IS_MF_STORAGE_ONLY(bp);
12101 /* Reduce memory usage in kdump environment by disabling TPA */
12102 bp->disable_tpa |= is_kdump_kernel();
12104 /* Set TPA flags */
12105 if (bp->disable_tpa) {
12106 bp->dev->hw_features &= ~NETIF_F_LRO;
12107 bp->dev->features &= ~NETIF_F_LRO;
12110 if (CHIP_IS_E1(bp))
12111 bp->dropless_fc = 0;
12113 bp->dropless_fc = dropless_fc | bnx2x_get_dropless_info(bp);
12117 bp->tx_ring_size = IS_MF_STORAGE_ONLY(bp) ? 0 : MAX_TX_AVAIL;
12119 bp->rx_ring_size = MAX_RX_AVAIL;
12121 /* make sure that the numbers are in the right granularity */
12122 bp->tx_ticks = (50 / BNX2X_BTR) * BNX2X_BTR;
12123 bp->rx_ticks = (25 / BNX2X_BTR) * BNX2X_BTR;
12125 bp->current_interval = CHIP_REV_IS_SLOW(bp) ? 5*HZ : HZ;
12127 init_timer(&bp->timer);
12128 bp->timer.expires = jiffies + bp->current_interval;
12129 bp->timer.data = (unsigned long) bp;
12130 bp->timer.function = bnx2x_timer;
12132 if (SHMEM2_HAS(bp, dcbx_lldp_params_offset) &&
12133 SHMEM2_HAS(bp, dcbx_lldp_dcbx_stat_offset) &&
12134 SHMEM2_RD(bp, dcbx_lldp_params_offset) &&
12135 SHMEM2_RD(bp, dcbx_lldp_dcbx_stat_offset)) {
12136 bnx2x_dcbx_set_state(bp, true, BNX2X_DCBX_ENABLED_ON_NEG_ON);
12137 bnx2x_dcbx_init_params(bp);
12139 bnx2x_dcbx_set_state(bp, false, BNX2X_DCBX_ENABLED_OFF);
12142 if (CHIP_IS_E1x(bp))
12143 bp->cnic_base_cl_id = FP_SB_MAX_E1x;
12145 bp->cnic_base_cl_id = FP_SB_MAX_E2;
12147 /* multiple tx priority */
12150 else if (CHIP_IS_E1x(bp))
12151 bp->max_cos = BNX2X_MULTI_TX_COS_E1X;
12152 else if (CHIP_IS_E2(bp) || CHIP_IS_E3A0(bp))
12153 bp->max_cos = BNX2X_MULTI_TX_COS_E2_E3A0;
12154 else if (CHIP_IS_E3B0(bp))
12155 bp->max_cos = BNX2X_MULTI_TX_COS_E3B0;
12157 BNX2X_ERR("unknown chip %x revision %x\n",
12158 CHIP_NUM(bp), CHIP_REV(bp));
12159 BNX2X_DEV_INFO("set bp->max_cos to %d\n", bp->max_cos);
12161 /* We need at least one default status block for slow-path events,
12162 * second status block for the L2 queue, and a third status block for
12163 * CNIC if supported.
12166 bp->min_msix_vec_cnt = 1;
12167 else if (CNIC_SUPPORT(bp))
12168 bp->min_msix_vec_cnt = 3;
12169 else /* PF w/o cnic */
12170 bp->min_msix_vec_cnt = 2;
12171 BNX2X_DEV_INFO("bp->min_msix_vec_cnt %d", bp->min_msix_vec_cnt);
12173 bp->dump_preset_idx = 1;
12175 if (CHIP_IS_E3B0(bp))
12176 bp->flags |= PTP_SUPPORTED;
12181 /****************************************************************************
12182 * General service functions
12183 ****************************************************************************/
12186 * net_device service functions
12189 /* called with rtnl_lock */
12190 static int bnx2x_open(struct net_device *dev)
12192 struct bnx2x *bp = netdev_priv(dev);
12195 bp->stats_init = true;
12197 netif_carrier_off(dev);
12199 bnx2x_set_power_state(bp, PCI_D0);
12201 /* If parity had happen during the unload, then attentions
12202 * and/or RECOVERY_IN_PROGRES may still be set. In this case we
12203 * want the first function loaded on the current engine to
12204 * complete the recovery.
12205 * Parity recovery is only relevant for PF driver.
12208 int other_engine = BP_PATH(bp) ? 0 : 1;
12209 bool other_load_status, load_status;
12210 bool global = false;
12212 other_load_status = bnx2x_get_load_status(bp, other_engine);
12213 load_status = bnx2x_get_load_status(bp, BP_PATH(bp));
12214 if (!bnx2x_reset_is_done(bp, BP_PATH(bp)) ||
12215 bnx2x_chk_parity_attn(bp, &global, true)) {
12217 /* If there are attentions and they are in a
12218 * global blocks, set the GLOBAL_RESET bit
12219 * regardless whether it will be this function
12220 * that will complete the recovery or not.
12223 bnx2x_set_reset_global(bp);
12225 /* Only the first function on the current
12226 * engine should try to recover in open. In case
12227 * of attentions in global blocks only the first
12228 * in the chip should try to recover.
12230 if ((!load_status &&
12231 (!global || !other_load_status)) &&
12232 bnx2x_trylock_leader_lock(bp) &&
12233 !bnx2x_leader_reset(bp)) {
12234 netdev_info(bp->dev,
12235 "Recovered in open\n");
12239 /* recovery has failed... */
12240 bnx2x_set_power_state(bp, PCI_D3hot);
12241 bp->recovery_state = BNX2X_RECOVERY_FAILED;
12243 BNX2X_ERR("Recovery flow hasn't been properly completed yet. Try again later.\n"
12244 "If you still see this message after a few retries then power cycle is required.\n");
12251 bp->recovery_state = BNX2X_RECOVERY_DONE;
12252 rc = bnx2x_nic_load(bp, LOAD_OPEN);
12258 /* called with rtnl_lock */
12259 static int bnx2x_close(struct net_device *dev)
12261 struct bnx2x *bp = netdev_priv(dev);
12263 /* Unload the driver, release IRQs */
12264 bnx2x_nic_unload(bp, UNLOAD_CLOSE, false);
12269 static int bnx2x_init_mcast_macs_list(struct bnx2x *bp,
12270 struct bnx2x_mcast_ramrod_params *p)
12272 int mc_count = netdev_mc_count(bp->dev);
12273 struct bnx2x_mcast_list_elem *mc_mac =
12274 kcalloc(mc_count, sizeof(*mc_mac), GFP_ATOMIC);
12275 struct netdev_hw_addr *ha;
12280 INIT_LIST_HEAD(&p->mcast_list);
12282 netdev_for_each_mc_addr(ha, bp->dev) {
12283 mc_mac->mac = bnx2x_mc_addr(ha);
12284 list_add_tail(&mc_mac->link, &p->mcast_list);
12288 p->mcast_list_len = mc_count;
12293 static void bnx2x_free_mcast_macs_list(
12294 struct bnx2x_mcast_ramrod_params *p)
12296 struct bnx2x_mcast_list_elem *mc_mac =
12297 list_first_entry(&p->mcast_list, struct bnx2x_mcast_list_elem,
12305 * bnx2x_set_uc_list - configure a new unicast MACs list.
12307 * @bp: driver handle
12309 * We will use zero (0) as a MAC type for these MACs.
12311 static int bnx2x_set_uc_list(struct bnx2x *bp)
12314 struct net_device *dev = bp->dev;
12315 struct netdev_hw_addr *ha;
12316 struct bnx2x_vlan_mac_obj *mac_obj = &bp->sp_objs->mac_obj;
12317 unsigned long ramrod_flags = 0;
12319 /* First schedule a cleanup up of old configuration */
12320 rc = bnx2x_del_all_macs(bp, mac_obj, BNX2X_UC_LIST_MAC, false);
12322 BNX2X_ERR("Failed to schedule DELETE operations: %d\n", rc);
12326 netdev_for_each_uc_addr(ha, dev) {
12327 rc = bnx2x_set_mac_one(bp, bnx2x_uc_addr(ha), mac_obj, true,
12328 BNX2X_UC_LIST_MAC, &ramrod_flags);
12329 if (rc == -EEXIST) {
12331 "Failed to schedule ADD operations: %d\n", rc);
12332 /* do not treat adding same MAC as error */
12335 } else if (rc < 0) {
12337 BNX2X_ERR("Failed to schedule ADD operations: %d\n",
12343 /* Execute the pending commands */
12344 __set_bit(RAMROD_CONT, &ramrod_flags);
12345 return bnx2x_set_mac_one(bp, NULL, mac_obj, false /* don't care */,
12346 BNX2X_UC_LIST_MAC, &ramrod_flags);
12349 static int bnx2x_set_mc_list(struct bnx2x *bp)
12351 struct net_device *dev = bp->dev;
12352 struct bnx2x_mcast_ramrod_params rparam = {NULL};
12355 rparam.mcast_obj = &bp->mcast_obj;
12357 /* first, clear all configured multicast MACs */
12358 rc = bnx2x_config_mcast(bp, &rparam, BNX2X_MCAST_CMD_DEL);
12360 BNX2X_ERR("Failed to clear multicast configuration: %d\n", rc);
12364 /* then, configure a new MACs list */
12365 if (netdev_mc_count(dev)) {
12366 rc = bnx2x_init_mcast_macs_list(bp, &rparam);
12368 BNX2X_ERR("Failed to create multicast MACs list: %d\n",
12373 /* Now add the new MACs */
12374 rc = bnx2x_config_mcast(bp, &rparam,
12375 BNX2X_MCAST_CMD_ADD);
12377 BNX2X_ERR("Failed to set a new multicast configuration: %d\n",
12380 bnx2x_free_mcast_macs_list(&rparam);
12386 /* If bp->state is OPEN, should be called with netif_addr_lock_bh() */
12387 static void bnx2x_set_rx_mode(struct net_device *dev)
12389 struct bnx2x *bp = netdev_priv(dev);
12391 if (bp->state != BNX2X_STATE_OPEN) {
12392 DP(NETIF_MSG_IFUP, "state is %x, returning\n", bp->state);
12395 /* Schedule an SP task to handle rest of change */
12396 bnx2x_schedule_sp_rtnl(bp, BNX2X_SP_RTNL_RX_MODE,
12401 void bnx2x_set_rx_mode_inner(struct bnx2x *bp)
12403 u32 rx_mode = BNX2X_RX_MODE_NORMAL;
12405 DP(NETIF_MSG_IFUP, "dev->flags = %x\n", bp->dev->flags);
12407 netif_addr_lock_bh(bp->dev);
12409 if (bp->dev->flags & IFF_PROMISC) {
12410 rx_mode = BNX2X_RX_MODE_PROMISC;
12411 } else if ((bp->dev->flags & IFF_ALLMULTI) ||
12412 ((netdev_mc_count(bp->dev) > BNX2X_MAX_MULTICAST) &&
12414 rx_mode = BNX2X_RX_MODE_ALLMULTI;
12417 /* some multicasts */
12418 if (bnx2x_set_mc_list(bp) < 0)
12419 rx_mode = BNX2X_RX_MODE_ALLMULTI;
12421 /* release bh lock, as bnx2x_set_uc_list might sleep */
12422 netif_addr_unlock_bh(bp->dev);
12423 if (bnx2x_set_uc_list(bp) < 0)
12424 rx_mode = BNX2X_RX_MODE_PROMISC;
12425 netif_addr_lock_bh(bp->dev);
12427 /* configuring mcast to a vf involves sleeping (when we
12428 * wait for the pf's response).
12430 bnx2x_schedule_sp_rtnl(bp,
12431 BNX2X_SP_RTNL_VFPF_MCAST, 0);
12435 bp->rx_mode = rx_mode;
12436 /* handle ISCSI SD mode */
12437 if (IS_MF_ISCSI_ONLY(bp))
12438 bp->rx_mode = BNX2X_RX_MODE_NONE;
12440 /* Schedule the rx_mode command */
12441 if (test_bit(BNX2X_FILTER_RX_MODE_PENDING, &bp->sp_state)) {
12442 set_bit(BNX2X_FILTER_RX_MODE_SCHED, &bp->sp_state);
12443 netif_addr_unlock_bh(bp->dev);
12448 bnx2x_set_storm_rx_mode(bp);
12449 netif_addr_unlock_bh(bp->dev);
12451 /* VF will need to request the PF to make this change, and so
12452 * the VF needs to release the bottom-half lock prior to the
12453 * request (as it will likely require sleep on the VF side)
12455 netif_addr_unlock_bh(bp->dev);
12456 bnx2x_vfpf_storm_rx_mode(bp);
12460 /* called with rtnl_lock */
12461 static int bnx2x_mdio_read(struct net_device *netdev, int prtad,
12462 int devad, u16 addr)
12464 struct bnx2x *bp = netdev_priv(netdev);
12468 DP(NETIF_MSG_LINK, "mdio_read: prtad 0x%x, devad 0x%x, addr 0x%x\n",
12469 prtad, devad, addr);
12471 /* The HW expects different devad if CL22 is used */
12472 devad = (devad == MDIO_DEVAD_NONE) ? DEFAULT_PHY_DEV_ADDR : devad;
12474 bnx2x_acquire_phy_lock(bp);
12475 rc = bnx2x_phy_read(&bp->link_params, prtad, devad, addr, &value);
12476 bnx2x_release_phy_lock(bp);
12477 DP(NETIF_MSG_LINK, "mdio_read_val 0x%x rc = 0x%x\n", value, rc);
12484 /* called with rtnl_lock */
12485 static int bnx2x_mdio_write(struct net_device *netdev, int prtad, int devad,
12486 u16 addr, u16 value)
12488 struct bnx2x *bp = netdev_priv(netdev);
12492 "mdio_write: prtad 0x%x, devad 0x%x, addr 0x%x, value 0x%x\n",
12493 prtad, devad, addr, value);
12495 /* The HW expects different devad if CL22 is used */
12496 devad = (devad == MDIO_DEVAD_NONE) ? DEFAULT_PHY_DEV_ADDR : devad;
12498 bnx2x_acquire_phy_lock(bp);
12499 rc = bnx2x_phy_write(&bp->link_params, prtad, devad, addr, value);
12500 bnx2x_release_phy_lock(bp);
12504 /* called with rtnl_lock */
12505 static int bnx2x_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
12507 struct bnx2x *bp = netdev_priv(dev);
12508 struct mii_ioctl_data *mdio = if_mii(ifr);
12510 if (!netif_running(dev))
12514 case SIOCSHWTSTAMP:
12515 return bnx2x_hwtstamp_ioctl(bp, ifr);
12517 DP(NETIF_MSG_LINK, "ioctl: phy id 0x%x, reg 0x%x, val_in 0x%x\n",
12518 mdio->phy_id, mdio->reg_num, mdio->val_in);
12519 return mdio_mii_ioctl(&bp->mdio, mdio, cmd);
12523 #ifdef CONFIG_NET_POLL_CONTROLLER
12524 static void poll_bnx2x(struct net_device *dev)
12526 struct bnx2x *bp = netdev_priv(dev);
12529 for_each_eth_queue(bp, i) {
12530 struct bnx2x_fastpath *fp = &bp->fp[i];
12531 napi_schedule(&bnx2x_fp(bp, fp->index, napi));
12536 static int bnx2x_validate_addr(struct net_device *dev)
12538 struct bnx2x *bp = netdev_priv(dev);
12540 /* query the bulletin board for mac address configured by the PF */
12542 bnx2x_sample_bulletin(bp);
12544 if (!is_valid_ether_addr(dev->dev_addr)) {
12545 BNX2X_ERR("Non-valid Ethernet address\n");
12546 return -EADDRNOTAVAIL;
12551 static int bnx2x_get_phys_port_id(struct net_device *netdev,
12552 struct netdev_phys_item_id *ppid)
12554 struct bnx2x *bp = netdev_priv(netdev);
12556 if (!(bp->flags & HAS_PHYS_PORT_ID))
12557 return -EOPNOTSUPP;
12559 ppid->id_len = sizeof(bp->phys_port_id);
12560 memcpy(ppid->id, bp->phys_port_id, ppid->id_len);
12565 static netdev_features_t bnx2x_features_check(struct sk_buff *skb,
12566 struct net_device *dev,
12567 netdev_features_t features)
12569 features = vlan_features_check(skb, features);
12570 return vxlan_features_check(skb, features);
12573 static const struct net_device_ops bnx2x_netdev_ops = {
12574 .ndo_open = bnx2x_open,
12575 .ndo_stop = bnx2x_close,
12576 .ndo_start_xmit = bnx2x_start_xmit,
12577 .ndo_select_queue = bnx2x_select_queue,
12578 .ndo_set_rx_mode = bnx2x_set_rx_mode,
12579 .ndo_set_mac_address = bnx2x_change_mac_addr,
12580 .ndo_validate_addr = bnx2x_validate_addr,
12581 .ndo_do_ioctl = bnx2x_ioctl,
12582 .ndo_change_mtu = bnx2x_change_mtu,
12583 .ndo_fix_features = bnx2x_fix_features,
12584 .ndo_set_features = bnx2x_set_features,
12585 .ndo_tx_timeout = bnx2x_tx_timeout,
12586 #ifdef CONFIG_NET_POLL_CONTROLLER
12587 .ndo_poll_controller = poll_bnx2x,
12589 .ndo_setup_tc = bnx2x_setup_tc,
12590 #ifdef CONFIG_BNX2X_SRIOV
12591 .ndo_set_vf_mac = bnx2x_set_vf_mac,
12592 .ndo_set_vf_vlan = bnx2x_set_vf_vlan,
12593 .ndo_get_vf_config = bnx2x_get_vf_config,
12595 #ifdef NETDEV_FCOE_WWNN
12596 .ndo_fcoe_get_wwn = bnx2x_fcoe_get_wwn,
12599 #ifdef CONFIG_NET_RX_BUSY_POLL
12600 .ndo_busy_poll = bnx2x_low_latency_recv,
12602 .ndo_get_phys_port_id = bnx2x_get_phys_port_id,
12603 .ndo_set_vf_link_state = bnx2x_set_vf_link_state,
12604 .ndo_features_check = bnx2x_features_check,
12607 static int bnx2x_set_coherency_mask(struct bnx2x *bp)
12609 struct device *dev = &bp->pdev->dev;
12611 if (dma_set_mask_and_coherent(dev, DMA_BIT_MASK(64)) != 0 &&
12612 dma_set_mask_and_coherent(dev, DMA_BIT_MASK(32)) != 0) {
12613 dev_err(dev, "System does not support DMA, aborting\n");
12620 static void bnx2x_disable_pcie_error_reporting(struct bnx2x *bp)
12622 if (bp->flags & AER_ENABLED) {
12623 pci_disable_pcie_error_reporting(bp->pdev);
12624 bp->flags &= ~AER_ENABLED;
12628 static int bnx2x_init_dev(struct bnx2x *bp, struct pci_dev *pdev,
12629 struct net_device *dev, unsigned long board_type)
12633 bool chip_is_e1x = (board_type == BCM57710 ||
12634 board_type == BCM57711 ||
12635 board_type == BCM57711E);
12637 SET_NETDEV_DEV(dev, &pdev->dev);
12642 rc = pci_enable_device(pdev);
12644 dev_err(&bp->pdev->dev,
12645 "Cannot enable PCI device, aborting\n");
12649 if (!(pci_resource_flags(pdev, 0) & IORESOURCE_MEM)) {
12650 dev_err(&bp->pdev->dev,
12651 "Cannot find PCI device base address, aborting\n");
12653 goto err_out_disable;
12656 if (IS_PF(bp) && !(pci_resource_flags(pdev, 2) & IORESOURCE_MEM)) {
12657 dev_err(&bp->pdev->dev, "Cannot find second PCI device base address, aborting\n");
12659 goto err_out_disable;
12662 pci_read_config_dword(pdev, PCICFG_REVISION_ID_OFFSET, &pci_cfg_dword);
12663 if ((pci_cfg_dword & PCICFG_REVESION_ID_MASK) ==
12664 PCICFG_REVESION_ID_ERROR_VAL) {
12665 pr_err("PCI device error, probably due to fan failure, aborting\n");
12667 goto err_out_disable;
12670 if (atomic_read(&pdev->enable_cnt) == 1) {
12671 rc = pci_request_regions(pdev, DRV_MODULE_NAME);
12673 dev_err(&bp->pdev->dev,
12674 "Cannot obtain PCI resources, aborting\n");
12675 goto err_out_disable;
12678 pci_set_master(pdev);
12679 pci_save_state(pdev);
12683 if (!pdev->pm_cap) {
12684 dev_err(&bp->pdev->dev,
12685 "Cannot find power management capability, aborting\n");
12687 goto err_out_release;
12691 if (!pci_is_pcie(pdev)) {
12692 dev_err(&bp->pdev->dev, "Not PCI Express, aborting\n");
12694 goto err_out_release;
12697 rc = bnx2x_set_coherency_mask(bp);
12699 goto err_out_release;
12701 dev->mem_start = pci_resource_start(pdev, 0);
12702 dev->base_addr = dev->mem_start;
12703 dev->mem_end = pci_resource_end(pdev, 0);
12705 dev->irq = pdev->irq;
12707 bp->regview = pci_ioremap_bar(pdev, 0);
12708 if (!bp->regview) {
12709 dev_err(&bp->pdev->dev,
12710 "Cannot map register space, aborting\n");
12712 goto err_out_release;
12715 /* In E1/E1H use pci device function given by kernel.
12716 * In E2/E3 read physical function from ME register since these chips
12717 * support Physical Device Assignment where kernel BDF maybe arbitrary
12718 * (depending on hypervisor).
12721 bp->pf_num = PCI_FUNC(pdev->devfn);
12724 pci_read_config_dword(bp->pdev,
12725 PCICFG_ME_REGISTER, &pci_cfg_dword);
12726 bp->pf_num = (u8)((pci_cfg_dword & ME_REG_ABS_PF_NUM) >>
12727 ME_REG_ABS_PF_NUM_SHIFT);
12729 BNX2X_DEV_INFO("me reg PF num: %d\n", bp->pf_num);
12731 /* clean indirect addresses */
12732 pci_write_config_dword(bp->pdev, PCICFG_GRC_ADDRESS,
12733 PCICFG_VENDOR_ID_OFFSET);
12735 /* Set PCIe reset type to fundamental for EEH recovery */
12736 pdev->needs_freset = 1;
12738 /* AER (Advanced Error reporting) configuration */
12739 rc = pci_enable_pcie_error_reporting(pdev);
12741 bp->flags |= AER_ENABLED;
12743 BNX2X_DEV_INFO("Failed To configure PCIe AER [%d]\n", rc);
12746 * Clean the following indirect addresses for all functions since it
12747 * is not used by the driver.
12750 REG_WR(bp, PXP2_REG_PGL_ADDR_88_F0, 0);
12751 REG_WR(bp, PXP2_REG_PGL_ADDR_8C_F0, 0);
12752 REG_WR(bp, PXP2_REG_PGL_ADDR_90_F0, 0);
12753 REG_WR(bp, PXP2_REG_PGL_ADDR_94_F0, 0);
12756 REG_WR(bp, PXP2_REG_PGL_ADDR_88_F1, 0);
12757 REG_WR(bp, PXP2_REG_PGL_ADDR_8C_F1, 0);
12758 REG_WR(bp, PXP2_REG_PGL_ADDR_90_F1, 0);
12759 REG_WR(bp, PXP2_REG_PGL_ADDR_94_F1, 0);
12762 /* Enable internal target-read (in case we are probed after PF
12763 * FLR). Must be done prior to any BAR read access. Only for
12768 PGLUE_B_REG_INTERNAL_PFID_ENABLE_TARGET_READ, 1);
12771 dev->watchdog_timeo = TX_TIMEOUT;
12773 dev->netdev_ops = &bnx2x_netdev_ops;
12774 bnx2x_set_ethtool_ops(bp, dev);
12776 dev->priv_flags |= IFF_UNICAST_FLT;
12778 dev->hw_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM |
12779 NETIF_F_TSO | NETIF_F_TSO_ECN | NETIF_F_TSO6 |
12780 NETIF_F_RXCSUM | NETIF_F_LRO | NETIF_F_GRO |
12781 NETIF_F_RXHASH | NETIF_F_HW_VLAN_CTAG_TX;
12782 if (!chip_is_e1x) {
12783 dev->hw_features |= NETIF_F_GSO_GRE | NETIF_F_GSO_UDP_TUNNEL |
12784 NETIF_F_GSO_IPIP | NETIF_F_GSO_SIT;
12785 dev->hw_enc_features =
12786 NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM | NETIF_F_SG |
12787 NETIF_F_TSO | NETIF_F_TSO_ECN | NETIF_F_TSO6 |
12790 NETIF_F_GSO_GRE | NETIF_F_GSO_UDP_TUNNEL;
12793 dev->vlan_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM |
12794 NETIF_F_TSO | NETIF_F_TSO_ECN | NETIF_F_TSO6 | NETIF_F_HIGHDMA;
12796 dev->features |= dev->hw_features | NETIF_F_HW_VLAN_CTAG_RX;
12797 dev->features |= NETIF_F_HIGHDMA;
12799 /* Add Loopback capability to the device */
12800 dev->hw_features |= NETIF_F_LOOPBACK;
12803 dev->dcbnl_ops = &bnx2x_dcbnl_ops;
12806 /* get_port_hwinfo() will set prtad and mmds properly */
12807 bp->mdio.prtad = MDIO_PRTAD_NONE;
12809 bp->mdio.mode_support = MDIO_SUPPORTS_C45 | MDIO_EMULATE_C22;
12810 bp->mdio.dev = dev;
12811 bp->mdio.mdio_read = bnx2x_mdio_read;
12812 bp->mdio.mdio_write = bnx2x_mdio_write;
12817 if (atomic_read(&pdev->enable_cnt) == 1)
12818 pci_release_regions(pdev);
12821 pci_disable_device(pdev);
12827 static int bnx2x_check_firmware(struct bnx2x *bp)
12829 const struct firmware *firmware = bp->firmware;
12830 struct bnx2x_fw_file_hdr *fw_hdr;
12831 struct bnx2x_fw_file_section *sections;
12832 u32 offset, len, num_ops;
12833 __be16 *ops_offsets;
12837 if (firmware->size < sizeof(struct bnx2x_fw_file_hdr)) {
12838 BNX2X_ERR("Wrong FW size\n");
12842 fw_hdr = (struct bnx2x_fw_file_hdr *)firmware->data;
12843 sections = (struct bnx2x_fw_file_section *)fw_hdr;
12845 /* Make sure none of the offsets and sizes make us read beyond
12846 * the end of the firmware data */
12847 for (i = 0; i < sizeof(*fw_hdr) / sizeof(*sections); i++) {
12848 offset = be32_to_cpu(sections[i].offset);
12849 len = be32_to_cpu(sections[i].len);
12850 if (offset + len > firmware->size) {
12851 BNX2X_ERR("Section %d length is out of bounds\n", i);
12856 /* Likewise for the init_ops offsets */
12857 offset = be32_to_cpu(fw_hdr->init_ops_offsets.offset);
12858 ops_offsets = (__force __be16 *)(firmware->data + offset);
12859 num_ops = be32_to_cpu(fw_hdr->init_ops.len) / sizeof(struct raw_op);
12861 for (i = 0; i < be32_to_cpu(fw_hdr->init_ops_offsets.len) / 2; i++) {
12862 if (be16_to_cpu(ops_offsets[i]) > num_ops) {
12863 BNX2X_ERR("Section offset %d is out of bounds\n", i);
12868 /* Check FW version */
12869 offset = be32_to_cpu(fw_hdr->fw_version.offset);
12870 fw_ver = firmware->data + offset;
12871 if ((fw_ver[0] != BCM_5710_FW_MAJOR_VERSION) ||
12872 (fw_ver[1] != BCM_5710_FW_MINOR_VERSION) ||
12873 (fw_ver[2] != BCM_5710_FW_REVISION_VERSION) ||
12874 (fw_ver[3] != BCM_5710_FW_ENGINEERING_VERSION)) {
12875 BNX2X_ERR("Bad FW version:%d.%d.%d.%d. Should be %d.%d.%d.%d\n",
12876 fw_ver[0], fw_ver[1], fw_ver[2], fw_ver[3],
12877 BCM_5710_FW_MAJOR_VERSION,
12878 BCM_5710_FW_MINOR_VERSION,
12879 BCM_5710_FW_REVISION_VERSION,
12880 BCM_5710_FW_ENGINEERING_VERSION);
12887 static void be32_to_cpu_n(const u8 *_source, u8 *_target, u32 n)
12889 const __be32 *source = (const __be32 *)_source;
12890 u32 *target = (u32 *)_target;
12893 for (i = 0; i < n/4; i++)
12894 target[i] = be32_to_cpu(source[i]);
12898 Ops array is stored in the following format:
12899 {op(8bit), offset(24bit, big endian), data(32bit, big endian)}
12901 static void bnx2x_prep_ops(const u8 *_source, u8 *_target, u32 n)
12903 const __be32 *source = (const __be32 *)_source;
12904 struct raw_op *target = (struct raw_op *)_target;
12907 for (i = 0, j = 0; i < n/8; i++, j += 2) {
12908 tmp = be32_to_cpu(source[j]);
12909 target[i].op = (tmp >> 24) & 0xff;
12910 target[i].offset = tmp & 0xffffff;
12911 target[i].raw_data = be32_to_cpu(source[j + 1]);
12915 /* IRO array is stored in the following format:
12916 * {base(24bit), m1(16bit), m2(16bit), m3(16bit), size(16bit) }
12918 static void bnx2x_prep_iro(const u8 *_source, u8 *_target, u32 n)
12920 const __be32 *source = (const __be32 *)_source;
12921 struct iro *target = (struct iro *)_target;
12924 for (i = 0, j = 0; i < n/sizeof(struct iro); i++) {
12925 target[i].base = be32_to_cpu(source[j]);
12927 tmp = be32_to_cpu(source[j]);
12928 target[i].m1 = (tmp >> 16) & 0xffff;
12929 target[i].m2 = tmp & 0xffff;
12931 tmp = be32_to_cpu(source[j]);
12932 target[i].m3 = (tmp >> 16) & 0xffff;
12933 target[i].size = tmp & 0xffff;
12938 static void be16_to_cpu_n(const u8 *_source, u8 *_target, u32 n)
12940 const __be16 *source = (const __be16 *)_source;
12941 u16 *target = (u16 *)_target;
12944 for (i = 0; i < n/2; i++)
12945 target[i] = be16_to_cpu(source[i]);
12948 #define BNX2X_ALLOC_AND_SET(arr, lbl, func) \
12950 u32 len = be32_to_cpu(fw_hdr->arr.len); \
12951 bp->arr = kmalloc(len, GFP_KERNEL); \
12954 func(bp->firmware->data + be32_to_cpu(fw_hdr->arr.offset), \
12955 (u8 *)bp->arr, len); \
12958 static int bnx2x_init_firmware(struct bnx2x *bp)
12960 const char *fw_file_name;
12961 struct bnx2x_fw_file_hdr *fw_hdr;
12967 if (CHIP_IS_E1(bp))
12968 fw_file_name = FW_FILE_NAME_E1;
12969 else if (CHIP_IS_E1H(bp))
12970 fw_file_name = FW_FILE_NAME_E1H;
12971 else if (!CHIP_IS_E1x(bp))
12972 fw_file_name = FW_FILE_NAME_E2;
12974 BNX2X_ERR("Unsupported chip revision\n");
12977 BNX2X_DEV_INFO("Loading %s\n", fw_file_name);
12979 rc = request_firmware(&bp->firmware, fw_file_name, &bp->pdev->dev);
12981 BNX2X_ERR("Can't load firmware file %s\n",
12983 goto request_firmware_exit;
12986 rc = bnx2x_check_firmware(bp);
12988 BNX2X_ERR("Corrupt firmware file %s\n", fw_file_name);
12989 goto request_firmware_exit;
12992 fw_hdr = (struct bnx2x_fw_file_hdr *)bp->firmware->data;
12994 /* Initialize the pointers to the init arrays */
12996 BNX2X_ALLOC_AND_SET(init_data, request_firmware_exit, be32_to_cpu_n);
12999 BNX2X_ALLOC_AND_SET(init_ops, init_ops_alloc_err, bnx2x_prep_ops);
13002 BNX2X_ALLOC_AND_SET(init_ops_offsets, init_offsets_alloc_err,
13005 /* STORMs firmware */
13006 INIT_TSEM_INT_TABLE_DATA(bp) = bp->firmware->data +
13007 be32_to_cpu(fw_hdr->tsem_int_table_data.offset);
13008 INIT_TSEM_PRAM_DATA(bp) = bp->firmware->data +
13009 be32_to_cpu(fw_hdr->tsem_pram_data.offset);
13010 INIT_USEM_INT_TABLE_DATA(bp) = bp->firmware->data +
13011 be32_to_cpu(fw_hdr->usem_int_table_data.offset);
13012 INIT_USEM_PRAM_DATA(bp) = bp->firmware->data +
13013 be32_to_cpu(fw_hdr->usem_pram_data.offset);
13014 INIT_XSEM_INT_TABLE_DATA(bp) = bp->firmware->data +
13015 be32_to_cpu(fw_hdr->xsem_int_table_data.offset);
13016 INIT_XSEM_PRAM_DATA(bp) = bp->firmware->data +
13017 be32_to_cpu(fw_hdr->xsem_pram_data.offset);
13018 INIT_CSEM_INT_TABLE_DATA(bp) = bp->firmware->data +
13019 be32_to_cpu(fw_hdr->csem_int_table_data.offset);
13020 INIT_CSEM_PRAM_DATA(bp) = bp->firmware->data +
13021 be32_to_cpu(fw_hdr->csem_pram_data.offset);
13023 BNX2X_ALLOC_AND_SET(iro_arr, iro_alloc_err, bnx2x_prep_iro);
13028 kfree(bp->init_ops_offsets);
13029 init_offsets_alloc_err:
13030 kfree(bp->init_ops);
13031 init_ops_alloc_err:
13032 kfree(bp->init_data);
13033 request_firmware_exit:
13034 release_firmware(bp->firmware);
13035 bp->firmware = NULL;
13040 static void bnx2x_release_firmware(struct bnx2x *bp)
13042 kfree(bp->init_ops_offsets);
13043 kfree(bp->init_ops);
13044 kfree(bp->init_data);
13045 release_firmware(bp->firmware);
13046 bp->firmware = NULL;
13049 static struct bnx2x_func_sp_drv_ops bnx2x_func_sp_drv = {
13050 .init_hw_cmn_chip = bnx2x_init_hw_common_chip,
13051 .init_hw_cmn = bnx2x_init_hw_common,
13052 .init_hw_port = bnx2x_init_hw_port,
13053 .init_hw_func = bnx2x_init_hw_func,
13055 .reset_hw_cmn = bnx2x_reset_common,
13056 .reset_hw_port = bnx2x_reset_port,
13057 .reset_hw_func = bnx2x_reset_func,
13059 .gunzip_init = bnx2x_gunzip_init,
13060 .gunzip_end = bnx2x_gunzip_end,
13062 .init_fw = bnx2x_init_firmware,
13063 .release_fw = bnx2x_release_firmware,
13066 void bnx2x__init_func_obj(struct bnx2x *bp)
13068 /* Prepare DMAE related driver resources */
13069 bnx2x_setup_dmae(bp);
13071 bnx2x_init_func_obj(bp, &bp->func_obj,
13072 bnx2x_sp(bp, func_rdata),
13073 bnx2x_sp_mapping(bp, func_rdata),
13074 bnx2x_sp(bp, func_afex_rdata),
13075 bnx2x_sp_mapping(bp, func_afex_rdata),
13076 &bnx2x_func_sp_drv);
13079 /* must be called after sriov-enable */
13080 static int bnx2x_set_qm_cid_count(struct bnx2x *bp)
13082 int cid_count = BNX2X_L2_MAX_CID(bp);
13085 cid_count += BNX2X_VF_CIDS;
13087 if (CNIC_SUPPORT(bp))
13088 cid_count += CNIC_CID_MAX;
13090 return roundup(cid_count, QM_CID_ROUND);
13094 * bnx2x_get_num_none_def_sbs - return the number of none default SBs
13099 static int bnx2x_get_num_non_def_sbs(struct pci_dev *pdev, int cnic_cnt)
13105 * If MSI-X is not supported - return number of SBs needed to support
13106 * one fast path queue: one FP queue + SB for CNIC
13108 if (!pdev->msix_cap) {
13109 dev_info(&pdev->dev, "no msix capability found\n");
13110 return 1 + cnic_cnt;
13112 dev_info(&pdev->dev, "msix capability found\n");
13115 * The value in the PCI configuration space is the index of the last
13116 * entry, namely one less than the actual size of the table, which is
13117 * exactly what we want to return from this function: number of all SBs
13118 * without the default SB.
13119 * For VFs there is no default SB, then we return (index+1).
13121 pci_read_config_word(pdev, pdev->msix_cap + PCI_MSIX_FLAGS, &control);
13123 index = control & PCI_MSIX_FLAGS_QSIZE;
13128 static int set_max_cos_est(int chip_id)
13134 return BNX2X_MULTI_TX_COS_E1X;
13137 return BNX2X_MULTI_TX_COS_E2_E3A0;
13142 case BCM57840_4_10:
13143 case BCM57840_2_20:
13149 return BNX2X_MULTI_TX_COS_E3B0;
13157 pr_err("Unknown board_type (%d), aborting\n", chip_id);
13162 static int set_is_vf(int chip_id)
13176 /* nig_tsgen registers relative address */
13177 #define tsgen_ctrl 0x0
13178 #define tsgen_freecount 0x10
13179 #define tsgen_synctime_t0 0x20
13180 #define tsgen_offset_t0 0x28
13181 #define tsgen_drift_t0 0x30
13182 #define tsgen_synctime_t1 0x58
13183 #define tsgen_offset_t1 0x60
13184 #define tsgen_drift_t1 0x68
13186 /* FW workaround for setting drift */
13187 static int bnx2x_send_update_drift_ramrod(struct bnx2x *bp, int drift_dir,
13188 int best_val, int best_period)
13190 struct bnx2x_func_state_params func_params = {NULL};
13191 struct bnx2x_func_set_timesync_params *set_timesync_params =
13192 &func_params.params.set_timesync;
13194 /* Prepare parameters for function state transitions */
13195 __set_bit(RAMROD_COMP_WAIT, &func_params.ramrod_flags);
13196 __set_bit(RAMROD_RETRY, &func_params.ramrod_flags);
13198 func_params.f_obj = &bp->func_obj;
13199 func_params.cmd = BNX2X_F_CMD_SET_TIMESYNC;
13201 /* Function parameters */
13202 set_timesync_params->drift_adjust_cmd = TS_DRIFT_ADJUST_SET;
13203 set_timesync_params->offset_cmd = TS_OFFSET_KEEP;
13204 set_timesync_params->add_sub_drift_adjust_value =
13205 drift_dir ? TS_ADD_VALUE : TS_SUB_VALUE;
13206 set_timesync_params->drift_adjust_value = best_val;
13207 set_timesync_params->drift_adjust_period = best_period;
13209 return bnx2x_func_state_change(bp, &func_params);
13212 static int bnx2x_ptp_adjfreq(struct ptp_clock_info *ptp, s32 ppb)
13214 struct bnx2x *bp = container_of(ptp, struct bnx2x, ptp_clock_info);
13217 int val, period, period1, period2, dif, dif1, dif2;
13218 int best_dif = BNX2X_MAX_PHC_DRIFT, best_period = 0, best_val = 0;
13220 DP(BNX2X_MSG_PTP, "PTP adjfreq called, ppb = %d\n", ppb);
13222 if (!netif_running(bp->dev)) {
13224 "PTP adjfreq called while the interface is down\n");
13235 best_period = 0x1FFFFFF;
13236 } else if (ppb >= BNX2X_MAX_PHC_DRIFT) {
13240 /* Changed not to allow val = 8, 16, 24 as these values
13241 * are not supported in workaround.
13243 for (val = 0; val <= 31; val++) {
13244 if ((val & 0x7) == 0)
13246 period1 = val * 1000000 / ppb;
13247 period2 = period1 + 1;
13249 dif1 = ppb - (val * 1000000 / period1);
13251 dif1 = BNX2X_MAX_PHC_DRIFT;
13254 dif2 = ppb - (val * 1000000 / period2);
13257 dif = (dif1 < dif2) ? dif1 : dif2;
13258 period = (dif1 < dif2) ? period1 : period2;
13259 if (dif < best_dif) {
13262 best_period = period;
13267 rc = bnx2x_send_update_drift_ramrod(bp, drift_dir, best_val,
13270 BNX2X_ERR("Failed to set drift\n");
13274 DP(BNX2X_MSG_PTP, "Configured val = %d, period = %d\n", best_val,
13280 static int bnx2x_ptp_adjtime(struct ptp_clock_info *ptp, s64 delta)
13282 struct bnx2x *bp = container_of(ptp, struct bnx2x, ptp_clock_info);
13284 DP(BNX2X_MSG_PTP, "PTP adjtime called, delta = %llx\n", delta);
13286 timecounter_adjtime(&bp->timecounter, delta);
13291 static int bnx2x_ptp_gettime(struct ptp_clock_info *ptp, struct timespec64 *ts)
13293 struct bnx2x *bp = container_of(ptp, struct bnx2x, ptp_clock_info);
13296 ns = timecounter_read(&bp->timecounter);
13298 DP(BNX2X_MSG_PTP, "PTP gettime called, ns = %llu\n", ns);
13300 *ts = ns_to_timespec64(ns);
13305 static int bnx2x_ptp_settime(struct ptp_clock_info *ptp,
13306 const struct timespec64 *ts)
13308 struct bnx2x *bp = container_of(ptp, struct bnx2x, ptp_clock_info);
13311 ns = timespec64_to_ns(ts);
13313 DP(BNX2X_MSG_PTP, "PTP settime called, ns = %llu\n", ns);
13315 /* Re-init the timecounter */
13316 timecounter_init(&bp->timecounter, &bp->cyclecounter, ns);
13321 /* Enable (or disable) ancillary features of the phc subsystem */
13322 static int bnx2x_ptp_enable(struct ptp_clock_info *ptp,
13323 struct ptp_clock_request *rq, int on)
13325 struct bnx2x *bp = container_of(ptp, struct bnx2x, ptp_clock_info);
13327 BNX2X_ERR("PHC ancillary features are not supported\n");
13331 static void bnx2x_register_phc(struct bnx2x *bp)
13333 /* Fill the ptp_clock_info struct and register PTP clock*/
13334 bp->ptp_clock_info.owner = THIS_MODULE;
13335 snprintf(bp->ptp_clock_info.name, 16, "%s", bp->dev->name);
13336 bp->ptp_clock_info.max_adj = BNX2X_MAX_PHC_DRIFT; /* In PPB */
13337 bp->ptp_clock_info.n_alarm = 0;
13338 bp->ptp_clock_info.n_ext_ts = 0;
13339 bp->ptp_clock_info.n_per_out = 0;
13340 bp->ptp_clock_info.pps = 0;
13341 bp->ptp_clock_info.adjfreq = bnx2x_ptp_adjfreq;
13342 bp->ptp_clock_info.adjtime = bnx2x_ptp_adjtime;
13343 bp->ptp_clock_info.gettime64 = bnx2x_ptp_gettime;
13344 bp->ptp_clock_info.settime64 = bnx2x_ptp_settime;
13345 bp->ptp_clock_info.enable = bnx2x_ptp_enable;
13347 bp->ptp_clock = ptp_clock_register(&bp->ptp_clock_info, &bp->pdev->dev);
13348 if (IS_ERR(bp->ptp_clock)) {
13349 bp->ptp_clock = NULL;
13350 BNX2X_ERR("PTP clock registeration failed\n");
13354 static int bnx2x_init_one(struct pci_dev *pdev,
13355 const struct pci_device_id *ent)
13357 struct net_device *dev = NULL;
13359 enum pcie_link_width pcie_width;
13360 enum pci_bus_speed pcie_speed;
13361 int rc, max_non_def_sbs;
13362 int rx_count, tx_count, rss_count, doorbell_size;
13367 /* Management FW 'remembers' living interfaces. Allow it some time
13368 * to forget previously living interfaces, allowing a proper re-load.
13370 if (is_kdump_kernel()) {
13371 ktime_t now = ktime_get_boottime();
13372 ktime_t fw_ready_time = ktime_set(5, 0);
13374 if (ktime_before(now, fw_ready_time))
13375 msleep(ktime_ms_delta(fw_ready_time, now));
13378 /* An estimated maximum supported CoS number according to the chip
13380 * We will try to roughly estimate the maximum number of CoSes this chip
13381 * may support in order to minimize the memory allocated for Tx
13382 * netdev_queue's. This number will be accurately calculated during the
13383 * initialization of bp->max_cos based on the chip versions AND chip
13384 * revision in the bnx2x_init_bp().
13386 max_cos_est = set_max_cos_est(ent->driver_data);
13387 if (max_cos_est < 0)
13388 return max_cos_est;
13389 is_vf = set_is_vf(ent->driver_data);
13390 cnic_cnt = is_vf ? 0 : 1;
13392 max_non_def_sbs = bnx2x_get_num_non_def_sbs(pdev, cnic_cnt);
13394 /* add another SB for VF as it has no default SB */
13395 max_non_def_sbs += is_vf ? 1 : 0;
13397 /* Maximum number of RSS queues: one IGU SB goes to CNIC */
13398 rss_count = max_non_def_sbs - cnic_cnt;
13403 /* Maximum number of netdev Rx queues: RSS + FCoE L2 */
13404 rx_count = rss_count + cnic_cnt;
13406 /* Maximum number of netdev Tx queues:
13407 * Maximum TSS queues * Maximum supported number of CoS + FCoE L2
13409 tx_count = rss_count * max_cos_est + cnic_cnt;
13411 /* dev zeroed in init_etherdev */
13412 dev = alloc_etherdev_mqs(sizeof(*bp), tx_count, rx_count);
13416 bp = netdev_priv(dev);
13420 bp->flags |= IS_VF_FLAG;
13422 bp->igu_sb_cnt = max_non_def_sbs;
13423 bp->igu_base_addr = IS_VF(bp) ? PXP_VF_ADDR_IGU_START : BAR_IGU_INTMEM;
13424 bp->msg_enable = debug;
13425 bp->cnic_support = cnic_cnt;
13426 bp->cnic_probe = bnx2x_cnic_probe;
13428 pci_set_drvdata(pdev, dev);
13430 rc = bnx2x_init_dev(bp, pdev, dev, ent->driver_data);
13436 BNX2X_DEV_INFO("This is a %s function\n",
13437 IS_PF(bp) ? "physical" : "virtual");
13438 BNX2X_DEV_INFO("Cnic support is %s\n", CNIC_SUPPORT(bp) ? "on" : "off");
13439 BNX2X_DEV_INFO("Max num of status blocks %d\n", max_non_def_sbs);
13440 BNX2X_DEV_INFO("Allocated netdev with %d tx and %d rx queues\n",
13441 tx_count, rx_count);
13443 rc = bnx2x_init_bp(bp);
13445 goto init_one_exit;
13447 /* Map doorbells here as we need the real value of bp->max_cos which
13448 * is initialized in bnx2x_init_bp() to determine the number of
13452 bp->doorbells = bnx2x_vf_doorbells(bp);
13453 rc = bnx2x_vf_pci_alloc(bp);
13455 goto init_one_exit;
13457 doorbell_size = BNX2X_L2_MAX_CID(bp) * (1 << BNX2X_DB_SHIFT);
13458 if (doorbell_size > pci_resource_len(pdev, 2)) {
13459 dev_err(&bp->pdev->dev,
13460 "Cannot map doorbells, bar size too small, aborting\n");
13462 goto init_one_exit;
13464 bp->doorbells = ioremap_nocache(pci_resource_start(pdev, 2),
13467 if (!bp->doorbells) {
13468 dev_err(&bp->pdev->dev,
13469 "Cannot map doorbell space, aborting\n");
13471 goto init_one_exit;
13475 rc = bnx2x_vfpf_acquire(bp, tx_count, rx_count);
13477 goto init_one_exit;
13480 /* Enable SRIOV if capability found in configuration space */
13481 rc = bnx2x_iov_init_one(bp, int_mode, BNX2X_MAX_NUM_OF_VFS);
13483 goto init_one_exit;
13485 /* calc qm_cid_count */
13486 bp->qm_cid_count = bnx2x_set_qm_cid_count(bp);
13487 BNX2X_DEV_INFO("qm_cid_count %d\n", bp->qm_cid_count);
13489 /* disable FCOE L2 queue for E1x*/
13490 if (CHIP_IS_E1x(bp))
13491 bp->flags |= NO_FCOE_FLAG;
13493 /* Set bp->num_queues for MSI-X mode*/
13494 bnx2x_set_num_queues(bp);
13496 /* Configure interrupt mode: try to enable MSI-X/MSI if
13499 rc = bnx2x_set_int_mode(bp);
13501 dev_err(&pdev->dev, "Cannot set interrupts\n");
13502 goto init_one_exit;
13504 BNX2X_DEV_INFO("set interrupts successfully\n");
13506 /* register the net device */
13507 rc = register_netdev(dev);
13509 dev_err(&pdev->dev, "Cannot register net device\n");
13510 goto init_one_exit;
13512 BNX2X_DEV_INFO("device name after netdev register %s\n", dev->name);
13514 if (!NO_FCOE(bp)) {
13515 /* Add storage MAC address */
13517 dev_addr_add(bp->dev, bp->fip_mac, NETDEV_HW_ADDR_T_SAN);
13520 if (pcie_get_minimum_link(bp->pdev, &pcie_speed, &pcie_width) ||
13521 pcie_speed == PCI_SPEED_UNKNOWN ||
13522 pcie_width == PCIE_LNK_WIDTH_UNKNOWN)
13523 BNX2X_DEV_INFO("Failed to determine PCI Express Bandwidth\n");
13526 "%s (%c%d) PCI-E x%d %s found at mem %lx, IRQ %d, node addr %pM\n",
13527 board_info[ent->driver_data].name,
13528 (CHIP_REV(bp) >> 12) + 'A', (CHIP_METAL(bp) >> 4),
13530 pcie_speed == PCIE_SPEED_2_5GT ? "2.5GHz" :
13531 pcie_speed == PCIE_SPEED_5_0GT ? "5.0GHz" :
13532 pcie_speed == PCIE_SPEED_8_0GT ? "8.0GHz" :
13534 dev->base_addr, bp->pdev->irq, dev->dev_addr);
13536 bnx2x_register_phc(bp);
13541 bnx2x_disable_pcie_error_reporting(bp);
13544 iounmap(bp->regview);
13546 if (IS_PF(bp) && bp->doorbells)
13547 iounmap(bp->doorbells);
13551 if (atomic_read(&pdev->enable_cnt) == 1)
13552 pci_release_regions(pdev);
13554 pci_disable_device(pdev);
13559 static void __bnx2x_remove(struct pci_dev *pdev,
13560 struct net_device *dev,
13562 bool remove_netdev)
13564 if (bp->ptp_clock) {
13565 ptp_clock_unregister(bp->ptp_clock);
13566 bp->ptp_clock = NULL;
13569 /* Delete storage MAC address */
13570 if (!NO_FCOE(bp)) {
13572 dev_addr_del(bp->dev, bp->fip_mac, NETDEV_HW_ADDR_T_SAN);
13577 /* Delete app tlvs from dcbnl */
13578 bnx2x_dcbnl_update_applist(bp, true);
13583 (bp->flags & BC_SUPPORTS_RMMOD_CMD))
13584 bnx2x_fw_command(bp, DRV_MSG_CODE_RMMOD, 0);
13586 /* Close the interface - either directly or implicitly */
13587 if (remove_netdev) {
13588 unregister_netdev(dev);
13595 bnx2x_iov_remove_one(bp);
13597 /* Power on: we can't let PCI layer write to us while we are in D3 */
13599 bnx2x_set_power_state(bp, PCI_D0);
13601 /* Set endianity registers to reset values in case next driver
13602 * boots in different endianty environment.
13604 bnx2x_reset_endianity(bp);
13607 /* Disable MSI/MSI-X */
13608 bnx2x_disable_msi(bp);
13612 bnx2x_set_power_state(bp, PCI_D3hot);
13614 /* Make sure RESET task is not scheduled before continuing */
13615 cancel_delayed_work_sync(&bp->sp_rtnl_task);
13617 /* send message via vfpf channel to release the resources of this vf */
13619 bnx2x_vfpf_release(bp);
13621 /* Assumes no further PCIe PM changes will occur */
13622 if (system_state == SYSTEM_POWER_OFF) {
13623 pci_wake_from_d3(pdev, bp->wol);
13624 pci_set_power_state(pdev, PCI_D3hot);
13627 bnx2x_disable_pcie_error_reporting(bp);
13628 if (remove_netdev) {
13630 iounmap(bp->regview);
13632 /* For vfs, doorbells are part of the regview and were unmapped
13633 * along with it. FW is only loaded by PF.
13637 iounmap(bp->doorbells);
13639 bnx2x_release_firmware(bp);
13641 bnx2x_vf_pci_dealloc(bp);
13643 bnx2x_free_mem_bp(bp);
13647 if (atomic_read(&pdev->enable_cnt) == 1)
13648 pci_release_regions(pdev);
13650 pci_disable_device(pdev);
13654 static void bnx2x_remove_one(struct pci_dev *pdev)
13656 struct net_device *dev = pci_get_drvdata(pdev);
13660 dev_err(&pdev->dev, "BAD net device from bnx2x_init_one\n");
13663 bp = netdev_priv(dev);
13665 __bnx2x_remove(pdev, dev, bp, true);
13668 static int bnx2x_eeh_nic_unload(struct bnx2x *bp)
13670 bp->state = BNX2X_STATE_CLOSING_WAIT4_HALT;
13672 bp->rx_mode = BNX2X_RX_MODE_NONE;
13674 if (CNIC_LOADED(bp))
13675 bnx2x_cnic_notify(bp, CNIC_CTL_STOP_CMD);
13678 bnx2x_tx_disable(bp);
13679 /* Delete all NAPI objects */
13680 bnx2x_del_all_napi(bp);
13681 if (CNIC_LOADED(bp))
13682 bnx2x_del_all_napi_cnic(bp);
13683 netdev_reset_tc(bp->dev);
13685 del_timer_sync(&bp->timer);
13686 cancel_delayed_work_sync(&bp->sp_task);
13687 cancel_delayed_work_sync(&bp->period_task);
13689 if (!down_timeout(&bp->stats_lock, HZ / 10)) {
13690 bp->stats_state = STATS_STATE_DISABLED;
13691 up(&bp->stats_lock);
13694 bnx2x_save_statistics(bp);
13696 netif_carrier_off(bp->dev);
13702 * bnx2x_io_error_detected - called when PCI error is detected
13703 * @pdev: Pointer to PCI device
13704 * @state: The current pci connection state
13706 * This function is called after a PCI bus error affecting
13707 * this device has been detected.
13709 static pci_ers_result_t bnx2x_io_error_detected(struct pci_dev *pdev,
13710 pci_channel_state_t state)
13712 struct net_device *dev = pci_get_drvdata(pdev);
13713 struct bnx2x *bp = netdev_priv(dev);
13717 BNX2X_ERR("IO error detected\n");
13719 netif_device_detach(dev);
13721 if (state == pci_channel_io_perm_failure) {
13723 return PCI_ERS_RESULT_DISCONNECT;
13726 if (netif_running(dev))
13727 bnx2x_eeh_nic_unload(bp);
13729 bnx2x_prev_path_mark_eeh(bp);
13731 pci_disable_device(pdev);
13735 /* Request a slot reset */
13736 return PCI_ERS_RESULT_NEED_RESET;
13740 * bnx2x_io_slot_reset - called after the PCI bus has been reset
13741 * @pdev: Pointer to PCI device
13743 * Restart the card from scratch, as if from a cold-boot.
13745 static pci_ers_result_t bnx2x_io_slot_reset(struct pci_dev *pdev)
13747 struct net_device *dev = pci_get_drvdata(pdev);
13748 struct bnx2x *bp = netdev_priv(dev);
13752 BNX2X_ERR("IO slot reset initializing...\n");
13753 if (pci_enable_device(pdev)) {
13754 dev_err(&pdev->dev,
13755 "Cannot re-enable PCI device after reset\n");
13757 return PCI_ERS_RESULT_DISCONNECT;
13760 pci_set_master(pdev);
13761 pci_restore_state(pdev);
13762 pci_save_state(pdev);
13764 if (netif_running(dev))
13765 bnx2x_set_power_state(bp, PCI_D0);
13767 if (netif_running(dev)) {
13768 BNX2X_ERR("IO slot reset --> driver unload\n");
13770 /* MCP should have been reset; Need to wait for validity */
13771 bnx2x_init_shmem(bp);
13773 if (IS_PF(bp) && SHMEM2_HAS(bp, drv_capabilities_flag)) {
13777 drv_capabilities_flag[BP_FW_MB_IDX(bp)]);
13778 SHMEM2_WR(bp, drv_capabilities_flag[BP_FW_MB_IDX(bp)],
13779 v & ~DRV_FLAGS_CAPABILITIES_LOADED_L2);
13781 bnx2x_drain_tx_queues(bp);
13782 bnx2x_send_unload_req(bp, UNLOAD_RECOVERY);
13783 bnx2x_netif_stop(bp, 1);
13784 bnx2x_free_irq(bp);
13786 /* Report UNLOAD_DONE to MCP */
13787 bnx2x_send_unload_done(bp, true);
13792 bnx2x_prev_unload(bp);
13794 /* We should have reseted the engine, so It's fair to
13795 * assume the FW will no longer write to the bnx2x driver.
13797 bnx2x_squeeze_objects(bp);
13798 bnx2x_free_skbs(bp);
13799 for_each_rx_queue(bp, i)
13800 bnx2x_free_rx_sge_range(bp, bp->fp + i, NUM_RX_SGE);
13801 bnx2x_free_fp_mem(bp);
13802 bnx2x_free_mem(bp);
13804 bp->state = BNX2X_STATE_CLOSED;
13809 /* If AER, perform cleanup of the PCIe registers */
13810 if (bp->flags & AER_ENABLED) {
13811 if (pci_cleanup_aer_uncorrect_error_status(pdev))
13812 BNX2X_ERR("pci_cleanup_aer_uncorrect_error_status failed\n");
13814 DP(NETIF_MSG_HW, "pci_cleanup_aer_uncorrect_error_status succeeded\n");
13817 return PCI_ERS_RESULT_RECOVERED;
13821 * bnx2x_io_resume - called when traffic can start flowing again
13822 * @pdev: Pointer to PCI device
13824 * This callback is called when the error recovery driver tells us that
13825 * its OK to resume normal operation.
13827 static void bnx2x_io_resume(struct pci_dev *pdev)
13829 struct net_device *dev = pci_get_drvdata(pdev);
13830 struct bnx2x *bp = netdev_priv(dev);
13832 if (bp->recovery_state != BNX2X_RECOVERY_DONE) {
13833 netdev_err(bp->dev, "Handling parity error recovery. Try again later\n");
13839 bp->fw_seq = SHMEM_RD(bp, func_mb[BP_FW_MB_IDX(bp)].drv_mb_header) &
13840 DRV_MSG_SEQ_NUMBER_MASK;
13842 if (netif_running(dev))
13843 bnx2x_nic_load(bp, LOAD_NORMAL);
13845 netif_device_attach(dev);
13850 static const struct pci_error_handlers bnx2x_err_handler = {
13851 .error_detected = bnx2x_io_error_detected,
13852 .slot_reset = bnx2x_io_slot_reset,
13853 .resume = bnx2x_io_resume,
13856 static void bnx2x_shutdown(struct pci_dev *pdev)
13858 struct net_device *dev = pci_get_drvdata(pdev);
13864 bp = netdev_priv(dev);
13869 netif_device_detach(dev);
13872 /* Don't remove the netdevice, as there are scenarios which will cause
13873 * the kernel to hang, e.g., when trying to remove bnx2i while the
13874 * rootfs is mounted from SAN.
13876 __bnx2x_remove(pdev, dev, bp, false);
13879 static struct pci_driver bnx2x_pci_driver = {
13880 .name = DRV_MODULE_NAME,
13881 .id_table = bnx2x_pci_tbl,
13882 .probe = bnx2x_init_one,
13883 .remove = bnx2x_remove_one,
13884 .suspend = bnx2x_suspend,
13885 .resume = bnx2x_resume,
13886 .err_handler = &bnx2x_err_handler,
13887 #ifdef CONFIG_BNX2X_SRIOV
13888 .sriov_configure = bnx2x_sriov_configure,
13890 .shutdown = bnx2x_shutdown,
13893 static int __init bnx2x_init(void)
13897 pr_info("%s", version);
13899 bnx2x_wq = create_singlethread_workqueue("bnx2x");
13900 if (bnx2x_wq == NULL) {
13901 pr_err("Cannot create workqueue\n");
13904 bnx2x_iov_wq = create_singlethread_workqueue("bnx2x_iov");
13905 if (!bnx2x_iov_wq) {
13906 pr_err("Cannot create iov workqueue\n");
13907 destroy_workqueue(bnx2x_wq);
13911 ret = pci_register_driver(&bnx2x_pci_driver);
13913 pr_err("Cannot register driver\n");
13914 destroy_workqueue(bnx2x_wq);
13915 destroy_workqueue(bnx2x_iov_wq);
13920 static void __exit bnx2x_cleanup(void)
13922 struct list_head *pos, *q;
13924 pci_unregister_driver(&bnx2x_pci_driver);
13926 destroy_workqueue(bnx2x_wq);
13927 destroy_workqueue(bnx2x_iov_wq);
13929 /* Free globally allocated resources */
13930 list_for_each_safe(pos, q, &bnx2x_prev_list) {
13931 struct bnx2x_prev_path_list *tmp =
13932 list_entry(pos, struct bnx2x_prev_path_list, list);
13938 void bnx2x_notify_link_changed(struct bnx2x *bp)
13940 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_12 + BP_FUNC(bp)*sizeof(u32), 1);
13943 module_init(bnx2x_init);
13944 module_exit(bnx2x_cleanup);
13947 * bnx2x_set_iscsi_eth_mac_addr - set iSCSI MAC(s).
13949 * @bp: driver handle
13950 * @set: set or clear the CAM entry
13952 * This function will wait until the ramrod completion returns.
13953 * Return 0 if success, -ENODEV if ramrod doesn't return.
13955 static int bnx2x_set_iscsi_eth_mac_addr(struct bnx2x *bp)
13957 unsigned long ramrod_flags = 0;
13959 __set_bit(RAMROD_COMP_WAIT, &ramrod_flags);
13960 return bnx2x_set_mac_one(bp, bp->cnic_eth_dev.iscsi_mac,
13961 &bp->iscsi_l2_mac_obj, true,
13962 BNX2X_ISCSI_ETH_MAC, &ramrod_flags);
13965 /* count denotes the number of new completions we have seen */
13966 static void bnx2x_cnic_sp_post(struct bnx2x *bp, int count)
13968 struct eth_spe *spe;
13969 int cxt_index, cxt_offset;
13971 #ifdef BNX2X_STOP_ON_ERROR
13972 if (unlikely(bp->panic))
13976 spin_lock_bh(&bp->spq_lock);
13977 BUG_ON(bp->cnic_spq_pending < count);
13978 bp->cnic_spq_pending -= count;
13980 for (; bp->cnic_kwq_pending; bp->cnic_kwq_pending--) {
13981 u16 type = (le16_to_cpu(bp->cnic_kwq_cons->hdr.type)
13982 & SPE_HDR_CONN_TYPE) >>
13983 SPE_HDR_CONN_TYPE_SHIFT;
13984 u8 cmd = (le32_to_cpu(bp->cnic_kwq_cons->hdr.conn_and_cmd_data)
13985 >> SPE_HDR_CMD_ID_SHIFT) & 0xff;
13987 /* Set validation for iSCSI L2 client before sending SETUP
13990 if (type == ETH_CONNECTION_TYPE) {
13991 if (cmd == RAMROD_CMD_ID_ETH_CLIENT_SETUP) {
13992 cxt_index = BNX2X_ISCSI_ETH_CID(bp) /
13994 cxt_offset = BNX2X_ISCSI_ETH_CID(bp) -
13995 (cxt_index * ILT_PAGE_CIDS);
13996 bnx2x_set_ctx_validation(bp,
13997 &bp->context[cxt_index].
13998 vcxt[cxt_offset].eth,
13999 BNX2X_ISCSI_ETH_CID(bp));
14004 * There may be not more than 8 L2, not more than 8 L5 SPEs
14005 * and in the air. We also check that number of outstanding
14006 * COMMON ramrods is not more than the EQ and SPQ can
14009 if (type == ETH_CONNECTION_TYPE) {
14010 if (!atomic_read(&bp->cq_spq_left))
14013 atomic_dec(&bp->cq_spq_left);
14014 } else if (type == NONE_CONNECTION_TYPE) {
14015 if (!atomic_read(&bp->eq_spq_left))
14018 atomic_dec(&bp->eq_spq_left);
14019 } else if ((type == ISCSI_CONNECTION_TYPE) ||
14020 (type == FCOE_CONNECTION_TYPE)) {
14021 if (bp->cnic_spq_pending >=
14022 bp->cnic_eth_dev.max_kwqe_pending)
14025 bp->cnic_spq_pending++;
14027 BNX2X_ERR("Unknown SPE type: %d\n", type);
14032 spe = bnx2x_sp_get_next(bp);
14033 *spe = *bp->cnic_kwq_cons;
14035 DP(BNX2X_MSG_SP, "pending on SPQ %d, on KWQ %d count %d\n",
14036 bp->cnic_spq_pending, bp->cnic_kwq_pending, count);
14038 if (bp->cnic_kwq_cons == bp->cnic_kwq_last)
14039 bp->cnic_kwq_cons = bp->cnic_kwq;
14041 bp->cnic_kwq_cons++;
14043 bnx2x_sp_prod_update(bp);
14044 spin_unlock_bh(&bp->spq_lock);
14047 static int bnx2x_cnic_sp_queue(struct net_device *dev,
14048 struct kwqe_16 *kwqes[], u32 count)
14050 struct bnx2x *bp = netdev_priv(dev);
14053 #ifdef BNX2X_STOP_ON_ERROR
14054 if (unlikely(bp->panic)) {
14055 BNX2X_ERR("Can't post to SP queue while panic\n");
14060 if ((bp->recovery_state != BNX2X_RECOVERY_DONE) &&
14061 (bp->recovery_state != BNX2X_RECOVERY_NIC_LOADING)) {
14062 BNX2X_ERR("Handling parity error recovery. Try again later\n");
14066 spin_lock_bh(&bp->spq_lock);
14068 for (i = 0; i < count; i++) {
14069 struct eth_spe *spe = (struct eth_spe *)kwqes[i];
14071 if (bp->cnic_kwq_pending == MAX_SP_DESC_CNT)
14074 *bp->cnic_kwq_prod = *spe;
14076 bp->cnic_kwq_pending++;
14078 DP(BNX2X_MSG_SP, "L5 SPQE %x %x %x:%x pos %d\n",
14079 spe->hdr.conn_and_cmd_data, spe->hdr.type,
14080 spe->data.update_data_addr.hi,
14081 spe->data.update_data_addr.lo,
14082 bp->cnic_kwq_pending);
14084 if (bp->cnic_kwq_prod == bp->cnic_kwq_last)
14085 bp->cnic_kwq_prod = bp->cnic_kwq;
14087 bp->cnic_kwq_prod++;
14090 spin_unlock_bh(&bp->spq_lock);
14092 if (bp->cnic_spq_pending < bp->cnic_eth_dev.max_kwqe_pending)
14093 bnx2x_cnic_sp_post(bp, 0);
14098 static int bnx2x_cnic_ctl_send(struct bnx2x *bp, struct cnic_ctl_info *ctl)
14100 struct cnic_ops *c_ops;
14103 mutex_lock(&bp->cnic_mutex);
14104 c_ops = rcu_dereference_protected(bp->cnic_ops,
14105 lockdep_is_held(&bp->cnic_mutex));
14107 rc = c_ops->cnic_ctl(bp->cnic_data, ctl);
14108 mutex_unlock(&bp->cnic_mutex);
14113 static int bnx2x_cnic_ctl_send_bh(struct bnx2x *bp, struct cnic_ctl_info *ctl)
14115 struct cnic_ops *c_ops;
14119 c_ops = rcu_dereference(bp->cnic_ops);
14121 rc = c_ops->cnic_ctl(bp->cnic_data, ctl);
14128 * for commands that have no data
14130 int bnx2x_cnic_notify(struct bnx2x *bp, int cmd)
14132 struct cnic_ctl_info ctl = {0};
14136 return bnx2x_cnic_ctl_send(bp, &ctl);
14139 static void bnx2x_cnic_cfc_comp(struct bnx2x *bp, int cid, u8 err)
14141 struct cnic_ctl_info ctl = {0};
14143 /* first we tell CNIC and only then we count this as a completion */
14144 ctl.cmd = CNIC_CTL_COMPLETION_CMD;
14145 ctl.data.comp.cid = cid;
14146 ctl.data.comp.error = err;
14148 bnx2x_cnic_ctl_send_bh(bp, &ctl);
14149 bnx2x_cnic_sp_post(bp, 0);
14152 /* Called with netif_addr_lock_bh() taken.
14153 * Sets an rx_mode config for an iSCSI ETH client.
14155 * Completion should be checked outside.
14157 static void bnx2x_set_iscsi_eth_rx_mode(struct bnx2x *bp, bool start)
14159 unsigned long accept_flags = 0, ramrod_flags = 0;
14160 u8 cl_id = bnx2x_cnic_eth_cl_id(bp, BNX2X_ISCSI_ETH_CL_ID_IDX);
14161 int sched_state = BNX2X_FILTER_ISCSI_ETH_STOP_SCHED;
14164 /* Start accepting on iSCSI L2 ring. Accept all multicasts
14165 * because it's the only way for UIO Queue to accept
14166 * multicasts (in non-promiscuous mode only one Queue per
14167 * function will receive multicast packets (leading in our
14170 __set_bit(BNX2X_ACCEPT_UNICAST, &accept_flags);
14171 __set_bit(BNX2X_ACCEPT_ALL_MULTICAST, &accept_flags);
14172 __set_bit(BNX2X_ACCEPT_BROADCAST, &accept_flags);
14173 __set_bit(BNX2X_ACCEPT_ANY_VLAN, &accept_flags);
14175 /* Clear STOP_PENDING bit if START is requested */
14176 clear_bit(BNX2X_FILTER_ISCSI_ETH_STOP_SCHED, &bp->sp_state);
14178 sched_state = BNX2X_FILTER_ISCSI_ETH_START_SCHED;
14180 /* Clear START_PENDING bit if STOP is requested */
14181 clear_bit(BNX2X_FILTER_ISCSI_ETH_START_SCHED, &bp->sp_state);
14183 if (test_bit(BNX2X_FILTER_RX_MODE_PENDING, &bp->sp_state))
14184 set_bit(sched_state, &bp->sp_state);
14186 __set_bit(RAMROD_RX, &ramrod_flags);
14187 bnx2x_set_q_rx_mode(bp, cl_id, 0, accept_flags, 0,
14192 static int bnx2x_drv_ctl(struct net_device *dev, struct drv_ctl_info *ctl)
14194 struct bnx2x *bp = netdev_priv(dev);
14197 switch (ctl->cmd) {
14198 case DRV_CTL_CTXTBL_WR_CMD: {
14199 u32 index = ctl->data.io.offset;
14200 dma_addr_t addr = ctl->data.io.dma_addr;
14202 bnx2x_ilt_wr(bp, index, addr);
14206 case DRV_CTL_RET_L5_SPQ_CREDIT_CMD: {
14207 int count = ctl->data.credit.credit_count;
14209 bnx2x_cnic_sp_post(bp, count);
14213 /* rtnl_lock is held. */
14214 case DRV_CTL_START_L2_CMD: {
14215 struct cnic_eth_dev *cp = &bp->cnic_eth_dev;
14216 unsigned long sp_bits = 0;
14218 /* Configure the iSCSI classification object */
14219 bnx2x_init_mac_obj(bp, &bp->iscsi_l2_mac_obj,
14220 cp->iscsi_l2_client_id,
14221 cp->iscsi_l2_cid, BP_FUNC(bp),
14222 bnx2x_sp(bp, mac_rdata),
14223 bnx2x_sp_mapping(bp, mac_rdata),
14224 BNX2X_FILTER_MAC_PENDING,
14225 &bp->sp_state, BNX2X_OBJ_TYPE_RX,
14228 /* Set iSCSI MAC address */
14229 rc = bnx2x_set_iscsi_eth_mac_addr(bp);
14236 /* Start accepting on iSCSI L2 ring */
14238 netif_addr_lock_bh(dev);
14239 bnx2x_set_iscsi_eth_rx_mode(bp, true);
14240 netif_addr_unlock_bh(dev);
14242 /* bits to wait on */
14243 __set_bit(BNX2X_FILTER_RX_MODE_PENDING, &sp_bits);
14244 __set_bit(BNX2X_FILTER_ISCSI_ETH_START_SCHED, &sp_bits);
14246 if (!bnx2x_wait_sp_comp(bp, sp_bits))
14247 BNX2X_ERR("rx_mode completion timed out!\n");
14252 /* rtnl_lock is held. */
14253 case DRV_CTL_STOP_L2_CMD: {
14254 unsigned long sp_bits = 0;
14256 /* Stop accepting on iSCSI L2 ring */
14257 netif_addr_lock_bh(dev);
14258 bnx2x_set_iscsi_eth_rx_mode(bp, false);
14259 netif_addr_unlock_bh(dev);
14261 /* bits to wait on */
14262 __set_bit(BNX2X_FILTER_RX_MODE_PENDING, &sp_bits);
14263 __set_bit(BNX2X_FILTER_ISCSI_ETH_STOP_SCHED, &sp_bits);
14265 if (!bnx2x_wait_sp_comp(bp, sp_bits))
14266 BNX2X_ERR("rx_mode completion timed out!\n");
14271 /* Unset iSCSI L2 MAC */
14272 rc = bnx2x_del_all_macs(bp, &bp->iscsi_l2_mac_obj,
14273 BNX2X_ISCSI_ETH_MAC, true);
14276 case DRV_CTL_RET_L2_SPQ_CREDIT_CMD: {
14277 int count = ctl->data.credit.credit_count;
14279 smp_mb__before_atomic();
14280 atomic_add(count, &bp->cq_spq_left);
14281 smp_mb__after_atomic();
14284 case DRV_CTL_ULP_REGISTER_CMD: {
14285 int ulp_type = ctl->data.register_data.ulp_type;
14287 if (CHIP_IS_E3(bp)) {
14288 int idx = BP_FW_MB_IDX(bp);
14289 u32 cap = SHMEM2_RD(bp, drv_capabilities_flag[idx]);
14290 int path = BP_PATH(bp);
14291 int port = BP_PORT(bp);
14293 u32 scratch_offset;
14296 /* first write capability to shmem2 */
14297 if (ulp_type == CNIC_ULP_ISCSI)
14298 cap |= DRV_FLAGS_CAPABILITIES_LOADED_ISCSI;
14299 else if (ulp_type == CNIC_ULP_FCOE)
14300 cap |= DRV_FLAGS_CAPABILITIES_LOADED_FCOE;
14301 SHMEM2_WR(bp, drv_capabilities_flag[idx], cap);
14303 if ((ulp_type != CNIC_ULP_FCOE) ||
14304 (!SHMEM2_HAS(bp, ncsi_oem_data_addr)) ||
14305 (!(bp->flags & BC_SUPPORTS_FCOE_FEATURES)))
14308 /* if reached here - should write fcoe capabilities */
14309 scratch_offset = SHMEM2_RD(bp, ncsi_oem_data_addr);
14310 if (!scratch_offset)
14312 scratch_offset += offsetof(struct glob_ncsi_oem_data,
14313 fcoe_features[path][port]);
14314 host_addr = (u32 *) &(ctl->data.register_data.
14316 for (i = 0; i < sizeof(struct fcoe_capabilities);
14318 REG_WR(bp, scratch_offset + i,
14319 *(host_addr + i/4));
14321 bnx2x_schedule_sp_rtnl(bp, BNX2X_SP_RTNL_GET_DRV_VERSION, 0);
14325 case DRV_CTL_ULP_UNREGISTER_CMD: {
14326 int ulp_type = ctl->data.ulp_type;
14328 if (CHIP_IS_E3(bp)) {
14329 int idx = BP_FW_MB_IDX(bp);
14332 cap = SHMEM2_RD(bp, drv_capabilities_flag[idx]);
14333 if (ulp_type == CNIC_ULP_ISCSI)
14334 cap &= ~DRV_FLAGS_CAPABILITIES_LOADED_ISCSI;
14335 else if (ulp_type == CNIC_ULP_FCOE)
14336 cap &= ~DRV_FLAGS_CAPABILITIES_LOADED_FCOE;
14337 SHMEM2_WR(bp, drv_capabilities_flag[idx], cap);
14339 bnx2x_schedule_sp_rtnl(bp, BNX2X_SP_RTNL_GET_DRV_VERSION, 0);
14344 BNX2X_ERR("unknown command %x\n", ctl->cmd);
14351 void bnx2x_setup_cnic_irq_info(struct bnx2x *bp)
14353 struct cnic_eth_dev *cp = &bp->cnic_eth_dev;
14355 if (bp->flags & USING_MSIX_FLAG) {
14356 cp->drv_state |= CNIC_DRV_STATE_USING_MSIX;
14357 cp->irq_arr[0].irq_flags |= CNIC_IRQ_FL_MSIX;
14358 cp->irq_arr[0].vector = bp->msix_table[1].vector;
14360 cp->drv_state &= ~CNIC_DRV_STATE_USING_MSIX;
14361 cp->irq_arr[0].irq_flags &= ~CNIC_IRQ_FL_MSIX;
14363 if (!CHIP_IS_E1x(bp))
14364 cp->irq_arr[0].status_blk = (void *)bp->cnic_sb.e2_sb;
14366 cp->irq_arr[0].status_blk = (void *)bp->cnic_sb.e1x_sb;
14368 cp->irq_arr[0].status_blk_num = bnx2x_cnic_fw_sb_id(bp);
14369 cp->irq_arr[0].status_blk_num2 = bnx2x_cnic_igu_sb_id(bp);
14370 cp->irq_arr[1].status_blk = bp->def_status_blk;
14371 cp->irq_arr[1].status_blk_num = DEF_SB_ID;
14372 cp->irq_arr[1].status_blk_num2 = DEF_SB_IGU_ID;
14377 void bnx2x_setup_cnic_info(struct bnx2x *bp)
14379 struct cnic_eth_dev *cp = &bp->cnic_eth_dev;
14381 cp->ctx_tbl_offset = FUNC_ILT_BASE(BP_FUNC(bp)) +
14382 bnx2x_cid_ilt_lines(bp);
14383 cp->starting_cid = bnx2x_cid_ilt_lines(bp) * ILT_PAGE_CIDS;
14384 cp->fcoe_init_cid = BNX2X_FCOE_ETH_CID(bp);
14385 cp->iscsi_l2_cid = BNX2X_ISCSI_ETH_CID(bp);
14387 DP(NETIF_MSG_IFUP, "BNX2X_1st_NON_L2_ETH_CID(bp) %x, cp->starting_cid %x, cp->fcoe_init_cid %x, cp->iscsi_l2_cid %x\n",
14388 BNX2X_1st_NON_L2_ETH_CID(bp), cp->starting_cid, cp->fcoe_init_cid,
14391 if (NO_ISCSI_OOO(bp))
14392 cp->drv_state |= CNIC_DRV_STATE_NO_ISCSI_OOO;
14395 static int bnx2x_register_cnic(struct net_device *dev, struct cnic_ops *ops,
14398 struct bnx2x *bp = netdev_priv(dev);
14399 struct cnic_eth_dev *cp = &bp->cnic_eth_dev;
14402 DP(NETIF_MSG_IFUP, "Register_cnic called\n");
14405 BNX2X_ERR("NULL ops received\n");
14409 if (!CNIC_SUPPORT(bp)) {
14410 BNX2X_ERR("Can't register CNIC when not supported\n");
14411 return -EOPNOTSUPP;
14414 if (!CNIC_LOADED(bp)) {
14415 rc = bnx2x_load_cnic(bp);
14417 BNX2X_ERR("CNIC-related load failed\n");
14422 bp->cnic_enabled = true;
14424 bp->cnic_kwq = kzalloc(PAGE_SIZE, GFP_KERNEL);
14428 bp->cnic_kwq_cons = bp->cnic_kwq;
14429 bp->cnic_kwq_prod = bp->cnic_kwq;
14430 bp->cnic_kwq_last = bp->cnic_kwq + MAX_SP_DESC_CNT;
14432 bp->cnic_spq_pending = 0;
14433 bp->cnic_kwq_pending = 0;
14435 bp->cnic_data = data;
14438 cp->drv_state |= CNIC_DRV_STATE_REGD;
14439 cp->iro_arr = bp->iro_arr;
14441 bnx2x_setup_cnic_irq_info(bp);
14443 rcu_assign_pointer(bp->cnic_ops, ops);
14445 /* Schedule driver to read CNIC driver versions */
14446 bnx2x_schedule_sp_rtnl(bp, BNX2X_SP_RTNL_GET_DRV_VERSION, 0);
14451 static int bnx2x_unregister_cnic(struct net_device *dev)
14453 struct bnx2x *bp = netdev_priv(dev);
14454 struct cnic_eth_dev *cp = &bp->cnic_eth_dev;
14456 mutex_lock(&bp->cnic_mutex);
14458 RCU_INIT_POINTER(bp->cnic_ops, NULL);
14459 mutex_unlock(&bp->cnic_mutex);
14461 bp->cnic_enabled = false;
14462 kfree(bp->cnic_kwq);
14463 bp->cnic_kwq = NULL;
14468 static struct cnic_eth_dev *bnx2x_cnic_probe(struct net_device *dev)
14470 struct bnx2x *bp = netdev_priv(dev);
14471 struct cnic_eth_dev *cp = &bp->cnic_eth_dev;
14473 /* If both iSCSI and FCoE are disabled - return NULL in
14474 * order to indicate CNIC that it should not try to work
14475 * with this device.
14477 if (NO_ISCSI(bp) && NO_FCOE(bp))
14480 cp->drv_owner = THIS_MODULE;
14481 cp->chip_id = CHIP_ID(bp);
14482 cp->pdev = bp->pdev;
14483 cp->io_base = bp->regview;
14484 cp->io_base2 = bp->doorbells;
14485 cp->max_kwqe_pending = 8;
14486 cp->ctx_blk_size = CDU_ILT_PAGE_SZ;
14487 cp->ctx_tbl_offset = FUNC_ILT_BASE(BP_FUNC(bp)) +
14488 bnx2x_cid_ilt_lines(bp);
14489 cp->ctx_tbl_len = CNIC_ILT_LINES;
14490 cp->starting_cid = bnx2x_cid_ilt_lines(bp) * ILT_PAGE_CIDS;
14491 cp->drv_submit_kwqes_16 = bnx2x_cnic_sp_queue;
14492 cp->drv_ctl = bnx2x_drv_ctl;
14493 cp->drv_register_cnic = bnx2x_register_cnic;
14494 cp->drv_unregister_cnic = bnx2x_unregister_cnic;
14495 cp->fcoe_init_cid = BNX2X_FCOE_ETH_CID(bp);
14496 cp->iscsi_l2_client_id =
14497 bnx2x_cnic_eth_cl_id(bp, BNX2X_ISCSI_ETH_CL_ID_IDX);
14498 cp->iscsi_l2_cid = BNX2X_ISCSI_ETH_CID(bp);
14500 if (NO_ISCSI_OOO(bp))
14501 cp->drv_state |= CNIC_DRV_STATE_NO_ISCSI_OOO;
14504 cp->drv_state |= CNIC_DRV_STATE_NO_ISCSI;
14507 cp->drv_state |= CNIC_DRV_STATE_NO_FCOE;
14510 "page_size %d, tbl_offset %d, tbl_lines %d, starting cid %d\n",
14512 cp->ctx_tbl_offset,
14518 static u32 bnx2x_rx_ustorm_prods_offset(struct bnx2x_fastpath *fp)
14520 struct bnx2x *bp = fp->bp;
14521 u32 offset = BAR_USTRORM_INTMEM;
14524 return bnx2x_vf_ustorm_prods_offset(bp, fp);
14525 else if (!CHIP_IS_E1x(bp))
14526 offset += USTORM_RX_PRODS_E2_OFFSET(fp->cl_qzone_id);
14528 offset += USTORM_RX_PRODS_E1X_OFFSET(BP_PORT(bp), fp->cl_id);
14533 /* called only on E1H or E2.
14534 * When pretending to be PF, the pretend value is the function number 0...7
14535 * When pretending to be VF, the pretend val is the PF-num:VF-valid:ABS-VFID
14538 int bnx2x_pretend_func(struct bnx2x *bp, u16 pretend_func_val)
14542 if (CHIP_IS_E1H(bp) && pretend_func_val >= E1H_FUNC_MAX)
14545 /* get my own pretend register */
14546 pretend_reg = bnx2x_get_pretend_reg(bp);
14547 REG_WR(bp, pretend_reg, pretend_func_val);
14548 REG_RD(bp, pretend_reg);
14552 static void bnx2x_ptp_task(struct work_struct *work)
14554 struct bnx2x *bp = container_of(work, struct bnx2x, ptp_task);
14555 int port = BP_PORT(bp);
14558 struct skb_shared_hwtstamps shhwtstamps;
14560 /* Read Tx timestamp registers */
14561 val_seq = REG_RD(bp, port ? NIG_REG_P1_TLLH_PTP_BUF_SEQID :
14562 NIG_REG_P0_TLLH_PTP_BUF_SEQID);
14563 if (val_seq & 0x10000) {
14564 /* There is a valid timestamp value */
14565 timestamp = REG_RD(bp, port ? NIG_REG_P1_TLLH_PTP_BUF_TS_MSB :
14566 NIG_REG_P0_TLLH_PTP_BUF_TS_MSB);
14568 timestamp |= REG_RD(bp, port ? NIG_REG_P1_TLLH_PTP_BUF_TS_LSB :
14569 NIG_REG_P0_TLLH_PTP_BUF_TS_LSB);
14570 /* Reset timestamp register to allow new timestamp */
14571 REG_WR(bp, port ? NIG_REG_P1_TLLH_PTP_BUF_SEQID :
14572 NIG_REG_P0_TLLH_PTP_BUF_SEQID, 0x10000);
14573 ns = timecounter_cyc2time(&bp->timecounter, timestamp);
14575 memset(&shhwtstamps, 0, sizeof(shhwtstamps));
14576 shhwtstamps.hwtstamp = ns_to_ktime(ns);
14577 skb_tstamp_tx(bp->ptp_tx_skb, &shhwtstamps);
14578 dev_kfree_skb_any(bp->ptp_tx_skb);
14579 bp->ptp_tx_skb = NULL;
14581 DP(BNX2X_MSG_PTP, "Tx timestamp, timestamp cycles = %llu, ns = %llu\n",
14584 DP(BNX2X_MSG_PTP, "There is no valid Tx timestamp yet\n");
14585 /* Reschedule to keep checking for a valid timestamp value */
14586 schedule_work(&bp->ptp_task);
14590 void bnx2x_set_rx_ts(struct bnx2x *bp, struct sk_buff *skb)
14592 int port = BP_PORT(bp);
14595 timestamp = REG_RD(bp, port ? NIG_REG_P1_LLH_PTP_HOST_BUF_TS_MSB :
14596 NIG_REG_P0_LLH_PTP_HOST_BUF_TS_MSB);
14598 timestamp |= REG_RD(bp, port ? NIG_REG_P1_LLH_PTP_HOST_BUF_TS_LSB :
14599 NIG_REG_P0_LLH_PTP_HOST_BUF_TS_LSB);
14601 /* Reset timestamp register to allow new timestamp */
14602 REG_WR(bp, port ? NIG_REG_P1_LLH_PTP_HOST_BUF_SEQID :
14603 NIG_REG_P0_LLH_PTP_HOST_BUF_SEQID, 0x10000);
14605 ns = timecounter_cyc2time(&bp->timecounter, timestamp);
14607 skb_hwtstamps(skb)->hwtstamp = ns_to_ktime(ns);
14609 DP(BNX2X_MSG_PTP, "Rx timestamp, timestamp cycles = %llu, ns = %llu\n",
14614 static cycle_t bnx2x_cyclecounter_read(const struct cyclecounter *cc)
14616 struct bnx2x *bp = container_of(cc, struct bnx2x, cyclecounter);
14617 int port = BP_PORT(bp);
14621 REG_RD_DMAE(bp, port ? NIG_REG_TIMESYNC_GEN_REG + tsgen_synctime_t1 :
14622 NIG_REG_TIMESYNC_GEN_REG + tsgen_synctime_t0, wb_data, 2);
14623 phc_cycles = wb_data[1];
14624 phc_cycles = (phc_cycles << 32) + wb_data[0];
14626 DP(BNX2X_MSG_PTP, "PHC read cycles = %llu\n", phc_cycles);
14631 static void bnx2x_init_cyclecounter(struct bnx2x *bp)
14633 memset(&bp->cyclecounter, 0, sizeof(bp->cyclecounter));
14634 bp->cyclecounter.read = bnx2x_cyclecounter_read;
14635 bp->cyclecounter.mask = CYCLECOUNTER_MASK(64);
14636 bp->cyclecounter.shift = 1;
14637 bp->cyclecounter.mult = 1;
14640 static int bnx2x_send_reset_timesync_ramrod(struct bnx2x *bp)
14642 struct bnx2x_func_state_params func_params = {NULL};
14643 struct bnx2x_func_set_timesync_params *set_timesync_params =
14644 &func_params.params.set_timesync;
14646 /* Prepare parameters for function state transitions */
14647 __set_bit(RAMROD_COMP_WAIT, &func_params.ramrod_flags);
14648 __set_bit(RAMROD_RETRY, &func_params.ramrod_flags);
14650 func_params.f_obj = &bp->func_obj;
14651 func_params.cmd = BNX2X_F_CMD_SET_TIMESYNC;
14653 /* Function parameters */
14654 set_timesync_params->drift_adjust_cmd = TS_DRIFT_ADJUST_RESET;
14655 set_timesync_params->offset_cmd = TS_OFFSET_KEEP;
14657 return bnx2x_func_state_change(bp, &func_params);
14660 static int bnx2x_enable_ptp_packets(struct bnx2x *bp)
14662 struct bnx2x_queue_state_params q_params;
14665 /* send queue update ramrod to enable PTP packets */
14666 memset(&q_params, 0, sizeof(q_params));
14667 __set_bit(RAMROD_COMP_WAIT, &q_params.ramrod_flags);
14668 q_params.cmd = BNX2X_Q_CMD_UPDATE;
14669 __set_bit(BNX2X_Q_UPDATE_PTP_PKTS_CHNG,
14670 &q_params.params.update.update_flags);
14671 __set_bit(BNX2X_Q_UPDATE_PTP_PKTS,
14672 &q_params.params.update.update_flags);
14674 /* send the ramrod on all the queues of the PF */
14675 for_each_eth_queue(bp, i) {
14676 struct bnx2x_fastpath *fp = &bp->fp[i];
14678 /* Set the appropriate Queue object */
14679 q_params.q_obj = &bnx2x_sp_obj(bp, fp).q_obj;
14681 /* Update the Queue state */
14682 rc = bnx2x_queue_state_change(bp, &q_params);
14684 BNX2X_ERR("Failed to enable PTP packets\n");
14692 int bnx2x_configure_ptp_filters(struct bnx2x *bp)
14694 int port = BP_PORT(bp);
14697 if (!bp->hwtstamp_ioctl_called)
14700 switch (bp->tx_type) {
14701 case HWTSTAMP_TX_ON:
14702 bp->flags |= TX_TIMESTAMPING_EN;
14703 REG_WR(bp, port ? NIG_REG_P1_TLLH_PTP_PARAM_MASK :
14704 NIG_REG_P0_TLLH_PTP_PARAM_MASK, 0x6AA);
14705 REG_WR(bp, port ? NIG_REG_P1_TLLH_PTP_RULE_MASK :
14706 NIG_REG_P0_TLLH_PTP_RULE_MASK, 0x3EEE);
14708 case HWTSTAMP_TX_ONESTEP_SYNC:
14709 BNX2X_ERR("One-step timestamping is not supported\n");
14713 switch (bp->rx_filter) {
14714 case HWTSTAMP_FILTER_NONE:
14716 case HWTSTAMP_FILTER_ALL:
14717 case HWTSTAMP_FILTER_SOME:
14718 bp->rx_filter = HWTSTAMP_FILTER_NONE;
14720 case HWTSTAMP_FILTER_PTP_V1_L4_EVENT:
14721 case HWTSTAMP_FILTER_PTP_V1_L4_SYNC:
14722 case HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ:
14723 bp->rx_filter = HWTSTAMP_FILTER_PTP_V1_L4_EVENT;
14724 /* Initialize PTP detection for UDP/IPv4 events */
14725 REG_WR(bp, port ? NIG_REG_P1_LLH_PTP_PARAM_MASK :
14726 NIG_REG_P0_LLH_PTP_PARAM_MASK, 0x7EE);
14727 REG_WR(bp, port ? NIG_REG_P1_LLH_PTP_RULE_MASK :
14728 NIG_REG_P0_LLH_PTP_RULE_MASK, 0x3FFE);
14730 case HWTSTAMP_FILTER_PTP_V2_L4_EVENT:
14731 case HWTSTAMP_FILTER_PTP_V2_L4_SYNC:
14732 case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ:
14733 bp->rx_filter = HWTSTAMP_FILTER_PTP_V2_L4_EVENT;
14734 /* Initialize PTP detection for UDP/IPv4 or UDP/IPv6 events */
14735 REG_WR(bp, port ? NIG_REG_P1_LLH_PTP_PARAM_MASK :
14736 NIG_REG_P0_LLH_PTP_PARAM_MASK, 0x7EA);
14737 REG_WR(bp, port ? NIG_REG_P1_LLH_PTP_RULE_MASK :
14738 NIG_REG_P0_LLH_PTP_RULE_MASK, 0x3FEE);
14740 case HWTSTAMP_FILTER_PTP_V2_L2_EVENT:
14741 case HWTSTAMP_FILTER_PTP_V2_L2_SYNC:
14742 case HWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ:
14743 bp->rx_filter = HWTSTAMP_FILTER_PTP_V2_L2_EVENT;
14744 /* Initialize PTP detection L2 events */
14745 REG_WR(bp, port ? NIG_REG_P1_LLH_PTP_PARAM_MASK :
14746 NIG_REG_P0_LLH_PTP_PARAM_MASK, 0x6BF);
14747 REG_WR(bp, port ? NIG_REG_P1_LLH_PTP_RULE_MASK :
14748 NIG_REG_P0_LLH_PTP_RULE_MASK, 0x3EFF);
14751 case HWTSTAMP_FILTER_PTP_V2_EVENT:
14752 case HWTSTAMP_FILTER_PTP_V2_SYNC:
14753 case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ:
14754 bp->rx_filter = HWTSTAMP_FILTER_PTP_V2_EVENT;
14755 /* Initialize PTP detection L2, UDP/IPv4 or UDP/IPv6 events */
14756 REG_WR(bp, port ? NIG_REG_P1_LLH_PTP_PARAM_MASK :
14757 NIG_REG_P0_LLH_PTP_PARAM_MASK, 0x6AA);
14758 REG_WR(bp, port ? NIG_REG_P1_LLH_PTP_RULE_MASK :
14759 NIG_REG_P0_LLH_PTP_RULE_MASK, 0x3EEE);
14763 /* Indicate to FW that this PF expects recorded PTP packets */
14764 rc = bnx2x_enable_ptp_packets(bp);
14768 /* Enable sending PTP packets to host */
14769 REG_WR(bp, port ? NIG_REG_P1_LLH_PTP_TO_HOST :
14770 NIG_REG_P0_LLH_PTP_TO_HOST, 0x1);
14775 static int bnx2x_hwtstamp_ioctl(struct bnx2x *bp, struct ifreq *ifr)
14777 struct hwtstamp_config config;
14780 DP(BNX2X_MSG_PTP, "HWTSTAMP IOCTL called\n");
14782 if (copy_from_user(&config, ifr->ifr_data, sizeof(config)))
14785 DP(BNX2X_MSG_PTP, "Requested tx_type: %d, requested rx_filters = %d\n",
14786 config.tx_type, config.rx_filter);
14788 if (config.flags) {
14789 BNX2X_ERR("config.flags is reserved for future use\n");
14793 bp->hwtstamp_ioctl_called = 1;
14794 bp->tx_type = config.tx_type;
14795 bp->rx_filter = config.rx_filter;
14797 rc = bnx2x_configure_ptp_filters(bp);
14801 config.rx_filter = bp->rx_filter;
14803 return copy_to_user(ifr->ifr_data, &config, sizeof(config)) ?
14807 /* Configures HW for PTP */
14808 static int bnx2x_configure_ptp(struct bnx2x *bp)
14810 int rc, port = BP_PORT(bp);
14813 /* Reset PTP event detection rules - will be configured in the IOCTL */
14814 REG_WR(bp, port ? NIG_REG_P1_LLH_PTP_PARAM_MASK :
14815 NIG_REG_P0_LLH_PTP_PARAM_MASK, 0x7FF);
14816 REG_WR(bp, port ? NIG_REG_P1_LLH_PTP_RULE_MASK :
14817 NIG_REG_P0_LLH_PTP_RULE_MASK, 0x3FFF);
14818 REG_WR(bp, port ? NIG_REG_P1_TLLH_PTP_PARAM_MASK :
14819 NIG_REG_P0_TLLH_PTP_PARAM_MASK, 0x7FF);
14820 REG_WR(bp, port ? NIG_REG_P1_TLLH_PTP_RULE_MASK :
14821 NIG_REG_P0_TLLH_PTP_RULE_MASK, 0x3FFF);
14823 /* Disable PTP packets to host - will be configured in the IOCTL*/
14824 REG_WR(bp, port ? NIG_REG_P1_LLH_PTP_TO_HOST :
14825 NIG_REG_P0_LLH_PTP_TO_HOST, 0x0);
14827 /* Enable the PTP feature */
14828 REG_WR(bp, port ? NIG_REG_P1_PTP_EN :
14829 NIG_REG_P0_PTP_EN, 0x3F);
14831 /* Enable the free-running counter */
14834 REG_WR_DMAE(bp, NIG_REG_TIMESYNC_GEN_REG + tsgen_ctrl, wb_data, 2);
14836 /* Reset drift register (offset register is not reset) */
14837 rc = bnx2x_send_reset_timesync_ramrod(bp);
14839 BNX2X_ERR("Failed to reset PHC drift register\n");
14843 /* Reset possibly old timestamps */
14844 REG_WR(bp, port ? NIG_REG_P1_LLH_PTP_HOST_BUF_SEQID :
14845 NIG_REG_P0_LLH_PTP_HOST_BUF_SEQID, 0x10000);
14846 REG_WR(bp, port ? NIG_REG_P1_TLLH_PTP_BUF_SEQID :
14847 NIG_REG_P0_TLLH_PTP_BUF_SEQID, 0x10000);
14852 /* Called during load, to initialize PTP-related stuff */
14853 void bnx2x_init_ptp(struct bnx2x *bp)
14857 /* Configure PTP in HW */
14858 rc = bnx2x_configure_ptp(bp);
14860 BNX2X_ERR("Stopping PTP initialization\n");
14864 /* Init work queue for Tx timestamping */
14865 INIT_WORK(&bp->ptp_task, bnx2x_ptp_task);
14867 /* Init cyclecounter and timecounter. This is done only in the first
14868 * load. If done in every load, PTP application will fail when doing
14869 * unload / load (e.g. MTU change) while it is running.
14871 if (!bp->timecounter_init_done) {
14872 bnx2x_init_cyclecounter(bp);
14873 timecounter_init(&bp->timecounter, &bp->cyclecounter,
14874 ktime_to_ns(ktime_get_real()));
14875 bp->timecounter_init_done = 1;
14878 DP(BNX2X_MSG_PTP, "PTP initialization ended successfully\n");