drivers/net/ethernet/broadcom/bnx2x/bnx2x_main.c

   1 /* bnx2x_main.c: QLogic Everest network driver.
   2  *
   3  * Copyright (c) 2007-2013 Broadcom Corporation
   4  * Copyright (c) 2014 QLogic Corporation
   5  * All rights reserved
   6  *
   7  * This program is free software; you can redistribute it and/or modify
   8  * it under the terms of the GNU General Public License as published by
   9  * the Free Software Foundation.
  10  *
  11  * Maintained by: Ariel Elior <ariel.elior@qlogic.com>
  12  * Written by: Eliezer Tamir
  13  * Based on code from Michael Chan's bnx2 driver
  14  * UDP CSUM errata workaround by Arik Gendelman
  15  * Slowpath and fastpath rework by Vladislav Zolotarov
  16  * Statistics and Link management by Yitchak Gertner
  17  *
  18  */
  19
  20 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
  21
  22 #include <linux/module.h>
  23 #include <linux/moduleparam.h>
  24 #include <linux/kernel.h>
  25 #include <linux/device.h>  /* for dev_info() */
  26 #include <linux/timer.h>
  27 #include <linux/errno.h>
  28 #include <linux/ioport.h>
  29 #include <linux/slab.h>
  30 #include <linux/interrupt.h>
  31 #include <linux/pci.h>
  32 #include <linux/aer.h>
  33 #include <linux/init.h>
  34 #include <linux/netdevice.h>
  35 #include <linux/etherdevice.h>
  36 #include <linux/skbuff.h>
  37 #include <linux/dma-mapping.h>
  38 #include <linux/bitops.h>
  39 #include <linux/irq.h>
  40 #include <linux/delay.h>
  41 #include <asm/byteorder.h>
  42 #include <linux/time.h>
  43 #include <linux/ethtool.h>
  44 #include <linux/mii.h>
  45 #include <linux/if_vlan.h>
  46 #include <linux/crash_dump.h>
  47 #include <net/ip.h>
  48 #include <net/ipv6.h>
  49 #include <net/tcp.h>
  50 #include <net/vxlan.h>
  51 #include <net/checksum.h>
  52 #include <net/ip6_checksum.h>
  53 #include <linux/workqueue.h>
  54 #include <linux/crc32.h>
  55 #include <linux/crc32c.h>
  56 #include <linux/prefetch.h>
  57 #include <linux/zlib.h>
  58 #include <linux/io.h>
  59 #include <linux/semaphore.h>
  60 #include <linux/stringify.h>
  61 #include <linux/vmalloc.h>
  62 #include "bnx2x.h"
  63 #include "bnx2x_init.h"
  64 #include "bnx2x_init_ops.h"
  65 #include "bnx2x_cmn.h"
  66 #include "bnx2x_vfpf.h"
  67 #include "bnx2x_dcb.h"
  68 #include "bnx2x_sp.h"
  69 #include <linux/firmware.h>
  70 #include "bnx2x_fw_file_hdr.h"
  71 /* FW files */
  72 #define FW_FILE_VERSION                                 \
  73         __stringify(BCM_5710_FW_MAJOR_VERSION) "."      \
  74         __stringify(BCM_5710_FW_MINOR_VERSION) "."      \
  75         __stringify(BCM_5710_FW_REVISION_VERSION) "."   \
  76         __stringify(BCM_5710_FW_ENGINEERING_VERSION)
  77 #define FW_FILE_NAME_E1         "bnx2x/bnx2x-e1-" FW_FILE_VERSION ".fw"
  78 #define FW_FILE_NAME_E1H        "bnx2x/bnx2x-e1h-" FW_FILE_VERSION ".fw"
  79 #define FW_FILE_NAME_E2         "bnx2x/bnx2x-e2-" FW_FILE_VERSION ".fw"
  80
  81 /* Time in jiffies before concluding the transmitter is hung */
  82 #define TX_TIMEOUT              (5*HZ)
  83
  84 static char version[] =
  85         "QLogic 5771x/578xx 10/20-Gigabit Ethernet Driver "
  86         DRV_MODULE_NAME " " DRV_MODULE_VERSION " (" DRV_MODULE_RELDATE ")\n";
  87
  88 MODULE_AUTHOR("Eliezer Tamir");
  89 MODULE_DESCRIPTION("QLogic "
  90                    "BCM57710/57711/57711E/"
  91                    "57712/57712_MF/57800/57800_MF/57810/57810_MF/"
  92                    "57840/57840_MF Driver");
  93 MODULE_LICENSE("GPL");
  94 MODULE_VERSION(DRV_MODULE_VERSION);
  95 MODULE_FIRMWARE(FW_FILE_NAME_E1);
  96 MODULE_FIRMWARE(FW_FILE_NAME_E1H);
  97 MODULE_FIRMWARE(FW_FILE_NAME_E2);
  98
  99 int bnx2x_num_queues;
 100 module_param_named(num_queues, bnx2x_num_queues, int, 0444);
 101 MODULE_PARM_DESC(num_queues,
 102                  " Set number of queues (default is as a number of CPUs)");
 103
 104 static int disable_tpa;
 105 module_param(disable_tpa, int, 0444);
 106 MODULE_PARM_DESC(disable_tpa, " Disable the TPA (LRO) feature");
 107
 108 static int int_mode;
 109 module_param(int_mode, int, 0444);
 110 MODULE_PARM_DESC(int_mode, " Force interrupt mode other than MSI-X "
 111                                 "(1 INT#x; 2 MSI)");
 112
 113 static int dropless_fc;
 114 module_param(dropless_fc, int, 0444);
 115 MODULE_PARM_DESC(dropless_fc, " Pause on exhausted host ring");
 116
 117 static int mrrs = -1;
 118 module_param(mrrs, int, 0444);
 119 MODULE_PARM_DESC(mrrs, " Force Max Read Req Size (0..3) (for debug)");
 120
 121 static int debug;
 122 module_param(debug, int, 0444);
 123 MODULE_PARM_DESC(debug, " Default debug msglevel");
 124
 125 static struct workqueue_struct *bnx2x_wq;
 126 struct workqueue_struct *bnx2x_iov_wq;
 127
 128 struct bnx2x_mac_vals {
 129         u32 xmac_addr;
 130         u32 xmac_val;
 131         u32 emac_addr;
 132         u32 emac_val;
 133         u32 umac_addr[2];
 134         u32 umac_val[2];
 135         u32 bmac_addr;
 136         u32 bmac_val[2];
 137 };
 138
 139 enum bnx2x_board_type {
 140         BCM57710 = 0,
 141         BCM57711,
 142         BCM57711E,
 143         BCM57712,
 144         BCM57712_MF,
 145         BCM57712_VF,
 146         BCM57800,
 147         BCM57800_MF,
 148         BCM57800_VF,
 149         BCM57810,
 150         BCM57810_MF,
 151         BCM57810_VF,
 152         BCM57840_4_10,
 153         BCM57840_2_20,
 154         BCM57840_MF,
 155         BCM57840_VF,
 156         BCM57811,
 157         BCM57811_MF,
 158         BCM57840_O,
 159         BCM57840_MFO,
 160         BCM57811_VF
 161 };
 162
 163 /* indexed by board_type, above */
 164 static struct {
 165         char *name;
 166 } board_info[] = {
 167         [BCM57710]      = { "QLogic BCM57710 10 Gigabit PCIe [Everest]" },
 168         [BCM57711]      = { "QLogic BCM57711 10 Gigabit PCIe" },
 169         [BCM57711E]     = { "QLogic BCM57711E 10 Gigabit PCIe" },
 170         [BCM57712]      = { "QLogic BCM57712 10 Gigabit Ethernet" },
 171         [BCM57712_MF]   = { "QLogic BCM57712 10 Gigabit Ethernet Multi Function" },
 172         [BCM57712_VF]   = { "QLogic BCM57712 10 Gigabit Ethernet Virtual Function" },
 173         [BCM57800]      = { "QLogic BCM57800 10 Gigabit Ethernet" },
 174         [BCM57800_MF]   = { "QLogic BCM57800 10 Gigabit Ethernet Multi Function" },
 175         [BCM57800_VF]   = { "QLogic BCM57800 10 Gigabit Ethernet Virtual Function" },
 176         [BCM57810]      = { "QLogic BCM57810 10 Gigabit Ethernet" },
 177         [BCM57810_MF]   = { "QLogic BCM57810 10 Gigabit Ethernet Multi Function" },
 178         [BCM57810_VF]   = { "QLogic BCM57810 10 Gigabit Ethernet Virtual Function" },
 179         [BCM57840_4_10] = { "QLogic BCM57840 10 Gigabit Ethernet" },
 180         [BCM57840_2_20] = { "QLogic BCM57840 20 Gigabit Ethernet" },
 181         [BCM57840_MF]   = { "QLogic BCM57840 10/20 Gigabit Ethernet Multi Function" },
 182         [BCM57840_VF]   = { "QLogic BCM57840 10/20 Gigabit Ethernet Virtual Function" },
 183         [BCM57811]      = { "QLogic BCM57811 10 Gigabit Ethernet" },
 184         [BCM57811_MF]   = { "QLogic BCM57811 10 Gigabit Ethernet Multi Function" },
 185         [BCM57840_O]    = { "QLogic BCM57840 10/20 Gigabit Ethernet" },
 186         [BCM57840_MFO]  = { "QLogic BCM57840 10/20 Gigabit Ethernet Multi Function" },
 187         [BCM57811_VF]   = { "QLogic BCM57840 10/20 Gigabit Ethernet Virtual Function" }
 188 };
 189
 190 #ifndef PCI_DEVICE_ID_NX2_57710
 191 #define PCI_DEVICE_ID_NX2_57710         CHIP_NUM_57710
 192 #endif
 193 #ifndef PCI_DEVICE_ID_NX2_57711
 194 #define PCI_DEVICE_ID_NX2_57711         CHIP_NUM_57711
 195 #endif
 196 #ifndef PCI_DEVICE_ID_NX2_57711E
 197 #define PCI_DEVICE_ID_NX2_57711E        CHIP_NUM_57711E
 198 #endif
 199 #ifndef PCI_DEVICE_ID_NX2_57712
 200 #define PCI_DEVICE_ID_NX2_57712         CHIP_NUM_57712
 201 #endif
 202 #ifndef PCI_DEVICE_ID_NX2_57712_MF
 203 #define PCI_DEVICE_ID_NX2_57712_MF      CHIP_NUM_57712_MF
 204 #endif
 205 #ifndef PCI_DEVICE_ID_NX2_57712_VF
 206 #define PCI_DEVICE_ID_NX2_57712_VF      CHIP_NUM_57712_VF
 207 #endif
 208 #ifndef PCI_DEVICE_ID_NX2_57800
 209 #define PCI_DEVICE_ID_NX2_57800         CHIP_NUM_57800
 210 #endif
 211 #ifndef PCI_DEVICE_ID_NX2_57800_MF
 212 #define PCI_DEVICE_ID_NX2_57800_MF      CHIP_NUM_57800_MF
 213 #endif
 214 #ifndef PCI_DEVICE_ID_NX2_57800_VF
 215 #define PCI_DEVICE_ID_NX2_57800_VF      CHIP_NUM_57800_VF
 216 #endif
 217 #ifndef PCI_DEVICE_ID_NX2_57810
 218 #define PCI_DEVICE_ID_NX2_57810         CHIP_NUM_57810
 219 #endif
 220 #ifndef PCI_DEVICE_ID_NX2_57810_MF
 221 #define PCI_DEVICE_ID_NX2_57810_MF      CHIP_NUM_57810_MF
 222 #endif
 223 #ifndef PCI_DEVICE_ID_NX2_57840_O
 224 #define PCI_DEVICE_ID_NX2_57840_O       CHIP_NUM_57840_OBSOLETE
 225 #endif
 226 #ifndef PCI_DEVICE_ID_NX2_57810_VF
 227 #define PCI_DEVICE_ID_NX2_57810_VF      CHIP_NUM_57810_VF
 228 #endif
 229 #ifndef PCI_DEVICE_ID_NX2_57840_4_10
 230 #define PCI_DEVICE_ID_NX2_57840_4_10    CHIP_NUM_57840_4_10
 231 #endif
 232 #ifndef PCI_DEVICE_ID_NX2_57840_2_20
 233 #define PCI_DEVICE_ID_NX2_57840_2_20    CHIP_NUM_57840_2_20
 234 #endif
 235 #ifndef PCI_DEVICE_ID_NX2_57840_MFO
 236 #define PCI_DEVICE_ID_NX2_57840_MFO     CHIP_NUM_57840_MF_OBSOLETE
 237 #endif
 238 #ifndef PCI_DEVICE_ID_NX2_57840_MF
 239 #define PCI_DEVICE_ID_NX2_57840_MF      CHIP_NUM_57840_MF
 240 #endif
 241 #ifndef PCI_DEVICE_ID_NX2_57840_VF
 242 #define PCI_DEVICE_ID_NX2_57840_VF      CHIP_NUM_57840_VF
 243 #endif
 244 #ifndef PCI_DEVICE_ID_NX2_57811
 245 #define PCI_DEVICE_ID_NX2_57811         CHIP_NUM_57811
 246 #endif
 247 #ifndef PCI_DEVICE_ID_NX2_57811_MF
 248 #define PCI_DEVICE_ID_NX2_57811_MF      CHIP_NUM_57811_MF
 249 #endif
 250 #ifndef PCI_DEVICE_ID_NX2_57811_VF
 251 #define PCI_DEVICE_ID_NX2_57811_VF      CHIP_NUM_57811_VF
 252 #endif
 253
 254 static const struct pci_device_id bnx2x_pci_tbl[] = {
 255         { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57710), BCM57710 },
 256         { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57711), BCM57711 },
 257         { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57711E), BCM57711E },
 258         { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57712), BCM57712 },
 259         { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57712_MF), BCM57712_MF },
 260         { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57712_VF), BCM57712_VF },
 261         { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57800), BCM57800 },
 262         { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57800_MF), BCM57800_MF },
 263         { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57800_VF), BCM57800_VF },
 264         { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57810), BCM57810 },
 265         { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57810_MF), BCM57810_MF },
 266         { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57840_O), BCM57840_O },
 267         { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57840_4_10), BCM57840_4_10 },
 268         { PCI_VDEVICE(QLOGIC,   PCI_DEVICE_ID_NX2_57840_4_10), BCM57840_4_10 },
 269         { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57840_2_20), BCM57840_2_20 },
 270         { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57810_VF), BCM57810_VF },
 271         { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57840_MFO), BCM57840_MFO },
 272         { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57840_MF), BCM57840_MF },
 273         { PCI_VDEVICE(QLOGIC,   PCI_DEVICE_ID_NX2_57840_MF), BCM57840_MF },
 274         { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57840_VF), BCM57840_VF },
 275         { PCI_VDEVICE(QLOGIC,   PCI_DEVICE_ID_NX2_57840_VF), BCM57840_VF },
 276         { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57811), BCM57811 },
 277         { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57811_MF), BCM57811_MF },
 278         { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57811_VF), BCM57811_VF },
 279         { 0 }
 280 };
 281
 282 MODULE_DEVICE_TABLE(pci, bnx2x_pci_tbl);
 283
 284 /* Global resources for unloading a previously loaded device */
 285 #define BNX2X_PREV_WAIT_NEEDED 1
 286 static DEFINE_SEMAPHORE(bnx2x_prev_sem);
 287 static LIST_HEAD(bnx2x_prev_list);
 288
 289 /* Forward declaration */
 290 static struct cnic_eth_dev *bnx2x_cnic_probe(struct net_device *dev);
 291 static u32 bnx2x_rx_ustorm_prods_offset(struct bnx2x_fastpath *fp);
 292 static int bnx2x_set_storm_rx_mode(struct bnx2x *bp);
 293
 294 /****************************************************************************
 295 * General service functions
 296 ****************************************************************************/
 297
 298 static int bnx2x_hwtstamp_ioctl(struct bnx2x *bp, struct ifreq *ifr);
 299
 300 static void __storm_memset_dma_mapping(struct bnx2x *bp,
 301                                        u32 addr, dma_addr_t mapping)
 302 {
 303         REG_WR(bp,  addr, U64_LO(mapping));
 304         REG_WR(bp,  addr + 4, U64_HI(mapping));
 305 }
 306
 307 static void storm_memset_spq_addr(struct bnx2x *bp,
 308                                   dma_addr_t mapping, u16 abs_fid)
 309 {
 310         u32 addr = XSEM_REG_FAST_MEMORY +
 311                         XSTORM_SPQ_PAGE_BASE_OFFSET(abs_fid);
 312
 313         __storm_memset_dma_mapping(bp, addr, mapping);
 314 }
 315
 316 static void storm_memset_vf_to_pf(struct bnx2x *bp, u16 abs_fid,
 317                                   u16 pf_id)
 318 {
 319         REG_WR8(bp, BAR_XSTRORM_INTMEM + XSTORM_VF_TO_PF_OFFSET(abs_fid),
 320                 pf_id);
 321         REG_WR8(bp, BAR_CSTRORM_INTMEM + CSTORM_VF_TO_PF_OFFSET(abs_fid),
 322                 pf_id);
 323         REG_WR8(bp, BAR_TSTRORM_INTMEM + TSTORM_VF_TO_PF_OFFSET(abs_fid),
 324                 pf_id);
 325         REG_WR8(bp, BAR_USTRORM_INTMEM + USTORM_VF_TO_PF_OFFSET(abs_fid),
 326                 pf_id);
 327 }
 328
 329 static void storm_memset_func_en(struct bnx2x *bp, u16 abs_fid,
 330                                  u8 enable)
 331 {
 332         REG_WR8(bp, BAR_XSTRORM_INTMEM + XSTORM_FUNC_EN_OFFSET(abs_fid),
 333                 enable);
 334         REG_WR8(bp, BAR_CSTRORM_INTMEM + CSTORM_FUNC_EN_OFFSET(abs_fid),
 335                 enable);
 336         REG_WR8(bp, BAR_TSTRORM_INTMEM + TSTORM_FUNC_EN_OFFSET(abs_fid),
 337                 enable);
 338         REG_WR8(bp, BAR_USTRORM_INTMEM + USTORM_FUNC_EN_OFFSET(abs_fid),
 339                 enable);
 340 }
 341
 342 static void storm_memset_eq_data(struct bnx2x *bp,
 343                                  struct event_ring_data *eq_data,
 344                                 u16 pfid)
 345 {
 346         size_t size = sizeof(struct event_ring_data);
 347
 348         u32 addr = BAR_CSTRORM_INTMEM + CSTORM_EVENT_RING_DATA_OFFSET(pfid);
 349
 350         __storm_memset_struct(bp, addr, size, (u32 *)eq_data);
 351 }
 352
 353 static void storm_memset_eq_prod(struct bnx2x *bp, u16 eq_prod,
 354                                  u16 pfid)
 355 {
 356         u32 addr = BAR_CSTRORM_INTMEM + CSTORM_EVENT_RING_PROD_OFFSET(pfid);
 357         REG_WR16(bp, addr, eq_prod);
 358 }
 359
 360 /* used only at init
 361  * locking is done by mcp
 362  */
 363 static void bnx2x_reg_wr_ind(struct bnx2x *bp, u32 addr, u32 val)
 364 {
 365         pci_write_config_dword(bp->pdev, PCICFG_GRC_ADDRESS, addr);
 366         pci_write_config_dword(bp->pdev, PCICFG_GRC_DATA, val);
 367         pci_write_config_dword(bp->pdev, PCICFG_GRC_ADDRESS,
 368                                PCICFG_VENDOR_ID_OFFSET);
 369 }
 370
 371 static u32 bnx2x_reg_rd_ind(struct bnx2x *bp, u32 addr)
 372 {
 373         u32 val;
 374
 375         pci_write_config_dword(bp->pdev, PCICFG_GRC_ADDRESS, addr);
 376         pci_read_config_dword(bp->pdev, PCICFG_GRC_DATA, &val);
 377         pci_write_config_dword(bp->pdev, PCICFG_GRC_ADDRESS,
 378                                PCICFG_VENDOR_ID_OFFSET);
 379
 380         return val;
 381 }
 382
 383 #define DMAE_DP_SRC_GRC         "grc src_addr [%08x]"
 384 #define DMAE_DP_SRC_PCI         "pci src_addr [%x:%08x]"
 385 #define DMAE_DP_DST_GRC         "grc dst_addr [%08x]"
 386 #define DMAE_DP_DST_PCI         "pci dst_addr [%x:%08x]"
 387 #define DMAE_DP_DST_NONE        "dst_addr [none]"
 388
 389 static void bnx2x_dp_dmae(struct bnx2x *bp,
 390                           struct dmae_command *dmae, int msglvl)
 391 {
 392         u32 src_type = dmae->opcode & DMAE_COMMAND_SRC;
 393         int i;
 394
 395         switch (dmae->opcode & DMAE_COMMAND_DST) {
 396         case DMAE_CMD_DST_PCI:
 397                 if (src_type == DMAE_CMD_SRC_PCI)
 398                         DP(msglvl, "DMAE: opcode 0x%08x\n"
 399                            "src [%x:%08x], len [%d*4], dst [%x:%08x]\n"
 400                            "comp_addr [%x:%08x], comp_val 0x%08x\n",
 401                            dmae->opcode, dmae->src_addr_hi, dmae->src_addr_lo,
 402                            dmae->len, dmae->dst_addr_hi, dmae->dst_addr_lo,
 403                            dmae->comp_addr_hi, dmae->comp_addr_lo,
 404                            dmae->comp_val);
 405                 else
 406                         DP(msglvl, "DMAE: opcode 0x%08x\n"
 407                            "src [%08x], len [%d*4], dst [%x:%08x]\n"
 408                            "comp_addr [%x:%08x], comp_val 0x%08x\n",
 409                            dmae->opcode, dmae->src_addr_lo >> 2,
 410                            dmae->len, dmae->dst_addr_hi, dmae->dst_addr_lo,
 411                            dmae->comp_addr_hi, dmae->comp_addr_lo,
 412                            dmae->comp_val);
 413                 break;
 414         case DMAE_CMD_DST_GRC:
 415                 if (src_type == DMAE_CMD_SRC_PCI)
 416                         DP(msglvl, "DMAE: opcode 0x%08x\n"
 417                            "src [%x:%08x], len [%d*4], dst_addr [%08x]\n"
 418                            "comp_addr [%x:%08x], comp_val 0x%08x\n",
 419                            dmae->opcode, dmae->src_addr_hi, dmae->src_addr_lo,
 420                            dmae->len, dmae->dst_addr_lo >> 2,
 421                            dmae->comp_addr_hi, dmae->comp_addr_lo,
 422                            dmae->comp_val);
 423                 else
 424                         DP(msglvl, "DMAE: opcode 0x%08x\n"
 425                            "src [%08x], len [%d*4], dst [%08x]\n"
 426                            "comp_addr [%x:%08x], comp_val 0x%08x\n",
 427                            dmae->opcode, dmae->src_addr_lo >> 2,
 428                            dmae->len, dmae->dst_addr_lo >> 2,
 429                            dmae->comp_addr_hi, dmae->comp_addr_lo,
 430                            dmae->comp_val);
 431                 break;
 432         default:
 433                 if (src_type == DMAE_CMD_SRC_PCI)
 434                         DP(msglvl, "DMAE: opcode 0x%08x\n"
 435                            "src_addr [%x:%08x]  len [%d * 4]  dst_addr [none]\n"
 436                            "comp_addr [%x:%08x]  comp_val 0x%08x\n",
 437                            dmae->opcode, dmae->src_addr_hi, dmae->src_addr_lo,
 438                            dmae->len, dmae->comp_addr_hi, dmae->comp_addr_lo,
 439                            dmae->comp_val);
 440                 else
 441                         DP(msglvl, "DMAE: opcode 0x%08x\n"
 442                            "src_addr [%08x]  len [%d * 4]  dst_addr [none]\n"
 443                            "comp_addr [%x:%08x]  comp_val 0x%08x\n",
 444                            dmae->opcode, dmae->src_addr_lo >> 2,
 445                            dmae->len, dmae->comp_addr_hi, dmae->comp_addr_lo,
 446                            dmae->comp_val);
 447                 break;
 448         }
 449
 450         for (i = 0; i < (sizeof(struct dmae_command)/4); i++)
 451                 DP(msglvl, "DMAE RAW [%02d]: 0x%08x\n",
 452                    i, *(((u32 *)dmae) + i));
 453 }
 454
 455 /* copy command into DMAE command memory and set DMAE command go */
 456 void bnx2x_post_dmae(struct bnx2x *bp, struct dmae_command *dmae, int idx)
 457 {
 458         u32 cmd_offset;
 459         int i;
 460
 461         cmd_offset = (DMAE_REG_CMD_MEM + sizeof(struct dmae_command) * idx);
 462         for (i = 0; i < (sizeof(struct dmae_command)/4); i++) {
 463                 REG_WR(bp, cmd_offset + i*4, *(((u32 *)dmae) + i));
 464         }
 465         REG_WR(bp, dmae_reg_go_c[idx], 1);
 466 }
 467
 468 u32 bnx2x_dmae_opcode_add_comp(u32 opcode, u8 comp_type)
 469 {
 470         return opcode | ((comp_type << DMAE_COMMAND_C_DST_SHIFT) |
 471                            DMAE_CMD_C_ENABLE);
 472 }
 473
 474 u32 bnx2x_dmae_opcode_clr_src_reset(u32 opcode)
 475 {
 476         return opcode & ~DMAE_CMD_SRC_RESET;
 477 }
 478
 479 u32 bnx2x_dmae_opcode(struct bnx2x *bp, u8 src_type, u8 dst_type,
 480                              bool with_comp, u8 comp_type)
 481 {
 482         u32 opcode = 0;
 483
 484         opcode |= ((src_type << DMAE_COMMAND_SRC_SHIFT) |
 485                    (dst_type << DMAE_COMMAND_DST_SHIFT));
 486
 487         opcode |= (DMAE_CMD_SRC_RESET | DMAE_CMD_DST_RESET);
 488
 489         opcode |= (BP_PORT(bp) ? DMAE_CMD_PORT_1 : DMAE_CMD_PORT_0);
 490         opcode |= ((BP_VN(bp) << DMAE_CMD_E1HVN_SHIFT) |
 491                    (BP_VN(bp) << DMAE_COMMAND_DST_VN_SHIFT));
 492         opcode |= (DMAE_COM_SET_ERR << DMAE_COMMAND_ERR_POLICY_SHIFT);
 493
 494 #ifdef __BIG_ENDIAN
 495         opcode |= DMAE_CMD_ENDIANITY_B_DW_SWAP;
 496 #else
 497         opcode |= DMAE_CMD_ENDIANITY_DW_SWAP;
 498 #endif
 499         if (with_comp)
 500                 opcode = bnx2x_dmae_opcode_add_comp(opcode, comp_type);
 501         return opcode;
 502 }
 503
 504 void bnx2x_prep_dmae_with_comp(struct bnx2x *bp,
 505                                       struct dmae_command *dmae,
 506                                       u8 src_type, u8 dst_type)
 507 {
 508         memset(dmae, 0, sizeof(struct dmae_command));
 509
 510         /* set the opcode */
 511         dmae->opcode = bnx2x_dmae_opcode(bp, src_type, dst_type,
 512                                          true, DMAE_COMP_PCI);
 513
 514         /* fill in the completion parameters */
 515         dmae->comp_addr_lo = U64_LO(bnx2x_sp_mapping(bp, wb_comp));
 516         dmae->comp_addr_hi = U64_HI(bnx2x_sp_mapping(bp, wb_comp));
 517         dmae->comp_val = DMAE_COMP_VAL;
 518 }
 519
 520 /* issue a dmae command over the init-channel and wait for completion */
 521 int bnx2x_issue_dmae_with_comp(struct bnx2x *bp, struct dmae_command *dmae,
 522                                u32 *comp)
 523 {
 524         int cnt = CHIP_REV_IS_SLOW(bp) ? (400000) : 4000;
 525         int rc = 0;
 526
 527         bnx2x_dp_dmae(bp, dmae, BNX2X_MSG_DMAE);
 528
 529         /* Lock the dmae channel. Disable BHs to prevent a dead-lock
 530          * as long as this code is called both from syscall context and
 531          * from ndo_set_rx_mode() flow that may be called from BH.
 532          */
 533
 534         spin_lock_bh(&bp->dmae_lock);
 535
 536         /* reset completion */
 537         *comp = 0;
 538
 539         /* post the command on the channel used for initializations */
 540         bnx2x_post_dmae(bp, dmae, INIT_DMAE_C(bp));
 541
 542         /* wait for completion */
 543         udelay(5);
 544         while ((*comp & ~DMAE_PCI_ERR_FLAG) != DMAE_COMP_VAL) {
 545
 546                 if (!cnt ||
 547                     (bp->recovery_state != BNX2X_RECOVERY_DONE &&
 548                      bp->recovery_state != BNX2X_RECOVERY_NIC_LOADING)) {
 549                         BNX2X_ERR("DMAE timeout!\n");
 550                         rc = DMAE_TIMEOUT;
 551                         goto unlock;
 552                 }
 553                 cnt--;
 554                 udelay(50);
 555         }
 556         if (*comp & DMAE_PCI_ERR_FLAG) {
 557                 BNX2X_ERR("DMAE PCI error!\n");
 558                 rc = DMAE_PCI_ERROR;
 559         }
 560
 561 unlock:
 562
 563         spin_unlock_bh(&bp->dmae_lock);
 564
 565         return rc;
 566 }
 567
 568 void bnx2x_write_dmae(struct bnx2x *bp, dma_addr_t dma_addr, u32 dst_addr,
 569                       u32 len32)
 570 {
 571         int rc;
 572         struct dmae_command dmae;
 573
 574         if (!bp->dmae_ready) {
 575                 u32 *data = bnx2x_sp(bp, wb_data[0]);
 576
 577                 if (CHIP_IS_E1(bp))
 578                         bnx2x_init_ind_wr(bp, dst_addr, data, len32);
 579                 else
 580                         bnx2x_init_str_wr(bp, dst_addr, data, len32);
 581                 return;
 582         }
 583
 584         /* set opcode and fixed command fields */
 585         bnx2x_prep_dmae_with_comp(bp, &dmae, DMAE_SRC_PCI, DMAE_DST_GRC);
 586
 587         /* fill in addresses and len */
 588         dmae.src_addr_lo = U64_LO(dma_addr);
 589         dmae.src_addr_hi = U64_HI(dma_addr);
 590         dmae.dst_addr_lo = dst_addr >> 2;
 591         dmae.dst_addr_hi = 0;
 592         dmae.len = len32;
 593
 594         /* issue the command and wait for completion */
 595         rc = bnx2x_issue_dmae_with_comp(bp, &dmae, bnx2x_sp(bp, wb_comp));
 596         if (rc) {
 597                 BNX2X_ERR("DMAE returned failure %d\n", rc);
 598 #ifdef BNX2X_STOP_ON_ERROR
 599                 bnx2x_panic();
 600 #endif
 601         }
 602 }
 603
 604 void bnx2x_read_dmae(struct bnx2x *bp, u32 src_addr, u32 len32)
 605 {
 606         int rc;
 607         struct dmae_command dmae;
 608
 609         if (!bp->dmae_ready) {
 610                 u32 *data = bnx2x_sp(bp, wb_data[0]);
 611                 int i;
 612
 613                 if (CHIP_IS_E1(bp))
 614                         for (i = 0; i < len32; i++)
 615                                 data[i] = bnx2x_reg_rd_ind(bp, src_addr + i*4);
 616                 else
 617                         for (i = 0; i < len32; i++)
 618                                 data[i] = REG_RD(bp, src_addr + i*4);
 619
 620                 return;
 621         }
 622
 623         /* set opcode and fixed command fields */
 624         bnx2x_prep_dmae_with_comp(bp, &dmae, DMAE_SRC_GRC, DMAE_DST_PCI);
 625
 626         /* fill in addresses and len */
 627         dmae.src_addr_lo = src_addr >> 2;
 628         dmae.src_addr_hi = 0;
 629         dmae.dst_addr_lo = U64_LO(bnx2x_sp_mapping(bp, wb_data));
 630         dmae.dst_addr_hi = U64_HI(bnx2x_sp_mapping(bp, wb_data));
 631         dmae.len = len32;
 632
 633         /* issue the command and wait for completion */
 634         rc = bnx2x_issue_dmae_with_comp(bp, &dmae, bnx2x_sp(bp, wb_comp));
 635         if (rc) {
 636                 BNX2X_ERR("DMAE returned failure %d\n", rc);
 637 #ifdef BNX2X_STOP_ON_ERROR
 638                 bnx2x_panic();
 639 #endif
 640         }
 641 }
 642
 643 static void bnx2x_write_dmae_phys_len(struct bnx2x *bp, dma_addr_t phys_addr,
 644                                       u32 addr, u32 len)
 645 {
 646         int dmae_wr_max = DMAE_LEN32_WR_MAX(bp);
 647         int offset = 0;
 648
 649         while (len > dmae_wr_max) {
 650                 bnx2x_write_dmae(bp, phys_addr + offset,
 651                                  addr + offset, dmae_wr_max);
 652                 offset += dmae_wr_max * 4;
 653                 len -= dmae_wr_max;
 654         }
 655
 656         bnx2x_write_dmae(bp, phys_addr + offset, addr + offset, len);
 657 }
 658
 659 enum storms {
 660            XSTORM,
 661            TSTORM,
 662            CSTORM,
 663            USTORM,
 664            MAX_STORMS
 665 };
 666
 667 #define STORMS_NUM 4
 668 #define REGS_IN_ENTRY 4
 669
 670 static inline int bnx2x_get_assert_list_entry(struct bnx2x *bp,
 671                                               enum storms storm,
 672                                               int entry)
 673 {
 674         switch (storm) {
 675         case XSTORM:
 676                 return XSTORM_ASSERT_LIST_OFFSET(entry);
 677         case TSTORM:
 678                 return TSTORM_ASSERT_LIST_OFFSET(entry);
 679         case CSTORM:
 680                 return CSTORM_ASSERT_LIST_OFFSET(entry);
 681         case USTORM:
 682                 return USTORM_ASSERT_LIST_OFFSET(entry);
 683         case MAX_STORMS:
 684         default:
 685                 BNX2X_ERR("unknown storm\n");
 686         }
 687         return -EINVAL;
 688 }
 689
 690 static int bnx2x_mc_assert(struct bnx2x *bp)
 691 {
 692         char last_idx;
 693         int i, j, rc = 0;
 694         enum storms storm;
 695         u32 regs[REGS_IN_ENTRY];
 696         u32 bar_storm_intmem[STORMS_NUM] = {
 697                 BAR_XSTRORM_INTMEM,
 698                 BAR_TSTRORM_INTMEM,
 699                 BAR_CSTRORM_INTMEM,
 700                 BAR_USTRORM_INTMEM
 701         };
 702         u32 storm_assert_list_index[STORMS_NUM] = {
 703                 XSTORM_ASSERT_LIST_INDEX_OFFSET,
 704                 TSTORM_ASSERT_LIST_INDEX_OFFSET,
 705                 CSTORM_ASSERT_LIST_INDEX_OFFSET,
 706                 USTORM_ASSERT_LIST_INDEX_OFFSET
 707         };
 708         char *storms_string[STORMS_NUM] = {
 709                 "XSTORM",
 710                 "TSTORM",
 711                 "CSTORM",
 712                 "USTORM"
 713         };
 714
 715         for (storm = XSTORM; storm < MAX_STORMS; storm++) {
 716                 last_idx = REG_RD8(bp, bar_storm_intmem[storm] +
 717                                    storm_assert_list_index[storm]);
 718                 if (last_idx)
 719                         BNX2X_ERR("%s_ASSERT_LIST_INDEX 0x%x\n",
 720                                   storms_string[storm], last_idx);
 721
 722                 /* print the asserts */
 723                 for (i = 0; i < STROM_ASSERT_ARRAY_SIZE; i++) {
 724                         /* read a single assert entry */
 725                         for (j = 0; j < REGS_IN_ENTRY; j++)
 726                                 regs[j] = REG_RD(bp, bar_storm_intmem[storm] +
 727                                           bnx2x_get_assert_list_entry(bp,
 728                                                                       storm,
 729                                                                       i) +
 730                                           sizeof(u32) * j);
 731
 732                         /* log entry if it contains a valid assert */
 733                         if (regs[0] != COMMON_ASM_INVALID_ASSERT_OPCODE) {
 734                                 BNX2X_ERR("%s_ASSERT_INDEX 0x%x = 0x%08x 0x%08x 0x%08x 0x%08x\n",
 735                                           storms_string[storm], i, regs[3],
 736                                           regs[2], regs[1], regs[0]);
 737                                 rc++;
 738                         } else {
 739                                 break;
 740                         }
 741                 }
 742         }
 743
 744         BNX2X_ERR("Chip Revision: %s, FW Version: %d_%d_%d\n",
 745                   CHIP_IS_E1(bp) ? "everest1" :
 746                   CHIP_IS_E1H(bp) ? "everest1h" :
 747                   CHIP_IS_E2(bp) ? "everest2" : "everest3",
 748                   BCM_5710_FW_MAJOR_VERSION,
 749                   BCM_5710_FW_MINOR_VERSION,
 750                   BCM_5710_FW_REVISION_VERSION);
 751
 752         return rc;
 753 }
 754
 755 #define MCPR_TRACE_BUFFER_SIZE  (0x800)
 756 #define SCRATCH_BUFFER_SIZE(bp) \
 757         (CHIP_IS_E1(bp) ? 0x10000 : (CHIP_IS_E1H(bp) ? 0x20000 : 0x28000))
 758
 759 void bnx2x_fw_dump_lvl(struct bnx2x *bp, const char *lvl)
 760 {
 761         u32 addr, val;
 762         u32 mark, offset;
 763         __be32 data[9];
 764         int word;
 765         u32 trace_shmem_base;
 766         if (BP_NOMCP(bp)) {
 767                 BNX2X_ERR("NO MCP - can not dump\n");
 768                 return;
 769         }
 770         netdev_printk(lvl, bp->dev, "bc %d.%d.%d\n",
 771                 (bp->common.bc_ver & 0xff0000) >> 16,
 772                 (bp->common.bc_ver & 0xff00) >> 8,
 773                 (bp->common.bc_ver & 0xff));
 774
 775         if (pci_channel_offline(bp->pdev)) {
 776                 BNX2X_ERR("Cannot dump MCP info while in PCI error\n");
 777                 return;
 778         }
 779
 780         val = REG_RD(bp, MCP_REG_MCPR_CPU_PROGRAM_COUNTER);
 781         if (val == REG_RD(bp, MCP_REG_MCPR_CPU_PROGRAM_COUNTER))
 782                 BNX2X_ERR("%s" "MCP PC at 0x%x\n", lvl, val);
 783
 784         if (BP_PATH(bp) == 0)
 785                 trace_shmem_base = bp->common.shmem_base;
 786         else
 787                 trace_shmem_base = SHMEM2_RD(bp, other_shmem_base_addr);
 788
 789         /* sanity */
 790         if (trace_shmem_base < MCPR_SCRATCH_BASE(bp) + MCPR_TRACE_BUFFER_SIZE ||
 791             trace_shmem_base >= MCPR_SCRATCH_BASE(bp) +
 792                                 SCRATCH_BUFFER_SIZE(bp)) {
 793                 BNX2X_ERR("Unable to dump trace buffer (mark %x)\n",
 794                           trace_shmem_base);
 795                 return;
 796         }
 797
 798         addr = trace_shmem_base - MCPR_TRACE_BUFFER_SIZE;
 799
 800         /* validate TRCB signature */
 801         mark = REG_RD(bp, addr);
 802         if (mark != MFW_TRACE_SIGNATURE) {
 803                 BNX2X_ERR("Trace buffer signature is missing.");
 804                 return ;
 805         }
 806
 807         /* read cyclic buffer pointer */
 808         addr += 4;
 809         mark = REG_RD(bp, addr);
 810         mark = MCPR_SCRATCH_BASE(bp) + ((mark + 0x3) & ~0x3) - 0x08000000;
 811         if (mark >= trace_shmem_base || mark < addr + 4) {
 812                 BNX2X_ERR("Mark doesn't fall inside Trace Buffer\n");
 813                 return;
 814         }
 815         printk("%s" "begin fw dump (mark 0x%x)\n", lvl, mark);
 816
 817         printk("%s", lvl);
 818
 819         /* dump buffer after the mark */
 820         for (offset = mark; offset < trace_shmem_base; offset += 0x8*4) {
 821                 for (word = 0; word < 8; word++)
 822                         data[word] = htonl(REG_RD(bp, offset + 4*word));
 823                 data[8] = 0x0;
 824                 pr_cont("%s", (char *)data);
 825         }
 826
 827         /* dump buffer before the mark */
 828         for (offset = addr + 4; offset <= mark; offset += 0x8*4) {
 829                 for (word = 0; word < 8; word++)
 830                         data[word] = htonl(REG_RD(bp, offset + 4*word));
 831                 data[8] = 0x0;
 832                 pr_cont("%s", (char *)data);
 833         }
 834         printk("%s" "end of fw dump\n", lvl);
 835 }
 836
 837 static void bnx2x_fw_dump(struct bnx2x *bp)
 838 {
 839         bnx2x_fw_dump_lvl(bp, KERN_ERR);
 840 }
 841
 842 static void bnx2x_hc_int_disable(struct bnx2x *bp)
 843 {
 844         int port = BP_PORT(bp);
 845         u32 addr = port ? HC_REG_CONFIG_1 : HC_REG_CONFIG_0;
 846         u32 val = REG_RD(bp, addr);
 847
 848         /* in E1 we must use only PCI configuration space to disable
 849          * MSI/MSIX capability
 850          * It's forbidden to disable IGU_PF_CONF_MSI_MSIX_EN in HC block
 851          */
 852         if (CHIP_IS_E1(bp)) {
 853                 /* Since IGU_PF_CONF_MSI_MSIX_EN still always on
 854                  * Use mask register to prevent from HC sending interrupts
 855                  * after we exit the function
 856                  */
 857                 REG_WR(bp, HC_REG_INT_MASK + port*4, 0);
 858
 859                 val &= ~(HC_CONFIG_0_REG_SINGLE_ISR_EN_0 |
 860                          HC_CONFIG_0_REG_INT_LINE_EN_0 |
 861                          HC_CONFIG_0_REG_ATTN_BIT_EN_0);
 862         } else
 863                 val &= ~(HC_CONFIG_0_REG_SINGLE_ISR_EN_0 |
 864                          HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0 |
 865                          HC_CONFIG_0_REG_INT_LINE_EN_0 |
 866                          HC_CONFIG_0_REG_ATTN_BIT_EN_0);
 867
 868         DP(NETIF_MSG_IFDOWN,
 869            "write %x to HC %d (addr 0x%x)\n",
 870            val, port, addr);
 871
 872         /* flush all outstanding writes */
 873         mmiowb();
 874
 875         REG_WR(bp, addr, val);
 876         if (REG_RD(bp, addr) != val)
 877                 BNX2X_ERR("BUG! Proper val not read from IGU!\n");
 878 }
 879
 880 static void bnx2x_igu_int_disable(struct bnx2x *bp)
 881 {
 882         u32 val = REG_RD(bp, IGU_REG_PF_CONFIGURATION);
 883
 884         val &= ~(IGU_PF_CONF_MSI_MSIX_EN |
 885                  IGU_PF_CONF_INT_LINE_EN |
 886                  IGU_PF_CONF_ATTN_BIT_EN);
 887
 888         DP(NETIF_MSG_IFDOWN, "write %x to IGU\n", val);
 889
 890         /* flush all outstanding writes */
 891         mmiowb();
 892
 893         REG_WR(bp, IGU_REG_PF_CONFIGURATION, val);
 894         if (REG_RD(bp, IGU_REG_PF_CONFIGURATION) != val)
 895                 BNX2X_ERR("BUG! Proper val not read from IGU!\n");
 896 }
 897
 898 static void bnx2x_int_disable(struct bnx2x *bp)
 899 {
 900         if (bp->common.int_block == INT_BLOCK_HC)
 901                 bnx2x_hc_int_disable(bp);
 902         else
 903                 bnx2x_igu_int_disable(bp);
 904 }
 905
 906 void bnx2x_panic_dump(struct bnx2x *bp, bool disable_int)
 907 {
 908         int i;
 909         u16 j;
 910         struct hc_sp_status_block_data sp_sb_data;
 911         int func = BP_FUNC(bp);
 912 #ifdef BNX2X_STOP_ON_ERROR
 913         u16 start = 0, end = 0;
 914         u8 cos;
 915 #endif
 916         if (IS_PF(bp) && disable_int)
 917                 bnx2x_int_disable(bp);
 918
 919         bp->stats_state = STATS_STATE_DISABLED;
 920         bp->eth_stats.unrecoverable_error++;
 921         DP(BNX2X_MSG_STATS, "stats_state - DISABLED\n");
 922
 923         BNX2X_ERR("begin crash dump -----------------\n");
 924
 925         /* Indices */
 926         /* Common */
 927         if (IS_PF(bp)) {
 928                 struct host_sp_status_block *def_sb = bp->def_status_blk;
 929                 int data_size, cstorm_offset;
 930
 931                 BNX2X_ERR("def_idx(0x%x)  def_att_idx(0x%x)  attn_state(0x%x)  spq_prod_idx(0x%x) next_stats_cnt(0x%x)\n",
 932                           bp->def_idx, bp->def_att_idx, bp->attn_state,
 933                           bp->spq_prod_idx, bp->stats_counter);
 934                 BNX2X_ERR("DSB: attn bits(0x%x)  ack(0x%x)  id(0x%x)  idx(0x%x)\n",
 935                           def_sb->atten_status_block.attn_bits,
 936                           def_sb->atten_status_block.attn_bits_ack,
 937                           def_sb->atten_status_block.status_block_id,
 938                           def_sb->atten_status_block.attn_bits_index);
 939                 BNX2X_ERR("     def (");
 940                 for (i = 0; i < HC_SP_SB_MAX_INDICES; i++)
 941                         pr_cont("0x%x%s",
 942                                 def_sb->sp_sb.index_values[i],
 943                                 (i == HC_SP_SB_MAX_INDICES - 1) ? ")  " : " ");
 944
 945                 data_size = sizeof(struct hc_sp_status_block_data) /
 946                             sizeof(u32);
 947                 cstorm_offset = CSTORM_SP_STATUS_BLOCK_DATA_OFFSET(func);
 948                 for (i = 0; i < data_size; i++)
 949                         *((u32 *)&sp_sb_data + i) =
 950                                 REG_RD(bp, BAR_CSTRORM_INTMEM + cstorm_offset +
 951                                            i * sizeof(u32));
 952
 953                 pr_cont("igu_sb_id(0x%x)  igu_seg_id(0x%x) pf_id(0x%x)  vnic_id(0x%x)  vf_id(0x%x)  vf_valid (0x%x) state(0x%x)\n",
 954                         sp_sb_data.igu_sb_id,
 955                         sp_sb_data.igu_seg_id,
 956                         sp_sb_data.p_func.pf_id,
 957                         sp_sb_data.p_func.vnic_id,
 958                         sp_sb_data.p_func.vf_id,
 959                         sp_sb_data.p_func.vf_valid,
 960                         sp_sb_data.state);
 961         }
 962
 963         for_each_eth_queue(bp, i) {
 964                 struct bnx2x_fastpath *fp = &bp->fp[i];
 965                 int loop;
 966                 struct hc_status_block_data_e2 sb_data_e2;
 967                 struct hc_status_block_data_e1x sb_data_e1x;
 968                 struct hc_status_block_sm  *hc_sm_p =
 969                         CHIP_IS_E1x(bp) ?
 970                         sb_data_e1x.common.state_machine :
 971                         sb_data_e2.common.state_machine;
 972                 struct hc_index_data *hc_index_p =
 973                         CHIP_IS_E1x(bp) ?
 974                         sb_data_e1x.index_data :
 975                         sb_data_e2.index_data;
 976                 u8 data_size, cos;
 977                 u32 *sb_data_p;
 978                 struct bnx2x_fp_txdata txdata;
 979
 980                 if (!bp->fp)
 981                         break;
 982
 983                 if (!fp->rx_cons_sb)
 984                         continue;
 985
 986                 /* Rx */
 987                 BNX2X_ERR("fp%d: rx_bd_prod(0x%x)  rx_bd_cons(0x%x)  rx_comp_prod(0x%x)  rx_comp_cons(0x%x)  *rx_cons_sb(0x%x)\n",
 988                           i, fp->rx_bd_prod, fp->rx_bd_cons,
 989                           fp->rx_comp_prod,
 990                           fp->rx_comp_cons, le16_to_cpu(*fp->rx_cons_sb));
 991                 BNX2X_ERR("     rx_sge_prod(0x%x)  last_max_sge(0x%x)  fp_hc_idx(0x%x)\n",
 992                           fp->rx_sge_prod, fp->last_max_sge,
 993                           le16_to_cpu(fp->fp_hc_idx));
 994
 995                 /* Tx */
 996                 for_each_cos_in_tx_queue(fp, cos)
 997                 {
 998                         if (!fp->txdata_ptr[cos])
 999                                 break;
1000
1001                         txdata = *fp->txdata_ptr[cos];
1002
1003                         if (!txdata.tx_cons_sb)
1004                                 continue;
1005
1006                         BNX2X_ERR("fp%d: tx_pkt_prod(0x%x)  tx_pkt_cons(0x%x)  tx_bd_prod(0x%x)  tx_bd_cons(0x%x)  *tx_cons_sb(0x%x)\n",
1007                                   i, txdata.tx_pkt_prod,
1008                                   txdata.tx_pkt_cons, txdata.tx_bd_prod,
1009                                   txdata.tx_bd_cons,
1010                                   le16_to_cpu(*txdata.tx_cons_sb));
1011                 }
1012
1013                 loop = CHIP_IS_E1x(bp) ?
1014                         HC_SB_MAX_INDICES_E1X : HC_SB_MAX_INDICES_E2;
1015
1016                 /* host sb data */
1017
1018                 if (IS_FCOE_FP(fp))
1019                         continue;
1020
1021                 BNX2X_ERR("     run indexes (");
1022                 for (j = 0; j < HC_SB_MAX_SM; j++)
1023                         pr_cont("0x%x%s",
1024                                fp->sb_running_index[j],
1025                                (j == HC_SB_MAX_SM - 1) ? ")" : " ");
1026
1027                 BNX2X_ERR("     indexes (");
1028                 for (j = 0; j < loop; j++)
1029                         pr_cont("0x%x%s",
1030                                fp->sb_index_values[j],
1031                                (j == loop - 1) ? ")" : " ");
1032
1033                 /* VF cannot access FW refelection for status block */
1034                 if (IS_VF(bp))
1035                         continue;
1036
1037                 /* fw sb data */
1038                 data_size = CHIP_IS_E1x(bp) ?
1039                         sizeof(struct hc_status_block_data_e1x) :
1040                         sizeof(struct hc_status_block_data_e2);
1041                 data_size /= sizeof(u32);
1042                 sb_data_p = CHIP_IS_E1x(bp) ?
1043                         (u32 *)&sb_data_e1x :
1044                         (u32 *)&sb_data_e2;
1045                 /* copy sb data in here */
1046                 for (j = 0; j < data_size; j++)
1047                         *(sb_data_p + j) = REG_RD(bp, BAR_CSTRORM_INTMEM +
1048                                 CSTORM_STATUS_BLOCK_DATA_OFFSET(fp->fw_sb_id) +
1049                                 j * sizeof(u32));
1050
1051                 if (!CHIP_IS_E1x(bp)) {
1052                         pr_cont("pf_id(0x%x)  vf_id(0x%x)  vf_valid(0x%x) vnic_id(0x%x)  same_igu_sb_1b(0x%x) state(0x%x)\n",
1053                                 sb_data_e2.common.p_func.pf_id,
1054                                 sb_data_e2.common.p_func.vf_id,
1055                                 sb_data_e2.common.p_func.vf_valid,
1056                                 sb_data_e2.common.p_func.vnic_id,
1057                                 sb_data_e2.common.same_igu_sb_1b,
1058                                 sb_data_e2.common.state);
1059                 } else {
1060                         pr_cont("pf_id(0x%x)  vf_id(0x%x)  vf_valid(0x%x) vnic_id(0x%x)  same_igu_sb_1b(0x%x) state(0x%x)\n",
1061                                 sb_data_e1x.common.p_func.pf_id,
1062                                 sb_data_e1x.common.p_func.vf_id,
1063                                 sb_data_e1x.common.p_func.vf_valid,
1064                                 sb_data_e1x.common.p_func.vnic_id,
1065                                 sb_data_e1x.common.same_igu_sb_1b,
1066                                 sb_data_e1x.common.state);
1067                 }
1068
1069                 /* SB_SMs data */
1070                 for (j = 0; j < HC_SB_MAX_SM; j++) {
1071                         pr_cont("SM[%d] __flags (0x%x) igu_sb_id (0x%x)  igu_seg_id(0x%x) time_to_expire (0x%x) timer_value(0x%x)\n",
1072                                 j, hc_sm_p[j].__flags,
1073                                 hc_sm_p[j].igu_sb_id,
1074                                 hc_sm_p[j].igu_seg_id,
1075                                 hc_sm_p[j].time_to_expire,
1076                                 hc_sm_p[j].timer_value);
1077                 }
1078
1079                 /* Indices data */
1080                 for (j = 0; j < loop; j++) {
1081                         pr_cont("INDEX[%d] flags (0x%x) timeout (0x%x)\n", j,
1082                                hc_index_p[j].flags,
1083                                hc_index_p[j].timeout);
1084                 }
1085         }
1086
1087 #ifdef BNX2X_STOP_ON_ERROR
1088         if (IS_PF(bp)) {
1089                 /* event queue */
1090                 BNX2X_ERR("eq cons %x prod %x\n", bp->eq_cons, bp->eq_prod);
1091                 for (i = 0; i < NUM_EQ_DESC; i++) {
1092                         u32 *data = (u32 *)&bp->eq_ring[i].message.data;
1093
1094                         BNX2X_ERR("event queue [%d]: header: opcode %d, error %d\n",
1095                                   i, bp->eq_ring[i].message.opcode,
1096                                   bp->eq_ring[i].message.error);
1097                         BNX2X_ERR("data: %x %x %x\n",
1098                                   data[0], data[1], data[2]);
1099                 }
1100         }
1101
1102         /* Rings */
1103         /* Rx */
1104         for_each_valid_rx_queue(bp, i) {
1105                 struct bnx2x_fastpath *fp = &bp->fp[i];
1106
1107                 if (!bp->fp)
1108                         break;
1109
1110                 if (!fp->rx_cons_sb)
1111                         continue;
1112
1113                 start = RX_BD(le16_to_cpu(*fp->rx_cons_sb) - 10);
1114                 end = RX_BD(le16_to_cpu(*fp->rx_cons_sb) + 503);
1115                 for (j = start; j != end; j = RX_BD(j + 1)) {
1116                         u32 *rx_bd = (u32 *)&fp->rx_desc_ring[j];
1117                         struct sw_rx_bd *sw_bd = &fp->rx_buf_ring[j];
1118
1119                         BNX2X_ERR("fp%d: rx_bd[%x]=[%x:%x]  sw_bd=[%p]\n",
1120                                   i, j, rx_bd[1], rx_bd[0], sw_bd->data);
1121                 }
1122
1123                 start = RX_SGE(fp->rx_sge_prod);
1124                 end = RX_SGE(fp->last_max_sge);
1125                 for (j = start; j != end; j = RX_SGE(j + 1)) {
1126                         u32 *rx_sge = (u32 *)&fp->rx_sge_ring[j];
1127                         struct sw_rx_page *sw_page = &fp->rx_page_ring[j];
1128
1129                         BNX2X_ERR("fp%d: rx_sge[%x]=[%x:%x]  sw_page=[%p]\n",
1130                                   i, j, rx_sge[1], rx_sge[0], sw_page->page);
1131                 }
1132
1133                 start = RCQ_BD(fp->rx_comp_cons - 10);
1134                 end = RCQ_BD(fp->rx_comp_cons + 503);
1135                 for (j = start; j != end; j = RCQ_BD(j + 1)) {
1136                         u32 *cqe = (u32 *)&fp->rx_comp_ring[j];
1137
1138                         BNX2X_ERR("fp%d: cqe[%x]=[%x:%x:%x:%x]\n",
1139                                   i, j, cqe[0], cqe[1], cqe[2], cqe[3]);
1140                 }
1141         }
1142
1143         /* Tx */
1144         for_each_valid_tx_queue(bp, i) {
1145                 struct bnx2x_fastpath *fp = &bp->fp[i];
1146
1147                 if (!bp->fp)
1148                         break;
1149
1150                 for_each_cos_in_tx_queue(fp, cos) {
1151                         struct bnx2x_fp_txdata *txdata = fp->txdata_ptr[cos];
1152
1153                         if (!fp->txdata_ptr[cos])
1154                                 break;
1155
1156                         if (!txdata->tx_cons_sb)
1157                                 continue;
1158
1159                         start = TX_BD(le16_to_cpu(*txdata->tx_cons_sb) - 10);
1160                         end = TX_BD(le16_to_cpu(*txdata->tx_cons_sb) + 245);
1161                         for (j = start; j != end; j = TX_BD(j + 1)) {
1162                                 struct sw_tx_bd *sw_bd =
1163                                         &txdata->tx_buf_ring[j];
1164
1165                                 BNX2X_ERR("fp%d: txdata %d, packet[%x]=[%p,%x]\n",
1166                                           i, cos, j, sw_bd->skb,
1167                                           sw_bd->first_bd);
1168                         }
1169
1170                         start = TX_BD(txdata->tx_bd_cons - 10);
1171                         end = TX_BD(txdata->tx_bd_cons + 254);
1172                         for (j = start; j != end; j = TX_BD(j + 1)) {
1173                                 u32 *tx_bd = (u32 *)&txdata->tx_desc_ring[j];
1174
1175                                 BNX2X_ERR("fp%d: txdata %d, tx_bd[%x]=[%x:%x:%x:%x]\n",
1176                                           i, cos, j, tx_bd[0], tx_bd[1],
1177                                           tx_bd[2], tx_bd[3]);
1178                         }
1179                 }
1180         }
1181 #endif
1182         if (IS_PF(bp)) {
1183                 bnx2x_fw_dump(bp);
1184                 bnx2x_mc_assert(bp);
1185         }
1186         BNX2X_ERR("end crash dump -----------------\n");
1187 }
1188
1189 /*
1190  * FLR Support for E2
1191  *
1192  * bnx2x_pf_flr_clnup() is called during nic_load in the per function HW
1193  * initialization.
1194  */
1195 #define FLR_WAIT_USEC           10000   /* 10 milliseconds */
1196 #define FLR_WAIT_INTERVAL       50      /* usec */
1197 #define FLR_POLL_CNT            (FLR_WAIT_USEC/FLR_WAIT_INTERVAL) /* 200 */
1198
1199 struct pbf_pN_buf_regs {
1200         int pN;
1201         u32 init_crd;
1202         u32 crd;
1203         u32 crd_freed;
1204 };
1205
1206 struct pbf_pN_cmd_regs {
1207         int pN;
1208         u32 lines_occup;
1209         u32 lines_freed;
1210 };
1211
1212 static void bnx2x_pbf_pN_buf_flushed(struct bnx2x *bp,
1213                                      struct pbf_pN_buf_regs *regs,
1214                                      u32 poll_count)
1215 {
1216         u32 init_crd, crd, crd_start, crd_freed, crd_freed_start;
1217         u32 cur_cnt = poll_count;
1218
1219         crd_freed = crd_freed_start = REG_RD(bp, regs->crd_freed);
1220         crd = crd_start = REG_RD(bp, regs->crd);
1221         init_crd = REG_RD(bp, regs->init_crd);
1222
1223         DP(BNX2X_MSG_SP, "INIT CREDIT[%d] : %x\n", regs->pN, init_crd);
1224         DP(BNX2X_MSG_SP, "CREDIT[%d]      : s:%x\n", regs->pN, crd);
1225         DP(BNX2X_MSG_SP, "CREDIT_FREED[%d]: s:%x\n", regs->pN, crd_freed);
1226
1227         while ((crd != init_crd) && ((u32)SUB_S32(crd_freed, crd_freed_start) <
1228                (init_crd - crd_start))) {
1229                 if (cur_cnt--) {
1230                         udelay(FLR_WAIT_INTERVAL);
1231                         crd = REG_RD(bp, regs->crd);
1232                         crd_freed = REG_RD(bp, regs->crd_freed);
1233                 } else {
1234                         DP(BNX2X_MSG_SP, "PBF tx buffer[%d] timed out\n",
1235                            regs->pN);
1236                         DP(BNX2X_MSG_SP, "CREDIT[%d]      : c:%x\n",
1237                            regs->pN, crd);
1238                         DP(BNX2X_MSG_SP, "CREDIT_FREED[%d]: c:%x\n",
1239                            regs->pN, crd_freed);
1240                         break;
1241                 }
1242         }
1243         DP(BNX2X_MSG_SP, "Waited %d*%d usec for PBF tx buffer[%d]\n",
1244            poll_count-cur_cnt, FLR_WAIT_INTERVAL, regs->pN);
1245 }
1246
1247 static void bnx2x_pbf_pN_cmd_flushed(struct bnx2x *bp,
1248                                      struct pbf_pN_cmd_regs *regs,
1249                                      u32 poll_count)
1250 {
1251         u32 occup, to_free, freed, freed_start;
1252         u32 cur_cnt = poll_count;
1253
1254         occup = to_free = REG_RD(bp, regs->lines_occup);
1255         freed = freed_start = REG_RD(bp, regs->lines_freed);
1256
1257         DP(BNX2X_MSG_SP, "OCCUPANCY[%d]   : s:%x\n", regs->pN, occup);
1258         DP(BNX2X_MSG_SP, "LINES_FREED[%d] : s:%x\n", regs->pN, freed);
1259
1260         while (occup && ((u32)SUB_S32(freed, freed_start) < to_free)) {
1261                 if (cur_cnt--) {
1262                         udelay(FLR_WAIT_INTERVAL);
1263                         occup = REG_RD(bp, regs->lines_occup);
1264                         freed = REG_RD(bp, regs->lines_freed);
1265                 } else {
1266                         DP(BNX2X_MSG_SP, "PBF cmd queue[%d] timed out\n",
1267                            regs->pN);
1268                         DP(BNX2X_MSG_SP, "OCCUPANCY[%d]   : s:%x\n",
1269                            regs->pN, occup);
1270                         DP(BNX2X_MSG_SP, "LINES_FREED[%d] : s:%x\n",
1271                            regs->pN, freed);
1272                         break;
1273                 }
1274         }
1275         DP(BNX2X_MSG_SP, "Waited %d*%d usec for PBF cmd queue[%d]\n",
1276            poll_count-cur_cnt, FLR_WAIT_INTERVAL, regs->pN);
1277 }
1278
1279 static u32 bnx2x_flr_clnup_reg_poll(struct bnx2x *bp, u32 reg,
1280                                     u32 expected, u32 poll_count)
1281 {
1282         u32 cur_cnt = poll_count;
1283         u32 val;
1284
1285         while ((val = REG_RD(bp, reg)) != expected && cur_cnt--)
1286                 udelay(FLR_WAIT_INTERVAL);
1287
1288         return val;
1289 }
1290
1291 int bnx2x_flr_clnup_poll_hw_counter(struct bnx2x *bp, u32 reg,
1292                                     char *msg, u32 poll_cnt)
1293 {
1294         u32 val = bnx2x_flr_clnup_reg_poll(bp, reg, 0, poll_cnt);
1295         if (val != 0) {
1296                 BNX2X_ERR("%s usage count=%d\n", msg, val);
1297                 return 1;
1298         }
1299         return 0;
1300 }
1301
1302 /* Common routines with VF FLR cleanup */
1303 u32 bnx2x_flr_clnup_poll_count(struct bnx2x *bp)
1304 {
1305         /* adjust polling timeout */
1306         if (CHIP_REV_IS_EMUL(bp))
1307                 return FLR_POLL_CNT * 2000;
1308
1309         if (CHIP_REV_IS_FPGA(bp))
1310                 return FLR_POLL_CNT * 120;
1311
1312         return FLR_POLL_CNT;
1313 }
1314
1315 void bnx2x_tx_hw_flushed(struct bnx2x *bp, u32 poll_count)
1316 {
1317         struct pbf_pN_cmd_regs cmd_regs[] = {
1318                 {0, (CHIP_IS_E3B0(bp)) ?
1319                         PBF_REG_TQ_OCCUPANCY_Q0 :
1320                         PBF_REG_P0_TQ_OCCUPANCY,
1321                     (CHIP_IS_E3B0(bp)) ?
1322                         PBF_REG_TQ_LINES_FREED_CNT_Q0 :
1323                         PBF_REG_P0_TQ_LINES_FREED_CNT},
1324                 {1, (CHIP_IS_E3B0(bp)) ?
1325                         PBF_REG_TQ_OCCUPANCY_Q1 :
1326                         PBF_REG_P1_TQ_OCCUPANCY,
1327                     (CHIP_IS_E3B0(bp)) ?
1328                         PBF_REG_TQ_LINES_FREED_CNT_Q1 :
1329                         PBF_REG_P1_TQ_LINES_FREED_CNT},
1330                 {4, (CHIP_IS_E3B0(bp)) ?
1331                         PBF_REG_TQ_OCCUPANCY_LB_Q :
1332                         PBF_REG_P4_TQ_OCCUPANCY,
1333                     (CHIP_IS_E3B0(bp)) ?
1334                         PBF_REG_TQ_LINES_FREED_CNT_LB_Q :
1335                         PBF_REG_P4_TQ_LINES_FREED_CNT}
1336         };
1337
1338         struct pbf_pN_buf_regs buf_regs[] = {
1339                 {0, (CHIP_IS_E3B0(bp)) ?
1340                         PBF_REG_INIT_CRD_Q0 :
1341                         PBF_REG_P0_INIT_CRD ,
1342                     (CHIP_IS_E3B0(bp)) ?
1343                         PBF_REG_CREDIT_Q0 :
1344                         PBF_REG_P0_CREDIT,
1345                     (CHIP_IS_E3B0(bp)) ?
1346                         PBF_REG_INTERNAL_CRD_FREED_CNT_Q0 :
1347                         PBF_REG_P0_INTERNAL_CRD_FREED_CNT},
1348                 {1, (CHIP_IS_E3B0(bp)) ?
1349                         PBF_REG_INIT_CRD_Q1 :
1350                         PBF_REG_P1_INIT_CRD,
1351                     (CHIP_IS_E3B0(bp)) ?
1352                         PBF_REG_CREDIT_Q1 :
1353                         PBF_REG_P1_CREDIT,
1354                     (CHIP_IS_E3B0(bp)) ?
1355                         PBF_REG_INTERNAL_CRD_FREED_CNT_Q1 :
1356                         PBF_REG_P1_INTERNAL_CRD_FREED_CNT},
1357                 {4, (CHIP_IS_E3B0(bp)) ?
1358                         PBF_REG_INIT_CRD_LB_Q :
1359                         PBF_REG_P4_INIT_CRD,
1360                     (CHIP_IS_E3B0(bp)) ?
1361                         PBF_REG_CREDIT_LB_Q :
1362                         PBF_REG_P4_CREDIT,
1363                     (CHIP_IS_E3B0(bp)) ?
1364                         PBF_REG_INTERNAL_CRD_FREED_CNT_LB_Q :
1365                         PBF_REG_P4_INTERNAL_CRD_FREED_CNT},
1366         };
1367
1368         int i;
1369
1370         /* Verify the command queues are flushed P0, P1, P4 */
1371         for (i = 0; i < ARRAY_SIZE(cmd_regs); i++)
1372                 bnx2x_pbf_pN_cmd_flushed(bp, &cmd_regs[i], poll_count);
1373
1374         /* Verify the transmission buffers are flushed P0, P1, P4 */
1375         for (i = 0; i < ARRAY_SIZE(buf_regs); i++)
1376                 bnx2x_pbf_pN_buf_flushed(bp, &buf_regs[i], poll_count);
1377 }
1378
1379 #define OP_GEN_PARAM(param) \
1380         (((param) << SDM_OP_GEN_COMP_PARAM_SHIFT) & SDM_OP_GEN_COMP_PARAM)
1381
1382 #define OP_GEN_TYPE(type) \
1383         (((type) << SDM_OP_GEN_COMP_TYPE_SHIFT) & SDM_OP_GEN_COMP_TYPE)
1384
1385 #define OP_GEN_AGG_VECT(index) \
1386         (((index) << SDM_OP_GEN_AGG_VECT_IDX_SHIFT) & SDM_OP_GEN_AGG_VECT_IDX)
1387
1388 int bnx2x_send_final_clnup(struct bnx2x *bp, u8 clnup_func, u32 poll_cnt)
1389 {
1390         u32 op_gen_command = 0;
1391         u32 comp_addr = BAR_CSTRORM_INTMEM +
1392                         CSTORM_FINAL_CLEANUP_COMPLETE_OFFSET(clnup_func);
1393         int ret = 0;
1394
1395         if (REG_RD(bp, comp_addr)) {
1396                 BNX2X_ERR("Cleanup complete was not 0 before sending\n");
1397                 return 1;
1398         }
1399
1400         op_gen_command |= OP_GEN_PARAM(XSTORM_AGG_INT_FINAL_CLEANUP_INDEX);
1401         op_gen_command |= OP_GEN_TYPE(XSTORM_AGG_INT_FINAL_CLEANUP_COMP_TYPE);
1402         op_gen_command |= OP_GEN_AGG_VECT(clnup_func);
1403         op_gen_command |= 1 << SDM_OP_GEN_AGG_VECT_IDX_VALID_SHIFT;
1404
1405         DP(BNX2X_MSG_SP, "sending FW Final cleanup\n");
1406         REG_WR(bp, XSDM_REG_OPERATION_GEN, op_gen_command);
1407
1408         if (bnx2x_flr_clnup_reg_poll(bp, comp_addr, 1, poll_cnt) != 1) {
1409                 BNX2X_ERR("FW final cleanup did not succeed\n");
1410                 DP(BNX2X_MSG_SP, "At timeout completion address contained %x\n",
1411                    (REG_RD(bp, comp_addr)));
1412                 bnx2x_panic();
1413                 return 1;
1414         }
1415         /* Zero completion for next FLR */
1416         REG_WR(bp, comp_addr, 0);
1417
1418         return ret;
1419 }
1420
1421 u8 bnx2x_is_pcie_pending(struct pci_dev *dev)
1422 {
1423         u16 status;
1424
1425         pcie_capability_read_word(dev, PCI_EXP_DEVSTA, &status);
1426         return status & PCI_EXP_DEVSTA_TRPND;
1427 }
1428
1429 /* PF FLR specific routines
1430 */
1431 static int bnx2x_poll_hw_usage_counters(struct bnx2x *bp, u32 poll_cnt)
1432 {
1433         /* wait for CFC PF usage-counter to zero (includes all the VFs) */
1434         if (bnx2x_flr_clnup_poll_hw_counter(bp,
1435                         CFC_REG_NUM_LCIDS_INSIDE_PF,
1436                         "CFC PF usage counter timed out",
1437                         poll_cnt))
1438                 return 1;
1439
1440         /* Wait for DQ PF usage-counter to zero (until DQ cleanup) */
1441         if (bnx2x_flr_clnup_poll_hw_counter(bp,
1442                         DORQ_REG_PF_USAGE_CNT,
1443                         "DQ PF usage counter timed out",
1444                         poll_cnt))
1445                 return 1;
1446
1447         /* Wait for QM PF usage-counter to zero (until DQ cleanup) */
1448         if (bnx2x_flr_clnup_poll_hw_counter(bp,
1449                         QM_REG_PF_USG_CNT_0 + 4*BP_FUNC(bp),
1450                         "QM PF usage counter timed out",
1451                         poll_cnt))
1452                 return 1;
1453
1454         /* Wait for Timer PF usage-counters to zero (until DQ cleanup) */
1455         if (bnx2x_flr_clnup_poll_hw_counter(bp,
1456                         TM_REG_LIN0_VNIC_UC + 4*BP_PORT(bp),
1457                         "Timers VNIC usage counter timed out",
1458                         poll_cnt))
1459                 return 1;
1460         if (bnx2x_flr_clnup_poll_hw_counter(bp,
1461                         TM_REG_LIN0_NUM_SCANS + 4*BP_PORT(bp),
1462                         "Timers NUM_SCANS usage counter timed out",
1463                         poll_cnt))
1464                 return 1;
1465
1466         /* Wait DMAE PF usage counter to zero */
1467         if (bnx2x_flr_clnup_poll_hw_counter(bp,
1468                         dmae_reg_go_c[INIT_DMAE_C(bp)],
1469                         "DMAE command register timed out",
1470                         poll_cnt))
1471                 return 1;
1472
1473         return 0;
1474 }
1475
1476 static void bnx2x_hw_enable_status(struct bnx2x *bp)
1477 {
1478         u32 val;
1479
1480         val = REG_RD(bp, CFC_REG_WEAK_ENABLE_PF);
1481         DP(BNX2X_MSG_SP, "CFC_REG_WEAK_ENABLE_PF is 0x%x\n", val);
1482
1483         val = REG_RD(bp, PBF_REG_DISABLE_PF);
1484         DP(BNX2X_MSG_SP, "PBF_REG_DISABLE_PF is 0x%x\n", val);
1485
1486         val = REG_RD(bp, IGU_REG_PCI_PF_MSI_EN);
1487         DP(BNX2X_MSG_SP, "IGU_REG_PCI_PF_MSI_EN is 0x%x\n", val);
1488
1489         val = REG_RD(bp, IGU_REG_PCI_PF_MSIX_EN);
1490         DP(BNX2X_MSG_SP, "IGU_REG_PCI_PF_MSIX_EN is 0x%x\n", val);
1491
1492         val = REG_RD(bp, IGU_REG_PCI_PF_MSIX_FUNC_MASK);
1493         DP(BNX2X_MSG_SP, "IGU_REG_PCI_PF_MSIX_FUNC_MASK is 0x%x\n", val);
1494
1495         val = REG_RD(bp, PGLUE_B_REG_SHADOW_BME_PF_7_0_CLR);
1496         DP(BNX2X_MSG_SP, "PGLUE_B_REG_SHADOW_BME_PF_7_0_CLR is 0x%x\n", val);
1497
1498         val = REG_RD(bp, PGLUE_B_REG_FLR_REQUEST_PF_7_0_CLR);
1499         DP(BNX2X_MSG_SP, "PGLUE_B_REG_FLR_REQUEST_PF_7_0_CLR is 0x%x\n", val);
1500
1501         val = REG_RD(bp, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER);
1502         DP(BNX2X_MSG_SP, "PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER is 0x%x\n",
1503            val);
1504 }
1505
1506 static int bnx2x_pf_flr_clnup(struct bnx2x *bp)
1507 {
1508         u32 poll_cnt = bnx2x_flr_clnup_poll_count(bp);
1509
1510         DP(BNX2X_MSG_SP, "Cleanup after FLR PF[%d]\n", BP_ABS_FUNC(bp));
1511
1512         /* Re-enable PF target read access */
1513         REG_WR(bp, PGLUE_B_REG_INTERNAL_PFID_ENABLE_TARGET_READ, 1);
1514
1515         /* Poll HW usage counters */
1516         DP(BNX2X_MSG_SP, "Polling usage counters\n");
1517         if (bnx2x_poll_hw_usage_counters(bp, poll_cnt))
1518                 return -EBUSY;
1519
1520         /* Zero the igu 'trailing edge' and 'leading edge' */
1521
1522         /* Send the FW cleanup command */
1523         if (bnx2x_send_final_clnup(bp, (u8)BP_FUNC(bp), poll_cnt))
1524                 return -EBUSY;
1525
1526         /* ATC cleanup */
1527
1528         /* Verify TX hw is flushed */
1529         bnx2x_tx_hw_flushed(bp, poll_cnt);
1530
1531         /* Wait 100ms (not adjusted according to platform) */
1532         msleep(100);
1533
1534         /* Verify no pending pci transactions */
1535         if (bnx2x_is_pcie_pending(bp->pdev))
1536                 BNX2X_ERR("PCIE Transactions still pending\n");
1537
1538         /* Debug */
1539         bnx2x_hw_enable_status(bp);
1540
1541         /*
1542          * Master enable - Due to WB DMAE writes performed before this
1543          * register is re-initialized as part of the regular function init
1544          */
1545         REG_WR(bp, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, 1);
1546
1547         return 0;
1548 }
1549
1550 static void bnx2x_hc_int_enable(struct bnx2x *bp)
1551 {
1552         int port = BP_PORT(bp);
1553         u32 addr = port ? HC_REG_CONFIG_1 : HC_REG_CONFIG_0;
1554         u32 val = REG_RD(bp, addr);
1555         bool msix = (bp->flags & USING_MSIX_FLAG) ? true : false;
1556         bool single_msix = (bp->flags & USING_SINGLE_MSIX_FLAG) ? true : false;
1557         bool msi = (bp->flags & USING_MSI_FLAG) ? true : false;
1558
1559         if (msix) {
1560                 val &= ~(HC_CONFIG_0_REG_SINGLE_ISR_EN_0 |
1561                          HC_CONFIG_0_REG_INT_LINE_EN_0);
1562                 val |= (HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0 |
1563                         HC_CONFIG_0_REG_ATTN_BIT_EN_0);
1564                 if (single_msix)
1565                         val |= HC_CONFIG_0_REG_SINGLE_ISR_EN_0;
1566         } else if (msi) {
1567                 val &= ~HC_CONFIG_0_REG_INT_LINE_EN_0;
1568                 val |= (HC_CONFIG_0_REG_SINGLE_ISR_EN_0 |
1569                         HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0 |
1570                         HC_CONFIG_0_REG_ATTN_BIT_EN_0);
1571         } else {
1572                 val |= (HC_CONFIG_0_REG_SINGLE_ISR_EN_0 |
1573                         HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0 |
1574                         HC_CONFIG_0_REG_INT_LINE_EN_0 |
1575                         HC_CONFIG_0_REG_ATTN_BIT_EN_0);
1576
1577                 if (!CHIP_IS_E1(bp)) {
1578                         DP(NETIF_MSG_IFUP,
1579                            "write %x to HC %d (addr 0x%x)\n", val, port, addr);
1580
1581                         REG_WR(bp, addr, val);
1582
1583                         val &= ~HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0;
1584                 }
1585         }
1586
1587         if (CHIP_IS_E1(bp))
1588                 REG_WR(bp, HC_REG_INT_MASK + port*4, 0x1FFFF);
1589
1590         DP(NETIF_MSG_IFUP,
1591            "write %x to HC %d (addr 0x%x) mode %s\n", val, port, addr,
1592            (msix ? "MSI-X" : (msi ? "MSI" : "INTx")));
1593
1594         REG_WR(bp, addr, val);
1595         /*
1596          * Ensure that HC_CONFIG is written before leading/trailing edge config
1597          */
1598         mmiowb();
1599         barrier();
1600
1601         if (!CHIP_IS_E1(bp)) {
1602                 /* init leading/trailing edge */
1603                 if (IS_MF(bp)) {
1604                         val = (0xee0f | (1 << (BP_VN(bp) + 4)));
1605                         if (bp->port.pmf)
1606                                 /* enable nig and gpio3 attention */
1607                                 val |= 0x1100;
1608                 } else
1609                         val = 0xffff;
1610
1611                 REG_WR(bp, HC_REG_TRAILING_EDGE_0 + port*8, val);
1612                 REG_WR(bp, HC_REG_LEADING_EDGE_0 + port*8, val);
1613         }
1614
1615         /* Make sure that interrupts are indeed enabled from here on */
1616         mmiowb();
1617 }
1618
1619 static void bnx2x_igu_int_enable(struct bnx2x *bp)
1620 {
1621         u32 val;
1622         bool msix = (bp->flags & USING_MSIX_FLAG) ? true : false;
1623         bool single_msix = (bp->flags & USING_SINGLE_MSIX_FLAG) ? true : false;
1624         bool msi = (bp->flags & USING_MSI_FLAG) ? true : false;
1625
1626         val = REG_RD(bp, IGU_REG_PF_CONFIGURATION);
1627
1628         if (msix) {
1629                 val &= ~(IGU_PF_CONF_INT_LINE_EN |
1630                          IGU_PF_CONF_SINGLE_ISR_EN);
1631                 val |= (IGU_PF_CONF_MSI_MSIX_EN |
1632                         IGU_PF_CONF_ATTN_BIT_EN);
1633
1634                 if (single_msix)
1635                         val |= IGU_PF_CONF_SINGLE_ISR_EN;
1636         } else if (msi) {
1637                 val &= ~IGU_PF_CONF_INT_LINE_EN;
1638                 val |= (IGU_PF_CONF_MSI_MSIX_EN |
1639                         IGU_PF_CONF_ATTN_BIT_EN |
1640                         IGU_PF_CONF_SINGLE_ISR_EN);
1641         } else {
1642                 val &= ~IGU_PF_CONF_MSI_MSIX_EN;
1643                 val |= (IGU_PF_CONF_INT_LINE_EN |
1644                         IGU_PF_CONF_ATTN_BIT_EN |
1645                         IGU_PF_CONF_SINGLE_ISR_EN);
1646         }
1647
1648         /* Clean previous status - need to configure igu prior to ack*/
1649         if ((!msix) || single_msix) {
1650                 REG_WR(bp, IGU_REG_PF_CONFIGURATION, val);
1651                 bnx2x_ack_int(bp);
1652         }
1653
1654         val |= IGU_PF_CONF_FUNC_EN;
1655
1656         DP(NETIF_MSG_IFUP, "write 0x%x to IGU  mode %s\n",
1657            val, (msix ? "MSI-X" : (msi ? "MSI" : "INTx")));
1658
1659         REG_WR(bp, IGU_REG_PF_CONFIGURATION, val);
1660
1661         if (val & IGU_PF_CONF_INT_LINE_EN)
1662                 pci_intx(bp->pdev, true);
1663
1664         barrier();
1665
1666         /* init leading/trailing edge */
1667         if (IS_MF(bp)) {
1668                 val = (0xee0f | (1 << (BP_VN(bp) + 4)));
1669                 if (bp->port.pmf)
1670                         /* enable nig and gpio3 attention */
1671                         val |= 0x1100;
1672         } else
1673                 val = 0xffff;
1674
1675         REG_WR(bp, IGU_REG_TRAILING_EDGE_LATCH, val);
1676         REG_WR(bp, IGU_REG_LEADING_EDGE_LATCH, val);
1677
1678         /* Make sure that interrupts are indeed enabled from here on */
1679         mmiowb();
1680 }
1681
1682 void bnx2x_int_enable(struct bnx2x *bp)
1683 {
1684         if (bp->common.int_block == INT_BLOCK_HC)
1685                 bnx2x_hc_int_enable(bp);
1686         else
1687                 bnx2x_igu_int_enable(bp);
1688 }
1689
1690 void bnx2x_int_disable_sync(struct bnx2x *bp, int disable_hw)
1691 {
1692         int msix = (bp->flags & USING_MSIX_FLAG) ? 1 : 0;
1693         int i, offset;
1694
1695         if (disable_hw)
1696                 /* prevent the HW from sending interrupts */
1697                 bnx2x_int_disable(bp);
1698
1699         /* make sure all ISRs are done */
1700         if (msix) {
1701                 synchronize_irq(bp->msix_table[0].vector);
1702                 offset = 1;
1703                 if (CNIC_SUPPORT(bp))
1704                         offset++;
1705                 for_each_eth_queue(bp, i)
1706                         synchronize_irq(bp->msix_table[offset++].vector);
1707         } else
1708                 synchronize_irq(bp->pdev->irq);
1709
1710         /* make sure sp_task is not running */
1711         cancel_delayed_work(&bp->sp_task);
1712         cancel_delayed_work(&bp->period_task);
1713         flush_workqueue(bnx2x_wq);
1714 }
1715
1716 /* fast path */
1717
1718 /*
1719  * General service functions
1720  */
1721
1722 /* Return true if succeeded to acquire the lock */
1723 static bool bnx2x_trylock_hw_lock(struct bnx2x *bp, u32 resource)
1724 {
1725         u32 lock_status;
1726         u32 resource_bit = (1 << resource);
1727         int func = BP_FUNC(bp);
1728         u32 hw_lock_control_reg;
1729
1730         DP(NETIF_MSG_HW | NETIF_MSG_IFUP,
1731            "Trying to take a lock on resource %d\n", resource);
1732
1733         /* Validating that the resource is within range */
1734         if (resource > HW_LOCK_MAX_RESOURCE_VALUE) {
1735                 DP(NETIF_MSG_HW | NETIF_MSG_IFUP,
1736                    "resource(0x%x) > HW_LOCK_MAX_RESOURCE_VALUE(0x%x)\n",
1737                    resource, HW_LOCK_MAX_RESOURCE_VALUE);
1738                 return false;
1739         }
1740
1741         if (func <= 5)
1742                 hw_lock_control_reg = (MISC_REG_DRIVER_CONTROL_1 + func*8);
1743         else
1744                 hw_lock_control_reg =
1745                                 (MISC_REG_DRIVER_CONTROL_7 + (func - 6)*8);
1746
1747         /* Try to acquire the lock */
1748         REG_WR(bp, hw_lock_control_reg + 4, resource_bit);
1749         lock_status = REG_RD(bp, hw_lock_control_reg);
1750         if (lock_status & resource_bit)
1751                 return true;
1752
1753         DP(NETIF_MSG_HW | NETIF_MSG_IFUP,
1754            "Failed to get a lock on resource %d\n", resource);
1755         return false;
1756 }
1757
1758 /**
1759  * bnx2x_get_leader_lock_resource - get the recovery leader resource id
1760  *
1761  * @bp: driver handle
1762  *
1763  * Returns the recovery leader resource id according to the engine this function
1764  * belongs to. Currently only only 2 engines is supported.
1765  */
1766 static int bnx2x_get_leader_lock_resource(struct bnx2x *bp)
1767 {
1768         if (BP_PATH(bp))
1769                 return HW_LOCK_RESOURCE_RECOVERY_LEADER_1;
1770         else
1771                 return HW_LOCK_RESOURCE_RECOVERY_LEADER_0;
1772 }
1773
1774 /**
1775  * bnx2x_trylock_leader_lock- try to acquire a leader lock.
1776  *
1777  * @bp: driver handle
1778  *
1779  * Tries to acquire a leader lock for current engine.
1780  */
1781 static bool bnx2x_trylock_leader_lock(struct bnx2x *bp)
1782 {
1783         return bnx2x_trylock_hw_lock(bp, bnx2x_get_leader_lock_resource(bp));
1784 }
1785
1786 static void bnx2x_cnic_cfc_comp(struct bnx2x *bp, int cid, u8 err);
1787
1788 /* schedule the sp task and mark that interrupt occurred (runs from ISR) */
1789 static int bnx2x_schedule_sp_task(struct bnx2x *bp)
1790 {
1791         /* Set the interrupt occurred bit for the sp-task to recognize it
1792          * must ack the interrupt and transition according to the IGU
1793          * state machine.
1794          */
1795         atomic_set(&bp->interrupt_occurred, 1);
1796
1797         /* The sp_task must execute only after this bit
1798          * is set, otherwise we will get out of sync and miss all
1799          * further interrupts. Hence, the barrier.
1800          */
1801         smp_wmb();
1802
1803         /* schedule sp_task to workqueue */
1804         return queue_delayed_work(bnx2x_wq, &bp->sp_task, 0);
1805 }
1806
1807 void bnx2x_sp_event(struct bnx2x_fastpath *fp, union eth_rx_cqe *rr_cqe)
1808 {
1809         struct bnx2x *bp = fp->bp;
1810         int cid = SW_CID(rr_cqe->ramrod_cqe.conn_and_cmd_data);
1811         int command = CQE_CMD(rr_cqe->ramrod_cqe.conn_and_cmd_data);
1812         enum bnx2x_queue_cmd drv_cmd = BNX2X_Q_CMD_MAX;
1813         struct bnx2x_queue_sp_obj *q_obj = &bnx2x_sp_obj(bp, fp).q_obj;
1814
1815         DP(BNX2X_MSG_SP,
1816            "fp %d  cid %d  got ramrod #%d  state is %x  type is %d\n",
1817            fp->index, cid, command, bp->state,
1818            rr_cqe->ramrod_cqe.ramrod_type);
1819
1820         /* If cid is within VF range, replace the slowpath object with the
1821          * one corresponding to this VF
1822          */
1823         if (cid >= BNX2X_FIRST_VF_CID  &&
1824             cid < BNX2X_FIRST_VF_CID + BNX2X_VF_CIDS)
1825                 bnx2x_iov_set_queue_sp_obj(bp, cid, &q_obj);
1826
1827         switch (command) {
1828         case (RAMROD_CMD_ID_ETH_CLIENT_UPDATE):
1829                 DP(BNX2X_MSG_SP, "got UPDATE ramrod. CID %d\n", cid);
1830                 drv_cmd = BNX2X_Q_CMD_UPDATE;
1831                 break;
1832
1833         case (RAMROD_CMD_ID_ETH_CLIENT_SETUP):
1834                 DP(BNX2X_MSG_SP, "got MULTI[%d] setup ramrod\n", cid);
1835                 drv_cmd = BNX2X_Q_CMD_SETUP;
1836                 break;
1837
1838         case (RAMROD_CMD_ID_ETH_TX_QUEUE_SETUP):
1839                 DP(BNX2X_MSG_SP, "got MULTI[%d] tx-only setup ramrod\n", cid);
1840                 drv_cmd = BNX2X_Q_CMD_SETUP_TX_ONLY;
1841                 break;
1842
1843         case (RAMROD_CMD_ID_ETH_HALT):
1844                 DP(BNX2X_MSG_SP, "got MULTI[%d] halt ramrod\n", cid);
1845                 drv_cmd = BNX2X_Q_CMD_HALT;
1846                 break;
1847
1848         case (RAMROD_CMD_ID_ETH_TERMINATE):
1849                 DP(BNX2X_MSG_SP, "got MULTI[%d] terminate ramrod\n", cid);
1850                 drv_cmd = BNX2X_Q_CMD_TERMINATE;
1851                 break;
1852
1853         case (RAMROD_CMD_ID_ETH_EMPTY):
1854                 DP(BNX2X_MSG_SP, "got MULTI[%d] empty ramrod\n", cid);
1855                 drv_cmd = BNX2X_Q_CMD_EMPTY;
1856                 break;
1857
1858         case (RAMROD_CMD_ID_ETH_TPA_UPDATE):
1859                 DP(BNX2X_MSG_SP, "got tpa update ramrod CID=%d\n", cid);
1860                 drv_cmd = BNX2X_Q_CMD_UPDATE_TPA;
1861                 break;
1862
1863         default:
1864                 BNX2X_ERR("unexpected MC reply (%d) on fp[%d]\n",
1865                           command, fp->index);
1866                 return;
1867         }
1868
1869         if ((drv_cmd != BNX2X_Q_CMD_MAX) &&
1870             q_obj->complete_cmd(bp, q_obj, drv_cmd))
1871                 /* q_obj->complete_cmd() failure means that this was
1872                  * an unexpected completion.
1873                  *
1874                  * In this case we don't want to increase the bp->spq_left
1875                  * because apparently we haven't sent this command the first
1876                  * place.
1877                  */
1878 #ifdef BNX2X_STOP_ON_ERROR
1879                 bnx2x_panic();
1880 #else
1881                 return;
1882 #endif
1883
1884         smp_mb__before_atomic();
1885         atomic_inc(&bp->cq_spq_left);
1886         /* push the change in bp->spq_left and towards the memory */
1887         smp_mb__after_atomic();
1888
1889         DP(BNX2X_MSG_SP, "bp->cq_spq_left %x\n", atomic_read(&bp->cq_spq_left));
1890
1891         if ((drv_cmd == BNX2X_Q_CMD_UPDATE) && (IS_FCOE_FP(fp)) &&
1892             (!!test_bit(BNX2X_AFEX_FCOE_Q_UPDATE_PENDING, &bp->sp_state))) {
1893                 /* if Q update ramrod is completed for last Q in AFEX vif set
1894                  * flow, then ACK MCP at the end
1895                  *
1896                  * mark pending ACK to MCP bit.
1897                  * prevent case that both bits are cleared.
1898                  * At the end of load/unload driver checks that
1899                  * sp_state is cleared, and this order prevents
1900                  * races
1901                  */
1902                 smp_mb__before_atomic();
1903                 set_bit(BNX2X_AFEX_PENDING_VIFSET_MCP_ACK, &bp->sp_state);
1904                 wmb();
1905                 clear_bit(BNX2X_AFEX_FCOE_Q_UPDATE_PENDING, &bp->sp_state);
1906                 smp_mb__after_atomic();
1907
1908                 /* schedule the sp task as mcp ack is required */
1909                 bnx2x_schedule_sp_task(bp);
1910         }
1911
1912         return;
1913 }
1914
1915 irqreturn_t bnx2x_interrupt(int irq, void *dev_instance)
1916 {
1917         struct bnx2x *bp = netdev_priv(dev_instance);
1918         u16 status = bnx2x_ack_int(bp);
1919         u16 mask;
1920         int i;
1921         u8 cos;
1922
1923         /* Return here if interrupt is shared and it's not for us */
1924         if (unlikely(status == 0)) {
1925                 DP(NETIF_MSG_INTR, "not our interrupt!\n");
1926                 return IRQ_NONE;
1927         }
1928         DP(NETIF_MSG_INTR, "got an interrupt  status 0x%x\n", status);
1929
1930 #ifdef BNX2X_STOP_ON_ERROR
1931         if (unlikely(bp->panic))
1932                 return IRQ_HANDLED;
1933 #endif
1934
1935         for_each_eth_queue(bp, i) {
1936                 struct bnx2x_fastpath *fp = &bp->fp[i];
1937
1938                 mask = 0x2 << (fp->index + CNIC_SUPPORT(bp));
1939                 if (status & mask) {
1940                         /* Handle Rx or Tx according to SB id */
1941                         for_each_cos_in_tx_queue(fp, cos)
1942                                 prefetch(fp->txdata_ptr[cos]->tx_cons_sb);
1943                         prefetch(&fp->sb_running_index[SM_RX_ID]);
1944                         napi_schedule_irqoff(&bnx2x_fp(bp, fp->index, napi));
1945                         status &= ~mask;
1946                 }
1947         }
1948
1949         if (CNIC_SUPPORT(bp)) {
1950                 mask = 0x2;
1951                 if (status & (mask | 0x1)) {
1952                         struct cnic_ops *c_ops = NULL;
1953
1954                         rcu_read_lock();
1955                         c_ops = rcu_dereference(bp->cnic_ops);
1956                         if (c_ops && (bp->cnic_eth_dev.drv_state &
1957                                       CNIC_DRV_STATE_HANDLES_IRQ))
1958                                 c_ops->cnic_handler(bp->cnic_data, NULL);
1959                         rcu_read_unlock();
1960
1961                         status &= ~mask;
1962                 }
1963         }
1964
1965         if (unlikely(status & 0x1)) {
1966
1967                 /* schedule sp task to perform default status block work, ack
1968                  * attentions and enable interrupts.
1969                  */
1970                 bnx2x_schedule_sp_task(bp);
1971
1972                 status &= ~0x1;
1973                 if (!status)
1974                         return IRQ_HANDLED;
1975         }
1976
1977         if (unlikely(status))
1978                 DP(NETIF_MSG_INTR, "got an unknown interrupt! (status 0x%x)\n",
1979                    status);
1980
1981         return IRQ_HANDLED;
1982 }
1983
1984 /* Link */
1985
1986 /*
1987  * General service functions
1988  */
1989
1990 int bnx2x_acquire_hw_lock(struct bnx2x *bp, u32 resource)
1991 {
1992         u32 lock_status;
1993         u32 resource_bit = (1 << resource);
1994         int func = BP_FUNC(bp);
1995         u32 hw_lock_control_reg;
1996         int cnt;
1997
1998         /* Validating that the resource is within range */
1999         if (resource > HW_LOCK_MAX_RESOURCE_VALUE) {
2000                 BNX2X_ERR("resource(0x%x) > HW_LOCK_MAX_RESOURCE_VALUE(0x%x)\n",
2001                    resource, HW_LOCK_MAX_RESOURCE_VALUE);
2002                 return -EINVAL;
2003         }
2004
2005         if (func <= 5) {
2006                 hw_lock_control_reg = (MISC_REG_DRIVER_CONTROL_1 + func*8);
2007         } else {
2008                 hw_lock_control_reg =
2009                                 (MISC_REG_DRIVER_CONTROL_7 + (func - 6)*8);
2010         }
2011
2012         /* Validating that the resource is not already taken */
2013         lock_status = REG_RD(bp, hw_lock_control_reg);
2014         if (lock_status & resource_bit) {
2015                 BNX2X_ERR("lock_status 0x%x  resource_bit 0x%x\n",
2016                    lock_status, resource_bit);
2017                 return -EEXIST;
2018         }
2019
2020         /* Try for 5 second every 5ms */
2021         for (cnt = 0; cnt < 1000; cnt++) {
2022                 /* Try to acquire the lock */
2023                 REG_WR(bp, hw_lock_control_reg + 4, resource_bit);
2024                 lock_status = REG_RD(bp, hw_lock_control_reg);
2025                 if (lock_status & resource_bit)
2026                         return 0;
2027
2028                 usleep_range(5000, 10000);
2029         }
2030         BNX2X_ERR("Timeout\n");
2031         return -EAGAIN;
2032 }
2033
2034 int bnx2x_release_leader_lock(struct bnx2x *bp)
2035 {
2036         return bnx2x_release_hw_lock(bp, bnx2x_get_leader_lock_resource(bp));
2037 }
2038
2039 int bnx2x_release_hw_lock(struct bnx2x *bp, u32 resource)
2040 {
2041         u32 lock_status;
2042         u32 resource_bit = (1 << resource);
2043         int func = BP_FUNC(bp);
2044         u32 hw_lock_control_reg;
2045
2046         /* Validating that the resource is within range */
2047         if (resource > HW_LOCK_MAX_RESOURCE_VALUE) {
2048                 BNX2X_ERR("resource(0x%x) > HW_LOCK_MAX_RESOURCE_VALUE(0x%x)\n",
2049                    resource, HW_LOCK_MAX_RESOURCE_VALUE);
2050                 return -EINVAL;
2051         }
2052
2053         if (func <= 5) {
2054                 hw_lock_control_reg = (MISC_REG_DRIVER_CONTROL_1 + func*8);
2055         } else {
2056                 hw_lock_control_reg =
2057                                 (MISC_REG_DRIVER_CONTROL_7 + (func - 6)*8);
2058         }
2059
2060         /* Validating that the resource is currently taken */
2061         lock_status = REG_RD(bp, hw_lock_control_reg);
2062         if (!(lock_status & resource_bit)) {
2063                 BNX2X_ERR("lock_status 0x%x resource_bit 0x%x. Unlock was called but lock wasn't taken!\n",
2064                           lock_status, resource_bit);
2065                 return -EFAULT;
2066         }
2067
2068         REG_WR(bp, hw_lock_control_reg, resource_bit);
2069         return 0;
2070 }
2071
2072 int bnx2x_get_gpio(struct bnx2x *bp, int gpio_num, u8 port)
2073 {
2074         /* The GPIO should be swapped if swap register is set and active */
2075         int gpio_port = (REG_RD(bp, NIG_REG_PORT_SWAP) &&
2076                          REG_RD(bp, NIG_REG_STRAP_OVERRIDE)) ^ port;
2077         int gpio_shift = gpio_num +
2078                         (gpio_port ? MISC_REGISTERS_GPIO_PORT_SHIFT : 0);
2079         u32 gpio_mask = (1 << gpio_shift);
2080         u32 gpio_reg;
2081         int value;
2082
2083         if (gpio_num > MISC_REGISTERS_GPIO_3) {
2084                 BNX2X_ERR("Invalid GPIO %d\n", gpio_num);
2085                 return -EINVAL;
2086         }
2087
2088         /* read GPIO value */
2089         gpio_reg = REG_RD(bp, MISC_REG_GPIO);
2090
2091         /* get the requested pin value */
2092         if ((gpio_reg & gpio_mask) == gpio_mask)
2093                 value = 1;
2094         else
2095                 value = 0;
2096
2097         return value;
2098 }
2099
2100 int bnx2x_set_gpio(struct bnx2x *bp, int gpio_num, u32 mode, u8 port)
2101 {
2102         /* The GPIO should be swapped if swap register is set and active */
2103         int gpio_port = (REG_RD(bp, NIG_REG_PORT_SWAP) &&
2104                          REG_RD(bp, NIG_REG_STRAP_OVERRIDE)) ^ port;
2105         int gpio_shift = gpio_num +
2106                         (gpio_port ? MISC_REGISTERS_GPIO_PORT_SHIFT : 0);
2107         u32 gpio_mask = (1 << gpio_shift);
2108         u32 gpio_reg;
2109
2110         if (gpio_num > MISC_REGISTERS_GPIO_3) {
2111                 BNX2X_ERR("Invalid GPIO %d\n", gpio_num);
2112                 return -EINVAL;
2113         }
2114
2115         bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_GPIO);
2116         /* read GPIO and mask except the float bits */
2117         gpio_reg = (REG_RD(bp, MISC_REG_GPIO) & MISC_REGISTERS_GPIO_FLOAT);
2118
2119         switch (mode) {
2120         case MISC_REGISTERS_GPIO_OUTPUT_LOW:
2121                 DP(NETIF_MSG_LINK,
2122                    "Set GPIO %d (shift %d) -> output low\n",
2123                    gpio_num, gpio_shift);
2124                 /* clear FLOAT and set CLR */
2125                 gpio_reg &= ~(gpio_mask << MISC_REGISTERS_GPIO_FLOAT_POS);
2126                 gpio_reg |=  (gpio_mask << MISC_REGISTERS_GPIO_CLR_POS);
2127                 break;
2128
2129         case MISC_REGISTERS_GPIO_OUTPUT_HIGH:
2130                 DP(NETIF_MSG_LINK,
2131                    "Set GPIO %d (shift %d) -> output high\n",
2132                    gpio_num, gpio_shift);
2133                 /* clear FLOAT and set SET */
2134                 gpio_reg &= ~(gpio_mask << MISC_REGISTERS_GPIO_FLOAT_POS);
2135                 gpio_reg |=  (gpio_mask << MISC_REGISTERS_GPIO_SET_POS);
2136                 break;
2137
2138         case MISC_REGISTERS_GPIO_INPUT_HI_Z:
2139                 DP(NETIF_MSG_LINK,
2140                    "Set GPIO %d (shift %d) -> input\n",
2141                    gpio_num, gpio_shift);
2142                 /* set FLOAT */
2143                 gpio_reg |= (gpio_mask << MISC_REGISTERS_GPIO_FLOAT_POS);
2144                 break;
2145
2146         default:
2147                 break;
2148         }
2149
2150         REG_WR(bp, MISC_REG_GPIO, gpio_reg);
2151         bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_GPIO);
2152
2153         return 0;
2154 }
2155
2156 int bnx2x_set_mult_gpio(struct bnx2x *bp, u8 pins, u32 mode)
2157 {
2158         u32 gpio_reg = 0;
2159         int rc = 0;
2160
2161         /* Any port swapping should be handled by caller. */
2162
2163         bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_GPIO);
2164         /* read GPIO and mask except the float bits */
2165         gpio_reg = REG_RD(bp, MISC_REG_GPIO);
2166         gpio_reg &= ~(pins << MISC_REGISTERS_GPIO_FLOAT_POS);
2167         gpio_reg &= ~(pins << MISC_REGISTERS_GPIO_CLR_POS);
2168         gpio_reg &= ~(pins << MISC_REGISTERS_GPIO_SET_POS);
2169
2170         switch (mode) {
2171         case MISC_REGISTERS_GPIO_OUTPUT_LOW:
2172                 DP(NETIF_MSG_LINK, "Set GPIO 0x%x -> output low\n", pins);
2173                 /* set CLR */
2174                 gpio_reg |= (pins << MISC_REGISTERS_GPIO_CLR_POS);
2175                 break;
2176
2177         case MISC_REGISTERS_GPIO_OUTPUT_HIGH:
2178                 DP(NETIF_MSG_LINK, "Set GPIO 0x%x -> output high\n", pins);
2179                 /* set SET */
2180                 gpio_reg |= (pins << MISC_REGISTERS_GPIO_SET_POS);
2181                 break;
2182
2183         case MISC_REGISTERS_GPIO_INPUT_HI_Z:
2184                 DP(NETIF_MSG_LINK, "Set GPIO 0x%x -> input\n", pins);
2185                 /* set FLOAT */
2186                 gpio_reg |= (pins << MISC_REGISTERS_GPIO_FLOAT_POS);
2187                 break;
2188
2189         default:
2190                 BNX2X_ERR("Invalid GPIO mode assignment %d\n", mode);
2191                 rc = -EINVAL;
2192                 break;
2193         }
2194
2195         if (rc == 0)
2196                 REG_WR(bp, MISC_REG_GPIO, gpio_reg);
2197
2198         bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_GPIO);
2199
2200         return rc;
2201 }
2202
2203 int bnx2x_set_gpio_int(struct bnx2x *bp, int gpio_num, u32 mode, u8 port)
2204 {
2205         /* The GPIO should be swapped if swap register is set and active */
2206         int gpio_port = (REG_RD(bp, NIG_REG_PORT_SWAP) &&
2207                          REG_RD(bp, NIG_REG_STRAP_OVERRIDE)) ^ port;
2208         int gpio_shift = gpio_num +
2209                         (gpio_port ? MISC_REGISTERS_GPIO_PORT_SHIFT : 0);
2210         u32 gpio_mask = (1 << gpio_shift);
2211         u32 gpio_reg;
2212
2213         if (gpio_num > MISC_REGISTERS_GPIO_3) {
2214                 BNX2X_ERR("Invalid GPIO %d\n", gpio_num);
2215                 return -EINVAL;
2216         }
2217
2218         bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_GPIO);
2219         /* read GPIO int */
2220         gpio_reg = REG_RD(bp, MISC_REG_GPIO_INT);
2221
2222         switch (mode) {
2223         case MISC_REGISTERS_GPIO_INT_OUTPUT_CLR:
2224                 DP(NETIF_MSG_LINK,
2225                    "Clear GPIO INT %d (shift %d) -> output low\n",
2226                    gpio_num, gpio_shift);
2227                 /* clear SET and set CLR */
2228                 gpio_reg &= ~(gpio_mask << MISC_REGISTERS_GPIO_INT_SET_POS);
2229                 gpio_reg |=  (gpio_mask << MISC_REGISTERS_GPIO_INT_CLR_POS);
2230                 break;
2231
2232         case MISC_REGISTERS_GPIO_INT_OUTPUT_SET:
2233                 DP(NETIF_MSG_LINK,
2234                    "Set GPIO INT %d (shift %d) -> output high\n",
2235                    gpio_num, gpio_shift);
2236                 /* clear CLR and set SET */
2237                 gpio_reg &= ~(gpio_mask << MISC_REGISTERS_GPIO_INT_CLR_POS);
2238                 gpio_reg |=  (gpio_mask << MISC_REGISTERS_GPIO_INT_SET_POS);
2239                 break;
2240
2241         default:
2242                 break;
2243         }
2244
2245         REG_WR(bp, MISC_REG_GPIO_INT, gpio_reg);
2246         bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_GPIO);
2247
2248         return 0;
2249 }
2250
2251 static int bnx2x_set_spio(struct bnx2x *bp, int spio, u32 mode)
2252 {
2253         u32 spio_reg;
2254
2255         /* Only 2 SPIOs are configurable */
2256         if ((spio != MISC_SPIO_SPIO4) && (spio != MISC_SPIO_SPIO5)) {
2257                 BNX2X_ERR("Invalid SPIO 0x%x\n", spio);
2258                 return -EINVAL;
2259         }
2260
2261         bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_SPIO);
2262         /* read SPIO and mask except the float bits */
2263         spio_reg = (REG_RD(bp, MISC_REG_SPIO) & MISC_SPIO_FLOAT);
2264
2265         switch (mode) {
2266         case MISC_SPIO_OUTPUT_LOW:
2267                 DP(NETIF_MSG_HW, "Set SPIO 0x%x -> output low\n", spio);
2268                 /* clear FLOAT and set CLR */
2269                 spio_reg &= ~(spio << MISC_SPIO_FLOAT_POS);
2270                 spio_reg |=  (spio << MISC_SPIO_CLR_POS);
2271                 break;
2272
2273         case MISC_SPIO_OUTPUT_HIGH:
2274                 DP(NETIF_MSG_HW, "Set SPIO 0x%x -> output high\n", spio);
2275                 /* clear FLOAT and set SET */
2276                 spio_reg &= ~(spio << MISC_SPIO_FLOAT_POS);
2277                 spio_reg |=  (spio << MISC_SPIO_SET_POS);
2278                 break;
2279
2280         case MISC_SPIO_INPUT_HI_Z:
2281                 DP(NETIF_MSG_HW, "Set SPIO 0x%x -> input\n", spio);
2282                 /* set FLOAT */
2283                 spio_reg |= (spio << MISC_SPIO_FLOAT_POS);
2284                 break;
2285
2286         default:
2287                 break;
2288         }
2289
2290         REG_WR(bp, MISC_REG_SPIO, spio_reg);
2291         bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_SPIO);
2292
2293         return 0;
2294 }
2295
2296 void bnx2x_calc_fc_adv(struct bnx2x *bp)
2297 {
2298         u8 cfg_idx = bnx2x_get_link_cfg_idx(bp);
2299
2300         bp->port.advertising[cfg_idx] &= ~(ADVERTISED_Asym_Pause |
2301                                            ADVERTISED_Pause);
2302         switch (bp->link_vars.ieee_fc &
2303                 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_MASK) {
2304         case MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH:
2305                 bp->port.advertising[cfg_idx] |= (ADVERTISED_Asym_Pause |
2306                                                   ADVERTISED_Pause);
2307                 break;
2308
2309         case MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC:
2310                 bp->port.advertising[cfg_idx] |= ADVERTISED_Asym_Pause;
2311                 break;
2312
2313         default:
2314                 break;
2315         }
2316 }
2317
2318 static void bnx2x_set_requested_fc(struct bnx2x *bp)
2319 {
2320         /* Initialize link parameters structure variables
2321          * It is recommended to turn off RX FC for jumbo frames
2322          *  for better performance
2323          */
2324         if (CHIP_IS_E1x(bp) && (bp->dev->mtu > 5000))
2325                 bp->link_params.req_fc_auto_adv = BNX2X_FLOW_CTRL_TX;
2326         else
2327                 bp->link_params.req_fc_auto_adv = BNX2X_FLOW_CTRL_BOTH;
2328 }
2329
2330 static void bnx2x_init_dropless_fc(struct bnx2x *bp)
2331 {
2332         u32 pause_enabled = 0;
2333
2334         if (!CHIP_IS_E1(bp) && bp->dropless_fc && bp->link_vars.link_up) {
2335                 if (bp->link_vars.flow_ctrl & BNX2X_FLOW_CTRL_TX)
2336                         pause_enabled = 1;
2337
2338                 REG_WR(bp, BAR_USTRORM_INTMEM +
2339                            USTORM_ETH_PAUSE_ENABLED_OFFSET(BP_PORT(bp)),
2340                        pause_enabled);
2341         }
2342
2343         DP(NETIF_MSG_IFUP | NETIF_MSG_LINK, "dropless_fc is %s\n",
2344            pause_enabled ? "enabled" : "disabled");
2345 }
2346
2347 int bnx2x_initial_phy_init(struct bnx2x *bp, int load_mode)
2348 {
2349         int rc, cfx_idx = bnx2x_get_link_cfg_idx(bp);
2350         u16 req_line_speed = bp->link_params.req_line_speed[cfx_idx];
2351
2352         if (!BP_NOMCP(bp)) {
2353                 bnx2x_set_requested_fc(bp);
2354                 bnx2x_acquire_phy_lock(bp);
2355
2356                 if (load_mode == LOAD_DIAG) {
2357                         struct link_params *lp = &bp->link_params;
2358                         lp->loopback_mode = LOOPBACK_XGXS;
2359                         /* Prefer doing PHY loopback at highest speed */
2360                         if (lp->req_line_speed[cfx_idx] < SPEED_20000) {
2361                                 if (lp->speed_cap_mask[cfx_idx] &
2362                                     PORT_HW_CFG_SPEED_CAPABILITY_D0_20G)
2363                                         lp->req_line_speed[cfx_idx] =
2364                                         SPEED_20000;
2365                                 else if (lp->speed_cap_mask[cfx_idx] &
2366                                             PORT_HW_CFG_SPEED_CAPABILITY_D0_10G)
2367                                                 lp->req_line_speed[cfx_idx] =
2368                                                 SPEED_10000;
2369                                 else
2370                                         lp->req_line_speed[cfx_idx] =
2371                                         SPEED_1000;
2372                         }
2373                 }
2374
2375                 if (load_mode == LOAD_LOOPBACK_EXT) {
2376                         struct link_params *lp = &bp->link_params;
2377                         lp->loopback_mode = LOOPBACK_EXT;
2378                 }
2379
2380                 rc = bnx2x_phy_init(&bp->link_params, &bp->link_vars);
2381
2382                 bnx2x_release_phy_lock(bp);
2383
2384                 bnx2x_init_dropless_fc(bp);
2385
2386                 bnx2x_calc_fc_adv(bp);
2387
2388                 if (bp->link_vars.link_up) {
2389                         bnx2x_stats_handle(bp, STATS_EVENT_LINK_UP);
2390                         bnx2x_link_report(bp);
2391                 }
2392                 queue_delayed_work(bnx2x_wq, &bp->period_task, 0);
2393                 bp->link_params.req_line_speed[cfx_idx] = req_line_speed;
2394                 return rc;
2395         }
2396         BNX2X_ERR("Bootcode is missing - can not initialize link\n");
2397         return -EINVAL;
2398 }
2399
2400 void bnx2x_link_set(struct bnx2x *bp)
2401 {
2402         if (!BP_NOMCP(bp)) {
2403                 bnx2x_acquire_phy_lock(bp);
2404                 bnx2x_phy_init(&bp->link_params, &bp->link_vars);
2405                 bnx2x_release_phy_lock(bp);
2406
2407                 bnx2x_init_dropless_fc(bp);
2408
2409                 bnx2x_calc_fc_adv(bp);
2410         } else
2411                 BNX2X_ERR("Bootcode is missing - can not set link\n");
2412 }
2413
2414 static void bnx2x__link_reset(struct bnx2x *bp)
2415 {
2416         if (!BP_NOMCP(bp)) {
2417                 bnx2x_acquire_phy_lock(bp);
2418                 bnx2x_lfa_reset(&bp->link_params, &bp->link_vars);
2419                 bnx2x_release_phy_lock(bp);
2420         } else
2421                 BNX2X_ERR("Bootcode is missing - can not reset link\n");
2422 }
2423
2424 void bnx2x_force_link_reset(struct bnx2x *bp)
2425 {
2426         bnx2x_acquire_phy_lock(bp);
2427         bnx2x_link_reset(&bp->link_params, &bp->link_vars, 1);
2428         bnx2x_release_phy_lock(bp);
2429 }
2430
2431 u8 bnx2x_link_test(struct bnx2x *bp, u8 is_serdes)
2432 {
2433         u8 rc = 0;
2434
2435         if (!BP_NOMCP(bp)) {
2436                 bnx2x_acquire_phy_lock(bp);
2437                 rc = bnx2x_test_link(&bp->link_params, &bp->link_vars,
2438                                      is_serdes);
2439                 bnx2x_release_phy_lock(bp);
2440         } else
2441                 BNX2X_ERR("Bootcode is missing - can not test link\n");
2442
2443         return rc;
2444 }
2445
2446 /* Calculates the sum of vn_min_rates.
2447    It's needed for further normalizing of the min_rates.
2448    Returns:
2449      sum of vn_min_rates.
2450        or
2451      0 - if all the min_rates are 0.
2452      In the later case fairness algorithm should be deactivated.
2453      If not all min_rates are zero then those that are zeroes will be set to 1.
2454  */
2455 static void bnx2x_calc_vn_min(struct bnx2x *bp,
2456                                       struct cmng_init_input *input)
2457 {
2458         int all_zero = 1;
2459         int vn;
2460
2461         for (vn = VN_0; vn < BP_MAX_VN_NUM(bp); vn++) {
2462                 u32 vn_cfg = bp->mf_config[vn];
2463                 u32 vn_min_rate = ((vn_cfg & FUNC_MF_CFG_MIN_BW_MASK) >>
2464                                    FUNC_MF_CFG_MIN_BW_SHIFT) * 100;
2465
2466                 /* Skip hidden vns */
2467                 if (vn_cfg & FUNC_MF_CFG_FUNC_HIDE)
2468                         vn_min_rate = 0;
2469                 /* If min rate is zero - set it to 1 */
2470                 else if (!vn_min_rate)
2471                         vn_min_rate = DEF_MIN_RATE;
2472                 else
2473                         all_zero = 0;
2474
2475                 input->vnic_min_rate[vn] = vn_min_rate;
2476         }
2477
2478         /* if ETS or all min rates are zeros - disable fairness */
2479         if (BNX2X_IS_ETS_ENABLED(bp)) {
2480                 input->flags.cmng_enables &=
2481                                         ~CMNG_FLAGS_PER_PORT_FAIRNESS_VN;
2482                 DP(NETIF_MSG_IFUP, "Fairness will be disabled due to ETS\n");
2483         } else if (all_zero) {
2484                 input->flags.cmng_enables &=
2485                                         ~CMNG_FLAGS_PER_PORT_FAIRNESS_VN;
2486                 DP(NETIF_MSG_IFUP,
2487                    "All MIN values are zeroes fairness will be disabled\n");
2488         } else
2489                 input->flags.cmng_enables |=
2490                                         CMNG_FLAGS_PER_PORT_FAIRNESS_VN;
2491 }
2492
2493 static void bnx2x_calc_vn_max(struct bnx2x *bp, int vn,
2494                                     struct cmng_init_input *input)
2495 {
2496         u16 vn_max_rate;
2497         u32 vn_cfg = bp->mf_config[vn];
2498
2499         if (vn_cfg & FUNC_MF_CFG_FUNC_HIDE)
2500                 vn_max_rate = 0;
2501         else {
2502                 u32 maxCfg = bnx2x_extract_max_cfg(bp, vn_cfg);
2503
2504                 if (IS_MF_PERCENT_BW(bp)) {
2505                         /* maxCfg in percents of linkspeed */
2506                         vn_max_rate = (bp->link_vars.line_speed * maxCfg) / 100;
2507                 } else /* SD modes */
2508                         /* maxCfg is absolute in 100Mb units */
2509                         vn_max_rate = maxCfg * 100;
2510         }
2511
2512         DP(NETIF_MSG_IFUP, "vn %d: vn_max_rate %d\n", vn, vn_max_rate);
2513
2514         input->vnic_max_rate[vn] = vn_max_rate;
2515 }
2516
2517 static int bnx2x_get_cmng_fns_mode(struct bnx2x *bp)
2518 {
2519         if (CHIP_REV_IS_SLOW(bp))
2520                 return CMNG_FNS_NONE;
2521         if (IS_MF(bp))
2522                 return CMNG_FNS_MINMAX;
2523
2524         return CMNG_FNS_NONE;
2525 }
2526
2527 void bnx2x_read_mf_cfg(struct bnx2x *bp)
2528 {
2529         int vn, n = (CHIP_MODE_IS_4_PORT(bp) ? 2 : 1);
2530
2531         if (BP_NOMCP(bp))
2532                 return; /* what should be the default value in this case */
2533
2534         /* For 2 port configuration the absolute function number formula
2535          * is:
2536          *      abs_func = 2 * vn + BP_PORT + BP_PATH
2537          *
2538          *      and there are 4 functions per port
2539          *
2540          * For 4 port configuration it is
2541          *      abs_func = 4 * vn + 2 * BP_PORT + BP_PATH
2542          *
2543          *      and there are 2 functions per port
2544          */
2545         for (vn = VN_0; vn < BP_MAX_VN_NUM(bp); vn++) {
2546                 int /*abs*/func = n * (2 * vn + BP_PORT(bp)) + BP_PATH(bp);
2547
2548                 if (func >= E1H_FUNC_MAX)
2549                         break;
2550
2551                 bp->mf_config[vn] =
2552                         MF_CFG_RD(bp, func_mf_config[func].config);
2553         }
2554         if (bp->mf_config[BP_VN(bp)] & FUNC_MF_CFG_FUNC_DISABLED) {
2555                 DP(NETIF_MSG_IFUP, "mf_cfg function disabled\n");
2556                 bp->flags |= MF_FUNC_DIS;
2557         } else {
2558                 DP(NETIF_MSG_IFUP, "mf_cfg function enabled\n");
2559                 bp->flags &= ~MF_FUNC_DIS;
2560         }
2561 }
2562
2563 static void bnx2x_cmng_fns_init(struct bnx2x *bp, u8 read_cfg, u8 cmng_type)
2564 {
2565         struct cmng_init_input input;
2566         memset(&input, 0, sizeof(struct cmng_init_input));
2567
2568         input.port_rate = bp->link_vars.line_speed;
2569
2570         if (cmng_type == CMNG_FNS_MINMAX && input.port_rate) {
2571                 int vn;
2572
2573                 /* read mf conf from shmem */
2574                 if (read_cfg)
2575                         bnx2x_read_mf_cfg(bp);
2576
2577                 /* vn_weight_sum and enable fairness if not 0 */
2578                 bnx2x_calc_vn_min(bp, &input);
2579
2580                 /* calculate and set min-max rate for each vn */
2581                 if (bp->port.pmf)
2582                         for (vn = VN_0; vn < BP_MAX_VN_NUM(bp); vn++)
2583                                 bnx2x_calc_vn_max(bp, vn, &input);
2584
2585                 /* always enable rate shaping and fairness */
2586                 input.flags.cmng_enables |=
2587                                         CMNG_FLAGS_PER_PORT_RATE_SHAPING_VN;
2588
2589                 bnx2x_init_cmng(&input, &bp->cmng);
2590                 return;
2591         }
2592
2593         /* rate shaping and fairness are disabled */
2594         DP(NETIF_MSG_IFUP,
2595            "rate shaping and fairness are disabled\n");
2596 }
2597
2598 static void storm_memset_cmng(struct bnx2x *bp,
2599                               struct cmng_init *cmng,
2600                               u8 port)
2601 {
2602         int vn;
2603         size_t size = sizeof(struct cmng_struct_per_port);
2604
2605         u32 addr = BAR_XSTRORM_INTMEM +
2606                         XSTORM_CMNG_PER_PORT_VARS_OFFSET(port);
2607
2608         __storm_memset_struct(bp, addr, size, (u32 *)&cmng->port);
2609
2610         for (vn = VN_0; vn < BP_MAX_VN_NUM(bp); vn++) {
2611                 int func = func_by_vn(bp, vn);
2612
2613                 addr = BAR_XSTRORM_INTMEM +
2614                        XSTORM_RATE_SHAPING_PER_VN_VARS_OFFSET(func);
2615                 size = sizeof(struct rate_shaping_vars_per_vn);
2616                 __storm_memset_struct(bp, addr, size,
2617                                       (u32 *)&cmng->vnic.vnic_max_rate[vn]);
2618
2619                 addr = BAR_XSTRORM_INTMEM +
2620                        XSTORM_FAIRNESS_PER_VN_VARS_OFFSET(func);
2621                 size = sizeof(struct fairness_vars_per_vn);
2622                 __storm_memset_struct(bp, addr, size,
2623                                       (u32 *)&cmng->vnic.vnic_min_rate[vn]);
2624         }
2625 }
2626
2627 /* init cmng mode in HW according to local configuration */
2628 void bnx2x_set_local_cmng(struct bnx2x *bp)
2629 {
2630         int cmng_fns = bnx2x_get_cmng_fns_mode(bp);
2631
2632         if (cmng_fns != CMNG_FNS_NONE) {
2633                 bnx2x_cmng_fns_init(bp, false, cmng_fns);
2634                 storm_memset_cmng(bp, &bp->cmng, BP_PORT(bp));
2635         } else {
2636                 /* rate shaping and fairness are disabled */
2637                 DP(NETIF_MSG_IFUP,
2638                    "single function mode without fairness\n");
2639         }
2640 }
2641
2642 /* This function is called upon link interrupt */
2643 static void bnx2x_link_attn(struct bnx2x *bp)
2644 {
2645         /* Make sure that we are synced with the current statistics */
2646         bnx2x_stats_handle(bp, STATS_EVENT_STOP);
2647
2648         bnx2x_link_update(&bp->link_params, &bp->link_vars);
2649
2650         bnx2x_init_dropless_fc(bp);
2651
2652         if (bp->link_vars.link_up) {
2653
2654                 if (bp->link_vars.mac_type != MAC_TYPE_EMAC) {
2655                         struct host_port_stats *pstats;
2656
2657                         pstats = bnx2x_sp(bp, port_stats);
2658                         /* reset old mac stats */
2659                         memset(&(pstats->mac_stx[0]), 0,
2660                                sizeof(struct mac_stx));
2661                 }
2662                 if (bp->state == BNX2X_STATE_OPEN)
2663                         bnx2x_stats_handle(bp, STATS_EVENT_LINK_UP);
2664         }
2665
2666         if (bp->link_vars.link_up && bp->link_vars.line_speed)
2667                 bnx2x_set_local_cmng(bp);
2668
2669         __bnx2x_link_report(bp);
2670
2671         if (IS_MF(bp))
2672                 bnx2x_link_sync_notify(bp);
2673 }
2674
2675 void bnx2x__link_status_update(struct bnx2x *bp)
2676 {
2677         if (bp->state != BNX2X_STATE_OPEN)
2678                 return;
2679
2680         /* read updated dcb configuration */
2681         if (IS_PF(bp)) {
2682                 bnx2x_dcbx_pmf_update(bp);
2683                 bnx2x_link_status_update(&bp->link_params, &bp->link_vars);
2684                 if (bp->link_vars.link_up)
2685                         bnx2x_stats_handle(bp, STATS_EVENT_LINK_UP);
2686                 else
2687                         bnx2x_stats_handle(bp, STATS_EVENT_STOP);
2688                         /* indicate link status */
2689                 bnx2x_link_report(bp);
2690
2691         } else { /* VF */
2692                 bp->port.supported[0] |= (SUPPORTED_10baseT_Half |
2693                                           SUPPORTED_10baseT_Full |
2694                                           SUPPORTED_100baseT_Half |
2695                                           SUPPORTED_100baseT_Full |
2696                                           SUPPORTED_1000baseT_Full |
2697                                           SUPPORTED_2500baseX_Full |
2698                                           SUPPORTED_10000baseT_Full |
2699                                           SUPPORTED_TP |
2700                                           SUPPORTED_FIBRE |
2701                                           SUPPORTED_Autoneg |
2702                                           SUPPORTED_Pause |
2703                                           SUPPORTED_Asym_Pause);
2704                 bp->port.advertising[0] = bp->port.supported[0];
2705
2706                 bp->link_params.bp = bp;
2707                 bp->link_params.port = BP_PORT(bp);
2708                 bp->link_params.req_duplex[0] = DUPLEX_FULL;
2709                 bp->link_params.req_flow_ctrl[0] = BNX2X_FLOW_CTRL_NONE;
2710                 bp->link_params.req_line_speed[0] = SPEED_10000;
2711                 bp->link_params.speed_cap_mask[0] = 0x7f0000;
2712                 bp->link_params.switch_cfg = SWITCH_CFG_10G;
2713                 bp->link_vars.mac_type = MAC_TYPE_BMAC;
2714                 bp->link_vars.line_speed = SPEED_10000;
2715                 bp->link_vars.link_status =
2716                         (LINK_STATUS_LINK_UP |
2717                          LINK_STATUS_SPEED_AND_DUPLEX_10GTFD);
2718                 bp->link_vars.link_up = 1;
2719                 bp->link_vars.duplex = DUPLEX_FULL;
2720                 bp->link_vars.flow_ctrl = BNX2X_FLOW_CTRL_NONE;
2721                 __bnx2x_link_report(bp);
2722
2723                 bnx2x_sample_bulletin(bp);
2724
2725                 /* if bulletin board did not have an update for link status
2726                  * __bnx2x_link_report will report current status
2727                  * but it will NOT duplicate report in case of already reported
2728                  * during sampling bulletin board.
2729                  */
2730                 bnx2x_stats_handle(bp, STATS_EVENT_LINK_UP);
2731         }
2732 }
2733
2734 static int bnx2x_afex_func_update(struct bnx2x *bp, u16 vifid,
2735                                   u16 vlan_val, u8 allowed_prio)
2736 {
2737         struct bnx2x_func_state_params func_params = {NULL};
2738         struct bnx2x_func_afex_update_params *f_update_params =
2739                 &func_params.params.afex_update;
2740
2741         func_params.f_obj = &bp->func_obj;
2742         func_params.cmd = BNX2X_F_CMD_AFEX_UPDATE;
2743
2744         /* no need to wait for RAMROD completion, so don't
2745          * set RAMROD_COMP_WAIT flag
2746          */
2747
2748         f_update_params->vif_id = vifid;
2749         f_update_params->afex_default_vlan = vlan_val;
2750         f_update_params->allowed_priorities = allowed_prio;
2751
2752         /* if ramrod can not be sent, response to MCP immediately */
2753         if (bnx2x_func_state_change(bp, &func_params) < 0)
2754                 bnx2x_fw_command(bp, DRV_MSG_CODE_AFEX_VIFSET_ACK, 0);
2755
2756         return 0;
2757 }
2758
2759 static int bnx2x_afex_handle_vif_list_cmd(struct bnx2x *bp, u8 cmd_type,
2760                                           u16 vif_index, u8 func_bit_map)
2761 {
2762         struct bnx2x_func_state_params func_params = {NULL};
2763         struct bnx2x_func_afex_viflists_params *update_params =
2764                 &func_params.params.afex_viflists;
2765         int rc;
2766         u32 drv_msg_code;
2767
2768         /* validate only LIST_SET and LIST_GET are received from switch */
2769         if ((cmd_type != VIF_LIST_RULE_GET) && (cmd_type != VIF_LIST_RULE_SET))
2770                 BNX2X_ERR("BUG! afex_handle_vif_list_cmd invalid type 0x%x\n",
2771                           cmd_type);
2772
2773         func_params.f_obj = &bp->func_obj;
2774         func_params.cmd = BNX2X_F_CMD_AFEX_VIFLISTS;
2775
2776         /* set parameters according to cmd_type */
2777         update_params->afex_vif_list_command = cmd_type;
2778         update_params->vif_list_index = vif_index;
2779         update_params->func_bit_map =
2780                 (cmd_type == VIF_LIST_RULE_GET) ? 0 : func_bit_map;
2781         update_params->func_to_clear = 0;
2782         drv_msg_code =
2783                 (cmd_type == VIF_LIST_RULE_GET) ?
2784                 DRV_MSG_CODE_AFEX_LISTGET_ACK :
2785                 DRV_MSG_CODE_AFEX_LISTSET_ACK;
2786
2787         /* if ramrod can not be sent, respond to MCP immediately for
2788          * SET and GET requests (other are not triggered from MCP)
2789          */
2790         rc = bnx2x_func_state_change(bp, &func_params);
2791         if (rc < 0)
2792                 bnx2x_fw_command(bp, drv_msg_code, 0);
2793
2794         return 0;
2795 }
2796
2797 static void bnx2x_handle_afex_cmd(struct bnx2x *bp, u32 cmd)
2798 {
2799         struct afex_stats afex_stats;
2800         u32 func = BP_ABS_FUNC(bp);
2801         u32 mf_config;
2802         u16 vlan_val;
2803         u32 vlan_prio;
2804         u16 vif_id;
2805         u8 allowed_prio;
2806         u8 vlan_mode;
2807         u32 addr_to_write, vifid, addrs, stats_type, i;
2808
2809         if (cmd & DRV_STATUS_AFEX_LISTGET_REQ) {
2810                 vifid = SHMEM2_RD(bp, afex_param1_to_driver[BP_FW_MB_IDX(bp)]);
2811                 DP(BNX2X_MSG_MCP,
2812                    "afex: got MCP req LISTGET_REQ for vifid 0x%x\n", vifid);
2813                 bnx2x_afex_handle_vif_list_cmd(bp, VIF_LIST_RULE_GET, vifid, 0);
2814         }
2815
2816         if (cmd & DRV_STATUS_AFEX_LISTSET_REQ) {
2817                 vifid = SHMEM2_RD(bp, afex_param1_to_driver[BP_FW_MB_IDX(bp)]);
2818                 addrs = SHMEM2_RD(bp, afex_param2_to_driver[BP_FW_MB_IDX(bp)]);
2819                 DP(BNX2X_MSG_MCP,
2820                    "afex: got MCP req LISTSET_REQ for vifid 0x%x addrs 0x%x\n",
2821                    vifid, addrs);
2822                 bnx2x_afex_handle_vif_list_cmd(bp, VIF_LIST_RULE_SET, vifid,
2823                                                addrs);
2824         }
2825
2826         if (cmd & DRV_STATUS_AFEX_STATSGET_REQ) {
2827                 addr_to_write = SHMEM2_RD(bp,
2828                         afex_scratchpad_addr_to_write[BP_FW_MB_IDX(bp)]);
2829                 stats_type = SHMEM2_RD(bp,
2830                         afex_param1_to_driver[BP_FW_MB_IDX(bp)]);
2831
2832                 DP(BNX2X_MSG_MCP,
2833                    "afex: got MCP req STATSGET_REQ, write to addr 0x%x\n",
2834                    addr_to_write);
2835
2836                 bnx2x_afex_collect_stats(bp, (void *)&afex_stats, stats_type);
2837
2838                 /* write response to scratchpad, for MCP */
2839                 for (i = 0; i < (sizeof(struct afex_stats)/sizeof(u32)); i++)
2840                         REG_WR(bp, addr_to_write + i*sizeof(u32),
2841                                *(((u32 *)(&afex_stats))+i));
2842
2843                 /* send ack message to MCP */
2844                 bnx2x_fw_command(bp, DRV_MSG_CODE_AFEX_STATSGET_ACK, 0);
2845         }
2846
2847         if (cmd & DRV_STATUS_AFEX_VIFSET_REQ) {
2848                 mf_config = MF_CFG_RD(bp, func_mf_config[func].config);
2849                 bp->mf_config[BP_VN(bp)] = mf_config;
2850                 DP(BNX2X_MSG_MCP,
2851                    "afex: got MCP req VIFSET_REQ, mf_config 0x%x\n",
2852                    mf_config);
2853
2854                 /* if VIF_SET is "enabled" */
2855                 if (!(mf_config & FUNC_MF_CFG_FUNC_DISABLED)) {
2856                         /* set rate limit directly to internal RAM */
2857                         struct cmng_init_input cmng_input;
2858                         struct rate_shaping_vars_per_vn m_rs_vn;
2859                         size_t size = sizeof(struct rate_shaping_vars_per_vn);
2860                         u32 addr = BAR_XSTRORM_INTMEM +
2861                             XSTORM_RATE_SHAPING_PER_VN_VARS_OFFSET(BP_FUNC(bp));
2862
2863                         bp->mf_config[BP_VN(bp)] = mf_config;
2864
2865                         bnx2x_calc_vn_max(bp, BP_VN(bp), &cmng_input);
2866                         m_rs_vn.vn_counter.rate =
2867                                 cmng_input.vnic_max_rate[BP_VN(bp)];
2868                         m_rs_vn.vn_counter.quota =
2869                                 (m_rs_vn.vn_counter.rate *
2870                                  RS_PERIODIC_TIMEOUT_USEC) / 8;
2871
2872                         __storm_memset_struct(bp, addr, size, (u32 *)&m_rs_vn);
2873
2874                         /* read relevant values from mf_cfg struct in shmem */
2875                         vif_id =
2876                                 (MF_CFG_RD(bp, func_mf_config[func].e1hov_tag) &
2877                                  FUNC_MF_CFG_E1HOV_TAG_MASK) >>
2878                                 FUNC_MF_CFG_E1HOV_TAG_SHIFT;
2879                         vlan_val =
2880                                 (MF_CFG_RD(bp, func_mf_config[func].e1hov_tag) &
2881                                  FUNC_MF_CFG_AFEX_VLAN_MASK) >>
2882                                 FUNC_MF_CFG_AFEX_VLAN_SHIFT;
2883                         vlan_prio = (mf_config &
2884                                      FUNC_MF_CFG_TRANSMIT_PRIORITY_MASK) >>
2885                                     FUNC_MF_CFG_TRANSMIT_PRIORITY_SHIFT;
2886                         vlan_val |= (vlan_prio << VLAN_PRIO_SHIFT);
2887                         vlan_mode =
2888                                 (MF_CFG_RD(bp,
2889                                            func_mf_config[func].afex_config) &
2890                                  FUNC_MF_CFG_AFEX_VLAN_MODE_MASK) >>
2891                                 FUNC_MF_CFG_AFEX_VLAN_MODE_SHIFT;
2892                         allowed_prio =
2893                                 (MF_CFG_RD(bp,
2894                                            func_mf_config[func].afex_config) &
2895                                  FUNC_MF_CFG_AFEX_COS_FILTER_MASK) >>
2896                                 FUNC_MF_CFG_AFEX_COS_FILTER_SHIFT;
2897
2898                         /* send ramrod to FW, return in case of failure */
2899                         if (bnx2x_afex_func_update(bp, vif_id, vlan_val,
2900                                                    allowed_prio))
2901                                 return;
2902
2903                         bp->afex_def_vlan_tag = vlan_val;
2904                         bp->afex_vlan_mode = vlan_mode;
2905                 } else {
2906                         /* notify link down because BP->flags is disabled */
2907                         bnx2x_link_report(bp);
2908
2909                         /* send INVALID VIF ramrod to FW */
2910                         bnx2x_afex_func_update(bp, 0xFFFF, 0, 0);
2911
2912                         /* Reset the default afex VLAN */
2913                         bp->afex_def_vlan_tag = -1;
2914                 }
2915         }
2916 }
2917
2918 static void bnx2x_handle_update_svid_cmd(struct bnx2x *bp)
2919 {
2920         struct bnx2x_func_switch_update_params *switch_update_params;
2921         struct bnx2x_func_state_params func_params;
2922
2923         memset(&func_params, 0, sizeof(struct bnx2x_func_state_params));
2924         switch_update_params = &func_params.params.switch_update;
2925         func_params.f_obj = &bp->func_obj;
2926         func_params.cmd = BNX2X_F_CMD_SWITCH_UPDATE;
2927
2928         if (IS_MF_UFP(bp) || IS_MF_BD(bp)) {
2929                 int func = BP_ABS_FUNC(bp);
2930                 u32 val;
2931
2932                 /* Re-learn the S-tag from shmem */
2933                 val = MF_CFG_RD(bp, func_mf_config[func].e1hov_tag) &
2934                                 FUNC_MF_CFG_E1HOV_TAG_MASK;
2935                 if (val != FUNC_MF_CFG_E1HOV_TAG_DEFAULT) {
2936                         bp->mf_ov = val;
2937                 } else {
2938                         BNX2X_ERR("Got an SVID event, but no tag is configured in shmem\n");
2939                         goto fail;
2940                 }
2941
2942                 /* Configure new S-tag in LLH */
2943                 REG_WR(bp, NIG_REG_LLH0_FUNC_VLAN_ID + BP_PORT(bp) * 8,
2944                        bp->mf_ov);
2945
2946                 /* Send Ramrod to update FW of change */
2947                 __set_bit(BNX2X_F_UPDATE_SD_VLAN_TAG_CHNG,
2948                           &switch_update_params->changes);
2949                 switch_update_params->vlan = bp->mf_ov;
2950
2951                 if (bnx2x_func_state_change(bp, &func_params) < 0) {
2952                         BNX2X_ERR("Failed to configure FW of S-tag Change to %02x\n",
2953                                   bp->mf_ov);
2954                         goto fail;
2955                 } else {
2956                         DP(BNX2X_MSG_MCP, "Configured S-tag %02x\n",
2957                            bp->mf_ov);
2958                 }
2959         } else {
2960                 goto fail;
2961         }
2962
2963         bnx2x_fw_command(bp, DRV_MSG_CODE_OEM_UPDATE_SVID_OK, 0);
2964         return;
2965 fail:
2966         bnx2x_fw_command(bp, DRV_MSG_CODE_OEM_UPDATE_SVID_FAILURE, 0);
2967 }
2968
2969 static void bnx2x_pmf_update(struct bnx2x *bp)
2970 {
2971         int port = BP_PORT(bp);
2972         u32 val;
2973
2974         bp->port.pmf = 1;
2975         DP(BNX2X_MSG_MCP, "pmf %d\n", bp->port.pmf);
2976
2977         /*
2978          * We need the mb() to ensure the ordering between the writing to
2979          * bp->port.pmf here and reading it from the bnx2x_periodic_task().
2980          */
2981         smp_mb();
2982
2983         /* queue a periodic task */
2984         queue_delayed_work(bnx2x_wq, &bp->period_task, 0);
2985
2986         bnx2x_dcbx_pmf_update(bp);
2987
2988         /* enable nig attention */
2989         val = (0xff0f | (1 << (BP_VN(bp) + 4)));
2990         if (bp->common.int_block == INT_BLOCK_HC) {
2991                 REG_WR(bp, HC_REG_TRAILING_EDGE_0 + port*8, val);
2992                 REG_WR(bp, HC_REG_LEADING_EDGE_0 + port*8, val);
2993         } else if (!CHIP_IS_E1x(bp)) {
2994                 REG_WR(bp, IGU_REG_TRAILING_EDGE_LATCH, val);
2995                 REG_WR(bp, IGU_REG_LEADING_EDGE_LATCH, val);
2996         }
2997
2998         bnx2x_stats_handle(bp, STATS_EVENT_PMF);
2999 }
3000
3001 /* end of Link */
3002
3003 /* slow path */
3004
3005 /*
3006  * General service functions
3007  */
3008
3009 /* send the MCP a request, block until there is a reply */
3010 u32 bnx2x_fw_command(struct bnx2x *bp, u32 command, u32 param)
3011 {
3012         int mb_idx = BP_FW_MB_IDX(bp);
3013         u32 seq;
3014         u32 rc = 0;
3015         u32 cnt = 1;
3016         u8 delay = CHIP_REV_IS_SLOW(bp) ? 100 : 10;
3017
3018         mutex_lock(&bp->fw_mb_mutex);
3019         seq = ++bp->fw_seq;
3020         SHMEM_WR(bp, func_mb[mb_idx].drv_mb_param, param);
3021         SHMEM_WR(bp, func_mb[mb_idx].drv_mb_header, (command | seq));
3022
3023         DP(BNX2X_MSG_MCP, "wrote command (%x) to FW MB param 0x%08x\n",
3024                         (command | seq), param);
3025
3026         do {
3027                 /* let the FW do it's magic ... */
3028                 msleep(delay);
3029
3030                 rc = SHMEM_RD(bp, func_mb[mb_idx].fw_mb_header);
3031
3032                 /* Give the FW up to 5 second (500*10ms) */
3033         } while ((seq != (rc & FW_MSG_SEQ_NUMBER_MASK)) && (cnt++ < 500));
3034
3035         DP(BNX2X_MSG_MCP, "[after %d ms] read (%x) seq is (%x) from FW MB\n",
3036            cnt*delay, rc, seq);
3037
3038         /* is this a reply to our command? */
3039         if (seq == (rc & FW_MSG_SEQ_NUMBER_MASK))
3040                 rc &= FW_MSG_CODE_MASK;
3041         else {
3042                 /* FW BUG! */
3043                 BNX2X_ERR("FW failed to respond!\n");
3044                 bnx2x_fw_dump(bp);
3045                 rc = 0;
3046         }
3047         mutex_unlock(&bp->fw_mb_mutex);
3048
3049         return rc;
3050 }
3051
3052 static void storm_memset_func_cfg(struct bnx2x *bp,
3053                                  struct tstorm_eth_function_common_config *tcfg,
3054                                  u16 abs_fid)
3055 {
3056         size_t size = sizeof(struct tstorm_eth_function_common_config);
3057
3058         u32 addr = BAR_TSTRORM_INTMEM +
3059                         TSTORM_FUNCTION_COMMON_CONFIG_OFFSET(abs_fid);
3060
3061         __storm_memset_struct(bp, addr, size, (u32 *)tcfg);
3062 }
3063
3064 void bnx2x_func_init(struct bnx2x *bp, struct bnx2x_func_init_params *p)
3065 {
3066         if (CHIP_IS_E1x(bp)) {
3067                 struct tstorm_eth_function_common_config tcfg = {0};
3068
3069                 storm_memset_func_cfg(bp, &tcfg, p->func_id);
3070         }
3071
3072         /* Enable the function in the FW */
3073         storm_memset_vf_to_pf(bp, p->func_id, p->pf_id);
3074         storm_memset_func_en(bp, p->func_id, 1);
3075
3076         /* spq */
3077         if (p->spq_active) {
3078                 storm_memset_spq_addr(bp, p->spq_map, p->func_id);
3079                 REG_WR(bp, XSEM_REG_FAST_MEMORY +
3080                        XSTORM_SPQ_PROD_OFFSET(p->func_id), p->spq_prod);
3081         }
3082 }
3083
3084 /**
3085  * bnx2x_get_common_flags - Return common flags
3086  *
3087  * @bp          device handle
3088  * @fp          queue handle
3089  * @zero_stats  TRUE if statistics zeroing is needed
3090  *
3091  * Return the flags that are common for the Tx-only and not normal connections.
3092  */
3093 static unsigned long bnx2x_get_common_flags(struct bnx2x *bp,
3094                                             struct bnx2x_fastpath *fp,
3095                                             bool zero_stats)
3096 {
3097         unsigned long flags = 0;
3098
3099         /* PF driver will always initialize the Queue to an ACTIVE state */
3100         __set_bit(BNX2X_Q_FLG_ACTIVE, &flags);
3101
3102         /* tx only connections collect statistics (on the same index as the
3103          * parent connection). The statistics are zeroed when the parent
3104          * connection is initialized.
3105          */
3106
3107         __set_bit(BNX2X_Q_FLG_STATS, &flags);
3108         if (zero_stats)
3109                 __set_bit(BNX2X_Q_FLG_ZERO_STATS, &flags);
3110
3111         if (bp->flags & TX_SWITCHING)
3112                 __set_bit(BNX2X_Q_FLG_TX_SWITCH, &flags);
3113
3114         __set_bit(BNX2X_Q_FLG_PCSUM_ON_PKT, &flags);
3115         __set_bit(BNX2X_Q_FLG_TUN_INC_INNER_IP_ID, &flags);
3116
3117 #ifdef BNX2X_STOP_ON_ERROR
3118         __set_bit(BNX2X_Q_FLG_TX_SEC, &flags);
3119 #endif
3120
3121         return flags;
3122 }
3123
3124 static unsigned long bnx2x_get_q_flags(struct bnx2x *bp,
3125                                        struct bnx2x_fastpath *fp,
3126                                        bool leading)
3127 {
3128         unsigned long flags = 0;
3129
3130         /* calculate other queue flags */
3131         if (IS_MF_SD(bp))
3132                 __set_bit(BNX2X_Q_FLG_OV, &flags);
3133
3134         if (IS_FCOE_FP(fp)) {
3135                 __set_bit(BNX2X_Q_FLG_FCOE, &flags);
3136                 /* For FCoE - force usage of default priority (for afex) */
3137                 __set_bit(BNX2X_Q_FLG_FORCE_DEFAULT_PRI, &flags);
3138         }
3139
3140         if (fp->mode != TPA_MODE_DISABLED) {
3141                 __set_bit(BNX2X_Q_FLG_TPA, &flags);
3142                 __set_bit(BNX2X_Q_FLG_TPA_IPV6, &flags);
3143                 if (fp->mode == TPA_MODE_GRO)
3144                         __set_bit(BNX2X_Q_FLG_TPA_GRO, &flags);
3145         }
3146
3147         if (leading) {
3148                 __set_bit(BNX2X_Q_FLG_LEADING_RSS, &flags);
3149                 __set_bit(BNX2X_Q_FLG_MCAST, &flags);
3150         }
3151
3152         /* Always set HW VLAN stripping */
3153         __set_bit(BNX2X_Q_FLG_VLAN, &flags);
3154
3155         /* configure silent vlan removal */
3156         if (IS_MF_AFEX(bp))
3157                 __set_bit(BNX2X_Q_FLG_SILENT_VLAN_REM, &flags);
3158
3159         return flags | bnx2x_get_common_flags(bp, fp, true);
3160 }
3161
3162 static void bnx2x_pf_q_prep_general(struct bnx2x *bp,
3163         struct bnx2x_fastpath *fp, struct bnx2x_general_setup_params *gen_init,
3164         u8 cos)
3165 {
3166         gen_init->stat_id = bnx2x_stats_id(fp);
3167         gen_init->spcl_id = fp->cl_id;
3168
3169         /* Always use mini-jumbo MTU for FCoE L2 ring */
3170         if (IS_FCOE_FP(fp))
3171                 gen_init->mtu = BNX2X_FCOE_MINI_JUMBO_MTU;
3172         else
3173                 gen_init->mtu = bp->dev->mtu;
3174
3175         gen_init->cos = cos;
3176
3177         gen_init->fp_hsi = ETH_FP_HSI_VERSION;
3178 }
3179
3180 static void bnx2x_pf_rx_q_prep(struct bnx2x *bp,
3181         struct bnx2x_fastpath *fp, struct rxq_pause_params *pause,
3182         struct bnx2x_rxq_setup_params *rxq_init)
3183 {
3184         u8 max_sge = 0;
3185         u16 sge_sz = 0;
3186         u16 tpa_agg_size = 0;
3187
3188         if (fp->mode != TPA_MODE_DISABLED) {
3189                 pause->sge_th_lo = SGE_TH_LO(bp);
3190                 pause->sge_th_hi = SGE_TH_HI(bp);
3191
3192                 /* validate SGE ring has enough to cross high threshold */
3193                 WARN_ON(bp->dropless_fc &&
3194                                 pause->sge_th_hi + FW_PREFETCH_CNT >
3195                                 MAX_RX_SGE_CNT * NUM_RX_SGE_PAGES);
3196
3197                 tpa_agg_size = TPA_AGG_SIZE;
3198                 max_sge = SGE_PAGE_ALIGN(bp->dev->mtu) >>
3199                         SGE_PAGE_SHIFT;
3200                 max_sge = ((max_sge + PAGES_PER_SGE - 1) &
3201                           (~(PAGES_PER_SGE-1))) >> PAGES_PER_SGE_SHIFT;
3202                 sge_sz = (u16)min_t(u32, SGE_PAGES, 0xffff);
3203         }
3204
3205         /* pause - not for e1 */
3206         if (!CHIP_IS_E1(bp)) {
3207                 pause->bd_th_lo = BD_TH_LO(bp);
3208                 pause->bd_th_hi = BD_TH_HI(bp);
3209
3210                 pause->rcq_th_lo = RCQ_TH_LO(bp);
3211                 pause->rcq_th_hi = RCQ_TH_HI(bp);
3212                 /*
3213                  * validate that rings have enough entries to cross
3214                  * high thresholds
3215                  */
3216                 WARN_ON(bp->dropless_fc &&
3217                                 pause->bd_th_hi + FW_PREFETCH_CNT >
3218                                 bp->rx_ring_size);
3219                 WARN_ON(bp->dropless_fc &&
3220                                 pause->rcq_th_hi + FW_PREFETCH_CNT >
3221                                 NUM_RCQ_RINGS * MAX_RCQ_DESC_CNT);
3222
3223                 pause->pri_map = 1;
3224         }
3225
3226         /* rxq setup */
3227         rxq_init->dscr_map = fp->rx_desc_mapping;
3228         rxq_init->sge_map = fp->rx_sge_mapping;
3229         rxq_init->rcq_map = fp->rx_comp_mapping;
3230         rxq_init->rcq_np_map = fp->rx_comp_mapping + BCM_PAGE_SIZE;
3231
3232         /* This should be a maximum number of data bytes that may be
3233          * placed on the BD (not including paddings).
3234          */
3235         rxq_init->buf_sz = fp->rx_buf_size - BNX2X_FW_RX_ALIGN_START -
3236                            BNX2X_FW_RX_ALIGN_END - IP_HEADER_ALIGNMENT_PADDING;
3237
3238         rxq_init->cl_qzone_id = fp->cl_qzone_id;
3239         rxq_init->tpa_agg_sz = tpa_agg_size;
3240         rxq_init->sge_buf_sz = sge_sz;
3241         rxq_init->max_sges_pkt = max_sge;
3242         rxq_init->rss_engine_id = BP_FUNC(bp);
3243         rxq_init->mcast_engine_id = BP_FUNC(bp);
3244
3245         /* Maximum number or simultaneous TPA aggregation for this Queue.
3246          *
3247          * For PF Clients it should be the maximum available number.
3248          * VF driver(s) may want to define it to a smaller value.
3249          */
3250         rxq_init->max_tpa_queues = MAX_AGG_QS(bp);
3251
3252         rxq_init->cache_line_log = BNX2X_RX_ALIGN_SHIFT;
3253         rxq_init->fw_sb_id = fp->fw_sb_id;
3254
3255         if (IS_FCOE_FP(fp))
3256                 rxq_init->sb_cq_index = HC_SP_INDEX_ETH_FCOE_RX_CQ_CONS;
3257         else
3258                 rxq_init->sb_cq_index = HC_INDEX_ETH_RX_CQ_CONS;
3259         /* configure silent vlan removal
3260          * if multi function mode is afex, then mask default vlan
3261          */
3262         if (IS_MF_AFEX(bp)) {
3263                 rxq_init->silent_removal_value = bp->afex_def_vlan_tag;
3264                 rxq_init->silent_removal_mask = VLAN_VID_MASK;
3265         }
3266 }
3267
3268 static void bnx2x_pf_tx_q_prep(struct bnx2x *bp,
3269         struct bnx2x_fastpath *fp, struct bnx2x_txq_setup_params *txq_init,
3270         u8 cos)
3271 {
3272         txq_init->dscr_map = fp->txdata_ptr[cos]->tx_desc_mapping;
3273         txq_init->sb_cq_index = HC_INDEX_ETH_FIRST_TX_CQ_CONS + cos;
3274         txq_init->traffic_type = LLFC_TRAFFIC_TYPE_NW;
3275         txq_init->fw_sb_id = fp->fw_sb_id;
3276
3277         /*
3278          * set the tss leading client id for TX classification ==
3279          * leading RSS client id
3280          */
3281         txq_init->tss_leading_cl_id = bnx2x_fp(bp, 0, cl_id);
3282
3283         if (IS_FCOE_FP(fp)) {
3284                 txq_init->sb_cq_index = HC_SP_INDEX_ETH_FCOE_TX_CQ_CONS;
3285                 txq_init->traffic_type = LLFC_TRAFFIC_TYPE_FCOE;
3286         }
3287 }
3288
3289 static void bnx2x_pf_init(struct bnx2x *bp)
3290 {
3291         struct bnx2x_func_init_params func_init = {0};
3292         struct event_ring_data eq_data = { {0} };
3293
3294         if (!CHIP_IS_E1x(bp)) {
3295                 /* reset IGU PF statistics: MSIX + ATTN */
3296                 /* PF */
3297                 REG_WR(bp, IGU_REG_STATISTIC_NUM_MESSAGE_SENT +
3298                            BNX2X_IGU_STAS_MSG_VF_CNT*4 +
3299                            (CHIP_MODE_IS_4_PORT(bp) ?
3300                                 BP_FUNC(bp) : BP_VN(bp))*4, 0);
3301                 /* ATTN */
3302                 REG_WR(bp, IGU_REG_STATISTIC_NUM_MESSAGE_SENT +
3303                            BNX2X_IGU_STAS_MSG_VF_CNT*4 +
3304                            BNX2X_IGU_STAS_MSG_PF_CNT*4 +
3305                            (CHIP_MODE_IS_4_PORT(bp) ?
3306                                 BP_FUNC(bp) : BP_VN(bp))*4, 0);
3307         }
3308
3309         func_init.spq_active = true;
3310         func_init.pf_id = BP_FUNC(bp);
3311         func_init.func_id = BP_FUNC(bp);
3312         func_init.spq_map = bp->spq_mapping;
3313         func_init.spq_prod = bp->spq_prod_idx;
3314
3315         bnx2x_func_init(bp, &func_init);
3316
3317         memset(&(bp->cmng), 0, sizeof(struct cmng_struct_per_port));
3318
3319         /*
3320          * Congestion management values depend on the link rate
3321          * There is no active link so initial link rate is set to 10 Gbps.
3322          * When the link comes up The congestion management values are
3323          * re-calculated according to the actual link rate.
3324          */
3325         bp->link_vars.line_speed = SPEED_10000;
3326         bnx2x_cmng_fns_init(bp, true, bnx2x_get_cmng_fns_mode(bp));
3327
3328         /* Only the PMF sets the HW */
3329         if (bp->port.pmf)
3330                 storm_memset_cmng(bp, &bp->cmng, BP_PORT(bp));
3331
3332         /* init Event Queue - PCI bus guarantees correct endianity*/
3333         eq_data.base_addr.hi = U64_HI(bp->eq_mapping);
3334         eq_data.base_addr.lo = U64_LO(bp->eq_mapping);
3335         eq_data.producer = bp->eq_prod;
3336         eq_data.index_id = HC_SP_INDEX_EQ_CONS;
3337         eq_data.sb_id = DEF_SB_ID;
3338         storm_memset_eq_data(bp, &eq_data, BP_FUNC(bp));
3339 }
3340
3341 static void bnx2x_e1h_disable(struct bnx2x *bp)
3342 {
3343         int port = BP_PORT(bp);
3344
3345         bnx2x_tx_disable(bp);
3346
3347         REG_WR(bp, NIG_REG_LLH0_FUNC_EN + port*8, 0);
3348 }
3349
3350 static void bnx2x_e1h_enable(struct bnx2x *bp)
3351 {
3352         int port = BP_PORT(bp);
3353
3354         if (!(IS_MF_UFP(bp) && BNX2X_IS_MF_SD_PROTOCOL_FCOE(bp)))
3355                 REG_WR(bp, NIG_REG_LLH0_FUNC_EN + port * 8, 1);
3356
3357         /* Tx queue should be only re-enabled */
3358         netif_tx_wake_all_queues(bp->dev);
3359
3360         /*
3361          * Should not call netif_carrier_on since it will be called if the link
3362          * is up when checking for link state
3363          */
3364 }
3365
3366 #define DRV_INFO_ETH_STAT_NUM_MACS_REQUIRED 3
3367
3368 static void bnx2x_drv_info_ether_stat(struct bnx2x *bp)
3369 {
3370         struct eth_stats_info *ether_stat =
3371                 &bp->slowpath->drv_info_to_mcp.ether_stat;
3372         struct bnx2x_vlan_mac_obj *mac_obj =
3373                 &bp->sp_objs->mac_obj;
3374         int i;
3375
3376         strlcpy(ether_stat->version, DRV_MODULE_VERSION,
3377                 ETH_STAT_INFO_VERSION_LEN);
3378
3379         /* get DRV_INFO_ETH_STAT_NUM_MACS_REQUIRED macs, placing them in the
3380          * mac_local field in ether_stat struct. The base address is offset by 2
3381          * bytes to account for the field being 8 bytes but a mac address is
3382          * only 6 bytes. Likewise, the stride for the get_n_elements function is
3383          * 2 bytes to compensate from the 6 bytes of a mac to the 8 bytes
3384          * allocated by the ether_stat struct, so the macs will land in their
3385          * proper positions.
3386          */
3387         for (i = 0; i < DRV_INFO_ETH_STAT_NUM_MACS_REQUIRED; i++)
3388                 memset(ether_stat->mac_local + i, 0,
3389                        sizeof(ether_stat->mac_local[0]));
3390         mac_obj->get_n_elements(bp, &bp->sp_objs[0].mac_obj,
3391                                 DRV_INFO_ETH_STAT_NUM_MACS_REQUIRED,
3392                                 ether_stat->mac_local + MAC_PAD, MAC_PAD,
3393                                 ETH_ALEN);
3394         ether_stat->mtu_size = bp->dev->mtu;
3395         if (bp->dev->features & NETIF_F_RXCSUM)
3396                 ether_stat->feature_flags |= FEATURE_ETH_CHKSUM_OFFLOAD_MASK;
3397         if (bp->dev->features & NETIF_F_TSO)
3398                 ether_stat->feature_flags |= FEATURE_ETH_LSO_MASK;
3399         ether_stat->feature_flags |= bp->common.boot_mode;
3400
3401         ether_stat->promiscuous_mode = (bp->dev->flags & IFF_PROMISC) ? 1 : 0;
3402
3403         ether_stat->txq_size = bp->tx_ring_size;
3404         ether_stat->rxq_size = bp->rx_ring_size;
3405
3406 #ifdef CONFIG_BNX2X_SRIOV
3407         ether_stat->vf_cnt = IS_SRIOV(bp) ? bp->vfdb->sriov.nr_virtfn : 0;
3408 #endif
3409 }
3410
3411 static void bnx2x_drv_info_fcoe_stat(struct bnx2x *bp)
3412 {
3413         struct bnx2x_dcbx_app_params *app = &bp->dcbx_port_params.app;
3414         struct fcoe_stats_info *fcoe_stat =
3415                 &bp->slowpath->drv_info_to_mcp.fcoe_stat;
3416
3417         if (!CNIC_LOADED(bp))
3418                 return;
3419
3420         memcpy(fcoe_stat->mac_local + MAC_PAD, bp->fip_mac, ETH_ALEN);
3421
3422         fcoe_stat->qos_priority =
3423                 app->traffic_type_priority[LLFC_TRAFFIC_TYPE_FCOE];
3424
3425         /* insert FCoE stats from ramrod response */
3426         if (!NO_FCOE(bp)) {
3427                 struct tstorm_per_queue_stats *fcoe_q_tstorm_stats =
3428                         &bp->fw_stats_data->queue_stats[FCOE_IDX(bp)].
3429                         tstorm_queue_statistics;
3430
3431                 struct xstorm_per_queue_stats *fcoe_q_xstorm_stats =
3432                         &bp->fw_stats_data->queue_stats[FCOE_IDX(bp)].
3433                         xstorm_queue_statistics;
3434
3435                 struct fcoe_statistics_params *fw_fcoe_stat =
3436                         &bp->fw_stats_data->fcoe;
3437
3438                 ADD_64_LE(fcoe_stat->rx_bytes_hi, LE32_0,
3439                           fcoe_stat->rx_bytes_lo,
3440                           fw_fcoe_stat->rx_stat0.fcoe_rx_byte_cnt);
3441
3442                 ADD_64_LE(fcoe_stat->rx_bytes_hi,
3443                           fcoe_q_tstorm_stats->rcv_ucast_bytes.hi,
3444                           fcoe_stat->rx_bytes_lo,
3445                           fcoe_q_tstorm_stats->rcv_ucast_bytes.lo);
3446
3447                 ADD_64_LE(fcoe_stat->rx_bytes_hi,
3448                           fcoe_q_tstorm_stats->rcv_bcast_bytes.hi,
3449                           fcoe_stat->rx_bytes_lo,
3450                           fcoe_q_tstorm_stats->rcv_bcast_bytes.lo);
3451
3452                 ADD_64_LE(fcoe_stat->rx_bytes_hi,
3453                           fcoe_q_tstorm_stats->rcv_mcast_bytes.hi,
3454                           fcoe_stat->rx_bytes_lo,
3455                           fcoe_q_tstorm_stats->rcv_mcast_bytes.lo);
3456
3457                 ADD_64_LE(fcoe_stat->rx_frames_hi, LE32_0,
3458                           fcoe_stat->rx_frames_lo,
3459                           fw_fcoe_stat->rx_stat0.fcoe_rx_pkt_cnt);
3460
3461                 ADD_64_LE(fcoe_stat->rx_frames_hi, LE32_0,
3462                           fcoe_stat->rx_frames_lo,
3463                           fcoe_q_tstorm_stats->rcv_ucast_pkts);
3464
3465                 ADD_64_LE(fcoe_stat->rx_frames_hi, LE32_0,
3466                           fcoe_stat->rx_frames_lo,
3467                           fcoe_q_tstorm_stats->rcv_bcast_pkts);
3468
3469                 ADD_64_LE(fcoe_stat->rx_frames_hi, LE32_0,
3470                           fcoe_stat->rx_frames_lo,
3471                           fcoe_q_tstorm_stats->rcv_mcast_pkts);
3472
3473                 ADD_64_LE(fcoe_stat->tx_bytes_hi, LE32_0,
3474                           fcoe_stat->tx_bytes_lo,
3475                           fw_fcoe_stat->tx_stat.fcoe_tx_byte_cnt);
3476
3477                 ADD_64_LE(fcoe_stat->tx_bytes_hi,
3478                           fcoe_q_xstorm_stats->ucast_bytes_sent.hi,
3479                           fcoe_stat->tx_bytes_lo,
3480                           fcoe_q_xstorm_stats->ucast_bytes_sent.lo);
3481
3482                 ADD_64_LE(fcoe_stat->tx_bytes_hi,
3483                           fcoe_q_xstorm_stats->bcast_bytes_sent.hi,
3484                           fcoe_stat->tx_bytes_lo,
3485                           fcoe_q_xstorm_stats->bcast_bytes_sent.lo);
3486
3487                 ADD_64_LE(fcoe_stat->tx_bytes_hi,
3488                           fcoe_q_xstorm_stats->mcast_bytes_sent.hi,
3489                           fcoe_stat->tx_bytes_lo,
3490                           fcoe_q_xstorm_stats->mcast_bytes_sent.lo);
3491
3492                 ADD_64_LE(fcoe_stat->tx_frames_hi, LE32_0,
3493                           fcoe_stat->tx_frames_lo,
3494                           fw_fcoe_stat->tx_stat.fcoe_tx_pkt_cnt);
3495
3496                 ADD_64_LE(fcoe_stat->tx_frames_hi, LE32_0,
3497                           fcoe_stat->tx_frames_lo,
3498                           fcoe_q_xstorm_stats->ucast_pkts_sent);
3499
3500                 ADD_64_LE(fcoe_stat->tx_frames_hi, LE32_0,
3501                           fcoe_stat->tx_frames_lo,
3502                           fcoe_q_xstorm_stats->bcast_pkts_sent);
3503
3504                 ADD_64_LE(fcoe_stat->tx_frames_hi, LE32_0,
3505                           fcoe_stat->tx_frames_lo,
3506                           fcoe_q_xstorm_stats->mcast_pkts_sent);
3507         }
3508
3509         /* ask L5 driver to add data to the struct */
3510         bnx2x_cnic_notify(bp, CNIC_CTL_FCOE_STATS_GET_CMD);
3511 }
3512
3513 static void bnx2x_drv_info_iscsi_stat(struct bnx2x *bp)
3514 {
3515         struct bnx2x_dcbx_app_params *app = &bp->dcbx_port_params.app;
3516         struct iscsi_stats_info *iscsi_stat =
3517                 &bp->slowpath->drv_info_to_mcp.iscsi_stat;
3518
3519         if (!CNIC_LOADED(bp))
3520                 return;
3521
3522         memcpy(iscsi_stat->mac_local + MAC_PAD, bp->cnic_eth_dev.iscsi_mac,
3523                ETH_ALEN);
3524
3525         iscsi_stat->qos_priority =
3526                 app->traffic_type_priority[LLFC_TRAFFIC_TYPE_ISCSI];
3527
3528         /* ask L5 driver to add data to the struct */
3529         bnx2x_cnic_notify(bp, CNIC_CTL_ISCSI_STATS_GET_CMD);
3530 }
3531
3532 /* called due to MCP event (on pmf):
3533  *      reread new bandwidth configuration
3534  *      configure FW
3535  *      notify others function about the change
3536  */
3537 static void bnx2x_config_mf_bw(struct bnx2x *bp)
3538 {
3539         /* Workaround for MFW bug.
3540          * MFW is not supposed to generate BW attention in
3541          * single function mode.
3542          */
3543         if (!IS_MF(bp)) {
3544                 DP(BNX2X_MSG_MCP,
3545                    "Ignoring MF BW config in single function mode\n");
3546                 return;
3547         }
3548
3549         if (bp->link_vars.link_up) {
3550                 bnx2x_cmng_fns_init(bp, true, CMNG_FNS_MINMAX);
3551                 bnx2x_link_sync_notify(bp);
3552         }
3553         storm_memset_cmng(bp, &bp->cmng, BP_PORT(bp));
3554 }
3555
3556 static void bnx2x_set_mf_bw(struct bnx2x *bp)
3557 {
3558         bnx2x_config_mf_bw(bp);
3559         bnx2x_fw_command(bp, DRV_MSG_CODE_SET_MF_BW_ACK, 0);
3560 }
3561
3562 static void bnx2x_handle_eee_event(struct bnx2x *bp)
3563 {
3564         DP(BNX2X_MSG_MCP, "EEE - LLDP event\n");
3565         bnx2x_fw_command(bp, DRV_MSG_CODE_EEE_RESULTS_ACK, 0);
3566 }
3567
3568 #define BNX2X_UPDATE_DRV_INFO_IND_LENGTH        (20)
3569 #define BNX2X_UPDATE_DRV_INFO_IND_COUNT         (25)
3570
3571 static void bnx2x_handle_drv_info_req(struct bnx2x *bp)
3572 {
3573         enum drv_info_opcode op_code;
3574         u32 drv_info_ctl = SHMEM2_RD(bp, drv_info_control);
3575         bool release = false;
3576         int wait;
3577
3578         /* if drv_info version supported by MFW doesn't match - send NACK */
3579         if ((drv_info_ctl & DRV_INFO_CONTROL_VER_MASK) != DRV_INFO_CUR_VER) {
3580                 bnx2x_fw_command(bp, DRV_MSG_CODE_DRV_INFO_NACK, 0);
3581                 return;
3582         }
3583
3584         op_code = (drv_info_ctl & DRV_INFO_CONTROL_OP_CODE_MASK) >>
3585                   DRV_INFO_CONTROL_OP_CODE_SHIFT;
3586
3587         /* Must prevent other flows from accessing drv_info_to_mcp */
3588         mutex_lock(&bp->drv_info_mutex);
3589
3590         memset(&bp->slowpath->drv_info_to_mcp, 0,
3591                sizeof(union drv_info_to_mcp));
3592
3593         switch (op_code) {
3594         case ETH_STATS_OPCODE:
3595                 bnx2x_drv_info_ether_stat(bp);
3596                 break;
3597         case FCOE_STATS_OPCODE:
3598                 bnx2x_drv_info_fcoe_stat(bp);
3599                 break;
3600         case ISCSI_STATS_OPCODE:
3601                 bnx2x_drv_info_iscsi_stat(bp);
3602                 break;
3603         default:
3604                 /* if op code isn't supported - send NACK */
3605                 bnx2x_fw_command(bp, DRV_MSG_CODE_DRV_INFO_NACK, 0);
3606                 goto out;
3607         }
3608
3609         /* if we got drv_info attn from MFW then these fields are defined in
3610          * shmem2 for sure
3611          */
3612         SHMEM2_WR(bp, drv_info_host_addr_lo,
3613                 U64_LO(bnx2x_sp_mapping(bp, drv_info_to_mcp)));
3614         SHMEM2_WR(bp, drv_info_host_addr_hi,
3615                 U64_HI(bnx2x_sp_mapping(bp, drv_info_to_mcp)));
3616
3617         bnx2x_fw_command(bp, DRV_MSG_CODE_DRV_INFO_ACK, 0);
3618
3619         /* Since possible management wants both this and get_driver_version
3620          * need to wait until management notifies us it finished utilizing
3621          * the buffer.
3622          */
3623         if (!SHMEM2_HAS(bp, mfw_drv_indication)) {
3624                 DP(BNX2X_MSG_MCP, "Management does not support indication\n");
3625         } else if (!bp->drv_info_mng_owner) {
3626                 u32 bit = MFW_DRV_IND_READ_DONE_OFFSET((BP_ABS_FUNC(bp) >> 1));
3627
3628                 for (wait = 0; wait < BNX2X_UPDATE_DRV_INFO_IND_COUNT; wait++) {
3629                         u32 indication = SHMEM2_RD(bp, mfw_drv_indication);
3630
3631                         /* Management is done; need to clear indication */
3632                         if (indication & bit) {
3633                                 SHMEM2_WR(bp, mfw_drv_indication,
3634                                           indication & ~bit);
3635                                 release = true;
3636                                 break;
3637                         }
3638
3639                         msleep(BNX2X_UPDATE_DRV_INFO_IND_LENGTH);
3640                 }
3641         }
3642         if (!release) {
3643                 DP(BNX2X_MSG_MCP, "Management did not release indication\n");
3644                 bp->drv_info_mng_owner = true;
3645         }
3646
3647 out:
3648         mutex_unlock(&bp->drv_info_mutex);
3649 }
3650
3651 static u32 bnx2x_update_mng_version_utility(u8 *version, bool bnx2x_format)
3652 {
3653         u8 vals[4];
3654         int i = 0;
3655
3656         if (bnx2x_format) {
3657                 i = sscanf(version, "1.%c%hhd.%hhd.%hhd",
3658                            &vals[0], &vals[1], &vals[2], &vals[3]);
3659                 if (i > 0)
3660                         vals[0] -= '0';
3661         } else {
3662                 i = sscanf(version, "%hhd.%hhd.%hhd.%hhd",
3663                            &vals[0], &vals[1], &vals[2], &vals[3]);
3664         }
3665
3666         while (i < 4)
3667                 vals[i++] = 0;
3668
3669         return (vals[0] << 24) | (vals[1] << 16) | (vals[2] << 8) | vals[3];
3670 }
3671
3672 void bnx2x_update_mng_version(struct bnx2x *bp)
3673 {
3674         u32 iscsiver = DRV_VER_NOT_LOADED;
3675         u32 fcoever = DRV_VER_NOT_LOADED;
3676         u32 ethver = DRV_VER_NOT_LOADED;
3677         int idx = BP_FW_MB_IDX(bp);
3678         u8 *version;
3679
3680         if (!SHMEM2_HAS(bp, func_os_drv_ver))
3681                 return;
3682
3683         mutex_lock(&bp->drv_info_mutex);
3684         /* Must not proceed when `bnx2x_handle_drv_info_req' is feasible */
3685         if (bp->drv_info_mng_owner)
3686                 goto out;
3687
3688         if (bp->state != BNX2X_STATE_OPEN)
3689                 goto out;
3690
3691         /* Parse ethernet driver version */
3692         ethver = bnx2x_update_mng_version_utility(DRV_MODULE_VERSION, true);
3693         if (!CNIC_LOADED(bp))
3694                 goto out;
3695
3696         /* Try getting storage driver version via cnic */
3697         memset(&bp->slowpath->drv_info_to_mcp, 0,
3698                sizeof(union drv_info_to_mcp));
3699         bnx2x_drv_info_iscsi_stat(bp);
3700         version = bp->slowpath->drv_info_to_mcp.iscsi_stat.version;
3701         iscsiver = bnx2x_update_mng_version_utility(version, false);
3702
3703         memset(&bp->slowpath->drv_info_to_mcp, 0,
3704                sizeof(union drv_info_to_mcp));
3705         bnx2x_drv_info_fcoe_stat(bp);
3706         version = bp->slowpath->drv_info_to_mcp.fcoe_stat.version;
3707         fcoever = bnx2x_update_mng_version_utility(version, false);
3708
3709 out:
3710         SHMEM2_WR(bp, func_os_drv_ver[idx].versions[DRV_PERS_ETHERNET], ethver);
3711         SHMEM2_WR(bp, func_os_drv_ver[idx].versions[DRV_PERS_ISCSI], iscsiver);
3712         SHMEM2_WR(bp, func_os_drv_ver[idx].versions[DRV_PERS_FCOE], fcoever);
3713
3714         mutex_unlock(&bp->drv_info_mutex);
3715
3716         DP(BNX2X_MSG_MCP, "Setting driver version: ETH [%08x] iSCSI [%08x] FCoE [%08x]\n",
3717            ethver, iscsiver, fcoever);
3718 }
3719
3720 void bnx2x_update_mfw_dump(struct bnx2x *bp)
3721 {
3722         u32 drv_ver;
3723         u32 valid_dump;
3724
3725         if (!SHMEM2_HAS(bp, drv_info))
3726                 return;
3727
3728         /* Update Driver load time, possibly broken in y2038 */
3729         SHMEM2_WR(bp, drv_info.epoc, (u32)ktime_get_real_seconds());
3730
3731         drv_ver = bnx2x_update_mng_version_utility(DRV_MODULE_VERSION, true);
3732         SHMEM2_WR(bp, drv_info.drv_ver, drv_ver);
3733
3734         SHMEM2_WR(bp, drv_info.fw_ver, REG_RD(bp, XSEM_REG_PRAM));
3735
3736         /* Check & notify On-Chip dump. */
3737         valid_dump = SHMEM2_RD(bp, drv_info.valid_dump);
3738
3739         if (valid_dump & FIRST_DUMP_VALID)
3740                 DP(NETIF_MSG_IFUP, "A valid On-Chip MFW dump found on 1st partition\n");
3741
3742         if (valid_dump & SECOND_DUMP_VALID)
3743                 DP(NETIF_MSG_IFUP, "A valid On-Chip MFW dump found on 2nd partition\n");
3744 }
3745
3746 static void bnx2x_oem_event(struct bnx2x *bp, u32 event)
3747 {
3748         u32 cmd_ok, cmd_fail;
3749
3750         /* sanity */
3751         if (event & DRV_STATUS_DCC_EVENT_MASK &&
3752             event & DRV_STATUS_OEM_EVENT_MASK) {
3753                 BNX2X_ERR("Received simultaneous events %08x\n", event);
3754                 return;
3755         }
3756
3757         if (event & DRV_STATUS_DCC_EVENT_MASK) {
3758                 cmd_fail = DRV_MSG_CODE_DCC_FAILURE;
3759                 cmd_ok = DRV_MSG_CODE_DCC_OK;
3760         } else /* if (event & DRV_STATUS_OEM_EVENT_MASK) */ {
3761                 cmd_fail = DRV_MSG_CODE_OEM_FAILURE;
3762                 cmd_ok = DRV_MSG_CODE_OEM_OK;
3763         }
3764
3765         DP(BNX2X_MSG_MCP, "oem_event 0x%x\n", event);
3766
3767         if (event & (DRV_STATUS_DCC_DISABLE_ENABLE_PF |
3768                      DRV_STATUS_OEM_DISABLE_ENABLE_PF)) {
3769                 /* This is the only place besides the function initialization
3770                  * where the bp->flags can change so it is done without any
3771                  * locks
3772                  */
3773                 if (bp->mf_config[BP_VN(bp)] & FUNC_MF_CFG_FUNC_DISABLED) {
3774                         DP(BNX2X_MSG_MCP, "mf_cfg function disabled\n");
3775                         bp->flags |= MF_FUNC_DIS;
3776
3777                         bnx2x_e1h_disable(bp);
3778                 } else {
3779                         DP(BNX2X_MSG_MCP, "mf_cfg function enabled\n");
3780                         bp->flags &= ~MF_FUNC_DIS;
3781
3782                         bnx2x_e1h_enable(bp);
3783                 }
3784                 event &= ~(DRV_STATUS_DCC_DISABLE_ENABLE_PF |
3785                            DRV_STATUS_OEM_DISABLE_ENABLE_PF);
3786         }
3787
3788         if (event & (DRV_STATUS_DCC_BANDWIDTH_ALLOCATION |
3789                      DRV_STATUS_OEM_BANDWIDTH_ALLOCATION)) {
3790                 bnx2x_config_mf_bw(bp);
3791                 event &= ~(DRV_STATUS_DCC_BANDWIDTH_ALLOCATION |
3792                            DRV_STATUS_OEM_BANDWIDTH_ALLOCATION);
3793         }
3794
3795         /* Report results to MCP */
3796         if (event)
3797                 bnx2x_fw_command(bp, cmd_fail, 0);
3798         else
3799                 bnx2x_fw_command(bp, cmd_ok, 0);
3800 }
3801
3802 /* must be called under the spq lock */
3803 static struct eth_spe *bnx2x_sp_get_next(struct bnx2x *bp)
3804 {
3805         struct eth_spe *next_spe = bp->spq_prod_bd;
3806
3807         if (bp->spq_prod_bd == bp->spq_last_bd) {
3808                 bp->spq_prod_bd = bp->spq;
3809                 bp->spq_prod_idx = 0;
3810                 DP(BNX2X_MSG_SP, "end of spq\n");
3811         } else {
3812                 bp->spq_prod_bd++;
3813                 bp->spq_prod_idx++;
3814         }
3815         return next_spe;
3816 }
3817
3818 /* must be called under the spq lock */
3819 static void bnx2x_sp_prod_update(struct bnx2x *bp)
3820 {
3821         int func = BP_FUNC(bp);
3822
3823         /*
3824          * Make sure that BD data is updated before writing the producer:
3825          * BD data is written to the memory, the producer is read from the
3826          * memory, thus we need a full memory barrier to ensure the ordering.
3827          */
3828         mb();
3829
3830         REG_WR16_RELAXED(bp, BAR_XSTRORM_INTMEM + XSTORM_SPQ_PROD_OFFSET(func),
3831                          bp->spq_prod_idx);
3832         mmiowb();
3833 }
3834
3835 /**
3836  * bnx2x_is_contextless_ramrod - check if the current command ends on EQ
3837  *
3838  * @cmd:        command to check
3839  * @cmd_type:   command type
3840  */
3841 static bool bnx2x_is_contextless_ramrod(int cmd, int cmd_type)
3842 {
3843         if ((cmd_type == NONE_CONNECTION_TYPE) ||
3844             (cmd == RAMROD_CMD_ID_ETH_FORWARD_SETUP) ||
3845             (cmd == RAMROD_CMD_ID_ETH_CLASSIFICATION_RULES) ||
3846             (cmd == RAMROD_CMD_ID_ETH_FILTER_RULES) ||
3847             (cmd == RAMROD_CMD_ID_ETH_MULTICAST_RULES) ||
3848             (cmd == RAMROD_CMD_ID_ETH_SET_MAC) ||
3849             (cmd == RAMROD_CMD_ID_ETH_RSS_UPDATE))
3850                 return true;
3851         else
3852                 return false;
3853 }
3854
3855 /**
3856  * bnx2x_sp_post - place a single command on an SP ring
3857  *
3858  * @bp:         driver handle
3859  * @command:    command to place (e.g. SETUP, FILTER_RULES, etc.)
3860  * @cid:        SW CID the command is related to
3861  * @data_hi:    command private data address (high 32 bits)
3862  * @data_lo:    command private data address (low 32 bits)
3863  * @cmd_type:   command type (e.g. NONE, ETH)
3864  *
3865  * SP data is handled as if it's always an address pair, thus data fields are
3866  * not swapped to little endian in upper functions. Instead this function swaps
3867  * data as if it's two u32 fields.
3868  */
3869 int bnx2x_sp_post(struct bnx2x *bp, int command, int cid,
3870                   u32 data_hi, u32 data_lo, int cmd_type)
3871 {
3872         struct eth_spe *spe;
3873         u16 type;
3874         bool common = bnx2x_is_contextless_ramrod(command, cmd_type);
3875
3876 #ifdef BNX2X_STOP_ON_ERROR
3877         if (unlikely(bp->panic)) {
3878                 BNX2X_ERR("Can't post SP when there is panic\n");
3879                 return -EIO;
3880         }
3881 #endif
3882
3883         spin_lock_bh(&bp->spq_lock);
3884
3885         if (common) {
3886                 if (!atomic_read(&bp->eq_spq_left)) {
3887                         BNX2X_ERR("BUG! EQ ring full!\n");
3888                         spin_unlock_bh(&bp->spq_lock);
3889                         bnx2x_panic();
3890                         return -EBUSY;
3891                 }
3892         } else if (!atomic_read(&bp->cq_spq_left)) {
3893                         BNX2X_ERR("BUG! SPQ ring full!\n");
3894                         spin_unlock_bh(&bp->spq_lock);
3895                         bnx2x_panic();
3896                         return -EBUSY;
3897         }
3898
3899         spe = bnx2x_sp_get_next(bp);
3900
3901         /* CID needs port number to be encoded int it */
3902         spe->hdr.conn_and_cmd_data =
3903                         cpu_to_le32((command << SPE_HDR_CMD_ID_SHIFT) |
3904                                     HW_CID(bp, cid));
3905
3906         /* In some cases, type may already contain the func-id
3907          * mainly in SRIOV related use cases, so we add it here only
3908          * if it's not already set.
3909          */
3910         if (!(cmd_type & SPE_HDR_FUNCTION_ID)) {
3911                 type = (cmd_type << SPE_HDR_CONN_TYPE_SHIFT) &
3912                         SPE_HDR_CONN_TYPE;
3913                 type |= ((BP_FUNC(bp) << SPE_HDR_FUNCTION_ID_SHIFT) &
3914                          SPE_HDR_FUNCTION_ID);
3915         } else {
3916                 type = cmd_type;
3917         }
3918
3919         spe->hdr.type = cpu_to_le16(type);
3920
3921         spe->data.update_data_addr.hi = cpu_to_le32(data_hi);
3922         spe->data.update_data_addr.lo = cpu_to_le32(data_lo);
3923
3924         /*
3925          * It's ok if the actual decrement is issued towards the memory
3926          * somewhere between the spin_lock and spin_unlock. Thus no
3927          * more explicit memory barrier is needed.
3928          */
3929         if (common)
3930                 atomic_dec(&bp->eq_spq_left);
3931         else
3932                 atomic_dec(&bp->cq_spq_left);
3933
3934         DP(BNX2X_MSG_SP,
3935            "SPQE[%x] (%x:%x)  (cmd, common?) (%d,%d)  hw_cid %x  data (%x:%x) type(0x%x) left (CQ, EQ) (%x,%x)\n",
3936            bp->spq_prod_idx, (u32)U64_HI(bp->spq_mapping),
3937            (u32)(U64_LO(bp->spq_mapping) +
3938            (void *)bp->spq_prod_bd - (void *)bp->spq), command, common,
3939            HW_CID(bp, cid), data_hi, data_lo, type,
3940            atomic_read(&bp->cq_spq_left), atomic_read(&bp->eq_spq_left));
3941
3942         bnx2x_sp_prod_update(bp);
3943         spin_unlock_bh(&bp->spq_lock);
3944         return 0;
3945 }
3946
3947 /* acquire split MCP access lock register */
3948 static int bnx2x_acquire_alr(struct bnx2x *bp)
3949 {
3950         u32 j, val;
3951         int rc = 0;
3952
3953         might_sleep();
3954         for (j = 0; j < 1000; j++) {
3955                 REG_WR(bp, MCP_REG_MCPR_ACCESS_LOCK, MCPR_ACCESS_LOCK_LOCK);
3956                 val = REG_RD(bp, MCP_REG_MCPR_ACCESS_LOCK);
3957                 if (val & MCPR_ACCESS_LOCK_LOCK)
3958                         break;
3959
3960                 usleep_range(5000, 10000);
3961         }
3962         if (!(val & MCPR_ACCESS_LOCK_LOCK)) {
3963                 BNX2X_ERR("Cannot acquire MCP access lock register\n");
3964                 rc = -EBUSY;
3965         }
3966
3967         return rc;
3968 }
3969
3970 /* release split MCP access lock register */
3971 static void bnx2x_release_alr(struct bnx2x *bp)
3972 {
3973         REG_WR(bp, MCP_REG_MCPR_ACCESS_LOCK, 0);
3974 }
3975
3976 #define BNX2X_DEF_SB_ATT_IDX    0x0001
3977 #define BNX2X_DEF_SB_IDX        0x0002
3978
3979 static u16 bnx2x_update_dsb_idx(struct bnx2x *bp)
3980 {
3981         struct host_sp_status_block *def_sb = bp->def_status_blk;
3982         u16 rc = 0;
3983
3984         barrier(); /* status block is written to by the chip */
3985         if (bp->def_att_idx != def_sb->atten_status_block.attn_bits_index) {
3986                 bp->def_att_idx = def_sb->atten_status_block.attn_bits_index;
3987                 rc |= BNX2X_DEF_SB_ATT_IDX;
3988         }
3989
3990         if (bp->def_idx != def_sb->sp_sb.running_index) {
3991                 bp->def_idx = def_sb->sp_sb.running_index;
3992                 rc |= BNX2X_DEF_SB_IDX;
3993         }
3994
3995         /* Do not reorder: indices reading should complete before handling */
3996         barrier();
3997         return rc;
3998 }
3999
4000 /*
4001  * slow path service functions
4002  */
4003
4004 static void bnx2x_attn_int_asserted(struct bnx2x *bp, u32 asserted)
4005 {
4006         int port = BP_PORT(bp);
4007         u32 aeu_addr = port ? MISC_REG_AEU_MASK_ATTN_FUNC_1 :
4008                               MISC_REG_AEU_MASK_ATTN_FUNC_0;
4009         u32 nig_int_mask_addr = port ? NIG_REG_MASK_INTERRUPT_PORT1 :
4010                                        NIG_REG_MASK_INTERRUPT_PORT0;
4011         u32 aeu_mask;
4012         u32 nig_mask = 0;
4013         u32 reg_addr;
4014
4015         if (bp->attn_state & asserted)
4016                 BNX2X_ERR("IGU ERROR\n");
4017
4018         bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_PORT0_ATT_MASK + port);
4019         aeu_mask = REG_RD(bp, aeu_addr);
4020
4021         DP(NETIF_MSG_HW, "aeu_mask %x  newly asserted %x\n",
4022            aeu_mask, asserted);
4023         aeu_mask &= ~(asserted & 0x3ff);
4024         DP(NETIF_MSG_HW, "new mask %x\n", aeu_mask);
4025
4026         REG_WR(bp, aeu_addr, aeu_mask);
4027         bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_PORT0_ATT_MASK + port);
4028
4029         DP(NETIF_MSG_HW, "attn_state %x\n", bp->attn_state);
4030         bp->attn_state |= asserted;
4031         DP(NETIF_MSG_HW, "new state %x\n", bp->attn_state);
4032
4033         if (asserted & ATTN_HARD_WIRED_MASK) {
4034                 if (asserted & ATTN_NIG_FOR_FUNC) {
4035
4036                         bnx2x_acquire_phy_lock(bp);
4037
4038                         /* save nig interrupt mask */
4039                         nig_mask = REG_RD(bp, nig_int_mask_addr);
4040
4041                         /* If nig_mask is not set, no need to call the update
4042                          * function.
4043                          */
4044                         if (nig_mask) {
4045                                 REG_WR(bp, nig_int_mask_addr, 0);
4046
4047                                 bnx2x_link_attn(bp);
4048                         }
4049
4050                         /* handle unicore attn? */
4051                 }
4052                 if (asserted & ATTN_SW_TIMER_4_FUNC)
4053                         DP(NETIF_MSG_HW, "ATTN_SW_TIMER_4_FUNC!\n");
4054
4055                 if (asserted & GPIO_2_FUNC)
4056                         DP(NETIF_MSG_HW, "GPIO_2_FUNC!\n");
4057
4058                 if (asserted & GPIO_3_FUNC)
4059                         DP(NETIF_MSG_HW, "GPIO_3_FUNC!\n");
4060
4061                 if (asserted & GPIO_4_FUNC)
4062                         DP(NETIF_MSG_HW, "GPIO_4_FUNC!\n");
4063
4064                 if (port == 0) {
4065                         if (asserted & ATTN_GENERAL_ATTN_1) {
4066                                 DP(NETIF_MSG_HW, "ATTN_GENERAL_ATTN_1!\n");
4067                                 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_1, 0x0);
4068                         }
4069                         if (asserted & ATTN_GENERAL_ATTN_2) {
4070                                 DP(NETIF_MSG_HW, "ATTN_GENERAL_ATTN_2!\n");
4071                                 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_2, 0x0);
4072                         }
4073                         if (asserted & ATTN_GENERAL_ATTN_3) {
4074                                 DP(NETIF_MSG_HW, "ATTN_GENERAL_ATTN_3!\n");
4075                                 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_3, 0x0);
4076                         }
4077                 } else {
4078                         if (asserted & ATTN_GENERAL_ATTN_4) {
4079                                 DP(NETIF_MSG_HW, "ATTN_GENERAL_ATTN_4!\n");
4080                                 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_4, 0x0);
4081                         }
4082                         if (asserted & ATTN_GENERAL_ATTN_5) {
4083                                 DP(NETIF_MSG_HW, "ATTN_GENERAL_ATTN_5!\n");
4084                                 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_5, 0x0);
4085                         }
4086                         if (asserted & ATTN_GENERAL_ATTN_6) {
4087                                 DP(NETIF_MSG_HW, "ATTN_GENERAL_ATTN_6!\n");
4088                                 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_6, 0x0);
4089                         }
4090                 }
4091
4092         } /* if hardwired */
4093
4094         if (bp->common.int_block == INT_BLOCK_HC)
4095                 reg_addr = (HC_REG_COMMAND_REG + port*32 +
4096                             COMMAND_REG_ATTN_BITS_SET);
4097         else
4098                 reg_addr = (BAR_IGU_INTMEM + IGU_CMD_ATTN_BIT_SET_UPPER*8);
4099
4100         DP(NETIF_MSG_HW, "about to mask 0x%08x at %s addr 0x%x\n", asserted,
4101            (bp->common.int_block == INT_BLOCK_HC) ? "HC" : "IGU", reg_addr);
4102         REG_WR(bp, reg_addr, asserted);
4103
4104         /* now set back the mask */
4105         if (asserted & ATTN_NIG_FOR_FUNC) {
4106                 /* Verify that IGU ack through BAR was written before restoring
4107                  * NIG mask. This loop should exit after 2-3 iterations max.
4108                  */
4109                 if (bp->common.int_block != INT_BLOCK_HC) {
4110                         u32 cnt = 0, igu_acked;
4111                         do {
4112                                 igu_acked = REG_RD(bp,
4113                                                    IGU_REG_ATTENTION_ACK_BITS);
4114                         } while (((igu_acked & ATTN_NIG_FOR_FUNC) == 0) &&
4115                                  (++cnt < MAX_IGU_ATTN_ACK_TO));
4116                         if (!igu_acked)
4117                                 DP(NETIF_MSG_HW,
4118                                    "Failed to verify IGU ack on time\n");
4119                         barrier();
4120                 }
4121                 REG_WR(bp, nig_int_mask_addr, nig_mask);
4122                 bnx2x_release_phy_lock(bp);
4123         }
4124 }
4125
4126 static void bnx2x_fan_failure(struct bnx2x *bp)
4127 {
4128         int port = BP_PORT(bp);
4129         u32 ext_phy_config;
4130         /* mark the failure */
4131         ext_phy_config =
4132                 SHMEM_RD(bp,
4133                          dev_info.port_hw_config[port].external_phy_config);
4134
4135         ext_phy_config &= ~PORT_HW_CFG_XGXS_EXT_PHY_TYPE_MASK;
4136         ext_phy_config |= PORT_HW_CFG_XGXS_EXT_PHY_TYPE_FAILURE;
4137         SHMEM_WR(bp, dev_info.port_hw_config[port].external_phy_config,
4138                  ext_phy_config);
4139
4140         /* log the failure */
4141         netdev_err(bp->dev, "Fan Failure on Network Controller has caused the driver to shutdown the card to prevent permanent damage.\n"
4142                             "Please contact OEM Support for assistance\n");
4143
4144         /* Schedule device reset (unload)
4145          * This is due to some boards consuming sufficient power when driver is
4146          * up to overheat if fan fails.
4147          */
4148         bnx2x_schedule_sp_rtnl(bp, BNX2X_SP_RTNL_FAN_FAILURE, 0);
4149 }
4150
4151 static void bnx2x_attn_int_deasserted0(struct bnx2x *bp, u32 attn)
4152 {
4153         int port = BP_PORT(bp);
4154         int reg_offset;
4155         u32 val;
4156
4157         reg_offset = (port ? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_0 :
4158                              MISC_REG_AEU_ENABLE1_FUNC_0_OUT_0);
4159
4160         if (attn & AEU_INPUTS_ATTN_BITS_SPIO5) {
4161
4162                 val = REG_RD(bp, reg_offset);
4163                 val &= ~AEU_INPUTS_ATTN_BITS_SPIO5;
4164                 REG_WR(bp, reg_offset, val);
4165
4166                 BNX2X_ERR("SPIO5 hw attention\n");
4167
4168                 /* Fan failure attention */
4169                 bnx2x_hw_reset_phy(&bp->link_params);
4170                 bnx2x_fan_failure(bp);
4171         }
4172
4173         if ((attn & bp->link_vars.aeu_int_mask) && bp->port.pmf) {
4174                 bnx2x_acquire_phy_lock(bp);
4175                 bnx2x_handle_module_detect_int(&bp->link_params);
4176                 bnx2x_release_phy_lock(bp);
4177         }
4178
4179         if (attn & HW_INTERRUPT_ASSERT_SET_0) {
4180
4181                 val = REG_RD(bp, reg_offset);
4182                 val &= ~(attn & HW_INTERRUPT_ASSERT_SET_0);
4183                 REG_WR(bp, reg_offset, val);
4184
4185                 BNX2X_ERR("FATAL HW block attention set0 0x%x\n",
4186                           (u32)(attn & HW_INTERRUPT_ASSERT_SET_0));
4187                 bnx2x_panic();
4188         }
4189 }
4190
4191 static void bnx2x_attn_int_deasserted1(struct bnx2x *bp, u32 attn)
4192 {
4193         u32 val;
4194
4195         if (attn & AEU_INPUTS_ATTN_BITS_DOORBELLQ_HW_INTERRUPT) {
4196
4197                 val = REG_RD(bp, DORQ_REG_DORQ_INT_STS_CLR);
4198                 BNX2X_ERR("DB hw attention 0x%x\n", val);
4199                 /* DORQ discard attention */
4200                 if (val & 0x2)
4201                         BNX2X_ERR("FATAL error from DORQ\n");
4202         }
4203
4204         if (attn & HW_INTERRUPT_ASSERT_SET_1) {
4205
4206                 int port = BP_PORT(bp);
4207                 int reg_offset;
4208
4209                 reg_offset = (port ? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_1 :
4210                                      MISC_REG_AEU_ENABLE1_FUNC_0_OUT_1);
4211
4212                 val = REG_RD(bp, reg_offset);
4213                 val &= ~(attn & HW_INTERRUPT_ASSERT_SET_1);
4214                 REG_WR(bp, reg_offset, val);
4215
4216                 BNX2X_ERR("FATAL HW block attention set1 0x%x\n",
4217                           (u32)(attn & HW_INTERRUPT_ASSERT_SET_1));
4218                 bnx2x_panic();
4219         }
4220 }
4221
4222 static void bnx2x_attn_int_deasserted2(struct bnx2x *bp, u32 attn)
4223 {
4224         u32 val;
4225
4226         if (attn & AEU_INPUTS_ATTN_BITS_CFC_HW_INTERRUPT) {
4227
4228                 val = REG_RD(bp, CFC_REG_CFC_INT_STS_CLR);
4229                 BNX2X_ERR("CFC hw attention 0x%x\n", val);
4230                 /* CFC error attention */
4231                 if (val & 0x2)
4232                         BNX2X_ERR("FATAL error from CFC\n");
4233         }
4234
4235         if (attn & AEU_INPUTS_ATTN_BITS_PXP_HW_INTERRUPT) {
4236                 val = REG_RD(bp, PXP_REG_PXP_INT_STS_CLR_0);
4237                 BNX2X_ERR("PXP hw attention-0 0x%x\n", val);
4238                 /* RQ_USDMDP_FIFO_OVERFLOW */
4239                 if (val & 0x18000)
4240                         BNX2X_ERR("FATAL error from PXP\n");
4241
4242                 if (!CHIP_IS_E1x(bp)) {
4243                         val = REG_RD(bp, PXP_REG_PXP_INT_STS_CLR_1);
4244                         BNX2X_ERR("PXP hw attention-1 0x%x\n", val);
4245                 }
4246         }
4247
4248         if (attn & HW_INTERRUPT_ASSERT_SET_2) {
4249
4250                 int port = BP_PORT(bp);
4251                 int reg_offset;
4252
4253                 reg_offset = (port ? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_2 :
4254                                      MISC_REG_AEU_ENABLE1_FUNC_0_OUT_2);
4255
4256                 val = REG_RD(bp, reg_offset);
4257                 val &= ~(attn & HW_INTERRUPT_ASSERT_SET_2);
4258                 REG_WR(bp, reg_offset, val);
4259
4260                 BNX2X_ERR("FATAL HW block attention set2 0x%x\n",
4261                           (u32)(attn & HW_INTERRUPT_ASSERT_SET_2));
4262                 bnx2x_panic();
4263         }
4264 }
4265
4266 static void bnx2x_attn_int_deasserted3(struct bnx2x *bp, u32 attn)
4267 {
4268         u32 val;
4269
4270         if (attn & EVEREST_GEN_ATTN_IN_USE_MASK) {
4271
4272                 if (attn & BNX2X_PMF_LINK_ASSERT) {
4273                         int func = BP_FUNC(bp);
4274
4275                         REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_12 + func*4, 0);
4276                         bnx2x_read_mf_cfg(bp);
4277                         bp->mf_config[BP_VN(bp)] = MF_CFG_RD(bp,
4278                                         func_mf_config[BP_ABS_FUNC(bp)].config);
4279                         val = SHMEM_RD(bp,
4280                                        func_mb[BP_FW_MB_IDX(bp)].drv_status);
4281
4282                         if (val & (DRV_STATUS_DCC_EVENT_MASK |
4283                                    DRV_STATUS_OEM_EVENT_MASK))
4284                                 bnx2x_oem_event(bp,
4285                                         (val & (DRV_STATUS_DCC_EVENT_MASK |
4286                                                 DRV_STATUS_OEM_EVENT_MASK)));
4287
4288                         if (val & DRV_STATUS_SET_MF_BW)
4289                                 bnx2x_set_mf_bw(bp);
4290
4291                         if (val & DRV_STATUS_DRV_INFO_REQ)
4292                                 bnx2x_handle_drv_info_req(bp);
4293
4294                         if (val & DRV_STATUS_VF_DISABLED)
4295                                 bnx2x_schedule_iov_task(bp,
4296                                                         BNX2X_IOV_HANDLE_FLR);
4297
4298                         if ((bp->port.pmf == 0) && (val & DRV_STATUS_PMF))
4299                                 bnx2x_pmf_update(bp);
4300
4301                         if (bp->port.pmf &&
4302                             (val & DRV_STATUS_DCBX_NEGOTIATION_RESULTS) &&
4303                                 bp->dcbx_enabled > 0)
4304                                 /* start dcbx state machine */
4305                                 bnx2x_dcbx_set_params(bp,
4306                                         BNX2X_DCBX_STATE_NEG_RECEIVED);
4307                         if (val & DRV_STATUS_AFEX_EVENT_MASK)
4308                                 bnx2x_handle_afex_cmd(bp,
4309                                         val & DRV_STATUS_AFEX_EVENT_MASK);
4310                         if (val & DRV_STATUS_EEE_NEGOTIATION_RESULTS)
4311                                 bnx2x_handle_eee_event(bp);
4312
4313                         if (val & DRV_STATUS_OEM_UPDATE_SVID)
4314                                 bnx2x_handle_update_svid_cmd(bp);
4315
4316                         if (bp->link_vars.periodic_flags &
4317                             PERIODIC_FLAGS_LINK_EVENT) {
4318                                 /*  sync with link */
4319                                 bnx2x_acquire_phy_lock(bp);
4320                                 bp->link_vars.periodic_flags &=
4321                                         ~PERIODIC_FLAGS_LINK_EVENT;
4322                                 bnx2x_release_phy_lock(bp);
4323                                 if (IS_MF(bp))
4324                                         bnx2x_link_sync_notify(bp);
4325                                 bnx2x_link_report(bp);
4326                         }
4327                         /* Always call it here: bnx2x_link_report() will
4328                          * prevent the link indication duplication.
4329                          */
4330                         bnx2x__link_status_update(bp);
4331                 } else if (attn & BNX2X_MC_ASSERT_BITS) {
4332
4333                         BNX2X_ERR("MC assert!\n");
4334                         bnx2x_mc_assert(bp);
4335                         REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_10, 0);
4336                         REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_9, 0);
4337                         REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_8, 0);
4338                         REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_7, 0);
4339                         bnx2x_panic();
4340
4341                 } else if (attn & BNX2X_MCP_ASSERT) {
4342
4343                         BNX2X_ERR("MCP assert!\n");
4344                         REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_11, 0);
4345                         bnx2x_fw_dump(bp);
4346
4347                 } else
4348                         BNX2X_ERR("Unknown HW assert! (attn 0x%x)\n", attn);
4349         }
4350
4351         if (attn & EVEREST_LATCHED_ATTN_IN_USE_MASK) {
4352                 BNX2X_ERR("LATCHED attention 0x%08x (masked)\n", attn);
4353                 if (attn & BNX2X_GRC_TIMEOUT) {
4354                         val = CHIP_IS_E1(bp) ? 0 :
4355                                         REG_RD(bp, MISC_REG_GRC_TIMEOUT_ATTN);
4356                         BNX2X_ERR("GRC time-out 0x%08x\n", val);
4357                 }
4358                 if (attn & BNX2X_GRC_RSV) {
4359                         val = CHIP_IS_E1(bp) ? 0 :
4360                                         REG_RD(bp, MISC_REG_GRC_RSV_ATTN);
4361                         BNX2X_ERR("GRC reserved 0x%08x\n", val);
4362                 }
4363                 REG_WR(bp, MISC_REG_AEU_CLR_LATCH_SIGNAL, 0x7ff);
4364         }
4365 }
4366
4367 /*
4368  * Bits map:
4369  * 0-7   - Engine0 load counter.
4370  * 8-15  - Engine1 load counter.
4371  * 16    - Engine0 RESET_IN_PROGRESS bit.
4372  * 17    - Engine1 RESET_IN_PROGRESS bit.
4373  * 18    - Engine0 ONE_IS_LOADED. Set when there is at least one active function
4374  *         on the engine
4375  * 19    - Engine1 ONE_IS_LOADED.
4376  * 20    - Chip reset flow bit. When set none-leader must wait for both engines
4377  *         leader to complete (check for both RESET_IN_PROGRESS bits and not for
4378  *         just the one belonging to its engine).
4379  *
4380  */
4381 #define BNX2X_RECOVERY_GLOB_REG         MISC_REG_GENERIC_POR_1
4382
4383 #define BNX2X_PATH0_LOAD_CNT_MASK       0x000000ff
4384 #define BNX2X_PATH0_LOAD_CNT_SHIFT      0
4385 #define BNX2X_PATH1_LOAD_CNT_MASK       0x0000ff00
4386 #define BNX2X_PATH1_LOAD_CNT_SHIFT      8
4387 #define BNX2X_PATH0_RST_IN_PROG_BIT     0x00010000
4388 #define BNX2X_PATH1_RST_IN_PROG_BIT     0x00020000
4389 #define BNX2X_GLOBAL_RESET_BIT          0x00040000
4390
4391 /*
4392  * Set the GLOBAL_RESET bit.
4393  *
4394  * Should be run under rtnl lock
4395  */
4396 void bnx2x_set_reset_global(struct bnx2x *bp)
4397 {
4398         u32 val;
4399         bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG);
4400         val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG);
4401         REG_WR(bp, BNX2X_RECOVERY_GLOB_REG, val | BNX2X_GLOBAL_RESET_BIT);
4402         bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG);
4403 }
4404
4405 /*
4406  * Clear the GLOBAL_RESET bit.
4407  *
4408  * Should be run under rtnl lock
4409  */
4410 static void bnx2x_clear_reset_global(struct bnx2x *bp)
4411 {
4412         u32 val;
4413         bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG);
4414         val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG);
4415         REG_WR(bp, BNX2X_RECOVERY_GLOB_REG, val & (~BNX2X_GLOBAL_RESET_BIT));
4416         bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG);
4417 }
4418
4419 /*
4420  * Checks the GLOBAL_RESET bit.
4421  *
4422  * should be run under rtnl lock
4423  */
4424 static bool bnx2x_reset_is_global(struct bnx2x *bp)
4425 {
4426         u32 val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG);
4427
4428         DP(NETIF_MSG_HW, "GEN_REG_VAL=0x%08x\n", val);
4429         return (val & BNX2X_GLOBAL_RESET_BIT) ? true : false;
4430 }
4431
4432 /*
4433  * Clear RESET_IN_PROGRESS bit for the current engine.
4434  *
4435  * Should be run under rtnl lock
4436  */
4437 static void bnx2x_set_reset_done(struct bnx2x *bp)
4438 {
4439         u32 val;
4440         u32 bit = BP_PATH(bp) ?
4441                 BNX2X_PATH1_RST_IN_PROG_BIT : BNX2X_PATH0_RST_IN_PROG_BIT;
4442         bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG);
4443         val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG);
4444
4445         /* Clear the bit */
4446         val &= ~bit;
4447         REG_WR(bp, BNX2X_RECOVERY_GLOB_REG, val);
4448
4449         bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG);
4450 }
4451
4452 /*
4453  * Set RESET_IN_PROGRESS for the current engine.
4454  *
4455  * should be run under rtnl lock
4456  */
4457 void bnx2x_set_reset_in_progress(struct bnx2x *bp)
4458 {
4459         u32 val;
4460         u32 bit = BP_PATH(bp) ?
4461                 BNX2X_PATH1_RST_IN_PROG_BIT : BNX2X_PATH0_RST_IN_PROG_BIT;
4462         bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG);
4463         val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG);
4464
4465         /* Set the bit */
4466         val |= bit;
4467         REG_WR(bp, BNX2X_RECOVERY_GLOB_REG, val);
4468         bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG);
4469 }
4470
4471 /*
4472  * Checks the RESET_IN_PROGRESS bit for the given engine.
4473  * should be run under rtnl lock
4474  */
4475 bool bnx2x_reset_is_done(struct bnx2x *bp, int engine)
4476 {
4477         u32 val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG);
4478         u32 bit = engine ?
4479                 BNX2X_PATH1_RST_IN_PROG_BIT : BNX2X_PATH0_RST_IN_PROG_BIT;
4480
4481         /* return false if bit is set */
4482         return (val & bit) ? false : true;
4483 }
4484
4485 /*
4486  * set pf load for the current pf.
4487  *
4488  * should be run under rtnl lock
4489  */
4490 void bnx2x_set_pf_load(struct bnx2x *bp)
4491 {
4492         u32 val1, val;
4493         u32 mask = BP_PATH(bp) ? BNX2X_PATH1_LOAD_CNT_MASK :
4494                              BNX2X_PATH0_LOAD_CNT_MASK;
4495         u32 shift = BP_PATH(bp) ? BNX2X_PATH1_LOAD_CNT_SHIFT :
4496                              BNX2X_PATH0_LOAD_CNT_SHIFT;
4497
4498         bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG);
4499         val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG);
4500
4501         DP(NETIF_MSG_IFUP, "Old GEN_REG_VAL=0x%08x\n", val);
4502
4503         /* get the current counter value */
4504         val1 = (val & mask) >> shift;
4505
4506         /* set bit of that PF */
4507         val1 |= (1 << bp->pf_num);
4508
4509         /* clear the old value */
4510         val &= ~mask;
4511
4512         /* set the new one */
4513         val |= ((val1 << shift) & mask);
4514
4515         REG_WR(bp, BNX2X_RECOVERY_GLOB_REG, val);
4516         bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG);
4517 }
4518
4519 /**
4520  * bnx2x_clear_pf_load - clear pf load mark
4521  *
4522  * @bp:         driver handle
4523  *
4524  * Should be run under rtnl lock.
4525  * Decrements the load counter for the current engine. Returns
4526  * whether other functions are still loaded
4527  */
4528 bool bnx2x_clear_pf_load(struct bnx2x *bp)
4529 {
4530         u32 val1, val;
4531         u32 mask = BP_PATH(bp) ? BNX2X_PATH1_LOAD_CNT_MASK :
4532                              BNX2X_PATH0_LOAD_CNT_MASK;
4533         u32 shift = BP_PATH(bp) ? BNX2X_PATH1_LOAD_CNT_SHIFT :
4534                              BNX2X_PATH0_LOAD_CNT_SHIFT;
4535
4536         bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG);
4537         val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG);
4538         DP(NETIF_MSG_IFDOWN, "Old GEN_REG_VAL=0x%08x\n", val);
4539
4540         /* get the current counter value */
4541         val1 = (val & mask) >> shift;
4542
4543         /* clear bit of that PF */
4544         val1 &= ~(1 << bp->pf_num);
4545
4546         /* clear the old value */
4547         val &= ~mask;
4548
4549         /* set the new one */
4550         val |= ((val1 << shift) & mask);
4551
4552         REG_WR(bp, BNX2X_RECOVERY_GLOB_REG, val);
4553         bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG);
4554         return val1 != 0;
4555 }
4556
4557 /*
4558  * Read the load status for the current engine.
4559  *
4560  * should be run under rtnl lock
4561  */
4562 static bool bnx2x_get_load_status(struct bnx2x *bp, int engine)
4563 {
4564         u32 mask = (engine ? BNX2X_PATH1_LOAD_CNT_MASK :
4565                              BNX2X_PATH0_LOAD_CNT_MASK);
4566         u32 shift = (engine ? BNX2X_PATH1_LOAD_CNT_SHIFT :
4567                              BNX2X_PATH0_LOAD_CNT_SHIFT);
4568         u32 val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG);
4569
4570         DP(NETIF_MSG_HW | NETIF_MSG_IFUP, "GLOB_REG=0x%08x\n", val);
4571
4572         val = (val & mask) >> shift;
4573
4574         DP(NETIF_MSG_HW | NETIF_MSG_IFUP, "load mask for engine %d = 0x%x\n",
4575            engine, val);
4576
4577         return val != 0;
4578 }
4579
4580 static void _print_parity(struct bnx2x *bp, u32 reg)
4581 {
4582         pr_cont(" [0x%08x] ", REG_RD(bp, reg));
4583 }
4584
4585 static void _print_next_block(int idx, const char *blk)
4586 {
4587         pr_cont("%s%s", idx ? ", " : "", blk);
4588 }
4589
4590 static bool bnx2x_check_blocks_with_parity0(struct bnx2x *bp, u32 sig,
4591                                             int *par_num, bool print)
4592 {
4593         u32 cur_bit;
4594         bool res;
4595         int i;
4596
4597         res = false;
4598
4599         for (i = 0; sig; i++) {
4600                 cur_bit = (0x1UL << i);
4601                 if (sig & cur_bit) {
4602                         res |= true; /* Each bit is real error! */
4603
4604                         if (print) {
4605                                 switch (cur_bit) {
4606                                 case AEU_INPUTS_ATTN_BITS_BRB_PARITY_ERROR:
4607                                         _print_next_block((*par_num)++, "BRB");
4608                                         _print_parity(bp,
4609                                                       BRB1_REG_BRB1_PRTY_STS);
4610                                         break;
4611                                 case AEU_INPUTS_ATTN_BITS_PARSER_PARITY_ERROR:
4612                                         _print_next_block((*par_num)++,
4613                                                           "PARSER");
4614                                         _print_parity(bp, PRS_REG_PRS_PRTY_STS);
4615                                         break;
4616                                 case AEU_INPUTS_ATTN_BITS_TSDM_PARITY_ERROR:
4617                                         _print_next_block((*par_num)++, "TSDM");
4618                                         _print_parity(bp,
4619                                                       TSDM_REG_TSDM_PRTY_STS);
4620                                         break;
4621                                 case AEU_INPUTS_ATTN_BITS_SEARCHER_PARITY_ERROR:
4622                                         _print_next_block((*par_num)++,
4623                                                           "SEARCHER");
4624                                         _print_parity(bp, SRC_REG_SRC_PRTY_STS);
4625                                         break;
4626                                 case AEU_INPUTS_ATTN_BITS_TCM_PARITY_ERROR:
4627                                         _print_next_block((*par_num)++, "TCM");
4628                                         _print_parity(bp, TCM_REG_TCM_PRTY_STS);
4629                                         break;
4630                                 case AEU_INPUTS_ATTN_BITS_TSEMI_PARITY_ERROR:
4631                                         _print_next_block((*par_num)++,
4632                                                           "TSEMI");
4633                                         _print_parity(bp,
4634                                                       TSEM_REG_TSEM_PRTY_STS_0);
4635                                         _print_parity(bp,
4636                                                       TSEM_REG_TSEM_PRTY_STS_1);
4637                                         break;
4638                                 case AEU_INPUTS_ATTN_BITS_PBCLIENT_PARITY_ERROR:
4639                                         _print_next_block((*par_num)++, "XPB");
4640                                         _print_parity(bp, GRCBASE_XPB +
4641                                                           PB_REG_PB_PRTY_STS);
4642                                         break;
4643                                 }
4644                         }
4645
4646                         /* Clear the bit */
4647                         sig &= ~cur_bit;
4648                 }
4649         }
4650
4651         return res;
4652 }
4653
4654 static bool bnx2x_check_blocks_with_parity1(struct bnx2x *bp, u32 sig,
4655                                             int *par_num, bool *global,
4656                                             bool print)
4657 {
4658         u32 cur_bit;
4659         bool res;
4660         int i;
4661
4662         res = false;
4663
4664         for (i = 0; sig; i++) {
4665                 cur_bit = (0x1UL << i);
4666                 if (sig & cur_bit) {
4667                         res |= true; /* Each bit is real error! */
4668                         switch (cur_bit) {
4669                         case AEU_INPUTS_ATTN_BITS_PBF_PARITY_ERROR:
4670                                 if (print) {
4671                                         _print_next_block((*par_num)++, "PBF");
4672                                         _print_parity(bp, PBF_REG_PBF_PRTY_STS);
4673                                 }
4674                                 break;
4675                         case AEU_INPUTS_ATTN_BITS_QM_PARITY_ERROR:
4676                                 if (print) {
4677                                         _print_next_block((*par_num)++, "QM");
4678                                         _print_parity(bp, QM_REG_QM_PRTY_STS);
4679                                 }
4680                                 break;
4681                         case AEU_INPUTS_ATTN_BITS_TIMERS_PARITY_ERROR:
4682                                 if (print) {
4683                                         _print_next_block((*par_num)++, "TM");
4684                                         _print_parity(bp, TM_REG_TM_PRTY_STS);
4685                                 }
4686                                 break;
4687                         case AEU_INPUTS_ATTN_BITS_XSDM_PARITY_ERROR:
4688                                 if (print) {
4689                                         _print_next_block((*par_num)++, "XSDM");
4690                                         _print_parity(bp,
4691                                                       XSDM_REG_XSDM_PRTY_STS);
4692                                 }
4693                                 break;
4694                         case AEU_INPUTS_ATTN_BITS_XCM_PARITY_ERROR:
4695                                 if (print) {
4696                                         _print_next_block((*par_num)++, "XCM");
4697                                         _print_parity(bp, XCM_REG_XCM_PRTY_STS);
4698                                 }
4699                                 break;
4700                         case AEU_INPUTS_ATTN_BITS_XSEMI_PARITY_ERROR:
4701                                 if (print) {
4702                                         _print_next_block((*par_num)++,
4703                                                           "XSEMI");
4704                                         _print_parity(bp,
4705                                                       XSEM_REG_XSEM_PRTY_STS_0);
4706                                         _print_parity(bp,
4707                                                       XSEM_REG_XSEM_PRTY_STS_1);
4708                                 }
4709                                 break;
4710                         case AEU_INPUTS_ATTN_BITS_DOORBELLQ_PARITY_ERROR:
4711                                 if (print) {
4712                                         _print_next_block((*par_num)++,
4713                                                           "DOORBELLQ");
4714                                         _print_parity(bp,
4715                                                       DORQ_REG_DORQ_PRTY_STS);
4716                                 }
4717                                 break;
4718                         case AEU_INPUTS_ATTN_BITS_NIG_PARITY_ERROR:
4719                                 if (print) {
4720                                         _print_next_block((*par_num)++, "NIG");
4721                                         if (CHIP_IS_E1x(bp)) {
4722                                                 _print_parity(bp,
4723                                                         NIG_REG_NIG_PRTY_STS);
4724                                         } else {
4725                                                 _print_parity(bp,
4726                                                         NIG_REG_NIG_PRTY_STS_0);
4727                                                 _print_parity(bp,
4728                                                         NIG_REG_NIG_PRTY_STS_1);
4729                                         }
4730                                 }
4731                                 break;
4732                         case AEU_INPUTS_ATTN_BITS_VAUX_PCI_CORE_PARITY_ERROR:
4733                                 if (print)
4734                                         _print_next_block((*par_num)++,
4735                                                           "VAUX PCI CORE");
4736                                 *global = true;
4737                                 break;
4738                         case AEU_INPUTS_ATTN_BITS_DEBUG_PARITY_ERROR:
4739                                 if (print) {
4740                                         _print_next_block((*par_num)++,
4741                                                           "DEBUG");
4742                                         _print_parity(bp, DBG_REG_DBG_PRTY_STS);
4743                                 }
4744                                 break;
4745                         case AEU_INPUTS_ATTN_BITS_USDM_PARITY_ERROR:
4746                                 if (print) {
4747                                         _print_next_block((*par_num)++, "USDM");
4748                                         _print_parity(bp,
4749                                                       USDM_REG_USDM_PRTY_STS);
4750                                 }
4751                                 break;
4752                         case AEU_INPUTS_ATTN_BITS_UCM_PARITY_ERROR:
4753                                 if (print) {
4754                                         _print_next_block((*par_num)++, "UCM");
4755                                         _print_parity(bp, UCM_REG_UCM_PRTY_STS);
4756                                 }
4757                                 break;
4758                         case AEU_INPUTS_ATTN_BITS_USEMI_PARITY_ERROR:
4759                                 if (print) {
4760                                         _print_next_block((*par_num)++,
4761                                                           "USEMI");
4762                                         _print_parity(bp,
4763                                                       USEM_REG_USEM_PRTY_STS_0);
4764                                         _print_parity(bp,
4765                                                       USEM_REG_USEM_PRTY_STS_1);
4766                                 }
4767                                 break;
4768                         case AEU_INPUTS_ATTN_BITS_UPB_PARITY_ERROR:
4769                                 if (print) {
4770                                         _print_next_block((*par_num)++, "UPB");
4771                                         _print_parity(bp, GRCBASE_UPB +
4772                                                           PB_REG_PB_PRTY_STS);
4773                                 }
4774                                 break;
4775                         case AEU_INPUTS_ATTN_BITS_CSDM_PARITY_ERROR:
4776                                 if (print) {
4777                                         _print_next_block((*par_num)++, "CSDM");
4778                                         _print_parity(bp,
4779                                                       CSDM_REG_CSDM_PRTY_STS);
4780                                 }
4781                                 break;
4782                         case AEU_INPUTS_ATTN_BITS_CCM_PARITY_ERROR:
4783                                 if (print) {
4784                                         _print_next_block((*par_num)++, "CCM");
4785                                         _print_parity(bp, CCM_REG_CCM_PRTY_STS);
4786                                 }
4787                                 break;
4788                         }
4789
4790                         /* Clear the bit */
4791                         sig &= ~cur_bit;
4792                 }
4793         }
4794
4795         return res;
4796 }
4797
4798 static bool bnx2x_check_blocks_with_parity2(struct bnx2x *bp, u32 sig,
4799                                             int *par_num, bool print)
4800 {
4801         u32 cur_bit;
4802         bool res;
4803         int i;
4804
4805         res = false;
4806
4807         for (i = 0; sig; i++) {
4808                 cur_bit = (0x1UL << i);
4809                 if (sig & cur_bit) {
4810                         res = true; /* Each bit is real error! */
4811                         if (print) {
4812                                 switch (cur_bit) {
4813                                 case AEU_INPUTS_ATTN_BITS_CSEMI_PARITY_ERROR:
4814                                         _print_next_block((*par_num)++,
4815                                                           "CSEMI");
4816                                         _print_parity(bp,
4817                                                       CSEM_REG_CSEM_PRTY_STS_0);
4818                                         _print_parity(bp,
4819                                                       CSEM_REG_CSEM_PRTY_STS_1);
4820                                         break;
4821                                 case AEU_INPUTS_ATTN_BITS_PXP_PARITY_ERROR:
4822                                         _print_next_block((*par_num)++, "PXP");
4823                                         _print_parity(bp, PXP_REG_PXP_PRTY_STS);
4824                                         _print_parity(bp,
4825                                                       PXP2_REG_PXP2_PRTY_STS_0);
4826                                         _print_parity(bp,
4827                                                       PXP2_REG_PXP2_PRTY_STS_1);
4828                                         break;
4829                                 case AEU_IN_ATTN_BITS_PXPPCICLOCKCLIENT_PARITY_ERROR:
4830                                         _print_next_block((*par_num)++,
4831                                                           "PXPPCICLOCKCLIENT");
4832                                         break;
4833                                 case AEU_INPUTS_ATTN_BITS_CFC_PARITY_ERROR:
4834                                         _print_next_block((*par_num)++, "CFC");
4835                                         _print_parity(bp,
4836                                                       CFC_REG_CFC_PRTY_STS);
4837                                         break;
4838                                 case AEU_INPUTS_ATTN_BITS_CDU_PARITY_ERROR:
4839                                         _print_next_block((*par_num)++, "CDU");
4840                                         _print_parity(bp, CDU_REG_CDU_PRTY_STS);
4841                                         break;
4842                                 case AEU_INPUTS_ATTN_BITS_DMAE_PARITY_ERROR:
4843                                         _print_next_block((*par_num)++, "DMAE");
4844                                         _print_parity(bp,
4845                                                       DMAE_REG_DMAE_PRTY_STS);
4846                                         break;
4847                                 case AEU_INPUTS_ATTN_BITS_IGU_PARITY_ERROR:
4848                                         _print_next_block((*par_num)++, "IGU");
4849                                         if (CHIP_IS_E1x(bp))
4850                                                 _print_parity(bp,
4851                                                         HC_REG_HC_PRTY_STS);
4852                                         else
4853                                                 _print_parity(bp,
4854                                                         IGU_REG_IGU_PRTY_STS);
4855                                         break;
4856                                 case AEU_INPUTS_ATTN_BITS_MISC_PARITY_ERROR:
4857                                         _print_next_block((*par_num)++, "MISC");
4858                                         _print_parity(bp,
4859                                                       MISC_REG_MISC_PRTY_STS);
4860                                         break;
4861                                 }
4862                         }
4863
4864                         /* Clear the bit */
4865                         sig &= ~cur_bit;
4866                 }
4867         }
4868
4869         return res;
4870 }
4871
4872 static bool bnx2x_check_blocks_with_parity3(struct bnx2x *bp, u32 sig,
4873                                             int *par_num, bool *global,
4874                                             bool print)
4875 {
4876         bool res = false;
4877         u32 cur_bit;
4878         int i;
4879
4880         for (i = 0; sig; i++) {
4881                 cur_bit = (0x1UL << i);
4882                 if (sig & cur_bit) {
4883                         switch (cur_bit) {
4884                         case AEU_INPUTS_ATTN_BITS_MCP_LATCHED_ROM_PARITY:
4885                                 if (print)
4886                                         _print_next_block((*par_num)++,
4887                                                           "MCP ROM");
4888                                 *global = true;
4889                                 res = true;
4890                                 break;
4891                         case AEU_INPUTS_ATTN_BITS_MCP_LATCHED_UMP_RX_PARITY:
4892                                 if (print)
4893                                         _print_next_block((*par_num)++,
4894                                                           "MCP UMP RX");
4895                                 *global = true;
4896                                 res = true;
4897                                 break;
4898                         case AEU_INPUTS_ATTN_BITS_MCP_LATCHED_UMP_TX_PARITY:
4899                                 if (print)
4900                                         _print_next_block((*par_num)++,
4901                                                           "MCP UMP TX");
4902                                 *global = true;
4903                                 res = true;
4904                                 break;
4905                         case AEU_INPUTS_ATTN_BITS_MCP_LATCHED_SCPAD_PARITY:
4906                                 (*par_num)++;
4907                                 /* clear latched SCPAD PATIRY from MCP */
4908                                 REG_WR(bp, MISC_REG_AEU_CLR_LATCH_SIGNAL,
4909                                        1UL << 10);
4910                                 break;
4911                         }
4912
4913                         /* Clear the bit */
4914                         sig &= ~cur_bit;
4915                 }
4916         }
4917
4918         return res;
4919 }
4920
4921 static bool bnx2x_check_blocks_with_parity4(struct bnx2x *bp, u32 sig,
4922                                             int *par_num, bool print)
4923 {
4924         u32 cur_bit;
4925         bool res;
4926         int i;
4927
4928         res = false;
4929
4930         for (i = 0; sig; i++) {
4931                 cur_bit = (0x1UL << i);
4932                 if (sig & cur_bit) {
4933                         res = true; /* Each bit is real error! */
4934                         if (print) {
4935                                 switch (cur_bit) {
4936                                 case AEU_INPUTS_ATTN_BITS_PGLUE_PARITY_ERROR:
4937                                         _print_next_block((*par_num)++,
4938                                                           "PGLUE_B");
4939                                         _print_parity(bp,
4940                                                       PGLUE_B_REG_PGLUE_B_PRTY_STS);
4941                                         break;
4942                                 case AEU_INPUTS_ATTN_BITS_ATC_PARITY_ERROR:
4943                                         _print_next_block((*par_num)++, "ATC");
4944                                         _print_parity(bp,
4945                                                       ATC_REG_ATC_PRTY_STS);
4946                                         break;
4947                                 }
4948                         }
4949                         /* Clear the bit */
4950                         sig &= ~cur_bit;
4951                 }
4952         }
4953
4954         return res;
4955 }
4956
4957 static bool bnx2x_parity_attn(struct bnx2x *bp, bool *global, bool print,
4958                               u32 *sig)
4959 {
4960         bool res = false;
4961
4962         if ((sig[0] & HW_PRTY_ASSERT_SET_0) ||
4963             (sig[1] & HW_PRTY_ASSERT_SET_1) ||
4964             (sig[2] & HW_PRTY_ASSERT_SET_2) ||
4965             (sig[3] & HW_PRTY_ASSERT_SET_3) ||
4966             (sig[4] & HW_PRTY_ASSERT_SET_4)) {
4967                 int par_num = 0;
4968
4969                 DP(NETIF_MSG_HW, "Was parity error: HW block parity attention:\n"
4970                                  "[0]:0x%08x [1]:0x%08x [2]:0x%08x [3]:0x%08x [4]:0x%08x\n",
4971                           sig[0] & HW_PRTY_ASSERT_SET_0,
4972                           sig[1] & HW_PRTY_ASSERT_SET_1,
4973                           sig[2] & HW_PRTY_ASSERT_SET_2,
4974                           sig[3] & HW_PRTY_ASSERT_SET_3,
4975                           sig[4] & HW_PRTY_ASSERT_SET_4);
4976                 if (print) {
4977                         if (((sig[0] & HW_PRTY_ASSERT_SET_0) ||
4978                              (sig[1] & HW_PRTY_ASSERT_SET_1) ||
4979                              (sig[2] & HW_PRTY_ASSERT_SET_2) ||
4980                              (sig[4] & HW_PRTY_ASSERT_SET_4)) ||
4981                              (sig[3] & HW_PRTY_ASSERT_SET_3_WITHOUT_SCPAD)) {
4982                                 netdev_err(bp->dev,
4983                                            "Parity errors detected in blocks: ");
4984                         } else {
4985                                 print = false;
4986                         }
4987                 }
4988                 res |= bnx2x_check_blocks_with_parity0(bp,
4989                         sig[0] & HW_PRTY_ASSERT_SET_0, &par_num, print);
4990                 res |= bnx2x_check_blocks_with_parity1(bp,
4991                         sig[1] & HW_PRTY_ASSERT_SET_1, &par_num, global, print);
4992                 res |= bnx2x_check_blocks_with_parity2(bp,
4993                         sig[2] & HW_PRTY_ASSERT_SET_2, &par_num, print);
4994                 res |= bnx2x_check_blocks_with_parity3(bp,
4995                         sig[3] & HW_PRTY_ASSERT_SET_3, &par_num, global, print);
4996                 res |= bnx2x_check_blocks_with_parity4(bp,
4997                         sig[4] & HW_PRTY_ASSERT_SET_4, &par_num, print);
4998
4999                 if (print)
5000                         pr_cont("\n");
5001         }
5002
5003         return res;
5004 }
5005
5006 /**
5007  * bnx2x_chk_parity_attn - checks for parity attentions.
5008  *
5009  * @bp:         driver handle
5010  * @global:     true if there was a global attention
5011  * @print:      show parity attention in syslog
5012  */
5013 bool bnx2x_chk_parity_attn(struct bnx2x *bp, bool *global, bool print)
5014 {
5015         struct attn_route attn = { {0} };
5016         int port = BP_PORT(bp);
5017
5018         attn.sig[0] = REG_RD(bp,
5019                 MISC_REG_AEU_AFTER_INVERT_1_FUNC_0 +
5020                              port*4);
5021         attn.sig[1] = REG_RD(bp,
5022                 MISC_REG_AEU_AFTER_INVERT_2_FUNC_0 +
5023                              port*4);
5024         attn.sig[2] = REG_RD(bp,
5025                 MISC_REG_AEU_AFTER_INVERT_3_FUNC_0 +
5026                              port*4);
5027         attn.sig[3] = REG_RD(bp,
5028                 MISC_REG_AEU_AFTER_INVERT_4_FUNC_0 +
5029                              port*4);
5030         /* Since MCP attentions can't be disabled inside the block, we need to
5031          * read AEU registers to see whether they're currently disabled
5032          */
5033         attn.sig[3] &= ((REG_RD(bp,
5034                                 !port ? MISC_REG_AEU_ENABLE4_FUNC_0_OUT_0
5035                                       : MISC_REG_AEU_ENABLE4_FUNC_1_OUT_0) &
5036                          MISC_AEU_ENABLE_MCP_PRTY_BITS) |
5037                         ~MISC_AEU_ENABLE_MCP_PRTY_BITS);
5038
5039         if (!CHIP_IS_E1x(bp))
5040                 attn.sig[4] = REG_RD(bp,
5041                         MISC_REG_AEU_AFTER_INVERT_5_FUNC_0 +
5042                                      port*4);
5043
5044         return bnx2x_parity_attn(bp, global, print, attn.sig);
5045 }
5046
5047 static void bnx2x_attn_int_deasserted4(struct bnx2x *bp, u32 attn)
5048 {
5049         u32 val;
5050         if (attn & AEU_INPUTS_ATTN_BITS_PGLUE_HW_INTERRUPT) {
5051
5052                 val = REG_RD(bp, PGLUE_B_REG_PGLUE_B_INT_STS_CLR);
5053                 BNX2X_ERR("PGLUE hw attention 0x%x\n", val);
5054                 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_ADDRESS_ERROR)
5055                         BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_ADDRESS_ERROR\n");
5056                 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_INCORRECT_RCV_BEHAVIOR)
5057                         BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_INCORRECT_RCV_BEHAVIOR\n");
5058                 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_WAS_ERROR_ATTN)
5059                         BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_WAS_ERROR_ATTN\n");
5060                 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_VF_LENGTH_VIOLATION_ATTN)
5061                         BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_VF_LENGTH_VIOLATION_ATTN\n");
5062                 if (val &
5063                     PGLUE_B_PGLUE_B_INT_STS_REG_VF_GRC_SPACE_VIOLATION_ATTN)
5064                         BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_VF_GRC_SPACE_VIOLATION_ATTN\n");
5065                 if (val &
5066                     PGLUE_B_PGLUE_B_INT_STS_REG_VF_MSIX_BAR_VIOLATION_ATTN)
5067                         BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_VF_MSIX_BAR_VIOLATION_ATTN\n");
5068                 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_TCPL_ERROR_ATTN)
5069                         BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_TCPL_ERROR_ATTN\n");
5070                 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_TCPL_IN_TWO_RCBS_ATTN)
5071                         BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_TCPL_IN_TWO_RCBS_ATTN\n");
5072                 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_CSSNOOP_FIFO_OVERFLOW)
5073                         BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_CSSNOOP_FIFO_OVERFLOW\n");
5074         }
5075         if (attn & AEU_INPUTS_ATTN_BITS_ATC_HW_INTERRUPT) {
5076                 val = REG_RD(bp, ATC_REG_ATC_INT_STS_CLR);
5077                 BNX2X_ERR("ATC hw attention 0x%x\n", val);
5078                 if (val & ATC_ATC_INT_STS_REG_ADDRESS_ERROR)
5079                         BNX2X_ERR("ATC_ATC_INT_STS_REG_ADDRESS_ERROR\n");
5080                 if (val & ATC_ATC_INT_STS_REG_ATC_TCPL_TO_NOT_PEND)
5081                         BNX2X_ERR("ATC_ATC_INT_STS_REG_ATC_TCPL_TO_NOT_PEND\n");
5082                 if (val & ATC_ATC_INT_STS_REG_ATC_GPA_MULTIPLE_HITS)
5083                         BNX2X_ERR("ATC_ATC_INT_STS_REG_ATC_GPA_MULTIPLE_HITS\n");
5084                 if (val & ATC_ATC_INT_STS_REG_ATC_RCPL_TO_EMPTY_CNT)
5085                         BNX2X_ERR("ATC_ATC_INT_STS_REG_ATC_RCPL_TO_EMPTY_CNT\n");
5086                 if (val & ATC_ATC_INT_STS_REG_ATC_TCPL_ERROR)
5087                         BNX2X_ERR("ATC_ATC_INT_STS_REG_ATC_TCPL_ERROR\n");
5088                 if (val & ATC_ATC_INT_STS_REG_ATC_IREQ_LESS_THAN_STU)
5089                         BNX2X_ERR("ATC_ATC_INT_STS_REG_ATC_IREQ_LESS_THAN_STU\n");
5090         }
5091
5092         if (attn & (AEU_INPUTS_ATTN_BITS_PGLUE_PARITY_ERROR |
5093                     AEU_INPUTS_ATTN_BITS_ATC_PARITY_ERROR)) {
5094                 BNX2X_ERR("FATAL parity attention set4 0x%x\n",
5095                 (u32)(attn & (AEU_INPUTS_ATTN_BITS_PGLUE_PARITY_ERROR |
5096                     AEU_INPUTS_ATTN_BITS_ATC_PARITY_ERROR)));
5097         }
5098 }
5099
5100 static void bnx2x_attn_int_deasserted(struct bnx2x *bp, u32 deasserted)
5101 {
5102         struct attn_route attn, *group_mask;
5103         int port = BP_PORT(bp);
5104         int index;
5105         u32 reg_addr;
5106         u32 val;
5107         u32 aeu_mask;
5108         bool global = false;
5109
5110         /* need to take HW lock because MCP or other port might also
5111            try to handle this event */
5112         bnx2x_acquire_alr(bp);
5113
5114         if (bnx2x_chk_parity_attn(bp, &global, true)) {
5115 #ifndef BNX2X_STOP_ON_ERROR
5116                 bp->recovery_state = BNX2X_RECOVERY_INIT;
5117                 schedule_delayed_work(&bp->sp_rtnl_task, 0);
5118                 /* Disable HW interrupts */
5119                 bnx2x_int_disable(bp);
5120                 /* In case of parity errors don't handle attentions so that
5121                  * other function would "see" parity errors.
5122                  */
5123 #else
5124                 bnx2x_panic();
5125 #endif
5126                 bnx2x_release_alr(bp);
5127                 return;
5128         }
5129
5130         attn.sig[0] = REG_RD(bp, MISC_REG_AEU_AFTER_INVERT_1_FUNC_0 + port*4);
5131         attn.sig[1] = REG_RD(bp, MISC_REG_AEU_AFTER_INVERT_2_FUNC_0 + port*4);
5132         attn.sig[2] = REG_RD(bp, MISC_REG_AEU_AFTER_INVERT_3_FUNC_0 + port*4);
5133         attn.sig[3] = REG_RD(bp, MISC_REG_AEU_AFTER_INVERT_4_FUNC_0 + port*4);
5134         if (!CHIP_IS_E1x(bp))
5135                 attn.sig[4] =
5136                       REG_RD(bp, MISC_REG_AEU_AFTER_INVERT_5_FUNC_0 + port*4);
5137         else
5138                 attn.sig[4] = 0;
5139
5140         DP(NETIF_MSG_HW, "attn: %08x %08x %08x %08x %08x\n",
5141            attn.sig[0], attn.sig[1], attn.sig[2], attn.sig[3], attn.sig[4]);
5142
5143         for (index = 0; index < MAX_DYNAMIC_ATTN_GRPS; index++) {
5144                 if (deasserted & (1 << index)) {
5145                         group_mask = &bp->attn_group[index];
5146
5147                         DP(NETIF_MSG_HW, "group[%d]: %08x %08x %08x %08x %08x\n",
5148                            index,
5149                            group_mask->sig[0], group_mask->sig[1],
5150                            group_mask->sig[2], group_mask->sig[3],
5151                            group_mask->sig[4]);
5152
5153                         bnx2x_attn_int_deasserted4(bp,
5154                                         attn.sig[4] & group_mask->sig[4]);
5155                         bnx2x_attn_int_deasserted3(bp,
5156                                         attn.sig[3] & group_mask->sig[3]);
5157                         bnx2x_attn_int_deasserted1(bp,
5158                                         attn.sig[1] & group_mask->sig[1]);
5159                         bnx2x_attn_int_deasserted2(bp,
5160                                         attn.sig[2] & group_mask->sig[2]);
5161                         bnx2x_attn_int_deasserted0(bp,
5162                                         attn.sig[0] & group_mask->sig[0]);
5163                 }
5164         }
5165
5166         bnx2x_release_alr(bp);
5167
5168         if (bp->common.int_block == INT_BLOCK_HC)
5169                 reg_addr = (HC_REG_COMMAND_REG + port*32 +
5170                             COMMAND_REG_ATTN_BITS_CLR);
5171         else
5172                 reg_addr = (BAR_IGU_INTMEM + IGU_CMD_ATTN_BIT_CLR_UPPER*8);
5173
5174         val = ~deasserted;
5175         DP(NETIF_MSG_HW, "about to mask 0x%08x at %s addr 0x%x\n", val,
5176            (bp->common.int_block == INT_BLOCK_HC) ? "HC" : "IGU", reg_addr);
5177         REG_WR(bp, reg_addr, val);
5178
5179         if (~bp->attn_state & deasserted)
5180                 BNX2X_ERR("IGU ERROR\n");
5181
5182         reg_addr = port ? MISC_REG_AEU_MASK_ATTN_FUNC_1 :
5183                           MISC_REG_AEU_MASK_ATTN_FUNC_0;
5184
5185         bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_PORT0_ATT_MASK + port);
5186         aeu_mask = REG_RD(bp, reg_addr);
5187
5188         DP(NETIF_MSG_HW, "aeu_mask %x  newly deasserted %x\n",
5189            aeu_mask, deasserted);
5190         aeu_mask |= (deasserted & 0x3ff);
5191         DP(NETIF_MSG_HW, "new mask %x\n", aeu_mask);
5192
5193         REG_WR(bp, reg_addr, aeu_mask);
5194         bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_PORT0_ATT_MASK + port);
5195
5196         DP(NETIF_MSG_HW, "attn_state %x\n", bp->attn_state);
5197         bp->attn_state &= ~deasserted;
5198         DP(NETIF_MSG_HW, "new state %x\n", bp->attn_state);
5199 }
5200
5201 static void bnx2x_attn_int(struct bnx2x *bp)
5202 {
5203         /* read local copy of bits */
5204         u32 attn_bits = le32_to_cpu(bp->def_status_blk->atten_status_block.
5205                                                                 attn_bits);
5206         u32 attn_ack = le32_to_cpu(bp->def_status_blk->atten_status_block.
5207                                                                 attn_bits_ack);
5208         u32 attn_state = bp->attn_state;
5209
5210         /* look for changed bits */
5211         u32 asserted   =  attn_bits & ~attn_ack & ~attn_state;
5212         u32 deasserted = ~attn_bits &  attn_ack &  attn_state;
5213
5214         DP(NETIF_MSG_HW,
5215            "attn_bits %x  attn_ack %x  asserted %x  deasserted %x\n",
5216            attn_bits, attn_ack, asserted, deasserted);
5217
5218         if (~(attn_bits ^ attn_ack) & (attn_bits ^ attn_state))
5219                 BNX2X_ERR("BAD attention state\n");
5220
5221         /* handle bits that were raised */
5222         if (asserted)
5223                 bnx2x_attn_int_asserted(bp, asserted);
5224
5225         if (deasserted)
5226                 bnx2x_attn_int_deasserted(bp, deasserted);
5227 }
5228
5229 void bnx2x_igu_ack_sb(struct bnx2x *bp, u8 igu_sb_id, u8 segment,
5230                       u16 index, u8 op, u8 update)
5231 {
5232         u32 igu_addr = bp->igu_base_addr;
5233         igu_addr += (IGU_CMD_INT_ACK_BASE + igu_sb_id)*8;
5234         bnx2x_igu_ack_sb_gen(bp, igu_sb_id, segment, index, op, update,
5235                              igu_addr);
5236 }
5237
5238 static void bnx2x_update_eq_prod(struct bnx2x *bp, u16 prod)
5239 {
5240         /* No memory barriers */
5241         storm_memset_eq_prod(bp, prod, BP_FUNC(bp));
5242         mmiowb(); /* keep prod updates ordered */
5243 }
5244
5245 static int  bnx2x_cnic_handle_cfc_del(struct bnx2x *bp, u32 cid,
5246                                       union event_ring_elem *elem)
5247 {
5248         u8 err = elem->message.error;
5249
5250         if (!bp->cnic_eth_dev.starting_cid  ||
5251             (cid < bp->cnic_eth_dev.starting_cid &&
5252             cid != bp->cnic_eth_dev.iscsi_l2_cid))
5253                 return 1;
5254
5255         DP(BNX2X_MSG_SP, "got delete ramrod for CNIC CID %d\n", cid);
5256
5257         if (unlikely(err)) {
5258
5259                 BNX2X_ERR("got delete ramrod for CNIC CID %d with error!\n",
5260                           cid);
5261                 bnx2x_panic_dump(bp, false);
5262         }
5263         bnx2x_cnic_cfc_comp(bp, cid, err);
5264         return 0;
5265 }
5266
5267 static void bnx2x_handle_mcast_eqe(struct bnx2x *bp)
5268 {
5269         struct bnx2x_mcast_ramrod_params rparam;
5270         int rc;
5271
5272         memset(&rparam, 0, sizeof(rparam));
5273
5274         rparam.mcast_obj = &bp->mcast_obj;
5275
5276         netif_addr_lock_bh(bp->dev);
5277
5278         /* Clear pending state for the last command */
5279         bp->mcast_obj.raw.clear_pending(&bp->mcast_obj.raw);
5280
5281         /* If there are pending mcast commands - send them */
5282         if (bp->mcast_obj.check_pending(&bp->mcast_obj)) {
5283                 rc = bnx2x_config_mcast(bp, &rparam, BNX2X_MCAST_CMD_CONT);
5284                 if (rc < 0)
5285                         BNX2X_ERR("Failed to send pending mcast commands: %d\n",
5286                                   rc);
5287         }
5288
5289         netif_addr_unlock_bh(bp->dev);
5290 }
5291
5292 static void bnx2x_handle_classification_eqe(struct bnx2x *bp,
5293                                             union event_ring_elem *elem)
5294 {
5295         unsigned long ramrod_flags = 0;
5296         int rc = 0;
5297         u32 echo = le32_to_cpu(elem->message.data.eth_event.echo);
5298         u32 cid = echo & BNX2X_SWCID_MASK;
5299         struct bnx2x_vlan_mac_obj *vlan_mac_obj;
5300
5301         /* Always push next commands out, don't wait here */
5302         __set_bit(RAMROD_CONT, &ramrod_flags);
5303
5304         switch (echo >> BNX2X_SWCID_SHIFT) {
5305         case BNX2X_FILTER_MAC_PENDING:
5306                 DP(BNX2X_MSG_SP, "Got SETUP_MAC completions\n");
5307                 if (CNIC_LOADED(bp) && (cid == BNX2X_ISCSI_ETH_CID(bp)))
5308                         vlan_mac_obj = &bp->iscsi_l2_mac_obj;
5309                 else
5310                         vlan_mac_obj = &bp->sp_objs[cid].mac_obj;
5311
5312                 break;
5313         case BNX2X_FILTER_VLAN_PENDING:
5314                 DP(BNX2X_MSG_SP, "Got SETUP_VLAN completions\n");
5315                 vlan_mac_obj = &bp->sp_objs[cid].vlan_obj;
5316                 break;
5317         case BNX2X_FILTER_MCAST_PENDING:
5318                 DP(BNX2X_MSG_SP, "Got SETUP_MCAST completions\n");
5319                 /* This is only relevant for 57710 where multicast MACs are
5320                  * configured as unicast MACs using the same ramrod.
5321                  */
5322                 bnx2x_handle_mcast_eqe(bp);
5323                 return;
5324         default:
5325                 BNX2X_ERR("Unsupported classification command: 0x%x\n", echo);
5326                 return;
5327         }
5328
5329         rc = vlan_mac_obj->complete(bp, vlan_mac_obj, elem, &ramrod_flags);
5330
5331         if (rc < 0)
5332                 BNX2X_ERR("Failed to schedule new commands: %d\n", rc);
5333         else if (rc > 0)
5334                 DP(BNX2X_MSG_SP, "Scheduled next pending commands...\n");
5335 }
5336
5337 static void bnx2x_set_iscsi_eth_rx_mode(struct bnx2x *bp, bool start);
5338
5339 static void bnx2x_handle_rx_mode_eqe(struct bnx2x *bp)
5340 {
5341         netif_addr_lock_bh(bp->dev);
5342
5343         clear_bit(BNX2X_FILTER_RX_MODE_PENDING, &bp->sp_state);
5344
5345         /* Send rx_mode command again if was requested */
5346         if (test_and_clear_bit(BNX2X_FILTER_RX_MODE_SCHED, &bp->sp_state))
5347                 bnx2x_set_storm_rx_mode(bp);
5348         else if (test_and_clear_bit(BNX2X_FILTER_ISCSI_ETH_START_SCHED,
5349                                     &bp->sp_state))
5350                 bnx2x_set_iscsi_eth_rx_mode(bp, true);
5351         else if (test_and_clear_bit(BNX2X_FILTER_ISCSI_ETH_STOP_SCHED,
5352                                     &bp->sp_state))
5353                 bnx2x_set_iscsi_eth_rx_mode(bp, false);
5354
5355         netif_addr_unlock_bh(bp->dev);
5356 }
5357
5358 static void bnx2x_after_afex_vif_lists(struct bnx2x *bp,
5359                                               union event_ring_elem *elem)
5360 {
5361         if (elem->message.data.vif_list_event.echo == VIF_LIST_RULE_GET) {
5362                 DP(BNX2X_MSG_SP,
5363                    "afex: ramrod completed VIF LIST_GET, addrs 0x%x\n",
5364                    elem->message.data.vif_list_event.func_bit_map);
5365                 bnx2x_fw_command(bp, DRV_MSG_CODE_AFEX_LISTGET_ACK,
5366                         elem->message.data.vif_list_event.func_bit_map);
5367         } else if (elem->message.data.vif_list_event.echo ==
5368                    VIF_LIST_RULE_SET) {
5369                 DP(BNX2X_MSG_SP, "afex: ramrod completed VIF LIST_SET\n");
5370                 bnx2x_fw_command(bp, DRV_MSG_CODE_AFEX_LISTSET_ACK, 0);
5371         }
5372 }
5373
5374 /* called with rtnl_lock */
5375 static void bnx2x_after_function_update(struct bnx2x *bp)
5376 {
5377         int q, rc;
5378         struct bnx2x_fastpath *fp;
5379         struct bnx2x_queue_state_params queue_params = {NULL};
5380         struct bnx2x_queue_update_params *q_update_params =
5381                 &queue_params.params.update;
5382
5383         /* Send Q update command with afex vlan removal values for all Qs */
5384         queue_params.cmd = BNX2X_Q_CMD_UPDATE;
5385
5386         /* set silent vlan removal values according to vlan mode */
5387         __set_bit(BNX2X_Q_UPDATE_SILENT_VLAN_REM_CHNG,
5388                   &q_update_params->update_flags);
5389         __set_bit(BNX2X_Q_UPDATE_SILENT_VLAN_REM,
5390                   &q_update_params->update_flags);
5391         __set_bit(RAMROD_COMP_WAIT, &queue_params.ramrod_flags);
5392
5393         /* in access mode mark mask and value are 0 to strip all vlans */
5394         if (bp->afex_vlan_mode == FUNC_MF_CFG_AFEX_VLAN_ACCESS_MODE) {
5395                 q_update_params->silent_removal_value = 0;
5396                 q_update_params->silent_removal_mask = 0;
5397         } else {
5398                 q_update_params->silent_removal_value =
5399                         (bp->afex_def_vlan_tag & VLAN_VID_MASK);
5400                 q_update_params->silent_removal_mask = VLAN_VID_MASK;
5401         }
5402
5403         for_each_eth_queue(bp, q) {
5404                 /* Set the appropriate Queue object */
5405                 fp = &bp->fp[q];
5406                 queue_params.q_obj = &bnx2x_sp_obj(bp, fp).q_obj;
5407
5408                 /* send the ramrod */
5409                 rc = bnx2x_queue_state_change(bp, &queue_params);
5410                 if (rc < 0)
5411                         BNX2X_ERR("Failed to config silent vlan rem for Q %d\n",
5412                                   q);
5413         }
5414
5415         if (!NO_FCOE(bp) && CNIC_ENABLED(bp)) {
5416                 fp = &bp->fp[FCOE_IDX(bp)];
5417                 queue_params.q_obj = &bnx2x_sp_obj(bp, fp).q_obj;
5418
5419                 /* clear pending completion bit */
5420                 __clear_bit(RAMROD_COMP_WAIT, &queue_params.ramrod_flags);
5421
5422                 /* mark latest Q bit */
5423                 smp_mb__before_atomic();
5424                 set_bit(BNX2X_AFEX_FCOE_Q_UPDATE_PENDING, &bp->sp_state);
5425                 smp_mb__after_atomic();
5426
5427                 /* send Q update ramrod for FCoE Q */
5428                 rc = bnx2x_queue_state_change(bp, &queue_params);
5429                 if (rc < 0)
5430                         BNX2X_ERR("Failed to config silent vlan rem for Q %d\n",
5431                                   q);
5432         } else {
5433                 /* If no FCoE ring - ACK MCP now */
5434                 bnx2x_link_report(bp);
5435                 bnx2x_fw_command(bp, DRV_MSG_CODE_AFEX_VIFSET_ACK, 0);
5436         }
5437 }
5438
5439 static struct bnx2x_queue_sp_obj *bnx2x_cid_to_q_obj(
5440         struct bnx2x *bp, u32 cid)
5441 {
5442         DP(BNX2X_MSG_SP, "retrieving fp from cid %d\n", cid);
5443
5444         if (CNIC_LOADED(bp) && (cid == BNX2X_FCOE_ETH_CID(bp)))
5445                 return &bnx2x_fcoe_sp_obj(bp, q_obj);
5446         else
5447                 return &bp->sp_objs[CID_TO_FP(cid, bp)].q_obj;
5448 }
5449
5450 static void bnx2x_eq_int(struct bnx2x *bp)
5451 {
5452         u16 hw_cons, sw_cons, sw_prod;
5453         union event_ring_elem *elem;
5454         u8 echo;
5455         u32 cid;
5456         u8 opcode;
5457         int rc, spqe_cnt = 0;
5458         struct bnx2x_queue_sp_obj *q_obj;
5459         struct bnx2x_func_sp_obj *f_obj = &bp->func_obj;
5460         struct bnx2x_raw_obj *rss_raw = &bp->rss_conf_obj.raw;
5461
5462         hw_cons = le16_to_cpu(*bp->eq_cons_sb);
5463
5464         /* The hw_cos range is 1-255, 257 - the sw_cons range is 0-254, 256.
5465          * when we get the next-page we need to adjust so the loop
5466          * condition below will be met. The next element is the size of a
5467          * regular element and hence incrementing by 1
5468          */
5469         if ((hw_cons & EQ_DESC_MAX_PAGE) == EQ_DESC_MAX_PAGE)
5470                 hw_cons++;
5471
5472         /* This function may never run in parallel with itself for a
5473          * specific bp, thus there is no need in "paired" read memory
5474          * barrier here.
5475          */
5476         sw_cons = bp->eq_cons;
5477         sw_prod = bp->eq_prod;
5478
5479         DP(BNX2X_MSG_SP, "EQ:  hw_cons %u  sw_cons %u bp->eq_spq_left %x\n",
5480                         hw_cons, sw_cons, atomic_read(&bp->eq_spq_left));
5481
5482         for (; sw_cons != hw_cons;
5483               sw_prod = NEXT_EQ_IDX(sw_prod), sw_cons = NEXT_EQ_IDX(sw_cons)) {
5484
5485                 elem = &bp->eq_ring[EQ_DESC(sw_cons)];
5486
5487                 rc = bnx2x_iov_eq_sp_event(bp, elem);
5488                 if (!rc) {
5489                         DP(BNX2X_MSG_IOV, "bnx2x_iov_eq_sp_event returned %d\n",
5490                            rc);
5491                         goto next_spqe;
5492                 }
5493
5494                 opcode = elem->message.opcode;
5495
5496                 /* handle eq element */
5497                 switch (opcode) {
5498                 case EVENT_RING_OPCODE_VF_PF_CHANNEL:
5499                         bnx2x_vf_mbx_schedule(bp,
5500                                               &elem->message.data.vf_pf_event);
5501                         continue;
5502
5503                 case EVENT_RING_OPCODE_STAT_QUERY:
5504                         DP_AND((BNX2X_MSG_SP | BNX2X_MSG_STATS),
5505                                "got statistics comp event %d\n",
5506                                bp->stats_comp++);
5507                         /* nothing to do with stats comp */
5508                         goto next_spqe;
5509
5510                 case EVENT_RING_OPCODE_CFC_DEL:
5511                         /* handle according to cid range */
5512                         /*
5513                          * we may want to verify here that the bp state is
5514                          * HALTING
5515                          */
5516
5517                         /* elem CID originates from FW; actually LE */
5518                         cid = SW_CID(elem->message.data.cfc_del_event.cid);
5519
5520                         DP(BNX2X_MSG_SP,
5521                            "got delete ramrod for MULTI[%d]\n", cid);
5522
5523                         if (CNIC_LOADED(bp) &&
5524                             !bnx2x_cnic_handle_cfc_del(bp, cid, elem))
5525                                 goto next_spqe;
5526
5527                         q_obj = bnx2x_cid_to_q_obj(bp, cid);
5528
5529                         if (q_obj->complete_cmd(bp, q_obj, BNX2X_Q_CMD_CFC_DEL))
5530                                 break;
5531
5532                         goto next_spqe;
5533
5534                 case EVENT_RING_OPCODE_STOP_TRAFFIC:
5535                         DP(BNX2X_MSG_SP | BNX2X_MSG_DCB, "got STOP TRAFFIC\n");
5536                         bnx2x_dcbx_set_params(bp, BNX2X_DCBX_STATE_TX_PAUSED);
5537                         if (f_obj->complete_cmd(bp, f_obj,
5538                                                 BNX2X_F_CMD_TX_STOP))
5539                                 break;
5540                         goto next_spqe;
5541
5542                 case EVENT_RING_OPCODE_START_TRAFFIC:
5543                         DP(BNX2X_MSG_SP | BNX2X_MSG_DCB, "got START TRAFFIC\n");
5544                         bnx2x_dcbx_set_params(bp, BNX2X_DCBX_STATE_TX_RELEASED);
5545                         if (f_obj->complete_cmd(bp, f_obj,
5546                                                 BNX2X_F_CMD_TX_START))
5547                                 break;
5548                         goto next_spqe;
5549
5550                 case EVENT_RING_OPCODE_FUNCTION_UPDATE:
5551                         echo = elem->message.data.function_update_event.echo;
5552                         if (echo == SWITCH_UPDATE) {
5553                                 DP(BNX2X_MSG_SP | NETIF_MSG_IFUP,
5554                                    "got FUNC_SWITCH_UPDATE ramrod\n");
5555                                 if (f_obj->complete_cmd(
5556                                         bp, f_obj, BNX2X_F_CMD_SWITCH_UPDATE))
5557                                         break;
5558
5559                         } else {
5560                                 int cmd = BNX2X_SP_RTNL_AFEX_F_UPDATE;
5561
5562                                 DP(BNX2X_MSG_SP | BNX2X_MSG_MCP,
5563                                    "AFEX: ramrod completed FUNCTION_UPDATE\n");
5564                                 f_obj->complete_cmd(bp, f_obj,
5565                                                     BNX2X_F_CMD_AFEX_UPDATE);
5566
5567                                 /* We will perform the Queues update from
5568                                  * sp_rtnl task as all Queue SP operations
5569                                  * should run under rtnl_lock.
5570                                  */
5571                                 bnx2x_schedule_sp_rtnl(bp, cmd, 0);
5572                         }
5573
5574                         goto next_spqe;
5575
5576                 case EVENT_RING_OPCODE_AFEX_VIF_LISTS:
5577                         f_obj->complete_cmd(bp, f_obj,
5578                                             BNX2X_F_CMD_AFEX_VIFLISTS);
5579                         bnx2x_after_afex_vif_lists(bp, elem);
5580                         goto next_spqe;
5581                 case EVENT_RING_OPCODE_FUNCTION_START:
5582                         DP(BNX2X_MSG_SP | NETIF_MSG_IFUP,
5583                            "got FUNC_START ramrod\n");
5584                         if (f_obj->complete_cmd(bp, f_obj, BNX2X_F_CMD_START))
5585                                 break;
5586
5587                         goto next_spqe;
5588
5589                 case EVENT_RING_OPCODE_FUNCTION_STOP:
5590                         DP(BNX2X_MSG_SP | NETIF_MSG_IFUP,
5591                            "got FUNC_STOP ramrod\n");
5592                         if (f_obj->complete_cmd(bp, f_obj, BNX2X_F_CMD_STOP))
5593                                 break;
5594
5595                         goto next_spqe;
5596
5597                 case EVENT_RING_OPCODE_SET_TIMESYNC:
5598                         DP(BNX2X_MSG_SP | BNX2X_MSG_PTP,
5599                            "got set_timesync ramrod completion\n");
5600                         if (f_obj->complete_cmd(bp, f_obj,
5601                                                 BNX2X_F_CMD_SET_TIMESYNC))
5602                                 break;
5603                         goto next_spqe;
5604                 }
5605
5606                 switch (opcode | bp->state) {
5607                 case (EVENT_RING_OPCODE_RSS_UPDATE_RULES |
5608                       BNX2X_STATE_OPEN):
5609                 case (EVENT_RING_OPCODE_RSS_UPDATE_RULES |
5610                       BNX2X_STATE_OPENING_WAIT4_PORT):
5611                 case (EVENT_RING_OPCODE_RSS_UPDATE_RULES |
5612                       BNX2X_STATE_CLOSING_WAIT4_HALT):
5613                         DP(BNX2X_MSG_SP, "got RSS_UPDATE ramrod. CID %d\n",
5614                            SW_CID(elem->message.data.eth_event.echo));
5615                         rss_raw->clear_pending(rss_raw);
5616                         break;
5617
5618                 case (EVENT_RING_OPCODE_SET_MAC | BNX2X_STATE_OPEN):
5619                 case (EVENT_RING_OPCODE_SET_MAC | BNX2X_STATE_DIAG):
5620                 case (EVENT_RING_OPCODE_SET_MAC |
5621                       BNX2X_STATE_CLOSING_WAIT4_HALT):
5622                 case (EVENT_RING_OPCODE_CLASSIFICATION_RULES |
5623                       BNX2X_STATE_OPEN):
5624                 case (EVENT_RING_OPCODE_CLASSIFICATION_RULES |
5625                       BNX2X_STATE_DIAG):
5626                 case (EVENT_RING_OPCODE_CLASSIFICATION_RULES |
5627                       BNX2X_STATE_CLOSING_WAIT4_HALT):
5628                         DP(BNX2X_MSG_SP, "got (un)set vlan/mac ramrod\n");
5629                         bnx2x_handle_classification_eqe(bp, elem);
5630                         break;
5631
5632                 case (EVENT_RING_OPCODE_MULTICAST_RULES |
5633                       BNX2X_STATE_OPEN):
5634                 case (EVENT_RING_OPCODE_MULTICAST_RULES |
5635                       BNX2X_STATE_DIAG):
5636                 case (EVENT_RING_OPCODE_MULTICAST_RULES |
5637                       BNX2X_STATE_CLOSING_WAIT4_HALT):
5638                         DP(BNX2X_MSG_SP, "got mcast ramrod\n");
5639                         bnx2x_handle_mcast_eqe(bp);
5640                         break;
5641
5642                 case (EVENT_RING_OPCODE_FILTERS_RULES |
5643                       BNX2X_STATE_OPEN):
5644                 case (EVENT_RING_OPCODE_FILTERS_RULES |
5645                       BNX2X_STATE_DIAG):
5646                 case (EVENT_RING_OPCODE_FILTERS_RULES |
5647                       BNX2X_STATE_CLOSING_WAIT4_HALT):
5648                         DP(BNX2X_MSG_SP, "got rx_mode ramrod\n");
5649                         bnx2x_handle_rx_mode_eqe(bp);
5650                         break;
5651                 default:
5652                         /* unknown event log error and continue */
5653                         BNX2X_ERR("Unknown EQ event %d, bp->state 0x%x\n",
5654                                   elem->message.opcode, bp->state);
5655                 }
5656 next_spqe:
5657                 spqe_cnt++;
5658         } /* for */
5659
5660         smp_mb__before_atomic();
5661         atomic_add(spqe_cnt, &bp->eq_spq_left);
5662
5663         bp->eq_cons = sw_cons;
5664         bp->eq_prod = sw_prod;
5665         /* Make sure that above mem writes were issued towards the memory */
5666         smp_wmb();
5667
5668         /* update producer */
5669         bnx2x_update_eq_prod(bp, bp->eq_prod);
5670 }
5671
5672 static void bnx2x_sp_task(struct work_struct *work)
5673 {
5674         struct bnx2x *bp = container_of(work, struct bnx2x, sp_task.work);
5675
5676         DP(BNX2X_MSG_SP, "sp task invoked\n");
5677
5678         /* make sure the atomic interrupt_occurred has been written */
5679         smp_rmb();
5680         if (atomic_read(&bp->interrupt_occurred)) {
5681
5682                 /* what work needs to be performed? */
5683                 u16 status = bnx2x_update_dsb_idx(bp);
5684
5685                 DP(BNX2X_MSG_SP, "status %x\n", status);
5686                 DP(BNX2X_MSG_SP, "setting interrupt_occurred to 0\n");
5687                 atomic_set(&bp->interrupt_occurred, 0);
5688
5689                 /* HW attentions */
5690                 if (status & BNX2X_DEF_SB_ATT_IDX) {
5691                         bnx2x_attn_int(bp);
5692                         status &= ~BNX2X_DEF_SB_ATT_IDX;
5693                 }
5694
5695                 /* SP events: STAT_QUERY and others */
5696                 if (status & BNX2X_DEF_SB_IDX) {
5697                         struct bnx2x_fastpath *fp = bnx2x_fcoe_fp(bp);
5698
5699                         if (FCOE_INIT(bp) &&
5700                             (bnx2x_has_rx_work(fp) || bnx2x_has_tx_work(fp))) {
5701                                 /* Prevent local bottom-halves from running as
5702                                  * we are going to change the local NAPI list.
5703                                  */
5704                                 local_bh_disable();
5705                                 napi_schedule(&bnx2x_fcoe(bp, napi));
5706                                 local_bh_enable();
5707                         }
5708
5709                         /* Handle EQ completions */
5710                         bnx2x_eq_int(bp);
5711                         bnx2x_ack_sb(bp, bp->igu_dsb_id, USTORM_ID,
5712                                      le16_to_cpu(bp->def_idx), IGU_INT_NOP, 1);
5713
5714                         status &= ~BNX2X_DEF_SB_IDX;
5715                 }
5716
5717                 /* if status is non zero then perhaps something went wrong */
5718                 if (unlikely(status))
5719                         DP(BNX2X_MSG_SP,
5720                            "got an unknown interrupt! (status 0x%x)\n", status);
5721
5722                 /* ack status block only if something was actually handled */
5723                 bnx2x_ack_sb(bp, bp->igu_dsb_id, ATTENTION_ID,
5724                              le16_to_cpu(bp->def_att_idx), IGU_INT_ENABLE, 1);
5725         }
5726
5727         /* afex - poll to check if VIFSET_ACK should be sent to MFW */
5728         if (test_and_clear_bit(BNX2X_AFEX_PENDING_VIFSET_MCP_ACK,
5729                                &bp->sp_state)) {
5730                 bnx2x_link_report(bp);
5731                 bnx2x_fw_command(bp, DRV_MSG_CODE_AFEX_VIFSET_ACK, 0);
5732         }
5733 }
5734
5735 irqreturn_t bnx2x_msix_sp_int(int irq, void *dev_instance)
5736 {
5737         struct net_device *dev = dev_instance;
5738         struct bnx2x *bp = netdev_priv(dev);
5739
5740         bnx2x_ack_sb(bp, bp->igu_dsb_id, USTORM_ID, 0,
5741                      IGU_INT_DISABLE, 0);
5742
5743 #ifdef BNX2X_STOP_ON_ERROR
5744         if (unlikely(bp->panic))
5745                 return IRQ_HANDLED;
5746 #endif
5747
5748         if (CNIC_LOADED(bp)) {
5749                 struct cnic_ops *c_ops;
5750
5751                 rcu_read_lock();
5752                 c_ops = rcu_dereference(bp->cnic_ops);
5753                 if (c_ops)
5754                         c_ops->cnic_handler(bp->cnic_data, NULL);
5755                 rcu_read_unlock();
5756         }
5757
5758         /* schedule sp task to perform default status block work, ack
5759          * attentions and enable interrupts.
5760          */
5761         bnx2x_schedule_sp_task(bp);
5762
5763         return IRQ_HANDLED;
5764 }
5765
5766 /* end of slow path */
5767
5768 void bnx2x_drv_pulse(struct bnx2x *bp)
5769 {
5770         SHMEM_WR(bp, func_mb[BP_FW_MB_IDX(bp)].drv_pulse_mb,
5771                  bp->fw_drv_pulse_wr_seq);
5772 }
5773
5774 static void bnx2x_timer(struct timer_list *t)
5775 {
5776         struct bnx2x *bp = from_timer(bp, t, timer);
5777
5778         if (!netif_running(bp->dev))
5779                 return;
5780
5781         if (IS_PF(bp) &&
5782             !BP_NOMCP(bp)) {
5783                 int mb_idx = BP_FW_MB_IDX(bp);
5784                 u16 drv_pulse;
5785                 u16 mcp_pulse;
5786
5787                 ++bp->fw_drv_pulse_wr_seq;
5788                 bp->fw_drv_pulse_wr_seq &= DRV_PULSE_SEQ_MASK;
5789                 drv_pulse = bp->fw_drv_pulse_wr_seq;
5790                 bnx2x_drv_pulse(bp);
5791
5792                 mcp_pulse = (SHMEM_RD(bp, func_mb[mb_idx].mcp_pulse_mb) &
5793                              MCP_PULSE_SEQ_MASK);
5794                 /* The delta between driver pulse and mcp response
5795                  * should not get too big. If the MFW is more than 5 pulses
5796                  * behind, we should worry about it enough to generate an error
5797                  * log.
5798                  */
5799                 if (((drv_pulse - mcp_pulse) & MCP_PULSE_SEQ_MASK) > 5)
5800                         BNX2X_ERR("MFW seems hanged: drv_pulse (0x%x) != mcp_pulse (0x%x)\n",
5801                                   drv_pulse, mcp_pulse);
5802         }
5803
5804         if (bp->state == BNX2X_STATE_OPEN)
5805                 bnx2x_stats_handle(bp, STATS_EVENT_UPDATE);
5806
5807         /* sample pf vf bulletin board for new posts from pf */
5808         if (IS_VF(bp))
5809                 bnx2x_timer_sriov(bp);
5810
5811         mod_timer(&bp->timer, jiffies + bp->current_interval);
5812 }
5813
5814 /* end of Statistics */
5815
5816 /* nic init */
5817
5818 /*
5819  * nic init service functions
5820  */
5821
5822 static void bnx2x_fill(struct bnx2x *bp, u32 addr, int fill, u32 len)
5823 {
5824         u32 i;
5825         if (!(len%4) && !(addr%4))
5826                 for (i = 0; i < len; i += 4)
5827                         REG_WR(bp, addr + i, fill);
5828         else
5829                 for (i = 0; i < len; i++)
5830                         REG_WR8(bp, addr + i, fill);
5831 }
5832
5833 /* helper: writes FP SP data to FW - data_size in dwords */
5834 static void bnx2x_wr_fp_sb_data(struct bnx2x *bp,
5835                                 int fw_sb_id,
5836                                 u32 *sb_data_p,
5837                                 u32 data_size)
5838 {
5839         int index;
5840         for (index = 0; index < data_size; index++)
5841                 REG_WR(bp, BAR_CSTRORM_INTMEM +
5842                         CSTORM_STATUS_BLOCK_DATA_OFFSET(fw_sb_id) +
5843                         sizeof(u32)*index,
5844                         *(sb_data_p + index));
5845 }
5846
5847 static void bnx2x_zero_fp_sb(struct bnx2x *bp, int fw_sb_id)
5848 {
5849         u32 *sb_data_p;
5850         u32 data_size = 0;
5851         struct hc_status_block_data_e2 sb_data_e2;
5852         struct hc_status_block_data_e1x sb_data_e1x;
5853
5854         /* disable the function first */
5855         if (!CHIP_IS_E1x(bp)) {
5856                 memset(&sb_data_e2, 0, sizeof(struct hc_status_block_data_e2));
5857                 sb_data_e2.common.state = SB_DISABLED;
5858                 sb_data_e2.common.p_func.vf_valid = false;
5859                 sb_data_p = (u32 *)&sb_data_e2;
5860                 data_size = sizeof(struct hc_status_block_data_e2)/sizeof(u32);
5861         } else {
5862                 memset(&sb_data_e1x, 0,
5863                        sizeof(struct hc_status_block_data_e1x));
5864                 sb_data_e1x.common.state = SB_DISABLED;
5865                 sb_data_e1x.common.p_func.vf_valid = false;
5866                 sb_data_p = (u32 *)&sb_data_e1x;
5867                 data_size = sizeof(struct hc_status_block_data_e1x)/sizeof(u32);
5868         }
5869         bnx2x_wr_fp_sb_data(bp, fw_sb_id, sb_data_p, data_size);
5870
5871         bnx2x_fill(bp, BAR_CSTRORM_INTMEM +
5872                         CSTORM_STATUS_BLOCK_OFFSET(fw_sb_id), 0,
5873                         CSTORM_STATUS_BLOCK_SIZE);
5874         bnx2x_fill(bp, BAR_CSTRORM_INTMEM +
5875                         CSTORM_SYNC_BLOCK_OFFSET(fw_sb_id), 0,
5876                         CSTORM_SYNC_BLOCK_SIZE);
5877 }
5878
5879 /* helper:  writes SP SB data to FW */
5880 static void bnx2x_wr_sp_sb_data(struct bnx2x *bp,
5881                 struct hc_sp_status_block_data *sp_sb_data)
5882 {
5883         int func = BP_FUNC(bp);
5884         int i;
5885         for (i = 0; i < sizeof(struct hc_sp_status_block_data)/sizeof(u32); i++)
5886                 REG_WR(bp, BAR_CSTRORM_INTMEM +
5887                         CSTORM_SP_STATUS_BLOCK_DATA_OFFSET(func) +
5888                         i*sizeof(u32),
5889                         *((u32 *)sp_sb_data + i));
5890 }
5891
5892 static void bnx2x_zero_sp_sb(struct bnx2x *bp)
5893 {
5894         int func = BP_FUNC(bp);
5895         struct hc_sp_status_block_data sp_sb_data;
5896         memset(&sp_sb_data, 0, sizeof(struct hc_sp_status_block_data));
5897
5898         sp_sb_data.state = SB_DISABLED;
5899         sp_sb_data.p_func.vf_valid = false;
5900
5901         bnx2x_wr_sp_sb_data(bp, &sp_sb_data);
5902
5903         bnx2x_fill(bp, BAR_CSTRORM_INTMEM +
5904                         CSTORM_SP_STATUS_BLOCK_OFFSET(func), 0,
5905                         CSTORM_SP_STATUS_BLOCK_SIZE);
5906         bnx2x_fill(bp, BAR_CSTRORM_INTMEM +
5907                         CSTORM_SP_SYNC_BLOCK_OFFSET(func), 0,
5908                         CSTORM_SP_SYNC_BLOCK_SIZE);
5909 }
5910
5911 static void bnx2x_setup_ndsb_state_machine(struct hc_status_block_sm *hc_sm,
5912                                            int igu_sb_id, int igu_seg_id)
5913 {
5914         hc_sm->igu_sb_id = igu_sb_id;
5915         hc_sm->igu_seg_id = igu_seg_id;
5916         hc_sm->timer_value = 0xFF;
5917         hc_sm->time_to_expire = 0xFFFFFFFF;
5918 }
5919
5920 /* allocates state machine ids. */
5921 static void bnx2x_map_sb_state_machines(struct hc_index_data *index_data)
5922 {
5923         /* zero out state machine indices */
5924         /* rx indices */
5925         index_data[HC_INDEX_ETH_RX_CQ_CONS].flags &= ~HC_INDEX_DATA_SM_ID;
5926
5927         /* tx indices */
5928         index_data[HC_INDEX_OOO_TX_CQ_CONS].flags &= ~HC_INDEX_DATA_SM_ID;
5929         index_data[HC_INDEX_ETH_TX_CQ_CONS_COS0].flags &= ~HC_INDEX_DATA_SM_ID;
5930         index_data[HC_INDEX_ETH_TX_CQ_CONS_COS1].flags &= ~HC_INDEX_DATA_SM_ID;
5931         index_data[HC_INDEX_ETH_TX_CQ_CONS_COS2].flags &= ~HC_INDEX_DATA_SM_ID;
5932
5933         /* map indices */
5934         /* rx indices */
5935         index_data[HC_INDEX_ETH_RX_CQ_CONS].flags |=
5936                 SM_RX_ID << HC_INDEX_DATA_SM_ID_SHIFT;
5937
5938         /* tx indices */
5939         index_data[HC_INDEX_OOO_TX_CQ_CONS].flags |=
5940                 SM_TX_ID << HC_INDEX_DATA_SM_ID_SHIFT;
5941         index_data[HC_INDEX_ETH_TX_CQ_CONS_COS0].flags |=
5942                 SM_TX_ID << HC_INDEX_DATA_SM_ID_SHIFT;
5943         index_data[HC_INDEX_ETH_TX_CQ_CONS_COS1].flags |=
5944                 SM_TX_ID << HC_INDEX_DATA_SM_ID_SHIFT;
5945         index_data[HC_INDEX_ETH_TX_CQ_CONS_COS2].flags |=
5946                 SM_TX_ID << HC_INDEX_DATA_SM_ID_SHIFT;
5947 }
5948
5949 void bnx2x_init_sb(struct bnx2x *bp, dma_addr_t mapping, int vfid,
5950                           u8 vf_valid, int fw_sb_id, int igu_sb_id)
5951 {
5952         int igu_seg_id;
5953
5954         struct hc_status_block_data_e2 sb_data_e2;
5955         struct hc_status_block_data_e1x sb_data_e1x;
5956         struct hc_status_block_sm  *hc_sm_p;
5957         int data_size;
5958         u32 *sb_data_p;
5959
5960         if (CHIP_INT_MODE_IS_BC(bp))
5961                 igu_seg_id = HC_SEG_ACCESS_NORM;
5962         else
5963                 igu_seg_id = IGU_SEG_ACCESS_NORM;
5964
5965         bnx2x_zero_fp_sb(bp, fw_sb_id);
5966
5967         if (!CHIP_IS_E1x(bp)) {
5968                 memset(&sb_data_e2, 0, sizeof(struct hc_status_block_data_e2));
5969                 sb_data_e2.common.state = SB_ENABLED;
5970                 sb_data_e2.common.p_func.pf_id = BP_FUNC(bp);
5971                 sb_data_e2.common.p_func.vf_id = vfid;
5972                 sb_data_e2.common.p_func.vf_valid = vf_valid;
5973                 sb_data_e2.common.p_func.vnic_id = BP_VN(bp);
5974                 sb_data_e2.common.same_igu_sb_1b = true;
5975                 sb_data_e2.common.host_sb_addr.hi = U64_HI(mapping);
5976                 sb_data_e2.common.host_sb_addr.lo = U64_LO(mapping);
5977                 hc_sm_p = sb_data_e2.common.state_machine;
5978                 sb_data_p = (u32 *)&sb_data_e2;
5979                 data_size = sizeof(struct hc_status_block_data_e2)/sizeof(u32);
5980                 bnx2x_map_sb_state_machines(sb_data_e2.index_data);
5981         } else {
5982                 memset(&sb_data_e1x, 0,
5983                        sizeof(struct hc_status_block_data_e1x));
5984                 sb_data_e1x.common.state = SB_ENABLED;
5985                 sb_data_e1x.common.p_func.pf_id = BP_FUNC(bp);
5986                 sb_data_e1x.common.p_func.vf_id = 0xff;
5987                 sb_data_e1x.common.p_func.vf_valid = false;
5988                 sb_data_e1x.common.p_func.vnic_id = BP_VN(bp);
5989                 sb_data_e1x.common.same_igu_sb_1b = true;
5990                 sb_data_e1x.common.host_sb_addr.hi = U64_HI(mapping);
5991                 sb_data_e1x.common.host_sb_addr.lo = U64_LO(mapping);
5992                 hc_sm_p = sb_data_e1x.common.state_machine;
5993                 sb_data_p = (u32 *)&sb_data_e1x;
5994                 data_size = sizeof(struct hc_status_block_data_e1x)/sizeof(u32);
5995                 bnx2x_map_sb_state_machines(sb_data_e1x.index_data);
5996         }
5997
5998         bnx2x_setup_ndsb_state_machine(&hc_sm_p[SM_RX_ID],
5999                                        igu_sb_id, igu_seg_id);
6000         bnx2x_setup_ndsb_state_machine(&hc_sm_p[SM_TX_ID],
6001                                        igu_sb_id, igu_seg_id);
6002
6003         DP(NETIF_MSG_IFUP, "Init FW SB %d\n", fw_sb_id);
6004
6005         /* write indices to HW - PCI guarantees endianity of regpairs */
6006         bnx2x_wr_fp_sb_data(bp, fw_sb_id, sb_data_p, data_size);
6007 }
6008
6009 static void bnx2x_update_coalesce_sb(struct bnx2x *bp, u8 fw_sb_id,
6010                                      u16 tx_usec, u16 rx_usec)
6011 {
6012         bnx2x_update_coalesce_sb_index(bp, fw_sb_id, HC_INDEX_ETH_RX_CQ_CONS,
6013                                     false, rx_usec);
6014         bnx2x_update_coalesce_sb_index(bp, fw_sb_id,
6015                                        HC_INDEX_ETH_TX_CQ_CONS_COS0, false,
6016                                        tx_usec);
6017         bnx2x_update_coalesce_sb_index(bp, fw_sb_id,
6018                                        HC_INDEX_ETH_TX_CQ_CONS_COS1, false,
6019                                        tx_usec);
6020         bnx2x_update_coalesce_sb_index(bp, fw_sb_id,
6021                                        HC_INDEX_ETH_TX_CQ_CONS_COS2, false,
6022                                        tx_usec);
6023 }
6024
6025 static void bnx2x_init_def_sb(struct bnx2x *bp)
6026 {
6027         struct host_sp_status_block *def_sb = bp->def_status_blk;
6028         dma_addr_t mapping = bp->def_status_blk_mapping;
6029         int igu_sp_sb_index;
6030         int igu_seg_id;
6031         int port = BP_PORT(bp);
6032         int func = BP_FUNC(bp);
6033         int reg_offset, reg_offset_en5;
6034         u64 section;
6035         int index;
6036         struct hc_sp_status_block_data sp_sb_data;
6037         memset(&sp_sb_data, 0, sizeof(struct hc_sp_status_block_data));
6038
6039         if (CHIP_INT_MODE_IS_BC(bp)) {
6040                 igu_sp_sb_index = DEF_SB_IGU_ID;
6041                 igu_seg_id = HC_SEG_ACCESS_DEF;
6042         } else {
6043                 igu_sp_sb_index = bp->igu_dsb_id;
6044                 igu_seg_id = IGU_SEG_ACCESS_DEF;
6045         }
6046
6047         /* ATTN */
6048         section = ((u64)mapping) + offsetof(struct host_sp_status_block,
6049                                             atten_status_block);
6050         def_sb->atten_status_block.status_block_id = igu_sp_sb_index;
6051
6052         bp->attn_state = 0;
6053
6054         reg_offset = (port ? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_0 :
6055                              MISC_REG_AEU_ENABLE1_FUNC_0_OUT_0);
6056         reg_offset_en5 = (port ? MISC_REG_AEU_ENABLE5_FUNC_1_OUT_0 :
6057                                  MISC_REG_AEU_ENABLE5_FUNC_0_OUT_0);
6058         for (index = 0; index < MAX_DYNAMIC_ATTN_GRPS; index++) {
6059                 int sindex;
6060                 /* take care of sig[0]..sig[4] */
6061                 for (sindex = 0; sindex < 4; sindex++)
6062                         bp->attn_group[index].sig[sindex] =
6063                            REG_RD(bp, reg_offset + sindex*0x4 + 0x10*index);
6064
6065                 if (!CHIP_IS_E1x(bp))
6066                         /*
6067                          * enable5 is separate from the rest of the registers,
6068                          * and therefore the address skip is 4
6069                          * and not 16 between the different groups
6070                          */
6071                         bp->attn_group[index].sig[4] = REG_RD(bp,
6072                                         reg_offset_en5 + 0x4*index);
6073                 else
6074                         bp->attn_group[index].sig[4] = 0;
6075         }
6076
6077         if (bp->common.int_block == INT_BLOCK_HC) {
6078                 reg_offset = (port ? HC_REG_ATTN_MSG1_ADDR_L :
6079                                      HC_REG_ATTN_MSG0_ADDR_L);
6080
6081                 REG_WR(bp, reg_offset, U64_LO(section));
6082                 REG_WR(bp, reg_offset + 4, U64_HI(section));
6083         } else if (!CHIP_IS_E1x(bp)) {
6084                 REG_WR(bp, IGU_REG_ATTN_MSG_ADDR_L, U64_LO(section));
6085                 REG_WR(bp, IGU_REG_ATTN_MSG_ADDR_H, U64_HI(section));
6086         }
6087
6088         section = ((u64)mapping) + offsetof(struct host_sp_status_block,
6089                                             sp_sb);
6090
6091         bnx2x_zero_sp_sb(bp);
6092
6093         /* PCI guarantees endianity of regpairs */
6094         sp_sb_data.state                = SB_ENABLED;
6095         sp_sb_data.host_sb_addr.lo      = U64_LO(section);
6096         sp_sb_data.host_sb_addr.hi      = U64_HI(section);
6097         sp_sb_data.igu_sb_id            = igu_sp_sb_index;
6098         sp_sb_data.igu_seg_id           = igu_seg_id;
6099         sp_sb_data.p_func.pf_id         = func;
6100         sp_sb_data.p_func.vnic_id       = BP_VN(bp);
6101         sp_sb_data.p_func.vf_id         = 0xff;
6102
6103         bnx2x_wr_sp_sb_data(bp, &sp_sb_data);
6104
6105         bnx2x_ack_sb(bp, bp->igu_dsb_id, USTORM_ID, 0, IGU_INT_ENABLE, 0);
6106 }
6107
6108 void bnx2x_update_coalesce(struct bnx2x *bp)
6109 {
6110         int i;
6111
6112         for_each_eth_queue(bp, i)
6113                 bnx2x_update_coalesce_sb(bp, bp->fp[i].fw_sb_id,
6114                                          bp->tx_ticks, bp->rx_ticks);
6115 }
6116
6117 static void bnx2x_init_sp_ring(struct bnx2x *bp)
6118 {
6119         spin_lock_init(&bp->spq_lock);
6120         atomic_set(&bp->cq_spq_left, MAX_SPQ_PENDING);
6121
6122         bp->spq_prod_idx = 0;
6123         bp->dsb_sp_prod = BNX2X_SP_DSB_INDEX;
6124         bp->spq_prod_bd = bp->spq;
6125         bp->spq_last_bd = bp->spq_prod_bd + MAX_SP_DESC_CNT;
6126 }
6127
6128 static void bnx2x_init_eq_ring(struct bnx2x *bp)
6129 {
6130         int i;
6131         for (i = 1; i <= NUM_EQ_PAGES; i++) {
6132                 union event_ring_elem *elem =
6133                         &bp->eq_ring[EQ_DESC_CNT_PAGE * i - 1];
6134
6135                 elem->next_page.addr.hi =
6136                         cpu_to_le32(U64_HI(bp->eq_mapping +
6137                                    BCM_PAGE_SIZE * (i % NUM_EQ_PAGES)));
6138                 elem->next_page.addr.lo =
6139                         cpu_to_le32(U64_LO(bp->eq_mapping +
6140                                    BCM_PAGE_SIZE*(i % NUM_EQ_PAGES)));
6141         }
6142         bp->eq_cons = 0;
6143         bp->eq_prod = NUM_EQ_DESC;
6144         bp->eq_cons_sb = BNX2X_EQ_INDEX;
6145         /* we want a warning message before it gets wrought... */
6146         atomic_set(&bp->eq_spq_left,
6147                 min_t(int, MAX_SP_DESC_CNT - MAX_SPQ_PENDING, NUM_EQ_DESC) - 1);
6148 }
6149
6150 /* called with netif_addr_lock_bh() */
6151 static int bnx2x_set_q_rx_mode(struct bnx2x *bp, u8 cl_id,
6152                                unsigned long rx_mode_flags,
6153                                unsigned long rx_accept_flags,
6154                                unsigned long tx_accept_flags,
6155                                unsigned long ramrod_flags)
6156 {
6157         struct bnx2x_rx_mode_ramrod_params ramrod_param;
6158         int rc;
6159
6160         memset(&ramrod_param, 0, sizeof(ramrod_param));
6161
6162         /* Prepare ramrod parameters */
6163         ramrod_param.cid = 0;
6164         ramrod_param.cl_id = cl_id;
6165         ramrod_param.rx_mode_obj = &bp->rx_mode_obj;
6166         ramrod_param.func_id = BP_FUNC(bp);
6167
6168         ramrod_param.pstate = &bp->sp_state;
6169         ramrod_param.state = BNX2X_FILTER_RX_MODE_PENDING;
6170
6171         ramrod_param.rdata = bnx2x_sp(bp, rx_mode_rdata);
6172         ramrod_param.rdata_mapping = bnx2x_sp_mapping(bp, rx_mode_rdata);
6173
6174         set_bit(BNX2X_FILTER_RX_MODE_PENDING, &bp->sp_state);
6175
6176         ramrod_param.ramrod_flags = ramrod_flags;
6177         ramrod_param.rx_mode_flags = rx_mode_flags;
6178
6179         ramrod_param.rx_accept_flags = rx_accept_flags;
6180         ramrod_param.tx_accept_flags = tx_accept_flags;
6181
6182         rc = bnx2x_config_rx_mode(bp, &ramrod_param);
6183         if (rc < 0) {
6184                 BNX2X_ERR("Set rx_mode %d failed\n", bp->rx_mode);
6185                 return rc;
6186         }
6187
6188         return 0;
6189 }
6190
6191 static int bnx2x_fill_accept_flags(struct bnx2x *bp, u32 rx_mode,
6192                                    unsigned long *rx_accept_flags,
6193                                    unsigned long *tx_accept_flags)
6194 {
6195         /* Clear the flags first */
6196         *rx_accept_flags = 0;
6197         *tx_accept_flags = 0;
6198
6199         switch (rx_mode) {
6200         case BNX2X_RX_MODE_NONE:
6201                 /*
6202                  * 'drop all' supersedes any accept flags that may have been
6203                  * passed to the function.
6204                  */
6205                 break;
6206         case BNX2X_RX_MODE_NORMAL:
6207                 __set_bit(BNX2X_ACCEPT_UNICAST, rx_accept_flags);
6208                 __set_bit(BNX2X_ACCEPT_MULTICAST, rx_accept_flags);
6209                 __set_bit(BNX2X_ACCEPT_BROADCAST, rx_accept_flags);
6210
6211                 /* internal switching mode */
6212                 __set_bit(BNX2X_ACCEPT_UNICAST, tx_accept_flags);
6213                 __set_bit(BNX2X_ACCEPT_MULTICAST, tx_accept_flags);
6214                 __set_bit(BNX2X_ACCEPT_BROADCAST, tx_accept_flags);
6215
6216                 if (bp->accept_any_vlan) {
6217                         __set_bit(BNX2X_ACCEPT_ANY_VLAN, rx_accept_flags);
6218                         __set_bit(BNX2X_ACCEPT_ANY_VLAN, tx_accept_flags);
6219                 }
6220
6221                 break;
6222         case BNX2X_RX_MODE_ALLMULTI:
6223                 __set_bit(BNX2X_ACCEPT_UNICAST, rx_accept_flags);
6224                 __set_bit(BNX2X_ACCEPT_ALL_MULTICAST, rx_accept_flags);
6225                 __set_bit(BNX2X_ACCEPT_BROADCAST, rx_accept_flags);
6226
6227                 /* internal switching mode */
6228                 __set_bit(BNX2X_ACCEPT_UNICAST, tx_accept_flags);
6229                 __set_bit(BNX2X_ACCEPT_ALL_MULTICAST, tx_accept_flags);
6230                 __set_bit(BNX2X_ACCEPT_BROADCAST, tx_accept_flags);
6231
6232                 if (bp->accept_any_vlan) {
6233                         __set_bit(BNX2X_ACCEPT_ANY_VLAN, rx_accept_flags);
6234                         __set_bit(BNX2X_ACCEPT_ANY_VLAN, tx_accept_flags);
6235                 }
6236
6237                 break;
6238         case BNX2X_RX_MODE_PROMISC:
6239                 /* According to definition of SI mode, iface in promisc mode
6240                  * should receive matched and unmatched (in resolution of port)
6241                  * unicast packets.
6242                  */
6243                 __set_bit(BNX2X_ACCEPT_UNMATCHED, rx_accept_flags);
6244                 __set_bit(BNX2X_ACCEPT_UNICAST, rx_accept_flags);
6245                 __set_bit(BNX2X_ACCEPT_ALL_MULTICAST, rx_accept_flags);
6246                 __set_bit(BNX2X_ACCEPT_BROADCAST, rx_accept_flags);
6247
6248                 /* internal switching mode */
6249                 __set_bit(BNX2X_ACCEPT_ALL_MULTICAST, tx_accept_flags);
6250                 __set_bit(BNX2X_ACCEPT_BROADCAST, tx_accept_flags);
6251
6252                 if (IS_MF_SI(bp))
6253                         __set_bit(BNX2X_ACCEPT_ALL_UNICAST, tx_accept_flags);
6254                 else
6255                         __set_bit(BNX2X_ACCEPT_UNICAST, tx_accept_flags);
6256
6257                 __set_bit(BNX2X_ACCEPT_ANY_VLAN, rx_accept_flags);
6258                 __set_bit(BNX2X_ACCEPT_ANY_VLAN, tx_accept_flags);
6259
6260                 break;
6261         default:
6262                 BNX2X_ERR("Unknown rx_mode: %d\n", rx_mode);
6263                 return -EINVAL;
6264         }
6265
6266         return 0;
6267 }
6268
6269 /* called with netif_addr_lock_bh() */
6270 static int bnx2x_set_storm_rx_mode(struct bnx2x *bp)
6271 {
6272         unsigned long rx_mode_flags = 0, ramrod_flags = 0;
6273         unsigned long rx_accept_flags = 0, tx_accept_flags = 0;
6274         int rc;
6275
6276         if (!NO_FCOE(bp))
6277                 /* Configure rx_mode of FCoE Queue */
6278                 __set_bit(BNX2X_RX_MODE_FCOE_ETH, &rx_mode_flags);
6279
6280         rc = bnx2x_fill_accept_flags(bp, bp->rx_mode, &rx_accept_flags,
6281                                      &tx_accept_flags);
6282         if (rc)
6283                 return rc;
6284
6285         __set_bit(RAMROD_RX, &ramrod_flags);
6286         __set_bit(RAMROD_TX, &ramrod_flags);
6287
6288         return bnx2x_set_q_rx_mode(bp, bp->fp->cl_id, rx_mode_flags,
6289                                    rx_accept_flags, tx_accept_flags,
6290                                    ramrod_flags);
6291 }
6292
6293 static void bnx2x_init_internal_common(struct bnx2x *bp)
6294 {
6295         int i;
6296
6297         /* Zero this manually as its initialization is
6298            currently missing in the initTool */
6299         for (i = 0; i < (USTORM_AGG_DATA_SIZE >> 2); i++)
6300                 REG_WR(bp, BAR_USTRORM_INTMEM +
6301                        USTORM_AGG_DATA_OFFSET + i * 4, 0);
6302         if (!CHIP_IS_E1x(bp)) {
6303                 REG_WR8(bp, BAR_CSTRORM_INTMEM + CSTORM_IGU_MODE_OFFSET,
6304                         CHIP_INT_MODE_IS_BC(bp) ?
6305                         HC_IGU_BC_MODE : HC_IGU_NBC_MODE);
6306         }
6307 }
6308
6309 static void bnx2x_init_internal(struct bnx2x *bp, u32 load_code)
6310 {
6311         switch (load_code) {
6312         case FW_MSG_CODE_DRV_LOAD_COMMON:
6313         case FW_MSG_CODE_DRV_LOAD_COMMON_CHIP:
6314                 bnx2x_init_internal_common(bp);
6315                 /* no break */
6316
6317         case FW_MSG_CODE_DRV_LOAD_PORT:
6318                 /* nothing to do */
6319                 /* no break */
6320
6321         case FW_MSG_CODE_DRV_LOAD_FUNCTION:
6322                 /* internal memory per function is
6323                    initialized inside bnx2x_pf_init */
6324                 break;
6325
6326         default:
6327                 BNX2X_ERR("Unknown load_code (0x%x) from MCP\n", load_code);
6328                 break;
6329         }
6330 }
6331
6332 static inline u8 bnx2x_fp_igu_sb_id(struct bnx2x_fastpath *fp)
6333 {
6334         return fp->bp->igu_base_sb + fp->index + CNIC_SUPPORT(fp->bp);
6335 }
6336
6337 static inline u8 bnx2x_fp_fw_sb_id(struct bnx2x_fastpath *fp)
6338 {
6339         return fp->bp->base_fw_ndsb + fp->index + CNIC_SUPPORT(fp->bp);
6340 }
6341
6342 static u8 bnx2x_fp_cl_id(struct bnx2x_fastpath *fp)
6343 {
6344         if (CHIP_IS_E1x(fp->bp))
6345                 return BP_L_ID(fp->bp) + fp->index;
6346         else    /* We want Client ID to be the same as IGU SB ID for 57712 */
6347                 return bnx2x_fp_igu_sb_id(fp);
6348 }
6349
6350 static void bnx2x_init_eth_fp(struct bnx2x *bp, int fp_idx)
6351 {
6352         struct bnx2x_fastpath *fp = &bp->fp[fp_idx];
6353         u8 cos;
6354         unsigned long q_type = 0;
6355         u32 cids[BNX2X_MULTI_TX_COS] = { 0 };
6356         fp->rx_queue = fp_idx;
6357         fp->cid = fp_idx;
6358         fp->cl_id = bnx2x_fp_cl_id(fp);
6359         fp->fw_sb_id = bnx2x_fp_fw_sb_id(fp);
6360         fp->igu_sb_id = bnx2x_fp_igu_sb_id(fp);
6361         /* qZone id equals to FW (per path) client id */
6362         fp->cl_qzone_id  = bnx2x_fp_qzone_id(fp);
6363
6364         /* init shortcut */
6365         fp->ustorm_rx_prods_offset = bnx2x_rx_ustorm_prods_offset(fp);
6366
6367         /* Setup SB indices */
6368         fp->rx_cons_sb = BNX2X_RX_SB_INDEX;
6369
6370         /* Configure Queue State object */
6371         __set_bit(BNX2X_Q_TYPE_HAS_RX, &q_type);
6372         __set_bit(BNX2X_Q_TYPE_HAS_TX, &q_type);
6373
6374         BUG_ON(fp->max_cos > BNX2X_MULTI_TX_COS);
6375
6376         /* init tx data */
6377         for_each_cos_in_tx_queue(fp, cos) {
6378                 bnx2x_init_txdata(bp, fp->txdata_ptr[cos],
6379                                   CID_COS_TO_TX_ONLY_CID(fp->cid, cos, bp),
6380                                   FP_COS_TO_TXQ(fp, cos, bp),
6381                                   BNX2X_TX_SB_INDEX_BASE + cos, fp);
6382                 cids[cos] = fp->txdata_ptr[cos]->cid;
6383         }
6384
6385         /* nothing more for vf to do here */
6386         if (IS_VF(bp))
6387                 return;
6388
6389         bnx2x_init_sb(bp, fp->status_blk_mapping, BNX2X_VF_ID_INVALID, false,
6390                       fp->fw_sb_id, fp->igu_sb_id);
6391         bnx2x_update_fpsb_idx(fp);
6392         bnx2x_init_queue_obj(bp, &bnx2x_sp_obj(bp, fp).q_obj, fp->cl_id, cids,
6393                              fp->max_cos, BP_FUNC(bp), bnx2x_sp(bp, q_rdata),
6394                              bnx2x_sp_mapping(bp, q_rdata), q_type);
6395
6396         /**
6397          * Configure classification DBs: Always enable Tx switching
6398          */
6399         bnx2x_init_vlan_mac_fp_objs(fp, BNX2X_OBJ_TYPE_RX_TX);
6400
6401         DP(NETIF_MSG_IFUP,
6402            "queue[%d]:  bnx2x_init_sb(%p,%p)  cl_id %d  fw_sb %d  igu_sb %d\n",
6403            fp_idx, bp, fp->status_blk.e2_sb, fp->cl_id, fp->fw_sb_id,
6404            fp->igu_sb_id);
6405 }
6406
6407 static void bnx2x_init_tx_ring_one(struct bnx2x_fp_txdata *txdata)
6408 {
6409         int i;
6410
6411         for (i = 1; i <= NUM_TX_RINGS; i++) {
6412                 struct eth_tx_next_bd *tx_next_bd =
6413                         &txdata->tx_desc_ring[TX_DESC_CNT * i - 1].next_bd;
6414
6415                 tx_next_bd->addr_hi =
6416                         cpu_to_le32(U64_HI(txdata->tx_desc_mapping +
6417                                     BCM_PAGE_SIZE*(i % NUM_TX_RINGS)));
6418                 tx_next_bd->addr_lo =
6419                         cpu_to_le32(U64_LO(txdata->tx_desc_mapping +
6420                                     BCM_PAGE_SIZE*(i % NUM_TX_RINGS)));
6421         }
6422
6423         *txdata->tx_cons_sb = cpu_to_le16(0);
6424
6425         SET_FLAG(txdata->tx_db.data.header.header, DOORBELL_HDR_DB_TYPE, 1);
6426         txdata->tx_db.data.zero_fill1 = 0;
6427         txdata->tx_db.data.prod = 0;
6428
6429         txdata->tx_pkt_prod = 0;
6430         txdata->tx_pkt_cons = 0;
6431         txdata->tx_bd_prod = 0;
6432         txdata->tx_bd_cons = 0;
6433         txdata->tx_pkt = 0;
6434 }
6435
6436 static void bnx2x_init_tx_rings_cnic(struct bnx2x *bp)
6437 {
6438         int i;
6439
6440         for_each_tx_queue_cnic(bp, i)
6441                 bnx2x_init_tx_ring_one(bp->fp[i].txdata_ptr[0]);
6442 }
6443
6444 static void bnx2x_init_tx_rings(struct bnx2x *bp)
6445 {
6446         int i;
6447         u8 cos;
6448
6449         for_each_eth_queue(bp, i)
6450                 for_each_cos_in_tx_queue(&bp->fp[i], cos)
6451                         bnx2x_init_tx_ring_one(bp->fp[i].txdata_ptr[cos]);
6452 }
6453
6454 static void bnx2x_init_fcoe_fp(struct bnx2x *bp)
6455 {
6456         struct bnx2x_fastpath *fp = bnx2x_fcoe_fp(bp);
6457         unsigned long q_type = 0;
6458
6459         bnx2x_fcoe(bp, rx_queue) = BNX2X_NUM_ETH_QUEUES(bp);
6460         bnx2x_fcoe(bp, cl_id) = bnx2x_cnic_eth_cl_id(bp,
6461                                                      BNX2X_FCOE_ETH_CL_ID_IDX);
6462         bnx2x_fcoe(bp, cid) = BNX2X_FCOE_ETH_CID(bp);
6463         bnx2x_fcoe(bp, fw_sb_id) = DEF_SB_ID;
6464         bnx2x_fcoe(bp, igu_sb_id) = bp->igu_dsb_id;
6465         bnx2x_fcoe(bp, rx_cons_sb) = BNX2X_FCOE_L2_RX_INDEX;
6466         bnx2x_init_txdata(bp, bnx2x_fcoe(bp, txdata_ptr[0]),
6467                           fp->cid, FCOE_TXQ_IDX(bp), BNX2X_FCOE_L2_TX_INDEX,
6468                           fp);
6469
6470         DP(NETIF_MSG_IFUP, "created fcoe tx data (fp index %d)\n", fp->index);
6471
6472         /* qZone id equals to FW (per path) client id */
6473         bnx2x_fcoe(bp, cl_qzone_id) = bnx2x_fp_qzone_id(fp);
6474         /* init shortcut */
6475         bnx2x_fcoe(bp, ustorm_rx_prods_offset) =
6476                 bnx2x_rx_ustorm_prods_offset(fp);
6477
6478         /* Configure Queue State object */
6479         __set_bit(BNX2X_Q_TYPE_HAS_RX, &q_type);
6480         __set_bit(BNX2X_Q_TYPE_HAS_TX, &q_type);
6481
6482         /* No multi-CoS for FCoE L2 client */
6483         BUG_ON(fp->max_cos != 1);
6484
6485         bnx2x_init_queue_obj(bp, &bnx2x_sp_obj(bp, fp).q_obj, fp->cl_id,
6486                              &fp->cid, 1, BP_FUNC(bp), bnx2x_sp(bp, q_rdata),
6487                              bnx2x_sp_mapping(bp, q_rdata), q_type);
6488
6489         DP(NETIF_MSG_IFUP,
6490            "queue[%d]: bnx2x_init_sb(%p,%p) cl_id %d fw_sb %d igu_sb %d\n",
6491            fp->index, bp, fp->status_blk.e2_sb, fp->cl_id, fp->fw_sb_id,
6492            fp->igu_sb_id);
6493 }
6494
6495 void bnx2x_nic_init_cnic(struct bnx2x *bp)
6496 {
6497         if (!NO_FCOE(bp))
6498                 bnx2x_init_fcoe_fp(bp);
6499
6500         bnx2x_init_sb(bp, bp->cnic_sb_mapping,
6501                       BNX2X_VF_ID_INVALID, false,
6502                       bnx2x_cnic_fw_sb_id(bp), bnx2x_cnic_igu_sb_id(bp));
6503
6504         /* ensure status block indices were read */
6505         rmb();
6506         bnx2x_init_rx_rings_cnic(bp);
6507         bnx2x_init_tx_rings_cnic(bp);
6508
6509         /* flush all */
6510         mb();
6511         mmiowb();
6512 }
6513
6514 void bnx2x_pre_irq_nic_init(struct bnx2x *bp)
6515 {
6516         int i;
6517
6518         /* Setup NIC internals and enable interrupts */
6519         for_each_eth_queue(bp, i)
6520                 bnx2x_init_eth_fp(bp, i);
6521
6522         /* ensure status block indices were read */
6523         rmb();
6524         bnx2x_init_rx_rings(bp);
6525         bnx2x_init_tx_rings(bp);
6526
6527         if (IS_PF(bp)) {
6528                 /* Initialize MOD_ABS interrupts */
6529                 bnx2x_init_mod_abs_int(bp, &bp->link_vars, bp->common.chip_id,
6530                                        bp->common.shmem_base,
6531                                        bp->common.shmem2_base, BP_PORT(bp));
6532
6533                 /* initialize the default status block and sp ring */
6534                 bnx2x_init_def_sb(bp);
6535                 bnx2x_update_dsb_idx(bp);
6536                 bnx2x_init_sp_ring(bp);
6537         } else {
6538                 bnx2x_memset_stats(bp);
6539         }
6540 }
6541
6542 void bnx2x_post_irq_nic_init(struct bnx2x *bp, u32 load_code)
6543 {
6544         bnx2x_init_eq_ring(bp);
6545         bnx2x_init_internal(bp, load_code);
6546         bnx2x_pf_init(bp);
6547         bnx2x_stats_init(bp);
6548
6549         /* flush all before enabling interrupts */
6550         mb();
6551         mmiowb();
6552
6553         bnx2x_int_enable(bp);
6554
6555         /* Check for SPIO5 */
6556         bnx2x_attn_int_deasserted0(bp,
6557                 REG_RD(bp, MISC_REG_AEU_AFTER_INVERT_1_FUNC_0 + BP_PORT(bp)*4) &
6558                                    AEU_INPUTS_ATTN_BITS_SPIO5);
6559 }
6560
6561 /* gzip service functions */
6562 static int bnx2x_gunzip_init(struct bnx2x *bp)
6563 {
6564         bp->gunzip_buf = dma_alloc_coherent(&bp->pdev->dev, FW_BUF_SIZE,
6565                                             &bp->gunzip_mapping, GFP_KERNEL);
6566         if (bp->gunzip_buf  == NULL)
6567                 goto gunzip_nomem1;
6568
6569         bp->strm = kmalloc(sizeof(*bp->strm), GFP_KERNEL);
6570         if (bp->strm  == NULL)
6571                 goto gunzip_nomem2;
6572
6573         bp->strm->workspace = vmalloc(zlib_inflate_workspacesize());
6574         if (bp->strm->workspace == NULL)
6575                 goto gunzip_nomem3;
6576
6577         return 0;
6578
6579 gunzip_nomem3:
6580         kfree(bp->strm);
6581         bp->strm = NULL;
6582
6583 gunzip_nomem2:
6584         dma_free_coherent(&bp->pdev->dev, FW_BUF_SIZE, bp->gunzip_buf,
6585                           bp->gunzip_mapping);
6586         bp->gunzip_buf = NULL;
6587
6588 gunzip_nomem1:
6589         BNX2X_ERR("Cannot allocate firmware buffer for un-compression\n");
6590         return -ENOMEM;
6591 }
6592
6593 static void bnx2x_gunzip_end(struct bnx2x *bp)
6594 {
6595         if (bp->strm) {
6596                 vfree(bp->strm->workspace);
6597                 kfree(bp->strm);
6598                 bp->strm = NULL;
6599         }
6600
6601         if (bp->gunzip_buf) {
6602                 dma_free_coherent(&bp->pdev->dev, FW_BUF_SIZE, bp->gunzip_buf,
6603                                   bp->gunzip_mapping);
6604                 bp->gunzip_buf = NULL;
6605         }
6606 }
6607
6608 static int bnx2x_gunzip(struct bnx2x *bp, const u8 *zbuf, int len)
6609 {
6610         int n, rc;
6611
6612         /* check gzip header */
6613         if ((zbuf[0] != 0x1f) || (zbuf[1] != 0x8b) || (zbuf[2] != Z_DEFLATED)) {
6614                 BNX2X_ERR("Bad gzip header\n");
6615                 return -EINVAL;
6616         }
6617
6618         n = 10;
6619
6620 #define FNAME                           0x8
6621
6622         if (zbuf[3] & FNAME)
6623                 while ((zbuf[n++] != 0) && (n < len));
6624
6625         bp->strm->next_in = (typeof(bp->strm->next_in))zbuf + n;
6626         bp->strm->avail_in = len - n;
6627         bp->strm->next_out = bp->gunzip_buf;
6628         bp->strm->avail_out = FW_BUF_SIZE;
6629
6630         rc = zlib_inflateInit2(bp->strm, -MAX_WBITS);
6631         if (rc != Z_OK)
6632                 return rc;
6633
6634         rc = zlib_inflate(bp->strm, Z_FINISH);
6635         if ((rc != Z_OK) && (rc != Z_STREAM_END))
6636                 netdev_err(bp->dev, "Firmware decompression error: %s\n",
6637                            bp->strm->msg);
6638
6639         bp->gunzip_outlen = (FW_BUF_SIZE - bp->strm->avail_out);
6640         if (bp->gunzip_outlen & 0x3)
6641                 netdev_err(bp->dev,
6642                            "Firmware decompression error: gunzip_outlen (%d) not aligned\n",
6643                                 bp->gunzip_outlen);
6644         bp->gunzip_outlen >>= 2;
6645
6646         zlib_inflateEnd(bp->strm);
6647
6648         if (rc == Z_STREAM_END)
6649                 return 0;
6650
6651         return rc;
6652 }
6653
6654 /* nic load/unload */
6655
6656 /*
6657  * General service functions
6658  */
6659
6660 /* send a NIG loopback debug packet */
6661 static void bnx2x_lb_pckt(struct bnx2x *bp)
6662 {
6663         u32 wb_write[3];
6664
6665         /* Ethernet source and destination addresses */
6666         wb_write[0] = 0x55555555;
6667         wb_write[1] = 0x55555555;
6668         wb_write[2] = 0x20;             /* SOP */
6669         REG_WR_DMAE(bp, NIG_REG_DEBUG_PACKET_LB, wb_write, 3);
6670
6671         /* NON-IP protocol */
6672         wb_write[0] = 0x09000000;
6673         wb_write[1] = 0x55555555;
6674         wb_write[2] = 0x10;             /* EOP, eop_bvalid = 0 */
6675         REG_WR_DMAE(bp, NIG_REG_DEBUG_PACKET_LB, wb_write, 3);
6676 }
6677
6678 /* some of the internal memories
6679  * are not directly readable from the driver
6680  * to test them we send debug packets
6681  */
6682 static int bnx2x_int_mem_test(struct bnx2x *bp)
6683 {
6684         int factor;
6685         int count, i;
6686         u32 val = 0;
6687
6688         if (CHIP_REV_IS_FPGA(bp))
6689                 factor = 120;
6690         else if (CHIP_REV_IS_EMUL(bp))
6691                 factor = 200;
6692         else
6693                 factor = 1;
6694
6695         /* Disable inputs of parser neighbor blocks */
6696         REG_WR(bp, TSDM_REG_ENABLE_IN1, 0x0);
6697         REG_WR(bp, TCM_REG_PRS_IFEN, 0x0);
6698         REG_WR(bp, CFC_REG_DEBUG0, 0x1);
6699         REG_WR(bp, NIG_REG_PRS_REQ_IN_EN, 0x0);
6700
6701         /*  Write 0 to parser credits for CFC search request */
6702         REG_WR(bp, PRS_REG_CFC_SEARCH_INITIAL_CREDIT, 0x0);
6703
6704         /* send Ethernet packet */
6705         bnx2x_lb_pckt(bp);
6706
6707         /* TODO do i reset NIG statistic? */
6708         /* Wait until NIG register shows 1 packet of size 0x10 */
6709         count = 1000 * factor;
6710         while (count) {
6711
6712                 bnx2x_read_dmae(bp, NIG_REG_STAT2_BRB_OCTET, 2);
6713                 val = *bnx2x_sp(bp, wb_data[0]);
6714                 if (val == 0x10)
6715                         break;
6716
6717                 usleep_range(10000, 20000);
6718                 count--;
6719         }
6720         if (val != 0x10) {
6721                 BNX2X_ERR("NIG timeout  val = 0x%x\n", val);
6722                 return -1;
6723         }
6724
6725         /* Wait until PRS register shows 1 packet */
6726         count = 1000 * factor;
6727         while (count) {
6728                 val = REG_RD(bp, PRS_REG_NUM_OF_PACKETS);
6729                 if (val == 1)
6730                         break;
6731
6732                 usleep_range(10000, 20000);
6733                 count--;
6734         }
6735         if (val != 0x1) {
6736                 BNX2X_ERR("PRS timeout val = 0x%x\n", val);
6737                 return -2;
6738         }
6739
6740         /* Reset and init BRB, PRS */
6741         REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_CLEAR, 0x03);
6742         msleep(50);
6743         REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_SET, 0x03);
6744         msleep(50);
6745         bnx2x_init_block(bp, BLOCK_BRB1, PHASE_COMMON);
6746         bnx2x_init_block(bp, BLOCK_PRS, PHASE_COMMON);
6747
6748         DP(NETIF_MSG_HW, "part2\n");
6749
6750         /* Disable inputs of parser neighbor blocks */
6751         REG_WR(bp, TSDM_REG_ENABLE_IN1, 0x0);
6752         REG_WR(bp, TCM_REG_PRS_IFEN, 0x0);
6753         REG_WR(bp, CFC_REG_DEBUG0, 0x1);
6754         REG_WR(bp, NIG_REG_PRS_REQ_IN_EN, 0x0);
6755
6756         /* Write 0 to parser credits for CFC search request */
6757         REG_WR(bp, PRS_REG_CFC_SEARCH_INITIAL_CREDIT, 0x0);
6758
6759         /* send 10 Ethernet packets */
6760         for (i = 0; i < 10; i++)
6761                 bnx2x_lb_pckt(bp);
6762
6763         /* Wait until NIG register shows 10 + 1
6764            packets of size 11*0x10 = 0xb0 */
6765         count = 1000 * factor;
6766         while (count) {
6767
6768                 bnx2x_read_dmae(bp, NIG_REG_STAT2_BRB_OCTET, 2);
6769                 val = *bnx2x_sp(bp, wb_data[0]);
6770                 if (val == 0xb0)
6771                         break;
6772
6773                 usleep_range(10000, 20000);
6774                 count--;
6775         }
6776         if (val != 0xb0) {
6777                 BNX2X_ERR("NIG timeout  val = 0x%x\n", val);
6778                 return -3;
6779         }
6780
6781         /* Wait until PRS register shows 2 packets */
6782         val = REG_RD(bp, PRS_REG_NUM_OF_PACKETS);
6783         if (val != 2)
6784                 BNX2X_ERR("PRS timeout  val = 0x%x\n", val);
6785
6786         /* Write 1 to parser credits for CFC search request */
6787         REG_WR(bp, PRS_REG_CFC_SEARCH_INITIAL_CREDIT, 0x1);
6788
6789         /* Wait until PRS register shows 3 packets */
6790         msleep(10 * factor);
6791         /* Wait until NIG register shows 1 packet of size 0x10 */
6792         val = REG_RD(bp, PRS_REG_NUM_OF_PACKETS);
6793         if (val != 3)
6794                 BNX2X_ERR("PRS timeout  val = 0x%x\n", val);
6795
6796         /* clear NIG EOP FIFO */
6797         for (i = 0; i < 11; i++)
6798                 REG_RD(bp, NIG_REG_INGRESS_EOP_LB_FIFO);
6799         val = REG_RD(bp, NIG_REG_INGRESS_EOP_LB_EMPTY);
6800         if (val != 1) {
6801                 BNX2X_ERR("clear of NIG failed\n");
6802                 return -4;
6803         }
6804
6805         /* Reset and init BRB, PRS, NIG */
6806         REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_CLEAR, 0x03);
6807         msleep(50);
6808         REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_SET, 0x03);
6809         msleep(50);
6810         bnx2x_init_block(bp, BLOCK_BRB1, PHASE_COMMON);
6811         bnx2x_init_block(bp, BLOCK_PRS, PHASE_COMMON);
6812         if (!CNIC_SUPPORT(bp))
6813                 /* set NIC mode */
6814                 REG_WR(bp, PRS_REG_NIC_MODE, 1);
6815
6816         /* Enable inputs of parser neighbor blocks */
6817         REG_WR(bp, TSDM_REG_ENABLE_IN1, 0x7fffffff);
6818         REG_WR(bp, TCM_REG_PRS_IFEN, 0x1);
6819         REG_WR(bp, CFC_REG_DEBUG0, 0x0);
6820         REG_WR(bp, NIG_REG_PRS_REQ_IN_EN, 0x1);
6821
6822         DP(NETIF_MSG_HW, "done\n");
6823
6824         return 0; /* OK */
6825 }
6826
6827 static void bnx2x_enable_blocks_attention(struct bnx2x *bp)
6828 {
6829         u32 val;
6830
6831         REG_WR(bp, PXP_REG_PXP_INT_MASK_0, 0);
6832         if (!CHIP_IS_E1x(bp))
6833                 REG_WR(bp, PXP_REG_PXP_INT_MASK_1, 0x40);
6834         else
6835                 REG_WR(bp, PXP_REG_PXP_INT_MASK_1, 0);
6836         REG_WR(bp, DORQ_REG_DORQ_INT_MASK, 0);
6837         REG_WR(bp, CFC_REG_CFC_INT_MASK, 0);
6838         /*
6839          * mask read length error interrupts in brb for parser
6840          * (parsing unit and 'checksum and crc' unit)
6841          * these errors are legal (PU reads fixed length and CAC can cause
6842          * read length error on truncated packets)
6843          */
6844         REG_WR(bp, BRB1_REG_BRB1_INT_MASK, 0xFC00);
6845         REG_WR(bp, QM_REG_QM_INT_MASK, 0);
6846         REG_WR(bp, TM_REG_TM_INT_MASK, 0);
6847         REG_WR(bp, XSDM_REG_XSDM_INT_MASK_0, 0);
6848         REG_WR(bp, XSDM_REG_XSDM_INT_MASK_1, 0);
6849         REG_WR(bp, XCM_REG_XCM_INT_MASK, 0);
6850 /*      REG_WR(bp, XSEM_REG_XSEM_INT_MASK_0, 0); */
6851 /*      REG_WR(bp, XSEM_REG_XSEM_INT_MASK_1, 0); */
6852         REG_WR(bp, USDM_REG_USDM_INT_MASK_0, 0);
6853         REG_WR(bp, USDM_REG_USDM_INT_MASK_1, 0);
6854         REG_WR(bp, UCM_REG_UCM_INT_MASK, 0);
6855 /*      REG_WR(bp, USEM_REG_USEM_INT_MASK_0, 0); */
6856 /*      REG_WR(bp, USEM_REG_USEM_INT_MASK_1, 0); */
6857         REG_WR(bp, GRCBASE_UPB + PB_REG_PB_INT_MASK, 0);
6858         REG_WR(bp, CSDM_REG_CSDM_INT_MASK_0, 0);
6859         REG_WR(bp, CSDM_REG_CSDM_INT_MASK_1, 0);
6860         REG_WR(bp, CCM_REG_CCM_INT_MASK, 0);
6861 /*      REG_WR(bp, CSEM_REG_CSEM_INT_MASK_0, 0); */
6862 /*      REG_WR(bp, CSEM_REG_CSEM_INT_MASK_1, 0); */
6863
6864         val = PXP2_PXP2_INT_MASK_0_REG_PGL_CPL_AFT  |
6865                 PXP2_PXP2_INT_MASK_0_REG_PGL_CPL_OF |
6866                 PXP2_PXP2_INT_MASK_0_REG_PGL_PCIE_ATTN;
6867         if (!CHIP_IS_E1x(bp))
6868                 val |= PXP2_PXP2_INT_MASK_0_REG_PGL_READ_BLOCKED |
6869                         PXP2_PXP2_INT_MASK_0_REG_PGL_WRITE_BLOCKED;
6870         REG_WR(bp, PXP2_REG_PXP2_INT_MASK_0, val);
6871
6872         REG_WR(bp, TSDM_REG_TSDM_INT_MASK_0, 0);
6873         REG_WR(bp, TSDM_REG_TSDM_INT_MASK_1, 0);
6874         REG_WR(bp, TCM_REG_TCM_INT_MASK, 0);
6875 /*      REG_WR(bp, TSEM_REG_TSEM_INT_MASK_0, 0); */
6876
6877         if (!CHIP_IS_E1x(bp))
6878                 /* enable VFC attentions: bits 11 and 12, bits 31:13 reserved */
6879                 REG_WR(bp, TSEM_REG_TSEM_INT_MASK_1, 0x07ff);
6880
6881         REG_WR(bp, CDU_REG_CDU_INT_MASK, 0);
6882         REG_WR(bp, DMAE_REG_DMAE_INT_MASK, 0);
6883 /*      REG_WR(bp, MISC_REG_MISC_INT_MASK, 0); */
6884         REG_WR(bp, PBF_REG_PBF_INT_MASK, 0x18);         /* bit 3,4 masked */
6885 }
6886
6887 static void bnx2x_reset_common(struct bnx2x *bp)
6888 {
6889         u32 val = 0x1400;
6890
6891         /* reset_common */
6892         REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_CLEAR,
6893                0xd3ffff7f);
6894
6895         if (CHIP_IS_E3(bp)) {
6896                 val |= MISC_REGISTERS_RESET_REG_2_MSTAT0;
6897                 val |= MISC_REGISTERS_RESET_REG_2_MSTAT1;
6898         }
6899
6900         REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR, val);
6901 }
6902
6903 static void bnx2x_setup_dmae(struct bnx2x *bp)
6904 {
6905         bp->dmae_ready = 0;
6906         spin_lock_init(&bp->dmae_lock);
6907 }
6908
6909 static void bnx2x_init_pxp(struct bnx2x *bp)
6910 {
6911         u16 devctl;
6912         int r_order, w_order;
6913
6914         pcie_capability_read_word(bp->pdev, PCI_EXP_DEVCTL, &devctl);
6915         DP(NETIF_MSG_HW, "read 0x%x from devctl\n", devctl);
6916         w_order = ((devctl & PCI_EXP_DEVCTL_PAYLOAD) >> 5);
6917         if (bp->mrrs == -1)
6918                 r_order = ((devctl & PCI_EXP_DEVCTL_READRQ) >> 12);
6919         else {
6920                 DP(NETIF_MSG_HW, "force read order to %d\n", bp->mrrs);
6921                 r_order = bp->mrrs;
6922         }
6923
6924         bnx2x_init_pxp_arb(bp, r_order, w_order);
6925 }
6926
6927 static void bnx2x_setup_fan_failure_detection(struct bnx2x *bp)
6928 {
6929         int is_required;
6930         u32 val;
6931         int port;
6932
6933         if (BP_NOMCP(bp))
6934                 return;
6935
6936         is_required = 0;
6937         val = SHMEM_RD(bp, dev_info.shared_hw_config.config2) &
6938               SHARED_HW_CFG_FAN_FAILURE_MASK;
6939
6940         if (val == SHARED_HW_CFG_FAN_FAILURE_ENABLED)
6941                 is_required = 1;
6942
6943         /*
6944          * The fan failure mechanism is usually related to the PHY type since
6945          * the power consumption of the board is affected by the PHY. Currently,
6946          * fan is required for most designs with SFX7101, BCM8727 and BCM8481.
6947          */
6948         else if (val == SHARED_HW_CFG_FAN_FAILURE_PHY_TYPE)
6949                 for (port = PORT_0; port < PORT_MAX; port++) {
6950                         is_required |=
6951                                 bnx2x_fan_failure_det_req(
6952                                         bp,
6953                                         bp->common.shmem_base,
6954                                         bp->common.shmem2_base,
6955                                         port);
6956                 }
6957
6958         DP(NETIF_MSG_HW, "fan detection setting: %d\n", is_required);
6959
6960         if (is_required == 0)
6961                 return;
6962
6963         /* Fan failure is indicated by SPIO 5 */
6964         bnx2x_set_spio(bp, MISC_SPIO_SPIO5, MISC_SPIO_INPUT_HI_Z);
6965
6966         /* set to active low mode */
6967         val = REG_RD(bp, MISC_REG_SPIO_INT);
6968         val |= (MISC_SPIO_SPIO5 << MISC_SPIO_INT_OLD_SET_POS);
6969         REG_WR(bp, MISC_REG_SPIO_INT, val);
6970
6971         /* enable interrupt to signal the IGU */
6972         val = REG_RD(bp, MISC_REG_SPIO_EVENT_EN);
6973         val |= MISC_SPIO_SPIO5;
6974         REG_WR(bp, MISC_REG_SPIO_EVENT_EN, val);
6975 }
6976
6977 void bnx2x_pf_disable(struct bnx2x *bp)
6978 {
6979         u32 val = REG_RD(bp, IGU_REG_PF_CONFIGURATION);
6980         val &= ~IGU_PF_CONF_FUNC_EN;
6981
6982         REG_WR(bp, IGU_REG_PF_CONFIGURATION, val);
6983         REG_WR(bp, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, 0);
6984         REG_WR(bp, CFC_REG_WEAK_ENABLE_PF, 0);
6985 }
6986
6987 static void bnx2x__common_init_phy(struct bnx2x *bp)
6988 {
6989         u32 shmem_base[2], shmem2_base[2];
6990         /* Avoid common init in case MFW supports LFA */
6991         if (SHMEM2_RD(bp, size) >
6992             (u32)offsetof(struct shmem2_region, lfa_host_addr[BP_PORT(bp)]))
6993                 return;
6994         shmem_base[0] =  bp->common.shmem_base;
6995         shmem2_base[0] = bp->common.shmem2_base;
6996         if (!CHIP_IS_E1x(bp)) {
6997                 shmem_base[1] =
6998                         SHMEM2_RD(bp, other_shmem_base_addr);
6999                 shmem2_base[1] =
7000                         SHMEM2_RD(bp, other_shmem2_base_addr);
7001         }
7002         bnx2x_acquire_phy_lock(bp);
7003         bnx2x_common_init_phy(bp, shmem_base, shmem2_base,
7004                               bp->common.chip_id);
7005         bnx2x_release_phy_lock(bp);
7006 }
7007
7008 static void bnx2x_config_endianity(struct bnx2x *bp, u32 val)
7009 {
7010         REG_WR(bp, PXP2_REG_RQ_QM_ENDIAN_M, val);
7011         REG_WR(bp, PXP2_REG_RQ_TM_ENDIAN_M, val);
7012         REG_WR(bp, PXP2_REG_RQ_SRC_ENDIAN_M, val);
7013         REG_WR(bp, PXP2_REG_RQ_CDU_ENDIAN_M, val);
7014         REG_WR(bp, PXP2_REG_RQ_DBG_ENDIAN_M, val);
7015
7016         /* make sure this value is 0 */
7017         REG_WR(bp, PXP2_REG_RQ_HC_ENDIAN_M, 0);
7018
7019         REG_WR(bp, PXP2_REG_RD_QM_SWAP_MODE, val);
7020         REG_WR(bp, PXP2_REG_RD_TM_SWAP_MODE, val);
7021         REG_WR(bp, PXP2_REG_RD_SRC_SWAP_MODE, val);
7022         REG_WR(bp, PXP2_REG_RD_CDURD_SWAP_MODE, val);
7023 }
7024
7025 static void bnx2x_set_endianity(struct bnx2x *bp)
7026 {
7027 #ifdef __BIG_ENDIAN
7028         bnx2x_config_endianity(bp, 1);
7029 #else
7030         bnx2x_config_endianity(bp, 0);
7031 #endif
7032 }
7033
7034 static void bnx2x_reset_endianity(struct bnx2x *bp)
7035 {
7036         bnx2x_config_endianity(bp, 0);
7037 }
7038
7039 /**
7040  * bnx2x_init_hw_common - initialize the HW at the COMMON phase.
7041  *
7042  * @bp:         driver handle
7043  */
7044 static int bnx2x_init_hw_common(struct bnx2x *bp)
7045 {
7046         u32 val;
7047
7048         DP(NETIF_MSG_HW, "starting common init  func %d\n", BP_ABS_FUNC(bp));
7049
7050         /*
7051          * take the RESET lock to protect undi_unload flow from accessing
7052          * registers while we're resetting the chip
7053          */
7054         bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_RESET);
7055
7056         bnx2x_reset_common(bp);
7057         REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_SET, 0xffffffff);
7058
7059         val = 0xfffc;
7060         if (CHIP_IS_E3(bp)) {
7061                 val |= MISC_REGISTERS_RESET_REG_2_MSTAT0;
7062                 val |= MISC_REGISTERS_RESET_REG_2_MSTAT1;
7063         }
7064         REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_SET, val);
7065
7066         bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_RESET);
7067
7068         bnx2x_init_block(bp, BLOCK_MISC, PHASE_COMMON);
7069
7070         if (!CHIP_IS_E1x(bp)) {
7071                 u8 abs_func_id;
7072
7073                 /**
7074                  * 4-port mode or 2-port mode we need to turn of master-enable
7075                  * for everyone, after that, turn it back on for self.
7076                  * so, we disregard multi-function or not, and always disable
7077                  * for all functions on the given path, this means 0,2,4,6 for
7078                  * path 0 and 1,3,5,7 for path 1
7079                  */
7080                 for (abs_func_id = BP_PATH(bp);
7081                      abs_func_id < E2_FUNC_MAX*2; abs_func_id += 2) {
7082                         if (abs_func_id == BP_ABS_FUNC(bp)) {
7083                                 REG_WR(bp,
7084                                     PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER,
7085                                     1);
7086                                 continue;
7087                         }
7088
7089                         bnx2x_pretend_func(bp, abs_func_id);
7090                         /* clear pf enable */
7091                         bnx2x_pf_disable(bp);
7092                         bnx2x_pretend_func(bp, BP_ABS_FUNC(bp));
7093                 }
7094         }
7095
7096         bnx2x_init_block(bp, BLOCK_PXP, PHASE_COMMON);
7097         if (CHIP_IS_E1(bp)) {
7098                 /* enable HW interrupt from PXP on USDM overflow
7099                    bit 16 on INT_MASK_0 */
7100                 REG_WR(bp, PXP_REG_PXP_INT_MASK_0, 0);
7101         }
7102
7103         bnx2x_init_block(bp, BLOCK_PXP2, PHASE_COMMON);
7104         bnx2x_init_pxp(bp);
7105         bnx2x_set_endianity(bp);
7106         bnx2x_ilt_init_page_size(bp, INITOP_SET);
7107
7108         if (CHIP_REV_IS_FPGA(bp) && CHIP_IS_E1H(bp))
7109                 REG_WR(bp, PXP2_REG_PGL_TAGS_LIMIT, 0x1);
7110
7111         /* let the HW do it's magic ... */
7112         msleep(100);
7113         /* finish PXP init */
7114         val = REG_RD(bp, PXP2_REG_RQ_CFG_DONE);
7115         if (val != 1) {
7116                 BNX2X_ERR("PXP2 CFG failed\n");
7117                 return -EBUSY;
7118         }
7119         val = REG_RD(bp, PXP2_REG_RD_INIT_DONE);
7120         if (val != 1) {
7121                 BNX2X_ERR("PXP2 RD_INIT failed\n");
7122                 return -EBUSY;
7123         }
7124
7125         /* Timers bug workaround E2 only. We need to set the entire ILT to
7126          * have entries with value "0" and valid bit on.
7127          * This needs to be done by the first PF that is loaded in a path
7128          * (i.e. common phase)
7129          */
7130         if (!CHIP_IS_E1x(bp)) {
7131 /* In E2 there is a bug in the timers block that can cause function 6 / 7
7132  * (i.e. vnic3) to start even if it is marked as "scan-off".
7133  * This occurs when a different function (func2,3) is being marked
7134  * as "scan-off". Real-life scenario for example: if a driver is being
7135  * load-unloaded while func6,7 are down. This will cause the timer to access
7136  * the ilt, translate to a logical address and send a request to read/write.
7137  * Since the ilt for the function that is down is not valid, this will cause
7138  * a translation error which is unrecoverable.
7139  * The Workaround is intended to make sure that when this happens nothing fatal
7140  * will occur. The workaround:
7141  *      1.  First PF driver which loads on a path will:
7142  *              a.  After taking the chip out of reset, by using pretend,
7143  *                  it will write "0" to the following registers of
7144  *                  the other vnics.
7145  *                  REG_WR(pdev, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, 0);
7146  *                  REG_WR(pdev, CFC_REG_WEAK_ENABLE_PF,0);
7147  *                  REG_WR(pdev, CFC_REG_STRONG_ENABLE_PF,0);
7148  *                  And for itself it will write '1' to
7149  *                  PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER to enable
7150  *                  dmae-operations (writing to pram for example.)
7151  *                  note: can be done for only function 6,7 but cleaner this
7152  *                        way.
7153  *              b.  Write zero+valid to the entire ILT.
7154  *              c.  Init the first_timers_ilt_entry, last_timers_ilt_entry of
7155  *                  VNIC3 (of that port). The range allocated will be the
7156  *                  entire ILT. This is needed to prevent  ILT range error.
7157  *      2.  Any PF driver load flow:
7158  *              a.  ILT update with the physical addresses of the allocated
7159  *                  logical pages.
7160  *              b.  Wait 20msec. - note that this timeout is needed to make
7161  *                  sure there are no requests in one of the PXP internal
7162  *                  queues with "old" ILT addresses.
7163  *              c.  PF enable in the PGLC.
7164  *              d.  Clear the was_error of the PF in the PGLC. (could have
7165  *                  occurred while driver was down)
7166  *              e.  PF enable in the CFC (WEAK + STRONG)
7167  *              f.  Timers scan enable
7168  *      3.  PF driver unload flow:
7169  *              a.  Clear the Timers scan_en.
7170  *              b.  Polling for scan_on=0 for that PF.
7171  *              c.  Clear the PF enable bit in the PXP.
7172  *              d.  Clear the PF enable in the CFC (WEAK + STRONG)
7173  *              e.  Write zero+valid to all ILT entries (The valid bit must
7174  *                  stay set)
7175  *              f.  If this is VNIC 3 of a port then also init
7176  *                  first_timers_ilt_entry to zero and last_timers_ilt_entry
7177  *                  to the last entry in the ILT.
7178  *
7179  *      Notes:
7180  *      Currently the PF error in the PGLC is non recoverable.
7181  *      In the future the there will be a recovery routine for this error.
7182  *      Currently attention is masked.
7183  *      Having an MCP lock on the load/unload process does not guarantee that
7184  *      there is no Timer disable during Func6/7 enable. This is because the
7185  *      Timers scan is currently being cleared by the MCP on FLR.
7186  *      Step 2.d can be done only for PF6/7 and the driver can also check if
7187  *      there is error before clearing it. But the flow above is simpler and
7188  *      more general.
7189  *      All ILT entries are written by zero+valid and not just PF6/7
7190  *      ILT entries since in the future the ILT entries allocation for
7191  *      PF-s might be dynamic.
7192  */
7193                 struct ilt_client_info ilt_cli;
7194                 struct bnx2x_ilt ilt;
7195                 memset(&ilt_cli, 0, sizeof(struct ilt_client_info));
7196                 memset(&ilt, 0, sizeof(struct bnx2x_ilt));
7197
7198                 /* initialize dummy TM client */
7199                 ilt_cli.start = 0;
7200                 ilt_cli.end = ILT_NUM_PAGE_ENTRIES - 1;
7201                 ilt_cli.client_num = ILT_CLIENT_TM;
7202
7203                 /* Step 1: set zeroes to all ilt page entries with valid bit on
7204                  * Step 2: set the timers first/last ilt entry to point
7205                  * to the entire range to prevent ILT range error for 3rd/4th
7206                  * vnic (this code assumes existence of the vnic)
7207                  *
7208                  * both steps performed by call to bnx2x_ilt_client_init_op()
7209                  * with dummy TM client
7210                  *
7211                  * we must use pretend since PXP2_REG_RQ_##blk##_FIRST_ILT
7212                  * and his brother are split registers
7213                  */
7214                 bnx2x_pretend_func(bp, (BP_PATH(bp) + 6));
7215                 bnx2x_ilt_client_init_op_ilt(bp, &ilt, &ilt_cli, INITOP_CLEAR);
7216                 bnx2x_pretend_func(bp, BP_ABS_FUNC(bp));
7217
7218                 REG_WR(bp, PXP2_REG_RQ_DRAM_ALIGN, BNX2X_PXP_DRAM_ALIGN);
7219                 REG_WR(bp, PXP2_REG_RQ_DRAM_ALIGN_RD, BNX2X_PXP_DRAM_ALIGN);
7220                 REG_WR(bp, PXP2_REG_RQ_DRAM_ALIGN_SEL, 1);
7221         }
7222
7223         REG_WR(bp, PXP2_REG_RQ_DISABLE_INPUTS, 0);
7224         REG_WR(bp, PXP2_REG_RD_DISABLE_INPUTS, 0);
7225
7226         if (!CHIP_IS_E1x(bp)) {
7227                 int factor = CHIP_REV_IS_EMUL(bp) ? 1000 :
7228                                 (CHIP_REV_IS_FPGA(bp) ? 400 : 0);
7229                 bnx2x_init_block(bp, BLOCK_PGLUE_B, PHASE_COMMON);
7230
7231                 bnx2x_init_block(bp, BLOCK_ATC, PHASE_COMMON);
7232
7233                 /* let the HW do it's magic ... */
7234                 do {
7235                         msleep(200);
7236                         val = REG_RD(bp, ATC_REG_ATC_INIT_DONE);
7237                 } while (factor-- && (val != 1));
7238
7239                 if (val != 1) {
7240                         BNX2X_ERR("ATC_INIT failed\n");
7241                         return -EBUSY;
7242                 }
7243         }
7244
7245         bnx2x_init_block(bp, BLOCK_DMAE, PHASE_COMMON);
7246
7247         bnx2x_iov_init_dmae(bp);
7248
7249         /* clean the DMAE memory */
7250         bp->dmae_ready = 1;
7251         bnx2x_init_fill(bp, TSEM_REG_PRAM, 0, 8, 1);
7252
7253         bnx2x_init_block(bp, BLOCK_TCM, PHASE_COMMON);
7254
7255         bnx2x_init_block(bp, BLOCK_UCM, PHASE_COMMON);
7256
7257         bnx2x_init_block(bp, BLOCK_CCM, PHASE_COMMON);
7258
7259         bnx2x_init_block(bp, BLOCK_XCM, PHASE_COMMON);
7260
7261         bnx2x_read_dmae(bp, XSEM_REG_PASSIVE_BUFFER, 3);
7262         bnx2x_read_dmae(bp, CSEM_REG_PASSIVE_BUFFER, 3);
7263         bnx2x_read_dmae(bp, TSEM_REG_PASSIVE_BUFFER, 3);
7264         bnx2x_read_dmae(bp, USEM_REG_PASSIVE_BUFFER, 3);
7265
7266         bnx2x_init_block(bp, BLOCK_QM, PHASE_COMMON);
7267
7268         /* QM queues pointers table */
7269         bnx2x_qm_init_ptr_table(bp, bp->qm_cid_count, INITOP_SET);
7270
7271         /* soft reset pulse */
7272         REG_WR(bp, QM_REG_SOFT_RESET, 1);
7273         REG_WR(bp, QM_REG_SOFT_RESET, 0);
7274
7275         if (CNIC_SUPPORT(bp))
7276                 bnx2x_init_block(bp, BLOCK_TM, PHASE_COMMON);
7277
7278         bnx2x_init_block(bp, BLOCK_DORQ, PHASE_COMMON);
7279
7280         if (!CHIP_REV_IS_SLOW(bp))
7281                 /* enable hw interrupt from doorbell Q */
7282                 REG_WR(bp, DORQ_REG_DORQ_INT_MASK, 0);
7283
7284         bnx2x_init_block(bp, BLOCK_BRB1, PHASE_COMMON);
7285
7286         bnx2x_init_block(bp, BLOCK_PRS, PHASE_COMMON);
7287         REG_WR(bp, PRS_REG_A_PRSU_20, 0xf);
7288
7289         if (!CHIP_IS_E1(bp))
7290                 REG_WR(bp, PRS_REG_E1HOV_MODE, bp->path_has_ovlan);
7291
7292         if (!CHIP_IS_E1x(bp) && !CHIP_IS_E3B0(bp)) {
7293                 if (IS_MF_AFEX(bp)) {
7294                         /* configure that VNTag and VLAN headers must be
7295                          * received in afex mode
7296                          */
7297                         REG_WR(bp, PRS_REG_HDRS_AFTER_BASIC, 0xE);
7298                         REG_WR(bp, PRS_REG_MUST_HAVE_HDRS, 0xA);
7299                         REG_WR(bp, PRS_REG_HDRS_AFTER_TAG_0, 0x6);
7300                         REG_WR(bp, PRS_REG_TAG_ETHERTYPE_0, 0x8926);
7301                         REG_WR(bp, PRS_REG_TAG_LEN_0, 0x4);
7302                 } else {
7303                         /* Bit-map indicating which L2 hdrs may appear
7304                          * after the basic Ethernet header
7305                          */
7306                         REG_WR(bp, PRS_REG_HDRS_AFTER_BASIC,
7307                                bp->path_has_ovlan ? 7 : 6);
7308                 }
7309         }
7310
7311         bnx2x_init_block(bp, BLOCK_TSDM, PHASE_COMMON);
7312         bnx2x_init_block(bp, BLOCK_CSDM, PHASE_COMMON);
7313         bnx2x_init_block(bp, BLOCK_USDM, PHASE_COMMON);
7314         bnx2x_init_block(bp, BLOCK_XSDM, PHASE_COMMON);
7315
7316         if (!CHIP_IS_E1x(bp)) {
7317                 /* reset VFC memories */
7318                 REG_WR(bp, TSEM_REG_FAST_MEMORY + VFC_REG_MEMORIES_RST,
7319                            VFC_MEMORIES_RST_REG_CAM_RST |
7320                            VFC_MEMORIES_RST_REG_RAM_RST);
7321                 REG_WR(bp, XSEM_REG_FAST_MEMORY + VFC_REG_MEMORIES_RST,
7322                            VFC_MEMORIES_RST_REG_CAM_RST |
7323                            VFC_MEMORIES_RST_REG_RAM_RST);
7324
7325                 msleep(20);
7326         }
7327
7328         bnx2x_init_block(bp, BLOCK_TSEM, PHASE_COMMON);
7329         bnx2x_init_block(bp, BLOCK_USEM, PHASE_COMMON);
7330         bnx2x_init_block(bp, BLOCK_CSEM, PHASE_COMMON);
7331         bnx2x_init_block(bp, BLOCK_XSEM, PHASE_COMMON);
7332
7333         /* sync semi rtc */
7334         REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_CLEAR,
7335                0x80000000);
7336         REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_SET,
7337                0x80000000);
7338
7339         bnx2x_init_block(bp, BLOCK_UPB, PHASE_COMMON);
7340         bnx2x_init_block(bp, BLOCK_XPB, PHASE_COMMON);
7341         bnx2x_init_block(bp, BLOCK_PBF, PHASE_COMMON);
7342
7343         if (!CHIP_IS_E1x(bp)) {
7344                 if (IS_MF_AFEX(bp)) {
7345                         /* configure that VNTag and VLAN headers must be
7346                          * sent in afex mode
7347                          */
7348                         REG_WR(bp, PBF_REG_HDRS_AFTER_BASIC, 0xE);
7349                         REG_WR(bp, PBF_REG_MUST_HAVE_HDRS, 0xA);
7350                         REG_WR(bp, PBF_REG_HDRS_AFTER_TAG_0, 0x6);
7351                         REG_WR(bp, PBF_REG_TAG_ETHERTYPE_0, 0x8926);
7352                         REG_WR(bp, PBF_REG_TAG_LEN_0, 0x4);
7353                 } else {
7354                         REG_WR(bp, PBF_REG_HDRS_AFTER_BASIC,
7355                                bp->path_has_ovlan ? 7 : 6);
7356                 }
7357         }
7358
7359         REG_WR(bp, SRC_REG_SOFT_RST, 1);
7360
7361         bnx2x_init_block(bp, BLOCK_SRC, PHASE_COMMON);
7362
7363         if (CNIC_SUPPORT(bp)) {
7364                 REG_WR(bp, SRC_REG_KEYSEARCH_0, 0x63285672);
7365                 REG_WR(bp, SRC_REG_KEYSEARCH_1, 0x24b8f2cc);
7366                 REG_WR(bp, SRC_REG_KEYSEARCH_2, 0x223aef9b);
7367                 REG_WR(bp, SRC_REG_KEYSEARCH_3, 0x26001e3a);
7368                 REG_WR(bp, SRC_REG_KEYSEARCH_4, 0x7ae91116);
7369                 REG_WR(bp, SRC_REG_KEYSEARCH_5, 0x5ce5230b);
7370                 REG_WR(bp, SRC_REG_KEYSEARCH_6, 0x298d8adf);
7371                 REG_WR(bp, SRC_REG_KEYSEARCH_7, 0x6eb0ff09);
7372                 REG_WR(bp, SRC_REG_KEYSEARCH_8, 0x1830f82f);
7373                 REG_WR(bp, SRC_REG_KEYSEARCH_9, 0x01e46be7);
7374         }
7375         REG_WR(bp, SRC_REG_SOFT_RST, 0);
7376
7377         if (sizeof(union cdu_context) != 1024)
7378                 /* we currently assume that a context is 1024 bytes */
7379                 dev_alert(&bp->pdev->dev,
7380                           "please adjust the size of cdu_context(%ld)\n",
7381                           (long)sizeof(union cdu_context));
7382
7383         bnx2x_init_block(bp, BLOCK_CDU, PHASE_COMMON);
7384         val = (4 << 24) + (0 << 12) + 1024;
7385         REG_WR(bp, CDU_REG_CDU_GLOBAL_PARAMS, val);
7386
7387         bnx2x_init_block(bp, BLOCK_CFC, PHASE_COMMON);
7388         REG_WR(bp, CFC_REG_INIT_REG, 0x7FF);
7389         /* enable context validation interrupt from CFC */
7390         REG_WR(bp, CFC_REG_CFC_INT_MASK, 0);
7391
7392         /* set the thresholds to prevent CFC/CDU race */
7393         REG_WR(bp, CFC_REG_DEBUG0, 0x20020000);
7394
7395         bnx2x_init_block(bp, BLOCK_HC, PHASE_COMMON);
7396
7397         if (!CHIP_IS_E1x(bp) && BP_NOMCP(bp))
7398                 REG_WR(bp, IGU_REG_RESET_MEMORIES, 0x36);
7399
7400         bnx2x_init_block(bp, BLOCK_IGU, PHASE_COMMON);
7401         bnx2x_init_block(bp, BLOCK_MISC_AEU, PHASE_COMMON);
7402
7403         /* Reset PCIE errors for debug */
7404         REG_WR(bp, 0x2814, 0xffffffff);
7405         REG_WR(bp, 0x3820, 0xffffffff);
7406
7407         if (!CHIP_IS_E1x(bp)) {
7408                 REG_WR(bp, PCICFG_OFFSET + PXPCS_TL_CONTROL_5,
7409                            (PXPCS_TL_CONTROL_5_ERR_UNSPPORT1 |
7410                                 PXPCS_TL_CONTROL_5_ERR_UNSPPORT));
7411                 REG_WR(bp, PCICFG_OFFSET + PXPCS_TL_FUNC345_STAT,
7412                            (PXPCS_TL_FUNC345_STAT_ERR_UNSPPORT4 |
7413                                 PXPCS_TL_FUNC345_STAT_ERR_UNSPPORT3 |
7414                                 PXPCS_TL_FUNC345_STAT_ERR_UNSPPORT2));
7415                 REG_WR(bp, PCICFG_OFFSET + PXPCS_TL_FUNC678_STAT,
7416                            (PXPCS_TL_FUNC678_STAT_ERR_UNSPPORT7 |
7417                                 PXPCS_TL_FUNC678_STAT_ERR_UNSPPORT6 |
7418                                 PXPCS_TL_FUNC678_STAT_ERR_UNSPPORT5));
7419         }
7420
7421         bnx2x_init_block(bp, BLOCK_NIG, PHASE_COMMON);
7422         if (!CHIP_IS_E1(bp)) {
7423                 /* in E3 this done in per-port section */
7424                 if (!CHIP_IS_E3(bp))
7425                         REG_WR(bp, NIG_REG_LLH_MF_MODE, IS_MF(bp));
7426         }
7427         if (CHIP_IS_E1H(bp))
7428                 /* not applicable for E2 (and above ...) */
7429                 REG_WR(bp, NIG_REG_LLH_E1HOV_MODE, IS_MF_SD(bp));
7430
7431         if (CHIP_REV_IS_SLOW(bp))
7432                 msleep(200);
7433
7434         /* finish CFC init */
7435         val = reg_poll(bp, CFC_REG_LL_INIT_DONE, 1, 100, 10);
7436         if (val != 1) {
7437                 BNX2X_ERR("CFC LL_INIT failed\n");
7438                 return -EBUSY;
7439         }
7440         val = reg_poll(bp, CFC_REG_AC_INIT_DONE, 1, 100, 10);
7441         if (val != 1) {
7442                 BNX2X_ERR("CFC AC_INIT failed\n");
7443                 return -EBUSY;
7444         }
7445         val = reg_poll(bp, CFC_REG_CAM_INIT_DONE, 1, 100, 10);
7446         if (val != 1) {
7447                 BNX2X_ERR("CFC CAM_INIT failed\n");
7448                 return -EBUSY;
7449         }
7450         REG_WR(bp, CFC_REG_DEBUG0, 0);
7451
7452         if (CHIP_IS_E1(bp)) {
7453                 /* read NIG statistic
7454                    to see if this is our first up since powerup */
7455                 bnx2x_read_dmae(bp, NIG_REG_STAT2_BRB_OCTET, 2);
7456                 val = *bnx2x_sp(bp, wb_data[0]);
7457
7458                 /* do internal memory self test */
7459                 if ((val == 0) && bnx2x_int_mem_test(bp)) {
7460                         BNX2X_ERR("internal mem self test failed\n");
7461                         return -EBUSY;
7462                 }
7463         }
7464
7465         bnx2x_setup_fan_failure_detection(bp);
7466
7467         /* clear PXP2 attentions */
7468         REG_RD(bp, PXP2_REG_PXP2_INT_STS_CLR_0);
7469
7470         bnx2x_enable_blocks_attention(bp);
7471         bnx2x_enable_blocks_parity(bp);
7472
7473         if (!BP_NOMCP(bp)) {
7474                 if (CHIP_IS_E1x(bp))
7475                         bnx2x__common_init_phy(bp);
7476         } else
7477                 BNX2X_ERR("Bootcode is missing - can not initialize link\n");
7478
7479         if (SHMEM2_HAS(bp, netproc_fw_ver))
7480                 SHMEM2_WR(bp, netproc_fw_ver, REG_RD(bp, XSEM_REG_PRAM));
7481
7482         return 0;
7483 }
7484
7485 /**
7486  * bnx2x_init_hw_common_chip - init HW at the COMMON_CHIP phase.
7487  *
7488  * @bp:         driver handle
7489  */
7490 static int bnx2x_init_hw_common_chip(struct bnx2x *bp)
7491 {
7492         int rc = bnx2x_init_hw_common(bp);
7493
7494         if (rc)
7495                 return rc;
7496
7497         /* In E2 2-PORT mode, same ext phy is used for the two paths */
7498         if (!BP_NOMCP(bp))
7499                 bnx2x__common_init_phy(bp);
7500
7501         return 0;
7502 }
7503
7504 static int bnx2x_init_hw_port(struct bnx2x *bp)
7505 {
7506         int port = BP_PORT(bp);
7507         int init_phase = port ? PHASE_PORT1 : PHASE_PORT0;
7508         u32 low, high;
7509         u32 val, reg;
7510
7511         DP(NETIF_MSG_HW, "starting port init  port %d\n", port);
7512
7513         REG_WR(bp, NIG_REG_MASK_INTERRUPT_PORT0 + port*4, 0);
7514
7515         bnx2x_init_block(bp, BLOCK_MISC, init_phase);
7516         bnx2x_init_block(bp, BLOCK_PXP, init_phase);
7517         bnx2x_init_block(bp, BLOCK_PXP2, init_phase);
7518
7519         /* Timers bug workaround: disables the pf_master bit in pglue at
7520          * common phase, we need to enable it here before any dmae access are
7521          * attempted. Therefore we manually added the enable-master to the
7522          * port phase (it also happens in the function phase)
7523          */
7524         if (!CHIP_IS_E1x(bp))
7525                 REG_WR(bp, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, 1);
7526
7527         bnx2x_init_block(bp, BLOCK_ATC, init_phase);
7528         bnx2x_init_block(bp, BLOCK_DMAE, init_phase);
7529         bnx2x_init_block(bp, BLOCK_PGLUE_B, init_phase);
7530         bnx2x_init_block(bp, BLOCK_QM, init_phase);
7531
7532         bnx2x_init_block(bp, BLOCK_TCM, init_phase);
7533         bnx2x_init_block(bp, BLOCK_UCM, init_phase);
7534         bnx2x_init_block(bp, BLOCK_CCM, init_phase);
7535         bnx2x_init_block(bp, BLOCK_XCM, init_phase);
7536
7537         /* QM cid (connection) count */
7538         bnx2x_qm_init_cid_count(bp, bp->qm_cid_count, INITOP_SET);
7539
7540         if (CNIC_SUPPORT(bp)) {
7541                 bnx2x_init_block(bp, BLOCK_TM, init_phase);
7542                 REG_WR(bp, TM_REG_LIN0_SCAN_TIME + port*4, 20);
7543                 REG_WR(bp, TM_REG_LIN0_MAX_ACTIVE_CID + port*4, 31);
7544         }
7545
7546         bnx2x_init_block(bp, BLOCK_DORQ, init_phase);
7547
7548         bnx2x_init_block(bp, BLOCK_BRB1, init_phase);
7549
7550         if (CHIP_IS_E1(bp) || CHIP_IS_E1H(bp)) {
7551
7552                 if (IS_MF(bp))
7553                         low = ((bp->flags & ONE_PORT_FLAG) ? 160 : 246);
7554                 else if (bp->dev->mtu > 4096) {
7555                         if (bp->flags & ONE_PORT_FLAG)
7556                                 low = 160;
7557                         else {
7558                                 val = bp->dev->mtu;
7559                                 /* (24*1024 + val*4)/256 */
7560                                 low = 96 + (val/64) +
7561                                                 ((val % 64) ? 1 : 0);
7562                         }
7563                 } else
7564                         low = ((bp->flags & ONE_PORT_FLAG) ? 80 : 160);
7565                 high = low + 56;        /* 14*1024/256 */
7566                 REG_WR(bp, BRB1_REG_PAUSE_LOW_THRESHOLD_0 + port*4, low);
7567                 REG_WR(bp, BRB1_REG_PAUSE_HIGH_THRESHOLD_0 + port*4, high);
7568         }
7569
7570         if (CHIP_MODE_IS_4_PORT(bp))
7571                 REG_WR(bp, (BP_PORT(bp) ?
7572                             BRB1_REG_MAC_GUARANTIED_1 :
7573                             BRB1_REG_MAC_GUARANTIED_0), 40);
7574
7575         bnx2x_init_block(bp, BLOCK_PRS, init_phase);
7576         if (CHIP_IS_E3B0(bp)) {
7577                 if (IS_MF_AFEX(bp)) {
7578                         /* configure headers for AFEX mode */
7579                         REG_WR(bp, BP_PORT(bp) ?
7580                                PRS_REG_HDRS_AFTER_BASIC_PORT_1 :
7581                                PRS_REG_HDRS_AFTER_BASIC_PORT_0, 0xE);
7582                         REG_WR(bp, BP_PORT(bp) ?
7583                                PRS_REG_HDRS_AFTER_TAG_0_PORT_1 :
7584                                PRS_REG_HDRS_AFTER_TAG_0_PORT_0, 0x6);
7585                         REG_WR(bp, BP_PORT(bp) ?
7586                                PRS_REG_MUST_HAVE_HDRS_PORT_1 :
7587                                PRS_REG_MUST_HAVE_HDRS_PORT_0, 0xA);
7588                 } else {
7589                         /* Ovlan exists only if we are in multi-function +
7590                          * switch-dependent mode, in switch-independent there
7591                          * is no ovlan headers
7592                          */
7593                         REG_WR(bp, BP_PORT(bp) ?
7594                                PRS_REG_HDRS_AFTER_BASIC_PORT_1 :
7595                                PRS_REG_HDRS_AFTER_BASIC_PORT_0,
7596                                (bp->path_has_ovlan ? 7 : 6));
7597                 }
7598         }
7599
7600         bnx2x_init_block(bp, BLOCK_TSDM, init_phase);
7601         bnx2x_init_block(bp, BLOCK_CSDM, init_phase);
7602         bnx2x_init_block(bp, BLOCK_USDM, init_phase);
7603         bnx2x_init_block(bp, BLOCK_XSDM, init_phase);
7604
7605         bnx2x_init_block(bp, BLOCK_TSEM, init_phase);
7606         bnx2x_init_block(bp, BLOCK_USEM, init_phase);
7607         bnx2x_init_block(bp, BLOCK_CSEM, init_phase);
7608         bnx2x_init_block(bp, BLOCK_XSEM, init_phase);
7609
7610         bnx2x_init_block(bp, BLOCK_UPB, init_phase);
7611         bnx2x_init_block(bp, BLOCK_XPB, init_phase);
7612
7613         bnx2x_init_block(bp, BLOCK_PBF, init_phase);
7614
7615         if (CHIP_IS_E1x(bp)) {
7616                 /* configure PBF to work without PAUSE mtu 9000 */
7617                 REG_WR(bp, PBF_REG_P0_PAUSE_ENABLE + port*4, 0);
7618
7619                 /* update threshold */
7620                 REG_WR(bp, PBF_REG_P0_ARB_THRSH + port*4, (9040/16));
7621                 /* update init credit */
7622                 REG_WR(bp, PBF_REG_P0_INIT_CRD + port*4, (9040/16) + 553 - 22);
7623
7624                 /* probe changes */
7625                 REG_WR(bp, PBF_REG_INIT_P0 + port*4, 1);
7626                 udelay(50);
7627                 REG_WR(bp, PBF_REG_INIT_P0 + port*4, 0);
7628         }
7629
7630         if (CNIC_SUPPORT(bp))
7631                 bnx2x_init_block(bp, BLOCK_SRC, init_phase);
7632
7633         bnx2x_init_block(bp, BLOCK_CDU, init_phase);
7634         bnx2x_init_block(bp, BLOCK_CFC, init_phase);
7635
7636         if (CHIP_IS_E1(bp)) {
7637                 REG_WR(bp, HC_REG_LEADING_EDGE_0 + port*8, 0);
7638                 REG_WR(bp, HC_REG_TRAILING_EDGE_0 + port*8, 0);
7639         }
7640         bnx2x_init_block(bp, BLOCK_HC, init_phase);
7641
7642         bnx2x_init_block(bp, BLOCK_IGU, init_phase);
7643
7644         bnx2x_init_block(bp, BLOCK_MISC_AEU, init_phase);
7645         /* init aeu_mask_attn_func_0/1:
7646          *  - SF mode: bits 3-7 are masked. Only bits 0-2 are in use
7647          *  - MF mode: bit 3 is masked. Bits 0-2 are in use as in SF
7648          *             bits 4-7 are used for "per vn group attention" */
7649         val = IS_MF(bp) ? 0xF7 : 0x7;
7650         /* Enable DCBX attention for all but E1 */
7651         val |= CHIP_IS_E1(bp) ? 0 : 0x10;
7652         REG_WR(bp, MISC_REG_AEU_MASK_ATTN_FUNC_0 + port*4, val);
7653
7654         /* SCPAD_PARITY should NOT trigger close the gates */
7655         reg = port ? MISC_REG_AEU_ENABLE4_NIG_1 : MISC_REG_AEU_ENABLE4_NIG_0;
7656         REG_WR(bp, reg,
7657                REG_RD(bp, reg) &
7658                ~AEU_INPUTS_ATTN_BITS_MCP_LATCHED_SCPAD_PARITY);
7659
7660         reg = port ? MISC_REG_AEU_ENABLE4_PXP_1 : MISC_REG_AEU_ENABLE4_PXP_0;
7661         REG_WR(bp, reg,
7662                REG_RD(bp, reg) &
7663                ~AEU_INPUTS_ATTN_BITS_MCP_LATCHED_SCPAD_PARITY);
7664
7665         bnx2x_init_block(bp, BLOCK_NIG, init_phase);
7666
7667         if (!CHIP_IS_E1x(bp)) {
7668                 /* Bit-map indicating which L2 hdrs may appear after the
7669                  * basic Ethernet header
7670                  */
7671                 if (IS_MF_AFEX(bp))
7672                         REG_WR(bp, BP_PORT(bp) ?
7673                                NIG_REG_P1_HDRS_AFTER_BASIC :
7674                                NIG_REG_P0_HDRS_AFTER_BASIC, 0xE);
7675                 else
7676                         REG_WR(bp, BP_PORT(bp) ?
7677                                NIG_REG_P1_HDRS_AFTER_BASIC :
7678                                NIG_REG_P0_HDRS_AFTER_BASIC,
7679                                IS_MF_SD(bp) ? 7 : 6);
7680
7681                 if (CHIP_IS_E3(bp))
7682                         REG_WR(bp, BP_PORT(bp) ?
7683                                    NIG_REG_LLH1_MF_MODE :
7684                                    NIG_REG_LLH_MF_MODE, IS_MF(bp));
7685         }
7686         if (!CHIP_IS_E3(bp))
7687                 REG_WR(bp, NIG_REG_XGXS_SERDES0_MODE_SEL + port*4, 1);
7688
7689         if (!CHIP_IS_E1(bp)) {
7690                 /* 0x2 disable mf_ov, 0x1 enable */
7691                 REG_WR(bp, NIG_REG_LLH0_BRB1_DRV_MASK_MF + port*4,
7692                        (IS_MF_SD(bp) ? 0x1 : 0x2));
7693
7694                 if (!CHIP_IS_E1x(bp)) {
7695                         val = 0;
7696                         switch (bp->mf_mode) {
7697                         case MULTI_FUNCTION_SD:
7698                                 val = 1;
7699                                 break;
7700                         case MULTI_FUNCTION_SI:
7701                         case MULTI_FUNCTION_AFEX:
7702                                 val = 2;
7703                                 break;
7704                         }
7705
7706                         REG_WR(bp, (BP_PORT(bp) ? NIG_REG_LLH1_CLS_TYPE :
7707                                                   NIG_REG_LLH0_CLS_TYPE), val);
7708                 }
7709                 {
7710                         REG_WR(bp, NIG_REG_LLFC_ENABLE_0 + port*4, 0);
7711                         REG_WR(bp, NIG_REG_LLFC_OUT_EN_0 + port*4, 0);
7712                         REG_WR(bp, NIG_REG_PAUSE_ENABLE_0 + port*4, 1);
7713                 }
7714         }
7715
7716         /* If SPIO5 is set to generate interrupts, enable it for this port */
7717         val = REG_RD(bp, MISC_REG_SPIO_EVENT_EN);
7718         if (val & MISC_SPIO_SPIO5) {
7719                 u32 reg_addr = (port ? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_0 :
7720                                        MISC_REG_AEU_ENABLE1_FUNC_0_OUT_0);
7721                 val = REG_RD(bp, reg_addr);
7722                 val |= AEU_INPUTS_ATTN_BITS_SPIO5;
7723                 REG_WR(bp, reg_addr, val);
7724         }
7725
7726         return 0;
7727 }
7728
7729 static void bnx2x_ilt_wr(struct bnx2x *bp, u32 index, dma_addr_t addr)
7730 {
7731         int reg;
7732         u32 wb_write[2];
7733
7734         if (CHIP_IS_E1(bp))
7735                 reg = PXP2_REG_RQ_ONCHIP_AT + index*8;
7736         else
7737                 reg = PXP2_REG_RQ_ONCHIP_AT_B0 + index*8;
7738
7739         wb_write[0] = ONCHIP_ADDR1(addr);
7740         wb_write[1] = ONCHIP_ADDR2(addr);
7741         REG_WR_DMAE(bp, reg, wb_write, 2);
7742 }
7743
7744 void bnx2x_igu_clear_sb_gen(struct bnx2x *bp, u8 func, u8 idu_sb_id, bool is_pf)
7745 {
7746         u32 data, ctl, cnt = 100;
7747         u32 igu_addr_data = IGU_REG_COMMAND_REG_32LSB_DATA;
7748         u32 igu_addr_ctl = IGU_REG_COMMAND_REG_CTRL;
7749         u32 igu_addr_ack = IGU_REG_CSTORM_TYPE_0_SB_CLEANUP + (idu_sb_id/32)*4;
7750         u32 sb_bit =  1 << (idu_sb_id%32);
7751         u32 func_encode = func | (is_pf ? 1 : 0) << IGU_FID_ENCODE_IS_PF_SHIFT;
7752         u32 addr_encode = IGU_CMD_E2_PROD_UPD_BASE + idu_sb_id;
7753
7754         /* Not supported in BC mode */
7755         if (CHIP_INT_MODE_IS_BC(bp))
7756                 return;
7757
7758         data = (IGU_USE_REGISTER_cstorm_type_0_sb_cleanup
7759                         << IGU_REGULAR_CLEANUP_TYPE_SHIFT)      |
7760                 IGU_REGULAR_CLEANUP_SET                         |
7761                 IGU_REGULAR_BCLEANUP;
7762
7763         ctl = addr_encode << IGU_CTRL_REG_ADDRESS_SHIFT         |
7764               func_encode << IGU_CTRL_REG_FID_SHIFT             |
7765               IGU_CTRL_CMD_TYPE_WR << IGU_CTRL_REG_TYPE_SHIFT;
7766
7767         DP(NETIF_MSG_HW, "write 0x%08x to IGU(via GRC) addr 0x%x\n",
7768                          data, igu_addr_data);
7769         REG_WR(bp, igu_addr_data, data);
7770         mmiowb();
7771         barrier();
7772         DP(NETIF_MSG_HW, "write 0x%08x to IGU(via GRC) addr 0x%x\n",
7773                           ctl, igu_addr_ctl);
7774         REG_WR(bp, igu_addr_ctl, ctl);
7775         mmiowb();
7776         barrier();
7777
7778         /* wait for clean up to finish */
7779         while (!(REG_RD(bp, igu_addr_ack) & sb_bit) && --cnt)
7780                 msleep(20);
7781
7782         if (!(REG_RD(bp, igu_addr_ack) & sb_bit)) {
7783                 DP(NETIF_MSG_HW,
7784                    "Unable to finish IGU cleanup: idu_sb_id %d offset %d bit %d (cnt %d)\n",
7785                           idu_sb_id, idu_sb_id/32, idu_sb_id%32, cnt);
7786         }
7787 }
7788
7789 static void bnx2x_igu_clear_sb(struct bnx2x *bp, u8 idu_sb_id)
7790 {
7791         bnx2x_igu_clear_sb_gen(bp, BP_FUNC(bp), idu_sb_id, true /*PF*/);
7792 }
7793
7794 static void bnx2x_clear_func_ilt(struct bnx2x *bp, u32 func)
7795 {
7796         u32 i, base = FUNC_ILT_BASE(func);
7797         for (i = base; i < base + ILT_PER_FUNC; i++)
7798                 bnx2x_ilt_wr(bp, i, 0);
7799 }
7800
7801 static void bnx2x_init_searcher(struct bnx2x *bp)
7802 {
7803         int port = BP_PORT(bp);
7804         bnx2x_src_init_t2(bp, bp->t2, bp->t2_mapping, SRC_CONN_NUM);
7805         /* T1 hash bits value determines the T1 number of entries */
7806         REG_WR(bp, SRC_REG_NUMBER_HASH_BITS0 + port*4, SRC_HASH_BITS);
7807 }
7808
7809 static inline int bnx2x_func_switch_update(struct bnx2x *bp, int suspend)
7810 {
7811         int rc;
7812         struct bnx2x_func_state_params func_params = {NULL};
7813         struct bnx2x_func_switch_update_params *switch_update_params =
7814                 &func_params.params.switch_update;
7815
7816         /* Prepare parameters for function state transitions */
7817         __set_bit(RAMROD_COMP_WAIT, &func_params.ramrod_flags);
7818         __set_bit(RAMROD_RETRY, &func_params.ramrod_flags);
7819
7820         func_params.f_obj = &bp->func_obj;
7821         func_params.cmd = BNX2X_F_CMD_SWITCH_UPDATE;
7822
7823         /* Function parameters */
7824         __set_bit(BNX2X_F_UPDATE_TX_SWITCH_SUSPEND_CHNG,
7825                   &switch_update_params->changes);
7826         if (suspend)
7827                 __set_bit(BNX2X_F_UPDATE_TX_SWITCH_SUSPEND,
7828                           &switch_update_params->changes);
7829
7830         rc = bnx2x_func_state_change(bp, &func_params);
7831
7832         return rc;
7833 }
7834
7835 static int bnx2x_reset_nic_mode(struct bnx2x *bp)
7836 {
7837         int rc, i, port = BP_PORT(bp);
7838         int vlan_en = 0, mac_en[NUM_MACS];
7839
7840         /* Close input from network */
7841         if (bp->mf_mode == SINGLE_FUNCTION) {
7842                 bnx2x_set_rx_filter(&bp->link_params, 0);
7843         } else {
7844                 vlan_en = REG_RD(bp, port ? NIG_REG_LLH1_FUNC_EN :
7845                                    NIG_REG_LLH0_FUNC_EN);
7846                 REG_WR(bp, port ? NIG_REG_LLH1_FUNC_EN :
7847                           NIG_REG_LLH0_FUNC_EN, 0);
7848                 for (i = 0; i < NUM_MACS; i++) {
7849                         mac_en[i] = REG_RD(bp, port ?
7850                                              (NIG_REG_LLH1_FUNC_MEM_ENABLE +
7851                                               4 * i) :
7852                                              (NIG_REG_LLH0_FUNC_MEM_ENABLE +
7853                                               4 * i));
7854                         REG_WR(bp, port ? (NIG_REG_LLH1_FUNC_MEM_ENABLE +
7855                                               4 * i) :
7856                                   (NIG_REG_LLH0_FUNC_MEM_ENABLE + 4 * i), 0);
7857                 }
7858         }
7859
7860         /* Close BMC to host */
7861         REG_WR(bp, port ? NIG_REG_P0_TX_MNG_HOST_ENABLE :
7862                NIG_REG_P1_TX_MNG_HOST_ENABLE, 0);
7863
7864         /* Suspend Tx switching to the PF. Completion of this ramrod
7865          * further guarantees that all the packets of that PF / child
7866          * VFs in BRB were processed by the Parser, so it is safe to
7867          * change the NIC_MODE register.
7868          */
7869         rc = bnx2x_func_switch_update(bp, 1);
7870         if (rc) {
7871                 BNX2X_ERR("Can't suspend tx-switching!\n");
7872                 return rc;
7873         }
7874
7875         /* Change NIC_MODE register */
7876         REG_WR(bp, PRS_REG_NIC_MODE, 0);
7877
7878         /* Open input from network */
7879         if (bp->mf_mode == SINGLE_FUNCTION) {
7880                 bnx2x_set_rx_filter(&bp->link_params, 1);
7881         } else {
7882                 REG_WR(bp, port ? NIG_REG_LLH1_FUNC_EN :
7883                           NIG_REG_LLH0_FUNC_EN, vlan_en);
7884                 for (i = 0; i < NUM_MACS; i++) {
7885                         REG_WR(bp, port ? (NIG_REG_LLH1_FUNC_MEM_ENABLE +
7886                                               4 * i) :
7887                                   (NIG_REG_LLH0_FUNC_MEM_ENABLE + 4 * i),
7888                                   mac_en[i]);
7889                 }
7890         }
7891
7892         /* Enable BMC to host */
7893         REG_WR(bp, port ? NIG_REG_P0_TX_MNG_HOST_ENABLE :
7894                NIG_REG_P1_TX_MNG_HOST_ENABLE, 1);
7895
7896         /* Resume Tx switching to the PF */
7897         rc = bnx2x_func_switch_update(bp, 0);
7898         if (rc) {
7899                 BNX2X_ERR("Can't resume tx-switching!\n");
7900                 return rc;
7901         }
7902
7903         DP(NETIF_MSG_IFUP, "NIC MODE disabled\n");
7904         return 0;
7905 }
7906
7907 int bnx2x_init_hw_func_cnic(struct bnx2x *bp)
7908 {
7909         int rc;
7910
7911         bnx2x_ilt_init_op_cnic(bp, INITOP_SET);
7912
7913         if (CONFIGURE_NIC_MODE(bp)) {
7914                 /* Configure searcher as part of function hw init */
7915                 bnx2x_init_searcher(bp);
7916
7917                 /* Reset NIC mode */
7918                 rc = bnx2x_reset_nic_mode(bp);
7919                 if (rc)
7920                         BNX2X_ERR("Can't change NIC mode!\n");
7921                 return rc;
7922         }
7923
7924         return 0;
7925 }
7926
7927 /* previous driver DMAE transaction may have occurred when pre-boot stage ended
7928  * and boot began, or when kdump kernel was loaded. Either case would invalidate
7929  * the addresses of the transaction, resulting in was-error bit set in the pci
7930  * causing all hw-to-host pcie transactions to timeout. If this happened we want
7931  * to clear the interrupt which detected this from the pglueb and the was done
7932  * bit
7933  */
7934 static void bnx2x_clean_pglue_errors(struct bnx2x *bp)
7935 {
7936         if (!CHIP_IS_E1x(bp))
7937                 REG_WR(bp, PGLUE_B_REG_WAS_ERROR_PF_7_0_CLR,
7938                        1 << BP_ABS_FUNC(bp));
7939 }
7940
7941 static int bnx2x_init_hw_func(struct bnx2x *bp)
7942 {
7943         int port = BP_PORT(bp);
7944         int func = BP_FUNC(bp);
7945         int init_phase = PHASE_PF0 + func;
7946         struct bnx2x_ilt *ilt = BP_ILT(bp);
7947         u16 cdu_ilt_start;
7948         u32 addr, val;
7949         u32 main_mem_base, main_mem_size, main_mem_prty_clr;
7950         int i, main_mem_width, rc;
7951
7952         DP(NETIF_MSG_HW, "starting func init  func %d\n", func);
7953
7954         /* FLR cleanup - hmmm */
7955         if (!CHIP_IS_E1x(bp)) {
7956                 rc = bnx2x_pf_flr_clnup(bp);
7957                 if (rc) {
7958                         bnx2x_fw_dump(bp);
7959                         return rc;
7960                 }
7961         }
7962
7963         /* set MSI reconfigure capability */
7964         if (bp->common.int_block == INT_BLOCK_HC) {
7965                 addr = (port ? HC_REG_CONFIG_1 : HC_REG_CONFIG_0);
7966                 val = REG_RD(bp, addr);
7967                 val |= HC_CONFIG_0_REG_MSI_ATTN_EN_0;
7968                 REG_WR(bp, addr, val);
7969         }
7970
7971         bnx2x_init_block(bp, BLOCK_PXP, init_phase);
7972         bnx2x_init_block(bp, BLOCK_PXP2, init_phase);
7973
7974         ilt = BP_ILT(bp);
7975         cdu_ilt_start = ilt->clients[ILT_CLIENT_CDU].start;
7976
7977         if (IS_SRIOV(bp))
7978                 cdu_ilt_start += BNX2X_FIRST_VF_CID/ILT_PAGE_CIDS;
7979         cdu_ilt_start = bnx2x_iov_init_ilt(bp, cdu_ilt_start);
7980
7981         /* since BNX2X_FIRST_VF_CID > 0 the PF L2 cids precedes
7982          * those of the VFs, so start line should be reset
7983          */
7984         cdu_ilt_start = ilt->clients[ILT_CLIENT_CDU].start;
7985         for (i = 0; i < L2_ILT_LINES(bp); i++) {
7986                 ilt->lines[cdu_ilt_start + i].page = bp->context[i].vcxt;
7987                 ilt->lines[cdu_ilt_start + i].page_mapping =
7988                         bp->context[i].cxt_mapping;
7989                 ilt->lines[cdu_ilt_start + i].size = bp->context[i].size;
7990         }
7991
7992         bnx2x_ilt_init_op(bp, INITOP_SET);
7993
7994         if (!CONFIGURE_NIC_MODE(bp)) {
7995                 bnx2x_init_searcher(bp);
7996                 REG_WR(bp, PRS_REG_NIC_MODE, 0);
7997                 DP(NETIF_MSG_IFUP, "NIC MODE disabled\n");
7998         } else {
7999                 /* Set NIC mode */
8000                 REG_WR(bp, PRS_REG_NIC_MODE, 1);
8001                 DP(NETIF_MSG_IFUP, "NIC MODE configured\n");
8002         }
8003
8004         if (!CHIP_IS_E1x(bp)) {
8005                 u32 pf_conf = IGU_PF_CONF_FUNC_EN;
8006
8007                 /* Turn on a single ISR mode in IGU if driver is going to use
8008                  * INT#x or MSI
8009                  */
8010                 if (!(bp->flags & USING_MSIX_FLAG))
8011                         pf_conf |= IGU_PF_CONF_SINGLE_ISR_EN;
8012                 /*
8013                  * Timers workaround bug: function init part.
8014                  * Need to wait 20msec after initializing ILT,
8015                  * needed to make sure there are no requests in
8016                  * one of the PXP internal queues with "old" ILT addresses
8017                  */
8018                 msleep(20);
8019                 /*
8020                  * Master enable - Due to WB DMAE writes performed before this
8021                  * register is re-initialized as part of the regular function
8022                  * init
8023                  */
8024                 REG_WR(bp, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, 1);
8025                 /* Enable the function in IGU */
8026                 REG_WR(bp, IGU_REG_PF_CONFIGURATION, pf_conf);
8027         }
8028
8029         bp->dmae_ready = 1;
8030
8031         bnx2x_init_block(bp, BLOCK_PGLUE_B, init_phase);
8032
8033         bnx2x_clean_pglue_errors(bp);
8034
8035         bnx2x_init_block(bp, BLOCK_ATC, init_phase);
8036         bnx2x_init_block(bp, BLOCK_DMAE, init_phase);
8037         bnx2x_init_block(bp, BLOCK_NIG, init_phase);
8038         bnx2x_init_block(bp, BLOCK_SRC, init_phase);
8039         bnx2x_init_block(bp, BLOCK_MISC, init_phase);
8040         bnx2x_init_block(bp, BLOCK_TCM, init_phase);
8041         bnx2x_init_block(bp, BLOCK_UCM, init_phase);
8042         bnx2x_init_block(bp, BLOCK_CCM, init_phase);
8043         bnx2x_init_block(bp, BLOCK_XCM, init_phase);
8044         bnx2x_init_block(bp, BLOCK_TSEM, init_phase);
8045         bnx2x_init_block(bp, BLOCK_USEM, init_phase);
8046         bnx2x_init_block(bp, BLOCK_CSEM, init_phase);
8047         bnx2x_init_block(bp, BLOCK_XSEM, init_phase);
8048
8049         if (!CHIP_IS_E1x(bp))
8050                 REG_WR(bp, QM_REG_PF_EN, 1);
8051
8052         if (!CHIP_IS_E1x(bp)) {
8053                 REG_WR(bp, TSEM_REG_VFPF_ERR_NUM, BNX2X_MAX_NUM_OF_VFS + func);
8054                 REG_WR(bp, USEM_REG_VFPF_ERR_NUM, BNX2X_MAX_NUM_OF_VFS + func);
8055                 REG_WR(bp, CSEM_REG_VFPF_ERR_NUM, BNX2X_MAX_NUM_OF_VFS + func);
8056                 REG_WR(bp, XSEM_REG_VFPF_ERR_NUM, BNX2X_MAX_NUM_OF_VFS + func);
8057         }
8058         bnx2x_init_block(bp, BLOCK_QM, init_phase);
8059
8060         bnx2x_init_block(bp, BLOCK_TM, init_phase);
8061         bnx2x_init_block(bp, BLOCK_DORQ, init_phase);
8062         REG_WR(bp, DORQ_REG_MODE_ACT, 1); /* no dpm */
8063
8064         bnx2x_iov_init_dq(bp);
8065
8066         bnx2x_init_block(bp, BLOCK_BRB1, init_phase);
8067         bnx2x_init_block(bp, BLOCK_PRS, init_phase);
8068         bnx2x_init_block(bp, BLOCK_TSDM, init_phase);
8069         bnx2x_init_block(bp, BLOCK_CSDM, init_phase);
8070         bnx2x_init_block(bp, BLOCK_USDM, init_phase);
8071         bnx2x_init_block(bp, BLOCK_XSDM, init_phase);
8072         bnx2x_init_block(bp, BLOCK_UPB, init_phase);
8073         bnx2x_init_block(bp, BLOCK_XPB, init_phase);
8074         bnx2x_init_block(bp, BLOCK_PBF, init_phase);
8075         if (!CHIP_IS_E1x(bp))
8076                 REG_WR(bp, PBF_REG_DISABLE_PF, 0);
8077
8078         bnx2x_init_block(bp, BLOCK_CDU, init_phase);
8079
8080         bnx2x_init_block(bp, BLOCK_CFC, init_phase);
8081
8082         if (!CHIP_IS_E1x(bp))
8083                 REG_WR(bp, CFC_REG_WEAK_ENABLE_PF, 1);
8084
8085         if (IS_MF(bp)) {
8086                 if (!(IS_MF_UFP(bp) && BNX2X_IS_MF_SD_PROTOCOL_FCOE(bp))) {
8087                         REG_WR(bp, NIG_REG_LLH0_FUNC_EN + port * 8, 1);
8088                         REG_WR(bp, NIG_REG_LLH0_FUNC_VLAN_ID + port * 8,
8089                                bp->mf_ov);
8090                 }
8091         }
8092
8093         bnx2x_init_block(bp, BLOCK_MISC_AEU, init_phase);
8094
8095         /* HC init per function */
8096         if (bp->common.int_block == INT_BLOCK_HC) {
8097                 if (CHIP_IS_E1H(bp)) {
8098                         REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_12 + func*4, 0);
8099
8100                         REG_WR(bp, HC_REG_LEADING_EDGE_0 + port*8, 0);
8101                         REG_WR(bp, HC_REG_TRAILING_EDGE_0 + port*8, 0);
8102                 }
8103                 bnx2x_init_block(bp, BLOCK_HC, init_phase);
8104
8105         } else {
8106                 int num_segs, sb_idx, prod_offset;
8107
8108                 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_12 + func*4, 0);
8109
8110                 if (!CHIP_IS_E1x(bp)) {
8111                         REG_WR(bp, IGU_REG_LEADING_EDGE_LATCH, 0);
8112                         REG_WR(bp, IGU_REG_TRAILING_EDGE_LATCH, 0);
8113                 }
8114
8115                 bnx2x_init_block(bp, BLOCK_IGU, init_phase);
8116
8117                 if (!CHIP_IS_E1x(bp)) {
8118                         int dsb_idx = 0;
8119                         /**
8120                          * Producer memory:
8121                          * E2 mode: address 0-135 match to the mapping memory;
8122                          * 136 - PF0 default prod; 137 - PF1 default prod;
8123                          * 138 - PF2 default prod; 139 - PF3 default prod;
8124                          * 140 - PF0 attn prod;    141 - PF1 attn prod;
8125                          * 142 - PF2 attn prod;    143 - PF3 attn prod;
8126                          * 144-147 reserved.
8127                          *
8128                          * E1.5 mode - In backward compatible mode;
8129                          * for non default SB; each even line in the memory
8130                          * holds the U producer and each odd line hold
8131                          * the C producer. The first 128 producers are for
8132                          * NDSB (PF0 - 0-31; PF1 - 32-63 and so on). The last 20
8133                          * producers are for the DSB for each PF.
8134                          * Each PF has five segments: (the order inside each
8135                          * segment is PF0; PF1; PF2; PF3) - 128-131 U prods;
8136                          * 132-135 C prods; 136-139 X prods; 140-143 T prods;
8137                          * 144-147 attn prods;
8138                          */
8139                         /* non-default-status-blocks */
8140                         num_segs = CHIP_INT_MODE_IS_BC(bp) ?
8141                                 IGU_BC_NDSB_NUM_SEGS : IGU_NORM_NDSB_NUM_SEGS;
8142                         for (sb_idx = 0; sb_idx < bp->igu_sb_cnt; sb_idx++) {
8143                                 prod_offset = (bp->igu_base_sb + sb_idx) *
8144                                         num_segs;
8145
8146                                 for (i = 0; i < num_segs; i++) {
8147                                         addr = IGU_REG_PROD_CONS_MEMORY +
8148                                                         (prod_offset + i) * 4;
8149                                         REG_WR(bp, addr, 0);
8150                                 }
8151                                 /* send consumer update with value 0 */
8152                                 bnx2x_ack_sb(bp, bp->igu_base_sb + sb_idx,
8153                                              USTORM_ID, 0, IGU_INT_NOP, 1);
8154                                 bnx2x_igu_clear_sb(bp,
8155                                                    bp->igu_base_sb + sb_idx);
8156                         }
8157
8158                         /* default-status-blocks */
8159                         num_segs = CHIP_INT_MODE_IS_BC(bp) ?
8160                                 IGU_BC_DSB_NUM_SEGS : IGU_NORM_DSB_NUM_SEGS;
8161
8162                         if (CHIP_MODE_IS_4_PORT(bp))
8163                                 dsb_idx = BP_FUNC(bp);
8164                         else
8165                                 dsb_idx = BP_VN(bp);
8166
8167                         prod_offset = (CHIP_INT_MODE_IS_BC(bp) ?
8168                                        IGU_BC_BASE_DSB_PROD + dsb_idx :
8169                                        IGU_NORM_BASE_DSB_PROD + dsb_idx);
8170
8171                         /*
8172                          * igu prods come in chunks of E1HVN_MAX (4) -
8173                          * does not matters what is the current chip mode
8174                          */
8175                         for (i = 0; i < (num_segs * E1HVN_MAX);
8176                              i += E1HVN_MAX) {
8177                                 addr = IGU_REG_PROD_CONS_MEMORY +
8178                                                         (prod_offset + i)*4;
8179                                 REG_WR(bp, addr, 0);
8180                         }
8181                         /* send consumer update with 0 */
8182                         if (CHIP_INT_MODE_IS_BC(bp)) {
8183                                 bnx2x_ack_sb(bp, bp->igu_dsb_id,
8184                                              USTORM_ID, 0, IGU_INT_NOP, 1);
8185                                 bnx2x_ack_sb(bp, bp->igu_dsb_id,
8186                                              CSTORM_ID, 0, IGU_INT_NOP, 1);
8187                                 bnx2x_ack_sb(bp, bp->igu_dsb_id,
8188                                              XSTORM_ID, 0, IGU_INT_NOP, 1);
8189                                 bnx2x_ack_sb(bp, bp->igu_dsb_id,
8190                                              TSTORM_ID, 0, IGU_INT_NOP, 1);
8191                                 bnx2x_ack_sb(bp, bp->igu_dsb_id,
8192                                              ATTENTION_ID, 0, IGU_INT_NOP, 1);
8193                         } else {
8194                                 bnx2x_ack_sb(bp, bp->igu_dsb_id,
8195                                              USTORM_ID, 0, IGU_INT_NOP, 1);
8196                                 bnx2x_ack_sb(bp, bp->igu_dsb_id,
8197                                              ATTENTION_ID, 0, IGU_INT_NOP, 1);
8198                         }
8199                         bnx2x_igu_clear_sb(bp, bp->igu_dsb_id);
8200
8201                         /* !!! These should become driver const once
8202                            rf-tool supports split-68 const */
8203                         REG_WR(bp, IGU_REG_SB_INT_BEFORE_MASK_LSB, 0);
8204                         REG_WR(bp, IGU_REG_SB_INT_BEFORE_MASK_MSB, 0);
8205                         REG_WR(bp, IGU_REG_SB_MASK_LSB, 0);
8206                         REG_WR(bp, IGU_REG_SB_MASK_MSB, 0);
8207                         REG_WR(bp, IGU_REG_PBA_STATUS_LSB, 0);
8208                         REG_WR(bp, IGU_REG_PBA_STATUS_MSB, 0);
8209                 }
8210         }
8211
8212         /* Reset PCIE errors for debug */
8213         REG_WR(bp, 0x2114, 0xffffffff);
8214         REG_WR(bp, 0x2120, 0xffffffff);
8215
8216         if (CHIP_IS_E1x(bp)) {
8217                 main_mem_size = HC_REG_MAIN_MEMORY_SIZE / 2; /*dwords*/
8218                 main_mem_base = HC_REG_MAIN_MEMORY +
8219                                 BP_PORT(bp) * (main_mem_size * 4);
8220                 main_mem_prty_clr = HC_REG_HC_PRTY_STS_CLR;
8221                 main_mem_width = 8;
8222
8223                 val = REG_RD(bp, main_mem_prty_clr);
8224                 if (val)
8225                         DP(NETIF_MSG_HW,
8226                            "Hmmm... Parity errors in HC block during function init (0x%x)!\n",
8227                            val);
8228
8229                 /* Clear "false" parity errors in MSI-X table */
8230                 for (i = main_mem_base;
8231                      i < main_mem_base + main_mem_size * 4;
8232                      i += main_mem_width) {
8233                         bnx2x_read_dmae(bp, i, main_mem_width / 4);
8234                         bnx2x_write_dmae(bp, bnx2x_sp_mapping(bp, wb_data),
8235                                          i, main_mem_width / 4);
8236                 }
8237                 /* Clear HC parity attention */
8238                 REG_RD(bp, main_mem_prty_clr);
8239         }
8240
8241 #ifdef BNX2X_STOP_ON_ERROR
8242         /* Enable STORMs SP logging */
8243         REG_WR8(bp, BAR_USTRORM_INTMEM +
8244                USTORM_RECORD_SLOW_PATH_OFFSET(BP_FUNC(bp)), 1);
8245         REG_WR8(bp, BAR_TSTRORM_INTMEM +
8246                TSTORM_RECORD_SLOW_PATH_OFFSET(BP_FUNC(bp)), 1);
8247         REG_WR8(bp, BAR_CSTRORM_INTMEM +
8248                CSTORM_RECORD_SLOW_PATH_OFFSET(BP_FUNC(bp)), 1);
8249         REG_WR8(bp, BAR_XSTRORM_INTMEM +
8250                XSTORM_RECORD_SLOW_PATH_OFFSET(BP_FUNC(bp)), 1);
8251 #endif
8252
8253         bnx2x_phy_probe(&bp->link_params);
8254
8255         return 0;
8256 }
8257
8258 void bnx2x_free_mem_cnic(struct bnx2x *bp)
8259 {
8260         bnx2x_ilt_mem_op_cnic(bp, ILT_MEMOP_FREE);
8261
8262         if (!CHIP_IS_E1x(bp))
8263                 BNX2X_PCI_FREE(bp->cnic_sb.e2_sb, bp->cnic_sb_mapping,
8264                                sizeof(struct host_hc_status_block_e2));
8265         else
8266                 BNX2X_PCI_FREE(bp->cnic_sb.e1x_sb, bp->cnic_sb_mapping,
8267                                sizeof(struct host_hc_status_block_e1x));
8268
8269         BNX2X_PCI_FREE(bp->t2, bp->t2_mapping, SRC_T2_SZ);
8270 }
8271
8272 void bnx2x_free_mem(struct bnx2x *bp)
8273 {
8274         int i;
8275
8276         BNX2X_PCI_FREE(bp->fw_stats, bp->fw_stats_mapping,
8277                        bp->fw_stats_data_sz + bp->fw_stats_req_sz);
8278
8279         if (IS_VF(bp))
8280                 return;
8281
8282         BNX2X_PCI_FREE(bp->def_status_blk, bp->def_status_blk_mapping,
8283                        sizeof(struct host_sp_status_block));
8284
8285         BNX2X_PCI_FREE(bp->slowpath, bp->slowpath_mapping,
8286                        sizeof(struct bnx2x_slowpath));
8287
8288         for (i = 0; i < L2_ILT_LINES(bp); i++)
8289                 BNX2X_PCI_FREE(bp->context[i].vcxt, bp->context[i].cxt_mapping,
8290                                bp->context[i].size);
8291         bnx2x_ilt_mem_op(bp, ILT_MEMOP_FREE);
8292
8293         BNX2X_FREE(bp->ilt->lines);
8294
8295         BNX2X_PCI_FREE(bp->spq, bp->spq_mapping, BCM_PAGE_SIZE);
8296
8297         BNX2X_PCI_FREE(bp->eq_ring, bp->eq_mapping,
8298                        BCM_PAGE_SIZE * NUM_EQ_PAGES);
8299
8300         BNX2X_PCI_FREE(bp->t2, bp->t2_mapping, SRC_T2_SZ);
8301
8302         bnx2x_iov_free_mem(bp);
8303 }
8304
8305 int bnx2x_alloc_mem_cnic(struct bnx2x *bp)
8306 {
8307         if (!CHIP_IS_E1x(bp)) {
8308                 /* size = the status block + ramrod buffers */
8309                 bp->cnic_sb.e2_sb = BNX2X_PCI_ALLOC(&bp->cnic_sb_mapping,
8310                                                     sizeof(struct host_hc_status_block_e2));
8311                 if (!bp->cnic_sb.e2_sb)
8312                         goto alloc_mem_err;
8313         } else {
8314                 bp->cnic_sb.e1x_sb = BNX2X_PCI_ALLOC(&bp->cnic_sb_mapping,
8315                                                      sizeof(struct host_hc_status_block_e1x));
8316                 if (!bp->cnic_sb.e1x_sb)
8317                         goto alloc_mem_err;
8318         }
8319
8320         if (CONFIGURE_NIC_MODE(bp) && !bp->t2) {
8321                 /* allocate searcher T2 table, as it wasn't allocated before */
8322                 bp->t2 = BNX2X_PCI_ALLOC(&bp->t2_mapping, SRC_T2_SZ);
8323                 if (!bp->t2)
8324                         goto alloc_mem_err;
8325         }
8326
8327         /* write address to which L5 should insert its values */
8328         bp->cnic_eth_dev.addr_drv_info_to_mcp =
8329                 &bp->slowpath->drv_info_to_mcp;
8330
8331         if (bnx2x_ilt_mem_op_cnic(bp, ILT_MEMOP_ALLOC))
8332                 goto alloc_mem_err;
8333
8334         return 0;
8335
8336 alloc_mem_err:
8337         bnx2x_free_mem_cnic(bp);
8338         BNX2X_ERR("Can't allocate memory\n");
8339         return -ENOMEM;
8340 }
8341
8342 int bnx2x_alloc_mem(struct bnx2x *bp)
8343 {
8344         int i, allocated, context_size;
8345
8346         if (!CONFIGURE_NIC_MODE(bp) && !bp->t2) {
8347                 /* allocate searcher T2 table */
8348                 bp->t2 = BNX2X_PCI_ALLOC(&bp->t2_mapping, SRC_T2_SZ);
8349                 if (!bp->t2)
8350                         goto alloc_mem_err;
8351         }
8352
8353         bp->def_status_blk = BNX2X_PCI_ALLOC(&bp->def_status_blk_mapping,
8354                                              sizeof(struct host_sp_status_block));
8355         if (!bp->def_status_blk)
8356                 goto alloc_mem_err;
8357
8358         bp->slowpath = BNX2X_PCI_ALLOC(&bp->slowpath_mapping,
8359                                        sizeof(struct bnx2x_slowpath));
8360         if (!bp->slowpath)
8361                 goto alloc_mem_err;
8362
8363         /* Allocate memory for CDU context:
8364          * This memory is allocated separately and not in the generic ILT
8365          * functions because CDU differs in few aspects:
8366          * 1. There are multiple entities allocating memory for context -
8367          * 'regular' driver, CNIC and SRIOV driver. Each separately controls
8368          * its own ILT lines.
8369          * 2. Since CDU page-size is not a single 4KB page (which is the case
8370          * for the other ILT clients), to be efficient we want to support
8371          * allocation of sub-page-size in the last entry.
8372          * 3. Context pointers are used by the driver to pass to FW / update
8373          * the context (for the other ILT clients the pointers are used just to
8374          * free the memory during unload).
8375          */
8376         context_size = sizeof(union cdu_context) * BNX2X_L2_CID_COUNT(bp);
8377
8378         for (i = 0, allocated = 0; allocated < context_size; i++) {
8379                 bp->context[i].size = min(CDU_ILT_PAGE_SZ,
8380                                           (context_size - allocated));
8381                 bp->context[i].vcxt = BNX2X_PCI_ALLOC(&bp->context[i].cxt_mapping,
8382                                                       bp->context[i].size);
8383                 if (!bp->context[i].vcxt)
8384                         goto alloc_mem_err;
8385                 allocated += bp->context[i].size;
8386         }
8387         bp->ilt->lines = kcalloc(ILT_MAX_LINES, sizeof(struct ilt_line),
8388                                  GFP_KERNEL);
8389         if (!bp->ilt->lines)
8390                 goto alloc_mem_err;
8391
8392         if (bnx2x_ilt_mem_op(bp, ILT_MEMOP_ALLOC))
8393                 goto alloc_mem_err;
8394
8395         if (bnx2x_iov_alloc_mem(bp))
8396                 goto alloc_mem_err;
8397
8398         /* Slow path ring */
8399         bp->spq = BNX2X_PCI_ALLOC(&bp->spq_mapping, BCM_PAGE_SIZE);
8400         if (!bp->spq)
8401                 goto alloc_mem_err;
8402
8403         /* EQ */
8404         bp->eq_ring = BNX2X_PCI_ALLOC(&bp->eq_mapping,
8405                                       BCM_PAGE_SIZE * NUM_EQ_PAGES);
8406         if (!bp->eq_ring)
8407                 goto alloc_mem_err;
8408
8409         return 0;
8410
8411 alloc_mem_err:
8412         bnx2x_free_mem(bp);
8413         BNX2X_ERR("Can't allocate memory\n");
8414         return -ENOMEM;
8415 }
8416
8417 /*
8418  * Init service functions
8419  */
8420
8421 int bnx2x_set_mac_one(struct bnx2x *bp, u8 *mac,
8422                       struct bnx2x_vlan_mac_obj *obj, bool set,
8423                       int mac_type, unsigned long *ramrod_flags)
8424 {
8425         int rc;
8426         struct bnx2x_vlan_mac_ramrod_params ramrod_param;
8427
8428         memset(&ramrod_param, 0, sizeof(ramrod_param));
8429
8430         /* Fill general parameters */
8431         ramrod_param.vlan_mac_obj = obj;
8432         ramrod_param.ramrod_flags = *ramrod_flags;
8433
8434         /* Fill a user request section if needed */
8435         if (!test_bit(RAMROD_CONT, ramrod_flags)) {
8436                 memcpy(ramrod_param.user_req.u.mac.mac, mac, ETH_ALEN);
8437
8438                 __set_bit(mac_type, &ramrod_param.user_req.vlan_mac_flags);
8439
8440                 /* Set the command: ADD or DEL */
8441                 if (set)
8442                         ramrod_param.user_req.cmd = BNX2X_VLAN_MAC_ADD;
8443                 else
8444                         ramrod_param.user_req.cmd = BNX2X_VLAN_MAC_DEL;
8445         }
8446
8447         rc = bnx2x_config_vlan_mac(bp, &ramrod_param);
8448
8449         if (rc == -EEXIST) {
8450                 DP(BNX2X_MSG_SP, "Failed to schedule ADD operations: %d\n", rc);
8451                 /* do not treat adding same MAC as error */
8452                 rc = 0;
8453         } else if (rc < 0)
8454                 BNX2X_ERR("%s MAC failed\n", (set ? "Set" : "Del"));
8455
8456         return rc;
8457 }
8458
8459 int bnx2x_set_vlan_one(struct bnx2x *bp, u16 vlan,
8460                        struct bnx2x_vlan_mac_obj *obj, bool set,
8461                        unsigned long *ramrod_flags)
8462 {
8463         int rc;
8464         struct bnx2x_vlan_mac_ramrod_params ramrod_param;
8465
8466         memset(&ramrod_param, 0, sizeof(ramrod_param));
8467
8468         /* Fill general parameters */
8469         ramrod_param.vlan_mac_obj = obj;
8470         ramrod_param.ramrod_flags = *ramrod_flags;
8471
8472         /* Fill a user request section if needed */
8473         if (!test_bit(RAMROD_CONT, ramrod_flags)) {
8474                 ramrod_param.user_req.u.vlan.vlan = vlan;
8475                 /* Set the command: ADD or DEL */
8476                 if (set)
8477                         ramrod_param.user_req.cmd = BNX2X_VLAN_MAC_ADD;
8478                 else
8479                         ramrod_param.user_req.cmd = BNX2X_VLAN_MAC_DEL;
8480         }
8481
8482         rc = bnx2x_config_vlan_mac(bp, &ramrod_param);
8483
8484         if (rc == -EEXIST) {
8485                 /* Do not treat adding same vlan as error. */
8486                 DP(BNX2X_MSG_SP, "Failed to schedule ADD operations: %d\n", rc);
8487                 rc = 0;
8488         } else if (rc < 0) {
8489                 BNX2X_ERR("%s VLAN failed\n", (set ? "Set" : "Del"));
8490         }
8491
8492         return rc;
8493 }
8494
8495 int bnx2x_del_all_macs(struct bnx2x *bp,
8496                        struct bnx2x_vlan_mac_obj *mac_obj,
8497                        int mac_type, bool wait_for_comp)
8498 {
8499         int rc;
8500         unsigned long ramrod_flags = 0, vlan_mac_flags = 0;
8501
8502         /* Wait for completion of requested */
8503         if (wait_for_comp)
8504                 __set_bit(RAMROD_COMP_WAIT, &ramrod_flags);
8505
8506         /* Set the mac type of addresses we want to clear */
8507         __set_bit(mac_type, &vlan_mac_flags);
8508
8509         rc = mac_obj->delete_all(bp, mac_obj, &vlan_mac_flags, &ramrod_flags);
8510         if (rc < 0)
8511                 BNX2X_ERR("Failed to delete MACs: %d\n", rc);
8512
8513         return rc;
8514 }
8515
8516 int bnx2x_set_eth_mac(struct bnx2x *bp, bool set)
8517 {
8518         if (IS_PF(bp)) {
8519                 unsigned long ramrod_flags = 0;
8520
8521                 DP(NETIF_MSG_IFUP, "Adding Eth MAC\n");
8522                 __set_bit(RAMROD_COMP_WAIT, &ramrod_flags);
8523                 return bnx2x_set_mac_one(bp, bp->dev->dev_addr,
8524                                          &bp->sp_objs->mac_obj, set,
8525                                          BNX2X_ETH_MAC, &ramrod_flags);
8526         } else { /* vf */
8527                 return bnx2x_vfpf_config_mac(bp, bp->dev->dev_addr,
8528                                              bp->fp->index, set);
8529         }
8530 }
8531
8532 int bnx2x_setup_leading(struct bnx2x *bp)
8533 {
8534         if (IS_PF(bp))
8535                 return bnx2x_setup_queue(bp, &bp->fp[0], true);
8536         else /* VF */
8537                 return bnx2x_vfpf_setup_q(bp, &bp->fp[0], true);
8538 }
8539
8540 /**
8541  * bnx2x_set_int_mode - configure interrupt mode
8542  *
8543  * @bp:         driver handle
8544  *
8545  * In case of MSI-X it will also try to enable MSI-X.
8546  */
8547 int bnx2x_set_int_mode(struct bnx2x *bp)
8548 {
8549         int rc = 0;
8550
8551         if (IS_VF(bp) && int_mode != BNX2X_INT_MODE_MSIX) {
8552                 BNX2X_ERR("VF not loaded since interrupt mode not msix\n");
8553                 return -EINVAL;
8554         }
8555
8556         switch (int_mode) {
8557         case BNX2X_INT_MODE_MSIX:
8558                 /* attempt to enable msix */
8559                 rc = bnx2x_enable_msix(bp);
8560
8561                 /* msix attained */
8562                 if (!rc)
8563                         return 0;
8564
8565                 /* vfs use only msix */
8566                 if (rc && IS_VF(bp))
8567                         return rc;
8568
8569                 /* failed to enable multiple MSI-X */
8570                 BNX2X_DEV_INFO("Failed to enable multiple MSI-X (%d), set number of queues to %d\n",
8571                                bp->num_queues,
8572                                1 + bp->num_cnic_queues);
8573
8574                 /* fall through */
8575         case BNX2X_INT_MODE_MSI:
8576                 bnx2x_enable_msi(bp);
8577
8578                 /* fall through */
8579         case BNX2X_INT_MODE_INTX:
8580                 bp->num_ethernet_queues = 1;
8581                 bp->num_queues = bp->num_ethernet_queues + bp->num_cnic_queues;
8582                 BNX2X_DEV_INFO("set number of queues to 1\n");
8583                 break;
8584         default:
8585                 BNX2X_DEV_INFO("unknown value in int_mode module parameter\n");
8586                 return -EINVAL;
8587         }
8588         return 0;
8589 }
8590
8591 /* must be called prior to any HW initializations */
8592 static inline u16 bnx2x_cid_ilt_lines(struct bnx2x *bp)
8593 {
8594         if (IS_SRIOV(bp))
8595                 return (BNX2X_FIRST_VF_CID + BNX2X_VF_CIDS)/ILT_PAGE_CIDS;
8596         return L2_ILT_LINES(bp);
8597 }
8598
8599 void bnx2x_ilt_set_info(struct bnx2x *bp)
8600 {
8601         struct ilt_client_info *ilt_client;
8602         struct bnx2x_ilt *ilt = BP_ILT(bp);
8603         u16 line = 0;
8604
8605         ilt->start_line = FUNC_ILT_BASE(BP_FUNC(bp));
8606         DP(BNX2X_MSG_SP, "ilt starts at line %d\n", ilt->start_line);
8607
8608         /* CDU */
8609         ilt_client = &ilt->clients[ILT_CLIENT_CDU];
8610         ilt_client->client_num = ILT_CLIENT_CDU;
8611         ilt_client->page_size = CDU_ILT_PAGE_SZ;
8612         ilt_client->flags = ILT_CLIENT_SKIP_MEM;
8613         ilt_client->start = line;
8614         line += bnx2x_cid_ilt_lines(bp);
8615
8616         if (CNIC_SUPPORT(bp))
8617                 line += CNIC_ILT_LINES;
8618         ilt_client->end = line - 1;
8619
8620         DP(NETIF_MSG_IFUP, "ilt client[CDU]: start %d, end %d, psz 0x%x, flags 0x%x, hw psz %d\n",
8621            ilt_client->start,
8622            ilt_client->end,
8623            ilt_client->page_size,
8624            ilt_client->flags,
8625            ilog2(ilt_client->page_size >> 12));
8626
8627         /* QM */
8628         if (QM_INIT(bp->qm_cid_count)) {
8629                 ilt_client = &ilt->clients[ILT_CLIENT_QM];
8630                 ilt_client->client_num = ILT_CLIENT_QM;
8631                 ilt_client->page_size = QM_ILT_PAGE_SZ;
8632                 ilt_client->flags = 0;
8633                 ilt_client->start = line;
8634
8635                 /* 4 bytes for each cid */
8636                 line += DIV_ROUND_UP(bp->qm_cid_count * QM_QUEUES_PER_FUNC * 4,
8637                                                          QM_ILT_PAGE_SZ);
8638
8639                 ilt_client->end = line - 1;
8640
8641                 DP(NETIF_MSG_IFUP,
8642                    "ilt client[QM]: start %d, end %d, psz 0x%x, flags 0x%x, hw psz %d\n",
8643                    ilt_client->start,
8644                    ilt_client->end,
8645                    ilt_client->page_size,
8646                    ilt_client->flags,
8647                    ilog2(ilt_client->page_size >> 12));
8648         }
8649
8650         if (CNIC_SUPPORT(bp)) {
8651                 /* SRC */
8652                 ilt_client = &ilt->clients[ILT_CLIENT_SRC];
8653                 ilt_client->client_num = ILT_CLIENT_SRC;
8654                 ilt_client->page_size = SRC_ILT_PAGE_SZ;
8655                 ilt_client->flags = 0;
8656                 ilt_client->start = line;
8657                 line += SRC_ILT_LINES;
8658                 ilt_client->end = line - 1;
8659
8660                 DP(NETIF_MSG_IFUP,
8661                    "ilt client[SRC]: start %d, end %d, psz 0x%x, flags 0x%x, hw psz %d\n",
8662                    ilt_client->start,
8663                    ilt_client->end,
8664                    ilt_client->page_size,
8665                    ilt_client->flags,
8666                    ilog2(ilt_client->page_size >> 12));
8667
8668                 /* TM */
8669                 ilt_client = &ilt->clients[ILT_CLIENT_TM];
8670                 ilt_client->client_num = ILT_CLIENT_TM;
8671                 ilt_client->page_size = TM_ILT_PAGE_SZ;
8672                 ilt_client->flags = 0;
8673                 ilt_client->start = line;
8674                 line += TM_ILT_LINES;
8675                 ilt_client->end = line - 1;
8676
8677                 DP(NETIF_MSG_IFUP,
8678                    "ilt client[TM]: start %d, end %d, psz 0x%x, flags 0x%x, hw psz %d\n",
8679                    ilt_client->start,
8680                    ilt_client->end,
8681                    ilt_client->page_size,
8682                    ilt_client->flags,
8683                    ilog2(ilt_client->page_size >> 12));
8684         }
8685
8686         BUG_ON(line > ILT_MAX_LINES);
8687 }
8688
8689 /**
8690  * bnx2x_pf_q_prep_init - prepare INIT transition parameters
8691  *
8692  * @bp:                 driver handle
8693  * @fp:                 pointer to fastpath
8694  * @init_params:        pointer to parameters structure
8695  *
8696  * parameters configured:
8697  *      - HC configuration
8698  *      - Queue's CDU context
8699  */
8700 static void bnx2x_pf_q_prep_init(struct bnx2x *bp,
8701         struct bnx2x_fastpath *fp, struct bnx2x_queue_init_params *init_params)
8702 {
8703         u8 cos;
8704         int cxt_index, cxt_offset;
8705
8706         /* FCoE Queue uses Default SB, thus has no HC capabilities */
8707         if (!IS_FCOE_FP(fp)) {
8708                 __set_bit(BNX2X_Q_FLG_HC, &init_params->rx.flags);
8709                 __set_bit(BNX2X_Q_FLG_HC, &init_params->tx.flags);
8710
8711                 /* If HC is supported, enable host coalescing in the transition
8712                  * to INIT state.
8713                  */
8714                 __set_bit(BNX2X_Q_FLG_HC_EN, &init_params->rx.flags);
8715                 __set_bit(BNX2X_Q_FLG_HC_EN, &init_params->tx.flags);
8716
8717                 /* HC rate */
8718                 init_params->rx.hc_rate = bp->rx_ticks ?
8719                         (1000000 / bp->rx_ticks) : 0;
8720                 init_params->tx.hc_rate = bp->tx_ticks ?
8721                         (1000000 / bp->tx_ticks) : 0;
8722
8723                 /* FW SB ID */
8724                 init_params->rx.fw_sb_id = init_params->tx.fw_sb_id =
8725                         fp->fw_sb_id;
8726
8727                 /*
8728                  * CQ index among the SB indices: FCoE clients uses the default
8729                  * SB, therefore it's different.
8730                  */
8731                 init_params->rx.sb_cq_index = HC_INDEX_ETH_RX_CQ_CONS;
8732                 init_params->tx.sb_cq_index = HC_INDEX_ETH_FIRST_TX_CQ_CONS;
8733         }
8734
8735         /* set maximum number of COSs supported by this queue */
8736         init_params->max_cos = fp->max_cos;
8737
8738         DP(NETIF_MSG_IFUP, "fp: %d setting queue params max cos to: %d\n",
8739             fp->index, init_params->max_cos);
8740
8741         /* set the context pointers queue object */
8742         for (cos = FIRST_TX_COS_INDEX; cos < init_params->max_cos; cos++) {
8743                 cxt_index = fp->txdata_ptr[cos]->cid / ILT_PAGE_CIDS;
8744                 cxt_offset = fp->txdata_ptr[cos]->cid - (cxt_index *
8745                                 ILT_PAGE_CIDS);
8746                 init_params->cxts[cos] =
8747                         &bp->context[cxt_index].vcxt[cxt_offset].eth;
8748         }
8749 }
8750
8751 static int bnx2x_setup_tx_only(struct bnx2x *bp, struct bnx2x_fastpath *fp,
8752                         struct bnx2x_queue_state_params *q_params,
8753                         struct bnx2x_queue_setup_tx_only_params *tx_only_params,
8754                         int tx_index, bool leading)
8755 {
8756         memset(tx_only_params, 0, sizeof(*tx_only_params));
8757
8758         /* Set the command */
8759         q_params->cmd = BNX2X_Q_CMD_SETUP_TX_ONLY;
8760
8761         /* Set tx-only QUEUE flags: don't zero statistics */
8762         tx_only_params->flags = bnx2x_get_common_flags(bp, fp, false);
8763
8764         /* choose the index of the cid to send the slow path on */
8765         tx_only_params->cid_index = tx_index;
8766
8767         /* Set general TX_ONLY_SETUP parameters */
8768         bnx2x_pf_q_prep_general(bp, fp, &tx_only_params->gen_params, tx_index);
8769
8770         /* Set Tx TX_ONLY_SETUP parameters */
8771         bnx2x_pf_tx_q_prep(bp, fp, &tx_only_params->txq_params, tx_index);
8772
8773         DP(NETIF_MSG_IFUP,
8774            "preparing to send tx-only ramrod for connection: cos %d, primary cid %d, cid %d, client id %d, sp-client id %d, flags %lx\n",
8775            tx_index, q_params->q_obj->cids[FIRST_TX_COS_INDEX],
8776            q_params->q_obj->cids[tx_index], q_params->q_obj->cl_id,
8777            tx_only_params->gen_params.spcl_id, tx_only_params->flags);
8778
8779         /* send the ramrod */
8780         return bnx2x_queue_state_change(bp, q_params);
8781 }
8782
8783 /**
8784  * bnx2x_setup_queue - setup queue
8785  *
8786  * @bp:         driver handle
8787  * @fp:         pointer to fastpath
8788  * @leading:    is leading
8789  *
8790  * This function performs 2 steps in a Queue state machine
8791  *      actually: 1) RESET->INIT 2) INIT->SETUP
8792  */
8793
8794 int bnx2x_setup_queue(struct bnx2x *bp, struct bnx2x_fastpath *fp,
8795                        bool leading)
8796 {
8797         struct bnx2x_queue_state_params q_params = {NULL};
8798         struct bnx2x_queue_setup_params *setup_params =
8799                                                 &q_params.params.setup;
8800         struct bnx2x_queue_setup_tx_only_params *tx_only_params =
8801                                                 &q_params.params.tx_only;
8802         int rc;
8803         u8 tx_index;
8804
8805         DP(NETIF_MSG_IFUP, "setting up queue %d\n", fp->index);
8806
8807         /* reset IGU state skip FCoE L2 queue */
8808         if (!IS_FCOE_FP(fp))
8809                 bnx2x_ack_sb(bp, fp->igu_sb_id, USTORM_ID, 0,
8810                              IGU_INT_ENABLE, 0);
8811
8812         q_params.q_obj = &bnx2x_sp_obj(bp, fp).q_obj;
8813         /* We want to wait for completion in this context */
8814         __set_bit(RAMROD_COMP_WAIT, &q_params.ramrod_flags);
8815
8816         /* Prepare the INIT parameters */
8817         bnx2x_pf_q_prep_init(bp, fp, &q_params.params.init);
8818
8819         /* Set the command */
8820         q_params.cmd = BNX2X_Q_CMD_INIT;
8821
8822         /* Change the state to INIT */
8823         rc = bnx2x_queue_state_change(bp, &q_params);
8824         if (rc) {
8825                 BNX2X_ERR("Queue(%d) INIT failed\n", fp->index);
8826                 return rc;
8827         }
8828
8829         DP(NETIF_MSG_IFUP, "init complete\n");
8830
8831         /* Now move the Queue to the SETUP state... */
8832         memset(setup_params, 0, sizeof(*setup_params));
8833
8834         /* Set QUEUE flags */
8835         setup_params->flags = bnx2x_get_q_flags(bp, fp, leading);
8836
8837         /* Set general SETUP parameters */
8838         bnx2x_pf_q_prep_general(bp, fp, &setup_params->gen_params,
8839                                 FIRST_TX_COS_INDEX);
8840
8841         bnx2x_pf_rx_q_prep(bp, fp, &setup_params->pause_params,
8842                             &setup_params->rxq_params);
8843
8844         bnx2x_pf_tx_q_prep(bp, fp, &setup_params->txq_params,
8845                            FIRST_TX_COS_INDEX);
8846
8847         /* Set the command */
8848         q_params.cmd = BNX2X_Q_CMD_SETUP;
8849
8850         if (IS_FCOE_FP(fp))
8851                 bp->fcoe_init = true;
8852
8853         /* Change the state to SETUP */
8854         rc = bnx2x_queue_state_change(bp, &q_params);
8855         if (rc) {
8856                 BNX2X_ERR("Queue(%d) SETUP failed\n", fp->index);
8857                 return rc;
8858         }
8859
8860         /* loop through the relevant tx-only indices */
8861         for (tx_index = FIRST_TX_ONLY_COS_INDEX;
8862               tx_index < fp->max_cos;
8863               tx_index++) {
8864
8865                 /* prepare and send tx-only ramrod*/
8866                 rc = bnx2x_setup_tx_only(bp, fp, &q_params,
8867                                           tx_only_params, tx_index, leading);
8868                 if (rc) {
8869                         BNX2X_ERR("Queue(%d.%d) TX_ONLY_SETUP failed\n",
8870                                   fp->index, tx_index);
8871                         return rc;
8872                 }
8873         }
8874
8875         return rc;
8876 }
8877
8878 static int bnx2x_stop_queue(struct bnx2x *bp, int index)
8879 {
8880         struct bnx2x_fastpath *fp = &bp->fp[index];
8881         struct bnx2x_fp_txdata *txdata;
8882         struct bnx2x_queue_state_params q_params = {NULL};
8883         int rc, tx_index;
8884
8885         DP(NETIF_MSG_IFDOWN, "stopping queue %d cid %d\n", index, fp->cid);
8886
8887         q_params.q_obj = &bnx2x_sp_obj(bp, fp).q_obj;
8888         /* We want to wait for completion in this context */
8889         __set_bit(RAMROD_COMP_WAIT, &q_params.ramrod_flags);
8890
8891         /* close tx-only connections */
8892         for (tx_index = FIRST_TX_ONLY_COS_INDEX;
8893              tx_index < fp->max_cos;
8894              tx_index++){
8895
8896                 /* ascertain this is a normal queue*/
8897                 txdata = fp->txdata_ptr[tx_index];
8898
8899                 DP(NETIF_MSG_IFDOWN, "stopping tx-only queue %d\n",
8900                                                         txdata->txq_index);
8901
8902                 /* send halt terminate on tx-only connection */
8903                 q_params.cmd = BNX2X_Q_CMD_TERMINATE;
8904                 memset(&q_params.params.terminate, 0,
8905                        sizeof(q_params.params.terminate));
8906                 q_params.params.terminate.cid_index = tx_index;
8907
8908                 rc = bnx2x_queue_state_change(bp, &q_params);
8909                 if (rc)
8910                         return rc;
8911
8912                 /* send halt terminate on tx-only connection */
8913                 q_params.cmd = BNX2X_Q_CMD_CFC_DEL;
8914                 memset(&q_params.params.cfc_del, 0,
8915                        sizeof(q_params.params.cfc_del));
8916                 q_params.params.cfc_del.cid_index = tx_index;
8917                 rc = bnx2x_queue_state_change(bp, &q_params);
8918                 if (rc)
8919                         return rc;
8920         }
8921         /* Stop the primary connection: */
8922         /* ...halt the connection */
8923         q_params.cmd = BNX2X_Q_CMD_HALT;
8924         rc = bnx2x_queue_state_change(bp, &q_params);
8925         if (rc)
8926                 return rc;
8927
8928         /* ...terminate the connection */
8929         q_params.cmd = BNX2X_Q_CMD_TERMINATE;
8930         memset(&q_params.params.terminate, 0,
8931                sizeof(q_params.params.terminate));
8932         q_params.params.terminate.cid_index = FIRST_TX_COS_INDEX;
8933         rc = bnx2x_queue_state_change(bp, &q_params);
8934         if (rc)
8935                 return rc;
8936         /* ...delete cfc entry */
8937         q_params.cmd = BNX2X_Q_CMD_CFC_DEL;
8938         memset(&q_params.params.cfc_del, 0,
8939                sizeof(q_params.params.cfc_del));
8940         q_params.params.cfc_del.cid_index = FIRST_TX_COS_INDEX;
8941         return bnx2x_queue_state_change(bp, &q_params);
8942 }
8943
8944 static void bnx2x_reset_func(struct bnx2x *bp)
8945 {
8946         int port = BP_PORT(bp);
8947         int func = BP_FUNC(bp);
8948         int i;
8949
8950         /* Disable the function in the FW */
8951         REG_WR8(bp, BAR_XSTRORM_INTMEM + XSTORM_FUNC_EN_OFFSET(func), 0);
8952         REG_WR8(bp, BAR_CSTRORM_INTMEM + CSTORM_FUNC_EN_OFFSET(func), 0);
8953         REG_WR8(bp, BAR_TSTRORM_INTMEM + TSTORM_FUNC_EN_OFFSET(func), 0);
8954         REG_WR8(bp, BAR_USTRORM_INTMEM + USTORM_FUNC_EN_OFFSET(func), 0);
8955
8956         /* FP SBs */
8957         for_each_eth_queue(bp, i) {
8958                 struct bnx2x_fastpath *fp = &bp->fp[i];
8959                 REG_WR8(bp, BAR_CSTRORM_INTMEM +
8960                            CSTORM_STATUS_BLOCK_DATA_STATE_OFFSET(fp->fw_sb_id),
8961                            SB_DISABLED);
8962         }
8963
8964         if (CNIC_LOADED(bp))
8965                 /* CNIC SB */
8966                 REG_WR8(bp, BAR_CSTRORM_INTMEM +
8967                         CSTORM_STATUS_BLOCK_DATA_STATE_OFFSET
8968                         (bnx2x_cnic_fw_sb_id(bp)), SB_DISABLED);
8969
8970         /* SP SB */
8971         REG_WR8(bp, BAR_CSTRORM_INTMEM +
8972                 CSTORM_SP_STATUS_BLOCK_DATA_STATE_OFFSET(func),
8973                 SB_DISABLED);
8974
8975         for (i = 0; i < XSTORM_SPQ_DATA_SIZE / 4; i++)
8976                 REG_WR(bp, BAR_XSTRORM_INTMEM + XSTORM_SPQ_DATA_OFFSET(func),
8977                        0);
8978
8979         /* Configure IGU */
8980         if (bp->common.int_block == INT_BLOCK_HC) {
8981                 REG_WR(bp, HC_REG_LEADING_EDGE_0 + port*8, 0);
8982                 REG_WR(bp, HC_REG_TRAILING_EDGE_0 + port*8, 0);
8983         } else {
8984                 REG_WR(bp, IGU_REG_LEADING_EDGE_LATCH, 0);
8985                 REG_WR(bp, IGU_REG_TRAILING_EDGE_LATCH, 0);
8986         }
8987
8988         if (CNIC_LOADED(bp)) {
8989                 /* Disable Timer scan */
8990                 REG_WR(bp, TM_REG_EN_LINEAR0_TIMER + port*4, 0);
8991                 /*
8992                  * Wait for at least 10ms and up to 2 second for the timers
8993                  * scan to complete
8994                  */
8995                 for (i = 0; i < 200; i++) {
8996                         usleep_range(10000, 20000);
8997                         if (!REG_RD(bp, TM_REG_LIN0_SCAN_ON + port*4))
8998                                 break;
8999                 }
9000         }
9001         /* Clear ILT */
9002         bnx2x_clear_func_ilt(bp, func);
9003
9004         /* Timers workaround bug for E2: if this is vnic-3,
9005          * we need to set the entire ilt range for this timers.
9006          */
9007         if (!CHIP_IS_E1x(bp) && BP_VN(bp) == 3) {
9008                 struct ilt_client_info ilt_cli;
9009                 /* use dummy TM client */
9010                 memset(&ilt_cli, 0, sizeof(struct ilt_client_info));
9011                 ilt_cli.start = 0;
9012                 ilt_cli.end = ILT_NUM_PAGE_ENTRIES - 1;
9013                 ilt_cli.client_num = ILT_CLIENT_TM;
9014
9015                 bnx2x_ilt_boundry_init_op(bp, &ilt_cli, 0, INITOP_CLEAR);
9016         }
9017
9018         /* this assumes that reset_port() called before reset_func()*/
9019         if (!CHIP_IS_E1x(bp))
9020                 bnx2x_pf_disable(bp);
9021
9022         bp->dmae_ready = 0;
9023 }
9024
9025 static void bnx2x_reset_port(struct bnx2x *bp)
9026 {
9027         int port = BP_PORT(bp);
9028         u32 val;
9029
9030         /* Reset physical Link */
9031         bnx2x__link_reset(bp);
9032
9033         REG_WR(bp, NIG_REG_MASK_INTERRUPT_PORT0 + port*4, 0);
9034
9035         /* Do not rcv packets to BRB */
9036         REG_WR(bp, NIG_REG_LLH0_BRB1_DRV_MASK + port*4, 0x0);
9037         /* Do not direct rcv packets that are not for MCP to the BRB */
9038         REG_WR(bp, (port ? NIG_REG_LLH1_BRB1_NOT_MCP :
9039                            NIG_REG_LLH0_BRB1_NOT_MCP), 0x0);
9040
9041         /* Configure AEU */
9042         REG_WR(bp, MISC_REG_AEU_MASK_ATTN_FUNC_0 + port*4, 0);
9043
9044         msleep(100);
9045         /* Check for BRB port occupancy */
9046         val = REG_RD(bp, BRB1_REG_PORT_NUM_OCC_BLOCKS_0 + port*4);
9047         if (val)
9048                 DP(NETIF_MSG_IFDOWN,
9049                    "BRB1 is not empty  %d blocks are occupied\n", val);
9050
9051         /* TODO: Close Doorbell port? */
9052 }
9053
9054 static int bnx2x_reset_hw(struct bnx2x *bp, u32 load_code)
9055 {
9056         struct bnx2x_func_state_params func_params = {NULL};
9057
9058         /* Prepare parameters for function state transitions */
9059         __set_bit(RAMROD_COMP_WAIT, &func_params.ramrod_flags);
9060
9061         func_params.f_obj = &bp->func_obj;
9062         func_params.cmd = BNX2X_F_CMD_HW_RESET;
9063
9064         func_params.params.hw_init.load_phase = load_code;
9065
9066         return bnx2x_func_state_change(bp, &func_params);
9067 }
9068
9069 static int bnx2x_func_stop(struct bnx2x *bp)
9070 {
9071         struct bnx2x_func_state_params func_params = {NULL};
9072         int rc;
9073
9074         /* Prepare parameters for function state transitions */
9075         __set_bit(RAMROD_COMP_WAIT, &func_params.ramrod_flags);
9076         func_params.f_obj = &bp->func_obj;
9077         func_params.cmd = BNX2X_F_CMD_STOP;
9078
9079         /*
9080          * Try to stop the function the 'good way'. If fails (in case
9081          * of a parity error during bnx2x_chip_cleanup()) and we are
9082          * not in a debug mode, perform a state transaction in order to
9083          * enable further HW_RESET transaction.
9084          */
9085         rc = bnx2x_func_state_change(bp, &func_params);
9086         if (rc) {
9087 #ifdef BNX2X_STOP_ON_ERROR
9088                 return rc;
9089 #else
9090                 BNX2X_ERR("FUNC_STOP ramrod failed. Running a dry transaction\n");
9091                 __set_bit(RAMROD_DRV_CLR_ONLY, &func_params.ramrod_flags);
9092                 return bnx2x_func_state_change(bp, &func_params);
9093 #endif
9094         }
9095
9096         return 0;
9097 }
9098
9099 /**
9100  * bnx2x_send_unload_req - request unload mode from the MCP.
9101  *
9102  * @bp:                 driver handle
9103  * @unload_mode:        requested function's unload mode
9104  *
9105  * Return unload mode returned by the MCP: COMMON, PORT or FUNC.
9106  */
9107 u32 bnx2x_send_unload_req(struct bnx2x *bp, int unload_mode)
9108 {
9109         u32 reset_code = 0;
9110         int port = BP_PORT(bp);
9111
9112         /* Select the UNLOAD request mode */
9113         if (unload_mode == UNLOAD_NORMAL)
9114                 reset_code = DRV_MSG_CODE_UNLOAD_REQ_WOL_DIS;
9115
9116         else if (bp->flags & NO_WOL_FLAG)
9117                 reset_code = DRV_MSG_CODE_UNLOAD_REQ_WOL_MCP;
9118
9119         else if (bp->wol) {
9120                 u32 emac_base = port ? GRCBASE_EMAC1 : GRCBASE_EMAC0;
9121                 u8 *mac_addr = bp->dev->dev_addr;
9122                 struct pci_dev *pdev = bp->pdev;
9123                 u32 val;
9124                 u16 pmc;
9125
9126                 /* The mac address is written to entries 1-4 to
9127                  * preserve entry 0 which is used by the PMF
9128                  */
9129                 u8 entry = (BP_VN(bp) + 1)*8;
9130
9131                 val = (mac_addr[0] << 8) | mac_addr[1];
9132                 EMAC_WR(bp, EMAC_REG_EMAC_MAC_MATCH + entry, val);
9133
9134                 val = (mac_addr[2] << 24) | (mac_addr[3] << 16) |
9135                       (mac_addr[4] << 8) | mac_addr[5];
9136                 EMAC_WR(bp, EMAC_REG_EMAC_MAC_MATCH + entry + 4, val);
9137
9138                 /* Enable the PME and clear the status */
9139                 pci_read_config_word(pdev, pdev->pm_cap + PCI_PM_CTRL, &pmc);
9140                 pmc |= PCI_PM_CTRL_PME_ENABLE | PCI_PM_CTRL_PME_STATUS;
9141                 pci_write_config_word(pdev, pdev->pm_cap + PCI_PM_CTRL, pmc);
9142
9143                 reset_code = DRV_MSG_CODE_UNLOAD_REQ_WOL_EN;
9144
9145         } else
9146                 reset_code = DRV_MSG_CODE_UNLOAD_REQ_WOL_DIS;
9147
9148         /* Send the request to the MCP */
9149         if (!BP_NOMCP(bp))
9150                 reset_code = bnx2x_fw_command(bp, reset_code, 0);
9151         else {
9152                 int path = BP_PATH(bp);
9153
9154                 DP(NETIF_MSG_IFDOWN, "NO MCP - load counts[%d]      %d, %d, %d\n",
9155                    path, bnx2x_load_count[path][0], bnx2x_load_count[path][1],
9156                    bnx2x_load_count[path][2]);
9157                 bnx2x_load_count[path][0]--;
9158                 bnx2x_load_count[path][1 + port]--;
9159                 DP(NETIF_MSG_IFDOWN, "NO MCP - new load counts[%d]  %d, %d, %d\n",
9160                    path, bnx2x_load_count[path][0], bnx2x_load_count[path][1],
9161                    bnx2x_load_count[path][2]);
9162                 if (bnx2x_load_count[path][0] == 0)
9163                         reset_code = FW_MSG_CODE_DRV_UNLOAD_COMMON;
9164                 else if (bnx2x_load_count[path][1 + port] == 0)
9165                         reset_code = FW_MSG_CODE_DRV_UNLOAD_PORT;
9166                 else
9167                         reset_code = FW_MSG_CODE_DRV_UNLOAD_FUNCTION;
9168         }
9169
9170         return reset_code;
9171 }
9172
9173 /**
9174  * bnx2x_send_unload_done - send UNLOAD_DONE command to the MCP.
9175  *
9176  * @bp:         driver handle
9177  * @keep_link:          true iff link should be kept up
9178  */
9179 void bnx2x_send_unload_done(struct bnx2x *bp, bool keep_link)
9180 {
9181         u32 reset_param = keep_link ? DRV_MSG_CODE_UNLOAD_SKIP_LINK_RESET : 0;
9182
9183         /* Report UNLOAD_DONE to MCP */
9184         if (!BP_NOMCP(bp))
9185                 bnx2x_fw_command(bp, DRV_MSG_CODE_UNLOAD_DONE, reset_param);
9186 }
9187
9188 static int bnx2x_func_wait_started(struct bnx2x *bp)
9189 {
9190         int tout = 50;
9191         int msix = (bp->flags & USING_MSIX_FLAG) ? 1 : 0;
9192
9193         if (!bp->port.pmf)
9194                 return 0;
9195
9196         /*
9197          * (assumption: No Attention from MCP at this stage)
9198          * PMF probably in the middle of TX disable/enable transaction
9199          * 1. Sync IRS for default SB
9200          * 2. Sync SP queue - this guarantees us that attention handling started
9201          * 3. Wait, that TX disable/enable transaction completes
9202          *
9203          * 1+2 guarantee that if DCBx attention was scheduled it already changed
9204          * pending bit of transaction from STARTED-->TX_STOPPED, if we already
9205          * received completion for the transaction the state is TX_STOPPED.
9206          * State will return to STARTED after completion of TX_STOPPED-->STARTED
9207          * transaction.
9208          */
9209
9210         /* make sure default SB ISR is done */
9211         if (msix)
9212                 synchronize_irq(bp->msix_table[0].vector);
9213         else
9214                 synchronize_irq(bp->pdev->irq);
9215
9216         flush_workqueue(bnx2x_wq);
9217         flush_workqueue(bnx2x_iov_wq);
9218
9219         while (bnx2x_func_get_state(bp, &bp->func_obj) !=
9220                                 BNX2X_F_STATE_STARTED && tout--)
9221                 msleep(20);
9222
9223         if (bnx2x_func_get_state(bp, &bp->func_obj) !=
9224                                                 BNX2X_F_STATE_STARTED) {
9225 #ifdef BNX2X_STOP_ON_ERROR
9226                 BNX2X_ERR("Wrong function state\n");
9227                 return -EBUSY;
9228 #else
9229                 /*
9230                  * Failed to complete the transaction in a "good way"
9231                  * Force both transactions with CLR bit
9232                  */
9233                 struct bnx2x_func_state_params func_params = {NULL};
9234
9235                 DP(NETIF_MSG_IFDOWN,
9236                    "Hmmm... Unexpected function state! Forcing STARTED-->TX_STOPPED-->STARTED\n");
9237
9238                 func_params.f_obj = &bp->func_obj;
9239                 __set_bit(RAMROD_DRV_CLR_ONLY,
9240                                         &func_params.ramrod_flags);
9241
9242                 /* STARTED-->TX_ST0PPED */
9243                 func_params.cmd = BNX2X_F_CMD_TX_STOP;
9244                 bnx2x_func_state_change(bp, &func_params);
9245
9246                 /* TX_ST0PPED-->STARTED */
9247                 func_params.cmd = BNX2X_F_CMD_TX_START;
9248                 return bnx2x_func_state_change(bp, &func_params);
9249 #endif
9250         }
9251
9252         return 0;
9253 }
9254
9255 static void bnx2x_disable_ptp(struct bnx2x *bp)
9256 {
9257         int port = BP_PORT(bp);
9258
9259         /* Disable sending PTP packets to host */
9260         REG_WR(bp, port ? NIG_REG_P1_LLH_PTP_TO_HOST :
9261                NIG_REG_P0_LLH_PTP_TO_HOST, 0x0);
9262
9263         /* Reset PTP event detection rules */
9264         REG_WR(bp, port ? NIG_REG_P1_LLH_PTP_PARAM_MASK :
9265                NIG_REG_P0_LLH_PTP_PARAM_MASK, 0x7FF);
9266         REG_WR(bp, port ? NIG_REG_P1_LLH_PTP_RULE_MASK :
9267                NIG_REG_P0_LLH_PTP_RULE_MASK, 0x3FFF);
9268         REG_WR(bp, port ? NIG_REG_P1_TLLH_PTP_PARAM_MASK :
9269                NIG_REG_P0_TLLH_PTP_PARAM_MASK, 0x7FF);
9270         REG_WR(bp, port ? NIG_REG_P1_TLLH_PTP_RULE_MASK :
9271                NIG_REG_P0_TLLH_PTP_RULE_MASK, 0x3FFF);
9272
9273         /* Disable the PTP feature */
9274         REG_WR(bp, port ? NIG_REG_P1_PTP_EN :
9275                NIG_REG_P0_PTP_EN, 0x0);
9276 }
9277
9278 /* Called during unload, to stop PTP-related stuff */
9279 static void bnx2x_stop_ptp(struct bnx2x *bp)
9280 {
9281         /* Cancel PTP work queue. Should be done after the Tx queues are
9282          * drained to prevent additional scheduling.
9283          */
9284         cancel_work_sync(&bp->ptp_task);
9285
9286         if (bp->ptp_tx_skb) {
9287                 dev_kfree_skb_any(bp->ptp_tx_skb);
9288                 bp->ptp_tx_skb = NULL;
9289         }
9290
9291         /* Disable PTP in HW */
9292         bnx2x_disable_ptp(bp);
9293
9294         DP(BNX2X_MSG_PTP, "PTP stop ended successfully\n");
9295 }
9296
9297 void bnx2x_chip_cleanup(struct bnx2x *bp, int unload_mode, bool keep_link)
9298 {
9299         int port = BP_PORT(bp);
9300         int i, rc = 0;
9301         u8 cos;
9302         struct bnx2x_mcast_ramrod_params rparam = {NULL};
9303         u32 reset_code;
9304
9305         /* Wait until tx fastpath tasks complete */
9306         for_each_tx_queue(bp, i) {
9307                 struct bnx2x_fastpath *fp = &bp->fp[i];
9308
9309                 for_each_cos_in_tx_queue(fp, cos)
9310                         rc = bnx2x_clean_tx_queue(bp, fp->txdata_ptr[cos]);
9311 #ifdef BNX2X_STOP_ON_ERROR
9312                 if (rc)
9313                         return;
9314 #endif
9315         }
9316
9317         /* Give HW time to discard old tx messages */
9318         usleep_range(1000, 2000);
9319
9320         /* Clean all ETH MACs */
9321         rc = bnx2x_del_all_macs(bp, &bp->sp_objs[0].mac_obj, BNX2X_ETH_MAC,
9322                                 false);
9323         if (rc < 0)
9324                 BNX2X_ERR("Failed to delete all ETH macs: %d\n", rc);
9325
9326         /* Clean up UC list  */
9327         rc = bnx2x_del_all_macs(bp, &bp->sp_objs[0].mac_obj, BNX2X_UC_LIST_MAC,
9328                                 true);
9329         if (rc < 0)
9330                 BNX2X_ERR("Failed to schedule DEL commands for UC MACs list: %d\n",
9331                           rc);
9332
9333         /* Disable LLH */
9334         if (!CHIP_IS_E1(bp))
9335                 REG_WR(bp, NIG_REG_LLH0_FUNC_EN + port*8, 0);
9336
9337         /* Set "drop all" (stop Rx).
9338          * We need to take a netif_addr_lock() here in order to prevent
9339          * a race between the completion code and this code.
9340          */
9341         netif_addr_lock_bh(bp->dev);
9342         /* Schedule the rx_mode command */
9343         if (test_bit(BNX2X_FILTER_RX_MODE_PENDING, &bp->sp_state))
9344                 set_bit(BNX2X_FILTER_RX_MODE_SCHED, &bp->sp_state);
9345         else if (bp->slowpath)
9346                 bnx2x_set_storm_rx_mode(bp);
9347
9348         /* Cleanup multicast configuration */
9349         rparam.mcast_obj = &bp->mcast_obj;
9350         rc = bnx2x_config_mcast(bp, &rparam, BNX2X_MCAST_CMD_DEL);
9351         if (rc < 0)
9352                 BNX2X_ERR("Failed to send DEL multicast command: %d\n", rc);
9353
9354         netif_addr_unlock_bh(bp->dev);
9355
9356         bnx2x_iov_chip_cleanup(bp);
9357
9358         /*
9359          * Send the UNLOAD_REQUEST to the MCP. This will return if
9360          * this function should perform FUNC, PORT or COMMON HW
9361          * reset.
9362          */
9363         reset_code = bnx2x_send_unload_req(bp, unload_mode);
9364
9365         /*
9366          * (assumption: No Attention from MCP at this stage)
9367          * PMF probably in the middle of TX disable/enable transaction
9368          */
9369         rc = bnx2x_func_wait_started(bp);
9370         if (rc) {
9371                 BNX2X_ERR("bnx2x_func_wait_started failed\n");
9372 #ifdef BNX2X_STOP_ON_ERROR
9373                 return;
9374 #endif
9375         }
9376
9377         /* Close multi and leading connections
9378          * Completions for ramrods are collected in a synchronous way
9379          */
9380         for_each_eth_queue(bp, i)
9381                 if (bnx2x_stop_queue(bp, i))
9382 #ifdef BNX2X_STOP_ON_ERROR
9383                         return;
9384 #else
9385                         goto unload_error;
9386 #endif
9387
9388         if (CNIC_LOADED(bp)) {
9389                 for_each_cnic_queue(bp, i)
9390                         if (bnx2x_stop_queue(bp, i))
9391 #ifdef BNX2X_STOP_ON_ERROR
9392                                 return;
9393 #else
9394                                 goto unload_error;
9395 #endif
9396         }
9397
9398         /* If SP settings didn't get completed so far - something
9399          * very wrong has happen.
9400          */
9401         if (!bnx2x_wait_sp_comp(bp, ~0x0UL))
9402                 BNX2X_ERR("Hmmm... Common slow path ramrods got stuck!\n");
9403
9404 #ifndef BNX2X_STOP_ON_ERROR
9405 unload_error:
9406 #endif
9407         rc = bnx2x_func_stop(bp);
9408         if (rc) {
9409                 BNX2X_ERR("Function stop failed!\n");
9410 #ifdef BNX2X_STOP_ON_ERROR
9411                 return;
9412 #endif
9413         }
9414
9415         /* stop_ptp should be after the Tx queues are drained to prevent
9416          * scheduling to the cancelled PTP work queue. It should also be after
9417          * function stop ramrod is sent, since as part of this ramrod FW access
9418          * PTP registers.
9419          */
9420         if (bp->flags & PTP_SUPPORTED)
9421                 bnx2x_stop_ptp(bp);
9422
9423         /* Disable HW interrupts, NAPI */
9424         bnx2x_netif_stop(bp, 1);
9425         /* Delete all NAPI objects */
9426         bnx2x_del_all_napi(bp);
9427         if (CNIC_LOADED(bp))
9428                 bnx2x_del_all_napi_cnic(bp);
9429
9430         /* Release IRQs */
9431         bnx2x_free_irq(bp);
9432
9433         /* Reset the chip, unless PCI function is offline. If we reach this
9434          * point following a PCI error handling, it means device is really
9435          * in a bad state and we're about to remove it, so reset the chip
9436          * is not a good idea.
9437          */
9438         if (!pci_channel_offline(bp->pdev)) {
9439                 rc = bnx2x_reset_hw(bp, reset_code);
9440                 if (rc)
9441                         BNX2X_ERR("HW_RESET failed\n");
9442         }
9443
9444         /* Report UNLOAD_DONE to MCP */
9445         bnx2x_send_unload_done(bp, keep_link);
9446 }
9447
9448 void bnx2x_disable_close_the_gate(struct bnx2x *bp)
9449 {
9450         u32 val;
9451
9452         DP(NETIF_MSG_IFDOWN, "Disabling \"close the gates\"\n");
9453
9454         if (CHIP_IS_E1(bp)) {
9455                 int port = BP_PORT(bp);
9456                 u32 addr = port ? MISC_REG_AEU_MASK_ATTN_FUNC_1 :
9457                         MISC_REG_AEU_MASK_ATTN_FUNC_0;
9458
9459                 val = REG_RD(bp, addr);
9460                 val &= ~(0x300);
9461                 REG_WR(bp, addr, val);
9462         } else {
9463                 val = REG_RD(bp, MISC_REG_AEU_GENERAL_MASK);
9464                 val &= ~(MISC_AEU_GENERAL_MASK_REG_AEU_PXP_CLOSE_MASK |
9465                          MISC_AEU_GENERAL_MASK_REG_AEU_NIG_CLOSE_MASK);
9466                 REG_WR(bp, MISC_REG_AEU_GENERAL_MASK, val);
9467         }
9468 }
9469
9470 /* Close gates #2, #3 and #4: */
9471 static void bnx2x_set_234_gates(struct bnx2x *bp, bool close)
9472 {
9473         u32 val;
9474
9475         /* Gates #2 and #4a are closed/opened for "not E1" only */
9476         if (!CHIP_IS_E1(bp)) {
9477                 /* #4 */
9478                 REG_WR(bp, PXP_REG_HST_DISCARD_DOORBELLS, !!close);
9479                 /* #2 */
9480                 REG_WR(bp, PXP_REG_HST_DISCARD_INTERNAL_WRITES, !!close);
9481         }
9482
9483         /* #3 */
9484         if (CHIP_IS_E1x(bp)) {
9485                 /* Prevent interrupts from HC on both ports */
9486                 val = REG_RD(bp, HC_REG_CONFIG_1);
9487                 REG_WR(bp, HC_REG_CONFIG_1,
9488                        (!close) ? (val | HC_CONFIG_1_REG_BLOCK_DISABLE_1) :
9489                        (val & ~(u32)HC_CONFIG_1_REG_BLOCK_DISABLE_1));
9490
9491                 val = REG_RD(bp, HC_REG_CONFIG_0);
9492                 REG_WR(bp, HC_REG_CONFIG_0,
9493                        (!close) ? (val | HC_CONFIG_0_REG_BLOCK_DISABLE_0) :
9494                        (val & ~(u32)HC_CONFIG_0_REG_BLOCK_DISABLE_0));
9495         } else {
9496                 /* Prevent incoming interrupts in IGU */
9497                 val = REG_RD(bp, IGU_REG_BLOCK_CONFIGURATION);
9498
9499                 REG_WR(bp, IGU_REG_BLOCK_CONFIGURATION,
9500                        (!close) ?
9501                        (val | IGU_BLOCK_CONFIGURATION_REG_BLOCK_ENABLE) :
9502                        (val & ~(u32)IGU_BLOCK_CONFIGURATION_REG_BLOCK_ENABLE));
9503         }
9504
9505         DP(NETIF_MSG_HW | NETIF_MSG_IFUP, "%s gates #2, #3 and #4\n",
9506                 close ? "closing" : "opening");
9507         mmiowb();
9508 }
9509
9510 #define SHARED_MF_CLP_MAGIC  0x80000000 /* `magic' bit */
9511
9512 static void bnx2x_clp_reset_prep(struct bnx2x *bp, u32 *magic_val)
9513 {
9514         /* Do some magic... */
9515         u32 val = MF_CFG_RD(bp, shared_mf_config.clp_mb);
9516         *magic_val = val & SHARED_MF_CLP_MAGIC;
9517         MF_CFG_WR(bp, shared_mf_config.clp_mb, val | SHARED_MF_CLP_MAGIC);
9518 }
9519
9520 /**
9521  * bnx2x_clp_reset_done - restore the value of the `magic' bit.
9522  *
9523  * @bp:         driver handle
9524  * @magic_val:  old value of the `magic' bit.
9525  */
9526 static void bnx2x_clp_reset_done(struct bnx2x *bp, u32 magic_val)
9527 {
9528         /* Restore the `magic' bit value... */
9529         u32 val = MF_CFG_RD(bp, shared_mf_config.clp_mb);
9530         MF_CFG_WR(bp, shared_mf_config.clp_mb,
9531                 (val & (~SHARED_MF_CLP_MAGIC)) | magic_val);
9532 }
9533
9534 /**
9535  * bnx2x_reset_mcp_prep - prepare for MCP reset.
9536  *
9537  * @bp:         driver handle
9538  * @magic_val:  old value of 'magic' bit.
9539  *
9540  * Takes care of CLP configurations.
9541  */
9542 static void bnx2x_reset_mcp_prep(struct bnx2x *bp, u32 *magic_val)
9543 {
9544         u32 shmem;
9545         u32 validity_offset;
9546
9547         DP(NETIF_MSG_HW | NETIF_MSG_IFUP, "Starting\n");
9548
9549         /* Set `magic' bit in order to save MF config */
9550         if (!CHIP_IS_E1(bp))
9551                 bnx2x_clp_reset_prep(bp, magic_val);
9552
9553         /* Get shmem offset */
9554         shmem = REG_RD(bp, MISC_REG_SHARED_MEM_ADDR);
9555         validity_offset =
9556                 offsetof(struct shmem_region, validity_map[BP_PORT(bp)]);
9557
9558         /* Clear validity map flags */
9559         if (shmem > 0)
9560                 REG_WR(bp, shmem + validity_offset, 0);
9561 }
9562
9563 #define MCP_TIMEOUT      5000   /* 5 seconds (in ms) */
9564 #define MCP_ONE_TIMEOUT  100    /* 100 ms */
9565
9566 /**
9567  * bnx2x_mcp_wait_one - wait for MCP_ONE_TIMEOUT
9568  *
9569  * @bp: driver handle
9570  */
9571 static void bnx2x_mcp_wait_one(struct bnx2x *bp)
9572 {
9573         /* special handling for emulation and FPGA,
9574            wait 10 times longer */
9575         if (CHIP_REV_IS_SLOW(bp))
9576                 msleep(MCP_ONE_TIMEOUT*10);
9577         else
9578                 msleep(MCP_ONE_TIMEOUT);
9579 }
9580
9581 /*
9582  * initializes bp->common.shmem_base and waits for validity signature to appear
9583  */
9584 static int bnx2x_init_shmem(struct bnx2x *bp)
9585 {
9586         int cnt = 0;
9587         u32 val = 0;
9588
9589         do {
9590                 bp->common.shmem_base = REG_RD(bp, MISC_REG_SHARED_MEM_ADDR);
9591
9592                 /* If we read all 0xFFs, means we are in PCI error state and
9593                  * should bail out to avoid crashes on adapter's FW reads.
9594                  */
9595                 if (bp->common.shmem_base == 0xFFFFFFFF) {
9596                         bp->flags |= NO_MCP_FLAG;
9597                         return -ENODEV;
9598                 }
9599
9600                 if (bp->common.shmem_base) {
9601                         val = SHMEM_RD(bp, validity_map[BP_PORT(bp)]);
9602                         if (val & SHR_MEM_VALIDITY_MB)
9603                                 return 0;
9604                 }
9605
9606                 bnx2x_mcp_wait_one(bp);
9607
9608         } while (cnt++ < (MCP_TIMEOUT / MCP_ONE_TIMEOUT));
9609
9610         BNX2X_ERR("BAD MCP validity signature\n");
9611
9612         return -ENODEV;
9613 }
9614
9615 static int bnx2x_reset_mcp_comp(struct bnx2x *bp, u32 magic_val)
9616 {
9617         int rc = bnx2x_init_shmem(bp);
9618
9619         /* Restore the `magic' bit value */
9620         if (!CHIP_IS_E1(bp))
9621                 bnx2x_clp_reset_done(bp, magic_val);
9622
9623         return rc;
9624 }
9625
9626 static void bnx2x_pxp_prep(struct bnx2x *bp)
9627 {
9628         if (!CHIP_IS_E1(bp)) {
9629                 REG_WR(bp, PXP2_REG_RD_START_INIT, 0);
9630                 REG_WR(bp, PXP2_REG_RQ_RBC_DONE, 0);
9631                 mmiowb();
9632         }
9633 }
9634
9635 /*
9636  * Reset the whole chip except for:
9637  *      - PCIE core
9638  *      - PCI Glue, PSWHST, PXP/PXP2 RF (all controlled by
9639  *              one reset bit)
9640  *      - IGU
9641  *      - MISC (including AEU)
9642  *      - GRC
9643  *      - RBCN, RBCP
9644  */
9645 static void bnx2x_process_kill_chip_reset(struct bnx2x *bp, bool global)
9646 {
9647         u32 not_reset_mask1, reset_mask1, not_reset_mask2, reset_mask2;
9648         u32 global_bits2, stay_reset2;
9649
9650         /*
9651          * Bits that have to be set in reset_mask2 if we want to reset 'global'
9652          * (per chip) blocks.
9653          */
9654         global_bits2 =
9655                 MISC_REGISTERS_RESET_REG_2_RST_MCP_N_RESET_CMN_CPU |
9656                 MISC_REGISTERS_RESET_REG_2_RST_MCP_N_RESET_CMN_CORE;
9657
9658         /* Don't reset the following blocks.
9659          * Important: per port blocks (such as EMAC, BMAC, UMAC) can't be
9660          *            reset, as in 4 port device they might still be owned
9661          *            by the MCP (there is only one leader per path).
9662          */
9663         not_reset_mask1 =
9664                 MISC_REGISTERS_RESET_REG_1_RST_HC |
9665                 MISC_REGISTERS_RESET_REG_1_RST_PXPV |
9666                 MISC_REGISTERS_RESET_REG_1_RST_PXP;
9667
9668         not_reset_mask2 =
9669                 MISC_REGISTERS_RESET_REG_2_RST_PCI_MDIO |
9670                 MISC_REGISTERS_RESET_REG_2_RST_EMAC0_HARD_CORE |
9671                 MISC_REGISTERS_RESET_REG_2_RST_EMAC1_HARD_CORE |
9672                 MISC_REGISTERS_RESET_REG_2_RST_MISC_CORE |
9673                 MISC_REGISTERS_RESET_REG_2_RST_RBCN |
9674                 MISC_REGISTERS_RESET_REG_2_RST_GRC  |
9675                 MISC_REGISTERS_RESET_REG_2_RST_MCP_N_RESET_REG_HARD_CORE |
9676                 MISC_REGISTERS_RESET_REG_2_RST_MCP_N_HARD_CORE_RST_B |
9677                 MISC_REGISTERS_RESET_REG_2_RST_ATC |
9678                 MISC_REGISTERS_RESET_REG_2_PGLC |
9679                 MISC_REGISTERS_RESET_REG_2_RST_BMAC0 |
9680                 MISC_REGISTERS_RESET_REG_2_RST_BMAC1 |
9681                 MISC_REGISTERS_RESET_REG_2_RST_EMAC0 |
9682                 MISC_REGISTERS_RESET_REG_2_RST_EMAC1 |
9683                 MISC_REGISTERS_RESET_REG_2_UMAC0 |
9684                 MISC_REGISTERS_RESET_REG_2_UMAC1;
9685
9686         /*
9687          * Keep the following blocks in reset:
9688          *  - all xxMACs are handled by the bnx2x_link code.
9689          */
9690         stay_reset2 =
9691                 MISC_REGISTERS_RESET_REG_2_XMAC |
9692                 MISC_REGISTERS_RESET_REG_2_XMAC_SOFT;
9693
9694         /* Full reset masks according to the chip */
9695         reset_mask1 = 0xffffffff;
9696
9697         if (CHIP_IS_E1(bp))
9698                 reset_mask2 = 0xffff;
9699         else if (CHIP_IS_E1H(bp))
9700                 reset_mask2 = 0x1ffff;
9701         else if (CHIP_IS_E2(bp))
9702                 reset_mask2 = 0xfffff;
9703         else /* CHIP_IS_E3 */
9704                 reset_mask2 = 0x3ffffff;
9705
9706         /* Don't reset global blocks unless we need to */
9707         if (!global)
9708                 reset_mask2 &= ~global_bits2;
9709
9710         /*
9711          * In case of attention in the QM, we need to reset PXP
9712          * (MISC_REGISTERS_RESET_REG_2_RST_PXP_RQ_RD_WR) before QM
9713          * because otherwise QM reset would release 'close the gates' shortly
9714          * before resetting the PXP, then the PSWRQ would send a write
9715          * request to PGLUE. Then when PXP is reset, PGLUE would try to
9716          * read the payload data from PSWWR, but PSWWR would not
9717          * respond. The write queue in PGLUE would stuck, dmae commands
9718          * would not return. Therefore it's important to reset the second
9719          * reset register (containing the
9720          * MISC_REGISTERS_RESET_REG_2_RST_PXP_RQ_RD_WR bit) before the
9721          * first one (containing the MISC_REGISTERS_RESET_REG_1_RST_QM
9722          * bit).
9723          */
9724         REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR,
9725                reset_mask2 & (~not_reset_mask2));
9726
9727         REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_CLEAR,
9728                reset_mask1 & (~not_reset_mask1));
9729
9730         barrier();
9731         mmiowb();
9732
9733         REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_SET,
9734                reset_mask2 & (~stay_reset2));
9735
9736         barrier();
9737         mmiowb();
9738
9739         REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_SET, reset_mask1);
9740         mmiowb();
9741 }
9742
9743 /**
9744  * bnx2x_er_poll_igu_vq - poll for pending writes bit.
9745  * It should get cleared in no more than 1s.
9746  *
9747  * @bp: driver handle
9748  *
9749  * It should get cleared in no more than 1s. Returns 0 if
9750  * pending writes bit gets cleared.
9751  */
9752 static int bnx2x_er_poll_igu_vq(struct bnx2x *bp)
9753 {
9754         u32 cnt = 1000;
9755         u32 pend_bits = 0;
9756
9757         do {
9758                 pend_bits  = REG_RD(bp, IGU_REG_PENDING_BITS_STATUS);
9759
9760                 if (pend_bits == 0)
9761                         break;
9762
9763                 usleep_range(1000, 2000);
9764         } while (cnt-- > 0);
9765
9766         if (cnt <= 0) {
9767                 BNX2X_ERR("Still pending IGU requests pend_bits=%x!\n",
9768                           pend_bits);
9769                 return -EBUSY;
9770         }
9771
9772         return 0;
9773 }
9774
9775 static int bnx2x_process_kill(struct bnx2x *bp, bool global)
9776 {
9777         int cnt = 1000;
9778         u32 val = 0;
9779         u32 sr_cnt, blk_cnt, port_is_idle_0, port_is_idle_1, pgl_exp_rom2;
9780         u32 tags_63_32 = 0;
9781
9782         /* Empty the Tetris buffer, wait for 1s */
9783         do {
9784                 sr_cnt  = REG_RD(bp, PXP2_REG_RD_SR_CNT);
9785                 blk_cnt = REG_RD(bp, PXP2_REG_RD_BLK_CNT);
9786                 port_is_idle_0 = REG_RD(bp, PXP2_REG_RD_PORT_IS_IDLE_0);
9787                 port_is_idle_1 = REG_RD(bp, PXP2_REG_RD_PORT_IS_IDLE_1);
9788                 pgl_exp_rom2 = REG_RD(bp, PXP2_REG_PGL_EXP_ROM2);
9789                 if (CHIP_IS_E3(bp))
9790                         tags_63_32 = REG_RD(bp, PGLUE_B_REG_TAGS_63_32);
9791
9792                 if ((sr_cnt == 0x7e) && (blk_cnt == 0xa0) &&
9793                     ((port_is_idle_0 & 0x1) == 0x1) &&
9794                     ((port_is_idle_1 & 0x1) == 0x1) &&
9795                     (pgl_exp_rom2 == 0xffffffff) &&
9796                     (!CHIP_IS_E3(bp) || (tags_63_32 == 0xffffffff)))
9797                         break;
9798                 usleep_range(1000, 2000);
9799         } while (cnt-- > 0);
9800
9801         if (cnt <= 0) {
9802                 BNX2X_ERR("Tetris buffer didn't get empty or there are still outstanding read requests after 1s!\n");
9803                 BNX2X_ERR("sr_cnt=0x%08x, blk_cnt=0x%08x, port_is_idle_0=0x%08x, port_is_idle_1=0x%08x, pgl_exp_rom2=0x%08x\n",
9804                           sr_cnt, blk_cnt, port_is_idle_0, port_is_idle_1,
9805                           pgl_exp_rom2);
9806                 return -EAGAIN;
9807         }
9808
9809         barrier();
9810
9811         /* Close gates #2, #3 and #4 */
9812         bnx2x_set_234_gates(bp, true);
9813
9814         /* Poll for IGU VQs for 57712 and newer chips */
9815         if (!CHIP_IS_E1x(bp) && bnx2x_er_poll_igu_vq(bp))
9816                 return -EAGAIN;
9817
9818         /* TBD: Indicate that "process kill" is in progress to MCP */
9819
9820         /* Clear "unprepared" bit */
9821         REG_WR(bp, MISC_REG_UNPREPARED, 0);
9822         barrier();
9823
9824         /* Make sure all is written to the chip before the reset */
9825         mmiowb();
9826
9827         /* Wait for 1ms to empty GLUE and PCI-E core queues,
9828          * PSWHST, GRC and PSWRD Tetris buffer.
9829          */
9830         usleep_range(1000, 2000);
9831
9832         /* Prepare to chip reset: */
9833         /* MCP */
9834         if (global)
9835                 bnx2x_reset_mcp_prep(bp, &val);
9836
9837         /* PXP */
9838         bnx2x_pxp_prep(bp);
9839         barrier();
9840
9841         /* reset the chip */
9842         bnx2x_process_kill_chip_reset(bp, global);
9843         barrier();
9844
9845         /* clear errors in PGB */
9846         if (!CHIP_IS_E1x(bp))
9847                 REG_WR(bp, PGLUE_B_REG_LATCHED_ERRORS_CLR, 0x7f);
9848
9849         /* Recover after reset: */
9850         /* MCP */
9851         if (global && bnx2x_reset_mcp_comp(bp, val))
9852                 return -EAGAIN;
9853
9854         /* TBD: Add resetting the NO_MCP mode DB here */
9855
9856         /* Open the gates #2, #3 and #4 */
9857         bnx2x_set_234_gates(bp, false);
9858
9859         /* TBD: IGU/AEU preparation bring back the AEU/IGU to a
9860          * reset state, re-enable attentions. */
9861
9862         return 0;
9863 }
9864
9865 static int bnx2x_leader_reset(struct bnx2x *bp)
9866 {
9867         int rc = 0;
9868         bool global = bnx2x_reset_is_global(bp);
9869         u32 load_code;
9870
9871         /* if not going to reset MCP - load "fake" driver to reset HW while
9872          * driver is owner of the HW
9873          */
9874         if (!global && !BP_NOMCP(bp)) {
9875                 load_code = bnx2x_fw_command(bp, DRV_MSG_CODE_LOAD_REQ,
9876                                              DRV_MSG_CODE_LOAD_REQ_WITH_LFA);
9877                 if (!load_code) {
9878                         BNX2X_ERR("MCP response failure, aborting\n");
9879                         rc = -EAGAIN;
9880                         goto exit_leader_reset;
9881                 }
9882                 if ((load_code != FW_MSG_CODE_DRV_LOAD_COMMON_CHIP) &&
9883                     (load_code != FW_MSG_CODE_DRV_LOAD_COMMON)) {
9884                         BNX2X_ERR("MCP unexpected resp, aborting\n");
9885                         rc = -EAGAIN;
9886                         goto exit_leader_reset2;
9887                 }
9888                 load_code = bnx2x_fw_command(bp, DRV_MSG_CODE_LOAD_DONE, 0);
9889                 if (!load_code) {
9890                         BNX2X_ERR("MCP response failure, aborting\n");
9891                         rc = -EAGAIN;
9892                         goto exit_leader_reset2;
9893                 }
9894         }
9895
9896         /* Try to recover after the failure */
9897         if (bnx2x_process_kill(bp, global)) {
9898                 BNX2X_ERR("Something bad had happen on engine %d! Aii!\n",
9899                           BP_PATH(bp));
9900                 rc = -EAGAIN;
9901                 goto exit_leader_reset2;
9902         }
9903
9904         /*
9905          * Clear RESET_IN_PROGRES and RESET_GLOBAL bits and update the driver
9906          * state.
9907          */
9908         bnx2x_set_reset_done(bp);
9909         if (global)
9910                 bnx2x_clear_reset_global(bp);
9911
9912 exit_leader_reset2:
9913         /* unload "fake driver" if it was loaded */
9914         if (!global && !BP_NOMCP(bp)) {
9915                 bnx2x_fw_command(bp, DRV_MSG_CODE_UNLOAD_REQ_WOL_MCP, 0);
9916                 bnx2x_fw_command(bp, DRV_MSG_CODE_UNLOAD_DONE, 0);
9917         }
9918 exit_leader_reset:
9919         bp->is_leader = 0;
9920         bnx2x_release_leader_lock(bp);
9921         smp_mb();
9922         return rc;
9923 }
9924
9925 static void bnx2x_recovery_failed(struct bnx2x *bp)
9926 {
9927         netdev_err(bp->dev, "Recovery has failed. Power cycle is needed.\n");
9928
9929         /* Disconnect this device */
9930         netif_device_detach(bp->dev);
9931
9932         /*
9933          * Block ifup for all function on this engine until "process kill"
9934          * or power cycle.
9935          */
9936         bnx2x_set_reset_in_progress(bp);
9937
9938         /* Shut down the power */
9939         bnx2x_set_power_state(bp, PCI_D3hot);
9940
9941         bp->recovery_state = BNX2X_RECOVERY_FAILED;
9942
9943         smp_mb();
9944 }
9945
9946 /*
9947  * Assumption: runs under rtnl lock. This together with the fact
9948  * that it's called only from bnx2x_sp_rtnl() ensure that it
9949  * will never be called when netif_running(bp->dev) is false.
9950  */
9951 static void bnx2x_parity_recover(struct bnx2x *bp)
9952 {
9953         bool global = false;
9954         u32 error_recovered, error_unrecovered;
9955         bool is_parity;
9956
9957         DP(NETIF_MSG_HW, "Handling parity\n");
9958         while (1) {
9959                 switch (bp->recovery_state) {
9960                 case BNX2X_RECOVERY_INIT:
9961                         DP(NETIF_MSG_HW, "State is BNX2X_RECOVERY_INIT\n");
9962                         is_parity = bnx2x_chk_parity_attn(bp, &global, false);
9963                         WARN_ON(!is_parity);
9964
9965                         /* Try to get a LEADER_LOCK HW lock */
9966                         if (bnx2x_trylock_leader_lock(bp)) {
9967                                 bnx2x_set_reset_in_progress(bp);
9968                                 /*
9969                                  * Check if there is a global attention and if
9970                                  * there was a global attention, set the global
9971                                  * reset bit.
9972                                  */
9973
9974                                 if (global)
9975                                         bnx2x_set_reset_global(bp);
9976
9977                                 bp->is_leader = 1;
9978                         }
9979
9980                         /* Stop the driver */
9981                         /* If interface has been removed - break */
9982                         if (bnx2x_nic_unload(bp, UNLOAD_RECOVERY, false))
9983                                 return;
9984
9985                         bp->recovery_state = BNX2X_RECOVERY_WAIT;
9986
9987                         /* Ensure "is_leader", MCP command sequence and
9988                          * "recovery_state" update values are seen on other
9989                          * CPUs.
9990                          */
9991                         smp_mb();
9992                         break;
9993
9994                 case BNX2X_RECOVERY_WAIT:
9995                         DP(NETIF_MSG_HW, "State is BNX2X_RECOVERY_WAIT\n");
9996                         if (bp->is_leader) {
9997                                 int other_engine = BP_PATH(bp) ? 0 : 1;
9998                                 bool other_load_status =
9999                                         bnx2x_get_load_status(bp, other_engine);
10000                                 bool load_status =
10001                                         bnx2x_get_load_status(bp, BP_PATH(bp));
10002                                 global = bnx2x_reset_is_global(bp);
10003
10004                                 /*
10005                                  * In case of a parity in a global block, let
10006                                  * the first leader that performs a
10007                                  * leader_reset() reset the global blocks in
10008                                  * order to clear global attentions. Otherwise
10009                                  * the gates will remain closed for that
10010                                  * engine.
10011                                  */
10012                                 if (load_status ||
10013                                     (global && other_load_status)) {
10014                                         /* Wait until all other functions get
10015                                          * down.
10016                                          */
10017                                         schedule_delayed_work(&bp->sp_rtnl_task,
10018                                                                 HZ/10);
10019                                         return;
10020                                 } else {
10021                                         /* If all other functions got down -
10022                                          * try to bring the chip back to
10023                                          * normal. In any case it's an exit
10024                                          * point for a leader.
10025                                          */
10026                                         if (bnx2x_leader_reset(bp)) {
10027                                                 bnx2x_recovery_failed(bp);
10028                                                 return;
10029                                         }
10030
10031                                         /* If we are here, means that the
10032                                          * leader has succeeded and doesn't
10033                                          * want to be a leader any more. Try
10034                                          * to continue as a none-leader.
10035                                          */
10036                                         break;
10037                                 }
10038                         } else { /* non-leader */
10039                                 if (!bnx2x_reset_is_done(bp, BP_PATH(bp))) {
10040                                         /* Try to get a LEADER_LOCK HW lock as
10041                                          * long as a former leader may have
10042                                          * been unloaded by the user or
10043                                          * released a leadership by another
10044                                          * reason.
10045                                          */
10046                                         if (bnx2x_trylock_leader_lock(bp)) {
10047                                                 /* I'm a leader now! Restart a
10048                                                  * switch case.
10049                                                  */
10050                                                 bp->is_leader = 1;
10051                                                 break;
10052                                         }
10053
10054                                         schedule_delayed_work(&bp->sp_rtnl_task,
10055                                                                 HZ/10);
10056                                         return;
10057
10058                                 } else {
10059                                         /*
10060                                          * If there was a global attention, wait
10061                                          * for it to be cleared.
10062                                          */
10063                                         if (bnx2x_reset_is_global(bp)) {
10064                                                 schedule_delayed_work(
10065                                                         &bp->sp_rtnl_task,
10066                                                         HZ/10);
10067                                                 return;
10068                                         }
10069
10070                                         error_recovered =
10071                                           bp->eth_stats.recoverable_error;
10072                                         error_unrecovered =
10073                                           bp->eth_stats.unrecoverable_error;
10074                                         bp->recovery_state =
10075                                                 BNX2X_RECOVERY_NIC_LOADING;
10076                                         if (bnx2x_nic_load(bp, LOAD_NORMAL)) {
10077                                                 error_unrecovered++;
10078                                                 netdev_err(bp->dev,
10079                                                            "Recovery failed. Power cycle needed\n");
10080                                                 /* Disconnect this device */
10081                                                 netif_device_detach(bp->dev);
10082                                                 /* Shut down the power */
10083                                                 bnx2x_set_power_state(
10084                                                         bp, PCI_D3hot);
10085                                                 smp_mb();
10086                                         } else {
10087                                                 bp->recovery_state =
10088                                                         BNX2X_RECOVERY_DONE;
10089                                                 error_recovered++;
10090                                                 smp_mb();
10091                                         }
10092                                         bp->eth_stats.recoverable_error =
10093                                                 error_recovered;
10094                                         bp->eth_stats.unrecoverable_error =
10095                                                 error_unrecovered;
10096
10097                                         return;
10098                                 }
10099                         }
10100                 default:
10101                         return;
10102                 }
10103         }
10104 }
10105
10106 static int bnx2x_udp_port_update(struct bnx2x *bp)
10107 {
10108         struct bnx2x_func_switch_update_params *switch_update_params;
10109         struct bnx2x_func_state_params func_params = {NULL};
10110         struct bnx2x_udp_tunnel *udp_tunnel;
10111         u16 vxlan_port = 0, geneve_port = 0;
10112         int rc;
10113
10114         switch_update_params = &func_params.params.switch_update;
10115
10116         /* Prepare parameters for function state transitions */
10117         __set_bit(RAMROD_COMP_WAIT, &func_params.ramrod_flags);
10118         __set_bit(RAMROD_RETRY, &func_params.ramrod_flags);
10119
10120         func_params.f_obj = &bp->func_obj;
10121         func_params.cmd = BNX2X_F_CMD_SWITCH_UPDATE;
10122
10123         /* Function parameters */
10124         __set_bit(BNX2X_F_UPDATE_TUNNEL_CFG_CHNG,
10125                   &switch_update_params->changes);
10126
10127         if (bp->udp_tunnel_ports[BNX2X_UDP_PORT_GENEVE].count) {
10128                 udp_tunnel = &bp->udp_tunnel_ports[BNX2X_UDP_PORT_GENEVE];
10129                 geneve_port = udp_tunnel->dst_port;
10130                 switch_update_params->geneve_dst_port = geneve_port;
10131         }
10132
10133         if (bp->udp_tunnel_ports[BNX2X_UDP_PORT_VXLAN].count) {
10134                 udp_tunnel = &bp->udp_tunnel_ports[BNX2X_UDP_PORT_VXLAN];
10135                 vxlan_port = udp_tunnel->dst_port;
10136                 switch_update_params->vxlan_dst_port = vxlan_port;
10137         }
10138
10139         /* Re-enable inner-rss for the offloaded UDP tunnels */
10140         __set_bit(BNX2X_F_UPDATE_TUNNEL_INNER_RSS,
10141                   &switch_update_params->changes);
10142
10143         rc = bnx2x_func_state_change(bp, &func_params);
10144         if (rc)
10145                 BNX2X_ERR("failed to set UDP dst port to %04x %04x (rc = 0x%x)\n",
10146                           vxlan_port, geneve_port, rc);
10147         else
10148                 DP(BNX2X_MSG_SP,
10149                    "Configured UDP ports: Vxlan [%04x] Geneve [%04x]\n",
10150                    vxlan_port, geneve_port);
10151
10152         return rc;
10153 }
10154
10155 static void __bnx2x_add_udp_port(struct bnx2x *bp, u16 port,
10156                                  enum bnx2x_udp_port_type type)
10157 {
10158         struct bnx2x_udp_tunnel *udp_port = &bp->udp_tunnel_ports[type];
10159
10160         if (!netif_running(bp->dev) || !IS_PF(bp) || CHIP_IS_E1x(bp))
10161                 return;
10162
10163         if (udp_port->count && udp_port->dst_port == port) {
10164                 udp_port->count++;
10165                 return;
10166         }
10167
10168         if (udp_port->count) {
10169                 DP(BNX2X_MSG_SP,
10170                    "UDP tunnel [%d] -  destination port limit reached\n",
10171                    type);
10172                 return;
10173         }
10174
10175         udp_port->dst_port = port;
10176         udp_port->count = 1;
10177         bnx2x_schedule_sp_rtnl(bp, BNX2X_SP_RTNL_CHANGE_UDP_PORT, 0);
10178 }
10179
10180 static void __bnx2x_del_udp_port(struct bnx2x *bp, u16 port,
10181                                  enum bnx2x_udp_port_type type)
10182 {
10183         struct bnx2x_udp_tunnel *udp_port = &bp->udp_tunnel_ports[type];
10184
10185         if (!IS_PF(bp) || CHIP_IS_E1x(bp))
10186                 return;
10187
10188         if (!udp_port->count || udp_port->dst_port != port) {
10189                 DP(BNX2X_MSG_SP, "Invalid UDP tunnel [%d] port\n",
10190                    type);
10191                 return;
10192         }
10193
10194         /* Remove reference, and make certain it's no longer in use */
10195         udp_port->count--;
10196         if (udp_port->count)
10197                 return;
10198         udp_port->dst_port = 0;
10199
10200         if (netif_running(bp->dev))
10201                 bnx2x_schedule_sp_rtnl(bp, BNX2X_SP_RTNL_CHANGE_UDP_PORT, 0);
10202         else
10203                 DP(BNX2X_MSG_SP, "Deleted UDP tunnel [%d] port %d\n",
10204                    type, port);
10205 }
10206
10207 static void bnx2x_udp_tunnel_add(struct net_device *netdev,
10208                                  struct udp_tunnel_info *ti)
10209 {
10210         struct bnx2x *bp = netdev_priv(netdev);
10211         u16 t_port = ntohs(ti->port);
10212
10213         switch (ti->type) {
10214         case UDP_TUNNEL_TYPE_VXLAN:
10215                 __bnx2x_add_udp_port(bp, t_port, BNX2X_UDP_PORT_VXLAN);
10216                 break;
10217         case UDP_TUNNEL_TYPE_GENEVE:
10218                 __bnx2x_add_udp_port(bp, t_port, BNX2X_UDP_PORT_GENEVE);
10219                 break;
10220         default:
10221                 break;
10222         }
10223 }
10224
10225 static void bnx2x_udp_tunnel_del(struct net_device *netdev,
10226                                  struct udp_tunnel_info *ti)
10227 {
10228         struct bnx2x *bp = netdev_priv(netdev);
10229         u16 t_port = ntohs(ti->port);
10230
10231         switch (ti->type) {
10232         case UDP_TUNNEL_TYPE_VXLAN:
10233                 __bnx2x_del_udp_port(bp, t_port, BNX2X_UDP_PORT_VXLAN);
10234                 break;
10235         case UDP_TUNNEL_TYPE_GENEVE:
10236                 __bnx2x_del_udp_port(bp, t_port, BNX2X_UDP_PORT_GENEVE);
10237                 break;
10238         default:
10239                 break;
10240         }
10241 }
10242
10243 static int bnx2x_close(struct net_device *dev);
10244
10245 /* bnx2x_nic_unload() flushes the bnx2x_wq, thus reset task is
10246  * scheduled on a general queue in order to prevent a dead lock.
10247  */
10248 static void bnx2x_sp_rtnl_task(struct work_struct *work)
10249 {
10250         struct bnx2x *bp = container_of(work, struct bnx2x, sp_rtnl_task.work);
10251
10252         rtnl_lock();
10253
10254         if (!netif_running(bp->dev)) {
10255                 rtnl_unlock();
10256                 return;
10257         }
10258
10259         if (unlikely(bp->recovery_state != BNX2X_RECOVERY_DONE)) {
10260 #ifdef BNX2X_STOP_ON_ERROR
10261                 BNX2X_ERR("recovery flow called but STOP_ON_ERROR defined so reset not done to allow debug dump,\n"
10262                           "you will need to reboot when done\n");
10263                 goto sp_rtnl_not_reset;
10264 #endif
10265                 /*
10266                  * Clear all pending SP commands as we are going to reset the
10267                  * function anyway.
10268                  */
10269                 bp->sp_rtnl_state = 0;
10270                 smp_mb();
10271
10272                 bnx2x_parity_recover(bp);
10273
10274                 rtnl_unlock();
10275                 return;
10276         }
10277
10278         if (test_and_clear_bit(BNX2X_SP_RTNL_TX_TIMEOUT, &bp->sp_rtnl_state)) {
10279 #ifdef BNX2X_STOP_ON_ERROR
10280                 BNX2X_ERR("recovery flow called but STOP_ON_ERROR defined so reset not done to allow debug dump,\n"
10281                           "you will need to reboot when done\n");
10282                 goto sp_rtnl_not_reset;
10283 #endif
10284
10285                 /*
10286                  * Clear all pending SP commands as we are going to reset the
10287                  * function anyway.
10288                  */
10289                 bp->sp_rtnl_state = 0;
10290                 smp_mb();
10291
10292                 /* Immediately indicate link as down */
10293                 bp->link_vars.link_up = 0;
10294                 bp->force_link_down = true;
10295                 netif_carrier_off(bp->dev);
10296                 BNX2X_ERR("Indicating link is down due to Tx-timeout\n");
10297
10298                 bnx2x_nic_unload(bp, UNLOAD_NORMAL, true);
10299                 /* When ret value shows failure of allocation failure,
10300                  * the nic is rebooted again. If open still fails, a error
10301                  * message to notify the user.
10302                  */
10303                 if (bnx2x_nic_load(bp, LOAD_NORMAL) == -ENOMEM) {
10304                         bnx2x_nic_unload(bp, UNLOAD_NORMAL, true);
10305                         if (bnx2x_nic_load(bp, LOAD_NORMAL))
10306                                 BNX2X_ERR("Open the NIC fails again!\n");
10307                 }
10308                 rtnl_unlock();
10309                 return;
10310         }
10311 #ifdef BNX2X_STOP_ON_ERROR
10312 sp_rtnl_not_reset:
10313 #endif
10314         if (test_and_clear_bit(BNX2X_SP_RTNL_SETUP_TC, &bp->sp_rtnl_state))
10315                 bnx2x_setup_tc(bp->dev, bp->dcbx_port_params.ets.num_of_cos);
10316         if (test_and_clear_bit(BNX2X_SP_RTNL_AFEX_F_UPDATE, &bp->sp_rtnl_state))
10317                 bnx2x_after_function_update(bp);
10318         /*
10319          * in case of fan failure we need to reset id if the "stop on error"
10320          * debug flag is set, since we trying to prevent permanent overheating
10321          * damage
10322          */
10323         if (test_and_clear_bit(BNX2X_SP_RTNL_FAN_FAILURE, &bp->sp_rtnl_state)) {
10324                 DP(NETIF_MSG_HW, "fan failure detected. Unloading driver\n");
10325                 netif_device_detach(bp->dev);
10326                 bnx2x_close(bp->dev);
10327                 rtnl_unlock();
10328                 return;
10329         }
10330
10331         if (test_and_clear_bit(BNX2X_SP_RTNL_VFPF_MCAST, &bp->sp_rtnl_state)) {
10332                 DP(BNX2X_MSG_SP,
10333                    "sending set mcast vf pf channel message from rtnl sp-task\n");
10334                 bnx2x_vfpf_set_mcast(bp->dev);
10335         }
10336         if (test_and_clear_bit(BNX2X_SP_RTNL_VFPF_CHANNEL_DOWN,
10337                                &bp->sp_rtnl_state)){
10338                 if (netif_carrier_ok(bp->dev)) {
10339                         bnx2x_tx_disable(bp);
10340                         BNX2X_ERR("PF indicated channel is not servicable anymore. This means this VF device is no longer operational\n");
10341                 }
10342         }
10343
10344         if (test_and_clear_bit(BNX2X_SP_RTNL_RX_MODE, &bp->sp_rtnl_state)) {
10345                 DP(BNX2X_MSG_SP, "Handling Rx Mode setting\n");
10346                 bnx2x_set_rx_mode_inner(bp);
10347         }
10348
10349         if (test_and_clear_bit(BNX2X_SP_RTNL_HYPERVISOR_VLAN,
10350                                &bp->sp_rtnl_state))
10351                 bnx2x_pf_set_vfs_vlan(bp);
10352
10353         if (test_and_clear_bit(BNX2X_SP_RTNL_TX_STOP, &bp->sp_rtnl_state)) {
10354                 bnx2x_dcbx_stop_hw_tx(bp);
10355                 bnx2x_dcbx_resume_hw_tx(bp);
10356         }
10357
10358         if (test_and_clear_bit(BNX2X_SP_RTNL_GET_DRV_VERSION,
10359                                &bp->sp_rtnl_state))
10360                 bnx2x_update_mng_version(bp);
10361
10362         if (test_and_clear_bit(BNX2X_SP_RTNL_CHANGE_UDP_PORT,
10363                                &bp->sp_rtnl_state)) {
10364                 if (bnx2x_udp_port_update(bp)) {
10365                         /* On error, forget configuration */
10366                         memset(bp->udp_tunnel_ports, 0,
10367                                sizeof(struct bnx2x_udp_tunnel) *
10368                                BNX2X_UDP_PORT_MAX);
10369                 } else {
10370                         /* Since we don't store additional port information,
10371                          * if no ports are configured for any feature ask for
10372                          * information about currently configured ports.
10373                          */
10374                         if (!bp->udp_tunnel_ports[BNX2X_UDP_PORT_VXLAN].count &&
10375                             !bp->udp_tunnel_ports[BNX2X_UDP_PORT_GENEVE].count)
10376                                 udp_tunnel_get_rx_info(bp->dev);
10377                 }
10378         }
10379
10380         /* work which needs rtnl lock not-taken (as it takes the lock itself and
10381          * can be called from other contexts as well)
10382          */
10383         rtnl_unlock();
10384
10385         /* enable SR-IOV if applicable */
10386         if (IS_SRIOV(bp) && test_and_clear_bit(BNX2X_SP_RTNL_ENABLE_SRIOV,
10387                                                &bp->sp_rtnl_state)) {
10388                 bnx2x_disable_sriov(bp);
10389                 bnx2x_enable_sriov(bp);
10390         }
10391 }
10392
10393 static void bnx2x_period_task(struct work_struct *work)
10394 {
10395         struct bnx2x *bp = container_of(work, struct bnx2x, period_task.work);
10396
10397         if (!netif_running(bp->dev))
10398                 goto period_task_exit;
10399
10400         if (CHIP_REV_IS_SLOW(bp)) {
10401                 BNX2X_ERR("period task called on emulation, ignoring\n");
10402                 goto period_task_exit;
10403         }
10404
10405         bnx2x_acquire_phy_lock(bp);
10406         /*
10407          * The barrier is needed to ensure the ordering between the writing to
10408          * the bp->port.pmf in the bnx2x_nic_load() or bnx2x_pmf_update() and
10409          * the reading here.
10410          */
10411         smp_mb();
10412         if (bp->port.pmf) {
10413                 bnx2x_period_func(&bp->link_params, &bp->link_vars);
10414
10415                 /* Re-queue task in 1 sec */
10416                 queue_delayed_work(bnx2x_wq, &bp->period_task, 1*HZ);
10417         }
10418
10419         bnx2x_release_phy_lock(bp);
10420 period_task_exit:
10421         return;
10422 }
10423
10424 /*
10425  * Init service functions
10426  */
10427
10428 static u32 bnx2x_get_pretend_reg(struct bnx2x *bp)
10429 {
10430         u32 base = PXP2_REG_PGL_PRETEND_FUNC_F0;
10431         u32 stride = PXP2_REG_PGL_PRETEND_FUNC_F1 - base;
10432         return base + (BP_ABS_FUNC(bp)) * stride;
10433 }
10434
10435 static bool bnx2x_prev_unload_close_umac(struct bnx2x *bp,
10436                                          u8 port, u32 reset_reg,
10437                                          struct bnx2x_mac_vals *vals)
10438 {
10439         u32 mask = MISC_REGISTERS_RESET_REG_2_UMAC0 << port;
10440         u32 base_addr;
10441
10442         if (!(mask & reset_reg))
10443                 return false;
10444
10445         BNX2X_DEV_INFO("Disable umac Rx %02x\n", port);
10446         base_addr = port ? GRCBASE_UMAC1 : GRCBASE_UMAC0;
10447         vals->umac_addr[port] = base_addr + UMAC_REG_COMMAND_CONFIG;
10448         vals->umac_val[port] = REG_RD(bp, vals->umac_addr[port]);
10449         REG_WR(bp, vals->umac_addr[port], 0);
10450
10451         return true;
10452 }
10453
10454 static void bnx2x_prev_unload_close_mac(struct bnx2x *bp,
10455                                         struct bnx2x_mac_vals *vals)
10456 {
10457         u32 val, base_addr, offset, mask, reset_reg;
10458         bool mac_stopped = false;
10459         u8 port = BP_PORT(bp);
10460
10461         /* reset addresses as they also mark which values were changed */
10462         memset(vals, 0, sizeof(*vals));
10463
10464         reset_reg = REG_RD(bp, MISC_REG_RESET_REG_2);
10465
10466         if (!CHIP_IS_E3(bp)) {
10467                 val = REG_RD(bp, NIG_REG_BMAC0_REGS_OUT_EN + port * 4);
10468                 mask = MISC_REGISTERS_RESET_REG_2_RST_BMAC0 << port;
10469                 if ((mask & reset_reg) && val) {
10470                         u32 wb_data[2];
10471                         BNX2X_DEV_INFO("Disable bmac Rx\n");
10472                         base_addr = BP_PORT(bp) ? NIG_REG_INGRESS_BMAC1_MEM
10473                                                 : NIG_REG_INGRESS_BMAC0_MEM;
10474                         offset = CHIP_IS_E2(bp) ? BIGMAC2_REGISTER_BMAC_CONTROL
10475                                                 : BIGMAC_REGISTER_BMAC_CONTROL;
10476
10477                         /*
10478                          * use rd/wr since we cannot use dmae. This is safe
10479                          * since MCP won't access the bus due to the request
10480                          * to unload, and no function on the path can be
10481                          * loaded at this time.
10482                          */
10483                         wb_data[0] = REG_RD(bp, base_addr + offset);
10484                         wb_data[1] = REG_RD(bp, base_addr + offset + 0x4);
10485                         vals->bmac_addr = base_addr + offset;
10486                         vals->bmac_val[0] = wb_data[0];
10487                         vals->bmac_val[1] = wb_data[1];
10488                         wb_data[0] &= ~BMAC_CONTROL_RX_ENABLE;
10489                         REG_WR(bp, vals->bmac_addr, wb_data[0]);
10490                         REG_WR(bp, vals->bmac_addr + 0x4, wb_data[1]);
10491                 }
10492                 BNX2X_DEV_INFO("Disable emac Rx\n");
10493                 vals->emac_addr = NIG_REG_NIG_EMAC0_EN + BP_PORT(bp)*4;
10494                 vals->emac_val = REG_RD(bp, vals->emac_addr);
10495                 REG_WR(bp, vals->emac_addr, 0);
10496                 mac_stopped = true;
10497         } else {
10498                 if (reset_reg & MISC_REGISTERS_RESET_REG_2_XMAC) {
10499                         BNX2X_DEV_INFO("Disable xmac Rx\n");
10500                         base_addr = BP_PORT(bp) ? GRCBASE_XMAC1 : GRCBASE_XMAC0;
10501                         val = REG_RD(bp, base_addr + XMAC_REG_PFC_CTRL_HI);
10502                         REG_WR(bp, base_addr + XMAC_REG_PFC_CTRL_HI,
10503                                val & ~(1 << 1));
10504                         REG_WR(bp, base_addr + XMAC_REG_PFC_CTRL_HI,
10505                                val | (1 << 1));
10506                         vals->xmac_addr = base_addr + XMAC_REG_CTRL;
10507                         vals->xmac_val = REG_RD(bp, vals->xmac_addr);
10508                         REG_WR(bp, vals->xmac_addr, 0);
10509                         mac_stopped = true;
10510                 }
10511
10512                 mac_stopped |= bnx2x_prev_unload_close_umac(bp, 0,
10513                                                             reset_reg, vals);
10514                 mac_stopped |= bnx2x_prev_unload_close_umac(bp, 1,
10515                                                             reset_reg, vals);
10516         }
10517
10518         if (mac_stopped)
10519                 msleep(20);
10520 }
10521
10522 #define BNX2X_PREV_UNDI_PROD_ADDR(p) (BAR_TSTRORM_INTMEM + 0x1508 + ((p) << 4))
10523 #define BNX2X_PREV_UNDI_PROD_ADDR_H(f) (BAR_TSTRORM_INTMEM + \
10524                                         0x1848 + ((f) << 4))
10525 #define BNX2X_PREV_UNDI_RCQ(val)        ((val) & 0xffff)
10526 #define BNX2X_PREV_UNDI_BD(val)         ((val) >> 16 & 0xffff)
10527 #define BNX2X_PREV_UNDI_PROD(rcq, bd)   ((bd) << 16 | (rcq))
10528
10529 #define BCM_5710_UNDI_FW_MF_MAJOR       (0x07)
10530 #define BCM_5710_UNDI_FW_MF_MINOR       (0x08)
10531 #define BCM_5710_UNDI_FW_MF_VERS        (0x05)
10532
10533 static bool bnx2x_prev_is_after_undi(struct bnx2x *bp)
10534 {
10535         /* UNDI marks its presence in DORQ -
10536          * it initializes CID offset for normal bell to 0x7
10537          */
10538         if (!(REG_RD(bp, MISC_REG_RESET_REG_1) &
10539             MISC_REGISTERS_RESET_REG_1_RST_DORQ))
10540                 return false;
10541
10542         if (REG_RD(bp, DORQ_REG_NORM_CID_OFST) == 0x7) {
10543                 BNX2X_DEV_INFO("UNDI previously loaded\n");
10544                 return true;
10545         }
10546
10547         return false;
10548 }
10549
10550 static void bnx2x_prev_unload_undi_inc(struct bnx2x *bp, u8 inc)
10551 {
10552         u16 rcq, bd;
10553         u32 addr, tmp_reg;
10554
10555         if (BP_FUNC(bp) < 2)
10556                 addr = BNX2X_PREV_UNDI_PROD_ADDR(BP_PORT(bp));
10557         else
10558                 addr = BNX2X_PREV_UNDI_PROD_ADDR_H(BP_FUNC(bp) - 2);
10559
10560         tmp_reg = REG_RD(bp, addr);
10561         rcq = BNX2X_PREV_UNDI_RCQ(tmp_reg) + inc;
10562         bd = BNX2X_PREV_UNDI_BD(tmp_reg) + inc;
10563
10564         tmp_reg = BNX2X_PREV_UNDI_PROD(rcq, bd);
10565         REG_WR(bp, addr, tmp_reg);
10566
10567         BNX2X_DEV_INFO("UNDI producer [%d/%d][%08x] rings bd -> 0x%04x, rcq -> 0x%04x\n",
10568                        BP_PORT(bp), BP_FUNC(bp), addr, bd, rcq);
10569 }
10570
10571 static int bnx2x_prev_mcp_done(struct bnx2x *bp)
10572 {
10573         u32 rc = bnx2x_fw_command(bp, DRV_MSG_CODE_UNLOAD_DONE,
10574                                   DRV_MSG_CODE_UNLOAD_SKIP_LINK_RESET);
10575         if (!rc) {
10576                 BNX2X_ERR("MCP response failure, aborting\n");
10577                 return -EBUSY;
10578         }
10579
10580         return 0;
10581 }
10582
10583 static struct bnx2x_prev_path_list *
10584                 bnx2x_prev_path_get_entry(struct bnx2x *bp)
10585 {
10586         struct bnx2x_prev_path_list *tmp_list;
10587
10588         list_for_each_entry(tmp_list, &bnx2x_prev_list, list)
10589                 if (PCI_SLOT(bp->pdev->devfn) == tmp_list->slot &&
10590                     bp->pdev->bus->number == tmp_list->bus &&
10591                     BP_PATH(bp) == tmp_list->path)
10592                         return tmp_list;
10593
10594         return NULL;
10595 }
10596
10597 static int bnx2x_prev_path_mark_eeh(struct bnx2x *bp)
10598 {
10599         struct bnx2x_prev_path_list *tmp_list;
10600         int rc;
10601
10602         rc = down_interruptible(&bnx2x_prev_sem);
10603         if (rc) {
10604                 BNX2X_ERR("Received %d when tried to take lock\n", rc);
10605                 return rc;
10606         }
10607
10608         tmp_list = bnx2x_prev_path_get_entry(bp);
10609         if (tmp_list) {
10610                 tmp_list->aer = 1;
10611                 rc = 0;
10612         } else {
10613                 BNX2X_ERR("path %d: Entry does not exist for eeh; Flow occurs before initial insmod is over ?\n",
10614                           BP_PATH(bp));
10615         }
10616
10617         up(&bnx2x_prev_sem);
10618
10619         return rc;
10620 }
10621
10622 static bool bnx2x_prev_is_path_marked(struct bnx2x *bp)
10623 {
10624         struct bnx2x_prev_path_list *tmp_list;
10625         bool rc = false;
10626
10627         if (down_trylock(&bnx2x_prev_sem))
10628                 return false;
10629
10630         tmp_list = bnx2x_prev_path_get_entry(bp);
10631         if (tmp_list) {
10632                 if (tmp_list->aer) {
10633                         DP(NETIF_MSG_HW, "Path %d was marked by AER\n",
10634                            BP_PATH(bp));
10635                 } else {
10636                         rc = true;
10637                         BNX2X_DEV_INFO("Path %d was already cleaned from previous drivers\n",
10638                                        BP_PATH(bp));
10639                 }
10640         }
10641
10642         up(&bnx2x_prev_sem);
10643
10644         return rc;
10645 }
10646
10647 bool bnx2x_port_after_undi(struct bnx2x *bp)
10648 {
10649         struct bnx2x_prev_path_list *entry;
10650         bool val;
10651
10652         down(&bnx2x_prev_sem);
10653
10654         entry = bnx2x_prev_path_get_entry(bp);
10655         val = !!(entry && (entry->undi & (1 << BP_PORT(bp))));
10656
10657         up(&bnx2x_prev_sem);
10658
10659         return val;
10660 }
10661
10662 static int bnx2x_prev_mark_path(struct bnx2x *bp, bool after_undi)
10663 {
10664         struct bnx2x_prev_path_list *tmp_list;
10665         int rc;
10666
10667         rc = down_interruptible(&bnx2x_prev_sem);
10668         if (rc) {
10669                 BNX2X_ERR("Received %d when tried to take lock\n", rc);
10670                 return rc;
10671         }
10672
10673         /* Check whether the entry for this path already exists */
10674         tmp_list = bnx2x_prev_path_get_entry(bp);
10675         if (tmp_list) {
10676                 if (!tmp_list->aer) {
10677                         BNX2X_ERR("Re-Marking the path.\n");
10678                 } else {
10679                         DP(NETIF_MSG_HW, "Removing AER indication from path %d\n",
10680                            BP_PATH(bp));
10681                         tmp_list->aer = 0;
10682                 }
10683                 up(&bnx2x_prev_sem);
10684                 return 0;
10685         }
10686         up(&bnx2x_prev_sem);
10687
10688         /* Create an entry for this path and add it */
10689         tmp_list = kmalloc(sizeof(struct bnx2x_prev_path_list), GFP_KERNEL);
10690         if (!tmp_list) {
10691                 BNX2X_ERR("Failed to allocate 'bnx2x_prev_path_list'\n");
10692                 return -ENOMEM;
10693         }
10694
10695         tmp_list->bus = bp->pdev->bus->number;
10696         tmp_list->slot = PCI_SLOT(bp->pdev->devfn);
10697         tmp_list->path = BP_PATH(bp);
10698         tmp_list->aer = 0;
10699         tmp_list->undi = after_undi ? (1 << BP_PORT(bp)) : 0;
10700
10701         rc = down_interruptible(&bnx2x_prev_sem);
10702         if (rc) {
10703                 BNX2X_ERR("Received %d when tried to take lock\n", rc);
10704                 kfree(tmp_list);
10705         } else {
10706                 DP(NETIF_MSG_HW, "Marked path [%d] - finished previous unload\n",
10707                    BP_PATH(bp));
10708                 list_add(&tmp_list->list, &bnx2x_prev_list);
10709                 up(&bnx2x_prev_sem);
10710         }
10711
10712         return rc;
10713 }
10714
10715 static int bnx2x_do_flr(struct bnx2x *bp)
10716 {
10717         struct pci_dev *dev = bp->pdev;
10718
10719         if (CHIP_IS_E1x(bp)) {
10720                 BNX2X_DEV_INFO("FLR not supported in E1/E1H\n");
10721                 return -EINVAL;
10722         }
10723
10724         /* only bootcode REQ_BC_VER_4_INITIATE_FLR and onwards support flr */
10725         if (bp->common.bc_ver < REQ_BC_VER_4_INITIATE_FLR) {
10726                 BNX2X_ERR("FLR not supported by BC_VER: 0x%x\n",
10727                           bp->common.bc_ver);
10728                 return -EINVAL;
10729         }
10730
10731         if (!pci_wait_for_pending_transaction(dev))
10732                 dev_err(&dev->dev, "transaction is not cleared; proceeding with reset anyway\n");
10733
10734         BNX2X_DEV_INFO("Initiating FLR\n");
10735         bnx2x_fw_command(bp, DRV_MSG_CODE_INITIATE_FLR, 0);
10736
10737         return 0;
10738 }
10739
10740 static int bnx2x_prev_unload_uncommon(struct bnx2x *bp)
10741 {
10742         int rc;
10743
10744         BNX2X_DEV_INFO("Uncommon unload Flow\n");
10745
10746         /* Test if previous unload process was already finished for this path */
10747         if (bnx2x_prev_is_path_marked(bp))
10748                 return bnx2x_prev_mcp_done(bp);
10749
10750         BNX2X_DEV_INFO("Path is unmarked\n");
10751
10752         /* Cannot proceed with FLR if UNDI is loaded, since FW does not match */
10753         if (bnx2x_prev_is_after_undi(bp))
10754                 goto out;
10755
10756         /* If function has FLR capabilities, and existing FW version matches
10757          * the one required, then FLR will be sufficient to clean any residue
10758          * left by previous driver
10759          */
10760         rc = bnx2x_compare_fw_ver(bp, FW_MSG_CODE_DRV_LOAD_FUNCTION, false);
10761
10762         if (!rc) {
10763                 /* fw version is good */
10764                 BNX2X_DEV_INFO("FW version matches our own. Attempting FLR\n");
10765                 rc = bnx2x_do_flr(bp);
10766         }
10767
10768         if (!rc) {
10769                 /* FLR was performed */
10770                 BNX2X_DEV_INFO("FLR successful\n");
10771                 return 0;
10772         }
10773
10774         BNX2X_DEV_INFO("Could not FLR\n");
10775
10776 out:
10777         /* Close the MCP request, return failure*/
10778         rc = bnx2x_prev_mcp_done(bp);
10779         if (!rc)
10780                 rc = BNX2X_PREV_WAIT_NEEDED;
10781
10782         return rc;
10783 }
10784
10785 static int bnx2x_prev_unload_common(struct bnx2x *bp)
10786 {
10787         u32 reset_reg, tmp_reg = 0, rc;
10788         bool prev_undi = false;
10789         struct bnx2x_mac_vals mac_vals;
10790
10791         /* It is possible a previous function received 'common' answer,
10792          * but hasn't loaded yet, therefore creating a scenario of
10793          * multiple functions receiving 'common' on the same path.
10794          */
10795         BNX2X_DEV_INFO("Common unload Flow\n");
10796
10797         memset(&mac_vals, 0, sizeof(mac_vals));
10798
10799         if (bnx2x_prev_is_path_marked(bp))
10800                 return bnx2x_prev_mcp_done(bp);
10801
10802         reset_reg = REG_RD(bp, MISC_REG_RESET_REG_1);
10803
10804         /* Reset should be performed after BRB is emptied */
10805         if (reset_reg & MISC_REGISTERS_RESET_REG_1_RST_BRB1) {
10806                 u32 timer_count = 1000;
10807
10808                 /* Close the MAC Rx to prevent BRB from filling up */
10809                 bnx2x_prev_unload_close_mac(bp, &mac_vals);
10810
10811                 /* close LLH filters for both ports towards the BRB */
10812                 bnx2x_set_rx_filter(&bp->link_params, 0);
10813                 bp->link_params.port ^= 1;
10814                 bnx2x_set_rx_filter(&bp->link_params, 0);
10815                 bp->link_params.port ^= 1;
10816
10817                 /* Check if the UNDI driver was previously loaded */
10818                 if (bnx2x_prev_is_after_undi(bp)) {
10819                         prev_undi = true;
10820                         /* clear the UNDI indication */
10821                         REG_WR(bp, DORQ_REG_NORM_CID_OFST, 0);
10822                         /* clear possible idle check errors */
10823                         REG_RD(bp, NIG_REG_NIG_INT_STS_CLR_0);
10824                 }
10825                 if (!CHIP_IS_E1x(bp))
10826                         /* block FW from writing to host */
10827                         REG_WR(bp, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, 0);
10828
10829                 /* wait until BRB is empty */
10830                 tmp_reg = REG_RD(bp, BRB1_REG_NUM_OF_FULL_BLOCKS);
10831                 while (timer_count) {
10832                         u32 prev_brb = tmp_reg;
10833
10834                         tmp_reg = REG_RD(bp, BRB1_REG_NUM_OF_FULL_BLOCKS);
10835                         if (!tmp_reg)
10836                                 break;
10837
10838                         BNX2X_DEV_INFO("BRB still has 0x%08x\n", tmp_reg);
10839
10840                         /* reset timer as long as BRB actually gets emptied */
10841                         if (prev_brb > tmp_reg)
10842                                 timer_count = 1000;
10843                         else
10844                                 timer_count--;
10845
10846                         /* If UNDI resides in memory, manually increment it */
10847                         if (prev_undi)
10848                                 bnx2x_prev_unload_undi_inc(bp, 1);
10849
10850                         udelay(10);
10851                 }
10852
10853                 if (!timer_count)
10854                         BNX2X_ERR("Failed to empty BRB, hope for the best\n");
10855         }
10856
10857         /* No packets are in the pipeline, path is ready for reset */
10858         bnx2x_reset_common(bp);
10859
10860         if (mac_vals.xmac_addr)
10861                 REG_WR(bp, mac_vals.xmac_addr, mac_vals.xmac_val);
10862         if (mac_vals.umac_addr[0])
10863                 REG_WR(bp, mac_vals.umac_addr[0], mac_vals.umac_val[0]);
10864         if (mac_vals.umac_addr[1])
10865                 REG_WR(bp, mac_vals.umac_addr[1], mac_vals.umac_val[1]);
10866         if (mac_vals.emac_addr)
10867                 REG_WR(bp, mac_vals.emac_addr, mac_vals.emac_val);
10868         if (mac_vals.bmac_addr) {
10869                 REG_WR(bp, mac_vals.bmac_addr, mac_vals.bmac_val[0]);
10870                 REG_WR(bp, mac_vals.bmac_addr + 4, mac_vals.bmac_val[1]);
10871         }
10872
10873         rc = bnx2x_prev_mark_path(bp, prev_undi);
10874         if (rc) {
10875                 bnx2x_prev_mcp_done(bp);
10876                 return rc;
10877         }
10878
10879         return bnx2x_prev_mcp_done(bp);
10880 }
10881
10882 static int bnx2x_prev_unload(struct bnx2x *bp)
10883 {
10884         int time_counter = 10;
10885         u32 rc, fw, hw_lock_reg, hw_lock_val;
10886         BNX2X_DEV_INFO("Entering Previous Unload Flow\n");
10887
10888         /* clear hw from errors which may have resulted from an interrupted
10889          * dmae transaction.
10890          */
10891         bnx2x_clean_pglue_errors(bp);
10892
10893         /* Release previously held locks */
10894         hw_lock_reg = (BP_FUNC(bp) <= 5) ?
10895                       (MISC_REG_DRIVER_CONTROL_1 + BP_FUNC(bp) * 8) :
10896                       (MISC_REG_DRIVER_CONTROL_7 + (BP_FUNC(bp) - 6) * 8);
10897
10898         hw_lock_val = REG_RD(bp, hw_lock_reg);
10899         if (hw_lock_val) {
10900                 if (hw_lock_val & HW_LOCK_RESOURCE_NVRAM) {
10901                         BNX2X_DEV_INFO("Release Previously held NVRAM lock\n");
10902                         REG_WR(bp, MCP_REG_MCPR_NVM_SW_ARB,
10903                                (MCPR_NVM_SW_ARB_ARB_REQ_CLR1 << BP_PORT(bp)));
10904                 }
10905
10906                 BNX2X_DEV_INFO("Release Previously held hw lock\n");
10907                 REG_WR(bp, hw_lock_reg, 0xffffffff);
10908         } else
10909                 BNX2X_DEV_INFO("No need to release hw/nvram locks\n");
10910
10911         if (MCPR_ACCESS_LOCK_LOCK & REG_RD(bp, MCP_REG_MCPR_ACCESS_LOCK)) {
10912                 BNX2X_DEV_INFO("Release previously held alr\n");
10913                 bnx2x_release_alr(bp);
10914         }
10915
10916         do {
10917                 int aer = 0;
10918                 /* Lock MCP using an unload request */
10919                 fw = bnx2x_fw_command(bp, DRV_MSG_CODE_UNLOAD_REQ_WOL_DIS, 0);
10920                 if (!fw) {
10921                         BNX2X_ERR("MCP response failure, aborting\n");
10922                         rc = -EBUSY;
10923                         break;
10924                 }
10925
10926                 rc = down_interruptible(&bnx2x_prev_sem);
10927                 if (rc) {
10928                         BNX2X_ERR("Cannot check for AER; Received %d when tried to take lock\n",
10929                                   rc);
10930                 } else {
10931                         /* If Path is marked by EEH, ignore unload status */
10932                         aer = !!(bnx2x_prev_path_get_entry(bp) &&
10933                                  bnx2x_prev_path_get_entry(bp)->aer);
10934                         up(&bnx2x_prev_sem);
10935                 }
10936
10937                 if (fw == FW_MSG_CODE_DRV_UNLOAD_COMMON || aer) {
10938                         rc = bnx2x_prev_unload_common(bp);
10939                         break;
10940                 }
10941
10942                 /* non-common reply from MCP might require looping */
10943                 rc = bnx2x_prev_unload_uncommon(bp);
10944                 if (rc != BNX2X_PREV_WAIT_NEEDED)
10945                         break;
10946
10947                 msleep(20);
10948         } while (--time_counter);
10949
10950         if (!time_counter || rc) {
10951                 BNX2X_DEV_INFO("Unloading previous driver did not occur, Possibly due to MF UNDI\n");
10952                 rc = -EPROBE_DEFER;
10953         }
10954
10955         /* Mark function if its port was used to boot from SAN */
10956         if (bnx2x_port_after_undi(bp))
10957                 bp->link_params.feature_config_flags |=
10958                         FEATURE_CONFIG_BOOT_FROM_SAN;
10959
10960         BNX2X_DEV_INFO("Finished Previous Unload Flow [%d]\n", rc);
10961
10962         return rc;
10963 }
10964
10965 static void bnx2x_get_common_hwinfo(struct bnx2x *bp)
10966 {
10967         u32 val, val2, val3, val4, id, boot_mode;
10968         u16 pmc;
10969
10970         /* Get the chip revision id and number. */
10971         /* chip num:16-31, rev:12-15, metal:4-11, bond_id:0-3 */
10972         val = REG_RD(bp, MISC_REG_CHIP_NUM);
10973         id = ((val & 0xffff) << 16);
10974         val = REG_RD(bp, MISC_REG_CHIP_REV);
10975         id |= ((val & 0xf) << 12);
10976
10977         /* Metal is read from PCI regs, but we can't access >=0x400 from
10978          * the configuration space (so we need to reg_rd)
10979          */
10980         val = REG_RD(bp, PCICFG_OFFSET + PCI_ID_VAL3);
10981         id |= (((val >> 24) & 0xf) << 4);
10982         val = REG_RD(bp, MISC_REG_BOND_ID);
10983         id |= (val & 0xf);
10984         bp->common.chip_id = id;
10985
10986         /* force 57811 according to MISC register */
10987         if (REG_RD(bp, MISC_REG_CHIP_TYPE) & MISC_REG_CHIP_TYPE_57811_MASK) {
10988                 if (CHIP_IS_57810(bp))
10989                         bp->common.chip_id = (CHIP_NUM_57811 << 16) |
10990                                 (bp->common.chip_id & 0x0000FFFF);
10991                 else if (CHIP_IS_57810_MF(bp))
10992                         bp->common.chip_id = (CHIP_NUM_57811_MF << 16) |
10993                                 (bp->common.chip_id & 0x0000FFFF);
10994                 bp->common.chip_id |= 0x1;
10995         }
10996
10997         /* Set doorbell size */
10998         bp->db_size = (1 << BNX2X_DB_SHIFT);
10999
11000         if (!CHIP_IS_E1x(bp)) {
11001                 val = REG_RD(bp, MISC_REG_PORT4MODE_EN_OVWR);
11002                 if ((val & 1) == 0)
11003                         val = REG_RD(bp, MISC_REG_PORT4MODE_EN);
11004                 else
11005                         val = (val >> 1) & 1;
11006                 BNX2X_DEV_INFO("chip is in %s\n", val ? "4_PORT_MODE" :
11007                                                        "2_PORT_MODE");
11008                 bp->common.chip_port_mode = val ? CHIP_4_PORT_MODE :
11009                                                  CHIP_2_PORT_MODE;
11010
11011                 if (CHIP_MODE_IS_4_PORT(bp))
11012                         bp->pfid = (bp->pf_num >> 1);   /* 0..3 */
11013                 else
11014                         bp->pfid = (bp->pf_num & 0x6);  /* 0, 2, 4, 6 */
11015         } else {
11016                 bp->common.chip_port_mode = CHIP_PORT_MODE_NONE; /* N/A */
11017                 bp->pfid = bp->pf_num;                  /* 0..7 */
11018         }
11019
11020         BNX2X_DEV_INFO("pf_id: %x", bp->pfid);
11021
11022         bp->link_params.chip_id = bp->common.chip_id;
11023         BNX2X_DEV_INFO("chip ID is 0x%x\n", id);
11024
11025         val = (REG_RD(bp, 0x2874) & 0x55);
11026         if ((bp->common.chip_id & 0x1) ||
11027             (CHIP_IS_E1(bp) && val) || (CHIP_IS_E1H(bp) && (val == 0x55))) {
11028                 bp->flags |= ONE_PORT_FLAG;
11029                 BNX2X_DEV_INFO("single port device\n");
11030         }
11031
11032         val = REG_RD(bp, MCP_REG_MCPR_NVM_CFG4);
11033         bp->common.flash_size = (BNX2X_NVRAM_1MB_SIZE <<
11034                                  (val & MCPR_NVM_CFG4_FLASH_SIZE));
11035         BNX2X_DEV_INFO("flash_size 0x%x (%d)\n",
11036                        bp->common.flash_size, bp->common.flash_size);
11037
11038         bnx2x_init_shmem(bp);
11039
11040         bp->common.shmem2_base = REG_RD(bp, (BP_PATH(bp) ?
11041                                         MISC_REG_GENERIC_CR_1 :
11042                                         MISC_REG_GENERIC_CR_0));
11043
11044         bp->link_params.shmem_base = bp->common.shmem_base;
11045         bp->link_params.shmem2_base = bp->common.shmem2_base;
11046         if (SHMEM2_RD(bp, size) >
11047             (u32)offsetof(struct shmem2_region, lfa_host_addr[BP_PORT(bp)]))
11048                 bp->link_params.lfa_base =
11049                 REG_RD(bp, bp->common.shmem2_base +
11050                        (u32)offsetof(struct shmem2_region,
11051                                      lfa_host_addr[BP_PORT(bp)]));
11052         else
11053                 bp->link_params.lfa_base = 0;
11054         BNX2X_DEV_INFO("shmem offset 0x%x  shmem2 offset 0x%x\n",
11055                        bp->common.shmem_base, bp->common.shmem2_base);
11056
11057         if (!bp->common.shmem_base) {
11058                 BNX2X_DEV_INFO("MCP not active\n");
11059                 bp->flags |= NO_MCP_FLAG;
11060                 return;
11061         }
11062
11063         bp->common.hw_config = SHMEM_RD(bp, dev_info.shared_hw_config.config);
11064         BNX2X_DEV_INFO("hw_config 0x%08x\n", bp->common.hw_config);
11065
11066         bp->link_params.hw_led_mode = ((bp->common.hw_config &
11067                                         SHARED_HW_CFG_LED_MODE_MASK) >>
11068                                        SHARED_HW_CFG_LED_MODE_SHIFT);
11069
11070         bp->link_params.feature_config_flags = 0;
11071         val = SHMEM_RD(bp, dev_info.shared_feature_config.config);
11072         if (val & SHARED_FEAT_CFG_OVERRIDE_PREEMPHASIS_CFG_ENABLED)
11073                 bp->link_params.feature_config_flags |=
11074                                 FEATURE_CONFIG_OVERRIDE_PREEMPHASIS_ENABLED;
11075         else
11076                 bp->link_params.feature_config_flags &=
11077                                 ~FEATURE_CONFIG_OVERRIDE_PREEMPHASIS_ENABLED;
11078
11079         val = SHMEM_RD(bp, dev_info.bc_rev) >> 8;
11080         bp->common.bc_ver = val;
11081         BNX2X_DEV_INFO("bc_ver %X\n", val);
11082         if (val < BNX2X_BC_VER) {
11083                 /* for now only warn
11084                  * later we might need to enforce this */
11085                 BNX2X_ERR("This driver needs bc_ver %X but found %X, please upgrade BC\n",
11086                           BNX2X_BC_VER, val);
11087         }
11088         bp->link_params.feature_config_flags |=
11089                                 (val >= REQ_BC_VER_4_VRFY_FIRST_PHY_OPT_MDL) ?
11090                                 FEATURE_CONFIG_BC_SUPPORTS_OPT_MDL_VRFY : 0;
11091
11092         bp->link_params.feature_config_flags |=
11093                 (val >= REQ_BC_VER_4_VRFY_SPECIFIC_PHY_OPT_MDL) ?
11094                 FEATURE_CONFIG_BC_SUPPORTS_DUAL_PHY_OPT_MDL_VRFY : 0;
11095         bp->link_params.feature_config_flags |=
11096                 (val >= REQ_BC_VER_4_VRFY_AFEX_SUPPORTED) ?
11097                 FEATURE_CONFIG_BC_SUPPORTS_AFEX : 0;
11098         bp->link_params.feature_config_flags |=
11099                 (val >= REQ_BC_VER_4_SFP_TX_DISABLE_SUPPORTED) ?
11100                 FEATURE_CONFIG_BC_SUPPORTS_SFP_TX_DISABLED : 0;
11101
11102         bp->link_params.feature_config_flags |=
11103                 (val >= REQ_BC_VER_4_MT_SUPPORTED) ?
11104                 FEATURE_CONFIG_MT_SUPPORT : 0;
11105
11106         bp->flags |= (val >= REQ_BC_VER_4_PFC_STATS_SUPPORTED) ?
11107                         BC_SUPPORTS_PFC_STATS : 0;
11108
11109         bp->flags |= (val >= REQ_BC_VER_4_FCOE_FEATURES) ?
11110                         BC_SUPPORTS_FCOE_FEATURES : 0;
11111
11112         bp->flags |= (val >= REQ_BC_VER_4_DCBX_ADMIN_MSG_NON_PMF) ?
11113                         BC_SUPPORTS_DCBX_MSG_NON_PMF : 0;
11114
11115         bp->flags |= (val >= REQ_BC_VER_4_RMMOD_CMD) ?
11116                         BC_SUPPORTS_RMMOD_CMD : 0;
11117
11118         boot_mode = SHMEM_RD(bp,
11119                         dev_info.port_feature_config[BP_PORT(bp)].mba_config) &
11120                         PORT_FEATURE_MBA_BOOT_AGENT_TYPE_MASK;
11121         switch (boot_mode) {
11122         case PORT_FEATURE_MBA_BOOT_AGENT_TYPE_PXE:
11123                 bp->common.boot_mode = FEATURE_ETH_BOOTMODE_PXE;
11124                 break;
11125         case PORT_FEATURE_MBA_BOOT_AGENT_TYPE_ISCSIB:
11126                 bp->common.boot_mode = FEATURE_ETH_BOOTMODE_ISCSI;
11127                 break;
11128         case PORT_FEATURE_MBA_BOOT_AGENT_TYPE_FCOE_BOOT:
11129                 bp->common.boot_mode = FEATURE_ETH_BOOTMODE_FCOE;
11130                 break;
11131         case PORT_FEATURE_MBA_BOOT_AGENT_TYPE_NONE:
11132                 bp->common.boot_mode = FEATURE_ETH_BOOTMODE_NONE;
11133                 break;
11134         }
11135
11136         pci_read_config_word(bp->pdev, bp->pdev->pm_cap + PCI_PM_PMC, &pmc);
11137         bp->flags |= (pmc & PCI_PM_CAP_PME_D3cold) ? 0 : NO_WOL_FLAG;
11138
11139         BNX2X_DEV_INFO("%sWoL capable\n",
11140                        (bp->flags & NO_WOL_FLAG) ? "not " : "");
11141
11142         val = SHMEM_RD(bp, dev_info.shared_hw_config.part_num);
11143         val2 = SHMEM_RD(bp, dev_info.shared_hw_config.part_num[4]);
11144         val3 = SHMEM_RD(bp, dev_info.shared_hw_config.part_num[8]);
11145         val4 = SHMEM_RD(bp, dev_info.shared_hw_config.part_num[12]);
11146
11147         dev_info(&bp->pdev->dev, "part number %X-%X-%X-%X\n",
11148                  val, val2, val3, val4);
11149 }
11150
11151 #define IGU_FID(val)    GET_FIELD((val), IGU_REG_MAPPING_MEMORY_FID)
11152 #define IGU_VEC(val)    GET_FIELD((val), IGU_REG_MAPPING_MEMORY_VECTOR)
11153
11154 static int bnx2x_get_igu_cam_info(struct bnx2x *bp)
11155 {
11156         int pfid = BP_FUNC(bp);
11157         int igu_sb_id;
11158         u32 val;
11159         u8 fid, igu_sb_cnt = 0;
11160
11161         bp->igu_base_sb = 0xff;
11162         if (CHIP_INT_MODE_IS_BC(bp)) {
11163                 int vn = BP_VN(bp);
11164                 igu_sb_cnt = bp->igu_sb_cnt;
11165                 bp->igu_base_sb = (CHIP_MODE_IS_4_PORT(bp) ? pfid : vn) *
11166                         FP_SB_MAX_E1x;
11167
11168                 bp->igu_dsb_id =  E1HVN_MAX * FP_SB_MAX_E1x +
11169                         (CHIP_MODE_IS_4_PORT(bp) ? pfid : vn);
11170
11171                 return 0;
11172         }
11173
11174         /* IGU in normal mode - read CAM */
11175         for (igu_sb_id = 0; igu_sb_id < IGU_REG_MAPPING_MEMORY_SIZE;
11176              igu_sb_id++) {
11177                 val = REG_RD(bp, IGU_REG_MAPPING_MEMORY + igu_sb_id * 4);
11178                 if (!(val & IGU_REG_MAPPING_MEMORY_VALID))
11179                         continue;
11180                 fid = IGU_FID(val);
11181                 if ((fid & IGU_FID_ENCODE_IS_PF)) {
11182                         if ((fid & IGU_FID_PF_NUM_MASK) != pfid)
11183                                 continue;
11184                         if (IGU_VEC(val) == 0)
11185                                 /* default status block */
11186                                 bp->igu_dsb_id = igu_sb_id;
11187                         else {
11188                                 if (bp->igu_base_sb == 0xff)
11189                                         bp->igu_base_sb = igu_sb_id;
11190                                 igu_sb_cnt++;
11191                         }
11192                 }
11193         }
11194
11195 #ifdef CONFIG_PCI_MSI
11196         /* Due to new PF resource allocation by MFW T7.4 and above, it's
11197          * optional that number of CAM entries will not be equal to the value
11198          * advertised in PCI.
11199          * Driver should use the minimal value of both as the actual status
11200          * block count
11201          */
11202         bp->igu_sb_cnt = min_t(int, bp->igu_sb_cnt, igu_sb_cnt);
11203 #endif
11204
11205         if (igu_sb_cnt == 0) {
11206                 BNX2X_ERR("CAM configuration error\n");
11207                 return -EINVAL;
11208         }
11209
11210         return 0;
11211 }
11212
11213 static void bnx2x_link_settings_supported(struct bnx2x *bp, u32 switch_cfg)
11214 {
11215         int cfg_size = 0, idx, port = BP_PORT(bp);
11216
11217         /* Aggregation of supported attributes of all external phys */
11218         bp->port.supported[0] = 0;
11219         bp->port.supported[1] = 0;
11220         switch (bp->link_params.num_phys) {
11221         case 1:
11222                 bp->port.supported[0] = bp->link_params.phy[INT_PHY].supported;
11223                 cfg_size = 1;
11224                 break;
11225         case 2:
11226                 bp->port.supported[0] = bp->link_params.phy[EXT_PHY1].supported;
11227                 cfg_size = 1;
11228                 break;
11229         case 3:
11230                 if (bp->link_params.multi_phy_config &
11231                     PORT_HW_CFG_PHY_SWAPPED_ENABLED) {
11232                         bp->port.supported[1] =
11233                                 bp->link_params.phy[EXT_PHY1].supported;
11234                         bp->port.supported[0] =
11235                                 bp->link_params.phy[EXT_PHY2].supported;
11236                 } else {
11237                         bp->port.supported[0] =
11238                                 bp->link_params.phy[EXT_PHY1].supported;
11239                         bp->port.supported[1] =
11240                                 bp->link_params.phy[EXT_PHY2].supported;
11241                 }
11242                 cfg_size = 2;
11243                 break;
11244         }
11245
11246         if (!(bp->port.supported[0] || bp->port.supported[1])) {
11247                 BNX2X_ERR("NVRAM config error. BAD phy config. PHY1 config 0x%x, PHY2 config 0x%x\n",
11248                            SHMEM_RD(bp,
11249                            dev_info.port_hw_config[port].external_phy_config),
11250                            SHMEM_RD(bp,
11251                            dev_info.port_hw_config[port].external_phy_config2));
11252                         return;
11253         }
11254
11255         if (CHIP_IS_E3(bp))
11256                 bp->port.phy_addr = REG_RD(bp, MISC_REG_WC0_CTRL_PHY_ADDR);
11257         else {
11258                 switch (switch_cfg) {
11259                 case SWITCH_CFG_1G:
11260                         bp->port.phy_addr = REG_RD(
11261                                 bp, NIG_REG_SERDES0_CTRL_PHY_ADDR + port*0x10);
11262                         break;
11263                 case SWITCH_CFG_10G:
11264                         bp->port.phy_addr = REG_RD(
11265                                 bp, NIG_REG_XGXS0_CTRL_PHY_ADDR + port*0x18);
11266                         break;
11267                 default:
11268                         BNX2X_ERR("BAD switch_cfg link_config 0x%x\n",
11269                                   bp->port.link_config[0]);
11270                         return;
11271                 }
11272         }
11273         BNX2X_DEV_INFO("phy_addr 0x%x\n", bp->port.phy_addr);
11274         /* mask what we support according to speed_cap_mask per configuration */
11275         for (idx = 0; idx < cfg_size; idx++) {
11276                 if (!(bp->link_params.speed_cap_mask[idx] &
11277                                 PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_HALF))
11278                         bp->port.supported[idx] &= ~SUPPORTED_10baseT_Half;
11279
11280                 if (!(bp->link_params.speed_cap_mask[idx] &
11281                                 PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_FULL))
11282                         bp->port.supported[idx] &= ~SUPPORTED_10baseT_Full;
11283
11284                 if (!(bp->link_params.speed_cap_mask[idx] &
11285                                 PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_HALF))
11286                         bp->port.supported[idx] &= ~SUPPORTED_100baseT_Half;
11287
11288                 if (!(bp->link_params.speed_cap_mask[idx] &
11289                                 PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_FULL))
11290                         bp->port.supported[idx] &= ~SUPPORTED_100baseT_Full;
11291
11292                 if (!(bp->link_params.speed_cap_mask[idx] &
11293                                         PORT_HW_CFG_SPEED_CAPABILITY_D0_1G))
11294                         bp->port.supported[idx] &= ~(SUPPORTED_1000baseT_Half |
11295                                                      SUPPORTED_1000baseT_Full);
11296
11297                 if (!(bp->link_params.speed_cap_mask[idx] &
11298                                         PORT_HW_CFG_SPEED_CAPABILITY_D0_2_5G))
11299                         bp->port.supported[idx] &= ~SUPPORTED_2500baseX_Full;
11300
11301                 if (!(bp->link_params.speed_cap_mask[idx] &
11302                                         PORT_HW_CFG_SPEED_CAPABILITY_D0_10G))
11303                         bp->port.supported[idx] &= ~SUPPORTED_10000baseT_Full;
11304
11305                 if (!(bp->link_params.speed_cap_mask[idx] &
11306                                         PORT_HW_CFG_SPEED_CAPABILITY_D0_20G))
11307                         bp->port.supported[idx] &= ~SUPPORTED_20000baseKR2_Full;
11308         }
11309
11310         BNX2X_DEV_INFO("supported 0x%x 0x%x\n", bp->port.supported[0],
11311                        bp->port.supported[1]);
11312 }
11313
11314 static void bnx2x_link_settings_requested(struct bnx2x *bp)
11315 {
11316         u32 link_config, idx, cfg_size = 0;
11317         bp->port.advertising[0] = 0;
11318         bp->port.advertising[1] = 0;
11319         switch (bp->link_params.num_phys) {
11320         case 1:
11321         case 2:
11322                 cfg_size = 1;
11323                 break;
11324         case 3:
11325                 cfg_size = 2;
11326                 break;
11327         }
11328         for (idx = 0; idx < cfg_size; idx++) {
11329                 bp->link_params.req_duplex[idx] = DUPLEX_FULL;
11330                 link_config = bp->port.link_config[idx];
11331                 switch (link_config & PORT_FEATURE_LINK_SPEED_MASK) {
11332                 case PORT_FEATURE_LINK_SPEED_AUTO:
11333                         if (bp->port.supported[idx] & SUPPORTED_Autoneg) {
11334                                 bp->link_params.req_line_speed[idx] =
11335                                         SPEED_AUTO_NEG;
11336                                 bp->port.advertising[idx] |=
11337                                         bp->port.supported[idx];
11338                                 if (bp->link_params.phy[EXT_PHY1].type ==
11339                                     PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84833)
11340                                         bp->port.advertising[idx] |=
11341                                         (SUPPORTED_100baseT_Half |
11342                                          SUPPORTED_100baseT_Full);
11343                         } else {
11344                                 /* force 10G, no AN */
11345                                 bp->link_params.req_line_speed[idx] =
11346                                         SPEED_10000;
11347                                 bp->port.advertising[idx] |=
11348                                         (ADVERTISED_10000baseT_Full |
11349                                          ADVERTISED_FIBRE);
11350                                 continue;
11351                         }
11352                         break;
11353
11354                 case PORT_FEATURE_LINK_SPEED_10M_FULL:
11355                         if (bp->port.supported[idx] & SUPPORTED_10baseT_Full) {
11356                                 bp->link_params.req_line_speed[idx] =
11357                                         SPEED_10;
11358                                 bp->port.advertising[idx] |=
11359                                         (ADVERTISED_10baseT_Full |
11360                                          ADVERTISED_TP);
11361                         } else {
11362                                 BNX2X_ERR("NVRAM config error. Invalid link_config 0x%x  speed_cap_mask 0x%x\n",
11363                                             link_config,
11364                                     bp->link_params.speed_cap_mask[idx]);
11365                                 return;
11366                         }
11367                         break;
11368
11369                 case PORT_FEATURE_LINK_SPEED_10M_HALF:
11370                         if (bp->port.supported[idx] & SUPPORTED_10baseT_Half) {
11371                                 bp->link_params.req_line_speed[idx] =
11372                                         SPEED_10;
11373                                 bp->link_params.req_duplex[idx] =
11374                                         DUPLEX_HALF;
11375                                 bp->port.advertising[idx] |=
11376                                         (ADVERTISED_10baseT_Half |
11377                                          ADVERTISED_TP);
11378                         } else {
11379                                 BNX2X_ERR("NVRAM config error. Invalid link_config 0x%x  speed_cap_mask 0x%x\n",
11380                                             link_config,
11381                                           bp->link_params.speed_cap_mask[idx]);
11382                                 return;
11383                         }
11384                         break;
11385
11386                 case PORT_FEATURE_LINK_SPEED_100M_FULL:
11387                         if (bp->port.supported[idx] &
11388                             SUPPORTED_100baseT_Full) {
11389                                 bp->link_params.req_line_speed[idx] =
11390                                         SPEED_100;
11391                                 bp->port.advertising[idx] |=
11392                                         (ADVERTISED_100baseT_Full |
11393                                          ADVERTISED_TP);
11394                         } else {
11395                                 BNX2X_ERR("NVRAM config error. Invalid link_config 0x%x  speed_cap_mask 0x%x\n",
11396                                             link_config,
11397                                           bp->link_params.speed_cap_mask[idx]);
11398                                 return;
11399                         }
11400                         break;
11401
11402                 case PORT_FEATURE_LINK_SPEED_100M_HALF:
11403                         if (bp->port.supported[idx] &
11404                             SUPPORTED_100baseT_Half) {
11405                                 bp->link_params.req_line_speed[idx] =
11406                                                                 SPEED_100;
11407                                 bp->link_params.req_duplex[idx] =
11408                                                                 DUPLEX_HALF;
11409                                 bp->port.advertising[idx] |=
11410                                         (ADVERTISED_100baseT_Half |
11411                                          ADVERTISED_TP);
11412                         } else {
11413                                 BNX2X_ERR("NVRAM config error. Invalid link_config 0x%x  speed_cap_mask 0x%x\n",
11414                                     link_config,
11415                                     bp->link_params.speed_cap_mask[idx]);
11416                                 return;
11417                         }
11418                         break;
11419
11420                 case PORT_FEATURE_LINK_SPEED_1G:
11421                         if (bp->port.supported[idx] &
11422                             SUPPORTED_1000baseT_Full) {
11423                                 bp->link_params.req_line_speed[idx] =
11424                                         SPEED_1000;
11425                                 bp->port.advertising[idx] |=
11426                                         (ADVERTISED_1000baseT_Full |
11427                                          ADVERTISED_TP);
11428                         } else if (bp->port.supported[idx] &
11429                                    SUPPORTED_1000baseKX_Full) {
11430                                 bp->link_params.req_line_speed[idx] =
11431                                         SPEED_1000;
11432                                 bp->port.advertising[idx] |=
11433                                         ADVERTISED_1000baseKX_Full;
11434                         } else {
11435                                 BNX2X_ERR("NVRAM config error. Invalid link_config 0x%x  speed_cap_mask 0x%x\n",
11436                                     link_config,
11437                                     bp->link_params.speed_cap_mask[idx]);
11438                                 return;
11439                         }
11440                         break;
11441
11442                 case PORT_FEATURE_LINK_SPEED_2_5G:
11443                         if (bp->port.supported[idx] &
11444                             SUPPORTED_2500baseX_Full) {
11445                                 bp->link_params.req_line_speed[idx] =
11446                                         SPEED_2500;
11447                                 bp->port.advertising[idx] |=
11448                                         (ADVERTISED_2500baseX_Full |
11449                                                 ADVERTISED_TP);
11450                         } else {
11451                                 BNX2X_ERR("NVRAM config error. Invalid link_config 0x%x  speed_cap_mask 0x%x\n",
11452                                     link_config,
11453                                     bp->link_params.speed_cap_mask[idx]);
11454                                 return;
11455                         }
11456                         break;
11457
11458                 case PORT_FEATURE_LINK_SPEED_10G_CX4:
11459                         if (bp->port.supported[idx] &
11460                             SUPPORTED_10000baseT_Full) {
11461                                 bp->link_params.req_line_speed[idx] =
11462                                         SPEED_10000;
11463                                 bp->port.advertising[idx] |=
11464                                         (ADVERTISED_10000baseT_Full |
11465                                                 ADVERTISED_FIBRE);
11466                         } else if (bp->port.supported[idx] &
11467                                    SUPPORTED_10000baseKR_Full) {
11468                                 bp->link_params.req_line_speed[idx] =
11469                                         SPEED_10000;
11470                                 bp->port.advertising[idx] |=
11471                                         (ADVERTISED_10000baseKR_Full |
11472                                                 ADVERTISED_FIBRE);
11473                         } else {
11474                                 BNX2X_ERR("NVRAM config error. Invalid link_config 0x%x  speed_cap_mask 0x%x\n",
11475                                     link_config,
11476                                     bp->link_params.speed_cap_mask[idx]);
11477                                 return;
11478                         }
11479                         break;
11480                 case PORT_FEATURE_LINK_SPEED_20G:
11481                         bp->link_params.req_line_speed[idx] = SPEED_20000;
11482
11483                         break;
11484                 default:
11485                         BNX2X_ERR("NVRAM config error. BAD link speed link_config 0x%x\n",
11486                                   link_config);
11487                                 bp->link_params.req_line_speed[idx] =
11488                                                         SPEED_AUTO_NEG;
11489                                 bp->port.advertising[idx] =
11490                                                 bp->port.supported[idx];
11491                         break;
11492                 }
11493
11494                 bp->link_params.req_flow_ctrl[idx] = (link_config &
11495                                          PORT_FEATURE_FLOW_CONTROL_MASK);
11496                 if (bp->link_params.req_flow_ctrl[idx] ==
11497                     BNX2X_FLOW_CTRL_AUTO) {
11498                         if (!(bp->port.supported[idx] & SUPPORTED_Autoneg))
11499                                 bp->link_params.req_flow_ctrl[idx] =
11500                                                         BNX2X_FLOW_CTRL_NONE;
11501                         else
11502                                 bnx2x_set_requested_fc(bp);
11503                 }
11504
11505                 BNX2X_DEV_INFO("req_line_speed %d  req_duplex %d req_flow_ctrl 0x%x advertising 0x%x\n",
11506                                bp->link_params.req_line_speed[idx],
11507                                bp->link_params.req_duplex[idx],
11508                                bp->link_params.req_flow_ctrl[idx],
11509                                bp->port.advertising[idx]);
11510         }
11511 }
11512
11513 static void bnx2x_set_mac_buf(u8 *mac_buf, u32 mac_lo, u16 mac_hi)
11514 {
11515         __be16 mac_hi_be = cpu_to_be16(mac_hi);
11516         __be32 mac_lo_be = cpu_to_be32(mac_lo);
11517         memcpy(mac_buf, &mac_hi_be, sizeof(mac_hi_be));
11518         memcpy(mac_buf + sizeof(mac_hi_be), &mac_lo_be, sizeof(mac_lo_be));
11519 }
11520
11521 static void bnx2x_get_port_hwinfo(struct bnx2x *bp)
11522 {
11523         int port = BP_PORT(bp);
11524         u32 config;
11525         u32 ext_phy_type, ext_phy_config, eee_mode;
11526
11527         bp->link_params.bp = bp;
11528         bp->link_params.port = port;
11529
11530         bp->link_params.lane_config =
11531                 SHMEM_RD(bp, dev_info.port_hw_config[port].lane_config);
11532
11533         bp->link_params.speed_cap_mask[0] =
11534                 SHMEM_RD(bp,
11535                          dev_info.port_hw_config[port].speed_capability_mask) &
11536                 PORT_HW_CFG_SPEED_CAPABILITY_D0_MASK;
11537         bp->link_params.speed_cap_mask[1] =
11538                 SHMEM_RD(bp,
11539                          dev_info.port_hw_config[port].speed_capability_mask2) &
11540                 PORT_HW_CFG_SPEED_CAPABILITY_D0_MASK;
11541         bp->port.link_config[0] =
11542                 SHMEM_RD(bp, dev_info.port_feature_config[port].link_config);
11543
11544         bp->port.link_config[1] =
11545                 SHMEM_RD(bp, dev_info.port_feature_config[port].link_config2);
11546
11547         bp->link_params.multi_phy_config =
11548                 SHMEM_RD(bp, dev_info.port_hw_config[port].multi_phy_config);
11549         /* If the device is capable of WoL, set the default state according
11550          * to the HW
11551          */
11552         config = SHMEM_RD(bp, dev_info.port_feature_config[port].config);
11553         bp->wol = (!(bp->flags & NO_WOL_FLAG) &&
11554                    (config & PORT_FEATURE_WOL_ENABLED));
11555
11556         if ((config & PORT_FEAT_CFG_STORAGE_PERSONALITY_MASK) ==
11557             PORT_FEAT_CFG_STORAGE_PERSONALITY_FCOE && !IS_MF(bp))
11558                 bp->flags |= NO_ISCSI_FLAG;
11559         if ((config & PORT_FEAT_CFG_STORAGE_PERSONALITY_MASK) ==
11560             PORT_FEAT_CFG_STORAGE_PERSONALITY_ISCSI && !(IS_MF(bp)))
11561                 bp->flags |= NO_FCOE_FLAG;
11562
11563         BNX2X_DEV_INFO("lane_config 0x%08x  speed_cap_mask0 0x%08x  link_config0 0x%08x\n",
11564                        bp->link_params.lane_config,
11565                        bp->link_params.speed_cap_mask[0],
11566                        bp->port.link_config[0]);
11567
11568         bp->link_params.switch_cfg = (bp->port.link_config[0] &
11569                                       PORT_FEATURE_CONNECTED_SWITCH_MASK);
11570         bnx2x_phy_probe(&bp->link_params);
11571         bnx2x_link_settings_supported(bp, bp->link_params.switch_cfg);
11572
11573         bnx2x_link_settings_requested(bp);
11574
11575         /*
11576          * If connected directly, work with the internal PHY, otherwise, work
11577          * with the external PHY
11578          */
11579         ext_phy_config =
11580                 SHMEM_RD(bp,
11581                          dev_info.port_hw_config[port].external_phy_config);
11582         ext_phy_type = XGXS_EXT_PHY_TYPE(ext_phy_config);
11583         if (ext_phy_type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT)
11584                 bp->mdio.prtad = bp->port.phy_addr;
11585
11586         else if ((ext_phy_type != PORT_HW_CFG_XGXS_EXT_PHY_TYPE_FAILURE) &&
11587                  (ext_phy_type != PORT_HW_CFG_XGXS_EXT_PHY_TYPE_NOT_CONN))
11588                 bp->mdio.prtad =
11589                         XGXS_EXT_PHY_ADDR(ext_phy_config);
11590
11591         /* Configure link feature according to nvram value */
11592         eee_mode = (((SHMEM_RD(bp, dev_info.
11593                       port_feature_config[port].eee_power_mode)) &
11594                      PORT_FEAT_CFG_EEE_POWER_MODE_MASK) >>
11595                     PORT_FEAT_CFG_EEE_POWER_MODE_SHIFT);
11596         if (eee_mode != PORT_FEAT_CFG_EEE_POWER_MODE_DISABLED) {
11597                 bp->link_params.eee_mode = EEE_MODE_ADV_LPI |
11598                                            EEE_MODE_ENABLE_LPI |
11599                                            EEE_MODE_OUTPUT_TIME;
11600         } else {
11601                 bp->link_params.eee_mode = 0;
11602         }
11603 }
11604
11605 void bnx2x_get_iscsi_info(struct bnx2x *bp)
11606 {
11607         u32 no_flags = NO_ISCSI_FLAG;
11608         int port = BP_PORT(bp);
11609         u32 max_iscsi_conn = FW_ENCODE_32BIT_PATTERN ^ SHMEM_RD(bp,
11610                                 drv_lic_key[port].max_iscsi_conn);
11611
11612         if (!CNIC_SUPPORT(bp)) {
11613                 bp->flags |= no_flags;
11614                 return;
11615         }
11616
11617         /* Get the number of maximum allowed iSCSI connections */
11618         bp->cnic_eth_dev.max_iscsi_conn =
11619                 (max_iscsi_conn & BNX2X_MAX_ISCSI_INIT_CONN_MASK) >>
11620                 BNX2X_MAX_ISCSI_INIT_CONN_SHIFT;
11621
11622         BNX2X_DEV_INFO("max_iscsi_conn 0x%x\n",
11623                        bp->cnic_eth_dev.max_iscsi_conn);
11624
11625         /*
11626          * If maximum allowed number of connections is zero -
11627          * disable the feature.
11628          */
11629         if (!bp->cnic_eth_dev.max_iscsi_conn)
11630                 bp->flags |= no_flags;
11631 }
11632
11633 static void bnx2x_get_ext_wwn_info(struct bnx2x *bp, int func)
11634 {
11635         /* Port info */
11636         bp->cnic_eth_dev.fcoe_wwn_port_name_hi =
11637                 MF_CFG_RD(bp, func_ext_config[func].fcoe_wwn_port_name_upper);
11638         bp->cnic_eth_dev.fcoe_wwn_port_name_lo =
11639                 MF_CFG_RD(bp, func_ext_config[func].fcoe_wwn_port_name_lower);
11640
11641         /* Node info */
11642         bp->cnic_eth_dev.fcoe_wwn_node_name_hi =
11643                 MF_CFG_RD(bp, func_ext_config[func].fcoe_wwn_node_name_upper);
11644         bp->cnic_eth_dev.fcoe_wwn_node_name_lo =
11645                 MF_CFG_RD(bp, func_ext_config[func].fcoe_wwn_node_name_lower);
11646 }
11647
11648 static int bnx2x_shared_fcoe_funcs(struct bnx2x *bp)
11649 {
11650         u8 count = 0;
11651
11652         if (IS_MF(bp)) {
11653                 u8 fid;
11654
11655                 /* iterate over absolute function ids for this path: */
11656                 for (fid = BP_PATH(bp); fid < E2_FUNC_MAX * 2; fid += 2) {
11657                         if (IS_MF_SD(bp)) {
11658                                 u32 cfg = MF_CFG_RD(bp,
11659                                                     func_mf_config[fid].config);
11660
11661                                 if (!(cfg & FUNC_MF_CFG_FUNC_HIDE) &&
11662                                     ((cfg & FUNC_MF_CFG_PROTOCOL_MASK) ==
11663                                             FUNC_MF_CFG_PROTOCOL_FCOE))
11664                                         count++;
11665                         } else {
11666                                 u32 cfg = MF_CFG_RD(bp,
11667                                                     func_ext_config[fid].
11668                                                                       func_cfg);
11669
11670                                 if ((cfg & MACP_FUNC_CFG_FLAGS_ENABLED) &&
11671                                     (cfg & MACP_FUNC_CFG_FLAGS_FCOE_OFFLOAD))
11672                                         count++;
11673                         }
11674                 }
11675         } else { /* SF */
11676                 int port, port_cnt = CHIP_MODE_IS_4_PORT(bp) ? 2 : 1;
11677
11678                 for (port = 0; port < port_cnt; port++) {
11679                         u32 lic = SHMEM_RD(bp,
11680                                            drv_lic_key[port].max_fcoe_conn) ^
11681                                   FW_ENCODE_32BIT_PATTERN;
11682                         if (lic)
11683                                 count++;
11684                 }
11685         }
11686
11687         return count;
11688 }
11689
11690 static void bnx2x_get_fcoe_info(struct bnx2x *bp)
11691 {
11692         int port = BP_PORT(bp);
11693         int func = BP_ABS_FUNC(bp);
11694         u32 max_fcoe_conn = FW_ENCODE_32BIT_PATTERN ^ SHMEM_RD(bp,
11695                                 drv_lic_key[port].max_fcoe_conn);
11696         u8 num_fcoe_func = bnx2x_shared_fcoe_funcs(bp);
11697
11698         if (!CNIC_SUPPORT(bp)) {
11699                 bp->flags |= NO_FCOE_FLAG;
11700                 return;
11701         }
11702
11703         /* Get the number of maximum allowed FCoE connections */
11704         bp->cnic_eth_dev.max_fcoe_conn =
11705                 (max_fcoe_conn & BNX2X_MAX_FCOE_INIT_CONN_MASK) >>
11706                 BNX2X_MAX_FCOE_INIT_CONN_SHIFT;
11707
11708         /* Calculate the number of maximum allowed FCoE tasks */
11709         bp->cnic_eth_dev.max_fcoe_exchanges = MAX_NUM_FCOE_TASKS_PER_ENGINE;
11710
11711         /* check if FCoE resources must be shared between different functions */
11712         if (num_fcoe_func)
11713                 bp->cnic_eth_dev.max_fcoe_exchanges /= num_fcoe_func;
11714
11715         /* Read the WWN: */
11716         if (!IS_MF(bp)) {
11717                 /* Port info */
11718                 bp->cnic_eth_dev.fcoe_wwn_port_name_hi =
11719                         SHMEM_RD(bp,
11720                                  dev_info.port_hw_config[port].
11721                                  fcoe_wwn_port_name_upper);
11722                 bp->cnic_eth_dev.fcoe_wwn_port_name_lo =
11723                         SHMEM_RD(bp,
11724                                  dev_info.port_hw_config[port].
11725                                  fcoe_wwn_port_name_lower);
11726
11727                 /* Node info */
11728                 bp->cnic_eth_dev.fcoe_wwn_node_name_hi =
11729                         SHMEM_RD(bp,
11730                                  dev_info.port_hw_config[port].
11731                                  fcoe_wwn_node_name_upper);
11732                 bp->cnic_eth_dev.fcoe_wwn_node_name_lo =
11733                         SHMEM_RD(bp,
11734                                  dev_info.port_hw_config[port].
11735                                  fcoe_wwn_node_name_lower);
11736         } else if (!IS_MF_SD(bp)) {
11737                 /* Read the WWN info only if the FCoE feature is enabled for
11738                  * this function.
11739                  */
11740                 if (BNX2X_HAS_MF_EXT_PROTOCOL_FCOE(bp))
11741                         bnx2x_get_ext_wwn_info(bp, func);
11742         } else {
11743                 if (BNX2X_IS_MF_SD_PROTOCOL_FCOE(bp) && !CHIP_IS_E1x(bp))
11744                         bnx2x_get_ext_wwn_info(bp, func);
11745         }
11746
11747         BNX2X_DEV_INFO("max_fcoe_conn 0x%x\n", bp->cnic_eth_dev.max_fcoe_conn);
11748
11749         /*
11750          * If maximum allowed number of connections is zero -
11751          * disable the feature.
11752          */
11753         if (!bp->cnic_eth_dev.max_fcoe_conn)
11754                 bp->flags |= NO_FCOE_FLAG;
11755 }
11756
11757 static void bnx2x_get_cnic_info(struct bnx2x *bp)
11758 {
11759         /*
11760          * iSCSI may be dynamically disabled but reading
11761          * info here we will decrease memory usage by driver
11762          * if the feature is disabled for good
11763          */
11764         bnx2x_get_iscsi_info(bp);
11765         bnx2x_get_fcoe_info(bp);
11766 }
11767
11768 static void bnx2x_get_cnic_mac_hwinfo(struct bnx2x *bp)
11769 {
11770         u32 val, val2;
11771         int func = BP_ABS_FUNC(bp);
11772         int port = BP_PORT(bp);
11773         u8 *iscsi_mac = bp->cnic_eth_dev.iscsi_mac;
11774         u8 *fip_mac = bp->fip_mac;
11775
11776         if (IS_MF(bp)) {
11777                 /* iSCSI and FCoE NPAR MACs: if there is no either iSCSI or
11778                  * FCoE MAC then the appropriate feature should be disabled.
11779                  * In non SD mode features configuration comes from struct
11780                  * func_ext_config.
11781                  */
11782                 if (!IS_MF_SD(bp)) {
11783                         u32 cfg = MF_CFG_RD(bp, func_ext_config[func].func_cfg);
11784                         if (cfg & MACP_FUNC_CFG_FLAGS_ISCSI_OFFLOAD) {
11785                                 val2 = MF_CFG_RD(bp, func_ext_config[func].
11786                                                  iscsi_mac_addr_upper);
11787                                 val = MF_CFG_RD(bp, func_ext_config[func].
11788                                                 iscsi_mac_addr_lower);
11789                                 bnx2x_set_mac_buf(iscsi_mac, val, val2);
11790                                 BNX2X_DEV_INFO
11791                                         ("Read iSCSI MAC: %pM\n", iscsi_mac);
11792                         } else {
11793                                 bp->flags |= NO_ISCSI_OOO_FLAG | NO_ISCSI_FLAG;
11794                         }
11795
11796                         if (cfg & MACP_FUNC_CFG_FLAGS_FCOE_OFFLOAD) {
11797                                 val2 = MF_CFG_RD(bp, func_ext_config[func].
11798                                                  fcoe_mac_addr_upper);
11799                                 val = MF_CFG_RD(bp, func_ext_config[func].
11800                                                 fcoe_mac_addr_lower);
11801                                 bnx2x_set_mac_buf(fip_mac, val, val2);
11802                                 BNX2X_DEV_INFO
11803                                         ("Read FCoE L2 MAC: %pM\n", fip_mac);
11804                         } else {
11805                                 bp->flags |= NO_FCOE_FLAG;
11806                         }
11807
11808                         bp->mf_ext_config = cfg;
11809
11810                 } else { /* SD MODE */
11811                         if (BNX2X_IS_MF_SD_PROTOCOL_ISCSI(bp)) {
11812                                 /* use primary mac as iscsi mac */
11813                                 memcpy(iscsi_mac, bp->dev->dev_addr, ETH_ALEN);
11814
11815                                 BNX2X_DEV_INFO("SD ISCSI MODE\n");
11816                                 BNX2X_DEV_INFO
11817                                         ("Read iSCSI MAC: %pM\n", iscsi_mac);
11818                         } else if (BNX2X_IS_MF_SD_PROTOCOL_FCOE(bp)) {
11819                                 /* use primary mac as fip mac */
11820                                 memcpy(fip_mac, bp->dev->dev_addr, ETH_ALEN);
11821                                 BNX2X_DEV_INFO("SD FCoE MODE\n");
11822                                 BNX2X_DEV_INFO
11823                                         ("Read FIP MAC: %pM\n", fip_mac);
11824                         }
11825                 }
11826
11827                 /* If this is a storage-only interface, use SAN mac as
11828                  * primary MAC. Notice that for SD this is already the case,
11829                  * as the SAN mac was copied from the primary MAC.
11830                  */
11831                 if (IS_MF_FCOE_AFEX(bp))
11832                         memcpy(bp->dev->dev_addr, fip_mac, ETH_ALEN);
11833         } else {
11834                 val2 = SHMEM_RD(bp, dev_info.port_hw_config[port].
11835                                 iscsi_mac_upper);
11836                 val = SHMEM_RD(bp, dev_info.port_hw_config[port].
11837                                iscsi_mac_lower);
11838                 bnx2x_set_mac_buf(iscsi_mac, val, val2);
11839
11840                 val2 = SHMEM_RD(bp, dev_info.port_hw_config[port].
11841                                 fcoe_fip_mac_upper);
11842                 val = SHMEM_RD(bp, dev_info.port_hw_config[port].
11843                                fcoe_fip_mac_lower);
11844                 bnx2x_set_mac_buf(fip_mac, val, val2);
11845         }
11846
11847         /* Disable iSCSI OOO if MAC configuration is invalid. */
11848         if (!is_valid_ether_addr(iscsi_mac)) {
11849                 bp->flags |= NO_ISCSI_OOO_FLAG | NO_ISCSI_FLAG;
11850                 eth_zero_addr(iscsi_mac);
11851         }
11852
11853         /* Disable FCoE if MAC configuration is invalid. */
11854         if (!is_valid_ether_addr(fip_mac)) {
11855                 bp->flags |= NO_FCOE_FLAG;
11856                 eth_zero_addr(bp->fip_mac);
11857         }
11858 }
11859
11860 static void bnx2x_get_mac_hwinfo(struct bnx2x *bp)
11861 {
11862         u32 val, val2;
11863         int func = BP_ABS_FUNC(bp);
11864         int port = BP_PORT(bp);
11865
11866         /* Zero primary MAC configuration */
11867         eth_zero_addr(bp->dev->dev_addr);
11868
11869         if (BP_NOMCP(bp)) {
11870                 BNX2X_ERROR("warning: random MAC workaround active\n");
11871                 eth_hw_addr_random(bp->dev);
11872         } else if (IS_MF(bp)) {
11873                 val2 = MF_CFG_RD(bp, func_mf_config[func].mac_upper);
11874                 val = MF_CFG_RD(bp, func_mf_config[func].mac_lower);
11875                 if ((val2 != FUNC_MF_CFG_UPPERMAC_DEFAULT) &&
11876                     (val != FUNC_MF_CFG_LOWERMAC_DEFAULT))
11877                         bnx2x_set_mac_buf(bp->dev->dev_addr, val, val2);
11878
11879                 if (CNIC_SUPPORT(bp))
11880                         bnx2x_get_cnic_mac_hwinfo(bp);
11881         } else {
11882                 /* in SF read MACs from port configuration */
11883                 val2 = SHMEM_RD(bp, dev_info.port_hw_config[port].mac_upper);
11884                 val = SHMEM_RD(bp, dev_info.port_hw_config[port].mac_lower);
11885                 bnx2x_set_mac_buf(bp->dev->dev_addr, val, val2);
11886
11887                 if (CNIC_SUPPORT(bp))
11888                         bnx2x_get_cnic_mac_hwinfo(bp);
11889         }
11890
11891         if (!BP_NOMCP(bp)) {
11892                 /* Read physical port identifier from shmem */
11893                 val2 = SHMEM_RD(bp, dev_info.port_hw_config[port].mac_upper);
11894                 val = SHMEM_RD(bp, dev_info.port_hw_config[port].mac_lower);
11895                 bnx2x_set_mac_buf(bp->phys_port_id, val, val2);
11896                 bp->flags |= HAS_PHYS_PORT_ID;
11897         }
11898
11899         memcpy(bp->link_params.mac_addr, bp->dev->dev_addr, ETH_ALEN);
11900
11901         if (!is_valid_ether_addr(bp->dev->dev_addr))
11902                 dev_err(&bp->pdev->dev,
11903                         "bad Ethernet MAC address configuration: %pM\n"
11904                         "change it manually before bringing up the appropriate network interface\n",
11905                         bp->dev->dev_addr);
11906 }
11907
11908 static bool bnx2x_get_dropless_info(struct bnx2x *bp)
11909 {
11910         int tmp;
11911         u32 cfg;
11912
11913         if (IS_VF(bp))
11914                 return false;
11915
11916         if (IS_MF(bp) && !CHIP_IS_E1x(bp)) {
11917                 /* Take function: tmp = func */
11918                 tmp = BP_ABS_FUNC(bp);
11919                 cfg = MF_CFG_RD(bp, func_ext_config[tmp].func_cfg);
11920                 cfg = !!(cfg & MACP_FUNC_CFG_PAUSE_ON_HOST_RING);
11921         } else {
11922                 /* Take port: tmp = port */
11923                 tmp = BP_PORT(bp);
11924                 cfg = SHMEM_RD(bp,
11925                                dev_info.port_hw_config[tmp].generic_features);
11926                 cfg = !!(cfg & PORT_HW_CFG_PAUSE_ON_HOST_RING_ENABLED);
11927         }
11928         return cfg;
11929 }
11930
11931 static void validate_set_si_mode(struct bnx2x *bp)
11932 {
11933         u8 func = BP_ABS_FUNC(bp);
11934         u32 val;
11935
11936         val = MF_CFG_RD(bp, func_mf_config[func].mac_upper);
11937
11938         /* check for legal mac (upper bytes) */
11939         if (val != 0xffff) {
11940                 bp->mf_mode = MULTI_FUNCTION_SI;
11941                 bp->mf_config[BP_VN(bp)] =
11942                         MF_CFG_RD(bp, func_mf_config[func].config);
11943         } else
11944                 BNX2X_DEV_INFO("illegal MAC address for SI\n");
11945 }
11946
11947 static int bnx2x_get_hwinfo(struct bnx2x *bp)
11948 {
11949         int /*abs*/func = BP_ABS_FUNC(bp);
11950         int vn, mfw_vn;
11951         u32 val = 0, val2 = 0;
11952         int rc = 0;
11953
11954         /* Validate that chip access is feasible */
11955         if (REG_RD(bp, MISC_REG_CHIP_NUM) == 0xffffffff) {
11956                 dev_err(&bp->pdev->dev,
11957                         "Chip read returns all Fs. Preventing probe from continuing\n");
11958                 return -EINVAL;
11959         }
11960
11961         bnx2x_get_common_hwinfo(bp);
11962
11963         /*
11964          * initialize IGU parameters
11965          */
11966         if (CHIP_IS_E1x(bp)) {
11967                 bp->common.int_block = INT_BLOCK_HC;
11968
11969                 bp->igu_dsb_id = DEF_SB_IGU_ID;
11970                 bp->igu_base_sb = 0;
11971         } else {
11972                 bp->common.int_block = INT_BLOCK_IGU;
11973
11974                 /* do not allow device reset during IGU info processing */
11975                 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_RESET);
11976
11977                 val = REG_RD(bp, IGU_REG_BLOCK_CONFIGURATION);
11978
11979                 if (val & IGU_BLOCK_CONFIGURATION_REG_BACKWARD_COMP_EN) {
11980                         int tout = 5000;
11981
11982                         BNX2X_DEV_INFO("FORCING Normal Mode\n");
11983
11984                         val &= ~(IGU_BLOCK_CONFIGURATION_REG_BACKWARD_COMP_EN);
11985                         REG_WR(bp, IGU_REG_BLOCK_CONFIGURATION, val);
11986                         REG_WR(bp, IGU_REG_RESET_MEMORIES, 0x7f);
11987
11988                         while (tout && REG_RD(bp, IGU_REG_RESET_MEMORIES)) {
11989                                 tout--;
11990                                 usleep_range(1000, 2000);
11991                         }
11992
11993                         if (REG_RD(bp, IGU_REG_RESET_MEMORIES)) {
11994                                 dev_err(&bp->pdev->dev,
11995                                         "FORCING Normal Mode failed!!!\n");
11996                                 bnx2x_release_hw_lock(bp,
11997                                                       HW_LOCK_RESOURCE_RESET);
11998                                 return -EPERM;
11999                         }
12000                 }
12001
12002                 if (val & IGU_BLOCK_CONFIGURATION_REG_BACKWARD_COMP_EN) {
12003                         BNX2X_DEV_INFO("IGU Backward Compatible Mode\n");
12004                         bp->common.int_block |= INT_BLOCK_MODE_BW_COMP;
12005                 } else
12006                         BNX2X_DEV_INFO("IGU Normal Mode\n");
12007
12008                 rc = bnx2x_get_igu_cam_info(bp);
12009                 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_RESET);
12010                 if (rc)
12011                         return rc;
12012         }
12013
12014         /*
12015          * set base FW non-default (fast path) status block id, this value is
12016          * used to initialize the fw_sb_id saved on the fp/queue structure to
12017          * determine the id used by the FW.
12018          */
12019         if (CHIP_IS_E1x(bp))
12020                 bp->base_fw_ndsb = BP_PORT(bp) * FP_SB_MAX_E1x + BP_L_ID(bp);
12021         else /*
12022               * 57712 - we currently use one FW SB per IGU SB (Rx and Tx of
12023               * the same queue are indicated on the same IGU SB). So we prefer
12024               * FW and IGU SBs to be the same value.
12025               */
12026                 bp->base_fw_ndsb = bp->igu_base_sb;
12027
12028         BNX2X_DEV_INFO("igu_dsb_id %d  igu_base_sb %d  igu_sb_cnt %d\n"
12029                        "base_fw_ndsb %d\n", bp->igu_dsb_id, bp->igu_base_sb,
12030                        bp->igu_sb_cnt, bp->base_fw_ndsb);
12031
12032         /*
12033          * Initialize MF configuration
12034          */
12035
12036         bp->mf_ov = 0;
12037         bp->mf_mode = 0;
12038         bp->mf_sub_mode = 0;
12039         vn = BP_VN(bp);
12040         mfw_vn = BP_FW_MB_IDX(bp);
12041
12042         if (!CHIP_IS_E1(bp) && !BP_NOMCP(bp)) {
12043                 BNX2X_DEV_INFO("shmem2base 0x%x, size %d, mfcfg offset %d\n",
12044                                bp->common.shmem2_base, SHMEM2_RD(bp, size),
12045                               (u32)offsetof(struct shmem2_region, mf_cfg_addr));
12046
12047                 if (SHMEM2_HAS(bp, mf_cfg_addr))
12048                         bp->common.mf_cfg_base = SHMEM2_RD(bp, mf_cfg_addr);
12049                 else
12050                         bp->common.mf_cfg_base = bp->common.shmem_base +
12051                                 offsetof(struct shmem_region, func_mb) +
12052                                 E1H_FUNC_MAX * sizeof(struct drv_func_mb);
12053                 /*
12054                  * get mf configuration:
12055                  * 1. Existence of MF configuration
12056                  * 2. MAC address must be legal (check only upper bytes)
12057                  *    for  Switch-Independent mode;
12058                  *    OVLAN must be legal for Switch-Dependent mode
12059                  * 3. SF_MODE configures specific MF mode
12060                  */
12061                 if (bp->common.mf_cfg_base != SHMEM_MF_CFG_ADDR_NONE) {
12062                         /* get mf configuration */
12063                         val = SHMEM_RD(bp,
12064                                        dev_info.shared_feature_config.config);
12065                         val &= SHARED_FEAT_CFG_FORCE_SF_MODE_MASK;
12066
12067                         switch (val) {
12068                         case SHARED_FEAT_CFG_FORCE_SF_MODE_SWITCH_INDEPT:
12069                                 validate_set_si_mode(bp);
12070                                 break;
12071                         case SHARED_FEAT_CFG_FORCE_SF_MODE_AFEX_MODE:
12072                                 if ((!CHIP_IS_E1x(bp)) &&
12073                                     (MF_CFG_RD(bp, func_mf_config[func].
12074                                                mac_upper) != 0xffff) &&
12075                                     (SHMEM2_HAS(bp,
12076                                                 afex_driver_support))) {
12077                                         bp->mf_mode = MULTI_FUNCTION_AFEX;
12078                                         bp->mf_config[vn] = MF_CFG_RD(bp,
12079                                                 func_mf_config[func].config);
12080                                 } else {
12081                                         BNX2X_DEV_INFO("can not configure afex mode\n");
12082                                 }
12083                                 break;
12084                         case SHARED_FEAT_CFG_FORCE_SF_MODE_MF_ALLOWED:
12085                                 /* get OV configuration */
12086                                 val = MF_CFG_RD(bp,
12087                                         func_mf_config[FUNC_0].e1hov_tag);
12088                                 val &= FUNC_MF_CFG_E1HOV_TAG_MASK;
12089
12090                                 if (val != FUNC_MF_CFG_E1HOV_TAG_DEFAULT) {
12091                                         bp->mf_mode = MULTI_FUNCTION_SD;
12092                                         bp->mf_config[vn] = MF_CFG_RD(bp,
12093                                                 func_mf_config[func].config);
12094                                 } else
12095                                         BNX2X_DEV_INFO("illegal OV for SD\n");
12096                                 break;
12097                         case SHARED_FEAT_CFG_FORCE_SF_MODE_BD_MODE:
12098                                 bp->mf_mode = MULTI_FUNCTION_SD;
12099                                 bp->mf_sub_mode = SUB_MF_MODE_BD;
12100                                 bp->mf_config[vn] =
12101                                         MF_CFG_RD(bp,
12102                                                   func_mf_config[func].config);
12103
12104                                 if (SHMEM2_HAS(bp, mtu_size)) {
12105                                         int mtu_idx = BP_FW_MB_IDX(bp);
12106                                         u16 mtu_size;
12107                                         u32 mtu;
12108
12109                                         mtu = SHMEM2_RD(bp, mtu_size[mtu_idx]);
12110                                         mtu_size = (u16)mtu;
12111                                         DP(NETIF_MSG_IFUP, "Read MTU size %04x [%08x]\n",
12112                                            mtu_size, mtu);
12113
12114                                         /* if valid: update device mtu */
12115                                         if ((mtu_size >= ETH_MIN_PACKET_SIZE) &&
12116                                             (mtu_size <=
12117                                              ETH_MAX_JUMBO_PACKET_SIZE))
12118                                                 bp->dev->mtu = mtu_size;
12119                                 }
12120                                 break;
12121                         case SHARED_FEAT_CFG_FORCE_SF_MODE_UFP_MODE:
12122                                 bp->mf_mode = MULTI_FUNCTION_SD;
12123                                 bp->mf_sub_mode = SUB_MF_MODE_UFP;
12124                                 bp->mf_config[vn] =
12125                                         MF_CFG_RD(bp,
12126                                                   func_mf_config[func].config);
12127                                 break;
12128                         case SHARED_FEAT_CFG_FORCE_SF_MODE_FORCED_SF:
12129                                 bp->mf_config[vn] = 0;
12130                                 break;
12131                         case SHARED_FEAT_CFG_FORCE_SF_MODE_EXTENDED_MODE:
12132                                 val2 = SHMEM_RD(bp,
12133                                         dev_info.shared_hw_config.config_3);
12134                                 val2 &= SHARED_HW_CFG_EXTENDED_MF_MODE_MASK;
12135                                 switch (val2) {
12136                                 case SHARED_HW_CFG_EXTENDED_MF_MODE_NPAR1_DOT_5:
12137                                         validate_set_si_mode(bp);
12138                                         bp->mf_sub_mode =
12139                                                         SUB_MF_MODE_NPAR1_DOT_5;
12140                                         break;
12141                                 default:
12142                                         /* Unknown configuration */
12143                                         bp->mf_config[vn] = 0;
12144                                         BNX2X_DEV_INFO("unknown extended MF mode 0x%x\n",
12145                                                        val);
12146                                 }
12147                                 break;
12148                         default:
12149                                 /* Unknown configuration: reset mf_config */
12150                                 bp->mf_config[vn] = 0;
12151                                 BNX2X_DEV_INFO("unknown MF mode 0x%x\n", val);
12152                         }
12153                 }
12154
12155                 BNX2X_DEV_INFO("%s function mode\n",
12156                                IS_MF(bp) ? "multi" : "single");
12157
12158                 switch (bp->mf_mode) {
12159                 case MULTI_FUNCTION_SD:
12160                         val = MF_CFG_RD(bp, func_mf_config[func].e1hov_tag) &
12161                               FUNC_MF_CFG_E1HOV_TAG_MASK;
12162                         if (val != FUNC_MF_CFG_E1HOV_TAG_DEFAULT) {
12163                                 bp->mf_ov = val;
12164                                 bp->path_has_ovlan = true;
12165
12166                                 BNX2X_DEV_INFO("MF OV for func %d is %d (0x%04x)\n",
12167                                                func, bp->mf_ov, bp->mf_ov);
12168                         } else if ((bp->mf_sub_mode == SUB_MF_MODE_UFP) ||
12169                                    (bp->mf_sub_mode == SUB_MF_MODE_BD)) {
12170                                 dev_err(&bp->pdev->dev,
12171                                         "Unexpected - no valid MF OV for func %d in UFP/BD mode\n",
12172                                         func);
12173                                 bp->path_has_ovlan = true;
12174                         } else {
12175                                 dev_err(&bp->pdev->dev,
12176                                         "No valid MF OV for func %d, aborting\n",
12177                                         func);
12178                                 return -EPERM;
12179                         }
12180                         break;
12181                 case MULTI_FUNCTION_AFEX:
12182                         BNX2X_DEV_INFO("func %d is in MF afex mode\n", func);
12183                         break;
12184                 case MULTI_FUNCTION_SI:
12185                         BNX2X_DEV_INFO("func %d is in MF switch-independent mode\n",
12186                                        func);
12187                         break;
12188                 default:
12189                         if (vn) {
12190                                 dev_err(&bp->pdev->dev,
12191                                         "VN %d is in a single function mode, aborting\n",
12192                                         vn);
12193                                 return -EPERM;
12194                         }
12195                         break;
12196                 }
12197
12198                 /* check if other port on the path needs ovlan:
12199                  * Since MF configuration is shared between ports
12200                  * Possible mixed modes are only
12201                  * {SF, SI} {SF, SD} {SD, SF} {SI, SF}
12202                  */
12203                 if (CHIP_MODE_IS_4_PORT(bp) &&
12204                     !bp->path_has_ovlan &&
12205                     !IS_MF(bp) &&
12206                     bp->common.mf_cfg_base != SHMEM_MF_CFG_ADDR_NONE) {
12207                         u8 other_port = !BP_PORT(bp);
12208                         u8 other_func = BP_PATH(bp) + 2*other_port;
12209                         val = MF_CFG_RD(bp,
12210                                         func_mf_config[other_func].e1hov_tag);
12211                         if (val != FUNC_MF_CFG_E1HOV_TAG_DEFAULT)
12212                                 bp->path_has_ovlan = true;
12213                 }
12214         }
12215
12216         /* adjust igu_sb_cnt to MF for E1H */
12217         if (CHIP_IS_E1H(bp) && IS_MF(bp))
12218                 bp->igu_sb_cnt = min_t(u8, bp->igu_sb_cnt, E1H_MAX_MF_SB_COUNT);
12219
12220         /* port info */
12221         bnx2x_get_port_hwinfo(bp);
12222
12223         /* Get MAC addresses */
12224         bnx2x_get_mac_hwinfo(bp);
12225
12226         bnx2x_get_cnic_info(bp);
12227
12228         return rc;
12229 }
12230
12231 static void bnx2x_read_fwinfo(struct bnx2x *bp)
12232 {
12233         int cnt, i, block_end, rodi;
12234         char vpd_start[BNX2X_VPD_LEN+1];
12235         char str_id_reg[VENDOR_ID_LEN+1];
12236         char str_id_cap[VENDOR_ID_LEN+1];
12237         char *vpd_data;
12238         char *vpd_extended_data = NULL;
12239         u8 len;
12240
12241         cnt = pci_read_vpd(bp->pdev, 0, BNX2X_VPD_LEN, vpd_start);
12242         memset(bp->fw_ver, 0, sizeof(bp->fw_ver));
12243
12244         if (cnt < BNX2X_VPD_LEN)
12245                 goto out_not_found;
12246
12247         /* VPD RO tag should be first tag after identifier string, hence
12248          * we should be able to find it in first BNX2X_VPD_LEN chars
12249          */
12250         i = pci_vpd_find_tag(vpd_start, 0, BNX2X_VPD_LEN,
12251                              PCI_VPD_LRDT_RO_DATA);
12252         if (i < 0)
12253                 goto out_not_found;
12254
12255         block_end = i + PCI_VPD_LRDT_TAG_SIZE +
12256                     pci_vpd_lrdt_size(&vpd_start[i]);
12257
12258         i += PCI_VPD_LRDT_TAG_SIZE;
12259
12260         if (block_end > BNX2X_VPD_LEN) {
12261                 vpd_extended_data = kmalloc(block_end, GFP_KERNEL);
12262                 if (vpd_extended_data  == NULL)
12263                         goto out_not_found;
12264
12265                 /* read rest of vpd image into vpd_extended_data */
12266                 memcpy(vpd_extended_data, vpd_start, BNX2X_VPD_LEN);
12267                 cnt = pci_read_vpd(bp->pdev, BNX2X_VPD_LEN,
12268                                    block_end - BNX2X_VPD_LEN,
12269                                    vpd_extended_data + BNX2X_VPD_LEN);
12270                 if (cnt < (block_end - BNX2X_VPD_LEN))
12271                         goto out_not_found;
12272                 vpd_data = vpd_extended_data;
12273         } else
12274                 vpd_data = vpd_start;
12275
12276         /* now vpd_data holds full vpd content in both cases */
12277
12278         rodi = pci_vpd_find_info_keyword(vpd_data, i, block_end,
12279                                    PCI_VPD_RO_KEYWORD_MFR_ID);
12280         if (rodi < 0)
12281                 goto out_not_found;
12282
12283         len = pci_vpd_info_field_size(&vpd_data[rodi]);
12284
12285         if (len != VENDOR_ID_LEN)
12286                 goto out_not_found;
12287
12288         rodi += PCI_VPD_INFO_FLD_HDR_SIZE;
12289
12290         /* vendor specific info */
12291         snprintf(str_id_reg, VENDOR_ID_LEN + 1, "%04x", PCI_VENDOR_ID_DELL);
12292         snprintf(str_id_cap, VENDOR_ID_LEN + 1, "%04X", PCI_VENDOR_ID_DELL);
12293         if (!strncmp(str_id_reg, &vpd_data[rodi], VENDOR_ID_LEN) ||
12294             !strncmp(str_id_cap, &vpd_data[rodi], VENDOR_ID_LEN)) {
12295
12296                 rodi = pci_vpd_find_info_keyword(vpd_data, i, block_end,
12297                                                 PCI_VPD_RO_KEYWORD_VENDOR0);
12298                 if (rodi >= 0) {
12299                         len = pci_vpd_info_field_size(&vpd_data[rodi]);
12300
12301                         rodi += PCI_VPD_INFO_FLD_HDR_SIZE;
12302
12303                         if (len < 32 && (len + rodi) <= BNX2X_VPD_LEN) {
12304                                 memcpy(bp->fw_ver, &vpd_data[rodi], len);
12305                                 bp->fw_ver[len] = ' ';
12306                         }
12307                 }
12308                 kfree(vpd_extended_data);
12309                 return;
12310         }
12311 out_not_found:
12312         kfree(vpd_extended_data);
12313         return;
12314 }
12315
12316 static void bnx2x_set_modes_bitmap(struct bnx2x *bp)
12317 {
12318         u32 flags = 0;
12319
12320         if (CHIP_REV_IS_FPGA(bp))
12321                 SET_FLAGS(flags, MODE_FPGA);
12322         else if (CHIP_REV_IS_EMUL(bp))
12323                 SET_FLAGS(flags, MODE_EMUL);
12324         else
12325                 SET_FLAGS(flags, MODE_ASIC);
12326
12327         if (CHIP_MODE_IS_4_PORT(bp))
12328                 SET_FLAGS(flags, MODE_PORT4);
12329         else
12330                 SET_FLAGS(flags, MODE_PORT2);
12331
12332         if (CHIP_IS_E2(bp))
12333                 SET_FLAGS(flags, MODE_E2);
12334         else if (CHIP_IS_E3(bp)) {
12335                 SET_FLAGS(flags, MODE_E3);
12336                 if (CHIP_REV(bp) == CHIP_REV_Ax)
12337                         SET_FLAGS(flags, MODE_E3_A0);
12338                 else /*if (CHIP_REV(bp) == CHIP_REV_Bx)*/
12339                         SET_FLAGS(flags, MODE_E3_B0 | MODE_COS3);
12340         }
12341
12342         if (IS_MF(bp)) {
12343                 SET_FLAGS(flags, MODE_MF);
12344                 switch (bp->mf_mode) {
12345                 case MULTI_FUNCTION_SD:
12346                         SET_FLAGS(flags, MODE_MF_SD);
12347                         break;
12348                 case MULTI_FUNCTION_SI:
12349                         SET_FLAGS(flags, MODE_MF_SI);
12350                         break;
12351                 case MULTI_FUNCTION_AFEX:
12352                         SET_FLAGS(flags, MODE_MF_AFEX);
12353                         break;
12354                 }
12355         } else
12356                 SET_FLAGS(flags, MODE_SF);
12357
12358 #if defined(__LITTLE_ENDIAN)
12359         SET_FLAGS(flags, MODE_LITTLE_ENDIAN);
12360 #else /*(__BIG_ENDIAN)*/
12361         SET_FLAGS(flags, MODE_BIG_ENDIAN);
12362 #endif
12363         INIT_MODE_FLAGS(bp) = flags;
12364 }
12365
12366 static int bnx2x_init_bp(struct bnx2x *bp)
12367 {
12368         int func;
12369         int rc;
12370
12371         mutex_init(&bp->port.phy_mutex);
12372         mutex_init(&bp->fw_mb_mutex);
12373         mutex_init(&bp->drv_info_mutex);
12374         sema_init(&bp->stats_lock, 1);
12375         bp->drv_info_mng_owner = false;
12376         INIT_LIST_HEAD(&bp->vlan_reg);
12377
12378         INIT_DELAYED_WORK(&bp->sp_task, bnx2x_sp_task);
12379         INIT_DELAYED_WORK(&bp->sp_rtnl_task, bnx2x_sp_rtnl_task);
12380         INIT_DELAYED_WORK(&bp->period_task, bnx2x_period_task);
12381         INIT_DELAYED_WORK(&bp->iov_task, bnx2x_iov_task);
12382         if (IS_PF(bp)) {
12383                 rc = bnx2x_get_hwinfo(bp);
12384                 if (rc)
12385                         return rc;
12386         } else {
12387                 eth_zero_addr(bp->dev->dev_addr);
12388         }
12389
12390         bnx2x_set_modes_bitmap(bp);
12391
12392         rc = bnx2x_alloc_mem_bp(bp);
12393         if (rc)
12394                 return rc;
12395
12396         bnx2x_read_fwinfo(bp);
12397
12398         func = BP_FUNC(bp);
12399
12400         /* need to reset chip if undi was active */
12401         if (IS_PF(bp) && !BP_NOMCP(bp)) {
12402                 /* init fw_seq */
12403                 bp->fw_seq =
12404                         SHMEM_RD(bp, func_mb[BP_FW_MB_IDX(bp)].drv_mb_header) &
12405                                                         DRV_MSG_SEQ_NUMBER_MASK;
12406                 BNX2X_DEV_INFO("fw_seq 0x%08x\n", bp->fw_seq);
12407
12408                 rc = bnx2x_prev_unload(bp);
12409                 if (rc) {
12410                         bnx2x_free_mem_bp(bp);
12411                         return rc;
12412                 }
12413         }
12414
12415         if (CHIP_REV_IS_FPGA(bp))
12416                 dev_err(&bp->pdev->dev, "FPGA detected\n");
12417
12418         if (BP_NOMCP(bp) && (func == 0))
12419                 dev_err(&bp->pdev->dev, "MCP disabled, must load devices in order!\n");
12420
12421         bp->disable_tpa = disable_tpa;
12422         bp->disable_tpa |= !!IS_MF_STORAGE_ONLY(bp);
12423         /* Reduce memory usage in kdump environment by disabling TPA */
12424         bp->disable_tpa |= is_kdump_kernel();
12425
12426         /* Set TPA flags */
12427         if (bp->disable_tpa) {
12428                 bp->dev->hw_features &= ~(NETIF_F_LRO | NETIF_F_GRO_HW);
12429                 bp->dev->features &= ~(NETIF_F_LRO | NETIF_F_GRO_HW);
12430         }
12431
12432         if (CHIP_IS_E1(bp))
12433                 bp->dropless_fc = 0;
12434         else
12435                 bp->dropless_fc = dropless_fc | bnx2x_get_dropless_info(bp);
12436
12437         bp->mrrs = mrrs;
12438
12439         bp->tx_ring_size = IS_MF_STORAGE_ONLY(bp) ? 0 : MAX_TX_AVAIL;
12440         if (IS_VF(bp))
12441                 bp->rx_ring_size = MAX_RX_AVAIL;
12442
12443         /* make sure that the numbers are in the right granularity */
12444         bp->tx_ticks = (50 / BNX2X_BTR) * BNX2X_BTR;
12445         bp->rx_ticks = (25 / BNX2X_BTR) * BNX2X_BTR;
12446
12447         bp->current_interval = CHIP_REV_IS_SLOW(bp) ? 5*HZ : HZ;
12448
12449         timer_setup(&bp->timer, bnx2x_timer, 0);
12450         bp->timer.expires = jiffies + bp->current_interval;
12451
12452         if (SHMEM2_HAS(bp, dcbx_lldp_params_offset) &&
12453             SHMEM2_HAS(bp, dcbx_lldp_dcbx_stat_offset) &&
12454             SHMEM2_HAS(bp, dcbx_en) &&
12455             SHMEM2_RD(bp, dcbx_lldp_params_offset) &&
12456             SHMEM2_RD(bp, dcbx_lldp_dcbx_stat_offset) &&
12457             SHMEM2_RD(bp, dcbx_en[BP_PORT(bp)])) {
12458                 bnx2x_dcbx_set_state(bp, true, BNX2X_DCBX_ENABLED_ON_NEG_ON);
12459                 bnx2x_dcbx_init_params(bp);
12460         } else {
12461                 bnx2x_dcbx_set_state(bp, false, BNX2X_DCBX_ENABLED_OFF);
12462         }
12463
12464         if (CHIP_IS_E1x(bp))
12465                 bp->cnic_base_cl_id = FP_SB_MAX_E1x;
12466         else
12467                 bp->cnic_base_cl_id = FP_SB_MAX_E2;
12468
12469         /* multiple tx priority */
12470         if (IS_VF(bp))
12471                 bp->max_cos = 1;
12472         else if (CHIP_IS_E1x(bp))
12473                 bp->max_cos = BNX2X_MULTI_TX_COS_E1X;
12474         else if (CHIP_IS_E2(bp) || CHIP_IS_E3A0(bp))
12475                 bp->max_cos = BNX2X_MULTI_TX_COS_E2_E3A0;
12476         else if (CHIP_IS_E3B0(bp))
12477                 bp->max_cos = BNX2X_MULTI_TX_COS_E3B0;
12478         else
12479                 BNX2X_ERR("unknown chip %x revision %x\n",
12480                           CHIP_NUM(bp), CHIP_REV(bp));
12481         BNX2X_DEV_INFO("set bp->max_cos to %d\n", bp->max_cos);
12482
12483         /* We need at least one default status block for slow-path events,
12484          * second status block for the L2 queue, and a third status block for
12485          * CNIC if supported.
12486          */
12487         if (IS_VF(bp))
12488                 bp->min_msix_vec_cnt = 1;
12489         else if (CNIC_SUPPORT(bp))
12490                 bp->min_msix_vec_cnt = 3;
12491         else /* PF w/o cnic */
12492                 bp->min_msix_vec_cnt = 2;
12493         BNX2X_DEV_INFO("bp->min_msix_vec_cnt %d", bp->min_msix_vec_cnt);
12494
12495         bp->dump_preset_idx = 1;
12496
12497         if (CHIP_IS_E3B0(bp))
12498                 bp->flags |= PTP_SUPPORTED;
12499
12500         return rc;
12501 }
12502
12503 /****************************************************************************
12504 * General service functions
12505 ****************************************************************************/
12506
12507 /*
12508  * net_device service functions
12509  */
12510
12511 /* called with rtnl_lock */
12512 static int bnx2x_open(struct net_device *dev)
12513 {
12514         struct bnx2x *bp = netdev_priv(dev);
12515         int rc;
12516
12517         bp->stats_init = true;
12518
12519         netif_carrier_off(dev);
12520
12521         bnx2x_set_power_state(bp, PCI_D0);
12522
12523         /* If parity had happen during the unload, then attentions
12524          * and/or RECOVERY_IN_PROGRES may still be set. In this case we
12525          * want the first function loaded on the current engine to
12526          * complete the recovery.
12527          * Parity recovery is only relevant for PF driver.
12528          */
12529         if (IS_PF(bp)) {
12530                 int other_engine = BP_PATH(bp) ? 0 : 1;
12531                 bool other_load_status, load_status;
12532                 bool global = false;
12533
12534                 other_load_status = bnx2x_get_load_status(bp, other_engine);
12535                 load_status = bnx2x_get_load_status(bp, BP_PATH(bp));
12536                 if (!bnx2x_reset_is_done(bp, BP_PATH(bp)) ||
12537                     bnx2x_chk_parity_attn(bp, &global, true)) {
12538                         do {
12539                                 /* If there are attentions and they are in a
12540                                  * global blocks, set the GLOBAL_RESET bit
12541                                  * regardless whether it will be this function
12542                                  * that will complete the recovery or not.
12543                                  */
12544                                 if (global)
12545                                         bnx2x_set_reset_global(bp);
12546
12547                                 /* Only the first function on the current
12548                                  * engine should try to recover in open. In case
12549                                  * of attentions in global blocks only the first
12550                                  * in the chip should try to recover.
12551                                  */
12552                                 if ((!load_status &&
12553                                      (!global || !other_load_status)) &&
12554                                       bnx2x_trylock_leader_lock(bp) &&
12555                                       !bnx2x_leader_reset(bp)) {
12556                                         netdev_info(bp->dev,
12557                                                     "Recovered in open\n");
12558                                         break;
12559                                 }
12560
12561                                 /* recovery has failed... */
12562                                 bnx2x_set_power_state(bp, PCI_D3hot);
12563                                 bp->recovery_state = BNX2X_RECOVERY_FAILED;
12564
12565                                 BNX2X_ERR("Recovery flow hasn't been properly completed yet. Try again later.\n"
12566                                           "If you still see this message after a few retries then power cycle is required.\n");
12567
12568                                 return -EAGAIN;
12569                         } while (0);
12570                 }
12571         }
12572
12573         bp->recovery_state = BNX2X_RECOVERY_DONE;
12574         rc = bnx2x_nic_load(bp, LOAD_OPEN);
12575         if (rc)
12576                 return rc;
12577
12578         if (IS_PF(bp))
12579                 udp_tunnel_get_rx_info(dev);
12580
12581         return 0;
12582 }
12583
12584 /* called with rtnl_lock */
12585 static int bnx2x_close(struct net_device *dev)
12586 {
12587         struct bnx2x *bp = netdev_priv(dev);
12588
12589         /* Unload the driver, release IRQs */
12590         bnx2x_nic_unload(bp, UNLOAD_CLOSE, false);
12591
12592         return 0;
12593 }
12594
12595 struct bnx2x_mcast_list_elem_group
12596 {
12597         struct list_head mcast_group_link;
12598         struct bnx2x_mcast_list_elem mcast_elems[];
12599 };
12600
12601 #define MCAST_ELEMS_PER_PG \
12602         ((PAGE_SIZE - sizeof(struct bnx2x_mcast_list_elem_group)) / \
12603         sizeof(struct bnx2x_mcast_list_elem))
12604
12605 static void bnx2x_free_mcast_macs_list(struct list_head *mcast_group_list)
12606 {
12607         struct bnx2x_mcast_list_elem_group *current_mcast_group;
12608
12609         while (!list_empty(mcast_group_list)) {
12610                 current_mcast_group = list_first_entry(mcast_group_list,
12611                                       struct bnx2x_mcast_list_elem_group,
12612                                       mcast_group_link);
12613                 list_del(&current_mcast_group->mcast_group_link);
12614                 free_page((unsigned long)current_mcast_group);
12615         }
12616 }
12617
12618 static int bnx2x_init_mcast_macs_list(struct bnx2x *bp,
12619                                       struct bnx2x_mcast_ramrod_params *p,
12620                                       struct list_head *mcast_group_list)
12621 {
12622         struct bnx2x_mcast_list_elem *mc_mac;
12623         struct netdev_hw_addr *ha;
12624         struct bnx2x_mcast_list_elem_group *current_mcast_group = NULL;
12625         int mc_count = netdev_mc_count(bp->dev);
12626         int offset = 0;
12627
12628         INIT_LIST_HEAD(&p->mcast_list);
12629         netdev_for_each_mc_addr(ha, bp->dev) {
12630                 if (!offset) {
12631                         current_mcast_group =
12632                                 (struct bnx2x_mcast_list_elem_group *)
12633                                 __get_free_page(GFP_ATOMIC);
12634                         if (!current_mcast_group) {
12635                                 bnx2x_free_mcast_macs_list(mcast_group_list);
12636                                 BNX2X_ERR("Failed to allocate mc MAC list\n");
12637                                 return -ENOMEM;
12638                         }
12639                         list_add(&current_mcast_group->mcast_group_link,
12640                                  mcast_group_list);
12641                 }
12642                 mc_mac = &current_mcast_group->mcast_elems[offset];
12643                 mc_mac->mac = bnx2x_mc_addr(ha);
12644                 list_add_tail(&mc_mac->link, &p->mcast_list);
12645                 offset++;
12646                 if (offset == MCAST_ELEMS_PER_PG)
12647                         offset = 0;
12648         }
12649         p->mcast_list_len = mc_count;
12650         return 0;
12651 }
12652
12653 /**
12654  * bnx2x_set_uc_list - configure a new unicast MACs list.
12655  *
12656  * @bp: driver handle
12657  *
12658  * We will use zero (0) as a MAC type for these MACs.
12659  */
12660 static int bnx2x_set_uc_list(struct bnx2x *bp)
12661 {
12662         int rc;
12663         struct net_device *dev = bp->dev;
12664         struct netdev_hw_addr *ha;
12665         struct bnx2x_vlan_mac_obj *mac_obj = &bp->sp_objs->mac_obj;
12666         unsigned long ramrod_flags = 0;
12667
12668         /* First schedule a cleanup up of old configuration */
12669         rc = bnx2x_del_all_macs(bp, mac_obj, BNX2X_UC_LIST_MAC, false);
12670         if (rc < 0) {
12671                 BNX2X_ERR("Failed to schedule DELETE operations: %d\n", rc);
12672                 return rc;
12673         }
12674
12675         netdev_for_each_uc_addr(ha, dev) {
12676                 rc = bnx2x_set_mac_one(bp, bnx2x_uc_addr(ha), mac_obj, true,
12677                                        BNX2X_UC_LIST_MAC, &ramrod_flags);
12678                 if (rc == -EEXIST) {
12679                         DP(BNX2X_MSG_SP,
12680                            "Failed to schedule ADD operations: %d\n", rc);
12681                         /* do not treat adding same MAC as error */
12682                         rc = 0;
12683
12684                 } else if (rc < 0) {
12685
12686                         BNX2X_ERR("Failed to schedule ADD operations: %d\n",
12687                                   rc);
12688                         return rc;
12689                 }
12690         }
12691
12692         /* Execute the pending commands */
12693         __set_bit(RAMROD_CONT, &ramrod_flags);
12694         return bnx2x_set_mac_one(bp, NULL, mac_obj, false /* don't care */,
12695                                  BNX2X_UC_LIST_MAC, &ramrod_flags);
12696 }
12697
12698 static int bnx2x_set_mc_list_e1x(struct bnx2x *bp)
12699 {
12700         LIST_HEAD(mcast_group_list);
12701         struct net_device *dev = bp->dev;
12702         struct bnx2x_mcast_ramrod_params rparam = {NULL};
12703         int rc = 0;
12704
12705         rparam.mcast_obj = &bp->mcast_obj;
12706
12707         /* first, clear all configured multicast MACs */
12708         rc = bnx2x_config_mcast(bp, &rparam, BNX2X_MCAST_CMD_DEL);
12709         if (rc < 0) {
12710                 BNX2X_ERR("Failed to clear multicast configuration: %d\n", rc);
12711                 return rc;
12712         }
12713
12714         /* then, configure a new MACs list */
12715         if (netdev_mc_count(dev)) {
12716                 rc = bnx2x_init_mcast_macs_list(bp, &rparam, &mcast_group_list);
12717                 if (rc)
12718                         return rc;
12719
12720                 /* Now add the new MACs */
12721                 rc = bnx2x_config_mcast(bp, &rparam,
12722                                         BNX2X_MCAST_CMD_ADD);
12723                 if (rc < 0)
12724                         BNX2X_ERR("Failed to set a new multicast configuration: %d\n",
12725                                   rc);
12726
12727                 bnx2x_free_mcast_macs_list(&mcast_group_list);
12728         }
12729
12730         return rc;
12731 }
12732
12733 static int bnx2x_set_mc_list(struct bnx2x *bp)
12734 {
12735         LIST_HEAD(mcast_group_list);
12736         struct bnx2x_mcast_ramrod_params rparam = {NULL};
12737         struct net_device *dev = bp->dev;
12738         int rc = 0;
12739
12740         /* On older adapters, we need to flush and re-add filters */
12741         if (CHIP_IS_E1x(bp))
12742                 return bnx2x_set_mc_list_e1x(bp);
12743
12744         rparam.mcast_obj = &bp->mcast_obj;
12745
12746         if (netdev_mc_count(dev)) {
12747                 rc = bnx2x_init_mcast_macs_list(bp, &rparam, &mcast_group_list);
12748                 if (rc)
12749                         return rc;
12750
12751                 /* Override the curently configured set of mc filters */
12752                 rc = bnx2x_config_mcast(bp, &rparam,
12753                                         BNX2X_MCAST_CMD_SET);
12754                 if (rc < 0)
12755                         BNX2X_ERR("Failed to set a new multicast configuration: %d\n",
12756                                   rc);
12757
12758                 bnx2x_free_mcast_macs_list(&mcast_group_list);
12759         } else {
12760                 /* If no mc addresses are required, flush the configuration */
12761                 rc = bnx2x_config_mcast(bp, &rparam, BNX2X_MCAST_CMD_DEL);
12762                 if (rc < 0)
12763                         BNX2X_ERR("Failed to clear multicast configuration %d\n",
12764                                   rc);
12765         }
12766
12767         return rc;
12768 }
12769
12770 /* If bp->state is OPEN, should be called with netif_addr_lock_bh() */
12771 static void bnx2x_set_rx_mode(struct net_device *dev)
12772 {
12773         struct bnx2x *bp = netdev_priv(dev);
12774
12775         if (bp->state != BNX2X_STATE_OPEN) {
12776                 DP(NETIF_MSG_IFUP, "state is %x, returning\n", bp->state);
12777                 return;
12778         } else {
12779                 /* Schedule an SP task to handle rest of change */
12780                 bnx2x_schedule_sp_rtnl(bp, BNX2X_SP_RTNL_RX_MODE,
12781                                        NETIF_MSG_IFUP);
12782         }
12783 }
12784
12785 void bnx2x_set_rx_mode_inner(struct bnx2x *bp)
12786 {
12787         u32 rx_mode = BNX2X_RX_MODE_NORMAL;
12788
12789         DP(NETIF_MSG_IFUP, "dev->flags = %x\n", bp->dev->flags);
12790
12791         netif_addr_lock_bh(bp->dev);
12792
12793         if (bp->dev->flags & IFF_PROMISC) {
12794                 rx_mode = BNX2X_RX_MODE_PROMISC;
12795         } else if ((bp->dev->flags & IFF_ALLMULTI) ||
12796                    ((netdev_mc_count(bp->dev) > BNX2X_MAX_MULTICAST) &&
12797                     CHIP_IS_E1(bp))) {
12798                 rx_mode = BNX2X_RX_MODE_ALLMULTI;
12799         } else {
12800                 if (IS_PF(bp)) {
12801                         /* some multicasts */
12802                         if (bnx2x_set_mc_list(bp) < 0)
12803                                 rx_mode = BNX2X_RX_MODE_ALLMULTI;
12804
12805                         /* release bh lock, as bnx2x_set_uc_list might sleep */
12806                         netif_addr_unlock_bh(bp->dev);
12807                         if (bnx2x_set_uc_list(bp) < 0)
12808                                 rx_mode = BNX2X_RX_MODE_PROMISC;
12809                         netif_addr_lock_bh(bp->dev);
12810                 } else {
12811                         /* configuring mcast to a vf involves sleeping (when we
12812                          * wait for the pf's response).
12813                          */
12814                         bnx2x_schedule_sp_rtnl(bp,
12815                                                BNX2X_SP_RTNL_VFPF_MCAST, 0);
12816                 }
12817         }
12818
12819         bp->rx_mode = rx_mode;
12820         /* handle ISCSI SD mode */
12821         if (IS_MF_ISCSI_ONLY(bp))
12822                 bp->rx_mode = BNX2X_RX_MODE_NONE;
12823
12824         /* Schedule the rx_mode command */
12825         if (test_bit(BNX2X_FILTER_RX_MODE_PENDING, &bp->sp_state)) {
12826                 set_bit(BNX2X_FILTER_RX_MODE_SCHED, &bp->sp_state);
12827                 netif_addr_unlock_bh(bp->dev);
12828                 return;
12829         }
12830
12831         if (IS_PF(bp)) {
12832                 bnx2x_set_storm_rx_mode(bp);
12833                 netif_addr_unlock_bh(bp->dev);
12834         } else {
12835                 /* VF will need to request the PF to make this change, and so
12836                  * the VF needs to release the bottom-half lock prior to the
12837                  * request (as it will likely require sleep on the VF side)
12838                  */
12839                 netif_addr_unlock_bh(bp->dev);
12840                 bnx2x_vfpf_storm_rx_mode(bp);
12841         }
12842 }
12843
12844 /* called with rtnl_lock */
12845 static int bnx2x_mdio_read(struct net_device *netdev, int prtad,
12846                            int devad, u16 addr)
12847 {
12848         struct bnx2x *bp = netdev_priv(netdev);
12849         u16 value;
12850         int rc;
12851
12852         DP(NETIF_MSG_LINK, "mdio_read: prtad 0x%x, devad 0x%x, addr 0x%x\n",
12853            prtad, devad, addr);
12854
12855         /* The HW expects different devad if CL22 is used */
12856         devad = (devad == MDIO_DEVAD_NONE) ? DEFAULT_PHY_DEV_ADDR : devad;
12857
12858         bnx2x_acquire_phy_lock(bp);
12859         rc = bnx2x_phy_read(&bp->link_params, prtad, devad, addr, &value);
12860         bnx2x_release_phy_lock(bp);
12861         DP(NETIF_MSG_LINK, "mdio_read_val 0x%x rc = 0x%x\n", value, rc);
12862
12863         if (!rc)
12864                 rc = value;
12865         return rc;
12866 }
12867
12868 /* called with rtnl_lock */
12869 static int bnx2x_mdio_write(struct net_device *netdev, int prtad, int devad,
12870                             u16 addr, u16 value)
12871 {
12872         struct bnx2x *bp = netdev_priv(netdev);
12873         int rc;
12874
12875         DP(NETIF_MSG_LINK,
12876            "mdio_write: prtad 0x%x, devad 0x%x, addr 0x%x, value 0x%x\n",
12877            prtad, devad, addr, value);
12878
12879         /* The HW expects different devad if CL22 is used */
12880         devad = (devad == MDIO_DEVAD_NONE) ? DEFAULT_PHY_DEV_ADDR : devad;
12881
12882         bnx2x_acquire_phy_lock(bp);
12883         rc = bnx2x_phy_write(&bp->link_params, prtad, devad, addr, value);
12884         bnx2x_release_phy_lock(bp);
12885         return rc;
12886 }
12887
12888 /* called with rtnl_lock */
12889 static int bnx2x_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
12890 {
12891         struct bnx2x *bp = netdev_priv(dev);
12892         struct mii_ioctl_data *mdio = if_mii(ifr);
12893
12894         if (!netif_running(dev))
12895                 return -EAGAIN;
12896
12897         switch (cmd) {
12898         case SIOCSHWTSTAMP:
12899                 return bnx2x_hwtstamp_ioctl(bp, ifr);
12900         default:
12901                 DP(NETIF_MSG_LINK, "ioctl: phy id 0x%x, reg 0x%x, val_in 0x%x\n",
12902                    mdio->phy_id, mdio->reg_num, mdio->val_in);
12903                 return mdio_mii_ioctl(&bp->mdio, mdio, cmd);
12904         }
12905 }
12906
12907 static int bnx2x_validate_addr(struct net_device *dev)
12908 {
12909         struct bnx2x *bp = netdev_priv(dev);
12910
12911         /* query the bulletin board for mac address configured by the PF */
12912         if (IS_VF(bp))
12913                 bnx2x_sample_bulletin(bp);
12914
12915         if (!is_valid_ether_addr(dev->dev_addr)) {
12916                 BNX2X_ERR("Non-valid Ethernet address\n");
12917                 return -EADDRNOTAVAIL;
12918         }
12919         return 0;
12920 }
12921
12922 static int bnx2x_get_phys_port_id(struct net_device *netdev,
12923                                   struct netdev_phys_item_id *ppid)
12924 {
12925         struct bnx2x *bp = netdev_priv(netdev);
12926
12927         if (!(bp->flags & HAS_PHYS_PORT_ID))
12928                 return -EOPNOTSUPP;
12929
12930         ppid->id_len = sizeof(bp->phys_port_id);
12931         memcpy(ppid->id, bp->phys_port_id, ppid->id_len);
12932
12933         return 0;
12934 }
12935
12936 static netdev_features_t bnx2x_features_check(struct sk_buff *skb,
12937                                               struct net_device *dev,
12938                                               netdev_features_t features)
12939 {
12940         /*
12941          * A skb with gso_size + header length > 9700 will cause a
12942          * firmware panic. Drop GSO support.
12943          *
12944          * Eventually the upper layer should not pass these packets down.
12945          *
12946          * For speed, if the gso_size is <= 9000, assume there will
12947          * not be 700 bytes of headers and pass it through. Only do a
12948          * full (slow) validation if the gso_size is > 9000.
12949          *
12950          * (Due to the way SKB_BY_FRAGS works this will also do a full
12951          * validation in that case.)
12952          */
12953         if (unlikely(skb_is_gso(skb) &&
12954                      (skb_shinfo(skb)->gso_size > 9000) &&
12955                      !skb_gso_validate_mac_len(skb, 9700)))
12956                 features &= ~NETIF_F_GSO_MASK;
12957
12958         features = vlan_features_check(skb, features);
12959         return vxlan_features_check(skb, features);
12960 }
12961
12962 static int __bnx2x_vlan_configure_vid(struct bnx2x *bp, u16 vid, bool add)
12963 {
12964         int rc;
12965
12966         if (IS_PF(bp)) {
12967                 unsigned long ramrod_flags = 0;
12968
12969                 __set_bit(RAMROD_COMP_WAIT, &ramrod_flags);
12970                 rc = bnx2x_set_vlan_one(bp, vid, &bp->sp_objs->vlan_obj,
12971                                         add, &ramrod_flags);
12972         } else {
12973                 rc = bnx2x_vfpf_update_vlan(bp, vid, bp->fp->index, add);
12974         }
12975
12976         return rc;
12977 }
12978
12979 static int bnx2x_vlan_configure_vid_list(struct bnx2x *bp)
12980 {
12981         struct bnx2x_vlan_entry *vlan;
12982         int rc = 0;
12983
12984         /* Configure all non-configured entries */
12985         list_for_each_entry(vlan, &bp->vlan_reg, link) {
12986                 if (vlan->hw)
12987                         continue;
12988
12989                 if (bp->vlan_cnt >= bp->vlan_credit)
12990                         return -ENOBUFS;
12991
12992                 rc = __bnx2x_vlan_configure_vid(bp, vlan->vid, true);
12993                 if (rc) {
12994                         BNX2X_ERR("Unable to config VLAN %d\n", vlan->vid);
12995                         return rc;
12996                 }
12997
12998                 DP(NETIF_MSG_IFUP, "HW configured for VLAN %d\n", vlan->vid);
12999                 vlan->hw = true;
13000                 bp->vlan_cnt++;
13001         }
13002
13003         return 0;
13004 }
13005
13006 static void bnx2x_vlan_configure(struct bnx2x *bp, bool set_rx_mode)
13007 {
13008         bool need_accept_any_vlan;
13009
13010         need_accept_any_vlan = !!bnx2x_vlan_configure_vid_list(bp);
13011
13012         if (bp->accept_any_vlan != need_accept_any_vlan) {
13013                 bp->accept_any_vlan = need_accept_any_vlan;
13014                 DP(NETIF_MSG_IFUP, "Accept all VLAN %s\n",
13015                    bp->accept_any_vlan ? "raised" : "cleared");
13016                 if (set_rx_mode) {
13017                         if (IS_PF(bp))
13018                                 bnx2x_set_rx_mode_inner(bp);
13019                         else
13020                                 bnx2x_vfpf_storm_rx_mode(bp);
13021                 }
13022         }
13023 }
13024
13025 int bnx2x_vlan_reconfigure_vid(struct bnx2x *bp)
13026 {
13027         struct bnx2x_vlan_entry *vlan;
13028
13029         /* The hw forgot all entries after reload */
13030         list_for_each_entry(vlan, &bp->vlan_reg, link)
13031                 vlan->hw = false;
13032         bp->vlan_cnt = 0;
13033
13034         /* Don't set rx mode here. Our caller will do it. */
13035         bnx2x_vlan_configure(bp, false);
13036
13037         return 0;
13038 }
13039
13040 static int bnx2x_vlan_rx_add_vid(struct net_device *dev, __be16 proto, u16 vid)
13041 {
13042         struct bnx2x *bp = netdev_priv(dev);
13043         struct bnx2x_vlan_entry *vlan;
13044
13045         DP(NETIF_MSG_IFUP, "Adding VLAN %d\n", vid);
13046
13047         vlan = kmalloc(sizeof(*vlan), GFP_KERNEL);
13048         if (!vlan)
13049                 return -ENOMEM;
13050
13051         vlan->vid = vid;
13052         vlan->hw = false;
13053         list_add_tail(&vlan->link, &bp->vlan_reg);
13054
13055         if (netif_running(dev))
13056                 bnx2x_vlan_configure(bp, true);
13057
13058         return 0;
13059 }
13060
13061 static int bnx2x_vlan_rx_kill_vid(struct net_device *dev, __be16 proto, u16 vid)
13062 {
13063         struct bnx2x *bp = netdev_priv(dev);
13064         struct bnx2x_vlan_entry *vlan;
13065         bool found = false;
13066         int rc = 0;
13067
13068         DP(NETIF_MSG_IFUP, "Removing VLAN %d\n", vid);
13069
13070         list_for_each_entry(vlan, &bp->vlan_reg, link)
13071                 if (vlan->vid == vid) {
13072                         found = true;
13073                         break;
13074                 }
13075
13076         if (!found) {
13077                 BNX2X_ERR("Unable to kill VLAN %d - not found\n", vid);
13078                 return -EINVAL;
13079         }
13080
13081         if (netif_running(dev) && vlan->hw) {
13082                 rc = __bnx2x_vlan_configure_vid(bp, vid, false);
13083                 DP(NETIF_MSG_IFUP, "HW deconfigured for VLAN %d\n", vid);
13084                 bp->vlan_cnt--;
13085         }
13086
13087         list_del(&vlan->link);
13088         kfree(vlan);
13089
13090         if (netif_running(dev))
13091                 bnx2x_vlan_configure(bp, true);
13092
13093         DP(NETIF_MSG_IFUP, "Removing VLAN result %d\n", rc);
13094
13095         return rc;
13096 }
13097
13098 static const struct net_device_ops bnx2x_netdev_ops = {
13099         .ndo_open               = bnx2x_open,
13100         .ndo_stop               = bnx2x_close,
13101         .ndo_start_xmit         = bnx2x_start_xmit,
13102         .ndo_select_queue       = bnx2x_select_queue,
13103         .ndo_set_rx_mode        = bnx2x_set_rx_mode,
13104         .ndo_set_mac_address    = bnx2x_change_mac_addr,
13105         .ndo_validate_addr      = bnx2x_validate_addr,
13106         .ndo_do_ioctl           = bnx2x_ioctl,
13107         .ndo_change_mtu         = bnx2x_change_mtu,
13108         .ndo_fix_features       = bnx2x_fix_features,
13109         .ndo_set_features       = bnx2x_set_features,
13110         .ndo_tx_timeout         = bnx2x_tx_timeout,
13111         .ndo_vlan_rx_add_vid    = bnx2x_vlan_rx_add_vid,
13112         .ndo_vlan_rx_kill_vid   = bnx2x_vlan_rx_kill_vid,
13113         .ndo_setup_tc           = __bnx2x_setup_tc,
13114 #ifdef CONFIG_BNX2X_SRIOV
13115         .ndo_set_vf_mac         = bnx2x_set_vf_mac,
13116         .ndo_set_vf_vlan        = bnx2x_set_vf_vlan,
13117         .ndo_get_vf_config      = bnx2x_get_vf_config,
13118         .ndo_set_vf_spoofchk    = bnx2x_set_vf_spoofchk,
13119 #endif
13120 #ifdef NETDEV_FCOE_WWNN
13121         .ndo_fcoe_get_wwn       = bnx2x_fcoe_get_wwn,
13122 #endif
13123
13124         .ndo_get_phys_port_id   = bnx2x_get_phys_port_id,
13125         .ndo_set_vf_link_state  = bnx2x_set_vf_link_state,
13126         .ndo_features_check     = bnx2x_features_check,
13127         .ndo_udp_tunnel_add     = bnx2x_udp_tunnel_add,
13128         .ndo_udp_tunnel_del     = bnx2x_udp_tunnel_del,
13129 };
13130
13131 static int bnx2x_set_coherency_mask(struct bnx2x *bp)
13132 {
13133         struct device *dev = &bp->pdev->dev;
13134
13135         if (dma_set_mask_and_coherent(dev, DMA_BIT_MASK(64)) != 0 &&
13136             dma_set_mask_and_coherent(dev, DMA_BIT_MASK(32)) != 0) {
13137                 dev_err(dev, "System does not support DMA, aborting\n");
13138                 return -EIO;
13139         }
13140
13141         return 0;
13142 }
13143
13144 static void bnx2x_disable_pcie_error_reporting(struct bnx2x *bp)
13145 {
13146         if (bp->flags & AER_ENABLED) {
13147                 pci_disable_pcie_error_reporting(bp->pdev);
13148                 bp->flags &= ~AER_ENABLED;
13149         }
13150 }
13151
13152 static int bnx2x_init_dev(struct bnx2x *bp, struct pci_dev *pdev,
13153                           struct net_device *dev, unsigned long board_type)
13154 {
13155         int rc;
13156         u32 pci_cfg_dword;
13157         bool chip_is_e1x = (board_type == BCM57710 ||
13158                             board_type == BCM57711 ||
13159                             board_type == BCM57711E);
13160
13161         SET_NETDEV_DEV(dev, &pdev->dev);
13162
13163         bp->dev = dev;
13164         bp->pdev = pdev;
13165
13166         rc = pci_enable_device(pdev);
13167         if (rc) {
13168                 dev_err(&bp->pdev->dev,
13169                         "Cannot enable PCI device, aborting\n");
13170                 goto err_out;
13171         }
13172
13173         if (!(pci_resource_flags(pdev, 0) & IORESOURCE_MEM)) {
13174                 dev_err(&bp->pdev->dev,
13175                         "Cannot find PCI device base address, aborting\n");
13176                 rc = -ENODEV;
13177                 goto err_out_disable;
13178         }
13179
13180         if (IS_PF(bp) && !(pci_resource_flags(pdev, 2) & IORESOURCE_MEM)) {
13181                 dev_err(&bp->pdev->dev, "Cannot find second PCI device base address, aborting\n");
13182                 rc = -ENODEV;
13183                 goto err_out_disable;
13184         }
13185
13186         pci_read_config_dword(pdev, PCICFG_REVISION_ID_OFFSET, &pci_cfg_dword);
13187         if ((pci_cfg_dword & PCICFG_REVESION_ID_MASK) ==
13188             PCICFG_REVESION_ID_ERROR_VAL) {
13189                 pr_err("PCI device error, probably due to fan failure, aborting\n");
13190                 rc = -ENODEV;
13191                 goto err_out_disable;
13192         }
13193
13194         if (atomic_read(&pdev->enable_cnt) == 1) {
13195                 rc = pci_request_regions(pdev, DRV_MODULE_NAME);
13196                 if (rc) {
13197                         dev_err(&bp->pdev->dev,
13198                                 "Cannot obtain PCI resources, aborting\n");
13199                         goto err_out_disable;
13200                 }
13201
13202                 pci_set_master(pdev);
13203                 pci_save_state(pdev);
13204         }
13205
13206         if (IS_PF(bp)) {
13207                 if (!pdev->pm_cap) {
13208                         dev_err(&bp->pdev->dev,
13209                                 "Cannot find power management capability, aborting\n");
13210                         rc = -EIO;
13211                         goto err_out_release;
13212                 }
13213         }
13214
13215         if (!pci_is_pcie(pdev)) {
13216                 dev_err(&bp->pdev->dev, "Not PCI Express, aborting\n");
13217                 rc = -EIO;
13218                 goto err_out_release;
13219         }
13220
13221         rc = bnx2x_set_coherency_mask(bp);
13222         if (rc)
13223                 goto err_out_release;
13224
13225         dev->mem_start = pci_resource_start(pdev, 0);
13226         dev->base_addr = dev->mem_start;
13227         dev->mem_end = pci_resource_end(pdev, 0);
13228
13229         dev->irq = pdev->irq;
13230
13231         bp->regview = pci_ioremap_bar(pdev, 0);
13232         if (!bp->regview) {
13233                 dev_err(&bp->pdev->dev,
13234                         "Cannot map register space, aborting\n");
13235                 rc = -ENOMEM;
13236                 goto err_out_release;
13237         }
13238
13239         /* In E1/E1H use pci device function given by kernel.
13240          * In E2/E3 read physical function from ME register since these chips
13241          * support Physical Device Assignment where kernel BDF maybe arbitrary
13242          * (depending on hypervisor).
13243          */
13244         if (chip_is_e1x) {
13245                 bp->pf_num = PCI_FUNC(pdev->devfn);
13246         } else {
13247                 /* chip is E2/3*/
13248                 pci_read_config_dword(bp->pdev,
13249                                       PCICFG_ME_REGISTER, &pci_cfg_dword);
13250                 bp->pf_num = (u8)((pci_cfg_dword & ME_REG_ABS_PF_NUM) >>
13251                                   ME_REG_ABS_PF_NUM_SHIFT);
13252         }
13253         BNX2X_DEV_INFO("me reg PF num: %d\n", bp->pf_num);
13254
13255         /* clean indirect addresses */
13256         pci_write_config_dword(bp->pdev, PCICFG_GRC_ADDRESS,
13257                                PCICFG_VENDOR_ID_OFFSET);
13258
13259         /* Set PCIe reset type to fundamental for EEH recovery */
13260         pdev->needs_freset = 1;
13261
13262         /* AER (Advanced Error reporting) configuration */
13263         rc = pci_enable_pcie_error_reporting(pdev);
13264         if (!rc)
13265                 bp->flags |= AER_ENABLED;
13266         else
13267                 BNX2X_DEV_INFO("Failed To configure PCIe AER [%d]\n", rc);
13268
13269         /*
13270          * Clean the following indirect addresses for all functions since it
13271          * is not used by the driver.
13272          */
13273         if (IS_PF(bp)) {
13274                 REG_WR(bp, PXP2_REG_PGL_ADDR_88_F0, 0);
13275                 REG_WR(bp, PXP2_REG_PGL_ADDR_8C_F0, 0);
13276                 REG_WR(bp, PXP2_REG_PGL_ADDR_90_F0, 0);
13277                 REG_WR(bp, PXP2_REG_PGL_ADDR_94_F0, 0);
13278
13279                 if (chip_is_e1x) {
13280                         REG_WR(bp, PXP2_REG_PGL_ADDR_88_F1, 0);
13281                         REG_WR(bp, PXP2_REG_PGL_ADDR_8C_F1, 0);
13282                         REG_WR(bp, PXP2_REG_PGL_ADDR_90_F1, 0);
13283                         REG_WR(bp, PXP2_REG_PGL_ADDR_94_F1, 0);
13284                 }
13285
13286                 /* Enable internal target-read (in case we are probed after PF
13287                  * FLR). Must be done prior to any BAR read access. Only for
13288                  * 57712 and up
13289                  */
13290                 if (!chip_is_e1x)
13291                         REG_WR(bp,
13292                                PGLUE_B_REG_INTERNAL_PFID_ENABLE_TARGET_READ, 1);
13293         }
13294
13295         dev->watchdog_timeo = TX_TIMEOUT;
13296
13297         dev->netdev_ops = &bnx2x_netdev_ops;
13298         bnx2x_set_ethtool_ops(bp, dev);
13299
13300         dev->priv_flags |= IFF_UNICAST_FLT;
13301
13302         dev->hw_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM |
13303                 NETIF_F_TSO | NETIF_F_TSO_ECN | NETIF_F_TSO6 |
13304                 NETIF_F_RXCSUM | NETIF_F_LRO | NETIF_F_GRO | NETIF_F_GRO_HW |
13305                 NETIF_F_RXHASH | NETIF_F_HW_VLAN_CTAG_TX;
13306         if (!chip_is_e1x) {
13307                 dev->hw_features |= NETIF_F_GSO_GRE | NETIF_F_GSO_GRE_CSUM |
13308                                     NETIF_F_GSO_IPXIP4 |
13309                                     NETIF_F_GSO_UDP_TUNNEL |
13310                                     NETIF_F_GSO_UDP_TUNNEL_CSUM |
13311                                     NETIF_F_GSO_PARTIAL;
13312
13313                 dev->hw_enc_features =
13314                         NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM | NETIF_F_SG |
13315                         NETIF_F_TSO | NETIF_F_TSO_ECN | NETIF_F_TSO6 |
13316                         NETIF_F_GSO_IPXIP4 |
13317                         NETIF_F_GSO_GRE | NETIF_F_GSO_GRE_CSUM |
13318                         NETIF_F_GSO_UDP_TUNNEL | NETIF_F_GSO_UDP_TUNNEL_CSUM |
13319                         NETIF_F_GSO_PARTIAL;
13320
13321                 dev->gso_partial_features = NETIF_F_GSO_GRE_CSUM |
13322                                             NETIF_F_GSO_UDP_TUNNEL_CSUM;
13323         }
13324
13325         dev->vlan_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM |
13326                 NETIF_F_TSO | NETIF_F_TSO_ECN | NETIF_F_TSO6 | NETIF_F_HIGHDMA;
13327
13328         if (IS_PF(bp)) {
13329                 if (chip_is_e1x)
13330                         bp->accept_any_vlan = true;
13331                 else
13332                         dev->hw_features |= NETIF_F_HW_VLAN_CTAG_FILTER;
13333         }
13334         /* For VF we'll know whether to enable VLAN filtering after
13335          * getting a response to CHANNEL_TLV_ACQUIRE from PF.
13336          */
13337
13338         dev->features |= dev->hw_features | NETIF_F_HW_VLAN_CTAG_RX;
13339         dev->features |= NETIF_F_HIGHDMA;
13340         if (dev->features & NETIF_F_LRO)
13341                 dev->features &= ~NETIF_F_GRO_HW;
13342
13343         /* Add Loopback capability to the device */
13344         dev->hw_features |= NETIF_F_LOOPBACK;
13345
13346 #ifdef BCM_DCBNL
13347         dev->dcbnl_ops = &bnx2x_dcbnl_ops;
13348 #endif
13349
13350         /* MTU range, 46 - 9600 */
13351         dev->min_mtu = ETH_MIN_PACKET_SIZE;
13352         dev->max_mtu = ETH_MAX_JUMBO_PACKET_SIZE;
13353
13354         /* get_port_hwinfo() will set prtad and mmds properly */
13355         bp->mdio.prtad = MDIO_PRTAD_NONE;
13356         bp->mdio.mmds = 0;
13357         bp->mdio.mode_support = MDIO_SUPPORTS_C45 | MDIO_EMULATE_C22;
13358         bp->mdio.dev = dev;
13359         bp->mdio.mdio_read = bnx2x_mdio_read;
13360         bp->mdio.mdio_write = bnx2x_mdio_write;
13361
13362         return 0;
13363
13364 err_out_release:
13365         if (atomic_read(&pdev->enable_cnt) == 1)
13366                 pci_release_regions(pdev);
13367
13368 err_out_disable:
13369         pci_disable_device(pdev);
13370
13371 err_out:
13372         return rc;
13373 }
13374
13375 static int bnx2x_check_firmware(struct bnx2x *bp)
13376 {
13377         const struct firmware *firmware = bp->firmware;
13378         struct bnx2x_fw_file_hdr *fw_hdr;
13379         struct bnx2x_fw_file_section *sections;
13380         u32 offset, len, num_ops;
13381         __be16 *ops_offsets;
13382         int i;
13383         const u8 *fw_ver;
13384
13385         if (firmware->size < sizeof(struct bnx2x_fw_file_hdr)) {
13386                 BNX2X_ERR("Wrong FW size\n");
13387                 return -EINVAL;
13388         }
13389
13390         fw_hdr = (struct bnx2x_fw_file_hdr *)firmware->data;
13391         sections = (struct bnx2x_fw_file_section *)fw_hdr;
13392
13393         /* Make sure none of the offsets and sizes make us read beyond
13394          * the end of the firmware data */
13395         for (i = 0; i < sizeof(*fw_hdr) / sizeof(*sections); i++) {
13396                 offset = be32_to_cpu(sections[i].offset);
13397                 len = be32_to_cpu(sections[i].len);
13398                 if (offset + len > firmware->size) {
13399                         BNX2X_ERR("Section %d length is out of bounds\n", i);
13400                         return -EINVAL;
13401                 }
13402         }
13403
13404         /* Likewise for the init_ops offsets */
13405         offset = be32_to_cpu(fw_hdr->init_ops_offsets.offset);
13406         ops_offsets = (__force __be16 *)(firmware->data + offset);
13407         num_ops = be32_to_cpu(fw_hdr->init_ops.len) / sizeof(struct raw_op);
13408
13409         for (i = 0; i < be32_to_cpu(fw_hdr->init_ops_offsets.len) / 2; i++) {
13410                 if (be16_to_cpu(ops_offsets[i]) > num_ops) {
13411                         BNX2X_ERR("Section offset %d is out of bounds\n", i);
13412                         return -EINVAL;
13413                 }
13414         }
13415
13416         /* Check FW version */
13417         offset = be32_to_cpu(fw_hdr->fw_version.offset);
13418         fw_ver = firmware->data + offset;
13419         if ((fw_ver[0] != BCM_5710_FW_MAJOR_VERSION) ||
13420             (fw_ver[1] != BCM_5710_FW_MINOR_VERSION) ||
13421             (fw_ver[2] != BCM_5710_FW_REVISION_VERSION) ||
13422             (fw_ver[3] != BCM_5710_FW_ENGINEERING_VERSION)) {
13423                 BNX2X_ERR("Bad FW version:%d.%d.%d.%d. Should be %d.%d.%d.%d\n",
13424                        fw_ver[0], fw_ver[1], fw_ver[2], fw_ver[3],
13425                        BCM_5710_FW_MAJOR_VERSION,
13426                        BCM_5710_FW_MINOR_VERSION,
13427                        BCM_5710_FW_REVISION_VERSION,
13428                        BCM_5710_FW_ENGINEERING_VERSION);
13429                 return -EINVAL;
13430         }
13431
13432         return 0;
13433 }
13434
13435 static void be32_to_cpu_n(const u8 *_source, u8 *_target, u32 n)
13436 {
13437         const __be32 *source = (const __be32 *)_source;
13438         u32 *target = (u32 *)_target;
13439         u32 i;
13440
13441         for (i = 0; i < n/4; i++)
13442                 target[i] = be32_to_cpu(source[i]);
13443 }
13444
13445 /*
13446    Ops array is stored in the following format:
13447    {op(8bit), offset(24bit, big endian), data(32bit, big endian)}
13448  */
13449 static void bnx2x_prep_ops(const u8 *_source, u8 *_target, u32 n)
13450 {
13451         const __be32 *source = (const __be32 *)_source;
13452         struct raw_op *target = (struct raw_op *)_target;
13453         u32 i, j, tmp;
13454
13455         for (i = 0, j = 0; i < n/8; i++, j += 2) {
13456                 tmp = be32_to_cpu(source[j]);
13457                 target[i].op = (tmp >> 24) & 0xff;
13458                 target[i].offset = tmp & 0xffffff;
13459                 target[i].raw_data = be32_to_cpu(source[j + 1]);
13460         }
13461 }
13462
13463 /* IRO array is stored in the following format:
13464  * {base(24bit), m1(16bit), m2(16bit), m3(16bit), size(16bit) }
13465  */
13466 static void bnx2x_prep_iro(const u8 *_source, u8 *_target, u32 n)
13467 {
13468         const __be32 *source = (const __be32 *)_source;
13469         struct iro *target = (struct iro *)_target;
13470         u32 i, j, tmp;
13471
13472         for (i = 0, j = 0; i < n/sizeof(struct iro); i++) {
13473                 target[i].base = be32_to_cpu(source[j]);
13474                 j++;
13475                 tmp = be32_to_cpu(source[j]);
13476                 target[i].m1 = (tmp >> 16) & 0xffff;
13477                 target[i].m2 = tmp & 0xffff;
13478                 j++;
13479                 tmp = be32_to_cpu(source[j]);
13480                 target[i].m3 = (tmp >> 16) & 0xffff;
13481                 target[i].size = tmp & 0xffff;
13482                 j++;
13483         }
13484 }
13485
13486 static void be16_to_cpu_n(const u8 *_source, u8 *_target, u32 n)
13487 {
13488         const __be16 *source = (const __be16 *)_source;
13489         u16 *target = (u16 *)_target;
13490         u32 i;
13491
13492         for (i = 0; i < n/2; i++)
13493                 target[i] = be16_to_cpu(source[i]);
13494 }
13495
13496 #define BNX2X_ALLOC_AND_SET(arr, lbl, func)                             \
13497 do {                                                                    \
13498         u32 len = be32_to_cpu(fw_hdr->arr.len);                         \
13499         bp->arr = kmalloc(len, GFP_KERNEL);                             \
13500         if (!bp->arr)                                                   \
13501                 goto lbl;                                               \
13502         func(bp->firmware->data + be32_to_cpu(fw_hdr->arr.offset),      \
13503              (u8 *)bp->arr, len);                                       \
13504 } while (0)
13505
13506 static int bnx2x_init_firmware(struct bnx2x *bp)
13507 {
13508         const char *fw_file_name;
13509         struct bnx2x_fw_file_hdr *fw_hdr;
13510         int rc;
13511
13512         if (bp->firmware)
13513                 return 0;
13514
13515         if (CHIP_IS_E1(bp))
13516                 fw_file_name = FW_FILE_NAME_E1;
13517         else if (CHIP_IS_E1H(bp))
13518                 fw_file_name = FW_FILE_NAME_E1H;
13519         else if (!CHIP_IS_E1x(bp))
13520                 fw_file_name = FW_FILE_NAME_E2;
13521         else {
13522                 BNX2X_ERR("Unsupported chip revision\n");
13523                 return -EINVAL;
13524         }
13525         BNX2X_DEV_INFO("Loading %s\n", fw_file_name);
13526
13527         rc = request_firmware(&bp->firmware, fw_file_name, &bp->pdev->dev);
13528         if (rc) {
13529                 BNX2X_ERR("Can't load firmware file %s\n",
13530                           fw_file_name);
13531                 goto request_firmware_exit;
13532         }
13533
13534         rc = bnx2x_check_firmware(bp);
13535         if (rc) {
13536                 BNX2X_ERR("Corrupt firmware file %s\n", fw_file_name);
13537                 goto request_firmware_exit;
13538         }
13539
13540         fw_hdr = (struct bnx2x_fw_file_hdr *)bp->firmware->data;
13541
13542         /* Initialize the pointers to the init arrays */
13543         /* Blob */
13544         rc = -ENOMEM;
13545         BNX2X_ALLOC_AND_SET(init_data, request_firmware_exit, be32_to_cpu_n);
13546
13547         /* Opcodes */
13548         BNX2X_ALLOC_AND_SET(init_ops, init_ops_alloc_err, bnx2x_prep_ops);
13549
13550         /* Offsets */
13551         BNX2X_ALLOC_AND_SET(init_ops_offsets, init_offsets_alloc_err,
13552                             be16_to_cpu_n);
13553
13554         /* STORMs firmware */
13555         INIT_TSEM_INT_TABLE_DATA(bp) = bp->firmware->data +
13556                         be32_to_cpu(fw_hdr->tsem_int_table_data.offset);
13557         INIT_TSEM_PRAM_DATA(bp)      = bp->firmware->data +
13558                         be32_to_cpu(fw_hdr->tsem_pram_data.offset);
13559         INIT_USEM_INT_TABLE_DATA(bp) = bp->firmware->data +
13560                         be32_to_cpu(fw_hdr->usem_int_table_data.offset);
13561         INIT_USEM_PRAM_DATA(bp)      = bp->firmware->data +
13562                         be32_to_cpu(fw_hdr->usem_pram_data.offset);
13563         INIT_XSEM_INT_TABLE_DATA(bp) = bp->firmware->data +
13564                         be32_to_cpu(fw_hdr->xsem_int_table_data.offset);
13565         INIT_XSEM_PRAM_DATA(bp)      = bp->firmware->data +
13566                         be32_to_cpu(fw_hdr->xsem_pram_data.offset);
13567         INIT_CSEM_INT_TABLE_DATA(bp) = bp->firmware->data +
13568                         be32_to_cpu(fw_hdr->csem_int_table_data.offset);
13569         INIT_CSEM_PRAM_DATA(bp)      = bp->firmware->data +
13570                         be32_to_cpu(fw_hdr->csem_pram_data.offset);
13571         /* IRO */
13572         BNX2X_ALLOC_AND_SET(iro_arr, iro_alloc_err, bnx2x_prep_iro);
13573
13574         return 0;
13575
13576 iro_alloc_err:
13577         kfree(bp->init_ops_offsets);
13578 init_offsets_alloc_err:
13579         kfree(bp->init_ops);
13580 init_ops_alloc_err:
13581         kfree(bp->init_data);
13582 request_firmware_exit:
13583         release_firmware(bp->firmware);
13584         bp->firmware = NULL;
13585
13586         return rc;
13587 }
13588
13589 static void bnx2x_release_firmware(struct bnx2x *bp)
13590 {
13591         kfree(bp->init_ops_offsets);
13592         kfree(bp->init_ops);
13593         kfree(bp->init_data);
13594         release_firmware(bp->firmware);
13595         bp->firmware = NULL;
13596 }
13597
13598 static struct bnx2x_func_sp_drv_ops bnx2x_func_sp_drv = {
13599         .init_hw_cmn_chip = bnx2x_init_hw_common_chip,
13600         .init_hw_cmn      = bnx2x_init_hw_common,
13601         .init_hw_port     = bnx2x_init_hw_port,
13602         .init_hw_func     = bnx2x_init_hw_func,
13603
13604         .reset_hw_cmn     = bnx2x_reset_common,
13605         .reset_hw_port    = bnx2x_reset_port,
13606         .reset_hw_func    = bnx2x_reset_func,
13607
13608         .gunzip_init      = bnx2x_gunzip_init,
13609         .gunzip_end       = bnx2x_gunzip_end,
13610
13611         .init_fw          = bnx2x_init_firmware,
13612         .release_fw       = bnx2x_release_firmware,
13613 };
13614
13615 void bnx2x__init_func_obj(struct bnx2x *bp)
13616 {
13617         /* Prepare DMAE related driver resources */
13618         bnx2x_setup_dmae(bp);
13619
13620         bnx2x_init_func_obj(bp, &bp->func_obj,
13621                             bnx2x_sp(bp, func_rdata),
13622                             bnx2x_sp_mapping(bp, func_rdata),
13623                             bnx2x_sp(bp, func_afex_rdata),
13624                             bnx2x_sp_mapping(bp, func_afex_rdata),
13625                             &bnx2x_func_sp_drv);
13626 }
13627
13628 /* must be called after sriov-enable */
13629 static int bnx2x_set_qm_cid_count(struct bnx2x *bp)
13630 {
13631         int cid_count = BNX2X_L2_MAX_CID(bp);
13632
13633         if (IS_SRIOV(bp))
13634                 cid_count += BNX2X_VF_CIDS;
13635
13636         if (CNIC_SUPPORT(bp))
13637                 cid_count += CNIC_CID_MAX;
13638
13639         return roundup(cid_count, QM_CID_ROUND);
13640 }
13641
13642 /**
13643  * bnx2x_get_num_none_def_sbs - return the number of none default SBs
13644  *
13645  * @dev:        pci device
13646  *
13647  */
13648 static int bnx2x_get_num_non_def_sbs(struct pci_dev *pdev, int cnic_cnt)
13649 {
13650         int index;
13651         u16 control = 0;
13652
13653         /*
13654          * If MSI-X is not supported - return number of SBs needed to support
13655          * one fast path queue: one FP queue + SB for CNIC
13656          */
13657         if (!pdev->msix_cap) {
13658                 dev_info(&pdev->dev, "no msix capability found\n");
13659                 return 1 + cnic_cnt;
13660         }
13661         dev_info(&pdev->dev, "msix capability found\n");
13662
13663         /*
13664          * The value in the PCI configuration space is the index of the last
13665          * entry, namely one less than the actual size of the table, which is
13666          * exactly what we want to return from this function: number of all SBs
13667          * without the default SB.
13668          * For VFs there is no default SB, then we return (index+1).
13669          */
13670         pci_read_config_word(pdev, pdev->msix_cap + PCI_MSIX_FLAGS, &control);
13671
13672         index = control & PCI_MSIX_FLAGS_QSIZE;
13673
13674         return index;
13675 }
13676
13677 static int set_max_cos_est(int chip_id)
13678 {
13679         switch (chip_id) {
13680         case BCM57710:
13681         case BCM57711:
13682         case BCM57711E:
13683                 return BNX2X_MULTI_TX_COS_E1X;
13684         case BCM57712:
13685         case BCM57712_MF:
13686                 return BNX2X_MULTI_TX_COS_E2_E3A0;
13687         case BCM57800:
13688         case BCM57800_MF:
13689         case BCM57810:
13690         case BCM57810_MF:
13691         case BCM57840_4_10:
13692         case BCM57840_2_20:
13693         case BCM57840_O:
13694         case BCM57840_MFO:
13695         case BCM57840_MF:
13696         case BCM57811:
13697         case BCM57811_MF:
13698                 return BNX2X_MULTI_TX_COS_E3B0;
13699         case BCM57712_VF:
13700         case BCM57800_VF:
13701         case BCM57810_VF:
13702         case BCM57840_VF:
13703         case BCM57811_VF:
13704                 return 1;
13705         default:
13706                 pr_err("Unknown board_type (%d), aborting\n", chip_id);
13707                 return -ENODEV;
13708         }
13709 }
13710
13711 static int set_is_vf(int chip_id)
13712 {
13713         switch (chip_id) {
13714         case BCM57712_VF:
13715         case BCM57800_VF:
13716         case BCM57810_VF:
13717         case BCM57840_VF:
13718         case BCM57811_VF:
13719                 return true;
13720         default:
13721                 return false;
13722         }
13723 }
13724
13725 /* nig_tsgen registers relative address */
13726 #define tsgen_ctrl 0x0
13727 #define tsgen_freecount 0x10
13728 #define tsgen_synctime_t0 0x20
13729 #define tsgen_offset_t0 0x28
13730 #define tsgen_drift_t0 0x30
13731 #define tsgen_synctime_t1 0x58
13732 #define tsgen_offset_t1 0x60
13733 #define tsgen_drift_t1 0x68
13734
13735 /* FW workaround for setting drift */
13736 static int bnx2x_send_update_drift_ramrod(struct bnx2x *bp, int drift_dir,
13737                                           int best_val, int best_period)
13738 {
13739         struct bnx2x_func_state_params func_params = {NULL};
13740         struct bnx2x_func_set_timesync_params *set_timesync_params =
13741                 &func_params.params.set_timesync;
13742
13743         /* Prepare parameters for function state transitions */
13744         __set_bit(RAMROD_COMP_WAIT, &func_params.ramrod_flags);
13745         __set_bit(RAMROD_RETRY, &func_params.ramrod_flags);
13746
13747         func_params.f_obj = &bp->func_obj;
13748         func_params.cmd = BNX2X_F_CMD_SET_TIMESYNC;
13749
13750         /* Function parameters */
13751         set_timesync_params->drift_adjust_cmd = TS_DRIFT_ADJUST_SET;
13752         set_timesync_params->offset_cmd = TS_OFFSET_KEEP;
13753         set_timesync_params->add_sub_drift_adjust_value =
13754                 drift_dir ? TS_ADD_VALUE : TS_SUB_VALUE;
13755         set_timesync_params->drift_adjust_value = best_val;
13756         set_timesync_params->drift_adjust_period = best_period;
13757
13758         return bnx2x_func_state_change(bp, &func_params);
13759 }
13760
13761 static int bnx2x_ptp_adjfreq(struct ptp_clock_info *ptp, s32 ppb)
13762 {
13763         struct bnx2x *bp = container_of(ptp, struct bnx2x, ptp_clock_info);
13764         int rc;
13765         int drift_dir = 1;
13766         int val, period, period1, period2, dif, dif1, dif2;
13767         int best_dif = BNX2X_MAX_PHC_DRIFT, best_period = 0, best_val = 0;
13768
13769         DP(BNX2X_MSG_PTP, "PTP adjfreq called, ppb = %d\n", ppb);
13770
13771         if (!netif_running(bp->dev)) {
13772                 DP(BNX2X_MSG_PTP,
13773                    "PTP adjfreq called while the interface is down\n");
13774                 return -ENETDOWN;
13775         }
13776
13777         if (ppb < 0) {
13778                 ppb = -ppb;
13779                 drift_dir = 0;
13780         }
13781
13782         if (ppb == 0) {
13783                 best_val = 1;
13784                 best_period = 0x1FFFFFF;
13785         } else if (ppb >= BNX2X_MAX_PHC_DRIFT) {
13786                 best_val = 31;
13787                 best_period = 1;
13788         } else {
13789                 /* Changed not to allow val = 8, 16, 24 as these values
13790                  * are not supported in workaround.
13791                  */
13792                 for (val = 0; val <= 31; val++) {
13793                         if ((val & 0x7) == 0)
13794                                 continue;
13795                         period1 = val * 1000000 / ppb;
13796                         period2 = period1 + 1;
13797                         if (period1 != 0)
13798                                 dif1 = ppb - (val * 1000000 / period1);
13799                         else
13800                                 dif1 = BNX2X_MAX_PHC_DRIFT;
13801                         if (dif1 < 0)
13802                                 dif1 = -dif1;
13803                         dif2 = ppb - (val * 1000000 / period2);
13804                         if (dif2 < 0)
13805                                 dif2 = -dif2;
13806                         dif = (dif1 < dif2) ? dif1 : dif2;
13807                         period = (dif1 < dif2) ? period1 : period2;
13808                         if (dif < best_dif) {
13809                                 best_dif = dif;
13810                                 best_val = val;
13811                                 best_period = period;
13812                         }
13813                 }
13814         }
13815
13816         rc = bnx2x_send_update_drift_ramrod(bp, drift_dir, best_val,
13817                                             best_period);
13818         if (rc) {
13819                 BNX2X_ERR("Failed to set drift\n");
13820                 return -EFAULT;
13821         }
13822
13823         DP(BNX2X_MSG_PTP, "Configured val = %d, period = %d\n", best_val,
13824            best_period);
13825
13826         return 0;
13827 }
13828
13829 static int bnx2x_ptp_adjtime(struct ptp_clock_info *ptp, s64 delta)
13830 {
13831         struct bnx2x *bp = container_of(ptp, struct bnx2x, ptp_clock_info);
13832
13833         if (!netif_running(bp->dev)) {
13834                 DP(BNX2X_MSG_PTP,
13835                    "PTP adjtime called while the interface is down\n");
13836                 return -ENETDOWN;
13837         }
13838
13839         DP(BNX2X_MSG_PTP, "PTP adjtime called, delta = %llx\n", delta);
13840
13841         timecounter_adjtime(&bp->timecounter, delta);
13842
13843         return 0;
13844 }
13845
13846 static int bnx2x_ptp_gettime(struct ptp_clock_info *ptp, struct timespec64 *ts)
13847 {
13848         struct bnx2x *bp = container_of(ptp, struct bnx2x, ptp_clock_info);
13849         u64 ns;
13850
13851         if (!netif_running(bp->dev)) {
13852                 DP(BNX2X_MSG_PTP,
13853                    "PTP gettime called while the interface is down\n");
13854                 return -ENETDOWN;
13855         }
13856
13857         ns = timecounter_read(&bp->timecounter);
13858
13859         DP(BNX2X_MSG_PTP, "PTP gettime called, ns = %llu\n", ns);
13860
13861         *ts = ns_to_timespec64(ns);
13862
13863         return 0;
13864 }
13865
13866 static int bnx2x_ptp_settime(struct ptp_clock_info *ptp,
13867                              const struct timespec64 *ts)
13868 {
13869         struct bnx2x *bp = container_of(ptp, struct bnx2x, ptp_clock_info);
13870         u64 ns;
13871
13872         if (!netif_running(bp->dev)) {
13873                 DP(BNX2X_MSG_PTP,
13874                    "PTP settime called while the interface is down\n");
13875                 return -ENETDOWN;
13876         }
13877
13878         ns = timespec64_to_ns(ts);
13879
13880         DP(BNX2X_MSG_PTP, "PTP settime called, ns = %llu\n", ns);
13881
13882         /* Re-init the timecounter */
13883         timecounter_init(&bp->timecounter, &bp->cyclecounter, ns);
13884
13885         return 0;
13886 }
13887
13888 /* Enable (or disable) ancillary features of the phc subsystem */
13889 static int bnx2x_ptp_enable(struct ptp_clock_info *ptp,
13890                             struct ptp_clock_request *rq, int on)
13891 {
13892         struct bnx2x *bp = container_of(ptp, struct bnx2x, ptp_clock_info);
13893
13894         BNX2X_ERR("PHC ancillary features are not supported\n");
13895         return -ENOTSUPP;
13896 }
13897
13898 static void bnx2x_register_phc(struct bnx2x *bp)
13899 {
13900         /* Fill the ptp_clock_info struct and register PTP clock*/
13901         bp->ptp_clock_info.owner = THIS_MODULE;
13902         snprintf(bp->ptp_clock_info.name, 16, "%s", bp->dev->name);
13903         bp->ptp_clock_info.max_adj = BNX2X_MAX_PHC_DRIFT; /* In PPB */
13904         bp->ptp_clock_info.n_alarm = 0;
13905         bp->ptp_clock_info.n_ext_ts = 0;
13906         bp->ptp_clock_info.n_per_out = 0;
13907         bp->ptp_clock_info.pps = 0;
13908         bp->ptp_clock_info.adjfreq = bnx2x_ptp_adjfreq;
13909         bp->ptp_clock_info.adjtime = bnx2x_ptp_adjtime;
13910         bp->ptp_clock_info.gettime64 = bnx2x_ptp_gettime;
13911         bp->ptp_clock_info.settime64 = bnx2x_ptp_settime;
13912         bp->ptp_clock_info.enable = bnx2x_ptp_enable;
13913
13914         bp->ptp_clock = ptp_clock_register(&bp->ptp_clock_info, &bp->pdev->dev);
13915         if (IS_ERR(bp->ptp_clock)) {
13916                 bp->ptp_clock = NULL;
13917                 BNX2X_ERR("PTP clock registration failed\n");
13918         }
13919 }
13920
13921 static int bnx2x_init_one(struct pci_dev *pdev,
13922                                     const struct pci_device_id *ent)
13923 {
13924         struct net_device *dev = NULL;
13925         struct bnx2x *bp;
13926         int rc, max_non_def_sbs;
13927         int rx_count, tx_count, rss_count, doorbell_size;
13928         int max_cos_est;
13929         bool is_vf;
13930         int cnic_cnt;
13931
13932         /* Management FW 'remembers' living interfaces. Allow it some time
13933          * to forget previously living interfaces, allowing a proper re-load.
13934          */
13935         if (is_kdump_kernel()) {
13936                 ktime_t now = ktime_get_boottime();
13937                 ktime_t fw_ready_time = ktime_set(5, 0);
13938
13939                 if (ktime_before(now, fw_ready_time))
13940                         msleep(ktime_ms_delta(fw_ready_time, now));
13941         }
13942
13943         /* An estimated maximum supported CoS number according to the chip
13944          * version.
13945          * We will try to roughly estimate the maximum number of CoSes this chip
13946          * may support in order to minimize the memory allocated for Tx
13947          * netdev_queue's. This number will be accurately calculated during the
13948          * initialization of bp->max_cos based on the chip versions AND chip
13949          * revision in the bnx2x_init_bp().
13950          */
13951         max_cos_est = set_max_cos_est(ent->driver_data);
13952         if (max_cos_est < 0)
13953                 return max_cos_est;
13954         is_vf = set_is_vf(ent->driver_data);
13955         cnic_cnt = is_vf ? 0 : 1;
13956
13957         max_non_def_sbs = bnx2x_get_num_non_def_sbs(pdev, cnic_cnt);
13958
13959         /* add another SB for VF as it has no default SB */
13960         max_non_def_sbs += is_vf ? 1 : 0;
13961
13962         /* Maximum number of RSS queues: one IGU SB goes to CNIC */
13963         rss_count = max_non_def_sbs - cnic_cnt;
13964
13965         if (rss_count < 1)
13966                 return -EINVAL;
13967
13968         /* Maximum number of netdev Rx queues: RSS + FCoE L2 */
13969         rx_count = rss_count + cnic_cnt;
13970
13971         /* Maximum number of netdev Tx queues:
13972          * Maximum TSS queues * Maximum supported number of CoS  + FCoE L2
13973          */
13974         tx_count = rss_count * max_cos_est + cnic_cnt;
13975
13976         /* dev zeroed in init_etherdev */
13977         dev = alloc_etherdev_mqs(sizeof(*bp), tx_count, rx_count);
13978         if (!dev)
13979                 return -ENOMEM;
13980
13981         bp = netdev_priv(dev);
13982
13983         bp->flags = 0;
13984         if (is_vf)
13985                 bp->flags |= IS_VF_FLAG;
13986
13987         bp->igu_sb_cnt = max_non_def_sbs;
13988         bp->igu_base_addr = IS_VF(bp) ? PXP_VF_ADDR_IGU_START : BAR_IGU_INTMEM;
13989         bp->msg_enable = debug;
13990         bp->cnic_support = cnic_cnt;
13991         bp->cnic_probe = bnx2x_cnic_probe;
13992
13993         pci_set_drvdata(pdev, dev);
13994
13995         rc = bnx2x_init_dev(bp, pdev, dev, ent->driver_data);
13996         if (rc < 0) {
13997                 free_netdev(dev);
13998                 return rc;
13999         }
14000
14001         BNX2X_DEV_INFO("This is a %s function\n",
14002                        IS_PF(bp) ? "physical" : "virtual");
14003         BNX2X_DEV_INFO("Cnic support is %s\n", CNIC_SUPPORT(bp) ? "on" : "off");
14004         BNX2X_DEV_INFO("Max num of status blocks %d\n", max_non_def_sbs);
14005         BNX2X_DEV_INFO("Allocated netdev with %d tx and %d rx queues\n",
14006                        tx_count, rx_count);
14007
14008         rc = bnx2x_init_bp(bp);
14009         if (rc)
14010                 goto init_one_exit;
14011
14012         /* Map doorbells here as we need the real value of bp->max_cos which
14013          * is initialized in bnx2x_init_bp() to determine the number of
14014          * l2 connections.
14015          */
14016         if (IS_VF(bp)) {
14017                 bp->doorbells = bnx2x_vf_doorbells(bp);
14018                 rc = bnx2x_vf_pci_alloc(bp);
14019                 if (rc)
14020                         goto init_one_freemem;
14021         } else {
14022                 doorbell_size = BNX2X_L2_MAX_CID(bp) * (1 << BNX2X_DB_SHIFT);
14023                 if (doorbell_size > pci_resource_len(pdev, 2)) {
14024                         dev_err(&bp->pdev->dev,
14025                                 "Cannot map doorbells, bar size too small, aborting\n");
14026                         rc = -ENOMEM;
14027                         goto init_one_freemem;
14028                 }
14029                 bp->doorbells = ioremap_nocache(pci_resource_start(pdev, 2),
14030                                                 doorbell_size);
14031         }
14032         if (!bp->doorbells) {
14033                 dev_err(&bp->pdev->dev,
14034                         "Cannot map doorbell space, aborting\n");
14035                 rc = -ENOMEM;
14036                 goto init_one_freemem;
14037         }
14038
14039         if (IS_VF(bp)) {
14040                 rc = bnx2x_vfpf_acquire(bp, tx_count, rx_count);
14041                 if (rc)
14042                         goto init_one_freemem;
14043
14044 #ifdef CONFIG_BNX2X_SRIOV
14045                 /* VF with OLD Hypervisor or old PF do not support filtering */
14046                 if (bp->acquire_resp.pfdev_info.pf_cap & PFVF_CAP_VLAN_FILTER) {
14047                         dev->hw_features |= NETIF_F_HW_VLAN_CTAG_FILTER;
14048                         dev->features |= NETIF_F_HW_VLAN_CTAG_FILTER;
14049                 }
14050 #endif
14051         }
14052
14053         /* Enable SRIOV if capability found in configuration space */
14054         rc = bnx2x_iov_init_one(bp, int_mode, BNX2X_MAX_NUM_OF_VFS);
14055         if (rc)
14056                 goto init_one_freemem;
14057
14058         /* calc qm_cid_count */
14059         bp->qm_cid_count = bnx2x_set_qm_cid_count(bp);
14060         BNX2X_DEV_INFO("qm_cid_count %d\n", bp->qm_cid_count);
14061
14062         /* disable FCOE L2 queue for E1x*/
14063         if (CHIP_IS_E1x(bp))
14064                 bp->flags |= NO_FCOE_FLAG;
14065
14066         /* Set bp->num_queues for MSI-X mode*/
14067         bnx2x_set_num_queues(bp);
14068
14069         /* Configure interrupt mode: try to enable MSI-X/MSI if
14070          * needed.
14071          */
14072         rc = bnx2x_set_int_mode(bp);
14073         if (rc) {
14074                 dev_err(&pdev->dev, "Cannot set interrupts\n");
14075                 goto init_one_freemem;
14076         }
14077         BNX2X_DEV_INFO("set interrupts successfully\n");
14078
14079         /* register the net device */
14080         rc = register_netdev(dev);
14081         if (rc) {
14082                 dev_err(&pdev->dev, "Cannot register net device\n");
14083                 goto init_one_freemem;
14084         }
14085         BNX2X_DEV_INFO("device name after netdev register %s\n", dev->name);
14086
14087         if (!NO_FCOE(bp)) {
14088                 /* Add storage MAC address */
14089                 rtnl_lock();
14090                 dev_addr_add(bp->dev, bp->fip_mac, NETDEV_HW_ADDR_T_SAN);
14091                 rtnl_unlock();
14092         }
14093         BNX2X_DEV_INFO(
14094                "%s (%c%d) PCI-E found at mem %lx, IRQ %d, node addr %pM\n",
14095                board_info[ent->driver_data].name,
14096                (CHIP_REV(bp) >> 12) + 'A', (CHIP_METAL(bp) >> 4),
14097                dev->base_addr, bp->pdev->irq, dev->dev_addr);
14098         pcie_print_link_status(bp->pdev);
14099
14100         bnx2x_register_phc(bp);
14101
14102         if (!IS_MF_SD_STORAGE_PERSONALITY_ONLY(bp))
14103                 bnx2x_set_os_driver_state(bp, OS_DRIVER_STATE_DISABLED);
14104
14105         return 0;
14106
14107 init_one_freemem:
14108         bnx2x_free_mem_bp(bp);
14109
14110 init_one_exit:
14111         bnx2x_disable_pcie_error_reporting(bp);
14112
14113         if (bp->regview)
14114                 iounmap(bp->regview);
14115
14116         if (IS_PF(bp) && bp->doorbells)
14117                 iounmap(bp->doorbells);
14118
14119         free_netdev(dev);
14120
14121         if (atomic_read(&pdev->enable_cnt) == 1)
14122                 pci_release_regions(pdev);
14123
14124         pci_disable_device(pdev);
14125
14126         return rc;
14127 }
14128
14129 static void __bnx2x_remove(struct pci_dev *pdev,
14130                            struct net_device *dev,
14131                            struct bnx2x *bp,
14132                            bool remove_netdev)
14133 {
14134         if (bp->ptp_clock) {
14135                 ptp_clock_unregister(bp->ptp_clock);
14136                 bp->ptp_clock = NULL;
14137         }
14138
14139         /* Delete storage MAC address */
14140         if (!NO_FCOE(bp)) {
14141                 rtnl_lock();
14142                 dev_addr_del(bp->dev, bp->fip_mac, NETDEV_HW_ADDR_T_SAN);
14143                 rtnl_unlock();
14144         }
14145
14146 #ifdef BCM_DCBNL
14147         /* Delete app tlvs from dcbnl */
14148         bnx2x_dcbnl_update_applist(bp, true);
14149 #endif
14150
14151         if (IS_PF(bp) &&
14152             !BP_NOMCP(bp) &&
14153             (bp->flags & BC_SUPPORTS_RMMOD_CMD))
14154                 bnx2x_fw_command(bp, DRV_MSG_CODE_RMMOD, 0);
14155
14156         /* Close the interface - either directly or implicitly */
14157         if (remove_netdev) {
14158                 unregister_netdev(dev);
14159         } else {
14160                 rtnl_lock();
14161                 dev_close(dev);
14162                 rtnl_unlock();
14163         }
14164
14165         bnx2x_iov_remove_one(bp);
14166
14167         /* Power on: we can't let PCI layer write to us while we are in D3 */
14168         if (IS_PF(bp)) {
14169                 bnx2x_set_power_state(bp, PCI_D0);
14170                 bnx2x_set_os_driver_state(bp, OS_DRIVER_STATE_NOT_LOADED);
14171
14172                 /* Set endianity registers to reset values in case next driver
14173                  * boots in different endianty environment.
14174                  */
14175                 bnx2x_reset_endianity(bp);
14176         }
14177
14178         /* Disable MSI/MSI-X */
14179         bnx2x_disable_msi(bp);
14180
14181         /* Power off */
14182         if (IS_PF(bp))
14183                 bnx2x_set_power_state(bp, PCI_D3hot);
14184
14185         /* Make sure RESET task is not scheduled before continuing */
14186         cancel_delayed_work_sync(&bp->sp_rtnl_task);
14187
14188         /* send message via vfpf channel to release the resources of this vf */
14189         if (IS_VF(bp))
14190                 bnx2x_vfpf_release(bp);
14191
14192         /* Assumes no further PCIe PM changes will occur */
14193         if (system_state == SYSTEM_POWER_OFF) {
14194                 pci_wake_from_d3(pdev, bp->wol);
14195                 pci_set_power_state(pdev, PCI_D3hot);
14196         }
14197
14198         bnx2x_disable_pcie_error_reporting(bp);
14199         if (remove_netdev) {
14200                 if (bp->regview)
14201                         iounmap(bp->regview);
14202
14203                 /* For vfs, doorbells are part of the regview and were unmapped
14204                  * along with it. FW is only loaded by PF.
14205                  */
14206                 if (IS_PF(bp)) {
14207                         if (bp->doorbells)
14208                                 iounmap(bp->doorbells);
14209
14210                         bnx2x_release_firmware(bp);
14211                 } else {
14212                         bnx2x_vf_pci_dealloc(bp);
14213                 }
14214                 bnx2x_free_mem_bp(bp);
14215
14216                 free_netdev(dev);
14217
14218                 if (atomic_read(&pdev->enable_cnt) == 1)
14219                         pci_release_regions(pdev);
14220
14221                 pci_disable_device(pdev);
14222         }
14223 }
14224
14225 static void bnx2x_remove_one(struct pci_dev *pdev)
14226 {
14227         struct net_device *dev = pci_get_drvdata(pdev);
14228         struct bnx2x *bp;
14229
14230         if (!dev) {
14231                 dev_err(&pdev->dev, "BAD net device from bnx2x_init_one\n");
14232                 return;
14233         }
14234         bp = netdev_priv(dev);
14235
14236         __bnx2x_remove(pdev, dev, bp, true);
14237 }
14238
14239 static int bnx2x_eeh_nic_unload(struct bnx2x *bp)
14240 {
14241         bp->state = BNX2X_STATE_CLOSING_WAIT4_HALT;
14242
14243         bp->rx_mode = BNX2X_RX_MODE_NONE;
14244
14245         if (CNIC_LOADED(bp))
14246                 bnx2x_cnic_notify(bp, CNIC_CTL_STOP_CMD);
14247
14248         /* Stop Tx */
14249         bnx2x_tx_disable(bp);
14250         /* Delete all NAPI objects */
14251         bnx2x_del_all_napi(bp);
14252         if (CNIC_LOADED(bp))
14253                 bnx2x_del_all_napi_cnic(bp);
14254         netdev_reset_tc(bp->dev);
14255
14256         del_timer_sync(&bp->timer);
14257         cancel_delayed_work_sync(&bp->sp_task);
14258         cancel_delayed_work_sync(&bp->period_task);
14259
14260         if (!down_timeout(&bp->stats_lock, HZ / 10)) {
14261                 bp->stats_state = STATS_STATE_DISABLED;
14262                 up(&bp->stats_lock);
14263         }
14264
14265         bnx2x_save_statistics(bp);
14266
14267         netif_carrier_off(bp->dev);
14268
14269         return 0;
14270 }
14271
14272 /**
14273  * bnx2x_io_error_detected - called when PCI error is detected
14274  * @pdev: Pointer to PCI device
14275  * @state: The current pci connection state
14276  *
14277  * This function is called after a PCI bus error affecting
14278  * this device has been detected.
14279  */
14280 static pci_ers_result_t bnx2x_io_error_detected(struct pci_dev *pdev,
14281                                                 pci_channel_state_t state)
14282 {
14283         struct net_device *dev = pci_get_drvdata(pdev);
14284         struct bnx2x *bp = netdev_priv(dev);
14285
14286         rtnl_lock();
14287
14288         BNX2X_ERR("IO error detected\n");
14289
14290         netif_device_detach(dev);
14291
14292         if (state == pci_channel_io_perm_failure) {
14293                 rtnl_unlock();
14294                 return PCI_ERS_RESULT_DISCONNECT;
14295         }
14296
14297         if (netif_running(dev))
14298                 bnx2x_eeh_nic_unload(bp);
14299
14300         bnx2x_prev_path_mark_eeh(bp);
14301
14302         pci_disable_device(pdev);
14303
14304         rtnl_unlock();
14305
14306         /* Request a slot reset */
14307         return PCI_ERS_RESULT_NEED_RESET;
14308 }
14309
14310 /**
14311  * bnx2x_io_slot_reset - called after the PCI bus has been reset
14312  * @pdev: Pointer to PCI device
14313  *
14314  * Restart the card from scratch, as if from a cold-boot.
14315  */
14316 static pci_ers_result_t bnx2x_io_slot_reset(struct pci_dev *pdev)
14317 {
14318         struct net_device *dev = pci_get_drvdata(pdev);
14319         struct bnx2x *bp = netdev_priv(dev);
14320         int i;
14321
14322         rtnl_lock();
14323         BNX2X_ERR("IO slot reset initializing...\n");
14324         if (pci_enable_device(pdev)) {
14325                 dev_err(&pdev->dev,
14326                         "Cannot re-enable PCI device after reset\n");
14327                 rtnl_unlock();
14328                 return PCI_ERS_RESULT_DISCONNECT;
14329         }
14330
14331         pci_set_master(pdev);
14332         pci_restore_state(pdev);
14333         pci_save_state(pdev);
14334
14335         if (netif_running(dev))
14336                 bnx2x_set_power_state(bp, PCI_D0);
14337
14338         if (netif_running(dev)) {
14339                 BNX2X_ERR("IO slot reset --> driver unload\n");
14340
14341                 /* MCP should have been reset; Need to wait for validity */
14342                 if (bnx2x_init_shmem(bp)) {
14343                         rtnl_unlock();
14344                         return PCI_ERS_RESULT_DISCONNECT;
14345                 }
14346
14347                 if (IS_PF(bp) && SHMEM2_HAS(bp, drv_capabilities_flag)) {
14348                         u32 v;
14349
14350                         v = SHMEM2_RD(bp,
14351                                       drv_capabilities_flag[BP_FW_MB_IDX(bp)]);
14352                         SHMEM2_WR(bp, drv_capabilities_flag[BP_FW_MB_IDX(bp)],
14353                                   v & ~DRV_FLAGS_CAPABILITIES_LOADED_L2);
14354                 }
14355                 bnx2x_drain_tx_queues(bp);
14356                 bnx2x_send_unload_req(bp, UNLOAD_RECOVERY);
14357                 bnx2x_netif_stop(bp, 1);
14358                 bnx2x_free_irq(bp);
14359
14360                 /* Report UNLOAD_DONE to MCP */
14361                 bnx2x_send_unload_done(bp, true);
14362
14363                 bp->sp_state = 0;
14364                 bp->port.pmf = 0;
14365
14366                 bnx2x_prev_unload(bp);
14367
14368                 /* We should have reseted the engine, so It's fair to
14369                  * assume the FW will no longer write to the bnx2x driver.
14370                  */
14371                 bnx2x_squeeze_objects(bp);
14372                 bnx2x_free_skbs(bp);
14373                 for_each_rx_queue(bp, i)
14374                         bnx2x_free_rx_sge_range(bp, bp->fp + i, NUM_RX_SGE);
14375                 bnx2x_free_fp_mem(bp);
14376                 bnx2x_free_mem(bp);
14377
14378                 bp->state = BNX2X_STATE_CLOSED;
14379         }
14380
14381         rtnl_unlock();
14382
14383         return PCI_ERS_RESULT_RECOVERED;
14384 }
14385
14386 /**
14387  * bnx2x_io_resume - called when traffic can start flowing again
14388  * @pdev: Pointer to PCI device
14389  *
14390  * This callback is called when the error recovery driver tells us that
14391  * its OK to resume normal operation.
14392  */
14393 static void bnx2x_io_resume(struct pci_dev *pdev)
14394 {
14395         struct net_device *dev = pci_get_drvdata(pdev);
14396         struct bnx2x *bp = netdev_priv(dev);
14397
14398         if (bp->recovery_state != BNX2X_RECOVERY_DONE) {
14399                 netdev_err(bp->dev, "Handling parity error recovery. Try again later\n");
14400                 return;
14401         }
14402
14403         rtnl_lock();
14404
14405         bp->fw_seq = SHMEM_RD(bp, func_mb[BP_FW_MB_IDX(bp)].drv_mb_header) &
14406                                                         DRV_MSG_SEQ_NUMBER_MASK;
14407
14408         if (netif_running(dev))
14409                 bnx2x_nic_load(bp, LOAD_NORMAL);
14410
14411         netif_device_attach(dev);
14412
14413         rtnl_unlock();
14414 }
14415
14416 static const struct pci_error_handlers bnx2x_err_handler = {
14417         .error_detected = bnx2x_io_error_detected,
14418         .slot_reset     = bnx2x_io_slot_reset,
14419         .resume         = bnx2x_io_resume,
14420 };
14421
14422 static void bnx2x_shutdown(struct pci_dev *pdev)
14423 {
14424         struct net_device *dev = pci_get_drvdata(pdev);
14425         struct bnx2x *bp;
14426
14427         if (!dev)
14428                 return;
14429
14430         bp = netdev_priv(dev);
14431         if (!bp)
14432                 return;
14433
14434         rtnl_lock();
14435         netif_device_detach(dev);
14436         rtnl_unlock();
14437
14438         /* Don't remove the netdevice, as there are scenarios which will cause
14439          * the kernel to hang, e.g., when trying to remove bnx2i while the
14440          * rootfs is mounted from SAN.
14441          */
14442         __bnx2x_remove(pdev, dev, bp, false);
14443 }
14444
14445 static struct pci_driver bnx2x_pci_driver = {
14446         .name        = DRV_MODULE_NAME,
14447         .id_table    = bnx2x_pci_tbl,
14448         .probe       = bnx2x_init_one,
14449         .remove      = bnx2x_remove_one,
14450         .suspend     = bnx2x_suspend,
14451         .resume      = bnx2x_resume,
14452         .err_handler = &bnx2x_err_handler,
14453 #ifdef CONFIG_BNX2X_SRIOV
14454         .sriov_configure = bnx2x_sriov_configure,
14455 #endif
14456         .shutdown    = bnx2x_shutdown,
14457 };
14458
14459 static int __init bnx2x_init(void)
14460 {
14461         int ret;
14462
14463         pr_info("%s", version);
14464
14465         bnx2x_wq = create_singlethread_workqueue("bnx2x");
14466         if (bnx2x_wq == NULL) {
14467                 pr_err("Cannot create workqueue\n");
14468                 return -ENOMEM;
14469         }
14470         bnx2x_iov_wq = create_singlethread_workqueue("bnx2x_iov");
14471         if (!bnx2x_iov_wq) {
14472                 pr_err("Cannot create iov workqueue\n");
14473                 destroy_workqueue(bnx2x_wq);
14474                 return -ENOMEM;
14475         }
14476
14477         ret = pci_register_driver(&bnx2x_pci_driver);
14478         if (ret) {
14479                 pr_err("Cannot register driver\n");
14480                 destroy_workqueue(bnx2x_wq);
14481                 destroy_workqueue(bnx2x_iov_wq);
14482         }
14483         return ret;
14484 }
14485
14486 static void __exit bnx2x_cleanup(void)
14487 {
14488         struct list_head *pos, *q;
14489
14490         pci_unregister_driver(&bnx2x_pci_driver);
14491
14492         destroy_workqueue(bnx2x_wq);
14493         destroy_workqueue(bnx2x_iov_wq);
14494
14495         /* Free globally allocated resources */
14496         list_for_each_safe(pos, q, &bnx2x_prev_list) {
14497                 struct bnx2x_prev_path_list *tmp =
14498                         list_entry(pos, struct bnx2x_prev_path_list, list);
14499                 list_del(pos);
14500                 kfree(tmp);
14501         }
14502 }
14503
14504 void bnx2x_notify_link_changed(struct bnx2x *bp)
14505 {
14506         REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_12 + BP_FUNC(bp)*sizeof(u32), 1);
14507 }
14508
14509 module_init(bnx2x_init);
14510 module_exit(bnx2x_cleanup);
14511
14512 /**
14513  * bnx2x_set_iscsi_eth_mac_addr - set iSCSI MAC(s).
14514  *
14515  * @bp:         driver handle
14516  * @set:        set or clear the CAM entry
14517  *
14518  * This function will wait until the ramrod completion returns.
14519  * Return 0 if success, -ENODEV if ramrod doesn't return.
14520  */
14521 static int bnx2x_set_iscsi_eth_mac_addr(struct bnx2x *bp)
14522 {
14523         unsigned long ramrod_flags = 0;
14524
14525         __set_bit(RAMROD_COMP_WAIT, &ramrod_flags);
14526         return bnx2x_set_mac_one(bp, bp->cnic_eth_dev.iscsi_mac,
14527                                  &bp->iscsi_l2_mac_obj, true,
14528                                  BNX2X_ISCSI_ETH_MAC, &ramrod_flags);
14529 }
14530
14531 /* count denotes the number of new completions we have seen */
14532 static void bnx2x_cnic_sp_post(struct bnx2x *bp, int count)
14533 {
14534         struct eth_spe *spe;
14535         int cxt_index, cxt_offset;
14536
14537 #ifdef BNX2X_STOP_ON_ERROR
14538         if (unlikely(bp->panic))
14539                 return;
14540 #endif
14541
14542         spin_lock_bh(&bp->spq_lock);
14543         BUG_ON(bp->cnic_spq_pending < count);
14544         bp->cnic_spq_pending -= count;
14545
14546         for (; bp->cnic_kwq_pending; bp->cnic_kwq_pending--) {
14547                 u16 type =  (le16_to_cpu(bp->cnic_kwq_cons->hdr.type)
14548                                 & SPE_HDR_CONN_TYPE) >>
14549                                 SPE_HDR_CONN_TYPE_SHIFT;
14550                 u8 cmd = (le32_to_cpu(bp->cnic_kwq_cons->hdr.conn_and_cmd_data)
14551                                 >> SPE_HDR_CMD_ID_SHIFT) & 0xff;
14552
14553                 /* Set validation for iSCSI L2 client before sending SETUP
14554                  *  ramrod
14555                  */
14556                 if (type == ETH_CONNECTION_TYPE) {
14557                         if (cmd == RAMROD_CMD_ID_ETH_CLIENT_SETUP) {
14558                                 cxt_index = BNX2X_ISCSI_ETH_CID(bp) /
14559                                         ILT_PAGE_CIDS;
14560                                 cxt_offset = BNX2X_ISCSI_ETH_CID(bp) -
14561                                         (cxt_index * ILT_PAGE_CIDS);
14562                                 bnx2x_set_ctx_validation(bp,
14563                                         &bp->context[cxt_index].
14564                                                          vcxt[cxt_offset].eth,
14565                                         BNX2X_ISCSI_ETH_CID(bp));
14566                         }
14567                 }
14568
14569                 /*
14570                  * There may be not more than 8 L2, not more than 8 L5 SPEs
14571                  * and in the air. We also check that number of outstanding
14572                  * COMMON ramrods is not more than the EQ and SPQ can
14573                  * accommodate.
14574                  */
14575                 if (type == ETH_CONNECTION_TYPE) {
14576                         if (!atomic_read(&bp->cq_spq_left))
14577                                 break;
14578                         else
14579                                 atomic_dec(&bp->cq_spq_left);
14580                 } else if (type == NONE_CONNECTION_TYPE) {
14581                         if (!atomic_read(&bp->eq_spq_left))
14582                                 break;
14583                         else
14584                                 atomic_dec(&bp->eq_spq_left);
14585                 } else if ((type == ISCSI_CONNECTION_TYPE) ||
14586                            (type == FCOE_CONNECTION_TYPE)) {
14587                         if (bp->cnic_spq_pending >=
14588                             bp->cnic_eth_dev.max_kwqe_pending)
14589                                 break;
14590                         else
14591                                 bp->cnic_spq_pending++;
14592                 } else {
14593                         BNX2X_ERR("Unknown SPE type: %d\n", type);
14594                         bnx2x_panic();
14595                         break;
14596                 }
14597
14598                 spe = bnx2x_sp_get_next(bp);
14599                 *spe = *bp->cnic_kwq_cons;
14600
14601                 DP(BNX2X_MSG_SP, "pending on SPQ %d, on KWQ %d count %d\n",
14602                    bp->cnic_spq_pending, bp->cnic_kwq_pending, count);
14603
14604                 if (bp->cnic_kwq_cons == bp->cnic_kwq_last)
14605                         bp->cnic_kwq_cons = bp->cnic_kwq;
14606                 else
14607                         bp->cnic_kwq_cons++;
14608         }
14609         bnx2x_sp_prod_update(bp);
14610         spin_unlock_bh(&bp->spq_lock);
14611 }
14612
14613 static int bnx2x_cnic_sp_queue(struct net_device *dev,
14614                                struct kwqe_16 *kwqes[], u32 count)
14615 {
14616         struct bnx2x *bp = netdev_priv(dev);
14617         int i;
14618
14619 #ifdef BNX2X_STOP_ON_ERROR
14620         if (unlikely(bp->panic)) {
14621                 BNX2X_ERR("Can't post to SP queue while panic\n");
14622                 return -EIO;
14623         }
14624 #endif
14625
14626         if ((bp->recovery_state != BNX2X_RECOVERY_DONE) &&
14627             (bp->recovery_state != BNX2X_RECOVERY_NIC_LOADING)) {
14628                 BNX2X_ERR("Handling parity error recovery. Try again later\n");
14629                 return -EAGAIN;
14630         }
14631
14632         spin_lock_bh(&bp->spq_lock);
14633
14634         for (i = 0; i < count; i++) {
14635                 struct eth_spe *spe = (struct eth_spe *)kwqes[i];
14636
14637                 if (bp->cnic_kwq_pending == MAX_SP_DESC_CNT)
14638                         break;
14639
14640                 *bp->cnic_kwq_prod = *spe;
14641
14642                 bp->cnic_kwq_pending++;
14643
14644                 DP(BNX2X_MSG_SP, "L5 SPQE %x %x %x:%x pos %d\n",
14645                    spe->hdr.conn_and_cmd_data, spe->hdr.type,
14646                    spe->data.update_data_addr.hi,
14647                    spe->data.update_data_addr.lo,
14648                    bp->cnic_kwq_pending);
14649
14650                 if (bp->cnic_kwq_prod == bp->cnic_kwq_last)
14651                         bp->cnic_kwq_prod = bp->cnic_kwq;
14652                 else
14653                         bp->cnic_kwq_prod++;
14654         }
14655
14656         spin_unlock_bh(&bp->spq_lock);
14657
14658         if (bp->cnic_spq_pending < bp->cnic_eth_dev.max_kwqe_pending)
14659                 bnx2x_cnic_sp_post(bp, 0);
14660
14661         return i;
14662 }
14663
14664 static int bnx2x_cnic_ctl_send(struct bnx2x *bp, struct cnic_ctl_info *ctl)
14665 {
14666         struct cnic_ops *c_ops;
14667         int rc = 0;
14668
14669         mutex_lock(&bp->cnic_mutex);
14670         c_ops = rcu_dereference_protected(bp->cnic_ops,
14671                                           lockdep_is_held(&bp->cnic_mutex));
14672         if (c_ops)
14673                 rc = c_ops->cnic_ctl(bp->cnic_data, ctl);
14674         mutex_unlock(&bp->cnic_mutex);
14675
14676         return rc;
14677 }
14678
14679 static int bnx2x_cnic_ctl_send_bh(struct bnx2x *bp, struct cnic_ctl_info *ctl)
14680 {
14681         struct cnic_ops *c_ops;
14682         int rc = 0;
14683
14684         rcu_read_lock();
14685         c_ops = rcu_dereference(bp->cnic_ops);
14686         if (c_ops)
14687                 rc = c_ops->cnic_ctl(bp->cnic_data, ctl);
14688         rcu_read_unlock();
14689
14690         return rc;
14691 }
14692
14693 /*
14694  * for commands that have no data
14695  */
14696 int bnx2x_cnic_notify(struct bnx2x *bp, int cmd)
14697 {
14698         struct cnic_ctl_info ctl = {0};
14699
14700         ctl.cmd = cmd;
14701
14702         return bnx2x_cnic_ctl_send(bp, &ctl);
14703 }
14704
14705 static void bnx2x_cnic_cfc_comp(struct bnx2x *bp, int cid, u8 err)
14706 {
14707         struct cnic_ctl_info ctl = {0};
14708
14709         /* first we tell CNIC and only then we count this as a completion */
14710         ctl.cmd = CNIC_CTL_COMPLETION_CMD;
14711         ctl.data.comp.cid = cid;
14712         ctl.data.comp.error = err;
14713
14714         bnx2x_cnic_ctl_send_bh(bp, &ctl);
14715         bnx2x_cnic_sp_post(bp, 0);
14716 }
14717
14718 /* Called with netif_addr_lock_bh() taken.
14719  * Sets an rx_mode config for an iSCSI ETH client.
14720  * Doesn't block.
14721  * Completion should be checked outside.
14722  */
14723 static void bnx2x_set_iscsi_eth_rx_mode(struct bnx2x *bp, bool start)
14724 {
14725         unsigned long accept_flags = 0, ramrod_flags = 0;
14726         u8 cl_id = bnx2x_cnic_eth_cl_id(bp, BNX2X_ISCSI_ETH_CL_ID_IDX);
14727         int sched_state = BNX2X_FILTER_ISCSI_ETH_STOP_SCHED;
14728
14729         if (start) {
14730                 /* Start accepting on iSCSI L2 ring. Accept all multicasts
14731                  * because it's the only way for UIO Queue to accept
14732                  * multicasts (in non-promiscuous mode only one Queue per
14733                  * function will receive multicast packets (leading in our
14734                  * case).
14735                  */
14736                 __set_bit(BNX2X_ACCEPT_UNICAST, &accept_flags);
14737                 __set_bit(BNX2X_ACCEPT_ALL_MULTICAST, &accept_flags);
14738                 __set_bit(BNX2X_ACCEPT_BROADCAST, &accept_flags);
14739                 __set_bit(BNX2X_ACCEPT_ANY_VLAN, &accept_flags);
14740
14741                 /* Clear STOP_PENDING bit if START is requested */
14742                 clear_bit(BNX2X_FILTER_ISCSI_ETH_STOP_SCHED, &bp->sp_state);
14743
14744                 sched_state = BNX2X_FILTER_ISCSI_ETH_START_SCHED;
14745         } else
14746                 /* Clear START_PENDING bit if STOP is requested */
14747                 clear_bit(BNX2X_FILTER_ISCSI_ETH_START_SCHED, &bp->sp_state);
14748
14749         if (test_bit(BNX2X_FILTER_RX_MODE_PENDING, &bp->sp_state))
14750                 set_bit(sched_state, &bp->sp_state);
14751         else {
14752                 __set_bit(RAMROD_RX, &ramrod_flags);
14753                 bnx2x_set_q_rx_mode(bp, cl_id, 0, accept_flags, 0,
14754                                     ramrod_flags);
14755         }
14756 }
14757
14758 static int bnx2x_drv_ctl(struct net_device *dev, struct drv_ctl_info *ctl)
14759 {
14760         struct bnx2x *bp = netdev_priv(dev);
14761         int rc = 0;
14762
14763         switch (ctl->cmd) {
14764         case DRV_CTL_CTXTBL_WR_CMD: {
14765                 u32 index = ctl->data.io.offset;
14766                 dma_addr_t addr = ctl->data.io.dma_addr;
14767
14768                 bnx2x_ilt_wr(bp, index, addr);
14769                 break;
14770         }
14771
14772         case DRV_CTL_RET_L5_SPQ_CREDIT_CMD: {
14773                 int count = ctl->data.credit.credit_count;
14774
14775                 bnx2x_cnic_sp_post(bp, count);
14776                 break;
14777         }
14778
14779         /* rtnl_lock is held.  */
14780         case DRV_CTL_START_L2_CMD: {
14781                 struct cnic_eth_dev *cp = &bp->cnic_eth_dev;
14782                 unsigned long sp_bits = 0;
14783
14784                 /* Configure the iSCSI classification object */
14785                 bnx2x_init_mac_obj(bp, &bp->iscsi_l2_mac_obj,
14786                                    cp->iscsi_l2_client_id,
14787                                    cp->iscsi_l2_cid, BP_FUNC(bp),
14788                                    bnx2x_sp(bp, mac_rdata),
14789                                    bnx2x_sp_mapping(bp, mac_rdata),
14790                                    BNX2X_FILTER_MAC_PENDING,
14791                                    &bp->sp_state, BNX2X_OBJ_TYPE_RX,
14792                                    &bp->macs_pool);
14793
14794                 /* Set iSCSI MAC address */
14795                 rc = bnx2x_set_iscsi_eth_mac_addr(bp);
14796                 if (rc)
14797                         break;
14798
14799                 mmiowb();
14800                 barrier();
14801
14802                 /* Start accepting on iSCSI L2 ring */
14803
14804                 netif_addr_lock_bh(dev);
14805                 bnx2x_set_iscsi_eth_rx_mode(bp, true);
14806                 netif_addr_unlock_bh(dev);
14807
14808                 /* bits to wait on */
14809                 __set_bit(BNX2X_FILTER_RX_MODE_PENDING, &sp_bits);
14810                 __set_bit(BNX2X_FILTER_ISCSI_ETH_START_SCHED, &sp_bits);
14811
14812                 if (!bnx2x_wait_sp_comp(bp, sp_bits))
14813                         BNX2X_ERR("rx_mode completion timed out!\n");
14814
14815                 break;
14816         }
14817
14818         /* rtnl_lock is held.  */
14819         case DRV_CTL_STOP_L2_CMD: {
14820                 unsigned long sp_bits = 0;
14821
14822                 /* Stop accepting on iSCSI L2 ring */
14823                 netif_addr_lock_bh(dev);
14824                 bnx2x_set_iscsi_eth_rx_mode(bp, false);
14825                 netif_addr_unlock_bh(dev);
14826
14827                 /* bits to wait on */
14828                 __set_bit(BNX2X_FILTER_RX_MODE_PENDING, &sp_bits);
14829                 __set_bit(BNX2X_FILTER_ISCSI_ETH_STOP_SCHED, &sp_bits);
14830
14831                 if (!bnx2x_wait_sp_comp(bp, sp_bits))
14832                         BNX2X_ERR("rx_mode completion timed out!\n");
14833
14834                 mmiowb();
14835                 barrier();
14836
14837                 /* Unset iSCSI L2 MAC */
14838                 rc = bnx2x_del_all_macs(bp, &bp->iscsi_l2_mac_obj,
14839                                         BNX2X_ISCSI_ETH_MAC, true);
14840                 break;
14841         }
14842         case DRV_CTL_RET_L2_SPQ_CREDIT_CMD: {
14843                 int count = ctl->data.credit.credit_count;
14844
14845                 smp_mb__before_atomic();
14846                 atomic_add(count, &bp->cq_spq_left);
14847                 smp_mb__after_atomic();
14848                 break;
14849         }
14850         case DRV_CTL_ULP_REGISTER_CMD: {
14851                 int ulp_type = ctl->data.register_data.ulp_type;
14852
14853                 if (CHIP_IS_E3(bp)) {
14854                         int idx = BP_FW_MB_IDX(bp);
14855                         u32 cap = SHMEM2_RD(bp, drv_capabilities_flag[idx]);
14856                         int path = BP_PATH(bp);
14857                         int port = BP_PORT(bp);
14858                         int i;
14859                         u32 scratch_offset;
14860                         u32 *host_addr;
14861
14862                         /* first write capability to shmem2 */
14863                         if (ulp_type == CNIC_ULP_ISCSI)
14864                                 cap |= DRV_FLAGS_CAPABILITIES_LOADED_ISCSI;
14865                         else if (ulp_type == CNIC_ULP_FCOE)
14866                                 cap |= DRV_FLAGS_CAPABILITIES_LOADED_FCOE;
14867                         SHMEM2_WR(bp, drv_capabilities_flag[idx], cap);
14868
14869                         if ((ulp_type != CNIC_ULP_FCOE) ||
14870                             (!SHMEM2_HAS(bp, ncsi_oem_data_addr)) ||
14871                             (!(bp->flags &  BC_SUPPORTS_FCOE_FEATURES)))
14872                                 break;
14873
14874                         /* if reached here - should write fcoe capabilities */
14875                         scratch_offset = SHMEM2_RD(bp, ncsi_oem_data_addr);
14876                         if (!scratch_offset)
14877                                 break;
14878                         scratch_offset += offsetof(struct glob_ncsi_oem_data,
14879                                                    fcoe_features[path][port]);
14880                         host_addr = (u32 *) &(ctl->data.register_data.
14881                                               fcoe_features);
14882                         for (i = 0; i < sizeof(struct fcoe_capabilities);
14883                              i += 4)
14884                                 REG_WR(bp, scratch_offset + i,
14885                                        *(host_addr + i/4));
14886                 }
14887                 bnx2x_schedule_sp_rtnl(bp, BNX2X_SP_RTNL_GET_DRV_VERSION, 0);
14888                 break;
14889         }
14890
14891         case DRV_CTL_ULP_UNREGISTER_CMD: {
14892                 int ulp_type = ctl->data.ulp_type;
14893
14894                 if (CHIP_IS_E3(bp)) {
14895                         int idx = BP_FW_MB_IDX(bp);
14896                         u32 cap;
14897
14898                         cap = SHMEM2_RD(bp, drv_capabilities_flag[idx]);
14899                         if (ulp_type == CNIC_ULP_ISCSI)
14900                                 cap &= ~DRV_FLAGS_CAPABILITIES_LOADED_ISCSI;
14901                         else if (ulp_type == CNIC_ULP_FCOE)
14902                                 cap &= ~DRV_FLAGS_CAPABILITIES_LOADED_FCOE;
14903                         SHMEM2_WR(bp, drv_capabilities_flag[idx], cap);
14904                 }
14905                 bnx2x_schedule_sp_rtnl(bp, BNX2X_SP_RTNL_GET_DRV_VERSION, 0);
14906                 break;
14907         }
14908
14909         default:
14910                 BNX2X_ERR("unknown command %x\n", ctl->cmd);
14911                 rc = -EINVAL;
14912         }
14913
14914         /* For storage-only interfaces, change driver state */
14915         if (IS_MF_SD_STORAGE_PERSONALITY_ONLY(bp)) {
14916                 switch (ctl->drv_state) {
14917                 case DRV_NOP:
14918                         break;
14919                 case DRV_ACTIVE:
14920                         bnx2x_set_os_driver_state(bp,
14921                                                   OS_DRIVER_STATE_ACTIVE);
14922                         break;
14923                 case DRV_INACTIVE:
14924                         bnx2x_set_os_driver_state(bp,
14925                                                   OS_DRIVER_STATE_DISABLED);
14926                         break;
14927                 case DRV_UNLOADED:
14928                         bnx2x_set_os_driver_state(bp,
14929                                                   OS_DRIVER_STATE_NOT_LOADED);
14930                         break;
14931                 default:
14932                 BNX2X_ERR("Unknown cnic driver state: %d\n", ctl->drv_state);
14933                 }
14934         }
14935
14936         return rc;
14937 }
14938
14939 static int bnx2x_get_fc_npiv(struct net_device *dev,
14940                              struct cnic_fc_npiv_tbl *cnic_tbl)
14941 {
14942         struct bnx2x *bp = netdev_priv(dev);
14943         struct bdn_fc_npiv_tbl *tbl = NULL;
14944         u32 offset, entries;
14945         int rc = -EINVAL;
14946         int i;
14947
14948         if (!SHMEM2_HAS(bp, fc_npiv_nvram_tbl_addr[0]))
14949                 goto out;
14950
14951         DP(BNX2X_MSG_MCP, "About to read the FC-NPIV table\n");
14952
14953         tbl = kmalloc(sizeof(*tbl), GFP_KERNEL);
14954         if (!tbl) {
14955                 BNX2X_ERR("Failed to allocate fc_npiv table\n");
14956                 goto out;
14957         }
14958
14959         offset = SHMEM2_RD(bp, fc_npiv_nvram_tbl_addr[BP_PORT(bp)]);
14960         if (!offset) {
14961                 DP(BNX2X_MSG_MCP, "No FC-NPIV in NVRAM\n");
14962                 goto out;
14963         }
14964         DP(BNX2X_MSG_MCP, "Offset of FC-NPIV in NVRAM: %08x\n", offset);
14965
14966         /* Read the table contents from nvram */
14967         if (bnx2x_nvram_read(bp, offset, (u8 *)tbl, sizeof(*tbl))) {
14968                 BNX2X_ERR("Failed to read FC-NPIV table\n");
14969                 goto out;
14970         }
14971
14972         /* Since bnx2x_nvram_read() returns data in be32, we need to convert
14973          * the number of entries back to cpu endianness.
14974          */
14975         entries = tbl->fc_npiv_cfg.num_of_npiv;
14976         entries = (__force u32)be32_to_cpu((__force __be32)entries);
14977         tbl->fc_npiv_cfg.num_of_npiv = entries;
14978
14979         if (!tbl->fc_npiv_cfg.num_of_npiv) {
14980                 DP(BNX2X_MSG_MCP,
14981                    "No FC-NPIV table [valid, simply not present]\n");
14982                 goto out;
14983         } else if (tbl->fc_npiv_cfg.num_of_npiv > MAX_NUMBER_NPIV) {
14984                 BNX2X_ERR("FC-NPIV table with bad length 0x%08x\n",
14985                           tbl->fc_npiv_cfg.num_of_npiv);
14986                 goto out;
14987         } else {
14988                 DP(BNX2X_MSG_MCP, "Read 0x%08x entries from NVRAM\n",
14989                    tbl->fc_npiv_cfg.num_of_npiv);
14990         }
14991
14992         /* Copy the data into cnic-provided struct */
14993         cnic_tbl->count = tbl->fc_npiv_cfg.num_of_npiv;
14994         for (i = 0; i < cnic_tbl->count; i++) {
14995                 memcpy(cnic_tbl->wwpn[i], tbl->settings[i].npiv_wwpn, 8);
14996                 memcpy(cnic_tbl->wwnn[i], tbl->settings[i].npiv_wwnn, 8);
14997         }
14998
14999         rc = 0;
15000 out:
15001         kfree(tbl);
15002         return rc;
15003 }
15004
15005 void bnx2x_setup_cnic_irq_info(struct bnx2x *bp)
15006 {
15007         struct cnic_eth_dev *cp = &bp->cnic_eth_dev;
15008
15009         if (bp->flags & USING_MSIX_FLAG) {
15010                 cp->drv_state |= CNIC_DRV_STATE_USING_MSIX;
15011                 cp->irq_arr[0].irq_flags |= CNIC_IRQ_FL_MSIX;
15012                 cp->irq_arr[0].vector = bp->msix_table[1].vector;
15013         } else {
15014                 cp->drv_state &= ~CNIC_DRV_STATE_USING_MSIX;
15015                 cp->irq_arr[0].irq_flags &= ~CNIC_IRQ_FL_MSIX;
15016         }
15017         if (!CHIP_IS_E1x(bp))
15018                 cp->irq_arr[0].status_blk = (void *)bp->cnic_sb.e2_sb;
15019         else
15020                 cp->irq_arr[0].status_blk = (void *)bp->cnic_sb.e1x_sb;
15021
15022         cp->irq_arr[0].status_blk_num =  bnx2x_cnic_fw_sb_id(bp);
15023         cp->irq_arr[0].status_blk_num2 = bnx2x_cnic_igu_sb_id(bp);
15024         cp->irq_arr[1].status_blk = bp->def_status_blk;
15025         cp->irq_arr[1].status_blk_num = DEF_SB_ID;
15026         cp->irq_arr[1].status_blk_num2 = DEF_SB_IGU_ID;
15027
15028         cp->num_irq = 2;
15029 }
15030
15031 void bnx2x_setup_cnic_info(struct bnx2x *bp)
15032 {
15033         struct cnic_eth_dev *cp = &bp->cnic_eth_dev;
15034
15035         cp->ctx_tbl_offset = FUNC_ILT_BASE(BP_FUNC(bp)) +
15036                              bnx2x_cid_ilt_lines(bp);
15037         cp->starting_cid = bnx2x_cid_ilt_lines(bp) * ILT_PAGE_CIDS;
15038         cp->fcoe_init_cid = BNX2X_FCOE_ETH_CID(bp);
15039         cp->iscsi_l2_cid = BNX2X_ISCSI_ETH_CID(bp);
15040
15041         DP(NETIF_MSG_IFUP, "BNX2X_1st_NON_L2_ETH_CID(bp) %x, cp->starting_cid %x, cp->fcoe_init_cid %x, cp->iscsi_l2_cid %x\n",
15042            BNX2X_1st_NON_L2_ETH_CID(bp), cp->starting_cid, cp->fcoe_init_cid,
15043            cp->iscsi_l2_cid);
15044
15045         if (NO_ISCSI_OOO(bp))
15046                 cp->drv_state |= CNIC_DRV_STATE_NO_ISCSI_OOO;
15047 }
15048
15049 static int bnx2x_register_cnic(struct net_device *dev, struct cnic_ops *ops,
15050                                void *data)
15051 {
15052         struct bnx2x *bp = netdev_priv(dev);
15053         struct cnic_eth_dev *cp = &bp->cnic_eth_dev;
15054         int rc;
15055
15056         DP(NETIF_MSG_IFUP, "Register_cnic called\n");
15057
15058         if (ops == NULL) {
15059                 BNX2X_ERR("NULL ops received\n");
15060                 return -EINVAL;
15061         }
15062
15063         if (!CNIC_SUPPORT(bp)) {
15064                 BNX2X_ERR("Can't register CNIC when not supported\n");
15065                 return -EOPNOTSUPP;
15066         }
15067
15068         if (!CNIC_LOADED(bp)) {
15069                 rc = bnx2x_load_cnic(bp);
15070                 if (rc) {
15071                         BNX2X_ERR("CNIC-related load failed\n");
15072                         return rc;
15073                 }
15074         }
15075
15076         bp->cnic_enabled = true;
15077
15078         bp->cnic_kwq = kzalloc(PAGE_SIZE, GFP_KERNEL);
15079         if (!bp->cnic_kwq)
15080                 return -ENOMEM;
15081
15082         bp->cnic_kwq_cons = bp->cnic_kwq;
15083         bp->cnic_kwq_prod = bp->cnic_kwq;
15084         bp->cnic_kwq_last = bp->cnic_kwq + MAX_SP_DESC_CNT;
15085
15086         bp->cnic_spq_pending = 0;
15087         bp->cnic_kwq_pending = 0;
15088
15089         bp->cnic_data = data;
15090
15091         cp->num_irq = 0;
15092         cp->drv_state |= CNIC_DRV_STATE_REGD;
15093         cp->iro_arr = bp->iro_arr;
15094
15095         bnx2x_setup_cnic_irq_info(bp);
15096
15097         rcu_assign_pointer(bp->cnic_ops, ops);
15098
15099         /* Schedule driver to read CNIC driver versions */
15100         bnx2x_schedule_sp_rtnl(bp, BNX2X_SP_RTNL_GET_DRV_VERSION, 0);
15101
15102         return 0;
15103 }
15104
15105 static int bnx2x_unregister_cnic(struct net_device *dev)
15106 {
15107         struct bnx2x *bp = netdev_priv(dev);
15108         struct cnic_eth_dev *cp = &bp->cnic_eth_dev;
15109
15110         mutex_lock(&bp->cnic_mutex);
15111         cp->drv_state = 0;
15112         RCU_INIT_POINTER(bp->cnic_ops, NULL);
15113         mutex_unlock(&bp->cnic_mutex);
15114         synchronize_rcu();
15115         bp->cnic_enabled = false;
15116         kfree(bp->cnic_kwq);
15117         bp->cnic_kwq = NULL;
15118
15119         return 0;
15120 }
15121
15122 static struct cnic_eth_dev *bnx2x_cnic_probe(struct net_device *dev)
15123 {
15124         struct bnx2x *bp = netdev_priv(dev);
15125         struct cnic_eth_dev *cp = &bp->cnic_eth_dev;
15126
15127         /* If both iSCSI and FCoE are disabled - return NULL in
15128          * order to indicate CNIC that it should not try to work
15129          * with this device.
15130          */
15131         if (NO_ISCSI(bp) && NO_FCOE(bp))
15132                 return NULL;
15133
15134         cp->drv_owner = THIS_MODULE;
15135         cp->chip_id = CHIP_ID(bp);
15136         cp->pdev = bp->pdev;
15137         cp->io_base = bp->regview;
15138         cp->io_base2 = bp->doorbells;
15139         cp->max_kwqe_pending = 8;
15140         cp->ctx_blk_size = CDU_ILT_PAGE_SZ;
15141         cp->ctx_tbl_offset = FUNC_ILT_BASE(BP_FUNC(bp)) +
15142                              bnx2x_cid_ilt_lines(bp);
15143         cp->ctx_tbl_len = CNIC_ILT_LINES;
15144         cp->starting_cid = bnx2x_cid_ilt_lines(bp) * ILT_PAGE_CIDS;
15145         cp->drv_submit_kwqes_16 = bnx2x_cnic_sp_queue;
15146         cp->drv_ctl = bnx2x_drv_ctl;
15147         cp->drv_get_fc_npiv_tbl = bnx2x_get_fc_npiv;
15148         cp->drv_register_cnic = bnx2x_register_cnic;
15149         cp->drv_unregister_cnic = bnx2x_unregister_cnic;
15150         cp->fcoe_init_cid = BNX2X_FCOE_ETH_CID(bp);
15151         cp->iscsi_l2_client_id =
15152                 bnx2x_cnic_eth_cl_id(bp, BNX2X_ISCSI_ETH_CL_ID_IDX);
15153         cp->iscsi_l2_cid = BNX2X_ISCSI_ETH_CID(bp);
15154
15155         if (NO_ISCSI_OOO(bp))
15156                 cp->drv_state |= CNIC_DRV_STATE_NO_ISCSI_OOO;
15157
15158         if (NO_ISCSI(bp))
15159                 cp->drv_state |= CNIC_DRV_STATE_NO_ISCSI;
15160
15161         if (NO_FCOE(bp))
15162                 cp->drv_state |= CNIC_DRV_STATE_NO_FCOE;
15163
15164         BNX2X_DEV_INFO(
15165                 "page_size %d, tbl_offset %d, tbl_lines %d, starting cid %d\n",
15166            cp->ctx_blk_size,
15167            cp->ctx_tbl_offset,
15168            cp->ctx_tbl_len,
15169            cp->starting_cid);
15170         return cp;
15171 }
15172
15173 static u32 bnx2x_rx_ustorm_prods_offset(struct bnx2x_fastpath *fp)
15174 {
15175         struct bnx2x *bp = fp->bp;
15176         u32 offset = BAR_USTRORM_INTMEM;
15177
15178         if (IS_VF(bp))
15179                 return bnx2x_vf_ustorm_prods_offset(bp, fp);
15180         else if (!CHIP_IS_E1x(bp))
15181                 offset += USTORM_RX_PRODS_E2_OFFSET(fp->cl_qzone_id);
15182         else
15183                 offset += USTORM_RX_PRODS_E1X_OFFSET(BP_PORT(bp), fp->cl_id);
15184
15185         return offset;
15186 }
15187
15188 /* called only on E1H or E2.
15189  * When pretending to be PF, the pretend value is the function number 0...7
15190  * When pretending to be VF, the pretend val is the PF-num:VF-valid:ABS-VFID
15191  * combination
15192  */
15193 int bnx2x_pretend_func(struct bnx2x *bp, u16 pretend_func_val)
15194 {
15195         u32 pretend_reg;
15196
15197         if (CHIP_IS_E1H(bp) && pretend_func_val >= E1H_FUNC_MAX)
15198                 return -1;
15199
15200         /* get my own pretend register */
15201         pretend_reg = bnx2x_get_pretend_reg(bp);
15202         REG_WR(bp, pretend_reg, pretend_func_val);
15203         REG_RD(bp, pretend_reg);
15204         return 0;
15205 }
15206
15207 static void bnx2x_ptp_task(struct work_struct *work)
15208 {
15209         struct bnx2x *bp = container_of(work, struct bnx2x, ptp_task);
15210         int port = BP_PORT(bp);
15211         u32 val_seq;
15212         u64 timestamp, ns;
15213         struct skb_shared_hwtstamps shhwtstamps;
15214
15215         /* Read Tx timestamp registers */
15216         val_seq = REG_RD(bp, port ? NIG_REG_P1_TLLH_PTP_BUF_SEQID :
15217                          NIG_REG_P0_TLLH_PTP_BUF_SEQID);
15218         if (val_seq & 0x10000) {
15219                 /* There is a valid timestamp value */
15220                 timestamp = REG_RD(bp, port ? NIG_REG_P1_TLLH_PTP_BUF_TS_MSB :
15221                                    NIG_REG_P0_TLLH_PTP_BUF_TS_MSB);
15222                 timestamp <<= 32;
15223                 timestamp |= REG_RD(bp, port ? NIG_REG_P1_TLLH_PTP_BUF_TS_LSB :
15224                                     NIG_REG_P0_TLLH_PTP_BUF_TS_LSB);
15225                 /* Reset timestamp register to allow new timestamp */
15226                 REG_WR(bp, port ? NIG_REG_P1_TLLH_PTP_BUF_SEQID :
15227                        NIG_REG_P0_TLLH_PTP_BUF_SEQID, 0x10000);
15228                 ns = timecounter_cyc2time(&bp->timecounter, timestamp);
15229
15230                 memset(&shhwtstamps, 0, sizeof(shhwtstamps));
15231                 shhwtstamps.hwtstamp = ns_to_ktime(ns);
15232                 skb_tstamp_tx(bp->ptp_tx_skb, &shhwtstamps);
15233                 dev_kfree_skb_any(bp->ptp_tx_skb);
15234                 bp->ptp_tx_skb = NULL;
15235
15236                 DP(BNX2X_MSG_PTP, "Tx timestamp, timestamp cycles = %llu, ns = %llu\n",
15237                    timestamp, ns);
15238         } else {
15239                 DP(BNX2X_MSG_PTP, "There is no valid Tx timestamp yet\n");
15240                 /* Reschedule to keep checking for a valid timestamp value */
15241                 schedule_work(&bp->ptp_task);
15242         }
15243 }
15244
15245 void bnx2x_set_rx_ts(struct bnx2x *bp, struct sk_buff *skb)
15246 {
15247         int port = BP_PORT(bp);
15248         u64 timestamp, ns;
15249
15250         timestamp = REG_RD(bp, port ? NIG_REG_P1_LLH_PTP_HOST_BUF_TS_MSB :
15251                             NIG_REG_P0_LLH_PTP_HOST_BUF_TS_MSB);
15252         timestamp <<= 32;
15253         timestamp |= REG_RD(bp, port ? NIG_REG_P1_LLH_PTP_HOST_BUF_TS_LSB :
15254                             NIG_REG_P0_LLH_PTP_HOST_BUF_TS_LSB);
15255
15256         /* Reset timestamp register to allow new timestamp */
15257         REG_WR(bp, port ? NIG_REG_P1_LLH_PTP_HOST_BUF_SEQID :
15258                NIG_REG_P0_LLH_PTP_HOST_BUF_SEQID, 0x10000);
15259
15260         ns = timecounter_cyc2time(&bp->timecounter, timestamp);
15261
15262         skb_hwtstamps(skb)->hwtstamp = ns_to_ktime(ns);
15263
15264         DP(BNX2X_MSG_PTP, "Rx timestamp, timestamp cycles = %llu, ns = %llu\n",
15265            timestamp, ns);
15266 }
15267
15268 /* Read the PHC */
15269 static u64 bnx2x_cyclecounter_read(const struct cyclecounter *cc)
15270 {
15271         struct bnx2x *bp = container_of(cc, struct bnx2x, cyclecounter);
15272         int port = BP_PORT(bp);
15273         u32 wb_data[2];
15274         u64 phc_cycles;
15275
15276         REG_RD_DMAE(bp, port ? NIG_REG_TIMESYNC_GEN_REG + tsgen_synctime_t1 :
15277                     NIG_REG_TIMESYNC_GEN_REG + tsgen_synctime_t0, wb_data, 2);
15278         phc_cycles = wb_data[1];
15279         phc_cycles = (phc_cycles << 32) + wb_data[0];
15280
15281         DP(BNX2X_MSG_PTP, "PHC read cycles = %llu\n", phc_cycles);
15282
15283         return phc_cycles;
15284 }
15285
15286 static void bnx2x_init_cyclecounter(struct bnx2x *bp)
15287 {
15288         memset(&bp->cyclecounter, 0, sizeof(bp->cyclecounter));
15289         bp->cyclecounter.read = bnx2x_cyclecounter_read;
15290         bp->cyclecounter.mask = CYCLECOUNTER_MASK(64);
15291         bp->cyclecounter.shift = 0;
15292         bp->cyclecounter.mult = 1;
15293 }
15294
15295 static int bnx2x_send_reset_timesync_ramrod(struct bnx2x *bp)
15296 {
15297         struct bnx2x_func_state_params func_params = {NULL};
15298         struct bnx2x_func_set_timesync_params *set_timesync_params =
15299                 &func_params.params.set_timesync;
15300
15301         /* Prepare parameters for function state transitions */
15302         __set_bit(RAMROD_COMP_WAIT, &func_params.ramrod_flags);
15303         __set_bit(RAMROD_RETRY, &func_params.ramrod_flags);
15304
15305         func_params.f_obj = &bp->func_obj;
15306         func_params.cmd = BNX2X_F_CMD_SET_TIMESYNC;
15307
15308         /* Function parameters */
15309         set_timesync_params->drift_adjust_cmd = TS_DRIFT_ADJUST_RESET;
15310         set_timesync_params->offset_cmd = TS_OFFSET_KEEP;
15311
15312         return bnx2x_func_state_change(bp, &func_params);
15313 }
15314
15315 static int bnx2x_enable_ptp_packets(struct bnx2x *bp)
15316 {
15317         struct bnx2x_queue_state_params q_params;
15318         int rc, i;
15319
15320         /* send queue update ramrod to enable PTP packets */
15321         memset(&q_params, 0, sizeof(q_params));
15322         __set_bit(RAMROD_COMP_WAIT, &q_params.ramrod_flags);
15323         q_params.cmd = BNX2X_Q_CMD_UPDATE;
15324         __set_bit(BNX2X_Q_UPDATE_PTP_PKTS_CHNG,
15325                   &q_params.params.update.update_flags);
15326         __set_bit(BNX2X_Q_UPDATE_PTP_PKTS,
15327                   &q_params.params.update.update_flags);
15328
15329         /* send the ramrod on all the queues of the PF */
15330         for_each_eth_queue(bp, i) {
15331                 struct bnx2x_fastpath *fp = &bp->fp[i];
15332
15333                 /* Set the appropriate Queue object */
15334                 q_params.q_obj = &bnx2x_sp_obj(bp, fp).q_obj;
15335
15336                 /* Update the Queue state */
15337                 rc = bnx2x_queue_state_change(bp, &q_params);
15338                 if (rc) {
15339                         BNX2X_ERR("Failed to enable PTP packets\n");
15340                         return rc;
15341                 }
15342         }
15343
15344         return 0;
15345 }
15346
15347 int bnx2x_configure_ptp_filters(struct bnx2x *bp)
15348 {
15349         int port = BP_PORT(bp);
15350         int rc;
15351
15352         if (!bp->hwtstamp_ioctl_called)
15353                 return 0;
15354
15355         switch (bp->tx_type) {
15356         case HWTSTAMP_TX_ON:
15357                 bp->flags |= TX_TIMESTAMPING_EN;
15358                 REG_WR(bp, port ? NIG_REG_P1_TLLH_PTP_PARAM_MASK :
15359                        NIG_REG_P0_TLLH_PTP_PARAM_MASK, 0x6AA);
15360                 REG_WR(bp, port ? NIG_REG_P1_TLLH_PTP_RULE_MASK :
15361                        NIG_REG_P0_TLLH_PTP_RULE_MASK, 0x3EEE);
15362                 break;
15363         case HWTSTAMP_TX_ONESTEP_SYNC:
15364                 BNX2X_ERR("One-step timestamping is not supported\n");
15365                 return -ERANGE;
15366         }
15367
15368         switch (bp->rx_filter) {
15369         case HWTSTAMP_FILTER_NONE:
15370                 break;
15371         case HWTSTAMP_FILTER_ALL:
15372         case HWTSTAMP_FILTER_SOME:
15373         case HWTSTAMP_FILTER_NTP_ALL:
15374                 bp->rx_filter = HWTSTAMP_FILTER_NONE;
15375                 break;
15376         case HWTSTAMP_FILTER_PTP_V1_L4_EVENT:
15377         case HWTSTAMP_FILTER_PTP_V1_L4_SYNC:
15378         case HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ:
15379                 bp->rx_filter = HWTSTAMP_FILTER_PTP_V1_L4_EVENT;
15380                 /* Initialize PTP detection for UDP/IPv4 events */
15381                 REG_WR(bp, port ? NIG_REG_P1_LLH_PTP_PARAM_MASK :
15382                        NIG_REG_P0_LLH_PTP_PARAM_MASK, 0x7EE);
15383                 REG_WR(bp, port ? NIG_REG_P1_LLH_PTP_RULE_MASK :
15384                        NIG_REG_P0_LLH_PTP_RULE_MASK, 0x3FFE);
15385                 break;
15386         case HWTSTAMP_FILTER_PTP_V2_L4_EVENT:
15387         case HWTSTAMP_FILTER_PTP_V2_L4_SYNC:
15388         case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ:
15389                 bp->rx_filter = HWTSTAMP_FILTER_PTP_V2_L4_EVENT;
15390                 /* Initialize PTP detection for UDP/IPv4 or UDP/IPv6 events */
15391                 REG_WR(bp, port ? NIG_REG_P1_LLH_PTP_PARAM_MASK :
15392                        NIG_REG_P0_LLH_PTP_PARAM_MASK, 0x7EA);
15393                 REG_WR(bp, port ? NIG_REG_P1_LLH_PTP_RULE_MASK :
15394                        NIG_REG_P0_LLH_PTP_RULE_MASK, 0x3FEE);
15395                 break;
15396         case HWTSTAMP_FILTER_PTP_V2_L2_EVENT:
15397         case HWTSTAMP_FILTER_PTP_V2_L2_SYNC:
15398         case HWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ:
15399                 bp->rx_filter = HWTSTAMP_FILTER_PTP_V2_L2_EVENT;
15400                 /* Initialize PTP detection L2 events */
15401                 REG_WR(bp, port ? NIG_REG_P1_LLH_PTP_PARAM_MASK :
15402                        NIG_REG_P0_LLH_PTP_PARAM_MASK, 0x6BF);
15403                 REG_WR(bp, port ? NIG_REG_P1_LLH_PTP_RULE_MASK :
15404                        NIG_REG_P0_LLH_PTP_RULE_MASK, 0x3EFF);
15405
15406                 break;
15407         case HWTSTAMP_FILTER_PTP_V2_EVENT:
15408         case HWTSTAMP_FILTER_PTP_V2_SYNC:
15409         case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ:
15410                 bp->rx_filter = HWTSTAMP_FILTER_PTP_V2_EVENT;
15411                 /* Initialize PTP detection L2, UDP/IPv4 or UDP/IPv6 events */
15412                 REG_WR(bp, port ? NIG_REG_P1_LLH_PTP_PARAM_MASK :
15413                        NIG_REG_P0_LLH_PTP_PARAM_MASK, 0x6AA);
15414                 REG_WR(bp, port ? NIG_REG_P1_LLH_PTP_RULE_MASK :
15415                        NIG_REG_P0_LLH_PTP_RULE_MASK, 0x3EEE);
15416                 break;
15417         }
15418
15419         /* Indicate to FW that this PF expects recorded PTP packets */
15420         rc = bnx2x_enable_ptp_packets(bp);
15421         if (rc)
15422                 return rc;
15423
15424         /* Enable sending PTP packets to host */
15425         REG_WR(bp, port ? NIG_REG_P1_LLH_PTP_TO_HOST :
15426                NIG_REG_P0_LLH_PTP_TO_HOST, 0x1);
15427
15428         return 0;
15429 }
15430
15431 static int bnx2x_hwtstamp_ioctl(struct bnx2x *bp, struct ifreq *ifr)
15432 {
15433         struct hwtstamp_config config;
15434         int rc;
15435
15436         DP(BNX2X_MSG_PTP, "HWTSTAMP IOCTL called\n");
15437
15438         if (copy_from_user(&config, ifr->ifr_data, sizeof(config)))
15439                 return -EFAULT;
15440
15441         DP(BNX2X_MSG_PTP, "Requested tx_type: %d, requested rx_filters = %d\n",
15442            config.tx_type, config.rx_filter);
15443
15444         if (config.flags) {
15445                 BNX2X_ERR("config.flags is reserved for future use\n");
15446                 return -EINVAL;
15447         }
15448
15449         bp->hwtstamp_ioctl_called = 1;
15450         bp->tx_type = config.tx_type;
15451         bp->rx_filter = config.rx_filter;
15452
15453         rc = bnx2x_configure_ptp_filters(bp);
15454         if (rc)
15455                 return rc;
15456
15457         config.rx_filter = bp->rx_filter;
15458
15459         return copy_to_user(ifr->ifr_data, &config, sizeof(config)) ?
15460                 -EFAULT : 0;
15461 }
15462
15463 /* Configures HW for PTP */
15464 static int bnx2x_configure_ptp(struct bnx2x *bp)
15465 {
15466         int rc, port = BP_PORT(bp);
15467         u32 wb_data[2];
15468
15469         /* Reset PTP event detection rules - will be configured in the IOCTL */
15470         REG_WR(bp, port ? NIG_REG_P1_LLH_PTP_PARAM_MASK :
15471                NIG_REG_P0_LLH_PTP_PARAM_MASK, 0x7FF);
15472         REG_WR(bp, port ? NIG_REG_P1_LLH_PTP_RULE_MASK :
15473                NIG_REG_P0_LLH_PTP_RULE_MASK, 0x3FFF);
15474         REG_WR(bp, port ? NIG_REG_P1_TLLH_PTP_PARAM_MASK :
15475                NIG_REG_P0_TLLH_PTP_PARAM_MASK, 0x7FF);
15476         REG_WR(bp, port ? NIG_REG_P1_TLLH_PTP_RULE_MASK :
15477                NIG_REG_P0_TLLH_PTP_RULE_MASK, 0x3FFF);
15478
15479         /* Disable PTP packets to host - will be configured in the IOCTL*/
15480         REG_WR(bp, port ? NIG_REG_P1_LLH_PTP_TO_HOST :
15481                NIG_REG_P0_LLH_PTP_TO_HOST, 0x0);
15482
15483         /* Enable the PTP feature */
15484         REG_WR(bp, port ? NIG_REG_P1_PTP_EN :
15485                NIG_REG_P0_PTP_EN, 0x3F);
15486
15487         /* Enable the free-running counter */
15488         wb_data[0] = 0;
15489         wb_data[1] = 0;
15490         REG_WR_DMAE(bp, NIG_REG_TIMESYNC_GEN_REG + tsgen_ctrl, wb_data, 2);
15491
15492         /* Reset drift register (offset register is not reset) */
15493         rc = bnx2x_send_reset_timesync_ramrod(bp);
15494         if (rc) {
15495                 BNX2X_ERR("Failed to reset PHC drift register\n");
15496                 return -EFAULT;
15497         }
15498
15499         /* Reset possibly old timestamps */
15500         REG_WR(bp, port ? NIG_REG_P1_LLH_PTP_HOST_BUF_SEQID :
15501                NIG_REG_P0_LLH_PTP_HOST_BUF_SEQID, 0x10000);
15502         REG_WR(bp, port ? NIG_REG_P1_TLLH_PTP_BUF_SEQID :
15503                NIG_REG_P0_TLLH_PTP_BUF_SEQID, 0x10000);
15504
15505         return 0;
15506 }
15507
15508 /* Called during load, to initialize PTP-related stuff */
15509 void bnx2x_init_ptp(struct bnx2x *bp)
15510 {
15511         int rc;
15512
15513         /* Configure PTP in HW */
15514         rc = bnx2x_configure_ptp(bp);
15515         if (rc) {
15516                 BNX2X_ERR("Stopping PTP initialization\n");
15517                 return;
15518         }
15519
15520         /* Init work queue for Tx timestamping */
15521         INIT_WORK(&bp->ptp_task, bnx2x_ptp_task);
15522
15523         /* Init cyclecounter and timecounter. This is done only in the first
15524          * load. If done in every load, PTP application will fail when doing
15525          * unload / load (e.g. MTU change) while it is running.
15526          */
15527         if (!bp->timecounter_init_done) {
15528                 bnx2x_init_cyclecounter(bp);
15529                 timecounter_init(&bp->timecounter, &bp->cyclecounter,
15530                                  ktime_to_ns(ktime_get_real()));
15531                 bp->timecounter_init_done = 1;
15532         }
15533
15534         DP(BNX2X_MSG_PTP, "PTP initialization ended successfully\n");
15535 }