1 /* bnx2x_main.c: Broadcom Everest network driver.
3 * Copyright (c) 2007-2013 Broadcom Corporation
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation.
9 * Maintained by: Eilon Greenstein <eilong@broadcom.com>
10 * Written by: Eliezer Tamir
11 * Based on code from Michael Chan's bnx2 driver
12 * UDP CSUM errata workaround by Arik Gendelman
13 * Slowpath and fastpath rework by Vladislav Zolotarov
14 * Statistics and Link management by Yitchak Gertner
18 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
20 #include <linux/module.h>
21 #include <linux/moduleparam.h>
22 #include <linux/kernel.h>
23 #include <linux/device.h> /* for dev_info() */
24 #include <linux/timer.h>
25 #include <linux/errno.h>
26 #include <linux/ioport.h>
27 #include <linux/slab.h>
28 #include <linux/interrupt.h>
29 #include <linux/pci.h>
30 #include <linux/init.h>
31 #include <linux/netdevice.h>
32 #include <linux/etherdevice.h>
33 #include <linux/skbuff.h>
34 #include <linux/dma-mapping.h>
35 #include <linux/bitops.h>
36 #include <linux/irq.h>
37 #include <linux/delay.h>
38 #include <asm/byteorder.h>
39 #include <linux/time.h>
40 #include <linux/ethtool.h>
41 #include <linux/mii.h>
42 #include <linux/if_vlan.h>
46 #include <net/checksum.h>
47 #include <net/ip6_checksum.h>
48 #include <linux/workqueue.h>
49 #include <linux/crc32.h>
50 #include <linux/crc32c.h>
51 #include <linux/prefetch.h>
52 #include <linux/zlib.h>
54 #include <linux/semaphore.h>
55 #include <linux/stringify.h>
56 #include <linux/vmalloc.h>
59 #include "bnx2x_init.h"
60 #include "bnx2x_init_ops.h"
61 #include "bnx2x_cmn.h"
62 #include "bnx2x_vfpf.h"
63 #include "bnx2x_dcb.h"
66 #include <linux/firmware.h>
67 #include "bnx2x_fw_file_hdr.h"
69 #define FW_FILE_VERSION \
70 __stringify(BCM_5710_FW_MAJOR_VERSION) "." \
71 __stringify(BCM_5710_FW_MINOR_VERSION) "." \
72 __stringify(BCM_5710_FW_REVISION_VERSION) "." \
73 __stringify(BCM_5710_FW_ENGINEERING_VERSION)
74 #define FW_FILE_NAME_E1 "bnx2x/bnx2x-e1-" FW_FILE_VERSION ".fw"
75 #define FW_FILE_NAME_E1H "bnx2x/bnx2x-e1h-" FW_FILE_VERSION ".fw"
76 #define FW_FILE_NAME_E2 "bnx2x/bnx2x-e2-" FW_FILE_VERSION ".fw"
78 /* Time in jiffies before concluding the transmitter is hung */
79 #define TX_TIMEOUT (5*HZ)
81 static char version[] =
82 "Broadcom NetXtreme II 5771x/578xx 10/20-Gigabit Ethernet Driver "
83 DRV_MODULE_NAME " " DRV_MODULE_VERSION " (" DRV_MODULE_RELDATE ")\n";
85 MODULE_AUTHOR("Eliezer Tamir");
86 MODULE_DESCRIPTION("Broadcom NetXtreme II "
87 "BCM57710/57711/57711E/"
88 "57712/57712_MF/57800/57800_MF/57810/57810_MF/"
89 "57840/57840_MF Driver");
90 MODULE_LICENSE("GPL");
91 MODULE_VERSION(DRV_MODULE_VERSION);
92 MODULE_FIRMWARE(FW_FILE_NAME_E1);
93 MODULE_FIRMWARE(FW_FILE_NAME_E1H);
94 MODULE_FIRMWARE(FW_FILE_NAME_E2);
97 module_param(num_queues, int, 0);
98 MODULE_PARM_DESC(num_queues,
99 " Set number of queues (default is as a number of CPUs)");
101 static int disable_tpa;
102 module_param(disable_tpa, int, 0);
103 MODULE_PARM_DESC(disable_tpa, " Disable the TPA (LRO) feature");
106 module_param(int_mode, int, 0);
107 MODULE_PARM_DESC(int_mode, " Force interrupt mode other than MSI-X "
110 static int dropless_fc;
111 module_param(dropless_fc, int, 0);
112 MODULE_PARM_DESC(dropless_fc, " Pause on exhausted host ring");
114 static int mrrs = -1;
115 module_param(mrrs, int, 0);
116 MODULE_PARM_DESC(mrrs, " Force Max Read Req Size (0..3) (for debug)");
119 module_param(debug, int, 0);
120 MODULE_PARM_DESC(debug, " Default debug msglevel");
122 struct workqueue_struct *bnx2x_wq;
124 struct bnx2x_mac_vals {
135 enum bnx2x_board_type {
159 /* indexed by board_type, above */
163 [BCM57710] = { "Broadcom NetXtreme II BCM57710 10 Gigabit PCIe [Everest]" },
164 [BCM57711] = { "Broadcom NetXtreme II BCM57711 10 Gigabit PCIe" },
165 [BCM57711E] = { "Broadcom NetXtreme II BCM57711E 10 Gigabit PCIe" },
166 [BCM57712] = { "Broadcom NetXtreme II BCM57712 10 Gigabit Ethernet" },
167 [BCM57712_MF] = { "Broadcom NetXtreme II BCM57712 10 Gigabit Ethernet Multi Function" },
168 [BCM57712_VF] = { "Broadcom NetXtreme II BCM57712 10 Gigabit Ethernet Virtual Function" },
169 [BCM57800] = { "Broadcom NetXtreme II BCM57800 10 Gigabit Ethernet" },
170 [BCM57800_MF] = { "Broadcom NetXtreme II BCM57800 10 Gigabit Ethernet Multi Function" },
171 [BCM57800_VF] = { "Broadcom NetXtreme II BCM57800 10 Gigabit Ethernet Virtual Function" },
172 [BCM57810] = { "Broadcom NetXtreme II BCM57810 10 Gigabit Ethernet" },
173 [BCM57810_MF] = { "Broadcom NetXtreme II BCM57810 10 Gigabit Ethernet Multi Function" },
174 [BCM57810_VF] = { "Broadcom NetXtreme II BCM57810 10 Gigabit Ethernet Virtual Function" },
175 [BCM57840_4_10] = { "Broadcom NetXtreme II BCM57840 10 Gigabit Ethernet" },
176 [BCM57840_2_20] = { "Broadcom NetXtreme II BCM57840 20 Gigabit Ethernet" },
177 [BCM57840_MF] = { "Broadcom NetXtreme II BCM57840 10/20 Gigabit Ethernet Multi Function" },
178 [BCM57840_VF] = { "Broadcom NetXtreme II BCM57840 10/20 Gigabit Ethernet Virtual Function" },
179 [BCM57811] = { "Broadcom NetXtreme II BCM57811 10 Gigabit Ethernet" },
180 [BCM57811_MF] = { "Broadcom NetXtreme II BCM57811 10 Gigabit Ethernet Multi Function" },
181 [BCM57840_O] = { "Broadcom NetXtreme II BCM57840 10/20 Gigabit Ethernet" },
182 [BCM57840_MFO] = { "Broadcom NetXtreme II BCM57840 10/20 Gigabit Ethernet Multi Function" },
183 [BCM57811_VF] = { "Broadcom NetXtreme II BCM57840 10/20 Gigabit Ethernet Virtual Function" }
186 #ifndef PCI_DEVICE_ID_NX2_57710
187 #define PCI_DEVICE_ID_NX2_57710 CHIP_NUM_57710
189 #ifndef PCI_DEVICE_ID_NX2_57711
190 #define PCI_DEVICE_ID_NX2_57711 CHIP_NUM_57711
192 #ifndef PCI_DEVICE_ID_NX2_57711E
193 #define PCI_DEVICE_ID_NX2_57711E CHIP_NUM_57711E
195 #ifndef PCI_DEVICE_ID_NX2_57712
196 #define PCI_DEVICE_ID_NX2_57712 CHIP_NUM_57712
198 #ifndef PCI_DEVICE_ID_NX2_57712_MF
199 #define PCI_DEVICE_ID_NX2_57712_MF CHIP_NUM_57712_MF
201 #ifndef PCI_DEVICE_ID_NX2_57712_VF
202 #define PCI_DEVICE_ID_NX2_57712_VF CHIP_NUM_57712_VF
204 #ifndef PCI_DEVICE_ID_NX2_57800
205 #define PCI_DEVICE_ID_NX2_57800 CHIP_NUM_57800
207 #ifndef PCI_DEVICE_ID_NX2_57800_MF
208 #define PCI_DEVICE_ID_NX2_57800_MF CHIP_NUM_57800_MF
210 #ifndef PCI_DEVICE_ID_NX2_57800_VF
211 #define PCI_DEVICE_ID_NX2_57800_VF CHIP_NUM_57800_VF
213 #ifndef PCI_DEVICE_ID_NX2_57810
214 #define PCI_DEVICE_ID_NX2_57810 CHIP_NUM_57810
216 #ifndef PCI_DEVICE_ID_NX2_57810_MF
217 #define PCI_DEVICE_ID_NX2_57810_MF CHIP_NUM_57810_MF
219 #ifndef PCI_DEVICE_ID_NX2_57840_O
220 #define PCI_DEVICE_ID_NX2_57840_O CHIP_NUM_57840_OBSOLETE
222 #ifndef PCI_DEVICE_ID_NX2_57810_VF
223 #define PCI_DEVICE_ID_NX2_57810_VF CHIP_NUM_57810_VF
225 #ifndef PCI_DEVICE_ID_NX2_57840_4_10
226 #define PCI_DEVICE_ID_NX2_57840_4_10 CHIP_NUM_57840_4_10
228 #ifndef PCI_DEVICE_ID_NX2_57840_2_20
229 #define PCI_DEVICE_ID_NX2_57840_2_20 CHIP_NUM_57840_2_20
231 #ifndef PCI_DEVICE_ID_NX2_57840_MFO
232 #define PCI_DEVICE_ID_NX2_57840_MFO CHIP_NUM_57840_MF_OBSOLETE
234 #ifndef PCI_DEVICE_ID_NX2_57840_MF
235 #define PCI_DEVICE_ID_NX2_57840_MF CHIP_NUM_57840_MF
237 #ifndef PCI_DEVICE_ID_NX2_57840_VF
238 #define PCI_DEVICE_ID_NX2_57840_VF CHIP_NUM_57840_VF
240 #ifndef PCI_DEVICE_ID_NX2_57811
241 #define PCI_DEVICE_ID_NX2_57811 CHIP_NUM_57811
243 #ifndef PCI_DEVICE_ID_NX2_57811_MF
244 #define PCI_DEVICE_ID_NX2_57811_MF CHIP_NUM_57811_MF
246 #ifndef PCI_DEVICE_ID_NX2_57811_VF
247 #define PCI_DEVICE_ID_NX2_57811_VF CHIP_NUM_57811_VF
250 static DEFINE_PCI_DEVICE_TABLE(bnx2x_pci_tbl) = {
251 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57710), BCM57710 },
252 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57711), BCM57711 },
253 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57711E), BCM57711E },
254 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57712), BCM57712 },
255 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57712_MF), BCM57712_MF },
256 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57712_VF), BCM57712_VF },
257 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57800), BCM57800 },
258 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57800_MF), BCM57800_MF },
259 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57800_VF), BCM57800_VF },
260 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57810), BCM57810 },
261 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57810_MF), BCM57810_MF },
262 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57840_O), BCM57840_O },
263 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57840_4_10), BCM57840_4_10 },
264 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57840_2_20), BCM57840_2_20 },
265 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57810_VF), BCM57810_VF },
266 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57840_MFO), BCM57840_MFO },
267 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57840_MF), BCM57840_MF },
268 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57840_VF), BCM57840_VF },
269 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57811), BCM57811 },
270 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57811_MF), BCM57811_MF },
271 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57811_VF), BCM57811_VF },
275 MODULE_DEVICE_TABLE(pci, bnx2x_pci_tbl);
277 /* Global resources for unloading a previously loaded device */
278 #define BNX2X_PREV_WAIT_NEEDED 1
279 static DEFINE_SEMAPHORE(bnx2x_prev_sem);
280 static LIST_HEAD(bnx2x_prev_list);
281 /****************************************************************************
282 * General service functions
283 ****************************************************************************/
285 static void __storm_memset_dma_mapping(struct bnx2x *bp,
286 u32 addr, dma_addr_t mapping)
288 REG_WR(bp, addr, U64_LO(mapping));
289 REG_WR(bp, addr + 4, U64_HI(mapping));
292 static void storm_memset_spq_addr(struct bnx2x *bp,
293 dma_addr_t mapping, u16 abs_fid)
295 u32 addr = XSEM_REG_FAST_MEMORY +
296 XSTORM_SPQ_PAGE_BASE_OFFSET(abs_fid);
298 __storm_memset_dma_mapping(bp, addr, mapping);
301 static void storm_memset_vf_to_pf(struct bnx2x *bp, u16 abs_fid,
304 REG_WR8(bp, BAR_XSTRORM_INTMEM + XSTORM_VF_TO_PF_OFFSET(abs_fid),
306 REG_WR8(bp, BAR_CSTRORM_INTMEM + CSTORM_VF_TO_PF_OFFSET(abs_fid),
308 REG_WR8(bp, BAR_TSTRORM_INTMEM + TSTORM_VF_TO_PF_OFFSET(abs_fid),
310 REG_WR8(bp, BAR_USTRORM_INTMEM + USTORM_VF_TO_PF_OFFSET(abs_fid),
314 static void storm_memset_func_en(struct bnx2x *bp, u16 abs_fid,
317 REG_WR8(bp, BAR_XSTRORM_INTMEM + XSTORM_FUNC_EN_OFFSET(abs_fid),
319 REG_WR8(bp, BAR_CSTRORM_INTMEM + CSTORM_FUNC_EN_OFFSET(abs_fid),
321 REG_WR8(bp, BAR_TSTRORM_INTMEM + TSTORM_FUNC_EN_OFFSET(abs_fid),
323 REG_WR8(bp, BAR_USTRORM_INTMEM + USTORM_FUNC_EN_OFFSET(abs_fid),
327 static void storm_memset_eq_data(struct bnx2x *bp,
328 struct event_ring_data *eq_data,
331 size_t size = sizeof(struct event_ring_data);
333 u32 addr = BAR_CSTRORM_INTMEM + CSTORM_EVENT_RING_DATA_OFFSET(pfid);
335 __storm_memset_struct(bp, addr, size, (u32 *)eq_data);
338 static void storm_memset_eq_prod(struct bnx2x *bp, u16 eq_prod,
341 u32 addr = BAR_CSTRORM_INTMEM + CSTORM_EVENT_RING_PROD_OFFSET(pfid);
342 REG_WR16(bp, addr, eq_prod);
346 * locking is done by mcp
348 static void bnx2x_reg_wr_ind(struct bnx2x *bp, u32 addr, u32 val)
350 pci_write_config_dword(bp->pdev, PCICFG_GRC_ADDRESS, addr);
351 pci_write_config_dword(bp->pdev, PCICFG_GRC_DATA, val);
352 pci_write_config_dword(bp->pdev, PCICFG_GRC_ADDRESS,
353 PCICFG_VENDOR_ID_OFFSET);
356 static u32 bnx2x_reg_rd_ind(struct bnx2x *bp, u32 addr)
360 pci_write_config_dword(bp->pdev, PCICFG_GRC_ADDRESS, addr);
361 pci_read_config_dword(bp->pdev, PCICFG_GRC_DATA, &val);
362 pci_write_config_dword(bp->pdev, PCICFG_GRC_ADDRESS,
363 PCICFG_VENDOR_ID_OFFSET);
368 #define DMAE_DP_SRC_GRC "grc src_addr [%08x]"
369 #define DMAE_DP_SRC_PCI "pci src_addr [%x:%08x]"
370 #define DMAE_DP_DST_GRC "grc dst_addr [%08x]"
371 #define DMAE_DP_DST_PCI "pci dst_addr [%x:%08x]"
372 #define DMAE_DP_DST_NONE "dst_addr [none]"
374 static void bnx2x_dp_dmae(struct bnx2x *bp,
375 struct dmae_command *dmae, int msglvl)
377 u32 src_type = dmae->opcode & DMAE_COMMAND_SRC;
380 switch (dmae->opcode & DMAE_COMMAND_DST) {
381 case DMAE_CMD_DST_PCI:
382 if (src_type == DMAE_CMD_SRC_PCI)
383 DP(msglvl, "DMAE: opcode 0x%08x\n"
384 "src [%x:%08x], len [%d*4], dst [%x:%08x]\n"
385 "comp_addr [%x:%08x], comp_val 0x%08x\n",
386 dmae->opcode, dmae->src_addr_hi, dmae->src_addr_lo,
387 dmae->len, dmae->dst_addr_hi, dmae->dst_addr_lo,
388 dmae->comp_addr_hi, dmae->comp_addr_lo,
391 DP(msglvl, "DMAE: opcode 0x%08x\n"
392 "src [%08x], len [%d*4], dst [%x:%08x]\n"
393 "comp_addr [%x:%08x], comp_val 0x%08x\n",
394 dmae->opcode, dmae->src_addr_lo >> 2,
395 dmae->len, dmae->dst_addr_hi, dmae->dst_addr_lo,
396 dmae->comp_addr_hi, dmae->comp_addr_lo,
399 case DMAE_CMD_DST_GRC:
400 if (src_type == DMAE_CMD_SRC_PCI)
401 DP(msglvl, "DMAE: opcode 0x%08x\n"
402 "src [%x:%08x], len [%d*4], dst_addr [%08x]\n"
403 "comp_addr [%x:%08x], comp_val 0x%08x\n",
404 dmae->opcode, dmae->src_addr_hi, dmae->src_addr_lo,
405 dmae->len, dmae->dst_addr_lo >> 2,
406 dmae->comp_addr_hi, dmae->comp_addr_lo,
409 DP(msglvl, "DMAE: opcode 0x%08x\n"
410 "src [%08x], len [%d*4], dst [%08x]\n"
411 "comp_addr [%x:%08x], comp_val 0x%08x\n",
412 dmae->opcode, dmae->src_addr_lo >> 2,
413 dmae->len, dmae->dst_addr_lo >> 2,
414 dmae->comp_addr_hi, dmae->comp_addr_lo,
418 if (src_type == DMAE_CMD_SRC_PCI)
419 DP(msglvl, "DMAE: opcode 0x%08x\n"
420 "src_addr [%x:%08x] len [%d * 4] dst_addr [none]\n"
421 "comp_addr [%x:%08x] comp_val 0x%08x\n",
422 dmae->opcode, dmae->src_addr_hi, dmae->src_addr_lo,
423 dmae->len, dmae->comp_addr_hi, dmae->comp_addr_lo,
426 DP(msglvl, "DMAE: opcode 0x%08x\n"
427 "src_addr [%08x] len [%d * 4] dst_addr [none]\n"
428 "comp_addr [%x:%08x] comp_val 0x%08x\n",
429 dmae->opcode, dmae->src_addr_lo >> 2,
430 dmae->len, dmae->comp_addr_hi, dmae->comp_addr_lo,
435 for (i = 0; i < (sizeof(struct dmae_command)/4); i++)
436 DP(msglvl, "DMAE RAW [%02d]: 0x%08x\n",
437 i, *(((u32 *)dmae) + i));
440 /* copy command into DMAE command memory and set DMAE command go */
441 void bnx2x_post_dmae(struct bnx2x *bp, struct dmae_command *dmae, int idx)
446 cmd_offset = (DMAE_REG_CMD_MEM + sizeof(struct dmae_command) * idx);
447 for (i = 0; i < (sizeof(struct dmae_command)/4); i++) {
448 REG_WR(bp, cmd_offset + i*4, *(((u32 *)dmae) + i));
450 REG_WR(bp, dmae_reg_go_c[idx], 1);
453 u32 bnx2x_dmae_opcode_add_comp(u32 opcode, u8 comp_type)
455 return opcode | ((comp_type << DMAE_COMMAND_C_DST_SHIFT) |
459 u32 bnx2x_dmae_opcode_clr_src_reset(u32 opcode)
461 return opcode & ~DMAE_CMD_SRC_RESET;
464 u32 bnx2x_dmae_opcode(struct bnx2x *bp, u8 src_type, u8 dst_type,
465 bool with_comp, u8 comp_type)
469 opcode |= ((src_type << DMAE_COMMAND_SRC_SHIFT) |
470 (dst_type << DMAE_COMMAND_DST_SHIFT));
472 opcode |= (DMAE_CMD_SRC_RESET | DMAE_CMD_DST_RESET);
474 opcode |= (BP_PORT(bp) ? DMAE_CMD_PORT_1 : DMAE_CMD_PORT_0);
475 opcode |= ((BP_VN(bp) << DMAE_CMD_E1HVN_SHIFT) |
476 (BP_VN(bp) << DMAE_COMMAND_DST_VN_SHIFT));
477 opcode |= (DMAE_COM_SET_ERR << DMAE_COMMAND_ERR_POLICY_SHIFT);
480 opcode |= DMAE_CMD_ENDIANITY_B_DW_SWAP;
482 opcode |= DMAE_CMD_ENDIANITY_DW_SWAP;
485 opcode = bnx2x_dmae_opcode_add_comp(opcode, comp_type);
489 void bnx2x_prep_dmae_with_comp(struct bnx2x *bp,
490 struct dmae_command *dmae,
491 u8 src_type, u8 dst_type)
493 memset(dmae, 0, sizeof(struct dmae_command));
496 dmae->opcode = bnx2x_dmae_opcode(bp, src_type, dst_type,
497 true, DMAE_COMP_PCI);
499 /* fill in the completion parameters */
500 dmae->comp_addr_lo = U64_LO(bnx2x_sp_mapping(bp, wb_comp));
501 dmae->comp_addr_hi = U64_HI(bnx2x_sp_mapping(bp, wb_comp));
502 dmae->comp_val = DMAE_COMP_VAL;
505 /* issue a dmae command over the init-channel and wait for completion */
506 int bnx2x_issue_dmae_with_comp(struct bnx2x *bp, struct dmae_command *dmae,
509 int cnt = CHIP_REV_IS_SLOW(bp) ? (400000) : 4000;
512 bnx2x_dp_dmae(bp, dmae, BNX2X_MSG_DMAE);
514 /* Lock the dmae channel. Disable BHs to prevent a dead-lock
515 * as long as this code is called both from syscall context and
516 * from ndo_set_rx_mode() flow that may be called from BH.
518 spin_lock_bh(&bp->dmae_lock);
520 /* reset completion */
523 /* post the command on the channel used for initializations */
524 bnx2x_post_dmae(bp, dmae, INIT_DMAE_C(bp));
526 /* wait for completion */
528 while ((*comp & ~DMAE_PCI_ERR_FLAG) != DMAE_COMP_VAL) {
531 (bp->recovery_state != BNX2X_RECOVERY_DONE &&
532 bp->recovery_state != BNX2X_RECOVERY_NIC_LOADING)) {
533 BNX2X_ERR("DMAE timeout!\n");
540 if (*comp & DMAE_PCI_ERR_FLAG) {
541 BNX2X_ERR("DMAE PCI error!\n");
546 spin_unlock_bh(&bp->dmae_lock);
550 void bnx2x_write_dmae(struct bnx2x *bp, dma_addr_t dma_addr, u32 dst_addr,
554 struct dmae_command dmae;
556 if (!bp->dmae_ready) {
557 u32 *data = bnx2x_sp(bp, wb_data[0]);
560 bnx2x_init_ind_wr(bp, dst_addr, data, len32);
562 bnx2x_init_str_wr(bp, dst_addr, data, len32);
566 /* set opcode and fixed command fields */
567 bnx2x_prep_dmae_with_comp(bp, &dmae, DMAE_SRC_PCI, DMAE_DST_GRC);
569 /* fill in addresses and len */
570 dmae.src_addr_lo = U64_LO(dma_addr);
571 dmae.src_addr_hi = U64_HI(dma_addr);
572 dmae.dst_addr_lo = dst_addr >> 2;
573 dmae.dst_addr_hi = 0;
576 /* issue the command and wait for completion */
577 rc = bnx2x_issue_dmae_with_comp(bp, &dmae, bnx2x_sp(bp, wb_comp));
579 BNX2X_ERR("DMAE returned failure %d\n", rc);
580 #ifdef BNX2X_STOP_ON_ERROR
586 void bnx2x_read_dmae(struct bnx2x *bp, u32 src_addr, u32 len32)
589 struct dmae_command dmae;
591 if (!bp->dmae_ready) {
592 u32 *data = bnx2x_sp(bp, wb_data[0]);
596 for (i = 0; i < len32; i++)
597 data[i] = bnx2x_reg_rd_ind(bp, src_addr + i*4);
599 for (i = 0; i < len32; i++)
600 data[i] = REG_RD(bp, src_addr + i*4);
605 /* set opcode and fixed command fields */
606 bnx2x_prep_dmae_with_comp(bp, &dmae, DMAE_SRC_GRC, DMAE_DST_PCI);
608 /* fill in addresses and len */
609 dmae.src_addr_lo = src_addr >> 2;
610 dmae.src_addr_hi = 0;
611 dmae.dst_addr_lo = U64_LO(bnx2x_sp_mapping(bp, wb_data));
612 dmae.dst_addr_hi = U64_HI(bnx2x_sp_mapping(bp, wb_data));
615 /* issue the command and wait for completion */
616 rc = bnx2x_issue_dmae_with_comp(bp, &dmae, bnx2x_sp(bp, wb_comp));
618 BNX2X_ERR("DMAE returned failure %d\n", rc);
619 #ifdef BNX2X_STOP_ON_ERROR
625 static void bnx2x_write_dmae_phys_len(struct bnx2x *bp, dma_addr_t phys_addr,
628 int dmae_wr_max = DMAE_LEN32_WR_MAX(bp);
631 while (len > dmae_wr_max) {
632 bnx2x_write_dmae(bp, phys_addr + offset,
633 addr + offset, dmae_wr_max);
634 offset += dmae_wr_max * 4;
638 bnx2x_write_dmae(bp, phys_addr + offset, addr + offset, len);
641 static int bnx2x_mc_assert(struct bnx2x *bp)
645 u32 row0, row1, row2, row3;
648 last_idx = REG_RD8(bp, BAR_XSTRORM_INTMEM +
649 XSTORM_ASSERT_LIST_INDEX_OFFSET);
651 BNX2X_ERR("XSTORM_ASSERT_LIST_INDEX 0x%x\n", last_idx);
653 /* print the asserts */
654 for (i = 0; i < STROM_ASSERT_ARRAY_SIZE; i++) {
656 row0 = REG_RD(bp, BAR_XSTRORM_INTMEM +
657 XSTORM_ASSERT_LIST_OFFSET(i));
658 row1 = REG_RD(bp, BAR_XSTRORM_INTMEM +
659 XSTORM_ASSERT_LIST_OFFSET(i) + 4);
660 row2 = REG_RD(bp, BAR_XSTRORM_INTMEM +
661 XSTORM_ASSERT_LIST_OFFSET(i) + 8);
662 row3 = REG_RD(bp, BAR_XSTRORM_INTMEM +
663 XSTORM_ASSERT_LIST_OFFSET(i) + 12);
665 if (row0 != COMMON_ASM_INVALID_ASSERT_OPCODE) {
666 BNX2X_ERR("XSTORM_ASSERT_INDEX 0x%x = 0x%08x 0x%08x 0x%08x 0x%08x\n",
667 i, row3, row2, row1, row0);
675 last_idx = REG_RD8(bp, BAR_TSTRORM_INTMEM +
676 TSTORM_ASSERT_LIST_INDEX_OFFSET);
678 BNX2X_ERR("TSTORM_ASSERT_LIST_INDEX 0x%x\n", last_idx);
680 /* print the asserts */
681 for (i = 0; i < STROM_ASSERT_ARRAY_SIZE; i++) {
683 row0 = REG_RD(bp, BAR_TSTRORM_INTMEM +
684 TSTORM_ASSERT_LIST_OFFSET(i));
685 row1 = REG_RD(bp, BAR_TSTRORM_INTMEM +
686 TSTORM_ASSERT_LIST_OFFSET(i) + 4);
687 row2 = REG_RD(bp, BAR_TSTRORM_INTMEM +
688 TSTORM_ASSERT_LIST_OFFSET(i) + 8);
689 row3 = REG_RD(bp, BAR_TSTRORM_INTMEM +
690 TSTORM_ASSERT_LIST_OFFSET(i) + 12);
692 if (row0 != COMMON_ASM_INVALID_ASSERT_OPCODE) {
693 BNX2X_ERR("TSTORM_ASSERT_INDEX 0x%x = 0x%08x 0x%08x 0x%08x 0x%08x\n",
694 i, row3, row2, row1, row0);
702 last_idx = REG_RD8(bp, BAR_CSTRORM_INTMEM +
703 CSTORM_ASSERT_LIST_INDEX_OFFSET);
705 BNX2X_ERR("CSTORM_ASSERT_LIST_INDEX 0x%x\n", last_idx);
707 /* print the asserts */
708 for (i = 0; i < STROM_ASSERT_ARRAY_SIZE; i++) {
710 row0 = REG_RD(bp, BAR_CSTRORM_INTMEM +
711 CSTORM_ASSERT_LIST_OFFSET(i));
712 row1 = REG_RD(bp, BAR_CSTRORM_INTMEM +
713 CSTORM_ASSERT_LIST_OFFSET(i) + 4);
714 row2 = REG_RD(bp, BAR_CSTRORM_INTMEM +
715 CSTORM_ASSERT_LIST_OFFSET(i) + 8);
716 row3 = REG_RD(bp, BAR_CSTRORM_INTMEM +
717 CSTORM_ASSERT_LIST_OFFSET(i) + 12);
719 if (row0 != COMMON_ASM_INVALID_ASSERT_OPCODE) {
720 BNX2X_ERR("CSTORM_ASSERT_INDEX 0x%x = 0x%08x 0x%08x 0x%08x 0x%08x\n",
721 i, row3, row2, row1, row0);
729 last_idx = REG_RD8(bp, BAR_USTRORM_INTMEM +
730 USTORM_ASSERT_LIST_INDEX_OFFSET);
732 BNX2X_ERR("USTORM_ASSERT_LIST_INDEX 0x%x\n", last_idx);
734 /* print the asserts */
735 for (i = 0; i < STROM_ASSERT_ARRAY_SIZE; i++) {
737 row0 = REG_RD(bp, BAR_USTRORM_INTMEM +
738 USTORM_ASSERT_LIST_OFFSET(i));
739 row1 = REG_RD(bp, BAR_USTRORM_INTMEM +
740 USTORM_ASSERT_LIST_OFFSET(i) + 4);
741 row2 = REG_RD(bp, BAR_USTRORM_INTMEM +
742 USTORM_ASSERT_LIST_OFFSET(i) + 8);
743 row3 = REG_RD(bp, BAR_USTRORM_INTMEM +
744 USTORM_ASSERT_LIST_OFFSET(i) + 12);
746 if (row0 != COMMON_ASM_INVALID_ASSERT_OPCODE) {
747 BNX2X_ERR("USTORM_ASSERT_INDEX 0x%x = 0x%08x 0x%08x 0x%08x 0x%08x\n",
748 i, row3, row2, row1, row0);
758 #define MCPR_TRACE_BUFFER_SIZE (0x800)
759 #define SCRATCH_BUFFER_SIZE(bp) \
760 (CHIP_IS_E1(bp) ? 0x10000 : (CHIP_IS_E1H(bp) ? 0x20000 : 0x28000))
762 void bnx2x_fw_dump_lvl(struct bnx2x *bp, const char *lvl)
768 u32 trace_shmem_base;
770 BNX2X_ERR("NO MCP - can not dump\n");
773 netdev_printk(lvl, bp->dev, "bc %d.%d.%d\n",
774 (bp->common.bc_ver & 0xff0000) >> 16,
775 (bp->common.bc_ver & 0xff00) >> 8,
776 (bp->common.bc_ver & 0xff));
778 val = REG_RD(bp, MCP_REG_MCPR_CPU_PROGRAM_COUNTER);
779 if (val == REG_RD(bp, MCP_REG_MCPR_CPU_PROGRAM_COUNTER))
780 BNX2X_ERR("%s" "MCP PC at 0x%x\n", lvl, val);
782 if (BP_PATH(bp) == 0)
783 trace_shmem_base = bp->common.shmem_base;
785 trace_shmem_base = SHMEM2_RD(bp, other_shmem_base_addr);
788 if (trace_shmem_base < MCPR_SCRATCH_BASE(bp) + MCPR_TRACE_BUFFER_SIZE ||
789 trace_shmem_base >= MCPR_SCRATCH_BASE(bp) +
790 SCRATCH_BUFFER_SIZE(bp)) {
791 BNX2X_ERR("Unable to dump trace buffer (mark %x)\n",
796 addr = trace_shmem_base - MCPR_TRACE_BUFFER_SIZE;
798 /* validate TRCB signature */
799 mark = REG_RD(bp, addr);
800 if (mark != MFW_TRACE_SIGNATURE) {
801 BNX2X_ERR("Trace buffer signature is missing.");
805 /* read cyclic buffer pointer */
807 mark = REG_RD(bp, addr);
808 mark = MCPR_SCRATCH_BASE(bp) + ((mark + 0x3) & ~0x3) - 0x08000000;
809 if (mark >= trace_shmem_base || mark < addr + 4) {
810 BNX2X_ERR("Mark doesn't fall inside Trace Buffer\n");
813 printk("%s" "begin fw dump (mark 0x%x)\n", lvl, mark);
817 /* dump buffer after the mark */
818 for (offset = mark; offset < trace_shmem_base; offset += 0x8*4) {
819 for (word = 0; word < 8; word++)
820 data[word] = htonl(REG_RD(bp, offset + 4*word));
822 pr_cont("%s", (char *)data);
825 /* dump buffer before the mark */
826 for (offset = addr + 4; offset <= mark; offset += 0x8*4) {
827 for (word = 0; word < 8; word++)
828 data[word] = htonl(REG_RD(bp, offset + 4*word));
830 pr_cont("%s", (char *)data);
832 printk("%s" "end of fw dump\n", lvl);
835 static void bnx2x_fw_dump(struct bnx2x *bp)
837 bnx2x_fw_dump_lvl(bp, KERN_ERR);
840 static void bnx2x_hc_int_disable(struct bnx2x *bp)
842 int port = BP_PORT(bp);
843 u32 addr = port ? HC_REG_CONFIG_1 : HC_REG_CONFIG_0;
844 u32 val = REG_RD(bp, addr);
846 /* in E1 we must use only PCI configuration space to disable
847 * MSI/MSIX capability
848 * It's forbidden to disable IGU_PF_CONF_MSI_MSIX_EN in HC block
850 if (CHIP_IS_E1(bp)) {
851 /* Since IGU_PF_CONF_MSI_MSIX_EN still always on
852 * Use mask register to prevent from HC sending interrupts
853 * after we exit the function
855 REG_WR(bp, HC_REG_INT_MASK + port*4, 0);
857 val &= ~(HC_CONFIG_0_REG_SINGLE_ISR_EN_0 |
858 HC_CONFIG_0_REG_INT_LINE_EN_0 |
859 HC_CONFIG_0_REG_ATTN_BIT_EN_0);
861 val &= ~(HC_CONFIG_0_REG_SINGLE_ISR_EN_0 |
862 HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0 |
863 HC_CONFIG_0_REG_INT_LINE_EN_0 |
864 HC_CONFIG_0_REG_ATTN_BIT_EN_0);
867 "write %x to HC %d (addr 0x%x)\n",
870 /* flush all outstanding writes */
873 REG_WR(bp, addr, val);
874 if (REG_RD(bp, addr) != val)
875 BNX2X_ERR("BUG! Proper val not read from IGU!\n");
878 static void bnx2x_igu_int_disable(struct bnx2x *bp)
880 u32 val = REG_RD(bp, IGU_REG_PF_CONFIGURATION);
882 val &= ~(IGU_PF_CONF_MSI_MSIX_EN |
883 IGU_PF_CONF_INT_LINE_EN |
884 IGU_PF_CONF_ATTN_BIT_EN);
886 DP(NETIF_MSG_IFDOWN, "write %x to IGU\n", val);
888 /* flush all outstanding writes */
891 REG_WR(bp, IGU_REG_PF_CONFIGURATION, val);
892 if (REG_RD(bp, IGU_REG_PF_CONFIGURATION) != val)
893 BNX2X_ERR("BUG! Proper val not read from IGU!\n");
896 static void bnx2x_int_disable(struct bnx2x *bp)
898 if (bp->common.int_block == INT_BLOCK_HC)
899 bnx2x_hc_int_disable(bp);
901 bnx2x_igu_int_disable(bp);
904 void bnx2x_panic_dump(struct bnx2x *bp, bool disable_int)
908 struct hc_sp_status_block_data sp_sb_data;
909 int func = BP_FUNC(bp);
910 #ifdef BNX2X_STOP_ON_ERROR
911 u16 start = 0, end = 0;
915 bnx2x_int_disable(bp);
917 bp->stats_state = STATS_STATE_DISABLED;
918 bp->eth_stats.unrecoverable_error++;
919 DP(BNX2X_MSG_STATS, "stats_state - DISABLED\n");
921 BNX2X_ERR("begin crash dump -----------------\n");
925 BNX2X_ERR("def_idx(0x%x) def_att_idx(0x%x) attn_state(0x%x) spq_prod_idx(0x%x) next_stats_cnt(0x%x)\n",
926 bp->def_idx, bp->def_att_idx, bp->attn_state,
927 bp->spq_prod_idx, bp->stats_counter);
928 BNX2X_ERR("DSB: attn bits(0x%x) ack(0x%x) id(0x%x) idx(0x%x)\n",
929 bp->def_status_blk->atten_status_block.attn_bits,
930 bp->def_status_blk->atten_status_block.attn_bits_ack,
931 bp->def_status_blk->atten_status_block.status_block_id,
932 bp->def_status_blk->atten_status_block.attn_bits_index);
934 for (i = 0; i < HC_SP_SB_MAX_INDICES; i++)
936 bp->def_status_blk->sp_sb.index_values[i],
937 (i == HC_SP_SB_MAX_INDICES - 1) ? ") " : " ");
939 for (i = 0; i < sizeof(struct hc_sp_status_block_data)/sizeof(u32); i++)
940 *((u32 *)&sp_sb_data + i) = REG_RD(bp, BAR_CSTRORM_INTMEM +
941 CSTORM_SP_STATUS_BLOCK_DATA_OFFSET(func) +
944 pr_cont("igu_sb_id(0x%x) igu_seg_id(0x%x) pf_id(0x%x) vnic_id(0x%x) vf_id(0x%x) vf_valid (0x%x) state(0x%x)\n",
945 sp_sb_data.igu_sb_id,
946 sp_sb_data.igu_seg_id,
947 sp_sb_data.p_func.pf_id,
948 sp_sb_data.p_func.vnic_id,
949 sp_sb_data.p_func.vf_id,
950 sp_sb_data.p_func.vf_valid,
953 for_each_eth_queue(bp, i) {
954 struct bnx2x_fastpath *fp = &bp->fp[i];
956 struct hc_status_block_data_e2 sb_data_e2;
957 struct hc_status_block_data_e1x sb_data_e1x;
958 struct hc_status_block_sm *hc_sm_p =
960 sb_data_e1x.common.state_machine :
961 sb_data_e2.common.state_machine;
962 struct hc_index_data *hc_index_p =
964 sb_data_e1x.index_data :
965 sb_data_e2.index_data;
968 struct bnx2x_fp_txdata txdata;
971 BNX2X_ERR("fp%d: rx_bd_prod(0x%x) rx_bd_cons(0x%x) rx_comp_prod(0x%x) rx_comp_cons(0x%x) *rx_cons_sb(0x%x)\n",
972 i, fp->rx_bd_prod, fp->rx_bd_cons,
974 fp->rx_comp_cons, le16_to_cpu(*fp->rx_cons_sb));
975 BNX2X_ERR(" rx_sge_prod(0x%x) last_max_sge(0x%x) fp_hc_idx(0x%x)\n",
976 fp->rx_sge_prod, fp->last_max_sge,
977 le16_to_cpu(fp->fp_hc_idx));
980 for_each_cos_in_tx_queue(fp, cos)
982 txdata = *fp->txdata_ptr[cos];
983 BNX2X_ERR("fp%d: tx_pkt_prod(0x%x) tx_pkt_cons(0x%x) tx_bd_prod(0x%x) tx_bd_cons(0x%x) *tx_cons_sb(0x%x)\n",
984 i, txdata.tx_pkt_prod,
985 txdata.tx_pkt_cons, txdata.tx_bd_prod,
987 le16_to_cpu(*txdata.tx_cons_sb));
990 loop = CHIP_IS_E1x(bp) ?
991 HC_SB_MAX_INDICES_E1X : HC_SB_MAX_INDICES_E2;
998 BNX2X_ERR(" run indexes (");
999 for (j = 0; j < HC_SB_MAX_SM; j++)
1001 fp->sb_running_index[j],
1002 (j == HC_SB_MAX_SM - 1) ? ")" : " ");
1004 BNX2X_ERR(" indexes (");
1005 for (j = 0; j < loop; j++)
1007 fp->sb_index_values[j],
1008 (j == loop - 1) ? ")" : " ");
1010 data_size = CHIP_IS_E1x(bp) ?
1011 sizeof(struct hc_status_block_data_e1x) :
1012 sizeof(struct hc_status_block_data_e2);
1013 data_size /= sizeof(u32);
1014 sb_data_p = CHIP_IS_E1x(bp) ?
1015 (u32 *)&sb_data_e1x :
1017 /* copy sb data in here */
1018 for (j = 0; j < data_size; j++)
1019 *(sb_data_p + j) = REG_RD(bp, BAR_CSTRORM_INTMEM +
1020 CSTORM_STATUS_BLOCK_DATA_OFFSET(fp->fw_sb_id) +
1023 if (!CHIP_IS_E1x(bp)) {
1024 pr_cont("pf_id(0x%x) vf_id(0x%x) vf_valid(0x%x) vnic_id(0x%x) same_igu_sb_1b(0x%x) state(0x%x)\n",
1025 sb_data_e2.common.p_func.pf_id,
1026 sb_data_e2.common.p_func.vf_id,
1027 sb_data_e2.common.p_func.vf_valid,
1028 sb_data_e2.common.p_func.vnic_id,
1029 sb_data_e2.common.same_igu_sb_1b,
1030 sb_data_e2.common.state);
1032 pr_cont("pf_id(0x%x) vf_id(0x%x) vf_valid(0x%x) vnic_id(0x%x) same_igu_sb_1b(0x%x) state(0x%x)\n",
1033 sb_data_e1x.common.p_func.pf_id,
1034 sb_data_e1x.common.p_func.vf_id,
1035 sb_data_e1x.common.p_func.vf_valid,
1036 sb_data_e1x.common.p_func.vnic_id,
1037 sb_data_e1x.common.same_igu_sb_1b,
1038 sb_data_e1x.common.state);
1042 for (j = 0; j < HC_SB_MAX_SM; j++) {
1043 pr_cont("SM[%d] __flags (0x%x) igu_sb_id (0x%x) igu_seg_id(0x%x) time_to_expire (0x%x) timer_value(0x%x)\n",
1044 j, hc_sm_p[j].__flags,
1045 hc_sm_p[j].igu_sb_id,
1046 hc_sm_p[j].igu_seg_id,
1047 hc_sm_p[j].time_to_expire,
1048 hc_sm_p[j].timer_value);
1052 for (j = 0; j < loop; j++) {
1053 pr_cont("INDEX[%d] flags (0x%x) timeout (0x%x)\n", j,
1054 hc_index_p[j].flags,
1055 hc_index_p[j].timeout);
1059 #ifdef BNX2X_STOP_ON_ERROR
1062 BNX2X_ERR("eq cons %x prod %x\n", bp->eq_cons, bp->eq_prod);
1063 for (i = 0; i < NUM_EQ_DESC; i++) {
1064 u32 *data = (u32 *)&bp->eq_ring[i].message.data;
1066 BNX2X_ERR("event queue [%d]: header: opcode %d, error %d\n",
1067 i, bp->eq_ring[i].message.opcode,
1068 bp->eq_ring[i].message.error);
1069 BNX2X_ERR("data: %x %x %x\n", data[0], data[1], data[2]);
1074 for_each_valid_rx_queue(bp, i) {
1075 struct bnx2x_fastpath *fp = &bp->fp[i];
1077 start = RX_BD(le16_to_cpu(*fp->rx_cons_sb) - 10);
1078 end = RX_BD(le16_to_cpu(*fp->rx_cons_sb) + 503);
1079 for (j = start; j != end; j = RX_BD(j + 1)) {
1080 u32 *rx_bd = (u32 *)&fp->rx_desc_ring[j];
1081 struct sw_rx_bd *sw_bd = &fp->rx_buf_ring[j];
1083 BNX2X_ERR("fp%d: rx_bd[%x]=[%x:%x] sw_bd=[%p]\n",
1084 i, j, rx_bd[1], rx_bd[0], sw_bd->data);
1087 start = RX_SGE(fp->rx_sge_prod);
1088 end = RX_SGE(fp->last_max_sge);
1089 for (j = start; j != end; j = RX_SGE(j + 1)) {
1090 u32 *rx_sge = (u32 *)&fp->rx_sge_ring[j];
1091 struct sw_rx_page *sw_page = &fp->rx_page_ring[j];
1093 BNX2X_ERR("fp%d: rx_sge[%x]=[%x:%x] sw_page=[%p]\n",
1094 i, j, rx_sge[1], rx_sge[0], sw_page->page);
1097 start = RCQ_BD(fp->rx_comp_cons - 10);
1098 end = RCQ_BD(fp->rx_comp_cons + 503);
1099 for (j = start; j != end; j = RCQ_BD(j + 1)) {
1100 u32 *cqe = (u32 *)&fp->rx_comp_ring[j];
1102 BNX2X_ERR("fp%d: cqe[%x]=[%x:%x:%x:%x]\n",
1103 i, j, cqe[0], cqe[1], cqe[2], cqe[3]);
1108 for_each_valid_tx_queue(bp, i) {
1109 struct bnx2x_fastpath *fp = &bp->fp[i];
1110 for_each_cos_in_tx_queue(fp, cos) {
1111 struct bnx2x_fp_txdata *txdata = fp->txdata_ptr[cos];
1113 start = TX_BD(le16_to_cpu(*txdata->tx_cons_sb) - 10);
1114 end = TX_BD(le16_to_cpu(*txdata->tx_cons_sb) + 245);
1115 for (j = start; j != end; j = TX_BD(j + 1)) {
1116 struct sw_tx_bd *sw_bd =
1117 &txdata->tx_buf_ring[j];
1119 BNX2X_ERR("fp%d: txdata %d, packet[%x]=[%p,%x]\n",
1120 i, cos, j, sw_bd->skb,
1124 start = TX_BD(txdata->tx_bd_cons - 10);
1125 end = TX_BD(txdata->tx_bd_cons + 254);
1126 for (j = start; j != end; j = TX_BD(j + 1)) {
1127 u32 *tx_bd = (u32 *)&txdata->tx_desc_ring[j];
1129 BNX2X_ERR("fp%d: txdata %d, tx_bd[%x]=[%x:%x:%x:%x]\n",
1130 i, cos, j, tx_bd[0], tx_bd[1],
1131 tx_bd[2], tx_bd[3]);
1137 bnx2x_mc_assert(bp);
1138 BNX2X_ERR("end crash dump -----------------\n");
1142 * FLR Support for E2
1144 * bnx2x_pf_flr_clnup() is called during nic_load in the per function HW
1147 #define FLR_WAIT_USEC 10000 /* 10 milliseconds */
1148 #define FLR_WAIT_INTERVAL 50 /* usec */
1149 #define FLR_POLL_CNT (FLR_WAIT_USEC/FLR_WAIT_INTERVAL) /* 200 */
1151 struct pbf_pN_buf_regs {
1158 struct pbf_pN_cmd_regs {
1164 static void bnx2x_pbf_pN_buf_flushed(struct bnx2x *bp,
1165 struct pbf_pN_buf_regs *regs,
1168 u32 init_crd, crd, crd_start, crd_freed, crd_freed_start;
1169 u32 cur_cnt = poll_count;
1171 crd_freed = crd_freed_start = REG_RD(bp, regs->crd_freed);
1172 crd = crd_start = REG_RD(bp, regs->crd);
1173 init_crd = REG_RD(bp, regs->init_crd);
1175 DP(BNX2X_MSG_SP, "INIT CREDIT[%d] : %x\n", regs->pN, init_crd);
1176 DP(BNX2X_MSG_SP, "CREDIT[%d] : s:%x\n", regs->pN, crd);
1177 DP(BNX2X_MSG_SP, "CREDIT_FREED[%d]: s:%x\n", regs->pN, crd_freed);
1179 while ((crd != init_crd) && ((u32)SUB_S32(crd_freed, crd_freed_start) <
1180 (init_crd - crd_start))) {
1182 udelay(FLR_WAIT_INTERVAL);
1183 crd = REG_RD(bp, regs->crd);
1184 crd_freed = REG_RD(bp, regs->crd_freed);
1186 DP(BNX2X_MSG_SP, "PBF tx buffer[%d] timed out\n",
1188 DP(BNX2X_MSG_SP, "CREDIT[%d] : c:%x\n",
1190 DP(BNX2X_MSG_SP, "CREDIT_FREED[%d]: c:%x\n",
1191 regs->pN, crd_freed);
1195 DP(BNX2X_MSG_SP, "Waited %d*%d usec for PBF tx buffer[%d]\n",
1196 poll_count-cur_cnt, FLR_WAIT_INTERVAL, regs->pN);
1199 static void bnx2x_pbf_pN_cmd_flushed(struct bnx2x *bp,
1200 struct pbf_pN_cmd_regs *regs,
1203 u32 occup, to_free, freed, freed_start;
1204 u32 cur_cnt = poll_count;
1206 occup = to_free = REG_RD(bp, regs->lines_occup);
1207 freed = freed_start = REG_RD(bp, regs->lines_freed);
1209 DP(BNX2X_MSG_SP, "OCCUPANCY[%d] : s:%x\n", regs->pN, occup);
1210 DP(BNX2X_MSG_SP, "LINES_FREED[%d] : s:%x\n", regs->pN, freed);
1212 while (occup && ((u32)SUB_S32(freed, freed_start) < to_free)) {
1214 udelay(FLR_WAIT_INTERVAL);
1215 occup = REG_RD(bp, regs->lines_occup);
1216 freed = REG_RD(bp, regs->lines_freed);
1218 DP(BNX2X_MSG_SP, "PBF cmd queue[%d] timed out\n",
1220 DP(BNX2X_MSG_SP, "OCCUPANCY[%d] : s:%x\n",
1222 DP(BNX2X_MSG_SP, "LINES_FREED[%d] : s:%x\n",
1227 DP(BNX2X_MSG_SP, "Waited %d*%d usec for PBF cmd queue[%d]\n",
1228 poll_count-cur_cnt, FLR_WAIT_INTERVAL, regs->pN);
1231 static u32 bnx2x_flr_clnup_reg_poll(struct bnx2x *bp, u32 reg,
1232 u32 expected, u32 poll_count)
1234 u32 cur_cnt = poll_count;
1237 while ((val = REG_RD(bp, reg)) != expected && cur_cnt--)
1238 udelay(FLR_WAIT_INTERVAL);
1243 int bnx2x_flr_clnup_poll_hw_counter(struct bnx2x *bp, u32 reg,
1244 char *msg, u32 poll_cnt)
1246 u32 val = bnx2x_flr_clnup_reg_poll(bp, reg, 0, poll_cnt);
1248 BNX2X_ERR("%s usage count=%d\n", msg, val);
1254 /* Common routines with VF FLR cleanup */
1255 u32 bnx2x_flr_clnup_poll_count(struct bnx2x *bp)
1257 /* adjust polling timeout */
1258 if (CHIP_REV_IS_EMUL(bp))
1259 return FLR_POLL_CNT * 2000;
1261 if (CHIP_REV_IS_FPGA(bp))
1262 return FLR_POLL_CNT * 120;
1264 return FLR_POLL_CNT;
1267 void bnx2x_tx_hw_flushed(struct bnx2x *bp, u32 poll_count)
1269 struct pbf_pN_cmd_regs cmd_regs[] = {
1270 {0, (CHIP_IS_E3B0(bp)) ?
1271 PBF_REG_TQ_OCCUPANCY_Q0 :
1272 PBF_REG_P0_TQ_OCCUPANCY,
1273 (CHIP_IS_E3B0(bp)) ?
1274 PBF_REG_TQ_LINES_FREED_CNT_Q0 :
1275 PBF_REG_P0_TQ_LINES_FREED_CNT},
1276 {1, (CHIP_IS_E3B0(bp)) ?
1277 PBF_REG_TQ_OCCUPANCY_Q1 :
1278 PBF_REG_P1_TQ_OCCUPANCY,
1279 (CHIP_IS_E3B0(bp)) ?
1280 PBF_REG_TQ_LINES_FREED_CNT_Q1 :
1281 PBF_REG_P1_TQ_LINES_FREED_CNT},
1282 {4, (CHIP_IS_E3B0(bp)) ?
1283 PBF_REG_TQ_OCCUPANCY_LB_Q :
1284 PBF_REG_P4_TQ_OCCUPANCY,
1285 (CHIP_IS_E3B0(bp)) ?
1286 PBF_REG_TQ_LINES_FREED_CNT_LB_Q :
1287 PBF_REG_P4_TQ_LINES_FREED_CNT}
1290 struct pbf_pN_buf_regs buf_regs[] = {
1291 {0, (CHIP_IS_E3B0(bp)) ?
1292 PBF_REG_INIT_CRD_Q0 :
1293 PBF_REG_P0_INIT_CRD ,
1294 (CHIP_IS_E3B0(bp)) ?
1297 (CHIP_IS_E3B0(bp)) ?
1298 PBF_REG_INTERNAL_CRD_FREED_CNT_Q0 :
1299 PBF_REG_P0_INTERNAL_CRD_FREED_CNT},
1300 {1, (CHIP_IS_E3B0(bp)) ?
1301 PBF_REG_INIT_CRD_Q1 :
1302 PBF_REG_P1_INIT_CRD,
1303 (CHIP_IS_E3B0(bp)) ?
1306 (CHIP_IS_E3B0(bp)) ?
1307 PBF_REG_INTERNAL_CRD_FREED_CNT_Q1 :
1308 PBF_REG_P1_INTERNAL_CRD_FREED_CNT},
1309 {4, (CHIP_IS_E3B0(bp)) ?
1310 PBF_REG_INIT_CRD_LB_Q :
1311 PBF_REG_P4_INIT_CRD,
1312 (CHIP_IS_E3B0(bp)) ?
1313 PBF_REG_CREDIT_LB_Q :
1315 (CHIP_IS_E3B0(bp)) ?
1316 PBF_REG_INTERNAL_CRD_FREED_CNT_LB_Q :
1317 PBF_REG_P4_INTERNAL_CRD_FREED_CNT},
1322 /* Verify the command queues are flushed P0, P1, P4 */
1323 for (i = 0; i < ARRAY_SIZE(cmd_regs); i++)
1324 bnx2x_pbf_pN_cmd_flushed(bp, &cmd_regs[i], poll_count);
1326 /* Verify the transmission buffers are flushed P0, P1, P4 */
1327 for (i = 0; i < ARRAY_SIZE(buf_regs); i++)
1328 bnx2x_pbf_pN_buf_flushed(bp, &buf_regs[i], poll_count);
1331 #define OP_GEN_PARAM(param) \
1332 (((param) << SDM_OP_GEN_COMP_PARAM_SHIFT) & SDM_OP_GEN_COMP_PARAM)
1334 #define OP_GEN_TYPE(type) \
1335 (((type) << SDM_OP_GEN_COMP_TYPE_SHIFT) & SDM_OP_GEN_COMP_TYPE)
1337 #define OP_GEN_AGG_VECT(index) \
1338 (((index) << SDM_OP_GEN_AGG_VECT_IDX_SHIFT) & SDM_OP_GEN_AGG_VECT_IDX)
1340 int bnx2x_send_final_clnup(struct bnx2x *bp, u8 clnup_func, u32 poll_cnt)
1342 u32 op_gen_command = 0;
1343 u32 comp_addr = BAR_CSTRORM_INTMEM +
1344 CSTORM_FINAL_CLEANUP_COMPLETE_OFFSET(clnup_func);
1347 if (REG_RD(bp, comp_addr)) {
1348 BNX2X_ERR("Cleanup complete was not 0 before sending\n");
1352 op_gen_command |= OP_GEN_PARAM(XSTORM_AGG_INT_FINAL_CLEANUP_INDEX);
1353 op_gen_command |= OP_GEN_TYPE(XSTORM_AGG_INT_FINAL_CLEANUP_COMP_TYPE);
1354 op_gen_command |= OP_GEN_AGG_VECT(clnup_func);
1355 op_gen_command |= 1 << SDM_OP_GEN_AGG_VECT_IDX_VALID_SHIFT;
1357 DP(BNX2X_MSG_SP, "sending FW Final cleanup\n");
1358 REG_WR(bp, XSDM_REG_OPERATION_GEN, op_gen_command);
1360 if (bnx2x_flr_clnup_reg_poll(bp, comp_addr, 1, poll_cnt) != 1) {
1361 BNX2X_ERR("FW final cleanup did not succeed\n");
1362 DP(BNX2X_MSG_SP, "At timeout completion address contained %x\n",
1363 (REG_RD(bp, comp_addr)));
1367 /* Zero completion for next FLR */
1368 REG_WR(bp, comp_addr, 0);
1373 u8 bnx2x_is_pcie_pending(struct pci_dev *dev)
1377 pcie_capability_read_word(dev, PCI_EXP_DEVSTA, &status);
1378 return status & PCI_EXP_DEVSTA_TRPND;
1381 /* PF FLR specific routines
1383 static int bnx2x_poll_hw_usage_counters(struct bnx2x *bp, u32 poll_cnt)
1385 /* wait for CFC PF usage-counter to zero (includes all the VFs) */
1386 if (bnx2x_flr_clnup_poll_hw_counter(bp,
1387 CFC_REG_NUM_LCIDS_INSIDE_PF,
1388 "CFC PF usage counter timed out",
1392 /* Wait for DQ PF usage-counter to zero (until DQ cleanup) */
1393 if (bnx2x_flr_clnup_poll_hw_counter(bp,
1394 DORQ_REG_PF_USAGE_CNT,
1395 "DQ PF usage counter timed out",
1399 /* Wait for QM PF usage-counter to zero (until DQ cleanup) */
1400 if (bnx2x_flr_clnup_poll_hw_counter(bp,
1401 QM_REG_PF_USG_CNT_0 + 4*BP_FUNC(bp),
1402 "QM PF usage counter timed out",
1406 /* Wait for Timer PF usage-counters to zero (until DQ cleanup) */
1407 if (bnx2x_flr_clnup_poll_hw_counter(bp,
1408 TM_REG_LIN0_VNIC_UC + 4*BP_PORT(bp),
1409 "Timers VNIC usage counter timed out",
1412 if (bnx2x_flr_clnup_poll_hw_counter(bp,
1413 TM_REG_LIN0_NUM_SCANS + 4*BP_PORT(bp),
1414 "Timers NUM_SCANS usage counter timed out",
1418 /* Wait DMAE PF usage counter to zero */
1419 if (bnx2x_flr_clnup_poll_hw_counter(bp,
1420 dmae_reg_go_c[INIT_DMAE_C(bp)],
1421 "DMAE command register timed out",
1428 static void bnx2x_hw_enable_status(struct bnx2x *bp)
1432 val = REG_RD(bp, CFC_REG_WEAK_ENABLE_PF);
1433 DP(BNX2X_MSG_SP, "CFC_REG_WEAK_ENABLE_PF is 0x%x\n", val);
1435 val = REG_RD(bp, PBF_REG_DISABLE_PF);
1436 DP(BNX2X_MSG_SP, "PBF_REG_DISABLE_PF is 0x%x\n", val);
1438 val = REG_RD(bp, IGU_REG_PCI_PF_MSI_EN);
1439 DP(BNX2X_MSG_SP, "IGU_REG_PCI_PF_MSI_EN is 0x%x\n", val);
1441 val = REG_RD(bp, IGU_REG_PCI_PF_MSIX_EN);
1442 DP(BNX2X_MSG_SP, "IGU_REG_PCI_PF_MSIX_EN is 0x%x\n", val);
1444 val = REG_RD(bp, IGU_REG_PCI_PF_MSIX_FUNC_MASK);
1445 DP(BNX2X_MSG_SP, "IGU_REG_PCI_PF_MSIX_FUNC_MASK is 0x%x\n", val);
1447 val = REG_RD(bp, PGLUE_B_REG_SHADOW_BME_PF_7_0_CLR);
1448 DP(BNX2X_MSG_SP, "PGLUE_B_REG_SHADOW_BME_PF_7_0_CLR is 0x%x\n", val);
1450 val = REG_RD(bp, PGLUE_B_REG_FLR_REQUEST_PF_7_0_CLR);
1451 DP(BNX2X_MSG_SP, "PGLUE_B_REG_FLR_REQUEST_PF_7_0_CLR is 0x%x\n", val);
1453 val = REG_RD(bp, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER);
1454 DP(BNX2X_MSG_SP, "PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER is 0x%x\n",
1458 static int bnx2x_pf_flr_clnup(struct bnx2x *bp)
1460 u32 poll_cnt = bnx2x_flr_clnup_poll_count(bp);
1462 DP(BNX2X_MSG_SP, "Cleanup after FLR PF[%d]\n", BP_ABS_FUNC(bp));
1464 /* Re-enable PF target read access */
1465 REG_WR(bp, PGLUE_B_REG_INTERNAL_PFID_ENABLE_TARGET_READ, 1);
1467 /* Poll HW usage counters */
1468 DP(BNX2X_MSG_SP, "Polling usage counters\n");
1469 if (bnx2x_poll_hw_usage_counters(bp, poll_cnt))
1472 /* Zero the igu 'trailing edge' and 'leading edge' */
1474 /* Send the FW cleanup command */
1475 if (bnx2x_send_final_clnup(bp, (u8)BP_FUNC(bp), poll_cnt))
1480 /* Verify TX hw is flushed */
1481 bnx2x_tx_hw_flushed(bp, poll_cnt);
1483 /* Wait 100ms (not adjusted according to platform) */
1486 /* Verify no pending pci transactions */
1487 if (bnx2x_is_pcie_pending(bp->pdev))
1488 BNX2X_ERR("PCIE Transactions still pending\n");
1491 bnx2x_hw_enable_status(bp);
1494 * Master enable - Due to WB DMAE writes performed before this
1495 * register is re-initialized as part of the regular function init
1497 REG_WR(bp, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, 1);
1502 static void bnx2x_hc_int_enable(struct bnx2x *bp)
1504 int port = BP_PORT(bp);
1505 u32 addr = port ? HC_REG_CONFIG_1 : HC_REG_CONFIG_0;
1506 u32 val = REG_RD(bp, addr);
1507 bool msix = (bp->flags & USING_MSIX_FLAG) ? true : false;
1508 bool single_msix = (bp->flags & USING_SINGLE_MSIX_FLAG) ? true : false;
1509 bool msi = (bp->flags & USING_MSI_FLAG) ? true : false;
1512 val &= ~(HC_CONFIG_0_REG_SINGLE_ISR_EN_0 |
1513 HC_CONFIG_0_REG_INT_LINE_EN_0);
1514 val |= (HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0 |
1515 HC_CONFIG_0_REG_ATTN_BIT_EN_0);
1517 val |= HC_CONFIG_0_REG_SINGLE_ISR_EN_0;
1519 val &= ~HC_CONFIG_0_REG_INT_LINE_EN_0;
1520 val |= (HC_CONFIG_0_REG_SINGLE_ISR_EN_0 |
1521 HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0 |
1522 HC_CONFIG_0_REG_ATTN_BIT_EN_0);
1524 val |= (HC_CONFIG_0_REG_SINGLE_ISR_EN_0 |
1525 HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0 |
1526 HC_CONFIG_0_REG_INT_LINE_EN_0 |
1527 HC_CONFIG_0_REG_ATTN_BIT_EN_0);
1529 if (!CHIP_IS_E1(bp)) {
1531 "write %x to HC %d (addr 0x%x)\n", val, port, addr);
1533 REG_WR(bp, addr, val);
1535 val &= ~HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0;
1540 REG_WR(bp, HC_REG_INT_MASK + port*4, 0x1FFFF);
1543 "write %x to HC %d (addr 0x%x) mode %s\n", val, port, addr,
1544 (msix ? "MSI-X" : (msi ? "MSI" : "INTx")));
1546 REG_WR(bp, addr, val);
1548 * Ensure that HC_CONFIG is written before leading/trailing edge config
1553 if (!CHIP_IS_E1(bp)) {
1554 /* init leading/trailing edge */
1556 val = (0xee0f | (1 << (BP_VN(bp) + 4)));
1558 /* enable nig and gpio3 attention */
1563 REG_WR(bp, HC_REG_TRAILING_EDGE_0 + port*8, val);
1564 REG_WR(bp, HC_REG_LEADING_EDGE_0 + port*8, val);
1567 /* Make sure that interrupts are indeed enabled from here on */
1571 static void bnx2x_igu_int_enable(struct bnx2x *bp)
1574 bool msix = (bp->flags & USING_MSIX_FLAG) ? true : false;
1575 bool single_msix = (bp->flags & USING_SINGLE_MSIX_FLAG) ? true : false;
1576 bool msi = (bp->flags & USING_MSI_FLAG) ? true : false;
1578 val = REG_RD(bp, IGU_REG_PF_CONFIGURATION);
1581 val &= ~(IGU_PF_CONF_INT_LINE_EN |
1582 IGU_PF_CONF_SINGLE_ISR_EN);
1583 val |= (IGU_PF_CONF_MSI_MSIX_EN |
1584 IGU_PF_CONF_ATTN_BIT_EN);
1587 val |= IGU_PF_CONF_SINGLE_ISR_EN;
1589 val &= ~IGU_PF_CONF_INT_LINE_EN;
1590 val |= (IGU_PF_CONF_MSI_MSIX_EN |
1591 IGU_PF_CONF_ATTN_BIT_EN |
1592 IGU_PF_CONF_SINGLE_ISR_EN);
1594 val &= ~IGU_PF_CONF_MSI_MSIX_EN;
1595 val |= (IGU_PF_CONF_INT_LINE_EN |
1596 IGU_PF_CONF_ATTN_BIT_EN |
1597 IGU_PF_CONF_SINGLE_ISR_EN);
1600 /* Clean previous status - need to configure igu prior to ack*/
1601 if ((!msix) || single_msix) {
1602 REG_WR(bp, IGU_REG_PF_CONFIGURATION, val);
1606 val |= IGU_PF_CONF_FUNC_EN;
1608 DP(NETIF_MSG_IFUP, "write 0x%x to IGU mode %s\n",
1609 val, (msix ? "MSI-X" : (msi ? "MSI" : "INTx")));
1611 REG_WR(bp, IGU_REG_PF_CONFIGURATION, val);
1613 if (val & IGU_PF_CONF_INT_LINE_EN)
1614 pci_intx(bp->pdev, true);
1618 /* init leading/trailing edge */
1620 val = (0xee0f | (1 << (BP_VN(bp) + 4)));
1622 /* enable nig and gpio3 attention */
1627 REG_WR(bp, IGU_REG_TRAILING_EDGE_LATCH, val);
1628 REG_WR(bp, IGU_REG_LEADING_EDGE_LATCH, val);
1630 /* Make sure that interrupts are indeed enabled from here on */
1634 void bnx2x_int_enable(struct bnx2x *bp)
1636 if (bp->common.int_block == INT_BLOCK_HC)
1637 bnx2x_hc_int_enable(bp);
1639 bnx2x_igu_int_enable(bp);
1642 void bnx2x_int_disable_sync(struct bnx2x *bp, int disable_hw)
1644 int msix = (bp->flags & USING_MSIX_FLAG) ? 1 : 0;
1648 /* prevent the HW from sending interrupts */
1649 bnx2x_int_disable(bp);
1651 /* make sure all ISRs are done */
1653 synchronize_irq(bp->msix_table[0].vector);
1655 if (CNIC_SUPPORT(bp))
1657 for_each_eth_queue(bp, i)
1658 synchronize_irq(bp->msix_table[offset++].vector);
1660 synchronize_irq(bp->pdev->irq);
1662 /* make sure sp_task is not running */
1663 cancel_delayed_work(&bp->sp_task);
1664 cancel_delayed_work(&bp->period_task);
1665 flush_workqueue(bnx2x_wq);
1671 * General service functions
1674 /* Return true if succeeded to acquire the lock */
1675 static bool bnx2x_trylock_hw_lock(struct bnx2x *bp, u32 resource)
1678 u32 resource_bit = (1 << resource);
1679 int func = BP_FUNC(bp);
1680 u32 hw_lock_control_reg;
1682 DP(NETIF_MSG_HW | NETIF_MSG_IFUP,
1683 "Trying to take a lock on resource %d\n", resource);
1685 /* Validating that the resource is within range */
1686 if (resource > HW_LOCK_MAX_RESOURCE_VALUE) {
1687 DP(NETIF_MSG_HW | NETIF_MSG_IFUP,
1688 "resource(0x%x) > HW_LOCK_MAX_RESOURCE_VALUE(0x%x)\n",
1689 resource, HW_LOCK_MAX_RESOURCE_VALUE);
1694 hw_lock_control_reg = (MISC_REG_DRIVER_CONTROL_1 + func*8);
1696 hw_lock_control_reg =
1697 (MISC_REG_DRIVER_CONTROL_7 + (func - 6)*8);
1699 /* Try to acquire the lock */
1700 REG_WR(bp, hw_lock_control_reg + 4, resource_bit);
1701 lock_status = REG_RD(bp, hw_lock_control_reg);
1702 if (lock_status & resource_bit)
1705 DP(NETIF_MSG_HW | NETIF_MSG_IFUP,
1706 "Failed to get a lock on resource %d\n", resource);
1711 * bnx2x_get_leader_lock_resource - get the recovery leader resource id
1713 * @bp: driver handle
1715 * Returns the recovery leader resource id according to the engine this function
1716 * belongs to. Currently only only 2 engines is supported.
1718 static int bnx2x_get_leader_lock_resource(struct bnx2x *bp)
1721 return HW_LOCK_RESOURCE_RECOVERY_LEADER_1;
1723 return HW_LOCK_RESOURCE_RECOVERY_LEADER_0;
1727 * bnx2x_trylock_leader_lock- try to acquire a leader lock.
1729 * @bp: driver handle
1731 * Tries to acquire a leader lock for current engine.
1733 static bool bnx2x_trylock_leader_lock(struct bnx2x *bp)
1735 return bnx2x_trylock_hw_lock(bp, bnx2x_get_leader_lock_resource(bp));
1738 static void bnx2x_cnic_cfc_comp(struct bnx2x *bp, int cid, u8 err);
1740 /* schedule the sp task and mark that interrupt occurred (runs from ISR) */
1741 static int bnx2x_schedule_sp_task(struct bnx2x *bp)
1743 /* Set the interrupt occurred bit for the sp-task to recognize it
1744 * must ack the interrupt and transition according to the IGU
1747 atomic_set(&bp->interrupt_occurred, 1);
1749 /* The sp_task must execute only after this bit
1750 * is set, otherwise we will get out of sync and miss all
1751 * further interrupts. Hence, the barrier.
1755 /* schedule sp_task to workqueue */
1756 return queue_delayed_work(bnx2x_wq, &bp->sp_task, 0);
1759 void bnx2x_sp_event(struct bnx2x_fastpath *fp, union eth_rx_cqe *rr_cqe)
1761 struct bnx2x *bp = fp->bp;
1762 int cid = SW_CID(rr_cqe->ramrod_cqe.conn_and_cmd_data);
1763 int command = CQE_CMD(rr_cqe->ramrod_cqe.conn_and_cmd_data);
1764 enum bnx2x_queue_cmd drv_cmd = BNX2X_Q_CMD_MAX;
1765 struct bnx2x_queue_sp_obj *q_obj = &bnx2x_sp_obj(bp, fp).q_obj;
1768 "fp %d cid %d got ramrod #%d state is %x type is %d\n",
1769 fp->index, cid, command, bp->state,
1770 rr_cqe->ramrod_cqe.ramrod_type);
1772 /* If cid is within VF range, replace the slowpath object with the
1773 * one corresponding to this VF
1775 if (cid >= BNX2X_FIRST_VF_CID &&
1776 cid < BNX2X_FIRST_VF_CID + BNX2X_VF_CIDS)
1777 bnx2x_iov_set_queue_sp_obj(bp, cid, &q_obj);
1780 case (RAMROD_CMD_ID_ETH_CLIENT_UPDATE):
1781 DP(BNX2X_MSG_SP, "got UPDATE ramrod. CID %d\n", cid);
1782 drv_cmd = BNX2X_Q_CMD_UPDATE;
1785 case (RAMROD_CMD_ID_ETH_CLIENT_SETUP):
1786 DP(BNX2X_MSG_SP, "got MULTI[%d] setup ramrod\n", cid);
1787 drv_cmd = BNX2X_Q_CMD_SETUP;
1790 case (RAMROD_CMD_ID_ETH_TX_QUEUE_SETUP):
1791 DP(BNX2X_MSG_SP, "got MULTI[%d] tx-only setup ramrod\n", cid);
1792 drv_cmd = BNX2X_Q_CMD_SETUP_TX_ONLY;
1795 case (RAMROD_CMD_ID_ETH_HALT):
1796 DP(BNX2X_MSG_SP, "got MULTI[%d] halt ramrod\n", cid);
1797 drv_cmd = BNX2X_Q_CMD_HALT;
1800 case (RAMROD_CMD_ID_ETH_TERMINATE):
1801 DP(BNX2X_MSG_SP, "got MULTI[%d] terminate ramrod\n", cid);
1802 drv_cmd = BNX2X_Q_CMD_TERMINATE;
1805 case (RAMROD_CMD_ID_ETH_EMPTY):
1806 DP(BNX2X_MSG_SP, "got MULTI[%d] empty ramrod\n", cid);
1807 drv_cmd = BNX2X_Q_CMD_EMPTY;
1811 BNX2X_ERR("unexpected MC reply (%d) on fp[%d]\n",
1812 command, fp->index);
1816 if ((drv_cmd != BNX2X_Q_CMD_MAX) &&
1817 q_obj->complete_cmd(bp, q_obj, drv_cmd))
1818 /* q_obj->complete_cmd() failure means that this was
1819 * an unexpected completion.
1821 * In this case we don't want to increase the bp->spq_left
1822 * because apparently we haven't sent this command the first
1825 #ifdef BNX2X_STOP_ON_ERROR
1830 /* SRIOV: reschedule any 'in_progress' operations */
1831 bnx2x_iov_sp_event(bp, cid, true);
1833 smp_mb__before_atomic_inc();
1834 atomic_inc(&bp->cq_spq_left);
1835 /* push the change in bp->spq_left and towards the memory */
1836 smp_mb__after_atomic_inc();
1838 DP(BNX2X_MSG_SP, "bp->cq_spq_left %x\n", atomic_read(&bp->cq_spq_left));
1840 if ((drv_cmd == BNX2X_Q_CMD_UPDATE) && (IS_FCOE_FP(fp)) &&
1841 (!!test_bit(BNX2X_AFEX_FCOE_Q_UPDATE_PENDING, &bp->sp_state))) {
1842 /* if Q update ramrod is completed for last Q in AFEX vif set
1843 * flow, then ACK MCP at the end
1845 * mark pending ACK to MCP bit.
1846 * prevent case that both bits are cleared.
1847 * At the end of load/unload driver checks that
1848 * sp_state is cleared, and this order prevents
1851 smp_mb__before_clear_bit();
1852 set_bit(BNX2X_AFEX_PENDING_VIFSET_MCP_ACK, &bp->sp_state);
1854 clear_bit(BNX2X_AFEX_FCOE_Q_UPDATE_PENDING, &bp->sp_state);
1855 smp_mb__after_clear_bit();
1857 /* schedule the sp task as mcp ack is required */
1858 bnx2x_schedule_sp_task(bp);
1864 irqreturn_t bnx2x_interrupt(int irq, void *dev_instance)
1866 struct bnx2x *bp = netdev_priv(dev_instance);
1867 u16 status = bnx2x_ack_int(bp);
1872 /* Return here if interrupt is shared and it's not for us */
1873 if (unlikely(status == 0)) {
1874 DP(NETIF_MSG_INTR, "not our interrupt!\n");
1877 DP(NETIF_MSG_INTR, "got an interrupt status 0x%x\n", status);
1879 #ifdef BNX2X_STOP_ON_ERROR
1880 if (unlikely(bp->panic))
1884 for_each_eth_queue(bp, i) {
1885 struct bnx2x_fastpath *fp = &bp->fp[i];
1887 mask = 0x2 << (fp->index + CNIC_SUPPORT(bp));
1888 if (status & mask) {
1889 /* Handle Rx or Tx according to SB id */
1890 for_each_cos_in_tx_queue(fp, cos)
1891 prefetch(fp->txdata_ptr[cos]->tx_cons_sb);
1892 prefetch(&fp->sb_running_index[SM_RX_ID]);
1893 napi_schedule(&bnx2x_fp(bp, fp->index, napi));
1898 if (CNIC_SUPPORT(bp)) {
1900 if (status & (mask | 0x1)) {
1901 struct cnic_ops *c_ops = NULL;
1904 c_ops = rcu_dereference(bp->cnic_ops);
1905 if (c_ops && (bp->cnic_eth_dev.drv_state &
1906 CNIC_DRV_STATE_HANDLES_IRQ))
1907 c_ops->cnic_handler(bp->cnic_data, NULL);
1914 if (unlikely(status & 0x1)) {
1916 /* schedule sp task to perform default status block work, ack
1917 * attentions and enable interrupts.
1919 bnx2x_schedule_sp_task(bp);
1926 if (unlikely(status))
1927 DP(NETIF_MSG_INTR, "got an unknown interrupt! (status 0x%x)\n",
1936 * General service functions
1939 int bnx2x_acquire_hw_lock(struct bnx2x *bp, u32 resource)
1942 u32 resource_bit = (1 << resource);
1943 int func = BP_FUNC(bp);
1944 u32 hw_lock_control_reg;
1947 /* Validating that the resource is within range */
1948 if (resource > HW_LOCK_MAX_RESOURCE_VALUE) {
1949 BNX2X_ERR("resource(0x%x) > HW_LOCK_MAX_RESOURCE_VALUE(0x%x)\n",
1950 resource, HW_LOCK_MAX_RESOURCE_VALUE);
1955 hw_lock_control_reg = (MISC_REG_DRIVER_CONTROL_1 + func*8);
1957 hw_lock_control_reg =
1958 (MISC_REG_DRIVER_CONTROL_7 + (func - 6)*8);
1961 /* Validating that the resource is not already taken */
1962 lock_status = REG_RD(bp, hw_lock_control_reg);
1963 if (lock_status & resource_bit) {
1964 BNX2X_ERR("lock_status 0x%x resource_bit 0x%x\n",
1965 lock_status, resource_bit);
1969 /* Try for 5 second every 5ms */
1970 for (cnt = 0; cnt < 1000; cnt++) {
1971 /* Try to acquire the lock */
1972 REG_WR(bp, hw_lock_control_reg + 4, resource_bit);
1973 lock_status = REG_RD(bp, hw_lock_control_reg);
1974 if (lock_status & resource_bit)
1977 usleep_range(5000, 10000);
1979 BNX2X_ERR("Timeout\n");
1983 int bnx2x_release_leader_lock(struct bnx2x *bp)
1985 return bnx2x_release_hw_lock(bp, bnx2x_get_leader_lock_resource(bp));
1988 int bnx2x_release_hw_lock(struct bnx2x *bp, u32 resource)
1991 u32 resource_bit = (1 << resource);
1992 int func = BP_FUNC(bp);
1993 u32 hw_lock_control_reg;
1995 /* Validating that the resource is within range */
1996 if (resource > HW_LOCK_MAX_RESOURCE_VALUE) {
1997 BNX2X_ERR("resource(0x%x) > HW_LOCK_MAX_RESOURCE_VALUE(0x%x)\n",
1998 resource, HW_LOCK_MAX_RESOURCE_VALUE);
2003 hw_lock_control_reg = (MISC_REG_DRIVER_CONTROL_1 + func*8);
2005 hw_lock_control_reg =
2006 (MISC_REG_DRIVER_CONTROL_7 + (func - 6)*8);
2009 /* Validating that the resource is currently taken */
2010 lock_status = REG_RD(bp, hw_lock_control_reg);
2011 if (!(lock_status & resource_bit)) {
2012 BNX2X_ERR("lock_status 0x%x resource_bit 0x%x. Unlock was called but lock wasn't taken!\n",
2013 lock_status, resource_bit);
2017 REG_WR(bp, hw_lock_control_reg, resource_bit);
2021 int bnx2x_get_gpio(struct bnx2x *bp, int gpio_num, u8 port)
2023 /* The GPIO should be swapped if swap register is set and active */
2024 int gpio_port = (REG_RD(bp, NIG_REG_PORT_SWAP) &&
2025 REG_RD(bp, NIG_REG_STRAP_OVERRIDE)) ^ port;
2026 int gpio_shift = gpio_num +
2027 (gpio_port ? MISC_REGISTERS_GPIO_PORT_SHIFT : 0);
2028 u32 gpio_mask = (1 << gpio_shift);
2032 if (gpio_num > MISC_REGISTERS_GPIO_3) {
2033 BNX2X_ERR("Invalid GPIO %d\n", gpio_num);
2037 /* read GPIO value */
2038 gpio_reg = REG_RD(bp, MISC_REG_GPIO);
2040 /* get the requested pin value */
2041 if ((gpio_reg & gpio_mask) == gpio_mask)
2046 DP(NETIF_MSG_LINK, "pin %d value 0x%x\n", gpio_num, value);
2051 int bnx2x_set_gpio(struct bnx2x *bp, int gpio_num, u32 mode, u8 port)
2053 /* The GPIO should be swapped if swap register is set and active */
2054 int gpio_port = (REG_RD(bp, NIG_REG_PORT_SWAP) &&
2055 REG_RD(bp, NIG_REG_STRAP_OVERRIDE)) ^ port;
2056 int gpio_shift = gpio_num +
2057 (gpio_port ? MISC_REGISTERS_GPIO_PORT_SHIFT : 0);
2058 u32 gpio_mask = (1 << gpio_shift);
2061 if (gpio_num > MISC_REGISTERS_GPIO_3) {
2062 BNX2X_ERR("Invalid GPIO %d\n", gpio_num);
2066 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_GPIO);
2067 /* read GPIO and mask except the float bits */
2068 gpio_reg = (REG_RD(bp, MISC_REG_GPIO) & MISC_REGISTERS_GPIO_FLOAT);
2071 case MISC_REGISTERS_GPIO_OUTPUT_LOW:
2073 "Set GPIO %d (shift %d) -> output low\n",
2074 gpio_num, gpio_shift);
2075 /* clear FLOAT and set CLR */
2076 gpio_reg &= ~(gpio_mask << MISC_REGISTERS_GPIO_FLOAT_POS);
2077 gpio_reg |= (gpio_mask << MISC_REGISTERS_GPIO_CLR_POS);
2080 case MISC_REGISTERS_GPIO_OUTPUT_HIGH:
2082 "Set GPIO %d (shift %d) -> output high\n",
2083 gpio_num, gpio_shift);
2084 /* clear FLOAT and set SET */
2085 gpio_reg &= ~(gpio_mask << MISC_REGISTERS_GPIO_FLOAT_POS);
2086 gpio_reg |= (gpio_mask << MISC_REGISTERS_GPIO_SET_POS);
2089 case MISC_REGISTERS_GPIO_INPUT_HI_Z:
2091 "Set GPIO %d (shift %d) -> input\n",
2092 gpio_num, gpio_shift);
2094 gpio_reg |= (gpio_mask << MISC_REGISTERS_GPIO_FLOAT_POS);
2101 REG_WR(bp, MISC_REG_GPIO, gpio_reg);
2102 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_GPIO);
2107 int bnx2x_set_mult_gpio(struct bnx2x *bp, u8 pins, u32 mode)
2112 /* Any port swapping should be handled by caller. */
2114 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_GPIO);
2115 /* read GPIO and mask except the float bits */
2116 gpio_reg = REG_RD(bp, MISC_REG_GPIO);
2117 gpio_reg &= ~(pins << MISC_REGISTERS_GPIO_FLOAT_POS);
2118 gpio_reg &= ~(pins << MISC_REGISTERS_GPIO_CLR_POS);
2119 gpio_reg &= ~(pins << MISC_REGISTERS_GPIO_SET_POS);
2122 case MISC_REGISTERS_GPIO_OUTPUT_LOW:
2123 DP(NETIF_MSG_LINK, "Set GPIO 0x%x -> output low\n", pins);
2125 gpio_reg |= (pins << MISC_REGISTERS_GPIO_CLR_POS);
2128 case MISC_REGISTERS_GPIO_OUTPUT_HIGH:
2129 DP(NETIF_MSG_LINK, "Set GPIO 0x%x -> output high\n", pins);
2131 gpio_reg |= (pins << MISC_REGISTERS_GPIO_SET_POS);
2134 case MISC_REGISTERS_GPIO_INPUT_HI_Z:
2135 DP(NETIF_MSG_LINK, "Set GPIO 0x%x -> input\n", pins);
2137 gpio_reg |= (pins << MISC_REGISTERS_GPIO_FLOAT_POS);
2141 BNX2X_ERR("Invalid GPIO mode assignment %d\n", mode);
2147 REG_WR(bp, MISC_REG_GPIO, gpio_reg);
2149 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_GPIO);
2154 int bnx2x_set_gpio_int(struct bnx2x *bp, int gpio_num, u32 mode, u8 port)
2156 /* The GPIO should be swapped if swap register is set and active */
2157 int gpio_port = (REG_RD(bp, NIG_REG_PORT_SWAP) &&
2158 REG_RD(bp, NIG_REG_STRAP_OVERRIDE)) ^ port;
2159 int gpio_shift = gpio_num +
2160 (gpio_port ? MISC_REGISTERS_GPIO_PORT_SHIFT : 0);
2161 u32 gpio_mask = (1 << gpio_shift);
2164 if (gpio_num > MISC_REGISTERS_GPIO_3) {
2165 BNX2X_ERR("Invalid GPIO %d\n", gpio_num);
2169 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_GPIO);
2171 gpio_reg = REG_RD(bp, MISC_REG_GPIO_INT);
2174 case MISC_REGISTERS_GPIO_INT_OUTPUT_CLR:
2176 "Clear GPIO INT %d (shift %d) -> output low\n",
2177 gpio_num, gpio_shift);
2178 /* clear SET and set CLR */
2179 gpio_reg &= ~(gpio_mask << MISC_REGISTERS_GPIO_INT_SET_POS);
2180 gpio_reg |= (gpio_mask << MISC_REGISTERS_GPIO_INT_CLR_POS);
2183 case MISC_REGISTERS_GPIO_INT_OUTPUT_SET:
2185 "Set GPIO INT %d (shift %d) -> output high\n",
2186 gpio_num, gpio_shift);
2187 /* clear CLR and set SET */
2188 gpio_reg &= ~(gpio_mask << MISC_REGISTERS_GPIO_INT_CLR_POS);
2189 gpio_reg |= (gpio_mask << MISC_REGISTERS_GPIO_INT_SET_POS);
2196 REG_WR(bp, MISC_REG_GPIO_INT, gpio_reg);
2197 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_GPIO);
2202 static int bnx2x_set_spio(struct bnx2x *bp, int spio, u32 mode)
2206 /* Only 2 SPIOs are configurable */
2207 if ((spio != MISC_SPIO_SPIO4) && (spio != MISC_SPIO_SPIO5)) {
2208 BNX2X_ERR("Invalid SPIO 0x%x\n", spio);
2212 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_SPIO);
2213 /* read SPIO and mask except the float bits */
2214 spio_reg = (REG_RD(bp, MISC_REG_SPIO) & MISC_SPIO_FLOAT);
2217 case MISC_SPIO_OUTPUT_LOW:
2218 DP(NETIF_MSG_HW, "Set SPIO 0x%x -> output low\n", spio);
2219 /* clear FLOAT and set CLR */
2220 spio_reg &= ~(spio << MISC_SPIO_FLOAT_POS);
2221 spio_reg |= (spio << MISC_SPIO_CLR_POS);
2224 case MISC_SPIO_OUTPUT_HIGH:
2225 DP(NETIF_MSG_HW, "Set SPIO 0x%x -> output high\n", spio);
2226 /* clear FLOAT and set SET */
2227 spio_reg &= ~(spio << MISC_SPIO_FLOAT_POS);
2228 spio_reg |= (spio << MISC_SPIO_SET_POS);
2231 case MISC_SPIO_INPUT_HI_Z:
2232 DP(NETIF_MSG_HW, "Set SPIO 0x%x -> input\n", spio);
2234 spio_reg |= (spio << MISC_SPIO_FLOAT_POS);
2241 REG_WR(bp, MISC_REG_SPIO, spio_reg);
2242 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_SPIO);
2247 void bnx2x_calc_fc_adv(struct bnx2x *bp)
2249 u8 cfg_idx = bnx2x_get_link_cfg_idx(bp);
2250 switch (bp->link_vars.ieee_fc &
2251 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_MASK) {
2252 case MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_NONE:
2253 bp->port.advertising[cfg_idx] &= ~(ADVERTISED_Asym_Pause |
2257 case MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH:
2258 bp->port.advertising[cfg_idx] |= (ADVERTISED_Asym_Pause |
2262 case MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC:
2263 bp->port.advertising[cfg_idx] |= ADVERTISED_Asym_Pause;
2267 bp->port.advertising[cfg_idx] &= ~(ADVERTISED_Asym_Pause |
2273 static void bnx2x_set_requested_fc(struct bnx2x *bp)
2275 /* Initialize link parameters structure variables
2276 * It is recommended to turn off RX FC for jumbo frames
2277 * for better performance
2279 if (CHIP_IS_E1x(bp) && (bp->dev->mtu > 5000))
2280 bp->link_params.req_fc_auto_adv = BNX2X_FLOW_CTRL_TX;
2282 bp->link_params.req_fc_auto_adv = BNX2X_FLOW_CTRL_BOTH;
2285 static void bnx2x_init_dropless_fc(struct bnx2x *bp)
2287 u32 pause_enabled = 0;
2289 if (!CHIP_IS_E1(bp) && bp->dropless_fc && bp->link_vars.link_up) {
2290 if (bp->link_vars.flow_ctrl & BNX2X_FLOW_CTRL_TX)
2293 REG_WR(bp, BAR_USTRORM_INTMEM +
2294 USTORM_ETH_PAUSE_ENABLED_OFFSET(BP_PORT(bp)),
2298 DP(NETIF_MSG_IFUP | NETIF_MSG_LINK, "dropless_fc is %s\n",
2299 pause_enabled ? "enabled" : "disabled");
2302 int bnx2x_initial_phy_init(struct bnx2x *bp, int load_mode)
2304 int rc, cfx_idx = bnx2x_get_link_cfg_idx(bp);
2305 u16 req_line_speed = bp->link_params.req_line_speed[cfx_idx];
2307 if (!BP_NOMCP(bp)) {
2308 bnx2x_set_requested_fc(bp);
2309 bnx2x_acquire_phy_lock(bp);
2311 if (load_mode == LOAD_DIAG) {
2312 struct link_params *lp = &bp->link_params;
2313 lp->loopback_mode = LOOPBACK_XGXS;
2314 /* do PHY loopback at 10G speed, if possible */
2315 if (lp->req_line_speed[cfx_idx] < SPEED_10000) {
2316 if (lp->speed_cap_mask[cfx_idx] &
2317 PORT_HW_CFG_SPEED_CAPABILITY_D0_10G)
2318 lp->req_line_speed[cfx_idx] =
2321 lp->req_line_speed[cfx_idx] =
2326 if (load_mode == LOAD_LOOPBACK_EXT) {
2327 struct link_params *lp = &bp->link_params;
2328 lp->loopback_mode = LOOPBACK_EXT;
2331 rc = bnx2x_phy_init(&bp->link_params, &bp->link_vars);
2333 bnx2x_release_phy_lock(bp);
2335 bnx2x_init_dropless_fc(bp);
2337 bnx2x_calc_fc_adv(bp);
2339 if (bp->link_vars.link_up) {
2340 bnx2x_stats_handle(bp, STATS_EVENT_LINK_UP);
2341 bnx2x_link_report(bp);
2343 queue_delayed_work(bnx2x_wq, &bp->period_task, 0);
2344 bp->link_params.req_line_speed[cfx_idx] = req_line_speed;
2347 BNX2X_ERR("Bootcode is missing - can not initialize link\n");
2351 void bnx2x_link_set(struct bnx2x *bp)
2353 if (!BP_NOMCP(bp)) {
2354 bnx2x_acquire_phy_lock(bp);
2355 bnx2x_phy_init(&bp->link_params, &bp->link_vars);
2356 bnx2x_release_phy_lock(bp);
2358 bnx2x_init_dropless_fc(bp);
2360 bnx2x_calc_fc_adv(bp);
2362 BNX2X_ERR("Bootcode is missing - can not set link\n");
2365 static void bnx2x__link_reset(struct bnx2x *bp)
2367 if (!BP_NOMCP(bp)) {
2368 bnx2x_acquire_phy_lock(bp);
2369 bnx2x_lfa_reset(&bp->link_params, &bp->link_vars);
2370 bnx2x_release_phy_lock(bp);
2372 BNX2X_ERR("Bootcode is missing - can not reset link\n");
2375 void bnx2x_force_link_reset(struct bnx2x *bp)
2377 bnx2x_acquire_phy_lock(bp);
2378 bnx2x_link_reset(&bp->link_params, &bp->link_vars, 1);
2379 bnx2x_release_phy_lock(bp);
2382 u8 bnx2x_link_test(struct bnx2x *bp, u8 is_serdes)
2386 if (!BP_NOMCP(bp)) {
2387 bnx2x_acquire_phy_lock(bp);
2388 rc = bnx2x_test_link(&bp->link_params, &bp->link_vars,
2390 bnx2x_release_phy_lock(bp);
2392 BNX2X_ERR("Bootcode is missing - can not test link\n");
2397 /* Calculates the sum of vn_min_rates.
2398 It's needed for further normalizing of the min_rates.
2400 sum of vn_min_rates.
2402 0 - if all the min_rates are 0.
2403 In the later case fairness algorithm should be deactivated.
2404 If not all min_rates are zero then those that are zeroes will be set to 1.
2406 static void bnx2x_calc_vn_min(struct bnx2x *bp,
2407 struct cmng_init_input *input)
2412 for (vn = VN_0; vn < BP_MAX_VN_NUM(bp); vn++) {
2413 u32 vn_cfg = bp->mf_config[vn];
2414 u32 vn_min_rate = ((vn_cfg & FUNC_MF_CFG_MIN_BW_MASK) >>
2415 FUNC_MF_CFG_MIN_BW_SHIFT) * 100;
2417 /* Skip hidden vns */
2418 if (vn_cfg & FUNC_MF_CFG_FUNC_HIDE)
2420 /* If min rate is zero - set it to 1 */
2421 else if (!vn_min_rate)
2422 vn_min_rate = DEF_MIN_RATE;
2426 input->vnic_min_rate[vn] = vn_min_rate;
2429 /* if ETS or all min rates are zeros - disable fairness */
2430 if (BNX2X_IS_ETS_ENABLED(bp)) {
2431 input->flags.cmng_enables &=
2432 ~CMNG_FLAGS_PER_PORT_FAIRNESS_VN;
2433 DP(NETIF_MSG_IFUP, "Fairness will be disabled due to ETS\n");
2434 } else if (all_zero) {
2435 input->flags.cmng_enables &=
2436 ~CMNG_FLAGS_PER_PORT_FAIRNESS_VN;
2438 "All MIN values are zeroes fairness will be disabled\n");
2440 input->flags.cmng_enables |=
2441 CMNG_FLAGS_PER_PORT_FAIRNESS_VN;
2444 static void bnx2x_calc_vn_max(struct bnx2x *bp, int vn,
2445 struct cmng_init_input *input)
2448 u32 vn_cfg = bp->mf_config[vn];
2450 if (vn_cfg & FUNC_MF_CFG_FUNC_HIDE)
2453 u32 maxCfg = bnx2x_extract_max_cfg(bp, vn_cfg);
2456 /* maxCfg in percents of linkspeed */
2457 vn_max_rate = (bp->link_vars.line_speed * maxCfg) / 100;
2458 } else /* SD modes */
2459 /* maxCfg is absolute in 100Mb units */
2460 vn_max_rate = maxCfg * 100;
2463 DP(NETIF_MSG_IFUP, "vn %d: vn_max_rate %d\n", vn, vn_max_rate);
2465 input->vnic_max_rate[vn] = vn_max_rate;
2468 static int bnx2x_get_cmng_fns_mode(struct bnx2x *bp)
2470 if (CHIP_REV_IS_SLOW(bp))
2471 return CMNG_FNS_NONE;
2473 return CMNG_FNS_MINMAX;
2475 return CMNG_FNS_NONE;
2478 void bnx2x_read_mf_cfg(struct bnx2x *bp)
2480 int vn, n = (CHIP_MODE_IS_4_PORT(bp) ? 2 : 1);
2483 return; /* what should be the default value in this case */
2485 /* For 2 port configuration the absolute function number formula
2487 * abs_func = 2 * vn + BP_PORT + BP_PATH
2489 * and there are 4 functions per port
2491 * For 4 port configuration it is
2492 * abs_func = 4 * vn + 2 * BP_PORT + BP_PATH
2494 * and there are 2 functions per port
2496 for (vn = VN_0; vn < BP_MAX_VN_NUM(bp); vn++) {
2497 int /*abs*/func = n * (2 * vn + BP_PORT(bp)) + BP_PATH(bp);
2499 if (func >= E1H_FUNC_MAX)
2503 MF_CFG_RD(bp, func_mf_config[func].config);
2505 if (bp->mf_config[BP_VN(bp)] & FUNC_MF_CFG_FUNC_DISABLED) {
2506 DP(NETIF_MSG_IFUP, "mf_cfg function disabled\n");
2507 bp->flags |= MF_FUNC_DIS;
2509 DP(NETIF_MSG_IFUP, "mf_cfg function enabled\n");
2510 bp->flags &= ~MF_FUNC_DIS;
2514 static void bnx2x_cmng_fns_init(struct bnx2x *bp, u8 read_cfg, u8 cmng_type)
2516 struct cmng_init_input input;
2517 memset(&input, 0, sizeof(struct cmng_init_input));
2519 input.port_rate = bp->link_vars.line_speed;
2521 if (cmng_type == CMNG_FNS_MINMAX && input.port_rate) {
2524 /* read mf conf from shmem */
2526 bnx2x_read_mf_cfg(bp);
2528 /* vn_weight_sum and enable fairness if not 0 */
2529 bnx2x_calc_vn_min(bp, &input);
2531 /* calculate and set min-max rate for each vn */
2533 for (vn = VN_0; vn < BP_MAX_VN_NUM(bp); vn++)
2534 bnx2x_calc_vn_max(bp, vn, &input);
2536 /* always enable rate shaping and fairness */
2537 input.flags.cmng_enables |=
2538 CMNG_FLAGS_PER_PORT_RATE_SHAPING_VN;
2540 bnx2x_init_cmng(&input, &bp->cmng);
2544 /* rate shaping and fairness are disabled */
2546 "rate shaping and fairness are disabled\n");
2549 static void storm_memset_cmng(struct bnx2x *bp,
2550 struct cmng_init *cmng,
2554 size_t size = sizeof(struct cmng_struct_per_port);
2556 u32 addr = BAR_XSTRORM_INTMEM +
2557 XSTORM_CMNG_PER_PORT_VARS_OFFSET(port);
2559 __storm_memset_struct(bp, addr, size, (u32 *)&cmng->port);
2561 for (vn = VN_0; vn < BP_MAX_VN_NUM(bp); vn++) {
2562 int func = func_by_vn(bp, vn);
2564 addr = BAR_XSTRORM_INTMEM +
2565 XSTORM_RATE_SHAPING_PER_VN_VARS_OFFSET(func);
2566 size = sizeof(struct rate_shaping_vars_per_vn);
2567 __storm_memset_struct(bp, addr, size,
2568 (u32 *)&cmng->vnic.vnic_max_rate[vn]);
2570 addr = BAR_XSTRORM_INTMEM +
2571 XSTORM_FAIRNESS_PER_VN_VARS_OFFSET(func);
2572 size = sizeof(struct fairness_vars_per_vn);
2573 __storm_memset_struct(bp, addr, size,
2574 (u32 *)&cmng->vnic.vnic_min_rate[vn]);
2578 /* init cmng mode in HW according to local configuration */
2579 void bnx2x_set_local_cmng(struct bnx2x *bp)
2581 int cmng_fns = bnx2x_get_cmng_fns_mode(bp);
2583 if (cmng_fns != CMNG_FNS_NONE) {
2584 bnx2x_cmng_fns_init(bp, false, cmng_fns);
2585 storm_memset_cmng(bp, &bp->cmng, BP_PORT(bp));
2587 /* rate shaping and fairness are disabled */
2589 "single function mode without fairness\n");
2593 /* This function is called upon link interrupt */
2594 static void bnx2x_link_attn(struct bnx2x *bp)
2596 /* Make sure that we are synced with the current statistics */
2597 bnx2x_stats_handle(bp, STATS_EVENT_STOP);
2599 bnx2x_link_update(&bp->link_params, &bp->link_vars);
2601 bnx2x_init_dropless_fc(bp);
2603 if (bp->link_vars.link_up) {
2605 if (bp->link_vars.mac_type != MAC_TYPE_EMAC) {
2606 struct host_port_stats *pstats;
2608 pstats = bnx2x_sp(bp, port_stats);
2609 /* reset old mac stats */
2610 memset(&(pstats->mac_stx[0]), 0,
2611 sizeof(struct mac_stx));
2613 if (bp->state == BNX2X_STATE_OPEN)
2614 bnx2x_stats_handle(bp, STATS_EVENT_LINK_UP);
2617 if (bp->link_vars.link_up && bp->link_vars.line_speed)
2618 bnx2x_set_local_cmng(bp);
2620 __bnx2x_link_report(bp);
2623 bnx2x_link_sync_notify(bp);
2626 void bnx2x__link_status_update(struct bnx2x *bp)
2628 if (bp->state != BNX2X_STATE_OPEN)
2631 /* read updated dcb configuration */
2633 bnx2x_dcbx_pmf_update(bp);
2634 bnx2x_link_status_update(&bp->link_params, &bp->link_vars);
2635 if (bp->link_vars.link_up)
2636 bnx2x_stats_handle(bp, STATS_EVENT_LINK_UP);
2638 bnx2x_stats_handle(bp, STATS_EVENT_STOP);
2639 /* indicate link status */
2640 bnx2x_link_report(bp);
2643 bp->port.supported[0] |= (SUPPORTED_10baseT_Half |
2644 SUPPORTED_10baseT_Full |
2645 SUPPORTED_100baseT_Half |
2646 SUPPORTED_100baseT_Full |
2647 SUPPORTED_1000baseT_Full |
2648 SUPPORTED_2500baseX_Full |
2649 SUPPORTED_10000baseT_Full |
2654 SUPPORTED_Asym_Pause);
2655 bp->port.advertising[0] = bp->port.supported[0];
2657 bp->link_params.bp = bp;
2658 bp->link_params.port = BP_PORT(bp);
2659 bp->link_params.req_duplex[0] = DUPLEX_FULL;
2660 bp->link_params.req_flow_ctrl[0] = BNX2X_FLOW_CTRL_NONE;
2661 bp->link_params.req_line_speed[0] = SPEED_10000;
2662 bp->link_params.speed_cap_mask[0] = 0x7f0000;
2663 bp->link_params.switch_cfg = SWITCH_CFG_10G;
2664 bp->link_vars.mac_type = MAC_TYPE_BMAC;
2665 bp->link_vars.line_speed = SPEED_10000;
2666 bp->link_vars.link_status =
2667 (LINK_STATUS_LINK_UP |
2668 LINK_STATUS_SPEED_AND_DUPLEX_10GTFD);
2669 bp->link_vars.link_up = 1;
2670 bp->link_vars.duplex = DUPLEX_FULL;
2671 bp->link_vars.flow_ctrl = BNX2X_FLOW_CTRL_NONE;
2672 __bnx2x_link_report(bp);
2673 bnx2x_stats_handle(bp, STATS_EVENT_LINK_UP);
2677 static int bnx2x_afex_func_update(struct bnx2x *bp, u16 vifid,
2678 u16 vlan_val, u8 allowed_prio)
2680 struct bnx2x_func_state_params func_params = {NULL};
2681 struct bnx2x_func_afex_update_params *f_update_params =
2682 &func_params.params.afex_update;
2684 func_params.f_obj = &bp->func_obj;
2685 func_params.cmd = BNX2X_F_CMD_AFEX_UPDATE;
2687 /* no need to wait for RAMROD completion, so don't
2688 * set RAMROD_COMP_WAIT flag
2691 f_update_params->vif_id = vifid;
2692 f_update_params->afex_default_vlan = vlan_val;
2693 f_update_params->allowed_priorities = allowed_prio;
2695 /* if ramrod can not be sent, response to MCP immediately */
2696 if (bnx2x_func_state_change(bp, &func_params) < 0)
2697 bnx2x_fw_command(bp, DRV_MSG_CODE_AFEX_VIFSET_ACK, 0);
2702 static int bnx2x_afex_handle_vif_list_cmd(struct bnx2x *bp, u8 cmd_type,
2703 u16 vif_index, u8 func_bit_map)
2705 struct bnx2x_func_state_params func_params = {NULL};
2706 struct bnx2x_func_afex_viflists_params *update_params =
2707 &func_params.params.afex_viflists;
2711 /* validate only LIST_SET and LIST_GET are received from switch */
2712 if ((cmd_type != VIF_LIST_RULE_GET) && (cmd_type != VIF_LIST_RULE_SET))
2713 BNX2X_ERR("BUG! afex_handle_vif_list_cmd invalid type 0x%x\n",
2716 func_params.f_obj = &bp->func_obj;
2717 func_params.cmd = BNX2X_F_CMD_AFEX_VIFLISTS;
2719 /* set parameters according to cmd_type */
2720 update_params->afex_vif_list_command = cmd_type;
2721 update_params->vif_list_index = vif_index;
2722 update_params->func_bit_map =
2723 (cmd_type == VIF_LIST_RULE_GET) ? 0 : func_bit_map;
2724 update_params->func_to_clear = 0;
2726 (cmd_type == VIF_LIST_RULE_GET) ?
2727 DRV_MSG_CODE_AFEX_LISTGET_ACK :
2728 DRV_MSG_CODE_AFEX_LISTSET_ACK;
2730 /* if ramrod can not be sent, respond to MCP immediately for
2731 * SET and GET requests (other are not triggered from MCP)
2733 rc = bnx2x_func_state_change(bp, &func_params);
2735 bnx2x_fw_command(bp, drv_msg_code, 0);
2740 static void bnx2x_handle_afex_cmd(struct bnx2x *bp, u32 cmd)
2742 struct afex_stats afex_stats;
2743 u32 func = BP_ABS_FUNC(bp);
2750 u32 addr_to_write, vifid, addrs, stats_type, i;
2752 if (cmd & DRV_STATUS_AFEX_LISTGET_REQ) {
2753 vifid = SHMEM2_RD(bp, afex_param1_to_driver[BP_FW_MB_IDX(bp)]);
2755 "afex: got MCP req LISTGET_REQ for vifid 0x%x\n", vifid);
2756 bnx2x_afex_handle_vif_list_cmd(bp, VIF_LIST_RULE_GET, vifid, 0);
2759 if (cmd & DRV_STATUS_AFEX_LISTSET_REQ) {
2760 vifid = SHMEM2_RD(bp, afex_param1_to_driver[BP_FW_MB_IDX(bp)]);
2761 addrs = SHMEM2_RD(bp, afex_param2_to_driver[BP_FW_MB_IDX(bp)]);
2763 "afex: got MCP req LISTSET_REQ for vifid 0x%x addrs 0x%x\n",
2765 bnx2x_afex_handle_vif_list_cmd(bp, VIF_LIST_RULE_SET, vifid,
2769 if (cmd & DRV_STATUS_AFEX_STATSGET_REQ) {
2770 addr_to_write = SHMEM2_RD(bp,
2771 afex_scratchpad_addr_to_write[BP_FW_MB_IDX(bp)]);
2772 stats_type = SHMEM2_RD(bp,
2773 afex_param1_to_driver[BP_FW_MB_IDX(bp)]);
2776 "afex: got MCP req STATSGET_REQ, write to addr 0x%x\n",
2779 bnx2x_afex_collect_stats(bp, (void *)&afex_stats, stats_type);
2781 /* write response to scratchpad, for MCP */
2782 for (i = 0; i < (sizeof(struct afex_stats)/sizeof(u32)); i++)
2783 REG_WR(bp, addr_to_write + i*sizeof(u32),
2784 *(((u32 *)(&afex_stats))+i));
2786 /* send ack message to MCP */
2787 bnx2x_fw_command(bp, DRV_MSG_CODE_AFEX_STATSGET_ACK, 0);
2790 if (cmd & DRV_STATUS_AFEX_VIFSET_REQ) {
2791 mf_config = MF_CFG_RD(bp, func_mf_config[func].config);
2792 bp->mf_config[BP_VN(bp)] = mf_config;
2794 "afex: got MCP req VIFSET_REQ, mf_config 0x%x\n",
2797 /* if VIF_SET is "enabled" */
2798 if (!(mf_config & FUNC_MF_CFG_FUNC_DISABLED)) {
2799 /* set rate limit directly to internal RAM */
2800 struct cmng_init_input cmng_input;
2801 struct rate_shaping_vars_per_vn m_rs_vn;
2802 size_t size = sizeof(struct rate_shaping_vars_per_vn);
2803 u32 addr = BAR_XSTRORM_INTMEM +
2804 XSTORM_RATE_SHAPING_PER_VN_VARS_OFFSET(BP_FUNC(bp));
2806 bp->mf_config[BP_VN(bp)] = mf_config;
2808 bnx2x_calc_vn_max(bp, BP_VN(bp), &cmng_input);
2809 m_rs_vn.vn_counter.rate =
2810 cmng_input.vnic_max_rate[BP_VN(bp)];
2811 m_rs_vn.vn_counter.quota =
2812 (m_rs_vn.vn_counter.rate *
2813 RS_PERIODIC_TIMEOUT_USEC) / 8;
2815 __storm_memset_struct(bp, addr, size, (u32 *)&m_rs_vn);
2817 /* read relevant values from mf_cfg struct in shmem */
2819 (MF_CFG_RD(bp, func_mf_config[func].e1hov_tag) &
2820 FUNC_MF_CFG_E1HOV_TAG_MASK) >>
2821 FUNC_MF_CFG_E1HOV_TAG_SHIFT;
2823 (MF_CFG_RD(bp, func_mf_config[func].e1hov_tag) &
2824 FUNC_MF_CFG_AFEX_VLAN_MASK) >>
2825 FUNC_MF_CFG_AFEX_VLAN_SHIFT;
2826 vlan_prio = (mf_config &
2827 FUNC_MF_CFG_TRANSMIT_PRIORITY_MASK) >>
2828 FUNC_MF_CFG_TRANSMIT_PRIORITY_SHIFT;
2829 vlan_val |= (vlan_prio << VLAN_PRIO_SHIFT);
2832 func_mf_config[func].afex_config) &
2833 FUNC_MF_CFG_AFEX_VLAN_MODE_MASK) >>
2834 FUNC_MF_CFG_AFEX_VLAN_MODE_SHIFT;
2837 func_mf_config[func].afex_config) &
2838 FUNC_MF_CFG_AFEX_COS_FILTER_MASK) >>
2839 FUNC_MF_CFG_AFEX_COS_FILTER_SHIFT;
2841 /* send ramrod to FW, return in case of failure */
2842 if (bnx2x_afex_func_update(bp, vif_id, vlan_val,
2846 bp->afex_def_vlan_tag = vlan_val;
2847 bp->afex_vlan_mode = vlan_mode;
2849 /* notify link down because BP->flags is disabled */
2850 bnx2x_link_report(bp);
2852 /* send INVALID VIF ramrod to FW */
2853 bnx2x_afex_func_update(bp, 0xFFFF, 0, 0);
2855 /* Reset the default afex VLAN */
2856 bp->afex_def_vlan_tag = -1;
2861 static void bnx2x_pmf_update(struct bnx2x *bp)
2863 int port = BP_PORT(bp);
2867 DP(BNX2X_MSG_MCP, "pmf %d\n", bp->port.pmf);
2870 * We need the mb() to ensure the ordering between the writing to
2871 * bp->port.pmf here and reading it from the bnx2x_periodic_task().
2875 /* queue a periodic task */
2876 queue_delayed_work(bnx2x_wq, &bp->period_task, 0);
2878 bnx2x_dcbx_pmf_update(bp);
2880 /* enable nig attention */
2881 val = (0xff0f | (1 << (BP_VN(bp) + 4)));
2882 if (bp->common.int_block == INT_BLOCK_HC) {
2883 REG_WR(bp, HC_REG_TRAILING_EDGE_0 + port*8, val);
2884 REG_WR(bp, HC_REG_LEADING_EDGE_0 + port*8, val);
2885 } else if (!CHIP_IS_E1x(bp)) {
2886 REG_WR(bp, IGU_REG_TRAILING_EDGE_LATCH, val);
2887 REG_WR(bp, IGU_REG_LEADING_EDGE_LATCH, val);
2890 bnx2x_stats_handle(bp, STATS_EVENT_PMF);
2898 * General service functions
2901 /* send the MCP a request, block until there is a reply */
2902 u32 bnx2x_fw_command(struct bnx2x *bp, u32 command, u32 param)
2904 int mb_idx = BP_FW_MB_IDX(bp);
2908 u8 delay = CHIP_REV_IS_SLOW(bp) ? 100 : 10;
2910 mutex_lock(&bp->fw_mb_mutex);
2912 SHMEM_WR(bp, func_mb[mb_idx].drv_mb_param, param);
2913 SHMEM_WR(bp, func_mb[mb_idx].drv_mb_header, (command | seq));
2915 DP(BNX2X_MSG_MCP, "wrote command (%x) to FW MB param 0x%08x\n",
2916 (command | seq), param);
2919 /* let the FW do it's magic ... */
2922 rc = SHMEM_RD(bp, func_mb[mb_idx].fw_mb_header);
2924 /* Give the FW up to 5 second (500*10ms) */
2925 } while ((seq != (rc & FW_MSG_SEQ_NUMBER_MASK)) && (cnt++ < 500));
2927 DP(BNX2X_MSG_MCP, "[after %d ms] read (%x) seq is (%x) from FW MB\n",
2928 cnt*delay, rc, seq);
2930 /* is this a reply to our command? */
2931 if (seq == (rc & FW_MSG_SEQ_NUMBER_MASK))
2932 rc &= FW_MSG_CODE_MASK;
2935 BNX2X_ERR("FW failed to respond!\n");
2939 mutex_unlock(&bp->fw_mb_mutex);
2944 static void storm_memset_func_cfg(struct bnx2x *bp,
2945 struct tstorm_eth_function_common_config *tcfg,
2948 size_t size = sizeof(struct tstorm_eth_function_common_config);
2950 u32 addr = BAR_TSTRORM_INTMEM +
2951 TSTORM_FUNCTION_COMMON_CONFIG_OFFSET(abs_fid);
2953 __storm_memset_struct(bp, addr, size, (u32 *)tcfg);
2956 void bnx2x_func_init(struct bnx2x *bp, struct bnx2x_func_init_params *p)
2958 if (CHIP_IS_E1x(bp)) {
2959 struct tstorm_eth_function_common_config tcfg = {0};
2961 storm_memset_func_cfg(bp, &tcfg, p->func_id);
2964 /* Enable the function in the FW */
2965 storm_memset_vf_to_pf(bp, p->func_id, p->pf_id);
2966 storm_memset_func_en(bp, p->func_id, 1);
2969 if (p->func_flgs & FUNC_FLG_SPQ) {
2970 storm_memset_spq_addr(bp, p->spq_map, p->func_id);
2971 REG_WR(bp, XSEM_REG_FAST_MEMORY +
2972 XSTORM_SPQ_PROD_OFFSET(p->func_id), p->spq_prod);
2977 * bnx2x_get_common_flags - Return common flags
2981 * @zero_stats TRUE if statistics zeroing is needed
2983 * Return the flags that are common for the Tx-only and not normal connections.
2985 static unsigned long bnx2x_get_common_flags(struct bnx2x *bp,
2986 struct bnx2x_fastpath *fp,
2989 unsigned long flags = 0;
2991 /* PF driver will always initialize the Queue to an ACTIVE state */
2992 __set_bit(BNX2X_Q_FLG_ACTIVE, &flags);
2994 /* tx only connections collect statistics (on the same index as the
2995 * parent connection). The statistics are zeroed when the parent
2996 * connection is initialized.
2999 __set_bit(BNX2X_Q_FLG_STATS, &flags);
3001 __set_bit(BNX2X_Q_FLG_ZERO_STATS, &flags);
3003 __set_bit(BNX2X_Q_FLG_PCSUM_ON_PKT, &flags);
3004 __set_bit(BNX2X_Q_FLG_TUN_INC_INNER_IP_ID, &flags);
3006 #ifdef BNX2X_STOP_ON_ERROR
3007 __set_bit(BNX2X_Q_FLG_TX_SEC, &flags);
3013 static unsigned long bnx2x_get_q_flags(struct bnx2x *bp,
3014 struct bnx2x_fastpath *fp,
3017 unsigned long flags = 0;
3019 /* calculate other queue flags */
3021 __set_bit(BNX2X_Q_FLG_OV, &flags);
3023 if (IS_FCOE_FP(fp)) {
3024 __set_bit(BNX2X_Q_FLG_FCOE, &flags);
3025 /* For FCoE - force usage of default priority (for afex) */
3026 __set_bit(BNX2X_Q_FLG_FORCE_DEFAULT_PRI, &flags);
3029 if (!fp->disable_tpa) {
3030 __set_bit(BNX2X_Q_FLG_TPA, &flags);
3031 __set_bit(BNX2X_Q_FLG_TPA_IPV6, &flags);
3032 if (fp->mode == TPA_MODE_GRO)
3033 __set_bit(BNX2X_Q_FLG_TPA_GRO, &flags);
3037 __set_bit(BNX2X_Q_FLG_LEADING_RSS, &flags);
3038 __set_bit(BNX2X_Q_FLG_MCAST, &flags);
3041 /* Always set HW VLAN stripping */
3042 __set_bit(BNX2X_Q_FLG_VLAN, &flags);
3044 /* configure silent vlan removal */
3046 __set_bit(BNX2X_Q_FLG_SILENT_VLAN_REM, &flags);
3048 return flags | bnx2x_get_common_flags(bp, fp, true);
3051 static void bnx2x_pf_q_prep_general(struct bnx2x *bp,
3052 struct bnx2x_fastpath *fp, struct bnx2x_general_setup_params *gen_init,
3055 gen_init->stat_id = bnx2x_stats_id(fp);
3056 gen_init->spcl_id = fp->cl_id;
3058 /* Always use mini-jumbo MTU for FCoE L2 ring */
3060 gen_init->mtu = BNX2X_FCOE_MINI_JUMBO_MTU;
3062 gen_init->mtu = bp->dev->mtu;
3064 gen_init->cos = cos;
3067 static void bnx2x_pf_rx_q_prep(struct bnx2x *bp,
3068 struct bnx2x_fastpath *fp, struct rxq_pause_params *pause,
3069 struct bnx2x_rxq_setup_params *rxq_init)
3073 u16 tpa_agg_size = 0;
3075 if (!fp->disable_tpa) {
3076 pause->sge_th_lo = SGE_TH_LO(bp);
3077 pause->sge_th_hi = SGE_TH_HI(bp);
3079 /* validate SGE ring has enough to cross high threshold */
3080 WARN_ON(bp->dropless_fc &&
3081 pause->sge_th_hi + FW_PREFETCH_CNT >
3082 MAX_RX_SGE_CNT * NUM_RX_SGE_PAGES);
3084 tpa_agg_size = TPA_AGG_SIZE;
3085 max_sge = SGE_PAGE_ALIGN(bp->dev->mtu) >>
3087 max_sge = ((max_sge + PAGES_PER_SGE - 1) &
3088 (~(PAGES_PER_SGE-1))) >> PAGES_PER_SGE_SHIFT;
3089 sge_sz = (u16)min_t(u32, SGE_PAGES, 0xffff);
3092 /* pause - not for e1 */
3093 if (!CHIP_IS_E1(bp)) {
3094 pause->bd_th_lo = BD_TH_LO(bp);
3095 pause->bd_th_hi = BD_TH_HI(bp);
3097 pause->rcq_th_lo = RCQ_TH_LO(bp);
3098 pause->rcq_th_hi = RCQ_TH_HI(bp);
3100 * validate that rings have enough entries to cross
3103 WARN_ON(bp->dropless_fc &&
3104 pause->bd_th_hi + FW_PREFETCH_CNT >
3106 WARN_ON(bp->dropless_fc &&
3107 pause->rcq_th_hi + FW_PREFETCH_CNT >
3108 NUM_RCQ_RINGS * MAX_RCQ_DESC_CNT);
3114 rxq_init->dscr_map = fp->rx_desc_mapping;
3115 rxq_init->sge_map = fp->rx_sge_mapping;
3116 rxq_init->rcq_map = fp->rx_comp_mapping;
3117 rxq_init->rcq_np_map = fp->rx_comp_mapping + BCM_PAGE_SIZE;
3119 /* This should be a maximum number of data bytes that may be
3120 * placed on the BD (not including paddings).
3122 rxq_init->buf_sz = fp->rx_buf_size - BNX2X_FW_RX_ALIGN_START -
3123 BNX2X_FW_RX_ALIGN_END - IP_HEADER_ALIGNMENT_PADDING;
3125 rxq_init->cl_qzone_id = fp->cl_qzone_id;
3126 rxq_init->tpa_agg_sz = tpa_agg_size;
3127 rxq_init->sge_buf_sz = sge_sz;
3128 rxq_init->max_sges_pkt = max_sge;
3129 rxq_init->rss_engine_id = BP_FUNC(bp);
3130 rxq_init->mcast_engine_id = BP_FUNC(bp);
3132 /* Maximum number or simultaneous TPA aggregation for this Queue.
3134 * For PF Clients it should be the maximum available number.
3135 * VF driver(s) may want to define it to a smaller value.
3137 rxq_init->max_tpa_queues = MAX_AGG_QS(bp);
3139 rxq_init->cache_line_log = BNX2X_RX_ALIGN_SHIFT;
3140 rxq_init->fw_sb_id = fp->fw_sb_id;
3143 rxq_init->sb_cq_index = HC_SP_INDEX_ETH_FCOE_RX_CQ_CONS;
3145 rxq_init->sb_cq_index = HC_INDEX_ETH_RX_CQ_CONS;
3146 /* configure silent vlan removal
3147 * if multi function mode is afex, then mask default vlan
3149 if (IS_MF_AFEX(bp)) {
3150 rxq_init->silent_removal_value = bp->afex_def_vlan_tag;
3151 rxq_init->silent_removal_mask = VLAN_VID_MASK;
3155 static void bnx2x_pf_tx_q_prep(struct bnx2x *bp,
3156 struct bnx2x_fastpath *fp, struct bnx2x_txq_setup_params *txq_init,
3159 txq_init->dscr_map = fp->txdata_ptr[cos]->tx_desc_mapping;
3160 txq_init->sb_cq_index = HC_INDEX_ETH_FIRST_TX_CQ_CONS + cos;
3161 txq_init->traffic_type = LLFC_TRAFFIC_TYPE_NW;
3162 txq_init->fw_sb_id = fp->fw_sb_id;
3165 * set the tss leading client id for TX classification ==
3166 * leading RSS client id
3168 txq_init->tss_leading_cl_id = bnx2x_fp(bp, 0, cl_id);
3170 if (IS_FCOE_FP(fp)) {
3171 txq_init->sb_cq_index = HC_SP_INDEX_ETH_FCOE_TX_CQ_CONS;
3172 txq_init->traffic_type = LLFC_TRAFFIC_TYPE_FCOE;
3176 static void bnx2x_pf_init(struct bnx2x *bp)
3178 struct bnx2x_func_init_params func_init = {0};
3179 struct event_ring_data eq_data = { {0} };
3182 if (!CHIP_IS_E1x(bp)) {
3183 /* reset IGU PF statistics: MSIX + ATTN */
3185 REG_WR(bp, IGU_REG_STATISTIC_NUM_MESSAGE_SENT +
3186 BNX2X_IGU_STAS_MSG_VF_CNT*4 +
3187 (CHIP_MODE_IS_4_PORT(bp) ?
3188 BP_FUNC(bp) : BP_VN(bp))*4, 0);
3190 REG_WR(bp, IGU_REG_STATISTIC_NUM_MESSAGE_SENT +
3191 BNX2X_IGU_STAS_MSG_VF_CNT*4 +
3192 BNX2X_IGU_STAS_MSG_PF_CNT*4 +
3193 (CHIP_MODE_IS_4_PORT(bp) ?
3194 BP_FUNC(bp) : BP_VN(bp))*4, 0);
3197 /* function setup flags */
3198 flags = (FUNC_FLG_STATS | FUNC_FLG_LEADING | FUNC_FLG_SPQ);
3200 /* This flag is relevant for E1x only.
3201 * E2 doesn't have a TPA configuration in a function level.
3203 flags |= (bp->flags & TPA_ENABLE_FLAG) ? FUNC_FLG_TPA : 0;
3205 func_init.func_flgs = flags;
3206 func_init.pf_id = BP_FUNC(bp);
3207 func_init.func_id = BP_FUNC(bp);
3208 func_init.spq_map = bp->spq_mapping;
3209 func_init.spq_prod = bp->spq_prod_idx;
3211 bnx2x_func_init(bp, &func_init);
3213 memset(&(bp->cmng), 0, sizeof(struct cmng_struct_per_port));
3216 * Congestion management values depend on the link rate
3217 * There is no active link so initial link rate is set to 10 Gbps.
3218 * When the link comes up The congestion management values are
3219 * re-calculated according to the actual link rate.
3221 bp->link_vars.line_speed = SPEED_10000;
3222 bnx2x_cmng_fns_init(bp, true, bnx2x_get_cmng_fns_mode(bp));
3224 /* Only the PMF sets the HW */
3226 storm_memset_cmng(bp, &bp->cmng, BP_PORT(bp));
3228 /* init Event Queue - PCI bus guarantees correct endianity*/
3229 eq_data.base_addr.hi = U64_HI(bp->eq_mapping);
3230 eq_data.base_addr.lo = U64_LO(bp->eq_mapping);
3231 eq_data.producer = bp->eq_prod;
3232 eq_data.index_id = HC_SP_INDEX_EQ_CONS;
3233 eq_data.sb_id = DEF_SB_ID;
3234 storm_memset_eq_data(bp, &eq_data, BP_FUNC(bp));
3237 static void bnx2x_e1h_disable(struct bnx2x *bp)
3239 int port = BP_PORT(bp);
3241 bnx2x_tx_disable(bp);
3243 REG_WR(bp, NIG_REG_LLH0_FUNC_EN + port*8, 0);
3246 static void bnx2x_e1h_enable(struct bnx2x *bp)
3248 int port = BP_PORT(bp);
3250 REG_WR(bp, NIG_REG_LLH0_FUNC_EN + port*8, 1);
3252 /* Tx queue should be only re-enabled */
3253 netif_tx_wake_all_queues(bp->dev);
3256 * Should not call netif_carrier_on since it will be called if the link
3257 * is up when checking for link state
3261 #define DRV_INFO_ETH_STAT_NUM_MACS_REQUIRED 3
3263 static void bnx2x_drv_info_ether_stat(struct bnx2x *bp)
3265 struct eth_stats_info *ether_stat =
3266 &bp->slowpath->drv_info_to_mcp.ether_stat;
3267 struct bnx2x_vlan_mac_obj *mac_obj =
3268 &bp->sp_objs->mac_obj;
3271 strlcpy(ether_stat->version, DRV_MODULE_VERSION,
3272 ETH_STAT_INFO_VERSION_LEN);
3274 /* get DRV_INFO_ETH_STAT_NUM_MACS_REQUIRED macs, placing them in the
3275 * mac_local field in ether_stat struct. The base address is offset by 2
3276 * bytes to account for the field being 8 bytes but a mac address is
3277 * only 6 bytes. Likewise, the stride for the get_n_elements function is
3278 * 2 bytes to compensate from the 6 bytes of a mac to the 8 bytes
3279 * allocated by the ether_stat struct, so the macs will land in their
3282 for (i = 0; i < DRV_INFO_ETH_STAT_NUM_MACS_REQUIRED; i++)
3283 memset(ether_stat->mac_local + i, 0,
3284 sizeof(ether_stat->mac_local[0]));
3285 mac_obj->get_n_elements(bp, &bp->sp_objs[0].mac_obj,
3286 DRV_INFO_ETH_STAT_NUM_MACS_REQUIRED,
3287 ether_stat->mac_local + MAC_PAD, MAC_PAD,
3289 ether_stat->mtu_size = bp->dev->mtu;
3290 if (bp->dev->features & NETIF_F_RXCSUM)
3291 ether_stat->feature_flags |= FEATURE_ETH_CHKSUM_OFFLOAD_MASK;
3292 if (bp->dev->features & NETIF_F_TSO)
3293 ether_stat->feature_flags |= FEATURE_ETH_LSO_MASK;
3294 ether_stat->feature_flags |= bp->common.boot_mode;
3296 ether_stat->promiscuous_mode = (bp->dev->flags & IFF_PROMISC) ? 1 : 0;
3298 ether_stat->txq_size = bp->tx_ring_size;
3299 ether_stat->rxq_size = bp->rx_ring_size;
3302 static void bnx2x_drv_info_fcoe_stat(struct bnx2x *bp)
3304 struct bnx2x_dcbx_app_params *app = &bp->dcbx_port_params.app;
3305 struct fcoe_stats_info *fcoe_stat =
3306 &bp->slowpath->drv_info_to_mcp.fcoe_stat;
3308 if (!CNIC_LOADED(bp))
3311 memcpy(fcoe_stat->mac_local + MAC_PAD, bp->fip_mac, ETH_ALEN);
3313 fcoe_stat->qos_priority =
3314 app->traffic_type_priority[LLFC_TRAFFIC_TYPE_FCOE];
3316 /* insert FCoE stats from ramrod response */
3318 struct tstorm_per_queue_stats *fcoe_q_tstorm_stats =
3319 &bp->fw_stats_data->queue_stats[FCOE_IDX(bp)].
3320 tstorm_queue_statistics;
3322 struct xstorm_per_queue_stats *fcoe_q_xstorm_stats =
3323 &bp->fw_stats_data->queue_stats[FCOE_IDX(bp)].
3324 xstorm_queue_statistics;
3326 struct fcoe_statistics_params *fw_fcoe_stat =
3327 &bp->fw_stats_data->fcoe;
3329 ADD_64_LE(fcoe_stat->rx_bytes_hi, LE32_0,
3330 fcoe_stat->rx_bytes_lo,
3331 fw_fcoe_stat->rx_stat0.fcoe_rx_byte_cnt);
3333 ADD_64_LE(fcoe_stat->rx_bytes_hi,
3334 fcoe_q_tstorm_stats->rcv_ucast_bytes.hi,
3335 fcoe_stat->rx_bytes_lo,
3336 fcoe_q_tstorm_stats->rcv_ucast_bytes.lo);
3338 ADD_64_LE(fcoe_stat->rx_bytes_hi,
3339 fcoe_q_tstorm_stats->rcv_bcast_bytes.hi,
3340 fcoe_stat->rx_bytes_lo,
3341 fcoe_q_tstorm_stats->rcv_bcast_bytes.lo);
3343 ADD_64_LE(fcoe_stat->rx_bytes_hi,
3344 fcoe_q_tstorm_stats->rcv_mcast_bytes.hi,
3345 fcoe_stat->rx_bytes_lo,
3346 fcoe_q_tstorm_stats->rcv_mcast_bytes.lo);
3348 ADD_64_LE(fcoe_stat->rx_frames_hi, LE32_0,
3349 fcoe_stat->rx_frames_lo,
3350 fw_fcoe_stat->rx_stat0.fcoe_rx_pkt_cnt);
3352 ADD_64_LE(fcoe_stat->rx_frames_hi, LE32_0,
3353 fcoe_stat->rx_frames_lo,
3354 fcoe_q_tstorm_stats->rcv_ucast_pkts);
3356 ADD_64_LE(fcoe_stat->rx_frames_hi, LE32_0,
3357 fcoe_stat->rx_frames_lo,
3358 fcoe_q_tstorm_stats->rcv_bcast_pkts);
3360 ADD_64_LE(fcoe_stat->rx_frames_hi, LE32_0,
3361 fcoe_stat->rx_frames_lo,
3362 fcoe_q_tstorm_stats->rcv_mcast_pkts);
3364 ADD_64_LE(fcoe_stat->tx_bytes_hi, LE32_0,
3365 fcoe_stat->tx_bytes_lo,
3366 fw_fcoe_stat->tx_stat.fcoe_tx_byte_cnt);
3368 ADD_64_LE(fcoe_stat->tx_bytes_hi,
3369 fcoe_q_xstorm_stats->ucast_bytes_sent.hi,
3370 fcoe_stat->tx_bytes_lo,
3371 fcoe_q_xstorm_stats->ucast_bytes_sent.lo);
3373 ADD_64_LE(fcoe_stat->tx_bytes_hi,
3374 fcoe_q_xstorm_stats->bcast_bytes_sent.hi,
3375 fcoe_stat->tx_bytes_lo,
3376 fcoe_q_xstorm_stats->bcast_bytes_sent.lo);
3378 ADD_64_LE(fcoe_stat->tx_bytes_hi,
3379 fcoe_q_xstorm_stats->mcast_bytes_sent.hi,
3380 fcoe_stat->tx_bytes_lo,
3381 fcoe_q_xstorm_stats->mcast_bytes_sent.lo);
3383 ADD_64_LE(fcoe_stat->tx_frames_hi, LE32_0,
3384 fcoe_stat->tx_frames_lo,
3385 fw_fcoe_stat->tx_stat.fcoe_tx_pkt_cnt);
3387 ADD_64_LE(fcoe_stat->tx_frames_hi, LE32_0,
3388 fcoe_stat->tx_frames_lo,
3389 fcoe_q_xstorm_stats->ucast_pkts_sent);
3391 ADD_64_LE(fcoe_stat->tx_frames_hi, LE32_0,
3392 fcoe_stat->tx_frames_lo,
3393 fcoe_q_xstorm_stats->bcast_pkts_sent);
3395 ADD_64_LE(fcoe_stat->tx_frames_hi, LE32_0,
3396 fcoe_stat->tx_frames_lo,
3397 fcoe_q_xstorm_stats->mcast_pkts_sent);
3400 /* ask L5 driver to add data to the struct */
3401 bnx2x_cnic_notify(bp, CNIC_CTL_FCOE_STATS_GET_CMD);
3404 static void bnx2x_drv_info_iscsi_stat(struct bnx2x *bp)
3406 struct bnx2x_dcbx_app_params *app = &bp->dcbx_port_params.app;
3407 struct iscsi_stats_info *iscsi_stat =
3408 &bp->slowpath->drv_info_to_mcp.iscsi_stat;
3410 if (!CNIC_LOADED(bp))
3413 memcpy(iscsi_stat->mac_local + MAC_PAD, bp->cnic_eth_dev.iscsi_mac,
3416 iscsi_stat->qos_priority =
3417 app->traffic_type_priority[LLFC_TRAFFIC_TYPE_ISCSI];
3419 /* ask L5 driver to add data to the struct */
3420 bnx2x_cnic_notify(bp, CNIC_CTL_ISCSI_STATS_GET_CMD);
3423 /* called due to MCP event (on pmf):
3424 * reread new bandwidth configuration
3426 * notify others function about the change
3428 static void bnx2x_config_mf_bw(struct bnx2x *bp)
3430 if (bp->link_vars.link_up) {
3431 bnx2x_cmng_fns_init(bp, true, CMNG_FNS_MINMAX);
3432 bnx2x_link_sync_notify(bp);
3434 storm_memset_cmng(bp, &bp->cmng, BP_PORT(bp));
3437 static void bnx2x_set_mf_bw(struct bnx2x *bp)
3439 bnx2x_config_mf_bw(bp);
3440 bnx2x_fw_command(bp, DRV_MSG_CODE_SET_MF_BW_ACK, 0);
3443 static void bnx2x_handle_eee_event(struct bnx2x *bp)
3445 DP(BNX2X_MSG_MCP, "EEE - LLDP event\n");
3446 bnx2x_fw_command(bp, DRV_MSG_CODE_EEE_RESULTS_ACK, 0);
3449 static void bnx2x_handle_drv_info_req(struct bnx2x *bp)
3451 enum drv_info_opcode op_code;
3452 u32 drv_info_ctl = SHMEM2_RD(bp, drv_info_control);
3454 /* if drv_info version supported by MFW doesn't match - send NACK */
3455 if ((drv_info_ctl & DRV_INFO_CONTROL_VER_MASK) != DRV_INFO_CUR_VER) {
3456 bnx2x_fw_command(bp, DRV_MSG_CODE_DRV_INFO_NACK, 0);
3460 op_code = (drv_info_ctl & DRV_INFO_CONTROL_OP_CODE_MASK) >>
3461 DRV_INFO_CONTROL_OP_CODE_SHIFT;
3463 memset(&bp->slowpath->drv_info_to_mcp, 0,
3464 sizeof(union drv_info_to_mcp));
3467 case ETH_STATS_OPCODE:
3468 bnx2x_drv_info_ether_stat(bp);
3470 case FCOE_STATS_OPCODE:
3471 bnx2x_drv_info_fcoe_stat(bp);
3473 case ISCSI_STATS_OPCODE:
3474 bnx2x_drv_info_iscsi_stat(bp);
3477 /* if op code isn't supported - send NACK */
3478 bnx2x_fw_command(bp, DRV_MSG_CODE_DRV_INFO_NACK, 0);
3482 /* if we got drv_info attn from MFW then these fields are defined in
3485 SHMEM2_WR(bp, drv_info_host_addr_lo,
3486 U64_LO(bnx2x_sp_mapping(bp, drv_info_to_mcp)));
3487 SHMEM2_WR(bp, drv_info_host_addr_hi,
3488 U64_HI(bnx2x_sp_mapping(bp, drv_info_to_mcp)));
3490 bnx2x_fw_command(bp, DRV_MSG_CODE_DRV_INFO_ACK, 0);
3493 static void bnx2x_dcc_event(struct bnx2x *bp, u32 dcc_event)
3495 DP(BNX2X_MSG_MCP, "dcc_event 0x%x\n", dcc_event);
3497 if (dcc_event & DRV_STATUS_DCC_DISABLE_ENABLE_PF) {
3500 * This is the only place besides the function initialization
3501 * where the bp->flags can change so it is done without any
3504 if (bp->mf_config[BP_VN(bp)] & FUNC_MF_CFG_FUNC_DISABLED) {
3505 DP(BNX2X_MSG_MCP, "mf_cfg function disabled\n");
3506 bp->flags |= MF_FUNC_DIS;
3508 bnx2x_e1h_disable(bp);
3510 DP(BNX2X_MSG_MCP, "mf_cfg function enabled\n");
3511 bp->flags &= ~MF_FUNC_DIS;
3513 bnx2x_e1h_enable(bp);
3515 dcc_event &= ~DRV_STATUS_DCC_DISABLE_ENABLE_PF;
3517 if (dcc_event & DRV_STATUS_DCC_BANDWIDTH_ALLOCATION) {
3518 bnx2x_config_mf_bw(bp);
3519 dcc_event &= ~DRV_STATUS_DCC_BANDWIDTH_ALLOCATION;
3522 /* Report results to MCP */
3524 bnx2x_fw_command(bp, DRV_MSG_CODE_DCC_FAILURE, 0);
3526 bnx2x_fw_command(bp, DRV_MSG_CODE_DCC_OK, 0);
3529 /* must be called under the spq lock */
3530 static struct eth_spe *bnx2x_sp_get_next(struct bnx2x *bp)
3532 struct eth_spe *next_spe = bp->spq_prod_bd;
3534 if (bp->spq_prod_bd == bp->spq_last_bd) {
3535 bp->spq_prod_bd = bp->spq;
3536 bp->spq_prod_idx = 0;
3537 DP(BNX2X_MSG_SP, "end of spq\n");
3545 /* must be called under the spq lock */
3546 static void bnx2x_sp_prod_update(struct bnx2x *bp)
3548 int func = BP_FUNC(bp);
3551 * Make sure that BD data is updated before writing the producer:
3552 * BD data is written to the memory, the producer is read from the
3553 * memory, thus we need a full memory barrier to ensure the ordering.
3557 REG_WR16(bp, BAR_XSTRORM_INTMEM + XSTORM_SPQ_PROD_OFFSET(func),
3563 * bnx2x_is_contextless_ramrod - check if the current command ends on EQ
3565 * @cmd: command to check
3566 * @cmd_type: command type
3568 static bool bnx2x_is_contextless_ramrod(int cmd, int cmd_type)
3570 if ((cmd_type == NONE_CONNECTION_TYPE) ||
3571 (cmd == RAMROD_CMD_ID_ETH_FORWARD_SETUP) ||
3572 (cmd == RAMROD_CMD_ID_ETH_CLASSIFICATION_RULES) ||
3573 (cmd == RAMROD_CMD_ID_ETH_FILTER_RULES) ||
3574 (cmd == RAMROD_CMD_ID_ETH_MULTICAST_RULES) ||
3575 (cmd == RAMROD_CMD_ID_ETH_SET_MAC) ||
3576 (cmd == RAMROD_CMD_ID_ETH_RSS_UPDATE))
3583 * bnx2x_sp_post - place a single command on an SP ring
3585 * @bp: driver handle
3586 * @command: command to place (e.g. SETUP, FILTER_RULES, etc.)
3587 * @cid: SW CID the command is related to
3588 * @data_hi: command private data address (high 32 bits)
3589 * @data_lo: command private data address (low 32 bits)
3590 * @cmd_type: command type (e.g. NONE, ETH)
3592 * SP data is handled as if it's always an address pair, thus data fields are
3593 * not swapped to little endian in upper functions. Instead this function swaps
3594 * data as if it's two u32 fields.
3596 int bnx2x_sp_post(struct bnx2x *bp, int command, int cid,
3597 u32 data_hi, u32 data_lo, int cmd_type)
3599 struct eth_spe *spe;
3601 bool common = bnx2x_is_contextless_ramrod(command, cmd_type);
3603 #ifdef BNX2X_STOP_ON_ERROR
3604 if (unlikely(bp->panic)) {
3605 BNX2X_ERR("Can't post SP when there is panic\n");
3610 spin_lock_bh(&bp->spq_lock);
3613 if (!atomic_read(&bp->eq_spq_left)) {
3614 BNX2X_ERR("BUG! EQ ring full!\n");
3615 spin_unlock_bh(&bp->spq_lock);
3619 } else if (!atomic_read(&bp->cq_spq_left)) {
3620 BNX2X_ERR("BUG! SPQ ring full!\n");
3621 spin_unlock_bh(&bp->spq_lock);
3626 spe = bnx2x_sp_get_next(bp);
3628 /* CID needs port number to be encoded int it */
3629 spe->hdr.conn_and_cmd_data =
3630 cpu_to_le32((command << SPE_HDR_CMD_ID_SHIFT) |
3633 type = (cmd_type << SPE_HDR_CONN_TYPE_SHIFT) & SPE_HDR_CONN_TYPE;
3635 type |= ((BP_FUNC(bp) << SPE_HDR_FUNCTION_ID_SHIFT) &
3636 SPE_HDR_FUNCTION_ID);
3638 spe->hdr.type = cpu_to_le16(type);
3640 spe->data.update_data_addr.hi = cpu_to_le32(data_hi);
3641 spe->data.update_data_addr.lo = cpu_to_le32(data_lo);
3644 * It's ok if the actual decrement is issued towards the memory
3645 * somewhere between the spin_lock and spin_unlock. Thus no
3646 * more explicit memory barrier is needed.
3649 atomic_dec(&bp->eq_spq_left);
3651 atomic_dec(&bp->cq_spq_left);
3654 "SPQE[%x] (%x:%x) (cmd, common?) (%d,%d) hw_cid %x data (%x:%x) type(0x%x) left (CQ, EQ) (%x,%x)\n",
3655 bp->spq_prod_idx, (u32)U64_HI(bp->spq_mapping),
3656 (u32)(U64_LO(bp->spq_mapping) +
3657 (void *)bp->spq_prod_bd - (void *)bp->spq), command, common,
3658 HW_CID(bp, cid), data_hi, data_lo, type,
3659 atomic_read(&bp->cq_spq_left), atomic_read(&bp->eq_spq_left));
3661 bnx2x_sp_prod_update(bp);
3662 spin_unlock_bh(&bp->spq_lock);
3666 /* acquire split MCP access lock register */
3667 static int bnx2x_acquire_alr(struct bnx2x *bp)
3673 for (j = 0; j < 1000; j++) {
3674 REG_WR(bp, MCP_REG_MCPR_ACCESS_LOCK, MCPR_ACCESS_LOCK_LOCK);
3675 val = REG_RD(bp, MCP_REG_MCPR_ACCESS_LOCK);
3676 if (val & MCPR_ACCESS_LOCK_LOCK)
3679 usleep_range(5000, 10000);
3681 if (!(val & MCPR_ACCESS_LOCK_LOCK)) {
3682 BNX2X_ERR("Cannot acquire MCP access lock register\n");
3689 /* release split MCP access lock register */
3690 static void bnx2x_release_alr(struct bnx2x *bp)
3692 REG_WR(bp, MCP_REG_MCPR_ACCESS_LOCK, 0);
3695 #define BNX2X_DEF_SB_ATT_IDX 0x0001
3696 #define BNX2X_DEF_SB_IDX 0x0002
3698 static u16 bnx2x_update_dsb_idx(struct bnx2x *bp)
3700 struct host_sp_status_block *def_sb = bp->def_status_blk;
3703 barrier(); /* status block is written to by the chip */
3704 if (bp->def_att_idx != def_sb->atten_status_block.attn_bits_index) {
3705 bp->def_att_idx = def_sb->atten_status_block.attn_bits_index;
3706 rc |= BNX2X_DEF_SB_ATT_IDX;
3709 if (bp->def_idx != def_sb->sp_sb.running_index) {
3710 bp->def_idx = def_sb->sp_sb.running_index;
3711 rc |= BNX2X_DEF_SB_IDX;
3714 /* Do not reorder: indices reading should complete before handling */
3720 * slow path service functions
3723 static void bnx2x_attn_int_asserted(struct bnx2x *bp, u32 asserted)
3725 int port = BP_PORT(bp);
3726 u32 aeu_addr = port ? MISC_REG_AEU_MASK_ATTN_FUNC_1 :
3727 MISC_REG_AEU_MASK_ATTN_FUNC_0;
3728 u32 nig_int_mask_addr = port ? NIG_REG_MASK_INTERRUPT_PORT1 :
3729 NIG_REG_MASK_INTERRUPT_PORT0;
3734 if (bp->attn_state & asserted)
3735 BNX2X_ERR("IGU ERROR\n");
3737 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_PORT0_ATT_MASK + port);
3738 aeu_mask = REG_RD(bp, aeu_addr);
3740 DP(NETIF_MSG_HW, "aeu_mask %x newly asserted %x\n",
3741 aeu_mask, asserted);
3742 aeu_mask &= ~(asserted & 0x3ff);
3743 DP(NETIF_MSG_HW, "new mask %x\n", aeu_mask);
3745 REG_WR(bp, aeu_addr, aeu_mask);
3746 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_PORT0_ATT_MASK + port);
3748 DP(NETIF_MSG_HW, "attn_state %x\n", bp->attn_state);
3749 bp->attn_state |= asserted;
3750 DP(NETIF_MSG_HW, "new state %x\n", bp->attn_state);
3752 if (asserted & ATTN_HARD_WIRED_MASK) {
3753 if (asserted & ATTN_NIG_FOR_FUNC) {
3755 bnx2x_acquire_phy_lock(bp);
3757 /* save nig interrupt mask */
3758 nig_mask = REG_RD(bp, nig_int_mask_addr);
3760 /* If nig_mask is not set, no need to call the update
3764 REG_WR(bp, nig_int_mask_addr, 0);
3766 bnx2x_link_attn(bp);
3769 /* handle unicore attn? */
3771 if (asserted & ATTN_SW_TIMER_4_FUNC)
3772 DP(NETIF_MSG_HW, "ATTN_SW_TIMER_4_FUNC!\n");
3774 if (asserted & GPIO_2_FUNC)
3775 DP(NETIF_MSG_HW, "GPIO_2_FUNC!\n");
3777 if (asserted & GPIO_3_FUNC)
3778 DP(NETIF_MSG_HW, "GPIO_3_FUNC!\n");
3780 if (asserted & GPIO_4_FUNC)
3781 DP(NETIF_MSG_HW, "GPIO_4_FUNC!\n");
3784 if (asserted & ATTN_GENERAL_ATTN_1) {
3785 DP(NETIF_MSG_HW, "ATTN_GENERAL_ATTN_1!\n");
3786 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_1, 0x0);
3788 if (asserted & ATTN_GENERAL_ATTN_2) {
3789 DP(NETIF_MSG_HW, "ATTN_GENERAL_ATTN_2!\n");
3790 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_2, 0x0);
3792 if (asserted & ATTN_GENERAL_ATTN_3) {
3793 DP(NETIF_MSG_HW, "ATTN_GENERAL_ATTN_3!\n");
3794 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_3, 0x0);
3797 if (asserted & ATTN_GENERAL_ATTN_4) {
3798 DP(NETIF_MSG_HW, "ATTN_GENERAL_ATTN_4!\n");
3799 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_4, 0x0);
3801 if (asserted & ATTN_GENERAL_ATTN_5) {
3802 DP(NETIF_MSG_HW, "ATTN_GENERAL_ATTN_5!\n");
3803 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_5, 0x0);
3805 if (asserted & ATTN_GENERAL_ATTN_6) {
3806 DP(NETIF_MSG_HW, "ATTN_GENERAL_ATTN_6!\n");
3807 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_6, 0x0);
3811 } /* if hardwired */
3813 if (bp->common.int_block == INT_BLOCK_HC)
3814 reg_addr = (HC_REG_COMMAND_REG + port*32 +
3815 COMMAND_REG_ATTN_BITS_SET);
3817 reg_addr = (BAR_IGU_INTMEM + IGU_CMD_ATTN_BIT_SET_UPPER*8);
3819 DP(NETIF_MSG_HW, "about to mask 0x%08x at %s addr 0x%x\n", asserted,
3820 (bp->common.int_block == INT_BLOCK_HC) ? "HC" : "IGU", reg_addr);
3821 REG_WR(bp, reg_addr, asserted);
3823 /* now set back the mask */
3824 if (asserted & ATTN_NIG_FOR_FUNC) {
3825 /* Verify that IGU ack through BAR was written before restoring
3826 * NIG mask. This loop should exit after 2-3 iterations max.
3828 if (bp->common.int_block != INT_BLOCK_HC) {
3829 u32 cnt = 0, igu_acked;
3831 igu_acked = REG_RD(bp,
3832 IGU_REG_ATTENTION_ACK_BITS);
3833 } while (((igu_acked & ATTN_NIG_FOR_FUNC) == 0) &&
3834 (++cnt < MAX_IGU_ATTN_ACK_TO));
3837 "Failed to verify IGU ack on time\n");
3840 REG_WR(bp, nig_int_mask_addr, nig_mask);
3841 bnx2x_release_phy_lock(bp);
3845 static void bnx2x_fan_failure(struct bnx2x *bp)
3847 int port = BP_PORT(bp);
3849 /* mark the failure */
3852 dev_info.port_hw_config[port].external_phy_config);
3854 ext_phy_config &= ~PORT_HW_CFG_XGXS_EXT_PHY_TYPE_MASK;
3855 ext_phy_config |= PORT_HW_CFG_XGXS_EXT_PHY_TYPE_FAILURE;
3856 SHMEM_WR(bp, dev_info.port_hw_config[port].external_phy_config,
3859 /* log the failure */
3860 netdev_err(bp->dev, "Fan Failure on Network Controller has caused the driver to shutdown the card to prevent permanent damage.\n"
3861 "Please contact OEM Support for assistance\n");
3863 /* Schedule device reset (unload)
3864 * This is due to some boards consuming sufficient power when driver is
3865 * up to overheat if fan fails.
3867 smp_mb__before_clear_bit();
3868 set_bit(BNX2X_SP_RTNL_FAN_FAILURE, &bp->sp_rtnl_state);
3869 smp_mb__after_clear_bit();
3870 schedule_delayed_work(&bp->sp_rtnl_task, 0);
3873 static void bnx2x_attn_int_deasserted0(struct bnx2x *bp, u32 attn)
3875 int port = BP_PORT(bp);
3879 reg_offset = (port ? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_0 :
3880 MISC_REG_AEU_ENABLE1_FUNC_0_OUT_0);
3882 if (attn & AEU_INPUTS_ATTN_BITS_SPIO5) {
3884 val = REG_RD(bp, reg_offset);
3885 val &= ~AEU_INPUTS_ATTN_BITS_SPIO5;
3886 REG_WR(bp, reg_offset, val);
3888 BNX2X_ERR("SPIO5 hw attention\n");
3890 /* Fan failure attention */
3891 bnx2x_hw_reset_phy(&bp->link_params);
3892 bnx2x_fan_failure(bp);
3895 if ((attn & bp->link_vars.aeu_int_mask) && bp->port.pmf) {
3896 bnx2x_acquire_phy_lock(bp);
3897 bnx2x_handle_module_detect_int(&bp->link_params);
3898 bnx2x_release_phy_lock(bp);
3901 if (attn & HW_INTERRUT_ASSERT_SET_0) {
3903 val = REG_RD(bp, reg_offset);
3904 val &= ~(attn & HW_INTERRUT_ASSERT_SET_0);
3905 REG_WR(bp, reg_offset, val);
3907 BNX2X_ERR("FATAL HW block attention set0 0x%x\n",
3908 (u32)(attn & HW_INTERRUT_ASSERT_SET_0));
3913 static void bnx2x_attn_int_deasserted1(struct bnx2x *bp, u32 attn)
3917 if (attn & AEU_INPUTS_ATTN_BITS_DOORBELLQ_HW_INTERRUPT) {
3919 val = REG_RD(bp, DORQ_REG_DORQ_INT_STS_CLR);
3920 BNX2X_ERR("DB hw attention 0x%x\n", val);
3921 /* DORQ discard attention */
3923 BNX2X_ERR("FATAL error from DORQ\n");
3926 if (attn & HW_INTERRUT_ASSERT_SET_1) {
3928 int port = BP_PORT(bp);
3931 reg_offset = (port ? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_1 :
3932 MISC_REG_AEU_ENABLE1_FUNC_0_OUT_1);
3934 val = REG_RD(bp, reg_offset);
3935 val &= ~(attn & HW_INTERRUT_ASSERT_SET_1);
3936 REG_WR(bp, reg_offset, val);
3938 BNX2X_ERR("FATAL HW block attention set1 0x%x\n",
3939 (u32)(attn & HW_INTERRUT_ASSERT_SET_1));
3944 static void bnx2x_attn_int_deasserted2(struct bnx2x *bp, u32 attn)
3948 if (attn & AEU_INPUTS_ATTN_BITS_CFC_HW_INTERRUPT) {
3950 val = REG_RD(bp, CFC_REG_CFC_INT_STS_CLR);
3951 BNX2X_ERR("CFC hw attention 0x%x\n", val);
3952 /* CFC error attention */
3954 BNX2X_ERR("FATAL error from CFC\n");
3957 if (attn & AEU_INPUTS_ATTN_BITS_PXP_HW_INTERRUPT) {
3958 val = REG_RD(bp, PXP_REG_PXP_INT_STS_CLR_0);
3959 BNX2X_ERR("PXP hw attention-0 0x%x\n", val);
3960 /* RQ_USDMDP_FIFO_OVERFLOW */
3962 BNX2X_ERR("FATAL error from PXP\n");
3964 if (!CHIP_IS_E1x(bp)) {
3965 val = REG_RD(bp, PXP_REG_PXP_INT_STS_CLR_1);
3966 BNX2X_ERR("PXP hw attention-1 0x%x\n", val);
3970 if (attn & HW_INTERRUT_ASSERT_SET_2) {
3972 int port = BP_PORT(bp);
3975 reg_offset = (port ? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_2 :
3976 MISC_REG_AEU_ENABLE1_FUNC_0_OUT_2);
3978 val = REG_RD(bp, reg_offset);
3979 val &= ~(attn & HW_INTERRUT_ASSERT_SET_2);
3980 REG_WR(bp, reg_offset, val);
3982 BNX2X_ERR("FATAL HW block attention set2 0x%x\n",
3983 (u32)(attn & HW_INTERRUT_ASSERT_SET_2));
3988 static void bnx2x_attn_int_deasserted3(struct bnx2x *bp, u32 attn)
3992 if (attn & EVEREST_GEN_ATTN_IN_USE_MASK) {
3994 if (attn & BNX2X_PMF_LINK_ASSERT) {
3995 int func = BP_FUNC(bp);
3997 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_12 + func*4, 0);
3998 bnx2x_read_mf_cfg(bp);
3999 bp->mf_config[BP_VN(bp)] = MF_CFG_RD(bp,
4000 func_mf_config[BP_ABS_FUNC(bp)].config);
4002 func_mb[BP_FW_MB_IDX(bp)].drv_status);
4003 if (val & DRV_STATUS_DCC_EVENT_MASK)
4005 (val & DRV_STATUS_DCC_EVENT_MASK));
4007 if (val & DRV_STATUS_SET_MF_BW)
4008 bnx2x_set_mf_bw(bp);
4010 if (val & DRV_STATUS_DRV_INFO_REQ)
4011 bnx2x_handle_drv_info_req(bp);
4013 if (val & DRV_STATUS_VF_DISABLED)
4014 bnx2x_vf_handle_flr_event(bp);
4016 if ((bp->port.pmf == 0) && (val & DRV_STATUS_PMF))
4017 bnx2x_pmf_update(bp);
4020 (val & DRV_STATUS_DCBX_NEGOTIATION_RESULTS) &&
4021 bp->dcbx_enabled > 0)
4022 /* start dcbx state machine */
4023 bnx2x_dcbx_set_params(bp,
4024 BNX2X_DCBX_STATE_NEG_RECEIVED);
4025 if (val & DRV_STATUS_AFEX_EVENT_MASK)
4026 bnx2x_handle_afex_cmd(bp,
4027 val & DRV_STATUS_AFEX_EVENT_MASK);
4028 if (val & DRV_STATUS_EEE_NEGOTIATION_RESULTS)
4029 bnx2x_handle_eee_event(bp);
4030 if (bp->link_vars.periodic_flags &
4031 PERIODIC_FLAGS_LINK_EVENT) {
4032 /* sync with link */
4033 bnx2x_acquire_phy_lock(bp);
4034 bp->link_vars.periodic_flags &=
4035 ~PERIODIC_FLAGS_LINK_EVENT;
4036 bnx2x_release_phy_lock(bp);
4038 bnx2x_link_sync_notify(bp);
4039 bnx2x_link_report(bp);
4041 /* Always call it here: bnx2x_link_report() will
4042 * prevent the link indication duplication.
4044 bnx2x__link_status_update(bp);
4045 } else if (attn & BNX2X_MC_ASSERT_BITS) {
4047 BNX2X_ERR("MC assert!\n");
4048 bnx2x_mc_assert(bp);
4049 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_10, 0);
4050 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_9, 0);
4051 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_8, 0);
4052 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_7, 0);
4055 } else if (attn & BNX2X_MCP_ASSERT) {
4057 BNX2X_ERR("MCP assert!\n");
4058 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_11, 0);
4062 BNX2X_ERR("Unknown HW assert! (attn 0x%x)\n", attn);
4065 if (attn & EVEREST_LATCHED_ATTN_IN_USE_MASK) {
4066 BNX2X_ERR("LATCHED attention 0x%08x (masked)\n", attn);
4067 if (attn & BNX2X_GRC_TIMEOUT) {
4068 val = CHIP_IS_E1(bp) ? 0 :
4069 REG_RD(bp, MISC_REG_GRC_TIMEOUT_ATTN);
4070 BNX2X_ERR("GRC time-out 0x%08x\n", val);
4072 if (attn & BNX2X_GRC_RSV) {
4073 val = CHIP_IS_E1(bp) ? 0 :
4074 REG_RD(bp, MISC_REG_GRC_RSV_ATTN);
4075 BNX2X_ERR("GRC reserved 0x%08x\n", val);
4077 REG_WR(bp, MISC_REG_AEU_CLR_LATCH_SIGNAL, 0x7ff);
4083 * 0-7 - Engine0 load counter.
4084 * 8-15 - Engine1 load counter.
4085 * 16 - Engine0 RESET_IN_PROGRESS bit.
4086 * 17 - Engine1 RESET_IN_PROGRESS bit.
4087 * 18 - Engine0 ONE_IS_LOADED. Set when there is at least one active function
4089 * 19 - Engine1 ONE_IS_LOADED.
4090 * 20 - Chip reset flow bit. When set none-leader must wait for both engines
4091 * leader to complete (check for both RESET_IN_PROGRESS bits and not for
4092 * just the one belonging to its engine).
4095 #define BNX2X_RECOVERY_GLOB_REG MISC_REG_GENERIC_POR_1
4097 #define BNX2X_PATH0_LOAD_CNT_MASK 0x000000ff
4098 #define BNX2X_PATH0_LOAD_CNT_SHIFT 0
4099 #define BNX2X_PATH1_LOAD_CNT_MASK 0x0000ff00
4100 #define BNX2X_PATH1_LOAD_CNT_SHIFT 8
4101 #define BNX2X_PATH0_RST_IN_PROG_BIT 0x00010000
4102 #define BNX2X_PATH1_RST_IN_PROG_BIT 0x00020000
4103 #define BNX2X_GLOBAL_RESET_BIT 0x00040000
4106 * Set the GLOBAL_RESET bit.
4108 * Should be run under rtnl lock
4110 void bnx2x_set_reset_global(struct bnx2x *bp)
4113 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG);
4114 val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG);
4115 REG_WR(bp, BNX2X_RECOVERY_GLOB_REG, val | BNX2X_GLOBAL_RESET_BIT);
4116 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG);
4120 * Clear the GLOBAL_RESET bit.
4122 * Should be run under rtnl lock
4124 static void bnx2x_clear_reset_global(struct bnx2x *bp)
4127 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG);
4128 val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG);
4129 REG_WR(bp, BNX2X_RECOVERY_GLOB_REG, val & (~BNX2X_GLOBAL_RESET_BIT));
4130 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG);
4134 * Checks the GLOBAL_RESET bit.
4136 * should be run under rtnl lock
4138 static bool bnx2x_reset_is_global(struct bnx2x *bp)
4140 u32 val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG);
4142 DP(NETIF_MSG_HW, "GEN_REG_VAL=0x%08x\n", val);
4143 return (val & BNX2X_GLOBAL_RESET_BIT) ? true : false;
4147 * Clear RESET_IN_PROGRESS bit for the current engine.
4149 * Should be run under rtnl lock
4151 static void bnx2x_set_reset_done(struct bnx2x *bp)
4154 u32 bit = BP_PATH(bp) ?
4155 BNX2X_PATH1_RST_IN_PROG_BIT : BNX2X_PATH0_RST_IN_PROG_BIT;
4156 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG);
4157 val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG);
4161 REG_WR(bp, BNX2X_RECOVERY_GLOB_REG, val);
4163 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG);
4167 * Set RESET_IN_PROGRESS for the current engine.
4169 * should be run under rtnl lock
4171 void bnx2x_set_reset_in_progress(struct bnx2x *bp)
4174 u32 bit = BP_PATH(bp) ?
4175 BNX2X_PATH1_RST_IN_PROG_BIT : BNX2X_PATH0_RST_IN_PROG_BIT;
4176 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG);
4177 val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG);
4181 REG_WR(bp, BNX2X_RECOVERY_GLOB_REG, val);
4182 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG);
4186 * Checks the RESET_IN_PROGRESS bit for the given engine.
4187 * should be run under rtnl lock
4189 bool bnx2x_reset_is_done(struct bnx2x *bp, int engine)
4191 u32 val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG);
4193 BNX2X_PATH1_RST_IN_PROG_BIT : BNX2X_PATH0_RST_IN_PROG_BIT;
4195 /* return false if bit is set */
4196 return (val & bit) ? false : true;
4200 * set pf load for the current pf.
4202 * should be run under rtnl lock
4204 void bnx2x_set_pf_load(struct bnx2x *bp)
4207 u32 mask = BP_PATH(bp) ? BNX2X_PATH1_LOAD_CNT_MASK :
4208 BNX2X_PATH0_LOAD_CNT_MASK;
4209 u32 shift = BP_PATH(bp) ? BNX2X_PATH1_LOAD_CNT_SHIFT :
4210 BNX2X_PATH0_LOAD_CNT_SHIFT;
4212 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG);
4213 val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG);
4215 DP(NETIF_MSG_IFUP, "Old GEN_REG_VAL=0x%08x\n", val);
4217 /* get the current counter value */
4218 val1 = (val & mask) >> shift;
4220 /* set bit of that PF */
4221 val1 |= (1 << bp->pf_num);
4223 /* clear the old value */
4226 /* set the new one */
4227 val |= ((val1 << shift) & mask);
4229 REG_WR(bp, BNX2X_RECOVERY_GLOB_REG, val);
4230 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG);
4234 * bnx2x_clear_pf_load - clear pf load mark
4236 * @bp: driver handle
4238 * Should be run under rtnl lock.
4239 * Decrements the load counter for the current engine. Returns
4240 * whether other functions are still loaded
4242 bool bnx2x_clear_pf_load(struct bnx2x *bp)
4245 u32 mask = BP_PATH(bp) ? BNX2X_PATH1_LOAD_CNT_MASK :
4246 BNX2X_PATH0_LOAD_CNT_MASK;
4247 u32 shift = BP_PATH(bp) ? BNX2X_PATH1_LOAD_CNT_SHIFT :
4248 BNX2X_PATH0_LOAD_CNT_SHIFT;
4250 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG);
4251 val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG);
4252 DP(NETIF_MSG_IFDOWN, "Old GEN_REG_VAL=0x%08x\n", val);
4254 /* get the current counter value */
4255 val1 = (val & mask) >> shift;
4257 /* clear bit of that PF */
4258 val1 &= ~(1 << bp->pf_num);
4260 /* clear the old value */
4263 /* set the new one */
4264 val |= ((val1 << shift) & mask);
4266 REG_WR(bp, BNX2X_RECOVERY_GLOB_REG, val);
4267 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG);
4272 * Read the load status for the current engine.
4274 * should be run under rtnl lock
4276 static bool bnx2x_get_load_status(struct bnx2x *bp, int engine)
4278 u32 mask = (engine ? BNX2X_PATH1_LOAD_CNT_MASK :
4279 BNX2X_PATH0_LOAD_CNT_MASK);
4280 u32 shift = (engine ? BNX2X_PATH1_LOAD_CNT_SHIFT :
4281 BNX2X_PATH0_LOAD_CNT_SHIFT);
4282 u32 val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG);
4284 DP(NETIF_MSG_HW | NETIF_MSG_IFUP, "GLOB_REG=0x%08x\n", val);
4286 val = (val & mask) >> shift;
4288 DP(NETIF_MSG_HW | NETIF_MSG_IFUP, "load mask for engine %d = 0x%x\n",
4294 static void _print_parity(struct bnx2x *bp, u32 reg)
4296 pr_cont(" [0x%08x] ", REG_RD(bp, reg));
4299 static void _print_next_block(int idx, const char *blk)
4301 pr_cont("%s%s", idx ? ", " : "", blk);
4304 static bool bnx2x_check_blocks_with_parity0(struct bnx2x *bp, u32 sig,
4305 int *par_num, bool print)
4313 for (i = 0; sig; i++) {
4314 cur_bit = (0x1UL << i);
4315 if (sig & cur_bit) {
4316 res |= true; /* Each bit is real error! */
4320 case AEU_INPUTS_ATTN_BITS_BRB_PARITY_ERROR:
4321 _print_next_block((*par_num)++, "BRB");
4323 BRB1_REG_BRB1_PRTY_STS);
4325 case AEU_INPUTS_ATTN_BITS_PARSER_PARITY_ERROR:
4326 _print_next_block((*par_num)++,
4328 _print_parity(bp, PRS_REG_PRS_PRTY_STS);
4330 case AEU_INPUTS_ATTN_BITS_TSDM_PARITY_ERROR:
4331 _print_next_block((*par_num)++, "TSDM");
4333 TSDM_REG_TSDM_PRTY_STS);
4335 case AEU_INPUTS_ATTN_BITS_SEARCHER_PARITY_ERROR:
4336 _print_next_block((*par_num)++,
4338 _print_parity(bp, SRC_REG_SRC_PRTY_STS);
4340 case AEU_INPUTS_ATTN_BITS_TCM_PARITY_ERROR:
4341 _print_next_block((*par_num)++, "TCM");
4342 _print_parity(bp, TCM_REG_TCM_PRTY_STS);
4344 case AEU_INPUTS_ATTN_BITS_TSEMI_PARITY_ERROR:
4345 _print_next_block((*par_num)++,
4348 TSEM_REG_TSEM_PRTY_STS_0);
4350 TSEM_REG_TSEM_PRTY_STS_1);
4352 case AEU_INPUTS_ATTN_BITS_PBCLIENT_PARITY_ERROR:
4353 _print_next_block((*par_num)++, "XPB");
4354 _print_parity(bp, GRCBASE_XPB +
4355 PB_REG_PB_PRTY_STS);
4368 static bool bnx2x_check_blocks_with_parity1(struct bnx2x *bp, u32 sig,
4369 int *par_num, bool *global,
4378 for (i = 0; sig; i++) {
4379 cur_bit = (0x1UL << i);
4380 if (sig & cur_bit) {
4381 res |= true; /* Each bit is real error! */
4383 case AEU_INPUTS_ATTN_BITS_PBF_PARITY_ERROR:
4385 _print_next_block((*par_num)++, "PBF");
4386 _print_parity(bp, PBF_REG_PBF_PRTY_STS);
4389 case AEU_INPUTS_ATTN_BITS_QM_PARITY_ERROR:
4391 _print_next_block((*par_num)++, "QM");
4392 _print_parity(bp, QM_REG_QM_PRTY_STS);
4395 case AEU_INPUTS_ATTN_BITS_TIMERS_PARITY_ERROR:
4397 _print_next_block((*par_num)++, "TM");
4398 _print_parity(bp, TM_REG_TM_PRTY_STS);
4401 case AEU_INPUTS_ATTN_BITS_XSDM_PARITY_ERROR:
4403 _print_next_block((*par_num)++, "XSDM");
4405 XSDM_REG_XSDM_PRTY_STS);
4408 case AEU_INPUTS_ATTN_BITS_XCM_PARITY_ERROR:
4410 _print_next_block((*par_num)++, "XCM");
4411 _print_parity(bp, XCM_REG_XCM_PRTY_STS);
4414 case AEU_INPUTS_ATTN_BITS_XSEMI_PARITY_ERROR:
4416 _print_next_block((*par_num)++,
4419 XSEM_REG_XSEM_PRTY_STS_0);
4421 XSEM_REG_XSEM_PRTY_STS_1);
4424 case AEU_INPUTS_ATTN_BITS_DOORBELLQ_PARITY_ERROR:
4426 _print_next_block((*par_num)++,
4429 DORQ_REG_DORQ_PRTY_STS);
4432 case AEU_INPUTS_ATTN_BITS_NIG_PARITY_ERROR:
4434 _print_next_block((*par_num)++, "NIG");
4435 if (CHIP_IS_E1x(bp)) {
4437 NIG_REG_NIG_PRTY_STS);
4440 NIG_REG_NIG_PRTY_STS_0);
4442 NIG_REG_NIG_PRTY_STS_1);
4446 case AEU_INPUTS_ATTN_BITS_VAUX_PCI_CORE_PARITY_ERROR:
4448 _print_next_block((*par_num)++,
4452 case AEU_INPUTS_ATTN_BITS_DEBUG_PARITY_ERROR:
4454 _print_next_block((*par_num)++,
4456 _print_parity(bp, DBG_REG_DBG_PRTY_STS);
4459 case AEU_INPUTS_ATTN_BITS_USDM_PARITY_ERROR:
4461 _print_next_block((*par_num)++, "USDM");
4463 USDM_REG_USDM_PRTY_STS);
4466 case AEU_INPUTS_ATTN_BITS_UCM_PARITY_ERROR:
4468 _print_next_block((*par_num)++, "UCM");
4469 _print_parity(bp, UCM_REG_UCM_PRTY_STS);
4472 case AEU_INPUTS_ATTN_BITS_USEMI_PARITY_ERROR:
4474 _print_next_block((*par_num)++,
4477 USEM_REG_USEM_PRTY_STS_0);
4479 USEM_REG_USEM_PRTY_STS_1);
4482 case AEU_INPUTS_ATTN_BITS_UPB_PARITY_ERROR:
4484 _print_next_block((*par_num)++, "UPB");
4485 _print_parity(bp, GRCBASE_UPB +
4486 PB_REG_PB_PRTY_STS);
4489 case AEU_INPUTS_ATTN_BITS_CSDM_PARITY_ERROR:
4491 _print_next_block((*par_num)++, "CSDM");
4493 CSDM_REG_CSDM_PRTY_STS);
4496 case AEU_INPUTS_ATTN_BITS_CCM_PARITY_ERROR:
4498 _print_next_block((*par_num)++, "CCM");
4499 _print_parity(bp, CCM_REG_CCM_PRTY_STS);
4512 static bool bnx2x_check_blocks_with_parity2(struct bnx2x *bp, u32 sig,
4513 int *par_num, bool print)
4521 for (i = 0; sig; i++) {
4522 cur_bit = (0x1UL << i);
4523 if (sig & cur_bit) {
4524 res |= true; /* Each bit is real error! */
4527 case AEU_INPUTS_ATTN_BITS_CSEMI_PARITY_ERROR:
4528 _print_next_block((*par_num)++,
4531 CSEM_REG_CSEM_PRTY_STS_0);
4533 CSEM_REG_CSEM_PRTY_STS_1);
4535 case AEU_INPUTS_ATTN_BITS_PXP_PARITY_ERROR:
4536 _print_next_block((*par_num)++, "PXP");
4537 _print_parity(bp, PXP_REG_PXP_PRTY_STS);
4539 PXP2_REG_PXP2_PRTY_STS_0);
4541 PXP2_REG_PXP2_PRTY_STS_1);
4543 case AEU_IN_ATTN_BITS_PXPPCICLOCKCLIENT_PARITY_ERROR:
4544 _print_next_block((*par_num)++,
4545 "PXPPCICLOCKCLIENT");
4547 case AEU_INPUTS_ATTN_BITS_CFC_PARITY_ERROR:
4548 _print_next_block((*par_num)++, "CFC");
4550 CFC_REG_CFC_PRTY_STS);
4552 case AEU_INPUTS_ATTN_BITS_CDU_PARITY_ERROR:
4553 _print_next_block((*par_num)++, "CDU");
4554 _print_parity(bp, CDU_REG_CDU_PRTY_STS);
4556 case AEU_INPUTS_ATTN_BITS_DMAE_PARITY_ERROR:
4557 _print_next_block((*par_num)++, "DMAE");
4559 DMAE_REG_DMAE_PRTY_STS);
4561 case AEU_INPUTS_ATTN_BITS_IGU_PARITY_ERROR:
4562 _print_next_block((*par_num)++, "IGU");
4563 if (CHIP_IS_E1x(bp))
4565 HC_REG_HC_PRTY_STS);
4568 IGU_REG_IGU_PRTY_STS);
4570 case AEU_INPUTS_ATTN_BITS_MISC_PARITY_ERROR:
4571 _print_next_block((*par_num)++, "MISC");
4573 MISC_REG_MISC_PRTY_STS);
4586 static bool bnx2x_check_blocks_with_parity3(struct bnx2x *bp, u32 sig,
4587 int *par_num, bool *global,
4594 for (i = 0; sig; i++) {
4595 cur_bit = (0x1UL << i);
4596 if (sig & cur_bit) {
4598 case AEU_INPUTS_ATTN_BITS_MCP_LATCHED_ROM_PARITY:
4600 _print_next_block((*par_num)++,
4605 case AEU_INPUTS_ATTN_BITS_MCP_LATCHED_UMP_RX_PARITY:
4607 _print_next_block((*par_num)++,
4612 case AEU_INPUTS_ATTN_BITS_MCP_LATCHED_UMP_TX_PARITY:
4614 _print_next_block((*par_num)++,
4619 case AEU_INPUTS_ATTN_BITS_MCP_LATCHED_SCPAD_PARITY:
4621 _print_next_block((*par_num)++,
4623 /* clear latched SCPAD PATIRY from MCP */
4624 REG_WR(bp, MISC_REG_AEU_CLR_LATCH_SIGNAL,
4637 static bool bnx2x_check_blocks_with_parity4(struct bnx2x *bp, u32 sig,
4638 int *par_num, bool print)
4646 for (i = 0; sig; i++) {
4647 cur_bit = (0x1UL << i);
4648 if (sig & cur_bit) {
4649 res |= true; /* Each bit is real error! */
4652 case AEU_INPUTS_ATTN_BITS_PGLUE_PARITY_ERROR:
4653 _print_next_block((*par_num)++,
4656 PGLUE_B_REG_PGLUE_B_PRTY_STS);
4658 case AEU_INPUTS_ATTN_BITS_ATC_PARITY_ERROR:
4659 _print_next_block((*par_num)++, "ATC");
4661 ATC_REG_ATC_PRTY_STS);
4673 static bool bnx2x_parity_attn(struct bnx2x *bp, bool *global, bool print,
4678 if ((sig[0] & HW_PRTY_ASSERT_SET_0) ||
4679 (sig[1] & HW_PRTY_ASSERT_SET_1) ||
4680 (sig[2] & HW_PRTY_ASSERT_SET_2) ||
4681 (sig[3] & HW_PRTY_ASSERT_SET_3) ||
4682 (sig[4] & HW_PRTY_ASSERT_SET_4)) {
4684 DP(NETIF_MSG_HW, "Was parity error: HW block parity attention:\n"
4685 "[0]:0x%08x [1]:0x%08x [2]:0x%08x [3]:0x%08x [4]:0x%08x\n",
4686 sig[0] & HW_PRTY_ASSERT_SET_0,
4687 sig[1] & HW_PRTY_ASSERT_SET_1,
4688 sig[2] & HW_PRTY_ASSERT_SET_2,
4689 sig[3] & HW_PRTY_ASSERT_SET_3,
4690 sig[4] & HW_PRTY_ASSERT_SET_4);
4693 "Parity errors detected in blocks: ");
4694 res |= bnx2x_check_blocks_with_parity0(bp,
4695 sig[0] & HW_PRTY_ASSERT_SET_0, &par_num, print);
4696 res |= bnx2x_check_blocks_with_parity1(bp,
4697 sig[1] & HW_PRTY_ASSERT_SET_1, &par_num, global, print);
4698 res |= bnx2x_check_blocks_with_parity2(bp,
4699 sig[2] & HW_PRTY_ASSERT_SET_2, &par_num, print);
4700 res |= bnx2x_check_blocks_with_parity3(bp,
4701 sig[3] & HW_PRTY_ASSERT_SET_3, &par_num, global, print);
4702 res |= bnx2x_check_blocks_with_parity4(bp,
4703 sig[4] & HW_PRTY_ASSERT_SET_4, &par_num, print);
4713 * bnx2x_chk_parity_attn - checks for parity attentions.
4715 * @bp: driver handle
4716 * @global: true if there was a global attention
4717 * @print: show parity attention in syslog
4719 bool bnx2x_chk_parity_attn(struct bnx2x *bp, bool *global, bool print)
4721 struct attn_route attn = { {0} };
4722 int port = BP_PORT(bp);
4724 attn.sig[0] = REG_RD(bp,
4725 MISC_REG_AEU_AFTER_INVERT_1_FUNC_0 +
4727 attn.sig[1] = REG_RD(bp,
4728 MISC_REG_AEU_AFTER_INVERT_2_FUNC_0 +
4730 attn.sig[2] = REG_RD(bp,
4731 MISC_REG_AEU_AFTER_INVERT_3_FUNC_0 +
4733 attn.sig[3] = REG_RD(bp,
4734 MISC_REG_AEU_AFTER_INVERT_4_FUNC_0 +
4736 /* Since MCP attentions can't be disabled inside the block, we need to
4737 * read AEU registers to see whether they're currently disabled
4739 attn.sig[3] &= ((REG_RD(bp,
4740 !port ? MISC_REG_AEU_ENABLE4_FUNC_0_OUT_0
4741 : MISC_REG_AEU_ENABLE4_FUNC_1_OUT_0) &
4742 MISC_AEU_ENABLE_MCP_PRTY_BITS) |
4743 ~MISC_AEU_ENABLE_MCP_PRTY_BITS);
4745 if (!CHIP_IS_E1x(bp))
4746 attn.sig[4] = REG_RD(bp,
4747 MISC_REG_AEU_AFTER_INVERT_5_FUNC_0 +
4750 return bnx2x_parity_attn(bp, global, print, attn.sig);
4753 static void bnx2x_attn_int_deasserted4(struct bnx2x *bp, u32 attn)
4756 if (attn & AEU_INPUTS_ATTN_BITS_PGLUE_HW_INTERRUPT) {
4758 val = REG_RD(bp, PGLUE_B_REG_PGLUE_B_INT_STS_CLR);
4759 BNX2X_ERR("PGLUE hw attention 0x%x\n", val);
4760 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_ADDRESS_ERROR)
4761 BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_ADDRESS_ERROR\n");
4762 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_INCORRECT_RCV_BEHAVIOR)
4763 BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_INCORRECT_RCV_BEHAVIOR\n");
4764 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_WAS_ERROR_ATTN)
4765 BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_WAS_ERROR_ATTN\n");
4766 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_VF_LENGTH_VIOLATION_ATTN)
4767 BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_VF_LENGTH_VIOLATION_ATTN\n");
4769 PGLUE_B_PGLUE_B_INT_STS_REG_VF_GRC_SPACE_VIOLATION_ATTN)
4770 BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_VF_GRC_SPACE_VIOLATION_ATTN\n");
4772 PGLUE_B_PGLUE_B_INT_STS_REG_VF_MSIX_BAR_VIOLATION_ATTN)
4773 BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_VF_MSIX_BAR_VIOLATION_ATTN\n");
4774 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_TCPL_ERROR_ATTN)
4775 BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_TCPL_ERROR_ATTN\n");
4776 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_TCPL_IN_TWO_RCBS_ATTN)
4777 BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_TCPL_IN_TWO_RCBS_ATTN\n");
4778 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_CSSNOOP_FIFO_OVERFLOW)
4779 BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_CSSNOOP_FIFO_OVERFLOW\n");
4781 if (attn & AEU_INPUTS_ATTN_BITS_ATC_HW_INTERRUPT) {
4782 val = REG_RD(bp, ATC_REG_ATC_INT_STS_CLR);
4783 BNX2X_ERR("ATC hw attention 0x%x\n", val);
4784 if (val & ATC_ATC_INT_STS_REG_ADDRESS_ERROR)
4785 BNX2X_ERR("ATC_ATC_INT_STS_REG_ADDRESS_ERROR\n");
4786 if (val & ATC_ATC_INT_STS_REG_ATC_TCPL_TO_NOT_PEND)
4787 BNX2X_ERR("ATC_ATC_INT_STS_REG_ATC_TCPL_TO_NOT_PEND\n");
4788 if (val & ATC_ATC_INT_STS_REG_ATC_GPA_MULTIPLE_HITS)
4789 BNX2X_ERR("ATC_ATC_INT_STS_REG_ATC_GPA_MULTIPLE_HITS\n");
4790 if (val & ATC_ATC_INT_STS_REG_ATC_RCPL_TO_EMPTY_CNT)
4791 BNX2X_ERR("ATC_ATC_INT_STS_REG_ATC_RCPL_TO_EMPTY_CNT\n");
4792 if (val & ATC_ATC_INT_STS_REG_ATC_TCPL_ERROR)
4793 BNX2X_ERR("ATC_ATC_INT_STS_REG_ATC_TCPL_ERROR\n");
4794 if (val & ATC_ATC_INT_STS_REG_ATC_IREQ_LESS_THAN_STU)
4795 BNX2X_ERR("ATC_ATC_INT_STS_REG_ATC_IREQ_LESS_THAN_STU\n");
4798 if (attn & (AEU_INPUTS_ATTN_BITS_PGLUE_PARITY_ERROR |
4799 AEU_INPUTS_ATTN_BITS_ATC_PARITY_ERROR)) {
4800 BNX2X_ERR("FATAL parity attention set4 0x%x\n",
4801 (u32)(attn & (AEU_INPUTS_ATTN_BITS_PGLUE_PARITY_ERROR |
4802 AEU_INPUTS_ATTN_BITS_ATC_PARITY_ERROR)));
4806 static void bnx2x_attn_int_deasserted(struct bnx2x *bp, u32 deasserted)
4808 struct attn_route attn, *group_mask;
4809 int port = BP_PORT(bp);
4814 bool global = false;
4816 /* need to take HW lock because MCP or other port might also
4817 try to handle this event */
4818 bnx2x_acquire_alr(bp);
4820 if (bnx2x_chk_parity_attn(bp, &global, true)) {
4821 #ifndef BNX2X_STOP_ON_ERROR
4822 bp->recovery_state = BNX2X_RECOVERY_INIT;
4823 schedule_delayed_work(&bp->sp_rtnl_task, 0);
4824 /* Disable HW interrupts */
4825 bnx2x_int_disable(bp);
4826 /* In case of parity errors don't handle attentions so that
4827 * other function would "see" parity errors.
4832 bnx2x_release_alr(bp);
4836 attn.sig[0] = REG_RD(bp, MISC_REG_AEU_AFTER_INVERT_1_FUNC_0 + port*4);
4837 attn.sig[1] = REG_RD(bp, MISC_REG_AEU_AFTER_INVERT_2_FUNC_0 + port*4);
4838 attn.sig[2] = REG_RD(bp, MISC_REG_AEU_AFTER_INVERT_3_FUNC_0 + port*4);
4839 attn.sig[3] = REG_RD(bp, MISC_REG_AEU_AFTER_INVERT_4_FUNC_0 + port*4);
4840 if (!CHIP_IS_E1x(bp))
4842 REG_RD(bp, MISC_REG_AEU_AFTER_INVERT_5_FUNC_0 + port*4);
4846 DP(NETIF_MSG_HW, "attn: %08x %08x %08x %08x %08x\n",
4847 attn.sig[0], attn.sig[1], attn.sig[2], attn.sig[3], attn.sig[4]);
4849 for (index = 0; index < MAX_DYNAMIC_ATTN_GRPS; index++) {
4850 if (deasserted & (1 << index)) {
4851 group_mask = &bp->attn_group[index];
4853 DP(NETIF_MSG_HW, "group[%d]: %08x %08x %08x %08x %08x\n",
4855 group_mask->sig[0], group_mask->sig[1],
4856 group_mask->sig[2], group_mask->sig[3],
4857 group_mask->sig[4]);
4859 bnx2x_attn_int_deasserted4(bp,
4860 attn.sig[4] & group_mask->sig[4]);
4861 bnx2x_attn_int_deasserted3(bp,
4862 attn.sig[3] & group_mask->sig[3]);
4863 bnx2x_attn_int_deasserted1(bp,
4864 attn.sig[1] & group_mask->sig[1]);
4865 bnx2x_attn_int_deasserted2(bp,
4866 attn.sig[2] & group_mask->sig[2]);
4867 bnx2x_attn_int_deasserted0(bp,
4868 attn.sig[0] & group_mask->sig[0]);
4872 bnx2x_release_alr(bp);
4874 if (bp->common.int_block == INT_BLOCK_HC)
4875 reg_addr = (HC_REG_COMMAND_REG + port*32 +
4876 COMMAND_REG_ATTN_BITS_CLR);
4878 reg_addr = (BAR_IGU_INTMEM + IGU_CMD_ATTN_BIT_CLR_UPPER*8);
4881 DP(NETIF_MSG_HW, "about to mask 0x%08x at %s addr 0x%x\n", val,
4882 (bp->common.int_block == INT_BLOCK_HC) ? "HC" : "IGU", reg_addr);
4883 REG_WR(bp, reg_addr, val);
4885 if (~bp->attn_state & deasserted)
4886 BNX2X_ERR("IGU ERROR\n");
4888 reg_addr = port ? MISC_REG_AEU_MASK_ATTN_FUNC_1 :
4889 MISC_REG_AEU_MASK_ATTN_FUNC_0;
4891 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_PORT0_ATT_MASK + port);
4892 aeu_mask = REG_RD(bp, reg_addr);
4894 DP(NETIF_MSG_HW, "aeu_mask %x newly deasserted %x\n",
4895 aeu_mask, deasserted);
4896 aeu_mask |= (deasserted & 0x3ff);
4897 DP(NETIF_MSG_HW, "new mask %x\n", aeu_mask);
4899 REG_WR(bp, reg_addr, aeu_mask);
4900 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_PORT0_ATT_MASK + port);
4902 DP(NETIF_MSG_HW, "attn_state %x\n", bp->attn_state);
4903 bp->attn_state &= ~deasserted;
4904 DP(NETIF_MSG_HW, "new state %x\n", bp->attn_state);
4907 static void bnx2x_attn_int(struct bnx2x *bp)
4909 /* read local copy of bits */
4910 u32 attn_bits = le32_to_cpu(bp->def_status_blk->atten_status_block.
4912 u32 attn_ack = le32_to_cpu(bp->def_status_blk->atten_status_block.
4914 u32 attn_state = bp->attn_state;
4916 /* look for changed bits */
4917 u32 asserted = attn_bits & ~attn_ack & ~attn_state;
4918 u32 deasserted = ~attn_bits & attn_ack & attn_state;
4921 "attn_bits %x attn_ack %x asserted %x deasserted %x\n",
4922 attn_bits, attn_ack, asserted, deasserted);
4924 if (~(attn_bits ^ attn_ack) & (attn_bits ^ attn_state))
4925 BNX2X_ERR("BAD attention state\n");
4927 /* handle bits that were raised */
4929 bnx2x_attn_int_asserted(bp, asserted);
4932 bnx2x_attn_int_deasserted(bp, deasserted);
4935 void bnx2x_igu_ack_sb(struct bnx2x *bp, u8 igu_sb_id, u8 segment,
4936 u16 index, u8 op, u8 update)
4938 u32 igu_addr = bp->igu_base_addr;
4939 igu_addr += (IGU_CMD_INT_ACK_BASE + igu_sb_id)*8;
4940 bnx2x_igu_ack_sb_gen(bp, igu_sb_id, segment, index, op, update,
4944 static void bnx2x_update_eq_prod(struct bnx2x *bp, u16 prod)
4946 /* No memory barriers */
4947 storm_memset_eq_prod(bp, prod, BP_FUNC(bp));
4948 mmiowb(); /* keep prod updates ordered */
4951 static int bnx2x_cnic_handle_cfc_del(struct bnx2x *bp, u32 cid,
4952 union event_ring_elem *elem)
4954 u8 err = elem->message.error;
4956 if (!bp->cnic_eth_dev.starting_cid ||
4957 (cid < bp->cnic_eth_dev.starting_cid &&
4958 cid != bp->cnic_eth_dev.iscsi_l2_cid))
4961 DP(BNX2X_MSG_SP, "got delete ramrod for CNIC CID %d\n", cid);
4963 if (unlikely(err)) {
4965 BNX2X_ERR("got delete ramrod for CNIC CID %d with error!\n",
4967 bnx2x_panic_dump(bp, false);
4969 bnx2x_cnic_cfc_comp(bp, cid, err);
4973 static void bnx2x_handle_mcast_eqe(struct bnx2x *bp)
4975 struct bnx2x_mcast_ramrod_params rparam;
4978 memset(&rparam, 0, sizeof(rparam));
4980 rparam.mcast_obj = &bp->mcast_obj;
4982 netif_addr_lock_bh(bp->dev);
4984 /* Clear pending state for the last command */
4985 bp->mcast_obj.raw.clear_pending(&bp->mcast_obj.raw);
4987 /* If there are pending mcast commands - send them */
4988 if (bp->mcast_obj.check_pending(&bp->mcast_obj)) {
4989 rc = bnx2x_config_mcast(bp, &rparam, BNX2X_MCAST_CMD_CONT);
4991 BNX2X_ERR("Failed to send pending mcast commands: %d\n",
4995 netif_addr_unlock_bh(bp->dev);
4998 static void bnx2x_handle_classification_eqe(struct bnx2x *bp,
4999 union event_ring_elem *elem)
5001 unsigned long ramrod_flags = 0;
5003 u32 cid = elem->message.data.eth_event.echo & BNX2X_SWCID_MASK;
5004 struct bnx2x_vlan_mac_obj *vlan_mac_obj;
5006 /* Always push next commands out, don't wait here */
5007 __set_bit(RAMROD_CONT, &ramrod_flags);
5009 switch (le32_to_cpu((__force __le32)elem->message.data.eth_event.echo)
5010 >> BNX2X_SWCID_SHIFT) {
5011 case BNX2X_FILTER_MAC_PENDING:
5012 DP(BNX2X_MSG_SP, "Got SETUP_MAC completions\n");
5013 if (CNIC_LOADED(bp) && (cid == BNX2X_ISCSI_ETH_CID(bp)))
5014 vlan_mac_obj = &bp->iscsi_l2_mac_obj;
5016 vlan_mac_obj = &bp->sp_objs[cid].mac_obj;
5019 case BNX2X_FILTER_MCAST_PENDING:
5020 DP(BNX2X_MSG_SP, "Got SETUP_MCAST completions\n");
5021 /* This is only relevant for 57710 where multicast MACs are
5022 * configured as unicast MACs using the same ramrod.
5024 bnx2x_handle_mcast_eqe(bp);
5027 BNX2X_ERR("Unsupported classification command: %d\n",
5028 elem->message.data.eth_event.echo);
5032 rc = vlan_mac_obj->complete(bp, vlan_mac_obj, elem, &ramrod_flags);
5035 BNX2X_ERR("Failed to schedule new commands: %d\n", rc);
5037 DP(BNX2X_MSG_SP, "Scheduled next pending commands...\n");
5040 static void bnx2x_set_iscsi_eth_rx_mode(struct bnx2x *bp, bool start);
5042 static void bnx2x_handle_rx_mode_eqe(struct bnx2x *bp)
5044 netif_addr_lock_bh(bp->dev);
5046 clear_bit(BNX2X_FILTER_RX_MODE_PENDING, &bp->sp_state);
5048 /* Send rx_mode command again if was requested */
5049 if (test_and_clear_bit(BNX2X_FILTER_RX_MODE_SCHED, &bp->sp_state))
5050 bnx2x_set_storm_rx_mode(bp);
5051 else if (test_and_clear_bit(BNX2X_FILTER_ISCSI_ETH_START_SCHED,
5053 bnx2x_set_iscsi_eth_rx_mode(bp, true);
5054 else if (test_and_clear_bit(BNX2X_FILTER_ISCSI_ETH_STOP_SCHED,
5056 bnx2x_set_iscsi_eth_rx_mode(bp, false);
5058 netif_addr_unlock_bh(bp->dev);
5061 static void bnx2x_after_afex_vif_lists(struct bnx2x *bp,
5062 union event_ring_elem *elem)
5064 if (elem->message.data.vif_list_event.echo == VIF_LIST_RULE_GET) {
5066 "afex: ramrod completed VIF LIST_GET, addrs 0x%x\n",
5067 elem->message.data.vif_list_event.func_bit_map);
5068 bnx2x_fw_command(bp, DRV_MSG_CODE_AFEX_LISTGET_ACK,
5069 elem->message.data.vif_list_event.func_bit_map);
5070 } else if (elem->message.data.vif_list_event.echo ==
5071 VIF_LIST_RULE_SET) {
5072 DP(BNX2X_MSG_SP, "afex: ramrod completed VIF LIST_SET\n");
5073 bnx2x_fw_command(bp, DRV_MSG_CODE_AFEX_LISTSET_ACK, 0);
5077 /* called with rtnl_lock */
5078 static void bnx2x_after_function_update(struct bnx2x *bp)
5081 struct bnx2x_fastpath *fp;
5082 struct bnx2x_queue_state_params queue_params = {NULL};
5083 struct bnx2x_queue_update_params *q_update_params =
5084 &queue_params.params.update;
5086 /* Send Q update command with afex vlan removal values for all Qs */
5087 queue_params.cmd = BNX2X_Q_CMD_UPDATE;
5089 /* set silent vlan removal values according to vlan mode */
5090 __set_bit(BNX2X_Q_UPDATE_SILENT_VLAN_REM_CHNG,
5091 &q_update_params->update_flags);
5092 __set_bit(BNX2X_Q_UPDATE_SILENT_VLAN_REM,
5093 &q_update_params->update_flags);
5094 __set_bit(RAMROD_COMP_WAIT, &queue_params.ramrod_flags);
5096 /* in access mode mark mask and value are 0 to strip all vlans */
5097 if (bp->afex_vlan_mode == FUNC_MF_CFG_AFEX_VLAN_ACCESS_MODE) {
5098 q_update_params->silent_removal_value = 0;
5099 q_update_params->silent_removal_mask = 0;
5101 q_update_params->silent_removal_value =
5102 (bp->afex_def_vlan_tag & VLAN_VID_MASK);
5103 q_update_params->silent_removal_mask = VLAN_VID_MASK;
5106 for_each_eth_queue(bp, q) {
5107 /* Set the appropriate Queue object */
5109 queue_params.q_obj = &bnx2x_sp_obj(bp, fp).q_obj;
5111 /* send the ramrod */
5112 rc = bnx2x_queue_state_change(bp, &queue_params);
5114 BNX2X_ERR("Failed to config silent vlan rem for Q %d\n",
5118 if (!NO_FCOE(bp) && CNIC_ENABLED(bp)) {
5119 fp = &bp->fp[FCOE_IDX(bp)];
5120 queue_params.q_obj = &bnx2x_sp_obj(bp, fp).q_obj;
5122 /* clear pending completion bit */
5123 __clear_bit(RAMROD_COMP_WAIT, &queue_params.ramrod_flags);
5125 /* mark latest Q bit */
5126 smp_mb__before_clear_bit();
5127 set_bit(BNX2X_AFEX_FCOE_Q_UPDATE_PENDING, &bp->sp_state);
5128 smp_mb__after_clear_bit();
5130 /* send Q update ramrod for FCoE Q */
5131 rc = bnx2x_queue_state_change(bp, &queue_params);
5133 BNX2X_ERR("Failed to config silent vlan rem for Q %d\n",
5136 /* If no FCoE ring - ACK MCP now */
5137 bnx2x_link_report(bp);
5138 bnx2x_fw_command(bp, DRV_MSG_CODE_AFEX_VIFSET_ACK, 0);
5142 static struct bnx2x_queue_sp_obj *bnx2x_cid_to_q_obj(
5143 struct bnx2x *bp, u32 cid)
5145 DP(BNX2X_MSG_SP, "retrieving fp from cid %d\n", cid);
5147 if (CNIC_LOADED(bp) && (cid == BNX2X_FCOE_ETH_CID(bp)))
5148 return &bnx2x_fcoe_sp_obj(bp, q_obj);
5150 return &bp->sp_objs[CID_TO_FP(cid, bp)].q_obj;
5153 static void bnx2x_eq_int(struct bnx2x *bp)
5155 u16 hw_cons, sw_cons, sw_prod;
5156 union event_ring_elem *elem;
5160 int rc, spqe_cnt = 0;
5161 struct bnx2x_queue_sp_obj *q_obj;
5162 struct bnx2x_func_sp_obj *f_obj = &bp->func_obj;
5163 struct bnx2x_raw_obj *rss_raw = &bp->rss_conf_obj.raw;
5165 hw_cons = le16_to_cpu(*bp->eq_cons_sb);
5167 /* The hw_cos range is 1-255, 257 - the sw_cons range is 0-254, 256.
5168 * when we get the next-page we need to adjust so the loop
5169 * condition below will be met. The next element is the size of a
5170 * regular element and hence incrementing by 1
5172 if ((hw_cons & EQ_DESC_MAX_PAGE) == EQ_DESC_MAX_PAGE)
5175 /* This function may never run in parallel with itself for a
5176 * specific bp, thus there is no need in "paired" read memory
5179 sw_cons = bp->eq_cons;
5180 sw_prod = bp->eq_prod;
5182 DP(BNX2X_MSG_SP, "EQ: hw_cons %u sw_cons %u bp->eq_spq_left %x\n",
5183 hw_cons, sw_cons, atomic_read(&bp->eq_spq_left));
5185 for (; sw_cons != hw_cons;
5186 sw_prod = NEXT_EQ_IDX(sw_prod), sw_cons = NEXT_EQ_IDX(sw_cons)) {
5188 elem = &bp->eq_ring[EQ_DESC(sw_cons)];
5190 rc = bnx2x_iov_eq_sp_event(bp, elem);
5192 DP(BNX2X_MSG_IOV, "bnx2x_iov_eq_sp_event returned %d\n",
5197 /* elem CID originates from FW; actually LE */
5198 cid = SW_CID((__force __le32)
5199 elem->message.data.cfc_del_event.cid);
5200 opcode = elem->message.opcode;
5202 /* handle eq element */
5204 case EVENT_RING_OPCODE_VF_PF_CHANNEL:
5205 DP(BNX2X_MSG_IOV, "vf pf channel element on eq\n");
5206 bnx2x_vf_mbx(bp, &elem->message.data.vf_pf_event);
5209 case EVENT_RING_OPCODE_STAT_QUERY:
5210 DP(BNX2X_MSG_SP | BNX2X_MSG_STATS,
5211 "got statistics comp event %d\n",
5213 /* nothing to do with stats comp */
5216 case EVENT_RING_OPCODE_CFC_DEL:
5217 /* handle according to cid range */
5219 * we may want to verify here that the bp state is
5223 "got delete ramrod for MULTI[%d]\n", cid);
5225 if (CNIC_LOADED(bp) &&
5226 !bnx2x_cnic_handle_cfc_del(bp, cid, elem))
5229 q_obj = bnx2x_cid_to_q_obj(bp, cid);
5231 if (q_obj->complete_cmd(bp, q_obj, BNX2X_Q_CMD_CFC_DEL))
5236 case EVENT_RING_OPCODE_STOP_TRAFFIC:
5237 DP(BNX2X_MSG_SP | BNX2X_MSG_DCB, "got STOP TRAFFIC\n");
5238 bnx2x_dcbx_set_params(bp, BNX2X_DCBX_STATE_TX_PAUSED);
5239 if (f_obj->complete_cmd(bp, f_obj,
5240 BNX2X_F_CMD_TX_STOP))
5244 case EVENT_RING_OPCODE_START_TRAFFIC:
5245 DP(BNX2X_MSG_SP | BNX2X_MSG_DCB, "got START TRAFFIC\n");
5246 bnx2x_dcbx_set_params(bp, BNX2X_DCBX_STATE_TX_RELEASED);
5247 if (f_obj->complete_cmd(bp, f_obj,
5248 BNX2X_F_CMD_TX_START))
5252 case EVENT_RING_OPCODE_FUNCTION_UPDATE:
5253 echo = elem->message.data.function_update_event.echo;
5254 if (echo == SWITCH_UPDATE) {
5255 DP(BNX2X_MSG_SP | NETIF_MSG_IFUP,
5256 "got FUNC_SWITCH_UPDATE ramrod\n");
5257 if (f_obj->complete_cmd(
5258 bp, f_obj, BNX2X_F_CMD_SWITCH_UPDATE))
5262 DP(BNX2X_MSG_SP | BNX2X_MSG_MCP,
5263 "AFEX: ramrod completed FUNCTION_UPDATE\n");
5264 f_obj->complete_cmd(bp, f_obj,
5265 BNX2X_F_CMD_AFEX_UPDATE);
5267 /* We will perform the Queues update from
5268 * sp_rtnl task as all Queue SP operations
5269 * should run under rtnl_lock.
5271 smp_mb__before_clear_bit();
5272 set_bit(BNX2X_SP_RTNL_AFEX_F_UPDATE,
5273 &bp->sp_rtnl_state);
5274 smp_mb__after_clear_bit();
5276 schedule_delayed_work(&bp->sp_rtnl_task, 0);
5281 case EVENT_RING_OPCODE_AFEX_VIF_LISTS:
5282 f_obj->complete_cmd(bp, f_obj,
5283 BNX2X_F_CMD_AFEX_VIFLISTS);
5284 bnx2x_after_afex_vif_lists(bp, elem);
5286 case EVENT_RING_OPCODE_FUNCTION_START:
5287 DP(BNX2X_MSG_SP | NETIF_MSG_IFUP,
5288 "got FUNC_START ramrod\n");
5289 if (f_obj->complete_cmd(bp, f_obj, BNX2X_F_CMD_START))
5294 case EVENT_RING_OPCODE_FUNCTION_STOP:
5295 DP(BNX2X_MSG_SP | NETIF_MSG_IFUP,
5296 "got FUNC_STOP ramrod\n");
5297 if (f_obj->complete_cmd(bp, f_obj, BNX2X_F_CMD_STOP))
5303 switch (opcode | bp->state) {
5304 case (EVENT_RING_OPCODE_RSS_UPDATE_RULES |
5306 case (EVENT_RING_OPCODE_RSS_UPDATE_RULES |
5307 BNX2X_STATE_OPENING_WAIT4_PORT):
5308 cid = elem->message.data.eth_event.echo &
5310 DP(BNX2X_MSG_SP, "got RSS_UPDATE ramrod. CID %d\n",
5312 rss_raw->clear_pending(rss_raw);
5315 case (EVENT_RING_OPCODE_SET_MAC | BNX2X_STATE_OPEN):
5316 case (EVENT_RING_OPCODE_SET_MAC | BNX2X_STATE_DIAG):
5317 case (EVENT_RING_OPCODE_SET_MAC |
5318 BNX2X_STATE_CLOSING_WAIT4_HALT):
5319 case (EVENT_RING_OPCODE_CLASSIFICATION_RULES |
5321 case (EVENT_RING_OPCODE_CLASSIFICATION_RULES |
5323 case (EVENT_RING_OPCODE_CLASSIFICATION_RULES |
5324 BNX2X_STATE_CLOSING_WAIT4_HALT):
5325 DP(BNX2X_MSG_SP, "got (un)set mac ramrod\n");
5326 bnx2x_handle_classification_eqe(bp, elem);
5329 case (EVENT_RING_OPCODE_MULTICAST_RULES |
5331 case (EVENT_RING_OPCODE_MULTICAST_RULES |
5333 case (EVENT_RING_OPCODE_MULTICAST_RULES |
5334 BNX2X_STATE_CLOSING_WAIT4_HALT):
5335 DP(BNX2X_MSG_SP, "got mcast ramrod\n");
5336 bnx2x_handle_mcast_eqe(bp);
5339 case (EVENT_RING_OPCODE_FILTERS_RULES |
5341 case (EVENT_RING_OPCODE_FILTERS_RULES |
5343 case (EVENT_RING_OPCODE_FILTERS_RULES |
5344 BNX2X_STATE_CLOSING_WAIT4_HALT):
5345 DP(BNX2X_MSG_SP, "got rx_mode ramrod\n");
5346 bnx2x_handle_rx_mode_eqe(bp);
5349 /* unknown event log error and continue */
5350 BNX2X_ERR("Unknown EQ event %d, bp->state 0x%x\n",
5351 elem->message.opcode, bp->state);
5357 smp_mb__before_atomic_inc();
5358 atomic_add(spqe_cnt, &bp->eq_spq_left);
5360 bp->eq_cons = sw_cons;
5361 bp->eq_prod = sw_prod;
5362 /* Make sure that above mem writes were issued towards the memory */
5365 /* update producer */
5366 bnx2x_update_eq_prod(bp, bp->eq_prod);
5369 static void bnx2x_sp_task(struct work_struct *work)
5371 struct bnx2x *bp = container_of(work, struct bnx2x, sp_task.work);
5373 DP(BNX2X_MSG_SP, "sp task invoked\n");
5375 /* make sure the atomic interrupt_occurred has been written */
5377 if (atomic_read(&bp->interrupt_occurred)) {
5379 /* what work needs to be performed? */
5380 u16 status = bnx2x_update_dsb_idx(bp);
5382 DP(BNX2X_MSG_SP, "status %x\n", status);
5383 DP(BNX2X_MSG_SP, "setting interrupt_occurred to 0\n");
5384 atomic_set(&bp->interrupt_occurred, 0);
5387 if (status & BNX2X_DEF_SB_ATT_IDX) {
5389 status &= ~BNX2X_DEF_SB_ATT_IDX;
5392 /* SP events: STAT_QUERY and others */
5393 if (status & BNX2X_DEF_SB_IDX) {
5394 struct bnx2x_fastpath *fp = bnx2x_fcoe_fp(bp);
5396 if (FCOE_INIT(bp) &&
5397 (bnx2x_has_rx_work(fp) || bnx2x_has_tx_work(fp))) {
5398 /* Prevent local bottom-halves from running as
5399 * we are going to change the local NAPI list.
5402 napi_schedule(&bnx2x_fcoe(bp, napi));
5406 /* Handle EQ completions */
5408 bnx2x_ack_sb(bp, bp->igu_dsb_id, USTORM_ID,
5409 le16_to_cpu(bp->def_idx), IGU_INT_NOP, 1);
5411 status &= ~BNX2X_DEF_SB_IDX;
5414 /* if status is non zero then perhaps something went wrong */
5415 if (unlikely(status))
5417 "got an unknown interrupt! (status 0x%x)\n", status);
5419 /* ack status block only if something was actually handled */
5420 bnx2x_ack_sb(bp, bp->igu_dsb_id, ATTENTION_ID,
5421 le16_to_cpu(bp->def_att_idx), IGU_INT_ENABLE, 1);
5424 /* must be called after the EQ processing (since eq leads to sriov
5425 * ramrod completion flows).
5426 * This flow may have been scheduled by the arrival of a ramrod
5427 * completion, or by the sriov code rescheduling itself.
5429 bnx2x_iov_sp_task(bp);
5431 /* afex - poll to check if VIFSET_ACK should be sent to MFW */
5432 if (test_and_clear_bit(BNX2X_AFEX_PENDING_VIFSET_MCP_ACK,
5434 bnx2x_link_report(bp);
5435 bnx2x_fw_command(bp, DRV_MSG_CODE_AFEX_VIFSET_ACK, 0);
5439 irqreturn_t bnx2x_msix_sp_int(int irq, void *dev_instance)
5441 struct net_device *dev = dev_instance;
5442 struct bnx2x *bp = netdev_priv(dev);
5444 bnx2x_ack_sb(bp, bp->igu_dsb_id, USTORM_ID, 0,
5445 IGU_INT_DISABLE, 0);
5447 #ifdef BNX2X_STOP_ON_ERROR
5448 if (unlikely(bp->panic))
5452 if (CNIC_LOADED(bp)) {
5453 struct cnic_ops *c_ops;
5456 c_ops = rcu_dereference(bp->cnic_ops);
5458 c_ops->cnic_handler(bp->cnic_data, NULL);
5462 /* schedule sp task to perform default status block work, ack
5463 * attentions and enable interrupts.
5465 bnx2x_schedule_sp_task(bp);
5470 /* end of slow path */
5472 void bnx2x_drv_pulse(struct bnx2x *bp)
5474 SHMEM_WR(bp, func_mb[BP_FW_MB_IDX(bp)].drv_pulse_mb,
5475 bp->fw_drv_pulse_wr_seq);
5478 static void bnx2x_timer(unsigned long data)
5480 struct bnx2x *bp = (struct bnx2x *) data;
5482 if (!netif_running(bp->dev))
5487 int mb_idx = BP_FW_MB_IDX(bp);
5491 ++bp->fw_drv_pulse_wr_seq;
5492 bp->fw_drv_pulse_wr_seq &= DRV_PULSE_SEQ_MASK;
5493 drv_pulse = bp->fw_drv_pulse_wr_seq;
5494 bnx2x_drv_pulse(bp);
5496 mcp_pulse = (SHMEM_RD(bp, func_mb[mb_idx].mcp_pulse_mb) &
5497 MCP_PULSE_SEQ_MASK);
5498 /* The delta between driver pulse and mcp response
5499 * should not get too big. If the MFW is more than 5 pulses
5500 * behind, we should worry about it enough to generate an error
5503 if (((drv_pulse - mcp_pulse) & MCP_PULSE_SEQ_MASK) > 5)
5504 BNX2X_ERR("MFW seems hanged: drv_pulse (0x%x) != mcp_pulse (0x%x)\n",
5505 drv_pulse, mcp_pulse);
5508 if (bp->state == BNX2X_STATE_OPEN)
5509 bnx2x_stats_handle(bp, STATS_EVENT_UPDATE);
5511 /* sample pf vf bulletin board for new posts from pf */
5513 bnx2x_timer_sriov(bp);
5515 mod_timer(&bp->timer, jiffies + bp->current_interval);
5518 /* end of Statistics */
5523 * nic init service functions
5526 static void bnx2x_fill(struct bnx2x *bp, u32 addr, int fill, u32 len)
5529 if (!(len%4) && !(addr%4))
5530 for (i = 0; i < len; i += 4)
5531 REG_WR(bp, addr + i, fill);
5533 for (i = 0; i < len; i++)
5534 REG_WR8(bp, addr + i, fill);
5537 /* helper: writes FP SP data to FW - data_size in dwords */
5538 static void bnx2x_wr_fp_sb_data(struct bnx2x *bp,
5544 for (index = 0; index < data_size; index++)
5545 REG_WR(bp, BAR_CSTRORM_INTMEM +
5546 CSTORM_STATUS_BLOCK_DATA_OFFSET(fw_sb_id) +
5548 *(sb_data_p + index));
5551 static void bnx2x_zero_fp_sb(struct bnx2x *bp, int fw_sb_id)
5555 struct hc_status_block_data_e2 sb_data_e2;
5556 struct hc_status_block_data_e1x sb_data_e1x;
5558 /* disable the function first */
5559 if (!CHIP_IS_E1x(bp)) {
5560 memset(&sb_data_e2, 0, sizeof(struct hc_status_block_data_e2));
5561 sb_data_e2.common.state = SB_DISABLED;
5562 sb_data_e2.common.p_func.vf_valid = false;
5563 sb_data_p = (u32 *)&sb_data_e2;
5564 data_size = sizeof(struct hc_status_block_data_e2)/sizeof(u32);
5566 memset(&sb_data_e1x, 0,
5567 sizeof(struct hc_status_block_data_e1x));
5568 sb_data_e1x.common.state = SB_DISABLED;
5569 sb_data_e1x.common.p_func.vf_valid = false;
5570 sb_data_p = (u32 *)&sb_data_e1x;
5571 data_size = sizeof(struct hc_status_block_data_e1x)/sizeof(u32);
5573 bnx2x_wr_fp_sb_data(bp, fw_sb_id, sb_data_p, data_size);
5575 bnx2x_fill(bp, BAR_CSTRORM_INTMEM +
5576 CSTORM_STATUS_BLOCK_OFFSET(fw_sb_id), 0,
5577 CSTORM_STATUS_BLOCK_SIZE);
5578 bnx2x_fill(bp, BAR_CSTRORM_INTMEM +
5579 CSTORM_SYNC_BLOCK_OFFSET(fw_sb_id), 0,
5580 CSTORM_SYNC_BLOCK_SIZE);
5583 /* helper: writes SP SB data to FW */
5584 static void bnx2x_wr_sp_sb_data(struct bnx2x *bp,
5585 struct hc_sp_status_block_data *sp_sb_data)
5587 int func = BP_FUNC(bp);
5589 for (i = 0; i < sizeof(struct hc_sp_status_block_data)/sizeof(u32); i++)
5590 REG_WR(bp, BAR_CSTRORM_INTMEM +
5591 CSTORM_SP_STATUS_BLOCK_DATA_OFFSET(func) +
5593 *((u32 *)sp_sb_data + i));
5596 static void bnx2x_zero_sp_sb(struct bnx2x *bp)
5598 int func = BP_FUNC(bp);
5599 struct hc_sp_status_block_data sp_sb_data;
5600 memset(&sp_sb_data, 0, sizeof(struct hc_sp_status_block_data));
5602 sp_sb_data.state = SB_DISABLED;
5603 sp_sb_data.p_func.vf_valid = false;
5605 bnx2x_wr_sp_sb_data(bp, &sp_sb_data);
5607 bnx2x_fill(bp, BAR_CSTRORM_INTMEM +
5608 CSTORM_SP_STATUS_BLOCK_OFFSET(func), 0,
5609 CSTORM_SP_STATUS_BLOCK_SIZE);
5610 bnx2x_fill(bp, BAR_CSTRORM_INTMEM +
5611 CSTORM_SP_SYNC_BLOCK_OFFSET(func), 0,
5612 CSTORM_SP_SYNC_BLOCK_SIZE);
5615 static void bnx2x_setup_ndsb_state_machine(struct hc_status_block_sm *hc_sm,
5616 int igu_sb_id, int igu_seg_id)
5618 hc_sm->igu_sb_id = igu_sb_id;
5619 hc_sm->igu_seg_id = igu_seg_id;
5620 hc_sm->timer_value = 0xFF;
5621 hc_sm->time_to_expire = 0xFFFFFFFF;
5624 /* allocates state machine ids. */
5625 static void bnx2x_map_sb_state_machines(struct hc_index_data *index_data)
5627 /* zero out state machine indices */
5629 index_data[HC_INDEX_ETH_RX_CQ_CONS].flags &= ~HC_INDEX_DATA_SM_ID;
5632 index_data[HC_INDEX_OOO_TX_CQ_CONS].flags &= ~HC_INDEX_DATA_SM_ID;
5633 index_data[HC_INDEX_ETH_TX_CQ_CONS_COS0].flags &= ~HC_INDEX_DATA_SM_ID;
5634 index_data[HC_INDEX_ETH_TX_CQ_CONS_COS1].flags &= ~HC_INDEX_DATA_SM_ID;
5635 index_data[HC_INDEX_ETH_TX_CQ_CONS_COS2].flags &= ~HC_INDEX_DATA_SM_ID;
5639 index_data[HC_INDEX_ETH_RX_CQ_CONS].flags |=
5640 SM_RX_ID << HC_INDEX_DATA_SM_ID_SHIFT;
5643 index_data[HC_INDEX_OOO_TX_CQ_CONS].flags |=
5644 SM_TX_ID << HC_INDEX_DATA_SM_ID_SHIFT;
5645 index_data[HC_INDEX_ETH_TX_CQ_CONS_COS0].flags |=
5646 SM_TX_ID << HC_INDEX_DATA_SM_ID_SHIFT;
5647 index_data[HC_INDEX_ETH_TX_CQ_CONS_COS1].flags |=
5648 SM_TX_ID << HC_INDEX_DATA_SM_ID_SHIFT;
5649 index_data[HC_INDEX_ETH_TX_CQ_CONS_COS2].flags |=
5650 SM_TX_ID << HC_INDEX_DATA_SM_ID_SHIFT;
5653 void bnx2x_init_sb(struct bnx2x *bp, dma_addr_t mapping, int vfid,
5654 u8 vf_valid, int fw_sb_id, int igu_sb_id)
5658 struct hc_status_block_data_e2 sb_data_e2;
5659 struct hc_status_block_data_e1x sb_data_e1x;
5660 struct hc_status_block_sm *hc_sm_p;
5664 if (CHIP_INT_MODE_IS_BC(bp))
5665 igu_seg_id = HC_SEG_ACCESS_NORM;
5667 igu_seg_id = IGU_SEG_ACCESS_NORM;
5669 bnx2x_zero_fp_sb(bp, fw_sb_id);
5671 if (!CHIP_IS_E1x(bp)) {
5672 memset(&sb_data_e2, 0, sizeof(struct hc_status_block_data_e2));
5673 sb_data_e2.common.state = SB_ENABLED;
5674 sb_data_e2.common.p_func.pf_id = BP_FUNC(bp);
5675 sb_data_e2.common.p_func.vf_id = vfid;
5676 sb_data_e2.common.p_func.vf_valid = vf_valid;
5677 sb_data_e2.common.p_func.vnic_id = BP_VN(bp);
5678 sb_data_e2.common.same_igu_sb_1b = true;
5679 sb_data_e2.common.host_sb_addr.hi = U64_HI(mapping);
5680 sb_data_e2.common.host_sb_addr.lo = U64_LO(mapping);
5681 hc_sm_p = sb_data_e2.common.state_machine;
5682 sb_data_p = (u32 *)&sb_data_e2;
5683 data_size = sizeof(struct hc_status_block_data_e2)/sizeof(u32);
5684 bnx2x_map_sb_state_machines(sb_data_e2.index_data);
5686 memset(&sb_data_e1x, 0,
5687 sizeof(struct hc_status_block_data_e1x));
5688 sb_data_e1x.common.state = SB_ENABLED;
5689 sb_data_e1x.common.p_func.pf_id = BP_FUNC(bp);
5690 sb_data_e1x.common.p_func.vf_id = 0xff;
5691 sb_data_e1x.common.p_func.vf_valid = false;
5692 sb_data_e1x.common.p_func.vnic_id = BP_VN(bp);
5693 sb_data_e1x.common.same_igu_sb_1b = true;
5694 sb_data_e1x.common.host_sb_addr.hi = U64_HI(mapping);
5695 sb_data_e1x.common.host_sb_addr.lo = U64_LO(mapping);
5696 hc_sm_p = sb_data_e1x.common.state_machine;
5697 sb_data_p = (u32 *)&sb_data_e1x;
5698 data_size = sizeof(struct hc_status_block_data_e1x)/sizeof(u32);
5699 bnx2x_map_sb_state_machines(sb_data_e1x.index_data);
5702 bnx2x_setup_ndsb_state_machine(&hc_sm_p[SM_RX_ID],
5703 igu_sb_id, igu_seg_id);
5704 bnx2x_setup_ndsb_state_machine(&hc_sm_p[SM_TX_ID],
5705 igu_sb_id, igu_seg_id);
5707 DP(NETIF_MSG_IFUP, "Init FW SB %d\n", fw_sb_id);
5709 /* write indices to HW - PCI guarantees endianity of regpairs */
5710 bnx2x_wr_fp_sb_data(bp, fw_sb_id, sb_data_p, data_size);
5713 static void bnx2x_update_coalesce_sb(struct bnx2x *bp, u8 fw_sb_id,
5714 u16 tx_usec, u16 rx_usec)
5716 bnx2x_update_coalesce_sb_index(bp, fw_sb_id, HC_INDEX_ETH_RX_CQ_CONS,
5718 bnx2x_update_coalesce_sb_index(bp, fw_sb_id,
5719 HC_INDEX_ETH_TX_CQ_CONS_COS0, false,
5721 bnx2x_update_coalesce_sb_index(bp, fw_sb_id,
5722 HC_INDEX_ETH_TX_CQ_CONS_COS1, false,
5724 bnx2x_update_coalesce_sb_index(bp, fw_sb_id,
5725 HC_INDEX_ETH_TX_CQ_CONS_COS2, false,
5729 static void bnx2x_init_def_sb(struct bnx2x *bp)
5731 struct host_sp_status_block *def_sb = bp->def_status_blk;
5732 dma_addr_t mapping = bp->def_status_blk_mapping;
5733 int igu_sp_sb_index;
5735 int port = BP_PORT(bp);
5736 int func = BP_FUNC(bp);
5737 int reg_offset, reg_offset_en5;
5740 struct hc_sp_status_block_data sp_sb_data;
5741 memset(&sp_sb_data, 0, sizeof(struct hc_sp_status_block_data));
5743 if (CHIP_INT_MODE_IS_BC(bp)) {
5744 igu_sp_sb_index = DEF_SB_IGU_ID;
5745 igu_seg_id = HC_SEG_ACCESS_DEF;
5747 igu_sp_sb_index = bp->igu_dsb_id;
5748 igu_seg_id = IGU_SEG_ACCESS_DEF;
5752 section = ((u64)mapping) + offsetof(struct host_sp_status_block,
5753 atten_status_block);
5754 def_sb->atten_status_block.status_block_id = igu_sp_sb_index;
5758 reg_offset = (port ? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_0 :
5759 MISC_REG_AEU_ENABLE1_FUNC_0_OUT_0);
5760 reg_offset_en5 = (port ? MISC_REG_AEU_ENABLE5_FUNC_1_OUT_0 :
5761 MISC_REG_AEU_ENABLE5_FUNC_0_OUT_0);
5762 for (index = 0; index < MAX_DYNAMIC_ATTN_GRPS; index++) {
5764 /* take care of sig[0]..sig[4] */
5765 for (sindex = 0; sindex < 4; sindex++)
5766 bp->attn_group[index].sig[sindex] =
5767 REG_RD(bp, reg_offset + sindex*0x4 + 0x10*index);
5769 if (!CHIP_IS_E1x(bp))
5771 * enable5 is separate from the rest of the registers,
5772 * and therefore the address skip is 4
5773 * and not 16 between the different groups
5775 bp->attn_group[index].sig[4] = REG_RD(bp,
5776 reg_offset_en5 + 0x4*index);
5778 bp->attn_group[index].sig[4] = 0;
5781 if (bp->common.int_block == INT_BLOCK_HC) {
5782 reg_offset = (port ? HC_REG_ATTN_MSG1_ADDR_L :
5783 HC_REG_ATTN_MSG0_ADDR_L);
5785 REG_WR(bp, reg_offset, U64_LO(section));
5786 REG_WR(bp, reg_offset + 4, U64_HI(section));
5787 } else if (!CHIP_IS_E1x(bp)) {
5788 REG_WR(bp, IGU_REG_ATTN_MSG_ADDR_L, U64_LO(section));
5789 REG_WR(bp, IGU_REG_ATTN_MSG_ADDR_H, U64_HI(section));
5792 section = ((u64)mapping) + offsetof(struct host_sp_status_block,
5795 bnx2x_zero_sp_sb(bp);
5797 /* PCI guarantees endianity of regpairs */
5798 sp_sb_data.state = SB_ENABLED;
5799 sp_sb_data.host_sb_addr.lo = U64_LO(section);
5800 sp_sb_data.host_sb_addr.hi = U64_HI(section);
5801 sp_sb_data.igu_sb_id = igu_sp_sb_index;
5802 sp_sb_data.igu_seg_id = igu_seg_id;
5803 sp_sb_data.p_func.pf_id = func;
5804 sp_sb_data.p_func.vnic_id = BP_VN(bp);
5805 sp_sb_data.p_func.vf_id = 0xff;
5807 bnx2x_wr_sp_sb_data(bp, &sp_sb_data);
5809 bnx2x_ack_sb(bp, bp->igu_dsb_id, USTORM_ID, 0, IGU_INT_ENABLE, 0);
5812 void bnx2x_update_coalesce(struct bnx2x *bp)
5816 for_each_eth_queue(bp, i)
5817 bnx2x_update_coalesce_sb(bp, bp->fp[i].fw_sb_id,
5818 bp->tx_ticks, bp->rx_ticks);
5821 static void bnx2x_init_sp_ring(struct bnx2x *bp)
5823 spin_lock_init(&bp->spq_lock);
5824 atomic_set(&bp->cq_spq_left, MAX_SPQ_PENDING);
5826 bp->spq_prod_idx = 0;
5827 bp->dsb_sp_prod = BNX2X_SP_DSB_INDEX;
5828 bp->spq_prod_bd = bp->spq;
5829 bp->spq_last_bd = bp->spq_prod_bd + MAX_SP_DESC_CNT;
5832 static void bnx2x_init_eq_ring(struct bnx2x *bp)
5835 for (i = 1; i <= NUM_EQ_PAGES; i++) {
5836 union event_ring_elem *elem =
5837 &bp->eq_ring[EQ_DESC_CNT_PAGE * i - 1];
5839 elem->next_page.addr.hi =
5840 cpu_to_le32(U64_HI(bp->eq_mapping +
5841 BCM_PAGE_SIZE * (i % NUM_EQ_PAGES)));
5842 elem->next_page.addr.lo =
5843 cpu_to_le32(U64_LO(bp->eq_mapping +
5844 BCM_PAGE_SIZE*(i % NUM_EQ_PAGES)));
5847 bp->eq_prod = NUM_EQ_DESC;
5848 bp->eq_cons_sb = BNX2X_EQ_INDEX;
5849 /* we want a warning message before it gets wrought... */
5850 atomic_set(&bp->eq_spq_left,
5851 min_t(int, MAX_SP_DESC_CNT - MAX_SPQ_PENDING, NUM_EQ_DESC) - 1);
5854 /* called with netif_addr_lock_bh() */
5855 int bnx2x_set_q_rx_mode(struct bnx2x *bp, u8 cl_id,
5856 unsigned long rx_mode_flags,
5857 unsigned long rx_accept_flags,
5858 unsigned long tx_accept_flags,
5859 unsigned long ramrod_flags)
5861 struct bnx2x_rx_mode_ramrod_params ramrod_param;
5864 memset(&ramrod_param, 0, sizeof(ramrod_param));
5866 /* Prepare ramrod parameters */
5867 ramrod_param.cid = 0;
5868 ramrod_param.cl_id = cl_id;
5869 ramrod_param.rx_mode_obj = &bp->rx_mode_obj;
5870 ramrod_param.func_id = BP_FUNC(bp);
5872 ramrod_param.pstate = &bp->sp_state;
5873 ramrod_param.state = BNX2X_FILTER_RX_MODE_PENDING;
5875 ramrod_param.rdata = bnx2x_sp(bp, rx_mode_rdata);
5876 ramrod_param.rdata_mapping = bnx2x_sp_mapping(bp, rx_mode_rdata);
5878 set_bit(BNX2X_FILTER_RX_MODE_PENDING, &bp->sp_state);
5880 ramrod_param.ramrod_flags = ramrod_flags;
5881 ramrod_param.rx_mode_flags = rx_mode_flags;
5883 ramrod_param.rx_accept_flags = rx_accept_flags;
5884 ramrod_param.tx_accept_flags = tx_accept_flags;
5886 rc = bnx2x_config_rx_mode(bp, &ramrod_param);
5888 BNX2X_ERR("Set rx_mode %d failed\n", bp->rx_mode);
5895 static int bnx2x_fill_accept_flags(struct bnx2x *bp, u32 rx_mode,
5896 unsigned long *rx_accept_flags,
5897 unsigned long *tx_accept_flags)
5899 /* Clear the flags first */
5900 *rx_accept_flags = 0;
5901 *tx_accept_flags = 0;
5904 case BNX2X_RX_MODE_NONE:
5906 * 'drop all' supersedes any accept flags that may have been
5907 * passed to the function.
5910 case BNX2X_RX_MODE_NORMAL:
5911 __set_bit(BNX2X_ACCEPT_UNICAST, rx_accept_flags);
5912 __set_bit(BNX2X_ACCEPT_MULTICAST, rx_accept_flags);
5913 __set_bit(BNX2X_ACCEPT_BROADCAST, rx_accept_flags);
5915 /* internal switching mode */
5916 __set_bit(BNX2X_ACCEPT_UNICAST, tx_accept_flags);
5917 __set_bit(BNX2X_ACCEPT_MULTICAST, tx_accept_flags);
5918 __set_bit(BNX2X_ACCEPT_BROADCAST, tx_accept_flags);
5921 case BNX2X_RX_MODE_ALLMULTI:
5922 __set_bit(BNX2X_ACCEPT_UNICAST, rx_accept_flags);
5923 __set_bit(BNX2X_ACCEPT_ALL_MULTICAST, rx_accept_flags);
5924 __set_bit(BNX2X_ACCEPT_BROADCAST, rx_accept_flags);
5926 /* internal switching mode */
5927 __set_bit(BNX2X_ACCEPT_UNICAST, tx_accept_flags);
5928 __set_bit(BNX2X_ACCEPT_ALL_MULTICAST, tx_accept_flags);
5929 __set_bit(BNX2X_ACCEPT_BROADCAST, tx_accept_flags);
5932 case BNX2X_RX_MODE_PROMISC:
5933 /* According to definition of SI mode, iface in promisc mode
5934 * should receive matched and unmatched (in resolution of port)
5937 __set_bit(BNX2X_ACCEPT_UNMATCHED, rx_accept_flags);
5938 __set_bit(BNX2X_ACCEPT_UNICAST, rx_accept_flags);
5939 __set_bit(BNX2X_ACCEPT_ALL_MULTICAST, rx_accept_flags);
5940 __set_bit(BNX2X_ACCEPT_BROADCAST, rx_accept_flags);
5942 /* internal switching mode */
5943 __set_bit(BNX2X_ACCEPT_ALL_MULTICAST, tx_accept_flags);
5944 __set_bit(BNX2X_ACCEPT_BROADCAST, tx_accept_flags);
5947 __set_bit(BNX2X_ACCEPT_ALL_UNICAST, tx_accept_flags);
5949 __set_bit(BNX2X_ACCEPT_UNICAST, tx_accept_flags);
5953 BNX2X_ERR("Unknown rx_mode: %d\n", rx_mode);
5957 /* Set ACCEPT_ANY_VLAN as we do not enable filtering by VLAN */
5958 if (bp->rx_mode != BNX2X_RX_MODE_NONE) {
5959 __set_bit(BNX2X_ACCEPT_ANY_VLAN, rx_accept_flags);
5960 __set_bit(BNX2X_ACCEPT_ANY_VLAN, tx_accept_flags);
5966 /* called with netif_addr_lock_bh() */
5967 int bnx2x_set_storm_rx_mode(struct bnx2x *bp)
5969 unsigned long rx_mode_flags = 0, ramrod_flags = 0;
5970 unsigned long rx_accept_flags = 0, tx_accept_flags = 0;
5974 /* Configure rx_mode of FCoE Queue */
5975 __set_bit(BNX2X_RX_MODE_FCOE_ETH, &rx_mode_flags);
5977 rc = bnx2x_fill_accept_flags(bp, bp->rx_mode, &rx_accept_flags,
5982 __set_bit(RAMROD_RX, &ramrod_flags);
5983 __set_bit(RAMROD_TX, &ramrod_flags);
5985 return bnx2x_set_q_rx_mode(bp, bp->fp->cl_id, rx_mode_flags,
5986 rx_accept_flags, tx_accept_flags,
5990 static void bnx2x_init_internal_common(struct bnx2x *bp)
5996 * In switch independent mode, the TSTORM needs to accept
5997 * packets that failed classification, since approximate match
5998 * mac addresses aren't written to NIG LLH
6000 REG_WR8(bp, BAR_TSTRORM_INTMEM +
6001 TSTORM_ACCEPT_CLASSIFY_FAILED_OFFSET, 2);
6002 else if (!CHIP_IS_E1(bp)) /* 57710 doesn't support MF */
6003 REG_WR8(bp, BAR_TSTRORM_INTMEM +
6004 TSTORM_ACCEPT_CLASSIFY_FAILED_OFFSET, 0);
6006 /* Zero this manually as its initialization is
6007 currently missing in the initTool */
6008 for (i = 0; i < (USTORM_AGG_DATA_SIZE >> 2); i++)
6009 REG_WR(bp, BAR_USTRORM_INTMEM +
6010 USTORM_AGG_DATA_OFFSET + i * 4, 0);
6011 if (!CHIP_IS_E1x(bp)) {
6012 REG_WR8(bp, BAR_CSTRORM_INTMEM + CSTORM_IGU_MODE_OFFSET,
6013 CHIP_INT_MODE_IS_BC(bp) ?
6014 HC_IGU_BC_MODE : HC_IGU_NBC_MODE);
6018 static void bnx2x_init_internal(struct bnx2x *bp, u32 load_code)
6020 switch (load_code) {
6021 case FW_MSG_CODE_DRV_LOAD_COMMON:
6022 case FW_MSG_CODE_DRV_LOAD_COMMON_CHIP:
6023 bnx2x_init_internal_common(bp);
6026 case FW_MSG_CODE_DRV_LOAD_PORT:
6030 case FW_MSG_CODE_DRV_LOAD_FUNCTION:
6031 /* internal memory per function is
6032 initialized inside bnx2x_pf_init */
6036 BNX2X_ERR("Unknown load_code (0x%x) from MCP\n", load_code);
6041 static inline u8 bnx2x_fp_igu_sb_id(struct bnx2x_fastpath *fp)
6043 return fp->bp->igu_base_sb + fp->index + CNIC_SUPPORT(fp->bp);
6046 static inline u8 bnx2x_fp_fw_sb_id(struct bnx2x_fastpath *fp)
6048 return fp->bp->base_fw_ndsb + fp->index + CNIC_SUPPORT(fp->bp);
6051 static u8 bnx2x_fp_cl_id(struct bnx2x_fastpath *fp)
6053 if (CHIP_IS_E1x(fp->bp))
6054 return BP_L_ID(fp->bp) + fp->index;
6055 else /* We want Client ID to be the same as IGU SB ID for 57712 */
6056 return bnx2x_fp_igu_sb_id(fp);
6059 static void bnx2x_init_eth_fp(struct bnx2x *bp, int fp_idx)
6061 struct bnx2x_fastpath *fp = &bp->fp[fp_idx];
6063 unsigned long q_type = 0;
6064 u32 cids[BNX2X_MULTI_TX_COS] = { 0 };
6065 fp->rx_queue = fp_idx;
6067 fp->cl_id = bnx2x_fp_cl_id(fp);
6068 fp->fw_sb_id = bnx2x_fp_fw_sb_id(fp);
6069 fp->igu_sb_id = bnx2x_fp_igu_sb_id(fp);
6070 /* qZone id equals to FW (per path) client id */
6071 fp->cl_qzone_id = bnx2x_fp_qzone_id(fp);
6074 fp->ustorm_rx_prods_offset = bnx2x_rx_ustorm_prods_offset(fp);
6076 /* Setup SB indices */
6077 fp->rx_cons_sb = BNX2X_RX_SB_INDEX;
6079 /* Configure Queue State object */
6080 __set_bit(BNX2X_Q_TYPE_HAS_RX, &q_type);
6081 __set_bit(BNX2X_Q_TYPE_HAS_TX, &q_type);
6083 BUG_ON(fp->max_cos > BNX2X_MULTI_TX_COS);
6086 for_each_cos_in_tx_queue(fp, cos) {
6087 bnx2x_init_txdata(bp, fp->txdata_ptr[cos],
6088 CID_COS_TO_TX_ONLY_CID(fp->cid, cos, bp),
6089 FP_COS_TO_TXQ(fp, cos, bp),
6090 BNX2X_TX_SB_INDEX_BASE + cos, fp);
6091 cids[cos] = fp->txdata_ptr[cos]->cid;
6094 /* nothing more for vf to do here */
6098 bnx2x_init_sb(bp, fp->status_blk_mapping, BNX2X_VF_ID_INVALID, false,
6099 fp->fw_sb_id, fp->igu_sb_id);
6100 bnx2x_update_fpsb_idx(fp);
6101 bnx2x_init_queue_obj(bp, &bnx2x_sp_obj(bp, fp).q_obj, fp->cl_id, cids,
6102 fp->max_cos, BP_FUNC(bp), bnx2x_sp(bp, q_rdata),
6103 bnx2x_sp_mapping(bp, q_rdata), q_type);
6106 * Configure classification DBs: Always enable Tx switching
6108 bnx2x_init_vlan_mac_fp_objs(fp, BNX2X_OBJ_TYPE_RX_TX);
6111 "queue[%d]: bnx2x_init_sb(%p,%p) cl_id %d fw_sb %d igu_sb %d\n",
6112 fp_idx, bp, fp->status_blk.e2_sb, fp->cl_id, fp->fw_sb_id,
6116 static void bnx2x_init_tx_ring_one(struct bnx2x_fp_txdata *txdata)
6120 for (i = 1; i <= NUM_TX_RINGS; i++) {
6121 struct eth_tx_next_bd *tx_next_bd =
6122 &txdata->tx_desc_ring[TX_DESC_CNT * i - 1].next_bd;
6124 tx_next_bd->addr_hi =
6125 cpu_to_le32(U64_HI(txdata->tx_desc_mapping +
6126 BCM_PAGE_SIZE*(i % NUM_TX_RINGS)));
6127 tx_next_bd->addr_lo =
6128 cpu_to_le32(U64_LO(txdata->tx_desc_mapping +
6129 BCM_PAGE_SIZE*(i % NUM_TX_RINGS)));
6132 *txdata->tx_cons_sb = cpu_to_le16(0);
6134 SET_FLAG(txdata->tx_db.data.header.header, DOORBELL_HDR_DB_TYPE, 1);
6135 txdata->tx_db.data.zero_fill1 = 0;
6136 txdata->tx_db.data.prod = 0;
6138 txdata->tx_pkt_prod = 0;
6139 txdata->tx_pkt_cons = 0;
6140 txdata->tx_bd_prod = 0;
6141 txdata->tx_bd_cons = 0;
6145 static void bnx2x_init_tx_rings_cnic(struct bnx2x *bp)
6149 for_each_tx_queue_cnic(bp, i)
6150 bnx2x_init_tx_ring_one(bp->fp[i].txdata_ptr[0]);
6153 static void bnx2x_init_tx_rings(struct bnx2x *bp)
6158 for_each_eth_queue(bp, i)
6159 for_each_cos_in_tx_queue(&bp->fp[i], cos)
6160 bnx2x_init_tx_ring_one(bp->fp[i].txdata_ptr[cos]);
6163 void bnx2x_nic_init_cnic(struct bnx2x *bp)
6166 bnx2x_init_fcoe_fp(bp);
6168 bnx2x_init_sb(bp, bp->cnic_sb_mapping,
6169 BNX2X_VF_ID_INVALID, false,
6170 bnx2x_cnic_fw_sb_id(bp), bnx2x_cnic_igu_sb_id(bp));
6172 /* ensure status block indices were read */
6174 bnx2x_init_rx_rings_cnic(bp);
6175 bnx2x_init_tx_rings_cnic(bp);
6182 void bnx2x_pre_irq_nic_init(struct bnx2x *bp)
6186 /* Setup NIC internals and enable interrupts */
6187 for_each_eth_queue(bp, i)
6188 bnx2x_init_eth_fp(bp, i);
6190 /* ensure status block indices were read */
6192 bnx2x_init_rx_rings(bp);
6193 bnx2x_init_tx_rings(bp);
6196 /* Initialize MOD_ABS interrupts */
6197 bnx2x_init_mod_abs_int(bp, &bp->link_vars, bp->common.chip_id,
6198 bp->common.shmem_base,
6199 bp->common.shmem2_base, BP_PORT(bp));
6201 /* initialize the default status block and sp ring */
6202 bnx2x_init_def_sb(bp);
6203 bnx2x_update_dsb_idx(bp);
6204 bnx2x_init_sp_ring(bp);
6206 bnx2x_memset_stats(bp);
6210 void bnx2x_post_irq_nic_init(struct bnx2x *bp, u32 load_code)
6212 bnx2x_init_eq_ring(bp);
6213 bnx2x_init_internal(bp, load_code);
6215 bnx2x_stats_init(bp);
6217 /* flush all before enabling interrupts */
6221 bnx2x_int_enable(bp);
6223 /* Check for SPIO5 */
6224 bnx2x_attn_int_deasserted0(bp,
6225 REG_RD(bp, MISC_REG_AEU_AFTER_INVERT_1_FUNC_0 + BP_PORT(bp)*4) &
6226 AEU_INPUTS_ATTN_BITS_SPIO5);
6229 /* gzip service functions */
6230 static int bnx2x_gunzip_init(struct bnx2x *bp)
6232 bp->gunzip_buf = dma_alloc_coherent(&bp->pdev->dev, FW_BUF_SIZE,
6233 &bp->gunzip_mapping, GFP_KERNEL);
6234 if (bp->gunzip_buf == NULL)
6237 bp->strm = kmalloc(sizeof(*bp->strm), GFP_KERNEL);
6238 if (bp->strm == NULL)
6241 bp->strm->workspace = vmalloc(zlib_inflate_workspacesize());
6242 if (bp->strm->workspace == NULL)
6252 dma_free_coherent(&bp->pdev->dev, FW_BUF_SIZE, bp->gunzip_buf,
6253 bp->gunzip_mapping);
6254 bp->gunzip_buf = NULL;
6257 BNX2X_ERR("Cannot allocate firmware buffer for un-compression\n");
6261 static void bnx2x_gunzip_end(struct bnx2x *bp)
6264 vfree(bp->strm->workspace);
6269 if (bp->gunzip_buf) {
6270 dma_free_coherent(&bp->pdev->dev, FW_BUF_SIZE, bp->gunzip_buf,
6271 bp->gunzip_mapping);
6272 bp->gunzip_buf = NULL;
6276 static int bnx2x_gunzip(struct bnx2x *bp, const u8 *zbuf, int len)
6280 /* check gzip header */
6281 if ((zbuf[0] != 0x1f) || (zbuf[1] != 0x8b) || (zbuf[2] != Z_DEFLATED)) {
6282 BNX2X_ERR("Bad gzip header\n");
6290 if (zbuf[3] & FNAME)
6291 while ((zbuf[n++] != 0) && (n < len));
6293 bp->strm->next_in = (typeof(bp->strm->next_in))zbuf + n;
6294 bp->strm->avail_in = len - n;
6295 bp->strm->next_out = bp->gunzip_buf;
6296 bp->strm->avail_out = FW_BUF_SIZE;
6298 rc = zlib_inflateInit2(bp->strm, -MAX_WBITS);
6302 rc = zlib_inflate(bp->strm, Z_FINISH);
6303 if ((rc != Z_OK) && (rc != Z_STREAM_END))
6304 netdev_err(bp->dev, "Firmware decompression error: %s\n",
6307 bp->gunzip_outlen = (FW_BUF_SIZE - bp->strm->avail_out);
6308 if (bp->gunzip_outlen & 0x3)
6310 "Firmware decompression error: gunzip_outlen (%d) not aligned\n",
6312 bp->gunzip_outlen >>= 2;
6314 zlib_inflateEnd(bp->strm);
6316 if (rc == Z_STREAM_END)
6322 /* nic load/unload */
6325 * General service functions
6328 /* send a NIG loopback debug packet */
6329 static void bnx2x_lb_pckt(struct bnx2x *bp)
6333 /* Ethernet source and destination addresses */
6334 wb_write[0] = 0x55555555;
6335 wb_write[1] = 0x55555555;
6336 wb_write[2] = 0x20; /* SOP */
6337 REG_WR_DMAE(bp, NIG_REG_DEBUG_PACKET_LB, wb_write, 3);
6339 /* NON-IP protocol */
6340 wb_write[0] = 0x09000000;
6341 wb_write[1] = 0x55555555;
6342 wb_write[2] = 0x10; /* EOP, eop_bvalid = 0 */
6343 REG_WR_DMAE(bp, NIG_REG_DEBUG_PACKET_LB, wb_write, 3);
6346 /* some of the internal memories
6347 * are not directly readable from the driver
6348 * to test them we send debug packets
6350 static int bnx2x_int_mem_test(struct bnx2x *bp)
6356 if (CHIP_REV_IS_FPGA(bp))
6358 else if (CHIP_REV_IS_EMUL(bp))
6363 /* Disable inputs of parser neighbor blocks */
6364 REG_WR(bp, TSDM_REG_ENABLE_IN1, 0x0);
6365 REG_WR(bp, TCM_REG_PRS_IFEN, 0x0);
6366 REG_WR(bp, CFC_REG_DEBUG0, 0x1);
6367 REG_WR(bp, NIG_REG_PRS_REQ_IN_EN, 0x0);
6369 /* Write 0 to parser credits for CFC search request */
6370 REG_WR(bp, PRS_REG_CFC_SEARCH_INITIAL_CREDIT, 0x0);
6372 /* send Ethernet packet */
6375 /* TODO do i reset NIG statistic? */
6376 /* Wait until NIG register shows 1 packet of size 0x10 */
6377 count = 1000 * factor;
6380 bnx2x_read_dmae(bp, NIG_REG_STAT2_BRB_OCTET, 2);
6381 val = *bnx2x_sp(bp, wb_data[0]);
6385 usleep_range(10000, 20000);
6389 BNX2X_ERR("NIG timeout val = 0x%x\n", val);
6393 /* Wait until PRS register shows 1 packet */
6394 count = 1000 * factor;
6396 val = REG_RD(bp, PRS_REG_NUM_OF_PACKETS);
6400 usleep_range(10000, 20000);
6404 BNX2X_ERR("PRS timeout val = 0x%x\n", val);
6408 /* Reset and init BRB, PRS */
6409 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_CLEAR, 0x03);
6411 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_SET, 0x03);
6413 bnx2x_init_block(bp, BLOCK_BRB1, PHASE_COMMON);
6414 bnx2x_init_block(bp, BLOCK_PRS, PHASE_COMMON);
6416 DP(NETIF_MSG_HW, "part2\n");
6418 /* Disable inputs of parser neighbor blocks */
6419 REG_WR(bp, TSDM_REG_ENABLE_IN1, 0x0);
6420 REG_WR(bp, TCM_REG_PRS_IFEN, 0x0);
6421 REG_WR(bp, CFC_REG_DEBUG0, 0x1);
6422 REG_WR(bp, NIG_REG_PRS_REQ_IN_EN, 0x0);
6424 /* Write 0 to parser credits for CFC search request */
6425 REG_WR(bp, PRS_REG_CFC_SEARCH_INITIAL_CREDIT, 0x0);
6427 /* send 10 Ethernet packets */
6428 for (i = 0; i < 10; i++)
6431 /* Wait until NIG register shows 10 + 1
6432 packets of size 11*0x10 = 0xb0 */
6433 count = 1000 * factor;
6436 bnx2x_read_dmae(bp, NIG_REG_STAT2_BRB_OCTET, 2);
6437 val = *bnx2x_sp(bp, wb_data[0]);
6441 usleep_range(10000, 20000);
6445 BNX2X_ERR("NIG timeout val = 0x%x\n", val);
6449 /* Wait until PRS register shows 2 packets */
6450 val = REG_RD(bp, PRS_REG_NUM_OF_PACKETS);
6452 BNX2X_ERR("PRS timeout val = 0x%x\n", val);
6454 /* Write 1 to parser credits for CFC search request */
6455 REG_WR(bp, PRS_REG_CFC_SEARCH_INITIAL_CREDIT, 0x1);
6457 /* Wait until PRS register shows 3 packets */
6458 msleep(10 * factor);
6459 /* Wait until NIG register shows 1 packet of size 0x10 */
6460 val = REG_RD(bp, PRS_REG_NUM_OF_PACKETS);
6462 BNX2X_ERR("PRS timeout val = 0x%x\n", val);
6464 /* clear NIG EOP FIFO */
6465 for (i = 0; i < 11; i++)
6466 REG_RD(bp, NIG_REG_INGRESS_EOP_LB_FIFO);
6467 val = REG_RD(bp, NIG_REG_INGRESS_EOP_LB_EMPTY);
6469 BNX2X_ERR("clear of NIG failed\n");
6473 /* Reset and init BRB, PRS, NIG */
6474 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_CLEAR, 0x03);
6476 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_SET, 0x03);
6478 bnx2x_init_block(bp, BLOCK_BRB1, PHASE_COMMON);
6479 bnx2x_init_block(bp, BLOCK_PRS, PHASE_COMMON);
6480 if (!CNIC_SUPPORT(bp))
6482 REG_WR(bp, PRS_REG_NIC_MODE, 1);
6484 /* Enable inputs of parser neighbor blocks */
6485 REG_WR(bp, TSDM_REG_ENABLE_IN1, 0x7fffffff);
6486 REG_WR(bp, TCM_REG_PRS_IFEN, 0x1);
6487 REG_WR(bp, CFC_REG_DEBUG0, 0x0);
6488 REG_WR(bp, NIG_REG_PRS_REQ_IN_EN, 0x1);
6490 DP(NETIF_MSG_HW, "done\n");
6495 static void bnx2x_enable_blocks_attention(struct bnx2x *bp)
6499 REG_WR(bp, PXP_REG_PXP_INT_MASK_0, 0);
6500 if (!CHIP_IS_E1x(bp))
6501 REG_WR(bp, PXP_REG_PXP_INT_MASK_1, 0x40);
6503 REG_WR(bp, PXP_REG_PXP_INT_MASK_1, 0);
6504 REG_WR(bp, DORQ_REG_DORQ_INT_MASK, 0);
6505 REG_WR(bp, CFC_REG_CFC_INT_MASK, 0);
6507 * mask read length error interrupts in brb for parser
6508 * (parsing unit and 'checksum and crc' unit)
6509 * these errors are legal (PU reads fixed length and CAC can cause
6510 * read length error on truncated packets)
6512 REG_WR(bp, BRB1_REG_BRB1_INT_MASK, 0xFC00);
6513 REG_WR(bp, QM_REG_QM_INT_MASK, 0);
6514 REG_WR(bp, TM_REG_TM_INT_MASK, 0);
6515 REG_WR(bp, XSDM_REG_XSDM_INT_MASK_0, 0);
6516 REG_WR(bp, XSDM_REG_XSDM_INT_MASK_1, 0);
6517 REG_WR(bp, XCM_REG_XCM_INT_MASK, 0);
6518 /* REG_WR(bp, XSEM_REG_XSEM_INT_MASK_0, 0); */
6519 /* REG_WR(bp, XSEM_REG_XSEM_INT_MASK_1, 0); */
6520 REG_WR(bp, USDM_REG_USDM_INT_MASK_0, 0);
6521 REG_WR(bp, USDM_REG_USDM_INT_MASK_1, 0);
6522 REG_WR(bp, UCM_REG_UCM_INT_MASK, 0);
6523 /* REG_WR(bp, USEM_REG_USEM_INT_MASK_0, 0); */
6524 /* REG_WR(bp, USEM_REG_USEM_INT_MASK_1, 0); */
6525 REG_WR(bp, GRCBASE_UPB + PB_REG_PB_INT_MASK, 0);
6526 REG_WR(bp, CSDM_REG_CSDM_INT_MASK_0, 0);
6527 REG_WR(bp, CSDM_REG_CSDM_INT_MASK_1, 0);
6528 REG_WR(bp, CCM_REG_CCM_INT_MASK, 0);
6529 /* REG_WR(bp, CSEM_REG_CSEM_INT_MASK_0, 0); */
6530 /* REG_WR(bp, CSEM_REG_CSEM_INT_MASK_1, 0); */
6532 val = PXP2_PXP2_INT_MASK_0_REG_PGL_CPL_AFT |
6533 PXP2_PXP2_INT_MASK_0_REG_PGL_CPL_OF |
6534 PXP2_PXP2_INT_MASK_0_REG_PGL_PCIE_ATTN;
6535 if (!CHIP_IS_E1x(bp))
6536 val |= PXP2_PXP2_INT_MASK_0_REG_PGL_READ_BLOCKED |
6537 PXP2_PXP2_INT_MASK_0_REG_PGL_WRITE_BLOCKED;
6538 REG_WR(bp, PXP2_REG_PXP2_INT_MASK_0, val);
6540 REG_WR(bp, TSDM_REG_TSDM_INT_MASK_0, 0);
6541 REG_WR(bp, TSDM_REG_TSDM_INT_MASK_1, 0);
6542 REG_WR(bp, TCM_REG_TCM_INT_MASK, 0);
6543 /* REG_WR(bp, TSEM_REG_TSEM_INT_MASK_0, 0); */
6545 if (!CHIP_IS_E1x(bp))
6546 /* enable VFC attentions: bits 11 and 12, bits 31:13 reserved */
6547 REG_WR(bp, TSEM_REG_TSEM_INT_MASK_1, 0x07ff);
6549 REG_WR(bp, CDU_REG_CDU_INT_MASK, 0);
6550 REG_WR(bp, DMAE_REG_DMAE_INT_MASK, 0);
6551 /* REG_WR(bp, MISC_REG_MISC_INT_MASK, 0); */
6552 REG_WR(bp, PBF_REG_PBF_INT_MASK, 0x18); /* bit 3,4 masked */
6555 static void bnx2x_reset_common(struct bnx2x *bp)
6560 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_CLEAR,
6563 if (CHIP_IS_E3(bp)) {
6564 val |= MISC_REGISTERS_RESET_REG_2_MSTAT0;
6565 val |= MISC_REGISTERS_RESET_REG_2_MSTAT1;
6568 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR, val);
6571 static void bnx2x_setup_dmae(struct bnx2x *bp)
6574 spin_lock_init(&bp->dmae_lock);
6577 static void bnx2x_init_pxp(struct bnx2x *bp)
6580 int r_order, w_order;
6582 pcie_capability_read_word(bp->pdev, PCI_EXP_DEVCTL, &devctl);
6583 DP(NETIF_MSG_HW, "read 0x%x from devctl\n", devctl);
6584 w_order = ((devctl & PCI_EXP_DEVCTL_PAYLOAD) >> 5);
6586 r_order = ((devctl & PCI_EXP_DEVCTL_READRQ) >> 12);
6588 DP(NETIF_MSG_HW, "force read order to %d\n", bp->mrrs);
6592 bnx2x_init_pxp_arb(bp, r_order, w_order);
6595 static void bnx2x_setup_fan_failure_detection(struct bnx2x *bp)
6605 val = SHMEM_RD(bp, dev_info.shared_hw_config.config2) &
6606 SHARED_HW_CFG_FAN_FAILURE_MASK;
6608 if (val == SHARED_HW_CFG_FAN_FAILURE_ENABLED)
6612 * The fan failure mechanism is usually related to the PHY type since
6613 * the power consumption of the board is affected by the PHY. Currently,
6614 * fan is required for most designs with SFX7101, BCM8727 and BCM8481.
6616 else if (val == SHARED_HW_CFG_FAN_FAILURE_PHY_TYPE)
6617 for (port = PORT_0; port < PORT_MAX; port++) {
6619 bnx2x_fan_failure_det_req(
6621 bp->common.shmem_base,
6622 bp->common.shmem2_base,
6626 DP(NETIF_MSG_HW, "fan detection setting: %d\n", is_required);
6628 if (is_required == 0)
6631 /* Fan failure is indicated by SPIO 5 */
6632 bnx2x_set_spio(bp, MISC_SPIO_SPIO5, MISC_SPIO_INPUT_HI_Z);
6634 /* set to active low mode */
6635 val = REG_RD(bp, MISC_REG_SPIO_INT);
6636 val |= (MISC_SPIO_SPIO5 << MISC_SPIO_INT_OLD_SET_POS);
6637 REG_WR(bp, MISC_REG_SPIO_INT, val);
6639 /* enable interrupt to signal the IGU */
6640 val = REG_RD(bp, MISC_REG_SPIO_EVENT_EN);
6641 val |= MISC_SPIO_SPIO5;
6642 REG_WR(bp, MISC_REG_SPIO_EVENT_EN, val);
6645 void bnx2x_pf_disable(struct bnx2x *bp)
6647 u32 val = REG_RD(bp, IGU_REG_PF_CONFIGURATION);
6648 val &= ~IGU_PF_CONF_FUNC_EN;
6650 REG_WR(bp, IGU_REG_PF_CONFIGURATION, val);
6651 REG_WR(bp, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, 0);
6652 REG_WR(bp, CFC_REG_WEAK_ENABLE_PF, 0);
6655 static void bnx2x__common_init_phy(struct bnx2x *bp)
6657 u32 shmem_base[2], shmem2_base[2];
6658 /* Avoid common init in case MFW supports LFA */
6659 if (SHMEM2_RD(bp, size) >
6660 (u32)offsetof(struct shmem2_region, lfa_host_addr[BP_PORT(bp)]))
6662 shmem_base[0] = bp->common.shmem_base;
6663 shmem2_base[0] = bp->common.shmem2_base;
6664 if (!CHIP_IS_E1x(bp)) {
6666 SHMEM2_RD(bp, other_shmem_base_addr);
6668 SHMEM2_RD(bp, other_shmem2_base_addr);
6670 bnx2x_acquire_phy_lock(bp);
6671 bnx2x_common_init_phy(bp, shmem_base, shmem2_base,
6672 bp->common.chip_id);
6673 bnx2x_release_phy_lock(bp);
6677 * bnx2x_init_hw_common - initialize the HW at the COMMON phase.
6679 * @bp: driver handle
6681 static int bnx2x_init_hw_common(struct bnx2x *bp)
6685 DP(NETIF_MSG_HW, "starting common init func %d\n", BP_ABS_FUNC(bp));
6688 * take the RESET lock to protect undi_unload flow from accessing
6689 * registers while we're resetting the chip
6691 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_RESET);
6693 bnx2x_reset_common(bp);
6694 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_SET, 0xffffffff);
6697 if (CHIP_IS_E3(bp)) {
6698 val |= MISC_REGISTERS_RESET_REG_2_MSTAT0;
6699 val |= MISC_REGISTERS_RESET_REG_2_MSTAT1;
6701 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_SET, val);
6703 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_RESET);
6705 bnx2x_init_block(bp, BLOCK_MISC, PHASE_COMMON);
6707 if (!CHIP_IS_E1x(bp)) {
6711 * 4-port mode or 2-port mode we need to turn of master-enable
6712 * for everyone, after that, turn it back on for self.
6713 * so, we disregard multi-function or not, and always disable
6714 * for all functions on the given path, this means 0,2,4,6 for
6715 * path 0 and 1,3,5,7 for path 1
6717 for (abs_func_id = BP_PATH(bp);
6718 abs_func_id < E2_FUNC_MAX*2; abs_func_id += 2) {
6719 if (abs_func_id == BP_ABS_FUNC(bp)) {
6721 PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER,
6726 bnx2x_pretend_func(bp, abs_func_id);
6727 /* clear pf enable */
6728 bnx2x_pf_disable(bp);
6729 bnx2x_pretend_func(bp, BP_ABS_FUNC(bp));
6733 bnx2x_init_block(bp, BLOCK_PXP, PHASE_COMMON);
6734 if (CHIP_IS_E1(bp)) {
6735 /* enable HW interrupt from PXP on USDM overflow
6736 bit 16 on INT_MASK_0 */
6737 REG_WR(bp, PXP_REG_PXP_INT_MASK_0, 0);
6740 bnx2x_init_block(bp, BLOCK_PXP2, PHASE_COMMON);
6744 REG_WR(bp, PXP2_REG_RQ_QM_ENDIAN_M, 1);
6745 REG_WR(bp, PXP2_REG_RQ_TM_ENDIAN_M, 1);
6746 REG_WR(bp, PXP2_REG_RQ_SRC_ENDIAN_M, 1);
6747 REG_WR(bp, PXP2_REG_RQ_CDU_ENDIAN_M, 1);
6748 REG_WR(bp, PXP2_REG_RQ_DBG_ENDIAN_M, 1);
6749 /* make sure this value is 0 */
6750 REG_WR(bp, PXP2_REG_RQ_HC_ENDIAN_M, 0);
6752 /* REG_WR(bp, PXP2_REG_RD_PBF_SWAP_MODE, 1); */
6753 REG_WR(bp, PXP2_REG_RD_QM_SWAP_MODE, 1);
6754 REG_WR(bp, PXP2_REG_RD_TM_SWAP_MODE, 1);
6755 REG_WR(bp, PXP2_REG_RD_SRC_SWAP_MODE, 1);
6756 REG_WR(bp, PXP2_REG_RD_CDURD_SWAP_MODE, 1);
6759 bnx2x_ilt_init_page_size(bp, INITOP_SET);
6761 if (CHIP_REV_IS_FPGA(bp) && CHIP_IS_E1H(bp))
6762 REG_WR(bp, PXP2_REG_PGL_TAGS_LIMIT, 0x1);
6764 /* let the HW do it's magic ... */
6766 /* finish PXP init */
6767 val = REG_RD(bp, PXP2_REG_RQ_CFG_DONE);
6769 BNX2X_ERR("PXP2 CFG failed\n");
6772 val = REG_RD(bp, PXP2_REG_RD_INIT_DONE);
6774 BNX2X_ERR("PXP2 RD_INIT failed\n");
6778 /* Timers bug workaround E2 only. We need to set the entire ILT to
6779 * have entries with value "0" and valid bit on.
6780 * This needs to be done by the first PF that is loaded in a path
6781 * (i.e. common phase)
6783 if (!CHIP_IS_E1x(bp)) {
6784 /* In E2 there is a bug in the timers block that can cause function 6 / 7
6785 * (i.e. vnic3) to start even if it is marked as "scan-off".
6786 * This occurs when a different function (func2,3) is being marked
6787 * as "scan-off". Real-life scenario for example: if a driver is being
6788 * load-unloaded while func6,7 are down. This will cause the timer to access
6789 * the ilt, translate to a logical address and send a request to read/write.
6790 * Since the ilt for the function that is down is not valid, this will cause
6791 * a translation error which is unrecoverable.
6792 * The Workaround is intended to make sure that when this happens nothing fatal
6793 * will occur. The workaround:
6794 * 1. First PF driver which loads on a path will:
6795 * a. After taking the chip out of reset, by using pretend,
6796 * it will write "0" to the following registers of
6798 * REG_WR(pdev, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, 0);
6799 * REG_WR(pdev, CFC_REG_WEAK_ENABLE_PF,0);
6800 * REG_WR(pdev, CFC_REG_STRONG_ENABLE_PF,0);
6801 * And for itself it will write '1' to
6802 * PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER to enable
6803 * dmae-operations (writing to pram for example.)
6804 * note: can be done for only function 6,7 but cleaner this
6806 * b. Write zero+valid to the entire ILT.
6807 * c. Init the first_timers_ilt_entry, last_timers_ilt_entry of
6808 * VNIC3 (of that port). The range allocated will be the
6809 * entire ILT. This is needed to prevent ILT range error.
6810 * 2. Any PF driver load flow:
6811 * a. ILT update with the physical addresses of the allocated
6813 * b. Wait 20msec. - note that this timeout is needed to make
6814 * sure there are no requests in one of the PXP internal
6815 * queues with "old" ILT addresses.
6816 * c. PF enable in the PGLC.
6817 * d. Clear the was_error of the PF in the PGLC. (could have
6818 * occurred while driver was down)
6819 * e. PF enable in the CFC (WEAK + STRONG)
6820 * f. Timers scan enable
6821 * 3. PF driver unload flow:
6822 * a. Clear the Timers scan_en.
6823 * b. Polling for scan_on=0 for that PF.
6824 * c. Clear the PF enable bit in the PXP.
6825 * d. Clear the PF enable in the CFC (WEAK + STRONG)
6826 * e. Write zero+valid to all ILT entries (The valid bit must
6828 * f. If this is VNIC 3 of a port then also init
6829 * first_timers_ilt_entry to zero and last_timers_ilt_entry
6830 * to the last entry in the ILT.
6833 * Currently the PF error in the PGLC is non recoverable.
6834 * In the future the there will be a recovery routine for this error.
6835 * Currently attention is masked.
6836 * Having an MCP lock on the load/unload process does not guarantee that
6837 * there is no Timer disable during Func6/7 enable. This is because the
6838 * Timers scan is currently being cleared by the MCP on FLR.
6839 * Step 2.d can be done only for PF6/7 and the driver can also check if
6840 * there is error before clearing it. But the flow above is simpler and
6842 * All ILT entries are written by zero+valid and not just PF6/7
6843 * ILT entries since in the future the ILT entries allocation for
6844 * PF-s might be dynamic.
6846 struct ilt_client_info ilt_cli;
6847 struct bnx2x_ilt ilt;
6848 memset(&ilt_cli, 0, sizeof(struct ilt_client_info));
6849 memset(&ilt, 0, sizeof(struct bnx2x_ilt));
6851 /* initialize dummy TM client */
6853 ilt_cli.end = ILT_NUM_PAGE_ENTRIES - 1;
6854 ilt_cli.client_num = ILT_CLIENT_TM;
6856 /* Step 1: set zeroes to all ilt page entries with valid bit on
6857 * Step 2: set the timers first/last ilt entry to point
6858 * to the entire range to prevent ILT range error for 3rd/4th
6859 * vnic (this code assumes existence of the vnic)
6861 * both steps performed by call to bnx2x_ilt_client_init_op()
6862 * with dummy TM client
6864 * we must use pretend since PXP2_REG_RQ_##blk##_FIRST_ILT
6865 * and his brother are split registers
6867 bnx2x_pretend_func(bp, (BP_PATH(bp) + 6));
6868 bnx2x_ilt_client_init_op_ilt(bp, &ilt, &ilt_cli, INITOP_CLEAR);
6869 bnx2x_pretend_func(bp, BP_ABS_FUNC(bp));
6871 REG_WR(bp, PXP2_REG_RQ_DRAM_ALIGN, BNX2X_PXP_DRAM_ALIGN);
6872 REG_WR(bp, PXP2_REG_RQ_DRAM_ALIGN_RD, BNX2X_PXP_DRAM_ALIGN);
6873 REG_WR(bp, PXP2_REG_RQ_DRAM_ALIGN_SEL, 1);
6876 REG_WR(bp, PXP2_REG_RQ_DISABLE_INPUTS, 0);
6877 REG_WR(bp, PXP2_REG_RD_DISABLE_INPUTS, 0);
6879 if (!CHIP_IS_E1x(bp)) {
6880 int factor = CHIP_REV_IS_EMUL(bp) ? 1000 :
6881 (CHIP_REV_IS_FPGA(bp) ? 400 : 0);
6882 bnx2x_init_block(bp, BLOCK_PGLUE_B, PHASE_COMMON);
6884 bnx2x_init_block(bp, BLOCK_ATC, PHASE_COMMON);
6886 /* let the HW do it's magic ... */
6889 val = REG_RD(bp, ATC_REG_ATC_INIT_DONE);
6890 } while (factor-- && (val != 1));
6893 BNX2X_ERR("ATC_INIT failed\n");
6898 bnx2x_init_block(bp, BLOCK_DMAE, PHASE_COMMON);
6900 bnx2x_iov_init_dmae(bp);
6902 /* clean the DMAE memory */
6904 bnx2x_init_fill(bp, TSEM_REG_PRAM, 0, 8, 1);
6906 bnx2x_init_block(bp, BLOCK_TCM, PHASE_COMMON);
6908 bnx2x_init_block(bp, BLOCK_UCM, PHASE_COMMON);
6910 bnx2x_init_block(bp, BLOCK_CCM, PHASE_COMMON);
6912 bnx2x_init_block(bp, BLOCK_XCM, PHASE_COMMON);
6914 bnx2x_read_dmae(bp, XSEM_REG_PASSIVE_BUFFER, 3);
6915 bnx2x_read_dmae(bp, CSEM_REG_PASSIVE_BUFFER, 3);
6916 bnx2x_read_dmae(bp, TSEM_REG_PASSIVE_BUFFER, 3);
6917 bnx2x_read_dmae(bp, USEM_REG_PASSIVE_BUFFER, 3);
6919 bnx2x_init_block(bp, BLOCK_QM, PHASE_COMMON);
6921 /* QM queues pointers table */
6922 bnx2x_qm_init_ptr_table(bp, bp->qm_cid_count, INITOP_SET);
6924 /* soft reset pulse */
6925 REG_WR(bp, QM_REG_SOFT_RESET, 1);
6926 REG_WR(bp, QM_REG_SOFT_RESET, 0);
6928 if (CNIC_SUPPORT(bp))
6929 bnx2x_init_block(bp, BLOCK_TM, PHASE_COMMON);
6931 bnx2x_init_block(bp, BLOCK_DORQ, PHASE_COMMON);
6933 if (!CHIP_REV_IS_SLOW(bp))
6934 /* enable hw interrupt from doorbell Q */
6935 REG_WR(bp, DORQ_REG_DORQ_INT_MASK, 0);
6937 bnx2x_init_block(bp, BLOCK_BRB1, PHASE_COMMON);
6939 bnx2x_init_block(bp, BLOCK_PRS, PHASE_COMMON);
6940 REG_WR(bp, PRS_REG_A_PRSU_20, 0xf);
6942 if (!CHIP_IS_E1(bp))
6943 REG_WR(bp, PRS_REG_E1HOV_MODE, bp->path_has_ovlan);
6945 if (!CHIP_IS_E1x(bp) && !CHIP_IS_E3B0(bp)) {
6946 if (IS_MF_AFEX(bp)) {
6947 /* configure that VNTag and VLAN headers must be
6948 * received in afex mode
6950 REG_WR(bp, PRS_REG_HDRS_AFTER_BASIC, 0xE);
6951 REG_WR(bp, PRS_REG_MUST_HAVE_HDRS, 0xA);
6952 REG_WR(bp, PRS_REG_HDRS_AFTER_TAG_0, 0x6);
6953 REG_WR(bp, PRS_REG_TAG_ETHERTYPE_0, 0x8926);
6954 REG_WR(bp, PRS_REG_TAG_LEN_0, 0x4);
6956 /* Bit-map indicating which L2 hdrs may appear
6957 * after the basic Ethernet header
6959 REG_WR(bp, PRS_REG_HDRS_AFTER_BASIC,
6960 bp->path_has_ovlan ? 7 : 6);
6964 bnx2x_init_block(bp, BLOCK_TSDM, PHASE_COMMON);
6965 bnx2x_init_block(bp, BLOCK_CSDM, PHASE_COMMON);
6966 bnx2x_init_block(bp, BLOCK_USDM, PHASE_COMMON);
6967 bnx2x_init_block(bp, BLOCK_XSDM, PHASE_COMMON);
6969 if (!CHIP_IS_E1x(bp)) {
6970 /* reset VFC memories */
6971 REG_WR(bp, TSEM_REG_FAST_MEMORY + VFC_REG_MEMORIES_RST,
6972 VFC_MEMORIES_RST_REG_CAM_RST |
6973 VFC_MEMORIES_RST_REG_RAM_RST);
6974 REG_WR(bp, XSEM_REG_FAST_MEMORY + VFC_REG_MEMORIES_RST,
6975 VFC_MEMORIES_RST_REG_CAM_RST |
6976 VFC_MEMORIES_RST_REG_RAM_RST);
6981 bnx2x_init_block(bp, BLOCK_TSEM, PHASE_COMMON);
6982 bnx2x_init_block(bp, BLOCK_USEM, PHASE_COMMON);
6983 bnx2x_init_block(bp, BLOCK_CSEM, PHASE_COMMON);
6984 bnx2x_init_block(bp, BLOCK_XSEM, PHASE_COMMON);
6987 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_CLEAR,
6989 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_SET,
6992 bnx2x_init_block(bp, BLOCK_UPB, PHASE_COMMON);
6993 bnx2x_init_block(bp, BLOCK_XPB, PHASE_COMMON);
6994 bnx2x_init_block(bp, BLOCK_PBF, PHASE_COMMON);
6996 if (!CHIP_IS_E1x(bp)) {
6997 if (IS_MF_AFEX(bp)) {
6998 /* configure that VNTag and VLAN headers must be
7001 REG_WR(bp, PBF_REG_HDRS_AFTER_BASIC, 0xE);
7002 REG_WR(bp, PBF_REG_MUST_HAVE_HDRS, 0xA);
7003 REG_WR(bp, PBF_REG_HDRS_AFTER_TAG_0, 0x6);
7004 REG_WR(bp, PBF_REG_TAG_ETHERTYPE_0, 0x8926);
7005 REG_WR(bp, PBF_REG_TAG_LEN_0, 0x4);
7007 REG_WR(bp, PBF_REG_HDRS_AFTER_BASIC,
7008 bp->path_has_ovlan ? 7 : 6);
7012 REG_WR(bp, SRC_REG_SOFT_RST, 1);
7014 bnx2x_init_block(bp, BLOCK_SRC, PHASE_COMMON);
7016 if (CNIC_SUPPORT(bp)) {
7017 REG_WR(bp, SRC_REG_KEYSEARCH_0, 0x63285672);
7018 REG_WR(bp, SRC_REG_KEYSEARCH_1, 0x24b8f2cc);
7019 REG_WR(bp, SRC_REG_KEYSEARCH_2, 0x223aef9b);
7020 REG_WR(bp, SRC_REG_KEYSEARCH_3, 0x26001e3a);
7021 REG_WR(bp, SRC_REG_KEYSEARCH_4, 0x7ae91116);
7022 REG_WR(bp, SRC_REG_KEYSEARCH_5, 0x5ce5230b);
7023 REG_WR(bp, SRC_REG_KEYSEARCH_6, 0x298d8adf);
7024 REG_WR(bp, SRC_REG_KEYSEARCH_7, 0x6eb0ff09);
7025 REG_WR(bp, SRC_REG_KEYSEARCH_8, 0x1830f82f);
7026 REG_WR(bp, SRC_REG_KEYSEARCH_9, 0x01e46be7);
7028 REG_WR(bp, SRC_REG_SOFT_RST, 0);
7030 if (sizeof(union cdu_context) != 1024)
7031 /* we currently assume that a context is 1024 bytes */
7032 dev_alert(&bp->pdev->dev,
7033 "please adjust the size of cdu_context(%ld)\n",
7034 (long)sizeof(union cdu_context));
7036 bnx2x_init_block(bp, BLOCK_CDU, PHASE_COMMON);
7037 val = (4 << 24) + (0 << 12) + 1024;
7038 REG_WR(bp, CDU_REG_CDU_GLOBAL_PARAMS, val);
7040 bnx2x_init_block(bp, BLOCK_CFC, PHASE_COMMON);
7041 REG_WR(bp, CFC_REG_INIT_REG, 0x7FF);
7042 /* enable context validation interrupt from CFC */
7043 REG_WR(bp, CFC_REG_CFC_INT_MASK, 0);
7045 /* set the thresholds to prevent CFC/CDU race */
7046 REG_WR(bp, CFC_REG_DEBUG0, 0x20020000);
7048 bnx2x_init_block(bp, BLOCK_HC, PHASE_COMMON);
7050 if (!CHIP_IS_E1x(bp) && BP_NOMCP(bp))
7051 REG_WR(bp, IGU_REG_RESET_MEMORIES, 0x36);
7053 bnx2x_init_block(bp, BLOCK_IGU, PHASE_COMMON);
7054 bnx2x_init_block(bp, BLOCK_MISC_AEU, PHASE_COMMON);
7056 /* Reset PCIE errors for debug */
7057 REG_WR(bp, 0x2814, 0xffffffff);
7058 REG_WR(bp, 0x3820, 0xffffffff);
7060 if (!CHIP_IS_E1x(bp)) {
7061 REG_WR(bp, PCICFG_OFFSET + PXPCS_TL_CONTROL_5,
7062 (PXPCS_TL_CONTROL_5_ERR_UNSPPORT1 |
7063 PXPCS_TL_CONTROL_5_ERR_UNSPPORT));
7064 REG_WR(bp, PCICFG_OFFSET + PXPCS_TL_FUNC345_STAT,
7065 (PXPCS_TL_FUNC345_STAT_ERR_UNSPPORT4 |
7066 PXPCS_TL_FUNC345_STAT_ERR_UNSPPORT3 |
7067 PXPCS_TL_FUNC345_STAT_ERR_UNSPPORT2));
7068 REG_WR(bp, PCICFG_OFFSET + PXPCS_TL_FUNC678_STAT,
7069 (PXPCS_TL_FUNC678_STAT_ERR_UNSPPORT7 |
7070 PXPCS_TL_FUNC678_STAT_ERR_UNSPPORT6 |
7071 PXPCS_TL_FUNC678_STAT_ERR_UNSPPORT5));
7074 bnx2x_init_block(bp, BLOCK_NIG, PHASE_COMMON);
7075 if (!CHIP_IS_E1(bp)) {
7076 /* in E3 this done in per-port section */
7077 if (!CHIP_IS_E3(bp))
7078 REG_WR(bp, NIG_REG_LLH_MF_MODE, IS_MF(bp));
7080 if (CHIP_IS_E1H(bp))
7081 /* not applicable for E2 (and above ...) */
7082 REG_WR(bp, NIG_REG_LLH_E1HOV_MODE, IS_MF_SD(bp));
7084 if (CHIP_REV_IS_SLOW(bp))
7087 /* finish CFC init */
7088 val = reg_poll(bp, CFC_REG_LL_INIT_DONE, 1, 100, 10);
7090 BNX2X_ERR("CFC LL_INIT failed\n");
7093 val = reg_poll(bp, CFC_REG_AC_INIT_DONE, 1, 100, 10);
7095 BNX2X_ERR("CFC AC_INIT failed\n");
7098 val = reg_poll(bp, CFC_REG_CAM_INIT_DONE, 1, 100, 10);
7100 BNX2X_ERR("CFC CAM_INIT failed\n");
7103 REG_WR(bp, CFC_REG_DEBUG0, 0);
7105 if (CHIP_IS_E1(bp)) {
7106 /* read NIG statistic
7107 to see if this is our first up since powerup */
7108 bnx2x_read_dmae(bp, NIG_REG_STAT2_BRB_OCTET, 2);
7109 val = *bnx2x_sp(bp, wb_data[0]);
7111 /* do internal memory self test */
7112 if ((val == 0) && bnx2x_int_mem_test(bp)) {
7113 BNX2X_ERR("internal mem self test failed\n");
7118 bnx2x_setup_fan_failure_detection(bp);
7120 /* clear PXP2 attentions */
7121 REG_RD(bp, PXP2_REG_PXP2_INT_STS_CLR_0);
7123 bnx2x_enable_blocks_attention(bp);
7124 bnx2x_enable_blocks_parity(bp);
7126 if (!BP_NOMCP(bp)) {
7127 if (CHIP_IS_E1x(bp))
7128 bnx2x__common_init_phy(bp);
7130 BNX2X_ERR("Bootcode is missing - can not initialize link\n");
7136 * bnx2x_init_hw_common_chip - init HW at the COMMON_CHIP phase.
7138 * @bp: driver handle
7140 static int bnx2x_init_hw_common_chip(struct bnx2x *bp)
7142 int rc = bnx2x_init_hw_common(bp);
7147 /* In E2 2-PORT mode, same ext phy is used for the two paths */
7149 bnx2x__common_init_phy(bp);
7154 static int bnx2x_init_hw_port(struct bnx2x *bp)
7156 int port = BP_PORT(bp);
7157 int init_phase = port ? PHASE_PORT1 : PHASE_PORT0;
7161 DP(NETIF_MSG_HW, "starting port init port %d\n", port);
7163 REG_WR(bp, NIG_REG_MASK_INTERRUPT_PORT0 + port*4, 0);
7165 bnx2x_init_block(bp, BLOCK_MISC, init_phase);
7166 bnx2x_init_block(bp, BLOCK_PXP, init_phase);
7167 bnx2x_init_block(bp, BLOCK_PXP2, init_phase);
7169 /* Timers bug workaround: disables the pf_master bit in pglue at
7170 * common phase, we need to enable it here before any dmae access are
7171 * attempted. Therefore we manually added the enable-master to the
7172 * port phase (it also happens in the function phase)
7174 if (!CHIP_IS_E1x(bp))
7175 REG_WR(bp, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, 1);
7177 bnx2x_init_block(bp, BLOCK_ATC, init_phase);
7178 bnx2x_init_block(bp, BLOCK_DMAE, init_phase);
7179 bnx2x_init_block(bp, BLOCK_PGLUE_B, init_phase);
7180 bnx2x_init_block(bp, BLOCK_QM, init_phase);
7182 bnx2x_init_block(bp, BLOCK_TCM, init_phase);
7183 bnx2x_init_block(bp, BLOCK_UCM, init_phase);
7184 bnx2x_init_block(bp, BLOCK_CCM, init_phase);
7185 bnx2x_init_block(bp, BLOCK_XCM, init_phase);
7187 /* QM cid (connection) count */
7188 bnx2x_qm_init_cid_count(bp, bp->qm_cid_count, INITOP_SET);
7190 if (CNIC_SUPPORT(bp)) {
7191 bnx2x_init_block(bp, BLOCK_TM, init_phase);
7192 REG_WR(bp, TM_REG_LIN0_SCAN_TIME + port*4, 20);
7193 REG_WR(bp, TM_REG_LIN0_MAX_ACTIVE_CID + port*4, 31);
7196 bnx2x_init_block(bp, BLOCK_DORQ, init_phase);
7198 bnx2x_init_block(bp, BLOCK_BRB1, init_phase);
7200 if (CHIP_IS_E1(bp) || CHIP_IS_E1H(bp)) {
7203 low = ((bp->flags & ONE_PORT_FLAG) ? 160 : 246);
7204 else if (bp->dev->mtu > 4096) {
7205 if (bp->flags & ONE_PORT_FLAG)
7209 /* (24*1024 + val*4)/256 */
7210 low = 96 + (val/64) +
7211 ((val % 64) ? 1 : 0);
7214 low = ((bp->flags & ONE_PORT_FLAG) ? 80 : 160);
7215 high = low + 56; /* 14*1024/256 */
7216 REG_WR(bp, BRB1_REG_PAUSE_LOW_THRESHOLD_0 + port*4, low);
7217 REG_WR(bp, BRB1_REG_PAUSE_HIGH_THRESHOLD_0 + port*4, high);
7220 if (CHIP_MODE_IS_4_PORT(bp))
7221 REG_WR(bp, (BP_PORT(bp) ?
7222 BRB1_REG_MAC_GUARANTIED_1 :
7223 BRB1_REG_MAC_GUARANTIED_0), 40);
7225 bnx2x_init_block(bp, BLOCK_PRS, init_phase);
7226 if (CHIP_IS_E3B0(bp)) {
7227 if (IS_MF_AFEX(bp)) {
7228 /* configure headers for AFEX mode */
7229 REG_WR(bp, BP_PORT(bp) ?
7230 PRS_REG_HDRS_AFTER_BASIC_PORT_1 :
7231 PRS_REG_HDRS_AFTER_BASIC_PORT_0, 0xE);
7232 REG_WR(bp, BP_PORT(bp) ?
7233 PRS_REG_HDRS_AFTER_TAG_0_PORT_1 :
7234 PRS_REG_HDRS_AFTER_TAG_0_PORT_0, 0x6);
7235 REG_WR(bp, BP_PORT(bp) ?
7236 PRS_REG_MUST_HAVE_HDRS_PORT_1 :
7237 PRS_REG_MUST_HAVE_HDRS_PORT_0, 0xA);
7239 /* Ovlan exists only if we are in multi-function +
7240 * switch-dependent mode, in switch-independent there
7241 * is no ovlan headers
7243 REG_WR(bp, BP_PORT(bp) ?
7244 PRS_REG_HDRS_AFTER_BASIC_PORT_1 :
7245 PRS_REG_HDRS_AFTER_BASIC_PORT_0,
7246 (bp->path_has_ovlan ? 7 : 6));
7250 bnx2x_init_block(bp, BLOCK_TSDM, init_phase);
7251 bnx2x_init_block(bp, BLOCK_CSDM, init_phase);
7252 bnx2x_init_block(bp, BLOCK_USDM, init_phase);
7253 bnx2x_init_block(bp, BLOCK_XSDM, init_phase);
7255 bnx2x_init_block(bp, BLOCK_TSEM, init_phase);
7256 bnx2x_init_block(bp, BLOCK_USEM, init_phase);
7257 bnx2x_init_block(bp, BLOCK_CSEM, init_phase);
7258 bnx2x_init_block(bp, BLOCK_XSEM, init_phase);
7260 bnx2x_init_block(bp, BLOCK_UPB, init_phase);
7261 bnx2x_init_block(bp, BLOCK_XPB, init_phase);
7263 bnx2x_init_block(bp, BLOCK_PBF, init_phase);
7265 if (CHIP_IS_E1x(bp)) {
7266 /* configure PBF to work without PAUSE mtu 9000 */
7267 REG_WR(bp, PBF_REG_P0_PAUSE_ENABLE + port*4, 0);
7269 /* update threshold */
7270 REG_WR(bp, PBF_REG_P0_ARB_THRSH + port*4, (9040/16));
7271 /* update init credit */
7272 REG_WR(bp, PBF_REG_P0_INIT_CRD + port*4, (9040/16) + 553 - 22);
7275 REG_WR(bp, PBF_REG_INIT_P0 + port*4, 1);
7277 REG_WR(bp, PBF_REG_INIT_P0 + port*4, 0);
7280 if (CNIC_SUPPORT(bp))
7281 bnx2x_init_block(bp, BLOCK_SRC, init_phase);
7283 bnx2x_init_block(bp, BLOCK_CDU, init_phase);
7284 bnx2x_init_block(bp, BLOCK_CFC, init_phase);
7286 if (CHIP_IS_E1(bp)) {
7287 REG_WR(bp, HC_REG_LEADING_EDGE_0 + port*8, 0);
7288 REG_WR(bp, HC_REG_TRAILING_EDGE_0 + port*8, 0);
7290 bnx2x_init_block(bp, BLOCK_HC, init_phase);
7292 bnx2x_init_block(bp, BLOCK_IGU, init_phase);
7294 bnx2x_init_block(bp, BLOCK_MISC_AEU, init_phase);
7295 /* init aeu_mask_attn_func_0/1:
7296 * - SF mode: bits 3-7 are masked. Only bits 0-2 are in use
7297 * - MF mode: bit 3 is masked. Bits 0-2 are in use as in SF
7298 * bits 4-7 are used for "per vn group attention" */
7299 val = IS_MF(bp) ? 0xF7 : 0x7;
7300 /* Enable DCBX attention for all but E1 */
7301 val |= CHIP_IS_E1(bp) ? 0 : 0x10;
7302 REG_WR(bp, MISC_REG_AEU_MASK_ATTN_FUNC_0 + port*4, val);
7304 /* SCPAD_PARITY should NOT trigger close the gates */
7305 reg = port ? MISC_REG_AEU_ENABLE4_NIG_1 : MISC_REG_AEU_ENABLE4_NIG_0;
7308 ~AEU_INPUTS_ATTN_BITS_MCP_LATCHED_SCPAD_PARITY);
7310 reg = port ? MISC_REG_AEU_ENABLE4_PXP_1 : MISC_REG_AEU_ENABLE4_PXP_0;
7313 ~AEU_INPUTS_ATTN_BITS_MCP_LATCHED_SCPAD_PARITY);
7315 bnx2x_init_block(bp, BLOCK_NIG, init_phase);
7317 if (!CHIP_IS_E1x(bp)) {
7318 /* Bit-map indicating which L2 hdrs may appear after the
7319 * basic Ethernet header
7322 REG_WR(bp, BP_PORT(bp) ?
7323 NIG_REG_P1_HDRS_AFTER_BASIC :
7324 NIG_REG_P0_HDRS_AFTER_BASIC, 0xE);
7326 REG_WR(bp, BP_PORT(bp) ?
7327 NIG_REG_P1_HDRS_AFTER_BASIC :
7328 NIG_REG_P0_HDRS_AFTER_BASIC,
7329 IS_MF_SD(bp) ? 7 : 6);
7332 REG_WR(bp, BP_PORT(bp) ?
7333 NIG_REG_LLH1_MF_MODE :
7334 NIG_REG_LLH_MF_MODE, IS_MF(bp));
7336 if (!CHIP_IS_E3(bp))
7337 REG_WR(bp, NIG_REG_XGXS_SERDES0_MODE_SEL + port*4, 1);
7339 if (!CHIP_IS_E1(bp)) {
7340 /* 0x2 disable mf_ov, 0x1 enable */
7341 REG_WR(bp, NIG_REG_LLH0_BRB1_DRV_MASK_MF + port*4,
7342 (IS_MF_SD(bp) ? 0x1 : 0x2));
7344 if (!CHIP_IS_E1x(bp)) {
7346 switch (bp->mf_mode) {
7347 case MULTI_FUNCTION_SD:
7350 case MULTI_FUNCTION_SI:
7351 case MULTI_FUNCTION_AFEX:
7356 REG_WR(bp, (BP_PORT(bp) ? NIG_REG_LLH1_CLS_TYPE :
7357 NIG_REG_LLH0_CLS_TYPE), val);
7360 REG_WR(bp, NIG_REG_LLFC_ENABLE_0 + port*4, 0);
7361 REG_WR(bp, NIG_REG_LLFC_OUT_EN_0 + port*4, 0);
7362 REG_WR(bp, NIG_REG_PAUSE_ENABLE_0 + port*4, 1);
7366 /* If SPIO5 is set to generate interrupts, enable it for this port */
7367 val = REG_RD(bp, MISC_REG_SPIO_EVENT_EN);
7368 if (val & MISC_SPIO_SPIO5) {
7369 u32 reg_addr = (port ? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_0 :
7370 MISC_REG_AEU_ENABLE1_FUNC_0_OUT_0);
7371 val = REG_RD(bp, reg_addr);
7372 val |= AEU_INPUTS_ATTN_BITS_SPIO5;
7373 REG_WR(bp, reg_addr, val);
7379 static void bnx2x_ilt_wr(struct bnx2x *bp, u32 index, dma_addr_t addr)
7385 reg = PXP2_REG_RQ_ONCHIP_AT + index*8;
7387 reg = PXP2_REG_RQ_ONCHIP_AT_B0 + index*8;
7389 wb_write[0] = ONCHIP_ADDR1(addr);
7390 wb_write[1] = ONCHIP_ADDR2(addr);
7391 REG_WR_DMAE(bp, reg, wb_write, 2);
7394 void bnx2x_igu_clear_sb_gen(struct bnx2x *bp, u8 func, u8 idu_sb_id, bool is_pf)
7396 u32 data, ctl, cnt = 100;
7397 u32 igu_addr_data = IGU_REG_COMMAND_REG_32LSB_DATA;
7398 u32 igu_addr_ctl = IGU_REG_COMMAND_REG_CTRL;
7399 u32 igu_addr_ack = IGU_REG_CSTORM_TYPE_0_SB_CLEANUP + (idu_sb_id/32)*4;
7400 u32 sb_bit = 1 << (idu_sb_id%32);
7401 u32 func_encode = func | (is_pf ? 1 : 0) << IGU_FID_ENCODE_IS_PF_SHIFT;
7402 u32 addr_encode = IGU_CMD_E2_PROD_UPD_BASE + idu_sb_id;
7404 /* Not supported in BC mode */
7405 if (CHIP_INT_MODE_IS_BC(bp))
7408 data = (IGU_USE_REGISTER_cstorm_type_0_sb_cleanup
7409 << IGU_REGULAR_CLEANUP_TYPE_SHIFT) |
7410 IGU_REGULAR_CLEANUP_SET |
7411 IGU_REGULAR_BCLEANUP;
7413 ctl = addr_encode << IGU_CTRL_REG_ADDRESS_SHIFT |
7414 func_encode << IGU_CTRL_REG_FID_SHIFT |
7415 IGU_CTRL_CMD_TYPE_WR << IGU_CTRL_REG_TYPE_SHIFT;
7417 DP(NETIF_MSG_HW, "write 0x%08x to IGU(via GRC) addr 0x%x\n",
7418 data, igu_addr_data);
7419 REG_WR(bp, igu_addr_data, data);
7422 DP(NETIF_MSG_HW, "write 0x%08x to IGU(via GRC) addr 0x%x\n",
7424 REG_WR(bp, igu_addr_ctl, ctl);
7428 /* wait for clean up to finish */
7429 while (!(REG_RD(bp, igu_addr_ack) & sb_bit) && --cnt)
7432 if (!(REG_RD(bp, igu_addr_ack) & sb_bit)) {
7434 "Unable to finish IGU cleanup: idu_sb_id %d offset %d bit %d (cnt %d)\n",
7435 idu_sb_id, idu_sb_id/32, idu_sb_id%32, cnt);
7439 static void bnx2x_igu_clear_sb(struct bnx2x *bp, u8 idu_sb_id)
7441 bnx2x_igu_clear_sb_gen(bp, BP_FUNC(bp), idu_sb_id, true /*PF*/);
7444 static void bnx2x_clear_func_ilt(struct bnx2x *bp, u32 func)
7446 u32 i, base = FUNC_ILT_BASE(func);
7447 for (i = base; i < base + ILT_PER_FUNC; i++)
7448 bnx2x_ilt_wr(bp, i, 0);
7451 static void bnx2x_init_searcher(struct bnx2x *bp)
7453 int port = BP_PORT(bp);
7454 bnx2x_src_init_t2(bp, bp->t2, bp->t2_mapping, SRC_CONN_NUM);
7455 /* T1 hash bits value determines the T1 number of entries */
7456 REG_WR(bp, SRC_REG_NUMBER_HASH_BITS0 + port*4, SRC_HASH_BITS);
7459 static inline int bnx2x_func_switch_update(struct bnx2x *bp, int suspend)
7462 struct bnx2x_func_state_params func_params = {NULL};
7463 struct bnx2x_func_switch_update_params *switch_update_params =
7464 &func_params.params.switch_update;
7466 /* Prepare parameters for function state transitions */
7467 __set_bit(RAMROD_COMP_WAIT, &func_params.ramrod_flags);
7468 __set_bit(RAMROD_RETRY, &func_params.ramrod_flags);
7470 func_params.f_obj = &bp->func_obj;
7471 func_params.cmd = BNX2X_F_CMD_SWITCH_UPDATE;
7473 /* Function parameters */
7474 switch_update_params->suspend = suspend;
7476 rc = bnx2x_func_state_change(bp, &func_params);
7481 static int bnx2x_reset_nic_mode(struct bnx2x *bp)
7483 int rc, i, port = BP_PORT(bp);
7484 int vlan_en = 0, mac_en[NUM_MACS];
7486 /* Close input from network */
7487 if (bp->mf_mode == SINGLE_FUNCTION) {
7488 bnx2x_set_rx_filter(&bp->link_params, 0);
7490 vlan_en = REG_RD(bp, port ? NIG_REG_LLH1_FUNC_EN :
7491 NIG_REG_LLH0_FUNC_EN);
7492 REG_WR(bp, port ? NIG_REG_LLH1_FUNC_EN :
7493 NIG_REG_LLH0_FUNC_EN, 0);
7494 for (i = 0; i < NUM_MACS; i++) {
7495 mac_en[i] = REG_RD(bp, port ?
7496 (NIG_REG_LLH1_FUNC_MEM_ENABLE +
7498 (NIG_REG_LLH0_FUNC_MEM_ENABLE +
7500 REG_WR(bp, port ? (NIG_REG_LLH1_FUNC_MEM_ENABLE +
7502 (NIG_REG_LLH0_FUNC_MEM_ENABLE + 4 * i), 0);
7506 /* Close BMC to host */
7507 REG_WR(bp, port ? NIG_REG_P0_TX_MNG_HOST_ENABLE :
7508 NIG_REG_P1_TX_MNG_HOST_ENABLE, 0);
7510 /* Suspend Tx switching to the PF. Completion of this ramrod
7511 * further guarantees that all the packets of that PF / child
7512 * VFs in BRB were processed by the Parser, so it is safe to
7513 * change the NIC_MODE register.
7515 rc = bnx2x_func_switch_update(bp, 1);
7517 BNX2X_ERR("Can't suspend tx-switching!\n");
7521 /* Change NIC_MODE register */
7522 REG_WR(bp, PRS_REG_NIC_MODE, 0);
7524 /* Open input from network */
7525 if (bp->mf_mode == SINGLE_FUNCTION) {
7526 bnx2x_set_rx_filter(&bp->link_params, 1);
7528 REG_WR(bp, port ? NIG_REG_LLH1_FUNC_EN :
7529 NIG_REG_LLH0_FUNC_EN, vlan_en);
7530 for (i = 0; i < NUM_MACS; i++) {
7531 REG_WR(bp, port ? (NIG_REG_LLH1_FUNC_MEM_ENABLE +
7533 (NIG_REG_LLH0_FUNC_MEM_ENABLE + 4 * i),
7538 /* Enable BMC to host */
7539 REG_WR(bp, port ? NIG_REG_P0_TX_MNG_HOST_ENABLE :
7540 NIG_REG_P1_TX_MNG_HOST_ENABLE, 1);
7542 /* Resume Tx switching to the PF */
7543 rc = bnx2x_func_switch_update(bp, 0);
7545 BNX2X_ERR("Can't resume tx-switching!\n");
7549 DP(NETIF_MSG_IFUP, "NIC MODE disabled\n");
7553 int bnx2x_init_hw_func_cnic(struct bnx2x *bp)
7557 bnx2x_ilt_init_op_cnic(bp, INITOP_SET);
7559 if (CONFIGURE_NIC_MODE(bp)) {
7560 /* Configure searcher as part of function hw init */
7561 bnx2x_init_searcher(bp);
7563 /* Reset NIC mode */
7564 rc = bnx2x_reset_nic_mode(bp);
7566 BNX2X_ERR("Can't change NIC mode!\n");
7573 static int bnx2x_init_hw_func(struct bnx2x *bp)
7575 int port = BP_PORT(bp);
7576 int func = BP_FUNC(bp);
7577 int init_phase = PHASE_PF0 + func;
7578 struct bnx2x_ilt *ilt = BP_ILT(bp);
7581 u32 main_mem_base, main_mem_size, main_mem_prty_clr;
7582 int i, main_mem_width, rc;
7584 DP(NETIF_MSG_HW, "starting func init func %d\n", func);
7586 /* FLR cleanup - hmmm */
7587 if (!CHIP_IS_E1x(bp)) {
7588 rc = bnx2x_pf_flr_clnup(bp);
7595 /* set MSI reconfigure capability */
7596 if (bp->common.int_block == INT_BLOCK_HC) {
7597 addr = (port ? HC_REG_CONFIG_1 : HC_REG_CONFIG_0);
7598 val = REG_RD(bp, addr);
7599 val |= HC_CONFIG_0_REG_MSI_ATTN_EN_0;
7600 REG_WR(bp, addr, val);
7603 bnx2x_init_block(bp, BLOCK_PXP, init_phase);
7604 bnx2x_init_block(bp, BLOCK_PXP2, init_phase);
7607 cdu_ilt_start = ilt->clients[ILT_CLIENT_CDU].start;
7610 cdu_ilt_start += BNX2X_FIRST_VF_CID/ILT_PAGE_CIDS;
7611 cdu_ilt_start = bnx2x_iov_init_ilt(bp, cdu_ilt_start);
7613 /* since BNX2X_FIRST_VF_CID > 0 the PF L2 cids precedes
7614 * those of the VFs, so start line should be reset
7616 cdu_ilt_start = ilt->clients[ILT_CLIENT_CDU].start;
7617 for (i = 0; i < L2_ILT_LINES(bp); i++) {
7618 ilt->lines[cdu_ilt_start + i].page = bp->context[i].vcxt;
7619 ilt->lines[cdu_ilt_start + i].page_mapping =
7620 bp->context[i].cxt_mapping;
7621 ilt->lines[cdu_ilt_start + i].size = bp->context[i].size;
7624 bnx2x_ilt_init_op(bp, INITOP_SET);
7626 if (!CONFIGURE_NIC_MODE(bp)) {
7627 bnx2x_init_searcher(bp);
7628 REG_WR(bp, PRS_REG_NIC_MODE, 0);
7629 DP(NETIF_MSG_IFUP, "NIC MODE disabled\n");
7632 REG_WR(bp, PRS_REG_NIC_MODE, 1);
7633 DP(NETIF_MSG_IFUP, "NIC MODE configured\n");
7636 if (!CHIP_IS_E1x(bp)) {
7637 u32 pf_conf = IGU_PF_CONF_FUNC_EN;
7639 /* Turn on a single ISR mode in IGU if driver is going to use
7642 if (!(bp->flags & USING_MSIX_FLAG))
7643 pf_conf |= IGU_PF_CONF_SINGLE_ISR_EN;
7645 * Timers workaround bug: function init part.
7646 * Need to wait 20msec after initializing ILT,
7647 * needed to make sure there are no requests in
7648 * one of the PXP internal queues with "old" ILT addresses
7652 * Master enable - Due to WB DMAE writes performed before this
7653 * register is re-initialized as part of the regular function
7656 REG_WR(bp, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, 1);
7657 /* Enable the function in IGU */
7658 REG_WR(bp, IGU_REG_PF_CONFIGURATION, pf_conf);
7663 bnx2x_init_block(bp, BLOCK_PGLUE_B, init_phase);
7665 if (!CHIP_IS_E1x(bp))
7666 REG_WR(bp, PGLUE_B_REG_WAS_ERROR_PF_7_0_CLR, func);
7668 bnx2x_init_block(bp, BLOCK_ATC, init_phase);
7669 bnx2x_init_block(bp, BLOCK_DMAE, init_phase);
7670 bnx2x_init_block(bp, BLOCK_NIG, init_phase);
7671 bnx2x_init_block(bp, BLOCK_SRC, init_phase);
7672 bnx2x_init_block(bp, BLOCK_MISC, init_phase);
7673 bnx2x_init_block(bp, BLOCK_TCM, init_phase);
7674 bnx2x_init_block(bp, BLOCK_UCM, init_phase);
7675 bnx2x_init_block(bp, BLOCK_CCM, init_phase);
7676 bnx2x_init_block(bp, BLOCK_XCM, init_phase);
7677 bnx2x_init_block(bp, BLOCK_TSEM, init_phase);
7678 bnx2x_init_block(bp, BLOCK_USEM, init_phase);
7679 bnx2x_init_block(bp, BLOCK_CSEM, init_phase);
7680 bnx2x_init_block(bp, BLOCK_XSEM, init_phase);
7682 if (!CHIP_IS_E1x(bp))
7683 REG_WR(bp, QM_REG_PF_EN, 1);
7685 if (!CHIP_IS_E1x(bp)) {
7686 REG_WR(bp, TSEM_REG_VFPF_ERR_NUM, BNX2X_MAX_NUM_OF_VFS + func);
7687 REG_WR(bp, USEM_REG_VFPF_ERR_NUM, BNX2X_MAX_NUM_OF_VFS + func);
7688 REG_WR(bp, CSEM_REG_VFPF_ERR_NUM, BNX2X_MAX_NUM_OF_VFS + func);
7689 REG_WR(bp, XSEM_REG_VFPF_ERR_NUM, BNX2X_MAX_NUM_OF_VFS + func);
7691 bnx2x_init_block(bp, BLOCK_QM, init_phase);
7693 bnx2x_init_block(bp, BLOCK_TM, init_phase);
7694 bnx2x_init_block(bp, BLOCK_DORQ, init_phase);
7695 REG_WR(bp, DORQ_REG_MODE_ACT, 1); /* no dpm */
7697 bnx2x_iov_init_dq(bp);
7699 bnx2x_init_block(bp, BLOCK_BRB1, init_phase);
7700 bnx2x_init_block(bp, BLOCK_PRS, init_phase);
7701 bnx2x_init_block(bp, BLOCK_TSDM, init_phase);
7702 bnx2x_init_block(bp, BLOCK_CSDM, init_phase);
7703 bnx2x_init_block(bp, BLOCK_USDM, init_phase);
7704 bnx2x_init_block(bp, BLOCK_XSDM, init_phase);
7705 bnx2x_init_block(bp, BLOCK_UPB, init_phase);
7706 bnx2x_init_block(bp, BLOCK_XPB, init_phase);
7707 bnx2x_init_block(bp, BLOCK_PBF, init_phase);
7708 if (!CHIP_IS_E1x(bp))
7709 REG_WR(bp, PBF_REG_DISABLE_PF, 0);
7711 bnx2x_init_block(bp, BLOCK_CDU, init_phase);
7713 bnx2x_init_block(bp, BLOCK_CFC, init_phase);
7715 if (!CHIP_IS_E1x(bp))
7716 REG_WR(bp, CFC_REG_WEAK_ENABLE_PF, 1);
7719 REG_WR(bp, NIG_REG_LLH0_FUNC_EN + port*8, 1);
7720 REG_WR(bp, NIG_REG_LLH0_FUNC_VLAN_ID + port*8, bp->mf_ov);
7723 bnx2x_init_block(bp, BLOCK_MISC_AEU, init_phase);
7725 /* HC init per function */
7726 if (bp->common.int_block == INT_BLOCK_HC) {
7727 if (CHIP_IS_E1H(bp)) {
7728 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_12 + func*4, 0);
7730 REG_WR(bp, HC_REG_LEADING_EDGE_0 + port*8, 0);
7731 REG_WR(bp, HC_REG_TRAILING_EDGE_0 + port*8, 0);
7733 bnx2x_init_block(bp, BLOCK_HC, init_phase);
7736 int num_segs, sb_idx, prod_offset;
7738 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_12 + func*4, 0);
7740 if (!CHIP_IS_E1x(bp)) {
7741 REG_WR(bp, IGU_REG_LEADING_EDGE_LATCH, 0);
7742 REG_WR(bp, IGU_REG_TRAILING_EDGE_LATCH, 0);
7745 bnx2x_init_block(bp, BLOCK_IGU, init_phase);
7747 if (!CHIP_IS_E1x(bp)) {
7751 * E2 mode: address 0-135 match to the mapping memory;
7752 * 136 - PF0 default prod; 137 - PF1 default prod;
7753 * 138 - PF2 default prod; 139 - PF3 default prod;
7754 * 140 - PF0 attn prod; 141 - PF1 attn prod;
7755 * 142 - PF2 attn prod; 143 - PF3 attn prod;
7758 * E1.5 mode - In backward compatible mode;
7759 * for non default SB; each even line in the memory
7760 * holds the U producer and each odd line hold
7761 * the C producer. The first 128 producers are for
7762 * NDSB (PF0 - 0-31; PF1 - 32-63 and so on). The last 20
7763 * producers are for the DSB for each PF.
7764 * Each PF has five segments: (the order inside each
7765 * segment is PF0; PF1; PF2; PF3) - 128-131 U prods;
7766 * 132-135 C prods; 136-139 X prods; 140-143 T prods;
7767 * 144-147 attn prods;
7769 /* non-default-status-blocks */
7770 num_segs = CHIP_INT_MODE_IS_BC(bp) ?
7771 IGU_BC_NDSB_NUM_SEGS : IGU_NORM_NDSB_NUM_SEGS;
7772 for (sb_idx = 0; sb_idx < bp->igu_sb_cnt; sb_idx++) {
7773 prod_offset = (bp->igu_base_sb + sb_idx) *
7776 for (i = 0; i < num_segs; i++) {
7777 addr = IGU_REG_PROD_CONS_MEMORY +
7778 (prod_offset + i) * 4;
7779 REG_WR(bp, addr, 0);
7781 /* send consumer update with value 0 */
7782 bnx2x_ack_sb(bp, bp->igu_base_sb + sb_idx,
7783 USTORM_ID, 0, IGU_INT_NOP, 1);
7784 bnx2x_igu_clear_sb(bp,
7785 bp->igu_base_sb + sb_idx);
7788 /* default-status-blocks */
7789 num_segs = CHIP_INT_MODE_IS_BC(bp) ?
7790 IGU_BC_DSB_NUM_SEGS : IGU_NORM_DSB_NUM_SEGS;
7792 if (CHIP_MODE_IS_4_PORT(bp))
7793 dsb_idx = BP_FUNC(bp);
7795 dsb_idx = BP_VN(bp);
7797 prod_offset = (CHIP_INT_MODE_IS_BC(bp) ?
7798 IGU_BC_BASE_DSB_PROD + dsb_idx :
7799 IGU_NORM_BASE_DSB_PROD + dsb_idx);
7802 * igu prods come in chunks of E1HVN_MAX (4) -
7803 * does not matters what is the current chip mode
7805 for (i = 0; i < (num_segs * E1HVN_MAX);
7807 addr = IGU_REG_PROD_CONS_MEMORY +
7808 (prod_offset + i)*4;
7809 REG_WR(bp, addr, 0);
7811 /* send consumer update with 0 */
7812 if (CHIP_INT_MODE_IS_BC(bp)) {
7813 bnx2x_ack_sb(bp, bp->igu_dsb_id,
7814 USTORM_ID, 0, IGU_INT_NOP, 1);
7815 bnx2x_ack_sb(bp, bp->igu_dsb_id,
7816 CSTORM_ID, 0, IGU_INT_NOP, 1);
7817 bnx2x_ack_sb(bp, bp->igu_dsb_id,
7818 XSTORM_ID, 0, IGU_INT_NOP, 1);
7819 bnx2x_ack_sb(bp, bp->igu_dsb_id,
7820 TSTORM_ID, 0, IGU_INT_NOP, 1);
7821 bnx2x_ack_sb(bp, bp->igu_dsb_id,
7822 ATTENTION_ID, 0, IGU_INT_NOP, 1);
7824 bnx2x_ack_sb(bp, bp->igu_dsb_id,
7825 USTORM_ID, 0, IGU_INT_NOP, 1);
7826 bnx2x_ack_sb(bp, bp->igu_dsb_id,
7827 ATTENTION_ID, 0, IGU_INT_NOP, 1);
7829 bnx2x_igu_clear_sb(bp, bp->igu_dsb_id);
7831 /* !!! These should become driver const once
7832 rf-tool supports split-68 const */
7833 REG_WR(bp, IGU_REG_SB_INT_BEFORE_MASK_LSB, 0);
7834 REG_WR(bp, IGU_REG_SB_INT_BEFORE_MASK_MSB, 0);
7835 REG_WR(bp, IGU_REG_SB_MASK_LSB, 0);
7836 REG_WR(bp, IGU_REG_SB_MASK_MSB, 0);
7837 REG_WR(bp, IGU_REG_PBA_STATUS_LSB, 0);
7838 REG_WR(bp, IGU_REG_PBA_STATUS_MSB, 0);
7842 /* Reset PCIE errors for debug */
7843 REG_WR(bp, 0x2114, 0xffffffff);
7844 REG_WR(bp, 0x2120, 0xffffffff);
7846 if (CHIP_IS_E1x(bp)) {
7847 main_mem_size = HC_REG_MAIN_MEMORY_SIZE / 2; /*dwords*/
7848 main_mem_base = HC_REG_MAIN_MEMORY +
7849 BP_PORT(bp) * (main_mem_size * 4);
7850 main_mem_prty_clr = HC_REG_HC_PRTY_STS_CLR;
7853 val = REG_RD(bp, main_mem_prty_clr);
7856 "Hmmm... Parity errors in HC block during function init (0x%x)!\n",
7859 /* Clear "false" parity errors in MSI-X table */
7860 for (i = main_mem_base;
7861 i < main_mem_base + main_mem_size * 4;
7862 i += main_mem_width) {
7863 bnx2x_read_dmae(bp, i, main_mem_width / 4);
7864 bnx2x_write_dmae(bp, bnx2x_sp_mapping(bp, wb_data),
7865 i, main_mem_width / 4);
7867 /* Clear HC parity attention */
7868 REG_RD(bp, main_mem_prty_clr);
7871 #ifdef BNX2X_STOP_ON_ERROR
7872 /* Enable STORMs SP logging */
7873 REG_WR8(bp, BAR_USTRORM_INTMEM +
7874 USTORM_RECORD_SLOW_PATH_OFFSET(BP_FUNC(bp)), 1);
7875 REG_WR8(bp, BAR_TSTRORM_INTMEM +
7876 TSTORM_RECORD_SLOW_PATH_OFFSET(BP_FUNC(bp)), 1);
7877 REG_WR8(bp, BAR_CSTRORM_INTMEM +
7878 CSTORM_RECORD_SLOW_PATH_OFFSET(BP_FUNC(bp)), 1);
7879 REG_WR8(bp, BAR_XSTRORM_INTMEM +
7880 XSTORM_RECORD_SLOW_PATH_OFFSET(BP_FUNC(bp)), 1);
7883 bnx2x_phy_probe(&bp->link_params);
7888 void bnx2x_free_mem_cnic(struct bnx2x *bp)
7890 bnx2x_ilt_mem_op_cnic(bp, ILT_MEMOP_FREE);
7892 if (!CHIP_IS_E1x(bp))
7893 BNX2X_PCI_FREE(bp->cnic_sb.e2_sb, bp->cnic_sb_mapping,
7894 sizeof(struct host_hc_status_block_e2));
7896 BNX2X_PCI_FREE(bp->cnic_sb.e1x_sb, bp->cnic_sb_mapping,
7897 sizeof(struct host_hc_status_block_e1x));
7899 BNX2X_PCI_FREE(bp->t2, bp->t2_mapping, SRC_T2_SZ);
7902 void bnx2x_free_mem(struct bnx2x *bp)
7906 BNX2X_PCI_FREE(bp->fw_stats, bp->fw_stats_mapping,
7907 bp->fw_stats_data_sz + bp->fw_stats_req_sz);
7912 BNX2X_PCI_FREE(bp->def_status_blk, bp->def_status_blk_mapping,
7913 sizeof(struct host_sp_status_block));
7915 BNX2X_PCI_FREE(bp->slowpath, bp->slowpath_mapping,
7916 sizeof(struct bnx2x_slowpath));
7918 for (i = 0; i < L2_ILT_LINES(bp); i++)
7919 BNX2X_PCI_FREE(bp->context[i].vcxt, bp->context[i].cxt_mapping,
7920 bp->context[i].size);
7921 bnx2x_ilt_mem_op(bp, ILT_MEMOP_FREE);
7923 BNX2X_FREE(bp->ilt->lines);
7925 BNX2X_PCI_FREE(bp->spq, bp->spq_mapping, BCM_PAGE_SIZE);
7927 BNX2X_PCI_FREE(bp->eq_ring, bp->eq_mapping,
7928 BCM_PAGE_SIZE * NUM_EQ_PAGES);
7930 BNX2X_PCI_FREE(bp->t2, bp->t2_mapping, SRC_T2_SZ);
7932 bnx2x_iov_free_mem(bp);
7935 int bnx2x_alloc_mem_cnic(struct bnx2x *bp)
7937 if (!CHIP_IS_E1x(bp))
7938 /* size = the status block + ramrod buffers */
7939 BNX2X_PCI_ALLOC(bp->cnic_sb.e2_sb, &bp->cnic_sb_mapping,
7940 sizeof(struct host_hc_status_block_e2));
7942 BNX2X_PCI_ALLOC(bp->cnic_sb.e1x_sb,
7943 &bp->cnic_sb_mapping,
7945 host_hc_status_block_e1x));
7947 if (CONFIGURE_NIC_MODE(bp) && !bp->t2)
7948 /* allocate searcher T2 table, as it wasn't allocated before */
7949 BNX2X_PCI_ALLOC(bp->t2, &bp->t2_mapping, SRC_T2_SZ);
7951 /* write address to which L5 should insert its values */
7952 bp->cnic_eth_dev.addr_drv_info_to_mcp =
7953 &bp->slowpath->drv_info_to_mcp;
7955 if (bnx2x_ilt_mem_op_cnic(bp, ILT_MEMOP_ALLOC))
7961 bnx2x_free_mem_cnic(bp);
7962 BNX2X_ERR("Can't allocate memory\n");
7966 int bnx2x_alloc_mem(struct bnx2x *bp)
7968 int i, allocated, context_size;
7970 if (!CONFIGURE_NIC_MODE(bp) && !bp->t2)
7971 /* allocate searcher T2 table */
7972 BNX2X_PCI_ALLOC(bp->t2, &bp->t2_mapping, SRC_T2_SZ);
7974 BNX2X_PCI_ALLOC(bp->def_status_blk, &bp->def_status_blk_mapping,
7975 sizeof(struct host_sp_status_block));
7977 BNX2X_PCI_ALLOC(bp->slowpath, &bp->slowpath_mapping,
7978 sizeof(struct bnx2x_slowpath));
7980 /* Allocate memory for CDU context:
7981 * This memory is allocated separately and not in the generic ILT
7982 * functions because CDU differs in few aspects:
7983 * 1. There are multiple entities allocating memory for context -
7984 * 'regular' driver, CNIC and SRIOV driver. Each separately controls
7985 * its own ILT lines.
7986 * 2. Since CDU page-size is not a single 4KB page (which is the case
7987 * for the other ILT clients), to be efficient we want to support
7988 * allocation of sub-page-size in the last entry.
7989 * 3. Context pointers are used by the driver to pass to FW / update
7990 * the context (for the other ILT clients the pointers are used just to
7991 * free the memory during unload).
7993 context_size = sizeof(union cdu_context) * BNX2X_L2_CID_COUNT(bp);
7995 for (i = 0, allocated = 0; allocated < context_size; i++) {
7996 bp->context[i].size = min(CDU_ILT_PAGE_SZ,
7997 (context_size - allocated));
7998 BNX2X_PCI_ALLOC(bp->context[i].vcxt,
7999 &bp->context[i].cxt_mapping,
8000 bp->context[i].size);
8001 allocated += bp->context[i].size;
8003 BNX2X_ALLOC(bp->ilt->lines, sizeof(struct ilt_line) * ILT_MAX_LINES);
8005 if (bnx2x_ilt_mem_op(bp, ILT_MEMOP_ALLOC))
8008 if (bnx2x_iov_alloc_mem(bp))
8011 /* Slow path ring */
8012 BNX2X_PCI_ALLOC(bp->spq, &bp->spq_mapping, BCM_PAGE_SIZE);
8015 BNX2X_PCI_ALLOC(bp->eq_ring, &bp->eq_mapping,
8016 BCM_PAGE_SIZE * NUM_EQ_PAGES);
8022 BNX2X_ERR("Can't allocate memory\n");
8027 * Init service functions
8030 int bnx2x_set_mac_one(struct bnx2x *bp, u8 *mac,
8031 struct bnx2x_vlan_mac_obj *obj, bool set,
8032 int mac_type, unsigned long *ramrod_flags)
8035 struct bnx2x_vlan_mac_ramrod_params ramrod_param;
8037 memset(&ramrod_param, 0, sizeof(ramrod_param));
8039 /* Fill general parameters */
8040 ramrod_param.vlan_mac_obj = obj;
8041 ramrod_param.ramrod_flags = *ramrod_flags;
8043 /* Fill a user request section if needed */
8044 if (!test_bit(RAMROD_CONT, ramrod_flags)) {
8045 memcpy(ramrod_param.user_req.u.mac.mac, mac, ETH_ALEN);
8047 __set_bit(mac_type, &ramrod_param.user_req.vlan_mac_flags);
8049 /* Set the command: ADD or DEL */
8051 ramrod_param.user_req.cmd = BNX2X_VLAN_MAC_ADD;
8053 ramrod_param.user_req.cmd = BNX2X_VLAN_MAC_DEL;
8056 rc = bnx2x_config_vlan_mac(bp, &ramrod_param);
8058 if (rc == -EEXIST) {
8059 DP(BNX2X_MSG_SP, "Failed to schedule ADD operations: %d\n", rc);
8060 /* do not treat adding same MAC as error */
8063 BNX2X_ERR("%s MAC failed\n", (set ? "Set" : "Del"));
8068 int bnx2x_del_all_macs(struct bnx2x *bp,
8069 struct bnx2x_vlan_mac_obj *mac_obj,
8070 int mac_type, bool wait_for_comp)
8073 unsigned long ramrod_flags = 0, vlan_mac_flags = 0;
8075 /* Wait for completion of requested */
8077 __set_bit(RAMROD_COMP_WAIT, &ramrod_flags);
8079 /* Set the mac type of addresses we want to clear */
8080 __set_bit(mac_type, &vlan_mac_flags);
8082 rc = mac_obj->delete_all(bp, mac_obj, &vlan_mac_flags, &ramrod_flags);
8084 BNX2X_ERR("Failed to delete MACs: %d\n", rc);
8089 int bnx2x_set_eth_mac(struct bnx2x *bp, bool set)
8091 if (is_zero_ether_addr(bp->dev->dev_addr) &&
8092 (IS_MF_STORAGE_SD(bp) || IS_MF_FCOE_AFEX(bp))) {
8093 DP(NETIF_MSG_IFUP | NETIF_MSG_IFDOWN,
8094 "Ignoring Zero MAC for STORAGE SD mode\n");
8099 unsigned long ramrod_flags = 0;
8101 DP(NETIF_MSG_IFUP, "Adding Eth MAC\n");
8102 __set_bit(RAMROD_COMP_WAIT, &ramrod_flags);
8103 return bnx2x_set_mac_one(bp, bp->dev->dev_addr,
8104 &bp->sp_objs->mac_obj, set,
8105 BNX2X_ETH_MAC, &ramrod_flags);
8107 return bnx2x_vfpf_config_mac(bp, bp->dev->dev_addr,
8108 bp->fp->index, true);
8112 int bnx2x_setup_leading(struct bnx2x *bp)
8115 return bnx2x_setup_queue(bp, &bp->fp[0], true);
8117 return bnx2x_vfpf_setup_q(bp, &bp->fp[0], true);
8121 * bnx2x_set_int_mode - configure interrupt mode
8123 * @bp: driver handle
8125 * In case of MSI-X it will also try to enable MSI-X.
8127 int bnx2x_set_int_mode(struct bnx2x *bp)
8131 if (IS_VF(bp) && int_mode != BNX2X_INT_MODE_MSIX) {
8132 BNX2X_ERR("VF not loaded since interrupt mode not msix\n");
8137 case BNX2X_INT_MODE_MSIX:
8138 /* attempt to enable msix */
8139 rc = bnx2x_enable_msix(bp);
8145 /* vfs use only msix */
8146 if (rc && IS_VF(bp))
8149 /* failed to enable multiple MSI-X */
8150 BNX2X_DEV_INFO("Failed to enable multiple MSI-X (%d), set number of queues to %d\n",
8152 1 + bp->num_cnic_queues);
8154 /* falling through... */
8155 case BNX2X_INT_MODE_MSI:
8156 bnx2x_enable_msi(bp);
8158 /* falling through... */
8159 case BNX2X_INT_MODE_INTX:
8160 bp->num_ethernet_queues = 1;
8161 bp->num_queues = bp->num_ethernet_queues + bp->num_cnic_queues;
8162 BNX2X_DEV_INFO("set number of queues to 1\n");
8165 BNX2X_DEV_INFO("unknown value in int_mode module parameter\n");
8171 /* must be called prior to any HW initializations */
8172 static inline u16 bnx2x_cid_ilt_lines(struct bnx2x *bp)
8175 return (BNX2X_FIRST_VF_CID + BNX2X_VF_CIDS)/ILT_PAGE_CIDS;
8176 return L2_ILT_LINES(bp);
8179 void bnx2x_ilt_set_info(struct bnx2x *bp)
8181 struct ilt_client_info *ilt_client;
8182 struct bnx2x_ilt *ilt = BP_ILT(bp);
8185 ilt->start_line = FUNC_ILT_BASE(BP_FUNC(bp));
8186 DP(BNX2X_MSG_SP, "ilt starts at line %d\n", ilt->start_line);
8189 ilt_client = &ilt->clients[ILT_CLIENT_CDU];
8190 ilt_client->client_num = ILT_CLIENT_CDU;
8191 ilt_client->page_size = CDU_ILT_PAGE_SZ;
8192 ilt_client->flags = ILT_CLIENT_SKIP_MEM;
8193 ilt_client->start = line;
8194 line += bnx2x_cid_ilt_lines(bp);
8196 if (CNIC_SUPPORT(bp))
8197 line += CNIC_ILT_LINES;
8198 ilt_client->end = line - 1;
8200 DP(NETIF_MSG_IFUP, "ilt client[CDU]: start %d, end %d, psz 0x%x, flags 0x%x, hw psz %d\n",
8203 ilt_client->page_size,
8205 ilog2(ilt_client->page_size >> 12));
8208 if (QM_INIT(bp->qm_cid_count)) {
8209 ilt_client = &ilt->clients[ILT_CLIENT_QM];
8210 ilt_client->client_num = ILT_CLIENT_QM;
8211 ilt_client->page_size = QM_ILT_PAGE_SZ;
8212 ilt_client->flags = 0;
8213 ilt_client->start = line;
8215 /* 4 bytes for each cid */
8216 line += DIV_ROUND_UP(bp->qm_cid_count * QM_QUEUES_PER_FUNC * 4,
8219 ilt_client->end = line - 1;
8222 "ilt client[QM]: start %d, end %d, psz 0x%x, flags 0x%x, hw psz %d\n",
8225 ilt_client->page_size,
8227 ilog2(ilt_client->page_size >> 12));
8230 if (CNIC_SUPPORT(bp)) {
8232 ilt_client = &ilt->clients[ILT_CLIENT_SRC];
8233 ilt_client->client_num = ILT_CLIENT_SRC;
8234 ilt_client->page_size = SRC_ILT_PAGE_SZ;
8235 ilt_client->flags = 0;
8236 ilt_client->start = line;
8237 line += SRC_ILT_LINES;
8238 ilt_client->end = line - 1;
8241 "ilt client[SRC]: start %d, end %d, psz 0x%x, flags 0x%x, hw psz %d\n",
8244 ilt_client->page_size,
8246 ilog2(ilt_client->page_size >> 12));
8249 ilt_client = &ilt->clients[ILT_CLIENT_TM];
8250 ilt_client->client_num = ILT_CLIENT_TM;
8251 ilt_client->page_size = TM_ILT_PAGE_SZ;
8252 ilt_client->flags = 0;
8253 ilt_client->start = line;
8254 line += TM_ILT_LINES;
8255 ilt_client->end = line - 1;
8258 "ilt client[TM]: start %d, end %d, psz 0x%x, flags 0x%x, hw psz %d\n",
8261 ilt_client->page_size,
8263 ilog2(ilt_client->page_size >> 12));
8266 BUG_ON(line > ILT_MAX_LINES);
8270 * bnx2x_pf_q_prep_init - prepare INIT transition parameters
8272 * @bp: driver handle
8273 * @fp: pointer to fastpath
8274 * @init_params: pointer to parameters structure
8276 * parameters configured:
8277 * - HC configuration
8278 * - Queue's CDU context
8280 static void bnx2x_pf_q_prep_init(struct bnx2x *bp,
8281 struct bnx2x_fastpath *fp, struct bnx2x_queue_init_params *init_params)
8284 int cxt_index, cxt_offset;
8286 /* FCoE Queue uses Default SB, thus has no HC capabilities */
8287 if (!IS_FCOE_FP(fp)) {
8288 __set_bit(BNX2X_Q_FLG_HC, &init_params->rx.flags);
8289 __set_bit(BNX2X_Q_FLG_HC, &init_params->tx.flags);
8291 /* If HC is supported, enable host coalescing in the transition
8294 __set_bit(BNX2X_Q_FLG_HC_EN, &init_params->rx.flags);
8295 __set_bit(BNX2X_Q_FLG_HC_EN, &init_params->tx.flags);
8298 init_params->rx.hc_rate = bp->rx_ticks ?
8299 (1000000 / bp->rx_ticks) : 0;
8300 init_params->tx.hc_rate = bp->tx_ticks ?
8301 (1000000 / bp->tx_ticks) : 0;
8304 init_params->rx.fw_sb_id = init_params->tx.fw_sb_id =
8308 * CQ index among the SB indices: FCoE clients uses the default
8309 * SB, therefore it's different.
8311 init_params->rx.sb_cq_index = HC_INDEX_ETH_RX_CQ_CONS;
8312 init_params->tx.sb_cq_index = HC_INDEX_ETH_FIRST_TX_CQ_CONS;
8315 /* set maximum number of COSs supported by this queue */
8316 init_params->max_cos = fp->max_cos;
8318 DP(NETIF_MSG_IFUP, "fp: %d setting queue params max cos to: %d\n",
8319 fp->index, init_params->max_cos);
8321 /* set the context pointers queue object */
8322 for (cos = FIRST_TX_COS_INDEX; cos < init_params->max_cos; cos++) {
8323 cxt_index = fp->txdata_ptr[cos]->cid / ILT_PAGE_CIDS;
8324 cxt_offset = fp->txdata_ptr[cos]->cid - (cxt_index *
8326 init_params->cxts[cos] =
8327 &bp->context[cxt_index].vcxt[cxt_offset].eth;
8331 static int bnx2x_setup_tx_only(struct bnx2x *bp, struct bnx2x_fastpath *fp,
8332 struct bnx2x_queue_state_params *q_params,
8333 struct bnx2x_queue_setup_tx_only_params *tx_only_params,
8334 int tx_index, bool leading)
8336 memset(tx_only_params, 0, sizeof(*tx_only_params));
8338 /* Set the command */
8339 q_params->cmd = BNX2X_Q_CMD_SETUP_TX_ONLY;
8341 /* Set tx-only QUEUE flags: don't zero statistics */
8342 tx_only_params->flags = bnx2x_get_common_flags(bp, fp, false);
8344 /* choose the index of the cid to send the slow path on */
8345 tx_only_params->cid_index = tx_index;
8347 /* Set general TX_ONLY_SETUP parameters */
8348 bnx2x_pf_q_prep_general(bp, fp, &tx_only_params->gen_params, tx_index);
8350 /* Set Tx TX_ONLY_SETUP parameters */
8351 bnx2x_pf_tx_q_prep(bp, fp, &tx_only_params->txq_params, tx_index);
8354 "preparing to send tx-only ramrod for connection: cos %d, primary cid %d, cid %d, client id %d, sp-client id %d, flags %lx\n",
8355 tx_index, q_params->q_obj->cids[FIRST_TX_COS_INDEX],
8356 q_params->q_obj->cids[tx_index], q_params->q_obj->cl_id,
8357 tx_only_params->gen_params.spcl_id, tx_only_params->flags);
8359 /* send the ramrod */
8360 return bnx2x_queue_state_change(bp, q_params);
8364 * bnx2x_setup_queue - setup queue
8366 * @bp: driver handle
8367 * @fp: pointer to fastpath
8368 * @leading: is leading
8370 * This function performs 2 steps in a Queue state machine
8371 * actually: 1) RESET->INIT 2) INIT->SETUP
8374 int bnx2x_setup_queue(struct bnx2x *bp, struct bnx2x_fastpath *fp,
8377 struct bnx2x_queue_state_params q_params = {NULL};
8378 struct bnx2x_queue_setup_params *setup_params =
8379 &q_params.params.setup;
8380 struct bnx2x_queue_setup_tx_only_params *tx_only_params =
8381 &q_params.params.tx_only;
8385 DP(NETIF_MSG_IFUP, "setting up queue %d\n", fp->index);
8387 /* reset IGU state skip FCoE L2 queue */
8388 if (!IS_FCOE_FP(fp))
8389 bnx2x_ack_sb(bp, fp->igu_sb_id, USTORM_ID, 0,
8392 q_params.q_obj = &bnx2x_sp_obj(bp, fp).q_obj;
8393 /* We want to wait for completion in this context */
8394 __set_bit(RAMROD_COMP_WAIT, &q_params.ramrod_flags);
8396 /* Prepare the INIT parameters */
8397 bnx2x_pf_q_prep_init(bp, fp, &q_params.params.init);
8399 /* Set the command */
8400 q_params.cmd = BNX2X_Q_CMD_INIT;
8402 /* Change the state to INIT */
8403 rc = bnx2x_queue_state_change(bp, &q_params);
8405 BNX2X_ERR("Queue(%d) INIT failed\n", fp->index);
8409 DP(NETIF_MSG_IFUP, "init complete\n");
8411 /* Now move the Queue to the SETUP state... */
8412 memset(setup_params, 0, sizeof(*setup_params));
8414 /* Set QUEUE flags */
8415 setup_params->flags = bnx2x_get_q_flags(bp, fp, leading);
8417 /* Set general SETUP parameters */
8418 bnx2x_pf_q_prep_general(bp, fp, &setup_params->gen_params,
8419 FIRST_TX_COS_INDEX);
8421 bnx2x_pf_rx_q_prep(bp, fp, &setup_params->pause_params,
8422 &setup_params->rxq_params);
8424 bnx2x_pf_tx_q_prep(bp, fp, &setup_params->txq_params,
8425 FIRST_TX_COS_INDEX);
8427 /* Set the command */
8428 q_params.cmd = BNX2X_Q_CMD_SETUP;
8431 bp->fcoe_init = true;
8433 /* Change the state to SETUP */
8434 rc = bnx2x_queue_state_change(bp, &q_params);
8436 BNX2X_ERR("Queue(%d) SETUP failed\n", fp->index);
8440 /* loop through the relevant tx-only indices */
8441 for (tx_index = FIRST_TX_ONLY_COS_INDEX;
8442 tx_index < fp->max_cos;
8445 /* prepare and send tx-only ramrod*/
8446 rc = bnx2x_setup_tx_only(bp, fp, &q_params,
8447 tx_only_params, tx_index, leading);
8449 BNX2X_ERR("Queue(%d.%d) TX_ONLY_SETUP failed\n",
8450 fp->index, tx_index);
8458 static int bnx2x_stop_queue(struct bnx2x *bp, int index)
8460 struct bnx2x_fastpath *fp = &bp->fp[index];
8461 struct bnx2x_fp_txdata *txdata;
8462 struct bnx2x_queue_state_params q_params = {NULL};
8465 DP(NETIF_MSG_IFDOWN, "stopping queue %d cid %d\n", index, fp->cid);
8467 q_params.q_obj = &bnx2x_sp_obj(bp, fp).q_obj;
8468 /* We want to wait for completion in this context */
8469 __set_bit(RAMROD_COMP_WAIT, &q_params.ramrod_flags);
8471 /* close tx-only connections */
8472 for (tx_index = FIRST_TX_ONLY_COS_INDEX;
8473 tx_index < fp->max_cos;
8476 /* ascertain this is a normal queue*/
8477 txdata = fp->txdata_ptr[tx_index];
8479 DP(NETIF_MSG_IFDOWN, "stopping tx-only queue %d\n",
8482 /* send halt terminate on tx-only connection */
8483 q_params.cmd = BNX2X_Q_CMD_TERMINATE;
8484 memset(&q_params.params.terminate, 0,
8485 sizeof(q_params.params.terminate));
8486 q_params.params.terminate.cid_index = tx_index;
8488 rc = bnx2x_queue_state_change(bp, &q_params);
8492 /* send halt terminate on tx-only connection */
8493 q_params.cmd = BNX2X_Q_CMD_CFC_DEL;
8494 memset(&q_params.params.cfc_del, 0,
8495 sizeof(q_params.params.cfc_del));
8496 q_params.params.cfc_del.cid_index = tx_index;
8497 rc = bnx2x_queue_state_change(bp, &q_params);
8501 /* Stop the primary connection: */
8502 /* ...halt the connection */
8503 q_params.cmd = BNX2X_Q_CMD_HALT;
8504 rc = bnx2x_queue_state_change(bp, &q_params);
8508 /* ...terminate the connection */
8509 q_params.cmd = BNX2X_Q_CMD_TERMINATE;
8510 memset(&q_params.params.terminate, 0,
8511 sizeof(q_params.params.terminate));
8512 q_params.params.terminate.cid_index = FIRST_TX_COS_INDEX;
8513 rc = bnx2x_queue_state_change(bp, &q_params);
8516 /* ...delete cfc entry */
8517 q_params.cmd = BNX2X_Q_CMD_CFC_DEL;
8518 memset(&q_params.params.cfc_del, 0,
8519 sizeof(q_params.params.cfc_del));
8520 q_params.params.cfc_del.cid_index = FIRST_TX_COS_INDEX;
8521 return bnx2x_queue_state_change(bp, &q_params);
8524 static void bnx2x_reset_func(struct bnx2x *bp)
8526 int port = BP_PORT(bp);
8527 int func = BP_FUNC(bp);
8530 /* Disable the function in the FW */
8531 REG_WR8(bp, BAR_XSTRORM_INTMEM + XSTORM_FUNC_EN_OFFSET(func), 0);
8532 REG_WR8(bp, BAR_CSTRORM_INTMEM + CSTORM_FUNC_EN_OFFSET(func), 0);
8533 REG_WR8(bp, BAR_TSTRORM_INTMEM + TSTORM_FUNC_EN_OFFSET(func), 0);
8534 REG_WR8(bp, BAR_USTRORM_INTMEM + USTORM_FUNC_EN_OFFSET(func), 0);
8537 for_each_eth_queue(bp, i) {
8538 struct bnx2x_fastpath *fp = &bp->fp[i];
8539 REG_WR8(bp, BAR_CSTRORM_INTMEM +
8540 CSTORM_STATUS_BLOCK_DATA_STATE_OFFSET(fp->fw_sb_id),
8544 if (CNIC_LOADED(bp))
8546 REG_WR8(bp, BAR_CSTRORM_INTMEM +
8547 CSTORM_STATUS_BLOCK_DATA_STATE_OFFSET
8548 (bnx2x_cnic_fw_sb_id(bp)), SB_DISABLED);
8551 REG_WR8(bp, BAR_CSTRORM_INTMEM +
8552 CSTORM_SP_STATUS_BLOCK_DATA_STATE_OFFSET(func),
8555 for (i = 0; i < XSTORM_SPQ_DATA_SIZE / 4; i++)
8556 REG_WR(bp, BAR_XSTRORM_INTMEM + XSTORM_SPQ_DATA_OFFSET(func),
8560 if (bp->common.int_block == INT_BLOCK_HC) {
8561 REG_WR(bp, HC_REG_LEADING_EDGE_0 + port*8, 0);
8562 REG_WR(bp, HC_REG_TRAILING_EDGE_0 + port*8, 0);
8564 REG_WR(bp, IGU_REG_LEADING_EDGE_LATCH, 0);
8565 REG_WR(bp, IGU_REG_TRAILING_EDGE_LATCH, 0);
8568 if (CNIC_LOADED(bp)) {
8569 /* Disable Timer scan */
8570 REG_WR(bp, TM_REG_EN_LINEAR0_TIMER + port*4, 0);
8572 * Wait for at least 10ms and up to 2 second for the timers
8575 for (i = 0; i < 200; i++) {
8576 usleep_range(10000, 20000);
8577 if (!REG_RD(bp, TM_REG_LIN0_SCAN_ON + port*4))
8582 bnx2x_clear_func_ilt(bp, func);
8584 /* Timers workaround bug for E2: if this is vnic-3,
8585 * we need to set the entire ilt range for this timers.
8587 if (!CHIP_IS_E1x(bp) && BP_VN(bp) == 3) {
8588 struct ilt_client_info ilt_cli;
8589 /* use dummy TM client */
8590 memset(&ilt_cli, 0, sizeof(struct ilt_client_info));
8592 ilt_cli.end = ILT_NUM_PAGE_ENTRIES - 1;
8593 ilt_cli.client_num = ILT_CLIENT_TM;
8595 bnx2x_ilt_boundry_init_op(bp, &ilt_cli, 0, INITOP_CLEAR);
8598 /* this assumes that reset_port() called before reset_func()*/
8599 if (!CHIP_IS_E1x(bp))
8600 bnx2x_pf_disable(bp);
8605 static void bnx2x_reset_port(struct bnx2x *bp)
8607 int port = BP_PORT(bp);
8610 /* Reset physical Link */
8611 bnx2x__link_reset(bp);
8613 REG_WR(bp, NIG_REG_MASK_INTERRUPT_PORT0 + port*4, 0);
8615 /* Do not rcv packets to BRB */
8616 REG_WR(bp, NIG_REG_LLH0_BRB1_DRV_MASK + port*4, 0x0);
8617 /* Do not direct rcv packets that are not for MCP to the BRB */
8618 REG_WR(bp, (port ? NIG_REG_LLH1_BRB1_NOT_MCP :
8619 NIG_REG_LLH0_BRB1_NOT_MCP), 0x0);
8622 REG_WR(bp, MISC_REG_AEU_MASK_ATTN_FUNC_0 + port*4, 0);
8625 /* Check for BRB port occupancy */
8626 val = REG_RD(bp, BRB1_REG_PORT_NUM_OCC_BLOCKS_0 + port*4);
8628 DP(NETIF_MSG_IFDOWN,
8629 "BRB1 is not empty %d blocks are occupied\n", val);
8631 /* TODO: Close Doorbell port? */
8634 static int bnx2x_reset_hw(struct bnx2x *bp, u32 load_code)
8636 struct bnx2x_func_state_params func_params = {NULL};
8638 /* Prepare parameters for function state transitions */
8639 __set_bit(RAMROD_COMP_WAIT, &func_params.ramrod_flags);
8641 func_params.f_obj = &bp->func_obj;
8642 func_params.cmd = BNX2X_F_CMD_HW_RESET;
8644 func_params.params.hw_init.load_phase = load_code;
8646 return bnx2x_func_state_change(bp, &func_params);
8649 static int bnx2x_func_stop(struct bnx2x *bp)
8651 struct bnx2x_func_state_params func_params = {NULL};
8654 /* Prepare parameters for function state transitions */
8655 __set_bit(RAMROD_COMP_WAIT, &func_params.ramrod_flags);
8656 func_params.f_obj = &bp->func_obj;
8657 func_params.cmd = BNX2X_F_CMD_STOP;
8660 * Try to stop the function the 'good way'. If fails (in case
8661 * of a parity error during bnx2x_chip_cleanup()) and we are
8662 * not in a debug mode, perform a state transaction in order to
8663 * enable further HW_RESET transaction.
8665 rc = bnx2x_func_state_change(bp, &func_params);
8667 #ifdef BNX2X_STOP_ON_ERROR
8670 BNX2X_ERR("FUNC_STOP ramrod failed. Running a dry transaction\n");
8671 __set_bit(RAMROD_DRV_CLR_ONLY, &func_params.ramrod_flags);
8672 return bnx2x_func_state_change(bp, &func_params);
8680 * bnx2x_send_unload_req - request unload mode from the MCP.
8682 * @bp: driver handle
8683 * @unload_mode: requested function's unload mode
8685 * Return unload mode returned by the MCP: COMMON, PORT or FUNC.
8687 u32 bnx2x_send_unload_req(struct bnx2x *bp, int unload_mode)
8690 int port = BP_PORT(bp);
8692 /* Select the UNLOAD request mode */
8693 if (unload_mode == UNLOAD_NORMAL)
8694 reset_code = DRV_MSG_CODE_UNLOAD_REQ_WOL_DIS;
8696 else if (bp->flags & NO_WOL_FLAG)
8697 reset_code = DRV_MSG_CODE_UNLOAD_REQ_WOL_MCP;
8700 u32 emac_base = port ? GRCBASE_EMAC1 : GRCBASE_EMAC0;
8701 u8 *mac_addr = bp->dev->dev_addr;
8702 struct pci_dev *pdev = bp->pdev;
8706 /* The mac address is written to entries 1-4 to
8707 * preserve entry 0 which is used by the PMF
8709 u8 entry = (BP_VN(bp) + 1)*8;
8711 val = (mac_addr[0] << 8) | mac_addr[1];
8712 EMAC_WR(bp, EMAC_REG_EMAC_MAC_MATCH + entry, val);
8714 val = (mac_addr[2] << 24) | (mac_addr[3] << 16) |
8715 (mac_addr[4] << 8) | mac_addr[5];
8716 EMAC_WR(bp, EMAC_REG_EMAC_MAC_MATCH + entry + 4, val);
8718 /* Enable the PME and clear the status */
8719 pci_read_config_word(pdev, pdev->pm_cap + PCI_PM_CTRL, &pmc);
8720 pmc |= PCI_PM_CTRL_PME_ENABLE | PCI_PM_CTRL_PME_STATUS;
8721 pci_write_config_word(pdev, pdev->pm_cap + PCI_PM_CTRL, pmc);
8723 reset_code = DRV_MSG_CODE_UNLOAD_REQ_WOL_EN;
8726 reset_code = DRV_MSG_CODE_UNLOAD_REQ_WOL_DIS;
8728 /* Send the request to the MCP */
8730 reset_code = bnx2x_fw_command(bp, reset_code, 0);
8732 int path = BP_PATH(bp);
8734 DP(NETIF_MSG_IFDOWN, "NO MCP - load counts[%d] %d, %d, %d\n",
8735 path, load_count[path][0], load_count[path][1],
8736 load_count[path][2]);
8737 load_count[path][0]--;
8738 load_count[path][1 + port]--;
8739 DP(NETIF_MSG_IFDOWN, "NO MCP - new load counts[%d] %d, %d, %d\n",
8740 path, load_count[path][0], load_count[path][1],
8741 load_count[path][2]);
8742 if (load_count[path][0] == 0)
8743 reset_code = FW_MSG_CODE_DRV_UNLOAD_COMMON;
8744 else if (load_count[path][1 + port] == 0)
8745 reset_code = FW_MSG_CODE_DRV_UNLOAD_PORT;
8747 reset_code = FW_MSG_CODE_DRV_UNLOAD_FUNCTION;
8754 * bnx2x_send_unload_done - send UNLOAD_DONE command to the MCP.
8756 * @bp: driver handle
8757 * @keep_link: true iff link should be kept up
8759 void bnx2x_send_unload_done(struct bnx2x *bp, bool keep_link)
8761 u32 reset_param = keep_link ? DRV_MSG_CODE_UNLOAD_SKIP_LINK_RESET : 0;
8763 /* Report UNLOAD_DONE to MCP */
8765 bnx2x_fw_command(bp, DRV_MSG_CODE_UNLOAD_DONE, reset_param);
8768 static int bnx2x_func_wait_started(struct bnx2x *bp)
8771 int msix = (bp->flags & USING_MSIX_FLAG) ? 1 : 0;
8777 * (assumption: No Attention from MCP at this stage)
8778 * PMF probably in the middle of TX disable/enable transaction
8779 * 1. Sync IRS for default SB
8780 * 2. Sync SP queue - this guarantees us that attention handling started
8781 * 3. Wait, that TX disable/enable transaction completes
8783 * 1+2 guarantee that if DCBx attention was scheduled it already changed
8784 * pending bit of transaction from STARTED-->TX_STOPPED, if we already
8785 * received completion for the transaction the state is TX_STOPPED.
8786 * State will return to STARTED after completion of TX_STOPPED-->STARTED
8790 /* make sure default SB ISR is done */
8792 synchronize_irq(bp->msix_table[0].vector);
8794 synchronize_irq(bp->pdev->irq);
8796 flush_workqueue(bnx2x_wq);
8798 while (bnx2x_func_get_state(bp, &bp->func_obj) !=
8799 BNX2X_F_STATE_STARTED && tout--)
8802 if (bnx2x_func_get_state(bp, &bp->func_obj) !=
8803 BNX2X_F_STATE_STARTED) {
8804 #ifdef BNX2X_STOP_ON_ERROR
8805 BNX2X_ERR("Wrong function state\n");
8809 * Failed to complete the transaction in a "good way"
8810 * Force both transactions with CLR bit
8812 struct bnx2x_func_state_params func_params = {NULL};
8814 DP(NETIF_MSG_IFDOWN,
8815 "Hmmm... Unexpected function state! Forcing STARTED-->TX_ST0PPED-->STARTED\n");
8817 func_params.f_obj = &bp->func_obj;
8818 __set_bit(RAMROD_DRV_CLR_ONLY,
8819 &func_params.ramrod_flags);
8821 /* STARTED-->TX_ST0PPED */
8822 func_params.cmd = BNX2X_F_CMD_TX_STOP;
8823 bnx2x_func_state_change(bp, &func_params);
8825 /* TX_ST0PPED-->STARTED */
8826 func_params.cmd = BNX2X_F_CMD_TX_START;
8827 return bnx2x_func_state_change(bp, &func_params);
8834 void bnx2x_chip_cleanup(struct bnx2x *bp, int unload_mode, bool keep_link)
8836 int port = BP_PORT(bp);
8839 struct bnx2x_mcast_ramrod_params rparam = {NULL};
8842 /* Wait until tx fastpath tasks complete */
8843 for_each_tx_queue(bp, i) {
8844 struct bnx2x_fastpath *fp = &bp->fp[i];
8846 for_each_cos_in_tx_queue(fp, cos)
8847 rc = bnx2x_clean_tx_queue(bp, fp->txdata_ptr[cos]);
8848 #ifdef BNX2X_STOP_ON_ERROR
8854 /* Give HW time to discard old tx messages */
8855 usleep_range(1000, 2000);
8857 /* Clean all ETH MACs */
8858 rc = bnx2x_del_all_macs(bp, &bp->sp_objs[0].mac_obj, BNX2X_ETH_MAC,
8861 BNX2X_ERR("Failed to delete all ETH macs: %d\n", rc);
8863 /* Clean up UC list */
8864 rc = bnx2x_del_all_macs(bp, &bp->sp_objs[0].mac_obj, BNX2X_UC_LIST_MAC,
8867 BNX2X_ERR("Failed to schedule DEL commands for UC MACs list: %d\n",
8871 if (!CHIP_IS_E1(bp))
8872 REG_WR(bp, NIG_REG_LLH0_FUNC_EN + port*8, 0);
8874 /* Set "drop all" (stop Rx).
8875 * We need to take a netif_addr_lock() here in order to prevent
8876 * a race between the completion code and this code.
8878 netif_addr_lock_bh(bp->dev);
8879 /* Schedule the rx_mode command */
8880 if (test_bit(BNX2X_FILTER_RX_MODE_PENDING, &bp->sp_state))
8881 set_bit(BNX2X_FILTER_RX_MODE_SCHED, &bp->sp_state);
8883 bnx2x_set_storm_rx_mode(bp);
8885 /* Cleanup multicast configuration */
8886 rparam.mcast_obj = &bp->mcast_obj;
8887 rc = bnx2x_config_mcast(bp, &rparam, BNX2X_MCAST_CMD_DEL);
8889 BNX2X_ERR("Failed to send DEL multicast command: %d\n", rc);
8891 netif_addr_unlock_bh(bp->dev);
8893 bnx2x_iov_chip_cleanup(bp);
8896 * Send the UNLOAD_REQUEST to the MCP. This will return if
8897 * this function should perform FUNC, PORT or COMMON HW
8900 reset_code = bnx2x_send_unload_req(bp, unload_mode);
8903 * (assumption: No Attention from MCP at this stage)
8904 * PMF probably in the middle of TX disable/enable transaction
8906 rc = bnx2x_func_wait_started(bp);
8908 BNX2X_ERR("bnx2x_func_wait_started failed\n");
8909 #ifdef BNX2X_STOP_ON_ERROR
8914 /* Close multi and leading connections
8915 * Completions for ramrods are collected in a synchronous way
8917 for_each_eth_queue(bp, i)
8918 if (bnx2x_stop_queue(bp, i))
8919 #ifdef BNX2X_STOP_ON_ERROR
8925 if (CNIC_LOADED(bp)) {
8926 for_each_cnic_queue(bp, i)
8927 if (bnx2x_stop_queue(bp, i))
8928 #ifdef BNX2X_STOP_ON_ERROR
8935 /* If SP settings didn't get completed so far - something
8936 * very wrong has happen.
8938 if (!bnx2x_wait_sp_comp(bp, ~0x0UL))
8939 BNX2X_ERR("Hmmm... Common slow path ramrods got stuck!\n");
8941 #ifndef BNX2X_STOP_ON_ERROR
8944 rc = bnx2x_func_stop(bp);
8946 BNX2X_ERR("Function stop failed!\n");
8947 #ifdef BNX2X_STOP_ON_ERROR
8952 /* Disable HW interrupts, NAPI */
8953 bnx2x_netif_stop(bp, 1);
8954 /* Delete all NAPI objects */
8955 bnx2x_del_all_napi(bp);
8956 if (CNIC_LOADED(bp))
8957 bnx2x_del_all_napi_cnic(bp);
8962 /* Reset the chip */
8963 rc = bnx2x_reset_hw(bp, reset_code);
8965 BNX2X_ERR("HW_RESET failed\n");
8967 /* Report UNLOAD_DONE to MCP */
8968 bnx2x_send_unload_done(bp, keep_link);
8971 void bnx2x_disable_close_the_gate(struct bnx2x *bp)
8975 DP(NETIF_MSG_IFDOWN, "Disabling \"close the gates\"\n");
8977 if (CHIP_IS_E1(bp)) {
8978 int port = BP_PORT(bp);
8979 u32 addr = port ? MISC_REG_AEU_MASK_ATTN_FUNC_1 :
8980 MISC_REG_AEU_MASK_ATTN_FUNC_0;
8982 val = REG_RD(bp, addr);
8984 REG_WR(bp, addr, val);
8986 val = REG_RD(bp, MISC_REG_AEU_GENERAL_MASK);
8987 val &= ~(MISC_AEU_GENERAL_MASK_REG_AEU_PXP_CLOSE_MASK |
8988 MISC_AEU_GENERAL_MASK_REG_AEU_NIG_CLOSE_MASK);
8989 REG_WR(bp, MISC_REG_AEU_GENERAL_MASK, val);
8993 /* Close gates #2, #3 and #4: */
8994 static void bnx2x_set_234_gates(struct bnx2x *bp, bool close)
8998 /* Gates #2 and #4a are closed/opened for "not E1" only */
8999 if (!CHIP_IS_E1(bp)) {
9001 REG_WR(bp, PXP_REG_HST_DISCARD_DOORBELLS, !!close);
9003 REG_WR(bp, PXP_REG_HST_DISCARD_INTERNAL_WRITES, !!close);
9007 if (CHIP_IS_E1x(bp)) {
9008 /* Prevent interrupts from HC on both ports */
9009 val = REG_RD(bp, HC_REG_CONFIG_1);
9010 REG_WR(bp, HC_REG_CONFIG_1,
9011 (!close) ? (val | HC_CONFIG_1_REG_BLOCK_DISABLE_1) :
9012 (val & ~(u32)HC_CONFIG_1_REG_BLOCK_DISABLE_1));
9014 val = REG_RD(bp, HC_REG_CONFIG_0);
9015 REG_WR(bp, HC_REG_CONFIG_0,
9016 (!close) ? (val | HC_CONFIG_0_REG_BLOCK_DISABLE_0) :
9017 (val & ~(u32)HC_CONFIG_0_REG_BLOCK_DISABLE_0));
9019 /* Prevent incoming interrupts in IGU */
9020 val = REG_RD(bp, IGU_REG_BLOCK_CONFIGURATION);
9022 REG_WR(bp, IGU_REG_BLOCK_CONFIGURATION,
9024 (val | IGU_BLOCK_CONFIGURATION_REG_BLOCK_ENABLE) :
9025 (val & ~(u32)IGU_BLOCK_CONFIGURATION_REG_BLOCK_ENABLE));
9028 DP(NETIF_MSG_HW | NETIF_MSG_IFUP, "%s gates #2, #3 and #4\n",
9029 close ? "closing" : "opening");
9033 #define SHARED_MF_CLP_MAGIC 0x80000000 /* `magic' bit */
9035 static void bnx2x_clp_reset_prep(struct bnx2x *bp, u32 *magic_val)
9037 /* Do some magic... */
9038 u32 val = MF_CFG_RD(bp, shared_mf_config.clp_mb);
9039 *magic_val = val & SHARED_MF_CLP_MAGIC;
9040 MF_CFG_WR(bp, shared_mf_config.clp_mb, val | SHARED_MF_CLP_MAGIC);
9044 * bnx2x_clp_reset_done - restore the value of the `magic' bit.
9046 * @bp: driver handle
9047 * @magic_val: old value of the `magic' bit.
9049 static void bnx2x_clp_reset_done(struct bnx2x *bp, u32 magic_val)
9051 /* Restore the `magic' bit value... */
9052 u32 val = MF_CFG_RD(bp, shared_mf_config.clp_mb);
9053 MF_CFG_WR(bp, shared_mf_config.clp_mb,
9054 (val & (~SHARED_MF_CLP_MAGIC)) | magic_val);
9058 * bnx2x_reset_mcp_prep - prepare for MCP reset.
9060 * @bp: driver handle
9061 * @magic_val: old value of 'magic' bit.
9063 * Takes care of CLP configurations.
9065 static void bnx2x_reset_mcp_prep(struct bnx2x *bp, u32 *magic_val)
9068 u32 validity_offset;
9070 DP(NETIF_MSG_HW | NETIF_MSG_IFUP, "Starting\n");
9072 /* Set `magic' bit in order to save MF config */
9073 if (!CHIP_IS_E1(bp))
9074 bnx2x_clp_reset_prep(bp, magic_val);
9076 /* Get shmem offset */
9077 shmem = REG_RD(bp, MISC_REG_SHARED_MEM_ADDR);
9079 offsetof(struct shmem_region, validity_map[BP_PORT(bp)]);
9081 /* Clear validity map flags */
9083 REG_WR(bp, shmem + validity_offset, 0);
9086 #define MCP_TIMEOUT 5000 /* 5 seconds (in ms) */
9087 #define MCP_ONE_TIMEOUT 100 /* 100 ms */
9090 * bnx2x_mcp_wait_one - wait for MCP_ONE_TIMEOUT
9092 * @bp: driver handle
9094 static void bnx2x_mcp_wait_one(struct bnx2x *bp)
9096 /* special handling for emulation and FPGA,
9097 wait 10 times longer */
9098 if (CHIP_REV_IS_SLOW(bp))
9099 msleep(MCP_ONE_TIMEOUT*10);
9101 msleep(MCP_ONE_TIMEOUT);
9105 * initializes bp->common.shmem_base and waits for validity signature to appear
9107 static int bnx2x_init_shmem(struct bnx2x *bp)
9113 bp->common.shmem_base = REG_RD(bp, MISC_REG_SHARED_MEM_ADDR);
9114 if (bp->common.shmem_base) {
9115 val = SHMEM_RD(bp, validity_map[BP_PORT(bp)]);
9116 if (val & SHR_MEM_VALIDITY_MB)
9120 bnx2x_mcp_wait_one(bp);
9122 } while (cnt++ < (MCP_TIMEOUT / MCP_ONE_TIMEOUT));
9124 BNX2X_ERR("BAD MCP validity signature\n");
9129 static int bnx2x_reset_mcp_comp(struct bnx2x *bp, u32 magic_val)
9131 int rc = bnx2x_init_shmem(bp);
9133 /* Restore the `magic' bit value */
9134 if (!CHIP_IS_E1(bp))
9135 bnx2x_clp_reset_done(bp, magic_val);
9140 static void bnx2x_pxp_prep(struct bnx2x *bp)
9142 if (!CHIP_IS_E1(bp)) {
9143 REG_WR(bp, PXP2_REG_RD_START_INIT, 0);
9144 REG_WR(bp, PXP2_REG_RQ_RBC_DONE, 0);
9150 * Reset the whole chip except for:
9152 * - PCI Glue, PSWHST, PXP/PXP2 RF (all controlled by
9155 * - MISC (including AEU)
9159 static void bnx2x_process_kill_chip_reset(struct bnx2x *bp, bool global)
9161 u32 not_reset_mask1, reset_mask1, not_reset_mask2, reset_mask2;
9162 u32 global_bits2, stay_reset2;
9165 * Bits that have to be set in reset_mask2 if we want to reset 'global'
9166 * (per chip) blocks.
9169 MISC_REGISTERS_RESET_REG_2_RST_MCP_N_RESET_CMN_CPU |
9170 MISC_REGISTERS_RESET_REG_2_RST_MCP_N_RESET_CMN_CORE;
9172 /* Don't reset the following blocks.
9173 * Important: per port blocks (such as EMAC, BMAC, UMAC) can't be
9174 * reset, as in 4 port device they might still be owned
9175 * by the MCP (there is only one leader per path).
9178 MISC_REGISTERS_RESET_REG_1_RST_HC |
9179 MISC_REGISTERS_RESET_REG_1_RST_PXPV |
9180 MISC_REGISTERS_RESET_REG_1_RST_PXP;
9183 MISC_REGISTERS_RESET_REG_2_RST_PCI_MDIO |
9184 MISC_REGISTERS_RESET_REG_2_RST_EMAC0_HARD_CORE |
9185 MISC_REGISTERS_RESET_REG_2_RST_EMAC1_HARD_CORE |
9186 MISC_REGISTERS_RESET_REG_2_RST_MISC_CORE |
9187 MISC_REGISTERS_RESET_REG_2_RST_RBCN |
9188 MISC_REGISTERS_RESET_REG_2_RST_GRC |
9189 MISC_REGISTERS_RESET_REG_2_RST_MCP_N_RESET_REG_HARD_CORE |
9190 MISC_REGISTERS_RESET_REG_2_RST_MCP_N_HARD_CORE_RST_B |
9191 MISC_REGISTERS_RESET_REG_2_RST_ATC |
9192 MISC_REGISTERS_RESET_REG_2_PGLC |
9193 MISC_REGISTERS_RESET_REG_2_RST_BMAC0 |
9194 MISC_REGISTERS_RESET_REG_2_RST_BMAC1 |
9195 MISC_REGISTERS_RESET_REG_2_RST_EMAC0 |
9196 MISC_REGISTERS_RESET_REG_2_RST_EMAC1 |
9197 MISC_REGISTERS_RESET_REG_2_UMAC0 |
9198 MISC_REGISTERS_RESET_REG_2_UMAC1;
9201 * Keep the following blocks in reset:
9202 * - all xxMACs are handled by the bnx2x_link code.
9205 MISC_REGISTERS_RESET_REG_2_XMAC |
9206 MISC_REGISTERS_RESET_REG_2_XMAC_SOFT;
9208 /* Full reset masks according to the chip */
9209 reset_mask1 = 0xffffffff;
9212 reset_mask2 = 0xffff;
9213 else if (CHIP_IS_E1H(bp))
9214 reset_mask2 = 0x1ffff;
9215 else if (CHIP_IS_E2(bp))
9216 reset_mask2 = 0xfffff;
9217 else /* CHIP_IS_E3 */
9218 reset_mask2 = 0x3ffffff;
9220 /* Don't reset global blocks unless we need to */
9222 reset_mask2 &= ~global_bits2;
9225 * In case of attention in the QM, we need to reset PXP
9226 * (MISC_REGISTERS_RESET_REG_2_RST_PXP_RQ_RD_WR) before QM
9227 * because otherwise QM reset would release 'close the gates' shortly
9228 * before resetting the PXP, then the PSWRQ would send a write
9229 * request to PGLUE. Then when PXP is reset, PGLUE would try to
9230 * read the payload data from PSWWR, but PSWWR would not
9231 * respond. The write queue in PGLUE would stuck, dmae commands
9232 * would not return. Therefore it's important to reset the second
9233 * reset register (containing the
9234 * MISC_REGISTERS_RESET_REG_2_RST_PXP_RQ_RD_WR bit) before the
9235 * first one (containing the MISC_REGISTERS_RESET_REG_1_RST_QM
9238 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR,
9239 reset_mask2 & (~not_reset_mask2));
9241 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_CLEAR,
9242 reset_mask1 & (~not_reset_mask1));
9247 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_SET,
9248 reset_mask2 & (~stay_reset2));
9253 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_SET, reset_mask1);
9258 * bnx2x_er_poll_igu_vq - poll for pending writes bit.
9259 * It should get cleared in no more than 1s.
9261 * @bp: driver handle
9263 * It should get cleared in no more than 1s. Returns 0 if
9264 * pending writes bit gets cleared.
9266 static int bnx2x_er_poll_igu_vq(struct bnx2x *bp)
9272 pend_bits = REG_RD(bp, IGU_REG_PENDING_BITS_STATUS);
9277 usleep_range(1000, 2000);
9278 } while (cnt-- > 0);
9281 BNX2X_ERR("Still pending IGU requests pend_bits=%x!\n",
9289 static int bnx2x_process_kill(struct bnx2x *bp, bool global)
9293 u32 sr_cnt, blk_cnt, port_is_idle_0, port_is_idle_1, pgl_exp_rom2;
9296 /* Empty the Tetris buffer, wait for 1s */
9298 sr_cnt = REG_RD(bp, PXP2_REG_RD_SR_CNT);
9299 blk_cnt = REG_RD(bp, PXP2_REG_RD_BLK_CNT);
9300 port_is_idle_0 = REG_RD(bp, PXP2_REG_RD_PORT_IS_IDLE_0);
9301 port_is_idle_1 = REG_RD(bp, PXP2_REG_RD_PORT_IS_IDLE_1);
9302 pgl_exp_rom2 = REG_RD(bp, PXP2_REG_PGL_EXP_ROM2);
9304 tags_63_32 = REG_RD(bp, PGLUE_B_REG_TAGS_63_32);
9306 if ((sr_cnt == 0x7e) && (blk_cnt == 0xa0) &&
9307 ((port_is_idle_0 & 0x1) == 0x1) &&
9308 ((port_is_idle_1 & 0x1) == 0x1) &&
9309 (pgl_exp_rom2 == 0xffffffff) &&
9310 (!CHIP_IS_E3(bp) || (tags_63_32 == 0xffffffff)))
9312 usleep_range(1000, 2000);
9313 } while (cnt-- > 0);
9316 BNX2X_ERR("Tetris buffer didn't get empty or there are still outstanding read requests after 1s!\n");
9317 BNX2X_ERR("sr_cnt=0x%08x, blk_cnt=0x%08x, port_is_idle_0=0x%08x, port_is_idle_1=0x%08x, pgl_exp_rom2=0x%08x\n",
9318 sr_cnt, blk_cnt, port_is_idle_0, port_is_idle_1,
9325 /* Close gates #2, #3 and #4 */
9326 bnx2x_set_234_gates(bp, true);
9328 /* Poll for IGU VQs for 57712 and newer chips */
9329 if (!CHIP_IS_E1x(bp) && bnx2x_er_poll_igu_vq(bp))
9332 /* TBD: Indicate that "process kill" is in progress to MCP */
9334 /* Clear "unprepared" bit */
9335 REG_WR(bp, MISC_REG_UNPREPARED, 0);
9338 /* Make sure all is written to the chip before the reset */
9341 /* Wait for 1ms to empty GLUE and PCI-E core queues,
9342 * PSWHST, GRC and PSWRD Tetris buffer.
9344 usleep_range(1000, 2000);
9346 /* Prepare to chip reset: */
9349 bnx2x_reset_mcp_prep(bp, &val);
9355 /* reset the chip */
9356 bnx2x_process_kill_chip_reset(bp, global);
9359 /* clear errors in PGB */
9360 if (!CHIP_IS_E1x(bp))
9361 REG_WR(bp, PGLUE_B_REG_LATCHED_ERRORS_CLR, 0x7f);
9363 /* Recover after reset: */
9365 if (global && bnx2x_reset_mcp_comp(bp, val))
9368 /* TBD: Add resetting the NO_MCP mode DB here */
9370 /* Open the gates #2, #3 and #4 */
9371 bnx2x_set_234_gates(bp, false);
9373 /* TBD: IGU/AEU preparation bring back the AEU/IGU to a
9374 * reset state, re-enable attentions. */
9379 static int bnx2x_leader_reset(struct bnx2x *bp)
9382 bool global = bnx2x_reset_is_global(bp);
9385 /* if not going to reset MCP - load "fake" driver to reset HW while
9386 * driver is owner of the HW
9388 if (!global && !BP_NOMCP(bp)) {
9389 load_code = bnx2x_fw_command(bp, DRV_MSG_CODE_LOAD_REQ,
9390 DRV_MSG_CODE_LOAD_REQ_WITH_LFA);
9392 BNX2X_ERR("MCP response failure, aborting\n");
9394 goto exit_leader_reset;
9396 if ((load_code != FW_MSG_CODE_DRV_LOAD_COMMON_CHIP) &&
9397 (load_code != FW_MSG_CODE_DRV_LOAD_COMMON)) {
9398 BNX2X_ERR("MCP unexpected resp, aborting\n");
9400 goto exit_leader_reset2;
9402 load_code = bnx2x_fw_command(bp, DRV_MSG_CODE_LOAD_DONE, 0);
9404 BNX2X_ERR("MCP response failure, aborting\n");
9406 goto exit_leader_reset2;
9410 /* Try to recover after the failure */
9411 if (bnx2x_process_kill(bp, global)) {
9412 BNX2X_ERR("Something bad had happen on engine %d! Aii!\n",
9415 goto exit_leader_reset2;
9419 * Clear RESET_IN_PROGRES and RESET_GLOBAL bits and update the driver
9422 bnx2x_set_reset_done(bp);
9424 bnx2x_clear_reset_global(bp);
9427 /* unload "fake driver" if it was loaded */
9428 if (!global && !BP_NOMCP(bp)) {
9429 bnx2x_fw_command(bp, DRV_MSG_CODE_UNLOAD_REQ_WOL_MCP, 0);
9430 bnx2x_fw_command(bp, DRV_MSG_CODE_UNLOAD_DONE, 0);
9434 bnx2x_release_leader_lock(bp);
9439 static void bnx2x_recovery_failed(struct bnx2x *bp)
9441 netdev_err(bp->dev, "Recovery has failed. Power cycle is needed.\n");
9443 /* Disconnect this device */
9444 netif_device_detach(bp->dev);
9447 * Block ifup for all function on this engine until "process kill"
9450 bnx2x_set_reset_in_progress(bp);
9452 /* Shut down the power */
9453 bnx2x_set_power_state(bp, PCI_D3hot);
9455 bp->recovery_state = BNX2X_RECOVERY_FAILED;
9461 * Assumption: runs under rtnl lock. This together with the fact
9462 * that it's called only from bnx2x_sp_rtnl() ensure that it
9463 * will never be called when netif_running(bp->dev) is false.
9465 static void bnx2x_parity_recover(struct bnx2x *bp)
9467 bool global = false;
9468 u32 error_recovered, error_unrecovered;
9471 DP(NETIF_MSG_HW, "Handling parity\n");
9473 switch (bp->recovery_state) {
9474 case BNX2X_RECOVERY_INIT:
9475 DP(NETIF_MSG_HW, "State is BNX2X_RECOVERY_INIT\n");
9476 is_parity = bnx2x_chk_parity_attn(bp, &global, false);
9477 WARN_ON(!is_parity);
9479 /* Try to get a LEADER_LOCK HW lock */
9480 if (bnx2x_trylock_leader_lock(bp)) {
9481 bnx2x_set_reset_in_progress(bp);
9483 * Check if there is a global attention and if
9484 * there was a global attention, set the global
9489 bnx2x_set_reset_global(bp);
9494 /* Stop the driver */
9495 /* If interface has been removed - break */
9496 if (bnx2x_nic_unload(bp, UNLOAD_RECOVERY, false))
9499 bp->recovery_state = BNX2X_RECOVERY_WAIT;
9501 /* Ensure "is_leader", MCP command sequence and
9502 * "recovery_state" update values are seen on other
9508 case BNX2X_RECOVERY_WAIT:
9509 DP(NETIF_MSG_HW, "State is BNX2X_RECOVERY_WAIT\n");
9510 if (bp->is_leader) {
9511 int other_engine = BP_PATH(bp) ? 0 : 1;
9512 bool other_load_status =
9513 bnx2x_get_load_status(bp, other_engine);
9515 bnx2x_get_load_status(bp, BP_PATH(bp));
9516 global = bnx2x_reset_is_global(bp);
9519 * In case of a parity in a global block, let
9520 * the first leader that performs a
9521 * leader_reset() reset the global blocks in
9522 * order to clear global attentions. Otherwise
9523 * the gates will remain closed for that
9527 (global && other_load_status)) {
9528 /* Wait until all other functions get
9531 schedule_delayed_work(&bp->sp_rtnl_task,
9535 /* If all other functions got down -
9536 * try to bring the chip back to
9537 * normal. In any case it's an exit
9538 * point for a leader.
9540 if (bnx2x_leader_reset(bp)) {
9541 bnx2x_recovery_failed(bp);
9545 /* If we are here, means that the
9546 * leader has succeeded and doesn't
9547 * want to be a leader any more. Try
9548 * to continue as a none-leader.
9552 } else { /* non-leader */
9553 if (!bnx2x_reset_is_done(bp, BP_PATH(bp))) {
9554 /* Try to get a LEADER_LOCK HW lock as
9555 * long as a former leader may have
9556 * been unloaded by the user or
9557 * released a leadership by another
9560 if (bnx2x_trylock_leader_lock(bp)) {
9561 /* I'm a leader now! Restart a
9568 schedule_delayed_work(&bp->sp_rtnl_task,
9574 * If there was a global attention, wait
9575 * for it to be cleared.
9577 if (bnx2x_reset_is_global(bp)) {
9578 schedule_delayed_work(
9585 bp->eth_stats.recoverable_error;
9587 bp->eth_stats.unrecoverable_error;
9588 bp->recovery_state =
9589 BNX2X_RECOVERY_NIC_LOADING;
9590 if (bnx2x_nic_load(bp, LOAD_NORMAL)) {
9591 error_unrecovered++;
9593 "Recovery failed. Power cycle needed\n");
9594 /* Disconnect this device */
9595 netif_device_detach(bp->dev);
9596 /* Shut down the power */
9597 bnx2x_set_power_state(
9601 bp->recovery_state =
9602 BNX2X_RECOVERY_DONE;
9606 bp->eth_stats.recoverable_error =
9608 bp->eth_stats.unrecoverable_error =
9620 static int bnx2x_close(struct net_device *dev);
9622 /* bnx2x_nic_unload() flushes the bnx2x_wq, thus reset task is
9623 * scheduled on a general queue in order to prevent a dead lock.
9625 static void bnx2x_sp_rtnl_task(struct work_struct *work)
9627 struct bnx2x *bp = container_of(work, struct bnx2x, sp_rtnl_task.work);
9631 if (!netif_running(bp->dev)) {
9636 if (unlikely(bp->recovery_state != BNX2X_RECOVERY_DONE)) {
9637 #ifdef BNX2X_STOP_ON_ERROR
9638 BNX2X_ERR("recovery flow called but STOP_ON_ERROR defined so reset not done to allow debug dump,\n"
9639 "you will need to reboot when done\n");
9640 goto sp_rtnl_not_reset;
9643 * Clear all pending SP commands as we are going to reset the
9646 bp->sp_rtnl_state = 0;
9649 bnx2x_parity_recover(bp);
9655 if (test_and_clear_bit(BNX2X_SP_RTNL_TX_TIMEOUT, &bp->sp_rtnl_state)) {
9656 #ifdef BNX2X_STOP_ON_ERROR
9657 BNX2X_ERR("recovery flow called but STOP_ON_ERROR defined so reset not done to allow debug dump,\n"
9658 "you will need to reboot when done\n");
9659 goto sp_rtnl_not_reset;
9663 * Clear all pending SP commands as we are going to reset the
9666 bp->sp_rtnl_state = 0;
9669 bnx2x_nic_unload(bp, UNLOAD_NORMAL, true);
9670 bnx2x_nic_load(bp, LOAD_NORMAL);
9675 #ifdef BNX2X_STOP_ON_ERROR
9678 if (test_and_clear_bit(BNX2X_SP_RTNL_SETUP_TC, &bp->sp_rtnl_state))
9679 bnx2x_setup_tc(bp->dev, bp->dcbx_port_params.ets.num_of_cos);
9680 if (test_and_clear_bit(BNX2X_SP_RTNL_AFEX_F_UPDATE, &bp->sp_rtnl_state))
9681 bnx2x_after_function_update(bp);
9683 * in case of fan failure we need to reset id if the "stop on error"
9684 * debug flag is set, since we trying to prevent permanent overheating
9687 if (test_and_clear_bit(BNX2X_SP_RTNL_FAN_FAILURE, &bp->sp_rtnl_state)) {
9688 DP(NETIF_MSG_HW, "fan failure detected. Unloading driver\n");
9689 netif_device_detach(bp->dev);
9690 bnx2x_close(bp->dev);
9695 if (test_and_clear_bit(BNX2X_SP_RTNL_VFPF_MCAST, &bp->sp_rtnl_state)) {
9697 "sending set mcast vf pf channel message from rtnl sp-task\n");
9698 bnx2x_vfpf_set_mcast(bp->dev);
9700 if (test_and_clear_bit(BNX2X_SP_RTNL_VFPF_CHANNEL_DOWN,
9701 &bp->sp_rtnl_state)){
9702 if (!test_bit(__LINK_STATE_NOCARRIER, &bp->dev->state)) {
9703 bnx2x_tx_disable(bp);
9704 BNX2X_ERR("PF indicated channel is not servicable anymore. This means this VF device is no longer operational\n");
9708 if (test_and_clear_bit(BNX2X_SP_RTNL_RX_MODE, &bp->sp_rtnl_state)) {
9709 DP(BNX2X_MSG_SP, "Handling Rx Mode setting\n");
9710 bnx2x_set_rx_mode_inner(bp);
9713 if (test_and_clear_bit(BNX2X_SP_RTNL_HYPERVISOR_VLAN,
9714 &bp->sp_rtnl_state))
9715 bnx2x_pf_set_vfs_vlan(bp);
9717 if (test_and_clear_bit(BNX2X_SP_RTNL_TX_STOP, &bp->sp_rtnl_state)) {
9718 bnx2x_dcbx_stop_hw_tx(bp);
9719 bnx2x_dcbx_resume_hw_tx(bp);
9722 /* work which needs rtnl lock not-taken (as it takes the lock itself and
9723 * can be called from other contexts as well)
9727 /* enable SR-IOV if applicable */
9728 if (IS_SRIOV(bp) && test_and_clear_bit(BNX2X_SP_RTNL_ENABLE_SRIOV,
9729 &bp->sp_rtnl_state)) {
9730 bnx2x_disable_sriov(bp);
9731 bnx2x_enable_sriov(bp);
9735 static void bnx2x_period_task(struct work_struct *work)
9737 struct bnx2x *bp = container_of(work, struct bnx2x, period_task.work);
9739 if (!netif_running(bp->dev))
9740 goto period_task_exit;
9742 if (CHIP_REV_IS_SLOW(bp)) {
9743 BNX2X_ERR("period task called on emulation, ignoring\n");
9744 goto period_task_exit;
9747 bnx2x_acquire_phy_lock(bp);
9749 * The barrier is needed to ensure the ordering between the writing to
9750 * the bp->port.pmf in the bnx2x_nic_load() or bnx2x_pmf_update() and
9755 bnx2x_period_func(&bp->link_params, &bp->link_vars);
9757 /* Re-queue task in 1 sec */
9758 queue_delayed_work(bnx2x_wq, &bp->period_task, 1*HZ);
9761 bnx2x_release_phy_lock(bp);
9767 * Init service functions
9770 u32 bnx2x_get_pretend_reg(struct bnx2x *bp)
9772 u32 base = PXP2_REG_PGL_PRETEND_FUNC_F0;
9773 u32 stride = PXP2_REG_PGL_PRETEND_FUNC_F1 - base;
9774 return base + (BP_ABS_FUNC(bp)) * stride;
9777 static void bnx2x_prev_unload_close_mac(struct bnx2x *bp,
9778 struct bnx2x_mac_vals *vals)
9780 u32 val, base_addr, offset, mask, reset_reg;
9781 bool mac_stopped = false;
9782 u8 port = BP_PORT(bp);
9784 /* reset addresses as they also mark which values were changed */
9785 vals->bmac_addr = 0;
9786 vals->umac_addr = 0;
9787 vals->xmac_addr = 0;
9788 vals->emac_addr = 0;
9790 reset_reg = REG_RD(bp, MISC_REG_RESET_REG_2);
9792 if (!CHIP_IS_E3(bp)) {
9793 val = REG_RD(bp, NIG_REG_BMAC0_REGS_OUT_EN + port * 4);
9794 mask = MISC_REGISTERS_RESET_REG_2_RST_BMAC0 << port;
9795 if ((mask & reset_reg) && val) {
9797 BNX2X_DEV_INFO("Disable bmac Rx\n");
9798 base_addr = BP_PORT(bp) ? NIG_REG_INGRESS_BMAC1_MEM
9799 : NIG_REG_INGRESS_BMAC0_MEM;
9800 offset = CHIP_IS_E2(bp) ? BIGMAC2_REGISTER_BMAC_CONTROL
9801 : BIGMAC_REGISTER_BMAC_CONTROL;
9804 * use rd/wr since we cannot use dmae. This is safe
9805 * since MCP won't access the bus due to the request
9806 * to unload, and no function on the path can be
9807 * loaded at this time.
9809 wb_data[0] = REG_RD(bp, base_addr + offset);
9810 wb_data[1] = REG_RD(bp, base_addr + offset + 0x4);
9811 vals->bmac_addr = base_addr + offset;
9812 vals->bmac_val[0] = wb_data[0];
9813 vals->bmac_val[1] = wb_data[1];
9814 wb_data[0] &= ~BMAC_CONTROL_RX_ENABLE;
9815 REG_WR(bp, vals->bmac_addr, wb_data[0]);
9816 REG_WR(bp, vals->bmac_addr + 0x4, wb_data[1]);
9818 BNX2X_DEV_INFO("Disable emac Rx\n");
9819 vals->emac_addr = NIG_REG_NIG_EMAC0_EN + BP_PORT(bp)*4;
9820 vals->emac_val = REG_RD(bp, vals->emac_addr);
9821 REG_WR(bp, vals->emac_addr, 0);
9824 if (reset_reg & MISC_REGISTERS_RESET_REG_2_XMAC) {
9825 BNX2X_DEV_INFO("Disable xmac Rx\n");
9826 base_addr = BP_PORT(bp) ? GRCBASE_XMAC1 : GRCBASE_XMAC0;
9827 val = REG_RD(bp, base_addr + XMAC_REG_PFC_CTRL_HI);
9828 REG_WR(bp, base_addr + XMAC_REG_PFC_CTRL_HI,
9830 REG_WR(bp, base_addr + XMAC_REG_PFC_CTRL_HI,
9832 vals->xmac_addr = base_addr + XMAC_REG_CTRL;
9833 vals->xmac_val = REG_RD(bp, vals->xmac_addr);
9834 REG_WR(bp, vals->xmac_addr, 0);
9837 mask = MISC_REGISTERS_RESET_REG_2_UMAC0 << port;
9838 if (mask & reset_reg) {
9839 BNX2X_DEV_INFO("Disable umac Rx\n");
9840 base_addr = BP_PORT(bp) ? GRCBASE_UMAC1 : GRCBASE_UMAC0;
9841 vals->umac_addr = base_addr + UMAC_REG_COMMAND_CONFIG;
9842 vals->umac_val = REG_RD(bp, vals->umac_addr);
9843 REG_WR(bp, vals->umac_addr, 0);
9852 #define BNX2X_PREV_UNDI_PROD_ADDR(p) (BAR_TSTRORM_INTMEM + 0x1508 + ((p) << 4))
9853 #define BNX2X_PREV_UNDI_RCQ(val) ((val) & 0xffff)
9854 #define BNX2X_PREV_UNDI_BD(val) ((val) >> 16 & 0xffff)
9855 #define BNX2X_PREV_UNDI_PROD(rcq, bd) ((bd) << 16 | (rcq))
9857 static void bnx2x_prev_unload_undi_inc(struct bnx2x *bp, u8 port, u8 inc)
9860 u32 tmp_reg = REG_RD(bp, BNX2X_PREV_UNDI_PROD_ADDR(port));
9862 rcq = BNX2X_PREV_UNDI_RCQ(tmp_reg) + inc;
9863 bd = BNX2X_PREV_UNDI_BD(tmp_reg) + inc;
9865 tmp_reg = BNX2X_PREV_UNDI_PROD(rcq, bd);
9866 REG_WR(bp, BNX2X_PREV_UNDI_PROD_ADDR(port), tmp_reg);
9868 BNX2X_DEV_INFO("UNDI producer [%d] rings bd -> 0x%04x, rcq -> 0x%04x\n",
9872 static int bnx2x_prev_mcp_done(struct bnx2x *bp)
9874 u32 rc = bnx2x_fw_command(bp, DRV_MSG_CODE_UNLOAD_DONE,
9875 DRV_MSG_CODE_UNLOAD_SKIP_LINK_RESET);
9877 BNX2X_ERR("MCP response failure, aborting\n");
9884 static struct bnx2x_prev_path_list *
9885 bnx2x_prev_path_get_entry(struct bnx2x *bp)
9887 struct bnx2x_prev_path_list *tmp_list;
9889 list_for_each_entry(tmp_list, &bnx2x_prev_list, list)
9890 if (PCI_SLOT(bp->pdev->devfn) == tmp_list->slot &&
9891 bp->pdev->bus->number == tmp_list->bus &&
9892 BP_PATH(bp) == tmp_list->path)
9898 static int bnx2x_prev_path_mark_eeh(struct bnx2x *bp)
9900 struct bnx2x_prev_path_list *tmp_list;
9903 rc = down_interruptible(&bnx2x_prev_sem);
9905 BNX2X_ERR("Received %d when tried to take lock\n", rc);
9909 tmp_list = bnx2x_prev_path_get_entry(bp);
9914 BNX2X_ERR("path %d: Entry does not exist for eeh; Flow occurs before initial insmod is over ?\n",
9918 up(&bnx2x_prev_sem);
9923 static bool bnx2x_prev_is_path_marked(struct bnx2x *bp)
9925 struct bnx2x_prev_path_list *tmp_list;
9928 if (down_trylock(&bnx2x_prev_sem))
9931 tmp_list = bnx2x_prev_path_get_entry(bp);
9933 if (tmp_list->aer) {
9934 DP(NETIF_MSG_HW, "Path %d was marked by AER\n",
9938 BNX2X_DEV_INFO("Path %d was already cleaned from previous drivers\n",
9943 up(&bnx2x_prev_sem);
9948 bool bnx2x_port_after_undi(struct bnx2x *bp)
9950 struct bnx2x_prev_path_list *entry;
9953 down(&bnx2x_prev_sem);
9955 entry = bnx2x_prev_path_get_entry(bp);
9956 val = !!(entry && (entry->undi & (1 << BP_PORT(bp))));
9958 up(&bnx2x_prev_sem);
9963 static int bnx2x_prev_mark_path(struct bnx2x *bp, bool after_undi)
9965 struct bnx2x_prev_path_list *tmp_list;
9968 rc = down_interruptible(&bnx2x_prev_sem);
9970 BNX2X_ERR("Received %d when tried to take lock\n", rc);
9974 /* Check whether the entry for this path already exists */
9975 tmp_list = bnx2x_prev_path_get_entry(bp);
9977 if (!tmp_list->aer) {
9978 BNX2X_ERR("Re-Marking the path.\n");
9980 DP(NETIF_MSG_HW, "Removing AER indication from path %d\n",
9984 up(&bnx2x_prev_sem);
9987 up(&bnx2x_prev_sem);
9989 /* Create an entry for this path and add it */
9990 tmp_list = kmalloc(sizeof(struct bnx2x_prev_path_list), GFP_KERNEL);
9992 BNX2X_ERR("Failed to allocate 'bnx2x_prev_path_list'\n");
9996 tmp_list->bus = bp->pdev->bus->number;
9997 tmp_list->slot = PCI_SLOT(bp->pdev->devfn);
9998 tmp_list->path = BP_PATH(bp);
10000 tmp_list->undi = after_undi ? (1 << BP_PORT(bp)) : 0;
10002 rc = down_interruptible(&bnx2x_prev_sem);
10004 BNX2X_ERR("Received %d when tried to take lock\n", rc);
10007 DP(NETIF_MSG_HW, "Marked path [%d] - finished previous unload\n",
10009 list_add(&tmp_list->list, &bnx2x_prev_list);
10010 up(&bnx2x_prev_sem);
10016 static int bnx2x_do_flr(struct bnx2x *bp)
10018 struct pci_dev *dev = bp->pdev;
10020 if (CHIP_IS_E1x(bp)) {
10021 BNX2X_DEV_INFO("FLR not supported in E1/E1H\n");
10025 /* only bootcode REQ_BC_VER_4_INITIATE_FLR and onwards support flr */
10026 if (bp->common.bc_ver < REQ_BC_VER_4_INITIATE_FLR) {
10027 BNX2X_ERR("FLR not supported by BC_VER: 0x%x\n",
10028 bp->common.bc_ver);
10032 if (!pci_wait_for_pending_transaction(dev))
10033 dev_err(&dev->dev, "transaction is not cleared; proceeding with reset anyway\n");
10035 BNX2X_DEV_INFO("Initiating FLR\n");
10036 bnx2x_fw_command(bp, DRV_MSG_CODE_INITIATE_FLR, 0);
10041 static int bnx2x_prev_unload_uncommon(struct bnx2x *bp)
10045 BNX2X_DEV_INFO("Uncommon unload Flow\n");
10047 /* Test if previous unload process was already finished for this path */
10048 if (bnx2x_prev_is_path_marked(bp))
10049 return bnx2x_prev_mcp_done(bp);
10051 BNX2X_DEV_INFO("Path is unmarked\n");
10053 /* If function has FLR capabilities, and existing FW version matches
10054 * the one required, then FLR will be sufficient to clean any residue
10055 * left by previous driver
10057 rc = bnx2x_nic_load_analyze_req(bp, FW_MSG_CODE_DRV_LOAD_FUNCTION);
10060 /* fw version is good */
10061 BNX2X_DEV_INFO("FW version matches our own. Attempting FLR\n");
10062 rc = bnx2x_do_flr(bp);
10066 /* FLR was performed */
10067 BNX2X_DEV_INFO("FLR successful\n");
10071 BNX2X_DEV_INFO("Could not FLR\n");
10073 /* Close the MCP request, return failure*/
10074 rc = bnx2x_prev_mcp_done(bp);
10076 rc = BNX2X_PREV_WAIT_NEEDED;
10081 static int bnx2x_prev_unload_common(struct bnx2x *bp)
10083 u32 reset_reg, tmp_reg = 0, rc;
10084 bool prev_undi = false;
10085 struct bnx2x_mac_vals mac_vals;
10087 /* It is possible a previous function received 'common' answer,
10088 * but hasn't loaded yet, therefore creating a scenario of
10089 * multiple functions receiving 'common' on the same path.
10091 BNX2X_DEV_INFO("Common unload Flow\n");
10093 memset(&mac_vals, 0, sizeof(mac_vals));
10095 if (bnx2x_prev_is_path_marked(bp))
10096 return bnx2x_prev_mcp_done(bp);
10098 reset_reg = REG_RD(bp, MISC_REG_RESET_REG_1);
10100 /* Reset should be performed after BRB is emptied */
10101 if (reset_reg & MISC_REGISTERS_RESET_REG_1_RST_BRB1) {
10102 u32 timer_count = 1000;
10104 /* Close the MAC Rx to prevent BRB from filling up */
10105 bnx2x_prev_unload_close_mac(bp, &mac_vals);
10107 /* close LLH filters towards the BRB */
10108 bnx2x_set_rx_filter(&bp->link_params, 0);
10110 /* Check if the UNDI driver was previously loaded
10111 * UNDI driver initializes CID offset for normal bell to 0x7
10113 if (reset_reg & MISC_REGISTERS_RESET_REG_1_RST_DORQ) {
10114 tmp_reg = REG_RD(bp, DORQ_REG_NORM_CID_OFST);
10115 if (tmp_reg == 0x7) {
10116 BNX2X_DEV_INFO("UNDI previously loaded\n");
10118 /* clear the UNDI indication */
10119 REG_WR(bp, DORQ_REG_NORM_CID_OFST, 0);
10120 /* clear possible idle check errors */
10121 REG_RD(bp, NIG_REG_NIG_INT_STS_CLR_0);
10124 if (!CHIP_IS_E1x(bp))
10125 /* block FW from writing to host */
10126 REG_WR(bp, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, 0);
10128 /* wait until BRB is empty */
10129 tmp_reg = REG_RD(bp, BRB1_REG_NUM_OF_FULL_BLOCKS);
10130 while (timer_count) {
10131 u32 prev_brb = tmp_reg;
10133 tmp_reg = REG_RD(bp, BRB1_REG_NUM_OF_FULL_BLOCKS);
10137 BNX2X_DEV_INFO("BRB still has 0x%08x\n", tmp_reg);
10139 /* reset timer as long as BRB actually gets emptied */
10140 if (prev_brb > tmp_reg)
10141 timer_count = 1000;
10145 /* If UNDI resides in memory, manually increment it */
10147 bnx2x_prev_unload_undi_inc(bp, BP_PORT(bp), 1);
10153 BNX2X_ERR("Failed to empty BRB, hope for the best\n");
10156 /* No packets are in the pipeline, path is ready for reset */
10157 bnx2x_reset_common(bp);
10159 if (mac_vals.xmac_addr)
10160 REG_WR(bp, mac_vals.xmac_addr, mac_vals.xmac_val);
10161 if (mac_vals.umac_addr)
10162 REG_WR(bp, mac_vals.umac_addr, mac_vals.umac_val);
10163 if (mac_vals.emac_addr)
10164 REG_WR(bp, mac_vals.emac_addr, mac_vals.emac_val);
10165 if (mac_vals.bmac_addr) {
10166 REG_WR(bp, mac_vals.bmac_addr, mac_vals.bmac_val[0]);
10167 REG_WR(bp, mac_vals.bmac_addr + 4, mac_vals.bmac_val[1]);
10170 rc = bnx2x_prev_mark_path(bp, prev_undi);
10172 bnx2x_prev_mcp_done(bp);
10176 return bnx2x_prev_mcp_done(bp);
10179 /* previous driver DMAE transaction may have occurred when pre-boot stage ended
10180 * and boot began, or when kdump kernel was loaded. Either case would invalidate
10181 * the addresses of the transaction, resulting in was-error bit set in the pci
10182 * causing all hw-to-host pcie transactions to timeout. If this happened we want
10183 * to clear the interrupt which detected this from the pglueb and the was done
10186 static void bnx2x_prev_interrupted_dmae(struct bnx2x *bp)
10188 if (!CHIP_IS_E1x(bp)) {
10189 u32 val = REG_RD(bp, PGLUE_B_REG_PGLUE_B_INT_STS);
10190 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_WAS_ERROR_ATTN) {
10192 "'was error' bit was found to be set in pglueb upon startup. Clearing\n");
10193 REG_WR(bp, PGLUE_B_REG_WAS_ERROR_PF_7_0_CLR,
10199 static int bnx2x_prev_unload(struct bnx2x *bp)
10201 int time_counter = 10;
10202 u32 rc, fw, hw_lock_reg, hw_lock_val;
10203 BNX2X_DEV_INFO("Entering Previous Unload Flow\n");
10205 /* clear hw from errors which may have resulted from an interrupted
10206 * dmae transaction.
10208 bnx2x_prev_interrupted_dmae(bp);
10210 /* Release previously held locks */
10211 hw_lock_reg = (BP_FUNC(bp) <= 5) ?
10212 (MISC_REG_DRIVER_CONTROL_1 + BP_FUNC(bp) * 8) :
10213 (MISC_REG_DRIVER_CONTROL_7 + (BP_FUNC(bp) - 6) * 8);
10215 hw_lock_val = REG_RD(bp, hw_lock_reg);
10217 if (hw_lock_val & HW_LOCK_RESOURCE_NVRAM) {
10218 BNX2X_DEV_INFO("Release Previously held NVRAM lock\n");
10219 REG_WR(bp, MCP_REG_MCPR_NVM_SW_ARB,
10220 (MCPR_NVM_SW_ARB_ARB_REQ_CLR1 << BP_PORT(bp)));
10223 BNX2X_DEV_INFO("Release Previously held hw lock\n");
10224 REG_WR(bp, hw_lock_reg, 0xffffffff);
10226 BNX2X_DEV_INFO("No need to release hw/nvram locks\n");
10228 if (MCPR_ACCESS_LOCK_LOCK & REG_RD(bp, MCP_REG_MCPR_ACCESS_LOCK)) {
10229 BNX2X_DEV_INFO("Release previously held alr\n");
10230 bnx2x_release_alr(bp);
10235 /* Lock MCP using an unload request */
10236 fw = bnx2x_fw_command(bp, DRV_MSG_CODE_UNLOAD_REQ_WOL_DIS, 0);
10238 BNX2X_ERR("MCP response failure, aborting\n");
10243 rc = down_interruptible(&bnx2x_prev_sem);
10245 BNX2X_ERR("Cannot check for AER; Received %d when tried to take lock\n",
10248 /* If Path is marked by EEH, ignore unload status */
10249 aer = !!(bnx2x_prev_path_get_entry(bp) &&
10250 bnx2x_prev_path_get_entry(bp)->aer);
10251 up(&bnx2x_prev_sem);
10254 if (fw == FW_MSG_CODE_DRV_UNLOAD_COMMON || aer) {
10255 rc = bnx2x_prev_unload_common(bp);
10259 /* non-common reply from MCP might require looping */
10260 rc = bnx2x_prev_unload_uncommon(bp);
10261 if (rc != BNX2X_PREV_WAIT_NEEDED)
10265 } while (--time_counter);
10267 if (!time_counter || rc) {
10268 BNX2X_ERR("Failed unloading previous driver, aborting\n");
10272 /* Mark function if its port was used to boot from SAN */
10273 if (bnx2x_port_after_undi(bp))
10274 bp->link_params.feature_config_flags |=
10275 FEATURE_CONFIG_BOOT_FROM_SAN;
10277 BNX2X_DEV_INFO("Finished Previous Unload Flow [%d]\n", rc);
10282 static void bnx2x_get_common_hwinfo(struct bnx2x *bp)
10284 u32 val, val2, val3, val4, id, boot_mode;
10287 /* Get the chip revision id and number. */
10288 /* chip num:16-31, rev:12-15, metal:4-11, bond_id:0-3 */
10289 val = REG_RD(bp, MISC_REG_CHIP_NUM);
10290 id = ((val & 0xffff) << 16);
10291 val = REG_RD(bp, MISC_REG_CHIP_REV);
10292 id |= ((val & 0xf) << 12);
10294 /* Metal is read from PCI regs, but we can't access >=0x400 from
10295 * the configuration space (so we need to reg_rd)
10297 val = REG_RD(bp, PCICFG_OFFSET + PCI_ID_VAL3);
10298 id |= (((val >> 24) & 0xf) << 4);
10299 val = REG_RD(bp, MISC_REG_BOND_ID);
10301 bp->common.chip_id = id;
10303 /* force 57811 according to MISC register */
10304 if (REG_RD(bp, MISC_REG_CHIP_TYPE) & MISC_REG_CHIP_TYPE_57811_MASK) {
10305 if (CHIP_IS_57810(bp))
10306 bp->common.chip_id = (CHIP_NUM_57811 << 16) |
10307 (bp->common.chip_id & 0x0000FFFF);
10308 else if (CHIP_IS_57810_MF(bp))
10309 bp->common.chip_id = (CHIP_NUM_57811_MF << 16) |
10310 (bp->common.chip_id & 0x0000FFFF);
10311 bp->common.chip_id |= 0x1;
10314 /* Set doorbell size */
10315 bp->db_size = (1 << BNX2X_DB_SHIFT);
10317 if (!CHIP_IS_E1x(bp)) {
10318 val = REG_RD(bp, MISC_REG_PORT4MODE_EN_OVWR);
10319 if ((val & 1) == 0)
10320 val = REG_RD(bp, MISC_REG_PORT4MODE_EN);
10322 val = (val >> 1) & 1;
10323 BNX2X_DEV_INFO("chip is in %s\n", val ? "4_PORT_MODE" :
10325 bp->common.chip_port_mode = val ? CHIP_4_PORT_MODE :
10328 if (CHIP_MODE_IS_4_PORT(bp))
10329 bp->pfid = (bp->pf_num >> 1); /* 0..3 */
10331 bp->pfid = (bp->pf_num & 0x6); /* 0, 2, 4, 6 */
10333 bp->common.chip_port_mode = CHIP_PORT_MODE_NONE; /* N/A */
10334 bp->pfid = bp->pf_num; /* 0..7 */
10337 BNX2X_DEV_INFO("pf_id: %x", bp->pfid);
10339 bp->link_params.chip_id = bp->common.chip_id;
10340 BNX2X_DEV_INFO("chip ID is 0x%x\n", id);
10342 val = (REG_RD(bp, 0x2874) & 0x55);
10343 if ((bp->common.chip_id & 0x1) ||
10344 (CHIP_IS_E1(bp) && val) || (CHIP_IS_E1H(bp) && (val == 0x55))) {
10345 bp->flags |= ONE_PORT_FLAG;
10346 BNX2X_DEV_INFO("single port device\n");
10349 val = REG_RD(bp, MCP_REG_MCPR_NVM_CFG4);
10350 bp->common.flash_size = (BNX2X_NVRAM_1MB_SIZE <<
10351 (val & MCPR_NVM_CFG4_FLASH_SIZE));
10352 BNX2X_DEV_INFO("flash_size 0x%x (%d)\n",
10353 bp->common.flash_size, bp->common.flash_size);
10355 bnx2x_init_shmem(bp);
10357 bp->common.shmem2_base = REG_RD(bp, (BP_PATH(bp) ?
10358 MISC_REG_GENERIC_CR_1 :
10359 MISC_REG_GENERIC_CR_0));
10361 bp->link_params.shmem_base = bp->common.shmem_base;
10362 bp->link_params.shmem2_base = bp->common.shmem2_base;
10363 if (SHMEM2_RD(bp, size) >
10364 (u32)offsetof(struct shmem2_region, lfa_host_addr[BP_PORT(bp)]))
10365 bp->link_params.lfa_base =
10366 REG_RD(bp, bp->common.shmem2_base +
10367 (u32)offsetof(struct shmem2_region,
10368 lfa_host_addr[BP_PORT(bp)]));
10370 bp->link_params.lfa_base = 0;
10371 BNX2X_DEV_INFO("shmem offset 0x%x shmem2 offset 0x%x\n",
10372 bp->common.shmem_base, bp->common.shmem2_base);
10374 if (!bp->common.shmem_base) {
10375 BNX2X_DEV_INFO("MCP not active\n");
10376 bp->flags |= NO_MCP_FLAG;
10380 bp->common.hw_config = SHMEM_RD(bp, dev_info.shared_hw_config.config);
10381 BNX2X_DEV_INFO("hw_config 0x%08x\n", bp->common.hw_config);
10383 bp->link_params.hw_led_mode = ((bp->common.hw_config &
10384 SHARED_HW_CFG_LED_MODE_MASK) >>
10385 SHARED_HW_CFG_LED_MODE_SHIFT);
10387 bp->link_params.feature_config_flags = 0;
10388 val = SHMEM_RD(bp, dev_info.shared_feature_config.config);
10389 if (val & SHARED_FEAT_CFG_OVERRIDE_PREEMPHASIS_CFG_ENABLED)
10390 bp->link_params.feature_config_flags |=
10391 FEATURE_CONFIG_OVERRIDE_PREEMPHASIS_ENABLED;
10393 bp->link_params.feature_config_flags &=
10394 ~FEATURE_CONFIG_OVERRIDE_PREEMPHASIS_ENABLED;
10396 val = SHMEM_RD(bp, dev_info.bc_rev) >> 8;
10397 bp->common.bc_ver = val;
10398 BNX2X_DEV_INFO("bc_ver %X\n", val);
10399 if (val < BNX2X_BC_VER) {
10400 /* for now only warn
10401 * later we might need to enforce this */
10402 BNX2X_ERR("This driver needs bc_ver %X but found %X, please upgrade BC\n",
10403 BNX2X_BC_VER, val);
10405 bp->link_params.feature_config_flags |=
10406 (val >= REQ_BC_VER_4_VRFY_FIRST_PHY_OPT_MDL) ?
10407 FEATURE_CONFIG_BC_SUPPORTS_OPT_MDL_VRFY : 0;
10409 bp->link_params.feature_config_flags |=
10410 (val >= REQ_BC_VER_4_VRFY_SPECIFIC_PHY_OPT_MDL) ?
10411 FEATURE_CONFIG_BC_SUPPORTS_DUAL_PHY_OPT_MDL_VRFY : 0;
10412 bp->link_params.feature_config_flags |=
10413 (val >= REQ_BC_VER_4_VRFY_AFEX_SUPPORTED) ?
10414 FEATURE_CONFIG_BC_SUPPORTS_AFEX : 0;
10415 bp->link_params.feature_config_flags |=
10416 (val >= REQ_BC_VER_4_SFP_TX_DISABLE_SUPPORTED) ?
10417 FEATURE_CONFIG_BC_SUPPORTS_SFP_TX_DISABLED : 0;
10419 bp->link_params.feature_config_flags |=
10420 (val >= REQ_BC_VER_4_MT_SUPPORTED) ?
10421 FEATURE_CONFIG_MT_SUPPORT : 0;
10423 bp->flags |= (val >= REQ_BC_VER_4_PFC_STATS_SUPPORTED) ?
10424 BC_SUPPORTS_PFC_STATS : 0;
10426 bp->flags |= (val >= REQ_BC_VER_4_FCOE_FEATURES) ?
10427 BC_SUPPORTS_FCOE_FEATURES : 0;
10429 bp->flags |= (val >= REQ_BC_VER_4_DCBX_ADMIN_MSG_NON_PMF) ?
10430 BC_SUPPORTS_DCBX_MSG_NON_PMF : 0;
10432 bp->flags |= (val >= REQ_BC_VER_4_RMMOD_CMD) ?
10433 BC_SUPPORTS_RMMOD_CMD : 0;
10435 boot_mode = SHMEM_RD(bp,
10436 dev_info.port_feature_config[BP_PORT(bp)].mba_config) &
10437 PORT_FEATURE_MBA_BOOT_AGENT_TYPE_MASK;
10438 switch (boot_mode) {
10439 case PORT_FEATURE_MBA_BOOT_AGENT_TYPE_PXE:
10440 bp->common.boot_mode = FEATURE_ETH_BOOTMODE_PXE;
10442 case PORT_FEATURE_MBA_BOOT_AGENT_TYPE_ISCSIB:
10443 bp->common.boot_mode = FEATURE_ETH_BOOTMODE_ISCSI;
10445 case PORT_FEATURE_MBA_BOOT_AGENT_TYPE_FCOE_BOOT:
10446 bp->common.boot_mode = FEATURE_ETH_BOOTMODE_FCOE;
10448 case PORT_FEATURE_MBA_BOOT_AGENT_TYPE_NONE:
10449 bp->common.boot_mode = FEATURE_ETH_BOOTMODE_NONE;
10453 pci_read_config_word(bp->pdev, bp->pdev->pm_cap + PCI_PM_PMC, &pmc);
10454 bp->flags |= (pmc & PCI_PM_CAP_PME_D3cold) ? 0 : NO_WOL_FLAG;
10456 BNX2X_DEV_INFO("%sWoL capable\n",
10457 (bp->flags & NO_WOL_FLAG) ? "not " : "");
10459 val = SHMEM_RD(bp, dev_info.shared_hw_config.part_num);
10460 val2 = SHMEM_RD(bp, dev_info.shared_hw_config.part_num[4]);
10461 val3 = SHMEM_RD(bp, dev_info.shared_hw_config.part_num[8]);
10462 val4 = SHMEM_RD(bp, dev_info.shared_hw_config.part_num[12]);
10464 dev_info(&bp->pdev->dev, "part number %X-%X-%X-%X\n",
10465 val, val2, val3, val4);
10468 #define IGU_FID(val) GET_FIELD((val), IGU_REG_MAPPING_MEMORY_FID)
10469 #define IGU_VEC(val) GET_FIELD((val), IGU_REG_MAPPING_MEMORY_VECTOR)
10471 static int bnx2x_get_igu_cam_info(struct bnx2x *bp)
10473 int pfid = BP_FUNC(bp);
10476 u8 fid, igu_sb_cnt = 0;
10478 bp->igu_base_sb = 0xff;
10479 if (CHIP_INT_MODE_IS_BC(bp)) {
10480 int vn = BP_VN(bp);
10481 igu_sb_cnt = bp->igu_sb_cnt;
10482 bp->igu_base_sb = (CHIP_MODE_IS_4_PORT(bp) ? pfid : vn) *
10485 bp->igu_dsb_id = E1HVN_MAX * FP_SB_MAX_E1x +
10486 (CHIP_MODE_IS_4_PORT(bp) ? pfid : vn);
10491 /* IGU in normal mode - read CAM */
10492 for (igu_sb_id = 0; igu_sb_id < IGU_REG_MAPPING_MEMORY_SIZE;
10494 val = REG_RD(bp, IGU_REG_MAPPING_MEMORY + igu_sb_id * 4);
10495 if (!(val & IGU_REG_MAPPING_MEMORY_VALID))
10497 fid = IGU_FID(val);
10498 if ((fid & IGU_FID_ENCODE_IS_PF)) {
10499 if ((fid & IGU_FID_PF_NUM_MASK) != pfid)
10501 if (IGU_VEC(val) == 0)
10502 /* default status block */
10503 bp->igu_dsb_id = igu_sb_id;
10505 if (bp->igu_base_sb == 0xff)
10506 bp->igu_base_sb = igu_sb_id;
10512 #ifdef CONFIG_PCI_MSI
10513 /* Due to new PF resource allocation by MFW T7.4 and above, it's
10514 * optional that number of CAM entries will not be equal to the value
10515 * advertised in PCI.
10516 * Driver should use the minimal value of both as the actual status
10519 bp->igu_sb_cnt = min_t(int, bp->igu_sb_cnt, igu_sb_cnt);
10522 if (igu_sb_cnt == 0) {
10523 BNX2X_ERR("CAM configuration error\n");
10530 static void bnx2x_link_settings_supported(struct bnx2x *bp, u32 switch_cfg)
10532 int cfg_size = 0, idx, port = BP_PORT(bp);
10534 /* Aggregation of supported attributes of all external phys */
10535 bp->port.supported[0] = 0;
10536 bp->port.supported[1] = 0;
10537 switch (bp->link_params.num_phys) {
10539 bp->port.supported[0] = bp->link_params.phy[INT_PHY].supported;
10543 bp->port.supported[0] = bp->link_params.phy[EXT_PHY1].supported;
10547 if (bp->link_params.multi_phy_config &
10548 PORT_HW_CFG_PHY_SWAPPED_ENABLED) {
10549 bp->port.supported[1] =
10550 bp->link_params.phy[EXT_PHY1].supported;
10551 bp->port.supported[0] =
10552 bp->link_params.phy[EXT_PHY2].supported;
10554 bp->port.supported[0] =
10555 bp->link_params.phy[EXT_PHY1].supported;
10556 bp->port.supported[1] =
10557 bp->link_params.phy[EXT_PHY2].supported;
10563 if (!(bp->port.supported[0] || bp->port.supported[1])) {
10564 BNX2X_ERR("NVRAM config error. BAD phy config. PHY1 config 0x%x, PHY2 config 0x%x\n",
10566 dev_info.port_hw_config[port].external_phy_config),
10568 dev_info.port_hw_config[port].external_phy_config2));
10572 if (CHIP_IS_E3(bp))
10573 bp->port.phy_addr = REG_RD(bp, MISC_REG_WC0_CTRL_PHY_ADDR);
10575 switch (switch_cfg) {
10576 case SWITCH_CFG_1G:
10577 bp->port.phy_addr = REG_RD(
10578 bp, NIG_REG_SERDES0_CTRL_PHY_ADDR + port*0x10);
10580 case SWITCH_CFG_10G:
10581 bp->port.phy_addr = REG_RD(
10582 bp, NIG_REG_XGXS0_CTRL_PHY_ADDR + port*0x18);
10585 BNX2X_ERR("BAD switch_cfg link_config 0x%x\n",
10586 bp->port.link_config[0]);
10590 BNX2X_DEV_INFO("phy_addr 0x%x\n", bp->port.phy_addr);
10591 /* mask what we support according to speed_cap_mask per configuration */
10592 for (idx = 0; idx < cfg_size; idx++) {
10593 if (!(bp->link_params.speed_cap_mask[idx] &
10594 PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_HALF))
10595 bp->port.supported[idx] &= ~SUPPORTED_10baseT_Half;
10597 if (!(bp->link_params.speed_cap_mask[idx] &
10598 PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_FULL))
10599 bp->port.supported[idx] &= ~SUPPORTED_10baseT_Full;
10601 if (!(bp->link_params.speed_cap_mask[idx] &
10602 PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_HALF))
10603 bp->port.supported[idx] &= ~SUPPORTED_100baseT_Half;
10605 if (!(bp->link_params.speed_cap_mask[idx] &
10606 PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_FULL))
10607 bp->port.supported[idx] &= ~SUPPORTED_100baseT_Full;
10609 if (!(bp->link_params.speed_cap_mask[idx] &
10610 PORT_HW_CFG_SPEED_CAPABILITY_D0_1G))
10611 bp->port.supported[idx] &= ~(SUPPORTED_1000baseT_Half |
10612 SUPPORTED_1000baseT_Full);
10614 if (!(bp->link_params.speed_cap_mask[idx] &
10615 PORT_HW_CFG_SPEED_CAPABILITY_D0_2_5G))
10616 bp->port.supported[idx] &= ~SUPPORTED_2500baseX_Full;
10618 if (!(bp->link_params.speed_cap_mask[idx] &
10619 PORT_HW_CFG_SPEED_CAPABILITY_D0_10G))
10620 bp->port.supported[idx] &= ~SUPPORTED_10000baseT_Full;
10622 if (!(bp->link_params.speed_cap_mask[idx] &
10623 PORT_HW_CFG_SPEED_CAPABILITY_D0_20G))
10624 bp->port.supported[idx] &= ~SUPPORTED_20000baseKR2_Full;
10627 BNX2X_DEV_INFO("supported 0x%x 0x%x\n", bp->port.supported[0],
10628 bp->port.supported[1]);
10631 static void bnx2x_link_settings_requested(struct bnx2x *bp)
10633 u32 link_config, idx, cfg_size = 0;
10634 bp->port.advertising[0] = 0;
10635 bp->port.advertising[1] = 0;
10636 switch (bp->link_params.num_phys) {
10645 for (idx = 0; idx < cfg_size; idx++) {
10646 bp->link_params.req_duplex[idx] = DUPLEX_FULL;
10647 link_config = bp->port.link_config[idx];
10648 switch (link_config & PORT_FEATURE_LINK_SPEED_MASK) {
10649 case PORT_FEATURE_LINK_SPEED_AUTO:
10650 if (bp->port.supported[idx] & SUPPORTED_Autoneg) {
10651 bp->link_params.req_line_speed[idx] =
10653 bp->port.advertising[idx] |=
10654 bp->port.supported[idx];
10655 if (bp->link_params.phy[EXT_PHY1].type ==
10656 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84833)
10657 bp->port.advertising[idx] |=
10658 (SUPPORTED_100baseT_Half |
10659 SUPPORTED_100baseT_Full);
10661 /* force 10G, no AN */
10662 bp->link_params.req_line_speed[idx] =
10664 bp->port.advertising[idx] |=
10665 (ADVERTISED_10000baseT_Full |
10671 case PORT_FEATURE_LINK_SPEED_10M_FULL:
10672 if (bp->port.supported[idx] & SUPPORTED_10baseT_Full) {
10673 bp->link_params.req_line_speed[idx] =
10675 bp->port.advertising[idx] |=
10676 (ADVERTISED_10baseT_Full |
10679 BNX2X_ERR("NVRAM config error. Invalid link_config 0x%x speed_cap_mask 0x%x\n",
10681 bp->link_params.speed_cap_mask[idx]);
10686 case PORT_FEATURE_LINK_SPEED_10M_HALF:
10687 if (bp->port.supported[idx] & SUPPORTED_10baseT_Half) {
10688 bp->link_params.req_line_speed[idx] =
10690 bp->link_params.req_duplex[idx] =
10692 bp->port.advertising[idx] |=
10693 (ADVERTISED_10baseT_Half |
10696 BNX2X_ERR("NVRAM config error. Invalid link_config 0x%x speed_cap_mask 0x%x\n",
10698 bp->link_params.speed_cap_mask[idx]);
10703 case PORT_FEATURE_LINK_SPEED_100M_FULL:
10704 if (bp->port.supported[idx] &
10705 SUPPORTED_100baseT_Full) {
10706 bp->link_params.req_line_speed[idx] =
10708 bp->port.advertising[idx] |=
10709 (ADVERTISED_100baseT_Full |
10712 BNX2X_ERR("NVRAM config error. Invalid link_config 0x%x speed_cap_mask 0x%x\n",
10714 bp->link_params.speed_cap_mask[idx]);
10719 case PORT_FEATURE_LINK_SPEED_100M_HALF:
10720 if (bp->port.supported[idx] &
10721 SUPPORTED_100baseT_Half) {
10722 bp->link_params.req_line_speed[idx] =
10724 bp->link_params.req_duplex[idx] =
10726 bp->port.advertising[idx] |=
10727 (ADVERTISED_100baseT_Half |
10730 BNX2X_ERR("NVRAM config error. Invalid link_config 0x%x speed_cap_mask 0x%x\n",
10732 bp->link_params.speed_cap_mask[idx]);
10737 case PORT_FEATURE_LINK_SPEED_1G:
10738 if (bp->port.supported[idx] &
10739 SUPPORTED_1000baseT_Full) {
10740 bp->link_params.req_line_speed[idx] =
10742 bp->port.advertising[idx] |=
10743 (ADVERTISED_1000baseT_Full |
10746 BNX2X_ERR("NVRAM config error. Invalid link_config 0x%x speed_cap_mask 0x%x\n",
10748 bp->link_params.speed_cap_mask[idx]);
10753 case PORT_FEATURE_LINK_SPEED_2_5G:
10754 if (bp->port.supported[idx] &
10755 SUPPORTED_2500baseX_Full) {
10756 bp->link_params.req_line_speed[idx] =
10758 bp->port.advertising[idx] |=
10759 (ADVERTISED_2500baseX_Full |
10762 BNX2X_ERR("NVRAM config error. Invalid link_config 0x%x speed_cap_mask 0x%x\n",
10764 bp->link_params.speed_cap_mask[idx]);
10769 case PORT_FEATURE_LINK_SPEED_10G_CX4:
10770 if (bp->port.supported[idx] &
10771 SUPPORTED_10000baseT_Full) {
10772 bp->link_params.req_line_speed[idx] =
10774 bp->port.advertising[idx] |=
10775 (ADVERTISED_10000baseT_Full |
10778 BNX2X_ERR("NVRAM config error. Invalid link_config 0x%x speed_cap_mask 0x%x\n",
10780 bp->link_params.speed_cap_mask[idx]);
10784 case PORT_FEATURE_LINK_SPEED_20G:
10785 bp->link_params.req_line_speed[idx] = SPEED_20000;
10789 BNX2X_ERR("NVRAM config error. BAD link speed link_config 0x%x\n",
10791 bp->link_params.req_line_speed[idx] =
10793 bp->port.advertising[idx] =
10794 bp->port.supported[idx];
10798 bp->link_params.req_flow_ctrl[idx] = (link_config &
10799 PORT_FEATURE_FLOW_CONTROL_MASK);
10800 if (bp->link_params.req_flow_ctrl[idx] ==
10801 BNX2X_FLOW_CTRL_AUTO) {
10802 if (!(bp->port.supported[idx] & SUPPORTED_Autoneg))
10803 bp->link_params.req_flow_ctrl[idx] =
10804 BNX2X_FLOW_CTRL_NONE;
10806 bnx2x_set_requested_fc(bp);
10809 BNX2X_DEV_INFO("req_line_speed %d req_duplex %d req_flow_ctrl 0x%x advertising 0x%x\n",
10810 bp->link_params.req_line_speed[idx],
10811 bp->link_params.req_duplex[idx],
10812 bp->link_params.req_flow_ctrl[idx],
10813 bp->port.advertising[idx]);
10817 static void bnx2x_set_mac_buf(u8 *mac_buf, u32 mac_lo, u16 mac_hi)
10819 __be16 mac_hi_be = cpu_to_be16(mac_hi);
10820 __be32 mac_lo_be = cpu_to_be32(mac_lo);
10821 memcpy(mac_buf, &mac_hi_be, sizeof(mac_hi_be));
10822 memcpy(mac_buf + sizeof(mac_hi_be), &mac_lo_be, sizeof(mac_lo_be));
10825 static void bnx2x_get_port_hwinfo(struct bnx2x *bp)
10827 int port = BP_PORT(bp);
10829 u32 ext_phy_type, ext_phy_config, eee_mode;
10831 bp->link_params.bp = bp;
10832 bp->link_params.port = port;
10834 bp->link_params.lane_config =
10835 SHMEM_RD(bp, dev_info.port_hw_config[port].lane_config);
10837 bp->link_params.speed_cap_mask[0] =
10839 dev_info.port_hw_config[port].speed_capability_mask) &
10840 PORT_HW_CFG_SPEED_CAPABILITY_D0_MASK;
10841 bp->link_params.speed_cap_mask[1] =
10843 dev_info.port_hw_config[port].speed_capability_mask2) &
10844 PORT_HW_CFG_SPEED_CAPABILITY_D0_MASK;
10845 bp->port.link_config[0] =
10846 SHMEM_RD(bp, dev_info.port_feature_config[port].link_config);
10848 bp->port.link_config[1] =
10849 SHMEM_RD(bp, dev_info.port_feature_config[port].link_config2);
10851 bp->link_params.multi_phy_config =
10852 SHMEM_RD(bp, dev_info.port_hw_config[port].multi_phy_config);
10853 /* If the device is capable of WoL, set the default state according
10856 config = SHMEM_RD(bp, dev_info.port_feature_config[port].config);
10857 bp->wol = (!(bp->flags & NO_WOL_FLAG) &&
10858 (config & PORT_FEATURE_WOL_ENABLED));
10860 if ((config & PORT_FEAT_CFG_STORAGE_PERSONALITY_MASK) ==
10861 PORT_FEAT_CFG_STORAGE_PERSONALITY_FCOE && !IS_MF(bp))
10862 bp->flags |= NO_ISCSI_FLAG;
10863 if ((config & PORT_FEAT_CFG_STORAGE_PERSONALITY_MASK) ==
10864 PORT_FEAT_CFG_STORAGE_PERSONALITY_ISCSI && !(IS_MF(bp)))
10865 bp->flags |= NO_FCOE_FLAG;
10867 BNX2X_DEV_INFO("lane_config 0x%08x speed_cap_mask0 0x%08x link_config0 0x%08x\n",
10868 bp->link_params.lane_config,
10869 bp->link_params.speed_cap_mask[0],
10870 bp->port.link_config[0]);
10872 bp->link_params.switch_cfg = (bp->port.link_config[0] &
10873 PORT_FEATURE_CONNECTED_SWITCH_MASK);
10874 bnx2x_phy_probe(&bp->link_params);
10875 bnx2x_link_settings_supported(bp, bp->link_params.switch_cfg);
10877 bnx2x_link_settings_requested(bp);
10880 * If connected directly, work with the internal PHY, otherwise, work
10881 * with the external PHY
10885 dev_info.port_hw_config[port].external_phy_config);
10886 ext_phy_type = XGXS_EXT_PHY_TYPE(ext_phy_config);
10887 if (ext_phy_type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT)
10888 bp->mdio.prtad = bp->port.phy_addr;
10890 else if ((ext_phy_type != PORT_HW_CFG_XGXS_EXT_PHY_TYPE_FAILURE) &&
10891 (ext_phy_type != PORT_HW_CFG_XGXS_EXT_PHY_TYPE_NOT_CONN))
10893 XGXS_EXT_PHY_ADDR(ext_phy_config);
10895 /* Configure link feature according to nvram value */
10896 eee_mode = (((SHMEM_RD(bp, dev_info.
10897 port_feature_config[port].eee_power_mode)) &
10898 PORT_FEAT_CFG_EEE_POWER_MODE_MASK) >>
10899 PORT_FEAT_CFG_EEE_POWER_MODE_SHIFT);
10900 if (eee_mode != PORT_FEAT_CFG_EEE_POWER_MODE_DISABLED) {
10901 bp->link_params.eee_mode = EEE_MODE_ADV_LPI |
10902 EEE_MODE_ENABLE_LPI |
10903 EEE_MODE_OUTPUT_TIME;
10905 bp->link_params.eee_mode = 0;
10909 void bnx2x_get_iscsi_info(struct bnx2x *bp)
10911 u32 no_flags = NO_ISCSI_FLAG;
10912 int port = BP_PORT(bp);
10913 u32 max_iscsi_conn = FW_ENCODE_32BIT_PATTERN ^ SHMEM_RD(bp,
10914 drv_lic_key[port].max_iscsi_conn);
10916 if (!CNIC_SUPPORT(bp)) {
10917 bp->flags |= no_flags;
10921 /* Get the number of maximum allowed iSCSI connections */
10922 bp->cnic_eth_dev.max_iscsi_conn =
10923 (max_iscsi_conn & BNX2X_MAX_ISCSI_INIT_CONN_MASK) >>
10924 BNX2X_MAX_ISCSI_INIT_CONN_SHIFT;
10926 BNX2X_DEV_INFO("max_iscsi_conn 0x%x\n",
10927 bp->cnic_eth_dev.max_iscsi_conn);
10930 * If maximum allowed number of connections is zero -
10931 * disable the feature.
10933 if (!bp->cnic_eth_dev.max_iscsi_conn)
10934 bp->flags |= no_flags;
10937 static void bnx2x_get_ext_wwn_info(struct bnx2x *bp, int func)
10940 bp->cnic_eth_dev.fcoe_wwn_port_name_hi =
10941 MF_CFG_RD(bp, func_ext_config[func].fcoe_wwn_port_name_upper);
10942 bp->cnic_eth_dev.fcoe_wwn_port_name_lo =
10943 MF_CFG_RD(bp, func_ext_config[func].fcoe_wwn_port_name_lower);
10946 bp->cnic_eth_dev.fcoe_wwn_node_name_hi =
10947 MF_CFG_RD(bp, func_ext_config[func].fcoe_wwn_node_name_upper);
10948 bp->cnic_eth_dev.fcoe_wwn_node_name_lo =
10949 MF_CFG_RD(bp, func_ext_config[func].fcoe_wwn_node_name_lower);
10952 static int bnx2x_shared_fcoe_funcs(struct bnx2x *bp)
10959 /* iterate over absolute function ids for this path: */
10960 for (fid = BP_PATH(bp); fid < E2_FUNC_MAX * 2; fid += 2) {
10961 if (IS_MF_SD(bp)) {
10962 u32 cfg = MF_CFG_RD(bp,
10963 func_mf_config[fid].config);
10965 if (!(cfg & FUNC_MF_CFG_FUNC_HIDE) &&
10966 ((cfg & FUNC_MF_CFG_PROTOCOL_MASK) ==
10967 FUNC_MF_CFG_PROTOCOL_FCOE))
10970 u32 cfg = MF_CFG_RD(bp,
10971 func_ext_config[fid].
10974 if ((cfg & MACP_FUNC_CFG_FLAGS_ENABLED) &&
10975 (cfg & MACP_FUNC_CFG_FLAGS_FCOE_OFFLOAD))
10980 int port, port_cnt = CHIP_MODE_IS_4_PORT(bp) ? 2 : 1;
10982 for (port = 0; port < port_cnt; port++) {
10983 u32 lic = SHMEM_RD(bp,
10984 drv_lic_key[port].max_fcoe_conn) ^
10985 FW_ENCODE_32BIT_PATTERN;
10994 static void bnx2x_get_fcoe_info(struct bnx2x *bp)
10996 int port = BP_PORT(bp);
10997 int func = BP_ABS_FUNC(bp);
10998 u32 max_fcoe_conn = FW_ENCODE_32BIT_PATTERN ^ SHMEM_RD(bp,
10999 drv_lic_key[port].max_fcoe_conn);
11000 u8 num_fcoe_func = bnx2x_shared_fcoe_funcs(bp);
11002 if (!CNIC_SUPPORT(bp)) {
11003 bp->flags |= NO_FCOE_FLAG;
11007 /* Get the number of maximum allowed FCoE connections */
11008 bp->cnic_eth_dev.max_fcoe_conn =
11009 (max_fcoe_conn & BNX2X_MAX_FCOE_INIT_CONN_MASK) >>
11010 BNX2X_MAX_FCOE_INIT_CONN_SHIFT;
11012 /* Calculate the number of maximum allowed FCoE tasks */
11013 bp->cnic_eth_dev.max_fcoe_exchanges = MAX_NUM_FCOE_TASKS_PER_ENGINE;
11015 /* check if FCoE resources must be shared between different functions */
11017 bp->cnic_eth_dev.max_fcoe_exchanges /= num_fcoe_func;
11019 /* Read the WWN: */
11022 bp->cnic_eth_dev.fcoe_wwn_port_name_hi =
11024 dev_info.port_hw_config[port].
11025 fcoe_wwn_port_name_upper);
11026 bp->cnic_eth_dev.fcoe_wwn_port_name_lo =
11028 dev_info.port_hw_config[port].
11029 fcoe_wwn_port_name_lower);
11032 bp->cnic_eth_dev.fcoe_wwn_node_name_hi =
11034 dev_info.port_hw_config[port].
11035 fcoe_wwn_node_name_upper);
11036 bp->cnic_eth_dev.fcoe_wwn_node_name_lo =
11038 dev_info.port_hw_config[port].
11039 fcoe_wwn_node_name_lower);
11040 } else if (!IS_MF_SD(bp)) {
11042 * Read the WWN info only if the FCoE feature is enabled for
11045 if (BNX2X_MF_EXT_PROTOCOL_FCOE(bp) && !CHIP_IS_E1x(bp))
11046 bnx2x_get_ext_wwn_info(bp, func);
11048 } else if (IS_MF_FCOE_SD(bp) && !CHIP_IS_E1x(bp)) {
11049 bnx2x_get_ext_wwn_info(bp, func);
11052 BNX2X_DEV_INFO("max_fcoe_conn 0x%x\n", bp->cnic_eth_dev.max_fcoe_conn);
11055 * If maximum allowed number of connections is zero -
11056 * disable the feature.
11058 if (!bp->cnic_eth_dev.max_fcoe_conn)
11059 bp->flags |= NO_FCOE_FLAG;
11062 static void bnx2x_get_cnic_info(struct bnx2x *bp)
11065 * iSCSI may be dynamically disabled but reading
11066 * info here we will decrease memory usage by driver
11067 * if the feature is disabled for good
11069 bnx2x_get_iscsi_info(bp);
11070 bnx2x_get_fcoe_info(bp);
11073 static void bnx2x_get_cnic_mac_hwinfo(struct bnx2x *bp)
11076 int func = BP_ABS_FUNC(bp);
11077 int port = BP_PORT(bp);
11078 u8 *iscsi_mac = bp->cnic_eth_dev.iscsi_mac;
11079 u8 *fip_mac = bp->fip_mac;
11082 /* iSCSI and FCoE NPAR MACs: if there is no either iSCSI or
11083 * FCoE MAC then the appropriate feature should be disabled.
11084 * In non SD mode features configuration comes from struct
11087 if (!IS_MF_SD(bp) && !CHIP_IS_E1x(bp)) {
11088 u32 cfg = MF_CFG_RD(bp, func_ext_config[func].func_cfg);
11089 if (cfg & MACP_FUNC_CFG_FLAGS_ISCSI_OFFLOAD) {
11090 val2 = MF_CFG_RD(bp, func_ext_config[func].
11091 iscsi_mac_addr_upper);
11092 val = MF_CFG_RD(bp, func_ext_config[func].
11093 iscsi_mac_addr_lower);
11094 bnx2x_set_mac_buf(iscsi_mac, val, val2);
11096 ("Read iSCSI MAC: %pM\n", iscsi_mac);
11098 bp->flags |= NO_ISCSI_OOO_FLAG | NO_ISCSI_FLAG;
11101 if (cfg & MACP_FUNC_CFG_FLAGS_FCOE_OFFLOAD) {
11102 val2 = MF_CFG_RD(bp, func_ext_config[func].
11103 fcoe_mac_addr_upper);
11104 val = MF_CFG_RD(bp, func_ext_config[func].
11105 fcoe_mac_addr_lower);
11106 bnx2x_set_mac_buf(fip_mac, val, val2);
11108 ("Read FCoE L2 MAC: %pM\n", fip_mac);
11110 bp->flags |= NO_FCOE_FLAG;
11113 bp->mf_ext_config = cfg;
11115 } else { /* SD MODE */
11116 if (BNX2X_IS_MF_SD_PROTOCOL_ISCSI(bp)) {
11117 /* use primary mac as iscsi mac */
11118 memcpy(iscsi_mac, bp->dev->dev_addr, ETH_ALEN);
11120 BNX2X_DEV_INFO("SD ISCSI MODE\n");
11122 ("Read iSCSI MAC: %pM\n", iscsi_mac);
11123 } else if (BNX2X_IS_MF_SD_PROTOCOL_FCOE(bp)) {
11124 /* use primary mac as fip mac */
11125 memcpy(fip_mac, bp->dev->dev_addr, ETH_ALEN);
11126 BNX2X_DEV_INFO("SD FCoE MODE\n");
11128 ("Read FIP MAC: %pM\n", fip_mac);
11132 /* If this is a storage-only interface, use SAN mac as
11133 * primary MAC. Notice that for SD this is already the case,
11134 * as the SAN mac was copied from the primary MAC.
11136 if (IS_MF_FCOE_AFEX(bp))
11137 memcpy(bp->dev->dev_addr, fip_mac, ETH_ALEN);
11139 val2 = SHMEM_RD(bp, dev_info.port_hw_config[port].
11141 val = SHMEM_RD(bp, dev_info.port_hw_config[port].
11143 bnx2x_set_mac_buf(iscsi_mac, val, val2);
11145 val2 = SHMEM_RD(bp, dev_info.port_hw_config[port].
11146 fcoe_fip_mac_upper);
11147 val = SHMEM_RD(bp, dev_info.port_hw_config[port].
11148 fcoe_fip_mac_lower);
11149 bnx2x_set_mac_buf(fip_mac, val, val2);
11152 /* Disable iSCSI OOO if MAC configuration is invalid. */
11153 if (!is_valid_ether_addr(iscsi_mac)) {
11154 bp->flags |= NO_ISCSI_OOO_FLAG | NO_ISCSI_FLAG;
11155 memset(iscsi_mac, 0, ETH_ALEN);
11158 /* Disable FCoE if MAC configuration is invalid. */
11159 if (!is_valid_ether_addr(fip_mac)) {
11160 bp->flags |= NO_FCOE_FLAG;
11161 memset(bp->fip_mac, 0, ETH_ALEN);
11165 static void bnx2x_get_mac_hwinfo(struct bnx2x *bp)
11168 int func = BP_ABS_FUNC(bp);
11169 int port = BP_PORT(bp);
11171 /* Zero primary MAC configuration */
11172 memset(bp->dev->dev_addr, 0, ETH_ALEN);
11174 if (BP_NOMCP(bp)) {
11175 BNX2X_ERROR("warning: random MAC workaround active\n");
11176 eth_hw_addr_random(bp->dev);
11177 } else if (IS_MF(bp)) {
11178 val2 = MF_CFG_RD(bp, func_mf_config[func].mac_upper);
11179 val = MF_CFG_RD(bp, func_mf_config[func].mac_lower);
11180 if ((val2 != FUNC_MF_CFG_UPPERMAC_DEFAULT) &&
11181 (val != FUNC_MF_CFG_LOWERMAC_DEFAULT))
11182 bnx2x_set_mac_buf(bp->dev->dev_addr, val, val2);
11184 if (CNIC_SUPPORT(bp))
11185 bnx2x_get_cnic_mac_hwinfo(bp);
11187 /* in SF read MACs from port configuration */
11188 val2 = SHMEM_RD(bp, dev_info.port_hw_config[port].mac_upper);
11189 val = SHMEM_RD(bp, dev_info.port_hw_config[port].mac_lower);
11190 bnx2x_set_mac_buf(bp->dev->dev_addr, val, val2);
11192 if (CNIC_SUPPORT(bp))
11193 bnx2x_get_cnic_mac_hwinfo(bp);
11196 if (!BP_NOMCP(bp)) {
11197 /* Read physical port identifier from shmem */
11198 val2 = SHMEM_RD(bp, dev_info.port_hw_config[port].mac_upper);
11199 val = SHMEM_RD(bp, dev_info.port_hw_config[port].mac_lower);
11200 bnx2x_set_mac_buf(bp->phys_port_id, val, val2);
11201 bp->flags |= HAS_PHYS_PORT_ID;
11204 memcpy(bp->link_params.mac_addr, bp->dev->dev_addr, ETH_ALEN);
11206 if (!bnx2x_is_valid_ether_addr(bp, bp->dev->dev_addr))
11207 dev_err(&bp->pdev->dev,
11208 "bad Ethernet MAC address configuration: %pM\n"
11209 "change it manually before bringing up the appropriate network interface\n",
11210 bp->dev->dev_addr);
11213 static bool bnx2x_get_dropless_info(struct bnx2x *bp)
11221 if (IS_MF(bp) && !CHIP_IS_E1x(bp)) {
11222 /* Take function: tmp = func */
11223 tmp = BP_ABS_FUNC(bp);
11224 cfg = MF_CFG_RD(bp, func_ext_config[tmp].func_cfg);
11225 cfg = !!(cfg & MACP_FUNC_CFG_PAUSE_ON_HOST_RING);
11227 /* Take port: tmp = port */
11230 dev_info.port_hw_config[tmp].generic_features);
11231 cfg = !!(cfg & PORT_HW_CFG_PAUSE_ON_HOST_RING_ENABLED);
11236 static int bnx2x_get_hwinfo(struct bnx2x *bp)
11238 int /*abs*/func = BP_ABS_FUNC(bp);
11243 bnx2x_get_common_hwinfo(bp);
11246 * initialize IGU parameters
11248 if (CHIP_IS_E1x(bp)) {
11249 bp->common.int_block = INT_BLOCK_HC;
11251 bp->igu_dsb_id = DEF_SB_IGU_ID;
11252 bp->igu_base_sb = 0;
11254 bp->common.int_block = INT_BLOCK_IGU;
11256 /* do not allow device reset during IGU info processing */
11257 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_RESET);
11259 val = REG_RD(bp, IGU_REG_BLOCK_CONFIGURATION);
11261 if (val & IGU_BLOCK_CONFIGURATION_REG_BACKWARD_COMP_EN) {
11264 BNX2X_DEV_INFO("FORCING Normal Mode\n");
11266 val &= ~(IGU_BLOCK_CONFIGURATION_REG_BACKWARD_COMP_EN);
11267 REG_WR(bp, IGU_REG_BLOCK_CONFIGURATION, val);
11268 REG_WR(bp, IGU_REG_RESET_MEMORIES, 0x7f);
11270 while (tout && REG_RD(bp, IGU_REG_RESET_MEMORIES)) {
11272 usleep_range(1000, 2000);
11275 if (REG_RD(bp, IGU_REG_RESET_MEMORIES)) {
11276 dev_err(&bp->pdev->dev,
11277 "FORCING Normal Mode failed!!!\n");
11278 bnx2x_release_hw_lock(bp,
11279 HW_LOCK_RESOURCE_RESET);
11284 if (val & IGU_BLOCK_CONFIGURATION_REG_BACKWARD_COMP_EN) {
11285 BNX2X_DEV_INFO("IGU Backward Compatible Mode\n");
11286 bp->common.int_block |= INT_BLOCK_MODE_BW_COMP;
11288 BNX2X_DEV_INFO("IGU Normal Mode\n");
11290 rc = bnx2x_get_igu_cam_info(bp);
11291 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_RESET);
11297 * set base FW non-default (fast path) status block id, this value is
11298 * used to initialize the fw_sb_id saved on the fp/queue structure to
11299 * determine the id used by the FW.
11301 if (CHIP_IS_E1x(bp))
11302 bp->base_fw_ndsb = BP_PORT(bp) * FP_SB_MAX_E1x + BP_L_ID(bp);
11304 * 57712 - we currently use one FW SB per IGU SB (Rx and Tx of
11305 * the same queue are indicated on the same IGU SB). So we prefer
11306 * FW and IGU SBs to be the same value.
11308 bp->base_fw_ndsb = bp->igu_base_sb;
11310 BNX2X_DEV_INFO("igu_dsb_id %d igu_base_sb %d igu_sb_cnt %d\n"
11311 "base_fw_ndsb %d\n", bp->igu_dsb_id, bp->igu_base_sb,
11312 bp->igu_sb_cnt, bp->base_fw_ndsb);
11315 * Initialize MF configuration
11322 if (!CHIP_IS_E1(bp) && !BP_NOMCP(bp)) {
11323 BNX2X_DEV_INFO("shmem2base 0x%x, size %d, mfcfg offset %d\n",
11324 bp->common.shmem2_base, SHMEM2_RD(bp, size),
11325 (u32)offsetof(struct shmem2_region, mf_cfg_addr));
11327 if (SHMEM2_HAS(bp, mf_cfg_addr))
11328 bp->common.mf_cfg_base = SHMEM2_RD(bp, mf_cfg_addr);
11330 bp->common.mf_cfg_base = bp->common.shmem_base +
11331 offsetof(struct shmem_region, func_mb) +
11332 E1H_FUNC_MAX * sizeof(struct drv_func_mb);
11334 * get mf configuration:
11335 * 1. Existence of MF configuration
11336 * 2. MAC address must be legal (check only upper bytes)
11337 * for Switch-Independent mode;
11338 * OVLAN must be legal for Switch-Dependent mode
11339 * 3. SF_MODE configures specific MF mode
11341 if (bp->common.mf_cfg_base != SHMEM_MF_CFG_ADDR_NONE) {
11342 /* get mf configuration */
11344 dev_info.shared_feature_config.config);
11345 val &= SHARED_FEAT_CFG_FORCE_SF_MODE_MASK;
11348 case SHARED_FEAT_CFG_FORCE_SF_MODE_SWITCH_INDEPT:
11349 val = MF_CFG_RD(bp, func_mf_config[func].
11351 /* check for legal mac (upper bytes)*/
11352 if (val != 0xffff) {
11353 bp->mf_mode = MULTI_FUNCTION_SI;
11354 bp->mf_config[vn] = MF_CFG_RD(bp,
11355 func_mf_config[func].config);
11357 BNX2X_DEV_INFO("illegal MAC address for SI\n");
11359 case SHARED_FEAT_CFG_FORCE_SF_MODE_AFEX_MODE:
11360 if ((!CHIP_IS_E1x(bp)) &&
11361 (MF_CFG_RD(bp, func_mf_config[func].
11362 mac_upper) != 0xffff) &&
11364 afex_driver_support))) {
11365 bp->mf_mode = MULTI_FUNCTION_AFEX;
11366 bp->mf_config[vn] = MF_CFG_RD(bp,
11367 func_mf_config[func].config);
11369 BNX2X_DEV_INFO("can not configure afex mode\n");
11372 case SHARED_FEAT_CFG_FORCE_SF_MODE_MF_ALLOWED:
11373 /* get OV configuration */
11374 val = MF_CFG_RD(bp,
11375 func_mf_config[FUNC_0].e1hov_tag);
11376 val &= FUNC_MF_CFG_E1HOV_TAG_MASK;
11378 if (val != FUNC_MF_CFG_E1HOV_TAG_DEFAULT) {
11379 bp->mf_mode = MULTI_FUNCTION_SD;
11380 bp->mf_config[vn] = MF_CFG_RD(bp,
11381 func_mf_config[func].config);
11383 BNX2X_DEV_INFO("illegal OV for SD\n");
11385 case SHARED_FEAT_CFG_FORCE_SF_MODE_FORCED_SF:
11386 bp->mf_config[vn] = 0;
11389 /* Unknown configuration: reset mf_config */
11390 bp->mf_config[vn] = 0;
11391 BNX2X_DEV_INFO("unknown MF mode 0x%x\n", val);
11395 BNX2X_DEV_INFO("%s function mode\n",
11396 IS_MF(bp) ? "multi" : "single");
11398 switch (bp->mf_mode) {
11399 case MULTI_FUNCTION_SD:
11400 val = MF_CFG_RD(bp, func_mf_config[func].e1hov_tag) &
11401 FUNC_MF_CFG_E1HOV_TAG_MASK;
11402 if (val != FUNC_MF_CFG_E1HOV_TAG_DEFAULT) {
11404 bp->path_has_ovlan = true;
11406 BNX2X_DEV_INFO("MF OV for func %d is %d (0x%04x)\n",
11407 func, bp->mf_ov, bp->mf_ov);
11409 dev_err(&bp->pdev->dev,
11410 "No valid MF OV for func %d, aborting\n",
11415 case MULTI_FUNCTION_AFEX:
11416 BNX2X_DEV_INFO("func %d is in MF afex mode\n", func);
11418 case MULTI_FUNCTION_SI:
11419 BNX2X_DEV_INFO("func %d is in MF switch-independent mode\n",
11424 dev_err(&bp->pdev->dev,
11425 "VN %d is in a single function mode, aborting\n",
11432 /* check if other port on the path needs ovlan:
11433 * Since MF configuration is shared between ports
11434 * Possible mixed modes are only
11435 * {SF, SI} {SF, SD} {SD, SF} {SI, SF}
11437 if (CHIP_MODE_IS_4_PORT(bp) &&
11438 !bp->path_has_ovlan &&
11440 bp->common.mf_cfg_base != SHMEM_MF_CFG_ADDR_NONE) {
11441 u8 other_port = !BP_PORT(bp);
11442 u8 other_func = BP_PATH(bp) + 2*other_port;
11443 val = MF_CFG_RD(bp,
11444 func_mf_config[other_func].e1hov_tag);
11445 if (val != FUNC_MF_CFG_E1HOV_TAG_DEFAULT)
11446 bp->path_has_ovlan = true;
11450 /* adjust igu_sb_cnt to MF for E1H */
11451 if (CHIP_IS_E1H(bp) && IS_MF(bp))
11452 bp->igu_sb_cnt = min_t(u8, bp->igu_sb_cnt, E1H_MAX_MF_SB_COUNT);
11455 bnx2x_get_port_hwinfo(bp);
11457 /* Get MAC addresses */
11458 bnx2x_get_mac_hwinfo(bp);
11460 bnx2x_get_cnic_info(bp);
11465 static void bnx2x_read_fwinfo(struct bnx2x *bp)
11467 int cnt, i, block_end, rodi;
11468 char vpd_start[BNX2X_VPD_LEN+1];
11469 char str_id_reg[VENDOR_ID_LEN+1];
11470 char str_id_cap[VENDOR_ID_LEN+1];
11472 char *vpd_extended_data = NULL;
11475 cnt = pci_read_vpd(bp->pdev, 0, BNX2X_VPD_LEN, vpd_start);
11476 memset(bp->fw_ver, 0, sizeof(bp->fw_ver));
11478 if (cnt < BNX2X_VPD_LEN)
11479 goto out_not_found;
11481 /* VPD RO tag should be first tag after identifier string, hence
11482 * we should be able to find it in first BNX2X_VPD_LEN chars
11484 i = pci_vpd_find_tag(vpd_start, 0, BNX2X_VPD_LEN,
11485 PCI_VPD_LRDT_RO_DATA);
11487 goto out_not_found;
11489 block_end = i + PCI_VPD_LRDT_TAG_SIZE +
11490 pci_vpd_lrdt_size(&vpd_start[i]);
11492 i += PCI_VPD_LRDT_TAG_SIZE;
11494 if (block_end > BNX2X_VPD_LEN) {
11495 vpd_extended_data = kmalloc(block_end, GFP_KERNEL);
11496 if (vpd_extended_data == NULL)
11497 goto out_not_found;
11499 /* read rest of vpd image into vpd_extended_data */
11500 memcpy(vpd_extended_data, vpd_start, BNX2X_VPD_LEN);
11501 cnt = pci_read_vpd(bp->pdev, BNX2X_VPD_LEN,
11502 block_end - BNX2X_VPD_LEN,
11503 vpd_extended_data + BNX2X_VPD_LEN);
11504 if (cnt < (block_end - BNX2X_VPD_LEN))
11505 goto out_not_found;
11506 vpd_data = vpd_extended_data;
11508 vpd_data = vpd_start;
11510 /* now vpd_data holds full vpd content in both cases */
11512 rodi = pci_vpd_find_info_keyword(vpd_data, i, block_end,
11513 PCI_VPD_RO_KEYWORD_MFR_ID);
11515 goto out_not_found;
11517 len = pci_vpd_info_field_size(&vpd_data[rodi]);
11519 if (len != VENDOR_ID_LEN)
11520 goto out_not_found;
11522 rodi += PCI_VPD_INFO_FLD_HDR_SIZE;
11524 /* vendor specific info */
11525 snprintf(str_id_reg, VENDOR_ID_LEN + 1, "%04x", PCI_VENDOR_ID_DELL);
11526 snprintf(str_id_cap, VENDOR_ID_LEN + 1, "%04X", PCI_VENDOR_ID_DELL);
11527 if (!strncmp(str_id_reg, &vpd_data[rodi], VENDOR_ID_LEN) ||
11528 !strncmp(str_id_cap, &vpd_data[rodi], VENDOR_ID_LEN)) {
11530 rodi = pci_vpd_find_info_keyword(vpd_data, i, block_end,
11531 PCI_VPD_RO_KEYWORD_VENDOR0);
11533 len = pci_vpd_info_field_size(&vpd_data[rodi]);
11535 rodi += PCI_VPD_INFO_FLD_HDR_SIZE;
11537 if (len < 32 && (len + rodi) <= BNX2X_VPD_LEN) {
11538 memcpy(bp->fw_ver, &vpd_data[rodi], len);
11539 bp->fw_ver[len] = ' ';
11542 kfree(vpd_extended_data);
11546 kfree(vpd_extended_data);
11550 static void bnx2x_set_modes_bitmap(struct bnx2x *bp)
11554 if (CHIP_REV_IS_FPGA(bp))
11555 SET_FLAGS(flags, MODE_FPGA);
11556 else if (CHIP_REV_IS_EMUL(bp))
11557 SET_FLAGS(flags, MODE_EMUL);
11559 SET_FLAGS(flags, MODE_ASIC);
11561 if (CHIP_MODE_IS_4_PORT(bp))
11562 SET_FLAGS(flags, MODE_PORT4);
11564 SET_FLAGS(flags, MODE_PORT2);
11566 if (CHIP_IS_E2(bp))
11567 SET_FLAGS(flags, MODE_E2);
11568 else if (CHIP_IS_E3(bp)) {
11569 SET_FLAGS(flags, MODE_E3);
11570 if (CHIP_REV(bp) == CHIP_REV_Ax)
11571 SET_FLAGS(flags, MODE_E3_A0);
11572 else /*if (CHIP_REV(bp) == CHIP_REV_Bx)*/
11573 SET_FLAGS(flags, MODE_E3_B0 | MODE_COS3);
11577 SET_FLAGS(flags, MODE_MF);
11578 switch (bp->mf_mode) {
11579 case MULTI_FUNCTION_SD:
11580 SET_FLAGS(flags, MODE_MF_SD);
11582 case MULTI_FUNCTION_SI:
11583 SET_FLAGS(flags, MODE_MF_SI);
11585 case MULTI_FUNCTION_AFEX:
11586 SET_FLAGS(flags, MODE_MF_AFEX);
11590 SET_FLAGS(flags, MODE_SF);
11592 #if defined(__LITTLE_ENDIAN)
11593 SET_FLAGS(flags, MODE_LITTLE_ENDIAN);
11594 #else /*(__BIG_ENDIAN)*/
11595 SET_FLAGS(flags, MODE_BIG_ENDIAN);
11597 INIT_MODE_FLAGS(bp) = flags;
11600 static int bnx2x_init_bp(struct bnx2x *bp)
11605 mutex_init(&bp->port.phy_mutex);
11606 mutex_init(&bp->fw_mb_mutex);
11607 spin_lock_init(&bp->stats_lock);
11608 sema_init(&bp->stats_sema, 1);
11610 INIT_DELAYED_WORK(&bp->sp_task, bnx2x_sp_task);
11611 INIT_DELAYED_WORK(&bp->sp_rtnl_task, bnx2x_sp_rtnl_task);
11612 INIT_DELAYED_WORK(&bp->period_task, bnx2x_period_task);
11614 rc = bnx2x_get_hwinfo(bp);
11618 eth_zero_addr(bp->dev->dev_addr);
11621 bnx2x_set_modes_bitmap(bp);
11623 rc = bnx2x_alloc_mem_bp(bp);
11627 bnx2x_read_fwinfo(bp);
11629 func = BP_FUNC(bp);
11631 /* need to reset chip if undi was active */
11632 if (IS_PF(bp) && !BP_NOMCP(bp)) {
11635 SHMEM_RD(bp, func_mb[BP_FW_MB_IDX(bp)].drv_mb_header) &
11636 DRV_MSG_SEQ_NUMBER_MASK;
11637 BNX2X_DEV_INFO("fw_seq 0x%08x\n", bp->fw_seq);
11639 bnx2x_prev_unload(bp);
11642 if (CHIP_REV_IS_FPGA(bp))
11643 dev_err(&bp->pdev->dev, "FPGA detected\n");
11645 if (BP_NOMCP(bp) && (func == 0))
11646 dev_err(&bp->pdev->dev, "MCP disabled, must load devices in order!\n");
11648 bp->disable_tpa = disable_tpa;
11649 bp->disable_tpa |= IS_MF_STORAGE_SD(bp) || IS_MF_FCOE_AFEX(bp);
11651 /* Set TPA flags */
11652 if (bp->disable_tpa) {
11653 bp->flags &= ~(TPA_ENABLE_FLAG | GRO_ENABLE_FLAG);
11654 bp->dev->features &= ~NETIF_F_LRO;
11656 bp->flags |= (TPA_ENABLE_FLAG | GRO_ENABLE_FLAG);
11657 bp->dev->features |= NETIF_F_LRO;
11660 if (CHIP_IS_E1(bp))
11661 bp->dropless_fc = 0;
11663 bp->dropless_fc = dropless_fc | bnx2x_get_dropless_info(bp);
11667 bp->tx_ring_size = IS_MF_FCOE_AFEX(bp) ? 0 : MAX_TX_AVAIL;
11669 bp->rx_ring_size = MAX_RX_AVAIL;
11671 /* make sure that the numbers are in the right granularity */
11672 bp->tx_ticks = (50 / BNX2X_BTR) * BNX2X_BTR;
11673 bp->rx_ticks = (25 / BNX2X_BTR) * BNX2X_BTR;
11675 bp->current_interval = CHIP_REV_IS_SLOW(bp) ? 5*HZ : HZ;
11677 init_timer(&bp->timer);
11678 bp->timer.expires = jiffies + bp->current_interval;
11679 bp->timer.data = (unsigned long) bp;
11680 bp->timer.function = bnx2x_timer;
11682 if (SHMEM2_HAS(bp, dcbx_lldp_params_offset) &&
11683 SHMEM2_HAS(bp, dcbx_lldp_dcbx_stat_offset) &&
11684 SHMEM2_RD(bp, dcbx_lldp_params_offset) &&
11685 SHMEM2_RD(bp, dcbx_lldp_dcbx_stat_offset)) {
11686 bnx2x_dcbx_set_state(bp, true, BNX2X_DCBX_ENABLED_ON_NEG_ON);
11687 bnx2x_dcbx_init_params(bp);
11689 bnx2x_dcbx_set_state(bp, false, BNX2X_DCBX_ENABLED_OFF);
11692 if (CHIP_IS_E1x(bp))
11693 bp->cnic_base_cl_id = FP_SB_MAX_E1x;
11695 bp->cnic_base_cl_id = FP_SB_MAX_E2;
11697 /* multiple tx priority */
11700 else if (CHIP_IS_E1x(bp))
11701 bp->max_cos = BNX2X_MULTI_TX_COS_E1X;
11702 else if (CHIP_IS_E2(bp) || CHIP_IS_E3A0(bp))
11703 bp->max_cos = BNX2X_MULTI_TX_COS_E2_E3A0;
11704 else if (CHIP_IS_E3B0(bp))
11705 bp->max_cos = BNX2X_MULTI_TX_COS_E3B0;
11707 BNX2X_ERR("unknown chip %x revision %x\n",
11708 CHIP_NUM(bp), CHIP_REV(bp));
11709 BNX2X_DEV_INFO("set bp->max_cos to %d\n", bp->max_cos);
11711 /* We need at least one default status block for slow-path events,
11712 * second status block for the L2 queue, and a third status block for
11713 * CNIC if supported.
11716 bp->min_msix_vec_cnt = 1;
11717 else if (CNIC_SUPPORT(bp))
11718 bp->min_msix_vec_cnt = 3;
11719 else /* PF w/o cnic */
11720 bp->min_msix_vec_cnt = 2;
11721 BNX2X_DEV_INFO("bp->min_msix_vec_cnt %d", bp->min_msix_vec_cnt);
11723 bp->dump_preset_idx = 1;
11728 /****************************************************************************
11729 * General service functions
11730 ****************************************************************************/
11733 * net_device service functions
11736 /* called with rtnl_lock */
11737 static int bnx2x_open(struct net_device *dev)
11739 struct bnx2x *bp = netdev_priv(dev);
11742 bp->stats_init = true;
11744 netif_carrier_off(dev);
11746 bnx2x_set_power_state(bp, PCI_D0);
11748 /* If parity had happen during the unload, then attentions
11749 * and/or RECOVERY_IN_PROGRES may still be set. In this case we
11750 * want the first function loaded on the current engine to
11751 * complete the recovery.
11752 * Parity recovery is only relevant for PF driver.
11755 int other_engine = BP_PATH(bp) ? 0 : 1;
11756 bool other_load_status, load_status;
11757 bool global = false;
11759 other_load_status = bnx2x_get_load_status(bp, other_engine);
11760 load_status = bnx2x_get_load_status(bp, BP_PATH(bp));
11761 if (!bnx2x_reset_is_done(bp, BP_PATH(bp)) ||
11762 bnx2x_chk_parity_attn(bp, &global, true)) {
11764 /* If there are attentions and they are in a
11765 * global blocks, set the GLOBAL_RESET bit
11766 * regardless whether it will be this function
11767 * that will complete the recovery or not.
11770 bnx2x_set_reset_global(bp);
11772 /* Only the first function on the current
11773 * engine should try to recover in open. In case
11774 * of attentions in global blocks only the first
11775 * in the chip should try to recover.
11777 if ((!load_status &&
11778 (!global || !other_load_status)) &&
11779 bnx2x_trylock_leader_lock(bp) &&
11780 !bnx2x_leader_reset(bp)) {
11781 netdev_info(bp->dev,
11782 "Recovered in open\n");
11786 /* recovery has failed... */
11787 bnx2x_set_power_state(bp, PCI_D3hot);
11788 bp->recovery_state = BNX2X_RECOVERY_FAILED;
11790 BNX2X_ERR("Recovery flow hasn't been properly completed yet. Try again later.\n"
11791 "If you still see this message after a few retries then power cycle is required.\n");
11798 bp->recovery_state = BNX2X_RECOVERY_DONE;
11799 rc = bnx2x_nic_load(bp, LOAD_OPEN);
11805 /* called with rtnl_lock */
11806 static int bnx2x_close(struct net_device *dev)
11808 struct bnx2x *bp = netdev_priv(dev);
11810 /* Unload the driver, release IRQs */
11811 bnx2x_nic_unload(bp, UNLOAD_CLOSE, false);
11816 static int bnx2x_init_mcast_macs_list(struct bnx2x *bp,
11817 struct bnx2x_mcast_ramrod_params *p)
11819 int mc_count = netdev_mc_count(bp->dev);
11820 struct bnx2x_mcast_list_elem *mc_mac =
11821 kzalloc(sizeof(*mc_mac) * mc_count, GFP_ATOMIC);
11822 struct netdev_hw_addr *ha;
11827 INIT_LIST_HEAD(&p->mcast_list);
11829 netdev_for_each_mc_addr(ha, bp->dev) {
11830 mc_mac->mac = bnx2x_mc_addr(ha);
11831 list_add_tail(&mc_mac->link, &p->mcast_list);
11835 p->mcast_list_len = mc_count;
11840 static void bnx2x_free_mcast_macs_list(
11841 struct bnx2x_mcast_ramrod_params *p)
11843 struct bnx2x_mcast_list_elem *mc_mac =
11844 list_first_entry(&p->mcast_list, struct bnx2x_mcast_list_elem,
11852 * bnx2x_set_uc_list - configure a new unicast MACs list.
11854 * @bp: driver handle
11856 * We will use zero (0) as a MAC type for these MACs.
11858 static int bnx2x_set_uc_list(struct bnx2x *bp)
11861 struct net_device *dev = bp->dev;
11862 struct netdev_hw_addr *ha;
11863 struct bnx2x_vlan_mac_obj *mac_obj = &bp->sp_objs->mac_obj;
11864 unsigned long ramrod_flags = 0;
11866 /* First schedule a cleanup up of old configuration */
11867 rc = bnx2x_del_all_macs(bp, mac_obj, BNX2X_UC_LIST_MAC, false);
11869 BNX2X_ERR("Failed to schedule DELETE operations: %d\n", rc);
11873 netdev_for_each_uc_addr(ha, dev) {
11874 rc = bnx2x_set_mac_one(bp, bnx2x_uc_addr(ha), mac_obj, true,
11875 BNX2X_UC_LIST_MAC, &ramrod_flags);
11876 if (rc == -EEXIST) {
11878 "Failed to schedule ADD operations: %d\n", rc);
11879 /* do not treat adding same MAC as error */
11882 } else if (rc < 0) {
11884 BNX2X_ERR("Failed to schedule ADD operations: %d\n",
11890 /* Execute the pending commands */
11891 __set_bit(RAMROD_CONT, &ramrod_flags);
11892 return bnx2x_set_mac_one(bp, NULL, mac_obj, false /* don't care */,
11893 BNX2X_UC_LIST_MAC, &ramrod_flags);
11896 static int bnx2x_set_mc_list(struct bnx2x *bp)
11898 struct net_device *dev = bp->dev;
11899 struct bnx2x_mcast_ramrod_params rparam = {NULL};
11902 rparam.mcast_obj = &bp->mcast_obj;
11904 /* first, clear all configured multicast MACs */
11905 rc = bnx2x_config_mcast(bp, &rparam, BNX2X_MCAST_CMD_DEL);
11907 BNX2X_ERR("Failed to clear multicast configuration: %d\n", rc);
11911 /* then, configure a new MACs list */
11912 if (netdev_mc_count(dev)) {
11913 rc = bnx2x_init_mcast_macs_list(bp, &rparam);
11915 BNX2X_ERR("Failed to create multicast MACs list: %d\n",
11920 /* Now add the new MACs */
11921 rc = bnx2x_config_mcast(bp, &rparam,
11922 BNX2X_MCAST_CMD_ADD);
11924 BNX2X_ERR("Failed to set a new multicast configuration: %d\n",
11927 bnx2x_free_mcast_macs_list(&rparam);
11933 /* If bp->state is OPEN, should be called with netif_addr_lock_bh() */
11934 void bnx2x_set_rx_mode(struct net_device *dev)
11936 struct bnx2x *bp = netdev_priv(dev);
11938 if (bp->state != BNX2X_STATE_OPEN) {
11939 DP(NETIF_MSG_IFUP, "state is %x, returning\n", bp->state);
11942 /* Schedule an SP task to handle rest of change */
11943 DP(NETIF_MSG_IFUP, "Scheduling an Rx mode change\n");
11944 smp_mb__before_clear_bit();
11945 set_bit(BNX2X_SP_RTNL_RX_MODE, &bp->sp_rtnl_state);
11946 smp_mb__after_clear_bit();
11947 schedule_delayed_work(&bp->sp_rtnl_task, 0);
11951 void bnx2x_set_rx_mode_inner(struct bnx2x *bp)
11953 u32 rx_mode = BNX2X_RX_MODE_NORMAL;
11955 DP(NETIF_MSG_IFUP, "dev->flags = %x\n", bp->dev->flags);
11957 netif_addr_lock_bh(bp->dev);
11959 if (bp->dev->flags & IFF_PROMISC) {
11960 rx_mode = BNX2X_RX_MODE_PROMISC;
11961 } else if ((bp->dev->flags & IFF_ALLMULTI) ||
11962 ((netdev_mc_count(bp->dev) > BNX2X_MAX_MULTICAST) &&
11964 rx_mode = BNX2X_RX_MODE_ALLMULTI;
11967 /* some multicasts */
11968 if (bnx2x_set_mc_list(bp) < 0)
11969 rx_mode = BNX2X_RX_MODE_ALLMULTI;
11971 /* release bh lock, as bnx2x_set_uc_list might sleep */
11972 netif_addr_unlock_bh(bp->dev);
11973 if (bnx2x_set_uc_list(bp) < 0)
11974 rx_mode = BNX2X_RX_MODE_PROMISC;
11975 netif_addr_lock_bh(bp->dev);
11977 /* configuring mcast to a vf involves sleeping (when we
11978 * wait for the pf's response).
11980 smp_mb__before_clear_bit();
11981 set_bit(BNX2X_SP_RTNL_VFPF_MCAST,
11982 &bp->sp_rtnl_state);
11983 smp_mb__after_clear_bit();
11984 schedule_delayed_work(&bp->sp_rtnl_task, 0);
11988 bp->rx_mode = rx_mode;
11989 /* handle ISCSI SD mode */
11990 if (IS_MF_ISCSI_SD(bp))
11991 bp->rx_mode = BNX2X_RX_MODE_NONE;
11993 /* Schedule the rx_mode command */
11994 if (test_bit(BNX2X_FILTER_RX_MODE_PENDING, &bp->sp_state)) {
11995 set_bit(BNX2X_FILTER_RX_MODE_SCHED, &bp->sp_state);
11996 netif_addr_unlock_bh(bp->dev);
12001 bnx2x_set_storm_rx_mode(bp);
12002 netif_addr_unlock_bh(bp->dev);
12004 /* VF will need to request the PF to make this change, and so
12005 * the VF needs to release the bottom-half lock prior to the
12006 * request (as it will likely require sleep on the VF side)
12008 netif_addr_unlock_bh(bp->dev);
12009 bnx2x_vfpf_storm_rx_mode(bp);
12013 /* called with rtnl_lock */
12014 static int bnx2x_mdio_read(struct net_device *netdev, int prtad,
12015 int devad, u16 addr)
12017 struct bnx2x *bp = netdev_priv(netdev);
12021 DP(NETIF_MSG_LINK, "mdio_read: prtad 0x%x, devad 0x%x, addr 0x%x\n",
12022 prtad, devad, addr);
12024 /* The HW expects different devad if CL22 is used */
12025 devad = (devad == MDIO_DEVAD_NONE) ? DEFAULT_PHY_DEV_ADDR : devad;
12027 bnx2x_acquire_phy_lock(bp);
12028 rc = bnx2x_phy_read(&bp->link_params, prtad, devad, addr, &value);
12029 bnx2x_release_phy_lock(bp);
12030 DP(NETIF_MSG_LINK, "mdio_read_val 0x%x rc = 0x%x\n", value, rc);
12037 /* called with rtnl_lock */
12038 static int bnx2x_mdio_write(struct net_device *netdev, int prtad, int devad,
12039 u16 addr, u16 value)
12041 struct bnx2x *bp = netdev_priv(netdev);
12045 "mdio_write: prtad 0x%x, devad 0x%x, addr 0x%x, value 0x%x\n",
12046 prtad, devad, addr, value);
12048 /* The HW expects different devad if CL22 is used */
12049 devad = (devad == MDIO_DEVAD_NONE) ? DEFAULT_PHY_DEV_ADDR : devad;
12051 bnx2x_acquire_phy_lock(bp);
12052 rc = bnx2x_phy_write(&bp->link_params, prtad, devad, addr, value);
12053 bnx2x_release_phy_lock(bp);
12057 /* called with rtnl_lock */
12058 static int bnx2x_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
12060 struct bnx2x *bp = netdev_priv(dev);
12061 struct mii_ioctl_data *mdio = if_mii(ifr);
12063 DP(NETIF_MSG_LINK, "ioctl: phy id 0x%x, reg 0x%x, val_in 0x%x\n",
12064 mdio->phy_id, mdio->reg_num, mdio->val_in);
12066 if (!netif_running(dev))
12069 return mdio_mii_ioctl(&bp->mdio, mdio, cmd);
12072 #ifdef CONFIG_NET_POLL_CONTROLLER
12073 static void poll_bnx2x(struct net_device *dev)
12075 struct bnx2x *bp = netdev_priv(dev);
12078 for_each_eth_queue(bp, i) {
12079 struct bnx2x_fastpath *fp = &bp->fp[i];
12080 napi_schedule(&bnx2x_fp(bp, fp->index, napi));
12085 static int bnx2x_validate_addr(struct net_device *dev)
12087 struct bnx2x *bp = netdev_priv(dev);
12089 /* query the bulletin board for mac address configured by the PF */
12091 bnx2x_sample_bulletin(bp);
12093 if (!bnx2x_is_valid_ether_addr(bp, dev->dev_addr)) {
12094 BNX2X_ERR("Non-valid Ethernet address\n");
12095 return -EADDRNOTAVAIL;
12100 static int bnx2x_get_phys_port_id(struct net_device *netdev,
12101 struct netdev_phys_port_id *ppid)
12103 struct bnx2x *bp = netdev_priv(netdev);
12105 if (!(bp->flags & HAS_PHYS_PORT_ID))
12106 return -EOPNOTSUPP;
12108 ppid->id_len = sizeof(bp->phys_port_id);
12109 memcpy(ppid->id, bp->phys_port_id, ppid->id_len);
12114 static const struct net_device_ops bnx2x_netdev_ops = {
12115 .ndo_open = bnx2x_open,
12116 .ndo_stop = bnx2x_close,
12117 .ndo_start_xmit = bnx2x_start_xmit,
12118 .ndo_select_queue = bnx2x_select_queue,
12119 .ndo_set_rx_mode = bnx2x_set_rx_mode,
12120 .ndo_set_mac_address = bnx2x_change_mac_addr,
12121 .ndo_validate_addr = bnx2x_validate_addr,
12122 .ndo_do_ioctl = bnx2x_ioctl,
12123 .ndo_change_mtu = bnx2x_change_mtu,
12124 .ndo_fix_features = bnx2x_fix_features,
12125 .ndo_set_features = bnx2x_set_features,
12126 .ndo_tx_timeout = bnx2x_tx_timeout,
12127 #ifdef CONFIG_NET_POLL_CONTROLLER
12128 .ndo_poll_controller = poll_bnx2x,
12130 .ndo_setup_tc = bnx2x_setup_tc,
12131 #ifdef CONFIG_BNX2X_SRIOV
12132 .ndo_set_vf_mac = bnx2x_set_vf_mac,
12133 .ndo_set_vf_vlan = bnx2x_set_vf_vlan,
12134 .ndo_get_vf_config = bnx2x_get_vf_config,
12136 #ifdef NETDEV_FCOE_WWNN
12137 .ndo_fcoe_get_wwn = bnx2x_fcoe_get_wwn,
12140 #ifdef CONFIG_NET_RX_BUSY_POLL
12141 .ndo_busy_poll = bnx2x_low_latency_recv,
12143 .ndo_get_phys_port_id = bnx2x_get_phys_port_id,
12146 static int bnx2x_set_coherency_mask(struct bnx2x *bp)
12148 struct device *dev = &bp->pdev->dev;
12150 if (dma_set_mask_and_coherent(dev, DMA_BIT_MASK(64)) != 0 &&
12151 dma_set_mask_and_coherent(dev, DMA_BIT_MASK(32)) != 0) {
12152 dev_err(dev, "System does not support DMA, aborting\n");
12159 static int bnx2x_init_dev(struct bnx2x *bp, struct pci_dev *pdev,
12160 struct net_device *dev, unsigned long board_type)
12164 bool chip_is_e1x = (board_type == BCM57710 ||
12165 board_type == BCM57711 ||
12166 board_type == BCM57711E);
12168 SET_NETDEV_DEV(dev, &pdev->dev);
12173 rc = pci_enable_device(pdev);
12175 dev_err(&bp->pdev->dev,
12176 "Cannot enable PCI device, aborting\n");
12180 if (!(pci_resource_flags(pdev, 0) & IORESOURCE_MEM)) {
12181 dev_err(&bp->pdev->dev,
12182 "Cannot find PCI device base address, aborting\n");
12184 goto err_out_disable;
12187 if (IS_PF(bp) && !(pci_resource_flags(pdev, 2) & IORESOURCE_MEM)) {
12188 dev_err(&bp->pdev->dev, "Cannot find second PCI device base address, aborting\n");
12190 goto err_out_disable;
12193 pci_read_config_dword(pdev, PCICFG_REVISION_ID_OFFSET, &pci_cfg_dword);
12194 if ((pci_cfg_dword & PCICFG_REVESION_ID_MASK) ==
12195 PCICFG_REVESION_ID_ERROR_VAL) {
12196 pr_err("PCI device error, probably due to fan failure, aborting\n");
12198 goto err_out_disable;
12201 if (atomic_read(&pdev->enable_cnt) == 1) {
12202 rc = pci_request_regions(pdev, DRV_MODULE_NAME);
12204 dev_err(&bp->pdev->dev,
12205 "Cannot obtain PCI resources, aborting\n");
12206 goto err_out_disable;
12209 pci_set_master(pdev);
12210 pci_save_state(pdev);
12214 if (!pdev->pm_cap) {
12215 dev_err(&bp->pdev->dev,
12216 "Cannot find power management capability, aborting\n");
12218 goto err_out_release;
12222 if (!pci_is_pcie(pdev)) {
12223 dev_err(&bp->pdev->dev, "Not PCI Express, aborting\n");
12225 goto err_out_release;
12228 rc = bnx2x_set_coherency_mask(bp);
12230 goto err_out_release;
12232 dev->mem_start = pci_resource_start(pdev, 0);
12233 dev->base_addr = dev->mem_start;
12234 dev->mem_end = pci_resource_end(pdev, 0);
12236 dev->irq = pdev->irq;
12238 bp->regview = pci_ioremap_bar(pdev, 0);
12239 if (!bp->regview) {
12240 dev_err(&bp->pdev->dev,
12241 "Cannot map register space, aborting\n");
12243 goto err_out_release;
12246 /* In E1/E1H use pci device function given by kernel.
12247 * In E2/E3 read physical function from ME register since these chips
12248 * support Physical Device Assignment where kernel BDF maybe arbitrary
12249 * (depending on hypervisor).
12252 bp->pf_num = PCI_FUNC(pdev->devfn);
12255 pci_read_config_dword(bp->pdev,
12256 PCICFG_ME_REGISTER, &pci_cfg_dword);
12257 bp->pf_num = (u8)((pci_cfg_dword & ME_REG_ABS_PF_NUM) >>
12258 ME_REG_ABS_PF_NUM_SHIFT);
12260 BNX2X_DEV_INFO("me reg PF num: %d\n", bp->pf_num);
12262 /* clean indirect addresses */
12263 pci_write_config_dword(bp->pdev, PCICFG_GRC_ADDRESS,
12264 PCICFG_VENDOR_ID_OFFSET);
12266 * Clean the following indirect addresses for all functions since it
12267 * is not used by the driver.
12270 REG_WR(bp, PXP2_REG_PGL_ADDR_88_F0, 0);
12271 REG_WR(bp, PXP2_REG_PGL_ADDR_8C_F0, 0);
12272 REG_WR(bp, PXP2_REG_PGL_ADDR_90_F0, 0);
12273 REG_WR(bp, PXP2_REG_PGL_ADDR_94_F0, 0);
12276 REG_WR(bp, PXP2_REG_PGL_ADDR_88_F1, 0);
12277 REG_WR(bp, PXP2_REG_PGL_ADDR_8C_F1, 0);
12278 REG_WR(bp, PXP2_REG_PGL_ADDR_90_F1, 0);
12279 REG_WR(bp, PXP2_REG_PGL_ADDR_94_F1, 0);
12282 /* Enable internal target-read (in case we are probed after PF
12283 * FLR). Must be done prior to any BAR read access. Only for
12288 PGLUE_B_REG_INTERNAL_PFID_ENABLE_TARGET_READ, 1);
12291 dev->watchdog_timeo = TX_TIMEOUT;
12293 dev->netdev_ops = &bnx2x_netdev_ops;
12294 bnx2x_set_ethtool_ops(bp, dev);
12296 dev->priv_flags |= IFF_UNICAST_FLT;
12298 dev->hw_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM |
12299 NETIF_F_TSO | NETIF_F_TSO_ECN | NETIF_F_TSO6 |
12300 NETIF_F_RXCSUM | NETIF_F_LRO | NETIF_F_GRO |
12301 NETIF_F_RXHASH | NETIF_F_HW_VLAN_CTAG_TX;
12302 if (!CHIP_IS_E1x(bp)) {
12303 dev->hw_features |= NETIF_F_GSO_GRE | NETIF_F_GSO_UDP_TUNNEL |
12304 NETIF_F_GSO_IPIP | NETIF_F_GSO_SIT;
12305 dev->hw_enc_features =
12306 NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM | NETIF_F_SG |
12307 NETIF_F_TSO | NETIF_F_TSO_ECN | NETIF_F_TSO6 |
12310 NETIF_F_GSO_GRE | NETIF_F_GSO_UDP_TUNNEL;
12313 dev->vlan_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM |
12314 NETIF_F_TSO | NETIF_F_TSO_ECN | NETIF_F_TSO6 | NETIF_F_HIGHDMA;
12316 dev->features |= dev->hw_features | NETIF_F_HW_VLAN_CTAG_RX;
12317 dev->features |= NETIF_F_HIGHDMA;
12319 /* Add Loopback capability to the device */
12320 dev->hw_features |= NETIF_F_LOOPBACK;
12323 dev->dcbnl_ops = &bnx2x_dcbnl_ops;
12326 /* get_port_hwinfo() will set prtad and mmds properly */
12327 bp->mdio.prtad = MDIO_PRTAD_NONE;
12329 bp->mdio.mode_support = MDIO_SUPPORTS_C45 | MDIO_EMULATE_C22;
12330 bp->mdio.dev = dev;
12331 bp->mdio.mdio_read = bnx2x_mdio_read;
12332 bp->mdio.mdio_write = bnx2x_mdio_write;
12337 if (atomic_read(&pdev->enable_cnt) == 1)
12338 pci_release_regions(pdev);
12341 pci_disable_device(pdev);
12347 static int bnx2x_check_firmware(struct bnx2x *bp)
12349 const struct firmware *firmware = bp->firmware;
12350 struct bnx2x_fw_file_hdr *fw_hdr;
12351 struct bnx2x_fw_file_section *sections;
12352 u32 offset, len, num_ops;
12353 __be16 *ops_offsets;
12357 if (firmware->size < sizeof(struct bnx2x_fw_file_hdr)) {
12358 BNX2X_ERR("Wrong FW size\n");
12362 fw_hdr = (struct bnx2x_fw_file_hdr *)firmware->data;
12363 sections = (struct bnx2x_fw_file_section *)fw_hdr;
12365 /* Make sure none of the offsets and sizes make us read beyond
12366 * the end of the firmware data */
12367 for (i = 0; i < sizeof(*fw_hdr) / sizeof(*sections); i++) {
12368 offset = be32_to_cpu(sections[i].offset);
12369 len = be32_to_cpu(sections[i].len);
12370 if (offset + len > firmware->size) {
12371 BNX2X_ERR("Section %d length is out of bounds\n", i);
12376 /* Likewise for the init_ops offsets */
12377 offset = be32_to_cpu(fw_hdr->init_ops_offsets.offset);
12378 ops_offsets = (__force __be16 *)(firmware->data + offset);
12379 num_ops = be32_to_cpu(fw_hdr->init_ops.len) / sizeof(struct raw_op);
12381 for (i = 0; i < be32_to_cpu(fw_hdr->init_ops_offsets.len) / 2; i++) {
12382 if (be16_to_cpu(ops_offsets[i]) > num_ops) {
12383 BNX2X_ERR("Section offset %d is out of bounds\n", i);
12388 /* Check FW version */
12389 offset = be32_to_cpu(fw_hdr->fw_version.offset);
12390 fw_ver = firmware->data + offset;
12391 if ((fw_ver[0] != BCM_5710_FW_MAJOR_VERSION) ||
12392 (fw_ver[1] != BCM_5710_FW_MINOR_VERSION) ||
12393 (fw_ver[2] != BCM_5710_FW_REVISION_VERSION) ||
12394 (fw_ver[3] != BCM_5710_FW_ENGINEERING_VERSION)) {
12395 BNX2X_ERR("Bad FW version:%d.%d.%d.%d. Should be %d.%d.%d.%d\n",
12396 fw_ver[0], fw_ver[1], fw_ver[2], fw_ver[3],
12397 BCM_5710_FW_MAJOR_VERSION,
12398 BCM_5710_FW_MINOR_VERSION,
12399 BCM_5710_FW_REVISION_VERSION,
12400 BCM_5710_FW_ENGINEERING_VERSION);
12407 static void be32_to_cpu_n(const u8 *_source, u8 *_target, u32 n)
12409 const __be32 *source = (const __be32 *)_source;
12410 u32 *target = (u32 *)_target;
12413 for (i = 0; i < n/4; i++)
12414 target[i] = be32_to_cpu(source[i]);
12418 Ops array is stored in the following format:
12419 {op(8bit), offset(24bit, big endian), data(32bit, big endian)}
12421 static void bnx2x_prep_ops(const u8 *_source, u8 *_target, u32 n)
12423 const __be32 *source = (const __be32 *)_source;
12424 struct raw_op *target = (struct raw_op *)_target;
12427 for (i = 0, j = 0; i < n/8; i++, j += 2) {
12428 tmp = be32_to_cpu(source[j]);
12429 target[i].op = (tmp >> 24) & 0xff;
12430 target[i].offset = tmp & 0xffffff;
12431 target[i].raw_data = be32_to_cpu(source[j + 1]);
12435 /* IRO array is stored in the following format:
12436 * {base(24bit), m1(16bit), m2(16bit), m3(16bit), size(16bit) }
12438 static void bnx2x_prep_iro(const u8 *_source, u8 *_target, u32 n)
12440 const __be32 *source = (const __be32 *)_source;
12441 struct iro *target = (struct iro *)_target;
12444 for (i = 0, j = 0; i < n/sizeof(struct iro); i++) {
12445 target[i].base = be32_to_cpu(source[j]);
12447 tmp = be32_to_cpu(source[j]);
12448 target[i].m1 = (tmp >> 16) & 0xffff;
12449 target[i].m2 = tmp & 0xffff;
12451 tmp = be32_to_cpu(source[j]);
12452 target[i].m3 = (tmp >> 16) & 0xffff;
12453 target[i].size = tmp & 0xffff;
12458 static void be16_to_cpu_n(const u8 *_source, u8 *_target, u32 n)
12460 const __be16 *source = (const __be16 *)_source;
12461 u16 *target = (u16 *)_target;
12464 for (i = 0; i < n/2; i++)
12465 target[i] = be16_to_cpu(source[i]);
12468 #define BNX2X_ALLOC_AND_SET(arr, lbl, func) \
12470 u32 len = be32_to_cpu(fw_hdr->arr.len); \
12471 bp->arr = kmalloc(len, GFP_KERNEL); \
12474 func(bp->firmware->data + be32_to_cpu(fw_hdr->arr.offset), \
12475 (u8 *)bp->arr, len); \
12478 static int bnx2x_init_firmware(struct bnx2x *bp)
12480 const char *fw_file_name;
12481 struct bnx2x_fw_file_hdr *fw_hdr;
12487 if (CHIP_IS_E1(bp))
12488 fw_file_name = FW_FILE_NAME_E1;
12489 else if (CHIP_IS_E1H(bp))
12490 fw_file_name = FW_FILE_NAME_E1H;
12491 else if (!CHIP_IS_E1x(bp))
12492 fw_file_name = FW_FILE_NAME_E2;
12494 BNX2X_ERR("Unsupported chip revision\n");
12497 BNX2X_DEV_INFO("Loading %s\n", fw_file_name);
12499 rc = request_firmware(&bp->firmware, fw_file_name, &bp->pdev->dev);
12501 BNX2X_ERR("Can't load firmware file %s\n",
12503 goto request_firmware_exit;
12506 rc = bnx2x_check_firmware(bp);
12508 BNX2X_ERR("Corrupt firmware file %s\n", fw_file_name);
12509 goto request_firmware_exit;
12512 fw_hdr = (struct bnx2x_fw_file_hdr *)bp->firmware->data;
12514 /* Initialize the pointers to the init arrays */
12516 BNX2X_ALLOC_AND_SET(init_data, request_firmware_exit, be32_to_cpu_n);
12519 BNX2X_ALLOC_AND_SET(init_ops, init_ops_alloc_err, bnx2x_prep_ops);
12522 BNX2X_ALLOC_AND_SET(init_ops_offsets, init_offsets_alloc_err,
12525 /* STORMs firmware */
12526 INIT_TSEM_INT_TABLE_DATA(bp) = bp->firmware->data +
12527 be32_to_cpu(fw_hdr->tsem_int_table_data.offset);
12528 INIT_TSEM_PRAM_DATA(bp) = bp->firmware->data +
12529 be32_to_cpu(fw_hdr->tsem_pram_data.offset);
12530 INIT_USEM_INT_TABLE_DATA(bp) = bp->firmware->data +
12531 be32_to_cpu(fw_hdr->usem_int_table_data.offset);
12532 INIT_USEM_PRAM_DATA(bp) = bp->firmware->data +
12533 be32_to_cpu(fw_hdr->usem_pram_data.offset);
12534 INIT_XSEM_INT_TABLE_DATA(bp) = bp->firmware->data +
12535 be32_to_cpu(fw_hdr->xsem_int_table_data.offset);
12536 INIT_XSEM_PRAM_DATA(bp) = bp->firmware->data +
12537 be32_to_cpu(fw_hdr->xsem_pram_data.offset);
12538 INIT_CSEM_INT_TABLE_DATA(bp) = bp->firmware->data +
12539 be32_to_cpu(fw_hdr->csem_int_table_data.offset);
12540 INIT_CSEM_PRAM_DATA(bp) = bp->firmware->data +
12541 be32_to_cpu(fw_hdr->csem_pram_data.offset);
12543 BNX2X_ALLOC_AND_SET(iro_arr, iro_alloc_err, bnx2x_prep_iro);
12548 kfree(bp->init_ops_offsets);
12549 init_offsets_alloc_err:
12550 kfree(bp->init_ops);
12551 init_ops_alloc_err:
12552 kfree(bp->init_data);
12553 request_firmware_exit:
12554 release_firmware(bp->firmware);
12555 bp->firmware = NULL;
12560 static void bnx2x_release_firmware(struct bnx2x *bp)
12562 kfree(bp->init_ops_offsets);
12563 kfree(bp->init_ops);
12564 kfree(bp->init_data);
12565 release_firmware(bp->firmware);
12566 bp->firmware = NULL;
12569 static struct bnx2x_func_sp_drv_ops bnx2x_func_sp_drv = {
12570 .init_hw_cmn_chip = bnx2x_init_hw_common_chip,
12571 .init_hw_cmn = bnx2x_init_hw_common,
12572 .init_hw_port = bnx2x_init_hw_port,
12573 .init_hw_func = bnx2x_init_hw_func,
12575 .reset_hw_cmn = bnx2x_reset_common,
12576 .reset_hw_port = bnx2x_reset_port,
12577 .reset_hw_func = bnx2x_reset_func,
12579 .gunzip_init = bnx2x_gunzip_init,
12580 .gunzip_end = bnx2x_gunzip_end,
12582 .init_fw = bnx2x_init_firmware,
12583 .release_fw = bnx2x_release_firmware,
12586 void bnx2x__init_func_obj(struct bnx2x *bp)
12588 /* Prepare DMAE related driver resources */
12589 bnx2x_setup_dmae(bp);
12591 bnx2x_init_func_obj(bp, &bp->func_obj,
12592 bnx2x_sp(bp, func_rdata),
12593 bnx2x_sp_mapping(bp, func_rdata),
12594 bnx2x_sp(bp, func_afex_rdata),
12595 bnx2x_sp_mapping(bp, func_afex_rdata),
12596 &bnx2x_func_sp_drv);
12599 /* must be called after sriov-enable */
12600 static int bnx2x_set_qm_cid_count(struct bnx2x *bp)
12602 int cid_count = BNX2X_L2_MAX_CID(bp);
12605 cid_count += BNX2X_VF_CIDS;
12607 if (CNIC_SUPPORT(bp))
12608 cid_count += CNIC_CID_MAX;
12610 return roundup(cid_count, QM_CID_ROUND);
12614 * bnx2x_get_num_none_def_sbs - return the number of none default SBs
12619 static int bnx2x_get_num_non_def_sbs(struct pci_dev *pdev, int cnic_cnt)
12625 * If MSI-X is not supported - return number of SBs needed to support
12626 * one fast path queue: one FP queue + SB for CNIC
12628 if (!pdev->msix_cap) {
12629 dev_info(&pdev->dev, "no msix capability found\n");
12630 return 1 + cnic_cnt;
12632 dev_info(&pdev->dev, "msix capability found\n");
12635 * The value in the PCI configuration space is the index of the last
12636 * entry, namely one less than the actual size of the table, which is
12637 * exactly what we want to return from this function: number of all SBs
12638 * without the default SB.
12639 * For VFs there is no default SB, then we return (index+1).
12641 pci_read_config_word(pdev, pdev->msix_cap + PCI_MSI_FLAGS, &control);
12643 index = control & PCI_MSIX_FLAGS_QSIZE;
12648 static int set_max_cos_est(int chip_id)
12654 return BNX2X_MULTI_TX_COS_E1X;
12657 return BNX2X_MULTI_TX_COS_E2_E3A0;
12662 case BCM57840_4_10:
12663 case BCM57840_2_20:
12669 return BNX2X_MULTI_TX_COS_E3B0;
12677 pr_err("Unknown board_type (%d), aborting\n", chip_id);
12682 static int set_is_vf(int chip_id)
12696 struct cnic_eth_dev *bnx2x_cnic_probe(struct net_device *dev);
12698 static int bnx2x_init_one(struct pci_dev *pdev,
12699 const struct pci_device_id *ent)
12701 struct net_device *dev = NULL;
12703 enum pcie_link_width pcie_width;
12704 enum pci_bus_speed pcie_speed;
12705 int rc, max_non_def_sbs;
12706 int rx_count, tx_count, rss_count, doorbell_size;
12711 /* An estimated maximum supported CoS number according to the chip
12713 * We will try to roughly estimate the maximum number of CoSes this chip
12714 * may support in order to minimize the memory allocated for Tx
12715 * netdev_queue's. This number will be accurately calculated during the
12716 * initialization of bp->max_cos based on the chip versions AND chip
12717 * revision in the bnx2x_init_bp().
12719 max_cos_est = set_max_cos_est(ent->driver_data);
12720 if (max_cos_est < 0)
12721 return max_cos_est;
12722 is_vf = set_is_vf(ent->driver_data);
12723 cnic_cnt = is_vf ? 0 : 1;
12725 max_non_def_sbs = bnx2x_get_num_non_def_sbs(pdev, cnic_cnt);
12727 /* add another SB for VF as it has no default SB */
12728 max_non_def_sbs += is_vf ? 1 : 0;
12730 /* Maximum number of RSS queues: one IGU SB goes to CNIC */
12731 rss_count = max_non_def_sbs - cnic_cnt;
12736 /* Maximum number of netdev Rx queues: RSS + FCoE L2 */
12737 rx_count = rss_count + cnic_cnt;
12739 /* Maximum number of netdev Tx queues:
12740 * Maximum TSS queues * Maximum supported number of CoS + FCoE L2
12742 tx_count = rss_count * max_cos_est + cnic_cnt;
12744 /* dev zeroed in init_etherdev */
12745 dev = alloc_etherdev_mqs(sizeof(*bp), tx_count, rx_count);
12749 bp = netdev_priv(dev);
12753 bp->flags |= IS_VF_FLAG;
12755 bp->igu_sb_cnt = max_non_def_sbs;
12756 bp->igu_base_addr = IS_VF(bp) ? PXP_VF_ADDR_IGU_START : BAR_IGU_INTMEM;
12757 bp->msg_enable = debug;
12758 bp->cnic_support = cnic_cnt;
12759 bp->cnic_probe = bnx2x_cnic_probe;
12761 pci_set_drvdata(pdev, dev);
12763 rc = bnx2x_init_dev(bp, pdev, dev, ent->driver_data);
12769 BNX2X_DEV_INFO("This is a %s function\n",
12770 IS_PF(bp) ? "physical" : "virtual");
12771 BNX2X_DEV_INFO("Cnic support is %s\n", CNIC_SUPPORT(bp) ? "on" : "off");
12772 BNX2X_DEV_INFO("Max num of status blocks %d\n", max_non_def_sbs);
12773 BNX2X_DEV_INFO("Allocated netdev with %d tx and %d rx queues\n",
12774 tx_count, rx_count);
12776 rc = bnx2x_init_bp(bp);
12778 goto init_one_exit;
12780 /* Map doorbells here as we need the real value of bp->max_cos which
12781 * is initialized in bnx2x_init_bp() to determine the number of
12785 bp->doorbells = bnx2x_vf_doorbells(bp);
12786 rc = bnx2x_vf_pci_alloc(bp);
12788 goto init_one_exit;
12790 doorbell_size = BNX2X_L2_MAX_CID(bp) * (1 << BNX2X_DB_SHIFT);
12791 if (doorbell_size > pci_resource_len(pdev, 2)) {
12792 dev_err(&bp->pdev->dev,
12793 "Cannot map doorbells, bar size too small, aborting\n");
12795 goto init_one_exit;
12797 bp->doorbells = ioremap_nocache(pci_resource_start(pdev, 2),
12800 if (!bp->doorbells) {
12801 dev_err(&bp->pdev->dev,
12802 "Cannot map doorbell space, aborting\n");
12804 goto init_one_exit;
12808 rc = bnx2x_vfpf_acquire(bp, tx_count, rx_count);
12810 goto init_one_exit;
12813 /* Enable SRIOV if capability found in configuration space */
12814 rc = bnx2x_iov_init_one(bp, int_mode, BNX2X_MAX_NUM_OF_VFS);
12816 goto init_one_exit;
12818 /* calc qm_cid_count */
12819 bp->qm_cid_count = bnx2x_set_qm_cid_count(bp);
12820 BNX2X_DEV_INFO("qm_cid_count %d\n", bp->qm_cid_count);
12822 /* disable FCOE L2 queue for E1x*/
12823 if (CHIP_IS_E1x(bp))
12824 bp->flags |= NO_FCOE_FLAG;
12826 /* Set bp->num_queues for MSI-X mode*/
12827 bnx2x_set_num_queues(bp);
12829 /* Configure interrupt mode: try to enable MSI-X/MSI if
12832 rc = bnx2x_set_int_mode(bp);
12834 dev_err(&pdev->dev, "Cannot set interrupts\n");
12835 goto init_one_exit;
12837 BNX2X_DEV_INFO("set interrupts successfully\n");
12839 /* register the net device */
12840 rc = register_netdev(dev);
12842 dev_err(&pdev->dev, "Cannot register net device\n");
12843 goto init_one_exit;
12845 BNX2X_DEV_INFO("device name after netdev register %s\n", dev->name);
12847 if (!NO_FCOE(bp)) {
12848 /* Add storage MAC address */
12850 dev_addr_add(bp->dev, bp->fip_mac, NETDEV_HW_ADDR_T_SAN);
12853 if (pcie_get_minimum_link(bp->pdev, &pcie_speed, &pcie_width) ||
12854 pcie_speed == PCI_SPEED_UNKNOWN ||
12855 pcie_width == PCIE_LNK_WIDTH_UNKNOWN)
12856 BNX2X_DEV_INFO("Failed to determine PCI Express Bandwidth\n");
12859 "%s (%c%d) PCI-E x%d %s found at mem %lx, IRQ %d, node addr %pM\n",
12860 board_info[ent->driver_data].name,
12861 (CHIP_REV(bp) >> 12) + 'A', (CHIP_METAL(bp) >> 4),
12863 pcie_speed == PCIE_SPEED_2_5GT ? "2.5GHz" :
12864 pcie_speed == PCIE_SPEED_5_0GT ? "5.0GHz" :
12865 pcie_speed == PCIE_SPEED_8_0GT ? "8.0GHz" :
12867 dev->base_addr, bp->pdev->irq, dev->dev_addr);
12873 iounmap(bp->regview);
12875 if (IS_PF(bp) && bp->doorbells)
12876 iounmap(bp->doorbells);
12880 if (atomic_read(&pdev->enable_cnt) == 1)
12881 pci_release_regions(pdev);
12883 pci_disable_device(pdev);
12888 static void __bnx2x_remove(struct pci_dev *pdev,
12889 struct net_device *dev,
12891 bool remove_netdev)
12893 /* Delete storage MAC address */
12894 if (!NO_FCOE(bp)) {
12896 dev_addr_del(bp->dev, bp->fip_mac, NETDEV_HW_ADDR_T_SAN);
12901 /* Delete app tlvs from dcbnl */
12902 bnx2x_dcbnl_update_applist(bp, true);
12907 (bp->flags & BC_SUPPORTS_RMMOD_CMD))
12908 bnx2x_fw_command(bp, DRV_MSG_CODE_RMMOD, 0);
12910 /* Close the interface - either directly or implicitly */
12911 if (remove_netdev) {
12912 unregister_netdev(dev);
12919 bnx2x_iov_remove_one(bp);
12921 /* Power on: we can't let PCI layer write to us while we are in D3 */
12923 bnx2x_set_power_state(bp, PCI_D0);
12925 /* Disable MSI/MSI-X */
12926 bnx2x_disable_msi(bp);
12930 bnx2x_set_power_state(bp, PCI_D3hot);
12932 /* Make sure RESET task is not scheduled before continuing */
12933 cancel_delayed_work_sync(&bp->sp_rtnl_task);
12935 /* send message via vfpf channel to release the resources of this vf */
12937 bnx2x_vfpf_release(bp);
12939 /* Assumes no further PCIe PM changes will occur */
12940 if (system_state == SYSTEM_POWER_OFF) {
12941 pci_wake_from_d3(pdev, bp->wol);
12942 pci_set_power_state(pdev, PCI_D3hot);
12946 iounmap(bp->regview);
12948 /* for vf doorbells are part of the regview and were unmapped along with
12949 * it. FW is only loaded by PF.
12953 iounmap(bp->doorbells);
12955 bnx2x_release_firmware(bp);
12957 bnx2x_free_mem_bp(bp);
12962 if (atomic_read(&pdev->enable_cnt) == 1)
12963 pci_release_regions(pdev);
12965 pci_disable_device(pdev);
12968 static void bnx2x_remove_one(struct pci_dev *pdev)
12970 struct net_device *dev = pci_get_drvdata(pdev);
12974 dev_err(&pdev->dev, "BAD net device from bnx2x_init_one\n");
12977 bp = netdev_priv(dev);
12979 __bnx2x_remove(pdev, dev, bp, true);
12982 static int bnx2x_eeh_nic_unload(struct bnx2x *bp)
12984 bp->state = BNX2X_STATE_CLOSING_WAIT4_HALT;
12986 bp->rx_mode = BNX2X_RX_MODE_NONE;
12988 if (CNIC_LOADED(bp))
12989 bnx2x_cnic_notify(bp, CNIC_CTL_STOP_CMD);
12992 bnx2x_tx_disable(bp);
12993 /* Delete all NAPI objects */
12994 bnx2x_del_all_napi(bp);
12995 if (CNIC_LOADED(bp))
12996 bnx2x_del_all_napi_cnic(bp);
12997 netdev_reset_tc(bp->dev);
12999 del_timer_sync(&bp->timer);
13000 cancel_delayed_work(&bp->sp_task);
13001 cancel_delayed_work(&bp->period_task);
13003 spin_lock_bh(&bp->stats_lock);
13004 bp->stats_state = STATS_STATE_DISABLED;
13005 spin_unlock_bh(&bp->stats_lock);
13007 bnx2x_save_statistics(bp);
13009 netif_carrier_off(bp->dev);
13015 * bnx2x_io_error_detected - called when PCI error is detected
13016 * @pdev: Pointer to PCI device
13017 * @state: The current pci connection state
13019 * This function is called after a PCI bus error affecting
13020 * this device has been detected.
13022 static pci_ers_result_t bnx2x_io_error_detected(struct pci_dev *pdev,
13023 pci_channel_state_t state)
13025 struct net_device *dev = pci_get_drvdata(pdev);
13026 struct bnx2x *bp = netdev_priv(dev);
13030 BNX2X_ERR("IO error detected\n");
13032 netif_device_detach(dev);
13034 if (state == pci_channel_io_perm_failure) {
13036 return PCI_ERS_RESULT_DISCONNECT;
13039 if (netif_running(dev))
13040 bnx2x_eeh_nic_unload(bp);
13042 bnx2x_prev_path_mark_eeh(bp);
13044 pci_disable_device(pdev);
13048 /* Request a slot reset */
13049 return PCI_ERS_RESULT_NEED_RESET;
13053 * bnx2x_io_slot_reset - called after the PCI bus has been reset
13054 * @pdev: Pointer to PCI device
13056 * Restart the card from scratch, as if from a cold-boot.
13058 static pci_ers_result_t bnx2x_io_slot_reset(struct pci_dev *pdev)
13060 struct net_device *dev = pci_get_drvdata(pdev);
13061 struct bnx2x *bp = netdev_priv(dev);
13065 BNX2X_ERR("IO slot reset initializing...\n");
13066 if (pci_enable_device(pdev)) {
13067 dev_err(&pdev->dev,
13068 "Cannot re-enable PCI device after reset\n");
13070 return PCI_ERS_RESULT_DISCONNECT;
13073 pci_set_master(pdev);
13074 pci_restore_state(pdev);
13075 pci_save_state(pdev);
13077 if (netif_running(dev))
13078 bnx2x_set_power_state(bp, PCI_D0);
13080 if (netif_running(dev)) {
13081 BNX2X_ERR("IO slot reset --> driver unload\n");
13083 /* MCP should have been reset; Need to wait for validity */
13084 bnx2x_init_shmem(bp);
13086 if (IS_PF(bp) && SHMEM2_HAS(bp, drv_capabilities_flag)) {
13090 drv_capabilities_flag[BP_FW_MB_IDX(bp)]);
13091 SHMEM2_WR(bp, drv_capabilities_flag[BP_FW_MB_IDX(bp)],
13092 v & ~DRV_FLAGS_CAPABILITIES_LOADED_L2);
13094 bnx2x_drain_tx_queues(bp);
13095 bnx2x_send_unload_req(bp, UNLOAD_RECOVERY);
13096 bnx2x_netif_stop(bp, 1);
13097 bnx2x_free_irq(bp);
13099 /* Report UNLOAD_DONE to MCP */
13100 bnx2x_send_unload_done(bp, true);
13105 bnx2x_prev_unload(bp);
13107 /* We should have reseted the engine, so It's fair to
13108 * assume the FW will no longer write to the bnx2x driver.
13110 bnx2x_squeeze_objects(bp);
13111 bnx2x_free_skbs(bp);
13112 for_each_rx_queue(bp, i)
13113 bnx2x_free_rx_sge_range(bp, bp->fp + i, NUM_RX_SGE);
13114 bnx2x_free_fp_mem(bp);
13115 bnx2x_free_mem(bp);
13117 bp->state = BNX2X_STATE_CLOSED;
13122 return PCI_ERS_RESULT_RECOVERED;
13126 * bnx2x_io_resume - called when traffic can start flowing again
13127 * @pdev: Pointer to PCI device
13129 * This callback is called when the error recovery driver tells us that
13130 * its OK to resume normal operation.
13132 static void bnx2x_io_resume(struct pci_dev *pdev)
13134 struct net_device *dev = pci_get_drvdata(pdev);
13135 struct bnx2x *bp = netdev_priv(dev);
13137 if (bp->recovery_state != BNX2X_RECOVERY_DONE) {
13138 netdev_err(bp->dev, "Handling parity error recovery. Try again later\n");
13144 bp->fw_seq = SHMEM_RD(bp, func_mb[BP_FW_MB_IDX(bp)].drv_mb_header) &
13145 DRV_MSG_SEQ_NUMBER_MASK;
13147 if (netif_running(dev))
13148 bnx2x_nic_load(bp, LOAD_NORMAL);
13150 netif_device_attach(dev);
13155 static const struct pci_error_handlers bnx2x_err_handler = {
13156 .error_detected = bnx2x_io_error_detected,
13157 .slot_reset = bnx2x_io_slot_reset,
13158 .resume = bnx2x_io_resume,
13161 static void bnx2x_shutdown(struct pci_dev *pdev)
13163 struct net_device *dev = pci_get_drvdata(pdev);
13169 bp = netdev_priv(dev);
13174 netif_device_detach(dev);
13177 /* Don't remove the netdevice, as there are scenarios which will cause
13178 * the kernel to hang, e.g., when trying to remove bnx2i while the
13179 * rootfs is mounted from SAN.
13181 __bnx2x_remove(pdev, dev, bp, false);
13184 static struct pci_driver bnx2x_pci_driver = {
13185 .name = DRV_MODULE_NAME,
13186 .id_table = bnx2x_pci_tbl,
13187 .probe = bnx2x_init_one,
13188 .remove = bnx2x_remove_one,
13189 .suspend = bnx2x_suspend,
13190 .resume = bnx2x_resume,
13191 .err_handler = &bnx2x_err_handler,
13192 #ifdef CONFIG_BNX2X_SRIOV
13193 .sriov_configure = bnx2x_sriov_configure,
13195 .shutdown = bnx2x_shutdown,
13198 static int __init bnx2x_init(void)
13202 pr_info("%s", version);
13204 bnx2x_wq = create_singlethread_workqueue("bnx2x");
13205 if (bnx2x_wq == NULL) {
13206 pr_err("Cannot create workqueue\n");
13210 ret = pci_register_driver(&bnx2x_pci_driver);
13212 pr_err("Cannot register driver\n");
13213 destroy_workqueue(bnx2x_wq);
13218 static void __exit bnx2x_cleanup(void)
13220 struct list_head *pos, *q;
13222 pci_unregister_driver(&bnx2x_pci_driver);
13224 destroy_workqueue(bnx2x_wq);
13226 /* Free globally allocated resources */
13227 list_for_each_safe(pos, q, &bnx2x_prev_list) {
13228 struct bnx2x_prev_path_list *tmp =
13229 list_entry(pos, struct bnx2x_prev_path_list, list);
13235 void bnx2x_notify_link_changed(struct bnx2x *bp)
13237 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_12 + BP_FUNC(bp)*sizeof(u32), 1);
13240 module_init(bnx2x_init);
13241 module_exit(bnx2x_cleanup);
13244 * bnx2x_set_iscsi_eth_mac_addr - set iSCSI MAC(s).
13246 * @bp: driver handle
13247 * @set: set or clear the CAM entry
13249 * This function will wait until the ramrod completion returns.
13250 * Return 0 if success, -ENODEV if ramrod doesn't return.
13252 static int bnx2x_set_iscsi_eth_mac_addr(struct bnx2x *bp)
13254 unsigned long ramrod_flags = 0;
13256 __set_bit(RAMROD_COMP_WAIT, &ramrod_flags);
13257 return bnx2x_set_mac_one(bp, bp->cnic_eth_dev.iscsi_mac,
13258 &bp->iscsi_l2_mac_obj, true,
13259 BNX2X_ISCSI_ETH_MAC, &ramrod_flags);
13262 /* count denotes the number of new completions we have seen */
13263 static void bnx2x_cnic_sp_post(struct bnx2x *bp, int count)
13265 struct eth_spe *spe;
13266 int cxt_index, cxt_offset;
13268 #ifdef BNX2X_STOP_ON_ERROR
13269 if (unlikely(bp->panic))
13273 spin_lock_bh(&bp->spq_lock);
13274 BUG_ON(bp->cnic_spq_pending < count);
13275 bp->cnic_spq_pending -= count;
13277 for (; bp->cnic_kwq_pending; bp->cnic_kwq_pending--) {
13278 u16 type = (le16_to_cpu(bp->cnic_kwq_cons->hdr.type)
13279 & SPE_HDR_CONN_TYPE) >>
13280 SPE_HDR_CONN_TYPE_SHIFT;
13281 u8 cmd = (le32_to_cpu(bp->cnic_kwq_cons->hdr.conn_and_cmd_data)
13282 >> SPE_HDR_CMD_ID_SHIFT) & 0xff;
13284 /* Set validation for iSCSI L2 client before sending SETUP
13287 if (type == ETH_CONNECTION_TYPE) {
13288 if (cmd == RAMROD_CMD_ID_ETH_CLIENT_SETUP) {
13289 cxt_index = BNX2X_ISCSI_ETH_CID(bp) /
13291 cxt_offset = BNX2X_ISCSI_ETH_CID(bp) -
13292 (cxt_index * ILT_PAGE_CIDS);
13293 bnx2x_set_ctx_validation(bp,
13294 &bp->context[cxt_index].
13295 vcxt[cxt_offset].eth,
13296 BNX2X_ISCSI_ETH_CID(bp));
13301 * There may be not more than 8 L2, not more than 8 L5 SPEs
13302 * and in the air. We also check that number of outstanding
13303 * COMMON ramrods is not more than the EQ and SPQ can
13306 if (type == ETH_CONNECTION_TYPE) {
13307 if (!atomic_read(&bp->cq_spq_left))
13310 atomic_dec(&bp->cq_spq_left);
13311 } else if (type == NONE_CONNECTION_TYPE) {
13312 if (!atomic_read(&bp->eq_spq_left))
13315 atomic_dec(&bp->eq_spq_left);
13316 } else if ((type == ISCSI_CONNECTION_TYPE) ||
13317 (type == FCOE_CONNECTION_TYPE)) {
13318 if (bp->cnic_spq_pending >=
13319 bp->cnic_eth_dev.max_kwqe_pending)
13322 bp->cnic_spq_pending++;
13324 BNX2X_ERR("Unknown SPE type: %d\n", type);
13329 spe = bnx2x_sp_get_next(bp);
13330 *spe = *bp->cnic_kwq_cons;
13332 DP(BNX2X_MSG_SP, "pending on SPQ %d, on KWQ %d count %d\n",
13333 bp->cnic_spq_pending, bp->cnic_kwq_pending, count);
13335 if (bp->cnic_kwq_cons == bp->cnic_kwq_last)
13336 bp->cnic_kwq_cons = bp->cnic_kwq;
13338 bp->cnic_kwq_cons++;
13340 bnx2x_sp_prod_update(bp);
13341 spin_unlock_bh(&bp->spq_lock);
13344 static int bnx2x_cnic_sp_queue(struct net_device *dev,
13345 struct kwqe_16 *kwqes[], u32 count)
13347 struct bnx2x *bp = netdev_priv(dev);
13350 #ifdef BNX2X_STOP_ON_ERROR
13351 if (unlikely(bp->panic)) {
13352 BNX2X_ERR("Can't post to SP queue while panic\n");
13357 if ((bp->recovery_state != BNX2X_RECOVERY_DONE) &&
13358 (bp->recovery_state != BNX2X_RECOVERY_NIC_LOADING)) {
13359 BNX2X_ERR("Handling parity error recovery. Try again later\n");
13363 spin_lock_bh(&bp->spq_lock);
13365 for (i = 0; i < count; i++) {
13366 struct eth_spe *spe = (struct eth_spe *)kwqes[i];
13368 if (bp->cnic_kwq_pending == MAX_SP_DESC_CNT)
13371 *bp->cnic_kwq_prod = *spe;
13373 bp->cnic_kwq_pending++;
13375 DP(BNX2X_MSG_SP, "L5 SPQE %x %x %x:%x pos %d\n",
13376 spe->hdr.conn_and_cmd_data, spe->hdr.type,
13377 spe->data.update_data_addr.hi,
13378 spe->data.update_data_addr.lo,
13379 bp->cnic_kwq_pending);
13381 if (bp->cnic_kwq_prod == bp->cnic_kwq_last)
13382 bp->cnic_kwq_prod = bp->cnic_kwq;
13384 bp->cnic_kwq_prod++;
13387 spin_unlock_bh(&bp->spq_lock);
13389 if (bp->cnic_spq_pending < bp->cnic_eth_dev.max_kwqe_pending)
13390 bnx2x_cnic_sp_post(bp, 0);
13395 static int bnx2x_cnic_ctl_send(struct bnx2x *bp, struct cnic_ctl_info *ctl)
13397 struct cnic_ops *c_ops;
13400 mutex_lock(&bp->cnic_mutex);
13401 c_ops = rcu_dereference_protected(bp->cnic_ops,
13402 lockdep_is_held(&bp->cnic_mutex));
13404 rc = c_ops->cnic_ctl(bp->cnic_data, ctl);
13405 mutex_unlock(&bp->cnic_mutex);
13410 static int bnx2x_cnic_ctl_send_bh(struct bnx2x *bp, struct cnic_ctl_info *ctl)
13412 struct cnic_ops *c_ops;
13416 c_ops = rcu_dereference(bp->cnic_ops);
13418 rc = c_ops->cnic_ctl(bp->cnic_data, ctl);
13425 * for commands that have no data
13427 int bnx2x_cnic_notify(struct bnx2x *bp, int cmd)
13429 struct cnic_ctl_info ctl = {0};
13433 return bnx2x_cnic_ctl_send(bp, &ctl);
13436 static void bnx2x_cnic_cfc_comp(struct bnx2x *bp, int cid, u8 err)
13438 struct cnic_ctl_info ctl = {0};
13440 /* first we tell CNIC and only then we count this as a completion */
13441 ctl.cmd = CNIC_CTL_COMPLETION_CMD;
13442 ctl.data.comp.cid = cid;
13443 ctl.data.comp.error = err;
13445 bnx2x_cnic_ctl_send_bh(bp, &ctl);
13446 bnx2x_cnic_sp_post(bp, 0);
13449 /* Called with netif_addr_lock_bh() taken.
13450 * Sets an rx_mode config for an iSCSI ETH client.
13452 * Completion should be checked outside.
13454 static void bnx2x_set_iscsi_eth_rx_mode(struct bnx2x *bp, bool start)
13456 unsigned long accept_flags = 0, ramrod_flags = 0;
13457 u8 cl_id = bnx2x_cnic_eth_cl_id(bp, BNX2X_ISCSI_ETH_CL_ID_IDX);
13458 int sched_state = BNX2X_FILTER_ISCSI_ETH_STOP_SCHED;
13461 /* Start accepting on iSCSI L2 ring. Accept all multicasts
13462 * because it's the only way for UIO Queue to accept
13463 * multicasts (in non-promiscuous mode only one Queue per
13464 * function will receive multicast packets (leading in our
13467 __set_bit(BNX2X_ACCEPT_UNICAST, &accept_flags);
13468 __set_bit(BNX2X_ACCEPT_ALL_MULTICAST, &accept_flags);
13469 __set_bit(BNX2X_ACCEPT_BROADCAST, &accept_flags);
13470 __set_bit(BNX2X_ACCEPT_ANY_VLAN, &accept_flags);
13472 /* Clear STOP_PENDING bit if START is requested */
13473 clear_bit(BNX2X_FILTER_ISCSI_ETH_STOP_SCHED, &bp->sp_state);
13475 sched_state = BNX2X_FILTER_ISCSI_ETH_START_SCHED;
13477 /* Clear START_PENDING bit if STOP is requested */
13478 clear_bit(BNX2X_FILTER_ISCSI_ETH_START_SCHED, &bp->sp_state);
13480 if (test_bit(BNX2X_FILTER_RX_MODE_PENDING, &bp->sp_state))
13481 set_bit(sched_state, &bp->sp_state);
13483 __set_bit(RAMROD_RX, &ramrod_flags);
13484 bnx2x_set_q_rx_mode(bp, cl_id, 0, accept_flags, 0,
13489 static int bnx2x_drv_ctl(struct net_device *dev, struct drv_ctl_info *ctl)
13491 struct bnx2x *bp = netdev_priv(dev);
13494 switch (ctl->cmd) {
13495 case DRV_CTL_CTXTBL_WR_CMD: {
13496 u32 index = ctl->data.io.offset;
13497 dma_addr_t addr = ctl->data.io.dma_addr;
13499 bnx2x_ilt_wr(bp, index, addr);
13503 case DRV_CTL_RET_L5_SPQ_CREDIT_CMD: {
13504 int count = ctl->data.credit.credit_count;
13506 bnx2x_cnic_sp_post(bp, count);
13510 /* rtnl_lock is held. */
13511 case DRV_CTL_START_L2_CMD: {
13512 struct cnic_eth_dev *cp = &bp->cnic_eth_dev;
13513 unsigned long sp_bits = 0;
13515 /* Configure the iSCSI classification object */
13516 bnx2x_init_mac_obj(bp, &bp->iscsi_l2_mac_obj,
13517 cp->iscsi_l2_client_id,
13518 cp->iscsi_l2_cid, BP_FUNC(bp),
13519 bnx2x_sp(bp, mac_rdata),
13520 bnx2x_sp_mapping(bp, mac_rdata),
13521 BNX2X_FILTER_MAC_PENDING,
13522 &bp->sp_state, BNX2X_OBJ_TYPE_RX,
13525 /* Set iSCSI MAC address */
13526 rc = bnx2x_set_iscsi_eth_mac_addr(bp);
13533 /* Start accepting on iSCSI L2 ring */
13535 netif_addr_lock_bh(dev);
13536 bnx2x_set_iscsi_eth_rx_mode(bp, true);
13537 netif_addr_unlock_bh(dev);
13539 /* bits to wait on */
13540 __set_bit(BNX2X_FILTER_RX_MODE_PENDING, &sp_bits);
13541 __set_bit(BNX2X_FILTER_ISCSI_ETH_START_SCHED, &sp_bits);
13543 if (!bnx2x_wait_sp_comp(bp, sp_bits))
13544 BNX2X_ERR("rx_mode completion timed out!\n");
13549 /* rtnl_lock is held. */
13550 case DRV_CTL_STOP_L2_CMD: {
13551 unsigned long sp_bits = 0;
13553 /* Stop accepting on iSCSI L2 ring */
13554 netif_addr_lock_bh(dev);
13555 bnx2x_set_iscsi_eth_rx_mode(bp, false);
13556 netif_addr_unlock_bh(dev);
13558 /* bits to wait on */
13559 __set_bit(BNX2X_FILTER_RX_MODE_PENDING, &sp_bits);
13560 __set_bit(BNX2X_FILTER_ISCSI_ETH_STOP_SCHED, &sp_bits);
13562 if (!bnx2x_wait_sp_comp(bp, sp_bits))
13563 BNX2X_ERR("rx_mode completion timed out!\n");
13568 /* Unset iSCSI L2 MAC */
13569 rc = bnx2x_del_all_macs(bp, &bp->iscsi_l2_mac_obj,
13570 BNX2X_ISCSI_ETH_MAC, true);
13573 case DRV_CTL_RET_L2_SPQ_CREDIT_CMD: {
13574 int count = ctl->data.credit.credit_count;
13576 smp_mb__before_atomic_inc();
13577 atomic_add(count, &bp->cq_spq_left);
13578 smp_mb__after_atomic_inc();
13581 case DRV_CTL_ULP_REGISTER_CMD: {
13582 int ulp_type = ctl->data.register_data.ulp_type;
13584 if (CHIP_IS_E3(bp)) {
13585 int idx = BP_FW_MB_IDX(bp);
13586 u32 cap = SHMEM2_RD(bp, drv_capabilities_flag[idx]);
13587 int path = BP_PATH(bp);
13588 int port = BP_PORT(bp);
13590 u32 scratch_offset;
13593 /* first write capability to shmem2 */
13594 if (ulp_type == CNIC_ULP_ISCSI)
13595 cap |= DRV_FLAGS_CAPABILITIES_LOADED_ISCSI;
13596 else if (ulp_type == CNIC_ULP_FCOE)
13597 cap |= DRV_FLAGS_CAPABILITIES_LOADED_FCOE;
13598 SHMEM2_WR(bp, drv_capabilities_flag[idx], cap);
13600 if ((ulp_type != CNIC_ULP_FCOE) ||
13601 (!SHMEM2_HAS(bp, ncsi_oem_data_addr)) ||
13602 (!(bp->flags & BC_SUPPORTS_FCOE_FEATURES)))
13605 /* if reached here - should write fcoe capabilities */
13606 scratch_offset = SHMEM2_RD(bp, ncsi_oem_data_addr);
13607 if (!scratch_offset)
13609 scratch_offset += offsetof(struct glob_ncsi_oem_data,
13610 fcoe_features[path][port]);
13611 host_addr = (u32 *) &(ctl->data.register_data.
13613 for (i = 0; i < sizeof(struct fcoe_capabilities);
13615 REG_WR(bp, scratch_offset + i,
13616 *(host_addr + i/4));
13621 case DRV_CTL_ULP_UNREGISTER_CMD: {
13622 int ulp_type = ctl->data.ulp_type;
13624 if (CHIP_IS_E3(bp)) {
13625 int idx = BP_FW_MB_IDX(bp);
13628 cap = SHMEM2_RD(bp, drv_capabilities_flag[idx]);
13629 if (ulp_type == CNIC_ULP_ISCSI)
13630 cap &= ~DRV_FLAGS_CAPABILITIES_LOADED_ISCSI;
13631 else if (ulp_type == CNIC_ULP_FCOE)
13632 cap &= ~DRV_FLAGS_CAPABILITIES_LOADED_FCOE;
13633 SHMEM2_WR(bp, drv_capabilities_flag[idx], cap);
13639 BNX2X_ERR("unknown command %x\n", ctl->cmd);
13646 void bnx2x_setup_cnic_irq_info(struct bnx2x *bp)
13648 struct cnic_eth_dev *cp = &bp->cnic_eth_dev;
13650 if (bp->flags & USING_MSIX_FLAG) {
13651 cp->drv_state |= CNIC_DRV_STATE_USING_MSIX;
13652 cp->irq_arr[0].irq_flags |= CNIC_IRQ_FL_MSIX;
13653 cp->irq_arr[0].vector = bp->msix_table[1].vector;
13655 cp->drv_state &= ~CNIC_DRV_STATE_USING_MSIX;
13656 cp->irq_arr[0].irq_flags &= ~CNIC_IRQ_FL_MSIX;
13658 if (!CHIP_IS_E1x(bp))
13659 cp->irq_arr[0].status_blk = (void *)bp->cnic_sb.e2_sb;
13661 cp->irq_arr[0].status_blk = (void *)bp->cnic_sb.e1x_sb;
13663 cp->irq_arr[0].status_blk_num = bnx2x_cnic_fw_sb_id(bp);
13664 cp->irq_arr[0].status_blk_num2 = bnx2x_cnic_igu_sb_id(bp);
13665 cp->irq_arr[1].status_blk = bp->def_status_blk;
13666 cp->irq_arr[1].status_blk_num = DEF_SB_ID;
13667 cp->irq_arr[1].status_blk_num2 = DEF_SB_IGU_ID;
13672 void bnx2x_setup_cnic_info(struct bnx2x *bp)
13674 struct cnic_eth_dev *cp = &bp->cnic_eth_dev;
13676 cp->ctx_tbl_offset = FUNC_ILT_BASE(BP_FUNC(bp)) +
13677 bnx2x_cid_ilt_lines(bp);
13678 cp->starting_cid = bnx2x_cid_ilt_lines(bp) * ILT_PAGE_CIDS;
13679 cp->fcoe_init_cid = BNX2X_FCOE_ETH_CID(bp);
13680 cp->iscsi_l2_cid = BNX2X_ISCSI_ETH_CID(bp);
13682 DP(NETIF_MSG_IFUP, "BNX2X_1st_NON_L2_ETH_CID(bp) %x, cp->starting_cid %x, cp->fcoe_init_cid %x, cp->iscsi_l2_cid %x\n",
13683 BNX2X_1st_NON_L2_ETH_CID(bp), cp->starting_cid, cp->fcoe_init_cid,
13686 if (NO_ISCSI_OOO(bp))
13687 cp->drv_state |= CNIC_DRV_STATE_NO_ISCSI_OOO;
13690 static int bnx2x_register_cnic(struct net_device *dev, struct cnic_ops *ops,
13693 struct bnx2x *bp = netdev_priv(dev);
13694 struct cnic_eth_dev *cp = &bp->cnic_eth_dev;
13697 DP(NETIF_MSG_IFUP, "Register_cnic called\n");
13700 BNX2X_ERR("NULL ops received\n");
13704 if (!CNIC_SUPPORT(bp)) {
13705 BNX2X_ERR("Can't register CNIC when not supported\n");
13706 return -EOPNOTSUPP;
13709 if (!CNIC_LOADED(bp)) {
13710 rc = bnx2x_load_cnic(bp);
13712 BNX2X_ERR("CNIC-related load failed\n");
13717 bp->cnic_enabled = true;
13719 bp->cnic_kwq = kzalloc(PAGE_SIZE, GFP_KERNEL);
13723 bp->cnic_kwq_cons = bp->cnic_kwq;
13724 bp->cnic_kwq_prod = bp->cnic_kwq;
13725 bp->cnic_kwq_last = bp->cnic_kwq + MAX_SP_DESC_CNT;
13727 bp->cnic_spq_pending = 0;
13728 bp->cnic_kwq_pending = 0;
13730 bp->cnic_data = data;
13733 cp->drv_state |= CNIC_DRV_STATE_REGD;
13734 cp->iro_arr = bp->iro_arr;
13736 bnx2x_setup_cnic_irq_info(bp);
13738 rcu_assign_pointer(bp->cnic_ops, ops);
13743 static int bnx2x_unregister_cnic(struct net_device *dev)
13745 struct bnx2x *bp = netdev_priv(dev);
13746 struct cnic_eth_dev *cp = &bp->cnic_eth_dev;
13748 mutex_lock(&bp->cnic_mutex);
13750 RCU_INIT_POINTER(bp->cnic_ops, NULL);
13751 mutex_unlock(&bp->cnic_mutex);
13753 bp->cnic_enabled = false;
13754 kfree(bp->cnic_kwq);
13755 bp->cnic_kwq = NULL;
13760 struct cnic_eth_dev *bnx2x_cnic_probe(struct net_device *dev)
13762 struct bnx2x *bp = netdev_priv(dev);
13763 struct cnic_eth_dev *cp = &bp->cnic_eth_dev;
13765 /* If both iSCSI and FCoE are disabled - return NULL in
13766 * order to indicate CNIC that it should not try to work
13767 * with this device.
13769 if (NO_ISCSI(bp) && NO_FCOE(bp))
13772 cp->drv_owner = THIS_MODULE;
13773 cp->chip_id = CHIP_ID(bp);
13774 cp->pdev = bp->pdev;
13775 cp->io_base = bp->regview;
13776 cp->io_base2 = bp->doorbells;
13777 cp->max_kwqe_pending = 8;
13778 cp->ctx_blk_size = CDU_ILT_PAGE_SZ;
13779 cp->ctx_tbl_offset = FUNC_ILT_BASE(BP_FUNC(bp)) +
13780 bnx2x_cid_ilt_lines(bp);
13781 cp->ctx_tbl_len = CNIC_ILT_LINES;
13782 cp->starting_cid = bnx2x_cid_ilt_lines(bp) * ILT_PAGE_CIDS;
13783 cp->drv_submit_kwqes_16 = bnx2x_cnic_sp_queue;
13784 cp->drv_ctl = bnx2x_drv_ctl;
13785 cp->drv_register_cnic = bnx2x_register_cnic;
13786 cp->drv_unregister_cnic = bnx2x_unregister_cnic;
13787 cp->fcoe_init_cid = BNX2X_FCOE_ETH_CID(bp);
13788 cp->iscsi_l2_client_id =
13789 bnx2x_cnic_eth_cl_id(bp, BNX2X_ISCSI_ETH_CL_ID_IDX);
13790 cp->iscsi_l2_cid = BNX2X_ISCSI_ETH_CID(bp);
13792 if (NO_ISCSI_OOO(bp))
13793 cp->drv_state |= CNIC_DRV_STATE_NO_ISCSI_OOO;
13796 cp->drv_state |= CNIC_DRV_STATE_NO_ISCSI;
13799 cp->drv_state |= CNIC_DRV_STATE_NO_FCOE;
13802 "page_size %d, tbl_offset %d, tbl_lines %d, starting cid %d\n",
13804 cp->ctx_tbl_offset,
13810 u32 bnx2x_rx_ustorm_prods_offset(struct bnx2x_fastpath *fp)
13812 struct bnx2x *bp = fp->bp;
13813 u32 offset = BAR_USTRORM_INTMEM;
13816 return bnx2x_vf_ustorm_prods_offset(bp, fp);
13817 else if (!CHIP_IS_E1x(bp))
13818 offset += USTORM_RX_PRODS_E2_OFFSET(fp->cl_qzone_id);
13820 offset += USTORM_RX_PRODS_E1X_OFFSET(BP_PORT(bp), fp->cl_id);
13825 /* called only on E1H or E2.
13826 * When pretending to be PF, the pretend value is the function number 0...7
13827 * When pretending to be VF, the pretend val is the PF-num:VF-valid:ABS-VFID
13830 int bnx2x_pretend_func(struct bnx2x *bp, u16 pretend_func_val)
13834 if (CHIP_IS_E1H(bp) && pretend_func_val >= E1H_FUNC_MAX)
13837 /* get my own pretend register */
13838 pretend_reg = bnx2x_get_pretend_reg(bp);
13839 REG_WR(bp, pretend_reg, pretend_func_val);
13840 REG_RD(bp, pretend_reg);