1 /* bnx2x_main.c: QLogic Everest network driver.
3 * Copyright (c) 2007-2013 Broadcom Corporation
4 * Copyright (c) 2014 QLogic Corporation
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation.
11 * Maintained by: Ariel Elior <ariel.elior@qlogic.com>
12 * Written by: Eliezer Tamir
13 * Based on code from Michael Chan's bnx2 driver
14 * UDP CSUM errata workaround by Arik Gendelman
15 * Slowpath and fastpath rework by Vladislav Zolotarov
16 * Statistics and Link management by Yitchak Gertner
20 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
22 #include <linux/module.h>
23 #include <linux/moduleparam.h>
24 #include <linux/kernel.h>
25 #include <linux/device.h> /* for dev_info() */
26 #include <linux/timer.h>
27 #include <linux/errno.h>
28 #include <linux/ioport.h>
29 #include <linux/slab.h>
30 #include <linux/interrupt.h>
31 #include <linux/pci.h>
32 #include <linux/aer.h>
33 #include <linux/init.h>
34 #include <linux/netdevice.h>
35 #include <linux/etherdevice.h>
36 #include <linux/skbuff.h>
37 #include <linux/dma-mapping.h>
38 #include <linux/bitops.h>
39 #include <linux/irq.h>
40 #include <linux/delay.h>
41 #include <asm/byteorder.h>
42 #include <linux/time.h>
43 #include <linux/ethtool.h>
44 #include <linux/mii.h>
45 #include <linux/if_vlan.h>
46 #include <linux/crash_dump.h>
50 #include <net/vxlan.h>
51 #include <net/checksum.h>
52 #include <net/ip6_checksum.h>
53 #include <linux/workqueue.h>
54 #include <linux/crc32.h>
55 #include <linux/crc32c.h>
56 #include <linux/prefetch.h>
57 #include <linux/zlib.h>
59 #include <linux/semaphore.h>
60 #include <linux/stringify.h>
61 #include <linux/vmalloc.h>
64 #include "bnx2x_init.h"
65 #include "bnx2x_init_ops.h"
66 #include "bnx2x_cmn.h"
67 #include "bnx2x_vfpf.h"
68 #include "bnx2x_dcb.h"
70 #include <linux/firmware.h>
71 #include "bnx2x_fw_file_hdr.h"
73 #define FW_FILE_VERSION \
74 __stringify(BCM_5710_FW_MAJOR_VERSION) "." \
75 __stringify(BCM_5710_FW_MINOR_VERSION) "." \
76 __stringify(BCM_5710_FW_REVISION_VERSION) "." \
77 __stringify(BCM_5710_FW_ENGINEERING_VERSION)
78 #define FW_FILE_NAME_E1 "bnx2x/bnx2x-e1-" FW_FILE_VERSION ".fw"
79 #define FW_FILE_NAME_E1H "bnx2x/bnx2x-e1h-" FW_FILE_VERSION ".fw"
80 #define FW_FILE_NAME_E2 "bnx2x/bnx2x-e2-" FW_FILE_VERSION ".fw"
82 /* Time in jiffies before concluding the transmitter is hung */
83 #define TX_TIMEOUT (5*HZ)
85 static char version[] =
86 "QLogic 5771x/578xx 10/20-Gigabit Ethernet Driver "
87 DRV_MODULE_NAME " " DRV_MODULE_VERSION " (" DRV_MODULE_RELDATE ")\n";
89 MODULE_AUTHOR("Eliezer Tamir");
90 MODULE_DESCRIPTION("QLogic "
91 "BCM57710/57711/57711E/"
92 "57712/57712_MF/57800/57800_MF/57810/57810_MF/"
93 "57840/57840_MF Driver");
94 MODULE_LICENSE("GPL");
95 MODULE_VERSION(DRV_MODULE_VERSION);
96 MODULE_FIRMWARE(FW_FILE_NAME_E1);
97 MODULE_FIRMWARE(FW_FILE_NAME_E1H);
98 MODULE_FIRMWARE(FW_FILE_NAME_E2);
100 int bnx2x_num_queues;
101 module_param_named(num_queues, bnx2x_num_queues, int, S_IRUGO);
102 MODULE_PARM_DESC(num_queues,
103 " Set number of queues (default is as a number of CPUs)");
105 static int disable_tpa;
106 module_param(disable_tpa, int, S_IRUGO);
107 MODULE_PARM_DESC(disable_tpa, " Disable the TPA (LRO) feature");
110 module_param(int_mode, int, S_IRUGO);
111 MODULE_PARM_DESC(int_mode, " Force interrupt mode other than MSI-X "
114 static int dropless_fc;
115 module_param(dropless_fc, int, S_IRUGO);
116 MODULE_PARM_DESC(dropless_fc, " Pause on exhausted host ring");
118 static int mrrs = -1;
119 module_param(mrrs, int, S_IRUGO);
120 MODULE_PARM_DESC(mrrs, " Force Max Read Req Size (0..3) (for debug)");
123 module_param(debug, int, S_IRUGO);
124 MODULE_PARM_DESC(debug, " Default debug msglevel");
126 static struct workqueue_struct *bnx2x_wq;
127 struct workqueue_struct *bnx2x_iov_wq;
129 struct bnx2x_mac_vals {
140 enum bnx2x_board_type {
164 /* indexed by board_type, above */
168 [BCM57710] = { "QLogic BCM57710 10 Gigabit PCIe [Everest]" },
169 [BCM57711] = { "QLogic BCM57711 10 Gigabit PCIe" },
170 [BCM57711E] = { "QLogic BCM57711E 10 Gigabit PCIe" },
171 [BCM57712] = { "QLogic BCM57712 10 Gigabit Ethernet" },
172 [BCM57712_MF] = { "QLogic BCM57712 10 Gigabit Ethernet Multi Function" },
173 [BCM57712_VF] = { "QLogic BCM57712 10 Gigabit Ethernet Virtual Function" },
174 [BCM57800] = { "QLogic BCM57800 10 Gigabit Ethernet" },
175 [BCM57800_MF] = { "QLogic BCM57800 10 Gigabit Ethernet Multi Function" },
176 [BCM57800_VF] = { "QLogic BCM57800 10 Gigabit Ethernet Virtual Function" },
177 [BCM57810] = { "QLogic BCM57810 10 Gigabit Ethernet" },
178 [BCM57810_MF] = { "QLogic BCM57810 10 Gigabit Ethernet Multi Function" },
179 [BCM57810_VF] = { "QLogic BCM57810 10 Gigabit Ethernet Virtual Function" },
180 [BCM57840_4_10] = { "QLogic BCM57840 10 Gigabit Ethernet" },
181 [BCM57840_2_20] = { "QLogic BCM57840 20 Gigabit Ethernet" },
182 [BCM57840_MF] = { "QLogic BCM57840 10/20 Gigabit Ethernet Multi Function" },
183 [BCM57840_VF] = { "QLogic BCM57840 10/20 Gigabit Ethernet Virtual Function" },
184 [BCM57811] = { "QLogic BCM57811 10 Gigabit Ethernet" },
185 [BCM57811_MF] = { "QLogic BCM57811 10 Gigabit Ethernet Multi Function" },
186 [BCM57840_O] = { "QLogic BCM57840 10/20 Gigabit Ethernet" },
187 [BCM57840_MFO] = { "QLogic BCM57840 10/20 Gigabit Ethernet Multi Function" },
188 [BCM57811_VF] = { "QLogic BCM57840 10/20 Gigabit Ethernet Virtual Function" }
191 #ifndef PCI_DEVICE_ID_NX2_57710
192 #define PCI_DEVICE_ID_NX2_57710 CHIP_NUM_57710
194 #ifndef PCI_DEVICE_ID_NX2_57711
195 #define PCI_DEVICE_ID_NX2_57711 CHIP_NUM_57711
197 #ifndef PCI_DEVICE_ID_NX2_57711E
198 #define PCI_DEVICE_ID_NX2_57711E CHIP_NUM_57711E
200 #ifndef PCI_DEVICE_ID_NX2_57712
201 #define PCI_DEVICE_ID_NX2_57712 CHIP_NUM_57712
203 #ifndef PCI_DEVICE_ID_NX2_57712_MF
204 #define PCI_DEVICE_ID_NX2_57712_MF CHIP_NUM_57712_MF
206 #ifndef PCI_DEVICE_ID_NX2_57712_VF
207 #define PCI_DEVICE_ID_NX2_57712_VF CHIP_NUM_57712_VF
209 #ifndef PCI_DEVICE_ID_NX2_57800
210 #define PCI_DEVICE_ID_NX2_57800 CHIP_NUM_57800
212 #ifndef PCI_DEVICE_ID_NX2_57800_MF
213 #define PCI_DEVICE_ID_NX2_57800_MF CHIP_NUM_57800_MF
215 #ifndef PCI_DEVICE_ID_NX2_57800_VF
216 #define PCI_DEVICE_ID_NX2_57800_VF CHIP_NUM_57800_VF
218 #ifndef PCI_DEVICE_ID_NX2_57810
219 #define PCI_DEVICE_ID_NX2_57810 CHIP_NUM_57810
221 #ifndef PCI_DEVICE_ID_NX2_57810_MF
222 #define PCI_DEVICE_ID_NX2_57810_MF CHIP_NUM_57810_MF
224 #ifndef PCI_DEVICE_ID_NX2_57840_O
225 #define PCI_DEVICE_ID_NX2_57840_O CHIP_NUM_57840_OBSOLETE
227 #ifndef PCI_DEVICE_ID_NX2_57810_VF
228 #define PCI_DEVICE_ID_NX2_57810_VF CHIP_NUM_57810_VF
230 #ifndef PCI_DEVICE_ID_NX2_57840_4_10
231 #define PCI_DEVICE_ID_NX2_57840_4_10 CHIP_NUM_57840_4_10
233 #ifndef PCI_DEVICE_ID_NX2_57840_2_20
234 #define PCI_DEVICE_ID_NX2_57840_2_20 CHIP_NUM_57840_2_20
236 #ifndef PCI_DEVICE_ID_NX2_57840_MFO
237 #define PCI_DEVICE_ID_NX2_57840_MFO CHIP_NUM_57840_MF_OBSOLETE
239 #ifndef PCI_DEVICE_ID_NX2_57840_MF
240 #define PCI_DEVICE_ID_NX2_57840_MF CHIP_NUM_57840_MF
242 #ifndef PCI_DEVICE_ID_NX2_57840_VF
243 #define PCI_DEVICE_ID_NX2_57840_VF CHIP_NUM_57840_VF
245 #ifndef PCI_DEVICE_ID_NX2_57811
246 #define PCI_DEVICE_ID_NX2_57811 CHIP_NUM_57811
248 #ifndef PCI_DEVICE_ID_NX2_57811_MF
249 #define PCI_DEVICE_ID_NX2_57811_MF CHIP_NUM_57811_MF
251 #ifndef PCI_DEVICE_ID_NX2_57811_VF
252 #define PCI_DEVICE_ID_NX2_57811_VF CHIP_NUM_57811_VF
255 static const struct pci_device_id bnx2x_pci_tbl[] = {
256 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57710), BCM57710 },
257 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57711), BCM57711 },
258 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57711E), BCM57711E },
259 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57712), BCM57712 },
260 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57712_MF), BCM57712_MF },
261 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57712_VF), BCM57712_VF },
262 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57800), BCM57800 },
263 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57800_MF), BCM57800_MF },
264 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57800_VF), BCM57800_VF },
265 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57810), BCM57810 },
266 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57810_MF), BCM57810_MF },
267 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57840_O), BCM57840_O },
268 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57840_4_10), BCM57840_4_10 },
269 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57840_2_20), BCM57840_2_20 },
270 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57810_VF), BCM57810_VF },
271 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57840_MFO), BCM57840_MFO },
272 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57840_MF), BCM57840_MF },
273 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57840_VF), BCM57840_VF },
274 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57811), BCM57811 },
275 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57811_MF), BCM57811_MF },
276 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57811_VF), BCM57811_VF },
280 MODULE_DEVICE_TABLE(pci, bnx2x_pci_tbl);
282 /* Global resources for unloading a previously loaded device */
283 #define BNX2X_PREV_WAIT_NEEDED 1
284 static DEFINE_SEMAPHORE(bnx2x_prev_sem);
285 static LIST_HEAD(bnx2x_prev_list);
287 /* Forward declaration */
288 static struct cnic_eth_dev *bnx2x_cnic_probe(struct net_device *dev);
289 static u32 bnx2x_rx_ustorm_prods_offset(struct bnx2x_fastpath *fp);
290 static int bnx2x_set_storm_rx_mode(struct bnx2x *bp);
292 /****************************************************************************
293 * General service functions
294 ****************************************************************************/
296 static int bnx2x_hwtstamp_ioctl(struct bnx2x *bp, struct ifreq *ifr);
298 static void __storm_memset_dma_mapping(struct bnx2x *bp,
299 u32 addr, dma_addr_t mapping)
301 REG_WR(bp, addr, U64_LO(mapping));
302 REG_WR(bp, addr + 4, U64_HI(mapping));
305 static void storm_memset_spq_addr(struct bnx2x *bp,
306 dma_addr_t mapping, u16 abs_fid)
308 u32 addr = XSEM_REG_FAST_MEMORY +
309 XSTORM_SPQ_PAGE_BASE_OFFSET(abs_fid);
311 __storm_memset_dma_mapping(bp, addr, mapping);
314 static void storm_memset_vf_to_pf(struct bnx2x *bp, u16 abs_fid,
317 REG_WR8(bp, BAR_XSTRORM_INTMEM + XSTORM_VF_TO_PF_OFFSET(abs_fid),
319 REG_WR8(bp, BAR_CSTRORM_INTMEM + CSTORM_VF_TO_PF_OFFSET(abs_fid),
321 REG_WR8(bp, BAR_TSTRORM_INTMEM + TSTORM_VF_TO_PF_OFFSET(abs_fid),
323 REG_WR8(bp, BAR_USTRORM_INTMEM + USTORM_VF_TO_PF_OFFSET(abs_fid),
327 static void storm_memset_func_en(struct bnx2x *bp, u16 abs_fid,
330 REG_WR8(bp, BAR_XSTRORM_INTMEM + XSTORM_FUNC_EN_OFFSET(abs_fid),
332 REG_WR8(bp, BAR_CSTRORM_INTMEM + CSTORM_FUNC_EN_OFFSET(abs_fid),
334 REG_WR8(bp, BAR_TSTRORM_INTMEM + TSTORM_FUNC_EN_OFFSET(abs_fid),
336 REG_WR8(bp, BAR_USTRORM_INTMEM + USTORM_FUNC_EN_OFFSET(abs_fid),
340 static void storm_memset_eq_data(struct bnx2x *bp,
341 struct event_ring_data *eq_data,
344 size_t size = sizeof(struct event_ring_data);
346 u32 addr = BAR_CSTRORM_INTMEM + CSTORM_EVENT_RING_DATA_OFFSET(pfid);
348 __storm_memset_struct(bp, addr, size, (u32 *)eq_data);
351 static void storm_memset_eq_prod(struct bnx2x *bp, u16 eq_prod,
354 u32 addr = BAR_CSTRORM_INTMEM + CSTORM_EVENT_RING_PROD_OFFSET(pfid);
355 REG_WR16(bp, addr, eq_prod);
359 * locking is done by mcp
361 static void bnx2x_reg_wr_ind(struct bnx2x *bp, u32 addr, u32 val)
363 pci_write_config_dword(bp->pdev, PCICFG_GRC_ADDRESS, addr);
364 pci_write_config_dword(bp->pdev, PCICFG_GRC_DATA, val);
365 pci_write_config_dword(bp->pdev, PCICFG_GRC_ADDRESS,
366 PCICFG_VENDOR_ID_OFFSET);
369 static u32 bnx2x_reg_rd_ind(struct bnx2x *bp, u32 addr)
373 pci_write_config_dword(bp->pdev, PCICFG_GRC_ADDRESS, addr);
374 pci_read_config_dword(bp->pdev, PCICFG_GRC_DATA, &val);
375 pci_write_config_dword(bp->pdev, PCICFG_GRC_ADDRESS,
376 PCICFG_VENDOR_ID_OFFSET);
381 #define DMAE_DP_SRC_GRC "grc src_addr [%08x]"
382 #define DMAE_DP_SRC_PCI "pci src_addr [%x:%08x]"
383 #define DMAE_DP_DST_GRC "grc dst_addr [%08x]"
384 #define DMAE_DP_DST_PCI "pci dst_addr [%x:%08x]"
385 #define DMAE_DP_DST_NONE "dst_addr [none]"
387 static void bnx2x_dp_dmae(struct bnx2x *bp,
388 struct dmae_command *dmae, int msglvl)
390 u32 src_type = dmae->opcode & DMAE_COMMAND_SRC;
393 switch (dmae->opcode & DMAE_COMMAND_DST) {
394 case DMAE_CMD_DST_PCI:
395 if (src_type == DMAE_CMD_SRC_PCI)
396 DP(msglvl, "DMAE: opcode 0x%08x\n"
397 "src [%x:%08x], len [%d*4], dst [%x:%08x]\n"
398 "comp_addr [%x:%08x], comp_val 0x%08x\n",
399 dmae->opcode, dmae->src_addr_hi, dmae->src_addr_lo,
400 dmae->len, dmae->dst_addr_hi, dmae->dst_addr_lo,
401 dmae->comp_addr_hi, dmae->comp_addr_lo,
404 DP(msglvl, "DMAE: opcode 0x%08x\n"
405 "src [%08x], len [%d*4], dst [%x:%08x]\n"
406 "comp_addr [%x:%08x], comp_val 0x%08x\n",
407 dmae->opcode, dmae->src_addr_lo >> 2,
408 dmae->len, dmae->dst_addr_hi, dmae->dst_addr_lo,
409 dmae->comp_addr_hi, dmae->comp_addr_lo,
412 case DMAE_CMD_DST_GRC:
413 if (src_type == DMAE_CMD_SRC_PCI)
414 DP(msglvl, "DMAE: opcode 0x%08x\n"
415 "src [%x:%08x], len [%d*4], dst_addr [%08x]\n"
416 "comp_addr [%x:%08x], comp_val 0x%08x\n",
417 dmae->opcode, dmae->src_addr_hi, dmae->src_addr_lo,
418 dmae->len, dmae->dst_addr_lo >> 2,
419 dmae->comp_addr_hi, dmae->comp_addr_lo,
422 DP(msglvl, "DMAE: opcode 0x%08x\n"
423 "src [%08x], len [%d*4], dst [%08x]\n"
424 "comp_addr [%x:%08x], comp_val 0x%08x\n",
425 dmae->opcode, dmae->src_addr_lo >> 2,
426 dmae->len, dmae->dst_addr_lo >> 2,
427 dmae->comp_addr_hi, dmae->comp_addr_lo,
431 if (src_type == DMAE_CMD_SRC_PCI)
432 DP(msglvl, "DMAE: opcode 0x%08x\n"
433 "src_addr [%x:%08x] len [%d * 4] dst_addr [none]\n"
434 "comp_addr [%x:%08x] comp_val 0x%08x\n",
435 dmae->opcode, dmae->src_addr_hi, dmae->src_addr_lo,
436 dmae->len, dmae->comp_addr_hi, dmae->comp_addr_lo,
439 DP(msglvl, "DMAE: opcode 0x%08x\n"
440 "src_addr [%08x] len [%d * 4] dst_addr [none]\n"
441 "comp_addr [%x:%08x] comp_val 0x%08x\n",
442 dmae->opcode, dmae->src_addr_lo >> 2,
443 dmae->len, dmae->comp_addr_hi, dmae->comp_addr_lo,
448 for (i = 0; i < (sizeof(struct dmae_command)/4); i++)
449 DP(msglvl, "DMAE RAW [%02d]: 0x%08x\n",
450 i, *(((u32 *)dmae) + i));
453 /* copy command into DMAE command memory and set DMAE command go */
454 void bnx2x_post_dmae(struct bnx2x *bp, struct dmae_command *dmae, int idx)
459 cmd_offset = (DMAE_REG_CMD_MEM + sizeof(struct dmae_command) * idx);
460 for (i = 0; i < (sizeof(struct dmae_command)/4); i++) {
461 REG_WR(bp, cmd_offset + i*4, *(((u32 *)dmae) + i));
463 REG_WR(bp, dmae_reg_go_c[idx], 1);
466 u32 bnx2x_dmae_opcode_add_comp(u32 opcode, u8 comp_type)
468 return opcode | ((comp_type << DMAE_COMMAND_C_DST_SHIFT) |
472 u32 bnx2x_dmae_opcode_clr_src_reset(u32 opcode)
474 return opcode & ~DMAE_CMD_SRC_RESET;
477 u32 bnx2x_dmae_opcode(struct bnx2x *bp, u8 src_type, u8 dst_type,
478 bool with_comp, u8 comp_type)
482 opcode |= ((src_type << DMAE_COMMAND_SRC_SHIFT) |
483 (dst_type << DMAE_COMMAND_DST_SHIFT));
485 opcode |= (DMAE_CMD_SRC_RESET | DMAE_CMD_DST_RESET);
487 opcode |= (BP_PORT(bp) ? DMAE_CMD_PORT_1 : DMAE_CMD_PORT_0);
488 opcode |= ((BP_VN(bp) << DMAE_CMD_E1HVN_SHIFT) |
489 (BP_VN(bp) << DMAE_COMMAND_DST_VN_SHIFT));
490 opcode |= (DMAE_COM_SET_ERR << DMAE_COMMAND_ERR_POLICY_SHIFT);
493 opcode |= DMAE_CMD_ENDIANITY_B_DW_SWAP;
495 opcode |= DMAE_CMD_ENDIANITY_DW_SWAP;
498 opcode = bnx2x_dmae_opcode_add_comp(opcode, comp_type);
502 void bnx2x_prep_dmae_with_comp(struct bnx2x *bp,
503 struct dmae_command *dmae,
504 u8 src_type, u8 dst_type)
506 memset(dmae, 0, sizeof(struct dmae_command));
509 dmae->opcode = bnx2x_dmae_opcode(bp, src_type, dst_type,
510 true, DMAE_COMP_PCI);
512 /* fill in the completion parameters */
513 dmae->comp_addr_lo = U64_LO(bnx2x_sp_mapping(bp, wb_comp));
514 dmae->comp_addr_hi = U64_HI(bnx2x_sp_mapping(bp, wb_comp));
515 dmae->comp_val = DMAE_COMP_VAL;
518 /* issue a dmae command over the init-channel and wait for completion */
519 int bnx2x_issue_dmae_with_comp(struct bnx2x *bp, struct dmae_command *dmae,
522 int cnt = CHIP_REV_IS_SLOW(bp) ? (400000) : 4000;
525 bnx2x_dp_dmae(bp, dmae, BNX2X_MSG_DMAE);
527 /* Lock the dmae channel. Disable BHs to prevent a dead-lock
528 * as long as this code is called both from syscall context and
529 * from ndo_set_rx_mode() flow that may be called from BH.
532 spin_lock_bh(&bp->dmae_lock);
534 /* reset completion */
537 /* post the command on the channel used for initializations */
538 bnx2x_post_dmae(bp, dmae, INIT_DMAE_C(bp));
540 /* wait for completion */
542 while ((*comp & ~DMAE_PCI_ERR_FLAG) != DMAE_COMP_VAL) {
545 (bp->recovery_state != BNX2X_RECOVERY_DONE &&
546 bp->recovery_state != BNX2X_RECOVERY_NIC_LOADING)) {
547 BNX2X_ERR("DMAE timeout!\n");
554 if (*comp & DMAE_PCI_ERR_FLAG) {
555 BNX2X_ERR("DMAE PCI error!\n");
561 spin_unlock_bh(&bp->dmae_lock);
566 void bnx2x_write_dmae(struct bnx2x *bp, dma_addr_t dma_addr, u32 dst_addr,
570 struct dmae_command dmae;
572 if (!bp->dmae_ready) {
573 u32 *data = bnx2x_sp(bp, wb_data[0]);
576 bnx2x_init_ind_wr(bp, dst_addr, data, len32);
578 bnx2x_init_str_wr(bp, dst_addr, data, len32);
582 /* set opcode and fixed command fields */
583 bnx2x_prep_dmae_with_comp(bp, &dmae, DMAE_SRC_PCI, DMAE_DST_GRC);
585 /* fill in addresses and len */
586 dmae.src_addr_lo = U64_LO(dma_addr);
587 dmae.src_addr_hi = U64_HI(dma_addr);
588 dmae.dst_addr_lo = dst_addr >> 2;
589 dmae.dst_addr_hi = 0;
592 /* issue the command and wait for completion */
593 rc = bnx2x_issue_dmae_with_comp(bp, &dmae, bnx2x_sp(bp, wb_comp));
595 BNX2X_ERR("DMAE returned failure %d\n", rc);
596 #ifdef BNX2X_STOP_ON_ERROR
602 void bnx2x_read_dmae(struct bnx2x *bp, u32 src_addr, u32 len32)
605 struct dmae_command dmae;
607 if (!bp->dmae_ready) {
608 u32 *data = bnx2x_sp(bp, wb_data[0]);
612 for (i = 0; i < len32; i++)
613 data[i] = bnx2x_reg_rd_ind(bp, src_addr + i*4);
615 for (i = 0; i < len32; i++)
616 data[i] = REG_RD(bp, src_addr + i*4);
621 /* set opcode and fixed command fields */
622 bnx2x_prep_dmae_with_comp(bp, &dmae, DMAE_SRC_GRC, DMAE_DST_PCI);
624 /* fill in addresses and len */
625 dmae.src_addr_lo = src_addr >> 2;
626 dmae.src_addr_hi = 0;
627 dmae.dst_addr_lo = U64_LO(bnx2x_sp_mapping(bp, wb_data));
628 dmae.dst_addr_hi = U64_HI(bnx2x_sp_mapping(bp, wb_data));
631 /* issue the command and wait for completion */
632 rc = bnx2x_issue_dmae_with_comp(bp, &dmae, bnx2x_sp(bp, wb_comp));
634 BNX2X_ERR("DMAE returned failure %d\n", rc);
635 #ifdef BNX2X_STOP_ON_ERROR
641 static void bnx2x_write_dmae_phys_len(struct bnx2x *bp, dma_addr_t phys_addr,
644 int dmae_wr_max = DMAE_LEN32_WR_MAX(bp);
647 while (len > dmae_wr_max) {
648 bnx2x_write_dmae(bp, phys_addr + offset,
649 addr + offset, dmae_wr_max);
650 offset += dmae_wr_max * 4;
654 bnx2x_write_dmae(bp, phys_addr + offset, addr + offset, len);
666 #define REGS_IN_ENTRY 4
668 static inline int bnx2x_get_assert_list_entry(struct bnx2x *bp,
674 return XSTORM_ASSERT_LIST_OFFSET(entry);
676 return TSTORM_ASSERT_LIST_OFFSET(entry);
678 return CSTORM_ASSERT_LIST_OFFSET(entry);
680 return USTORM_ASSERT_LIST_OFFSET(entry);
683 BNX2X_ERR("unknown storm\n");
688 static int bnx2x_mc_assert(struct bnx2x *bp)
693 u32 regs[REGS_IN_ENTRY];
694 u32 bar_storm_intmem[STORMS_NUM] = {
700 u32 storm_assert_list_index[STORMS_NUM] = {
701 XSTORM_ASSERT_LIST_INDEX_OFFSET,
702 TSTORM_ASSERT_LIST_INDEX_OFFSET,
703 CSTORM_ASSERT_LIST_INDEX_OFFSET,
704 USTORM_ASSERT_LIST_INDEX_OFFSET
706 char *storms_string[STORMS_NUM] = {
713 for (storm = XSTORM; storm < MAX_STORMS; storm++) {
714 last_idx = REG_RD8(bp, bar_storm_intmem[storm] +
715 storm_assert_list_index[storm]);
717 BNX2X_ERR("%s_ASSERT_LIST_INDEX 0x%x\n",
718 storms_string[storm], last_idx);
720 /* print the asserts */
721 for (i = 0; i < STROM_ASSERT_ARRAY_SIZE; i++) {
722 /* read a single assert entry */
723 for (j = 0; j < REGS_IN_ENTRY; j++)
724 regs[j] = REG_RD(bp, bar_storm_intmem[storm] +
725 bnx2x_get_assert_list_entry(bp,
730 /* log entry if it contains a valid assert */
731 if (regs[0] != COMMON_ASM_INVALID_ASSERT_OPCODE) {
732 BNX2X_ERR("%s_ASSERT_INDEX 0x%x = 0x%08x 0x%08x 0x%08x 0x%08x\n",
733 storms_string[storm], i, regs[3],
734 regs[2], regs[1], regs[0]);
742 BNX2X_ERR("Chip Revision: %s, FW Version: %d_%d_%d\n",
743 CHIP_IS_E1(bp) ? "everest1" :
744 CHIP_IS_E1H(bp) ? "everest1h" :
745 CHIP_IS_E2(bp) ? "everest2" : "everest3",
746 BCM_5710_FW_MAJOR_VERSION,
747 BCM_5710_FW_MINOR_VERSION,
748 BCM_5710_FW_REVISION_VERSION);
753 #define MCPR_TRACE_BUFFER_SIZE (0x800)
754 #define SCRATCH_BUFFER_SIZE(bp) \
755 (CHIP_IS_E1(bp) ? 0x10000 : (CHIP_IS_E1H(bp) ? 0x20000 : 0x28000))
757 void bnx2x_fw_dump_lvl(struct bnx2x *bp, const char *lvl)
763 u32 trace_shmem_base;
765 BNX2X_ERR("NO MCP - can not dump\n");
768 netdev_printk(lvl, bp->dev, "bc %d.%d.%d\n",
769 (bp->common.bc_ver & 0xff0000) >> 16,
770 (bp->common.bc_ver & 0xff00) >> 8,
771 (bp->common.bc_ver & 0xff));
773 val = REG_RD(bp, MCP_REG_MCPR_CPU_PROGRAM_COUNTER);
774 if (val == REG_RD(bp, MCP_REG_MCPR_CPU_PROGRAM_COUNTER))
775 BNX2X_ERR("%s" "MCP PC at 0x%x\n", lvl, val);
777 if (BP_PATH(bp) == 0)
778 trace_shmem_base = bp->common.shmem_base;
780 trace_shmem_base = SHMEM2_RD(bp, other_shmem_base_addr);
783 if (trace_shmem_base < MCPR_SCRATCH_BASE(bp) + MCPR_TRACE_BUFFER_SIZE ||
784 trace_shmem_base >= MCPR_SCRATCH_BASE(bp) +
785 SCRATCH_BUFFER_SIZE(bp)) {
786 BNX2X_ERR("Unable to dump trace buffer (mark %x)\n",
791 addr = trace_shmem_base - MCPR_TRACE_BUFFER_SIZE;
793 /* validate TRCB signature */
794 mark = REG_RD(bp, addr);
795 if (mark != MFW_TRACE_SIGNATURE) {
796 BNX2X_ERR("Trace buffer signature is missing.");
800 /* read cyclic buffer pointer */
802 mark = REG_RD(bp, addr);
803 mark = MCPR_SCRATCH_BASE(bp) + ((mark + 0x3) & ~0x3) - 0x08000000;
804 if (mark >= trace_shmem_base || mark < addr + 4) {
805 BNX2X_ERR("Mark doesn't fall inside Trace Buffer\n");
808 printk("%s" "begin fw dump (mark 0x%x)\n", lvl, mark);
812 /* dump buffer after the mark */
813 for (offset = mark; offset < trace_shmem_base; offset += 0x8*4) {
814 for (word = 0; word < 8; word++)
815 data[word] = htonl(REG_RD(bp, offset + 4*word));
817 pr_cont("%s", (char *)data);
820 /* dump buffer before the mark */
821 for (offset = addr + 4; offset <= mark; offset += 0x8*4) {
822 for (word = 0; word < 8; word++)
823 data[word] = htonl(REG_RD(bp, offset + 4*word));
825 pr_cont("%s", (char *)data);
827 printk("%s" "end of fw dump\n", lvl);
830 static void bnx2x_fw_dump(struct bnx2x *bp)
832 bnx2x_fw_dump_lvl(bp, KERN_ERR);
835 static void bnx2x_hc_int_disable(struct bnx2x *bp)
837 int port = BP_PORT(bp);
838 u32 addr = port ? HC_REG_CONFIG_1 : HC_REG_CONFIG_0;
839 u32 val = REG_RD(bp, addr);
841 /* in E1 we must use only PCI configuration space to disable
842 * MSI/MSIX capability
843 * It's forbidden to disable IGU_PF_CONF_MSI_MSIX_EN in HC block
845 if (CHIP_IS_E1(bp)) {
846 /* Since IGU_PF_CONF_MSI_MSIX_EN still always on
847 * Use mask register to prevent from HC sending interrupts
848 * after we exit the function
850 REG_WR(bp, HC_REG_INT_MASK + port*4, 0);
852 val &= ~(HC_CONFIG_0_REG_SINGLE_ISR_EN_0 |
853 HC_CONFIG_0_REG_INT_LINE_EN_0 |
854 HC_CONFIG_0_REG_ATTN_BIT_EN_0);
856 val &= ~(HC_CONFIG_0_REG_SINGLE_ISR_EN_0 |
857 HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0 |
858 HC_CONFIG_0_REG_INT_LINE_EN_0 |
859 HC_CONFIG_0_REG_ATTN_BIT_EN_0);
862 "write %x to HC %d (addr 0x%x)\n",
865 /* flush all outstanding writes */
868 REG_WR(bp, addr, val);
869 if (REG_RD(bp, addr) != val)
870 BNX2X_ERR("BUG! Proper val not read from IGU!\n");
873 static void bnx2x_igu_int_disable(struct bnx2x *bp)
875 u32 val = REG_RD(bp, IGU_REG_PF_CONFIGURATION);
877 val &= ~(IGU_PF_CONF_MSI_MSIX_EN |
878 IGU_PF_CONF_INT_LINE_EN |
879 IGU_PF_CONF_ATTN_BIT_EN);
881 DP(NETIF_MSG_IFDOWN, "write %x to IGU\n", val);
883 /* flush all outstanding writes */
886 REG_WR(bp, IGU_REG_PF_CONFIGURATION, val);
887 if (REG_RD(bp, IGU_REG_PF_CONFIGURATION) != val)
888 BNX2X_ERR("BUG! Proper val not read from IGU!\n");
891 static void bnx2x_int_disable(struct bnx2x *bp)
893 if (bp->common.int_block == INT_BLOCK_HC)
894 bnx2x_hc_int_disable(bp);
896 bnx2x_igu_int_disable(bp);
899 void bnx2x_panic_dump(struct bnx2x *bp, bool disable_int)
903 struct hc_sp_status_block_data sp_sb_data;
904 int func = BP_FUNC(bp);
905 #ifdef BNX2X_STOP_ON_ERROR
906 u16 start = 0, end = 0;
909 if (IS_PF(bp) && disable_int)
910 bnx2x_int_disable(bp);
912 bp->stats_state = STATS_STATE_DISABLED;
913 bp->eth_stats.unrecoverable_error++;
914 DP(BNX2X_MSG_STATS, "stats_state - DISABLED\n");
916 BNX2X_ERR("begin crash dump -----------------\n");
921 struct host_sp_status_block *def_sb = bp->def_status_blk;
922 int data_size, cstorm_offset;
924 BNX2X_ERR("def_idx(0x%x) def_att_idx(0x%x) attn_state(0x%x) spq_prod_idx(0x%x) next_stats_cnt(0x%x)\n",
925 bp->def_idx, bp->def_att_idx, bp->attn_state,
926 bp->spq_prod_idx, bp->stats_counter);
927 BNX2X_ERR("DSB: attn bits(0x%x) ack(0x%x) id(0x%x) idx(0x%x)\n",
928 def_sb->atten_status_block.attn_bits,
929 def_sb->atten_status_block.attn_bits_ack,
930 def_sb->atten_status_block.status_block_id,
931 def_sb->atten_status_block.attn_bits_index);
933 for (i = 0; i < HC_SP_SB_MAX_INDICES; i++)
935 def_sb->sp_sb.index_values[i],
936 (i == HC_SP_SB_MAX_INDICES - 1) ? ") " : " ");
938 data_size = sizeof(struct hc_sp_status_block_data) /
940 cstorm_offset = CSTORM_SP_STATUS_BLOCK_DATA_OFFSET(func);
941 for (i = 0; i < data_size; i++)
942 *((u32 *)&sp_sb_data + i) =
943 REG_RD(bp, BAR_CSTRORM_INTMEM + cstorm_offset +
946 pr_cont("igu_sb_id(0x%x) igu_seg_id(0x%x) pf_id(0x%x) vnic_id(0x%x) vf_id(0x%x) vf_valid (0x%x) state(0x%x)\n",
947 sp_sb_data.igu_sb_id,
948 sp_sb_data.igu_seg_id,
949 sp_sb_data.p_func.pf_id,
950 sp_sb_data.p_func.vnic_id,
951 sp_sb_data.p_func.vf_id,
952 sp_sb_data.p_func.vf_valid,
956 for_each_eth_queue(bp, i) {
957 struct bnx2x_fastpath *fp = &bp->fp[i];
959 struct hc_status_block_data_e2 sb_data_e2;
960 struct hc_status_block_data_e1x sb_data_e1x;
961 struct hc_status_block_sm *hc_sm_p =
963 sb_data_e1x.common.state_machine :
964 sb_data_e2.common.state_machine;
965 struct hc_index_data *hc_index_p =
967 sb_data_e1x.index_data :
968 sb_data_e2.index_data;
971 struct bnx2x_fp_txdata txdata;
980 BNX2X_ERR("fp%d: rx_bd_prod(0x%x) rx_bd_cons(0x%x) rx_comp_prod(0x%x) rx_comp_cons(0x%x) *rx_cons_sb(0x%x)\n",
981 i, fp->rx_bd_prod, fp->rx_bd_cons,
983 fp->rx_comp_cons, le16_to_cpu(*fp->rx_cons_sb));
984 BNX2X_ERR(" rx_sge_prod(0x%x) last_max_sge(0x%x) fp_hc_idx(0x%x)\n",
985 fp->rx_sge_prod, fp->last_max_sge,
986 le16_to_cpu(fp->fp_hc_idx));
989 for_each_cos_in_tx_queue(fp, cos)
991 if (!fp->txdata_ptr[cos])
994 txdata = *fp->txdata_ptr[cos];
996 if (!txdata.tx_cons_sb)
999 BNX2X_ERR("fp%d: tx_pkt_prod(0x%x) tx_pkt_cons(0x%x) tx_bd_prod(0x%x) tx_bd_cons(0x%x) *tx_cons_sb(0x%x)\n",
1000 i, txdata.tx_pkt_prod,
1001 txdata.tx_pkt_cons, txdata.tx_bd_prod,
1003 le16_to_cpu(*txdata.tx_cons_sb));
1006 loop = CHIP_IS_E1x(bp) ?
1007 HC_SB_MAX_INDICES_E1X : HC_SB_MAX_INDICES_E2;
1014 BNX2X_ERR(" run indexes (");
1015 for (j = 0; j < HC_SB_MAX_SM; j++)
1017 fp->sb_running_index[j],
1018 (j == HC_SB_MAX_SM - 1) ? ")" : " ");
1020 BNX2X_ERR(" indexes (");
1021 for (j = 0; j < loop; j++)
1023 fp->sb_index_values[j],
1024 (j == loop - 1) ? ")" : " ");
1026 /* VF cannot access FW refelection for status block */
1031 data_size = CHIP_IS_E1x(bp) ?
1032 sizeof(struct hc_status_block_data_e1x) :
1033 sizeof(struct hc_status_block_data_e2);
1034 data_size /= sizeof(u32);
1035 sb_data_p = CHIP_IS_E1x(bp) ?
1036 (u32 *)&sb_data_e1x :
1038 /* copy sb data in here */
1039 for (j = 0; j < data_size; j++)
1040 *(sb_data_p + j) = REG_RD(bp, BAR_CSTRORM_INTMEM +
1041 CSTORM_STATUS_BLOCK_DATA_OFFSET(fp->fw_sb_id) +
1044 if (!CHIP_IS_E1x(bp)) {
1045 pr_cont("pf_id(0x%x) vf_id(0x%x) vf_valid(0x%x) vnic_id(0x%x) same_igu_sb_1b(0x%x) state(0x%x)\n",
1046 sb_data_e2.common.p_func.pf_id,
1047 sb_data_e2.common.p_func.vf_id,
1048 sb_data_e2.common.p_func.vf_valid,
1049 sb_data_e2.common.p_func.vnic_id,
1050 sb_data_e2.common.same_igu_sb_1b,
1051 sb_data_e2.common.state);
1053 pr_cont("pf_id(0x%x) vf_id(0x%x) vf_valid(0x%x) vnic_id(0x%x) same_igu_sb_1b(0x%x) state(0x%x)\n",
1054 sb_data_e1x.common.p_func.pf_id,
1055 sb_data_e1x.common.p_func.vf_id,
1056 sb_data_e1x.common.p_func.vf_valid,
1057 sb_data_e1x.common.p_func.vnic_id,
1058 sb_data_e1x.common.same_igu_sb_1b,
1059 sb_data_e1x.common.state);
1063 for (j = 0; j < HC_SB_MAX_SM; j++) {
1064 pr_cont("SM[%d] __flags (0x%x) igu_sb_id (0x%x) igu_seg_id(0x%x) time_to_expire (0x%x) timer_value(0x%x)\n",
1065 j, hc_sm_p[j].__flags,
1066 hc_sm_p[j].igu_sb_id,
1067 hc_sm_p[j].igu_seg_id,
1068 hc_sm_p[j].time_to_expire,
1069 hc_sm_p[j].timer_value);
1073 for (j = 0; j < loop; j++) {
1074 pr_cont("INDEX[%d] flags (0x%x) timeout (0x%x)\n", j,
1075 hc_index_p[j].flags,
1076 hc_index_p[j].timeout);
1080 #ifdef BNX2X_STOP_ON_ERROR
1083 BNX2X_ERR("eq cons %x prod %x\n", bp->eq_cons, bp->eq_prod);
1084 for (i = 0; i < NUM_EQ_DESC; i++) {
1085 u32 *data = (u32 *)&bp->eq_ring[i].message.data;
1087 BNX2X_ERR("event queue [%d]: header: opcode %d, error %d\n",
1088 i, bp->eq_ring[i].message.opcode,
1089 bp->eq_ring[i].message.error);
1090 BNX2X_ERR("data: %x %x %x\n",
1091 data[0], data[1], data[2]);
1097 for_each_valid_rx_queue(bp, i) {
1098 struct bnx2x_fastpath *fp = &bp->fp[i];
1103 if (!fp->rx_cons_sb)
1106 start = RX_BD(le16_to_cpu(*fp->rx_cons_sb) - 10);
1107 end = RX_BD(le16_to_cpu(*fp->rx_cons_sb) + 503);
1108 for (j = start; j != end; j = RX_BD(j + 1)) {
1109 u32 *rx_bd = (u32 *)&fp->rx_desc_ring[j];
1110 struct sw_rx_bd *sw_bd = &fp->rx_buf_ring[j];
1112 BNX2X_ERR("fp%d: rx_bd[%x]=[%x:%x] sw_bd=[%p]\n",
1113 i, j, rx_bd[1], rx_bd[0], sw_bd->data);
1116 start = RX_SGE(fp->rx_sge_prod);
1117 end = RX_SGE(fp->last_max_sge);
1118 for (j = start; j != end; j = RX_SGE(j + 1)) {
1119 u32 *rx_sge = (u32 *)&fp->rx_sge_ring[j];
1120 struct sw_rx_page *sw_page = &fp->rx_page_ring[j];
1122 BNX2X_ERR("fp%d: rx_sge[%x]=[%x:%x] sw_page=[%p]\n",
1123 i, j, rx_sge[1], rx_sge[0], sw_page->page);
1126 start = RCQ_BD(fp->rx_comp_cons - 10);
1127 end = RCQ_BD(fp->rx_comp_cons + 503);
1128 for (j = start; j != end; j = RCQ_BD(j + 1)) {
1129 u32 *cqe = (u32 *)&fp->rx_comp_ring[j];
1131 BNX2X_ERR("fp%d: cqe[%x]=[%x:%x:%x:%x]\n",
1132 i, j, cqe[0], cqe[1], cqe[2], cqe[3]);
1137 for_each_valid_tx_queue(bp, i) {
1138 struct bnx2x_fastpath *fp = &bp->fp[i];
1143 for_each_cos_in_tx_queue(fp, cos) {
1144 struct bnx2x_fp_txdata *txdata = fp->txdata_ptr[cos];
1146 if (!fp->txdata_ptr[cos])
1149 if (!txdata->tx_cons_sb)
1152 start = TX_BD(le16_to_cpu(*txdata->tx_cons_sb) - 10);
1153 end = TX_BD(le16_to_cpu(*txdata->tx_cons_sb) + 245);
1154 for (j = start; j != end; j = TX_BD(j + 1)) {
1155 struct sw_tx_bd *sw_bd =
1156 &txdata->tx_buf_ring[j];
1158 BNX2X_ERR("fp%d: txdata %d, packet[%x]=[%p,%x]\n",
1159 i, cos, j, sw_bd->skb,
1163 start = TX_BD(txdata->tx_bd_cons - 10);
1164 end = TX_BD(txdata->tx_bd_cons + 254);
1165 for (j = start; j != end; j = TX_BD(j + 1)) {
1166 u32 *tx_bd = (u32 *)&txdata->tx_desc_ring[j];
1168 BNX2X_ERR("fp%d: txdata %d, tx_bd[%x]=[%x:%x:%x:%x]\n",
1169 i, cos, j, tx_bd[0], tx_bd[1],
1170 tx_bd[2], tx_bd[3]);
1177 bnx2x_mc_assert(bp);
1179 BNX2X_ERR("end crash dump -----------------\n");
1183 * FLR Support for E2
1185 * bnx2x_pf_flr_clnup() is called during nic_load in the per function HW
1188 #define FLR_WAIT_USEC 10000 /* 10 milliseconds */
1189 #define FLR_WAIT_INTERVAL 50 /* usec */
1190 #define FLR_POLL_CNT (FLR_WAIT_USEC/FLR_WAIT_INTERVAL) /* 200 */
1192 struct pbf_pN_buf_regs {
1199 struct pbf_pN_cmd_regs {
1205 static void bnx2x_pbf_pN_buf_flushed(struct bnx2x *bp,
1206 struct pbf_pN_buf_regs *regs,
1209 u32 init_crd, crd, crd_start, crd_freed, crd_freed_start;
1210 u32 cur_cnt = poll_count;
1212 crd_freed = crd_freed_start = REG_RD(bp, regs->crd_freed);
1213 crd = crd_start = REG_RD(bp, regs->crd);
1214 init_crd = REG_RD(bp, regs->init_crd);
1216 DP(BNX2X_MSG_SP, "INIT CREDIT[%d] : %x\n", regs->pN, init_crd);
1217 DP(BNX2X_MSG_SP, "CREDIT[%d] : s:%x\n", regs->pN, crd);
1218 DP(BNX2X_MSG_SP, "CREDIT_FREED[%d]: s:%x\n", regs->pN, crd_freed);
1220 while ((crd != init_crd) && ((u32)SUB_S32(crd_freed, crd_freed_start) <
1221 (init_crd - crd_start))) {
1223 udelay(FLR_WAIT_INTERVAL);
1224 crd = REG_RD(bp, regs->crd);
1225 crd_freed = REG_RD(bp, regs->crd_freed);
1227 DP(BNX2X_MSG_SP, "PBF tx buffer[%d] timed out\n",
1229 DP(BNX2X_MSG_SP, "CREDIT[%d] : c:%x\n",
1231 DP(BNX2X_MSG_SP, "CREDIT_FREED[%d]: c:%x\n",
1232 regs->pN, crd_freed);
1236 DP(BNX2X_MSG_SP, "Waited %d*%d usec for PBF tx buffer[%d]\n",
1237 poll_count-cur_cnt, FLR_WAIT_INTERVAL, regs->pN);
1240 static void bnx2x_pbf_pN_cmd_flushed(struct bnx2x *bp,
1241 struct pbf_pN_cmd_regs *regs,
1244 u32 occup, to_free, freed, freed_start;
1245 u32 cur_cnt = poll_count;
1247 occup = to_free = REG_RD(bp, regs->lines_occup);
1248 freed = freed_start = REG_RD(bp, regs->lines_freed);
1250 DP(BNX2X_MSG_SP, "OCCUPANCY[%d] : s:%x\n", regs->pN, occup);
1251 DP(BNX2X_MSG_SP, "LINES_FREED[%d] : s:%x\n", regs->pN, freed);
1253 while (occup && ((u32)SUB_S32(freed, freed_start) < to_free)) {
1255 udelay(FLR_WAIT_INTERVAL);
1256 occup = REG_RD(bp, regs->lines_occup);
1257 freed = REG_RD(bp, regs->lines_freed);
1259 DP(BNX2X_MSG_SP, "PBF cmd queue[%d] timed out\n",
1261 DP(BNX2X_MSG_SP, "OCCUPANCY[%d] : s:%x\n",
1263 DP(BNX2X_MSG_SP, "LINES_FREED[%d] : s:%x\n",
1268 DP(BNX2X_MSG_SP, "Waited %d*%d usec for PBF cmd queue[%d]\n",
1269 poll_count-cur_cnt, FLR_WAIT_INTERVAL, regs->pN);
1272 static u32 bnx2x_flr_clnup_reg_poll(struct bnx2x *bp, u32 reg,
1273 u32 expected, u32 poll_count)
1275 u32 cur_cnt = poll_count;
1278 while ((val = REG_RD(bp, reg)) != expected && cur_cnt--)
1279 udelay(FLR_WAIT_INTERVAL);
1284 int bnx2x_flr_clnup_poll_hw_counter(struct bnx2x *bp, u32 reg,
1285 char *msg, u32 poll_cnt)
1287 u32 val = bnx2x_flr_clnup_reg_poll(bp, reg, 0, poll_cnt);
1289 BNX2X_ERR("%s usage count=%d\n", msg, val);
1295 /* Common routines with VF FLR cleanup */
1296 u32 bnx2x_flr_clnup_poll_count(struct bnx2x *bp)
1298 /* adjust polling timeout */
1299 if (CHIP_REV_IS_EMUL(bp))
1300 return FLR_POLL_CNT * 2000;
1302 if (CHIP_REV_IS_FPGA(bp))
1303 return FLR_POLL_CNT * 120;
1305 return FLR_POLL_CNT;
1308 void bnx2x_tx_hw_flushed(struct bnx2x *bp, u32 poll_count)
1310 struct pbf_pN_cmd_regs cmd_regs[] = {
1311 {0, (CHIP_IS_E3B0(bp)) ?
1312 PBF_REG_TQ_OCCUPANCY_Q0 :
1313 PBF_REG_P0_TQ_OCCUPANCY,
1314 (CHIP_IS_E3B0(bp)) ?
1315 PBF_REG_TQ_LINES_FREED_CNT_Q0 :
1316 PBF_REG_P0_TQ_LINES_FREED_CNT},
1317 {1, (CHIP_IS_E3B0(bp)) ?
1318 PBF_REG_TQ_OCCUPANCY_Q1 :
1319 PBF_REG_P1_TQ_OCCUPANCY,
1320 (CHIP_IS_E3B0(bp)) ?
1321 PBF_REG_TQ_LINES_FREED_CNT_Q1 :
1322 PBF_REG_P1_TQ_LINES_FREED_CNT},
1323 {4, (CHIP_IS_E3B0(bp)) ?
1324 PBF_REG_TQ_OCCUPANCY_LB_Q :
1325 PBF_REG_P4_TQ_OCCUPANCY,
1326 (CHIP_IS_E3B0(bp)) ?
1327 PBF_REG_TQ_LINES_FREED_CNT_LB_Q :
1328 PBF_REG_P4_TQ_LINES_FREED_CNT}
1331 struct pbf_pN_buf_regs buf_regs[] = {
1332 {0, (CHIP_IS_E3B0(bp)) ?
1333 PBF_REG_INIT_CRD_Q0 :
1334 PBF_REG_P0_INIT_CRD ,
1335 (CHIP_IS_E3B0(bp)) ?
1338 (CHIP_IS_E3B0(bp)) ?
1339 PBF_REG_INTERNAL_CRD_FREED_CNT_Q0 :
1340 PBF_REG_P0_INTERNAL_CRD_FREED_CNT},
1341 {1, (CHIP_IS_E3B0(bp)) ?
1342 PBF_REG_INIT_CRD_Q1 :
1343 PBF_REG_P1_INIT_CRD,
1344 (CHIP_IS_E3B0(bp)) ?
1347 (CHIP_IS_E3B0(bp)) ?
1348 PBF_REG_INTERNAL_CRD_FREED_CNT_Q1 :
1349 PBF_REG_P1_INTERNAL_CRD_FREED_CNT},
1350 {4, (CHIP_IS_E3B0(bp)) ?
1351 PBF_REG_INIT_CRD_LB_Q :
1352 PBF_REG_P4_INIT_CRD,
1353 (CHIP_IS_E3B0(bp)) ?
1354 PBF_REG_CREDIT_LB_Q :
1356 (CHIP_IS_E3B0(bp)) ?
1357 PBF_REG_INTERNAL_CRD_FREED_CNT_LB_Q :
1358 PBF_REG_P4_INTERNAL_CRD_FREED_CNT},
1363 /* Verify the command queues are flushed P0, P1, P4 */
1364 for (i = 0; i < ARRAY_SIZE(cmd_regs); i++)
1365 bnx2x_pbf_pN_cmd_flushed(bp, &cmd_regs[i], poll_count);
1367 /* Verify the transmission buffers are flushed P0, P1, P4 */
1368 for (i = 0; i < ARRAY_SIZE(buf_regs); i++)
1369 bnx2x_pbf_pN_buf_flushed(bp, &buf_regs[i], poll_count);
1372 #define OP_GEN_PARAM(param) \
1373 (((param) << SDM_OP_GEN_COMP_PARAM_SHIFT) & SDM_OP_GEN_COMP_PARAM)
1375 #define OP_GEN_TYPE(type) \
1376 (((type) << SDM_OP_GEN_COMP_TYPE_SHIFT) & SDM_OP_GEN_COMP_TYPE)
1378 #define OP_GEN_AGG_VECT(index) \
1379 (((index) << SDM_OP_GEN_AGG_VECT_IDX_SHIFT) & SDM_OP_GEN_AGG_VECT_IDX)
1381 int bnx2x_send_final_clnup(struct bnx2x *bp, u8 clnup_func, u32 poll_cnt)
1383 u32 op_gen_command = 0;
1384 u32 comp_addr = BAR_CSTRORM_INTMEM +
1385 CSTORM_FINAL_CLEANUP_COMPLETE_OFFSET(clnup_func);
1388 if (REG_RD(bp, comp_addr)) {
1389 BNX2X_ERR("Cleanup complete was not 0 before sending\n");
1393 op_gen_command |= OP_GEN_PARAM(XSTORM_AGG_INT_FINAL_CLEANUP_INDEX);
1394 op_gen_command |= OP_GEN_TYPE(XSTORM_AGG_INT_FINAL_CLEANUP_COMP_TYPE);
1395 op_gen_command |= OP_GEN_AGG_VECT(clnup_func);
1396 op_gen_command |= 1 << SDM_OP_GEN_AGG_VECT_IDX_VALID_SHIFT;
1398 DP(BNX2X_MSG_SP, "sending FW Final cleanup\n");
1399 REG_WR(bp, XSDM_REG_OPERATION_GEN, op_gen_command);
1401 if (bnx2x_flr_clnup_reg_poll(bp, comp_addr, 1, poll_cnt) != 1) {
1402 BNX2X_ERR("FW final cleanup did not succeed\n");
1403 DP(BNX2X_MSG_SP, "At timeout completion address contained %x\n",
1404 (REG_RD(bp, comp_addr)));
1408 /* Zero completion for next FLR */
1409 REG_WR(bp, comp_addr, 0);
1414 u8 bnx2x_is_pcie_pending(struct pci_dev *dev)
1418 pcie_capability_read_word(dev, PCI_EXP_DEVSTA, &status);
1419 return status & PCI_EXP_DEVSTA_TRPND;
1422 /* PF FLR specific routines
1424 static int bnx2x_poll_hw_usage_counters(struct bnx2x *bp, u32 poll_cnt)
1426 /* wait for CFC PF usage-counter to zero (includes all the VFs) */
1427 if (bnx2x_flr_clnup_poll_hw_counter(bp,
1428 CFC_REG_NUM_LCIDS_INSIDE_PF,
1429 "CFC PF usage counter timed out",
1433 /* Wait for DQ PF usage-counter to zero (until DQ cleanup) */
1434 if (bnx2x_flr_clnup_poll_hw_counter(bp,
1435 DORQ_REG_PF_USAGE_CNT,
1436 "DQ PF usage counter timed out",
1440 /* Wait for QM PF usage-counter to zero (until DQ cleanup) */
1441 if (bnx2x_flr_clnup_poll_hw_counter(bp,
1442 QM_REG_PF_USG_CNT_0 + 4*BP_FUNC(bp),
1443 "QM PF usage counter timed out",
1447 /* Wait for Timer PF usage-counters to zero (until DQ cleanup) */
1448 if (bnx2x_flr_clnup_poll_hw_counter(bp,
1449 TM_REG_LIN0_VNIC_UC + 4*BP_PORT(bp),
1450 "Timers VNIC usage counter timed out",
1453 if (bnx2x_flr_clnup_poll_hw_counter(bp,
1454 TM_REG_LIN0_NUM_SCANS + 4*BP_PORT(bp),
1455 "Timers NUM_SCANS usage counter timed out",
1459 /* Wait DMAE PF usage counter to zero */
1460 if (bnx2x_flr_clnup_poll_hw_counter(bp,
1461 dmae_reg_go_c[INIT_DMAE_C(bp)],
1462 "DMAE command register timed out",
1469 static void bnx2x_hw_enable_status(struct bnx2x *bp)
1473 val = REG_RD(bp, CFC_REG_WEAK_ENABLE_PF);
1474 DP(BNX2X_MSG_SP, "CFC_REG_WEAK_ENABLE_PF is 0x%x\n", val);
1476 val = REG_RD(bp, PBF_REG_DISABLE_PF);
1477 DP(BNX2X_MSG_SP, "PBF_REG_DISABLE_PF is 0x%x\n", val);
1479 val = REG_RD(bp, IGU_REG_PCI_PF_MSI_EN);
1480 DP(BNX2X_MSG_SP, "IGU_REG_PCI_PF_MSI_EN is 0x%x\n", val);
1482 val = REG_RD(bp, IGU_REG_PCI_PF_MSIX_EN);
1483 DP(BNX2X_MSG_SP, "IGU_REG_PCI_PF_MSIX_EN is 0x%x\n", val);
1485 val = REG_RD(bp, IGU_REG_PCI_PF_MSIX_FUNC_MASK);
1486 DP(BNX2X_MSG_SP, "IGU_REG_PCI_PF_MSIX_FUNC_MASK is 0x%x\n", val);
1488 val = REG_RD(bp, PGLUE_B_REG_SHADOW_BME_PF_7_0_CLR);
1489 DP(BNX2X_MSG_SP, "PGLUE_B_REG_SHADOW_BME_PF_7_0_CLR is 0x%x\n", val);
1491 val = REG_RD(bp, PGLUE_B_REG_FLR_REQUEST_PF_7_0_CLR);
1492 DP(BNX2X_MSG_SP, "PGLUE_B_REG_FLR_REQUEST_PF_7_0_CLR is 0x%x\n", val);
1494 val = REG_RD(bp, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER);
1495 DP(BNX2X_MSG_SP, "PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER is 0x%x\n",
1499 static int bnx2x_pf_flr_clnup(struct bnx2x *bp)
1501 u32 poll_cnt = bnx2x_flr_clnup_poll_count(bp);
1503 DP(BNX2X_MSG_SP, "Cleanup after FLR PF[%d]\n", BP_ABS_FUNC(bp));
1505 /* Re-enable PF target read access */
1506 REG_WR(bp, PGLUE_B_REG_INTERNAL_PFID_ENABLE_TARGET_READ, 1);
1508 /* Poll HW usage counters */
1509 DP(BNX2X_MSG_SP, "Polling usage counters\n");
1510 if (bnx2x_poll_hw_usage_counters(bp, poll_cnt))
1513 /* Zero the igu 'trailing edge' and 'leading edge' */
1515 /* Send the FW cleanup command */
1516 if (bnx2x_send_final_clnup(bp, (u8)BP_FUNC(bp), poll_cnt))
1521 /* Verify TX hw is flushed */
1522 bnx2x_tx_hw_flushed(bp, poll_cnt);
1524 /* Wait 100ms (not adjusted according to platform) */
1527 /* Verify no pending pci transactions */
1528 if (bnx2x_is_pcie_pending(bp->pdev))
1529 BNX2X_ERR("PCIE Transactions still pending\n");
1532 bnx2x_hw_enable_status(bp);
1535 * Master enable - Due to WB DMAE writes performed before this
1536 * register is re-initialized as part of the regular function init
1538 REG_WR(bp, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, 1);
1543 static void bnx2x_hc_int_enable(struct bnx2x *bp)
1545 int port = BP_PORT(bp);
1546 u32 addr = port ? HC_REG_CONFIG_1 : HC_REG_CONFIG_0;
1547 u32 val = REG_RD(bp, addr);
1548 bool msix = (bp->flags & USING_MSIX_FLAG) ? true : false;
1549 bool single_msix = (bp->flags & USING_SINGLE_MSIX_FLAG) ? true : false;
1550 bool msi = (bp->flags & USING_MSI_FLAG) ? true : false;
1553 val &= ~(HC_CONFIG_0_REG_SINGLE_ISR_EN_0 |
1554 HC_CONFIG_0_REG_INT_LINE_EN_0);
1555 val |= (HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0 |
1556 HC_CONFIG_0_REG_ATTN_BIT_EN_0);
1558 val |= HC_CONFIG_0_REG_SINGLE_ISR_EN_0;
1560 val &= ~HC_CONFIG_0_REG_INT_LINE_EN_0;
1561 val |= (HC_CONFIG_0_REG_SINGLE_ISR_EN_0 |
1562 HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0 |
1563 HC_CONFIG_0_REG_ATTN_BIT_EN_0);
1565 val |= (HC_CONFIG_0_REG_SINGLE_ISR_EN_0 |
1566 HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0 |
1567 HC_CONFIG_0_REG_INT_LINE_EN_0 |
1568 HC_CONFIG_0_REG_ATTN_BIT_EN_0);
1570 if (!CHIP_IS_E1(bp)) {
1572 "write %x to HC %d (addr 0x%x)\n", val, port, addr);
1574 REG_WR(bp, addr, val);
1576 val &= ~HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0;
1581 REG_WR(bp, HC_REG_INT_MASK + port*4, 0x1FFFF);
1584 "write %x to HC %d (addr 0x%x) mode %s\n", val, port, addr,
1585 (msix ? "MSI-X" : (msi ? "MSI" : "INTx")));
1587 REG_WR(bp, addr, val);
1589 * Ensure that HC_CONFIG is written before leading/trailing edge config
1594 if (!CHIP_IS_E1(bp)) {
1595 /* init leading/trailing edge */
1597 val = (0xee0f | (1 << (BP_VN(bp) + 4)));
1599 /* enable nig and gpio3 attention */
1604 REG_WR(bp, HC_REG_TRAILING_EDGE_0 + port*8, val);
1605 REG_WR(bp, HC_REG_LEADING_EDGE_0 + port*8, val);
1608 /* Make sure that interrupts are indeed enabled from here on */
1612 static void bnx2x_igu_int_enable(struct bnx2x *bp)
1615 bool msix = (bp->flags & USING_MSIX_FLAG) ? true : false;
1616 bool single_msix = (bp->flags & USING_SINGLE_MSIX_FLAG) ? true : false;
1617 bool msi = (bp->flags & USING_MSI_FLAG) ? true : false;
1619 val = REG_RD(bp, IGU_REG_PF_CONFIGURATION);
1622 val &= ~(IGU_PF_CONF_INT_LINE_EN |
1623 IGU_PF_CONF_SINGLE_ISR_EN);
1624 val |= (IGU_PF_CONF_MSI_MSIX_EN |
1625 IGU_PF_CONF_ATTN_BIT_EN);
1628 val |= IGU_PF_CONF_SINGLE_ISR_EN;
1630 val &= ~IGU_PF_CONF_INT_LINE_EN;
1631 val |= (IGU_PF_CONF_MSI_MSIX_EN |
1632 IGU_PF_CONF_ATTN_BIT_EN |
1633 IGU_PF_CONF_SINGLE_ISR_EN);
1635 val &= ~IGU_PF_CONF_MSI_MSIX_EN;
1636 val |= (IGU_PF_CONF_INT_LINE_EN |
1637 IGU_PF_CONF_ATTN_BIT_EN |
1638 IGU_PF_CONF_SINGLE_ISR_EN);
1641 /* Clean previous status - need to configure igu prior to ack*/
1642 if ((!msix) || single_msix) {
1643 REG_WR(bp, IGU_REG_PF_CONFIGURATION, val);
1647 val |= IGU_PF_CONF_FUNC_EN;
1649 DP(NETIF_MSG_IFUP, "write 0x%x to IGU mode %s\n",
1650 val, (msix ? "MSI-X" : (msi ? "MSI" : "INTx")));
1652 REG_WR(bp, IGU_REG_PF_CONFIGURATION, val);
1654 if (val & IGU_PF_CONF_INT_LINE_EN)
1655 pci_intx(bp->pdev, true);
1659 /* init leading/trailing edge */
1661 val = (0xee0f | (1 << (BP_VN(bp) + 4)));
1663 /* enable nig and gpio3 attention */
1668 REG_WR(bp, IGU_REG_TRAILING_EDGE_LATCH, val);
1669 REG_WR(bp, IGU_REG_LEADING_EDGE_LATCH, val);
1671 /* Make sure that interrupts are indeed enabled from here on */
1675 void bnx2x_int_enable(struct bnx2x *bp)
1677 if (bp->common.int_block == INT_BLOCK_HC)
1678 bnx2x_hc_int_enable(bp);
1680 bnx2x_igu_int_enable(bp);
1683 void bnx2x_int_disable_sync(struct bnx2x *bp, int disable_hw)
1685 int msix = (bp->flags & USING_MSIX_FLAG) ? 1 : 0;
1689 /* prevent the HW from sending interrupts */
1690 bnx2x_int_disable(bp);
1692 /* make sure all ISRs are done */
1694 synchronize_irq(bp->msix_table[0].vector);
1696 if (CNIC_SUPPORT(bp))
1698 for_each_eth_queue(bp, i)
1699 synchronize_irq(bp->msix_table[offset++].vector);
1701 synchronize_irq(bp->pdev->irq);
1703 /* make sure sp_task is not running */
1704 cancel_delayed_work(&bp->sp_task);
1705 cancel_delayed_work(&bp->period_task);
1706 flush_workqueue(bnx2x_wq);
1712 * General service functions
1715 /* Return true if succeeded to acquire the lock */
1716 static bool bnx2x_trylock_hw_lock(struct bnx2x *bp, u32 resource)
1719 u32 resource_bit = (1 << resource);
1720 int func = BP_FUNC(bp);
1721 u32 hw_lock_control_reg;
1723 DP(NETIF_MSG_HW | NETIF_MSG_IFUP,
1724 "Trying to take a lock on resource %d\n", resource);
1726 /* Validating that the resource is within range */
1727 if (resource > HW_LOCK_MAX_RESOURCE_VALUE) {
1728 DP(NETIF_MSG_HW | NETIF_MSG_IFUP,
1729 "resource(0x%x) > HW_LOCK_MAX_RESOURCE_VALUE(0x%x)\n",
1730 resource, HW_LOCK_MAX_RESOURCE_VALUE);
1735 hw_lock_control_reg = (MISC_REG_DRIVER_CONTROL_1 + func*8);
1737 hw_lock_control_reg =
1738 (MISC_REG_DRIVER_CONTROL_7 + (func - 6)*8);
1740 /* Try to acquire the lock */
1741 REG_WR(bp, hw_lock_control_reg + 4, resource_bit);
1742 lock_status = REG_RD(bp, hw_lock_control_reg);
1743 if (lock_status & resource_bit)
1746 DP(NETIF_MSG_HW | NETIF_MSG_IFUP,
1747 "Failed to get a lock on resource %d\n", resource);
1752 * bnx2x_get_leader_lock_resource - get the recovery leader resource id
1754 * @bp: driver handle
1756 * Returns the recovery leader resource id according to the engine this function
1757 * belongs to. Currently only only 2 engines is supported.
1759 static int bnx2x_get_leader_lock_resource(struct bnx2x *bp)
1762 return HW_LOCK_RESOURCE_RECOVERY_LEADER_1;
1764 return HW_LOCK_RESOURCE_RECOVERY_LEADER_0;
1768 * bnx2x_trylock_leader_lock- try to acquire a leader lock.
1770 * @bp: driver handle
1772 * Tries to acquire a leader lock for current engine.
1774 static bool bnx2x_trylock_leader_lock(struct bnx2x *bp)
1776 return bnx2x_trylock_hw_lock(bp, bnx2x_get_leader_lock_resource(bp));
1779 static void bnx2x_cnic_cfc_comp(struct bnx2x *bp, int cid, u8 err);
1781 /* schedule the sp task and mark that interrupt occurred (runs from ISR) */
1782 static int bnx2x_schedule_sp_task(struct bnx2x *bp)
1784 /* Set the interrupt occurred bit for the sp-task to recognize it
1785 * must ack the interrupt and transition according to the IGU
1788 atomic_set(&bp->interrupt_occurred, 1);
1790 /* The sp_task must execute only after this bit
1791 * is set, otherwise we will get out of sync and miss all
1792 * further interrupts. Hence, the barrier.
1796 /* schedule sp_task to workqueue */
1797 return queue_delayed_work(bnx2x_wq, &bp->sp_task, 0);
1800 void bnx2x_sp_event(struct bnx2x_fastpath *fp, union eth_rx_cqe *rr_cqe)
1802 struct bnx2x *bp = fp->bp;
1803 int cid = SW_CID(rr_cqe->ramrod_cqe.conn_and_cmd_data);
1804 int command = CQE_CMD(rr_cqe->ramrod_cqe.conn_and_cmd_data);
1805 enum bnx2x_queue_cmd drv_cmd = BNX2X_Q_CMD_MAX;
1806 struct bnx2x_queue_sp_obj *q_obj = &bnx2x_sp_obj(bp, fp).q_obj;
1809 "fp %d cid %d got ramrod #%d state is %x type is %d\n",
1810 fp->index, cid, command, bp->state,
1811 rr_cqe->ramrod_cqe.ramrod_type);
1813 /* If cid is within VF range, replace the slowpath object with the
1814 * one corresponding to this VF
1816 if (cid >= BNX2X_FIRST_VF_CID &&
1817 cid < BNX2X_FIRST_VF_CID + BNX2X_VF_CIDS)
1818 bnx2x_iov_set_queue_sp_obj(bp, cid, &q_obj);
1821 case (RAMROD_CMD_ID_ETH_CLIENT_UPDATE):
1822 DP(BNX2X_MSG_SP, "got UPDATE ramrod. CID %d\n", cid);
1823 drv_cmd = BNX2X_Q_CMD_UPDATE;
1826 case (RAMROD_CMD_ID_ETH_CLIENT_SETUP):
1827 DP(BNX2X_MSG_SP, "got MULTI[%d] setup ramrod\n", cid);
1828 drv_cmd = BNX2X_Q_CMD_SETUP;
1831 case (RAMROD_CMD_ID_ETH_TX_QUEUE_SETUP):
1832 DP(BNX2X_MSG_SP, "got MULTI[%d] tx-only setup ramrod\n", cid);
1833 drv_cmd = BNX2X_Q_CMD_SETUP_TX_ONLY;
1836 case (RAMROD_CMD_ID_ETH_HALT):
1837 DP(BNX2X_MSG_SP, "got MULTI[%d] halt ramrod\n", cid);
1838 drv_cmd = BNX2X_Q_CMD_HALT;
1841 case (RAMROD_CMD_ID_ETH_TERMINATE):
1842 DP(BNX2X_MSG_SP, "got MULTI[%d] terminate ramrod\n", cid);
1843 drv_cmd = BNX2X_Q_CMD_TERMINATE;
1846 case (RAMROD_CMD_ID_ETH_EMPTY):
1847 DP(BNX2X_MSG_SP, "got MULTI[%d] empty ramrod\n", cid);
1848 drv_cmd = BNX2X_Q_CMD_EMPTY;
1851 case (RAMROD_CMD_ID_ETH_TPA_UPDATE):
1852 DP(BNX2X_MSG_SP, "got tpa update ramrod CID=%d\n", cid);
1853 drv_cmd = BNX2X_Q_CMD_UPDATE_TPA;
1857 BNX2X_ERR("unexpected MC reply (%d) on fp[%d]\n",
1858 command, fp->index);
1862 if ((drv_cmd != BNX2X_Q_CMD_MAX) &&
1863 q_obj->complete_cmd(bp, q_obj, drv_cmd))
1864 /* q_obj->complete_cmd() failure means that this was
1865 * an unexpected completion.
1867 * In this case we don't want to increase the bp->spq_left
1868 * because apparently we haven't sent this command the first
1871 #ifdef BNX2X_STOP_ON_ERROR
1877 smp_mb__before_atomic();
1878 atomic_inc(&bp->cq_spq_left);
1879 /* push the change in bp->spq_left and towards the memory */
1880 smp_mb__after_atomic();
1882 DP(BNX2X_MSG_SP, "bp->cq_spq_left %x\n", atomic_read(&bp->cq_spq_left));
1884 if ((drv_cmd == BNX2X_Q_CMD_UPDATE) && (IS_FCOE_FP(fp)) &&
1885 (!!test_bit(BNX2X_AFEX_FCOE_Q_UPDATE_PENDING, &bp->sp_state))) {
1886 /* if Q update ramrod is completed for last Q in AFEX vif set
1887 * flow, then ACK MCP at the end
1889 * mark pending ACK to MCP bit.
1890 * prevent case that both bits are cleared.
1891 * At the end of load/unload driver checks that
1892 * sp_state is cleared, and this order prevents
1895 smp_mb__before_atomic();
1896 set_bit(BNX2X_AFEX_PENDING_VIFSET_MCP_ACK, &bp->sp_state);
1898 clear_bit(BNX2X_AFEX_FCOE_Q_UPDATE_PENDING, &bp->sp_state);
1899 smp_mb__after_atomic();
1901 /* schedule the sp task as mcp ack is required */
1902 bnx2x_schedule_sp_task(bp);
1908 irqreturn_t bnx2x_interrupt(int irq, void *dev_instance)
1910 struct bnx2x *bp = netdev_priv(dev_instance);
1911 u16 status = bnx2x_ack_int(bp);
1916 /* Return here if interrupt is shared and it's not for us */
1917 if (unlikely(status == 0)) {
1918 DP(NETIF_MSG_INTR, "not our interrupt!\n");
1921 DP(NETIF_MSG_INTR, "got an interrupt status 0x%x\n", status);
1923 #ifdef BNX2X_STOP_ON_ERROR
1924 if (unlikely(bp->panic))
1928 for_each_eth_queue(bp, i) {
1929 struct bnx2x_fastpath *fp = &bp->fp[i];
1931 mask = 0x2 << (fp->index + CNIC_SUPPORT(bp));
1932 if (status & mask) {
1933 /* Handle Rx or Tx according to SB id */
1934 for_each_cos_in_tx_queue(fp, cos)
1935 prefetch(fp->txdata_ptr[cos]->tx_cons_sb);
1936 prefetch(&fp->sb_running_index[SM_RX_ID]);
1937 napi_schedule_irqoff(&bnx2x_fp(bp, fp->index, napi));
1942 if (CNIC_SUPPORT(bp)) {
1944 if (status & (mask | 0x1)) {
1945 struct cnic_ops *c_ops = NULL;
1948 c_ops = rcu_dereference(bp->cnic_ops);
1949 if (c_ops && (bp->cnic_eth_dev.drv_state &
1950 CNIC_DRV_STATE_HANDLES_IRQ))
1951 c_ops->cnic_handler(bp->cnic_data, NULL);
1958 if (unlikely(status & 0x1)) {
1960 /* schedule sp task to perform default status block work, ack
1961 * attentions and enable interrupts.
1963 bnx2x_schedule_sp_task(bp);
1970 if (unlikely(status))
1971 DP(NETIF_MSG_INTR, "got an unknown interrupt! (status 0x%x)\n",
1980 * General service functions
1983 int bnx2x_acquire_hw_lock(struct bnx2x *bp, u32 resource)
1986 u32 resource_bit = (1 << resource);
1987 int func = BP_FUNC(bp);
1988 u32 hw_lock_control_reg;
1991 /* Validating that the resource is within range */
1992 if (resource > HW_LOCK_MAX_RESOURCE_VALUE) {
1993 BNX2X_ERR("resource(0x%x) > HW_LOCK_MAX_RESOURCE_VALUE(0x%x)\n",
1994 resource, HW_LOCK_MAX_RESOURCE_VALUE);
1999 hw_lock_control_reg = (MISC_REG_DRIVER_CONTROL_1 + func*8);
2001 hw_lock_control_reg =
2002 (MISC_REG_DRIVER_CONTROL_7 + (func - 6)*8);
2005 /* Validating that the resource is not already taken */
2006 lock_status = REG_RD(bp, hw_lock_control_reg);
2007 if (lock_status & resource_bit) {
2008 BNX2X_ERR("lock_status 0x%x resource_bit 0x%x\n",
2009 lock_status, resource_bit);
2013 /* Try for 5 second every 5ms */
2014 for (cnt = 0; cnt < 1000; cnt++) {
2015 /* Try to acquire the lock */
2016 REG_WR(bp, hw_lock_control_reg + 4, resource_bit);
2017 lock_status = REG_RD(bp, hw_lock_control_reg);
2018 if (lock_status & resource_bit)
2021 usleep_range(5000, 10000);
2023 BNX2X_ERR("Timeout\n");
2027 int bnx2x_release_leader_lock(struct bnx2x *bp)
2029 return bnx2x_release_hw_lock(bp, bnx2x_get_leader_lock_resource(bp));
2032 int bnx2x_release_hw_lock(struct bnx2x *bp, u32 resource)
2035 u32 resource_bit = (1 << resource);
2036 int func = BP_FUNC(bp);
2037 u32 hw_lock_control_reg;
2039 /* Validating that the resource is within range */
2040 if (resource > HW_LOCK_MAX_RESOURCE_VALUE) {
2041 BNX2X_ERR("resource(0x%x) > HW_LOCK_MAX_RESOURCE_VALUE(0x%x)\n",
2042 resource, HW_LOCK_MAX_RESOURCE_VALUE);
2047 hw_lock_control_reg = (MISC_REG_DRIVER_CONTROL_1 + func*8);
2049 hw_lock_control_reg =
2050 (MISC_REG_DRIVER_CONTROL_7 + (func - 6)*8);
2053 /* Validating that the resource is currently taken */
2054 lock_status = REG_RD(bp, hw_lock_control_reg);
2055 if (!(lock_status & resource_bit)) {
2056 BNX2X_ERR("lock_status 0x%x resource_bit 0x%x. Unlock was called but lock wasn't taken!\n",
2057 lock_status, resource_bit);
2061 REG_WR(bp, hw_lock_control_reg, resource_bit);
2065 int bnx2x_get_gpio(struct bnx2x *bp, int gpio_num, u8 port)
2067 /* The GPIO should be swapped if swap register is set and active */
2068 int gpio_port = (REG_RD(bp, NIG_REG_PORT_SWAP) &&
2069 REG_RD(bp, NIG_REG_STRAP_OVERRIDE)) ^ port;
2070 int gpio_shift = gpio_num +
2071 (gpio_port ? MISC_REGISTERS_GPIO_PORT_SHIFT : 0);
2072 u32 gpio_mask = (1 << gpio_shift);
2076 if (gpio_num > MISC_REGISTERS_GPIO_3) {
2077 BNX2X_ERR("Invalid GPIO %d\n", gpio_num);
2081 /* read GPIO value */
2082 gpio_reg = REG_RD(bp, MISC_REG_GPIO);
2084 /* get the requested pin value */
2085 if ((gpio_reg & gpio_mask) == gpio_mask)
2093 int bnx2x_set_gpio(struct bnx2x *bp, int gpio_num, u32 mode, u8 port)
2095 /* The GPIO should be swapped if swap register is set and active */
2096 int gpio_port = (REG_RD(bp, NIG_REG_PORT_SWAP) &&
2097 REG_RD(bp, NIG_REG_STRAP_OVERRIDE)) ^ port;
2098 int gpio_shift = gpio_num +
2099 (gpio_port ? MISC_REGISTERS_GPIO_PORT_SHIFT : 0);
2100 u32 gpio_mask = (1 << gpio_shift);
2103 if (gpio_num > MISC_REGISTERS_GPIO_3) {
2104 BNX2X_ERR("Invalid GPIO %d\n", gpio_num);
2108 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_GPIO);
2109 /* read GPIO and mask except the float bits */
2110 gpio_reg = (REG_RD(bp, MISC_REG_GPIO) & MISC_REGISTERS_GPIO_FLOAT);
2113 case MISC_REGISTERS_GPIO_OUTPUT_LOW:
2115 "Set GPIO %d (shift %d) -> output low\n",
2116 gpio_num, gpio_shift);
2117 /* clear FLOAT and set CLR */
2118 gpio_reg &= ~(gpio_mask << MISC_REGISTERS_GPIO_FLOAT_POS);
2119 gpio_reg |= (gpio_mask << MISC_REGISTERS_GPIO_CLR_POS);
2122 case MISC_REGISTERS_GPIO_OUTPUT_HIGH:
2124 "Set GPIO %d (shift %d) -> output high\n",
2125 gpio_num, gpio_shift);
2126 /* clear FLOAT and set SET */
2127 gpio_reg &= ~(gpio_mask << MISC_REGISTERS_GPIO_FLOAT_POS);
2128 gpio_reg |= (gpio_mask << MISC_REGISTERS_GPIO_SET_POS);
2131 case MISC_REGISTERS_GPIO_INPUT_HI_Z:
2133 "Set GPIO %d (shift %d) -> input\n",
2134 gpio_num, gpio_shift);
2136 gpio_reg |= (gpio_mask << MISC_REGISTERS_GPIO_FLOAT_POS);
2143 REG_WR(bp, MISC_REG_GPIO, gpio_reg);
2144 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_GPIO);
2149 int bnx2x_set_mult_gpio(struct bnx2x *bp, u8 pins, u32 mode)
2154 /* Any port swapping should be handled by caller. */
2156 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_GPIO);
2157 /* read GPIO and mask except the float bits */
2158 gpio_reg = REG_RD(bp, MISC_REG_GPIO);
2159 gpio_reg &= ~(pins << MISC_REGISTERS_GPIO_FLOAT_POS);
2160 gpio_reg &= ~(pins << MISC_REGISTERS_GPIO_CLR_POS);
2161 gpio_reg &= ~(pins << MISC_REGISTERS_GPIO_SET_POS);
2164 case MISC_REGISTERS_GPIO_OUTPUT_LOW:
2165 DP(NETIF_MSG_LINK, "Set GPIO 0x%x -> output low\n", pins);
2167 gpio_reg |= (pins << MISC_REGISTERS_GPIO_CLR_POS);
2170 case MISC_REGISTERS_GPIO_OUTPUT_HIGH:
2171 DP(NETIF_MSG_LINK, "Set GPIO 0x%x -> output high\n", pins);
2173 gpio_reg |= (pins << MISC_REGISTERS_GPIO_SET_POS);
2176 case MISC_REGISTERS_GPIO_INPUT_HI_Z:
2177 DP(NETIF_MSG_LINK, "Set GPIO 0x%x -> input\n", pins);
2179 gpio_reg |= (pins << MISC_REGISTERS_GPIO_FLOAT_POS);
2183 BNX2X_ERR("Invalid GPIO mode assignment %d\n", mode);
2189 REG_WR(bp, MISC_REG_GPIO, gpio_reg);
2191 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_GPIO);
2196 int bnx2x_set_gpio_int(struct bnx2x *bp, int gpio_num, u32 mode, u8 port)
2198 /* The GPIO should be swapped if swap register is set and active */
2199 int gpio_port = (REG_RD(bp, NIG_REG_PORT_SWAP) &&
2200 REG_RD(bp, NIG_REG_STRAP_OVERRIDE)) ^ port;
2201 int gpio_shift = gpio_num +
2202 (gpio_port ? MISC_REGISTERS_GPIO_PORT_SHIFT : 0);
2203 u32 gpio_mask = (1 << gpio_shift);
2206 if (gpio_num > MISC_REGISTERS_GPIO_3) {
2207 BNX2X_ERR("Invalid GPIO %d\n", gpio_num);
2211 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_GPIO);
2213 gpio_reg = REG_RD(bp, MISC_REG_GPIO_INT);
2216 case MISC_REGISTERS_GPIO_INT_OUTPUT_CLR:
2218 "Clear GPIO INT %d (shift %d) -> output low\n",
2219 gpio_num, gpio_shift);
2220 /* clear SET and set CLR */
2221 gpio_reg &= ~(gpio_mask << MISC_REGISTERS_GPIO_INT_SET_POS);
2222 gpio_reg |= (gpio_mask << MISC_REGISTERS_GPIO_INT_CLR_POS);
2225 case MISC_REGISTERS_GPIO_INT_OUTPUT_SET:
2227 "Set GPIO INT %d (shift %d) -> output high\n",
2228 gpio_num, gpio_shift);
2229 /* clear CLR and set SET */
2230 gpio_reg &= ~(gpio_mask << MISC_REGISTERS_GPIO_INT_CLR_POS);
2231 gpio_reg |= (gpio_mask << MISC_REGISTERS_GPIO_INT_SET_POS);
2238 REG_WR(bp, MISC_REG_GPIO_INT, gpio_reg);
2239 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_GPIO);
2244 static int bnx2x_set_spio(struct bnx2x *bp, int spio, u32 mode)
2248 /* Only 2 SPIOs are configurable */
2249 if ((spio != MISC_SPIO_SPIO4) && (spio != MISC_SPIO_SPIO5)) {
2250 BNX2X_ERR("Invalid SPIO 0x%x\n", spio);
2254 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_SPIO);
2255 /* read SPIO and mask except the float bits */
2256 spio_reg = (REG_RD(bp, MISC_REG_SPIO) & MISC_SPIO_FLOAT);
2259 case MISC_SPIO_OUTPUT_LOW:
2260 DP(NETIF_MSG_HW, "Set SPIO 0x%x -> output low\n", spio);
2261 /* clear FLOAT and set CLR */
2262 spio_reg &= ~(spio << MISC_SPIO_FLOAT_POS);
2263 spio_reg |= (spio << MISC_SPIO_CLR_POS);
2266 case MISC_SPIO_OUTPUT_HIGH:
2267 DP(NETIF_MSG_HW, "Set SPIO 0x%x -> output high\n", spio);
2268 /* clear FLOAT and set SET */
2269 spio_reg &= ~(spio << MISC_SPIO_FLOAT_POS);
2270 spio_reg |= (spio << MISC_SPIO_SET_POS);
2273 case MISC_SPIO_INPUT_HI_Z:
2274 DP(NETIF_MSG_HW, "Set SPIO 0x%x -> input\n", spio);
2276 spio_reg |= (spio << MISC_SPIO_FLOAT_POS);
2283 REG_WR(bp, MISC_REG_SPIO, spio_reg);
2284 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_SPIO);
2289 void bnx2x_calc_fc_adv(struct bnx2x *bp)
2291 u8 cfg_idx = bnx2x_get_link_cfg_idx(bp);
2293 bp->port.advertising[cfg_idx] &= ~(ADVERTISED_Asym_Pause |
2295 switch (bp->link_vars.ieee_fc &
2296 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_MASK) {
2297 case MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH:
2298 bp->port.advertising[cfg_idx] |= (ADVERTISED_Asym_Pause |
2302 case MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC:
2303 bp->port.advertising[cfg_idx] |= ADVERTISED_Asym_Pause;
2311 static void bnx2x_set_requested_fc(struct bnx2x *bp)
2313 /* Initialize link parameters structure variables
2314 * It is recommended to turn off RX FC for jumbo frames
2315 * for better performance
2317 if (CHIP_IS_E1x(bp) && (bp->dev->mtu > 5000))
2318 bp->link_params.req_fc_auto_adv = BNX2X_FLOW_CTRL_TX;
2320 bp->link_params.req_fc_auto_adv = BNX2X_FLOW_CTRL_BOTH;
2323 static void bnx2x_init_dropless_fc(struct bnx2x *bp)
2325 u32 pause_enabled = 0;
2327 if (!CHIP_IS_E1(bp) && bp->dropless_fc && bp->link_vars.link_up) {
2328 if (bp->link_vars.flow_ctrl & BNX2X_FLOW_CTRL_TX)
2331 REG_WR(bp, BAR_USTRORM_INTMEM +
2332 USTORM_ETH_PAUSE_ENABLED_OFFSET(BP_PORT(bp)),
2336 DP(NETIF_MSG_IFUP | NETIF_MSG_LINK, "dropless_fc is %s\n",
2337 pause_enabled ? "enabled" : "disabled");
2340 int bnx2x_initial_phy_init(struct bnx2x *bp, int load_mode)
2342 int rc, cfx_idx = bnx2x_get_link_cfg_idx(bp);
2343 u16 req_line_speed = bp->link_params.req_line_speed[cfx_idx];
2345 if (!BP_NOMCP(bp)) {
2346 bnx2x_set_requested_fc(bp);
2347 bnx2x_acquire_phy_lock(bp);
2349 if (load_mode == LOAD_DIAG) {
2350 struct link_params *lp = &bp->link_params;
2351 lp->loopback_mode = LOOPBACK_XGXS;
2352 /* Prefer doing PHY loopback at highest speed */
2353 if (lp->req_line_speed[cfx_idx] < SPEED_20000) {
2354 if (lp->speed_cap_mask[cfx_idx] &
2355 PORT_HW_CFG_SPEED_CAPABILITY_D0_20G)
2356 lp->req_line_speed[cfx_idx] =
2358 else if (lp->speed_cap_mask[cfx_idx] &
2359 PORT_HW_CFG_SPEED_CAPABILITY_D0_10G)
2360 lp->req_line_speed[cfx_idx] =
2363 lp->req_line_speed[cfx_idx] =
2368 if (load_mode == LOAD_LOOPBACK_EXT) {
2369 struct link_params *lp = &bp->link_params;
2370 lp->loopback_mode = LOOPBACK_EXT;
2373 rc = bnx2x_phy_init(&bp->link_params, &bp->link_vars);
2375 bnx2x_release_phy_lock(bp);
2377 bnx2x_init_dropless_fc(bp);
2379 bnx2x_calc_fc_adv(bp);
2381 if (bp->link_vars.link_up) {
2382 bnx2x_stats_handle(bp, STATS_EVENT_LINK_UP);
2383 bnx2x_link_report(bp);
2385 queue_delayed_work(bnx2x_wq, &bp->period_task, 0);
2386 bp->link_params.req_line_speed[cfx_idx] = req_line_speed;
2389 BNX2X_ERR("Bootcode is missing - can not initialize link\n");
2393 void bnx2x_link_set(struct bnx2x *bp)
2395 if (!BP_NOMCP(bp)) {
2396 bnx2x_acquire_phy_lock(bp);
2397 bnx2x_phy_init(&bp->link_params, &bp->link_vars);
2398 bnx2x_release_phy_lock(bp);
2400 bnx2x_init_dropless_fc(bp);
2402 bnx2x_calc_fc_adv(bp);
2404 BNX2X_ERR("Bootcode is missing - can not set link\n");
2407 static void bnx2x__link_reset(struct bnx2x *bp)
2409 if (!BP_NOMCP(bp)) {
2410 bnx2x_acquire_phy_lock(bp);
2411 bnx2x_lfa_reset(&bp->link_params, &bp->link_vars);
2412 bnx2x_release_phy_lock(bp);
2414 BNX2X_ERR("Bootcode is missing - can not reset link\n");
2417 void bnx2x_force_link_reset(struct bnx2x *bp)
2419 bnx2x_acquire_phy_lock(bp);
2420 bnx2x_link_reset(&bp->link_params, &bp->link_vars, 1);
2421 bnx2x_release_phy_lock(bp);
2424 u8 bnx2x_link_test(struct bnx2x *bp, u8 is_serdes)
2428 if (!BP_NOMCP(bp)) {
2429 bnx2x_acquire_phy_lock(bp);
2430 rc = bnx2x_test_link(&bp->link_params, &bp->link_vars,
2432 bnx2x_release_phy_lock(bp);
2434 BNX2X_ERR("Bootcode is missing - can not test link\n");
2439 /* Calculates the sum of vn_min_rates.
2440 It's needed for further normalizing of the min_rates.
2442 sum of vn_min_rates.
2444 0 - if all the min_rates are 0.
2445 In the later case fairness algorithm should be deactivated.
2446 If not all min_rates are zero then those that are zeroes will be set to 1.
2448 static void bnx2x_calc_vn_min(struct bnx2x *bp,
2449 struct cmng_init_input *input)
2454 for (vn = VN_0; vn < BP_MAX_VN_NUM(bp); vn++) {
2455 u32 vn_cfg = bp->mf_config[vn];
2456 u32 vn_min_rate = ((vn_cfg & FUNC_MF_CFG_MIN_BW_MASK) >>
2457 FUNC_MF_CFG_MIN_BW_SHIFT) * 100;
2459 /* Skip hidden vns */
2460 if (vn_cfg & FUNC_MF_CFG_FUNC_HIDE)
2462 /* If min rate is zero - set it to 1 */
2463 else if (!vn_min_rate)
2464 vn_min_rate = DEF_MIN_RATE;
2468 input->vnic_min_rate[vn] = vn_min_rate;
2471 /* if ETS or all min rates are zeros - disable fairness */
2472 if (BNX2X_IS_ETS_ENABLED(bp)) {
2473 input->flags.cmng_enables &=
2474 ~CMNG_FLAGS_PER_PORT_FAIRNESS_VN;
2475 DP(NETIF_MSG_IFUP, "Fairness will be disabled due to ETS\n");
2476 } else if (all_zero) {
2477 input->flags.cmng_enables &=
2478 ~CMNG_FLAGS_PER_PORT_FAIRNESS_VN;
2480 "All MIN values are zeroes fairness will be disabled\n");
2482 input->flags.cmng_enables |=
2483 CMNG_FLAGS_PER_PORT_FAIRNESS_VN;
2486 static void bnx2x_calc_vn_max(struct bnx2x *bp, int vn,
2487 struct cmng_init_input *input)
2490 u32 vn_cfg = bp->mf_config[vn];
2492 if (vn_cfg & FUNC_MF_CFG_FUNC_HIDE)
2495 u32 maxCfg = bnx2x_extract_max_cfg(bp, vn_cfg);
2498 /* maxCfg in percents of linkspeed */
2499 vn_max_rate = (bp->link_vars.line_speed * maxCfg) / 100;
2500 } else /* SD modes */
2501 /* maxCfg is absolute in 100Mb units */
2502 vn_max_rate = maxCfg * 100;
2505 DP(NETIF_MSG_IFUP, "vn %d: vn_max_rate %d\n", vn, vn_max_rate);
2507 input->vnic_max_rate[vn] = vn_max_rate;
2510 static int bnx2x_get_cmng_fns_mode(struct bnx2x *bp)
2512 if (CHIP_REV_IS_SLOW(bp))
2513 return CMNG_FNS_NONE;
2515 return CMNG_FNS_MINMAX;
2517 return CMNG_FNS_NONE;
2520 void bnx2x_read_mf_cfg(struct bnx2x *bp)
2522 int vn, n = (CHIP_MODE_IS_4_PORT(bp) ? 2 : 1);
2525 return; /* what should be the default value in this case */
2527 /* For 2 port configuration the absolute function number formula
2529 * abs_func = 2 * vn + BP_PORT + BP_PATH
2531 * and there are 4 functions per port
2533 * For 4 port configuration it is
2534 * abs_func = 4 * vn + 2 * BP_PORT + BP_PATH
2536 * and there are 2 functions per port
2538 for (vn = VN_0; vn < BP_MAX_VN_NUM(bp); vn++) {
2539 int /*abs*/func = n * (2 * vn + BP_PORT(bp)) + BP_PATH(bp);
2541 if (func >= E1H_FUNC_MAX)
2545 MF_CFG_RD(bp, func_mf_config[func].config);
2547 if (bp->mf_config[BP_VN(bp)] & FUNC_MF_CFG_FUNC_DISABLED) {
2548 DP(NETIF_MSG_IFUP, "mf_cfg function disabled\n");
2549 bp->flags |= MF_FUNC_DIS;
2551 DP(NETIF_MSG_IFUP, "mf_cfg function enabled\n");
2552 bp->flags &= ~MF_FUNC_DIS;
2556 static void bnx2x_cmng_fns_init(struct bnx2x *bp, u8 read_cfg, u8 cmng_type)
2558 struct cmng_init_input input;
2559 memset(&input, 0, sizeof(struct cmng_init_input));
2561 input.port_rate = bp->link_vars.line_speed;
2563 if (cmng_type == CMNG_FNS_MINMAX && input.port_rate) {
2566 /* read mf conf from shmem */
2568 bnx2x_read_mf_cfg(bp);
2570 /* vn_weight_sum and enable fairness if not 0 */
2571 bnx2x_calc_vn_min(bp, &input);
2573 /* calculate and set min-max rate for each vn */
2575 for (vn = VN_0; vn < BP_MAX_VN_NUM(bp); vn++)
2576 bnx2x_calc_vn_max(bp, vn, &input);
2578 /* always enable rate shaping and fairness */
2579 input.flags.cmng_enables |=
2580 CMNG_FLAGS_PER_PORT_RATE_SHAPING_VN;
2582 bnx2x_init_cmng(&input, &bp->cmng);
2586 /* rate shaping and fairness are disabled */
2588 "rate shaping and fairness are disabled\n");
2591 static void storm_memset_cmng(struct bnx2x *bp,
2592 struct cmng_init *cmng,
2596 size_t size = sizeof(struct cmng_struct_per_port);
2598 u32 addr = BAR_XSTRORM_INTMEM +
2599 XSTORM_CMNG_PER_PORT_VARS_OFFSET(port);
2601 __storm_memset_struct(bp, addr, size, (u32 *)&cmng->port);
2603 for (vn = VN_0; vn < BP_MAX_VN_NUM(bp); vn++) {
2604 int func = func_by_vn(bp, vn);
2606 addr = BAR_XSTRORM_INTMEM +
2607 XSTORM_RATE_SHAPING_PER_VN_VARS_OFFSET(func);
2608 size = sizeof(struct rate_shaping_vars_per_vn);
2609 __storm_memset_struct(bp, addr, size,
2610 (u32 *)&cmng->vnic.vnic_max_rate[vn]);
2612 addr = BAR_XSTRORM_INTMEM +
2613 XSTORM_FAIRNESS_PER_VN_VARS_OFFSET(func);
2614 size = sizeof(struct fairness_vars_per_vn);
2615 __storm_memset_struct(bp, addr, size,
2616 (u32 *)&cmng->vnic.vnic_min_rate[vn]);
2620 /* init cmng mode in HW according to local configuration */
2621 void bnx2x_set_local_cmng(struct bnx2x *bp)
2623 int cmng_fns = bnx2x_get_cmng_fns_mode(bp);
2625 if (cmng_fns != CMNG_FNS_NONE) {
2626 bnx2x_cmng_fns_init(bp, false, cmng_fns);
2627 storm_memset_cmng(bp, &bp->cmng, BP_PORT(bp));
2629 /* rate shaping and fairness are disabled */
2631 "single function mode without fairness\n");
2635 /* This function is called upon link interrupt */
2636 static void bnx2x_link_attn(struct bnx2x *bp)
2638 /* Make sure that we are synced with the current statistics */
2639 bnx2x_stats_handle(bp, STATS_EVENT_STOP);
2641 bnx2x_link_update(&bp->link_params, &bp->link_vars);
2643 bnx2x_init_dropless_fc(bp);
2645 if (bp->link_vars.link_up) {
2647 if (bp->link_vars.mac_type != MAC_TYPE_EMAC) {
2648 struct host_port_stats *pstats;
2650 pstats = bnx2x_sp(bp, port_stats);
2651 /* reset old mac stats */
2652 memset(&(pstats->mac_stx[0]), 0,
2653 sizeof(struct mac_stx));
2655 if (bp->state == BNX2X_STATE_OPEN)
2656 bnx2x_stats_handle(bp, STATS_EVENT_LINK_UP);
2659 if (bp->link_vars.link_up && bp->link_vars.line_speed)
2660 bnx2x_set_local_cmng(bp);
2662 __bnx2x_link_report(bp);
2665 bnx2x_link_sync_notify(bp);
2668 void bnx2x__link_status_update(struct bnx2x *bp)
2670 if (bp->state != BNX2X_STATE_OPEN)
2673 /* read updated dcb configuration */
2675 bnx2x_dcbx_pmf_update(bp);
2676 bnx2x_link_status_update(&bp->link_params, &bp->link_vars);
2677 if (bp->link_vars.link_up)
2678 bnx2x_stats_handle(bp, STATS_EVENT_LINK_UP);
2680 bnx2x_stats_handle(bp, STATS_EVENT_STOP);
2681 /* indicate link status */
2682 bnx2x_link_report(bp);
2685 bp->port.supported[0] |= (SUPPORTED_10baseT_Half |
2686 SUPPORTED_10baseT_Full |
2687 SUPPORTED_100baseT_Half |
2688 SUPPORTED_100baseT_Full |
2689 SUPPORTED_1000baseT_Full |
2690 SUPPORTED_2500baseX_Full |
2691 SUPPORTED_10000baseT_Full |
2696 SUPPORTED_Asym_Pause);
2697 bp->port.advertising[0] = bp->port.supported[0];
2699 bp->link_params.bp = bp;
2700 bp->link_params.port = BP_PORT(bp);
2701 bp->link_params.req_duplex[0] = DUPLEX_FULL;
2702 bp->link_params.req_flow_ctrl[0] = BNX2X_FLOW_CTRL_NONE;
2703 bp->link_params.req_line_speed[0] = SPEED_10000;
2704 bp->link_params.speed_cap_mask[0] = 0x7f0000;
2705 bp->link_params.switch_cfg = SWITCH_CFG_10G;
2706 bp->link_vars.mac_type = MAC_TYPE_BMAC;
2707 bp->link_vars.line_speed = SPEED_10000;
2708 bp->link_vars.link_status =
2709 (LINK_STATUS_LINK_UP |
2710 LINK_STATUS_SPEED_AND_DUPLEX_10GTFD);
2711 bp->link_vars.link_up = 1;
2712 bp->link_vars.duplex = DUPLEX_FULL;
2713 bp->link_vars.flow_ctrl = BNX2X_FLOW_CTRL_NONE;
2714 __bnx2x_link_report(bp);
2716 bnx2x_sample_bulletin(bp);
2718 /* if bulletin board did not have an update for link status
2719 * __bnx2x_link_report will report current status
2720 * but it will NOT duplicate report in case of already reported
2721 * during sampling bulletin board.
2723 bnx2x_stats_handle(bp, STATS_EVENT_LINK_UP);
2727 static int bnx2x_afex_func_update(struct bnx2x *bp, u16 vifid,
2728 u16 vlan_val, u8 allowed_prio)
2730 struct bnx2x_func_state_params func_params = {NULL};
2731 struct bnx2x_func_afex_update_params *f_update_params =
2732 &func_params.params.afex_update;
2734 func_params.f_obj = &bp->func_obj;
2735 func_params.cmd = BNX2X_F_CMD_AFEX_UPDATE;
2737 /* no need to wait for RAMROD completion, so don't
2738 * set RAMROD_COMP_WAIT flag
2741 f_update_params->vif_id = vifid;
2742 f_update_params->afex_default_vlan = vlan_val;
2743 f_update_params->allowed_priorities = allowed_prio;
2745 /* if ramrod can not be sent, response to MCP immediately */
2746 if (bnx2x_func_state_change(bp, &func_params) < 0)
2747 bnx2x_fw_command(bp, DRV_MSG_CODE_AFEX_VIFSET_ACK, 0);
2752 static int bnx2x_afex_handle_vif_list_cmd(struct bnx2x *bp, u8 cmd_type,
2753 u16 vif_index, u8 func_bit_map)
2755 struct bnx2x_func_state_params func_params = {NULL};
2756 struct bnx2x_func_afex_viflists_params *update_params =
2757 &func_params.params.afex_viflists;
2761 /* validate only LIST_SET and LIST_GET are received from switch */
2762 if ((cmd_type != VIF_LIST_RULE_GET) && (cmd_type != VIF_LIST_RULE_SET))
2763 BNX2X_ERR("BUG! afex_handle_vif_list_cmd invalid type 0x%x\n",
2766 func_params.f_obj = &bp->func_obj;
2767 func_params.cmd = BNX2X_F_CMD_AFEX_VIFLISTS;
2769 /* set parameters according to cmd_type */
2770 update_params->afex_vif_list_command = cmd_type;
2771 update_params->vif_list_index = vif_index;
2772 update_params->func_bit_map =
2773 (cmd_type == VIF_LIST_RULE_GET) ? 0 : func_bit_map;
2774 update_params->func_to_clear = 0;
2776 (cmd_type == VIF_LIST_RULE_GET) ?
2777 DRV_MSG_CODE_AFEX_LISTGET_ACK :
2778 DRV_MSG_CODE_AFEX_LISTSET_ACK;
2780 /* if ramrod can not be sent, respond to MCP immediately for
2781 * SET and GET requests (other are not triggered from MCP)
2783 rc = bnx2x_func_state_change(bp, &func_params);
2785 bnx2x_fw_command(bp, drv_msg_code, 0);
2790 static void bnx2x_handle_afex_cmd(struct bnx2x *bp, u32 cmd)
2792 struct afex_stats afex_stats;
2793 u32 func = BP_ABS_FUNC(bp);
2800 u32 addr_to_write, vifid, addrs, stats_type, i;
2802 if (cmd & DRV_STATUS_AFEX_LISTGET_REQ) {
2803 vifid = SHMEM2_RD(bp, afex_param1_to_driver[BP_FW_MB_IDX(bp)]);
2805 "afex: got MCP req LISTGET_REQ for vifid 0x%x\n", vifid);
2806 bnx2x_afex_handle_vif_list_cmd(bp, VIF_LIST_RULE_GET, vifid, 0);
2809 if (cmd & DRV_STATUS_AFEX_LISTSET_REQ) {
2810 vifid = SHMEM2_RD(bp, afex_param1_to_driver[BP_FW_MB_IDX(bp)]);
2811 addrs = SHMEM2_RD(bp, afex_param2_to_driver[BP_FW_MB_IDX(bp)]);
2813 "afex: got MCP req LISTSET_REQ for vifid 0x%x addrs 0x%x\n",
2815 bnx2x_afex_handle_vif_list_cmd(bp, VIF_LIST_RULE_SET, vifid,
2819 if (cmd & DRV_STATUS_AFEX_STATSGET_REQ) {
2820 addr_to_write = SHMEM2_RD(bp,
2821 afex_scratchpad_addr_to_write[BP_FW_MB_IDX(bp)]);
2822 stats_type = SHMEM2_RD(bp,
2823 afex_param1_to_driver[BP_FW_MB_IDX(bp)]);
2826 "afex: got MCP req STATSGET_REQ, write to addr 0x%x\n",
2829 bnx2x_afex_collect_stats(bp, (void *)&afex_stats, stats_type);
2831 /* write response to scratchpad, for MCP */
2832 for (i = 0; i < (sizeof(struct afex_stats)/sizeof(u32)); i++)
2833 REG_WR(bp, addr_to_write + i*sizeof(u32),
2834 *(((u32 *)(&afex_stats))+i));
2836 /* send ack message to MCP */
2837 bnx2x_fw_command(bp, DRV_MSG_CODE_AFEX_STATSGET_ACK, 0);
2840 if (cmd & DRV_STATUS_AFEX_VIFSET_REQ) {
2841 mf_config = MF_CFG_RD(bp, func_mf_config[func].config);
2842 bp->mf_config[BP_VN(bp)] = mf_config;
2844 "afex: got MCP req VIFSET_REQ, mf_config 0x%x\n",
2847 /* if VIF_SET is "enabled" */
2848 if (!(mf_config & FUNC_MF_CFG_FUNC_DISABLED)) {
2849 /* set rate limit directly to internal RAM */
2850 struct cmng_init_input cmng_input;
2851 struct rate_shaping_vars_per_vn m_rs_vn;
2852 size_t size = sizeof(struct rate_shaping_vars_per_vn);
2853 u32 addr = BAR_XSTRORM_INTMEM +
2854 XSTORM_RATE_SHAPING_PER_VN_VARS_OFFSET(BP_FUNC(bp));
2856 bp->mf_config[BP_VN(bp)] = mf_config;
2858 bnx2x_calc_vn_max(bp, BP_VN(bp), &cmng_input);
2859 m_rs_vn.vn_counter.rate =
2860 cmng_input.vnic_max_rate[BP_VN(bp)];
2861 m_rs_vn.vn_counter.quota =
2862 (m_rs_vn.vn_counter.rate *
2863 RS_PERIODIC_TIMEOUT_USEC) / 8;
2865 __storm_memset_struct(bp, addr, size, (u32 *)&m_rs_vn);
2867 /* read relevant values from mf_cfg struct in shmem */
2869 (MF_CFG_RD(bp, func_mf_config[func].e1hov_tag) &
2870 FUNC_MF_CFG_E1HOV_TAG_MASK) >>
2871 FUNC_MF_CFG_E1HOV_TAG_SHIFT;
2873 (MF_CFG_RD(bp, func_mf_config[func].e1hov_tag) &
2874 FUNC_MF_CFG_AFEX_VLAN_MASK) >>
2875 FUNC_MF_CFG_AFEX_VLAN_SHIFT;
2876 vlan_prio = (mf_config &
2877 FUNC_MF_CFG_TRANSMIT_PRIORITY_MASK) >>
2878 FUNC_MF_CFG_TRANSMIT_PRIORITY_SHIFT;
2879 vlan_val |= (vlan_prio << VLAN_PRIO_SHIFT);
2882 func_mf_config[func].afex_config) &
2883 FUNC_MF_CFG_AFEX_VLAN_MODE_MASK) >>
2884 FUNC_MF_CFG_AFEX_VLAN_MODE_SHIFT;
2887 func_mf_config[func].afex_config) &
2888 FUNC_MF_CFG_AFEX_COS_FILTER_MASK) >>
2889 FUNC_MF_CFG_AFEX_COS_FILTER_SHIFT;
2891 /* send ramrod to FW, return in case of failure */
2892 if (bnx2x_afex_func_update(bp, vif_id, vlan_val,
2896 bp->afex_def_vlan_tag = vlan_val;
2897 bp->afex_vlan_mode = vlan_mode;
2899 /* notify link down because BP->flags is disabled */
2900 bnx2x_link_report(bp);
2902 /* send INVALID VIF ramrod to FW */
2903 bnx2x_afex_func_update(bp, 0xFFFF, 0, 0);
2905 /* Reset the default afex VLAN */
2906 bp->afex_def_vlan_tag = -1;
2911 static void bnx2x_handle_update_svid_cmd(struct bnx2x *bp)
2913 struct bnx2x_func_switch_update_params *switch_update_params;
2914 struct bnx2x_func_state_params func_params;
2916 memset(&func_params, 0, sizeof(struct bnx2x_func_state_params));
2917 switch_update_params = &func_params.params.switch_update;
2918 func_params.f_obj = &bp->func_obj;
2919 func_params.cmd = BNX2X_F_CMD_SWITCH_UPDATE;
2921 if (IS_MF_UFP(bp) || IS_MF_BD(bp)) {
2922 int func = BP_ABS_FUNC(bp);
2925 /* Re-learn the S-tag from shmem */
2926 val = MF_CFG_RD(bp, func_mf_config[func].e1hov_tag) &
2927 FUNC_MF_CFG_E1HOV_TAG_MASK;
2928 if (val != FUNC_MF_CFG_E1HOV_TAG_DEFAULT) {
2931 BNX2X_ERR("Got an SVID event, but no tag is configured in shmem\n");
2935 /* Configure new S-tag in LLH */
2936 REG_WR(bp, NIG_REG_LLH0_FUNC_VLAN_ID + BP_PORT(bp) * 8,
2939 /* Send Ramrod to update FW of change */
2940 __set_bit(BNX2X_F_UPDATE_SD_VLAN_TAG_CHNG,
2941 &switch_update_params->changes);
2942 switch_update_params->vlan = bp->mf_ov;
2944 if (bnx2x_func_state_change(bp, &func_params) < 0) {
2945 BNX2X_ERR("Failed to configure FW of S-tag Change to %02x\n",
2949 DP(BNX2X_MSG_MCP, "Configured S-tag %02x\n",
2956 bnx2x_fw_command(bp, DRV_MSG_CODE_OEM_UPDATE_SVID_OK, 0);
2959 bnx2x_fw_command(bp, DRV_MSG_CODE_OEM_UPDATE_SVID_FAILURE, 0);
2962 static void bnx2x_pmf_update(struct bnx2x *bp)
2964 int port = BP_PORT(bp);
2968 DP(BNX2X_MSG_MCP, "pmf %d\n", bp->port.pmf);
2971 * We need the mb() to ensure the ordering between the writing to
2972 * bp->port.pmf here and reading it from the bnx2x_periodic_task().
2976 /* queue a periodic task */
2977 queue_delayed_work(bnx2x_wq, &bp->period_task, 0);
2979 bnx2x_dcbx_pmf_update(bp);
2981 /* enable nig attention */
2982 val = (0xff0f | (1 << (BP_VN(bp) + 4)));
2983 if (bp->common.int_block == INT_BLOCK_HC) {
2984 REG_WR(bp, HC_REG_TRAILING_EDGE_0 + port*8, val);
2985 REG_WR(bp, HC_REG_LEADING_EDGE_0 + port*8, val);
2986 } else if (!CHIP_IS_E1x(bp)) {
2987 REG_WR(bp, IGU_REG_TRAILING_EDGE_LATCH, val);
2988 REG_WR(bp, IGU_REG_LEADING_EDGE_LATCH, val);
2991 bnx2x_stats_handle(bp, STATS_EVENT_PMF);
2999 * General service functions
3002 /* send the MCP a request, block until there is a reply */
3003 u32 bnx2x_fw_command(struct bnx2x *bp, u32 command, u32 param)
3005 int mb_idx = BP_FW_MB_IDX(bp);
3009 u8 delay = CHIP_REV_IS_SLOW(bp) ? 100 : 10;
3011 mutex_lock(&bp->fw_mb_mutex);
3013 SHMEM_WR(bp, func_mb[mb_idx].drv_mb_param, param);
3014 SHMEM_WR(bp, func_mb[mb_idx].drv_mb_header, (command | seq));
3016 DP(BNX2X_MSG_MCP, "wrote command (%x) to FW MB param 0x%08x\n",
3017 (command | seq), param);
3020 /* let the FW do it's magic ... */
3023 rc = SHMEM_RD(bp, func_mb[mb_idx].fw_mb_header);
3025 /* Give the FW up to 5 second (500*10ms) */
3026 } while ((seq != (rc & FW_MSG_SEQ_NUMBER_MASK)) && (cnt++ < 500));
3028 DP(BNX2X_MSG_MCP, "[after %d ms] read (%x) seq is (%x) from FW MB\n",
3029 cnt*delay, rc, seq);
3031 /* is this a reply to our command? */
3032 if (seq == (rc & FW_MSG_SEQ_NUMBER_MASK))
3033 rc &= FW_MSG_CODE_MASK;
3036 BNX2X_ERR("FW failed to respond!\n");
3040 mutex_unlock(&bp->fw_mb_mutex);
3045 static void storm_memset_func_cfg(struct bnx2x *bp,
3046 struct tstorm_eth_function_common_config *tcfg,
3049 size_t size = sizeof(struct tstorm_eth_function_common_config);
3051 u32 addr = BAR_TSTRORM_INTMEM +
3052 TSTORM_FUNCTION_COMMON_CONFIG_OFFSET(abs_fid);
3054 __storm_memset_struct(bp, addr, size, (u32 *)tcfg);
3057 void bnx2x_func_init(struct bnx2x *bp, struct bnx2x_func_init_params *p)
3059 if (CHIP_IS_E1x(bp)) {
3060 struct tstorm_eth_function_common_config tcfg = {0};
3062 storm_memset_func_cfg(bp, &tcfg, p->func_id);
3065 /* Enable the function in the FW */
3066 storm_memset_vf_to_pf(bp, p->func_id, p->pf_id);
3067 storm_memset_func_en(bp, p->func_id, 1);
3070 if (p->func_flgs & FUNC_FLG_SPQ) {
3071 storm_memset_spq_addr(bp, p->spq_map, p->func_id);
3072 REG_WR(bp, XSEM_REG_FAST_MEMORY +
3073 XSTORM_SPQ_PROD_OFFSET(p->func_id), p->spq_prod);
3078 * bnx2x_get_common_flags - Return common flags
3082 * @zero_stats TRUE if statistics zeroing is needed
3084 * Return the flags that are common for the Tx-only and not normal connections.
3086 static unsigned long bnx2x_get_common_flags(struct bnx2x *bp,
3087 struct bnx2x_fastpath *fp,
3090 unsigned long flags = 0;
3092 /* PF driver will always initialize the Queue to an ACTIVE state */
3093 __set_bit(BNX2X_Q_FLG_ACTIVE, &flags);
3095 /* tx only connections collect statistics (on the same index as the
3096 * parent connection). The statistics are zeroed when the parent
3097 * connection is initialized.
3100 __set_bit(BNX2X_Q_FLG_STATS, &flags);
3102 __set_bit(BNX2X_Q_FLG_ZERO_STATS, &flags);
3104 if (bp->flags & TX_SWITCHING)
3105 __set_bit(BNX2X_Q_FLG_TX_SWITCH, &flags);
3107 __set_bit(BNX2X_Q_FLG_PCSUM_ON_PKT, &flags);
3108 __set_bit(BNX2X_Q_FLG_TUN_INC_INNER_IP_ID, &flags);
3110 #ifdef BNX2X_STOP_ON_ERROR
3111 __set_bit(BNX2X_Q_FLG_TX_SEC, &flags);
3117 static unsigned long bnx2x_get_q_flags(struct bnx2x *bp,
3118 struct bnx2x_fastpath *fp,
3121 unsigned long flags = 0;
3123 /* calculate other queue flags */
3125 __set_bit(BNX2X_Q_FLG_OV, &flags);
3127 if (IS_FCOE_FP(fp)) {
3128 __set_bit(BNX2X_Q_FLG_FCOE, &flags);
3129 /* For FCoE - force usage of default priority (for afex) */
3130 __set_bit(BNX2X_Q_FLG_FORCE_DEFAULT_PRI, &flags);
3133 if (fp->mode != TPA_MODE_DISABLED) {
3134 __set_bit(BNX2X_Q_FLG_TPA, &flags);
3135 __set_bit(BNX2X_Q_FLG_TPA_IPV6, &flags);
3136 if (fp->mode == TPA_MODE_GRO)
3137 __set_bit(BNX2X_Q_FLG_TPA_GRO, &flags);
3141 __set_bit(BNX2X_Q_FLG_LEADING_RSS, &flags);
3142 __set_bit(BNX2X_Q_FLG_MCAST, &flags);
3145 /* Always set HW VLAN stripping */
3146 __set_bit(BNX2X_Q_FLG_VLAN, &flags);
3148 /* configure silent vlan removal */
3150 __set_bit(BNX2X_Q_FLG_SILENT_VLAN_REM, &flags);
3152 return flags | bnx2x_get_common_flags(bp, fp, true);
3155 static void bnx2x_pf_q_prep_general(struct bnx2x *bp,
3156 struct bnx2x_fastpath *fp, struct bnx2x_general_setup_params *gen_init,
3159 gen_init->stat_id = bnx2x_stats_id(fp);
3160 gen_init->spcl_id = fp->cl_id;
3162 /* Always use mini-jumbo MTU for FCoE L2 ring */
3164 gen_init->mtu = BNX2X_FCOE_MINI_JUMBO_MTU;
3166 gen_init->mtu = bp->dev->mtu;
3168 gen_init->cos = cos;
3170 gen_init->fp_hsi = ETH_FP_HSI_VERSION;
3173 static void bnx2x_pf_rx_q_prep(struct bnx2x *bp,
3174 struct bnx2x_fastpath *fp, struct rxq_pause_params *pause,
3175 struct bnx2x_rxq_setup_params *rxq_init)
3179 u16 tpa_agg_size = 0;
3181 if (fp->mode != TPA_MODE_DISABLED) {
3182 pause->sge_th_lo = SGE_TH_LO(bp);
3183 pause->sge_th_hi = SGE_TH_HI(bp);
3185 /* validate SGE ring has enough to cross high threshold */
3186 WARN_ON(bp->dropless_fc &&
3187 pause->sge_th_hi + FW_PREFETCH_CNT >
3188 MAX_RX_SGE_CNT * NUM_RX_SGE_PAGES);
3190 tpa_agg_size = TPA_AGG_SIZE;
3191 max_sge = SGE_PAGE_ALIGN(bp->dev->mtu) >>
3193 max_sge = ((max_sge + PAGES_PER_SGE - 1) &
3194 (~(PAGES_PER_SGE-1))) >> PAGES_PER_SGE_SHIFT;
3195 sge_sz = (u16)min_t(u32, SGE_PAGES, 0xffff);
3198 /* pause - not for e1 */
3199 if (!CHIP_IS_E1(bp)) {
3200 pause->bd_th_lo = BD_TH_LO(bp);
3201 pause->bd_th_hi = BD_TH_HI(bp);
3203 pause->rcq_th_lo = RCQ_TH_LO(bp);
3204 pause->rcq_th_hi = RCQ_TH_HI(bp);
3206 * validate that rings have enough entries to cross
3209 WARN_ON(bp->dropless_fc &&
3210 pause->bd_th_hi + FW_PREFETCH_CNT >
3212 WARN_ON(bp->dropless_fc &&
3213 pause->rcq_th_hi + FW_PREFETCH_CNT >
3214 NUM_RCQ_RINGS * MAX_RCQ_DESC_CNT);
3220 rxq_init->dscr_map = fp->rx_desc_mapping;
3221 rxq_init->sge_map = fp->rx_sge_mapping;
3222 rxq_init->rcq_map = fp->rx_comp_mapping;
3223 rxq_init->rcq_np_map = fp->rx_comp_mapping + BCM_PAGE_SIZE;
3225 /* This should be a maximum number of data bytes that may be
3226 * placed on the BD (not including paddings).
3228 rxq_init->buf_sz = fp->rx_buf_size - BNX2X_FW_RX_ALIGN_START -
3229 BNX2X_FW_RX_ALIGN_END - IP_HEADER_ALIGNMENT_PADDING;
3231 rxq_init->cl_qzone_id = fp->cl_qzone_id;
3232 rxq_init->tpa_agg_sz = tpa_agg_size;
3233 rxq_init->sge_buf_sz = sge_sz;
3234 rxq_init->max_sges_pkt = max_sge;
3235 rxq_init->rss_engine_id = BP_FUNC(bp);
3236 rxq_init->mcast_engine_id = BP_FUNC(bp);
3238 /* Maximum number or simultaneous TPA aggregation for this Queue.
3240 * For PF Clients it should be the maximum available number.
3241 * VF driver(s) may want to define it to a smaller value.
3243 rxq_init->max_tpa_queues = MAX_AGG_QS(bp);
3245 rxq_init->cache_line_log = BNX2X_RX_ALIGN_SHIFT;
3246 rxq_init->fw_sb_id = fp->fw_sb_id;
3249 rxq_init->sb_cq_index = HC_SP_INDEX_ETH_FCOE_RX_CQ_CONS;
3251 rxq_init->sb_cq_index = HC_INDEX_ETH_RX_CQ_CONS;
3252 /* configure silent vlan removal
3253 * if multi function mode is afex, then mask default vlan
3255 if (IS_MF_AFEX(bp)) {
3256 rxq_init->silent_removal_value = bp->afex_def_vlan_tag;
3257 rxq_init->silent_removal_mask = VLAN_VID_MASK;
3261 static void bnx2x_pf_tx_q_prep(struct bnx2x *bp,
3262 struct bnx2x_fastpath *fp, struct bnx2x_txq_setup_params *txq_init,
3265 txq_init->dscr_map = fp->txdata_ptr[cos]->tx_desc_mapping;
3266 txq_init->sb_cq_index = HC_INDEX_ETH_FIRST_TX_CQ_CONS + cos;
3267 txq_init->traffic_type = LLFC_TRAFFIC_TYPE_NW;
3268 txq_init->fw_sb_id = fp->fw_sb_id;
3271 * set the tss leading client id for TX classification ==
3272 * leading RSS client id
3274 txq_init->tss_leading_cl_id = bnx2x_fp(bp, 0, cl_id);
3276 if (IS_FCOE_FP(fp)) {
3277 txq_init->sb_cq_index = HC_SP_INDEX_ETH_FCOE_TX_CQ_CONS;
3278 txq_init->traffic_type = LLFC_TRAFFIC_TYPE_FCOE;
3282 static void bnx2x_pf_init(struct bnx2x *bp)
3284 struct bnx2x_func_init_params func_init = {0};
3285 struct event_ring_data eq_data = { {0} };
3288 if (!CHIP_IS_E1x(bp)) {
3289 /* reset IGU PF statistics: MSIX + ATTN */
3291 REG_WR(bp, IGU_REG_STATISTIC_NUM_MESSAGE_SENT +
3292 BNX2X_IGU_STAS_MSG_VF_CNT*4 +
3293 (CHIP_MODE_IS_4_PORT(bp) ?
3294 BP_FUNC(bp) : BP_VN(bp))*4, 0);
3296 REG_WR(bp, IGU_REG_STATISTIC_NUM_MESSAGE_SENT +
3297 BNX2X_IGU_STAS_MSG_VF_CNT*4 +
3298 BNX2X_IGU_STAS_MSG_PF_CNT*4 +
3299 (CHIP_MODE_IS_4_PORT(bp) ?
3300 BP_FUNC(bp) : BP_VN(bp))*4, 0);
3303 /* function setup flags */
3304 flags = (FUNC_FLG_STATS | FUNC_FLG_LEADING | FUNC_FLG_SPQ);
3306 /* This flag is relevant for E1x only.
3307 * E2 doesn't have a TPA configuration in a function level.
3309 flags |= (bp->dev->features & NETIF_F_LRO) ? FUNC_FLG_TPA : 0;
3311 func_init.func_flgs = flags;
3312 func_init.pf_id = BP_FUNC(bp);
3313 func_init.func_id = BP_FUNC(bp);
3314 func_init.spq_map = bp->spq_mapping;
3315 func_init.spq_prod = bp->spq_prod_idx;
3317 bnx2x_func_init(bp, &func_init);
3319 memset(&(bp->cmng), 0, sizeof(struct cmng_struct_per_port));
3322 * Congestion management values depend on the link rate
3323 * There is no active link so initial link rate is set to 10 Gbps.
3324 * When the link comes up The congestion management values are
3325 * re-calculated according to the actual link rate.
3327 bp->link_vars.line_speed = SPEED_10000;
3328 bnx2x_cmng_fns_init(bp, true, bnx2x_get_cmng_fns_mode(bp));
3330 /* Only the PMF sets the HW */
3332 storm_memset_cmng(bp, &bp->cmng, BP_PORT(bp));
3334 /* init Event Queue - PCI bus guarantees correct endianity*/
3335 eq_data.base_addr.hi = U64_HI(bp->eq_mapping);
3336 eq_data.base_addr.lo = U64_LO(bp->eq_mapping);
3337 eq_data.producer = bp->eq_prod;
3338 eq_data.index_id = HC_SP_INDEX_EQ_CONS;
3339 eq_data.sb_id = DEF_SB_ID;
3340 storm_memset_eq_data(bp, &eq_data, BP_FUNC(bp));
3343 static void bnx2x_e1h_disable(struct bnx2x *bp)
3345 int port = BP_PORT(bp);
3347 bnx2x_tx_disable(bp);
3349 REG_WR(bp, NIG_REG_LLH0_FUNC_EN + port*8, 0);
3352 static void bnx2x_e1h_enable(struct bnx2x *bp)
3354 int port = BP_PORT(bp);
3356 if (!(IS_MF_UFP(bp) && BNX2X_IS_MF_SD_PROTOCOL_FCOE(bp)))
3357 REG_WR(bp, NIG_REG_LLH0_FUNC_EN + port * 8, 1);
3359 /* Tx queue should be only re-enabled */
3360 netif_tx_wake_all_queues(bp->dev);
3363 * Should not call netif_carrier_on since it will be called if the link
3364 * is up when checking for link state
3368 #define DRV_INFO_ETH_STAT_NUM_MACS_REQUIRED 3
3370 static void bnx2x_drv_info_ether_stat(struct bnx2x *bp)
3372 struct eth_stats_info *ether_stat =
3373 &bp->slowpath->drv_info_to_mcp.ether_stat;
3374 struct bnx2x_vlan_mac_obj *mac_obj =
3375 &bp->sp_objs->mac_obj;
3378 strlcpy(ether_stat->version, DRV_MODULE_VERSION,
3379 ETH_STAT_INFO_VERSION_LEN);
3381 /* get DRV_INFO_ETH_STAT_NUM_MACS_REQUIRED macs, placing them in the
3382 * mac_local field in ether_stat struct. The base address is offset by 2
3383 * bytes to account for the field being 8 bytes but a mac address is
3384 * only 6 bytes. Likewise, the stride for the get_n_elements function is
3385 * 2 bytes to compensate from the 6 bytes of a mac to the 8 bytes
3386 * allocated by the ether_stat struct, so the macs will land in their
3389 for (i = 0; i < DRV_INFO_ETH_STAT_NUM_MACS_REQUIRED; i++)
3390 memset(ether_stat->mac_local + i, 0,
3391 sizeof(ether_stat->mac_local[0]));
3392 mac_obj->get_n_elements(bp, &bp->sp_objs[0].mac_obj,
3393 DRV_INFO_ETH_STAT_NUM_MACS_REQUIRED,
3394 ether_stat->mac_local + MAC_PAD, MAC_PAD,
3396 ether_stat->mtu_size = bp->dev->mtu;
3397 if (bp->dev->features & NETIF_F_RXCSUM)
3398 ether_stat->feature_flags |= FEATURE_ETH_CHKSUM_OFFLOAD_MASK;
3399 if (bp->dev->features & NETIF_F_TSO)
3400 ether_stat->feature_flags |= FEATURE_ETH_LSO_MASK;
3401 ether_stat->feature_flags |= bp->common.boot_mode;
3403 ether_stat->promiscuous_mode = (bp->dev->flags & IFF_PROMISC) ? 1 : 0;
3405 ether_stat->txq_size = bp->tx_ring_size;
3406 ether_stat->rxq_size = bp->rx_ring_size;
3408 #ifdef CONFIG_BNX2X_SRIOV
3409 ether_stat->vf_cnt = IS_SRIOV(bp) ? bp->vfdb->sriov.nr_virtfn : 0;
3413 static void bnx2x_drv_info_fcoe_stat(struct bnx2x *bp)
3415 struct bnx2x_dcbx_app_params *app = &bp->dcbx_port_params.app;
3416 struct fcoe_stats_info *fcoe_stat =
3417 &bp->slowpath->drv_info_to_mcp.fcoe_stat;
3419 if (!CNIC_LOADED(bp))
3422 memcpy(fcoe_stat->mac_local + MAC_PAD, bp->fip_mac, ETH_ALEN);
3424 fcoe_stat->qos_priority =
3425 app->traffic_type_priority[LLFC_TRAFFIC_TYPE_FCOE];
3427 /* insert FCoE stats from ramrod response */
3429 struct tstorm_per_queue_stats *fcoe_q_tstorm_stats =
3430 &bp->fw_stats_data->queue_stats[FCOE_IDX(bp)].
3431 tstorm_queue_statistics;
3433 struct xstorm_per_queue_stats *fcoe_q_xstorm_stats =
3434 &bp->fw_stats_data->queue_stats[FCOE_IDX(bp)].
3435 xstorm_queue_statistics;
3437 struct fcoe_statistics_params *fw_fcoe_stat =
3438 &bp->fw_stats_data->fcoe;
3440 ADD_64_LE(fcoe_stat->rx_bytes_hi, LE32_0,
3441 fcoe_stat->rx_bytes_lo,
3442 fw_fcoe_stat->rx_stat0.fcoe_rx_byte_cnt);
3444 ADD_64_LE(fcoe_stat->rx_bytes_hi,
3445 fcoe_q_tstorm_stats->rcv_ucast_bytes.hi,
3446 fcoe_stat->rx_bytes_lo,
3447 fcoe_q_tstorm_stats->rcv_ucast_bytes.lo);
3449 ADD_64_LE(fcoe_stat->rx_bytes_hi,
3450 fcoe_q_tstorm_stats->rcv_bcast_bytes.hi,
3451 fcoe_stat->rx_bytes_lo,
3452 fcoe_q_tstorm_stats->rcv_bcast_bytes.lo);
3454 ADD_64_LE(fcoe_stat->rx_bytes_hi,
3455 fcoe_q_tstorm_stats->rcv_mcast_bytes.hi,
3456 fcoe_stat->rx_bytes_lo,
3457 fcoe_q_tstorm_stats->rcv_mcast_bytes.lo);
3459 ADD_64_LE(fcoe_stat->rx_frames_hi, LE32_0,
3460 fcoe_stat->rx_frames_lo,
3461 fw_fcoe_stat->rx_stat0.fcoe_rx_pkt_cnt);
3463 ADD_64_LE(fcoe_stat->rx_frames_hi, LE32_0,
3464 fcoe_stat->rx_frames_lo,
3465 fcoe_q_tstorm_stats->rcv_ucast_pkts);
3467 ADD_64_LE(fcoe_stat->rx_frames_hi, LE32_0,
3468 fcoe_stat->rx_frames_lo,
3469 fcoe_q_tstorm_stats->rcv_bcast_pkts);
3471 ADD_64_LE(fcoe_stat->rx_frames_hi, LE32_0,
3472 fcoe_stat->rx_frames_lo,
3473 fcoe_q_tstorm_stats->rcv_mcast_pkts);
3475 ADD_64_LE(fcoe_stat->tx_bytes_hi, LE32_0,
3476 fcoe_stat->tx_bytes_lo,
3477 fw_fcoe_stat->tx_stat.fcoe_tx_byte_cnt);
3479 ADD_64_LE(fcoe_stat->tx_bytes_hi,
3480 fcoe_q_xstorm_stats->ucast_bytes_sent.hi,
3481 fcoe_stat->tx_bytes_lo,
3482 fcoe_q_xstorm_stats->ucast_bytes_sent.lo);
3484 ADD_64_LE(fcoe_stat->tx_bytes_hi,
3485 fcoe_q_xstorm_stats->bcast_bytes_sent.hi,
3486 fcoe_stat->tx_bytes_lo,
3487 fcoe_q_xstorm_stats->bcast_bytes_sent.lo);
3489 ADD_64_LE(fcoe_stat->tx_bytes_hi,
3490 fcoe_q_xstorm_stats->mcast_bytes_sent.hi,
3491 fcoe_stat->tx_bytes_lo,
3492 fcoe_q_xstorm_stats->mcast_bytes_sent.lo);
3494 ADD_64_LE(fcoe_stat->tx_frames_hi, LE32_0,
3495 fcoe_stat->tx_frames_lo,
3496 fw_fcoe_stat->tx_stat.fcoe_tx_pkt_cnt);
3498 ADD_64_LE(fcoe_stat->tx_frames_hi, LE32_0,
3499 fcoe_stat->tx_frames_lo,
3500 fcoe_q_xstorm_stats->ucast_pkts_sent);
3502 ADD_64_LE(fcoe_stat->tx_frames_hi, LE32_0,
3503 fcoe_stat->tx_frames_lo,
3504 fcoe_q_xstorm_stats->bcast_pkts_sent);
3506 ADD_64_LE(fcoe_stat->tx_frames_hi, LE32_0,
3507 fcoe_stat->tx_frames_lo,
3508 fcoe_q_xstorm_stats->mcast_pkts_sent);
3511 /* ask L5 driver to add data to the struct */
3512 bnx2x_cnic_notify(bp, CNIC_CTL_FCOE_STATS_GET_CMD);
3515 static void bnx2x_drv_info_iscsi_stat(struct bnx2x *bp)
3517 struct bnx2x_dcbx_app_params *app = &bp->dcbx_port_params.app;
3518 struct iscsi_stats_info *iscsi_stat =
3519 &bp->slowpath->drv_info_to_mcp.iscsi_stat;
3521 if (!CNIC_LOADED(bp))
3524 memcpy(iscsi_stat->mac_local + MAC_PAD, bp->cnic_eth_dev.iscsi_mac,
3527 iscsi_stat->qos_priority =
3528 app->traffic_type_priority[LLFC_TRAFFIC_TYPE_ISCSI];
3530 /* ask L5 driver to add data to the struct */
3531 bnx2x_cnic_notify(bp, CNIC_CTL_ISCSI_STATS_GET_CMD);
3534 /* called due to MCP event (on pmf):
3535 * reread new bandwidth configuration
3537 * notify others function about the change
3539 static void bnx2x_config_mf_bw(struct bnx2x *bp)
3541 if (bp->link_vars.link_up) {
3542 bnx2x_cmng_fns_init(bp, true, CMNG_FNS_MINMAX);
3543 bnx2x_link_sync_notify(bp);
3545 storm_memset_cmng(bp, &bp->cmng, BP_PORT(bp));
3548 static void bnx2x_set_mf_bw(struct bnx2x *bp)
3550 bnx2x_config_mf_bw(bp);
3551 bnx2x_fw_command(bp, DRV_MSG_CODE_SET_MF_BW_ACK, 0);
3554 static void bnx2x_handle_eee_event(struct bnx2x *bp)
3556 DP(BNX2X_MSG_MCP, "EEE - LLDP event\n");
3557 bnx2x_fw_command(bp, DRV_MSG_CODE_EEE_RESULTS_ACK, 0);
3560 #define BNX2X_UPDATE_DRV_INFO_IND_LENGTH (20)
3561 #define BNX2X_UPDATE_DRV_INFO_IND_COUNT (25)
3563 static void bnx2x_handle_drv_info_req(struct bnx2x *bp)
3565 enum drv_info_opcode op_code;
3566 u32 drv_info_ctl = SHMEM2_RD(bp, drv_info_control);
3567 bool release = false;
3570 /* if drv_info version supported by MFW doesn't match - send NACK */
3571 if ((drv_info_ctl & DRV_INFO_CONTROL_VER_MASK) != DRV_INFO_CUR_VER) {
3572 bnx2x_fw_command(bp, DRV_MSG_CODE_DRV_INFO_NACK, 0);
3576 op_code = (drv_info_ctl & DRV_INFO_CONTROL_OP_CODE_MASK) >>
3577 DRV_INFO_CONTROL_OP_CODE_SHIFT;
3579 /* Must prevent other flows from accessing drv_info_to_mcp */
3580 mutex_lock(&bp->drv_info_mutex);
3582 memset(&bp->slowpath->drv_info_to_mcp, 0,
3583 sizeof(union drv_info_to_mcp));
3586 case ETH_STATS_OPCODE:
3587 bnx2x_drv_info_ether_stat(bp);
3589 case FCOE_STATS_OPCODE:
3590 bnx2x_drv_info_fcoe_stat(bp);
3592 case ISCSI_STATS_OPCODE:
3593 bnx2x_drv_info_iscsi_stat(bp);
3596 /* if op code isn't supported - send NACK */
3597 bnx2x_fw_command(bp, DRV_MSG_CODE_DRV_INFO_NACK, 0);
3601 /* if we got drv_info attn from MFW then these fields are defined in
3604 SHMEM2_WR(bp, drv_info_host_addr_lo,
3605 U64_LO(bnx2x_sp_mapping(bp, drv_info_to_mcp)));
3606 SHMEM2_WR(bp, drv_info_host_addr_hi,
3607 U64_HI(bnx2x_sp_mapping(bp, drv_info_to_mcp)));
3609 bnx2x_fw_command(bp, DRV_MSG_CODE_DRV_INFO_ACK, 0);
3611 /* Since possible management wants both this and get_driver_version
3612 * need to wait until management notifies us it finished utilizing
3615 if (!SHMEM2_HAS(bp, mfw_drv_indication)) {
3616 DP(BNX2X_MSG_MCP, "Management does not support indication\n");
3617 } else if (!bp->drv_info_mng_owner) {
3618 u32 bit = MFW_DRV_IND_READ_DONE_OFFSET((BP_ABS_FUNC(bp) >> 1));
3620 for (wait = 0; wait < BNX2X_UPDATE_DRV_INFO_IND_COUNT; wait++) {
3621 u32 indication = SHMEM2_RD(bp, mfw_drv_indication);
3623 /* Management is done; need to clear indication */
3624 if (indication & bit) {
3625 SHMEM2_WR(bp, mfw_drv_indication,
3631 msleep(BNX2X_UPDATE_DRV_INFO_IND_LENGTH);
3635 DP(BNX2X_MSG_MCP, "Management did not release indication\n");
3636 bp->drv_info_mng_owner = true;
3640 mutex_unlock(&bp->drv_info_mutex);
3643 static u32 bnx2x_update_mng_version_utility(u8 *version, bool bnx2x_format)
3649 i = sscanf(version, "1.%c%hhd.%hhd.%hhd",
3650 &vals[0], &vals[1], &vals[2], &vals[3]);
3654 i = sscanf(version, "%hhd.%hhd.%hhd.%hhd",
3655 &vals[0], &vals[1], &vals[2], &vals[3]);
3661 return (vals[0] << 24) | (vals[1] << 16) | (vals[2] << 8) | vals[3];
3664 void bnx2x_update_mng_version(struct bnx2x *bp)
3666 u32 iscsiver = DRV_VER_NOT_LOADED;
3667 u32 fcoever = DRV_VER_NOT_LOADED;
3668 u32 ethver = DRV_VER_NOT_LOADED;
3669 int idx = BP_FW_MB_IDX(bp);
3672 if (!SHMEM2_HAS(bp, func_os_drv_ver))
3675 mutex_lock(&bp->drv_info_mutex);
3676 /* Must not proceed when `bnx2x_handle_drv_info_req' is feasible */
3677 if (bp->drv_info_mng_owner)
3680 if (bp->state != BNX2X_STATE_OPEN)
3683 /* Parse ethernet driver version */
3684 ethver = bnx2x_update_mng_version_utility(DRV_MODULE_VERSION, true);
3685 if (!CNIC_LOADED(bp))
3688 /* Try getting storage driver version via cnic */
3689 memset(&bp->slowpath->drv_info_to_mcp, 0,
3690 sizeof(union drv_info_to_mcp));
3691 bnx2x_drv_info_iscsi_stat(bp);
3692 version = bp->slowpath->drv_info_to_mcp.iscsi_stat.version;
3693 iscsiver = bnx2x_update_mng_version_utility(version, false);
3695 memset(&bp->slowpath->drv_info_to_mcp, 0,
3696 sizeof(union drv_info_to_mcp));
3697 bnx2x_drv_info_fcoe_stat(bp);
3698 version = bp->slowpath->drv_info_to_mcp.fcoe_stat.version;
3699 fcoever = bnx2x_update_mng_version_utility(version, false);
3702 SHMEM2_WR(bp, func_os_drv_ver[idx].versions[DRV_PERS_ETHERNET], ethver);
3703 SHMEM2_WR(bp, func_os_drv_ver[idx].versions[DRV_PERS_ISCSI], iscsiver);
3704 SHMEM2_WR(bp, func_os_drv_ver[idx].versions[DRV_PERS_FCOE], fcoever);
3706 mutex_unlock(&bp->drv_info_mutex);
3708 DP(BNX2X_MSG_MCP, "Setting driver version: ETH [%08x] iSCSI [%08x] FCoE [%08x]\n",
3709 ethver, iscsiver, fcoever);
3712 static void bnx2x_oem_event(struct bnx2x *bp, u32 event)
3714 u32 cmd_ok, cmd_fail;
3717 if (event & DRV_STATUS_DCC_EVENT_MASK &&
3718 event & DRV_STATUS_OEM_EVENT_MASK) {
3719 BNX2X_ERR("Received simultaneous events %08x\n", event);
3723 if (event & DRV_STATUS_DCC_EVENT_MASK) {
3724 cmd_fail = DRV_MSG_CODE_DCC_FAILURE;
3725 cmd_ok = DRV_MSG_CODE_DCC_OK;
3726 } else /* if (event & DRV_STATUS_OEM_EVENT_MASK) */ {
3727 cmd_fail = DRV_MSG_CODE_OEM_FAILURE;
3728 cmd_ok = DRV_MSG_CODE_OEM_OK;
3731 DP(BNX2X_MSG_MCP, "oem_event 0x%x\n", event);
3733 if (event & (DRV_STATUS_DCC_DISABLE_ENABLE_PF |
3734 DRV_STATUS_OEM_DISABLE_ENABLE_PF)) {
3735 /* This is the only place besides the function initialization
3736 * where the bp->flags can change so it is done without any
3739 if (bp->mf_config[BP_VN(bp)] & FUNC_MF_CFG_FUNC_DISABLED) {
3740 DP(BNX2X_MSG_MCP, "mf_cfg function disabled\n");
3741 bp->flags |= MF_FUNC_DIS;
3743 bnx2x_e1h_disable(bp);
3745 DP(BNX2X_MSG_MCP, "mf_cfg function enabled\n");
3746 bp->flags &= ~MF_FUNC_DIS;
3748 bnx2x_e1h_enable(bp);
3750 event &= ~(DRV_STATUS_DCC_DISABLE_ENABLE_PF |
3751 DRV_STATUS_OEM_DISABLE_ENABLE_PF);
3754 if (event & (DRV_STATUS_DCC_BANDWIDTH_ALLOCATION |
3755 DRV_STATUS_OEM_BANDWIDTH_ALLOCATION)) {
3756 bnx2x_config_mf_bw(bp);
3757 event &= ~(DRV_STATUS_DCC_BANDWIDTH_ALLOCATION |
3758 DRV_STATUS_OEM_BANDWIDTH_ALLOCATION);
3761 /* Report results to MCP */
3763 bnx2x_fw_command(bp, cmd_fail, 0);
3765 bnx2x_fw_command(bp, cmd_ok, 0);
3768 /* must be called under the spq lock */
3769 static struct eth_spe *bnx2x_sp_get_next(struct bnx2x *bp)
3771 struct eth_spe *next_spe = bp->spq_prod_bd;
3773 if (bp->spq_prod_bd == bp->spq_last_bd) {
3774 bp->spq_prod_bd = bp->spq;
3775 bp->spq_prod_idx = 0;
3776 DP(BNX2X_MSG_SP, "end of spq\n");
3784 /* must be called under the spq lock */
3785 static void bnx2x_sp_prod_update(struct bnx2x *bp)
3787 int func = BP_FUNC(bp);
3790 * Make sure that BD data is updated before writing the producer:
3791 * BD data is written to the memory, the producer is read from the
3792 * memory, thus we need a full memory barrier to ensure the ordering.
3796 REG_WR16(bp, BAR_XSTRORM_INTMEM + XSTORM_SPQ_PROD_OFFSET(func),
3802 * bnx2x_is_contextless_ramrod - check if the current command ends on EQ
3804 * @cmd: command to check
3805 * @cmd_type: command type
3807 static bool bnx2x_is_contextless_ramrod(int cmd, int cmd_type)
3809 if ((cmd_type == NONE_CONNECTION_TYPE) ||
3810 (cmd == RAMROD_CMD_ID_ETH_FORWARD_SETUP) ||
3811 (cmd == RAMROD_CMD_ID_ETH_CLASSIFICATION_RULES) ||
3812 (cmd == RAMROD_CMD_ID_ETH_FILTER_RULES) ||
3813 (cmd == RAMROD_CMD_ID_ETH_MULTICAST_RULES) ||
3814 (cmd == RAMROD_CMD_ID_ETH_SET_MAC) ||
3815 (cmd == RAMROD_CMD_ID_ETH_RSS_UPDATE))
3822 * bnx2x_sp_post - place a single command on an SP ring
3824 * @bp: driver handle
3825 * @command: command to place (e.g. SETUP, FILTER_RULES, etc.)
3826 * @cid: SW CID the command is related to
3827 * @data_hi: command private data address (high 32 bits)
3828 * @data_lo: command private data address (low 32 bits)
3829 * @cmd_type: command type (e.g. NONE, ETH)
3831 * SP data is handled as if it's always an address pair, thus data fields are
3832 * not swapped to little endian in upper functions. Instead this function swaps
3833 * data as if it's two u32 fields.
3835 int bnx2x_sp_post(struct bnx2x *bp, int command, int cid,
3836 u32 data_hi, u32 data_lo, int cmd_type)
3838 struct eth_spe *spe;
3840 bool common = bnx2x_is_contextless_ramrod(command, cmd_type);
3842 #ifdef BNX2X_STOP_ON_ERROR
3843 if (unlikely(bp->panic)) {
3844 BNX2X_ERR("Can't post SP when there is panic\n");
3849 spin_lock_bh(&bp->spq_lock);
3852 if (!atomic_read(&bp->eq_spq_left)) {
3853 BNX2X_ERR("BUG! EQ ring full!\n");
3854 spin_unlock_bh(&bp->spq_lock);
3858 } else if (!atomic_read(&bp->cq_spq_left)) {
3859 BNX2X_ERR("BUG! SPQ ring full!\n");
3860 spin_unlock_bh(&bp->spq_lock);
3865 spe = bnx2x_sp_get_next(bp);
3867 /* CID needs port number to be encoded int it */
3868 spe->hdr.conn_and_cmd_data =
3869 cpu_to_le32((command << SPE_HDR_CMD_ID_SHIFT) |
3872 /* In some cases, type may already contain the func-id
3873 * mainly in SRIOV related use cases, so we add it here only
3874 * if it's not already set.
3876 if (!(cmd_type & SPE_HDR_FUNCTION_ID)) {
3877 type = (cmd_type << SPE_HDR_CONN_TYPE_SHIFT) &
3879 type |= ((BP_FUNC(bp) << SPE_HDR_FUNCTION_ID_SHIFT) &
3880 SPE_HDR_FUNCTION_ID);
3885 spe->hdr.type = cpu_to_le16(type);
3887 spe->data.update_data_addr.hi = cpu_to_le32(data_hi);
3888 spe->data.update_data_addr.lo = cpu_to_le32(data_lo);
3891 * It's ok if the actual decrement is issued towards the memory
3892 * somewhere between the spin_lock and spin_unlock. Thus no
3893 * more explicit memory barrier is needed.
3896 atomic_dec(&bp->eq_spq_left);
3898 atomic_dec(&bp->cq_spq_left);
3901 "SPQE[%x] (%x:%x) (cmd, common?) (%d,%d) hw_cid %x data (%x:%x) type(0x%x) left (CQ, EQ) (%x,%x)\n",
3902 bp->spq_prod_idx, (u32)U64_HI(bp->spq_mapping),
3903 (u32)(U64_LO(bp->spq_mapping) +
3904 (void *)bp->spq_prod_bd - (void *)bp->spq), command, common,
3905 HW_CID(bp, cid), data_hi, data_lo, type,
3906 atomic_read(&bp->cq_spq_left), atomic_read(&bp->eq_spq_left));
3908 bnx2x_sp_prod_update(bp);
3909 spin_unlock_bh(&bp->spq_lock);
3913 /* acquire split MCP access lock register */
3914 static int bnx2x_acquire_alr(struct bnx2x *bp)
3920 for (j = 0; j < 1000; j++) {
3921 REG_WR(bp, MCP_REG_MCPR_ACCESS_LOCK, MCPR_ACCESS_LOCK_LOCK);
3922 val = REG_RD(bp, MCP_REG_MCPR_ACCESS_LOCK);
3923 if (val & MCPR_ACCESS_LOCK_LOCK)
3926 usleep_range(5000, 10000);
3928 if (!(val & MCPR_ACCESS_LOCK_LOCK)) {
3929 BNX2X_ERR("Cannot acquire MCP access lock register\n");
3936 /* release split MCP access lock register */
3937 static void bnx2x_release_alr(struct bnx2x *bp)
3939 REG_WR(bp, MCP_REG_MCPR_ACCESS_LOCK, 0);
3942 #define BNX2X_DEF_SB_ATT_IDX 0x0001
3943 #define BNX2X_DEF_SB_IDX 0x0002
3945 static u16 bnx2x_update_dsb_idx(struct bnx2x *bp)
3947 struct host_sp_status_block *def_sb = bp->def_status_blk;
3950 barrier(); /* status block is written to by the chip */
3951 if (bp->def_att_idx != def_sb->atten_status_block.attn_bits_index) {
3952 bp->def_att_idx = def_sb->atten_status_block.attn_bits_index;
3953 rc |= BNX2X_DEF_SB_ATT_IDX;
3956 if (bp->def_idx != def_sb->sp_sb.running_index) {
3957 bp->def_idx = def_sb->sp_sb.running_index;
3958 rc |= BNX2X_DEF_SB_IDX;
3961 /* Do not reorder: indices reading should complete before handling */
3967 * slow path service functions
3970 static void bnx2x_attn_int_asserted(struct bnx2x *bp, u32 asserted)
3972 int port = BP_PORT(bp);
3973 u32 aeu_addr = port ? MISC_REG_AEU_MASK_ATTN_FUNC_1 :
3974 MISC_REG_AEU_MASK_ATTN_FUNC_0;
3975 u32 nig_int_mask_addr = port ? NIG_REG_MASK_INTERRUPT_PORT1 :
3976 NIG_REG_MASK_INTERRUPT_PORT0;
3981 if (bp->attn_state & asserted)
3982 BNX2X_ERR("IGU ERROR\n");
3984 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_PORT0_ATT_MASK + port);
3985 aeu_mask = REG_RD(bp, aeu_addr);
3987 DP(NETIF_MSG_HW, "aeu_mask %x newly asserted %x\n",
3988 aeu_mask, asserted);
3989 aeu_mask &= ~(asserted & 0x3ff);
3990 DP(NETIF_MSG_HW, "new mask %x\n", aeu_mask);
3992 REG_WR(bp, aeu_addr, aeu_mask);
3993 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_PORT0_ATT_MASK + port);
3995 DP(NETIF_MSG_HW, "attn_state %x\n", bp->attn_state);
3996 bp->attn_state |= asserted;
3997 DP(NETIF_MSG_HW, "new state %x\n", bp->attn_state);
3999 if (asserted & ATTN_HARD_WIRED_MASK) {
4000 if (asserted & ATTN_NIG_FOR_FUNC) {
4002 bnx2x_acquire_phy_lock(bp);
4004 /* save nig interrupt mask */
4005 nig_mask = REG_RD(bp, nig_int_mask_addr);
4007 /* If nig_mask is not set, no need to call the update
4011 REG_WR(bp, nig_int_mask_addr, 0);
4013 bnx2x_link_attn(bp);
4016 /* handle unicore attn? */
4018 if (asserted & ATTN_SW_TIMER_4_FUNC)
4019 DP(NETIF_MSG_HW, "ATTN_SW_TIMER_4_FUNC!\n");
4021 if (asserted & GPIO_2_FUNC)
4022 DP(NETIF_MSG_HW, "GPIO_2_FUNC!\n");
4024 if (asserted & GPIO_3_FUNC)
4025 DP(NETIF_MSG_HW, "GPIO_3_FUNC!\n");
4027 if (asserted & GPIO_4_FUNC)
4028 DP(NETIF_MSG_HW, "GPIO_4_FUNC!\n");
4031 if (asserted & ATTN_GENERAL_ATTN_1) {
4032 DP(NETIF_MSG_HW, "ATTN_GENERAL_ATTN_1!\n");
4033 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_1, 0x0);
4035 if (asserted & ATTN_GENERAL_ATTN_2) {
4036 DP(NETIF_MSG_HW, "ATTN_GENERAL_ATTN_2!\n");
4037 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_2, 0x0);
4039 if (asserted & ATTN_GENERAL_ATTN_3) {
4040 DP(NETIF_MSG_HW, "ATTN_GENERAL_ATTN_3!\n");
4041 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_3, 0x0);
4044 if (asserted & ATTN_GENERAL_ATTN_4) {
4045 DP(NETIF_MSG_HW, "ATTN_GENERAL_ATTN_4!\n");
4046 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_4, 0x0);
4048 if (asserted & ATTN_GENERAL_ATTN_5) {
4049 DP(NETIF_MSG_HW, "ATTN_GENERAL_ATTN_5!\n");
4050 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_5, 0x0);
4052 if (asserted & ATTN_GENERAL_ATTN_6) {
4053 DP(NETIF_MSG_HW, "ATTN_GENERAL_ATTN_6!\n");
4054 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_6, 0x0);
4058 } /* if hardwired */
4060 if (bp->common.int_block == INT_BLOCK_HC)
4061 reg_addr = (HC_REG_COMMAND_REG + port*32 +
4062 COMMAND_REG_ATTN_BITS_SET);
4064 reg_addr = (BAR_IGU_INTMEM + IGU_CMD_ATTN_BIT_SET_UPPER*8);
4066 DP(NETIF_MSG_HW, "about to mask 0x%08x at %s addr 0x%x\n", asserted,
4067 (bp->common.int_block == INT_BLOCK_HC) ? "HC" : "IGU", reg_addr);
4068 REG_WR(bp, reg_addr, asserted);
4070 /* now set back the mask */
4071 if (asserted & ATTN_NIG_FOR_FUNC) {
4072 /* Verify that IGU ack through BAR was written before restoring
4073 * NIG mask. This loop should exit after 2-3 iterations max.
4075 if (bp->common.int_block != INT_BLOCK_HC) {
4076 u32 cnt = 0, igu_acked;
4078 igu_acked = REG_RD(bp,
4079 IGU_REG_ATTENTION_ACK_BITS);
4080 } while (((igu_acked & ATTN_NIG_FOR_FUNC) == 0) &&
4081 (++cnt < MAX_IGU_ATTN_ACK_TO));
4084 "Failed to verify IGU ack on time\n");
4087 REG_WR(bp, nig_int_mask_addr, nig_mask);
4088 bnx2x_release_phy_lock(bp);
4092 static void bnx2x_fan_failure(struct bnx2x *bp)
4094 int port = BP_PORT(bp);
4096 /* mark the failure */
4099 dev_info.port_hw_config[port].external_phy_config);
4101 ext_phy_config &= ~PORT_HW_CFG_XGXS_EXT_PHY_TYPE_MASK;
4102 ext_phy_config |= PORT_HW_CFG_XGXS_EXT_PHY_TYPE_FAILURE;
4103 SHMEM_WR(bp, dev_info.port_hw_config[port].external_phy_config,
4106 /* log the failure */
4107 netdev_err(bp->dev, "Fan Failure on Network Controller has caused the driver to shutdown the card to prevent permanent damage.\n"
4108 "Please contact OEM Support for assistance\n");
4110 /* Schedule device reset (unload)
4111 * This is due to some boards consuming sufficient power when driver is
4112 * up to overheat if fan fails.
4114 bnx2x_schedule_sp_rtnl(bp, BNX2X_SP_RTNL_FAN_FAILURE, 0);
4117 static void bnx2x_attn_int_deasserted0(struct bnx2x *bp, u32 attn)
4119 int port = BP_PORT(bp);
4123 reg_offset = (port ? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_0 :
4124 MISC_REG_AEU_ENABLE1_FUNC_0_OUT_0);
4126 if (attn & AEU_INPUTS_ATTN_BITS_SPIO5) {
4128 val = REG_RD(bp, reg_offset);
4129 val &= ~AEU_INPUTS_ATTN_BITS_SPIO5;
4130 REG_WR(bp, reg_offset, val);
4132 BNX2X_ERR("SPIO5 hw attention\n");
4134 /* Fan failure attention */
4135 bnx2x_hw_reset_phy(&bp->link_params);
4136 bnx2x_fan_failure(bp);
4139 if ((attn & bp->link_vars.aeu_int_mask) && bp->port.pmf) {
4140 bnx2x_acquire_phy_lock(bp);
4141 bnx2x_handle_module_detect_int(&bp->link_params);
4142 bnx2x_release_phy_lock(bp);
4145 if (attn & HW_INTERRUT_ASSERT_SET_0) {
4147 val = REG_RD(bp, reg_offset);
4148 val &= ~(attn & HW_INTERRUT_ASSERT_SET_0);
4149 REG_WR(bp, reg_offset, val);
4151 BNX2X_ERR("FATAL HW block attention set0 0x%x\n",
4152 (u32)(attn & HW_INTERRUT_ASSERT_SET_0));
4157 static void bnx2x_attn_int_deasserted1(struct bnx2x *bp, u32 attn)
4161 if (attn & AEU_INPUTS_ATTN_BITS_DOORBELLQ_HW_INTERRUPT) {
4163 val = REG_RD(bp, DORQ_REG_DORQ_INT_STS_CLR);
4164 BNX2X_ERR("DB hw attention 0x%x\n", val);
4165 /* DORQ discard attention */
4167 BNX2X_ERR("FATAL error from DORQ\n");
4170 if (attn & HW_INTERRUT_ASSERT_SET_1) {
4172 int port = BP_PORT(bp);
4175 reg_offset = (port ? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_1 :
4176 MISC_REG_AEU_ENABLE1_FUNC_0_OUT_1);
4178 val = REG_RD(bp, reg_offset);
4179 val &= ~(attn & HW_INTERRUT_ASSERT_SET_1);
4180 REG_WR(bp, reg_offset, val);
4182 BNX2X_ERR("FATAL HW block attention set1 0x%x\n",
4183 (u32)(attn & HW_INTERRUT_ASSERT_SET_1));
4188 static void bnx2x_attn_int_deasserted2(struct bnx2x *bp, u32 attn)
4192 if (attn & AEU_INPUTS_ATTN_BITS_CFC_HW_INTERRUPT) {
4194 val = REG_RD(bp, CFC_REG_CFC_INT_STS_CLR);
4195 BNX2X_ERR("CFC hw attention 0x%x\n", val);
4196 /* CFC error attention */
4198 BNX2X_ERR("FATAL error from CFC\n");
4201 if (attn & AEU_INPUTS_ATTN_BITS_PXP_HW_INTERRUPT) {
4202 val = REG_RD(bp, PXP_REG_PXP_INT_STS_CLR_0);
4203 BNX2X_ERR("PXP hw attention-0 0x%x\n", val);
4204 /* RQ_USDMDP_FIFO_OVERFLOW */
4206 BNX2X_ERR("FATAL error from PXP\n");
4208 if (!CHIP_IS_E1x(bp)) {
4209 val = REG_RD(bp, PXP_REG_PXP_INT_STS_CLR_1);
4210 BNX2X_ERR("PXP hw attention-1 0x%x\n", val);
4214 if (attn & HW_INTERRUT_ASSERT_SET_2) {
4216 int port = BP_PORT(bp);
4219 reg_offset = (port ? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_2 :
4220 MISC_REG_AEU_ENABLE1_FUNC_0_OUT_2);
4222 val = REG_RD(bp, reg_offset);
4223 val &= ~(attn & HW_INTERRUT_ASSERT_SET_2);
4224 REG_WR(bp, reg_offset, val);
4226 BNX2X_ERR("FATAL HW block attention set2 0x%x\n",
4227 (u32)(attn & HW_INTERRUT_ASSERT_SET_2));
4232 static void bnx2x_attn_int_deasserted3(struct bnx2x *bp, u32 attn)
4236 if (attn & EVEREST_GEN_ATTN_IN_USE_MASK) {
4238 if (attn & BNX2X_PMF_LINK_ASSERT) {
4239 int func = BP_FUNC(bp);
4241 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_12 + func*4, 0);
4242 bnx2x_read_mf_cfg(bp);
4243 bp->mf_config[BP_VN(bp)] = MF_CFG_RD(bp,
4244 func_mf_config[BP_ABS_FUNC(bp)].config);
4246 func_mb[BP_FW_MB_IDX(bp)].drv_status);
4248 if (val & (DRV_STATUS_DCC_EVENT_MASK |
4249 DRV_STATUS_OEM_EVENT_MASK))
4251 (val & (DRV_STATUS_DCC_EVENT_MASK |
4252 DRV_STATUS_OEM_EVENT_MASK)));
4254 if (val & DRV_STATUS_SET_MF_BW)
4255 bnx2x_set_mf_bw(bp);
4257 if (val & DRV_STATUS_DRV_INFO_REQ)
4258 bnx2x_handle_drv_info_req(bp);
4260 if (val & DRV_STATUS_VF_DISABLED)
4261 bnx2x_schedule_iov_task(bp,
4262 BNX2X_IOV_HANDLE_FLR);
4264 if ((bp->port.pmf == 0) && (val & DRV_STATUS_PMF))
4265 bnx2x_pmf_update(bp);
4268 (val & DRV_STATUS_DCBX_NEGOTIATION_RESULTS) &&
4269 bp->dcbx_enabled > 0)
4270 /* start dcbx state machine */
4271 bnx2x_dcbx_set_params(bp,
4272 BNX2X_DCBX_STATE_NEG_RECEIVED);
4273 if (val & DRV_STATUS_AFEX_EVENT_MASK)
4274 bnx2x_handle_afex_cmd(bp,
4275 val & DRV_STATUS_AFEX_EVENT_MASK);
4276 if (val & DRV_STATUS_EEE_NEGOTIATION_RESULTS)
4277 bnx2x_handle_eee_event(bp);
4279 if (val & DRV_STATUS_OEM_UPDATE_SVID)
4280 bnx2x_handle_update_svid_cmd(bp);
4282 if (bp->link_vars.periodic_flags &
4283 PERIODIC_FLAGS_LINK_EVENT) {
4284 /* sync with link */
4285 bnx2x_acquire_phy_lock(bp);
4286 bp->link_vars.periodic_flags &=
4287 ~PERIODIC_FLAGS_LINK_EVENT;
4288 bnx2x_release_phy_lock(bp);
4290 bnx2x_link_sync_notify(bp);
4291 bnx2x_link_report(bp);
4293 /* Always call it here: bnx2x_link_report() will
4294 * prevent the link indication duplication.
4296 bnx2x__link_status_update(bp);
4297 } else if (attn & BNX2X_MC_ASSERT_BITS) {
4299 BNX2X_ERR("MC assert!\n");
4300 bnx2x_mc_assert(bp);
4301 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_10, 0);
4302 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_9, 0);
4303 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_8, 0);
4304 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_7, 0);
4307 } else if (attn & BNX2X_MCP_ASSERT) {
4309 BNX2X_ERR("MCP assert!\n");
4310 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_11, 0);
4314 BNX2X_ERR("Unknown HW assert! (attn 0x%x)\n", attn);
4317 if (attn & EVEREST_LATCHED_ATTN_IN_USE_MASK) {
4318 BNX2X_ERR("LATCHED attention 0x%08x (masked)\n", attn);
4319 if (attn & BNX2X_GRC_TIMEOUT) {
4320 val = CHIP_IS_E1(bp) ? 0 :
4321 REG_RD(bp, MISC_REG_GRC_TIMEOUT_ATTN);
4322 BNX2X_ERR("GRC time-out 0x%08x\n", val);
4324 if (attn & BNX2X_GRC_RSV) {
4325 val = CHIP_IS_E1(bp) ? 0 :
4326 REG_RD(bp, MISC_REG_GRC_RSV_ATTN);
4327 BNX2X_ERR("GRC reserved 0x%08x\n", val);
4329 REG_WR(bp, MISC_REG_AEU_CLR_LATCH_SIGNAL, 0x7ff);
4335 * 0-7 - Engine0 load counter.
4336 * 8-15 - Engine1 load counter.
4337 * 16 - Engine0 RESET_IN_PROGRESS bit.
4338 * 17 - Engine1 RESET_IN_PROGRESS bit.
4339 * 18 - Engine0 ONE_IS_LOADED. Set when there is at least one active function
4341 * 19 - Engine1 ONE_IS_LOADED.
4342 * 20 - Chip reset flow bit. When set none-leader must wait for both engines
4343 * leader to complete (check for both RESET_IN_PROGRESS bits and not for
4344 * just the one belonging to its engine).
4347 #define BNX2X_RECOVERY_GLOB_REG MISC_REG_GENERIC_POR_1
4349 #define BNX2X_PATH0_LOAD_CNT_MASK 0x000000ff
4350 #define BNX2X_PATH0_LOAD_CNT_SHIFT 0
4351 #define BNX2X_PATH1_LOAD_CNT_MASK 0x0000ff00
4352 #define BNX2X_PATH1_LOAD_CNT_SHIFT 8
4353 #define BNX2X_PATH0_RST_IN_PROG_BIT 0x00010000
4354 #define BNX2X_PATH1_RST_IN_PROG_BIT 0x00020000
4355 #define BNX2X_GLOBAL_RESET_BIT 0x00040000
4358 * Set the GLOBAL_RESET bit.
4360 * Should be run under rtnl lock
4362 void bnx2x_set_reset_global(struct bnx2x *bp)
4365 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG);
4366 val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG);
4367 REG_WR(bp, BNX2X_RECOVERY_GLOB_REG, val | BNX2X_GLOBAL_RESET_BIT);
4368 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG);
4372 * Clear the GLOBAL_RESET bit.
4374 * Should be run under rtnl lock
4376 static void bnx2x_clear_reset_global(struct bnx2x *bp)
4379 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG);
4380 val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG);
4381 REG_WR(bp, BNX2X_RECOVERY_GLOB_REG, val & (~BNX2X_GLOBAL_RESET_BIT));
4382 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG);
4386 * Checks the GLOBAL_RESET bit.
4388 * should be run under rtnl lock
4390 static bool bnx2x_reset_is_global(struct bnx2x *bp)
4392 u32 val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG);
4394 DP(NETIF_MSG_HW, "GEN_REG_VAL=0x%08x\n", val);
4395 return (val & BNX2X_GLOBAL_RESET_BIT) ? true : false;
4399 * Clear RESET_IN_PROGRESS bit for the current engine.
4401 * Should be run under rtnl lock
4403 static void bnx2x_set_reset_done(struct bnx2x *bp)
4406 u32 bit = BP_PATH(bp) ?
4407 BNX2X_PATH1_RST_IN_PROG_BIT : BNX2X_PATH0_RST_IN_PROG_BIT;
4408 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG);
4409 val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG);
4413 REG_WR(bp, BNX2X_RECOVERY_GLOB_REG, val);
4415 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG);
4419 * Set RESET_IN_PROGRESS for the current engine.
4421 * should be run under rtnl lock
4423 void bnx2x_set_reset_in_progress(struct bnx2x *bp)
4426 u32 bit = BP_PATH(bp) ?
4427 BNX2X_PATH1_RST_IN_PROG_BIT : BNX2X_PATH0_RST_IN_PROG_BIT;
4428 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG);
4429 val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG);
4433 REG_WR(bp, BNX2X_RECOVERY_GLOB_REG, val);
4434 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG);
4438 * Checks the RESET_IN_PROGRESS bit for the given engine.
4439 * should be run under rtnl lock
4441 bool bnx2x_reset_is_done(struct bnx2x *bp, int engine)
4443 u32 val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG);
4445 BNX2X_PATH1_RST_IN_PROG_BIT : BNX2X_PATH0_RST_IN_PROG_BIT;
4447 /* return false if bit is set */
4448 return (val & bit) ? false : true;
4452 * set pf load for the current pf.
4454 * should be run under rtnl lock
4456 void bnx2x_set_pf_load(struct bnx2x *bp)
4459 u32 mask = BP_PATH(bp) ? BNX2X_PATH1_LOAD_CNT_MASK :
4460 BNX2X_PATH0_LOAD_CNT_MASK;
4461 u32 shift = BP_PATH(bp) ? BNX2X_PATH1_LOAD_CNT_SHIFT :
4462 BNX2X_PATH0_LOAD_CNT_SHIFT;
4464 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG);
4465 val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG);
4467 DP(NETIF_MSG_IFUP, "Old GEN_REG_VAL=0x%08x\n", val);
4469 /* get the current counter value */
4470 val1 = (val & mask) >> shift;
4472 /* set bit of that PF */
4473 val1 |= (1 << bp->pf_num);
4475 /* clear the old value */
4478 /* set the new one */
4479 val |= ((val1 << shift) & mask);
4481 REG_WR(bp, BNX2X_RECOVERY_GLOB_REG, val);
4482 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG);
4486 * bnx2x_clear_pf_load - clear pf load mark
4488 * @bp: driver handle
4490 * Should be run under rtnl lock.
4491 * Decrements the load counter for the current engine. Returns
4492 * whether other functions are still loaded
4494 bool bnx2x_clear_pf_load(struct bnx2x *bp)
4497 u32 mask = BP_PATH(bp) ? BNX2X_PATH1_LOAD_CNT_MASK :
4498 BNX2X_PATH0_LOAD_CNT_MASK;
4499 u32 shift = BP_PATH(bp) ? BNX2X_PATH1_LOAD_CNT_SHIFT :
4500 BNX2X_PATH0_LOAD_CNT_SHIFT;
4502 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG);
4503 val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG);
4504 DP(NETIF_MSG_IFDOWN, "Old GEN_REG_VAL=0x%08x\n", val);
4506 /* get the current counter value */
4507 val1 = (val & mask) >> shift;
4509 /* clear bit of that PF */
4510 val1 &= ~(1 << bp->pf_num);
4512 /* clear the old value */
4515 /* set the new one */
4516 val |= ((val1 << shift) & mask);
4518 REG_WR(bp, BNX2X_RECOVERY_GLOB_REG, val);
4519 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG);
4524 * Read the load status for the current engine.
4526 * should be run under rtnl lock
4528 static bool bnx2x_get_load_status(struct bnx2x *bp, int engine)
4530 u32 mask = (engine ? BNX2X_PATH1_LOAD_CNT_MASK :
4531 BNX2X_PATH0_LOAD_CNT_MASK);
4532 u32 shift = (engine ? BNX2X_PATH1_LOAD_CNT_SHIFT :
4533 BNX2X_PATH0_LOAD_CNT_SHIFT);
4534 u32 val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG);
4536 DP(NETIF_MSG_HW | NETIF_MSG_IFUP, "GLOB_REG=0x%08x\n", val);
4538 val = (val & mask) >> shift;
4540 DP(NETIF_MSG_HW | NETIF_MSG_IFUP, "load mask for engine %d = 0x%x\n",
4546 static void _print_parity(struct bnx2x *bp, u32 reg)
4548 pr_cont(" [0x%08x] ", REG_RD(bp, reg));
4551 static void _print_next_block(int idx, const char *blk)
4553 pr_cont("%s%s", idx ? ", " : "", blk);
4556 static bool bnx2x_check_blocks_with_parity0(struct bnx2x *bp, u32 sig,
4557 int *par_num, bool print)
4565 for (i = 0; sig; i++) {
4566 cur_bit = (0x1UL << i);
4567 if (sig & cur_bit) {
4568 res |= true; /* Each bit is real error! */
4572 case AEU_INPUTS_ATTN_BITS_BRB_PARITY_ERROR:
4573 _print_next_block((*par_num)++, "BRB");
4575 BRB1_REG_BRB1_PRTY_STS);
4577 case AEU_INPUTS_ATTN_BITS_PARSER_PARITY_ERROR:
4578 _print_next_block((*par_num)++,
4580 _print_parity(bp, PRS_REG_PRS_PRTY_STS);
4582 case AEU_INPUTS_ATTN_BITS_TSDM_PARITY_ERROR:
4583 _print_next_block((*par_num)++, "TSDM");
4585 TSDM_REG_TSDM_PRTY_STS);
4587 case AEU_INPUTS_ATTN_BITS_SEARCHER_PARITY_ERROR:
4588 _print_next_block((*par_num)++,
4590 _print_parity(bp, SRC_REG_SRC_PRTY_STS);
4592 case AEU_INPUTS_ATTN_BITS_TCM_PARITY_ERROR:
4593 _print_next_block((*par_num)++, "TCM");
4594 _print_parity(bp, TCM_REG_TCM_PRTY_STS);
4596 case AEU_INPUTS_ATTN_BITS_TSEMI_PARITY_ERROR:
4597 _print_next_block((*par_num)++,
4600 TSEM_REG_TSEM_PRTY_STS_0);
4602 TSEM_REG_TSEM_PRTY_STS_1);
4604 case AEU_INPUTS_ATTN_BITS_PBCLIENT_PARITY_ERROR:
4605 _print_next_block((*par_num)++, "XPB");
4606 _print_parity(bp, GRCBASE_XPB +
4607 PB_REG_PB_PRTY_STS);
4620 static bool bnx2x_check_blocks_with_parity1(struct bnx2x *bp, u32 sig,
4621 int *par_num, bool *global,
4630 for (i = 0; sig; i++) {
4631 cur_bit = (0x1UL << i);
4632 if (sig & cur_bit) {
4633 res |= true; /* Each bit is real error! */
4635 case AEU_INPUTS_ATTN_BITS_PBF_PARITY_ERROR:
4637 _print_next_block((*par_num)++, "PBF");
4638 _print_parity(bp, PBF_REG_PBF_PRTY_STS);
4641 case AEU_INPUTS_ATTN_BITS_QM_PARITY_ERROR:
4643 _print_next_block((*par_num)++, "QM");
4644 _print_parity(bp, QM_REG_QM_PRTY_STS);
4647 case AEU_INPUTS_ATTN_BITS_TIMERS_PARITY_ERROR:
4649 _print_next_block((*par_num)++, "TM");
4650 _print_parity(bp, TM_REG_TM_PRTY_STS);
4653 case AEU_INPUTS_ATTN_BITS_XSDM_PARITY_ERROR:
4655 _print_next_block((*par_num)++, "XSDM");
4657 XSDM_REG_XSDM_PRTY_STS);
4660 case AEU_INPUTS_ATTN_BITS_XCM_PARITY_ERROR:
4662 _print_next_block((*par_num)++, "XCM");
4663 _print_parity(bp, XCM_REG_XCM_PRTY_STS);
4666 case AEU_INPUTS_ATTN_BITS_XSEMI_PARITY_ERROR:
4668 _print_next_block((*par_num)++,
4671 XSEM_REG_XSEM_PRTY_STS_0);
4673 XSEM_REG_XSEM_PRTY_STS_1);
4676 case AEU_INPUTS_ATTN_BITS_DOORBELLQ_PARITY_ERROR:
4678 _print_next_block((*par_num)++,
4681 DORQ_REG_DORQ_PRTY_STS);
4684 case AEU_INPUTS_ATTN_BITS_NIG_PARITY_ERROR:
4686 _print_next_block((*par_num)++, "NIG");
4687 if (CHIP_IS_E1x(bp)) {
4689 NIG_REG_NIG_PRTY_STS);
4692 NIG_REG_NIG_PRTY_STS_0);
4694 NIG_REG_NIG_PRTY_STS_1);
4698 case AEU_INPUTS_ATTN_BITS_VAUX_PCI_CORE_PARITY_ERROR:
4700 _print_next_block((*par_num)++,
4704 case AEU_INPUTS_ATTN_BITS_DEBUG_PARITY_ERROR:
4706 _print_next_block((*par_num)++,
4708 _print_parity(bp, DBG_REG_DBG_PRTY_STS);
4711 case AEU_INPUTS_ATTN_BITS_USDM_PARITY_ERROR:
4713 _print_next_block((*par_num)++, "USDM");
4715 USDM_REG_USDM_PRTY_STS);
4718 case AEU_INPUTS_ATTN_BITS_UCM_PARITY_ERROR:
4720 _print_next_block((*par_num)++, "UCM");
4721 _print_parity(bp, UCM_REG_UCM_PRTY_STS);
4724 case AEU_INPUTS_ATTN_BITS_USEMI_PARITY_ERROR:
4726 _print_next_block((*par_num)++,
4729 USEM_REG_USEM_PRTY_STS_0);
4731 USEM_REG_USEM_PRTY_STS_1);
4734 case AEU_INPUTS_ATTN_BITS_UPB_PARITY_ERROR:
4736 _print_next_block((*par_num)++, "UPB");
4737 _print_parity(bp, GRCBASE_UPB +
4738 PB_REG_PB_PRTY_STS);
4741 case AEU_INPUTS_ATTN_BITS_CSDM_PARITY_ERROR:
4743 _print_next_block((*par_num)++, "CSDM");
4745 CSDM_REG_CSDM_PRTY_STS);
4748 case AEU_INPUTS_ATTN_BITS_CCM_PARITY_ERROR:
4750 _print_next_block((*par_num)++, "CCM");
4751 _print_parity(bp, CCM_REG_CCM_PRTY_STS);
4764 static bool bnx2x_check_blocks_with_parity2(struct bnx2x *bp, u32 sig,
4765 int *par_num, bool print)
4773 for (i = 0; sig; i++) {
4774 cur_bit = (0x1UL << i);
4775 if (sig & cur_bit) {
4776 res = true; /* Each bit is real error! */
4779 case AEU_INPUTS_ATTN_BITS_CSEMI_PARITY_ERROR:
4780 _print_next_block((*par_num)++,
4783 CSEM_REG_CSEM_PRTY_STS_0);
4785 CSEM_REG_CSEM_PRTY_STS_1);
4787 case AEU_INPUTS_ATTN_BITS_PXP_PARITY_ERROR:
4788 _print_next_block((*par_num)++, "PXP");
4789 _print_parity(bp, PXP_REG_PXP_PRTY_STS);
4791 PXP2_REG_PXP2_PRTY_STS_0);
4793 PXP2_REG_PXP2_PRTY_STS_1);
4795 case AEU_IN_ATTN_BITS_PXPPCICLOCKCLIENT_PARITY_ERROR:
4796 _print_next_block((*par_num)++,
4797 "PXPPCICLOCKCLIENT");
4799 case AEU_INPUTS_ATTN_BITS_CFC_PARITY_ERROR:
4800 _print_next_block((*par_num)++, "CFC");
4802 CFC_REG_CFC_PRTY_STS);
4804 case AEU_INPUTS_ATTN_BITS_CDU_PARITY_ERROR:
4805 _print_next_block((*par_num)++, "CDU");
4806 _print_parity(bp, CDU_REG_CDU_PRTY_STS);
4808 case AEU_INPUTS_ATTN_BITS_DMAE_PARITY_ERROR:
4809 _print_next_block((*par_num)++, "DMAE");
4811 DMAE_REG_DMAE_PRTY_STS);
4813 case AEU_INPUTS_ATTN_BITS_IGU_PARITY_ERROR:
4814 _print_next_block((*par_num)++, "IGU");
4815 if (CHIP_IS_E1x(bp))
4817 HC_REG_HC_PRTY_STS);
4820 IGU_REG_IGU_PRTY_STS);
4822 case AEU_INPUTS_ATTN_BITS_MISC_PARITY_ERROR:
4823 _print_next_block((*par_num)++, "MISC");
4825 MISC_REG_MISC_PRTY_STS);
4838 static bool bnx2x_check_blocks_with_parity3(struct bnx2x *bp, u32 sig,
4839 int *par_num, bool *global,
4846 for (i = 0; sig; i++) {
4847 cur_bit = (0x1UL << i);
4848 if (sig & cur_bit) {
4850 case AEU_INPUTS_ATTN_BITS_MCP_LATCHED_ROM_PARITY:
4852 _print_next_block((*par_num)++,
4857 case AEU_INPUTS_ATTN_BITS_MCP_LATCHED_UMP_RX_PARITY:
4859 _print_next_block((*par_num)++,
4864 case AEU_INPUTS_ATTN_BITS_MCP_LATCHED_UMP_TX_PARITY:
4866 _print_next_block((*par_num)++,
4871 case AEU_INPUTS_ATTN_BITS_MCP_LATCHED_SCPAD_PARITY:
4873 /* clear latched SCPAD PATIRY from MCP */
4874 REG_WR(bp, MISC_REG_AEU_CLR_LATCH_SIGNAL,
4887 static bool bnx2x_check_blocks_with_parity4(struct bnx2x *bp, u32 sig,
4888 int *par_num, bool print)
4896 for (i = 0; sig; i++) {
4897 cur_bit = (0x1UL << i);
4898 if (sig & cur_bit) {
4899 res = true; /* Each bit is real error! */
4902 case AEU_INPUTS_ATTN_BITS_PGLUE_PARITY_ERROR:
4903 _print_next_block((*par_num)++,
4906 PGLUE_B_REG_PGLUE_B_PRTY_STS);
4908 case AEU_INPUTS_ATTN_BITS_ATC_PARITY_ERROR:
4909 _print_next_block((*par_num)++, "ATC");
4911 ATC_REG_ATC_PRTY_STS);
4923 static bool bnx2x_parity_attn(struct bnx2x *bp, bool *global, bool print,
4928 if ((sig[0] & HW_PRTY_ASSERT_SET_0) ||
4929 (sig[1] & HW_PRTY_ASSERT_SET_1) ||
4930 (sig[2] & HW_PRTY_ASSERT_SET_2) ||
4931 (sig[3] & HW_PRTY_ASSERT_SET_3) ||
4932 (sig[4] & HW_PRTY_ASSERT_SET_4)) {
4935 DP(NETIF_MSG_HW, "Was parity error: HW block parity attention:\n"
4936 "[0]:0x%08x [1]:0x%08x [2]:0x%08x [3]:0x%08x [4]:0x%08x\n",
4937 sig[0] & HW_PRTY_ASSERT_SET_0,
4938 sig[1] & HW_PRTY_ASSERT_SET_1,
4939 sig[2] & HW_PRTY_ASSERT_SET_2,
4940 sig[3] & HW_PRTY_ASSERT_SET_3,
4941 sig[4] & HW_PRTY_ASSERT_SET_4);
4943 if (((sig[0] & HW_PRTY_ASSERT_SET_0) ||
4944 (sig[1] & HW_PRTY_ASSERT_SET_1) ||
4945 (sig[2] & HW_PRTY_ASSERT_SET_2) ||
4946 (sig[4] & HW_PRTY_ASSERT_SET_4)) ||
4947 (sig[3] & HW_PRTY_ASSERT_SET_3_WITHOUT_SCPAD)) {
4949 "Parity errors detected in blocks: ");
4954 res |= bnx2x_check_blocks_with_parity0(bp,
4955 sig[0] & HW_PRTY_ASSERT_SET_0, &par_num, print);
4956 res |= bnx2x_check_blocks_with_parity1(bp,
4957 sig[1] & HW_PRTY_ASSERT_SET_1, &par_num, global, print);
4958 res |= bnx2x_check_blocks_with_parity2(bp,
4959 sig[2] & HW_PRTY_ASSERT_SET_2, &par_num, print);
4960 res |= bnx2x_check_blocks_with_parity3(bp,
4961 sig[3] & HW_PRTY_ASSERT_SET_3, &par_num, global, print);
4962 res |= bnx2x_check_blocks_with_parity4(bp,
4963 sig[4] & HW_PRTY_ASSERT_SET_4, &par_num, print);
4973 * bnx2x_chk_parity_attn - checks for parity attentions.
4975 * @bp: driver handle
4976 * @global: true if there was a global attention
4977 * @print: show parity attention in syslog
4979 bool bnx2x_chk_parity_attn(struct bnx2x *bp, bool *global, bool print)
4981 struct attn_route attn = { {0} };
4982 int port = BP_PORT(bp);
4984 attn.sig[0] = REG_RD(bp,
4985 MISC_REG_AEU_AFTER_INVERT_1_FUNC_0 +
4987 attn.sig[1] = REG_RD(bp,
4988 MISC_REG_AEU_AFTER_INVERT_2_FUNC_0 +
4990 attn.sig[2] = REG_RD(bp,
4991 MISC_REG_AEU_AFTER_INVERT_3_FUNC_0 +
4993 attn.sig[3] = REG_RD(bp,
4994 MISC_REG_AEU_AFTER_INVERT_4_FUNC_0 +
4996 /* Since MCP attentions can't be disabled inside the block, we need to
4997 * read AEU registers to see whether they're currently disabled
4999 attn.sig[3] &= ((REG_RD(bp,
5000 !port ? MISC_REG_AEU_ENABLE4_FUNC_0_OUT_0
5001 : MISC_REG_AEU_ENABLE4_FUNC_1_OUT_0) &
5002 MISC_AEU_ENABLE_MCP_PRTY_BITS) |
5003 ~MISC_AEU_ENABLE_MCP_PRTY_BITS);
5005 if (!CHIP_IS_E1x(bp))
5006 attn.sig[4] = REG_RD(bp,
5007 MISC_REG_AEU_AFTER_INVERT_5_FUNC_0 +
5010 return bnx2x_parity_attn(bp, global, print, attn.sig);
5013 static void bnx2x_attn_int_deasserted4(struct bnx2x *bp, u32 attn)
5016 if (attn & AEU_INPUTS_ATTN_BITS_PGLUE_HW_INTERRUPT) {
5018 val = REG_RD(bp, PGLUE_B_REG_PGLUE_B_INT_STS_CLR);
5019 BNX2X_ERR("PGLUE hw attention 0x%x\n", val);
5020 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_ADDRESS_ERROR)
5021 BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_ADDRESS_ERROR\n");
5022 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_INCORRECT_RCV_BEHAVIOR)
5023 BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_INCORRECT_RCV_BEHAVIOR\n");
5024 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_WAS_ERROR_ATTN)
5025 BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_WAS_ERROR_ATTN\n");
5026 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_VF_LENGTH_VIOLATION_ATTN)
5027 BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_VF_LENGTH_VIOLATION_ATTN\n");
5029 PGLUE_B_PGLUE_B_INT_STS_REG_VF_GRC_SPACE_VIOLATION_ATTN)
5030 BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_VF_GRC_SPACE_VIOLATION_ATTN\n");
5032 PGLUE_B_PGLUE_B_INT_STS_REG_VF_MSIX_BAR_VIOLATION_ATTN)
5033 BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_VF_MSIX_BAR_VIOLATION_ATTN\n");
5034 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_TCPL_ERROR_ATTN)
5035 BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_TCPL_ERROR_ATTN\n");
5036 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_TCPL_IN_TWO_RCBS_ATTN)
5037 BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_TCPL_IN_TWO_RCBS_ATTN\n");
5038 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_CSSNOOP_FIFO_OVERFLOW)
5039 BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_CSSNOOP_FIFO_OVERFLOW\n");
5041 if (attn & AEU_INPUTS_ATTN_BITS_ATC_HW_INTERRUPT) {
5042 val = REG_RD(bp, ATC_REG_ATC_INT_STS_CLR);
5043 BNX2X_ERR("ATC hw attention 0x%x\n", val);
5044 if (val & ATC_ATC_INT_STS_REG_ADDRESS_ERROR)
5045 BNX2X_ERR("ATC_ATC_INT_STS_REG_ADDRESS_ERROR\n");
5046 if (val & ATC_ATC_INT_STS_REG_ATC_TCPL_TO_NOT_PEND)
5047 BNX2X_ERR("ATC_ATC_INT_STS_REG_ATC_TCPL_TO_NOT_PEND\n");
5048 if (val & ATC_ATC_INT_STS_REG_ATC_GPA_MULTIPLE_HITS)
5049 BNX2X_ERR("ATC_ATC_INT_STS_REG_ATC_GPA_MULTIPLE_HITS\n");
5050 if (val & ATC_ATC_INT_STS_REG_ATC_RCPL_TO_EMPTY_CNT)
5051 BNX2X_ERR("ATC_ATC_INT_STS_REG_ATC_RCPL_TO_EMPTY_CNT\n");
5052 if (val & ATC_ATC_INT_STS_REG_ATC_TCPL_ERROR)
5053 BNX2X_ERR("ATC_ATC_INT_STS_REG_ATC_TCPL_ERROR\n");
5054 if (val & ATC_ATC_INT_STS_REG_ATC_IREQ_LESS_THAN_STU)
5055 BNX2X_ERR("ATC_ATC_INT_STS_REG_ATC_IREQ_LESS_THAN_STU\n");
5058 if (attn & (AEU_INPUTS_ATTN_BITS_PGLUE_PARITY_ERROR |
5059 AEU_INPUTS_ATTN_BITS_ATC_PARITY_ERROR)) {
5060 BNX2X_ERR("FATAL parity attention set4 0x%x\n",
5061 (u32)(attn & (AEU_INPUTS_ATTN_BITS_PGLUE_PARITY_ERROR |
5062 AEU_INPUTS_ATTN_BITS_ATC_PARITY_ERROR)));
5066 static void bnx2x_attn_int_deasserted(struct bnx2x *bp, u32 deasserted)
5068 struct attn_route attn, *group_mask;
5069 int port = BP_PORT(bp);
5074 bool global = false;
5076 /* need to take HW lock because MCP or other port might also
5077 try to handle this event */
5078 bnx2x_acquire_alr(bp);
5080 if (bnx2x_chk_parity_attn(bp, &global, true)) {
5081 #ifndef BNX2X_STOP_ON_ERROR
5082 bp->recovery_state = BNX2X_RECOVERY_INIT;
5083 schedule_delayed_work(&bp->sp_rtnl_task, 0);
5084 /* Disable HW interrupts */
5085 bnx2x_int_disable(bp);
5086 /* In case of parity errors don't handle attentions so that
5087 * other function would "see" parity errors.
5092 bnx2x_release_alr(bp);
5096 attn.sig[0] = REG_RD(bp, MISC_REG_AEU_AFTER_INVERT_1_FUNC_0 + port*4);
5097 attn.sig[1] = REG_RD(bp, MISC_REG_AEU_AFTER_INVERT_2_FUNC_0 + port*4);
5098 attn.sig[2] = REG_RD(bp, MISC_REG_AEU_AFTER_INVERT_3_FUNC_0 + port*4);
5099 attn.sig[3] = REG_RD(bp, MISC_REG_AEU_AFTER_INVERT_4_FUNC_0 + port*4);
5100 if (!CHIP_IS_E1x(bp))
5102 REG_RD(bp, MISC_REG_AEU_AFTER_INVERT_5_FUNC_0 + port*4);
5106 DP(NETIF_MSG_HW, "attn: %08x %08x %08x %08x %08x\n",
5107 attn.sig[0], attn.sig[1], attn.sig[2], attn.sig[3], attn.sig[4]);
5109 for (index = 0; index < MAX_DYNAMIC_ATTN_GRPS; index++) {
5110 if (deasserted & (1 << index)) {
5111 group_mask = &bp->attn_group[index];
5113 DP(NETIF_MSG_HW, "group[%d]: %08x %08x %08x %08x %08x\n",
5115 group_mask->sig[0], group_mask->sig[1],
5116 group_mask->sig[2], group_mask->sig[3],
5117 group_mask->sig[4]);
5119 bnx2x_attn_int_deasserted4(bp,
5120 attn.sig[4] & group_mask->sig[4]);
5121 bnx2x_attn_int_deasserted3(bp,
5122 attn.sig[3] & group_mask->sig[3]);
5123 bnx2x_attn_int_deasserted1(bp,
5124 attn.sig[1] & group_mask->sig[1]);
5125 bnx2x_attn_int_deasserted2(bp,
5126 attn.sig[2] & group_mask->sig[2]);
5127 bnx2x_attn_int_deasserted0(bp,
5128 attn.sig[0] & group_mask->sig[0]);
5132 bnx2x_release_alr(bp);
5134 if (bp->common.int_block == INT_BLOCK_HC)
5135 reg_addr = (HC_REG_COMMAND_REG + port*32 +
5136 COMMAND_REG_ATTN_BITS_CLR);
5138 reg_addr = (BAR_IGU_INTMEM + IGU_CMD_ATTN_BIT_CLR_UPPER*8);
5141 DP(NETIF_MSG_HW, "about to mask 0x%08x at %s addr 0x%x\n", val,
5142 (bp->common.int_block == INT_BLOCK_HC) ? "HC" : "IGU", reg_addr);
5143 REG_WR(bp, reg_addr, val);
5145 if (~bp->attn_state & deasserted)
5146 BNX2X_ERR("IGU ERROR\n");
5148 reg_addr = port ? MISC_REG_AEU_MASK_ATTN_FUNC_1 :
5149 MISC_REG_AEU_MASK_ATTN_FUNC_0;
5151 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_PORT0_ATT_MASK + port);
5152 aeu_mask = REG_RD(bp, reg_addr);
5154 DP(NETIF_MSG_HW, "aeu_mask %x newly deasserted %x\n",
5155 aeu_mask, deasserted);
5156 aeu_mask |= (deasserted & 0x3ff);
5157 DP(NETIF_MSG_HW, "new mask %x\n", aeu_mask);
5159 REG_WR(bp, reg_addr, aeu_mask);
5160 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_PORT0_ATT_MASK + port);
5162 DP(NETIF_MSG_HW, "attn_state %x\n", bp->attn_state);
5163 bp->attn_state &= ~deasserted;
5164 DP(NETIF_MSG_HW, "new state %x\n", bp->attn_state);
5167 static void bnx2x_attn_int(struct bnx2x *bp)
5169 /* read local copy of bits */
5170 u32 attn_bits = le32_to_cpu(bp->def_status_blk->atten_status_block.
5172 u32 attn_ack = le32_to_cpu(bp->def_status_blk->atten_status_block.
5174 u32 attn_state = bp->attn_state;
5176 /* look for changed bits */
5177 u32 asserted = attn_bits & ~attn_ack & ~attn_state;
5178 u32 deasserted = ~attn_bits & attn_ack & attn_state;
5181 "attn_bits %x attn_ack %x asserted %x deasserted %x\n",
5182 attn_bits, attn_ack, asserted, deasserted);
5184 if (~(attn_bits ^ attn_ack) & (attn_bits ^ attn_state))
5185 BNX2X_ERR("BAD attention state\n");
5187 /* handle bits that were raised */
5189 bnx2x_attn_int_asserted(bp, asserted);
5192 bnx2x_attn_int_deasserted(bp, deasserted);
5195 void bnx2x_igu_ack_sb(struct bnx2x *bp, u8 igu_sb_id, u8 segment,
5196 u16 index, u8 op, u8 update)
5198 u32 igu_addr = bp->igu_base_addr;
5199 igu_addr += (IGU_CMD_INT_ACK_BASE + igu_sb_id)*8;
5200 bnx2x_igu_ack_sb_gen(bp, igu_sb_id, segment, index, op, update,
5204 static void bnx2x_update_eq_prod(struct bnx2x *bp, u16 prod)
5206 /* No memory barriers */
5207 storm_memset_eq_prod(bp, prod, BP_FUNC(bp));
5208 mmiowb(); /* keep prod updates ordered */
5211 static int bnx2x_cnic_handle_cfc_del(struct bnx2x *bp, u32 cid,
5212 union event_ring_elem *elem)
5214 u8 err = elem->message.error;
5216 if (!bp->cnic_eth_dev.starting_cid ||
5217 (cid < bp->cnic_eth_dev.starting_cid &&
5218 cid != bp->cnic_eth_dev.iscsi_l2_cid))
5221 DP(BNX2X_MSG_SP, "got delete ramrod for CNIC CID %d\n", cid);
5223 if (unlikely(err)) {
5225 BNX2X_ERR("got delete ramrod for CNIC CID %d with error!\n",
5227 bnx2x_panic_dump(bp, false);
5229 bnx2x_cnic_cfc_comp(bp, cid, err);
5233 static void bnx2x_handle_mcast_eqe(struct bnx2x *bp)
5235 struct bnx2x_mcast_ramrod_params rparam;
5238 memset(&rparam, 0, sizeof(rparam));
5240 rparam.mcast_obj = &bp->mcast_obj;
5242 netif_addr_lock_bh(bp->dev);
5244 /* Clear pending state for the last command */
5245 bp->mcast_obj.raw.clear_pending(&bp->mcast_obj.raw);
5247 /* If there are pending mcast commands - send them */
5248 if (bp->mcast_obj.check_pending(&bp->mcast_obj)) {
5249 rc = bnx2x_config_mcast(bp, &rparam, BNX2X_MCAST_CMD_CONT);
5251 BNX2X_ERR("Failed to send pending mcast commands: %d\n",
5255 netif_addr_unlock_bh(bp->dev);
5258 static void bnx2x_handle_classification_eqe(struct bnx2x *bp,
5259 union event_ring_elem *elem)
5261 unsigned long ramrod_flags = 0;
5263 u32 cid = elem->message.data.eth_event.echo & BNX2X_SWCID_MASK;
5264 struct bnx2x_vlan_mac_obj *vlan_mac_obj;
5266 /* Always push next commands out, don't wait here */
5267 __set_bit(RAMROD_CONT, &ramrod_flags);
5269 switch (le32_to_cpu((__force __le32)elem->message.data.eth_event.echo)
5270 >> BNX2X_SWCID_SHIFT) {
5271 case BNX2X_FILTER_MAC_PENDING:
5272 DP(BNX2X_MSG_SP, "Got SETUP_MAC completions\n");
5273 if (CNIC_LOADED(bp) && (cid == BNX2X_ISCSI_ETH_CID(bp)))
5274 vlan_mac_obj = &bp->iscsi_l2_mac_obj;
5276 vlan_mac_obj = &bp->sp_objs[cid].mac_obj;
5279 case BNX2X_FILTER_MCAST_PENDING:
5280 DP(BNX2X_MSG_SP, "Got SETUP_MCAST completions\n");
5281 /* This is only relevant for 57710 where multicast MACs are
5282 * configured as unicast MACs using the same ramrod.
5284 bnx2x_handle_mcast_eqe(bp);
5287 BNX2X_ERR("Unsupported classification command: %d\n",
5288 elem->message.data.eth_event.echo);
5292 rc = vlan_mac_obj->complete(bp, vlan_mac_obj, elem, &ramrod_flags);
5295 BNX2X_ERR("Failed to schedule new commands: %d\n", rc);
5297 DP(BNX2X_MSG_SP, "Scheduled next pending commands...\n");
5300 static void bnx2x_set_iscsi_eth_rx_mode(struct bnx2x *bp, bool start);
5302 static void bnx2x_handle_rx_mode_eqe(struct bnx2x *bp)
5304 netif_addr_lock_bh(bp->dev);
5306 clear_bit(BNX2X_FILTER_RX_MODE_PENDING, &bp->sp_state);
5308 /* Send rx_mode command again if was requested */
5309 if (test_and_clear_bit(BNX2X_FILTER_RX_MODE_SCHED, &bp->sp_state))
5310 bnx2x_set_storm_rx_mode(bp);
5311 else if (test_and_clear_bit(BNX2X_FILTER_ISCSI_ETH_START_SCHED,
5313 bnx2x_set_iscsi_eth_rx_mode(bp, true);
5314 else if (test_and_clear_bit(BNX2X_FILTER_ISCSI_ETH_STOP_SCHED,
5316 bnx2x_set_iscsi_eth_rx_mode(bp, false);
5318 netif_addr_unlock_bh(bp->dev);
5321 static void bnx2x_after_afex_vif_lists(struct bnx2x *bp,
5322 union event_ring_elem *elem)
5324 if (elem->message.data.vif_list_event.echo == VIF_LIST_RULE_GET) {
5326 "afex: ramrod completed VIF LIST_GET, addrs 0x%x\n",
5327 elem->message.data.vif_list_event.func_bit_map);
5328 bnx2x_fw_command(bp, DRV_MSG_CODE_AFEX_LISTGET_ACK,
5329 elem->message.data.vif_list_event.func_bit_map);
5330 } else if (elem->message.data.vif_list_event.echo ==
5331 VIF_LIST_RULE_SET) {
5332 DP(BNX2X_MSG_SP, "afex: ramrod completed VIF LIST_SET\n");
5333 bnx2x_fw_command(bp, DRV_MSG_CODE_AFEX_LISTSET_ACK, 0);
5337 /* called with rtnl_lock */
5338 static void bnx2x_after_function_update(struct bnx2x *bp)
5341 struct bnx2x_fastpath *fp;
5342 struct bnx2x_queue_state_params queue_params = {NULL};
5343 struct bnx2x_queue_update_params *q_update_params =
5344 &queue_params.params.update;
5346 /* Send Q update command with afex vlan removal values for all Qs */
5347 queue_params.cmd = BNX2X_Q_CMD_UPDATE;
5349 /* set silent vlan removal values according to vlan mode */
5350 __set_bit(BNX2X_Q_UPDATE_SILENT_VLAN_REM_CHNG,
5351 &q_update_params->update_flags);
5352 __set_bit(BNX2X_Q_UPDATE_SILENT_VLAN_REM,
5353 &q_update_params->update_flags);
5354 __set_bit(RAMROD_COMP_WAIT, &queue_params.ramrod_flags);
5356 /* in access mode mark mask and value are 0 to strip all vlans */
5357 if (bp->afex_vlan_mode == FUNC_MF_CFG_AFEX_VLAN_ACCESS_MODE) {
5358 q_update_params->silent_removal_value = 0;
5359 q_update_params->silent_removal_mask = 0;
5361 q_update_params->silent_removal_value =
5362 (bp->afex_def_vlan_tag & VLAN_VID_MASK);
5363 q_update_params->silent_removal_mask = VLAN_VID_MASK;
5366 for_each_eth_queue(bp, q) {
5367 /* Set the appropriate Queue object */
5369 queue_params.q_obj = &bnx2x_sp_obj(bp, fp).q_obj;
5371 /* send the ramrod */
5372 rc = bnx2x_queue_state_change(bp, &queue_params);
5374 BNX2X_ERR("Failed to config silent vlan rem for Q %d\n",
5378 if (!NO_FCOE(bp) && CNIC_ENABLED(bp)) {
5379 fp = &bp->fp[FCOE_IDX(bp)];
5380 queue_params.q_obj = &bnx2x_sp_obj(bp, fp).q_obj;
5382 /* clear pending completion bit */
5383 __clear_bit(RAMROD_COMP_WAIT, &queue_params.ramrod_flags);
5385 /* mark latest Q bit */
5386 smp_mb__before_atomic();
5387 set_bit(BNX2X_AFEX_FCOE_Q_UPDATE_PENDING, &bp->sp_state);
5388 smp_mb__after_atomic();
5390 /* send Q update ramrod for FCoE Q */
5391 rc = bnx2x_queue_state_change(bp, &queue_params);
5393 BNX2X_ERR("Failed to config silent vlan rem for Q %d\n",
5396 /* If no FCoE ring - ACK MCP now */
5397 bnx2x_link_report(bp);
5398 bnx2x_fw_command(bp, DRV_MSG_CODE_AFEX_VIFSET_ACK, 0);
5402 static struct bnx2x_queue_sp_obj *bnx2x_cid_to_q_obj(
5403 struct bnx2x *bp, u32 cid)
5405 DP(BNX2X_MSG_SP, "retrieving fp from cid %d\n", cid);
5407 if (CNIC_LOADED(bp) && (cid == BNX2X_FCOE_ETH_CID(bp)))
5408 return &bnx2x_fcoe_sp_obj(bp, q_obj);
5410 return &bp->sp_objs[CID_TO_FP(cid, bp)].q_obj;
5413 static void bnx2x_eq_int(struct bnx2x *bp)
5415 u16 hw_cons, sw_cons, sw_prod;
5416 union event_ring_elem *elem;
5420 int rc, spqe_cnt = 0;
5421 struct bnx2x_queue_sp_obj *q_obj;
5422 struct bnx2x_func_sp_obj *f_obj = &bp->func_obj;
5423 struct bnx2x_raw_obj *rss_raw = &bp->rss_conf_obj.raw;
5425 hw_cons = le16_to_cpu(*bp->eq_cons_sb);
5427 /* The hw_cos range is 1-255, 257 - the sw_cons range is 0-254, 256.
5428 * when we get the next-page we need to adjust so the loop
5429 * condition below will be met. The next element is the size of a
5430 * regular element and hence incrementing by 1
5432 if ((hw_cons & EQ_DESC_MAX_PAGE) == EQ_DESC_MAX_PAGE)
5435 /* This function may never run in parallel with itself for a
5436 * specific bp, thus there is no need in "paired" read memory
5439 sw_cons = bp->eq_cons;
5440 sw_prod = bp->eq_prod;
5442 DP(BNX2X_MSG_SP, "EQ: hw_cons %u sw_cons %u bp->eq_spq_left %x\n",
5443 hw_cons, sw_cons, atomic_read(&bp->eq_spq_left));
5445 for (; sw_cons != hw_cons;
5446 sw_prod = NEXT_EQ_IDX(sw_prod), sw_cons = NEXT_EQ_IDX(sw_cons)) {
5448 elem = &bp->eq_ring[EQ_DESC(sw_cons)];
5450 rc = bnx2x_iov_eq_sp_event(bp, elem);
5452 DP(BNX2X_MSG_IOV, "bnx2x_iov_eq_sp_event returned %d\n",
5457 /* elem CID originates from FW; actually LE */
5458 cid = SW_CID((__force __le32)
5459 elem->message.data.cfc_del_event.cid);
5460 opcode = elem->message.opcode;
5462 /* handle eq element */
5464 case EVENT_RING_OPCODE_VF_PF_CHANNEL:
5465 bnx2x_vf_mbx_schedule(bp,
5466 &elem->message.data.vf_pf_event);
5469 case EVENT_RING_OPCODE_STAT_QUERY:
5470 DP_AND((BNX2X_MSG_SP | BNX2X_MSG_STATS),
5471 "got statistics comp event %d\n",
5473 /* nothing to do with stats comp */
5476 case EVENT_RING_OPCODE_CFC_DEL:
5477 /* handle according to cid range */
5479 * we may want to verify here that the bp state is
5483 "got delete ramrod for MULTI[%d]\n", cid);
5485 if (CNIC_LOADED(bp) &&
5486 !bnx2x_cnic_handle_cfc_del(bp, cid, elem))
5489 q_obj = bnx2x_cid_to_q_obj(bp, cid);
5491 if (q_obj->complete_cmd(bp, q_obj, BNX2X_Q_CMD_CFC_DEL))
5496 case EVENT_RING_OPCODE_STOP_TRAFFIC:
5497 DP(BNX2X_MSG_SP | BNX2X_MSG_DCB, "got STOP TRAFFIC\n");
5498 bnx2x_dcbx_set_params(bp, BNX2X_DCBX_STATE_TX_PAUSED);
5499 if (f_obj->complete_cmd(bp, f_obj,
5500 BNX2X_F_CMD_TX_STOP))
5504 case EVENT_RING_OPCODE_START_TRAFFIC:
5505 DP(BNX2X_MSG_SP | BNX2X_MSG_DCB, "got START TRAFFIC\n");
5506 bnx2x_dcbx_set_params(bp, BNX2X_DCBX_STATE_TX_RELEASED);
5507 if (f_obj->complete_cmd(bp, f_obj,
5508 BNX2X_F_CMD_TX_START))
5512 case EVENT_RING_OPCODE_FUNCTION_UPDATE:
5513 echo = elem->message.data.function_update_event.echo;
5514 if (echo == SWITCH_UPDATE) {
5515 DP(BNX2X_MSG_SP | NETIF_MSG_IFUP,
5516 "got FUNC_SWITCH_UPDATE ramrod\n");
5517 if (f_obj->complete_cmd(
5518 bp, f_obj, BNX2X_F_CMD_SWITCH_UPDATE))
5522 int cmd = BNX2X_SP_RTNL_AFEX_F_UPDATE;
5524 DP(BNX2X_MSG_SP | BNX2X_MSG_MCP,
5525 "AFEX: ramrod completed FUNCTION_UPDATE\n");
5526 f_obj->complete_cmd(bp, f_obj,
5527 BNX2X_F_CMD_AFEX_UPDATE);
5529 /* We will perform the Queues update from
5530 * sp_rtnl task as all Queue SP operations
5531 * should run under rtnl_lock.
5533 bnx2x_schedule_sp_rtnl(bp, cmd, 0);
5538 case EVENT_RING_OPCODE_AFEX_VIF_LISTS:
5539 f_obj->complete_cmd(bp, f_obj,
5540 BNX2X_F_CMD_AFEX_VIFLISTS);
5541 bnx2x_after_afex_vif_lists(bp, elem);
5543 case EVENT_RING_OPCODE_FUNCTION_START:
5544 DP(BNX2X_MSG_SP | NETIF_MSG_IFUP,
5545 "got FUNC_START ramrod\n");
5546 if (f_obj->complete_cmd(bp, f_obj, BNX2X_F_CMD_START))
5551 case EVENT_RING_OPCODE_FUNCTION_STOP:
5552 DP(BNX2X_MSG_SP | NETIF_MSG_IFUP,
5553 "got FUNC_STOP ramrod\n");
5554 if (f_obj->complete_cmd(bp, f_obj, BNX2X_F_CMD_STOP))
5559 case EVENT_RING_OPCODE_SET_TIMESYNC:
5560 DP(BNX2X_MSG_SP | BNX2X_MSG_PTP,
5561 "got set_timesync ramrod completion\n");
5562 if (f_obj->complete_cmd(bp, f_obj,
5563 BNX2X_F_CMD_SET_TIMESYNC))
5568 switch (opcode | bp->state) {
5569 case (EVENT_RING_OPCODE_RSS_UPDATE_RULES |
5571 case (EVENT_RING_OPCODE_RSS_UPDATE_RULES |
5572 BNX2X_STATE_OPENING_WAIT4_PORT):
5573 case (EVENT_RING_OPCODE_RSS_UPDATE_RULES |
5574 BNX2X_STATE_CLOSING_WAIT4_HALT):
5575 cid = elem->message.data.eth_event.echo &
5577 DP(BNX2X_MSG_SP, "got RSS_UPDATE ramrod. CID %d\n",
5579 rss_raw->clear_pending(rss_raw);
5582 case (EVENT_RING_OPCODE_SET_MAC | BNX2X_STATE_OPEN):
5583 case (EVENT_RING_OPCODE_SET_MAC | BNX2X_STATE_DIAG):
5584 case (EVENT_RING_OPCODE_SET_MAC |
5585 BNX2X_STATE_CLOSING_WAIT4_HALT):
5586 case (EVENT_RING_OPCODE_CLASSIFICATION_RULES |
5588 case (EVENT_RING_OPCODE_CLASSIFICATION_RULES |
5590 case (EVENT_RING_OPCODE_CLASSIFICATION_RULES |
5591 BNX2X_STATE_CLOSING_WAIT4_HALT):
5592 DP(BNX2X_MSG_SP, "got (un)set mac ramrod\n");
5593 bnx2x_handle_classification_eqe(bp, elem);
5596 case (EVENT_RING_OPCODE_MULTICAST_RULES |
5598 case (EVENT_RING_OPCODE_MULTICAST_RULES |
5600 case (EVENT_RING_OPCODE_MULTICAST_RULES |
5601 BNX2X_STATE_CLOSING_WAIT4_HALT):
5602 DP(BNX2X_MSG_SP, "got mcast ramrod\n");
5603 bnx2x_handle_mcast_eqe(bp);
5606 case (EVENT_RING_OPCODE_FILTERS_RULES |
5608 case (EVENT_RING_OPCODE_FILTERS_RULES |
5610 case (EVENT_RING_OPCODE_FILTERS_RULES |
5611 BNX2X_STATE_CLOSING_WAIT4_HALT):
5612 DP(BNX2X_MSG_SP, "got rx_mode ramrod\n");
5613 bnx2x_handle_rx_mode_eqe(bp);
5616 /* unknown event log error and continue */
5617 BNX2X_ERR("Unknown EQ event %d, bp->state 0x%x\n",
5618 elem->message.opcode, bp->state);
5624 smp_mb__before_atomic();
5625 atomic_add(spqe_cnt, &bp->eq_spq_left);
5627 bp->eq_cons = sw_cons;
5628 bp->eq_prod = sw_prod;
5629 /* Make sure that above mem writes were issued towards the memory */
5632 /* update producer */
5633 bnx2x_update_eq_prod(bp, bp->eq_prod);
5636 static void bnx2x_sp_task(struct work_struct *work)
5638 struct bnx2x *bp = container_of(work, struct bnx2x, sp_task.work);
5640 DP(BNX2X_MSG_SP, "sp task invoked\n");
5642 /* make sure the atomic interrupt_occurred has been written */
5644 if (atomic_read(&bp->interrupt_occurred)) {
5646 /* what work needs to be performed? */
5647 u16 status = bnx2x_update_dsb_idx(bp);
5649 DP(BNX2X_MSG_SP, "status %x\n", status);
5650 DP(BNX2X_MSG_SP, "setting interrupt_occurred to 0\n");
5651 atomic_set(&bp->interrupt_occurred, 0);
5654 if (status & BNX2X_DEF_SB_ATT_IDX) {
5656 status &= ~BNX2X_DEF_SB_ATT_IDX;
5659 /* SP events: STAT_QUERY and others */
5660 if (status & BNX2X_DEF_SB_IDX) {
5661 struct bnx2x_fastpath *fp = bnx2x_fcoe_fp(bp);
5663 if (FCOE_INIT(bp) &&
5664 (bnx2x_has_rx_work(fp) || bnx2x_has_tx_work(fp))) {
5665 /* Prevent local bottom-halves from running as
5666 * we are going to change the local NAPI list.
5669 napi_schedule(&bnx2x_fcoe(bp, napi));
5673 /* Handle EQ completions */
5675 bnx2x_ack_sb(bp, bp->igu_dsb_id, USTORM_ID,
5676 le16_to_cpu(bp->def_idx), IGU_INT_NOP, 1);
5678 status &= ~BNX2X_DEF_SB_IDX;
5681 /* if status is non zero then perhaps something went wrong */
5682 if (unlikely(status))
5684 "got an unknown interrupt! (status 0x%x)\n", status);
5686 /* ack status block only if something was actually handled */
5687 bnx2x_ack_sb(bp, bp->igu_dsb_id, ATTENTION_ID,
5688 le16_to_cpu(bp->def_att_idx), IGU_INT_ENABLE, 1);
5691 /* afex - poll to check if VIFSET_ACK should be sent to MFW */
5692 if (test_and_clear_bit(BNX2X_AFEX_PENDING_VIFSET_MCP_ACK,
5694 bnx2x_link_report(bp);
5695 bnx2x_fw_command(bp, DRV_MSG_CODE_AFEX_VIFSET_ACK, 0);
5699 irqreturn_t bnx2x_msix_sp_int(int irq, void *dev_instance)
5701 struct net_device *dev = dev_instance;
5702 struct bnx2x *bp = netdev_priv(dev);
5704 bnx2x_ack_sb(bp, bp->igu_dsb_id, USTORM_ID, 0,
5705 IGU_INT_DISABLE, 0);
5707 #ifdef BNX2X_STOP_ON_ERROR
5708 if (unlikely(bp->panic))
5712 if (CNIC_LOADED(bp)) {
5713 struct cnic_ops *c_ops;
5716 c_ops = rcu_dereference(bp->cnic_ops);
5718 c_ops->cnic_handler(bp->cnic_data, NULL);
5722 /* schedule sp task to perform default status block work, ack
5723 * attentions and enable interrupts.
5725 bnx2x_schedule_sp_task(bp);
5730 /* end of slow path */
5732 void bnx2x_drv_pulse(struct bnx2x *bp)
5734 SHMEM_WR(bp, func_mb[BP_FW_MB_IDX(bp)].drv_pulse_mb,
5735 bp->fw_drv_pulse_wr_seq);
5738 static void bnx2x_timer(unsigned long data)
5740 struct bnx2x *bp = (struct bnx2x *) data;
5742 if (!netif_running(bp->dev))
5747 int mb_idx = BP_FW_MB_IDX(bp);
5751 ++bp->fw_drv_pulse_wr_seq;
5752 bp->fw_drv_pulse_wr_seq &= DRV_PULSE_SEQ_MASK;
5753 drv_pulse = bp->fw_drv_pulse_wr_seq;
5754 bnx2x_drv_pulse(bp);
5756 mcp_pulse = (SHMEM_RD(bp, func_mb[mb_idx].mcp_pulse_mb) &
5757 MCP_PULSE_SEQ_MASK);
5758 /* The delta between driver pulse and mcp response
5759 * should not get too big. If the MFW is more than 5 pulses
5760 * behind, we should worry about it enough to generate an error
5763 if (((drv_pulse - mcp_pulse) & MCP_PULSE_SEQ_MASK) > 5)
5764 BNX2X_ERR("MFW seems hanged: drv_pulse (0x%x) != mcp_pulse (0x%x)\n",
5765 drv_pulse, mcp_pulse);
5768 if (bp->state == BNX2X_STATE_OPEN)
5769 bnx2x_stats_handle(bp, STATS_EVENT_UPDATE);
5771 /* sample pf vf bulletin board for new posts from pf */
5773 bnx2x_timer_sriov(bp);
5775 mod_timer(&bp->timer, jiffies + bp->current_interval);
5778 /* end of Statistics */
5783 * nic init service functions
5786 static void bnx2x_fill(struct bnx2x *bp, u32 addr, int fill, u32 len)
5789 if (!(len%4) && !(addr%4))
5790 for (i = 0; i < len; i += 4)
5791 REG_WR(bp, addr + i, fill);
5793 for (i = 0; i < len; i++)
5794 REG_WR8(bp, addr + i, fill);
5797 /* helper: writes FP SP data to FW - data_size in dwords */
5798 static void bnx2x_wr_fp_sb_data(struct bnx2x *bp,
5804 for (index = 0; index < data_size; index++)
5805 REG_WR(bp, BAR_CSTRORM_INTMEM +
5806 CSTORM_STATUS_BLOCK_DATA_OFFSET(fw_sb_id) +
5808 *(sb_data_p + index));
5811 static void bnx2x_zero_fp_sb(struct bnx2x *bp, int fw_sb_id)
5815 struct hc_status_block_data_e2 sb_data_e2;
5816 struct hc_status_block_data_e1x sb_data_e1x;
5818 /* disable the function first */
5819 if (!CHIP_IS_E1x(bp)) {
5820 memset(&sb_data_e2, 0, sizeof(struct hc_status_block_data_e2));
5821 sb_data_e2.common.state = SB_DISABLED;
5822 sb_data_e2.common.p_func.vf_valid = false;
5823 sb_data_p = (u32 *)&sb_data_e2;
5824 data_size = sizeof(struct hc_status_block_data_e2)/sizeof(u32);
5826 memset(&sb_data_e1x, 0,
5827 sizeof(struct hc_status_block_data_e1x));
5828 sb_data_e1x.common.state = SB_DISABLED;
5829 sb_data_e1x.common.p_func.vf_valid = false;
5830 sb_data_p = (u32 *)&sb_data_e1x;
5831 data_size = sizeof(struct hc_status_block_data_e1x)/sizeof(u32);
5833 bnx2x_wr_fp_sb_data(bp, fw_sb_id, sb_data_p, data_size);
5835 bnx2x_fill(bp, BAR_CSTRORM_INTMEM +
5836 CSTORM_STATUS_BLOCK_OFFSET(fw_sb_id), 0,
5837 CSTORM_STATUS_BLOCK_SIZE);
5838 bnx2x_fill(bp, BAR_CSTRORM_INTMEM +
5839 CSTORM_SYNC_BLOCK_OFFSET(fw_sb_id), 0,
5840 CSTORM_SYNC_BLOCK_SIZE);
5843 /* helper: writes SP SB data to FW */
5844 static void bnx2x_wr_sp_sb_data(struct bnx2x *bp,
5845 struct hc_sp_status_block_data *sp_sb_data)
5847 int func = BP_FUNC(bp);
5849 for (i = 0; i < sizeof(struct hc_sp_status_block_data)/sizeof(u32); i++)
5850 REG_WR(bp, BAR_CSTRORM_INTMEM +
5851 CSTORM_SP_STATUS_BLOCK_DATA_OFFSET(func) +
5853 *((u32 *)sp_sb_data + i));
5856 static void bnx2x_zero_sp_sb(struct bnx2x *bp)
5858 int func = BP_FUNC(bp);
5859 struct hc_sp_status_block_data sp_sb_data;
5860 memset(&sp_sb_data, 0, sizeof(struct hc_sp_status_block_data));
5862 sp_sb_data.state = SB_DISABLED;
5863 sp_sb_data.p_func.vf_valid = false;
5865 bnx2x_wr_sp_sb_data(bp, &sp_sb_data);
5867 bnx2x_fill(bp, BAR_CSTRORM_INTMEM +
5868 CSTORM_SP_STATUS_BLOCK_OFFSET(func), 0,
5869 CSTORM_SP_STATUS_BLOCK_SIZE);
5870 bnx2x_fill(bp, BAR_CSTRORM_INTMEM +
5871 CSTORM_SP_SYNC_BLOCK_OFFSET(func), 0,
5872 CSTORM_SP_SYNC_BLOCK_SIZE);
5875 static void bnx2x_setup_ndsb_state_machine(struct hc_status_block_sm *hc_sm,
5876 int igu_sb_id, int igu_seg_id)
5878 hc_sm->igu_sb_id = igu_sb_id;
5879 hc_sm->igu_seg_id = igu_seg_id;
5880 hc_sm->timer_value = 0xFF;
5881 hc_sm->time_to_expire = 0xFFFFFFFF;
5884 /* allocates state machine ids. */
5885 static void bnx2x_map_sb_state_machines(struct hc_index_data *index_data)
5887 /* zero out state machine indices */
5889 index_data[HC_INDEX_ETH_RX_CQ_CONS].flags &= ~HC_INDEX_DATA_SM_ID;
5892 index_data[HC_INDEX_OOO_TX_CQ_CONS].flags &= ~HC_INDEX_DATA_SM_ID;
5893 index_data[HC_INDEX_ETH_TX_CQ_CONS_COS0].flags &= ~HC_INDEX_DATA_SM_ID;
5894 index_data[HC_INDEX_ETH_TX_CQ_CONS_COS1].flags &= ~HC_INDEX_DATA_SM_ID;
5895 index_data[HC_INDEX_ETH_TX_CQ_CONS_COS2].flags &= ~HC_INDEX_DATA_SM_ID;
5899 index_data[HC_INDEX_ETH_RX_CQ_CONS].flags |=
5900 SM_RX_ID << HC_INDEX_DATA_SM_ID_SHIFT;
5903 index_data[HC_INDEX_OOO_TX_CQ_CONS].flags |=
5904 SM_TX_ID << HC_INDEX_DATA_SM_ID_SHIFT;
5905 index_data[HC_INDEX_ETH_TX_CQ_CONS_COS0].flags |=
5906 SM_TX_ID << HC_INDEX_DATA_SM_ID_SHIFT;
5907 index_data[HC_INDEX_ETH_TX_CQ_CONS_COS1].flags |=
5908 SM_TX_ID << HC_INDEX_DATA_SM_ID_SHIFT;
5909 index_data[HC_INDEX_ETH_TX_CQ_CONS_COS2].flags |=
5910 SM_TX_ID << HC_INDEX_DATA_SM_ID_SHIFT;
5913 void bnx2x_init_sb(struct bnx2x *bp, dma_addr_t mapping, int vfid,
5914 u8 vf_valid, int fw_sb_id, int igu_sb_id)
5918 struct hc_status_block_data_e2 sb_data_e2;
5919 struct hc_status_block_data_e1x sb_data_e1x;
5920 struct hc_status_block_sm *hc_sm_p;
5924 if (CHIP_INT_MODE_IS_BC(bp))
5925 igu_seg_id = HC_SEG_ACCESS_NORM;
5927 igu_seg_id = IGU_SEG_ACCESS_NORM;
5929 bnx2x_zero_fp_sb(bp, fw_sb_id);
5931 if (!CHIP_IS_E1x(bp)) {
5932 memset(&sb_data_e2, 0, sizeof(struct hc_status_block_data_e2));
5933 sb_data_e2.common.state = SB_ENABLED;
5934 sb_data_e2.common.p_func.pf_id = BP_FUNC(bp);
5935 sb_data_e2.common.p_func.vf_id = vfid;
5936 sb_data_e2.common.p_func.vf_valid = vf_valid;
5937 sb_data_e2.common.p_func.vnic_id = BP_VN(bp);
5938 sb_data_e2.common.same_igu_sb_1b = true;
5939 sb_data_e2.common.host_sb_addr.hi = U64_HI(mapping);
5940 sb_data_e2.common.host_sb_addr.lo = U64_LO(mapping);
5941 hc_sm_p = sb_data_e2.common.state_machine;
5942 sb_data_p = (u32 *)&sb_data_e2;
5943 data_size = sizeof(struct hc_status_block_data_e2)/sizeof(u32);
5944 bnx2x_map_sb_state_machines(sb_data_e2.index_data);
5946 memset(&sb_data_e1x, 0,
5947 sizeof(struct hc_status_block_data_e1x));
5948 sb_data_e1x.common.state = SB_ENABLED;
5949 sb_data_e1x.common.p_func.pf_id = BP_FUNC(bp);
5950 sb_data_e1x.common.p_func.vf_id = 0xff;
5951 sb_data_e1x.common.p_func.vf_valid = false;
5952 sb_data_e1x.common.p_func.vnic_id = BP_VN(bp);
5953 sb_data_e1x.common.same_igu_sb_1b = true;
5954 sb_data_e1x.common.host_sb_addr.hi = U64_HI(mapping);
5955 sb_data_e1x.common.host_sb_addr.lo = U64_LO(mapping);
5956 hc_sm_p = sb_data_e1x.common.state_machine;
5957 sb_data_p = (u32 *)&sb_data_e1x;
5958 data_size = sizeof(struct hc_status_block_data_e1x)/sizeof(u32);
5959 bnx2x_map_sb_state_machines(sb_data_e1x.index_data);
5962 bnx2x_setup_ndsb_state_machine(&hc_sm_p[SM_RX_ID],
5963 igu_sb_id, igu_seg_id);
5964 bnx2x_setup_ndsb_state_machine(&hc_sm_p[SM_TX_ID],
5965 igu_sb_id, igu_seg_id);
5967 DP(NETIF_MSG_IFUP, "Init FW SB %d\n", fw_sb_id);
5969 /* write indices to HW - PCI guarantees endianity of regpairs */
5970 bnx2x_wr_fp_sb_data(bp, fw_sb_id, sb_data_p, data_size);
5973 static void bnx2x_update_coalesce_sb(struct bnx2x *bp, u8 fw_sb_id,
5974 u16 tx_usec, u16 rx_usec)
5976 bnx2x_update_coalesce_sb_index(bp, fw_sb_id, HC_INDEX_ETH_RX_CQ_CONS,
5978 bnx2x_update_coalesce_sb_index(bp, fw_sb_id,
5979 HC_INDEX_ETH_TX_CQ_CONS_COS0, false,
5981 bnx2x_update_coalesce_sb_index(bp, fw_sb_id,
5982 HC_INDEX_ETH_TX_CQ_CONS_COS1, false,
5984 bnx2x_update_coalesce_sb_index(bp, fw_sb_id,
5985 HC_INDEX_ETH_TX_CQ_CONS_COS2, false,
5989 static void bnx2x_init_def_sb(struct bnx2x *bp)
5991 struct host_sp_status_block *def_sb = bp->def_status_blk;
5992 dma_addr_t mapping = bp->def_status_blk_mapping;
5993 int igu_sp_sb_index;
5995 int port = BP_PORT(bp);
5996 int func = BP_FUNC(bp);
5997 int reg_offset, reg_offset_en5;
6000 struct hc_sp_status_block_data sp_sb_data;
6001 memset(&sp_sb_data, 0, sizeof(struct hc_sp_status_block_data));
6003 if (CHIP_INT_MODE_IS_BC(bp)) {
6004 igu_sp_sb_index = DEF_SB_IGU_ID;
6005 igu_seg_id = HC_SEG_ACCESS_DEF;
6007 igu_sp_sb_index = bp->igu_dsb_id;
6008 igu_seg_id = IGU_SEG_ACCESS_DEF;
6012 section = ((u64)mapping) + offsetof(struct host_sp_status_block,
6013 atten_status_block);
6014 def_sb->atten_status_block.status_block_id = igu_sp_sb_index;
6018 reg_offset = (port ? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_0 :
6019 MISC_REG_AEU_ENABLE1_FUNC_0_OUT_0);
6020 reg_offset_en5 = (port ? MISC_REG_AEU_ENABLE5_FUNC_1_OUT_0 :
6021 MISC_REG_AEU_ENABLE5_FUNC_0_OUT_0);
6022 for (index = 0; index < MAX_DYNAMIC_ATTN_GRPS; index++) {
6024 /* take care of sig[0]..sig[4] */
6025 for (sindex = 0; sindex < 4; sindex++)
6026 bp->attn_group[index].sig[sindex] =
6027 REG_RD(bp, reg_offset + sindex*0x4 + 0x10*index);
6029 if (!CHIP_IS_E1x(bp))
6031 * enable5 is separate from the rest of the registers,
6032 * and therefore the address skip is 4
6033 * and not 16 between the different groups
6035 bp->attn_group[index].sig[4] = REG_RD(bp,
6036 reg_offset_en5 + 0x4*index);
6038 bp->attn_group[index].sig[4] = 0;
6041 if (bp->common.int_block == INT_BLOCK_HC) {
6042 reg_offset = (port ? HC_REG_ATTN_MSG1_ADDR_L :
6043 HC_REG_ATTN_MSG0_ADDR_L);
6045 REG_WR(bp, reg_offset, U64_LO(section));
6046 REG_WR(bp, reg_offset + 4, U64_HI(section));
6047 } else if (!CHIP_IS_E1x(bp)) {
6048 REG_WR(bp, IGU_REG_ATTN_MSG_ADDR_L, U64_LO(section));
6049 REG_WR(bp, IGU_REG_ATTN_MSG_ADDR_H, U64_HI(section));
6052 section = ((u64)mapping) + offsetof(struct host_sp_status_block,
6055 bnx2x_zero_sp_sb(bp);
6057 /* PCI guarantees endianity of regpairs */
6058 sp_sb_data.state = SB_ENABLED;
6059 sp_sb_data.host_sb_addr.lo = U64_LO(section);
6060 sp_sb_data.host_sb_addr.hi = U64_HI(section);
6061 sp_sb_data.igu_sb_id = igu_sp_sb_index;
6062 sp_sb_data.igu_seg_id = igu_seg_id;
6063 sp_sb_data.p_func.pf_id = func;
6064 sp_sb_data.p_func.vnic_id = BP_VN(bp);
6065 sp_sb_data.p_func.vf_id = 0xff;
6067 bnx2x_wr_sp_sb_data(bp, &sp_sb_data);
6069 bnx2x_ack_sb(bp, bp->igu_dsb_id, USTORM_ID, 0, IGU_INT_ENABLE, 0);
6072 void bnx2x_update_coalesce(struct bnx2x *bp)
6076 for_each_eth_queue(bp, i)
6077 bnx2x_update_coalesce_sb(bp, bp->fp[i].fw_sb_id,
6078 bp->tx_ticks, bp->rx_ticks);
6081 static void bnx2x_init_sp_ring(struct bnx2x *bp)
6083 spin_lock_init(&bp->spq_lock);
6084 atomic_set(&bp->cq_spq_left, MAX_SPQ_PENDING);
6086 bp->spq_prod_idx = 0;
6087 bp->dsb_sp_prod = BNX2X_SP_DSB_INDEX;
6088 bp->spq_prod_bd = bp->spq;
6089 bp->spq_last_bd = bp->spq_prod_bd + MAX_SP_DESC_CNT;
6092 static void bnx2x_init_eq_ring(struct bnx2x *bp)
6095 for (i = 1; i <= NUM_EQ_PAGES; i++) {
6096 union event_ring_elem *elem =
6097 &bp->eq_ring[EQ_DESC_CNT_PAGE * i - 1];
6099 elem->next_page.addr.hi =
6100 cpu_to_le32(U64_HI(bp->eq_mapping +
6101 BCM_PAGE_SIZE * (i % NUM_EQ_PAGES)));
6102 elem->next_page.addr.lo =
6103 cpu_to_le32(U64_LO(bp->eq_mapping +
6104 BCM_PAGE_SIZE*(i % NUM_EQ_PAGES)));
6107 bp->eq_prod = NUM_EQ_DESC;
6108 bp->eq_cons_sb = BNX2X_EQ_INDEX;
6109 /* we want a warning message before it gets wrought... */
6110 atomic_set(&bp->eq_spq_left,
6111 min_t(int, MAX_SP_DESC_CNT - MAX_SPQ_PENDING, NUM_EQ_DESC) - 1);
6114 /* called with netif_addr_lock_bh() */
6115 static int bnx2x_set_q_rx_mode(struct bnx2x *bp, u8 cl_id,
6116 unsigned long rx_mode_flags,
6117 unsigned long rx_accept_flags,
6118 unsigned long tx_accept_flags,
6119 unsigned long ramrod_flags)
6121 struct bnx2x_rx_mode_ramrod_params ramrod_param;
6124 memset(&ramrod_param, 0, sizeof(ramrod_param));
6126 /* Prepare ramrod parameters */
6127 ramrod_param.cid = 0;
6128 ramrod_param.cl_id = cl_id;
6129 ramrod_param.rx_mode_obj = &bp->rx_mode_obj;
6130 ramrod_param.func_id = BP_FUNC(bp);
6132 ramrod_param.pstate = &bp->sp_state;
6133 ramrod_param.state = BNX2X_FILTER_RX_MODE_PENDING;
6135 ramrod_param.rdata = bnx2x_sp(bp, rx_mode_rdata);
6136 ramrod_param.rdata_mapping = bnx2x_sp_mapping(bp, rx_mode_rdata);
6138 set_bit(BNX2X_FILTER_RX_MODE_PENDING, &bp->sp_state);
6140 ramrod_param.ramrod_flags = ramrod_flags;
6141 ramrod_param.rx_mode_flags = rx_mode_flags;
6143 ramrod_param.rx_accept_flags = rx_accept_flags;
6144 ramrod_param.tx_accept_flags = tx_accept_flags;
6146 rc = bnx2x_config_rx_mode(bp, &ramrod_param);
6148 BNX2X_ERR("Set rx_mode %d failed\n", bp->rx_mode);
6155 static int bnx2x_fill_accept_flags(struct bnx2x *bp, u32 rx_mode,
6156 unsigned long *rx_accept_flags,
6157 unsigned long *tx_accept_flags)
6159 /* Clear the flags first */
6160 *rx_accept_flags = 0;
6161 *tx_accept_flags = 0;
6164 case BNX2X_RX_MODE_NONE:
6166 * 'drop all' supersedes any accept flags that may have been
6167 * passed to the function.
6170 case BNX2X_RX_MODE_NORMAL:
6171 __set_bit(BNX2X_ACCEPT_UNICAST, rx_accept_flags);
6172 __set_bit(BNX2X_ACCEPT_MULTICAST, rx_accept_flags);
6173 __set_bit(BNX2X_ACCEPT_BROADCAST, rx_accept_flags);
6175 /* internal switching mode */
6176 __set_bit(BNX2X_ACCEPT_UNICAST, tx_accept_flags);
6177 __set_bit(BNX2X_ACCEPT_MULTICAST, tx_accept_flags);
6178 __set_bit(BNX2X_ACCEPT_BROADCAST, tx_accept_flags);
6181 case BNX2X_RX_MODE_ALLMULTI:
6182 __set_bit(BNX2X_ACCEPT_UNICAST, rx_accept_flags);
6183 __set_bit(BNX2X_ACCEPT_ALL_MULTICAST, rx_accept_flags);
6184 __set_bit(BNX2X_ACCEPT_BROADCAST, rx_accept_flags);
6186 /* internal switching mode */
6187 __set_bit(BNX2X_ACCEPT_UNICAST, tx_accept_flags);
6188 __set_bit(BNX2X_ACCEPT_ALL_MULTICAST, tx_accept_flags);
6189 __set_bit(BNX2X_ACCEPT_BROADCAST, tx_accept_flags);
6192 case BNX2X_RX_MODE_PROMISC:
6193 /* According to definition of SI mode, iface in promisc mode
6194 * should receive matched and unmatched (in resolution of port)
6197 __set_bit(BNX2X_ACCEPT_UNMATCHED, rx_accept_flags);
6198 __set_bit(BNX2X_ACCEPT_UNICAST, rx_accept_flags);
6199 __set_bit(BNX2X_ACCEPT_ALL_MULTICAST, rx_accept_flags);
6200 __set_bit(BNX2X_ACCEPT_BROADCAST, rx_accept_flags);
6202 /* internal switching mode */
6203 __set_bit(BNX2X_ACCEPT_ALL_MULTICAST, tx_accept_flags);
6204 __set_bit(BNX2X_ACCEPT_BROADCAST, tx_accept_flags);
6207 __set_bit(BNX2X_ACCEPT_ALL_UNICAST, tx_accept_flags);
6209 __set_bit(BNX2X_ACCEPT_UNICAST, tx_accept_flags);
6213 BNX2X_ERR("Unknown rx_mode: %d\n", rx_mode);
6217 /* Set ACCEPT_ANY_VLAN as we do not enable filtering by VLAN */
6218 if (rx_mode != BNX2X_RX_MODE_NONE) {
6219 __set_bit(BNX2X_ACCEPT_ANY_VLAN, rx_accept_flags);
6220 __set_bit(BNX2X_ACCEPT_ANY_VLAN, tx_accept_flags);
6226 /* called with netif_addr_lock_bh() */
6227 static int bnx2x_set_storm_rx_mode(struct bnx2x *bp)
6229 unsigned long rx_mode_flags = 0, ramrod_flags = 0;
6230 unsigned long rx_accept_flags = 0, tx_accept_flags = 0;
6234 /* Configure rx_mode of FCoE Queue */
6235 __set_bit(BNX2X_RX_MODE_FCOE_ETH, &rx_mode_flags);
6237 rc = bnx2x_fill_accept_flags(bp, bp->rx_mode, &rx_accept_flags,
6242 __set_bit(RAMROD_RX, &ramrod_flags);
6243 __set_bit(RAMROD_TX, &ramrod_flags);
6245 return bnx2x_set_q_rx_mode(bp, bp->fp->cl_id, rx_mode_flags,
6246 rx_accept_flags, tx_accept_flags,
6250 static void bnx2x_init_internal_common(struct bnx2x *bp)
6254 /* Zero this manually as its initialization is
6255 currently missing in the initTool */
6256 for (i = 0; i < (USTORM_AGG_DATA_SIZE >> 2); i++)
6257 REG_WR(bp, BAR_USTRORM_INTMEM +
6258 USTORM_AGG_DATA_OFFSET + i * 4, 0);
6259 if (!CHIP_IS_E1x(bp)) {
6260 REG_WR8(bp, BAR_CSTRORM_INTMEM + CSTORM_IGU_MODE_OFFSET,
6261 CHIP_INT_MODE_IS_BC(bp) ?
6262 HC_IGU_BC_MODE : HC_IGU_NBC_MODE);
6266 static void bnx2x_init_internal(struct bnx2x *bp, u32 load_code)
6268 switch (load_code) {
6269 case FW_MSG_CODE_DRV_LOAD_COMMON:
6270 case FW_MSG_CODE_DRV_LOAD_COMMON_CHIP:
6271 bnx2x_init_internal_common(bp);
6274 case FW_MSG_CODE_DRV_LOAD_PORT:
6278 case FW_MSG_CODE_DRV_LOAD_FUNCTION:
6279 /* internal memory per function is
6280 initialized inside bnx2x_pf_init */
6284 BNX2X_ERR("Unknown load_code (0x%x) from MCP\n", load_code);
6289 static inline u8 bnx2x_fp_igu_sb_id(struct bnx2x_fastpath *fp)
6291 return fp->bp->igu_base_sb + fp->index + CNIC_SUPPORT(fp->bp);
6294 static inline u8 bnx2x_fp_fw_sb_id(struct bnx2x_fastpath *fp)
6296 return fp->bp->base_fw_ndsb + fp->index + CNIC_SUPPORT(fp->bp);
6299 static u8 bnx2x_fp_cl_id(struct bnx2x_fastpath *fp)
6301 if (CHIP_IS_E1x(fp->bp))
6302 return BP_L_ID(fp->bp) + fp->index;
6303 else /* We want Client ID to be the same as IGU SB ID for 57712 */
6304 return bnx2x_fp_igu_sb_id(fp);
6307 static void bnx2x_init_eth_fp(struct bnx2x *bp, int fp_idx)
6309 struct bnx2x_fastpath *fp = &bp->fp[fp_idx];
6311 unsigned long q_type = 0;
6312 u32 cids[BNX2X_MULTI_TX_COS] = { 0 };
6313 fp->rx_queue = fp_idx;
6315 fp->cl_id = bnx2x_fp_cl_id(fp);
6316 fp->fw_sb_id = bnx2x_fp_fw_sb_id(fp);
6317 fp->igu_sb_id = bnx2x_fp_igu_sb_id(fp);
6318 /* qZone id equals to FW (per path) client id */
6319 fp->cl_qzone_id = bnx2x_fp_qzone_id(fp);
6322 fp->ustorm_rx_prods_offset = bnx2x_rx_ustorm_prods_offset(fp);
6324 /* Setup SB indices */
6325 fp->rx_cons_sb = BNX2X_RX_SB_INDEX;
6327 /* Configure Queue State object */
6328 __set_bit(BNX2X_Q_TYPE_HAS_RX, &q_type);
6329 __set_bit(BNX2X_Q_TYPE_HAS_TX, &q_type);
6331 BUG_ON(fp->max_cos > BNX2X_MULTI_TX_COS);
6334 for_each_cos_in_tx_queue(fp, cos) {
6335 bnx2x_init_txdata(bp, fp->txdata_ptr[cos],
6336 CID_COS_TO_TX_ONLY_CID(fp->cid, cos, bp),
6337 FP_COS_TO_TXQ(fp, cos, bp),
6338 BNX2X_TX_SB_INDEX_BASE + cos, fp);
6339 cids[cos] = fp->txdata_ptr[cos]->cid;
6342 /* nothing more for vf to do here */
6346 bnx2x_init_sb(bp, fp->status_blk_mapping, BNX2X_VF_ID_INVALID, false,
6347 fp->fw_sb_id, fp->igu_sb_id);
6348 bnx2x_update_fpsb_idx(fp);
6349 bnx2x_init_queue_obj(bp, &bnx2x_sp_obj(bp, fp).q_obj, fp->cl_id, cids,
6350 fp->max_cos, BP_FUNC(bp), bnx2x_sp(bp, q_rdata),
6351 bnx2x_sp_mapping(bp, q_rdata), q_type);
6354 * Configure classification DBs: Always enable Tx switching
6356 bnx2x_init_vlan_mac_fp_objs(fp, BNX2X_OBJ_TYPE_RX_TX);
6359 "queue[%d]: bnx2x_init_sb(%p,%p) cl_id %d fw_sb %d igu_sb %d\n",
6360 fp_idx, bp, fp->status_blk.e2_sb, fp->cl_id, fp->fw_sb_id,
6364 static void bnx2x_init_tx_ring_one(struct bnx2x_fp_txdata *txdata)
6368 for (i = 1; i <= NUM_TX_RINGS; i++) {
6369 struct eth_tx_next_bd *tx_next_bd =
6370 &txdata->tx_desc_ring[TX_DESC_CNT * i - 1].next_bd;
6372 tx_next_bd->addr_hi =
6373 cpu_to_le32(U64_HI(txdata->tx_desc_mapping +
6374 BCM_PAGE_SIZE*(i % NUM_TX_RINGS)));
6375 tx_next_bd->addr_lo =
6376 cpu_to_le32(U64_LO(txdata->tx_desc_mapping +
6377 BCM_PAGE_SIZE*(i % NUM_TX_RINGS)));
6380 *txdata->tx_cons_sb = cpu_to_le16(0);
6382 SET_FLAG(txdata->tx_db.data.header.header, DOORBELL_HDR_DB_TYPE, 1);
6383 txdata->tx_db.data.zero_fill1 = 0;
6384 txdata->tx_db.data.prod = 0;
6386 txdata->tx_pkt_prod = 0;
6387 txdata->tx_pkt_cons = 0;
6388 txdata->tx_bd_prod = 0;
6389 txdata->tx_bd_cons = 0;
6393 static void bnx2x_init_tx_rings_cnic(struct bnx2x *bp)
6397 for_each_tx_queue_cnic(bp, i)
6398 bnx2x_init_tx_ring_one(bp->fp[i].txdata_ptr[0]);
6401 static void bnx2x_init_tx_rings(struct bnx2x *bp)
6406 for_each_eth_queue(bp, i)
6407 for_each_cos_in_tx_queue(&bp->fp[i], cos)
6408 bnx2x_init_tx_ring_one(bp->fp[i].txdata_ptr[cos]);
6411 static void bnx2x_init_fcoe_fp(struct bnx2x *bp)
6413 struct bnx2x_fastpath *fp = bnx2x_fcoe_fp(bp);
6414 unsigned long q_type = 0;
6416 bnx2x_fcoe(bp, rx_queue) = BNX2X_NUM_ETH_QUEUES(bp);
6417 bnx2x_fcoe(bp, cl_id) = bnx2x_cnic_eth_cl_id(bp,
6418 BNX2X_FCOE_ETH_CL_ID_IDX);
6419 bnx2x_fcoe(bp, cid) = BNX2X_FCOE_ETH_CID(bp);
6420 bnx2x_fcoe(bp, fw_sb_id) = DEF_SB_ID;
6421 bnx2x_fcoe(bp, igu_sb_id) = bp->igu_dsb_id;
6422 bnx2x_fcoe(bp, rx_cons_sb) = BNX2X_FCOE_L2_RX_INDEX;
6423 bnx2x_init_txdata(bp, bnx2x_fcoe(bp, txdata_ptr[0]),
6424 fp->cid, FCOE_TXQ_IDX(bp), BNX2X_FCOE_L2_TX_INDEX,
6427 DP(NETIF_MSG_IFUP, "created fcoe tx data (fp index %d)\n", fp->index);
6429 /* qZone id equals to FW (per path) client id */
6430 bnx2x_fcoe(bp, cl_qzone_id) = bnx2x_fp_qzone_id(fp);
6432 bnx2x_fcoe(bp, ustorm_rx_prods_offset) =
6433 bnx2x_rx_ustorm_prods_offset(fp);
6435 /* Configure Queue State object */
6436 __set_bit(BNX2X_Q_TYPE_HAS_RX, &q_type);
6437 __set_bit(BNX2X_Q_TYPE_HAS_TX, &q_type);
6439 /* No multi-CoS for FCoE L2 client */
6440 BUG_ON(fp->max_cos != 1);
6442 bnx2x_init_queue_obj(bp, &bnx2x_sp_obj(bp, fp).q_obj, fp->cl_id,
6443 &fp->cid, 1, BP_FUNC(bp), bnx2x_sp(bp, q_rdata),
6444 bnx2x_sp_mapping(bp, q_rdata), q_type);
6447 "queue[%d]: bnx2x_init_sb(%p,%p) cl_id %d fw_sb %d igu_sb %d\n",
6448 fp->index, bp, fp->status_blk.e2_sb, fp->cl_id, fp->fw_sb_id,
6452 void bnx2x_nic_init_cnic(struct bnx2x *bp)
6455 bnx2x_init_fcoe_fp(bp);
6457 bnx2x_init_sb(bp, bp->cnic_sb_mapping,
6458 BNX2X_VF_ID_INVALID, false,
6459 bnx2x_cnic_fw_sb_id(bp), bnx2x_cnic_igu_sb_id(bp));
6461 /* ensure status block indices were read */
6463 bnx2x_init_rx_rings_cnic(bp);
6464 bnx2x_init_tx_rings_cnic(bp);
6471 void bnx2x_pre_irq_nic_init(struct bnx2x *bp)
6475 /* Setup NIC internals and enable interrupts */
6476 for_each_eth_queue(bp, i)
6477 bnx2x_init_eth_fp(bp, i);
6479 /* ensure status block indices were read */
6481 bnx2x_init_rx_rings(bp);
6482 bnx2x_init_tx_rings(bp);
6485 /* Initialize MOD_ABS interrupts */
6486 bnx2x_init_mod_abs_int(bp, &bp->link_vars, bp->common.chip_id,
6487 bp->common.shmem_base,
6488 bp->common.shmem2_base, BP_PORT(bp));
6490 /* initialize the default status block and sp ring */
6491 bnx2x_init_def_sb(bp);
6492 bnx2x_update_dsb_idx(bp);
6493 bnx2x_init_sp_ring(bp);
6495 bnx2x_memset_stats(bp);
6499 void bnx2x_post_irq_nic_init(struct bnx2x *bp, u32 load_code)
6501 bnx2x_init_eq_ring(bp);
6502 bnx2x_init_internal(bp, load_code);
6504 bnx2x_stats_init(bp);
6506 /* flush all before enabling interrupts */
6510 bnx2x_int_enable(bp);
6512 /* Check for SPIO5 */
6513 bnx2x_attn_int_deasserted0(bp,
6514 REG_RD(bp, MISC_REG_AEU_AFTER_INVERT_1_FUNC_0 + BP_PORT(bp)*4) &
6515 AEU_INPUTS_ATTN_BITS_SPIO5);
6518 /* gzip service functions */
6519 static int bnx2x_gunzip_init(struct bnx2x *bp)
6521 bp->gunzip_buf = dma_alloc_coherent(&bp->pdev->dev, FW_BUF_SIZE,
6522 &bp->gunzip_mapping, GFP_KERNEL);
6523 if (bp->gunzip_buf == NULL)
6526 bp->strm = kmalloc(sizeof(*bp->strm), GFP_KERNEL);
6527 if (bp->strm == NULL)
6530 bp->strm->workspace = vmalloc(zlib_inflate_workspacesize());
6531 if (bp->strm->workspace == NULL)
6541 dma_free_coherent(&bp->pdev->dev, FW_BUF_SIZE, bp->gunzip_buf,
6542 bp->gunzip_mapping);
6543 bp->gunzip_buf = NULL;
6546 BNX2X_ERR("Cannot allocate firmware buffer for un-compression\n");
6550 static void bnx2x_gunzip_end(struct bnx2x *bp)
6553 vfree(bp->strm->workspace);
6558 if (bp->gunzip_buf) {
6559 dma_free_coherent(&bp->pdev->dev, FW_BUF_SIZE, bp->gunzip_buf,
6560 bp->gunzip_mapping);
6561 bp->gunzip_buf = NULL;
6565 static int bnx2x_gunzip(struct bnx2x *bp, const u8 *zbuf, int len)
6569 /* check gzip header */
6570 if ((zbuf[0] != 0x1f) || (zbuf[1] != 0x8b) || (zbuf[2] != Z_DEFLATED)) {
6571 BNX2X_ERR("Bad gzip header\n");
6579 if (zbuf[3] & FNAME)
6580 while ((zbuf[n++] != 0) && (n < len));
6582 bp->strm->next_in = (typeof(bp->strm->next_in))zbuf + n;
6583 bp->strm->avail_in = len - n;
6584 bp->strm->next_out = bp->gunzip_buf;
6585 bp->strm->avail_out = FW_BUF_SIZE;
6587 rc = zlib_inflateInit2(bp->strm, -MAX_WBITS);
6591 rc = zlib_inflate(bp->strm, Z_FINISH);
6592 if ((rc != Z_OK) && (rc != Z_STREAM_END))
6593 netdev_err(bp->dev, "Firmware decompression error: %s\n",
6596 bp->gunzip_outlen = (FW_BUF_SIZE - bp->strm->avail_out);
6597 if (bp->gunzip_outlen & 0x3)
6599 "Firmware decompression error: gunzip_outlen (%d) not aligned\n",
6601 bp->gunzip_outlen >>= 2;
6603 zlib_inflateEnd(bp->strm);
6605 if (rc == Z_STREAM_END)
6611 /* nic load/unload */
6614 * General service functions
6617 /* send a NIG loopback debug packet */
6618 static void bnx2x_lb_pckt(struct bnx2x *bp)
6622 /* Ethernet source and destination addresses */
6623 wb_write[0] = 0x55555555;
6624 wb_write[1] = 0x55555555;
6625 wb_write[2] = 0x20; /* SOP */
6626 REG_WR_DMAE(bp, NIG_REG_DEBUG_PACKET_LB, wb_write, 3);
6628 /* NON-IP protocol */
6629 wb_write[0] = 0x09000000;
6630 wb_write[1] = 0x55555555;
6631 wb_write[2] = 0x10; /* EOP, eop_bvalid = 0 */
6632 REG_WR_DMAE(bp, NIG_REG_DEBUG_PACKET_LB, wb_write, 3);
6635 /* some of the internal memories
6636 * are not directly readable from the driver
6637 * to test them we send debug packets
6639 static int bnx2x_int_mem_test(struct bnx2x *bp)
6645 if (CHIP_REV_IS_FPGA(bp))
6647 else if (CHIP_REV_IS_EMUL(bp))
6652 /* Disable inputs of parser neighbor blocks */
6653 REG_WR(bp, TSDM_REG_ENABLE_IN1, 0x0);
6654 REG_WR(bp, TCM_REG_PRS_IFEN, 0x0);
6655 REG_WR(bp, CFC_REG_DEBUG0, 0x1);
6656 REG_WR(bp, NIG_REG_PRS_REQ_IN_EN, 0x0);
6658 /* Write 0 to parser credits for CFC search request */
6659 REG_WR(bp, PRS_REG_CFC_SEARCH_INITIAL_CREDIT, 0x0);
6661 /* send Ethernet packet */
6664 /* TODO do i reset NIG statistic? */
6665 /* Wait until NIG register shows 1 packet of size 0x10 */
6666 count = 1000 * factor;
6669 bnx2x_read_dmae(bp, NIG_REG_STAT2_BRB_OCTET, 2);
6670 val = *bnx2x_sp(bp, wb_data[0]);
6674 usleep_range(10000, 20000);
6678 BNX2X_ERR("NIG timeout val = 0x%x\n", val);
6682 /* Wait until PRS register shows 1 packet */
6683 count = 1000 * factor;
6685 val = REG_RD(bp, PRS_REG_NUM_OF_PACKETS);
6689 usleep_range(10000, 20000);
6693 BNX2X_ERR("PRS timeout val = 0x%x\n", val);
6697 /* Reset and init BRB, PRS */
6698 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_CLEAR, 0x03);
6700 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_SET, 0x03);
6702 bnx2x_init_block(bp, BLOCK_BRB1, PHASE_COMMON);
6703 bnx2x_init_block(bp, BLOCK_PRS, PHASE_COMMON);
6705 DP(NETIF_MSG_HW, "part2\n");
6707 /* Disable inputs of parser neighbor blocks */
6708 REG_WR(bp, TSDM_REG_ENABLE_IN1, 0x0);
6709 REG_WR(bp, TCM_REG_PRS_IFEN, 0x0);
6710 REG_WR(bp, CFC_REG_DEBUG0, 0x1);
6711 REG_WR(bp, NIG_REG_PRS_REQ_IN_EN, 0x0);
6713 /* Write 0 to parser credits for CFC search request */
6714 REG_WR(bp, PRS_REG_CFC_SEARCH_INITIAL_CREDIT, 0x0);
6716 /* send 10 Ethernet packets */
6717 for (i = 0; i < 10; i++)
6720 /* Wait until NIG register shows 10 + 1
6721 packets of size 11*0x10 = 0xb0 */
6722 count = 1000 * factor;
6725 bnx2x_read_dmae(bp, NIG_REG_STAT2_BRB_OCTET, 2);
6726 val = *bnx2x_sp(bp, wb_data[0]);
6730 usleep_range(10000, 20000);
6734 BNX2X_ERR("NIG timeout val = 0x%x\n", val);
6738 /* Wait until PRS register shows 2 packets */
6739 val = REG_RD(bp, PRS_REG_NUM_OF_PACKETS);
6741 BNX2X_ERR("PRS timeout val = 0x%x\n", val);
6743 /* Write 1 to parser credits for CFC search request */
6744 REG_WR(bp, PRS_REG_CFC_SEARCH_INITIAL_CREDIT, 0x1);
6746 /* Wait until PRS register shows 3 packets */
6747 msleep(10 * factor);
6748 /* Wait until NIG register shows 1 packet of size 0x10 */
6749 val = REG_RD(bp, PRS_REG_NUM_OF_PACKETS);
6751 BNX2X_ERR("PRS timeout val = 0x%x\n", val);
6753 /* clear NIG EOP FIFO */
6754 for (i = 0; i < 11; i++)
6755 REG_RD(bp, NIG_REG_INGRESS_EOP_LB_FIFO);
6756 val = REG_RD(bp, NIG_REG_INGRESS_EOP_LB_EMPTY);
6758 BNX2X_ERR("clear of NIG failed\n");
6762 /* Reset and init BRB, PRS, NIG */
6763 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_CLEAR, 0x03);
6765 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_SET, 0x03);
6767 bnx2x_init_block(bp, BLOCK_BRB1, PHASE_COMMON);
6768 bnx2x_init_block(bp, BLOCK_PRS, PHASE_COMMON);
6769 if (!CNIC_SUPPORT(bp))
6771 REG_WR(bp, PRS_REG_NIC_MODE, 1);
6773 /* Enable inputs of parser neighbor blocks */
6774 REG_WR(bp, TSDM_REG_ENABLE_IN1, 0x7fffffff);
6775 REG_WR(bp, TCM_REG_PRS_IFEN, 0x1);
6776 REG_WR(bp, CFC_REG_DEBUG0, 0x0);
6777 REG_WR(bp, NIG_REG_PRS_REQ_IN_EN, 0x1);
6779 DP(NETIF_MSG_HW, "done\n");
6784 static void bnx2x_enable_blocks_attention(struct bnx2x *bp)
6788 REG_WR(bp, PXP_REG_PXP_INT_MASK_0, 0);
6789 if (!CHIP_IS_E1x(bp))
6790 REG_WR(bp, PXP_REG_PXP_INT_MASK_1, 0x40);
6792 REG_WR(bp, PXP_REG_PXP_INT_MASK_1, 0);
6793 REG_WR(bp, DORQ_REG_DORQ_INT_MASK, 0);
6794 REG_WR(bp, CFC_REG_CFC_INT_MASK, 0);
6796 * mask read length error interrupts in brb for parser
6797 * (parsing unit and 'checksum and crc' unit)
6798 * these errors are legal (PU reads fixed length and CAC can cause
6799 * read length error on truncated packets)
6801 REG_WR(bp, BRB1_REG_BRB1_INT_MASK, 0xFC00);
6802 REG_WR(bp, QM_REG_QM_INT_MASK, 0);
6803 REG_WR(bp, TM_REG_TM_INT_MASK, 0);
6804 REG_WR(bp, XSDM_REG_XSDM_INT_MASK_0, 0);
6805 REG_WR(bp, XSDM_REG_XSDM_INT_MASK_1, 0);
6806 REG_WR(bp, XCM_REG_XCM_INT_MASK, 0);
6807 /* REG_WR(bp, XSEM_REG_XSEM_INT_MASK_0, 0); */
6808 /* REG_WR(bp, XSEM_REG_XSEM_INT_MASK_1, 0); */
6809 REG_WR(bp, USDM_REG_USDM_INT_MASK_0, 0);
6810 REG_WR(bp, USDM_REG_USDM_INT_MASK_1, 0);
6811 REG_WR(bp, UCM_REG_UCM_INT_MASK, 0);
6812 /* REG_WR(bp, USEM_REG_USEM_INT_MASK_0, 0); */
6813 /* REG_WR(bp, USEM_REG_USEM_INT_MASK_1, 0); */
6814 REG_WR(bp, GRCBASE_UPB + PB_REG_PB_INT_MASK, 0);
6815 REG_WR(bp, CSDM_REG_CSDM_INT_MASK_0, 0);
6816 REG_WR(bp, CSDM_REG_CSDM_INT_MASK_1, 0);
6817 REG_WR(bp, CCM_REG_CCM_INT_MASK, 0);
6818 /* REG_WR(bp, CSEM_REG_CSEM_INT_MASK_0, 0); */
6819 /* REG_WR(bp, CSEM_REG_CSEM_INT_MASK_1, 0); */
6821 val = PXP2_PXP2_INT_MASK_0_REG_PGL_CPL_AFT |
6822 PXP2_PXP2_INT_MASK_0_REG_PGL_CPL_OF |
6823 PXP2_PXP2_INT_MASK_0_REG_PGL_PCIE_ATTN;
6824 if (!CHIP_IS_E1x(bp))
6825 val |= PXP2_PXP2_INT_MASK_0_REG_PGL_READ_BLOCKED |
6826 PXP2_PXP2_INT_MASK_0_REG_PGL_WRITE_BLOCKED;
6827 REG_WR(bp, PXP2_REG_PXP2_INT_MASK_0, val);
6829 REG_WR(bp, TSDM_REG_TSDM_INT_MASK_0, 0);
6830 REG_WR(bp, TSDM_REG_TSDM_INT_MASK_1, 0);
6831 REG_WR(bp, TCM_REG_TCM_INT_MASK, 0);
6832 /* REG_WR(bp, TSEM_REG_TSEM_INT_MASK_0, 0); */
6834 if (!CHIP_IS_E1x(bp))
6835 /* enable VFC attentions: bits 11 and 12, bits 31:13 reserved */
6836 REG_WR(bp, TSEM_REG_TSEM_INT_MASK_1, 0x07ff);
6838 REG_WR(bp, CDU_REG_CDU_INT_MASK, 0);
6839 REG_WR(bp, DMAE_REG_DMAE_INT_MASK, 0);
6840 /* REG_WR(bp, MISC_REG_MISC_INT_MASK, 0); */
6841 REG_WR(bp, PBF_REG_PBF_INT_MASK, 0x18); /* bit 3,4 masked */
6844 static void bnx2x_reset_common(struct bnx2x *bp)
6849 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_CLEAR,
6852 if (CHIP_IS_E3(bp)) {
6853 val |= MISC_REGISTERS_RESET_REG_2_MSTAT0;
6854 val |= MISC_REGISTERS_RESET_REG_2_MSTAT1;
6857 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR, val);
6860 static void bnx2x_setup_dmae(struct bnx2x *bp)
6863 spin_lock_init(&bp->dmae_lock);
6866 static void bnx2x_init_pxp(struct bnx2x *bp)
6869 int r_order, w_order;
6871 pcie_capability_read_word(bp->pdev, PCI_EXP_DEVCTL, &devctl);
6872 DP(NETIF_MSG_HW, "read 0x%x from devctl\n", devctl);
6873 w_order = ((devctl & PCI_EXP_DEVCTL_PAYLOAD) >> 5);
6875 r_order = ((devctl & PCI_EXP_DEVCTL_READRQ) >> 12);
6877 DP(NETIF_MSG_HW, "force read order to %d\n", bp->mrrs);
6881 bnx2x_init_pxp_arb(bp, r_order, w_order);
6884 static void bnx2x_setup_fan_failure_detection(struct bnx2x *bp)
6894 val = SHMEM_RD(bp, dev_info.shared_hw_config.config2) &
6895 SHARED_HW_CFG_FAN_FAILURE_MASK;
6897 if (val == SHARED_HW_CFG_FAN_FAILURE_ENABLED)
6901 * The fan failure mechanism is usually related to the PHY type since
6902 * the power consumption of the board is affected by the PHY. Currently,
6903 * fan is required for most designs with SFX7101, BCM8727 and BCM8481.
6905 else if (val == SHARED_HW_CFG_FAN_FAILURE_PHY_TYPE)
6906 for (port = PORT_0; port < PORT_MAX; port++) {
6908 bnx2x_fan_failure_det_req(
6910 bp->common.shmem_base,
6911 bp->common.shmem2_base,
6915 DP(NETIF_MSG_HW, "fan detection setting: %d\n", is_required);
6917 if (is_required == 0)
6920 /* Fan failure is indicated by SPIO 5 */
6921 bnx2x_set_spio(bp, MISC_SPIO_SPIO5, MISC_SPIO_INPUT_HI_Z);
6923 /* set to active low mode */
6924 val = REG_RD(bp, MISC_REG_SPIO_INT);
6925 val |= (MISC_SPIO_SPIO5 << MISC_SPIO_INT_OLD_SET_POS);
6926 REG_WR(bp, MISC_REG_SPIO_INT, val);
6928 /* enable interrupt to signal the IGU */
6929 val = REG_RD(bp, MISC_REG_SPIO_EVENT_EN);
6930 val |= MISC_SPIO_SPIO5;
6931 REG_WR(bp, MISC_REG_SPIO_EVENT_EN, val);
6934 void bnx2x_pf_disable(struct bnx2x *bp)
6936 u32 val = REG_RD(bp, IGU_REG_PF_CONFIGURATION);
6937 val &= ~IGU_PF_CONF_FUNC_EN;
6939 REG_WR(bp, IGU_REG_PF_CONFIGURATION, val);
6940 REG_WR(bp, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, 0);
6941 REG_WR(bp, CFC_REG_WEAK_ENABLE_PF, 0);
6944 static void bnx2x__common_init_phy(struct bnx2x *bp)
6946 u32 shmem_base[2], shmem2_base[2];
6947 /* Avoid common init in case MFW supports LFA */
6948 if (SHMEM2_RD(bp, size) >
6949 (u32)offsetof(struct shmem2_region, lfa_host_addr[BP_PORT(bp)]))
6951 shmem_base[0] = bp->common.shmem_base;
6952 shmem2_base[0] = bp->common.shmem2_base;
6953 if (!CHIP_IS_E1x(bp)) {
6955 SHMEM2_RD(bp, other_shmem_base_addr);
6957 SHMEM2_RD(bp, other_shmem2_base_addr);
6959 bnx2x_acquire_phy_lock(bp);
6960 bnx2x_common_init_phy(bp, shmem_base, shmem2_base,
6961 bp->common.chip_id);
6962 bnx2x_release_phy_lock(bp);
6965 static void bnx2x_config_endianity(struct bnx2x *bp, u32 val)
6967 REG_WR(bp, PXP2_REG_RQ_QM_ENDIAN_M, val);
6968 REG_WR(bp, PXP2_REG_RQ_TM_ENDIAN_M, val);
6969 REG_WR(bp, PXP2_REG_RQ_SRC_ENDIAN_M, val);
6970 REG_WR(bp, PXP2_REG_RQ_CDU_ENDIAN_M, val);
6971 REG_WR(bp, PXP2_REG_RQ_DBG_ENDIAN_M, val);
6973 /* make sure this value is 0 */
6974 REG_WR(bp, PXP2_REG_RQ_HC_ENDIAN_M, 0);
6976 REG_WR(bp, PXP2_REG_RD_QM_SWAP_MODE, val);
6977 REG_WR(bp, PXP2_REG_RD_TM_SWAP_MODE, val);
6978 REG_WR(bp, PXP2_REG_RD_SRC_SWAP_MODE, val);
6979 REG_WR(bp, PXP2_REG_RD_CDURD_SWAP_MODE, val);
6982 static void bnx2x_set_endianity(struct bnx2x *bp)
6985 bnx2x_config_endianity(bp, 1);
6987 bnx2x_config_endianity(bp, 0);
6991 static void bnx2x_reset_endianity(struct bnx2x *bp)
6993 bnx2x_config_endianity(bp, 0);
6997 * bnx2x_init_hw_common - initialize the HW at the COMMON phase.
6999 * @bp: driver handle
7001 static int bnx2x_init_hw_common(struct bnx2x *bp)
7005 DP(NETIF_MSG_HW, "starting common init func %d\n", BP_ABS_FUNC(bp));
7008 * take the RESET lock to protect undi_unload flow from accessing
7009 * registers while we're resetting the chip
7011 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_RESET);
7013 bnx2x_reset_common(bp);
7014 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_SET, 0xffffffff);
7017 if (CHIP_IS_E3(bp)) {
7018 val |= MISC_REGISTERS_RESET_REG_2_MSTAT0;
7019 val |= MISC_REGISTERS_RESET_REG_2_MSTAT1;
7021 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_SET, val);
7023 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_RESET);
7025 bnx2x_init_block(bp, BLOCK_MISC, PHASE_COMMON);
7027 if (!CHIP_IS_E1x(bp)) {
7031 * 4-port mode or 2-port mode we need to turn of master-enable
7032 * for everyone, after that, turn it back on for self.
7033 * so, we disregard multi-function or not, and always disable
7034 * for all functions on the given path, this means 0,2,4,6 for
7035 * path 0 and 1,3,5,7 for path 1
7037 for (abs_func_id = BP_PATH(bp);
7038 abs_func_id < E2_FUNC_MAX*2; abs_func_id += 2) {
7039 if (abs_func_id == BP_ABS_FUNC(bp)) {
7041 PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER,
7046 bnx2x_pretend_func(bp, abs_func_id);
7047 /* clear pf enable */
7048 bnx2x_pf_disable(bp);
7049 bnx2x_pretend_func(bp, BP_ABS_FUNC(bp));
7053 bnx2x_init_block(bp, BLOCK_PXP, PHASE_COMMON);
7054 if (CHIP_IS_E1(bp)) {
7055 /* enable HW interrupt from PXP on USDM overflow
7056 bit 16 on INT_MASK_0 */
7057 REG_WR(bp, PXP_REG_PXP_INT_MASK_0, 0);
7060 bnx2x_init_block(bp, BLOCK_PXP2, PHASE_COMMON);
7062 bnx2x_set_endianity(bp);
7063 bnx2x_ilt_init_page_size(bp, INITOP_SET);
7065 if (CHIP_REV_IS_FPGA(bp) && CHIP_IS_E1H(bp))
7066 REG_WR(bp, PXP2_REG_PGL_TAGS_LIMIT, 0x1);
7068 /* let the HW do it's magic ... */
7070 /* finish PXP init */
7071 val = REG_RD(bp, PXP2_REG_RQ_CFG_DONE);
7073 BNX2X_ERR("PXP2 CFG failed\n");
7076 val = REG_RD(bp, PXP2_REG_RD_INIT_DONE);
7078 BNX2X_ERR("PXP2 RD_INIT failed\n");
7082 /* Timers bug workaround E2 only. We need to set the entire ILT to
7083 * have entries with value "0" and valid bit on.
7084 * This needs to be done by the first PF that is loaded in a path
7085 * (i.e. common phase)
7087 if (!CHIP_IS_E1x(bp)) {
7088 /* In E2 there is a bug in the timers block that can cause function 6 / 7
7089 * (i.e. vnic3) to start even if it is marked as "scan-off".
7090 * This occurs when a different function (func2,3) is being marked
7091 * as "scan-off". Real-life scenario for example: if a driver is being
7092 * load-unloaded while func6,7 are down. This will cause the timer to access
7093 * the ilt, translate to a logical address and send a request to read/write.
7094 * Since the ilt for the function that is down is not valid, this will cause
7095 * a translation error which is unrecoverable.
7096 * The Workaround is intended to make sure that when this happens nothing fatal
7097 * will occur. The workaround:
7098 * 1. First PF driver which loads on a path will:
7099 * a. After taking the chip out of reset, by using pretend,
7100 * it will write "0" to the following registers of
7102 * REG_WR(pdev, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, 0);
7103 * REG_WR(pdev, CFC_REG_WEAK_ENABLE_PF,0);
7104 * REG_WR(pdev, CFC_REG_STRONG_ENABLE_PF,0);
7105 * And for itself it will write '1' to
7106 * PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER to enable
7107 * dmae-operations (writing to pram for example.)
7108 * note: can be done for only function 6,7 but cleaner this
7110 * b. Write zero+valid to the entire ILT.
7111 * c. Init the first_timers_ilt_entry, last_timers_ilt_entry of
7112 * VNIC3 (of that port). The range allocated will be the
7113 * entire ILT. This is needed to prevent ILT range error.
7114 * 2. Any PF driver load flow:
7115 * a. ILT update with the physical addresses of the allocated
7117 * b. Wait 20msec. - note that this timeout is needed to make
7118 * sure there are no requests in one of the PXP internal
7119 * queues with "old" ILT addresses.
7120 * c. PF enable in the PGLC.
7121 * d. Clear the was_error of the PF in the PGLC. (could have
7122 * occurred while driver was down)
7123 * e. PF enable in the CFC (WEAK + STRONG)
7124 * f. Timers scan enable
7125 * 3. PF driver unload flow:
7126 * a. Clear the Timers scan_en.
7127 * b. Polling for scan_on=0 for that PF.
7128 * c. Clear the PF enable bit in the PXP.
7129 * d. Clear the PF enable in the CFC (WEAK + STRONG)
7130 * e. Write zero+valid to all ILT entries (The valid bit must
7132 * f. If this is VNIC 3 of a port then also init
7133 * first_timers_ilt_entry to zero and last_timers_ilt_entry
7134 * to the last entry in the ILT.
7137 * Currently the PF error in the PGLC is non recoverable.
7138 * In the future the there will be a recovery routine for this error.
7139 * Currently attention is masked.
7140 * Having an MCP lock on the load/unload process does not guarantee that
7141 * there is no Timer disable during Func6/7 enable. This is because the
7142 * Timers scan is currently being cleared by the MCP on FLR.
7143 * Step 2.d can be done only for PF6/7 and the driver can also check if
7144 * there is error before clearing it. But the flow above is simpler and
7146 * All ILT entries are written by zero+valid and not just PF6/7
7147 * ILT entries since in the future the ILT entries allocation for
7148 * PF-s might be dynamic.
7150 struct ilt_client_info ilt_cli;
7151 struct bnx2x_ilt ilt;
7152 memset(&ilt_cli, 0, sizeof(struct ilt_client_info));
7153 memset(&ilt, 0, sizeof(struct bnx2x_ilt));
7155 /* initialize dummy TM client */
7157 ilt_cli.end = ILT_NUM_PAGE_ENTRIES - 1;
7158 ilt_cli.client_num = ILT_CLIENT_TM;
7160 /* Step 1: set zeroes to all ilt page entries with valid bit on
7161 * Step 2: set the timers first/last ilt entry to point
7162 * to the entire range to prevent ILT range error for 3rd/4th
7163 * vnic (this code assumes existence of the vnic)
7165 * both steps performed by call to bnx2x_ilt_client_init_op()
7166 * with dummy TM client
7168 * we must use pretend since PXP2_REG_RQ_##blk##_FIRST_ILT
7169 * and his brother are split registers
7171 bnx2x_pretend_func(bp, (BP_PATH(bp) + 6));
7172 bnx2x_ilt_client_init_op_ilt(bp, &ilt, &ilt_cli, INITOP_CLEAR);
7173 bnx2x_pretend_func(bp, BP_ABS_FUNC(bp));
7175 REG_WR(bp, PXP2_REG_RQ_DRAM_ALIGN, BNX2X_PXP_DRAM_ALIGN);
7176 REG_WR(bp, PXP2_REG_RQ_DRAM_ALIGN_RD, BNX2X_PXP_DRAM_ALIGN);
7177 REG_WR(bp, PXP2_REG_RQ_DRAM_ALIGN_SEL, 1);
7180 REG_WR(bp, PXP2_REG_RQ_DISABLE_INPUTS, 0);
7181 REG_WR(bp, PXP2_REG_RD_DISABLE_INPUTS, 0);
7183 if (!CHIP_IS_E1x(bp)) {
7184 int factor = CHIP_REV_IS_EMUL(bp) ? 1000 :
7185 (CHIP_REV_IS_FPGA(bp) ? 400 : 0);
7186 bnx2x_init_block(bp, BLOCK_PGLUE_B, PHASE_COMMON);
7188 bnx2x_init_block(bp, BLOCK_ATC, PHASE_COMMON);
7190 /* let the HW do it's magic ... */
7193 val = REG_RD(bp, ATC_REG_ATC_INIT_DONE);
7194 } while (factor-- && (val != 1));
7197 BNX2X_ERR("ATC_INIT failed\n");
7202 bnx2x_init_block(bp, BLOCK_DMAE, PHASE_COMMON);
7204 bnx2x_iov_init_dmae(bp);
7206 /* clean the DMAE memory */
7208 bnx2x_init_fill(bp, TSEM_REG_PRAM, 0, 8, 1);
7210 bnx2x_init_block(bp, BLOCK_TCM, PHASE_COMMON);
7212 bnx2x_init_block(bp, BLOCK_UCM, PHASE_COMMON);
7214 bnx2x_init_block(bp, BLOCK_CCM, PHASE_COMMON);
7216 bnx2x_init_block(bp, BLOCK_XCM, PHASE_COMMON);
7218 bnx2x_read_dmae(bp, XSEM_REG_PASSIVE_BUFFER, 3);
7219 bnx2x_read_dmae(bp, CSEM_REG_PASSIVE_BUFFER, 3);
7220 bnx2x_read_dmae(bp, TSEM_REG_PASSIVE_BUFFER, 3);
7221 bnx2x_read_dmae(bp, USEM_REG_PASSIVE_BUFFER, 3);
7223 bnx2x_init_block(bp, BLOCK_QM, PHASE_COMMON);
7225 /* QM queues pointers table */
7226 bnx2x_qm_init_ptr_table(bp, bp->qm_cid_count, INITOP_SET);
7228 /* soft reset pulse */
7229 REG_WR(bp, QM_REG_SOFT_RESET, 1);
7230 REG_WR(bp, QM_REG_SOFT_RESET, 0);
7232 if (CNIC_SUPPORT(bp))
7233 bnx2x_init_block(bp, BLOCK_TM, PHASE_COMMON);
7235 bnx2x_init_block(bp, BLOCK_DORQ, PHASE_COMMON);
7237 if (!CHIP_REV_IS_SLOW(bp))
7238 /* enable hw interrupt from doorbell Q */
7239 REG_WR(bp, DORQ_REG_DORQ_INT_MASK, 0);
7241 bnx2x_init_block(bp, BLOCK_BRB1, PHASE_COMMON);
7243 bnx2x_init_block(bp, BLOCK_PRS, PHASE_COMMON);
7244 REG_WR(bp, PRS_REG_A_PRSU_20, 0xf);
7246 if (!CHIP_IS_E1(bp))
7247 REG_WR(bp, PRS_REG_E1HOV_MODE, bp->path_has_ovlan);
7249 if (!CHIP_IS_E1x(bp) && !CHIP_IS_E3B0(bp)) {
7250 if (IS_MF_AFEX(bp)) {
7251 /* configure that VNTag and VLAN headers must be
7252 * received in afex mode
7254 REG_WR(bp, PRS_REG_HDRS_AFTER_BASIC, 0xE);
7255 REG_WR(bp, PRS_REG_MUST_HAVE_HDRS, 0xA);
7256 REG_WR(bp, PRS_REG_HDRS_AFTER_TAG_0, 0x6);
7257 REG_WR(bp, PRS_REG_TAG_ETHERTYPE_0, 0x8926);
7258 REG_WR(bp, PRS_REG_TAG_LEN_0, 0x4);
7260 /* Bit-map indicating which L2 hdrs may appear
7261 * after the basic Ethernet header
7263 REG_WR(bp, PRS_REG_HDRS_AFTER_BASIC,
7264 bp->path_has_ovlan ? 7 : 6);
7268 bnx2x_init_block(bp, BLOCK_TSDM, PHASE_COMMON);
7269 bnx2x_init_block(bp, BLOCK_CSDM, PHASE_COMMON);
7270 bnx2x_init_block(bp, BLOCK_USDM, PHASE_COMMON);
7271 bnx2x_init_block(bp, BLOCK_XSDM, PHASE_COMMON);
7273 if (!CHIP_IS_E1x(bp)) {
7274 /* reset VFC memories */
7275 REG_WR(bp, TSEM_REG_FAST_MEMORY + VFC_REG_MEMORIES_RST,
7276 VFC_MEMORIES_RST_REG_CAM_RST |
7277 VFC_MEMORIES_RST_REG_RAM_RST);
7278 REG_WR(bp, XSEM_REG_FAST_MEMORY + VFC_REG_MEMORIES_RST,
7279 VFC_MEMORIES_RST_REG_CAM_RST |
7280 VFC_MEMORIES_RST_REG_RAM_RST);
7285 bnx2x_init_block(bp, BLOCK_TSEM, PHASE_COMMON);
7286 bnx2x_init_block(bp, BLOCK_USEM, PHASE_COMMON);
7287 bnx2x_init_block(bp, BLOCK_CSEM, PHASE_COMMON);
7288 bnx2x_init_block(bp, BLOCK_XSEM, PHASE_COMMON);
7291 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_CLEAR,
7293 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_SET,
7296 bnx2x_init_block(bp, BLOCK_UPB, PHASE_COMMON);
7297 bnx2x_init_block(bp, BLOCK_XPB, PHASE_COMMON);
7298 bnx2x_init_block(bp, BLOCK_PBF, PHASE_COMMON);
7300 if (!CHIP_IS_E1x(bp)) {
7301 if (IS_MF_AFEX(bp)) {
7302 /* configure that VNTag and VLAN headers must be
7305 REG_WR(bp, PBF_REG_HDRS_AFTER_BASIC, 0xE);
7306 REG_WR(bp, PBF_REG_MUST_HAVE_HDRS, 0xA);
7307 REG_WR(bp, PBF_REG_HDRS_AFTER_TAG_0, 0x6);
7308 REG_WR(bp, PBF_REG_TAG_ETHERTYPE_0, 0x8926);
7309 REG_WR(bp, PBF_REG_TAG_LEN_0, 0x4);
7311 REG_WR(bp, PBF_REG_HDRS_AFTER_BASIC,
7312 bp->path_has_ovlan ? 7 : 6);
7316 REG_WR(bp, SRC_REG_SOFT_RST, 1);
7318 bnx2x_init_block(bp, BLOCK_SRC, PHASE_COMMON);
7320 if (CNIC_SUPPORT(bp)) {
7321 REG_WR(bp, SRC_REG_KEYSEARCH_0, 0x63285672);
7322 REG_WR(bp, SRC_REG_KEYSEARCH_1, 0x24b8f2cc);
7323 REG_WR(bp, SRC_REG_KEYSEARCH_2, 0x223aef9b);
7324 REG_WR(bp, SRC_REG_KEYSEARCH_3, 0x26001e3a);
7325 REG_WR(bp, SRC_REG_KEYSEARCH_4, 0x7ae91116);
7326 REG_WR(bp, SRC_REG_KEYSEARCH_5, 0x5ce5230b);
7327 REG_WR(bp, SRC_REG_KEYSEARCH_6, 0x298d8adf);
7328 REG_WR(bp, SRC_REG_KEYSEARCH_7, 0x6eb0ff09);
7329 REG_WR(bp, SRC_REG_KEYSEARCH_8, 0x1830f82f);
7330 REG_WR(bp, SRC_REG_KEYSEARCH_9, 0x01e46be7);
7332 REG_WR(bp, SRC_REG_SOFT_RST, 0);
7334 if (sizeof(union cdu_context) != 1024)
7335 /* we currently assume that a context is 1024 bytes */
7336 dev_alert(&bp->pdev->dev,
7337 "please adjust the size of cdu_context(%ld)\n",
7338 (long)sizeof(union cdu_context));
7340 bnx2x_init_block(bp, BLOCK_CDU, PHASE_COMMON);
7341 val = (4 << 24) + (0 << 12) + 1024;
7342 REG_WR(bp, CDU_REG_CDU_GLOBAL_PARAMS, val);
7344 bnx2x_init_block(bp, BLOCK_CFC, PHASE_COMMON);
7345 REG_WR(bp, CFC_REG_INIT_REG, 0x7FF);
7346 /* enable context validation interrupt from CFC */
7347 REG_WR(bp, CFC_REG_CFC_INT_MASK, 0);
7349 /* set the thresholds to prevent CFC/CDU race */
7350 REG_WR(bp, CFC_REG_DEBUG0, 0x20020000);
7352 bnx2x_init_block(bp, BLOCK_HC, PHASE_COMMON);
7354 if (!CHIP_IS_E1x(bp) && BP_NOMCP(bp))
7355 REG_WR(bp, IGU_REG_RESET_MEMORIES, 0x36);
7357 bnx2x_init_block(bp, BLOCK_IGU, PHASE_COMMON);
7358 bnx2x_init_block(bp, BLOCK_MISC_AEU, PHASE_COMMON);
7360 /* Reset PCIE errors for debug */
7361 REG_WR(bp, 0x2814, 0xffffffff);
7362 REG_WR(bp, 0x3820, 0xffffffff);
7364 if (!CHIP_IS_E1x(bp)) {
7365 REG_WR(bp, PCICFG_OFFSET + PXPCS_TL_CONTROL_5,
7366 (PXPCS_TL_CONTROL_5_ERR_UNSPPORT1 |
7367 PXPCS_TL_CONTROL_5_ERR_UNSPPORT));
7368 REG_WR(bp, PCICFG_OFFSET + PXPCS_TL_FUNC345_STAT,
7369 (PXPCS_TL_FUNC345_STAT_ERR_UNSPPORT4 |
7370 PXPCS_TL_FUNC345_STAT_ERR_UNSPPORT3 |
7371 PXPCS_TL_FUNC345_STAT_ERR_UNSPPORT2));
7372 REG_WR(bp, PCICFG_OFFSET + PXPCS_TL_FUNC678_STAT,
7373 (PXPCS_TL_FUNC678_STAT_ERR_UNSPPORT7 |
7374 PXPCS_TL_FUNC678_STAT_ERR_UNSPPORT6 |
7375 PXPCS_TL_FUNC678_STAT_ERR_UNSPPORT5));
7378 bnx2x_init_block(bp, BLOCK_NIG, PHASE_COMMON);
7379 if (!CHIP_IS_E1(bp)) {
7380 /* in E3 this done in per-port section */
7381 if (!CHIP_IS_E3(bp))
7382 REG_WR(bp, NIG_REG_LLH_MF_MODE, IS_MF(bp));
7384 if (CHIP_IS_E1H(bp))
7385 /* not applicable for E2 (and above ...) */
7386 REG_WR(bp, NIG_REG_LLH_E1HOV_MODE, IS_MF_SD(bp));
7388 if (CHIP_REV_IS_SLOW(bp))
7391 /* finish CFC init */
7392 val = reg_poll(bp, CFC_REG_LL_INIT_DONE, 1, 100, 10);
7394 BNX2X_ERR("CFC LL_INIT failed\n");
7397 val = reg_poll(bp, CFC_REG_AC_INIT_DONE, 1, 100, 10);
7399 BNX2X_ERR("CFC AC_INIT failed\n");
7402 val = reg_poll(bp, CFC_REG_CAM_INIT_DONE, 1, 100, 10);
7404 BNX2X_ERR("CFC CAM_INIT failed\n");
7407 REG_WR(bp, CFC_REG_DEBUG0, 0);
7409 if (CHIP_IS_E1(bp)) {
7410 /* read NIG statistic
7411 to see if this is our first up since powerup */
7412 bnx2x_read_dmae(bp, NIG_REG_STAT2_BRB_OCTET, 2);
7413 val = *bnx2x_sp(bp, wb_data[0]);
7415 /* do internal memory self test */
7416 if ((val == 0) && bnx2x_int_mem_test(bp)) {
7417 BNX2X_ERR("internal mem self test failed\n");
7422 bnx2x_setup_fan_failure_detection(bp);
7424 /* clear PXP2 attentions */
7425 REG_RD(bp, PXP2_REG_PXP2_INT_STS_CLR_0);
7427 bnx2x_enable_blocks_attention(bp);
7428 bnx2x_enable_blocks_parity(bp);
7430 if (!BP_NOMCP(bp)) {
7431 if (CHIP_IS_E1x(bp))
7432 bnx2x__common_init_phy(bp);
7434 BNX2X_ERR("Bootcode is missing - can not initialize link\n");
7436 if (SHMEM2_HAS(bp, netproc_fw_ver))
7437 SHMEM2_WR(bp, netproc_fw_ver, REG_RD(bp, XSEM_REG_PRAM));
7443 * bnx2x_init_hw_common_chip - init HW at the COMMON_CHIP phase.
7445 * @bp: driver handle
7447 static int bnx2x_init_hw_common_chip(struct bnx2x *bp)
7449 int rc = bnx2x_init_hw_common(bp);
7454 /* In E2 2-PORT mode, same ext phy is used for the two paths */
7456 bnx2x__common_init_phy(bp);
7461 static int bnx2x_init_hw_port(struct bnx2x *bp)
7463 int port = BP_PORT(bp);
7464 int init_phase = port ? PHASE_PORT1 : PHASE_PORT0;
7468 DP(NETIF_MSG_HW, "starting port init port %d\n", port);
7470 REG_WR(bp, NIG_REG_MASK_INTERRUPT_PORT0 + port*4, 0);
7472 bnx2x_init_block(bp, BLOCK_MISC, init_phase);
7473 bnx2x_init_block(bp, BLOCK_PXP, init_phase);
7474 bnx2x_init_block(bp, BLOCK_PXP2, init_phase);
7476 /* Timers bug workaround: disables the pf_master bit in pglue at
7477 * common phase, we need to enable it here before any dmae access are
7478 * attempted. Therefore we manually added the enable-master to the
7479 * port phase (it also happens in the function phase)
7481 if (!CHIP_IS_E1x(bp))
7482 REG_WR(bp, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, 1);
7484 bnx2x_init_block(bp, BLOCK_ATC, init_phase);
7485 bnx2x_init_block(bp, BLOCK_DMAE, init_phase);
7486 bnx2x_init_block(bp, BLOCK_PGLUE_B, init_phase);
7487 bnx2x_init_block(bp, BLOCK_QM, init_phase);
7489 bnx2x_init_block(bp, BLOCK_TCM, init_phase);
7490 bnx2x_init_block(bp, BLOCK_UCM, init_phase);
7491 bnx2x_init_block(bp, BLOCK_CCM, init_phase);
7492 bnx2x_init_block(bp, BLOCK_XCM, init_phase);
7494 /* QM cid (connection) count */
7495 bnx2x_qm_init_cid_count(bp, bp->qm_cid_count, INITOP_SET);
7497 if (CNIC_SUPPORT(bp)) {
7498 bnx2x_init_block(bp, BLOCK_TM, init_phase);
7499 REG_WR(bp, TM_REG_LIN0_SCAN_TIME + port*4, 20);
7500 REG_WR(bp, TM_REG_LIN0_MAX_ACTIVE_CID + port*4, 31);
7503 bnx2x_init_block(bp, BLOCK_DORQ, init_phase);
7505 bnx2x_init_block(bp, BLOCK_BRB1, init_phase);
7507 if (CHIP_IS_E1(bp) || CHIP_IS_E1H(bp)) {
7510 low = ((bp->flags & ONE_PORT_FLAG) ? 160 : 246);
7511 else if (bp->dev->mtu > 4096) {
7512 if (bp->flags & ONE_PORT_FLAG)
7516 /* (24*1024 + val*4)/256 */
7517 low = 96 + (val/64) +
7518 ((val % 64) ? 1 : 0);
7521 low = ((bp->flags & ONE_PORT_FLAG) ? 80 : 160);
7522 high = low + 56; /* 14*1024/256 */
7523 REG_WR(bp, BRB1_REG_PAUSE_LOW_THRESHOLD_0 + port*4, low);
7524 REG_WR(bp, BRB1_REG_PAUSE_HIGH_THRESHOLD_0 + port*4, high);
7527 if (CHIP_MODE_IS_4_PORT(bp))
7528 REG_WR(bp, (BP_PORT(bp) ?
7529 BRB1_REG_MAC_GUARANTIED_1 :
7530 BRB1_REG_MAC_GUARANTIED_0), 40);
7532 bnx2x_init_block(bp, BLOCK_PRS, init_phase);
7533 if (CHIP_IS_E3B0(bp)) {
7534 if (IS_MF_AFEX(bp)) {
7535 /* configure headers for AFEX mode */
7536 REG_WR(bp, BP_PORT(bp) ?
7537 PRS_REG_HDRS_AFTER_BASIC_PORT_1 :
7538 PRS_REG_HDRS_AFTER_BASIC_PORT_0, 0xE);
7539 REG_WR(bp, BP_PORT(bp) ?
7540 PRS_REG_HDRS_AFTER_TAG_0_PORT_1 :
7541 PRS_REG_HDRS_AFTER_TAG_0_PORT_0, 0x6);
7542 REG_WR(bp, BP_PORT(bp) ?
7543 PRS_REG_MUST_HAVE_HDRS_PORT_1 :
7544 PRS_REG_MUST_HAVE_HDRS_PORT_0, 0xA);
7546 /* Ovlan exists only if we are in multi-function +
7547 * switch-dependent mode, in switch-independent there
7548 * is no ovlan headers
7550 REG_WR(bp, BP_PORT(bp) ?
7551 PRS_REG_HDRS_AFTER_BASIC_PORT_1 :
7552 PRS_REG_HDRS_AFTER_BASIC_PORT_0,
7553 (bp->path_has_ovlan ? 7 : 6));
7557 bnx2x_init_block(bp, BLOCK_TSDM, init_phase);
7558 bnx2x_init_block(bp, BLOCK_CSDM, init_phase);
7559 bnx2x_init_block(bp, BLOCK_USDM, init_phase);
7560 bnx2x_init_block(bp, BLOCK_XSDM, init_phase);
7562 bnx2x_init_block(bp, BLOCK_TSEM, init_phase);
7563 bnx2x_init_block(bp, BLOCK_USEM, init_phase);
7564 bnx2x_init_block(bp, BLOCK_CSEM, init_phase);
7565 bnx2x_init_block(bp, BLOCK_XSEM, init_phase);
7567 bnx2x_init_block(bp, BLOCK_UPB, init_phase);
7568 bnx2x_init_block(bp, BLOCK_XPB, init_phase);
7570 bnx2x_init_block(bp, BLOCK_PBF, init_phase);
7572 if (CHIP_IS_E1x(bp)) {
7573 /* configure PBF to work without PAUSE mtu 9000 */
7574 REG_WR(bp, PBF_REG_P0_PAUSE_ENABLE + port*4, 0);
7576 /* update threshold */
7577 REG_WR(bp, PBF_REG_P0_ARB_THRSH + port*4, (9040/16));
7578 /* update init credit */
7579 REG_WR(bp, PBF_REG_P0_INIT_CRD + port*4, (9040/16) + 553 - 22);
7582 REG_WR(bp, PBF_REG_INIT_P0 + port*4, 1);
7584 REG_WR(bp, PBF_REG_INIT_P0 + port*4, 0);
7587 if (CNIC_SUPPORT(bp))
7588 bnx2x_init_block(bp, BLOCK_SRC, init_phase);
7590 bnx2x_init_block(bp, BLOCK_CDU, init_phase);
7591 bnx2x_init_block(bp, BLOCK_CFC, init_phase);
7593 if (CHIP_IS_E1(bp)) {
7594 REG_WR(bp, HC_REG_LEADING_EDGE_0 + port*8, 0);
7595 REG_WR(bp, HC_REG_TRAILING_EDGE_0 + port*8, 0);
7597 bnx2x_init_block(bp, BLOCK_HC, init_phase);
7599 bnx2x_init_block(bp, BLOCK_IGU, init_phase);
7601 bnx2x_init_block(bp, BLOCK_MISC_AEU, init_phase);
7602 /* init aeu_mask_attn_func_0/1:
7603 * - SF mode: bits 3-7 are masked. Only bits 0-2 are in use
7604 * - MF mode: bit 3 is masked. Bits 0-2 are in use as in SF
7605 * bits 4-7 are used for "per vn group attention" */
7606 val = IS_MF(bp) ? 0xF7 : 0x7;
7607 /* Enable DCBX attention for all but E1 */
7608 val |= CHIP_IS_E1(bp) ? 0 : 0x10;
7609 REG_WR(bp, MISC_REG_AEU_MASK_ATTN_FUNC_0 + port*4, val);
7611 /* SCPAD_PARITY should NOT trigger close the gates */
7612 reg = port ? MISC_REG_AEU_ENABLE4_NIG_1 : MISC_REG_AEU_ENABLE4_NIG_0;
7615 ~AEU_INPUTS_ATTN_BITS_MCP_LATCHED_SCPAD_PARITY);
7617 reg = port ? MISC_REG_AEU_ENABLE4_PXP_1 : MISC_REG_AEU_ENABLE4_PXP_0;
7620 ~AEU_INPUTS_ATTN_BITS_MCP_LATCHED_SCPAD_PARITY);
7622 bnx2x_init_block(bp, BLOCK_NIG, init_phase);
7624 if (!CHIP_IS_E1x(bp)) {
7625 /* Bit-map indicating which L2 hdrs may appear after the
7626 * basic Ethernet header
7629 REG_WR(bp, BP_PORT(bp) ?
7630 NIG_REG_P1_HDRS_AFTER_BASIC :
7631 NIG_REG_P0_HDRS_AFTER_BASIC, 0xE);
7633 REG_WR(bp, BP_PORT(bp) ?
7634 NIG_REG_P1_HDRS_AFTER_BASIC :
7635 NIG_REG_P0_HDRS_AFTER_BASIC,
7636 IS_MF_SD(bp) ? 7 : 6);
7639 REG_WR(bp, BP_PORT(bp) ?
7640 NIG_REG_LLH1_MF_MODE :
7641 NIG_REG_LLH_MF_MODE, IS_MF(bp));
7643 if (!CHIP_IS_E3(bp))
7644 REG_WR(bp, NIG_REG_XGXS_SERDES0_MODE_SEL + port*4, 1);
7646 if (!CHIP_IS_E1(bp)) {
7647 /* 0x2 disable mf_ov, 0x1 enable */
7648 REG_WR(bp, NIG_REG_LLH0_BRB1_DRV_MASK_MF + port*4,
7649 (IS_MF_SD(bp) ? 0x1 : 0x2));
7651 if (!CHIP_IS_E1x(bp)) {
7653 switch (bp->mf_mode) {
7654 case MULTI_FUNCTION_SD:
7657 case MULTI_FUNCTION_SI:
7658 case MULTI_FUNCTION_AFEX:
7663 REG_WR(bp, (BP_PORT(bp) ? NIG_REG_LLH1_CLS_TYPE :
7664 NIG_REG_LLH0_CLS_TYPE), val);
7667 REG_WR(bp, NIG_REG_LLFC_ENABLE_0 + port*4, 0);
7668 REG_WR(bp, NIG_REG_LLFC_OUT_EN_0 + port*4, 0);
7669 REG_WR(bp, NIG_REG_PAUSE_ENABLE_0 + port*4, 1);
7673 /* If SPIO5 is set to generate interrupts, enable it for this port */
7674 val = REG_RD(bp, MISC_REG_SPIO_EVENT_EN);
7675 if (val & MISC_SPIO_SPIO5) {
7676 u32 reg_addr = (port ? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_0 :
7677 MISC_REG_AEU_ENABLE1_FUNC_0_OUT_0);
7678 val = REG_RD(bp, reg_addr);
7679 val |= AEU_INPUTS_ATTN_BITS_SPIO5;
7680 REG_WR(bp, reg_addr, val);
7686 static void bnx2x_ilt_wr(struct bnx2x *bp, u32 index, dma_addr_t addr)
7692 reg = PXP2_REG_RQ_ONCHIP_AT + index*8;
7694 reg = PXP2_REG_RQ_ONCHIP_AT_B0 + index*8;
7696 wb_write[0] = ONCHIP_ADDR1(addr);
7697 wb_write[1] = ONCHIP_ADDR2(addr);
7698 REG_WR_DMAE(bp, reg, wb_write, 2);
7701 void bnx2x_igu_clear_sb_gen(struct bnx2x *bp, u8 func, u8 idu_sb_id, bool is_pf)
7703 u32 data, ctl, cnt = 100;
7704 u32 igu_addr_data = IGU_REG_COMMAND_REG_32LSB_DATA;
7705 u32 igu_addr_ctl = IGU_REG_COMMAND_REG_CTRL;
7706 u32 igu_addr_ack = IGU_REG_CSTORM_TYPE_0_SB_CLEANUP + (idu_sb_id/32)*4;
7707 u32 sb_bit = 1 << (idu_sb_id%32);
7708 u32 func_encode = func | (is_pf ? 1 : 0) << IGU_FID_ENCODE_IS_PF_SHIFT;
7709 u32 addr_encode = IGU_CMD_E2_PROD_UPD_BASE + idu_sb_id;
7711 /* Not supported in BC mode */
7712 if (CHIP_INT_MODE_IS_BC(bp))
7715 data = (IGU_USE_REGISTER_cstorm_type_0_sb_cleanup
7716 << IGU_REGULAR_CLEANUP_TYPE_SHIFT) |
7717 IGU_REGULAR_CLEANUP_SET |
7718 IGU_REGULAR_BCLEANUP;
7720 ctl = addr_encode << IGU_CTRL_REG_ADDRESS_SHIFT |
7721 func_encode << IGU_CTRL_REG_FID_SHIFT |
7722 IGU_CTRL_CMD_TYPE_WR << IGU_CTRL_REG_TYPE_SHIFT;
7724 DP(NETIF_MSG_HW, "write 0x%08x to IGU(via GRC) addr 0x%x\n",
7725 data, igu_addr_data);
7726 REG_WR(bp, igu_addr_data, data);
7729 DP(NETIF_MSG_HW, "write 0x%08x to IGU(via GRC) addr 0x%x\n",
7731 REG_WR(bp, igu_addr_ctl, ctl);
7735 /* wait for clean up to finish */
7736 while (!(REG_RD(bp, igu_addr_ack) & sb_bit) && --cnt)
7739 if (!(REG_RD(bp, igu_addr_ack) & sb_bit)) {
7741 "Unable to finish IGU cleanup: idu_sb_id %d offset %d bit %d (cnt %d)\n",
7742 idu_sb_id, idu_sb_id/32, idu_sb_id%32, cnt);
7746 static void bnx2x_igu_clear_sb(struct bnx2x *bp, u8 idu_sb_id)
7748 bnx2x_igu_clear_sb_gen(bp, BP_FUNC(bp), idu_sb_id, true /*PF*/);
7751 static void bnx2x_clear_func_ilt(struct bnx2x *bp, u32 func)
7753 u32 i, base = FUNC_ILT_BASE(func);
7754 for (i = base; i < base + ILT_PER_FUNC; i++)
7755 bnx2x_ilt_wr(bp, i, 0);
7758 static void bnx2x_init_searcher(struct bnx2x *bp)
7760 int port = BP_PORT(bp);
7761 bnx2x_src_init_t2(bp, bp->t2, bp->t2_mapping, SRC_CONN_NUM);
7762 /* T1 hash bits value determines the T1 number of entries */
7763 REG_WR(bp, SRC_REG_NUMBER_HASH_BITS0 + port*4, SRC_HASH_BITS);
7766 static inline int bnx2x_func_switch_update(struct bnx2x *bp, int suspend)
7769 struct bnx2x_func_state_params func_params = {NULL};
7770 struct bnx2x_func_switch_update_params *switch_update_params =
7771 &func_params.params.switch_update;
7773 /* Prepare parameters for function state transitions */
7774 __set_bit(RAMROD_COMP_WAIT, &func_params.ramrod_flags);
7775 __set_bit(RAMROD_RETRY, &func_params.ramrod_flags);
7777 func_params.f_obj = &bp->func_obj;
7778 func_params.cmd = BNX2X_F_CMD_SWITCH_UPDATE;
7780 /* Function parameters */
7781 __set_bit(BNX2X_F_UPDATE_TX_SWITCH_SUSPEND_CHNG,
7782 &switch_update_params->changes);
7784 __set_bit(BNX2X_F_UPDATE_TX_SWITCH_SUSPEND,
7785 &switch_update_params->changes);
7787 rc = bnx2x_func_state_change(bp, &func_params);
7792 static int bnx2x_reset_nic_mode(struct bnx2x *bp)
7794 int rc, i, port = BP_PORT(bp);
7795 int vlan_en = 0, mac_en[NUM_MACS];
7797 /* Close input from network */
7798 if (bp->mf_mode == SINGLE_FUNCTION) {
7799 bnx2x_set_rx_filter(&bp->link_params, 0);
7801 vlan_en = REG_RD(bp, port ? NIG_REG_LLH1_FUNC_EN :
7802 NIG_REG_LLH0_FUNC_EN);
7803 REG_WR(bp, port ? NIG_REG_LLH1_FUNC_EN :
7804 NIG_REG_LLH0_FUNC_EN, 0);
7805 for (i = 0; i < NUM_MACS; i++) {
7806 mac_en[i] = REG_RD(bp, port ?
7807 (NIG_REG_LLH1_FUNC_MEM_ENABLE +
7809 (NIG_REG_LLH0_FUNC_MEM_ENABLE +
7811 REG_WR(bp, port ? (NIG_REG_LLH1_FUNC_MEM_ENABLE +
7813 (NIG_REG_LLH0_FUNC_MEM_ENABLE + 4 * i), 0);
7817 /* Close BMC to host */
7818 REG_WR(bp, port ? NIG_REG_P0_TX_MNG_HOST_ENABLE :
7819 NIG_REG_P1_TX_MNG_HOST_ENABLE, 0);
7821 /* Suspend Tx switching to the PF. Completion of this ramrod
7822 * further guarantees that all the packets of that PF / child
7823 * VFs in BRB were processed by the Parser, so it is safe to
7824 * change the NIC_MODE register.
7826 rc = bnx2x_func_switch_update(bp, 1);
7828 BNX2X_ERR("Can't suspend tx-switching!\n");
7832 /* Change NIC_MODE register */
7833 REG_WR(bp, PRS_REG_NIC_MODE, 0);
7835 /* Open input from network */
7836 if (bp->mf_mode == SINGLE_FUNCTION) {
7837 bnx2x_set_rx_filter(&bp->link_params, 1);
7839 REG_WR(bp, port ? NIG_REG_LLH1_FUNC_EN :
7840 NIG_REG_LLH0_FUNC_EN, vlan_en);
7841 for (i = 0; i < NUM_MACS; i++) {
7842 REG_WR(bp, port ? (NIG_REG_LLH1_FUNC_MEM_ENABLE +
7844 (NIG_REG_LLH0_FUNC_MEM_ENABLE + 4 * i),
7849 /* Enable BMC to host */
7850 REG_WR(bp, port ? NIG_REG_P0_TX_MNG_HOST_ENABLE :
7851 NIG_REG_P1_TX_MNG_HOST_ENABLE, 1);
7853 /* Resume Tx switching to the PF */
7854 rc = bnx2x_func_switch_update(bp, 0);
7856 BNX2X_ERR("Can't resume tx-switching!\n");
7860 DP(NETIF_MSG_IFUP, "NIC MODE disabled\n");
7864 int bnx2x_init_hw_func_cnic(struct bnx2x *bp)
7868 bnx2x_ilt_init_op_cnic(bp, INITOP_SET);
7870 if (CONFIGURE_NIC_MODE(bp)) {
7871 /* Configure searcher as part of function hw init */
7872 bnx2x_init_searcher(bp);
7874 /* Reset NIC mode */
7875 rc = bnx2x_reset_nic_mode(bp);
7877 BNX2X_ERR("Can't change NIC mode!\n");
7884 /* previous driver DMAE transaction may have occurred when pre-boot stage ended
7885 * and boot began, or when kdump kernel was loaded. Either case would invalidate
7886 * the addresses of the transaction, resulting in was-error bit set in the pci
7887 * causing all hw-to-host pcie transactions to timeout. If this happened we want
7888 * to clear the interrupt which detected this from the pglueb and the was done
7891 static void bnx2x_clean_pglue_errors(struct bnx2x *bp)
7893 if (!CHIP_IS_E1x(bp))
7894 REG_WR(bp, PGLUE_B_REG_WAS_ERROR_PF_7_0_CLR,
7895 1 << BP_ABS_FUNC(bp));
7898 static int bnx2x_init_hw_func(struct bnx2x *bp)
7900 int port = BP_PORT(bp);
7901 int func = BP_FUNC(bp);
7902 int init_phase = PHASE_PF0 + func;
7903 struct bnx2x_ilt *ilt = BP_ILT(bp);
7906 u32 main_mem_base, main_mem_size, main_mem_prty_clr;
7907 int i, main_mem_width, rc;
7909 DP(NETIF_MSG_HW, "starting func init func %d\n", func);
7911 /* FLR cleanup - hmmm */
7912 if (!CHIP_IS_E1x(bp)) {
7913 rc = bnx2x_pf_flr_clnup(bp);
7920 /* set MSI reconfigure capability */
7921 if (bp->common.int_block == INT_BLOCK_HC) {
7922 addr = (port ? HC_REG_CONFIG_1 : HC_REG_CONFIG_0);
7923 val = REG_RD(bp, addr);
7924 val |= HC_CONFIG_0_REG_MSI_ATTN_EN_0;
7925 REG_WR(bp, addr, val);
7928 bnx2x_init_block(bp, BLOCK_PXP, init_phase);
7929 bnx2x_init_block(bp, BLOCK_PXP2, init_phase);
7932 cdu_ilt_start = ilt->clients[ILT_CLIENT_CDU].start;
7935 cdu_ilt_start += BNX2X_FIRST_VF_CID/ILT_PAGE_CIDS;
7936 cdu_ilt_start = bnx2x_iov_init_ilt(bp, cdu_ilt_start);
7938 /* since BNX2X_FIRST_VF_CID > 0 the PF L2 cids precedes
7939 * those of the VFs, so start line should be reset
7941 cdu_ilt_start = ilt->clients[ILT_CLIENT_CDU].start;
7942 for (i = 0; i < L2_ILT_LINES(bp); i++) {
7943 ilt->lines[cdu_ilt_start + i].page = bp->context[i].vcxt;
7944 ilt->lines[cdu_ilt_start + i].page_mapping =
7945 bp->context[i].cxt_mapping;
7946 ilt->lines[cdu_ilt_start + i].size = bp->context[i].size;
7949 bnx2x_ilt_init_op(bp, INITOP_SET);
7951 if (!CONFIGURE_NIC_MODE(bp)) {
7952 bnx2x_init_searcher(bp);
7953 REG_WR(bp, PRS_REG_NIC_MODE, 0);
7954 DP(NETIF_MSG_IFUP, "NIC MODE disabled\n");
7957 REG_WR(bp, PRS_REG_NIC_MODE, 1);
7958 DP(NETIF_MSG_IFUP, "NIC MODE configured\n");
7961 if (!CHIP_IS_E1x(bp)) {
7962 u32 pf_conf = IGU_PF_CONF_FUNC_EN;
7964 /* Turn on a single ISR mode in IGU if driver is going to use
7967 if (!(bp->flags & USING_MSIX_FLAG))
7968 pf_conf |= IGU_PF_CONF_SINGLE_ISR_EN;
7970 * Timers workaround bug: function init part.
7971 * Need to wait 20msec after initializing ILT,
7972 * needed to make sure there are no requests in
7973 * one of the PXP internal queues with "old" ILT addresses
7977 * Master enable - Due to WB DMAE writes performed before this
7978 * register is re-initialized as part of the regular function
7981 REG_WR(bp, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, 1);
7982 /* Enable the function in IGU */
7983 REG_WR(bp, IGU_REG_PF_CONFIGURATION, pf_conf);
7988 bnx2x_init_block(bp, BLOCK_PGLUE_B, init_phase);
7990 bnx2x_clean_pglue_errors(bp);
7992 bnx2x_init_block(bp, BLOCK_ATC, init_phase);
7993 bnx2x_init_block(bp, BLOCK_DMAE, init_phase);
7994 bnx2x_init_block(bp, BLOCK_NIG, init_phase);
7995 bnx2x_init_block(bp, BLOCK_SRC, init_phase);
7996 bnx2x_init_block(bp, BLOCK_MISC, init_phase);
7997 bnx2x_init_block(bp, BLOCK_TCM, init_phase);
7998 bnx2x_init_block(bp, BLOCK_UCM, init_phase);
7999 bnx2x_init_block(bp, BLOCK_CCM, init_phase);
8000 bnx2x_init_block(bp, BLOCK_XCM, init_phase);
8001 bnx2x_init_block(bp, BLOCK_TSEM, init_phase);
8002 bnx2x_init_block(bp, BLOCK_USEM, init_phase);
8003 bnx2x_init_block(bp, BLOCK_CSEM, init_phase);
8004 bnx2x_init_block(bp, BLOCK_XSEM, init_phase);
8006 if (!CHIP_IS_E1x(bp))
8007 REG_WR(bp, QM_REG_PF_EN, 1);
8009 if (!CHIP_IS_E1x(bp)) {
8010 REG_WR(bp, TSEM_REG_VFPF_ERR_NUM, BNX2X_MAX_NUM_OF_VFS + func);
8011 REG_WR(bp, USEM_REG_VFPF_ERR_NUM, BNX2X_MAX_NUM_OF_VFS + func);
8012 REG_WR(bp, CSEM_REG_VFPF_ERR_NUM, BNX2X_MAX_NUM_OF_VFS + func);
8013 REG_WR(bp, XSEM_REG_VFPF_ERR_NUM, BNX2X_MAX_NUM_OF_VFS + func);
8015 bnx2x_init_block(bp, BLOCK_QM, init_phase);
8017 bnx2x_init_block(bp, BLOCK_TM, init_phase);
8018 bnx2x_init_block(bp, BLOCK_DORQ, init_phase);
8019 REG_WR(bp, DORQ_REG_MODE_ACT, 1); /* no dpm */
8021 bnx2x_iov_init_dq(bp);
8023 bnx2x_init_block(bp, BLOCK_BRB1, init_phase);
8024 bnx2x_init_block(bp, BLOCK_PRS, init_phase);
8025 bnx2x_init_block(bp, BLOCK_TSDM, init_phase);
8026 bnx2x_init_block(bp, BLOCK_CSDM, init_phase);
8027 bnx2x_init_block(bp, BLOCK_USDM, init_phase);
8028 bnx2x_init_block(bp, BLOCK_XSDM, init_phase);
8029 bnx2x_init_block(bp, BLOCK_UPB, init_phase);
8030 bnx2x_init_block(bp, BLOCK_XPB, init_phase);
8031 bnx2x_init_block(bp, BLOCK_PBF, init_phase);
8032 if (!CHIP_IS_E1x(bp))
8033 REG_WR(bp, PBF_REG_DISABLE_PF, 0);
8035 bnx2x_init_block(bp, BLOCK_CDU, init_phase);
8037 bnx2x_init_block(bp, BLOCK_CFC, init_phase);
8039 if (!CHIP_IS_E1x(bp))
8040 REG_WR(bp, CFC_REG_WEAK_ENABLE_PF, 1);
8043 if (!(IS_MF_UFP(bp) && BNX2X_IS_MF_SD_PROTOCOL_FCOE(bp))) {
8044 REG_WR(bp, NIG_REG_LLH0_FUNC_EN + port * 8, 1);
8045 REG_WR(bp, NIG_REG_LLH0_FUNC_VLAN_ID + port * 8,
8050 bnx2x_init_block(bp, BLOCK_MISC_AEU, init_phase);
8052 /* HC init per function */
8053 if (bp->common.int_block == INT_BLOCK_HC) {
8054 if (CHIP_IS_E1H(bp)) {
8055 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_12 + func*4, 0);
8057 REG_WR(bp, HC_REG_LEADING_EDGE_0 + port*8, 0);
8058 REG_WR(bp, HC_REG_TRAILING_EDGE_0 + port*8, 0);
8060 bnx2x_init_block(bp, BLOCK_HC, init_phase);
8063 int num_segs, sb_idx, prod_offset;
8065 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_12 + func*4, 0);
8067 if (!CHIP_IS_E1x(bp)) {
8068 REG_WR(bp, IGU_REG_LEADING_EDGE_LATCH, 0);
8069 REG_WR(bp, IGU_REG_TRAILING_EDGE_LATCH, 0);
8072 bnx2x_init_block(bp, BLOCK_IGU, init_phase);
8074 if (!CHIP_IS_E1x(bp)) {
8078 * E2 mode: address 0-135 match to the mapping memory;
8079 * 136 - PF0 default prod; 137 - PF1 default prod;
8080 * 138 - PF2 default prod; 139 - PF3 default prod;
8081 * 140 - PF0 attn prod; 141 - PF1 attn prod;
8082 * 142 - PF2 attn prod; 143 - PF3 attn prod;
8085 * E1.5 mode - In backward compatible mode;
8086 * for non default SB; each even line in the memory
8087 * holds the U producer and each odd line hold
8088 * the C producer. The first 128 producers are for
8089 * NDSB (PF0 - 0-31; PF1 - 32-63 and so on). The last 20
8090 * producers are for the DSB for each PF.
8091 * Each PF has five segments: (the order inside each
8092 * segment is PF0; PF1; PF2; PF3) - 128-131 U prods;
8093 * 132-135 C prods; 136-139 X prods; 140-143 T prods;
8094 * 144-147 attn prods;
8096 /* non-default-status-blocks */
8097 num_segs = CHIP_INT_MODE_IS_BC(bp) ?
8098 IGU_BC_NDSB_NUM_SEGS : IGU_NORM_NDSB_NUM_SEGS;
8099 for (sb_idx = 0; sb_idx < bp->igu_sb_cnt; sb_idx++) {
8100 prod_offset = (bp->igu_base_sb + sb_idx) *
8103 for (i = 0; i < num_segs; i++) {
8104 addr = IGU_REG_PROD_CONS_MEMORY +
8105 (prod_offset + i) * 4;
8106 REG_WR(bp, addr, 0);
8108 /* send consumer update with value 0 */
8109 bnx2x_ack_sb(bp, bp->igu_base_sb + sb_idx,
8110 USTORM_ID, 0, IGU_INT_NOP, 1);
8111 bnx2x_igu_clear_sb(bp,
8112 bp->igu_base_sb + sb_idx);
8115 /* default-status-blocks */
8116 num_segs = CHIP_INT_MODE_IS_BC(bp) ?
8117 IGU_BC_DSB_NUM_SEGS : IGU_NORM_DSB_NUM_SEGS;
8119 if (CHIP_MODE_IS_4_PORT(bp))
8120 dsb_idx = BP_FUNC(bp);
8122 dsb_idx = BP_VN(bp);
8124 prod_offset = (CHIP_INT_MODE_IS_BC(bp) ?
8125 IGU_BC_BASE_DSB_PROD + dsb_idx :
8126 IGU_NORM_BASE_DSB_PROD + dsb_idx);
8129 * igu prods come in chunks of E1HVN_MAX (4) -
8130 * does not matters what is the current chip mode
8132 for (i = 0; i < (num_segs * E1HVN_MAX);
8134 addr = IGU_REG_PROD_CONS_MEMORY +
8135 (prod_offset + i)*4;
8136 REG_WR(bp, addr, 0);
8138 /* send consumer update with 0 */
8139 if (CHIP_INT_MODE_IS_BC(bp)) {
8140 bnx2x_ack_sb(bp, bp->igu_dsb_id,
8141 USTORM_ID, 0, IGU_INT_NOP, 1);
8142 bnx2x_ack_sb(bp, bp->igu_dsb_id,
8143 CSTORM_ID, 0, IGU_INT_NOP, 1);
8144 bnx2x_ack_sb(bp, bp->igu_dsb_id,
8145 XSTORM_ID, 0, IGU_INT_NOP, 1);
8146 bnx2x_ack_sb(bp, bp->igu_dsb_id,
8147 TSTORM_ID, 0, IGU_INT_NOP, 1);
8148 bnx2x_ack_sb(bp, bp->igu_dsb_id,
8149 ATTENTION_ID, 0, IGU_INT_NOP, 1);
8151 bnx2x_ack_sb(bp, bp->igu_dsb_id,
8152 USTORM_ID, 0, IGU_INT_NOP, 1);
8153 bnx2x_ack_sb(bp, bp->igu_dsb_id,
8154 ATTENTION_ID, 0, IGU_INT_NOP, 1);
8156 bnx2x_igu_clear_sb(bp, bp->igu_dsb_id);
8158 /* !!! These should become driver const once
8159 rf-tool supports split-68 const */
8160 REG_WR(bp, IGU_REG_SB_INT_BEFORE_MASK_LSB, 0);
8161 REG_WR(bp, IGU_REG_SB_INT_BEFORE_MASK_MSB, 0);
8162 REG_WR(bp, IGU_REG_SB_MASK_LSB, 0);
8163 REG_WR(bp, IGU_REG_SB_MASK_MSB, 0);
8164 REG_WR(bp, IGU_REG_PBA_STATUS_LSB, 0);
8165 REG_WR(bp, IGU_REG_PBA_STATUS_MSB, 0);
8169 /* Reset PCIE errors for debug */
8170 REG_WR(bp, 0x2114, 0xffffffff);
8171 REG_WR(bp, 0x2120, 0xffffffff);
8173 if (CHIP_IS_E1x(bp)) {
8174 main_mem_size = HC_REG_MAIN_MEMORY_SIZE / 2; /*dwords*/
8175 main_mem_base = HC_REG_MAIN_MEMORY +
8176 BP_PORT(bp) * (main_mem_size * 4);
8177 main_mem_prty_clr = HC_REG_HC_PRTY_STS_CLR;
8180 val = REG_RD(bp, main_mem_prty_clr);
8183 "Hmmm... Parity errors in HC block during function init (0x%x)!\n",
8186 /* Clear "false" parity errors in MSI-X table */
8187 for (i = main_mem_base;
8188 i < main_mem_base + main_mem_size * 4;
8189 i += main_mem_width) {
8190 bnx2x_read_dmae(bp, i, main_mem_width / 4);
8191 bnx2x_write_dmae(bp, bnx2x_sp_mapping(bp, wb_data),
8192 i, main_mem_width / 4);
8194 /* Clear HC parity attention */
8195 REG_RD(bp, main_mem_prty_clr);
8198 #ifdef BNX2X_STOP_ON_ERROR
8199 /* Enable STORMs SP logging */
8200 REG_WR8(bp, BAR_USTRORM_INTMEM +
8201 USTORM_RECORD_SLOW_PATH_OFFSET(BP_FUNC(bp)), 1);
8202 REG_WR8(bp, BAR_TSTRORM_INTMEM +
8203 TSTORM_RECORD_SLOW_PATH_OFFSET(BP_FUNC(bp)), 1);
8204 REG_WR8(bp, BAR_CSTRORM_INTMEM +
8205 CSTORM_RECORD_SLOW_PATH_OFFSET(BP_FUNC(bp)), 1);
8206 REG_WR8(bp, BAR_XSTRORM_INTMEM +
8207 XSTORM_RECORD_SLOW_PATH_OFFSET(BP_FUNC(bp)), 1);
8210 bnx2x_phy_probe(&bp->link_params);
8215 void bnx2x_free_mem_cnic(struct bnx2x *bp)
8217 bnx2x_ilt_mem_op_cnic(bp, ILT_MEMOP_FREE);
8219 if (!CHIP_IS_E1x(bp))
8220 BNX2X_PCI_FREE(bp->cnic_sb.e2_sb, bp->cnic_sb_mapping,
8221 sizeof(struct host_hc_status_block_e2));
8223 BNX2X_PCI_FREE(bp->cnic_sb.e1x_sb, bp->cnic_sb_mapping,
8224 sizeof(struct host_hc_status_block_e1x));
8226 BNX2X_PCI_FREE(bp->t2, bp->t2_mapping, SRC_T2_SZ);
8229 void bnx2x_free_mem(struct bnx2x *bp)
8233 BNX2X_PCI_FREE(bp->fw_stats, bp->fw_stats_mapping,
8234 bp->fw_stats_data_sz + bp->fw_stats_req_sz);
8239 BNX2X_PCI_FREE(bp->def_status_blk, bp->def_status_blk_mapping,
8240 sizeof(struct host_sp_status_block));
8242 BNX2X_PCI_FREE(bp->slowpath, bp->slowpath_mapping,
8243 sizeof(struct bnx2x_slowpath));
8245 for (i = 0; i < L2_ILT_LINES(bp); i++)
8246 BNX2X_PCI_FREE(bp->context[i].vcxt, bp->context[i].cxt_mapping,
8247 bp->context[i].size);
8248 bnx2x_ilt_mem_op(bp, ILT_MEMOP_FREE);
8250 BNX2X_FREE(bp->ilt->lines);
8252 BNX2X_PCI_FREE(bp->spq, bp->spq_mapping, BCM_PAGE_SIZE);
8254 BNX2X_PCI_FREE(bp->eq_ring, bp->eq_mapping,
8255 BCM_PAGE_SIZE * NUM_EQ_PAGES);
8257 BNX2X_PCI_FREE(bp->t2, bp->t2_mapping, SRC_T2_SZ);
8259 bnx2x_iov_free_mem(bp);
8262 int bnx2x_alloc_mem_cnic(struct bnx2x *bp)
8264 if (!CHIP_IS_E1x(bp)) {
8265 /* size = the status block + ramrod buffers */
8266 bp->cnic_sb.e2_sb = BNX2X_PCI_ALLOC(&bp->cnic_sb_mapping,
8267 sizeof(struct host_hc_status_block_e2));
8268 if (!bp->cnic_sb.e2_sb)
8271 bp->cnic_sb.e1x_sb = BNX2X_PCI_ALLOC(&bp->cnic_sb_mapping,
8272 sizeof(struct host_hc_status_block_e1x));
8273 if (!bp->cnic_sb.e1x_sb)
8277 if (CONFIGURE_NIC_MODE(bp) && !bp->t2) {
8278 /* allocate searcher T2 table, as it wasn't allocated before */
8279 bp->t2 = BNX2X_PCI_ALLOC(&bp->t2_mapping, SRC_T2_SZ);
8284 /* write address to which L5 should insert its values */
8285 bp->cnic_eth_dev.addr_drv_info_to_mcp =
8286 &bp->slowpath->drv_info_to_mcp;
8288 if (bnx2x_ilt_mem_op_cnic(bp, ILT_MEMOP_ALLOC))
8294 bnx2x_free_mem_cnic(bp);
8295 BNX2X_ERR("Can't allocate memory\n");
8299 int bnx2x_alloc_mem(struct bnx2x *bp)
8301 int i, allocated, context_size;
8303 if (!CONFIGURE_NIC_MODE(bp) && !bp->t2) {
8304 /* allocate searcher T2 table */
8305 bp->t2 = BNX2X_PCI_ALLOC(&bp->t2_mapping, SRC_T2_SZ);
8310 bp->def_status_blk = BNX2X_PCI_ALLOC(&bp->def_status_blk_mapping,
8311 sizeof(struct host_sp_status_block));
8312 if (!bp->def_status_blk)
8315 bp->slowpath = BNX2X_PCI_ALLOC(&bp->slowpath_mapping,
8316 sizeof(struct bnx2x_slowpath));
8320 /* Allocate memory for CDU context:
8321 * This memory is allocated separately and not in the generic ILT
8322 * functions because CDU differs in few aspects:
8323 * 1. There are multiple entities allocating memory for context -
8324 * 'regular' driver, CNIC and SRIOV driver. Each separately controls
8325 * its own ILT lines.
8326 * 2. Since CDU page-size is not a single 4KB page (which is the case
8327 * for the other ILT clients), to be efficient we want to support
8328 * allocation of sub-page-size in the last entry.
8329 * 3. Context pointers are used by the driver to pass to FW / update
8330 * the context (for the other ILT clients the pointers are used just to
8331 * free the memory during unload).
8333 context_size = sizeof(union cdu_context) * BNX2X_L2_CID_COUNT(bp);
8335 for (i = 0, allocated = 0; allocated < context_size; i++) {
8336 bp->context[i].size = min(CDU_ILT_PAGE_SZ,
8337 (context_size - allocated));
8338 bp->context[i].vcxt = BNX2X_PCI_ALLOC(&bp->context[i].cxt_mapping,
8339 bp->context[i].size);
8340 if (!bp->context[i].vcxt)
8342 allocated += bp->context[i].size;
8344 bp->ilt->lines = kcalloc(ILT_MAX_LINES, sizeof(struct ilt_line),
8346 if (!bp->ilt->lines)
8349 if (bnx2x_ilt_mem_op(bp, ILT_MEMOP_ALLOC))
8352 if (bnx2x_iov_alloc_mem(bp))
8355 /* Slow path ring */
8356 bp->spq = BNX2X_PCI_ALLOC(&bp->spq_mapping, BCM_PAGE_SIZE);
8361 bp->eq_ring = BNX2X_PCI_ALLOC(&bp->eq_mapping,
8362 BCM_PAGE_SIZE * NUM_EQ_PAGES);
8370 BNX2X_ERR("Can't allocate memory\n");
8375 * Init service functions
8378 int bnx2x_set_mac_one(struct bnx2x *bp, u8 *mac,
8379 struct bnx2x_vlan_mac_obj *obj, bool set,
8380 int mac_type, unsigned long *ramrod_flags)
8383 struct bnx2x_vlan_mac_ramrod_params ramrod_param;
8385 memset(&ramrod_param, 0, sizeof(ramrod_param));
8387 /* Fill general parameters */
8388 ramrod_param.vlan_mac_obj = obj;
8389 ramrod_param.ramrod_flags = *ramrod_flags;
8391 /* Fill a user request section if needed */
8392 if (!test_bit(RAMROD_CONT, ramrod_flags)) {
8393 memcpy(ramrod_param.user_req.u.mac.mac, mac, ETH_ALEN);
8395 __set_bit(mac_type, &ramrod_param.user_req.vlan_mac_flags);
8397 /* Set the command: ADD or DEL */
8399 ramrod_param.user_req.cmd = BNX2X_VLAN_MAC_ADD;
8401 ramrod_param.user_req.cmd = BNX2X_VLAN_MAC_DEL;
8404 rc = bnx2x_config_vlan_mac(bp, &ramrod_param);
8406 if (rc == -EEXIST) {
8407 DP(BNX2X_MSG_SP, "Failed to schedule ADD operations: %d\n", rc);
8408 /* do not treat adding same MAC as error */
8411 BNX2X_ERR("%s MAC failed\n", (set ? "Set" : "Del"));
8416 int bnx2x_del_all_macs(struct bnx2x *bp,
8417 struct bnx2x_vlan_mac_obj *mac_obj,
8418 int mac_type, bool wait_for_comp)
8421 unsigned long ramrod_flags = 0, vlan_mac_flags = 0;
8423 /* Wait for completion of requested */
8425 __set_bit(RAMROD_COMP_WAIT, &ramrod_flags);
8427 /* Set the mac type of addresses we want to clear */
8428 __set_bit(mac_type, &vlan_mac_flags);
8430 rc = mac_obj->delete_all(bp, mac_obj, &vlan_mac_flags, &ramrod_flags);
8432 BNX2X_ERR("Failed to delete MACs: %d\n", rc);
8437 int bnx2x_set_eth_mac(struct bnx2x *bp, bool set)
8440 unsigned long ramrod_flags = 0;
8442 DP(NETIF_MSG_IFUP, "Adding Eth MAC\n");
8443 __set_bit(RAMROD_COMP_WAIT, &ramrod_flags);
8444 return bnx2x_set_mac_one(bp, bp->dev->dev_addr,
8445 &bp->sp_objs->mac_obj, set,
8446 BNX2X_ETH_MAC, &ramrod_flags);
8448 return bnx2x_vfpf_config_mac(bp, bp->dev->dev_addr,
8449 bp->fp->index, set);
8453 int bnx2x_setup_leading(struct bnx2x *bp)
8456 return bnx2x_setup_queue(bp, &bp->fp[0], true);
8458 return bnx2x_vfpf_setup_q(bp, &bp->fp[0], true);
8462 * bnx2x_set_int_mode - configure interrupt mode
8464 * @bp: driver handle
8466 * In case of MSI-X it will also try to enable MSI-X.
8468 int bnx2x_set_int_mode(struct bnx2x *bp)
8472 if (IS_VF(bp) && int_mode != BNX2X_INT_MODE_MSIX) {
8473 BNX2X_ERR("VF not loaded since interrupt mode not msix\n");
8478 case BNX2X_INT_MODE_MSIX:
8479 /* attempt to enable msix */
8480 rc = bnx2x_enable_msix(bp);
8486 /* vfs use only msix */
8487 if (rc && IS_VF(bp))
8490 /* failed to enable multiple MSI-X */
8491 BNX2X_DEV_INFO("Failed to enable multiple MSI-X (%d), set number of queues to %d\n",
8493 1 + bp->num_cnic_queues);
8495 /* falling through... */
8496 case BNX2X_INT_MODE_MSI:
8497 bnx2x_enable_msi(bp);
8499 /* falling through... */
8500 case BNX2X_INT_MODE_INTX:
8501 bp->num_ethernet_queues = 1;
8502 bp->num_queues = bp->num_ethernet_queues + bp->num_cnic_queues;
8503 BNX2X_DEV_INFO("set number of queues to 1\n");
8506 BNX2X_DEV_INFO("unknown value in int_mode module parameter\n");
8512 /* must be called prior to any HW initializations */
8513 static inline u16 bnx2x_cid_ilt_lines(struct bnx2x *bp)
8516 return (BNX2X_FIRST_VF_CID + BNX2X_VF_CIDS)/ILT_PAGE_CIDS;
8517 return L2_ILT_LINES(bp);
8520 void bnx2x_ilt_set_info(struct bnx2x *bp)
8522 struct ilt_client_info *ilt_client;
8523 struct bnx2x_ilt *ilt = BP_ILT(bp);
8526 ilt->start_line = FUNC_ILT_BASE(BP_FUNC(bp));
8527 DP(BNX2X_MSG_SP, "ilt starts at line %d\n", ilt->start_line);
8530 ilt_client = &ilt->clients[ILT_CLIENT_CDU];
8531 ilt_client->client_num = ILT_CLIENT_CDU;
8532 ilt_client->page_size = CDU_ILT_PAGE_SZ;
8533 ilt_client->flags = ILT_CLIENT_SKIP_MEM;
8534 ilt_client->start = line;
8535 line += bnx2x_cid_ilt_lines(bp);
8537 if (CNIC_SUPPORT(bp))
8538 line += CNIC_ILT_LINES;
8539 ilt_client->end = line - 1;
8541 DP(NETIF_MSG_IFUP, "ilt client[CDU]: start %d, end %d, psz 0x%x, flags 0x%x, hw psz %d\n",
8544 ilt_client->page_size,
8546 ilog2(ilt_client->page_size >> 12));
8549 if (QM_INIT(bp->qm_cid_count)) {
8550 ilt_client = &ilt->clients[ILT_CLIENT_QM];
8551 ilt_client->client_num = ILT_CLIENT_QM;
8552 ilt_client->page_size = QM_ILT_PAGE_SZ;
8553 ilt_client->flags = 0;
8554 ilt_client->start = line;
8556 /* 4 bytes for each cid */
8557 line += DIV_ROUND_UP(bp->qm_cid_count * QM_QUEUES_PER_FUNC * 4,
8560 ilt_client->end = line - 1;
8563 "ilt client[QM]: start %d, end %d, psz 0x%x, flags 0x%x, hw psz %d\n",
8566 ilt_client->page_size,
8568 ilog2(ilt_client->page_size >> 12));
8571 if (CNIC_SUPPORT(bp)) {
8573 ilt_client = &ilt->clients[ILT_CLIENT_SRC];
8574 ilt_client->client_num = ILT_CLIENT_SRC;
8575 ilt_client->page_size = SRC_ILT_PAGE_SZ;
8576 ilt_client->flags = 0;
8577 ilt_client->start = line;
8578 line += SRC_ILT_LINES;
8579 ilt_client->end = line - 1;
8582 "ilt client[SRC]: start %d, end %d, psz 0x%x, flags 0x%x, hw psz %d\n",
8585 ilt_client->page_size,
8587 ilog2(ilt_client->page_size >> 12));
8590 ilt_client = &ilt->clients[ILT_CLIENT_TM];
8591 ilt_client->client_num = ILT_CLIENT_TM;
8592 ilt_client->page_size = TM_ILT_PAGE_SZ;
8593 ilt_client->flags = 0;
8594 ilt_client->start = line;
8595 line += TM_ILT_LINES;
8596 ilt_client->end = line - 1;
8599 "ilt client[TM]: start %d, end %d, psz 0x%x, flags 0x%x, hw psz %d\n",
8602 ilt_client->page_size,
8604 ilog2(ilt_client->page_size >> 12));
8607 BUG_ON(line > ILT_MAX_LINES);
8611 * bnx2x_pf_q_prep_init - prepare INIT transition parameters
8613 * @bp: driver handle
8614 * @fp: pointer to fastpath
8615 * @init_params: pointer to parameters structure
8617 * parameters configured:
8618 * - HC configuration
8619 * - Queue's CDU context
8621 static void bnx2x_pf_q_prep_init(struct bnx2x *bp,
8622 struct bnx2x_fastpath *fp, struct bnx2x_queue_init_params *init_params)
8625 int cxt_index, cxt_offset;
8627 /* FCoE Queue uses Default SB, thus has no HC capabilities */
8628 if (!IS_FCOE_FP(fp)) {
8629 __set_bit(BNX2X_Q_FLG_HC, &init_params->rx.flags);
8630 __set_bit(BNX2X_Q_FLG_HC, &init_params->tx.flags);
8632 /* If HC is supported, enable host coalescing in the transition
8635 __set_bit(BNX2X_Q_FLG_HC_EN, &init_params->rx.flags);
8636 __set_bit(BNX2X_Q_FLG_HC_EN, &init_params->tx.flags);
8639 init_params->rx.hc_rate = bp->rx_ticks ?
8640 (1000000 / bp->rx_ticks) : 0;
8641 init_params->tx.hc_rate = bp->tx_ticks ?
8642 (1000000 / bp->tx_ticks) : 0;
8645 init_params->rx.fw_sb_id = init_params->tx.fw_sb_id =
8649 * CQ index among the SB indices: FCoE clients uses the default
8650 * SB, therefore it's different.
8652 init_params->rx.sb_cq_index = HC_INDEX_ETH_RX_CQ_CONS;
8653 init_params->tx.sb_cq_index = HC_INDEX_ETH_FIRST_TX_CQ_CONS;
8656 /* set maximum number of COSs supported by this queue */
8657 init_params->max_cos = fp->max_cos;
8659 DP(NETIF_MSG_IFUP, "fp: %d setting queue params max cos to: %d\n",
8660 fp->index, init_params->max_cos);
8662 /* set the context pointers queue object */
8663 for (cos = FIRST_TX_COS_INDEX; cos < init_params->max_cos; cos++) {
8664 cxt_index = fp->txdata_ptr[cos]->cid / ILT_PAGE_CIDS;
8665 cxt_offset = fp->txdata_ptr[cos]->cid - (cxt_index *
8667 init_params->cxts[cos] =
8668 &bp->context[cxt_index].vcxt[cxt_offset].eth;
8672 static int bnx2x_setup_tx_only(struct bnx2x *bp, struct bnx2x_fastpath *fp,
8673 struct bnx2x_queue_state_params *q_params,
8674 struct bnx2x_queue_setup_tx_only_params *tx_only_params,
8675 int tx_index, bool leading)
8677 memset(tx_only_params, 0, sizeof(*tx_only_params));
8679 /* Set the command */
8680 q_params->cmd = BNX2X_Q_CMD_SETUP_TX_ONLY;
8682 /* Set tx-only QUEUE flags: don't zero statistics */
8683 tx_only_params->flags = bnx2x_get_common_flags(bp, fp, false);
8685 /* choose the index of the cid to send the slow path on */
8686 tx_only_params->cid_index = tx_index;
8688 /* Set general TX_ONLY_SETUP parameters */
8689 bnx2x_pf_q_prep_general(bp, fp, &tx_only_params->gen_params, tx_index);
8691 /* Set Tx TX_ONLY_SETUP parameters */
8692 bnx2x_pf_tx_q_prep(bp, fp, &tx_only_params->txq_params, tx_index);
8695 "preparing to send tx-only ramrod for connection: cos %d, primary cid %d, cid %d, client id %d, sp-client id %d, flags %lx\n",
8696 tx_index, q_params->q_obj->cids[FIRST_TX_COS_INDEX],
8697 q_params->q_obj->cids[tx_index], q_params->q_obj->cl_id,
8698 tx_only_params->gen_params.spcl_id, tx_only_params->flags);
8700 /* send the ramrod */
8701 return bnx2x_queue_state_change(bp, q_params);
8705 * bnx2x_setup_queue - setup queue
8707 * @bp: driver handle
8708 * @fp: pointer to fastpath
8709 * @leading: is leading
8711 * This function performs 2 steps in a Queue state machine
8712 * actually: 1) RESET->INIT 2) INIT->SETUP
8715 int bnx2x_setup_queue(struct bnx2x *bp, struct bnx2x_fastpath *fp,
8718 struct bnx2x_queue_state_params q_params = {NULL};
8719 struct bnx2x_queue_setup_params *setup_params =
8720 &q_params.params.setup;
8721 struct bnx2x_queue_setup_tx_only_params *tx_only_params =
8722 &q_params.params.tx_only;
8726 DP(NETIF_MSG_IFUP, "setting up queue %d\n", fp->index);
8728 /* reset IGU state skip FCoE L2 queue */
8729 if (!IS_FCOE_FP(fp))
8730 bnx2x_ack_sb(bp, fp->igu_sb_id, USTORM_ID, 0,
8733 q_params.q_obj = &bnx2x_sp_obj(bp, fp).q_obj;
8734 /* We want to wait for completion in this context */
8735 __set_bit(RAMROD_COMP_WAIT, &q_params.ramrod_flags);
8737 /* Prepare the INIT parameters */
8738 bnx2x_pf_q_prep_init(bp, fp, &q_params.params.init);
8740 /* Set the command */
8741 q_params.cmd = BNX2X_Q_CMD_INIT;
8743 /* Change the state to INIT */
8744 rc = bnx2x_queue_state_change(bp, &q_params);
8746 BNX2X_ERR("Queue(%d) INIT failed\n", fp->index);
8750 DP(NETIF_MSG_IFUP, "init complete\n");
8752 /* Now move the Queue to the SETUP state... */
8753 memset(setup_params, 0, sizeof(*setup_params));
8755 /* Set QUEUE flags */
8756 setup_params->flags = bnx2x_get_q_flags(bp, fp, leading);
8758 /* Set general SETUP parameters */
8759 bnx2x_pf_q_prep_general(bp, fp, &setup_params->gen_params,
8760 FIRST_TX_COS_INDEX);
8762 bnx2x_pf_rx_q_prep(bp, fp, &setup_params->pause_params,
8763 &setup_params->rxq_params);
8765 bnx2x_pf_tx_q_prep(bp, fp, &setup_params->txq_params,
8766 FIRST_TX_COS_INDEX);
8768 /* Set the command */
8769 q_params.cmd = BNX2X_Q_CMD_SETUP;
8772 bp->fcoe_init = true;
8774 /* Change the state to SETUP */
8775 rc = bnx2x_queue_state_change(bp, &q_params);
8777 BNX2X_ERR("Queue(%d) SETUP failed\n", fp->index);
8781 /* loop through the relevant tx-only indices */
8782 for (tx_index = FIRST_TX_ONLY_COS_INDEX;
8783 tx_index < fp->max_cos;
8786 /* prepare and send tx-only ramrod*/
8787 rc = bnx2x_setup_tx_only(bp, fp, &q_params,
8788 tx_only_params, tx_index, leading);
8790 BNX2X_ERR("Queue(%d.%d) TX_ONLY_SETUP failed\n",
8791 fp->index, tx_index);
8799 static int bnx2x_stop_queue(struct bnx2x *bp, int index)
8801 struct bnx2x_fastpath *fp = &bp->fp[index];
8802 struct bnx2x_fp_txdata *txdata;
8803 struct bnx2x_queue_state_params q_params = {NULL};
8806 DP(NETIF_MSG_IFDOWN, "stopping queue %d cid %d\n", index, fp->cid);
8808 q_params.q_obj = &bnx2x_sp_obj(bp, fp).q_obj;
8809 /* We want to wait for completion in this context */
8810 __set_bit(RAMROD_COMP_WAIT, &q_params.ramrod_flags);
8812 /* close tx-only connections */
8813 for (tx_index = FIRST_TX_ONLY_COS_INDEX;
8814 tx_index < fp->max_cos;
8817 /* ascertain this is a normal queue*/
8818 txdata = fp->txdata_ptr[tx_index];
8820 DP(NETIF_MSG_IFDOWN, "stopping tx-only queue %d\n",
8823 /* send halt terminate on tx-only connection */
8824 q_params.cmd = BNX2X_Q_CMD_TERMINATE;
8825 memset(&q_params.params.terminate, 0,
8826 sizeof(q_params.params.terminate));
8827 q_params.params.terminate.cid_index = tx_index;
8829 rc = bnx2x_queue_state_change(bp, &q_params);
8833 /* send halt terminate on tx-only connection */
8834 q_params.cmd = BNX2X_Q_CMD_CFC_DEL;
8835 memset(&q_params.params.cfc_del, 0,
8836 sizeof(q_params.params.cfc_del));
8837 q_params.params.cfc_del.cid_index = tx_index;
8838 rc = bnx2x_queue_state_change(bp, &q_params);
8842 /* Stop the primary connection: */
8843 /* ...halt the connection */
8844 q_params.cmd = BNX2X_Q_CMD_HALT;
8845 rc = bnx2x_queue_state_change(bp, &q_params);
8849 /* ...terminate the connection */
8850 q_params.cmd = BNX2X_Q_CMD_TERMINATE;
8851 memset(&q_params.params.terminate, 0,
8852 sizeof(q_params.params.terminate));
8853 q_params.params.terminate.cid_index = FIRST_TX_COS_INDEX;
8854 rc = bnx2x_queue_state_change(bp, &q_params);
8857 /* ...delete cfc entry */
8858 q_params.cmd = BNX2X_Q_CMD_CFC_DEL;
8859 memset(&q_params.params.cfc_del, 0,
8860 sizeof(q_params.params.cfc_del));
8861 q_params.params.cfc_del.cid_index = FIRST_TX_COS_INDEX;
8862 return bnx2x_queue_state_change(bp, &q_params);
8865 static void bnx2x_reset_func(struct bnx2x *bp)
8867 int port = BP_PORT(bp);
8868 int func = BP_FUNC(bp);
8871 /* Disable the function in the FW */
8872 REG_WR8(bp, BAR_XSTRORM_INTMEM + XSTORM_FUNC_EN_OFFSET(func), 0);
8873 REG_WR8(bp, BAR_CSTRORM_INTMEM + CSTORM_FUNC_EN_OFFSET(func), 0);
8874 REG_WR8(bp, BAR_TSTRORM_INTMEM + TSTORM_FUNC_EN_OFFSET(func), 0);
8875 REG_WR8(bp, BAR_USTRORM_INTMEM + USTORM_FUNC_EN_OFFSET(func), 0);
8878 for_each_eth_queue(bp, i) {
8879 struct bnx2x_fastpath *fp = &bp->fp[i];
8880 REG_WR8(bp, BAR_CSTRORM_INTMEM +
8881 CSTORM_STATUS_BLOCK_DATA_STATE_OFFSET(fp->fw_sb_id),
8885 if (CNIC_LOADED(bp))
8887 REG_WR8(bp, BAR_CSTRORM_INTMEM +
8888 CSTORM_STATUS_BLOCK_DATA_STATE_OFFSET
8889 (bnx2x_cnic_fw_sb_id(bp)), SB_DISABLED);
8892 REG_WR8(bp, BAR_CSTRORM_INTMEM +
8893 CSTORM_SP_STATUS_BLOCK_DATA_STATE_OFFSET(func),
8896 for (i = 0; i < XSTORM_SPQ_DATA_SIZE / 4; i++)
8897 REG_WR(bp, BAR_XSTRORM_INTMEM + XSTORM_SPQ_DATA_OFFSET(func),
8901 if (bp->common.int_block == INT_BLOCK_HC) {
8902 REG_WR(bp, HC_REG_LEADING_EDGE_0 + port*8, 0);
8903 REG_WR(bp, HC_REG_TRAILING_EDGE_0 + port*8, 0);
8905 REG_WR(bp, IGU_REG_LEADING_EDGE_LATCH, 0);
8906 REG_WR(bp, IGU_REG_TRAILING_EDGE_LATCH, 0);
8909 if (CNIC_LOADED(bp)) {
8910 /* Disable Timer scan */
8911 REG_WR(bp, TM_REG_EN_LINEAR0_TIMER + port*4, 0);
8913 * Wait for at least 10ms and up to 2 second for the timers
8916 for (i = 0; i < 200; i++) {
8917 usleep_range(10000, 20000);
8918 if (!REG_RD(bp, TM_REG_LIN0_SCAN_ON + port*4))
8923 bnx2x_clear_func_ilt(bp, func);
8925 /* Timers workaround bug for E2: if this is vnic-3,
8926 * we need to set the entire ilt range for this timers.
8928 if (!CHIP_IS_E1x(bp) && BP_VN(bp) == 3) {
8929 struct ilt_client_info ilt_cli;
8930 /* use dummy TM client */
8931 memset(&ilt_cli, 0, sizeof(struct ilt_client_info));
8933 ilt_cli.end = ILT_NUM_PAGE_ENTRIES - 1;
8934 ilt_cli.client_num = ILT_CLIENT_TM;
8936 bnx2x_ilt_boundry_init_op(bp, &ilt_cli, 0, INITOP_CLEAR);
8939 /* this assumes that reset_port() called before reset_func()*/
8940 if (!CHIP_IS_E1x(bp))
8941 bnx2x_pf_disable(bp);
8946 static void bnx2x_reset_port(struct bnx2x *bp)
8948 int port = BP_PORT(bp);
8951 /* Reset physical Link */
8952 bnx2x__link_reset(bp);
8954 REG_WR(bp, NIG_REG_MASK_INTERRUPT_PORT0 + port*4, 0);
8956 /* Do not rcv packets to BRB */
8957 REG_WR(bp, NIG_REG_LLH0_BRB1_DRV_MASK + port*4, 0x0);
8958 /* Do not direct rcv packets that are not for MCP to the BRB */
8959 REG_WR(bp, (port ? NIG_REG_LLH1_BRB1_NOT_MCP :
8960 NIG_REG_LLH0_BRB1_NOT_MCP), 0x0);
8963 REG_WR(bp, MISC_REG_AEU_MASK_ATTN_FUNC_0 + port*4, 0);
8966 /* Check for BRB port occupancy */
8967 val = REG_RD(bp, BRB1_REG_PORT_NUM_OCC_BLOCKS_0 + port*4);
8969 DP(NETIF_MSG_IFDOWN,
8970 "BRB1 is not empty %d blocks are occupied\n", val);
8972 /* TODO: Close Doorbell port? */
8975 static int bnx2x_reset_hw(struct bnx2x *bp, u32 load_code)
8977 struct bnx2x_func_state_params func_params = {NULL};
8979 /* Prepare parameters for function state transitions */
8980 __set_bit(RAMROD_COMP_WAIT, &func_params.ramrod_flags);
8982 func_params.f_obj = &bp->func_obj;
8983 func_params.cmd = BNX2X_F_CMD_HW_RESET;
8985 func_params.params.hw_init.load_phase = load_code;
8987 return bnx2x_func_state_change(bp, &func_params);
8990 static int bnx2x_func_stop(struct bnx2x *bp)
8992 struct bnx2x_func_state_params func_params = {NULL};
8995 /* Prepare parameters for function state transitions */
8996 __set_bit(RAMROD_COMP_WAIT, &func_params.ramrod_flags);
8997 func_params.f_obj = &bp->func_obj;
8998 func_params.cmd = BNX2X_F_CMD_STOP;
9001 * Try to stop the function the 'good way'. If fails (in case
9002 * of a parity error during bnx2x_chip_cleanup()) and we are
9003 * not in a debug mode, perform a state transaction in order to
9004 * enable further HW_RESET transaction.
9006 rc = bnx2x_func_state_change(bp, &func_params);
9008 #ifdef BNX2X_STOP_ON_ERROR
9011 BNX2X_ERR("FUNC_STOP ramrod failed. Running a dry transaction\n");
9012 __set_bit(RAMROD_DRV_CLR_ONLY, &func_params.ramrod_flags);
9013 return bnx2x_func_state_change(bp, &func_params);
9021 * bnx2x_send_unload_req - request unload mode from the MCP.
9023 * @bp: driver handle
9024 * @unload_mode: requested function's unload mode
9026 * Return unload mode returned by the MCP: COMMON, PORT or FUNC.
9028 u32 bnx2x_send_unload_req(struct bnx2x *bp, int unload_mode)
9031 int port = BP_PORT(bp);
9033 /* Select the UNLOAD request mode */
9034 if (unload_mode == UNLOAD_NORMAL)
9035 reset_code = DRV_MSG_CODE_UNLOAD_REQ_WOL_DIS;
9037 else if (bp->flags & NO_WOL_FLAG)
9038 reset_code = DRV_MSG_CODE_UNLOAD_REQ_WOL_MCP;
9041 u32 emac_base = port ? GRCBASE_EMAC1 : GRCBASE_EMAC0;
9042 u8 *mac_addr = bp->dev->dev_addr;
9043 struct pci_dev *pdev = bp->pdev;
9047 /* The mac address is written to entries 1-4 to
9048 * preserve entry 0 which is used by the PMF
9050 u8 entry = (BP_VN(bp) + 1)*8;
9052 val = (mac_addr[0] << 8) | mac_addr[1];
9053 EMAC_WR(bp, EMAC_REG_EMAC_MAC_MATCH + entry, val);
9055 val = (mac_addr[2] << 24) | (mac_addr[3] << 16) |
9056 (mac_addr[4] << 8) | mac_addr[5];
9057 EMAC_WR(bp, EMAC_REG_EMAC_MAC_MATCH + entry + 4, val);
9059 /* Enable the PME and clear the status */
9060 pci_read_config_word(pdev, pdev->pm_cap + PCI_PM_CTRL, &pmc);
9061 pmc |= PCI_PM_CTRL_PME_ENABLE | PCI_PM_CTRL_PME_STATUS;
9062 pci_write_config_word(pdev, pdev->pm_cap + PCI_PM_CTRL, pmc);
9064 reset_code = DRV_MSG_CODE_UNLOAD_REQ_WOL_EN;
9067 reset_code = DRV_MSG_CODE_UNLOAD_REQ_WOL_DIS;
9069 /* Send the request to the MCP */
9071 reset_code = bnx2x_fw_command(bp, reset_code, 0);
9073 int path = BP_PATH(bp);
9075 DP(NETIF_MSG_IFDOWN, "NO MCP - load counts[%d] %d, %d, %d\n",
9076 path, bnx2x_load_count[path][0], bnx2x_load_count[path][1],
9077 bnx2x_load_count[path][2]);
9078 bnx2x_load_count[path][0]--;
9079 bnx2x_load_count[path][1 + port]--;
9080 DP(NETIF_MSG_IFDOWN, "NO MCP - new load counts[%d] %d, %d, %d\n",
9081 path, bnx2x_load_count[path][0], bnx2x_load_count[path][1],
9082 bnx2x_load_count[path][2]);
9083 if (bnx2x_load_count[path][0] == 0)
9084 reset_code = FW_MSG_CODE_DRV_UNLOAD_COMMON;
9085 else if (bnx2x_load_count[path][1 + port] == 0)
9086 reset_code = FW_MSG_CODE_DRV_UNLOAD_PORT;
9088 reset_code = FW_MSG_CODE_DRV_UNLOAD_FUNCTION;
9095 * bnx2x_send_unload_done - send UNLOAD_DONE command to the MCP.
9097 * @bp: driver handle
9098 * @keep_link: true iff link should be kept up
9100 void bnx2x_send_unload_done(struct bnx2x *bp, bool keep_link)
9102 u32 reset_param = keep_link ? DRV_MSG_CODE_UNLOAD_SKIP_LINK_RESET : 0;
9104 /* Report UNLOAD_DONE to MCP */
9106 bnx2x_fw_command(bp, DRV_MSG_CODE_UNLOAD_DONE, reset_param);
9109 static int bnx2x_func_wait_started(struct bnx2x *bp)
9112 int msix = (bp->flags & USING_MSIX_FLAG) ? 1 : 0;
9118 * (assumption: No Attention from MCP at this stage)
9119 * PMF probably in the middle of TX disable/enable transaction
9120 * 1. Sync IRS for default SB
9121 * 2. Sync SP queue - this guarantees us that attention handling started
9122 * 3. Wait, that TX disable/enable transaction completes
9124 * 1+2 guarantee that if DCBx attention was scheduled it already changed
9125 * pending bit of transaction from STARTED-->TX_STOPPED, if we already
9126 * received completion for the transaction the state is TX_STOPPED.
9127 * State will return to STARTED after completion of TX_STOPPED-->STARTED
9131 /* make sure default SB ISR is done */
9133 synchronize_irq(bp->msix_table[0].vector);
9135 synchronize_irq(bp->pdev->irq);
9137 flush_workqueue(bnx2x_wq);
9138 flush_workqueue(bnx2x_iov_wq);
9140 while (bnx2x_func_get_state(bp, &bp->func_obj) !=
9141 BNX2X_F_STATE_STARTED && tout--)
9144 if (bnx2x_func_get_state(bp, &bp->func_obj) !=
9145 BNX2X_F_STATE_STARTED) {
9146 #ifdef BNX2X_STOP_ON_ERROR
9147 BNX2X_ERR("Wrong function state\n");
9151 * Failed to complete the transaction in a "good way"
9152 * Force both transactions with CLR bit
9154 struct bnx2x_func_state_params func_params = {NULL};
9156 DP(NETIF_MSG_IFDOWN,
9157 "Hmmm... Unexpected function state! Forcing STARTED-->TX_STOPPED-->STARTED\n");
9159 func_params.f_obj = &bp->func_obj;
9160 __set_bit(RAMROD_DRV_CLR_ONLY,
9161 &func_params.ramrod_flags);
9163 /* STARTED-->TX_ST0PPED */
9164 func_params.cmd = BNX2X_F_CMD_TX_STOP;
9165 bnx2x_func_state_change(bp, &func_params);
9167 /* TX_ST0PPED-->STARTED */
9168 func_params.cmd = BNX2X_F_CMD_TX_START;
9169 return bnx2x_func_state_change(bp, &func_params);
9176 static void bnx2x_disable_ptp(struct bnx2x *bp)
9178 int port = BP_PORT(bp);
9180 /* Disable sending PTP packets to host */
9181 REG_WR(bp, port ? NIG_REG_P1_LLH_PTP_TO_HOST :
9182 NIG_REG_P0_LLH_PTP_TO_HOST, 0x0);
9184 /* Reset PTP event detection rules */
9185 REG_WR(bp, port ? NIG_REG_P1_LLH_PTP_PARAM_MASK :
9186 NIG_REG_P0_LLH_PTP_PARAM_MASK, 0x7FF);
9187 REG_WR(bp, port ? NIG_REG_P1_LLH_PTP_RULE_MASK :
9188 NIG_REG_P0_LLH_PTP_RULE_MASK, 0x3FFF);
9189 REG_WR(bp, port ? NIG_REG_P1_TLLH_PTP_PARAM_MASK :
9190 NIG_REG_P0_TLLH_PTP_PARAM_MASK, 0x7FF);
9191 REG_WR(bp, port ? NIG_REG_P1_TLLH_PTP_RULE_MASK :
9192 NIG_REG_P0_TLLH_PTP_RULE_MASK, 0x3FFF);
9194 /* Disable the PTP feature */
9195 REG_WR(bp, port ? NIG_REG_P1_PTP_EN :
9196 NIG_REG_P0_PTP_EN, 0x0);
9199 /* Called during unload, to stop PTP-related stuff */
9200 static void bnx2x_stop_ptp(struct bnx2x *bp)
9202 /* Cancel PTP work queue. Should be done after the Tx queues are
9203 * drained to prevent additional scheduling.
9205 cancel_work_sync(&bp->ptp_task);
9207 if (bp->ptp_tx_skb) {
9208 dev_kfree_skb_any(bp->ptp_tx_skb);
9209 bp->ptp_tx_skb = NULL;
9212 /* Disable PTP in HW */
9213 bnx2x_disable_ptp(bp);
9215 DP(BNX2X_MSG_PTP, "PTP stop ended successfully\n");
9218 void bnx2x_chip_cleanup(struct bnx2x *bp, int unload_mode, bool keep_link)
9220 int port = BP_PORT(bp);
9223 struct bnx2x_mcast_ramrod_params rparam = {NULL};
9226 /* Wait until tx fastpath tasks complete */
9227 for_each_tx_queue(bp, i) {
9228 struct bnx2x_fastpath *fp = &bp->fp[i];
9230 for_each_cos_in_tx_queue(fp, cos)
9231 rc = bnx2x_clean_tx_queue(bp, fp->txdata_ptr[cos]);
9232 #ifdef BNX2X_STOP_ON_ERROR
9238 /* Give HW time to discard old tx messages */
9239 usleep_range(1000, 2000);
9241 /* Clean all ETH MACs */
9242 rc = bnx2x_del_all_macs(bp, &bp->sp_objs[0].mac_obj, BNX2X_ETH_MAC,
9245 BNX2X_ERR("Failed to delete all ETH macs: %d\n", rc);
9247 /* Clean up UC list */
9248 rc = bnx2x_del_all_macs(bp, &bp->sp_objs[0].mac_obj, BNX2X_UC_LIST_MAC,
9251 BNX2X_ERR("Failed to schedule DEL commands for UC MACs list: %d\n",
9255 if (!CHIP_IS_E1(bp))
9256 REG_WR(bp, NIG_REG_LLH0_FUNC_EN + port*8, 0);
9258 /* Set "drop all" (stop Rx).
9259 * We need to take a netif_addr_lock() here in order to prevent
9260 * a race between the completion code and this code.
9262 netif_addr_lock_bh(bp->dev);
9263 /* Schedule the rx_mode command */
9264 if (test_bit(BNX2X_FILTER_RX_MODE_PENDING, &bp->sp_state))
9265 set_bit(BNX2X_FILTER_RX_MODE_SCHED, &bp->sp_state);
9267 bnx2x_set_storm_rx_mode(bp);
9269 /* Cleanup multicast configuration */
9270 rparam.mcast_obj = &bp->mcast_obj;
9271 rc = bnx2x_config_mcast(bp, &rparam, BNX2X_MCAST_CMD_DEL);
9273 BNX2X_ERR("Failed to send DEL multicast command: %d\n", rc);
9275 netif_addr_unlock_bh(bp->dev);
9277 bnx2x_iov_chip_cleanup(bp);
9280 * Send the UNLOAD_REQUEST to the MCP. This will return if
9281 * this function should perform FUNC, PORT or COMMON HW
9284 reset_code = bnx2x_send_unload_req(bp, unload_mode);
9287 * (assumption: No Attention from MCP at this stage)
9288 * PMF probably in the middle of TX disable/enable transaction
9290 rc = bnx2x_func_wait_started(bp);
9292 BNX2X_ERR("bnx2x_func_wait_started failed\n");
9293 #ifdef BNX2X_STOP_ON_ERROR
9298 /* Close multi and leading connections
9299 * Completions for ramrods are collected in a synchronous way
9301 for_each_eth_queue(bp, i)
9302 if (bnx2x_stop_queue(bp, i))
9303 #ifdef BNX2X_STOP_ON_ERROR
9309 if (CNIC_LOADED(bp)) {
9310 for_each_cnic_queue(bp, i)
9311 if (bnx2x_stop_queue(bp, i))
9312 #ifdef BNX2X_STOP_ON_ERROR
9319 /* If SP settings didn't get completed so far - something
9320 * very wrong has happen.
9322 if (!bnx2x_wait_sp_comp(bp, ~0x0UL))
9323 BNX2X_ERR("Hmmm... Common slow path ramrods got stuck!\n");
9325 #ifndef BNX2X_STOP_ON_ERROR
9328 rc = bnx2x_func_stop(bp);
9330 BNX2X_ERR("Function stop failed!\n");
9331 #ifdef BNX2X_STOP_ON_ERROR
9336 /* stop_ptp should be after the Tx queues are drained to prevent
9337 * scheduling to the cancelled PTP work queue. It should also be after
9338 * function stop ramrod is sent, since as part of this ramrod FW access
9341 if (bp->flags & PTP_SUPPORTED)
9344 /* Disable HW interrupts, NAPI */
9345 bnx2x_netif_stop(bp, 1);
9346 /* Delete all NAPI objects */
9347 bnx2x_del_all_napi(bp);
9348 if (CNIC_LOADED(bp))
9349 bnx2x_del_all_napi_cnic(bp);
9354 /* Reset the chip */
9355 rc = bnx2x_reset_hw(bp, reset_code);
9357 BNX2X_ERR("HW_RESET failed\n");
9359 /* Report UNLOAD_DONE to MCP */
9360 bnx2x_send_unload_done(bp, keep_link);
9363 void bnx2x_disable_close_the_gate(struct bnx2x *bp)
9367 DP(NETIF_MSG_IFDOWN, "Disabling \"close the gates\"\n");
9369 if (CHIP_IS_E1(bp)) {
9370 int port = BP_PORT(bp);
9371 u32 addr = port ? MISC_REG_AEU_MASK_ATTN_FUNC_1 :
9372 MISC_REG_AEU_MASK_ATTN_FUNC_0;
9374 val = REG_RD(bp, addr);
9376 REG_WR(bp, addr, val);
9378 val = REG_RD(bp, MISC_REG_AEU_GENERAL_MASK);
9379 val &= ~(MISC_AEU_GENERAL_MASK_REG_AEU_PXP_CLOSE_MASK |
9380 MISC_AEU_GENERAL_MASK_REG_AEU_NIG_CLOSE_MASK);
9381 REG_WR(bp, MISC_REG_AEU_GENERAL_MASK, val);
9385 /* Close gates #2, #3 and #4: */
9386 static void bnx2x_set_234_gates(struct bnx2x *bp, bool close)
9390 /* Gates #2 and #4a are closed/opened for "not E1" only */
9391 if (!CHIP_IS_E1(bp)) {
9393 REG_WR(bp, PXP_REG_HST_DISCARD_DOORBELLS, !!close);
9395 REG_WR(bp, PXP_REG_HST_DISCARD_INTERNAL_WRITES, !!close);
9399 if (CHIP_IS_E1x(bp)) {
9400 /* Prevent interrupts from HC on both ports */
9401 val = REG_RD(bp, HC_REG_CONFIG_1);
9402 REG_WR(bp, HC_REG_CONFIG_1,
9403 (!close) ? (val | HC_CONFIG_1_REG_BLOCK_DISABLE_1) :
9404 (val & ~(u32)HC_CONFIG_1_REG_BLOCK_DISABLE_1));
9406 val = REG_RD(bp, HC_REG_CONFIG_0);
9407 REG_WR(bp, HC_REG_CONFIG_0,
9408 (!close) ? (val | HC_CONFIG_0_REG_BLOCK_DISABLE_0) :
9409 (val & ~(u32)HC_CONFIG_0_REG_BLOCK_DISABLE_0));
9411 /* Prevent incoming interrupts in IGU */
9412 val = REG_RD(bp, IGU_REG_BLOCK_CONFIGURATION);
9414 REG_WR(bp, IGU_REG_BLOCK_CONFIGURATION,
9416 (val | IGU_BLOCK_CONFIGURATION_REG_BLOCK_ENABLE) :
9417 (val & ~(u32)IGU_BLOCK_CONFIGURATION_REG_BLOCK_ENABLE));
9420 DP(NETIF_MSG_HW | NETIF_MSG_IFUP, "%s gates #2, #3 and #4\n",
9421 close ? "closing" : "opening");
9425 #define SHARED_MF_CLP_MAGIC 0x80000000 /* `magic' bit */
9427 static void bnx2x_clp_reset_prep(struct bnx2x *bp, u32 *magic_val)
9429 /* Do some magic... */
9430 u32 val = MF_CFG_RD(bp, shared_mf_config.clp_mb);
9431 *magic_val = val & SHARED_MF_CLP_MAGIC;
9432 MF_CFG_WR(bp, shared_mf_config.clp_mb, val | SHARED_MF_CLP_MAGIC);
9436 * bnx2x_clp_reset_done - restore the value of the `magic' bit.
9438 * @bp: driver handle
9439 * @magic_val: old value of the `magic' bit.
9441 static void bnx2x_clp_reset_done(struct bnx2x *bp, u32 magic_val)
9443 /* Restore the `magic' bit value... */
9444 u32 val = MF_CFG_RD(bp, shared_mf_config.clp_mb);
9445 MF_CFG_WR(bp, shared_mf_config.clp_mb,
9446 (val & (~SHARED_MF_CLP_MAGIC)) | magic_val);
9450 * bnx2x_reset_mcp_prep - prepare for MCP reset.
9452 * @bp: driver handle
9453 * @magic_val: old value of 'magic' bit.
9455 * Takes care of CLP configurations.
9457 static void bnx2x_reset_mcp_prep(struct bnx2x *bp, u32 *magic_val)
9460 u32 validity_offset;
9462 DP(NETIF_MSG_HW | NETIF_MSG_IFUP, "Starting\n");
9464 /* Set `magic' bit in order to save MF config */
9465 if (!CHIP_IS_E1(bp))
9466 bnx2x_clp_reset_prep(bp, magic_val);
9468 /* Get shmem offset */
9469 shmem = REG_RD(bp, MISC_REG_SHARED_MEM_ADDR);
9471 offsetof(struct shmem_region, validity_map[BP_PORT(bp)]);
9473 /* Clear validity map flags */
9475 REG_WR(bp, shmem + validity_offset, 0);
9478 #define MCP_TIMEOUT 5000 /* 5 seconds (in ms) */
9479 #define MCP_ONE_TIMEOUT 100 /* 100 ms */
9482 * bnx2x_mcp_wait_one - wait for MCP_ONE_TIMEOUT
9484 * @bp: driver handle
9486 static void bnx2x_mcp_wait_one(struct bnx2x *bp)
9488 /* special handling for emulation and FPGA,
9489 wait 10 times longer */
9490 if (CHIP_REV_IS_SLOW(bp))
9491 msleep(MCP_ONE_TIMEOUT*10);
9493 msleep(MCP_ONE_TIMEOUT);
9497 * initializes bp->common.shmem_base and waits for validity signature to appear
9499 static int bnx2x_init_shmem(struct bnx2x *bp)
9505 bp->common.shmem_base = REG_RD(bp, MISC_REG_SHARED_MEM_ADDR);
9506 if (bp->common.shmem_base) {
9507 val = SHMEM_RD(bp, validity_map[BP_PORT(bp)]);
9508 if (val & SHR_MEM_VALIDITY_MB)
9512 bnx2x_mcp_wait_one(bp);
9514 } while (cnt++ < (MCP_TIMEOUT / MCP_ONE_TIMEOUT));
9516 BNX2X_ERR("BAD MCP validity signature\n");
9521 static int bnx2x_reset_mcp_comp(struct bnx2x *bp, u32 magic_val)
9523 int rc = bnx2x_init_shmem(bp);
9525 /* Restore the `magic' bit value */
9526 if (!CHIP_IS_E1(bp))
9527 bnx2x_clp_reset_done(bp, magic_val);
9532 static void bnx2x_pxp_prep(struct bnx2x *bp)
9534 if (!CHIP_IS_E1(bp)) {
9535 REG_WR(bp, PXP2_REG_RD_START_INIT, 0);
9536 REG_WR(bp, PXP2_REG_RQ_RBC_DONE, 0);
9542 * Reset the whole chip except for:
9544 * - PCI Glue, PSWHST, PXP/PXP2 RF (all controlled by
9547 * - MISC (including AEU)
9551 static void bnx2x_process_kill_chip_reset(struct bnx2x *bp, bool global)
9553 u32 not_reset_mask1, reset_mask1, not_reset_mask2, reset_mask2;
9554 u32 global_bits2, stay_reset2;
9557 * Bits that have to be set in reset_mask2 if we want to reset 'global'
9558 * (per chip) blocks.
9561 MISC_REGISTERS_RESET_REG_2_RST_MCP_N_RESET_CMN_CPU |
9562 MISC_REGISTERS_RESET_REG_2_RST_MCP_N_RESET_CMN_CORE;
9564 /* Don't reset the following blocks.
9565 * Important: per port blocks (such as EMAC, BMAC, UMAC) can't be
9566 * reset, as in 4 port device they might still be owned
9567 * by the MCP (there is only one leader per path).
9570 MISC_REGISTERS_RESET_REG_1_RST_HC |
9571 MISC_REGISTERS_RESET_REG_1_RST_PXPV |
9572 MISC_REGISTERS_RESET_REG_1_RST_PXP;
9575 MISC_REGISTERS_RESET_REG_2_RST_PCI_MDIO |
9576 MISC_REGISTERS_RESET_REG_2_RST_EMAC0_HARD_CORE |
9577 MISC_REGISTERS_RESET_REG_2_RST_EMAC1_HARD_CORE |
9578 MISC_REGISTERS_RESET_REG_2_RST_MISC_CORE |
9579 MISC_REGISTERS_RESET_REG_2_RST_RBCN |
9580 MISC_REGISTERS_RESET_REG_2_RST_GRC |
9581 MISC_REGISTERS_RESET_REG_2_RST_MCP_N_RESET_REG_HARD_CORE |
9582 MISC_REGISTERS_RESET_REG_2_RST_MCP_N_HARD_CORE_RST_B |
9583 MISC_REGISTERS_RESET_REG_2_RST_ATC |
9584 MISC_REGISTERS_RESET_REG_2_PGLC |
9585 MISC_REGISTERS_RESET_REG_2_RST_BMAC0 |
9586 MISC_REGISTERS_RESET_REG_2_RST_BMAC1 |
9587 MISC_REGISTERS_RESET_REG_2_RST_EMAC0 |
9588 MISC_REGISTERS_RESET_REG_2_RST_EMAC1 |
9589 MISC_REGISTERS_RESET_REG_2_UMAC0 |
9590 MISC_REGISTERS_RESET_REG_2_UMAC1;
9593 * Keep the following blocks in reset:
9594 * - all xxMACs are handled by the bnx2x_link code.
9597 MISC_REGISTERS_RESET_REG_2_XMAC |
9598 MISC_REGISTERS_RESET_REG_2_XMAC_SOFT;
9600 /* Full reset masks according to the chip */
9601 reset_mask1 = 0xffffffff;
9604 reset_mask2 = 0xffff;
9605 else if (CHIP_IS_E1H(bp))
9606 reset_mask2 = 0x1ffff;
9607 else if (CHIP_IS_E2(bp))
9608 reset_mask2 = 0xfffff;
9609 else /* CHIP_IS_E3 */
9610 reset_mask2 = 0x3ffffff;
9612 /* Don't reset global blocks unless we need to */
9614 reset_mask2 &= ~global_bits2;
9617 * In case of attention in the QM, we need to reset PXP
9618 * (MISC_REGISTERS_RESET_REG_2_RST_PXP_RQ_RD_WR) before QM
9619 * because otherwise QM reset would release 'close the gates' shortly
9620 * before resetting the PXP, then the PSWRQ would send a write
9621 * request to PGLUE. Then when PXP is reset, PGLUE would try to
9622 * read the payload data from PSWWR, but PSWWR would not
9623 * respond. The write queue in PGLUE would stuck, dmae commands
9624 * would not return. Therefore it's important to reset the second
9625 * reset register (containing the
9626 * MISC_REGISTERS_RESET_REG_2_RST_PXP_RQ_RD_WR bit) before the
9627 * first one (containing the MISC_REGISTERS_RESET_REG_1_RST_QM
9630 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR,
9631 reset_mask2 & (~not_reset_mask2));
9633 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_CLEAR,
9634 reset_mask1 & (~not_reset_mask1));
9639 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_SET,
9640 reset_mask2 & (~stay_reset2));
9645 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_SET, reset_mask1);
9650 * bnx2x_er_poll_igu_vq - poll for pending writes bit.
9651 * It should get cleared in no more than 1s.
9653 * @bp: driver handle
9655 * It should get cleared in no more than 1s. Returns 0 if
9656 * pending writes bit gets cleared.
9658 static int bnx2x_er_poll_igu_vq(struct bnx2x *bp)
9664 pend_bits = REG_RD(bp, IGU_REG_PENDING_BITS_STATUS);
9669 usleep_range(1000, 2000);
9670 } while (cnt-- > 0);
9673 BNX2X_ERR("Still pending IGU requests pend_bits=%x!\n",
9681 static int bnx2x_process_kill(struct bnx2x *bp, bool global)
9685 u32 sr_cnt, blk_cnt, port_is_idle_0, port_is_idle_1, pgl_exp_rom2;
9688 /* Empty the Tetris buffer, wait for 1s */
9690 sr_cnt = REG_RD(bp, PXP2_REG_RD_SR_CNT);
9691 blk_cnt = REG_RD(bp, PXP2_REG_RD_BLK_CNT);
9692 port_is_idle_0 = REG_RD(bp, PXP2_REG_RD_PORT_IS_IDLE_0);
9693 port_is_idle_1 = REG_RD(bp, PXP2_REG_RD_PORT_IS_IDLE_1);
9694 pgl_exp_rom2 = REG_RD(bp, PXP2_REG_PGL_EXP_ROM2);
9696 tags_63_32 = REG_RD(bp, PGLUE_B_REG_TAGS_63_32);
9698 if ((sr_cnt == 0x7e) && (blk_cnt == 0xa0) &&
9699 ((port_is_idle_0 & 0x1) == 0x1) &&
9700 ((port_is_idle_1 & 0x1) == 0x1) &&
9701 (pgl_exp_rom2 == 0xffffffff) &&
9702 (!CHIP_IS_E3(bp) || (tags_63_32 == 0xffffffff)))
9704 usleep_range(1000, 2000);
9705 } while (cnt-- > 0);
9708 BNX2X_ERR("Tetris buffer didn't get empty or there are still outstanding read requests after 1s!\n");
9709 BNX2X_ERR("sr_cnt=0x%08x, blk_cnt=0x%08x, port_is_idle_0=0x%08x, port_is_idle_1=0x%08x, pgl_exp_rom2=0x%08x\n",
9710 sr_cnt, blk_cnt, port_is_idle_0, port_is_idle_1,
9717 /* Close gates #2, #3 and #4 */
9718 bnx2x_set_234_gates(bp, true);
9720 /* Poll for IGU VQs for 57712 and newer chips */
9721 if (!CHIP_IS_E1x(bp) && bnx2x_er_poll_igu_vq(bp))
9724 /* TBD: Indicate that "process kill" is in progress to MCP */
9726 /* Clear "unprepared" bit */
9727 REG_WR(bp, MISC_REG_UNPREPARED, 0);
9730 /* Make sure all is written to the chip before the reset */
9733 /* Wait for 1ms to empty GLUE and PCI-E core queues,
9734 * PSWHST, GRC and PSWRD Tetris buffer.
9736 usleep_range(1000, 2000);
9738 /* Prepare to chip reset: */
9741 bnx2x_reset_mcp_prep(bp, &val);
9747 /* reset the chip */
9748 bnx2x_process_kill_chip_reset(bp, global);
9751 /* clear errors in PGB */
9752 if (!CHIP_IS_E1x(bp))
9753 REG_WR(bp, PGLUE_B_REG_LATCHED_ERRORS_CLR, 0x7f);
9755 /* Recover after reset: */
9757 if (global && bnx2x_reset_mcp_comp(bp, val))
9760 /* TBD: Add resetting the NO_MCP mode DB here */
9762 /* Open the gates #2, #3 and #4 */
9763 bnx2x_set_234_gates(bp, false);
9765 /* TBD: IGU/AEU preparation bring back the AEU/IGU to a
9766 * reset state, re-enable attentions. */
9771 static int bnx2x_leader_reset(struct bnx2x *bp)
9774 bool global = bnx2x_reset_is_global(bp);
9777 /* if not going to reset MCP - load "fake" driver to reset HW while
9778 * driver is owner of the HW
9780 if (!global && !BP_NOMCP(bp)) {
9781 load_code = bnx2x_fw_command(bp, DRV_MSG_CODE_LOAD_REQ,
9782 DRV_MSG_CODE_LOAD_REQ_WITH_LFA);
9784 BNX2X_ERR("MCP response failure, aborting\n");
9786 goto exit_leader_reset;
9788 if ((load_code != FW_MSG_CODE_DRV_LOAD_COMMON_CHIP) &&
9789 (load_code != FW_MSG_CODE_DRV_LOAD_COMMON)) {
9790 BNX2X_ERR("MCP unexpected resp, aborting\n");
9792 goto exit_leader_reset2;
9794 load_code = bnx2x_fw_command(bp, DRV_MSG_CODE_LOAD_DONE, 0);
9796 BNX2X_ERR("MCP response failure, aborting\n");
9798 goto exit_leader_reset2;
9802 /* Try to recover after the failure */
9803 if (bnx2x_process_kill(bp, global)) {
9804 BNX2X_ERR("Something bad had happen on engine %d! Aii!\n",
9807 goto exit_leader_reset2;
9811 * Clear RESET_IN_PROGRES and RESET_GLOBAL bits and update the driver
9814 bnx2x_set_reset_done(bp);
9816 bnx2x_clear_reset_global(bp);
9819 /* unload "fake driver" if it was loaded */
9820 if (!global && !BP_NOMCP(bp)) {
9821 bnx2x_fw_command(bp, DRV_MSG_CODE_UNLOAD_REQ_WOL_MCP, 0);
9822 bnx2x_fw_command(bp, DRV_MSG_CODE_UNLOAD_DONE, 0);
9826 bnx2x_release_leader_lock(bp);
9831 static void bnx2x_recovery_failed(struct bnx2x *bp)
9833 netdev_err(bp->dev, "Recovery has failed. Power cycle is needed.\n");
9835 /* Disconnect this device */
9836 netif_device_detach(bp->dev);
9839 * Block ifup for all function on this engine until "process kill"
9842 bnx2x_set_reset_in_progress(bp);
9844 /* Shut down the power */
9845 bnx2x_set_power_state(bp, PCI_D3hot);
9847 bp->recovery_state = BNX2X_RECOVERY_FAILED;
9853 * Assumption: runs under rtnl lock. This together with the fact
9854 * that it's called only from bnx2x_sp_rtnl() ensure that it
9855 * will never be called when netif_running(bp->dev) is false.
9857 static void bnx2x_parity_recover(struct bnx2x *bp)
9859 bool global = false;
9860 u32 error_recovered, error_unrecovered;
9863 DP(NETIF_MSG_HW, "Handling parity\n");
9865 switch (bp->recovery_state) {
9866 case BNX2X_RECOVERY_INIT:
9867 DP(NETIF_MSG_HW, "State is BNX2X_RECOVERY_INIT\n");
9868 is_parity = bnx2x_chk_parity_attn(bp, &global, false);
9869 WARN_ON(!is_parity);
9871 /* Try to get a LEADER_LOCK HW lock */
9872 if (bnx2x_trylock_leader_lock(bp)) {
9873 bnx2x_set_reset_in_progress(bp);
9875 * Check if there is a global attention and if
9876 * there was a global attention, set the global
9881 bnx2x_set_reset_global(bp);
9886 /* Stop the driver */
9887 /* If interface has been removed - break */
9888 if (bnx2x_nic_unload(bp, UNLOAD_RECOVERY, false))
9891 bp->recovery_state = BNX2X_RECOVERY_WAIT;
9893 /* Ensure "is_leader", MCP command sequence and
9894 * "recovery_state" update values are seen on other
9900 case BNX2X_RECOVERY_WAIT:
9901 DP(NETIF_MSG_HW, "State is BNX2X_RECOVERY_WAIT\n");
9902 if (bp->is_leader) {
9903 int other_engine = BP_PATH(bp) ? 0 : 1;
9904 bool other_load_status =
9905 bnx2x_get_load_status(bp, other_engine);
9907 bnx2x_get_load_status(bp, BP_PATH(bp));
9908 global = bnx2x_reset_is_global(bp);
9911 * In case of a parity in a global block, let
9912 * the first leader that performs a
9913 * leader_reset() reset the global blocks in
9914 * order to clear global attentions. Otherwise
9915 * the gates will remain closed for that
9919 (global && other_load_status)) {
9920 /* Wait until all other functions get
9923 schedule_delayed_work(&bp->sp_rtnl_task,
9927 /* If all other functions got down -
9928 * try to bring the chip back to
9929 * normal. In any case it's an exit
9930 * point for a leader.
9932 if (bnx2x_leader_reset(bp)) {
9933 bnx2x_recovery_failed(bp);
9937 /* If we are here, means that the
9938 * leader has succeeded and doesn't
9939 * want to be a leader any more. Try
9940 * to continue as a none-leader.
9944 } else { /* non-leader */
9945 if (!bnx2x_reset_is_done(bp, BP_PATH(bp))) {
9946 /* Try to get a LEADER_LOCK HW lock as
9947 * long as a former leader may have
9948 * been unloaded by the user or
9949 * released a leadership by another
9952 if (bnx2x_trylock_leader_lock(bp)) {
9953 /* I'm a leader now! Restart a
9960 schedule_delayed_work(&bp->sp_rtnl_task,
9966 * If there was a global attention, wait
9967 * for it to be cleared.
9969 if (bnx2x_reset_is_global(bp)) {
9970 schedule_delayed_work(
9977 bp->eth_stats.recoverable_error;
9979 bp->eth_stats.unrecoverable_error;
9980 bp->recovery_state =
9981 BNX2X_RECOVERY_NIC_LOADING;
9982 if (bnx2x_nic_load(bp, LOAD_NORMAL)) {
9983 error_unrecovered++;
9985 "Recovery failed. Power cycle needed\n");
9986 /* Disconnect this device */
9987 netif_device_detach(bp->dev);
9988 /* Shut down the power */
9989 bnx2x_set_power_state(
9993 bp->recovery_state =
9994 BNX2X_RECOVERY_DONE;
9998 bp->eth_stats.recoverable_error =
10000 bp->eth_stats.unrecoverable_error =
10012 static int bnx2x_close(struct net_device *dev);
10014 /* bnx2x_nic_unload() flushes the bnx2x_wq, thus reset task is
10015 * scheduled on a general queue in order to prevent a dead lock.
10017 static void bnx2x_sp_rtnl_task(struct work_struct *work)
10019 struct bnx2x *bp = container_of(work, struct bnx2x, sp_rtnl_task.work);
10023 if (!netif_running(bp->dev)) {
10028 if (unlikely(bp->recovery_state != BNX2X_RECOVERY_DONE)) {
10029 #ifdef BNX2X_STOP_ON_ERROR
10030 BNX2X_ERR("recovery flow called but STOP_ON_ERROR defined so reset not done to allow debug dump,\n"
10031 "you will need to reboot when done\n");
10032 goto sp_rtnl_not_reset;
10035 * Clear all pending SP commands as we are going to reset the
10038 bp->sp_rtnl_state = 0;
10041 bnx2x_parity_recover(bp);
10047 if (test_and_clear_bit(BNX2X_SP_RTNL_TX_TIMEOUT, &bp->sp_rtnl_state)) {
10048 #ifdef BNX2X_STOP_ON_ERROR
10049 BNX2X_ERR("recovery flow called but STOP_ON_ERROR defined so reset not done to allow debug dump,\n"
10050 "you will need to reboot when done\n");
10051 goto sp_rtnl_not_reset;
10055 * Clear all pending SP commands as we are going to reset the
10058 bp->sp_rtnl_state = 0;
10061 bnx2x_nic_unload(bp, UNLOAD_NORMAL, true);
10062 bnx2x_nic_load(bp, LOAD_NORMAL);
10067 #ifdef BNX2X_STOP_ON_ERROR
10070 if (test_and_clear_bit(BNX2X_SP_RTNL_SETUP_TC, &bp->sp_rtnl_state))
10071 bnx2x_setup_tc(bp->dev, bp->dcbx_port_params.ets.num_of_cos);
10072 if (test_and_clear_bit(BNX2X_SP_RTNL_AFEX_F_UPDATE, &bp->sp_rtnl_state))
10073 bnx2x_after_function_update(bp);
10075 * in case of fan failure we need to reset id if the "stop on error"
10076 * debug flag is set, since we trying to prevent permanent overheating
10079 if (test_and_clear_bit(BNX2X_SP_RTNL_FAN_FAILURE, &bp->sp_rtnl_state)) {
10080 DP(NETIF_MSG_HW, "fan failure detected. Unloading driver\n");
10081 netif_device_detach(bp->dev);
10082 bnx2x_close(bp->dev);
10087 if (test_and_clear_bit(BNX2X_SP_RTNL_VFPF_MCAST, &bp->sp_rtnl_state)) {
10089 "sending set mcast vf pf channel message from rtnl sp-task\n");
10090 bnx2x_vfpf_set_mcast(bp->dev);
10092 if (test_and_clear_bit(BNX2X_SP_RTNL_VFPF_CHANNEL_DOWN,
10093 &bp->sp_rtnl_state)){
10094 if (!test_bit(__LINK_STATE_NOCARRIER, &bp->dev->state)) {
10095 bnx2x_tx_disable(bp);
10096 BNX2X_ERR("PF indicated channel is not servicable anymore. This means this VF device is no longer operational\n");
10100 if (test_and_clear_bit(BNX2X_SP_RTNL_RX_MODE, &bp->sp_rtnl_state)) {
10101 DP(BNX2X_MSG_SP, "Handling Rx Mode setting\n");
10102 bnx2x_set_rx_mode_inner(bp);
10105 if (test_and_clear_bit(BNX2X_SP_RTNL_HYPERVISOR_VLAN,
10106 &bp->sp_rtnl_state))
10107 bnx2x_pf_set_vfs_vlan(bp);
10109 if (test_and_clear_bit(BNX2X_SP_RTNL_TX_STOP, &bp->sp_rtnl_state)) {
10110 bnx2x_dcbx_stop_hw_tx(bp);
10111 bnx2x_dcbx_resume_hw_tx(bp);
10114 if (test_and_clear_bit(BNX2X_SP_RTNL_GET_DRV_VERSION,
10115 &bp->sp_rtnl_state))
10116 bnx2x_update_mng_version(bp);
10118 /* work which needs rtnl lock not-taken (as it takes the lock itself and
10119 * can be called from other contexts as well)
10123 /* enable SR-IOV if applicable */
10124 if (IS_SRIOV(bp) && test_and_clear_bit(BNX2X_SP_RTNL_ENABLE_SRIOV,
10125 &bp->sp_rtnl_state)) {
10126 bnx2x_disable_sriov(bp);
10127 bnx2x_enable_sriov(bp);
10131 static void bnx2x_period_task(struct work_struct *work)
10133 struct bnx2x *bp = container_of(work, struct bnx2x, period_task.work);
10135 if (!netif_running(bp->dev))
10136 goto period_task_exit;
10138 if (CHIP_REV_IS_SLOW(bp)) {
10139 BNX2X_ERR("period task called on emulation, ignoring\n");
10140 goto period_task_exit;
10143 bnx2x_acquire_phy_lock(bp);
10145 * The barrier is needed to ensure the ordering between the writing to
10146 * the bp->port.pmf in the bnx2x_nic_load() or bnx2x_pmf_update() and
10147 * the reading here.
10150 if (bp->port.pmf) {
10151 bnx2x_period_func(&bp->link_params, &bp->link_vars);
10153 /* Re-queue task in 1 sec */
10154 queue_delayed_work(bnx2x_wq, &bp->period_task, 1*HZ);
10157 bnx2x_release_phy_lock(bp);
10163 * Init service functions
10166 static u32 bnx2x_get_pretend_reg(struct bnx2x *bp)
10168 u32 base = PXP2_REG_PGL_PRETEND_FUNC_F0;
10169 u32 stride = PXP2_REG_PGL_PRETEND_FUNC_F1 - base;
10170 return base + (BP_ABS_FUNC(bp)) * stride;
10173 static bool bnx2x_prev_unload_close_umac(struct bnx2x *bp,
10174 u8 port, u32 reset_reg,
10175 struct bnx2x_mac_vals *vals)
10177 u32 mask = MISC_REGISTERS_RESET_REG_2_UMAC0 << port;
10180 if (!(mask & reset_reg))
10183 BNX2X_DEV_INFO("Disable umac Rx %02x\n", port);
10184 base_addr = port ? GRCBASE_UMAC1 : GRCBASE_UMAC0;
10185 vals->umac_addr[port] = base_addr + UMAC_REG_COMMAND_CONFIG;
10186 vals->umac_val[port] = REG_RD(bp, vals->umac_addr[port]);
10187 REG_WR(bp, vals->umac_addr[port], 0);
10192 static void bnx2x_prev_unload_close_mac(struct bnx2x *bp,
10193 struct bnx2x_mac_vals *vals)
10195 u32 val, base_addr, offset, mask, reset_reg;
10196 bool mac_stopped = false;
10197 u8 port = BP_PORT(bp);
10199 /* reset addresses as they also mark which values were changed */
10200 memset(vals, 0, sizeof(*vals));
10202 reset_reg = REG_RD(bp, MISC_REG_RESET_REG_2);
10204 if (!CHIP_IS_E3(bp)) {
10205 val = REG_RD(bp, NIG_REG_BMAC0_REGS_OUT_EN + port * 4);
10206 mask = MISC_REGISTERS_RESET_REG_2_RST_BMAC0 << port;
10207 if ((mask & reset_reg) && val) {
10209 BNX2X_DEV_INFO("Disable bmac Rx\n");
10210 base_addr = BP_PORT(bp) ? NIG_REG_INGRESS_BMAC1_MEM
10211 : NIG_REG_INGRESS_BMAC0_MEM;
10212 offset = CHIP_IS_E2(bp) ? BIGMAC2_REGISTER_BMAC_CONTROL
10213 : BIGMAC_REGISTER_BMAC_CONTROL;
10216 * use rd/wr since we cannot use dmae. This is safe
10217 * since MCP won't access the bus due to the request
10218 * to unload, and no function on the path can be
10219 * loaded at this time.
10221 wb_data[0] = REG_RD(bp, base_addr + offset);
10222 wb_data[1] = REG_RD(bp, base_addr + offset + 0x4);
10223 vals->bmac_addr = base_addr + offset;
10224 vals->bmac_val[0] = wb_data[0];
10225 vals->bmac_val[1] = wb_data[1];
10226 wb_data[0] &= ~BMAC_CONTROL_RX_ENABLE;
10227 REG_WR(bp, vals->bmac_addr, wb_data[0]);
10228 REG_WR(bp, vals->bmac_addr + 0x4, wb_data[1]);
10230 BNX2X_DEV_INFO("Disable emac Rx\n");
10231 vals->emac_addr = NIG_REG_NIG_EMAC0_EN + BP_PORT(bp)*4;
10232 vals->emac_val = REG_RD(bp, vals->emac_addr);
10233 REG_WR(bp, vals->emac_addr, 0);
10234 mac_stopped = true;
10236 if (reset_reg & MISC_REGISTERS_RESET_REG_2_XMAC) {
10237 BNX2X_DEV_INFO("Disable xmac Rx\n");
10238 base_addr = BP_PORT(bp) ? GRCBASE_XMAC1 : GRCBASE_XMAC0;
10239 val = REG_RD(bp, base_addr + XMAC_REG_PFC_CTRL_HI);
10240 REG_WR(bp, base_addr + XMAC_REG_PFC_CTRL_HI,
10242 REG_WR(bp, base_addr + XMAC_REG_PFC_CTRL_HI,
10244 vals->xmac_addr = base_addr + XMAC_REG_CTRL;
10245 vals->xmac_val = REG_RD(bp, vals->xmac_addr);
10246 REG_WR(bp, vals->xmac_addr, 0);
10247 mac_stopped = true;
10250 mac_stopped |= bnx2x_prev_unload_close_umac(bp, 0,
10252 mac_stopped |= bnx2x_prev_unload_close_umac(bp, 1,
10260 #define BNX2X_PREV_UNDI_PROD_ADDR(p) (BAR_TSTRORM_INTMEM + 0x1508 + ((p) << 4))
10261 #define BNX2X_PREV_UNDI_PROD_ADDR_H(f) (BAR_TSTRORM_INTMEM + \
10262 0x1848 + ((f) << 4))
10263 #define BNX2X_PREV_UNDI_RCQ(val) ((val) & 0xffff)
10264 #define BNX2X_PREV_UNDI_BD(val) ((val) >> 16 & 0xffff)
10265 #define BNX2X_PREV_UNDI_PROD(rcq, bd) ((bd) << 16 | (rcq))
10267 #define BCM_5710_UNDI_FW_MF_MAJOR (0x07)
10268 #define BCM_5710_UNDI_FW_MF_MINOR (0x08)
10269 #define BCM_5710_UNDI_FW_MF_VERS (0x05)
10271 static bool bnx2x_prev_is_after_undi(struct bnx2x *bp)
10273 /* UNDI marks its presence in DORQ -
10274 * it initializes CID offset for normal bell to 0x7
10276 if (!(REG_RD(bp, MISC_REG_RESET_REG_1) &
10277 MISC_REGISTERS_RESET_REG_1_RST_DORQ))
10280 if (REG_RD(bp, DORQ_REG_NORM_CID_OFST) == 0x7) {
10281 BNX2X_DEV_INFO("UNDI previously loaded\n");
10288 static void bnx2x_prev_unload_undi_inc(struct bnx2x *bp, u8 inc)
10293 if (BP_FUNC(bp) < 2)
10294 addr = BNX2X_PREV_UNDI_PROD_ADDR(BP_PORT(bp));
10296 addr = BNX2X_PREV_UNDI_PROD_ADDR_H(BP_FUNC(bp) - 2);
10298 tmp_reg = REG_RD(bp, addr);
10299 rcq = BNX2X_PREV_UNDI_RCQ(tmp_reg) + inc;
10300 bd = BNX2X_PREV_UNDI_BD(tmp_reg) + inc;
10302 tmp_reg = BNX2X_PREV_UNDI_PROD(rcq, bd);
10303 REG_WR(bp, addr, tmp_reg);
10305 BNX2X_DEV_INFO("UNDI producer [%d/%d][%08x] rings bd -> 0x%04x, rcq -> 0x%04x\n",
10306 BP_PORT(bp), BP_FUNC(bp), addr, bd, rcq);
10309 static int bnx2x_prev_mcp_done(struct bnx2x *bp)
10311 u32 rc = bnx2x_fw_command(bp, DRV_MSG_CODE_UNLOAD_DONE,
10312 DRV_MSG_CODE_UNLOAD_SKIP_LINK_RESET);
10314 BNX2X_ERR("MCP response failure, aborting\n");
10321 static struct bnx2x_prev_path_list *
10322 bnx2x_prev_path_get_entry(struct bnx2x *bp)
10324 struct bnx2x_prev_path_list *tmp_list;
10326 list_for_each_entry(tmp_list, &bnx2x_prev_list, list)
10327 if (PCI_SLOT(bp->pdev->devfn) == tmp_list->slot &&
10328 bp->pdev->bus->number == tmp_list->bus &&
10329 BP_PATH(bp) == tmp_list->path)
10335 static int bnx2x_prev_path_mark_eeh(struct bnx2x *bp)
10337 struct bnx2x_prev_path_list *tmp_list;
10340 rc = down_interruptible(&bnx2x_prev_sem);
10342 BNX2X_ERR("Received %d when tried to take lock\n", rc);
10346 tmp_list = bnx2x_prev_path_get_entry(bp);
10351 BNX2X_ERR("path %d: Entry does not exist for eeh; Flow occurs before initial insmod is over ?\n",
10355 up(&bnx2x_prev_sem);
10360 static bool bnx2x_prev_is_path_marked(struct bnx2x *bp)
10362 struct bnx2x_prev_path_list *tmp_list;
10365 if (down_trylock(&bnx2x_prev_sem))
10368 tmp_list = bnx2x_prev_path_get_entry(bp);
10370 if (tmp_list->aer) {
10371 DP(NETIF_MSG_HW, "Path %d was marked by AER\n",
10375 BNX2X_DEV_INFO("Path %d was already cleaned from previous drivers\n",
10380 up(&bnx2x_prev_sem);
10385 bool bnx2x_port_after_undi(struct bnx2x *bp)
10387 struct bnx2x_prev_path_list *entry;
10390 down(&bnx2x_prev_sem);
10392 entry = bnx2x_prev_path_get_entry(bp);
10393 val = !!(entry && (entry->undi & (1 << BP_PORT(bp))));
10395 up(&bnx2x_prev_sem);
10400 static int bnx2x_prev_mark_path(struct bnx2x *bp, bool after_undi)
10402 struct bnx2x_prev_path_list *tmp_list;
10405 rc = down_interruptible(&bnx2x_prev_sem);
10407 BNX2X_ERR("Received %d when tried to take lock\n", rc);
10411 /* Check whether the entry for this path already exists */
10412 tmp_list = bnx2x_prev_path_get_entry(bp);
10414 if (!tmp_list->aer) {
10415 BNX2X_ERR("Re-Marking the path.\n");
10417 DP(NETIF_MSG_HW, "Removing AER indication from path %d\n",
10421 up(&bnx2x_prev_sem);
10424 up(&bnx2x_prev_sem);
10426 /* Create an entry for this path and add it */
10427 tmp_list = kmalloc(sizeof(struct bnx2x_prev_path_list), GFP_KERNEL);
10429 BNX2X_ERR("Failed to allocate 'bnx2x_prev_path_list'\n");
10433 tmp_list->bus = bp->pdev->bus->number;
10434 tmp_list->slot = PCI_SLOT(bp->pdev->devfn);
10435 tmp_list->path = BP_PATH(bp);
10437 tmp_list->undi = after_undi ? (1 << BP_PORT(bp)) : 0;
10439 rc = down_interruptible(&bnx2x_prev_sem);
10441 BNX2X_ERR("Received %d when tried to take lock\n", rc);
10444 DP(NETIF_MSG_HW, "Marked path [%d] - finished previous unload\n",
10446 list_add(&tmp_list->list, &bnx2x_prev_list);
10447 up(&bnx2x_prev_sem);
10453 static int bnx2x_do_flr(struct bnx2x *bp)
10455 struct pci_dev *dev = bp->pdev;
10457 if (CHIP_IS_E1x(bp)) {
10458 BNX2X_DEV_INFO("FLR not supported in E1/E1H\n");
10462 /* only bootcode REQ_BC_VER_4_INITIATE_FLR and onwards support flr */
10463 if (bp->common.bc_ver < REQ_BC_VER_4_INITIATE_FLR) {
10464 BNX2X_ERR("FLR not supported by BC_VER: 0x%x\n",
10465 bp->common.bc_ver);
10469 if (!pci_wait_for_pending_transaction(dev))
10470 dev_err(&dev->dev, "transaction is not cleared; proceeding with reset anyway\n");
10472 BNX2X_DEV_INFO("Initiating FLR\n");
10473 bnx2x_fw_command(bp, DRV_MSG_CODE_INITIATE_FLR, 0);
10478 static int bnx2x_prev_unload_uncommon(struct bnx2x *bp)
10482 BNX2X_DEV_INFO("Uncommon unload Flow\n");
10484 /* Test if previous unload process was already finished for this path */
10485 if (bnx2x_prev_is_path_marked(bp))
10486 return bnx2x_prev_mcp_done(bp);
10488 BNX2X_DEV_INFO("Path is unmarked\n");
10490 /* Cannot proceed with FLR if UNDI is loaded, since FW does not match */
10491 if (bnx2x_prev_is_after_undi(bp))
10494 /* If function has FLR capabilities, and existing FW version matches
10495 * the one required, then FLR will be sufficient to clean any residue
10496 * left by previous driver
10498 rc = bnx2x_compare_fw_ver(bp, FW_MSG_CODE_DRV_LOAD_FUNCTION, false);
10501 /* fw version is good */
10502 BNX2X_DEV_INFO("FW version matches our own. Attempting FLR\n");
10503 rc = bnx2x_do_flr(bp);
10507 /* FLR was performed */
10508 BNX2X_DEV_INFO("FLR successful\n");
10512 BNX2X_DEV_INFO("Could not FLR\n");
10515 /* Close the MCP request, return failure*/
10516 rc = bnx2x_prev_mcp_done(bp);
10518 rc = BNX2X_PREV_WAIT_NEEDED;
10523 static int bnx2x_prev_unload_common(struct bnx2x *bp)
10525 u32 reset_reg, tmp_reg = 0, rc;
10526 bool prev_undi = false;
10527 struct bnx2x_mac_vals mac_vals;
10529 /* It is possible a previous function received 'common' answer,
10530 * but hasn't loaded yet, therefore creating a scenario of
10531 * multiple functions receiving 'common' on the same path.
10533 BNX2X_DEV_INFO("Common unload Flow\n");
10535 memset(&mac_vals, 0, sizeof(mac_vals));
10537 if (bnx2x_prev_is_path_marked(bp))
10538 return bnx2x_prev_mcp_done(bp);
10540 reset_reg = REG_RD(bp, MISC_REG_RESET_REG_1);
10542 /* Reset should be performed after BRB is emptied */
10543 if (reset_reg & MISC_REGISTERS_RESET_REG_1_RST_BRB1) {
10544 u32 timer_count = 1000;
10546 /* Close the MAC Rx to prevent BRB from filling up */
10547 bnx2x_prev_unload_close_mac(bp, &mac_vals);
10549 /* close LLH filters for both ports towards the BRB */
10550 bnx2x_set_rx_filter(&bp->link_params, 0);
10551 bp->link_params.port ^= 1;
10552 bnx2x_set_rx_filter(&bp->link_params, 0);
10553 bp->link_params.port ^= 1;
10555 /* Check if the UNDI driver was previously loaded */
10556 if (bnx2x_prev_is_after_undi(bp)) {
10558 /* clear the UNDI indication */
10559 REG_WR(bp, DORQ_REG_NORM_CID_OFST, 0);
10560 /* clear possible idle check errors */
10561 REG_RD(bp, NIG_REG_NIG_INT_STS_CLR_0);
10563 if (!CHIP_IS_E1x(bp))
10564 /* block FW from writing to host */
10565 REG_WR(bp, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, 0);
10567 /* wait until BRB is empty */
10568 tmp_reg = REG_RD(bp, BRB1_REG_NUM_OF_FULL_BLOCKS);
10569 while (timer_count) {
10570 u32 prev_brb = tmp_reg;
10572 tmp_reg = REG_RD(bp, BRB1_REG_NUM_OF_FULL_BLOCKS);
10576 BNX2X_DEV_INFO("BRB still has 0x%08x\n", tmp_reg);
10578 /* reset timer as long as BRB actually gets emptied */
10579 if (prev_brb > tmp_reg)
10580 timer_count = 1000;
10584 /* If UNDI resides in memory, manually increment it */
10586 bnx2x_prev_unload_undi_inc(bp, 1);
10592 BNX2X_ERR("Failed to empty BRB, hope for the best\n");
10595 /* No packets are in the pipeline, path is ready for reset */
10596 bnx2x_reset_common(bp);
10598 if (mac_vals.xmac_addr)
10599 REG_WR(bp, mac_vals.xmac_addr, mac_vals.xmac_val);
10600 if (mac_vals.umac_addr[0])
10601 REG_WR(bp, mac_vals.umac_addr[0], mac_vals.umac_val[0]);
10602 if (mac_vals.umac_addr[1])
10603 REG_WR(bp, mac_vals.umac_addr[1], mac_vals.umac_val[1]);
10604 if (mac_vals.emac_addr)
10605 REG_WR(bp, mac_vals.emac_addr, mac_vals.emac_val);
10606 if (mac_vals.bmac_addr) {
10607 REG_WR(bp, mac_vals.bmac_addr, mac_vals.bmac_val[0]);
10608 REG_WR(bp, mac_vals.bmac_addr + 4, mac_vals.bmac_val[1]);
10611 rc = bnx2x_prev_mark_path(bp, prev_undi);
10613 bnx2x_prev_mcp_done(bp);
10617 return bnx2x_prev_mcp_done(bp);
10620 static int bnx2x_prev_unload(struct bnx2x *bp)
10622 int time_counter = 10;
10623 u32 rc, fw, hw_lock_reg, hw_lock_val;
10624 BNX2X_DEV_INFO("Entering Previous Unload Flow\n");
10626 /* clear hw from errors which may have resulted from an interrupted
10627 * dmae transaction.
10629 bnx2x_clean_pglue_errors(bp);
10631 /* Release previously held locks */
10632 hw_lock_reg = (BP_FUNC(bp) <= 5) ?
10633 (MISC_REG_DRIVER_CONTROL_1 + BP_FUNC(bp) * 8) :
10634 (MISC_REG_DRIVER_CONTROL_7 + (BP_FUNC(bp) - 6) * 8);
10636 hw_lock_val = REG_RD(bp, hw_lock_reg);
10638 if (hw_lock_val & HW_LOCK_RESOURCE_NVRAM) {
10639 BNX2X_DEV_INFO("Release Previously held NVRAM lock\n");
10640 REG_WR(bp, MCP_REG_MCPR_NVM_SW_ARB,
10641 (MCPR_NVM_SW_ARB_ARB_REQ_CLR1 << BP_PORT(bp)));
10644 BNX2X_DEV_INFO("Release Previously held hw lock\n");
10645 REG_WR(bp, hw_lock_reg, 0xffffffff);
10647 BNX2X_DEV_INFO("No need to release hw/nvram locks\n");
10649 if (MCPR_ACCESS_LOCK_LOCK & REG_RD(bp, MCP_REG_MCPR_ACCESS_LOCK)) {
10650 BNX2X_DEV_INFO("Release previously held alr\n");
10651 bnx2x_release_alr(bp);
10656 /* Lock MCP using an unload request */
10657 fw = bnx2x_fw_command(bp, DRV_MSG_CODE_UNLOAD_REQ_WOL_DIS, 0);
10659 BNX2X_ERR("MCP response failure, aborting\n");
10664 rc = down_interruptible(&bnx2x_prev_sem);
10666 BNX2X_ERR("Cannot check for AER; Received %d when tried to take lock\n",
10669 /* If Path is marked by EEH, ignore unload status */
10670 aer = !!(bnx2x_prev_path_get_entry(bp) &&
10671 bnx2x_prev_path_get_entry(bp)->aer);
10672 up(&bnx2x_prev_sem);
10675 if (fw == FW_MSG_CODE_DRV_UNLOAD_COMMON || aer) {
10676 rc = bnx2x_prev_unload_common(bp);
10680 /* non-common reply from MCP might require looping */
10681 rc = bnx2x_prev_unload_uncommon(bp);
10682 if (rc != BNX2X_PREV_WAIT_NEEDED)
10686 } while (--time_counter);
10688 if (!time_counter || rc) {
10689 BNX2X_DEV_INFO("Unloading previous driver did not occur, Possibly due to MF UNDI\n");
10690 rc = -EPROBE_DEFER;
10693 /* Mark function if its port was used to boot from SAN */
10694 if (bnx2x_port_after_undi(bp))
10695 bp->link_params.feature_config_flags |=
10696 FEATURE_CONFIG_BOOT_FROM_SAN;
10698 BNX2X_DEV_INFO("Finished Previous Unload Flow [%d]\n", rc);
10703 static void bnx2x_get_common_hwinfo(struct bnx2x *bp)
10705 u32 val, val2, val3, val4, id, boot_mode;
10708 /* Get the chip revision id and number. */
10709 /* chip num:16-31, rev:12-15, metal:4-11, bond_id:0-3 */
10710 val = REG_RD(bp, MISC_REG_CHIP_NUM);
10711 id = ((val & 0xffff) << 16);
10712 val = REG_RD(bp, MISC_REG_CHIP_REV);
10713 id |= ((val & 0xf) << 12);
10715 /* Metal is read from PCI regs, but we can't access >=0x400 from
10716 * the configuration space (so we need to reg_rd)
10718 val = REG_RD(bp, PCICFG_OFFSET + PCI_ID_VAL3);
10719 id |= (((val >> 24) & 0xf) << 4);
10720 val = REG_RD(bp, MISC_REG_BOND_ID);
10722 bp->common.chip_id = id;
10724 /* force 57811 according to MISC register */
10725 if (REG_RD(bp, MISC_REG_CHIP_TYPE) & MISC_REG_CHIP_TYPE_57811_MASK) {
10726 if (CHIP_IS_57810(bp))
10727 bp->common.chip_id = (CHIP_NUM_57811 << 16) |
10728 (bp->common.chip_id & 0x0000FFFF);
10729 else if (CHIP_IS_57810_MF(bp))
10730 bp->common.chip_id = (CHIP_NUM_57811_MF << 16) |
10731 (bp->common.chip_id & 0x0000FFFF);
10732 bp->common.chip_id |= 0x1;
10735 /* Set doorbell size */
10736 bp->db_size = (1 << BNX2X_DB_SHIFT);
10738 if (!CHIP_IS_E1x(bp)) {
10739 val = REG_RD(bp, MISC_REG_PORT4MODE_EN_OVWR);
10740 if ((val & 1) == 0)
10741 val = REG_RD(bp, MISC_REG_PORT4MODE_EN);
10743 val = (val >> 1) & 1;
10744 BNX2X_DEV_INFO("chip is in %s\n", val ? "4_PORT_MODE" :
10746 bp->common.chip_port_mode = val ? CHIP_4_PORT_MODE :
10749 if (CHIP_MODE_IS_4_PORT(bp))
10750 bp->pfid = (bp->pf_num >> 1); /* 0..3 */
10752 bp->pfid = (bp->pf_num & 0x6); /* 0, 2, 4, 6 */
10754 bp->common.chip_port_mode = CHIP_PORT_MODE_NONE; /* N/A */
10755 bp->pfid = bp->pf_num; /* 0..7 */
10758 BNX2X_DEV_INFO("pf_id: %x", bp->pfid);
10760 bp->link_params.chip_id = bp->common.chip_id;
10761 BNX2X_DEV_INFO("chip ID is 0x%x\n", id);
10763 val = (REG_RD(bp, 0x2874) & 0x55);
10764 if ((bp->common.chip_id & 0x1) ||
10765 (CHIP_IS_E1(bp) && val) || (CHIP_IS_E1H(bp) && (val == 0x55))) {
10766 bp->flags |= ONE_PORT_FLAG;
10767 BNX2X_DEV_INFO("single port device\n");
10770 val = REG_RD(bp, MCP_REG_MCPR_NVM_CFG4);
10771 bp->common.flash_size = (BNX2X_NVRAM_1MB_SIZE <<
10772 (val & MCPR_NVM_CFG4_FLASH_SIZE));
10773 BNX2X_DEV_INFO("flash_size 0x%x (%d)\n",
10774 bp->common.flash_size, bp->common.flash_size);
10776 bnx2x_init_shmem(bp);
10778 bp->common.shmem2_base = REG_RD(bp, (BP_PATH(bp) ?
10779 MISC_REG_GENERIC_CR_1 :
10780 MISC_REG_GENERIC_CR_0));
10782 bp->link_params.shmem_base = bp->common.shmem_base;
10783 bp->link_params.shmem2_base = bp->common.shmem2_base;
10784 if (SHMEM2_RD(bp, size) >
10785 (u32)offsetof(struct shmem2_region, lfa_host_addr[BP_PORT(bp)]))
10786 bp->link_params.lfa_base =
10787 REG_RD(bp, bp->common.shmem2_base +
10788 (u32)offsetof(struct shmem2_region,
10789 lfa_host_addr[BP_PORT(bp)]));
10791 bp->link_params.lfa_base = 0;
10792 BNX2X_DEV_INFO("shmem offset 0x%x shmem2 offset 0x%x\n",
10793 bp->common.shmem_base, bp->common.shmem2_base);
10795 if (!bp->common.shmem_base) {
10796 BNX2X_DEV_INFO("MCP not active\n");
10797 bp->flags |= NO_MCP_FLAG;
10801 bp->common.hw_config = SHMEM_RD(bp, dev_info.shared_hw_config.config);
10802 BNX2X_DEV_INFO("hw_config 0x%08x\n", bp->common.hw_config);
10804 bp->link_params.hw_led_mode = ((bp->common.hw_config &
10805 SHARED_HW_CFG_LED_MODE_MASK) >>
10806 SHARED_HW_CFG_LED_MODE_SHIFT);
10808 bp->link_params.feature_config_flags = 0;
10809 val = SHMEM_RD(bp, dev_info.shared_feature_config.config);
10810 if (val & SHARED_FEAT_CFG_OVERRIDE_PREEMPHASIS_CFG_ENABLED)
10811 bp->link_params.feature_config_flags |=
10812 FEATURE_CONFIG_OVERRIDE_PREEMPHASIS_ENABLED;
10814 bp->link_params.feature_config_flags &=
10815 ~FEATURE_CONFIG_OVERRIDE_PREEMPHASIS_ENABLED;
10817 val = SHMEM_RD(bp, dev_info.bc_rev) >> 8;
10818 bp->common.bc_ver = val;
10819 BNX2X_DEV_INFO("bc_ver %X\n", val);
10820 if (val < BNX2X_BC_VER) {
10821 /* for now only warn
10822 * later we might need to enforce this */
10823 BNX2X_ERR("This driver needs bc_ver %X but found %X, please upgrade BC\n",
10824 BNX2X_BC_VER, val);
10826 bp->link_params.feature_config_flags |=
10827 (val >= REQ_BC_VER_4_VRFY_FIRST_PHY_OPT_MDL) ?
10828 FEATURE_CONFIG_BC_SUPPORTS_OPT_MDL_VRFY : 0;
10830 bp->link_params.feature_config_flags |=
10831 (val >= REQ_BC_VER_4_VRFY_SPECIFIC_PHY_OPT_MDL) ?
10832 FEATURE_CONFIG_BC_SUPPORTS_DUAL_PHY_OPT_MDL_VRFY : 0;
10833 bp->link_params.feature_config_flags |=
10834 (val >= REQ_BC_VER_4_VRFY_AFEX_SUPPORTED) ?
10835 FEATURE_CONFIG_BC_SUPPORTS_AFEX : 0;
10836 bp->link_params.feature_config_flags |=
10837 (val >= REQ_BC_VER_4_SFP_TX_DISABLE_SUPPORTED) ?
10838 FEATURE_CONFIG_BC_SUPPORTS_SFP_TX_DISABLED : 0;
10840 bp->link_params.feature_config_flags |=
10841 (val >= REQ_BC_VER_4_MT_SUPPORTED) ?
10842 FEATURE_CONFIG_MT_SUPPORT : 0;
10844 bp->flags |= (val >= REQ_BC_VER_4_PFC_STATS_SUPPORTED) ?
10845 BC_SUPPORTS_PFC_STATS : 0;
10847 bp->flags |= (val >= REQ_BC_VER_4_FCOE_FEATURES) ?
10848 BC_SUPPORTS_FCOE_FEATURES : 0;
10850 bp->flags |= (val >= REQ_BC_VER_4_DCBX_ADMIN_MSG_NON_PMF) ?
10851 BC_SUPPORTS_DCBX_MSG_NON_PMF : 0;
10853 bp->flags |= (val >= REQ_BC_VER_4_RMMOD_CMD) ?
10854 BC_SUPPORTS_RMMOD_CMD : 0;
10856 boot_mode = SHMEM_RD(bp,
10857 dev_info.port_feature_config[BP_PORT(bp)].mba_config) &
10858 PORT_FEATURE_MBA_BOOT_AGENT_TYPE_MASK;
10859 switch (boot_mode) {
10860 case PORT_FEATURE_MBA_BOOT_AGENT_TYPE_PXE:
10861 bp->common.boot_mode = FEATURE_ETH_BOOTMODE_PXE;
10863 case PORT_FEATURE_MBA_BOOT_AGENT_TYPE_ISCSIB:
10864 bp->common.boot_mode = FEATURE_ETH_BOOTMODE_ISCSI;
10866 case PORT_FEATURE_MBA_BOOT_AGENT_TYPE_FCOE_BOOT:
10867 bp->common.boot_mode = FEATURE_ETH_BOOTMODE_FCOE;
10869 case PORT_FEATURE_MBA_BOOT_AGENT_TYPE_NONE:
10870 bp->common.boot_mode = FEATURE_ETH_BOOTMODE_NONE;
10874 pci_read_config_word(bp->pdev, bp->pdev->pm_cap + PCI_PM_PMC, &pmc);
10875 bp->flags |= (pmc & PCI_PM_CAP_PME_D3cold) ? 0 : NO_WOL_FLAG;
10877 BNX2X_DEV_INFO("%sWoL capable\n",
10878 (bp->flags & NO_WOL_FLAG) ? "not " : "");
10880 val = SHMEM_RD(bp, dev_info.shared_hw_config.part_num);
10881 val2 = SHMEM_RD(bp, dev_info.shared_hw_config.part_num[4]);
10882 val3 = SHMEM_RD(bp, dev_info.shared_hw_config.part_num[8]);
10883 val4 = SHMEM_RD(bp, dev_info.shared_hw_config.part_num[12]);
10885 dev_info(&bp->pdev->dev, "part number %X-%X-%X-%X\n",
10886 val, val2, val3, val4);
10889 #define IGU_FID(val) GET_FIELD((val), IGU_REG_MAPPING_MEMORY_FID)
10890 #define IGU_VEC(val) GET_FIELD((val), IGU_REG_MAPPING_MEMORY_VECTOR)
10892 static int bnx2x_get_igu_cam_info(struct bnx2x *bp)
10894 int pfid = BP_FUNC(bp);
10897 u8 fid, igu_sb_cnt = 0;
10899 bp->igu_base_sb = 0xff;
10900 if (CHIP_INT_MODE_IS_BC(bp)) {
10901 int vn = BP_VN(bp);
10902 igu_sb_cnt = bp->igu_sb_cnt;
10903 bp->igu_base_sb = (CHIP_MODE_IS_4_PORT(bp) ? pfid : vn) *
10906 bp->igu_dsb_id = E1HVN_MAX * FP_SB_MAX_E1x +
10907 (CHIP_MODE_IS_4_PORT(bp) ? pfid : vn);
10912 /* IGU in normal mode - read CAM */
10913 for (igu_sb_id = 0; igu_sb_id < IGU_REG_MAPPING_MEMORY_SIZE;
10915 val = REG_RD(bp, IGU_REG_MAPPING_MEMORY + igu_sb_id * 4);
10916 if (!(val & IGU_REG_MAPPING_MEMORY_VALID))
10918 fid = IGU_FID(val);
10919 if ((fid & IGU_FID_ENCODE_IS_PF)) {
10920 if ((fid & IGU_FID_PF_NUM_MASK) != pfid)
10922 if (IGU_VEC(val) == 0)
10923 /* default status block */
10924 bp->igu_dsb_id = igu_sb_id;
10926 if (bp->igu_base_sb == 0xff)
10927 bp->igu_base_sb = igu_sb_id;
10933 #ifdef CONFIG_PCI_MSI
10934 /* Due to new PF resource allocation by MFW T7.4 and above, it's
10935 * optional that number of CAM entries will not be equal to the value
10936 * advertised in PCI.
10937 * Driver should use the minimal value of both as the actual status
10940 bp->igu_sb_cnt = min_t(int, bp->igu_sb_cnt, igu_sb_cnt);
10943 if (igu_sb_cnt == 0) {
10944 BNX2X_ERR("CAM configuration error\n");
10951 static void bnx2x_link_settings_supported(struct bnx2x *bp, u32 switch_cfg)
10953 int cfg_size = 0, idx, port = BP_PORT(bp);
10955 /* Aggregation of supported attributes of all external phys */
10956 bp->port.supported[0] = 0;
10957 bp->port.supported[1] = 0;
10958 switch (bp->link_params.num_phys) {
10960 bp->port.supported[0] = bp->link_params.phy[INT_PHY].supported;
10964 bp->port.supported[0] = bp->link_params.phy[EXT_PHY1].supported;
10968 if (bp->link_params.multi_phy_config &
10969 PORT_HW_CFG_PHY_SWAPPED_ENABLED) {
10970 bp->port.supported[1] =
10971 bp->link_params.phy[EXT_PHY1].supported;
10972 bp->port.supported[0] =
10973 bp->link_params.phy[EXT_PHY2].supported;
10975 bp->port.supported[0] =
10976 bp->link_params.phy[EXT_PHY1].supported;
10977 bp->port.supported[1] =
10978 bp->link_params.phy[EXT_PHY2].supported;
10984 if (!(bp->port.supported[0] || bp->port.supported[1])) {
10985 BNX2X_ERR("NVRAM config error. BAD phy config. PHY1 config 0x%x, PHY2 config 0x%x\n",
10987 dev_info.port_hw_config[port].external_phy_config),
10989 dev_info.port_hw_config[port].external_phy_config2));
10993 if (CHIP_IS_E3(bp))
10994 bp->port.phy_addr = REG_RD(bp, MISC_REG_WC0_CTRL_PHY_ADDR);
10996 switch (switch_cfg) {
10997 case SWITCH_CFG_1G:
10998 bp->port.phy_addr = REG_RD(
10999 bp, NIG_REG_SERDES0_CTRL_PHY_ADDR + port*0x10);
11001 case SWITCH_CFG_10G:
11002 bp->port.phy_addr = REG_RD(
11003 bp, NIG_REG_XGXS0_CTRL_PHY_ADDR + port*0x18);
11006 BNX2X_ERR("BAD switch_cfg link_config 0x%x\n",
11007 bp->port.link_config[0]);
11011 BNX2X_DEV_INFO("phy_addr 0x%x\n", bp->port.phy_addr);
11012 /* mask what we support according to speed_cap_mask per configuration */
11013 for (idx = 0; idx < cfg_size; idx++) {
11014 if (!(bp->link_params.speed_cap_mask[idx] &
11015 PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_HALF))
11016 bp->port.supported[idx] &= ~SUPPORTED_10baseT_Half;
11018 if (!(bp->link_params.speed_cap_mask[idx] &
11019 PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_FULL))
11020 bp->port.supported[idx] &= ~SUPPORTED_10baseT_Full;
11022 if (!(bp->link_params.speed_cap_mask[idx] &
11023 PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_HALF))
11024 bp->port.supported[idx] &= ~SUPPORTED_100baseT_Half;
11026 if (!(bp->link_params.speed_cap_mask[idx] &
11027 PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_FULL))
11028 bp->port.supported[idx] &= ~SUPPORTED_100baseT_Full;
11030 if (!(bp->link_params.speed_cap_mask[idx] &
11031 PORT_HW_CFG_SPEED_CAPABILITY_D0_1G))
11032 bp->port.supported[idx] &= ~(SUPPORTED_1000baseT_Half |
11033 SUPPORTED_1000baseT_Full);
11035 if (!(bp->link_params.speed_cap_mask[idx] &
11036 PORT_HW_CFG_SPEED_CAPABILITY_D0_2_5G))
11037 bp->port.supported[idx] &= ~SUPPORTED_2500baseX_Full;
11039 if (!(bp->link_params.speed_cap_mask[idx] &
11040 PORT_HW_CFG_SPEED_CAPABILITY_D0_10G))
11041 bp->port.supported[idx] &= ~SUPPORTED_10000baseT_Full;
11043 if (!(bp->link_params.speed_cap_mask[idx] &
11044 PORT_HW_CFG_SPEED_CAPABILITY_D0_20G))
11045 bp->port.supported[idx] &= ~SUPPORTED_20000baseKR2_Full;
11048 BNX2X_DEV_INFO("supported 0x%x 0x%x\n", bp->port.supported[0],
11049 bp->port.supported[1]);
11052 static void bnx2x_link_settings_requested(struct bnx2x *bp)
11054 u32 link_config, idx, cfg_size = 0;
11055 bp->port.advertising[0] = 0;
11056 bp->port.advertising[1] = 0;
11057 switch (bp->link_params.num_phys) {
11066 for (idx = 0; idx < cfg_size; idx++) {
11067 bp->link_params.req_duplex[idx] = DUPLEX_FULL;
11068 link_config = bp->port.link_config[idx];
11069 switch (link_config & PORT_FEATURE_LINK_SPEED_MASK) {
11070 case PORT_FEATURE_LINK_SPEED_AUTO:
11071 if (bp->port.supported[idx] & SUPPORTED_Autoneg) {
11072 bp->link_params.req_line_speed[idx] =
11074 bp->port.advertising[idx] |=
11075 bp->port.supported[idx];
11076 if (bp->link_params.phy[EXT_PHY1].type ==
11077 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84833)
11078 bp->port.advertising[idx] |=
11079 (SUPPORTED_100baseT_Half |
11080 SUPPORTED_100baseT_Full);
11082 /* force 10G, no AN */
11083 bp->link_params.req_line_speed[idx] =
11085 bp->port.advertising[idx] |=
11086 (ADVERTISED_10000baseT_Full |
11092 case PORT_FEATURE_LINK_SPEED_10M_FULL:
11093 if (bp->port.supported[idx] & SUPPORTED_10baseT_Full) {
11094 bp->link_params.req_line_speed[idx] =
11096 bp->port.advertising[idx] |=
11097 (ADVERTISED_10baseT_Full |
11100 BNX2X_ERR("NVRAM config error. Invalid link_config 0x%x speed_cap_mask 0x%x\n",
11102 bp->link_params.speed_cap_mask[idx]);
11107 case PORT_FEATURE_LINK_SPEED_10M_HALF:
11108 if (bp->port.supported[idx] & SUPPORTED_10baseT_Half) {
11109 bp->link_params.req_line_speed[idx] =
11111 bp->link_params.req_duplex[idx] =
11113 bp->port.advertising[idx] |=
11114 (ADVERTISED_10baseT_Half |
11117 BNX2X_ERR("NVRAM config error. Invalid link_config 0x%x speed_cap_mask 0x%x\n",
11119 bp->link_params.speed_cap_mask[idx]);
11124 case PORT_FEATURE_LINK_SPEED_100M_FULL:
11125 if (bp->port.supported[idx] &
11126 SUPPORTED_100baseT_Full) {
11127 bp->link_params.req_line_speed[idx] =
11129 bp->port.advertising[idx] |=
11130 (ADVERTISED_100baseT_Full |
11133 BNX2X_ERR("NVRAM config error. Invalid link_config 0x%x speed_cap_mask 0x%x\n",
11135 bp->link_params.speed_cap_mask[idx]);
11140 case PORT_FEATURE_LINK_SPEED_100M_HALF:
11141 if (bp->port.supported[idx] &
11142 SUPPORTED_100baseT_Half) {
11143 bp->link_params.req_line_speed[idx] =
11145 bp->link_params.req_duplex[idx] =
11147 bp->port.advertising[idx] |=
11148 (ADVERTISED_100baseT_Half |
11151 BNX2X_ERR("NVRAM config error. Invalid link_config 0x%x speed_cap_mask 0x%x\n",
11153 bp->link_params.speed_cap_mask[idx]);
11158 case PORT_FEATURE_LINK_SPEED_1G:
11159 if (bp->port.supported[idx] &
11160 SUPPORTED_1000baseT_Full) {
11161 bp->link_params.req_line_speed[idx] =
11163 bp->port.advertising[idx] |=
11164 (ADVERTISED_1000baseT_Full |
11166 } else if (bp->port.supported[idx] &
11167 SUPPORTED_1000baseKX_Full) {
11168 bp->link_params.req_line_speed[idx] =
11170 bp->port.advertising[idx] |=
11171 ADVERTISED_1000baseKX_Full;
11173 BNX2X_ERR("NVRAM config error. Invalid link_config 0x%x speed_cap_mask 0x%x\n",
11175 bp->link_params.speed_cap_mask[idx]);
11180 case PORT_FEATURE_LINK_SPEED_2_5G:
11181 if (bp->port.supported[idx] &
11182 SUPPORTED_2500baseX_Full) {
11183 bp->link_params.req_line_speed[idx] =
11185 bp->port.advertising[idx] |=
11186 (ADVERTISED_2500baseX_Full |
11189 BNX2X_ERR("NVRAM config error. Invalid link_config 0x%x speed_cap_mask 0x%x\n",
11191 bp->link_params.speed_cap_mask[idx]);
11196 case PORT_FEATURE_LINK_SPEED_10G_CX4:
11197 if (bp->port.supported[idx] &
11198 SUPPORTED_10000baseT_Full) {
11199 bp->link_params.req_line_speed[idx] =
11201 bp->port.advertising[idx] |=
11202 (ADVERTISED_10000baseT_Full |
11204 } else if (bp->port.supported[idx] &
11205 SUPPORTED_10000baseKR_Full) {
11206 bp->link_params.req_line_speed[idx] =
11208 bp->port.advertising[idx] |=
11209 (ADVERTISED_10000baseKR_Full |
11212 BNX2X_ERR("NVRAM config error. Invalid link_config 0x%x speed_cap_mask 0x%x\n",
11214 bp->link_params.speed_cap_mask[idx]);
11218 case PORT_FEATURE_LINK_SPEED_20G:
11219 bp->link_params.req_line_speed[idx] = SPEED_20000;
11223 BNX2X_ERR("NVRAM config error. BAD link speed link_config 0x%x\n",
11225 bp->link_params.req_line_speed[idx] =
11227 bp->port.advertising[idx] =
11228 bp->port.supported[idx];
11232 bp->link_params.req_flow_ctrl[idx] = (link_config &
11233 PORT_FEATURE_FLOW_CONTROL_MASK);
11234 if (bp->link_params.req_flow_ctrl[idx] ==
11235 BNX2X_FLOW_CTRL_AUTO) {
11236 if (!(bp->port.supported[idx] & SUPPORTED_Autoneg))
11237 bp->link_params.req_flow_ctrl[idx] =
11238 BNX2X_FLOW_CTRL_NONE;
11240 bnx2x_set_requested_fc(bp);
11243 BNX2X_DEV_INFO("req_line_speed %d req_duplex %d req_flow_ctrl 0x%x advertising 0x%x\n",
11244 bp->link_params.req_line_speed[idx],
11245 bp->link_params.req_duplex[idx],
11246 bp->link_params.req_flow_ctrl[idx],
11247 bp->port.advertising[idx]);
11251 static void bnx2x_set_mac_buf(u8 *mac_buf, u32 mac_lo, u16 mac_hi)
11253 __be16 mac_hi_be = cpu_to_be16(mac_hi);
11254 __be32 mac_lo_be = cpu_to_be32(mac_lo);
11255 memcpy(mac_buf, &mac_hi_be, sizeof(mac_hi_be));
11256 memcpy(mac_buf + sizeof(mac_hi_be), &mac_lo_be, sizeof(mac_lo_be));
11259 static void bnx2x_get_port_hwinfo(struct bnx2x *bp)
11261 int port = BP_PORT(bp);
11263 u32 ext_phy_type, ext_phy_config, eee_mode;
11265 bp->link_params.bp = bp;
11266 bp->link_params.port = port;
11268 bp->link_params.lane_config =
11269 SHMEM_RD(bp, dev_info.port_hw_config[port].lane_config);
11271 bp->link_params.speed_cap_mask[0] =
11273 dev_info.port_hw_config[port].speed_capability_mask) &
11274 PORT_HW_CFG_SPEED_CAPABILITY_D0_MASK;
11275 bp->link_params.speed_cap_mask[1] =
11277 dev_info.port_hw_config[port].speed_capability_mask2) &
11278 PORT_HW_CFG_SPEED_CAPABILITY_D0_MASK;
11279 bp->port.link_config[0] =
11280 SHMEM_RD(bp, dev_info.port_feature_config[port].link_config);
11282 bp->port.link_config[1] =
11283 SHMEM_RD(bp, dev_info.port_feature_config[port].link_config2);
11285 bp->link_params.multi_phy_config =
11286 SHMEM_RD(bp, dev_info.port_hw_config[port].multi_phy_config);
11287 /* If the device is capable of WoL, set the default state according
11290 config = SHMEM_RD(bp, dev_info.port_feature_config[port].config);
11291 bp->wol = (!(bp->flags & NO_WOL_FLAG) &&
11292 (config & PORT_FEATURE_WOL_ENABLED));
11294 if ((config & PORT_FEAT_CFG_STORAGE_PERSONALITY_MASK) ==
11295 PORT_FEAT_CFG_STORAGE_PERSONALITY_FCOE && !IS_MF(bp))
11296 bp->flags |= NO_ISCSI_FLAG;
11297 if ((config & PORT_FEAT_CFG_STORAGE_PERSONALITY_MASK) ==
11298 PORT_FEAT_CFG_STORAGE_PERSONALITY_ISCSI && !(IS_MF(bp)))
11299 bp->flags |= NO_FCOE_FLAG;
11301 BNX2X_DEV_INFO("lane_config 0x%08x speed_cap_mask0 0x%08x link_config0 0x%08x\n",
11302 bp->link_params.lane_config,
11303 bp->link_params.speed_cap_mask[0],
11304 bp->port.link_config[0]);
11306 bp->link_params.switch_cfg = (bp->port.link_config[0] &
11307 PORT_FEATURE_CONNECTED_SWITCH_MASK);
11308 bnx2x_phy_probe(&bp->link_params);
11309 bnx2x_link_settings_supported(bp, bp->link_params.switch_cfg);
11311 bnx2x_link_settings_requested(bp);
11314 * If connected directly, work with the internal PHY, otherwise, work
11315 * with the external PHY
11319 dev_info.port_hw_config[port].external_phy_config);
11320 ext_phy_type = XGXS_EXT_PHY_TYPE(ext_phy_config);
11321 if (ext_phy_type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT)
11322 bp->mdio.prtad = bp->port.phy_addr;
11324 else if ((ext_phy_type != PORT_HW_CFG_XGXS_EXT_PHY_TYPE_FAILURE) &&
11325 (ext_phy_type != PORT_HW_CFG_XGXS_EXT_PHY_TYPE_NOT_CONN))
11327 XGXS_EXT_PHY_ADDR(ext_phy_config);
11329 /* Configure link feature according to nvram value */
11330 eee_mode = (((SHMEM_RD(bp, dev_info.
11331 port_feature_config[port].eee_power_mode)) &
11332 PORT_FEAT_CFG_EEE_POWER_MODE_MASK) >>
11333 PORT_FEAT_CFG_EEE_POWER_MODE_SHIFT);
11334 if (eee_mode != PORT_FEAT_CFG_EEE_POWER_MODE_DISABLED) {
11335 bp->link_params.eee_mode = EEE_MODE_ADV_LPI |
11336 EEE_MODE_ENABLE_LPI |
11337 EEE_MODE_OUTPUT_TIME;
11339 bp->link_params.eee_mode = 0;
11343 void bnx2x_get_iscsi_info(struct bnx2x *bp)
11345 u32 no_flags = NO_ISCSI_FLAG;
11346 int port = BP_PORT(bp);
11347 u32 max_iscsi_conn = FW_ENCODE_32BIT_PATTERN ^ SHMEM_RD(bp,
11348 drv_lic_key[port].max_iscsi_conn);
11350 if (!CNIC_SUPPORT(bp)) {
11351 bp->flags |= no_flags;
11355 /* Get the number of maximum allowed iSCSI connections */
11356 bp->cnic_eth_dev.max_iscsi_conn =
11357 (max_iscsi_conn & BNX2X_MAX_ISCSI_INIT_CONN_MASK) >>
11358 BNX2X_MAX_ISCSI_INIT_CONN_SHIFT;
11360 BNX2X_DEV_INFO("max_iscsi_conn 0x%x\n",
11361 bp->cnic_eth_dev.max_iscsi_conn);
11364 * If maximum allowed number of connections is zero -
11365 * disable the feature.
11367 if (!bp->cnic_eth_dev.max_iscsi_conn)
11368 bp->flags |= no_flags;
11371 static void bnx2x_get_ext_wwn_info(struct bnx2x *bp, int func)
11374 bp->cnic_eth_dev.fcoe_wwn_port_name_hi =
11375 MF_CFG_RD(bp, func_ext_config[func].fcoe_wwn_port_name_upper);
11376 bp->cnic_eth_dev.fcoe_wwn_port_name_lo =
11377 MF_CFG_RD(bp, func_ext_config[func].fcoe_wwn_port_name_lower);
11380 bp->cnic_eth_dev.fcoe_wwn_node_name_hi =
11381 MF_CFG_RD(bp, func_ext_config[func].fcoe_wwn_node_name_upper);
11382 bp->cnic_eth_dev.fcoe_wwn_node_name_lo =
11383 MF_CFG_RD(bp, func_ext_config[func].fcoe_wwn_node_name_lower);
11386 static int bnx2x_shared_fcoe_funcs(struct bnx2x *bp)
11393 /* iterate over absolute function ids for this path: */
11394 for (fid = BP_PATH(bp); fid < E2_FUNC_MAX * 2; fid += 2) {
11395 if (IS_MF_SD(bp)) {
11396 u32 cfg = MF_CFG_RD(bp,
11397 func_mf_config[fid].config);
11399 if (!(cfg & FUNC_MF_CFG_FUNC_HIDE) &&
11400 ((cfg & FUNC_MF_CFG_PROTOCOL_MASK) ==
11401 FUNC_MF_CFG_PROTOCOL_FCOE))
11404 u32 cfg = MF_CFG_RD(bp,
11405 func_ext_config[fid].
11408 if ((cfg & MACP_FUNC_CFG_FLAGS_ENABLED) &&
11409 (cfg & MACP_FUNC_CFG_FLAGS_FCOE_OFFLOAD))
11414 int port, port_cnt = CHIP_MODE_IS_4_PORT(bp) ? 2 : 1;
11416 for (port = 0; port < port_cnt; port++) {
11417 u32 lic = SHMEM_RD(bp,
11418 drv_lic_key[port].max_fcoe_conn) ^
11419 FW_ENCODE_32BIT_PATTERN;
11428 static void bnx2x_get_fcoe_info(struct bnx2x *bp)
11430 int port = BP_PORT(bp);
11431 int func = BP_ABS_FUNC(bp);
11432 u32 max_fcoe_conn = FW_ENCODE_32BIT_PATTERN ^ SHMEM_RD(bp,
11433 drv_lic_key[port].max_fcoe_conn);
11434 u8 num_fcoe_func = bnx2x_shared_fcoe_funcs(bp);
11436 if (!CNIC_SUPPORT(bp)) {
11437 bp->flags |= NO_FCOE_FLAG;
11441 /* Get the number of maximum allowed FCoE connections */
11442 bp->cnic_eth_dev.max_fcoe_conn =
11443 (max_fcoe_conn & BNX2X_MAX_FCOE_INIT_CONN_MASK) >>
11444 BNX2X_MAX_FCOE_INIT_CONN_SHIFT;
11446 /* Calculate the number of maximum allowed FCoE tasks */
11447 bp->cnic_eth_dev.max_fcoe_exchanges = MAX_NUM_FCOE_TASKS_PER_ENGINE;
11449 /* check if FCoE resources must be shared between different functions */
11451 bp->cnic_eth_dev.max_fcoe_exchanges /= num_fcoe_func;
11453 /* Read the WWN: */
11456 bp->cnic_eth_dev.fcoe_wwn_port_name_hi =
11458 dev_info.port_hw_config[port].
11459 fcoe_wwn_port_name_upper);
11460 bp->cnic_eth_dev.fcoe_wwn_port_name_lo =
11462 dev_info.port_hw_config[port].
11463 fcoe_wwn_port_name_lower);
11466 bp->cnic_eth_dev.fcoe_wwn_node_name_hi =
11468 dev_info.port_hw_config[port].
11469 fcoe_wwn_node_name_upper);
11470 bp->cnic_eth_dev.fcoe_wwn_node_name_lo =
11472 dev_info.port_hw_config[port].
11473 fcoe_wwn_node_name_lower);
11474 } else if (!IS_MF_SD(bp)) {
11475 /* Read the WWN info only if the FCoE feature is enabled for
11478 if (BNX2X_HAS_MF_EXT_PROTOCOL_FCOE(bp))
11479 bnx2x_get_ext_wwn_info(bp, func);
11481 if (BNX2X_IS_MF_SD_PROTOCOL_FCOE(bp) && !CHIP_IS_E1x(bp))
11482 bnx2x_get_ext_wwn_info(bp, func);
11485 BNX2X_DEV_INFO("max_fcoe_conn 0x%x\n", bp->cnic_eth_dev.max_fcoe_conn);
11488 * If maximum allowed number of connections is zero -
11489 * disable the feature.
11491 if (!bp->cnic_eth_dev.max_fcoe_conn)
11492 bp->flags |= NO_FCOE_FLAG;
11495 static void bnx2x_get_cnic_info(struct bnx2x *bp)
11498 * iSCSI may be dynamically disabled but reading
11499 * info here we will decrease memory usage by driver
11500 * if the feature is disabled for good
11502 bnx2x_get_iscsi_info(bp);
11503 bnx2x_get_fcoe_info(bp);
11506 static void bnx2x_get_cnic_mac_hwinfo(struct bnx2x *bp)
11509 int func = BP_ABS_FUNC(bp);
11510 int port = BP_PORT(bp);
11511 u8 *iscsi_mac = bp->cnic_eth_dev.iscsi_mac;
11512 u8 *fip_mac = bp->fip_mac;
11515 /* iSCSI and FCoE NPAR MACs: if there is no either iSCSI or
11516 * FCoE MAC then the appropriate feature should be disabled.
11517 * In non SD mode features configuration comes from struct
11520 if (!IS_MF_SD(bp)) {
11521 u32 cfg = MF_CFG_RD(bp, func_ext_config[func].func_cfg);
11522 if (cfg & MACP_FUNC_CFG_FLAGS_ISCSI_OFFLOAD) {
11523 val2 = MF_CFG_RD(bp, func_ext_config[func].
11524 iscsi_mac_addr_upper);
11525 val = MF_CFG_RD(bp, func_ext_config[func].
11526 iscsi_mac_addr_lower);
11527 bnx2x_set_mac_buf(iscsi_mac, val, val2);
11529 ("Read iSCSI MAC: %pM\n", iscsi_mac);
11531 bp->flags |= NO_ISCSI_OOO_FLAG | NO_ISCSI_FLAG;
11534 if (cfg & MACP_FUNC_CFG_FLAGS_FCOE_OFFLOAD) {
11535 val2 = MF_CFG_RD(bp, func_ext_config[func].
11536 fcoe_mac_addr_upper);
11537 val = MF_CFG_RD(bp, func_ext_config[func].
11538 fcoe_mac_addr_lower);
11539 bnx2x_set_mac_buf(fip_mac, val, val2);
11541 ("Read FCoE L2 MAC: %pM\n", fip_mac);
11543 bp->flags |= NO_FCOE_FLAG;
11546 bp->mf_ext_config = cfg;
11548 } else { /* SD MODE */
11549 if (BNX2X_IS_MF_SD_PROTOCOL_ISCSI(bp)) {
11550 /* use primary mac as iscsi mac */
11551 memcpy(iscsi_mac, bp->dev->dev_addr, ETH_ALEN);
11553 BNX2X_DEV_INFO("SD ISCSI MODE\n");
11555 ("Read iSCSI MAC: %pM\n", iscsi_mac);
11556 } else if (BNX2X_IS_MF_SD_PROTOCOL_FCOE(bp)) {
11557 /* use primary mac as fip mac */
11558 memcpy(fip_mac, bp->dev->dev_addr, ETH_ALEN);
11559 BNX2X_DEV_INFO("SD FCoE MODE\n");
11561 ("Read FIP MAC: %pM\n", fip_mac);
11565 /* If this is a storage-only interface, use SAN mac as
11566 * primary MAC. Notice that for SD this is already the case,
11567 * as the SAN mac was copied from the primary MAC.
11569 if (IS_MF_FCOE_AFEX(bp))
11570 memcpy(bp->dev->dev_addr, fip_mac, ETH_ALEN);
11572 val2 = SHMEM_RD(bp, dev_info.port_hw_config[port].
11574 val = SHMEM_RD(bp, dev_info.port_hw_config[port].
11576 bnx2x_set_mac_buf(iscsi_mac, val, val2);
11578 val2 = SHMEM_RD(bp, dev_info.port_hw_config[port].
11579 fcoe_fip_mac_upper);
11580 val = SHMEM_RD(bp, dev_info.port_hw_config[port].
11581 fcoe_fip_mac_lower);
11582 bnx2x_set_mac_buf(fip_mac, val, val2);
11585 /* Disable iSCSI OOO if MAC configuration is invalid. */
11586 if (!is_valid_ether_addr(iscsi_mac)) {
11587 bp->flags |= NO_ISCSI_OOO_FLAG | NO_ISCSI_FLAG;
11588 eth_zero_addr(iscsi_mac);
11591 /* Disable FCoE if MAC configuration is invalid. */
11592 if (!is_valid_ether_addr(fip_mac)) {
11593 bp->flags |= NO_FCOE_FLAG;
11594 eth_zero_addr(bp->fip_mac);
11598 static void bnx2x_get_mac_hwinfo(struct bnx2x *bp)
11601 int func = BP_ABS_FUNC(bp);
11602 int port = BP_PORT(bp);
11604 /* Zero primary MAC configuration */
11605 eth_zero_addr(bp->dev->dev_addr);
11607 if (BP_NOMCP(bp)) {
11608 BNX2X_ERROR("warning: random MAC workaround active\n");
11609 eth_hw_addr_random(bp->dev);
11610 } else if (IS_MF(bp)) {
11611 val2 = MF_CFG_RD(bp, func_mf_config[func].mac_upper);
11612 val = MF_CFG_RD(bp, func_mf_config[func].mac_lower);
11613 if ((val2 != FUNC_MF_CFG_UPPERMAC_DEFAULT) &&
11614 (val != FUNC_MF_CFG_LOWERMAC_DEFAULT))
11615 bnx2x_set_mac_buf(bp->dev->dev_addr, val, val2);
11617 if (CNIC_SUPPORT(bp))
11618 bnx2x_get_cnic_mac_hwinfo(bp);
11620 /* in SF read MACs from port configuration */
11621 val2 = SHMEM_RD(bp, dev_info.port_hw_config[port].mac_upper);
11622 val = SHMEM_RD(bp, dev_info.port_hw_config[port].mac_lower);
11623 bnx2x_set_mac_buf(bp->dev->dev_addr, val, val2);
11625 if (CNIC_SUPPORT(bp))
11626 bnx2x_get_cnic_mac_hwinfo(bp);
11629 if (!BP_NOMCP(bp)) {
11630 /* Read physical port identifier from shmem */
11631 val2 = SHMEM_RD(bp, dev_info.port_hw_config[port].mac_upper);
11632 val = SHMEM_RD(bp, dev_info.port_hw_config[port].mac_lower);
11633 bnx2x_set_mac_buf(bp->phys_port_id, val, val2);
11634 bp->flags |= HAS_PHYS_PORT_ID;
11637 memcpy(bp->link_params.mac_addr, bp->dev->dev_addr, ETH_ALEN);
11639 if (!is_valid_ether_addr(bp->dev->dev_addr))
11640 dev_err(&bp->pdev->dev,
11641 "bad Ethernet MAC address configuration: %pM\n"
11642 "change it manually before bringing up the appropriate network interface\n",
11643 bp->dev->dev_addr);
11646 static bool bnx2x_get_dropless_info(struct bnx2x *bp)
11654 if (IS_MF(bp) && !CHIP_IS_E1x(bp)) {
11655 /* Take function: tmp = func */
11656 tmp = BP_ABS_FUNC(bp);
11657 cfg = MF_CFG_RD(bp, func_ext_config[tmp].func_cfg);
11658 cfg = !!(cfg & MACP_FUNC_CFG_PAUSE_ON_HOST_RING);
11660 /* Take port: tmp = port */
11663 dev_info.port_hw_config[tmp].generic_features);
11664 cfg = !!(cfg & PORT_HW_CFG_PAUSE_ON_HOST_RING_ENABLED);
11669 static void validate_set_si_mode(struct bnx2x *bp)
11671 u8 func = BP_ABS_FUNC(bp);
11674 val = MF_CFG_RD(bp, func_mf_config[func].mac_upper);
11676 /* check for legal mac (upper bytes) */
11677 if (val != 0xffff) {
11678 bp->mf_mode = MULTI_FUNCTION_SI;
11679 bp->mf_config[BP_VN(bp)] =
11680 MF_CFG_RD(bp, func_mf_config[func].config);
11682 BNX2X_DEV_INFO("illegal MAC address for SI\n");
11685 static int bnx2x_get_hwinfo(struct bnx2x *bp)
11687 int /*abs*/func = BP_ABS_FUNC(bp);
11689 u32 val = 0, val2 = 0;
11692 /* Validate that chip access is feasible */
11693 if (REG_RD(bp, MISC_REG_CHIP_NUM) == 0xffffffff) {
11694 dev_err(&bp->pdev->dev,
11695 "Chip read returns all Fs. Preventing probe from continuing\n");
11699 bnx2x_get_common_hwinfo(bp);
11702 * initialize IGU parameters
11704 if (CHIP_IS_E1x(bp)) {
11705 bp->common.int_block = INT_BLOCK_HC;
11707 bp->igu_dsb_id = DEF_SB_IGU_ID;
11708 bp->igu_base_sb = 0;
11710 bp->common.int_block = INT_BLOCK_IGU;
11712 /* do not allow device reset during IGU info processing */
11713 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_RESET);
11715 val = REG_RD(bp, IGU_REG_BLOCK_CONFIGURATION);
11717 if (val & IGU_BLOCK_CONFIGURATION_REG_BACKWARD_COMP_EN) {
11720 BNX2X_DEV_INFO("FORCING Normal Mode\n");
11722 val &= ~(IGU_BLOCK_CONFIGURATION_REG_BACKWARD_COMP_EN);
11723 REG_WR(bp, IGU_REG_BLOCK_CONFIGURATION, val);
11724 REG_WR(bp, IGU_REG_RESET_MEMORIES, 0x7f);
11726 while (tout && REG_RD(bp, IGU_REG_RESET_MEMORIES)) {
11728 usleep_range(1000, 2000);
11731 if (REG_RD(bp, IGU_REG_RESET_MEMORIES)) {
11732 dev_err(&bp->pdev->dev,
11733 "FORCING Normal Mode failed!!!\n");
11734 bnx2x_release_hw_lock(bp,
11735 HW_LOCK_RESOURCE_RESET);
11740 if (val & IGU_BLOCK_CONFIGURATION_REG_BACKWARD_COMP_EN) {
11741 BNX2X_DEV_INFO("IGU Backward Compatible Mode\n");
11742 bp->common.int_block |= INT_BLOCK_MODE_BW_COMP;
11744 BNX2X_DEV_INFO("IGU Normal Mode\n");
11746 rc = bnx2x_get_igu_cam_info(bp);
11747 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_RESET);
11753 * set base FW non-default (fast path) status block id, this value is
11754 * used to initialize the fw_sb_id saved on the fp/queue structure to
11755 * determine the id used by the FW.
11757 if (CHIP_IS_E1x(bp))
11758 bp->base_fw_ndsb = BP_PORT(bp) * FP_SB_MAX_E1x + BP_L_ID(bp);
11760 * 57712 - we currently use one FW SB per IGU SB (Rx and Tx of
11761 * the same queue are indicated on the same IGU SB). So we prefer
11762 * FW and IGU SBs to be the same value.
11764 bp->base_fw_ndsb = bp->igu_base_sb;
11766 BNX2X_DEV_INFO("igu_dsb_id %d igu_base_sb %d igu_sb_cnt %d\n"
11767 "base_fw_ndsb %d\n", bp->igu_dsb_id, bp->igu_base_sb,
11768 bp->igu_sb_cnt, bp->base_fw_ndsb);
11771 * Initialize MF configuration
11776 bp->mf_sub_mode = 0;
11778 mfw_vn = BP_FW_MB_IDX(bp);
11780 if (!CHIP_IS_E1(bp) && !BP_NOMCP(bp)) {
11781 BNX2X_DEV_INFO("shmem2base 0x%x, size %d, mfcfg offset %d\n",
11782 bp->common.shmem2_base, SHMEM2_RD(bp, size),
11783 (u32)offsetof(struct shmem2_region, mf_cfg_addr));
11785 if (SHMEM2_HAS(bp, mf_cfg_addr))
11786 bp->common.mf_cfg_base = SHMEM2_RD(bp, mf_cfg_addr);
11788 bp->common.mf_cfg_base = bp->common.shmem_base +
11789 offsetof(struct shmem_region, func_mb) +
11790 E1H_FUNC_MAX * sizeof(struct drv_func_mb);
11792 * get mf configuration:
11793 * 1. Existence of MF configuration
11794 * 2. MAC address must be legal (check only upper bytes)
11795 * for Switch-Independent mode;
11796 * OVLAN must be legal for Switch-Dependent mode
11797 * 3. SF_MODE configures specific MF mode
11799 if (bp->common.mf_cfg_base != SHMEM_MF_CFG_ADDR_NONE) {
11800 /* get mf configuration */
11802 dev_info.shared_feature_config.config);
11803 val &= SHARED_FEAT_CFG_FORCE_SF_MODE_MASK;
11806 case SHARED_FEAT_CFG_FORCE_SF_MODE_SWITCH_INDEPT:
11807 validate_set_si_mode(bp);
11809 case SHARED_FEAT_CFG_FORCE_SF_MODE_AFEX_MODE:
11810 if ((!CHIP_IS_E1x(bp)) &&
11811 (MF_CFG_RD(bp, func_mf_config[func].
11812 mac_upper) != 0xffff) &&
11814 afex_driver_support))) {
11815 bp->mf_mode = MULTI_FUNCTION_AFEX;
11816 bp->mf_config[vn] = MF_CFG_RD(bp,
11817 func_mf_config[func].config);
11819 BNX2X_DEV_INFO("can not configure afex mode\n");
11822 case SHARED_FEAT_CFG_FORCE_SF_MODE_MF_ALLOWED:
11823 /* get OV configuration */
11824 val = MF_CFG_RD(bp,
11825 func_mf_config[FUNC_0].e1hov_tag);
11826 val &= FUNC_MF_CFG_E1HOV_TAG_MASK;
11828 if (val != FUNC_MF_CFG_E1HOV_TAG_DEFAULT) {
11829 bp->mf_mode = MULTI_FUNCTION_SD;
11830 bp->mf_config[vn] = MF_CFG_RD(bp,
11831 func_mf_config[func].config);
11833 BNX2X_DEV_INFO("illegal OV for SD\n");
11835 case SHARED_FEAT_CFG_FORCE_SF_MODE_BD_MODE:
11836 bp->mf_mode = MULTI_FUNCTION_SD;
11837 bp->mf_sub_mode = SUB_MF_MODE_BD;
11838 bp->mf_config[vn] =
11840 func_mf_config[func].config);
11842 if (SHMEM2_HAS(bp, mtu_size)) {
11843 int mtu_idx = BP_FW_MB_IDX(bp);
11847 mtu = SHMEM2_RD(bp, mtu_size[mtu_idx]);
11848 mtu_size = (u16)mtu;
11849 DP(NETIF_MSG_IFUP, "Read MTU size %04x [%08x]\n",
11852 /* if valid: update device mtu */
11853 if (((mtu_size + ETH_HLEN) >=
11854 ETH_MIN_PACKET_SIZE) &&
11856 ETH_MAX_JUMBO_PACKET_SIZE))
11857 bp->dev->mtu = mtu_size;
11860 case SHARED_FEAT_CFG_FORCE_SF_MODE_UFP_MODE:
11861 bp->mf_mode = MULTI_FUNCTION_SD;
11862 bp->mf_sub_mode = SUB_MF_MODE_UFP;
11863 bp->mf_config[vn] =
11865 func_mf_config[func].config);
11867 case SHARED_FEAT_CFG_FORCE_SF_MODE_FORCED_SF:
11868 bp->mf_config[vn] = 0;
11870 case SHARED_FEAT_CFG_FORCE_SF_MODE_EXTENDED_MODE:
11871 val2 = SHMEM_RD(bp,
11872 dev_info.shared_hw_config.config_3);
11873 val2 &= SHARED_HW_CFG_EXTENDED_MF_MODE_MASK;
11875 case SHARED_HW_CFG_EXTENDED_MF_MODE_NPAR1_DOT_5:
11876 validate_set_si_mode(bp);
11878 SUB_MF_MODE_NPAR1_DOT_5;
11881 /* Unknown configuration */
11882 bp->mf_config[vn] = 0;
11883 BNX2X_DEV_INFO("unknown extended MF mode 0x%x\n",
11888 /* Unknown configuration: reset mf_config */
11889 bp->mf_config[vn] = 0;
11890 BNX2X_DEV_INFO("unknown MF mode 0x%x\n", val);
11894 BNX2X_DEV_INFO("%s function mode\n",
11895 IS_MF(bp) ? "multi" : "single");
11897 switch (bp->mf_mode) {
11898 case MULTI_FUNCTION_SD:
11899 val = MF_CFG_RD(bp, func_mf_config[func].e1hov_tag) &
11900 FUNC_MF_CFG_E1HOV_TAG_MASK;
11901 if (val != FUNC_MF_CFG_E1HOV_TAG_DEFAULT) {
11903 bp->path_has_ovlan = true;
11905 BNX2X_DEV_INFO("MF OV for func %d is %d (0x%04x)\n",
11906 func, bp->mf_ov, bp->mf_ov);
11907 } else if ((bp->mf_sub_mode == SUB_MF_MODE_UFP) ||
11908 (bp->mf_sub_mode == SUB_MF_MODE_BD)) {
11909 dev_err(&bp->pdev->dev,
11910 "Unexpected - no valid MF OV for func %d in UFP/BD mode\n",
11912 bp->path_has_ovlan = true;
11914 dev_err(&bp->pdev->dev,
11915 "No valid MF OV for func %d, aborting\n",
11920 case MULTI_FUNCTION_AFEX:
11921 BNX2X_DEV_INFO("func %d is in MF afex mode\n", func);
11923 case MULTI_FUNCTION_SI:
11924 BNX2X_DEV_INFO("func %d is in MF switch-independent mode\n",
11929 dev_err(&bp->pdev->dev,
11930 "VN %d is in a single function mode, aborting\n",
11937 /* check if other port on the path needs ovlan:
11938 * Since MF configuration is shared between ports
11939 * Possible mixed modes are only
11940 * {SF, SI} {SF, SD} {SD, SF} {SI, SF}
11942 if (CHIP_MODE_IS_4_PORT(bp) &&
11943 !bp->path_has_ovlan &&
11945 bp->common.mf_cfg_base != SHMEM_MF_CFG_ADDR_NONE) {
11946 u8 other_port = !BP_PORT(bp);
11947 u8 other_func = BP_PATH(bp) + 2*other_port;
11948 val = MF_CFG_RD(bp,
11949 func_mf_config[other_func].e1hov_tag);
11950 if (val != FUNC_MF_CFG_E1HOV_TAG_DEFAULT)
11951 bp->path_has_ovlan = true;
11955 /* adjust igu_sb_cnt to MF for E1H */
11956 if (CHIP_IS_E1H(bp) && IS_MF(bp))
11957 bp->igu_sb_cnt = min_t(u8, bp->igu_sb_cnt, E1H_MAX_MF_SB_COUNT);
11960 bnx2x_get_port_hwinfo(bp);
11962 /* Get MAC addresses */
11963 bnx2x_get_mac_hwinfo(bp);
11965 bnx2x_get_cnic_info(bp);
11970 static void bnx2x_read_fwinfo(struct bnx2x *bp)
11972 int cnt, i, block_end, rodi;
11973 char vpd_start[BNX2X_VPD_LEN+1];
11974 char str_id_reg[VENDOR_ID_LEN+1];
11975 char str_id_cap[VENDOR_ID_LEN+1];
11977 char *vpd_extended_data = NULL;
11980 cnt = pci_read_vpd(bp->pdev, 0, BNX2X_VPD_LEN, vpd_start);
11981 memset(bp->fw_ver, 0, sizeof(bp->fw_ver));
11983 if (cnt < BNX2X_VPD_LEN)
11984 goto out_not_found;
11986 /* VPD RO tag should be first tag after identifier string, hence
11987 * we should be able to find it in first BNX2X_VPD_LEN chars
11989 i = pci_vpd_find_tag(vpd_start, 0, BNX2X_VPD_LEN,
11990 PCI_VPD_LRDT_RO_DATA);
11992 goto out_not_found;
11994 block_end = i + PCI_VPD_LRDT_TAG_SIZE +
11995 pci_vpd_lrdt_size(&vpd_start[i]);
11997 i += PCI_VPD_LRDT_TAG_SIZE;
11999 if (block_end > BNX2X_VPD_LEN) {
12000 vpd_extended_data = kmalloc(block_end, GFP_KERNEL);
12001 if (vpd_extended_data == NULL)
12002 goto out_not_found;
12004 /* read rest of vpd image into vpd_extended_data */
12005 memcpy(vpd_extended_data, vpd_start, BNX2X_VPD_LEN);
12006 cnt = pci_read_vpd(bp->pdev, BNX2X_VPD_LEN,
12007 block_end - BNX2X_VPD_LEN,
12008 vpd_extended_data + BNX2X_VPD_LEN);
12009 if (cnt < (block_end - BNX2X_VPD_LEN))
12010 goto out_not_found;
12011 vpd_data = vpd_extended_data;
12013 vpd_data = vpd_start;
12015 /* now vpd_data holds full vpd content in both cases */
12017 rodi = pci_vpd_find_info_keyword(vpd_data, i, block_end,
12018 PCI_VPD_RO_KEYWORD_MFR_ID);
12020 goto out_not_found;
12022 len = pci_vpd_info_field_size(&vpd_data[rodi]);
12024 if (len != VENDOR_ID_LEN)
12025 goto out_not_found;
12027 rodi += PCI_VPD_INFO_FLD_HDR_SIZE;
12029 /* vendor specific info */
12030 snprintf(str_id_reg, VENDOR_ID_LEN + 1, "%04x", PCI_VENDOR_ID_DELL);
12031 snprintf(str_id_cap, VENDOR_ID_LEN + 1, "%04X", PCI_VENDOR_ID_DELL);
12032 if (!strncmp(str_id_reg, &vpd_data[rodi], VENDOR_ID_LEN) ||
12033 !strncmp(str_id_cap, &vpd_data[rodi], VENDOR_ID_LEN)) {
12035 rodi = pci_vpd_find_info_keyword(vpd_data, i, block_end,
12036 PCI_VPD_RO_KEYWORD_VENDOR0);
12038 len = pci_vpd_info_field_size(&vpd_data[rodi]);
12040 rodi += PCI_VPD_INFO_FLD_HDR_SIZE;
12042 if (len < 32 && (len + rodi) <= BNX2X_VPD_LEN) {
12043 memcpy(bp->fw_ver, &vpd_data[rodi], len);
12044 bp->fw_ver[len] = ' ';
12047 kfree(vpd_extended_data);
12051 kfree(vpd_extended_data);
12055 static void bnx2x_set_modes_bitmap(struct bnx2x *bp)
12059 if (CHIP_REV_IS_FPGA(bp))
12060 SET_FLAGS(flags, MODE_FPGA);
12061 else if (CHIP_REV_IS_EMUL(bp))
12062 SET_FLAGS(flags, MODE_EMUL);
12064 SET_FLAGS(flags, MODE_ASIC);
12066 if (CHIP_MODE_IS_4_PORT(bp))
12067 SET_FLAGS(flags, MODE_PORT4);
12069 SET_FLAGS(flags, MODE_PORT2);
12071 if (CHIP_IS_E2(bp))
12072 SET_FLAGS(flags, MODE_E2);
12073 else if (CHIP_IS_E3(bp)) {
12074 SET_FLAGS(flags, MODE_E3);
12075 if (CHIP_REV(bp) == CHIP_REV_Ax)
12076 SET_FLAGS(flags, MODE_E3_A0);
12077 else /*if (CHIP_REV(bp) == CHIP_REV_Bx)*/
12078 SET_FLAGS(flags, MODE_E3_B0 | MODE_COS3);
12082 SET_FLAGS(flags, MODE_MF);
12083 switch (bp->mf_mode) {
12084 case MULTI_FUNCTION_SD:
12085 SET_FLAGS(flags, MODE_MF_SD);
12087 case MULTI_FUNCTION_SI:
12088 SET_FLAGS(flags, MODE_MF_SI);
12090 case MULTI_FUNCTION_AFEX:
12091 SET_FLAGS(flags, MODE_MF_AFEX);
12095 SET_FLAGS(flags, MODE_SF);
12097 #if defined(__LITTLE_ENDIAN)
12098 SET_FLAGS(flags, MODE_LITTLE_ENDIAN);
12099 #else /*(__BIG_ENDIAN)*/
12100 SET_FLAGS(flags, MODE_BIG_ENDIAN);
12102 INIT_MODE_FLAGS(bp) = flags;
12105 static int bnx2x_init_bp(struct bnx2x *bp)
12110 mutex_init(&bp->port.phy_mutex);
12111 mutex_init(&bp->fw_mb_mutex);
12112 mutex_init(&bp->drv_info_mutex);
12113 sema_init(&bp->stats_lock, 1);
12114 bp->drv_info_mng_owner = false;
12116 INIT_DELAYED_WORK(&bp->sp_task, bnx2x_sp_task);
12117 INIT_DELAYED_WORK(&bp->sp_rtnl_task, bnx2x_sp_rtnl_task);
12118 INIT_DELAYED_WORK(&bp->period_task, bnx2x_period_task);
12119 INIT_DELAYED_WORK(&bp->iov_task, bnx2x_iov_task);
12121 rc = bnx2x_get_hwinfo(bp);
12125 eth_zero_addr(bp->dev->dev_addr);
12128 bnx2x_set_modes_bitmap(bp);
12130 rc = bnx2x_alloc_mem_bp(bp);
12134 bnx2x_read_fwinfo(bp);
12136 func = BP_FUNC(bp);
12138 /* need to reset chip if undi was active */
12139 if (IS_PF(bp) && !BP_NOMCP(bp)) {
12142 SHMEM_RD(bp, func_mb[BP_FW_MB_IDX(bp)].drv_mb_header) &
12143 DRV_MSG_SEQ_NUMBER_MASK;
12144 BNX2X_DEV_INFO("fw_seq 0x%08x\n", bp->fw_seq);
12146 rc = bnx2x_prev_unload(bp);
12148 bnx2x_free_mem_bp(bp);
12153 if (CHIP_REV_IS_FPGA(bp))
12154 dev_err(&bp->pdev->dev, "FPGA detected\n");
12156 if (BP_NOMCP(bp) && (func == 0))
12157 dev_err(&bp->pdev->dev, "MCP disabled, must load devices in order!\n");
12159 bp->disable_tpa = disable_tpa;
12160 bp->disable_tpa |= !!IS_MF_STORAGE_ONLY(bp);
12161 /* Reduce memory usage in kdump environment by disabling TPA */
12162 bp->disable_tpa |= is_kdump_kernel();
12164 /* Set TPA flags */
12165 if (bp->disable_tpa) {
12166 bp->dev->hw_features &= ~NETIF_F_LRO;
12167 bp->dev->features &= ~NETIF_F_LRO;
12170 if (CHIP_IS_E1(bp))
12171 bp->dropless_fc = 0;
12173 bp->dropless_fc = dropless_fc | bnx2x_get_dropless_info(bp);
12177 bp->tx_ring_size = IS_MF_STORAGE_ONLY(bp) ? 0 : MAX_TX_AVAIL;
12179 bp->rx_ring_size = MAX_RX_AVAIL;
12181 /* make sure that the numbers are in the right granularity */
12182 bp->tx_ticks = (50 / BNX2X_BTR) * BNX2X_BTR;
12183 bp->rx_ticks = (25 / BNX2X_BTR) * BNX2X_BTR;
12185 bp->current_interval = CHIP_REV_IS_SLOW(bp) ? 5*HZ : HZ;
12187 init_timer(&bp->timer);
12188 bp->timer.expires = jiffies + bp->current_interval;
12189 bp->timer.data = (unsigned long) bp;
12190 bp->timer.function = bnx2x_timer;
12192 if (SHMEM2_HAS(bp, dcbx_lldp_params_offset) &&
12193 SHMEM2_HAS(bp, dcbx_lldp_dcbx_stat_offset) &&
12194 SHMEM2_RD(bp, dcbx_lldp_params_offset) &&
12195 SHMEM2_RD(bp, dcbx_lldp_dcbx_stat_offset)) {
12196 bnx2x_dcbx_set_state(bp, true, BNX2X_DCBX_ENABLED_ON_NEG_ON);
12197 bnx2x_dcbx_init_params(bp);
12199 bnx2x_dcbx_set_state(bp, false, BNX2X_DCBX_ENABLED_OFF);
12202 if (CHIP_IS_E1x(bp))
12203 bp->cnic_base_cl_id = FP_SB_MAX_E1x;
12205 bp->cnic_base_cl_id = FP_SB_MAX_E2;
12207 /* multiple tx priority */
12210 else if (CHIP_IS_E1x(bp))
12211 bp->max_cos = BNX2X_MULTI_TX_COS_E1X;
12212 else if (CHIP_IS_E2(bp) || CHIP_IS_E3A0(bp))
12213 bp->max_cos = BNX2X_MULTI_TX_COS_E2_E3A0;
12214 else if (CHIP_IS_E3B0(bp))
12215 bp->max_cos = BNX2X_MULTI_TX_COS_E3B0;
12217 BNX2X_ERR("unknown chip %x revision %x\n",
12218 CHIP_NUM(bp), CHIP_REV(bp));
12219 BNX2X_DEV_INFO("set bp->max_cos to %d\n", bp->max_cos);
12221 /* We need at least one default status block for slow-path events,
12222 * second status block for the L2 queue, and a third status block for
12223 * CNIC if supported.
12226 bp->min_msix_vec_cnt = 1;
12227 else if (CNIC_SUPPORT(bp))
12228 bp->min_msix_vec_cnt = 3;
12229 else /* PF w/o cnic */
12230 bp->min_msix_vec_cnt = 2;
12231 BNX2X_DEV_INFO("bp->min_msix_vec_cnt %d", bp->min_msix_vec_cnt);
12233 bp->dump_preset_idx = 1;
12235 if (CHIP_IS_E3B0(bp))
12236 bp->flags |= PTP_SUPPORTED;
12241 /****************************************************************************
12242 * General service functions
12243 ****************************************************************************/
12246 * net_device service functions
12249 /* called with rtnl_lock */
12250 static int bnx2x_open(struct net_device *dev)
12252 struct bnx2x *bp = netdev_priv(dev);
12255 bp->stats_init = true;
12257 netif_carrier_off(dev);
12259 bnx2x_set_power_state(bp, PCI_D0);
12261 /* If parity had happen during the unload, then attentions
12262 * and/or RECOVERY_IN_PROGRES may still be set. In this case we
12263 * want the first function loaded on the current engine to
12264 * complete the recovery.
12265 * Parity recovery is only relevant for PF driver.
12268 int other_engine = BP_PATH(bp) ? 0 : 1;
12269 bool other_load_status, load_status;
12270 bool global = false;
12272 other_load_status = bnx2x_get_load_status(bp, other_engine);
12273 load_status = bnx2x_get_load_status(bp, BP_PATH(bp));
12274 if (!bnx2x_reset_is_done(bp, BP_PATH(bp)) ||
12275 bnx2x_chk_parity_attn(bp, &global, true)) {
12277 /* If there are attentions and they are in a
12278 * global blocks, set the GLOBAL_RESET bit
12279 * regardless whether it will be this function
12280 * that will complete the recovery or not.
12283 bnx2x_set_reset_global(bp);
12285 /* Only the first function on the current
12286 * engine should try to recover in open. In case
12287 * of attentions in global blocks only the first
12288 * in the chip should try to recover.
12290 if ((!load_status &&
12291 (!global || !other_load_status)) &&
12292 bnx2x_trylock_leader_lock(bp) &&
12293 !bnx2x_leader_reset(bp)) {
12294 netdev_info(bp->dev,
12295 "Recovered in open\n");
12299 /* recovery has failed... */
12300 bnx2x_set_power_state(bp, PCI_D3hot);
12301 bp->recovery_state = BNX2X_RECOVERY_FAILED;
12303 BNX2X_ERR("Recovery flow hasn't been properly completed yet. Try again later.\n"
12304 "If you still see this message after a few retries then power cycle is required.\n");
12311 bp->recovery_state = BNX2X_RECOVERY_DONE;
12312 rc = bnx2x_nic_load(bp, LOAD_OPEN);
12318 /* called with rtnl_lock */
12319 static int bnx2x_close(struct net_device *dev)
12321 struct bnx2x *bp = netdev_priv(dev);
12323 /* Unload the driver, release IRQs */
12324 bnx2x_nic_unload(bp, UNLOAD_CLOSE, false);
12329 static int bnx2x_init_mcast_macs_list(struct bnx2x *bp,
12330 struct bnx2x_mcast_ramrod_params *p)
12332 int mc_count = netdev_mc_count(bp->dev);
12333 struct bnx2x_mcast_list_elem *mc_mac =
12334 kcalloc(mc_count, sizeof(*mc_mac), GFP_ATOMIC);
12335 struct netdev_hw_addr *ha;
12340 INIT_LIST_HEAD(&p->mcast_list);
12342 netdev_for_each_mc_addr(ha, bp->dev) {
12343 mc_mac->mac = bnx2x_mc_addr(ha);
12344 list_add_tail(&mc_mac->link, &p->mcast_list);
12348 p->mcast_list_len = mc_count;
12353 static void bnx2x_free_mcast_macs_list(
12354 struct bnx2x_mcast_ramrod_params *p)
12356 struct bnx2x_mcast_list_elem *mc_mac =
12357 list_first_entry(&p->mcast_list, struct bnx2x_mcast_list_elem,
12365 * bnx2x_set_uc_list - configure a new unicast MACs list.
12367 * @bp: driver handle
12369 * We will use zero (0) as a MAC type for these MACs.
12371 static int bnx2x_set_uc_list(struct bnx2x *bp)
12374 struct net_device *dev = bp->dev;
12375 struct netdev_hw_addr *ha;
12376 struct bnx2x_vlan_mac_obj *mac_obj = &bp->sp_objs->mac_obj;
12377 unsigned long ramrod_flags = 0;
12379 /* First schedule a cleanup up of old configuration */
12380 rc = bnx2x_del_all_macs(bp, mac_obj, BNX2X_UC_LIST_MAC, false);
12382 BNX2X_ERR("Failed to schedule DELETE operations: %d\n", rc);
12386 netdev_for_each_uc_addr(ha, dev) {
12387 rc = bnx2x_set_mac_one(bp, bnx2x_uc_addr(ha), mac_obj, true,
12388 BNX2X_UC_LIST_MAC, &ramrod_flags);
12389 if (rc == -EEXIST) {
12391 "Failed to schedule ADD operations: %d\n", rc);
12392 /* do not treat adding same MAC as error */
12395 } else if (rc < 0) {
12397 BNX2X_ERR("Failed to schedule ADD operations: %d\n",
12403 /* Execute the pending commands */
12404 __set_bit(RAMROD_CONT, &ramrod_flags);
12405 return bnx2x_set_mac_one(bp, NULL, mac_obj, false /* don't care */,
12406 BNX2X_UC_LIST_MAC, &ramrod_flags);
12409 static int bnx2x_set_mc_list(struct bnx2x *bp)
12411 struct net_device *dev = bp->dev;
12412 struct bnx2x_mcast_ramrod_params rparam = {NULL};
12415 rparam.mcast_obj = &bp->mcast_obj;
12417 /* first, clear all configured multicast MACs */
12418 rc = bnx2x_config_mcast(bp, &rparam, BNX2X_MCAST_CMD_DEL);
12420 BNX2X_ERR("Failed to clear multicast configuration: %d\n", rc);
12424 /* then, configure a new MACs list */
12425 if (netdev_mc_count(dev)) {
12426 rc = bnx2x_init_mcast_macs_list(bp, &rparam);
12428 BNX2X_ERR("Failed to create multicast MACs list: %d\n",
12433 /* Now add the new MACs */
12434 rc = bnx2x_config_mcast(bp, &rparam,
12435 BNX2X_MCAST_CMD_ADD);
12437 BNX2X_ERR("Failed to set a new multicast configuration: %d\n",
12440 bnx2x_free_mcast_macs_list(&rparam);
12446 /* If bp->state is OPEN, should be called with netif_addr_lock_bh() */
12447 static void bnx2x_set_rx_mode(struct net_device *dev)
12449 struct bnx2x *bp = netdev_priv(dev);
12451 if (bp->state != BNX2X_STATE_OPEN) {
12452 DP(NETIF_MSG_IFUP, "state is %x, returning\n", bp->state);
12455 /* Schedule an SP task to handle rest of change */
12456 bnx2x_schedule_sp_rtnl(bp, BNX2X_SP_RTNL_RX_MODE,
12461 void bnx2x_set_rx_mode_inner(struct bnx2x *bp)
12463 u32 rx_mode = BNX2X_RX_MODE_NORMAL;
12465 DP(NETIF_MSG_IFUP, "dev->flags = %x\n", bp->dev->flags);
12467 netif_addr_lock_bh(bp->dev);
12469 if (bp->dev->flags & IFF_PROMISC) {
12470 rx_mode = BNX2X_RX_MODE_PROMISC;
12471 } else if ((bp->dev->flags & IFF_ALLMULTI) ||
12472 ((netdev_mc_count(bp->dev) > BNX2X_MAX_MULTICAST) &&
12474 rx_mode = BNX2X_RX_MODE_ALLMULTI;
12477 /* some multicasts */
12478 if (bnx2x_set_mc_list(bp) < 0)
12479 rx_mode = BNX2X_RX_MODE_ALLMULTI;
12481 /* release bh lock, as bnx2x_set_uc_list might sleep */
12482 netif_addr_unlock_bh(bp->dev);
12483 if (bnx2x_set_uc_list(bp) < 0)
12484 rx_mode = BNX2X_RX_MODE_PROMISC;
12485 netif_addr_lock_bh(bp->dev);
12487 /* configuring mcast to a vf involves sleeping (when we
12488 * wait for the pf's response).
12490 bnx2x_schedule_sp_rtnl(bp,
12491 BNX2X_SP_RTNL_VFPF_MCAST, 0);
12495 bp->rx_mode = rx_mode;
12496 /* handle ISCSI SD mode */
12497 if (IS_MF_ISCSI_ONLY(bp))
12498 bp->rx_mode = BNX2X_RX_MODE_NONE;
12500 /* Schedule the rx_mode command */
12501 if (test_bit(BNX2X_FILTER_RX_MODE_PENDING, &bp->sp_state)) {
12502 set_bit(BNX2X_FILTER_RX_MODE_SCHED, &bp->sp_state);
12503 netif_addr_unlock_bh(bp->dev);
12508 bnx2x_set_storm_rx_mode(bp);
12509 netif_addr_unlock_bh(bp->dev);
12511 /* VF will need to request the PF to make this change, and so
12512 * the VF needs to release the bottom-half lock prior to the
12513 * request (as it will likely require sleep on the VF side)
12515 netif_addr_unlock_bh(bp->dev);
12516 bnx2x_vfpf_storm_rx_mode(bp);
12520 /* called with rtnl_lock */
12521 static int bnx2x_mdio_read(struct net_device *netdev, int prtad,
12522 int devad, u16 addr)
12524 struct bnx2x *bp = netdev_priv(netdev);
12528 DP(NETIF_MSG_LINK, "mdio_read: prtad 0x%x, devad 0x%x, addr 0x%x\n",
12529 prtad, devad, addr);
12531 /* The HW expects different devad if CL22 is used */
12532 devad = (devad == MDIO_DEVAD_NONE) ? DEFAULT_PHY_DEV_ADDR : devad;
12534 bnx2x_acquire_phy_lock(bp);
12535 rc = bnx2x_phy_read(&bp->link_params, prtad, devad, addr, &value);
12536 bnx2x_release_phy_lock(bp);
12537 DP(NETIF_MSG_LINK, "mdio_read_val 0x%x rc = 0x%x\n", value, rc);
12544 /* called with rtnl_lock */
12545 static int bnx2x_mdio_write(struct net_device *netdev, int prtad, int devad,
12546 u16 addr, u16 value)
12548 struct bnx2x *bp = netdev_priv(netdev);
12552 "mdio_write: prtad 0x%x, devad 0x%x, addr 0x%x, value 0x%x\n",
12553 prtad, devad, addr, value);
12555 /* The HW expects different devad if CL22 is used */
12556 devad = (devad == MDIO_DEVAD_NONE) ? DEFAULT_PHY_DEV_ADDR : devad;
12558 bnx2x_acquire_phy_lock(bp);
12559 rc = bnx2x_phy_write(&bp->link_params, prtad, devad, addr, value);
12560 bnx2x_release_phy_lock(bp);
12564 /* called with rtnl_lock */
12565 static int bnx2x_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
12567 struct bnx2x *bp = netdev_priv(dev);
12568 struct mii_ioctl_data *mdio = if_mii(ifr);
12570 if (!netif_running(dev))
12574 case SIOCSHWTSTAMP:
12575 return bnx2x_hwtstamp_ioctl(bp, ifr);
12577 DP(NETIF_MSG_LINK, "ioctl: phy id 0x%x, reg 0x%x, val_in 0x%x\n",
12578 mdio->phy_id, mdio->reg_num, mdio->val_in);
12579 return mdio_mii_ioctl(&bp->mdio, mdio, cmd);
12583 #ifdef CONFIG_NET_POLL_CONTROLLER
12584 static void poll_bnx2x(struct net_device *dev)
12586 struct bnx2x *bp = netdev_priv(dev);
12589 for_each_eth_queue(bp, i) {
12590 struct bnx2x_fastpath *fp = &bp->fp[i];
12591 napi_schedule(&bnx2x_fp(bp, fp->index, napi));
12596 static int bnx2x_validate_addr(struct net_device *dev)
12598 struct bnx2x *bp = netdev_priv(dev);
12600 /* query the bulletin board for mac address configured by the PF */
12602 bnx2x_sample_bulletin(bp);
12604 if (!is_valid_ether_addr(dev->dev_addr)) {
12605 BNX2X_ERR("Non-valid Ethernet address\n");
12606 return -EADDRNOTAVAIL;
12611 static int bnx2x_get_phys_port_id(struct net_device *netdev,
12612 struct netdev_phys_item_id *ppid)
12614 struct bnx2x *bp = netdev_priv(netdev);
12616 if (!(bp->flags & HAS_PHYS_PORT_ID))
12617 return -EOPNOTSUPP;
12619 ppid->id_len = sizeof(bp->phys_port_id);
12620 memcpy(ppid->id, bp->phys_port_id, ppid->id_len);
12625 static netdev_features_t bnx2x_features_check(struct sk_buff *skb,
12626 struct net_device *dev,
12627 netdev_features_t features)
12629 features = vlan_features_check(skb, features);
12630 return vxlan_features_check(skb, features);
12633 static const struct net_device_ops bnx2x_netdev_ops = {
12634 .ndo_open = bnx2x_open,
12635 .ndo_stop = bnx2x_close,
12636 .ndo_start_xmit = bnx2x_start_xmit,
12637 .ndo_select_queue = bnx2x_select_queue,
12638 .ndo_set_rx_mode = bnx2x_set_rx_mode,
12639 .ndo_set_mac_address = bnx2x_change_mac_addr,
12640 .ndo_validate_addr = bnx2x_validate_addr,
12641 .ndo_do_ioctl = bnx2x_ioctl,
12642 .ndo_change_mtu = bnx2x_change_mtu,
12643 .ndo_fix_features = bnx2x_fix_features,
12644 .ndo_set_features = bnx2x_set_features,
12645 .ndo_tx_timeout = bnx2x_tx_timeout,
12646 #ifdef CONFIG_NET_POLL_CONTROLLER
12647 .ndo_poll_controller = poll_bnx2x,
12649 .ndo_setup_tc = bnx2x_setup_tc,
12650 #ifdef CONFIG_BNX2X_SRIOV
12651 .ndo_set_vf_mac = bnx2x_set_vf_mac,
12652 .ndo_set_vf_vlan = bnx2x_set_vf_vlan,
12653 .ndo_get_vf_config = bnx2x_get_vf_config,
12655 #ifdef NETDEV_FCOE_WWNN
12656 .ndo_fcoe_get_wwn = bnx2x_fcoe_get_wwn,
12659 #ifdef CONFIG_NET_RX_BUSY_POLL
12660 .ndo_busy_poll = bnx2x_low_latency_recv,
12662 .ndo_get_phys_port_id = bnx2x_get_phys_port_id,
12663 .ndo_set_vf_link_state = bnx2x_set_vf_link_state,
12664 .ndo_features_check = bnx2x_features_check,
12667 static int bnx2x_set_coherency_mask(struct bnx2x *bp)
12669 struct device *dev = &bp->pdev->dev;
12671 if (dma_set_mask_and_coherent(dev, DMA_BIT_MASK(64)) != 0 &&
12672 dma_set_mask_and_coherent(dev, DMA_BIT_MASK(32)) != 0) {
12673 dev_err(dev, "System does not support DMA, aborting\n");
12680 static void bnx2x_disable_pcie_error_reporting(struct bnx2x *bp)
12682 if (bp->flags & AER_ENABLED) {
12683 pci_disable_pcie_error_reporting(bp->pdev);
12684 bp->flags &= ~AER_ENABLED;
12688 static int bnx2x_init_dev(struct bnx2x *bp, struct pci_dev *pdev,
12689 struct net_device *dev, unsigned long board_type)
12693 bool chip_is_e1x = (board_type == BCM57710 ||
12694 board_type == BCM57711 ||
12695 board_type == BCM57711E);
12697 SET_NETDEV_DEV(dev, &pdev->dev);
12702 rc = pci_enable_device(pdev);
12704 dev_err(&bp->pdev->dev,
12705 "Cannot enable PCI device, aborting\n");
12709 if (!(pci_resource_flags(pdev, 0) & IORESOURCE_MEM)) {
12710 dev_err(&bp->pdev->dev,
12711 "Cannot find PCI device base address, aborting\n");
12713 goto err_out_disable;
12716 if (IS_PF(bp) && !(pci_resource_flags(pdev, 2) & IORESOURCE_MEM)) {
12717 dev_err(&bp->pdev->dev, "Cannot find second PCI device base address, aborting\n");
12719 goto err_out_disable;
12722 pci_read_config_dword(pdev, PCICFG_REVISION_ID_OFFSET, &pci_cfg_dword);
12723 if ((pci_cfg_dword & PCICFG_REVESION_ID_MASK) ==
12724 PCICFG_REVESION_ID_ERROR_VAL) {
12725 pr_err("PCI device error, probably due to fan failure, aborting\n");
12727 goto err_out_disable;
12730 if (atomic_read(&pdev->enable_cnt) == 1) {
12731 rc = pci_request_regions(pdev, DRV_MODULE_NAME);
12733 dev_err(&bp->pdev->dev,
12734 "Cannot obtain PCI resources, aborting\n");
12735 goto err_out_disable;
12738 pci_set_master(pdev);
12739 pci_save_state(pdev);
12743 if (!pdev->pm_cap) {
12744 dev_err(&bp->pdev->dev,
12745 "Cannot find power management capability, aborting\n");
12747 goto err_out_release;
12751 if (!pci_is_pcie(pdev)) {
12752 dev_err(&bp->pdev->dev, "Not PCI Express, aborting\n");
12754 goto err_out_release;
12757 rc = bnx2x_set_coherency_mask(bp);
12759 goto err_out_release;
12761 dev->mem_start = pci_resource_start(pdev, 0);
12762 dev->base_addr = dev->mem_start;
12763 dev->mem_end = pci_resource_end(pdev, 0);
12765 dev->irq = pdev->irq;
12767 bp->regview = pci_ioremap_bar(pdev, 0);
12768 if (!bp->regview) {
12769 dev_err(&bp->pdev->dev,
12770 "Cannot map register space, aborting\n");
12772 goto err_out_release;
12775 /* In E1/E1H use pci device function given by kernel.
12776 * In E2/E3 read physical function from ME register since these chips
12777 * support Physical Device Assignment where kernel BDF maybe arbitrary
12778 * (depending on hypervisor).
12781 bp->pf_num = PCI_FUNC(pdev->devfn);
12784 pci_read_config_dword(bp->pdev,
12785 PCICFG_ME_REGISTER, &pci_cfg_dword);
12786 bp->pf_num = (u8)((pci_cfg_dword & ME_REG_ABS_PF_NUM) >>
12787 ME_REG_ABS_PF_NUM_SHIFT);
12789 BNX2X_DEV_INFO("me reg PF num: %d\n", bp->pf_num);
12791 /* clean indirect addresses */
12792 pci_write_config_dword(bp->pdev, PCICFG_GRC_ADDRESS,
12793 PCICFG_VENDOR_ID_OFFSET);
12795 /* Set PCIe reset type to fundamental for EEH recovery */
12796 pdev->needs_freset = 1;
12798 /* AER (Advanced Error reporting) configuration */
12799 rc = pci_enable_pcie_error_reporting(pdev);
12801 bp->flags |= AER_ENABLED;
12803 BNX2X_DEV_INFO("Failed To configure PCIe AER [%d]\n", rc);
12806 * Clean the following indirect addresses for all functions since it
12807 * is not used by the driver.
12810 REG_WR(bp, PXP2_REG_PGL_ADDR_88_F0, 0);
12811 REG_WR(bp, PXP2_REG_PGL_ADDR_8C_F0, 0);
12812 REG_WR(bp, PXP2_REG_PGL_ADDR_90_F0, 0);
12813 REG_WR(bp, PXP2_REG_PGL_ADDR_94_F0, 0);
12816 REG_WR(bp, PXP2_REG_PGL_ADDR_88_F1, 0);
12817 REG_WR(bp, PXP2_REG_PGL_ADDR_8C_F1, 0);
12818 REG_WR(bp, PXP2_REG_PGL_ADDR_90_F1, 0);
12819 REG_WR(bp, PXP2_REG_PGL_ADDR_94_F1, 0);
12822 /* Enable internal target-read (in case we are probed after PF
12823 * FLR). Must be done prior to any BAR read access. Only for
12828 PGLUE_B_REG_INTERNAL_PFID_ENABLE_TARGET_READ, 1);
12831 dev->watchdog_timeo = TX_TIMEOUT;
12833 dev->netdev_ops = &bnx2x_netdev_ops;
12834 bnx2x_set_ethtool_ops(bp, dev);
12836 dev->priv_flags |= IFF_UNICAST_FLT;
12838 dev->hw_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM |
12839 NETIF_F_TSO | NETIF_F_TSO_ECN | NETIF_F_TSO6 |
12840 NETIF_F_RXCSUM | NETIF_F_LRO | NETIF_F_GRO |
12841 NETIF_F_RXHASH | NETIF_F_HW_VLAN_CTAG_TX;
12842 if (!chip_is_e1x) {
12843 dev->hw_features |= NETIF_F_GSO_GRE | NETIF_F_GSO_UDP_TUNNEL |
12844 NETIF_F_GSO_IPIP | NETIF_F_GSO_SIT;
12845 dev->hw_enc_features =
12846 NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM | NETIF_F_SG |
12847 NETIF_F_TSO | NETIF_F_TSO_ECN | NETIF_F_TSO6 |
12850 NETIF_F_GSO_GRE | NETIF_F_GSO_UDP_TUNNEL;
12853 dev->vlan_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM |
12854 NETIF_F_TSO | NETIF_F_TSO_ECN | NETIF_F_TSO6 | NETIF_F_HIGHDMA;
12856 dev->features |= dev->hw_features | NETIF_F_HW_VLAN_CTAG_RX;
12857 dev->features |= NETIF_F_HIGHDMA;
12859 /* Add Loopback capability to the device */
12860 dev->hw_features |= NETIF_F_LOOPBACK;
12863 dev->dcbnl_ops = &bnx2x_dcbnl_ops;
12866 /* get_port_hwinfo() will set prtad and mmds properly */
12867 bp->mdio.prtad = MDIO_PRTAD_NONE;
12869 bp->mdio.mode_support = MDIO_SUPPORTS_C45 | MDIO_EMULATE_C22;
12870 bp->mdio.dev = dev;
12871 bp->mdio.mdio_read = bnx2x_mdio_read;
12872 bp->mdio.mdio_write = bnx2x_mdio_write;
12877 if (atomic_read(&pdev->enable_cnt) == 1)
12878 pci_release_regions(pdev);
12881 pci_disable_device(pdev);
12887 static int bnx2x_check_firmware(struct bnx2x *bp)
12889 const struct firmware *firmware = bp->firmware;
12890 struct bnx2x_fw_file_hdr *fw_hdr;
12891 struct bnx2x_fw_file_section *sections;
12892 u32 offset, len, num_ops;
12893 __be16 *ops_offsets;
12897 if (firmware->size < sizeof(struct bnx2x_fw_file_hdr)) {
12898 BNX2X_ERR("Wrong FW size\n");
12902 fw_hdr = (struct bnx2x_fw_file_hdr *)firmware->data;
12903 sections = (struct bnx2x_fw_file_section *)fw_hdr;
12905 /* Make sure none of the offsets and sizes make us read beyond
12906 * the end of the firmware data */
12907 for (i = 0; i < sizeof(*fw_hdr) / sizeof(*sections); i++) {
12908 offset = be32_to_cpu(sections[i].offset);
12909 len = be32_to_cpu(sections[i].len);
12910 if (offset + len > firmware->size) {
12911 BNX2X_ERR("Section %d length is out of bounds\n", i);
12916 /* Likewise for the init_ops offsets */
12917 offset = be32_to_cpu(fw_hdr->init_ops_offsets.offset);
12918 ops_offsets = (__force __be16 *)(firmware->data + offset);
12919 num_ops = be32_to_cpu(fw_hdr->init_ops.len) / sizeof(struct raw_op);
12921 for (i = 0; i < be32_to_cpu(fw_hdr->init_ops_offsets.len) / 2; i++) {
12922 if (be16_to_cpu(ops_offsets[i]) > num_ops) {
12923 BNX2X_ERR("Section offset %d is out of bounds\n", i);
12928 /* Check FW version */
12929 offset = be32_to_cpu(fw_hdr->fw_version.offset);
12930 fw_ver = firmware->data + offset;
12931 if ((fw_ver[0] != BCM_5710_FW_MAJOR_VERSION) ||
12932 (fw_ver[1] != BCM_5710_FW_MINOR_VERSION) ||
12933 (fw_ver[2] != BCM_5710_FW_REVISION_VERSION) ||
12934 (fw_ver[3] != BCM_5710_FW_ENGINEERING_VERSION)) {
12935 BNX2X_ERR("Bad FW version:%d.%d.%d.%d. Should be %d.%d.%d.%d\n",
12936 fw_ver[0], fw_ver[1], fw_ver[2], fw_ver[3],
12937 BCM_5710_FW_MAJOR_VERSION,
12938 BCM_5710_FW_MINOR_VERSION,
12939 BCM_5710_FW_REVISION_VERSION,
12940 BCM_5710_FW_ENGINEERING_VERSION);
12947 static void be32_to_cpu_n(const u8 *_source, u8 *_target, u32 n)
12949 const __be32 *source = (const __be32 *)_source;
12950 u32 *target = (u32 *)_target;
12953 for (i = 0; i < n/4; i++)
12954 target[i] = be32_to_cpu(source[i]);
12958 Ops array is stored in the following format:
12959 {op(8bit), offset(24bit, big endian), data(32bit, big endian)}
12961 static void bnx2x_prep_ops(const u8 *_source, u8 *_target, u32 n)
12963 const __be32 *source = (const __be32 *)_source;
12964 struct raw_op *target = (struct raw_op *)_target;
12967 for (i = 0, j = 0; i < n/8; i++, j += 2) {
12968 tmp = be32_to_cpu(source[j]);
12969 target[i].op = (tmp >> 24) & 0xff;
12970 target[i].offset = tmp & 0xffffff;
12971 target[i].raw_data = be32_to_cpu(source[j + 1]);
12975 /* IRO array is stored in the following format:
12976 * {base(24bit), m1(16bit), m2(16bit), m3(16bit), size(16bit) }
12978 static void bnx2x_prep_iro(const u8 *_source, u8 *_target, u32 n)
12980 const __be32 *source = (const __be32 *)_source;
12981 struct iro *target = (struct iro *)_target;
12984 for (i = 0, j = 0; i < n/sizeof(struct iro); i++) {
12985 target[i].base = be32_to_cpu(source[j]);
12987 tmp = be32_to_cpu(source[j]);
12988 target[i].m1 = (tmp >> 16) & 0xffff;
12989 target[i].m2 = tmp & 0xffff;
12991 tmp = be32_to_cpu(source[j]);
12992 target[i].m3 = (tmp >> 16) & 0xffff;
12993 target[i].size = tmp & 0xffff;
12998 static void be16_to_cpu_n(const u8 *_source, u8 *_target, u32 n)
13000 const __be16 *source = (const __be16 *)_source;
13001 u16 *target = (u16 *)_target;
13004 for (i = 0; i < n/2; i++)
13005 target[i] = be16_to_cpu(source[i]);
13008 #define BNX2X_ALLOC_AND_SET(arr, lbl, func) \
13010 u32 len = be32_to_cpu(fw_hdr->arr.len); \
13011 bp->arr = kmalloc(len, GFP_KERNEL); \
13014 func(bp->firmware->data + be32_to_cpu(fw_hdr->arr.offset), \
13015 (u8 *)bp->arr, len); \
13018 static int bnx2x_init_firmware(struct bnx2x *bp)
13020 const char *fw_file_name;
13021 struct bnx2x_fw_file_hdr *fw_hdr;
13027 if (CHIP_IS_E1(bp))
13028 fw_file_name = FW_FILE_NAME_E1;
13029 else if (CHIP_IS_E1H(bp))
13030 fw_file_name = FW_FILE_NAME_E1H;
13031 else if (!CHIP_IS_E1x(bp))
13032 fw_file_name = FW_FILE_NAME_E2;
13034 BNX2X_ERR("Unsupported chip revision\n");
13037 BNX2X_DEV_INFO("Loading %s\n", fw_file_name);
13039 rc = request_firmware(&bp->firmware, fw_file_name, &bp->pdev->dev);
13041 BNX2X_ERR("Can't load firmware file %s\n",
13043 goto request_firmware_exit;
13046 rc = bnx2x_check_firmware(bp);
13048 BNX2X_ERR("Corrupt firmware file %s\n", fw_file_name);
13049 goto request_firmware_exit;
13052 fw_hdr = (struct bnx2x_fw_file_hdr *)bp->firmware->data;
13054 /* Initialize the pointers to the init arrays */
13056 BNX2X_ALLOC_AND_SET(init_data, request_firmware_exit, be32_to_cpu_n);
13059 BNX2X_ALLOC_AND_SET(init_ops, init_ops_alloc_err, bnx2x_prep_ops);
13062 BNX2X_ALLOC_AND_SET(init_ops_offsets, init_offsets_alloc_err,
13065 /* STORMs firmware */
13066 INIT_TSEM_INT_TABLE_DATA(bp) = bp->firmware->data +
13067 be32_to_cpu(fw_hdr->tsem_int_table_data.offset);
13068 INIT_TSEM_PRAM_DATA(bp) = bp->firmware->data +
13069 be32_to_cpu(fw_hdr->tsem_pram_data.offset);
13070 INIT_USEM_INT_TABLE_DATA(bp) = bp->firmware->data +
13071 be32_to_cpu(fw_hdr->usem_int_table_data.offset);
13072 INIT_USEM_PRAM_DATA(bp) = bp->firmware->data +
13073 be32_to_cpu(fw_hdr->usem_pram_data.offset);
13074 INIT_XSEM_INT_TABLE_DATA(bp) = bp->firmware->data +
13075 be32_to_cpu(fw_hdr->xsem_int_table_data.offset);
13076 INIT_XSEM_PRAM_DATA(bp) = bp->firmware->data +
13077 be32_to_cpu(fw_hdr->xsem_pram_data.offset);
13078 INIT_CSEM_INT_TABLE_DATA(bp) = bp->firmware->data +
13079 be32_to_cpu(fw_hdr->csem_int_table_data.offset);
13080 INIT_CSEM_PRAM_DATA(bp) = bp->firmware->data +
13081 be32_to_cpu(fw_hdr->csem_pram_data.offset);
13083 BNX2X_ALLOC_AND_SET(iro_arr, iro_alloc_err, bnx2x_prep_iro);
13088 kfree(bp->init_ops_offsets);
13089 init_offsets_alloc_err:
13090 kfree(bp->init_ops);
13091 init_ops_alloc_err:
13092 kfree(bp->init_data);
13093 request_firmware_exit:
13094 release_firmware(bp->firmware);
13095 bp->firmware = NULL;
13100 static void bnx2x_release_firmware(struct bnx2x *bp)
13102 kfree(bp->init_ops_offsets);
13103 kfree(bp->init_ops);
13104 kfree(bp->init_data);
13105 release_firmware(bp->firmware);
13106 bp->firmware = NULL;
13109 static struct bnx2x_func_sp_drv_ops bnx2x_func_sp_drv = {
13110 .init_hw_cmn_chip = bnx2x_init_hw_common_chip,
13111 .init_hw_cmn = bnx2x_init_hw_common,
13112 .init_hw_port = bnx2x_init_hw_port,
13113 .init_hw_func = bnx2x_init_hw_func,
13115 .reset_hw_cmn = bnx2x_reset_common,
13116 .reset_hw_port = bnx2x_reset_port,
13117 .reset_hw_func = bnx2x_reset_func,
13119 .gunzip_init = bnx2x_gunzip_init,
13120 .gunzip_end = bnx2x_gunzip_end,
13122 .init_fw = bnx2x_init_firmware,
13123 .release_fw = bnx2x_release_firmware,
13126 void bnx2x__init_func_obj(struct bnx2x *bp)
13128 /* Prepare DMAE related driver resources */
13129 bnx2x_setup_dmae(bp);
13131 bnx2x_init_func_obj(bp, &bp->func_obj,
13132 bnx2x_sp(bp, func_rdata),
13133 bnx2x_sp_mapping(bp, func_rdata),
13134 bnx2x_sp(bp, func_afex_rdata),
13135 bnx2x_sp_mapping(bp, func_afex_rdata),
13136 &bnx2x_func_sp_drv);
13139 /* must be called after sriov-enable */
13140 static int bnx2x_set_qm_cid_count(struct bnx2x *bp)
13142 int cid_count = BNX2X_L2_MAX_CID(bp);
13145 cid_count += BNX2X_VF_CIDS;
13147 if (CNIC_SUPPORT(bp))
13148 cid_count += CNIC_CID_MAX;
13150 return roundup(cid_count, QM_CID_ROUND);
13154 * bnx2x_get_num_none_def_sbs - return the number of none default SBs
13159 static int bnx2x_get_num_non_def_sbs(struct pci_dev *pdev, int cnic_cnt)
13165 * If MSI-X is not supported - return number of SBs needed to support
13166 * one fast path queue: one FP queue + SB for CNIC
13168 if (!pdev->msix_cap) {
13169 dev_info(&pdev->dev, "no msix capability found\n");
13170 return 1 + cnic_cnt;
13172 dev_info(&pdev->dev, "msix capability found\n");
13175 * The value in the PCI configuration space is the index of the last
13176 * entry, namely one less than the actual size of the table, which is
13177 * exactly what we want to return from this function: number of all SBs
13178 * without the default SB.
13179 * For VFs there is no default SB, then we return (index+1).
13181 pci_read_config_word(pdev, pdev->msix_cap + PCI_MSIX_FLAGS, &control);
13183 index = control & PCI_MSIX_FLAGS_QSIZE;
13188 static int set_max_cos_est(int chip_id)
13194 return BNX2X_MULTI_TX_COS_E1X;
13197 return BNX2X_MULTI_TX_COS_E2_E3A0;
13202 case BCM57840_4_10:
13203 case BCM57840_2_20:
13209 return BNX2X_MULTI_TX_COS_E3B0;
13217 pr_err("Unknown board_type (%d), aborting\n", chip_id);
13222 static int set_is_vf(int chip_id)
13236 /* nig_tsgen registers relative address */
13237 #define tsgen_ctrl 0x0
13238 #define tsgen_freecount 0x10
13239 #define tsgen_synctime_t0 0x20
13240 #define tsgen_offset_t0 0x28
13241 #define tsgen_drift_t0 0x30
13242 #define tsgen_synctime_t1 0x58
13243 #define tsgen_offset_t1 0x60
13244 #define tsgen_drift_t1 0x68
13246 /* FW workaround for setting drift */
13247 static int bnx2x_send_update_drift_ramrod(struct bnx2x *bp, int drift_dir,
13248 int best_val, int best_period)
13250 struct bnx2x_func_state_params func_params = {NULL};
13251 struct bnx2x_func_set_timesync_params *set_timesync_params =
13252 &func_params.params.set_timesync;
13254 /* Prepare parameters for function state transitions */
13255 __set_bit(RAMROD_COMP_WAIT, &func_params.ramrod_flags);
13256 __set_bit(RAMROD_RETRY, &func_params.ramrod_flags);
13258 func_params.f_obj = &bp->func_obj;
13259 func_params.cmd = BNX2X_F_CMD_SET_TIMESYNC;
13261 /* Function parameters */
13262 set_timesync_params->drift_adjust_cmd = TS_DRIFT_ADJUST_SET;
13263 set_timesync_params->offset_cmd = TS_OFFSET_KEEP;
13264 set_timesync_params->add_sub_drift_adjust_value =
13265 drift_dir ? TS_ADD_VALUE : TS_SUB_VALUE;
13266 set_timesync_params->drift_adjust_value = best_val;
13267 set_timesync_params->drift_adjust_period = best_period;
13269 return bnx2x_func_state_change(bp, &func_params);
13272 static int bnx2x_ptp_adjfreq(struct ptp_clock_info *ptp, s32 ppb)
13274 struct bnx2x *bp = container_of(ptp, struct bnx2x, ptp_clock_info);
13277 int val, period, period1, period2, dif, dif1, dif2;
13278 int best_dif = BNX2X_MAX_PHC_DRIFT, best_period = 0, best_val = 0;
13280 DP(BNX2X_MSG_PTP, "PTP adjfreq called, ppb = %d\n", ppb);
13282 if (!netif_running(bp->dev)) {
13284 "PTP adjfreq called while the interface is down\n");
13295 best_period = 0x1FFFFFF;
13296 } else if (ppb >= BNX2X_MAX_PHC_DRIFT) {
13300 /* Changed not to allow val = 8, 16, 24 as these values
13301 * are not supported in workaround.
13303 for (val = 0; val <= 31; val++) {
13304 if ((val & 0x7) == 0)
13306 period1 = val * 1000000 / ppb;
13307 period2 = period1 + 1;
13309 dif1 = ppb - (val * 1000000 / period1);
13311 dif1 = BNX2X_MAX_PHC_DRIFT;
13314 dif2 = ppb - (val * 1000000 / period2);
13317 dif = (dif1 < dif2) ? dif1 : dif2;
13318 period = (dif1 < dif2) ? period1 : period2;
13319 if (dif < best_dif) {
13322 best_period = period;
13327 rc = bnx2x_send_update_drift_ramrod(bp, drift_dir, best_val,
13330 BNX2X_ERR("Failed to set drift\n");
13334 DP(BNX2X_MSG_PTP, "Configured val = %d, period = %d\n", best_val,
13340 static int bnx2x_ptp_adjtime(struct ptp_clock_info *ptp, s64 delta)
13342 struct bnx2x *bp = container_of(ptp, struct bnx2x, ptp_clock_info);
13344 DP(BNX2X_MSG_PTP, "PTP adjtime called, delta = %llx\n", delta);
13346 timecounter_adjtime(&bp->timecounter, delta);
13351 static int bnx2x_ptp_gettime(struct ptp_clock_info *ptp, struct timespec64 *ts)
13353 struct bnx2x *bp = container_of(ptp, struct bnx2x, ptp_clock_info);
13356 ns = timecounter_read(&bp->timecounter);
13358 DP(BNX2X_MSG_PTP, "PTP gettime called, ns = %llu\n", ns);
13360 *ts = ns_to_timespec64(ns);
13365 static int bnx2x_ptp_settime(struct ptp_clock_info *ptp,
13366 const struct timespec64 *ts)
13368 struct bnx2x *bp = container_of(ptp, struct bnx2x, ptp_clock_info);
13371 ns = timespec64_to_ns(ts);
13373 DP(BNX2X_MSG_PTP, "PTP settime called, ns = %llu\n", ns);
13375 /* Re-init the timecounter */
13376 timecounter_init(&bp->timecounter, &bp->cyclecounter, ns);
13381 /* Enable (or disable) ancillary features of the phc subsystem */
13382 static int bnx2x_ptp_enable(struct ptp_clock_info *ptp,
13383 struct ptp_clock_request *rq, int on)
13385 struct bnx2x *bp = container_of(ptp, struct bnx2x, ptp_clock_info);
13387 BNX2X_ERR("PHC ancillary features are not supported\n");
13391 static void bnx2x_register_phc(struct bnx2x *bp)
13393 /* Fill the ptp_clock_info struct and register PTP clock*/
13394 bp->ptp_clock_info.owner = THIS_MODULE;
13395 snprintf(bp->ptp_clock_info.name, 16, "%s", bp->dev->name);
13396 bp->ptp_clock_info.max_adj = BNX2X_MAX_PHC_DRIFT; /* In PPB */
13397 bp->ptp_clock_info.n_alarm = 0;
13398 bp->ptp_clock_info.n_ext_ts = 0;
13399 bp->ptp_clock_info.n_per_out = 0;
13400 bp->ptp_clock_info.pps = 0;
13401 bp->ptp_clock_info.adjfreq = bnx2x_ptp_adjfreq;
13402 bp->ptp_clock_info.adjtime = bnx2x_ptp_adjtime;
13403 bp->ptp_clock_info.gettime64 = bnx2x_ptp_gettime;
13404 bp->ptp_clock_info.settime64 = bnx2x_ptp_settime;
13405 bp->ptp_clock_info.enable = bnx2x_ptp_enable;
13407 bp->ptp_clock = ptp_clock_register(&bp->ptp_clock_info, &bp->pdev->dev);
13408 if (IS_ERR(bp->ptp_clock)) {
13409 bp->ptp_clock = NULL;
13410 BNX2X_ERR("PTP clock registeration failed\n");
13414 static int bnx2x_init_one(struct pci_dev *pdev,
13415 const struct pci_device_id *ent)
13417 struct net_device *dev = NULL;
13419 enum pcie_link_width pcie_width;
13420 enum pci_bus_speed pcie_speed;
13421 int rc, max_non_def_sbs;
13422 int rx_count, tx_count, rss_count, doorbell_size;
13427 /* Management FW 'remembers' living interfaces. Allow it some time
13428 * to forget previously living interfaces, allowing a proper re-load.
13430 if (is_kdump_kernel()) {
13431 ktime_t now = ktime_get_boottime();
13432 ktime_t fw_ready_time = ktime_set(5, 0);
13434 if (ktime_before(now, fw_ready_time))
13435 msleep(ktime_ms_delta(fw_ready_time, now));
13438 /* An estimated maximum supported CoS number according to the chip
13440 * We will try to roughly estimate the maximum number of CoSes this chip
13441 * may support in order to minimize the memory allocated for Tx
13442 * netdev_queue's. This number will be accurately calculated during the
13443 * initialization of bp->max_cos based on the chip versions AND chip
13444 * revision in the bnx2x_init_bp().
13446 max_cos_est = set_max_cos_est(ent->driver_data);
13447 if (max_cos_est < 0)
13448 return max_cos_est;
13449 is_vf = set_is_vf(ent->driver_data);
13450 cnic_cnt = is_vf ? 0 : 1;
13452 max_non_def_sbs = bnx2x_get_num_non_def_sbs(pdev, cnic_cnt);
13454 /* add another SB for VF as it has no default SB */
13455 max_non_def_sbs += is_vf ? 1 : 0;
13457 /* Maximum number of RSS queues: one IGU SB goes to CNIC */
13458 rss_count = max_non_def_sbs - cnic_cnt;
13463 /* Maximum number of netdev Rx queues: RSS + FCoE L2 */
13464 rx_count = rss_count + cnic_cnt;
13466 /* Maximum number of netdev Tx queues:
13467 * Maximum TSS queues * Maximum supported number of CoS + FCoE L2
13469 tx_count = rss_count * max_cos_est + cnic_cnt;
13471 /* dev zeroed in init_etherdev */
13472 dev = alloc_etherdev_mqs(sizeof(*bp), tx_count, rx_count);
13476 bp = netdev_priv(dev);
13480 bp->flags |= IS_VF_FLAG;
13482 bp->igu_sb_cnt = max_non_def_sbs;
13483 bp->igu_base_addr = IS_VF(bp) ? PXP_VF_ADDR_IGU_START : BAR_IGU_INTMEM;
13484 bp->msg_enable = debug;
13485 bp->cnic_support = cnic_cnt;
13486 bp->cnic_probe = bnx2x_cnic_probe;
13488 pci_set_drvdata(pdev, dev);
13490 rc = bnx2x_init_dev(bp, pdev, dev, ent->driver_data);
13496 BNX2X_DEV_INFO("This is a %s function\n",
13497 IS_PF(bp) ? "physical" : "virtual");
13498 BNX2X_DEV_INFO("Cnic support is %s\n", CNIC_SUPPORT(bp) ? "on" : "off");
13499 BNX2X_DEV_INFO("Max num of status blocks %d\n", max_non_def_sbs);
13500 BNX2X_DEV_INFO("Allocated netdev with %d tx and %d rx queues\n",
13501 tx_count, rx_count);
13503 rc = bnx2x_init_bp(bp);
13505 goto init_one_exit;
13507 /* Map doorbells here as we need the real value of bp->max_cos which
13508 * is initialized in bnx2x_init_bp() to determine the number of
13512 bp->doorbells = bnx2x_vf_doorbells(bp);
13513 rc = bnx2x_vf_pci_alloc(bp);
13515 goto init_one_exit;
13517 doorbell_size = BNX2X_L2_MAX_CID(bp) * (1 << BNX2X_DB_SHIFT);
13518 if (doorbell_size > pci_resource_len(pdev, 2)) {
13519 dev_err(&bp->pdev->dev,
13520 "Cannot map doorbells, bar size too small, aborting\n");
13522 goto init_one_exit;
13524 bp->doorbells = ioremap_nocache(pci_resource_start(pdev, 2),
13527 if (!bp->doorbells) {
13528 dev_err(&bp->pdev->dev,
13529 "Cannot map doorbell space, aborting\n");
13531 goto init_one_exit;
13535 rc = bnx2x_vfpf_acquire(bp, tx_count, rx_count);
13537 goto init_one_exit;
13540 /* Enable SRIOV if capability found in configuration space */
13541 rc = bnx2x_iov_init_one(bp, int_mode, BNX2X_MAX_NUM_OF_VFS);
13543 goto init_one_exit;
13545 /* calc qm_cid_count */
13546 bp->qm_cid_count = bnx2x_set_qm_cid_count(bp);
13547 BNX2X_DEV_INFO("qm_cid_count %d\n", bp->qm_cid_count);
13549 /* disable FCOE L2 queue for E1x*/
13550 if (CHIP_IS_E1x(bp))
13551 bp->flags |= NO_FCOE_FLAG;
13553 /* Set bp->num_queues for MSI-X mode*/
13554 bnx2x_set_num_queues(bp);
13556 /* Configure interrupt mode: try to enable MSI-X/MSI if
13559 rc = bnx2x_set_int_mode(bp);
13561 dev_err(&pdev->dev, "Cannot set interrupts\n");
13562 goto init_one_exit;
13564 BNX2X_DEV_INFO("set interrupts successfully\n");
13566 /* register the net device */
13567 rc = register_netdev(dev);
13569 dev_err(&pdev->dev, "Cannot register net device\n");
13570 goto init_one_exit;
13572 BNX2X_DEV_INFO("device name after netdev register %s\n", dev->name);
13574 if (!NO_FCOE(bp)) {
13575 /* Add storage MAC address */
13577 dev_addr_add(bp->dev, bp->fip_mac, NETDEV_HW_ADDR_T_SAN);
13580 if (pcie_get_minimum_link(bp->pdev, &pcie_speed, &pcie_width) ||
13581 pcie_speed == PCI_SPEED_UNKNOWN ||
13582 pcie_width == PCIE_LNK_WIDTH_UNKNOWN)
13583 BNX2X_DEV_INFO("Failed to determine PCI Express Bandwidth\n");
13586 "%s (%c%d) PCI-E x%d %s found at mem %lx, IRQ %d, node addr %pM\n",
13587 board_info[ent->driver_data].name,
13588 (CHIP_REV(bp) >> 12) + 'A', (CHIP_METAL(bp) >> 4),
13590 pcie_speed == PCIE_SPEED_2_5GT ? "2.5GHz" :
13591 pcie_speed == PCIE_SPEED_5_0GT ? "5.0GHz" :
13592 pcie_speed == PCIE_SPEED_8_0GT ? "8.0GHz" :
13594 dev->base_addr, bp->pdev->irq, dev->dev_addr);
13596 bnx2x_register_phc(bp);
13598 if (!IS_MF_SD_STORAGE_PERSONALITY_ONLY(bp))
13599 bnx2x_set_os_driver_state(bp, OS_DRIVER_STATE_DISABLED);
13604 bnx2x_disable_pcie_error_reporting(bp);
13607 iounmap(bp->regview);
13609 if (IS_PF(bp) && bp->doorbells)
13610 iounmap(bp->doorbells);
13614 if (atomic_read(&pdev->enable_cnt) == 1)
13615 pci_release_regions(pdev);
13617 pci_disable_device(pdev);
13622 static void __bnx2x_remove(struct pci_dev *pdev,
13623 struct net_device *dev,
13625 bool remove_netdev)
13627 if (bp->ptp_clock) {
13628 ptp_clock_unregister(bp->ptp_clock);
13629 bp->ptp_clock = NULL;
13632 /* Delete storage MAC address */
13633 if (!NO_FCOE(bp)) {
13635 dev_addr_del(bp->dev, bp->fip_mac, NETDEV_HW_ADDR_T_SAN);
13640 /* Delete app tlvs from dcbnl */
13641 bnx2x_dcbnl_update_applist(bp, true);
13646 (bp->flags & BC_SUPPORTS_RMMOD_CMD))
13647 bnx2x_fw_command(bp, DRV_MSG_CODE_RMMOD, 0);
13649 /* Close the interface - either directly or implicitly */
13650 if (remove_netdev) {
13651 unregister_netdev(dev);
13658 bnx2x_iov_remove_one(bp);
13660 /* Power on: we can't let PCI layer write to us while we are in D3 */
13662 bnx2x_set_power_state(bp, PCI_D0);
13663 bnx2x_set_os_driver_state(bp, OS_DRIVER_STATE_NOT_LOADED);
13665 /* Set endianity registers to reset values in case next driver
13666 * boots in different endianty environment.
13668 bnx2x_reset_endianity(bp);
13671 /* Disable MSI/MSI-X */
13672 bnx2x_disable_msi(bp);
13676 bnx2x_set_power_state(bp, PCI_D3hot);
13678 /* Make sure RESET task is not scheduled before continuing */
13679 cancel_delayed_work_sync(&bp->sp_rtnl_task);
13681 /* send message via vfpf channel to release the resources of this vf */
13683 bnx2x_vfpf_release(bp);
13685 /* Assumes no further PCIe PM changes will occur */
13686 if (system_state == SYSTEM_POWER_OFF) {
13687 pci_wake_from_d3(pdev, bp->wol);
13688 pci_set_power_state(pdev, PCI_D3hot);
13691 bnx2x_disable_pcie_error_reporting(bp);
13692 if (remove_netdev) {
13694 iounmap(bp->regview);
13696 /* For vfs, doorbells are part of the regview and were unmapped
13697 * along with it. FW is only loaded by PF.
13701 iounmap(bp->doorbells);
13703 bnx2x_release_firmware(bp);
13705 bnx2x_vf_pci_dealloc(bp);
13707 bnx2x_free_mem_bp(bp);
13711 if (atomic_read(&pdev->enable_cnt) == 1)
13712 pci_release_regions(pdev);
13714 pci_disable_device(pdev);
13718 static void bnx2x_remove_one(struct pci_dev *pdev)
13720 struct net_device *dev = pci_get_drvdata(pdev);
13724 dev_err(&pdev->dev, "BAD net device from bnx2x_init_one\n");
13727 bp = netdev_priv(dev);
13729 __bnx2x_remove(pdev, dev, bp, true);
13732 static int bnx2x_eeh_nic_unload(struct bnx2x *bp)
13734 bp->state = BNX2X_STATE_CLOSING_WAIT4_HALT;
13736 bp->rx_mode = BNX2X_RX_MODE_NONE;
13738 if (CNIC_LOADED(bp))
13739 bnx2x_cnic_notify(bp, CNIC_CTL_STOP_CMD);
13742 bnx2x_tx_disable(bp);
13743 /* Delete all NAPI objects */
13744 bnx2x_del_all_napi(bp);
13745 if (CNIC_LOADED(bp))
13746 bnx2x_del_all_napi_cnic(bp);
13747 netdev_reset_tc(bp->dev);
13749 del_timer_sync(&bp->timer);
13750 cancel_delayed_work_sync(&bp->sp_task);
13751 cancel_delayed_work_sync(&bp->period_task);
13753 if (!down_timeout(&bp->stats_lock, HZ / 10)) {
13754 bp->stats_state = STATS_STATE_DISABLED;
13755 up(&bp->stats_lock);
13758 bnx2x_save_statistics(bp);
13760 netif_carrier_off(bp->dev);
13766 * bnx2x_io_error_detected - called when PCI error is detected
13767 * @pdev: Pointer to PCI device
13768 * @state: The current pci connection state
13770 * This function is called after a PCI bus error affecting
13771 * this device has been detected.
13773 static pci_ers_result_t bnx2x_io_error_detected(struct pci_dev *pdev,
13774 pci_channel_state_t state)
13776 struct net_device *dev = pci_get_drvdata(pdev);
13777 struct bnx2x *bp = netdev_priv(dev);
13781 BNX2X_ERR("IO error detected\n");
13783 netif_device_detach(dev);
13785 if (state == pci_channel_io_perm_failure) {
13787 return PCI_ERS_RESULT_DISCONNECT;
13790 if (netif_running(dev))
13791 bnx2x_eeh_nic_unload(bp);
13793 bnx2x_prev_path_mark_eeh(bp);
13795 pci_disable_device(pdev);
13799 /* Request a slot reset */
13800 return PCI_ERS_RESULT_NEED_RESET;
13804 * bnx2x_io_slot_reset - called after the PCI bus has been reset
13805 * @pdev: Pointer to PCI device
13807 * Restart the card from scratch, as if from a cold-boot.
13809 static pci_ers_result_t bnx2x_io_slot_reset(struct pci_dev *pdev)
13811 struct net_device *dev = pci_get_drvdata(pdev);
13812 struct bnx2x *bp = netdev_priv(dev);
13816 BNX2X_ERR("IO slot reset initializing...\n");
13817 if (pci_enable_device(pdev)) {
13818 dev_err(&pdev->dev,
13819 "Cannot re-enable PCI device after reset\n");
13821 return PCI_ERS_RESULT_DISCONNECT;
13824 pci_set_master(pdev);
13825 pci_restore_state(pdev);
13826 pci_save_state(pdev);
13828 if (netif_running(dev))
13829 bnx2x_set_power_state(bp, PCI_D0);
13831 if (netif_running(dev)) {
13832 BNX2X_ERR("IO slot reset --> driver unload\n");
13834 /* MCP should have been reset; Need to wait for validity */
13835 bnx2x_init_shmem(bp);
13837 if (IS_PF(bp) && SHMEM2_HAS(bp, drv_capabilities_flag)) {
13841 drv_capabilities_flag[BP_FW_MB_IDX(bp)]);
13842 SHMEM2_WR(bp, drv_capabilities_flag[BP_FW_MB_IDX(bp)],
13843 v & ~DRV_FLAGS_CAPABILITIES_LOADED_L2);
13845 bnx2x_drain_tx_queues(bp);
13846 bnx2x_send_unload_req(bp, UNLOAD_RECOVERY);
13847 bnx2x_netif_stop(bp, 1);
13848 bnx2x_free_irq(bp);
13850 /* Report UNLOAD_DONE to MCP */
13851 bnx2x_send_unload_done(bp, true);
13856 bnx2x_prev_unload(bp);
13858 /* We should have reseted the engine, so It's fair to
13859 * assume the FW will no longer write to the bnx2x driver.
13861 bnx2x_squeeze_objects(bp);
13862 bnx2x_free_skbs(bp);
13863 for_each_rx_queue(bp, i)
13864 bnx2x_free_rx_sge_range(bp, bp->fp + i, NUM_RX_SGE);
13865 bnx2x_free_fp_mem(bp);
13866 bnx2x_free_mem(bp);
13868 bp->state = BNX2X_STATE_CLOSED;
13873 /* If AER, perform cleanup of the PCIe registers */
13874 if (bp->flags & AER_ENABLED) {
13875 if (pci_cleanup_aer_uncorrect_error_status(pdev))
13876 BNX2X_ERR("pci_cleanup_aer_uncorrect_error_status failed\n");
13878 DP(NETIF_MSG_HW, "pci_cleanup_aer_uncorrect_error_status succeeded\n");
13881 return PCI_ERS_RESULT_RECOVERED;
13885 * bnx2x_io_resume - called when traffic can start flowing again
13886 * @pdev: Pointer to PCI device
13888 * This callback is called when the error recovery driver tells us that
13889 * its OK to resume normal operation.
13891 static void bnx2x_io_resume(struct pci_dev *pdev)
13893 struct net_device *dev = pci_get_drvdata(pdev);
13894 struct bnx2x *bp = netdev_priv(dev);
13896 if (bp->recovery_state != BNX2X_RECOVERY_DONE) {
13897 netdev_err(bp->dev, "Handling parity error recovery. Try again later\n");
13903 bp->fw_seq = SHMEM_RD(bp, func_mb[BP_FW_MB_IDX(bp)].drv_mb_header) &
13904 DRV_MSG_SEQ_NUMBER_MASK;
13906 if (netif_running(dev))
13907 bnx2x_nic_load(bp, LOAD_NORMAL);
13909 netif_device_attach(dev);
13914 static const struct pci_error_handlers bnx2x_err_handler = {
13915 .error_detected = bnx2x_io_error_detected,
13916 .slot_reset = bnx2x_io_slot_reset,
13917 .resume = bnx2x_io_resume,
13920 static void bnx2x_shutdown(struct pci_dev *pdev)
13922 struct net_device *dev = pci_get_drvdata(pdev);
13928 bp = netdev_priv(dev);
13933 netif_device_detach(dev);
13936 /* Don't remove the netdevice, as there are scenarios which will cause
13937 * the kernel to hang, e.g., when trying to remove bnx2i while the
13938 * rootfs is mounted from SAN.
13940 __bnx2x_remove(pdev, dev, bp, false);
13943 static struct pci_driver bnx2x_pci_driver = {
13944 .name = DRV_MODULE_NAME,
13945 .id_table = bnx2x_pci_tbl,
13946 .probe = bnx2x_init_one,
13947 .remove = bnx2x_remove_one,
13948 .suspend = bnx2x_suspend,
13949 .resume = bnx2x_resume,
13950 .err_handler = &bnx2x_err_handler,
13951 #ifdef CONFIG_BNX2X_SRIOV
13952 .sriov_configure = bnx2x_sriov_configure,
13954 .shutdown = bnx2x_shutdown,
13957 static int __init bnx2x_init(void)
13961 pr_info("%s", version);
13963 bnx2x_wq = create_singlethread_workqueue("bnx2x");
13964 if (bnx2x_wq == NULL) {
13965 pr_err("Cannot create workqueue\n");
13968 bnx2x_iov_wq = create_singlethread_workqueue("bnx2x_iov");
13969 if (!bnx2x_iov_wq) {
13970 pr_err("Cannot create iov workqueue\n");
13971 destroy_workqueue(bnx2x_wq);
13975 ret = pci_register_driver(&bnx2x_pci_driver);
13977 pr_err("Cannot register driver\n");
13978 destroy_workqueue(bnx2x_wq);
13979 destroy_workqueue(bnx2x_iov_wq);
13984 static void __exit bnx2x_cleanup(void)
13986 struct list_head *pos, *q;
13988 pci_unregister_driver(&bnx2x_pci_driver);
13990 destroy_workqueue(bnx2x_wq);
13991 destroy_workqueue(bnx2x_iov_wq);
13993 /* Free globally allocated resources */
13994 list_for_each_safe(pos, q, &bnx2x_prev_list) {
13995 struct bnx2x_prev_path_list *tmp =
13996 list_entry(pos, struct bnx2x_prev_path_list, list);
14002 void bnx2x_notify_link_changed(struct bnx2x *bp)
14004 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_12 + BP_FUNC(bp)*sizeof(u32), 1);
14007 module_init(bnx2x_init);
14008 module_exit(bnx2x_cleanup);
14011 * bnx2x_set_iscsi_eth_mac_addr - set iSCSI MAC(s).
14013 * @bp: driver handle
14014 * @set: set or clear the CAM entry
14016 * This function will wait until the ramrod completion returns.
14017 * Return 0 if success, -ENODEV if ramrod doesn't return.
14019 static int bnx2x_set_iscsi_eth_mac_addr(struct bnx2x *bp)
14021 unsigned long ramrod_flags = 0;
14023 __set_bit(RAMROD_COMP_WAIT, &ramrod_flags);
14024 return bnx2x_set_mac_one(bp, bp->cnic_eth_dev.iscsi_mac,
14025 &bp->iscsi_l2_mac_obj, true,
14026 BNX2X_ISCSI_ETH_MAC, &ramrod_flags);
14029 /* count denotes the number of new completions we have seen */
14030 static void bnx2x_cnic_sp_post(struct bnx2x *bp, int count)
14032 struct eth_spe *spe;
14033 int cxt_index, cxt_offset;
14035 #ifdef BNX2X_STOP_ON_ERROR
14036 if (unlikely(bp->panic))
14040 spin_lock_bh(&bp->spq_lock);
14041 BUG_ON(bp->cnic_spq_pending < count);
14042 bp->cnic_spq_pending -= count;
14044 for (; bp->cnic_kwq_pending; bp->cnic_kwq_pending--) {
14045 u16 type = (le16_to_cpu(bp->cnic_kwq_cons->hdr.type)
14046 & SPE_HDR_CONN_TYPE) >>
14047 SPE_HDR_CONN_TYPE_SHIFT;
14048 u8 cmd = (le32_to_cpu(bp->cnic_kwq_cons->hdr.conn_and_cmd_data)
14049 >> SPE_HDR_CMD_ID_SHIFT) & 0xff;
14051 /* Set validation for iSCSI L2 client before sending SETUP
14054 if (type == ETH_CONNECTION_TYPE) {
14055 if (cmd == RAMROD_CMD_ID_ETH_CLIENT_SETUP) {
14056 cxt_index = BNX2X_ISCSI_ETH_CID(bp) /
14058 cxt_offset = BNX2X_ISCSI_ETH_CID(bp) -
14059 (cxt_index * ILT_PAGE_CIDS);
14060 bnx2x_set_ctx_validation(bp,
14061 &bp->context[cxt_index].
14062 vcxt[cxt_offset].eth,
14063 BNX2X_ISCSI_ETH_CID(bp));
14068 * There may be not more than 8 L2, not more than 8 L5 SPEs
14069 * and in the air. We also check that number of outstanding
14070 * COMMON ramrods is not more than the EQ and SPQ can
14073 if (type == ETH_CONNECTION_TYPE) {
14074 if (!atomic_read(&bp->cq_spq_left))
14077 atomic_dec(&bp->cq_spq_left);
14078 } else if (type == NONE_CONNECTION_TYPE) {
14079 if (!atomic_read(&bp->eq_spq_left))
14082 atomic_dec(&bp->eq_spq_left);
14083 } else if ((type == ISCSI_CONNECTION_TYPE) ||
14084 (type == FCOE_CONNECTION_TYPE)) {
14085 if (bp->cnic_spq_pending >=
14086 bp->cnic_eth_dev.max_kwqe_pending)
14089 bp->cnic_spq_pending++;
14091 BNX2X_ERR("Unknown SPE type: %d\n", type);
14096 spe = bnx2x_sp_get_next(bp);
14097 *spe = *bp->cnic_kwq_cons;
14099 DP(BNX2X_MSG_SP, "pending on SPQ %d, on KWQ %d count %d\n",
14100 bp->cnic_spq_pending, bp->cnic_kwq_pending, count);
14102 if (bp->cnic_kwq_cons == bp->cnic_kwq_last)
14103 bp->cnic_kwq_cons = bp->cnic_kwq;
14105 bp->cnic_kwq_cons++;
14107 bnx2x_sp_prod_update(bp);
14108 spin_unlock_bh(&bp->spq_lock);
14111 static int bnx2x_cnic_sp_queue(struct net_device *dev,
14112 struct kwqe_16 *kwqes[], u32 count)
14114 struct bnx2x *bp = netdev_priv(dev);
14117 #ifdef BNX2X_STOP_ON_ERROR
14118 if (unlikely(bp->panic)) {
14119 BNX2X_ERR("Can't post to SP queue while panic\n");
14124 if ((bp->recovery_state != BNX2X_RECOVERY_DONE) &&
14125 (bp->recovery_state != BNX2X_RECOVERY_NIC_LOADING)) {
14126 BNX2X_ERR("Handling parity error recovery. Try again later\n");
14130 spin_lock_bh(&bp->spq_lock);
14132 for (i = 0; i < count; i++) {
14133 struct eth_spe *spe = (struct eth_spe *)kwqes[i];
14135 if (bp->cnic_kwq_pending == MAX_SP_DESC_CNT)
14138 *bp->cnic_kwq_prod = *spe;
14140 bp->cnic_kwq_pending++;
14142 DP(BNX2X_MSG_SP, "L5 SPQE %x %x %x:%x pos %d\n",
14143 spe->hdr.conn_and_cmd_data, spe->hdr.type,
14144 spe->data.update_data_addr.hi,
14145 spe->data.update_data_addr.lo,
14146 bp->cnic_kwq_pending);
14148 if (bp->cnic_kwq_prod == bp->cnic_kwq_last)
14149 bp->cnic_kwq_prod = bp->cnic_kwq;
14151 bp->cnic_kwq_prod++;
14154 spin_unlock_bh(&bp->spq_lock);
14156 if (bp->cnic_spq_pending < bp->cnic_eth_dev.max_kwqe_pending)
14157 bnx2x_cnic_sp_post(bp, 0);
14162 static int bnx2x_cnic_ctl_send(struct bnx2x *bp, struct cnic_ctl_info *ctl)
14164 struct cnic_ops *c_ops;
14167 mutex_lock(&bp->cnic_mutex);
14168 c_ops = rcu_dereference_protected(bp->cnic_ops,
14169 lockdep_is_held(&bp->cnic_mutex));
14171 rc = c_ops->cnic_ctl(bp->cnic_data, ctl);
14172 mutex_unlock(&bp->cnic_mutex);
14177 static int bnx2x_cnic_ctl_send_bh(struct bnx2x *bp, struct cnic_ctl_info *ctl)
14179 struct cnic_ops *c_ops;
14183 c_ops = rcu_dereference(bp->cnic_ops);
14185 rc = c_ops->cnic_ctl(bp->cnic_data, ctl);
14192 * for commands that have no data
14194 int bnx2x_cnic_notify(struct bnx2x *bp, int cmd)
14196 struct cnic_ctl_info ctl = {0};
14200 return bnx2x_cnic_ctl_send(bp, &ctl);
14203 static void bnx2x_cnic_cfc_comp(struct bnx2x *bp, int cid, u8 err)
14205 struct cnic_ctl_info ctl = {0};
14207 /* first we tell CNIC and only then we count this as a completion */
14208 ctl.cmd = CNIC_CTL_COMPLETION_CMD;
14209 ctl.data.comp.cid = cid;
14210 ctl.data.comp.error = err;
14212 bnx2x_cnic_ctl_send_bh(bp, &ctl);
14213 bnx2x_cnic_sp_post(bp, 0);
14216 /* Called with netif_addr_lock_bh() taken.
14217 * Sets an rx_mode config for an iSCSI ETH client.
14219 * Completion should be checked outside.
14221 static void bnx2x_set_iscsi_eth_rx_mode(struct bnx2x *bp, bool start)
14223 unsigned long accept_flags = 0, ramrod_flags = 0;
14224 u8 cl_id = bnx2x_cnic_eth_cl_id(bp, BNX2X_ISCSI_ETH_CL_ID_IDX);
14225 int sched_state = BNX2X_FILTER_ISCSI_ETH_STOP_SCHED;
14228 /* Start accepting on iSCSI L2 ring. Accept all multicasts
14229 * because it's the only way for UIO Queue to accept
14230 * multicasts (in non-promiscuous mode only one Queue per
14231 * function will receive multicast packets (leading in our
14234 __set_bit(BNX2X_ACCEPT_UNICAST, &accept_flags);
14235 __set_bit(BNX2X_ACCEPT_ALL_MULTICAST, &accept_flags);
14236 __set_bit(BNX2X_ACCEPT_BROADCAST, &accept_flags);
14237 __set_bit(BNX2X_ACCEPT_ANY_VLAN, &accept_flags);
14239 /* Clear STOP_PENDING bit if START is requested */
14240 clear_bit(BNX2X_FILTER_ISCSI_ETH_STOP_SCHED, &bp->sp_state);
14242 sched_state = BNX2X_FILTER_ISCSI_ETH_START_SCHED;
14244 /* Clear START_PENDING bit if STOP is requested */
14245 clear_bit(BNX2X_FILTER_ISCSI_ETH_START_SCHED, &bp->sp_state);
14247 if (test_bit(BNX2X_FILTER_RX_MODE_PENDING, &bp->sp_state))
14248 set_bit(sched_state, &bp->sp_state);
14250 __set_bit(RAMROD_RX, &ramrod_flags);
14251 bnx2x_set_q_rx_mode(bp, cl_id, 0, accept_flags, 0,
14256 static int bnx2x_drv_ctl(struct net_device *dev, struct drv_ctl_info *ctl)
14258 struct bnx2x *bp = netdev_priv(dev);
14261 switch (ctl->cmd) {
14262 case DRV_CTL_CTXTBL_WR_CMD: {
14263 u32 index = ctl->data.io.offset;
14264 dma_addr_t addr = ctl->data.io.dma_addr;
14266 bnx2x_ilt_wr(bp, index, addr);
14270 case DRV_CTL_RET_L5_SPQ_CREDIT_CMD: {
14271 int count = ctl->data.credit.credit_count;
14273 bnx2x_cnic_sp_post(bp, count);
14277 /* rtnl_lock is held. */
14278 case DRV_CTL_START_L2_CMD: {
14279 struct cnic_eth_dev *cp = &bp->cnic_eth_dev;
14280 unsigned long sp_bits = 0;
14282 /* Configure the iSCSI classification object */
14283 bnx2x_init_mac_obj(bp, &bp->iscsi_l2_mac_obj,
14284 cp->iscsi_l2_client_id,
14285 cp->iscsi_l2_cid, BP_FUNC(bp),
14286 bnx2x_sp(bp, mac_rdata),
14287 bnx2x_sp_mapping(bp, mac_rdata),
14288 BNX2X_FILTER_MAC_PENDING,
14289 &bp->sp_state, BNX2X_OBJ_TYPE_RX,
14292 /* Set iSCSI MAC address */
14293 rc = bnx2x_set_iscsi_eth_mac_addr(bp);
14300 /* Start accepting on iSCSI L2 ring */
14302 netif_addr_lock_bh(dev);
14303 bnx2x_set_iscsi_eth_rx_mode(bp, true);
14304 netif_addr_unlock_bh(dev);
14306 /* bits to wait on */
14307 __set_bit(BNX2X_FILTER_RX_MODE_PENDING, &sp_bits);
14308 __set_bit(BNX2X_FILTER_ISCSI_ETH_START_SCHED, &sp_bits);
14310 if (!bnx2x_wait_sp_comp(bp, sp_bits))
14311 BNX2X_ERR("rx_mode completion timed out!\n");
14316 /* rtnl_lock is held. */
14317 case DRV_CTL_STOP_L2_CMD: {
14318 unsigned long sp_bits = 0;
14320 /* Stop accepting on iSCSI L2 ring */
14321 netif_addr_lock_bh(dev);
14322 bnx2x_set_iscsi_eth_rx_mode(bp, false);
14323 netif_addr_unlock_bh(dev);
14325 /* bits to wait on */
14326 __set_bit(BNX2X_FILTER_RX_MODE_PENDING, &sp_bits);
14327 __set_bit(BNX2X_FILTER_ISCSI_ETH_STOP_SCHED, &sp_bits);
14329 if (!bnx2x_wait_sp_comp(bp, sp_bits))
14330 BNX2X_ERR("rx_mode completion timed out!\n");
14335 /* Unset iSCSI L2 MAC */
14336 rc = bnx2x_del_all_macs(bp, &bp->iscsi_l2_mac_obj,
14337 BNX2X_ISCSI_ETH_MAC, true);
14340 case DRV_CTL_RET_L2_SPQ_CREDIT_CMD: {
14341 int count = ctl->data.credit.credit_count;
14343 smp_mb__before_atomic();
14344 atomic_add(count, &bp->cq_spq_left);
14345 smp_mb__after_atomic();
14348 case DRV_CTL_ULP_REGISTER_CMD: {
14349 int ulp_type = ctl->data.register_data.ulp_type;
14351 if (CHIP_IS_E3(bp)) {
14352 int idx = BP_FW_MB_IDX(bp);
14353 u32 cap = SHMEM2_RD(bp, drv_capabilities_flag[idx]);
14354 int path = BP_PATH(bp);
14355 int port = BP_PORT(bp);
14357 u32 scratch_offset;
14360 /* first write capability to shmem2 */
14361 if (ulp_type == CNIC_ULP_ISCSI)
14362 cap |= DRV_FLAGS_CAPABILITIES_LOADED_ISCSI;
14363 else if (ulp_type == CNIC_ULP_FCOE)
14364 cap |= DRV_FLAGS_CAPABILITIES_LOADED_FCOE;
14365 SHMEM2_WR(bp, drv_capabilities_flag[idx], cap);
14367 if ((ulp_type != CNIC_ULP_FCOE) ||
14368 (!SHMEM2_HAS(bp, ncsi_oem_data_addr)) ||
14369 (!(bp->flags & BC_SUPPORTS_FCOE_FEATURES)))
14372 /* if reached here - should write fcoe capabilities */
14373 scratch_offset = SHMEM2_RD(bp, ncsi_oem_data_addr);
14374 if (!scratch_offset)
14376 scratch_offset += offsetof(struct glob_ncsi_oem_data,
14377 fcoe_features[path][port]);
14378 host_addr = (u32 *) &(ctl->data.register_data.
14380 for (i = 0; i < sizeof(struct fcoe_capabilities);
14382 REG_WR(bp, scratch_offset + i,
14383 *(host_addr + i/4));
14385 bnx2x_schedule_sp_rtnl(bp, BNX2X_SP_RTNL_GET_DRV_VERSION, 0);
14389 case DRV_CTL_ULP_UNREGISTER_CMD: {
14390 int ulp_type = ctl->data.ulp_type;
14392 if (CHIP_IS_E3(bp)) {
14393 int idx = BP_FW_MB_IDX(bp);
14396 cap = SHMEM2_RD(bp, drv_capabilities_flag[idx]);
14397 if (ulp_type == CNIC_ULP_ISCSI)
14398 cap &= ~DRV_FLAGS_CAPABILITIES_LOADED_ISCSI;
14399 else if (ulp_type == CNIC_ULP_FCOE)
14400 cap &= ~DRV_FLAGS_CAPABILITIES_LOADED_FCOE;
14401 SHMEM2_WR(bp, drv_capabilities_flag[idx], cap);
14403 bnx2x_schedule_sp_rtnl(bp, BNX2X_SP_RTNL_GET_DRV_VERSION, 0);
14408 BNX2X_ERR("unknown command %x\n", ctl->cmd);
14415 void bnx2x_setup_cnic_irq_info(struct bnx2x *bp)
14417 struct cnic_eth_dev *cp = &bp->cnic_eth_dev;
14419 if (bp->flags & USING_MSIX_FLAG) {
14420 cp->drv_state |= CNIC_DRV_STATE_USING_MSIX;
14421 cp->irq_arr[0].irq_flags |= CNIC_IRQ_FL_MSIX;
14422 cp->irq_arr[0].vector = bp->msix_table[1].vector;
14424 cp->drv_state &= ~CNIC_DRV_STATE_USING_MSIX;
14425 cp->irq_arr[0].irq_flags &= ~CNIC_IRQ_FL_MSIX;
14427 if (!CHIP_IS_E1x(bp))
14428 cp->irq_arr[0].status_blk = (void *)bp->cnic_sb.e2_sb;
14430 cp->irq_arr[0].status_blk = (void *)bp->cnic_sb.e1x_sb;
14432 cp->irq_arr[0].status_blk_num = bnx2x_cnic_fw_sb_id(bp);
14433 cp->irq_arr[0].status_blk_num2 = bnx2x_cnic_igu_sb_id(bp);
14434 cp->irq_arr[1].status_blk = bp->def_status_blk;
14435 cp->irq_arr[1].status_blk_num = DEF_SB_ID;
14436 cp->irq_arr[1].status_blk_num2 = DEF_SB_IGU_ID;
14441 void bnx2x_setup_cnic_info(struct bnx2x *bp)
14443 struct cnic_eth_dev *cp = &bp->cnic_eth_dev;
14445 cp->ctx_tbl_offset = FUNC_ILT_BASE(BP_FUNC(bp)) +
14446 bnx2x_cid_ilt_lines(bp);
14447 cp->starting_cid = bnx2x_cid_ilt_lines(bp) * ILT_PAGE_CIDS;
14448 cp->fcoe_init_cid = BNX2X_FCOE_ETH_CID(bp);
14449 cp->iscsi_l2_cid = BNX2X_ISCSI_ETH_CID(bp);
14451 DP(NETIF_MSG_IFUP, "BNX2X_1st_NON_L2_ETH_CID(bp) %x, cp->starting_cid %x, cp->fcoe_init_cid %x, cp->iscsi_l2_cid %x\n",
14452 BNX2X_1st_NON_L2_ETH_CID(bp), cp->starting_cid, cp->fcoe_init_cid,
14455 if (NO_ISCSI_OOO(bp))
14456 cp->drv_state |= CNIC_DRV_STATE_NO_ISCSI_OOO;
14459 static int bnx2x_register_cnic(struct net_device *dev, struct cnic_ops *ops,
14462 struct bnx2x *bp = netdev_priv(dev);
14463 struct cnic_eth_dev *cp = &bp->cnic_eth_dev;
14466 DP(NETIF_MSG_IFUP, "Register_cnic called\n");
14469 BNX2X_ERR("NULL ops received\n");
14473 if (!CNIC_SUPPORT(bp)) {
14474 BNX2X_ERR("Can't register CNIC when not supported\n");
14475 return -EOPNOTSUPP;
14478 if (!CNIC_LOADED(bp)) {
14479 rc = bnx2x_load_cnic(bp);
14481 BNX2X_ERR("CNIC-related load failed\n");
14486 bp->cnic_enabled = true;
14488 bp->cnic_kwq = kzalloc(PAGE_SIZE, GFP_KERNEL);
14492 bp->cnic_kwq_cons = bp->cnic_kwq;
14493 bp->cnic_kwq_prod = bp->cnic_kwq;
14494 bp->cnic_kwq_last = bp->cnic_kwq + MAX_SP_DESC_CNT;
14496 bp->cnic_spq_pending = 0;
14497 bp->cnic_kwq_pending = 0;
14499 bp->cnic_data = data;
14502 cp->drv_state |= CNIC_DRV_STATE_REGD;
14503 cp->iro_arr = bp->iro_arr;
14505 bnx2x_setup_cnic_irq_info(bp);
14507 rcu_assign_pointer(bp->cnic_ops, ops);
14509 /* Schedule driver to read CNIC driver versions */
14510 bnx2x_schedule_sp_rtnl(bp, BNX2X_SP_RTNL_GET_DRV_VERSION, 0);
14515 static int bnx2x_unregister_cnic(struct net_device *dev)
14517 struct bnx2x *bp = netdev_priv(dev);
14518 struct cnic_eth_dev *cp = &bp->cnic_eth_dev;
14520 mutex_lock(&bp->cnic_mutex);
14522 RCU_INIT_POINTER(bp->cnic_ops, NULL);
14523 mutex_unlock(&bp->cnic_mutex);
14525 bp->cnic_enabled = false;
14526 kfree(bp->cnic_kwq);
14527 bp->cnic_kwq = NULL;
14532 static struct cnic_eth_dev *bnx2x_cnic_probe(struct net_device *dev)
14534 struct bnx2x *bp = netdev_priv(dev);
14535 struct cnic_eth_dev *cp = &bp->cnic_eth_dev;
14537 /* If both iSCSI and FCoE are disabled - return NULL in
14538 * order to indicate CNIC that it should not try to work
14539 * with this device.
14541 if (NO_ISCSI(bp) && NO_FCOE(bp))
14544 cp->drv_owner = THIS_MODULE;
14545 cp->chip_id = CHIP_ID(bp);
14546 cp->pdev = bp->pdev;
14547 cp->io_base = bp->regview;
14548 cp->io_base2 = bp->doorbells;
14549 cp->max_kwqe_pending = 8;
14550 cp->ctx_blk_size = CDU_ILT_PAGE_SZ;
14551 cp->ctx_tbl_offset = FUNC_ILT_BASE(BP_FUNC(bp)) +
14552 bnx2x_cid_ilt_lines(bp);
14553 cp->ctx_tbl_len = CNIC_ILT_LINES;
14554 cp->starting_cid = bnx2x_cid_ilt_lines(bp) * ILT_PAGE_CIDS;
14555 cp->drv_submit_kwqes_16 = bnx2x_cnic_sp_queue;
14556 cp->drv_ctl = bnx2x_drv_ctl;
14557 cp->drv_register_cnic = bnx2x_register_cnic;
14558 cp->drv_unregister_cnic = bnx2x_unregister_cnic;
14559 cp->fcoe_init_cid = BNX2X_FCOE_ETH_CID(bp);
14560 cp->iscsi_l2_client_id =
14561 bnx2x_cnic_eth_cl_id(bp, BNX2X_ISCSI_ETH_CL_ID_IDX);
14562 cp->iscsi_l2_cid = BNX2X_ISCSI_ETH_CID(bp);
14564 if (NO_ISCSI_OOO(bp))
14565 cp->drv_state |= CNIC_DRV_STATE_NO_ISCSI_OOO;
14568 cp->drv_state |= CNIC_DRV_STATE_NO_ISCSI;
14571 cp->drv_state |= CNIC_DRV_STATE_NO_FCOE;
14574 "page_size %d, tbl_offset %d, tbl_lines %d, starting cid %d\n",
14576 cp->ctx_tbl_offset,
14582 static u32 bnx2x_rx_ustorm_prods_offset(struct bnx2x_fastpath *fp)
14584 struct bnx2x *bp = fp->bp;
14585 u32 offset = BAR_USTRORM_INTMEM;
14588 return bnx2x_vf_ustorm_prods_offset(bp, fp);
14589 else if (!CHIP_IS_E1x(bp))
14590 offset += USTORM_RX_PRODS_E2_OFFSET(fp->cl_qzone_id);
14592 offset += USTORM_RX_PRODS_E1X_OFFSET(BP_PORT(bp), fp->cl_id);
14597 /* called only on E1H or E2.
14598 * When pretending to be PF, the pretend value is the function number 0...7
14599 * When pretending to be VF, the pretend val is the PF-num:VF-valid:ABS-VFID
14602 int bnx2x_pretend_func(struct bnx2x *bp, u16 pretend_func_val)
14606 if (CHIP_IS_E1H(bp) && pretend_func_val >= E1H_FUNC_MAX)
14609 /* get my own pretend register */
14610 pretend_reg = bnx2x_get_pretend_reg(bp);
14611 REG_WR(bp, pretend_reg, pretend_func_val);
14612 REG_RD(bp, pretend_reg);
14616 static void bnx2x_ptp_task(struct work_struct *work)
14618 struct bnx2x *bp = container_of(work, struct bnx2x, ptp_task);
14619 int port = BP_PORT(bp);
14622 struct skb_shared_hwtstamps shhwtstamps;
14624 /* Read Tx timestamp registers */
14625 val_seq = REG_RD(bp, port ? NIG_REG_P1_TLLH_PTP_BUF_SEQID :
14626 NIG_REG_P0_TLLH_PTP_BUF_SEQID);
14627 if (val_seq & 0x10000) {
14628 /* There is a valid timestamp value */
14629 timestamp = REG_RD(bp, port ? NIG_REG_P1_TLLH_PTP_BUF_TS_MSB :
14630 NIG_REG_P0_TLLH_PTP_BUF_TS_MSB);
14632 timestamp |= REG_RD(bp, port ? NIG_REG_P1_TLLH_PTP_BUF_TS_LSB :
14633 NIG_REG_P0_TLLH_PTP_BUF_TS_LSB);
14634 /* Reset timestamp register to allow new timestamp */
14635 REG_WR(bp, port ? NIG_REG_P1_TLLH_PTP_BUF_SEQID :
14636 NIG_REG_P0_TLLH_PTP_BUF_SEQID, 0x10000);
14637 ns = timecounter_cyc2time(&bp->timecounter, timestamp);
14639 memset(&shhwtstamps, 0, sizeof(shhwtstamps));
14640 shhwtstamps.hwtstamp = ns_to_ktime(ns);
14641 skb_tstamp_tx(bp->ptp_tx_skb, &shhwtstamps);
14642 dev_kfree_skb_any(bp->ptp_tx_skb);
14643 bp->ptp_tx_skb = NULL;
14645 DP(BNX2X_MSG_PTP, "Tx timestamp, timestamp cycles = %llu, ns = %llu\n",
14648 DP(BNX2X_MSG_PTP, "There is no valid Tx timestamp yet\n");
14649 /* Reschedule to keep checking for a valid timestamp value */
14650 schedule_work(&bp->ptp_task);
14654 void bnx2x_set_rx_ts(struct bnx2x *bp, struct sk_buff *skb)
14656 int port = BP_PORT(bp);
14659 timestamp = REG_RD(bp, port ? NIG_REG_P1_LLH_PTP_HOST_BUF_TS_MSB :
14660 NIG_REG_P0_LLH_PTP_HOST_BUF_TS_MSB);
14662 timestamp |= REG_RD(bp, port ? NIG_REG_P1_LLH_PTP_HOST_BUF_TS_LSB :
14663 NIG_REG_P0_LLH_PTP_HOST_BUF_TS_LSB);
14665 /* Reset timestamp register to allow new timestamp */
14666 REG_WR(bp, port ? NIG_REG_P1_LLH_PTP_HOST_BUF_SEQID :
14667 NIG_REG_P0_LLH_PTP_HOST_BUF_SEQID, 0x10000);
14669 ns = timecounter_cyc2time(&bp->timecounter, timestamp);
14671 skb_hwtstamps(skb)->hwtstamp = ns_to_ktime(ns);
14673 DP(BNX2X_MSG_PTP, "Rx timestamp, timestamp cycles = %llu, ns = %llu\n",
14678 static cycle_t bnx2x_cyclecounter_read(const struct cyclecounter *cc)
14680 struct bnx2x *bp = container_of(cc, struct bnx2x, cyclecounter);
14681 int port = BP_PORT(bp);
14685 REG_RD_DMAE(bp, port ? NIG_REG_TIMESYNC_GEN_REG + tsgen_synctime_t1 :
14686 NIG_REG_TIMESYNC_GEN_REG + tsgen_synctime_t0, wb_data, 2);
14687 phc_cycles = wb_data[1];
14688 phc_cycles = (phc_cycles << 32) + wb_data[0];
14690 DP(BNX2X_MSG_PTP, "PHC read cycles = %llu\n", phc_cycles);
14695 static void bnx2x_init_cyclecounter(struct bnx2x *bp)
14697 memset(&bp->cyclecounter, 0, sizeof(bp->cyclecounter));
14698 bp->cyclecounter.read = bnx2x_cyclecounter_read;
14699 bp->cyclecounter.mask = CYCLECOUNTER_MASK(64);
14700 bp->cyclecounter.shift = 1;
14701 bp->cyclecounter.mult = 1;
14704 static int bnx2x_send_reset_timesync_ramrod(struct bnx2x *bp)
14706 struct bnx2x_func_state_params func_params = {NULL};
14707 struct bnx2x_func_set_timesync_params *set_timesync_params =
14708 &func_params.params.set_timesync;
14710 /* Prepare parameters for function state transitions */
14711 __set_bit(RAMROD_COMP_WAIT, &func_params.ramrod_flags);
14712 __set_bit(RAMROD_RETRY, &func_params.ramrod_flags);
14714 func_params.f_obj = &bp->func_obj;
14715 func_params.cmd = BNX2X_F_CMD_SET_TIMESYNC;
14717 /* Function parameters */
14718 set_timesync_params->drift_adjust_cmd = TS_DRIFT_ADJUST_RESET;
14719 set_timesync_params->offset_cmd = TS_OFFSET_KEEP;
14721 return bnx2x_func_state_change(bp, &func_params);
14724 static int bnx2x_enable_ptp_packets(struct bnx2x *bp)
14726 struct bnx2x_queue_state_params q_params;
14729 /* send queue update ramrod to enable PTP packets */
14730 memset(&q_params, 0, sizeof(q_params));
14731 __set_bit(RAMROD_COMP_WAIT, &q_params.ramrod_flags);
14732 q_params.cmd = BNX2X_Q_CMD_UPDATE;
14733 __set_bit(BNX2X_Q_UPDATE_PTP_PKTS_CHNG,
14734 &q_params.params.update.update_flags);
14735 __set_bit(BNX2X_Q_UPDATE_PTP_PKTS,
14736 &q_params.params.update.update_flags);
14738 /* send the ramrod on all the queues of the PF */
14739 for_each_eth_queue(bp, i) {
14740 struct bnx2x_fastpath *fp = &bp->fp[i];
14742 /* Set the appropriate Queue object */
14743 q_params.q_obj = &bnx2x_sp_obj(bp, fp).q_obj;
14745 /* Update the Queue state */
14746 rc = bnx2x_queue_state_change(bp, &q_params);
14748 BNX2X_ERR("Failed to enable PTP packets\n");
14756 int bnx2x_configure_ptp_filters(struct bnx2x *bp)
14758 int port = BP_PORT(bp);
14761 if (!bp->hwtstamp_ioctl_called)
14764 switch (bp->tx_type) {
14765 case HWTSTAMP_TX_ON:
14766 bp->flags |= TX_TIMESTAMPING_EN;
14767 REG_WR(bp, port ? NIG_REG_P1_TLLH_PTP_PARAM_MASK :
14768 NIG_REG_P0_TLLH_PTP_PARAM_MASK, 0x6AA);
14769 REG_WR(bp, port ? NIG_REG_P1_TLLH_PTP_RULE_MASK :
14770 NIG_REG_P0_TLLH_PTP_RULE_MASK, 0x3EEE);
14772 case HWTSTAMP_TX_ONESTEP_SYNC:
14773 BNX2X_ERR("One-step timestamping is not supported\n");
14777 switch (bp->rx_filter) {
14778 case HWTSTAMP_FILTER_NONE:
14780 case HWTSTAMP_FILTER_ALL:
14781 case HWTSTAMP_FILTER_SOME:
14782 bp->rx_filter = HWTSTAMP_FILTER_NONE;
14784 case HWTSTAMP_FILTER_PTP_V1_L4_EVENT:
14785 case HWTSTAMP_FILTER_PTP_V1_L4_SYNC:
14786 case HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ:
14787 bp->rx_filter = HWTSTAMP_FILTER_PTP_V1_L4_EVENT;
14788 /* Initialize PTP detection for UDP/IPv4 events */
14789 REG_WR(bp, port ? NIG_REG_P1_LLH_PTP_PARAM_MASK :
14790 NIG_REG_P0_LLH_PTP_PARAM_MASK, 0x7EE);
14791 REG_WR(bp, port ? NIG_REG_P1_LLH_PTP_RULE_MASK :
14792 NIG_REG_P0_LLH_PTP_RULE_MASK, 0x3FFE);
14794 case HWTSTAMP_FILTER_PTP_V2_L4_EVENT:
14795 case HWTSTAMP_FILTER_PTP_V2_L4_SYNC:
14796 case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ:
14797 bp->rx_filter = HWTSTAMP_FILTER_PTP_V2_L4_EVENT;
14798 /* Initialize PTP detection for UDP/IPv4 or UDP/IPv6 events */
14799 REG_WR(bp, port ? NIG_REG_P1_LLH_PTP_PARAM_MASK :
14800 NIG_REG_P0_LLH_PTP_PARAM_MASK, 0x7EA);
14801 REG_WR(bp, port ? NIG_REG_P1_LLH_PTP_RULE_MASK :
14802 NIG_REG_P0_LLH_PTP_RULE_MASK, 0x3FEE);
14804 case HWTSTAMP_FILTER_PTP_V2_L2_EVENT:
14805 case HWTSTAMP_FILTER_PTP_V2_L2_SYNC:
14806 case HWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ:
14807 bp->rx_filter = HWTSTAMP_FILTER_PTP_V2_L2_EVENT;
14808 /* Initialize PTP detection L2 events */
14809 REG_WR(bp, port ? NIG_REG_P1_LLH_PTP_PARAM_MASK :
14810 NIG_REG_P0_LLH_PTP_PARAM_MASK, 0x6BF);
14811 REG_WR(bp, port ? NIG_REG_P1_LLH_PTP_RULE_MASK :
14812 NIG_REG_P0_LLH_PTP_RULE_MASK, 0x3EFF);
14815 case HWTSTAMP_FILTER_PTP_V2_EVENT:
14816 case HWTSTAMP_FILTER_PTP_V2_SYNC:
14817 case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ:
14818 bp->rx_filter = HWTSTAMP_FILTER_PTP_V2_EVENT;
14819 /* Initialize PTP detection L2, UDP/IPv4 or UDP/IPv6 events */
14820 REG_WR(bp, port ? NIG_REG_P1_LLH_PTP_PARAM_MASK :
14821 NIG_REG_P0_LLH_PTP_PARAM_MASK, 0x6AA);
14822 REG_WR(bp, port ? NIG_REG_P1_LLH_PTP_RULE_MASK :
14823 NIG_REG_P0_LLH_PTP_RULE_MASK, 0x3EEE);
14827 /* Indicate to FW that this PF expects recorded PTP packets */
14828 rc = bnx2x_enable_ptp_packets(bp);
14832 /* Enable sending PTP packets to host */
14833 REG_WR(bp, port ? NIG_REG_P1_LLH_PTP_TO_HOST :
14834 NIG_REG_P0_LLH_PTP_TO_HOST, 0x1);
14839 static int bnx2x_hwtstamp_ioctl(struct bnx2x *bp, struct ifreq *ifr)
14841 struct hwtstamp_config config;
14844 DP(BNX2X_MSG_PTP, "HWTSTAMP IOCTL called\n");
14846 if (copy_from_user(&config, ifr->ifr_data, sizeof(config)))
14849 DP(BNX2X_MSG_PTP, "Requested tx_type: %d, requested rx_filters = %d\n",
14850 config.tx_type, config.rx_filter);
14852 if (config.flags) {
14853 BNX2X_ERR("config.flags is reserved for future use\n");
14857 bp->hwtstamp_ioctl_called = 1;
14858 bp->tx_type = config.tx_type;
14859 bp->rx_filter = config.rx_filter;
14861 rc = bnx2x_configure_ptp_filters(bp);
14865 config.rx_filter = bp->rx_filter;
14867 return copy_to_user(ifr->ifr_data, &config, sizeof(config)) ?
14871 /* Configures HW for PTP */
14872 static int bnx2x_configure_ptp(struct bnx2x *bp)
14874 int rc, port = BP_PORT(bp);
14877 /* Reset PTP event detection rules - will be configured in the IOCTL */
14878 REG_WR(bp, port ? NIG_REG_P1_LLH_PTP_PARAM_MASK :
14879 NIG_REG_P0_LLH_PTP_PARAM_MASK, 0x7FF);
14880 REG_WR(bp, port ? NIG_REG_P1_LLH_PTP_RULE_MASK :
14881 NIG_REG_P0_LLH_PTP_RULE_MASK, 0x3FFF);
14882 REG_WR(bp, port ? NIG_REG_P1_TLLH_PTP_PARAM_MASK :
14883 NIG_REG_P0_TLLH_PTP_PARAM_MASK, 0x7FF);
14884 REG_WR(bp, port ? NIG_REG_P1_TLLH_PTP_RULE_MASK :
14885 NIG_REG_P0_TLLH_PTP_RULE_MASK, 0x3FFF);
14887 /* Disable PTP packets to host - will be configured in the IOCTL*/
14888 REG_WR(bp, port ? NIG_REG_P1_LLH_PTP_TO_HOST :
14889 NIG_REG_P0_LLH_PTP_TO_HOST, 0x0);
14891 /* Enable the PTP feature */
14892 REG_WR(bp, port ? NIG_REG_P1_PTP_EN :
14893 NIG_REG_P0_PTP_EN, 0x3F);
14895 /* Enable the free-running counter */
14898 REG_WR_DMAE(bp, NIG_REG_TIMESYNC_GEN_REG + tsgen_ctrl, wb_data, 2);
14900 /* Reset drift register (offset register is not reset) */
14901 rc = bnx2x_send_reset_timesync_ramrod(bp);
14903 BNX2X_ERR("Failed to reset PHC drift register\n");
14907 /* Reset possibly old timestamps */
14908 REG_WR(bp, port ? NIG_REG_P1_LLH_PTP_HOST_BUF_SEQID :
14909 NIG_REG_P0_LLH_PTP_HOST_BUF_SEQID, 0x10000);
14910 REG_WR(bp, port ? NIG_REG_P1_TLLH_PTP_BUF_SEQID :
14911 NIG_REG_P0_TLLH_PTP_BUF_SEQID, 0x10000);
14916 /* Called during load, to initialize PTP-related stuff */
14917 void bnx2x_init_ptp(struct bnx2x *bp)
14921 /* Configure PTP in HW */
14922 rc = bnx2x_configure_ptp(bp);
14924 BNX2X_ERR("Stopping PTP initialization\n");
14928 /* Init work queue for Tx timestamping */
14929 INIT_WORK(&bp->ptp_task, bnx2x_ptp_task);
14931 /* Init cyclecounter and timecounter. This is done only in the first
14932 * load. If done in every load, PTP application will fail when doing
14933 * unload / load (e.g. MTU change) while it is running.
14935 if (!bp->timecounter_init_done) {
14936 bnx2x_init_cyclecounter(bp);
14937 timecounter_init(&bp->timecounter, &bp->cyclecounter,
14938 ktime_to_ns(ktime_get_real()));
14939 bp->timecounter_init_done = 1;
14942 DP(BNX2X_MSG_PTP, "PTP initialization ended successfully\n");