drivers/net/ethernet/broadcom/bnx2x/bnx2x_main.c

   1 /* bnx2x_main.c: QLogic Everest network driver.
   2  *
   3  * Copyright (c) 2007-2013 Broadcom Corporation
   4  * Copyright (c) 2014 QLogic Corporation
   5  * All rights reserved
   6  *
   7  * This program is free software; you can redistribute it and/or modify
   8  * it under the terms of the GNU General Public License as published by
   9  * the Free Software Foundation.
  10  *
  11  * Maintained by: Ariel Elior <ariel.elior@qlogic.com>
  12  * Written by: Eliezer Tamir
  13  * Based on code from Michael Chan's bnx2 driver
  14  * UDP CSUM errata workaround by Arik Gendelman
  15  * Slowpath and fastpath rework by Vladislav Zolotarov
  16  * Statistics and Link management by Yitchak Gertner
  17  *
  18  */
  19
  20 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
  21
  22 #include <linux/module.h>
  23 #include <linux/moduleparam.h>
  24 #include <linux/kernel.h>
  25 #include <linux/device.h>  /* for dev_info() */
  26 #include <linux/timer.h>
  27 #include <linux/errno.h>
  28 #include <linux/ioport.h>
  29 #include <linux/slab.h>
  30 #include <linux/interrupt.h>
  31 #include <linux/pci.h>
  32 #include <linux/aer.h>
  33 #include <linux/init.h>
  34 #include <linux/netdevice.h>
  35 #include <linux/etherdevice.h>
  36 #include <linux/skbuff.h>
  37 #include <linux/dma-mapping.h>
  38 #include <linux/bitops.h>
  39 #include <linux/irq.h>
  40 #include <linux/delay.h>
  41 #include <asm/byteorder.h>
  42 #include <linux/time.h>
  43 #include <linux/ethtool.h>
  44 #include <linux/mii.h>
  45 #include <linux/if_vlan.h>
  46 #include <linux/crash_dump.h>
  47 #include <net/ip.h>
  48 #include <net/ipv6.h>
  49 #include <net/tcp.h>
  50 #include <net/vxlan.h>
  51 #include <net/checksum.h>
  52 #include <net/ip6_checksum.h>
  53 #include <linux/workqueue.h>
  54 #include <linux/crc32.h>
  55 #include <linux/crc32c.h>
  56 #include <linux/prefetch.h>
  57 #include <linux/zlib.h>
  58 #include <linux/io.h>
  59 #include <linux/semaphore.h>
  60 #include <linux/stringify.h>
  61 #include <linux/vmalloc.h>
  62
  63 #include "bnx2x.h"
  64 #include "bnx2x_init.h"
  65 #include "bnx2x_init_ops.h"
  66 #include "bnx2x_cmn.h"
  67 #include "bnx2x_vfpf.h"
  68 #include "bnx2x_dcb.h"
  69 #include "bnx2x_sp.h"
  70 #include <linux/firmware.h>
  71 #include "bnx2x_fw_file_hdr.h"
  72 /* FW files */
  73 #define FW_FILE_VERSION                                 \
  74         __stringify(BCM_5710_FW_MAJOR_VERSION) "."      \
  75         __stringify(BCM_5710_FW_MINOR_VERSION) "."      \
  76         __stringify(BCM_5710_FW_REVISION_VERSION) "."   \
  77         __stringify(BCM_5710_FW_ENGINEERING_VERSION)
  78 #define FW_FILE_NAME_E1         "bnx2x/bnx2x-e1-" FW_FILE_VERSION ".fw"
  79 #define FW_FILE_NAME_E1H        "bnx2x/bnx2x-e1h-" FW_FILE_VERSION ".fw"
  80 #define FW_FILE_NAME_E2         "bnx2x/bnx2x-e2-" FW_FILE_VERSION ".fw"
  81
  82 /* Time in jiffies before concluding the transmitter is hung */
  83 #define TX_TIMEOUT              (5*HZ)
  84
  85 static char version[] =
  86         "QLogic 5771x/578xx 10/20-Gigabit Ethernet Driver "
  87         DRV_MODULE_NAME " " DRV_MODULE_VERSION " (" DRV_MODULE_RELDATE ")\n";
  88
  89 MODULE_AUTHOR("Eliezer Tamir");
  90 MODULE_DESCRIPTION("QLogic "
  91                    "BCM57710/57711/57711E/"
  92                    "57712/57712_MF/57800/57800_MF/57810/57810_MF/"
  93                    "57840/57840_MF Driver");
  94 MODULE_LICENSE("GPL");
  95 MODULE_VERSION(DRV_MODULE_VERSION);
  96 MODULE_FIRMWARE(FW_FILE_NAME_E1);
  97 MODULE_FIRMWARE(FW_FILE_NAME_E1H);
  98 MODULE_FIRMWARE(FW_FILE_NAME_E2);
  99
 100 int bnx2x_num_queues;
 101 module_param_named(num_queues, bnx2x_num_queues, int, S_IRUGO);
 102 MODULE_PARM_DESC(num_queues,
 103                  " Set number of queues (default is as a number of CPUs)");
 104
 105 static int disable_tpa;
 106 module_param(disable_tpa, int, S_IRUGO);
 107 MODULE_PARM_DESC(disable_tpa, " Disable the TPA (LRO) feature");
 108
 109 static int int_mode;
 110 module_param(int_mode, int, S_IRUGO);
 111 MODULE_PARM_DESC(int_mode, " Force interrupt mode other than MSI-X "
 112                                 "(1 INT#x; 2 MSI)");
 113
 114 static int dropless_fc;
 115 module_param(dropless_fc, int, S_IRUGO);
 116 MODULE_PARM_DESC(dropless_fc, " Pause on exhausted host ring");
 117
 118 static int mrrs = -1;
 119 module_param(mrrs, int, S_IRUGO);
 120 MODULE_PARM_DESC(mrrs, " Force Max Read Req Size (0..3) (for debug)");
 121
 122 static int debug;
 123 module_param(debug, int, S_IRUGO);
 124 MODULE_PARM_DESC(debug, " Default debug msglevel");
 125
 126 static struct workqueue_struct *bnx2x_wq;
 127 struct workqueue_struct *bnx2x_iov_wq;
 128
 129 struct bnx2x_mac_vals {
 130         u32 xmac_addr;
 131         u32 xmac_val;
 132         u32 emac_addr;
 133         u32 emac_val;
 134         u32 umac_addr[2];
 135         u32 umac_val[2];
 136         u32 bmac_addr;
 137         u32 bmac_val[2];
 138 };
 139
 140 enum bnx2x_board_type {
 141         BCM57710 = 0,
 142         BCM57711,
 143         BCM57711E,
 144         BCM57712,
 145         BCM57712_MF,
 146         BCM57712_VF,
 147         BCM57800,
 148         BCM57800_MF,
 149         BCM57800_VF,
 150         BCM57810,
 151         BCM57810_MF,
 152         BCM57810_VF,
 153         BCM57840_4_10,
 154         BCM57840_2_20,
 155         BCM57840_MF,
 156         BCM57840_VF,
 157         BCM57811,
 158         BCM57811_MF,
 159         BCM57840_O,
 160         BCM57840_MFO,
 161         BCM57811_VF
 162 };
 163
 164 /* indexed by board_type, above */
 165 static struct {
 166         char *name;
 167 } board_info[] = {
 168         [BCM57710]      = { "QLogic BCM57710 10 Gigabit PCIe [Everest]" },
 169         [BCM57711]      = { "QLogic BCM57711 10 Gigabit PCIe" },
 170         [BCM57711E]     = { "QLogic BCM57711E 10 Gigabit PCIe" },
 171         [BCM57712]      = { "QLogic BCM57712 10 Gigabit Ethernet" },
 172         [BCM57712_MF]   = { "QLogic BCM57712 10 Gigabit Ethernet Multi Function" },
 173         [BCM57712_VF]   = { "QLogic BCM57712 10 Gigabit Ethernet Virtual Function" },
 174         [BCM57800]      = { "QLogic BCM57800 10 Gigabit Ethernet" },
 175         [BCM57800_MF]   = { "QLogic BCM57800 10 Gigabit Ethernet Multi Function" },
 176         [BCM57800_VF]   = { "QLogic BCM57800 10 Gigabit Ethernet Virtual Function" },
 177         [BCM57810]      = { "QLogic BCM57810 10 Gigabit Ethernet" },
 178         [BCM57810_MF]   = { "QLogic BCM57810 10 Gigabit Ethernet Multi Function" },
 179         [BCM57810_VF]   = { "QLogic BCM57810 10 Gigabit Ethernet Virtual Function" },
 180         [BCM57840_4_10] = { "QLogic BCM57840 10 Gigabit Ethernet" },
 181         [BCM57840_2_20] = { "QLogic BCM57840 20 Gigabit Ethernet" },
 182         [BCM57840_MF]   = { "QLogic BCM57840 10/20 Gigabit Ethernet Multi Function" },
 183         [BCM57840_VF]   = { "QLogic BCM57840 10/20 Gigabit Ethernet Virtual Function" },
 184         [BCM57811]      = { "QLogic BCM57811 10 Gigabit Ethernet" },
 185         [BCM57811_MF]   = { "QLogic BCM57811 10 Gigabit Ethernet Multi Function" },
 186         [BCM57840_O]    = { "QLogic BCM57840 10/20 Gigabit Ethernet" },
 187         [BCM57840_MFO]  = { "QLogic BCM57840 10/20 Gigabit Ethernet Multi Function" },
 188         [BCM57811_VF]   = { "QLogic BCM57840 10/20 Gigabit Ethernet Virtual Function" }
 189 };
 190
 191 #ifndef PCI_DEVICE_ID_NX2_57710
 192 #define PCI_DEVICE_ID_NX2_57710         CHIP_NUM_57710
 193 #endif
 194 #ifndef PCI_DEVICE_ID_NX2_57711
 195 #define PCI_DEVICE_ID_NX2_57711         CHIP_NUM_57711
 196 #endif
 197 #ifndef PCI_DEVICE_ID_NX2_57711E
 198 #define PCI_DEVICE_ID_NX2_57711E        CHIP_NUM_57711E
 199 #endif
 200 #ifndef PCI_DEVICE_ID_NX2_57712
 201 #define PCI_DEVICE_ID_NX2_57712         CHIP_NUM_57712
 202 #endif
 203 #ifndef PCI_DEVICE_ID_NX2_57712_MF
 204 #define PCI_DEVICE_ID_NX2_57712_MF      CHIP_NUM_57712_MF
 205 #endif
 206 #ifndef PCI_DEVICE_ID_NX2_57712_VF
 207 #define PCI_DEVICE_ID_NX2_57712_VF      CHIP_NUM_57712_VF
 208 #endif
 209 #ifndef PCI_DEVICE_ID_NX2_57800
 210 #define PCI_DEVICE_ID_NX2_57800         CHIP_NUM_57800
 211 #endif
 212 #ifndef PCI_DEVICE_ID_NX2_57800_MF
 213 #define PCI_DEVICE_ID_NX2_57800_MF      CHIP_NUM_57800_MF
 214 #endif
 215 #ifndef PCI_DEVICE_ID_NX2_57800_VF
 216 #define PCI_DEVICE_ID_NX2_57800_VF      CHIP_NUM_57800_VF
 217 #endif
 218 #ifndef PCI_DEVICE_ID_NX2_57810
 219 #define PCI_DEVICE_ID_NX2_57810         CHIP_NUM_57810
 220 #endif
 221 #ifndef PCI_DEVICE_ID_NX2_57810_MF
 222 #define PCI_DEVICE_ID_NX2_57810_MF      CHIP_NUM_57810_MF
 223 #endif
 224 #ifndef PCI_DEVICE_ID_NX2_57840_O
 225 #define PCI_DEVICE_ID_NX2_57840_O       CHIP_NUM_57840_OBSOLETE
 226 #endif
 227 #ifndef PCI_DEVICE_ID_NX2_57810_VF
 228 #define PCI_DEVICE_ID_NX2_57810_VF      CHIP_NUM_57810_VF
 229 #endif
 230 #ifndef PCI_DEVICE_ID_NX2_57840_4_10
 231 #define PCI_DEVICE_ID_NX2_57840_4_10    CHIP_NUM_57840_4_10
 232 #endif
 233 #ifndef PCI_DEVICE_ID_NX2_57840_2_20
 234 #define PCI_DEVICE_ID_NX2_57840_2_20    CHIP_NUM_57840_2_20
 235 #endif
 236 #ifndef PCI_DEVICE_ID_NX2_57840_MFO
 237 #define PCI_DEVICE_ID_NX2_57840_MFO     CHIP_NUM_57840_MF_OBSOLETE
 238 #endif
 239 #ifndef PCI_DEVICE_ID_NX2_57840_MF
 240 #define PCI_DEVICE_ID_NX2_57840_MF      CHIP_NUM_57840_MF
 241 #endif
 242 #ifndef PCI_DEVICE_ID_NX2_57840_VF
 243 #define PCI_DEVICE_ID_NX2_57840_VF      CHIP_NUM_57840_VF
 244 #endif
 245 #ifndef PCI_DEVICE_ID_NX2_57811
 246 #define PCI_DEVICE_ID_NX2_57811         CHIP_NUM_57811
 247 #endif
 248 #ifndef PCI_DEVICE_ID_NX2_57811_MF
 249 #define PCI_DEVICE_ID_NX2_57811_MF      CHIP_NUM_57811_MF
 250 #endif
 251 #ifndef PCI_DEVICE_ID_NX2_57811_VF
 252 #define PCI_DEVICE_ID_NX2_57811_VF      CHIP_NUM_57811_VF
 253 #endif
 254
 255 static const struct pci_device_id bnx2x_pci_tbl[] = {
 256         { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57710), BCM57710 },
 257         { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57711), BCM57711 },
 258         { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57711E), BCM57711E },
 259         { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57712), BCM57712 },
 260         { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57712_MF), BCM57712_MF },
 261         { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57712_VF), BCM57712_VF },
 262         { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57800), BCM57800 },
 263         { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57800_MF), BCM57800_MF },
 264         { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57800_VF), BCM57800_VF },
 265         { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57810), BCM57810 },
 266         { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57810_MF), BCM57810_MF },
 267         { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57840_O), BCM57840_O },
 268         { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57840_4_10), BCM57840_4_10 },
 269         { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57840_2_20), BCM57840_2_20 },
 270         { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57810_VF), BCM57810_VF },
 271         { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57840_MFO), BCM57840_MFO },
 272         { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57840_MF), BCM57840_MF },
 273         { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57840_VF), BCM57840_VF },
 274         { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57811), BCM57811 },
 275         { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57811_MF), BCM57811_MF },
 276         { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57811_VF), BCM57811_VF },
 277         { 0 }
 278 };
 279
 280 MODULE_DEVICE_TABLE(pci, bnx2x_pci_tbl);
 281
 282 /* Global resources for unloading a previously loaded device */
 283 #define BNX2X_PREV_WAIT_NEEDED 1
 284 static DEFINE_SEMAPHORE(bnx2x_prev_sem);
 285 static LIST_HEAD(bnx2x_prev_list);
 286
 287 /* Forward declaration */
 288 static struct cnic_eth_dev *bnx2x_cnic_probe(struct net_device *dev);
 289 static u32 bnx2x_rx_ustorm_prods_offset(struct bnx2x_fastpath *fp);
 290 static int bnx2x_set_storm_rx_mode(struct bnx2x *bp);
 291
 292 /****************************************************************************
 293 * General service functions
 294 ****************************************************************************/
 295
 296 static int bnx2x_hwtstamp_ioctl(struct bnx2x *bp, struct ifreq *ifr);
 297
 298 static void __storm_memset_dma_mapping(struct bnx2x *bp,
 299                                        u32 addr, dma_addr_t mapping)
 300 {
 301         REG_WR(bp,  addr, U64_LO(mapping));
 302         REG_WR(bp,  addr + 4, U64_HI(mapping));
 303 }
 304
 305 static void storm_memset_spq_addr(struct bnx2x *bp,
 306                                   dma_addr_t mapping, u16 abs_fid)
 307 {
 308         u32 addr = XSEM_REG_FAST_MEMORY +
 309                         XSTORM_SPQ_PAGE_BASE_OFFSET(abs_fid);
 310
 311         __storm_memset_dma_mapping(bp, addr, mapping);
 312 }
 313
 314 static void storm_memset_vf_to_pf(struct bnx2x *bp, u16 abs_fid,
 315                                   u16 pf_id)
 316 {
 317         REG_WR8(bp, BAR_XSTRORM_INTMEM + XSTORM_VF_TO_PF_OFFSET(abs_fid),
 318                 pf_id);
 319         REG_WR8(bp, BAR_CSTRORM_INTMEM + CSTORM_VF_TO_PF_OFFSET(abs_fid),
 320                 pf_id);
 321         REG_WR8(bp, BAR_TSTRORM_INTMEM + TSTORM_VF_TO_PF_OFFSET(abs_fid),
 322                 pf_id);
 323         REG_WR8(bp, BAR_USTRORM_INTMEM + USTORM_VF_TO_PF_OFFSET(abs_fid),
 324                 pf_id);
 325 }
 326
 327 static void storm_memset_func_en(struct bnx2x *bp, u16 abs_fid,
 328                                  u8 enable)
 329 {
 330         REG_WR8(bp, BAR_XSTRORM_INTMEM + XSTORM_FUNC_EN_OFFSET(abs_fid),
 331                 enable);
 332         REG_WR8(bp, BAR_CSTRORM_INTMEM + CSTORM_FUNC_EN_OFFSET(abs_fid),
 333                 enable);
 334         REG_WR8(bp, BAR_TSTRORM_INTMEM + TSTORM_FUNC_EN_OFFSET(abs_fid),
 335                 enable);
 336         REG_WR8(bp, BAR_USTRORM_INTMEM + USTORM_FUNC_EN_OFFSET(abs_fid),
 337                 enable);
 338 }
 339
 340 static void storm_memset_eq_data(struct bnx2x *bp,
 341                                  struct event_ring_data *eq_data,
 342                                 u16 pfid)
 343 {
 344         size_t size = sizeof(struct event_ring_data);
 345
 346         u32 addr = BAR_CSTRORM_INTMEM + CSTORM_EVENT_RING_DATA_OFFSET(pfid);
 347
 348         __storm_memset_struct(bp, addr, size, (u32 *)eq_data);
 349 }
 350
 351 static void storm_memset_eq_prod(struct bnx2x *bp, u16 eq_prod,
 352                                  u16 pfid)
 353 {
 354         u32 addr = BAR_CSTRORM_INTMEM + CSTORM_EVENT_RING_PROD_OFFSET(pfid);
 355         REG_WR16(bp, addr, eq_prod);
 356 }
 357
 358 /* used only at init
 359  * locking is done by mcp
 360  */
 361 static void bnx2x_reg_wr_ind(struct bnx2x *bp, u32 addr, u32 val)
 362 {
 363         pci_write_config_dword(bp->pdev, PCICFG_GRC_ADDRESS, addr);
 364         pci_write_config_dword(bp->pdev, PCICFG_GRC_DATA, val);
 365         pci_write_config_dword(bp->pdev, PCICFG_GRC_ADDRESS,
 366                                PCICFG_VENDOR_ID_OFFSET);
 367 }
 368
 369 static u32 bnx2x_reg_rd_ind(struct bnx2x *bp, u32 addr)
 370 {
 371         u32 val;
 372
 373         pci_write_config_dword(bp->pdev, PCICFG_GRC_ADDRESS, addr);
 374         pci_read_config_dword(bp->pdev, PCICFG_GRC_DATA, &val);
 375         pci_write_config_dword(bp->pdev, PCICFG_GRC_ADDRESS,
 376                                PCICFG_VENDOR_ID_OFFSET);
 377
 378         return val;
 379 }
 380
 381 #define DMAE_DP_SRC_GRC         "grc src_addr [%08x]"
 382 #define DMAE_DP_SRC_PCI         "pci src_addr [%x:%08x]"
 383 #define DMAE_DP_DST_GRC         "grc dst_addr [%08x]"
 384 #define DMAE_DP_DST_PCI         "pci dst_addr [%x:%08x]"
 385 #define DMAE_DP_DST_NONE        "dst_addr [none]"
 386
 387 static void bnx2x_dp_dmae(struct bnx2x *bp,
 388                           struct dmae_command *dmae, int msglvl)
 389 {
 390         u32 src_type = dmae->opcode & DMAE_COMMAND_SRC;
 391         int i;
 392
 393         switch (dmae->opcode & DMAE_COMMAND_DST) {
 394         case DMAE_CMD_DST_PCI:
 395                 if (src_type == DMAE_CMD_SRC_PCI)
 396                         DP(msglvl, "DMAE: opcode 0x%08x\n"
 397                            "src [%x:%08x], len [%d*4], dst [%x:%08x]\n"
 398                            "comp_addr [%x:%08x], comp_val 0x%08x\n",
 399                            dmae->opcode, dmae->src_addr_hi, dmae->src_addr_lo,
 400                            dmae->len, dmae->dst_addr_hi, dmae->dst_addr_lo,
 401                            dmae->comp_addr_hi, dmae->comp_addr_lo,
 402                            dmae->comp_val);
 403                 else
 404                         DP(msglvl, "DMAE: opcode 0x%08x\n"
 405                            "src [%08x], len [%d*4], dst [%x:%08x]\n"
 406                            "comp_addr [%x:%08x], comp_val 0x%08x\n",
 407                            dmae->opcode, dmae->src_addr_lo >> 2,
 408                            dmae->len, dmae->dst_addr_hi, dmae->dst_addr_lo,
 409                            dmae->comp_addr_hi, dmae->comp_addr_lo,
 410                            dmae->comp_val);
 411                 break;
 412         case DMAE_CMD_DST_GRC:
 413                 if (src_type == DMAE_CMD_SRC_PCI)
 414                         DP(msglvl, "DMAE: opcode 0x%08x\n"
 415                            "src [%x:%08x], len [%d*4], dst_addr [%08x]\n"
 416                            "comp_addr [%x:%08x], comp_val 0x%08x\n",
 417                            dmae->opcode, dmae->src_addr_hi, dmae->src_addr_lo,
 418                            dmae->len, dmae->dst_addr_lo >> 2,
 419                            dmae->comp_addr_hi, dmae->comp_addr_lo,
 420                            dmae->comp_val);
 421                 else
 422                         DP(msglvl, "DMAE: opcode 0x%08x\n"
 423                            "src [%08x], len [%d*4], dst [%08x]\n"
 424                            "comp_addr [%x:%08x], comp_val 0x%08x\n",
 425                            dmae->opcode, dmae->src_addr_lo >> 2,
 426                            dmae->len, dmae->dst_addr_lo >> 2,
 427                            dmae->comp_addr_hi, dmae->comp_addr_lo,
 428                            dmae->comp_val);
 429                 break;
 430         default:
 431                 if (src_type == DMAE_CMD_SRC_PCI)
 432                         DP(msglvl, "DMAE: opcode 0x%08x\n"
 433                            "src_addr [%x:%08x]  len [%d * 4]  dst_addr [none]\n"
 434                            "comp_addr [%x:%08x]  comp_val 0x%08x\n",
 435                            dmae->opcode, dmae->src_addr_hi, dmae->src_addr_lo,
 436                            dmae->len, dmae->comp_addr_hi, dmae->comp_addr_lo,
 437                            dmae->comp_val);
 438                 else
 439                         DP(msglvl, "DMAE: opcode 0x%08x\n"
 440                            "src_addr [%08x]  len [%d * 4]  dst_addr [none]\n"
 441                            "comp_addr [%x:%08x]  comp_val 0x%08x\n",
 442                            dmae->opcode, dmae->src_addr_lo >> 2,
 443                            dmae->len, dmae->comp_addr_hi, dmae->comp_addr_lo,
 444                            dmae->comp_val);
 445                 break;
 446         }
 447
 448         for (i = 0; i < (sizeof(struct dmae_command)/4); i++)
 449                 DP(msglvl, "DMAE RAW [%02d]: 0x%08x\n",
 450                    i, *(((u32 *)dmae) + i));
 451 }
 452
 453 /* copy command into DMAE command memory and set DMAE command go */
 454 void bnx2x_post_dmae(struct bnx2x *bp, struct dmae_command *dmae, int idx)
 455 {
 456         u32 cmd_offset;
 457         int i;
 458
 459         cmd_offset = (DMAE_REG_CMD_MEM + sizeof(struct dmae_command) * idx);
 460         for (i = 0; i < (sizeof(struct dmae_command)/4); i++) {
 461                 REG_WR(bp, cmd_offset + i*4, *(((u32 *)dmae) + i));
 462         }
 463         REG_WR(bp, dmae_reg_go_c[idx], 1);
 464 }
 465
 466 u32 bnx2x_dmae_opcode_add_comp(u32 opcode, u8 comp_type)
 467 {
 468         return opcode | ((comp_type << DMAE_COMMAND_C_DST_SHIFT) |
 469                            DMAE_CMD_C_ENABLE);
 470 }
 471
 472 u32 bnx2x_dmae_opcode_clr_src_reset(u32 opcode)
 473 {
 474         return opcode & ~DMAE_CMD_SRC_RESET;
 475 }
 476
 477 u32 bnx2x_dmae_opcode(struct bnx2x *bp, u8 src_type, u8 dst_type,
 478                              bool with_comp, u8 comp_type)
 479 {
 480         u32 opcode = 0;
 481
 482         opcode |= ((src_type << DMAE_COMMAND_SRC_SHIFT) |
 483                    (dst_type << DMAE_COMMAND_DST_SHIFT));
 484
 485         opcode |= (DMAE_CMD_SRC_RESET | DMAE_CMD_DST_RESET);
 486
 487         opcode |= (BP_PORT(bp) ? DMAE_CMD_PORT_1 : DMAE_CMD_PORT_0);
 488         opcode |= ((BP_VN(bp) << DMAE_CMD_E1HVN_SHIFT) |
 489                    (BP_VN(bp) << DMAE_COMMAND_DST_VN_SHIFT));
 490         opcode |= (DMAE_COM_SET_ERR << DMAE_COMMAND_ERR_POLICY_SHIFT);
 491
 492 #ifdef __BIG_ENDIAN
 493         opcode |= DMAE_CMD_ENDIANITY_B_DW_SWAP;
 494 #else
 495         opcode |= DMAE_CMD_ENDIANITY_DW_SWAP;
 496 #endif
 497         if (with_comp)
 498                 opcode = bnx2x_dmae_opcode_add_comp(opcode, comp_type);
 499         return opcode;
 500 }
 501
 502 void bnx2x_prep_dmae_with_comp(struct bnx2x *bp,
 503                                       struct dmae_command *dmae,
 504                                       u8 src_type, u8 dst_type)
 505 {
 506         memset(dmae, 0, sizeof(struct dmae_command));
 507
 508         /* set the opcode */
 509         dmae->opcode = bnx2x_dmae_opcode(bp, src_type, dst_type,
 510                                          true, DMAE_COMP_PCI);
 511
 512         /* fill in the completion parameters */
 513         dmae->comp_addr_lo = U64_LO(bnx2x_sp_mapping(bp, wb_comp));
 514         dmae->comp_addr_hi = U64_HI(bnx2x_sp_mapping(bp, wb_comp));
 515         dmae->comp_val = DMAE_COMP_VAL;
 516 }
 517
 518 /* issue a dmae command over the init-channel and wait for completion */
 519 int bnx2x_issue_dmae_with_comp(struct bnx2x *bp, struct dmae_command *dmae,
 520                                u32 *comp)
 521 {
 522         int cnt = CHIP_REV_IS_SLOW(bp) ? (400000) : 4000;
 523         int rc = 0;
 524
 525         bnx2x_dp_dmae(bp, dmae, BNX2X_MSG_DMAE);
 526
 527         /* Lock the dmae channel. Disable BHs to prevent a dead-lock
 528          * as long as this code is called both from syscall context and
 529          * from ndo_set_rx_mode() flow that may be called from BH.
 530          */
 531
 532         spin_lock_bh(&bp->dmae_lock);
 533
 534         /* reset completion */
 535         *comp = 0;
 536
 537         /* post the command on the channel used for initializations */
 538         bnx2x_post_dmae(bp, dmae, INIT_DMAE_C(bp));
 539
 540         /* wait for completion */
 541         udelay(5);
 542         while ((*comp & ~DMAE_PCI_ERR_FLAG) != DMAE_COMP_VAL) {
 543
 544                 if (!cnt ||
 545                     (bp->recovery_state != BNX2X_RECOVERY_DONE &&
 546                      bp->recovery_state != BNX2X_RECOVERY_NIC_LOADING)) {
 547                         BNX2X_ERR("DMAE timeout!\n");
 548                         rc = DMAE_TIMEOUT;
 549                         goto unlock;
 550                 }
 551                 cnt--;
 552                 udelay(50);
 553         }
 554         if (*comp & DMAE_PCI_ERR_FLAG) {
 555                 BNX2X_ERR("DMAE PCI error!\n");
 556                 rc = DMAE_PCI_ERROR;
 557         }
 558
 559 unlock:
 560
 561         spin_unlock_bh(&bp->dmae_lock);
 562
 563         return rc;
 564 }
 565
 566 void bnx2x_write_dmae(struct bnx2x *bp, dma_addr_t dma_addr, u32 dst_addr,
 567                       u32 len32)
 568 {
 569         int rc;
 570         struct dmae_command dmae;
 571
 572         if (!bp->dmae_ready) {
 573                 u32 *data = bnx2x_sp(bp, wb_data[0]);
 574
 575                 if (CHIP_IS_E1(bp))
 576                         bnx2x_init_ind_wr(bp, dst_addr, data, len32);
 577                 else
 578                         bnx2x_init_str_wr(bp, dst_addr, data, len32);
 579                 return;
 580         }
 581
 582         /* set opcode and fixed command fields */
 583         bnx2x_prep_dmae_with_comp(bp, &dmae, DMAE_SRC_PCI, DMAE_DST_GRC);
 584
 585         /* fill in addresses and len */
 586         dmae.src_addr_lo = U64_LO(dma_addr);
 587         dmae.src_addr_hi = U64_HI(dma_addr);
 588         dmae.dst_addr_lo = dst_addr >> 2;
 589         dmae.dst_addr_hi = 0;
 590         dmae.len = len32;
 591
 592         /* issue the command and wait for completion */
 593         rc = bnx2x_issue_dmae_with_comp(bp, &dmae, bnx2x_sp(bp, wb_comp));
 594         if (rc) {
 595                 BNX2X_ERR("DMAE returned failure %d\n", rc);
 596 #ifdef BNX2X_STOP_ON_ERROR
 597                 bnx2x_panic();
 598 #endif
 599         }
 600 }
 601
 602 void bnx2x_read_dmae(struct bnx2x *bp, u32 src_addr, u32 len32)
 603 {
 604         int rc;
 605         struct dmae_command dmae;
 606
 607         if (!bp->dmae_ready) {
 608                 u32 *data = bnx2x_sp(bp, wb_data[0]);
 609                 int i;
 610
 611                 if (CHIP_IS_E1(bp))
 612                         for (i = 0; i < len32; i++)
 613                                 data[i] = bnx2x_reg_rd_ind(bp, src_addr + i*4);
 614                 else
 615                         for (i = 0; i < len32; i++)
 616                                 data[i] = REG_RD(bp, src_addr + i*4);
 617
 618                 return;
 619         }
 620
 621         /* set opcode and fixed command fields */
 622         bnx2x_prep_dmae_with_comp(bp, &dmae, DMAE_SRC_GRC, DMAE_DST_PCI);
 623
 624         /* fill in addresses and len */
 625         dmae.src_addr_lo = src_addr >> 2;
 626         dmae.src_addr_hi = 0;
 627         dmae.dst_addr_lo = U64_LO(bnx2x_sp_mapping(bp, wb_data));
 628         dmae.dst_addr_hi = U64_HI(bnx2x_sp_mapping(bp, wb_data));
 629         dmae.len = len32;
 630
 631         /* issue the command and wait for completion */
 632         rc = bnx2x_issue_dmae_with_comp(bp, &dmae, bnx2x_sp(bp, wb_comp));
 633         if (rc) {
 634                 BNX2X_ERR("DMAE returned failure %d\n", rc);
 635 #ifdef BNX2X_STOP_ON_ERROR
 636                 bnx2x_panic();
 637 #endif
 638         }
 639 }
 640
 641 static void bnx2x_write_dmae_phys_len(struct bnx2x *bp, dma_addr_t phys_addr,
 642                                       u32 addr, u32 len)
 643 {
 644         int dmae_wr_max = DMAE_LEN32_WR_MAX(bp);
 645         int offset = 0;
 646
 647         while (len > dmae_wr_max) {
 648                 bnx2x_write_dmae(bp, phys_addr + offset,
 649                                  addr + offset, dmae_wr_max);
 650                 offset += dmae_wr_max * 4;
 651                 len -= dmae_wr_max;
 652         }
 653
 654         bnx2x_write_dmae(bp, phys_addr + offset, addr + offset, len);
 655 }
 656
 657 enum storms {
 658            XSTORM,
 659            TSTORM,
 660            CSTORM,
 661            USTORM,
 662            MAX_STORMS
 663 };
 664
 665 #define STORMS_NUM 4
 666 #define REGS_IN_ENTRY 4
 667
 668 static inline int bnx2x_get_assert_list_entry(struct bnx2x *bp,
 669                                               enum storms storm,
 670                                               int entry)
 671 {
 672         switch (storm) {
 673         case XSTORM:
 674                 return XSTORM_ASSERT_LIST_OFFSET(entry);
 675         case TSTORM:
 676                 return TSTORM_ASSERT_LIST_OFFSET(entry);
 677         case CSTORM:
 678                 return CSTORM_ASSERT_LIST_OFFSET(entry);
 679         case USTORM:
 680                 return USTORM_ASSERT_LIST_OFFSET(entry);
 681         case MAX_STORMS:
 682         default:
 683                 BNX2X_ERR("unknown storm\n");
 684         }
 685         return -EINVAL;
 686 }
 687
 688 static int bnx2x_mc_assert(struct bnx2x *bp)
 689 {
 690         char last_idx;
 691         int i, j, rc = 0;
 692         enum storms storm;
 693         u32 regs[REGS_IN_ENTRY];
 694         u32 bar_storm_intmem[STORMS_NUM] = {
 695                 BAR_XSTRORM_INTMEM,
 696                 BAR_TSTRORM_INTMEM,
 697                 BAR_CSTRORM_INTMEM,
 698                 BAR_USTRORM_INTMEM
 699         };
 700         u32 storm_assert_list_index[STORMS_NUM] = {
 701                 XSTORM_ASSERT_LIST_INDEX_OFFSET,
 702                 TSTORM_ASSERT_LIST_INDEX_OFFSET,
 703                 CSTORM_ASSERT_LIST_INDEX_OFFSET,
 704                 USTORM_ASSERT_LIST_INDEX_OFFSET
 705         };
 706         char *storms_string[STORMS_NUM] = {
 707                 "XSTORM",
 708                 "TSTORM",
 709                 "CSTORM",
 710                 "USTORM"
 711         };
 712
 713         for (storm = XSTORM; storm < MAX_STORMS; storm++) {
 714                 last_idx = REG_RD8(bp, bar_storm_intmem[storm] +
 715                                    storm_assert_list_index[storm]);
 716                 if (last_idx)
 717                         BNX2X_ERR("%s_ASSERT_LIST_INDEX 0x%x\n",
 718                                   storms_string[storm], last_idx);
 719
 720                 /* print the asserts */
 721                 for (i = 0; i < STROM_ASSERT_ARRAY_SIZE; i++) {
 722                         /* read a single assert entry */
 723                         for (j = 0; j < REGS_IN_ENTRY; j++)
 724                                 regs[j] = REG_RD(bp, bar_storm_intmem[storm] +
 725                                           bnx2x_get_assert_list_entry(bp,
 726                                                                       storm,
 727                                                                       i) +
 728                                           sizeof(u32) * j);
 729
 730                         /* log entry if it contains a valid assert */
 731                         if (regs[0] != COMMON_ASM_INVALID_ASSERT_OPCODE) {
 732                                 BNX2X_ERR("%s_ASSERT_INDEX 0x%x = 0x%08x 0x%08x 0x%08x 0x%08x\n",
 733                                           storms_string[storm], i, regs[3],
 734                                           regs[2], regs[1], regs[0]);
 735                                 rc++;
 736                         } else {
 737                                 break;
 738                         }
 739                 }
 740         }
 741
 742         BNX2X_ERR("Chip Revision: %s, FW Version: %d_%d_%d\n",
 743                   CHIP_IS_E1(bp) ? "everest1" :
 744                   CHIP_IS_E1H(bp) ? "everest1h" :
 745                   CHIP_IS_E2(bp) ? "everest2" : "everest3",
 746                   BCM_5710_FW_MAJOR_VERSION,
 747                   BCM_5710_FW_MINOR_VERSION,
 748                   BCM_5710_FW_REVISION_VERSION);
 749
 750         return rc;
 751 }
 752
 753 #define MCPR_TRACE_BUFFER_SIZE  (0x800)
 754 #define SCRATCH_BUFFER_SIZE(bp) \
 755         (CHIP_IS_E1(bp) ? 0x10000 : (CHIP_IS_E1H(bp) ? 0x20000 : 0x28000))
 756
 757 void bnx2x_fw_dump_lvl(struct bnx2x *bp, const char *lvl)
 758 {
 759         u32 addr, val;
 760         u32 mark, offset;
 761         __be32 data[9];
 762         int word;
 763         u32 trace_shmem_base;
 764         if (BP_NOMCP(bp)) {
 765                 BNX2X_ERR("NO MCP - can not dump\n");
 766                 return;
 767         }
 768         netdev_printk(lvl, bp->dev, "bc %d.%d.%d\n",
 769                 (bp->common.bc_ver & 0xff0000) >> 16,
 770                 (bp->common.bc_ver & 0xff00) >> 8,
 771                 (bp->common.bc_ver & 0xff));
 772
 773         val = REG_RD(bp, MCP_REG_MCPR_CPU_PROGRAM_COUNTER);
 774         if (val == REG_RD(bp, MCP_REG_MCPR_CPU_PROGRAM_COUNTER))
 775                 BNX2X_ERR("%s" "MCP PC at 0x%x\n", lvl, val);
 776
 777         if (BP_PATH(bp) == 0)
 778                 trace_shmem_base = bp->common.shmem_base;
 779         else
 780                 trace_shmem_base = SHMEM2_RD(bp, other_shmem_base_addr);
 781
 782         /* sanity */
 783         if (trace_shmem_base < MCPR_SCRATCH_BASE(bp) + MCPR_TRACE_BUFFER_SIZE ||
 784             trace_shmem_base >= MCPR_SCRATCH_BASE(bp) +
 785                                 SCRATCH_BUFFER_SIZE(bp)) {
 786                 BNX2X_ERR("Unable to dump trace buffer (mark %x)\n",
 787                           trace_shmem_base);
 788                 return;
 789         }
 790
 791         addr = trace_shmem_base - MCPR_TRACE_BUFFER_SIZE;
 792
 793         /* validate TRCB signature */
 794         mark = REG_RD(bp, addr);
 795         if (mark != MFW_TRACE_SIGNATURE) {
 796                 BNX2X_ERR("Trace buffer signature is missing.");
 797                 return ;
 798         }
 799
 800         /* read cyclic buffer pointer */
 801         addr += 4;
 802         mark = REG_RD(bp, addr);
 803         mark = MCPR_SCRATCH_BASE(bp) + ((mark + 0x3) & ~0x3) - 0x08000000;
 804         if (mark >= trace_shmem_base || mark < addr + 4) {
 805                 BNX2X_ERR("Mark doesn't fall inside Trace Buffer\n");
 806                 return;
 807         }
 808         printk("%s" "begin fw dump (mark 0x%x)\n", lvl, mark);
 809
 810         printk("%s", lvl);
 811
 812         /* dump buffer after the mark */
 813         for (offset = mark; offset < trace_shmem_base; offset += 0x8*4) {
 814                 for (word = 0; word < 8; word++)
 815                         data[word] = htonl(REG_RD(bp, offset + 4*word));
 816                 data[8] = 0x0;
 817                 pr_cont("%s", (char *)data);
 818         }
 819
 820         /* dump buffer before the mark */
 821         for (offset = addr + 4; offset <= mark; offset += 0x8*4) {
 822                 for (word = 0; word < 8; word++)
 823                         data[word] = htonl(REG_RD(bp, offset + 4*word));
 824                 data[8] = 0x0;
 825                 pr_cont("%s", (char *)data);
 826         }
 827         printk("%s" "end of fw dump\n", lvl);
 828 }
 829
 830 static void bnx2x_fw_dump(struct bnx2x *bp)
 831 {
 832         bnx2x_fw_dump_lvl(bp, KERN_ERR);
 833 }
 834
 835 static void bnx2x_hc_int_disable(struct bnx2x *bp)
 836 {
 837         int port = BP_PORT(bp);
 838         u32 addr = port ? HC_REG_CONFIG_1 : HC_REG_CONFIG_0;
 839         u32 val = REG_RD(bp, addr);
 840
 841         /* in E1 we must use only PCI configuration space to disable
 842          * MSI/MSIX capability
 843          * It's forbidden to disable IGU_PF_CONF_MSI_MSIX_EN in HC block
 844          */
 845         if (CHIP_IS_E1(bp)) {
 846                 /* Since IGU_PF_CONF_MSI_MSIX_EN still always on
 847                  * Use mask register to prevent from HC sending interrupts
 848                  * after we exit the function
 849                  */
 850                 REG_WR(bp, HC_REG_INT_MASK + port*4, 0);
 851
 852                 val &= ~(HC_CONFIG_0_REG_SINGLE_ISR_EN_0 |
 853                          HC_CONFIG_0_REG_INT_LINE_EN_0 |
 854                          HC_CONFIG_0_REG_ATTN_BIT_EN_0);
 855         } else
 856                 val &= ~(HC_CONFIG_0_REG_SINGLE_ISR_EN_0 |
 857                          HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0 |
 858                          HC_CONFIG_0_REG_INT_LINE_EN_0 |
 859                          HC_CONFIG_0_REG_ATTN_BIT_EN_0);
 860
 861         DP(NETIF_MSG_IFDOWN,
 862            "write %x to HC %d (addr 0x%x)\n",
 863            val, port, addr);
 864
 865         /* flush all outstanding writes */
 866         mmiowb();
 867
 868         REG_WR(bp, addr, val);
 869         if (REG_RD(bp, addr) != val)
 870                 BNX2X_ERR("BUG! Proper val not read from IGU!\n");
 871 }
 872
 873 static void bnx2x_igu_int_disable(struct bnx2x *bp)
 874 {
 875         u32 val = REG_RD(bp, IGU_REG_PF_CONFIGURATION);
 876
 877         val &= ~(IGU_PF_CONF_MSI_MSIX_EN |
 878                  IGU_PF_CONF_INT_LINE_EN |
 879                  IGU_PF_CONF_ATTN_BIT_EN);
 880
 881         DP(NETIF_MSG_IFDOWN, "write %x to IGU\n", val);
 882
 883         /* flush all outstanding writes */
 884         mmiowb();
 885
 886         REG_WR(bp, IGU_REG_PF_CONFIGURATION, val);
 887         if (REG_RD(bp, IGU_REG_PF_CONFIGURATION) != val)
 888                 BNX2X_ERR("BUG! Proper val not read from IGU!\n");
 889 }
 890
 891 static void bnx2x_int_disable(struct bnx2x *bp)
 892 {
 893         if (bp->common.int_block == INT_BLOCK_HC)
 894                 bnx2x_hc_int_disable(bp);
 895         else
 896                 bnx2x_igu_int_disable(bp);
 897 }
 898
 899 void bnx2x_panic_dump(struct bnx2x *bp, bool disable_int)
 900 {
 901         int i;
 902         u16 j;
 903         struct hc_sp_status_block_data sp_sb_data;
 904         int func = BP_FUNC(bp);
 905 #ifdef BNX2X_STOP_ON_ERROR
 906         u16 start = 0, end = 0;
 907         u8 cos;
 908 #endif
 909         if (IS_PF(bp) && disable_int)
 910                 bnx2x_int_disable(bp);
 911
 912         bp->stats_state = STATS_STATE_DISABLED;
 913         bp->eth_stats.unrecoverable_error++;
 914         DP(BNX2X_MSG_STATS, "stats_state - DISABLED\n");
 915
 916         BNX2X_ERR("begin crash dump -----------------\n");
 917
 918         /* Indices */
 919         /* Common */
 920         if (IS_PF(bp)) {
 921                 struct host_sp_status_block *def_sb = bp->def_status_blk;
 922                 int data_size, cstorm_offset;
 923
 924                 BNX2X_ERR("def_idx(0x%x)  def_att_idx(0x%x)  attn_state(0x%x)  spq_prod_idx(0x%x) next_stats_cnt(0x%x)\n",
 925                           bp->def_idx, bp->def_att_idx, bp->attn_state,
 926                           bp->spq_prod_idx, bp->stats_counter);
 927                 BNX2X_ERR("DSB: attn bits(0x%x)  ack(0x%x)  id(0x%x)  idx(0x%x)\n",
 928                           def_sb->atten_status_block.attn_bits,
 929                           def_sb->atten_status_block.attn_bits_ack,
 930                           def_sb->atten_status_block.status_block_id,
 931                           def_sb->atten_status_block.attn_bits_index);
 932                 BNX2X_ERR("     def (");
 933                 for (i = 0; i < HC_SP_SB_MAX_INDICES; i++)
 934                         pr_cont("0x%x%s",
 935                                 def_sb->sp_sb.index_values[i],
 936                                 (i == HC_SP_SB_MAX_INDICES - 1) ? ")  " : " ");
 937
 938                 data_size = sizeof(struct hc_sp_status_block_data) /
 939                             sizeof(u32);
 940                 cstorm_offset = CSTORM_SP_STATUS_BLOCK_DATA_OFFSET(func);
 941                 for (i = 0; i < data_size; i++)
 942                         *((u32 *)&sp_sb_data + i) =
 943                                 REG_RD(bp, BAR_CSTRORM_INTMEM + cstorm_offset +
 944                                            i * sizeof(u32));
 945
 946                 pr_cont("igu_sb_id(0x%x)  igu_seg_id(0x%x) pf_id(0x%x)  vnic_id(0x%x)  vf_id(0x%x)  vf_valid (0x%x) state(0x%x)\n",
 947                         sp_sb_data.igu_sb_id,
 948                         sp_sb_data.igu_seg_id,
 949                         sp_sb_data.p_func.pf_id,
 950                         sp_sb_data.p_func.vnic_id,
 951                         sp_sb_data.p_func.vf_id,
 952                         sp_sb_data.p_func.vf_valid,
 953                         sp_sb_data.state);
 954         }
 955
 956         for_each_eth_queue(bp, i) {
 957                 struct bnx2x_fastpath *fp = &bp->fp[i];
 958                 int loop;
 959                 struct hc_status_block_data_e2 sb_data_e2;
 960                 struct hc_status_block_data_e1x sb_data_e1x;
 961                 struct hc_status_block_sm  *hc_sm_p =
 962                         CHIP_IS_E1x(bp) ?
 963                         sb_data_e1x.common.state_machine :
 964                         sb_data_e2.common.state_machine;
 965                 struct hc_index_data *hc_index_p =
 966                         CHIP_IS_E1x(bp) ?
 967                         sb_data_e1x.index_data :
 968                         sb_data_e2.index_data;
 969                 u8 data_size, cos;
 970                 u32 *sb_data_p;
 971                 struct bnx2x_fp_txdata txdata;
 972
 973                 if (!bp->fp)
 974                         break;
 975
 976                 if (!fp->rx_cons_sb)
 977                         continue;
 978
 979                 /* Rx */
 980                 BNX2X_ERR("fp%d: rx_bd_prod(0x%x)  rx_bd_cons(0x%x)  rx_comp_prod(0x%x)  rx_comp_cons(0x%x)  *rx_cons_sb(0x%x)\n",
 981                           i, fp->rx_bd_prod, fp->rx_bd_cons,
 982                           fp->rx_comp_prod,
 983                           fp->rx_comp_cons, le16_to_cpu(*fp->rx_cons_sb));
 984                 BNX2X_ERR("     rx_sge_prod(0x%x)  last_max_sge(0x%x)  fp_hc_idx(0x%x)\n",
 985                           fp->rx_sge_prod, fp->last_max_sge,
 986                           le16_to_cpu(fp->fp_hc_idx));
 987
 988                 /* Tx */
 989                 for_each_cos_in_tx_queue(fp, cos)
 990                 {
 991                         if (!fp->txdata_ptr[cos])
 992                                 break;
 993
 994                         txdata = *fp->txdata_ptr[cos];
 995
 996                         if (!txdata.tx_cons_sb)
 997                                 continue;
 998
 999                         BNX2X_ERR("fp%d: tx_pkt_prod(0x%x)  tx_pkt_cons(0x%x)  tx_bd_prod(0x%x)  tx_bd_cons(0x%x)  *tx_cons_sb(0x%x)\n",
1000                                   i, txdata.tx_pkt_prod,
1001                                   txdata.tx_pkt_cons, txdata.tx_bd_prod,
1002                                   txdata.tx_bd_cons,
1003                                   le16_to_cpu(*txdata.tx_cons_sb));
1004                 }
1005
1006                 loop = CHIP_IS_E1x(bp) ?
1007                         HC_SB_MAX_INDICES_E1X : HC_SB_MAX_INDICES_E2;
1008
1009                 /* host sb data */
1010
1011                 if (IS_FCOE_FP(fp))
1012                         continue;
1013
1014                 BNX2X_ERR("     run indexes (");
1015                 for (j = 0; j < HC_SB_MAX_SM; j++)
1016                         pr_cont("0x%x%s",
1017                                fp->sb_running_index[j],
1018                                (j == HC_SB_MAX_SM - 1) ? ")" : " ");
1019
1020                 BNX2X_ERR("     indexes (");
1021                 for (j = 0; j < loop; j++)
1022                         pr_cont("0x%x%s",
1023                                fp->sb_index_values[j],
1024                                (j == loop - 1) ? ")" : " ");
1025
1026                 /* VF cannot access FW refelection for status block */
1027                 if (IS_VF(bp))
1028                         continue;
1029
1030                 /* fw sb data */
1031                 data_size = CHIP_IS_E1x(bp) ?
1032                         sizeof(struct hc_status_block_data_e1x) :
1033                         sizeof(struct hc_status_block_data_e2);
1034                 data_size /= sizeof(u32);
1035                 sb_data_p = CHIP_IS_E1x(bp) ?
1036                         (u32 *)&sb_data_e1x :
1037                         (u32 *)&sb_data_e2;
1038                 /* copy sb data in here */
1039                 for (j = 0; j < data_size; j++)
1040                         *(sb_data_p + j) = REG_RD(bp, BAR_CSTRORM_INTMEM +
1041                                 CSTORM_STATUS_BLOCK_DATA_OFFSET(fp->fw_sb_id) +
1042                                 j * sizeof(u32));
1043
1044                 if (!CHIP_IS_E1x(bp)) {
1045                         pr_cont("pf_id(0x%x)  vf_id(0x%x)  vf_valid(0x%x) vnic_id(0x%x)  same_igu_sb_1b(0x%x) state(0x%x)\n",
1046                                 sb_data_e2.common.p_func.pf_id,
1047                                 sb_data_e2.common.p_func.vf_id,
1048                                 sb_data_e2.common.p_func.vf_valid,
1049                                 sb_data_e2.common.p_func.vnic_id,
1050                                 sb_data_e2.common.same_igu_sb_1b,
1051                                 sb_data_e2.common.state);
1052                 } else {
1053                         pr_cont("pf_id(0x%x)  vf_id(0x%x)  vf_valid(0x%x) vnic_id(0x%x)  same_igu_sb_1b(0x%x) state(0x%x)\n",
1054                                 sb_data_e1x.common.p_func.pf_id,
1055                                 sb_data_e1x.common.p_func.vf_id,
1056                                 sb_data_e1x.common.p_func.vf_valid,
1057                                 sb_data_e1x.common.p_func.vnic_id,
1058                                 sb_data_e1x.common.same_igu_sb_1b,
1059                                 sb_data_e1x.common.state);
1060                 }
1061
1062                 /* SB_SMs data */
1063                 for (j = 0; j < HC_SB_MAX_SM; j++) {
1064                         pr_cont("SM[%d] __flags (0x%x) igu_sb_id (0x%x)  igu_seg_id(0x%x) time_to_expire (0x%x) timer_value(0x%x)\n",
1065                                 j, hc_sm_p[j].__flags,
1066                                 hc_sm_p[j].igu_sb_id,
1067                                 hc_sm_p[j].igu_seg_id,
1068                                 hc_sm_p[j].time_to_expire,
1069                                 hc_sm_p[j].timer_value);
1070                 }
1071
1072                 /* Indices data */
1073                 for (j = 0; j < loop; j++) {
1074                         pr_cont("INDEX[%d] flags (0x%x) timeout (0x%x)\n", j,
1075                                hc_index_p[j].flags,
1076                                hc_index_p[j].timeout);
1077                 }
1078         }
1079
1080 #ifdef BNX2X_STOP_ON_ERROR
1081         if (IS_PF(bp)) {
1082                 /* event queue */
1083                 BNX2X_ERR("eq cons %x prod %x\n", bp->eq_cons, bp->eq_prod);
1084                 for (i = 0; i < NUM_EQ_DESC; i++) {
1085                         u32 *data = (u32 *)&bp->eq_ring[i].message.data;
1086
1087                         BNX2X_ERR("event queue [%d]: header: opcode %d, error %d\n",
1088                                   i, bp->eq_ring[i].message.opcode,
1089                                   bp->eq_ring[i].message.error);
1090                         BNX2X_ERR("data: %x %x %x\n",
1091                                   data[0], data[1], data[2]);
1092                 }
1093         }
1094
1095         /* Rings */
1096         /* Rx */
1097         for_each_valid_rx_queue(bp, i) {
1098                 struct bnx2x_fastpath *fp = &bp->fp[i];
1099
1100                 if (!bp->fp)
1101                         break;
1102
1103                 if (!fp->rx_cons_sb)
1104                         continue;
1105
1106                 start = RX_BD(le16_to_cpu(*fp->rx_cons_sb) - 10);
1107                 end = RX_BD(le16_to_cpu(*fp->rx_cons_sb) + 503);
1108                 for (j = start; j != end; j = RX_BD(j + 1)) {
1109                         u32 *rx_bd = (u32 *)&fp->rx_desc_ring[j];
1110                         struct sw_rx_bd *sw_bd = &fp->rx_buf_ring[j];
1111
1112                         BNX2X_ERR("fp%d: rx_bd[%x]=[%x:%x]  sw_bd=[%p]\n",
1113                                   i, j, rx_bd[1], rx_bd[0], sw_bd->data);
1114                 }
1115
1116                 start = RX_SGE(fp->rx_sge_prod);
1117                 end = RX_SGE(fp->last_max_sge);
1118                 for (j = start; j != end; j = RX_SGE(j + 1)) {
1119                         u32 *rx_sge = (u32 *)&fp->rx_sge_ring[j];
1120                         struct sw_rx_page *sw_page = &fp->rx_page_ring[j];
1121
1122                         BNX2X_ERR("fp%d: rx_sge[%x]=[%x:%x]  sw_page=[%p]\n",
1123                                   i, j, rx_sge[1], rx_sge[0], sw_page->page);
1124                 }
1125
1126                 start = RCQ_BD(fp->rx_comp_cons - 10);
1127                 end = RCQ_BD(fp->rx_comp_cons + 503);
1128                 for (j = start; j != end; j = RCQ_BD(j + 1)) {
1129                         u32 *cqe = (u32 *)&fp->rx_comp_ring[j];
1130
1131                         BNX2X_ERR("fp%d: cqe[%x]=[%x:%x:%x:%x]\n",
1132                                   i, j, cqe[0], cqe[1], cqe[2], cqe[3]);
1133                 }
1134         }
1135
1136         /* Tx */
1137         for_each_valid_tx_queue(bp, i) {
1138                 struct bnx2x_fastpath *fp = &bp->fp[i];
1139
1140                 if (!bp->fp)
1141                         break;
1142
1143                 for_each_cos_in_tx_queue(fp, cos) {
1144                         struct bnx2x_fp_txdata *txdata = fp->txdata_ptr[cos];
1145
1146                         if (!fp->txdata_ptr[cos])
1147                                 break;
1148
1149                         if (!txdata->tx_cons_sb)
1150                                 continue;
1151
1152                         start = TX_BD(le16_to_cpu(*txdata->tx_cons_sb) - 10);
1153                         end = TX_BD(le16_to_cpu(*txdata->tx_cons_sb) + 245);
1154                         for (j = start; j != end; j = TX_BD(j + 1)) {
1155                                 struct sw_tx_bd *sw_bd =
1156                                         &txdata->tx_buf_ring[j];
1157
1158                                 BNX2X_ERR("fp%d: txdata %d, packet[%x]=[%p,%x]\n",
1159                                           i, cos, j, sw_bd->skb,
1160                                           sw_bd->first_bd);
1161                         }
1162
1163                         start = TX_BD(txdata->tx_bd_cons - 10);
1164                         end = TX_BD(txdata->tx_bd_cons + 254);
1165                         for (j = start; j != end; j = TX_BD(j + 1)) {
1166                                 u32 *tx_bd = (u32 *)&txdata->tx_desc_ring[j];
1167
1168                                 BNX2X_ERR("fp%d: txdata %d, tx_bd[%x]=[%x:%x:%x:%x]\n",
1169                                           i, cos, j, tx_bd[0], tx_bd[1],
1170                                           tx_bd[2], tx_bd[3]);
1171                         }
1172                 }
1173         }
1174 #endif
1175         if (IS_PF(bp)) {
1176                 bnx2x_fw_dump(bp);
1177                 bnx2x_mc_assert(bp);
1178         }
1179         BNX2X_ERR("end crash dump -----------------\n");
1180 }
1181
1182 /*
1183  * FLR Support for E2
1184  *
1185  * bnx2x_pf_flr_clnup() is called during nic_load in the per function HW
1186  * initialization.
1187  */
1188 #define FLR_WAIT_USEC           10000   /* 10 milliseconds */
1189 #define FLR_WAIT_INTERVAL       50      /* usec */
1190 #define FLR_POLL_CNT            (FLR_WAIT_USEC/FLR_WAIT_INTERVAL) /* 200 */
1191
1192 struct pbf_pN_buf_regs {
1193         int pN;
1194         u32 init_crd;
1195         u32 crd;
1196         u32 crd_freed;
1197 };
1198
1199 struct pbf_pN_cmd_regs {
1200         int pN;
1201         u32 lines_occup;
1202         u32 lines_freed;
1203 };
1204
1205 static void bnx2x_pbf_pN_buf_flushed(struct bnx2x *bp,
1206                                      struct pbf_pN_buf_regs *regs,
1207                                      u32 poll_count)
1208 {
1209         u32 init_crd, crd, crd_start, crd_freed, crd_freed_start;
1210         u32 cur_cnt = poll_count;
1211
1212         crd_freed = crd_freed_start = REG_RD(bp, regs->crd_freed);
1213         crd = crd_start = REG_RD(bp, regs->crd);
1214         init_crd = REG_RD(bp, regs->init_crd);
1215
1216         DP(BNX2X_MSG_SP, "INIT CREDIT[%d] : %x\n", regs->pN, init_crd);
1217         DP(BNX2X_MSG_SP, "CREDIT[%d]      : s:%x\n", regs->pN, crd);
1218         DP(BNX2X_MSG_SP, "CREDIT_FREED[%d]: s:%x\n", regs->pN, crd_freed);
1219
1220         while ((crd != init_crd) && ((u32)SUB_S32(crd_freed, crd_freed_start) <
1221                (init_crd - crd_start))) {
1222                 if (cur_cnt--) {
1223                         udelay(FLR_WAIT_INTERVAL);
1224                         crd = REG_RD(bp, regs->crd);
1225                         crd_freed = REG_RD(bp, regs->crd_freed);
1226                 } else {
1227                         DP(BNX2X_MSG_SP, "PBF tx buffer[%d] timed out\n",
1228                            regs->pN);
1229                         DP(BNX2X_MSG_SP, "CREDIT[%d]      : c:%x\n",
1230                            regs->pN, crd);
1231                         DP(BNX2X_MSG_SP, "CREDIT_FREED[%d]: c:%x\n",
1232                            regs->pN, crd_freed);
1233                         break;
1234                 }
1235         }
1236         DP(BNX2X_MSG_SP, "Waited %d*%d usec for PBF tx buffer[%d]\n",
1237            poll_count-cur_cnt, FLR_WAIT_INTERVAL, regs->pN);
1238 }
1239
1240 static void bnx2x_pbf_pN_cmd_flushed(struct bnx2x *bp,
1241                                      struct pbf_pN_cmd_regs *regs,
1242                                      u32 poll_count)
1243 {
1244         u32 occup, to_free, freed, freed_start;
1245         u32 cur_cnt = poll_count;
1246
1247         occup = to_free = REG_RD(bp, regs->lines_occup);
1248         freed = freed_start = REG_RD(bp, regs->lines_freed);
1249
1250         DP(BNX2X_MSG_SP, "OCCUPANCY[%d]   : s:%x\n", regs->pN, occup);
1251         DP(BNX2X_MSG_SP, "LINES_FREED[%d] : s:%x\n", regs->pN, freed);
1252
1253         while (occup && ((u32)SUB_S32(freed, freed_start) < to_free)) {
1254                 if (cur_cnt--) {
1255                         udelay(FLR_WAIT_INTERVAL);
1256                         occup = REG_RD(bp, regs->lines_occup);
1257                         freed = REG_RD(bp, regs->lines_freed);
1258                 } else {
1259                         DP(BNX2X_MSG_SP, "PBF cmd queue[%d] timed out\n",
1260                            regs->pN);
1261                         DP(BNX2X_MSG_SP, "OCCUPANCY[%d]   : s:%x\n",
1262                            regs->pN, occup);
1263                         DP(BNX2X_MSG_SP, "LINES_FREED[%d] : s:%x\n",
1264                            regs->pN, freed);
1265                         break;
1266                 }
1267         }
1268         DP(BNX2X_MSG_SP, "Waited %d*%d usec for PBF cmd queue[%d]\n",
1269            poll_count-cur_cnt, FLR_WAIT_INTERVAL, regs->pN);
1270 }
1271
1272 static u32 bnx2x_flr_clnup_reg_poll(struct bnx2x *bp, u32 reg,
1273                                     u32 expected, u32 poll_count)
1274 {
1275         u32 cur_cnt = poll_count;
1276         u32 val;
1277
1278         while ((val = REG_RD(bp, reg)) != expected && cur_cnt--)
1279                 udelay(FLR_WAIT_INTERVAL);
1280
1281         return val;
1282 }
1283
1284 int bnx2x_flr_clnup_poll_hw_counter(struct bnx2x *bp, u32 reg,
1285                                     char *msg, u32 poll_cnt)
1286 {
1287         u32 val = bnx2x_flr_clnup_reg_poll(bp, reg, 0, poll_cnt);
1288         if (val != 0) {
1289                 BNX2X_ERR("%s usage count=%d\n", msg, val);
1290                 return 1;
1291         }
1292         return 0;
1293 }
1294
1295 /* Common routines with VF FLR cleanup */
1296 u32 bnx2x_flr_clnup_poll_count(struct bnx2x *bp)
1297 {
1298         /* adjust polling timeout */
1299         if (CHIP_REV_IS_EMUL(bp))
1300                 return FLR_POLL_CNT * 2000;
1301
1302         if (CHIP_REV_IS_FPGA(bp))
1303                 return FLR_POLL_CNT * 120;
1304
1305         return FLR_POLL_CNT;
1306 }
1307
1308 void bnx2x_tx_hw_flushed(struct bnx2x *bp, u32 poll_count)
1309 {
1310         struct pbf_pN_cmd_regs cmd_regs[] = {
1311                 {0, (CHIP_IS_E3B0(bp)) ?
1312                         PBF_REG_TQ_OCCUPANCY_Q0 :
1313                         PBF_REG_P0_TQ_OCCUPANCY,
1314                     (CHIP_IS_E3B0(bp)) ?
1315                         PBF_REG_TQ_LINES_FREED_CNT_Q0 :
1316                         PBF_REG_P0_TQ_LINES_FREED_CNT},
1317                 {1, (CHIP_IS_E3B0(bp)) ?
1318                         PBF_REG_TQ_OCCUPANCY_Q1 :
1319                         PBF_REG_P1_TQ_OCCUPANCY,
1320                     (CHIP_IS_E3B0(bp)) ?
1321                         PBF_REG_TQ_LINES_FREED_CNT_Q1 :
1322                         PBF_REG_P1_TQ_LINES_FREED_CNT},
1323                 {4, (CHIP_IS_E3B0(bp)) ?
1324                         PBF_REG_TQ_OCCUPANCY_LB_Q :
1325                         PBF_REG_P4_TQ_OCCUPANCY,
1326                     (CHIP_IS_E3B0(bp)) ?
1327                         PBF_REG_TQ_LINES_FREED_CNT_LB_Q :
1328                         PBF_REG_P4_TQ_LINES_FREED_CNT}
1329         };
1330
1331         struct pbf_pN_buf_regs buf_regs[] = {
1332                 {0, (CHIP_IS_E3B0(bp)) ?
1333                         PBF_REG_INIT_CRD_Q0 :
1334                         PBF_REG_P0_INIT_CRD ,
1335                     (CHIP_IS_E3B0(bp)) ?
1336                         PBF_REG_CREDIT_Q0 :
1337                         PBF_REG_P0_CREDIT,
1338                     (CHIP_IS_E3B0(bp)) ?
1339                         PBF_REG_INTERNAL_CRD_FREED_CNT_Q0 :
1340                         PBF_REG_P0_INTERNAL_CRD_FREED_CNT},
1341                 {1, (CHIP_IS_E3B0(bp)) ?
1342                         PBF_REG_INIT_CRD_Q1 :
1343                         PBF_REG_P1_INIT_CRD,
1344                     (CHIP_IS_E3B0(bp)) ?
1345                         PBF_REG_CREDIT_Q1 :
1346                         PBF_REG_P1_CREDIT,
1347                     (CHIP_IS_E3B0(bp)) ?
1348                         PBF_REG_INTERNAL_CRD_FREED_CNT_Q1 :
1349                         PBF_REG_P1_INTERNAL_CRD_FREED_CNT},
1350                 {4, (CHIP_IS_E3B0(bp)) ?
1351                         PBF_REG_INIT_CRD_LB_Q :
1352                         PBF_REG_P4_INIT_CRD,
1353                     (CHIP_IS_E3B0(bp)) ?
1354                         PBF_REG_CREDIT_LB_Q :
1355                         PBF_REG_P4_CREDIT,
1356                     (CHIP_IS_E3B0(bp)) ?
1357                         PBF_REG_INTERNAL_CRD_FREED_CNT_LB_Q :
1358                         PBF_REG_P4_INTERNAL_CRD_FREED_CNT},
1359         };
1360
1361         int i;
1362
1363         /* Verify the command queues are flushed P0, P1, P4 */
1364         for (i = 0; i < ARRAY_SIZE(cmd_regs); i++)
1365                 bnx2x_pbf_pN_cmd_flushed(bp, &cmd_regs[i], poll_count);
1366
1367         /* Verify the transmission buffers are flushed P0, P1, P4 */
1368         for (i = 0; i < ARRAY_SIZE(buf_regs); i++)
1369                 bnx2x_pbf_pN_buf_flushed(bp, &buf_regs[i], poll_count);
1370 }
1371
1372 #define OP_GEN_PARAM(param) \
1373         (((param) << SDM_OP_GEN_COMP_PARAM_SHIFT) & SDM_OP_GEN_COMP_PARAM)
1374
1375 #define OP_GEN_TYPE(type) \
1376         (((type) << SDM_OP_GEN_COMP_TYPE_SHIFT) & SDM_OP_GEN_COMP_TYPE)
1377
1378 #define OP_GEN_AGG_VECT(index) \
1379         (((index) << SDM_OP_GEN_AGG_VECT_IDX_SHIFT) & SDM_OP_GEN_AGG_VECT_IDX)
1380
1381 int bnx2x_send_final_clnup(struct bnx2x *bp, u8 clnup_func, u32 poll_cnt)
1382 {
1383         u32 op_gen_command = 0;
1384         u32 comp_addr = BAR_CSTRORM_INTMEM +
1385                         CSTORM_FINAL_CLEANUP_COMPLETE_OFFSET(clnup_func);
1386         int ret = 0;
1387
1388         if (REG_RD(bp, comp_addr)) {
1389                 BNX2X_ERR("Cleanup complete was not 0 before sending\n");
1390                 return 1;
1391         }
1392
1393         op_gen_command |= OP_GEN_PARAM(XSTORM_AGG_INT_FINAL_CLEANUP_INDEX);
1394         op_gen_command |= OP_GEN_TYPE(XSTORM_AGG_INT_FINAL_CLEANUP_COMP_TYPE);
1395         op_gen_command |= OP_GEN_AGG_VECT(clnup_func);
1396         op_gen_command |= 1 << SDM_OP_GEN_AGG_VECT_IDX_VALID_SHIFT;
1397
1398         DP(BNX2X_MSG_SP, "sending FW Final cleanup\n");
1399         REG_WR(bp, XSDM_REG_OPERATION_GEN, op_gen_command);
1400
1401         if (bnx2x_flr_clnup_reg_poll(bp, comp_addr, 1, poll_cnt) != 1) {
1402                 BNX2X_ERR("FW final cleanup did not succeed\n");
1403                 DP(BNX2X_MSG_SP, "At timeout completion address contained %x\n",
1404                    (REG_RD(bp, comp_addr)));
1405                 bnx2x_panic();
1406                 return 1;
1407         }
1408         /* Zero completion for next FLR */
1409         REG_WR(bp, comp_addr, 0);
1410
1411         return ret;
1412 }
1413
1414 u8 bnx2x_is_pcie_pending(struct pci_dev *dev)
1415 {
1416         u16 status;
1417
1418         pcie_capability_read_word(dev, PCI_EXP_DEVSTA, &status);
1419         return status & PCI_EXP_DEVSTA_TRPND;
1420 }
1421
1422 /* PF FLR specific routines
1423 */
1424 static int bnx2x_poll_hw_usage_counters(struct bnx2x *bp, u32 poll_cnt)
1425 {
1426         /* wait for CFC PF usage-counter to zero (includes all the VFs) */
1427         if (bnx2x_flr_clnup_poll_hw_counter(bp,
1428                         CFC_REG_NUM_LCIDS_INSIDE_PF,
1429                         "CFC PF usage counter timed out",
1430                         poll_cnt))
1431                 return 1;
1432
1433         /* Wait for DQ PF usage-counter to zero (until DQ cleanup) */
1434         if (bnx2x_flr_clnup_poll_hw_counter(bp,
1435                         DORQ_REG_PF_USAGE_CNT,
1436                         "DQ PF usage counter timed out",
1437                         poll_cnt))
1438                 return 1;
1439
1440         /* Wait for QM PF usage-counter to zero (until DQ cleanup) */
1441         if (bnx2x_flr_clnup_poll_hw_counter(bp,
1442                         QM_REG_PF_USG_CNT_0 + 4*BP_FUNC(bp),
1443                         "QM PF usage counter timed out",
1444                         poll_cnt))
1445                 return 1;
1446
1447         /* Wait for Timer PF usage-counters to zero (until DQ cleanup) */
1448         if (bnx2x_flr_clnup_poll_hw_counter(bp,
1449                         TM_REG_LIN0_VNIC_UC + 4*BP_PORT(bp),
1450                         "Timers VNIC usage counter timed out",
1451                         poll_cnt))
1452                 return 1;
1453         if (bnx2x_flr_clnup_poll_hw_counter(bp,
1454                         TM_REG_LIN0_NUM_SCANS + 4*BP_PORT(bp),
1455                         "Timers NUM_SCANS usage counter timed out",
1456                         poll_cnt))
1457                 return 1;
1458
1459         /* Wait DMAE PF usage counter to zero */
1460         if (bnx2x_flr_clnup_poll_hw_counter(bp,
1461                         dmae_reg_go_c[INIT_DMAE_C(bp)],
1462                         "DMAE command register timed out",
1463                         poll_cnt))
1464                 return 1;
1465
1466         return 0;
1467 }
1468
1469 static void bnx2x_hw_enable_status(struct bnx2x *bp)
1470 {
1471         u32 val;
1472
1473         val = REG_RD(bp, CFC_REG_WEAK_ENABLE_PF);
1474         DP(BNX2X_MSG_SP, "CFC_REG_WEAK_ENABLE_PF is 0x%x\n", val);
1475
1476         val = REG_RD(bp, PBF_REG_DISABLE_PF);
1477         DP(BNX2X_MSG_SP, "PBF_REG_DISABLE_PF is 0x%x\n", val);
1478
1479         val = REG_RD(bp, IGU_REG_PCI_PF_MSI_EN);
1480         DP(BNX2X_MSG_SP, "IGU_REG_PCI_PF_MSI_EN is 0x%x\n", val);
1481
1482         val = REG_RD(bp, IGU_REG_PCI_PF_MSIX_EN);
1483         DP(BNX2X_MSG_SP, "IGU_REG_PCI_PF_MSIX_EN is 0x%x\n", val);
1484
1485         val = REG_RD(bp, IGU_REG_PCI_PF_MSIX_FUNC_MASK);
1486         DP(BNX2X_MSG_SP, "IGU_REG_PCI_PF_MSIX_FUNC_MASK is 0x%x\n", val);
1487
1488         val = REG_RD(bp, PGLUE_B_REG_SHADOW_BME_PF_7_0_CLR);
1489         DP(BNX2X_MSG_SP, "PGLUE_B_REG_SHADOW_BME_PF_7_0_CLR is 0x%x\n", val);
1490
1491         val = REG_RD(bp, PGLUE_B_REG_FLR_REQUEST_PF_7_0_CLR);
1492         DP(BNX2X_MSG_SP, "PGLUE_B_REG_FLR_REQUEST_PF_7_0_CLR is 0x%x\n", val);
1493
1494         val = REG_RD(bp, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER);
1495         DP(BNX2X_MSG_SP, "PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER is 0x%x\n",
1496            val);
1497 }
1498
1499 static int bnx2x_pf_flr_clnup(struct bnx2x *bp)
1500 {
1501         u32 poll_cnt = bnx2x_flr_clnup_poll_count(bp);
1502
1503         DP(BNX2X_MSG_SP, "Cleanup after FLR PF[%d]\n", BP_ABS_FUNC(bp));
1504
1505         /* Re-enable PF target read access */
1506         REG_WR(bp, PGLUE_B_REG_INTERNAL_PFID_ENABLE_TARGET_READ, 1);
1507
1508         /* Poll HW usage counters */
1509         DP(BNX2X_MSG_SP, "Polling usage counters\n");
1510         if (bnx2x_poll_hw_usage_counters(bp, poll_cnt))
1511                 return -EBUSY;
1512
1513         /* Zero the igu 'trailing edge' and 'leading edge' */
1514
1515         /* Send the FW cleanup command */
1516         if (bnx2x_send_final_clnup(bp, (u8)BP_FUNC(bp), poll_cnt))
1517                 return -EBUSY;
1518
1519         /* ATC cleanup */
1520
1521         /* Verify TX hw is flushed */
1522         bnx2x_tx_hw_flushed(bp, poll_cnt);
1523
1524         /* Wait 100ms (not adjusted according to platform) */
1525         msleep(100);
1526
1527         /* Verify no pending pci transactions */
1528         if (bnx2x_is_pcie_pending(bp->pdev))
1529                 BNX2X_ERR("PCIE Transactions still pending\n");
1530
1531         /* Debug */
1532         bnx2x_hw_enable_status(bp);
1533
1534         /*
1535          * Master enable - Due to WB DMAE writes performed before this
1536          * register is re-initialized as part of the regular function init
1537          */
1538         REG_WR(bp, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, 1);
1539
1540         return 0;
1541 }
1542
1543 static void bnx2x_hc_int_enable(struct bnx2x *bp)
1544 {
1545         int port = BP_PORT(bp);
1546         u32 addr = port ? HC_REG_CONFIG_1 : HC_REG_CONFIG_0;
1547         u32 val = REG_RD(bp, addr);
1548         bool msix = (bp->flags & USING_MSIX_FLAG) ? true : false;
1549         bool single_msix = (bp->flags & USING_SINGLE_MSIX_FLAG) ? true : false;
1550         bool msi = (bp->flags & USING_MSI_FLAG) ? true : false;
1551
1552         if (msix) {
1553                 val &= ~(HC_CONFIG_0_REG_SINGLE_ISR_EN_0 |
1554                          HC_CONFIG_0_REG_INT_LINE_EN_0);
1555                 val |= (HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0 |
1556                         HC_CONFIG_0_REG_ATTN_BIT_EN_0);
1557                 if (single_msix)
1558                         val |= HC_CONFIG_0_REG_SINGLE_ISR_EN_0;
1559         } else if (msi) {
1560                 val &= ~HC_CONFIG_0_REG_INT_LINE_EN_0;
1561                 val |= (HC_CONFIG_0_REG_SINGLE_ISR_EN_0 |
1562                         HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0 |
1563                         HC_CONFIG_0_REG_ATTN_BIT_EN_0);
1564         } else {
1565                 val |= (HC_CONFIG_0_REG_SINGLE_ISR_EN_0 |
1566                         HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0 |
1567                         HC_CONFIG_0_REG_INT_LINE_EN_0 |
1568                         HC_CONFIG_0_REG_ATTN_BIT_EN_0);
1569
1570                 if (!CHIP_IS_E1(bp)) {
1571                         DP(NETIF_MSG_IFUP,
1572                            "write %x to HC %d (addr 0x%x)\n", val, port, addr);
1573
1574                         REG_WR(bp, addr, val);
1575
1576                         val &= ~HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0;
1577                 }
1578         }
1579
1580         if (CHIP_IS_E1(bp))
1581                 REG_WR(bp, HC_REG_INT_MASK + port*4, 0x1FFFF);
1582
1583         DP(NETIF_MSG_IFUP,
1584            "write %x to HC %d (addr 0x%x) mode %s\n", val, port, addr,
1585            (msix ? "MSI-X" : (msi ? "MSI" : "INTx")));
1586
1587         REG_WR(bp, addr, val);
1588         /*
1589          * Ensure that HC_CONFIG is written before leading/trailing edge config
1590          */
1591         mmiowb();
1592         barrier();
1593
1594         if (!CHIP_IS_E1(bp)) {
1595                 /* init leading/trailing edge */
1596                 if (IS_MF(bp)) {
1597                         val = (0xee0f | (1 << (BP_VN(bp) + 4)));
1598                         if (bp->port.pmf)
1599                                 /* enable nig and gpio3 attention */
1600                                 val |= 0x1100;
1601                 } else
1602                         val = 0xffff;
1603
1604                 REG_WR(bp, HC_REG_TRAILING_EDGE_0 + port*8, val);
1605                 REG_WR(bp, HC_REG_LEADING_EDGE_0 + port*8, val);
1606         }
1607
1608         /* Make sure that interrupts are indeed enabled from here on */
1609         mmiowb();
1610 }
1611
1612 static void bnx2x_igu_int_enable(struct bnx2x *bp)
1613 {
1614         u32 val;
1615         bool msix = (bp->flags & USING_MSIX_FLAG) ? true : false;
1616         bool single_msix = (bp->flags & USING_SINGLE_MSIX_FLAG) ? true : false;
1617         bool msi = (bp->flags & USING_MSI_FLAG) ? true : false;
1618
1619         val = REG_RD(bp, IGU_REG_PF_CONFIGURATION);
1620
1621         if (msix) {
1622                 val &= ~(IGU_PF_CONF_INT_LINE_EN |
1623                          IGU_PF_CONF_SINGLE_ISR_EN);
1624                 val |= (IGU_PF_CONF_MSI_MSIX_EN |
1625                         IGU_PF_CONF_ATTN_BIT_EN);
1626
1627                 if (single_msix)
1628                         val |= IGU_PF_CONF_SINGLE_ISR_EN;
1629         } else if (msi) {
1630                 val &= ~IGU_PF_CONF_INT_LINE_EN;
1631                 val |= (IGU_PF_CONF_MSI_MSIX_EN |
1632                         IGU_PF_CONF_ATTN_BIT_EN |
1633                         IGU_PF_CONF_SINGLE_ISR_EN);
1634         } else {
1635                 val &= ~IGU_PF_CONF_MSI_MSIX_EN;
1636                 val |= (IGU_PF_CONF_INT_LINE_EN |
1637                         IGU_PF_CONF_ATTN_BIT_EN |
1638                         IGU_PF_CONF_SINGLE_ISR_EN);
1639         }
1640
1641         /* Clean previous status - need to configure igu prior to ack*/
1642         if ((!msix) || single_msix) {
1643                 REG_WR(bp, IGU_REG_PF_CONFIGURATION, val);
1644                 bnx2x_ack_int(bp);
1645         }
1646
1647         val |= IGU_PF_CONF_FUNC_EN;
1648
1649         DP(NETIF_MSG_IFUP, "write 0x%x to IGU  mode %s\n",
1650            val, (msix ? "MSI-X" : (msi ? "MSI" : "INTx")));
1651
1652         REG_WR(bp, IGU_REG_PF_CONFIGURATION, val);
1653
1654         if (val & IGU_PF_CONF_INT_LINE_EN)
1655                 pci_intx(bp->pdev, true);
1656
1657         barrier();
1658
1659         /* init leading/trailing edge */
1660         if (IS_MF(bp)) {
1661                 val = (0xee0f | (1 << (BP_VN(bp) + 4)));
1662                 if (bp->port.pmf)
1663                         /* enable nig and gpio3 attention */
1664                         val |= 0x1100;
1665         } else
1666                 val = 0xffff;
1667
1668         REG_WR(bp, IGU_REG_TRAILING_EDGE_LATCH, val);
1669         REG_WR(bp, IGU_REG_LEADING_EDGE_LATCH, val);
1670
1671         /* Make sure that interrupts are indeed enabled from here on */
1672         mmiowb();
1673 }
1674
1675 void bnx2x_int_enable(struct bnx2x *bp)
1676 {
1677         if (bp->common.int_block == INT_BLOCK_HC)
1678                 bnx2x_hc_int_enable(bp);
1679         else
1680                 bnx2x_igu_int_enable(bp);
1681 }
1682
1683 void bnx2x_int_disable_sync(struct bnx2x *bp, int disable_hw)
1684 {
1685         int msix = (bp->flags & USING_MSIX_FLAG) ? 1 : 0;
1686         int i, offset;
1687
1688         if (disable_hw)
1689                 /* prevent the HW from sending interrupts */
1690                 bnx2x_int_disable(bp);
1691
1692         /* make sure all ISRs are done */
1693         if (msix) {
1694                 synchronize_irq(bp->msix_table[0].vector);
1695                 offset = 1;
1696                 if (CNIC_SUPPORT(bp))
1697                         offset++;
1698                 for_each_eth_queue(bp, i)
1699                         synchronize_irq(bp->msix_table[offset++].vector);
1700         } else
1701                 synchronize_irq(bp->pdev->irq);
1702
1703         /* make sure sp_task is not running */
1704         cancel_delayed_work(&bp->sp_task);
1705         cancel_delayed_work(&bp->period_task);
1706         flush_workqueue(bnx2x_wq);
1707 }
1708
1709 /* fast path */
1710
1711 /*
1712  * General service functions
1713  */
1714
1715 /* Return true if succeeded to acquire the lock */
1716 static bool bnx2x_trylock_hw_lock(struct bnx2x *bp, u32 resource)
1717 {
1718         u32 lock_status;
1719         u32 resource_bit = (1 << resource);
1720         int func = BP_FUNC(bp);
1721         u32 hw_lock_control_reg;
1722
1723         DP(NETIF_MSG_HW | NETIF_MSG_IFUP,
1724            "Trying to take a lock on resource %d\n", resource);
1725
1726         /* Validating that the resource is within range */
1727         if (resource > HW_LOCK_MAX_RESOURCE_VALUE) {
1728                 DP(NETIF_MSG_HW | NETIF_MSG_IFUP,
1729                    "resource(0x%x) > HW_LOCK_MAX_RESOURCE_VALUE(0x%x)\n",
1730                    resource, HW_LOCK_MAX_RESOURCE_VALUE);
1731                 return false;
1732         }
1733
1734         if (func <= 5)
1735                 hw_lock_control_reg = (MISC_REG_DRIVER_CONTROL_1 + func*8);
1736         else
1737                 hw_lock_control_reg =
1738                                 (MISC_REG_DRIVER_CONTROL_7 + (func - 6)*8);
1739
1740         /* Try to acquire the lock */
1741         REG_WR(bp, hw_lock_control_reg + 4, resource_bit);
1742         lock_status = REG_RD(bp, hw_lock_control_reg);
1743         if (lock_status & resource_bit)
1744                 return true;
1745
1746         DP(NETIF_MSG_HW | NETIF_MSG_IFUP,
1747            "Failed to get a lock on resource %d\n", resource);
1748         return false;
1749 }
1750
1751 /**
1752  * bnx2x_get_leader_lock_resource - get the recovery leader resource id
1753  *
1754  * @bp: driver handle
1755  *
1756  * Returns the recovery leader resource id according to the engine this function
1757  * belongs to. Currently only only 2 engines is supported.
1758  */
1759 static int bnx2x_get_leader_lock_resource(struct bnx2x *bp)
1760 {
1761         if (BP_PATH(bp))
1762                 return HW_LOCK_RESOURCE_RECOVERY_LEADER_1;
1763         else
1764                 return HW_LOCK_RESOURCE_RECOVERY_LEADER_0;
1765 }
1766
1767 /**
1768  * bnx2x_trylock_leader_lock- try to acquire a leader lock.
1769  *
1770  * @bp: driver handle
1771  *
1772  * Tries to acquire a leader lock for current engine.
1773  */
1774 static bool bnx2x_trylock_leader_lock(struct bnx2x *bp)
1775 {
1776         return bnx2x_trylock_hw_lock(bp, bnx2x_get_leader_lock_resource(bp));
1777 }
1778
1779 static void bnx2x_cnic_cfc_comp(struct bnx2x *bp, int cid, u8 err);
1780
1781 /* schedule the sp task and mark that interrupt occurred (runs from ISR) */
1782 static int bnx2x_schedule_sp_task(struct bnx2x *bp)
1783 {
1784         /* Set the interrupt occurred bit for the sp-task to recognize it
1785          * must ack the interrupt and transition according to the IGU
1786          * state machine.
1787          */
1788         atomic_set(&bp->interrupt_occurred, 1);
1789
1790         /* The sp_task must execute only after this bit
1791          * is set, otherwise we will get out of sync and miss all
1792          * further interrupts. Hence, the barrier.
1793          */
1794         smp_wmb();
1795
1796         /* schedule sp_task to workqueue */
1797         return queue_delayed_work(bnx2x_wq, &bp->sp_task, 0);
1798 }
1799
1800 void bnx2x_sp_event(struct bnx2x_fastpath *fp, union eth_rx_cqe *rr_cqe)
1801 {
1802         struct bnx2x *bp = fp->bp;
1803         int cid = SW_CID(rr_cqe->ramrod_cqe.conn_and_cmd_data);
1804         int command = CQE_CMD(rr_cqe->ramrod_cqe.conn_and_cmd_data);
1805         enum bnx2x_queue_cmd drv_cmd = BNX2X_Q_CMD_MAX;
1806         struct bnx2x_queue_sp_obj *q_obj = &bnx2x_sp_obj(bp, fp).q_obj;
1807
1808         DP(BNX2X_MSG_SP,
1809            "fp %d  cid %d  got ramrod #%d  state is %x  type is %d\n",
1810            fp->index, cid, command, bp->state,
1811            rr_cqe->ramrod_cqe.ramrod_type);
1812
1813         /* If cid is within VF range, replace the slowpath object with the
1814          * one corresponding to this VF
1815          */
1816         if (cid >= BNX2X_FIRST_VF_CID  &&
1817             cid < BNX2X_FIRST_VF_CID + BNX2X_VF_CIDS)
1818                 bnx2x_iov_set_queue_sp_obj(bp, cid, &q_obj);
1819
1820         switch (command) {
1821         case (RAMROD_CMD_ID_ETH_CLIENT_UPDATE):
1822                 DP(BNX2X_MSG_SP, "got UPDATE ramrod. CID %d\n", cid);
1823                 drv_cmd = BNX2X_Q_CMD_UPDATE;
1824                 break;
1825
1826         case (RAMROD_CMD_ID_ETH_CLIENT_SETUP):
1827                 DP(BNX2X_MSG_SP, "got MULTI[%d] setup ramrod\n", cid);
1828                 drv_cmd = BNX2X_Q_CMD_SETUP;
1829                 break;
1830
1831         case (RAMROD_CMD_ID_ETH_TX_QUEUE_SETUP):
1832                 DP(BNX2X_MSG_SP, "got MULTI[%d] tx-only setup ramrod\n", cid);
1833                 drv_cmd = BNX2X_Q_CMD_SETUP_TX_ONLY;
1834                 break;
1835
1836         case (RAMROD_CMD_ID_ETH_HALT):
1837                 DP(BNX2X_MSG_SP, "got MULTI[%d] halt ramrod\n", cid);
1838                 drv_cmd = BNX2X_Q_CMD_HALT;
1839                 break;
1840
1841         case (RAMROD_CMD_ID_ETH_TERMINATE):
1842                 DP(BNX2X_MSG_SP, "got MULTI[%d] terminate ramrod\n", cid);
1843                 drv_cmd = BNX2X_Q_CMD_TERMINATE;
1844                 break;
1845
1846         case (RAMROD_CMD_ID_ETH_EMPTY):
1847                 DP(BNX2X_MSG_SP, "got MULTI[%d] empty ramrod\n", cid);
1848                 drv_cmd = BNX2X_Q_CMD_EMPTY;
1849                 break;
1850
1851         case (RAMROD_CMD_ID_ETH_TPA_UPDATE):
1852                 DP(BNX2X_MSG_SP, "got tpa update ramrod CID=%d\n", cid);
1853                 drv_cmd = BNX2X_Q_CMD_UPDATE_TPA;
1854                 break;
1855
1856         default:
1857                 BNX2X_ERR("unexpected MC reply (%d) on fp[%d]\n",
1858                           command, fp->index);
1859                 return;
1860         }
1861
1862         if ((drv_cmd != BNX2X_Q_CMD_MAX) &&
1863             q_obj->complete_cmd(bp, q_obj, drv_cmd))
1864                 /* q_obj->complete_cmd() failure means that this was
1865                  * an unexpected completion.
1866                  *
1867                  * In this case we don't want to increase the bp->spq_left
1868                  * because apparently we haven't sent this command the first
1869                  * place.
1870                  */
1871 #ifdef BNX2X_STOP_ON_ERROR
1872                 bnx2x_panic();
1873 #else
1874                 return;
1875 #endif
1876
1877         smp_mb__before_atomic();
1878         atomic_inc(&bp->cq_spq_left);
1879         /* push the change in bp->spq_left and towards the memory */
1880         smp_mb__after_atomic();
1881
1882         DP(BNX2X_MSG_SP, "bp->cq_spq_left %x\n", atomic_read(&bp->cq_spq_left));
1883
1884         if ((drv_cmd == BNX2X_Q_CMD_UPDATE) && (IS_FCOE_FP(fp)) &&
1885             (!!test_bit(BNX2X_AFEX_FCOE_Q_UPDATE_PENDING, &bp->sp_state))) {
1886                 /* if Q update ramrod is completed for last Q in AFEX vif set
1887                  * flow, then ACK MCP at the end
1888                  *
1889                  * mark pending ACK to MCP bit.
1890                  * prevent case that both bits are cleared.
1891                  * At the end of load/unload driver checks that
1892                  * sp_state is cleared, and this order prevents
1893                  * races
1894                  */
1895                 smp_mb__before_atomic();
1896                 set_bit(BNX2X_AFEX_PENDING_VIFSET_MCP_ACK, &bp->sp_state);
1897                 wmb();
1898                 clear_bit(BNX2X_AFEX_FCOE_Q_UPDATE_PENDING, &bp->sp_state);
1899                 smp_mb__after_atomic();
1900
1901                 /* schedule the sp task as mcp ack is required */
1902                 bnx2x_schedule_sp_task(bp);
1903         }
1904
1905         return;
1906 }
1907
1908 irqreturn_t bnx2x_interrupt(int irq, void *dev_instance)
1909 {
1910         struct bnx2x *bp = netdev_priv(dev_instance);
1911         u16 status = bnx2x_ack_int(bp);
1912         u16 mask;
1913         int i;
1914         u8 cos;
1915
1916         /* Return here if interrupt is shared and it's not for us */
1917         if (unlikely(status == 0)) {
1918                 DP(NETIF_MSG_INTR, "not our interrupt!\n");
1919                 return IRQ_NONE;
1920         }
1921         DP(NETIF_MSG_INTR, "got an interrupt  status 0x%x\n", status);
1922
1923 #ifdef BNX2X_STOP_ON_ERROR
1924         if (unlikely(bp->panic))
1925                 return IRQ_HANDLED;
1926 #endif
1927
1928         for_each_eth_queue(bp, i) {
1929                 struct bnx2x_fastpath *fp = &bp->fp[i];
1930
1931                 mask = 0x2 << (fp->index + CNIC_SUPPORT(bp));
1932                 if (status & mask) {
1933                         /* Handle Rx or Tx according to SB id */
1934                         for_each_cos_in_tx_queue(fp, cos)
1935                                 prefetch(fp->txdata_ptr[cos]->tx_cons_sb);
1936                         prefetch(&fp->sb_running_index[SM_RX_ID]);
1937                         napi_schedule_irqoff(&bnx2x_fp(bp, fp->index, napi));
1938                         status &= ~mask;
1939                 }
1940         }
1941
1942         if (CNIC_SUPPORT(bp)) {
1943                 mask = 0x2;
1944                 if (status & (mask | 0x1)) {
1945                         struct cnic_ops *c_ops = NULL;
1946
1947                         rcu_read_lock();
1948                         c_ops = rcu_dereference(bp->cnic_ops);
1949                         if (c_ops && (bp->cnic_eth_dev.drv_state &
1950                                       CNIC_DRV_STATE_HANDLES_IRQ))
1951                                 c_ops->cnic_handler(bp->cnic_data, NULL);
1952                         rcu_read_unlock();
1953
1954                         status &= ~mask;
1955                 }
1956         }
1957
1958         if (unlikely(status & 0x1)) {
1959
1960                 /* schedule sp task to perform default status block work, ack
1961                  * attentions and enable interrupts.
1962                  */
1963                 bnx2x_schedule_sp_task(bp);
1964
1965                 status &= ~0x1;
1966                 if (!status)
1967                         return IRQ_HANDLED;
1968         }
1969
1970         if (unlikely(status))
1971                 DP(NETIF_MSG_INTR, "got an unknown interrupt! (status 0x%x)\n",
1972                    status);
1973
1974         return IRQ_HANDLED;
1975 }
1976
1977 /* Link */
1978
1979 /*
1980  * General service functions
1981  */
1982
1983 int bnx2x_acquire_hw_lock(struct bnx2x *bp, u32 resource)
1984 {
1985         u32 lock_status;
1986         u32 resource_bit = (1 << resource);
1987         int func = BP_FUNC(bp);
1988         u32 hw_lock_control_reg;
1989         int cnt;
1990
1991         /* Validating that the resource is within range */
1992         if (resource > HW_LOCK_MAX_RESOURCE_VALUE) {
1993                 BNX2X_ERR("resource(0x%x) > HW_LOCK_MAX_RESOURCE_VALUE(0x%x)\n",
1994                    resource, HW_LOCK_MAX_RESOURCE_VALUE);
1995                 return -EINVAL;
1996         }
1997
1998         if (func <= 5) {
1999                 hw_lock_control_reg = (MISC_REG_DRIVER_CONTROL_1 + func*8);
2000         } else {
2001                 hw_lock_control_reg =
2002                                 (MISC_REG_DRIVER_CONTROL_7 + (func - 6)*8);
2003         }
2004
2005         /* Validating that the resource is not already taken */
2006         lock_status = REG_RD(bp, hw_lock_control_reg);
2007         if (lock_status & resource_bit) {
2008                 BNX2X_ERR("lock_status 0x%x  resource_bit 0x%x\n",
2009                    lock_status, resource_bit);
2010                 return -EEXIST;
2011         }
2012
2013         /* Try for 5 second every 5ms */
2014         for (cnt = 0; cnt < 1000; cnt++) {
2015                 /* Try to acquire the lock */
2016                 REG_WR(bp, hw_lock_control_reg + 4, resource_bit);
2017                 lock_status = REG_RD(bp, hw_lock_control_reg);
2018                 if (lock_status & resource_bit)
2019                         return 0;
2020
2021                 usleep_range(5000, 10000);
2022         }
2023         BNX2X_ERR("Timeout\n");
2024         return -EAGAIN;
2025 }
2026
2027 int bnx2x_release_leader_lock(struct bnx2x *bp)
2028 {
2029         return bnx2x_release_hw_lock(bp, bnx2x_get_leader_lock_resource(bp));
2030 }
2031
2032 int bnx2x_release_hw_lock(struct bnx2x *bp, u32 resource)
2033 {
2034         u32 lock_status;
2035         u32 resource_bit = (1 << resource);
2036         int func = BP_FUNC(bp);
2037         u32 hw_lock_control_reg;
2038
2039         /* Validating that the resource is within range */
2040         if (resource > HW_LOCK_MAX_RESOURCE_VALUE) {
2041                 BNX2X_ERR("resource(0x%x) > HW_LOCK_MAX_RESOURCE_VALUE(0x%x)\n",
2042                    resource, HW_LOCK_MAX_RESOURCE_VALUE);
2043                 return -EINVAL;
2044         }
2045
2046         if (func <= 5) {
2047                 hw_lock_control_reg = (MISC_REG_DRIVER_CONTROL_1 + func*8);
2048         } else {
2049                 hw_lock_control_reg =
2050                                 (MISC_REG_DRIVER_CONTROL_7 + (func - 6)*8);
2051         }
2052
2053         /* Validating that the resource is currently taken */
2054         lock_status = REG_RD(bp, hw_lock_control_reg);
2055         if (!(lock_status & resource_bit)) {
2056                 BNX2X_ERR("lock_status 0x%x resource_bit 0x%x. Unlock was called but lock wasn't taken!\n",
2057                           lock_status, resource_bit);
2058                 return -EFAULT;
2059         }
2060
2061         REG_WR(bp, hw_lock_control_reg, resource_bit);
2062         return 0;
2063 }
2064
2065 int bnx2x_get_gpio(struct bnx2x *bp, int gpio_num, u8 port)
2066 {
2067         /* The GPIO should be swapped if swap register is set and active */
2068         int gpio_port = (REG_RD(bp, NIG_REG_PORT_SWAP) &&
2069                          REG_RD(bp, NIG_REG_STRAP_OVERRIDE)) ^ port;
2070         int gpio_shift = gpio_num +
2071                         (gpio_port ? MISC_REGISTERS_GPIO_PORT_SHIFT : 0);
2072         u32 gpio_mask = (1 << gpio_shift);
2073         u32 gpio_reg;
2074         int value;
2075
2076         if (gpio_num > MISC_REGISTERS_GPIO_3) {
2077                 BNX2X_ERR("Invalid GPIO %d\n", gpio_num);
2078                 return -EINVAL;
2079         }
2080
2081         /* read GPIO value */
2082         gpio_reg = REG_RD(bp, MISC_REG_GPIO);
2083
2084         /* get the requested pin value */
2085         if ((gpio_reg & gpio_mask) == gpio_mask)
2086                 value = 1;
2087         else
2088                 value = 0;
2089
2090         return value;
2091 }
2092
2093 int bnx2x_set_gpio(struct bnx2x *bp, int gpio_num, u32 mode, u8 port)
2094 {
2095         /* The GPIO should be swapped if swap register is set and active */
2096         int gpio_port = (REG_RD(bp, NIG_REG_PORT_SWAP) &&
2097                          REG_RD(bp, NIG_REG_STRAP_OVERRIDE)) ^ port;
2098         int gpio_shift = gpio_num +
2099                         (gpio_port ? MISC_REGISTERS_GPIO_PORT_SHIFT : 0);
2100         u32 gpio_mask = (1 << gpio_shift);
2101         u32 gpio_reg;
2102
2103         if (gpio_num > MISC_REGISTERS_GPIO_3) {
2104                 BNX2X_ERR("Invalid GPIO %d\n", gpio_num);
2105                 return -EINVAL;
2106         }
2107
2108         bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_GPIO);
2109         /* read GPIO and mask except the float bits */
2110         gpio_reg = (REG_RD(bp, MISC_REG_GPIO) & MISC_REGISTERS_GPIO_FLOAT);
2111
2112         switch (mode) {
2113         case MISC_REGISTERS_GPIO_OUTPUT_LOW:
2114                 DP(NETIF_MSG_LINK,
2115                    "Set GPIO %d (shift %d) -> output low\n",
2116                    gpio_num, gpio_shift);
2117                 /* clear FLOAT and set CLR */
2118                 gpio_reg &= ~(gpio_mask << MISC_REGISTERS_GPIO_FLOAT_POS);
2119                 gpio_reg |=  (gpio_mask << MISC_REGISTERS_GPIO_CLR_POS);
2120                 break;
2121
2122         case MISC_REGISTERS_GPIO_OUTPUT_HIGH:
2123                 DP(NETIF_MSG_LINK,
2124                    "Set GPIO %d (shift %d) -> output high\n",
2125                    gpio_num, gpio_shift);
2126                 /* clear FLOAT and set SET */
2127                 gpio_reg &= ~(gpio_mask << MISC_REGISTERS_GPIO_FLOAT_POS);
2128                 gpio_reg |=  (gpio_mask << MISC_REGISTERS_GPIO_SET_POS);
2129                 break;
2130
2131         case MISC_REGISTERS_GPIO_INPUT_HI_Z:
2132                 DP(NETIF_MSG_LINK,
2133                    "Set GPIO %d (shift %d) -> input\n",
2134                    gpio_num, gpio_shift);
2135                 /* set FLOAT */
2136                 gpio_reg |= (gpio_mask << MISC_REGISTERS_GPIO_FLOAT_POS);
2137                 break;
2138
2139         default:
2140                 break;
2141         }
2142
2143         REG_WR(bp, MISC_REG_GPIO, gpio_reg);
2144         bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_GPIO);
2145
2146         return 0;
2147 }
2148
2149 int bnx2x_set_mult_gpio(struct bnx2x *bp, u8 pins, u32 mode)
2150 {
2151         u32 gpio_reg = 0;
2152         int rc = 0;
2153
2154         /* Any port swapping should be handled by caller. */
2155
2156         bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_GPIO);
2157         /* read GPIO and mask except the float bits */
2158         gpio_reg = REG_RD(bp, MISC_REG_GPIO);
2159         gpio_reg &= ~(pins << MISC_REGISTERS_GPIO_FLOAT_POS);
2160         gpio_reg &= ~(pins << MISC_REGISTERS_GPIO_CLR_POS);
2161         gpio_reg &= ~(pins << MISC_REGISTERS_GPIO_SET_POS);
2162
2163         switch (mode) {
2164         case MISC_REGISTERS_GPIO_OUTPUT_LOW:
2165                 DP(NETIF_MSG_LINK, "Set GPIO 0x%x -> output low\n", pins);
2166                 /* set CLR */
2167                 gpio_reg |= (pins << MISC_REGISTERS_GPIO_CLR_POS);
2168                 break;
2169
2170         case MISC_REGISTERS_GPIO_OUTPUT_HIGH:
2171                 DP(NETIF_MSG_LINK, "Set GPIO 0x%x -> output high\n", pins);
2172                 /* set SET */
2173                 gpio_reg |= (pins << MISC_REGISTERS_GPIO_SET_POS);
2174                 break;
2175
2176         case MISC_REGISTERS_GPIO_INPUT_HI_Z:
2177                 DP(NETIF_MSG_LINK, "Set GPIO 0x%x -> input\n", pins);
2178                 /* set FLOAT */
2179                 gpio_reg |= (pins << MISC_REGISTERS_GPIO_FLOAT_POS);
2180                 break;
2181
2182         default:
2183                 BNX2X_ERR("Invalid GPIO mode assignment %d\n", mode);
2184                 rc = -EINVAL;
2185                 break;
2186         }
2187
2188         if (rc == 0)
2189                 REG_WR(bp, MISC_REG_GPIO, gpio_reg);
2190
2191         bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_GPIO);
2192
2193         return rc;
2194 }
2195
2196 int bnx2x_set_gpio_int(struct bnx2x *bp, int gpio_num, u32 mode, u8 port)
2197 {
2198         /* The GPIO should be swapped if swap register is set and active */
2199         int gpio_port = (REG_RD(bp, NIG_REG_PORT_SWAP) &&
2200                          REG_RD(bp, NIG_REG_STRAP_OVERRIDE)) ^ port;
2201         int gpio_shift = gpio_num +
2202                         (gpio_port ? MISC_REGISTERS_GPIO_PORT_SHIFT : 0);
2203         u32 gpio_mask = (1 << gpio_shift);
2204         u32 gpio_reg;
2205
2206         if (gpio_num > MISC_REGISTERS_GPIO_3) {
2207                 BNX2X_ERR("Invalid GPIO %d\n", gpio_num);
2208                 return -EINVAL;
2209         }
2210
2211         bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_GPIO);
2212         /* read GPIO int */
2213         gpio_reg = REG_RD(bp, MISC_REG_GPIO_INT);
2214
2215         switch (mode) {
2216         case MISC_REGISTERS_GPIO_INT_OUTPUT_CLR:
2217                 DP(NETIF_MSG_LINK,
2218                    "Clear GPIO INT %d (shift %d) -> output low\n",
2219                    gpio_num, gpio_shift);
2220                 /* clear SET and set CLR */
2221                 gpio_reg &= ~(gpio_mask << MISC_REGISTERS_GPIO_INT_SET_POS);
2222                 gpio_reg |=  (gpio_mask << MISC_REGISTERS_GPIO_INT_CLR_POS);
2223                 break;
2224
2225         case MISC_REGISTERS_GPIO_INT_OUTPUT_SET:
2226                 DP(NETIF_MSG_LINK,
2227                    "Set GPIO INT %d (shift %d) -> output high\n",
2228                    gpio_num, gpio_shift);
2229                 /* clear CLR and set SET */
2230                 gpio_reg &= ~(gpio_mask << MISC_REGISTERS_GPIO_INT_CLR_POS);
2231                 gpio_reg |=  (gpio_mask << MISC_REGISTERS_GPIO_INT_SET_POS);
2232                 break;
2233
2234         default:
2235                 break;
2236         }
2237
2238         REG_WR(bp, MISC_REG_GPIO_INT, gpio_reg);
2239         bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_GPIO);
2240
2241         return 0;
2242 }
2243
2244 static int bnx2x_set_spio(struct bnx2x *bp, int spio, u32 mode)
2245 {
2246         u32 spio_reg;
2247
2248         /* Only 2 SPIOs are configurable */
2249         if ((spio != MISC_SPIO_SPIO4) && (spio != MISC_SPIO_SPIO5)) {
2250                 BNX2X_ERR("Invalid SPIO 0x%x\n", spio);
2251                 return -EINVAL;
2252         }
2253
2254         bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_SPIO);
2255         /* read SPIO and mask except the float bits */
2256         spio_reg = (REG_RD(bp, MISC_REG_SPIO) & MISC_SPIO_FLOAT);
2257
2258         switch (mode) {
2259         case MISC_SPIO_OUTPUT_LOW:
2260                 DP(NETIF_MSG_HW, "Set SPIO 0x%x -> output low\n", spio);
2261                 /* clear FLOAT and set CLR */
2262                 spio_reg &= ~(spio << MISC_SPIO_FLOAT_POS);
2263                 spio_reg |=  (spio << MISC_SPIO_CLR_POS);
2264                 break;
2265
2266         case MISC_SPIO_OUTPUT_HIGH:
2267                 DP(NETIF_MSG_HW, "Set SPIO 0x%x -> output high\n", spio);
2268                 /* clear FLOAT and set SET */
2269                 spio_reg &= ~(spio << MISC_SPIO_FLOAT_POS);
2270                 spio_reg |=  (spio << MISC_SPIO_SET_POS);
2271                 break;
2272
2273         case MISC_SPIO_INPUT_HI_Z:
2274                 DP(NETIF_MSG_HW, "Set SPIO 0x%x -> input\n", spio);
2275                 /* set FLOAT */
2276                 spio_reg |= (spio << MISC_SPIO_FLOAT_POS);
2277                 break;
2278
2279         default:
2280                 break;
2281         }
2282
2283         REG_WR(bp, MISC_REG_SPIO, spio_reg);
2284         bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_SPIO);
2285
2286         return 0;
2287 }
2288
2289 void bnx2x_calc_fc_adv(struct bnx2x *bp)
2290 {
2291         u8 cfg_idx = bnx2x_get_link_cfg_idx(bp);
2292
2293         bp->port.advertising[cfg_idx] &= ~(ADVERTISED_Asym_Pause |
2294                                            ADVERTISED_Pause);
2295         switch (bp->link_vars.ieee_fc &
2296                 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_MASK) {
2297         case MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH:
2298                 bp->port.advertising[cfg_idx] |= (ADVERTISED_Asym_Pause |
2299                                                   ADVERTISED_Pause);
2300                 break;
2301
2302         case MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC:
2303                 bp->port.advertising[cfg_idx] |= ADVERTISED_Asym_Pause;
2304                 break;
2305
2306         default:
2307                 break;
2308         }
2309 }
2310
2311 static void bnx2x_set_requested_fc(struct bnx2x *bp)
2312 {
2313         /* Initialize link parameters structure variables
2314          * It is recommended to turn off RX FC for jumbo frames
2315          *  for better performance
2316          */
2317         if (CHIP_IS_E1x(bp) && (bp->dev->mtu > 5000))
2318                 bp->link_params.req_fc_auto_adv = BNX2X_FLOW_CTRL_TX;
2319         else
2320                 bp->link_params.req_fc_auto_adv = BNX2X_FLOW_CTRL_BOTH;
2321 }
2322
2323 static void bnx2x_init_dropless_fc(struct bnx2x *bp)
2324 {
2325         u32 pause_enabled = 0;
2326
2327         if (!CHIP_IS_E1(bp) && bp->dropless_fc && bp->link_vars.link_up) {
2328                 if (bp->link_vars.flow_ctrl & BNX2X_FLOW_CTRL_TX)
2329                         pause_enabled = 1;
2330
2331                 REG_WR(bp, BAR_USTRORM_INTMEM +
2332                            USTORM_ETH_PAUSE_ENABLED_OFFSET(BP_PORT(bp)),
2333                        pause_enabled);
2334         }
2335
2336         DP(NETIF_MSG_IFUP | NETIF_MSG_LINK, "dropless_fc is %s\n",
2337            pause_enabled ? "enabled" : "disabled");
2338 }
2339
2340 int bnx2x_initial_phy_init(struct bnx2x *bp, int load_mode)
2341 {
2342         int rc, cfx_idx = bnx2x_get_link_cfg_idx(bp);
2343         u16 req_line_speed = bp->link_params.req_line_speed[cfx_idx];
2344
2345         if (!BP_NOMCP(bp)) {
2346                 bnx2x_set_requested_fc(bp);
2347                 bnx2x_acquire_phy_lock(bp);
2348
2349                 if (load_mode == LOAD_DIAG) {
2350                         struct link_params *lp = &bp->link_params;
2351                         lp->loopback_mode = LOOPBACK_XGXS;
2352                         /* Prefer doing PHY loopback at highest speed */
2353                         if (lp->req_line_speed[cfx_idx] < SPEED_20000) {
2354                                 if (lp->speed_cap_mask[cfx_idx] &
2355                                     PORT_HW_CFG_SPEED_CAPABILITY_D0_20G)
2356                                         lp->req_line_speed[cfx_idx] =
2357                                         SPEED_20000;
2358                                 else if (lp->speed_cap_mask[cfx_idx] &
2359                                             PORT_HW_CFG_SPEED_CAPABILITY_D0_10G)
2360                                                 lp->req_line_speed[cfx_idx] =
2361                                                 SPEED_10000;
2362                                 else
2363                                         lp->req_line_speed[cfx_idx] =
2364                                         SPEED_1000;
2365                         }
2366                 }
2367
2368                 if (load_mode == LOAD_LOOPBACK_EXT) {
2369                         struct link_params *lp = &bp->link_params;
2370                         lp->loopback_mode = LOOPBACK_EXT;
2371                 }
2372
2373                 rc = bnx2x_phy_init(&bp->link_params, &bp->link_vars);
2374
2375                 bnx2x_release_phy_lock(bp);
2376
2377                 bnx2x_init_dropless_fc(bp);
2378
2379                 bnx2x_calc_fc_adv(bp);
2380
2381                 if (bp->link_vars.link_up) {
2382                         bnx2x_stats_handle(bp, STATS_EVENT_LINK_UP);
2383                         bnx2x_link_report(bp);
2384                 }
2385                 queue_delayed_work(bnx2x_wq, &bp->period_task, 0);
2386                 bp->link_params.req_line_speed[cfx_idx] = req_line_speed;
2387                 return rc;
2388         }
2389         BNX2X_ERR("Bootcode is missing - can not initialize link\n");
2390         return -EINVAL;
2391 }
2392
2393 void bnx2x_link_set(struct bnx2x *bp)
2394 {
2395         if (!BP_NOMCP(bp)) {
2396                 bnx2x_acquire_phy_lock(bp);
2397                 bnx2x_phy_init(&bp->link_params, &bp->link_vars);
2398                 bnx2x_release_phy_lock(bp);
2399
2400                 bnx2x_init_dropless_fc(bp);
2401
2402                 bnx2x_calc_fc_adv(bp);
2403         } else
2404                 BNX2X_ERR("Bootcode is missing - can not set link\n");
2405 }
2406
2407 static void bnx2x__link_reset(struct bnx2x *bp)
2408 {
2409         if (!BP_NOMCP(bp)) {
2410                 bnx2x_acquire_phy_lock(bp);
2411                 bnx2x_lfa_reset(&bp->link_params, &bp->link_vars);
2412                 bnx2x_release_phy_lock(bp);
2413         } else
2414                 BNX2X_ERR("Bootcode is missing - can not reset link\n");
2415 }
2416
2417 void bnx2x_force_link_reset(struct bnx2x *bp)
2418 {
2419         bnx2x_acquire_phy_lock(bp);
2420         bnx2x_link_reset(&bp->link_params, &bp->link_vars, 1);
2421         bnx2x_release_phy_lock(bp);
2422 }
2423
2424 u8 bnx2x_link_test(struct bnx2x *bp, u8 is_serdes)
2425 {
2426         u8 rc = 0;
2427
2428         if (!BP_NOMCP(bp)) {
2429                 bnx2x_acquire_phy_lock(bp);
2430                 rc = bnx2x_test_link(&bp->link_params, &bp->link_vars,
2431                                      is_serdes);
2432                 bnx2x_release_phy_lock(bp);
2433         } else
2434                 BNX2X_ERR("Bootcode is missing - can not test link\n");
2435
2436         return rc;
2437 }
2438
2439 /* Calculates the sum of vn_min_rates.
2440    It's needed for further normalizing of the min_rates.
2441    Returns:
2442      sum of vn_min_rates.
2443        or
2444      0 - if all the min_rates are 0.
2445      In the later case fairness algorithm should be deactivated.
2446      If not all min_rates are zero then those that are zeroes will be set to 1.
2447  */
2448 static void bnx2x_calc_vn_min(struct bnx2x *bp,
2449                                       struct cmng_init_input *input)
2450 {
2451         int all_zero = 1;
2452         int vn;
2453
2454         for (vn = VN_0; vn < BP_MAX_VN_NUM(bp); vn++) {
2455                 u32 vn_cfg = bp->mf_config[vn];
2456                 u32 vn_min_rate = ((vn_cfg & FUNC_MF_CFG_MIN_BW_MASK) >>
2457                                    FUNC_MF_CFG_MIN_BW_SHIFT) * 100;
2458
2459                 /* Skip hidden vns */
2460                 if (vn_cfg & FUNC_MF_CFG_FUNC_HIDE)
2461                         vn_min_rate = 0;
2462                 /* If min rate is zero - set it to 1 */
2463                 else if (!vn_min_rate)
2464                         vn_min_rate = DEF_MIN_RATE;
2465                 else
2466                         all_zero = 0;
2467
2468                 input->vnic_min_rate[vn] = vn_min_rate;
2469         }
2470
2471         /* if ETS or all min rates are zeros - disable fairness */
2472         if (BNX2X_IS_ETS_ENABLED(bp)) {
2473                 input->flags.cmng_enables &=
2474                                         ~CMNG_FLAGS_PER_PORT_FAIRNESS_VN;
2475                 DP(NETIF_MSG_IFUP, "Fairness will be disabled due to ETS\n");
2476         } else if (all_zero) {
2477                 input->flags.cmng_enables &=
2478                                         ~CMNG_FLAGS_PER_PORT_FAIRNESS_VN;
2479                 DP(NETIF_MSG_IFUP,
2480                    "All MIN values are zeroes fairness will be disabled\n");
2481         } else
2482                 input->flags.cmng_enables |=
2483                                         CMNG_FLAGS_PER_PORT_FAIRNESS_VN;
2484 }
2485
2486 static void bnx2x_calc_vn_max(struct bnx2x *bp, int vn,
2487                                     struct cmng_init_input *input)
2488 {
2489         u16 vn_max_rate;
2490         u32 vn_cfg = bp->mf_config[vn];
2491
2492         if (vn_cfg & FUNC_MF_CFG_FUNC_HIDE)
2493                 vn_max_rate = 0;
2494         else {
2495                 u32 maxCfg = bnx2x_extract_max_cfg(bp, vn_cfg);
2496
2497                 if (IS_MF_SI(bp)) {
2498                         /* maxCfg in percents of linkspeed */
2499                         vn_max_rate = (bp->link_vars.line_speed * maxCfg) / 100;
2500                 } else /* SD modes */
2501                         /* maxCfg is absolute in 100Mb units */
2502                         vn_max_rate = maxCfg * 100;
2503         }
2504
2505         DP(NETIF_MSG_IFUP, "vn %d: vn_max_rate %d\n", vn, vn_max_rate);
2506
2507         input->vnic_max_rate[vn] = vn_max_rate;
2508 }
2509
2510 static int bnx2x_get_cmng_fns_mode(struct bnx2x *bp)
2511 {
2512         if (CHIP_REV_IS_SLOW(bp))
2513                 return CMNG_FNS_NONE;
2514         if (IS_MF(bp))
2515                 return CMNG_FNS_MINMAX;
2516
2517         return CMNG_FNS_NONE;
2518 }
2519
2520 void bnx2x_read_mf_cfg(struct bnx2x *bp)
2521 {
2522         int vn, n = (CHIP_MODE_IS_4_PORT(bp) ? 2 : 1);
2523
2524         if (BP_NOMCP(bp))
2525                 return; /* what should be the default value in this case */
2526
2527         /* For 2 port configuration the absolute function number formula
2528          * is:
2529          *      abs_func = 2 * vn + BP_PORT + BP_PATH
2530          *
2531          *      and there are 4 functions per port
2532          *
2533          * For 4 port configuration it is
2534          *      abs_func = 4 * vn + 2 * BP_PORT + BP_PATH
2535          *
2536          *      and there are 2 functions per port
2537          */
2538         for (vn = VN_0; vn < BP_MAX_VN_NUM(bp); vn++) {
2539                 int /*abs*/func = n * (2 * vn + BP_PORT(bp)) + BP_PATH(bp);
2540
2541                 if (func >= E1H_FUNC_MAX)
2542                         break;
2543
2544                 bp->mf_config[vn] =
2545                         MF_CFG_RD(bp, func_mf_config[func].config);
2546         }
2547         if (bp->mf_config[BP_VN(bp)] & FUNC_MF_CFG_FUNC_DISABLED) {
2548                 DP(NETIF_MSG_IFUP, "mf_cfg function disabled\n");
2549                 bp->flags |= MF_FUNC_DIS;
2550         } else {
2551                 DP(NETIF_MSG_IFUP, "mf_cfg function enabled\n");
2552                 bp->flags &= ~MF_FUNC_DIS;
2553         }
2554 }
2555
2556 static void bnx2x_cmng_fns_init(struct bnx2x *bp, u8 read_cfg, u8 cmng_type)
2557 {
2558         struct cmng_init_input input;
2559         memset(&input, 0, sizeof(struct cmng_init_input));
2560
2561         input.port_rate = bp->link_vars.line_speed;
2562
2563         if (cmng_type == CMNG_FNS_MINMAX && input.port_rate) {
2564                 int vn;
2565
2566                 /* read mf conf from shmem */
2567                 if (read_cfg)
2568                         bnx2x_read_mf_cfg(bp);
2569
2570                 /* vn_weight_sum and enable fairness if not 0 */
2571                 bnx2x_calc_vn_min(bp, &input);
2572
2573                 /* calculate and set min-max rate for each vn */
2574                 if (bp->port.pmf)
2575                         for (vn = VN_0; vn < BP_MAX_VN_NUM(bp); vn++)
2576                                 bnx2x_calc_vn_max(bp, vn, &input);
2577
2578                 /* always enable rate shaping and fairness */
2579                 input.flags.cmng_enables |=
2580                                         CMNG_FLAGS_PER_PORT_RATE_SHAPING_VN;
2581
2582                 bnx2x_init_cmng(&input, &bp->cmng);
2583                 return;
2584         }
2585
2586         /* rate shaping and fairness are disabled */
2587         DP(NETIF_MSG_IFUP,
2588            "rate shaping and fairness are disabled\n");
2589 }
2590
2591 static void storm_memset_cmng(struct bnx2x *bp,
2592                               struct cmng_init *cmng,
2593                               u8 port)
2594 {
2595         int vn;
2596         size_t size = sizeof(struct cmng_struct_per_port);
2597
2598         u32 addr = BAR_XSTRORM_INTMEM +
2599                         XSTORM_CMNG_PER_PORT_VARS_OFFSET(port);
2600
2601         __storm_memset_struct(bp, addr, size, (u32 *)&cmng->port);
2602
2603         for (vn = VN_0; vn < BP_MAX_VN_NUM(bp); vn++) {
2604                 int func = func_by_vn(bp, vn);
2605
2606                 addr = BAR_XSTRORM_INTMEM +
2607                        XSTORM_RATE_SHAPING_PER_VN_VARS_OFFSET(func);
2608                 size = sizeof(struct rate_shaping_vars_per_vn);
2609                 __storm_memset_struct(bp, addr, size,
2610                                       (u32 *)&cmng->vnic.vnic_max_rate[vn]);
2611
2612                 addr = BAR_XSTRORM_INTMEM +
2613                        XSTORM_FAIRNESS_PER_VN_VARS_OFFSET(func);
2614                 size = sizeof(struct fairness_vars_per_vn);
2615                 __storm_memset_struct(bp, addr, size,
2616                                       (u32 *)&cmng->vnic.vnic_min_rate[vn]);
2617         }
2618 }
2619
2620 /* init cmng mode in HW according to local configuration */
2621 void bnx2x_set_local_cmng(struct bnx2x *bp)
2622 {
2623         int cmng_fns = bnx2x_get_cmng_fns_mode(bp);
2624
2625         if (cmng_fns != CMNG_FNS_NONE) {
2626                 bnx2x_cmng_fns_init(bp, false, cmng_fns);
2627                 storm_memset_cmng(bp, &bp->cmng, BP_PORT(bp));
2628         } else {
2629                 /* rate shaping and fairness are disabled */
2630                 DP(NETIF_MSG_IFUP,
2631                    "single function mode without fairness\n");
2632         }
2633 }
2634
2635 /* This function is called upon link interrupt */
2636 static void bnx2x_link_attn(struct bnx2x *bp)
2637 {
2638         /* Make sure that we are synced with the current statistics */
2639         bnx2x_stats_handle(bp, STATS_EVENT_STOP);
2640
2641         bnx2x_link_update(&bp->link_params, &bp->link_vars);
2642
2643         bnx2x_init_dropless_fc(bp);
2644
2645         if (bp->link_vars.link_up) {
2646
2647                 if (bp->link_vars.mac_type != MAC_TYPE_EMAC) {
2648                         struct host_port_stats *pstats;
2649
2650                         pstats = bnx2x_sp(bp, port_stats);
2651                         /* reset old mac stats */
2652                         memset(&(pstats->mac_stx[0]), 0,
2653                                sizeof(struct mac_stx));
2654                 }
2655                 if (bp->state == BNX2X_STATE_OPEN)
2656                         bnx2x_stats_handle(bp, STATS_EVENT_LINK_UP);
2657         }
2658
2659         if (bp->link_vars.link_up && bp->link_vars.line_speed)
2660                 bnx2x_set_local_cmng(bp);
2661
2662         __bnx2x_link_report(bp);
2663
2664         if (IS_MF(bp))
2665                 bnx2x_link_sync_notify(bp);
2666 }
2667
2668 void bnx2x__link_status_update(struct bnx2x *bp)
2669 {
2670         if (bp->state != BNX2X_STATE_OPEN)
2671                 return;
2672
2673         /* read updated dcb configuration */
2674         if (IS_PF(bp)) {
2675                 bnx2x_dcbx_pmf_update(bp);
2676                 bnx2x_link_status_update(&bp->link_params, &bp->link_vars);
2677                 if (bp->link_vars.link_up)
2678                         bnx2x_stats_handle(bp, STATS_EVENT_LINK_UP);
2679                 else
2680                         bnx2x_stats_handle(bp, STATS_EVENT_STOP);
2681                         /* indicate link status */
2682                 bnx2x_link_report(bp);
2683
2684         } else { /* VF */
2685                 bp->port.supported[0] |= (SUPPORTED_10baseT_Half |
2686                                           SUPPORTED_10baseT_Full |
2687                                           SUPPORTED_100baseT_Half |
2688                                           SUPPORTED_100baseT_Full |
2689                                           SUPPORTED_1000baseT_Full |
2690                                           SUPPORTED_2500baseX_Full |
2691                                           SUPPORTED_10000baseT_Full |
2692                                           SUPPORTED_TP |
2693                                           SUPPORTED_FIBRE |
2694                                           SUPPORTED_Autoneg |
2695                                           SUPPORTED_Pause |
2696                                           SUPPORTED_Asym_Pause);
2697                 bp->port.advertising[0] = bp->port.supported[0];
2698
2699                 bp->link_params.bp = bp;
2700                 bp->link_params.port = BP_PORT(bp);
2701                 bp->link_params.req_duplex[0] = DUPLEX_FULL;
2702                 bp->link_params.req_flow_ctrl[0] = BNX2X_FLOW_CTRL_NONE;
2703                 bp->link_params.req_line_speed[0] = SPEED_10000;
2704                 bp->link_params.speed_cap_mask[0] = 0x7f0000;
2705                 bp->link_params.switch_cfg = SWITCH_CFG_10G;
2706                 bp->link_vars.mac_type = MAC_TYPE_BMAC;
2707                 bp->link_vars.line_speed = SPEED_10000;
2708                 bp->link_vars.link_status =
2709                         (LINK_STATUS_LINK_UP |
2710                          LINK_STATUS_SPEED_AND_DUPLEX_10GTFD);
2711                 bp->link_vars.link_up = 1;
2712                 bp->link_vars.duplex = DUPLEX_FULL;
2713                 bp->link_vars.flow_ctrl = BNX2X_FLOW_CTRL_NONE;
2714                 __bnx2x_link_report(bp);
2715
2716                 bnx2x_sample_bulletin(bp);
2717
2718                 /* if bulletin board did not have an update for link status
2719                  * __bnx2x_link_report will report current status
2720                  * but it will NOT duplicate report in case of already reported
2721                  * during sampling bulletin board.
2722                  */
2723                 bnx2x_stats_handle(bp, STATS_EVENT_LINK_UP);
2724         }
2725 }
2726
2727 static int bnx2x_afex_func_update(struct bnx2x *bp, u16 vifid,
2728                                   u16 vlan_val, u8 allowed_prio)
2729 {
2730         struct bnx2x_func_state_params func_params = {NULL};
2731         struct bnx2x_func_afex_update_params *f_update_params =
2732                 &func_params.params.afex_update;
2733
2734         func_params.f_obj = &bp->func_obj;
2735         func_params.cmd = BNX2X_F_CMD_AFEX_UPDATE;
2736
2737         /* no need to wait for RAMROD completion, so don't
2738          * set RAMROD_COMP_WAIT flag
2739          */
2740
2741         f_update_params->vif_id = vifid;
2742         f_update_params->afex_default_vlan = vlan_val;
2743         f_update_params->allowed_priorities = allowed_prio;
2744
2745         /* if ramrod can not be sent, response to MCP immediately */
2746         if (bnx2x_func_state_change(bp, &func_params) < 0)
2747                 bnx2x_fw_command(bp, DRV_MSG_CODE_AFEX_VIFSET_ACK, 0);
2748
2749         return 0;
2750 }
2751
2752 static int bnx2x_afex_handle_vif_list_cmd(struct bnx2x *bp, u8 cmd_type,
2753                                           u16 vif_index, u8 func_bit_map)
2754 {
2755         struct bnx2x_func_state_params func_params = {NULL};
2756         struct bnx2x_func_afex_viflists_params *update_params =
2757                 &func_params.params.afex_viflists;
2758         int rc;
2759         u32 drv_msg_code;
2760
2761         /* validate only LIST_SET and LIST_GET are received from switch */
2762         if ((cmd_type != VIF_LIST_RULE_GET) && (cmd_type != VIF_LIST_RULE_SET))
2763                 BNX2X_ERR("BUG! afex_handle_vif_list_cmd invalid type 0x%x\n",
2764                           cmd_type);
2765
2766         func_params.f_obj = &bp->func_obj;
2767         func_params.cmd = BNX2X_F_CMD_AFEX_VIFLISTS;
2768
2769         /* set parameters according to cmd_type */
2770         update_params->afex_vif_list_command = cmd_type;
2771         update_params->vif_list_index = vif_index;
2772         update_params->func_bit_map =
2773                 (cmd_type == VIF_LIST_RULE_GET) ? 0 : func_bit_map;
2774         update_params->func_to_clear = 0;
2775         drv_msg_code =
2776                 (cmd_type == VIF_LIST_RULE_GET) ?
2777                 DRV_MSG_CODE_AFEX_LISTGET_ACK :
2778                 DRV_MSG_CODE_AFEX_LISTSET_ACK;
2779
2780         /* if ramrod can not be sent, respond to MCP immediately for
2781          * SET and GET requests (other are not triggered from MCP)
2782          */
2783         rc = bnx2x_func_state_change(bp, &func_params);
2784         if (rc < 0)
2785                 bnx2x_fw_command(bp, drv_msg_code, 0);
2786
2787         return 0;
2788 }
2789
2790 static void bnx2x_handle_afex_cmd(struct bnx2x *bp, u32 cmd)
2791 {
2792         struct afex_stats afex_stats;
2793         u32 func = BP_ABS_FUNC(bp);
2794         u32 mf_config;
2795         u16 vlan_val;
2796         u32 vlan_prio;
2797         u16 vif_id;
2798         u8 allowed_prio;
2799         u8 vlan_mode;
2800         u32 addr_to_write, vifid, addrs, stats_type, i;
2801
2802         if (cmd & DRV_STATUS_AFEX_LISTGET_REQ) {
2803                 vifid = SHMEM2_RD(bp, afex_param1_to_driver[BP_FW_MB_IDX(bp)]);
2804                 DP(BNX2X_MSG_MCP,
2805                    "afex: got MCP req LISTGET_REQ for vifid 0x%x\n", vifid);
2806                 bnx2x_afex_handle_vif_list_cmd(bp, VIF_LIST_RULE_GET, vifid, 0);
2807         }
2808
2809         if (cmd & DRV_STATUS_AFEX_LISTSET_REQ) {
2810                 vifid = SHMEM2_RD(bp, afex_param1_to_driver[BP_FW_MB_IDX(bp)]);
2811                 addrs = SHMEM2_RD(bp, afex_param2_to_driver[BP_FW_MB_IDX(bp)]);
2812                 DP(BNX2X_MSG_MCP,
2813                    "afex: got MCP req LISTSET_REQ for vifid 0x%x addrs 0x%x\n",
2814                    vifid, addrs);
2815                 bnx2x_afex_handle_vif_list_cmd(bp, VIF_LIST_RULE_SET, vifid,
2816                                                addrs);
2817         }
2818
2819         if (cmd & DRV_STATUS_AFEX_STATSGET_REQ) {
2820                 addr_to_write = SHMEM2_RD(bp,
2821                         afex_scratchpad_addr_to_write[BP_FW_MB_IDX(bp)]);
2822                 stats_type = SHMEM2_RD(bp,
2823                         afex_param1_to_driver[BP_FW_MB_IDX(bp)]);
2824
2825                 DP(BNX2X_MSG_MCP,
2826                    "afex: got MCP req STATSGET_REQ, write to addr 0x%x\n",
2827                    addr_to_write);
2828
2829                 bnx2x_afex_collect_stats(bp, (void *)&afex_stats, stats_type);
2830
2831                 /* write response to scratchpad, for MCP */
2832                 for (i = 0; i < (sizeof(struct afex_stats)/sizeof(u32)); i++)
2833                         REG_WR(bp, addr_to_write + i*sizeof(u32),
2834                                *(((u32 *)(&afex_stats))+i));
2835
2836                 /* send ack message to MCP */
2837                 bnx2x_fw_command(bp, DRV_MSG_CODE_AFEX_STATSGET_ACK, 0);
2838         }
2839
2840         if (cmd & DRV_STATUS_AFEX_VIFSET_REQ) {
2841                 mf_config = MF_CFG_RD(bp, func_mf_config[func].config);
2842                 bp->mf_config[BP_VN(bp)] = mf_config;
2843                 DP(BNX2X_MSG_MCP,
2844                    "afex: got MCP req VIFSET_REQ, mf_config 0x%x\n",
2845                    mf_config);
2846
2847                 /* if VIF_SET is "enabled" */
2848                 if (!(mf_config & FUNC_MF_CFG_FUNC_DISABLED)) {
2849                         /* set rate limit directly to internal RAM */
2850                         struct cmng_init_input cmng_input;
2851                         struct rate_shaping_vars_per_vn m_rs_vn;
2852                         size_t size = sizeof(struct rate_shaping_vars_per_vn);
2853                         u32 addr = BAR_XSTRORM_INTMEM +
2854                             XSTORM_RATE_SHAPING_PER_VN_VARS_OFFSET(BP_FUNC(bp));
2855
2856                         bp->mf_config[BP_VN(bp)] = mf_config;
2857
2858                         bnx2x_calc_vn_max(bp, BP_VN(bp), &cmng_input);
2859                         m_rs_vn.vn_counter.rate =
2860                                 cmng_input.vnic_max_rate[BP_VN(bp)];
2861                         m_rs_vn.vn_counter.quota =
2862                                 (m_rs_vn.vn_counter.rate *
2863                                  RS_PERIODIC_TIMEOUT_USEC) / 8;
2864
2865                         __storm_memset_struct(bp, addr, size, (u32 *)&m_rs_vn);
2866
2867                         /* read relevant values from mf_cfg struct in shmem */
2868                         vif_id =
2869                                 (MF_CFG_RD(bp, func_mf_config[func].e1hov_tag) &
2870                                  FUNC_MF_CFG_E1HOV_TAG_MASK) >>
2871                                 FUNC_MF_CFG_E1HOV_TAG_SHIFT;
2872                         vlan_val =
2873                                 (MF_CFG_RD(bp, func_mf_config[func].e1hov_tag) &
2874                                  FUNC_MF_CFG_AFEX_VLAN_MASK) >>
2875                                 FUNC_MF_CFG_AFEX_VLAN_SHIFT;
2876                         vlan_prio = (mf_config &
2877                                      FUNC_MF_CFG_TRANSMIT_PRIORITY_MASK) >>
2878                                     FUNC_MF_CFG_TRANSMIT_PRIORITY_SHIFT;
2879                         vlan_val |= (vlan_prio << VLAN_PRIO_SHIFT);
2880                         vlan_mode =
2881                                 (MF_CFG_RD(bp,
2882                                            func_mf_config[func].afex_config) &
2883                                  FUNC_MF_CFG_AFEX_VLAN_MODE_MASK) >>
2884                                 FUNC_MF_CFG_AFEX_VLAN_MODE_SHIFT;
2885                         allowed_prio =
2886                                 (MF_CFG_RD(bp,
2887                                            func_mf_config[func].afex_config) &
2888                                  FUNC_MF_CFG_AFEX_COS_FILTER_MASK) >>
2889                                 FUNC_MF_CFG_AFEX_COS_FILTER_SHIFT;
2890
2891                         /* send ramrod to FW, return in case of failure */
2892                         if (bnx2x_afex_func_update(bp, vif_id, vlan_val,
2893                                                    allowed_prio))
2894                                 return;
2895
2896                         bp->afex_def_vlan_tag = vlan_val;
2897                         bp->afex_vlan_mode = vlan_mode;
2898                 } else {
2899                         /* notify link down because BP->flags is disabled */
2900                         bnx2x_link_report(bp);
2901
2902                         /* send INVALID VIF ramrod to FW */
2903                         bnx2x_afex_func_update(bp, 0xFFFF, 0, 0);
2904
2905                         /* Reset the default afex VLAN */
2906                         bp->afex_def_vlan_tag = -1;
2907                 }
2908         }
2909 }
2910
2911 static void bnx2x_handle_update_svid_cmd(struct bnx2x *bp)
2912 {
2913         struct bnx2x_func_switch_update_params *switch_update_params;
2914         struct bnx2x_func_state_params func_params;
2915
2916         memset(&func_params, 0, sizeof(struct bnx2x_func_state_params));
2917         switch_update_params = &func_params.params.switch_update;
2918         func_params.f_obj = &bp->func_obj;
2919         func_params.cmd = BNX2X_F_CMD_SWITCH_UPDATE;
2920
2921         if (IS_MF_UFP(bp) || IS_MF_BD(bp)) {
2922                 int func = BP_ABS_FUNC(bp);
2923                 u32 val;
2924
2925                 /* Re-learn the S-tag from shmem */
2926                 val = MF_CFG_RD(bp, func_mf_config[func].e1hov_tag) &
2927                                 FUNC_MF_CFG_E1HOV_TAG_MASK;
2928                 if (val != FUNC_MF_CFG_E1HOV_TAG_DEFAULT) {
2929                         bp->mf_ov = val;
2930                 } else {
2931                         BNX2X_ERR("Got an SVID event, but no tag is configured in shmem\n");
2932                         goto fail;
2933                 }
2934
2935                 /* Configure new S-tag in LLH */
2936                 REG_WR(bp, NIG_REG_LLH0_FUNC_VLAN_ID + BP_PORT(bp) * 8,
2937                        bp->mf_ov);
2938
2939                 /* Send Ramrod to update FW of change */
2940                 __set_bit(BNX2X_F_UPDATE_SD_VLAN_TAG_CHNG,
2941                           &switch_update_params->changes);
2942                 switch_update_params->vlan = bp->mf_ov;
2943
2944                 if (bnx2x_func_state_change(bp, &func_params) < 0) {
2945                         BNX2X_ERR("Failed to configure FW of S-tag Change to %02x\n",
2946                                   bp->mf_ov);
2947                         goto fail;
2948                 } else {
2949                         DP(BNX2X_MSG_MCP, "Configured S-tag %02x\n",
2950                            bp->mf_ov);
2951                 }
2952         } else {
2953                 goto fail;
2954         }
2955
2956         bnx2x_fw_command(bp, DRV_MSG_CODE_OEM_UPDATE_SVID_OK, 0);
2957         return;
2958 fail:
2959         bnx2x_fw_command(bp, DRV_MSG_CODE_OEM_UPDATE_SVID_FAILURE, 0);
2960 }
2961
2962 static void bnx2x_pmf_update(struct bnx2x *bp)
2963 {
2964         int port = BP_PORT(bp);
2965         u32 val;
2966
2967         bp->port.pmf = 1;
2968         DP(BNX2X_MSG_MCP, "pmf %d\n", bp->port.pmf);
2969
2970         /*
2971          * We need the mb() to ensure the ordering between the writing to
2972          * bp->port.pmf here and reading it from the bnx2x_periodic_task().
2973          */
2974         smp_mb();
2975
2976         /* queue a periodic task */
2977         queue_delayed_work(bnx2x_wq, &bp->period_task, 0);
2978
2979         bnx2x_dcbx_pmf_update(bp);
2980
2981         /* enable nig attention */
2982         val = (0xff0f | (1 << (BP_VN(bp) + 4)));
2983         if (bp->common.int_block == INT_BLOCK_HC) {
2984                 REG_WR(bp, HC_REG_TRAILING_EDGE_0 + port*8, val);
2985                 REG_WR(bp, HC_REG_LEADING_EDGE_0 + port*8, val);
2986         } else if (!CHIP_IS_E1x(bp)) {
2987                 REG_WR(bp, IGU_REG_TRAILING_EDGE_LATCH, val);
2988                 REG_WR(bp, IGU_REG_LEADING_EDGE_LATCH, val);
2989         }
2990
2991         bnx2x_stats_handle(bp, STATS_EVENT_PMF);
2992 }
2993
2994 /* end of Link */
2995
2996 /* slow path */
2997
2998 /*
2999  * General service functions
3000  */
3001
3002 /* send the MCP a request, block until there is a reply */
3003 u32 bnx2x_fw_command(struct bnx2x *bp, u32 command, u32 param)
3004 {
3005         int mb_idx = BP_FW_MB_IDX(bp);
3006         u32 seq;
3007         u32 rc = 0;
3008         u32 cnt = 1;
3009         u8 delay = CHIP_REV_IS_SLOW(bp) ? 100 : 10;
3010
3011         mutex_lock(&bp->fw_mb_mutex);
3012         seq = ++bp->fw_seq;
3013         SHMEM_WR(bp, func_mb[mb_idx].drv_mb_param, param);
3014         SHMEM_WR(bp, func_mb[mb_idx].drv_mb_header, (command | seq));
3015
3016         DP(BNX2X_MSG_MCP, "wrote command (%x) to FW MB param 0x%08x\n",
3017                         (command | seq), param);
3018
3019         do {
3020                 /* let the FW do it's magic ... */
3021                 msleep(delay);
3022
3023                 rc = SHMEM_RD(bp, func_mb[mb_idx].fw_mb_header);
3024
3025                 /* Give the FW up to 5 second (500*10ms) */
3026         } while ((seq != (rc & FW_MSG_SEQ_NUMBER_MASK)) && (cnt++ < 500));
3027
3028         DP(BNX2X_MSG_MCP, "[after %d ms] read (%x) seq is (%x) from FW MB\n",
3029            cnt*delay, rc, seq);
3030
3031         /* is this a reply to our command? */
3032         if (seq == (rc & FW_MSG_SEQ_NUMBER_MASK))
3033                 rc &= FW_MSG_CODE_MASK;
3034         else {
3035                 /* FW BUG! */
3036                 BNX2X_ERR("FW failed to respond!\n");
3037                 bnx2x_fw_dump(bp);
3038                 rc = 0;
3039         }
3040         mutex_unlock(&bp->fw_mb_mutex);
3041
3042         return rc;
3043 }
3044
3045 static void storm_memset_func_cfg(struct bnx2x *bp,
3046                                  struct tstorm_eth_function_common_config *tcfg,
3047                                  u16 abs_fid)
3048 {
3049         size_t size = sizeof(struct tstorm_eth_function_common_config);
3050
3051         u32 addr = BAR_TSTRORM_INTMEM +
3052                         TSTORM_FUNCTION_COMMON_CONFIG_OFFSET(abs_fid);
3053
3054         __storm_memset_struct(bp, addr, size, (u32 *)tcfg);
3055 }
3056
3057 void bnx2x_func_init(struct bnx2x *bp, struct bnx2x_func_init_params *p)
3058 {
3059         if (CHIP_IS_E1x(bp)) {
3060                 struct tstorm_eth_function_common_config tcfg = {0};
3061
3062                 storm_memset_func_cfg(bp, &tcfg, p->func_id);
3063         }
3064
3065         /* Enable the function in the FW */
3066         storm_memset_vf_to_pf(bp, p->func_id, p->pf_id);
3067         storm_memset_func_en(bp, p->func_id, 1);
3068
3069         /* spq */
3070         if (p->func_flgs & FUNC_FLG_SPQ) {
3071                 storm_memset_spq_addr(bp, p->spq_map, p->func_id);
3072                 REG_WR(bp, XSEM_REG_FAST_MEMORY +
3073                        XSTORM_SPQ_PROD_OFFSET(p->func_id), p->spq_prod);
3074         }
3075 }
3076
3077 /**
3078  * bnx2x_get_common_flags - Return common flags
3079  *
3080  * @bp          device handle
3081  * @fp          queue handle
3082  * @zero_stats  TRUE if statistics zeroing is needed
3083  *
3084  * Return the flags that are common for the Tx-only and not normal connections.
3085  */
3086 static unsigned long bnx2x_get_common_flags(struct bnx2x *bp,
3087                                             struct bnx2x_fastpath *fp,
3088                                             bool zero_stats)
3089 {
3090         unsigned long flags = 0;
3091
3092         /* PF driver will always initialize the Queue to an ACTIVE state */
3093         __set_bit(BNX2X_Q_FLG_ACTIVE, &flags);
3094
3095         /* tx only connections collect statistics (on the same index as the
3096          * parent connection). The statistics are zeroed when the parent
3097          * connection is initialized.
3098          */
3099
3100         __set_bit(BNX2X_Q_FLG_STATS, &flags);
3101         if (zero_stats)
3102                 __set_bit(BNX2X_Q_FLG_ZERO_STATS, &flags);
3103
3104         if (bp->flags & TX_SWITCHING)
3105                 __set_bit(BNX2X_Q_FLG_TX_SWITCH, &flags);
3106
3107         __set_bit(BNX2X_Q_FLG_PCSUM_ON_PKT, &flags);
3108         __set_bit(BNX2X_Q_FLG_TUN_INC_INNER_IP_ID, &flags);
3109
3110 #ifdef BNX2X_STOP_ON_ERROR
3111         __set_bit(BNX2X_Q_FLG_TX_SEC, &flags);
3112 #endif
3113
3114         return flags;
3115 }
3116
3117 static unsigned long bnx2x_get_q_flags(struct bnx2x *bp,
3118                                        struct bnx2x_fastpath *fp,
3119                                        bool leading)
3120 {
3121         unsigned long flags = 0;
3122
3123         /* calculate other queue flags */
3124         if (IS_MF_SD(bp))
3125                 __set_bit(BNX2X_Q_FLG_OV, &flags);
3126
3127         if (IS_FCOE_FP(fp)) {
3128                 __set_bit(BNX2X_Q_FLG_FCOE, &flags);
3129                 /* For FCoE - force usage of default priority (for afex) */
3130                 __set_bit(BNX2X_Q_FLG_FORCE_DEFAULT_PRI, &flags);
3131         }
3132
3133         if (fp->mode != TPA_MODE_DISABLED) {
3134                 __set_bit(BNX2X_Q_FLG_TPA, &flags);
3135                 __set_bit(BNX2X_Q_FLG_TPA_IPV6, &flags);
3136                 if (fp->mode == TPA_MODE_GRO)
3137                         __set_bit(BNX2X_Q_FLG_TPA_GRO, &flags);
3138         }
3139
3140         if (leading) {
3141                 __set_bit(BNX2X_Q_FLG_LEADING_RSS, &flags);
3142                 __set_bit(BNX2X_Q_FLG_MCAST, &flags);
3143         }
3144
3145         /* Always set HW VLAN stripping */
3146         __set_bit(BNX2X_Q_FLG_VLAN, &flags);
3147
3148         /* configure silent vlan removal */
3149         if (IS_MF_AFEX(bp))
3150                 __set_bit(BNX2X_Q_FLG_SILENT_VLAN_REM, &flags);
3151
3152         return flags | bnx2x_get_common_flags(bp, fp, true);
3153 }
3154
3155 static void bnx2x_pf_q_prep_general(struct bnx2x *bp,
3156         struct bnx2x_fastpath *fp, struct bnx2x_general_setup_params *gen_init,
3157         u8 cos)
3158 {
3159         gen_init->stat_id = bnx2x_stats_id(fp);
3160         gen_init->spcl_id = fp->cl_id;
3161
3162         /* Always use mini-jumbo MTU for FCoE L2 ring */
3163         if (IS_FCOE_FP(fp))
3164                 gen_init->mtu = BNX2X_FCOE_MINI_JUMBO_MTU;
3165         else
3166                 gen_init->mtu = bp->dev->mtu;
3167
3168         gen_init->cos = cos;
3169
3170         gen_init->fp_hsi = ETH_FP_HSI_VERSION;
3171 }
3172
3173 static void bnx2x_pf_rx_q_prep(struct bnx2x *bp,
3174         struct bnx2x_fastpath *fp, struct rxq_pause_params *pause,
3175         struct bnx2x_rxq_setup_params *rxq_init)
3176 {
3177         u8 max_sge = 0;
3178         u16 sge_sz = 0;
3179         u16 tpa_agg_size = 0;
3180
3181         if (fp->mode != TPA_MODE_DISABLED) {
3182                 pause->sge_th_lo = SGE_TH_LO(bp);
3183                 pause->sge_th_hi = SGE_TH_HI(bp);
3184
3185                 /* validate SGE ring has enough to cross high threshold */
3186                 WARN_ON(bp->dropless_fc &&
3187                                 pause->sge_th_hi + FW_PREFETCH_CNT >
3188                                 MAX_RX_SGE_CNT * NUM_RX_SGE_PAGES);
3189
3190                 tpa_agg_size = TPA_AGG_SIZE;
3191                 max_sge = SGE_PAGE_ALIGN(bp->dev->mtu) >>
3192                         SGE_PAGE_SHIFT;
3193                 max_sge = ((max_sge + PAGES_PER_SGE - 1) &
3194                           (~(PAGES_PER_SGE-1))) >> PAGES_PER_SGE_SHIFT;
3195                 sge_sz = (u16)min_t(u32, SGE_PAGES, 0xffff);
3196         }
3197
3198         /* pause - not for e1 */
3199         if (!CHIP_IS_E1(bp)) {
3200                 pause->bd_th_lo = BD_TH_LO(bp);
3201                 pause->bd_th_hi = BD_TH_HI(bp);
3202
3203                 pause->rcq_th_lo = RCQ_TH_LO(bp);
3204                 pause->rcq_th_hi = RCQ_TH_HI(bp);
3205                 /*
3206                  * validate that rings have enough entries to cross
3207                  * high thresholds
3208                  */
3209                 WARN_ON(bp->dropless_fc &&
3210                                 pause->bd_th_hi + FW_PREFETCH_CNT >
3211                                 bp->rx_ring_size);
3212                 WARN_ON(bp->dropless_fc &&
3213                                 pause->rcq_th_hi + FW_PREFETCH_CNT >
3214                                 NUM_RCQ_RINGS * MAX_RCQ_DESC_CNT);
3215
3216                 pause->pri_map = 1;
3217         }
3218
3219         /* rxq setup */
3220         rxq_init->dscr_map = fp->rx_desc_mapping;
3221         rxq_init->sge_map = fp->rx_sge_mapping;
3222         rxq_init->rcq_map = fp->rx_comp_mapping;
3223         rxq_init->rcq_np_map = fp->rx_comp_mapping + BCM_PAGE_SIZE;
3224
3225         /* This should be a maximum number of data bytes that may be
3226          * placed on the BD (not including paddings).
3227          */
3228         rxq_init->buf_sz = fp->rx_buf_size - BNX2X_FW_RX_ALIGN_START -
3229                            BNX2X_FW_RX_ALIGN_END - IP_HEADER_ALIGNMENT_PADDING;
3230
3231         rxq_init->cl_qzone_id = fp->cl_qzone_id;
3232         rxq_init->tpa_agg_sz = tpa_agg_size;
3233         rxq_init->sge_buf_sz = sge_sz;
3234         rxq_init->max_sges_pkt = max_sge;
3235         rxq_init->rss_engine_id = BP_FUNC(bp);
3236         rxq_init->mcast_engine_id = BP_FUNC(bp);
3237
3238         /* Maximum number or simultaneous TPA aggregation for this Queue.
3239          *
3240          * For PF Clients it should be the maximum available number.
3241          * VF driver(s) may want to define it to a smaller value.
3242          */
3243         rxq_init->max_tpa_queues = MAX_AGG_QS(bp);
3244
3245         rxq_init->cache_line_log = BNX2X_RX_ALIGN_SHIFT;
3246         rxq_init->fw_sb_id = fp->fw_sb_id;
3247
3248         if (IS_FCOE_FP(fp))
3249                 rxq_init->sb_cq_index = HC_SP_INDEX_ETH_FCOE_RX_CQ_CONS;
3250         else
3251                 rxq_init->sb_cq_index = HC_INDEX_ETH_RX_CQ_CONS;
3252         /* configure silent vlan removal
3253          * if multi function mode is afex, then mask default vlan
3254          */
3255         if (IS_MF_AFEX(bp)) {
3256                 rxq_init->silent_removal_value = bp->afex_def_vlan_tag;
3257                 rxq_init->silent_removal_mask = VLAN_VID_MASK;
3258         }
3259 }
3260
3261 static void bnx2x_pf_tx_q_prep(struct bnx2x *bp,
3262         struct bnx2x_fastpath *fp, struct bnx2x_txq_setup_params *txq_init,
3263         u8 cos)
3264 {
3265         txq_init->dscr_map = fp->txdata_ptr[cos]->tx_desc_mapping;
3266         txq_init->sb_cq_index = HC_INDEX_ETH_FIRST_TX_CQ_CONS + cos;
3267         txq_init->traffic_type = LLFC_TRAFFIC_TYPE_NW;
3268         txq_init->fw_sb_id = fp->fw_sb_id;
3269
3270         /*
3271          * set the tss leading client id for TX classification ==
3272          * leading RSS client id
3273          */
3274         txq_init->tss_leading_cl_id = bnx2x_fp(bp, 0, cl_id);
3275
3276         if (IS_FCOE_FP(fp)) {
3277                 txq_init->sb_cq_index = HC_SP_INDEX_ETH_FCOE_TX_CQ_CONS;
3278                 txq_init->traffic_type = LLFC_TRAFFIC_TYPE_FCOE;
3279         }
3280 }
3281
3282 static void bnx2x_pf_init(struct bnx2x *bp)
3283 {
3284         struct bnx2x_func_init_params func_init = {0};
3285         struct event_ring_data eq_data = { {0} };
3286         u16 flags;
3287
3288         if (!CHIP_IS_E1x(bp)) {
3289                 /* reset IGU PF statistics: MSIX + ATTN */
3290                 /* PF */
3291                 REG_WR(bp, IGU_REG_STATISTIC_NUM_MESSAGE_SENT +
3292                            BNX2X_IGU_STAS_MSG_VF_CNT*4 +
3293                            (CHIP_MODE_IS_4_PORT(bp) ?
3294                                 BP_FUNC(bp) : BP_VN(bp))*4, 0);
3295                 /* ATTN */
3296                 REG_WR(bp, IGU_REG_STATISTIC_NUM_MESSAGE_SENT +
3297                            BNX2X_IGU_STAS_MSG_VF_CNT*4 +
3298                            BNX2X_IGU_STAS_MSG_PF_CNT*4 +
3299                            (CHIP_MODE_IS_4_PORT(bp) ?
3300                                 BP_FUNC(bp) : BP_VN(bp))*4, 0);
3301         }
3302
3303         /* function setup flags */
3304         flags = (FUNC_FLG_STATS | FUNC_FLG_LEADING | FUNC_FLG_SPQ);
3305
3306         /* This flag is relevant for E1x only.
3307          * E2 doesn't have a TPA configuration in a function level.
3308          */
3309         flags |= (bp->dev->features & NETIF_F_LRO) ? FUNC_FLG_TPA : 0;
3310
3311         func_init.func_flgs = flags;
3312         func_init.pf_id = BP_FUNC(bp);
3313         func_init.func_id = BP_FUNC(bp);
3314         func_init.spq_map = bp->spq_mapping;
3315         func_init.spq_prod = bp->spq_prod_idx;
3316
3317         bnx2x_func_init(bp, &func_init);
3318
3319         memset(&(bp->cmng), 0, sizeof(struct cmng_struct_per_port));
3320
3321         /*
3322          * Congestion management values depend on the link rate
3323          * There is no active link so initial link rate is set to 10 Gbps.
3324          * When the link comes up The congestion management values are
3325          * re-calculated according to the actual link rate.
3326          */
3327         bp->link_vars.line_speed = SPEED_10000;
3328         bnx2x_cmng_fns_init(bp, true, bnx2x_get_cmng_fns_mode(bp));
3329
3330         /* Only the PMF sets the HW */
3331         if (bp->port.pmf)
3332                 storm_memset_cmng(bp, &bp->cmng, BP_PORT(bp));
3333
3334         /* init Event Queue - PCI bus guarantees correct endianity*/
3335         eq_data.base_addr.hi = U64_HI(bp->eq_mapping);
3336         eq_data.base_addr.lo = U64_LO(bp->eq_mapping);
3337         eq_data.producer = bp->eq_prod;
3338         eq_data.index_id = HC_SP_INDEX_EQ_CONS;
3339         eq_data.sb_id = DEF_SB_ID;
3340         storm_memset_eq_data(bp, &eq_data, BP_FUNC(bp));
3341 }
3342
3343 static void bnx2x_e1h_disable(struct bnx2x *bp)
3344 {
3345         int port = BP_PORT(bp);
3346
3347         bnx2x_tx_disable(bp);
3348
3349         REG_WR(bp, NIG_REG_LLH0_FUNC_EN + port*8, 0);
3350 }
3351
3352 static void bnx2x_e1h_enable(struct bnx2x *bp)
3353 {
3354         int port = BP_PORT(bp);
3355
3356         if (!(IS_MF_UFP(bp) && BNX2X_IS_MF_SD_PROTOCOL_FCOE(bp)))
3357                 REG_WR(bp, NIG_REG_LLH0_FUNC_EN + port * 8, 1);
3358
3359         /* Tx queue should be only re-enabled */
3360         netif_tx_wake_all_queues(bp->dev);
3361
3362         /*
3363          * Should not call netif_carrier_on since it will be called if the link
3364          * is up when checking for link state
3365          */
3366 }
3367
3368 #define DRV_INFO_ETH_STAT_NUM_MACS_REQUIRED 3
3369
3370 static void bnx2x_drv_info_ether_stat(struct bnx2x *bp)
3371 {
3372         struct eth_stats_info *ether_stat =
3373                 &bp->slowpath->drv_info_to_mcp.ether_stat;
3374         struct bnx2x_vlan_mac_obj *mac_obj =
3375                 &bp->sp_objs->mac_obj;
3376         int i;
3377
3378         strlcpy(ether_stat->version, DRV_MODULE_VERSION,
3379                 ETH_STAT_INFO_VERSION_LEN);
3380
3381         /* get DRV_INFO_ETH_STAT_NUM_MACS_REQUIRED macs, placing them in the
3382          * mac_local field in ether_stat struct. The base address is offset by 2
3383          * bytes to account for the field being 8 bytes but a mac address is
3384          * only 6 bytes. Likewise, the stride for the get_n_elements function is
3385          * 2 bytes to compensate from the 6 bytes of a mac to the 8 bytes
3386          * allocated by the ether_stat struct, so the macs will land in their
3387          * proper positions.
3388          */
3389         for (i = 0; i < DRV_INFO_ETH_STAT_NUM_MACS_REQUIRED; i++)
3390                 memset(ether_stat->mac_local + i, 0,
3391                        sizeof(ether_stat->mac_local[0]));
3392         mac_obj->get_n_elements(bp, &bp->sp_objs[0].mac_obj,
3393                                 DRV_INFO_ETH_STAT_NUM_MACS_REQUIRED,
3394                                 ether_stat->mac_local + MAC_PAD, MAC_PAD,
3395                                 ETH_ALEN);
3396         ether_stat->mtu_size = bp->dev->mtu;
3397         if (bp->dev->features & NETIF_F_RXCSUM)
3398                 ether_stat->feature_flags |= FEATURE_ETH_CHKSUM_OFFLOAD_MASK;
3399         if (bp->dev->features & NETIF_F_TSO)
3400                 ether_stat->feature_flags |= FEATURE_ETH_LSO_MASK;
3401         ether_stat->feature_flags |= bp->common.boot_mode;
3402
3403         ether_stat->promiscuous_mode = (bp->dev->flags & IFF_PROMISC) ? 1 : 0;
3404
3405         ether_stat->txq_size = bp->tx_ring_size;
3406         ether_stat->rxq_size = bp->rx_ring_size;
3407
3408 #ifdef CONFIG_BNX2X_SRIOV
3409         ether_stat->vf_cnt = IS_SRIOV(bp) ? bp->vfdb->sriov.nr_virtfn : 0;
3410 #endif
3411 }
3412
3413 static void bnx2x_drv_info_fcoe_stat(struct bnx2x *bp)
3414 {
3415         struct bnx2x_dcbx_app_params *app = &bp->dcbx_port_params.app;
3416         struct fcoe_stats_info *fcoe_stat =
3417                 &bp->slowpath->drv_info_to_mcp.fcoe_stat;
3418
3419         if (!CNIC_LOADED(bp))
3420                 return;
3421
3422         memcpy(fcoe_stat->mac_local + MAC_PAD, bp->fip_mac, ETH_ALEN);
3423
3424         fcoe_stat->qos_priority =
3425                 app->traffic_type_priority[LLFC_TRAFFIC_TYPE_FCOE];
3426
3427         /* insert FCoE stats from ramrod response */
3428         if (!NO_FCOE(bp)) {
3429                 struct tstorm_per_queue_stats *fcoe_q_tstorm_stats =
3430                         &bp->fw_stats_data->queue_stats[FCOE_IDX(bp)].
3431                         tstorm_queue_statistics;
3432
3433                 struct xstorm_per_queue_stats *fcoe_q_xstorm_stats =
3434                         &bp->fw_stats_data->queue_stats[FCOE_IDX(bp)].
3435                         xstorm_queue_statistics;
3436
3437                 struct fcoe_statistics_params *fw_fcoe_stat =
3438                         &bp->fw_stats_data->fcoe;
3439
3440                 ADD_64_LE(fcoe_stat->rx_bytes_hi, LE32_0,
3441                           fcoe_stat->rx_bytes_lo,
3442                           fw_fcoe_stat->rx_stat0.fcoe_rx_byte_cnt);
3443
3444                 ADD_64_LE(fcoe_stat->rx_bytes_hi,
3445                           fcoe_q_tstorm_stats->rcv_ucast_bytes.hi,
3446                           fcoe_stat->rx_bytes_lo,
3447                           fcoe_q_tstorm_stats->rcv_ucast_bytes.lo);
3448
3449                 ADD_64_LE(fcoe_stat->rx_bytes_hi,
3450                           fcoe_q_tstorm_stats->rcv_bcast_bytes.hi,
3451                           fcoe_stat->rx_bytes_lo,
3452                           fcoe_q_tstorm_stats->rcv_bcast_bytes.lo);
3453
3454                 ADD_64_LE(fcoe_stat->rx_bytes_hi,
3455                           fcoe_q_tstorm_stats->rcv_mcast_bytes.hi,
3456                           fcoe_stat->rx_bytes_lo,
3457                           fcoe_q_tstorm_stats->rcv_mcast_bytes.lo);
3458
3459                 ADD_64_LE(fcoe_stat->rx_frames_hi, LE32_0,
3460                           fcoe_stat->rx_frames_lo,
3461                           fw_fcoe_stat->rx_stat0.fcoe_rx_pkt_cnt);
3462
3463                 ADD_64_LE(fcoe_stat->rx_frames_hi, LE32_0,
3464                           fcoe_stat->rx_frames_lo,
3465                           fcoe_q_tstorm_stats->rcv_ucast_pkts);
3466
3467                 ADD_64_LE(fcoe_stat->rx_frames_hi, LE32_0,
3468                           fcoe_stat->rx_frames_lo,
3469                           fcoe_q_tstorm_stats->rcv_bcast_pkts);
3470
3471                 ADD_64_LE(fcoe_stat->rx_frames_hi, LE32_0,
3472                           fcoe_stat->rx_frames_lo,
3473                           fcoe_q_tstorm_stats->rcv_mcast_pkts);
3474
3475                 ADD_64_LE(fcoe_stat->tx_bytes_hi, LE32_0,
3476                           fcoe_stat->tx_bytes_lo,
3477                           fw_fcoe_stat->tx_stat.fcoe_tx_byte_cnt);
3478
3479                 ADD_64_LE(fcoe_stat->tx_bytes_hi,
3480                           fcoe_q_xstorm_stats->ucast_bytes_sent.hi,
3481                           fcoe_stat->tx_bytes_lo,
3482                           fcoe_q_xstorm_stats->ucast_bytes_sent.lo);
3483
3484                 ADD_64_LE(fcoe_stat->tx_bytes_hi,
3485                           fcoe_q_xstorm_stats->bcast_bytes_sent.hi,
3486                           fcoe_stat->tx_bytes_lo,
3487                           fcoe_q_xstorm_stats->bcast_bytes_sent.lo);
3488
3489                 ADD_64_LE(fcoe_stat->tx_bytes_hi,
3490                           fcoe_q_xstorm_stats->mcast_bytes_sent.hi,
3491                           fcoe_stat->tx_bytes_lo,
3492                           fcoe_q_xstorm_stats->mcast_bytes_sent.lo);
3493
3494                 ADD_64_LE(fcoe_stat->tx_frames_hi, LE32_0,
3495                           fcoe_stat->tx_frames_lo,
3496                           fw_fcoe_stat->tx_stat.fcoe_tx_pkt_cnt);
3497
3498                 ADD_64_LE(fcoe_stat->tx_frames_hi, LE32_0,
3499                           fcoe_stat->tx_frames_lo,
3500                           fcoe_q_xstorm_stats->ucast_pkts_sent);
3501
3502                 ADD_64_LE(fcoe_stat->tx_frames_hi, LE32_0,
3503                           fcoe_stat->tx_frames_lo,
3504                           fcoe_q_xstorm_stats->bcast_pkts_sent);
3505
3506                 ADD_64_LE(fcoe_stat->tx_frames_hi, LE32_0,
3507                           fcoe_stat->tx_frames_lo,
3508                           fcoe_q_xstorm_stats->mcast_pkts_sent);
3509         }
3510
3511         /* ask L5 driver to add data to the struct */
3512         bnx2x_cnic_notify(bp, CNIC_CTL_FCOE_STATS_GET_CMD);
3513 }
3514
3515 static void bnx2x_drv_info_iscsi_stat(struct bnx2x *bp)
3516 {
3517         struct bnx2x_dcbx_app_params *app = &bp->dcbx_port_params.app;
3518         struct iscsi_stats_info *iscsi_stat =
3519                 &bp->slowpath->drv_info_to_mcp.iscsi_stat;
3520
3521         if (!CNIC_LOADED(bp))
3522                 return;
3523
3524         memcpy(iscsi_stat->mac_local + MAC_PAD, bp->cnic_eth_dev.iscsi_mac,
3525                ETH_ALEN);
3526
3527         iscsi_stat->qos_priority =
3528                 app->traffic_type_priority[LLFC_TRAFFIC_TYPE_ISCSI];
3529
3530         /* ask L5 driver to add data to the struct */
3531         bnx2x_cnic_notify(bp, CNIC_CTL_ISCSI_STATS_GET_CMD);
3532 }
3533
3534 /* called due to MCP event (on pmf):
3535  *      reread new bandwidth configuration
3536  *      configure FW
3537  *      notify others function about the change
3538  */
3539 static void bnx2x_config_mf_bw(struct bnx2x *bp)
3540 {
3541         if (bp->link_vars.link_up) {
3542                 bnx2x_cmng_fns_init(bp, true, CMNG_FNS_MINMAX);
3543                 bnx2x_link_sync_notify(bp);
3544         }
3545         storm_memset_cmng(bp, &bp->cmng, BP_PORT(bp));
3546 }
3547
3548 static void bnx2x_set_mf_bw(struct bnx2x *bp)
3549 {
3550         bnx2x_config_mf_bw(bp);
3551         bnx2x_fw_command(bp, DRV_MSG_CODE_SET_MF_BW_ACK, 0);
3552 }
3553
3554 static void bnx2x_handle_eee_event(struct bnx2x *bp)
3555 {
3556         DP(BNX2X_MSG_MCP, "EEE - LLDP event\n");
3557         bnx2x_fw_command(bp, DRV_MSG_CODE_EEE_RESULTS_ACK, 0);
3558 }
3559
3560 #define BNX2X_UPDATE_DRV_INFO_IND_LENGTH        (20)
3561 #define BNX2X_UPDATE_DRV_INFO_IND_COUNT         (25)
3562
3563 static void bnx2x_handle_drv_info_req(struct bnx2x *bp)
3564 {
3565         enum drv_info_opcode op_code;
3566         u32 drv_info_ctl = SHMEM2_RD(bp, drv_info_control);
3567         bool release = false;
3568         int wait;
3569
3570         /* if drv_info version supported by MFW doesn't match - send NACK */
3571         if ((drv_info_ctl & DRV_INFO_CONTROL_VER_MASK) != DRV_INFO_CUR_VER) {
3572                 bnx2x_fw_command(bp, DRV_MSG_CODE_DRV_INFO_NACK, 0);
3573                 return;
3574         }
3575
3576         op_code = (drv_info_ctl & DRV_INFO_CONTROL_OP_CODE_MASK) >>
3577                   DRV_INFO_CONTROL_OP_CODE_SHIFT;
3578
3579         /* Must prevent other flows from accessing drv_info_to_mcp */
3580         mutex_lock(&bp->drv_info_mutex);
3581
3582         memset(&bp->slowpath->drv_info_to_mcp, 0,
3583                sizeof(union drv_info_to_mcp));
3584
3585         switch (op_code) {
3586         case ETH_STATS_OPCODE:
3587                 bnx2x_drv_info_ether_stat(bp);
3588                 break;
3589         case FCOE_STATS_OPCODE:
3590                 bnx2x_drv_info_fcoe_stat(bp);
3591                 break;
3592         case ISCSI_STATS_OPCODE:
3593                 bnx2x_drv_info_iscsi_stat(bp);
3594                 break;
3595         default:
3596                 /* if op code isn't supported - send NACK */
3597                 bnx2x_fw_command(bp, DRV_MSG_CODE_DRV_INFO_NACK, 0);
3598                 goto out;
3599         }
3600
3601         /* if we got drv_info attn from MFW then these fields are defined in
3602          * shmem2 for sure
3603          */
3604         SHMEM2_WR(bp, drv_info_host_addr_lo,
3605                 U64_LO(bnx2x_sp_mapping(bp, drv_info_to_mcp)));
3606         SHMEM2_WR(bp, drv_info_host_addr_hi,
3607                 U64_HI(bnx2x_sp_mapping(bp, drv_info_to_mcp)));
3608
3609         bnx2x_fw_command(bp, DRV_MSG_CODE_DRV_INFO_ACK, 0);
3610
3611         /* Since possible management wants both this and get_driver_version
3612          * need to wait until management notifies us it finished utilizing
3613          * the buffer.
3614          */
3615         if (!SHMEM2_HAS(bp, mfw_drv_indication)) {
3616                 DP(BNX2X_MSG_MCP, "Management does not support indication\n");
3617         } else if (!bp->drv_info_mng_owner) {
3618                 u32 bit = MFW_DRV_IND_READ_DONE_OFFSET((BP_ABS_FUNC(bp) >> 1));
3619
3620                 for (wait = 0; wait < BNX2X_UPDATE_DRV_INFO_IND_COUNT; wait++) {
3621                         u32 indication = SHMEM2_RD(bp, mfw_drv_indication);
3622
3623                         /* Management is done; need to clear indication */
3624                         if (indication & bit) {
3625                                 SHMEM2_WR(bp, mfw_drv_indication,
3626                                           indication & ~bit);
3627                                 release = true;
3628                                 break;
3629                         }
3630
3631                         msleep(BNX2X_UPDATE_DRV_INFO_IND_LENGTH);
3632                 }
3633         }
3634         if (!release) {
3635                 DP(BNX2X_MSG_MCP, "Management did not release indication\n");
3636                 bp->drv_info_mng_owner = true;
3637         }
3638
3639 out:
3640         mutex_unlock(&bp->drv_info_mutex);
3641 }
3642
3643 static u32 bnx2x_update_mng_version_utility(u8 *version, bool bnx2x_format)
3644 {
3645         u8 vals[4];
3646         int i = 0;
3647
3648         if (bnx2x_format) {
3649                 i = sscanf(version, "1.%c%hhd.%hhd.%hhd",
3650                            &vals[0], &vals[1], &vals[2], &vals[3]);
3651                 if (i > 0)
3652                         vals[0] -= '0';
3653         } else {
3654                 i = sscanf(version, "%hhd.%hhd.%hhd.%hhd",
3655                            &vals[0], &vals[1], &vals[2], &vals[3]);
3656         }
3657
3658         while (i < 4)
3659                 vals[i++] = 0;
3660
3661         return (vals[0] << 24) | (vals[1] << 16) | (vals[2] << 8) | vals[3];
3662 }
3663
3664 void bnx2x_update_mng_version(struct bnx2x *bp)
3665 {
3666         u32 iscsiver = DRV_VER_NOT_LOADED;
3667         u32 fcoever = DRV_VER_NOT_LOADED;
3668         u32 ethver = DRV_VER_NOT_LOADED;
3669         int idx = BP_FW_MB_IDX(bp);
3670         u8 *version;
3671
3672         if (!SHMEM2_HAS(bp, func_os_drv_ver))
3673                 return;
3674
3675         mutex_lock(&bp->drv_info_mutex);
3676         /* Must not proceed when `bnx2x_handle_drv_info_req' is feasible */
3677         if (bp->drv_info_mng_owner)
3678                 goto out;
3679
3680         if (bp->state != BNX2X_STATE_OPEN)
3681                 goto out;
3682
3683         /* Parse ethernet driver version */
3684         ethver = bnx2x_update_mng_version_utility(DRV_MODULE_VERSION, true);
3685         if (!CNIC_LOADED(bp))
3686                 goto out;
3687
3688         /* Try getting storage driver version via cnic */
3689         memset(&bp->slowpath->drv_info_to_mcp, 0,
3690                sizeof(union drv_info_to_mcp));
3691         bnx2x_drv_info_iscsi_stat(bp);
3692         version = bp->slowpath->drv_info_to_mcp.iscsi_stat.version;
3693         iscsiver = bnx2x_update_mng_version_utility(version, false);
3694
3695         memset(&bp->slowpath->drv_info_to_mcp, 0,
3696                sizeof(union drv_info_to_mcp));
3697         bnx2x_drv_info_fcoe_stat(bp);
3698         version = bp->slowpath->drv_info_to_mcp.fcoe_stat.version;
3699         fcoever = bnx2x_update_mng_version_utility(version, false);
3700
3701 out:
3702         SHMEM2_WR(bp, func_os_drv_ver[idx].versions[DRV_PERS_ETHERNET], ethver);
3703         SHMEM2_WR(bp, func_os_drv_ver[idx].versions[DRV_PERS_ISCSI], iscsiver);
3704         SHMEM2_WR(bp, func_os_drv_ver[idx].versions[DRV_PERS_FCOE], fcoever);
3705
3706         mutex_unlock(&bp->drv_info_mutex);
3707
3708         DP(BNX2X_MSG_MCP, "Setting driver version: ETH [%08x] iSCSI [%08x] FCoE [%08x]\n",
3709            ethver, iscsiver, fcoever);
3710 }
3711
3712 static void bnx2x_oem_event(struct bnx2x *bp, u32 event)
3713 {
3714         u32 cmd_ok, cmd_fail;
3715
3716         /* sanity */
3717         if (event & DRV_STATUS_DCC_EVENT_MASK &&
3718             event & DRV_STATUS_OEM_EVENT_MASK) {
3719                 BNX2X_ERR("Received simultaneous events %08x\n", event);
3720                 return;
3721         }
3722
3723         if (event & DRV_STATUS_DCC_EVENT_MASK) {
3724                 cmd_fail = DRV_MSG_CODE_DCC_FAILURE;
3725                 cmd_ok = DRV_MSG_CODE_DCC_OK;
3726         } else /* if (event & DRV_STATUS_OEM_EVENT_MASK) */ {
3727                 cmd_fail = DRV_MSG_CODE_OEM_FAILURE;
3728                 cmd_ok = DRV_MSG_CODE_OEM_OK;
3729         }
3730
3731         DP(BNX2X_MSG_MCP, "oem_event 0x%x\n", event);
3732
3733         if (event & (DRV_STATUS_DCC_DISABLE_ENABLE_PF |
3734                      DRV_STATUS_OEM_DISABLE_ENABLE_PF)) {
3735                 /* This is the only place besides the function initialization
3736                  * where the bp->flags can change so it is done without any
3737                  * locks
3738                  */
3739                 if (bp->mf_config[BP_VN(bp)] & FUNC_MF_CFG_FUNC_DISABLED) {
3740                         DP(BNX2X_MSG_MCP, "mf_cfg function disabled\n");
3741                         bp->flags |= MF_FUNC_DIS;
3742
3743                         bnx2x_e1h_disable(bp);
3744                 } else {
3745                         DP(BNX2X_MSG_MCP, "mf_cfg function enabled\n");
3746                         bp->flags &= ~MF_FUNC_DIS;
3747
3748                         bnx2x_e1h_enable(bp);
3749                 }
3750                 event &= ~(DRV_STATUS_DCC_DISABLE_ENABLE_PF |
3751                            DRV_STATUS_OEM_DISABLE_ENABLE_PF);
3752         }
3753
3754         if (event & (DRV_STATUS_DCC_BANDWIDTH_ALLOCATION |
3755                      DRV_STATUS_OEM_BANDWIDTH_ALLOCATION)) {
3756                 bnx2x_config_mf_bw(bp);
3757                 event &= ~(DRV_STATUS_DCC_BANDWIDTH_ALLOCATION |
3758                            DRV_STATUS_OEM_BANDWIDTH_ALLOCATION);
3759         }
3760
3761         /* Report results to MCP */
3762         if (event)
3763                 bnx2x_fw_command(bp, cmd_fail, 0);
3764         else
3765                 bnx2x_fw_command(bp, cmd_ok, 0);
3766 }
3767
3768 /* must be called under the spq lock */
3769 static struct eth_spe *bnx2x_sp_get_next(struct bnx2x *bp)
3770 {
3771         struct eth_spe *next_spe = bp->spq_prod_bd;
3772
3773         if (bp->spq_prod_bd == bp->spq_last_bd) {
3774                 bp->spq_prod_bd = bp->spq;
3775                 bp->spq_prod_idx = 0;
3776                 DP(BNX2X_MSG_SP, "end of spq\n");
3777         } else {
3778                 bp->spq_prod_bd++;
3779                 bp->spq_prod_idx++;
3780         }
3781         return next_spe;
3782 }
3783
3784 /* must be called under the spq lock */
3785 static void bnx2x_sp_prod_update(struct bnx2x *bp)
3786 {
3787         int func = BP_FUNC(bp);
3788
3789         /*
3790          * Make sure that BD data is updated before writing the producer:
3791          * BD data is written to the memory, the producer is read from the
3792          * memory, thus we need a full memory barrier to ensure the ordering.
3793          */
3794         mb();
3795
3796         REG_WR16(bp, BAR_XSTRORM_INTMEM + XSTORM_SPQ_PROD_OFFSET(func),
3797                  bp->spq_prod_idx);
3798         mmiowb();
3799 }
3800
3801 /**
3802  * bnx2x_is_contextless_ramrod - check if the current command ends on EQ
3803  *
3804  * @cmd:        command to check
3805  * @cmd_type:   command type
3806  */
3807 static bool bnx2x_is_contextless_ramrod(int cmd, int cmd_type)
3808 {
3809         if ((cmd_type == NONE_CONNECTION_TYPE) ||
3810             (cmd == RAMROD_CMD_ID_ETH_FORWARD_SETUP) ||
3811             (cmd == RAMROD_CMD_ID_ETH_CLASSIFICATION_RULES) ||
3812             (cmd == RAMROD_CMD_ID_ETH_FILTER_RULES) ||
3813             (cmd == RAMROD_CMD_ID_ETH_MULTICAST_RULES) ||
3814             (cmd == RAMROD_CMD_ID_ETH_SET_MAC) ||
3815             (cmd == RAMROD_CMD_ID_ETH_RSS_UPDATE))
3816                 return true;
3817         else
3818                 return false;
3819 }
3820
3821 /**
3822  * bnx2x_sp_post - place a single command on an SP ring
3823  *
3824  * @bp:         driver handle
3825  * @command:    command to place (e.g. SETUP, FILTER_RULES, etc.)
3826  * @cid:        SW CID the command is related to
3827  * @data_hi:    command private data address (high 32 bits)
3828  * @data_lo:    command private data address (low 32 bits)
3829  * @cmd_type:   command type (e.g. NONE, ETH)
3830  *
3831  * SP data is handled as if it's always an address pair, thus data fields are
3832  * not swapped to little endian in upper functions. Instead this function swaps
3833  * data as if it's two u32 fields.
3834  */
3835 int bnx2x_sp_post(struct bnx2x *bp, int command, int cid,
3836                   u32 data_hi, u32 data_lo, int cmd_type)
3837 {
3838         struct eth_spe *spe;
3839         u16 type;
3840         bool common = bnx2x_is_contextless_ramrod(command, cmd_type);
3841
3842 #ifdef BNX2X_STOP_ON_ERROR
3843         if (unlikely(bp->panic)) {
3844                 BNX2X_ERR("Can't post SP when there is panic\n");
3845                 return -EIO;
3846         }
3847 #endif
3848
3849         spin_lock_bh(&bp->spq_lock);
3850
3851         if (common) {
3852                 if (!atomic_read(&bp->eq_spq_left)) {
3853                         BNX2X_ERR("BUG! EQ ring full!\n");
3854                         spin_unlock_bh(&bp->spq_lock);
3855                         bnx2x_panic();
3856                         return -EBUSY;
3857                 }
3858         } else if (!atomic_read(&bp->cq_spq_left)) {
3859                         BNX2X_ERR("BUG! SPQ ring full!\n");
3860                         spin_unlock_bh(&bp->spq_lock);
3861                         bnx2x_panic();
3862                         return -EBUSY;
3863         }
3864
3865         spe = bnx2x_sp_get_next(bp);
3866
3867         /* CID needs port number to be encoded int it */
3868         spe->hdr.conn_and_cmd_data =
3869                         cpu_to_le32((command << SPE_HDR_CMD_ID_SHIFT) |
3870                                     HW_CID(bp, cid));
3871
3872         /* In some cases, type may already contain the func-id
3873          * mainly in SRIOV related use cases, so we add it here only
3874          * if it's not already set.
3875          */
3876         if (!(cmd_type & SPE_HDR_FUNCTION_ID)) {
3877                 type = (cmd_type << SPE_HDR_CONN_TYPE_SHIFT) &
3878                         SPE_HDR_CONN_TYPE;
3879                 type |= ((BP_FUNC(bp) << SPE_HDR_FUNCTION_ID_SHIFT) &
3880                          SPE_HDR_FUNCTION_ID);
3881         } else {
3882                 type = cmd_type;
3883         }
3884
3885         spe->hdr.type = cpu_to_le16(type);
3886
3887         spe->data.update_data_addr.hi = cpu_to_le32(data_hi);
3888         spe->data.update_data_addr.lo = cpu_to_le32(data_lo);
3889
3890         /*
3891          * It's ok if the actual decrement is issued towards the memory
3892          * somewhere between the spin_lock and spin_unlock. Thus no
3893          * more explicit memory barrier is needed.
3894          */
3895         if (common)
3896                 atomic_dec(&bp->eq_spq_left);
3897         else
3898                 atomic_dec(&bp->cq_spq_left);
3899
3900         DP(BNX2X_MSG_SP,
3901            "SPQE[%x] (%x:%x)  (cmd, common?) (%d,%d)  hw_cid %x  data (%x:%x) type(0x%x) left (CQ, EQ) (%x,%x)\n",
3902            bp->spq_prod_idx, (u32)U64_HI(bp->spq_mapping),
3903            (u32)(U64_LO(bp->spq_mapping) +
3904            (void *)bp->spq_prod_bd - (void *)bp->spq), command, common,
3905            HW_CID(bp, cid), data_hi, data_lo, type,
3906            atomic_read(&bp->cq_spq_left), atomic_read(&bp->eq_spq_left));
3907
3908         bnx2x_sp_prod_update(bp);
3909         spin_unlock_bh(&bp->spq_lock);
3910         return 0;
3911 }
3912
3913 /* acquire split MCP access lock register */
3914 static int bnx2x_acquire_alr(struct bnx2x *bp)
3915 {
3916         u32 j, val;
3917         int rc = 0;
3918
3919         might_sleep();
3920         for (j = 0; j < 1000; j++) {
3921                 REG_WR(bp, MCP_REG_MCPR_ACCESS_LOCK, MCPR_ACCESS_LOCK_LOCK);
3922                 val = REG_RD(bp, MCP_REG_MCPR_ACCESS_LOCK);
3923                 if (val & MCPR_ACCESS_LOCK_LOCK)
3924                         break;
3925
3926                 usleep_range(5000, 10000);
3927         }
3928         if (!(val & MCPR_ACCESS_LOCK_LOCK)) {
3929                 BNX2X_ERR("Cannot acquire MCP access lock register\n");
3930                 rc = -EBUSY;
3931         }
3932
3933         return rc;
3934 }
3935
3936 /* release split MCP access lock register */
3937 static void bnx2x_release_alr(struct bnx2x *bp)
3938 {
3939         REG_WR(bp, MCP_REG_MCPR_ACCESS_LOCK, 0);
3940 }
3941
3942 #define BNX2X_DEF_SB_ATT_IDX    0x0001
3943 #define BNX2X_DEF_SB_IDX        0x0002
3944
3945 static u16 bnx2x_update_dsb_idx(struct bnx2x *bp)
3946 {
3947         struct host_sp_status_block *def_sb = bp->def_status_blk;
3948         u16 rc = 0;
3949
3950         barrier(); /* status block is written to by the chip */
3951         if (bp->def_att_idx != def_sb->atten_status_block.attn_bits_index) {
3952                 bp->def_att_idx = def_sb->atten_status_block.attn_bits_index;
3953                 rc |= BNX2X_DEF_SB_ATT_IDX;
3954         }
3955
3956         if (bp->def_idx != def_sb->sp_sb.running_index) {
3957                 bp->def_idx = def_sb->sp_sb.running_index;
3958                 rc |= BNX2X_DEF_SB_IDX;
3959         }
3960
3961         /* Do not reorder: indices reading should complete before handling */
3962         barrier();
3963         return rc;
3964 }
3965
3966 /*
3967  * slow path service functions
3968  */
3969
3970 static void bnx2x_attn_int_asserted(struct bnx2x *bp, u32 asserted)
3971 {
3972         int port = BP_PORT(bp);
3973         u32 aeu_addr = port ? MISC_REG_AEU_MASK_ATTN_FUNC_1 :
3974                               MISC_REG_AEU_MASK_ATTN_FUNC_0;
3975         u32 nig_int_mask_addr = port ? NIG_REG_MASK_INTERRUPT_PORT1 :
3976                                        NIG_REG_MASK_INTERRUPT_PORT0;
3977         u32 aeu_mask;
3978         u32 nig_mask = 0;
3979         u32 reg_addr;
3980
3981         if (bp->attn_state & asserted)
3982                 BNX2X_ERR("IGU ERROR\n");
3983
3984         bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_PORT0_ATT_MASK + port);
3985         aeu_mask = REG_RD(bp, aeu_addr);
3986
3987         DP(NETIF_MSG_HW, "aeu_mask %x  newly asserted %x\n",
3988            aeu_mask, asserted);
3989         aeu_mask &= ~(asserted & 0x3ff);
3990         DP(NETIF_MSG_HW, "new mask %x\n", aeu_mask);
3991
3992         REG_WR(bp, aeu_addr, aeu_mask);
3993         bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_PORT0_ATT_MASK + port);
3994
3995         DP(NETIF_MSG_HW, "attn_state %x\n", bp->attn_state);
3996         bp->attn_state |= asserted;
3997         DP(NETIF_MSG_HW, "new state %x\n", bp->attn_state);
3998
3999         if (asserted & ATTN_HARD_WIRED_MASK) {
4000                 if (asserted & ATTN_NIG_FOR_FUNC) {
4001
4002                         bnx2x_acquire_phy_lock(bp);
4003
4004                         /* save nig interrupt mask */
4005                         nig_mask = REG_RD(bp, nig_int_mask_addr);
4006
4007                         /* If nig_mask is not set, no need to call the update
4008                          * function.
4009                          */
4010                         if (nig_mask) {
4011                                 REG_WR(bp, nig_int_mask_addr, 0);
4012
4013                                 bnx2x_link_attn(bp);
4014                         }
4015
4016                         /* handle unicore attn? */
4017                 }
4018                 if (asserted & ATTN_SW_TIMER_4_FUNC)
4019                         DP(NETIF_MSG_HW, "ATTN_SW_TIMER_4_FUNC!\n");
4020
4021                 if (asserted & GPIO_2_FUNC)
4022                         DP(NETIF_MSG_HW, "GPIO_2_FUNC!\n");
4023
4024                 if (asserted & GPIO_3_FUNC)
4025                         DP(NETIF_MSG_HW, "GPIO_3_FUNC!\n");
4026
4027                 if (asserted & GPIO_4_FUNC)
4028                         DP(NETIF_MSG_HW, "GPIO_4_FUNC!\n");
4029
4030                 if (port == 0) {
4031                         if (asserted & ATTN_GENERAL_ATTN_1) {
4032                                 DP(NETIF_MSG_HW, "ATTN_GENERAL_ATTN_1!\n");
4033                                 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_1, 0x0);
4034                         }
4035                         if (asserted & ATTN_GENERAL_ATTN_2) {
4036                                 DP(NETIF_MSG_HW, "ATTN_GENERAL_ATTN_2!\n");
4037                                 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_2, 0x0);
4038                         }
4039                         if (asserted & ATTN_GENERAL_ATTN_3) {
4040                                 DP(NETIF_MSG_HW, "ATTN_GENERAL_ATTN_3!\n");
4041                                 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_3, 0x0);
4042                         }
4043                 } else {
4044                         if (asserted & ATTN_GENERAL_ATTN_4) {
4045                                 DP(NETIF_MSG_HW, "ATTN_GENERAL_ATTN_4!\n");
4046                                 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_4, 0x0);
4047                         }
4048                         if (asserted & ATTN_GENERAL_ATTN_5) {
4049                                 DP(NETIF_MSG_HW, "ATTN_GENERAL_ATTN_5!\n");
4050                                 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_5, 0x0);
4051                         }
4052                         if (asserted & ATTN_GENERAL_ATTN_6) {
4053                                 DP(NETIF_MSG_HW, "ATTN_GENERAL_ATTN_6!\n");
4054                                 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_6, 0x0);
4055                         }
4056                 }
4057
4058         } /* if hardwired */
4059
4060         if (bp->common.int_block == INT_BLOCK_HC)
4061                 reg_addr = (HC_REG_COMMAND_REG + port*32 +
4062                             COMMAND_REG_ATTN_BITS_SET);
4063         else
4064                 reg_addr = (BAR_IGU_INTMEM + IGU_CMD_ATTN_BIT_SET_UPPER*8);
4065
4066         DP(NETIF_MSG_HW, "about to mask 0x%08x at %s addr 0x%x\n", asserted,
4067            (bp->common.int_block == INT_BLOCK_HC) ? "HC" : "IGU", reg_addr);
4068         REG_WR(bp, reg_addr, asserted);
4069
4070         /* now set back the mask */
4071         if (asserted & ATTN_NIG_FOR_FUNC) {
4072                 /* Verify that IGU ack through BAR was written before restoring
4073                  * NIG mask. This loop should exit after 2-3 iterations max.
4074                  */
4075                 if (bp->common.int_block != INT_BLOCK_HC) {
4076                         u32 cnt = 0, igu_acked;
4077                         do {
4078                                 igu_acked = REG_RD(bp,
4079                                                    IGU_REG_ATTENTION_ACK_BITS);
4080                         } while (((igu_acked & ATTN_NIG_FOR_FUNC) == 0) &&
4081                                  (++cnt < MAX_IGU_ATTN_ACK_TO));
4082                         if (!igu_acked)
4083                                 DP(NETIF_MSG_HW,
4084                                    "Failed to verify IGU ack on time\n");
4085                         barrier();
4086                 }
4087                 REG_WR(bp, nig_int_mask_addr, nig_mask);
4088                 bnx2x_release_phy_lock(bp);
4089         }
4090 }
4091
4092 static void bnx2x_fan_failure(struct bnx2x *bp)
4093 {
4094         int port = BP_PORT(bp);
4095         u32 ext_phy_config;
4096         /* mark the failure */
4097         ext_phy_config =
4098                 SHMEM_RD(bp,
4099                          dev_info.port_hw_config[port].external_phy_config);
4100
4101         ext_phy_config &= ~PORT_HW_CFG_XGXS_EXT_PHY_TYPE_MASK;
4102         ext_phy_config |= PORT_HW_CFG_XGXS_EXT_PHY_TYPE_FAILURE;
4103         SHMEM_WR(bp, dev_info.port_hw_config[port].external_phy_config,
4104                  ext_phy_config);
4105
4106         /* log the failure */
4107         netdev_err(bp->dev, "Fan Failure on Network Controller has caused the driver to shutdown the card to prevent permanent damage.\n"
4108                             "Please contact OEM Support for assistance\n");
4109
4110         /* Schedule device reset (unload)
4111          * This is due to some boards consuming sufficient power when driver is
4112          * up to overheat if fan fails.
4113          */
4114         bnx2x_schedule_sp_rtnl(bp, BNX2X_SP_RTNL_FAN_FAILURE, 0);
4115 }
4116
4117 static void bnx2x_attn_int_deasserted0(struct bnx2x *bp, u32 attn)
4118 {
4119         int port = BP_PORT(bp);
4120         int reg_offset;
4121         u32 val;
4122
4123         reg_offset = (port ? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_0 :
4124                              MISC_REG_AEU_ENABLE1_FUNC_0_OUT_0);
4125
4126         if (attn & AEU_INPUTS_ATTN_BITS_SPIO5) {
4127
4128                 val = REG_RD(bp, reg_offset);
4129                 val &= ~AEU_INPUTS_ATTN_BITS_SPIO5;
4130                 REG_WR(bp, reg_offset, val);
4131
4132                 BNX2X_ERR("SPIO5 hw attention\n");
4133
4134                 /* Fan failure attention */
4135                 bnx2x_hw_reset_phy(&bp->link_params);
4136                 bnx2x_fan_failure(bp);
4137         }
4138
4139         if ((attn & bp->link_vars.aeu_int_mask) && bp->port.pmf) {
4140                 bnx2x_acquire_phy_lock(bp);
4141                 bnx2x_handle_module_detect_int(&bp->link_params);
4142                 bnx2x_release_phy_lock(bp);
4143         }
4144
4145         if (attn & HW_INTERRUT_ASSERT_SET_0) {
4146
4147                 val = REG_RD(bp, reg_offset);
4148                 val &= ~(attn & HW_INTERRUT_ASSERT_SET_0);
4149                 REG_WR(bp, reg_offset, val);
4150
4151                 BNX2X_ERR("FATAL HW block attention set0 0x%x\n",
4152                           (u32)(attn & HW_INTERRUT_ASSERT_SET_0));
4153                 bnx2x_panic();
4154         }
4155 }
4156
4157 static void bnx2x_attn_int_deasserted1(struct bnx2x *bp, u32 attn)
4158 {
4159         u32 val;
4160
4161         if (attn & AEU_INPUTS_ATTN_BITS_DOORBELLQ_HW_INTERRUPT) {
4162
4163                 val = REG_RD(bp, DORQ_REG_DORQ_INT_STS_CLR);
4164                 BNX2X_ERR("DB hw attention 0x%x\n", val);
4165                 /* DORQ discard attention */
4166                 if (val & 0x2)
4167                         BNX2X_ERR("FATAL error from DORQ\n");
4168         }
4169
4170         if (attn & HW_INTERRUT_ASSERT_SET_1) {
4171
4172                 int port = BP_PORT(bp);
4173                 int reg_offset;
4174
4175                 reg_offset = (port ? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_1 :
4176                                      MISC_REG_AEU_ENABLE1_FUNC_0_OUT_1);
4177
4178                 val = REG_RD(bp, reg_offset);
4179                 val &= ~(attn & HW_INTERRUT_ASSERT_SET_1);
4180                 REG_WR(bp, reg_offset, val);
4181
4182                 BNX2X_ERR("FATAL HW block attention set1 0x%x\n",
4183                           (u32)(attn & HW_INTERRUT_ASSERT_SET_1));
4184                 bnx2x_panic();
4185         }
4186 }
4187
4188 static void bnx2x_attn_int_deasserted2(struct bnx2x *bp, u32 attn)
4189 {
4190         u32 val;
4191
4192         if (attn & AEU_INPUTS_ATTN_BITS_CFC_HW_INTERRUPT) {
4193
4194                 val = REG_RD(bp, CFC_REG_CFC_INT_STS_CLR);
4195                 BNX2X_ERR("CFC hw attention 0x%x\n", val);
4196                 /* CFC error attention */
4197                 if (val & 0x2)
4198                         BNX2X_ERR("FATAL error from CFC\n");
4199         }
4200
4201         if (attn & AEU_INPUTS_ATTN_BITS_PXP_HW_INTERRUPT) {
4202                 val = REG_RD(bp, PXP_REG_PXP_INT_STS_CLR_0);
4203                 BNX2X_ERR("PXP hw attention-0 0x%x\n", val);
4204                 /* RQ_USDMDP_FIFO_OVERFLOW */
4205                 if (val & 0x18000)
4206                         BNX2X_ERR("FATAL error from PXP\n");
4207
4208                 if (!CHIP_IS_E1x(bp)) {
4209                         val = REG_RD(bp, PXP_REG_PXP_INT_STS_CLR_1);
4210                         BNX2X_ERR("PXP hw attention-1 0x%x\n", val);
4211                 }
4212         }
4213
4214         if (attn & HW_INTERRUT_ASSERT_SET_2) {
4215
4216                 int port = BP_PORT(bp);
4217                 int reg_offset;
4218
4219                 reg_offset = (port ? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_2 :
4220                                      MISC_REG_AEU_ENABLE1_FUNC_0_OUT_2);
4221
4222                 val = REG_RD(bp, reg_offset);
4223                 val &= ~(attn & HW_INTERRUT_ASSERT_SET_2);
4224                 REG_WR(bp, reg_offset, val);
4225
4226                 BNX2X_ERR("FATAL HW block attention set2 0x%x\n",
4227                           (u32)(attn & HW_INTERRUT_ASSERT_SET_2));
4228                 bnx2x_panic();
4229         }
4230 }
4231
4232 static void bnx2x_attn_int_deasserted3(struct bnx2x *bp, u32 attn)
4233 {
4234         u32 val;
4235
4236         if (attn & EVEREST_GEN_ATTN_IN_USE_MASK) {
4237
4238                 if (attn & BNX2X_PMF_LINK_ASSERT) {
4239                         int func = BP_FUNC(bp);
4240
4241                         REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_12 + func*4, 0);
4242                         bnx2x_read_mf_cfg(bp);
4243                         bp->mf_config[BP_VN(bp)] = MF_CFG_RD(bp,
4244                                         func_mf_config[BP_ABS_FUNC(bp)].config);
4245                         val = SHMEM_RD(bp,
4246                                        func_mb[BP_FW_MB_IDX(bp)].drv_status);
4247
4248                         if (val & (DRV_STATUS_DCC_EVENT_MASK |
4249                                    DRV_STATUS_OEM_EVENT_MASK))
4250                                 bnx2x_oem_event(bp,
4251                                         (val & (DRV_STATUS_DCC_EVENT_MASK |
4252                                                 DRV_STATUS_OEM_EVENT_MASK)));
4253
4254                         if (val & DRV_STATUS_SET_MF_BW)
4255                                 bnx2x_set_mf_bw(bp);
4256
4257                         if (val & DRV_STATUS_DRV_INFO_REQ)
4258                                 bnx2x_handle_drv_info_req(bp);
4259
4260                         if (val & DRV_STATUS_VF_DISABLED)
4261                                 bnx2x_schedule_iov_task(bp,
4262                                                         BNX2X_IOV_HANDLE_FLR);
4263
4264                         if ((bp->port.pmf == 0) && (val & DRV_STATUS_PMF))
4265                                 bnx2x_pmf_update(bp);
4266
4267                         if (bp->port.pmf &&
4268                             (val & DRV_STATUS_DCBX_NEGOTIATION_RESULTS) &&
4269                                 bp->dcbx_enabled > 0)
4270                                 /* start dcbx state machine */
4271                                 bnx2x_dcbx_set_params(bp,
4272                                         BNX2X_DCBX_STATE_NEG_RECEIVED);
4273                         if (val & DRV_STATUS_AFEX_EVENT_MASK)
4274                                 bnx2x_handle_afex_cmd(bp,
4275                                         val & DRV_STATUS_AFEX_EVENT_MASK);
4276                         if (val & DRV_STATUS_EEE_NEGOTIATION_RESULTS)
4277                                 bnx2x_handle_eee_event(bp);
4278
4279                         if (val & DRV_STATUS_OEM_UPDATE_SVID)
4280                                 bnx2x_handle_update_svid_cmd(bp);
4281
4282                         if (bp->link_vars.periodic_flags &
4283                             PERIODIC_FLAGS_LINK_EVENT) {
4284                                 /*  sync with link */
4285                                 bnx2x_acquire_phy_lock(bp);
4286                                 bp->link_vars.periodic_flags &=
4287                                         ~PERIODIC_FLAGS_LINK_EVENT;
4288                                 bnx2x_release_phy_lock(bp);
4289                                 if (IS_MF(bp))
4290                                         bnx2x_link_sync_notify(bp);
4291                                 bnx2x_link_report(bp);
4292                         }
4293                         /* Always call it here: bnx2x_link_report() will
4294                          * prevent the link indication duplication.
4295                          */
4296                         bnx2x__link_status_update(bp);
4297                 } else if (attn & BNX2X_MC_ASSERT_BITS) {
4298
4299                         BNX2X_ERR("MC assert!\n");
4300                         bnx2x_mc_assert(bp);
4301                         REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_10, 0);
4302                         REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_9, 0);
4303                         REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_8, 0);
4304                         REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_7, 0);
4305                         bnx2x_panic();
4306
4307                 } else if (attn & BNX2X_MCP_ASSERT) {
4308
4309                         BNX2X_ERR("MCP assert!\n");
4310                         REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_11, 0);
4311                         bnx2x_fw_dump(bp);
4312
4313                 } else
4314                         BNX2X_ERR("Unknown HW assert! (attn 0x%x)\n", attn);
4315         }
4316
4317         if (attn & EVEREST_LATCHED_ATTN_IN_USE_MASK) {
4318                 BNX2X_ERR("LATCHED attention 0x%08x (masked)\n", attn);
4319                 if (attn & BNX2X_GRC_TIMEOUT) {
4320                         val = CHIP_IS_E1(bp) ? 0 :
4321                                         REG_RD(bp, MISC_REG_GRC_TIMEOUT_ATTN);
4322                         BNX2X_ERR("GRC time-out 0x%08x\n", val);
4323                 }
4324                 if (attn & BNX2X_GRC_RSV) {
4325                         val = CHIP_IS_E1(bp) ? 0 :
4326                                         REG_RD(bp, MISC_REG_GRC_RSV_ATTN);
4327                         BNX2X_ERR("GRC reserved 0x%08x\n", val);
4328                 }
4329                 REG_WR(bp, MISC_REG_AEU_CLR_LATCH_SIGNAL, 0x7ff);
4330         }
4331 }
4332
4333 /*
4334  * Bits map:
4335  * 0-7   - Engine0 load counter.
4336  * 8-15  - Engine1 load counter.
4337  * 16    - Engine0 RESET_IN_PROGRESS bit.
4338  * 17    - Engine1 RESET_IN_PROGRESS bit.
4339  * 18    - Engine0 ONE_IS_LOADED. Set when there is at least one active function
4340  *         on the engine
4341  * 19    - Engine1 ONE_IS_LOADED.
4342  * 20    - Chip reset flow bit. When set none-leader must wait for both engines
4343  *         leader to complete (check for both RESET_IN_PROGRESS bits and not for
4344  *         just the one belonging to its engine).
4345  *
4346  */
4347 #define BNX2X_RECOVERY_GLOB_REG         MISC_REG_GENERIC_POR_1
4348
4349 #define BNX2X_PATH0_LOAD_CNT_MASK       0x000000ff
4350 #define BNX2X_PATH0_LOAD_CNT_SHIFT      0
4351 #define BNX2X_PATH1_LOAD_CNT_MASK       0x0000ff00
4352 #define BNX2X_PATH1_LOAD_CNT_SHIFT      8
4353 #define BNX2X_PATH0_RST_IN_PROG_BIT     0x00010000
4354 #define BNX2X_PATH1_RST_IN_PROG_BIT     0x00020000
4355 #define BNX2X_GLOBAL_RESET_BIT          0x00040000
4356
4357 /*
4358  * Set the GLOBAL_RESET bit.
4359  *
4360  * Should be run under rtnl lock
4361  */
4362 void bnx2x_set_reset_global(struct bnx2x *bp)
4363 {
4364         u32 val;
4365         bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG);
4366         val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG);
4367         REG_WR(bp, BNX2X_RECOVERY_GLOB_REG, val | BNX2X_GLOBAL_RESET_BIT);
4368         bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG);
4369 }
4370
4371 /*
4372  * Clear the GLOBAL_RESET bit.
4373  *
4374  * Should be run under rtnl lock
4375  */
4376 static void bnx2x_clear_reset_global(struct bnx2x *bp)
4377 {
4378         u32 val;
4379         bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG);
4380         val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG);
4381         REG_WR(bp, BNX2X_RECOVERY_GLOB_REG, val & (~BNX2X_GLOBAL_RESET_BIT));
4382         bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG);
4383 }
4384
4385 /*
4386  * Checks the GLOBAL_RESET bit.
4387  *
4388  * should be run under rtnl lock
4389  */
4390 static bool bnx2x_reset_is_global(struct bnx2x *bp)
4391 {
4392         u32 val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG);
4393
4394         DP(NETIF_MSG_HW, "GEN_REG_VAL=0x%08x\n", val);
4395         return (val & BNX2X_GLOBAL_RESET_BIT) ? true : false;
4396 }
4397
4398 /*
4399  * Clear RESET_IN_PROGRESS bit for the current engine.
4400  *
4401  * Should be run under rtnl lock
4402  */
4403 static void bnx2x_set_reset_done(struct bnx2x *bp)
4404 {
4405         u32 val;
4406         u32 bit = BP_PATH(bp) ?
4407                 BNX2X_PATH1_RST_IN_PROG_BIT : BNX2X_PATH0_RST_IN_PROG_BIT;
4408         bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG);
4409         val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG);
4410
4411         /* Clear the bit */
4412         val &= ~bit;
4413         REG_WR(bp, BNX2X_RECOVERY_GLOB_REG, val);
4414
4415         bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG);
4416 }
4417
4418 /*
4419  * Set RESET_IN_PROGRESS for the current engine.
4420  *
4421  * should be run under rtnl lock
4422  */
4423 void bnx2x_set_reset_in_progress(struct bnx2x *bp)
4424 {
4425         u32 val;
4426         u32 bit = BP_PATH(bp) ?
4427                 BNX2X_PATH1_RST_IN_PROG_BIT : BNX2X_PATH0_RST_IN_PROG_BIT;
4428         bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG);
4429         val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG);
4430
4431         /* Set the bit */
4432         val |= bit;
4433         REG_WR(bp, BNX2X_RECOVERY_GLOB_REG, val);
4434         bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG);
4435 }
4436
4437 /*
4438  * Checks the RESET_IN_PROGRESS bit for the given engine.
4439  * should be run under rtnl lock
4440  */
4441 bool bnx2x_reset_is_done(struct bnx2x *bp, int engine)
4442 {
4443         u32 val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG);
4444         u32 bit = engine ?
4445                 BNX2X_PATH1_RST_IN_PROG_BIT : BNX2X_PATH0_RST_IN_PROG_BIT;
4446
4447         /* return false if bit is set */
4448         return (val & bit) ? false : true;
4449 }
4450
4451 /*
4452  * set pf load for the current pf.
4453  *
4454  * should be run under rtnl lock
4455  */
4456 void bnx2x_set_pf_load(struct bnx2x *bp)
4457 {
4458         u32 val1, val;
4459         u32 mask = BP_PATH(bp) ? BNX2X_PATH1_LOAD_CNT_MASK :
4460                              BNX2X_PATH0_LOAD_CNT_MASK;
4461         u32 shift = BP_PATH(bp) ? BNX2X_PATH1_LOAD_CNT_SHIFT :
4462                              BNX2X_PATH0_LOAD_CNT_SHIFT;
4463
4464         bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG);
4465         val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG);
4466
4467         DP(NETIF_MSG_IFUP, "Old GEN_REG_VAL=0x%08x\n", val);
4468
4469         /* get the current counter value */
4470         val1 = (val & mask) >> shift;
4471
4472         /* set bit of that PF */
4473         val1 |= (1 << bp->pf_num);
4474
4475         /* clear the old value */
4476         val &= ~mask;
4477
4478         /* set the new one */
4479         val |= ((val1 << shift) & mask);
4480
4481         REG_WR(bp, BNX2X_RECOVERY_GLOB_REG, val);
4482         bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG);
4483 }
4484
4485 /**
4486  * bnx2x_clear_pf_load - clear pf load mark
4487  *
4488  * @bp:         driver handle
4489  *
4490  * Should be run under rtnl lock.
4491  * Decrements the load counter for the current engine. Returns
4492  * whether other functions are still loaded
4493  */
4494 bool bnx2x_clear_pf_load(struct bnx2x *bp)
4495 {
4496         u32 val1, val;
4497         u32 mask = BP_PATH(bp) ? BNX2X_PATH1_LOAD_CNT_MASK :
4498                              BNX2X_PATH0_LOAD_CNT_MASK;
4499         u32 shift = BP_PATH(bp) ? BNX2X_PATH1_LOAD_CNT_SHIFT :
4500                              BNX2X_PATH0_LOAD_CNT_SHIFT;
4501
4502         bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG);
4503         val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG);
4504         DP(NETIF_MSG_IFDOWN, "Old GEN_REG_VAL=0x%08x\n", val);
4505
4506         /* get the current counter value */
4507         val1 = (val & mask) >> shift;
4508
4509         /* clear bit of that PF */
4510         val1 &= ~(1 << bp->pf_num);
4511
4512         /* clear the old value */
4513         val &= ~mask;
4514
4515         /* set the new one */
4516         val |= ((val1 << shift) & mask);
4517
4518         REG_WR(bp, BNX2X_RECOVERY_GLOB_REG, val);
4519         bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG);
4520         return val1 != 0;
4521 }
4522
4523 /*
4524  * Read the load status for the current engine.
4525  *
4526  * should be run under rtnl lock
4527  */
4528 static bool bnx2x_get_load_status(struct bnx2x *bp, int engine)
4529 {
4530         u32 mask = (engine ? BNX2X_PATH1_LOAD_CNT_MASK :
4531                              BNX2X_PATH0_LOAD_CNT_MASK);
4532         u32 shift = (engine ? BNX2X_PATH1_LOAD_CNT_SHIFT :
4533                              BNX2X_PATH0_LOAD_CNT_SHIFT);
4534         u32 val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG);
4535
4536         DP(NETIF_MSG_HW | NETIF_MSG_IFUP, "GLOB_REG=0x%08x\n", val);
4537
4538         val = (val & mask) >> shift;
4539
4540         DP(NETIF_MSG_HW | NETIF_MSG_IFUP, "load mask for engine %d = 0x%x\n",
4541            engine, val);
4542
4543         return val != 0;
4544 }
4545
4546 static void _print_parity(struct bnx2x *bp, u32 reg)
4547 {
4548         pr_cont(" [0x%08x] ", REG_RD(bp, reg));
4549 }
4550
4551 static void _print_next_block(int idx, const char *blk)
4552 {
4553         pr_cont("%s%s", idx ? ", " : "", blk);
4554 }
4555
4556 static bool bnx2x_check_blocks_with_parity0(struct bnx2x *bp, u32 sig,
4557                                             int *par_num, bool print)
4558 {
4559         u32 cur_bit;
4560         bool res;
4561         int i;
4562
4563         res = false;
4564
4565         for (i = 0; sig; i++) {
4566                 cur_bit = (0x1UL << i);
4567                 if (sig & cur_bit) {
4568                         res |= true; /* Each bit is real error! */
4569
4570                         if (print) {
4571                                 switch (cur_bit) {
4572                                 case AEU_INPUTS_ATTN_BITS_BRB_PARITY_ERROR:
4573                                         _print_next_block((*par_num)++, "BRB");
4574                                         _print_parity(bp,
4575                                                       BRB1_REG_BRB1_PRTY_STS);
4576                                         break;
4577                                 case AEU_INPUTS_ATTN_BITS_PARSER_PARITY_ERROR:
4578                                         _print_next_block((*par_num)++,
4579                                                           "PARSER");
4580                                         _print_parity(bp, PRS_REG_PRS_PRTY_STS);
4581                                         break;
4582                                 case AEU_INPUTS_ATTN_BITS_TSDM_PARITY_ERROR:
4583                                         _print_next_block((*par_num)++, "TSDM");
4584                                         _print_parity(bp,
4585                                                       TSDM_REG_TSDM_PRTY_STS);
4586                                         break;
4587                                 case AEU_INPUTS_ATTN_BITS_SEARCHER_PARITY_ERROR:
4588                                         _print_next_block((*par_num)++,
4589                                                           "SEARCHER");
4590                                         _print_parity(bp, SRC_REG_SRC_PRTY_STS);
4591                                         break;
4592                                 case AEU_INPUTS_ATTN_BITS_TCM_PARITY_ERROR:
4593                                         _print_next_block((*par_num)++, "TCM");
4594                                         _print_parity(bp, TCM_REG_TCM_PRTY_STS);
4595                                         break;
4596                                 case AEU_INPUTS_ATTN_BITS_TSEMI_PARITY_ERROR:
4597                                         _print_next_block((*par_num)++,
4598                                                           "TSEMI");
4599                                         _print_parity(bp,
4600                                                       TSEM_REG_TSEM_PRTY_STS_0);
4601                                         _print_parity(bp,
4602                                                       TSEM_REG_TSEM_PRTY_STS_1);
4603                                         break;
4604                                 case AEU_INPUTS_ATTN_BITS_PBCLIENT_PARITY_ERROR:
4605                                         _print_next_block((*par_num)++, "XPB");
4606                                         _print_parity(bp, GRCBASE_XPB +
4607                                                           PB_REG_PB_PRTY_STS);
4608                                         break;
4609                                 }
4610                         }
4611
4612                         /* Clear the bit */
4613                         sig &= ~cur_bit;
4614                 }
4615         }
4616
4617         return res;
4618 }
4619
4620 static bool bnx2x_check_blocks_with_parity1(struct bnx2x *bp, u32 sig,
4621                                             int *par_num, bool *global,
4622                                             bool print)
4623 {
4624         u32 cur_bit;
4625         bool res;
4626         int i;
4627
4628         res = false;
4629
4630         for (i = 0; sig; i++) {
4631                 cur_bit = (0x1UL << i);
4632                 if (sig & cur_bit) {
4633                         res |= true; /* Each bit is real error! */
4634                         switch (cur_bit) {
4635                         case AEU_INPUTS_ATTN_BITS_PBF_PARITY_ERROR:
4636                                 if (print) {
4637                                         _print_next_block((*par_num)++, "PBF");
4638                                         _print_parity(bp, PBF_REG_PBF_PRTY_STS);
4639                                 }
4640                                 break;
4641                         case AEU_INPUTS_ATTN_BITS_QM_PARITY_ERROR:
4642                                 if (print) {
4643                                         _print_next_block((*par_num)++, "QM");
4644                                         _print_parity(bp, QM_REG_QM_PRTY_STS);
4645                                 }
4646                                 break;
4647                         case AEU_INPUTS_ATTN_BITS_TIMERS_PARITY_ERROR:
4648                                 if (print) {
4649                                         _print_next_block((*par_num)++, "TM");
4650                                         _print_parity(bp, TM_REG_TM_PRTY_STS);
4651                                 }
4652                                 break;
4653                         case AEU_INPUTS_ATTN_BITS_XSDM_PARITY_ERROR:
4654                                 if (print) {
4655                                         _print_next_block((*par_num)++, "XSDM");
4656                                         _print_parity(bp,
4657                                                       XSDM_REG_XSDM_PRTY_STS);
4658                                 }
4659                                 break;
4660                         case AEU_INPUTS_ATTN_BITS_XCM_PARITY_ERROR:
4661                                 if (print) {
4662                                         _print_next_block((*par_num)++, "XCM");
4663                                         _print_parity(bp, XCM_REG_XCM_PRTY_STS);
4664                                 }
4665                                 break;
4666                         case AEU_INPUTS_ATTN_BITS_XSEMI_PARITY_ERROR:
4667                                 if (print) {
4668                                         _print_next_block((*par_num)++,
4669                                                           "XSEMI");
4670                                         _print_parity(bp,
4671                                                       XSEM_REG_XSEM_PRTY_STS_0);
4672                                         _print_parity(bp,
4673                                                       XSEM_REG_XSEM_PRTY_STS_1);
4674                                 }
4675                                 break;
4676                         case AEU_INPUTS_ATTN_BITS_DOORBELLQ_PARITY_ERROR:
4677                                 if (print) {
4678                                         _print_next_block((*par_num)++,
4679                                                           "DOORBELLQ");
4680                                         _print_parity(bp,
4681                                                       DORQ_REG_DORQ_PRTY_STS);
4682                                 }
4683                                 break;
4684                         case AEU_INPUTS_ATTN_BITS_NIG_PARITY_ERROR:
4685                                 if (print) {
4686                                         _print_next_block((*par_num)++, "NIG");
4687                                         if (CHIP_IS_E1x(bp)) {
4688                                                 _print_parity(bp,
4689                                                         NIG_REG_NIG_PRTY_STS);
4690                                         } else {
4691                                                 _print_parity(bp,
4692                                                         NIG_REG_NIG_PRTY_STS_0);
4693                                                 _print_parity(bp,
4694                                                         NIG_REG_NIG_PRTY_STS_1);
4695                                         }
4696                                 }
4697                                 break;
4698                         case AEU_INPUTS_ATTN_BITS_VAUX_PCI_CORE_PARITY_ERROR:
4699                                 if (print)
4700                                         _print_next_block((*par_num)++,
4701                                                           "VAUX PCI CORE");
4702                                 *global = true;
4703                                 break;
4704                         case AEU_INPUTS_ATTN_BITS_DEBUG_PARITY_ERROR:
4705                                 if (print) {
4706                                         _print_next_block((*par_num)++,
4707                                                           "DEBUG");
4708                                         _print_parity(bp, DBG_REG_DBG_PRTY_STS);
4709                                 }
4710                                 break;
4711                         case AEU_INPUTS_ATTN_BITS_USDM_PARITY_ERROR:
4712                                 if (print) {
4713                                         _print_next_block((*par_num)++, "USDM");
4714                                         _print_parity(bp,
4715                                                       USDM_REG_USDM_PRTY_STS);
4716                                 }
4717                                 break;
4718                         case AEU_INPUTS_ATTN_BITS_UCM_PARITY_ERROR:
4719                                 if (print) {
4720                                         _print_next_block((*par_num)++, "UCM");
4721                                         _print_parity(bp, UCM_REG_UCM_PRTY_STS);
4722                                 }
4723                                 break;
4724                         case AEU_INPUTS_ATTN_BITS_USEMI_PARITY_ERROR:
4725                                 if (print) {
4726                                         _print_next_block((*par_num)++,
4727                                                           "USEMI");
4728                                         _print_parity(bp,
4729                                                       USEM_REG_USEM_PRTY_STS_0);
4730                                         _print_parity(bp,
4731                                                       USEM_REG_USEM_PRTY_STS_1);
4732                                 }
4733                                 break;
4734                         case AEU_INPUTS_ATTN_BITS_UPB_PARITY_ERROR:
4735                                 if (print) {
4736                                         _print_next_block((*par_num)++, "UPB");
4737                                         _print_parity(bp, GRCBASE_UPB +
4738                                                           PB_REG_PB_PRTY_STS);
4739                                 }
4740                                 break;
4741                         case AEU_INPUTS_ATTN_BITS_CSDM_PARITY_ERROR:
4742                                 if (print) {
4743                                         _print_next_block((*par_num)++, "CSDM");
4744                                         _print_parity(bp,
4745                                                       CSDM_REG_CSDM_PRTY_STS);
4746                                 }
4747                                 break;
4748                         case AEU_INPUTS_ATTN_BITS_CCM_PARITY_ERROR:
4749                                 if (print) {
4750                                         _print_next_block((*par_num)++, "CCM");
4751                                         _print_parity(bp, CCM_REG_CCM_PRTY_STS);
4752                                 }
4753                                 break;
4754                         }
4755
4756                         /* Clear the bit */
4757                         sig &= ~cur_bit;
4758                 }
4759         }
4760
4761         return res;
4762 }
4763
4764 static bool bnx2x_check_blocks_with_parity2(struct bnx2x *bp, u32 sig,
4765                                             int *par_num, bool print)
4766 {
4767         u32 cur_bit;
4768         bool res;
4769         int i;
4770
4771         res = false;
4772
4773         for (i = 0; sig; i++) {
4774                 cur_bit = (0x1UL << i);
4775                 if (sig & cur_bit) {
4776                         res = true; /* Each bit is real error! */
4777                         if (print) {
4778                                 switch (cur_bit) {
4779                                 case AEU_INPUTS_ATTN_BITS_CSEMI_PARITY_ERROR:
4780                                         _print_next_block((*par_num)++,
4781                                                           "CSEMI");
4782                                         _print_parity(bp,
4783                                                       CSEM_REG_CSEM_PRTY_STS_0);
4784                                         _print_parity(bp,
4785                                                       CSEM_REG_CSEM_PRTY_STS_1);
4786                                         break;
4787                                 case AEU_INPUTS_ATTN_BITS_PXP_PARITY_ERROR:
4788                                         _print_next_block((*par_num)++, "PXP");
4789                                         _print_parity(bp, PXP_REG_PXP_PRTY_STS);
4790                                         _print_parity(bp,
4791                                                       PXP2_REG_PXP2_PRTY_STS_0);
4792                                         _print_parity(bp,
4793                                                       PXP2_REG_PXP2_PRTY_STS_1);
4794                                         break;
4795                                 case AEU_IN_ATTN_BITS_PXPPCICLOCKCLIENT_PARITY_ERROR:
4796                                         _print_next_block((*par_num)++,
4797                                                           "PXPPCICLOCKCLIENT");
4798                                         break;
4799                                 case AEU_INPUTS_ATTN_BITS_CFC_PARITY_ERROR:
4800                                         _print_next_block((*par_num)++, "CFC");
4801                                         _print_parity(bp,
4802                                                       CFC_REG_CFC_PRTY_STS);
4803                                         break;
4804                                 case AEU_INPUTS_ATTN_BITS_CDU_PARITY_ERROR:
4805                                         _print_next_block((*par_num)++, "CDU");
4806                                         _print_parity(bp, CDU_REG_CDU_PRTY_STS);
4807                                         break;
4808                                 case AEU_INPUTS_ATTN_BITS_DMAE_PARITY_ERROR:
4809                                         _print_next_block((*par_num)++, "DMAE");
4810                                         _print_parity(bp,
4811                                                       DMAE_REG_DMAE_PRTY_STS);
4812                                         break;
4813                                 case AEU_INPUTS_ATTN_BITS_IGU_PARITY_ERROR:
4814                                         _print_next_block((*par_num)++, "IGU");
4815                                         if (CHIP_IS_E1x(bp))
4816                                                 _print_parity(bp,
4817                                                         HC_REG_HC_PRTY_STS);
4818                                         else
4819                                                 _print_parity(bp,
4820                                                         IGU_REG_IGU_PRTY_STS);
4821                                         break;
4822                                 case AEU_INPUTS_ATTN_BITS_MISC_PARITY_ERROR:
4823                                         _print_next_block((*par_num)++, "MISC");
4824                                         _print_parity(bp,
4825                                                       MISC_REG_MISC_PRTY_STS);
4826                                         break;
4827                                 }
4828                         }
4829
4830                         /* Clear the bit */
4831                         sig &= ~cur_bit;
4832                 }
4833         }
4834
4835         return res;
4836 }
4837
4838 static bool bnx2x_check_blocks_with_parity3(struct bnx2x *bp, u32 sig,
4839                                             int *par_num, bool *global,
4840                                             bool print)
4841 {
4842         bool res = false;
4843         u32 cur_bit;
4844         int i;
4845
4846         for (i = 0; sig; i++) {
4847                 cur_bit = (0x1UL << i);
4848                 if (sig & cur_bit) {
4849                         switch (cur_bit) {
4850                         case AEU_INPUTS_ATTN_BITS_MCP_LATCHED_ROM_PARITY:
4851                                 if (print)
4852                                         _print_next_block((*par_num)++,
4853                                                           "MCP ROM");
4854                                 *global = true;
4855                                 res = true;
4856                                 break;
4857                         case AEU_INPUTS_ATTN_BITS_MCP_LATCHED_UMP_RX_PARITY:
4858                                 if (print)
4859                                         _print_next_block((*par_num)++,
4860                                                           "MCP UMP RX");
4861                                 *global = true;
4862                                 res = true;
4863                                 break;
4864                         case AEU_INPUTS_ATTN_BITS_MCP_LATCHED_UMP_TX_PARITY:
4865                                 if (print)
4866                                         _print_next_block((*par_num)++,
4867                                                           "MCP UMP TX");
4868                                 *global = true;
4869                                 res = true;
4870                                 break;
4871                         case AEU_INPUTS_ATTN_BITS_MCP_LATCHED_SCPAD_PARITY:
4872                                 (*par_num)++;
4873                                 /* clear latched SCPAD PATIRY from MCP */
4874                                 REG_WR(bp, MISC_REG_AEU_CLR_LATCH_SIGNAL,
4875                                        1UL << 10);
4876                                 break;
4877                         }
4878
4879                         /* Clear the bit */
4880                         sig &= ~cur_bit;
4881                 }
4882         }
4883
4884         return res;
4885 }
4886
4887 static bool bnx2x_check_blocks_with_parity4(struct bnx2x *bp, u32 sig,
4888                                             int *par_num, bool print)
4889 {
4890         u32 cur_bit;
4891         bool res;
4892         int i;
4893
4894         res = false;
4895
4896         for (i = 0; sig; i++) {
4897                 cur_bit = (0x1UL << i);
4898                 if (sig & cur_bit) {
4899                         res = true; /* Each bit is real error! */
4900                         if (print) {
4901                                 switch (cur_bit) {
4902                                 case AEU_INPUTS_ATTN_BITS_PGLUE_PARITY_ERROR:
4903                                         _print_next_block((*par_num)++,
4904                                                           "PGLUE_B");
4905                                         _print_parity(bp,
4906                                                       PGLUE_B_REG_PGLUE_B_PRTY_STS);
4907                                         break;
4908                                 case AEU_INPUTS_ATTN_BITS_ATC_PARITY_ERROR:
4909                                         _print_next_block((*par_num)++, "ATC");
4910                                         _print_parity(bp,
4911                                                       ATC_REG_ATC_PRTY_STS);
4912                                         break;
4913                                 }
4914                         }
4915                         /* Clear the bit */
4916                         sig &= ~cur_bit;
4917                 }
4918         }
4919
4920         return res;
4921 }
4922
4923 static bool bnx2x_parity_attn(struct bnx2x *bp, bool *global, bool print,
4924                               u32 *sig)
4925 {
4926         bool res = false;
4927
4928         if ((sig[0] & HW_PRTY_ASSERT_SET_0) ||
4929             (sig[1] & HW_PRTY_ASSERT_SET_1) ||
4930             (sig[2] & HW_PRTY_ASSERT_SET_2) ||
4931             (sig[3] & HW_PRTY_ASSERT_SET_3) ||
4932             (sig[4] & HW_PRTY_ASSERT_SET_4)) {
4933                 int par_num = 0;
4934
4935                 DP(NETIF_MSG_HW, "Was parity error: HW block parity attention:\n"
4936                                  "[0]:0x%08x [1]:0x%08x [2]:0x%08x [3]:0x%08x [4]:0x%08x\n",
4937                           sig[0] & HW_PRTY_ASSERT_SET_0,
4938                           sig[1] & HW_PRTY_ASSERT_SET_1,
4939                           sig[2] & HW_PRTY_ASSERT_SET_2,
4940                           sig[3] & HW_PRTY_ASSERT_SET_3,
4941                           sig[4] & HW_PRTY_ASSERT_SET_4);
4942                 if (print) {
4943                         if (((sig[0] & HW_PRTY_ASSERT_SET_0) ||
4944                              (sig[1] & HW_PRTY_ASSERT_SET_1) ||
4945                              (sig[2] & HW_PRTY_ASSERT_SET_2) ||
4946                              (sig[4] & HW_PRTY_ASSERT_SET_4)) ||
4947                              (sig[3] & HW_PRTY_ASSERT_SET_3_WITHOUT_SCPAD)) {
4948                                 netdev_err(bp->dev,
4949                                            "Parity errors detected in blocks: ");
4950                         } else {
4951                                 print = false;
4952                         }
4953                 }
4954                 res |= bnx2x_check_blocks_with_parity0(bp,
4955                         sig[0] & HW_PRTY_ASSERT_SET_0, &par_num, print);
4956                 res |= bnx2x_check_blocks_with_parity1(bp,
4957                         sig[1] & HW_PRTY_ASSERT_SET_1, &par_num, global, print);
4958                 res |= bnx2x_check_blocks_with_parity2(bp,
4959                         sig[2] & HW_PRTY_ASSERT_SET_2, &par_num, print);
4960                 res |= bnx2x_check_blocks_with_parity3(bp,
4961                         sig[3] & HW_PRTY_ASSERT_SET_3, &par_num, global, print);
4962                 res |= bnx2x_check_blocks_with_parity4(bp,
4963                         sig[4] & HW_PRTY_ASSERT_SET_4, &par_num, print);
4964
4965                 if (print)
4966                         pr_cont("\n");
4967         }
4968
4969         return res;
4970 }
4971
4972 /**
4973  * bnx2x_chk_parity_attn - checks for parity attentions.
4974  *
4975  * @bp:         driver handle
4976  * @global:     true if there was a global attention
4977  * @print:      show parity attention in syslog
4978  */
4979 bool bnx2x_chk_parity_attn(struct bnx2x *bp, bool *global, bool print)
4980 {
4981         struct attn_route attn = { {0} };
4982         int port = BP_PORT(bp);
4983
4984         attn.sig[0] = REG_RD(bp,
4985                 MISC_REG_AEU_AFTER_INVERT_1_FUNC_0 +
4986                              port*4);
4987         attn.sig[1] = REG_RD(bp,
4988                 MISC_REG_AEU_AFTER_INVERT_2_FUNC_0 +
4989                              port*4);
4990         attn.sig[2] = REG_RD(bp,
4991                 MISC_REG_AEU_AFTER_INVERT_3_FUNC_0 +
4992                              port*4);
4993         attn.sig[3] = REG_RD(bp,
4994                 MISC_REG_AEU_AFTER_INVERT_4_FUNC_0 +
4995                              port*4);
4996         /* Since MCP attentions can't be disabled inside the block, we need to
4997          * read AEU registers to see whether they're currently disabled
4998          */
4999         attn.sig[3] &= ((REG_RD(bp,
5000                                 !port ? MISC_REG_AEU_ENABLE4_FUNC_0_OUT_0
5001                                       : MISC_REG_AEU_ENABLE4_FUNC_1_OUT_0) &
5002                          MISC_AEU_ENABLE_MCP_PRTY_BITS) |
5003                         ~MISC_AEU_ENABLE_MCP_PRTY_BITS);
5004
5005         if (!CHIP_IS_E1x(bp))
5006                 attn.sig[4] = REG_RD(bp,
5007                         MISC_REG_AEU_AFTER_INVERT_5_FUNC_0 +
5008                                      port*4);
5009
5010         return bnx2x_parity_attn(bp, global, print, attn.sig);
5011 }
5012
5013 static void bnx2x_attn_int_deasserted4(struct bnx2x *bp, u32 attn)
5014 {
5015         u32 val;
5016         if (attn & AEU_INPUTS_ATTN_BITS_PGLUE_HW_INTERRUPT) {
5017
5018                 val = REG_RD(bp, PGLUE_B_REG_PGLUE_B_INT_STS_CLR);
5019                 BNX2X_ERR("PGLUE hw attention 0x%x\n", val);
5020                 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_ADDRESS_ERROR)
5021                         BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_ADDRESS_ERROR\n");
5022                 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_INCORRECT_RCV_BEHAVIOR)
5023                         BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_INCORRECT_RCV_BEHAVIOR\n");
5024                 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_WAS_ERROR_ATTN)
5025                         BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_WAS_ERROR_ATTN\n");
5026                 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_VF_LENGTH_VIOLATION_ATTN)
5027                         BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_VF_LENGTH_VIOLATION_ATTN\n");
5028                 if (val &
5029                     PGLUE_B_PGLUE_B_INT_STS_REG_VF_GRC_SPACE_VIOLATION_ATTN)
5030                         BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_VF_GRC_SPACE_VIOLATION_ATTN\n");
5031                 if (val &
5032                     PGLUE_B_PGLUE_B_INT_STS_REG_VF_MSIX_BAR_VIOLATION_ATTN)
5033                         BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_VF_MSIX_BAR_VIOLATION_ATTN\n");
5034                 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_TCPL_ERROR_ATTN)
5035                         BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_TCPL_ERROR_ATTN\n");
5036                 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_TCPL_IN_TWO_RCBS_ATTN)
5037                         BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_TCPL_IN_TWO_RCBS_ATTN\n");
5038                 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_CSSNOOP_FIFO_OVERFLOW)
5039                         BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_CSSNOOP_FIFO_OVERFLOW\n");
5040         }
5041         if (attn & AEU_INPUTS_ATTN_BITS_ATC_HW_INTERRUPT) {
5042                 val = REG_RD(bp, ATC_REG_ATC_INT_STS_CLR);
5043                 BNX2X_ERR("ATC hw attention 0x%x\n", val);
5044                 if (val & ATC_ATC_INT_STS_REG_ADDRESS_ERROR)
5045                         BNX2X_ERR("ATC_ATC_INT_STS_REG_ADDRESS_ERROR\n");
5046                 if (val & ATC_ATC_INT_STS_REG_ATC_TCPL_TO_NOT_PEND)
5047                         BNX2X_ERR("ATC_ATC_INT_STS_REG_ATC_TCPL_TO_NOT_PEND\n");
5048                 if (val & ATC_ATC_INT_STS_REG_ATC_GPA_MULTIPLE_HITS)
5049                         BNX2X_ERR("ATC_ATC_INT_STS_REG_ATC_GPA_MULTIPLE_HITS\n");
5050                 if (val & ATC_ATC_INT_STS_REG_ATC_RCPL_TO_EMPTY_CNT)
5051                         BNX2X_ERR("ATC_ATC_INT_STS_REG_ATC_RCPL_TO_EMPTY_CNT\n");
5052                 if (val & ATC_ATC_INT_STS_REG_ATC_TCPL_ERROR)
5053                         BNX2X_ERR("ATC_ATC_INT_STS_REG_ATC_TCPL_ERROR\n");
5054                 if (val & ATC_ATC_INT_STS_REG_ATC_IREQ_LESS_THAN_STU)
5055                         BNX2X_ERR("ATC_ATC_INT_STS_REG_ATC_IREQ_LESS_THAN_STU\n");
5056         }
5057
5058         if (attn & (AEU_INPUTS_ATTN_BITS_PGLUE_PARITY_ERROR |
5059                     AEU_INPUTS_ATTN_BITS_ATC_PARITY_ERROR)) {
5060                 BNX2X_ERR("FATAL parity attention set4 0x%x\n",
5061                 (u32)(attn & (AEU_INPUTS_ATTN_BITS_PGLUE_PARITY_ERROR |
5062                     AEU_INPUTS_ATTN_BITS_ATC_PARITY_ERROR)));
5063         }
5064 }
5065
5066 static void bnx2x_attn_int_deasserted(struct bnx2x *bp, u32 deasserted)
5067 {
5068         struct attn_route attn, *group_mask;
5069         int port = BP_PORT(bp);
5070         int index;
5071         u32 reg_addr;
5072         u32 val;
5073         u32 aeu_mask;
5074         bool global = false;
5075
5076         /* need to take HW lock because MCP or other port might also
5077            try to handle this event */
5078         bnx2x_acquire_alr(bp);
5079
5080         if (bnx2x_chk_parity_attn(bp, &global, true)) {
5081 #ifndef BNX2X_STOP_ON_ERROR
5082                 bp->recovery_state = BNX2X_RECOVERY_INIT;
5083                 schedule_delayed_work(&bp->sp_rtnl_task, 0);
5084                 /* Disable HW interrupts */
5085                 bnx2x_int_disable(bp);
5086                 /* In case of parity errors don't handle attentions so that
5087                  * other function would "see" parity errors.
5088                  */
5089 #else
5090                 bnx2x_panic();
5091 #endif
5092                 bnx2x_release_alr(bp);
5093                 return;
5094         }
5095
5096         attn.sig[0] = REG_RD(bp, MISC_REG_AEU_AFTER_INVERT_1_FUNC_0 + port*4);
5097         attn.sig[1] = REG_RD(bp, MISC_REG_AEU_AFTER_INVERT_2_FUNC_0 + port*4);
5098         attn.sig[2] = REG_RD(bp, MISC_REG_AEU_AFTER_INVERT_3_FUNC_0 + port*4);
5099         attn.sig[3] = REG_RD(bp, MISC_REG_AEU_AFTER_INVERT_4_FUNC_0 + port*4);
5100         if (!CHIP_IS_E1x(bp))
5101                 attn.sig[4] =
5102                       REG_RD(bp, MISC_REG_AEU_AFTER_INVERT_5_FUNC_0 + port*4);
5103         else
5104                 attn.sig[4] = 0;
5105
5106         DP(NETIF_MSG_HW, "attn: %08x %08x %08x %08x %08x\n",
5107            attn.sig[0], attn.sig[1], attn.sig[2], attn.sig[3], attn.sig[4]);
5108
5109         for (index = 0; index < MAX_DYNAMIC_ATTN_GRPS; index++) {
5110                 if (deasserted & (1 << index)) {
5111                         group_mask = &bp->attn_group[index];
5112
5113                         DP(NETIF_MSG_HW, "group[%d]: %08x %08x %08x %08x %08x\n",
5114                            index,
5115                            group_mask->sig[0], group_mask->sig[1],
5116                            group_mask->sig[2], group_mask->sig[3],
5117                            group_mask->sig[4]);
5118
5119                         bnx2x_attn_int_deasserted4(bp,
5120                                         attn.sig[4] & group_mask->sig[4]);
5121                         bnx2x_attn_int_deasserted3(bp,
5122                                         attn.sig[3] & group_mask->sig[3]);
5123                         bnx2x_attn_int_deasserted1(bp,
5124                                         attn.sig[1] & group_mask->sig[1]);
5125                         bnx2x_attn_int_deasserted2(bp,
5126                                         attn.sig[2] & group_mask->sig[2]);
5127                         bnx2x_attn_int_deasserted0(bp,
5128                                         attn.sig[0] & group_mask->sig[0]);
5129                 }
5130         }
5131
5132         bnx2x_release_alr(bp);
5133
5134         if (bp->common.int_block == INT_BLOCK_HC)
5135                 reg_addr = (HC_REG_COMMAND_REG + port*32 +
5136                             COMMAND_REG_ATTN_BITS_CLR);
5137         else
5138                 reg_addr = (BAR_IGU_INTMEM + IGU_CMD_ATTN_BIT_CLR_UPPER*8);
5139
5140         val = ~deasserted;
5141         DP(NETIF_MSG_HW, "about to mask 0x%08x at %s addr 0x%x\n", val,
5142            (bp->common.int_block == INT_BLOCK_HC) ? "HC" : "IGU", reg_addr);
5143         REG_WR(bp, reg_addr, val);
5144
5145         if (~bp->attn_state & deasserted)
5146                 BNX2X_ERR("IGU ERROR\n");
5147
5148         reg_addr = port ? MISC_REG_AEU_MASK_ATTN_FUNC_1 :
5149                           MISC_REG_AEU_MASK_ATTN_FUNC_0;
5150
5151         bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_PORT0_ATT_MASK + port);
5152         aeu_mask = REG_RD(bp, reg_addr);
5153
5154         DP(NETIF_MSG_HW, "aeu_mask %x  newly deasserted %x\n",
5155            aeu_mask, deasserted);
5156         aeu_mask |= (deasserted & 0x3ff);
5157         DP(NETIF_MSG_HW, "new mask %x\n", aeu_mask);
5158
5159         REG_WR(bp, reg_addr, aeu_mask);
5160         bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_PORT0_ATT_MASK + port);
5161
5162         DP(NETIF_MSG_HW, "attn_state %x\n", bp->attn_state);
5163         bp->attn_state &= ~deasserted;
5164         DP(NETIF_MSG_HW, "new state %x\n", bp->attn_state);
5165 }
5166
5167 static void bnx2x_attn_int(struct bnx2x *bp)
5168 {
5169         /* read local copy of bits */
5170         u32 attn_bits = le32_to_cpu(bp->def_status_blk->atten_status_block.
5171                                                                 attn_bits);
5172         u32 attn_ack = le32_to_cpu(bp->def_status_blk->atten_status_block.
5173                                                                 attn_bits_ack);
5174         u32 attn_state = bp->attn_state;
5175
5176         /* look for changed bits */
5177         u32 asserted   =  attn_bits & ~attn_ack & ~attn_state;
5178         u32 deasserted = ~attn_bits &  attn_ack &  attn_state;
5179
5180         DP(NETIF_MSG_HW,
5181            "attn_bits %x  attn_ack %x  asserted %x  deasserted %x\n",
5182            attn_bits, attn_ack, asserted, deasserted);
5183
5184         if (~(attn_bits ^ attn_ack) & (attn_bits ^ attn_state))
5185                 BNX2X_ERR("BAD attention state\n");
5186
5187         /* handle bits that were raised */
5188         if (asserted)
5189                 bnx2x_attn_int_asserted(bp, asserted);
5190
5191         if (deasserted)
5192                 bnx2x_attn_int_deasserted(bp, deasserted);
5193 }
5194
5195 void bnx2x_igu_ack_sb(struct bnx2x *bp, u8 igu_sb_id, u8 segment,
5196                       u16 index, u8 op, u8 update)
5197 {
5198         u32 igu_addr = bp->igu_base_addr;
5199         igu_addr += (IGU_CMD_INT_ACK_BASE + igu_sb_id)*8;
5200         bnx2x_igu_ack_sb_gen(bp, igu_sb_id, segment, index, op, update,
5201                              igu_addr);
5202 }
5203
5204 static void bnx2x_update_eq_prod(struct bnx2x *bp, u16 prod)
5205 {
5206         /* No memory barriers */
5207         storm_memset_eq_prod(bp, prod, BP_FUNC(bp));
5208         mmiowb(); /* keep prod updates ordered */
5209 }
5210
5211 static int  bnx2x_cnic_handle_cfc_del(struct bnx2x *bp, u32 cid,
5212                                       union event_ring_elem *elem)
5213 {
5214         u8 err = elem->message.error;
5215
5216         if (!bp->cnic_eth_dev.starting_cid  ||
5217             (cid < bp->cnic_eth_dev.starting_cid &&
5218             cid != bp->cnic_eth_dev.iscsi_l2_cid))
5219                 return 1;
5220
5221         DP(BNX2X_MSG_SP, "got delete ramrod for CNIC CID %d\n", cid);
5222
5223         if (unlikely(err)) {
5224
5225                 BNX2X_ERR("got delete ramrod for CNIC CID %d with error!\n",
5226                           cid);
5227                 bnx2x_panic_dump(bp, false);
5228         }
5229         bnx2x_cnic_cfc_comp(bp, cid, err);
5230         return 0;
5231 }
5232
5233 static void bnx2x_handle_mcast_eqe(struct bnx2x *bp)
5234 {
5235         struct bnx2x_mcast_ramrod_params rparam;
5236         int rc;
5237
5238         memset(&rparam, 0, sizeof(rparam));
5239
5240         rparam.mcast_obj = &bp->mcast_obj;
5241
5242         netif_addr_lock_bh(bp->dev);
5243
5244         /* Clear pending state for the last command */
5245         bp->mcast_obj.raw.clear_pending(&bp->mcast_obj.raw);
5246
5247         /* If there are pending mcast commands - send them */
5248         if (bp->mcast_obj.check_pending(&bp->mcast_obj)) {
5249                 rc = bnx2x_config_mcast(bp, &rparam, BNX2X_MCAST_CMD_CONT);
5250                 if (rc < 0)
5251                         BNX2X_ERR("Failed to send pending mcast commands: %d\n",
5252                                   rc);
5253         }
5254
5255         netif_addr_unlock_bh(bp->dev);
5256 }
5257
5258 static void bnx2x_handle_classification_eqe(struct bnx2x *bp,
5259                                             union event_ring_elem *elem)
5260 {
5261         unsigned long ramrod_flags = 0;
5262         int rc = 0;
5263         u32 cid = elem->message.data.eth_event.echo & BNX2X_SWCID_MASK;
5264         struct bnx2x_vlan_mac_obj *vlan_mac_obj;
5265
5266         /* Always push next commands out, don't wait here */
5267         __set_bit(RAMROD_CONT, &ramrod_flags);
5268
5269         switch (le32_to_cpu((__force __le32)elem->message.data.eth_event.echo)
5270                             >> BNX2X_SWCID_SHIFT) {
5271         case BNX2X_FILTER_MAC_PENDING:
5272                 DP(BNX2X_MSG_SP, "Got SETUP_MAC completions\n");
5273                 if (CNIC_LOADED(bp) && (cid == BNX2X_ISCSI_ETH_CID(bp)))
5274                         vlan_mac_obj = &bp->iscsi_l2_mac_obj;
5275                 else
5276                         vlan_mac_obj = &bp->sp_objs[cid].mac_obj;
5277
5278                 break;
5279         case BNX2X_FILTER_MCAST_PENDING:
5280                 DP(BNX2X_MSG_SP, "Got SETUP_MCAST completions\n");
5281                 /* This is only relevant for 57710 where multicast MACs are
5282                  * configured as unicast MACs using the same ramrod.
5283                  */
5284                 bnx2x_handle_mcast_eqe(bp);
5285                 return;
5286         default:
5287                 BNX2X_ERR("Unsupported classification command: %d\n",
5288                           elem->message.data.eth_event.echo);
5289                 return;
5290         }
5291
5292         rc = vlan_mac_obj->complete(bp, vlan_mac_obj, elem, &ramrod_flags);
5293
5294         if (rc < 0)
5295                 BNX2X_ERR("Failed to schedule new commands: %d\n", rc);
5296         else if (rc > 0)
5297                 DP(BNX2X_MSG_SP, "Scheduled next pending commands...\n");
5298 }
5299
5300 static void bnx2x_set_iscsi_eth_rx_mode(struct bnx2x *bp, bool start);
5301
5302 static void bnx2x_handle_rx_mode_eqe(struct bnx2x *bp)
5303 {
5304         netif_addr_lock_bh(bp->dev);
5305
5306         clear_bit(BNX2X_FILTER_RX_MODE_PENDING, &bp->sp_state);
5307
5308         /* Send rx_mode command again if was requested */
5309         if (test_and_clear_bit(BNX2X_FILTER_RX_MODE_SCHED, &bp->sp_state))
5310                 bnx2x_set_storm_rx_mode(bp);
5311         else if (test_and_clear_bit(BNX2X_FILTER_ISCSI_ETH_START_SCHED,
5312                                     &bp->sp_state))
5313                 bnx2x_set_iscsi_eth_rx_mode(bp, true);
5314         else if (test_and_clear_bit(BNX2X_FILTER_ISCSI_ETH_STOP_SCHED,
5315                                     &bp->sp_state))
5316                 bnx2x_set_iscsi_eth_rx_mode(bp, false);
5317
5318         netif_addr_unlock_bh(bp->dev);
5319 }
5320
5321 static void bnx2x_after_afex_vif_lists(struct bnx2x *bp,
5322                                               union event_ring_elem *elem)
5323 {
5324         if (elem->message.data.vif_list_event.echo == VIF_LIST_RULE_GET) {
5325                 DP(BNX2X_MSG_SP,
5326                    "afex: ramrod completed VIF LIST_GET, addrs 0x%x\n",
5327                    elem->message.data.vif_list_event.func_bit_map);
5328                 bnx2x_fw_command(bp, DRV_MSG_CODE_AFEX_LISTGET_ACK,
5329                         elem->message.data.vif_list_event.func_bit_map);
5330         } else if (elem->message.data.vif_list_event.echo ==
5331                    VIF_LIST_RULE_SET) {
5332                 DP(BNX2X_MSG_SP, "afex: ramrod completed VIF LIST_SET\n");
5333                 bnx2x_fw_command(bp, DRV_MSG_CODE_AFEX_LISTSET_ACK, 0);
5334         }
5335 }
5336
5337 /* called with rtnl_lock */
5338 static void bnx2x_after_function_update(struct bnx2x *bp)
5339 {
5340         int q, rc;
5341         struct bnx2x_fastpath *fp;
5342         struct bnx2x_queue_state_params queue_params = {NULL};
5343         struct bnx2x_queue_update_params *q_update_params =
5344                 &queue_params.params.update;
5345
5346         /* Send Q update command with afex vlan removal values for all Qs */
5347         queue_params.cmd = BNX2X_Q_CMD_UPDATE;
5348
5349         /* set silent vlan removal values according to vlan mode */
5350         __set_bit(BNX2X_Q_UPDATE_SILENT_VLAN_REM_CHNG,
5351                   &q_update_params->update_flags);
5352         __set_bit(BNX2X_Q_UPDATE_SILENT_VLAN_REM,
5353                   &q_update_params->update_flags);
5354         __set_bit(RAMROD_COMP_WAIT, &queue_params.ramrod_flags);
5355
5356         /* in access mode mark mask and value are 0 to strip all vlans */
5357         if (bp->afex_vlan_mode == FUNC_MF_CFG_AFEX_VLAN_ACCESS_MODE) {
5358                 q_update_params->silent_removal_value = 0;
5359                 q_update_params->silent_removal_mask = 0;
5360         } else {
5361                 q_update_params->silent_removal_value =
5362                         (bp->afex_def_vlan_tag & VLAN_VID_MASK);
5363                 q_update_params->silent_removal_mask = VLAN_VID_MASK;
5364         }
5365
5366         for_each_eth_queue(bp, q) {
5367                 /* Set the appropriate Queue object */
5368                 fp = &bp->fp[q];
5369                 queue_params.q_obj = &bnx2x_sp_obj(bp, fp).q_obj;
5370
5371                 /* send the ramrod */
5372                 rc = bnx2x_queue_state_change(bp, &queue_params);
5373                 if (rc < 0)
5374                         BNX2X_ERR("Failed to config silent vlan rem for Q %d\n",
5375                                   q);
5376         }
5377
5378         if (!NO_FCOE(bp) && CNIC_ENABLED(bp)) {
5379                 fp = &bp->fp[FCOE_IDX(bp)];
5380                 queue_params.q_obj = &bnx2x_sp_obj(bp, fp).q_obj;
5381
5382                 /* clear pending completion bit */
5383                 __clear_bit(RAMROD_COMP_WAIT, &queue_params.ramrod_flags);
5384
5385                 /* mark latest Q bit */
5386                 smp_mb__before_atomic();
5387                 set_bit(BNX2X_AFEX_FCOE_Q_UPDATE_PENDING, &bp->sp_state);
5388                 smp_mb__after_atomic();
5389
5390                 /* send Q update ramrod for FCoE Q */
5391                 rc = bnx2x_queue_state_change(bp, &queue_params);
5392                 if (rc < 0)
5393                         BNX2X_ERR("Failed to config silent vlan rem for Q %d\n",
5394                                   q);
5395         } else {
5396                 /* If no FCoE ring - ACK MCP now */
5397                 bnx2x_link_report(bp);
5398                 bnx2x_fw_command(bp, DRV_MSG_CODE_AFEX_VIFSET_ACK, 0);
5399         }
5400 }
5401
5402 static struct bnx2x_queue_sp_obj *bnx2x_cid_to_q_obj(
5403         struct bnx2x *bp, u32 cid)
5404 {
5405         DP(BNX2X_MSG_SP, "retrieving fp from cid %d\n", cid);
5406
5407         if (CNIC_LOADED(bp) && (cid == BNX2X_FCOE_ETH_CID(bp)))
5408                 return &bnx2x_fcoe_sp_obj(bp, q_obj);
5409         else
5410                 return &bp->sp_objs[CID_TO_FP(cid, bp)].q_obj;
5411 }
5412
5413 static void bnx2x_eq_int(struct bnx2x *bp)
5414 {
5415         u16 hw_cons, sw_cons, sw_prod;
5416         union event_ring_elem *elem;
5417         u8 echo;
5418         u32 cid;
5419         u8 opcode;
5420         int rc, spqe_cnt = 0;
5421         struct bnx2x_queue_sp_obj *q_obj;
5422         struct bnx2x_func_sp_obj *f_obj = &bp->func_obj;
5423         struct bnx2x_raw_obj *rss_raw = &bp->rss_conf_obj.raw;
5424
5425         hw_cons = le16_to_cpu(*bp->eq_cons_sb);
5426
5427         /* The hw_cos range is 1-255, 257 - the sw_cons range is 0-254, 256.
5428          * when we get the next-page we need to adjust so the loop
5429          * condition below will be met. The next element is the size of a
5430          * regular element and hence incrementing by 1
5431          */
5432         if ((hw_cons & EQ_DESC_MAX_PAGE) == EQ_DESC_MAX_PAGE)
5433                 hw_cons++;
5434
5435         /* This function may never run in parallel with itself for a
5436          * specific bp, thus there is no need in "paired" read memory
5437          * barrier here.
5438          */
5439         sw_cons = bp->eq_cons;
5440         sw_prod = bp->eq_prod;
5441
5442         DP(BNX2X_MSG_SP, "EQ:  hw_cons %u  sw_cons %u bp->eq_spq_left %x\n",
5443                         hw_cons, sw_cons, atomic_read(&bp->eq_spq_left));
5444
5445         for (; sw_cons != hw_cons;
5446               sw_prod = NEXT_EQ_IDX(sw_prod), sw_cons = NEXT_EQ_IDX(sw_cons)) {
5447
5448                 elem = &bp->eq_ring[EQ_DESC(sw_cons)];
5449
5450                 rc = bnx2x_iov_eq_sp_event(bp, elem);
5451                 if (!rc) {
5452                         DP(BNX2X_MSG_IOV, "bnx2x_iov_eq_sp_event returned %d\n",
5453                            rc);
5454                         goto next_spqe;
5455                 }
5456
5457                 /* elem CID originates from FW; actually LE */
5458                 cid = SW_CID((__force __le32)
5459                              elem->message.data.cfc_del_event.cid);
5460                 opcode = elem->message.opcode;
5461
5462                 /* handle eq element */
5463                 switch (opcode) {
5464                 case EVENT_RING_OPCODE_VF_PF_CHANNEL:
5465                         bnx2x_vf_mbx_schedule(bp,
5466                                               &elem->message.data.vf_pf_event);
5467                         continue;
5468
5469                 case EVENT_RING_OPCODE_STAT_QUERY:
5470                         DP_AND((BNX2X_MSG_SP | BNX2X_MSG_STATS),
5471                                "got statistics comp event %d\n",
5472                                bp->stats_comp++);
5473                         /* nothing to do with stats comp */
5474                         goto next_spqe;
5475
5476                 case EVENT_RING_OPCODE_CFC_DEL:
5477                         /* handle according to cid range */
5478                         /*
5479                          * we may want to verify here that the bp state is
5480                          * HALTING
5481                          */
5482                         DP(BNX2X_MSG_SP,
5483                            "got delete ramrod for MULTI[%d]\n", cid);
5484
5485                         if (CNIC_LOADED(bp) &&
5486                             !bnx2x_cnic_handle_cfc_del(bp, cid, elem))
5487                                 goto next_spqe;
5488
5489                         q_obj = bnx2x_cid_to_q_obj(bp, cid);
5490
5491                         if (q_obj->complete_cmd(bp, q_obj, BNX2X_Q_CMD_CFC_DEL))
5492                                 break;
5493
5494                         goto next_spqe;
5495
5496                 case EVENT_RING_OPCODE_STOP_TRAFFIC:
5497                         DP(BNX2X_MSG_SP | BNX2X_MSG_DCB, "got STOP TRAFFIC\n");
5498                         bnx2x_dcbx_set_params(bp, BNX2X_DCBX_STATE_TX_PAUSED);
5499                         if (f_obj->complete_cmd(bp, f_obj,
5500                                                 BNX2X_F_CMD_TX_STOP))
5501                                 break;
5502                         goto next_spqe;
5503
5504                 case EVENT_RING_OPCODE_START_TRAFFIC:
5505                         DP(BNX2X_MSG_SP | BNX2X_MSG_DCB, "got START TRAFFIC\n");
5506                         bnx2x_dcbx_set_params(bp, BNX2X_DCBX_STATE_TX_RELEASED);
5507                         if (f_obj->complete_cmd(bp, f_obj,
5508                                                 BNX2X_F_CMD_TX_START))
5509                                 break;
5510                         goto next_spqe;
5511
5512                 case EVENT_RING_OPCODE_FUNCTION_UPDATE:
5513                         echo = elem->message.data.function_update_event.echo;
5514                         if (echo == SWITCH_UPDATE) {
5515                                 DP(BNX2X_MSG_SP | NETIF_MSG_IFUP,
5516                                    "got FUNC_SWITCH_UPDATE ramrod\n");
5517                                 if (f_obj->complete_cmd(
5518                                         bp, f_obj, BNX2X_F_CMD_SWITCH_UPDATE))
5519                                         break;
5520
5521                         } else {
5522                                 int cmd = BNX2X_SP_RTNL_AFEX_F_UPDATE;
5523
5524                                 DP(BNX2X_MSG_SP | BNX2X_MSG_MCP,
5525                                    "AFEX: ramrod completed FUNCTION_UPDATE\n");
5526                                 f_obj->complete_cmd(bp, f_obj,
5527                                                     BNX2X_F_CMD_AFEX_UPDATE);
5528
5529                                 /* We will perform the Queues update from
5530                                  * sp_rtnl task as all Queue SP operations
5531                                  * should run under rtnl_lock.
5532                                  */
5533                                 bnx2x_schedule_sp_rtnl(bp, cmd, 0);
5534                         }
5535
5536                         goto next_spqe;
5537
5538                 case EVENT_RING_OPCODE_AFEX_VIF_LISTS:
5539                         f_obj->complete_cmd(bp, f_obj,
5540                                             BNX2X_F_CMD_AFEX_VIFLISTS);
5541                         bnx2x_after_afex_vif_lists(bp, elem);
5542                         goto next_spqe;
5543                 case EVENT_RING_OPCODE_FUNCTION_START:
5544                         DP(BNX2X_MSG_SP | NETIF_MSG_IFUP,
5545                            "got FUNC_START ramrod\n");
5546                         if (f_obj->complete_cmd(bp, f_obj, BNX2X_F_CMD_START))
5547                                 break;
5548
5549                         goto next_spqe;
5550
5551                 case EVENT_RING_OPCODE_FUNCTION_STOP:
5552                         DP(BNX2X_MSG_SP | NETIF_MSG_IFUP,
5553                            "got FUNC_STOP ramrod\n");
5554                         if (f_obj->complete_cmd(bp, f_obj, BNX2X_F_CMD_STOP))
5555                                 break;
5556
5557                         goto next_spqe;
5558
5559                 case EVENT_RING_OPCODE_SET_TIMESYNC:
5560                         DP(BNX2X_MSG_SP | BNX2X_MSG_PTP,
5561                            "got set_timesync ramrod completion\n");
5562                         if (f_obj->complete_cmd(bp, f_obj,
5563                                                 BNX2X_F_CMD_SET_TIMESYNC))
5564                                 break;
5565                         goto next_spqe;
5566                 }
5567
5568                 switch (opcode | bp->state) {
5569                 case (EVENT_RING_OPCODE_RSS_UPDATE_RULES |
5570                       BNX2X_STATE_OPEN):
5571                 case (EVENT_RING_OPCODE_RSS_UPDATE_RULES |
5572                       BNX2X_STATE_OPENING_WAIT4_PORT):
5573                 case (EVENT_RING_OPCODE_RSS_UPDATE_RULES |
5574                       BNX2X_STATE_CLOSING_WAIT4_HALT):
5575                         cid = elem->message.data.eth_event.echo &
5576                                 BNX2X_SWCID_MASK;
5577                         DP(BNX2X_MSG_SP, "got RSS_UPDATE ramrod. CID %d\n",
5578                            cid);
5579                         rss_raw->clear_pending(rss_raw);
5580                         break;
5581
5582                 case (EVENT_RING_OPCODE_SET_MAC | BNX2X_STATE_OPEN):
5583                 case (EVENT_RING_OPCODE_SET_MAC | BNX2X_STATE_DIAG):
5584                 case (EVENT_RING_OPCODE_SET_MAC |
5585                       BNX2X_STATE_CLOSING_WAIT4_HALT):
5586                 case (EVENT_RING_OPCODE_CLASSIFICATION_RULES |
5587                       BNX2X_STATE_OPEN):
5588                 case (EVENT_RING_OPCODE_CLASSIFICATION_RULES |
5589                       BNX2X_STATE_DIAG):
5590                 case (EVENT_RING_OPCODE_CLASSIFICATION_RULES |
5591                       BNX2X_STATE_CLOSING_WAIT4_HALT):
5592                         DP(BNX2X_MSG_SP, "got (un)set mac ramrod\n");
5593                         bnx2x_handle_classification_eqe(bp, elem);
5594                         break;
5595
5596                 case (EVENT_RING_OPCODE_MULTICAST_RULES |
5597                       BNX2X_STATE_OPEN):
5598                 case (EVENT_RING_OPCODE_MULTICAST_RULES |
5599                       BNX2X_STATE_DIAG):
5600                 case (EVENT_RING_OPCODE_MULTICAST_RULES |
5601                       BNX2X_STATE_CLOSING_WAIT4_HALT):
5602                         DP(BNX2X_MSG_SP, "got mcast ramrod\n");
5603                         bnx2x_handle_mcast_eqe(bp);
5604                         break;
5605
5606                 case (EVENT_RING_OPCODE_FILTERS_RULES |
5607                       BNX2X_STATE_OPEN):
5608                 case (EVENT_RING_OPCODE_FILTERS_RULES |
5609                       BNX2X_STATE_DIAG):
5610                 case (EVENT_RING_OPCODE_FILTERS_RULES |
5611                       BNX2X_STATE_CLOSING_WAIT4_HALT):
5612                         DP(BNX2X_MSG_SP, "got rx_mode ramrod\n");
5613                         bnx2x_handle_rx_mode_eqe(bp);
5614                         break;
5615                 default:
5616                         /* unknown event log error and continue */
5617                         BNX2X_ERR("Unknown EQ event %d, bp->state 0x%x\n",
5618                                   elem->message.opcode, bp->state);
5619                 }
5620 next_spqe:
5621                 spqe_cnt++;
5622         } /* for */
5623
5624         smp_mb__before_atomic();
5625         atomic_add(spqe_cnt, &bp->eq_spq_left);
5626
5627         bp->eq_cons = sw_cons;
5628         bp->eq_prod = sw_prod;
5629         /* Make sure that above mem writes were issued towards the memory */
5630         smp_wmb();
5631
5632         /* update producer */
5633         bnx2x_update_eq_prod(bp, bp->eq_prod);
5634 }
5635
5636 static void bnx2x_sp_task(struct work_struct *work)
5637 {
5638         struct bnx2x *bp = container_of(work, struct bnx2x, sp_task.work);
5639
5640         DP(BNX2X_MSG_SP, "sp task invoked\n");
5641
5642         /* make sure the atomic interrupt_occurred has been written */
5643         smp_rmb();
5644         if (atomic_read(&bp->interrupt_occurred)) {
5645
5646                 /* what work needs to be performed? */
5647                 u16 status = bnx2x_update_dsb_idx(bp);
5648
5649                 DP(BNX2X_MSG_SP, "status %x\n", status);
5650                 DP(BNX2X_MSG_SP, "setting interrupt_occurred to 0\n");
5651                 atomic_set(&bp->interrupt_occurred, 0);
5652
5653                 /* HW attentions */
5654                 if (status & BNX2X_DEF_SB_ATT_IDX) {
5655                         bnx2x_attn_int(bp);
5656                         status &= ~BNX2X_DEF_SB_ATT_IDX;
5657                 }
5658
5659                 /* SP events: STAT_QUERY and others */
5660                 if (status & BNX2X_DEF_SB_IDX) {
5661                         struct bnx2x_fastpath *fp = bnx2x_fcoe_fp(bp);
5662
5663                 if (FCOE_INIT(bp) &&
5664                             (bnx2x_has_rx_work(fp) || bnx2x_has_tx_work(fp))) {
5665                                 /* Prevent local bottom-halves from running as
5666                                  * we are going to change the local NAPI list.
5667                                  */
5668                                 local_bh_disable();
5669                                 napi_schedule(&bnx2x_fcoe(bp, napi));
5670                                 local_bh_enable();
5671                         }
5672
5673                         /* Handle EQ completions */
5674                         bnx2x_eq_int(bp);
5675                         bnx2x_ack_sb(bp, bp->igu_dsb_id, USTORM_ID,
5676                                      le16_to_cpu(bp->def_idx), IGU_INT_NOP, 1);
5677
5678                         status &= ~BNX2X_DEF_SB_IDX;
5679                 }
5680
5681                 /* if status is non zero then perhaps something went wrong */
5682                 if (unlikely(status))
5683                         DP(BNX2X_MSG_SP,
5684                            "got an unknown interrupt! (status 0x%x)\n", status);
5685
5686                 /* ack status block only if something was actually handled */
5687                 bnx2x_ack_sb(bp, bp->igu_dsb_id, ATTENTION_ID,
5688                              le16_to_cpu(bp->def_att_idx), IGU_INT_ENABLE, 1);
5689         }
5690
5691         /* afex - poll to check if VIFSET_ACK should be sent to MFW */
5692         if (test_and_clear_bit(BNX2X_AFEX_PENDING_VIFSET_MCP_ACK,
5693                                &bp->sp_state)) {
5694                 bnx2x_link_report(bp);
5695                 bnx2x_fw_command(bp, DRV_MSG_CODE_AFEX_VIFSET_ACK, 0);
5696         }
5697 }
5698
5699 irqreturn_t bnx2x_msix_sp_int(int irq, void *dev_instance)
5700 {
5701         struct net_device *dev = dev_instance;
5702         struct bnx2x *bp = netdev_priv(dev);
5703
5704         bnx2x_ack_sb(bp, bp->igu_dsb_id, USTORM_ID, 0,
5705                      IGU_INT_DISABLE, 0);
5706
5707 #ifdef BNX2X_STOP_ON_ERROR
5708         if (unlikely(bp->panic))
5709                 return IRQ_HANDLED;
5710 #endif
5711
5712         if (CNIC_LOADED(bp)) {
5713                 struct cnic_ops *c_ops;
5714
5715                 rcu_read_lock();
5716                 c_ops = rcu_dereference(bp->cnic_ops);
5717                 if (c_ops)
5718                         c_ops->cnic_handler(bp->cnic_data, NULL);
5719                 rcu_read_unlock();
5720         }
5721
5722         /* schedule sp task to perform default status block work, ack
5723          * attentions and enable interrupts.
5724          */
5725         bnx2x_schedule_sp_task(bp);
5726
5727         return IRQ_HANDLED;
5728 }
5729
5730 /* end of slow path */
5731
5732 void bnx2x_drv_pulse(struct bnx2x *bp)
5733 {
5734         SHMEM_WR(bp, func_mb[BP_FW_MB_IDX(bp)].drv_pulse_mb,
5735                  bp->fw_drv_pulse_wr_seq);
5736 }
5737
5738 static void bnx2x_timer(unsigned long data)
5739 {
5740         struct bnx2x *bp = (struct bnx2x *) data;
5741
5742         if (!netif_running(bp->dev))
5743                 return;
5744
5745         if (IS_PF(bp) &&
5746             !BP_NOMCP(bp)) {
5747                 int mb_idx = BP_FW_MB_IDX(bp);
5748                 u16 drv_pulse;
5749                 u16 mcp_pulse;
5750
5751                 ++bp->fw_drv_pulse_wr_seq;
5752                 bp->fw_drv_pulse_wr_seq &= DRV_PULSE_SEQ_MASK;
5753                 drv_pulse = bp->fw_drv_pulse_wr_seq;
5754                 bnx2x_drv_pulse(bp);
5755
5756                 mcp_pulse = (SHMEM_RD(bp, func_mb[mb_idx].mcp_pulse_mb) &
5757                              MCP_PULSE_SEQ_MASK);
5758                 /* The delta between driver pulse and mcp response
5759                  * should not get too big. If the MFW is more than 5 pulses
5760                  * behind, we should worry about it enough to generate an error
5761                  * log.
5762                  */
5763                 if (((drv_pulse - mcp_pulse) & MCP_PULSE_SEQ_MASK) > 5)
5764                         BNX2X_ERR("MFW seems hanged: drv_pulse (0x%x) != mcp_pulse (0x%x)\n",
5765                                   drv_pulse, mcp_pulse);
5766         }
5767
5768         if (bp->state == BNX2X_STATE_OPEN)
5769                 bnx2x_stats_handle(bp, STATS_EVENT_UPDATE);
5770
5771         /* sample pf vf bulletin board for new posts from pf */
5772         if (IS_VF(bp))
5773                 bnx2x_timer_sriov(bp);
5774
5775         mod_timer(&bp->timer, jiffies + bp->current_interval);
5776 }
5777
5778 /* end of Statistics */
5779
5780 /* nic init */
5781
5782 /*
5783  * nic init service functions
5784  */
5785
5786 static void bnx2x_fill(struct bnx2x *bp, u32 addr, int fill, u32 len)
5787 {
5788         u32 i;
5789         if (!(len%4) && !(addr%4))
5790                 for (i = 0; i < len; i += 4)
5791                         REG_WR(bp, addr + i, fill);
5792         else
5793                 for (i = 0; i < len; i++)
5794                         REG_WR8(bp, addr + i, fill);
5795 }
5796
5797 /* helper: writes FP SP data to FW - data_size in dwords */
5798 static void bnx2x_wr_fp_sb_data(struct bnx2x *bp,
5799                                 int fw_sb_id,
5800                                 u32 *sb_data_p,
5801                                 u32 data_size)
5802 {
5803         int index;
5804         for (index = 0; index < data_size; index++)
5805                 REG_WR(bp, BAR_CSTRORM_INTMEM +
5806                         CSTORM_STATUS_BLOCK_DATA_OFFSET(fw_sb_id) +
5807                         sizeof(u32)*index,
5808                         *(sb_data_p + index));
5809 }
5810
5811 static void bnx2x_zero_fp_sb(struct bnx2x *bp, int fw_sb_id)
5812 {
5813         u32 *sb_data_p;
5814         u32 data_size = 0;
5815         struct hc_status_block_data_e2 sb_data_e2;
5816         struct hc_status_block_data_e1x sb_data_e1x;
5817
5818         /* disable the function first */
5819         if (!CHIP_IS_E1x(bp)) {
5820                 memset(&sb_data_e2, 0, sizeof(struct hc_status_block_data_e2));
5821                 sb_data_e2.common.state = SB_DISABLED;
5822                 sb_data_e2.common.p_func.vf_valid = false;
5823                 sb_data_p = (u32 *)&sb_data_e2;
5824                 data_size = sizeof(struct hc_status_block_data_e2)/sizeof(u32);
5825         } else {
5826                 memset(&sb_data_e1x, 0,
5827                        sizeof(struct hc_status_block_data_e1x));
5828                 sb_data_e1x.common.state = SB_DISABLED;
5829                 sb_data_e1x.common.p_func.vf_valid = false;
5830                 sb_data_p = (u32 *)&sb_data_e1x;
5831                 data_size = sizeof(struct hc_status_block_data_e1x)/sizeof(u32);
5832         }
5833         bnx2x_wr_fp_sb_data(bp, fw_sb_id, sb_data_p, data_size);
5834
5835         bnx2x_fill(bp, BAR_CSTRORM_INTMEM +
5836                         CSTORM_STATUS_BLOCK_OFFSET(fw_sb_id), 0,
5837                         CSTORM_STATUS_BLOCK_SIZE);
5838         bnx2x_fill(bp, BAR_CSTRORM_INTMEM +
5839                         CSTORM_SYNC_BLOCK_OFFSET(fw_sb_id), 0,
5840                         CSTORM_SYNC_BLOCK_SIZE);
5841 }
5842
5843 /* helper:  writes SP SB data to FW */
5844 static void bnx2x_wr_sp_sb_data(struct bnx2x *bp,
5845                 struct hc_sp_status_block_data *sp_sb_data)
5846 {
5847         int func = BP_FUNC(bp);
5848         int i;
5849         for (i = 0; i < sizeof(struct hc_sp_status_block_data)/sizeof(u32); i++)
5850                 REG_WR(bp, BAR_CSTRORM_INTMEM +
5851                         CSTORM_SP_STATUS_BLOCK_DATA_OFFSET(func) +
5852                         i*sizeof(u32),
5853                         *((u32 *)sp_sb_data + i));
5854 }
5855
5856 static void bnx2x_zero_sp_sb(struct bnx2x *bp)
5857 {
5858         int func = BP_FUNC(bp);
5859         struct hc_sp_status_block_data sp_sb_data;
5860         memset(&sp_sb_data, 0, sizeof(struct hc_sp_status_block_data));
5861
5862         sp_sb_data.state = SB_DISABLED;
5863         sp_sb_data.p_func.vf_valid = false;
5864
5865         bnx2x_wr_sp_sb_data(bp, &sp_sb_data);
5866
5867         bnx2x_fill(bp, BAR_CSTRORM_INTMEM +
5868                         CSTORM_SP_STATUS_BLOCK_OFFSET(func), 0,
5869                         CSTORM_SP_STATUS_BLOCK_SIZE);
5870         bnx2x_fill(bp, BAR_CSTRORM_INTMEM +
5871                         CSTORM_SP_SYNC_BLOCK_OFFSET(func), 0,
5872                         CSTORM_SP_SYNC_BLOCK_SIZE);
5873 }
5874
5875 static void bnx2x_setup_ndsb_state_machine(struct hc_status_block_sm *hc_sm,
5876                                            int igu_sb_id, int igu_seg_id)
5877 {
5878         hc_sm->igu_sb_id = igu_sb_id;
5879         hc_sm->igu_seg_id = igu_seg_id;
5880         hc_sm->timer_value = 0xFF;
5881         hc_sm->time_to_expire = 0xFFFFFFFF;
5882 }
5883
5884 /* allocates state machine ids. */
5885 static void bnx2x_map_sb_state_machines(struct hc_index_data *index_data)
5886 {
5887         /* zero out state machine indices */
5888         /* rx indices */
5889         index_data[HC_INDEX_ETH_RX_CQ_CONS].flags &= ~HC_INDEX_DATA_SM_ID;
5890
5891         /* tx indices */
5892         index_data[HC_INDEX_OOO_TX_CQ_CONS].flags &= ~HC_INDEX_DATA_SM_ID;
5893         index_data[HC_INDEX_ETH_TX_CQ_CONS_COS0].flags &= ~HC_INDEX_DATA_SM_ID;
5894         index_data[HC_INDEX_ETH_TX_CQ_CONS_COS1].flags &= ~HC_INDEX_DATA_SM_ID;
5895         index_data[HC_INDEX_ETH_TX_CQ_CONS_COS2].flags &= ~HC_INDEX_DATA_SM_ID;
5896
5897         /* map indices */
5898         /* rx indices */
5899         index_data[HC_INDEX_ETH_RX_CQ_CONS].flags |=
5900                 SM_RX_ID << HC_INDEX_DATA_SM_ID_SHIFT;
5901
5902         /* tx indices */
5903         index_data[HC_INDEX_OOO_TX_CQ_CONS].flags |=
5904                 SM_TX_ID << HC_INDEX_DATA_SM_ID_SHIFT;
5905         index_data[HC_INDEX_ETH_TX_CQ_CONS_COS0].flags |=
5906                 SM_TX_ID << HC_INDEX_DATA_SM_ID_SHIFT;
5907         index_data[HC_INDEX_ETH_TX_CQ_CONS_COS1].flags |=
5908                 SM_TX_ID << HC_INDEX_DATA_SM_ID_SHIFT;
5909         index_data[HC_INDEX_ETH_TX_CQ_CONS_COS2].flags |=
5910                 SM_TX_ID << HC_INDEX_DATA_SM_ID_SHIFT;
5911 }
5912
5913 void bnx2x_init_sb(struct bnx2x *bp, dma_addr_t mapping, int vfid,
5914                           u8 vf_valid, int fw_sb_id, int igu_sb_id)
5915 {
5916         int igu_seg_id;
5917
5918         struct hc_status_block_data_e2 sb_data_e2;
5919         struct hc_status_block_data_e1x sb_data_e1x;
5920         struct hc_status_block_sm  *hc_sm_p;
5921         int data_size;
5922         u32 *sb_data_p;
5923
5924         if (CHIP_INT_MODE_IS_BC(bp))
5925                 igu_seg_id = HC_SEG_ACCESS_NORM;
5926         else
5927                 igu_seg_id = IGU_SEG_ACCESS_NORM;
5928
5929         bnx2x_zero_fp_sb(bp, fw_sb_id);
5930
5931         if (!CHIP_IS_E1x(bp)) {
5932                 memset(&sb_data_e2, 0, sizeof(struct hc_status_block_data_e2));
5933                 sb_data_e2.common.state = SB_ENABLED;
5934                 sb_data_e2.common.p_func.pf_id = BP_FUNC(bp);
5935                 sb_data_e2.common.p_func.vf_id = vfid;
5936                 sb_data_e2.common.p_func.vf_valid = vf_valid;
5937                 sb_data_e2.common.p_func.vnic_id = BP_VN(bp);
5938                 sb_data_e2.common.same_igu_sb_1b = true;
5939                 sb_data_e2.common.host_sb_addr.hi = U64_HI(mapping);
5940                 sb_data_e2.common.host_sb_addr.lo = U64_LO(mapping);
5941                 hc_sm_p = sb_data_e2.common.state_machine;
5942                 sb_data_p = (u32 *)&sb_data_e2;
5943                 data_size = sizeof(struct hc_status_block_data_e2)/sizeof(u32);
5944                 bnx2x_map_sb_state_machines(sb_data_e2.index_data);
5945         } else {
5946                 memset(&sb_data_e1x, 0,
5947                        sizeof(struct hc_status_block_data_e1x));
5948                 sb_data_e1x.common.state = SB_ENABLED;
5949                 sb_data_e1x.common.p_func.pf_id = BP_FUNC(bp);
5950                 sb_data_e1x.common.p_func.vf_id = 0xff;
5951                 sb_data_e1x.common.p_func.vf_valid = false;
5952                 sb_data_e1x.common.p_func.vnic_id = BP_VN(bp);
5953                 sb_data_e1x.common.same_igu_sb_1b = true;
5954                 sb_data_e1x.common.host_sb_addr.hi = U64_HI(mapping);
5955                 sb_data_e1x.common.host_sb_addr.lo = U64_LO(mapping);
5956                 hc_sm_p = sb_data_e1x.common.state_machine;
5957                 sb_data_p = (u32 *)&sb_data_e1x;
5958                 data_size = sizeof(struct hc_status_block_data_e1x)/sizeof(u32);
5959                 bnx2x_map_sb_state_machines(sb_data_e1x.index_data);
5960         }
5961
5962         bnx2x_setup_ndsb_state_machine(&hc_sm_p[SM_RX_ID],
5963                                        igu_sb_id, igu_seg_id);
5964         bnx2x_setup_ndsb_state_machine(&hc_sm_p[SM_TX_ID],
5965                                        igu_sb_id, igu_seg_id);
5966
5967         DP(NETIF_MSG_IFUP, "Init FW SB %d\n", fw_sb_id);
5968
5969         /* write indices to HW - PCI guarantees endianity of regpairs */
5970         bnx2x_wr_fp_sb_data(bp, fw_sb_id, sb_data_p, data_size);
5971 }
5972
5973 static void bnx2x_update_coalesce_sb(struct bnx2x *bp, u8 fw_sb_id,
5974                                      u16 tx_usec, u16 rx_usec)
5975 {
5976         bnx2x_update_coalesce_sb_index(bp, fw_sb_id, HC_INDEX_ETH_RX_CQ_CONS,
5977                                     false, rx_usec);
5978         bnx2x_update_coalesce_sb_index(bp, fw_sb_id,
5979                                        HC_INDEX_ETH_TX_CQ_CONS_COS0, false,
5980                                        tx_usec);
5981         bnx2x_update_coalesce_sb_index(bp, fw_sb_id,
5982                                        HC_INDEX_ETH_TX_CQ_CONS_COS1, false,
5983                                        tx_usec);
5984         bnx2x_update_coalesce_sb_index(bp, fw_sb_id,
5985                                        HC_INDEX_ETH_TX_CQ_CONS_COS2, false,
5986                                        tx_usec);
5987 }
5988
5989 static void bnx2x_init_def_sb(struct bnx2x *bp)
5990 {
5991         struct host_sp_status_block *def_sb = bp->def_status_blk;
5992         dma_addr_t mapping = bp->def_status_blk_mapping;
5993         int igu_sp_sb_index;
5994         int igu_seg_id;
5995         int port = BP_PORT(bp);
5996         int func = BP_FUNC(bp);
5997         int reg_offset, reg_offset_en5;
5998         u64 section;
5999         int index;
6000         struct hc_sp_status_block_data sp_sb_data;
6001         memset(&sp_sb_data, 0, sizeof(struct hc_sp_status_block_data));
6002
6003         if (CHIP_INT_MODE_IS_BC(bp)) {
6004                 igu_sp_sb_index = DEF_SB_IGU_ID;
6005                 igu_seg_id = HC_SEG_ACCESS_DEF;
6006         } else {
6007                 igu_sp_sb_index = bp->igu_dsb_id;
6008                 igu_seg_id = IGU_SEG_ACCESS_DEF;
6009         }
6010
6011         /* ATTN */
6012         section = ((u64)mapping) + offsetof(struct host_sp_status_block,
6013                                             atten_status_block);
6014         def_sb->atten_status_block.status_block_id = igu_sp_sb_index;
6015
6016         bp->attn_state = 0;
6017
6018         reg_offset = (port ? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_0 :
6019                              MISC_REG_AEU_ENABLE1_FUNC_0_OUT_0);
6020         reg_offset_en5 = (port ? MISC_REG_AEU_ENABLE5_FUNC_1_OUT_0 :
6021                                  MISC_REG_AEU_ENABLE5_FUNC_0_OUT_0);
6022         for (index = 0; index < MAX_DYNAMIC_ATTN_GRPS; index++) {
6023                 int sindex;
6024                 /* take care of sig[0]..sig[4] */
6025                 for (sindex = 0; sindex < 4; sindex++)
6026                         bp->attn_group[index].sig[sindex] =
6027                            REG_RD(bp, reg_offset + sindex*0x4 + 0x10*index);
6028
6029                 if (!CHIP_IS_E1x(bp))
6030                         /*
6031                          * enable5 is separate from the rest of the registers,
6032                          * and therefore the address skip is 4
6033                          * and not 16 between the different groups
6034                          */
6035                         bp->attn_group[index].sig[4] = REG_RD(bp,
6036                                         reg_offset_en5 + 0x4*index);
6037                 else
6038                         bp->attn_group[index].sig[4] = 0;
6039         }
6040
6041         if (bp->common.int_block == INT_BLOCK_HC) {
6042                 reg_offset = (port ? HC_REG_ATTN_MSG1_ADDR_L :
6043                                      HC_REG_ATTN_MSG0_ADDR_L);
6044
6045                 REG_WR(bp, reg_offset, U64_LO(section));
6046                 REG_WR(bp, reg_offset + 4, U64_HI(section));
6047         } else if (!CHIP_IS_E1x(bp)) {
6048                 REG_WR(bp, IGU_REG_ATTN_MSG_ADDR_L, U64_LO(section));
6049                 REG_WR(bp, IGU_REG_ATTN_MSG_ADDR_H, U64_HI(section));
6050         }
6051
6052         section = ((u64)mapping) + offsetof(struct host_sp_status_block,
6053                                             sp_sb);
6054
6055         bnx2x_zero_sp_sb(bp);
6056
6057         /* PCI guarantees endianity of regpairs */
6058         sp_sb_data.state                = SB_ENABLED;
6059         sp_sb_data.host_sb_addr.lo      = U64_LO(section);
6060         sp_sb_data.host_sb_addr.hi      = U64_HI(section);
6061         sp_sb_data.igu_sb_id            = igu_sp_sb_index;
6062         sp_sb_data.igu_seg_id           = igu_seg_id;
6063         sp_sb_data.p_func.pf_id         = func;
6064         sp_sb_data.p_func.vnic_id       = BP_VN(bp);
6065         sp_sb_data.p_func.vf_id         = 0xff;
6066
6067         bnx2x_wr_sp_sb_data(bp, &sp_sb_data);
6068
6069         bnx2x_ack_sb(bp, bp->igu_dsb_id, USTORM_ID, 0, IGU_INT_ENABLE, 0);
6070 }
6071
6072 void bnx2x_update_coalesce(struct bnx2x *bp)
6073 {
6074         int i;
6075
6076         for_each_eth_queue(bp, i)
6077                 bnx2x_update_coalesce_sb(bp, bp->fp[i].fw_sb_id,
6078                                          bp->tx_ticks, bp->rx_ticks);
6079 }
6080
6081 static void bnx2x_init_sp_ring(struct bnx2x *bp)
6082 {
6083         spin_lock_init(&bp->spq_lock);
6084         atomic_set(&bp->cq_spq_left, MAX_SPQ_PENDING);
6085
6086         bp->spq_prod_idx = 0;
6087         bp->dsb_sp_prod = BNX2X_SP_DSB_INDEX;
6088         bp->spq_prod_bd = bp->spq;
6089         bp->spq_last_bd = bp->spq_prod_bd + MAX_SP_DESC_CNT;
6090 }
6091
6092 static void bnx2x_init_eq_ring(struct bnx2x *bp)
6093 {
6094         int i;
6095         for (i = 1; i <= NUM_EQ_PAGES; i++) {
6096                 union event_ring_elem *elem =
6097                         &bp->eq_ring[EQ_DESC_CNT_PAGE * i - 1];
6098
6099                 elem->next_page.addr.hi =
6100                         cpu_to_le32(U64_HI(bp->eq_mapping +
6101                                    BCM_PAGE_SIZE * (i % NUM_EQ_PAGES)));
6102                 elem->next_page.addr.lo =
6103                         cpu_to_le32(U64_LO(bp->eq_mapping +
6104                                    BCM_PAGE_SIZE*(i % NUM_EQ_PAGES)));
6105         }
6106         bp->eq_cons = 0;
6107         bp->eq_prod = NUM_EQ_DESC;
6108         bp->eq_cons_sb = BNX2X_EQ_INDEX;
6109         /* we want a warning message before it gets wrought... */
6110         atomic_set(&bp->eq_spq_left,
6111                 min_t(int, MAX_SP_DESC_CNT - MAX_SPQ_PENDING, NUM_EQ_DESC) - 1);
6112 }
6113
6114 /* called with netif_addr_lock_bh() */
6115 static int bnx2x_set_q_rx_mode(struct bnx2x *bp, u8 cl_id,
6116                                unsigned long rx_mode_flags,
6117                                unsigned long rx_accept_flags,
6118                                unsigned long tx_accept_flags,
6119                                unsigned long ramrod_flags)
6120 {
6121         struct bnx2x_rx_mode_ramrod_params ramrod_param;
6122         int rc;
6123
6124         memset(&ramrod_param, 0, sizeof(ramrod_param));
6125
6126         /* Prepare ramrod parameters */
6127         ramrod_param.cid = 0;
6128         ramrod_param.cl_id = cl_id;
6129         ramrod_param.rx_mode_obj = &bp->rx_mode_obj;
6130         ramrod_param.func_id = BP_FUNC(bp);
6131
6132         ramrod_param.pstate = &bp->sp_state;
6133         ramrod_param.state = BNX2X_FILTER_RX_MODE_PENDING;
6134
6135         ramrod_param.rdata = bnx2x_sp(bp, rx_mode_rdata);
6136         ramrod_param.rdata_mapping = bnx2x_sp_mapping(bp, rx_mode_rdata);
6137
6138         set_bit(BNX2X_FILTER_RX_MODE_PENDING, &bp->sp_state);
6139
6140         ramrod_param.ramrod_flags = ramrod_flags;
6141         ramrod_param.rx_mode_flags = rx_mode_flags;
6142
6143         ramrod_param.rx_accept_flags = rx_accept_flags;
6144         ramrod_param.tx_accept_flags = tx_accept_flags;
6145
6146         rc = bnx2x_config_rx_mode(bp, &ramrod_param);
6147         if (rc < 0) {
6148                 BNX2X_ERR("Set rx_mode %d failed\n", bp->rx_mode);
6149                 return rc;
6150         }
6151
6152         return 0;
6153 }
6154
6155 static int bnx2x_fill_accept_flags(struct bnx2x *bp, u32 rx_mode,
6156                                    unsigned long *rx_accept_flags,
6157                                    unsigned long *tx_accept_flags)
6158 {
6159         /* Clear the flags first */
6160         *rx_accept_flags = 0;
6161         *tx_accept_flags = 0;
6162
6163         switch (rx_mode) {
6164         case BNX2X_RX_MODE_NONE:
6165                 /*
6166                  * 'drop all' supersedes any accept flags that may have been
6167                  * passed to the function.
6168                  */
6169                 break;
6170         case BNX2X_RX_MODE_NORMAL:
6171                 __set_bit(BNX2X_ACCEPT_UNICAST, rx_accept_flags);
6172                 __set_bit(BNX2X_ACCEPT_MULTICAST, rx_accept_flags);
6173                 __set_bit(BNX2X_ACCEPT_BROADCAST, rx_accept_flags);
6174
6175                 /* internal switching mode */
6176                 __set_bit(BNX2X_ACCEPT_UNICAST, tx_accept_flags);
6177                 __set_bit(BNX2X_ACCEPT_MULTICAST, tx_accept_flags);
6178                 __set_bit(BNX2X_ACCEPT_BROADCAST, tx_accept_flags);
6179
6180                 break;
6181         case BNX2X_RX_MODE_ALLMULTI:
6182                 __set_bit(BNX2X_ACCEPT_UNICAST, rx_accept_flags);
6183                 __set_bit(BNX2X_ACCEPT_ALL_MULTICAST, rx_accept_flags);
6184                 __set_bit(BNX2X_ACCEPT_BROADCAST, rx_accept_flags);
6185
6186                 /* internal switching mode */
6187                 __set_bit(BNX2X_ACCEPT_UNICAST, tx_accept_flags);
6188                 __set_bit(BNX2X_ACCEPT_ALL_MULTICAST, tx_accept_flags);
6189                 __set_bit(BNX2X_ACCEPT_BROADCAST, tx_accept_flags);
6190
6191                 break;
6192         case BNX2X_RX_MODE_PROMISC:
6193                 /* According to definition of SI mode, iface in promisc mode
6194                  * should receive matched and unmatched (in resolution of port)
6195                  * unicast packets.
6196                  */
6197                 __set_bit(BNX2X_ACCEPT_UNMATCHED, rx_accept_flags);
6198                 __set_bit(BNX2X_ACCEPT_UNICAST, rx_accept_flags);
6199                 __set_bit(BNX2X_ACCEPT_ALL_MULTICAST, rx_accept_flags);
6200                 __set_bit(BNX2X_ACCEPT_BROADCAST, rx_accept_flags);
6201
6202                 /* internal switching mode */
6203                 __set_bit(BNX2X_ACCEPT_ALL_MULTICAST, tx_accept_flags);
6204                 __set_bit(BNX2X_ACCEPT_BROADCAST, tx_accept_flags);
6205
6206                 if (IS_MF_SI(bp))
6207                         __set_bit(BNX2X_ACCEPT_ALL_UNICAST, tx_accept_flags);
6208                 else
6209                         __set_bit(BNX2X_ACCEPT_UNICAST, tx_accept_flags);
6210
6211                 break;
6212         default:
6213                 BNX2X_ERR("Unknown rx_mode: %d\n", rx_mode);
6214                 return -EINVAL;
6215         }
6216
6217         /* Set ACCEPT_ANY_VLAN as we do not enable filtering by VLAN */
6218         if (rx_mode != BNX2X_RX_MODE_NONE) {
6219                 __set_bit(BNX2X_ACCEPT_ANY_VLAN, rx_accept_flags);
6220                 __set_bit(BNX2X_ACCEPT_ANY_VLAN, tx_accept_flags);
6221         }
6222
6223         return 0;
6224 }
6225
6226 /* called with netif_addr_lock_bh() */
6227 static int bnx2x_set_storm_rx_mode(struct bnx2x *bp)
6228 {
6229         unsigned long rx_mode_flags = 0, ramrod_flags = 0;
6230         unsigned long rx_accept_flags = 0, tx_accept_flags = 0;
6231         int rc;
6232
6233         if (!NO_FCOE(bp))
6234                 /* Configure rx_mode of FCoE Queue */
6235                 __set_bit(BNX2X_RX_MODE_FCOE_ETH, &rx_mode_flags);
6236
6237         rc = bnx2x_fill_accept_flags(bp, bp->rx_mode, &rx_accept_flags,
6238                                      &tx_accept_flags);
6239         if (rc)
6240                 return rc;
6241
6242         __set_bit(RAMROD_RX, &ramrod_flags);
6243         __set_bit(RAMROD_TX, &ramrod_flags);
6244
6245         return bnx2x_set_q_rx_mode(bp, bp->fp->cl_id, rx_mode_flags,
6246                                    rx_accept_flags, tx_accept_flags,
6247                                    ramrod_flags);
6248 }
6249
6250 static void bnx2x_init_internal_common(struct bnx2x *bp)
6251 {
6252         int i;
6253
6254         /* Zero this manually as its initialization is
6255            currently missing in the initTool */
6256         for (i = 0; i < (USTORM_AGG_DATA_SIZE >> 2); i++)
6257                 REG_WR(bp, BAR_USTRORM_INTMEM +
6258                        USTORM_AGG_DATA_OFFSET + i * 4, 0);
6259         if (!CHIP_IS_E1x(bp)) {
6260                 REG_WR8(bp, BAR_CSTRORM_INTMEM + CSTORM_IGU_MODE_OFFSET,
6261                         CHIP_INT_MODE_IS_BC(bp) ?
6262                         HC_IGU_BC_MODE : HC_IGU_NBC_MODE);
6263         }
6264 }
6265
6266 static void bnx2x_init_internal(struct bnx2x *bp, u32 load_code)
6267 {
6268         switch (load_code) {
6269         case FW_MSG_CODE_DRV_LOAD_COMMON:
6270         case FW_MSG_CODE_DRV_LOAD_COMMON_CHIP:
6271                 bnx2x_init_internal_common(bp);
6272                 /* no break */
6273
6274         case FW_MSG_CODE_DRV_LOAD_PORT:
6275                 /* nothing to do */
6276                 /* no break */
6277
6278         case FW_MSG_CODE_DRV_LOAD_FUNCTION:
6279                 /* internal memory per function is
6280                    initialized inside bnx2x_pf_init */
6281                 break;
6282
6283         default:
6284                 BNX2X_ERR("Unknown load_code (0x%x) from MCP\n", load_code);
6285                 break;
6286         }
6287 }
6288
6289 static inline u8 bnx2x_fp_igu_sb_id(struct bnx2x_fastpath *fp)
6290 {
6291         return fp->bp->igu_base_sb + fp->index + CNIC_SUPPORT(fp->bp);
6292 }
6293
6294 static inline u8 bnx2x_fp_fw_sb_id(struct bnx2x_fastpath *fp)
6295 {
6296         return fp->bp->base_fw_ndsb + fp->index + CNIC_SUPPORT(fp->bp);
6297 }
6298
6299 static u8 bnx2x_fp_cl_id(struct bnx2x_fastpath *fp)
6300 {
6301         if (CHIP_IS_E1x(fp->bp))
6302                 return BP_L_ID(fp->bp) + fp->index;
6303         else    /* We want Client ID to be the same as IGU SB ID for 57712 */
6304                 return bnx2x_fp_igu_sb_id(fp);
6305 }
6306
6307 static void bnx2x_init_eth_fp(struct bnx2x *bp, int fp_idx)
6308 {
6309         struct bnx2x_fastpath *fp = &bp->fp[fp_idx];
6310         u8 cos;
6311         unsigned long q_type = 0;
6312         u32 cids[BNX2X_MULTI_TX_COS] = { 0 };
6313         fp->rx_queue = fp_idx;
6314         fp->cid = fp_idx;
6315         fp->cl_id = bnx2x_fp_cl_id(fp);
6316         fp->fw_sb_id = bnx2x_fp_fw_sb_id(fp);
6317         fp->igu_sb_id = bnx2x_fp_igu_sb_id(fp);
6318         /* qZone id equals to FW (per path) client id */
6319         fp->cl_qzone_id  = bnx2x_fp_qzone_id(fp);
6320
6321         /* init shortcut */
6322         fp->ustorm_rx_prods_offset = bnx2x_rx_ustorm_prods_offset(fp);
6323
6324         /* Setup SB indices */
6325         fp->rx_cons_sb = BNX2X_RX_SB_INDEX;
6326
6327         /* Configure Queue State object */
6328         __set_bit(BNX2X_Q_TYPE_HAS_RX, &q_type);
6329         __set_bit(BNX2X_Q_TYPE_HAS_TX, &q_type);
6330
6331         BUG_ON(fp->max_cos > BNX2X_MULTI_TX_COS);
6332
6333         /* init tx data */
6334         for_each_cos_in_tx_queue(fp, cos) {
6335                 bnx2x_init_txdata(bp, fp->txdata_ptr[cos],
6336                                   CID_COS_TO_TX_ONLY_CID(fp->cid, cos, bp),
6337                                   FP_COS_TO_TXQ(fp, cos, bp),
6338                                   BNX2X_TX_SB_INDEX_BASE + cos, fp);
6339                 cids[cos] = fp->txdata_ptr[cos]->cid;
6340         }
6341
6342         /* nothing more for vf to do here */
6343         if (IS_VF(bp))
6344                 return;
6345
6346         bnx2x_init_sb(bp, fp->status_blk_mapping, BNX2X_VF_ID_INVALID, false,
6347                       fp->fw_sb_id, fp->igu_sb_id);
6348         bnx2x_update_fpsb_idx(fp);
6349         bnx2x_init_queue_obj(bp, &bnx2x_sp_obj(bp, fp).q_obj, fp->cl_id, cids,
6350                              fp->max_cos, BP_FUNC(bp), bnx2x_sp(bp, q_rdata),
6351                              bnx2x_sp_mapping(bp, q_rdata), q_type);
6352
6353         /**
6354          * Configure classification DBs: Always enable Tx switching
6355          */
6356         bnx2x_init_vlan_mac_fp_objs(fp, BNX2X_OBJ_TYPE_RX_TX);
6357
6358         DP(NETIF_MSG_IFUP,
6359            "queue[%d]:  bnx2x_init_sb(%p,%p)  cl_id %d  fw_sb %d  igu_sb %d\n",
6360            fp_idx, bp, fp->status_blk.e2_sb, fp->cl_id, fp->fw_sb_id,
6361            fp->igu_sb_id);
6362 }
6363
6364 static void bnx2x_init_tx_ring_one(struct bnx2x_fp_txdata *txdata)
6365 {
6366         int i;
6367
6368         for (i = 1; i <= NUM_TX_RINGS; i++) {
6369                 struct eth_tx_next_bd *tx_next_bd =
6370                         &txdata->tx_desc_ring[TX_DESC_CNT * i - 1].next_bd;
6371
6372                 tx_next_bd->addr_hi =
6373                         cpu_to_le32(U64_HI(txdata->tx_desc_mapping +
6374                                     BCM_PAGE_SIZE*(i % NUM_TX_RINGS)));
6375                 tx_next_bd->addr_lo =
6376                         cpu_to_le32(U64_LO(txdata->tx_desc_mapping +
6377                                     BCM_PAGE_SIZE*(i % NUM_TX_RINGS)));
6378         }
6379
6380         *txdata->tx_cons_sb = cpu_to_le16(0);
6381
6382         SET_FLAG(txdata->tx_db.data.header.header, DOORBELL_HDR_DB_TYPE, 1);
6383         txdata->tx_db.data.zero_fill1 = 0;
6384         txdata->tx_db.data.prod = 0;
6385
6386         txdata->tx_pkt_prod = 0;
6387         txdata->tx_pkt_cons = 0;
6388         txdata->tx_bd_prod = 0;
6389         txdata->tx_bd_cons = 0;
6390         txdata->tx_pkt = 0;
6391 }
6392
6393 static void bnx2x_init_tx_rings_cnic(struct bnx2x *bp)
6394 {
6395         int i;
6396
6397         for_each_tx_queue_cnic(bp, i)
6398                 bnx2x_init_tx_ring_one(bp->fp[i].txdata_ptr[0]);
6399 }
6400
6401 static void bnx2x_init_tx_rings(struct bnx2x *bp)
6402 {
6403         int i;
6404         u8 cos;
6405
6406         for_each_eth_queue(bp, i)
6407                 for_each_cos_in_tx_queue(&bp->fp[i], cos)
6408                         bnx2x_init_tx_ring_one(bp->fp[i].txdata_ptr[cos]);
6409 }
6410
6411 static void bnx2x_init_fcoe_fp(struct bnx2x *bp)
6412 {
6413         struct bnx2x_fastpath *fp = bnx2x_fcoe_fp(bp);
6414         unsigned long q_type = 0;
6415
6416         bnx2x_fcoe(bp, rx_queue) = BNX2X_NUM_ETH_QUEUES(bp);
6417         bnx2x_fcoe(bp, cl_id) = bnx2x_cnic_eth_cl_id(bp,
6418                                                      BNX2X_FCOE_ETH_CL_ID_IDX);
6419         bnx2x_fcoe(bp, cid) = BNX2X_FCOE_ETH_CID(bp);
6420         bnx2x_fcoe(bp, fw_sb_id) = DEF_SB_ID;
6421         bnx2x_fcoe(bp, igu_sb_id) = bp->igu_dsb_id;
6422         bnx2x_fcoe(bp, rx_cons_sb) = BNX2X_FCOE_L2_RX_INDEX;
6423         bnx2x_init_txdata(bp, bnx2x_fcoe(bp, txdata_ptr[0]),
6424                           fp->cid, FCOE_TXQ_IDX(bp), BNX2X_FCOE_L2_TX_INDEX,
6425                           fp);
6426
6427         DP(NETIF_MSG_IFUP, "created fcoe tx data (fp index %d)\n", fp->index);
6428
6429         /* qZone id equals to FW (per path) client id */
6430         bnx2x_fcoe(bp, cl_qzone_id) = bnx2x_fp_qzone_id(fp);
6431         /* init shortcut */
6432         bnx2x_fcoe(bp, ustorm_rx_prods_offset) =
6433                 bnx2x_rx_ustorm_prods_offset(fp);
6434
6435         /* Configure Queue State object */
6436         __set_bit(BNX2X_Q_TYPE_HAS_RX, &q_type);
6437         __set_bit(BNX2X_Q_TYPE_HAS_TX, &q_type);
6438
6439         /* No multi-CoS for FCoE L2 client */
6440         BUG_ON(fp->max_cos != 1);
6441
6442         bnx2x_init_queue_obj(bp, &bnx2x_sp_obj(bp, fp).q_obj, fp->cl_id,
6443                              &fp->cid, 1, BP_FUNC(bp), bnx2x_sp(bp, q_rdata),
6444                              bnx2x_sp_mapping(bp, q_rdata), q_type);
6445
6446         DP(NETIF_MSG_IFUP,
6447            "queue[%d]: bnx2x_init_sb(%p,%p) cl_id %d fw_sb %d igu_sb %d\n",
6448            fp->index, bp, fp->status_blk.e2_sb, fp->cl_id, fp->fw_sb_id,
6449            fp->igu_sb_id);
6450 }
6451
6452 void bnx2x_nic_init_cnic(struct bnx2x *bp)
6453 {
6454         if (!NO_FCOE(bp))
6455                 bnx2x_init_fcoe_fp(bp);
6456
6457         bnx2x_init_sb(bp, bp->cnic_sb_mapping,
6458                       BNX2X_VF_ID_INVALID, false,
6459                       bnx2x_cnic_fw_sb_id(bp), bnx2x_cnic_igu_sb_id(bp));
6460
6461         /* ensure status block indices were read */
6462         rmb();
6463         bnx2x_init_rx_rings_cnic(bp);
6464         bnx2x_init_tx_rings_cnic(bp);
6465
6466         /* flush all */
6467         mb();
6468         mmiowb();
6469 }
6470
6471 void bnx2x_pre_irq_nic_init(struct bnx2x *bp)
6472 {
6473         int i;
6474
6475         /* Setup NIC internals and enable interrupts */
6476         for_each_eth_queue(bp, i)
6477                 bnx2x_init_eth_fp(bp, i);
6478
6479         /* ensure status block indices were read */
6480         rmb();
6481         bnx2x_init_rx_rings(bp);
6482         bnx2x_init_tx_rings(bp);
6483
6484         if (IS_PF(bp)) {
6485                 /* Initialize MOD_ABS interrupts */
6486                 bnx2x_init_mod_abs_int(bp, &bp->link_vars, bp->common.chip_id,
6487                                        bp->common.shmem_base,
6488                                        bp->common.shmem2_base, BP_PORT(bp));
6489
6490                 /* initialize the default status block and sp ring */
6491                 bnx2x_init_def_sb(bp);
6492                 bnx2x_update_dsb_idx(bp);
6493                 bnx2x_init_sp_ring(bp);
6494         } else {
6495                 bnx2x_memset_stats(bp);
6496         }
6497 }
6498
6499 void bnx2x_post_irq_nic_init(struct bnx2x *bp, u32 load_code)
6500 {
6501         bnx2x_init_eq_ring(bp);
6502         bnx2x_init_internal(bp, load_code);
6503         bnx2x_pf_init(bp);
6504         bnx2x_stats_init(bp);
6505
6506         /* flush all before enabling interrupts */
6507         mb();
6508         mmiowb();
6509
6510         bnx2x_int_enable(bp);
6511
6512         /* Check for SPIO5 */
6513         bnx2x_attn_int_deasserted0(bp,
6514                 REG_RD(bp, MISC_REG_AEU_AFTER_INVERT_1_FUNC_0 + BP_PORT(bp)*4) &
6515                                    AEU_INPUTS_ATTN_BITS_SPIO5);
6516 }
6517
6518 /* gzip service functions */
6519 static int bnx2x_gunzip_init(struct bnx2x *bp)
6520 {
6521         bp->gunzip_buf = dma_alloc_coherent(&bp->pdev->dev, FW_BUF_SIZE,
6522                                             &bp->gunzip_mapping, GFP_KERNEL);
6523         if (bp->gunzip_buf  == NULL)
6524                 goto gunzip_nomem1;
6525
6526         bp->strm = kmalloc(sizeof(*bp->strm), GFP_KERNEL);
6527         if (bp->strm  == NULL)
6528                 goto gunzip_nomem2;
6529
6530         bp->strm->workspace = vmalloc(zlib_inflate_workspacesize());
6531         if (bp->strm->workspace == NULL)
6532                 goto gunzip_nomem3;
6533
6534         return 0;
6535
6536 gunzip_nomem3:
6537         kfree(bp->strm);
6538         bp->strm = NULL;
6539
6540 gunzip_nomem2:
6541         dma_free_coherent(&bp->pdev->dev, FW_BUF_SIZE, bp->gunzip_buf,
6542                           bp->gunzip_mapping);
6543         bp->gunzip_buf = NULL;
6544
6545 gunzip_nomem1:
6546         BNX2X_ERR("Cannot allocate firmware buffer for un-compression\n");
6547         return -ENOMEM;
6548 }
6549
6550 static void bnx2x_gunzip_end(struct bnx2x *bp)
6551 {
6552         if (bp->strm) {
6553                 vfree(bp->strm->workspace);
6554                 kfree(bp->strm);
6555                 bp->strm = NULL;
6556         }
6557
6558         if (bp->gunzip_buf) {
6559                 dma_free_coherent(&bp->pdev->dev, FW_BUF_SIZE, bp->gunzip_buf,
6560                                   bp->gunzip_mapping);
6561                 bp->gunzip_buf = NULL;
6562         }
6563 }
6564
6565 static int bnx2x_gunzip(struct bnx2x *bp, const u8 *zbuf, int len)
6566 {
6567         int n, rc;
6568
6569         /* check gzip header */
6570         if ((zbuf[0] != 0x1f) || (zbuf[1] != 0x8b) || (zbuf[2] != Z_DEFLATED)) {
6571                 BNX2X_ERR("Bad gzip header\n");
6572                 return -EINVAL;
6573         }
6574
6575         n = 10;
6576
6577 #define FNAME                           0x8
6578
6579         if (zbuf[3] & FNAME)
6580                 while ((zbuf[n++] != 0) && (n < len));
6581
6582         bp->strm->next_in = (typeof(bp->strm->next_in))zbuf + n;
6583         bp->strm->avail_in = len - n;
6584         bp->strm->next_out = bp->gunzip_buf;
6585         bp->strm->avail_out = FW_BUF_SIZE;
6586
6587         rc = zlib_inflateInit2(bp->strm, -MAX_WBITS);
6588         if (rc != Z_OK)
6589                 return rc;
6590
6591         rc = zlib_inflate(bp->strm, Z_FINISH);
6592         if ((rc != Z_OK) && (rc != Z_STREAM_END))
6593                 netdev_err(bp->dev, "Firmware decompression error: %s\n",
6594                            bp->strm->msg);
6595
6596         bp->gunzip_outlen = (FW_BUF_SIZE - bp->strm->avail_out);
6597         if (bp->gunzip_outlen & 0x3)
6598                 netdev_err(bp->dev,
6599                            "Firmware decompression error: gunzip_outlen (%d) not aligned\n",
6600                                 bp->gunzip_outlen);
6601         bp->gunzip_outlen >>= 2;
6602
6603         zlib_inflateEnd(bp->strm);
6604
6605         if (rc == Z_STREAM_END)
6606                 return 0;
6607
6608         return rc;
6609 }
6610
6611 /* nic load/unload */
6612
6613 /*
6614  * General service functions
6615  */
6616
6617 /* send a NIG loopback debug packet */
6618 static void bnx2x_lb_pckt(struct bnx2x *bp)
6619 {
6620         u32 wb_write[3];
6621
6622         /* Ethernet source and destination addresses */
6623         wb_write[0] = 0x55555555;
6624         wb_write[1] = 0x55555555;
6625         wb_write[2] = 0x20;             /* SOP */
6626         REG_WR_DMAE(bp, NIG_REG_DEBUG_PACKET_LB, wb_write, 3);
6627
6628         /* NON-IP protocol */
6629         wb_write[0] = 0x09000000;
6630         wb_write[1] = 0x55555555;
6631         wb_write[2] = 0x10;             /* EOP, eop_bvalid = 0 */
6632         REG_WR_DMAE(bp, NIG_REG_DEBUG_PACKET_LB, wb_write, 3);
6633 }
6634
6635 /* some of the internal memories
6636  * are not directly readable from the driver
6637  * to test them we send debug packets
6638  */
6639 static int bnx2x_int_mem_test(struct bnx2x *bp)
6640 {
6641         int factor;
6642         int count, i;
6643         u32 val = 0;
6644
6645         if (CHIP_REV_IS_FPGA(bp))
6646                 factor = 120;
6647         else if (CHIP_REV_IS_EMUL(bp))
6648                 factor = 200;
6649         else
6650                 factor = 1;
6651
6652         /* Disable inputs of parser neighbor blocks */
6653         REG_WR(bp, TSDM_REG_ENABLE_IN1, 0x0);
6654         REG_WR(bp, TCM_REG_PRS_IFEN, 0x0);
6655         REG_WR(bp, CFC_REG_DEBUG0, 0x1);
6656         REG_WR(bp, NIG_REG_PRS_REQ_IN_EN, 0x0);
6657
6658         /*  Write 0 to parser credits for CFC search request */
6659         REG_WR(bp, PRS_REG_CFC_SEARCH_INITIAL_CREDIT, 0x0);
6660
6661         /* send Ethernet packet */
6662         bnx2x_lb_pckt(bp);
6663
6664         /* TODO do i reset NIG statistic? */
6665         /* Wait until NIG register shows 1 packet of size 0x10 */
6666         count = 1000 * factor;
6667         while (count) {
6668
6669                 bnx2x_read_dmae(bp, NIG_REG_STAT2_BRB_OCTET, 2);
6670                 val = *bnx2x_sp(bp, wb_data[0]);
6671                 if (val == 0x10)
6672                         break;
6673
6674                 usleep_range(10000, 20000);
6675                 count--;
6676         }
6677         if (val != 0x10) {
6678                 BNX2X_ERR("NIG timeout  val = 0x%x\n", val);
6679                 return -1;
6680         }
6681
6682         /* Wait until PRS register shows 1 packet */
6683         count = 1000 * factor;
6684         while (count) {
6685                 val = REG_RD(bp, PRS_REG_NUM_OF_PACKETS);
6686                 if (val == 1)
6687                         break;
6688
6689                 usleep_range(10000, 20000);
6690                 count--;
6691         }
6692         if (val != 0x1) {
6693                 BNX2X_ERR("PRS timeout val = 0x%x\n", val);
6694                 return -2;
6695         }
6696
6697         /* Reset and init BRB, PRS */
6698         REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_CLEAR, 0x03);
6699         msleep(50);
6700         REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_SET, 0x03);
6701         msleep(50);
6702         bnx2x_init_block(bp, BLOCK_BRB1, PHASE_COMMON);
6703         bnx2x_init_block(bp, BLOCK_PRS, PHASE_COMMON);
6704
6705         DP(NETIF_MSG_HW, "part2\n");
6706
6707         /* Disable inputs of parser neighbor blocks */
6708         REG_WR(bp, TSDM_REG_ENABLE_IN1, 0x0);
6709         REG_WR(bp, TCM_REG_PRS_IFEN, 0x0);
6710         REG_WR(bp, CFC_REG_DEBUG0, 0x1);
6711         REG_WR(bp, NIG_REG_PRS_REQ_IN_EN, 0x0);
6712
6713         /* Write 0 to parser credits for CFC search request */
6714         REG_WR(bp, PRS_REG_CFC_SEARCH_INITIAL_CREDIT, 0x0);
6715
6716         /* send 10 Ethernet packets */
6717         for (i = 0; i < 10; i++)
6718                 bnx2x_lb_pckt(bp);
6719
6720         /* Wait until NIG register shows 10 + 1
6721            packets of size 11*0x10 = 0xb0 */
6722         count = 1000 * factor;
6723         while (count) {
6724
6725                 bnx2x_read_dmae(bp, NIG_REG_STAT2_BRB_OCTET, 2);
6726                 val = *bnx2x_sp(bp, wb_data[0]);
6727                 if (val == 0xb0)
6728                         break;
6729
6730                 usleep_range(10000, 20000);
6731                 count--;
6732         }
6733         if (val != 0xb0) {
6734                 BNX2X_ERR("NIG timeout  val = 0x%x\n", val);
6735                 return -3;
6736         }
6737
6738         /* Wait until PRS register shows 2 packets */
6739         val = REG_RD(bp, PRS_REG_NUM_OF_PACKETS);
6740         if (val != 2)
6741                 BNX2X_ERR("PRS timeout  val = 0x%x\n", val);
6742
6743         /* Write 1 to parser credits for CFC search request */
6744         REG_WR(bp, PRS_REG_CFC_SEARCH_INITIAL_CREDIT, 0x1);
6745
6746         /* Wait until PRS register shows 3 packets */
6747         msleep(10 * factor);
6748         /* Wait until NIG register shows 1 packet of size 0x10 */
6749         val = REG_RD(bp, PRS_REG_NUM_OF_PACKETS);
6750         if (val != 3)
6751                 BNX2X_ERR("PRS timeout  val = 0x%x\n", val);
6752
6753         /* clear NIG EOP FIFO */
6754         for (i = 0; i < 11; i++)
6755                 REG_RD(bp, NIG_REG_INGRESS_EOP_LB_FIFO);
6756         val = REG_RD(bp, NIG_REG_INGRESS_EOP_LB_EMPTY);
6757         if (val != 1) {
6758                 BNX2X_ERR("clear of NIG failed\n");
6759                 return -4;
6760         }
6761
6762         /* Reset and init BRB, PRS, NIG */
6763         REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_CLEAR, 0x03);
6764         msleep(50);
6765         REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_SET, 0x03);
6766         msleep(50);
6767         bnx2x_init_block(bp, BLOCK_BRB1, PHASE_COMMON);
6768         bnx2x_init_block(bp, BLOCK_PRS, PHASE_COMMON);
6769         if (!CNIC_SUPPORT(bp))
6770                 /* set NIC mode */
6771                 REG_WR(bp, PRS_REG_NIC_MODE, 1);
6772
6773         /* Enable inputs of parser neighbor blocks */
6774         REG_WR(bp, TSDM_REG_ENABLE_IN1, 0x7fffffff);
6775         REG_WR(bp, TCM_REG_PRS_IFEN, 0x1);
6776         REG_WR(bp, CFC_REG_DEBUG0, 0x0);
6777         REG_WR(bp, NIG_REG_PRS_REQ_IN_EN, 0x1);
6778
6779         DP(NETIF_MSG_HW, "done\n");
6780
6781         return 0; /* OK */
6782 }
6783
6784 static void bnx2x_enable_blocks_attention(struct bnx2x *bp)
6785 {
6786         u32 val;
6787
6788         REG_WR(bp, PXP_REG_PXP_INT_MASK_0, 0);
6789         if (!CHIP_IS_E1x(bp))
6790                 REG_WR(bp, PXP_REG_PXP_INT_MASK_1, 0x40);
6791         else
6792                 REG_WR(bp, PXP_REG_PXP_INT_MASK_1, 0);
6793         REG_WR(bp, DORQ_REG_DORQ_INT_MASK, 0);
6794         REG_WR(bp, CFC_REG_CFC_INT_MASK, 0);
6795         /*
6796          * mask read length error interrupts in brb for parser
6797          * (parsing unit and 'checksum and crc' unit)
6798          * these errors are legal (PU reads fixed length and CAC can cause
6799          * read length error on truncated packets)
6800          */
6801         REG_WR(bp, BRB1_REG_BRB1_INT_MASK, 0xFC00);
6802         REG_WR(bp, QM_REG_QM_INT_MASK, 0);
6803         REG_WR(bp, TM_REG_TM_INT_MASK, 0);
6804         REG_WR(bp, XSDM_REG_XSDM_INT_MASK_0, 0);
6805         REG_WR(bp, XSDM_REG_XSDM_INT_MASK_1, 0);
6806         REG_WR(bp, XCM_REG_XCM_INT_MASK, 0);
6807 /*      REG_WR(bp, XSEM_REG_XSEM_INT_MASK_0, 0); */
6808 /*      REG_WR(bp, XSEM_REG_XSEM_INT_MASK_1, 0); */
6809         REG_WR(bp, USDM_REG_USDM_INT_MASK_0, 0);
6810         REG_WR(bp, USDM_REG_USDM_INT_MASK_1, 0);
6811         REG_WR(bp, UCM_REG_UCM_INT_MASK, 0);
6812 /*      REG_WR(bp, USEM_REG_USEM_INT_MASK_0, 0); */
6813 /*      REG_WR(bp, USEM_REG_USEM_INT_MASK_1, 0); */
6814         REG_WR(bp, GRCBASE_UPB + PB_REG_PB_INT_MASK, 0);
6815         REG_WR(bp, CSDM_REG_CSDM_INT_MASK_0, 0);
6816         REG_WR(bp, CSDM_REG_CSDM_INT_MASK_1, 0);
6817         REG_WR(bp, CCM_REG_CCM_INT_MASK, 0);
6818 /*      REG_WR(bp, CSEM_REG_CSEM_INT_MASK_0, 0); */
6819 /*      REG_WR(bp, CSEM_REG_CSEM_INT_MASK_1, 0); */
6820
6821         val = PXP2_PXP2_INT_MASK_0_REG_PGL_CPL_AFT  |
6822                 PXP2_PXP2_INT_MASK_0_REG_PGL_CPL_OF |
6823                 PXP2_PXP2_INT_MASK_0_REG_PGL_PCIE_ATTN;
6824         if (!CHIP_IS_E1x(bp))
6825                 val |= PXP2_PXP2_INT_MASK_0_REG_PGL_READ_BLOCKED |
6826                         PXP2_PXP2_INT_MASK_0_REG_PGL_WRITE_BLOCKED;
6827         REG_WR(bp, PXP2_REG_PXP2_INT_MASK_0, val);
6828
6829         REG_WR(bp, TSDM_REG_TSDM_INT_MASK_0, 0);
6830         REG_WR(bp, TSDM_REG_TSDM_INT_MASK_1, 0);
6831         REG_WR(bp, TCM_REG_TCM_INT_MASK, 0);
6832 /*      REG_WR(bp, TSEM_REG_TSEM_INT_MASK_0, 0); */
6833
6834         if (!CHIP_IS_E1x(bp))
6835                 /* enable VFC attentions: bits 11 and 12, bits 31:13 reserved */
6836                 REG_WR(bp, TSEM_REG_TSEM_INT_MASK_1, 0x07ff);
6837
6838         REG_WR(bp, CDU_REG_CDU_INT_MASK, 0);
6839         REG_WR(bp, DMAE_REG_DMAE_INT_MASK, 0);
6840 /*      REG_WR(bp, MISC_REG_MISC_INT_MASK, 0); */
6841         REG_WR(bp, PBF_REG_PBF_INT_MASK, 0x18);         /* bit 3,4 masked */
6842 }
6843
6844 static void bnx2x_reset_common(struct bnx2x *bp)
6845 {
6846         u32 val = 0x1400;
6847
6848         /* reset_common */
6849         REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_CLEAR,
6850                0xd3ffff7f);
6851
6852         if (CHIP_IS_E3(bp)) {
6853                 val |= MISC_REGISTERS_RESET_REG_2_MSTAT0;
6854                 val |= MISC_REGISTERS_RESET_REG_2_MSTAT1;
6855         }
6856
6857         REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR, val);
6858 }
6859
6860 static void bnx2x_setup_dmae(struct bnx2x *bp)
6861 {
6862         bp->dmae_ready = 0;
6863         spin_lock_init(&bp->dmae_lock);
6864 }
6865
6866 static void bnx2x_init_pxp(struct bnx2x *bp)
6867 {
6868         u16 devctl;
6869         int r_order, w_order;
6870
6871         pcie_capability_read_word(bp->pdev, PCI_EXP_DEVCTL, &devctl);
6872         DP(NETIF_MSG_HW, "read 0x%x from devctl\n", devctl);
6873         w_order = ((devctl & PCI_EXP_DEVCTL_PAYLOAD) >> 5);
6874         if (bp->mrrs == -1)
6875                 r_order = ((devctl & PCI_EXP_DEVCTL_READRQ) >> 12);
6876         else {
6877                 DP(NETIF_MSG_HW, "force read order to %d\n", bp->mrrs);
6878                 r_order = bp->mrrs;
6879         }
6880
6881         bnx2x_init_pxp_arb(bp, r_order, w_order);
6882 }
6883
6884 static void bnx2x_setup_fan_failure_detection(struct bnx2x *bp)
6885 {
6886         int is_required;
6887         u32 val;
6888         int port;
6889
6890         if (BP_NOMCP(bp))
6891                 return;
6892
6893         is_required = 0;
6894         val = SHMEM_RD(bp, dev_info.shared_hw_config.config2) &
6895               SHARED_HW_CFG_FAN_FAILURE_MASK;
6896
6897         if (val == SHARED_HW_CFG_FAN_FAILURE_ENABLED)
6898                 is_required = 1;
6899
6900         /*
6901          * The fan failure mechanism is usually related to the PHY type since
6902          * the power consumption of the board is affected by the PHY. Currently,
6903          * fan is required for most designs with SFX7101, BCM8727 and BCM8481.
6904          */
6905         else if (val == SHARED_HW_CFG_FAN_FAILURE_PHY_TYPE)
6906                 for (port = PORT_0; port < PORT_MAX; port++) {
6907                         is_required |=
6908                                 bnx2x_fan_failure_det_req(
6909                                         bp,
6910                                         bp->common.shmem_base,
6911                                         bp->common.shmem2_base,
6912                                         port);
6913                 }
6914
6915         DP(NETIF_MSG_HW, "fan detection setting: %d\n", is_required);
6916
6917         if (is_required == 0)
6918                 return;
6919
6920         /* Fan failure is indicated by SPIO 5 */
6921         bnx2x_set_spio(bp, MISC_SPIO_SPIO5, MISC_SPIO_INPUT_HI_Z);
6922
6923         /* set to active low mode */
6924         val = REG_RD(bp, MISC_REG_SPIO_INT);
6925         val |= (MISC_SPIO_SPIO5 << MISC_SPIO_INT_OLD_SET_POS);
6926         REG_WR(bp, MISC_REG_SPIO_INT, val);
6927
6928         /* enable interrupt to signal the IGU */
6929         val = REG_RD(bp, MISC_REG_SPIO_EVENT_EN);
6930         val |= MISC_SPIO_SPIO5;
6931         REG_WR(bp, MISC_REG_SPIO_EVENT_EN, val);
6932 }
6933
6934 void bnx2x_pf_disable(struct bnx2x *bp)
6935 {
6936         u32 val = REG_RD(bp, IGU_REG_PF_CONFIGURATION);
6937         val &= ~IGU_PF_CONF_FUNC_EN;
6938
6939         REG_WR(bp, IGU_REG_PF_CONFIGURATION, val);
6940         REG_WR(bp, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, 0);
6941         REG_WR(bp, CFC_REG_WEAK_ENABLE_PF, 0);
6942 }
6943
6944 static void bnx2x__common_init_phy(struct bnx2x *bp)
6945 {
6946         u32 shmem_base[2], shmem2_base[2];
6947         /* Avoid common init in case MFW supports LFA */
6948         if (SHMEM2_RD(bp, size) >
6949             (u32)offsetof(struct shmem2_region, lfa_host_addr[BP_PORT(bp)]))
6950                 return;
6951         shmem_base[0] =  bp->common.shmem_base;
6952         shmem2_base[0] = bp->common.shmem2_base;
6953         if (!CHIP_IS_E1x(bp)) {
6954                 shmem_base[1] =
6955                         SHMEM2_RD(bp, other_shmem_base_addr);
6956                 shmem2_base[1] =
6957                         SHMEM2_RD(bp, other_shmem2_base_addr);
6958         }
6959         bnx2x_acquire_phy_lock(bp);
6960         bnx2x_common_init_phy(bp, shmem_base, shmem2_base,
6961                               bp->common.chip_id);
6962         bnx2x_release_phy_lock(bp);
6963 }
6964
6965 static void bnx2x_config_endianity(struct bnx2x *bp, u32 val)
6966 {
6967         REG_WR(bp, PXP2_REG_RQ_QM_ENDIAN_M, val);
6968         REG_WR(bp, PXP2_REG_RQ_TM_ENDIAN_M, val);
6969         REG_WR(bp, PXP2_REG_RQ_SRC_ENDIAN_M, val);
6970         REG_WR(bp, PXP2_REG_RQ_CDU_ENDIAN_M, val);
6971         REG_WR(bp, PXP2_REG_RQ_DBG_ENDIAN_M, val);
6972
6973         /* make sure this value is 0 */
6974         REG_WR(bp, PXP2_REG_RQ_HC_ENDIAN_M, 0);
6975
6976         REG_WR(bp, PXP2_REG_RD_QM_SWAP_MODE, val);
6977         REG_WR(bp, PXP2_REG_RD_TM_SWAP_MODE, val);
6978         REG_WR(bp, PXP2_REG_RD_SRC_SWAP_MODE, val);
6979         REG_WR(bp, PXP2_REG_RD_CDURD_SWAP_MODE, val);
6980 }
6981
6982 static void bnx2x_set_endianity(struct bnx2x *bp)
6983 {
6984 #ifdef __BIG_ENDIAN
6985         bnx2x_config_endianity(bp, 1);
6986 #else
6987         bnx2x_config_endianity(bp, 0);
6988 #endif
6989 }
6990
6991 static void bnx2x_reset_endianity(struct bnx2x *bp)
6992 {
6993         bnx2x_config_endianity(bp, 0);
6994 }
6995
6996 /**
6997  * bnx2x_init_hw_common - initialize the HW at the COMMON phase.
6998  *
6999  * @bp:         driver handle
7000  */
7001 static int bnx2x_init_hw_common(struct bnx2x *bp)
7002 {
7003         u32 val;
7004
7005         DP(NETIF_MSG_HW, "starting common init  func %d\n", BP_ABS_FUNC(bp));
7006
7007         /*
7008          * take the RESET lock to protect undi_unload flow from accessing
7009          * registers while we're resetting the chip
7010          */
7011         bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_RESET);
7012
7013         bnx2x_reset_common(bp);
7014         REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_SET, 0xffffffff);
7015
7016         val = 0xfffc;
7017         if (CHIP_IS_E3(bp)) {
7018                 val |= MISC_REGISTERS_RESET_REG_2_MSTAT0;
7019                 val |= MISC_REGISTERS_RESET_REG_2_MSTAT1;
7020         }
7021         REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_SET, val);
7022
7023         bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_RESET);
7024
7025         bnx2x_init_block(bp, BLOCK_MISC, PHASE_COMMON);
7026
7027         if (!CHIP_IS_E1x(bp)) {
7028                 u8 abs_func_id;
7029
7030                 /**
7031                  * 4-port mode or 2-port mode we need to turn of master-enable
7032                  * for everyone, after that, turn it back on for self.
7033                  * so, we disregard multi-function or not, and always disable
7034                  * for all functions on the given path, this means 0,2,4,6 for
7035                  * path 0 and 1,3,5,7 for path 1
7036                  */
7037                 for (abs_func_id = BP_PATH(bp);
7038                      abs_func_id < E2_FUNC_MAX*2; abs_func_id += 2) {
7039                         if (abs_func_id == BP_ABS_FUNC(bp)) {
7040                                 REG_WR(bp,
7041                                     PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER,
7042                                     1);
7043                                 continue;
7044                         }
7045
7046                         bnx2x_pretend_func(bp, abs_func_id);
7047                         /* clear pf enable */
7048                         bnx2x_pf_disable(bp);
7049                         bnx2x_pretend_func(bp, BP_ABS_FUNC(bp));
7050                 }
7051         }
7052
7053         bnx2x_init_block(bp, BLOCK_PXP, PHASE_COMMON);
7054         if (CHIP_IS_E1(bp)) {
7055                 /* enable HW interrupt from PXP on USDM overflow
7056                    bit 16 on INT_MASK_0 */
7057                 REG_WR(bp, PXP_REG_PXP_INT_MASK_0, 0);
7058         }
7059
7060         bnx2x_init_block(bp, BLOCK_PXP2, PHASE_COMMON);
7061         bnx2x_init_pxp(bp);
7062         bnx2x_set_endianity(bp);
7063         bnx2x_ilt_init_page_size(bp, INITOP_SET);
7064
7065         if (CHIP_REV_IS_FPGA(bp) && CHIP_IS_E1H(bp))
7066                 REG_WR(bp, PXP2_REG_PGL_TAGS_LIMIT, 0x1);
7067
7068         /* let the HW do it's magic ... */
7069         msleep(100);
7070         /* finish PXP init */
7071         val = REG_RD(bp, PXP2_REG_RQ_CFG_DONE);
7072         if (val != 1) {
7073                 BNX2X_ERR("PXP2 CFG failed\n");
7074                 return -EBUSY;
7075         }
7076         val = REG_RD(bp, PXP2_REG_RD_INIT_DONE);
7077         if (val != 1) {
7078                 BNX2X_ERR("PXP2 RD_INIT failed\n");
7079                 return -EBUSY;
7080         }
7081
7082         /* Timers bug workaround E2 only. We need to set the entire ILT to
7083          * have entries with value "0" and valid bit on.
7084          * This needs to be done by the first PF that is loaded in a path
7085          * (i.e. common phase)
7086          */
7087         if (!CHIP_IS_E1x(bp)) {
7088 /* In E2 there is a bug in the timers block that can cause function 6 / 7
7089  * (i.e. vnic3) to start even if it is marked as "scan-off".
7090  * This occurs when a different function (func2,3) is being marked
7091  * as "scan-off". Real-life scenario for example: if a driver is being
7092  * load-unloaded while func6,7 are down. This will cause the timer to access
7093  * the ilt, translate to a logical address and send a request to read/write.
7094  * Since the ilt for the function that is down is not valid, this will cause
7095  * a translation error which is unrecoverable.
7096  * The Workaround is intended to make sure that when this happens nothing fatal
7097  * will occur. The workaround:
7098  *      1.  First PF driver which loads on a path will:
7099  *              a.  After taking the chip out of reset, by using pretend,
7100  *                  it will write "0" to the following registers of
7101  *                  the other vnics.
7102  *                  REG_WR(pdev, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, 0);
7103  *                  REG_WR(pdev, CFC_REG_WEAK_ENABLE_PF,0);
7104  *                  REG_WR(pdev, CFC_REG_STRONG_ENABLE_PF,0);
7105  *                  And for itself it will write '1' to
7106  *                  PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER to enable
7107  *                  dmae-operations (writing to pram for example.)
7108  *                  note: can be done for only function 6,7 but cleaner this
7109  *                        way.
7110  *              b.  Write zero+valid to the entire ILT.
7111  *              c.  Init the first_timers_ilt_entry, last_timers_ilt_entry of
7112  *                  VNIC3 (of that port). The range allocated will be the
7113  *                  entire ILT. This is needed to prevent  ILT range error.
7114  *      2.  Any PF driver load flow:
7115  *              a.  ILT update with the physical addresses of the allocated
7116  *                  logical pages.
7117  *              b.  Wait 20msec. - note that this timeout is needed to make
7118  *                  sure there are no requests in one of the PXP internal
7119  *                  queues with "old" ILT addresses.
7120  *              c.  PF enable in the PGLC.
7121  *              d.  Clear the was_error of the PF in the PGLC. (could have
7122  *                  occurred while driver was down)
7123  *              e.  PF enable in the CFC (WEAK + STRONG)
7124  *              f.  Timers scan enable
7125  *      3.  PF driver unload flow:
7126  *              a.  Clear the Timers scan_en.
7127  *              b.  Polling for scan_on=0 for that PF.
7128  *              c.  Clear the PF enable bit in the PXP.
7129  *              d.  Clear the PF enable in the CFC (WEAK + STRONG)
7130  *              e.  Write zero+valid to all ILT entries (The valid bit must
7131  *                  stay set)
7132  *              f.  If this is VNIC 3 of a port then also init
7133  *                  first_timers_ilt_entry to zero and last_timers_ilt_entry
7134  *                  to the last entry in the ILT.
7135  *
7136  *      Notes:
7137  *      Currently the PF error in the PGLC is non recoverable.
7138  *      In the future the there will be a recovery routine for this error.
7139  *      Currently attention is masked.
7140  *      Having an MCP lock on the load/unload process does not guarantee that
7141  *      there is no Timer disable during Func6/7 enable. This is because the
7142  *      Timers scan is currently being cleared by the MCP on FLR.
7143  *      Step 2.d can be done only for PF6/7 and the driver can also check if
7144  *      there is error before clearing it. But the flow above is simpler and
7145  *      more general.
7146  *      All ILT entries are written by zero+valid and not just PF6/7
7147  *      ILT entries since in the future the ILT entries allocation for
7148  *      PF-s might be dynamic.
7149  */
7150                 struct ilt_client_info ilt_cli;
7151                 struct bnx2x_ilt ilt;
7152                 memset(&ilt_cli, 0, sizeof(struct ilt_client_info));
7153                 memset(&ilt, 0, sizeof(struct bnx2x_ilt));
7154
7155                 /* initialize dummy TM client */
7156                 ilt_cli.start = 0;
7157                 ilt_cli.end = ILT_NUM_PAGE_ENTRIES - 1;
7158                 ilt_cli.client_num = ILT_CLIENT_TM;
7159
7160                 /* Step 1: set zeroes to all ilt page entries with valid bit on
7161                  * Step 2: set the timers first/last ilt entry to point
7162                  * to the entire range to prevent ILT range error for 3rd/4th
7163                  * vnic (this code assumes existence of the vnic)
7164                  *
7165                  * both steps performed by call to bnx2x_ilt_client_init_op()
7166                  * with dummy TM client
7167                  *
7168                  * we must use pretend since PXP2_REG_RQ_##blk##_FIRST_ILT
7169                  * and his brother are split registers
7170                  */
7171                 bnx2x_pretend_func(bp, (BP_PATH(bp) + 6));
7172                 bnx2x_ilt_client_init_op_ilt(bp, &ilt, &ilt_cli, INITOP_CLEAR);
7173                 bnx2x_pretend_func(bp, BP_ABS_FUNC(bp));
7174
7175                 REG_WR(bp, PXP2_REG_RQ_DRAM_ALIGN, BNX2X_PXP_DRAM_ALIGN);
7176                 REG_WR(bp, PXP2_REG_RQ_DRAM_ALIGN_RD, BNX2X_PXP_DRAM_ALIGN);
7177                 REG_WR(bp, PXP2_REG_RQ_DRAM_ALIGN_SEL, 1);
7178         }
7179
7180         REG_WR(bp, PXP2_REG_RQ_DISABLE_INPUTS, 0);
7181         REG_WR(bp, PXP2_REG_RD_DISABLE_INPUTS, 0);
7182
7183         if (!CHIP_IS_E1x(bp)) {
7184                 int factor = CHIP_REV_IS_EMUL(bp) ? 1000 :
7185                                 (CHIP_REV_IS_FPGA(bp) ? 400 : 0);
7186                 bnx2x_init_block(bp, BLOCK_PGLUE_B, PHASE_COMMON);
7187
7188                 bnx2x_init_block(bp, BLOCK_ATC, PHASE_COMMON);
7189
7190                 /* let the HW do it's magic ... */
7191                 do {
7192                         msleep(200);
7193                         val = REG_RD(bp, ATC_REG_ATC_INIT_DONE);
7194                 } while (factor-- && (val != 1));
7195
7196                 if (val != 1) {
7197                         BNX2X_ERR("ATC_INIT failed\n");
7198                         return -EBUSY;
7199                 }
7200         }
7201
7202         bnx2x_init_block(bp, BLOCK_DMAE, PHASE_COMMON);
7203
7204         bnx2x_iov_init_dmae(bp);
7205
7206         /* clean the DMAE memory */
7207         bp->dmae_ready = 1;
7208         bnx2x_init_fill(bp, TSEM_REG_PRAM, 0, 8, 1);
7209
7210         bnx2x_init_block(bp, BLOCK_TCM, PHASE_COMMON);
7211
7212         bnx2x_init_block(bp, BLOCK_UCM, PHASE_COMMON);
7213
7214         bnx2x_init_block(bp, BLOCK_CCM, PHASE_COMMON);
7215
7216         bnx2x_init_block(bp, BLOCK_XCM, PHASE_COMMON);
7217
7218         bnx2x_read_dmae(bp, XSEM_REG_PASSIVE_BUFFER, 3);
7219         bnx2x_read_dmae(bp, CSEM_REG_PASSIVE_BUFFER, 3);
7220         bnx2x_read_dmae(bp, TSEM_REG_PASSIVE_BUFFER, 3);
7221         bnx2x_read_dmae(bp, USEM_REG_PASSIVE_BUFFER, 3);
7222
7223         bnx2x_init_block(bp, BLOCK_QM, PHASE_COMMON);
7224
7225         /* QM queues pointers table */
7226         bnx2x_qm_init_ptr_table(bp, bp->qm_cid_count, INITOP_SET);
7227
7228         /* soft reset pulse */
7229         REG_WR(bp, QM_REG_SOFT_RESET, 1);
7230         REG_WR(bp, QM_REG_SOFT_RESET, 0);
7231
7232         if (CNIC_SUPPORT(bp))
7233                 bnx2x_init_block(bp, BLOCK_TM, PHASE_COMMON);
7234
7235         bnx2x_init_block(bp, BLOCK_DORQ, PHASE_COMMON);
7236
7237         if (!CHIP_REV_IS_SLOW(bp))
7238                 /* enable hw interrupt from doorbell Q */
7239                 REG_WR(bp, DORQ_REG_DORQ_INT_MASK, 0);
7240
7241         bnx2x_init_block(bp, BLOCK_BRB1, PHASE_COMMON);
7242
7243         bnx2x_init_block(bp, BLOCK_PRS, PHASE_COMMON);
7244         REG_WR(bp, PRS_REG_A_PRSU_20, 0xf);
7245
7246         if (!CHIP_IS_E1(bp))
7247                 REG_WR(bp, PRS_REG_E1HOV_MODE, bp->path_has_ovlan);
7248
7249         if (!CHIP_IS_E1x(bp) && !CHIP_IS_E3B0(bp)) {
7250                 if (IS_MF_AFEX(bp)) {
7251                         /* configure that VNTag and VLAN headers must be
7252                          * received in afex mode
7253                          */
7254                         REG_WR(bp, PRS_REG_HDRS_AFTER_BASIC, 0xE);
7255                         REG_WR(bp, PRS_REG_MUST_HAVE_HDRS, 0xA);
7256                         REG_WR(bp, PRS_REG_HDRS_AFTER_TAG_0, 0x6);
7257                         REG_WR(bp, PRS_REG_TAG_ETHERTYPE_0, 0x8926);
7258                         REG_WR(bp, PRS_REG_TAG_LEN_0, 0x4);
7259                 } else {
7260                         /* Bit-map indicating which L2 hdrs may appear
7261                          * after the basic Ethernet header
7262                          */
7263                         REG_WR(bp, PRS_REG_HDRS_AFTER_BASIC,
7264                                bp->path_has_ovlan ? 7 : 6);
7265                 }
7266         }
7267
7268         bnx2x_init_block(bp, BLOCK_TSDM, PHASE_COMMON);
7269         bnx2x_init_block(bp, BLOCK_CSDM, PHASE_COMMON);
7270         bnx2x_init_block(bp, BLOCK_USDM, PHASE_COMMON);
7271         bnx2x_init_block(bp, BLOCK_XSDM, PHASE_COMMON);
7272
7273         if (!CHIP_IS_E1x(bp)) {
7274                 /* reset VFC memories */
7275                 REG_WR(bp, TSEM_REG_FAST_MEMORY + VFC_REG_MEMORIES_RST,
7276                            VFC_MEMORIES_RST_REG_CAM_RST |
7277                            VFC_MEMORIES_RST_REG_RAM_RST);
7278                 REG_WR(bp, XSEM_REG_FAST_MEMORY + VFC_REG_MEMORIES_RST,
7279                            VFC_MEMORIES_RST_REG_CAM_RST |
7280                            VFC_MEMORIES_RST_REG_RAM_RST);
7281
7282                 msleep(20);
7283         }
7284
7285         bnx2x_init_block(bp, BLOCK_TSEM, PHASE_COMMON);
7286         bnx2x_init_block(bp, BLOCK_USEM, PHASE_COMMON);
7287         bnx2x_init_block(bp, BLOCK_CSEM, PHASE_COMMON);
7288         bnx2x_init_block(bp, BLOCK_XSEM, PHASE_COMMON);
7289
7290         /* sync semi rtc */
7291         REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_CLEAR,
7292                0x80000000);
7293         REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_SET,
7294                0x80000000);
7295
7296         bnx2x_init_block(bp, BLOCK_UPB, PHASE_COMMON);
7297         bnx2x_init_block(bp, BLOCK_XPB, PHASE_COMMON);
7298         bnx2x_init_block(bp, BLOCK_PBF, PHASE_COMMON);
7299
7300         if (!CHIP_IS_E1x(bp)) {
7301                 if (IS_MF_AFEX(bp)) {
7302                         /* configure that VNTag and VLAN headers must be
7303                          * sent in afex mode
7304                          */
7305                         REG_WR(bp, PBF_REG_HDRS_AFTER_BASIC, 0xE);
7306                         REG_WR(bp, PBF_REG_MUST_HAVE_HDRS, 0xA);
7307                         REG_WR(bp, PBF_REG_HDRS_AFTER_TAG_0, 0x6);
7308                         REG_WR(bp, PBF_REG_TAG_ETHERTYPE_0, 0x8926);
7309                         REG_WR(bp, PBF_REG_TAG_LEN_0, 0x4);
7310                 } else {
7311                         REG_WR(bp, PBF_REG_HDRS_AFTER_BASIC,
7312                                bp->path_has_ovlan ? 7 : 6);
7313                 }
7314         }
7315
7316         REG_WR(bp, SRC_REG_SOFT_RST, 1);
7317
7318         bnx2x_init_block(bp, BLOCK_SRC, PHASE_COMMON);
7319
7320         if (CNIC_SUPPORT(bp)) {
7321                 REG_WR(bp, SRC_REG_KEYSEARCH_0, 0x63285672);
7322                 REG_WR(bp, SRC_REG_KEYSEARCH_1, 0x24b8f2cc);
7323                 REG_WR(bp, SRC_REG_KEYSEARCH_2, 0x223aef9b);
7324                 REG_WR(bp, SRC_REG_KEYSEARCH_3, 0x26001e3a);
7325                 REG_WR(bp, SRC_REG_KEYSEARCH_4, 0x7ae91116);
7326                 REG_WR(bp, SRC_REG_KEYSEARCH_5, 0x5ce5230b);
7327                 REG_WR(bp, SRC_REG_KEYSEARCH_6, 0x298d8adf);
7328                 REG_WR(bp, SRC_REG_KEYSEARCH_7, 0x6eb0ff09);
7329                 REG_WR(bp, SRC_REG_KEYSEARCH_8, 0x1830f82f);
7330                 REG_WR(bp, SRC_REG_KEYSEARCH_9, 0x01e46be7);
7331         }
7332         REG_WR(bp, SRC_REG_SOFT_RST, 0);
7333
7334         if (sizeof(union cdu_context) != 1024)
7335                 /* we currently assume that a context is 1024 bytes */
7336                 dev_alert(&bp->pdev->dev,
7337                           "please adjust the size of cdu_context(%ld)\n",
7338                           (long)sizeof(union cdu_context));
7339
7340         bnx2x_init_block(bp, BLOCK_CDU, PHASE_COMMON);
7341         val = (4 << 24) + (0 << 12) + 1024;
7342         REG_WR(bp, CDU_REG_CDU_GLOBAL_PARAMS, val);
7343
7344         bnx2x_init_block(bp, BLOCK_CFC, PHASE_COMMON);
7345         REG_WR(bp, CFC_REG_INIT_REG, 0x7FF);
7346         /* enable context validation interrupt from CFC */
7347         REG_WR(bp, CFC_REG_CFC_INT_MASK, 0);
7348
7349         /* set the thresholds to prevent CFC/CDU race */
7350         REG_WR(bp, CFC_REG_DEBUG0, 0x20020000);
7351
7352         bnx2x_init_block(bp, BLOCK_HC, PHASE_COMMON);
7353
7354         if (!CHIP_IS_E1x(bp) && BP_NOMCP(bp))
7355                 REG_WR(bp, IGU_REG_RESET_MEMORIES, 0x36);
7356
7357         bnx2x_init_block(bp, BLOCK_IGU, PHASE_COMMON);
7358         bnx2x_init_block(bp, BLOCK_MISC_AEU, PHASE_COMMON);
7359
7360         /* Reset PCIE errors for debug */
7361         REG_WR(bp, 0x2814, 0xffffffff);
7362         REG_WR(bp, 0x3820, 0xffffffff);
7363
7364         if (!CHIP_IS_E1x(bp)) {
7365                 REG_WR(bp, PCICFG_OFFSET + PXPCS_TL_CONTROL_5,
7366                            (PXPCS_TL_CONTROL_5_ERR_UNSPPORT1 |
7367                                 PXPCS_TL_CONTROL_5_ERR_UNSPPORT));
7368                 REG_WR(bp, PCICFG_OFFSET + PXPCS_TL_FUNC345_STAT,
7369                            (PXPCS_TL_FUNC345_STAT_ERR_UNSPPORT4 |
7370                                 PXPCS_TL_FUNC345_STAT_ERR_UNSPPORT3 |
7371                                 PXPCS_TL_FUNC345_STAT_ERR_UNSPPORT2));
7372                 REG_WR(bp, PCICFG_OFFSET + PXPCS_TL_FUNC678_STAT,
7373                            (PXPCS_TL_FUNC678_STAT_ERR_UNSPPORT7 |
7374                                 PXPCS_TL_FUNC678_STAT_ERR_UNSPPORT6 |
7375                                 PXPCS_TL_FUNC678_STAT_ERR_UNSPPORT5));
7376         }
7377
7378         bnx2x_init_block(bp, BLOCK_NIG, PHASE_COMMON);
7379         if (!CHIP_IS_E1(bp)) {
7380                 /* in E3 this done in per-port section */
7381                 if (!CHIP_IS_E3(bp))
7382                         REG_WR(bp, NIG_REG_LLH_MF_MODE, IS_MF(bp));
7383         }
7384         if (CHIP_IS_E1H(bp))
7385                 /* not applicable for E2 (and above ...) */
7386                 REG_WR(bp, NIG_REG_LLH_E1HOV_MODE, IS_MF_SD(bp));
7387
7388         if (CHIP_REV_IS_SLOW(bp))
7389                 msleep(200);
7390
7391         /* finish CFC init */
7392         val = reg_poll(bp, CFC_REG_LL_INIT_DONE, 1, 100, 10);
7393         if (val != 1) {
7394                 BNX2X_ERR("CFC LL_INIT failed\n");
7395                 return -EBUSY;
7396         }
7397         val = reg_poll(bp, CFC_REG_AC_INIT_DONE, 1, 100, 10);
7398         if (val != 1) {
7399                 BNX2X_ERR("CFC AC_INIT failed\n");
7400                 return -EBUSY;
7401         }
7402         val = reg_poll(bp, CFC_REG_CAM_INIT_DONE, 1, 100, 10);
7403         if (val != 1) {
7404                 BNX2X_ERR("CFC CAM_INIT failed\n");
7405                 return -EBUSY;
7406         }
7407         REG_WR(bp, CFC_REG_DEBUG0, 0);
7408
7409         if (CHIP_IS_E1(bp)) {
7410                 /* read NIG statistic
7411                    to see if this is our first up since powerup */
7412                 bnx2x_read_dmae(bp, NIG_REG_STAT2_BRB_OCTET, 2);
7413                 val = *bnx2x_sp(bp, wb_data[0]);
7414
7415                 /* do internal memory self test */
7416                 if ((val == 0) && bnx2x_int_mem_test(bp)) {
7417                         BNX2X_ERR("internal mem self test failed\n");
7418                         return -EBUSY;
7419                 }
7420         }
7421
7422         bnx2x_setup_fan_failure_detection(bp);
7423
7424         /* clear PXP2 attentions */
7425         REG_RD(bp, PXP2_REG_PXP2_INT_STS_CLR_0);
7426
7427         bnx2x_enable_blocks_attention(bp);
7428         bnx2x_enable_blocks_parity(bp);
7429
7430         if (!BP_NOMCP(bp)) {
7431                 if (CHIP_IS_E1x(bp))
7432                         bnx2x__common_init_phy(bp);
7433         } else
7434                 BNX2X_ERR("Bootcode is missing - can not initialize link\n");
7435
7436         if (SHMEM2_HAS(bp, netproc_fw_ver))
7437                 SHMEM2_WR(bp, netproc_fw_ver, REG_RD(bp, XSEM_REG_PRAM));
7438
7439         return 0;
7440 }
7441
7442 /**
7443  * bnx2x_init_hw_common_chip - init HW at the COMMON_CHIP phase.
7444  *
7445  * @bp:         driver handle
7446  */
7447 static int bnx2x_init_hw_common_chip(struct bnx2x *bp)
7448 {
7449         int rc = bnx2x_init_hw_common(bp);
7450
7451         if (rc)
7452                 return rc;
7453
7454         /* In E2 2-PORT mode, same ext phy is used for the two paths */
7455         if (!BP_NOMCP(bp))
7456                 bnx2x__common_init_phy(bp);
7457
7458         return 0;
7459 }
7460
7461 static int bnx2x_init_hw_port(struct bnx2x *bp)
7462 {
7463         int port = BP_PORT(bp);
7464         int init_phase = port ? PHASE_PORT1 : PHASE_PORT0;
7465         u32 low, high;
7466         u32 val, reg;
7467
7468         DP(NETIF_MSG_HW, "starting port init  port %d\n", port);
7469
7470         REG_WR(bp, NIG_REG_MASK_INTERRUPT_PORT0 + port*4, 0);
7471
7472         bnx2x_init_block(bp, BLOCK_MISC, init_phase);
7473         bnx2x_init_block(bp, BLOCK_PXP, init_phase);
7474         bnx2x_init_block(bp, BLOCK_PXP2, init_phase);
7475
7476         /* Timers bug workaround: disables the pf_master bit in pglue at
7477          * common phase, we need to enable it here before any dmae access are
7478          * attempted. Therefore we manually added the enable-master to the
7479          * port phase (it also happens in the function phase)
7480          */
7481         if (!CHIP_IS_E1x(bp))
7482                 REG_WR(bp, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, 1);
7483
7484         bnx2x_init_block(bp, BLOCK_ATC, init_phase);
7485         bnx2x_init_block(bp, BLOCK_DMAE, init_phase);
7486         bnx2x_init_block(bp, BLOCK_PGLUE_B, init_phase);
7487         bnx2x_init_block(bp, BLOCK_QM, init_phase);
7488
7489         bnx2x_init_block(bp, BLOCK_TCM, init_phase);
7490         bnx2x_init_block(bp, BLOCK_UCM, init_phase);
7491         bnx2x_init_block(bp, BLOCK_CCM, init_phase);
7492         bnx2x_init_block(bp, BLOCK_XCM, init_phase);
7493
7494         /* QM cid (connection) count */
7495         bnx2x_qm_init_cid_count(bp, bp->qm_cid_count, INITOP_SET);
7496
7497         if (CNIC_SUPPORT(bp)) {
7498                 bnx2x_init_block(bp, BLOCK_TM, init_phase);
7499                 REG_WR(bp, TM_REG_LIN0_SCAN_TIME + port*4, 20);
7500                 REG_WR(bp, TM_REG_LIN0_MAX_ACTIVE_CID + port*4, 31);
7501         }
7502
7503         bnx2x_init_block(bp, BLOCK_DORQ, init_phase);
7504
7505         bnx2x_init_block(bp, BLOCK_BRB1, init_phase);
7506
7507         if (CHIP_IS_E1(bp) || CHIP_IS_E1H(bp)) {
7508
7509                 if (IS_MF(bp))
7510                         low = ((bp->flags & ONE_PORT_FLAG) ? 160 : 246);
7511                 else if (bp->dev->mtu > 4096) {
7512                         if (bp->flags & ONE_PORT_FLAG)
7513                                 low = 160;
7514                         else {
7515                                 val = bp->dev->mtu;
7516                                 /* (24*1024 + val*4)/256 */
7517                                 low = 96 + (val/64) +
7518                                                 ((val % 64) ? 1 : 0);
7519                         }
7520                 } else
7521                         low = ((bp->flags & ONE_PORT_FLAG) ? 80 : 160);
7522                 high = low + 56;        /* 14*1024/256 */
7523                 REG_WR(bp, BRB1_REG_PAUSE_LOW_THRESHOLD_0 + port*4, low);
7524                 REG_WR(bp, BRB1_REG_PAUSE_HIGH_THRESHOLD_0 + port*4, high);
7525         }
7526
7527         if (CHIP_MODE_IS_4_PORT(bp))
7528                 REG_WR(bp, (BP_PORT(bp) ?
7529                             BRB1_REG_MAC_GUARANTIED_1 :
7530                             BRB1_REG_MAC_GUARANTIED_0), 40);
7531
7532         bnx2x_init_block(bp, BLOCK_PRS, init_phase);
7533         if (CHIP_IS_E3B0(bp)) {
7534                 if (IS_MF_AFEX(bp)) {
7535                         /* configure headers for AFEX mode */
7536                         REG_WR(bp, BP_PORT(bp) ?
7537                                PRS_REG_HDRS_AFTER_BASIC_PORT_1 :
7538                                PRS_REG_HDRS_AFTER_BASIC_PORT_0, 0xE);
7539                         REG_WR(bp, BP_PORT(bp) ?
7540                                PRS_REG_HDRS_AFTER_TAG_0_PORT_1 :
7541                                PRS_REG_HDRS_AFTER_TAG_0_PORT_0, 0x6);
7542                         REG_WR(bp, BP_PORT(bp) ?
7543                                PRS_REG_MUST_HAVE_HDRS_PORT_1 :
7544                                PRS_REG_MUST_HAVE_HDRS_PORT_0, 0xA);
7545                 } else {
7546                         /* Ovlan exists only if we are in multi-function +
7547                          * switch-dependent mode, in switch-independent there
7548                          * is no ovlan headers
7549                          */
7550                         REG_WR(bp, BP_PORT(bp) ?
7551                                PRS_REG_HDRS_AFTER_BASIC_PORT_1 :
7552                                PRS_REG_HDRS_AFTER_BASIC_PORT_0,
7553                                (bp->path_has_ovlan ? 7 : 6));
7554                 }
7555         }
7556
7557         bnx2x_init_block(bp, BLOCK_TSDM, init_phase);
7558         bnx2x_init_block(bp, BLOCK_CSDM, init_phase);
7559         bnx2x_init_block(bp, BLOCK_USDM, init_phase);
7560         bnx2x_init_block(bp, BLOCK_XSDM, init_phase);
7561
7562         bnx2x_init_block(bp, BLOCK_TSEM, init_phase);
7563         bnx2x_init_block(bp, BLOCK_USEM, init_phase);
7564         bnx2x_init_block(bp, BLOCK_CSEM, init_phase);
7565         bnx2x_init_block(bp, BLOCK_XSEM, init_phase);
7566
7567         bnx2x_init_block(bp, BLOCK_UPB, init_phase);
7568         bnx2x_init_block(bp, BLOCK_XPB, init_phase);
7569
7570         bnx2x_init_block(bp, BLOCK_PBF, init_phase);
7571
7572         if (CHIP_IS_E1x(bp)) {
7573                 /* configure PBF to work without PAUSE mtu 9000 */
7574                 REG_WR(bp, PBF_REG_P0_PAUSE_ENABLE + port*4, 0);
7575
7576                 /* update threshold */
7577                 REG_WR(bp, PBF_REG_P0_ARB_THRSH + port*4, (9040/16));
7578                 /* update init credit */
7579                 REG_WR(bp, PBF_REG_P0_INIT_CRD + port*4, (9040/16) + 553 - 22);
7580
7581                 /* probe changes */
7582                 REG_WR(bp, PBF_REG_INIT_P0 + port*4, 1);
7583                 udelay(50);
7584                 REG_WR(bp, PBF_REG_INIT_P0 + port*4, 0);
7585         }
7586
7587         if (CNIC_SUPPORT(bp))
7588                 bnx2x_init_block(bp, BLOCK_SRC, init_phase);
7589
7590         bnx2x_init_block(bp, BLOCK_CDU, init_phase);
7591         bnx2x_init_block(bp, BLOCK_CFC, init_phase);
7592
7593         if (CHIP_IS_E1(bp)) {
7594                 REG_WR(bp, HC_REG_LEADING_EDGE_0 + port*8, 0);
7595                 REG_WR(bp, HC_REG_TRAILING_EDGE_0 + port*8, 0);
7596         }
7597         bnx2x_init_block(bp, BLOCK_HC, init_phase);
7598
7599         bnx2x_init_block(bp, BLOCK_IGU, init_phase);
7600
7601         bnx2x_init_block(bp, BLOCK_MISC_AEU, init_phase);
7602         /* init aeu_mask_attn_func_0/1:
7603          *  - SF mode: bits 3-7 are masked. Only bits 0-2 are in use
7604          *  - MF mode: bit 3 is masked. Bits 0-2 are in use as in SF
7605          *             bits 4-7 are used for "per vn group attention" */
7606         val = IS_MF(bp) ? 0xF7 : 0x7;
7607         /* Enable DCBX attention for all but E1 */
7608         val |= CHIP_IS_E1(bp) ? 0 : 0x10;
7609         REG_WR(bp, MISC_REG_AEU_MASK_ATTN_FUNC_0 + port*4, val);
7610
7611         /* SCPAD_PARITY should NOT trigger close the gates */
7612         reg = port ? MISC_REG_AEU_ENABLE4_NIG_1 : MISC_REG_AEU_ENABLE4_NIG_0;
7613         REG_WR(bp, reg,
7614                REG_RD(bp, reg) &
7615                ~AEU_INPUTS_ATTN_BITS_MCP_LATCHED_SCPAD_PARITY);
7616
7617         reg = port ? MISC_REG_AEU_ENABLE4_PXP_1 : MISC_REG_AEU_ENABLE4_PXP_0;
7618         REG_WR(bp, reg,
7619                REG_RD(bp, reg) &
7620                ~AEU_INPUTS_ATTN_BITS_MCP_LATCHED_SCPAD_PARITY);
7621
7622         bnx2x_init_block(bp, BLOCK_NIG, init_phase);
7623
7624         if (!CHIP_IS_E1x(bp)) {
7625                 /* Bit-map indicating which L2 hdrs may appear after the
7626                  * basic Ethernet header
7627                  */
7628                 if (IS_MF_AFEX(bp))
7629                         REG_WR(bp, BP_PORT(bp) ?
7630                                NIG_REG_P1_HDRS_AFTER_BASIC :
7631                                NIG_REG_P0_HDRS_AFTER_BASIC, 0xE);
7632                 else
7633                         REG_WR(bp, BP_PORT(bp) ?
7634                                NIG_REG_P1_HDRS_AFTER_BASIC :
7635                                NIG_REG_P0_HDRS_AFTER_BASIC,
7636                                IS_MF_SD(bp) ? 7 : 6);
7637
7638                 if (CHIP_IS_E3(bp))
7639                         REG_WR(bp, BP_PORT(bp) ?
7640                                    NIG_REG_LLH1_MF_MODE :
7641                                    NIG_REG_LLH_MF_MODE, IS_MF(bp));
7642         }
7643         if (!CHIP_IS_E3(bp))
7644                 REG_WR(bp, NIG_REG_XGXS_SERDES0_MODE_SEL + port*4, 1);
7645
7646         if (!CHIP_IS_E1(bp)) {
7647                 /* 0x2 disable mf_ov, 0x1 enable */
7648                 REG_WR(bp, NIG_REG_LLH0_BRB1_DRV_MASK_MF + port*4,
7649                        (IS_MF_SD(bp) ? 0x1 : 0x2));
7650
7651                 if (!CHIP_IS_E1x(bp)) {
7652                         val = 0;
7653                         switch (bp->mf_mode) {
7654                         case MULTI_FUNCTION_SD:
7655                                 val = 1;
7656                                 break;
7657                         case MULTI_FUNCTION_SI:
7658                         case MULTI_FUNCTION_AFEX:
7659                                 val = 2;
7660                                 break;
7661                         }
7662
7663                         REG_WR(bp, (BP_PORT(bp) ? NIG_REG_LLH1_CLS_TYPE :
7664                                                   NIG_REG_LLH0_CLS_TYPE), val);
7665                 }
7666                 {
7667                         REG_WR(bp, NIG_REG_LLFC_ENABLE_0 + port*4, 0);
7668                         REG_WR(bp, NIG_REG_LLFC_OUT_EN_0 + port*4, 0);
7669                         REG_WR(bp, NIG_REG_PAUSE_ENABLE_0 + port*4, 1);
7670                 }
7671         }
7672
7673         /* If SPIO5 is set to generate interrupts, enable it for this port */
7674         val = REG_RD(bp, MISC_REG_SPIO_EVENT_EN);
7675         if (val & MISC_SPIO_SPIO5) {
7676                 u32 reg_addr = (port ? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_0 :
7677                                        MISC_REG_AEU_ENABLE1_FUNC_0_OUT_0);
7678                 val = REG_RD(bp, reg_addr);
7679                 val |= AEU_INPUTS_ATTN_BITS_SPIO5;
7680                 REG_WR(bp, reg_addr, val);
7681         }
7682
7683         return 0;
7684 }
7685
7686 static void bnx2x_ilt_wr(struct bnx2x *bp, u32 index, dma_addr_t addr)
7687 {
7688         int reg;
7689         u32 wb_write[2];
7690
7691         if (CHIP_IS_E1(bp))
7692                 reg = PXP2_REG_RQ_ONCHIP_AT + index*8;
7693         else
7694                 reg = PXP2_REG_RQ_ONCHIP_AT_B0 + index*8;
7695
7696         wb_write[0] = ONCHIP_ADDR1(addr);
7697         wb_write[1] = ONCHIP_ADDR2(addr);
7698         REG_WR_DMAE(bp, reg, wb_write, 2);
7699 }
7700
7701 void bnx2x_igu_clear_sb_gen(struct bnx2x *bp, u8 func, u8 idu_sb_id, bool is_pf)
7702 {
7703         u32 data, ctl, cnt = 100;
7704         u32 igu_addr_data = IGU_REG_COMMAND_REG_32LSB_DATA;
7705         u32 igu_addr_ctl = IGU_REG_COMMAND_REG_CTRL;
7706         u32 igu_addr_ack = IGU_REG_CSTORM_TYPE_0_SB_CLEANUP + (idu_sb_id/32)*4;
7707         u32 sb_bit =  1 << (idu_sb_id%32);
7708         u32 func_encode = func | (is_pf ? 1 : 0) << IGU_FID_ENCODE_IS_PF_SHIFT;
7709         u32 addr_encode = IGU_CMD_E2_PROD_UPD_BASE + idu_sb_id;
7710
7711         /* Not supported in BC mode */
7712         if (CHIP_INT_MODE_IS_BC(bp))
7713                 return;
7714
7715         data = (IGU_USE_REGISTER_cstorm_type_0_sb_cleanup
7716                         << IGU_REGULAR_CLEANUP_TYPE_SHIFT)      |
7717                 IGU_REGULAR_CLEANUP_SET                         |
7718                 IGU_REGULAR_BCLEANUP;
7719
7720         ctl = addr_encode << IGU_CTRL_REG_ADDRESS_SHIFT         |
7721               func_encode << IGU_CTRL_REG_FID_SHIFT             |
7722               IGU_CTRL_CMD_TYPE_WR << IGU_CTRL_REG_TYPE_SHIFT;
7723
7724         DP(NETIF_MSG_HW, "write 0x%08x to IGU(via GRC) addr 0x%x\n",
7725                          data, igu_addr_data);
7726         REG_WR(bp, igu_addr_data, data);
7727         mmiowb();
7728         barrier();
7729         DP(NETIF_MSG_HW, "write 0x%08x to IGU(via GRC) addr 0x%x\n",
7730                           ctl, igu_addr_ctl);
7731         REG_WR(bp, igu_addr_ctl, ctl);
7732         mmiowb();
7733         barrier();
7734
7735         /* wait for clean up to finish */
7736         while (!(REG_RD(bp, igu_addr_ack) & sb_bit) && --cnt)
7737                 msleep(20);
7738
7739         if (!(REG_RD(bp, igu_addr_ack) & sb_bit)) {
7740                 DP(NETIF_MSG_HW,
7741                    "Unable to finish IGU cleanup: idu_sb_id %d offset %d bit %d (cnt %d)\n",
7742                           idu_sb_id, idu_sb_id/32, idu_sb_id%32, cnt);
7743         }
7744 }
7745
7746 static void bnx2x_igu_clear_sb(struct bnx2x *bp, u8 idu_sb_id)
7747 {
7748         bnx2x_igu_clear_sb_gen(bp, BP_FUNC(bp), idu_sb_id, true /*PF*/);
7749 }
7750
7751 static void bnx2x_clear_func_ilt(struct bnx2x *bp, u32 func)
7752 {
7753         u32 i, base = FUNC_ILT_BASE(func);
7754         for (i = base; i < base + ILT_PER_FUNC; i++)
7755                 bnx2x_ilt_wr(bp, i, 0);
7756 }
7757
7758 static void bnx2x_init_searcher(struct bnx2x *bp)
7759 {
7760         int port = BP_PORT(bp);
7761         bnx2x_src_init_t2(bp, bp->t2, bp->t2_mapping, SRC_CONN_NUM);
7762         /* T1 hash bits value determines the T1 number of entries */
7763         REG_WR(bp, SRC_REG_NUMBER_HASH_BITS0 + port*4, SRC_HASH_BITS);
7764 }
7765
7766 static inline int bnx2x_func_switch_update(struct bnx2x *bp, int suspend)
7767 {
7768         int rc;
7769         struct bnx2x_func_state_params func_params = {NULL};
7770         struct bnx2x_func_switch_update_params *switch_update_params =
7771                 &func_params.params.switch_update;
7772
7773         /* Prepare parameters for function state transitions */
7774         __set_bit(RAMROD_COMP_WAIT, &func_params.ramrod_flags);
7775         __set_bit(RAMROD_RETRY, &func_params.ramrod_flags);
7776
7777         func_params.f_obj = &bp->func_obj;
7778         func_params.cmd = BNX2X_F_CMD_SWITCH_UPDATE;
7779
7780         /* Function parameters */
7781         __set_bit(BNX2X_F_UPDATE_TX_SWITCH_SUSPEND_CHNG,
7782                   &switch_update_params->changes);
7783         if (suspend)
7784                 __set_bit(BNX2X_F_UPDATE_TX_SWITCH_SUSPEND,
7785                           &switch_update_params->changes);
7786
7787         rc = bnx2x_func_state_change(bp, &func_params);
7788
7789         return rc;
7790 }
7791
7792 static int bnx2x_reset_nic_mode(struct bnx2x *bp)
7793 {
7794         int rc, i, port = BP_PORT(bp);
7795         int vlan_en = 0, mac_en[NUM_MACS];
7796
7797         /* Close input from network */
7798         if (bp->mf_mode == SINGLE_FUNCTION) {
7799                 bnx2x_set_rx_filter(&bp->link_params, 0);
7800         } else {
7801                 vlan_en = REG_RD(bp, port ? NIG_REG_LLH1_FUNC_EN :
7802                                    NIG_REG_LLH0_FUNC_EN);
7803                 REG_WR(bp, port ? NIG_REG_LLH1_FUNC_EN :
7804                           NIG_REG_LLH0_FUNC_EN, 0);
7805                 for (i = 0; i < NUM_MACS; i++) {
7806                         mac_en[i] = REG_RD(bp, port ?
7807                                              (NIG_REG_LLH1_FUNC_MEM_ENABLE +
7808                                               4 * i) :
7809                                              (NIG_REG_LLH0_FUNC_MEM_ENABLE +
7810                                               4 * i));
7811                         REG_WR(bp, port ? (NIG_REG_LLH1_FUNC_MEM_ENABLE +
7812                                               4 * i) :
7813                                   (NIG_REG_LLH0_FUNC_MEM_ENABLE + 4 * i), 0);
7814                 }
7815         }
7816
7817         /* Close BMC to host */
7818         REG_WR(bp, port ? NIG_REG_P0_TX_MNG_HOST_ENABLE :
7819                NIG_REG_P1_TX_MNG_HOST_ENABLE, 0);
7820
7821         /* Suspend Tx switching to the PF. Completion of this ramrod
7822          * further guarantees that all the packets of that PF / child
7823          * VFs in BRB were processed by the Parser, so it is safe to
7824          * change the NIC_MODE register.
7825          */
7826         rc = bnx2x_func_switch_update(bp, 1);
7827         if (rc) {
7828                 BNX2X_ERR("Can't suspend tx-switching!\n");
7829                 return rc;
7830         }
7831
7832         /* Change NIC_MODE register */
7833         REG_WR(bp, PRS_REG_NIC_MODE, 0);
7834
7835         /* Open input from network */
7836         if (bp->mf_mode == SINGLE_FUNCTION) {
7837                 bnx2x_set_rx_filter(&bp->link_params, 1);
7838         } else {
7839                 REG_WR(bp, port ? NIG_REG_LLH1_FUNC_EN :
7840                           NIG_REG_LLH0_FUNC_EN, vlan_en);
7841                 for (i = 0; i < NUM_MACS; i++) {
7842                         REG_WR(bp, port ? (NIG_REG_LLH1_FUNC_MEM_ENABLE +
7843                                               4 * i) :
7844                                   (NIG_REG_LLH0_FUNC_MEM_ENABLE + 4 * i),
7845                                   mac_en[i]);
7846                 }
7847         }
7848
7849         /* Enable BMC to host */
7850         REG_WR(bp, port ? NIG_REG_P0_TX_MNG_HOST_ENABLE :
7851                NIG_REG_P1_TX_MNG_HOST_ENABLE, 1);
7852
7853         /* Resume Tx switching to the PF */
7854         rc = bnx2x_func_switch_update(bp, 0);
7855         if (rc) {
7856                 BNX2X_ERR("Can't resume tx-switching!\n");
7857                 return rc;
7858         }
7859
7860         DP(NETIF_MSG_IFUP, "NIC MODE disabled\n");
7861         return 0;
7862 }
7863
7864 int bnx2x_init_hw_func_cnic(struct bnx2x *bp)
7865 {
7866         int rc;
7867
7868         bnx2x_ilt_init_op_cnic(bp, INITOP_SET);
7869
7870         if (CONFIGURE_NIC_MODE(bp)) {
7871                 /* Configure searcher as part of function hw init */
7872                 bnx2x_init_searcher(bp);
7873
7874                 /* Reset NIC mode */
7875                 rc = bnx2x_reset_nic_mode(bp);
7876                 if (rc)
7877                         BNX2X_ERR("Can't change NIC mode!\n");
7878                 return rc;
7879         }
7880
7881         return 0;
7882 }
7883
7884 /* previous driver DMAE transaction may have occurred when pre-boot stage ended
7885  * and boot began, or when kdump kernel was loaded. Either case would invalidate
7886  * the addresses of the transaction, resulting in was-error bit set in the pci
7887  * causing all hw-to-host pcie transactions to timeout. If this happened we want
7888  * to clear the interrupt which detected this from the pglueb and the was done
7889  * bit
7890  */
7891 static void bnx2x_clean_pglue_errors(struct bnx2x *bp)
7892 {
7893         if (!CHIP_IS_E1x(bp))
7894                 REG_WR(bp, PGLUE_B_REG_WAS_ERROR_PF_7_0_CLR,
7895                        1 << BP_ABS_FUNC(bp));
7896 }
7897
7898 static int bnx2x_init_hw_func(struct bnx2x *bp)
7899 {
7900         int port = BP_PORT(bp);
7901         int func = BP_FUNC(bp);
7902         int init_phase = PHASE_PF0 + func;
7903         struct bnx2x_ilt *ilt = BP_ILT(bp);
7904         u16 cdu_ilt_start;
7905         u32 addr, val;
7906         u32 main_mem_base, main_mem_size, main_mem_prty_clr;
7907         int i, main_mem_width, rc;
7908
7909         DP(NETIF_MSG_HW, "starting func init  func %d\n", func);
7910
7911         /* FLR cleanup - hmmm */
7912         if (!CHIP_IS_E1x(bp)) {
7913                 rc = bnx2x_pf_flr_clnup(bp);
7914                 if (rc) {
7915                         bnx2x_fw_dump(bp);
7916                         return rc;
7917                 }
7918         }
7919
7920         /* set MSI reconfigure capability */
7921         if (bp->common.int_block == INT_BLOCK_HC) {
7922                 addr = (port ? HC_REG_CONFIG_1 : HC_REG_CONFIG_0);
7923                 val = REG_RD(bp, addr);
7924                 val |= HC_CONFIG_0_REG_MSI_ATTN_EN_0;
7925                 REG_WR(bp, addr, val);
7926         }
7927
7928         bnx2x_init_block(bp, BLOCK_PXP, init_phase);
7929         bnx2x_init_block(bp, BLOCK_PXP2, init_phase);
7930
7931         ilt = BP_ILT(bp);
7932         cdu_ilt_start = ilt->clients[ILT_CLIENT_CDU].start;
7933
7934         if (IS_SRIOV(bp))
7935                 cdu_ilt_start += BNX2X_FIRST_VF_CID/ILT_PAGE_CIDS;
7936         cdu_ilt_start = bnx2x_iov_init_ilt(bp, cdu_ilt_start);
7937
7938         /* since BNX2X_FIRST_VF_CID > 0 the PF L2 cids precedes
7939          * those of the VFs, so start line should be reset
7940          */
7941         cdu_ilt_start = ilt->clients[ILT_CLIENT_CDU].start;
7942         for (i = 0; i < L2_ILT_LINES(bp); i++) {
7943                 ilt->lines[cdu_ilt_start + i].page = bp->context[i].vcxt;
7944                 ilt->lines[cdu_ilt_start + i].page_mapping =
7945                         bp->context[i].cxt_mapping;
7946                 ilt->lines[cdu_ilt_start + i].size = bp->context[i].size;
7947         }
7948
7949         bnx2x_ilt_init_op(bp, INITOP_SET);
7950
7951         if (!CONFIGURE_NIC_MODE(bp)) {
7952                 bnx2x_init_searcher(bp);
7953                 REG_WR(bp, PRS_REG_NIC_MODE, 0);
7954                 DP(NETIF_MSG_IFUP, "NIC MODE disabled\n");
7955         } else {
7956                 /* Set NIC mode */
7957                 REG_WR(bp, PRS_REG_NIC_MODE, 1);
7958                 DP(NETIF_MSG_IFUP, "NIC MODE configured\n");
7959         }
7960
7961         if (!CHIP_IS_E1x(bp)) {
7962                 u32 pf_conf = IGU_PF_CONF_FUNC_EN;
7963
7964                 /* Turn on a single ISR mode in IGU if driver is going to use
7965                  * INT#x or MSI
7966                  */
7967                 if (!(bp->flags & USING_MSIX_FLAG))
7968                         pf_conf |= IGU_PF_CONF_SINGLE_ISR_EN;
7969                 /*
7970                  * Timers workaround bug: function init part.
7971                  * Need to wait 20msec after initializing ILT,
7972                  * needed to make sure there are no requests in
7973                  * one of the PXP internal queues with "old" ILT addresses
7974                  */
7975                 msleep(20);
7976                 /*
7977                  * Master enable - Due to WB DMAE writes performed before this
7978                  * register is re-initialized as part of the regular function
7979                  * init
7980                  */
7981                 REG_WR(bp, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, 1);
7982                 /* Enable the function in IGU */
7983                 REG_WR(bp, IGU_REG_PF_CONFIGURATION, pf_conf);
7984         }
7985
7986         bp->dmae_ready = 1;
7987
7988         bnx2x_init_block(bp, BLOCK_PGLUE_B, init_phase);
7989
7990         bnx2x_clean_pglue_errors(bp);
7991
7992         bnx2x_init_block(bp, BLOCK_ATC, init_phase);
7993         bnx2x_init_block(bp, BLOCK_DMAE, init_phase);
7994         bnx2x_init_block(bp, BLOCK_NIG, init_phase);
7995         bnx2x_init_block(bp, BLOCK_SRC, init_phase);
7996         bnx2x_init_block(bp, BLOCK_MISC, init_phase);
7997         bnx2x_init_block(bp, BLOCK_TCM, init_phase);
7998         bnx2x_init_block(bp, BLOCK_UCM, init_phase);
7999         bnx2x_init_block(bp, BLOCK_CCM, init_phase);
8000         bnx2x_init_block(bp, BLOCK_XCM, init_phase);
8001         bnx2x_init_block(bp, BLOCK_TSEM, init_phase);
8002         bnx2x_init_block(bp, BLOCK_USEM, init_phase);
8003         bnx2x_init_block(bp, BLOCK_CSEM, init_phase);
8004         bnx2x_init_block(bp, BLOCK_XSEM, init_phase);
8005
8006         if (!CHIP_IS_E1x(bp))
8007                 REG_WR(bp, QM_REG_PF_EN, 1);
8008
8009         if (!CHIP_IS_E1x(bp)) {
8010                 REG_WR(bp, TSEM_REG_VFPF_ERR_NUM, BNX2X_MAX_NUM_OF_VFS + func);
8011                 REG_WR(bp, USEM_REG_VFPF_ERR_NUM, BNX2X_MAX_NUM_OF_VFS + func);
8012                 REG_WR(bp, CSEM_REG_VFPF_ERR_NUM, BNX2X_MAX_NUM_OF_VFS + func);
8013                 REG_WR(bp, XSEM_REG_VFPF_ERR_NUM, BNX2X_MAX_NUM_OF_VFS + func);
8014         }
8015         bnx2x_init_block(bp, BLOCK_QM, init_phase);
8016
8017         bnx2x_init_block(bp, BLOCK_TM, init_phase);
8018         bnx2x_init_block(bp, BLOCK_DORQ, init_phase);
8019         REG_WR(bp, DORQ_REG_MODE_ACT, 1); /* no dpm */
8020
8021         bnx2x_iov_init_dq(bp);
8022
8023         bnx2x_init_block(bp, BLOCK_BRB1, init_phase);
8024         bnx2x_init_block(bp, BLOCK_PRS, init_phase);
8025         bnx2x_init_block(bp, BLOCK_TSDM, init_phase);
8026         bnx2x_init_block(bp, BLOCK_CSDM, init_phase);
8027         bnx2x_init_block(bp, BLOCK_USDM, init_phase);
8028         bnx2x_init_block(bp, BLOCK_XSDM, init_phase);
8029         bnx2x_init_block(bp, BLOCK_UPB, init_phase);
8030         bnx2x_init_block(bp, BLOCK_XPB, init_phase);
8031         bnx2x_init_block(bp, BLOCK_PBF, init_phase);
8032         if (!CHIP_IS_E1x(bp))
8033                 REG_WR(bp, PBF_REG_DISABLE_PF, 0);
8034
8035         bnx2x_init_block(bp, BLOCK_CDU, init_phase);
8036
8037         bnx2x_init_block(bp, BLOCK_CFC, init_phase);
8038
8039         if (!CHIP_IS_E1x(bp))
8040                 REG_WR(bp, CFC_REG_WEAK_ENABLE_PF, 1);
8041
8042         if (IS_MF(bp)) {
8043                 if (!(IS_MF_UFP(bp) && BNX2X_IS_MF_SD_PROTOCOL_FCOE(bp))) {
8044                         REG_WR(bp, NIG_REG_LLH0_FUNC_EN + port * 8, 1);
8045                         REG_WR(bp, NIG_REG_LLH0_FUNC_VLAN_ID + port * 8,
8046                                bp->mf_ov);
8047                 }
8048         }
8049
8050         bnx2x_init_block(bp, BLOCK_MISC_AEU, init_phase);
8051
8052         /* HC init per function */
8053         if (bp->common.int_block == INT_BLOCK_HC) {
8054                 if (CHIP_IS_E1H(bp)) {
8055                         REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_12 + func*4, 0);
8056
8057                         REG_WR(bp, HC_REG_LEADING_EDGE_0 + port*8, 0);
8058                         REG_WR(bp, HC_REG_TRAILING_EDGE_0 + port*8, 0);
8059                 }
8060                 bnx2x_init_block(bp, BLOCK_HC, init_phase);
8061
8062         } else {
8063                 int num_segs, sb_idx, prod_offset;
8064
8065                 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_12 + func*4, 0);
8066
8067                 if (!CHIP_IS_E1x(bp)) {
8068                         REG_WR(bp, IGU_REG_LEADING_EDGE_LATCH, 0);
8069                         REG_WR(bp, IGU_REG_TRAILING_EDGE_LATCH, 0);
8070                 }
8071
8072                 bnx2x_init_block(bp, BLOCK_IGU, init_phase);
8073
8074                 if (!CHIP_IS_E1x(bp)) {
8075                         int dsb_idx = 0;
8076                         /**
8077                          * Producer memory:
8078                          * E2 mode: address 0-135 match to the mapping memory;
8079                          * 136 - PF0 default prod; 137 - PF1 default prod;
8080                          * 138 - PF2 default prod; 139 - PF3 default prod;
8081                          * 140 - PF0 attn prod;    141 - PF1 attn prod;
8082                          * 142 - PF2 attn prod;    143 - PF3 attn prod;
8083                          * 144-147 reserved.
8084                          *
8085                          * E1.5 mode - In backward compatible mode;
8086                          * for non default SB; each even line in the memory
8087                          * holds the U producer and each odd line hold
8088                          * the C producer. The first 128 producers are for
8089                          * NDSB (PF0 - 0-31; PF1 - 32-63 and so on). The last 20
8090                          * producers are for the DSB for each PF.
8091                          * Each PF has five segments: (the order inside each
8092                          * segment is PF0; PF1; PF2; PF3) - 128-131 U prods;
8093                          * 132-135 C prods; 136-139 X prods; 140-143 T prods;
8094                          * 144-147 attn prods;
8095                          */
8096                         /* non-default-status-blocks */
8097                         num_segs = CHIP_INT_MODE_IS_BC(bp) ?
8098                                 IGU_BC_NDSB_NUM_SEGS : IGU_NORM_NDSB_NUM_SEGS;
8099                         for (sb_idx = 0; sb_idx < bp->igu_sb_cnt; sb_idx++) {
8100                                 prod_offset = (bp->igu_base_sb + sb_idx) *
8101                                         num_segs;
8102
8103                                 for (i = 0; i < num_segs; i++) {
8104                                         addr = IGU_REG_PROD_CONS_MEMORY +
8105                                                         (prod_offset + i) * 4;
8106                                         REG_WR(bp, addr, 0);
8107                                 }
8108                                 /* send consumer update with value 0 */
8109                                 bnx2x_ack_sb(bp, bp->igu_base_sb + sb_idx,
8110                                              USTORM_ID, 0, IGU_INT_NOP, 1);
8111                                 bnx2x_igu_clear_sb(bp,
8112                                                    bp->igu_base_sb + sb_idx);
8113                         }
8114
8115                         /* default-status-blocks */
8116                         num_segs = CHIP_INT_MODE_IS_BC(bp) ?
8117                                 IGU_BC_DSB_NUM_SEGS : IGU_NORM_DSB_NUM_SEGS;
8118
8119                         if (CHIP_MODE_IS_4_PORT(bp))
8120                                 dsb_idx = BP_FUNC(bp);
8121                         else
8122                                 dsb_idx = BP_VN(bp);
8123
8124                         prod_offset = (CHIP_INT_MODE_IS_BC(bp) ?
8125                                        IGU_BC_BASE_DSB_PROD + dsb_idx :
8126                                        IGU_NORM_BASE_DSB_PROD + dsb_idx);
8127
8128                         /*
8129                          * igu prods come in chunks of E1HVN_MAX (4) -
8130                          * does not matters what is the current chip mode
8131                          */
8132                         for (i = 0; i < (num_segs * E1HVN_MAX);
8133                              i += E1HVN_MAX) {
8134                                 addr = IGU_REG_PROD_CONS_MEMORY +
8135                                                         (prod_offset + i)*4;
8136                                 REG_WR(bp, addr, 0);
8137                         }
8138                         /* send consumer update with 0 */
8139                         if (CHIP_INT_MODE_IS_BC(bp)) {
8140                                 bnx2x_ack_sb(bp, bp->igu_dsb_id,
8141                                              USTORM_ID, 0, IGU_INT_NOP, 1);
8142                                 bnx2x_ack_sb(bp, bp->igu_dsb_id,
8143                                              CSTORM_ID, 0, IGU_INT_NOP, 1);
8144                                 bnx2x_ack_sb(bp, bp->igu_dsb_id,
8145                                              XSTORM_ID, 0, IGU_INT_NOP, 1);
8146                                 bnx2x_ack_sb(bp, bp->igu_dsb_id,
8147                                              TSTORM_ID, 0, IGU_INT_NOP, 1);
8148                                 bnx2x_ack_sb(bp, bp->igu_dsb_id,
8149                                              ATTENTION_ID, 0, IGU_INT_NOP, 1);
8150                         } else {
8151                                 bnx2x_ack_sb(bp, bp->igu_dsb_id,
8152                                              USTORM_ID, 0, IGU_INT_NOP, 1);
8153                                 bnx2x_ack_sb(bp, bp->igu_dsb_id,
8154                                              ATTENTION_ID, 0, IGU_INT_NOP, 1);
8155                         }
8156                         bnx2x_igu_clear_sb(bp, bp->igu_dsb_id);
8157
8158                         /* !!! These should become driver const once
8159                            rf-tool supports split-68 const */
8160                         REG_WR(bp, IGU_REG_SB_INT_BEFORE_MASK_LSB, 0);
8161                         REG_WR(bp, IGU_REG_SB_INT_BEFORE_MASK_MSB, 0);
8162                         REG_WR(bp, IGU_REG_SB_MASK_LSB, 0);
8163                         REG_WR(bp, IGU_REG_SB_MASK_MSB, 0);
8164                         REG_WR(bp, IGU_REG_PBA_STATUS_LSB, 0);
8165                         REG_WR(bp, IGU_REG_PBA_STATUS_MSB, 0);
8166                 }
8167         }
8168
8169         /* Reset PCIE errors for debug */
8170         REG_WR(bp, 0x2114, 0xffffffff);
8171         REG_WR(bp, 0x2120, 0xffffffff);
8172
8173         if (CHIP_IS_E1x(bp)) {
8174                 main_mem_size = HC_REG_MAIN_MEMORY_SIZE / 2; /*dwords*/
8175                 main_mem_base = HC_REG_MAIN_MEMORY +
8176                                 BP_PORT(bp) * (main_mem_size * 4);
8177                 main_mem_prty_clr = HC_REG_HC_PRTY_STS_CLR;
8178                 main_mem_width = 8;
8179
8180                 val = REG_RD(bp, main_mem_prty_clr);
8181                 if (val)
8182                         DP(NETIF_MSG_HW,
8183                            "Hmmm... Parity errors in HC block during function init (0x%x)!\n",
8184                            val);
8185
8186                 /* Clear "false" parity errors in MSI-X table */
8187                 for (i = main_mem_base;
8188                      i < main_mem_base + main_mem_size * 4;
8189                      i += main_mem_width) {
8190                         bnx2x_read_dmae(bp, i, main_mem_width / 4);
8191                         bnx2x_write_dmae(bp, bnx2x_sp_mapping(bp, wb_data),
8192                                          i, main_mem_width / 4);
8193                 }
8194                 /* Clear HC parity attention */
8195                 REG_RD(bp, main_mem_prty_clr);
8196         }
8197
8198 #ifdef BNX2X_STOP_ON_ERROR
8199         /* Enable STORMs SP logging */
8200         REG_WR8(bp, BAR_USTRORM_INTMEM +
8201                USTORM_RECORD_SLOW_PATH_OFFSET(BP_FUNC(bp)), 1);
8202         REG_WR8(bp, BAR_TSTRORM_INTMEM +
8203                TSTORM_RECORD_SLOW_PATH_OFFSET(BP_FUNC(bp)), 1);
8204         REG_WR8(bp, BAR_CSTRORM_INTMEM +
8205                CSTORM_RECORD_SLOW_PATH_OFFSET(BP_FUNC(bp)), 1);
8206         REG_WR8(bp, BAR_XSTRORM_INTMEM +
8207                XSTORM_RECORD_SLOW_PATH_OFFSET(BP_FUNC(bp)), 1);
8208 #endif
8209
8210         bnx2x_phy_probe(&bp->link_params);
8211
8212         return 0;
8213 }
8214
8215 void bnx2x_free_mem_cnic(struct bnx2x *bp)
8216 {
8217         bnx2x_ilt_mem_op_cnic(bp, ILT_MEMOP_FREE);
8218
8219         if (!CHIP_IS_E1x(bp))
8220                 BNX2X_PCI_FREE(bp->cnic_sb.e2_sb, bp->cnic_sb_mapping,
8221                                sizeof(struct host_hc_status_block_e2));
8222         else
8223                 BNX2X_PCI_FREE(bp->cnic_sb.e1x_sb, bp->cnic_sb_mapping,
8224                                sizeof(struct host_hc_status_block_e1x));
8225
8226         BNX2X_PCI_FREE(bp->t2, bp->t2_mapping, SRC_T2_SZ);
8227 }
8228
8229 void bnx2x_free_mem(struct bnx2x *bp)
8230 {
8231         int i;
8232
8233         BNX2X_PCI_FREE(bp->fw_stats, bp->fw_stats_mapping,
8234                        bp->fw_stats_data_sz + bp->fw_stats_req_sz);
8235
8236         if (IS_VF(bp))
8237                 return;
8238
8239         BNX2X_PCI_FREE(bp->def_status_blk, bp->def_status_blk_mapping,
8240                        sizeof(struct host_sp_status_block));
8241
8242         BNX2X_PCI_FREE(bp->slowpath, bp->slowpath_mapping,
8243                        sizeof(struct bnx2x_slowpath));
8244
8245         for (i = 0; i < L2_ILT_LINES(bp); i++)
8246                 BNX2X_PCI_FREE(bp->context[i].vcxt, bp->context[i].cxt_mapping,
8247                                bp->context[i].size);
8248         bnx2x_ilt_mem_op(bp, ILT_MEMOP_FREE);
8249
8250         BNX2X_FREE(bp->ilt->lines);
8251
8252         BNX2X_PCI_FREE(bp->spq, bp->spq_mapping, BCM_PAGE_SIZE);
8253
8254         BNX2X_PCI_FREE(bp->eq_ring, bp->eq_mapping,
8255                        BCM_PAGE_SIZE * NUM_EQ_PAGES);
8256
8257         BNX2X_PCI_FREE(bp->t2, bp->t2_mapping, SRC_T2_SZ);
8258
8259         bnx2x_iov_free_mem(bp);
8260 }
8261
8262 int bnx2x_alloc_mem_cnic(struct bnx2x *bp)
8263 {
8264         if (!CHIP_IS_E1x(bp)) {
8265                 /* size = the status block + ramrod buffers */
8266                 bp->cnic_sb.e2_sb = BNX2X_PCI_ALLOC(&bp->cnic_sb_mapping,
8267                                                     sizeof(struct host_hc_status_block_e2));
8268                 if (!bp->cnic_sb.e2_sb)
8269                         goto alloc_mem_err;
8270         } else {
8271                 bp->cnic_sb.e1x_sb = BNX2X_PCI_ALLOC(&bp->cnic_sb_mapping,
8272                                                      sizeof(struct host_hc_status_block_e1x));
8273                 if (!bp->cnic_sb.e1x_sb)
8274                         goto alloc_mem_err;
8275         }
8276
8277         if (CONFIGURE_NIC_MODE(bp) && !bp->t2) {
8278                 /* allocate searcher T2 table, as it wasn't allocated before */
8279                 bp->t2 = BNX2X_PCI_ALLOC(&bp->t2_mapping, SRC_T2_SZ);
8280                 if (!bp->t2)
8281                         goto alloc_mem_err;
8282         }
8283
8284         /* write address to which L5 should insert its values */
8285         bp->cnic_eth_dev.addr_drv_info_to_mcp =
8286                 &bp->slowpath->drv_info_to_mcp;
8287
8288         if (bnx2x_ilt_mem_op_cnic(bp, ILT_MEMOP_ALLOC))
8289                 goto alloc_mem_err;
8290
8291         return 0;
8292
8293 alloc_mem_err:
8294         bnx2x_free_mem_cnic(bp);
8295         BNX2X_ERR("Can't allocate memory\n");
8296         return -ENOMEM;
8297 }
8298
8299 int bnx2x_alloc_mem(struct bnx2x *bp)
8300 {
8301         int i, allocated, context_size;
8302
8303         if (!CONFIGURE_NIC_MODE(bp) && !bp->t2) {
8304                 /* allocate searcher T2 table */
8305                 bp->t2 = BNX2X_PCI_ALLOC(&bp->t2_mapping, SRC_T2_SZ);
8306                 if (!bp->t2)
8307                         goto alloc_mem_err;
8308         }
8309
8310         bp->def_status_blk = BNX2X_PCI_ALLOC(&bp->def_status_blk_mapping,
8311                                              sizeof(struct host_sp_status_block));
8312         if (!bp->def_status_blk)
8313                 goto alloc_mem_err;
8314
8315         bp->slowpath = BNX2X_PCI_ALLOC(&bp->slowpath_mapping,
8316                                        sizeof(struct bnx2x_slowpath));
8317         if (!bp->slowpath)
8318                 goto alloc_mem_err;
8319
8320         /* Allocate memory for CDU context:
8321          * This memory is allocated separately and not in the generic ILT
8322          * functions because CDU differs in few aspects:
8323          * 1. There are multiple entities allocating memory for context -
8324          * 'regular' driver, CNIC and SRIOV driver. Each separately controls
8325          * its own ILT lines.
8326          * 2. Since CDU page-size is not a single 4KB page (which is the case
8327          * for the other ILT clients), to be efficient we want to support
8328          * allocation of sub-page-size in the last entry.
8329          * 3. Context pointers are used by the driver to pass to FW / update
8330          * the context (for the other ILT clients the pointers are used just to
8331          * free the memory during unload).
8332          */
8333         context_size = sizeof(union cdu_context) * BNX2X_L2_CID_COUNT(bp);
8334
8335         for (i = 0, allocated = 0; allocated < context_size; i++) {
8336                 bp->context[i].size = min(CDU_ILT_PAGE_SZ,
8337                                           (context_size - allocated));
8338                 bp->context[i].vcxt = BNX2X_PCI_ALLOC(&bp->context[i].cxt_mapping,
8339                                                       bp->context[i].size);
8340                 if (!bp->context[i].vcxt)
8341                         goto alloc_mem_err;
8342                 allocated += bp->context[i].size;
8343         }
8344         bp->ilt->lines = kcalloc(ILT_MAX_LINES, sizeof(struct ilt_line),
8345                                  GFP_KERNEL);
8346         if (!bp->ilt->lines)
8347                 goto alloc_mem_err;
8348
8349         if (bnx2x_ilt_mem_op(bp, ILT_MEMOP_ALLOC))
8350                 goto alloc_mem_err;
8351
8352         if (bnx2x_iov_alloc_mem(bp))
8353                 goto alloc_mem_err;
8354
8355         /* Slow path ring */
8356         bp->spq = BNX2X_PCI_ALLOC(&bp->spq_mapping, BCM_PAGE_SIZE);
8357         if (!bp->spq)
8358                 goto alloc_mem_err;
8359
8360         /* EQ */
8361         bp->eq_ring = BNX2X_PCI_ALLOC(&bp->eq_mapping,
8362                                       BCM_PAGE_SIZE * NUM_EQ_PAGES);
8363         if (!bp->eq_ring)
8364                 goto alloc_mem_err;
8365
8366         return 0;
8367
8368 alloc_mem_err:
8369         bnx2x_free_mem(bp);
8370         BNX2X_ERR("Can't allocate memory\n");
8371         return -ENOMEM;
8372 }
8373
8374 /*
8375  * Init service functions
8376  */
8377
8378 int bnx2x_set_mac_one(struct bnx2x *bp, u8 *mac,
8379                       struct bnx2x_vlan_mac_obj *obj, bool set,
8380                       int mac_type, unsigned long *ramrod_flags)
8381 {
8382         int rc;
8383         struct bnx2x_vlan_mac_ramrod_params ramrod_param;
8384
8385         memset(&ramrod_param, 0, sizeof(ramrod_param));
8386
8387         /* Fill general parameters */
8388         ramrod_param.vlan_mac_obj = obj;
8389         ramrod_param.ramrod_flags = *ramrod_flags;
8390
8391         /* Fill a user request section if needed */
8392         if (!test_bit(RAMROD_CONT, ramrod_flags)) {
8393                 memcpy(ramrod_param.user_req.u.mac.mac, mac, ETH_ALEN);
8394
8395                 __set_bit(mac_type, &ramrod_param.user_req.vlan_mac_flags);
8396
8397                 /* Set the command: ADD or DEL */
8398                 if (set)
8399                         ramrod_param.user_req.cmd = BNX2X_VLAN_MAC_ADD;
8400                 else
8401                         ramrod_param.user_req.cmd = BNX2X_VLAN_MAC_DEL;
8402         }
8403
8404         rc = bnx2x_config_vlan_mac(bp, &ramrod_param);
8405
8406         if (rc == -EEXIST) {
8407                 DP(BNX2X_MSG_SP, "Failed to schedule ADD operations: %d\n", rc);
8408                 /* do not treat adding same MAC as error */
8409                 rc = 0;
8410         } else if (rc < 0)
8411                 BNX2X_ERR("%s MAC failed\n", (set ? "Set" : "Del"));
8412
8413         return rc;
8414 }
8415
8416 int bnx2x_del_all_macs(struct bnx2x *bp,
8417                        struct bnx2x_vlan_mac_obj *mac_obj,
8418                        int mac_type, bool wait_for_comp)
8419 {
8420         int rc;
8421         unsigned long ramrod_flags = 0, vlan_mac_flags = 0;
8422
8423         /* Wait for completion of requested */
8424         if (wait_for_comp)
8425                 __set_bit(RAMROD_COMP_WAIT, &ramrod_flags);
8426
8427         /* Set the mac type of addresses we want to clear */
8428         __set_bit(mac_type, &vlan_mac_flags);
8429
8430         rc = mac_obj->delete_all(bp, mac_obj, &vlan_mac_flags, &ramrod_flags);
8431         if (rc < 0)
8432                 BNX2X_ERR("Failed to delete MACs: %d\n", rc);
8433
8434         return rc;
8435 }
8436
8437 int bnx2x_set_eth_mac(struct bnx2x *bp, bool set)
8438 {
8439         if (IS_PF(bp)) {
8440                 unsigned long ramrod_flags = 0;
8441
8442                 DP(NETIF_MSG_IFUP, "Adding Eth MAC\n");
8443                 __set_bit(RAMROD_COMP_WAIT, &ramrod_flags);
8444                 return bnx2x_set_mac_one(bp, bp->dev->dev_addr,
8445                                          &bp->sp_objs->mac_obj, set,
8446                                          BNX2X_ETH_MAC, &ramrod_flags);
8447         } else { /* vf */
8448                 return bnx2x_vfpf_config_mac(bp, bp->dev->dev_addr,
8449                                              bp->fp->index, set);
8450         }
8451 }
8452
8453 int bnx2x_setup_leading(struct bnx2x *bp)
8454 {
8455         if (IS_PF(bp))
8456                 return bnx2x_setup_queue(bp, &bp->fp[0], true);
8457         else /* VF */
8458                 return bnx2x_vfpf_setup_q(bp, &bp->fp[0], true);
8459 }
8460
8461 /**
8462  * bnx2x_set_int_mode - configure interrupt mode
8463  *
8464  * @bp:         driver handle
8465  *
8466  * In case of MSI-X it will also try to enable MSI-X.
8467  */
8468 int bnx2x_set_int_mode(struct bnx2x *bp)
8469 {
8470         int rc = 0;
8471
8472         if (IS_VF(bp) && int_mode != BNX2X_INT_MODE_MSIX) {
8473                 BNX2X_ERR("VF not loaded since interrupt mode not msix\n");
8474                 return -EINVAL;
8475         }
8476
8477         switch (int_mode) {
8478         case BNX2X_INT_MODE_MSIX:
8479                 /* attempt to enable msix */
8480                 rc = bnx2x_enable_msix(bp);
8481
8482                 /* msix attained */
8483                 if (!rc)
8484                         return 0;
8485
8486                 /* vfs use only msix */
8487                 if (rc && IS_VF(bp))
8488                         return rc;
8489
8490                 /* failed to enable multiple MSI-X */
8491                 BNX2X_DEV_INFO("Failed to enable multiple MSI-X (%d), set number of queues to %d\n",
8492                                bp->num_queues,
8493                                1 + bp->num_cnic_queues);
8494
8495                 /* falling through... */
8496         case BNX2X_INT_MODE_MSI:
8497                 bnx2x_enable_msi(bp);
8498
8499                 /* falling through... */
8500         case BNX2X_INT_MODE_INTX:
8501                 bp->num_ethernet_queues = 1;
8502                 bp->num_queues = bp->num_ethernet_queues + bp->num_cnic_queues;
8503                 BNX2X_DEV_INFO("set number of queues to 1\n");
8504                 break;
8505         default:
8506                 BNX2X_DEV_INFO("unknown value in int_mode module parameter\n");
8507                 return -EINVAL;
8508         }
8509         return 0;
8510 }
8511
8512 /* must be called prior to any HW initializations */
8513 static inline u16 bnx2x_cid_ilt_lines(struct bnx2x *bp)
8514 {
8515         if (IS_SRIOV(bp))
8516                 return (BNX2X_FIRST_VF_CID + BNX2X_VF_CIDS)/ILT_PAGE_CIDS;
8517         return L2_ILT_LINES(bp);
8518 }
8519
8520 void bnx2x_ilt_set_info(struct bnx2x *bp)
8521 {
8522         struct ilt_client_info *ilt_client;
8523         struct bnx2x_ilt *ilt = BP_ILT(bp);
8524         u16 line = 0;
8525
8526         ilt->start_line = FUNC_ILT_BASE(BP_FUNC(bp));
8527         DP(BNX2X_MSG_SP, "ilt starts at line %d\n", ilt->start_line);
8528
8529         /* CDU */
8530         ilt_client = &ilt->clients[ILT_CLIENT_CDU];
8531         ilt_client->client_num = ILT_CLIENT_CDU;
8532         ilt_client->page_size = CDU_ILT_PAGE_SZ;
8533         ilt_client->flags = ILT_CLIENT_SKIP_MEM;
8534         ilt_client->start = line;
8535         line += bnx2x_cid_ilt_lines(bp);
8536
8537         if (CNIC_SUPPORT(bp))
8538                 line += CNIC_ILT_LINES;
8539         ilt_client->end = line - 1;
8540
8541         DP(NETIF_MSG_IFUP, "ilt client[CDU]: start %d, end %d, psz 0x%x, flags 0x%x, hw psz %d\n",
8542            ilt_client->start,
8543            ilt_client->end,
8544            ilt_client->page_size,
8545            ilt_client->flags,
8546            ilog2(ilt_client->page_size >> 12));
8547
8548         /* QM */
8549         if (QM_INIT(bp->qm_cid_count)) {
8550                 ilt_client = &ilt->clients[ILT_CLIENT_QM];
8551                 ilt_client->client_num = ILT_CLIENT_QM;
8552                 ilt_client->page_size = QM_ILT_PAGE_SZ;
8553                 ilt_client->flags = 0;
8554                 ilt_client->start = line;
8555
8556                 /* 4 bytes for each cid */
8557                 line += DIV_ROUND_UP(bp->qm_cid_count * QM_QUEUES_PER_FUNC * 4,
8558                                                          QM_ILT_PAGE_SZ);
8559
8560                 ilt_client->end = line - 1;
8561
8562                 DP(NETIF_MSG_IFUP,
8563                    "ilt client[QM]: start %d, end %d, psz 0x%x, flags 0x%x, hw psz %d\n",
8564                    ilt_client->start,
8565                    ilt_client->end,
8566                    ilt_client->page_size,
8567                    ilt_client->flags,
8568                    ilog2(ilt_client->page_size >> 12));
8569         }
8570
8571         if (CNIC_SUPPORT(bp)) {
8572                 /* SRC */
8573                 ilt_client = &ilt->clients[ILT_CLIENT_SRC];
8574                 ilt_client->client_num = ILT_CLIENT_SRC;
8575                 ilt_client->page_size = SRC_ILT_PAGE_SZ;
8576                 ilt_client->flags = 0;
8577                 ilt_client->start = line;
8578                 line += SRC_ILT_LINES;
8579                 ilt_client->end = line - 1;
8580
8581                 DP(NETIF_MSG_IFUP,
8582                    "ilt client[SRC]: start %d, end %d, psz 0x%x, flags 0x%x, hw psz %d\n",
8583                    ilt_client->start,
8584                    ilt_client->end,
8585                    ilt_client->page_size,
8586                    ilt_client->flags,
8587                    ilog2(ilt_client->page_size >> 12));
8588
8589                 /* TM */
8590                 ilt_client = &ilt->clients[ILT_CLIENT_TM];
8591                 ilt_client->client_num = ILT_CLIENT_TM;
8592                 ilt_client->page_size = TM_ILT_PAGE_SZ;
8593                 ilt_client->flags = 0;
8594                 ilt_client->start = line;
8595                 line += TM_ILT_LINES;
8596                 ilt_client->end = line - 1;
8597
8598                 DP(NETIF_MSG_IFUP,
8599                    "ilt client[TM]: start %d, end %d, psz 0x%x, flags 0x%x, hw psz %d\n",
8600                    ilt_client->start,
8601                    ilt_client->end,
8602                    ilt_client->page_size,
8603                    ilt_client->flags,
8604                    ilog2(ilt_client->page_size >> 12));
8605         }
8606
8607         BUG_ON(line > ILT_MAX_LINES);
8608 }
8609
8610 /**
8611  * bnx2x_pf_q_prep_init - prepare INIT transition parameters
8612  *
8613  * @bp:                 driver handle
8614  * @fp:                 pointer to fastpath
8615  * @init_params:        pointer to parameters structure
8616  *
8617  * parameters configured:
8618  *      - HC configuration
8619  *      - Queue's CDU context
8620  */
8621 static void bnx2x_pf_q_prep_init(struct bnx2x *bp,
8622         struct bnx2x_fastpath *fp, struct bnx2x_queue_init_params *init_params)
8623 {
8624         u8 cos;
8625         int cxt_index, cxt_offset;
8626
8627         /* FCoE Queue uses Default SB, thus has no HC capabilities */
8628         if (!IS_FCOE_FP(fp)) {
8629                 __set_bit(BNX2X_Q_FLG_HC, &init_params->rx.flags);
8630                 __set_bit(BNX2X_Q_FLG_HC, &init_params->tx.flags);
8631
8632                 /* If HC is supported, enable host coalescing in the transition
8633                  * to INIT state.
8634                  */
8635                 __set_bit(BNX2X_Q_FLG_HC_EN, &init_params->rx.flags);
8636                 __set_bit(BNX2X_Q_FLG_HC_EN, &init_params->tx.flags);
8637
8638                 /* HC rate */
8639                 init_params->rx.hc_rate = bp->rx_ticks ?
8640                         (1000000 / bp->rx_ticks) : 0;
8641                 init_params->tx.hc_rate = bp->tx_ticks ?
8642                         (1000000 / bp->tx_ticks) : 0;
8643
8644                 /* FW SB ID */
8645                 init_params->rx.fw_sb_id = init_params->tx.fw_sb_id =
8646                         fp->fw_sb_id;
8647
8648                 /*
8649                  * CQ index among the SB indices: FCoE clients uses the default
8650                  * SB, therefore it's different.
8651                  */
8652                 init_params->rx.sb_cq_index = HC_INDEX_ETH_RX_CQ_CONS;
8653                 init_params->tx.sb_cq_index = HC_INDEX_ETH_FIRST_TX_CQ_CONS;
8654         }
8655
8656         /* set maximum number of COSs supported by this queue */
8657         init_params->max_cos = fp->max_cos;
8658
8659         DP(NETIF_MSG_IFUP, "fp: %d setting queue params max cos to: %d\n",
8660             fp->index, init_params->max_cos);
8661
8662         /* set the context pointers queue object */
8663         for (cos = FIRST_TX_COS_INDEX; cos < init_params->max_cos; cos++) {
8664                 cxt_index = fp->txdata_ptr[cos]->cid / ILT_PAGE_CIDS;
8665                 cxt_offset = fp->txdata_ptr[cos]->cid - (cxt_index *
8666                                 ILT_PAGE_CIDS);
8667                 init_params->cxts[cos] =
8668                         &bp->context[cxt_index].vcxt[cxt_offset].eth;
8669         }
8670 }
8671
8672 static int bnx2x_setup_tx_only(struct bnx2x *bp, struct bnx2x_fastpath *fp,
8673                         struct bnx2x_queue_state_params *q_params,
8674                         struct bnx2x_queue_setup_tx_only_params *tx_only_params,
8675                         int tx_index, bool leading)
8676 {
8677         memset(tx_only_params, 0, sizeof(*tx_only_params));
8678
8679         /* Set the command */
8680         q_params->cmd = BNX2X_Q_CMD_SETUP_TX_ONLY;
8681
8682         /* Set tx-only QUEUE flags: don't zero statistics */
8683         tx_only_params->flags = bnx2x_get_common_flags(bp, fp, false);
8684
8685         /* choose the index of the cid to send the slow path on */
8686         tx_only_params->cid_index = tx_index;
8687
8688         /* Set general TX_ONLY_SETUP parameters */
8689         bnx2x_pf_q_prep_general(bp, fp, &tx_only_params->gen_params, tx_index);
8690
8691         /* Set Tx TX_ONLY_SETUP parameters */
8692         bnx2x_pf_tx_q_prep(bp, fp, &tx_only_params->txq_params, tx_index);
8693
8694         DP(NETIF_MSG_IFUP,
8695            "preparing to send tx-only ramrod for connection: cos %d, primary cid %d, cid %d, client id %d, sp-client id %d, flags %lx\n",
8696            tx_index, q_params->q_obj->cids[FIRST_TX_COS_INDEX],
8697            q_params->q_obj->cids[tx_index], q_params->q_obj->cl_id,
8698            tx_only_params->gen_params.spcl_id, tx_only_params->flags);
8699
8700         /* send the ramrod */
8701         return bnx2x_queue_state_change(bp, q_params);
8702 }
8703
8704 /**
8705  * bnx2x_setup_queue - setup queue
8706  *
8707  * @bp:         driver handle
8708  * @fp:         pointer to fastpath
8709  * @leading:    is leading
8710  *
8711  * This function performs 2 steps in a Queue state machine
8712  *      actually: 1) RESET->INIT 2) INIT->SETUP
8713  */
8714
8715 int bnx2x_setup_queue(struct bnx2x *bp, struct bnx2x_fastpath *fp,
8716                        bool leading)
8717 {
8718         struct bnx2x_queue_state_params q_params = {NULL};
8719         struct bnx2x_queue_setup_params *setup_params =
8720                                                 &q_params.params.setup;
8721         struct bnx2x_queue_setup_tx_only_params *tx_only_params =
8722                                                 &q_params.params.tx_only;
8723         int rc;
8724         u8 tx_index;
8725
8726         DP(NETIF_MSG_IFUP, "setting up queue %d\n", fp->index);
8727
8728         /* reset IGU state skip FCoE L2 queue */
8729         if (!IS_FCOE_FP(fp))
8730                 bnx2x_ack_sb(bp, fp->igu_sb_id, USTORM_ID, 0,
8731                              IGU_INT_ENABLE, 0);
8732
8733         q_params.q_obj = &bnx2x_sp_obj(bp, fp).q_obj;
8734         /* We want to wait for completion in this context */
8735         __set_bit(RAMROD_COMP_WAIT, &q_params.ramrod_flags);
8736
8737         /* Prepare the INIT parameters */
8738         bnx2x_pf_q_prep_init(bp, fp, &q_params.params.init);
8739
8740         /* Set the command */
8741         q_params.cmd = BNX2X_Q_CMD_INIT;
8742
8743         /* Change the state to INIT */
8744         rc = bnx2x_queue_state_change(bp, &q_params);
8745         if (rc) {
8746                 BNX2X_ERR("Queue(%d) INIT failed\n", fp->index);
8747                 return rc;
8748         }
8749
8750         DP(NETIF_MSG_IFUP, "init complete\n");
8751
8752         /* Now move the Queue to the SETUP state... */
8753         memset(setup_params, 0, sizeof(*setup_params));
8754
8755         /* Set QUEUE flags */
8756         setup_params->flags = bnx2x_get_q_flags(bp, fp, leading);
8757
8758         /* Set general SETUP parameters */
8759         bnx2x_pf_q_prep_general(bp, fp, &setup_params->gen_params,
8760                                 FIRST_TX_COS_INDEX);
8761
8762         bnx2x_pf_rx_q_prep(bp, fp, &setup_params->pause_params,
8763                             &setup_params->rxq_params);
8764
8765         bnx2x_pf_tx_q_prep(bp, fp, &setup_params->txq_params,
8766                            FIRST_TX_COS_INDEX);
8767
8768         /* Set the command */
8769         q_params.cmd = BNX2X_Q_CMD_SETUP;
8770
8771         if (IS_FCOE_FP(fp))
8772                 bp->fcoe_init = true;
8773
8774         /* Change the state to SETUP */
8775         rc = bnx2x_queue_state_change(bp, &q_params);
8776         if (rc) {
8777                 BNX2X_ERR("Queue(%d) SETUP failed\n", fp->index);
8778                 return rc;
8779         }
8780
8781         /* loop through the relevant tx-only indices */
8782         for (tx_index = FIRST_TX_ONLY_COS_INDEX;
8783               tx_index < fp->max_cos;
8784               tx_index++) {
8785
8786                 /* prepare and send tx-only ramrod*/
8787                 rc = bnx2x_setup_tx_only(bp, fp, &q_params,
8788                                           tx_only_params, tx_index, leading);
8789                 if (rc) {
8790                         BNX2X_ERR("Queue(%d.%d) TX_ONLY_SETUP failed\n",
8791                                   fp->index, tx_index);
8792                         return rc;
8793                 }
8794         }
8795
8796         return rc;
8797 }
8798
8799 static int bnx2x_stop_queue(struct bnx2x *bp, int index)
8800 {
8801         struct bnx2x_fastpath *fp = &bp->fp[index];
8802         struct bnx2x_fp_txdata *txdata;
8803         struct bnx2x_queue_state_params q_params = {NULL};
8804         int rc, tx_index;
8805
8806         DP(NETIF_MSG_IFDOWN, "stopping queue %d cid %d\n", index, fp->cid);
8807
8808         q_params.q_obj = &bnx2x_sp_obj(bp, fp).q_obj;
8809         /* We want to wait for completion in this context */
8810         __set_bit(RAMROD_COMP_WAIT, &q_params.ramrod_flags);
8811
8812         /* close tx-only connections */
8813         for (tx_index = FIRST_TX_ONLY_COS_INDEX;
8814              tx_index < fp->max_cos;
8815              tx_index++){
8816
8817                 /* ascertain this is a normal queue*/
8818                 txdata = fp->txdata_ptr[tx_index];
8819
8820                 DP(NETIF_MSG_IFDOWN, "stopping tx-only queue %d\n",
8821                                                         txdata->txq_index);
8822
8823                 /* send halt terminate on tx-only connection */
8824                 q_params.cmd = BNX2X_Q_CMD_TERMINATE;
8825                 memset(&q_params.params.terminate, 0,
8826                        sizeof(q_params.params.terminate));
8827                 q_params.params.terminate.cid_index = tx_index;
8828
8829                 rc = bnx2x_queue_state_change(bp, &q_params);
8830                 if (rc)
8831                         return rc;
8832
8833                 /* send halt terminate on tx-only connection */
8834                 q_params.cmd = BNX2X_Q_CMD_CFC_DEL;
8835                 memset(&q_params.params.cfc_del, 0,
8836                        sizeof(q_params.params.cfc_del));
8837                 q_params.params.cfc_del.cid_index = tx_index;
8838                 rc = bnx2x_queue_state_change(bp, &q_params);
8839                 if (rc)
8840                         return rc;
8841         }
8842         /* Stop the primary connection: */
8843         /* ...halt the connection */
8844         q_params.cmd = BNX2X_Q_CMD_HALT;
8845         rc = bnx2x_queue_state_change(bp, &q_params);
8846         if (rc)
8847                 return rc;
8848
8849         /* ...terminate the connection */
8850         q_params.cmd = BNX2X_Q_CMD_TERMINATE;
8851         memset(&q_params.params.terminate, 0,
8852                sizeof(q_params.params.terminate));
8853         q_params.params.terminate.cid_index = FIRST_TX_COS_INDEX;
8854         rc = bnx2x_queue_state_change(bp, &q_params);
8855         if (rc)
8856                 return rc;
8857         /* ...delete cfc entry */
8858         q_params.cmd = BNX2X_Q_CMD_CFC_DEL;
8859         memset(&q_params.params.cfc_del, 0,
8860                sizeof(q_params.params.cfc_del));
8861         q_params.params.cfc_del.cid_index = FIRST_TX_COS_INDEX;
8862         return bnx2x_queue_state_change(bp, &q_params);
8863 }
8864
8865 static void bnx2x_reset_func(struct bnx2x *bp)
8866 {
8867         int port = BP_PORT(bp);
8868         int func = BP_FUNC(bp);
8869         int i;
8870
8871         /* Disable the function in the FW */
8872         REG_WR8(bp, BAR_XSTRORM_INTMEM + XSTORM_FUNC_EN_OFFSET(func), 0);
8873         REG_WR8(bp, BAR_CSTRORM_INTMEM + CSTORM_FUNC_EN_OFFSET(func), 0);
8874         REG_WR8(bp, BAR_TSTRORM_INTMEM + TSTORM_FUNC_EN_OFFSET(func), 0);
8875         REG_WR8(bp, BAR_USTRORM_INTMEM + USTORM_FUNC_EN_OFFSET(func), 0);
8876
8877         /* FP SBs */
8878         for_each_eth_queue(bp, i) {
8879                 struct bnx2x_fastpath *fp = &bp->fp[i];
8880                 REG_WR8(bp, BAR_CSTRORM_INTMEM +
8881                            CSTORM_STATUS_BLOCK_DATA_STATE_OFFSET(fp->fw_sb_id),
8882                            SB_DISABLED);
8883         }
8884
8885         if (CNIC_LOADED(bp))
8886                 /* CNIC SB */
8887                 REG_WR8(bp, BAR_CSTRORM_INTMEM +
8888                         CSTORM_STATUS_BLOCK_DATA_STATE_OFFSET
8889                         (bnx2x_cnic_fw_sb_id(bp)), SB_DISABLED);
8890
8891         /* SP SB */
8892         REG_WR8(bp, BAR_CSTRORM_INTMEM +
8893                 CSTORM_SP_STATUS_BLOCK_DATA_STATE_OFFSET(func),
8894                 SB_DISABLED);
8895
8896         for (i = 0; i < XSTORM_SPQ_DATA_SIZE / 4; i++)
8897                 REG_WR(bp, BAR_XSTRORM_INTMEM + XSTORM_SPQ_DATA_OFFSET(func),
8898                        0);
8899
8900         /* Configure IGU */
8901         if (bp->common.int_block == INT_BLOCK_HC) {
8902                 REG_WR(bp, HC_REG_LEADING_EDGE_0 + port*8, 0);
8903                 REG_WR(bp, HC_REG_TRAILING_EDGE_0 + port*8, 0);
8904         } else {
8905                 REG_WR(bp, IGU_REG_LEADING_EDGE_LATCH, 0);
8906                 REG_WR(bp, IGU_REG_TRAILING_EDGE_LATCH, 0);
8907         }
8908
8909         if (CNIC_LOADED(bp)) {
8910                 /* Disable Timer scan */
8911                 REG_WR(bp, TM_REG_EN_LINEAR0_TIMER + port*4, 0);
8912                 /*
8913                  * Wait for at least 10ms and up to 2 second for the timers
8914                  * scan to complete
8915                  */
8916                 for (i = 0; i < 200; i++) {
8917                         usleep_range(10000, 20000);
8918                         if (!REG_RD(bp, TM_REG_LIN0_SCAN_ON + port*4))
8919                                 break;
8920                 }
8921         }
8922         /* Clear ILT */
8923         bnx2x_clear_func_ilt(bp, func);
8924
8925         /* Timers workaround bug for E2: if this is vnic-3,
8926          * we need to set the entire ilt range for this timers.
8927          */
8928         if (!CHIP_IS_E1x(bp) && BP_VN(bp) == 3) {
8929                 struct ilt_client_info ilt_cli;
8930                 /* use dummy TM client */
8931                 memset(&ilt_cli, 0, sizeof(struct ilt_client_info));
8932                 ilt_cli.start = 0;
8933                 ilt_cli.end = ILT_NUM_PAGE_ENTRIES - 1;
8934                 ilt_cli.client_num = ILT_CLIENT_TM;
8935
8936                 bnx2x_ilt_boundry_init_op(bp, &ilt_cli, 0, INITOP_CLEAR);
8937         }
8938
8939         /* this assumes that reset_port() called before reset_func()*/
8940         if (!CHIP_IS_E1x(bp))
8941                 bnx2x_pf_disable(bp);
8942
8943         bp->dmae_ready = 0;
8944 }
8945
8946 static void bnx2x_reset_port(struct bnx2x *bp)
8947 {
8948         int port = BP_PORT(bp);
8949         u32 val;
8950
8951         /* Reset physical Link */
8952         bnx2x__link_reset(bp);
8953
8954         REG_WR(bp, NIG_REG_MASK_INTERRUPT_PORT0 + port*4, 0);
8955
8956         /* Do not rcv packets to BRB */
8957         REG_WR(bp, NIG_REG_LLH0_BRB1_DRV_MASK + port*4, 0x0);
8958         /* Do not direct rcv packets that are not for MCP to the BRB */
8959         REG_WR(bp, (port ? NIG_REG_LLH1_BRB1_NOT_MCP :
8960                            NIG_REG_LLH0_BRB1_NOT_MCP), 0x0);
8961
8962         /* Configure AEU */
8963         REG_WR(bp, MISC_REG_AEU_MASK_ATTN_FUNC_0 + port*4, 0);
8964
8965         msleep(100);
8966         /* Check for BRB port occupancy */
8967         val = REG_RD(bp, BRB1_REG_PORT_NUM_OCC_BLOCKS_0 + port*4);
8968         if (val)
8969                 DP(NETIF_MSG_IFDOWN,
8970                    "BRB1 is not empty  %d blocks are occupied\n", val);
8971
8972         /* TODO: Close Doorbell port? */
8973 }
8974
8975 static int bnx2x_reset_hw(struct bnx2x *bp, u32 load_code)
8976 {
8977         struct bnx2x_func_state_params func_params = {NULL};
8978
8979         /* Prepare parameters for function state transitions */
8980         __set_bit(RAMROD_COMP_WAIT, &func_params.ramrod_flags);
8981
8982         func_params.f_obj = &bp->func_obj;
8983         func_params.cmd = BNX2X_F_CMD_HW_RESET;
8984
8985         func_params.params.hw_init.load_phase = load_code;
8986
8987         return bnx2x_func_state_change(bp, &func_params);
8988 }
8989
8990 static int bnx2x_func_stop(struct bnx2x *bp)
8991 {
8992         struct bnx2x_func_state_params func_params = {NULL};
8993         int rc;
8994
8995         /* Prepare parameters for function state transitions */
8996         __set_bit(RAMROD_COMP_WAIT, &func_params.ramrod_flags);
8997         func_params.f_obj = &bp->func_obj;
8998         func_params.cmd = BNX2X_F_CMD_STOP;
8999
9000         /*
9001          * Try to stop the function the 'good way'. If fails (in case
9002          * of a parity error during bnx2x_chip_cleanup()) and we are
9003          * not in a debug mode, perform a state transaction in order to
9004          * enable further HW_RESET transaction.
9005          */
9006         rc = bnx2x_func_state_change(bp, &func_params);
9007         if (rc) {
9008 #ifdef BNX2X_STOP_ON_ERROR
9009                 return rc;
9010 #else
9011                 BNX2X_ERR("FUNC_STOP ramrod failed. Running a dry transaction\n");
9012                 __set_bit(RAMROD_DRV_CLR_ONLY, &func_params.ramrod_flags);
9013                 return bnx2x_func_state_change(bp, &func_params);
9014 #endif
9015         }
9016
9017         return 0;
9018 }
9019
9020 /**
9021  * bnx2x_send_unload_req - request unload mode from the MCP.
9022  *
9023  * @bp:                 driver handle
9024  * @unload_mode:        requested function's unload mode
9025  *
9026  * Return unload mode returned by the MCP: COMMON, PORT or FUNC.
9027  */
9028 u32 bnx2x_send_unload_req(struct bnx2x *bp, int unload_mode)
9029 {
9030         u32 reset_code = 0;
9031         int port = BP_PORT(bp);
9032
9033         /* Select the UNLOAD request mode */
9034         if (unload_mode == UNLOAD_NORMAL)
9035                 reset_code = DRV_MSG_CODE_UNLOAD_REQ_WOL_DIS;
9036
9037         else if (bp->flags & NO_WOL_FLAG)
9038                 reset_code = DRV_MSG_CODE_UNLOAD_REQ_WOL_MCP;
9039
9040         else if (bp->wol) {
9041                 u32 emac_base = port ? GRCBASE_EMAC1 : GRCBASE_EMAC0;
9042                 u8 *mac_addr = bp->dev->dev_addr;
9043                 struct pci_dev *pdev = bp->pdev;
9044                 u32 val;
9045                 u16 pmc;
9046
9047                 /* The mac address is written to entries 1-4 to
9048                  * preserve entry 0 which is used by the PMF
9049                  */
9050                 u8 entry = (BP_VN(bp) + 1)*8;
9051
9052                 val = (mac_addr[0] << 8) | mac_addr[1];
9053                 EMAC_WR(bp, EMAC_REG_EMAC_MAC_MATCH + entry, val);
9054
9055                 val = (mac_addr[2] << 24) | (mac_addr[3] << 16) |
9056                       (mac_addr[4] << 8) | mac_addr[5];
9057                 EMAC_WR(bp, EMAC_REG_EMAC_MAC_MATCH + entry + 4, val);
9058
9059                 /* Enable the PME and clear the status */
9060                 pci_read_config_word(pdev, pdev->pm_cap + PCI_PM_CTRL, &pmc);
9061                 pmc |= PCI_PM_CTRL_PME_ENABLE | PCI_PM_CTRL_PME_STATUS;
9062                 pci_write_config_word(pdev, pdev->pm_cap + PCI_PM_CTRL, pmc);
9063
9064                 reset_code = DRV_MSG_CODE_UNLOAD_REQ_WOL_EN;
9065
9066         } else
9067                 reset_code = DRV_MSG_CODE_UNLOAD_REQ_WOL_DIS;
9068
9069         /* Send the request to the MCP */
9070         if (!BP_NOMCP(bp))
9071                 reset_code = bnx2x_fw_command(bp, reset_code, 0);
9072         else {
9073                 int path = BP_PATH(bp);
9074
9075                 DP(NETIF_MSG_IFDOWN, "NO MCP - load counts[%d]      %d, %d, %d\n",
9076                    path, bnx2x_load_count[path][0], bnx2x_load_count[path][1],
9077                    bnx2x_load_count[path][2]);
9078                 bnx2x_load_count[path][0]--;
9079                 bnx2x_load_count[path][1 + port]--;
9080                 DP(NETIF_MSG_IFDOWN, "NO MCP - new load counts[%d]  %d, %d, %d\n",
9081                    path, bnx2x_load_count[path][0], bnx2x_load_count[path][1],
9082                    bnx2x_load_count[path][2]);
9083                 if (bnx2x_load_count[path][0] == 0)
9084                         reset_code = FW_MSG_CODE_DRV_UNLOAD_COMMON;
9085                 else if (bnx2x_load_count[path][1 + port] == 0)
9086                         reset_code = FW_MSG_CODE_DRV_UNLOAD_PORT;
9087                 else
9088                         reset_code = FW_MSG_CODE_DRV_UNLOAD_FUNCTION;
9089         }
9090
9091         return reset_code;
9092 }
9093
9094 /**
9095  * bnx2x_send_unload_done - send UNLOAD_DONE command to the MCP.
9096  *
9097  * @bp:         driver handle
9098  * @keep_link:          true iff link should be kept up
9099  */
9100 void bnx2x_send_unload_done(struct bnx2x *bp, bool keep_link)
9101 {
9102         u32 reset_param = keep_link ? DRV_MSG_CODE_UNLOAD_SKIP_LINK_RESET : 0;
9103
9104         /* Report UNLOAD_DONE to MCP */
9105         if (!BP_NOMCP(bp))
9106                 bnx2x_fw_command(bp, DRV_MSG_CODE_UNLOAD_DONE, reset_param);
9107 }
9108
9109 static int bnx2x_func_wait_started(struct bnx2x *bp)
9110 {
9111         int tout = 50;
9112         int msix = (bp->flags & USING_MSIX_FLAG) ? 1 : 0;
9113
9114         if (!bp->port.pmf)
9115                 return 0;
9116
9117         /*
9118          * (assumption: No Attention from MCP at this stage)
9119          * PMF probably in the middle of TX disable/enable transaction
9120          * 1. Sync IRS for default SB
9121          * 2. Sync SP queue - this guarantees us that attention handling started
9122          * 3. Wait, that TX disable/enable transaction completes
9123          *
9124          * 1+2 guarantee that if DCBx attention was scheduled it already changed
9125          * pending bit of transaction from STARTED-->TX_STOPPED, if we already
9126          * received completion for the transaction the state is TX_STOPPED.
9127          * State will return to STARTED after completion of TX_STOPPED-->STARTED
9128          * transaction.
9129          */
9130
9131         /* make sure default SB ISR is done */
9132         if (msix)
9133                 synchronize_irq(bp->msix_table[0].vector);
9134         else
9135                 synchronize_irq(bp->pdev->irq);
9136
9137         flush_workqueue(bnx2x_wq);
9138         flush_workqueue(bnx2x_iov_wq);
9139
9140         while (bnx2x_func_get_state(bp, &bp->func_obj) !=
9141                                 BNX2X_F_STATE_STARTED && tout--)
9142                 msleep(20);
9143
9144         if (bnx2x_func_get_state(bp, &bp->func_obj) !=
9145                                                 BNX2X_F_STATE_STARTED) {
9146 #ifdef BNX2X_STOP_ON_ERROR
9147                 BNX2X_ERR("Wrong function state\n");
9148                 return -EBUSY;
9149 #else
9150                 /*
9151                  * Failed to complete the transaction in a "good way"
9152                  * Force both transactions with CLR bit
9153                  */
9154                 struct bnx2x_func_state_params func_params = {NULL};
9155
9156                 DP(NETIF_MSG_IFDOWN,
9157                    "Hmmm... Unexpected function state! Forcing STARTED-->TX_STOPPED-->STARTED\n");
9158
9159                 func_params.f_obj = &bp->func_obj;
9160                 __set_bit(RAMROD_DRV_CLR_ONLY,
9161                                         &func_params.ramrod_flags);
9162
9163                 /* STARTED-->TX_ST0PPED */
9164                 func_params.cmd = BNX2X_F_CMD_TX_STOP;
9165                 bnx2x_func_state_change(bp, &func_params);
9166
9167                 /* TX_ST0PPED-->STARTED */
9168                 func_params.cmd = BNX2X_F_CMD_TX_START;
9169                 return bnx2x_func_state_change(bp, &func_params);
9170 #endif
9171         }
9172
9173         return 0;
9174 }
9175
9176 static void bnx2x_disable_ptp(struct bnx2x *bp)
9177 {
9178         int port = BP_PORT(bp);
9179
9180         /* Disable sending PTP packets to host */
9181         REG_WR(bp, port ? NIG_REG_P1_LLH_PTP_TO_HOST :
9182                NIG_REG_P0_LLH_PTP_TO_HOST, 0x0);
9183
9184         /* Reset PTP event detection rules */
9185         REG_WR(bp, port ? NIG_REG_P1_LLH_PTP_PARAM_MASK :
9186                NIG_REG_P0_LLH_PTP_PARAM_MASK, 0x7FF);
9187         REG_WR(bp, port ? NIG_REG_P1_LLH_PTP_RULE_MASK :
9188                NIG_REG_P0_LLH_PTP_RULE_MASK, 0x3FFF);
9189         REG_WR(bp, port ? NIG_REG_P1_TLLH_PTP_PARAM_MASK :
9190                NIG_REG_P0_TLLH_PTP_PARAM_MASK, 0x7FF);
9191         REG_WR(bp, port ? NIG_REG_P1_TLLH_PTP_RULE_MASK :
9192                NIG_REG_P0_TLLH_PTP_RULE_MASK, 0x3FFF);
9193
9194         /* Disable the PTP feature */
9195         REG_WR(bp, port ? NIG_REG_P1_PTP_EN :
9196                NIG_REG_P0_PTP_EN, 0x0);
9197 }
9198
9199 /* Called during unload, to stop PTP-related stuff */
9200 static void bnx2x_stop_ptp(struct bnx2x *bp)
9201 {
9202         /* Cancel PTP work queue. Should be done after the Tx queues are
9203          * drained to prevent additional scheduling.
9204          */
9205         cancel_work_sync(&bp->ptp_task);
9206
9207         if (bp->ptp_tx_skb) {
9208                 dev_kfree_skb_any(bp->ptp_tx_skb);
9209                 bp->ptp_tx_skb = NULL;
9210         }
9211
9212         /* Disable PTP in HW */
9213         bnx2x_disable_ptp(bp);
9214
9215         DP(BNX2X_MSG_PTP, "PTP stop ended successfully\n");
9216 }
9217
9218 void bnx2x_chip_cleanup(struct bnx2x *bp, int unload_mode, bool keep_link)
9219 {
9220         int port = BP_PORT(bp);
9221         int i, rc = 0;
9222         u8 cos;
9223         struct bnx2x_mcast_ramrod_params rparam = {NULL};
9224         u32 reset_code;
9225
9226         /* Wait until tx fastpath tasks complete */
9227         for_each_tx_queue(bp, i) {
9228                 struct bnx2x_fastpath *fp = &bp->fp[i];
9229
9230                 for_each_cos_in_tx_queue(fp, cos)
9231                         rc = bnx2x_clean_tx_queue(bp, fp->txdata_ptr[cos]);
9232 #ifdef BNX2X_STOP_ON_ERROR
9233                 if (rc)
9234                         return;
9235 #endif
9236         }
9237
9238         /* Give HW time to discard old tx messages */
9239         usleep_range(1000, 2000);
9240
9241         /* Clean all ETH MACs */
9242         rc = bnx2x_del_all_macs(bp, &bp->sp_objs[0].mac_obj, BNX2X_ETH_MAC,
9243                                 false);
9244         if (rc < 0)
9245                 BNX2X_ERR("Failed to delete all ETH macs: %d\n", rc);
9246
9247         /* Clean up UC list  */
9248         rc = bnx2x_del_all_macs(bp, &bp->sp_objs[0].mac_obj, BNX2X_UC_LIST_MAC,
9249                                 true);
9250         if (rc < 0)
9251                 BNX2X_ERR("Failed to schedule DEL commands for UC MACs list: %d\n",
9252                           rc);
9253
9254         /* Disable LLH */
9255         if (!CHIP_IS_E1(bp))
9256                 REG_WR(bp, NIG_REG_LLH0_FUNC_EN + port*8, 0);
9257
9258         /* Set "drop all" (stop Rx).
9259          * We need to take a netif_addr_lock() here in order to prevent
9260          * a race between the completion code and this code.
9261          */
9262         netif_addr_lock_bh(bp->dev);
9263         /* Schedule the rx_mode command */
9264         if (test_bit(BNX2X_FILTER_RX_MODE_PENDING, &bp->sp_state))
9265                 set_bit(BNX2X_FILTER_RX_MODE_SCHED, &bp->sp_state);
9266         else
9267                 bnx2x_set_storm_rx_mode(bp);
9268
9269         /* Cleanup multicast configuration */
9270         rparam.mcast_obj = &bp->mcast_obj;
9271         rc = bnx2x_config_mcast(bp, &rparam, BNX2X_MCAST_CMD_DEL);
9272         if (rc < 0)
9273                 BNX2X_ERR("Failed to send DEL multicast command: %d\n", rc);
9274
9275         netif_addr_unlock_bh(bp->dev);
9276
9277         bnx2x_iov_chip_cleanup(bp);
9278
9279         /*
9280          * Send the UNLOAD_REQUEST to the MCP. This will return if
9281          * this function should perform FUNC, PORT or COMMON HW
9282          * reset.
9283          */
9284         reset_code = bnx2x_send_unload_req(bp, unload_mode);
9285
9286         /*
9287          * (assumption: No Attention from MCP at this stage)
9288          * PMF probably in the middle of TX disable/enable transaction
9289          */
9290         rc = bnx2x_func_wait_started(bp);
9291         if (rc) {
9292                 BNX2X_ERR("bnx2x_func_wait_started failed\n");
9293 #ifdef BNX2X_STOP_ON_ERROR
9294                 return;
9295 #endif
9296         }
9297
9298         /* Close multi and leading connections
9299          * Completions for ramrods are collected in a synchronous way
9300          */
9301         for_each_eth_queue(bp, i)
9302                 if (bnx2x_stop_queue(bp, i))
9303 #ifdef BNX2X_STOP_ON_ERROR
9304                         return;
9305 #else
9306                         goto unload_error;
9307 #endif
9308
9309         if (CNIC_LOADED(bp)) {
9310                 for_each_cnic_queue(bp, i)
9311                         if (bnx2x_stop_queue(bp, i))
9312 #ifdef BNX2X_STOP_ON_ERROR
9313                                 return;
9314 #else
9315                                 goto unload_error;
9316 #endif
9317         }
9318
9319         /* If SP settings didn't get completed so far - something
9320          * very wrong has happen.
9321          */
9322         if (!bnx2x_wait_sp_comp(bp, ~0x0UL))
9323                 BNX2X_ERR("Hmmm... Common slow path ramrods got stuck!\n");
9324
9325 #ifndef BNX2X_STOP_ON_ERROR
9326 unload_error:
9327 #endif
9328         rc = bnx2x_func_stop(bp);
9329         if (rc) {
9330                 BNX2X_ERR("Function stop failed!\n");
9331 #ifdef BNX2X_STOP_ON_ERROR
9332                 return;
9333 #endif
9334         }
9335
9336         /* stop_ptp should be after the Tx queues are drained to prevent
9337          * scheduling to the cancelled PTP work queue. It should also be after
9338          * function stop ramrod is sent, since as part of this ramrod FW access
9339          * PTP registers.
9340          */
9341         if (bp->flags & PTP_SUPPORTED)
9342                 bnx2x_stop_ptp(bp);
9343
9344         /* Disable HW interrupts, NAPI */
9345         bnx2x_netif_stop(bp, 1);
9346         /* Delete all NAPI objects */
9347         bnx2x_del_all_napi(bp);
9348         if (CNIC_LOADED(bp))
9349                 bnx2x_del_all_napi_cnic(bp);
9350
9351         /* Release IRQs */
9352         bnx2x_free_irq(bp);
9353
9354         /* Reset the chip */
9355         rc = bnx2x_reset_hw(bp, reset_code);
9356         if (rc)
9357                 BNX2X_ERR("HW_RESET failed\n");
9358
9359         /* Report UNLOAD_DONE to MCP */
9360         bnx2x_send_unload_done(bp, keep_link);
9361 }
9362
9363 void bnx2x_disable_close_the_gate(struct bnx2x *bp)
9364 {
9365         u32 val;
9366
9367         DP(NETIF_MSG_IFDOWN, "Disabling \"close the gates\"\n");
9368
9369         if (CHIP_IS_E1(bp)) {
9370                 int port = BP_PORT(bp);
9371                 u32 addr = port ? MISC_REG_AEU_MASK_ATTN_FUNC_1 :
9372                         MISC_REG_AEU_MASK_ATTN_FUNC_0;
9373
9374                 val = REG_RD(bp, addr);
9375                 val &= ~(0x300);
9376                 REG_WR(bp, addr, val);
9377         } else {
9378                 val = REG_RD(bp, MISC_REG_AEU_GENERAL_MASK);
9379                 val &= ~(MISC_AEU_GENERAL_MASK_REG_AEU_PXP_CLOSE_MASK |
9380                          MISC_AEU_GENERAL_MASK_REG_AEU_NIG_CLOSE_MASK);
9381                 REG_WR(bp, MISC_REG_AEU_GENERAL_MASK, val);
9382         }
9383 }
9384
9385 /* Close gates #2, #3 and #4: */
9386 static void bnx2x_set_234_gates(struct bnx2x *bp, bool close)
9387 {
9388         u32 val;
9389
9390         /* Gates #2 and #4a are closed/opened for "not E1" only */
9391         if (!CHIP_IS_E1(bp)) {
9392                 /* #4 */
9393                 REG_WR(bp, PXP_REG_HST_DISCARD_DOORBELLS, !!close);
9394                 /* #2 */
9395                 REG_WR(bp, PXP_REG_HST_DISCARD_INTERNAL_WRITES, !!close);
9396         }
9397
9398         /* #3 */
9399         if (CHIP_IS_E1x(bp)) {
9400                 /* Prevent interrupts from HC on both ports */
9401                 val = REG_RD(bp, HC_REG_CONFIG_1);
9402                 REG_WR(bp, HC_REG_CONFIG_1,
9403                        (!close) ? (val | HC_CONFIG_1_REG_BLOCK_DISABLE_1) :
9404                        (val & ~(u32)HC_CONFIG_1_REG_BLOCK_DISABLE_1));
9405
9406                 val = REG_RD(bp, HC_REG_CONFIG_0);
9407                 REG_WR(bp, HC_REG_CONFIG_0,
9408                        (!close) ? (val | HC_CONFIG_0_REG_BLOCK_DISABLE_0) :
9409                        (val & ~(u32)HC_CONFIG_0_REG_BLOCK_DISABLE_0));
9410         } else {
9411                 /* Prevent incoming interrupts in IGU */
9412                 val = REG_RD(bp, IGU_REG_BLOCK_CONFIGURATION);
9413
9414                 REG_WR(bp, IGU_REG_BLOCK_CONFIGURATION,
9415                        (!close) ?
9416                        (val | IGU_BLOCK_CONFIGURATION_REG_BLOCK_ENABLE) :
9417                        (val & ~(u32)IGU_BLOCK_CONFIGURATION_REG_BLOCK_ENABLE));
9418         }
9419
9420         DP(NETIF_MSG_HW | NETIF_MSG_IFUP, "%s gates #2, #3 and #4\n",
9421                 close ? "closing" : "opening");
9422         mmiowb();
9423 }
9424
9425 #define SHARED_MF_CLP_MAGIC  0x80000000 /* `magic' bit */
9426
9427 static void bnx2x_clp_reset_prep(struct bnx2x *bp, u32 *magic_val)
9428 {
9429         /* Do some magic... */
9430         u32 val = MF_CFG_RD(bp, shared_mf_config.clp_mb);
9431         *magic_val = val & SHARED_MF_CLP_MAGIC;
9432         MF_CFG_WR(bp, shared_mf_config.clp_mb, val | SHARED_MF_CLP_MAGIC);
9433 }
9434
9435 /**
9436  * bnx2x_clp_reset_done - restore the value of the `magic' bit.
9437  *
9438  * @bp:         driver handle
9439  * @magic_val:  old value of the `magic' bit.
9440  */
9441 static void bnx2x_clp_reset_done(struct bnx2x *bp, u32 magic_val)
9442 {
9443         /* Restore the `magic' bit value... */
9444         u32 val = MF_CFG_RD(bp, shared_mf_config.clp_mb);
9445         MF_CFG_WR(bp, shared_mf_config.clp_mb,
9446                 (val & (~SHARED_MF_CLP_MAGIC)) | magic_val);
9447 }
9448
9449 /**
9450  * bnx2x_reset_mcp_prep - prepare for MCP reset.
9451  *
9452  * @bp:         driver handle
9453  * @magic_val:  old value of 'magic' bit.
9454  *
9455  * Takes care of CLP configurations.
9456  */
9457 static void bnx2x_reset_mcp_prep(struct bnx2x *bp, u32 *magic_val)
9458 {
9459         u32 shmem;
9460         u32 validity_offset;
9461
9462         DP(NETIF_MSG_HW | NETIF_MSG_IFUP, "Starting\n");
9463
9464         /* Set `magic' bit in order to save MF config */
9465         if (!CHIP_IS_E1(bp))
9466                 bnx2x_clp_reset_prep(bp, magic_val);
9467
9468         /* Get shmem offset */
9469         shmem = REG_RD(bp, MISC_REG_SHARED_MEM_ADDR);
9470         validity_offset =
9471                 offsetof(struct shmem_region, validity_map[BP_PORT(bp)]);
9472
9473         /* Clear validity map flags */
9474         if (shmem > 0)
9475                 REG_WR(bp, shmem + validity_offset, 0);
9476 }
9477
9478 #define MCP_TIMEOUT      5000   /* 5 seconds (in ms) */
9479 #define MCP_ONE_TIMEOUT  100    /* 100 ms */
9480
9481 /**
9482  * bnx2x_mcp_wait_one - wait for MCP_ONE_TIMEOUT
9483  *
9484  * @bp: driver handle
9485  */
9486 static void bnx2x_mcp_wait_one(struct bnx2x *bp)
9487 {
9488         /* special handling for emulation and FPGA,
9489            wait 10 times longer */
9490         if (CHIP_REV_IS_SLOW(bp))
9491                 msleep(MCP_ONE_TIMEOUT*10);
9492         else
9493                 msleep(MCP_ONE_TIMEOUT);
9494 }
9495
9496 /*
9497  * initializes bp->common.shmem_base and waits for validity signature to appear
9498  */
9499 static int bnx2x_init_shmem(struct bnx2x *bp)
9500 {
9501         int cnt = 0;
9502         u32 val = 0;
9503
9504         do {
9505                 bp->common.shmem_base = REG_RD(bp, MISC_REG_SHARED_MEM_ADDR);
9506                 if (bp->common.shmem_base) {
9507                         val = SHMEM_RD(bp, validity_map[BP_PORT(bp)]);
9508                         if (val & SHR_MEM_VALIDITY_MB)
9509                                 return 0;
9510                 }
9511
9512                 bnx2x_mcp_wait_one(bp);
9513
9514         } while (cnt++ < (MCP_TIMEOUT / MCP_ONE_TIMEOUT));
9515
9516         BNX2X_ERR("BAD MCP validity signature\n");
9517
9518         return -ENODEV;
9519 }
9520
9521 static int bnx2x_reset_mcp_comp(struct bnx2x *bp, u32 magic_val)
9522 {
9523         int rc = bnx2x_init_shmem(bp);
9524
9525         /* Restore the `magic' bit value */
9526         if (!CHIP_IS_E1(bp))
9527                 bnx2x_clp_reset_done(bp, magic_val);
9528
9529         return rc;
9530 }
9531
9532 static void bnx2x_pxp_prep(struct bnx2x *bp)
9533 {
9534         if (!CHIP_IS_E1(bp)) {
9535                 REG_WR(bp, PXP2_REG_RD_START_INIT, 0);
9536                 REG_WR(bp, PXP2_REG_RQ_RBC_DONE, 0);
9537                 mmiowb();
9538         }
9539 }
9540
9541 /*
9542  * Reset the whole chip except for:
9543  *      - PCIE core
9544  *      - PCI Glue, PSWHST, PXP/PXP2 RF (all controlled by
9545  *              one reset bit)
9546  *      - IGU
9547  *      - MISC (including AEU)
9548  *      - GRC
9549  *      - RBCN, RBCP
9550  */
9551 static void bnx2x_process_kill_chip_reset(struct bnx2x *bp, bool global)
9552 {
9553         u32 not_reset_mask1, reset_mask1, not_reset_mask2, reset_mask2;
9554         u32 global_bits2, stay_reset2;
9555
9556         /*
9557          * Bits that have to be set in reset_mask2 if we want to reset 'global'
9558          * (per chip) blocks.
9559          */
9560         global_bits2 =
9561                 MISC_REGISTERS_RESET_REG_2_RST_MCP_N_RESET_CMN_CPU |
9562                 MISC_REGISTERS_RESET_REG_2_RST_MCP_N_RESET_CMN_CORE;
9563
9564         /* Don't reset the following blocks.
9565          * Important: per port blocks (such as EMAC, BMAC, UMAC) can't be
9566          *            reset, as in 4 port device they might still be owned
9567          *            by the MCP (there is only one leader per path).
9568          */
9569         not_reset_mask1 =
9570                 MISC_REGISTERS_RESET_REG_1_RST_HC |
9571                 MISC_REGISTERS_RESET_REG_1_RST_PXPV |
9572                 MISC_REGISTERS_RESET_REG_1_RST_PXP;
9573
9574         not_reset_mask2 =
9575                 MISC_REGISTERS_RESET_REG_2_RST_PCI_MDIO |
9576                 MISC_REGISTERS_RESET_REG_2_RST_EMAC0_HARD_CORE |
9577                 MISC_REGISTERS_RESET_REG_2_RST_EMAC1_HARD_CORE |
9578                 MISC_REGISTERS_RESET_REG_2_RST_MISC_CORE |
9579                 MISC_REGISTERS_RESET_REG_2_RST_RBCN |
9580                 MISC_REGISTERS_RESET_REG_2_RST_GRC  |
9581                 MISC_REGISTERS_RESET_REG_2_RST_MCP_N_RESET_REG_HARD_CORE |
9582                 MISC_REGISTERS_RESET_REG_2_RST_MCP_N_HARD_CORE_RST_B |
9583                 MISC_REGISTERS_RESET_REG_2_RST_ATC |
9584                 MISC_REGISTERS_RESET_REG_2_PGLC |
9585                 MISC_REGISTERS_RESET_REG_2_RST_BMAC0 |
9586                 MISC_REGISTERS_RESET_REG_2_RST_BMAC1 |
9587                 MISC_REGISTERS_RESET_REG_2_RST_EMAC0 |
9588                 MISC_REGISTERS_RESET_REG_2_RST_EMAC1 |
9589                 MISC_REGISTERS_RESET_REG_2_UMAC0 |
9590                 MISC_REGISTERS_RESET_REG_2_UMAC1;
9591
9592         /*
9593          * Keep the following blocks in reset:
9594          *  - all xxMACs are handled by the bnx2x_link code.
9595          */
9596         stay_reset2 =
9597                 MISC_REGISTERS_RESET_REG_2_XMAC |
9598                 MISC_REGISTERS_RESET_REG_2_XMAC_SOFT;
9599
9600         /* Full reset masks according to the chip */
9601         reset_mask1 = 0xffffffff;
9602
9603         if (CHIP_IS_E1(bp))
9604                 reset_mask2 = 0xffff;
9605         else if (CHIP_IS_E1H(bp))
9606                 reset_mask2 = 0x1ffff;
9607         else if (CHIP_IS_E2(bp))
9608                 reset_mask2 = 0xfffff;
9609         else /* CHIP_IS_E3 */
9610                 reset_mask2 = 0x3ffffff;
9611
9612         /* Don't reset global blocks unless we need to */
9613         if (!global)
9614                 reset_mask2 &= ~global_bits2;
9615
9616         /*
9617          * In case of attention in the QM, we need to reset PXP
9618          * (MISC_REGISTERS_RESET_REG_2_RST_PXP_RQ_RD_WR) before QM
9619          * because otherwise QM reset would release 'close the gates' shortly
9620          * before resetting the PXP, then the PSWRQ would send a write
9621          * request to PGLUE. Then when PXP is reset, PGLUE would try to
9622          * read the payload data from PSWWR, but PSWWR would not
9623          * respond. The write queue in PGLUE would stuck, dmae commands
9624          * would not return. Therefore it's important to reset the second
9625          * reset register (containing the
9626          * MISC_REGISTERS_RESET_REG_2_RST_PXP_RQ_RD_WR bit) before the
9627          * first one (containing the MISC_REGISTERS_RESET_REG_1_RST_QM
9628          * bit).
9629          */
9630         REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR,
9631                reset_mask2 & (~not_reset_mask2));
9632
9633         REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_CLEAR,
9634                reset_mask1 & (~not_reset_mask1));
9635
9636         barrier();
9637         mmiowb();
9638
9639         REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_SET,
9640                reset_mask2 & (~stay_reset2));
9641
9642         barrier();
9643         mmiowb();
9644
9645         REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_SET, reset_mask1);
9646         mmiowb();
9647 }
9648
9649 /**
9650  * bnx2x_er_poll_igu_vq - poll for pending writes bit.
9651  * It should get cleared in no more than 1s.
9652  *
9653  * @bp: driver handle
9654  *
9655  * It should get cleared in no more than 1s. Returns 0 if
9656  * pending writes bit gets cleared.
9657  */
9658 static int bnx2x_er_poll_igu_vq(struct bnx2x *bp)
9659 {
9660         u32 cnt = 1000;
9661         u32 pend_bits = 0;
9662
9663         do {
9664                 pend_bits  = REG_RD(bp, IGU_REG_PENDING_BITS_STATUS);
9665
9666                 if (pend_bits == 0)
9667                         break;
9668
9669                 usleep_range(1000, 2000);
9670         } while (cnt-- > 0);
9671
9672         if (cnt <= 0) {
9673                 BNX2X_ERR("Still pending IGU requests pend_bits=%x!\n",
9674                           pend_bits);
9675                 return -EBUSY;
9676         }
9677
9678         return 0;
9679 }
9680
9681 static int bnx2x_process_kill(struct bnx2x *bp, bool global)
9682 {
9683         int cnt = 1000;
9684         u32 val = 0;
9685         u32 sr_cnt, blk_cnt, port_is_idle_0, port_is_idle_1, pgl_exp_rom2;
9686         u32 tags_63_32 = 0;
9687
9688         /* Empty the Tetris buffer, wait for 1s */
9689         do {
9690                 sr_cnt  = REG_RD(bp, PXP2_REG_RD_SR_CNT);
9691                 blk_cnt = REG_RD(bp, PXP2_REG_RD_BLK_CNT);
9692                 port_is_idle_0 = REG_RD(bp, PXP2_REG_RD_PORT_IS_IDLE_0);
9693                 port_is_idle_1 = REG_RD(bp, PXP2_REG_RD_PORT_IS_IDLE_1);
9694                 pgl_exp_rom2 = REG_RD(bp, PXP2_REG_PGL_EXP_ROM2);
9695                 if (CHIP_IS_E3(bp))
9696                         tags_63_32 = REG_RD(bp, PGLUE_B_REG_TAGS_63_32);
9697
9698                 if ((sr_cnt == 0x7e) && (blk_cnt == 0xa0) &&
9699                     ((port_is_idle_0 & 0x1) == 0x1) &&
9700                     ((port_is_idle_1 & 0x1) == 0x1) &&
9701                     (pgl_exp_rom2 == 0xffffffff) &&
9702                     (!CHIP_IS_E3(bp) || (tags_63_32 == 0xffffffff)))
9703                         break;
9704                 usleep_range(1000, 2000);
9705         } while (cnt-- > 0);
9706
9707         if (cnt <= 0) {
9708                 BNX2X_ERR("Tetris buffer didn't get empty or there are still outstanding read requests after 1s!\n");
9709                 BNX2X_ERR("sr_cnt=0x%08x, blk_cnt=0x%08x, port_is_idle_0=0x%08x, port_is_idle_1=0x%08x, pgl_exp_rom2=0x%08x\n",
9710                           sr_cnt, blk_cnt, port_is_idle_0, port_is_idle_1,
9711                           pgl_exp_rom2);
9712                 return -EAGAIN;
9713         }
9714
9715         barrier();
9716
9717         /* Close gates #2, #3 and #4 */
9718         bnx2x_set_234_gates(bp, true);
9719
9720         /* Poll for IGU VQs for 57712 and newer chips */
9721         if (!CHIP_IS_E1x(bp) && bnx2x_er_poll_igu_vq(bp))
9722                 return -EAGAIN;
9723
9724         /* TBD: Indicate that "process kill" is in progress to MCP */
9725
9726         /* Clear "unprepared" bit */
9727         REG_WR(bp, MISC_REG_UNPREPARED, 0);
9728         barrier();
9729
9730         /* Make sure all is written to the chip before the reset */
9731         mmiowb();
9732
9733         /* Wait for 1ms to empty GLUE and PCI-E core queues,
9734          * PSWHST, GRC and PSWRD Tetris buffer.
9735          */
9736         usleep_range(1000, 2000);
9737
9738         /* Prepare to chip reset: */
9739         /* MCP */
9740         if (global)
9741                 bnx2x_reset_mcp_prep(bp, &val);
9742
9743         /* PXP */
9744         bnx2x_pxp_prep(bp);
9745         barrier();
9746
9747         /* reset the chip */
9748         bnx2x_process_kill_chip_reset(bp, global);
9749         barrier();
9750
9751         /* clear errors in PGB */
9752         if (!CHIP_IS_E1x(bp))
9753                 REG_WR(bp, PGLUE_B_REG_LATCHED_ERRORS_CLR, 0x7f);
9754
9755         /* Recover after reset: */
9756         /* MCP */
9757         if (global && bnx2x_reset_mcp_comp(bp, val))
9758                 return -EAGAIN;
9759
9760         /* TBD: Add resetting the NO_MCP mode DB here */
9761
9762         /* Open the gates #2, #3 and #4 */
9763         bnx2x_set_234_gates(bp, false);
9764
9765         /* TBD: IGU/AEU preparation bring back the AEU/IGU to a
9766          * reset state, re-enable attentions. */
9767
9768         return 0;
9769 }
9770
9771 static int bnx2x_leader_reset(struct bnx2x *bp)
9772 {
9773         int rc = 0;
9774         bool global = bnx2x_reset_is_global(bp);
9775         u32 load_code;
9776
9777         /* if not going to reset MCP - load "fake" driver to reset HW while
9778          * driver is owner of the HW
9779          */
9780         if (!global && !BP_NOMCP(bp)) {
9781                 load_code = bnx2x_fw_command(bp, DRV_MSG_CODE_LOAD_REQ,
9782                                              DRV_MSG_CODE_LOAD_REQ_WITH_LFA);
9783                 if (!load_code) {
9784                         BNX2X_ERR("MCP response failure, aborting\n");
9785                         rc = -EAGAIN;
9786                         goto exit_leader_reset;
9787                 }
9788                 if ((load_code != FW_MSG_CODE_DRV_LOAD_COMMON_CHIP) &&
9789                     (load_code != FW_MSG_CODE_DRV_LOAD_COMMON)) {
9790                         BNX2X_ERR("MCP unexpected resp, aborting\n");
9791                         rc = -EAGAIN;
9792                         goto exit_leader_reset2;
9793                 }
9794                 load_code = bnx2x_fw_command(bp, DRV_MSG_CODE_LOAD_DONE, 0);
9795                 if (!load_code) {
9796                         BNX2X_ERR("MCP response failure, aborting\n");
9797                         rc = -EAGAIN;
9798                         goto exit_leader_reset2;
9799                 }
9800         }
9801
9802         /* Try to recover after the failure */
9803         if (bnx2x_process_kill(bp, global)) {
9804                 BNX2X_ERR("Something bad had happen on engine %d! Aii!\n",
9805                           BP_PATH(bp));
9806                 rc = -EAGAIN;
9807                 goto exit_leader_reset2;
9808         }
9809
9810         /*
9811          * Clear RESET_IN_PROGRES and RESET_GLOBAL bits and update the driver
9812          * state.
9813          */
9814         bnx2x_set_reset_done(bp);
9815         if (global)
9816                 bnx2x_clear_reset_global(bp);
9817
9818 exit_leader_reset2:
9819         /* unload "fake driver" if it was loaded */
9820         if (!global && !BP_NOMCP(bp)) {
9821                 bnx2x_fw_command(bp, DRV_MSG_CODE_UNLOAD_REQ_WOL_MCP, 0);
9822                 bnx2x_fw_command(bp, DRV_MSG_CODE_UNLOAD_DONE, 0);
9823         }
9824 exit_leader_reset:
9825         bp->is_leader = 0;
9826         bnx2x_release_leader_lock(bp);
9827         smp_mb();
9828         return rc;
9829 }
9830
9831 static void bnx2x_recovery_failed(struct bnx2x *bp)
9832 {
9833         netdev_err(bp->dev, "Recovery has failed. Power cycle is needed.\n");
9834
9835         /* Disconnect this device */
9836         netif_device_detach(bp->dev);
9837
9838         /*
9839          * Block ifup for all function on this engine until "process kill"
9840          * or power cycle.
9841          */
9842         bnx2x_set_reset_in_progress(bp);
9843
9844         /* Shut down the power */
9845         bnx2x_set_power_state(bp, PCI_D3hot);
9846
9847         bp->recovery_state = BNX2X_RECOVERY_FAILED;
9848
9849         smp_mb();
9850 }
9851
9852 /*
9853  * Assumption: runs under rtnl lock. This together with the fact
9854  * that it's called only from bnx2x_sp_rtnl() ensure that it
9855  * will never be called when netif_running(bp->dev) is false.
9856  */
9857 static void bnx2x_parity_recover(struct bnx2x *bp)
9858 {
9859         bool global = false;
9860         u32 error_recovered, error_unrecovered;
9861         bool is_parity;
9862
9863         DP(NETIF_MSG_HW, "Handling parity\n");
9864         while (1) {
9865                 switch (bp->recovery_state) {
9866                 case BNX2X_RECOVERY_INIT:
9867                         DP(NETIF_MSG_HW, "State is BNX2X_RECOVERY_INIT\n");
9868                         is_parity = bnx2x_chk_parity_attn(bp, &global, false);
9869                         WARN_ON(!is_parity);
9870
9871                         /* Try to get a LEADER_LOCK HW lock */
9872                         if (bnx2x_trylock_leader_lock(bp)) {
9873                                 bnx2x_set_reset_in_progress(bp);
9874                                 /*
9875                                  * Check if there is a global attention and if
9876                                  * there was a global attention, set the global
9877                                  * reset bit.
9878                                  */
9879
9880                                 if (global)
9881                                         bnx2x_set_reset_global(bp);
9882
9883                                 bp->is_leader = 1;
9884                         }
9885
9886                         /* Stop the driver */
9887                         /* If interface has been removed - break */
9888                         if (bnx2x_nic_unload(bp, UNLOAD_RECOVERY, false))
9889                                 return;
9890
9891                         bp->recovery_state = BNX2X_RECOVERY_WAIT;
9892
9893                         /* Ensure "is_leader", MCP command sequence and
9894                          * "recovery_state" update values are seen on other
9895                          * CPUs.
9896                          */
9897                         smp_mb();
9898                         break;
9899
9900                 case BNX2X_RECOVERY_WAIT:
9901                         DP(NETIF_MSG_HW, "State is BNX2X_RECOVERY_WAIT\n");
9902                         if (bp->is_leader) {
9903                                 int other_engine = BP_PATH(bp) ? 0 : 1;
9904                                 bool other_load_status =
9905                                         bnx2x_get_load_status(bp, other_engine);
9906                                 bool load_status =
9907                                         bnx2x_get_load_status(bp, BP_PATH(bp));
9908                                 global = bnx2x_reset_is_global(bp);
9909
9910                                 /*
9911                                  * In case of a parity in a global block, let
9912                                  * the first leader that performs a
9913                                  * leader_reset() reset the global blocks in
9914                                  * order to clear global attentions. Otherwise
9915                                  * the gates will remain closed for that
9916                                  * engine.
9917                                  */
9918                                 if (load_status ||
9919                                     (global && other_load_status)) {
9920                                         /* Wait until all other functions get
9921                                          * down.
9922                                          */
9923                                         schedule_delayed_work(&bp->sp_rtnl_task,
9924                                                                 HZ/10);
9925                                         return;
9926                                 } else {
9927                                         /* If all other functions got down -
9928                                          * try to bring the chip back to
9929                                          * normal. In any case it's an exit
9930                                          * point for a leader.
9931                                          */
9932                                         if (bnx2x_leader_reset(bp)) {
9933                                                 bnx2x_recovery_failed(bp);
9934                                                 return;
9935                                         }
9936
9937                                         /* If we are here, means that the
9938                                          * leader has succeeded and doesn't
9939                                          * want to be a leader any more. Try
9940                                          * to continue as a none-leader.
9941                                          */
9942                                         break;
9943                                 }
9944                         } else { /* non-leader */
9945                                 if (!bnx2x_reset_is_done(bp, BP_PATH(bp))) {
9946                                         /* Try to get a LEADER_LOCK HW lock as
9947                                          * long as a former leader may have
9948                                          * been unloaded by the user or
9949                                          * released a leadership by another
9950                                          * reason.
9951                                          */
9952                                         if (bnx2x_trylock_leader_lock(bp)) {
9953                                                 /* I'm a leader now! Restart a
9954                                                  * switch case.
9955                                                  */
9956                                                 bp->is_leader = 1;
9957                                                 break;
9958                                         }
9959
9960                                         schedule_delayed_work(&bp->sp_rtnl_task,
9961                                                                 HZ/10);
9962                                         return;
9963
9964                                 } else {
9965                                         /*
9966                                          * If there was a global attention, wait
9967                                          * for it to be cleared.
9968                                          */
9969                                         if (bnx2x_reset_is_global(bp)) {
9970                                                 schedule_delayed_work(
9971                                                         &bp->sp_rtnl_task,
9972                                                         HZ/10);
9973                                                 return;
9974                                         }
9975
9976                                         error_recovered =
9977                                           bp->eth_stats.recoverable_error;
9978                                         error_unrecovered =
9979                                           bp->eth_stats.unrecoverable_error;
9980                                         bp->recovery_state =
9981                                                 BNX2X_RECOVERY_NIC_LOADING;
9982                                         if (bnx2x_nic_load(bp, LOAD_NORMAL)) {
9983                                                 error_unrecovered++;
9984                                                 netdev_err(bp->dev,
9985                                                            "Recovery failed. Power cycle needed\n");
9986                                                 /* Disconnect this device */
9987                                                 netif_device_detach(bp->dev);
9988                                                 /* Shut down the power */
9989                                                 bnx2x_set_power_state(
9990                                                         bp, PCI_D3hot);
9991                                                 smp_mb();
9992                                         } else {
9993                                                 bp->recovery_state =
9994                                                         BNX2X_RECOVERY_DONE;
9995                                                 error_recovered++;
9996                                                 smp_mb();
9997                                         }
9998                                         bp->eth_stats.recoverable_error =
9999                                                 error_recovered;
10000                                         bp->eth_stats.unrecoverable_error =
10001                                                 error_unrecovered;
10002
10003                                         return;
10004                                 }
10005                         }
10006                 default:
10007                         return;
10008                 }
10009         }
10010 }
10011
10012 static int bnx2x_close(struct net_device *dev);
10013
10014 /* bnx2x_nic_unload() flushes the bnx2x_wq, thus reset task is
10015  * scheduled on a general queue in order to prevent a dead lock.
10016  */
10017 static void bnx2x_sp_rtnl_task(struct work_struct *work)
10018 {
10019         struct bnx2x *bp = container_of(work, struct bnx2x, sp_rtnl_task.work);
10020
10021         rtnl_lock();
10022
10023         if (!netif_running(bp->dev)) {
10024                 rtnl_unlock();
10025                 return;
10026         }
10027
10028         if (unlikely(bp->recovery_state != BNX2X_RECOVERY_DONE)) {
10029 #ifdef BNX2X_STOP_ON_ERROR
10030                 BNX2X_ERR("recovery flow called but STOP_ON_ERROR defined so reset not done to allow debug dump,\n"
10031                           "you will need to reboot when done\n");
10032                 goto sp_rtnl_not_reset;
10033 #endif
10034                 /*
10035                  * Clear all pending SP commands as we are going to reset the
10036                  * function anyway.
10037                  */
10038                 bp->sp_rtnl_state = 0;
10039                 smp_mb();
10040
10041                 bnx2x_parity_recover(bp);
10042
10043                 rtnl_unlock();
10044                 return;
10045         }
10046
10047         if (test_and_clear_bit(BNX2X_SP_RTNL_TX_TIMEOUT, &bp->sp_rtnl_state)) {
10048 #ifdef BNX2X_STOP_ON_ERROR
10049                 BNX2X_ERR("recovery flow called but STOP_ON_ERROR defined so reset not done to allow debug dump,\n"
10050                           "you will need to reboot when done\n");
10051                 goto sp_rtnl_not_reset;
10052 #endif
10053
10054                 /*
10055                  * Clear all pending SP commands as we are going to reset the
10056                  * function anyway.
10057                  */
10058                 bp->sp_rtnl_state = 0;
10059                 smp_mb();
10060
10061                 bnx2x_nic_unload(bp, UNLOAD_NORMAL, true);
10062                 bnx2x_nic_load(bp, LOAD_NORMAL);
10063
10064                 rtnl_unlock();
10065                 return;
10066         }
10067 #ifdef BNX2X_STOP_ON_ERROR
10068 sp_rtnl_not_reset:
10069 #endif
10070         if (test_and_clear_bit(BNX2X_SP_RTNL_SETUP_TC, &bp->sp_rtnl_state))
10071                 bnx2x_setup_tc(bp->dev, bp->dcbx_port_params.ets.num_of_cos);
10072         if (test_and_clear_bit(BNX2X_SP_RTNL_AFEX_F_UPDATE, &bp->sp_rtnl_state))
10073                 bnx2x_after_function_update(bp);
10074         /*
10075          * in case of fan failure we need to reset id if the "stop on error"
10076          * debug flag is set, since we trying to prevent permanent overheating
10077          * damage
10078          */
10079         if (test_and_clear_bit(BNX2X_SP_RTNL_FAN_FAILURE, &bp->sp_rtnl_state)) {
10080                 DP(NETIF_MSG_HW, "fan failure detected. Unloading driver\n");
10081                 netif_device_detach(bp->dev);
10082                 bnx2x_close(bp->dev);
10083                 rtnl_unlock();
10084                 return;
10085         }
10086
10087         if (test_and_clear_bit(BNX2X_SP_RTNL_VFPF_MCAST, &bp->sp_rtnl_state)) {
10088                 DP(BNX2X_MSG_SP,
10089                    "sending set mcast vf pf channel message from rtnl sp-task\n");
10090                 bnx2x_vfpf_set_mcast(bp->dev);
10091         }
10092         if (test_and_clear_bit(BNX2X_SP_RTNL_VFPF_CHANNEL_DOWN,
10093                                &bp->sp_rtnl_state)){
10094                 if (!test_bit(__LINK_STATE_NOCARRIER, &bp->dev->state)) {
10095                         bnx2x_tx_disable(bp);
10096                         BNX2X_ERR("PF indicated channel is not servicable anymore. This means this VF device is no longer operational\n");
10097                 }
10098         }
10099
10100         if (test_and_clear_bit(BNX2X_SP_RTNL_RX_MODE, &bp->sp_rtnl_state)) {
10101                 DP(BNX2X_MSG_SP, "Handling Rx Mode setting\n");
10102                 bnx2x_set_rx_mode_inner(bp);
10103         }
10104
10105         if (test_and_clear_bit(BNX2X_SP_RTNL_HYPERVISOR_VLAN,
10106                                &bp->sp_rtnl_state))
10107                 bnx2x_pf_set_vfs_vlan(bp);
10108
10109         if (test_and_clear_bit(BNX2X_SP_RTNL_TX_STOP, &bp->sp_rtnl_state)) {
10110                 bnx2x_dcbx_stop_hw_tx(bp);
10111                 bnx2x_dcbx_resume_hw_tx(bp);
10112         }
10113
10114         if (test_and_clear_bit(BNX2X_SP_RTNL_GET_DRV_VERSION,
10115                                &bp->sp_rtnl_state))
10116                 bnx2x_update_mng_version(bp);
10117
10118         /* work which needs rtnl lock not-taken (as it takes the lock itself and
10119          * can be called from other contexts as well)
10120          */
10121         rtnl_unlock();
10122
10123         /* enable SR-IOV if applicable */
10124         if (IS_SRIOV(bp) && test_and_clear_bit(BNX2X_SP_RTNL_ENABLE_SRIOV,
10125                                                &bp->sp_rtnl_state)) {
10126                 bnx2x_disable_sriov(bp);
10127                 bnx2x_enable_sriov(bp);
10128         }
10129 }
10130
10131 static void bnx2x_period_task(struct work_struct *work)
10132 {
10133         struct bnx2x *bp = container_of(work, struct bnx2x, period_task.work);
10134
10135         if (!netif_running(bp->dev))
10136                 goto period_task_exit;
10137
10138         if (CHIP_REV_IS_SLOW(bp)) {
10139                 BNX2X_ERR("period task called on emulation, ignoring\n");
10140                 goto period_task_exit;
10141         }
10142
10143         bnx2x_acquire_phy_lock(bp);
10144         /*
10145          * The barrier is needed to ensure the ordering between the writing to
10146          * the bp->port.pmf in the bnx2x_nic_load() or bnx2x_pmf_update() and
10147          * the reading here.
10148          */
10149         smp_mb();
10150         if (bp->port.pmf) {
10151                 bnx2x_period_func(&bp->link_params, &bp->link_vars);
10152
10153                 /* Re-queue task in 1 sec */
10154                 queue_delayed_work(bnx2x_wq, &bp->period_task, 1*HZ);
10155         }
10156
10157         bnx2x_release_phy_lock(bp);
10158 period_task_exit:
10159         return;
10160 }
10161
10162 /*
10163  * Init service functions
10164  */
10165
10166 static u32 bnx2x_get_pretend_reg(struct bnx2x *bp)
10167 {
10168         u32 base = PXP2_REG_PGL_PRETEND_FUNC_F0;
10169         u32 stride = PXP2_REG_PGL_PRETEND_FUNC_F1 - base;
10170         return base + (BP_ABS_FUNC(bp)) * stride;
10171 }
10172
10173 static bool bnx2x_prev_unload_close_umac(struct bnx2x *bp,
10174                                          u8 port, u32 reset_reg,
10175                                          struct bnx2x_mac_vals *vals)
10176 {
10177         u32 mask = MISC_REGISTERS_RESET_REG_2_UMAC0 << port;
10178         u32 base_addr;
10179
10180         if (!(mask & reset_reg))
10181                 return false;
10182
10183         BNX2X_DEV_INFO("Disable umac Rx %02x\n", port);
10184         base_addr = port ? GRCBASE_UMAC1 : GRCBASE_UMAC0;
10185         vals->umac_addr[port] = base_addr + UMAC_REG_COMMAND_CONFIG;
10186         vals->umac_val[port] = REG_RD(bp, vals->umac_addr[port]);
10187         REG_WR(bp, vals->umac_addr[port], 0);
10188
10189         return true;
10190 }
10191
10192 static void bnx2x_prev_unload_close_mac(struct bnx2x *bp,
10193                                         struct bnx2x_mac_vals *vals)
10194 {
10195         u32 val, base_addr, offset, mask, reset_reg;
10196         bool mac_stopped = false;
10197         u8 port = BP_PORT(bp);
10198
10199         /* reset addresses as they also mark which values were changed */
10200         memset(vals, 0, sizeof(*vals));
10201
10202         reset_reg = REG_RD(bp, MISC_REG_RESET_REG_2);
10203
10204         if (!CHIP_IS_E3(bp)) {
10205                 val = REG_RD(bp, NIG_REG_BMAC0_REGS_OUT_EN + port * 4);
10206                 mask = MISC_REGISTERS_RESET_REG_2_RST_BMAC0 << port;
10207                 if ((mask & reset_reg) && val) {
10208                         u32 wb_data[2];
10209                         BNX2X_DEV_INFO("Disable bmac Rx\n");
10210                         base_addr = BP_PORT(bp) ? NIG_REG_INGRESS_BMAC1_MEM
10211                                                 : NIG_REG_INGRESS_BMAC0_MEM;
10212                         offset = CHIP_IS_E2(bp) ? BIGMAC2_REGISTER_BMAC_CONTROL
10213                                                 : BIGMAC_REGISTER_BMAC_CONTROL;
10214
10215                         /*
10216                          * use rd/wr since we cannot use dmae. This is safe
10217                          * since MCP won't access the bus due to the request
10218                          * to unload, and no function on the path can be
10219                          * loaded at this time.
10220                          */
10221                         wb_data[0] = REG_RD(bp, base_addr + offset);
10222                         wb_data[1] = REG_RD(bp, base_addr + offset + 0x4);
10223                         vals->bmac_addr = base_addr + offset;
10224                         vals->bmac_val[0] = wb_data[0];
10225                         vals->bmac_val[1] = wb_data[1];
10226                         wb_data[0] &= ~BMAC_CONTROL_RX_ENABLE;
10227                         REG_WR(bp, vals->bmac_addr, wb_data[0]);
10228                         REG_WR(bp, vals->bmac_addr + 0x4, wb_data[1]);
10229                 }
10230                 BNX2X_DEV_INFO("Disable emac Rx\n");
10231                 vals->emac_addr = NIG_REG_NIG_EMAC0_EN + BP_PORT(bp)*4;
10232                 vals->emac_val = REG_RD(bp, vals->emac_addr);
10233                 REG_WR(bp, vals->emac_addr, 0);
10234                 mac_stopped = true;
10235         } else {
10236                 if (reset_reg & MISC_REGISTERS_RESET_REG_2_XMAC) {
10237                         BNX2X_DEV_INFO("Disable xmac Rx\n");
10238                         base_addr = BP_PORT(bp) ? GRCBASE_XMAC1 : GRCBASE_XMAC0;
10239                         val = REG_RD(bp, base_addr + XMAC_REG_PFC_CTRL_HI);
10240                         REG_WR(bp, base_addr + XMAC_REG_PFC_CTRL_HI,
10241                                val & ~(1 << 1));
10242                         REG_WR(bp, base_addr + XMAC_REG_PFC_CTRL_HI,
10243                                val | (1 << 1));
10244                         vals->xmac_addr = base_addr + XMAC_REG_CTRL;
10245                         vals->xmac_val = REG_RD(bp, vals->xmac_addr);
10246                         REG_WR(bp, vals->xmac_addr, 0);
10247                         mac_stopped = true;
10248                 }
10249
10250                 mac_stopped |= bnx2x_prev_unload_close_umac(bp, 0,
10251                                                             reset_reg, vals);
10252                 mac_stopped |= bnx2x_prev_unload_close_umac(bp, 1,
10253                                                             reset_reg, vals);
10254         }
10255
10256         if (mac_stopped)
10257                 msleep(20);
10258 }
10259
10260 #define BNX2X_PREV_UNDI_PROD_ADDR(p) (BAR_TSTRORM_INTMEM + 0x1508 + ((p) << 4))
10261 #define BNX2X_PREV_UNDI_PROD_ADDR_H(f) (BAR_TSTRORM_INTMEM + \
10262                                         0x1848 + ((f) << 4))
10263 #define BNX2X_PREV_UNDI_RCQ(val)        ((val) & 0xffff)
10264 #define BNX2X_PREV_UNDI_BD(val)         ((val) >> 16 & 0xffff)
10265 #define BNX2X_PREV_UNDI_PROD(rcq, bd)   ((bd) << 16 | (rcq))
10266
10267 #define BCM_5710_UNDI_FW_MF_MAJOR       (0x07)
10268 #define BCM_5710_UNDI_FW_MF_MINOR       (0x08)
10269 #define BCM_5710_UNDI_FW_MF_VERS        (0x05)
10270
10271 static bool bnx2x_prev_is_after_undi(struct bnx2x *bp)
10272 {
10273         /* UNDI marks its presence in DORQ -
10274          * it initializes CID offset for normal bell to 0x7
10275          */
10276         if (!(REG_RD(bp, MISC_REG_RESET_REG_1) &
10277             MISC_REGISTERS_RESET_REG_1_RST_DORQ))
10278                 return false;
10279
10280         if (REG_RD(bp, DORQ_REG_NORM_CID_OFST) == 0x7) {
10281                 BNX2X_DEV_INFO("UNDI previously loaded\n");
10282                 return true;
10283         }
10284
10285         return false;
10286 }
10287
10288 static void bnx2x_prev_unload_undi_inc(struct bnx2x *bp, u8 inc)
10289 {
10290         u16 rcq, bd;
10291         u32 addr, tmp_reg;
10292
10293         if (BP_FUNC(bp) < 2)
10294                 addr = BNX2X_PREV_UNDI_PROD_ADDR(BP_PORT(bp));
10295         else
10296                 addr = BNX2X_PREV_UNDI_PROD_ADDR_H(BP_FUNC(bp) - 2);
10297
10298         tmp_reg = REG_RD(bp, addr);
10299         rcq = BNX2X_PREV_UNDI_RCQ(tmp_reg) + inc;
10300         bd = BNX2X_PREV_UNDI_BD(tmp_reg) + inc;
10301
10302         tmp_reg = BNX2X_PREV_UNDI_PROD(rcq, bd);
10303         REG_WR(bp, addr, tmp_reg);
10304
10305         BNX2X_DEV_INFO("UNDI producer [%d/%d][%08x] rings bd -> 0x%04x, rcq -> 0x%04x\n",
10306                        BP_PORT(bp), BP_FUNC(bp), addr, bd, rcq);
10307 }
10308
10309 static int bnx2x_prev_mcp_done(struct bnx2x *bp)
10310 {
10311         u32 rc = bnx2x_fw_command(bp, DRV_MSG_CODE_UNLOAD_DONE,
10312                                   DRV_MSG_CODE_UNLOAD_SKIP_LINK_RESET);
10313         if (!rc) {
10314                 BNX2X_ERR("MCP response failure, aborting\n");
10315                 return -EBUSY;
10316         }
10317
10318         return 0;
10319 }
10320
10321 static struct bnx2x_prev_path_list *
10322                 bnx2x_prev_path_get_entry(struct bnx2x *bp)
10323 {
10324         struct bnx2x_prev_path_list *tmp_list;
10325
10326         list_for_each_entry(tmp_list, &bnx2x_prev_list, list)
10327                 if (PCI_SLOT(bp->pdev->devfn) == tmp_list->slot &&
10328                     bp->pdev->bus->number == tmp_list->bus &&
10329                     BP_PATH(bp) == tmp_list->path)
10330                         return tmp_list;
10331
10332         return NULL;
10333 }
10334
10335 static int bnx2x_prev_path_mark_eeh(struct bnx2x *bp)
10336 {
10337         struct bnx2x_prev_path_list *tmp_list;
10338         int rc;
10339
10340         rc = down_interruptible(&bnx2x_prev_sem);
10341         if (rc) {
10342                 BNX2X_ERR("Received %d when tried to take lock\n", rc);
10343                 return rc;
10344         }
10345
10346         tmp_list = bnx2x_prev_path_get_entry(bp);
10347         if (tmp_list) {
10348                 tmp_list->aer = 1;
10349                 rc = 0;
10350         } else {
10351                 BNX2X_ERR("path %d: Entry does not exist for eeh; Flow occurs before initial insmod is over ?\n",
10352                           BP_PATH(bp));
10353         }
10354
10355         up(&bnx2x_prev_sem);
10356
10357         return rc;
10358 }
10359
10360 static bool bnx2x_prev_is_path_marked(struct bnx2x *bp)
10361 {
10362         struct bnx2x_prev_path_list *tmp_list;
10363         bool rc = false;
10364
10365         if (down_trylock(&bnx2x_prev_sem))
10366                 return false;
10367
10368         tmp_list = bnx2x_prev_path_get_entry(bp);
10369         if (tmp_list) {
10370                 if (tmp_list->aer) {
10371                         DP(NETIF_MSG_HW, "Path %d was marked by AER\n",
10372                            BP_PATH(bp));
10373                 } else {
10374                         rc = true;
10375                         BNX2X_DEV_INFO("Path %d was already cleaned from previous drivers\n",
10376                                        BP_PATH(bp));
10377                 }
10378         }
10379
10380         up(&bnx2x_prev_sem);
10381
10382         return rc;
10383 }
10384
10385 bool bnx2x_port_after_undi(struct bnx2x *bp)
10386 {
10387         struct bnx2x_prev_path_list *entry;
10388         bool val;
10389
10390         down(&bnx2x_prev_sem);
10391
10392         entry = bnx2x_prev_path_get_entry(bp);
10393         val = !!(entry && (entry->undi & (1 << BP_PORT(bp))));
10394
10395         up(&bnx2x_prev_sem);
10396
10397         return val;
10398 }
10399
10400 static int bnx2x_prev_mark_path(struct bnx2x *bp, bool after_undi)
10401 {
10402         struct bnx2x_prev_path_list *tmp_list;
10403         int rc;
10404
10405         rc = down_interruptible(&bnx2x_prev_sem);
10406         if (rc) {
10407                 BNX2X_ERR("Received %d when tried to take lock\n", rc);
10408                 return rc;
10409         }
10410
10411         /* Check whether the entry for this path already exists */
10412         tmp_list = bnx2x_prev_path_get_entry(bp);
10413         if (tmp_list) {
10414                 if (!tmp_list->aer) {
10415                         BNX2X_ERR("Re-Marking the path.\n");
10416                 } else {
10417                         DP(NETIF_MSG_HW, "Removing AER indication from path %d\n",
10418                            BP_PATH(bp));
10419                         tmp_list->aer = 0;
10420                 }
10421                 up(&bnx2x_prev_sem);
10422                 return 0;
10423         }
10424         up(&bnx2x_prev_sem);
10425
10426         /* Create an entry for this path and add it */
10427         tmp_list = kmalloc(sizeof(struct bnx2x_prev_path_list), GFP_KERNEL);
10428         if (!tmp_list) {
10429                 BNX2X_ERR("Failed to allocate 'bnx2x_prev_path_list'\n");
10430                 return -ENOMEM;
10431         }
10432
10433         tmp_list->bus = bp->pdev->bus->number;
10434         tmp_list->slot = PCI_SLOT(bp->pdev->devfn);
10435         tmp_list->path = BP_PATH(bp);
10436         tmp_list->aer = 0;
10437         tmp_list->undi = after_undi ? (1 << BP_PORT(bp)) : 0;
10438
10439         rc = down_interruptible(&bnx2x_prev_sem);
10440         if (rc) {
10441                 BNX2X_ERR("Received %d when tried to take lock\n", rc);
10442                 kfree(tmp_list);
10443         } else {
10444                 DP(NETIF_MSG_HW, "Marked path [%d] - finished previous unload\n",
10445                    BP_PATH(bp));
10446                 list_add(&tmp_list->list, &bnx2x_prev_list);
10447                 up(&bnx2x_prev_sem);
10448         }
10449
10450         return rc;
10451 }
10452
10453 static int bnx2x_do_flr(struct bnx2x *bp)
10454 {
10455         struct pci_dev *dev = bp->pdev;
10456
10457         if (CHIP_IS_E1x(bp)) {
10458                 BNX2X_DEV_INFO("FLR not supported in E1/E1H\n");
10459                 return -EINVAL;
10460         }
10461
10462         /* only bootcode REQ_BC_VER_4_INITIATE_FLR and onwards support flr */
10463         if (bp->common.bc_ver < REQ_BC_VER_4_INITIATE_FLR) {
10464                 BNX2X_ERR("FLR not supported by BC_VER: 0x%x\n",
10465                           bp->common.bc_ver);
10466                 return -EINVAL;
10467         }
10468
10469         if (!pci_wait_for_pending_transaction(dev))
10470                 dev_err(&dev->dev, "transaction is not cleared; proceeding with reset anyway\n");
10471
10472         BNX2X_DEV_INFO("Initiating FLR\n");
10473         bnx2x_fw_command(bp, DRV_MSG_CODE_INITIATE_FLR, 0);
10474
10475         return 0;
10476 }
10477
10478 static int bnx2x_prev_unload_uncommon(struct bnx2x *bp)
10479 {
10480         int rc;
10481
10482         BNX2X_DEV_INFO("Uncommon unload Flow\n");
10483
10484         /* Test if previous unload process was already finished for this path */
10485         if (bnx2x_prev_is_path_marked(bp))
10486                 return bnx2x_prev_mcp_done(bp);
10487
10488         BNX2X_DEV_INFO("Path is unmarked\n");
10489
10490         /* Cannot proceed with FLR if UNDI is loaded, since FW does not match */
10491         if (bnx2x_prev_is_after_undi(bp))
10492                 goto out;
10493
10494         /* If function has FLR capabilities, and existing FW version matches
10495          * the one required, then FLR will be sufficient to clean any residue
10496          * left by previous driver
10497          */
10498         rc = bnx2x_compare_fw_ver(bp, FW_MSG_CODE_DRV_LOAD_FUNCTION, false);
10499
10500         if (!rc) {
10501                 /* fw version is good */
10502                 BNX2X_DEV_INFO("FW version matches our own. Attempting FLR\n");
10503                 rc = bnx2x_do_flr(bp);
10504         }
10505
10506         if (!rc) {
10507                 /* FLR was performed */
10508                 BNX2X_DEV_INFO("FLR successful\n");
10509                 return 0;
10510         }
10511
10512         BNX2X_DEV_INFO("Could not FLR\n");
10513
10514 out:
10515         /* Close the MCP request, return failure*/
10516         rc = bnx2x_prev_mcp_done(bp);
10517         if (!rc)
10518                 rc = BNX2X_PREV_WAIT_NEEDED;
10519
10520         return rc;
10521 }
10522
10523 static int bnx2x_prev_unload_common(struct bnx2x *bp)
10524 {
10525         u32 reset_reg, tmp_reg = 0, rc;
10526         bool prev_undi = false;
10527         struct bnx2x_mac_vals mac_vals;
10528
10529         /* It is possible a previous function received 'common' answer,
10530          * but hasn't loaded yet, therefore creating a scenario of
10531          * multiple functions receiving 'common' on the same path.
10532          */
10533         BNX2X_DEV_INFO("Common unload Flow\n");
10534
10535         memset(&mac_vals, 0, sizeof(mac_vals));
10536
10537         if (bnx2x_prev_is_path_marked(bp))
10538                 return bnx2x_prev_mcp_done(bp);
10539
10540         reset_reg = REG_RD(bp, MISC_REG_RESET_REG_1);
10541
10542         /* Reset should be performed after BRB is emptied */
10543         if (reset_reg & MISC_REGISTERS_RESET_REG_1_RST_BRB1) {
10544                 u32 timer_count = 1000;
10545
10546                 /* Close the MAC Rx to prevent BRB from filling up */
10547                 bnx2x_prev_unload_close_mac(bp, &mac_vals);
10548
10549                 /* close LLH filters for both ports towards the BRB */
10550                 bnx2x_set_rx_filter(&bp->link_params, 0);
10551                 bp->link_params.port ^= 1;
10552                 bnx2x_set_rx_filter(&bp->link_params, 0);
10553                 bp->link_params.port ^= 1;
10554
10555                 /* Check if the UNDI driver was previously loaded */
10556                 if (bnx2x_prev_is_after_undi(bp)) {
10557                         prev_undi = true;
10558                         /* clear the UNDI indication */
10559                         REG_WR(bp, DORQ_REG_NORM_CID_OFST, 0);
10560                         /* clear possible idle check errors */
10561                         REG_RD(bp, NIG_REG_NIG_INT_STS_CLR_0);
10562                 }
10563                 if (!CHIP_IS_E1x(bp))
10564                         /* block FW from writing to host */
10565                         REG_WR(bp, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, 0);
10566
10567                 /* wait until BRB is empty */
10568                 tmp_reg = REG_RD(bp, BRB1_REG_NUM_OF_FULL_BLOCKS);
10569                 while (timer_count) {
10570                         u32 prev_brb = tmp_reg;
10571
10572                         tmp_reg = REG_RD(bp, BRB1_REG_NUM_OF_FULL_BLOCKS);
10573                         if (!tmp_reg)
10574                                 break;
10575
10576                         BNX2X_DEV_INFO("BRB still has 0x%08x\n", tmp_reg);
10577
10578                         /* reset timer as long as BRB actually gets emptied */
10579                         if (prev_brb > tmp_reg)
10580                                 timer_count = 1000;
10581                         else
10582                                 timer_count--;
10583
10584                         /* If UNDI resides in memory, manually increment it */
10585                         if (prev_undi)
10586                                 bnx2x_prev_unload_undi_inc(bp, 1);
10587
10588                         udelay(10);
10589                 }
10590
10591                 if (!timer_count)
10592                         BNX2X_ERR("Failed to empty BRB, hope for the best\n");
10593         }
10594
10595         /* No packets are in the pipeline, path is ready for reset */
10596         bnx2x_reset_common(bp);
10597
10598         if (mac_vals.xmac_addr)
10599                 REG_WR(bp, mac_vals.xmac_addr, mac_vals.xmac_val);
10600         if (mac_vals.umac_addr[0])
10601                 REG_WR(bp, mac_vals.umac_addr[0], mac_vals.umac_val[0]);
10602         if (mac_vals.umac_addr[1])
10603                 REG_WR(bp, mac_vals.umac_addr[1], mac_vals.umac_val[1]);
10604         if (mac_vals.emac_addr)
10605                 REG_WR(bp, mac_vals.emac_addr, mac_vals.emac_val);
10606         if (mac_vals.bmac_addr) {
10607                 REG_WR(bp, mac_vals.bmac_addr, mac_vals.bmac_val[0]);
10608                 REG_WR(bp, mac_vals.bmac_addr + 4, mac_vals.bmac_val[1]);
10609         }
10610
10611         rc = bnx2x_prev_mark_path(bp, prev_undi);
10612         if (rc) {
10613                 bnx2x_prev_mcp_done(bp);
10614                 return rc;
10615         }
10616
10617         return bnx2x_prev_mcp_done(bp);
10618 }
10619
10620 static int bnx2x_prev_unload(struct bnx2x *bp)
10621 {
10622         int time_counter = 10;
10623         u32 rc, fw, hw_lock_reg, hw_lock_val;
10624         BNX2X_DEV_INFO("Entering Previous Unload Flow\n");
10625
10626         /* clear hw from errors which may have resulted from an interrupted
10627          * dmae transaction.
10628          */
10629         bnx2x_clean_pglue_errors(bp);
10630
10631         /* Release previously held locks */
10632         hw_lock_reg = (BP_FUNC(bp) <= 5) ?
10633                       (MISC_REG_DRIVER_CONTROL_1 + BP_FUNC(bp) * 8) :
10634                       (MISC_REG_DRIVER_CONTROL_7 + (BP_FUNC(bp) - 6) * 8);
10635
10636         hw_lock_val = REG_RD(bp, hw_lock_reg);
10637         if (hw_lock_val) {
10638                 if (hw_lock_val & HW_LOCK_RESOURCE_NVRAM) {
10639                         BNX2X_DEV_INFO("Release Previously held NVRAM lock\n");
10640                         REG_WR(bp, MCP_REG_MCPR_NVM_SW_ARB,
10641                                (MCPR_NVM_SW_ARB_ARB_REQ_CLR1 << BP_PORT(bp)));
10642                 }
10643
10644                 BNX2X_DEV_INFO("Release Previously held hw lock\n");
10645                 REG_WR(bp, hw_lock_reg, 0xffffffff);
10646         } else
10647                 BNX2X_DEV_INFO("No need to release hw/nvram locks\n");
10648
10649         if (MCPR_ACCESS_LOCK_LOCK & REG_RD(bp, MCP_REG_MCPR_ACCESS_LOCK)) {
10650                 BNX2X_DEV_INFO("Release previously held alr\n");
10651                 bnx2x_release_alr(bp);
10652         }
10653
10654         do {
10655                 int aer = 0;
10656                 /* Lock MCP using an unload request */
10657                 fw = bnx2x_fw_command(bp, DRV_MSG_CODE_UNLOAD_REQ_WOL_DIS, 0);
10658                 if (!fw) {
10659                         BNX2X_ERR("MCP response failure, aborting\n");
10660                         rc = -EBUSY;
10661                         break;
10662                 }
10663
10664                 rc = down_interruptible(&bnx2x_prev_sem);
10665                 if (rc) {
10666                         BNX2X_ERR("Cannot check for AER; Received %d when tried to take lock\n",
10667                                   rc);
10668                 } else {
10669                         /* If Path is marked by EEH, ignore unload status */
10670                         aer = !!(bnx2x_prev_path_get_entry(bp) &&
10671                                  bnx2x_prev_path_get_entry(bp)->aer);
10672                         up(&bnx2x_prev_sem);
10673                 }
10674
10675                 if (fw == FW_MSG_CODE_DRV_UNLOAD_COMMON || aer) {
10676                         rc = bnx2x_prev_unload_common(bp);
10677                         break;
10678                 }
10679
10680                 /* non-common reply from MCP might require looping */
10681                 rc = bnx2x_prev_unload_uncommon(bp);
10682                 if (rc != BNX2X_PREV_WAIT_NEEDED)
10683                         break;
10684
10685                 msleep(20);
10686         } while (--time_counter);
10687
10688         if (!time_counter || rc) {
10689                 BNX2X_DEV_INFO("Unloading previous driver did not occur, Possibly due to MF UNDI\n");
10690                 rc = -EPROBE_DEFER;
10691         }
10692
10693         /* Mark function if its port was used to boot from SAN */
10694         if (bnx2x_port_after_undi(bp))
10695                 bp->link_params.feature_config_flags |=
10696                         FEATURE_CONFIG_BOOT_FROM_SAN;
10697
10698         BNX2X_DEV_INFO("Finished Previous Unload Flow [%d]\n", rc);
10699
10700         return rc;
10701 }
10702
10703 static void bnx2x_get_common_hwinfo(struct bnx2x *bp)
10704 {
10705         u32 val, val2, val3, val4, id, boot_mode;
10706         u16 pmc;
10707
10708         /* Get the chip revision id and number. */
10709         /* chip num:16-31, rev:12-15, metal:4-11, bond_id:0-3 */
10710         val = REG_RD(bp, MISC_REG_CHIP_NUM);
10711         id = ((val & 0xffff) << 16);
10712         val = REG_RD(bp, MISC_REG_CHIP_REV);
10713         id |= ((val & 0xf) << 12);
10714
10715         /* Metal is read from PCI regs, but we can't access >=0x400 from
10716          * the configuration space (so we need to reg_rd)
10717          */
10718         val = REG_RD(bp, PCICFG_OFFSET + PCI_ID_VAL3);
10719         id |= (((val >> 24) & 0xf) << 4);
10720         val = REG_RD(bp, MISC_REG_BOND_ID);
10721         id |= (val & 0xf);
10722         bp->common.chip_id = id;
10723
10724         /* force 57811 according to MISC register */
10725         if (REG_RD(bp, MISC_REG_CHIP_TYPE) & MISC_REG_CHIP_TYPE_57811_MASK) {
10726                 if (CHIP_IS_57810(bp))
10727                         bp->common.chip_id = (CHIP_NUM_57811 << 16) |
10728                                 (bp->common.chip_id & 0x0000FFFF);
10729                 else if (CHIP_IS_57810_MF(bp))
10730                         bp->common.chip_id = (CHIP_NUM_57811_MF << 16) |
10731                                 (bp->common.chip_id & 0x0000FFFF);
10732                 bp->common.chip_id |= 0x1;
10733         }
10734
10735         /* Set doorbell size */
10736         bp->db_size = (1 << BNX2X_DB_SHIFT);
10737
10738         if (!CHIP_IS_E1x(bp)) {
10739                 val = REG_RD(bp, MISC_REG_PORT4MODE_EN_OVWR);
10740                 if ((val & 1) == 0)
10741                         val = REG_RD(bp, MISC_REG_PORT4MODE_EN);
10742                 else
10743                         val = (val >> 1) & 1;
10744                 BNX2X_DEV_INFO("chip is in %s\n", val ? "4_PORT_MODE" :
10745                                                        "2_PORT_MODE");
10746                 bp->common.chip_port_mode = val ? CHIP_4_PORT_MODE :
10747                                                  CHIP_2_PORT_MODE;
10748
10749                 if (CHIP_MODE_IS_4_PORT(bp))
10750                         bp->pfid = (bp->pf_num >> 1);   /* 0..3 */
10751                 else
10752                         bp->pfid = (bp->pf_num & 0x6);  /* 0, 2, 4, 6 */
10753         } else {
10754                 bp->common.chip_port_mode = CHIP_PORT_MODE_NONE; /* N/A */
10755                 bp->pfid = bp->pf_num;                  /* 0..7 */
10756         }
10757
10758         BNX2X_DEV_INFO("pf_id: %x", bp->pfid);
10759
10760         bp->link_params.chip_id = bp->common.chip_id;
10761         BNX2X_DEV_INFO("chip ID is 0x%x\n", id);
10762
10763         val = (REG_RD(bp, 0x2874) & 0x55);
10764         if ((bp->common.chip_id & 0x1) ||
10765             (CHIP_IS_E1(bp) && val) || (CHIP_IS_E1H(bp) && (val == 0x55))) {
10766                 bp->flags |= ONE_PORT_FLAG;
10767                 BNX2X_DEV_INFO("single port device\n");
10768         }
10769
10770         val = REG_RD(bp, MCP_REG_MCPR_NVM_CFG4);
10771         bp->common.flash_size = (BNX2X_NVRAM_1MB_SIZE <<
10772                                  (val & MCPR_NVM_CFG4_FLASH_SIZE));
10773         BNX2X_DEV_INFO("flash_size 0x%x (%d)\n",
10774                        bp->common.flash_size, bp->common.flash_size);
10775
10776         bnx2x_init_shmem(bp);
10777
10778         bp->common.shmem2_base = REG_RD(bp, (BP_PATH(bp) ?
10779                                         MISC_REG_GENERIC_CR_1 :
10780                                         MISC_REG_GENERIC_CR_0));
10781
10782         bp->link_params.shmem_base = bp->common.shmem_base;
10783         bp->link_params.shmem2_base = bp->common.shmem2_base;
10784         if (SHMEM2_RD(bp, size) >
10785             (u32)offsetof(struct shmem2_region, lfa_host_addr[BP_PORT(bp)]))
10786                 bp->link_params.lfa_base =
10787                 REG_RD(bp, bp->common.shmem2_base +
10788                        (u32)offsetof(struct shmem2_region,
10789                                      lfa_host_addr[BP_PORT(bp)]));
10790         else
10791                 bp->link_params.lfa_base = 0;
10792         BNX2X_DEV_INFO("shmem offset 0x%x  shmem2 offset 0x%x\n",
10793                        bp->common.shmem_base, bp->common.shmem2_base);
10794
10795         if (!bp->common.shmem_base) {
10796                 BNX2X_DEV_INFO("MCP not active\n");
10797                 bp->flags |= NO_MCP_FLAG;
10798                 return;
10799         }
10800
10801         bp->common.hw_config = SHMEM_RD(bp, dev_info.shared_hw_config.config);
10802         BNX2X_DEV_INFO("hw_config 0x%08x\n", bp->common.hw_config);
10803
10804         bp->link_params.hw_led_mode = ((bp->common.hw_config &
10805                                         SHARED_HW_CFG_LED_MODE_MASK) >>
10806                                        SHARED_HW_CFG_LED_MODE_SHIFT);
10807
10808         bp->link_params.feature_config_flags = 0;
10809         val = SHMEM_RD(bp, dev_info.shared_feature_config.config);
10810         if (val & SHARED_FEAT_CFG_OVERRIDE_PREEMPHASIS_CFG_ENABLED)
10811                 bp->link_params.feature_config_flags |=
10812                                 FEATURE_CONFIG_OVERRIDE_PREEMPHASIS_ENABLED;
10813         else
10814                 bp->link_params.feature_config_flags &=
10815                                 ~FEATURE_CONFIG_OVERRIDE_PREEMPHASIS_ENABLED;
10816
10817         val = SHMEM_RD(bp, dev_info.bc_rev) >> 8;
10818         bp->common.bc_ver = val;
10819         BNX2X_DEV_INFO("bc_ver %X\n", val);
10820         if (val < BNX2X_BC_VER) {
10821                 /* for now only warn
10822                  * later we might need to enforce this */
10823                 BNX2X_ERR("This driver needs bc_ver %X but found %X, please upgrade BC\n",
10824                           BNX2X_BC_VER, val);
10825         }
10826         bp->link_params.feature_config_flags |=
10827                                 (val >= REQ_BC_VER_4_VRFY_FIRST_PHY_OPT_MDL) ?
10828                                 FEATURE_CONFIG_BC_SUPPORTS_OPT_MDL_VRFY : 0;
10829
10830         bp->link_params.feature_config_flags |=
10831                 (val >= REQ_BC_VER_4_VRFY_SPECIFIC_PHY_OPT_MDL) ?
10832                 FEATURE_CONFIG_BC_SUPPORTS_DUAL_PHY_OPT_MDL_VRFY : 0;
10833         bp->link_params.feature_config_flags |=
10834                 (val >= REQ_BC_VER_4_VRFY_AFEX_SUPPORTED) ?
10835                 FEATURE_CONFIG_BC_SUPPORTS_AFEX : 0;
10836         bp->link_params.feature_config_flags |=
10837                 (val >= REQ_BC_VER_4_SFP_TX_DISABLE_SUPPORTED) ?
10838                 FEATURE_CONFIG_BC_SUPPORTS_SFP_TX_DISABLED : 0;
10839
10840         bp->link_params.feature_config_flags |=
10841                 (val >= REQ_BC_VER_4_MT_SUPPORTED) ?
10842                 FEATURE_CONFIG_MT_SUPPORT : 0;
10843
10844         bp->flags |= (val >= REQ_BC_VER_4_PFC_STATS_SUPPORTED) ?
10845                         BC_SUPPORTS_PFC_STATS : 0;
10846
10847         bp->flags |= (val >= REQ_BC_VER_4_FCOE_FEATURES) ?
10848                         BC_SUPPORTS_FCOE_FEATURES : 0;
10849
10850         bp->flags |= (val >= REQ_BC_VER_4_DCBX_ADMIN_MSG_NON_PMF) ?
10851                         BC_SUPPORTS_DCBX_MSG_NON_PMF : 0;
10852
10853         bp->flags |= (val >= REQ_BC_VER_4_RMMOD_CMD) ?
10854                         BC_SUPPORTS_RMMOD_CMD : 0;
10855
10856         boot_mode = SHMEM_RD(bp,
10857                         dev_info.port_feature_config[BP_PORT(bp)].mba_config) &
10858                         PORT_FEATURE_MBA_BOOT_AGENT_TYPE_MASK;
10859         switch (boot_mode) {
10860         case PORT_FEATURE_MBA_BOOT_AGENT_TYPE_PXE:
10861                 bp->common.boot_mode = FEATURE_ETH_BOOTMODE_PXE;
10862                 break;
10863         case PORT_FEATURE_MBA_BOOT_AGENT_TYPE_ISCSIB:
10864                 bp->common.boot_mode = FEATURE_ETH_BOOTMODE_ISCSI;
10865                 break;
10866         case PORT_FEATURE_MBA_BOOT_AGENT_TYPE_FCOE_BOOT:
10867                 bp->common.boot_mode = FEATURE_ETH_BOOTMODE_FCOE;
10868                 break;
10869         case PORT_FEATURE_MBA_BOOT_AGENT_TYPE_NONE:
10870                 bp->common.boot_mode = FEATURE_ETH_BOOTMODE_NONE;
10871                 break;
10872         }
10873
10874         pci_read_config_word(bp->pdev, bp->pdev->pm_cap + PCI_PM_PMC, &pmc);
10875         bp->flags |= (pmc & PCI_PM_CAP_PME_D3cold) ? 0 : NO_WOL_FLAG;
10876
10877         BNX2X_DEV_INFO("%sWoL capable\n",
10878                        (bp->flags & NO_WOL_FLAG) ? "not " : "");
10879
10880         val = SHMEM_RD(bp, dev_info.shared_hw_config.part_num);
10881         val2 = SHMEM_RD(bp, dev_info.shared_hw_config.part_num[4]);
10882         val3 = SHMEM_RD(bp, dev_info.shared_hw_config.part_num[8]);
10883         val4 = SHMEM_RD(bp, dev_info.shared_hw_config.part_num[12]);
10884
10885         dev_info(&bp->pdev->dev, "part number %X-%X-%X-%X\n",
10886                  val, val2, val3, val4);
10887 }
10888
10889 #define IGU_FID(val)    GET_FIELD((val), IGU_REG_MAPPING_MEMORY_FID)
10890 #define IGU_VEC(val)    GET_FIELD((val), IGU_REG_MAPPING_MEMORY_VECTOR)
10891
10892 static int bnx2x_get_igu_cam_info(struct bnx2x *bp)
10893 {
10894         int pfid = BP_FUNC(bp);
10895         int igu_sb_id;
10896         u32 val;
10897         u8 fid, igu_sb_cnt = 0;
10898
10899         bp->igu_base_sb = 0xff;
10900         if (CHIP_INT_MODE_IS_BC(bp)) {
10901                 int vn = BP_VN(bp);
10902                 igu_sb_cnt = bp->igu_sb_cnt;
10903                 bp->igu_base_sb = (CHIP_MODE_IS_4_PORT(bp) ? pfid : vn) *
10904                         FP_SB_MAX_E1x;
10905
10906                 bp->igu_dsb_id =  E1HVN_MAX * FP_SB_MAX_E1x +
10907                         (CHIP_MODE_IS_4_PORT(bp) ? pfid : vn);
10908
10909                 return 0;
10910         }
10911
10912         /* IGU in normal mode - read CAM */
10913         for (igu_sb_id = 0; igu_sb_id < IGU_REG_MAPPING_MEMORY_SIZE;
10914              igu_sb_id++) {
10915                 val = REG_RD(bp, IGU_REG_MAPPING_MEMORY + igu_sb_id * 4);
10916                 if (!(val & IGU_REG_MAPPING_MEMORY_VALID))
10917                         continue;
10918                 fid = IGU_FID(val);
10919                 if ((fid & IGU_FID_ENCODE_IS_PF)) {
10920                         if ((fid & IGU_FID_PF_NUM_MASK) != pfid)
10921                                 continue;
10922                         if (IGU_VEC(val) == 0)
10923                                 /* default status block */
10924                                 bp->igu_dsb_id = igu_sb_id;
10925                         else {
10926                                 if (bp->igu_base_sb == 0xff)
10927                                         bp->igu_base_sb = igu_sb_id;
10928                                 igu_sb_cnt++;
10929                         }
10930                 }
10931         }
10932
10933 #ifdef CONFIG_PCI_MSI
10934         /* Due to new PF resource allocation by MFW T7.4 and above, it's
10935          * optional that number of CAM entries will not be equal to the value
10936          * advertised in PCI.
10937          * Driver should use the minimal value of both as the actual status
10938          * block count
10939          */
10940         bp->igu_sb_cnt = min_t(int, bp->igu_sb_cnt, igu_sb_cnt);
10941 #endif
10942
10943         if (igu_sb_cnt == 0) {
10944                 BNX2X_ERR("CAM configuration error\n");
10945                 return -EINVAL;
10946         }
10947
10948         return 0;
10949 }
10950
10951 static void bnx2x_link_settings_supported(struct bnx2x *bp, u32 switch_cfg)
10952 {
10953         int cfg_size = 0, idx, port = BP_PORT(bp);
10954
10955         /* Aggregation of supported attributes of all external phys */
10956         bp->port.supported[0] = 0;
10957         bp->port.supported[1] = 0;
10958         switch (bp->link_params.num_phys) {
10959         case 1:
10960                 bp->port.supported[0] = bp->link_params.phy[INT_PHY].supported;
10961                 cfg_size = 1;
10962                 break;
10963         case 2:
10964                 bp->port.supported[0] = bp->link_params.phy[EXT_PHY1].supported;
10965                 cfg_size = 1;
10966                 break;
10967         case 3:
10968                 if (bp->link_params.multi_phy_config &
10969                     PORT_HW_CFG_PHY_SWAPPED_ENABLED) {
10970                         bp->port.supported[1] =
10971                                 bp->link_params.phy[EXT_PHY1].supported;
10972                         bp->port.supported[0] =
10973                                 bp->link_params.phy[EXT_PHY2].supported;
10974                 } else {
10975                         bp->port.supported[0] =
10976                                 bp->link_params.phy[EXT_PHY1].supported;
10977                         bp->port.supported[1] =
10978                                 bp->link_params.phy[EXT_PHY2].supported;
10979                 }
10980                 cfg_size = 2;
10981                 break;
10982         }
10983
10984         if (!(bp->port.supported[0] || bp->port.supported[1])) {
10985                 BNX2X_ERR("NVRAM config error. BAD phy config. PHY1 config 0x%x, PHY2 config 0x%x\n",
10986                            SHMEM_RD(bp,
10987                            dev_info.port_hw_config[port].external_phy_config),
10988                            SHMEM_RD(bp,
10989                            dev_info.port_hw_config[port].external_phy_config2));
10990                         return;
10991         }
10992
10993         if (CHIP_IS_E3(bp))
10994                 bp->port.phy_addr = REG_RD(bp, MISC_REG_WC0_CTRL_PHY_ADDR);
10995         else {
10996                 switch (switch_cfg) {
10997                 case SWITCH_CFG_1G:
10998                         bp->port.phy_addr = REG_RD(
10999                                 bp, NIG_REG_SERDES0_CTRL_PHY_ADDR + port*0x10);
11000                         break;
11001                 case SWITCH_CFG_10G:
11002                         bp->port.phy_addr = REG_RD(
11003                                 bp, NIG_REG_XGXS0_CTRL_PHY_ADDR + port*0x18);
11004                         break;
11005                 default:
11006                         BNX2X_ERR("BAD switch_cfg link_config 0x%x\n",
11007                                   bp->port.link_config[0]);
11008                         return;
11009                 }
11010         }
11011         BNX2X_DEV_INFO("phy_addr 0x%x\n", bp->port.phy_addr);
11012         /* mask what we support according to speed_cap_mask per configuration */
11013         for (idx = 0; idx < cfg_size; idx++) {
11014                 if (!(bp->link_params.speed_cap_mask[idx] &
11015                                 PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_HALF))
11016                         bp->port.supported[idx] &= ~SUPPORTED_10baseT_Half;
11017
11018                 if (!(bp->link_params.speed_cap_mask[idx] &
11019                                 PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_FULL))
11020                         bp->port.supported[idx] &= ~SUPPORTED_10baseT_Full;
11021
11022                 if (!(bp->link_params.speed_cap_mask[idx] &
11023                                 PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_HALF))
11024                         bp->port.supported[idx] &= ~SUPPORTED_100baseT_Half;
11025
11026                 if (!(bp->link_params.speed_cap_mask[idx] &
11027                                 PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_FULL))
11028                         bp->port.supported[idx] &= ~SUPPORTED_100baseT_Full;
11029
11030                 if (!(bp->link_params.speed_cap_mask[idx] &
11031                                         PORT_HW_CFG_SPEED_CAPABILITY_D0_1G))
11032                         bp->port.supported[idx] &= ~(SUPPORTED_1000baseT_Half |
11033                                                      SUPPORTED_1000baseT_Full);
11034
11035                 if (!(bp->link_params.speed_cap_mask[idx] &
11036                                         PORT_HW_CFG_SPEED_CAPABILITY_D0_2_5G))
11037                         bp->port.supported[idx] &= ~SUPPORTED_2500baseX_Full;
11038
11039                 if (!(bp->link_params.speed_cap_mask[idx] &
11040                                         PORT_HW_CFG_SPEED_CAPABILITY_D0_10G))
11041                         bp->port.supported[idx] &= ~SUPPORTED_10000baseT_Full;
11042
11043                 if (!(bp->link_params.speed_cap_mask[idx] &
11044                                         PORT_HW_CFG_SPEED_CAPABILITY_D0_20G))
11045                         bp->port.supported[idx] &= ~SUPPORTED_20000baseKR2_Full;
11046         }
11047
11048         BNX2X_DEV_INFO("supported 0x%x 0x%x\n", bp->port.supported[0],
11049                        bp->port.supported[1]);
11050 }
11051
11052 static void bnx2x_link_settings_requested(struct bnx2x *bp)
11053 {
11054         u32 link_config, idx, cfg_size = 0;
11055         bp->port.advertising[0] = 0;
11056         bp->port.advertising[1] = 0;
11057         switch (bp->link_params.num_phys) {
11058         case 1:
11059         case 2:
11060                 cfg_size = 1;
11061                 break;
11062         case 3:
11063                 cfg_size = 2;
11064                 break;
11065         }
11066         for (idx = 0; idx < cfg_size; idx++) {
11067                 bp->link_params.req_duplex[idx] = DUPLEX_FULL;
11068                 link_config = bp->port.link_config[idx];
11069                 switch (link_config & PORT_FEATURE_LINK_SPEED_MASK) {
11070                 case PORT_FEATURE_LINK_SPEED_AUTO:
11071                         if (bp->port.supported[idx] & SUPPORTED_Autoneg) {
11072                                 bp->link_params.req_line_speed[idx] =
11073                                         SPEED_AUTO_NEG;
11074                                 bp->port.advertising[idx] |=
11075                                         bp->port.supported[idx];
11076                                 if (bp->link_params.phy[EXT_PHY1].type ==
11077                                     PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84833)
11078                                         bp->port.advertising[idx] |=
11079                                         (SUPPORTED_100baseT_Half |
11080                                          SUPPORTED_100baseT_Full);
11081                         } else {
11082                                 /* force 10G, no AN */
11083                                 bp->link_params.req_line_speed[idx] =
11084                                         SPEED_10000;
11085                                 bp->port.advertising[idx] |=
11086                                         (ADVERTISED_10000baseT_Full |
11087                                          ADVERTISED_FIBRE);
11088                                 continue;
11089                         }
11090                         break;
11091
11092                 case PORT_FEATURE_LINK_SPEED_10M_FULL:
11093                         if (bp->port.supported[idx] & SUPPORTED_10baseT_Full) {
11094                                 bp->link_params.req_line_speed[idx] =
11095                                         SPEED_10;
11096                                 bp->port.advertising[idx] |=
11097                                         (ADVERTISED_10baseT_Full |
11098                                          ADVERTISED_TP);
11099                         } else {
11100                                 BNX2X_ERR("NVRAM config error. Invalid link_config 0x%x  speed_cap_mask 0x%x\n",
11101                                             link_config,
11102                                     bp->link_params.speed_cap_mask[idx]);
11103                                 return;
11104                         }
11105                         break;
11106
11107                 case PORT_FEATURE_LINK_SPEED_10M_HALF:
11108                         if (bp->port.supported[idx] & SUPPORTED_10baseT_Half) {
11109                                 bp->link_params.req_line_speed[idx] =
11110                                         SPEED_10;
11111                                 bp->link_params.req_duplex[idx] =
11112                                         DUPLEX_HALF;
11113                                 bp->port.advertising[idx] |=
11114                                         (ADVERTISED_10baseT_Half |
11115                                          ADVERTISED_TP);
11116                         } else {
11117                                 BNX2X_ERR("NVRAM config error. Invalid link_config 0x%x  speed_cap_mask 0x%x\n",
11118                                             link_config,
11119                                           bp->link_params.speed_cap_mask[idx]);
11120                                 return;
11121                         }
11122                         break;
11123
11124                 case PORT_FEATURE_LINK_SPEED_100M_FULL:
11125                         if (bp->port.supported[idx] &
11126                             SUPPORTED_100baseT_Full) {
11127                                 bp->link_params.req_line_speed[idx] =
11128                                         SPEED_100;
11129                                 bp->port.advertising[idx] |=
11130                                         (ADVERTISED_100baseT_Full |
11131                                          ADVERTISED_TP);
11132                         } else {
11133                                 BNX2X_ERR("NVRAM config error. Invalid link_config 0x%x  speed_cap_mask 0x%x\n",
11134                                             link_config,
11135                                           bp->link_params.speed_cap_mask[idx]);
11136                                 return;
11137                         }
11138                         break;
11139
11140                 case PORT_FEATURE_LINK_SPEED_100M_HALF:
11141                         if (bp->port.supported[idx] &
11142                             SUPPORTED_100baseT_Half) {
11143                                 bp->link_params.req_line_speed[idx] =
11144                                                                 SPEED_100;
11145                                 bp->link_params.req_duplex[idx] =
11146                                                                 DUPLEX_HALF;
11147                                 bp->port.advertising[idx] |=
11148                                         (ADVERTISED_100baseT_Half |
11149                                          ADVERTISED_TP);
11150                         } else {
11151                                 BNX2X_ERR("NVRAM config error. Invalid link_config 0x%x  speed_cap_mask 0x%x\n",
11152                                     link_config,
11153                                     bp->link_params.speed_cap_mask[idx]);
11154                                 return;
11155                         }
11156                         break;
11157
11158                 case PORT_FEATURE_LINK_SPEED_1G:
11159                         if (bp->port.supported[idx] &
11160                             SUPPORTED_1000baseT_Full) {
11161                                 bp->link_params.req_line_speed[idx] =
11162                                         SPEED_1000;
11163                                 bp->port.advertising[idx] |=
11164                                         (ADVERTISED_1000baseT_Full |
11165                                          ADVERTISED_TP);
11166                         } else if (bp->port.supported[idx] &
11167                                    SUPPORTED_1000baseKX_Full) {
11168                                 bp->link_params.req_line_speed[idx] =
11169                                         SPEED_1000;
11170                                 bp->port.advertising[idx] |=
11171                                         ADVERTISED_1000baseKX_Full;
11172                         } else {
11173                                 BNX2X_ERR("NVRAM config error. Invalid link_config 0x%x  speed_cap_mask 0x%x\n",
11174                                     link_config,
11175                                     bp->link_params.speed_cap_mask[idx]);
11176                                 return;
11177                         }
11178                         break;
11179
11180                 case PORT_FEATURE_LINK_SPEED_2_5G:
11181                         if (bp->port.supported[idx] &
11182                             SUPPORTED_2500baseX_Full) {
11183                                 bp->link_params.req_line_speed[idx] =
11184                                         SPEED_2500;
11185                                 bp->port.advertising[idx] |=
11186                                         (ADVERTISED_2500baseX_Full |
11187                                                 ADVERTISED_TP);
11188                         } else {
11189                                 BNX2X_ERR("NVRAM config error. Invalid link_config 0x%x  speed_cap_mask 0x%x\n",
11190                                     link_config,
11191                                     bp->link_params.speed_cap_mask[idx]);
11192                                 return;
11193                         }
11194                         break;
11195
11196                 case PORT_FEATURE_LINK_SPEED_10G_CX4:
11197                         if (bp->port.supported[idx] &
11198                             SUPPORTED_10000baseT_Full) {
11199                                 bp->link_params.req_line_speed[idx] =
11200                                         SPEED_10000;
11201                                 bp->port.advertising[idx] |=
11202                                         (ADVERTISED_10000baseT_Full |
11203                                                 ADVERTISED_FIBRE);
11204                         } else if (bp->port.supported[idx] &
11205                                    SUPPORTED_10000baseKR_Full) {
11206                                 bp->link_params.req_line_speed[idx] =
11207                                         SPEED_10000;
11208                                 bp->port.advertising[idx] |=
11209                                         (ADVERTISED_10000baseKR_Full |
11210                                                 ADVERTISED_FIBRE);
11211                         } else {
11212                                 BNX2X_ERR("NVRAM config error. Invalid link_config 0x%x  speed_cap_mask 0x%x\n",
11213                                     link_config,
11214                                     bp->link_params.speed_cap_mask[idx]);
11215                                 return;
11216                         }
11217                         break;
11218                 case PORT_FEATURE_LINK_SPEED_20G:
11219                         bp->link_params.req_line_speed[idx] = SPEED_20000;
11220
11221                         break;
11222                 default:
11223                         BNX2X_ERR("NVRAM config error. BAD link speed link_config 0x%x\n",
11224                                   link_config);
11225                                 bp->link_params.req_line_speed[idx] =
11226                                                         SPEED_AUTO_NEG;
11227                                 bp->port.advertising[idx] =
11228                                                 bp->port.supported[idx];
11229                         break;
11230                 }
11231
11232                 bp->link_params.req_flow_ctrl[idx] = (link_config &
11233                                          PORT_FEATURE_FLOW_CONTROL_MASK);
11234                 if (bp->link_params.req_flow_ctrl[idx] ==
11235                     BNX2X_FLOW_CTRL_AUTO) {
11236                         if (!(bp->port.supported[idx] & SUPPORTED_Autoneg))
11237                                 bp->link_params.req_flow_ctrl[idx] =
11238                                                         BNX2X_FLOW_CTRL_NONE;
11239                         else
11240                                 bnx2x_set_requested_fc(bp);
11241                 }
11242
11243                 BNX2X_DEV_INFO("req_line_speed %d  req_duplex %d req_flow_ctrl 0x%x advertising 0x%x\n",
11244                                bp->link_params.req_line_speed[idx],
11245                                bp->link_params.req_duplex[idx],
11246                                bp->link_params.req_flow_ctrl[idx],
11247                                bp->port.advertising[idx]);
11248         }
11249 }
11250
11251 static void bnx2x_set_mac_buf(u8 *mac_buf, u32 mac_lo, u16 mac_hi)
11252 {
11253         __be16 mac_hi_be = cpu_to_be16(mac_hi);
11254         __be32 mac_lo_be = cpu_to_be32(mac_lo);
11255         memcpy(mac_buf, &mac_hi_be, sizeof(mac_hi_be));
11256         memcpy(mac_buf + sizeof(mac_hi_be), &mac_lo_be, sizeof(mac_lo_be));
11257 }
11258
11259 static void bnx2x_get_port_hwinfo(struct bnx2x *bp)
11260 {
11261         int port = BP_PORT(bp);
11262         u32 config;
11263         u32 ext_phy_type, ext_phy_config, eee_mode;
11264
11265         bp->link_params.bp = bp;
11266         bp->link_params.port = port;
11267
11268         bp->link_params.lane_config =
11269                 SHMEM_RD(bp, dev_info.port_hw_config[port].lane_config);
11270
11271         bp->link_params.speed_cap_mask[0] =
11272                 SHMEM_RD(bp,
11273                          dev_info.port_hw_config[port].speed_capability_mask) &
11274                 PORT_HW_CFG_SPEED_CAPABILITY_D0_MASK;
11275         bp->link_params.speed_cap_mask[1] =
11276                 SHMEM_RD(bp,
11277                          dev_info.port_hw_config[port].speed_capability_mask2) &
11278                 PORT_HW_CFG_SPEED_CAPABILITY_D0_MASK;
11279         bp->port.link_config[0] =
11280                 SHMEM_RD(bp, dev_info.port_feature_config[port].link_config);
11281
11282         bp->port.link_config[1] =
11283                 SHMEM_RD(bp, dev_info.port_feature_config[port].link_config2);
11284
11285         bp->link_params.multi_phy_config =
11286                 SHMEM_RD(bp, dev_info.port_hw_config[port].multi_phy_config);
11287         /* If the device is capable of WoL, set the default state according
11288          * to the HW
11289          */
11290         config = SHMEM_RD(bp, dev_info.port_feature_config[port].config);
11291         bp->wol = (!(bp->flags & NO_WOL_FLAG) &&
11292                    (config & PORT_FEATURE_WOL_ENABLED));
11293
11294         if ((config & PORT_FEAT_CFG_STORAGE_PERSONALITY_MASK) ==
11295             PORT_FEAT_CFG_STORAGE_PERSONALITY_FCOE && !IS_MF(bp))
11296                 bp->flags |= NO_ISCSI_FLAG;
11297         if ((config & PORT_FEAT_CFG_STORAGE_PERSONALITY_MASK) ==
11298             PORT_FEAT_CFG_STORAGE_PERSONALITY_ISCSI && !(IS_MF(bp)))
11299                 bp->flags |= NO_FCOE_FLAG;
11300
11301         BNX2X_DEV_INFO("lane_config 0x%08x  speed_cap_mask0 0x%08x  link_config0 0x%08x\n",
11302                        bp->link_params.lane_config,
11303                        bp->link_params.speed_cap_mask[0],
11304                        bp->port.link_config[0]);
11305
11306         bp->link_params.switch_cfg = (bp->port.link_config[0] &
11307                                       PORT_FEATURE_CONNECTED_SWITCH_MASK);
11308         bnx2x_phy_probe(&bp->link_params);
11309         bnx2x_link_settings_supported(bp, bp->link_params.switch_cfg);
11310
11311         bnx2x_link_settings_requested(bp);
11312
11313         /*
11314          * If connected directly, work with the internal PHY, otherwise, work
11315          * with the external PHY
11316          */
11317         ext_phy_config =
11318                 SHMEM_RD(bp,
11319                          dev_info.port_hw_config[port].external_phy_config);
11320         ext_phy_type = XGXS_EXT_PHY_TYPE(ext_phy_config);
11321         if (ext_phy_type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT)
11322                 bp->mdio.prtad = bp->port.phy_addr;
11323
11324         else if ((ext_phy_type != PORT_HW_CFG_XGXS_EXT_PHY_TYPE_FAILURE) &&
11325                  (ext_phy_type != PORT_HW_CFG_XGXS_EXT_PHY_TYPE_NOT_CONN))
11326                 bp->mdio.prtad =
11327                         XGXS_EXT_PHY_ADDR(ext_phy_config);
11328
11329         /* Configure link feature according to nvram value */
11330         eee_mode = (((SHMEM_RD(bp, dev_info.
11331                       port_feature_config[port].eee_power_mode)) &
11332                      PORT_FEAT_CFG_EEE_POWER_MODE_MASK) >>
11333                     PORT_FEAT_CFG_EEE_POWER_MODE_SHIFT);
11334         if (eee_mode != PORT_FEAT_CFG_EEE_POWER_MODE_DISABLED) {
11335                 bp->link_params.eee_mode = EEE_MODE_ADV_LPI |
11336                                            EEE_MODE_ENABLE_LPI |
11337                                            EEE_MODE_OUTPUT_TIME;
11338         } else {
11339                 bp->link_params.eee_mode = 0;
11340         }
11341 }
11342
11343 void bnx2x_get_iscsi_info(struct bnx2x *bp)
11344 {
11345         u32 no_flags = NO_ISCSI_FLAG;
11346         int port = BP_PORT(bp);
11347         u32 max_iscsi_conn = FW_ENCODE_32BIT_PATTERN ^ SHMEM_RD(bp,
11348                                 drv_lic_key[port].max_iscsi_conn);
11349
11350         if (!CNIC_SUPPORT(bp)) {
11351                 bp->flags |= no_flags;
11352                 return;
11353         }
11354
11355         /* Get the number of maximum allowed iSCSI connections */
11356         bp->cnic_eth_dev.max_iscsi_conn =
11357                 (max_iscsi_conn & BNX2X_MAX_ISCSI_INIT_CONN_MASK) >>
11358                 BNX2X_MAX_ISCSI_INIT_CONN_SHIFT;
11359
11360         BNX2X_DEV_INFO("max_iscsi_conn 0x%x\n",
11361                        bp->cnic_eth_dev.max_iscsi_conn);
11362
11363         /*
11364          * If maximum allowed number of connections is zero -
11365          * disable the feature.
11366          */
11367         if (!bp->cnic_eth_dev.max_iscsi_conn)
11368                 bp->flags |= no_flags;
11369 }
11370
11371 static void bnx2x_get_ext_wwn_info(struct bnx2x *bp, int func)
11372 {
11373         /* Port info */
11374         bp->cnic_eth_dev.fcoe_wwn_port_name_hi =
11375                 MF_CFG_RD(bp, func_ext_config[func].fcoe_wwn_port_name_upper);
11376         bp->cnic_eth_dev.fcoe_wwn_port_name_lo =
11377                 MF_CFG_RD(bp, func_ext_config[func].fcoe_wwn_port_name_lower);
11378
11379         /* Node info */
11380         bp->cnic_eth_dev.fcoe_wwn_node_name_hi =
11381                 MF_CFG_RD(bp, func_ext_config[func].fcoe_wwn_node_name_upper);
11382         bp->cnic_eth_dev.fcoe_wwn_node_name_lo =
11383                 MF_CFG_RD(bp, func_ext_config[func].fcoe_wwn_node_name_lower);
11384 }
11385
11386 static int bnx2x_shared_fcoe_funcs(struct bnx2x *bp)
11387 {
11388         u8 count = 0;
11389
11390         if (IS_MF(bp)) {
11391                 u8 fid;
11392
11393                 /* iterate over absolute function ids for this path: */
11394                 for (fid = BP_PATH(bp); fid < E2_FUNC_MAX * 2; fid += 2) {
11395                         if (IS_MF_SD(bp)) {
11396                                 u32 cfg = MF_CFG_RD(bp,
11397                                                     func_mf_config[fid].config);
11398
11399                                 if (!(cfg & FUNC_MF_CFG_FUNC_HIDE) &&
11400                                     ((cfg & FUNC_MF_CFG_PROTOCOL_MASK) ==
11401                                             FUNC_MF_CFG_PROTOCOL_FCOE))
11402                                         count++;
11403                         } else {
11404                                 u32 cfg = MF_CFG_RD(bp,
11405                                                     func_ext_config[fid].
11406                                                                       func_cfg);
11407
11408                                 if ((cfg & MACP_FUNC_CFG_FLAGS_ENABLED) &&
11409                                     (cfg & MACP_FUNC_CFG_FLAGS_FCOE_OFFLOAD))
11410                                         count++;
11411                         }
11412                 }
11413         } else { /* SF */
11414                 int port, port_cnt = CHIP_MODE_IS_4_PORT(bp) ? 2 : 1;
11415
11416                 for (port = 0; port < port_cnt; port++) {
11417                         u32 lic = SHMEM_RD(bp,
11418                                            drv_lic_key[port].max_fcoe_conn) ^
11419                                   FW_ENCODE_32BIT_PATTERN;
11420                         if (lic)
11421                                 count++;
11422                 }
11423         }
11424
11425         return count;
11426 }
11427
11428 static void bnx2x_get_fcoe_info(struct bnx2x *bp)
11429 {
11430         int port = BP_PORT(bp);
11431         int func = BP_ABS_FUNC(bp);
11432         u32 max_fcoe_conn = FW_ENCODE_32BIT_PATTERN ^ SHMEM_RD(bp,
11433                                 drv_lic_key[port].max_fcoe_conn);
11434         u8 num_fcoe_func = bnx2x_shared_fcoe_funcs(bp);
11435
11436         if (!CNIC_SUPPORT(bp)) {
11437                 bp->flags |= NO_FCOE_FLAG;
11438                 return;
11439         }
11440
11441         /* Get the number of maximum allowed FCoE connections */
11442         bp->cnic_eth_dev.max_fcoe_conn =
11443                 (max_fcoe_conn & BNX2X_MAX_FCOE_INIT_CONN_MASK) >>
11444                 BNX2X_MAX_FCOE_INIT_CONN_SHIFT;
11445
11446         /* Calculate the number of maximum allowed FCoE tasks */
11447         bp->cnic_eth_dev.max_fcoe_exchanges = MAX_NUM_FCOE_TASKS_PER_ENGINE;
11448
11449         /* check if FCoE resources must be shared between different functions */
11450         if (num_fcoe_func)
11451                 bp->cnic_eth_dev.max_fcoe_exchanges /= num_fcoe_func;
11452
11453         /* Read the WWN: */
11454         if (!IS_MF(bp)) {
11455                 /* Port info */
11456                 bp->cnic_eth_dev.fcoe_wwn_port_name_hi =
11457                         SHMEM_RD(bp,
11458                                  dev_info.port_hw_config[port].
11459                                  fcoe_wwn_port_name_upper);
11460                 bp->cnic_eth_dev.fcoe_wwn_port_name_lo =
11461                         SHMEM_RD(bp,
11462                                  dev_info.port_hw_config[port].
11463                                  fcoe_wwn_port_name_lower);
11464
11465                 /* Node info */
11466                 bp->cnic_eth_dev.fcoe_wwn_node_name_hi =
11467                         SHMEM_RD(bp,
11468                                  dev_info.port_hw_config[port].
11469                                  fcoe_wwn_node_name_upper);
11470                 bp->cnic_eth_dev.fcoe_wwn_node_name_lo =
11471                         SHMEM_RD(bp,
11472                                  dev_info.port_hw_config[port].
11473                                  fcoe_wwn_node_name_lower);
11474         } else if (!IS_MF_SD(bp)) {
11475                 /* Read the WWN info only if the FCoE feature is enabled for
11476                  * this function.
11477                  */
11478                 if (BNX2X_HAS_MF_EXT_PROTOCOL_FCOE(bp))
11479                         bnx2x_get_ext_wwn_info(bp, func);
11480         } else {
11481                 if (BNX2X_IS_MF_SD_PROTOCOL_FCOE(bp) && !CHIP_IS_E1x(bp))
11482                         bnx2x_get_ext_wwn_info(bp, func);
11483         }
11484
11485         BNX2X_DEV_INFO("max_fcoe_conn 0x%x\n", bp->cnic_eth_dev.max_fcoe_conn);
11486
11487         /*
11488          * If maximum allowed number of connections is zero -
11489          * disable the feature.
11490          */
11491         if (!bp->cnic_eth_dev.max_fcoe_conn)
11492                 bp->flags |= NO_FCOE_FLAG;
11493 }
11494
11495 static void bnx2x_get_cnic_info(struct bnx2x *bp)
11496 {
11497         /*
11498          * iSCSI may be dynamically disabled but reading
11499          * info here we will decrease memory usage by driver
11500          * if the feature is disabled for good
11501          */
11502         bnx2x_get_iscsi_info(bp);
11503         bnx2x_get_fcoe_info(bp);
11504 }
11505
11506 static void bnx2x_get_cnic_mac_hwinfo(struct bnx2x *bp)
11507 {
11508         u32 val, val2;
11509         int func = BP_ABS_FUNC(bp);
11510         int port = BP_PORT(bp);
11511         u8 *iscsi_mac = bp->cnic_eth_dev.iscsi_mac;
11512         u8 *fip_mac = bp->fip_mac;
11513
11514         if (IS_MF(bp)) {
11515                 /* iSCSI and FCoE NPAR MACs: if there is no either iSCSI or
11516                  * FCoE MAC then the appropriate feature should be disabled.
11517                  * In non SD mode features configuration comes from struct
11518                  * func_ext_config.
11519                  */
11520                 if (!IS_MF_SD(bp)) {
11521                         u32 cfg = MF_CFG_RD(bp, func_ext_config[func].func_cfg);
11522                         if (cfg & MACP_FUNC_CFG_FLAGS_ISCSI_OFFLOAD) {
11523                                 val2 = MF_CFG_RD(bp, func_ext_config[func].
11524                                                  iscsi_mac_addr_upper);
11525                                 val = MF_CFG_RD(bp, func_ext_config[func].
11526                                                 iscsi_mac_addr_lower);
11527                                 bnx2x_set_mac_buf(iscsi_mac, val, val2);
11528                                 BNX2X_DEV_INFO
11529                                         ("Read iSCSI MAC: %pM\n", iscsi_mac);
11530                         } else {
11531                                 bp->flags |= NO_ISCSI_OOO_FLAG | NO_ISCSI_FLAG;
11532                         }
11533
11534                         if (cfg & MACP_FUNC_CFG_FLAGS_FCOE_OFFLOAD) {
11535                                 val2 = MF_CFG_RD(bp, func_ext_config[func].
11536                                                  fcoe_mac_addr_upper);
11537                                 val = MF_CFG_RD(bp, func_ext_config[func].
11538                                                 fcoe_mac_addr_lower);
11539                                 bnx2x_set_mac_buf(fip_mac, val, val2);
11540                                 BNX2X_DEV_INFO
11541                                         ("Read FCoE L2 MAC: %pM\n", fip_mac);
11542                         } else {
11543                                 bp->flags |= NO_FCOE_FLAG;
11544                         }
11545
11546                         bp->mf_ext_config = cfg;
11547
11548                 } else { /* SD MODE */
11549                         if (BNX2X_IS_MF_SD_PROTOCOL_ISCSI(bp)) {
11550                                 /* use primary mac as iscsi mac */
11551                                 memcpy(iscsi_mac, bp->dev->dev_addr, ETH_ALEN);
11552
11553                                 BNX2X_DEV_INFO("SD ISCSI MODE\n");
11554                                 BNX2X_DEV_INFO
11555                                         ("Read iSCSI MAC: %pM\n", iscsi_mac);
11556                         } else if (BNX2X_IS_MF_SD_PROTOCOL_FCOE(bp)) {
11557                                 /* use primary mac as fip mac */
11558                                 memcpy(fip_mac, bp->dev->dev_addr, ETH_ALEN);
11559                                 BNX2X_DEV_INFO("SD FCoE MODE\n");
11560                                 BNX2X_DEV_INFO
11561                                         ("Read FIP MAC: %pM\n", fip_mac);
11562                         }
11563                 }
11564
11565                 /* If this is a storage-only interface, use SAN mac as
11566                  * primary MAC. Notice that for SD this is already the case,
11567                  * as the SAN mac was copied from the primary MAC.
11568                  */
11569                 if (IS_MF_FCOE_AFEX(bp))
11570                         memcpy(bp->dev->dev_addr, fip_mac, ETH_ALEN);
11571         } else {
11572                 val2 = SHMEM_RD(bp, dev_info.port_hw_config[port].
11573                                 iscsi_mac_upper);
11574                 val = SHMEM_RD(bp, dev_info.port_hw_config[port].
11575                                iscsi_mac_lower);
11576                 bnx2x_set_mac_buf(iscsi_mac, val, val2);
11577
11578                 val2 = SHMEM_RD(bp, dev_info.port_hw_config[port].
11579                                 fcoe_fip_mac_upper);
11580                 val = SHMEM_RD(bp, dev_info.port_hw_config[port].
11581                                fcoe_fip_mac_lower);
11582                 bnx2x_set_mac_buf(fip_mac, val, val2);
11583         }
11584
11585         /* Disable iSCSI OOO if MAC configuration is invalid. */
11586         if (!is_valid_ether_addr(iscsi_mac)) {
11587                 bp->flags |= NO_ISCSI_OOO_FLAG | NO_ISCSI_FLAG;
11588                 eth_zero_addr(iscsi_mac);
11589         }
11590
11591         /* Disable FCoE if MAC configuration is invalid. */
11592         if (!is_valid_ether_addr(fip_mac)) {
11593                 bp->flags |= NO_FCOE_FLAG;
11594                 eth_zero_addr(bp->fip_mac);
11595         }
11596 }
11597
11598 static void bnx2x_get_mac_hwinfo(struct bnx2x *bp)
11599 {
11600         u32 val, val2;
11601         int func = BP_ABS_FUNC(bp);
11602         int port = BP_PORT(bp);
11603
11604         /* Zero primary MAC configuration */
11605         eth_zero_addr(bp->dev->dev_addr);
11606
11607         if (BP_NOMCP(bp)) {
11608                 BNX2X_ERROR("warning: random MAC workaround active\n");
11609                 eth_hw_addr_random(bp->dev);
11610         } else if (IS_MF(bp)) {
11611                 val2 = MF_CFG_RD(bp, func_mf_config[func].mac_upper);
11612                 val = MF_CFG_RD(bp, func_mf_config[func].mac_lower);
11613                 if ((val2 != FUNC_MF_CFG_UPPERMAC_DEFAULT) &&
11614                     (val != FUNC_MF_CFG_LOWERMAC_DEFAULT))
11615                         bnx2x_set_mac_buf(bp->dev->dev_addr, val, val2);
11616
11617                 if (CNIC_SUPPORT(bp))
11618                         bnx2x_get_cnic_mac_hwinfo(bp);
11619         } else {
11620                 /* in SF read MACs from port configuration */
11621                 val2 = SHMEM_RD(bp, dev_info.port_hw_config[port].mac_upper);
11622                 val = SHMEM_RD(bp, dev_info.port_hw_config[port].mac_lower);
11623                 bnx2x_set_mac_buf(bp->dev->dev_addr, val, val2);
11624
11625                 if (CNIC_SUPPORT(bp))
11626                         bnx2x_get_cnic_mac_hwinfo(bp);
11627         }
11628
11629         if (!BP_NOMCP(bp)) {
11630                 /* Read physical port identifier from shmem */
11631                 val2 = SHMEM_RD(bp, dev_info.port_hw_config[port].mac_upper);
11632                 val = SHMEM_RD(bp, dev_info.port_hw_config[port].mac_lower);
11633                 bnx2x_set_mac_buf(bp->phys_port_id, val, val2);
11634                 bp->flags |= HAS_PHYS_PORT_ID;
11635         }
11636
11637         memcpy(bp->link_params.mac_addr, bp->dev->dev_addr, ETH_ALEN);
11638
11639         if (!is_valid_ether_addr(bp->dev->dev_addr))
11640                 dev_err(&bp->pdev->dev,
11641                         "bad Ethernet MAC address configuration: %pM\n"
11642                         "change it manually before bringing up the appropriate network interface\n",
11643                         bp->dev->dev_addr);
11644 }
11645
11646 static bool bnx2x_get_dropless_info(struct bnx2x *bp)
11647 {
11648         int tmp;
11649         u32 cfg;
11650
11651         if (IS_VF(bp))
11652                 return false;
11653
11654         if (IS_MF(bp) && !CHIP_IS_E1x(bp)) {
11655                 /* Take function: tmp = func */
11656                 tmp = BP_ABS_FUNC(bp);
11657                 cfg = MF_CFG_RD(bp, func_ext_config[tmp].func_cfg);
11658                 cfg = !!(cfg & MACP_FUNC_CFG_PAUSE_ON_HOST_RING);
11659         } else {
11660                 /* Take port: tmp = port */
11661                 tmp = BP_PORT(bp);
11662                 cfg = SHMEM_RD(bp,
11663                                dev_info.port_hw_config[tmp].generic_features);
11664                 cfg = !!(cfg & PORT_HW_CFG_PAUSE_ON_HOST_RING_ENABLED);
11665         }
11666         return cfg;
11667 }
11668
11669 static void validate_set_si_mode(struct bnx2x *bp)
11670 {
11671         u8 func = BP_ABS_FUNC(bp);
11672         u32 val;
11673
11674         val = MF_CFG_RD(bp, func_mf_config[func].mac_upper);
11675
11676         /* check for legal mac (upper bytes) */
11677         if (val != 0xffff) {
11678                 bp->mf_mode = MULTI_FUNCTION_SI;
11679                 bp->mf_config[BP_VN(bp)] =
11680                         MF_CFG_RD(bp, func_mf_config[func].config);
11681         } else
11682                 BNX2X_DEV_INFO("illegal MAC address for SI\n");
11683 }
11684
11685 static int bnx2x_get_hwinfo(struct bnx2x *bp)
11686 {
11687         int /*abs*/func = BP_ABS_FUNC(bp);
11688         int vn, mfw_vn;
11689         u32 val = 0, val2 = 0;
11690         int rc = 0;
11691
11692         /* Validate that chip access is feasible */
11693         if (REG_RD(bp, MISC_REG_CHIP_NUM) == 0xffffffff) {
11694                 dev_err(&bp->pdev->dev,
11695                         "Chip read returns all Fs. Preventing probe from continuing\n");
11696                 return -EINVAL;
11697         }
11698
11699         bnx2x_get_common_hwinfo(bp);
11700
11701         /*
11702          * initialize IGU parameters
11703          */
11704         if (CHIP_IS_E1x(bp)) {
11705                 bp->common.int_block = INT_BLOCK_HC;
11706
11707                 bp->igu_dsb_id = DEF_SB_IGU_ID;
11708                 bp->igu_base_sb = 0;
11709         } else {
11710                 bp->common.int_block = INT_BLOCK_IGU;
11711
11712                 /* do not allow device reset during IGU info processing */
11713                 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_RESET);
11714
11715                 val = REG_RD(bp, IGU_REG_BLOCK_CONFIGURATION);
11716
11717                 if (val & IGU_BLOCK_CONFIGURATION_REG_BACKWARD_COMP_EN) {
11718                         int tout = 5000;
11719
11720                         BNX2X_DEV_INFO("FORCING Normal Mode\n");
11721
11722                         val &= ~(IGU_BLOCK_CONFIGURATION_REG_BACKWARD_COMP_EN);
11723                         REG_WR(bp, IGU_REG_BLOCK_CONFIGURATION, val);
11724                         REG_WR(bp, IGU_REG_RESET_MEMORIES, 0x7f);
11725
11726                         while (tout && REG_RD(bp, IGU_REG_RESET_MEMORIES)) {
11727                                 tout--;
11728                                 usleep_range(1000, 2000);
11729                         }
11730
11731                         if (REG_RD(bp, IGU_REG_RESET_MEMORIES)) {
11732                                 dev_err(&bp->pdev->dev,
11733                                         "FORCING Normal Mode failed!!!\n");
11734                                 bnx2x_release_hw_lock(bp,
11735                                                       HW_LOCK_RESOURCE_RESET);
11736                                 return -EPERM;
11737                         }
11738                 }
11739
11740                 if (val & IGU_BLOCK_CONFIGURATION_REG_BACKWARD_COMP_EN) {
11741                         BNX2X_DEV_INFO("IGU Backward Compatible Mode\n");
11742                         bp->common.int_block |= INT_BLOCK_MODE_BW_COMP;
11743                 } else
11744                         BNX2X_DEV_INFO("IGU Normal Mode\n");
11745
11746                 rc = bnx2x_get_igu_cam_info(bp);
11747                 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_RESET);
11748                 if (rc)
11749                         return rc;
11750         }
11751
11752         /*
11753          * set base FW non-default (fast path) status block id, this value is
11754          * used to initialize the fw_sb_id saved on the fp/queue structure to
11755          * determine the id used by the FW.
11756          */
11757         if (CHIP_IS_E1x(bp))
11758                 bp->base_fw_ndsb = BP_PORT(bp) * FP_SB_MAX_E1x + BP_L_ID(bp);
11759         else /*
11760               * 57712 - we currently use one FW SB per IGU SB (Rx and Tx of
11761               * the same queue are indicated on the same IGU SB). So we prefer
11762               * FW and IGU SBs to be the same value.
11763               */
11764                 bp->base_fw_ndsb = bp->igu_base_sb;
11765
11766         BNX2X_DEV_INFO("igu_dsb_id %d  igu_base_sb %d  igu_sb_cnt %d\n"
11767                        "base_fw_ndsb %d\n", bp->igu_dsb_id, bp->igu_base_sb,
11768                        bp->igu_sb_cnt, bp->base_fw_ndsb);
11769
11770         /*
11771          * Initialize MF configuration
11772          */
11773
11774         bp->mf_ov = 0;
11775         bp->mf_mode = 0;
11776         bp->mf_sub_mode = 0;
11777         vn = BP_VN(bp);
11778         mfw_vn = BP_FW_MB_IDX(bp);
11779
11780         if (!CHIP_IS_E1(bp) && !BP_NOMCP(bp)) {
11781                 BNX2X_DEV_INFO("shmem2base 0x%x, size %d, mfcfg offset %d\n",
11782                                bp->common.shmem2_base, SHMEM2_RD(bp, size),
11783                               (u32)offsetof(struct shmem2_region, mf_cfg_addr));
11784
11785                 if (SHMEM2_HAS(bp, mf_cfg_addr))
11786                         bp->common.mf_cfg_base = SHMEM2_RD(bp, mf_cfg_addr);
11787                 else
11788                         bp->common.mf_cfg_base = bp->common.shmem_base +
11789                                 offsetof(struct shmem_region, func_mb) +
11790                                 E1H_FUNC_MAX * sizeof(struct drv_func_mb);
11791                 /*
11792                  * get mf configuration:
11793                  * 1. Existence of MF configuration
11794                  * 2. MAC address must be legal (check only upper bytes)
11795                  *    for  Switch-Independent mode;
11796                  *    OVLAN must be legal for Switch-Dependent mode
11797                  * 3. SF_MODE configures specific MF mode
11798                  */
11799                 if (bp->common.mf_cfg_base != SHMEM_MF_CFG_ADDR_NONE) {
11800                         /* get mf configuration */
11801                         val = SHMEM_RD(bp,
11802                                        dev_info.shared_feature_config.config);
11803                         val &= SHARED_FEAT_CFG_FORCE_SF_MODE_MASK;
11804
11805                         switch (val) {
11806                         case SHARED_FEAT_CFG_FORCE_SF_MODE_SWITCH_INDEPT:
11807                                 validate_set_si_mode(bp);
11808                                 break;
11809                         case SHARED_FEAT_CFG_FORCE_SF_MODE_AFEX_MODE:
11810                                 if ((!CHIP_IS_E1x(bp)) &&
11811                                     (MF_CFG_RD(bp, func_mf_config[func].
11812                                                mac_upper) != 0xffff) &&
11813                                     (SHMEM2_HAS(bp,
11814                                                 afex_driver_support))) {
11815                                         bp->mf_mode = MULTI_FUNCTION_AFEX;
11816                                         bp->mf_config[vn] = MF_CFG_RD(bp,
11817                                                 func_mf_config[func].config);
11818                                 } else {
11819                                         BNX2X_DEV_INFO("can not configure afex mode\n");
11820                                 }
11821                                 break;
11822                         case SHARED_FEAT_CFG_FORCE_SF_MODE_MF_ALLOWED:
11823                                 /* get OV configuration */
11824                                 val = MF_CFG_RD(bp,
11825                                         func_mf_config[FUNC_0].e1hov_tag);
11826                                 val &= FUNC_MF_CFG_E1HOV_TAG_MASK;
11827
11828                                 if (val != FUNC_MF_CFG_E1HOV_TAG_DEFAULT) {
11829                                         bp->mf_mode = MULTI_FUNCTION_SD;
11830                                         bp->mf_config[vn] = MF_CFG_RD(bp,
11831                                                 func_mf_config[func].config);
11832                                 } else
11833                                         BNX2X_DEV_INFO("illegal OV for SD\n");
11834                                 break;
11835                         case SHARED_FEAT_CFG_FORCE_SF_MODE_BD_MODE:
11836                                 bp->mf_mode = MULTI_FUNCTION_SD;
11837                                 bp->mf_sub_mode = SUB_MF_MODE_BD;
11838                                 bp->mf_config[vn] =
11839                                         MF_CFG_RD(bp,
11840                                                   func_mf_config[func].config);
11841
11842                                 if (SHMEM2_HAS(bp, mtu_size)) {
11843                                         int mtu_idx = BP_FW_MB_IDX(bp);
11844                                         u16 mtu_size;
11845                                         u32 mtu;
11846
11847                                         mtu = SHMEM2_RD(bp, mtu_size[mtu_idx]);
11848                                         mtu_size = (u16)mtu;
11849                                         DP(NETIF_MSG_IFUP, "Read MTU size %04x [%08x]\n",
11850                                            mtu_size, mtu);
11851
11852                                         /* if valid: update device mtu */
11853                                         if (((mtu_size + ETH_HLEN) >=
11854                                              ETH_MIN_PACKET_SIZE) &&
11855                                             (mtu_size <=
11856                                              ETH_MAX_JUMBO_PACKET_SIZE))
11857                                                 bp->dev->mtu = mtu_size;
11858                                 }
11859                                 break;
11860                         case SHARED_FEAT_CFG_FORCE_SF_MODE_UFP_MODE:
11861                                 bp->mf_mode = MULTI_FUNCTION_SD;
11862                                 bp->mf_sub_mode = SUB_MF_MODE_UFP;
11863                                 bp->mf_config[vn] =
11864                                         MF_CFG_RD(bp,
11865                                                   func_mf_config[func].config);
11866                                 break;
11867                         case SHARED_FEAT_CFG_FORCE_SF_MODE_FORCED_SF:
11868                                 bp->mf_config[vn] = 0;
11869                                 break;
11870                         case SHARED_FEAT_CFG_FORCE_SF_MODE_EXTENDED_MODE:
11871                                 val2 = SHMEM_RD(bp,
11872                                         dev_info.shared_hw_config.config_3);
11873                                 val2 &= SHARED_HW_CFG_EXTENDED_MF_MODE_MASK;
11874                                 switch (val2) {
11875                                 case SHARED_HW_CFG_EXTENDED_MF_MODE_NPAR1_DOT_5:
11876                                         validate_set_si_mode(bp);
11877                                         bp->mf_sub_mode =
11878                                                         SUB_MF_MODE_NPAR1_DOT_5;
11879                                         break;
11880                                 default:
11881                                         /* Unknown configuration */
11882                                         bp->mf_config[vn] = 0;
11883                                         BNX2X_DEV_INFO("unknown extended MF mode 0x%x\n",
11884                                                        val);
11885                                 }
11886                                 break;
11887                         default:
11888                                 /* Unknown configuration: reset mf_config */
11889                                 bp->mf_config[vn] = 0;
11890                                 BNX2X_DEV_INFO("unknown MF mode 0x%x\n", val);
11891                         }
11892                 }
11893
11894                 BNX2X_DEV_INFO("%s function mode\n",
11895                                IS_MF(bp) ? "multi" : "single");
11896
11897                 switch (bp->mf_mode) {
11898                 case MULTI_FUNCTION_SD:
11899                         val = MF_CFG_RD(bp, func_mf_config[func].e1hov_tag) &
11900                               FUNC_MF_CFG_E1HOV_TAG_MASK;
11901                         if (val != FUNC_MF_CFG_E1HOV_TAG_DEFAULT) {
11902                                 bp->mf_ov = val;
11903                                 bp->path_has_ovlan = true;
11904
11905                                 BNX2X_DEV_INFO("MF OV for func %d is %d (0x%04x)\n",
11906                                                func, bp->mf_ov, bp->mf_ov);
11907                         } else if ((bp->mf_sub_mode == SUB_MF_MODE_UFP) ||
11908                                    (bp->mf_sub_mode == SUB_MF_MODE_BD)) {
11909                                 dev_err(&bp->pdev->dev,
11910                                         "Unexpected - no valid MF OV for func %d in UFP/BD mode\n",
11911                                         func);
11912                                 bp->path_has_ovlan = true;
11913                         } else {
11914                                 dev_err(&bp->pdev->dev,
11915                                         "No valid MF OV for func %d, aborting\n",
11916                                         func);
11917                                 return -EPERM;
11918                         }
11919                         break;
11920                 case MULTI_FUNCTION_AFEX:
11921                         BNX2X_DEV_INFO("func %d is in MF afex mode\n", func);
11922                         break;
11923                 case MULTI_FUNCTION_SI:
11924                         BNX2X_DEV_INFO("func %d is in MF switch-independent mode\n",
11925                                        func);
11926                         break;
11927                 default:
11928                         if (vn) {
11929                                 dev_err(&bp->pdev->dev,
11930                                         "VN %d is in a single function mode, aborting\n",
11931                                         vn);
11932                                 return -EPERM;
11933                         }
11934                         break;
11935                 }
11936
11937                 /* check if other port on the path needs ovlan:
11938                  * Since MF configuration is shared between ports
11939                  * Possible mixed modes are only
11940                  * {SF, SI} {SF, SD} {SD, SF} {SI, SF}
11941                  */
11942                 if (CHIP_MODE_IS_4_PORT(bp) &&
11943                     !bp->path_has_ovlan &&
11944                     !IS_MF(bp) &&
11945                     bp->common.mf_cfg_base != SHMEM_MF_CFG_ADDR_NONE) {
11946                         u8 other_port = !BP_PORT(bp);
11947                         u8 other_func = BP_PATH(bp) + 2*other_port;
11948                         val = MF_CFG_RD(bp,
11949                                         func_mf_config[other_func].e1hov_tag);
11950                         if (val != FUNC_MF_CFG_E1HOV_TAG_DEFAULT)
11951                                 bp->path_has_ovlan = true;
11952                 }
11953         }
11954
11955         /* adjust igu_sb_cnt to MF for E1H */
11956         if (CHIP_IS_E1H(bp) && IS_MF(bp))
11957                 bp->igu_sb_cnt = min_t(u8, bp->igu_sb_cnt, E1H_MAX_MF_SB_COUNT);
11958
11959         /* port info */
11960         bnx2x_get_port_hwinfo(bp);
11961
11962         /* Get MAC addresses */
11963         bnx2x_get_mac_hwinfo(bp);
11964
11965         bnx2x_get_cnic_info(bp);
11966
11967         return rc;
11968 }
11969
11970 static void bnx2x_read_fwinfo(struct bnx2x *bp)
11971 {
11972         int cnt, i, block_end, rodi;
11973         char vpd_start[BNX2X_VPD_LEN+1];
11974         char str_id_reg[VENDOR_ID_LEN+1];
11975         char str_id_cap[VENDOR_ID_LEN+1];
11976         char *vpd_data;
11977         char *vpd_extended_data = NULL;
11978         u8 len;
11979
11980         cnt = pci_read_vpd(bp->pdev, 0, BNX2X_VPD_LEN, vpd_start);
11981         memset(bp->fw_ver, 0, sizeof(bp->fw_ver));
11982
11983         if (cnt < BNX2X_VPD_LEN)
11984                 goto out_not_found;
11985
11986         /* VPD RO tag should be first tag after identifier string, hence
11987          * we should be able to find it in first BNX2X_VPD_LEN chars
11988          */
11989         i = pci_vpd_find_tag(vpd_start, 0, BNX2X_VPD_LEN,
11990                              PCI_VPD_LRDT_RO_DATA);
11991         if (i < 0)
11992                 goto out_not_found;
11993
11994         block_end = i + PCI_VPD_LRDT_TAG_SIZE +
11995                     pci_vpd_lrdt_size(&vpd_start[i]);
11996
11997         i += PCI_VPD_LRDT_TAG_SIZE;
11998
11999         if (block_end > BNX2X_VPD_LEN) {
12000                 vpd_extended_data = kmalloc(block_end, GFP_KERNEL);
12001                 if (vpd_extended_data  == NULL)
12002                         goto out_not_found;
12003
12004                 /* read rest of vpd image into vpd_extended_data */
12005                 memcpy(vpd_extended_data, vpd_start, BNX2X_VPD_LEN);
12006                 cnt = pci_read_vpd(bp->pdev, BNX2X_VPD_LEN,
12007                                    block_end - BNX2X_VPD_LEN,
12008                                    vpd_extended_data + BNX2X_VPD_LEN);
12009                 if (cnt < (block_end - BNX2X_VPD_LEN))
12010                         goto out_not_found;
12011                 vpd_data = vpd_extended_data;
12012         } else
12013                 vpd_data = vpd_start;
12014
12015         /* now vpd_data holds full vpd content in both cases */
12016
12017         rodi = pci_vpd_find_info_keyword(vpd_data, i, block_end,
12018                                    PCI_VPD_RO_KEYWORD_MFR_ID);
12019         if (rodi < 0)
12020                 goto out_not_found;
12021
12022         len = pci_vpd_info_field_size(&vpd_data[rodi]);
12023
12024         if (len != VENDOR_ID_LEN)
12025                 goto out_not_found;
12026
12027         rodi += PCI_VPD_INFO_FLD_HDR_SIZE;
12028
12029         /* vendor specific info */
12030         snprintf(str_id_reg, VENDOR_ID_LEN + 1, "%04x", PCI_VENDOR_ID_DELL);
12031         snprintf(str_id_cap, VENDOR_ID_LEN + 1, "%04X", PCI_VENDOR_ID_DELL);
12032         if (!strncmp(str_id_reg, &vpd_data[rodi], VENDOR_ID_LEN) ||
12033             !strncmp(str_id_cap, &vpd_data[rodi], VENDOR_ID_LEN)) {
12034
12035                 rodi = pci_vpd_find_info_keyword(vpd_data, i, block_end,
12036                                                 PCI_VPD_RO_KEYWORD_VENDOR0);
12037                 if (rodi >= 0) {
12038                         len = pci_vpd_info_field_size(&vpd_data[rodi]);
12039
12040                         rodi += PCI_VPD_INFO_FLD_HDR_SIZE;
12041
12042                         if (len < 32 && (len + rodi) <= BNX2X_VPD_LEN) {
12043                                 memcpy(bp->fw_ver, &vpd_data[rodi], len);
12044                                 bp->fw_ver[len] = ' ';
12045                         }
12046                 }
12047                 kfree(vpd_extended_data);
12048                 return;
12049         }
12050 out_not_found:
12051         kfree(vpd_extended_data);
12052         return;
12053 }
12054
12055 static void bnx2x_set_modes_bitmap(struct bnx2x *bp)
12056 {
12057         u32 flags = 0;
12058
12059         if (CHIP_REV_IS_FPGA(bp))
12060                 SET_FLAGS(flags, MODE_FPGA);
12061         else if (CHIP_REV_IS_EMUL(bp))
12062                 SET_FLAGS(flags, MODE_EMUL);
12063         else
12064                 SET_FLAGS(flags, MODE_ASIC);
12065
12066         if (CHIP_MODE_IS_4_PORT(bp))
12067                 SET_FLAGS(flags, MODE_PORT4);
12068         else
12069                 SET_FLAGS(flags, MODE_PORT2);
12070
12071         if (CHIP_IS_E2(bp))
12072                 SET_FLAGS(flags, MODE_E2);
12073         else if (CHIP_IS_E3(bp)) {
12074                 SET_FLAGS(flags, MODE_E3);
12075                 if (CHIP_REV(bp) == CHIP_REV_Ax)
12076                         SET_FLAGS(flags, MODE_E3_A0);
12077                 else /*if (CHIP_REV(bp) == CHIP_REV_Bx)*/
12078                         SET_FLAGS(flags, MODE_E3_B0 | MODE_COS3);
12079         }
12080
12081         if (IS_MF(bp)) {
12082                 SET_FLAGS(flags, MODE_MF);
12083                 switch (bp->mf_mode) {
12084                 case MULTI_FUNCTION_SD:
12085                         SET_FLAGS(flags, MODE_MF_SD);
12086                         break;
12087                 case MULTI_FUNCTION_SI:
12088                         SET_FLAGS(flags, MODE_MF_SI);
12089                         break;
12090                 case MULTI_FUNCTION_AFEX:
12091                         SET_FLAGS(flags, MODE_MF_AFEX);
12092                         break;
12093                 }
12094         } else
12095                 SET_FLAGS(flags, MODE_SF);
12096
12097 #if defined(__LITTLE_ENDIAN)
12098         SET_FLAGS(flags, MODE_LITTLE_ENDIAN);
12099 #else /*(__BIG_ENDIAN)*/
12100         SET_FLAGS(flags, MODE_BIG_ENDIAN);
12101 #endif
12102         INIT_MODE_FLAGS(bp) = flags;
12103 }
12104
12105 static int bnx2x_init_bp(struct bnx2x *bp)
12106 {
12107         int func;
12108         int rc;
12109
12110         mutex_init(&bp->port.phy_mutex);
12111         mutex_init(&bp->fw_mb_mutex);
12112         mutex_init(&bp->drv_info_mutex);
12113         sema_init(&bp->stats_lock, 1);
12114         bp->drv_info_mng_owner = false;
12115
12116         INIT_DELAYED_WORK(&bp->sp_task, bnx2x_sp_task);
12117         INIT_DELAYED_WORK(&bp->sp_rtnl_task, bnx2x_sp_rtnl_task);
12118         INIT_DELAYED_WORK(&bp->period_task, bnx2x_period_task);
12119         INIT_DELAYED_WORK(&bp->iov_task, bnx2x_iov_task);
12120         if (IS_PF(bp)) {
12121                 rc = bnx2x_get_hwinfo(bp);
12122                 if (rc)
12123                         return rc;
12124         } else {
12125                 eth_zero_addr(bp->dev->dev_addr);
12126         }
12127
12128         bnx2x_set_modes_bitmap(bp);
12129
12130         rc = bnx2x_alloc_mem_bp(bp);
12131         if (rc)
12132                 return rc;
12133
12134         bnx2x_read_fwinfo(bp);
12135
12136         func = BP_FUNC(bp);
12137
12138         /* need to reset chip if undi was active */
12139         if (IS_PF(bp) && !BP_NOMCP(bp)) {
12140                 /* init fw_seq */
12141                 bp->fw_seq =
12142                         SHMEM_RD(bp, func_mb[BP_FW_MB_IDX(bp)].drv_mb_header) &
12143                                                         DRV_MSG_SEQ_NUMBER_MASK;
12144                 BNX2X_DEV_INFO("fw_seq 0x%08x\n", bp->fw_seq);
12145
12146                 rc = bnx2x_prev_unload(bp);
12147                 if (rc) {
12148                         bnx2x_free_mem_bp(bp);
12149                         return rc;
12150                 }
12151         }
12152
12153         if (CHIP_REV_IS_FPGA(bp))
12154                 dev_err(&bp->pdev->dev, "FPGA detected\n");
12155
12156         if (BP_NOMCP(bp) && (func == 0))
12157                 dev_err(&bp->pdev->dev, "MCP disabled, must load devices in order!\n");
12158
12159         bp->disable_tpa = disable_tpa;
12160         bp->disable_tpa |= !!IS_MF_STORAGE_ONLY(bp);
12161         /* Reduce memory usage in kdump environment by disabling TPA */
12162         bp->disable_tpa |= is_kdump_kernel();
12163
12164         /* Set TPA flags */
12165         if (bp->disable_tpa) {
12166                 bp->dev->hw_features &= ~NETIF_F_LRO;
12167                 bp->dev->features &= ~NETIF_F_LRO;
12168         }
12169
12170         if (CHIP_IS_E1(bp))
12171                 bp->dropless_fc = 0;
12172         else
12173                 bp->dropless_fc = dropless_fc | bnx2x_get_dropless_info(bp);
12174
12175         bp->mrrs = mrrs;
12176
12177         bp->tx_ring_size = IS_MF_STORAGE_ONLY(bp) ? 0 : MAX_TX_AVAIL;
12178         if (IS_VF(bp))
12179                 bp->rx_ring_size = MAX_RX_AVAIL;
12180
12181         /* make sure that the numbers are in the right granularity */
12182         bp->tx_ticks = (50 / BNX2X_BTR) * BNX2X_BTR;
12183         bp->rx_ticks = (25 / BNX2X_BTR) * BNX2X_BTR;
12184
12185         bp->current_interval = CHIP_REV_IS_SLOW(bp) ? 5*HZ : HZ;
12186
12187         init_timer(&bp->timer);
12188         bp->timer.expires = jiffies + bp->current_interval;
12189         bp->timer.data = (unsigned long) bp;
12190         bp->timer.function = bnx2x_timer;
12191
12192         if (SHMEM2_HAS(bp, dcbx_lldp_params_offset) &&
12193             SHMEM2_HAS(bp, dcbx_lldp_dcbx_stat_offset) &&
12194             SHMEM2_RD(bp, dcbx_lldp_params_offset) &&
12195             SHMEM2_RD(bp, dcbx_lldp_dcbx_stat_offset)) {
12196                 bnx2x_dcbx_set_state(bp, true, BNX2X_DCBX_ENABLED_ON_NEG_ON);
12197                 bnx2x_dcbx_init_params(bp);
12198         } else {
12199                 bnx2x_dcbx_set_state(bp, false, BNX2X_DCBX_ENABLED_OFF);
12200         }
12201
12202         if (CHIP_IS_E1x(bp))
12203                 bp->cnic_base_cl_id = FP_SB_MAX_E1x;
12204         else
12205                 bp->cnic_base_cl_id = FP_SB_MAX_E2;
12206
12207         /* multiple tx priority */
12208         if (IS_VF(bp))
12209                 bp->max_cos = 1;
12210         else if (CHIP_IS_E1x(bp))
12211                 bp->max_cos = BNX2X_MULTI_TX_COS_E1X;
12212         else if (CHIP_IS_E2(bp) || CHIP_IS_E3A0(bp))
12213                 bp->max_cos = BNX2X_MULTI_TX_COS_E2_E3A0;
12214         else if (CHIP_IS_E3B0(bp))
12215                 bp->max_cos = BNX2X_MULTI_TX_COS_E3B0;
12216         else
12217                 BNX2X_ERR("unknown chip %x revision %x\n",
12218                           CHIP_NUM(bp), CHIP_REV(bp));
12219         BNX2X_DEV_INFO("set bp->max_cos to %d\n", bp->max_cos);
12220
12221         /* We need at least one default status block for slow-path events,
12222          * second status block for the L2 queue, and a third status block for
12223          * CNIC if supported.
12224          */
12225         if (IS_VF(bp))
12226                 bp->min_msix_vec_cnt = 1;
12227         else if (CNIC_SUPPORT(bp))
12228                 bp->min_msix_vec_cnt = 3;
12229         else /* PF w/o cnic */
12230                 bp->min_msix_vec_cnt = 2;
12231         BNX2X_DEV_INFO("bp->min_msix_vec_cnt %d", bp->min_msix_vec_cnt);
12232
12233         bp->dump_preset_idx = 1;
12234
12235         if (CHIP_IS_E3B0(bp))
12236                 bp->flags |= PTP_SUPPORTED;
12237
12238         return rc;
12239 }
12240
12241 /****************************************************************************
12242 * General service functions
12243 ****************************************************************************/
12244
12245 /*
12246  * net_device service functions
12247  */
12248
12249 /* called with rtnl_lock */
12250 static int bnx2x_open(struct net_device *dev)
12251 {
12252         struct bnx2x *bp = netdev_priv(dev);
12253         int rc;
12254
12255         bp->stats_init = true;
12256
12257         netif_carrier_off(dev);
12258
12259         bnx2x_set_power_state(bp, PCI_D0);
12260
12261         /* If parity had happen during the unload, then attentions
12262          * and/or RECOVERY_IN_PROGRES may still be set. In this case we
12263          * want the first function loaded on the current engine to
12264          * complete the recovery.
12265          * Parity recovery is only relevant for PF driver.
12266          */
12267         if (IS_PF(bp)) {
12268                 int other_engine = BP_PATH(bp) ? 0 : 1;
12269                 bool other_load_status, load_status;
12270                 bool global = false;
12271
12272                 other_load_status = bnx2x_get_load_status(bp, other_engine);
12273                 load_status = bnx2x_get_load_status(bp, BP_PATH(bp));
12274                 if (!bnx2x_reset_is_done(bp, BP_PATH(bp)) ||
12275                     bnx2x_chk_parity_attn(bp, &global, true)) {
12276                         do {
12277                                 /* If there are attentions and they are in a
12278                                  * global blocks, set the GLOBAL_RESET bit
12279                                  * regardless whether it will be this function
12280                                  * that will complete the recovery or not.
12281                                  */
12282                                 if (global)
12283                                         bnx2x_set_reset_global(bp);
12284
12285                                 /* Only the first function on the current
12286                                  * engine should try to recover in open. In case
12287                                  * of attentions in global blocks only the first
12288                                  * in the chip should try to recover.
12289                                  */
12290                                 if ((!load_status &&
12291                                      (!global || !other_load_status)) &&
12292                                       bnx2x_trylock_leader_lock(bp) &&
12293                                       !bnx2x_leader_reset(bp)) {
12294                                         netdev_info(bp->dev,
12295                                                     "Recovered in open\n");
12296                                         break;
12297                                 }
12298
12299                                 /* recovery has failed... */
12300                                 bnx2x_set_power_state(bp, PCI_D3hot);
12301                                 bp->recovery_state = BNX2X_RECOVERY_FAILED;
12302
12303                                 BNX2X_ERR("Recovery flow hasn't been properly completed yet. Try again later.\n"
12304                                           "If you still see this message after a few retries then power cycle is required.\n");
12305
12306                                 return -EAGAIN;
12307                         } while (0);
12308                 }
12309         }
12310
12311         bp->recovery_state = BNX2X_RECOVERY_DONE;
12312         rc = bnx2x_nic_load(bp, LOAD_OPEN);
12313         if (rc)
12314                 return rc;
12315         return 0;
12316 }
12317
12318 /* called with rtnl_lock */
12319 static int bnx2x_close(struct net_device *dev)
12320 {
12321         struct bnx2x *bp = netdev_priv(dev);
12322
12323         /* Unload the driver, release IRQs */
12324         bnx2x_nic_unload(bp, UNLOAD_CLOSE, false);
12325
12326         return 0;
12327 }
12328
12329 static int bnx2x_init_mcast_macs_list(struct bnx2x *bp,
12330                                       struct bnx2x_mcast_ramrod_params *p)
12331 {
12332         int mc_count = netdev_mc_count(bp->dev);
12333         struct bnx2x_mcast_list_elem *mc_mac =
12334                 kcalloc(mc_count, sizeof(*mc_mac), GFP_ATOMIC);
12335         struct netdev_hw_addr *ha;
12336
12337         if (!mc_mac)
12338                 return -ENOMEM;
12339
12340         INIT_LIST_HEAD(&p->mcast_list);
12341
12342         netdev_for_each_mc_addr(ha, bp->dev) {
12343                 mc_mac->mac = bnx2x_mc_addr(ha);
12344                 list_add_tail(&mc_mac->link, &p->mcast_list);
12345                 mc_mac++;
12346         }
12347
12348         p->mcast_list_len = mc_count;
12349
12350         return 0;
12351 }
12352
12353 static void bnx2x_free_mcast_macs_list(
12354         struct bnx2x_mcast_ramrod_params *p)
12355 {
12356         struct bnx2x_mcast_list_elem *mc_mac =
12357                 list_first_entry(&p->mcast_list, struct bnx2x_mcast_list_elem,
12358                                  link);
12359
12360         WARN_ON(!mc_mac);
12361         kfree(mc_mac);
12362 }
12363
12364 /**
12365  * bnx2x_set_uc_list - configure a new unicast MACs list.
12366  *
12367  * @bp: driver handle
12368  *
12369  * We will use zero (0) as a MAC type for these MACs.
12370  */
12371 static int bnx2x_set_uc_list(struct bnx2x *bp)
12372 {
12373         int rc;
12374         struct net_device *dev = bp->dev;
12375         struct netdev_hw_addr *ha;
12376         struct bnx2x_vlan_mac_obj *mac_obj = &bp->sp_objs->mac_obj;
12377         unsigned long ramrod_flags = 0;
12378
12379         /* First schedule a cleanup up of old configuration */
12380         rc = bnx2x_del_all_macs(bp, mac_obj, BNX2X_UC_LIST_MAC, false);
12381         if (rc < 0) {
12382                 BNX2X_ERR("Failed to schedule DELETE operations: %d\n", rc);
12383                 return rc;
12384         }
12385
12386         netdev_for_each_uc_addr(ha, dev) {
12387                 rc = bnx2x_set_mac_one(bp, bnx2x_uc_addr(ha), mac_obj, true,
12388                                        BNX2X_UC_LIST_MAC, &ramrod_flags);
12389                 if (rc == -EEXIST) {
12390                         DP(BNX2X_MSG_SP,
12391                            "Failed to schedule ADD operations: %d\n", rc);
12392                         /* do not treat adding same MAC as error */
12393                         rc = 0;
12394
12395                 } else if (rc < 0) {
12396
12397                         BNX2X_ERR("Failed to schedule ADD operations: %d\n",
12398                                   rc);
12399                         return rc;
12400                 }
12401         }
12402
12403         /* Execute the pending commands */
12404         __set_bit(RAMROD_CONT, &ramrod_flags);
12405         return bnx2x_set_mac_one(bp, NULL, mac_obj, false /* don't care */,
12406                                  BNX2X_UC_LIST_MAC, &ramrod_flags);
12407 }
12408
12409 static int bnx2x_set_mc_list(struct bnx2x *bp)
12410 {
12411         struct net_device *dev = bp->dev;
12412         struct bnx2x_mcast_ramrod_params rparam = {NULL};
12413         int rc = 0;
12414
12415         rparam.mcast_obj = &bp->mcast_obj;
12416
12417         /* first, clear all configured multicast MACs */
12418         rc = bnx2x_config_mcast(bp, &rparam, BNX2X_MCAST_CMD_DEL);
12419         if (rc < 0) {
12420                 BNX2X_ERR("Failed to clear multicast configuration: %d\n", rc);
12421                 return rc;
12422         }
12423
12424         /* then, configure a new MACs list */
12425         if (netdev_mc_count(dev)) {
12426                 rc = bnx2x_init_mcast_macs_list(bp, &rparam);
12427                 if (rc) {
12428                         BNX2X_ERR("Failed to create multicast MACs list: %d\n",
12429                                   rc);
12430                         return rc;
12431                 }
12432
12433                 /* Now add the new MACs */
12434                 rc = bnx2x_config_mcast(bp, &rparam,
12435                                         BNX2X_MCAST_CMD_ADD);
12436                 if (rc < 0)
12437                         BNX2X_ERR("Failed to set a new multicast configuration: %d\n",
12438                                   rc);
12439
12440                 bnx2x_free_mcast_macs_list(&rparam);
12441         }
12442
12443         return rc;
12444 }
12445
12446 /* If bp->state is OPEN, should be called with netif_addr_lock_bh() */
12447 static void bnx2x_set_rx_mode(struct net_device *dev)
12448 {
12449         struct bnx2x *bp = netdev_priv(dev);
12450
12451         if (bp->state != BNX2X_STATE_OPEN) {
12452                 DP(NETIF_MSG_IFUP, "state is %x, returning\n", bp->state);
12453                 return;
12454         } else {
12455                 /* Schedule an SP task to handle rest of change */
12456                 bnx2x_schedule_sp_rtnl(bp, BNX2X_SP_RTNL_RX_MODE,
12457                                        NETIF_MSG_IFUP);
12458         }
12459 }
12460
12461 void bnx2x_set_rx_mode_inner(struct bnx2x *bp)
12462 {
12463         u32 rx_mode = BNX2X_RX_MODE_NORMAL;
12464
12465         DP(NETIF_MSG_IFUP, "dev->flags = %x\n", bp->dev->flags);
12466
12467         netif_addr_lock_bh(bp->dev);
12468
12469         if (bp->dev->flags & IFF_PROMISC) {
12470                 rx_mode = BNX2X_RX_MODE_PROMISC;
12471         } else if ((bp->dev->flags & IFF_ALLMULTI) ||
12472                    ((netdev_mc_count(bp->dev) > BNX2X_MAX_MULTICAST) &&
12473                     CHIP_IS_E1(bp))) {
12474                 rx_mode = BNX2X_RX_MODE_ALLMULTI;
12475         } else {
12476                 if (IS_PF(bp)) {
12477                         /* some multicasts */
12478                         if (bnx2x_set_mc_list(bp) < 0)
12479                                 rx_mode = BNX2X_RX_MODE_ALLMULTI;
12480
12481                         /* release bh lock, as bnx2x_set_uc_list might sleep */
12482                         netif_addr_unlock_bh(bp->dev);
12483                         if (bnx2x_set_uc_list(bp) < 0)
12484                                 rx_mode = BNX2X_RX_MODE_PROMISC;
12485                         netif_addr_lock_bh(bp->dev);
12486                 } else {
12487                         /* configuring mcast to a vf involves sleeping (when we
12488                          * wait for the pf's response).
12489                          */
12490                         bnx2x_schedule_sp_rtnl(bp,
12491                                                BNX2X_SP_RTNL_VFPF_MCAST, 0);
12492                 }
12493         }
12494
12495         bp->rx_mode = rx_mode;
12496         /* handle ISCSI SD mode */
12497         if (IS_MF_ISCSI_ONLY(bp))
12498                 bp->rx_mode = BNX2X_RX_MODE_NONE;
12499
12500         /* Schedule the rx_mode command */
12501         if (test_bit(BNX2X_FILTER_RX_MODE_PENDING, &bp->sp_state)) {
12502                 set_bit(BNX2X_FILTER_RX_MODE_SCHED, &bp->sp_state);
12503                 netif_addr_unlock_bh(bp->dev);
12504                 return;
12505         }
12506
12507         if (IS_PF(bp)) {
12508                 bnx2x_set_storm_rx_mode(bp);
12509                 netif_addr_unlock_bh(bp->dev);
12510         } else {
12511                 /* VF will need to request the PF to make this change, and so
12512                  * the VF needs to release the bottom-half lock prior to the
12513                  * request (as it will likely require sleep on the VF side)
12514                  */
12515                 netif_addr_unlock_bh(bp->dev);
12516                 bnx2x_vfpf_storm_rx_mode(bp);
12517         }
12518 }
12519
12520 /* called with rtnl_lock */
12521 static int bnx2x_mdio_read(struct net_device *netdev, int prtad,
12522                            int devad, u16 addr)
12523 {
12524         struct bnx2x *bp = netdev_priv(netdev);
12525         u16 value;
12526         int rc;
12527
12528         DP(NETIF_MSG_LINK, "mdio_read: prtad 0x%x, devad 0x%x, addr 0x%x\n",
12529            prtad, devad, addr);
12530
12531         /* The HW expects different devad if CL22 is used */
12532         devad = (devad == MDIO_DEVAD_NONE) ? DEFAULT_PHY_DEV_ADDR : devad;
12533
12534         bnx2x_acquire_phy_lock(bp);
12535         rc = bnx2x_phy_read(&bp->link_params, prtad, devad, addr, &value);
12536         bnx2x_release_phy_lock(bp);
12537         DP(NETIF_MSG_LINK, "mdio_read_val 0x%x rc = 0x%x\n", value, rc);
12538
12539         if (!rc)
12540                 rc = value;
12541         return rc;
12542 }
12543
12544 /* called with rtnl_lock */
12545 static int bnx2x_mdio_write(struct net_device *netdev, int prtad, int devad,
12546                             u16 addr, u16 value)
12547 {
12548         struct bnx2x *bp = netdev_priv(netdev);
12549         int rc;
12550
12551         DP(NETIF_MSG_LINK,
12552            "mdio_write: prtad 0x%x, devad 0x%x, addr 0x%x, value 0x%x\n",
12553            prtad, devad, addr, value);
12554
12555         /* The HW expects different devad if CL22 is used */
12556         devad = (devad == MDIO_DEVAD_NONE) ? DEFAULT_PHY_DEV_ADDR : devad;
12557
12558         bnx2x_acquire_phy_lock(bp);
12559         rc = bnx2x_phy_write(&bp->link_params, prtad, devad, addr, value);
12560         bnx2x_release_phy_lock(bp);
12561         return rc;
12562 }
12563
12564 /* called with rtnl_lock */
12565 static int bnx2x_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
12566 {
12567         struct bnx2x *bp = netdev_priv(dev);
12568         struct mii_ioctl_data *mdio = if_mii(ifr);
12569
12570         if (!netif_running(dev))
12571                 return -EAGAIN;
12572
12573         switch (cmd) {
12574         case SIOCSHWTSTAMP:
12575                 return bnx2x_hwtstamp_ioctl(bp, ifr);
12576         default:
12577                 DP(NETIF_MSG_LINK, "ioctl: phy id 0x%x, reg 0x%x, val_in 0x%x\n",
12578                    mdio->phy_id, mdio->reg_num, mdio->val_in);
12579                 return mdio_mii_ioctl(&bp->mdio, mdio, cmd);
12580         }
12581 }
12582
12583 #ifdef CONFIG_NET_POLL_CONTROLLER
12584 static void poll_bnx2x(struct net_device *dev)
12585 {
12586         struct bnx2x *bp = netdev_priv(dev);
12587         int i;
12588
12589         for_each_eth_queue(bp, i) {
12590                 struct bnx2x_fastpath *fp = &bp->fp[i];
12591                 napi_schedule(&bnx2x_fp(bp, fp->index, napi));
12592         }
12593 }
12594 #endif
12595
12596 static int bnx2x_validate_addr(struct net_device *dev)
12597 {
12598         struct bnx2x *bp = netdev_priv(dev);
12599
12600         /* query the bulletin board for mac address configured by the PF */
12601         if (IS_VF(bp))
12602                 bnx2x_sample_bulletin(bp);
12603
12604         if (!is_valid_ether_addr(dev->dev_addr)) {
12605                 BNX2X_ERR("Non-valid Ethernet address\n");
12606                 return -EADDRNOTAVAIL;
12607         }
12608         return 0;
12609 }
12610
12611 static int bnx2x_get_phys_port_id(struct net_device *netdev,
12612                                   struct netdev_phys_item_id *ppid)
12613 {
12614         struct bnx2x *bp = netdev_priv(netdev);
12615
12616         if (!(bp->flags & HAS_PHYS_PORT_ID))
12617                 return -EOPNOTSUPP;
12618
12619         ppid->id_len = sizeof(bp->phys_port_id);
12620         memcpy(ppid->id, bp->phys_port_id, ppid->id_len);
12621
12622         return 0;
12623 }
12624
12625 static netdev_features_t bnx2x_features_check(struct sk_buff *skb,
12626                                               struct net_device *dev,
12627                                               netdev_features_t features)
12628 {
12629         features = vlan_features_check(skb, features);
12630         return vxlan_features_check(skb, features);
12631 }
12632
12633 static const struct net_device_ops bnx2x_netdev_ops = {
12634         .ndo_open               = bnx2x_open,
12635         .ndo_stop               = bnx2x_close,
12636         .ndo_start_xmit         = bnx2x_start_xmit,
12637         .ndo_select_queue       = bnx2x_select_queue,
12638         .ndo_set_rx_mode        = bnx2x_set_rx_mode,
12639         .ndo_set_mac_address    = bnx2x_change_mac_addr,
12640         .ndo_validate_addr      = bnx2x_validate_addr,
12641         .ndo_do_ioctl           = bnx2x_ioctl,
12642         .ndo_change_mtu         = bnx2x_change_mtu,
12643         .ndo_fix_features       = bnx2x_fix_features,
12644         .ndo_set_features       = bnx2x_set_features,
12645         .ndo_tx_timeout         = bnx2x_tx_timeout,
12646 #ifdef CONFIG_NET_POLL_CONTROLLER
12647         .ndo_poll_controller    = poll_bnx2x,
12648 #endif
12649         .ndo_setup_tc           = bnx2x_setup_tc,
12650 #ifdef CONFIG_BNX2X_SRIOV
12651         .ndo_set_vf_mac         = bnx2x_set_vf_mac,
12652         .ndo_set_vf_vlan        = bnx2x_set_vf_vlan,
12653         .ndo_get_vf_config      = bnx2x_get_vf_config,
12654 #endif
12655 #ifdef NETDEV_FCOE_WWNN
12656         .ndo_fcoe_get_wwn       = bnx2x_fcoe_get_wwn,
12657 #endif
12658
12659 #ifdef CONFIG_NET_RX_BUSY_POLL
12660         .ndo_busy_poll          = bnx2x_low_latency_recv,
12661 #endif
12662         .ndo_get_phys_port_id   = bnx2x_get_phys_port_id,
12663         .ndo_set_vf_link_state  = bnx2x_set_vf_link_state,
12664         .ndo_features_check     = bnx2x_features_check,
12665 };
12666
12667 static int bnx2x_set_coherency_mask(struct bnx2x *bp)
12668 {
12669         struct device *dev = &bp->pdev->dev;
12670
12671         if (dma_set_mask_and_coherent(dev, DMA_BIT_MASK(64)) != 0 &&
12672             dma_set_mask_and_coherent(dev, DMA_BIT_MASK(32)) != 0) {
12673                 dev_err(dev, "System does not support DMA, aborting\n");
12674                 return -EIO;
12675         }
12676
12677         return 0;
12678 }
12679
12680 static void bnx2x_disable_pcie_error_reporting(struct bnx2x *bp)
12681 {
12682         if (bp->flags & AER_ENABLED) {
12683                 pci_disable_pcie_error_reporting(bp->pdev);
12684                 bp->flags &= ~AER_ENABLED;
12685         }
12686 }
12687
12688 static int bnx2x_init_dev(struct bnx2x *bp, struct pci_dev *pdev,
12689                           struct net_device *dev, unsigned long board_type)
12690 {
12691         int rc;
12692         u32 pci_cfg_dword;
12693         bool chip_is_e1x = (board_type == BCM57710 ||
12694                             board_type == BCM57711 ||
12695                             board_type == BCM57711E);
12696
12697         SET_NETDEV_DEV(dev, &pdev->dev);
12698
12699         bp->dev = dev;
12700         bp->pdev = pdev;
12701
12702         rc = pci_enable_device(pdev);
12703         if (rc) {
12704                 dev_err(&bp->pdev->dev,
12705                         "Cannot enable PCI device, aborting\n");
12706                 goto err_out;
12707         }
12708
12709         if (!(pci_resource_flags(pdev, 0) & IORESOURCE_MEM)) {
12710                 dev_err(&bp->pdev->dev,
12711                         "Cannot find PCI device base address, aborting\n");
12712                 rc = -ENODEV;
12713                 goto err_out_disable;
12714         }
12715
12716         if (IS_PF(bp) && !(pci_resource_flags(pdev, 2) & IORESOURCE_MEM)) {
12717                 dev_err(&bp->pdev->dev, "Cannot find second PCI device base address, aborting\n");
12718                 rc = -ENODEV;
12719                 goto err_out_disable;
12720         }
12721
12722         pci_read_config_dword(pdev, PCICFG_REVISION_ID_OFFSET, &pci_cfg_dword);
12723         if ((pci_cfg_dword & PCICFG_REVESION_ID_MASK) ==
12724             PCICFG_REVESION_ID_ERROR_VAL) {
12725                 pr_err("PCI device error, probably due to fan failure, aborting\n");
12726                 rc = -ENODEV;
12727                 goto err_out_disable;
12728         }
12729
12730         if (atomic_read(&pdev->enable_cnt) == 1) {
12731                 rc = pci_request_regions(pdev, DRV_MODULE_NAME);
12732                 if (rc) {
12733                         dev_err(&bp->pdev->dev,
12734                                 "Cannot obtain PCI resources, aborting\n");
12735                         goto err_out_disable;
12736                 }
12737
12738                 pci_set_master(pdev);
12739                 pci_save_state(pdev);
12740         }
12741
12742         if (IS_PF(bp)) {
12743                 if (!pdev->pm_cap) {
12744                         dev_err(&bp->pdev->dev,
12745                                 "Cannot find power management capability, aborting\n");
12746                         rc = -EIO;
12747                         goto err_out_release;
12748                 }
12749         }
12750
12751         if (!pci_is_pcie(pdev)) {
12752                 dev_err(&bp->pdev->dev, "Not PCI Express, aborting\n");
12753                 rc = -EIO;
12754                 goto err_out_release;
12755         }
12756
12757         rc = bnx2x_set_coherency_mask(bp);
12758         if (rc)
12759                 goto err_out_release;
12760
12761         dev->mem_start = pci_resource_start(pdev, 0);
12762         dev->base_addr = dev->mem_start;
12763         dev->mem_end = pci_resource_end(pdev, 0);
12764
12765         dev->irq = pdev->irq;
12766
12767         bp->regview = pci_ioremap_bar(pdev, 0);
12768         if (!bp->regview) {
12769                 dev_err(&bp->pdev->dev,
12770                         "Cannot map register space, aborting\n");
12771                 rc = -ENOMEM;
12772                 goto err_out_release;
12773         }
12774
12775         /* In E1/E1H use pci device function given by kernel.
12776          * In E2/E3 read physical function from ME register since these chips
12777          * support Physical Device Assignment where kernel BDF maybe arbitrary
12778          * (depending on hypervisor).
12779          */
12780         if (chip_is_e1x) {
12781                 bp->pf_num = PCI_FUNC(pdev->devfn);
12782         } else {
12783                 /* chip is E2/3*/
12784                 pci_read_config_dword(bp->pdev,
12785                                       PCICFG_ME_REGISTER, &pci_cfg_dword);
12786                 bp->pf_num = (u8)((pci_cfg_dword & ME_REG_ABS_PF_NUM) >>
12787                                   ME_REG_ABS_PF_NUM_SHIFT);
12788         }
12789         BNX2X_DEV_INFO("me reg PF num: %d\n", bp->pf_num);
12790
12791         /* clean indirect addresses */
12792         pci_write_config_dword(bp->pdev, PCICFG_GRC_ADDRESS,
12793                                PCICFG_VENDOR_ID_OFFSET);
12794
12795         /* Set PCIe reset type to fundamental for EEH recovery */
12796         pdev->needs_freset = 1;
12797
12798         /* AER (Advanced Error reporting) configuration */
12799         rc = pci_enable_pcie_error_reporting(pdev);
12800         if (!rc)
12801                 bp->flags |= AER_ENABLED;
12802         else
12803                 BNX2X_DEV_INFO("Failed To configure PCIe AER [%d]\n", rc);
12804
12805         /*
12806          * Clean the following indirect addresses for all functions since it
12807          * is not used by the driver.
12808          */
12809         if (IS_PF(bp)) {
12810                 REG_WR(bp, PXP2_REG_PGL_ADDR_88_F0, 0);
12811                 REG_WR(bp, PXP2_REG_PGL_ADDR_8C_F0, 0);
12812                 REG_WR(bp, PXP2_REG_PGL_ADDR_90_F0, 0);
12813                 REG_WR(bp, PXP2_REG_PGL_ADDR_94_F0, 0);
12814
12815                 if (chip_is_e1x) {
12816                         REG_WR(bp, PXP2_REG_PGL_ADDR_88_F1, 0);
12817                         REG_WR(bp, PXP2_REG_PGL_ADDR_8C_F1, 0);
12818                         REG_WR(bp, PXP2_REG_PGL_ADDR_90_F1, 0);
12819                         REG_WR(bp, PXP2_REG_PGL_ADDR_94_F1, 0);
12820                 }
12821
12822                 /* Enable internal target-read (in case we are probed after PF
12823                  * FLR). Must be done prior to any BAR read access. Only for
12824                  * 57712 and up
12825                  */
12826                 if (!chip_is_e1x)
12827                         REG_WR(bp,
12828                                PGLUE_B_REG_INTERNAL_PFID_ENABLE_TARGET_READ, 1);
12829         }
12830
12831         dev->watchdog_timeo = TX_TIMEOUT;
12832
12833         dev->netdev_ops = &bnx2x_netdev_ops;
12834         bnx2x_set_ethtool_ops(bp, dev);
12835
12836         dev->priv_flags |= IFF_UNICAST_FLT;
12837
12838         dev->hw_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM |
12839                 NETIF_F_TSO | NETIF_F_TSO_ECN | NETIF_F_TSO6 |
12840                 NETIF_F_RXCSUM | NETIF_F_LRO | NETIF_F_GRO |
12841                 NETIF_F_RXHASH | NETIF_F_HW_VLAN_CTAG_TX;
12842         if (!chip_is_e1x) {
12843                 dev->hw_features |= NETIF_F_GSO_GRE | NETIF_F_GSO_UDP_TUNNEL |
12844                                     NETIF_F_GSO_IPIP | NETIF_F_GSO_SIT;
12845                 dev->hw_enc_features =
12846                         NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM | NETIF_F_SG |
12847                         NETIF_F_TSO | NETIF_F_TSO_ECN | NETIF_F_TSO6 |
12848                         NETIF_F_GSO_IPIP |
12849                         NETIF_F_GSO_SIT |
12850                         NETIF_F_GSO_GRE | NETIF_F_GSO_UDP_TUNNEL;
12851         }
12852
12853         dev->vlan_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM |
12854                 NETIF_F_TSO | NETIF_F_TSO_ECN | NETIF_F_TSO6 | NETIF_F_HIGHDMA;
12855
12856         dev->features |= dev->hw_features | NETIF_F_HW_VLAN_CTAG_RX;
12857         dev->features |= NETIF_F_HIGHDMA;
12858
12859         /* Add Loopback capability to the device */
12860         dev->hw_features |= NETIF_F_LOOPBACK;
12861
12862 #ifdef BCM_DCBNL
12863         dev->dcbnl_ops = &bnx2x_dcbnl_ops;
12864 #endif
12865
12866         /* get_port_hwinfo() will set prtad and mmds properly */
12867         bp->mdio.prtad = MDIO_PRTAD_NONE;
12868         bp->mdio.mmds = 0;
12869         bp->mdio.mode_support = MDIO_SUPPORTS_C45 | MDIO_EMULATE_C22;
12870         bp->mdio.dev = dev;
12871         bp->mdio.mdio_read = bnx2x_mdio_read;
12872         bp->mdio.mdio_write = bnx2x_mdio_write;
12873
12874         return 0;
12875
12876 err_out_release:
12877         if (atomic_read(&pdev->enable_cnt) == 1)
12878                 pci_release_regions(pdev);
12879
12880 err_out_disable:
12881         pci_disable_device(pdev);
12882
12883 err_out:
12884         return rc;
12885 }
12886
12887 static int bnx2x_check_firmware(struct bnx2x *bp)
12888 {
12889         const struct firmware *firmware = bp->firmware;
12890         struct bnx2x_fw_file_hdr *fw_hdr;
12891         struct bnx2x_fw_file_section *sections;
12892         u32 offset, len, num_ops;
12893         __be16 *ops_offsets;
12894         int i;
12895         const u8 *fw_ver;
12896
12897         if (firmware->size < sizeof(struct bnx2x_fw_file_hdr)) {
12898                 BNX2X_ERR("Wrong FW size\n");
12899                 return -EINVAL;
12900         }
12901
12902         fw_hdr = (struct bnx2x_fw_file_hdr *)firmware->data;
12903         sections = (struct bnx2x_fw_file_section *)fw_hdr;
12904
12905         /* Make sure none of the offsets and sizes make us read beyond
12906          * the end of the firmware data */
12907         for (i = 0; i < sizeof(*fw_hdr) / sizeof(*sections); i++) {
12908                 offset = be32_to_cpu(sections[i].offset);
12909                 len = be32_to_cpu(sections[i].len);
12910                 if (offset + len > firmware->size) {
12911                         BNX2X_ERR("Section %d length is out of bounds\n", i);
12912                         return -EINVAL;
12913                 }
12914         }
12915
12916         /* Likewise for the init_ops offsets */
12917         offset = be32_to_cpu(fw_hdr->init_ops_offsets.offset);
12918         ops_offsets = (__force __be16 *)(firmware->data + offset);
12919         num_ops = be32_to_cpu(fw_hdr->init_ops.len) / sizeof(struct raw_op);
12920
12921         for (i = 0; i < be32_to_cpu(fw_hdr->init_ops_offsets.len) / 2; i++) {
12922                 if (be16_to_cpu(ops_offsets[i]) > num_ops) {
12923                         BNX2X_ERR("Section offset %d is out of bounds\n", i);
12924                         return -EINVAL;
12925                 }
12926         }
12927
12928         /* Check FW version */
12929         offset = be32_to_cpu(fw_hdr->fw_version.offset);
12930         fw_ver = firmware->data + offset;
12931         if ((fw_ver[0] != BCM_5710_FW_MAJOR_VERSION) ||
12932             (fw_ver[1] != BCM_5710_FW_MINOR_VERSION) ||
12933             (fw_ver[2] != BCM_5710_FW_REVISION_VERSION) ||
12934             (fw_ver[3] != BCM_5710_FW_ENGINEERING_VERSION)) {
12935                 BNX2X_ERR("Bad FW version:%d.%d.%d.%d. Should be %d.%d.%d.%d\n",
12936                        fw_ver[0], fw_ver[1], fw_ver[2], fw_ver[3],
12937                        BCM_5710_FW_MAJOR_VERSION,
12938                        BCM_5710_FW_MINOR_VERSION,
12939                        BCM_5710_FW_REVISION_VERSION,
12940                        BCM_5710_FW_ENGINEERING_VERSION);
12941                 return -EINVAL;
12942         }
12943
12944         return 0;
12945 }
12946
12947 static void be32_to_cpu_n(const u8 *_source, u8 *_target, u32 n)
12948 {
12949         const __be32 *source = (const __be32 *)_source;
12950         u32 *target = (u32 *)_target;
12951         u32 i;
12952
12953         for (i = 0; i < n/4; i++)
12954                 target[i] = be32_to_cpu(source[i]);
12955 }
12956
12957 /*
12958    Ops array is stored in the following format:
12959    {op(8bit), offset(24bit, big endian), data(32bit, big endian)}
12960  */
12961 static void bnx2x_prep_ops(const u8 *_source, u8 *_target, u32 n)
12962 {
12963         const __be32 *source = (const __be32 *)_source;
12964         struct raw_op *target = (struct raw_op *)_target;
12965         u32 i, j, tmp;
12966
12967         for (i = 0, j = 0; i < n/8; i++, j += 2) {
12968                 tmp = be32_to_cpu(source[j]);
12969                 target[i].op = (tmp >> 24) & 0xff;
12970                 target[i].offset = tmp & 0xffffff;
12971                 target[i].raw_data = be32_to_cpu(source[j + 1]);
12972         }
12973 }
12974
12975 /* IRO array is stored in the following format:
12976  * {base(24bit), m1(16bit), m2(16bit), m3(16bit), size(16bit) }
12977  */
12978 static void bnx2x_prep_iro(const u8 *_source, u8 *_target, u32 n)
12979 {
12980         const __be32 *source = (const __be32 *)_source;
12981         struct iro *target = (struct iro *)_target;
12982         u32 i, j, tmp;
12983
12984         for (i = 0, j = 0; i < n/sizeof(struct iro); i++) {
12985                 target[i].base = be32_to_cpu(source[j]);
12986                 j++;
12987                 tmp = be32_to_cpu(source[j]);
12988                 target[i].m1 = (tmp >> 16) & 0xffff;
12989                 target[i].m2 = tmp & 0xffff;
12990                 j++;
12991                 tmp = be32_to_cpu(source[j]);
12992                 target[i].m3 = (tmp >> 16) & 0xffff;
12993                 target[i].size = tmp & 0xffff;
12994                 j++;
12995         }
12996 }
12997
12998 static void be16_to_cpu_n(const u8 *_source, u8 *_target, u32 n)
12999 {
13000         const __be16 *source = (const __be16 *)_source;
13001         u16 *target = (u16 *)_target;
13002         u32 i;
13003
13004         for (i = 0; i < n/2; i++)
13005                 target[i] = be16_to_cpu(source[i]);
13006 }
13007
13008 #define BNX2X_ALLOC_AND_SET(arr, lbl, func)                             \
13009 do {                                                                    \
13010         u32 len = be32_to_cpu(fw_hdr->arr.len);                         \
13011         bp->arr = kmalloc(len, GFP_KERNEL);                             \
13012         if (!bp->arr)                                                   \
13013                 goto lbl;                                               \
13014         func(bp->firmware->data + be32_to_cpu(fw_hdr->arr.offset),      \
13015              (u8 *)bp->arr, len);                                       \
13016 } while (0)
13017
13018 static int bnx2x_init_firmware(struct bnx2x *bp)
13019 {
13020         const char *fw_file_name;
13021         struct bnx2x_fw_file_hdr *fw_hdr;
13022         int rc;
13023
13024         if (bp->firmware)
13025                 return 0;
13026
13027         if (CHIP_IS_E1(bp))
13028                 fw_file_name = FW_FILE_NAME_E1;
13029         else if (CHIP_IS_E1H(bp))
13030                 fw_file_name = FW_FILE_NAME_E1H;
13031         else if (!CHIP_IS_E1x(bp))
13032                 fw_file_name = FW_FILE_NAME_E2;
13033         else {
13034                 BNX2X_ERR("Unsupported chip revision\n");
13035                 return -EINVAL;
13036         }
13037         BNX2X_DEV_INFO("Loading %s\n", fw_file_name);
13038
13039         rc = request_firmware(&bp->firmware, fw_file_name, &bp->pdev->dev);
13040         if (rc) {
13041                 BNX2X_ERR("Can't load firmware file %s\n",
13042                           fw_file_name);
13043                 goto request_firmware_exit;
13044         }
13045
13046         rc = bnx2x_check_firmware(bp);
13047         if (rc) {
13048                 BNX2X_ERR("Corrupt firmware file %s\n", fw_file_name);
13049                 goto request_firmware_exit;
13050         }
13051
13052         fw_hdr = (struct bnx2x_fw_file_hdr *)bp->firmware->data;
13053
13054         /* Initialize the pointers to the init arrays */
13055         /* Blob */
13056         BNX2X_ALLOC_AND_SET(init_data, request_firmware_exit, be32_to_cpu_n);
13057
13058         /* Opcodes */
13059         BNX2X_ALLOC_AND_SET(init_ops, init_ops_alloc_err, bnx2x_prep_ops);
13060
13061         /* Offsets */
13062         BNX2X_ALLOC_AND_SET(init_ops_offsets, init_offsets_alloc_err,
13063                             be16_to_cpu_n);
13064
13065         /* STORMs firmware */
13066         INIT_TSEM_INT_TABLE_DATA(bp) = bp->firmware->data +
13067                         be32_to_cpu(fw_hdr->tsem_int_table_data.offset);
13068         INIT_TSEM_PRAM_DATA(bp)      = bp->firmware->data +
13069                         be32_to_cpu(fw_hdr->tsem_pram_data.offset);
13070         INIT_USEM_INT_TABLE_DATA(bp) = bp->firmware->data +
13071                         be32_to_cpu(fw_hdr->usem_int_table_data.offset);
13072         INIT_USEM_PRAM_DATA(bp)      = bp->firmware->data +
13073                         be32_to_cpu(fw_hdr->usem_pram_data.offset);
13074         INIT_XSEM_INT_TABLE_DATA(bp) = bp->firmware->data +
13075                         be32_to_cpu(fw_hdr->xsem_int_table_data.offset);
13076         INIT_XSEM_PRAM_DATA(bp)      = bp->firmware->data +
13077                         be32_to_cpu(fw_hdr->xsem_pram_data.offset);
13078         INIT_CSEM_INT_TABLE_DATA(bp) = bp->firmware->data +
13079                         be32_to_cpu(fw_hdr->csem_int_table_data.offset);
13080         INIT_CSEM_PRAM_DATA(bp)      = bp->firmware->data +
13081                         be32_to_cpu(fw_hdr->csem_pram_data.offset);
13082         /* IRO */
13083         BNX2X_ALLOC_AND_SET(iro_arr, iro_alloc_err, bnx2x_prep_iro);
13084
13085         return 0;
13086
13087 iro_alloc_err:
13088         kfree(bp->init_ops_offsets);
13089 init_offsets_alloc_err:
13090         kfree(bp->init_ops);
13091 init_ops_alloc_err:
13092         kfree(bp->init_data);
13093 request_firmware_exit:
13094         release_firmware(bp->firmware);
13095         bp->firmware = NULL;
13096
13097         return rc;
13098 }
13099
13100 static void bnx2x_release_firmware(struct bnx2x *bp)
13101 {
13102         kfree(bp->init_ops_offsets);
13103         kfree(bp->init_ops);
13104         kfree(bp->init_data);
13105         release_firmware(bp->firmware);
13106         bp->firmware = NULL;
13107 }
13108
13109 static struct bnx2x_func_sp_drv_ops bnx2x_func_sp_drv = {
13110         .init_hw_cmn_chip = bnx2x_init_hw_common_chip,
13111         .init_hw_cmn      = bnx2x_init_hw_common,
13112         .init_hw_port     = bnx2x_init_hw_port,
13113         .init_hw_func     = bnx2x_init_hw_func,
13114
13115         .reset_hw_cmn     = bnx2x_reset_common,
13116         .reset_hw_port    = bnx2x_reset_port,
13117         .reset_hw_func    = bnx2x_reset_func,
13118
13119         .gunzip_init      = bnx2x_gunzip_init,
13120         .gunzip_end       = bnx2x_gunzip_end,
13121
13122         .init_fw          = bnx2x_init_firmware,
13123         .release_fw       = bnx2x_release_firmware,
13124 };
13125
13126 void bnx2x__init_func_obj(struct bnx2x *bp)
13127 {
13128         /* Prepare DMAE related driver resources */
13129         bnx2x_setup_dmae(bp);
13130
13131         bnx2x_init_func_obj(bp, &bp->func_obj,
13132                             bnx2x_sp(bp, func_rdata),
13133                             bnx2x_sp_mapping(bp, func_rdata),
13134                             bnx2x_sp(bp, func_afex_rdata),
13135                             bnx2x_sp_mapping(bp, func_afex_rdata),
13136                             &bnx2x_func_sp_drv);
13137 }
13138
13139 /* must be called after sriov-enable */
13140 static int bnx2x_set_qm_cid_count(struct bnx2x *bp)
13141 {
13142         int cid_count = BNX2X_L2_MAX_CID(bp);
13143
13144         if (IS_SRIOV(bp))
13145                 cid_count += BNX2X_VF_CIDS;
13146
13147         if (CNIC_SUPPORT(bp))
13148                 cid_count += CNIC_CID_MAX;
13149
13150         return roundup(cid_count, QM_CID_ROUND);
13151 }
13152
13153 /**
13154  * bnx2x_get_num_none_def_sbs - return the number of none default SBs
13155  *
13156  * @dev:        pci device
13157  *
13158  */
13159 static int bnx2x_get_num_non_def_sbs(struct pci_dev *pdev, int cnic_cnt)
13160 {
13161         int index;
13162         u16 control = 0;
13163
13164         /*
13165          * If MSI-X is not supported - return number of SBs needed to support
13166          * one fast path queue: one FP queue + SB for CNIC
13167          */
13168         if (!pdev->msix_cap) {
13169                 dev_info(&pdev->dev, "no msix capability found\n");
13170                 return 1 + cnic_cnt;
13171         }
13172         dev_info(&pdev->dev, "msix capability found\n");
13173
13174         /*
13175          * The value in the PCI configuration space is the index of the last
13176          * entry, namely one less than the actual size of the table, which is
13177          * exactly what we want to return from this function: number of all SBs
13178          * without the default SB.
13179          * For VFs there is no default SB, then we return (index+1).
13180          */
13181         pci_read_config_word(pdev, pdev->msix_cap + PCI_MSIX_FLAGS, &control);
13182
13183         index = control & PCI_MSIX_FLAGS_QSIZE;
13184
13185         return index;
13186 }
13187
13188 static int set_max_cos_est(int chip_id)
13189 {
13190         switch (chip_id) {
13191         case BCM57710:
13192         case BCM57711:
13193         case BCM57711E:
13194                 return BNX2X_MULTI_TX_COS_E1X;
13195         case BCM57712:
13196         case BCM57712_MF:
13197                 return BNX2X_MULTI_TX_COS_E2_E3A0;
13198         case BCM57800:
13199         case BCM57800_MF:
13200         case BCM57810:
13201         case BCM57810_MF:
13202         case BCM57840_4_10:
13203         case BCM57840_2_20:
13204         case BCM57840_O:
13205         case BCM57840_MFO:
13206         case BCM57840_MF:
13207         case BCM57811:
13208         case BCM57811_MF:
13209                 return BNX2X_MULTI_TX_COS_E3B0;
13210         case BCM57712_VF:
13211         case BCM57800_VF:
13212         case BCM57810_VF:
13213         case BCM57840_VF:
13214         case BCM57811_VF:
13215                 return 1;
13216         default:
13217                 pr_err("Unknown board_type (%d), aborting\n", chip_id);
13218                 return -ENODEV;
13219         }
13220 }
13221
13222 static int set_is_vf(int chip_id)
13223 {
13224         switch (chip_id) {
13225         case BCM57712_VF:
13226         case BCM57800_VF:
13227         case BCM57810_VF:
13228         case BCM57840_VF:
13229         case BCM57811_VF:
13230                 return true;
13231         default:
13232                 return false;
13233         }
13234 }
13235
13236 /* nig_tsgen registers relative address */
13237 #define tsgen_ctrl 0x0
13238 #define tsgen_freecount 0x10
13239 #define tsgen_synctime_t0 0x20
13240 #define tsgen_offset_t0 0x28
13241 #define tsgen_drift_t0 0x30
13242 #define tsgen_synctime_t1 0x58
13243 #define tsgen_offset_t1 0x60
13244 #define tsgen_drift_t1 0x68
13245
13246 /* FW workaround for setting drift */
13247 static int bnx2x_send_update_drift_ramrod(struct bnx2x *bp, int drift_dir,
13248                                           int best_val, int best_period)
13249 {
13250         struct bnx2x_func_state_params func_params = {NULL};
13251         struct bnx2x_func_set_timesync_params *set_timesync_params =
13252                 &func_params.params.set_timesync;
13253
13254         /* Prepare parameters for function state transitions */
13255         __set_bit(RAMROD_COMP_WAIT, &func_params.ramrod_flags);
13256         __set_bit(RAMROD_RETRY, &func_params.ramrod_flags);
13257
13258         func_params.f_obj = &bp->func_obj;
13259         func_params.cmd = BNX2X_F_CMD_SET_TIMESYNC;
13260
13261         /* Function parameters */
13262         set_timesync_params->drift_adjust_cmd = TS_DRIFT_ADJUST_SET;
13263         set_timesync_params->offset_cmd = TS_OFFSET_KEEP;
13264         set_timesync_params->add_sub_drift_adjust_value =
13265                 drift_dir ? TS_ADD_VALUE : TS_SUB_VALUE;
13266         set_timesync_params->drift_adjust_value = best_val;
13267         set_timesync_params->drift_adjust_period = best_period;
13268
13269         return bnx2x_func_state_change(bp, &func_params);
13270 }
13271
13272 static int bnx2x_ptp_adjfreq(struct ptp_clock_info *ptp, s32 ppb)
13273 {
13274         struct bnx2x *bp = container_of(ptp, struct bnx2x, ptp_clock_info);
13275         int rc;
13276         int drift_dir = 1;
13277         int val, period, period1, period2, dif, dif1, dif2;
13278         int best_dif = BNX2X_MAX_PHC_DRIFT, best_period = 0, best_val = 0;
13279
13280         DP(BNX2X_MSG_PTP, "PTP adjfreq called, ppb = %d\n", ppb);
13281
13282         if (!netif_running(bp->dev)) {
13283                 DP(BNX2X_MSG_PTP,
13284                    "PTP adjfreq called while the interface is down\n");
13285                 return -EFAULT;
13286         }
13287
13288         if (ppb < 0) {
13289                 ppb = -ppb;
13290                 drift_dir = 0;
13291         }
13292
13293         if (ppb == 0) {
13294                 best_val = 1;
13295                 best_period = 0x1FFFFFF;
13296         } else if (ppb >= BNX2X_MAX_PHC_DRIFT) {
13297                 best_val = 31;
13298                 best_period = 1;
13299         } else {
13300                 /* Changed not to allow val = 8, 16, 24 as these values
13301                  * are not supported in workaround.
13302                  */
13303                 for (val = 0; val <= 31; val++) {
13304                         if ((val & 0x7) == 0)
13305                                 continue;
13306                         period1 = val * 1000000 / ppb;
13307                         period2 = period1 + 1;
13308                         if (period1 != 0)
13309                                 dif1 = ppb - (val * 1000000 / period1);
13310                         else
13311                                 dif1 = BNX2X_MAX_PHC_DRIFT;
13312                         if (dif1 < 0)
13313                                 dif1 = -dif1;
13314                         dif2 = ppb - (val * 1000000 / period2);
13315                         if (dif2 < 0)
13316                                 dif2 = -dif2;
13317                         dif = (dif1 < dif2) ? dif1 : dif2;
13318                         period = (dif1 < dif2) ? period1 : period2;
13319                         if (dif < best_dif) {
13320                                 best_dif = dif;
13321                                 best_val = val;
13322                                 best_period = period;
13323                         }
13324                 }
13325         }
13326
13327         rc = bnx2x_send_update_drift_ramrod(bp, drift_dir, best_val,
13328                                             best_period);
13329         if (rc) {
13330                 BNX2X_ERR("Failed to set drift\n");
13331                 return -EFAULT;
13332         }
13333
13334         DP(BNX2X_MSG_PTP, "Configured val = %d, period = %d\n", best_val,
13335            best_period);
13336
13337         return 0;
13338 }
13339
13340 static int bnx2x_ptp_adjtime(struct ptp_clock_info *ptp, s64 delta)
13341 {
13342         struct bnx2x *bp = container_of(ptp, struct bnx2x, ptp_clock_info);
13343
13344         DP(BNX2X_MSG_PTP, "PTP adjtime called, delta = %llx\n", delta);
13345
13346         timecounter_adjtime(&bp->timecounter, delta);
13347
13348         return 0;
13349 }
13350
13351 static int bnx2x_ptp_gettime(struct ptp_clock_info *ptp, struct timespec64 *ts)
13352 {
13353         struct bnx2x *bp = container_of(ptp, struct bnx2x, ptp_clock_info);
13354         u64 ns;
13355
13356         ns = timecounter_read(&bp->timecounter);
13357
13358         DP(BNX2X_MSG_PTP, "PTP gettime called, ns = %llu\n", ns);
13359
13360         *ts = ns_to_timespec64(ns);
13361
13362         return 0;
13363 }
13364
13365 static int bnx2x_ptp_settime(struct ptp_clock_info *ptp,
13366                              const struct timespec64 *ts)
13367 {
13368         struct bnx2x *bp = container_of(ptp, struct bnx2x, ptp_clock_info);
13369         u64 ns;
13370
13371         ns = timespec64_to_ns(ts);
13372
13373         DP(BNX2X_MSG_PTP, "PTP settime called, ns = %llu\n", ns);
13374
13375         /* Re-init the timecounter */
13376         timecounter_init(&bp->timecounter, &bp->cyclecounter, ns);
13377
13378         return 0;
13379 }
13380
13381 /* Enable (or disable) ancillary features of the phc subsystem */
13382 static int bnx2x_ptp_enable(struct ptp_clock_info *ptp,
13383                             struct ptp_clock_request *rq, int on)
13384 {
13385         struct bnx2x *bp = container_of(ptp, struct bnx2x, ptp_clock_info);
13386
13387         BNX2X_ERR("PHC ancillary features are not supported\n");
13388         return -ENOTSUPP;
13389 }
13390
13391 static void bnx2x_register_phc(struct bnx2x *bp)
13392 {
13393         /* Fill the ptp_clock_info struct and register PTP clock*/
13394         bp->ptp_clock_info.owner = THIS_MODULE;
13395         snprintf(bp->ptp_clock_info.name, 16, "%s", bp->dev->name);
13396         bp->ptp_clock_info.max_adj = BNX2X_MAX_PHC_DRIFT; /* In PPB */
13397         bp->ptp_clock_info.n_alarm = 0;
13398         bp->ptp_clock_info.n_ext_ts = 0;
13399         bp->ptp_clock_info.n_per_out = 0;
13400         bp->ptp_clock_info.pps = 0;
13401         bp->ptp_clock_info.adjfreq = bnx2x_ptp_adjfreq;
13402         bp->ptp_clock_info.adjtime = bnx2x_ptp_adjtime;
13403         bp->ptp_clock_info.gettime64 = bnx2x_ptp_gettime;
13404         bp->ptp_clock_info.settime64 = bnx2x_ptp_settime;
13405         bp->ptp_clock_info.enable = bnx2x_ptp_enable;
13406
13407         bp->ptp_clock = ptp_clock_register(&bp->ptp_clock_info, &bp->pdev->dev);
13408         if (IS_ERR(bp->ptp_clock)) {
13409                 bp->ptp_clock = NULL;
13410                 BNX2X_ERR("PTP clock registeration failed\n");
13411         }
13412 }
13413
13414 static int bnx2x_init_one(struct pci_dev *pdev,
13415                                     const struct pci_device_id *ent)
13416 {
13417         struct net_device *dev = NULL;
13418         struct bnx2x *bp;
13419         enum pcie_link_width pcie_width;
13420         enum pci_bus_speed pcie_speed;
13421         int rc, max_non_def_sbs;
13422         int rx_count, tx_count, rss_count, doorbell_size;
13423         int max_cos_est;
13424         bool is_vf;
13425         int cnic_cnt;
13426
13427         /* Management FW 'remembers' living interfaces. Allow it some time
13428          * to forget previously living interfaces, allowing a proper re-load.
13429          */
13430         if (is_kdump_kernel()) {
13431                 ktime_t now = ktime_get_boottime();
13432                 ktime_t fw_ready_time = ktime_set(5, 0);
13433
13434                 if (ktime_before(now, fw_ready_time))
13435                         msleep(ktime_ms_delta(fw_ready_time, now));
13436         }
13437
13438         /* An estimated maximum supported CoS number according to the chip
13439          * version.
13440          * We will try to roughly estimate the maximum number of CoSes this chip
13441          * may support in order to minimize the memory allocated for Tx
13442          * netdev_queue's. This number will be accurately calculated during the
13443          * initialization of bp->max_cos based on the chip versions AND chip
13444          * revision in the bnx2x_init_bp().
13445          */
13446         max_cos_est = set_max_cos_est(ent->driver_data);
13447         if (max_cos_est < 0)
13448                 return max_cos_est;
13449         is_vf = set_is_vf(ent->driver_data);
13450         cnic_cnt = is_vf ? 0 : 1;
13451
13452         max_non_def_sbs = bnx2x_get_num_non_def_sbs(pdev, cnic_cnt);
13453
13454         /* add another SB for VF as it has no default SB */
13455         max_non_def_sbs += is_vf ? 1 : 0;
13456
13457         /* Maximum number of RSS queues: one IGU SB goes to CNIC */
13458         rss_count = max_non_def_sbs - cnic_cnt;
13459
13460         if (rss_count < 1)
13461                 return -EINVAL;
13462
13463         /* Maximum number of netdev Rx queues: RSS + FCoE L2 */
13464         rx_count = rss_count + cnic_cnt;
13465
13466         /* Maximum number of netdev Tx queues:
13467          * Maximum TSS queues * Maximum supported number of CoS  + FCoE L2
13468          */
13469         tx_count = rss_count * max_cos_est + cnic_cnt;
13470
13471         /* dev zeroed in init_etherdev */
13472         dev = alloc_etherdev_mqs(sizeof(*bp), tx_count, rx_count);
13473         if (!dev)
13474                 return -ENOMEM;
13475
13476         bp = netdev_priv(dev);
13477
13478         bp->flags = 0;
13479         if (is_vf)
13480                 bp->flags |= IS_VF_FLAG;
13481
13482         bp->igu_sb_cnt = max_non_def_sbs;
13483         bp->igu_base_addr = IS_VF(bp) ? PXP_VF_ADDR_IGU_START : BAR_IGU_INTMEM;
13484         bp->msg_enable = debug;
13485         bp->cnic_support = cnic_cnt;
13486         bp->cnic_probe = bnx2x_cnic_probe;
13487
13488         pci_set_drvdata(pdev, dev);
13489
13490         rc = bnx2x_init_dev(bp, pdev, dev, ent->driver_data);
13491         if (rc < 0) {
13492                 free_netdev(dev);
13493                 return rc;
13494         }
13495
13496         BNX2X_DEV_INFO("This is a %s function\n",
13497                        IS_PF(bp) ? "physical" : "virtual");
13498         BNX2X_DEV_INFO("Cnic support is %s\n", CNIC_SUPPORT(bp) ? "on" : "off");
13499         BNX2X_DEV_INFO("Max num of status blocks %d\n", max_non_def_sbs);
13500         BNX2X_DEV_INFO("Allocated netdev with %d tx and %d rx queues\n",
13501                        tx_count, rx_count);
13502
13503         rc = bnx2x_init_bp(bp);
13504         if (rc)
13505                 goto init_one_exit;
13506
13507         /* Map doorbells here as we need the real value of bp->max_cos which
13508          * is initialized in bnx2x_init_bp() to determine the number of
13509          * l2 connections.
13510          */
13511         if (IS_VF(bp)) {
13512                 bp->doorbells = bnx2x_vf_doorbells(bp);
13513                 rc = bnx2x_vf_pci_alloc(bp);
13514                 if (rc)
13515                         goto init_one_exit;
13516         } else {
13517                 doorbell_size = BNX2X_L2_MAX_CID(bp) * (1 << BNX2X_DB_SHIFT);
13518                 if (doorbell_size > pci_resource_len(pdev, 2)) {
13519                         dev_err(&bp->pdev->dev,
13520                                 "Cannot map doorbells, bar size too small, aborting\n");
13521                         rc = -ENOMEM;
13522                         goto init_one_exit;
13523                 }
13524                 bp->doorbells = ioremap_nocache(pci_resource_start(pdev, 2),
13525                                                 doorbell_size);
13526         }
13527         if (!bp->doorbells) {
13528                 dev_err(&bp->pdev->dev,
13529                         "Cannot map doorbell space, aborting\n");
13530                 rc = -ENOMEM;
13531                 goto init_one_exit;
13532         }
13533
13534         if (IS_VF(bp)) {
13535                 rc = bnx2x_vfpf_acquire(bp, tx_count, rx_count);
13536                 if (rc)
13537                         goto init_one_exit;
13538         }
13539
13540         /* Enable SRIOV if capability found in configuration space */
13541         rc = bnx2x_iov_init_one(bp, int_mode, BNX2X_MAX_NUM_OF_VFS);
13542         if (rc)
13543                 goto init_one_exit;
13544
13545         /* calc qm_cid_count */
13546         bp->qm_cid_count = bnx2x_set_qm_cid_count(bp);
13547         BNX2X_DEV_INFO("qm_cid_count %d\n", bp->qm_cid_count);
13548
13549         /* disable FCOE L2 queue for E1x*/
13550         if (CHIP_IS_E1x(bp))
13551                 bp->flags |= NO_FCOE_FLAG;
13552
13553         /* Set bp->num_queues for MSI-X mode*/
13554         bnx2x_set_num_queues(bp);
13555
13556         /* Configure interrupt mode: try to enable MSI-X/MSI if
13557          * needed.
13558          */
13559         rc = bnx2x_set_int_mode(bp);
13560         if (rc) {
13561                 dev_err(&pdev->dev, "Cannot set interrupts\n");
13562                 goto init_one_exit;
13563         }
13564         BNX2X_DEV_INFO("set interrupts successfully\n");
13565
13566         /* register the net device */
13567         rc = register_netdev(dev);
13568         if (rc) {
13569                 dev_err(&pdev->dev, "Cannot register net device\n");
13570                 goto init_one_exit;
13571         }
13572         BNX2X_DEV_INFO("device name after netdev register %s\n", dev->name);
13573
13574         if (!NO_FCOE(bp)) {
13575                 /* Add storage MAC address */
13576                 rtnl_lock();
13577                 dev_addr_add(bp->dev, bp->fip_mac, NETDEV_HW_ADDR_T_SAN);
13578                 rtnl_unlock();
13579         }
13580         if (pcie_get_minimum_link(bp->pdev, &pcie_speed, &pcie_width) ||
13581             pcie_speed == PCI_SPEED_UNKNOWN ||
13582             pcie_width == PCIE_LNK_WIDTH_UNKNOWN)
13583                 BNX2X_DEV_INFO("Failed to determine PCI Express Bandwidth\n");
13584         else
13585                 BNX2X_DEV_INFO(
13586                        "%s (%c%d) PCI-E x%d %s found at mem %lx, IRQ %d, node addr %pM\n",
13587                        board_info[ent->driver_data].name,
13588                        (CHIP_REV(bp) >> 12) + 'A', (CHIP_METAL(bp) >> 4),
13589                        pcie_width,
13590                        pcie_speed == PCIE_SPEED_2_5GT ? "2.5GHz" :
13591                        pcie_speed == PCIE_SPEED_5_0GT ? "5.0GHz" :
13592                        pcie_speed == PCIE_SPEED_8_0GT ? "8.0GHz" :
13593                        "Unknown",
13594                        dev->base_addr, bp->pdev->irq, dev->dev_addr);
13595
13596         bnx2x_register_phc(bp);
13597
13598         if (!IS_MF_SD_STORAGE_PERSONALITY_ONLY(bp))
13599                 bnx2x_set_os_driver_state(bp, OS_DRIVER_STATE_DISABLED);
13600
13601         return 0;
13602
13603 init_one_exit:
13604         bnx2x_disable_pcie_error_reporting(bp);
13605
13606         if (bp->regview)
13607                 iounmap(bp->regview);
13608
13609         if (IS_PF(bp) && bp->doorbells)
13610                 iounmap(bp->doorbells);
13611
13612         free_netdev(dev);
13613
13614         if (atomic_read(&pdev->enable_cnt) == 1)
13615                 pci_release_regions(pdev);
13616
13617         pci_disable_device(pdev);
13618
13619         return rc;
13620 }
13621
13622 static void __bnx2x_remove(struct pci_dev *pdev,
13623                            struct net_device *dev,
13624                            struct bnx2x *bp,
13625                            bool remove_netdev)
13626 {
13627         if (bp->ptp_clock) {
13628                 ptp_clock_unregister(bp->ptp_clock);
13629                 bp->ptp_clock = NULL;
13630         }
13631
13632         /* Delete storage MAC address */
13633         if (!NO_FCOE(bp)) {
13634                 rtnl_lock();
13635                 dev_addr_del(bp->dev, bp->fip_mac, NETDEV_HW_ADDR_T_SAN);
13636                 rtnl_unlock();
13637         }
13638
13639 #ifdef BCM_DCBNL
13640         /* Delete app tlvs from dcbnl */
13641         bnx2x_dcbnl_update_applist(bp, true);
13642 #endif
13643
13644         if (IS_PF(bp) &&
13645             !BP_NOMCP(bp) &&
13646             (bp->flags & BC_SUPPORTS_RMMOD_CMD))
13647                 bnx2x_fw_command(bp, DRV_MSG_CODE_RMMOD, 0);
13648
13649         /* Close the interface - either directly or implicitly */
13650         if (remove_netdev) {
13651                 unregister_netdev(dev);
13652         } else {
13653                 rtnl_lock();
13654                 dev_close(dev);
13655                 rtnl_unlock();
13656         }
13657
13658         bnx2x_iov_remove_one(bp);
13659
13660         /* Power on: we can't let PCI layer write to us while we are in D3 */
13661         if (IS_PF(bp)) {
13662                 bnx2x_set_power_state(bp, PCI_D0);
13663                 bnx2x_set_os_driver_state(bp, OS_DRIVER_STATE_NOT_LOADED);
13664
13665                 /* Set endianity registers to reset values in case next driver
13666                  * boots in different endianty environment.
13667                  */
13668                 bnx2x_reset_endianity(bp);
13669         }
13670
13671         /* Disable MSI/MSI-X */
13672         bnx2x_disable_msi(bp);
13673
13674         /* Power off */
13675         if (IS_PF(bp))
13676                 bnx2x_set_power_state(bp, PCI_D3hot);
13677
13678         /* Make sure RESET task is not scheduled before continuing */
13679         cancel_delayed_work_sync(&bp->sp_rtnl_task);
13680
13681         /* send message via vfpf channel to release the resources of this vf */
13682         if (IS_VF(bp))
13683                 bnx2x_vfpf_release(bp);
13684
13685         /* Assumes no further PCIe PM changes will occur */
13686         if (system_state == SYSTEM_POWER_OFF) {
13687                 pci_wake_from_d3(pdev, bp->wol);
13688                 pci_set_power_state(pdev, PCI_D3hot);
13689         }
13690
13691         bnx2x_disable_pcie_error_reporting(bp);
13692         if (remove_netdev) {
13693                 if (bp->regview)
13694                         iounmap(bp->regview);
13695
13696                 /* For vfs, doorbells are part of the regview and were unmapped
13697                  * along with it. FW is only loaded by PF.
13698                  */
13699                 if (IS_PF(bp)) {
13700                         if (bp->doorbells)
13701                                 iounmap(bp->doorbells);
13702
13703                         bnx2x_release_firmware(bp);
13704                 } else {
13705                         bnx2x_vf_pci_dealloc(bp);
13706                 }
13707                 bnx2x_free_mem_bp(bp);
13708
13709                 free_netdev(dev);
13710
13711                 if (atomic_read(&pdev->enable_cnt) == 1)
13712                         pci_release_regions(pdev);
13713
13714                 pci_disable_device(pdev);
13715         }
13716 }
13717
13718 static void bnx2x_remove_one(struct pci_dev *pdev)
13719 {
13720         struct net_device *dev = pci_get_drvdata(pdev);
13721         struct bnx2x *bp;
13722
13723         if (!dev) {
13724                 dev_err(&pdev->dev, "BAD net device from bnx2x_init_one\n");
13725                 return;
13726         }
13727         bp = netdev_priv(dev);
13728
13729         __bnx2x_remove(pdev, dev, bp, true);
13730 }
13731
13732 static int bnx2x_eeh_nic_unload(struct bnx2x *bp)
13733 {
13734         bp->state = BNX2X_STATE_CLOSING_WAIT4_HALT;
13735
13736         bp->rx_mode = BNX2X_RX_MODE_NONE;
13737
13738         if (CNIC_LOADED(bp))
13739                 bnx2x_cnic_notify(bp, CNIC_CTL_STOP_CMD);
13740
13741         /* Stop Tx */
13742         bnx2x_tx_disable(bp);
13743         /* Delete all NAPI objects */
13744         bnx2x_del_all_napi(bp);
13745         if (CNIC_LOADED(bp))
13746                 bnx2x_del_all_napi_cnic(bp);
13747         netdev_reset_tc(bp->dev);
13748
13749         del_timer_sync(&bp->timer);
13750         cancel_delayed_work_sync(&bp->sp_task);
13751         cancel_delayed_work_sync(&bp->period_task);
13752
13753         if (!down_timeout(&bp->stats_lock, HZ / 10)) {
13754                 bp->stats_state = STATS_STATE_DISABLED;
13755                 up(&bp->stats_lock);
13756         }
13757
13758         bnx2x_save_statistics(bp);
13759
13760         netif_carrier_off(bp->dev);
13761
13762         return 0;
13763 }
13764
13765 /**
13766  * bnx2x_io_error_detected - called when PCI error is detected
13767  * @pdev: Pointer to PCI device
13768  * @state: The current pci connection state
13769  *
13770  * This function is called after a PCI bus error affecting
13771  * this device has been detected.
13772  */
13773 static pci_ers_result_t bnx2x_io_error_detected(struct pci_dev *pdev,
13774                                                 pci_channel_state_t state)
13775 {
13776         struct net_device *dev = pci_get_drvdata(pdev);
13777         struct bnx2x *bp = netdev_priv(dev);
13778
13779         rtnl_lock();
13780
13781         BNX2X_ERR("IO error detected\n");
13782
13783         netif_device_detach(dev);
13784
13785         if (state == pci_channel_io_perm_failure) {
13786                 rtnl_unlock();
13787                 return PCI_ERS_RESULT_DISCONNECT;
13788         }
13789
13790         if (netif_running(dev))
13791                 bnx2x_eeh_nic_unload(bp);
13792
13793         bnx2x_prev_path_mark_eeh(bp);
13794
13795         pci_disable_device(pdev);
13796
13797         rtnl_unlock();
13798
13799         /* Request a slot reset */
13800         return PCI_ERS_RESULT_NEED_RESET;
13801 }
13802
13803 /**
13804  * bnx2x_io_slot_reset - called after the PCI bus has been reset
13805  * @pdev: Pointer to PCI device
13806  *
13807  * Restart the card from scratch, as if from a cold-boot.
13808  */
13809 static pci_ers_result_t bnx2x_io_slot_reset(struct pci_dev *pdev)
13810 {
13811         struct net_device *dev = pci_get_drvdata(pdev);
13812         struct bnx2x *bp = netdev_priv(dev);
13813         int i;
13814
13815         rtnl_lock();
13816         BNX2X_ERR("IO slot reset initializing...\n");
13817         if (pci_enable_device(pdev)) {
13818                 dev_err(&pdev->dev,
13819                         "Cannot re-enable PCI device after reset\n");
13820                 rtnl_unlock();
13821                 return PCI_ERS_RESULT_DISCONNECT;
13822         }
13823
13824         pci_set_master(pdev);
13825         pci_restore_state(pdev);
13826         pci_save_state(pdev);
13827
13828         if (netif_running(dev))
13829                 bnx2x_set_power_state(bp, PCI_D0);
13830
13831         if (netif_running(dev)) {
13832                 BNX2X_ERR("IO slot reset --> driver unload\n");
13833
13834                 /* MCP should have been reset; Need to wait for validity */
13835                 bnx2x_init_shmem(bp);
13836
13837                 if (IS_PF(bp) && SHMEM2_HAS(bp, drv_capabilities_flag)) {
13838                         u32 v;
13839
13840                         v = SHMEM2_RD(bp,
13841                                       drv_capabilities_flag[BP_FW_MB_IDX(bp)]);
13842                         SHMEM2_WR(bp, drv_capabilities_flag[BP_FW_MB_IDX(bp)],
13843                                   v & ~DRV_FLAGS_CAPABILITIES_LOADED_L2);
13844                 }
13845                 bnx2x_drain_tx_queues(bp);
13846                 bnx2x_send_unload_req(bp, UNLOAD_RECOVERY);
13847                 bnx2x_netif_stop(bp, 1);
13848                 bnx2x_free_irq(bp);
13849
13850                 /* Report UNLOAD_DONE to MCP */
13851                 bnx2x_send_unload_done(bp, true);
13852
13853                 bp->sp_state = 0;
13854                 bp->port.pmf = 0;
13855
13856                 bnx2x_prev_unload(bp);
13857
13858                 /* We should have reseted the engine, so It's fair to
13859                  * assume the FW will no longer write to the bnx2x driver.
13860                  */
13861                 bnx2x_squeeze_objects(bp);
13862                 bnx2x_free_skbs(bp);
13863                 for_each_rx_queue(bp, i)
13864                         bnx2x_free_rx_sge_range(bp, bp->fp + i, NUM_RX_SGE);
13865                 bnx2x_free_fp_mem(bp);
13866                 bnx2x_free_mem(bp);
13867
13868                 bp->state = BNX2X_STATE_CLOSED;
13869         }
13870
13871         rtnl_unlock();
13872
13873         /* If AER, perform cleanup of the PCIe registers */
13874         if (bp->flags & AER_ENABLED) {
13875                 if (pci_cleanup_aer_uncorrect_error_status(pdev))
13876                         BNX2X_ERR("pci_cleanup_aer_uncorrect_error_status failed\n");
13877                 else
13878                         DP(NETIF_MSG_HW, "pci_cleanup_aer_uncorrect_error_status succeeded\n");
13879         }
13880
13881         return PCI_ERS_RESULT_RECOVERED;
13882 }
13883
13884 /**
13885  * bnx2x_io_resume - called when traffic can start flowing again
13886  * @pdev: Pointer to PCI device
13887  *
13888  * This callback is called when the error recovery driver tells us that
13889  * its OK to resume normal operation.
13890  */
13891 static void bnx2x_io_resume(struct pci_dev *pdev)
13892 {
13893         struct net_device *dev = pci_get_drvdata(pdev);
13894         struct bnx2x *bp = netdev_priv(dev);
13895
13896         if (bp->recovery_state != BNX2X_RECOVERY_DONE) {
13897                 netdev_err(bp->dev, "Handling parity error recovery. Try again later\n");
13898                 return;
13899         }
13900
13901         rtnl_lock();
13902
13903         bp->fw_seq = SHMEM_RD(bp, func_mb[BP_FW_MB_IDX(bp)].drv_mb_header) &
13904                                                         DRV_MSG_SEQ_NUMBER_MASK;
13905
13906         if (netif_running(dev))
13907                 bnx2x_nic_load(bp, LOAD_NORMAL);
13908
13909         netif_device_attach(dev);
13910
13911         rtnl_unlock();
13912 }
13913
13914 static const struct pci_error_handlers bnx2x_err_handler = {
13915         .error_detected = bnx2x_io_error_detected,
13916         .slot_reset     = bnx2x_io_slot_reset,
13917         .resume         = bnx2x_io_resume,
13918 };
13919
13920 static void bnx2x_shutdown(struct pci_dev *pdev)
13921 {
13922         struct net_device *dev = pci_get_drvdata(pdev);
13923         struct bnx2x *bp;
13924
13925         if (!dev)
13926                 return;
13927
13928         bp = netdev_priv(dev);
13929         if (!bp)
13930                 return;
13931
13932         rtnl_lock();
13933         netif_device_detach(dev);
13934         rtnl_unlock();
13935
13936         /* Don't remove the netdevice, as there are scenarios which will cause
13937          * the kernel to hang, e.g., when trying to remove bnx2i while the
13938          * rootfs is mounted from SAN.
13939          */
13940         __bnx2x_remove(pdev, dev, bp, false);
13941 }
13942
13943 static struct pci_driver bnx2x_pci_driver = {
13944         .name        = DRV_MODULE_NAME,
13945         .id_table    = bnx2x_pci_tbl,
13946         .probe       = bnx2x_init_one,
13947         .remove      = bnx2x_remove_one,
13948         .suspend     = bnx2x_suspend,
13949         .resume      = bnx2x_resume,
13950         .err_handler = &bnx2x_err_handler,
13951 #ifdef CONFIG_BNX2X_SRIOV
13952         .sriov_configure = bnx2x_sriov_configure,
13953 #endif
13954         .shutdown    = bnx2x_shutdown,
13955 };
13956
13957 static int __init bnx2x_init(void)
13958 {
13959         int ret;
13960
13961         pr_info("%s", version);
13962
13963         bnx2x_wq = create_singlethread_workqueue("bnx2x");
13964         if (bnx2x_wq == NULL) {
13965                 pr_err("Cannot create workqueue\n");
13966                 return -ENOMEM;
13967         }
13968         bnx2x_iov_wq = create_singlethread_workqueue("bnx2x_iov");
13969         if (!bnx2x_iov_wq) {
13970                 pr_err("Cannot create iov workqueue\n");
13971                 destroy_workqueue(bnx2x_wq);
13972                 return -ENOMEM;
13973         }
13974
13975         ret = pci_register_driver(&bnx2x_pci_driver);
13976         if (ret) {
13977                 pr_err("Cannot register driver\n");
13978                 destroy_workqueue(bnx2x_wq);
13979                 destroy_workqueue(bnx2x_iov_wq);
13980         }
13981         return ret;
13982 }
13983
13984 static void __exit bnx2x_cleanup(void)
13985 {
13986         struct list_head *pos, *q;
13987
13988         pci_unregister_driver(&bnx2x_pci_driver);
13989
13990         destroy_workqueue(bnx2x_wq);
13991         destroy_workqueue(bnx2x_iov_wq);
13992
13993         /* Free globally allocated resources */
13994         list_for_each_safe(pos, q, &bnx2x_prev_list) {
13995                 struct bnx2x_prev_path_list *tmp =
13996                         list_entry(pos, struct bnx2x_prev_path_list, list);
13997                 list_del(pos);
13998                 kfree(tmp);
13999         }
14000 }
14001
14002 void bnx2x_notify_link_changed(struct bnx2x *bp)
14003 {
14004         REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_12 + BP_FUNC(bp)*sizeof(u32), 1);
14005 }
14006
14007 module_init(bnx2x_init);
14008 module_exit(bnx2x_cleanup);
14009
14010 /**
14011  * bnx2x_set_iscsi_eth_mac_addr - set iSCSI MAC(s).
14012  *
14013  * @bp:         driver handle
14014  * @set:        set or clear the CAM entry
14015  *
14016  * This function will wait until the ramrod completion returns.
14017  * Return 0 if success, -ENODEV if ramrod doesn't return.
14018  */
14019 static int bnx2x_set_iscsi_eth_mac_addr(struct bnx2x *bp)
14020 {
14021         unsigned long ramrod_flags = 0;
14022
14023         __set_bit(RAMROD_COMP_WAIT, &ramrod_flags);
14024         return bnx2x_set_mac_one(bp, bp->cnic_eth_dev.iscsi_mac,
14025                                  &bp->iscsi_l2_mac_obj, true,
14026                                  BNX2X_ISCSI_ETH_MAC, &ramrod_flags);
14027 }
14028
14029 /* count denotes the number of new completions we have seen */
14030 static void bnx2x_cnic_sp_post(struct bnx2x *bp, int count)
14031 {
14032         struct eth_spe *spe;
14033         int cxt_index, cxt_offset;
14034
14035 #ifdef BNX2X_STOP_ON_ERROR
14036         if (unlikely(bp->panic))
14037                 return;
14038 #endif
14039
14040         spin_lock_bh(&bp->spq_lock);
14041         BUG_ON(bp->cnic_spq_pending < count);
14042         bp->cnic_spq_pending -= count;
14043
14044         for (; bp->cnic_kwq_pending; bp->cnic_kwq_pending--) {
14045                 u16 type =  (le16_to_cpu(bp->cnic_kwq_cons->hdr.type)
14046                                 & SPE_HDR_CONN_TYPE) >>
14047                                 SPE_HDR_CONN_TYPE_SHIFT;
14048                 u8 cmd = (le32_to_cpu(bp->cnic_kwq_cons->hdr.conn_and_cmd_data)
14049                                 >> SPE_HDR_CMD_ID_SHIFT) & 0xff;
14050
14051                 /* Set validation for iSCSI L2 client before sending SETUP
14052                  *  ramrod
14053                  */
14054                 if (type == ETH_CONNECTION_TYPE) {
14055                         if (cmd == RAMROD_CMD_ID_ETH_CLIENT_SETUP) {
14056                                 cxt_index = BNX2X_ISCSI_ETH_CID(bp) /
14057                                         ILT_PAGE_CIDS;
14058                                 cxt_offset = BNX2X_ISCSI_ETH_CID(bp) -
14059                                         (cxt_index * ILT_PAGE_CIDS);
14060                                 bnx2x_set_ctx_validation(bp,
14061                                         &bp->context[cxt_index].
14062                                                          vcxt[cxt_offset].eth,
14063                                         BNX2X_ISCSI_ETH_CID(bp));
14064                         }
14065                 }
14066
14067                 /*
14068                  * There may be not more than 8 L2, not more than 8 L5 SPEs
14069                  * and in the air. We also check that number of outstanding
14070                  * COMMON ramrods is not more than the EQ and SPQ can
14071                  * accommodate.
14072                  */
14073                 if (type == ETH_CONNECTION_TYPE) {
14074                         if (!atomic_read(&bp->cq_spq_left))
14075                                 break;
14076                         else
14077                                 atomic_dec(&bp->cq_spq_left);
14078                 } else if (type == NONE_CONNECTION_TYPE) {
14079                         if (!atomic_read(&bp->eq_spq_left))
14080                                 break;
14081                         else
14082                                 atomic_dec(&bp->eq_spq_left);
14083                 } else if ((type == ISCSI_CONNECTION_TYPE) ||
14084                            (type == FCOE_CONNECTION_TYPE)) {
14085                         if (bp->cnic_spq_pending >=
14086                             bp->cnic_eth_dev.max_kwqe_pending)
14087                                 break;
14088                         else
14089                                 bp->cnic_spq_pending++;
14090                 } else {
14091                         BNX2X_ERR("Unknown SPE type: %d\n", type);
14092                         bnx2x_panic();
14093                         break;
14094                 }
14095
14096                 spe = bnx2x_sp_get_next(bp);
14097                 *spe = *bp->cnic_kwq_cons;
14098
14099                 DP(BNX2X_MSG_SP, "pending on SPQ %d, on KWQ %d count %d\n",
14100                    bp->cnic_spq_pending, bp->cnic_kwq_pending, count);
14101
14102                 if (bp->cnic_kwq_cons == bp->cnic_kwq_last)
14103                         bp->cnic_kwq_cons = bp->cnic_kwq;
14104                 else
14105                         bp->cnic_kwq_cons++;
14106         }
14107         bnx2x_sp_prod_update(bp);
14108         spin_unlock_bh(&bp->spq_lock);
14109 }
14110
14111 static int bnx2x_cnic_sp_queue(struct net_device *dev,
14112                                struct kwqe_16 *kwqes[], u32 count)
14113 {
14114         struct bnx2x *bp = netdev_priv(dev);
14115         int i;
14116
14117 #ifdef BNX2X_STOP_ON_ERROR
14118         if (unlikely(bp->panic)) {
14119                 BNX2X_ERR("Can't post to SP queue while panic\n");
14120                 return -EIO;
14121         }
14122 #endif
14123
14124         if ((bp->recovery_state != BNX2X_RECOVERY_DONE) &&
14125             (bp->recovery_state != BNX2X_RECOVERY_NIC_LOADING)) {
14126                 BNX2X_ERR("Handling parity error recovery. Try again later\n");
14127                 return -EAGAIN;
14128         }
14129
14130         spin_lock_bh(&bp->spq_lock);
14131
14132         for (i = 0; i < count; i++) {
14133                 struct eth_spe *spe = (struct eth_spe *)kwqes[i];
14134
14135                 if (bp->cnic_kwq_pending == MAX_SP_DESC_CNT)
14136                         break;
14137
14138                 *bp->cnic_kwq_prod = *spe;
14139
14140                 bp->cnic_kwq_pending++;
14141
14142                 DP(BNX2X_MSG_SP, "L5 SPQE %x %x %x:%x pos %d\n",
14143                    spe->hdr.conn_and_cmd_data, spe->hdr.type,
14144                    spe->data.update_data_addr.hi,
14145                    spe->data.update_data_addr.lo,
14146                    bp->cnic_kwq_pending);
14147
14148                 if (bp->cnic_kwq_prod == bp->cnic_kwq_last)
14149                         bp->cnic_kwq_prod = bp->cnic_kwq;
14150                 else
14151                         bp->cnic_kwq_prod++;
14152         }
14153
14154         spin_unlock_bh(&bp->spq_lock);
14155
14156         if (bp->cnic_spq_pending < bp->cnic_eth_dev.max_kwqe_pending)
14157                 bnx2x_cnic_sp_post(bp, 0);
14158
14159         return i;
14160 }
14161
14162 static int bnx2x_cnic_ctl_send(struct bnx2x *bp, struct cnic_ctl_info *ctl)
14163 {
14164         struct cnic_ops *c_ops;
14165         int rc = 0;
14166
14167         mutex_lock(&bp->cnic_mutex);
14168         c_ops = rcu_dereference_protected(bp->cnic_ops,
14169                                           lockdep_is_held(&bp->cnic_mutex));
14170         if (c_ops)
14171                 rc = c_ops->cnic_ctl(bp->cnic_data, ctl);
14172         mutex_unlock(&bp->cnic_mutex);
14173
14174         return rc;
14175 }
14176
14177 static int bnx2x_cnic_ctl_send_bh(struct bnx2x *bp, struct cnic_ctl_info *ctl)
14178 {
14179         struct cnic_ops *c_ops;
14180         int rc = 0;
14181
14182         rcu_read_lock();
14183         c_ops = rcu_dereference(bp->cnic_ops);
14184         if (c_ops)
14185                 rc = c_ops->cnic_ctl(bp->cnic_data, ctl);
14186         rcu_read_unlock();
14187
14188         return rc;
14189 }
14190
14191 /*
14192  * for commands that have no data
14193  */
14194 int bnx2x_cnic_notify(struct bnx2x *bp, int cmd)
14195 {
14196         struct cnic_ctl_info ctl = {0};
14197
14198         ctl.cmd = cmd;
14199
14200         return bnx2x_cnic_ctl_send(bp, &ctl);
14201 }
14202
14203 static void bnx2x_cnic_cfc_comp(struct bnx2x *bp, int cid, u8 err)
14204 {
14205         struct cnic_ctl_info ctl = {0};
14206
14207         /* first we tell CNIC and only then we count this as a completion */
14208         ctl.cmd = CNIC_CTL_COMPLETION_CMD;
14209         ctl.data.comp.cid = cid;
14210         ctl.data.comp.error = err;
14211
14212         bnx2x_cnic_ctl_send_bh(bp, &ctl);
14213         bnx2x_cnic_sp_post(bp, 0);
14214 }
14215
14216 /* Called with netif_addr_lock_bh() taken.
14217  * Sets an rx_mode config for an iSCSI ETH client.
14218  * Doesn't block.
14219  * Completion should be checked outside.
14220  */
14221 static void bnx2x_set_iscsi_eth_rx_mode(struct bnx2x *bp, bool start)
14222 {
14223         unsigned long accept_flags = 0, ramrod_flags = 0;
14224         u8 cl_id = bnx2x_cnic_eth_cl_id(bp, BNX2X_ISCSI_ETH_CL_ID_IDX);
14225         int sched_state = BNX2X_FILTER_ISCSI_ETH_STOP_SCHED;
14226
14227         if (start) {
14228                 /* Start accepting on iSCSI L2 ring. Accept all multicasts
14229                  * because it's the only way for UIO Queue to accept
14230                  * multicasts (in non-promiscuous mode only one Queue per
14231                  * function will receive multicast packets (leading in our
14232                  * case).
14233                  */
14234                 __set_bit(BNX2X_ACCEPT_UNICAST, &accept_flags);
14235                 __set_bit(BNX2X_ACCEPT_ALL_MULTICAST, &accept_flags);
14236                 __set_bit(BNX2X_ACCEPT_BROADCAST, &accept_flags);
14237                 __set_bit(BNX2X_ACCEPT_ANY_VLAN, &accept_flags);
14238
14239                 /* Clear STOP_PENDING bit if START is requested */
14240                 clear_bit(BNX2X_FILTER_ISCSI_ETH_STOP_SCHED, &bp->sp_state);
14241
14242                 sched_state = BNX2X_FILTER_ISCSI_ETH_START_SCHED;
14243         } else
14244                 /* Clear START_PENDING bit if STOP is requested */
14245                 clear_bit(BNX2X_FILTER_ISCSI_ETH_START_SCHED, &bp->sp_state);
14246
14247         if (test_bit(BNX2X_FILTER_RX_MODE_PENDING, &bp->sp_state))
14248                 set_bit(sched_state, &bp->sp_state);
14249         else {
14250                 __set_bit(RAMROD_RX, &ramrod_flags);
14251                 bnx2x_set_q_rx_mode(bp, cl_id, 0, accept_flags, 0,
14252                                     ramrod_flags);
14253         }
14254 }
14255
14256 static int bnx2x_drv_ctl(struct net_device *dev, struct drv_ctl_info *ctl)
14257 {
14258         struct bnx2x *bp = netdev_priv(dev);
14259         int rc = 0;
14260
14261         switch (ctl->cmd) {
14262         case DRV_CTL_CTXTBL_WR_CMD: {
14263                 u32 index = ctl->data.io.offset;
14264                 dma_addr_t addr = ctl->data.io.dma_addr;
14265
14266                 bnx2x_ilt_wr(bp, index, addr);
14267                 break;
14268         }
14269
14270         case DRV_CTL_RET_L5_SPQ_CREDIT_CMD: {
14271                 int count = ctl->data.credit.credit_count;
14272
14273                 bnx2x_cnic_sp_post(bp, count);
14274                 break;
14275         }
14276
14277         /* rtnl_lock is held.  */
14278         case DRV_CTL_START_L2_CMD: {
14279                 struct cnic_eth_dev *cp = &bp->cnic_eth_dev;
14280                 unsigned long sp_bits = 0;
14281
14282                 /* Configure the iSCSI classification object */
14283                 bnx2x_init_mac_obj(bp, &bp->iscsi_l2_mac_obj,
14284                                    cp->iscsi_l2_client_id,
14285                                    cp->iscsi_l2_cid, BP_FUNC(bp),
14286                                    bnx2x_sp(bp, mac_rdata),
14287                                    bnx2x_sp_mapping(bp, mac_rdata),
14288                                    BNX2X_FILTER_MAC_PENDING,
14289                                    &bp->sp_state, BNX2X_OBJ_TYPE_RX,
14290                                    &bp->macs_pool);
14291
14292                 /* Set iSCSI MAC address */
14293                 rc = bnx2x_set_iscsi_eth_mac_addr(bp);
14294                 if (rc)
14295                         break;
14296
14297                 mmiowb();
14298                 barrier();
14299
14300                 /* Start accepting on iSCSI L2 ring */
14301
14302                 netif_addr_lock_bh(dev);
14303                 bnx2x_set_iscsi_eth_rx_mode(bp, true);
14304                 netif_addr_unlock_bh(dev);
14305
14306                 /* bits to wait on */
14307                 __set_bit(BNX2X_FILTER_RX_MODE_PENDING, &sp_bits);
14308                 __set_bit(BNX2X_FILTER_ISCSI_ETH_START_SCHED, &sp_bits);
14309
14310                 if (!bnx2x_wait_sp_comp(bp, sp_bits))
14311                         BNX2X_ERR("rx_mode completion timed out!\n");
14312
14313                 break;
14314         }
14315
14316         /* rtnl_lock is held.  */
14317         case DRV_CTL_STOP_L2_CMD: {
14318                 unsigned long sp_bits = 0;
14319
14320                 /* Stop accepting on iSCSI L2 ring */
14321                 netif_addr_lock_bh(dev);
14322                 bnx2x_set_iscsi_eth_rx_mode(bp, false);
14323                 netif_addr_unlock_bh(dev);
14324
14325                 /* bits to wait on */
14326                 __set_bit(BNX2X_FILTER_RX_MODE_PENDING, &sp_bits);
14327                 __set_bit(BNX2X_FILTER_ISCSI_ETH_STOP_SCHED, &sp_bits);
14328
14329                 if (!bnx2x_wait_sp_comp(bp, sp_bits))
14330                         BNX2X_ERR("rx_mode completion timed out!\n");
14331
14332                 mmiowb();
14333                 barrier();
14334
14335                 /* Unset iSCSI L2 MAC */
14336                 rc = bnx2x_del_all_macs(bp, &bp->iscsi_l2_mac_obj,
14337                                         BNX2X_ISCSI_ETH_MAC, true);
14338                 break;
14339         }
14340         case DRV_CTL_RET_L2_SPQ_CREDIT_CMD: {
14341                 int count = ctl->data.credit.credit_count;
14342
14343                 smp_mb__before_atomic();
14344                 atomic_add(count, &bp->cq_spq_left);
14345                 smp_mb__after_atomic();
14346                 break;
14347         }
14348         case DRV_CTL_ULP_REGISTER_CMD: {
14349                 int ulp_type = ctl->data.register_data.ulp_type;
14350
14351                 if (CHIP_IS_E3(bp)) {
14352                         int idx = BP_FW_MB_IDX(bp);
14353                         u32 cap = SHMEM2_RD(bp, drv_capabilities_flag[idx]);
14354                         int path = BP_PATH(bp);
14355                         int port = BP_PORT(bp);
14356                         int i;
14357                         u32 scratch_offset;
14358                         u32 *host_addr;
14359
14360                         /* first write capability to shmem2 */
14361                         if (ulp_type == CNIC_ULP_ISCSI)
14362                                 cap |= DRV_FLAGS_CAPABILITIES_LOADED_ISCSI;
14363                         else if (ulp_type == CNIC_ULP_FCOE)
14364                                 cap |= DRV_FLAGS_CAPABILITIES_LOADED_FCOE;
14365                         SHMEM2_WR(bp, drv_capabilities_flag[idx], cap);
14366
14367                         if ((ulp_type != CNIC_ULP_FCOE) ||
14368                             (!SHMEM2_HAS(bp, ncsi_oem_data_addr)) ||
14369                             (!(bp->flags &  BC_SUPPORTS_FCOE_FEATURES)))
14370                                 break;
14371
14372                         /* if reached here - should write fcoe capabilities */
14373                         scratch_offset = SHMEM2_RD(bp, ncsi_oem_data_addr);
14374                         if (!scratch_offset)
14375                                 break;
14376                         scratch_offset += offsetof(struct glob_ncsi_oem_data,
14377                                                    fcoe_features[path][port]);
14378                         host_addr = (u32 *) &(ctl->data.register_data.
14379                                               fcoe_features);
14380                         for (i = 0; i < sizeof(struct fcoe_capabilities);
14381                              i += 4)
14382                                 REG_WR(bp, scratch_offset + i,
14383                                        *(host_addr + i/4));
14384                 }
14385                 bnx2x_schedule_sp_rtnl(bp, BNX2X_SP_RTNL_GET_DRV_VERSION, 0);
14386                 break;
14387         }
14388
14389         case DRV_CTL_ULP_UNREGISTER_CMD: {
14390                 int ulp_type = ctl->data.ulp_type;
14391
14392                 if (CHIP_IS_E3(bp)) {
14393                         int idx = BP_FW_MB_IDX(bp);
14394                         u32 cap;
14395
14396                         cap = SHMEM2_RD(bp, drv_capabilities_flag[idx]);
14397                         if (ulp_type == CNIC_ULP_ISCSI)
14398                                 cap &= ~DRV_FLAGS_CAPABILITIES_LOADED_ISCSI;
14399                         else if (ulp_type == CNIC_ULP_FCOE)
14400                                 cap &= ~DRV_FLAGS_CAPABILITIES_LOADED_FCOE;
14401                         SHMEM2_WR(bp, drv_capabilities_flag[idx], cap);
14402                 }
14403                 bnx2x_schedule_sp_rtnl(bp, BNX2X_SP_RTNL_GET_DRV_VERSION, 0);
14404                 break;
14405         }
14406
14407         default:
14408                 BNX2X_ERR("unknown command %x\n", ctl->cmd);
14409                 rc = -EINVAL;
14410         }
14411
14412         return rc;
14413 }
14414
14415 void bnx2x_setup_cnic_irq_info(struct bnx2x *bp)
14416 {
14417         struct cnic_eth_dev *cp = &bp->cnic_eth_dev;
14418
14419         if (bp->flags & USING_MSIX_FLAG) {
14420                 cp->drv_state |= CNIC_DRV_STATE_USING_MSIX;
14421                 cp->irq_arr[0].irq_flags |= CNIC_IRQ_FL_MSIX;
14422                 cp->irq_arr[0].vector = bp->msix_table[1].vector;
14423         } else {
14424                 cp->drv_state &= ~CNIC_DRV_STATE_USING_MSIX;
14425                 cp->irq_arr[0].irq_flags &= ~CNIC_IRQ_FL_MSIX;
14426         }
14427         if (!CHIP_IS_E1x(bp))
14428                 cp->irq_arr[0].status_blk = (void *)bp->cnic_sb.e2_sb;
14429         else
14430                 cp->irq_arr[0].status_blk = (void *)bp->cnic_sb.e1x_sb;
14431
14432         cp->irq_arr[0].status_blk_num =  bnx2x_cnic_fw_sb_id(bp);
14433         cp->irq_arr[0].status_blk_num2 = bnx2x_cnic_igu_sb_id(bp);
14434         cp->irq_arr[1].status_blk = bp->def_status_blk;
14435         cp->irq_arr[1].status_blk_num = DEF_SB_ID;
14436         cp->irq_arr[1].status_blk_num2 = DEF_SB_IGU_ID;
14437
14438         cp->num_irq = 2;
14439 }
14440
14441 void bnx2x_setup_cnic_info(struct bnx2x *bp)
14442 {
14443         struct cnic_eth_dev *cp = &bp->cnic_eth_dev;
14444
14445         cp->ctx_tbl_offset = FUNC_ILT_BASE(BP_FUNC(bp)) +
14446                              bnx2x_cid_ilt_lines(bp);
14447         cp->starting_cid = bnx2x_cid_ilt_lines(bp) * ILT_PAGE_CIDS;
14448         cp->fcoe_init_cid = BNX2X_FCOE_ETH_CID(bp);
14449         cp->iscsi_l2_cid = BNX2X_ISCSI_ETH_CID(bp);
14450
14451         DP(NETIF_MSG_IFUP, "BNX2X_1st_NON_L2_ETH_CID(bp) %x, cp->starting_cid %x, cp->fcoe_init_cid %x, cp->iscsi_l2_cid %x\n",
14452            BNX2X_1st_NON_L2_ETH_CID(bp), cp->starting_cid, cp->fcoe_init_cid,
14453            cp->iscsi_l2_cid);
14454
14455         if (NO_ISCSI_OOO(bp))
14456                 cp->drv_state |= CNIC_DRV_STATE_NO_ISCSI_OOO;
14457 }
14458
14459 static int bnx2x_register_cnic(struct net_device *dev, struct cnic_ops *ops,
14460                                void *data)
14461 {
14462         struct bnx2x *bp = netdev_priv(dev);
14463         struct cnic_eth_dev *cp = &bp->cnic_eth_dev;
14464         int rc;
14465
14466         DP(NETIF_MSG_IFUP, "Register_cnic called\n");
14467
14468         if (ops == NULL) {
14469                 BNX2X_ERR("NULL ops received\n");
14470                 return -EINVAL;
14471         }
14472
14473         if (!CNIC_SUPPORT(bp)) {
14474                 BNX2X_ERR("Can't register CNIC when not supported\n");
14475                 return -EOPNOTSUPP;
14476         }
14477
14478         if (!CNIC_LOADED(bp)) {
14479                 rc = bnx2x_load_cnic(bp);
14480                 if (rc) {
14481                         BNX2X_ERR("CNIC-related load failed\n");
14482                         return rc;
14483                 }
14484         }
14485
14486         bp->cnic_enabled = true;
14487
14488         bp->cnic_kwq = kzalloc(PAGE_SIZE, GFP_KERNEL);
14489         if (!bp->cnic_kwq)
14490                 return -ENOMEM;
14491
14492         bp->cnic_kwq_cons = bp->cnic_kwq;
14493         bp->cnic_kwq_prod = bp->cnic_kwq;
14494         bp->cnic_kwq_last = bp->cnic_kwq + MAX_SP_DESC_CNT;
14495
14496         bp->cnic_spq_pending = 0;
14497         bp->cnic_kwq_pending = 0;
14498
14499         bp->cnic_data = data;
14500
14501         cp->num_irq = 0;
14502         cp->drv_state |= CNIC_DRV_STATE_REGD;
14503         cp->iro_arr = bp->iro_arr;
14504
14505         bnx2x_setup_cnic_irq_info(bp);
14506
14507         rcu_assign_pointer(bp->cnic_ops, ops);
14508
14509         /* Schedule driver to read CNIC driver versions */
14510         bnx2x_schedule_sp_rtnl(bp, BNX2X_SP_RTNL_GET_DRV_VERSION, 0);
14511
14512         return 0;
14513 }
14514
14515 static int bnx2x_unregister_cnic(struct net_device *dev)
14516 {
14517         struct bnx2x *bp = netdev_priv(dev);
14518         struct cnic_eth_dev *cp = &bp->cnic_eth_dev;
14519
14520         mutex_lock(&bp->cnic_mutex);
14521         cp->drv_state = 0;
14522         RCU_INIT_POINTER(bp->cnic_ops, NULL);
14523         mutex_unlock(&bp->cnic_mutex);
14524         synchronize_rcu();
14525         bp->cnic_enabled = false;
14526         kfree(bp->cnic_kwq);
14527         bp->cnic_kwq = NULL;
14528
14529         return 0;
14530 }
14531
14532 static struct cnic_eth_dev *bnx2x_cnic_probe(struct net_device *dev)
14533 {
14534         struct bnx2x *bp = netdev_priv(dev);
14535         struct cnic_eth_dev *cp = &bp->cnic_eth_dev;
14536
14537         /* If both iSCSI and FCoE are disabled - return NULL in
14538          * order to indicate CNIC that it should not try to work
14539          * with this device.
14540          */
14541         if (NO_ISCSI(bp) && NO_FCOE(bp))
14542                 return NULL;
14543
14544         cp->drv_owner = THIS_MODULE;
14545         cp->chip_id = CHIP_ID(bp);
14546         cp->pdev = bp->pdev;
14547         cp->io_base = bp->regview;
14548         cp->io_base2 = bp->doorbells;
14549         cp->max_kwqe_pending = 8;
14550         cp->ctx_blk_size = CDU_ILT_PAGE_SZ;
14551         cp->ctx_tbl_offset = FUNC_ILT_BASE(BP_FUNC(bp)) +
14552                              bnx2x_cid_ilt_lines(bp);
14553         cp->ctx_tbl_len = CNIC_ILT_LINES;
14554         cp->starting_cid = bnx2x_cid_ilt_lines(bp) * ILT_PAGE_CIDS;
14555         cp->drv_submit_kwqes_16 = bnx2x_cnic_sp_queue;
14556         cp->drv_ctl = bnx2x_drv_ctl;
14557         cp->drv_register_cnic = bnx2x_register_cnic;
14558         cp->drv_unregister_cnic = bnx2x_unregister_cnic;
14559         cp->fcoe_init_cid = BNX2X_FCOE_ETH_CID(bp);
14560         cp->iscsi_l2_client_id =
14561                 bnx2x_cnic_eth_cl_id(bp, BNX2X_ISCSI_ETH_CL_ID_IDX);
14562         cp->iscsi_l2_cid = BNX2X_ISCSI_ETH_CID(bp);
14563
14564         if (NO_ISCSI_OOO(bp))
14565                 cp->drv_state |= CNIC_DRV_STATE_NO_ISCSI_OOO;
14566
14567         if (NO_ISCSI(bp))
14568                 cp->drv_state |= CNIC_DRV_STATE_NO_ISCSI;
14569
14570         if (NO_FCOE(bp))
14571                 cp->drv_state |= CNIC_DRV_STATE_NO_FCOE;
14572
14573         BNX2X_DEV_INFO(
14574                 "page_size %d, tbl_offset %d, tbl_lines %d, starting cid %d\n",
14575            cp->ctx_blk_size,
14576            cp->ctx_tbl_offset,
14577            cp->ctx_tbl_len,
14578            cp->starting_cid);
14579         return cp;
14580 }
14581
14582 static u32 bnx2x_rx_ustorm_prods_offset(struct bnx2x_fastpath *fp)
14583 {
14584         struct bnx2x *bp = fp->bp;
14585         u32 offset = BAR_USTRORM_INTMEM;
14586
14587         if (IS_VF(bp))
14588                 return bnx2x_vf_ustorm_prods_offset(bp, fp);
14589         else if (!CHIP_IS_E1x(bp))
14590                 offset += USTORM_RX_PRODS_E2_OFFSET(fp->cl_qzone_id);
14591         else
14592                 offset += USTORM_RX_PRODS_E1X_OFFSET(BP_PORT(bp), fp->cl_id);
14593
14594         return offset;
14595 }
14596
14597 /* called only on E1H or E2.
14598  * When pretending to be PF, the pretend value is the function number 0...7
14599  * When pretending to be VF, the pretend val is the PF-num:VF-valid:ABS-VFID
14600  * combination
14601  */
14602 int bnx2x_pretend_func(struct bnx2x *bp, u16 pretend_func_val)
14603 {
14604         u32 pretend_reg;
14605
14606         if (CHIP_IS_E1H(bp) && pretend_func_val >= E1H_FUNC_MAX)
14607                 return -1;
14608
14609         /* get my own pretend register */
14610         pretend_reg = bnx2x_get_pretend_reg(bp);
14611         REG_WR(bp, pretend_reg, pretend_func_val);
14612         REG_RD(bp, pretend_reg);
14613         return 0;
14614 }
14615
14616 static void bnx2x_ptp_task(struct work_struct *work)
14617 {
14618         struct bnx2x *bp = container_of(work, struct bnx2x, ptp_task);
14619         int port = BP_PORT(bp);
14620         u32 val_seq;
14621         u64 timestamp, ns;
14622         struct skb_shared_hwtstamps shhwtstamps;
14623
14624         /* Read Tx timestamp registers */
14625         val_seq = REG_RD(bp, port ? NIG_REG_P1_TLLH_PTP_BUF_SEQID :
14626                          NIG_REG_P0_TLLH_PTP_BUF_SEQID);
14627         if (val_seq & 0x10000) {
14628                 /* There is a valid timestamp value */
14629                 timestamp = REG_RD(bp, port ? NIG_REG_P1_TLLH_PTP_BUF_TS_MSB :
14630                                    NIG_REG_P0_TLLH_PTP_BUF_TS_MSB);
14631                 timestamp <<= 32;
14632                 timestamp |= REG_RD(bp, port ? NIG_REG_P1_TLLH_PTP_BUF_TS_LSB :
14633                                     NIG_REG_P0_TLLH_PTP_BUF_TS_LSB);
14634                 /* Reset timestamp register to allow new timestamp */
14635                 REG_WR(bp, port ? NIG_REG_P1_TLLH_PTP_BUF_SEQID :
14636                        NIG_REG_P0_TLLH_PTP_BUF_SEQID, 0x10000);
14637                 ns = timecounter_cyc2time(&bp->timecounter, timestamp);
14638
14639                 memset(&shhwtstamps, 0, sizeof(shhwtstamps));
14640                 shhwtstamps.hwtstamp = ns_to_ktime(ns);
14641                 skb_tstamp_tx(bp->ptp_tx_skb, &shhwtstamps);
14642                 dev_kfree_skb_any(bp->ptp_tx_skb);
14643                 bp->ptp_tx_skb = NULL;
14644
14645                 DP(BNX2X_MSG_PTP, "Tx timestamp, timestamp cycles = %llu, ns = %llu\n",
14646                    timestamp, ns);
14647         } else {
14648                 DP(BNX2X_MSG_PTP, "There is no valid Tx timestamp yet\n");
14649                 /* Reschedule to keep checking for a valid timestamp value */
14650                 schedule_work(&bp->ptp_task);
14651         }
14652 }
14653
14654 void bnx2x_set_rx_ts(struct bnx2x *bp, struct sk_buff *skb)
14655 {
14656         int port = BP_PORT(bp);
14657         u64 timestamp, ns;
14658
14659         timestamp = REG_RD(bp, port ? NIG_REG_P1_LLH_PTP_HOST_BUF_TS_MSB :
14660                             NIG_REG_P0_LLH_PTP_HOST_BUF_TS_MSB);
14661         timestamp <<= 32;
14662         timestamp |= REG_RD(bp, port ? NIG_REG_P1_LLH_PTP_HOST_BUF_TS_LSB :
14663                             NIG_REG_P0_LLH_PTP_HOST_BUF_TS_LSB);
14664
14665         /* Reset timestamp register to allow new timestamp */
14666         REG_WR(bp, port ? NIG_REG_P1_LLH_PTP_HOST_BUF_SEQID :
14667                NIG_REG_P0_LLH_PTP_HOST_BUF_SEQID, 0x10000);
14668
14669         ns = timecounter_cyc2time(&bp->timecounter, timestamp);
14670
14671         skb_hwtstamps(skb)->hwtstamp = ns_to_ktime(ns);
14672
14673         DP(BNX2X_MSG_PTP, "Rx timestamp, timestamp cycles = %llu, ns = %llu\n",
14674            timestamp, ns);
14675 }
14676
14677 /* Read the PHC */
14678 static cycle_t bnx2x_cyclecounter_read(const struct cyclecounter *cc)
14679 {
14680         struct bnx2x *bp = container_of(cc, struct bnx2x, cyclecounter);
14681         int port = BP_PORT(bp);
14682         u32 wb_data[2];
14683         u64 phc_cycles;
14684
14685         REG_RD_DMAE(bp, port ? NIG_REG_TIMESYNC_GEN_REG + tsgen_synctime_t1 :
14686                     NIG_REG_TIMESYNC_GEN_REG + tsgen_synctime_t0, wb_data, 2);
14687         phc_cycles = wb_data[1];
14688         phc_cycles = (phc_cycles << 32) + wb_data[0];
14689
14690         DP(BNX2X_MSG_PTP, "PHC read cycles = %llu\n", phc_cycles);
14691
14692         return phc_cycles;
14693 }
14694
14695 static void bnx2x_init_cyclecounter(struct bnx2x *bp)
14696 {
14697         memset(&bp->cyclecounter, 0, sizeof(bp->cyclecounter));
14698         bp->cyclecounter.read = bnx2x_cyclecounter_read;
14699         bp->cyclecounter.mask = CYCLECOUNTER_MASK(64);
14700         bp->cyclecounter.shift = 1;
14701         bp->cyclecounter.mult = 1;
14702 }
14703
14704 static int bnx2x_send_reset_timesync_ramrod(struct bnx2x *bp)
14705 {
14706         struct bnx2x_func_state_params func_params = {NULL};
14707         struct bnx2x_func_set_timesync_params *set_timesync_params =
14708                 &func_params.params.set_timesync;
14709
14710         /* Prepare parameters for function state transitions */
14711         __set_bit(RAMROD_COMP_WAIT, &func_params.ramrod_flags);
14712         __set_bit(RAMROD_RETRY, &func_params.ramrod_flags);
14713
14714         func_params.f_obj = &bp->func_obj;
14715         func_params.cmd = BNX2X_F_CMD_SET_TIMESYNC;
14716
14717         /* Function parameters */
14718         set_timesync_params->drift_adjust_cmd = TS_DRIFT_ADJUST_RESET;
14719         set_timesync_params->offset_cmd = TS_OFFSET_KEEP;
14720
14721         return bnx2x_func_state_change(bp, &func_params);
14722 }
14723
14724 static int bnx2x_enable_ptp_packets(struct bnx2x *bp)
14725 {
14726         struct bnx2x_queue_state_params q_params;
14727         int rc, i;
14728
14729         /* send queue update ramrod to enable PTP packets */
14730         memset(&q_params, 0, sizeof(q_params));
14731         __set_bit(RAMROD_COMP_WAIT, &q_params.ramrod_flags);
14732         q_params.cmd = BNX2X_Q_CMD_UPDATE;
14733         __set_bit(BNX2X_Q_UPDATE_PTP_PKTS_CHNG,
14734                   &q_params.params.update.update_flags);
14735         __set_bit(BNX2X_Q_UPDATE_PTP_PKTS,
14736                   &q_params.params.update.update_flags);
14737
14738         /* send the ramrod on all the queues of the PF */
14739         for_each_eth_queue(bp, i) {
14740                 struct bnx2x_fastpath *fp = &bp->fp[i];
14741
14742                 /* Set the appropriate Queue object */
14743                 q_params.q_obj = &bnx2x_sp_obj(bp, fp).q_obj;
14744
14745                 /* Update the Queue state */
14746                 rc = bnx2x_queue_state_change(bp, &q_params);
14747                 if (rc) {
14748                         BNX2X_ERR("Failed to enable PTP packets\n");
14749                         return rc;
14750                 }
14751         }
14752
14753         return 0;
14754 }
14755
14756 int bnx2x_configure_ptp_filters(struct bnx2x *bp)
14757 {
14758         int port = BP_PORT(bp);
14759         int rc;
14760
14761         if (!bp->hwtstamp_ioctl_called)
14762                 return 0;
14763
14764         switch (bp->tx_type) {
14765         case HWTSTAMP_TX_ON:
14766                 bp->flags |= TX_TIMESTAMPING_EN;
14767                 REG_WR(bp, port ? NIG_REG_P1_TLLH_PTP_PARAM_MASK :
14768                        NIG_REG_P0_TLLH_PTP_PARAM_MASK, 0x6AA);
14769                 REG_WR(bp, port ? NIG_REG_P1_TLLH_PTP_RULE_MASK :
14770                        NIG_REG_P0_TLLH_PTP_RULE_MASK, 0x3EEE);
14771                 break;
14772         case HWTSTAMP_TX_ONESTEP_SYNC:
14773                 BNX2X_ERR("One-step timestamping is not supported\n");
14774                 return -ERANGE;
14775         }
14776
14777         switch (bp->rx_filter) {
14778         case HWTSTAMP_FILTER_NONE:
14779                 break;
14780         case HWTSTAMP_FILTER_ALL:
14781         case HWTSTAMP_FILTER_SOME:
14782                 bp->rx_filter = HWTSTAMP_FILTER_NONE;
14783                 break;
14784         case HWTSTAMP_FILTER_PTP_V1_L4_EVENT:
14785         case HWTSTAMP_FILTER_PTP_V1_L4_SYNC:
14786         case HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ:
14787                 bp->rx_filter = HWTSTAMP_FILTER_PTP_V1_L4_EVENT;
14788                 /* Initialize PTP detection for UDP/IPv4 events */
14789                 REG_WR(bp, port ? NIG_REG_P1_LLH_PTP_PARAM_MASK :
14790                        NIG_REG_P0_LLH_PTP_PARAM_MASK, 0x7EE);
14791                 REG_WR(bp, port ? NIG_REG_P1_LLH_PTP_RULE_MASK :
14792                        NIG_REG_P0_LLH_PTP_RULE_MASK, 0x3FFE);
14793                 break;
14794         case HWTSTAMP_FILTER_PTP_V2_L4_EVENT:
14795         case HWTSTAMP_FILTER_PTP_V2_L4_SYNC:
14796         case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ:
14797                 bp->rx_filter = HWTSTAMP_FILTER_PTP_V2_L4_EVENT;
14798                 /* Initialize PTP detection for UDP/IPv4 or UDP/IPv6 events */
14799                 REG_WR(bp, port ? NIG_REG_P1_LLH_PTP_PARAM_MASK :
14800                        NIG_REG_P0_LLH_PTP_PARAM_MASK, 0x7EA);
14801                 REG_WR(bp, port ? NIG_REG_P1_LLH_PTP_RULE_MASK :
14802                        NIG_REG_P0_LLH_PTP_RULE_MASK, 0x3FEE);
14803                 break;
14804         case HWTSTAMP_FILTER_PTP_V2_L2_EVENT:
14805         case HWTSTAMP_FILTER_PTP_V2_L2_SYNC:
14806         case HWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ:
14807                 bp->rx_filter = HWTSTAMP_FILTER_PTP_V2_L2_EVENT;
14808                 /* Initialize PTP detection L2 events */
14809                 REG_WR(bp, port ? NIG_REG_P1_LLH_PTP_PARAM_MASK :
14810                        NIG_REG_P0_LLH_PTP_PARAM_MASK, 0x6BF);
14811                 REG_WR(bp, port ? NIG_REG_P1_LLH_PTP_RULE_MASK :
14812                        NIG_REG_P0_LLH_PTP_RULE_MASK, 0x3EFF);
14813
14814                 break;
14815         case HWTSTAMP_FILTER_PTP_V2_EVENT:
14816         case HWTSTAMP_FILTER_PTP_V2_SYNC:
14817         case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ:
14818                 bp->rx_filter = HWTSTAMP_FILTER_PTP_V2_EVENT;
14819                 /* Initialize PTP detection L2, UDP/IPv4 or UDP/IPv6 events */
14820                 REG_WR(bp, port ? NIG_REG_P1_LLH_PTP_PARAM_MASK :
14821                        NIG_REG_P0_LLH_PTP_PARAM_MASK, 0x6AA);
14822                 REG_WR(bp, port ? NIG_REG_P1_LLH_PTP_RULE_MASK :
14823                        NIG_REG_P0_LLH_PTP_RULE_MASK, 0x3EEE);
14824                 break;
14825         }
14826
14827         /* Indicate to FW that this PF expects recorded PTP packets */
14828         rc = bnx2x_enable_ptp_packets(bp);
14829         if (rc)
14830                 return rc;
14831
14832         /* Enable sending PTP packets to host */
14833         REG_WR(bp, port ? NIG_REG_P1_LLH_PTP_TO_HOST :
14834                NIG_REG_P0_LLH_PTP_TO_HOST, 0x1);
14835
14836         return 0;
14837 }
14838
14839 static int bnx2x_hwtstamp_ioctl(struct bnx2x *bp, struct ifreq *ifr)
14840 {
14841         struct hwtstamp_config config;
14842         int rc;
14843
14844         DP(BNX2X_MSG_PTP, "HWTSTAMP IOCTL called\n");
14845
14846         if (copy_from_user(&config, ifr->ifr_data, sizeof(config)))
14847                 return -EFAULT;
14848
14849         DP(BNX2X_MSG_PTP, "Requested tx_type: %d, requested rx_filters = %d\n",
14850            config.tx_type, config.rx_filter);
14851
14852         if (config.flags) {
14853                 BNX2X_ERR("config.flags is reserved for future use\n");
14854                 return -EINVAL;
14855         }
14856
14857         bp->hwtstamp_ioctl_called = 1;
14858         bp->tx_type = config.tx_type;
14859         bp->rx_filter = config.rx_filter;
14860
14861         rc = bnx2x_configure_ptp_filters(bp);
14862         if (rc)
14863                 return rc;
14864
14865         config.rx_filter = bp->rx_filter;
14866
14867         return copy_to_user(ifr->ifr_data, &config, sizeof(config)) ?
14868                 -EFAULT : 0;
14869 }
14870
14871 /* Configures HW for PTP */
14872 static int bnx2x_configure_ptp(struct bnx2x *bp)
14873 {
14874         int rc, port = BP_PORT(bp);
14875         u32 wb_data[2];
14876
14877         /* Reset PTP event detection rules - will be configured in the IOCTL */
14878         REG_WR(bp, port ? NIG_REG_P1_LLH_PTP_PARAM_MASK :
14879                NIG_REG_P0_LLH_PTP_PARAM_MASK, 0x7FF);
14880         REG_WR(bp, port ? NIG_REG_P1_LLH_PTP_RULE_MASK :
14881                NIG_REG_P0_LLH_PTP_RULE_MASK, 0x3FFF);
14882         REG_WR(bp, port ? NIG_REG_P1_TLLH_PTP_PARAM_MASK :
14883                NIG_REG_P0_TLLH_PTP_PARAM_MASK, 0x7FF);
14884         REG_WR(bp, port ? NIG_REG_P1_TLLH_PTP_RULE_MASK :
14885                NIG_REG_P0_TLLH_PTP_RULE_MASK, 0x3FFF);
14886
14887         /* Disable PTP packets to host - will be configured in the IOCTL*/
14888         REG_WR(bp, port ? NIG_REG_P1_LLH_PTP_TO_HOST :
14889                NIG_REG_P0_LLH_PTP_TO_HOST, 0x0);
14890
14891         /* Enable the PTP feature */
14892         REG_WR(bp, port ? NIG_REG_P1_PTP_EN :
14893                NIG_REG_P0_PTP_EN, 0x3F);
14894
14895         /* Enable the free-running counter */
14896         wb_data[0] = 0;
14897         wb_data[1] = 0;
14898         REG_WR_DMAE(bp, NIG_REG_TIMESYNC_GEN_REG + tsgen_ctrl, wb_data, 2);
14899
14900         /* Reset drift register (offset register is not reset) */
14901         rc = bnx2x_send_reset_timesync_ramrod(bp);
14902         if (rc) {
14903                 BNX2X_ERR("Failed to reset PHC drift register\n");
14904                 return -EFAULT;
14905         }
14906
14907         /* Reset possibly old timestamps */
14908         REG_WR(bp, port ? NIG_REG_P1_LLH_PTP_HOST_BUF_SEQID :
14909                NIG_REG_P0_LLH_PTP_HOST_BUF_SEQID, 0x10000);
14910         REG_WR(bp, port ? NIG_REG_P1_TLLH_PTP_BUF_SEQID :
14911                NIG_REG_P0_TLLH_PTP_BUF_SEQID, 0x10000);
14912
14913         return 0;
14914 }
14915
14916 /* Called during load, to initialize PTP-related stuff */
14917 void bnx2x_init_ptp(struct bnx2x *bp)
14918 {
14919         int rc;
14920
14921         /* Configure PTP in HW */
14922         rc = bnx2x_configure_ptp(bp);
14923         if (rc) {
14924                 BNX2X_ERR("Stopping PTP initialization\n");
14925                 return;
14926         }
14927
14928         /* Init work queue for Tx timestamping */
14929         INIT_WORK(&bp->ptp_task, bnx2x_ptp_task);
14930
14931         /* Init cyclecounter and timecounter. This is done only in the first
14932          * load. If done in every load, PTP application will fail when doing
14933          * unload / load (e.g. MTU change) while it is running.
14934          */
14935         if (!bp->timecounter_init_done) {
14936                 bnx2x_init_cyclecounter(bp);
14937                 timecounter_init(&bp->timecounter, &bp->cyclecounter,
14938                                  ktime_to_ns(ktime_get_real()));
14939                 bp->timecounter_init_done = 1;
14940         }
14941
14942         DP(BNX2X_MSG_PTP, "PTP initialization ended successfully\n");
14943 }