drivers/net/ethernet/broadcom/bnx2x/bnx2x_link.c

   1 /* Copyright 2008-2012 Broadcom Corporation
   2  *
   3  * Unless you and Broadcom execute a separate written software license
   4  * agreement governing use of this software, this software is licensed to you
   5  * under the terms of the GNU General Public License version 2, available
   6  * at http://www.gnu.org/licenses/old-licenses/gpl-2.0.html (the "GPL").
   7  *
   8  * Notwithstanding the above, under no circumstances may you combine this
   9  * software in any way with any other Broadcom software provided under a
  10  * license other than the GPL, without Broadcom's express prior written
  11  * consent.
  12  *
  13  * Written by Yaniv Rosner
  14  *
  15  */
  16
  17 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
  18
  19 #include <linux/kernel.h>
  20 #include <linux/errno.h>
  21 #include <linux/pci.h>
  22 #include <linux/netdevice.h>
  23 #include <linux/delay.h>
  24 #include <linux/ethtool.h>
  25 #include <linux/mutex.h>
  26
  27 #include "bnx2x.h"
  28 #include "bnx2x_cmn.h"
  29
  30 /********************************************************/
  31 #define ETH_HLEN                        14
  32 /* L2 header size + 2*VLANs (8 bytes) + LLC SNAP (8 bytes) */
  33 #define ETH_OVREHEAD                    (ETH_HLEN + 8 + 8)
  34 #define ETH_MIN_PACKET_SIZE             60
  35 #define ETH_MAX_PACKET_SIZE             1500
  36 #define ETH_MAX_JUMBO_PACKET_SIZE       9600
  37 #define MDIO_ACCESS_TIMEOUT             1000
  38 #define WC_LANE_MAX                     4
  39 #define I2C_SWITCH_WIDTH                2
  40 #define I2C_BSC0                        0
  41 #define I2C_BSC1                        1
  42 #define I2C_WA_RETRY_CNT                3
  43 #define MCPR_IMC_COMMAND_READ_OP        1
  44 #define MCPR_IMC_COMMAND_WRITE_OP       2
  45
  46 /* LED Blink rate that will achieve ~15.9Hz */
  47 #define LED_BLINK_RATE_VAL_E3           354
  48 #define LED_BLINK_RATE_VAL_E1X_E2       480
  49 /***********************************************************/
  50 /*                      Shortcut definitions               */
  51 /***********************************************************/
  52
  53 #define NIG_LATCH_BC_ENABLE_MI_INT 0
  54
  55 #define NIG_STATUS_EMAC0_MI_INT \
  56                 NIG_STATUS_INTERRUPT_PORT0_REG_STATUS_EMAC0_MISC_MI_INT
  57 #define NIG_STATUS_XGXS0_LINK10G \
  58                 NIG_STATUS_INTERRUPT_PORT0_REG_STATUS_XGXS0_LINK10G
  59 #define NIG_STATUS_XGXS0_LINK_STATUS \
  60                 NIG_STATUS_INTERRUPT_PORT0_REG_STATUS_XGXS0_LINK_STATUS
  61 #define NIG_STATUS_XGXS0_LINK_STATUS_SIZE \
  62                 NIG_STATUS_INTERRUPT_PORT0_REG_STATUS_XGXS0_LINK_STATUS_SIZE
  63 #define NIG_STATUS_SERDES0_LINK_STATUS \
  64                 NIG_STATUS_INTERRUPT_PORT0_REG_STATUS_SERDES0_LINK_STATUS
  65 #define NIG_MASK_MI_INT \
  66                 NIG_MASK_INTERRUPT_PORT0_REG_MASK_EMAC0_MISC_MI_INT
  67 #define NIG_MASK_XGXS0_LINK10G \
  68                 NIG_MASK_INTERRUPT_PORT0_REG_MASK_XGXS0_LINK10G
  69 #define NIG_MASK_XGXS0_LINK_STATUS \
  70                 NIG_MASK_INTERRUPT_PORT0_REG_MASK_XGXS0_LINK_STATUS
  71 #define NIG_MASK_SERDES0_LINK_STATUS \
  72                 NIG_MASK_INTERRUPT_PORT0_REG_MASK_SERDES0_LINK_STATUS
  73
  74 #define MDIO_AN_CL73_OR_37_COMPLETE \
  75                 (MDIO_GP_STATUS_TOP_AN_STATUS1_CL73_AUTONEG_COMPLETE | \
  76                  MDIO_GP_STATUS_TOP_AN_STATUS1_CL37_AUTONEG_COMPLETE)
  77
  78 #define XGXS_RESET_BITS \
  79         (MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_XGXS0_RSTB_HW |   \
  80          MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_XGXS0_IDDQ |      \
  81          MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_XGXS0_PWRDWN |    \
  82          MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_XGXS0_PWRDWN_SD | \
  83          MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_XGXS0_TXD_FIFO_RSTB)
  84
  85 #define SERDES_RESET_BITS \
  86         (MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_SERDES0_RSTB_HW | \
  87          MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_SERDES0_IDDQ |    \
  88          MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_SERDES0_PWRDWN |  \
  89          MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_SERDES0_PWRDWN_SD)
  90
  91 #define AUTONEG_CL37            SHARED_HW_CFG_AN_ENABLE_CL37
  92 #define AUTONEG_CL73            SHARED_HW_CFG_AN_ENABLE_CL73
  93 #define AUTONEG_BAM             SHARED_HW_CFG_AN_ENABLE_BAM
  94 #define AUTONEG_PARALLEL \
  95                                 SHARED_HW_CFG_AN_ENABLE_PARALLEL_DETECTION
  96 #define AUTONEG_SGMII_FIBER_AUTODET \
  97                                 SHARED_HW_CFG_AN_EN_SGMII_FIBER_AUTO_DETECT
  98 #define AUTONEG_REMOTE_PHY      SHARED_HW_CFG_AN_ENABLE_REMOTE_PHY
  99
 100 #define GP_STATUS_PAUSE_RSOLUTION_TXSIDE \
 101                         MDIO_GP_STATUS_TOP_AN_STATUS1_PAUSE_RSOLUTION_TXSIDE
 102 #define GP_STATUS_PAUSE_RSOLUTION_RXSIDE \
 103                         MDIO_GP_STATUS_TOP_AN_STATUS1_PAUSE_RSOLUTION_RXSIDE
 104 #define GP_STATUS_SPEED_MASK \
 105                         MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_MASK
 106 #define GP_STATUS_10M   MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10M
 107 #define GP_STATUS_100M  MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_100M
 108 #define GP_STATUS_1G    MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_1G
 109 #define GP_STATUS_2_5G  MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_2_5G
 110 #define GP_STATUS_5G    MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_5G
 111 #define GP_STATUS_6G    MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_6G
 112 #define GP_STATUS_10G_HIG \
 113                         MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10G_HIG
 114 #define GP_STATUS_10G_CX4 \
 115                         MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10G_CX4
 116 #define GP_STATUS_1G_KX MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_1G_KX
 117 #define GP_STATUS_10G_KX4 \
 118                         MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10G_KX4
 119 #define GP_STATUS_10G_KR MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10G_KR
 120 #define GP_STATUS_10G_XFI   MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10G_XFI
 121 #define GP_STATUS_20G_DXGXS MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_20G_DXGXS
 122 #define GP_STATUS_10G_SFI   MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10G_SFI
 123 #define LINK_10THD              LINK_STATUS_SPEED_AND_DUPLEX_10THD
 124 #define LINK_10TFD              LINK_STATUS_SPEED_AND_DUPLEX_10TFD
 125 #define LINK_100TXHD            LINK_STATUS_SPEED_AND_DUPLEX_100TXHD
 126 #define LINK_100T4              LINK_STATUS_SPEED_AND_DUPLEX_100T4
 127 #define LINK_100TXFD            LINK_STATUS_SPEED_AND_DUPLEX_100TXFD
 128 #define LINK_1000THD            LINK_STATUS_SPEED_AND_DUPLEX_1000THD
 129 #define LINK_1000TFD            LINK_STATUS_SPEED_AND_DUPLEX_1000TFD
 130 #define LINK_1000XFD            LINK_STATUS_SPEED_AND_DUPLEX_1000XFD
 131 #define LINK_2500THD            LINK_STATUS_SPEED_AND_DUPLEX_2500THD
 132 #define LINK_2500TFD            LINK_STATUS_SPEED_AND_DUPLEX_2500TFD
 133 #define LINK_2500XFD            LINK_STATUS_SPEED_AND_DUPLEX_2500XFD
 134 #define LINK_10GTFD             LINK_STATUS_SPEED_AND_DUPLEX_10GTFD
 135 #define LINK_10GXFD             LINK_STATUS_SPEED_AND_DUPLEX_10GXFD
 136 #define LINK_20GTFD             LINK_STATUS_SPEED_AND_DUPLEX_20GTFD
 137 #define LINK_20GXFD             LINK_STATUS_SPEED_AND_DUPLEX_20GXFD
 138
 139
 140
 141 #define SFP_EEPROM_CON_TYPE_ADDR                0x2
 142         #define SFP_EEPROM_CON_TYPE_VAL_LC      0x7
 143         #define SFP_EEPROM_CON_TYPE_VAL_COPPER  0x21
 144
 145
 146 #define SFP_EEPROM_COMP_CODE_ADDR               0x3
 147         #define SFP_EEPROM_COMP_CODE_SR_MASK    (1<<4)
 148         #define SFP_EEPROM_COMP_CODE_LR_MASK    (1<<5)
 149         #define SFP_EEPROM_COMP_CODE_LRM_MASK   (1<<6)
 150
 151 #define SFP_EEPROM_FC_TX_TECH_ADDR              0x8
 152         #define SFP_EEPROM_FC_TX_TECH_BITMASK_COPPER_PASSIVE 0x4
 153         #define SFP_EEPROM_FC_TX_TECH_BITMASK_COPPER_ACTIVE  0x8
 154
 155 #define SFP_EEPROM_OPTIONS_ADDR                 0x40
 156         #define SFP_EEPROM_OPTIONS_LINEAR_RX_OUT_MASK 0x1
 157 #define SFP_EEPROM_OPTIONS_SIZE                 2
 158
 159 #define EDC_MODE_LINEAR                         0x0022
 160 #define EDC_MODE_LIMITING                               0x0044
 161 #define EDC_MODE_PASSIVE_DAC                    0x0055
 162
 163 /* BRB default for class 0 E2 */
 164 #define DEFAULT0_E2_BRB_MAC_PAUSE_XOFF_THR      170
 165 #define DEFAULT0_E2_BRB_MAC_PAUSE_XON_THR               250
 166 #define DEFAULT0_E2_BRB_MAC_FULL_XOFF_THR               10
 167 #define DEFAULT0_E2_BRB_MAC_FULL_XON_THR                50
 168
 169 /* BRB thresholds for E2*/
 170 #define PFC_E2_BRB_MAC_PAUSE_XOFF_THR_PAUSE             170
 171 #define PFC_E2_BRB_MAC_PAUSE_XOFF_THR_NON_PAUSE         0
 172
 173 #define PFC_E2_BRB_MAC_PAUSE_XON_THR_PAUSE              250
 174 #define PFC_E2_BRB_MAC_PAUSE_XON_THR_NON_PAUSE          0
 175
 176 #define PFC_E2_BRB_MAC_FULL_XOFF_THR_PAUSE              10
 177 #define PFC_E2_BRB_MAC_FULL_XOFF_THR_NON_PAUSE          90
 178
 179 #define PFC_E2_BRB_MAC_FULL_XON_THR_PAUSE                       50
 180 #define PFC_E2_BRB_MAC_FULL_XON_THR_NON_PAUSE           250
 181
 182 /* BRB default for class 0 E3A0 */
 183 #define DEFAULT0_E3A0_BRB_MAC_PAUSE_XOFF_THR    290
 184 #define DEFAULT0_E3A0_BRB_MAC_PAUSE_XON_THR     410
 185 #define DEFAULT0_E3A0_BRB_MAC_FULL_XOFF_THR     10
 186 #define DEFAULT0_E3A0_BRB_MAC_FULL_XON_THR      50
 187
 188 /* BRB thresholds for E3A0 */
 189 #define PFC_E3A0_BRB_MAC_PAUSE_XOFF_THR_PAUSE           290
 190 #define PFC_E3A0_BRB_MAC_PAUSE_XOFF_THR_NON_PAUSE               0
 191
 192 #define PFC_E3A0_BRB_MAC_PAUSE_XON_THR_PAUSE            410
 193 #define PFC_E3A0_BRB_MAC_PAUSE_XON_THR_NON_PAUSE                0
 194
 195 #define PFC_E3A0_BRB_MAC_FULL_XOFF_THR_PAUSE            10
 196 #define PFC_E3A0_BRB_MAC_FULL_XOFF_THR_NON_PAUSE                170
 197
 198 #define PFC_E3A0_BRB_MAC_FULL_XON_THR_PAUSE             50
 199 #define PFC_E3A0_BRB_MAC_FULL_XON_THR_NON_PAUSE         410
 200
 201 /* BRB default for E3B0 */
 202 #define DEFAULT0_E3B0_BRB_MAC_PAUSE_XOFF_THR    330
 203 #define DEFAULT0_E3B0_BRB_MAC_PAUSE_XON_THR     490
 204 #define DEFAULT0_E3B0_BRB_MAC_FULL_XOFF_THR     15
 205 #define DEFAULT0_E3B0_BRB_MAC_FULL_XON_THR      55
 206
 207 /* BRB thresholds for E3B0 2 port mode*/
 208 #define PFC_E3B0_2P_BRB_MAC_PAUSE_XOFF_THR_PAUSE                1025
 209 #define PFC_E3B0_2P_BRB_MAC_PAUSE_XOFF_THR_NON_PAUSE    0
 210
 211 #define PFC_E3B0_2P_BRB_MAC_PAUSE_XON_THR_PAUSE         1025
 212 #define PFC_E3B0_2P_BRB_MAC_PAUSE_XON_THR_NON_PAUSE     0
 213
 214 #define PFC_E3B0_2P_BRB_MAC_FULL_XOFF_THR_PAUSE         10
 215 #define PFC_E3B0_2P_BRB_MAC_FULL_XOFF_THR_NON_PAUSE     1025
 216
 217 #define PFC_E3B0_2P_BRB_MAC_FULL_XON_THR_PAUSE          50
 218 #define PFC_E3B0_2P_BRB_MAC_FULL_XON_THR_NON_PAUSE      1025
 219
 220 /* only for E3B0*/
 221 #define PFC_E3B0_2P_BRB_FULL_LB_XOFF_THR                        1025
 222 #define PFC_E3B0_2P_BRB_FULL_LB_XON_THR                 1025
 223
 224 /* Lossy +Lossless GUARANTIED == GUART */
 225 #define PFC_E3B0_2P_MIX_PAUSE_LB_GUART                  284
 226 /* Lossless +Lossless*/
 227 #define PFC_E3B0_2P_PAUSE_LB_GUART                      236
 228 /* Lossy +Lossy*/
 229 #define PFC_E3B0_2P_NON_PAUSE_LB_GUART                  342
 230
 231 /* Lossy +Lossless*/
 232 #define PFC_E3B0_2P_MIX_PAUSE_MAC_0_CLASS_T_GUART               284
 233 /* Lossless +Lossless*/
 234 #define PFC_E3B0_2P_PAUSE_MAC_0_CLASS_T_GUART           236
 235 /* Lossy +Lossy*/
 236 #define PFC_E3B0_2P_NON_PAUSE_MAC_0_CLASS_T_GUART               336
 237 #define PFC_E3B0_2P_BRB_MAC_0_CLASS_T_GUART_HYST                80
 238
 239 #define PFC_E3B0_2P_BRB_MAC_1_CLASS_T_GUART             0
 240 #define PFC_E3B0_2P_BRB_MAC_1_CLASS_T_GUART_HYST                0
 241
 242 /* BRB thresholds for E3B0 4 port mode */
 243 #define PFC_E3B0_4P_BRB_MAC_PAUSE_XOFF_THR_PAUSE                304
 244 #define PFC_E3B0_4P_BRB_MAC_PAUSE_XOFF_THR_NON_PAUSE    0
 245
 246 #define PFC_E3B0_4P_BRB_MAC_PAUSE_XON_THR_PAUSE         384
 247 #define PFC_E3B0_4P_BRB_MAC_PAUSE_XON_THR_NON_PAUSE     0
 248
 249 #define PFC_E3B0_4P_BRB_MAC_FULL_XOFF_THR_PAUSE         10
 250 #define PFC_E3B0_4P_BRB_MAC_FULL_XOFF_THR_NON_PAUSE     304
 251
 252 #define PFC_E3B0_4P_BRB_MAC_FULL_XON_THR_PAUSE          50
 253 #define PFC_E3B0_4P_BRB_MAC_FULL_XON_THR_NON_PAUSE      384
 254
 255 /* only for E3B0*/
 256 #define PFC_E3B0_4P_BRB_FULL_LB_XOFF_THR                        304
 257 #define PFC_E3B0_4P_BRB_FULL_LB_XON_THR                 384
 258 #define PFC_E3B0_4P_LB_GUART            120
 259
 260 #define PFC_E3B0_4P_BRB_MAC_0_CLASS_T_GUART             120
 261 #define PFC_E3B0_4P_BRB_MAC_0_CLASS_T_GUART_HYST        80
 262
 263 #define PFC_E3B0_4P_BRB_MAC_1_CLASS_T_GUART             80
 264 #define PFC_E3B0_4P_BRB_MAC_1_CLASS_T_GUART_HYST        120
 265
 266 /* Pause defines*/
 267 #define DEFAULT_E3B0_BRB_FULL_LB_XOFF_THR                       330
 268 #define DEFAULT_E3B0_BRB_FULL_LB_XON_THR                        490
 269 #define DEFAULT_E3B0_LB_GUART           40
 270
 271 #define DEFAULT_E3B0_BRB_MAC_0_CLASS_T_GUART            40
 272 #define DEFAULT_E3B0_BRB_MAC_0_CLASS_T_GUART_HYST       0
 273
 274 #define DEFAULT_E3B0_BRB_MAC_1_CLASS_T_GUART            40
 275 #define DEFAULT_E3B0_BRB_MAC_1_CLASS_T_GUART_HYST       0
 276
 277 /* ETS defines*/
 278 #define DCBX_INVALID_COS                                        (0xFF)
 279
 280 #define ETS_BW_LIMIT_CREDIT_UPPER_BOUND         (0x5000)
 281 #define ETS_BW_LIMIT_CREDIT_WEIGHT              (0x5000)
 282 #define ETS_E3B0_NIG_MIN_W_VAL_UP_TO_10GBPS             (1360)
 283 #define ETS_E3B0_NIG_MIN_W_VAL_20GBPS                   (2720)
 284 #define ETS_E3B0_PBF_MIN_W_VAL                          (10000)
 285
 286 #define MAX_PACKET_SIZE                                 (9700)
 287 #define WC_UC_TIMEOUT                                   100
 288 #define MAX_KR_LINK_RETRY                               4
 289
 290 /**********************************************************/
 291 /*                     INTERFACE                          */
 292 /**********************************************************/
 293
 294 #define CL22_WR_OVER_CL45(_bp, _phy, _bank, _addr, _val) \
 295         bnx2x_cl45_write(_bp, _phy, \
 296                 (_phy)->def_md_devad, \
 297                 (_bank + (_addr & 0xf)), \
 298                 _val)
 299
 300 #define CL22_RD_OVER_CL45(_bp, _phy, _bank, _addr, _val) \
 301         bnx2x_cl45_read(_bp, _phy, \
 302                 (_phy)->def_md_devad, \
 303                 (_bank + (_addr & 0xf)), \
 304                 _val)
 305
 306 static u32 bnx2x_bits_en(struct bnx2x *bp, u32 reg, u32 bits)
 307 {
 308         u32 val = REG_RD(bp, reg);
 309
 310         val |= bits;
 311         REG_WR(bp, reg, val);
 312         return val;
 313 }
 314
 315 static u32 bnx2x_bits_dis(struct bnx2x *bp, u32 reg, u32 bits)
 316 {
 317         u32 val = REG_RD(bp, reg);
 318
 319         val &= ~bits;
 320         REG_WR(bp, reg, val);
 321         return val;
 322 }
 323
 324 /******************************************************************/
 325 /*                      EPIO/GPIO section                         */
 326 /******************************************************************/
 327 static void bnx2x_get_epio(struct bnx2x *bp, u32 epio_pin, u32 *en)
 328 {
 329         u32 epio_mask, gp_oenable;
 330         *en = 0;
 331         /* Sanity check */
 332         if (epio_pin > 31) {
 333                 DP(NETIF_MSG_LINK, "Invalid EPIO pin %d to get\n", epio_pin);
 334                 return;
 335         }
 336
 337         epio_mask = 1 << epio_pin;
 338         /* Set this EPIO to output */
 339         gp_oenable = REG_RD(bp, MCP_REG_MCPR_GP_OENABLE);
 340         REG_WR(bp, MCP_REG_MCPR_GP_OENABLE, gp_oenable & ~epio_mask);
 341
 342         *en = (REG_RD(bp, MCP_REG_MCPR_GP_INPUTS) & epio_mask) >> epio_pin;
 343 }
 344 static void bnx2x_set_epio(struct bnx2x *bp, u32 epio_pin, u32 en)
 345 {
 346         u32 epio_mask, gp_output, gp_oenable;
 347
 348         /* Sanity check */
 349         if (epio_pin > 31) {
 350                 DP(NETIF_MSG_LINK, "Invalid EPIO pin %d to set\n", epio_pin);
 351                 return;
 352         }
 353         DP(NETIF_MSG_LINK, "Setting EPIO pin %d to %d\n", epio_pin, en);
 354         epio_mask = 1 << epio_pin;
 355         /* Set this EPIO to output */
 356         gp_output = REG_RD(bp, MCP_REG_MCPR_GP_OUTPUTS);
 357         if (en)
 358                 gp_output |= epio_mask;
 359         else
 360                 gp_output &= ~epio_mask;
 361
 362         REG_WR(bp, MCP_REG_MCPR_GP_OUTPUTS, gp_output);
 363
 364         /* Set the value for this EPIO */
 365         gp_oenable = REG_RD(bp, MCP_REG_MCPR_GP_OENABLE);
 366         REG_WR(bp, MCP_REG_MCPR_GP_OENABLE, gp_oenable | epio_mask);
 367 }
 368
 369 static void bnx2x_set_cfg_pin(struct bnx2x *bp, u32 pin_cfg, u32 val)
 370 {
 371         if (pin_cfg == PIN_CFG_NA)
 372                 return;
 373         if (pin_cfg >= PIN_CFG_EPIO0) {
 374                 bnx2x_set_epio(bp, pin_cfg - PIN_CFG_EPIO0, val);
 375         } else {
 376                 u8 gpio_num = (pin_cfg - PIN_CFG_GPIO0_P0) & 0x3;
 377                 u8 gpio_port = (pin_cfg - PIN_CFG_GPIO0_P0) >> 2;
 378                 bnx2x_set_gpio(bp, gpio_num, (u8)val, gpio_port);
 379         }
 380 }
 381
 382 static u32 bnx2x_get_cfg_pin(struct bnx2x *bp, u32 pin_cfg, u32 *val)
 383 {
 384         if (pin_cfg == PIN_CFG_NA)
 385                 return -EINVAL;
 386         if (pin_cfg >= PIN_CFG_EPIO0) {
 387                 bnx2x_get_epio(bp, pin_cfg - PIN_CFG_EPIO0, val);
 388         } else {
 389                 u8 gpio_num = (pin_cfg - PIN_CFG_GPIO0_P0) & 0x3;
 390                 u8 gpio_port = (pin_cfg - PIN_CFG_GPIO0_P0) >> 2;
 391                 *val = bnx2x_get_gpio(bp, gpio_num, gpio_port);
 392         }
 393         return 0;
 394
 395 }
 396 /******************************************************************/
 397 /*                              ETS section                       */
 398 /******************************************************************/
 399 static void bnx2x_ets_e2e3a0_disabled(struct link_params *params)
 400 {
 401         /* ETS disabled configuration*/
 402         struct bnx2x *bp = params->bp;
 403
 404         DP(NETIF_MSG_LINK, "ETS E2E3 disabled configuration\n");
 405
 406         /* mapping between entry  priority to client number (0,1,2 -debug and
 407          * management clients, 3 - COS0 client, 4 - COS client)(HIGHEST)
 408          * 3bits client num.
 409          *   PRI4    |    PRI3    |    PRI2    |    PRI1    |    PRI0
 410          * cos1-100     cos0-011     dbg1-010     dbg0-001     MCP-000
 411          */
 412
 413         REG_WR(bp, NIG_REG_P0_TX_ARB_PRIORITY_CLIENT, 0x4688);
 414         /* Bitmap of 5bits length. Each bit specifies whether the entry behaves
 415          * as strict.  Bits 0,1,2 - debug and management entries, 3 -
 416          * COS0 entry, 4 - COS1 entry.
 417          * COS1 | COS0 | DEBUG1 | DEBUG0 | MGMT
 418          * bit4   bit3    bit2   bit1     bit0
 419          * MCP and debug are strict
 420          */
 421
 422         REG_WR(bp, NIG_REG_P0_TX_ARB_CLIENT_IS_STRICT, 0x7);
 423         /* defines which entries (clients) are subjected to WFQ arbitration */
 424         REG_WR(bp, NIG_REG_P0_TX_ARB_CLIENT_IS_SUBJECT2WFQ, 0);
 425         /* For strict priority entries defines the number of consecutive
 426          * slots for the highest priority.
 427          */
 428         REG_WR(bp, NIG_REG_P0_TX_ARB_NUM_STRICT_ARB_SLOTS, 0x100);
 429         /* mapping between the CREDIT_WEIGHT registers and actual client
 430          * numbers
 431          */
 432         REG_WR(bp, NIG_REG_P0_TX_ARB_CLIENT_CREDIT_MAP, 0);
 433         REG_WR(bp, NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_0, 0);
 434         REG_WR(bp, NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_1, 0);
 435
 436         REG_WR(bp, NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_0, 0);
 437         REG_WR(bp, NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_1, 0);
 438         REG_WR(bp, PBF_REG_HIGH_PRIORITY_COS_NUM, 0);
 439         /* ETS mode disable */
 440         REG_WR(bp, PBF_REG_ETS_ENABLED, 0);
 441         /* If ETS mode is enabled (there is no strict priority) defines a WFQ
 442          * weight for COS0/COS1.
 443          */
 444         REG_WR(bp, PBF_REG_COS0_WEIGHT, 0x2710);
 445         REG_WR(bp, PBF_REG_COS1_WEIGHT, 0x2710);
 446         /* Upper bound that COS0_WEIGHT can reach in the WFQ arbiter */
 447         REG_WR(bp, PBF_REG_COS0_UPPER_BOUND, 0x989680);
 448         REG_WR(bp, PBF_REG_COS1_UPPER_BOUND, 0x989680);
 449         /* Defines the number of consecutive slots for the strict priority */
 450         REG_WR(bp, PBF_REG_NUM_STRICT_ARB_SLOTS, 0);
 451 }
 452 /******************************************************************************
 453 * Description:
 454 *       Getting min_w_val will be set according to line speed .
 455 *.
 456 ******************************************************************************/
 457 static u32 bnx2x_ets_get_min_w_val_nig(const struct link_vars *vars)
 458 {
 459         u32 min_w_val = 0;
 460         /* Calculate min_w_val.*/
 461         if (vars->link_up) {
 462                 if (vars->line_speed == SPEED_20000)
 463                         min_w_val = ETS_E3B0_NIG_MIN_W_VAL_20GBPS;
 464                 else
 465                         min_w_val = ETS_E3B0_NIG_MIN_W_VAL_UP_TO_10GBPS;
 466         } else
 467                 min_w_val = ETS_E3B0_NIG_MIN_W_VAL_20GBPS;
 468         /* If the link isn't up (static configuration for example ) The
 469          * link will be according to 20GBPS.
 470          */
 471         return min_w_val;
 472 }
 473 /******************************************************************************
 474 * Description:
 475 *       Getting credit upper bound form min_w_val.
 476 *.
 477 ******************************************************************************/
 478 static u32 bnx2x_ets_get_credit_upper_bound(const u32 min_w_val)
 479 {
 480         const u32 credit_upper_bound = (u32)MAXVAL((150 * min_w_val),
 481                                                 MAX_PACKET_SIZE);
 482         return credit_upper_bound;
 483 }
 484 /******************************************************************************
 485 * Description:
 486 *       Set credit upper bound for NIG.
 487 *.
 488 ******************************************************************************/
 489 static void bnx2x_ets_e3b0_set_credit_upper_bound_nig(
 490         const struct link_params *params,
 491         const u32 min_w_val)
 492 {
 493         struct bnx2x *bp = params->bp;
 494         const u8 port = params->port;
 495         const u32 credit_upper_bound =
 496             bnx2x_ets_get_credit_upper_bound(min_w_val);
 497
 498         REG_WR(bp, (port) ? NIG_REG_P1_TX_ARB_CREDIT_UPPER_BOUND_0 :
 499                 NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_0, credit_upper_bound);
 500         REG_WR(bp, (port) ? NIG_REG_P1_TX_ARB_CREDIT_UPPER_BOUND_1 :
 501                    NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_1, credit_upper_bound);
 502         REG_WR(bp, (port) ? NIG_REG_P1_TX_ARB_CREDIT_UPPER_BOUND_2 :
 503                    NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_2, credit_upper_bound);
 504         REG_WR(bp, (port) ? NIG_REG_P1_TX_ARB_CREDIT_UPPER_BOUND_3 :
 505                    NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_3, credit_upper_bound);
 506         REG_WR(bp, (port) ? NIG_REG_P1_TX_ARB_CREDIT_UPPER_BOUND_4 :
 507                    NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_4, credit_upper_bound);
 508         REG_WR(bp, (port) ? NIG_REG_P1_TX_ARB_CREDIT_UPPER_BOUND_5 :
 509                    NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_5, credit_upper_bound);
 510
 511         if (!port) {
 512                 REG_WR(bp, NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_6,
 513                         credit_upper_bound);
 514                 REG_WR(bp, NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_7,
 515                         credit_upper_bound);
 516                 REG_WR(bp, NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_8,
 517                         credit_upper_bound);
 518         }
 519 }
 520 /******************************************************************************
 521 * Description:
 522 *       Will return the NIG ETS registers to init values.Except
 523 *       credit_upper_bound.
 524 *       That isn't used in this configuration (No WFQ is enabled) and will be
 525 *       configured acording to spec
 526 *.
 527 ******************************************************************************/
 528 static void bnx2x_ets_e3b0_nig_disabled(const struct link_params *params,
 529                                         const struct link_vars *vars)
 530 {
 531         struct bnx2x *bp = params->bp;
 532         const u8 port = params->port;
 533         const u32 min_w_val = bnx2x_ets_get_min_w_val_nig(vars);
 534         /* Mapping between entry  priority to client number (0,1,2 -debug and
 535          * management clients, 3 - COS0 client, 4 - COS1, ... 8 -
 536          * COS5)(HIGHEST) 4bits client num.TODO_ETS - Should be done by
 537          * reset value or init tool
 538          */
 539         if (port) {
 540                 REG_WR(bp, NIG_REG_P1_TX_ARB_PRIORITY_CLIENT2_LSB, 0x543210);
 541                 REG_WR(bp, NIG_REG_P1_TX_ARB_PRIORITY_CLIENT2_MSB, 0x0);
 542         } else {
 543                 REG_WR(bp, NIG_REG_P0_TX_ARB_PRIORITY_CLIENT2_LSB, 0x76543210);
 544                 REG_WR(bp, NIG_REG_P0_TX_ARB_PRIORITY_CLIENT2_MSB, 0x8);
 545         }
 546         /* For strict priority entries defines the number of consecutive
 547          * slots for the highest priority.
 548          */
 549         REG_WR(bp, (port) ? NIG_REG_P1_TX_ARB_NUM_STRICT_ARB_SLOTS :
 550                    NIG_REG_P1_TX_ARB_NUM_STRICT_ARB_SLOTS, 0x100);
 551         /* Mapping between the CREDIT_WEIGHT registers and actual client
 552          * numbers
 553          */
 554         if (port) {
 555                 /*Port 1 has 6 COS*/
 556                 REG_WR(bp, NIG_REG_P1_TX_ARB_CLIENT_CREDIT_MAP2_LSB, 0x210543);
 557                 REG_WR(bp, NIG_REG_P1_TX_ARB_CLIENT_CREDIT_MAP2_MSB, 0x0);
 558         } else {
 559                 /*Port 0 has 9 COS*/
 560                 REG_WR(bp, NIG_REG_P0_TX_ARB_CLIENT_CREDIT_MAP2_LSB,
 561                        0x43210876);
 562                 REG_WR(bp, NIG_REG_P0_TX_ARB_CLIENT_CREDIT_MAP2_MSB, 0x5);
 563         }
 564
 565         /* Bitmap of 5bits length. Each bit specifies whether the entry behaves
 566          * as strict.  Bits 0,1,2 - debug and management entries, 3 -
 567          * COS0 entry, 4 - COS1 entry.
 568          * COS1 | COS0 | DEBUG1 | DEBUG0 | MGMT
 569          * bit4   bit3    bit2   bit1     bit0
 570          * MCP and debug are strict
 571          */
 572         if (port)
 573                 REG_WR(bp, NIG_REG_P1_TX_ARB_CLIENT_IS_STRICT, 0x3f);
 574         else
 575                 REG_WR(bp, NIG_REG_P0_TX_ARB_CLIENT_IS_STRICT, 0x1ff);
 576         /* defines which entries (clients) are subjected to WFQ arbitration */
 577         REG_WR(bp, (port) ? NIG_REG_P1_TX_ARB_CLIENT_IS_SUBJECT2WFQ :
 578                    NIG_REG_P0_TX_ARB_CLIENT_IS_SUBJECT2WFQ, 0);
 579
 580         /* Please notice the register address are note continuous and a
 581          * for here is note appropriate.In 2 port mode port0 only COS0-5
 582          * can be used. DEBUG1,DEBUG1,MGMT are never used for WFQ* In 4
 583          * port mode port1 only COS0-2 can be used. DEBUG1,DEBUG1,MGMT
 584          * are never used for WFQ
 585          */
 586         REG_WR(bp, (port) ? NIG_REG_P1_TX_ARB_CREDIT_WEIGHT_0 :
 587                    NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_0, 0x0);
 588         REG_WR(bp, (port) ? NIG_REG_P1_TX_ARB_CREDIT_WEIGHT_1 :
 589                    NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_1, 0x0);
 590         REG_WR(bp, (port) ? NIG_REG_P1_TX_ARB_CREDIT_WEIGHT_2 :
 591                    NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_2, 0x0);
 592         REG_WR(bp, (port) ? NIG_REG_P1_TX_ARB_CREDIT_WEIGHT_3 :
 593                    NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_3, 0x0);
 594         REG_WR(bp, (port) ? NIG_REG_P1_TX_ARB_CREDIT_WEIGHT_4 :
 595                    NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_4, 0x0);
 596         REG_WR(bp, (port) ? NIG_REG_P1_TX_ARB_CREDIT_WEIGHT_5 :
 597                    NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_5, 0x0);
 598         if (!port) {
 599                 REG_WR(bp, NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_6, 0x0);
 600                 REG_WR(bp, NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_7, 0x0);
 601                 REG_WR(bp, NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_8, 0x0);
 602         }
 603
 604         bnx2x_ets_e3b0_set_credit_upper_bound_nig(params, min_w_val);
 605 }
 606 /******************************************************************************
 607 * Description:
 608 *       Set credit upper bound for PBF.
 609 *.
 610 ******************************************************************************/
 611 static void bnx2x_ets_e3b0_set_credit_upper_bound_pbf(
 612         const struct link_params *params,
 613         const u32 min_w_val)
 614 {
 615         struct bnx2x *bp = params->bp;
 616         const u32 credit_upper_bound =
 617             bnx2x_ets_get_credit_upper_bound(min_w_val);
 618         const u8 port = params->port;
 619         u32 base_upper_bound = 0;
 620         u8 max_cos = 0;
 621         u8 i = 0;
 622         /* In 2 port mode port0 has COS0-5 that can be used for WFQ.In 4
 623          * port mode port1 has COS0-2 that can be used for WFQ.
 624          */
 625         if (!port) {
 626                 base_upper_bound = PBF_REG_COS0_UPPER_BOUND_P0;
 627                 max_cos = DCBX_E3B0_MAX_NUM_COS_PORT0;
 628         } else {
 629                 base_upper_bound = PBF_REG_COS0_UPPER_BOUND_P1;
 630                 max_cos = DCBX_E3B0_MAX_NUM_COS_PORT1;
 631         }
 632
 633         for (i = 0; i < max_cos; i++)
 634                 REG_WR(bp, base_upper_bound + (i << 2), credit_upper_bound);
 635 }
 636
 637 /******************************************************************************
 638 * Description:
 639 *       Will return the PBF ETS registers to init values.Except
 640 *       credit_upper_bound.
 641 *       That isn't used in this configuration (No WFQ is enabled) and will be
 642 *       configured acording to spec
 643 *.
 644 ******************************************************************************/
 645 static void bnx2x_ets_e3b0_pbf_disabled(const struct link_params *params)
 646 {
 647         struct bnx2x *bp = params->bp;
 648         const u8 port = params->port;
 649         const u32 min_w_val_pbf = ETS_E3B0_PBF_MIN_W_VAL;
 650         u8 i = 0;
 651         u32 base_weight = 0;
 652         u8 max_cos = 0;
 653
 654         /* Mapping between entry  priority to client number 0 - COS0
 655          * client, 2 - COS1, ... 5 - COS5)(HIGHEST) 4bits client num.
 656          * TODO_ETS - Should be done by reset value or init tool
 657          */
 658         if (port)
 659                 /*  0x688 (|011|0 10|00 1|000) */
 660                 REG_WR(bp, PBF_REG_ETS_ARB_PRIORITY_CLIENT_P1 , 0x688);
 661         else
 662                 /*  (10 1|100 |011|0 10|00 1|000) */
 663                 REG_WR(bp, PBF_REG_ETS_ARB_PRIORITY_CLIENT_P0 , 0x2C688);
 664
 665         /* TODO_ETS - Should be done by reset value or init tool */
 666         if (port)
 667                 /* 0x688 (|011|0 10|00 1|000)*/
 668                 REG_WR(bp, PBF_REG_ETS_ARB_CLIENT_CREDIT_MAP_P1, 0x688);
 669         else
 670         /* 0x2C688 (10 1|100 |011|0 10|00 1|000) */
 671         REG_WR(bp, PBF_REG_ETS_ARB_CLIENT_CREDIT_MAP_P0, 0x2C688);
 672
 673         REG_WR(bp, (port) ? PBF_REG_ETS_ARB_NUM_STRICT_ARB_SLOTS_P1 :
 674                    PBF_REG_ETS_ARB_NUM_STRICT_ARB_SLOTS_P0 , 0x100);
 675
 676
 677         REG_WR(bp, (port) ? PBF_REG_ETS_ARB_CLIENT_IS_STRICT_P1 :
 678                    PBF_REG_ETS_ARB_CLIENT_IS_STRICT_P0 , 0);
 679
 680         REG_WR(bp, (port) ? PBF_REG_ETS_ARB_CLIENT_IS_SUBJECT2WFQ_P1 :
 681                    PBF_REG_ETS_ARB_CLIENT_IS_SUBJECT2WFQ_P0 , 0);
 682         /* In 2 port mode port0 has COS0-5 that can be used for WFQ.
 683          * In 4 port mode port1 has COS0-2 that can be used for WFQ.
 684          */
 685         if (!port) {
 686                 base_weight = PBF_REG_COS0_WEIGHT_P0;
 687                 max_cos = DCBX_E3B0_MAX_NUM_COS_PORT0;
 688         } else {
 689                 base_weight = PBF_REG_COS0_WEIGHT_P1;
 690                 max_cos = DCBX_E3B0_MAX_NUM_COS_PORT1;
 691         }
 692
 693         for (i = 0; i < max_cos; i++)
 694                 REG_WR(bp, base_weight + (0x4 * i), 0);
 695
 696         bnx2x_ets_e3b0_set_credit_upper_bound_pbf(params, min_w_val_pbf);
 697 }
 698 /******************************************************************************
 699 * Description:
 700 *       E3B0 disable will return basicly the values to init values.
 701 *.
 702 ******************************************************************************/
 703 static int bnx2x_ets_e3b0_disabled(const struct link_params *params,
 704                                    const struct link_vars *vars)
 705 {
 706         struct bnx2x *bp = params->bp;
 707
 708         if (!CHIP_IS_E3B0(bp)) {
 709                 DP(NETIF_MSG_LINK,
 710                    "bnx2x_ets_e3b0_disabled the chip isn't E3B0\n");
 711                 return -EINVAL;
 712         }
 713
 714         bnx2x_ets_e3b0_nig_disabled(params, vars);
 715
 716         bnx2x_ets_e3b0_pbf_disabled(params);
 717
 718         return 0;
 719 }
 720
 721 /******************************************************************************
 722 * Description:
 723 *       Disable will return basicly the values to init values.
 724 *
 725 ******************************************************************************/
 726 int bnx2x_ets_disabled(struct link_params *params,
 727                       struct link_vars *vars)
 728 {
 729         struct bnx2x *bp = params->bp;
 730         int bnx2x_status = 0;
 731
 732         if ((CHIP_IS_E2(bp)) || (CHIP_IS_E3A0(bp)))
 733                 bnx2x_ets_e2e3a0_disabled(params);
 734         else if (CHIP_IS_E3B0(bp))
 735                 bnx2x_status = bnx2x_ets_e3b0_disabled(params, vars);
 736         else {
 737                 DP(NETIF_MSG_LINK, "bnx2x_ets_disabled - chip not supported\n");
 738                 return -EINVAL;
 739         }
 740
 741         return bnx2x_status;
 742 }
 743
 744 /******************************************************************************
 745 * Description
 746 *       Set the COS mappimg to SP and BW until this point all the COS are not
 747 *       set as SP or BW.
 748 ******************************************************************************/
 749 static int bnx2x_ets_e3b0_cli_map(const struct link_params *params,
 750                                   const struct bnx2x_ets_params *ets_params,
 751                                   const u8 cos_sp_bitmap,
 752                                   const u8 cos_bw_bitmap)
 753 {
 754         struct bnx2x *bp = params->bp;
 755         const u8 port = params->port;
 756         const u8 nig_cli_sp_bitmap = 0x7 | (cos_sp_bitmap << 3);
 757         const u8 pbf_cli_sp_bitmap = cos_sp_bitmap;
 758         const u8 nig_cli_subject2wfq_bitmap = cos_bw_bitmap << 3;
 759         const u8 pbf_cli_subject2wfq_bitmap = cos_bw_bitmap;
 760
 761         REG_WR(bp, (port) ? NIG_REG_P1_TX_ARB_CLIENT_IS_STRICT :
 762                NIG_REG_P0_TX_ARB_CLIENT_IS_STRICT, nig_cli_sp_bitmap);
 763
 764         REG_WR(bp, (port) ? PBF_REG_ETS_ARB_CLIENT_IS_STRICT_P1 :
 765                PBF_REG_ETS_ARB_CLIENT_IS_STRICT_P0 , pbf_cli_sp_bitmap);
 766
 767         REG_WR(bp, (port) ? NIG_REG_P1_TX_ARB_CLIENT_IS_SUBJECT2WFQ :
 768                NIG_REG_P0_TX_ARB_CLIENT_IS_SUBJECT2WFQ,
 769                nig_cli_subject2wfq_bitmap);
 770
 771         REG_WR(bp, (port) ? PBF_REG_ETS_ARB_CLIENT_IS_SUBJECT2WFQ_P1 :
 772                PBF_REG_ETS_ARB_CLIENT_IS_SUBJECT2WFQ_P0,
 773                pbf_cli_subject2wfq_bitmap);
 774
 775         return 0;
 776 }
 777
 778 /******************************************************************************
 779 * Description:
 780 *       This function is needed because NIG ARB_CREDIT_WEIGHT_X are
 781 *       not continues and ARB_CREDIT_WEIGHT_0 + offset is suitable.
 782 ******************************************************************************/
 783 static int bnx2x_ets_e3b0_set_cos_bw(struct bnx2x *bp,
 784                                      const u8 cos_entry,
 785                                      const u32 min_w_val_nig,
 786                                      const u32 min_w_val_pbf,
 787                                      const u16 total_bw,
 788                                      const u8 bw,
 789                                      const u8 port)
 790 {
 791         u32 nig_reg_adress_crd_weight = 0;
 792         u32 pbf_reg_adress_crd_weight = 0;
 793         /* Calculate and set BW for this COS - use 1 instead of 0 for BW */
 794         const u32 cos_bw_nig = ((bw ? bw : 1) * min_w_val_nig) / total_bw;
 795         const u32 cos_bw_pbf = ((bw ? bw : 1) * min_w_val_pbf) / total_bw;
 796
 797         switch (cos_entry) {
 798         case 0:
 799             nig_reg_adress_crd_weight =
 800                  (port) ? NIG_REG_P1_TX_ARB_CREDIT_WEIGHT_0 :
 801                      NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_0;
 802              pbf_reg_adress_crd_weight = (port) ?
 803                  PBF_REG_COS0_WEIGHT_P1 : PBF_REG_COS0_WEIGHT_P0;
 804              break;
 805         case 1:
 806              nig_reg_adress_crd_weight = (port) ?
 807                  NIG_REG_P1_TX_ARB_CREDIT_WEIGHT_1 :
 808                  NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_1;
 809              pbf_reg_adress_crd_weight = (port) ?
 810                  PBF_REG_COS1_WEIGHT_P1 : PBF_REG_COS1_WEIGHT_P0;
 811              break;
 812         case 2:
 813              nig_reg_adress_crd_weight = (port) ?
 814                  NIG_REG_P1_TX_ARB_CREDIT_WEIGHT_2 :
 815                  NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_2;
 816
 817                  pbf_reg_adress_crd_weight = (port) ?
 818                      PBF_REG_COS2_WEIGHT_P1 : PBF_REG_COS2_WEIGHT_P0;
 819              break;
 820         case 3:
 821             if (port)
 822                         return -EINVAL;
 823              nig_reg_adress_crd_weight =
 824                  NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_3;
 825              pbf_reg_adress_crd_weight =
 826                  PBF_REG_COS3_WEIGHT_P0;
 827              break;
 828         case 4:
 829             if (port)
 830                 return -EINVAL;
 831              nig_reg_adress_crd_weight =
 832                  NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_4;
 833              pbf_reg_adress_crd_weight = PBF_REG_COS4_WEIGHT_P0;
 834              break;
 835         case 5:
 836             if (port)
 837                 return -EINVAL;
 838              nig_reg_adress_crd_weight =
 839                  NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_5;
 840              pbf_reg_adress_crd_weight = PBF_REG_COS5_WEIGHT_P0;
 841              break;
 842         }
 843
 844         REG_WR(bp, nig_reg_adress_crd_weight, cos_bw_nig);
 845
 846         REG_WR(bp, pbf_reg_adress_crd_weight, cos_bw_pbf);
 847
 848         return 0;
 849 }
 850 /******************************************************************************
 851 * Description:
 852 *       Calculate the total BW.A value of 0 isn't legal.
 853 *
 854 ******************************************************************************/
 855 static int bnx2x_ets_e3b0_get_total_bw(
 856         const struct link_params *params,
 857         struct bnx2x_ets_params *ets_params,
 858         u16 *total_bw)
 859 {
 860         struct bnx2x *bp = params->bp;
 861         u8 cos_idx = 0;
 862         u8 is_bw_cos_exist = 0;
 863
 864         *total_bw = 0 ;
 865         /* Calculate total BW requested */
 866         for (cos_idx = 0; cos_idx < ets_params->num_of_cos; cos_idx++) {
 867                 if (ets_params->cos[cos_idx].state == bnx2x_cos_state_bw) {
 868                         is_bw_cos_exist = 1;
 869                         if (!ets_params->cos[cos_idx].params.bw_params.bw) {
 870                                 DP(NETIF_MSG_LINK, "bnx2x_ets_E3B0_config BW"
 871                                                    "was set to 0\n");
 872                                 /* This is to prevent a state when ramrods
 873                                  * can't be sent
 874                                  */
 875                                 ets_params->cos[cos_idx].params.bw_params.bw
 876                                          = 1;
 877                         }
 878                         *total_bw +=
 879                                 ets_params->cos[cos_idx].params.bw_params.bw;
 880                 }
 881         }
 882
 883         /* Check total BW is valid */
 884         if ((is_bw_cos_exist == 1) && (*total_bw != 100)) {
 885                 if (*total_bw == 0) {
 886                         DP(NETIF_MSG_LINK,
 887                            "bnx2x_ets_E3B0_config total BW shouldn't be 0\n");
 888                         return -EINVAL;
 889                 }
 890                 DP(NETIF_MSG_LINK,
 891                    "bnx2x_ets_E3B0_config total BW should be 100\n");
 892                 /* We can handle a case whre the BW isn't 100 this can happen
 893                  * if the TC are joined.
 894                  */
 895         }
 896         return 0;
 897 }
 898
 899 /******************************************************************************
 900 * Description:
 901 *       Invalidate all the sp_pri_to_cos.
 902 *
 903 ******************************************************************************/
 904 static void bnx2x_ets_e3b0_sp_pri_to_cos_init(u8 *sp_pri_to_cos)
 905 {
 906         u8 pri = 0;
 907         for (pri = 0; pri < DCBX_MAX_NUM_COS; pri++)
 908                 sp_pri_to_cos[pri] = DCBX_INVALID_COS;
 909 }
 910 /******************************************************************************
 911 * Description:
 912 *       Calculate and set the SP (ARB_PRIORITY_CLIENT) NIG and PBF registers
 913 *       according to sp_pri_to_cos.
 914 *
 915 ******************************************************************************/
 916 static int bnx2x_ets_e3b0_sp_pri_to_cos_set(const struct link_params *params,
 917                                             u8 *sp_pri_to_cos, const u8 pri,
 918                                             const u8 cos_entry)
 919 {
 920         struct bnx2x *bp = params->bp;
 921         const u8 port = params->port;
 922         const u8 max_num_of_cos = (port) ? DCBX_E3B0_MAX_NUM_COS_PORT1 :
 923                 DCBX_E3B0_MAX_NUM_COS_PORT0;
 924
 925         if (sp_pri_to_cos[pri] != DCBX_INVALID_COS) {
 926                 DP(NETIF_MSG_LINK, "bnx2x_ets_e3b0_sp_pri_to_cos_set invalid "
 927                                    "parameter There can't be two COS's with "
 928                                    "the same strict pri\n");
 929                 return -EINVAL;
 930         }
 931
 932         if (pri > max_num_of_cos) {
 933                 DP(NETIF_MSG_LINK, "bnx2x_ets_e3b0_sp_pri_to_cos_set invalid "
 934                    "parameter Illegal strict priority\n");
 935             return -EINVAL;
 936         }
 937
 938         sp_pri_to_cos[pri] = cos_entry;
 939         return 0;
 940
 941 }
 942
 943 /******************************************************************************
 944 * Description:
 945 *       Returns the correct value according to COS and priority in
 946 *       the sp_pri_cli register.
 947 *
 948 ******************************************************************************/
 949 static u64 bnx2x_e3b0_sp_get_pri_cli_reg(const u8 cos, const u8 cos_offset,
 950                                          const u8 pri_set,
 951                                          const u8 pri_offset,
 952                                          const u8 entry_size)
 953 {
 954         u64 pri_cli_nig = 0;
 955         pri_cli_nig = ((u64)(cos + cos_offset)) << (entry_size *
 956                                                     (pri_set + pri_offset));
 957
 958         return pri_cli_nig;
 959 }
 960 /******************************************************************************
 961 * Description:
 962 *       Returns the correct value according to COS and priority in the
 963 *       sp_pri_cli register for NIG.
 964 *
 965 ******************************************************************************/
 966 static u64 bnx2x_e3b0_sp_get_pri_cli_reg_nig(const u8 cos, const u8 pri_set)
 967 {
 968         /* MCP Dbg0 and dbg1 are always with higher strict pri*/
 969         const u8 nig_cos_offset = 3;
 970         const u8 nig_pri_offset = 3;
 971
 972         return bnx2x_e3b0_sp_get_pri_cli_reg(cos, nig_cos_offset, pri_set,
 973                 nig_pri_offset, 4);
 974
 975 }
 976 /******************************************************************************
 977 * Description:
 978 *       Returns the correct value according to COS and priority in the
 979 *       sp_pri_cli register for PBF.
 980 *
 981 ******************************************************************************/
 982 static u64 bnx2x_e3b0_sp_get_pri_cli_reg_pbf(const u8 cos, const u8 pri_set)
 983 {
 984         const u8 pbf_cos_offset = 0;
 985         const u8 pbf_pri_offset = 0;
 986
 987         return bnx2x_e3b0_sp_get_pri_cli_reg(cos, pbf_cos_offset, pri_set,
 988                 pbf_pri_offset, 3);
 989
 990 }
 991
 992 /******************************************************************************
 993 * Description:
 994 *       Calculate and set the SP (ARB_PRIORITY_CLIENT) NIG and PBF registers
 995 *       according to sp_pri_to_cos.(which COS has higher priority)
 996 *
 997 ******************************************************************************/
 998 static int bnx2x_ets_e3b0_sp_set_pri_cli_reg(const struct link_params *params,
 999                                              u8 *sp_pri_to_cos)
1000 {
1001         struct bnx2x *bp = params->bp;
1002         u8 i = 0;
1003         const u8 port = params->port;
1004         /* MCP Dbg0 and dbg1 are always with higher strict pri*/
1005         u64 pri_cli_nig = 0x210;
1006         u32 pri_cli_pbf = 0x0;
1007         u8 pri_set = 0;
1008         u8 pri_bitmask = 0;
1009         const u8 max_num_of_cos = (port) ? DCBX_E3B0_MAX_NUM_COS_PORT1 :
1010                 DCBX_E3B0_MAX_NUM_COS_PORT0;
1011
1012         u8 cos_bit_to_set = (1 << max_num_of_cos) - 1;
1013
1014         /* Set all the strict priority first */
1015         for (i = 0; i < max_num_of_cos; i++) {
1016                 if (sp_pri_to_cos[i] != DCBX_INVALID_COS) {
1017                         if (sp_pri_to_cos[i] >= DCBX_MAX_NUM_COS) {
1018                                 DP(NETIF_MSG_LINK,
1019                                            "bnx2x_ets_e3b0_sp_set_pri_cli_reg "
1020                                            "invalid cos entry\n");
1021                                 return -EINVAL;
1022                         }
1023
1024                         pri_cli_nig |= bnx2x_e3b0_sp_get_pri_cli_reg_nig(
1025                             sp_pri_to_cos[i], pri_set);
1026
1027                         pri_cli_pbf |= bnx2x_e3b0_sp_get_pri_cli_reg_pbf(
1028                             sp_pri_to_cos[i], pri_set);
1029                         pri_bitmask = 1 << sp_pri_to_cos[i];
1030                         /* COS is used remove it from bitmap.*/
1031                         if (!(pri_bitmask & cos_bit_to_set)) {
1032                                 DP(NETIF_MSG_LINK,
1033                                         "bnx2x_ets_e3b0_sp_set_pri_cli_reg "
1034                                         "invalid There can't be two COS's with"
1035                                         " the same strict pri\n");
1036                                 return -EINVAL;
1037                         }
1038                         cos_bit_to_set &= ~pri_bitmask;
1039                         pri_set++;
1040                 }
1041         }
1042
1043         /* Set all the Non strict priority i= COS*/
1044         for (i = 0; i < max_num_of_cos; i++) {
1045                 pri_bitmask = 1 << i;
1046                 /* Check if COS was already used for SP */
1047                 if (pri_bitmask & cos_bit_to_set) {
1048                         /* COS wasn't used for SP */
1049                         pri_cli_nig |= bnx2x_e3b0_sp_get_pri_cli_reg_nig(
1050                             i, pri_set);
1051
1052                         pri_cli_pbf |= bnx2x_e3b0_sp_get_pri_cli_reg_pbf(
1053                             i, pri_set);
1054                         /* COS is used remove it from bitmap.*/
1055                         cos_bit_to_set &= ~pri_bitmask;
1056                         pri_set++;
1057                 }
1058         }
1059
1060         if (pri_set != max_num_of_cos) {
1061                 DP(NETIF_MSG_LINK, "bnx2x_ets_e3b0_sp_set_pri_cli_reg not all "
1062                                    "entries were set\n");
1063                 return -EINVAL;
1064         }
1065
1066         if (port) {
1067                 /* Only 6 usable clients*/
1068                 REG_WR(bp, NIG_REG_P1_TX_ARB_PRIORITY_CLIENT2_LSB,
1069                        (u32)pri_cli_nig);
1070
1071                 REG_WR(bp, PBF_REG_ETS_ARB_PRIORITY_CLIENT_P1 , pri_cli_pbf);
1072         } else {
1073                 /* Only 9 usable clients*/
1074                 const u32 pri_cli_nig_lsb = (u32) (pri_cli_nig);
1075                 const u32 pri_cli_nig_msb = (u32) ((pri_cli_nig >> 32) & 0xF);
1076
1077                 REG_WR(bp, NIG_REG_P0_TX_ARB_PRIORITY_CLIENT2_LSB,
1078                        pri_cli_nig_lsb);
1079                 REG_WR(bp, NIG_REG_P0_TX_ARB_PRIORITY_CLIENT2_MSB,
1080                        pri_cli_nig_msb);
1081
1082                 REG_WR(bp, PBF_REG_ETS_ARB_PRIORITY_CLIENT_P0 , pri_cli_pbf);
1083         }
1084         return 0;
1085 }
1086
1087 /******************************************************************************
1088 * Description:
1089 *       Configure the COS to ETS according to BW and SP settings.
1090 ******************************************************************************/
1091 int bnx2x_ets_e3b0_config(const struct link_params *params,
1092                          const struct link_vars *vars,
1093                          struct bnx2x_ets_params *ets_params)
1094 {
1095         struct bnx2x *bp = params->bp;
1096         int bnx2x_status = 0;
1097         const u8 port = params->port;
1098         u16 total_bw = 0;
1099         const u32 min_w_val_nig = bnx2x_ets_get_min_w_val_nig(vars);
1100         const u32 min_w_val_pbf = ETS_E3B0_PBF_MIN_W_VAL;
1101         u8 cos_bw_bitmap = 0;
1102         u8 cos_sp_bitmap = 0;
1103         u8 sp_pri_to_cos[DCBX_MAX_NUM_COS] = {0};
1104         const u8 max_num_of_cos = (port) ? DCBX_E3B0_MAX_NUM_COS_PORT1 :
1105                 DCBX_E3B0_MAX_NUM_COS_PORT0;
1106         u8 cos_entry = 0;
1107
1108         if (!CHIP_IS_E3B0(bp)) {
1109                 DP(NETIF_MSG_LINK,
1110                    "bnx2x_ets_e3b0_disabled the chip isn't E3B0\n");
1111                 return -EINVAL;
1112         }
1113
1114         if ((ets_params->num_of_cos > max_num_of_cos)) {
1115                 DP(NETIF_MSG_LINK, "bnx2x_ets_E3B0_config the number of COS "
1116                                    "isn't supported\n");
1117                 return -EINVAL;
1118         }
1119
1120         /* Prepare sp strict priority parameters*/
1121         bnx2x_ets_e3b0_sp_pri_to_cos_init(sp_pri_to_cos);
1122
1123         /* Prepare BW parameters*/
1124         bnx2x_status = bnx2x_ets_e3b0_get_total_bw(params, ets_params,
1125                                                    &total_bw);
1126         if (bnx2x_status) {
1127                 DP(NETIF_MSG_LINK,
1128                    "bnx2x_ets_E3B0_config get_total_bw failed\n");
1129                 return -EINVAL;
1130         }
1131
1132         /* Upper bound is set according to current link speed (min_w_val
1133          * should be the same for upper bound and COS credit val).
1134          */
1135         bnx2x_ets_e3b0_set_credit_upper_bound_nig(params, min_w_val_nig);
1136         bnx2x_ets_e3b0_set_credit_upper_bound_pbf(params, min_w_val_pbf);
1137
1138
1139         for (cos_entry = 0; cos_entry < ets_params->num_of_cos; cos_entry++) {
1140                 if (bnx2x_cos_state_bw == ets_params->cos[cos_entry].state) {
1141                         cos_bw_bitmap |= (1 << cos_entry);
1142                         /* The function also sets the BW in HW(not the mappin
1143                          * yet)
1144                          */
1145                         bnx2x_status = bnx2x_ets_e3b0_set_cos_bw(
1146                                 bp, cos_entry, min_w_val_nig, min_w_val_pbf,
1147                                 total_bw,
1148                                 ets_params->cos[cos_entry].params.bw_params.bw,
1149                                  port);
1150                 } else if (bnx2x_cos_state_strict ==
1151                         ets_params->cos[cos_entry].state){
1152                         cos_sp_bitmap |= (1 << cos_entry);
1153
1154                         bnx2x_status = bnx2x_ets_e3b0_sp_pri_to_cos_set(
1155                                 params,
1156                                 sp_pri_to_cos,
1157                                 ets_params->cos[cos_entry].params.sp_params.pri,
1158                                 cos_entry);
1159
1160                 } else {
1161                         DP(NETIF_MSG_LINK,
1162                            "bnx2x_ets_e3b0_config cos state not valid\n");
1163                         return -EINVAL;
1164                 }
1165                 if (bnx2x_status) {
1166                         DP(NETIF_MSG_LINK,
1167                            "bnx2x_ets_e3b0_config set cos bw failed\n");
1168                         return bnx2x_status;
1169                 }
1170         }
1171
1172         /* Set SP register (which COS has higher priority) */
1173         bnx2x_status = bnx2x_ets_e3b0_sp_set_pri_cli_reg(params,
1174                                                          sp_pri_to_cos);
1175
1176         if (bnx2x_status) {
1177                 DP(NETIF_MSG_LINK,
1178                    "bnx2x_ets_E3B0_config set_pri_cli_reg failed\n");
1179                 return bnx2x_status;
1180         }
1181
1182         /* Set client mapping of BW and strict */
1183         bnx2x_status = bnx2x_ets_e3b0_cli_map(params, ets_params,
1184                                               cos_sp_bitmap,
1185                                               cos_bw_bitmap);
1186
1187         if (bnx2x_status) {
1188                 DP(NETIF_MSG_LINK, "bnx2x_ets_E3B0_config SP failed\n");
1189                 return bnx2x_status;
1190         }
1191         return 0;
1192 }
1193 static void bnx2x_ets_bw_limit_common(const struct link_params *params)
1194 {
1195         /* ETS disabled configuration */
1196         struct bnx2x *bp = params->bp;
1197         DP(NETIF_MSG_LINK, "ETS enabled BW limit configuration\n");
1198         /* Defines which entries (clients) are subjected to WFQ arbitration
1199          * COS0 0x8
1200          * COS1 0x10
1201          */
1202         REG_WR(bp, NIG_REG_P0_TX_ARB_CLIENT_IS_SUBJECT2WFQ, 0x18);
1203         /* Mapping between the ARB_CREDIT_WEIGHT registers and actual
1204          * client numbers (WEIGHT_0 does not actually have to represent
1205          * client 0)
1206          *    PRI4    |    PRI3    |    PRI2    |    PRI1    |    PRI0
1207          *  cos1-001     cos0-000     dbg1-100     dbg0-011     MCP-010
1208          */
1209         REG_WR(bp, NIG_REG_P0_TX_ARB_CLIENT_CREDIT_MAP, 0x111A);
1210
1211         REG_WR(bp, NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_0,
1212                ETS_BW_LIMIT_CREDIT_UPPER_BOUND);
1213         REG_WR(bp, NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_1,
1214                ETS_BW_LIMIT_CREDIT_UPPER_BOUND);
1215
1216         /* ETS mode enabled*/
1217         REG_WR(bp, PBF_REG_ETS_ENABLED, 1);
1218
1219         /* Defines the number of consecutive slots for the strict priority */
1220         REG_WR(bp, PBF_REG_NUM_STRICT_ARB_SLOTS, 0);
1221         /* Bitmap of 5bits length. Each bit specifies whether the entry behaves
1222          * as strict.  Bits 0,1,2 - debug and management entries, 3 - COS0
1223          * entry, 4 - COS1 entry.
1224          * COS1 | COS0 | DEBUG21 | DEBUG0 | MGMT
1225          * bit4   bit3    bit2     bit1    bit0
1226          * MCP and debug are strict
1227          */
1228         REG_WR(bp, NIG_REG_P0_TX_ARB_CLIENT_IS_STRICT, 0x7);
1229
1230         /* Upper bound that COS0_WEIGHT can reach in the WFQ arbiter.*/
1231         REG_WR(bp, PBF_REG_COS0_UPPER_BOUND,
1232                ETS_BW_LIMIT_CREDIT_UPPER_BOUND);
1233         REG_WR(bp, PBF_REG_COS1_UPPER_BOUND,
1234                ETS_BW_LIMIT_CREDIT_UPPER_BOUND);
1235 }
1236
1237 void bnx2x_ets_bw_limit(const struct link_params *params, const u32 cos0_bw,
1238                         const u32 cos1_bw)
1239 {
1240         /* ETS disabled configuration*/
1241         struct bnx2x *bp = params->bp;
1242         const u32 total_bw = cos0_bw + cos1_bw;
1243         u32 cos0_credit_weight = 0;
1244         u32 cos1_credit_weight = 0;
1245
1246         DP(NETIF_MSG_LINK, "ETS enabled BW limit configuration\n");
1247
1248         if ((!total_bw) ||
1249             (!cos0_bw) ||
1250             (!cos1_bw)) {
1251                 DP(NETIF_MSG_LINK, "Total BW can't be zero\n");
1252                 return;
1253         }
1254
1255         cos0_credit_weight = (cos0_bw * ETS_BW_LIMIT_CREDIT_WEIGHT)/
1256                 total_bw;
1257         cos1_credit_weight = (cos1_bw * ETS_BW_LIMIT_CREDIT_WEIGHT)/
1258                 total_bw;
1259
1260         bnx2x_ets_bw_limit_common(params);
1261
1262         REG_WR(bp, NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_0, cos0_credit_weight);
1263         REG_WR(bp, NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_1, cos1_credit_weight);
1264
1265         REG_WR(bp, PBF_REG_COS0_WEIGHT, cos0_credit_weight);
1266         REG_WR(bp, PBF_REG_COS1_WEIGHT, cos1_credit_weight);
1267 }
1268
1269 int bnx2x_ets_strict(const struct link_params *params, const u8 strict_cos)
1270 {
1271         /* ETS disabled configuration*/
1272         struct bnx2x *bp = params->bp;
1273         u32 val = 0;
1274
1275         DP(NETIF_MSG_LINK, "ETS enabled strict configuration\n");
1276         /* Bitmap of 5bits length. Each bit specifies whether the entry behaves
1277          * as strict.  Bits 0,1,2 - debug and management entries,
1278          * 3 - COS0 entry, 4 - COS1 entry.
1279          *  COS1 | COS0 | DEBUG21 | DEBUG0 | MGMT
1280          *  bit4   bit3   bit2      bit1     bit0
1281          * MCP and debug are strict
1282          */
1283         REG_WR(bp, NIG_REG_P0_TX_ARB_CLIENT_IS_STRICT, 0x1F);
1284         /* For strict priority entries defines the number of consecutive slots
1285          * for the highest priority.
1286          */
1287         REG_WR(bp, NIG_REG_P0_TX_ARB_NUM_STRICT_ARB_SLOTS, 0x100);
1288         /* ETS mode disable */
1289         REG_WR(bp, PBF_REG_ETS_ENABLED, 0);
1290         /* Defines the number of consecutive slots for the strict priority */
1291         REG_WR(bp, PBF_REG_NUM_STRICT_ARB_SLOTS, 0x100);
1292
1293         /* Defines the number of consecutive slots for the strict priority */
1294         REG_WR(bp, PBF_REG_HIGH_PRIORITY_COS_NUM, strict_cos);
1295
1296         /* Mapping between entry  priority to client number (0,1,2 -debug and
1297          * management clients, 3 - COS0 client, 4 - COS client)(HIGHEST)
1298          * 3bits client num.
1299          *   PRI4    |    PRI3    |    PRI2    |    PRI1    |    PRI0
1300          * dbg0-010     dbg1-001     cos1-100     cos0-011     MCP-000
1301          * dbg0-010     dbg1-001     cos0-011     cos1-100     MCP-000
1302          */
1303         val = (!strict_cos) ? 0x2318 : 0x22E0;
1304         REG_WR(bp, NIG_REG_P0_TX_ARB_PRIORITY_CLIENT, val);
1305
1306         return 0;
1307 }
1308 /******************************************************************/
1309 /*                      PFC section                               */
1310 /******************************************************************/
1311 static void bnx2x_update_pfc_xmac(struct link_params *params,
1312                                   struct link_vars *vars,
1313                                   u8 is_lb)
1314 {
1315         struct bnx2x *bp = params->bp;
1316         u32 xmac_base;
1317         u32 pause_val, pfc0_val, pfc1_val;
1318
1319         /* XMAC base adrr */
1320         xmac_base = (params->port) ? GRCBASE_XMAC1 : GRCBASE_XMAC0;
1321
1322         /* Initialize pause and pfc registers */
1323         pause_val = 0x18000;
1324         pfc0_val = 0xFFFF8000;
1325         pfc1_val = 0x2;
1326
1327         /* No PFC support */
1328         if (!(params->feature_config_flags &
1329               FEATURE_CONFIG_PFC_ENABLED)) {
1330
1331                 /* RX flow control - Process pause frame in receive direction
1332                  */
1333                 if (vars->flow_ctrl & BNX2X_FLOW_CTRL_RX)
1334                         pause_val |= XMAC_PAUSE_CTRL_REG_RX_PAUSE_EN;
1335
1336                 /* TX flow control - Send pause packet when buffer is full */
1337                 if (vars->flow_ctrl & BNX2X_FLOW_CTRL_TX)
1338                         pause_val |= XMAC_PAUSE_CTRL_REG_TX_PAUSE_EN;
1339         } else {/* PFC support */
1340                 pfc1_val |= XMAC_PFC_CTRL_HI_REG_PFC_REFRESH_EN |
1341                         XMAC_PFC_CTRL_HI_REG_PFC_STATS_EN |
1342                         XMAC_PFC_CTRL_HI_REG_RX_PFC_EN |
1343                         XMAC_PFC_CTRL_HI_REG_TX_PFC_EN |
1344                         XMAC_PFC_CTRL_HI_REG_FORCE_PFC_XON;
1345                 /* Write pause and PFC registers */
1346                 REG_WR(bp, xmac_base + XMAC_REG_PAUSE_CTRL, pause_val);
1347                 REG_WR(bp, xmac_base + XMAC_REG_PFC_CTRL, pfc0_val);
1348                 REG_WR(bp, xmac_base + XMAC_REG_PFC_CTRL_HI, pfc1_val);
1349                 pfc1_val &= ~XMAC_PFC_CTRL_HI_REG_FORCE_PFC_XON;
1350
1351         }
1352
1353         /* Write pause and PFC registers */
1354         REG_WR(bp, xmac_base + XMAC_REG_PAUSE_CTRL, pause_val);
1355         REG_WR(bp, xmac_base + XMAC_REG_PFC_CTRL, pfc0_val);
1356         REG_WR(bp, xmac_base + XMAC_REG_PFC_CTRL_HI, pfc1_val);
1357
1358
1359         /* Set MAC address for source TX Pause/PFC frames */
1360         REG_WR(bp, xmac_base + XMAC_REG_CTRL_SA_LO,
1361                ((params->mac_addr[2] << 24) |
1362                 (params->mac_addr[3] << 16) |
1363                 (params->mac_addr[4] << 8) |
1364                 (params->mac_addr[5])));
1365         REG_WR(bp, xmac_base + XMAC_REG_CTRL_SA_HI,
1366                ((params->mac_addr[0] << 8) |
1367                 (params->mac_addr[1])));
1368
1369         udelay(30);
1370 }
1371
1372
1373 static void bnx2x_emac_get_pfc_stat(struct link_params *params,
1374                                     u32 pfc_frames_sent[2],
1375                                     u32 pfc_frames_received[2])
1376 {
1377         /* Read pfc statistic */
1378         struct bnx2x *bp = params->bp;
1379         u32 emac_base = params->port ? GRCBASE_EMAC1 : GRCBASE_EMAC0;
1380         u32 val_xon = 0;
1381         u32 val_xoff = 0;
1382
1383         DP(NETIF_MSG_LINK, "pfc statistic read from EMAC\n");
1384
1385         /* PFC received frames */
1386         val_xoff = REG_RD(bp, emac_base +
1387                                 EMAC_REG_RX_PFC_STATS_XOFF_RCVD);
1388         val_xoff &= EMAC_REG_RX_PFC_STATS_XOFF_RCVD_COUNT;
1389         val_xon = REG_RD(bp, emac_base + EMAC_REG_RX_PFC_STATS_XON_RCVD);
1390         val_xon &= EMAC_REG_RX_PFC_STATS_XON_RCVD_COUNT;
1391
1392         pfc_frames_received[0] = val_xon + val_xoff;
1393
1394         /* PFC received sent */
1395         val_xoff = REG_RD(bp, emac_base +
1396                                 EMAC_REG_RX_PFC_STATS_XOFF_SENT);
1397         val_xoff &= EMAC_REG_RX_PFC_STATS_XOFF_SENT_COUNT;
1398         val_xon = REG_RD(bp, emac_base + EMAC_REG_RX_PFC_STATS_XON_SENT);
1399         val_xon &= EMAC_REG_RX_PFC_STATS_XON_SENT_COUNT;
1400
1401         pfc_frames_sent[0] = val_xon + val_xoff;
1402 }
1403
1404 /* Read pfc statistic*/
1405 void bnx2x_pfc_statistic(struct link_params *params, struct link_vars *vars,
1406                          u32 pfc_frames_sent[2],
1407                          u32 pfc_frames_received[2])
1408 {
1409         /* Read pfc statistic */
1410         struct bnx2x *bp = params->bp;
1411
1412         DP(NETIF_MSG_LINK, "pfc statistic\n");
1413
1414         if (!vars->link_up)
1415                 return;
1416
1417         if (vars->mac_type == MAC_TYPE_EMAC) {
1418                 DP(NETIF_MSG_LINK, "About to read PFC stats from EMAC\n");
1419                 bnx2x_emac_get_pfc_stat(params, pfc_frames_sent,
1420                                         pfc_frames_received);
1421         }
1422 }
1423 /******************************************************************/
1424 /*                      MAC/PBF section                           */
1425 /******************************************************************/
1426 static void bnx2x_set_mdio_clk(struct bnx2x *bp, u32 chip_id, u8 port)
1427 {
1428         u32 mode, emac_base;
1429         /* Set clause 45 mode, slow down the MDIO clock to 2.5MHz
1430          * (a value of 49==0x31) and make sure that the AUTO poll is off
1431          */
1432
1433         if (CHIP_IS_E2(bp))
1434                 emac_base = GRCBASE_EMAC0;
1435         else
1436                 emac_base = (port) ? GRCBASE_EMAC1 : GRCBASE_EMAC0;
1437         mode = REG_RD(bp, emac_base + EMAC_REG_EMAC_MDIO_MODE);
1438         mode &= ~(EMAC_MDIO_MODE_AUTO_POLL |
1439                   EMAC_MDIO_MODE_CLOCK_CNT);
1440         if (USES_WARPCORE(bp))
1441                 mode |= (74L << EMAC_MDIO_MODE_CLOCK_CNT_BITSHIFT);
1442         else
1443                 mode |= (49L << EMAC_MDIO_MODE_CLOCK_CNT_BITSHIFT);
1444
1445         mode |= (EMAC_MDIO_MODE_CLAUSE_45);
1446         REG_WR(bp, emac_base + EMAC_REG_EMAC_MDIO_MODE, mode);
1447
1448         udelay(40);
1449 }
1450 static u8 bnx2x_is_4_port_mode(struct bnx2x *bp)
1451 {
1452         u32 port4mode_ovwr_val;
1453         /* Check 4-port override enabled */
1454         port4mode_ovwr_val = REG_RD(bp, MISC_REG_PORT4MODE_EN_OVWR);
1455         if (port4mode_ovwr_val & (1<<0)) {
1456                 /* Return 4-port mode override value */
1457                 return ((port4mode_ovwr_val & (1<<1)) == (1<<1));
1458         }
1459         /* Return 4-port mode from input pin */
1460         return (u8)REG_RD(bp, MISC_REG_PORT4MODE_EN);
1461 }
1462
1463 static void bnx2x_emac_init(struct link_params *params,
1464                             struct link_vars *vars)
1465 {
1466         /* reset and unreset the emac core */
1467         struct bnx2x *bp = params->bp;
1468         u8 port = params->port;
1469         u32 emac_base = port ? GRCBASE_EMAC1 : GRCBASE_EMAC0;
1470         u32 val;
1471         u16 timeout;
1472
1473         REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR,
1474                (MISC_REGISTERS_RESET_REG_2_RST_EMAC0_HARD_CORE << port));
1475         udelay(5);
1476         REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_SET,
1477                (MISC_REGISTERS_RESET_REG_2_RST_EMAC0_HARD_CORE << port));
1478
1479         /* init emac - use read-modify-write */
1480         /* self clear reset */
1481         val = REG_RD(bp, emac_base + EMAC_REG_EMAC_MODE);
1482         EMAC_WR(bp, EMAC_REG_EMAC_MODE, (val | EMAC_MODE_RESET));
1483
1484         timeout = 200;
1485         do {
1486                 val = REG_RD(bp, emac_base + EMAC_REG_EMAC_MODE);
1487                 DP(NETIF_MSG_LINK, "EMAC reset reg is %u\n", val);
1488                 if (!timeout) {
1489                         DP(NETIF_MSG_LINK, "EMAC timeout!\n");
1490                         return;
1491                 }
1492                 timeout--;
1493         } while (val & EMAC_MODE_RESET);
1494         bnx2x_set_mdio_clk(bp, params->chip_id, port);
1495         /* Set mac address */
1496         val = ((params->mac_addr[0] << 8) |
1497                 params->mac_addr[1]);
1498         EMAC_WR(bp, EMAC_REG_EMAC_MAC_MATCH, val);
1499
1500         val = ((params->mac_addr[2] << 24) |
1501                (params->mac_addr[3] << 16) |
1502                (params->mac_addr[4] << 8) |
1503                 params->mac_addr[5]);
1504         EMAC_WR(bp, EMAC_REG_EMAC_MAC_MATCH + 4, val);
1505 }
1506
1507 static void bnx2x_set_xumac_nig(struct link_params *params,
1508                                 u16 tx_pause_en,
1509                                 u8 enable)
1510 {
1511         struct bnx2x *bp = params->bp;
1512
1513         REG_WR(bp, params->port ? NIG_REG_P1_MAC_IN_EN : NIG_REG_P0_MAC_IN_EN,
1514                enable);
1515         REG_WR(bp, params->port ? NIG_REG_P1_MAC_OUT_EN : NIG_REG_P0_MAC_OUT_EN,
1516                enable);
1517         REG_WR(bp, params->port ? NIG_REG_P1_MAC_PAUSE_OUT_EN :
1518                NIG_REG_P0_MAC_PAUSE_OUT_EN, tx_pause_en);
1519 }
1520
1521 static void bnx2x_umac_disable(struct link_params *params)
1522 {
1523         u32 umac_base = params->port ? GRCBASE_UMAC1 : GRCBASE_UMAC0;
1524         struct bnx2x *bp = params->bp;
1525         if (!(REG_RD(bp, MISC_REG_RESET_REG_2) &
1526                    (MISC_REGISTERS_RESET_REG_2_UMAC0 << params->port)))
1527                 return;
1528
1529         /* Disable RX and TX */
1530         REG_WR(bp, umac_base + UMAC_REG_COMMAND_CONFIG, 0);
1531 }
1532
1533 static void bnx2x_umac_enable(struct link_params *params,
1534                             struct link_vars *vars, u8 lb)
1535 {
1536         u32 val;
1537         u32 umac_base = params->port ? GRCBASE_UMAC1 : GRCBASE_UMAC0;
1538         struct bnx2x *bp = params->bp;
1539         /* Reset UMAC */
1540         REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR,
1541                (MISC_REGISTERS_RESET_REG_2_UMAC0 << params->port));
1542         usleep_range(1000, 1000);
1543
1544         REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_SET,
1545                (MISC_REGISTERS_RESET_REG_2_UMAC0 << params->port));
1546
1547         DP(NETIF_MSG_LINK, "enabling UMAC\n");
1548
1549         /* This register opens the gate for the UMAC despite its name */
1550         REG_WR(bp, NIG_REG_EGRESS_EMAC0_PORT + params->port*4, 1);
1551
1552         val = UMAC_COMMAND_CONFIG_REG_PROMIS_EN |
1553                 UMAC_COMMAND_CONFIG_REG_PAD_EN |
1554                 UMAC_COMMAND_CONFIG_REG_SW_RESET |
1555                 UMAC_COMMAND_CONFIG_REG_NO_LGTH_CHECK;
1556         switch (vars->line_speed) {
1557         case SPEED_10:
1558                 val |= (0<<2);
1559                 break;
1560         case SPEED_100:
1561                 val |= (1<<2);
1562                 break;
1563         case SPEED_1000:
1564                 val |= (2<<2);
1565                 break;
1566         case SPEED_2500:
1567                 val |= (3<<2);
1568                 break;
1569         default:
1570                 DP(NETIF_MSG_LINK, "Invalid speed for UMAC %d\n",
1571                                vars->line_speed);
1572                 break;
1573         }
1574         if (!(vars->flow_ctrl & BNX2X_FLOW_CTRL_TX))
1575                 val |= UMAC_COMMAND_CONFIG_REG_IGNORE_TX_PAUSE;
1576
1577         if (!(vars->flow_ctrl & BNX2X_FLOW_CTRL_RX))
1578                 val |= UMAC_COMMAND_CONFIG_REG_PAUSE_IGNORE;
1579
1580         if (vars->duplex == DUPLEX_HALF)
1581                 val |= UMAC_COMMAND_CONFIG_REG_HD_ENA;
1582
1583         REG_WR(bp, umac_base + UMAC_REG_COMMAND_CONFIG, val);
1584         udelay(50);
1585
1586         /* Set MAC address for source TX Pause/PFC frames (under SW reset) */
1587         REG_WR(bp, umac_base + UMAC_REG_MAC_ADDR0,
1588                ((params->mac_addr[2] << 24) |
1589                 (params->mac_addr[3] << 16) |
1590                 (params->mac_addr[4] << 8) |
1591                 (params->mac_addr[5])));
1592         REG_WR(bp, umac_base + UMAC_REG_MAC_ADDR1,
1593                ((params->mac_addr[0] << 8) |
1594                 (params->mac_addr[1])));
1595
1596         /* Enable RX and TX */
1597         val &= ~UMAC_COMMAND_CONFIG_REG_PAD_EN;
1598         val |= UMAC_COMMAND_CONFIG_REG_TX_ENA |
1599                 UMAC_COMMAND_CONFIG_REG_RX_ENA;
1600         REG_WR(bp, umac_base + UMAC_REG_COMMAND_CONFIG, val);
1601         udelay(50);
1602
1603         /* Remove SW Reset */
1604         val &= ~UMAC_COMMAND_CONFIG_REG_SW_RESET;
1605
1606         /* Check loopback mode */
1607         if (lb)
1608                 val |= UMAC_COMMAND_CONFIG_REG_LOOP_ENA;
1609         REG_WR(bp, umac_base + UMAC_REG_COMMAND_CONFIG, val);
1610
1611         /* Maximum Frame Length (RW). Defines a 14-Bit maximum frame
1612          * length used by the MAC receive logic to check frames.
1613          */
1614         REG_WR(bp, umac_base + UMAC_REG_MAXFR, 0x2710);
1615         bnx2x_set_xumac_nig(params,
1616                             ((vars->flow_ctrl & BNX2X_FLOW_CTRL_TX) != 0), 1);
1617         vars->mac_type = MAC_TYPE_UMAC;
1618
1619 }
1620
1621 /* Define the XMAC mode */
1622 static void bnx2x_xmac_init(struct link_params *params, u32 max_speed)
1623 {
1624         struct bnx2x *bp = params->bp;
1625         u32 is_port4mode = bnx2x_is_4_port_mode(bp);
1626
1627         /* In 4-port mode, need to set the mode only once, so if XMAC is
1628          * already out of reset, it means the mode has already been set,
1629          * and it must not* reset the XMAC again, since it controls both
1630          * ports of the path
1631          */
1632
1633         if ((CHIP_NUM(bp) == CHIP_NUM_57840) &&
1634             (REG_RD(bp, MISC_REG_RESET_REG_2) &
1635              MISC_REGISTERS_RESET_REG_2_XMAC)) {
1636                 DP(NETIF_MSG_LINK,
1637                    "XMAC already out of reset in 4-port mode\n");
1638                 return;
1639         }
1640
1641         /* Hard reset */
1642         REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR,
1643                MISC_REGISTERS_RESET_REG_2_XMAC);
1644         usleep_range(1000, 1000);
1645
1646         REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_SET,
1647                MISC_REGISTERS_RESET_REG_2_XMAC);
1648         if (is_port4mode) {
1649                 DP(NETIF_MSG_LINK, "Init XMAC to 2 ports x 10G per path\n");
1650
1651                 /* Set the number of ports on the system side to up to 2 */
1652                 REG_WR(bp, MISC_REG_XMAC_CORE_PORT_MODE, 1);
1653
1654                 /* Set the number of ports on the Warp Core to 10G */
1655                 REG_WR(bp, MISC_REG_XMAC_PHY_PORT_MODE, 3);
1656         } else {
1657                 /* Set the number of ports on the system side to 1 */
1658                 REG_WR(bp, MISC_REG_XMAC_CORE_PORT_MODE, 0);
1659                 if (max_speed == SPEED_10000) {
1660                         DP(NETIF_MSG_LINK,
1661                            "Init XMAC to 10G x 1 port per path\n");
1662                         /* Set the number of ports on the Warp Core to 10G */
1663                         REG_WR(bp, MISC_REG_XMAC_PHY_PORT_MODE, 3);
1664                 } else {
1665                         DP(NETIF_MSG_LINK,
1666                            "Init XMAC to 20G x 2 ports per path\n");
1667                         /* Set the number of ports on the Warp Core to 20G */
1668                         REG_WR(bp, MISC_REG_XMAC_PHY_PORT_MODE, 1);
1669                 }
1670         }
1671         /* Soft reset */
1672         REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR,
1673                MISC_REGISTERS_RESET_REG_2_XMAC_SOFT);
1674         usleep_range(1000, 1000);
1675
1676         REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_SET,
1677                MISC_REGISTERS_RESET_REG_2_XMAC_SOFT);
1678
1679 }
1680
1681 static void bnx2x_xmac_disable(struct link_params *params)
1682 {
1683         u8 port = params->port;
1684         struct bnx2x *bp = params->bp;
1685         u32 pfc_ctrl, xmac_base = (port) ? GRCBASE_XMAC1 : GRCBASE_XMAC0;
1686
1687         if (REG_RD(bp, MISC_REG_RESET_REG_2) &
1688             MISC_REGISTERS_RESET_REG_2_XMAC) {
1689                 /* Send an indication to change the state in the NIG back to XON
1690                  * Clearing this bit enables the next set of this bit to get
1691                  * rising edge
1692                  */
1693                 pfc_ctrl = REG_RD(bp, xmac_base + XMAC_REG_PFC_CTRL_HI);
1694                 REG_WR(bp, xmac_base + XMAC_REG_PFC_CTRL_HI,
1695                        (pfc_ctrl & ~(1<<1)));
1696                 REG_WR(bp, xmac_base + XMAC_REG_PFC_CTRL_HI,
1697                        (pfc_ctrl | (1<<1)));
1698                 DP(NETIF_MSG_LINK, "Disable XMAC on port %x\n", port);
1699                 REG_WR(bp, xmac_base + XMAC_REG_CTRL, 0);
1700         }
1701 }
1702
1703 static int bnx2x_xmac_enable(struct link_params *params,
1704                              struct link_vars *vars, u8 lb)
1705 {
1706         u32 val, xmac_base;
1707         struct bnx2x *bp = params->bp;
1708         DP(NETIF_MSG_LINK, "enabling XMAC\n");
1709
1710         xmac_base = (params->port) ? GRCBASE_XMAC1 : GRCBASE_XMAC0;
1711
1712         bnx2x_xmac_init(params, vars->line_speed);
1713
1714         /* This register determines on which events the MAC will assert
1715          * error on the i/f to the NIG along w/ EOP.
1716          */
1717
1718         /* This register tells the NIG whether to send traffic to UMAC
1719          * or XMAC
1720          */
1721         REG_WR(bp, NIG_REG_EGRESS_EMAC0_PORT + params->port*4, 0);
1722
1723         /* Set Max packet size */
1724         REG_WR(bp, xmac_base + XMAC_REG_RX_MAX_SIZE, 0x2710);
1725
1726         /* CRC append for Tx packets */
1727         REG_WR(bp, xmac_base + XMAC_REG_TX_CTRL, 0xC800);
1728
1729         /* update PFC */
1730         bnx2x_update_pfc_xmac(params, vars, 0);
1731
1732         /* Enable TX and RX */
1733         val = XMAC_CTRL_REG_TX_EN | XMAC_CTRL_REG_RX_EN;
1734
1735         /* Check loopback mode */
1736         if (lb)
1737                 val |= XMAC_CTRL_REG_LINE_LOCAL_LPBK;
1738         REG_WR(bp, xmac_base + XMAC_REG_CTRL, val);
1739         bnx2x_set_xumac_nig(params,
1740                             ((vars->flow_ctrl & BNX2X_FLOW_CTRL_TX) != 0), 1);
1741
1742         vars->mac_type = MAC_TYPE_XMAC;
1743
1744         return 0;
1745 }
1746
1747 static int bnx2x_emac_enable(struct link_params *params,
1748                              struct link_vars *vars, u8 lb)
1749 {
1750         struct bnx2x *bp = params->bp;
1751         u8 port = params->port;
1752         u32 emac_base = port ? GRCBASE_EMAC1 : GRCBASE_EMAC0;
1753         u32 val;
1754
1755         DP(NETIF_MSG_LINK, "enabling EMAC\n");
1756
1757         /* Disable BMAC */
1758         REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR,
1759                (MISC_REGISTERS_RESET_REG_2_RST_BMAC0 << port));
1760
1761         /* enable emac and not bmac */
1762         REG_WR(bp, NIG_REG_EGRESS_EMAC0_PORT + port*4, 1);
1763
1764         /* ASIC */
1765         if (vars->phy_flags & PHY_XGXS_FLAG) {
1766                 u32 ser_lane = ((params->lane_config &
1767                                  PORT_HW_CFG_LANE_SWAP_CFG_MASTER_MASK) >>
1768                                 PORT_HW_CFG_LANE_SWAP_CFG_MASTER_SHIFT);
1769
1770                 DP(NETIF_MSG_LINK, "XGXS\n");
1771                 /* select the master lanes (out of 0-3) */
1772                 REG_WR(bp, NIG_REG_XGXS_LANE_SEL_P0 + port*4, ser_lane);
1773                 /* select XGXS */
1774                 REG_WR(bp, NIG_REG_XGXS_SERDES0_MODE_SEL + port*4, 1);
1775
1776         } else { /* SerDes */
1777                 DP(NETIF_MSG_LINK, "SerDes\n");
1778                 /* select SerDes */
1779                 REG_WR(bp, NIG_REG_XGXS_SERDES0_MODE_SEL + port*4, 0);
1780         }
1781
1782         bnx2x_bits_en(bp, emac_base + EMAC_REG_EMAC_RX_MODE,
1783                       EMAC_RX_MODE_RESET);
1784         bnx2x_bits_en(bp, emac_base + EMAC_REG_EMAC_TX_MODE,
1785                       EMAC_TX_MODE_RESET);
1786
1787         if (CHIP_REV_IS_SLOW(bp)) {
1788                 /* config GMII mode */
1789                 val = REG_RD(bp, emac_base + EMAC_REG_EMAC_MODE);
1790                 EMAC_WR(bp, EMAC_REG_EMAC_MODE, (val | EMAC_MODE_PORT_GMII));
1791         } else { /* ASIC */
1792                 /* pause enable/disable */
1793                 bnx2x_bits_dis(bp, emac_base + EMAC_REG_EMAC_RX_MODE,
1794                                EMAC_RX_MODE_FLOW_EN);
1795
1796                 bnx2x_bits_dis(bp,  emac_base + EMAC_REG_EMAC_TX_MODE,
1797                                (EMAC_TX_MODE_EXT_PAUSE_EN |
1798                                 EMAC_TX_MODE_FLOW_EN));
1799                 if (!(params->feature_config_flags &
1800                       FEATURE_CONFIG_PFC_ENABLED)) {
1801                         if (vars->flow_ctrl & BNX2X_FLOW_CTRL_RX)
1802                                 bnx2x_bits_en(bp, emac_base +
1803                                               EMAC_REG_EMAC_RX_MODE,
1804                                               EMAC_RX_MODE_FLOW_EN);
1805
1806                         if (vars->flow_ctrl & BNX2X_FLOW_CTRL_TX)
1807                                 bnx2x_bits_en(bp, emac_base +
1808                                               EMAC_REG_EMAC_TX_MODE,
1809                                               (EMAC_TX_MODE_EXT_PAUSE_EN |
1810                                                EMAC_TX_MODE_FLOW_EN));
1811                 } else
1812                         bnx2x_bits_en(bp, emac_base + EMAC_REG_EMAC_TX_MODE,
1813                                       EMAC_TX_MODE_FLOW_EN);
1814         }
1815
1816         /* KEEP_VLAN_TAG, promiscuous */
1817         val = REG_RD(bp, emac_base + EMAC_REG_EMAC_RX_MODE);
1818         val |= EMAC_RX_MODE_KEEP_VLAN_TAG | EMAC_RX_MODE_PROMISCUOUS;
1819
1820         /* Setting this bit causes MAC control frames (except for pause
1821          * frames) to be passed on for processing. This setting has no
1822          * affect on the operation of the pause frames. This bit effects
1823          * all packets regardless of RX Parser packet sorting logic.
1824          * Turn the PFC off to make sure we are in Xon state before
1825          * enabling it.
1826          */
1827         EMAC_WR(bp, EMAC_REG_RX_PFC_MODE, 0);
1828         if (params->feature_config_flags & FEATURE_CONFIG_PFC_ENABLED) {
1829                 DP(NETIF_MSG_LINK, "PFC is enabled\n");
1830                 /* Enable PFC again */
1831                 EMAC_WR(bp, EMAC_REG_RX_PFC_MODE,
1832                         EMAC_REG_RX_PFC_MODE_RX_EN |
1833                         EMAC_REG_RX_PFC_MODE_TX_EN |
1834                         EMAC_REG_RX_PFC_MODE_PRIORITIES);
1835
1836                 EMAC_WR(bp, EMAC_REG_RX_PFC_PARAM,
1837                         ((0x0101 <<
1838                           EMAC_REG_RX_PFC_PARAM_OPCODE_BITSHIFT) |
1839                          (0x00ff <<
1840                           EMAC_REG_RX_PFC_PARAM_PRIORITY_EN_BITSHIFT)));
1841                 val |= EMAC_RX_MODE_KEEP_MAC_CONTROL;
1842         }
1843         EMAC_WR(bp, EMAC_REG_EMAC_RX_MODE, val);
1844
1845         /* Set Loopback */
1846         val = REG_RD(bp, emac_base + EMAC_REG_EMAC_MODE);
1847         if (lb)
1848                 val |= 0x810;
1849         else
1850                 val &= ~0x810;
1851         EMAC_WR(bp, EMAC_REG_EMAC_MODE, val);
1852
1853         /* enable emac */
1854         REG_WR(bp, NIG_REG_NIG_EMAC0_EN + port*4, 1);
1855
1856         /* enable emac for jumbo packets */
1857         EMAC_WR(bp, EMAC_REG_EMAC_RX_MTU_SIZE,
1858                 (EMAC_RX_MTU_SIZE_JUMBO_ENA |
1859                  (ETH_MAX_JUMBO_PACKET_SIZE + ETH_OVREHEAD)));
1860
1861         /* strip CRC */
1862         REG_WR(bp, NIG_REG_NIG_INGRESS_EMAC0_NO_CRC + port*4, 0x1);
1863
1864         /* disable the NIG in/out to the bmac */
1865         REG_WR(bp, NIG_REG_BMAC0_IN_EN + port*4, 0x0);
1866         REG_WR(bp, NIG_REG_BMAC0_PAUSE_OUT_EN + port*4, 0x0);
1867         REG_WR(bp, NIG_REG_BMAC0_OUT_EN + port*4, 0x0);
1868
1869         /* enable the NIG in/out to the emac */
1870         REG_WR(bp, NIG_REG_EMAC0_IN_EN + port*4, 0x1);
1871         val = 0;
1872         if ((params->feature_config_flags &
1873               FEATURE_CONFIG_PFC_ENABLED) ||
1874             (vars->flow_ctrl & BNX2X_FLOW_CTRL_TX))
1875                 val = 1;
1876
1877         REG_WR(bp, NIG_REG_EMAC0_PAUSE_OUT_EN + port*4, val);
1878         REG_WR(bp, NIG_REG_EGRESS_EMAC0_OUT_EN + port*4, 0x1);
1879
1880         REG_WR(bp, NIG_REG_BMAC0_REGS_OUT_EN + port*4, 0x0);
1881
1882         vars->mac_type = MAC_TYPE_EMAC;
1883         return 0;
1884 }
1885
1886 static void bnx2x_update_pfc_bmac1(struct link_params *params,
1887                                    struct link_vars *vars)
1888 {
1889         u32 wb_data[2];
1890         struct bnx2x *bp = params->bp;
1891         u32 bmac_addr =  params->port ? NIG_REG_INGRESS_BMAC1_MEM :
1892                 NIG_REG_INGRESS_BMAC0_MEM;
1893
1894         u32 val = 0x14;
1895         if ((!(params->feature_config_flags &
1896               FEATURE_CONFIG_PFC_ENABLED)) &&
1897                 (vars->flow_ctrl & BNX2X_FLOW_CTRL_RX))
1898                 /* Enable BigMAC to react on received Pause packets */
1899                 val |= (1<<5);
1900         wb_data[0] = val;
1901         wb_data[1] = 0;
1902         REG_WR_DMAE(bp, bmac_addr + BIGMAC_REGISTER_RX_CONTROL, wb_data, 2);
1903
1904         /* tx control */
1905         val = 0xc0;
1906         if (!(params->feature_config_flags &
1907               FEATURE_CONFIG_PFC_ENABLED) &&
1908                 (vars->flow_ctrl & BNX2X_FLOW_CTRL_TX))
1909                 val |= 0x800000;
1910         wb_data[0] = val;
1911         wb_data[1] = 0;
1912         REG_WR_DMAE(bp, bmac_addr + BIGMAC_REGISTER_TX_CONTROL, wb_data, 2);
1913 }
1914
1915 static void bnx2x_update_pfc_bmac2(struct link_params *params,
1916                                    struct link_vars *vars,
1917                                    u8 is_lb)
1918 {
1919         /* Set rx control: Strip CRC and enable BigMAC to relay
1920          * control packets to the system as well
1921          */
1922         u32 wb_data[2];
1923         struct bnx2x *bp = params->bp;
1924         u32 bmac_addr = params->port ? NIG_REG_INGRESS_BMAC1_MEM :
1925                 NIG_REG_INGRESS_BMAC0_MEM;
1926         u32 val = 0x14;
1927
1928         if ((!(params->feature_config_flags &
1929               FEATURE_CONFIG_PFC_ENABLED)) &&
1930                 (vars->flow_ctrl & BNX2X_FLOW_CTRL_RX))
1931                 /* Enable BigMAC to react on received Pause packets */
1932                 val |= (1<<5);
1933         wb_data[0] = val;
1934         wb_data[1] = 0;
1935         REG_WR_DMAE(bp, bmac_addr + BIGMAC2_REGISTER_RX_CONTROL, wb_data, 2);
1936         udelay(30);
1937
1938         /* Tx control */
1939         val = 0xc0;
1940         if (!(params->feature_config_flags &
1941                                 FEATURE_CONFIG_PFC_ENABLED) &&
1942             (vars->flow_ctrl & BNX2X_FLOW_CTRL_TX))
1943                 val |= 0x800000;
1944         wb_data[0] = val;
1945         wb_data[1] = 0;
1946         REG_WR_DMAE(bp, bmac_addr + BIGMAC2_REGISTER_TX_CONTROL, wb_data, 2);
1947
1948         if (params->feature_config_flags & FEATURE_CONFIG_PFC_ENABLED) {
1949                 DP(NETIF_MSG_LINK, "PFC is enabled\n");
1950                 /* Enable PFC RX & TX & STATS and set 8 COS  */
1951                 wb_data[0] = 0x0;
1952                 wb_data[0] |= (1<<0);  /* RX */
1953                 wb_data[0] |= (1<<1);  /* TX */
1954                 wb_data[0] |= (1<<2);  /* Force initial Xon */
1955                 wb_data[0] |= (1<<3);  /* 8 cos */
1956                 wb_data[0] |= (1<<5);  /* STATS */
1957                 wb_data[1] = 0;
1958                 REG_WR_DMAE(bp, bmac_addr + BIGMAC2_REGISTER_PFC_CONTROL,
1959                             wb_data, 2);
1960                 /* Clear the force Xon */
1961                 wb_data[0] &= ~(1<<2);
1962         } else {
1963                 DP(NETIF_MSG_LINK, "PFC is disabled\n");
1964                 /* disable PFC RX & TX & STATS and set 8 COS */
1965                 wb_data[0] = 0x8;
1966                 wb_data[1] = 0;
1967         }
1968
1969         REG_WR_DMAE(bp, bmac_addr + BIGMAC2_REGISTER_PFC_CONTROL, wb_data, 2);
1970
1971         /* Set Time (based unit is 512 bit time) between automatic
1972          * re-sending of PP packets amd enable automatic re-send of
1973          * Per-Priroity Packet as long as pp_gen is asserted and
1974          * pp_disable is low.
1975          */
1976         val = 0x8000;
1977         if (params->feature_config_flags & FEATURE_CONFIG_PFC_ENABLED)
1978                 val |= (1<<16); /* enable automatic re-send */
1979
1980         wb_data[0] = val;
1981         wb_data[1] = 0;
1982         REG_WR_DMAE(bp, bmac_addr + BIGMAC2_REGISTER_TX_PAUSE_CONTROL,
1983                     wb_data, 2);
1984
1985         /* mac control */
1986         val = 0x3; /* Enable RX and TX */
1987         if (is_lb) {
1988                 val |= 0x4; /* Local loopback */
1989                 DP(NETIF_MSG_LINK, "enable bmac loopback\n");
1990         }
1991         /* When PFC enabled, Pass pause frames towards the NIG. */
1992         if (params->feature_config_flags & FEATURE_CONFIG_PFC_ENABLED)
1993                 val |= ((1<<6)|(1<<5));
1994
1995         wb_data[0] = val;
1996         wb_data[1] = 0;
1997         REG_WR_DMAE(bp, bmac_addr + BIGMAC2_REGISTER_BMAC_CONTROL, wb_data, 2);
1998 }
1999
2000 /* PFC BRB internal port configuration params */
2001 struct bnx2x_pfc_brb_threshold_val {
2002         u32 pause_xoff;
2003         u32 pause_xon;
2004         u32 full_xoff;
2005         u32 full_xon;
2006 };
2007
2008 struct bnx2x_pfc_brb_e3b0_val {
2009         u32 per_class_guaranty_mode;
2010         u32 lb_guarantied_hyst;
2011         u32 full_lb_xoff_th;
2012         u32 full_lb_xon_threshold;
2013         u32 lb_guarantied;
2014         u32 mac_0_class_t_guarantied;
2015         u32 mac_0_class_t_guarantied_hyst;
2016         u32 mac_1_class_t_guarantied;
2017         u32 mac_1_class_t_guarantied_hyst;
2018 };
2019
2020 struct bnx2x_pfc_brb_th_val {
2021         struct bnx2x_pfc_brb_threshold_val pauseable_th;
2022         struct bnx2x_pfc_brb_threshold_val non_pauseable_th;
2023         struct bnx2x_pfc_brb_threshold_val default_class0;
2024         struct bnx2x_pfc_brb_threshold_val default_class1;
2025
2026 };
2027 static int bnx2x_pfc_brb_get_config_params(
2028                                 struct link_params *params,
2029                                 struct bnx2x_pfc_brb_th_val *config_val)
2030 {
2031         struct bnx2x *bp = params->bp;
2032         DP(NETIF_MSG_LINK, "Setting PFC BRB configuration\n");
2033
2034         config_val->default_class1.pause_xoff = 0;
2035         config_val->default_class1.pause_xon = 0;
2036         config_val->default_class1.full_xoff = 0;
2037         config_val->default_class1.full_xon = 0;
2038
2039         if (CHIP_IS_E2(bp)) {
2040                 /* Class0 defaults */
2041                 config_val->default_class0.pause_xoff =
2042                         DEFAULT0_E2_BRB_MAC_PAUSE_XOFF_THR;
2043                 config_val->default_class0.pause_xon =
2044                         DEFAULT0_E2_BRB_MAC_PAUSE_XON_THR;
2045                 config_val->default_class0.full_xoff =
2046                         DEFAULT0_E2_BRB_MAC_FULL_XOFF_THR;
2047                 config_val->default_class0.full_xon =
2048                         DEFAULT0_E2_BRB_MAC_FULL_XON_THR;
2049                 /* Pause able*/
2050                 config_val->pauseable_th.pause_xoff =
2051                         PFC_E2_BRB_MAC_PAUSE_XOFF_THR_PAUSE;
2052                 config_val->pauseable_th.pause_xon =
2053                         PFC_E2_BRB_MAC_PAUSE_XON_THR_PAUSE;
2054                 config_val->pauseable_th.full_xoff =
2055                         PFC_E2_BRB_MAC_FULL_XOFF_THR_PAUSE;
2056                 config_val->pauseable_th.full_xon =
2057                         PFC_E2_BRB_MAC_FULL_XON_THR_PAUSE;
2058                 /* non pause able*/
2059                 config_val->non_pauseable_th.pause_xoff =
2060                         PFC_E2_BRB_MAC_PAUSE_XOFF_THR_NON_PAUSE;
2061                 config_val->non_pauseable_th.pause_xon =
2062                         PFC_E2_BRB_MAC_PAUSE_XON_THR_NON_PAUSE;
2063                 config_val->non_pauseable_th.full_xoff =
2064                         PFC_E2_BRB_MAC_FULL_XOFF_THR_NON_PAUSE;
2065                 config_val->non_pauseable_th.full_xon =
2066                         PFC_E2_BRB_MAC_FULL_XON_THR_NON_PAUSE;
2067         } else if (CHIP_IS_E3A0(bp)) {
2068                 /* Class0 defaults */
2069                 config_val->default_class0.pause_xoff =
2070                         DEFAULT0_E3A0_BRB_MAC_PAUSE_XOFF_THR;
2071                 config_val->default_class0.pause_xon =
2072                         DEFAULT0_E3A0_BRB_MAC_PAUSE_XON_THR;
2073                 config_val->default_class0.full_xoff =
2074                         DEFAULT0_E3A0_BRB_MAC_FULL_XOFF_THR;
2075                 config_val->default_class0.full_xon =
2076                         DEFAULT0_E3A0_BRB_MAC_FULL_XON_THR;
2077                 /* Pause able */
2078                 config_val->pauseable_th.pause_xoff =
2079                         PFC_E3A0_BRB_MAC_PAUSE_XOFF_THR_PAUSE;
2080                 config_val->pauseable_th.pause_xon =
2081                         PFC_E3A0_BRB_MAC_PAUSE_XON_THR_PAUSE;
2082                 config_val->pauseable_th.full_xoff =
2083                         PFC_E3A0_BRB_MAC_FULL_XOFF_THR_PAUSE;
2084                 config_val->pauseable_th.full_xon =
2085                         PFC_E3A0_BRB_MAC_FULL_XON_THR_PAUSE;
2086                 /* non pause able*/
2087                 config_val->non_pauseable_th.pause_xoff =
2088                         PFC_E3A0_BRB_MAC_PAUSE_XOFF_THR_NON_PAUSE;
2089                 config_val->non_pauseable_th.pause_xon =
2090                         PFC_E3A0_BRB_MAC_PAUSE_XON_THR_NON_PAUSE;
2091                 config_val->non_pauseable_th.full_xoff =
2092                         PFC_E3A0_BRB_MAC_FULL_XOFF_THR_NON_PAUSE;
2093                 config_val->non_pauseable_th.full_xon =
2094                         PFC_E3A0_BRB_MAC_FULL_XON_THR_NON_PAUSE;
2095         } else if (CHIP_IS_E3B0(bp)) {
2096                 /* Class0 defaults */
2097                 config_val->default_class0.pause_xoff =
2098                         DEFAULT0_E3B0_BRB_MAC_PAUSE_XOFF_THR;
2099                 config_val->default_class0.pause_xon =
2100                     DEFAULT0_E3B0_BRB_MAC_PAUSE_XON_THR;
2101                 config_val->default_class0.full_xoff =
2102                     DEFAULT0_E3B0_BRB_MAC_FULL_XOFF_THR;
2103                 config_val->default_class0.full_xon =
2104                     DEFAULT0_E3B0_BRB_MAC_FULL_XON_THR;
2105
2106                 if (params->phy[INT_PHY].flags &
2107                     FLAGS_4_PORT_MODE) {
2108                         config_val->pauseable_th.pause_xoff =
2109                                 PFC_E3B0_4P_BRB_MAC_PAUSE_XOFF_THR_PAUSE;
2110                         config_val->pauseable_th.pause_xon =
2111                                 PFC_E3B0_4P_BRB_MAC_PAUSE_XON_THR_PAUSE;
2112                         config_val->pauseable_th.full_xoff =
2113                                 PFC_E3B0_4P_BRB_MAC_FULL_XOFF_THR_PAUSE;
2114                         config_val->pauseable_th.full_xon =
2115                                 PFC_E3B0_4P_BRB_MAC_FULL_XON_THR_PAUSE;
2116                         /* non pause able*/
2117                         config_val->non_pauseable_th.pause_xoff =
2118                         PFC_E3B0_4P_BRB_MAC_PAUSE_XOFF_THR_NON_PAUSE;
2119                         config_val->non_pauseable_th.pause_xon =
2120                         PFC_E3B0_4P_BRB_MAC_PAUSE_XON_THR_NON_PAUSE;
2121                         config_val->non_pauseable_th.full_xoff =
2122                         PFC_E3B0_4P_BRB_MAC_FULL_XOFF_THR_NON_PAUSE;
2123                         config_val->non_pauseable_th.full_xon =
2124                         PFC_E3B0_4P_BRB_MAC_FULL_XON_THR_NON_PAUSE;
2125                 } else {
2126                         config_val->pauseable_th.pause_xoff =
2127                                 PFC_E3B0_2P_BRB_MAC_PAUSE_XOFF_THR_PAUSE;
2128                         config_val->pauseable_th.pause_xon =
2129                                 PFC_E3B0_2P_BRB_MAC_PAUSE_XON_THR_PAUSE;
2130                         config_val->pauseable_th.full_xoff =
2131                                 PFC_E3B0_2P_BRB_MAC_FULL_XOFF_THR_PAUSE;
2132                         config_val->pauseable_th.full_xon =
2133                                 PFC_E3B0_2P_BRB_MAC_FULL_XON_THR_PAUSE;
2134                         /* non pause able*/
2135                         config_val->non_pauseable_th.pause_xoff =
2136                                 PFC_E3B0_2P_BRB_MAC_PAUSE_XOFF_THR_NON_PAUSE;
2137                         config_val->non_pauseable_th.pause_xon =
2138                                 PFC_E3B0_2P_BRB_MAC_PAUSE_XON_THR_NON_PAUSE;
2139                         config_val->non_pauseable_th.full_xoff =
2140                                 PFC_E3B0_2P_BRB_MAC_FULL_XOFF_THR_NON_PAUSE;
2141                         config_val->non_pauseable_th.full_xon =
2142                                 PFC_E3B0_2P_BRB_MAC_FULL_XON_THR_NON_PAUSE;
2143                 }
2144         } else
2145             return -EINVAL;
2146
2147         return 0;
2148 }
2149
2150 static void bnx2x_pfc_brb_get_e3b0_config_params(
2151                 struct link_params *params,
2152                 struct bnx2x_pfc_brb_e3b0_val
2153                 *e3b0_val,
2154                 struct bnx2x_nig_brb_pfc_port_params *pfc_params,
2155                 const u8 pfc_enabled)
2156 {
2157         if (pfc_enabled && pfc_params) {
2158                 e3b0_val->per_class_guaranty_mode = 1;
2159                 e3b0_val->lb_guarantied_hyst = 80;
2160
2161                 if (params->phy[INT_PHY].flags &
2162                     FLAGS_4_PORT_MODE) {
2163                         e3b0_val->full_lb_xoff_th =
2164                                 PFC_E3B0_4P_BRB_FULL_LB_XOFF_THR;
2165                         e3b0_val->full_lb_xon_threshold =
2166                                 PFC_E3B0_4P_BRB_FULL_LB_XON_THR;
2167                         e3b0_val->lb_guarantied =
2168                                 PFC_E3B0_4P_LB_GUART;
2169                         e3b0_val->mac_0_class_t_guarantied =
2170                                 PFC_E3B0_4P_BRB_MAC_0_CLASS_T_GUART;
2171                         e3b0_val->mac_0_class_t_guarantied_hyst =
2172                                 PFC_E3B0_4P_BRB_MAC_0_CLASS_T_GUART_HYST;
2173                         e3b0_val->mac_1_class_t_guarantied =
2174                                 PFC_E3B0_4P_BRB_MAC_1_CLASS_T_GUART;
2175                         e3b0_val->mac_1_class_t_guarantied_hyst =
2176                                 PFC_E3B0_4P_BRB_MAC_1_CLASS_T_GUART_HYST;
2177                 } else {
2178                         e3b0_val->full_lb_xoff_th =
2179                                 PFC_E3B0_2P_BRB_FULL_LB_XOFF_THR;
2180                         e3b0_val->full_lb_xon_threshold =
2181                                 PFC_E3B0_2P_BRB_FULL_LB_XON_THR;
2182                         e3b0_val->mac_0_class_t_guarantied_hyst =
2183                                 PFC_E3B0_2P_BRB_MAC_0_CLASS_T_GUART_HYST;
2184                         e3b0_val->mac_1_class_t_guarantied =
2185                                 PFC_E3B0_2P_BRB_MAC_1_CLASS_T_GUART;
2186                         e3b0_val->mac_1_class_t_guarantied_hyst =
2187                                 PFC_E3B0_2P_BRB_MAC_1_CLASS_T_GUART_HYST;
2188
2189                         if (pfc_params->cos0_pauseable !=
2190                                 pfc_params->cos1_pauseable) {
2191                                 /* nonpauseable= Lossy + pauseable = Lossless*/
2192                                 e3b0_val->lb_guarantied =
2193                                         PFC_E3B0_2P_MIX_PAUSE_LB_GUART;
2194                                 e3b0_val->mac_0_class_t_guarantied =
2195                                PFC_E3B0_2P_MIX_PAUSE_MAC_0_CLASS_T_GUART;
2196                         } else if (pfc_params->cos0_pauseable) {
2197                                 /* Lossless +Lossless*/
2198                                 e3b0_val->lb_guarantied =
2199                                         PFC_E3B0_2P_PAUSE_LB_GUART;
2200                                 e3b0_val->mac_0_class_t_guarantied =
2201                                    PFC_E3B0_2P_PAUSE_MAC_0_CLASS_T_GUART;
2202                         } else {
2203                                 /* Lossy +Lossy*/
2204                                 e3b0_val->lb_guarantied =
2205                                         PFC_E3B0_2P_NON_PAUSE_LB_GUART;
2206                                 e3b0_val->mac_0_class_t_guarantied =
2207                                PFC_E3B0_2P_NON_PAUSE_MAC_0_CLASS_T_GUART;
2208                         }
2209                 }
2210         } else {
2211                 e3b0_val->per_class_guaranty_mode = 0;
2212                 e3b0_val->lb_guarantied_hyst = 0;
2213                 e3b0_val->full_lb_xoff_th =
2214                         DEFAULT_E3B0_BRB_FULL_LB_XOFF_THR;
2215                 e3b0_val->full_lb_xon_threshold =
2216                         DEFAULT_E3B0_BRB_FULL_LB_XON_THR;
2217                 e3b0_val->lb_guarantied =
2218                         DEFAULT_E3B0_LB_GUART;
2219                 e3b0_val->mac_0_class_t_guarantied =
2220                         DEFAULT_E3B0_BRB_MAC_0_CLASS_T_GUART;
2221                 e3b0_val->mac_0_class_t_guarantied_hyst =
2222                         DEFAULT_E3B0_BRB_MAC_0_CLASS_T_GUART_HYST;
2223                 e3b0_val->mac_1_class_t_guarantied =
2224                         DEFAULT_E3B0_BRB_MAC_1_CLASS_T_GUART;
2225                 e3b0_val->mac_1_class_t_guarantied_hyst =
2226                         DEFAULT_E3B0_BRB_MAC_1_CLASS_T_GUART_HYST;
2227         }
2228 }
2229 static int bnx2x_update_pfc_brb(struct link_params *params,
2230                                 struct link_vars *vars,
2231                                 struct bnx2x_nig_brb_pfc_port_params
2232                                 *pfc_params)
2233 {
2234         struct bnx2x *bp = params->bp;
2235         struct bnx2x_pfc_brb_th_val config_val = { {0} };
2236         struct bnx2x_pfc_brb_threshold_val *reg_th_config =
2237                 &config_val.pauseable_th;
2238         struct bnx2x_pfc_brb_e3b0_val e3b0_val = {0};
2239         const int set_pfc = params->feature_config_flags &
2240                 FEATURE_CONFIG_PFC_ENABLED;
2241         const u8 pfc_enabled = (set_pfc && pfc_params);
2242         int bnx2x_status = 0;
2243         u8 port = params->port;
2244
2245         /* default - pause configuration */
2246         reg_th_config = &config_val.pauseable_th;
2247         bnx2x_status = bnx2x_pfc_brb_get_config_params(params, &config_val);
2248         if (bnx2x_status)
2249                 return bnx2x_status;
2250
2251         if (pfc_enabled) {
2252                 /* First COS */
2253                 if (pfc_params->cos0_pauseable)
2254                         reg_th_config = &config_val.pauseable_th;
2255                 else
2256                         reg_th_config = &config_val.non_pauseable_th;
2257         } else
2258                 reg_th_config = &config_val.default_class0;
2259         /* The number of free blocks below which the pause signal to class 0
2260          * of MAC #n is asserted. n=0,1
2261          */
2262         REG_WR(bp, (port) ? BRB1_REG_PAUSE_0_XOFF_THRESHOLD_1 :
2263                BRB1_REG_PAUSE_0_XOFF_THRESHOLD_0 ,
2264                reg_th_config->pause_xoff);
2265         /* The number of free blocks above which the pause signal to class 0
2266          * of MAC #n is de-asserted. n=0,1
2267          */
2268         REG_WR(bp, (port) ? BRB1_REG_PAUSE_0_XON_THRESHOLD_1 :
2269                BRB1_REG_PAUSE_0_XON_THRESHOLD_0 , reg_th_config->pause_xon);
2270         /* The number of free blocks below which the full signal to class 0
2271          * of MAC #n is asserted. n=0,1
2272          */
2273         REG_WR(bp, (port) ? BRB1_REG_FULL_0_XOFF_THRESHOLD_1 :
2274                BRB1_REG_FULL_0_XOFF_THRESHOLD_0 , reg_th_config->full_xoff);
2275         /* The number of free blocks above which the full signal to class 0
2276          * of MAC #n is de-asserted. n=0,1
2277          */
2278         REG_WR(bp, (port) ? BRB1_REG_FULL_0_XON_THRESHOLD_1 :
2279                BRB1_REG_FULL_0_XON_THRESHOLD_0 , reg_th_config->full_xon);
2280
2281         if (pfc_enabled) {
2282                 /* Second COS */
2283                 if (pfc_params->cos1_pauseable)
2284                         reg_th_config = &config_val.pauseable_th;
2285                 else
2286                         reg_th_config = &config_val.non_pauseable_th;
2287         } else
2288                 reg_th_config = &config_val.default_class1;
2289         /* The number of free blocks below which the pause signal to
2290          * class 1 of MAC #n is asserted. n=0,1
2291          */
2292         REG_WR(bp, (port) ? BRB1_REG_PAUSE_1_XOFF_THRESHOLD_1 :
2293                BRB1_REG_PAUSE_1_XOFF_THRESHOLD_0,
2294                reg_th_config->pause_xoff);
2295
2296         /* The number of free blocks above which the pause signal to
2297          * class 1 of MAC #n is de-asserted. n=0,1
2298          */
2299         REG_WR(bp, (port) ? BRB1_REG_PAUSE_1_XON_THRESHOLD_1 :
2300                BRB1_REG_PAUSE_1_XON_THRESHOLD_0,
2301                reg_th_config->pause_xon);
2302         /* The number of free blocks below which the full signal to
2303          * class 1 of MAC #n is asserted. n=0,1
2304          */
2305         REG_WR(bp, (port) ? BRB1_REG_FULL_1_XOFF_THRESHOLD_1 :
2306                BRB1_REG_FULL_1_XOFF_THRESHOLD_0,
2307                reg_th_config->full_xoff);
2308         /* The number of free blocks above which the full signal to
2309          * class 1 of MAC #n is de-asserted. n=0,1
2310          */
2311         REG_WR(bp, (port) ? BRB1_REG_FULL_1_XON_THRESHOLD_1 :
2312                BRB1_REG_FULL_1_XON_THRESHOLD_0,
2313                reg_th_config->full_xon);
2314
2315         if (CHIP_IS_E3B0(bp)) {
2316                 bnx2x_pfc_brb_get_e3b0_config_params(
2317                         params,
2318                         &e3b0_val,
2319                         pfc_params,
2320                         pfc_enabled);
2321
2322                 REG_WR(bp, BRB1_REG_PER_CLASS_GUARANTY_MODE,
2323                            e3b0_val.per_class_guaranty_mode);
2324
2325                 /* The hysteresis on the guarantied buffer space for the Lb
2326                  * port before signaling XON.
2327                  */
2328                 REG_WR(bp, BRB1_REG_LB_GUARANTIED_HYST,
2329                            e3b0_val.lb_guarantied_hyst);
2330
2331                 /* The number of free blocks below which the full signal to the
2332                  * LB port is asserted.
2333                  */
2334                 REG_WR(bp, BRB1_REG_FULL_LB_XOFF_THRESHOLD,
2335                        e3b0_val.full_lb_xoff_th);
2336                 /* The number of free blocks above which the full signal to the
2337                  * LB port is de-asserted.
2338                  */
2339                 REG_WR(bp, BRB1_REG_FULL_LB_XON_THRESHOLD,
2340                        e3b0_val.full_lb_xon_threshold);
2341                 /* The number of blocks guarantied for the MAC #n port. n=0,1
2342                  */
2343
2344                 /* The number of blocks guarantied for the LB port. */
2345                 REG_WR(bp, BRB1_REG_LB_GUARANTIED,
2346                        e3b0_val.lb_guarantied);
2347
2348                 /* The number of blocks guarantied for the MAC #n port. */
2349                 REG_WR(bp, BRB1_REG_MAC_GUARANTIED_0,
2350                        2 * e3b0_val.mac_0_class_t_guarantied);
2351                 REG_WR(bp, BRB1_REG_MAC_GUARANTIED_1,
2352                        2 * e3b0_val.mac_1_class_t_guarantied);
2353                 /* The number of blocks guarantied for class #t in MAC0. t=0,1
2354                  */
2355                 REG_WR(bp, BRB1_REG_MAC_0_CLASS_0_GUARANTIED,
2356                        e3b0_val.mac_0_class_t_guarantied);
2357                 REG_WR(bp, BRB1_REG_MAC_0_CLASS_1_GUARANTIED,
2358                        e3b0_val.mac_0_class_t_guarantied);
2359                 /* The hysteresis on the guarantied buffer space for class in
2360                  * MAC0.  t=0,1
2361                  */
2362                 REG_WR(bp, BRB1_REG_MAC_0_CLASS_0_GUARANTIED_HYST,
2363                        e3b0_val.mac_0_class_t_guarantied_hyst);
2364                 REG_WR(bp, BRB1_REG_MAC_0_CLASS_1_GUARANTIED_HYST,
2365                        e3b0_val.mac_0_class_t_guarantied_hyst);
2366
2367                 /* The number of blocks guarantied for class #t in MAC1.t=0,1
2368                  */
2369                 REG_WR(bp, BRB1_REG_MAC_1_CLASS_0_GUARANTIED,
2370                        e3b0_val.mac_1_class_t_guarantied);
2371                 REG_WR(bp, BRB1_REG_MAC_1_CLASS_1_GUARANTIED,
2372                        e3b0_val.mac_1_class_t_guarantied);
2373                 /* The hysteresis on the guarantied buffer space for class #t
2374                  * in MAC1.  t=0,1
2375                  */
2376                 REG_WR(bp, BRB1_REG_MAC_1_CLASS_0_GUARANTIED_HYST,
2377                        e3b0_val.mac_1_class_t_guarantied_hyst);
2378                 REG_WR(bp, BRB1_REG_MAC_1_CLASS_1_GUARANTIED_HYST,
2379                        e3b0_val.mac_1_class_t_guarantied_hyst);
2380         }
2381
2382         return bnx2x_status;
2383 }
2384
2385 /******************************************************************************
2386 * Description:
2387 *  This function is needed because NIG ARB_CREDIT_WEIGHT_X are
2388 *  not continues and ARB_CREDIT_WEIGHT_0 + offset is suitable.
2389 ******************************************************************************/
2390 int bnx2x_pfc_nig_rx_priority_mask(struct bnx2x *bp,
2391                                               u8 cos_entry,
2392                                               u32 priority_mask, u8 port)
2393 {
2394         u32 nig_reg_rx_priority_mask_add = 0;
2395
2396         switch (cos_entry) {
2397         case 0:
2398              nig_reg_rx_priority_mask_add = (port) ?
2399                  NIG_REG_P1_RX_COS0_PRIORITY_MASK :
2400                  NIG_REG_P0_RX_COS0_PRIORITY_MASK;
2401              break;
2402         case 1:
2403             nig_reg_rx_priority_mask_add = (port) ?
2404                 NIG_REG_P1_RX_COS1_PRIORITY_MASK :
2405                 NIG_REG_P0_RX_COS1_PRIORITY_MASK;
2406             break;
2407         case 2:
2408             nig_reg_rx_priority_mask_add = (port) ?
2409                 NIG_REG_P1_RX_COS2_PRIORITY_MASK :
2410                 NIG_REG_P0_RX_COS2_PRIORITY_MASK;
2411             break;
2412         case 3:
2413             if (port)
2414                 return -EINVAL;
2415             nig_reg_rx_priority_mask_add = NIG_REG_P0_RX_COS3_PRIORITY_MASK;
2416             break;
2417         case 4:
2418             if (port)
2419                 return -EINVAL;
2420             nig_reg_rx_priority_mask_add = NIG_REG_P0_RX_COS4_PRIORITY_MASK;
2421             break;
2422         case 5:
2423             if (port)
2424                 return -EINVAL;
2425             nig_reg_rx_priority_mask_add = NIG_REG_P0_RX_COS5_PRIORITY_MASK;
2426             break;
2427         }
2428
2429         REG_WR(bp, nig_reg_rx_priority_mask_add, priority_mask);
2430
2431         return 0;
2432 }
2433 static void bnx2x_update_mng(struct link_params *params, u32 link_status)
2434 {
2435         struct bnx2x *bp = params->bp;
2436
2437         REG_WR(bp, params->shmem_base +
2438                offsetof(struct shmem_region,
2439                         port_mb[params->port].link_status), link_status);
2440 }
2441
2442 static void bnx2x_update_pfc_nig(struct link_params *params,
2443                 struct link_vars *vars,
2444                 struct bnx2x_nig_brb_pfc_port_params *nig_params)
2445 {
2446         u32 xcm_mask = 0, ppp_enable = 0, pause_enable = 0, llfc_out_en = 0;
2447         u32 llfc_enable = 0, xcm_out_en = 0, hwpfc_enable = 0;
2448         u32 pkt_priority_to_cos = 0;
2449         struct bnx2x *bp = params->bp;
2450         u8 port = params->port;
2451
2452         int set_pfc = params->feature_config_flags &
2453                 FEATURE_CONFIG_PFC_ENABLED;
2454         DP(NETIF_MSG_LINK, "updating pfc nig parameters\n");
2455
2456         /* When NIG_LLH0_XCM_MASK_REG_LLHX_XCM_MASK_BCN bit is set
2457          * MAC control frames (that are not pause packets)
2458          * will be forwarded to the XCM.
2459          */
2460         xcm_mask = REG_RD(bp, port ? NIG_REG_LLH1_XCM_MASK :
2461                           NIG_REG_LLH0_XCM_MASK);
2462         /* NIG params will override non PFC params, since it's possible to
2463          * do transition from PFC to SAFC
2464          */
2465         if (set_pfc) {
2466                 pause_enable = 0;
2467                 llfc_out_en = 0;
2468                 llfc_enable = 0;
2469                 if (CHIP_IS_E3(bp))
2470                         ppp_enable = 0;
2471                 else
2472                 ppp_enable = 1;
2473                 xcm_mask &= ~(port ? NIG_LLH1_XCM_MASK_REG_LLH1_XCM_MASK_BCN :
2474                                      NIG_LLH0_XCM_MASK_REG_LLH0_XCM_MASK_BCN);
2475                 xcm_out_en = 0;
2476                 hwpfc_enable = 1;
2477         } else  {
2478                 if (nig_params) {
2479                         llfc_out_en = nig_params->llfc_out_en;
2480                         llfc_enable = nig_params->llfc_enable;
2481                         pause_enable = nig_params->pause_enable;
2482                 } else  /* Default non PFC mode - PAUSE */
2483                         pause_enable = 1;
2484
2485                 xcm_mask |= (port ? NIG_LLH1_XCM_MASK_REG_LLH1_XCM_MASK_BCN :
2486                         NIG_LLH0_XCM_MASK_REG_LLH0_XCM_MASK_BCN);
2487                 xcm_out_en = 1;
2488         }
2489
2490         if (CHIP_IS_E3(bp))
2491                 REG_WR(bp, port ? NIG_REG_BRB1_PAUSE_IN_EN :
2492                        NIG_REG_BRB0_PAUSE_IN_EN, pause_enable);
2493         REG_WR(bp, port ? NIG_REG_LLFC_OUT_EN_1 :
2494                NIG_REG_LLFC_OUT_EN_0, llfc_out_en);
2495         REG_WR(bp, port ? NIG_REG_LLFC_ENABLE_1 :
2496                NIG_REG_LLFC_ENABLE_0, llfc_enable);
2497         REG_WR(bp, port ? NIG_REG_PAUSE_ENABLE_1 :
2498                NIG_REG_PAUSE_ENABLE_0, pause_enable);
2499
2500         REG_WR(bp, port ? NIG_REG_PPP_ENABLE_1 :
2501                NIG_REG_PPP_ENABLE_0, ppp_enable);
2502
2503         REG_WR(bp, port ? NIG_REG_LLH1_XCM_MASK :
2504                NIG_REG_LLH0_XCM_MASK, xcm_mask);
2505
2506         REG_WR(bp, port ? NIG_REG_LLFC_EGRESS_SRC_ENABLE_1 :
2507                NIG_REG_LLFC_EGRESS_SRC_ENABLE_0, 0x7);
2508
2509         /* output enable for RX_XCM # IF */
2510         REG_WR(bp, port ? NIG_REG_XCM1_OUT_EN :
2511                NIG_REG_XCM0_OUT_EN, xcm_out_en);
2512
2513         /* HW PFC TX enable */
2514         REG_WR(bp, port ? NIG_REG_P1_HWPFC_ENABLE :
2515                NIG_REG_P0_HWPFC_ENABLE, hwpfc_enable);
2516
2517         if (nig_params) {
2518                 u8 i = 0;
2519                 pkt_priority_to_cos = nig_params->pkt_priority_to_cos;
2520
2521                 for (i = 0; i < nig_params->num_of_rx_cos_priority_mask; i++)
2522                         bnx2x_pfc_nig_rx_priority_mask(bp, i,
2523                 nig_params->rx_cos_priority_mask[i], port);
2524
2525                 REG_WR(bp, port ? NIG_REG_LLFC_HIGH_PRIORITY_CLASSES_1 :
2526                        NIG_REG_LLFC_HIGH_PRIORITY_CLASSES_0,
2527                        nig_params->llfc_high_priority_classes);
2528
2529                 REG_WR(bp, port ? NIG_REG_LLFC_LOW_PRIORITY_CLASSES_1 :
2530                        NIG_REG_LLFC_LOW_PRIORITY_CLASSES_0,
2531                        nig_params->llfc_low_priority_classes);
2532         }
2533         REG_WR(bp, port ? NIG_REG_P1_PKT_PRIORITY_TO_COS :
2534                NIG_REG_P0_PKT_PRIORITY_TO_COS,
2535                pkt_priority_to_cos);
2536 }
2537
2538 int bnx2x_update_pfc(struct link_params *params,
2539                       struct link_vars *vars,
2540                       struct bnx2x_nig_brb_pfc_port_params *pfc_params)
2541 {
2542         /* The PFC and pause are orthogonal to one another, meaning when
2543          * PFC is enabled, the pause are disabled, and when PFC is
2544          * disabled, pause are set according to the pause result.
2545          */
2546         u32 val;
2547         struct bnx2x *bp = params->bp;
2548         int bnx2x_status = 0;
2549         u8 bmac_loopback = (params->loopback_mode == LOOPBACK_BMAC);
2550
2551         if (params->feature_config_flags & FEATURE_CONFIG_PFC_ENABLED)
2552                 vars->link_status |= LINK_STATUS_PFC_ENABLED;
2553         else
2554                 vars->link_status &= ~LINK_STATUS_PFC_ENABLED;
2555
2556         bnx2x_update_mng(params, vars->link_status);
2557
2558         /* update NIG params */
2559         bnx2x_update_pfc_nig(params, vars, pfc_params);
2560
2561         /* update BRB params */
2562         bnx2x_status = bnx2x_update_pfc_brb(params, vars, pfc_params);
2563         if (bnx2x_status)
2564                 return bnx2x_status;
2565
2566         if (!vars->link_up)
2567                 return bnx2x_status;
2568
2569         DP(NETIF_MSG_LINK, "About to update PFC in BMAC\n");
2570         if (CHIP_IS_E3(bp))
2571                 bnx2x_update_pfc_xmac(params, vars, 0);
2572         else {
2573                 val = REG_RD(bp, MISC_REG_RESET_REG_2);
2574                 if ((val &
2575                      (MISC_REGISTERS_RESET_REG_2_RST_BMAC0 << params->port))
2576                     == 0) {
2577                         DP(NETIF_MSG_LINK, "About to update PFC in EMAC\n");
2578                         bnx2x_emac_enable(params, vars, 0);
2579                         return bnx2x_status;
2580                 }
2581                 if (CHIP_IS_E2(bp))
2582                         bnx2x_update_pfc_bmac2(params, vars, bmac_loopback);
2583                 else
2584                         bnx2x_update_pfc_bmac1(params, vars);
2585
2586                 val = 0;
2587                 if ((params->feature_config_flags &
2588                      FEATURE_CONFIG_PFC_ENABLED) ||
2589                     (vars->flow_ctrl & BNX2X_FLOW_CTRL_TX))
2590                         val = 1;
2591                 REG_WR(bp, NIG_REG_BMAC0_PAUSE_OUT_EN + params->port*4, val);
2592         }
2593         return bnx2x_status;
2594 }
2595
2596
2597 static int bnx2x_bmac1_enable(struct link_params *params,
2598                               struct link_vars *vars,
2599                               u8 is_lb)
2600 {
2601         struct bnx2x *bp = params->bp;
2602         u8 port = params->port;
2603         u32 bmac_addr = port ? NIG_REG_INGRESS_BMAC1_MEM :
2604                                NIG_REG_INGRESS_BMAC0_MEM;
2605         u32 wb_data[2];
2606         u32 val;
2607
2608         DP(NETIF_MSG_LINK, "Enabling BigMAC1\n");
2609
2610         /* XGXS control */
2611         wb_data[0] = 0x3c;
2612         wb_data[1] = 0;
2613         REG_WR_DMAE(bp, bmac_addr + BIGMAC_REGISTER_BMAC_XGXS_CONTROL,
2614                     wb_data, 2);
2615
2616         /* tx MAC SA */
2617         wb_data[0] = ((params->mac_addr[2] << 24) |
2618                        (params->mac_addr[3] << 16) |
2619                        (params->mac_addr[4] << 8) |
2620                         params->mac_addr[5]);
2621         wb_data[1] = ((params->mac_addr[0] << 8) |
2622                         params->mac_addr[1]);
2623         REG_WR_DMAE(bp, bmac_addr + BIGMAC_REGISTER_TX_SOURCE_ADDR, wb_data, 2);
2624
2625         /* mac control */
2626         val = 0x3;
2627         if (is_lb) {
2628                 val |= 0x4;
2629                 DP(NETIF_MSG_LINK, "enable bmac loopback\n");
2630         }
2631         wb_data[0] = val;
2632         wb_data[1] = 0;
2633         REG_WR_DMAE(bp, bmac_addr + BIGMAC_REGISTER_BMAC_CONTROL, wb_data, 2);
2634
2635         /* set rx mtu */
2636         wb_data[0] = ETH_MAX_JUMBO_PACKET_SIZE + ETH_OVREHEAD;
2637         wb_data[1] = 0;
2638         REG_WR_DMAE(bp, bmac_addr + BIGMAC_REGISTER_RX_MAX_SIZE, wb_data, 2);
2639
2640         bnx2x_update_pfc_bmac1(params, vars);
2641
2642         /* set tx mtu */
2643         wb_data[0] = ETH_MAX_JUMBO_PACKET_SIZE + ETH_OVREHEAD;
2644         wb_data[1] = 0;
2645         REG_WR_DMAE(bp, bmac_addr + BIGMAC_REGISTER_TX_MAX_SIZE, wb_data, 2);
2646
2647         /* set cnt max size */
2648         wb_data[0] = ETH_MAX_JUMBO_PACKET_SIZE + ETH_OVREHEAD;
2649         wb_data[1] = 0;
2650         REG_WR_DMAE(bp, bmac_addr + BIGMAC_REGISTER_CNT_MAX_SIZE, wb_data, 2);
2651
2652         /* configure safc */
2653         wb_data[0] = 0x1000200;
2654         wb_data[1] = 0;
2655         REG_WR_DMAE(bp, bmac_addr + BIGMAC_REGISTER_RX_LLFC_MSG_FLDS,
2656                     wb_data, 2);
2657
2658         return 0;
2659 }
2660
2661 static int bnx2x_bmac2_enable(struct link_params *params,
2662                               struct link_vars *vars,
2663                               u8 is_lb)
2664 {
2665         struct bnx2x *bp = params->bp;
2666         u8 port = params->port;
2667         u32 bmac_addr = port ? NIG_REG_INGRESS_BMAC1_MEM :
2668                                NIG_REG_INGRESS_BMAC0_MEM;
2669         u32 wb_data[2];
2670
2671         DP(NETIF_MSG_LINK, "Enabling BigMAC2\n");
2672
2673         wb_data[0] = 0;
2674         wb_data[1] = 0;
2675         REG_WR_DMAE(bp, bmac_addr + BIGMAC2_REGISTER_BMAC_CONTROL, wb_data, 2);
2676         udelay(30);
2677
2678         /* XGXS control: Reset phy HW, MDIO registers, PHY PLL and BMAC */
2679         wb_data[0] = 0x3c;
2680         wb_data[1] = 0;
2681         REG_WR_DMAE(bp, bmac_addr + BIGMAC2_REGISTER_BMAC_XGXS_CONTROL,
2682                     wb_data, 2);
2683
2684         udelay(30);
2685
2686         /* tx MAC SA */
2687         wb_data[0] = ((params->mac_addr[2] << 24) |
2688                        (params->mac_addr[3] << 16) |
2689                        (params->mac_addr[4] << 8) |
2690                         params->mac_addr[5]);
2691         wb_data[1] = ((params->mac_addr[0] << 8) |
2692                         params->mac_addr[1]);
2693         REG_WR_DMAE(bp, bmac_addr + BIGMAC2_REGISTER_TX_SOURCE_ADDR,
2694                     wb_data, 2);
2695
2696         udelay(30);
2697
2698         /* Configure SAFC */
2699         wb_data[0] = 0x1000200;
2700         wb_data[1] = 0;
2701         REG_WR_DMAE(bp, bmac_addr + BIGMAC2_REGISTER_RX_LLFC_MSG_FLDS,
2702                     wb_data, 2);
2703         udelay(30);
2704
2705         /* set rx mtu */
2706         wb_data[0] = ETH_MAX_JUMBO_PACKET_SIZE + ETH_OVREHEAD;
2707         wb_data[1] = 0;
2708         REG_WR_DMAE(bp, bmac_addr + BIGMAC2_REGISTER_RX_MAX_SIZE, wb_data, 2);
2709         udelay(30);
2710
2711         /* set tx mtu */
2712         wb_data[0] = ETH_MAX_JUMBO_PACKET_SIZE + ETH_OVREHEAD;
2713         wb_data[1] = 0;
2714         REG_WR_DMAE(bp, bmac_addr + BIGMAC2_REGISTER_TX_MAX_SIZE, wb_data, 2);
2715         udelay(30);
2716         /* set cnt max size */
2717         wb_data[0] = ETH_MAX_JUMBO_PACKET_SIZE + ETH_OVREHEAD - 2;
2718         wb_data[1] = 0;
2719         REG_WR_DMAE(bp, bmac_addr + BIGMAC2_REGISTER_CNT_MAX_SIZE, wb_data, 2);
2720         udelay(30);
2721         bnx2x_update_pfc_bmac2(params, vars, is_lb);
2722
2723         return 0;
2724 }
2725
2726 static int bnx2x_bmac_enable(struct link_params *params,
2727                              struct link_vars *vars,
2728                              u8 is_lb)
2729 {
2730         int rc = 0;
2731         u8 port = params->port;
2732         struct bnx2x *bp = params->bp;
2733         u32 val;
2734         /* reset and unreset the BigMac */
2735         REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR,
2736                (MISC_REGISTERS_RESET_REG_2_RST_BMAC0 << port));
2737         msleep(1);
2738
2739         REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_SET,
2740                (MISC_REGISTERS_RESET_REG_2_RST_BMAC0 << port));
2741
2742         /* enable access for bmac registers */
2743         REG_WR(bp, NIG_REG_BMAC0_REGS_OUT_EN + port*4, 0x1);
2744
2745         /* Enable BMAC according to BMAC type*/
2746         if (CHIP_IS_E2(bp))
2747                 rc = bnx2x_bmac2_enable(params, vars, is_lb);
2748         else
2749                 rc = bnx2x_bmac1_enable(params, vars, is_lb);
2750         REG_WR(bp, NIG_REG_XGXS_SERDES0_MODE_SEL + port*4, 0x1);
2751         REG_WR(bp, NIG_REG_XGXS_LANE_SEL_P0 + port*4, 0x0);
2752         REG_WR(bp, NIG_REG_EGRESS_EMAC0_PORT + port*4, 0x0);
2753         val = 0;
2754         if ((params->feature_config_flags &
2755               FEATURE_CONFIG_PFC_ENABLED) ||
2756             (vars->flow_ctrl & BNX2X_FLOW_CTRL_TX))
2757                 val = 1;
2758         REG_WR(bp, NIG_REG_BMAC0_PAUSE_OUT_EN + port*4, val);
2759         REG_WR(bp, NIG_REG_EGRESS_EMAC0_OUT_EN + port*4, 0x0);
2760         REG_WR(bp, NIG_REG_EMAC0_IN_EN + port*4, 0x0);
2761         REG_WR(bp, NIG_REG_EMAC0_PAUSE_OUT_EN + port*4, 0x0);
2762         REG_WR(bp, NIG_REG_BMAC0_IN_EN + port*4, 0x1);
2763         REG_WR(bp, NIG_REG_BMAC0_OUT_EN + port*4, 0x1);
2764
2765         vars->mac_type = MAC_TYPE_BMAC;
2766         return rc;
2767 }
2768
2769 static void bnx2x_bmac_rx_disable(struct bnx2x *bp, u8 port)
2770 {
2771         u32 bmac_addr = port ? NIG_REG_INGRESS_BMAC1_MEM :
2772                         NIG_REG_INGRESS_BMAC0_MEM;
2773         u32 wb_data[2];
2774         u32 nig_bmac_enable = REG_RD(bp, NIG_REG_BMAC0_REGS_OUT_EN + port*4);
2775
2776         /* Only if the bmac is out of reset */
2777         if (REG_RD(bp, MISC_REG_RESET_REG_2) &
2778                         (MISC_REGISTERS_RESET_REG_2_RST_BMAC0 << port) &&
2779             nig_bmac_enable) {
2780
2781                 if (CHIP_IS_E2(bp)) {
2782                         /* Clear Rx Enable bit in BMAC_CONTROL register */
2783                         REG_RD_DMAE(bp, bmac_addr +
2784                                     BIGMAC2_REGISTER_BMAC_CONTROL,
2785                                     wb_data, 2);
2786                         wb_data[0] &= ~BMAC_CONTROL_RX_ENABLE;
2787                         REG_WR_DMAE(bp, bmac_addr +
2788                                     BIGMAC2_REGISTER_BMAC_CONTROL,
2789                                     wb_data, 2);
2790                 } else {
2791                         /* Clear Rx Enable bit in BMAC_CONTROL register */
2792                         REG_RD_DMAE(bp, bmac_addr +
2793                                         BIGMAC_REGISTER_BMAC_CONTROL,
2794                                         wb_data, 2);
2795                         wb_data[0] &= ~BMAC_CONTROL_RX_ENABLE;
2796                         REG_WR_DMAE(bp, bmac_addr +
2797                                         BIGMAC_REGISTER_BMAC_CONTROL,
2798                                         wb_data, 2);
2799                 }
2800                 msleep(1);
2801         }
2802 }
2803
2804 static int bnx2x_pbf_update(struct link_params *params, u32 flow_ctrl,
2805                             u32 line_speed)
2806 {
2807         struct bnx2x *bp = params->bp;
2808         u8 port = params->port;
2809         u32 init_crd, crd;
2810         u32 count = 1000;
2811
2812         /* disable port */
2813         REG_WR(bp, PBF_REG_DISABLE_NEW_TASK_PROC_P0 + port*4, 0x1);
2814
2815         /* wait for init credit */
2816         init_crd = REG_RD(bp, PBF_REG_P0_INIT_CRD + port*4);
2817         crd = REG_RD(bp, PBF_REG_P0_CREDIT + port*8);
2818         DP(NETIF_MSG_LINK, "init_crd 0x%x  crd 0x%x\n", init_crd, crd);
2819
2820         while ((init_crd != crd) && count) {
2821                 msleep(5);
2822
2823                 crd = REG_RD(bp, PBF_REG_P0_CREDIT + port*8);
2824                 count--;
2825         }
2826         crd = REG_RD(bp, PBF_REG_P0_CREDIT + port*8);
2827         if (init_crd != crd) {
2828                 DP(NETIF_MSG_LINK, "BUG! init_crd 0x%x != crd 0x%x\n",
2829                           init_crd, crd);
2830                 return -EINVAL;
2831         }
2832
2833         if (flow_ctrl & BNX2X_FLOW_CTRL_RX ||
2834             line_speed == SPEED_10 ||
2835             line_speed == SPEED_100 ||
2836             line_speed == SPEED_1000 ||
2837             line_speed == SPEED_2500) {
2838                 REG_WR(bp, PBF_REG_P0_PAUSE_ENABLE + port*4, 1);
2839                 /* update threshold */
2840                 REG_WR(bp, PBF_REG_P0_ARB_THRSH + port*4, 0);
2841                 /* update init credit */
2842                 init_crd = 778;         /* (800-18-4) */
2843
2844         } else {
2845                 u32 thresh = (ETH_MAX_JUMBO_PACKET_SIZE +
2846                               ETH_OVREHEAD)/16;
2847                 REG_WR(bp, PBF_REG_P0_PAUSE_ENABLE + port*4, 0);
2848                 /* update threshold */
2849                 REG_WR(bp, PBF_REG_P0_ARB_THRSH + port*4, thresh);
2850                 /* update init credit */
2851                 switch (line_speed) {
2852                 case SPEED_10000:
2853                         init_crd = thresh + 553 - 22;
2854                         break;
2855                 default:
2856                         DP(NETIF_MSG_LINK, "Invalid line_speed 0x%x\n",
2857                                   line_speed);
2858                         return -EINVAL;
2859                 }
2860         }
2861         REG_WR(bp, PBF_REG_P0_INIT_CRD + port*4, init_crd);
2862         DP(NETIF_MSG_LINK, "PBF updated to speed %d credit %d\n",
2863                  line_speed, init_crd);
2864
2865         /* probe the credit changes */
2866         REG_WR(bp, PBF_REG_INIT_P0 + port*4, 0x1);
2867         msleep(5);
2868         REG_WR(bp, PBF_REG_INIT_P0 + port*4, 0x0);
2869
2870         /* enable port */
2871         REG_WR(bp, PBF_REG_DISABLE_NEW_TASK_PROC_P0 + port*4, 0x0);
2872         return 0;
2873 }
2874
2875 /**
2876  * bnx2x_get_emac_base - retrive emac base address
2877  *
2878  * @bp:                 driver handle
2879  * @mdc_mdio_access:    access type
2880  * @port:               port id
2881  *
2882  * This function selects the MDC/MDIO access (through emac0 or
2883  * emac1) depend on the mdc_mdio_access, port, port swapped. Each
2884  * phy has a default access mode, which could also be overridden
2885  * by nvram configuration. This parameter, whether this is the
2886  * default phy configuration, or the nvram overrun
2887  * configuration, is passed here as mdc_mdio_access and selects
2888  * the emac_base for the CL45 read/writes operations
2889  */
2890 static u32 bnx2x_get_emac_base(struct bnx2x *bp,
2891                                u32 mdc_mdio_access, u8 port)
2892 {
2893         u32 emac_base = 0;
2894         switch (mdc_mdio_access) {
2895         case SHARED_HW_CFG_MDC_MDIO_ACCESS1_PHY_TYPE:
2896                 break;
2897         case SHARED_HW_CFG_MDC_MDIO_ACCESS1_EMAC0:
2898                 if (REG_RD(bp, NIG_REG_PORT_SWAP))
2899                         emac_base = GRCBASE_EMAC1;
2900                 else
2901                         emac_base = GRCBASE_EMAC0;
2902                 break;
2903         case SHARED_HW_CFG_MDC_MDIO_ACCESS1_EMAC1:
2904                 if (REG_RD(bp, NIG_REG_PORT_SWAP))
2905                         emac_base = GRCBASE_EMAC0;
2906                 else
2907                         emac_base = GRCBASE_EMAC1;
2908                 break;
2909         case SHARED_HW_CFG_MDC_MDIO_ACCESS1_BOTH:
2910                 emac_base = (port) ? GRCBASE_EMAC1 : GRCBASE_EMAC0;
2911                 break;
2912         case SHARED_HW_CFG_MDC_MDIO_ACCESS1_SWAPPED:
2913                 emac_base = (port) ? GRCBASE_EMAC0 : GRCBASE_EMAC1;
2914                 break;
2915         default:
2916                 break;
2917         }
2918         return emac_base;
2919
2920 }
2921
2922 /******************************************************************/
2923 /*                      CL22 access functions                     */
2924 /******************************************************************/
2925 static int bnx2x_cl22_write(struct bnx2x *bp,
2926                                        struct bnx2x_phy *phy,
2927                                        u16 reg, u16 val)
2928 {
2929         u32 tmp, mode;
2930         u8 i;
2931         int rc = 0;
2932         /* Switch to CL22 */
2933         mode = REG_RD(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_MODE);
2934         REG_WR(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_MODE,
2935                mode & ~EMAC_MDIO_MODE_CLAUSE_45);
2936
2937         /* address */
2938         tmp = ((phy->addr << 21) | (reg << 16) | val |
2939                EMAC_MDIO_COMM_COMMAND_WRITE_22 |
2940                EMAC_MDIO_COMM_START_BUSY);
2941         REG_WR(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM, tmp);
2942
2943         for (i = 0; i < 50; i++) {
2944                 udelay(10);
2945
2946                 tmp = REG_RD(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM);
2947                 if (!(tmp & EMAC_MDIO_COMM_START_BUSY)) {
2948                         udelay(5);
2949                         break;
2950                 }
2951         }
2952         if (tmp & EMAC_MDIO_COMM_START_BUSY) {
2953                 DP(NETIF_MSG_LINK, "write phy register failed\n");
2954                 rc = -EFAULT;
2955         }
2956         REG_WR(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_MODE, mode);
2957         return rc;
2958 }
2959
2960 static int bnx2x_cl22_read(struct bnx2x *bp,
2961                                       struct bnx2x_phy *phy,
2962                                       u16 reg, u16 *ret_val)
2963 {
2964         u32 val, mode;
2965         u16 i;
2966         int rc = 0;
2967
2968         /* Switch to CL22 */
2969         mode = REG_RD(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_MODE);
2970         REG_WR(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_MODE,
2971                mode & ~EMAC_MDIO_MODE_CLAUSE_45);
2972
2973         /* address */
2974         val = ((phy->addr << 21) | (reg << 16) |
2975                EMAC_MDIO_COMM_COMMAND_READ_22 |
2976                EMAC_MDIO_COMM_START_BUSY);
2977         REG_WR(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM, val);
2978
2979         for (i = 0; i < 50; i++) {
2980                 udelay(10);
2981
2982                 val = REG_RD(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM);
2983                 if (!(val & EMAC_MDIO_COMM_START_BUSY)) {
2984                         *ret_val = (u16)(val & EMAC_MDIO_COMM_DATA);
2985                         udelay(5);
2986                         break;
2987                 }
2988         }
2989         if (val & EMAC_MDIO_COMM_START_BUSY) {
2990                 DP(NETIF_MSG_LINK, "read phy register failed\n");
2991
2992                 *ret_val = 0;
2993                 rc = -EFAULT;
2994         }
2995         REG_WR(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_MODE, mode);
2996         return rc;
2997 }
2998
2999 /******************************************************************/
3000 /*                      CL45 access functions                     */
3001 /******************************************************************/
3002 static int bnx2x_cl45_read(struct bnx2x *bp, struct bnx2x_phy *phy,
3003                            u8 devad, u16 reg, u16 *ret_val)
3004 {
3005         u32 val;
3006         u16 i;
3007         int rc = 0;
3008         if (phy->flags & FLAGS_MDC_MDIO_WA_B0)
3009                 bnx2x_bits_en(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_STATUS,
3010                               EMAC_MDIO_STATUS_10MB);
3011         /* address */
3012         val = ((phy->addr << 21) | (devad << 16) | reg |
3013                EMAC_MDIO_COMM_COMMAND_ADDRESS |
3014                EMAC_MDIO_COMM_START_BUSY);
3015         REG_WR(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM, val);
3016
3017         for (i = 0; i < 50; i++) {
3018                 udelay(10);
3019
3020                 val = REG_RD(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM);
3021                 if (!(val & EMAC_MDIO_COMM_START_BUSY)) {
3022                         udelay(5);
3023                         break;
3024                 }
3025         }
3026         if (val & EMAC_MDIO_COMM_START_BUSY) {
3027                 DP(NETIF_MSG_LINK, "read phy register failed\n");
3028                 netdev_err(bp->dev,  "MDC/MDIO access timeout\n");
3029                 *ret_val = 0;
3030                 rc = -EFAULT;
3031         } else {
3032                 /* data */
3033                 val = ((phy->addr << 21) | (devad << 16) |
3034                        EMAC_MDIO_COMM_COMMAND_READ_45 |
3035                        EMAC_MDIO_COMM_START_BUSY);
3036                 REG_WR(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM, val);
3037
3038                 for (i = 0; i < 50; i++) {
3039                         udelay(10);
3040
3041                         val = REG_RD(bp, phy->mdio_ctrl +
3042                                      EMAC_REG_EMAC_MDIO_COMM);
3043                         if (!(val & EMAC_MDIO_COMM_START_BUSY)) {
3044                                 *ret_val = (u16)(val & EMAC_MDIO_COMM_DATA);
3045                                 break;
3046                         }
3047                 }
3048                 if (val & EMAC_MDIO_COMM_START_BUSY) {
3049                         DP(NETIF_MSG_LINK, "read phy register failed\n");
3050                         netdev_err(bp->dev,  "MDC/MDIO access timeout\n");
3051                         *ret_val = 0;
3052                         rc = -EFAULT;
3053                 }
3054         }
3055         /* Work around for E3 A0 */
3056         if (phy->flags & FLAGS_MDC_MDIO_WA) {
3057                 phy->flags ^= FLAGS_DUMMY_READ;
3058                 if (phy->flags & FLAGS_DUMMY_READ) {
3059                         u16 temp_val;
3060                         bnx2x_cl45_read(bp, phy, devad, 0xf, &temp_val);
3061                 }
3062         }
3063
3064         if (phy->flags & FLAGS_MDC_MDIO_WA_B0)
3065                 bnx2x_bits_dis(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_STATUS,
3066                                EMAC_MDIO_STATUS_10MB);
3067         return rc;
3068 }
3069
3070 static int bnx2x_cl45_write(struct bnx2x *bp, struct bnx2x_phy *phy,
3071                             u8 devad, u16 reg, u16 val)
3072 {
3073         u32 tmp;
3074         u8 i;
3075         int rc = 0;
3076         if (phy->flags & FLAGS_MDC_MDIO_WA_B0)
3077                 bnx2x_bits_en(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_STATUS,
3078                               EMAC_MDIO_STATUS_10MB);
3079
3080         /* address */
3081         tmp = ((phy->addr << 21) | (devad << 16) | reg |
3082                EMAC_MDIO_COMM_COMMAND_ADDRESS |
3083                EMAC_MDIO_COMM_START_BUSY);
3084         REG_WR(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM, tmp);
3085
3086         for (i = 0; i < 50; i++) {
3087                 udelay(10);
3088
3089                 tmp = REG_RD(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM);
3090                 if (!(tmp & EMAC_MDIO_COMM_START_BUSY)) {
3091                         udelay(5);
3092                         break;
3093                 }
3094         }
3095         if (tmp & EMAC_MDIO_COMM_START_BUSY) {
3096                 DP(NETIF_MSG_LINK, "write phy register failed\n");
3097                 netdev_err(bp->dev,  "MDC/MDIO access timeout\n");
3098                 rc = -EFAULT;
3099         } else {
3100                 /* data */
3101                 tmp = ((phy->addr << 21) | (devad << 16) | val |
3102                        EMAC_MDIO_COMM_COMMAND_WRITE_45 |
3103                        EMAC_MDIO_COMM_START_BUSY);
3104                 REG_WR(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM, tmp);
3105
3106                 for (i = 0; i < 50; i++) {
3107                         udelay(10);
3108
3109                         tmp = REG_RD(bp, phy->mdio_ctrl +
3110                                      EMAC_REG_EMAC_MDIO_COMM);
3111                         if (!(tmp & EMAC_MDIO_COMM_START_BUSY)) {
3112                                 udelay(5);
3113                                 break;
3114                         }
3115                 }
3116                 if (tmp & EMAC_MDIO_COMM_START_BUSY) {
3117                         DP(NETIF_MSG_LINK, "write phy register failed\n");
3118                         netdev_err(bp->dev,  "MDC/MDIO access timeout\n");
3119                         rc = -EFAULT;
3120                 }
3121         }
3122         /* Work around for E3 A0 */
3123         if (phy->flags & FLAGS_MDC_MDIO_WA) {
3124                 phy->flags ^= FLAGS_DUMMY_READ;
3125                 if (phy->flags & FLAGS_DUMMY_READ) {
3126                         u16 temp_val;
3127                         bnx2x_cl45_read(bp, phy, devad, 0xf, &temp_val);
3128                 }
3129         }
3130         if (phy->flags & FLAGS_MDC_MDIO_WA_B0)
3131                 bnx2x_bits_dis(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_STATUS,
3132                                EMAC_MDIO_STATUS_10MB);
3133         return rc;
3134 }
3135 /******************************************************************/
3136 /*                      BSC access functions from E3              */
3137 /******************************************************************/
3138 static void bnx2x_bsc_module_sel(struct link_params *params)
3139 {
3140         int idx;
3141         u32 board_cfg, sfp_ctrl;
3142         u32 i2c_pins[I2C_SWITCH_WIDTH], i2c_val[I2C_SWITCH_WIDTH];
3143         struct bnx2x *bp = params->bp;
3144         u8 port = params->port;
3145         /* Read I2C output PINs */
3146         board_cfg = REG_RD(bp, params->shmem_base +
3147                            offsetof(struct shmem_region,
3148                                     dev_info.shared_hw_config.board));
3149         i2c_pins[I2C_BSC0] = board_cfg & SHARED_HW_CFG_E3_I2C_MUX0_MASK;
3150         i2c_pins[I2C_BSC1] = (board_cfg & SHARED_HW_CFG_E3_I2C_MUX1_MASK) >>
3151                         SHARED_HW_CFG_E3_I2C_MUX1_SHIFT;
3152
3153         /* Read I2C output value */
3154         sfp_ctrl = REG_RD(bp, params->shmem_base +
3155                           offsetof(struct shmem_region,
3156                                  dev_info.port_hw_config[port].e3_cmn_pin_cfg));
3157         i2c_val[I2C_BSC0] = (sfp_ctrl & PORT_HW_CFG_E3_I2C_MUX0_MASK) > 0;
3158         i2c_val[I2C_BSC1] = (sfp_ctrl & PORT_HW_CFG_E3_I2C_MUX1_MASK) > 0;
3159         DP(NETIF_MSG_LINK, "Setting BSC switch\n");
3160         for (idx = 0; idx < I2C_SWITCH_WIDTH; idx++)
3161                 bnx2x_set_cfg_pin(bp, i2c_pins[idx], i2c_val[idx]);
3162 }
3163
3164 static int bnx2x_bsc_read(struct link_params *params,
3165                           struct bnx2x_phy *phy,
3166                           u8 sl_devid,
3167                           u16 sl_addr,
3168                           u8 lc_addr,
3169                           u8 xfer_cnt,
3170                           u32 *data_array)
3171 {
3172         u32 val, i;
3173         int rc = 0;
3174         struct bnx2x *bp = params->bp;
3175
3176         if ((sl_devid != 0xa0) && (sl_devid != 0xa2)) {
3177                 DP(NETIF_MSG_LINK, "invalid sl_devid 0x%x\n", sl_devid);
3178                 return -EINVAL;
3179         }
3180
3181         if (xfer_cnt > 16) {
3182                 DP(NETIF_MSG_LINK, "invalid xfer_cnt %d. Max is 16 bytes\n",
3183                                         xfer_cnt);
3184                 return -EINVAL;
3185         }
3186         bnx2x_bsc_module_sel(params);
3187
3188         xfer_cnt = 16 - lc_addr;
3189
3190         /* enable the engine */
3191         val = REG_RD(bp, MCP_REG_MCPR_IMC_COMMAND);
3192         val |= MCPR_IMC_COMMAND_ENABLE;
3193         REG_WR(bp, MCP_REG_MCPR_IMC_COMMAND, val);
3194
3195         /* program slave device ID */
3196         val = (sl_devid << 16) | sl_addr;
3197         REG_WR(bp, MCP_REG_MCPR_IMC_SLAVE_CONTROL, val);
3198
3199         /* start xfer with 0 byte to update the address pointer ???*/
3200         val = (MCPR_IMC_COMMAND_ENABLE) |
3201               (MCPR_IMC_COMMAND_WRITE_OP <<
3202                 MCPR_IMC_COMMAND_OPERATION_BITSHIFT) |
3203                 (lc_addr << MCPR_IMC_COMMAND_TRANSFER_ADDRESS_BITSHIFT) | (0);
3204         REG_WR(bp, MCP_REG_MCPR_IMC_COMMAND, val);
3205
3206         /* poll for completion */
3207         i = 0;
3208         val = REG_RD(bp, MCP_REG_MCPR_IMC_COMMAND);
3209         while (((val >> MCPR_IMC_COMMAND_IMC_STATUS_BITSHIFT) & 0x3) != 1) {
3210                 udelay(10);
3211                 val = REG_RD(bp, MCP_REG_MCPR_IMC_COMMAND);
3212                 if (i++ > 1000) {
3213                         DP(NETIF_MSG_LINK, "wr 0 byte timed out after %d try\n",
3214                                                                 i);
3215                         rc = -EFAULT;
3216                         break;
3217                 }
3218         }
3219         if (rc == -EFAULT)
3220                 return rc;
3221
3222         /* start xfer with read op */
3223         val = (MCPR_IMC_COMMAND_ENABLE) |
3224                 (MCPR_IMC_COMMAND_READ_OP <<
3225                 MCPR_IMC_COMMAND_OPERATION_BITSHIFT) |
3226                 (lc_addr << MCPR_IMC_COMMAND_TRANSFER_ADDRESS_BITSHIFT) |
3227                   (xfer_cnt);
3228         REG_WR(bp, MCP_REG_MCPR_IMC_COMMAND, val);
3229
3230         /* poll for completion */
3231         i = 0;
3232         val = REG_RD(bp, MCP_REG_MCPR_IMC_COMMAND);
3233         while (((val >> MCPR_IMC_COMMAND_IMC_STATUS_BITSHIFT) & 0x3) != 1) {
3234                 udelay(10);
3235                 val = REG_RD(bp, MCP_REG_MCPR_IMC_COMMAND);
3236                 if (i++ > 1000) {
3237                         DP(NETIF_MSG_LINK, "rd op timed out after %d try\n", i);
3238                         rc = -EFAULT;
3239                         break;
3240                 }
3241         }
3242         if (rc == -EFAULT)
3243                 return rc;
3244
3245         for (i = (lc_addr >> 2); i < 4; i++) {
3246                 data_array[i] = REG_RD(bp, (MCP_REG_MCPR_IMC_DATAREG0 + i*4));
3247 #ifdef __BIG_ENDIAN
3248                 data_array[i] = ((data_array[i] & 0x000000ff) << 24) |
3249                                 ((data_array[i] & 0x0000ff00) << 8) |
3250                                 ((data_array[i] & 0x00ff0000) >> 8) |
3251                                 ((data_array[i] & 0xff000000) >> 24);
3252 #endif
3253         }
3254         return rc;
3255 }
3256
3257 static void bnx2x_cl45_read_or_write(struct bnx2x *bp, struct bnx2x_phy *phy,
3258                                      u8 devad, u16 reg, u16 or_val)
3259 {
3260         u16 val;
3261         bnx2x_cl45_read(bp, phy, devad, reg, &val);
3262         bnx2x_cl45_write(bp, phy, devad, reg, val | or_val);
3263 }
3264
3265 int bnx2x_phy_read(struct link_params *params, u8 phy_addr,
3266                    u8 devad, u16 reg, u16 *ret_val)
3267 {
3268         u8 phy_index;
3269         /* Probe for the phy according to the given phy_addr, and execute
3270          * the read request on it
3271          */
3272         for (phy_index = 0; phy_index < params->num_phys; phy_index++) {
3273                 if (params->phy[phy_index].addr == phy_addr) {
3274                         return bnx2x_cl45_read(params->bp,
3275                                                &params->phy[phy_index], devad,
3276                                                reg, ret_val);
3277                 }
3278         }
3279         return -EINVAL;
3280 }
3281
3282 int bnx2x_phy_write(struct link_params *params, u8 phy_addr,
3283                     u8 devad, u16 reg, u16 val)
3284 {
3285         u8 phy_index;
3286         /* Probe for the phy according to the given phy_addr, and execute
3287          * the write request on it
3288          */
3289         for (phy_index = 0; phy_index < params->num_phys; phy_index++) {
3290                 if (params->phy[phy_index].addr == phy_addr) {
3291                         return bnx2x_cl45_write(params->bp,
3292                                                 &params->phy[phy_index], devad,
3293                                                 reg, val);
3294                 }
3295         }
3296         return -EINVAL;
3297 }
3298 static u8 bnx2x_get_warpcore_lane(struct bnx2x_phy *phy,
3299                                   struct link_params *params)
3300 {
3301         u8 lane = 0;
3302         struct bnx2x *bp = params->bp;
3303         u32 path_swap, path_swap_ovr;
3304         u8 path, port;
3305
3306         path = BP_PATH(bp);
3307         port = params->port;
3308
3309         if (bnx2x_is_4_port_mode(bp)) {
3310                 u32 port_swap, port_swap_ovr;
3311
3312                 /* Figure out path swap value */
3313                 path_swap_ovr = REG_RD(bp, MISC_REG_FOUR_PORT_PATH_SWAP_OVWR);
3314                 if (path_swap_ovr & 0x1)
3315                         path_swap = (path_swap_ovr & 0x2);
3316                 else
3317                         path_swap = REG_RD(bp, MISC_REG_FOUR_PORT_PATH_SWAP);
3318
3319                 if (path_swap)
3320                         path = path ^ 1;
3321
3322                 /* Figure out port swap value */
3323                 port_swap_ovr = REG_RD(bp, MISC_REG_FOUR_PORT_PORT_SWAP_OVWR);
3324                 if (port_swap_ovr & 0x1)
3325                         port_swap = (port_swap_ovr & 0x2);
3326                 else
3327                         port_swap = REG_RD(bp, MISC_REG_FOUR_PORT_PORT_SWAP);
3328
3329                 if (port_swap)
3330                         port = port ^ 1;
3331
3332                 lane = (port<<1) + path;
3333         } else { /* two port mode - no port swap */
3334
3335                 /* Figure out path swap value */
3336                 path_swap_ovr =
3337                         REG_RD(bp, MISC_REG_TWO_PORT_PATH_SWAP_OVWR);
3338                 if (path_swap_ovr & 0x1) {
3339                         path_swap = (path_swap_ovr & 0x2);
3340                 } else {
3341                         path_swap =
3342                                 REG_RD(bp, MISC_REG_TWO_PORT_PATH_SWAP);
3343                 }
3344                 if (path_swap)
3345                         path = path ^ 1;
3346
3347                 lane = path << 1 ;
3348         }
3349         return lane;
3350 }
3351
3352 static void bnx2x_set_aer_mmd(struct link_params *params,
3353                               struct bnx2x_phy *phy)
3354 {
3355         u32 ser_lane;
3356         u16 offset, aer_val;
3357         struct bnx2x *bp = params->bp;
3358         ser_lane = ((params->lane_config &
3359                      PORT_HW_CFG_LANE_SWAP_CFG_MASTER_MASK) >>
3360                      PORT_HW_CFG_LANE_SWAP_CFG_MASTER_SHIFT);
3361
3362         offset = (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT) ?
3363                 (phy->addr + ser_lane) : 0;
3364
3365         if (USES_WARPCORE(bp)) {
3366                 aer_val = bnx2x_get_warpcore_lane(phy, params);
3367                 /* In Dual-lane mode, two lanes are joined together,
3368                  * so in order to configure them, the AER broadcast method is
3369                  * used here.
3370                  * 0x200 is the broadcast address for lanes 0,1
3371                  * 0x201 is the broadcast address for lanes 2,3
3372                  */
3373                 if (phy->flags & FLAGS_WC_DUAL_MODE)
3374                         aer_val = (aer_val >> 1) | 0x200;
3375         } else if (CHIP_IS_E2(bp))
3376                 aer_val = 0x3800 + offset - 1;
3377         else
3378                 aer_val = 0x3800 + offset;
3379
3380         CL22_WR_OVER_CL45(bp, phy, MDIO_REG_BANK_AER_BLOCK,
3381                           MDIO_AER_BLOCK_AER_REG, aer_val);
3382
3383 }
3384
3385 /******************************************************************/
3386 /*                      Internal phy section                      */
3387 /******************************************************************/
3388
3389 static void bnx2x_set_serdes_access(struct bnx2x *bp, u8 port)
3390 {
3391         u32 emac_base = (port) ? GRCBASE_EMAC1 : GRCBASE_EMAC0;
3392
3393         /* Set Clause 22 */
3394         REG_WR(bp, NIG_REG_SERDES0_CTRL_MD_ST + port*0x10, 1);
3395         REG_WR(bp, emac_base + EMAC_REG_EMAC_MDIO_COMM, 0x245f8000);
3396         udelay(500);
3397         REG_WR(bp, emac_base + EMAC_REG_EMAC_MDIO_COMM, 0x245d000f);
3398         udelay(500);
3399          /* Set Clause 45 */
3400         REG_WR(bp, NIG_REG_SERDES0_CTRL_MD_ST + port*0x10, 0);
3401 }
3402
3403 static void bnx2x_serdes_deassert(struct bnx2x *bp, u8 port)
3404 {
3405         u32 val;
3406
3407         DP(NETIF_MSG_LINK, "bnx2x_serdes_deassert\n");
3408
3409         val = SERDES_RESET_BITS << (port*16);
3410
3411         /* reset and unreset the SerDes/XGXS */
3412         REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_3_CLEAR, val);
3413         udelay(500);
3414         REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_3_SET, val);
3415
3416         bnx2x_set_serdes_access(bp, port);
3417
3418         REG_WR(bp, NIG_REG_SERDES0_CTRL_MD_DEVAD + port*0x10,
3419                DEFAULT_PHY_DEV_ADDR);
3420 }
3421
3422 static void bnx2x_xgxs_deassert(struct link_params *params)
3423 {
3424         struct bnx2x *bp = params->bp;
3425         u8 port;
3426         u32 val;
3427         DP(NETIF_MSG_LINK, "bnx2x_xgxs_deassert\n");
3428         port = params->port;
3429
3430         val = XGXS_RESET_BITS << (port*16);
3431
3432         /* reset and unreset the SerDes/XGXS */
3433         REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_3_CLEAR, val);
3434         udelay(500);
3435         REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_3_SET, val);
3436
3437         REG_WR(bp, NIG_REG_XGXS0_CTRL_MD_ST + port*0x18, 0);
3438         REG_WR(bp, NIG_REG_XGXS0_CTRL_MD_DEVAD + port*0x18,
3439                params->phy[INT_PHY].def_md_devad);
3440 }
3441
3442 static void bnx2x_calc_ieee_aneg_adv(struct bnx2x_phy *phy,
3443                                      struct link_params *params, u16 *ieee_fc)
3444 {
3445         struct bnx2x *bp = params->bp;
3446         *ieee_fc = MDIO_COMBO_IEEE0_AUTO_NEG_ADV_FULL_DUPLEX;
3447         /* Resolve pause mode and advertisement Please refer to Table
3448          * 28B-3 of the 802.3ab-1999 spec
3449          */
3450
3451         switch (phy->req_flow_ctrl) {
3452         case BNX2X_FLOW_CTRL_AUTO:
3453                 if (params->req_fc_auto_adv == BNX2X_FLOW_CTRL_BOTH)
3454                         *ieee_fc |= MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH;
3455                 else
3456                         *ieee_fc |=
3457                         MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC;
3458                 break;
3459
3460         case BNX2X_FLOW_CTRL_TX:
3461                 *ieee_fc |= MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC;
3462                 break;
3463
3464         case BNX2X_FLOW_CTRL_RX:
3465         case BNX2X_FLOW_CTRL_BOTH:
3466                 *ieee_fc |= MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH;
3467                 break;
3468
3469         case BNX2X_FLOW_CTRL_NONE:
3470         default:
3471                 *ieee_fc |= MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_NONE;
3472                 break;
3473         }
3474         DP(NETIF_MSG_LINK, "ieee_fc = 0x%x\n", *ieee_fc);
3475 }
3476
3477 static void set_phy_vars(struct link_params *params,
3478                          struct link_vars *vars)
3479 {
3480         struct bnx2x *bp = params->bp;
3481         u8 actual_phy_idx, phy_index, link_cfg_idx;
3482         u8 phy_config_swapped = params->multi_phy_config &
3483                         PORT_HW_CFG_PHY_SWAPPED_ENABLED;
3484         for (phy_index = INT_PHY; phy_index < params->num_phys;
3485               phy_index++) {
3486                 link_cfg_idx = LINK_CONFIG_IDX(phy_index);
3487                 actual_phy_idx = phy_index;
3488                 if (phy_config_swapped) {
3489                         if (phy_index == EXT_PHY1)
3490                                 actual_phy_idx = EXT_PHY2;
3491                         else if (phy_index == EXT_PHY2)
3492                                 actual_phy_idx = EXT_PHY1;
3493                 }
3494                 params->phy[actual_phy_idx].req_flow_ctrl =
3495                         params->req_flow_ctrl[link_cfg_idx];
3496
3497                 params->phy[actual_phy_idx].req_line_speed =
3498                         params->req_line_speed[link_cfg_idx];
3499
3500                 params->phy[actual_phy_idx].speed_cap_mask =
3501                         params->speed_cap_mask[link_cfg_idx];
3502
3503                 params->phy[actual_phy_idx].req_duplex =
3504                         params->req_duplex[link_cfg_idx];
3505
3506                 if (params->req_line_speed[link_cfg_idx] ==
3507                     SPEED_AUTO_NEG)
3508                         vars->link_status |= LINK_STATUS_AUTO_NEGOTIATE_ENABLED;
3509
3510                 DP(NETIF_MSG_LINK, "req_flow_ctrl %x, req_line_speed %x,"
3511                            " speed_cap_mask %x\n",
3512                            params->phy[actual_phy_idx].req_flow_ctrl,
3513                            params->phy[actual_phy_idx].req_line_speed,
3514                            params->phy[actual_phy_idx].speed_cap_mask);
3515         }
3516 }
3517
3518 static void bnx2x_ext_phy_set_pause(struct link_params *params,
3519                                     struct bnx2x_phy *phy,
3520                                     struct link_vars *vars)
3521 {
3522         u16 val;
3523         struct bnx2x *bp = params->bp;
3524         /* read modify write pause advertizing */
3525         bnx2x_cl45_read(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_ADV_PAUSE, &val);
3526
3527         val &= ~MDIO_AN_REG_ADV_PAUSE_BOTH;
3528
3529         /* Please refer to Table 28B-3 of 802.3ab-1999 spec. */
3530         bnx2x_calc_ieee_aneg_adv(phy, params, &vars->ieee_fc);
3531         if ((vars->ieee_fc &
3532             MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC) ==
3533             MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC) {
3534                 val |= MDIO_AN_REG_ADV_PAUSE_ASYMMETRIC;
3535         }
3536         if ((vars->ieee_fc &
3537             MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH) ==
3538             MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH) {
3539                 val |= MDIO_AN_REG_ADV_PAUSE_PAUSE;
3540         }
3541         DP(NETIF_MSG_LINK, "Ext phy AN advertize 0x%x\n", val);
3542         bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_ADV_PAUSE, val);
3543 }
3544
3545 static void bnx2x_pause_resolve(struct link_vars *vars, u32 pause_result)
3546 {                                               /*  LD      LP   */
3547         switch (pause_result) {                 /* ASYM P ASYM P */
3548         case 0xb:                               /*   1  0   1  1 */
3549                 vars->flow_ctrl = BNX2X_FLOW_CTRL_TX;
3550                 break;
3551
3552         case 0xe:                               /*   1  1   1  0 */
3553                 vars->flow_ctrl = BNX2X_FLOW_CTRL_RX;
3554                 break;
3555
3556         case 0x5:                               /*   0  1   0  1 */
3557         case 0x7:                               /*   0  1   1  1 */
3558         case 0xd:                               /*   1  1   0  1 */
3559         case 0xf:                               /*   1  1   1  1 */
3560                 vars->flow_ctrl = BNX2X_FLOW_CTRL_BOTH;
3561                 break;
3562
3563         default:
3564                 break;
3565         }
3566         if (pause_result & (1<<0))
3567                 vars->link_status |= LINK_STATUS_LINK_PARTNER_SYMMETRIC_PAUSE;
3568         if (pause_result & (1<<1))
3569                 vars->link_status |= LINK_STATUS_LINK_PARTNER_ASYMMETRIC_PAUSE;
3570
3571 }
3572
3573 static void bnx2x_ext_phy_update_adv_fc(struct bnx2x_phy *phy,
3574                                         struct link_params *params,
3575                                         struct link_vars *vars)
3576 {
3577         u16 ld_pause;           /* local */
3578         u16 lp_pause;           /* link partner */
3579         u16 pause_result;
3580         struct bnx2x *bp = params->bp;
3581         if (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM54618SE) {
3582                 bnx2x_cl22_read(bp, phy, 0x4, &ld_pause);
3583                 bnx2x_cl22_read(bp, phy, 0x5, &lp_pause);
3584         } else if (CHIP_IS_E3(bp) &&
3585                 SINGLE_MEDIA_DIRECT(params)) {
3586                 u8 lane = bnx2x_get_warpcore_lane(phy, params);
3587                 u16 gp_status, gp_mask;
3588                 bnx2x_cl45_read(bp, phy,
3589                                 MDIO_AN_DEVAD, MDIO_WC_REG_GP2_STATUS_GP_2_4,
3590                                 &gp_status);
3591                 gp_mask = (MDIO_WC_REG_GP2_STATUS_GP_2_4_CL73_AN_CMPL |
3592                            MDIO_WC_REG_GP2_STATUS_GP_2_4_CL37_LP_AN_CAP) <<
3593                         lane;
3594                 if ((gp_status & gp_mask) == gp_mask) {
3595                         bnx2x_cl45_read(bp, phy, MDIO_AN_DEVAD,
3596                                         MDIO_AN_REG_ADV_PAUSE, &ld_pause);
3597                         bnx2x_cl45_read(bp, phy, MDIO_AN_DEVAD,
3598                                         MDIO_AN_REG_LP_AUTO_NEG, &lp_pause);
3599                 } else {
3600                         bnx2x_cl45_read(bp, phy, MDIO_AN_DEVAD,
3601                                         MDIO_AN_REG_CL37_FC_LD, &ld_pause);
3602                         bnx2x_cl45_read(bp, phy, MDIO_AN_DEVAD,
3603                                         MDIO_AN_REG_CL37_FC_LP, &lp_pause);
3604                         ld_pause = ((ld_pause &
3605                                      MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH)
3606                                     << 3);
3607                         lp_pause = ((lp_pause &
3608                                      MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH)
3609                                     << 3);
3610                 }
3611         } else {
3612                 bnx2x_cl45_read(bp, phy,
3613                                 MDIO_AN_DEVAD,
3614                                 MDIO_AN_REG_ADV_PAUSE, &ld_pause);
3615                 bnx2x_cl45_read(bp, phy,
3616                                 MDIO_AN_DEVAD,
3617                                 MDIO_AN_REG_LP_AUTO_NEG, &lp_pause);
3618         }
3619         pause_result = (ld_pause &
3620                         MDIO_AN_REG_ADV_PAUSE_MASK) >> 8;
3621         pause_result |= (lp_pause &
3622                          MDIO_AN_REG_ADV_PAUSE_MASK) >> 10;
3623         DP(NETIF_MSG_LINK, "Ext PHY pause result 0x%x\n", pause_result);
3624         bnx2x_pause_resolve(vars, pause_result);
3625
3626 }
3627
3628 static u8 bnx2x_ext_phy_resolve_fc(struct bnx2x_phy *phy,
3629                                    struct link_params *params,
3630                                    struct link_vars *vars)
3631 {
3632         u8 ret = 0;
3633         vars->flow_ctrl = BNX2X_FLOW_CTRL_NONE;
3634         if (phy->req_flow_ctrl != BNX2X_FLOW_CTRL_AUTO) {
3635                 /* Update the advertised flow-controled of LD/LP in AN */
3636                 if (phy->req_line_speed == SPEED_AUTO_NEG)
3637                         bnx2x_ext_phy_update_adv_fc(phy, params, vars);
3638                 /* But set the flow-control result as the requested one */
3639                 vars->flow_ctrl = phy->req_flow_ctrl;
3640         } else if (phy->req_line_speed != SPEED_AUTO_NEG)
3641                 vars->flow_ctrl = params->req_fc_auto_adv;
3642         else if (vars->link_status & LINK_STATUS_AUTO_NEGOTIATE_COMPLETE) {
3643                 ret = 1;
3644                 bnx2x_ext_phy_update_adv_fc(phy, params, vars);
3645         }
3646         return ret;
3647 }
3648 /******************************************************************/
3649 /*                      Warpcore section                          */
3650 /******************************************************************/
3651 /* The init_internal_warpcore should mirror the xgxs,
3652  * i.e. reset the lane (if needed), set aer for the
3653  * init configuration, and set/clear SGMII flag. Internal
3654  * phy init is done purely in phy_init stage.
3655  */
3656 static void bnx2x_warpcore_enable_AN_KR(struct bnx2x_phy *phy,
3657                                         struct link_params *params,
3658                                         struct link_vars *vars) {
3659         u16 val16 = 0, lane, bam37 = 0;
3660         struct bnx2x *bp = params->bp;
3661         DP(NETIF_MSG_LINK, "Enable Auto Negotiation for KR\n");
3662         /* Set to default registers that may be overriden by 10G force */
3663         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3664                          MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X2, 0x7);
3665         bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD,
3666                          MDIO_WC_REG_PAR_DET_10G_CTRL, 0);
3667         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3668                          MDIO_WC_REG_CL72_USERB0_CL72_MISC1_CONTROL, 0);
3669         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3670                         MDIO_WC_REG_XGXSBLK1_LANECTRL0, 0xff);
3671         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3672                         MDIO_WC_REG_XGXSBLK1_LANECTRL1, 0x5555);
3673         bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD,
3674                          MDIO_WC_REG_IEEE0BLK_AUTONEGNP, 0x0);
3675         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3676                          MDIO_WC_REG_RX66_CONTROL, 0x7415);
3677         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3678                          MDIO_WC_REG_SERDESDIGITAL_MISC2, 0x6190);
3679         /* Disable Autoneg: re-enable it after adv is done. */
3680         bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD,
3681                          MDIO_WC_REG_IEEE0BLK_MIICNTL, 0);
3682
3683         /* Check adding advertisement for 1G KX */
3684         if (((vars->line_speed == SPEED_AUTO_NEG) &&
3685              (phy->speed_cap_mask & PORT_HW_CFG_SPEED_CAPABILITY_D0_1G)) ||
3686             (vars->line_speed == SPEED_1000)) {
3687                 u16 sd_digital;
3688                 val16 |= (1<<5);
3689
3690                 /* Enable CL37 1G Parallel Detect */
3691                 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
3692                         MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X2, &sd_digital);
3693                 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3694                          MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X2,
3695                                  (sd_digital | 0x1));
3696
3697                 DP(NETIF_MSG_LINK, "Advertize 1G\n");
3698         }
3699         if (((vars->line_speed == SPEED_AUTO_NEG) &&
3700              (phy->speed_cap_mask & PORT_HW_CFG_SPEED_CAPABILITY_D0_10G)) ||
3701             (vars->line_speed ==  SPEED_10000)) {
3702                 /* Check adding advertisement for 10G KR */
3703                 val16 |= (1<<7);
3704                 /* Enable 10G Parallel Detect */
3705                 bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD,
3706                                 MDIO_WC_REG_PAR_DET_10G_CTRL, 1);
3707
3708                 DP(NETIF_MSG_LINK, "Advertize 10G\n");
3709         }
3710
3711         /* Set Transmit PMD settings */
3712         lane = bnx2x_get_warpcore_lane(phy, params);
3713         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3714                       MDIO_WC_REG_TX0_TX_DRIVER + 0x10*lane,
3715                      ((0x02 << MDIO_WC_REG_TX0_TX_DRIVER_POST2_COEFF_OFFSET) |
3716                       (0x06 << MDIO_WC_REG_TX0_TX_DRIVER_IDRIVER_OFFSET) |
3717                       (0x09 << MDIO_WC_REG_TX0_TX_DRIVER_IPRE_DRIVER_OFFSET)));
3718         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3719                          MDIO_WC_REG_CL72_USERB0_CL72_OS_DEF_CTRL,
3720                          0x03f0);
3721         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3722                          MDIO_WC_REG_CL72_USERB0_CL72_2P5_DEF_CTRL,
3723                          0x03f0);
3724
3725         /* Advertised speeds */
3726         bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD,
3727                          MDIO_WC_REG_AN_IEEE1BLK_AN_ADVERTISEMENT1, val16);
3728
3729         /* Advertised and set FEC (Forward Error Correction) */
3730         bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD,
3731                          MDIO_WC_REG_AN_IEEE1BLK_AN_ADVERTISEMENT2,
3732                          (MDIO_WC_REG_AN_IEEE1BLK_AN_ADV2_FEC_ABILITY |
3733                           MDIO_WC_REG_AN_IEEE1BLK_AN_ADV2_FEC_REQ));
3734
3735         /* Enable CL37 BAM */
3736         if (REG_RD(bp, params->shmem_base +
3737                    offsetof(struct shmem_region, dev_info.
3738                             port_hw_config[params->port].default_cfg)) &
3739             PORT_HW_CFG_ENABLE_BAM_ON_KR_ENABLED) {
3740                 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
3741                                 MDIO_WC_REG_DIGITAL6_MP5_NEXTPAGECTRL, &bam37);
3742                 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3743                         MDIO_WC_REG_DIGITAL6_MP5_NEXTPAGECTRL, bam37 | 1);
3744                 DP(NETIF_MSG_LINK, "Enable CL37 BAM on KR\n");
3745         }
3746
3747         /* Advertise pause */
3748         bnx2x_ext_phy_set_pause(params, phy, vars);
3749         /* Set KR Autoneg Work-Around flag for Warpcore version older than D108
3750          */
3751         bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
3752                         MDIO_WC_REG_UC_INFO_B1_VERSION, &val16);
3753         if (val16 < 0xd108) {
3754                 DP(NETIF_MSG_LINK, "Enable AN KR work-around\n");
3755                 vars->rx_tx_asic_rst = MAX_KR_LINK_RETRY;
3756         }
3757         bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
3758                         MDIO_WC_REG_DIGITAL5_MISC7, &val16);
3759
3760         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3761                          MDIO_WC_REG_DIGITAL5_MISC7, val16 | 0x100);
3762
3763         /* Over 1G - AN local device user page 1 */
3764         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3765                         MDIO_WC_REG_DIGITAL3_UP1, 0x1f);
3766
3767         /* Enable Autoneg */
3768         bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD,
3769                          MDIO_WC_REG_IEEE0BLK_MIICNTL, 0x1200);
3770
3771 }
3772
3773 static void bnx2x_warpcore_set_10G_KR(struct bnx2x_phy *phy,
3774                                       struct link_params *params,
3775                                       struct link_vars *vars)
3776 {
3777         struct bnx2x *bp = params->bp;
3778         u16 val;
3779
3780         /* Disable Autoneg */
3781         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3782                          MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X2, 0x7);
3783
3784         bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD,
3785                          MDIO_WC_REG_PAR_DET_10G_CTRL, 0);
3786
3787         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3788                          MDIO_WC_REG_CL72_USERB0_CL72_MISC1_CONTROL, 0x3f00);
3789
3790         bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD,
3791                          MDIO_WC_REG_AN_IEEE1BLK_AN_ADVERTISEMENT1, 0);
3792
3793         bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD,
3794                          MDIO_WC_REG_IEEE0BLK_MIICNTL, 0x0);
3795
3796         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3797                         MDIO_WC_REG_DIGITAL3_UP1, 0x1);
3798
3799         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3800                          MDIO_WC_REG_DIGITAL5_MISC7, 0xa);
3801
3802         /* Disable CL36 PCS Tx */
3803         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3804                         MDIO_WC_REG_XGXSBLK1_LANECTRL0, 0x0);
3805
3806         /* Double Wide Single Data Rate @ pll rate */
3807         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3808                         MDIO_WC_REG_XGXSBLK1_LANECTRL1, 0xFFFF);
3809
3810         /* Leave cl72 training enable, needed for KR */
3811         bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD,
3812                 MDIO_WC_REG_PMD_IEEE9BLK_TENGBASE_KR_PMD_CONTROL_REGISTER_150,
3813                 0x2);
3814
3815         /* Leave CL72 enabled */
3816         bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
3817                          MDIO_WC_REG_CL72_USERB0_CL72_MISC1_CONTROL,
3818                          &val);
3819         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3820                          MDIO_WC_REG_CL72_USERB0_CL72_MISC1_CONTROL,
3821                          val | 0x3800);
3822
3823         /* Set speed via PMA/PMD register */
3824         bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD,
3825                          MDIO_WC_REG_IEEE0BLK_MIICNTL, 0x2040);
3826
3827         bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD,
3828                          MDIO_WC_REG_IEEE0BLK_AUTONEGNP, 0xB);
3829
3830         /* Enable encoded forced speed */
3831         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3832                          MDIO_WC_REG_SERDESDIGITAL_MISC2, 0x30);
3833
3834         /* Turn TX scramble payload only the 64/66 scrambler */
3835         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3836                          MDIO_WC_REG_TX66_CONTROL, 0x9);
3837
3838         /* Turn RX scramble payload only the 64/66 scrambler */
3839         bnx2x_cl45_read_or_write(bp, phy, MDIO_WC_DEVAD,
3840                                  MDIO_WC_REG_RX66_CONTROL, 0xF9);
3841
3842         /* set and clear loopback to cause a reset to 64/66 decoder */
3843         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3844                          MDIO_WC_REG_IEEE0BLK_MIICNTL, 0x4000);
3845         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3846                          MDIO_WC_REG_IEEE0BLK_MIICNTL, 0x0);
3847
3848 }
3849
3850 static void bnx2x_warpcore_set_10G_XFI(struct bnx2x_phy *phy,
3851                                        struct link_params *params,
3852                                        u8 is_xfi)
3853 {
3854         struct bnx2x *bp = params->bp;
3855         u16 misc1_val, tap_val, tx_driver_val, lane, val;
3856         /* Hold rxSeqStart */
3857         bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
3858                         MDIO_WC_REG_DSC2B0_DSC_MISC_CTRL0, &val);
3859         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3860                          MDIO_WC_REG_DSC2B0_DSC_MISC_CTRL0, (val | 0x8000));
3861
3862         /* Hold tx_fifo_reset */
3863         bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
3864                         MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X3, &val);
3865         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3866                          MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X3, (val | 0x1));
3867
3868         /* Disable CL73 AN */
3869         bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_CTRL, 0);
3870
3871         /* Disable 100FX Enable and Auto-Detect */
3872         bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
3873                         MDIO_WC_REG_FX100_CTRL1, &val);
3874         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3875                          MDIO_WC_REG_FX100_CTRL1, (val & 0xFFFA));
3876
3877         /* Disable 100FX Idle detect */
3878         bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
3879                         MDIO_WC_REG_FX100_CTRL3, &val);
3880         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3881                          MDIO_WC_REG_FX100_CTRL3, (val | 0x0080));
3882
3883         /* Set Block address to Remote PHY & Clear forced_speed[5] */
3884         bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
3885                         MDIO_WC_REG_DIGITAL4_MISC3, &val);
3886         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3887                          MDIO_WC_REG_DIGITAL4_MISC3, (val & 0xFF7F));
3888
3889         /* Turn off auto-detect & fiber mode */
3890         bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
3891                         MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X1, &val);
3892         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3893                          MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X1,
3894                          (val & 0xFFEE));
3895
3896         /* Set filter_force_link, disable_false_link and parallel_detect */
3897         bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
3898                         MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X2, &val);
3899         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3900                          MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X2,
3901                          ((val | 0x0006) & 0xFFFE));
3902
3903         /* Set XFI / SFI */
3904         bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
3905                         MDIO_WC_REG_SERDESDIGITAL_MISC1, &misc1_val);
3906
3907         misc1_val &= ~(0x1f);
3908
3909         if (is_xfi) {
3910                 misc1_val |= 0x5;
3911                 tap_val = ((0x08 << MDIO_WC_REG_TX_FIR_TAP_POST_TAP_OFFSET) |
3912                            (0x37 << MDIO_WC_REG_TX_FIR_TAP_MAIN_TAP_OFFSET) |
3913                            (0x00 << MDIO_WC_REG_TX_FIR_TAP_PRE_TAP_OFFSET));
3914                 tx_driver_val =
3915                       ((0x00 << MDIO_WC_REG_TX0_TX_DRIVER_POST2_COEFF_OFFSET) |
3916                        (0x02 << MDIO_WC_REG_TX0_TX_DRIVER_IDRIVER_OFFSET) |
3917                        (0x03 << MDIO_WC_REG_TX0_TX_DRIVER_IPRE_DRIVER_OFFSET));
3918
3919         } else {
3920                 misc1_val |= 0x9;
3921                 tap_val = ((0x0f << MDIO_WC_REG_TX_FIR_TAP_POST_TAP_OFFSET) |
3922                            (0x2b << MDIO_WC_REG_TX_FIR_TAP_MAIN_TAP_OFFSET) |
3923                            (0x02 << MDIO_WC_REG_TX_FIR_TAP_PRE_TAP_OFFSET));
3924                 tx_driver_val =
3925                       ((0x03 << MDIO_WC_REG_TX0_TX_DRIVER_POST2_COEFF_OFFSET) |
3926                        (0x02 << MDIO_WC_REG_TX0_TX_DRIVER_IDRIVER_OFFSET) |
3927                        (0x06 << MDIO_WC_REG_TX0_TX_DRIVER_IPRE_DRIVER_OFFSET));
3928         }
3929         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3930                          MDIO_WC_REG_SERDESDIGITAL_MISC1, misc1_val);
3931
3932         /* Set Transmit PMD settings */
3933         lane = bnx2x_get_warpcore_lane(phy, params);
3934         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3935                          MDIO_WC_REG_TX_FIR_TAP,
3936                          tap_val | MDIO_WC_REG_TX_FIR_TAP_ENABLE);
3937         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3938                          MDIO_WC_REG_TX0_TX_DRIVER + 0x10*lane,
3939                          tx_driver_val);
3940
3941         /* Enable fiber mode, enable and invert sig_det */
3942         bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
3943                         MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X1, &val);
3944         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3945                          MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X1, val | 0xd);
3946
3947         /* Set Block address to Remote PHY & Set forced_speed[5], 40bit mode */
3948         bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
3949                         MDIO_WC_REG_DIGITAL4_MISC3, &val);
3950         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3951                          MDIO_WC_REG_DIGITAL4_MISC3, val | 0x8080);
3952
3953         /* 10G XFI Full Duplex */
3954         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3955                          MDIO_WC_REG_IEEE0BLK_MIICNTL, 0x100);
3956
3957         /* Release tx_fifo_reset */
3958         bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
3959                         MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X3, &val);
3960         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3961                          MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X3, val & 0xFFFE);
3962
3963         /* Release rxSeqStart */
3964         bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
3965                         MDIO_WC_REG_DSC2B0_DSC_MISC_CTRL0, &val);
3966         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3967                          MDIO_WC_REG_DSC2B0_DSC_MISC_CTRL0, (val & 0x7FFF));
3968 }
3969
3970 static void bnx2x_warpcore_set_20G_KR2(struct bnx2x *bp,
3971                                        struct bnx2x_phy *phy)
3972 {
3973         DP(NETIF_MSG_LINK, "KR2 still not supported !!!\n");
3974 }
3975
3976 static void bnx2x_warpcore_set_20G_DXGXS(struct bnx2x *bp,
3977                                          struct bnx2x_phy *phy,
3978                                          u16 lane)
3979 {
3980         /* Rx0 anaRxControl1G */
3981         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3982                          MDIO_WC_REG_RX0_ANARXCONTROL1G, 0x90);
3983
3984         /* Rx2 anaRxControl1G */
3985         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3986                          MDIO_WC_REG_RX2_ANARXCONTROL1G, 0x90);
3987
3988         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3989                          MDIO_WC_REG_RX66_SCW0, 0xE070);
3990
3991         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3992                          MDIO_WC_REG_RX66_SCW1, 0xC0D0);
3993
3994         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3995                          MDIO_WC_REG_RX66_SCW2, 0xA0B0);
3996
3997         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3998                          MDIO_WC_REG_RX66_SCW3, 0x8090);
3999
4000         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4001                          MDIO_WC_REG_RX66_SCW0_MASK, 0xF0F0);
4002
4003         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4004                          MDIO_WC_REG_RX66_SCW1_MASK, 0xF0F0);
4005
4006         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4007                          MDIO_WC_REG_RX66_SCW2_MASK, 0xF0F0);
4008
4009         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4010                          MDIO_WC_REG_RX66_SCW3_MASK, 0xF0F0);
4011
4012         /* Serdes Digital Misc1 */
4013         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4014                          MDIO_WC_REG_SERDESDIGITAL_MISC1, 0x6008);
4015
4016         /* Serdes Digital4 Misc3 */
4017         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4018                          MDIO_WC_REG_DIGITAL4_MISC3, 0x8088);
4019
4020         /* Set Transmit PMD settings */
4021         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4022                          MDIO_WC_REG_TX_FIR_TAP,
4023                         ((0x12 << MDIO_WC_REG_TX_FIR_TAP_POST_TAP_OFFSET) |
4024                          (0x2d << MDIO_WC_REG_TX_FIR_TAP_MAIN_TAP_OFFSET) |
4025                          (0x00 << MDIO_WC_REG_TX_FIR_TAP_PRE_TAP_OFFSET) |
4026                          MDIO_WC_REG_TX_FIR_TAP_ENABLE));
4027         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4028                       MDIO_WC_REG_TX0_TX_DRIVER + 0x10*lane,
4029                      ((0x02 << MDIO_WC_REG_TX0_TX_DRIVER_POST2_COEFF_OFFSET) |
4030                       (0x02 << MDIO_WC_REG_TX0_TX_DRIVER_IDRIVER_OFFSET) |
4031                       (0x02 << MDIO_WC_REG_TX0_TX_DRIVER_IPRE_DRIVER_OFFSET)));
4032 }
4033
4034 static void bnx2x_warpcore_set_sgmii_speed(struct bnx2x_phy *phy,
4035                                            struct link_params *params,
4036                                            u8 fiber_mode,
4037                                            u8 always_autoneg)
4038 {
4039         struct bnx2x *bp = params->bp;
4040         u16 val16, digctrl_kx1, digctrl_kx2;
4041
4042         /* Clear XFI clock comp in non-10G single lane mode. */
4043         bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
4044                         MDIO_WC_REG_RX66_CONTROL, &val16);
4045         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4046                          MDIO_WC_REG_RX66_CONTROL, val16 & ~(3<<13));
4047
4048         if (always_autoneg || phy->req_line_speed == SPEED_AUTO_NEG) {
4049                 /* SGMII Autoneg */
4050                 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
4051                                 MDIO_WC_REG_COMBO_IEEE0_MIICTRL, &val16);
4052                 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4053                                  MDIO_WC_REG_COMBO_IEEE0_MIICTRL,
4054                                  val16 | 0x1000);
4055                 DP(NETIF_MSG_LINK, "set SGMII AUTONEG\n");
4056         } else {
4057                 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
4058                                 MDIO_WC_REG_COMBO_IEEE0_MIICTRL, &val16);
4059                 val16 &= 0xcebf;
4060                 switch (phy->req_line_speed) {
4061                 case SPEED_10:
4062                         break;
4063                 case SPEED_100:
4064                         val16 |= 0x2000;
4065                         break;
4066                 case SPEED_1000:
4067                         val16 |= 0x0040;
4068                         break;
4069                 default:
4070                         DP(NETIF_MSG_LINK,
4071                            "Speed not supported: 0x%x\n", phy->req_line_speed);
4072                         return;
4073                 }
4074
4075                 if (phy->req_duplex == DUPLEX_FULL)
4076                         val16 |= 0x0100;
4077
4078                 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4079                                 MDIO_WC_REG_COMBO_IEEE0_MIICTRL, val16);
4080
4081                 DP(NETIF_MSG_LINK, "set SGMII force speed %d\n",
4082                                phy->req_line_speed);
4083                 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
4084                                 MDIO_WC_REG_COMBO_IEEE0_MIICTRL, &val16);
4085                 DP(NETIF_MSG_LINK, "  (readback) %x\n", val16);
4086         }
4087
4088         /* SGMII Slave mode and disable signal detect */
4089         bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
4090                         MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X1, &digctrl_kx1);
4091         if (fiber_mode)
4092                 digctrl_kx1 = 1;
4093         else
4094                 digctrl_kx1 &= 0xff4a;
4095
4096         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4097                         MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X1,
4098                         digctrl_kx1);
4099
4100         /* Turn off parallel detect */
4101         bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
4102                         MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X2, &digctrl_kx2);
4103         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4104                         MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X2,
4105                         (digctrl_kx2 & ~(1<<2)));
4106
4107         /* Re-enable parallel detect */
4108         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4109                         MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X2,
4110                         (digctrl_kx2 | (1<<2)));
4111
4112         /* Enable autodet */
4113         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4114                         MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X1,
4115                         (digctrl_kx1 | 0x10));
4116 }
4117
4118 static void bnx2x_warpcore_reset_lane(struct bnx2x *bp,
4119                                       struct bnx2x_phy *phy,
4120                                       u8 reset)
4121 {
4122         u16 val;
4123         /* Take lane out of reset after configuration is finished */
4124         bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
4125                         MDIO_WC_REG_DIGITAL5_MISC6, &val);
4126         if (reset)
4127                 val |= 0xC000;
4128         else
4129                 val &= 0x3FFF;
4130         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4131                          MDIO_WC_REG_DIGITAL5_MISC6, val);
4132         bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
4133                          MDIO_WC_REG_DIGITAL5_MISC6, &val);
4134 }
4135 /* Clear SFI/XFI link settings registers */
4136 static void bnx2x_warpcore_clear_regs(struct bnx2x_phy *phy,
4137                                       struct link_params *params,
4138                                       u16 lane)
4139 {
4140         struct bnx2x *bp = params->bp;
4141         u16 val16;
4142
4143         /* Set XFI clock comp as default. */
4144         bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
4145                         MDIO_WC_REG_RX66_CONTROL, &val16);
4146         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4147                          MDIO_WC_REG_RX66_CONTROL, val16 | (3<<13));
4148
4149         bnx2x_warpcore_reset_lane(bp, phy, 1);
4150         bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_CTRL, 0);
4151         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4152                          MDIO_WC_REG_FX100_CTRL1, 0x014a);
4153         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4154                          MDIO_WC_REG_FX100_CTRL3, 0x0800);
4155         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4156                          MDIO_WC_REG_DIGITAL4_MISC3, 0x8008);
4157         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4158                          MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X1, 0x0195);
4159         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4160                          MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X2, 0x0007);
4161         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4162                          MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X3, 0x0002);
4163         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4164                          MDIO_WC_REG_SERDESDIGITAL_MISC1, 0x6000);
4165         lane = bnx2x_get_warpcore_lane(phy, params);
4166         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4167                          MDIO_WC_REG_TX_FIR_TAP, 0x0000);
4168         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4169                          MDIO_WC_REG_TX0_TX_DRIVER + 0x10*lane, 0x0990);
4170         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4171                          MDIO_WC_REG_IEEE0BLK_MIICNTL, 0x2040);
4172         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4173                          MDIO_WC_REG_COMBO_IEEE0_MIICTRL, 0x0140);
4174         bnx2x_warpcore_reset_lane(bp, phy, 0);
4175 }
4176
4177 static int bnx2x_get_mod_abs_int_cfg(struct bnx2x *bp,
4178                                                 u32 chip_id,
4179                                                 u32 shmem_base, u8 port,
4180                                                 u8 *gpio_num, u8 *gpio_port)
4181 {
4182         u32 cfg_pin;
4183         *gpio_num = 0;
4184         *gpio_port = 0;
4185         if (CHIP_IS_E3(bp)) {
4186                 cfg_pin = (REG_RD(bp, shmem_base +
4187                                 offsetof(struct shmem_region,
4188                                 dev_info.port_hw_config[port].e3_sfp_ctrl)) &
4189                                 PORT_HW_CFG_E3_MOD_ABS_MASK) >>
4190                                 PORT_HW_CFG_E3_MOD_ABS_SHIFT;
4191
4192                 /* Should not happen. This function called upon interrupt
4193                  * triggered by GPIO ( since EPIO can only generate interrupts
4194                  * to MCP).
4195                  * So if this function was called and none of the GPIOs was set,
4196                  * it means the shit hit the fan.
4197                  */
4198                 if ((cfg_pin < PIN_CFG_GPIO0_P0) ||
4199                     (cfg_pin > PIN_CFG_GPIO3_P1)) {
4200                         DP(NETIF_MSG_LINK,
4201                            "ERROR: Invalid cfg pin %x for module detect indication\n",
4202                            cfg_pin);
4203                         return -EINVAL;
4204                 }
4205
4206                 *gpio_num = (cfg_pin - PIN_CFG_GPIO0_P0) & 0x3;
4207                 *gpio_port = (cfg_pin - PIN_CFG_GPIO0_P0) >> 2;
4208         } else {
4209                 *gpio_num = MISC_REGISTERS_GPIO_3;
4210                 *gpio_port = port;
4211         }
4212         DP(NETIF_MSG_LINK, "MOD_ABS int GPIO%d_P%d\n", *gpio_num, *gpio_port);
4213         return 0;
4214 }
4215
4216 static int bnx2x_is_sfp_module_plugged(struct bnx2x_phy *phy,
4217                                        struct link_params *params)
4218 {
4219         struct bnx2x *bp = params->bp;
4220         u8 gpio_num, gpio_port;
4221         u32 gpio_val;
4222         if (bnx2x_get_mod_abs_int_cfg(bp, params->chip_id,
4223                                       params->shmem_base, params->port,
4224                                       &gpio_num, &gpio_port) != 0)
4225                 return 0;
4226         gpio_val = bnx2x_get_gpio(bp, gpio_num, gpio_port);
4227
4228         /* Call the handling function in case module is detected */
4229         if (gpio_val == 0)
4230                 return 1;
4231         else
4232                 return 0;
4233 }
4234 static int bnx2x_warpcore_get_sigdet(struct bnx2x_phy *phy,
4235                                         struct link_params *params)
4236 {
4237         u16 gp2_status_reg0, lane;
4238         struct bnx2x *bp = params->bp;
4239
4240         lane = bnx2x_get_warpcore_lane(phy, params);
4241
4242         bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD, MDIO_WC_REG_GP2_STATUS_GP_2_0,
4243                                  &gp2_status_reg0);
4244
4245         return (gp2_status_reg0 >> (8+lane)) & 0x1;
4246 }
4247
4248 static void bnx2x_warpcore_config_runtime(struct bnx2x_phy *phy,
4249                                        struct link_params *params,
4250                                        struct link_vars *vars)
4251 {
4252         struct bnx2x *bp = params->bp;
4253         u32 serdes_net_if;
4254         u16 gp_status1 = 0, lnkup = 0, lnkup_kr = 0;
4255         u16 lane = bnx2x_get_warpcore_lane(phy, params);
4256
4257         vars->turn_to_run_wc_rt = vars->turn_to_run_wc_rt ? 0 : 1;
4258
4259         if (!vars->turn_to_run_wc_rt)
4260                 return;
4261
4262         /* return if there is no link partner */
4263         if (!(bnx2x_warpcore_get_sigdet(phy, params))) {
4264                 DP(NETIF_MSG_LINK, "bnx2x_warpcore_get_sigdet false\n");
4265                 return;
4266         }
4267
4268         if (vars->rx_tx_asic_rst) {
4269                 serdes_net_if = (REG_RD(bp, params->shmem_base +
4270                                 offsetof(struct shmem_region, dev_info.
4271                                 port_hw_config[params->port].default_cfg)) &
4272                                 PORT_HW_CFG_NET_SERDES_IF_MASK);
4273
4274                 switch (serdes_net_if) {
4275                 case PORT_HW_CFG_NET_SERDES_IF_KR:
4276                         /* Do we get link yet? */
4277                         bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD, 0x81d1,
4278                                                                 &gp_status1);
4279                         lnkup = (gp_status1 >> (8+lane)) & 0x1;/* 1G */
4280                                 /*10G KR*/
4281                         lnkup_kr = (gp_status1 >> (12+lane)) & 0x1;
4282
4283                         DP(NETIF_MSG_LINK,
4284                                 "gp_status1 0x%x\n", gp_status1);
4285
4286                         if (lnkup_kr || lnkup) {
4287                                         vars->rx_tx_asic_rst = 0;
4288                                         DP(NETIF_MSG_LINK,
4289                                         "link up, rx_tx_asic_rst 0x%x\n",
4290                                         vars->rx_tx_asic_rst);
4291                         } else {
4292                                 /* Reset the lane to see if link comes up.*/
4293                                 bnx2x_warpcore_reset_lane(bp, phy, 1);
4294                                 bnx2x_warpcore_reset_lane(bp, phy, 0);
4295
4296                                 /* restart Autoneg */
4297                                 bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD,
4298                                         MDIO_WC_REG_IEEE0BLK_MIICNTL, 0x1200);
4299
4300                                 vars->rx_tx_asic_rst--;
4301                                 DP(NETIF_MSG_LINK, "0x%x retry left\n",
4302                                 vars->rx_tx_asic_rst);
4303                         }
4304                         break;
4305
4306                 default:
4307                         break;
4308                 }
4309
4310         } /*params->rx_tx_asic_rst*/
4311
4312 }
4313 static void bnx2x_warpcore_config_init(struct bnx2x_phy *phy,
4314                                        struct link_params *params,
4315                                        struct link_vars *vars)
4316 {
4317         struct bnx2x *bp = params->bp;
4318         u32 serdes_net_if;
4319         u8 fiber_mode;
4320         u16 lane = bnx2x_get_warpcore_lane(phy, params);
4321         serdes_net_if = (REG_RD(bp, params->shmem_base +
4322                          offsetof(struct shmem_region, dev_info.
4323                                   port_hw_config[params->port].default_cfg)) &
4324                          PORT_HW_CFG_NET_SERDES_IF_MASK);
4325         DP(NETIF_MSG_LINK, "Begin Warpcore init, link_speed %d, "
4326                            "serdes_net_if = 0x%x\n",
4327                        vars->line_speed, serdes_net_if);
4328         bnx2x_set_aer_mmd(params, phy);
4329
4330         vars->phy_flags |= PHY_XGXS_FLAG;
4331         if ((serdes_net_if == PORT_HW_CFG_NET_SERDES_IF_SGMII) ||
4332             (phy->req_line_speed &&
4333              ((phy->req_line_speed == SPEED_100) ||
4334               (phy->req_line_speed == SPEED_10)))) {
4335                 vars->phy_flags |= PHY_SGMII_FLAG;
4336                 DP(NETIF_MSG_LINK, "Setting SGMII mode\n");
4337                 bnx2x_warpcore_clear_regs(phy, params, lane);
4338                 bnx2x_warpcore_set_sgmii_speed(phy, params, 0, 1);
4339         } else {
4340                 switch (serdes_net_if) {
4341                 case PORT_HW_CFG_NET_SERDES_IF_KR:
4342                         /* Enable KR Auto Neg */
4343                         if (params->loopback_mode != LOOPBACK_EXT)
4344                                 bnx2x_warpcore_enable_AN_KR(phy, params, vars);
4345                         else {
4346                                 DP(NETIF_MSG_LINK, "Setting KR 10G-Force\n");
4347                                 bnx2x_warpcore_set_10G_KR(phy, params, vars);
4348                         }
4349                         break;
4350
4351                 case PORT_HW_CFG_NET_SERDES_IF_XFI:
4352                         bnx2x_warpcore_clear_regs(phy, params, lane);
4353                         if (vars->line_speed == SPEED_10000) {
4354                                 DP(NETIF_MSG_LINK, "Setting 10G XFI\n");
4355                                 bnx2x_warpcore_set_10G_XFI(phy, params, 1);
4356                         } else {
4357                                 if (SINGLE_MEDIA_DIRECT(params)) {
4358                                         DP(NETIF_MSG_LINK, "1G Fiber\n");
4359                                         fiber_mode = 1;
4360                                 } else {
4361                                         DP(NETIF_MSG_LINK, "10/100/1G SGMII\n");
4362                                         fiber_mode = 0;
4363                                 }
4364                                 bnx2x_warpcore_set_sgmii_speed(phy,
4365                                                                 params,
4366                                                                 fiber_mode,
4367                                                                 0);
4368                         }
4369
4370                         break;
4371
4372                 case PORT_HW_CFG_NET_SERDES_IF_SFI:
4373
4374                         bnx2x_warpcore_clear_regs(phy, params, lane);
4375                         if (vars->line_speed == SPEED_10000) {
4376                                 DP(NETIF_MSG_LINK, "Setting 10G SFI\n");
4377                                 bnx2x_warpcore_set_10G_XFI(phy, params, 0);
4378                         } else if (vars->line_speed == SPEED_1000) {
4379                                 DP(NETIF_MSG_LINK, "Setting 1G Fiber\n");
4380                                 bnx2x_warpcore_set_sgmii_speed(
4381                                                 phy, params, 1, 0);
4382                         }
4383                         /* Issue Module detection */
4384                         if (bnx2x_is_sfp_module_plugged(phy, params))
4385                                 bnx2x_sfp_module_detection(phy, params);
4386                         break;
4387
4388                 case PORT_HW_CFG_NET_SERDES_IF_DXGXS:
4389                         if (vars->line_speed != SPEED_20000) {
4390                                 DP(NETIF_MSG_LINK, "Speed not supported yet\n");
4391                                 return;
4392                         }
4393                         DP(NETIF_MSG_LINK, "Setting 20G DXGXS\n");
4394                         bnx2x_warpcore_set_20G_DXGXS(bp, phy, lane);
4395                         /* Issue Module detection */
4396
4397                         bnx2x_sfp_module_detection(phy, params);
4398                         break;
4399
4400                 case PORT_HW_CFG_NET_SERDES_IF_KR2:
4401                         if (vars->line_speed != SPEED_20000) {
4402                                 DP(NETIF_MSG_LINK, "Speed not supported yet\n");
4403                                 return;
4404                         }
4405                         DP(NETIF_MSG_LINK, "Setting 20G KR2\n");
4406                         bnx2x_warpcore_set_20G_KR2(bp, phy);
4407                         break;
4408
4409                 default:
4410                         DP(NETIF_MSG_LINK,
4411                            "Unsupported Serdes Net Interface 0x%x\n",
4412                            serdes_net_if);
4413                         return;
4414                 }
4415         }
4416
4417         /* Take lane out of reset after configuration is finished */
4418         bnx2x_warpcore_reset_lane(bp, phy, 0);
4419         DP(NETIF_MSG_LINK, "Exit config init\n");
4420 }
4421
4422 static void bnx2x_sfp_e3_set_transmitter(struct link_params *params,
4423                                          struct bnx2x_phy *phy,
4424                                          u8 tx_en)
4425 {
4426         struct bnx2x *bp = params->bp;
4427         u32 cfg_pin;
4428         u8 port = params->port;
4429
4430         cfg_pin = REG_RD(bp, params->shmem_base +
4431                                 offsetof(struct shmem_region,
4432                                 dev_info.port_hw_config[port].e3_sfp_ctrl)) &
4433                                 PORT_HW_CFG_TX_LASER_MASK;
4434         /* Set the !tx_en since this pin is DISABLE_TX_LASER */
4435         DP(NETIF_MSG_LINK, "Setting WC TX to %d\n", tx_en);
4436         /* For 20G, the expected pin to be used is 3 pins after the current */
4437
4438         bnx2x_set_cfg_pin(bp, cfg_pin, tx_en ^ 1);
4439         if (phy->speed_cap_mask & PORT_HW_CFG_SPEED_CAPABILITY_D0_20G)
4440                 bnx2x_set_cfg_pin(bp, cfg_pin + 3, tx_en ^ 1);
4441 }
4442
4443 static void bnx2x_warpcore_link_reset(struct bnx2x_phy *phy,
4444                                       struct link_params *params)
4445 {
4446         struct bnx2x *bp = params->bp;
4447         u16 val16;
4448         bnx2x_sfp_e3_set_transmitter(params, phy, 0);
4449         bnx2x_set_mdio_clk(bp, params->chip_id, params->port);
4450         bnx2x_set_aer_mmd(params, phy);
4451         /* Global register */
4452         bnx2x_warpcore_reset_lane(bp, phy, 1);
4453
4454         /* Clear loopback settings (if any) */
4455         /* 10G & 20G */
4456         bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
4457                         MDIO_WC_REG_COMBO_IEEE0_MIICTRL, &val16);
4458         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4459                          MDIO_WC_REG_COMBO_IEEE0_MIICTRL, val16 &
4460                          0xBFFF);
4461
4462         bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
4463                         MDIO_WC_REG_IEEE0BLK_MIICNTL, &val16);
4464         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4465                         MDIO_WC_REG_IEEE0BLK_MIICNTL, val16 & 0xfffe);
4466
4467         /* Update those 1-copy registers */
4468         CL22_WR_OVER_CL45(bp, phy, MDIO_REG_BANK_AER_BLOCK,
4469                           MDIO_AER_BLOCK_AER_REG, 0);
4470         /* Enable 1G MDIO (1-copy) */
4471         bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
4472                         MDIO_WC_REG_XGXSBLK0_XGXSCONTROL,
4473                         &val16);
4474         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4475                          MDIO_WC_REG_XGXSBLK0_XGXSCONTROL,
4476                          val16 & ~0x10);
4477
4478         bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
4479                         MDIO_WC_REG_XGXSBLK1_LANECTRL2, &val16);
4480         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4481                          MDIO_WC_REG_XGXSBLK1_LANECTRL2,
4482                          val16 & 0xff00);
4483
4484 }
4485
4486 static void bnx2x_set_warpcore_loopback(struct bnx2x_phy *phy,
4487                                         struct link_params *params)
4488 {
4489         struct bnx2x *bp = params->bp;
4490         u16 val16;
4491         u32 lane;
4492         DP(NETIF_MSG_LINK, "Setting Warpcore loopback type %x, speed %d\n",
4493                        params->loopback_mode, phy->req_line_speed);
4494
4495         if (phy->req_line_speed < SPEED_10000) {
4496                 /* 10/100/1000 */
4497
4498                 /* Update those 1-copy registers */
4499                 CL22_WR_OVER_CL45(bp, phy, MDIO_REG_BANK_AER_BLOCK,
4500                                   MDIO_AER_BLOCK_AER_REG, 0);
4501                 /* Enable 1G MDIO (1-copy) */
4502                 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
4503                                 MDIO_WC_REG_XGXSBLK0_XGXSCONTROL,
4504                                 &val16);
4505                 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4506                                 MDIO_WC_REG_XGXSBLK0_XGXSCONTROL,
4507                                 val16 | 0x10);
4508                 /* Set 1G loopback based on lane (1-copy) */
4509                 lane = bnx2x_get_warpcore_lane(phy, params);
4510                 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
4511                                 MDIO_WC_REG_XGXSBLK1_LANECTRL2, &val16);
4512                 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4513                                 MDIO_WC_REG_XGXSBLK1_LANECTRL2,
4514                                 val16 | (1<<lane));
4515
4516                 /* Switch back to 4-copy registers */
4517                 bnx2x_set_aer_mmd(params, phy);
4518         } else {
4519                 /* 10G & 20G */
4520                 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
4521                                 MDIO_WC_REG_COMBO_IEEE0_MIICTRL, &val16);
4522                 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4523                                 MDIO_WC_REG_COMBO_IEEE0_MIICTRL, val16 |
4524                                  0x4000);
4525
4526                 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
4527                                 MDIO_WC_REG_IEEE0BLK_MIICNTL, &val16);
4528                 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4529                                 MDIO_WC_REG_IEEE0BLK_MIICNTL, val16 | 0x1);
4530         }
4531 }
4532
4533
4534 void bnx2x_sync_link(struct link_params *params,
4535                            struct link_vars *vars)
4536 {
4537         struct bnx2x *bp = params->bp;
4538         u8 link_10g_plus;
4539         if (vars->link_status & LINK_STATUS_PHYSICAL_LINK_FLAG)
4540                 vars->phy_flags |= PHY_PHYSICAL_LINK_FLAG;
4541         vars->link_up = (vars->link_status & LINK_STATUS_LINK_UP);
4542         if (vars->link_up) {
4543                 DP(NETIF_MSG_LINK, "phy link up\n");
4544
4545                 vars->phy_link_up = 1;
4546                 vars->duplex = DUPLEX_FULL;
4547                 switch (vars->link_status &
4548                         LINK_STATUS_SPEED_AND_DUPLEX_MASK) {
4549                 case LINK_10THD:
4550                         vars->duplex = DUPLEX_HALF;
4551                         /* Fall thru */
4552                 case LINK_10TFD:
4553                         vars->line_speed = SPEED_10;
4554                         break;
4555
4556                 case LINK_100TXHD:
4557                         vars->duplex = DUPLEX_HALF;
4558                         /* Fall thru */
4559                 case LINK_100T4:
4560                 case LINK_100TXFD:
4561                         vars->line_speed = SPEED_100;
4562                         break;
4563
4564                 case LINK_1000THD:
4565                         vars->duplex = DUPLEX_HALF;
4566                         /* Fall thru */
4567                 case LINK_1000TFD:
4568                         vars->line_speed = SPEED_1000;
4569                         break;
4570
4571                 case LINK_2500THD:
4572                         vars->duplex = DUPLEX_HALF;
4573                         /* Fall thru */
4574                 case LINK_2500TFD:
4575                         vars->line_speed = SPEED_2500;
4576                         break;
4577
4578                 case LINK_10GTFD:
4579                         vars->line_speed = SPEED_10000;
4580                         break;
4581                 case LINK_20GTFD:
4582                         vars->line_speed = SPEED_20000;
4583                         break;
4584                 default:
4585                         break;
4586                 }
4587                 vars->flow_ctrl = 0;
4588                 if (vars->link_status & LINK_STATUS_TX_FLOW_CONTROL_ENABLED)
4589                         vars->flow_ctrl |= BNX2X_FLOW_CTRL_TX;
4590
4591                 if (vars->link_status & LINK_STATUS_RX_FLOW_CONTROL_ENABLED)
4592                         vars->flow_ctrl |= BNX2X_FLOW_CTRL_RX;
4593
4594                 if (!vars->flow_ctrl)
4595                         vars->flow_ctrl = BNX2X_FLOW_CTRL_NONE;
4596
4597                 if (vars->line_speed &&
4598                     ((vars->line_speed == SPEED_10) ||
4599                      (vars->line_speed == SPEED_100))) {
4600                         vars->phy_flags |= PHY_SGMII_FLAG;
4601                 } else {
4602                         vars->phy_flags &= ~PHY_SGMII_FLAG;
4603                 }
4604                 if (vars->line_speed &&
4605                     USES_WARPCORE(bp) &&
4606                     (vars->line_speed == SPEED_1000))
4607                         vars->phy_flags |= PHY_SGMII_FLAG;
4608                 /* anything 10 and over uses the bmac */
4609                 link_10g_plus = (vars->line_speed >= SPEED_10000);
4610
4611                 if (link_10g_plus) {
4612                         if (USES_WARPCORE(bp))
4613                                 vars->mac_type = MAC_TYPE_XMAC;
4614                         else
4615                                 vars->mac_type = MAC_TYPE_BMAC;
4616                 } else {
4617                         if (USES_WARPCORE(bp))
4618                                 vars->mac_type = MAC_TYPE_UMAC;
4619                         else
4620                                 vars->mac_type = MAC_TYPE_EMAC;
4621                 }
4622         } else { /* link down */
4623                 DP(NETIF_MSG_LINK, "phy link down\n");
4624
4625                 vars->phy_link_up = 0;
4626
4627                 vars->line_speed = 0;
4628                 vars->duplex = DUPLEX_FULL;
4629                 vars->flow_ctrl = BNX2X_FLOW_CTRL_NONE;
4630
4631                 /* indicate no mac active */
4632                 vars->mac_type = MAC_TYPE_NONE;
4633                 if (vars->link_status & LINK_STATUS_PHYSICAL_LINK_FLAG)
4634                         vars->phy_flags |= PHY_HALF_OPEN_CONN_FLAG;
4635         }
4636 }
4637
4638 void bnx2x_link_status_update(struct link_params *params,
4639                               struct link_vars *vars)
4640 {
4641         struct bnx2x *bp = params->bp;
4642         u8 port = params->port;
4643         u32 sync_offset, media_types;
4644         /* Update PHY configuration */
4645         set_phy_vars(params, vars);
4646
4647         vars->link_status = REG_RD(bp, params->shmem_base +
4648                                    offsetof(struct shmem_region,
4649                                             port_mb[port].link_status));
4650
4651         vars->phy_flags = PHY_XGXS_FLAG;
4652         bnx2x_sync_link(params, vars);
4653         /* Sync media type */
4654         sync_offset = params->shmem_base +
4655                         offsetof(struct shmem_region,
4656                                  dev_info.port_hw_config[port].media_type);
4657         media_types = REG_RD(bp, sync_offset);
4658
4659         params->phy[INT_PHY].media_type =
4660                 (media_types & PORT_HW_CFG_MEDIA_TYPE_PHY0_MASK) >>
4661                 PORT_HW_CFG_MEDIA_TYPE_PHY0_SHIFT;
4662         params->phy[EXT_PHY1].media_type =
4663                 (media_types & PORT_HW_CFG_MEDIA_TYPE_PHY1_MASK) >>
4664                 PORT_HW_CFG_MEDIA_TYPE_PHY1_SHIFT;
4665         params->phy[EXT_PHY2].media_type =
4666                 (media_types & PORT_HW_CFG_MEDIA_TYPE_PHY2_MASK) >>
4667                 PORT_HW_CFG_MEDIA_TYPE_PHY2_SHIFT;
4668         DP(NETIF_MSG_LINK, "media_types = 0x%x\n", media_types);
4669
4670         /* Sync AEU offset */
4671         sync_offset = params->shmem_base +
4672                         offsetof(struct shmem_region,
4673                                  dev_info.port_hw_config[port].aeu_int_mask);
4674
4675         vars->aeu_int_mask = REG_RD(bp, sync_offset);
4676
4677         /* Sync PFC status */
4678         if (vars->link_status & LINK_STATUS_PFC_ENABLED)
4679                 params->feature_config_flags |=
4680                                         FEATURE_CONFIG_PFC_ENABLED;
4681         else
4682                 params->feature_config_flags &=
4683                                         ~FEATURE_CONFIG_PFC_ENABLED;
4684
4685         DP(NETIF_MSG_LINK, "link_status 0x%x  phy_link_up %x int_mask 0x%x\n",
4686                  vars->link_status, vars->phy_link_up, vars->aeu_int_mask);
4687         DP(NETIF_MSG_LINK, "line_speed %x  duplex %x  flow_ctrl 0x%x\n",
4688                  vars->line_speed, vars->duplex, vars->flow_ctrl);
4689 }
4690
4691 static void bnx2x_set_master_ln(struct link_params *params,
4692                                 struct bnx2x_phy *phy)
4693 {
4694         struct bnx2x *bp = params->bp;
4695         u16 new_master_ln, ser_lane;
4696         ser_lane = ((params->lane_config &
4697                      PORT_HW_CFG_LANE_SWAP_CFG_MASTER_MASK) >>
4698                     PORT_HW_CFG_LANE_SWAP_CFG_MASTER_SHIFT);
4699
4700         /* set the master_ln for AN */
4701         CL22_RD_OVER_CL45(bp, phy,
4702                           MDIO_REG_BANK_XGXS_BLOCK2,
4703                           MDIO_XGXS_BLOCK2_TEST_MODE_LANE,
4704                           &new_master_ln);
4705
4706         CL22_WR_OVER_CL45(bp, phy,
4707                           MDIO_REG_BANK_XGXS_BLOCK2 ,
4708                           MDIO_XGXS_BLOCK2_TEST_MODE_LANE,
4709                           (new_master_ln | ser_lane));
4710 }
4711
4712 static int bnx2x_reset_unicore(struct link_params *params,
4713                                struct bnx2x_phy *phy,
4714                                u8 set_serdes)
4715 {
4716         struct bnx2x *bp = params->bp;
4717         u16 mii_control;
4718         u16 i;
4719         CL22_RD_OVER_CL45(bp, phy,
4720                           MDIO_REG_BANK_COMBO_IEEE0,
4721                           MDIO_COMBO_IEEE0_MII_CONTROL, &mii_control);
4722
4723         /* reset the unicore */
4724         CL22_WR_OVER_CL45(bp, phy,
4725                           MDIO_REG_BANK_COMBO_IEEE0,
4726                           MDIO_COMBO_IEEE0_MII_CONTROL,
4727                           (mii_control |
4728                            MDIO_COMBO_IEEO_MII_CONTROL_RESET));
4729         if (set_serdes)
4730                 bnx2x_set_serdes_access(bp, params->port);
4731
4732         /* wait for the reset to self clear */
4733         for (i = 0; i < MDIO_ACCESS_TIMEOUT; i++) {
4734                 udelay(5);
4735
4736                 /* the reset erased the previous bank value */
4737                 CL22_RD_OVER_CL45(bp, phy,
4738                                   MDIO_REG_BANK_COMBO_IEEE0,
4739                                   MDIO_COMBO_IEEE0_MII_CONTROL,
4740                                   &mii_control);
4741
4742                 if (!(mii_control & MDIO_COMBO_IEEO_MII_CONTROL_RESET)) {
4743                         udelay(5);
4744                         return 0;
4745                 }
4746         }
4747
4748         netdev_err(bp->dev,  "Warning: PHY was not initialized,"
4749                               " Port %d\n",
4750                          params->port);
4751         DP(NETIF_MSG_LINK, "BUG! XGXS is still in reset!\n");
4752         return -EINVAL;
4753
4754 }
4755
4756 static void bnx2x_set_swap_lanes(struct link_params *params,
4757                                  struct bnx2x_phy *phy)
4758 {
4759         struct bnx2x *bp = params->bp;
4760         /* Each two bits represents a lane number:
4761          * No swap is 0123 => 0x1b no need to enable the swap
4762          */
4763         u16 rx_lane_swap, tx_lane_swap;
4764
4765         rx_lane_swap = ((params->lane_config &
4766                          PORT_HW_CFG_LANE_SWAP_CFG_RX_MASK) >>
4767                         PORT_HW_CFG_LANE_SWAP_CFG_RX_SHIFT);
4768         tx_lane_swap = ((params->lane_config &
4769                          PORT_HW_CFG_LANE_SWAP_CFG_TX_MASK) >>
4770                         PORT_HW_CFG_LANE_SWAP_CFG_TX_SHIFT);
4771
4772         if (rx_lane_swap != 0x1b) {
4773                 CL22_WR_OVER_CL45(bp, phy,
4774                                   MDIO_REG_BANK_XGXS_BLOCK2,
4775                                   MDIO_XGXS_BLOCK2_RX_LN_SWAP,
4776                                   (rx_lane_swap |
4777                                    MDIO_XGXS_BLOCK2_RX_LN_SWAP_ENABLE |
4778                                    MDIO_XGXS_BLOCK2_RX_LN_SWAP_FORCE_ENABLE));
4779         } else {
4780                 CL22_WR_OVER_CL45(bp, phy,
4781                                   MDIO_REG_BANK_XGXS_BLOCK2,
4782                                   MDIO_XGXS_BLOCK2_RX_LN_SWAP, 0);
4783         }
4784
4785         if (tx_lane_swap != 0x1b) {
4786                 CL22_WR_OVER_CL45(bp, phy,
4787                                   MDIO_REG_BANK_XGXS_BLOCK2,
4788                                   MDIO_XGXS_BLOCK2_TX_LN_SWAP,
4789                                   (tx_lane_swap |
4790                                    MDIO_XGXS_BLOCK2_TX_LN_SWAP_ENABLE));
4791         } else {
4792                 CL22_WR_OVER_CL45(bp, phy,
4793                                   MDIO_REG_BANK_XGXS_BLOCK2,
4794                                   MDIO_XGXS_BLOCK2_TX_LN_SWAP, 0);
4795         }
4796 }
4797
4798 static void bnx2x_set_parallel_detection(struct bnx2x_phy *phy,
4799                                          struct link_params *params)
4800 {
4801         struct bnx2x *bp = params->bp;
4802         u16 control2;
4803         CL22_RD_OVER_CL45(bp, phy,
4804                           MDIO_REG_BANK_SERDES_DIGITAL,
4805                           MDIO_SERDES_DIGITAL_A_1000X_CONTROL2,
4806                           &control2);
4807         if (phy->speed_cap_mask & PORT_HW_CFG_SPEED_CAPABILITY_D0_1G)
4808                 control2 |= MDIO_SERDES_DIGITAL_A_1000X_CONTROL2_PRL_DT_EN;
4809         else
4810                 control2 &= ~MDIO_SERDES_DIGITAL_A_1000X_CONTROL2_PRL_DT_EN;
4811         DP(NETIF_MSG_LINK, "phy->speed_cap_mask = 0x%x, control2 = 0x%x\n",
4812                 phy->speed_cap_mask, control2);
4813         CL22_WR_OVER_CL45(bp, phy,
4814                           MDIO_REG_BANK_SERDES_DIGITAL,
4815                           MDIO_SERDES_DIGITAL_A_1000X_CONTROL2,
4816                           control2);
4817
4818         if ((phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT) &&
4819              (phy->speed_cap_mask &
4820                     PORT_HW_CFG_SPEED_CAPABILITY_D0_10G)) {
4821                 DP(NETIF_MSG_LINK, "XGXS\n");
4822
4823                 CL22_WR_OVER_CL45(bp, phy,
4824                                  MDIO_REG_BANK_10G_PARALLEL_DETECT,
4825                                  MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_LINK,
4826                                  MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_LINK_CNT);
4827
4828                 CL22_RD_OVER_CL45(bp, phy,
4829                                   MDIO_REG_BANK_10G_PARALLEL_DETECT,
4830                                   MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_CONTROL,
4831                                   &control2);
4832
4833
4834                 control2 |=
4835                     MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_CONTROL_PARDET10G_EN;
4836
4837                 CL22_WR_OVER_CL45(bp, phy,
4838                                   MDIO_REG_BANK_10G_PARALLEL_DETECT,
4839                                   MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_CONTROL,
4840                                   control2);
4841
4842                 /* Disable parallel detection of HiG */
4843                 CL22_WR_OVER_CL45(bp, phy,
4844                                   MDIO_REG_BANK_XGXS_BLOCK2,
4845                                   MDIO_XGXS_BLOCK2_UNICORE_MODE_10G,
4846                                   MDIO_XGXS_BLOCK2_UNICORE_MODE_10G_CX4_XGXS |
4847                                   MDIO_XGXS_BLOCK2_UNICORE_MODE_10G_HIGIG_XGXS);
4848         }
4849 }
4850
4851 static void bnx2x_set_autoneg(struct bnx2x_phy *phy,
4852                               struct link_params *params,
4853                               struct link_vars *vars,
4854                               u8 enable_cl73)
4855 {
4856         struct bnx2x *bp = params->bp;
4857         u16 reg_val;
4858
4859         /* CL37 Autoneg */
4860         CL22_RD_OVER_CL45(bp, phy,
4861                           MDIO_REG_BANK_COMBO_IEEE0,
4862                           MDIO_COMBO_IEEE0_MII_CONTROL, &reg_val);
4863
4864         /* CL37 Autoneg Enabled */
4865         if (vars->line_speed == SPEED_AUTO_NEG)
4866                 reg_val |= MDIO_COMBO_IEEO_MII_CONTROL_AN_EN;
4867         else /* CL37 Autoneg Disabled */
4868                 reg_val &= ~(MDIO_COMBO_IEEO_MII_CONTROL_AN_EN |
4869                              MDIO_COMBO_IEEO_MII_CONTROL_RESTART_AN);
4870
4871         CL22_WR_OVER_CL45(bp, phy,
4872                           MDIO_REG_BANK_COMBO_IEEE0,
4873                           MDIO_COMBO_IEEE0_MII_CONTROL, reg_val);
4874
4875         /* Enable/Disable Autodetection */
4876
4877         CL22_RD_OVER_CL45(bp, phy,
4878                           MDIO_REG_BANK_SERDES_DIGITAL,
4879                           MDIO_SERDES_DIGITAL_A_1000X_CONTROL1, &reg_val);
4880         reg_val &= ~(MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_SIGNAL_DETECT_EN |
4881                     MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_INVERT_SIGNAL_DETECT);
4882         reg_val |= MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_FIBER_MODE;
4883         if (vars->line_speed == SPEED_AUTO_NEG)
4884                 reg_val |= MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_AUTODET;
4885         else
4886                 reg_val &= ~MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_AUTODET;
4887
4888         CL22_WR_OVER_CL45(bp, phy,
4889                           MDIO_REG_BANK_SERDES_DIGITAL,
4890                           MDIO_SERDES_DIGITAL_A_1000X_CONTROL1, reg_val);
4891
4892         /* Enable TetonII and BAM autoneg */
4893         CL22_RD_OVER_CL45(bp, phy,
4894                           MDIO_REG_BANK_BAM_NEXT_PAGE,
4895                           MDIO_BAM_NEXT_PAGE_MP5_NEXT_PAGE_CTRL,
4896                           &reg_val);
4897         if (vars->line_speed == SPEED_AUTO_NEG) {
4898                 /* Enable BAM aneg Mode and TetonII aneg Mode */
4899                 reg_val |= (MDIO_BAM_NEXT_PAGE_MP5_NEXT_PAGE_CTRL_BAM_MODE |
4900                             MDIO_BAM_NEXT_PAGE_MP5_NEXT_PAGE_CTRL_TETON_AN);
4901         } else {
4902                 /* TetonII and BAM Autoneg Disabled */
4903                 reg_val &= ~(MDIO_BAM_NEXT_PAGE_MP5_NEXT_PAGE_CTRL_BAM_MODE |
4904                              MDIO_BAM_NEXT_PAGE_MP5_NEXT_PAGE_CTRL_TETON_AN);
4905         }
4906         CL22_WR_OVER_CL45(bp, phy,
4907                           MDIO_REG_BANK_BAM_NEXT_PAGE,
4908                           MDIO_BAM_NEXT_PAGE_MP5_NEXT_PAGE_CTRL,
4909                           reg_val);
4910
4911         if (enable_cl73) {
4912                 /* Enable Cl73 FSM status bits */
4913                 CL22_WR_OVER_CL45(bp, phy,
4914                                   MDIO_REG_BANK_CL73_USERB0,
4915                                   MDIO_CL73_USERB0_CL73_UCTRL,
4916                                   0xe);
4917
4918                 /* Enable BAM Station Manager*/
4919                 CL22_WR_OVER_CL45(bp, phy,
4920                         MDIO_REG_BANK_CL73_USERB0,
4921                         MDIO_CL73_USERB0_CL73_BAM_CTRL1,
4922                         MDIO_CL73_USERB0_CL73_BAM_CTRL1_BAM_EN |
4923                         MDIO_CL73_USERB0_CL73_BAM_CTRL1_BAM_STATION_MNGR_EN |
4924                         MDIO_CL73_USERB0_CL73_BAM_CTRL1_BAM_NP_AFTER_BP_EN);
4925
4926                 /* Advertise CL73 link speeds */
4927                 CL22_RD_OVER_CL45(bp, phy,
4928                                   MDIO_REG_BANK_CL73_IEEEB1,
4929                                   MDIO_CL73_IEEEB1_AN_ADV2,
4930                                   &reg_val);
4931                 if (phy->speed_cap_mask &
4932                     PORT_HW_CFG_SPEED_CAPABILITY_D0_10G)
4933                         reg_val |= MDIO_CL73_IEEEB1_AN_ADV2_ADVR_10G_KX4;
4934                 if (phy->speed_cap_mask &
4935                     PORT_HW_CFG_SPEED_CAPABILITY_D0_1G)
4936                         reg_val |= MDIO_CL73_IEEEB1_AN_ADV2_ADVR_1000M_KX;
4937
4938                 CL22_WR_OVER_CL45(bp, phy,
4939                                   MDIO_REG_BANK_CL73_IEEEB1,
4940                                   MDIO_CL73_IEEEB1_AN_ADV2,
4941                                   reg_val);
4942
4943                 /* CL73 Autoneg Enabled */
4944                 reg_val = MDIO_CL73_IEEEB0_CL73_AN_CONTROL_AN_EN;
4945
4946         } else /* CL73 Autoneg Disabled */
4947                 reg_val = 0;
4948
4949         CL22_WR_OVER_CL45(bp, phy,
4950                           MDIO_REG_BANK_CL73_IEEEB0,
4951                           MDIO_CL73_IEEEB0_CL73_AN_CONTROL, reg_val);
4952 }
4953
4954 /* program SerDes, forced speed */
4955 static void bnx2x_program_serdes(struct bnx2x_phy *phy,
4956                                  struct link_params *params,
4957                                  struct link_vars *vars)
4958 {
4959         struct bnx2x *bp = params->bp;
4960         u16 reg_val;
4961
4962         /* program duplex, disable autoneg and sgmii*/
4963         CL22_RD_OVER_CL45(bp, phy,
4964                           MDIO_REG_BANK_COMBO_IEEE0,
4965                           MDIO_COMBO_IEEE0_MII_CONTROL, &reg_val);
4966         reg_val &= ~(MDIO_COMBO_IEEO_MII_CONTROL_FULL_DUPLEX |
4967                      MDIO_COMBO_IEEO_MII_CONTROL_AN_EN |
4968                      MDIO_COMBO_IEEO_MII_CONTROL_MAN_SGMII_SP_MASK);
4969         if (phy->req_duplex == DUPLEX_FULL)
4970                 reg_val |= MDIO_COMBO_IEEO_MII_CONTROL_FULL_DUPLEX;
4971         CL22_WR_OVER_CL45(bp, phy,
4972                           MDIO_REG_BANK_COMBO_IEEE0,
4973                           MDIO_COMBO_IEEE0_MII_CONTROL, reg_val);
4974
4975         /* Program speed
4976          *  - needed only if the speed is greater than 1G (2.5G or 10G)
4977          */
4978         CL22_RD_OVER_CL45(bp, phy,
4979                           MDIO_REG_BANK_SERDES_DIGITAL,
4980                           MDIO_SERDES_DIGITAL_MISC1, &reg_val);
4981         /* clearing the speed value before setting the right speed */
4982         DP(NETIF_MSG_LINK, "MDIO_REG_BANK_SERDES_DIGITAL = 0x%x\n", reg_val);
4983
4984         reg_val &= ~(MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_MASK |
4985                      MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_SEL);
4986
4987         if (!((vars->line_speed == SPEED_1000) ||
4988               (vars->line_speed == SPEED_100) ||
4989               (vars->line_speed == SPEED_10))) {
4990
4991                 reg_val |= (MDIO_SERDES_DIGITAL_MISC1_REFCLK_SEL_156_25M |
4992                             MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_SEL);
4993                 if (vars->line_speed == SPEED_10000)
4994                         reg_val |=
4995                                 MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_10G_CX4;
4996         }
4997
4998         CL22_WR_OVER_CL45(bp, phy,
4999                           MDIO_REG_BANK_SERDES_DIGITAL,
5000                           MDIO_SERDES_DIGITAL_MISC1, reg_val);
5001
5002 }
5003
5004 static void bnx2x_set_brcm_cl37_advertisement(struct bnx2x_phy *phy,
5005                                               struct link_params *params)
5006 {
5007         struct bnx2x *bp = params->bp;
5008         u16 val = 0;
5009
5010         /* set extended capabilities */
5011         if (phy->speed_cap_mask & PORT_HW_CFG_SPEED_CAPABILITY_D0_2_5G)
5012                 val |= MDIO_OVER_1G_UP1_2_5G;
5013         if (phy->speed_cap_mask & PORT_HW_CFG_SPEED_CAPABILITY_D0_10G)
5014                 val |= MDIO_OVER_1G_UP1_10G;
5015         CL22_WR_OVER_CL45(bp, phy,
5016                           MDIO_REG_BANK_OVER_1G,
5017                           MDIO_OVER_1G_UP1, val);
5018
5019         CL22_WR_OVER_CL45(bp, phy,
5020                           MDIO_REG_BANK_OVER_1G,
5021                           MDIO_OVER_1G_UP3, 0x400);
5022 }
5023
5024 static void bnx2x_set_ieee_aneg_advertisement(struct bnx2x_phy *phy,
5025                                               struct link_params *params,
5026                                               u16 ieee_fc)
5027 {
5028         struct bnx2x *bp = params->bp;
5029         u16 val;
5030         /* for AN, we are always publishing full duplex */
5031
5032         CL22_WR_OVER_CL45(bp, phy,
5033                           MDIO_REG_BANK_COMBO_IEEE0,
5034                           MDIO_COMBO_IEEE0_AUTO_NEG_ADV, ieee_fc);
5035         CL22_RD_OVER_CL45(bp, phy,
5036                           MDIO_REG_BANK_CL73_IEEEB1,
5037                           MDIO_CL73_IEEEB1_AN_ADV1, &val);
5038         val &= ~MDIO_CL73_IEEEB1_AN_ADV1_PAUSE_BOTH;
5039         val |= ((ieee_fc<<3) & MDIO_CL73_IEEEB1_AN_ADV1_PAUSE_MASK);
5040         CL22_WR_OVER_CL45(bp, phy,
5041                           MDIO_REG_BANK_CL73_IEEEB1,
5042                           MDIO_CL73_IEEEB1_AN_ADV1, val);
5043 }
5044
5045 static void bnx2x_restart_autoneg(struct bnx2x_phy *phy,
5046                                   struct link_params *params,
5047                                   u8 enable_cl73)
5048 {
5049         struct bnx2x *bp = params->bp;
5050         u16 mii_control;
5051
5052         DP(NETIF_MSG_LINK, "bnx2x_restart_autoneg\n");
5053         /* Enable and restart BAM/CL37 aneg */
5054
5055         if (enable_cl73) {
5056                 CL22_RD_OVER_CL45(bp, phy,
5057                                   MDIO_REG_BANK_CL73_IEEEB0,
5058                                   MDIO_CL73_IEEEB0_CL73_AN_CONTROL,
5059                                   &mii_control);
5060
5061                 CL22_WR_OVER_CL45(bp, phy,
5062                                   MDIO_REG_BANK_CL73_IEEEB0,
5063                                   MDIO_CL73_IEEEB0_CL73_AN_CONTROL,
5064                                   (mii_control |
5065                                   MDIO_CL73_IEEEB0_CL73_AN_CONTROL_AN_EN |
5066                                   MDIO_CL73_IEEEB0_CL73_AN_CONTROL_RESTART_AN));
5067         } else {
5068
5069                 CL22_RD_OVER_CL45(bp, phy,
5070                                   MDIO_REG_BANK_COMBO_IEEE0,
5071                                   MDIO_COMBO_IEEE0_MII_CONTROL,
5072                                   &mii_control);
5073                 DP(NETIF_MSG_LINK,
5074                          "bnx2x_restart_autoneg mii_control before = 0x%x\n",
5075                          mii_control);
5076                 CL22_WR_OVER_CL45(bp, phy,
5077                                   MDIO_REG_BANK_COMBO_IEEE0,
5078                                   MDIO_COMBO_IEEE0_MII_CONTROL,
5079                                   (mii_control |
5080                                    MDIO_COMBO_IEEO_MII_CONTROL_AN_EN |
5081                                    MDIO_COMBO_IEEO_MII_CONTROL_RESTART_AN));
5082         }
5083 }
5084
5085 static void bnx2x_initialize_sgmii_process(struct bnx2x_phy *phy,
5086                                            struct link_params *params,
5087                                            struct link_vars *vars)
5088 {
5089         struct bnx2x *bp = params->bp;
5090         u16 control1;
5091
5092         /* in SGMII mode, the unicore is always slave */
5093
5094         CL22_RD_OVER_CL45(bp, phy,
5095                           MDIO_REG_BANK_SERDES_DIGITAL,
5096                           MDIO_SERDES_DIGITAL_A_1000X_CONTROL1,
5097                           &control1);
5098         control1 |= MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_INVERT_SIGNAL_DETECT;
5099         /* set sgmii mode (and not fiber) */
5100         control1 &= ~(MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_FIBER_MODE |
5101                       MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_AUTODET |
5102                       MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_MSTR_MODE);
5103         CL22_WR_OVER_CL45(bp, phy,
5104                           MDIO_REG_BANK_SERDES_DIGITAL,
5105                           MDIO_SERDES_DIGITAL_A_1000X_CONTROL1,
5106                           control1);
5107
5108         /* if forced speed */
5109         if (!(vars->line_speed == SPEED_AUTO_NEG)) {
5110                 /* set speed, disable autoneg */
5111                 u16 mii_control;
5112
5113                 CL22_RD_OVER_CL45(bp, phy,
5114                                   MDIO_REG_BANK_COMBO_IEEE0,
5115                                   MDIO_COMBO_IEEE0_MII_CONTROL,
5116                                   &mii_control);
5117                 mii_control &= ~(MDIO_COMBO_IEEO_MII_CONTROL_AN_EN |
5118                                  MDIO_COMBO_IEEO_MII_CONTROL_MAN_SGMII_SP_MASK|
5119                                  MDIO_COMBO_IEEO_MII_CONTROL_FULL_DUPLEX);
5120
5121                 switch (vars->line_speed) {
5122                 case SPEED_100:
5123                         mii_control |=
5124                                 MDIO_COMBO_IEEO_MII_CONTROL_MAN_SGMII_SP_100;
5125                         break;
5126                 case SPEED_1000:
5127                         mii_control |=
5128                                 MDIO_COMBO_IEEO_MII_CONTROL_MAN_SGMII_SP_1000;
5129                         break;
5130                 case SPEED_10:
5131                         /* there is nothing to set for 10M */
5132                         break;
5133                 default:
5134                         /* invalid speed for SGMII */
5135                         DP(NETIF_MSG_LINK, "Invalid line_speed 0x%x\n",
5136                                   vars->line_speed);
5137                         break;
5138                 }
5139
5140                 /* setting the full duplex */
5141                 if (phy->req_duplex == DUPLEX_FULL)
5142                         mii_control |=
5143                                 MDIO_COMBO_IEEO_MII_CONTROL_FULL_DUPLEX;
5144                 CL22_WR_OVER_CL45(bp, phy,
5145                                   MDIO_REG_BANK_COMBO_IEEE0,
5146                                   MDIO_COMBO_IEEE0_MII_CONTROL,
5147                                   mii_control);
5148
5149         } else { /* AN mode */
5150                 /* enable and restart AN */
5151                 bnx2x_restart_autoneg(phy, params, 0);
5152         }
5153 }
5154
5155 /* Link management
5156  */
5157 static int bnx2x_direct_parallel_detect_used(struct bnx2x_phy *phy,
5158                                              struct link_params *params)
5159 {
5160         struct bnx2x *bp = params->bp;
5161         u16 pd_10g, status2_1000x;
5162         if (phy->req_line_speed != SPEED_AUTO_NEG)
5163                 return 0;
5164         CL22_RD_OVER_CL45(bp, phy,
5165                           MDIO_REG_BANK_SERDES_DIGITAL,
5166                           MDIO_SERDES_DIGITAL_A_1000X_STATUS2,
5167                           &status2_1000x);
5168         CL22_RD_OVER_CL45(bp, phy,
5169                           MDIO_REG_BANK_SERDES_DIGITAL,
5170                           MDIO_SERDES_DIGITAL_A_1000X_STATUS2,
5171                           &status2_1000x);
5172         if (status2_1000x & MDIO_SERDES_DIGITAL_A_1000X_STATUS2_AN_DISABLED) {
5173                 DP(NETIF_MSG_LINK, "1G parallel detect link on port %d\n",
5174                          params->port);
5175                 return 1;
5176         }
5177
5178         CL22_RD_OVER_CL45(bp, phy,
5179                           MDIO_REG_BANK_10G_PARALLEL_DETECT,
5180                           MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_STATUS,
5181                           &pd_10g);
5182
5183         if (pd_10g & MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_STATUS_PD_LINK) {
5184                 DP(NETIF_MSG_LINK, "10G parallel detect link on port %d\n",
5185                          params->port);
5186                 return 1;
5187         }
5188         return 0;
5189 }
5190
5191 static void bnx2x_update_adv_fc(struct bnx2x_phy *phy,
5192                                 struct link_params *params,
5193                                 struct link_vars *vars,
5194                                 u32 gp_status)
5195 {
5196         u16 ld_pause;   /* local driver */
5197         u16 lp_pause;   /* link partner */
5198         u16 pause_result;
5199         struct bnx2x *bp = params->bp;
5200         if ((gp_status &
5201              (MDIO_GP_STATUS_TOP_AN_STATUS1_CL73_AUTONEG_COMPLETE |
5202               MDIO_GP_STATUS_TOP_AN_STATUS1_CL73_MR_LP_NP_AN_ABLE)) ==
5203             (MDIO_GP_STATUS_TOP_AN_STATUS1_CL73_AUTONEG_COMPLETE |
5204              MDIO_GP_STATUS_TOP_AN_STATUS1_CL73_MR_LP_NP_AN_ABLE)) {
5205
5206                 CL22_RD_OVER_CL45(bp, phy,
5207                                   MDIO_REG_BANK_CL73_IEEEB1,
5208                                   MDIO_CL73_IEEEB1_AN_ADV1,
5209                                   &ld_pause);
5210                 CL22_RD_OVER_CL45(bp, phy,
5211                                   MDIO_REG_BANK_CL73_IEEEB1,
5212                                   MDIO_CL73_IEEEB1_AN_LP_ADV1,
5213                                   &lp_pause);
5214                 pause_result = (ld_pause &
5215                                 MDIO_CL73_IEEEB1_AN_ADV1_PAUSE_MASK) >> 8;
5216                 pause_result |= (lp_pause &
5217                                  MDIO_CL73_IEEEB1_AN_LP_ADV1_PAUSE_MASK) >> 10;
5218                 DP(NETIF_MSG_LINK, "pause_result CL73 0x%x\n", pause_result);
5219         } else {
5220                 CL22_RD_OVER_CL45(bp, phy,
5221                                   MDIO_REG_BANK_COMBO_IEEE0,
5222                                   MDIO_COMBO_IEEE0_AUTO_NEG_ADV,
5223                                   &ld_pause);
5224                 CL22_RD_OVER_CL45(bp, phy,
5225                         MDIO_REG_BANK_COMBO_IEEE0,
5226                         MDIO_COMBO_IEEE0_AUTO_NEG_LINK_PARTNER_ABILITY1,
5227                         &lp_pause);
5228                 pause_result = (ld_pause &
5229                                 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_MASK)>>5;
5230                 pause_result |= (lp_pause &
5231                                  MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_MASK)>>7;
5232                 DP(NETIF_MSG_LINK, "pause_result CL37 0x%x\n", pause_result);
5233         }
5234         bnx2x_pause_resolve(vars, pause_result);
5235
5236 }
5237
5238 static void bnx2x_flow_ctrl_resolve(struct bnx2x_phy *phy,
5239                                     struct link_params *params,
5240                                     struct link_vars *vars,
5241                                     u32 gp_status)
5242 {
5243         struct bnx2x *bp = params->bp;
5244         vars->flow_ctrl = BNX2X_FLOW_CTRL_NONE;
5245
5246         /* resolve from gp_status in case of AN complete and not sgmii */
5247         if (phy->req_flow_ctrl != BNX2X_FLOW_CTRL_AUTO) {
5248                 /* Update the advertised flow-controled of LD/LP in AN */
5249                 if (phy->req_line_speed == SPEED_AUTO_NEG)
5250                         bnx2x_update_adv_fc(phy, params, vars, gp_status);
5251                 /* But set the flow-control result as the requested one */
5252                 vars->flow_ctrl = phy->req_flow_ctrl;
5253         } else if (phy->req_line_speed != SPEED_AUTO_NEG)
5254                 vars->flow_ctrl = params->req_fc_auto_adv;
5255         else if ((gp_status & MDIO_AN_CL73_OR_37_COMPLETE) &&
5256                  (!(vars->phy_flags & PHY_SGMII_FLAG))) {
5257                 if (bnx2x_direct_parallel_detect_used(phy, params)) {
5258                         vars->flow_ctrl = params->req_fc_auto_adv;
5259                         return;
5260                 }
5261                 bnx2x_update_adv_fc(phy, params, vars, gp_status);
5262         }
5263         DP(NETIF_MSG_LINK, "flow_ctrl 0x%x\n", vars->flow_ctrl);
5264 }
5265
5266 static void bnx2x_check_fallback_to_cl37(struct bnx2x_phy *phy,
5267                                          struct link_params *params)
5268 {
5269         struct bnx2x *bp = params->bp;
5270         u16 rx_status, ustat_val, cl37_fsm_received;
5271         DP(NETIF_MSG_LINK, "bnx2x_check_fallback_to_cl37\n");
5272         /* Step 1: Make sure signal is detected */
5273         CL22_RD_OVER_CL45(bp, phy,
5274                           MDIO_REG_BANK_RX0,
5275                           MDIO_RX0_RX_STATUS,
5276                           &rx_status);
5277         if ((rx_status & MDIO_RX0_RX_STATUS_SIGDET) !=
5278             (MDIO_RX0_RX_STATUS_SIGDET)) {
5279                 DP(NETIF_MSG_LINK, "Signal is not detected. Restoring CL73."
5280                              "rx_status(0x80b0) = 0x%x\n", rx_status);
5281                 CL22_WR_OVER_CL45(bp, phy,
5282                                   MDIO_REG_BANK_CL73_IEEEB0,
5283                                   MDIO_CL73_IEEEB0_CL73_AN_CONTROL,
5284                                   MDIO_CL73_IEEEB0_CL73_AN_CONTROL_AN_EN);
5285                 return;
5286         }
5287         /* Step 2: Check CL73 state machine */
5288         CL22_RD_OVER_CL45(bp, phy,
5289                           MDIO_REG_BANK_CL73_USERB0,
5290                           MDIO_CL73_USERB0_CL73_USTAT1,
5291                           &ustat_val);
5292         if ((ustat_val &
5293              (MDIO_CL73_USERB0_CL73_USTAT1_LINK_STATUS_CHECK |
5294               MDIO_CL73_USERB0_CL73_USTAT1_AN_GOOD_CHECK_BAM37)) !=
5295             (MDIO_CL73_USERB0_CL73_USTAT1_LINK_STATUS_CHECK |
5296               MDIO_CL73_USERB0_CL73_USTAT1_AN_GOOD_CHECK_BAM37)) {
5297                 DP(NETIF_MSG_LINK, "CL73 state-machine is not stable. "
5298                              "ustat_val(0x8371) = 0x%x\n", ustat_val);
5299                 return;
5300         }
5301         /* Step 3: Check CL37 Message Pages received to indicate LP
5302          * supports only CL37
5303          */
5304         CL22_RD_OVER_CL45(bp, phy,
5305                           MDIO_REG_BANK_REMOTE_PHY,
5306                           MDIO_REMOTE_PHY_MISC_RX_STATUS,
5307                           &cl37_fsm_received);
5308         if ((cl37_fsm_received &
5309              (MDIO_REMOTE_PHY_MISC_RX_STATUS_CL37_FSM_RECEIVED_OVER1G_MSG |
5310              MDIO_REMOTE_PHY_MISC_RX_STATUS_CL37_FSM_RECEIVED_BRCM_OUI_MSG)) !=
5311             (MDIO_REMOTE_PHY_MISC_RX_STATUS_CL37_FSM_RECEIVED_OVER1G_MSG |
5312               MDIO_REMOTE_PHY_MISC_RX_STATUS_CL37_FSM_RECEIVED_BRCM_OUI_MSG)) {
5313                 DP(NETIF_MSG_LINK, "No CL37 FSM were received. "
5314                              "misc_rx_status(0x8330) = 0x%x\n",
5315                          cl37_fsm_received);
5316                 return;
5317         }
5318         /* The combined cl37/cl73 fsm state information indicating that
5319          * we are connected to a device which does not support cl73, but
5320          * does support cl37 BAM. In this case we disable cl73 and
5321          * restart cl37 auto-neg
5322          */
5323
5324         /* Disable CL73 */
5325         CL22_WR_OVER_CL45(bp, phy,
5326                           MDIO_REG_BANK_CL73_IEEEB0,
5327                           MDIO_CL73_IEEEB0_CL73_AN_CONTROL,
5328                           0);
5329         /* Restart CL37 autoneg */
5330         bnx2x_restart_autoneg(phy, params, 0);
5331         DP(NETIF_MSG_LINK, "Disabling CL73, and restarting CL37 autoneg\n");
5332 }
5333
5334 static void bnx2x_xgxs_an_resolve(struct bnx2x_phy *phy,
5335                                   struct link_params *params,
5336                                   struct link_vars *vars,
5337                                   u32 gp_status)
5338 {
5339         if (gp_status & MDIO_AN_CL73_OR_37_COMPLETE)
5340                 vars->link_status |=
5341                         LINK_STATUS_AUTO_NEGOTIATE_COMPLETE;
5342
5343         if (bnx2x_direct_parallel_detect_used(phy, params))
5344                 vars->link_status |=
5345                         LINK_STATUS_PARALLEL_DETECTION_USED;
5346 }
5347 static int bnx2x_get_link_speed_duplex(struct bnx2x_phy *phy,
5348                                      struct link_params *params,
5349                                       struct link_vars *vars,
5350                                       u16 is_link_up,
5351                                       u16 speed_mask,
5352                                       u16 is_duplex)
5353 {
5354         struct bnx2x *bp = params->bp;
5355         if (phy->req_line_speed == SPEED_AUTO_NEG)
5356                 vars->link_status |= LINK_STATUS_AUTO_NEGOTIATE_ENABLED;
5357         if (is_link_up) {
5358                 DP(NETIF_MSG_LINK, "phy link up\n");
5359
5360                 vars->phy_link_up = 1;
5361                 vars->link_status |= LINK_STATUS_LINK_UP;
5362
5363                 switch (speed_mask) {
5364                 case GP_STATUS_10M:
5365                         vars->line_speed = SPEED_10;
5366                         if (vars->duplex == DUPLEX_FULL)
5367                                 vars->link_status |= LINK_10TFD;
5368                         else
5369                                 vars->link_status |= LINK_10THD;
5370                         break;
5371
5372                 case GP_STATUS_100M:
5373                         vars->line_speed = SPEED_100;
5374                         if (vars->duplex == DUPLEX_FULL)
5375                                 vars->link_status |= LINK_100TXFD;
5376                         else
5377                                 vars->link_status |= LINK_100TXHD;
5378                         break;
5379
5380                 case GP_STATUS_1G:
5381                 case GP_STATUS_1G_KX:
5382                         vars->line_speed = SPEED_1000;
5383                         if (vars->duplex == DUPLEX_FULL)
5384                                 vars->link_status |= LINK_1000TFD;
5385                         else
5386                                 vars->link_status |= LINK_1000THD;
5387                         break;
5388
5389                 case GP_STATUS_2_5G:
5390                         vars->line_speed = SPEED_2500;
5391                         if (vars->duplex == DUPLEX_FULL)
5392                                 vars->link_status |= LINK_2500TFD;
5393                         else
5394                                 vars->link_status |= LINK_2500THD;
5395                         break;
5396
5397                 case GP_STATUS_5G:
5398                 case GP_STATUS_6G:
5399                         DP(NETIF_MSG_LINK,
5400                                  "link speed unsupported  gp_status 0x%x\n",
5401                                   speed_mask);
5402                         return -EINVAL;
5403
5404                 case GP_STATUS_10G_KX4:
5405                 case GP_STATUS_10G_HIG:
5406                 case GP_STATUS_10G_CX4:
5407                 case GP_STATUS_10G_KR:
5408                 case GP_STATUS_10G_SFI:
5409                 case GP_STATUS_10G_XFI:
5410                         vars->line_speed = SPEED_10000;
5411                         vars->link_status |= LINK_10GTFD;
5412                         break;
5413                 case GP_STATUS_20G_DXGXS:
5414                         vars->line_speed = SPEED_20000;
5415                         vars->link_status |= LINK_20GTFD;
5416                         break;
5417                 default:
5418                         DP(NETIF_MSG_LINK,
5419                                   "link speed unsupported gp_status 0x%x\n",
5420                                   speed_mask);
5421                         return -EINVAL;
5422                 }
5423         } else { /* link_down */
5424                 DP(NETIF_MSG_LINK, "phy link down\n");
5425
5426                 vars->phy_link_up = 0;
5427
5428                 vars->duplex = DUPLEX_FULL;
5429                 vars->flow_ctrl = BNX2X_FLOW_CTRL_NONE;
5430                 vars->mac_type = MAC_TYPE_NONE;
5431         }
5432         DP(NETIF_MSG_LINK, " phy_link_up %x line_speed %d\n",
5433                     vars->phy_link_up, vars->line_speed);
5434         return 0;
5435 }
5436
5437 static int bnx2x_link_settings_status(struct bnx2x_phy *phy,
5438                                       struct link_params *params,
5439                                       struct link_vars *vars)
5440 {
5441         struct bnx2x *bp = params->bp;
5442
5443         u16 gp_status, duplex = DUPLEX_HALF, link_up = 0, speed_mask;
5444         int rc = 0;
5445
5446         /* Read gp_status */
5447         CL22_RD_OVER_CL45(bp, phy,
5448                           MDIO_REG_BANK_GP_STATUS,
5449                           MDIO_GP_STATUS_TOP_AN_STATUS1,
5450                           &gp_status);
5451         if (gp_status & MDIO_GP_STATUS_TOP_AN_STATUS1_DUPLEX_STATUS)
5452                 duplex = DUPLEX_FULL;
5453         if (gp_status & MDIO_GP_STATUS_TOP_AN_STATUS1_LINK_STATUS)
5454                 link_up = 1;
5455         speed_mask = gp_status & GP_STATUS_SPEED_MASK;
5456         DP(NETIF_MSG_LINK, "gp_status 0x%x, is_link_up %d, speed_mask 0x%x\n",
5457                        gp_status, link_up, speed_mask);
5458         rc = bnx2x_get_link_speed_duplex(phy, params, vars, link_up, speed_mask,
5459                                          duplex);
5460         if (rc == -EINVAL)
5461                 return rc;
5462
5463         if (gp_status & MDIO_GP_STATUS_TOP_AN_STATUS1_LINK_STATUS) {
5464                 if (SINGLE_MEDIA_DIRECT(params)) {
5465                         bnx2x_flow_ctrl_resolve(phy, params, vars, gp_status);
5466                         if (phy->req_line_speed == SPEED_AUTO_NEG)
5467                                 bnx2x_xgxs_an_resolve(phy, params, vars,
5468                                                       gp_status);
5469                 }
5470         } else { /* link_down */
5471                 if ((phy->req_line_speed == SPEED_AUTO_NEG) &&
5472                     SINGLE_MEDIA_DIRECT(params)) {
5473                         /* Check signal is detected */
5474                         bnx2x_check_fallback_to_cl37(phy, params);
5475                 }
5476         }
5477
5478         /* Read LP advertised speeds*/
5479         if (SINGLE_MEDIA_DIRECT(params) &&
5480             (vars->link_status & LINK_STATUS_AUTO_NEGOTIATE_COMPLETE)) {
5481                 u16 val;
5482
5483                 CL22_RD_OVER_CL45(bp, phy, MDIO_REG_BANK_CL73_IEEEB1,
5484                                   MDIO_CL73_IEEEB1_AN_LP_ADV2, &val);
5485
5486                 if (val & MDIO_CL73_IEEEB1_AN_ADV2_ADVR_1000M_KX)
5487                         vars->link_status |=
5488                                 LINK_STATUS_LINK_PARTNER_1000TFD_CAPABLE;
5489                 if (val & (MDIO_CL73_IEEEB1_AN_ADV2_ADVR_10G_KX4 |
5490                            MDIO_CL73_IEEEB1_AN_ADV2_ADVR_10G_KR))
5491                         vars->link_status |=
5492                                 LINK_STATUS_LINK_PARTNER_10GXFD_CAPABLE;
5493
5494                 CL22_RD_OVER_CL45(bp, phy, MDIO_REG_BANK_OVER_1G,
5495                                   MDIO_OVER_1G_LP_UP1, &val);
5496
5497                 if (val & MDIO_OVER_1G_UP1_2_5G)
5498                         vars->link_status |=
5499                                 LINK_STATUS_LINK_PARTNER_2500XFD_CAPABLE;
5500                 if (val & (MDIO_OVER_1G_UP1_10G | MDIO_OVER_1G_UP1_10GH))
5501                         vars->link_status |=
5502                                 LINK_STATUS_LINK_PARTNER_10GXFD_CAPABLE;
5503         }
5504
5505         DP(NETIF_MSG_LINK, "duplex %x  flow_ctrl 0x%x link_status 0x%x\n",
5506                    vars->duplex, vars->flow_ctrl, vars->link_status);
5507         return rc;
5508 }
5509
5510 static int bnx2x_warpcore_read_status(struct bnx2x_phy *phy,
5511                                      struct link_params *params,
5512                                      struct link_vars *vars)
5513 {
5514         struct bnx2x *bp = params->bp;
5515         u8 lane;
5516         u16 gp_status1, gp_speed, link_up, duplex = DUPLEX_FULL;
5517         int rc = 0;
5518         lane = bnx2x_get_warpcore_lane(phy, params);
5519         /* Read gp_status */
5520         if (phy->req_line_speed > SPEED_10000) {
5521                 u16 temp_link_up;
5522                 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
5523                                 1, &temp_link_up);
5524                 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
5525                                 1, &link_up);
5526                 DP(NETIF_MSG_LINK, "PCS RX link status = 0x%x-->0x%x\n",
5527                                temp_link_up, link_up);
5528                 link_up &= (1<<2);
5529                 if (link_up)
5530                         bnx2x_ext_phy_resolve_fc(phy, params, vars);
5531         } else {
5532                 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
5533                                 MDIO_WC_REG_GP2_STATUS_GP_2_1, &gp_status1);
5534                 DP(NETIF_MSG_LINK, "0x81d1 = 0x%x\n", gp_status1);
5535                 /* Check for either KR or generic link up. */
5536                 gp_status1 = ((gp_status1 >> 8) & 0xf) |
5537                         ((gp_status1 >> 12) & 0xf);
5538                 link_up = gp_status1 & (1 << lane);
5539                 if (link_up && SINGLE_MEDIA_DIRECT(params)) {
5540                         u16 pd, gp_status4;
5541                         if (phy->req_line_speed == SPEED_AUTO_NEG) {
5542                                 /* Check Autoneg complete */
5543                                 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
5544                                                 MDIO_WC_REG_GP2_STATUS_GP_2_4,
5545                                                 &gp_status4);
5546                                 if (gp_status4 & ((1<<12)<<lane))
5547                                         vars->link_status |=
5548                                         LINK_STATUS_AUTO_NEGOTIATE_COMPLETE;
5549
5550                                 /* Check parallel detect used */
5551                                 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
5552                                                 MDIO_WC_REG_PAR_DET_10G_STATUS,
5553                                                 &pd);
5554                                 if (pd & (1<<15))
5555                                         vars->link_status |=
5556                                         LINK_STATUS_PARALLEL_DETECTION_USED;
5557                         }
5558                         bnx2x_ext_phy_resolve_fc(phy, params, vars);
5559                 }
5560         }
5561
5562         if ((vars->link_status & LINK_STATUS_AUTO_NEGOTIATE_COMPLETE) &&
5563             SINGLE_MEDIA_DIRECT(params)) {
5564                 u16 val;
5565
5566                 bnx2x_cl45_read(bp, phy, MDIO_AN_DEVAD,
5567                                 MDIO_AN_REG_LP_AUTO_NEG2, &val);
5568
5569                 if (val & MDIO_CL73_IEEEB1_AN_ADV2_ADVR_1000M_KX)
5570                         vars->link_status |=
5571                                 LINK_STATUS_LINK_PARTNER_1000TFD_CAPABLE;
5572                 if (val & (MDIO_CL73_IEEEB1_AN_ADV2_ADVR_10G_KX4 |
5573                            MDIO_CL73_IEEEB1_AN_ADV2_ADVR_10G_KR))
5574                         vars->link_status |=
5575                                 LINK_STATUS_LINK_PARTNER_10GXFD_CAPABLE;
5576
5577                 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
5578                                 MDIO_WC_REG_DIGITAL3_LP_UP1, &val);
5579
5580                 if (val & MDIO_OVER_1G_UP1_2_5G)
5581                         vars->link_status |=
5582                                 LINK_STATUS_LINK_PARTNER_2500XFD_CAPABLE;
5583                 if (val & (MDIO_OVER_1G_UP1_10G | MDIO_OVER_1G_UP1_10GH))
5584                         vars->link_status |=
5585                                 LINK_STATUS_LINK_PARTNER_10GXFD_CAPABLE;
5586
5587         }
5588
5589
5590         if (lane < 2) {
5591                 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
5592                                 MDIO_WC_REG_GP2_STATUS_GP_2_2, &gp_speed);
5593         } else {
5594                 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
5595                                 MDIO_WC_REG_GP2_STATUS_GP_2_3, &gp_speed);
5596         }
5597         DP(NETIF_MSG_LINK, "lane %d gp_speed 0x%x\n", lane, gp_speed);
5598
5599         if ((lane & 1) == 0)
5600                 gp_speed <<= 8;
5601         gp_speed &= 0x3f00;
5602
5603
5604         rc = bnx2x_get_link_speed_duplex(phy, params, vars, link_up, gp_speed,
5605                                          duplex);
5606
5607         DP(NETIF_MSG_LINK, "duplex %x  flow_ctrl 0x%x link_status 0x%x\n",
5608                    vars->duplex, vars->flow_ctrl, vars->link_status);
5609         return rc;
5610 }
5611 static void bnx2x_set_gmii_tx_driver(struct link_params *params)
5612 {
5613         struct bnx2x *bp = params->bp;
5614         struct bnx2x_phy *phy = &params->phy[INT_PHY];
5615         u16 lp_up2;
5616         u16 tx_driver;
5617         u16 bank;
5618
5619         /* read precomp */
5620         CL22_RD_OVER_CL45(bp, phy,
5621                           MDIO_REG_BANK_OVER_1G,
5622                           MDIO_OVER_1G_LP_UP2, &lp_up2);
5623
5624         /* bits [10:7] at lp_up2, positioned at [15:12] */
5625         lp_up2 = (((lp_up2 & MDIO_OVER_1G_LP_UP2_PREEMPHASIS_MASK) >>
5626                    MDIO_OVER_1G_LP_UP2_PREEMPHASIS_SHIFT) <<
5627                   MDIO_TX0_TX_DRIVER_PREEMPHASIS_SHIFT);
5628
5629         if (lp_up2 == 0)
5630                 return;
5631
5632         for (bank = MDIO_REG_BANK_TX0; bank <= MDIO_REG_BANK_TX3;
5633               bank += (MDIO_REG_BANK_TX1 - MDIO_REG_BANK_TX0)) {
5634                 CL22_RD_OVER_CL45(bp, phy,
5635                                   bank,
5636                                   MDIO_TX0_TX_DRIVER, &tx_driver);
5637
5638                 /* replace tx_driver bits [15:12] */
5639                 if (lp_up2 !=
5640                     (tx_driver & MDIO_TX0_TX_DRIVER_PREEMPHASIS_MASK)) {
5641                         tx_driver &= ~MDIO_TX0_TX_DRIVER_PREEMPHASIS_MASK;
5642                         tx_driver |= lp_up2;
5643                         CL22_WR_OVER_CL45(bp, phy,
5644                                           bank,
5645                                           MDIO_TX0_TX_DRIVER, tx_driver);
5646                 }
5647         }
5648 }
5649
5650 static int bnx2x_emac_program(struct link_params *params,
5651                               struct link_vars *vars)
5652 {
5653         struct bnx2x *bp = params->bp;
5654         u8 port = params->port;
5655         u16 mode = 0;
5656
5657         DP(NETIF_MSG_LINK, "setting link speed & duplex\n");
5658         bnx2x_bits_dis(bp, GRCBASE_EMAC0 + port*0x400 +
5659                        EMAC_REG_EMAC_MODE,
5660                        (EMAC_MODE_25G_MODE |
5661                         EMAC_MODE_PORT_MII_10M |
5662                         EMAC_MODE_HALF_DUPLEX));
5663         switch (vars->line_speed) {
5664         case SPEED_10:
5665                 mode |= EMAC_MODE_PORT_MII_10M;
5666                 break;
5667
5668         case SPEED_100:
5669                 mode |= EMAC_MODE_PORT_MII;
5670                 break;
5671
5672         case SPEED_1000:
5673                 mode |= EMAC_MODE_PORT_GMII;
5674                 break;
5675
5676         case SPEED_2500:
5677                 mode |= (EMAC_MODE_25G_MODE | EMAC_MODE_PORT_GMII);
5678                 break;
5679
5680         default:
5681                 /* 10G not valid for EMAC */
5682                 DP(NETIF_MSG_LINK, "Invalid line_speed 0x%x\n",
5683                            vars->line_speed);
5684                 return -EINVAL;
5685         }
5686
5687         if (vars->duplex == DUPLEX_HALF)
5688                 mode |= EMAC_MODE_HALF_DUPLEX;
5689         bnx2x_bits_en(bp,
5690                       GRCBASE_EMAC0 + port*0x400 + EMAC_REG_EMAC_MODE,
5691                       mode);
5692
5693         bnx2x_set_led(params, vars, LED_MODE_OPER, vars->line_speed);
5694         return 0;
5695 }
5696
5697 static void bnx2x_set_preemphasis(struct bnx2x_phy *phy,
5698                                   struct link_params *params)
5699 {
5700
5701         u16 bank, i = 0;
5702         struct bnx2x *bp = params->bp;
5703
5704         for (bank = MDIO_REG_BANK_RX0, i = 0; bank <= MDIO_REG_BANK_RX3;
5705               bank += (MDIO_REG_BANK_RX1-MDIO_REG_BANK_RX0), i++) {
5706                         CL22_WR_OVER_CL45(bp, phy,
5707                                           bank,
5708                                           MDIO_RX0_RX_EQ_BOOST,
5709                                           phy->rx_preemphasis[i]);
5710         }
5711
5712         for (bank = MDIO_REG_BANK_TX0, i = 0; bank <= MDIO_REG_BANK_TX3;
5713                       bank += (MDIO_REG_BANK_TX1 - MDIO_REG_BANK_TX0), i++) {
5714                         CL22_WR_OVER_CL45(bp, phy,
5715                                           bank,
5716                                           MDIO_TX0_TX_DRIVER,
5717                                           phy->tx_preemphasis[i]);
5718         }
5719 }
5720
5721 static void bnx2x_xgxs_config_init(struct bnx2x_phy *phy,
5722                                    struct link_params *params,
5723                                    struct link_vars *vars)
5724 {
5725         struct bnx2x *bp = params->bp;
5726         u8 enable_cl73 = (SINGLE_MEDIA_DIRECT(params) ||
5727                           (params->loopback_mode == LOOPBACK_XGXS));
5728         if (!(vars->phy_flags & PHY_SGMII_FLAG)) {
5729                 if (SINGLE_MEDIA_DIRECT(params) &&
5730                     (params->feature_config_flags &
5731                      FEATURE_CONFIG_OVERRIDE_PREEMPHASIS_ENABLED))
5732                         bnx2x_set_preemphasis(phy, params);
5733
5734                 /* forced speed requested? */
5735                 if (vars->line_speed != SPEED_AUTO_NEG ||
5736                     (SINGLE_MEDIA_DIRECT(params) &&
5737                      params->loopback_mode == LOOPBACK_EXT)) {
5738                         DP(NETIF_MSG_LINK, "not SGMII, no AN\n");
5739
5740                         /* disable autoneg */
5741                         bnx2x_set_autoneg(phy, params, vars, 0);
5742
5743                         /* program speed and duplex */
5744                         bnx2x_program_serdes(phy, params, vars);
5745
5746                 } else { /* AN_mode */
5747                         DP(NETIF_MSG_LINK, "not SGMII, AN\n");
5748
5749                         /* AN enabled */
5750                         bnx2x_set_brcm_cl37_advertisement(phy, params);
5751
5752                         /* program duplex & pause advertisement (for aneg) */
5753                         bnx2x_set_ieee_aneg_advertisement(phy, params,
5754                                                           vars->ieee_fc);
5755
5756                         /* enable autoneg */
5757                         bnx2x_set_autoneg(phy, params, vars, enable_cl73);
5758
5759                         /* enable and restart AN */
5760                         bnx2x_restart_autoneg(phy, params, enable_cl73);
5761                 }
5762
5763         } else { /* SGMII mode */
5764                 DP(NETIF_MSG_LINK, "SGMII\n");
5765
5766                 bnx2x_initialize_sgmii_process(phy, params, vars);
5767         }
5768 }
5769
5770 static int bnx2x_prepare_xgxs(struct bnx2x_phy *phy,
5771                           struct link_params *params,
5772                           struct link_vars *vars)
5773 {
5774         int rc;
5775         vars->phy_flags |= PHY_XGXS_FLAG;
5776         if ((phy->req_line_speed &&
5777              ((phy->req_line_speed == SPEED_100) ||
5778               (phy->req_line_speed == SPEED_10))) ||
5779             (!phy->req_line_speed &&
5780              (phy->speed_cap_mask >=
5781               PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_FULL) &&
5782              (phy->speed_cap_mask <
5783               PORT_HW_CFG_SPEED_CAPABILITY_D0_1G)) ||
5784             (phy->type == PORT_HW_CFG_SERDES_EXT_PHY_TYPE_DIRECT_SD))
5785                 vars->phy_flags |= PHY_SGMII_FLAG;
5786         else
5787                 vars->phy_flags &= ~PHY_SGMII_FLAG;
5788
5789         bnx2x_calc_ieee_aneg_adv(phy, params, &vars->ieee_fc);
5790         bnx2x_set_aer_mmd(params, phy);
5791         if (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT)
5792                 bnx2x_set_master_ln(params, phy);
5793
5794         rc = bnx2x_reset_unicore(params, phy, 0);
5795         /* reset the SerDes and wait for reset bit return low */
5796         if (rc != 0)
5797                 return rc;
5798
5799         bnx2x_set_aer_mmd(params, phy);
5800         /* setting the masterLn_def again after the reset */
5801         if (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT) {
5802                 bnx2x_set_master_ln(params, phy);
5803                 bnx2x_set_swap_lanes(params, phy);
5804         }
5805
5806         return rc;
5807 }
5808
5809 static u16 bnx2x_wait_reset_complete(struct bnx2x *bp,
5810                                      struct bnx2x_phy *phy,
5811                                      struct link_params *params)
5812 {
5813         u16 cnt, ctrl;
5814         /* Wait for soft reset to get cleared up to 1 sec */
5815         for (cnt = 0; cnt < 1000; cnt++) {
5816                 if (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM54618SE)
5817                         bnx2x_cl22_read(bp, phy,
5818                                 MDIO_PMA_REG_CTRL, &ctrl);
5819                 else
5820                         bnx2x_cl45_read(bp, phy,
5821                                 MDIO_PMA_DEVAD,
5822                                 MDIO_PMA_REG_CTRL, &ctrl);
5823                 if (!(ctrl & (1<<15)))
5824                         break;
5825                 msleep(1);
5826         }
5827
5828         if (cnt == 1000)
5829                 netdev_err(bp->dev,  "Warning: PHY was not initialized,"
5830                                       " Port %d\n",
5831                          params->port);
5832         DP(NETIF_MSG_LINK, "control reg 0x%x (after %d ms)\n", ctrl, cnt);
5833         return cnt;
5834 }
5835
5836 static void bnx2x_link_int_enable(struct link_params *params)
5837 {
5838         u8 port = params->port;
5839         u32 mask;
5840         struct bnx2x *bp = params->bp;
5841
5842         /* Setting the status to report on link up for either XGXS or SerDes */
5843         if (CHIP_IS_E3(bp)) {
5844                 mask = NIG_MASK_XGXS0_LINK_STATUS;
5845                 if (!(SINGLE_MEDIA_DIRECT(params)))
5846                         mask |= NIG_MASK_MI_INT;
5847         } else if (params->switch_cfg == SWITCH_CFG_10G) {
5848                 mask = (NIG_MASK_XGXS0_LINK10G |
5849                         NIG_MASK_XGXS0_LINK_STATUS);
5850                 DP(NETIF_MSG_LINK, "enabled XGXS interrupt\n");
5851                 if (!(SINGLE_MEDIA_DIRECT(params)) &&
5852                         params->phy[INT_PHY].type !=
5853                                 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_FAILURE) {
5854                         mask |= NIG_MASK_MI_INT;
5855                         DP(NETIF_MSG_LINK, "enabled external phy int\n");
5856                 }
5857
5858         } else { /* SerDes */
5859                 mask = NIG_MASK_SERDES0_LINK_STATUS;
5860                 DP(NETIF_MSG_LINK, "enabled SerDes interrupt\n");
5861                 if (!(SINGLE_MEDIA_DIRECT(params)) &&
5862                         params->phy[INT_PHY].type !=
5863                                 PORT_HW_CFG_SERDES_EXT_PHY_TYPE_NOT_CONN) {
5864                         mask |= NIG_MASK_MI_INT;
5865                         DP(NETIF_MSG_LINK, "enabled external phy int\n");
5866                 }
5867         }
5868         bnx2x_bits_en(bp,
5869                       NIG_REG_MASK_INTERRUPT_PORT0 + port*4,
5870                       mask);
5871
5872         DP(NETIF_MSG_LINK, "port %x, is_xgxs %x, int_status 0x%x\n", port,
5873                  (params->switch_cfg == SWITCH_CFG_10G),
5874                  REG_RD(bp, NIG_REG_STATUS_INTERRUPT_PORT0 + port*4));
5875         DP(NETIF_MSG_LINK, " int_mask 0x%x, MI_INT %x, SERDES_LINK %x\n",
5876                  REG_RD(bp, NIG_REG_MASK_INTERRUPT_PORT0 + port*4),
5877                  REG_RD(bp, NIG_REG_EMAC0_STATUS_MISC_MI_INT + port*0x18),
5878                  REG_RD(bp, NIG_REG_SERDES0_STATUS_LINK_STATUS+port*0x3c));
5879         DP(NETIF_MSG_LINK, " 10G %x, XGXS_LINK %x\n",
5880            REG_RD(bp, NIG_REG_XGXS0_STATUS_LINK10G + port*0x68),
5881            REG_RD(bp, NIG_REG_XGXS0_STATUS_LINK_STATUS + port*0x68));
5882 }
5883
5884 static void bnx2x_rearm_latch_signal(struct bnx2x *bp, u8 port,
5885                                      u8 exp_mi_int)
5886 {
5887         u32 latch_status = 0;
5888
5889         /* Disable the MI INT ( external phy int ) by writing 1 to the
5890          * status register. Link down indication is high-active-signal,
5891          * so in this case we need to write the status to clear the XOR
5892          */
5893         /* Read Latched signals */
5894         latch_status = REG_RD(bp,
5895                                     NIG_REG_LATCH_STATUS_0 + port*8);
5896         DP(NETIF_MSG_LINK, "latch_status = 0x%x\n", latch_status);
5897         /* Handle only those with latched-signal=up.*/
5898         if (exp_mi_int)
5899                 bnx2x_bits_en(bp,
5900                               NIG_REG_STATUS_INTERRUPT_PORT0
5901                               + port*4,
5902                               NIG_STATUS_EMAC0_MI_INT);
5903         else
5904                 bnx2x_bits_dis(bp,
5905                                NIG_REG_STATUS_INTERRUPT_PORT0
5906                                + port*4,
5907                                NIG_STATUS_EMAC0_MI_INT);
5908
5909         if (latch_status & 1) {
5910
5911                 /* For all latched-signal=up : Re-Arm Latch signals */
5912                 REG_WR(bp, NIG_REG_LATCH_STATUS_0 + port*8,
5913                        (latch_status & 0xfffe) | (latch_status & 1));
5914         }
5915         /* For all latched-signal=up,Write original_signal to status */
5916 }
5917
5918 static void bnx2x_link_int_ack(struct link_params *params,
5919                                struct link_vars *vars, u8 is_10g_plus)
5920 {
5921         struct bnx2x *bp = params->bp;
5922         u8 port = params->port;
5923         u32 mask;
5924         /* First reset all status we assume only one line will be
5925          * change at a time
5926          */
5927         bnx2x_bits_dis(bp, NIG_REG_STATUS_INTERRUPT_PORT0 + port*4,
5928                        (NIG_STATUS_XGXS0_LINK10G |
5929                         NIG_STATUS_XGXS0_LINK_STATUS |
5930                         NIG_STATUS_SERDES0_LINK_STATUS));
5931         if (vars->phy_link_up) {
5932                 if (USES_WARPCORE(bp))
5933                         mask = NIG_STATUS_XGXS0_LINK_STATUS;
5934                 else {
5935                         if (is_10g_plus)
5936                                 mask = NIG_STATUS_XGXS0_LINK10G;
5937                         else if (params->switch_cfg == SWITCH_CFG_10G) {
5938                                 /* Disable the link interrupt by writing 1 to
5939                                  * the relevant lane in the status register
5940                                  */
5941                                 u32 ser_lane =
5942                                         ((params->lane_config &
5943                                     PORT_HW_CFG_LANE_SWAP_CFG_MASTER_MASK) >>
5944                                     PORT_HW_CFG_LANE_SWAP_CFG_MASTER_SHIFT);
5945                                 mask = ((1 << ser_lane) <<
5946                                        NIG_STATUS_XGXS0_LINK_STATUS_SIZE);
5947                         } else
5948                                 mask = NIG_STATUS_SERDES0_LINK_STATUS;
5949                 }
5950                 DP(NETIF_MSG_LINK, "Ack link up interrupt with mask 0x%x\n",
5951                                mask);
5952                 bnx2x_bits_en(bp,
5953                               NIG_REG_STATUS_INTERRUPT_PORT0 + port*4,
5954                               mask);
5955         }
5956 }
5957
5958 static int bnx2x_format_ver(u32 num, u8 *str, u16 *len)
5959 {
5960         u8 *str_ptr = str;
5961         u32 mask = 0xf0000000;
5962         u8 shift = 8*4;
5963         u8 digit;
5964         u8 remove_leading_zeros = 1;
5965         if (*len < 10) {
5966                 /* Need more than 10chars for this format */
5967                 *str_ptr = '\0';
5968                 (*len)--;
5969                 return -EINVAL;
5970         }
5971         while (shift > 0) {
5972
5973                 shift -= 4;
5974                 digit = ((num & mask) >> shift);
5975                 if (digit == 0 && remove_leading_zeros) {
5976                         mask = mask >> 4;
5977                         continue;
5978                 } else if (digit < 0xa)
5979                         *str_ptr = digit + '0';
5980                 else
5981                         *str_ptr = digit - 0xa + 'a';
5982                 remove_leading_zeros = 0;
5983                 str_ptr++;
5984                 (*len)--;
5985                 mask = mask >> 4;
5986                 if (shift == 4*4) {
5987                         *str_ptr = '.';
5988                         str_ptr++;
5989                         (*len)--;
5990                         remove_leading_zeros = 1;
5991                 }
5992         }
5993         return 0;
5994 }
5995
5996
5997 static int bnx2x_null_format_ver(u32 spirom_ver, u8 *str, u16 *len)
5998 {
5999         str[0] = '\0';
6000         (*len)--;
6001         return 0;
6002 }
6003
6004 int bnx2x_get_ext_phy_fw_version(struct link_params *params, u8 *version,
6005                                  u16 len)
6006 {
6007         struct bnx2x *bp;
6008         u32 spirom_ver = 0;
6009         int status = 0;
6010         u8 *ver_p = version;
6011         u16 remain_len = len;
6012         if (version == NULL || params == NULL)
6013                 return -EINVAL;
6014         bp = params->bp;
6015
6016         /* Extract first external phy*/
6017         version[0] = '\0';
6018         spirom_ver = REG_RD(bp, params->phy[EXT_PHY1].ver_addr);
6019
6020         if (params->phy[EXT_PHY1].format_fw_ver) {
6021                 status |= params->phy[EXT_PHY1].format_fw_ver(spirom_ver,
6022                                                               ver_p,
6023                                                               &remain_len);
6024                 ver_p += (len - remain_len);
6025         }
6026         if ((params->num_phys == MAX_PHYS) &&
6027             (params->phy[EXT_PHY2].ver_addr != 0)) {
6028                 spirom_ver = REG_RD(bp, params->phy[EXT_PHY2].ver_addr);
6029                 if (params->phy[EXT_PHY2].format_fw_ver) {
6030                         *ver_p = '/';
6031                         ver_p++;
6032                         remain_len--;
6033                         status |= params->phy[EXT_PHY2].format_fw_ver(
6034                                 spirom_ver,
6035                                 ver_p,
6036                                 &remain_len);
6037                         ver_p = version + (len - remain_len);
6038                 }
6039         }
6040         *ver_p = '\0';
6041         return status;
6042 }
6043
6044 static void bnx2x_set_xgxs_loopback(struct bnx2x_phy *phy,
6045                                     struct link_params *params)
6046 {
6047         u8 port = params->port;
6048         struct bnx2x *bp = params->bp;
6049
6050         if (phy->req_line_speed != SPEED_1000) {
6051                 u32 md_devad = 0;
6052
6053                 DP(NETIF_MSG_LINK, "XGXS 10G loopback enable\n");
6054
6055                 if (!CHIP_IS_E3(bp)) {
6056                         /* change the uni_phy_addr in the nig */
6057                         md_devad = REG_RD(bp, (NIG_REG_XGXS0_CTRL_MD_DEVAD +
6058                                                port*0x18));
6059
6060                         REG_WR(bp, NIG_REG_XGXS0_CTRL_MD_DEVAD + port*0x18,
6061                                0x5);
6062                 }
6063
6064                 bnx2x_cl45_write(bp, phy,
6065                                  5,
6066                                  (MDIO_REG_BANK_AER_BLOCK +
6067                                   (MDIO_AER_BLOCK_AER_REG & 0xf)),
6068                                  0x2800);
6069
6070                 bnx2x_cl45_write(bp, phy,
6071                                  5,
6072                                  (MDIO_REG_BANK_CL73_IEEEB0 +
6073                                   (MDIO_CL73_IEEEB0_CL73_AN_CONTROL & 0xf)),
6074                                  0x6041);
6075                 msleep(200);
6076                 /* set aer mmd back */
6077                 bnx2x_set_aer_mmd(params, phy);
6078
6079                 if (!CHIP_IS_E3(bp)) {
6080                         /* and md_devad */
6081                         REG_WR(bp, NIG_REG_XGXS0_CTRL_MD_DEVAD + port*0x18,
6082                                md_devad);
6083                 }
6084         } else {
6085                 u16 mii_ctrl;
6086                 DP(NETIF_MSG_LINK, "XGXS 1G loopback enable\n");
6087                 bnx2x_cl45_read(bp, phy, 5,
6088                                 (MDIO_REG_BANK_COMBO_IEEE0 +
6089                                 (MDIO_COMBO_IEEE0_MII_CONTROL & 0xf)),
6090                                 &mii_ctrl);
6091                 bnx2x_cl45_write(bp, phy, 5,
6092                                  (MDIO_REG_BANK_COMBO_IEEE0 +
6093                                  (MDIO_COMBO_IEEE0_MII_CONTROL & 0xf)),
6094                                  mii_ctrl |
6095                                  MDIO_COMBO_IEEO_MII_CONTROL_LOOPBACK);
6096         }
6097 }
6098
6099 int bnx2x_set_led(struct link_params *params,
6100                   struct link_vars *vars, u8 mode, u32 speed)
6101 {
6102         u8 port = params->port;
6103         u16 hw_led_mode = params->hw_led_mode;
6104         int rc = 0;
6105         u8 phy_idx;
6106         u32 tmp;
6107         u32 emac_base = port ? GRCBASE_EMAC1 : GRCBASE_EMAC0;
6108         struct bnx2x *bp = params->bp;
6109         DP(NETIF_MSG_LINK, "bnx2x_set_led: port %x, mode %d\n", port, mode);
6110         DP(NETIF_MSG_LINK, "speed 0x%x, hw_led_mode 0x%x\n",
6111                  speed, hw_led_mode);
6112         /* In case */
6113         for (phy_idx = EXT_PHY1; phy_idx < MAX_PHYS; phy_idx++) {
6114                 if (params->phy[phy_idx].set_link_led) {
6115                         params->phy[phy_idx].set_link_led(
6116                                 &params->phy[phy_idx], params, mode);
6117                 }
6118         }
6119
6120         switch (mode) {
6121         case LED_MODE_FRONT_PANEL_OFF:
6122         case LED_MODE_OFF:
6123                 REG_WR(bp, NIG_REG_LED_10G_P0 + port*4, 0);
6124                 REG_WR(bp, NIG_REG_LED_MODE_P0 + port*4,
6125                        SHARED_HW_CFG_LED_MAC1);
6126
6127                 tmp = EMAC_RD(bp, EMAC_REG_EMAC_LED);
6128                 if (params->phy[EXT_PHY1].type ==
6129                         PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM54618SE)
6130                         tmp &= ~(EMAC_LED_1000MB_OVERRIDE |
6131                                 EMAC_LED_100MB_OVERRIDE |
6132                                 EMAC_LED_10MB_OVERRIDE);
6133                 else
6134                         tmp |= EMAC_LED_OVERRIDE;
6135
6136                 EMAC_WR(bp, EMAC_REG_EMAC_LED, tmp);
6137                 break;
6138
6139         case LED_MODE_OPER:
6140                 /* For all other phys, OPER mode is same as ON, so in case
6141                  * link is down, do nothing
6142                  */
6143                 if (!vars->link_up)
6144                         break;
6145         case LED_MODE_ON:
6146                 if (((params->phy[EXT_PHY1].type ==
6147                           PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727) ||
6148                          (params->phy[EXT_PHY1].type ==
6149                           PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8722)) &&
6150                     CHIP_IS_E2(bp) && params->num_phys == 2) {
6151                         /* This is a work-around for E2+8727 Configurations */
6152                         if (mode == LED_MODE_ON ||
6153                                 speed == SPEED_10000){
6154                                 REG_WR(bp, NIG_REG_LED_MODE_P0 + port*4, 0);
6155                                 REG_WR(bp, NIG_REG_LED_10G_P0 + port*4, 1);
6156
6157                                 tmp = EMAC_RD(bp, EMAC_REG_EMAC_LED);
6158                                 EMAC_WR(bp, EMAC_REG_EMAC_LED,
6159                                         (tmp | EMAC_LED_OVERRIDE));
6160                                 /* Return here without enabling traffic
6161                                  * LED blink and setting rate in ON mode.
6162                                  * In oper mode, enabling LED blink
6163                                  * and setting rate is needed.
6164                                  */
6165                                 if (mode == LED_MODE_ON)
6166                                         return rc;
6167                         }
6168                 } else if (SINGLE_MEDIA_DIRECT(params)) {
6169                         /* This is a work-around for HW issue found when link
6170                          * is up in CL73
6171                          */
6172                         if ((!CHIP_IS_E3(bp)) ||
6173                             (CHIP_IS_E3(bp) &&
6174                              mode == LED_MODE_ON))
6175                                 REG_WR(bp, NIG_REG_LED_10G_P0 + port*4, 1);
6176
6177                         if (CHIP_IS_E1x(bp) ||
6178                             CHIP_IS_E2(bp) ||
6179                             (mode == LED_MODE_ON))
6180                                 REG_WR(bp, NIG_REG_LED_MODE_P0 + port*4, 0);
6181                         else
6182                                 REG_WR(bp, NIG_REG_LED_MODE_P0 + port*4,
6183                                        hw_led_mode);
6184                 } else if ((params->phy[EXT_PHY1].type ==
6185                             PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM54618SE) &&
6186                            (mode == LED_MODE_ON)) {
6187                         REG_WR(bp, NIG_REG_LED_MODE_P0 + port*4, 0);
6188                         tmp = EMAC_RD(bp, EMAC_REG_EMAC_LED);
6189                         EMAC_WR(bp, EMAC_REG_EMAC_LED, tmp |
6190                                 EMAC_LED_OVERRIDE | EMAC_LED_1000MB_OVERRIDE);
6191                         /* Break here; otherwise, it'll disable the
6192                          * intended override.
6193                          */
6194                         break;
6195                 } else
6196                         REG_WR(bp, NIG_REG_LED_MODE_P0 + port*4,
6197                                hw_led_mode);
6198
6199                 REG_WR(bp, NIG_REG_LED_CONTROL_OVERRIDE_TRAFFIC_P0 + port*4, 0);
6200                 /* Set blinking rate to ~15.9Hz */
6201                 if (CHIP_IS_E3(bp))
6202                         REG_WR(bp, NIG_REG_LED_CONTROL_BLINK_RATE_P0 + port*4,
6203                                LED_BLINK_RATE_VAL_E3);
6204                 else
6205                         REG_WR(bp, NIG_REG_LED_CONTROL_BLINK_RATE_P0 + port*4,
6206                                LED_BLINK_RATE_VAL_E1X_E2);
6207                 REG_WR(bp, NIG_REG_LED_CONTROL_BLINK_RATE_ENA_P0 +
6208                        port*4, 1);
6209                 tmp = EMAC_RD(bp, EMAC_REG_EMAC_LED);
6210                 EMAC_WR(bp, EMAC_REG_EMAC_LED,
6211                         (tmp & (~EMAC_LED_OVERRIDE)));
6212
6213                 if (CHIP_IS_E1(bp) &&
6214                     ((speed == SPEED_2500) ||
6215                      (speed == SPEED_1000) ||
6216                      (speed == SPEED_100) ||
6217                      (speed == SPEED_10))) {
6218                         /* For speeds less than 10G LED scheme is different */
6219                         REG_WR(bp, NIG_REG_LED_CONTROL_OVERRIDE_TRAFFIC_P0
6220                                + port*4, 1);
6221                         REG_WR(bp, NIG_REG_LED_CONTROL_TRAFFIC_P0 +
6222                                port*4, 0);
6223                         REG_WR(bp, NIG_REG_LED_CONTROL_BLINK_TRAFFIC_P0 +
6224                                port*4, 1);
6225                 }
6226                 break;
6227
6228         default:
6229                 rc = -EINVAL;
6230                 DP(NETIF_MSG_LINK, "bnx2x_set_led: Invalid led mode %d\n",
6231                          mode);
6232                 break;
6233         }
6234         return rc;
6235
6236 }
6237
6238 /* This function comes to reflect the actual link state read DIRECTLY from the
6239  * HW
6240  */
6241 int bnx2x_test_link(struct link_params *params, struct link_vars *vars,
6242                     u8 is_serdes)
6243 {
6244         struct bnx2x *bp = params->bp;
6245         u16 gp_status = 0, phy_index = 0;
6246         u8 ext_phy_link_up = 0, serdes_phy_type;
6247         struct link_vars temp_vars;
6248         struct bnx2x_phy *int_phy = &params->phy[INT_PHY];
6249
6250         if (CHIP_IS_E3(bp)) {
6251                 u16 link_up;
6252                 if (params->req_line_speed[LINK_CONFIG_IDX(INT_PHY)]
6253                     > SPEED_10000) {
6254                         /* Check 20G link */
6255                         bnx2x_cl45_read(bp, int_phy, MDIO_WC_DEVAD,
6256                                         1, &link_up);
6257                         bnx2x_cl45_read(bp, int_phy, MDIO_WC_DEVAD,
6258                                         1, &link_up);
6259                         link_up &= (1<<2);
6260                 } else {
6261                         /* Check 10G link and below*/
6262                         u8 lane = bnx2x_get_warpcore_lane(int_phy, params);
6263                         bnx2x_cl45_read(bp, int_phy, MDIO_WC_DEVAD,
6264                                         MDIO_WC_REG_GP2_STATUS_GP_2_1,
6265                                         &gp_status);
6266                         gp_status = ((gp_status >> 8) & 0xf) |
6267                                 ((gp_status >> 12) & 0xf);
6268                         link_up = gp_status & (1 << lane);
6269                 }
6270                 if (!link_up)
6271                         return -ESRCH;
6272         } else {
6273                 CL22_RD_OVER_CL45(bp, int_phy,
6274                           MDIO_REG_BANK_GP_STATUS,
6275                           MDIO_GP_STATUS_TOP_AN_STATUS1,
6276                           &gp_status);
6277         /* link is up only if both local phy and external phy are up */
6278         if (!(gp_status & MDIO_GP_STATUS_TOP_AN_STATUS1_LINK_STATUS))
6279                 return -ESRCH;
6280         }
6281         /* In XGXS loopback mode, do not check external PHY */
6282         if (params->loopback_mode == LOOPBACK_XGXS)
6283                 return 0;
6284
6285         switch (params->num_phys) {
6286         case 1:
6287                 /* No external PHY */
6288                 return 0;
6289         case 2:
6290                 ext_phy_link_up = params->phy[EXT_PHY1].read_status(
6291                         &params->phy[EXT_PHY1],
6292                         params, &temp_vars);
6293                 break;
6294         case 3: /* Dual Media */
6295                 for (phy_index = EXT_PHY1; phy_index < params->num_phys;
6296                       phy_index++) {
6297                         serdes_phy_type = ((params->phy[phy_index].media_type ==
6298                                             ETH_PHY_SFP_FIBER) ||
6299                                            (params->phy[phy_index].media_type ==
6300                                             ETH_PHY_XFP_FIBER) ||
6301                                            (params->phy[phy_index].media_type ==
6302                                             ETH_PHY_DA_TWINAX));
6303
6304                         if (is_serdes != serdes_phy_type)
6305                                 continue;
6306                         if (params->phy[phy_index].read_status) {
6307                                 ext_phy_link_up |=
6308                                         params->phy[phy_index].read_status(
6309                                                 &params->phy[phy_index],
6310                                                 params, &temp_vars);
6311                         }
6312                 }
6313                 break;
6314         }
6315         if (ext_phy_link_up)
6316                 return 0;
6317         return -ESRCH;
6318 }
6319
6320 static int bnx2x_link_initialize(struct link_params *params,
6321                                  struct link_vars *vars)
6322 {
6323         int rc = 0;
6324         u8 phy_index, non_ext_phy;
6325         struct bnx2x *bp = params->bp;
6326         /* In case of external phy existence, the line speed would be the
6327          * line speed linked up by the external phy. In case it is direct
6328          * only, then the line_speed during initialization will be
6329          * equal to the req_line_speed
6330          */
6331         vars->line_speed = params->phy[INT_PHY].req_line_speed;
6332
6333         /* Initialize the internal phy in case this is a direct board
6334          * (no external phys), or this board has external phy which requires
6335          * to first.
6336          */
6337         if (!USES_WARPCORE(bp))
6338                 bnx2x_prepare_xgxs(&params->phy[INT_PHY], params, vars);
6339         /* init ext phy and enable link state int */
6340         non_ext_phy = (SINGLE_MEDIA_DIRECT(params) ||
6341                        (params->loopback_mode == LOOPBACK_XGXS));
6342
6343         if (non_ext_phy ||
6344             (params->phy[EXT_PHY1].flags & FLAGS_INIT_XGXS_FIRST) ||
6345             (params->loopback_mode == LOOPBACK_EXT_PHY)) {
6346                 struct bnx2x_phy *phy = &params->phy[INT_PHY];
6347                 if (vars->line_speed == SPEED_AUTO_NEG &&
6348                     (CHIP_IS_E1x(bp) ||
6349                      CHIP_IS_E2(bp)))
6350                         bnx2x_set_parallel_detection(phy, params);
6351                         if (params->phy[INT_PHY].config_init)
6352                                 params->phy[INT_PHY].config_init(phy,
6353                                                                  params,
6354                                                                  vars);
6355         }
6356
6357         /* Init external phy*/
6358         if (non_ext_phy) {
6359                 if (params->phy[INT_PHY].supported &
6360                     SUPPORTED_FIBRE)
6361                         vars->link_status |= LINK_STATUS_SERDES_LINK;
6362         } else {
6363                 for (phy_index = EXT_PHY1; phy_index < params->num_phys;
6364                       phy_index++) {
6365                         /* No need to initialize second phy in case of first
6366                          * phy only selection. In case of second phy, we do
6367                          * need to initialize the first phy, since they are
6368                          * connected.
6369                          */
6370                         if (params->phy[phy_index].supported &
6371                             SUPPORTED_FIBRE)
6372                                 vars->link_status |= LINK_STATUS_SERDES_LINK;
6373
6374                         if (phy_index == EXT_PHY2 &&
6375                             (bnx2x_phy_selection(params) ==
6376                              PORT_HW_CFG_PHY_SELECTION_FIRST_PHY)) {
6377                                 DP(NETIF_MSG_LINK,
6378                                    "Not initializing second phy\n");
6379                                 continue;
6380                         }
6381                         params->phy[phy_index].config_init(
6382                                 &params->phy[phy_index],
6383                                 params, vars);
6384                 }
6385         }
6386         /* Reset the interrupt indication after phy was initialized */
6387         bnx2x_bits_dis(bp, NIG_REG_STATUS_INTERRUPT_PORT0 +
6388                        params->port*4,
6389                        (NIG_STATUS_XGXS0_LINK10G |
6390                         NIG_STATUS_XGXS0_LINK_STATUS |
6391                         NIG_STATUS_SERDES0_LINK_STATUS |
6392                         NIG_MASK_MI_INT));
6393         return rc;
6394 }
6395
6396 static void bnx2x_int_link_reset(struct bnx2x_phy *phy,
6397                                  struct link_params *params)
6398 {
6399         /* reset the SerDes/XGXS */
6400         REG_WR(params->bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_3_CLEAR,
6401                (0x1ff << (params->port*16)));
6402 }
6403
6404 static void bnx2x_common_ext_link_reset(struct bnx2x_phy *phy,
6405                                         struct link_params *params)
6406 {
6407         struct bnx2x *bp = params->bp;
6408         u8 gpio_port;
6409         /* HW reset */
6410         if (CHIP_IS_E2(bp))
6411                 gpio_port = BP_PATH(bp);
6412         else
6413                 gpio_port = params->port;
6414         bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_1,
6415                        MISC_REGISTERS_GPIO_OUTPUT_LOW,
6416                        gpio_port);
6417         bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_2,
6418                        MISC_REGISTERS_GPIO_OUTPUT_LOW,
6419                        gpio_port);
6420         DP(NETIF_MSG_LINK, "reset external PHY\n");
6421 }
6422
6423 static int bnx2x_update_link_down(struct link_params *params,
6424                                   struct link_vars *vars)
6425 {
6426         struct bnx2x *bp = params->bp;
6427         u8 port = params->port;
6428
6429         DP(NETIF_MSG_LINK, "Port %x: Link is down\n", port);
6430         bnx2x_set_led(params, vars, LED_MODE_OFF, 0);
6431         vars->phy_flags &= ~PHY_PHYSICAL_LINK_FLAG;
6432         /* indicate no mac active */
6433         vars->mac_type = MAC_TYPE_NONE;
6434
6435         /* update shared memory */
6436         vars->link_status &= ~(LINK_STATUS_SPEED_AND_DUPLEX_MASK |
6437                                LINK_STATUS_LINK_UP |
6438                                LINK_STATUS_PHYSICAL_LINK_FLAG |
6439                                LINK_STATUS_AUTO_NEGOTIATE_COMPLETE |
6440                                LINK_STATUS_RX_FLOW_CONTROL_FLAG_MASK |
6441                                LINK_STATUS_TX_FLOW_CONTROL_FLAG_MASK |
6442                                LINK_STATUS_PARALLEL_DETECTION_FLAG_MASK |
6443                                LINK_STATUS_LINK_PARTNER_SYMMETRIC_PAUSE |
6444                                LINK_STATUS_LINK_PARTNER_ASYMMETRIC_PAUSE);
6445         vars->line_speed = 0;
6446         bnx2x_update_mng(params, vars->link_status);
6447
6448         /* activate nig drain */
6449         REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE + port*4, 1);
6450
6451         /* disable emac */
6452         if (!CHIP_IS_E3(bp))
6453                 REG_WR(bp, NIG_REG_NIG_EMAC0_EN + port*4, 0);
6454
6455         msleep(10);
6456         /* reset BigMac/Xmac */
6457         if (CHIP_IS_E1x(bp) ||
6458             CHIP_IS_E2(bp)) {
6459                 bnx2x_bmac_rx_disable(bp, params->port);
6460                 REG_WR(bp, GRCBASE_MISC +
6461                        MISC_REGISTERS_RESET_REG_2_CLEAR,
6462                (MISC_REGISTERS_RESET_REG_2_RST_BMAC0 << port));
6463         }
6464         if (CHIP_IS_E3(bp)) {
6465                 bnx2x_xmac_disable(params);
6466                 bnx2x_umac_disable(params);
6467         }
6468
6469         return 0;
6470 }
6471
6472 static int bnx2x_update_link_up(struct link_params *params,
6473                                 struct link_vars *vars,
6474                                 u8 link_10g)
6475 {
6476         struct bnx2x *bp = params->bp;
6477         u8 phy_idx, port = params->port;
6478         int rc = 0;
6479
6480         vars->link_status |= (LINK_STATUS_LINK_UP |
6481                               LINK_STATUS_PHYSICAL_LINK_FLAG);
6482         vars->phy_flags |= PHY_PHYSICAL_LINK_FLAG;
6483
6484         if (vars->flow_ctrl & BNX2X_FLOW_CTRL_TX)
6485                 vars->link_status |=
6486                         LINK_STATUS_TX_FLOW_CONTROL_ENABLED;
6487
6488         if (vars->flow_ctrl & BNX2X_FLOW_CTRL_RX)
6489                 vars->link_status |=
6490                         LINK_STATUS_RX_FLOW_CONTROL_ENABLED;
6491         if (USES_WARPCORE(bp)) {
6492                 if (link_10g) {
6493                         if (bnx2x_xmac_enable(params, vars, 0) ==
6494                             -ESRCH) {
6495                                 DP(NETIF_MSG_LINK, "Found errors on XMAC\n");
6496                                 vars->link_up = 0;
6497                                 vars->phy_flags |= PHY_HALF_OPEN_CONN_FLAG;
6498                                 vars->link_status &= ~LINK_STATUS_LINK_UP;
6499                         }
6500                 } else
6501                         bnx2x_umac_enable(params, vars, 0);
6502                 bnx2x_set_led(params, vars,
6503                               LED_MODE_OPER, vars->line_speed);
6504         }
6505         if ((CHIP_IS_E1x(bp) ||
6506              CHIP_IS_E2(bp))) {
6507                 if (link_10g) {
6508                         if (bnx2x_bmac_enable(params, vars, 0) ==
6509                             -ESRCH) {
6510                                 DP(NETIF_MSG_LINK, "Found errors on BMAC\n");
6511                                 vars->link_up = 0;
6512                                 vars->phy_flags |= PHY_HALF_OPEN_CONN_FLAG;
6513                                 vars->link_status &= ~LINK_STATUS_LINK_UP;
6514                         }
6515
6516                         bnx2x_set_led(params, vars,
6517                                       LED_MODE_OPER, SPEED_10000);
6518                 } else {
6519                         rc = bnx2x_emac_program(params, vars);
6520                         bnx2x_emac_enable(params, vars, 0);
6521
6522                         /* AN complete? */
6523                         if ((vars->link_status &
6524                              LINK_STATUS_AUTO_NEGOTIATE_COMPLETE)
6525                             && (!(vars->phy_flags & PHY_SGMII_FLAG)) &&
6526                             SINGLE_MEDIA_DIRECT(params))
6527                                 bnx2x_set_gmii_tx_driver(params);
6528                 }
6529         }
6530
6531         /* PBF - link up */
6532         if (CHIP_IS_E1x(bp))
6533                 rc |= bnx2x_pbf_update(params, vars->flow_ctrl,
6534                                        vars->line_speed);
6535
6536         /* disable drain */
6537         REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE + port*4, 0);
6538
6539         /* update shared memory */
6540         bnx2x_update_mng(params, vars->link_status);
6541
6542         /* Check remote fault */
6543         for (phy_idx = INT_PHY; phy_idx < MAX_PHYS; phy_idx++) {
6544                 if (params->phy[phy_idx].flags & FLAGS_TX_ERROR_CHECK) {
6545                         bnx2x_check_half_open_conn(params, vars, 0);
6546                         break;
6547                 }
6548         }
6549         msleep(20);
6550         return rc;
6551 }
6552 /* The bnx2x_link_update function should be called upon link
6553  * interrupt.
6554  * Link is considered up as follows:
6555  * - DIRECT_SINGLE_MEDIA - Only XGXS link (internal link) needs
6556  *   to be up
6557  * - SINGLE_MEDIA - The link between the 577xx and the external
6558  *   phy (XGXS) need to up as well as the external link of the
6559  *   phy (PHY_EXT1)
6560  * - DUAL_MEDIA - The link between the 577xx and the first
6561  *   external phy needs to be up, and at least one of the 2
6562  *   external phy link must be up.
6563  */
6564 int bnx2x_link_update(struct link_params *params, struct link_vars *vars)
6565 {
6566         struct bnx2x *bp = params->bp;
6567         struct link_vars phy_vars[MAX_PHYS];
6568         u8 port = params->port;
6569         u8 link_10g_plus, phy_index;
6570         u8 ext_phy_link_up = 0, cur_link_up;
6571         int rc = 0;
6572         u8 is_mi_int = 0;
6573         u16 ext_phy_line_speed = 0, prev_line_speed = vars->line_speed;
6574         u8 active_external_phy = INT_PHY;
6575         vars->phy_flags &= ~PHY_HALF_OPEN_CONN_FLAG;
6576         for (phy_index = INT_PHY; phy_index < params->num_phys;
6577               phy_index++) {
6578                 phy_vars[phy_index].flow_ctrl = 0;
6579                 phy_vars[phy_index].link_status = 0;
6580                 phy_vars[phy_index].line_speed = 0;
6581                 phy_vars[phy_index].duplex = DUPLEX_FULL;
6582                 phy_vars[phy_index].phy_link_up = 0;
6583                 phy_vars[phy_index].link_up = 0;
6584                 phy_vars[phy_index].fault_detected = 0;
6585         }
6586
6587         if (USES_WARPCORE(bp))
6588                 bnx2x_set_aer_mmd(params, &params->phy[INT_PHY]);
6589
6590         DP(NETIF_MSG_LINK, "port %x, XGXS?%x, int_status 0x%x\n",
6591                  port, (vars->phy_flags & PHY_XGXS_FLAG),
6592                  REG_RD(bp, NIG_REG_STATUS_INTERRUPT_PORT0 + port*4));
6593
6594         is_mi_int = (u8)(REG_RD(bp, NIG_REG_EMAC0_STATUS_MISC_MI_INT +
6595                                 port*0x18) > 0);
6596         DP(NETIF_MSG_LINK, "int_mask 0x%x MI_INT %x, SERDES_LINK %x\n",
6597                  REG_RD(bp, NIG_REG_MASK_INTERRUPT_PORT0 + port*4),
6598                  is_mi_int,
6599                  REG_RD(bp, NIG_REG_SERDES0_STATUS_LINK_STATUS + port*0x3c));
6600
6601         DP(NETIF_MSG_LINK, " 10G %x, XGXS_LINK %x\n",
6602           REG_RD(bp, NIG_REG_XGXS0_STATUS_LINK10G + port*0x68),
6603           REG_RD(bp, NIG_REG_XGXS0_STATUS_LINK_STATUS + port*0x68));
6604
6605         /* disable emac */
6606         if (!CHIP_IS_E3(bp))
6607                 REG_WR(bp, NIG_REG_NIG_EMAC0_EN + port*4, 0);
6608
6609         /* Step 1:
6610          * Check external link change only for external phys, and apply
6611          * priority selection between them in case the link on both phys
6612          * is up. Note that instead of the common vars, a temporary
6613          * vars argument is used since each phy may have different link/
6614          * speed/duplex result
6615          */
6616         for (phy_index = EXT_PHY1; phy_index < params->num_phys;
6617               phy_index++) {
6618                 struct bnx2x_phy *phy = &params->phy[phy_index];
6619                 if (!phy->read_status)
6620                         continue;
6621                 /* Read link status and params of this ext phy */
6622                 cur_link_up = phy->read_status(phy, params,
6623                                                &phy_vars[phy_index]);
6624                 if (cur_link_up) {
6625                         DP(NETIF_MSG_LINK, "phy in index %d link is up\n",
6626                                    phy_index);
6627                 } else {
6628                         DP(NETIF_MSG_LINK, "phy in index %d link is down\n",
6629                                    phy_index);
6630                         continue;
6631                 }
6632
6633                 if (!ext_phy_link_up) {
6634                         ext_phy_link_up = 1;
6635                         active_external_phy = phy_index;
6636                 } else {
6637                         switch (bnx2x_phy_selection(params)) {
6638                         case PORT_HW_CFG_PHY_SELECTION_HARDWARE_DEFAULT:
6639                         case PORT_HW_CFG_PHY_SELECTION_FIRST_PHY_PRIORITY:
6640                         /* In this option, the first PHY makes sure to pass the
6641                          * traffic through itself only.
6642                          * Its not clear how to reset the link on the second phy
6643                          */
6644                                 active_external_phy = EXT_PHY1;
6645                                 break;
6646                         case PORT_HW_CFG_PHY_SELECTION_SECOND_PHY_PRIORITY:
6647                         /* In this option, the first PHY makes sure to pass the
6648                          * traffic through the second PHY.
6649                          */
6650                                 active_external_phy = EXT_PHY2;
6651                                 break;
6652                         default:
6653                         /* Link indication on both PHYs with the following cases
6654                          * is invalid:
6655                          * - FIRST_PHY means that second phy wasn't initialized,
6656                          * hence its link is expected to be down
6657                          * - SECOND_PHY means that first phy should not be able
6658                          * to link up by itself (using configuration)
6659                          * - DEFAULT should be overriden during initialiazation
6660                          */
6661                                 DP(NETIF_MSG_LINK, "Invalid link indication"
6662                                            "mpc=0x%x. DISABLING LINK !!!\n",
6663                                            params->multi_phy_config);
6664                                 ext_phy_link_up = 0;
6665                                 break;
6666                         }
6667                 }
6668         }
6669         prev_line_speed = vars->line_speed;
6670         /* Step 2:
6671          * Read the status of the internal phy. In case of
6672          * DIRECT_SINGLE_MEDIA board, this link is the external link,
6673          * otherwise this is the link between the 577xx and the first
6674          * external phy
6675          */
6676         if (params->phy[INT_PHY].read_status)
6677                 params->phy[INT_PHY].read_status(
6678                         &params->phy[INT_PHY],
6679                         params, vars);
6680         /* The INT_PHY flow control reside in the vars. This include the
6681          * case where the speed or flow control are not set to AUTO.
6682          * Otherwise, the active external phy flow control result is set
6683          * to the vars. The ext_phy_line_speed is needed to check if the
6684          * speed is different between the internal phy and external phy.
6685          * This case may be result of intermediate link speed change.
6686          */
6687         if (active_external_phy > INT_PHY) {
6688                 vars->flow_ctrl = phy_vars[active_external_phy].flow_ctrl;
6689                 /* Link speed is taken from the XGXS. AN and FC result from
6690                  * the external phy.
6691                  */
6692                 vars->link_status |= phy_vars[active_external_phy].link_status;
6693
6694                 /* if active_external_phy is first PHY and link is up - disable
6695                  * disable TX on second external PHY
6696                  */
6697                 if (active_external_phy == EXT_PHY1) {
6698                         if (params->phy[EXT_PHY2].phy_specific_func) {
6699                                 DP(NETIF_MSG_LINK,
6700                                    "Disabling TX on EXT_PHY2\n");
6701                                 params->phy[EXT_PHY2].phy_specific_func(
6702                                         &params->phy[EXT_PHY2],
6703                                         params, DISABLE_TX);
6704                         }
6705                 }
6706
6707                 ext_phy_line_speed = phy_vars[active_external_phy].line_speed;
6708                 vars->duplex = phy_vars[active_external_phy].duplex;
6709                 if (params->phy[active_external_phy].supported &
6710                     SUPPORTED_FIBRE)
6711                         vars->link_status |= LINK_STATUS_SERDES_LINK;
6712                 else
6713                         vars->link_status &= ~LINK_STATUS_SERDES_LINK;
6714                 DP(NETIF_MSG_LINK, "Active external phy selected: %x\n",
6715                            active_external_phy);
6716         }
6717
6718         for (phy_index = EXT_PHY1; phy_index < params->num_phys;
6719               phy_index++) {
6720                 if (params->phy[phy_index].flags &
6721                     FLAGS_REARM_LATCH_SIGNAL) {
6722                         bnx2x_rearm_latch_signal(bp, port,
6723                                                  phy_index ==
6724                                                  active_external_phy);
6725                         break;
6726                 }
6727         }
6728         DP(NETIF_MSG_LINK, "vars->flow_ctrl = 0x%x, vars->link_status = 0x%x,"
6729                    " ext_phy_line_speed = %d\n", vars->flow_ctrl,
6730                    vars->link_status, ext_phy_line_speed);
6731         /* Upon link speed change set the NIG into drain mode. Comes to
6732          * deals with possible FIFO glitch due to clk change when speed
6733          * is decreased without link down indicator
6734          */
6735
6736         if (vars->phy_link_up) {
6737                 if (!(SINGLE_MEDIA_DIRECT(params)) && ext_phy_link_up &&
6738                     (ext_phy_line_speed != vars->line_speed)) {
6739                         DP(NETIF_MSG_LINK, "Internal link speed %d is"
6740                                    " different than the external"
6741                                    " link speed %d\n", vars->line_speed,
6742                                    ext_phy_line_speed);
6743                         vars->phy_link_up = 0;
6744                 } else if (prev_line_speed != vars->line_speed) {
6745                         REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE + params->port*4,
6746                                0);
6747                         msleep(1);
6748                 }
6749         }
6750
6751         /* anything 10 and over uses the bmac */
6752         link_10g_plus = (vars->line_speed >= SPEED_10000);
6753
6754         bnx2x_link_int_ack(params, vars, link_10g_plus);
6755
6756         /* In case external phy link is up, and internal link is down
6757          * (not initialized yet probably after link initialization, it
6758          * needs to be initialized.
6759          * Note that after link down-up as result of cable plug, the xgxs
6760          * link would probably become up again without the need
6761          * initialize it
6762          */
6763         if (!(SINGLE_MEDIA_DIRECT(params))) {
6764                 DP(NETIF_MSG_LINK, "ext_phy_link_up = %d, int_link_up = %d,"
6765                            " init_preceding = %d\n", ext_phy_link_up,
6766                            vars->phy_link_up,
6767                            params->phy[EXT_PHY1].flags &
6768                            FLAGS_INIT_XGXS_FIRST);
6769                 if (!(params->phy[EXT_PHY1].flags &
6770                       FLAGS_INIT_XGXS_FIRST)
6771                     && ext_phy_link_up && !vars->phy_link_up) {
6772                         vars->line_speed = ext_phy_line_speed;
6773                         if (vars->line_speed < SPEED_1000)
6774                                 vars->phy_flags |= PHY_SGMII_FLAG;
6775                         else
6776                                 vars->phy_flags &= ~PHY_SGMII_FLAG;
6777
6778                         if (params->phy[INT_PHY].config_init)
6779                                 params->phy[INT_PHY].config_init(
6780                                         &params->phy[INT_PHY], params,
6781                                                 vars);
6782                 }
6783         }
6784         /* Link is up only if both local phy and external phy (in case of
6785          * non-direct board) are up and no fault detected on active PHY.
6786          */
6787         vars->link_up = (vars->phy_link_up &&
6788                          (ext_phy_link_up ||
6789                           SINGLE_MEDIA_DIRECT(params)) &&
6790                          (phy_vars[active_external_phy].fault_detected == 0));
6791
6792         /* Update the PFC configuration in case it was changed */
6793         if (params->feature_config_flags & FEATURE_CONFIG_PFC_ENABLED)
6794                 vars->link_status |= LINK_STATUS_PFC_ENABLED;
6795         else
6796                 vars->link_status &= ~LINK_STATUS_PFC_ENABLED;
6797
6798         if (vars->link_up)
6799                 rc = bnx2x_update_link_up(params, vars, link_10g_plus);
6800         else
6801                 rc = bnx2x_update_link_down(params, vars);
6802
6803         return rc;
6804 }
6805
6806 /*****************************************************************************/
6807 /*                          External Phy section                             */
6808 /*****************************************************************************/
6809 void bnx2x_ext_phy_hw_reset(struct bnx2x *bp, u8 port)
6810 {
6811         bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_1,
6812                        MISC_REGISTERS_GPIO_OUTPUT_LOW, port);
6813         msleep(1);
6814         bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_1,
6815                        MISC_REGISTERS_GPIO_OUTPUT_HIGH, port);
6816 }
6817
6818 static void bnx2x_save_spirom_version(struct bnx2x *bp, u8 port,
6819                                       u32 spirom_ver, u32 ver_addr)
6820 {
6821         DP(NETIF_MSG_LINK, "FW version 0x%x:0x%x for port %d\n",
6822                  (u16)(spirom_ver>>16), (u16)spirom_ver, port);
6823
6824         if (ver_addr)
6825                 REG_WR(bp, ver_addr, spirom_ver);
6826 }
6827
6828 static void bnx2x_save_bcm_spirom_ver(struct bnx2x *bp,
6829                                       struct bnx2x_phy *phy,
6830                                       u8 port)
6831 {
6832         u16 fw_ver1, fw_ver2;
6833
6834         bnx2x_cl45_read(bp, phy, MDIO_PMA_DEVAD,
6835                         MDIO_PMA_REG_ROM_VER1, &fw_ver1);
6836         bnx2x_cl45_read(bp, phy, MDIO_PMA_DEVAD,
6837                         MDIO_PMA_REG_ROM_VER2, &fw_ver2);
6838         bnx2x_save_spirom_version(bp, port, (u32)(fw_ver1<<16 | fw_ver2),
6839                                   phy->ver_addr);
6840 }
6841
6842 static void bnx2x_ext_phy_10G_an_resolve(struct bnx2x *bp,
6843                                        struct bnx2x_phy *phy,
6844                                        struct link_vars *vars)
6845 {
6846         u16 val;
6847         bnx2x_cl45_read(bp, phy,
6848                         MDIO_AN_DEVAD,
6849                         MDIO_AN_REG_STATUS, &val);
6850         bnx2x_cl45_read(bp, phy,
6851                         MDIO_AN_DEVAD,
6852                         MDIO_AN_REG_STATUS, &val);
6853         if (val & (1<<5))
6854                 vars->link_status |= LINK_STATUS_AUTO_NEGOTIATE_COMPLETE;
6855         if ((val & (1<<0)) == 0)
6856                 vars->link_status |= LINK_STATUS_PARALLEL_DETECTION_USED;
6857 }
6858
6859 /******************************************************************/
6860 /*              common BCM8073/BCM8727 PHY SECTION                */
6861 /******************************************************************/
6862 static void bnx2x_8073_resolve_fc(struct bnx2x_phy *phy,
6863                                   struct link_params *params,
6864                                   struct link_vars *vars)
6865 {
6866         struct bnx2x *bp = params->bp;
6867         if (phy->req_line_speed == SPEED_10 ||
6868             phy->req_line_speed == SPEED_100) {
6869                 vars->flow_ctrl = phy->req_flow_ctrl;
6870                 return;
6871         }
6872
6873         if (bnx2x_ext_phy_resolve_fc(phy, params, vars) &&
6874             (vars->flow_ctrl == BNX2X_FLOW_CTRL_NONE)) {
6875                 u16 pause_result;
6876                 u16 ld_pause;           /* local */
6877                 u16 lp_pause;           /* link partner */
6878                 bnx2x_cl45_read(bp, phy,
6879                                 MDIO_AN_DEVAD,
6880                                 MDIO_AN_REG_CL37_FC_LD, &ld_pause);
6881
6882                 bnx2x_cl45_read(bp, phy,
6883                                 MDIO_AN_DEVAD,
6884                                 MDIO_AN_REG_CL37_FC_LP, &lp_pause);
6885                 pause_result = (ld_pause &
6886                                 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH) >> 5;
6887                 pause_result |= (lp_pause &
6888                                  MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH) >> 7;
6889
6890                 bnx2x_pause_resolve(vars, pause_result);
6891                 DP(NETIF_MSG_LINK, "Ext PHY CL37 pause result 0x%x\n",
6892                            pause_result);
6893         }
6894 }
6895 static int bnx2x_8073_8727_external_rom_boot(struct bnx2x *bp,
6896                                              struct bnx2x_phy *phy,
6897                                              u8 port)
6898 {
6899         u32 count = 0;
6900         u16 fw_ver1, fw_msgout;
6901         int rc = 0;
6902
6903         /* Boot port from external ROM  */
6904         /* EDC grst */
6905         bnx2x_cl45_write(bp, phy,
6906                          MDIO_PMA_DEVAD,
6907                          MDIO_PMA_REG_GEN_CTRL,
6908                          0x0001);
6909
6910         /* ucode reboot and rst */
6911         bnx2x_cl45_write(bp, phy,
6912                          MDIO_PMA_DEVAD,
6913                          MDIO_PMA_REG_GEN_CTRL,
6914                          0x008c);
6915
6916         bnx2x_cl45_write(bp, phy,
6917                          MDIO_PMA_DEVAD,
6918                          MDIO_PMA_REG_MISC_CTRL1, 0x0001);
6919
6920         /* Reset internal microprocessor */
6921         bnx2x_cl45_write(bp, phy,
6922                          MDIO_PMA_DEVAD,
6923                          MDIO_PMA_REG_GEN_CTRL,
6924                          MDIO_PMA_REG_GEN_CTRL_ROM_MICRO_RESET);
6925
6926         /* Release srst bit */
6927         bnx2x_cl45_write(bp, phy,
6928                          MDIO_PMA_DEVAD,
6929                          MDIO_PMA_REG_GEN_CTRL,
6930                          MDIO_PMA_REG_GEN_CTRL_ROM_RESET_INTERNAL_MP);
6931
6932         /* Delay 100ms per the PHY specifications */
6933         msleep(100);
6934
6935         /* 8073 sometimes taking longer to download */
6936         do {
6937                 count++;
6938                 if (count > 300) {
6939                         DP(NETIF_MSG_LINK,
6940                                  "bnx2x_8073_8727_external_rom_boot port %x:"
6941                                  "Download failed. fw version = 0x%x\n",
6942                                  port, fw_ver1);
6943                         rc = -EINVAL;
6944                         break;
6945                 }
6946
6947                 bnx2x_cl45_read(bp, phy,
6948                                 MDIO_PMA_DEVAD,
6949                                 MDIO_PMA_REG_ROM_VER1, &fw_ver1);
6950                 bnx2x_cl45_read(bp, phy,
6951                                 MDIO_PMA_DEVAD,
6952                                 MDIO_PMA_REG_M8051_MSGOUT_REG, &fw_msgout);
6953
6954                 msleep(1);
6955         } while (fw_ver1 == 0 || fw_ver1 == 0x4321 ||
6956                         ((fw_msgout & 0xff) != 0x03 && (phy->type ==
6957                         PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073)));
6958
6959         /* Clear ser_boot_ctl bit */
6960         bnx2x_cl45_write(bp, phy,
6961                          MDIO_PMA_DEVAD,
6962                          MDIO_PMA_REG_MISC_CTRL1, 0x0000);
6963         bnx2x_save_bcm_spirom_ver(bp, phy, port);
6964
6965         DP(NETIF_MSG_LINK,
6966                  "bnx2x_8073_8727_external_rom_boot port %x:"
6967                  "Download complete. fw version = 0x%x\n",
6968                  port, fw_ver1);
6969
6970         return rc;
6971 }
6972
6973 /******************************************************************/
6974 /*                      BCM8073 PHY SECTION                       */
6975 /******************************************************************/
6976 static int bnx2x_8073_is_snr_needed(struct bnx2x *bp, struct bnx2x_phy *phy)
6977 {
6978         /* This is only required for 8073A1, version 102 only */
6979         u16 val;
6980
6981         /* Read 8073 HW revision*/
6982         bnx2x_cl45_read(bp, phy,
6983                         MDIO_PMA_DEVAD,
6984                         MDIO_PMA_REG_8073_CHIP_REV, &val);
6985
6986         if (val != 1) {
6987                 /* No need to workaround in 8073 A1 */
6988                 return 0;
6989         }
6990
6991         bnx2x_cl45_read(bp, phy,
6992                         MDIO_PMA_DEVAD,
6993                         MDIO_PMA_REG_ROM_VER2, &val);
6994
6995         /* SNR should be applied only for version 0x102 */
6996         if (val != 0x102)
6997                 return 0;
6998
6999         return 1;
7000 }
7001
7002 static int bnx2x_8073_xaui_wa(struct bnx2x *bp, struct bnx2x_phy *phy)
7003 {
7004         u16 val, cnt, cnt1 ;
7005
7006         bnx2x_cl45_read(bp, phy,
7007                         MDIO_PMA_DEVAD,
7008                         MDIO_PMA_REG_8073_CHIP_REV, &val);
7009
7010         if (val > 0) {
7011                 /* No need to workaround in 8073 A1 */
7012                 return 0;
7013         }
7014         /* XAUI workaround in 8073 A0: */
7015
7016         /* After loading the boot ROM and restarting Autoneg, poll
7017          * Dev1, Reg $C820:
7018          */
7019
7020         for (cnt = 0; cnt < 1000; cnt++) {
7021                 bnx2x_cl45_read(bp, phy,
7022                                 MDIO_PMA_DEVAD,
7023                                 MDIO_PMA_REG_8073_SPEED_LINK_STATUS,
7024                                 &val);
7025                   /* If bit [14] = 0 or bit [13] = 0, continue on with
7026                    * system initialization (XAUI work-around not required, as
7027                    * these bits indicate 2.5G or 1G link up).
7028                    */
7029                 if (!(val & (1<<14)) || !(val & (1<<13))) {
7030                         DP(NETIF_MSG_LINK, "XAUI work-around not required\n");
7031                         return 0;
7032                 } else if (!(val & (1<<15))) {
7033                         DP(NETIF_MSG_LINK, "bit 15 went off\n");
7034                         /* If bit 15 is 0, then poll Dev1, Reg $C841 until it's
7035                          * MSB (bit15) goes to 1 (indicating that the XAUI
7036                          * workaround has completed), then continue on with
7037                          * system initialization.
7038                          */
7039                         for (cnt1 = 0; cnt1 < 1000; cnt1++) {
7040                                 bnx2x_cl45_read(bp, phy,
7041                                         MDIO_PMA_DEVAD,
7042                                         MDIO_PMA_REG_8073_XAUI_WA, &val);
7043                                 if (val & (1<<15)) {
7044                                         DP(NETIF_MSG_LINK,
7045                                           "XAUI workaround has completed\n");
7046                                         return 0;
7047                                  }
7048                                  msleep(3);
7049                         }
7050                         break;
7051                 }
7052                 msleep(3);
7053         }
7054         DP(NETIF_MSG_LINK, "Warning: XAUI work-around timeout !!!\n");
7055         return -EINVAL;
7056 }
7057
7058 static void bnx2x_807x_force_10G(struct bnx2x *bp, struct bnx2x_phy *phy)
7059 {
7060         /* Force KR or KX */
7061         bnx2x_cl45_write(bp, phy,
7062                          MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 0x2040);
7063         bnx2x_cl45_write(bp, phy,
7064                          MDIO_PMA_DEVAD, MDIO_PMA_REG_10G_CTRL2, 0x000b);
7065         bnx2x_cl45_write(bp, phy,
7066                          MDIO_PMA_DEVAD, MDIO_PMA_REG_BCM_CTRL, 0x0000);
7067         bnx2x_cl45_write(bp, phy,
7068                          MDIO_AN_DEVAD, MDIO_AN_REG_CTRL, 0x0000);
7069 }
7070
7071 static void bnx2x_8073_set_pause_cl37(struct link_params *params,
7072                                       struct bnx2x_phy *phy,
7073                                       struct link_vars *vars)
7074 {
7075         u16 cl37_val;
7076         struct bnx2x *bp = params->bp;
7077         bnx2x_cl45_read(bp, phy,
7078                         MDIO_AN_DEVAD, MDIO_AN_REG_CL37_FC_LD, &cl37_val);
7079
7080         cl37_val &= ~MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH;
7081         /* Please refer to Table 28B-3 of 802.3ab-1999 spec. */
7082         bnx2x_calc_ieee_aneg_adv(phy, params, &vars->ieee_fc);
7083         if ((vars->ieee_fc &
7084             MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_SYMMETRIC) ==
7085             MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_SYMMETRIC) {
7086                 cl37_val |=  MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_SYMMETRIC;
7087         }
7088         if ((vars->ieee_fc &
7089             MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC) ==
7090             MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC) {
7091                 cl37_val |=  MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC;
7092         }
7093         if ((vars->ieee_fc &
7094             MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH) ==
7095             MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH) {
7096                 cl37_val |= MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH;
7097         }
7098         DP(NETIF_MSG_LINK,
7099                  "Ext phy AN advertize cl37 0x%x\n", cl37_val);
7100
7101         bnx2x_cl45_write(bp, phy,
7102                          MDIO_AN_DEVAD, MDIO_AN_REG_CL37_FC_LD, cl37_val);
7103         msleep(500);
7104 }
7105
7106 static int bnx2x_8073_config_init(struct bnx2x_phy *phy,
7107                                   struct link_params *params,
7108                                   struct link_vars *vars)
7109 {
7110         struct bnx2x *bp = params->bp;
7111         u16 val = 0, tmp1;
7112         u8 gpio_port;
7113         DP(NETIF_MSG_LINK, "Init 8073\n");
7114
7115         if (CHIP_IS_E2(bp))
7116                 gpio_port = BP_PATH(bp);
7117         else
7118                 gpio_port = params->port;
7119         /* Restore normal power mode*/
7120         bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_2,
7121                        MISC_REGISTERS_GPIO_OUTPUT_HIGH, gpio_port);
7122
7123         bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_1,
7124                        MISC_REGISTERS_GPIO_OUTPUT_HIGH, gpio_port);
7125
7126         /* enable LASI */
7127         bnx2x_cl45_write(bp, phy,
7128                          MDIO_PMA_DEVAD, MDIO_PMA_LASI_RXCTRL, (1<<2));
7129         bnx2x_cl45_write(bp, phy,
7130                          MDIO_PMA_DEVAD, MDIO_PMA_LASI_CTRL,  0x0004);
7131
7132         bnx2x_8073_set_pause_cl37(params, phy, vars);
7133
7134         bnx2x_cl45_read(bp, phy,
7135                         MDIO_PMA_DEVAD, MDIO_PMA_REG_M8051_MSGOUT_REG, &tmp1);
7136
7137         bnx2x_cl45_read(bp, phy,
7138                         MDIO_PMA_DEVAD, MDIO_PMA_LASI_RXSTAT, &tmp1);
7139
7140         DP(NETIF_MSG_LINK, "Before rom RX_ALARM(port1): 0x%x\n", tmp1);
7141
7142         /* Swap polarity if required - Must be done only in non-1G mode */
7143         if (params->lane_config & PORT_HW_CFG_SWAP_PHY_POLARITY_ENABLED) {
7144                 /* Configure the 8073 to swap _P and _N of the KR lines */
7145                 DP(NETIF_MSG_LINK, "Swapping polarity for the 8073\n");
7146                 /* 10G Rx/Tx and 1G Tx signal polarity swap */
7147                 bnx2x_cl45_read(bp, phy,
7148                                 MDIO_PMA_DEVAD,
7149                                 MDIO_PMA_REG_8073_OPT_DIGITAL_CTRL, &val);
7150                 bnx2x_cl45_write(bp, phy,
7151                                  MDIO_PMA_DEVAD,
7152                                  MDIO_PMA_REG_8073_OPT_DIGITAL_CTRL,
7153                                  (val | (3<<9)));
7154         }
7155
7156
7157         /* Enable CL37 BAM */
7158         if (REG_RD(bp, params->shmem_base +
7159                          offsetof(struct shmem_region, dev_info.
7160                                   port_hw_config[params->port].default_cfg)) &
7161             PORT_HW_CFG_ENABLE_BAM_ON_KR_ENABLED) {
7162
7163                 bnx2x_cl45_read(bp, phy,
7164                                 MDIO_AN_DEVAD,
7165                                 MDIO_AN_REG_8073_BAM, &val);
7166                 bnx2x_cl45_write(bp, phy,
7167                                  MDIO_AN_DEVAD,
7168                                  MDIO_AN_REG_8073_BAM, val | 1);
7169                 DP(NETIF_MSG_LINK, "Enable CL37 BAM on KR\n");
7170         }
7171         if (params->loopback_mode == LOOPBACK_EXT) {
7172                 bnx2x_807x_force_10G(bp, phy);
7173                 DP(NETIF_MSG_LINK, "Forced speed 10G on 807X\n");
7174                 return 0;
7175         } else {
7176                 bnx2x_cl45_write(bp, phy,
7177                                  MDIO_PMA_DEVAD, MDIO_PMA_REG_BCM_CTRL, 0x0002);
7178         }
7179         if (phy->req_line_speed != SPEED_AUTO_NEG) {
7180                 if (phy->req_line_speed == SPEED_10000) {
7181                         val = (1<<7);
7182                 } else if (phy->req_line_speed ==  SPEED_2500) {
7183                         val = (1<<5);
7184                         /* Note that 2.5G works only when used with 1G
7185                          * advertisement
7186                          */
7187                 } else
7188                         val = (1<<5);
7189         } else {
7190                 val = 0;
7191                 if (phy->speed_cap_mask &
7192                         PORT_HW_CFG_SPEED_CAPABILITY_D0_10G)
7193                         val |= (1<<7);
7194
7195                 /* Note that 2.5G works only when used with 1G advertisement */
7196                 if (phy->speed_cap_mask &
7197                         (PORT_HW_CFG_SPEED_CAPABILITY_D0_1G |
7198                          PORT_HW_CFG_SPEED_CAPABILITY_D0_2_5G))
7199                         val |= (1<<5);
7200                 DP(NETIF_MSG_LINK, "807x autoneg val = 0x%x\n", val);
7201         }
7202
7203         bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_ADV, val);
7204         bnx2x_cl45_read(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_8073_2_5G, &tmp1);
7205
7206         if (((phy->speed_cap_mask & PORT_HW_CFG_SPEED_CAPABILITY_D0_2_5G) &&
7207              (phy->req_line_speed == SPEED_AUTO_NEG)) ||
7208             (phy->req_line_speed == SPEED_2500)) {
7209                 u16 phy_ver;
7210                 /* Allow 2.5G for A1 and above */
7211                 bnx2x_cl45_read(bp, phy,
7212                                 MDIO_PMA_DEVAD, MDIO_PMA_REG_8073_CHIP_REV,
7213                                 &phy_ver);
7214                 DP(NETIF_MSG_LINK, "Add 2.5G\n");
7215                 if (phy_ver > 0)
7216                         tmp1 |= 1;
7217                 else
7218                         tmp1 &= 0xfffe;
7219         } else {
7220                 DP(NETIF_MSG_LINK, "Disable 2.5G\n");
7221                 tmp1 &= 0xfffe;
7222         }
7223
7224         bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_8073_2_5G, tmp1);
7225         /* Add support for CL37 (passive mode) II */
7226
7227         bnx2x_cl45_read(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_CL37_FC_LD, &tmp1);
7228         bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_CL37_FC_LD,
7229                          (tmp1 | ((phy->req_duplex == DUPLEX_FULL) ?
7230                                   0x20 : 0x40)));
7231
7232         /* Add support for CL37 (passive mode) III */
7233         bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_CL37_AN, 0x1000);
7234
7235         /* The SNR will improve about 2db by changing BW and FEE main
7236          * tap. Rest commands are executed after link is up
7237          * Change FFE main cursor to 5 in EDC register
7238          */
7239         if (bnx2x_8073_is_snr_needed(bp, phy))
7240                 bnx2x_cl45_write(bp, phy,
7241                                  MDIO_PMA_DEVAD, MDIO_PMA_REG_EDC_FFE_MAIN,
7242                                  0xFB0C);
7243
7244         /* Enable FEC (Forware Error Correction) Request in the AN */
7245         bnx2x_cl45_read(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_ADV2, &tmp1);
7246         tmp1 |= (1<<15);
7247         bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_ADV2, tmp1);
7248
7249         bnx2x_ext_phy_set_pause(params, phy, vars);
7250
7251         /* Restart autoneg */
7252         msleep(500);
7253         bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_CTRL, 0x1200);
7254         DP(NETIF_MSG_LINK, "807x Autoneg Restart: Advertise 1G=%x, 10G=%x\n",
7255                    ((val & (1<<5)) > 0), ((val & (1<<7)) > 0));
7256         return 0;
7257 }
7258
7259 static u8 bnx2x_8073_read_status(struct bnx2x_phy *phy,
7260                                  struct link_params *params,
7261                                  struct link_vars *vars)
7262 {
7263         struct bnx2x *bp = params->bp;
7264         u8 link_up = 0;
7265         u16 val1, val2;
7266         u16 link_status = 0;
7267         u16 an1000_status = 0;
7268
7269         bnx2x_cl45_read(bp, phy,
7270                         MDIO_PMA_DEVAD, MDIO_PMA_LASI_STAT, &val1);
7271
7272         DP(NETIF_MSG_LINK, "8703 LASI status 0x%x\n", val1);
7273
7274         /* clear the interrupt LASI status register */
7275         bnx2x_cl45_read(bp, phy,
7276                         MDIO_PCS_DEVAD, MDIO_PCS_REG_STATUS, &val2);
7277         bnx2x_cl45_read(bp, phy,
7278                         MDIO_PCS_DEVAD, MDIO_PCS_REG_STATUS, &val1);
7279         DP(NETIF_MSG_LINK, "807x PCS status 0x%x->0x%x\n", val2, val1);
7280         /* Clear MSG-OUT */
7281         bnx2x_cl45_read(bp, phy,
7282                         MDIO_PMA_DEVAD, MDIO_PMA_REG_M8051_MSGOUT_REG, &val1);
7283
7284         /* Check the LASI */
7285         bnx2x_cl45_read(bp, phy,
7286                         MDIO_PMA_DEVAD, MDIO_PMA_LASI_RXSTAT, &val2);
7287
7288         DP(NETIF_MSG_LINK, "KR 0x9003 0x%x\n", val2);
7289
7290         /* Check the link status */
7291         bnx2x_cl45_read(bp, phy,
7292                         MDIO_PCS_DEVAD, MDIO_PCS_REG_STATUS, &val2);
7293         DP(NETIF_MSG_LINK, "KR PCS status 0x%x\n", val2);
7294
7295         bnx2x_cl45_read(bp, phy,
7296                         MDIO_PMA_DEVAD, MDIO_PMA_REG_STATUS, &val2);
7297         bnx2x_cl45_read(bp, phy,
7298                         MDIO_PMA_DEVAD, MDIO_PMA_REG_STATUS, &val1);
7299         link_up = ((val1 & 4) == 4);
7300         DP(NETIF_MSG_LINK, "PMA_REG_STATUS=0x%x\n", val1);
7301
7302         if (link_up &&
7303              ((phy->req_line_speed != SPEED_10000))) {
7304                 if (bnx2x_8073_xaui_wa(bp, phy) != 0)
7305                         return 0;
7306         }
7307         bnx2x_cl45_read(bp, phy,
7308                         MDIO_AN_DEVAD, MDIO_AN_REG_LINK_STATUS, &an1000_status);
7309         bnx2x_cl45_read(bp, phy,
7310                         MDIO_AN_DEVAD, MDIO_AN_REG_LINK_STATUS, &an1000_status);
7311
7312         /* Check the link status on 1.1.2 */
7313         bnx2x_cl45_read(bp, phy,
7314                         MDIO_PMA_DEVAD, MDIO_PMA_REG_STATUS, &val2);
7315         bnx2x_cl45_read(bp, phy,
7316                         MDIO_PMA_DEVAD, MDIO_PMA_REG_STATUS, &val1);
7317         DP(NETIF_MSG_LINK, "KR PMA status 0x%x->0x%x,"
7318                    "an_link_status=0x%x\n", val2, val1, an1000_status);
7319
7320         link_up = (((val1 & 4) == 4) || (an1000_status & (1<<1)));
7321         if (link_up && bnx2x_8073_is_snr_needed(bp, phy)) {
7322                 /* The SNR will improve about 2dbby changing the BW and FEE main
7323                  * tap. The 1st write to change FFE main tap is set before
7324                  * restart AN. Change PLL Bandwidth in EDC register
7325                  */
7326                 bnx2x_cl45_write(bp, phy,
7327                                  MDIO_PMA_DEVAD, MDIO_PMA_REG_PLL_BANDWIDTH,
7328                                  0x26BC);
7329
7330                 /* Change CDR Bandwidth in EDC register */
7331                 bnx2x_cl45_write(bp, phy,
7332                                  MDIO_PMA_DEVAD, MDIO_PMA_REG_CDR_BANDWIDTH,
7333                                  0x0333);
7334         }
7335         bnx2x_cl45_read(bp, phy,
7336                         MDIO_PMA_DEVAD, MDIO_PMA_REG_8073_SPEED_LINK_STATUS,
7337                         &link_status);
7338
7339         /* Bits 0..2 --> speed detected, bits 13..15--> link is down */
7340         if ((link_status & (1<<2)) && (!(link_status & (1<<15)))) {
7341                 link_up = 1;
7342                 vars->line_speed = SPEED_10000;
7343                 DP(NETIF_MSG_LINK, "port %x: External link up in 10G\n",
7344                            params->port);
7345         } else if ((link_status & (1<<1)) && (!(link_status & (1<<14)))) {
7346                 link_up = 1;
7347                 vars->line_speed = SPEED_2500;
7348                 DP(NETIF_MSG_LINK, "port %x: External link up in 2.5G\n",
7349                            params->port);
7350         } else if ((link_status & (1<<0)) && (!(link_status & (1<<13)))) {
7351                 link_up = 1;
7352                 vars->line_speed = SPEED_1000;
7353                 DP(NETIF_MSG_LINK, "port %x: External link up in 1G\n",
7354                            params->port);
7355         } else {
7356                 link_up = 0;
7357                 DP(NETIF_MSG_LINK, "port %x: External link is down\n",
7358                            params->port);
7359         }
7360
7361         if (link_up) {
7362                 /* Swap polarity if required */
7363                 if (params->lane_config &
7364                     PORT_HW_CFG_SWAP_PHY_POLARITY_ENABLED) {
7365                         /* Configure the 8073 to swap P and N of the KR lines */
7366                         bnx2x_cl45_read(bp, phy,
7367                                         MDIO_XS_DEVAD,
7368                                         MDIO_XS_REG_8073_RX_CTRL_PCIE, &val1);
7369                         /* Set bit 3 to invert Rx in 1G mode and clear this bit
7370                          * when it`s in 10G mode.
7371                          */
7372                         if (vars->line_speed == SPEED_1000) {
7373                                 DP(NETIF_MSG_LINK, "Swapping 1G polarity for"
7374                                               "the 8073\n");
7375                                 val1 |= (1<<3);
7376                         } else
7377                                 val1 &= ~(1<<3);
7378
7379                         bnx2x_cl45_write(bp, phy,
7380                                          MDIO_XS_DEVAD,
7381                                          MDIO_XS_REG_8073_RX_CTRL_PCIE,
7382                                          val1);
7383                 }
7384                 bnx2x_ext_phy_10G_an_resolve(bp, phy, vars);
7385                 bnx2x_8073_resolve_fc(phy, params, vars);
7386                 vars->duplex = DUPLEX_FULL;
7387         }
7388
7389         if (vars->link_status & LINK_STATUS_AUTO_NEGOTIATE_COMPLETE) {
7390                 bnx2x_cl45_read(bp, phy, MDIO_AN_DEVAD,
7391                                 MDIO_AN_REG_LP_AUTO_NEG2, &val1);
7392
7393                 if (val1 & (1<<5))
7394                         vars->link_status |=
7395                                 LINK_STATUS_LINK_PARTNER_1000TFD_CAPABLE;
7396                 if (val1 & (1<<7))
7397                         vars->link_status |=
7398                                 LINK_STATUS_LINK_PARTNER_10GXFD_CAPABLE;
7399         }
7400
7401         return link_up;
7402 }
7403
7404 static void bnx2x_8073_link_reset(struct bnx2x_phy *phy,
7405                                   struct link_params *params)
7406 {
7407         struct bnx2x *bp = params->bp;
7408         u8 gpio_port;
7409         if (CHIP_IS_E2(bp))
7410                 gpio_port = BP_PATH(bp);
7411         else
7412                 gpio_port = params->port;
7413         DP(NETIF_MSG_LINK, "Setting 8073 port %d into low power mode\n",
7414            gpio_port);
7415         bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_2,
7416                        MISC_REGISTERS_GPIO_OUTPUT_LOW,
7417                        gpio_port);
7418 }
7419
7420 /******************************************************************/
7421 /*                      BCM8705 PHY SECTION                       */
7422 /******************************************************************/
7423 static int bnx2x_8705_config_init(struct bnx2x_phy *phy,
7424                                   struct link_params *params,
7425                                   struct link_vars *vars)
7426 {
7427         struct bnx2x *bp = params->bp;
7428         DP(NETIF_MSG_LINK, "init 8705\n");
7429         /* Restore normal power mode*/
7430         bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_2,
7431                        MISC_REGISTERS_GPIO_OUTPUT_HIGH, params->port);
7432         /* HW reset */
7433         bnx2x_ext_phy_hw_reset(bp, params->port);
7434         bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 0xa040);
7435         bnx2x_wait_reset_complete(bp, phy, params);
7436
7437         bnx2x_cl45_write(bp, phy,
7438                          MDIO_PMA_DEVAD, MDIO_PMA_REG_MISC_CTRL, 0x8288);
7439         bnx2x_cl45_write(bp, phy,
7440                          MDIO_PMA_DEVAD, MDIO_PMA_REG_PHY_IDENTIFIER, 0x7fbf);
7441         bnx2x_cl45_write(bp, phy,
7442                          MDIO_PMA_DEVAD, MDIO_PMA_REG_CMU_PLL_BYPASS, 0x0100);
7443         bnx2x_cl45_write(bp, phy,
7444                          MDIO_WIS_DEVAD, MDIO_WIS_REG_LASI_CNTL, 0x1);
7445         /* BCM8705 doesn't have microcode, hence the 0 */
7446         bnx2x_save_spirom_version(bp, params->port, params->shmem_base, 0);
7447         return 0;
7448 }
7449
7450 static u8 bnx2x_8705_read_status(struct bnx2x_phy *phy,
7451                                  struct link_params *params,
7452                                  struct link_vars *vars)
7453 {
7454         u8 link_up = 0;
7455         u16 val1, rx_sd;
7456         struct bnx2x *bp = params->bp;
7457         DP(NETIF_MSG_LINK, "read status 8705\n");
7458         bnx2x_cl45_read(bp, phy,
7459                       MDIO_WIS_DEVAD, MDIO_WIS_REG_LASI_STATUS, &val1);
7460         DP(NETIF_MSG_LINK, "8705 LASI status 0x%x\n", val1);
7461
7462         bnx2x_cl45_read(bp, phy,
7463                       MDIO_WIS_DEVAD, MDIO_WIS_REG_LASI_STATUS, &val1);
7464         DP(NETIF_MSG_LINK, "8705 LASI status 0x%x\n", val1);
7465
7466         bnx2x_cl45_read(bp, phy,
7467                       MDIO_PMA_DEVAD, MDIO_PMA_REG_RX_SD, &rx_sd);
7468
7469         bnx2x_cl45_read(bp, phy,
7470                       MDIO_PMA_DEVAD, 0xc809, &val1);
7471         bnx2x_cl45_read(bp, phy,
7472                       MDIO_PMA_DEVAD, 0xc809, &val1);
7473
7474         DP(NETIF_MSG_LINK, "8705 1.c809 val=0x%x\n", val1);
7475         link_up = ((rx_sd & 0x1) && (val1 & (1<<9)) && ((val1 & (1<<8)) == 0));
7476         if (link_up) {
7477                 vars->line_speed = SPEED_10000;
7478                 bnx2x_ext_phy_resolve_fc(phy, params, vars);
7479         }
7480         return link_up;
7481 }
7482
7483 /******************************************************************/
7484 /*                      SFP+ module Section                       */
7485 /******************************************************************/
7486 static void bnx2x_set_disable_pmd_transmit(struct link_params *params,
7487                                            struct bnx2x_phy *phy,
7488                                            u8 pmd_dis)
7489 {
7490         struct bnx2x *bp = params->bp;
7491         /* Disable transmitter only for bootcodes which can enable it afterwards
7492          * (for D3 link)
7493          */
7494         if (pmd_dis) {
7495                 if (params->feature_config_flags &
7496                      FEATURE_CONFIG_BC_SUPPORTS_SFP_TX_DISABLED)
7497                         DP(NETIF_MSG_LINK, "Disabling PMD transmitter\n");
7498                 else {
7499                         DP(NETIF_MSG_LINK, "NOT disabling PMD transmitter\n");
7500                         return;
7501                 }
7502         } else
7503                 DP(NETIF_MSG_LINK, "Enabling PMD transmitter\n");
7504         bnx2x_cl45_write(bp, phy,
7505                          MDIO_PMA_DEVAD,
7506                          MDIO_PMA_REG_TX_DISABLE, pmd_dis);
7507 }
7508
7509 static u8 bnx2x_get_gpio_port(struct link_params *params)
7510 {
7511         u8 gpio_port;
7512         u32 swap_val, swap_override;
7513         struct bnx2x *bp = params->bp;
7514         if (CHIP_IS_E2(bp))
7515                 gpio_port = BP_PATH(bp);
7516         else
7517                 gpio_port = params->port;
7518         swap_val = REG_RD(bp, NIG_REG_PORT_SWAP);
7519         swap_override = REG_RD(bp, NIG_REG_STRAP_OVERRIDE);
7520         return gpio_port ^ (swap_val && swap_override);
7521 }
7522
7523 static void bnx2x_sfp_e1e2_set_transmitter(struct link_params *params,
7524                                            struct bnx2x_phy *phy,
7525                                            u8 tx_en)
7526 {
7527         u16 val;
7528         u8 port = params->port;
7529         struct bnx2x *bp = params->bp;
7530         u32 tx_en_mode;
7531
7532         /* Disable/Enable transmitter ( TX laser of the SFP+ module.)*/
7533         tx_en_mode = REG_RD(bp, params->shmem_base +
7534                             offsetof(struct shmem_region,
7535                                      dev_info.port_hw_config[port].sfp_ctrl)) &
7536                 PORT_HW_CFG_TX_LASER_MASK;
7537         DP(NETIF_MSG_LINK, "Setting transmitter tx_en=%x for port %x "
7538                            "mode = %x\n", tx_en, port, tx_en_mode);
7539         switch (tx_en_mode) {
7540         case PORT_HW_CFG_TX_LASER_MDIO:
7541
7542                 bnx2x_cl45_read(bp, phy,
7543                                 MDIO_PMA_DEVAD,
7544                                 MDIO_PMA_REG_PHY_IDENTIFIER,
7545                                 &val);
7546
7547                 if (tx_en)
7548                         val &= ~(1<<15);
7549                 else
7550                         val |= (1<<15);
7551
7552                 bnx2x_cl45_write(bp, phy,
7553                                  MDIO_PMA_DEVAD,
7554                                  MDIO_PMA_REG_PHY_IDENTIFIER,
7555                                  val);
7556         break;
7557         case PORT_HW_CFG_TX_LASER_GPIO0:
7558         case PORT_HW_CFG_TX_LASER_GPIO1:
7559         case PORT_HW_CFG_TX_LASER_GPIO2:
7560         case PORT_HW_CFG_TX_LASER_GPIO3:
7561         {
7562                 u16 gpio_pin;
7563                 u8 gpio_port, gpio_mode;
7564                 if (tx_en)
7565                         gpio_mode = MISC_REGISTERS_GPIO_OUTPUT_HIGH;
7566                 else
7567                         gpio_mode = MISC_REGISTERS_GPIO_OUTPUT_LOW;
7568
7569                 gpio_pin = tx_en_mode - PORT_HW_CFG_TX_LASER_GPIO0;
7570                 gpio_port = bnx2x_get_gpio_port(params);
7571                 bnx2x_set_gpio(bp, gpio_pin, gpio_mode, gpio_port);
7572                 break;
7573         }
7574         default:
7575                 DP(NETIF_MSG_LINK, "Invalid TX_LASER_MDIO 0x%x\n", tx_en_mode);
7576                 break;
7577         }
7578 }
7579
7580 static void bnx2x_sfp_set_transmitter(struct link_params *params,
7581                                       struct bnx2x_phy *phy,
7582                                       u8 tx_en)
7583 {
7584         struct bnx2x *bp = params->bp;
7585         DP(NETIF_MSG_LINK, "Setting SFP+ transmitter to %d\n", tx_en);
7586         if (CHIP_IS_E3(bp))
7587                 bnx2x_sfp_e3_set_transmitter(params, phy, tx_en);
7588         else
7589                 bnx2x_sfp_e1e2_set_transmitter(params, phy, tx_en);
7590 }
7591
7592 static int bnx2x_8726_read_sfp_module_eeprom(struct bnx2x_phy *phy,
7593                                              struct link_params *params,
7594                                              u16 addr, u8 byte_cnt, u8 *o_buf)
7595 {
7596         struct bnx2x *bp = params->bp;
7597         u16 val = 0;
7598         u16 i;
7599         if (byte_cnt > 16) {
7600                 DP(NETIF_MSG_LINK,
7601                    "Reading from eeprom is limited to 0xf\n");
7602                 return -EINVAL;
7603         }
7604         /* Set the read command byte count */
7605         bnx2x_cl45_write(bp, phy,
7606                          MDIO_PMA_DEVAD, MDIO_PMA_REG_SFP_TWO_WIRE_BYTE_CNT,
7607                          (byte_cnt | 0xa000));
7608
7609         /* Set the read command address */
7610         bnx2x_cl45_write(bp, phy,
7611                          MDIO_PMA_DEVAD, MDIO_PMA_REG_SFP_TWO_WIRE_MEM_ADDR,
7612                          addr);
7613
7614         /* Activate read command */
7615         bnx2x_cl45_write(bp, phy,
7616                          MDIO_PMA_DEVAD, MDIO_PMA_REG_SFP_TWO_WIRE_CTRL,
7617                          0x2c0f);
7618
7619         /* Wait up to 500us for command complete status */
7620         for (i = 0; i < 100; i++) {
7621                 bnx2x_cl45_read(bp, phy,
7622                                 MDIO_PMA_DEVAD,
7623                                 MDIO_PMA_REG_SFP_TWO_WIRE_CTRL, &val);
7624                 if ((val & MDIO_PMA_REG_SFP_TWO_WIRE_CTRL_STATUS_MASK) ==
7625                     MDIO_PMA_REG_SFP_TWO_WIRE_STATUS_COMPLETE)
7626                         break;
7627                 udelay(5);
7628         }
7629
7630         if ((val & MDIO_PMA_REG_SFP_TWO_WIRE_CTRL_STATUS_MASK) !=
7631                     MDIO_PMA_REG_SFP_TWO_WIRE_STATUS_COMPLETE) {
7632                 DP(NETIF_MSG_LINK,
7633                          "Got bad status 0x%x when reading from SFP+ EEPROM\n",
7634                          (val & MDIO_PMA_REG_SFP_TWO_WIRE_CTRL_STATUS_MASK));
7635                 return -EINVAL;
7636         }
7637
7638         /* Read the buffer */
7639         for (i = 0; i < byte_cnt; i++) {
7640                 bnx2x_cl45_read(bp, phy,
7641                                 MDIO_PMA_DEVAD,
7642                                 MDIO_PMA_REG_8726_TWO_WIRE_DATA_BUF + i, &val);
7643                 o_buf[i] = (u8)(val & MDIO_PMA_REG_8726_TWO_WIRE_DATA_MASK);
7644         }
7645
7646         for (i = 0; i < 100; i++) {
7647                 bnx2x_cl45_read(bp, phy,
7648                                 MDIO_PMA_DEVAD,
7649                                 MDIO_PMA_REG_SFP_TWO_WIRE_CTRL, &val);
7650                 if ((val & MDIO_PMA_REG_SFP_TWO_WIRE_CTRL_STATUS_MASK) ==
7651                     MDIO_PMA_REG_SFP_TWO_WIRE_STATUS_IDLE)
7652                         return 0;
7653                 msleep(1);
7654         }
7655         return -EINVAL;
7656 }
7657
7658 static int bnx2x_warpcore_read_sfp_module_eeprom(struct bnx2x_phy *phy,
7659                                                  struct link_params *params,
7660                                                  u16 addr, u8 byte_cnt,
7661                                                  u8 *o_buf)
7662 {
7663         int rc = 0;
7664         u8 i, j = 0, cnt = 0;
7665         u32 data_array[4];
7666         u16 addr32;
7667         struct bnx2x *bp = params->bp;
7668         if (byte_cnt > 16) {
7669                 DP(NETIF_MSG_LINK,
7670                    "Reading from eeprom is limited to 16 bytes\n");
7671                 return -EINVAL;
7672         }
7673
7674         /* 4 byte aligned address */
7675         addr32 = addr & (~0x3);
7676         do {
7677                 rc = bnx2x_bsc_read(params, phy, 0xa0, addr32, 0, byte_cnt,
7678                                     data_array);
7679         } while ((rc != 0) && (++cnt < I2C_WA_RETRY_CNT));
7680
7681         if (rc == 0) {
7682                 for (i = (addr - addr32); i < byte_cnt + (addr - addr32); i++) {
7683                         o_buf[j] = *((u8 *)data_array + i);
7684                         j++;
7685                 }
7686         }
7687
7688         return rc;
7689 }
7690
7691 static int bnx2x_8727_read_sfp_module_eeprom(struct bnx2x_phy *phy,
7692                                              struct link_params *params,
7693                                              u16 addr, u8 byte_cnt, u8 *o_buf)
7694 {
7695         struct bnx2x *bp = params->bp;
7696         u16 val, i;
7697
7698         if (byte_cnt > 16) {
7699                 DP(NETIF_MSG_LINK,
7700                    "Reading from eeprom is limited to 0xf\n");
7701                 return -EINVAL;
7702         }
7703
7704         /* Need to read from 1.8000 to clear it */
7705         bnx2x_cl45_read(bp, phy,
7706                         MDIO_PMA_DEVAD,
7707                         MDIO_PMA_REG_SFP_TWO_WIRE_CTRL,
7708                         &val);
7709
7710         /* Set the read command byte count */
7711         bnx2x_cl45_write(bp, phy,
7712                          MDIO_PMA_DEVAD,
7713                          MDIO_PMA_REG_SFP_TWO_WIRE_BYTE_CNT,
7714                          ((byte_cnt < 2) ? 2 : byte_cnt));
7715
7716         /* Set the read command address */
7717         bnx2x_cl45_write(bp, phy,
7718                          MDIO_PMA_DEVAD,
7719                          MDIO_PMA_REG_SFP_TWO_WIRE_MEM_ADDR,
7720                          addr);
7721         /* Set the destination address */
7722         bnx2x_cl45_write(bp, phy,
7723                          MDIO_PMA_DEVAD,
7724                          0x8004,
7725                          MDIO_PMA_REG_8727_TWO_WIRE_DATA_BUF);
7726
7727         /* Activate read command */
7728         bnx2x_cl45_write(bp, phy,
7729                          MDIO_PMA_DEVAD,
7730                          MDIO_PMA_REG_SFP_TWO_WIRE_CTRL,
7731                          0x8002);
7732         /* Wait appropriate time for two-wire command to finish before
7733          * polling the status register
7734          */
7735         msleep(1);
7736
7737         /* Wait up to 500us for command complete status */
7738         for (i = 0; i < 100; i++) {
7739                 bnx2x_cl45_read(bp, phy,
7740                                 MDIO_PMA_DEVAD,
7741                                 MDIO_PMA_REG_SFP_TWO_WIRE_CTRL, &val);
7742                 if ((val & MDIO_PMA_REG_SFP_TWO_WIRE_CTRL_STATUS_MASK) ==
7743                     MDIO_PMA_REG_SFP_TWO_WIRE_STATUS_COMPLETE)
7744                         break;
7745                 udelay(5);
7746         }
7747
7748         if ((val & MDIO_PMA_REG_SFP_TWO_WIRE_CTRL_STATUS_MASK) !=
7749                     MDIO_PMA_REG_SFP_TWO_WIRE_STATUS_COMPLETE) {
7750                 DP(NETIF_MSG_LINK,
7751                          "Got bad status 0x%x when reading from SFP+ EEPROM\n",
7752                          (val & MDIO_PMA_REG_SFP_TWO_WIRE_CTRL_STATUS_MASK));
7753                 return -EFAULT;
7754         }
7755
7756         /* Read the buffer */
7757         for (i = 0; i < byte_cnt; i++) {
7758                 bnx2x_cl45_read(bp, phy,
7759                                 MDIO_PMA_DEVAD,
7760                                 MDIO_PMA_REG_8727_TWO_WIRE_DATA_BUF + i, &val);
7761                 o_buf[i] = (u8)(val & MDIO_PMA_REG_8727_TWO_WIRE_DATA_MASK);
7762         }
7763
7764         for (i = 0; i < 100; i++) {
7765                 bnx2x_cl45_read(bp, phy,
7766                                 MDIO_PMA_DEVAD,
7767                                 MDIO_PMA_REG_SFP_TWO_WIRE_CTRL, &val);
7768                 if ((val & MDIO_PMA_REG_SFP_TWO_WIRE_CTRL_STATUS_MASK) ==
7769                     MDIO_PMA_REG_SFP_TWO_WIRE_STATUS_IDLE)
7770                         return 0;
7771                 msleep(1);
7772         }
7773
7774         return -EINVAL;
7775 }
7776
7777 int bnx2x_read_sfp_module_eeprom(struct bnx2x_phy *phy,
7778                                  struct link_params *params, u16 addr,
7779                                  u8 byte_cnt, u8 *o_buf)
7780 {
7781         int rc = -EINVAL;
7782         switch (phy->type) {
7783         case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8726:
7784                 rc = bnx2x_8726_read_sfp_module_eeprom(phy, params, addr,
7785                                                        byte_cnt, o_buf);
7786         break;
7787         case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727:
7788         case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8722:
7789                 rc = bnx2x_8727_read_sfp_module_eeprom(phy, params, addr,
7790                                                        byte_cnt, o_buf);
7791         break;
7792         case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT:
7793                 rc = bnx2x_warpcore_read_sfp_module_eeprom(phy, params, addr,
7794                                                            byte_cnt, o_buf);
7795         break;
7796         }
7797         return rc;
7798 }
7799
7800 static int bnx2x_get_edc_mode(struct bnx2x_phy *phy,
7801                               struct link_params *params,
7802                               u16 *edc_mode)
7803 {
7804         struct bnx2x *bp = params->bp;
7805         u32 sync_offset = 0, phy_idx, media_types;
7806         u8 val, check_limiting_mode = 0;
7807         *edc_mode = EDC_MODE_LIMITING;
7808
7809         phy->media_type = ETH_PHY_UNSPECIFIED;
7810         /* First check for copper cable */
7811         if (bnx2x_read_sfp_module_eeprom(phy,
7812                                          params,
7813                                          SFP_EEPROM_CON_TYPE_ADDR,
7814                                          1,
7815                                          &val) != 0) {
7816                 DP(NETIF_MSG_LINK, "Failed to read from SFP+ module EEPROM\n");
7817                 return -EINVAL;
7818         }
7819
7820         switch (val) {
7821         case SFP_EEPROM_CON_TYPE_VAL_COPPER:
7822         {
7823                 u8 copper_module_type;
7824                 phy->media_type = ETH_PHY_DA_TWINAX;
7825                 /* Check if its active cable (includes SFP+ module)
7826                  * of passive cable
7827                  */
7828                 if (bnx2x_read_sfp_module_eeprom(phy,
7829                                                params,
7830                                                SFP_EEPROM_FC_TX_TECH_ADDR,
7831                                                1,
7832                                                &copper_module_type) != 0) {
7833                         DP(NETIF_MSG_LINK,
7834                                 "Failed to read copper-cable-type"
7835                                 " from SFP+ EEPROM\n");
7836                         return -EINVAL;
7837                 }
7838
7839                 if (copper_module_type &
7840                     SFP_EEPROM_FC_TX_TECH_BITMASK_COPPER_ACTIVE) {
7841                         DP(NETIF_MSG_LINK, "Active Copper cable detected\n");
7842                         check_limiting_mode = 1;
7843                 } else if (copper_module_type &
7844                         SFP_EEPROM_FC_TX_TECH_BITMASK_COPPER_PASSIVE) {
7845                                 DP(NETIF_MSG_LINK,
7846                                    "Passive Copper cable detected\n");
7847                                 *edc_mode =
7848                                       EDC_MODE_PASSIVE_DAC;
7849                 } else {
7850                         DP(NETIF_MSG_LINK,
7851                            "Unknown copper-cable-type 0x%x !!!\n",
7852                            copper_module_type);
7853                         return -EINVAL;
7854                 }
7855                 break;
7856         }
7857         case SFP_EEPROM_CON_TYPE_VAL_LC:
7858                 phy->media_type = ETH_PHY_SFP_FIBER;
7859                 DP(NETIF_MSG_LINK, "Optic module detected\n");
7860                 check_limiting_mode = 1;
7861                 break;
7862         default:
7863                 DP(NETIF_MSG_LINK, "Unable to determine module type 0x%x !!!\n",
7864                          val);
7865                 return -EINVAL;
7866         }
7867         sync_offset = params->shmem_base +
7868                 offsetof(struct shmem_region,
7869                          dev_info.port_hw_config[params->port].media_type);
7870         media_types = REG_RD(bp, sync_offset);
7871         /* Update media type for non-PMF sync */
7872         for (phy_idx = INT_PHY; phy_idx < MAX_PHYS; phy_idx++) {
7873                 if (&(params->phy[phy_idx]) == phy) {
7874                         media_types &= ~(PORT_HW_CFG_MEDIA_TYPE_PHY0_MASK <<
7875                                 (PORT_HW_CFG_MEDIA_TYPE_PHY1_SHIFT * phy_idx));
7876                         media_types |= ((phy->media_type &
7877                                         PORT_HW_CFG_MEDIA_TYPE_PHY0_MASK) <<
7878                                 (PORT_HW_CFG_MEDIA_TYPE_PHY1_SHIFT * phy_idx));
7879                         break;
7880                 }
7881         }
7882         REG_WR(bp, sync_offset, media_types);
7883         if (check_limiting_mode) {
7884                 u8 options[SFP_EEPROM_OPTIONS_SIZE];
7885                 if (bnx2x_read_sfp_module_eeprom(phy,
7886                                                  params,
7887                                                  SFP_EEPROM_OPTIONS_ADDR,
7888                                                  SFP_EEPROM_OPTIONS_SIZE,
7889                                                  options) != 0) {
7890                         DP(NETIF_MSG_LINK,
7891                            "Failed to read Option field from module EEPROM\n");
7892                         return -EINVAL;
7893                 }
7894                 if ((options[0] & SFP_EEPROM_OPTIONS_LINEAR_RX_OUT_MASK))
7895                         *edc_mode = EDC_MODE_LINEAR;
7896                 else
7897                         *edc_mode = EDC_MODE_LIMITING;
7898         }
7899         DP(NETIF_MSG_LINK, "EDC mode is set to 0x%x\n", *edc_mode);
7900         return 0;
7901 }
7902 /* This function read the relevant field from the module (SFP+), and verify it
7903  * is compliant with this board
7904  */
7905 static int bnx2x_verify_sfp_module(struct bnx2x_phy *phy,
7906                                    struct link_params *params)
7907 {
7908         struct bnx2x *bp = params->bp;
7909         u32 val, cmd;
7910         u32 fw_resp, fw_cmd_param;
7911         char vendor_name[SFP_EEPROM_VENDOR_NAME_SIZE+1];
7912         char vendor_pn[SFP_EEPROM_PART_NO_SIZE+1];
7913         phy->flags &= ~FLAGS_SFP_NOT_APPROVED;
7914         val = REG_RD(bp, params->shmem_base +
7915                          offsetof(struct shmem_region, dev_info.
7916                                   port_feature_config[params->port].config));
7917         if ((val & PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_MASK) ==
7918             PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_NO_ENFORCEMENT) {
7919                 DP(NETIF_MSG_LINK, "NOT enforcing module verification\n");
7920                 return 0;
7921         }
7922
7923         if (params->feature_config_flags &
7924             FEATURE_CONFIG_BC_SUPPORTS_DUAL_PHY_OPT_MDL_VRFY) {
7925                 /* Use specific phy request */
7926                 cmd = DRV_MSG_CODE_VRFY_SPECIFIC_PHY_OPT_MDL;
7927         } else if (params->feature_config_flags &
7928                    FEATURE_CONFIG_BC_SUPPORTS_OPT_MDL_VRFY) {
7929                 /* Use first phy request only in case of non-dual media*/
7930                 if (DUAL_MEDIA(params)) {
7931                         DP(NETIF_MSG_LINK,
7932                            "FW does not support OPT MDL verification\n");
7933                         return -EINVAL;
7934                 }
7935                 cmd = DRV_MSG_CODE_VRFY_FIRST_PHY_OPT_MDL;
7936         } else {
7937                 /* No support in OPT MDL detection */
7938                 DP(NETIF_MSG_LINK,
7939                    "FW does not support OPT MDL verification\n");
7940                 return -EINVAL;
7941         }
7942
7943         fw_cmd_param = FW_PARAM_SET(phy->addr, phy->type, phy->mdio_ctrl);
7944         fw_resp = bnx2x_fw_command(bp, cmd, fw_cmd_param);
7945         if (fw_resp == FW_MSG_CODE_VRFY_OPT_MDL_SUCCESS) {
7946                 DP(NETIF_MSG_LINK, "Approved module\n");
7947                 return 0;
7948         }
7949
7950         /* format the warning message */
7951         if (bnx2x_read_sfp_module_eeprom(phy,
7952                                          params,
7953                                          SFP_EEPROM_VENDOR_NAME_ADDR,
7954                                          SFP_EEPROM_VENDOR_NAME_SIZE,
7955                                          (u8 *)vendor_name))
7956                 vendor_name[0] = '\0';
7957         else
7958                 vendor_name[SFP_EEPROM_VENDOR_NAME_SIZE] = '\0';
7959         if (bnx2x_read_sfp_module_eeprom(phy,
7960                                          params,
7961                                          SFP_EEPROM_PART_NO_ADDR,
7962                                          SFP_EEPROM_PART_NO_SIZE,
7963                                          (u8 *)vendor_pn))
7964                 vendor_pn[0] = '\0';
7965         else
7966                 vendor_pn[SFP_EEPROM_PART_NO_SIZE] = '\0';
7967
7968         netdev_err(bp->dev,  "Warning: Unqualified SFP+ module detected,"
7969                               " Port %d from %s part number %s\n",
7970                          params->port, vendor_name, vendor_pn);
7971         if ((val & PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_MASK) !=
7972             PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_WARNING_MSG)
7973                 phy->flags |= FLAGS_SFP_NOT_APPROVED;
7974         return -EINVAL;
7975 }
7976
7977 static int bnx2x_wait_for_sfp_module_initialized(struct bnx2x_phy *phy,
7978                                                  struct link_params *params)
7979
7980 {
7981         u8 val;
7982         struct bnx2x *bp = params->bp;
7983         u16 timeout;
7984         /* Initialization time after hot-plug may take up to 300ms for
7985          * some phys type ( e.g. JDSU )
7986          */
7987
7988         for (timeout = 0; timeout < 60; timeout++) {
7989                 if (bnx2x_read_sfp_module_eeprom(phy, params, 1, 1, &val)
7990                     == 0) {
7991                         DP(NETIF_MSG_LINK,
7992                            "SFP+ module initialization took %d ms\n",
7993                            timeout * 5);
7994                         return 0;
7995                 }
7996                 msleep(5);
7997         }
7998         return -EINVAL;
7999 }
8000
8001 static void bnx2x_8727_power_module(struct bnx2x *bp,
8002                                     struct bnx2x_phy *phy,
8003                                     u8 is_power_up) {
8004         /* Make sure GPIOs are not using for LED mode */
8005         u16 val;
8006         /* In the GPIO register, bit 4 is use to determine if the GPIOs are
8007          * operating as INPUT or as OUTPUT. Bit 1 is for input, and 0 for
8008          * output
8009          * Bits 0-1 determine the GPIOs value for OUTPUT in case bit 4 val is 0
8010          * Bits 8-9 determine the GPIOs value for INPUT in case bit 4 val is 1
8011          * where the 1st bit is the over-current(only input), and 2nd bit is
8012          * for power( only output )
8013          *
8014          * In case of NOC feature is disabled and power is up, set GPIO control
8015          *  as input to enable listening of over-current indication
8016          */
8017         if (phy->flags & FLAGS_NOC)
8018                 return;
8019         if (is_power_up)
8020                 val = (1<<4);
8021         else
8022                 /* Set GPIO control to OUTPUT, and set the power bit
8023                  * to according to the is_power_up
8024                  */
8025                 val = (1<<1);
8026
8027         bnx2x_cl45_write(bp, phy,
8028                          MDIO_PMA_DEVAD,
8029                          MDIO_PMA_REG_8727_GPIO_CTRL,
8030                          val);
8031 }
8032
8033 static int bnx2x_8726_set_limiting_mode(struct bnx2x *bp,
8034                                         struct bnx2x_phy *phy,
8035                                         u16 edc_mode)
8036 {
8037         u16 cur_limiting_mode;
8038
8039         bnx2x_cl45_read(bp, phy,
8040                         MDIO_PMA_DEVAD,
8041                         MDIO_PMA_REG_ROM_VER2,
8042                         &cur_limiting_mode);
8043         DP(NETIF_MSG_LINK, "Current Limiting mode is 0x%x\n",
8044                  cur_limiting_mode);
8045
8046         if (edc_mode == EDC_MODE_LIMITING) {
8047                 DP(NETIF_MSG_LINK, "Setting LIMITING MODE\n");
8048                 bnx2x_cl45_write(bp, phy,
8049                                  MDIO_PMA_DEVAD,
8050                                  MDIO_PMA_REG_ROM_VER2,
8051                                  EDC_MODE_LIMITING);
8052         } else { /* LRM mode ( default )*/
8053
8054                 DP(NETIF_MSG_LINK, "Setting LRM MODE\n");
8055
8056                 /* Changing to LRM mode takes quite few seconds. So do it only
8057                  * if current mode is limiting (default is LRM)
8058                  */
8059                 if (cur_limiting_mode != EDC_MODE_LIMITING)
8060                         return 0;
8061
8062                 bnx2x_cl45_write(bp, phy,
8063                                  MDIO_PMA_DEVAD,
8064                                  MDIO_PMA_REG_LRM_MODE,
8065                                  0);
8066                 bnx2x_cl45_write(bp, phy,
8067                                  MDIO_PMA_DEVAD,
8068                                  MDIO_PMA_REG_ROM_VER2,
8069                                  0x128);
8070                 bnx2x_cl45_write(bp, phy,
8071                                  MDIO_PMA_DEVAD,
8072                                  MDIO_PMA_REG_MISC_CTRL0,
8073                                  0x4008);
8074                 bnx2x_cl45_write(bp, phy,
8075                                  MDIO_PMA_DEVAD,
8076                                  MDIO_PMA_REG_LRM_MODE,
8077                                  0xaaaa);
8078         }
8079         return 0;
8080 }
8081
8082 static int bnx2x_8727_set_limiting_mode(struct bnx2x *bp,
8083                                         struct bnx2x_phy *phy,
8084                                         u16 edc_mode)
8085 {
8086         u16 phy_identifier;
8087         u16 rom_ver2_val;
8088         bnx2x_cl45_read(bp, phy,
8089                         MDIO_PMA_DEVAD,
8090                         MDIO_PMA_REG_PHY_IDENTIFIER,
8091                         &phy_identifier);
8092
8093         bnx2x_cl45_write(bp, phy,
8094                          MDIO_PMA_DEVAD,
8095                          MDIO_PMA_REG_PHY_IDENTIFIER,
8096                          (phy_identifier & ~(1<<9)));
8097
8098         bnx2x_cl45_read(bp, phy,
8099                         MDIO_PMA_DEVAD,
8100                         MDIO_PMA_REG_ROM_VER2,
8101                         &rom_ver2_val);
8102         /* Keep the MSB 8-bits, and set the LSB 8-bits with the edc_mode */
8103         bnx2x_cl45_write(bp, phy,
8104                          MDIO_PMA_DEVAD,
8105                          MDIO_PMA_REG_ROM_VER2,
8106                          (rom_ver2_val & 0xff00) | (edc_mode & 0x00ff));
8107
8108         bnx2x_cl45_write(bp, phy,
8109                          MDIO_PMA_DEVAD,
8110                          MDIO_PMA_REG_PHY_IDENTIFIER,
8111                          (phy_identifier | (1<<9)));
8112
8113         return 0;
8114 }
8115
8116 static void bnx2x_8727_specific_func(struct bnx2x_phy *phy,
8117                                      struct link_params *params,
8118                                      u32 action)
8119 {
8120         struct bnx2x *bp = params->bp;
8121
8122         switch (action) {
8123         case DISABLE_TX:
8124                 bnx2x_sfp_set_transmitter(params, phy, 0);
8125                 break;
8126         case ENABLE_TX:
8127                 if (!(phy->flags & FLAGS_SFP_NOT_APPROVED))
8128                         bnx2x_sfp_set_transmitter(params, phy, 1);
8129                 break;
8130         default:
8131                 DP(NETIF_MSG_LINK, "Function 0x%x not supported by 8727\n",
8132                    action);
8133                 return;
8134         }
8135 }
8136
8137 static void bnx2x_set_e1e2_module_fault_led(struct link_params *params,
8138                                            u8 gpio_mode)
8139 {
8140         struct bnx2x *bp = params->bp;
8141
8142         u32 fault_led_gpio = REG_RD(bp, params->shmem_base +
8143                             offsetof(struct shmem_region,
8144                         dev_info.port_hw_config[params->port].sfp_ctrl)) &
8145                 PORT_HW_CFG_FAULT_MODULE_LED_MASK;
8146         switch (fault_led_gpio) {
8147         case PORT_HW_CFG_FAULT_MODULE_LED_DISABLED:
8148                 return;
8149         case PORT_HW_CFG_FAULT_MODULE_LED_GPIO0:
8150         case PORT_HW_CFG_FAULT_MODULE_LED_GPIO1:
8151         case PORT_HW_CFG_FAULT_MODULE_LED_GPIO2:
8152         case PORT_HW_CFG_FAULT_MODULE_LED_GPIO3:
8153         {
8154                 u8 gpio_port = bnx2x_get_gpio_port(params);
8155                 u16 gpio_pin = fault_led_gpio -
8156                         PORT_HW_CFG_FAULT_MODULE_LED_GPIO0;
8157                 DP(NETIF_MSG_LINK, "Set fault module-detected led "
8158                                    "pin %x port %x mode %x\n",
8159                                gpio_pin, gpio_port, gpio_mode);
8160                 bnx2x_set_gpio(bp, gpio_pin, gpio_mode, gpio_port);
8161         }
8162         break;
8163         default:
8164                 DP(NETIF_MSG_LINK, "Error: Invalid fault led mode 0x%x\n",
8165                                fault_led_gpio);
8166         }
8167 }
8168
8169 static void bnx2x_set_e3_module_fault_led(struct link_params *params,
8170                                           u8 gpio_mode)
8171 {
8172         u32 pin_cfg;
8173         u8 port = params->port;
8174         struct bnx2x *bp = params->bp;
8175         pin_cfg = (REG_RD(bp, params->shmem_base +
8176                          offsetof(struct shmem_region,
8177                                   dev_info.port_hw_config[port].e3_sfp_ctrl)) &
8178                 PORT_HW_CFG_E3_FAULT_MDL_LED_MASK) >>
8179                 PORT_HW_CFG_E3_FAULT_MDL_LED_SHIFT;
8180         DP(NETIF_MSG_LINK, "Setting Fault LED to %d using pin cfg %d\n",
8181                        gpio_mode, pin_cfg);
8182         bnx2x_set_cfg_pin(bp, pin_cfg, gpio_mode);
8183 }
8184
8185 static void bnx2x_set_sfp_module_fault_led(struct link_params *params,
8186                                            u8 gpio_mode)
8187 {
8188         struct bnx2x *bp = params->bp;
8189         DP(NETIF_MSG_LINK, "Setting SFP+ module fault LED to %d\n", gpio_mode);
8190         if (CHIP_IS_E3(bp)) {
8191                 /* Low ==> if SFP+ module is supported otherwise
8192                  * High ==> if SFP+ module is not on the approved vendor list
8193                  */
8194                 bnx2x_set_e3_module_fault_led(params, gpio_mode);
8195         } else
8196                 bnx2x_set_e1e2_module_fault_led(params, gpio_mode);
8197 }
8198
8199 static void bnx2x_warpcore_power_module(struct link_params *params,
8200                                         struct bnx2x_phy *phy,
8201                                         u8 power)
8202 {
8203         u32 pin_cfg;
8204         struct bnx2x *bp = params->bp;
8205
8206         pin_cfg = (REG_RD(bp, params->shmem_base +
8207                           offsetof(struct shmem_region,
8208                         dev_info.port_hw_config[params->port].e3_sfp_ctrl)) &
8209                         PORT_HW_CFG_E3_PWR_DIS_MASK) >>
8210                         PORT_HW_CFG_E3_PWR_DIS_SHIFT;
8211
8212         if (pin_cfg == PIN_CFG_NA)
8213                 return;
8214         DP(NETIF_MSG_LINK, "Setting SFP+ module power to %d using pin cfg %d\n",
8215                        power, pin_cfg);
8216         /* Low ==> corresponding SFP+ module is powered
8217          * high ==> the SFP+ module is powered down
8218          */
8219         bnx2x_set_cfg_pin(bp, pin_cfg, power ^ 1);
8220 }
8221
8222 static void bnx2x_warpcore_hw_reset(struct bnx2x_phy *phy,
8223                                     struct link_params *params)
8224 {
8225         struct bnx2x *bp = params->bp;
8226         bnx2x_warpcore_power_module(params, phy, 0);
8227         /* Put Warpcore in low power mode */
8228         REG_WR(bp, MISC_REG_WC0_RESET, 0x0c0e);
8229
8230         /* Put LCPLL in low power mode */
8231         REG_WR(bp, MISC_REG_LCPLL_E40_PWRDWN, 1);
8232         REG_WR(bp, MISC_REG_LCPLL_E40_RESETB_ANA, 0);
8233         REG_WR(bp, MISC_REG_LCPLL_E40_RESETB_DIG, 0);
8234 }
8235
8236 static void bnx2x_power_sfp_module(struct link_params *params,
8237                                    struct bnx2x_phy *phy,
8238                                    u8 power)
8239 {
8240         struct bnx2x *bp = params->bp;
8241         DP(NETIF_MSG_LINK, "Setting SFP+ power to %x\n", power);
8242
8243         switch (phy->type) {
8244         case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727:
8245         case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8722:
8246                 bnx2x_8727_power_module(params->bp, phy, power);
8247                 break;
8248         case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT:
8249                 bnx2x_warpcore_power_module(params, phy, power);
8250                 break;
8251         default:
8252                 break;
8253         }
8254 }
8255 static void bnx2x_warpcore_set_limiting_mode(struct link_params *params,
8256                                              struct bnx2x_phy *phy,
8257                                              u16 edc_mode)
8258 {
8259         u16 val = 0;
8260         u16 mode = MDIO_WC_REG_UC_INFO_B1_FIRMWARE_MODE_DEFAULT;
8261         struct bnx2x *bp = params->bp;
8262
8263         u8 lane = bnx2x_get_warpcore_lane(phy, params);
8264         /* This is a global register which controls all lanes */
8265         bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
8266                         MDIO_WC_REG_UC_INFO_B1_FIRMWARE_MODE, &val);
8267         val &= ~(0xf << (lane << 2));
8268
8269         switch (edc_mode) {
8270         case EDC_MODE_LINEAR:
8271         case EDC_MODE_LIMITING:
8272                 mode = MDIO_WC_REG_UC_INFO_B1_FIRMWARE_MODE_DEFAULT;
8273                 break;
8274         case EDC_MODE_PASSIVE_DAC:
8275                 mode = MDIO_WC_REG_UC_INFO_B1_FIRMWARE_MODE_SFP_DAC;
8276                 break;
8277         default:
8278                 break;
8279         }
8280
8281         val |= (mode << (lane << 2));
8282         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
8283                          MDIO_WC_REG_UC_INFO_B1_FIRMWARE_MODE, val);
8284         /* A must read */
8285         bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
8286                         MDIO_WC_REG_UC_INFO_B1_FIRMWARE_MODE, &val);
8287
8288         /* Restart microcode to re-read the new mode */
8289         bnx2x_warpcore_reset_lane(bp, phy, 1);
8290         bnx2x_warpcore_reset_lane(bp, phy, 0);
8291
8292 }
8293
8294 static void bnx2x_set_limiting_mode(struct link_params *params,
8295                                     struct bnx2x_phy *phy,
8296                                     u16 edc_mode)
8297 {
8298         switch (phy->type) {
8299         case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8726:
8300                 bnx2x_8726_set_limiting_mode(params->bp, phy, edc_mode);
8301                 break;
8302         case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727:
8303         case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8722:
8304                 bnx2x_8727_set_limiting_mode(params->bp, phy, edc_mode);
8305                 break;
8306         case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT:
8307                 bnx2x_warpcore_set_limiting_mode(params, phy, edc_mode);
8308                 break;
8309         }
8310 }
8311
8312 int bnx2x_sfp_module_detection(struct bnx2x_phy *phy,
8313                                struct link_params *params)
8314 {
8315         struct bnx2x *bp = params->bp;
8316         u16 edc_mode;
8317         int rc = 0;
8318
8319         u32 val = REG_RD(bp, params->shmem_base +
8320                              offsetof(struct shmem_region, dev_info.
8321                                      port_feature_config[params->port].config));
8322
8323         DP(NETIF_MSG_LINK, "SFP+ module plugged in/out detected on port %d\n",
8324                  params->port);
8325         /* Power up module */
8326         bnx2x_power_sfp_module(params, phy, 1);
8327         if (bnx2x_get_edc_mode(phy, params, &edc_mode) != 0) {
8328                 DP(NETIF_MSG_LINK, "Failed to get valid module type\n");
8329                 return -EINVAL;
8330         } else if (bnx2x_verify_sfp_module(phy, params) != 0) {
8331                 /* check SFP+ module compatibility */
8332                 DP(NETIF_MSG_LINK, "Module verification failed!!\n");
8333                 rc = -EINVAL;
8334                 /* Turn on fault module-detected led */
8335                 bnx2x_set_sfp_module_fault_led(params,
8336                                                MISC_REGISTERS_GPIO_HIGH);
8337
8338                 /* Check if need to power down the SFP+ module */
8339                 if ((val & PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_MASK) ==
8340                      PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_POWER_DOWN) {
8341                         DP(NETIF_MSG_LINK, "Shutdown SFP+ module!!\n");
8342                         bnx2x_power_sfp_module(params, phy, 0);
8343                         return rc;
8344                 }
8345         } else {
8346                 /* Turn off fault module-detected led */
8347                 bnx2x_set_sfp_module_fault_led(params, MISC_REGISTERS_GPIO_LOW);
8348         }
8349
8350         /* Check and set limiting mode / LRM mode on 8726. On 8727 it
8351          * is done automatically
8352          */
8353         bnx2x_set_limiting_mode(params, phy, edc_mode);
8354
8355         /* Enable transmit for this module if the module is approved, or
8356          * if unapproved modules should also enable the Tx laser
8357          */
8358         if (rc == 0 ||
8359             (val & PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_MASK) !=
8360             PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_DISABLE_TX_LASER)
8361                 bnx2x_sfp_set_transmitter(params, phy, 1);
8362         else
8363                 bnx2x_sfp_set_transmitter(params, phy, 0);
8364
8365         return rc;
8366 }
8367
8368 void bnx2x_handle_module_detect_int(struct link_params *params)
8369 {
8370         struct bnx2x *bp = params->bp;
8371         struct bnx2x_phy *phy;
8372         u32 gpio_val;
8373         u8 gpio_num, gpio_port;
8374         if (CHIP_IS_E3(bp))
8375                 phy = &params->phy[INT_PHY];
8376         else
8377                 phy = &params->phy[EXT_PHY1];
8378
8379         if (bnx2x_get_mod_abs_int_cfg(bp, params->chip_id, params->shmem_base,
8380                                       params->port, &gpio_num, &gpio_port) ==
8381             -EINVAL) {
8382                 DP(NETIF_MSG_LINK, "Failed to get MOD_ABS interrupt config\n");
8383                 return;
8384         }
8385
8386         /* Set valid module led off */
8387         bnx2x_set_sfp_module_fault_led(params, MISC_REGISTERS_GPIO_HIGH);
8388
8389         /* Get current gpio val reflecting module plugged in / out*/
8390         gpio_val = bnx2x_get_gpio(bp, gpio_num, gpio_port);
8391
8392         /* Call the handling function in case module is detected */
8393         if (gpio_val == 0) {
8394                 bnx2x_power_sfp_module(params, phy, 1);
8395                 bnx2x_set_gpio_int(bp, gpio_num,
8396                                    MISC_REGISTERS_GPIO_INT_OUTPUT_CLR,
8397                                    gpio_port);
8398                 if (bnx2x_wait_for_sfp_module_initialized(phy, params) == 0)
8399                         bnx2x_sfp_module_detection(phy, params);
8400                 else
8401                         DP(NETIF_MSG_LINK, "SFP+ module is not initialized\n");
8402         } else {
8403                 u32 val = REG_RD(bp, params->shmem_base +
8404                                  offsetof(struct shmem_region, dev_info.
8405                                           port_feature_config[params->port].
8406                                           config));
8407                 bnx2x_set_gpio_int(bp, gpio_num,
8408                                    MISC_REGISTERS_GPIO_INT_OUTPUT_SET,
8409                                    gpio_port);
8410                 /* Module was plugged out.
8411                  * Disable transmit for this module
8412                  */
8413                 phy->media_type = ETH_PHY_NOT_PRESENT;
8414                 if (((val & PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_MASK) ==
8415                      PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_DISABLE_TX_LASER) ||
8416                     CHIP_IS_E3(bp))
8417                         bnx2x_sfp_set_transmitter(params, phy, 0);
8418         }
8419 }
8420
8421 /******************************************************************/
8422 /*              Used by 8706 and 8727                             */
8423 /******************************************************************/
8424 static void bnx2x_sfp_mask_fault(struct bnx2x *bp,
8425                                  struct bnx2x_phy *phy,
8426                                  u16 alarm_status_offset,
8427                                  u16 alarm_ctrl_offset)
8428 {
8429         u16 alarm_status, val;
8430         bnx2x_cl45_read(bp, phy,
8431                         MDIO_PMA_DEVAD, alarm_status_offset,
8432                         &alarm_status);
8433         bnx2x_cl45_read(bp, phy,
8434                         MDIO_PMA_DEVAD, alarm_status_offset,
8435                         &alarm_status);
8436         /* Mask or enable the fault event. */
8437         bnx2x_cl45_read(bp, phy, MDIO_PMA_DEVAD, alarm_ctrl_offset, &val);
8438         if (alarm_status & (1<<0))
8439                 val &= ~(1<<0);
8440         else
8441                 val |= (1<<0);
8442         bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, alarm_ctrl_offset, val);
8443 }
8444 /******************************************************************/
8445 /*              common BCM8706/BCM8726 PHY SECTION                */
8446 /******************************************************************/
8447 static u8 bnx2x_8706_8726_read_status(struct bnx2x_phy *phy,
8448                                       struct link_params *params,
8449                                       struct link_vars *vars)
8450 {
8451         u8 link_up = 0;
8452         u16 val1, val2, rx_sd, pcs_status;
8453         struct bnx2x *bp = params->bp;
8454         DP(NETIF_MSG_LINK, "XGXS 8706/8726\n");
8455         /* Clear RX Alarm*/
8456         bnx2x_cl45_read(bp, phy,
8457                         MDIO_PMA_DEVAD, MDIO_PMA_LASI_RXSTAT, &val2);
8458
8459         bnx2x_sfp_mask_fault(bp, phy, MDIO_PMA_LASI_TXSTAT,
8460                              MDIO_PMA_LASI_TXCTRL);
8461
8462         /* clear LASI indication*/
8463         bnx2x_cl45_read(bp, phy,
8464                         MDIO_PMA_DEVAD, MDIO_PMA_LASI_STAT, &val1);
8465         bnx2x_cl45_read(bp, phy,
8466                         MDIO_PMA_DEVAD, MDIO_PMA_LASI_STAT, &val2);
8467         DP(NETIF_MSG_LINK, "8706/8726 LASI status 0x%x--> 0x%x\n", val1, val2);
8468
8469         bnx2x_cl45_read(bp, phy,
8470                         MDIO_PMA_DEVAD, MDIO_PMA_REG_RX_SD, &rx_sd);
8471         bnx2x_cl45_read(bp, phy,
8472                         MDIO_PCS_DEVAD, MDIO_PCS_REG_STATUS, &pcs_status);
8473         bnx2x_cl45_read(bp, phy,
8474                         MDIO_AN_DEVAD, MDIO_AN_REG_LINK_STATUS, &val2);
8475         bnx2x_cl45_read(bp, phy,
8476                         MDIO_AN_DEVAD, MDIO_AN_REG_LINK_STATUS, &val2);
8477
8478         DP(NETIF_MSG_LINK, "8706/8726 rx_sd 0x%x pcs_status 0x%x 1Gbps"
8479                         " link_status 0x%x\n", rx_sd, pcs_status, val2);
8480         /* Link is up if both bit 0 of pmd_rx_sd and bit 0 of pcs_status
8481          * are set, or if the autoneg bit 1 is set
8482          */
8483         link_up = ((rx_sd & pcs_status & 0x1) || (val2 & (1<<1)));
8484         if (link_up) {
8485                 if (val2 & (1<<1))
8486                         vars->line_speed = SPEED_1000;
8487                 else
8488                         vars->line_speed = SPEED_10000;
8489                 bnx2x_ext_phy_resolve_fc(phy, params, vars);
8490                 vars->duplex = DUPLEX_FULL;
8491         }
8492
8493         /* Capture 10G link fault. Read twice to clear stale value. */
8494         if (vars->line_speed == SPEED_10000) {
8495                 bnx2x_cl45_read(bp, phy, MDIO_PMA_DEVAD,
8496                             MDIO_PMA_LASI_TXSTAT, &val1);
8497                 bnx2x_cl45_read(bp, phy, MDIO_PMA_DEVAD,
8498                             MDIO_PMA_LASI_TXSTAT, &val1);
8499                 if (val1 & (1<<0))
8500                         vars->fault_detected = 1;
8501         }
8502
8503         return link_up;
8504 }
8505
8506 /******************************************************************/
8507 /*                      BCM8706 PHY SECTION                       */
8508 /******************************************************************/
8509 static u8 bnx2x_8706_config_init(struct bnx2x_phy *phy,
8510                                  struct link_params *params,
8511                                  struct link_vars *vars)
8512 {
8513         u32 tx_en_mode;
8514         u16 cnt, val, tmp1;
8515         struct bnx2x *bp = params->bp;
8516
8517         bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_2,
8518                        MISC_REGISTERS_GPIO_OUTPUT_HIGH, params->port);
8519         /* HW reset */
8520         bnx2x_ext_phy_hw_reset(bp, params->port);
8521         bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 0xa040);
8522         bnx2x_wait_reset_complete(bp, phy, params);
8523
8524         /* Wait until fw is loaded */
8525         for (cnt = 0; cnt < 100; cnt++) {
8526                 bnx2x_cl45_read(bp, phy,
8527                                 MDIO_PMA_DEVAD, MDIO_PMA_REG_ROM_VER1, &val);
8528                 if (val)
8529                         break;
8530                 msleep(10);
8531         }
8532         DP(NETIF_MSG_LINK, "XGXS 8706 is initialized after %d ms\n", cnt);
8533         if ((params->feature_config_flags &
8534              FEATURE_CONFIG_OVERRIDE_PREEMPHASIS_ENABLED)) {
8535                 u8 i;
8536                 u16 reg;
8537                 for (i = 0; i < 4; i++) {
8538                         reg = MDIO_XS_8706_REG_BANK_RX0 +
8539                                 i*(MDIO_XS_8706_REG_BANK_RX1 -
8540                                    MDIO_XS_8706_REG_BANK_RX0);
8541                         bnx2x_cl45_read(bp, phy, MDIO_XS_DEVAD, reg, &val);
8542                         /* Clear first 3 bits of the control */
8543                         val &= ~0x7;
8544                         /* Set control bits according to configuration */
8545                         val |= (phy->rx_preemphasis[i] & 0x7);
8546                         DP(NETIF_MSG_LINK, "Setting RX Equalizer to BCM8706"
8547                                    " reg 0x%x <-- val 0x%x\n", reg, val);
8548                         bnx2x_cl45_write(bp, phy, MDIO_XS_DEVAD, reg, val);
8549                 }
8550         }
8551         /* Force speed */
8552         if (phy->req_line_speed == SPEED_10000) {
8553                 DP(NETIF_MSG_LINK, "XGXS 8706 force 10Gbps\n");
8554
8555                 bnx2x_cl45_write(bp, phy,
8556                                  MDIO_PMA_DEVAD,
8557                                  MDIO_PMA_REG_DIGITAL_CTRL, 0x400);
8558                 bnx2x_cl45_write(bp, phy,
8559                                  MDIO_PMA_DEVAD, MDIO_PMA_LASI_TXCTRL,
8560                                  0);
8561                 /* Arm LASI for link and Tx fault. */
8562                 bnx2x_cl45_write(bp, phy,
8563                                  MDIO_PMA_DEVAD, MDIO_PMA_LASI_CTRL, 3);
8564         } else {
8565                 /* Force 1Gbps using autoneg with 1G advertisement */
8566
8567                 /* Allow CL37 through CL73 */
8568                 DP(NETIF_MSG_LINK, "XGXS 8706 AutoNeg\n");
8569                 bnx2x_cl45_write(bp, phy,
8570                                  MDIO_AN_DEVAD, MDIO_AN_REG_CL37_CL73, 0x040c);
8571
8572                 /* Enable Full-Duplex advertisement on CL37 */
8573                 bnx2x_cl45_write(bp, phy,
8574                                  MDIO_AN_DEVAD, MDIO_AN_REG_CL37_FC_LP, 0x0020);
8575                 /* Enable CL37 AN */
8576                 bnx2x_cl45_write(bp, phy,
8577                                  MDIO_AN_DEVAD, MDIO_AN_REG_CL37_AN, 0x1000);
8578                 /* 1G support */
8579                 bnx2x_cl45_write(bp, phy,
8580                                  MDIO_AN_DEVAD, MDIO_AN_REG_ADV, (1<<5));
8581
8582                 /* Enable clause 73 AN */
8583                 bnx2x_cl45_write(bp, phy,
8584                                  MDIO_AN_DEVAD, MDIO_AN_REG_CTRL, 0x1200);
8585                 bnx2x_cl45_write(bp, phy,
8586                                  MDIO_PMA_DEVAD, MDIO_PMA_LASI_RXCTRL,
8587                                  0x0400);
8588                 bnx2x_cl45_write(bp, phy,
8589                                  MDIO_PMA_DEVAD, MDIO_PMA_LASI_CTRL,
8590                                  0x0004);
8591         }
8592         bnx2x_save_bcm_spirom_ver(bp, phy, params->port);
8593
8594         /* If TX Laser is controlled by GPIO_0, do not let PHY go into low
8595          * power mode, if TX Laser is disabled
8596          */
8597
8598         tx_en_mode = REG_RD(bp, params->shmem_base +
8599                             offsetof(struct shmem_region,
8600                                 dev_info.port_hw_config[params->port].sfp_ctrl))
8601                         & PORT_HW_CFG_TX_LASER_MASK;
8602
8603         if (tx_en_mode == PORT_HW_CFG_TX_LASER_GPIO0) {
8604                 DP(NETIF_MSG_LINK, "Enabling TXONOFF_PWRDN_DIS\n");
8605                 bnx2x_cl45_read(bp, phy,
8606                         MDIO_PMA_DEVAD, MDIO_PMA_REG_DIGITAL_CTRL, &tmp1);
8607                 tmp1 |= 0x1;
8608                 bnx2x_cl45_write(bp, phy,
8609                         MDIO_PMA_DEVAD, MDIO_PMA_REG_DIGITAL_CTRL, tmp1);
8610         }
8611
8612         return 0;
8613 }
8614
8615 static int bnx2x_8706_read_status(struct bnx2x_phy *phy,
8616                                   struct link_params *params,
8617                                   struct link_vars *vars)
8618 {
8619         return bnx2x_8706_8726_read_status(phy, params, vars);
8620 }
8621
8622 /******************************************************************/
8623 /*                      BCM8726 PHY SECTION                       */
8624 /******************************************************************/
8625 static void bnx2x_8726_config_loopback(struct bnx2x_phy *phy,
8626                                        struct link_params *params)
8627 {
8628         struct bnx2x *bp = params->bp;
8629         DP(NETIF_MSG_LINK, "PMA/PMD ext_phy_loopback: 8726\n");
8630         bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 0x0001);
8631 }
8632
8633 static void bnx2x_8726_external_rom_boot(struct bnx2x_phy *phy,
8634                                          struct link_params *params)
8635 {
8636         struct bnx2x *bp = params->bp;
8637         /* Need to wait 100ms after reset */
8638         msleep(100);
8639
8640         /* Micro controller re-boot */
8641         bnx2x_cl45_write(bp, phy,
8642                          MDIO_PMA_DEVAD, MDIO_PMA_REG_GEN_CTRL, 0x018B);
8643
8644         /* Set soft reset */
8645         bnx2x_cl45_write(bp, phy,
8646                          MDIO_PMA_DEVAD,
8647                          MDIO_PMA_REG_GEN_CTRL,
8648                          MDIO_PMA_REG_GEN_CTRL_ROM_MICRO_RESET);
8649
8650         bnx2x_cl45_write(bp, phy,
8651                          MDIO_PMA_DEVAD,
8652                          MDIO_PMA_REG_MISC_CTRL1, 0x0001);
8653
8654         bnx2x_cl45_write(bp, phy,
8655                          MDIO_PMA_DEVAD,
8656                          MDIO_PMA_REG_GEN_CTRL,
8657                          MDIO_PMA_REG_GEN_CTRL_ROM_RESET_INTERNAL_MP);
8658
8659         /* wait for 150ms for microcode load */
8660         msleep(150);
8661
8662         /* Disable serial boot control, tristates pins SS_N, SCK, MOSI, MISO */
8663         bnx2x_cl45_write(bp, phy,
8664                          MDIO_PMA_DEVAD,
8665                          MDIO_PMA_REG_MISC_CTRL1, 0x0000);
8666
8667         msleep(200);
8668         bnx2x_save_bcm_spirom_ver(bp, phy, params->port);
8669 }
8670
8671 static u8 bnx2x_8726_read_status(struct bnx2x_phy *phy,
8672                                  struct link_params *params,
8673                                  struct link_vars *vars)
8674 {
8675         struct bnx2x *bp = params->bp;
8676         u16 val1;
8677         u8 link_up = bnx2x_8706_8726_read_status(phy, params, vars);
8678         if (link_up) {
8679                 bnx2x_cl45_read(bp, phy,
8680                                 MDIO_PMA_DEVAD, MDIO_PMA_REG_PHY_IDENTIFIER,
8681                                 &val1);
8682                 if (val1 & (1<<15)) {
8683                         DP(NETIF_MSG_LINK, "Tx is disabled\n");
8684                         link_up = 0;
8685                         vars->line_speed = 0;
8686                 }
8687         }
8688         return link_up;
8689 }
8690
8691
8692 static int bnx2x_8726_config_init(struct bnx2x_phy *phy,
8693                                   struct link_params *params,
8694                                   struct link_vars *vars)
8695 {
8696         struct bnx2x *bp = params->bp;
8697         DP(NETIF_MSG_LINK, "Initializing BCM8726\n");
8698
8699         bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 1<<15);
8700         bnx2x_wait_reset_complete(bp, phy, params);
8701
8702         bnx2x_8726_external_rom_boot(phy, params);
8703
8704         /* Need to call module detected on initialization since the module
8705          * detection triggered by actual module insertion might occur before
8706          * driver is loaded, and when driver is loaded, it reset all
8707          * registers, including the transmitter
8708          */
8709         bnx2x_sfp_module_detection(phy, params);
8710
8711         if (phy->req_line_speed == SPEED_1000) {
8712                 DP(NETIF_MSG_LINK, "Setting 1G force\n");
8713                 bnx2x_cl45_write(bp, phy,
8714                                  MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 0x40);
8715                 bnx2x_cl45_write(bp, phy,
8716                                  MDIO_PMA_DEVAD, MDIO_PMA_REG_10G_CTRL2, 0xD);
8717                 bnx2x_cl45_write(bp, phy,
8718                                  MDIO_PMA_DEVAD, MDIO_PMA_LASI_CTRL, 0x5);
8719                 bnx2x_cl45_write(bp, phy,
8720                                  MDIO_PMA_DEVAD, MDIO_PMA_LASI_RXCTRL,
8721                                  0x400);
8722         } else if ((phy->req_line_speed == SPEED_AUTO_NEG) &&
8723                    (phy->speed_cap_mask &
8724                       PORT_HW_CFG_SPEED_CAPABILITY_D0_1G) &&
8725                    ((phy->speed_cap_mask &
8726                       PORT_HW_CFG_SPEED_CAPABILITY_D0_10G) !=
8727                     PORT_HW_CFG_SPEED_CAPABILITY_D0_10G)) {
8728                 DP(NETIF_MSG_LINK, "Setting 1G clause37\n");
8729                 /* Set Flow control */
8730                 bnx2x_ext_phy_set_pause(params, phy, vars);
8731                 bnx2x_cl45_write(bp, phy,
8732                                  MDIO_AN_DEVAD, MDIO_AN_REG_ADV, 0x20);
8733                 bnx2x_cl45_write(bp, phy,
8734                                  MDIO_AN_DEVAD, MDIO_AN_REG_CL37_CL73, 0x040c);
8735                 bnx2x_cl45_write(bp, phy,
8736                                  MDIO_AN_DEVAD, MDIO_AN_REG_CL37_FC_LD, 0x0020);
8737                 bnx2x_cl45_write(bp, phy,
8738                                  MDIO_AN_DEVAD, MDIO_AN_REG_CL37_AN, 0x1000);
8739                 bnx2x_cl45_write(bp, phy,
8740                                 MDIO_AN_DEVAD, MDIO_AN_REG_CTRL, 0x1200);
8741                 /* Enable RX-ALARM control to receive interrupt for 1G speed
8742                  * change
8743                  */
8744                 bnx2x_cl45_write(bp, phy,
8745                                  MDIO_PMA_DEVAD, MDIO_PMA_LASI_CTRL, 0x4);
8746                 bnx2x_cl45_write(bp, phy,
8747                                  MDIO_PMA_DEVAD, MDIO_PMA_LASI_RXCTRL,
8748                                  0x400);
8749
8750         } else { /* Default 10G. Set only LASI control */
8751                 bnx2x_cl45_write(bp, phy,
8752                                  MDIO_PMA_DEVAD, MDIO_PMA_LASI_CTRL, 1);
8753         }
8754
8755         /* Set TX PreEmphasis if needed */
8756         if ((params->feature_config_flags &
8757              FEATURE_CONFIG_OVERRIDE_PREEMPHASIS_ENABLED)) {
8758                 DP(NETIF_MSG_LINK,
8759                    "Setting TX_CTRL1 0x%x, TX_CTRL2 0x%x\n",
8760                          phy->tx_preemphasis[0],
8761                          phy->tx_preemphasis[1]);
8762                 bnx2x_cl45_write(bp, phy,
8763                                  MDIO_PMA_DEVAD,
8764                                  MDIO_PMA_REG_8726_TX_CTRL1,
8765                                  phy->tx_preemphasis[0]);
8766
8767                 bnx2x_cl45_write(bp, phy,
8768                                  MDIO_PMA_DEVAD,
8769                                  MDIO_PMA_REG_8726_TX_CTRL2,
8770                                  phy->tx_preemphasis[1]);
8771         }
8772
8773         return 0;
8774
8775 }
8776
8777 static void bnx2x_8726_link_reset(struct bnx2x_phy *phy,
8778                                   struct link_params *params)
8779 {
8780         struct bnx2x *bp = params->bp;
8781         DP(NETIF_MSG_LINK, "bnx2x_8726_link_reset port %d\n", params->port);
8782         /* Set serial boot control for external load */
8783         bnx2x_cl45_write(bp, phy,
8784                          MDIO_PMA_DEVAD,
8785                          MDIO_PMA_REG_GEN_CTRL, 0x0001);
8786 }
8787
8788 /******************************************************************/
8789 /*                      BCM8727 PHY SECTION                       */
8790 /******************************************************************/
8791
8792 static void bnx2x_8727_set_link_led(struct bnx2x_phy *phy,
8793                                     struct link_params *params, u8 mode)
8794 {
8795         struct bnx2x *bp = params->bp;
8796         u16 led_mode_bitmask = 0;
8797         u16 gpio_pins_bitmask = 0;
8798         u16 val;
8799         /* Only NOC flavor requires to set the LED specifically */
8800         if (!(phy->flags & FLAGS_NOC))
8801                 return;
8802         switch (mode) {
8803         case LED_MODE_FRONT_PANEL_OFF:
8804         case LED_MODE_OFF:
8805                 led_mode_bitmask = 0;
8806                 gpio_pins_bitmask = 0x03;
8807                 break;
8808         case LED_MODE_ON:
8809                 led_mode_bitmask = 0;
8810                 gpio_pins_bitmask = 0x02;
8811                 break;
8812         case LED_MODE_OPER:
8813                 led_mode_bitmask = 0x60;
8814                 gpio_pins_bitmask = 0x11;
8815                 break;
8816         }
8817         bnx2x_cl45_read(bp, phy,
8818                         MDIO_PMA_DEVAD,
8819                         MDIO_PMA_REG_8727_PCS_OPT_CTRL,
8820                         &val);
8821         val &= 0xff8f;
8822         val |= led_mode_bitmask;
8823         bnx2x_cl45_write(bp, phy,
8824                          MDIO_PMA_DEVAD,
8825                          MDIO_PMA_REG_8727_PCS_OPT_CTRL,
8826                          val);
8827         bnx2x_cl45_read(bp, phy,
8828                         MDIO_PMA_DEVAD,
8829                         MDIO_PMA_REG_8727_GPIO_CTRL,
8830                         &val);
8831         val &= 0xffe0;
8832         val |= gpio_pins_bitmask;
8833         bnx2x_cl45_write(bp, phy,
8834                          MDIO_PMA_DEVAD,
8835                          MDIO_PMA_REG_8727_GPIO_CTRL,
8836                          val);
8837 }
8838 static void bnx2x_8727_hw_reset(struct bnx2x_phy *phy,
8839                                 struct link_params *params) {
8840         u32 swap_val, swap_override;
8841         u8 port;
8842         /* The PHY reset is controlled by GPIO 1. Fake the port number
8843          * to cancel the swap done in set_gpio()
8844          */
8845         struct bnx2x *bp = params->bp;
8846         swap_val = REG_RD(bp, NIG_REG_PORT_SWAP);
8847         swap_override = REG_RD(bp, NIG_REG_STRAP_OVERRIDE);
8848         port = (swap_val && swap_override) ^ 1;
8849         bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_1,
8850                        MISC_REGISTERS_GPIO_OUTPUT_LOW, port);
8851 }
8852
8853 static int bnx2x_8727_config_init(struct bnx2x_phy *phy,
8854                                   struct link_params *params,
8855                                   struct link_vars *vars)
8856 {
8857         u32 tx_en_mode;
8858         u16 tmp1, val, mod_abs, tmp2;
8859         u16 rx_alarm_ctrl_val;
8860         u16 lasi_ctrl_val;
8861         struct bnx2x *bp = params->bp;
8862         /* Enable PMD link, MOD_ABS_FLT, and 1G link alarm */
8863
8864         bnx2x_wait_reset_complete(bp, phy, params);
8865         rx_alarm_ctrl_val = (1<<2) | (1<<5) ;
8866         /* Should be 0x6 to enable XS on Tx side. */
8867         lasi_ctrl_val = 0x0006;
8868
8869         DP(NETIF_MSG_LINK, "Initializing BCM8727\n");
8870         /* enable LASI */
8871         bnx2x_cl45_write(bp, phy,
8872                          MDIO_PMA_DEVAD, MDIO_PMA_LASI_RXCTRL,
8873                          rx_alarm_ctrl_val);
8874         bnx2x_cl45_write(bp, phy,
8875                          MDIO_PMA_DEVAD, MDIO_PMA_LASI_TXCTRL,
8876                          0);
8877         bnx2x_cl45_write(bp, phy,
8878                          MDIO_PMA_DEVAD, MDIO_PMA_LASI_CTRL, lasi_ctrl_val);
8879
8880         /* Initially configure MOD_ABS to interrupt when module is
8881          * presence( bit 8)
8882          */
8883         bnx2x_cl45_read(bp, phy,
8884                         MDIO_PMA_DEVAD, MDIO_PMA_REG_PHY_IDENTIFIER, &mod_abs);
8885         /* Set EDC off by setting OPTXLOS signal input to low (bit 9).
8886          * When the EDC is off it locks onto a reference clock and avoids
8887          * becoming 'lost'
8888          */
8889         mod_abs &= ~(1<<8);
8890         if (!(phy->flags & FLAGS_NOC))
8891                 mod_abs &= ~(1<<9);
8892         bnx2x_cl45_write(bp, phy,
8893                          MDIO_PMA_DEVAD, MDIO_PMA_REG_PHY_IDENTIFIER, mod_abs);
8894
8895
8896         /* Enable/Disable PHY transmitter output */
8897         bnx2x_set_disable_pmd_transmit(params, phy, 0);
8898
8899         /* Make MOD_ABS give interrupt on change */
8900         bnx2x_cl45_read(bp, phy, MDIO_PMA_DEVAD, MDIO_PMA_REG_8727_PCS_OPT_CTRL,
8901                         &val);
8902         val |= (1<<12);
8903         if (phy->flags & FLAGS_NOC)
8904                 val |= (3<<5);
8905
8906         /* Set 8727 GPIOs to input to allow reading from the 8727 GPIO0
8907          * status which reflect SFP+ module over-current
8908          */
8909         if (!(phy->flags & FLAGS_NOC))
8910                 val &= 0xff8f; /* Reset bits 4-6 */
8911         bnx2x_cl45_write(bp, phy,
8912                          MDIO_PMA_DEVAD, MDIO_PMA_REG_8727_PCS_OPT_CTRL, val);
8913
8914         bnx2x_8727_power_module(bp, phy, 1);
8915
8916         bnx2x_cl45_read(bp, phy,
8917                         MDIO_PMA_DEVAD, MDIO_PMA_REG_M8051_MSGOUT_REG, &tmp1);
8918
8919         bnx2x_cl45_read(bp, phy,
8920                         MDIO_PMA_DEVAD, MDIO_PMA_LASI_RXSTAT, &tmp1);
8921
8922         /* Set option 1G speed */
8923         if (phy->req_line_speed == SPEED_1000) {
8924                 DP(NETIF_MSG_LINK, "Setting 1G force\n");
8925                 bnx2x_cl45_write(bp, phy,
8926                                  MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 0x40);
8927                 bnx2x_cl45_write(bp, phy,
8928                                  MDIO_PMA_DEVAD, MDIO_PMA_REG_10G_CTRL2, 0xD);
8929                 bnx2x_cl45_read(bp, phy,
8930                                 MDIO_PMA_DEVAD, MDIO_PMA_REG_10G_CTRL2, &tmp1);
8931                 DP(NETIF_MSG_LINK, "1.7 = 0x%x\n", tmp1);
8932                 /* Power down the XAUI until link is up in case of dual-media
8933                  * and 1G
8934                  */
8935                 if (DUAL_MEDIA(params)) {
8936                         bnx2x_cl45_read(bp, phy,
8937                                         MDIO_PMA_DEVAD,
8938                                         MDIO_PMA_REG_8727_PCS_GP, &val);
8939                         val |= (3<<10);
8940                         bnx2x_cl45_write(bp, phy,
8941                                          MDIO_PMA_DEVAD,
8942                                          MDIO_PMA_REG_8727_PCS_GP, val);
8943                 }
8944         } else if ((phy->req_line_speed == SPEED_AUTO_NEG) &&
8945                    ((phy->speed_cap_mask &
8946                      PORT_HW_CFG_SPEED_CAPABILITY_D0_1G)) &&
8947                    ((phy->speed_cap_mask &
8948                       PORT_HW_CFG_SPEED_CAPABILITY_D0_10G) !=
8949                    PORT_HW_CFG_SPEED_CAPABILITY_D0_10G)) {
8950
8951                 DP(NETIF_MSG_LINK, "Setting 1G clause37\n");
8952                 bnx2x_cl45_write(bp, phy,
8953                                  MDIO_AN_DEVAD, MDIO_AN_REG_8727_MISC_CTRL, 0);
8954                 bnx2x_cl45_write(bp, phy,
8955                                  MDIO_AN_DEVAD, MDIO_AN_REG_CL37_AN, 0x1300);
8956         } else {
8957                 /* Since the 8727 has only single reset pin, need to set the 10G
8958                  * registers although it is default
8959                  */
8960                 bnx2x_cl45_write(bp, phy,
8961                                  MDIO_AN_DEVAD, MDIO_AN_REG_8727_MISC_CTRL,
8962                                  0x0020);
8963                 bnx2x_cl45_write(bp, phy,
8964                                  MDIO_AN_DEVAD, MDIO_AN_REG_CL37_AN, 0x0100);
8965                 bnx2x_cl45_write(bp, phy,
8966                                  MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 0x2040);
8967                 bnx2x_cl45_write(bp, phy,
8968                                  MDIO_PMA_DEVAD, MDIO_PMA_REG_10G_CTRL2,
8969                                  0x0008);
8970         }
8971
8972         /* Set 2-wire transfer rate of SFP+ module EEPROM
8973          * to 100Khz since some DACs(direct attached cables) do
8974          * not work at 400Khz.
8975          */
8976         bnx2x_cl45_write(bp, phy,
8977                          MDIO_PMA_DEVAD, MDIO_PMA_REG_8727_TWO_WIRE_SLAVE_ADDR,
8978                          0xa001);
8979
8980         /* Set TX PreEmphasis if needed */
8981         if ((params->feature_config_flags &
8982              FEATURE_CONFIG_OVERRIDE_PREEMPHASIS_ENABLED)) {
8983                 DP(NETIF_MSG_LINK, "Setting TX_CTRL1 0x%x, TX_CTRL2 0x%x\n",
8984                            phy->tx_preemphasis[0],
8985                            phy->tx_preemphasis[1]);
8986                 bnx2x_cl45_write(bp, phy,
8987                                  MDIO_PMA_DEVAD, MDIO_PMA_REG_8727_TX_CTRL1,
8988                                  phy->tx_preemphasis[0]);
8989
8990                 bnx2x_cl45_write(bp, phy,
8991                                  MDIO_PMA_DEVAD, MDIO_PMA_REG_8727_TX_CTRL2,
8992                                  phy->tx_preemphasis[1]);
8993         }
8994
8995         /* If TX Laser is controlled by GPIO_0, do not let PHY go into low
8996          * power mode, if TX Laser is disabled
8997          */
8998         tx_en_mode = REG_RD(bp, params->shmem_base +
8999                             offsetof(struct shmem_region,
9000                                 dev_info.port_hw_config[params->port].sfp_ctrl))
9001                         & PORT_HW_CFG_TX_LASER_MASK;
9002
9003         if (tx_en_mode == PORT_HW_CFG_TX_LASER_GPIO0) {
9004
9005                 DP(NETIF_MSG_LINK, "Enabling TXONOFF_PWRDN_DIS\n");
9006                 bnx2x_cl45_read(bp, phy,
9007                         MDIO_PMA_DEVAD, MDIO_PMA_REG_8727_OPT_CFG_REG, &tmp2);
9008                 tmp2 |= 0x1000;
9009                 tmp2 &= 0xFFEF;
9010                 bnx2x_cl45_write(bp, phy,
9011                         MDIO_PMA_DEVAD, MDIO_PMA_REG_8727_OPT_CFG_REG, tmp2);
9012                 bnx2x_cl45_read(bp, phy,
9013                                 MDIO_PMA_DEVAD, MDIO_PMA_REG_PHY_IDENTIFIER,
9014                                 &tmp2);
9015                 bnx2x_cl45_write(bp, phy,
9016                                  MDIO_PMA_DEVAD, MDIO_PMA_REG_PHY_IDENTIFIER,
9017                                  (tmp2 & 0x7fff));
9018         }
9019
9020         return 0;
9021 }
9022
9023 static void bnx2x_8727_handle_mod_abs(struct bnx2x_phy *phy,
9024                                       struct link_params *params)
9025 {
9026         struct bnx2x *bp = params->bp;
9027         u16 mod_abs, rx_alarm_status;
9028         u32 val = REG_RD(bp, params->shmem_base +
9029                              offsetof(struct shmem_region, dev_info.
9030                                       port_feature_config[params->port].
9031                                       config));
9032         bnx2x_cl45_read(bp, phy,
9033                         MDIO_PMA_DEVAD,
9034                         MDIO_PMA_REG_PHY_IDENTIFIER, &mod_abs);
9035         if (mod_abs & (1<<8)) {
9036
9037                 /* Module is absent */
9038                 DP(NETIF_MSG_LINK,
9039                    "MOD_ABS indication show module is absent\n");
9040                 phy->media_type = ETH_PHY_NOT_PRESENT;
9041                 /* 1. Set mod_abs to detect next module
9042                  *    presence event
9043                  * 2. Set EDC off by setting OPTXLOS signal input to low
9044                  *    (bit 9).
9045                  *    When the EDC is off it locks onto a reference clock and
9046                  *    avoids becoming 'lost'.
9047                  */
9048                 mod_abs &= ~(1<<8);
9049                 if (!(phy->flags & FLAGS_NOC))
9050                         mod_abs &= ~(1<<9);
9051                 bnx2x_cl45_write(bp, phy,
9052                                  MDIO_PMA_DEVAD,
9053                                  MDIO_PMA_REG_PHY_IDENTIFIER, mod_abs);
9054
9055                 /* Clear RX alarm since it stays up as long as
9056                  * the mod_abs wasn't changed
9057                  */
9058                 bnx2x_cl45_read(bp, phy,
9059                                 MDIO_PMA_DEVAD,
9060                                 MDIO_PMA_LASI_RXSTAT, &rx_alarm_status);
9061
9062         } else {
9063                 /* Module is present */
9064                 DP(NETIF_MSG_LINK,
9065                    "MOD_ABS indication show module is present\n");
9066                 /* First disable transmitter, and if the module is ok, the
9067                  * module_detection will enable it
9068                  * 1. Set mod_abs to detect next module absent event ( bit 8)
9069                  * 2. Restore the default polarity of the OPRXLOS signal and
9070                  * this signal will then correctly indicate the presence or
9071                  * absence of the Rx signal. (bit 9)
9072                  */
9073                 mod_abs |= (1<<8);
9074                 if (!(phy->flags & FLAGS_NOC))
9075                         mod_abs |= (1<<9);
9076                 bnx2x_cl45_write(bp, phy,
9077                                  MDIO_PMA_DEVAD,
9078                                  MDIO_PMA_REG_PHY_IDENTIFIER, mod_abs);
9079
9080                 /* Clear RX alarm since it stays up as long as the mod_abs
9081                  * wasn't changed. This is need to be done before calling the
9082                  * module detection, otherwise it will clear* the link update
9083                  * alarm
9084                  */
9085                 bnx2x_cl45_read(bp, phy,
9086                                 MDIO_PMA_DEVAD,
9087                                 MDIO_PMA_LASI_RXSTAT, &rx_alarm_status);
9088
9089
9090                 if ((val & PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_MASK) ==
9091                     PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_DISABLE_TX_LASER)
9092                         bnx2x_sfp_set_transmitter(params, phy, 0);
9093
9094                 if (bnx2x_wait_for_sfp_module_initialized(phy, params) == 0)
9095                         bnx2x_sfp_module_detection(phy, params);
9096                 else
9097                         DP(NETIF_MSG_LINK, "SFP+ module is not initialized\n");
9098         }
9099
9100         DP(NETIF_MSG_LINK, "8727 RX_ALARM_STATUS 0x%x\n",
9101                    rx_alarm_status);
9102         /* No need to check link status in case of module plugged in/out */
9103 }
9104
9105 static u8 bnx2x_8727_read_status(struct bnx2x_phy *phy,
9106                                  struct link_params *params,
9107                                  struct link_vars *vars)
9108
9109 {
9110         struct bnx2x *bp = params->bp;
9111         u8 link_up = 0, oc_port = params->port;
9112         u16 link_status = 0;
9113         u16 rx_alarm_status, lasi_ctrl, val1;
9114
9115         /* If PHY is not initialized, do not check link status */
9116         bnx2x_cl45_read(bp, phy,
9117                         MDIO_PMA_DEVAD, MDIO_PMA_LASI_CTRL,
9118                         &lasi_ctrl);
9119         if (!lasi_ctrl)
9120                 return 0;
9121
9122         /* Check the LASI on Rx */
9123         bnx2x_cl45_read(bp, phy,
9124                         MDIO_PMA_DEVAD, MDIO_PMA_LASI_RXSTAT,
9125                         &rx_alarm_status);
9126         vars->line_speed = 0;
9127         DP(NETIF_MSG_LINK, "8727 RX_ALARM_STATUS  0x%x\n", rx_alarm_status);
9128
9129         bnx2x_sfp_mask_fault(bp, phy, MDIO_PMA_LASI_TXSTAT,
9130                              MDIO_PMA_LASI_TXCTRL);
9131
9132         bnx2x_cl45_read(bp, phy,
9133                         MDIO_PMA_DEVAD, MDIO_PMA_LASI_STAT, &val1);
9134
9135         DP(NETIF_MSG_LINK, "8727 LASI status 0x%x\n", val1);
9136
9137         /* Clear MSG-OUT */
9138         bnx2x_cl45_read(bp, phy,
9139                         MDIO_PMA_DEVAD, MDIO_PMA_REG_M8051_MSGOUT_REG, &val1);
9140
9141         /* If a module is present and there is need to check
9142          * for over current
9143          */
9144         if (!(phy->flags & FLAGS_NOC) && !(rx_alarm_status & (1<<5))) {
9145                 /* Check over-current using 8727 GPIO0 input*/
9146                 bnx2x_cl45_read(bp, phy,
9147                                 MDIO_PMA_DEVAD, MDIO_PMA_REG_8727_GPIO_CTRL,
9148                                 &val1);
9149
9150                 if ((val1 & (1<<8)) == 0) {
9151                         if (!CHIP_IS_E1x(bp))
9152                                 oc_port = BP_PATH(bp) + (params->port << 1);
9153                         DP(NETIF_MSG_LINK,
9154                            "8727 Power fault has been detected on port %d\n",
9155                            oc_port);
9156                         netdev_err(bp->dev, "Error: Power fault on Port %d has "
9157                                             "been detected and the power to "
9158                                             "that SFP+ module has been removed "
9159                                             "to prevent failure of the card. "
9160                                             "Please remove the SFP+ module and "
9161                                             "restart the system to clear this "
9162                                             "error.\n",
9163                          oc_port);
9164                         /* Disable all RX_ALARMs except for mod_abs */
9165                         bnx2x_cl45_write(bp, phy,
9166                                          MDIO_PMA_DEVAD,
9167                                          MDIO_PMA_LASI_RXCTRL, (1<<5));
9168
9169                         bnx2x_cl45_read(bp, phy,
9170                                         MDIO_PMA_DEVAD,
9171                                         MDIO_PMA_REG_PHY_IDENTIFIER, &val1);
9172                         /* Wait for module_absent_event */
9173                         val1 |= (1<<8);
9174                         bnx2x_cl45_write(bp, phy,
9175                                          MDIO_PMA_DEVAD,
9176                                          MDIO_PMA_REG_PHY_IDENTIFIER, val1);
9177                         /* Clear RX alarm */
9178                         bnx2x_cl45_read(bp, phy,
9179                                 MDIO_PMA_DEVAD,
9180                                 MDIO_PMA_LASI_RXSTAT, &rx_alarm_status);
9181                         return 0;
9182                 }
9183         } /* Over current check */
9184
9185         /* When module absent bit is set, check module */
9186         if (rx_alarm_status & (1<<5)) {
9187                 bnx2x_8727_handle_mod_abs(phy, params);
9188                 /* Enable all mod_abs and link detection bits */
9189                 bnx2x_cl45_write(bp, phy,
9190                                  MDIO_PMA_DEVAD, MDIO_PMA_LASI_RXCTRL,
9191                                  ((1<<5) | (1<<2)));
9192         }
9193
9194         if (!(phy->flags & FLAGS_SFP_NOT_APPROVED)) {
9195                 DP(NETIF_MSG_LINK, "Enabling 8727 TX laser\n");
9196                 bnx2x_sfp_set_transmitter(params, phy, 1);
9197         } else {
9198                 DP(NETIF_MSG_LINK, "Tx is disabled\n");
9199                 return 0;
9200         }
9201
9202         bnx2x_cl45_read(bp, phy,
9203                         MDIO_PMA_DEVAD,
9204                         MDIO_PMA_REG_8073_SPEED_LINK_STATUS, &link_status);
9205
9206         /* Bits 0..2 --> speed detected,
9207          * Bits 13..15--> link is down
9208          */
9209         if ((link_status & (1<<2)) && (!(link_status & (1<<15)))) {
9210                 link_up = 1;
9211                 vars->line_speed = SPEED_10000;
9212                 DP(NETIF_MSG_LINK, "port %x: External link up in 10G\n",
9213                            params->port);
9214         } else if ((link_status & (1<<0)) && (!(link_status & (1<<13)))) {
9215                 link_up = 1;
9216                 vars->line_speed = SPEED_1000;
9217                 DP(NETIF_MSG_LINK, "port %x: External link up in 1G\n",
9218                            params->port);
9219         } else {
9220                 link_up = 0;
9221                 DP(NETIF_MSG_LINK, "port %x: External link is down\n",
9222                            params->port);
9223         }
9224
9225         /* Capture 10G link fault. */
9226         if (vars->line_speed == SPEED_10000) {
9227                 bnx2x_cl45_read(bp, phy, MDIO_PMA_DEVAD,
9228                             MDIO_PMA_LASI_TXSTAT, &val1);
9229
9230                 bnx2x_cl45_read(bp, phy, MDIO_PMA_DEVAD,
9231                             MDIO_PMA_LASI_TXSTAT, &val1);
9232
9233                 if (val1 & (1<<0)) {
9234                         vars->fault_detected = 1;
9235                 }
9236         }
9237
9238         if (link_up) {
9239                 bnx2x_ext_phy_resolve_fc(phy, params, vars);
9240                 vars->duplex = DUPLEX_FULL;
9241                 DP(NETIF_MSG_LINK, "duplex = 0x%x\n", vars->duplex);
9242         }
9243
9244         if ((DUAL_MEDIA(params)) &&
9245             (phy->req_line_speed == SPEED_1000)) {
9246                 bnx2x_cl45_read(bp, phy,
9247                                 MDIO_PMA_DEVAD,
9248                                 MDIO_PMA_REG_8727_PCS_GP, &val1);
9249                 /* In case of dual-media board and 1G, power up the XAUI side,
9250                  * otherwise power it down. For 10G it is done automatically
9251                  */
9252                 if (link_up)
9253                         val1 &= ~(3<<10);
9254                 else
9255                         val1 |= (3<<10);
9256                 bnx2x_cl45_write(bp, phy,
9257                                  MDIO_PMA_DEVAD,
9258                                  MDIO_PMA_REG_8727_PCS_GP, val1);
9259         }
9260         return link_up;
9261 }
9262
9263 static void bnx2x_8727_link_reset(struct bnx2x_phy *phy,
9264                                   struct link_params *params)
9265 {
9266         struct bnx2x *bp = params->bp;
9267
9268         /* Enable/Disable PHY transmitter output */
9269         bnx2x_set_disable_pmd_transmit(params, phy, 1);
9270
9271         /* Disable Transmitter */
9272         bnx2x_sfp_set_transmitter(params, phy, 0);
9273         /* Clear LASI */
9274         bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, MDIO_PMA_LASI_CTRL, 0);
9275
9276 }
9277
9278 /******************************************************************/
9279 /*              BCM8481/BCM84823/BCM84833 PHY SECTION             */
9280 /******************************************************************/
9281 static void bnx2x_save_848xx_spirom_version(struct bnx2x_phy *phy,
9282                                             struct bnx2x *bp,
9283                                             u8 port)
9284 {
9285         u16 val, fw_ver1, fw_ver2, cnt;
9286
9287         if (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84833) {
9288                 bnx2x_cl45_read(bp, phy, MDIO_CTL_DEVAD, 0x400f, &fw_ver1);
9289                 bnx2x_save_spirom_version(bp, port, fw_ver1 & 0xfff,
9290                                 phy->ver_addr);
9291         } else {
9292                 /* For 32-bit registers in 848xx, access via MDIO2ARM i/f. */
9293                 /* (1) set reg 0xc200_0014(SPI_BRIDGE_CTRL_2) to 0x03000000 */
9294                 bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, 0xA819, 0x0014);
9295                 bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, 0xA81A, 0xc200);
9296                 bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, 0xA81B, 0x0000);
9297                 bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, 0xA81C, 0x0300);
9298                 bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, 0xA817, 0x0009);
9299
9300                 for (cnt = 0; cnt < 100; cnt++) {
9301                         bnx2x_cl45_read(bp, phy, MDIO_PMA_DEVAD, 0xA818, &val);
9302                         if (val & 1)
9303                                 break;
9304                         udelay(5);
9305                 }
9306                 if (cnt == 100) {
9307                         DP(NETIF_MSG_LINK, "Unable to read 848xx "
9308                                         "phy fw version(1)\n");
9309                         bnx2x_save_spirom_version(bp, port, 0,
9310                                                   phy->ver_addr);
9311                         return;
9312                 }
9313
9314
9315                 /* 2) read register 0xc200_0000 (SPI_FW_STATUS) */
9316                 bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, 0xA819, 0x0000);
9317                 bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, 0xA81A, 0xc200);
9318                 bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, 0xA817, 0x000A);
9319                 for (cnt = 0; cnt < 100; cnt++) {
9320                         bnx2x_cl45_read(bp, phy, MDIO_PMA_DEVAD, 0xA818, &val);
9321                         if (val & 1)
9322                                 break;
9323                         udelay(5);
9324                 }
9325                 if (cnt == 100) {
9326                         DP(NETIF_MSG_LINK, "Unable to read 848xx phy fw "
9327                                         "version(2)\n");
9328                         bnx2x_save_spirom_version(bp, port, 0,
9329                                                   phy->ver_addr);
9330                         return;
9331                 }
9332
9333                 /* lower 16 bits of the register SPI_FW_STATUS */
9334                 bnx2x_cl45_read(bp, phy, MDIO_PMA_DEVAD, 0xA81B, &fw_ver1);
9335                 /* upper 16 bits of register SPI_FW_STATUS */
9336                 bnx2x_cl45_read(bp, phy, MDIO_PMA_DEVAD, 0xA81C, &fw_ver2);
9337
9338                 bnx2x_save_spirom_version(bp, port, (fw_ver2<<16) | fw_ver1,
9339                                           phy->ver_addr);
9340         }
9341
9342 }
9343 static void bnx2x_848xx_set_led(struct bnx2x *bp,
9344                                 struct bnx2x_phy *phy)
9345 {
9346         u16 val, offset;
9347
9348         /* PHYC_CTL_LED_CTL */
9349         bnx2x_cl45_read(bp, phy,
9350                         MDIO_PMA_DEVAD,
9351                         MDIO_PMA_REG_8481_LINK_SIGNAL, &val);
9352         val &= 0xFE00;
9353         val |= 0x0092;
9354
9355         bnx2x_cl45_write(bp, phy,
9356                          MDIO_PMA_DEVAD,
9357                          MDIO_PMA_REG_8481_LINK_SIGNAL, val);
9358
9359         bnx2x_cl45_write(bp, phy,
9360                          MDIO_PMA_DEVAD,
9361                          MDIO_PMA_REG_8481_LED1_MASK,
9362                          0x80);
9363
9364         bnx2x_cl45_write(bp, phy,
9365                          MDIO_PMA_DEVAD,
9366                          MDIO_PMA_REG_8481_LED2_MASK,
9367                          0x18);
9368
9369         /* Select activity source by Tx and Rx, as suggested by PHY AE */
9370         bnx2x_cl45_write(bp, phy,
9371                          MDIO_PMA_DEVAD,
9372                          MDIO_PMA_REG_8481_LED3_MASK,
9373                          0x0006);
9374
9375         /* Select the closest activity blink rate to that in 10/100/1000 */
9376         bnx2x_cl45_write(bp, phy,
9377                         MDIO_PMA_DEVAD,
9378                         MDIO_PMA_REG_8481_LED3_BLINK,
9379                         0);
9380
9381         /* Configure the blink rate to ~15.9 Hz */
9382         bnx2x_cl45_write(bp, phy,
9383                         MDIO_PMA_DEVAD,
9384                         MDIO_PMA_REG_84823_CTL_SLOW_CLK_CNT_HIGH,
9385                         MDIO_PMA_REG_84823_BLINK_RATE_VAL_15P9HZ);
9386
9387         if (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84833)
9388                 offset = MDIO_PMA_REG_84833_CTL_LED_CTL_1;
9389         else
9390                 offset = MDIO_PMA_REG_84823_CTL_LED_CTL_1;
9391
9392         bnx2x_cl45_read(bp, phy,
9393                         MDIO_PMA_DEVAD, offset, &val);
9394         val |= MDIO_PMA_REG_84823_LED3_STRETCH_EN; /* stretch_en for LED3*/
9395         bnx2x_cl45_write(bp, phy,
9396                          MDIO_PMA_DEVAD, offset, val);
9397
9398         /* 'Interrupt Mask' */
9399         bnx2x_cl45_write(bp, phy,
9400                          MDIO_AN_DEVAD,
9401                          0xFFFB, 0xFFFD);
9402 }
9403
9404 static int bnx2x_848xx_cmn_config_init(struct bnx2x_phy *phy,
9405                                        struct link_params *params,
9406                                        struct link_vars *vars)
9407 {
9408         struct bnx2x *bp = params->bp;
9409         u16 autoneg_val, an_1000_val, an_10_100_val, an_10g_val;
9410
9411         if (phy->type != PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84833) {
9412                 /* Save spirom version */
9413                 bnx2x_save_848xx_spirom_version(phy, bp, params->port);
9414         }
9415         /* This phy uses the NIG latch mechanism since link indication
9416          * arrives through its LED4 and not via its LASI signal, so we
9417          * get steady signal instead of clear on read
9418          */
9419         bnx2x_bits_en(bp, NIG_REG_LATCH_BC_0 + params->port*4,
9420                       1 << NIG_LATCH_BC_ENABLE_MI_INT);
9421
9422         bnx2x_cl45_write(bp, phy,
9423                          MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 0x0000);
9424
9425         bnx2x_848xx_set_led(bp, phy);
9426
9427         /* set 1000 speed advertisement */
9428         bnx2x_cl45_read(bp, phy,
9429                         MDIO_AN_DEVAD, MDIO_AN_REG_8481_1000T_CTRL,
9430                         &an_1000_val);
9431
9432         bnx2x_ext_phy_set_pause(params, phy, vars);
9433         bnx2x_cl45_read(bp, phy,
9434                         MDIO_AN_DEVAD,
9435                         MDIO_AN_REG_8481_LEGACY_AN_ADV,
9436                         &an_10_100_val);
9437         bnx2x_cl45_read(bp, phy,
9438                         MDIO_AN_DEVAD, MDIO_AN_REG_8481_LEGACY_MII_CTRL,
9439                         &autoneg_val);
9440         /* Disable forced speed */
9441         autoneg_val &= ~((1<<6) | (1<<8) | (1<<9) | (1<<12) | (1<<13));
9442         an_10_100_val &= ~((1<<5) | (1<<6) | (1<<7) | (1<<8));
9443
9444         if (((phy->req_line_speed == SPEED_AUTO_NEG) &&
9445              (phy->speed_cap_mask &
9446              PORT_HW_CFG_SPEED_CAPABILITY_D0_1G)) ||
9447             (phy->req_line_speed == SPEED_1000)) {
9448                 an_1000_val |= (1<<8);
9449                 autoneg_val |= (1<<9 | 1<<12);
9450                 if (phy->req_duplex == DUPLEX_FULL)
9451                         an_1000_val |= (1<<9);
9452                 DP(NETIF_MSG_LINK, "Advertising 1G\n");
9453         } else
9454                 an_1000_val &= ~((1<<8) | (1<<9));
9455
9456         bnx2x_cl45_write(bp, phy,
9457                          MDIO_AN_DEVAD, MDIO_AN_REG_8481_1000T_CTRL,
9458                          an_1000_val);
9459
9460         /* set 100 speed advertisement */
9461         if ((phy->req_line_speed == SPEED_AUTO_NEG) &&
9462              (phy->speed_cap_mask &
9463               (PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_FULL |
9464                PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_HALF))) {
9465                 an_10_100_val |= (1<<7);
9466                 /* Enable autoneg and restart autoneg for legacy speeds */
9467                 autoneg_val |= (1<<9 | 1<<12);
9468
9469                 if (phy->req_duplex == DUPLEX_FULL)
9470                         an_10_100_val |= (1<<8);
9471                 DP(NETIF_MSG_LINK, "Advertising 100M\n");
9472         }
9473         /* set 10 speed advertisement */
9474         if (((phy->req_line_speed == SPEED_AUTO_NEG) &&
9475              (phy->speed_cap_mask &
9476               (PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_FULL |
9477                PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_HALF)) &&
9478              (phy->supported &
9479               (SUPPORTED_10baseT_Half |
9480                SUPPORTED_10baseT_Full)))) {
9481                 an_10_100_val |= (1<<5);
9482                 autoneg_val |= (1<<9 | 1<<12);
9483                 if (phy->req_duplex == DUPLEX_FULL)
9484                         an_10_100_val |= (1<<6);
9485                 DP(NETIF_MSG_LINK, "Advertising 10M\n");
9486         }
9487
9488         /* Only 10/100 are allowed to work in FORCE mode */
9489         if ((phy->req_line_speed == SPEED_100) &&
9490             (phy->supported &
9491              (SUPPORTED_100baseT_Half |
9492               SUPPORTED_100baseT_Full))) {
9493                 autoneg_val |= (1<<13);
9494                 /* Enabled AUTO-MDIX when autoneg is disabled */
9495                 bnx2x_cl45_write(bp, phy,
9496                                  MDIO_AN_DEVAD, MDIO_AN_REG_8481_AUX_CTRL,
9497                                  (1<<15 | 1<<9 | 7<<0));
9498                 /* The PHY needs this set even for forced link. */
9499                 an_10_100_val |= (1<<8) | (1<<7);
9500                 DP(NETIF_MSG_LINK, "Setting 100M force\n");
9501         }
9502         if ((phy->req_line_speed == SPEED_10) &&
9503             (phy->supported &
9504              (SUPPORTED_10baseT_Half |
9505               SUPPORTED_10baseT_Full))) {
9506                 /* Enabled AUTO-MDIX when autoneg is disabled */
9507                 bnx2x_cl45_write(bp, phy,
9508                                  MDIO_AN_DEVAD, MDIO_AN_REG_8481_AUX_CTRL,
9509                                  (1<<15 | 1<<9 | 7<<0));
9510                 DP(NETIF_MSG_LINK, "Setting 10M force\n");
9511         }
9512
9513         bnx2x_cl45_write(bp, phy,
9514                          MDIO_AN_DEVAD, MDIO_AN_REG_8481_LEGACY_AN_ADV,
9515                          an_10_100_val);
9516
9517         if (phy->req_duplex == DUPLEX_FULL)
9518                 autoneg_val |= (1<<8);
9519
9520         /* Always write this if this is not 84833.
9521          * For 84833, write it only when it's a forced speed.
9522          */
9523         if ((phy->type != PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84833) ||
9524                 ((autoneg_val & (1<<12)) == 0))
9525                 bnx2x_cl45_write(bp, phy,
9526                          MDIO_AN_DEVAD,
9527                          MDIO_AN_REG_8481_LEGACY_MII_CTRL, autoneg_val);
9528
9529         if (((phy->req_line_speed == SPEED_AUTO_NEG) &&
9530             (phy->speed_cap_mask &
9531              PORT_HW_CFG_SPEED_CAPABILITY_D0_10G)) ||
9532                 (phy->req_line_speed == SPEED_10000)) {
9533                         DP(NETIF_MSG_LINK, "Advertising 10G\n");
9534                         /* Restart autoneg for 10G*/
9535
9536                         bnx2x_cl45_read(bp, phy,
9537                                         MDIO_AN_DEVAD,
9538                                         MDIO_AN_REG_8481_10GBASE_T_AN_CTRL,
9539                                         &an_10g_val);
9540                         bnx2x_cl45_write(bp, phy,
9541                                          MDIO_AN_DEVAD,
9542                                          MDIO_AN_REG_8481_10GBASE_T_AN_CTRL,
9543                                          an_10g_val | 0x1000);
9544                         bnx2x_cl45_write(bp, phy,
9545                                          MDIO_AN_DEVAD, MDIO_AN_REG_CTRL,
9546                                          0x3200);
9547         } else
9548                 bnx2x_cl45_write(bp, phy,
9549                                  MDIO_AN_DEVAD,
9550                                  MDIO_AN_REG_8481_10GBASE_T_AN_CTRL,
9551                                  1);
9552
9553         return 0;
9554 }
9555
9556 static int bnx2x_8481_config_init(struct bnx2x_phy *phy,
9557                                   struct link_params *params,
9558                                   struct link_vars *vars)
9559 {
9560         struct bnx2x *bp = params->bp;
9561         /* Restore normal power mode*/
9562         bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_2,
9563                        MISC_REGISTERS_GPIO_OUTPUT_HIGH, params->port);
9564
9565         /* HW reset */
9566         bnx2x_ext_phy_hw_reset(bp, params->port);
9567         bnx2x_wait_reset_complete(bp, phy, params);
9568
9569         bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 1<<15);
9570         return bnx2x_848xx_cmn_config_init(phy, params, vars);
9571 }
9572
9573 #define PHY84833_CMDHDLR_WAIT 300
9574 #define PHY84833_CMDHDLR_MAX_ARGS 5
9575 static int bnx2x_84833_cmd_hdlr(struct bnx2x_phy *phy,
9576                                    struct link_params *params,
9577                    u16 fw_cmd,
9578                    u16 cmd_args[])
9579 {
9580         u32 idx;
9581         u16 val;
9582         struct bnx2x *bp = params->bp;
9583         /* Write CMD_OPEN_OVERRIDE to STATUS reg */
9584         bnx2x_cl45_write(bp, phy, MDIO_CTL_DEVAD,
9585                         MDIO_84833_CMD_HDLR_STATUS,
9586                         PHY84833_STATUS_CMD_OPEN_OVERRIDE);
9587         for (idx = 0; idx < PHY84833_CMDHDLR_WAIT; idx++) {
9588                 bnx2x_cl45_read(bp, phy, MDIO_CTL_DEVAD,
9589                                 MDIO_84833_CMD_HDLR_STATUS, &val);
9590                 if (val == PHY84833_STATUS_CMD_OPEN_FOR_CMDS)
9591                         break;
9592                 msleep(1);
9593         }
9594         if (idx >= PHY84833_CMDHDLR_WAIT) {
9595                 DP(NETIF_MSG_LINK, "FW cmd: FW not ready.\n");
9596                 return -EINVAL;
9597         }
9598
9599         /* Prepare argument(s) and issue command */
9600         for (idx = 0; idx < PHY84833_CMDHDLR_MAX_ARGS; idx++) {
9601                 bnx2x_cl45_write(bp, phy, MDIO_CTL_DEVAD,
9602                                 MDIO_84833_CMD_HDLR_DATA1 + idx,
9603                                 cmd_args[idx]);
9604         }
9605         bnx2x_cl45_write(bp, phy, MDIO_CTL_DEVAD,
9606                         MDIO_84833_CMD_HDLR_COMMAND, fw_cmd);
9607         for (idx = 0; idx < PHY84833_CMDHDLR_WAIT; idx++) {
9608                 bnx2x_cl45_read(bp, phy, MDIO_CTL_DEVAD,
9609                                 MDIO_84833_CMD_HDLR_STATUS, &val);
9610                 if ((val == PHY84833_STATUS_CMD_COMPLETE_PASS) ||
9611                         (val == PHY84833_STATUS_CMD_COMPLETE_ERROR))
9612                         break;
9613                 msleep(1);
9614         }
9615         if ((idx >= PHY84833_CMDHDLR_WAIT) ||
9616                 (val == PHY84833_STATUS_CMD_COMPLETE_ERROR)) {
9617                 DP(NETIF_MSG_LINK, "FW cmd failed.\n");
9618                 return -EINVAL;
9619         }
9620         /* Gather returning data */
9621         for (idx = 0; idx < PHY84833_CMDHDLR_MAX_ARGS; idx++) {
9622                 bnx2x_cl45_read(bp, phy, MDIO_CTL_DEVAD,
9623                                 MDIO_84833_CMD_HDLR_DATA1 + idx,
9624                                 &cmd_args[idx]);
9625         }
9626         bnx2x_cl45_write(bp, phy, MDIO_CTL_DEVAD,
9627                         MDIO_84833_CMD_HDLR_STATUS,
9628                         PHY84833_STATUS_CMD_CLEAR_COMPLETE);
9629         return 0;
9630 }
9631
9632
9633 static int bnx2x_84833_pair_swap_cfg(struct bnx2x_phy *phy,
9634                                    struct link_params *params,
9635                                    struct link_vars *vars)
9636 {
9637         u32 pair_swap;
9638         u16 data[PHY84833_CMDHDLR_MAX_ARGS];
9639         int status;
9640         struct bnx2x *bp = params->bp;
9641
9642         /* Check for configuration. */
9643         pair_swap = REG_RD(bp, params->shmem_base +
9644                            offsetof(struct shmem_region,
9645                         dev_info.port_hw_config[params->port].xgbt_phy_cfg)) &
9646                 PORT_HW_CFG_RJ45_PAIR_SWAP_MASK;
9647
9648         if (pair_swap == 0)
9649                 return 0;
9650
9651         /* Only the second argument is used for this command */
9652         data[1] = (u16)pair_swap;
9653
9654         status = bnx2x_84833_cmd_hdlr(phy, params,
9655                 PHY84833_CMD_SET_PAIR_SWAP, data);
9656         if (status == 0)
9657                 DP(NETIF_MSG_LINK, "Pairswap OK, val=0x%x\n", data[1]);
9658
9659         return status;
9660 }
9661
9662 static u8 bnx2x_84833_get_reset_gpios(struct bnx2x *bp,
9663                                       u32 shmem_base_path[],
9664                                       u32 chip_id)
9665 {
9666         u32 reset_pin[2];
9667         u32 idx;
9668         u8 reset_gpios;
9669         if (CHIP_IS_E3(bp)) {
9670                 /* Assume that these will be GPIOs, not EPIOs. */
9671                 for (idx = 0; idx < 2; idx++) {
9672                         /* Map config param to register bit. */
9673                         reset_pin[idx] = REG_RD(bp, shmem_base_path[idx] +
9674                                 offsetof(struct shmem_region,
9675                                 dev_info.port_hw_config[0].e3_cmn_pin_cfg));
9676                         reset_pin[idx] = (reset_pin[idx] &
9677                                 PORT_HW_CFG_E3_PHY_RESET_MASK) >>
9678                                 PORT_HW_CFG_E3_PHY_RESET_SHIFT;
9679                         reset_pin[idx] -= PIN_CFG_GPIO0_P0;
9680                         reset_pin[idx] = (1 << reset_pin[idx]);
9681                 }
9682                 reset_gpios = (u8)(reset_pin[0] | reset_pin[1]);
9683         } else {
9684                 /* E2, look from diff place of shmem. */
9685                 for (idx = 0; idx < 2; idx++) {
9686                         reset_pin[idx] = REG_RD(bp, shmem_base_path[idx] +
9687                                 offsetof(struct shmem_region,
9688                                 dev_info.port_hw_config[0].default_cfg));
9689                         reset_pin[idx] &= PORT_HW_CFG_EXT_PHY_GPIO_RST_MASK;
9690                         reset_pin[idx] -= PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO0_P0;
9691                         reset_pin[idx] >>= PORT_HW_CFG_EXT_PHY_GPIO_RST_SHIFT;
9692                         reset_pin[idx] = (1 << reset_pin[idx]);
9693                 }
9694                 reset_gpios = (u8)(reset_pin[0] | reset_pin[1]);
9695         }
9696
9697         return reset_gpios;
9698 }
9699
9700 static int bnx2x_84833_hw_reset_phy(struct bnx2x_phy *phy,
9701                                 struct link_params *params)
9702 {
9703         struct bnx2x *bp = params->bp;
9704         u8 reset_gpios;
9705         u32 other_shmem_base_addr = REG_RD(bp, params->shmem2_base +
9706                                 offsetof(struct shmem2_region,
9707                                 other_shmem_base_addr));
9708
9709         u32 shmem_base_path[2];
9710
9711         /* Work around for 84833 LED failure inside RESET status */
9712         bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD,
9713                 MDIO_AN_REG_8481_LEGACY_MII_CTRL,
9714                 MDIO_AN_REG_8481_MII_CTRL_FORCE_1G);
9715         bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD,
9716                 MDIO_AN_REG_8481_1G_100T_EXT_CTRL,
9717                 MIDO_AN_REG_8481_EXT_CTRL_FORCE_LEDS_OFF);
9718
9719         shmem_base_path[0] = params->shmem_base;
9720         shmem_base_path[1] = other_shmem_base_addr;
9721
9722         reset_gpios = bnx2x_84833_get_reset_gpios(bp, shmem_base_path,
9723                                                   params->chip_id);
9724
9725         bnx2x_set_mult_gpio(bp, reset_gpios, MISC_REGISTERS_GPIO_OUTPUT_LOW);
9726         udelay(10);
9727         DP(NETIF_MSG_LINK, "84833 hw reset on pin values 0x%x\n",
9728                 reset_gpios);
9729
9730         return 0;
9731 }
9732
9733 #define PHY84833_CONSTANT_LATENCY 1193
9734 static int bnx2x_848x3_config_init(struct bnx2x_phy *phy,
9735                                    struct link_params *params,
9736                                    struct link_vars *vars)
9737 {
9738         struct bnx2x *bp = params->bp;
9739         u8 port, initialize = 1;
9740         u16 val;
9741         u32 actual_phy_selection, cms_enable;
9742         u16 cmd_args[PHY84833_CMDHDLR_MAX_ARGS];
9743         int rc = 0;
9744
9745         msleep(1);
9746
9747         if (!(CHIP_IS_E1(bp)))
9748                 port = BP_PATH(bp);
9749         else
9750                 port = params->port;
9751
9752         if (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84823) {
9753                 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_3,
9754                                MISC_REGISTERS_GPIO_OUTPUT_HIGH,
9755                                port);
9756         } else {
9757                 /* MDIO reset */
9758                 bnx2x_cl45_write(bp, phy,
9759                                 MDIO_PMA_DEVAD,
9760                                 MDIO_PMA_REG_CTRL, 0x8000);
9761         }
9762
9763         bnx2x_wait_reset_complete(bp, phy, params);
9764
9765         /* Wait for GPHY to come out of reset */
9766         msleep(50);
9767         if (phy->type != PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84833) {
9768                 /* BCM84823 requires that XGXS links up first @ 10G for normal
9769                  * behavior.
9770                  */
9771                 u16 temp;
9772                 temp = vars->line_speed;
9773                 vars->line_speed = SPEED_10000;
9774                 bnx2x_set_autoneg(&params->phy[INT_PHY], params, vars, 0);
9775                 bnx2x_program_serdes(&params->phy[INT_PHY], params, vars);
9776                 vars->line_speed = temp;
9777         }
9778
9779         bnx2x_cl45_read(bp, phy, MDIO_CTL_DEVAD,
9780                         MDIO_CTL_REG_84823_MEDIA, &val);
9781         val &= ~(MDIO_CTL_REG_84823_MEDIA_MAC_MASK |
9782                  MDIO_CTL_REG_84823_MEDIA_LINE_MASK |
9783                  MDIO_CTL_REG_84823_MEDIA_COPPER_CORE_DOWN |
9784                  MDIO_CTL_REG_84823_MEDIA_PRIORITY_MASK |
9785                  MDIO_CTL_REG_84823_MEDIA_FIBER_1G);
9786
9787         if (CHIP_IS_E3(bp)) {
9788                 val &= ~(MDIO_CTL_REG_84823_MEDIA_MAC_MASK |
9789                          MDIO_CTL_REG_84823_MEDIA_LINE_MASK);
9790         } else {
9791                 val |= (MDIO_CTL_REG_84823_CTRL_MAC_XFI |
9792                         MDIO_CTL_REG_84823_MEDIA_LINE_XAUI_L);
9793         }
9794
9795         actual_phy_selection = bnx2x_phy_selection(params);
9796
9797         switch (actual_phy_selection) {
9798         case PORT_HW_CFG_PHY_SELECTION_HARDWARE_DEFAULT:
9799                 /* Do nothing. Essentially this is like the priority copper */
9800                 break;
9801         case PORT_HW_CFG_PHY_SELECTION_FIRST_PHY_PRIORITY:
9802                 val |= MDIO_CTL_REG_84823_MEDIA_PRIORITY_COPPER;
9803                 break;
9804         case PORT_HW_CFG_PHY_SELECTION_SECOND_PHY_PRIORITY:
9805                 val |= MDIO_CTL_REG_84823_MEDIA_PRIORITY_FIBER;
9806                 break;
9807         case PORT_HW_CFG_PHY_SELECTION_FIRST_PHY:
9808                 /* Do nothing here. The first PHY won't be initialized at all */
9809                 break;
9810         case PORT_HW_CFG_PHY_SELECTION_SECOND_PHY:
9811                 val |= MDIO_CTL_REG_84823_MEDIA_COPPER_CORE_DOWN;
9812                 initialize = 0;
9813                 break;
9814         }
9815         if (params->phy[EXT_PHY2].req_line_speed == SPEED_1000)
9816                 val |= MDIO_CTL_REG_84823_MEDIA_FIBER_1G;
9817
9818         bnx2x_cl45_write(bp, phy, MDIO_CTL_DEVAD,
9819                          MDIO_CTL_REG_84823_MEDIA, val);
9820         DP(NETIF_MSG_LINK, "Multi_phy config = 0x%x, Media control = 0x%x\n",
9821                    params->multi_phy_config, val);
9822
9823         if (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84833) {
9824                 bnx2x_84833_pair_swap_cfg(phy, params, vars);
9825
9826                 /* Keep AutogrEEEn disabled. */
9827                 cmd_args[0] = 0x0;
9828                 cmd_args[1] = 0x0;
9829                 cmd_args[2] = PHY84833_CONSTANT_LATENCY + 1;
9830                 cmd_args[3] = PHY84833_CONSTANT_LATENCY;
9831                 rc = bnx2x_84833_cmd_hdlr(phy, params,
9832                         PHY84833_CMD_SET_EEE_MODE, cmd_args);
9833                 if (rc != 0)
9834                         DP(NETIF_MSG_LINK, "Cfg AutogrEEEn failed.\n");
9835         }
9836         if (initialize)
9837                 rc = bnx2x_848xx_cmn_config_init(phy, params, vars);
9838         else
9839                 bnx2x_save_848xx_spirom_version(phy, bp, params->port);
9840         /* 84833 PHY has a better feature and doesn't need to support this. */
9841         if (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84823) {
9842                 cms_enable = REG_RD(bp, params->shmem_base +
9843                         offsetof(struct shmem_region,
9844                         dev_info.port_hw_config[params->port].default_cfg)) &
9845                         PORT_HW_CFG_ENABLE_CMS_MASK;
9846
9847                 bnx2x_cl45_read(bp, phy, MDIO_CTL_DEVAD,
9848                                 MDIO_CTL_REG_84823_USER_CTRL_REG, &val);
9849                 if (cms_enable)
9850                         val |= MDIO_CTL_REG_84823_USER_CTRL_CMS;
9851                 else
9852                         val &= ~MDIO_CTL_REG_84823_USER_CTRL_CMS;
9853                 bnx2x_cl45_write(bp, phy, MDIO_CTL_DEVAD,
9854                                  MDIO_CTL_REG_84823_USER_CTRL_REG, val);
9855         }
9856
9857         if (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84833) {
9858                 /* Bring PHY out of super isolate mode as the final step. */
9859                 bnx2x_cl45_read(bp, phy,
9860                                 MDIO_CTL_DEVAD,
9861                                 MDIO_84833_TOP_CFG_XGPHY_STRAP1, &val);
9862                 val &= ~MDIO_84833_SUPER_ISOLATE;
9863                 bnx2x_cl45_write(bp, phy,
9864                                 MDIO_CTL_DEVAD,
9865                                 MDIO_84833_TOP_CFG_XGPHY_STRAP1, val);
9866         }
9867         return rc;
9868 }
9869
9870 static u8 bnx2x_848xx_read_status(struct bnx2x_phy *phy,
9871                                   struct link_params *params,
9872                                   struct link_vars *vars)
9873 {
9874         struct bnx2x *bp = params->bp;
9875         u16 val, val1, val2;
9876         u8 link_up = 0;
9877
9878
9879         /* Check 10G-BaseT link status */
9880         /* Check PMD signal ok */
9881         bnx2x_cl45_read(bp, phy,
9882                         MDIO_AN_DEVAD, 0xFFFA, &val1);
9883         bnx2x_cl45_read(bp, phy,
9884                         MDIO_PMA_DEVAD, MDIO_PMA_REG_8481_PMD_SIGNAL,
9885                         &val2);
9886         DP(NETIF_MSG_LINK, "BCM848xx: PMD_SIGNAL 1.a811 = 0x%x\n", val2);
9887
9888         /* Check link 10G */
9889         if (val2 & (1<<11)) {
9890                 vars->line_speed = SPEED_10000;
9891                 vars->duplex = DUPLEX_FULL;
9892                 link_up = 1;
9893                 bnx2x_ext_phy_10G_an_resolve(bp, phy, vars);
9894         } else { /* Check Legacy speed link */
9895                 u16 legacy_status, legacy_speed;
9896
9897                 /* Enable expansion register 0x42 (Operation mode status) */
9898                 bnx2x_cl45_write(bp, phy,
9899                                  MDIO_AN_DEVAD,
9900                                  MDIO_AN_REG_8481_EXPANSION_REG_ACCESS, 0xf42);
9901
9902                 /* Get legacy speed operation status */
9903                 bnx2x_cl45_read(bp, phy,
9904                                 MDIO_AN_DEVAD,
9905                                 MDIO_AN_REG_8481_EXPANSION_REG_RD_RW,
9906                                 &legacy_status);
9907
9908                 DP(NETIF_MSG_LINK, "Legacy speed status = 0x%x\n",
9909                    legacy_status);
9910                 link_up = ((legacy_status & (1<<11)) == (1<<11));
9911                 if (link_up) {
9912                         legacy_speed = (legacy_status & (3<<9));
9913                         if (legacy_speed == (0<<9))
9914                                 vars->line_speed = SPEED_10;
9915                         else if (legacy_speed == (1<<9))
9916                                 vars->line_speed = SPEED_100;
9917                         else if (legacy_speed == (2<<9))
9918                                 vars->line_speed = SPEED_1000;
9919                         else /* Should not happen */
9920                                 vars->line_speed = 0;
9921
9922                         if (legacy_status & (1<<8))
9923                                 vars->duplex = DUPLEX_FULL;
9924                         else
9925                                 vars->duplex = DUPLEX_HALF;
9926
9927                         DP(NETIF_MSG_LINK,
9928                            "Link is up in %dMbps, is_duplex_full= %d\n",
9929                            vars->line_speed,
9930                            (vars->duplex == DUPLEX_FULL));
9931                         /* Check legacy speed AN resolution */
9932                         bnx2x_cl45_read(bp, phy,
9933                                         MDIO_AN_DEVAD,
9934                                         MDIO_AN_REG_8481_LEGACY_MII_STATUS,
9935                                         &val);
9936                         if (val & (1<<5))
9937                                 vars->link_status |=
9938                                         LINK_STATUS_AUTO_NEGOTIATE_COMPLETE;
9939                         bnx2x_cl45_read(bp, phy,
9940                                         MDIO_AN_DEVAD,
9941                                         MDIO_AN_REG_8481_LEGACY_AN_EXPANSION,
9942                                         &val);
9943                         if ((val & (1<<0)) == 0)
9944                                 vars->link_status |=
9945                                         LINK_STATUS_PARALLEL_DETECTION_USED;
9946                 }
9947         }
9948         if (link_up) {
9949                 DP(NETIF_MSG_LINK, "BCM84823: link speed is %d\n",
9950                            vars->line_speed);
9951                 bnx2x_ext_phy_resolve_fc(phy, params, vars);
9952
9953                 /* Read LP advertised speeds */
9954                 bnx2x_cl45_read(bp, phy, MDIO_AN_DEVAD,
9955                                 MDIO_AN_REG_CL37_FC_LP, &val);
9956                 if (val & (1<<5))
9957                         vars->link_status |=
9958                                 LINK_STATUS_LINK_PARTNER_10THD_CAPABLE;
9959                 if (val & (1<<6))
9960                         vars->link_status |=
9961                                 LINK_STATUS_LINK_PARTNER_10TFD_CAPABLE;
9962                 if (val & (1<<7))
9963                         vars->link_status |=
9964                                 LINK_STATUS_LINK_PARTNER_100TXHD_CAPABLE;
9965                 if (val & (1<<8))
9966                         vars->link_status |=
9967                                 LINK_STATUS_LINK_PARTNER_100TXFD_CAPABLE;
9968                 if (val & (1<<9))
9969                         vars->link_status |=
9970                                 LINK_STATUS_LINK_PARTNER_100T4_CAPABLE;
9971
9972                 bnx2x_cl45_read(bp, phy, MDIO_AN_DEVAD,
9973                                 MDIO_AN_REG_1000T_STATUS, &val);
9974
9975                 if (val & (1<<10))
9976                         vars->link_status |=
9977                                 LINK_STATUS_LINK_PARTNER_1000THD_CAPABLE;
9978                 if (val & (1<<11))
9979                         vars->link_status |=
9980                                 LINK_STATUS_LINK_PARTNER_1000TFD_CAPABLE;
9981
9982                 bnx2x_cl45_read(bp, phy, MDIO_AN_DEVAD,
9983                                 MDIO_AN_REG_MASTER_STATUS, &val);
9984
9985                 if (val & (1<<11))
9986                         vars->link_status |=
9987                                 LINK_STATUS_LINK_PARTNER_10GXFD_CAPABLE;
9988         }
9989
9990         return link_up;
9991 }
9992
9993
9994 static int bnx2x_848xx_format_ver(u32 raw_ver, u8 *str, u16 *len)
9995 {
9996         int status = 0;
9997         u32 spirom_ver;
9998         spirom_ver = ((raw_ver & 0xF80) >> 7) << 16 | (raw_ver & 0x7F);
9999         status = bnx2x_format_ver(spirom_ver, str, len);
10000         return status;
10001 }
10002
10003 static void bnx2x_8481_hw_reset(struct bnx2x_phy *phy,
10004                                 struct link_params *params)
10005 {
10006         bnx2x_set_gpio(params->bp, MISC_REGISTERS_GPIO_1,
10007                        MISC_REGISTERS_GPIO_OUTPUT_LOW, 0);
10008         bnx2x_set_gpio(params->bp, MISC_REGISTERS_GPIO_1,
10009                        MISC_REGISTERS_GPIO_OUTPUT_LOW, 1);
10010 }
10011
10012 static void bnx2x_8481_link_reset(struct bnx2x_phy *phy,
10013                                         struct link_params *params)
10014 {
10015         bnx2x_cl45_write(params->bp, phy,
10016                          MDIO_AN_DEVAD, MDIO_AN_REG_CTRL, 0x0000);
10017         bnx2x_cl45_write(params->bp, phy,
10018                          MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 1);
10019 }
10020
10021 static void bnx2x_848x3_link_reset(struct bnx2x_phy *phy,
10022                                    struct link_params *params)
10023 {
10024         struct bnx2x *bp = params->bp;
10025         u8 port;
10026         u16 val16;
10027
10028         if (!(CHIP_IS_E1x(bp)))
10029                 port = BP_PATH(bp);
10030         else
10031                 port = params->port;
10032
10033         if (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84823) {
10034                 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_3,
10035                                MISC_REGISTERS_GPIO_OUTPUT_LOW,
10036                                port);
10037         } else {
10038                 bnx2x_cl45_read(bp, phy,
10039                                 MDIO_CTL_DEVAD,
10040                                 MDIO_84833_TOP_CFG_XGPHY_STRAP1, &val16);
10041                 val16 |= MDIO_84833_SUPER_ISOLATE;
10042                 bnx2x_cl45_write(bp, phy,
10043                                  MDIO_CTL_DEVAD,
10044                                  MDIO_84833_TOP_CFG_XGPHY_STRAP1, val16);
10045         }
10046 }
10047
10048 static void bnx2x_848xx_set_link_led(struct bnx2x_phy *phy,
10049                                      struct link_params *params, u8 mode)
10050 {
10051         struct bnx2x *bp = params->bp;
10052         u16 val;
10053         u8 port;
10054
10055         if (!(CHIP_IS_E1x(bp)))
10056                 port = BP_PATH(bp);
10057         else
10058                 port = params->port;
10059
10060         switch (mode) {
10061         case LED_MODE_OFF:
10062
10063                 DP(NETIF_MSG_LINK, "Port 0x%x: LED MODE OFF\n", port);
10064
10065                 if ((params->hw_led_mode << SHARED_HW_CFG_LED_MODE_SHIFT) ==
10066                     SHARED_HW_CFG_LED_EXTPHY1) {
10067
10068                         /* Set LED masks */
10069                         bnx2x_cl45_write(bp, phy,
10070                                         MDIO_PMA_DEVAD,
10071                                         MDIO_PMA_REG_8481_LED1_MASK,
10072                                         0x0);
10073
10074                         bnx2x_cl45_write(bp, phy,
10075                                         MDIO_PMA_DEVAD,
10076                                         MDIO_PMA_REG_8481_LED2_MASK,
10077                                         0x0);
10078
10079                         bnx2x_cl45_write(bp, phy,
10080                                         MDIO_PMA_DEVAD,
10081                                         MDIO_PMA_REG_8481_LED3_MASK,
10082                                         0x0);
10083
10084                         bnx2x_cl45_write(bp, phy,
10085                                         MDIO_PMA_DEVAD,
10086                                         MDIO_PMA_REG_8481_LED5_MASK,
10087                                         0x0);
10088
10089                 } else {
10090                         bnx2x_cl45_write(bp, phy,
10091                                          MDIO_PMA_DEVAD,
10092                                          MDIO_PMA_REG_8481_LED1_MASK,
10093                                          0x0);
10094                 }
10095                 break;
10096         case LED_MODE_FRONT_PANEL_OFF:
10097
10098                 DP(NETIF_MSG_LINK, "Port 0x%x: LED MODE FRONT PANEL OFF\n",
10099                    port);
10100
10101                 if ((params->hw_led_mode << SHARED_HW_CFG_LED_MODE_SHIFT) ==
10102                     SHARED_HW_CFG_LED_EXTPHY1) {
10103
10104                         /* Set LED masks */
10105                         bnx2x_cl45_write(bp, phy,
10106                                          MDIO_PMA_DEVAD,
10107                                          MDIO_PMA_REG_8481_LED1_MASK,
10108                                          0x0);
10109
10110                         bnx2x_cl45_write(bp, phy,
10111                                          MDIO_PMA_DEVAD,
10112                                          MDIO_PMA_REG_8481_LED2_MASK,
10113                                          0x0);
10114
10115                         bnx2x_cl45_write(bp, phy,
10116                                          MDIO_PMA_DEVAD,
10117                                          MDIO_PMA_REG_8481_LED3_MASK,
10118                                          0x0);
10119
10120                         bnx2x_cl45_write(bp, phy,
10121                                          MDIO_PMA_DEVAD,
10122                                          MDIO_PMA_REG_8481_LED5_MASK,
10123                                          0x20);
10124
10125                 } else {
10126                         bnx2x_cl45_write(bp, phy,
10127                                          MDIO_PMA_DEVAD,
10128                                          MDIO_PMA_REG_8481_LED1_MASK,
10129                                          0x0);
10130                 }
10131                 break;
10132         case LED_MODE_ON:
10133
10134                 DP(NETIF_MSG_LINK, "Port 0x%x: LED MODE ON\n", port);
10135
10136                 if ((params->hw_led_mode << SHARED_HW_CFG_LED_MODE_SHIFT) ==
10137                     SHARED_HW_CFG_LED_EXTPHY1) {
10138                         /* Set control reg */
10139                         bnx2x_cl45_read(bp, phy,
10140                                         MDIO_PMA_DEVAD,
10141                                         MDIO_PMA_REG_8481_LINK_SIGNAL,
10142                                         &val);
10143                         val &= 0x8000;
10144                         val |= 0x2492;
10145
10146                         bnx2x_cl45_write(bp, phy,
10147                                          MDIO_PMA_DEVAD,
10148                                          MDIO_PMA_REG_8481_LINK_SIGNAL,
10149                                          val);
10150
10151                         /* Set LED masks */
10152                         bnx2x_cl45_write(bp, phy,
10153                                          MDIO_PMA_DEVAD,
10154                                          MDIO_PMA_REG_8481_LED1_MASK,
10155                                          0x0);
10156
10157                         bnx2x_cl45_write(bp, phy,
10158                                          MDIO_PMA_DEVAD,
10159                                          MDIO_PMA_REG_8481_LED2_MASK,
10160                                          0x20);
10161
10162                         bnx2x_cl45_write(bp, phy,
10163                                          MDIO_PMA_DEVAD,
10164                                          MDIO_PMA_REG_8481_LED3_MASK,
10165                                          0x20);
10166
10167                         bnx2x_cl45_write(bp, phy,
10168                                          MDIO_PMA_DEVAD,
10169                                          MDIO_PMA_REG_8481_LED5_MASK,
10170                                          0x0);
10171                 } else {
10172                         bnx2x_cl45_write(bp, phy,
10173                                          MDIO_PMA_DEVAD,
10174                                          MDIO_PMA_REG_8481_LED1_MASK,
10175                                          0x20);
10176                 }
10177                 break;
10178
10179         case LED_MODE_OPER:
10180
10181                 DP(NETIF_MSG_LINK, "Port 0x%x: LED MODE OPER\n", port);
10182
10183                 if ((params->hw_led_mode << SHARED_HW_CFG_LED_MODE_SHIFT) ==
10184                     SHARED_HW_CFG_LED_EXTPHY1) {
10185
10186                         /* Set control reg */
10187                         bnx2x_cl45_read(bp, phy,
10188                                         MDIO_PMA_DEVAD,
10189                                         MDIO_PMA_REG_8481_LINK_SIGNAL,
10190                                         &val);
10191
10192                         if (!((val &
10193                                MDIO_PMA_REG_8481_LINK_SIGNAL_LED4_ENABLE_MASK)
10194                           >> MDIO_PMA_REG_8481_LINK_SIGNAL_LED4_ENABLE_SHIFT)) {
10195                                 DP(NETIF_MSG_LINK, "Setting LINK_SIGNAL\n");
10196                                 bnx2x_cl45_write(bp, phy,
10197                                                  MDIO_PMA_DEVAD,
10198                                                  MDIO_PMA_REG_8481_LINK_SIGNAL,
10199                                                  0xa492);
10200                         }
10201
10202                         /* Set LED masks */
10203                         bnx2x_cl45_write(bp, phy,
10204                                          MDIO_PMA_DEVAD,
10205                                          MDIO_PMA_REG_8481_LED1_MASK,
10206                                          0x10);
10207
10208                         bnx2x_cl45_write(bp, phy,
10209                                          MDIO_PMA_DEVAD,
10210                                          MDIO_PMA_REG_8481_LED2_MASK,
10211                                          0x80);
10212
10213                         bnx2x_cl45_write(bp, phy,
10214                                          MDIO_PMA_DEVAD,
10215                                          MDIO_PMA_REG_8481_LED3_MASK,
10216                                          0x98);
10217
10218                         bnx2x_cl45_write(bp, phy,
10219                                          MDIO_PMA_DEVAD,
10220                                          MDIO_PMA_REG_8481_LED5_MASK,
10221                                          0x40);
10222
10223                 } else {
10224                         bnx2x_cl45_write(bp, phy,
10225                                          MDIO_PMA_DEVAD,
10226                                          MDIO_PMA_REG_8481_LED1_MASK,
10227                                          0x80);
10228
10229                         /* Tell LED3 to blink on source */
10230                         bnx2x_cl45_read(bp, phy,
10231                                         MDIO_PMA_DEVAD,
10232                                         MDIO_PMA_REG_8481_LINK_SIGNAL,
10233                                         &val);
10234                         val &= ~(7<<6);
10235                         val |= (1<<6); /* A83B[8:6]= 1 */
10236                         bnx2x_cl45_write(bp, phy,
10237                                          MDIO_PMA_DEVAD,
10238                                          MDIO_PMA_REG_8481_LINK_SIGNAL,
10239                                          val);
10240                 }
10241                 break;
10242         }
10243
10244         /* This is a workaround for E3+84833 until autoneg
10245          * restart is fixed in f/w
10246          */
10247         if (CHIP_IS_E3(bp)) {
10248                 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
10249                                 MDIO_WC_REG_GP2_STATUS_GP_2_1, &val);
10250         }
10251 }
10252
10253 /******************************************************************/
10254 /*                      54618SE PHY SECTION                       */
10255 /******************************************************************/
10256 static int bnx2x_54618se_config_init(struct bnx2x_phy *phy,
10257                                                struct link_params *params,
10258                                                struct link_vars *vars)
10259 {
10260         struct bnx2x *bp = params->bp;
10261         u8 port;
10262         u16 autoneg_val, an_1000_val, an_10_100_val, fc_val, temp;
10263         u32 cfg_pin;
10264
10265         DP(NETIF_MSG_LINK, "54618SE cfg init\n");
10266         usleep_range(1000, 1000);
10267
10268         /* This works with E3 only, no need to check the chip
10269          * before determining the port.
10270          */
10271         port = params->port;
10272
10273         cfg_pin = (REG_RD(bp, params->shmem_base +
10274                         offsetof(struct shmem_region,
10275                         dev_info.port_hw_config[port].e3_cmn_pin_cfg)) &
10276                         PORT_HW_CFG_E3_PHY_RESET_MASK) >>
10277                         PORT_HW_CFG_E3_PHY_RESET_SHIFT;
10278
10279         /* Drive pin high to bring the GPHY out of reset. */
10280         bnx2x_set_cfg_pin(bp, cfg_pin, 1);
10281
10282         /* wait for GPHY to reset */
10283         msleep(50);
10284
10285         /* reset phy */
10286         bnx2x_cl22_write(bp, phy,
10287                          MDIO_PMA_REG_CTRL, 0x8000);
10288         bnx2x_wait_reset_complete(bp, phy, params);
10289
10290         /* Wait for GPHY to reset */
10291         msleep(50);
10292
10293         /* Configure LED4: set to INTR (0x6). */
10294         /* Accessing shadow register 0xe. */
10295         bnx2x_cl22_write(bp, phy,
10296                         MDIO_REG_GPHY_SHADOW,
10297                         MDIO_REG_GPHY_SHADOW_LED_SEL2);
10298         bnx2x_cl22_read(bp, phy,
10299                         MDIO_REG_GPHY_SHADOW,
10300                         &temp);
10301         temp &= ~(0xf << 4);
10302         temp |= (0x6 << 4);
10303         bnx2x_cl22_write(bp, phy,
10304                         MDIO_REG_GPHY_SHADOW,
10305                         MDIO_REG_GPHY_SHADOW_WR_ENA | temp);
10306         /* Configure INTR based on link status change. */
10307         bnx2x_cl22_write(bp, phy,
10308                         MDIO_REG_INTR_MASK,
10309                         ~MDIO_REG_INTR_MASK_LINK_STATUS);
10310
10311         /* Flip the signal detect polarity (set 0x1c.0x1e[8]). */
10312         bnx2x_cl22_write(bp, phy,
10313                         MDIO_REG_GPHY_SHADOW,
10314                         MDIO_REG_GPHY_SHADOW_AUTO_DET_MED);
10315         bnx2x_cl22_read(bp, phy,
10316                         MDIO_REG_GPHY_SHADOW,
10317                         &temp);
10318         temp |= MDIO_REG_GPHY_SHADOW_INVERT_FIB_SD;
10319         bnx2x_cl22_write(bp, phy,
10320                         MDIO_REG_GPHY_SHADOW,
10321                         MDIO_REG_GPHY_SHADOW_WR_ENA | temp);
10322
10323         /* Set up fc */
10324         /* Please refer to Table 28B-3 of 802.3ab-1999 spec. */
10325         bnx2x_calc_ieee_aneg_adv(phy, params, &vars->ieee_fc);
10326         fc_val = 0;
10327         if ((vars->ieee_fc & MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC) ==
10328                         MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC)
10329                 fc_val |= MDIO_AN_REG_ADV_PAUSE_ASYMMETRIC;
10330
10331         if ((vars->ieee_fc & MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH) ==
10332                         MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH)
10333                 fc_val |= MDIO_AN_REG_ADV_PAUSE_PAUSE;
10334
10335         /* read all advertisement */
10336         bnx2x_cl22_read(bp, phy,
10337                         0x09,
10338                         &an_1000_val);
10339
10340         bnx2x_cl22_read(bp, phy,
10341                         0x04,
10342                         &an_10_100_val);
10343
10344         bnx2x_cl22_read(bp, phy,
10345                         MDIO_PMA_REG_CTRL,
10346                         &autoneg_val);
10347
10348         /* Disable forced speed */
10349         autoneg_val &= ~((1<<6) | (1<<8) | (1<<9) | (1<<12) | (1<<13));
10350         an_10_100_val &= ~((1<<5) | (1<<6) | (1<<7) | (1<<8) | (1<<10) |
10351                            (1<<11));
10352
10353         if (((phy->req_line_speed == SPEED_AUTO_NEG) &&
10354                         (phy->speed_cap_mask &
10355                         PORT_HW_CFG_SPEED_CAPABILITY_D0_1G)) ||
10356                         (phy->req_line_speed == SPEED_1000)) {
10357                 an_1000_val |= (1<<8);
10358                 autoneg_val |= (1<<9 | 1<<12);
10359                 if (phy->req_duplex == DUPLEX_FULL)
10360                         an_1000_val |= (1<<9);
10361                 DP(NETIF_MSG_LINK, "Advertising 1G\n");
10362         } else
10363                 an_1000_val &= ~((1<<8) | (1<<9));
10364
10365         bnx2x_cl22_write(bp, phy,
10366                         0x09,
10367                         an_1000_val);
10368         bnx2x_cl22_read(bp, phy,
10369                         0x09,
10370                         &an_1000_val);
10371
10372         /* set 100 speed advertisement */
10373         if (((phy->req_line_speed == SPEED_AUTO_NEG) &&
10374                         (phy->speed_cap_mask &
10375                         (PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_FULL |
10376                         PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_HALF)))) {
10377                 an_10_100_val |= (1<<7);
10378                 /* Enable autoneg and restart autoneg for legacy speeds */
10379                 autoneg_val |= (1<<9 | 1<<12);
10380
10381                 if (phy->req_duplex == DUPLEX_FULL)
10382                         an_10_100_val |= (1<<8);
10383                 DP(NETIF_MSG_LINK, "Advertising 100M\n");
10384         }
10385
10386         /* set 10 speed advertisement */
10387         if (((phy->req_line_speed == SPEED_AUTO_NEG) &&
10388                         (phy->speed_cap_mask &
10389                         (PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_FULL |
10390                         PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_HALF)))) {
10391                 an_10_100_val |= (1<<5);
10392                 autoneg_val |= (1<<9 | 1<<12);
10393                 if (phy->req_duplex == DUPLEX_FULL)
10394                         an_10_100_val |= (1<<6);
10395                 DP(NETIF_MSG_LINK, "Advertising 10M\n");
10396         }
10397
10398         /* Only 10/100 are allowed to work in FORCE mode */
10399         if (phy->req_line_speed == SPEED_100) {
10400                 autoneg_val |= (1<<13);
10401                 /* Enabled AUTO-MDIX when autoneg is disabled */
10402                 bnx2x_cl22_write(bp, phy,
10403                                 0x18,
10404                                 (1<<15 | 1<<9 | 7<<0));
10405                 DP(NETIF_MSG_LINK, "Setting 100M force\n");
10406         }
10407         if (phy->req_line_speed == SPEED_10) {
10408                 /* Enabled AUTO-MDIX when autoneg is disabled */
10409                 bnx2x_cl22_write(bp, phy,
10410                                 0x18,
10411                                 (1<<15 | 1<<9 | 7<<0));
10412                 DP(NETIF_MSG_LINK, "Setting 10M force\n");
10413         }
10414
10415         /* Check if we should turn on Auto-GrEEEn */
10416         bnx2x_cl22_read(bp, phy, MDIO_REG_GPHY_PHYID_LSB, &temp);
10417         if (temp == MDIO_REG_GPHY_ID_54618SE) {
10418                 if (params->feature_config_flags &
10419                     FEATURE_CONFIG_AUTOGREEEN_ENABLED) {
10420                         temp = 6;
10421                         DP(NETIF_MSG_LINK, "Enabling Auto-GrEEEn\n");
10422                 } else {
10423                         temp = 0;
10424                         DP(NETIF_MSG_LINK, "Disabling Auto-GrEEEn\n");
10425                 }
10426                 bnx2x_cl22_write(bp, phy,
10427                                  MDIO_REG_GPHY_CL45_ADDR_REG, MDIO_AN_DEVAD);
10428                 bnx2x_cl22_write(bp, phy,
10429                                  MDIO_REG_GPHY_CL45_DATA_REG,
10430                                  MDIO_REG_GPHY_EEE_ADV);
10431                 bnx2x_cl22_write(bp, phy,
10432                                  MDIO_REG_GPHY_CL45_ADDR_REG,
10433                                  (0x1 << 14) | MDIO_AN_DEVAD);
10434                 bnx2x_cl22_write(bp, phy,
10435                                  MDIO_REG_GPHY_CL45_DATA_REG,
10436                                  temp);
10437         }
10438
10439         bnx2x_cl22_write(bp, phy,
10440                         0x04,
10441                         an_10_100_val | fc_val);
10442
10443         if (phy->req_duplex == DUPLEX_FULL)
10444                 autoneg_val |= (1<<8);
10445
10446         bnx2x_cl22_write(bp, phy,
10447                         MDIO_PMA_REG_CTRL, autoneg_val);
10448
10449         return 0;
10450 }
10451
10452
10453 static void bnx2x_5461x_set_link_led(struct bnx2x_phy *phy,
10454                                        struct link_params *params, u8 mode)
10455 {
10456         struct bnx2x *bp = params->bp;
10457         u16 temp;
10458
10459         bnx2x_cl22_write(bp, phy,
10460                 MDIO_REG_GPHY_SHADOW,
10461                 MDIO_REG_GPHY_SHADOW_LED_SEL1);
10462         bnx2x_cl22_read(bp, phy,
10463                 MDIO_REG_GPHY_SHADOW,
10464                 &temp);
10465         temp &= 0xff00;
10466
10467         DP(NETIF_MSG_LINK, "54618x set link led (mode=%x)\n", mode);
10468         switch (mode) {
10469         case LED_MODE_FRONT_PANEL_OFF:
10470         case LED_MODE_OFF:
10471                 temp |= 0x00ee;
10472                 break;
10473         case LED_MODE_OPER:
10474                 temp |= 0x0001;
10475                 break;
10476         case LED_MODE_ON:
10477                 temp |= 0x00ff;
10478                 break;
10479         default:
10480                 break;
10481         }
10482         bnx2x_cl22_write(bp, phy,
10483                 MDIO_REG_GPHY_SHADOW,
10484                 MDIO_REG_GPHY_SHADOW_WR_ENA | temp);
10485         return;
10486 }
10487
10488
10489 static void bnx2x_54618se_link_reset(struct bnx2x_phy *phy,
10490                                      struct link_params *params)
10491 {
10492         struct bnx2x *bp = params->bp;
10493         u32 cfg_pin;
10494         u8 port;
10495
10496         /* In case of no EPIO routed to reset the GPHY, put it
10497          * in low power mode.
10498          */
10499         bnx2x_cl22_write(bp, phy, MDIO_PMA_REG_CTRL, 0x800);
10500         /* This works with E3 only, no need to check the chip
10501          * before determining the port.
10502          */
10503         port = params->port;
10504         cfg_pin = (REG_RD(bp, params->shmem_base +
10505                         offsetof(struct shmem_region,
10506                         dev_info.port_hw_config[port].e3_cmn_pin_cfg)) &
10507                         PORT_HW_CFG_E3_PHY_RESET_MASK) >>
10508                         PORT_HW_CFG_E3_PHY_RESET_SHIFT;
10509
10510         /* Drive pin low to put GPHY in reset. */
10511         bnx2x_set_cfg_pin(bp, cfg_pin, 0);
10512 }
10513
10514 static u8 bnx2x_54618se_read_status(struct bnx2x_phy *phy,
10515                                     struct link_params *params,
10516                                     struct link_vars *vars)
10517 {
10518         struct bnx2x *bp = params->bp;
10519         u16 val;
10520         u8 link_up = 0;
10521         u16 legacy_status, legacy_speed;
10522
10523         /* Get speed operation status */
10524         bnx2x_cl22_read(bp, phy,
10525                         0x19,
10526                         &legacy_status);
10527         DP(NETIF_MSG_LINK, "54618SE read_status: 0x%x\n", legacy_status);
10528
10529         /* Read status to clear the PHY interrupt. */
10530         bnx2x_cl22_read(bp, phy,
10531                         MDIO_REG_INTR_STATUS,
10532                         &val);
10533
10534         link_up = ((legacy_status & (1<<2)) == (1<<2));
10535
10536         if (link_up) {
10537                 legacy_speed = (legacy_status & (7<<8));
10538                 if (legacy_speed == (7<<8)) {
10539                         vars->line_speed = SPEED_1000;
10540                         vars->duplex = DUPLEX_FULL;
10541                 } else if (legacy_speed == (6<<8)) {
10542                         vars->line_speed = SPEED_1000;
10543                         vars->duplex = DUPLEX_HALF;
10544                 } else if (legacy_speed == (5<<8)) {
10545                         vars->line_speed = SPEED_100;
10546                         vars->duplex = DUPLEX_FULL;
10547                 }
10548                 /* Omitting 100Base-T4 for now */
10549                 else if (legacy_speed == (3<<8)) {
10550                         vars->line_speed = SPEED_100;
10551                         vars->duplex = DUPLEX_HALF;
10552                 } else if (legacy_speed == (2<<8)) {
10553                         vars->line_speed = SPEED_10;
10554                         vars->duplex = DUPLEX_FULL;
10555                 } else if (legacy_speed == (1<<8)) {
10556                         vars->line_speed = SPEED_10;
10557                         vars->duplex = DUPLEX_HALF;
10558                 } else /* Should not happen */
10559                         vars->line_speed = 0;
10560
10561                 DP(NETIF_MSG_LINK,
10562                    "Link is up in %dMbps, is_duplex_full= %d\n",
10563                    vars->line_speed,
10564                    (vars->duplex == DUPLEX_FULL));
10565
10566                 /* Check legacy speed AN resolution */
10567                 bnx2x_cl22_read(bp, phy,
10568                                 0x01,
10569                                 &val);
10570                 if (val & (1<<5))
10571                         vars->link_status |=
10572                                 LINK_STATUS_AUTO_NEGOTIATE_COMPLETE;
10573                 bnx2x_cl22_read(bp, phy,
10574                                 0x06,
10575                                 &val);
10576                 if ((val & (1<<0)) == 0)
10577                         vars->link_status |=
10578                                 LINK_STATUS_PARALLEL_DETECTION_USED;
10579
10580                 DP(NETIF_MSG_LINK, "BCM54618SE: link speed is %d\n",
10581                            vars->line_speed);
10582
10583                 /* Report whether EEE is resolved. */
10584                 bnx2x_cl22_read(bp, phy, MDIO_REG_GPHY_PHYID_LSB, &val);
10585                 if (val == MDIO_REG_GPHY_ID_54618SE) {
10586                         if (vars->link_status &
10587                             LINK_STATUS_AUTO_NEGOTIATE_COMPLETE)
10588                                 val = 0;
10589                         else {
10590                                 bnx2x_cl22_write(bp, phy,
10591                                         MDIO_REG_GPHY_CL45_ADDR_REG,
10592                                         MDIO_AN_DEVAD);
10593                                 bnx2x_cl22_write(bp, phy,
10594                                         MDIO_REG_GPHY_CL45_DATA_REG,
10595                                         MDIO_REG_GPHY_EEE_RESOLVED);
10596                                 bnx2x_cl22_write(bp, phy,
10597                                         MDIO_REG_GPHY_CL45_ADDR_REG,
10598                                         (0x1 << 14) | MDIO_AN_DEVAD);
10599                                 bnx2x_cl22_read(bp, phy,
10600                                         MDIO_REG_GPHY_CL45_DATA_REG,
10601                                         &val);
10602                         }
10603                         DP(NETIF_MSG_LINK, "EEE resolution: 0x%x\n", val);
10604                 }
10605
10606                 bnx2x_ext_phy_resolve_fc(phy, params, vars);
10607
10608                 if (vars->link_status & LINK_STATUS_AUTO_NEGOTIATE_COMPLETE) {
10609                         /* Report LP advertised speeds */
10610                         bnx2x_cl22_read(bp, phy, 0x5, &val);
10611
10612                         if (val & (1<<5))
10613                                 vars->link_status |=
10614                                   LINK_STATUS_LINK_PARTNER_10THD_CAPABLE;
10615                         if (val & (1<<6))
10616                                 vars->link_status |=
10617                                   LINK_STATUS_LINK_PARTNER_10TFD_CAPABLE;
10618                         if (val & (1<<7))
10619                                 vars->link_status |=
10620                                   LINK_STATUS_LINK_PARTNER_100TXHD_CAPABLE;
10621                         if (val & (1<<8))
10622                                 vars->link_status |=
10623                                   LINK_STATUS_LINK_PARTNER_100TXFD_CAPABLE;
10624                         if (val & (1<<9))
10625                                 vars->link_status |=
10626                                   LINK_STATUS_LINK_PARTNER_100T4_CAPABLE;
10627
10628                         bnx2x_cl22_read(bp, phy, 0xa, &val);
10629                         if (val & (1<<10))
10630                                 vars->link_status |=
10631                                   LINK_STATUS_LINK_PARTNER_1000THD_CAPABLE;
10632                         if (val & (1<<11))
10633                                 vars->link_status |=
10634                                   LINK_STATUS_LINK_PARTNER_1000TFD_CAPABLE;
10635                 }
10636         }
10637         return link_up;
10638 }
10639
10640 static void bnx2x_54618se_config_loopback(struct bnx2x_phy *phy,
10641                                           struct link_params *params)
10642 {
10643         struct bnx2x *bp = params->bp;
10644         u16 val;
10645         u32 umac_base = params->port ? GRCBASE_UMAC1 : GRCBASE_UMAC0;
10646
10647         DP(NETIF_MSG_LINK, "2PMA/PMD ext_phy_loopback: 54618se\n");
10648
10649         /* Enable master/slave manual mmode and set to master */
10650         /* mii write 9 [bits set 11 12] */
10651         bnx2x_cl22_write(bp, phy, 0x09, 3<<11);
10652
10653         /* forced 1G and disable autoneg */
10654         /* set val [mii read 0] */
10655         /* set val [expr $val & [bits clear 6 12 13]] */
10656         /* set val [expr $val | [bits set 6 8]] */
10657         /* mii write 0 $val */
10658         bnx2x_cl22_read(bp, phy, 0x00, &val);
10659         val &= ~((1<<6) | (1<<12) | (1<<13));
10660         val |= (1<<6) | (1<<8);
10661         bnx2x_cl22_write(bp, phy, 0x00, val);
10662
10663         /* Set external loopback and Tx using 6dB coding */
10664         /* mii write 0x18 7 */
10665         /* set val [mii read 0x18] */
10666         /* mii write 0x18 [expr $val | [bits set 10 15]] */
10667         bnx2x_cl22_write(bp, phy, 0x18, 7);
10668         bnx2x_cl22_read(bp, phy, 0x18, &val);
10669         bnx2x_cl22_write(bp, phy, 0x18, val | (1<<10) | (1<<15));
10670
10671         /* This register opens the gate for the UMAC despite its name */
10672         REG_WR(bp, NIG_REG_EGRESS_EMAC0_PORT + params->port*4, 1);
10673
10674         /* Maximum Frame Length (RW). Defines a 14-Bit maximum frame
10675          * length used by the MAC receive logic to check frames.
10676          */
10677         REG_WR(bp, umac_base + UMAC_REG_MAXFR, 0x2710);
10678 }
10679
10680 /******************************************************************/
10681 /*                      SFX7101 PHY SECTION                       */
10682 /******************************************************************/
10683 static void bnx2x_7101_config_loopback(struct bnx2x_phy *phy,
10684                                        struct link_params *params)
10685 {
10686         struct bnx2x *bp = params->bp;
10687         /* SFX7101_XGXS_TEST1 */
10688         bnx2x_cl45_write(bp, phy,
10689                          MDIO_XS_DEVAD, MDIO_XS_SFX7101_XGXS_TEST1, 0x100);
10690 }
10691
10692 static int bnx2x_7101_config_init(struct bnx2x_phy *phy,
10693                                   struct link_params *params,
10694                                   struct link_vars *vars)
10695 {
10696         u16 fw_ver1, fw_ver2, val;
10697         struct bnx2x *bp = params->bp;
10698         DP(NETIF_MSG_LINK, "Setting the SFX7101 LASI indication\n");
10699
10700         /* Restore normal power mode*/
10701         bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_2,
10702                        MISC_REGISTERS_GPIO_OUTPUT_HIGH, params->port);
10703         /* HW reset */
10704         bnx2x_ext_phy_hw_reset(bp, params->port);
10705         bnx2x_wait_reset_complete(bp, phy, params);
10706
10707         bnx2x_cl45_write(bp, phy,
10708                          MDIO_PMA_DEVAD, MDIO_PMA_LASI_CTRL, 0x1);
10709         DP(NETIF_MSG_LINK, "Setting the SFX7101 LED to blink on traffic\n");
10710         bnx2x_cl45_write(bp, phy,
10711                          MDIO_PMA_DEVAD, MDIO_PMA_REG_7107_LED_CNTL, (1<<3));
10712
10713         bnx2x_ext_phy_set_pause(params, phy, vars);
10714         /* Restart autoneg */
10715         bnx2x_cl45_read(bp, phy,
10716                         MDIO_AN_DEVAD, MDIO_AN_REG_CTRL, &val);
10717         val |= 0x200;
10718         bnx2x_cl45_write(bp, phy,
10719                          MDIO_AN_DEVAD, MDIO_AN_REG_CTRL, val);
10720
10721         /* Save spirom version */
10722         bnx2x_cl45_read(bp, phy,
10723                         MDIO_PMA_DEVAD, MDIO_PMA_REG_7101_VER1, &fw_ver1);
10724
10725         bnx2x_cl45_read(bp, phy,
10726                         MDIO_PMA_DEVAD, MDIO_PMA_REG_7101_VER2, &fw_ver2);
10727         bnx2x_save_spirom_version(bp, params->port,
10728                                   (u32)(fw_ver1<<16 | fw_ver2), phy->ver_addr);
10729         return 0;
10730 }
10731
10732 static u8 bnx2x_7101_read_status(struct bnx2x_phy *phy,
10733                                  struct link_params *params,
10734                                  struct link_vars *vars)
10735 {
10736         struct bnx2x *bp = params->bp;
10737         u8 link_up;
10738         u16 val1, val2;
10739         bnx2x_cl45_read(bp, phy,
10740                         MDIO_PMA_DEVAD, MDIO_PMA_LASI_STAT, &val2);
10741         bnx2x_cl45_read(bp, phy,
10742                         MDIO_PMA_DEVAD, MDIO_PMA_LASI_STAT, &val1);
10743         DP(NETIF_MSG_LINK, "10G-base-T LASI status 0x%x->0x%x\n",
10744                    val2, val1);
10745         bnx2x_cl45_read(bp, phy,
10746                         MDIO_PMA_DEVAD, MDIO_PMA_REG_STATUS, &val2);
10747         bnx2x_cl45_read(bp, phy,
10748                         MDIO_PMA_DEVAD, MDIO_PMA_REG_STATUS, &val1);
10749         DP(NETIF_MSG_LINK, "10G-base-T PMA status 0x%x->0x%x\n",
10750                    val2, val1);
10751         link_up = ((val1 & 4) == 4);
10752         /* if link is up print the AN outcome of the SFX7101 PHY */
10753         if (link_up) {
10754                 bnx2x_cl45_read(bp, phy,
10755                                 MDIO_AN_DEVAD, MDIO_AN_REG_MASTER_STATUS,
10756                                 &val2);
10757                 vars->line_speed = SPEED_10000;
10758                 vars->duplex = DUPLEX_FULL;
10759                 DP(NETIF_MSG_LINK, "SFX7101 AN status 0x%x->Master=%x\n",
10760                            val2, (val2 & (1<<14)));
10761                 bnx2x_ext_phy_10G_an_resolve(bp, phy, vars);
10762                 bnx2x_ext_phy_resolve_fc(phy, params, vars);
10763
10764                 /* read LP advertised speeds */
10765                 if (val2 & (1<<11))
10766                         vars->link_status |=
10767                                 LINK_STATUS_LINK_PARTNER_10GXFD_CAPABLE;
10768         }
10769         return link_up;
10770 }
10771
10772 static int bnx2x_7101_format_ver(u32 spirom_ver, u8 *str, u16 *len)
10773 {
10774         if (*len < 5)
10775                 return -EINVAL;
10776         str[0] = (spirom_ver & 0xFF);
10777         str[1] = (spirom_ver & 0xFF00) >> 8;
10778         str[2] = (spirom_ver & 0xFF0000) >> 16;
10779         str[3] = (spirom_ver & 0xFF000000) >> 24;
10780         str[4] = '\0';
10781         *len -= 5;
10782         return 0;
10783 }
10784
10785 void bnx2x_sfx7101_sp_sw_reset(struct bnx2x *bp, struct bnx2x_phy *phy)
10786 {
10787         u16 val, cnt;
10788
10789         bnx2x_cl45_read(bp, phy,
10790                         MDIO_PMA_DEVAD,
10791                         MDIO_PMA_REG_7101_RESET, &val);
10792
10793         for (cnt = 0; cnt < 10; cnt++) {
10794                 msleep(50);
10795                 /* Writes a self-clearing reset */
10796                 bnx2x_cl45_write(bp, phy,
10797                                  MDIO_PMA_DEVAD,
10798                                  MDIO_PMA_REG_7101_RESET,
10799                                  (val | (1<<15)));
10800                 /* Wait for clear */
10801                 bnx2x_cl45_read(bp, phy,
10802                                 MDIO_PMA_DEVAD,
10803                                 MDIO_PMA_REG_7101_RESET, &val);
10804
10805                 if ((val & (1<<15)) == 0)
10806                         break;
10807         }
10808 }
10809
10810 static void bnx2x_7101_hw_reset(struct bnx2x_phy *phy,
10811                                 struct link_params *params) {
10812         /* Low power mode is controlled by GPIO 2 */
10813         bnx2x_set_gpio(params->bp, MISC_REGISTERS_GPIO_2,
10814                        MISC_REGISTERS_GPIO_OUTPUT_LOW, params->port);
10815         /* The PHY reset is controlled by GPIO 1 */
10816         bnx2x_set_gpio(params->bp, MISC_REGISTERS_GPIO_1,
10817                        MISC_REGISTERS_GPIO_OUTPUT_LOW, params->port);
10818 }
10819
10820 static void bnx2x_7101_set_link_led(struct bnx2x_phy *phy,
10821                                     struct link_params *params, u8 mode)
10822 {
10823         u16 val = 0;
10824         struct bnx2x *bp = params->bp;
10825         switch (mode) {
10826         case LED_MODE_FRONT_PANEL_OFF:
10827         case LED_MODE_OFF:
10828                 val = 2;
10829                 break;
10830         case LED_MODE_ON:
10831                 val = 1;
10832                 break;
10833         case LED_MODE_OPER:
10834                 val = 0;
10835                 break;
10836         }
10837         bnx2x_cl45_write(bp, phy,
10838                          MDIO_PMA_DEVAD,
10839                          MDIO_PMA_REG_7107_LINK_LED_CNTL,
10840                          val);
10841 }
10842
10843 /******************************************************************/
10844 /*                      STATIC PHY DECLARATION                    */
10845 /******************************************************************/
10846
10847 static struct bnx2x_phy phy_null = {
10848         .type           = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_NOT_CONN,
10849         .addr           = 0,
10850         .def_md_devad   = 0,
10851         .flags          = FLAGS_INIT_XGXS_FIRST,
10852         .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
10853         .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
10854         .mdio_ctrl      = 0,
10855         .supported      = 0,
10856         .media_type     = ETH_PHY_NOT_PRESENT,
10857         .ver_addr       = 0,
10858         .req_flow_ctrl  = 0,
10859         .req_line_speed = 0,
10860         .speed_cap_mask = 0,
10861         .req_duplex     = 0,
10862         .rsrv           = 0,
10863         .config_init    = (config_init_t)NULL,
10864         .read_status    = (read_status_t)NULL,
10865         .link_reset     = (link_reset_t)NULL,
10866         .config_loopback = (config_loopback_t)NULL,
10867         .format_fw_ver  = (format_fw_ver_t)NULL,
10868         .hw_reset       = (hw_reset_t)NULL,
10869         .set_link_led   = (set_link_led_t)NULL,
10870         .phy_specific_func = (phy_specific_func_t)NULL
10871 };
10872
10873 static struct bnx2x_phy phy_serdes = {
10874         .type           = PORT_HW_CFG_SERDES_EXT_PHY_TYPE_DIRECT,
10875         .addr           = 0xff,
10876         .def_md_devad   = 0,
10877         .flags          = 0,
10878         .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
10879         .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
10880         .mdio_ctrl      = 0,
10881         .supported      = (SUPPORTED_10baseT_Half |
10882                            SUPPORTED_10baseT_Full |
10883                            SUPPORTED_100baseT_Half |
10884                            SUPPORTED_100baseT_Full |
10885                            SUPPORTED_1000baseT_Full |
10886                            SUPPORTED_2500baseX_Full |
10887                            SUPPORTED_TP |
10888                            SUPPORTED_Autoneg |
10889                            SUPPORTED_Pause |
10890                            SUPPORTED_Asym_Pause),
10891         .media_type     = ETH_PHY_BASE_T,
10892         .ver_addr       = 0,
10893         .req_flow_ctrl  = 0,
10894         .req_line_speed = 0,
10895         .speed_cap_mask = 0,
10896         .req_duplex     = 0,
10897         .rsrv           = 0,
10898         .config_init    = (config_init_t)bnx2x_xgxs_config_init,
10899         .read_status    = (read_status_t)bnx2x_link_settings_status,
10900         .link_reset     = (link_reset_t)bnx2x_int_link_reset,
10901         .config_loopback = (config_loopback_t)NULL,
10902         .format_fw_ver  = (format_fw_ver_t)NULL,
10903         .hw_reset       = (hw_reset_t)NULL,
10904         .set_link_led   = (set_link_led_t)NULL,
10905         .phy_specific_func = (phy_specific_func_t)NULL
10906 };
10907
10908 static struct bnx2x_phy phy_xgxs = {
10909         .type           = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT,
10910         .addr           = 0xff,
10911         .def_md_devad   = 0,
10912         .flags          = 0,
10913         .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
10914         .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
10915         .mdio_ctrl      = 0,
10916         .supported      = (SUPPORTED_10baseT_Half |
10917                            SUPPORTED_10baseT_Full |
10918                            SUPPORTED_100baseT_Half |
10919                            SUPPORTED_100baseT_Full |
10920                            SUPPORTED_1000baseT_Full |
10921                            SUPPORTED_2500baseX_Full |
10922                            SUPPORTED_10000baseT_Full |
10923                            SUPPORTED_FIBRE |
10924                            SUPPORTED_Autoneg |
10925                            SUPPORTED_Pause |
10926                            SUPPORTED_Asym_Pause),
10927         .media_type     = ETH_PHY_CX4,
10928         .ver_addr       = 0,
10929         .req_flow_ctrl  = 0,
10930         .req_line_speed = 0,
10931         .speed_cap_mask = 0,
10932         .req_duplex     = 0,
10933         .rsrv           = 0,
10934         .config_init    = (config_init_t)bnx2x_xgxs_config_init,
10935         .read_status    = (read_status_t)bnx2x_link_settings_status,
10936         .link_reset     = (link_reset_t)bnx2x_int_link_reset,
10937         .config_loopback = (config_loopback_t)bnx2x_set_xgxs_loopback,
10938         .format_fw_ver  = (format_fw_ver_t)NULL,
10939         .hw_reset       = (hw_reset_t)NULL,
10940         .set_link_led   = (set_link_led_t)NULL,
10941         .phy_specific_func = (phy_specific_func_t)NULL
10942 };
10943 static struct bnx2x_phy phy_warpcore = {
10944         .type           = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT,
10945         .addr           = 0xff,
10946         .def_md_devad   = 0,
10947         .flags          = (FLAGS_HW_LOCK_REQUIRED |
10948                            FLAGS_TX_ERROR_CHECK),
10949         .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
10950         .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
10951         .mdio_ctrl      = 0,
10952         .supported      = (SUPPORTED_10baseT_Half |
10953                            SUPPORTED_10baseT_Full |
10954                            SUPPORTED_100baseT_Half |
10955                            SUPPORTED_100baseT_Full |
10956                            SUPPORTED_1000baseT_Full |
10957                            SUPPORTED_10000baseT_Full |
10958                            SUPPORTED_20000baseKR2_Full |
10959                            SUPPORTED_20000baseMLD2_Full |
10960                            SUPPORTED_FIBRE |
10961                            SUPPORTED_Autoneg |
10962                            SUPPORTED_Pause |
10963                            SUPPORTED_Asym_Pause),
10964         .media_type     = ETH_PHY_UNSPECIFIED,
10965         .ver_addr       = 0,
10966         .req_flow_ctrl  = 0,
10967         .req_line_speed = 0,
10968         .speed_cap_mask = 0,
10969         /* req_duplex = */0,
10970         /* rsrv = */0,
10971         .config_init    = (config_init_t)bnx2x_warpcore_config_init,
10972         .read_status    = (read_status_t)bnx2x_warpcore_read_status,
10973         .link_reset     = (link_reset_t)bnx2x_warpcore_link_reset,
10974         .config_loopback = (config_loopback_t)bnx2x_set_warpcore_loopback,
10975         .format_fw_ver  = (format_fw_ver_t)NULL,
10976         .hw_reset       = (hw_reset_t)bnx2x_warpcore_hw_reset,
10977         .set_link_led   = (set_link_led_t)NULL,
10978         .phy_specific_func = (phy_specific_func_t)NULL
10979 };
10980
10981
10982 static struct bnx2x_phy phy_7101 = {
10983         .type           = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_SFX7101,
10984         .addr           = 0xff,
10985         .def_md_devad   = 0,
10986         .flags          = FLAGS_FAN_FAILURE_DET_REQ,
10987         .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
10988         .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
10989         .mdio_ctrl      = 0,
10990         .supported      = (SUPPORTED_10000baseT_Full |
10991                            SUPPORTED_TP |
10992                            SUPPORTED_Autoneg |
10993                            SUPPORTED_Pause |
10994                            SUPPORTED_Asym_Pause),
10995         .media_type     = ETH_PHY_BASE_T,
10996         .ver_addr       = 0,
10997         .req_flow_ctrl  = 0,
10998         .req_line_speed = 0,
10999         .speed_cap_mask = 0,
11000         .req_duplex     = 0,
11001         .rsrv           = 0,
11002         .config_init    = (config_init_t)bnx2x_7101_config_init,
11003         .read_status    = (read_status_t)bnx2x_7101_read_status,
11004         .link_reset     = (link_reset_t)bnx2x_common_ext_link_reset,
11005         .config_loopback = (config_loopback_t)bnx2x_7101_config_loopback,
11006         .format_fw_ver  = (format_fw_ver_t)bnx2x_7101_format_ver,
11007         .hw_reset       = (hw_reset_t)bnx2x_7101_hw_reset,
11008         .set_link_led   = (set_link_led_t)bnx2x_7101_set_link_led,
11009         .phy_specific_func = (phy_specific_func_t)NULL
11010 };
11011 static struct bnx2x_phy phy_8073 = {
11012         .type           = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073,
11013         .addr           = 0xff,
11014         .def_md_devad   = 0,
11015         .flags          = FLAGS_HW_LOCK_REQUIRED,
11016         .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
11017         .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
11018         .mdio_ctrl      = 0,
11019         .supported      = (SUPPORTED_10000baseT_Full |
11020                            SUPPORTED_2500baseX_Full |
11021                            SUPPORTED_1000baseT_Full |
11022                            SUPPORTED_FIBRE |
11023                            SUPPORTED_Autoneg |
11024                            SUPPORTED_Pause |
11025                            SUPPORTED_Asym_Pause),
11026         .media_type     = ETH_PHY_KR,
11027         .ver_addr       = 0,
11028         .req_flow_ctrl  = 0,
11029         .req_line_speed = 0,
11030         .speed_cap_mask = 0,
11031         .req_duplex     = 0,
11032         .rsrv           = 0,
11033         .config_init    = (config_init_t)bnx2x_8073_config_init,
11034         .read_status    = (read_status_t)bnx2x_8073_read_status,
11035         .link_reset     = (link_reset_t)bnx2x_8073_link_reset,
11036         .config_loopback = (config_loopback_t)NULL,
11037         .format_fw_ver  = (format_fw_ver_t)bnx2x_format_ver,
11038         .hw_reset       = (hw_reset_t)NULL,
11039         .set_link_led   = (set_link_led_t)NULL,
11040         .phy_specific_func = (phy_specific_func_t)NULL
11041 };
11042 static struct bnx2x_phy phy_8705 = {
11043         .type           = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8705,
11044         .addr           = 0xff,
11045         .def_md_devad   = 0,
11046         .flags          = FLAGS_INIT_XGXS_FIRST,
11047         .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
11048         .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
11049         .mdio_ctrl      = 0,
11050         .supported      = (SUPPORTED_10000baseT_Full |
11051                            SUPPORTED_FIBRE |
11052                            SUPPORTED_Pause |
11053                            SUPPORTED_Asym_Pause),
11054         .media_type     = ETH_PHY_XFP_FIBER,
11055         .ver_addr       = 0,
11056         .req_flow_ctrl  = 0,
11057         .req_line_speed = 0,
11058         .speed_cap_mask = 0,
11059         .req_duplex     = 0,
11060         .rsrv           = 0,
11061         .config_init    = (config_init_t)bnx2x_8705_config_init,
11062         .read_status    = (read_status_t)bnx2x_8705_read_status,
11063         .link_reset     = (link_reset_t)bnx2x_common_ext_link_reset,
11064         .config_loopback = (config_loopback_t)NULL,
11065         .format_fw_ver  = (format_fw_ver_t)bnx2x_null_format_ver,
11066         .hw_reset       = (hw_reset_t)NULL,
11067         .set_link_led   = (set_link_led_t)NULL,
11068         .phy_specific_func = (phy_specific_func_t)NULL
11069 };
11070 static struct bnx2x_phy phy_8706 = {
11071         .type           = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8706,
11072         .addr           = 0xff,
11073         .def_md_devad   = 0,
11074         .flags          = FLAGS_INIT_XGXS_FIRST,
11075         .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
11076         .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
11077         .mdio_ctrl      = 0,
11078         .supported      = (SUPPORTED_10000baseT_Full |
11079                            SUPPORTED_1000baseT_Full |
11080                            SUPPORTED_FIBRE |
11081                            SUPPORTED_Pause |
11082                            SUPPORTED_Asym_Pause),
11083         .media_type     = ETH_PHY_SFP_FIBER,
11084         .ver_addr       = 0,
11085         .req_flow_ctrl  = 0,
11086         .req_line_speed = 0,
11087         .speed_cap_mask = 0,
11088         .req_duplex     = 0,
11089         .rsrv           = 0,
11090         .config_init    = (config_init_t)bnx2x_8706_config_init,
11091         .read_status    = (read_status_t)bnx2x_8706_read_status,
11092         .link_reset     = (link_reset_t)bnx2x_common_ext_link_reset,
11093         .config_loopback = (config_loopback_t)NULL,
11094         .format_fw_ver  = (format_fw_ver_t)bnx2x_format_ver,
11095         .hw_reset       = (hw_reset_t)NULL,
11096         .set_link_led   = (set_link_led_t)NULL,
11097         .phy_specific_func = (phy_specific_func_t)NULL
11098 };
11099
11100 static struct bnx2x_phy phy_8726 = {
11101         .type           = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8726,
11102         .addr           = 0xff,
11103         .def_md_devad   = 0,
11104         .flags          = (FLAGS_HW_LOCK_REQUIRED |
11105                            FLAGS_INIT_XGXS_FIRST |
11106                            FLAGS_TX_ERROR_CHECK),
11107         .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
11108         .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
11109         .mdio_ctrl      = 0,
11110         .supported      = (SUPPORTED_10000baseT_Full |
11111                            SUPPORTED_1000baseT_Full |
11112                            SUPPORTED_Autoneg |
11113                            SUPPORTED_FIBRE |
11114                            SUPPORTED_Pause |
11115                            SUPPORTED_Asym_Pause),
11116         .media_type     = ETH_PHY_NOT_PRESENT,
11117         .ver_addr       = 0,
11118         .req_flow_ctrl  = 0,
11119         .req_line_speed = 0,
11120         .speed_cap_mask = 0,
11121         .req_duplex     = 0,
11122         .rsrv           = 0,
11123         .config_init    = (config_init_t)bnx2x_8726_config_init,
11124         .read_status    = (read_status_t)bnx2x_8726_read_status,
11125         .link_reset     = (link_reset_t)bnx2x_8726_link_reset,
11126         .config_loopback = (config_loopback_t)bnx2x_8726_config_loopback,
11127         .format_fw_ver  = (format_fw_ver_t)bnx2x_format_ver,
11128         .hw_reset       = (hw_reset_t)NULL,
11129         .set_link_led   = (set_link_led_t)NULL,
11130         .phy_specific_func = (phy_specific_func_t)NULL
11131 };
11132
11133 static struct bnx2x_phy phy_8727 = {
11134         .type           = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727,
11135         .addr           = 0xff,
11136         .def_md_devad   = 0,
11137         .flags          = (FLAGS_FAN_FAILURE_DET_REQ |
11138                            FLAGS_TX_ERROR_CHECK),
11139         .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
11140         .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
11141         .mdio_ctrl      = 0,
11142         .supported      = (SUPPORTED_10000baseT_Full |
11143                            SUPPORTED_1000baseT_Full |
11144                            SUPPORTED_FIBRE |
11145                            SUPPORTED_Pause |
11146                            SUPPORTED_Asym_Pause),
11147         .media_type     = ETH_PHY_NOT_PRESENT,
11148         .ver_addr       = 0,
11149         .req_flow_ctrl  = 0,
11150         .req_line_speed = 0,
11151         .speed_cap_mask = 0,
11152         .req_duplex     = 0,
11153         .rsrv           = 0,
11154         .config_init    = (config_init_t)bnx2x_8727_config_init,
11155         .read_status    = (read_status_t)bnx2x_8727_read_status,
11156         .link_reset     = (link_reset_t)bnx2x_8727_link_reset,
11157         .config_loopback = (config_loopback_t)NULL,
11158         .format_fw_ver  = (format_fw_ver_t)bnx2x_format_ver,
11159         .hw_reset       = (hw_reset_t)bnx2x_8727_hw_reset,
11160         .set_link_led   = (set_link_led_t)bnx2x_8727_set_link_led,
11161         .phy_specific_func = (phy_specific_func_t)bnx2x_8727_specific_func
11162 };
11163 static struct bnx2x_phy phy_8481 = {
11164         .type           = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8481,
11165         .addr           = 0xff,
11166         .def_md_devad   = 0,
11167         .flags          = FLAGS_FAN_FAILURE_DET_REQ |
11168                           FLAGS_REARM_LATCH_SIGNAL,
11169         .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
11170         .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
11171         .mdio_ctrl      = 0,
11172         .supported      = (SUPPORTED_10baseT_Half |
11173                            SUPPORTED_10baseT_Full |
11174                            SUPPORTED_100baseT_Half |
11175                            SUPPORTED_100baseT_Full |
11176                            SUPPORTED_1000baseT_Full |
11177                            SUPPORTED_10000baseT_Full |
11178                            SUPPORTED_TP |
11179                            SUPPORTED_Autoneg |
11180                            SUPPORTED_Pause |
11181                            SUPPORTED_Asym_Pause),
11182         .media_type     = ETH_PHY_BASE_T,
11183         .ver_addr       = 0,
11184         .req_flow_ctrl  = 0,
11185         .req_line_speed = 0,
11186         .speed_cap_mask = 0,
11187         .req_duplex     = 0,
11188         .rsrv           = 0,
11189         .config_init    = (config_init_t)bnx2x_8481_config_init,
11190         .read_status    = (read_status_t)bnx2x_848xx_read_status,
11191         .link_reset     = (link_reset_t)bnx2x_8481_link_reset,
11192         .config_loopback = (config_loopback_t)NULL,
11193         .format_fw_ver  = (format_fw_ver_t)bnx2x_848xx_format_ver,
11194         .hw_reset       = (hw_reset_t)bnx2x_8481_hw_reset,
11195         .set_link_led   = (set_link_led_t)bnx2x_848xx_set_link_led,
11196         .phy_specific_func = (phy_specific_func_t)NULL
11197 };
11198
11199 static struct bnx2x_phy phy_84823 = {
11200         .type           = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84823,
11201         .addr           = 0xff,
11202         .def_md_devad   = 0,
11203         .flags          = (FLAGS_FAN_FAILURE_DET_REQ |
11204                            FLAGS_REARM_LATCH_SIGNAL |
11205                            FLAGS_TX_ERROR_CHECK),
11206         .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
11207         .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
11208         .mdio_ctrl      = 0,
11209         .supported      = (SUPPORTED_10baseT_Half |
11210                            SUPPORTED_10baseT_Full |
11211                            SUPPORTED_100baseT_Half |
11212                            SUPPORTED_100baseT_Full |
11213                            SUPPORTED_1000baseT_Full |
11214                            SUPPORTED_10000baseT_Full |
11215                            SUPPORTED_TP |
11216                            SUPPORTED_Autoneg |
11217                            SUPPORTED_Pause |
11218                            SUPPORTED_Asym_Pause),
11219         .media_type     = ETH_PHY_BASE_T,
11220         .ver_addr       = 0,
11221         .req_flow_ctrl  = 0,
11222         .req_line_speed = 0,
11223         .speed_cap_mask = 0,
11224         .req_duplex     = 0,
11225         .rsrv           = 0,
11226         .config_init    = (config_init_t)bnx2x_848x3_config_init,
11227         .read_status    = (read_status_t)bnx2x_848xx_read_status,
11228         .link_reset     = (link_reset_t)bnx2x_848x3_link_reset,
11229         .config_loopback = (config_loopback_t)NULL,
11230         .format_fw_ver  = (format_fw_ver_t)bnx2x_848xx_format_ver,
11231         .hw_reset       = (hw_reset_t)NULL,
11232         .set_link_led   = (set_link_led_t)bnx2x_848xx_set_link_led,
11233         .phy_specific_func = (phy_specific_func_t)NULL
11234 };
11235
11236 static struct bnx2x_phy phy_84833 = {
11237         .type           = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84833,
11238         .addr           = 0xff,
11239         .def_md_devad   = 0,
11240         .flags          = (FLAGS_FAN_FAILURE_DET_REQ |
11241                            FLAGS_REARM_LATCH_SIGNAL |
11242                            FLAGS_TX_ERROR_CHECK),
11243         .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
11244         .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
11245         .mdio_ctrl      = 0,
11246         .supported      = (SUPPORTED_100baseT_Half |
11247                            SUPPORTED_100baseT_Full |
11248                            SUPPORTED_1000baseT_Full |
11249                            SUPPORTED_10000baseT_Full |
11250                            SUPPORTED_TP |
11251                            SUPPORTED_Autoneg |
11252                            SUPPORTED_Pause |
11253                            SUPPORTED_Asym_Pause),
11254         .media_type     = ETH_PHY_BASE_T,
11255         .ver_addr       = 0,
11256         .req_flow_ctrl  = 0,
11257         .req_line_speed = 0,
11258         .speed_cap_mask = 0,
11259         .req_duplex     = 0,
11260         .rsrv           = 0,
11261         .config_init    = (config_init_t)bnx2x_848x3_config_init,
11262         .read_status    = (read_status_t)bnx2x_848xx_read_status,
11263         .link_reset     = (link_reset_t)bnx2x_848x3_link_reset,
11264         .config_loopback = (config_loopback_t)NULL,
11265         .format_fw_ver  = (format_fw_ver_t)bnx2x_848xx_format_ver,
11266         .hw_reset       = (hw_reset_t)bnx2x_84833_hw_reset_phy,
11267         .set_link_led   = (set_link_led_t)bnx2x_848xx_set_link_led,
11268         .phy_specific_func = (phy_specific_func_t)NULL
11269 };
11270
11271 static struct bnx2x_phy phy_54618se = {
11272         .type           = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM54618SE,
11273         .addr           = 0xff,
11274         .def_md_devad   = 0,
11275         .flags          = FLAGS_INIT_XGXS_FIRST,
11276         .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
11277         .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
11278         .mdio_ctrl      = 0,
11279         .supported      = (SUPPORTED_10baseT_Half |
11280                            SUPPORTED_10baseT_Full |
11281                            SUPPORTED_100baseT_Half |
11282                            SUPPORTED_100baseT_Full |
11283                            SUPPORTED_1000baseT_Full |
11284                            SUPPORTED_TP |
11285                            SUPPORTED_Autoneg |
11286                            SUPPORTED_Pause |
11287                            SUPPORTED_Asym_Pause),
11288         .media_type     = ETH_PHY_BASE_T,
11289         .ver_addr       = 0,
11290         .req_flow_ctrl  = 0,
11291         .req_line_speed = 0,
11292         .speed_cap_mask = 0,
11293         /* req_duplex = */0,
11294         /* rsrv = */0,
11295         .config_init    = (config_init_t)bnx2x_54618se_config_init,
11296         .read_status    = (read_status_t)bnx2x_54618se_read_status,
11297         .link_reset     = (link_reset_t)bnx2x_54618se_link_reset,
11298         .config_loopback = (config_loopback_t)bnx2x_54618se_config_loopback,
11299         .format_fw_ver  = (format_fw_ver_t)NULL,
11300         .hw_reset       = (hw_reset_t)NULL,
11301         .set_link_led   = (set_link_led_t)bnx2x_5461x_set_link_led,
11302         .phy_specific_func = (phy_specific_func_t)NULL
11303 };
11304 /*****************************************************************/
11305 /*                                                               */
11306 /* Populate the phy according. Main function: bnx2x_populate_phy   */
11307 /*                                                               */
11308 /*****************************************************************/
11309
11310 static void bnx2x_populate_preemphasis(struct bnx2x *bp, u32 shmem_base,
11311                                      struct bnx2x_phy *phy, u8 port,
11312                                      u8 phy_index)
11313 {
11314         /* Get the 4 lanes xgxs config rx and tx */
11315         u32 rx = 0, tx = 0, i;
11316         for (i = 0; i < 2; i++) {
11317                 /* INT_PHY and EXT_PHY1 share the same value location in
11318                  * the shmem. When num_phys is greater than 1, than this value
11319                  * applies only to EXT_PHY1
11320                  */
11321                 if (phy_index == INT_PHY || phy_index == EXT_PHY1) {
11322                         rx = REG_RD(bp, shmem_base +
11323                                     offsetof(struct shmem_region,
11324                           dev_info.port_hw_config[port].xgxs_config_rx[i<<1]));
11325
11326                         tx = REG_RD(bp, shmem_base +
11327                                     offsetof(struct shmem_region,
11328                           dev_info.port_hw_config[port].xgxs_config_tx[i<<1]));
11329                 } else {
11330                         rx = REG_RD(bp, shmem_base +
11331                                     offsetof(struct shmem_region,
11332                          dev_info.port_hw_config[port].xgxs_config2_rx[i<<1]));
11333
11334                         tx = REG_RD(bp, shmem_base +
11335                                     offsetof(struct shmem_region,
11336                          dev_info.port_hw_config[port].xgxs_config2_rx[i<<1]));
11337                 }
11338
11339                 phy->rx_preemphasis[i << 1] = ((rx>>16) & 0xffff);
11340                 phy->rx_preemphasis[(i << 1) + 1] = (rx & 0xffff);
11341
11342                 phy->tx_preemphasis[i << 1] = ((tx>>16) & 0xffff);
11343                 phy->tx_preemphasis[(i << 1) + 1] = (tx & 0xffff);
11344         }
11345 }
11346
11347 static u32 bnx2x_get_ext_phy_config(struct bnx2x *bp, u32 shmem_base,
11348                                     u8 phy_index, u8 port)
11349 {
11350         u32 ext_phy_config = 0;
11351         switch (phy_index) {
11352         case EXT_PHY1:
11353                 ext_phy_config = REG_RD(bp, shmem_base +
11354                                               offsetof(struct shmem_region,
11355                         dev_info.port_hw_config[port].external_phy_config));
11356                 break;
11357         case EXT_PHY2:
11358                 ext_phy_config = REG_RD(bp, shmem_base +
11359                                               offsetof(struct shmem_region,
11360                         dev_info.port_hw_config[port].external_phy_config2));
11361                 break;
11362         default:
11363                 DP(NETIF_MSG_LINK, "Invalid phy_index %d\n", phy_index);
11364                 return -EINVAL;
11365         }
11366
11367         return ext_phy_config;
11368 }
11369 static int bnx2x_populate_int_phy(struct bnx2x *bp, u32 shmem_base, u8 port,
11370                                   struct bnx2x_phy *phy)
11371 {
11372         u32 phy_addr;
11373         u32 chip_id;
11374         u32 switch_cfg = (REG_RD(bp, shmem_base +
11375                                        offsetof(struct shmem_region,
11376                         dev_info.port_feature_config[port].link_config)) &
11377                           PORT_FEATURE_CONNECTED_SWITCH_MASK);
11378         chip_id = (REG_RD(bp, MISC_REG_CHIP_NUM) << 16) |
11379                 ((REG_RD(bp, MISC_REG_CHIP_REV) & 0xf) << 12);
11380
11381         DP(NETIF_MSG_LINK, ":chip_id = 0x%x\n", chip_id);
11382         if (USES_WARPCORE(bp)) {
11383                 u32 serdes_net_if;
11384                 phy_addr = REG_RD(bp,
11385                                   MISC_REG_WC0_CTRL_PHY_ADDR);
11386                 *phy = phy_warpcore;
11387                 if (REG_RD(bp, MISC_REG_PORT4MODE_EN_OVWR) == 0x3)
11388                         phy->flags |= FLAGS_4_PORT_MODE;
11389                 else
11390                         phy->flags &= ~FLAGS_4_PORT_MODE;
11391                         /* Check Dual mode */
11392                 serdes_net_if = (REG_RD(bp, shmem_base +
11393                                         offsetof(struct shmem_region, dev_info.
11394                                         port_hw_config[port].default_cfg)) &
11395                                  PORT_HW_CFG_NET_SERDES_IF_MASK);
11396                 /* Set the appropriate supported and flags indications per
11397                  * interface type of the chip
11398                  */
11399                 switch (serdes_net_if) {
11400                 case PORT_HW_CFG_NET_SERDES_IF_SGMII:
11401                         phy->supported &= (SUPPORTED_10baseT_Half |
11402                                            SUPPORTED_10baseT_Full |
11403                                            SUPPORTED_100baseT_Half |
11404                                            SUPPORTED_100baseT_Full |
11405                                            SUPPORTED_1000baseT_Full |
11406                                            SUPPORTED_FIBRE |
11407                                            SUPPORTED_Autoneg |
11408                                            SUPPORTED_Pause |
11409                                            SUPPORTED_Asym_Pause);
11410                         phy->media_type = ETH_PHY_BASE_T;
11411                         break;
11412                 case PORT_HW_CFG_NET_SERDES_IF_XFI:
11413                         phy->media_type = ETH_PHY_XFP_FIBER;
11414                         break;
11415                 case PORT_HW_CFG_NET_SERDES_IF_SFI:
11416                         phy->supported &= (SUPPORTED_1000baseT_Full |
11417                                            SUPPORTED_10000baseT_Full |
11418                                            SUPPORTED_FIBRE |
11419                                            SUPPORTED_Pause |
11420                                            SUPPORTED_Asym_Pause);
11421                         phy->media_type = ETH_PHY_SFP_FIBER;
11422                         break;
11423                 case PORT_HW_CFG_NET_SERDES_IF_KR:
11424                         phy->media_type = ETH_PHY_KR;
11425                         phy->supported &= (SUPPORTED_1000baseT_Full |
11426                                            SUPPORTED_10000baseT_Full |
11427                                            SUPPORTED_FIBRE |
11428                                            SUPPORTED_Autoneg |
11429                                            SUPPORTED_Pause |
11430                                            SUPPORTED_Asym_Pause);
11431                         break;
11432                 case PORT_HW_CFG_NET_SERDES_IF_DXGXS:
11433                         phy->media_type = ETH_PHY_KR;
11434                         phy->flags |= FLAGS_WC_DUAL_MODE;
11435                         phy->supported &= (SUPPORTED_20000baseMLD2_Full |
11436                                            SUPPORTED_FIBRE |
11437                                            SUPPORTED_Pause |
11438                                            SUPPORTED_Asym_Pause);
11439                         break;
11440                 case PORT_HW_CFG_NET_SERDES_IF_KR2:
11441                         phy->media_type = ETH_PHY_KR;
11442                         phy->flags |= FLAGS_WC_DUAL_MODE;
11443                         phy->supported &= (SUPPORTED_20000baseKR2_Full |
11444                                            SUPPORTED_FIBRE |
11445                                            SUPPORTED_Pause |
11446                                            SUPPORTED_Asym_Pause);
11447                         break;
11448                 default:
11449                         DP(NETIF_MSG_LINK, "Unknown WC interface type 0x%x\n",
11450                                        serdes_net_if);
11451                         break;
11452                 }
11453
11454                 /* Enable MDC/MDIO work-around for E3 A0 since free running MDC
11455                  * was not set as expected. For B0, ECO will be enabled so there
11456                  * won't be an issue there
11457                  */
11458                 if (CHIP_REV(bp) == CHIP_REV_Ax)
11459                         phy->flags |= FLAGS_MDC_MDIO_WA;
11460                 else
11461                         phy->flags |= FLAGS_MDC_MDIO_WA_B0;
11462         } else {
11463                 switch (switch_cfg) {
11464                 case SWITCH_CFG_1G:
11465                         phy_addr = REG_RD(bp,
11466                                           NIG_REG_SERDES0_CTRL_PHY_ADDR +
11467                                           port * 0x10);
11468                         *phy = phy_serdes;
11469                         break;
11470                 case SWITCH_CFG_10G:
11471                         phy_addr = REG_RD(bp,
11472                                           NIG_REG_XGXS0_CTRL_PHY_ADDR +
11473                                           port * 0x18);
11474                         *phy = phy_xgxs;
11475                         break;
11476                 default:
11477                         DP(NETIF_MSG_LINK, "Invalid switch_cfg\n");
11478                         return -EINVAL;
11479                 }
11480         }
11481         phy->addr = (u8)phy_addr;
11482         phy->mdio_ctrl = bnx2x_get_emac_base(bp,
11483                                             SHARED_HW_CFG_MDC_MDIO_ACCESS1_BOTH,
11484                                             port);
11485         if (CHIP_IS_E2(bp))
11486                 phy->def_md_devad = E2_DEFAULT_PHY_DEV_ADDR;
11487         else
11488                 phy->def_md_devad = DEFAULT_PHY_DEV_ADDR;
11489
11490         DP(NETIF_MSG_LINK, "Internal phy port=%d, addr=0x%x, mdio_ctl=0x%x\n",
11491                    port, phy->addr, phy->mdio_ctrl);
11492
11493         bnx2x_populate_preemphasis(bp, shmem_base, phy, port, INT_PHY);
11494         return 0;
11495 }
11496
11497 static int bnx2x_populate_ext_phy(struct bnx2x *bp,
11498                                   u8 phy_index,
11499                                   u32 shmem_base,
11500                                   u32 shmem2_base,
11501                                   u8 port,
11502                                   struct bnx2x_phy *phy)
11503 {
11504         u32 ext_phy_config, phy_type, config2;
11505         u32 mdc_mdio_access = SHARED_HW_CFG_MDC_MDIO_ACCESS1_BOTH;
11506         ext_phy_config = bnx2x_get_ext_phy_config(bp, shmem_base,
11507                                                   phy_index, port);
11508         phy_type = XGXS_EXT_PHY_TYPE(ext_phy_config);
11509         /* Select the phy type */
11510         switch (phy_type) {
11511         case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073:
11512                 mdc_mdio_access = SHARED_HW_CFG_MDC_MDIO_ACCESS1_SWAPPED;
11513                 *phy = phy_8073;
11514                 break;
11515         case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8705:
11516                 *phy = phy_8705;
11517                 break;
11518         case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8706:
11519                 *phy = phy_8706;
11520                 break;
11521         case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8726:
11522                 mdc_mdio_access = SHARED_HW_CFG_MDC_MDIO_ACCESS1_EMAC1;
11523                 *phy = phy_8726;
11524                 break;
11525         case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727_NOC:
11526                 /* BCM8727_NOC => BCM8727 no over current */
11527                 mdc_mdio_access = SHARED_HW_CFG_MDC_MDIO_ACCESS1_EMAC1;
11528                 *phy = phy_8727;
11529                 phy->flags |= FLAGS_NOC;
11530                 break;
11531         case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8722:
11532         case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727:
11533                 mdc_mdio_access = SHARED_HW_CFG_MDC_MDIO_ACCESS1_EMAC1;
11534                 *phy = phy_8727;
11535                 break;
11536         case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8481:
11537                 *phy = phy_8481;
11538                 break;
11539         case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84823:
11540                 *phy = phy_84823;
11541                 break;
11542         case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84833:
11543                 *phy = phy_84833;
11544                 break;
11545         case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM54616:
11546         case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM54618SE:
11547                 *phy = phy_54618se;
11548                 break;
11549         case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_SFX7101:
11550                 *phy = phy_7101;
11551                 break;
11552         case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_FAILURE:
11553                 *phy = phy_null;
11554                 return -EINVAL;
11555         default:
11556                 *phy = phy_null;
11557                 /* In case external PHY wasn't found */
11558                 if ((phy_type != PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT) &&
11559                     (phy_type != PORT_HW_CFG_XGXS_EXT_PHY_TYPE_NOT_CONN))
11560                         return -EINVAL;
11561                 return 0;
11562         }
11563
11564         phy->addr = XGXS_EXT_PHY_ADDR(ext_phy_config);
11565         bnx2x_populate_preemphasis(bp, shmem_base, phy, port, phy_index);
11566
11567         /* The shmem address of the phy version is located on different
11568          * structures. In case this structure is too old, do not set
11569          * the address
11570          */
11571         config2 = REG_RD(bp, shmem_base + offsetof(struct shmem_region,
11572                                         dev_info.shared_hw_config.config2));
11573         if (phy_index == EXT_PHY1) {
11574                 phy->ver_addr = shmem_base + offsetof(struct shmem_region,
11575                                 port_mb[port].ext_phy_fw_version);
11576
11577                 /* Check specific mdc mdio settings */
11578                 if (config2 & SHARED_HW_CFG_MDC_MDIO_ACCESS1_MASK)
11579                         mdc_mdio_access = config2 &
11580                         SHARED_HW_CFG_MDC_MDIO_ACCESS1_MASK;
11581         } else {
11582                 u32 size = REG_RD(bp, shmem2_base);
11583
11584                 if (size >
11585                     offsetof(struct shmem2_region, ext_phy_fw_version2)) {
11586                         phy->ver_addr = shmem2_base +
11587                             offsetof(struct shmem2_region,
11588                                      ext_phy_fw_version2[port]);
11589                 }
11590                 /* Check specific mdc mdio settings */
11591                 if (config2 & SHARED_HW_CFG_MDC_MDIO_ACCESS2_MASK)
11592                         mdc_mdio_access = (config2 &
11593                         SHARED_HW_CFG_MDC_MDIO_ACCESS2_MASK) >>
11594                         (SHARED_HW_CFG_MDC_MDIO_ACCESS2_SHIFT -
11595                          SHARED_HW_CFG_MDC_MDIO_ACCESS1_SHIFT);
11596         }
11597         phy->mdio_ctrl = bnx2x_get_emac_base(bp, mdc_mdio_access, port);
11598
11599         if ((phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84833) &&
11600             (phy->ver_addr)) {
11601                 /* Remove 100Mb link supported for BCM84833 when phy fw
11602                  * version lower than or equal to 1.39
11603                  */
11604                 u32 raw_ver = REG_RD(bp, phy->ver_addr);
11605                 if (((raw_ver & 0x7F) <= 39) &&
11606                     (((raw_ver & 0xF80) >> 7) <= 1))
11607                         phy->supported &= ~(SUPPORTED_100baseT_Half |
11608                                             SUPPORTED_100baseT_Full);
11609         }
11610
11611         /* In case mdc/mdio_access of the external phy is different than the
11612          * mdc/mdio access of the XGXS, a HW lock must be taken in each access
11613          * to prevent one port interfere with another port's CL45 operations.
11614          */
11615         if (mdc_mdio_access != SHARED_HW_CFG_MDC_MDIO_ACCESS1_BOTH)
11616                 phy->flags |= FLAGS_HW_LOCK_REQUIRED;
11617         DP(NETIF_MSG_LINK, "phy_type 0x%x port %d found in index %d\n",
11618                    phy_type, port, phy_index);
11619         DP(NETIF_MSG_LINK, "             addr=0x%x, mdio_ctl=0x%x\n",
11620                    phy->addr, phy->mdio_ctrl);
11621         return 0;
11622 }
11623
11624 static int bnx2x_populate_phy(struct bnx2x *bp, u8 phy_index, u32 shmem_base,
11625                               u32 shmem2_base, u8 port, struct bnx2x_phy *phy)
11626 {
11627         int status = 0;
11628         phy->type = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_NOT_CONN;
11629         if (phy_index == INT_PHY)
11630                 return bnx2x_populate_int_phy(bp, shmem_base, port, phy);
11631         status = bnx2x_populate_ext_phy(bp, phy_index, shmem_base, shmem2_base,
11632                                         port, phy);
11633         return status;
11634 }
11635
11636 static void bnx2x_phy_def_cfg(struct link_params *params,
11637                               struct bnx2x_phy *phy,
11638                               u8 phy_index)
11639 {
11640         struct bnx2x *bp = params->bp;
11641         u32 link_config;
11642         /* Populate the default phy configuration for MF mode */
11643         if (phy_index == EXT_PHY2) {
11644                 link_config = REG_RD(bp, params->shmem_base +
11645                                      offsetof(struct shmem_region, dev_info.
11646                         port_feature_config[params->port].link_config2));
11647                 phy->speed_cap_mask = REG_RD(bp, params->shmem_base +
11648                                              offsetof(struct shmem_region,
11649                                                       dev_info.
11650                         port_hw_config[params->port].speed_capability_mask2));
11651         } else {
11652                 link_config = REG_RD(bp, params->shmem_base +
11653                                      offsetof(struct shmem_region, dev_info.
11654                                 port_feature_config[params->port].link_config));
11655                 phy->speed_cap_mask = REG_RD(bp, params->shmem_base +
11656                                              offsetof(struct shmem_region,
11657                                                       dev_info.
11658                         port_hw_config[params->port].speed_capability_mask));
11659         }
11660         DP(NETIF_MSG_LINK,
11661            "Default config phy idx %x cfg 0x%x speed_cap_mask 0x%x\n",
11662            phy_index, link_config, phy->speed_cap_mask);
11663
11664         phy->req_duplex = DUPLEX_FULL;
11665         switch (link_config  & PORT_FEATURE_LINK_SPEED_MASK) {
11666         case PORT_FEATURE_LINK_SPEED_10M_HALF:
11667                 phy->req_duplex = DUPLEX_HALF;
11668         case PORT_FEATURE_LINK_SPEED_10M_FULL:
11669                 phy->req_line_speed = SPEED_10;
11670                 break;
11671         case PORT_FEATURE_LINK_SPEED_100M_HALF:
11672                 phy->req_duplex = DUPLEX_HALF;
11673         case PORT_FEATURE_LINK_SPEED_100M_FULL:
11674                 phy->req_line_speed = SPEED_100;
11675                 break;
11676         case PORT_FEATURE_LINK_SPEED_1G:
11677                 phy->req_line_speed = SPEED_1000;
11678                 break;
11679         case PORT_FEATURE_LINK_SPEED_2_5G:
11680                 phy->req_line_speed = SPEED_2500;
11681                 break;
11682         case PORT_FEATURE_LINK_SPEED_10G_CX4:
11683                 phy->req_line_speed = SPEED_10000;
11684                 break;
11685         default:
11686                 phy->req_line_speed = SPEED_AUTO_NEG;
11687                 break;
11688         }
11689
11690         switch (link_config  & PORT_FEATURE_FLOW_CONTROL_MASK) {
11691         case PORT_FEATURE_FLOW_CONTROL_AUTO:
11692                 phy->req_flow_ctrl = BNX2X_FLOW_CTRL_AUTO;
11693                 break;
11694         case PORT_FEATURE_FLOW_CONTROL_TX:
11695                 phy->req_flow_ctrl = BNX2X_FLOW_CTRL_TX;
11696                 break;
11697         case PORT_FEATURE_FLOW_CONTROL_RX:
11698                 phy->req_flow_ctrl = BNX2X_FLOW_CTRL_RX;
11699                 break;
11700         case PORT_FEATURE_FLOW_CONTROL_BOTH:
11701                 phy->req_flow_ctrl = BNX2X_FLOW_CTRL_BOTH;
11702                 break;
11703         default:
11704                 phy->req_flow_ctrl = BNX2X_FLOW_CTRL_NONE;
11705                 break;
11706         }
11707 }
11708
11709 u32 bnx2x_phy_selection(struct link_params *params)
11710 {
11711         u32 phy_config_swapped, prio_cfg;
11712         u32 return_cfg = PORT_HW_CFG_PHY_SELECTION_HARDWARE_DEFAULT;
11713
11714         phy_config_swapped = params->multi_phy_config &
11715                 PORT_HW_CFG_PHY_SWAPPED_ENABLED;
11716
11717         prio_cfg = params->multi_phy_config &
11718                         PORT_HW_CFG_PHY_SELECTION_MASK;
11719
11720         if (phy_config_swapped) {
11721                 switch (prio_cfg) {
11722                 case PORT_HW_CFG_PHY_SELECTION_FIRST_PHY_PRIORITY:
11723                      return_cfg = PORT_HW_CFG_PHY_SELECTION_SECOND_PHY_PRIORITY;
11724                      break;
11725                 case PORT_HW_CFG_PHY_SELECTION_SECOND_PHY_PRIORITY:
11726                      return_cfg = PORT_HW_CFG_PHY_SELECTION_FIRST_PHY_PRIORITY;
11727                      break;
11728                 case PORT_HW_CFG_PHY_SELECTION_SECOND_PHY:
11729                      return_cfg = PORT_HW_CFG_PHY_SELECTION_FIRST_PHY;
11730                      break;
11731                 case PORT_HW_CFG_PHY_SELECTION_FIRST_PHY:
11732                      return_cfg = PORT_HW_CFG_PHY_SELECTION_SECOND_PHY;
11733                      break;
11734                 }
11735         } else
11736                 return_cfg = prio_cfg;
11737
11738         return return_cfg;
11739 }
11740
11741
11742 int bnx2x_phy_probe(struct link_params *params)
11743 {
11744         u8 phy_index, actual_phy_idx;
11745         u32 phy_config_swapped, sync_offset, media_types;
11746         struct bnx2x *bp = params->bp;
11747         struct bnx2x_phy *phy;
11748         params->num_phys = 0;
11749         DP(NETIF_MSG_LINK, "Begin phy probe\n");
11750         phy_config_swapped = params->multi_phy_config &
11751                 PORT_HW_CFG_PHY_SWAPPED_ENABLED;
11752
11753         for (phy_index = INT_PHY; phy_index < MAX_PHYS;
11754               phy_index++) {
11755                 actual_phy_idx = phy_index;
11756                 if (phy_config_swapped) {
11757                         if (phy_index == EXT_PHY1)
11758                                 actual_phy_idx = EXT_PHY2;
11759                         else if (phy_index == EXT_PHY2)
11760                                 actual_phy_idx = EXT_PHY1;
11761                 }
11762                 DP(NETIF_MSG_LINK, "phy_config_swapped %x, phy_index %x,"
11763                                " actual_phy_idx %x\n", phy_config_swapped,
11764                            phy_index, actual_phy_idx);
11765                 phy = &params->phy[actual_phy_idx];
11766                 if (bnx2x_populate_phy(bp, phy_index, params->shmem_base,
11767                                        params->shmem2_base, params->port,
11768                                        phy) != 0) {
11769                         params->num_phys = 0;
11770                         DP(NETIF_MSG_LINK, "phy probe failed in phy index %d\n",
11771                                    phy_index);
11772                         for (phy_index = INT_PHY;
11773                               phy_index < MAX_PHYS;
11774                               phy_index++)
11775                                 *phy = phy_null;
11776                         return -EINVAL;
11777                 }
11778                 if (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_NOT_CONN)
11779                         break;
11780
11781                 if (params->feature_config_flags &
11782                     FEATURE_CONFIG_DISABLE_REMOTE_FAULT_DET)
11783                         phy->flags &= ~FLAGS_TX_ERROR_CHECK;
11784
11785                 sync_offset = params->shmem_base +
11786                         offsetof(struct shmem_region,
11787                         dev_info.port_hw_config[params->port].media_type);
11788                 media_types = REG_RD(bp, sync_offset);
11789
11790                 /* Update media type for non-PMF sync only for the first time
11791                  * In case the media type changes afterwards, it will be updated
11792                  * using the update_status function
11793                  */
11794                 if ((media_types & (PORT_HW_CFG_MEDIA_TYPE_PHY0_MASK <<
11795                                     (PORT_HW_CFG_MEDIA_TYPE_PHY1_SHIFT *
11796                                      actual_phy_idx))) == 0) {
11797                         media_types |= ((phy->media_type &
11798                                         PORT_HW_CFG_MEDIA_TYPE_PHY0_MASK) <<
11799                                 (PORT_HW_CFG_MEDIA_TYPE_PHY1_SHIFT *
11800                                  actual_phy_idx));
11801                 }
11802                 REG_WR(bp, sync_offset, media_types);
11803
11804                 bnx2x_phy_def_cfg(params, phy, phy_index);
11805                 params->num_phys++;
11806         }
11807
11808         DP(NETIF_MSG_LINK, "End phy probe. #phys found %x\n", params->num_phys);
11809         return 0;
11810 }
11811
11812 void bnx2x_init_bmac_loopback(struct link_params *params,
11813                               struct link_vars *vars)
11814 {
11815         struct bnx2x *bp = params->bp;
11816                 vars->link_up = 1;
11817                 vars->line_speed = SPEED_10000;
11818                 vars->duplex = DUPLEX_FULL;
11819                 vars->flow_ctrl = BNX2X_FLOW_CTRL_NONE;
11820                 vars->mac_type = MAC_TYPE_BMAC;
11821
11822                 vars->phy_flags = PHY_XGXS_FLAG;
11823
11824                 bnx2x_xgxs_deassert(params);
11825
11826                 /* set bmac loopback */
11827                 bnx2x_bmac_enable(params, vars, 1);
11828
11829                 REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE + params->port*4, 0);
11830 }
11831
11832 void bnx2x_init_emac_loopback(struct link_params *params,
11833                               struct link_vars *vars)
11834 {
11835         struct bnx2x *bp = params->bp;
11836                 vars->link_up = 1;
11837                 vars->line_speed = SPEED_1000;
11838                 vars->duplex = DUPLEX_FULL;
11839                 vars->flow_ctrl = BNX2X_FLOW_CTRL_NONE;
11840                 vars->mac_type = MAC_TYPE_EMAC;
11841
11842                 vars->phy_flags = PHY_XGXS_FLAG;
11843
11844                 bnx2x_xgxs_deassert(params);
11845                 /* set bmac loopback */
11846                 bnx2x_emac_enable(params, vars, 1);
11847                 bnx2x_emac_program(params, vars);
11848                 REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE + params->port*4, 0);
11849 }
11850
11851 void bnx2x_init_xmac_loopback(struct link_params *params,
11852                               struct link_vars *vars)
11853 {
11854         struct bnx2x *bp = params->bp;
11855         vars->link_up = 1;
11856         if (!params->req_line_speed[0])
11857                 vars->line_speed = SPEED_10000;
11858         else
11859                 vars->line_speed = params->req_line_speed[0];
11860         vars->duplex = DUPLEX_FULL;
11861         vars->flow_ctrl = BNX2X_FLOW_CTRL_NONE;
11862         vars->mac_type = MAC_TYPE_XMAC;
11863         vars->phy_flags = PHY_XGXS_FLAG;
11864         /* Set WC to loopback mode since link is required to provide clock
11865          * to the XMAC in 20G mode
11866          */
11867         bnx2x_set_aer_mmd(params, &params->phy[0]);
11868         bnx2x_warpcore_reset_lane(bp, &params->phy[0], 0);
11869         params->phy[INT_PHY].config_loopback(
11870                         &params->phy[INT_PHY],
11871                         params);
11872
11873         bnx2x_xmac_enable(params, vars, 1);
11874         REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE + params->port*4, 0);
11875 }
11876
11877 void bnx2x_init_umac_loopback(struct link_params *params,
11878                               struct link_vars *vars)
11879 {
11880         struct bnx2x *bp = params->bp;
11881         vars->link_up = 1;
11882         vars->line_speed = SPEED_1000;
11883         vars->duplex = DUPLEX_FULL;
11884         vars->flow_ctrl = BNX2X_FLOW_CTRL_NONE;
11885         vars->mac_type = MAC_TYPE_UMAC;
11886         vars->phy_flags = PHY_XGXS_FLAG;
11887         bnx2x_umac_enable(params, vars, 1);
11888
11889         REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE + params->port*4, 0);
11890 }
11891
11892 void bnx2x_init_xgxs_loopback(struct link_params *params,
11893                               struct link_vars *vars)
11894 {
11895         struct bnx2x *bp = params->bp;
11896                 vars->link_up = 1;
11897                 vars->flow_ctrl = BNX2X_FLOW_CTRL_NONE;
11898                 vars->duplex = DUPLEX_FULL;
11899         if (params->req_line_speed[0] == SPEED_1000)
11900                         vars->line_speed = SPEED_1000;
11901         else
11902                         vars->line_speed = SPEED_10000;
11903
11904         if (!USES_WARPCORE(bp))
11905                 bnx2x_xgxs_deassert(params);
11906         bnx2x_link_initialize(params, vars);
11907
11908         if (params->req_line_speed[0] == SPEED_1000) {
11909                 if (USES_WARPCORE(bp))
11910                         bnx2x_umac_enable(params, vars, 0);
11911                 else {
11912                         bnx2x_emac_program(params, vars);
11913                         bnx2x_emac_enable(params, vars, 0);
11914                 }
11915         } else {
11916                 if (USES_WARPCORE(bp))
11917                         bnx2x_xmac_enable(params, vars, 0);
11918                 else
11919                         bnx2x_bmac_enable(params, vars, 0);
11920         }
11921
11922                 if (params->loopback_mode == LOOPBACK_XGXS) {
11923                         /* set 10G XGXS loopback */
11924                         params->phy[INT_PHY].config_loopback(
11925                                 &params->phy[INT_PHY],
11926                                 params);
11927
11928                 } else {
11929                         /* set external phy loopback */
11930                         u8 phy_index;
11931                         for (phy_index = EXT_PHY1;
11932                               phy_index < params->num_phys; phy_index++) {
11933                                 if (params->phy[phy_index].config_loopback)
11934                                         params->phy[phy_index].config_loopback(
11935                                                 &params->phy[phy_index],
11936                                                 params);
11937                         }
11938                 }
11939                 REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE + params->port*4, 0);
11940
11941         bnx2x_set_led(params, vars, LED_MODE_OPER, vars->line_speed);
11942 }
11943
11944 int bnx2x_phy_init(struct link_params *params, struct link_vars *vars)
11945 {
11946         struct bnx2x *bp = params->bp;
11947         DP(NETIF_MSG_LINK, "Phy Initialization started\n");
11948         DP(NETIF_MSG_LINK, "(1) req_speed %d, req_flowctrl %d\n",
11949                    params->req_line_speed[0], params->req_flow_ctrl[0]);
11950         DP(NETIF_MSG_LINK, "(2) req_speed %d, req_flowctrl %d\n",
11951                    params->req_line_speed[1], params->req_flow_ctrl[1]);
11952         vars->link_status = 0;
11953         vars->phy_link_up = 0;
11954         vars->link_up = 0;
11955         vars->line_speed = 0;
11956         vars->duplex = DUPLEX_FULL;
11957         vars->flow_ctrl = BNX2X_FLOW_CTRL_NONE;
11958         vars->mac_type = MAC_TYPE_NONE;
11959         vars->phy_flags = 0;
11960
11961         /* disable attentions */
11962         bnx2x_bits_dis(bp, NIG_REG_MASK_INTERRUPT_PORT0 + params->port*4,
11963                        (NIG_MASK_XGXS0_LINK_STATUS |
11964                         NIG_MASK_XGXS0_LINK10G |
11965                         NIG_MASK_SERDES0_LINK_STATUS |
11966                         NIG_MASK_MI_INT));
11967
11968         bnx2x_emac_init(params, vars);
11969
11970         if (params->feature_config_flags & FEATURE_CONFIG_PFC_ENABLED)
11971                 vars->link_status |= LINK_STATUS_PFC_ENABLED;
11972
11973         if (params->num_phys == 0) {
11974                 DP(NETIF_MSG_LINK, "No phy found for initialization !!\n");
11975                 return -EINVAL;
11976         }
11977         set_phy_vars(params, vars);
11978
11979         DP(NETIF_MSG_LINK, "Num of phys on board: %d\n", params->num_phys);
11980         switch (params->loopback_mode) {
11981         case LOOPBACK_BMAC:
11982                 bnx2x_init_bmac_loopback(params, vars);
11983                 break;
11984         case LOOPBACK_EMAC:
11985                 bnx2x_init_emac_loopback(params, vars);
11986                 break;
11987         case LOOPBACK_XMAC:
11988                 bnx2x_init_xmac_loopback(params, vars);
11989                 break;
11990         case LOOPBACK_UMAC:
11991                 bnx2x_init_umac_loopback(params, vars);
11992                 break;
11993         case LOOPBACK_XGXS:
11994         case LOOPBACK_EXT_PHY:
11995                 bnx2x_init_xgxs_loopback(params, vars);
11996                 break;
11997         default:
11998                 if (!CHIP_IS_E3(bp)) {
11999                         if (params->switch_cfg == SWITCH_CFG_10G)
12000                                 bnx2x_xgxs_deassert(params);
12001                         else
12002                                 bnx2x_serdes_deassert(bp, params->port);
12003                 }
12004                 bnx2x_link_initialize(params, vars);
12005                 msleep(30);
12006                 bnx2x_link_int_enable(params);
12007                 break;
12008         }
12009         bnx2x_update_mng(params, vars->link_status);
12010         return 0;
12011 }
12012
12013 int bnx2x_link_reset(struct link_params *params, struct link_vars *vars,
12014                      u8 reset_ext_phy)
12015 {
12016         struct bnx2x *bp = params->bp;
12017         u8 phy_index, port = params->port, clear_latch_ind = 0;
12018         DP(NETIF_MSG_LINK, "Resetting the link of port %d\n", port);
12019         /* disable attentions */
12020         vars->link_status = 0;
12021         bnx2x_update_mng(params, vars->link_status);
12022         bnx2x_bits_dis(bp, NIG_REG_MASK_INTERRUPT_PORT0 + port*4,
12023                        (NIG_MASK_XGXS0_LINK_STATUS |
12024                         NIG_MASK_XGXS0_LINK10G |
12025                         NIG_MASK_SERDES0_LINK_STATUS |
12026                         NIG_MASK_MI_INT));
12027
12028         /* activate nig drain */
12029         REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE + port*4, 1);
12030
12031         /* disable nig egress interface */
12032         if (!CHIP_IS_E3(bp)) {
12033                 REG_WR(bp, NIG_REG_BMAC0_OUT_EN + port*4, 0);
12034                 REG_WR(bp, NIG_REG_EGRESS_EMAC0_OUT_EN + port*4, 0);
12035         }
12036
12037         /* Stop BigMac rx */
12038         if (!CHIP_IS_E3(bp))
12039                 bnx2x_bmac_rx_disable(bp, port);
12040         else {
12041                 bnx2x_xmac_disable(params);
12042                 bnx2x_umac_disable(params);
12043         }
12044         /* disable emac */
12045         if (!CHIP_IS_E3(bp))
12046                 REG_WR(bp, NIG_REG_NIG_EMAC0_EN + port*4, 0);
12047
12048         msleep(10);
12049         /* The PHY reset is controlled by GPIO 1
12050          * Hold it as vars low
12051          */
12052          /* clear link led */
12053         bnx2x_set_mdio_clk(bp, params->chip_id, port);
12054         bnx2x_set_led(params, vars, LED_MODE_OFF, 0);
12055
12056         if (reset_ext_phy) {
12057                 for (phy_index = EXT_PHY1; phy_index < params->num_phys;
12058                       phy_index++) {
12059                         if (params->phy[phy_index].link_reset) {
12060                                 bnx2x_set_aer_mmd(params,
12061                                                   &params->phy[phy_index]);
12062                                 params->phy[phy_index].link_reset(
12063                                         &params->phy[phy_index],
12064                                         params);
12065                         }
12066                         if (params->phy[phy_index].flags &
12067                             FLAGS_REARM_LATCH_SIGNAL)
12068                                 clear_latch_ind = 1;
12069                 }
12070         }
12071
12072         if (clear_latch_ind) {
12073                 /* Clear latching indication */
12074                 bnx2x_rearm_latch_signal(bp, port, 0);
12075                 bnx2x_bits_dis(bp, NIG_REG_LATCH_BC_0 + port*4,
12076                                1 << NIG_LATCH_BC_ENABLE_MI_INT);
12077         }
12078         if (params->phy[INT_PHY].link_reset)
12079                 params->phy[INT_PHY].link_reset(
12080                         &params->phy[INT_PHY], params);
12081
12082         /* disable nig ingress interface */
12083         if (!CHIP_IS_E3(bp)) {
12084                 /* reset BigMac */
12085                 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR,
12086                        (MISC_REGISTERS_RESET_REG_2_RST_BMAC0 << port));
12087                 REG_WR(bp, NIG_REG_BMAC0_IN_EN + port*4, 0);
12088                 REG_WR(bp, NIG_REG_EMAC0_IN_EN + port*4, 0);
12089         } else {
12090                 u32 xmac_base = (params->port) ? GRCBASE_XMAC1 : GRCBASE_XMAC0;
12091                 bnx2x_set_xumac_nig(params, 0, 0);
12092                 if (REG_RD(bp, MISC_REG_RESET_REG_2) &
12093                     MISC_REGISTERS_RESET_REG_2_XMAC)
12094                         REG_WR(bp, xmac_base + XMAC_REG_CTRL,
12095                                XMAC_CTRL_REG_SOFT_RESET);
12096         }
12097         vars->link_up = 0;
12098         vars->phy_flags = 0;
12099         return 0;
12100 }
12101
12102 /****************************************************************************/
12103 /*                              Common function                             */
12104 /****************************************************************************/
12105 static int bnx2x_8073_common_init_phy(struct bnx2x *bp,
12106                                       u32 shmem_base_path[],
12107                                       u32 shmem2_base_path[], u8 phy_index,
12108                                       u32 chip_id)
12109 {
12110         struct bnx2x_phy phy[PORT_MAX];
12111         struct bnx2x_phy *phy_blk[PORT_MAX];
12112         u16 val;
12113         s8 port = 0;
12114         s8 port_of_path = 0;
12115         u32 swap_val, swap_override;
12116         swap_val = REG_RD(bp,  NIG_REG_PORT_SWAP);
12117         swap_override = REG_RD(bp,  NIG_REG_STRAP_OVERRIDE);
12118         port ^= (swap_val && swap_override);
12119         bnx2x_ext_phy_hw_reset(bp, port);
12120         /* PART1 - Reset both phys */
12121         for (port = PORT_MAX - 1; port >= PORT_0; port--) {
12122                 u32 shmem_base, shmem2_base;
12123                 /* In E2, same phy is using for port0 of the two paths */
12124                 if (CHIP_IS_E1x(bp)) {
12125                         shmem_base = shmem_base_path[0];
12126                         shmem2_base = shmem2_base_path[0];
12127                         port_of_path = port;
12128                 } else {
12129                         shmem_base = shmem_base_path[port];
12130                         shmem2_base = shmem2_base_path[port];
12131                         port_of_path = 0;
12132                 }
12133
12134                 /* Extract the ext phy address for the port */
12135                 if (bnx2x_populate_phy(bp, phy_index, shmem_base, shmem2_base,
12136                                        port_of_path, &phy[port]) !=
12137                     0) {
12138                         DP(NETIF_MSG_LINK, "populate_phy failed\n");
12139                         return -EINVAL;
12140                 }
12141                 /* disable attentions */
12142                 bnx2x_bits_dis(bp, NIG_REG_MASK_INTERRUPT_PORT0 +
12143                                port_of_path*4,
12144                                (NIG_MASK_XGXS0_LINK_STATUS |
12145                                 NIG_MASK_XGXS0_LINK10G |
12146                                 NIG_MASK_SERDES0_LINK_STATUS |
12147                                 NIG_MASK_MI_INT));
12148
12149                 /* Need to take the phy out of low power mode in order
12150                  * to write to access its registers
12151                  */
12152                 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_2,
12153                                MISC_REGISTERS_GPIO_OUTPUT_HIGH,
12154                                port);
12155
12156                 /* Reset the phy */
12157                 bnx2x_cl45_write(bp, &phy[port],
12158                                  MDIO_PMA_DEVAD,
12159                                  MDIO_PMA_REG_CTRL,
12160                                  1<<15);
12161         }
12162
12163         /* Add delay of 150ms after reset */
12164         msleep(150);
12165
12166         if (phy[PORT_0].addr & 0x1) {
12167                 phy_blk[PORT_0] = &(phy[PORT_1]);
12168                 phy_blk[PORT_1] = &(phy[PORT_0]);
12169         } else {
12170                 phy_blk[PORT_0] = &(phy[PORT_0]);
12171                 phy_blk[PORT_1] = &(phy[PORT_1]);
12172         }
12173
12174         /* PART2 - Download firmware to both phys */
12175         for (port = PORT_MAX - 1; port >= PORT_0; port--) {
12176                 if (CHIP_IS_E1x(bp))
12177                         port_of_path = port;
12178                 else
12179                         port_of_path = 0;
12180
12181                 DP(NETIF_MSG_LINK, "Loading spirom for phy address 0x%x\n",
12182                            phy_blk[port]->addr);
12183                 if (bnx2x_8073_8727_external_rom_boot(bp, phy_blk[port],
12184                                                       port_of_path))
12185                         return -EINVAL;
12186
12187                 /* Only set bit 10 = 1 (Tx power down) */
12188                 bnx2x_cl45_read(bp, phy_blk[port],
12189                                 MDIO_PMA_DEVAD,
12190                                 MDIO_PMA_REG_TX_POWER_DOWN, &val);
12191
12192                 /* Phase1 of TX_POWER_DOWN reset */
12193                 bnx2x_cl45_write(bp, phy_blk[port],
12194                                  MDIO_PMA_DEVAD,
12195                                  MDIO_PMA_REG_TX_POWER_DOWN,
12196                                  (val | 1<<10));
12197         }
12198
12199         /* Toggle Transmitter: Power down and then up with 600ms delay
12200          * between
12201          */
12202         msleep(600);
12203
12204         /* PART3 - complete TX_POWER_DOWN process, and set GPIO2 back to low */
12205         for (port = PORT_MAX - 1; port >= PORT_0; port--) {
12206                 /* Phase2 of POWER_DOWN_RESET */
12207                 /* Release bit 10 (Release Tx power down) */
12208                 bnx2x_cl45_read(bp, phy_blk[port],
12209                                 MDIO_PMA_DEVAD,
12210                                 MDIO_PMA_REG_TX_POWER_DOWN, &val);
12211
12212                 bnx2x_cl45_write(bp, phy_blk[port],
12213                                 MDIO_PMA_DEVAD,
12214                                 MDIO_PMA_REG_TX_POWER_DOWN, (val & (~(1<<10))));
12215                 msleep(15);
12216
12217                 /* Read modify write the SPI-ROM version select register */
12218                 bnx2x_cl45_read(bp, phy_blk[port],
12219                                 MDIO_PMA_DEVAD,
12220                                 MDIO_PMA_REG_EDC_FFE_MAIN, &val);
12221                 bnx2x_cl45_write(bp, phy_blk[port],
12222                                  MDIO_PMA_DEVAD,
12223                                  MDIO_PMA_REG_EDC_FFE_MAIN, (val | (1<<12)));
12224
12225                 /* set GPIO2 back to LOW */
12226                 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_2,
12227                                MISC_REGISTERS_GPIO_OUTPUT_LOW, port);
12228         }
12229         return 0;
12230 }
12231 static int bnx2x_8726_common_init_phy(struct bnx2x *bp,
12232                                       u32 shmem_base_path[],
12233                                       u32 shmem2_base_path[], u8 phy_index,
12234                                       u32 chip_id)
12235 {
12236         u32 val;
12237         s8 port;
12238         struct bnx2x_phy phy;
12239         /* Use port1 because of the static port-swap */
12240         /* Enable the module detection interrupt */
12241         val = REG_RD(bp, MISC_REG_GPIO_EVENT_EN);
12242         val |= ((1<<MISC_REGISTERS_GPIO_3)|
12243                 (1<<(MISC_REGISTERS_GPIO_3 + MISC_REGISTERS_GPIO_PORT_SHIFT)));
12244         REG_WR(bp, MISC_REG_GPIO_EVENT_EN, val);
12245
12246         bnx2x_ext_phy_hw_reset(bp, 0);
12247         msleep(5);
12248         for (port = 0; port < PORT_MAX; port++) {
12249                 u32 shmem_base, shmem2_base;
12250
12251                 /* In E2, same phy is using for port0 of the two paths */
12252                 if (CHIP_IS_E1x(bp)) {
12253                         shmem_base = shmem_base_path[0];
12254                         shmem2_base = shmem2_base_path[0];
12255                 } else {
12256                         shmem_base = shmem_base_path[port];
12257                         shmem2_base = shmem2_base_path[port];
12258                 }
12259                 /* Extract the ext phy address for the port */
12260                 if (bnx2x_populate_phy(bp, phy_index, shmem_base, shmem2_base,
12261                                        port, &phy) !=
12262                     0) {
12263                         DP(NETIF_MSG_LINK, "populate phy failed\n");
12264                         return -EINVAL;
12265                 }
12266
12267                 /* Reset phy*/
12268                 bnx2x_cl45_write(bp, &phy,
12269                                  MDIO_PMA_DEVAD, MDIO_PMA_REG_GEN_CTRL, 0x0001);
12270
12271
12272                 /* Set fault module detected LED on */
12273                 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_0,
12274                                MISC_REGISTERS_GPIO_HIGH,
12275                                port);
12276         }
12277
12278         return 0;
12279 }
12280 static void bnx2x_get_ext_phy_reset_gpio(struct bnx2x *bp, u32 shmem_base,
12281                                          u8 *io_gpio, u8 *io_port)
12282 {
12283
12284         u32 phy_gpio_reset = REG_RD(bp, shmem_base +
12285                                           offsetof(struct shmem_region,
12286                                 dev_info.port_hw_config[PORT_0].default_cfg));
12287         switch (phy_gpio_reset) {
12288         case PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO0_P0:
12289                 *io_gpio = 0;
12290                 *io_port = 0;
12291                 break;
12292         case PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO1_P0:
12293                 *io_gpio = 1;
12294                 *io_port = 0;
12295                 break;
12296         case PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO2_P0:
12297                 *io_gpio = 2;
12298                 *io_port = 0;
12299                 break;
12300         case PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO3_P0:
12301                 *io_gpio = 3;
12302                 *io_port = 0;
12303                 break;
12304         case PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO0_P1:
12305                 *io_gpio = 0;
12306                 *io_port = 1;
12307                 break;
12308         case PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO1_P1:
12309                 *io_gpio = 1;
12310                 *io_port = 1;
12311                 break;
12312         case PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO2_P1:
12313                 *io_gpio = 2;
12314                 *io_port = 1;
12315                 break;
12316         case PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO3_P1:
12317                 *io_gpio = 3;
12318                 *io_port = 1;
12319                 break;
12320         default:
12321                 /* Don't override the io_gpio and io_port */
12322                 break;
12323         }
12324 }
12325
12326 static int bnx2x_8727_common_init_phy(struct bnx2x *bp,
12327                                       u32 shmem_base_path[],
12328                                       u32 shmem2_base_path[], u8 phy_index,
12329                                       u32 chip_id)
12330 {
12331         s8 port, reset_gpio;
12332         u32 swap_val, swap_override;
12333         struct bnx2x_phy phy[PORT_MAX];
12334         struct bnx2x_phy *phy_blk[PORT_MAX];
12335         s8 port_of_path;
12336         swap_val = REG_RD(bp, NIG_REG_PORT_SWAP);
12337         swap_override = REG_RD(bp, NIG_REG_STRAP_OVERRIDE);
12338
12339         reset_gpio = MISC_REGISTERS_GPIO_1;
12340         port = 1;
12341
12342         /* Retrieve the reset gpio/port which control the reset.
12343          * Default is GPIO1, PORT1
12344          */
12345         bnx2x_get_ext_phy_reset_gpio(bp, shmem_base_path[0],
12346                                      (u8 *)&reset_gpio, (u8 *)&port);
12347
12348         /* Calculate the port based on port swap */
12349         port ^= (swap_val && swap_override);
12350
12351         /* Initiate PHY reset*/
12352         bnx2x_set_gpio(bp, reset_gpio, MISC_REGISTERS_GPIO_OUTPUT_LOW,
12353                        port);
12354         msleep(1);
12355         bnx2x_set_gpio(bp, reset_gpio, MISC_REGISTERS_GPIO_OUTPUT_HIGH,
12356                        port);
12357
12358         msleep(5);
12359
12360         /* PART1 - Reset both phys */
12361         for (port = PORT_MAX - 1; port >= PORT_0; port--) {
12362                 u32 shmem_base, shmem2_base;
12363
12364                 /* In E2, same phy is using for port0 of the two paths */
12365                 if (CHIP_IS_E1x(bp)) {
12366                         shmem_base = shmem_base_path[0];
12367                         shmem2_base = shmem2_base_path[0];
12368                         port_of_path = port;
12369                 } else {
12370                         shmem_base = shmem_base_path[port];
12371                         shmem2_base = shmem2_base_path[port];
12372                         port_of_path = 0;
12373                 }
12374
12375                 /* Extract the ext phy address for the port */
12376                 if (bnx2x_populate_phy(bp, phy_index, shmem_base, shmem2_base,
12377                                        port_of_path, &phy[port]) !=
12378                                        0) {
12379                         DP(NETIF_MSG_LINK, "populate phy failed\n");
12380                         return -EINVAL;
12381                 }
12382                 /* disable attentions */
12383                 bnx2x_bits_dis(bp, NIG_REG_MASK_INTERRUPT_PORT0 +
12384                                port_of_path*4,
12385                                (NIG_MASK_XGXS0_LINK_STATUS |
12386                                 NIG_MASK_XGXS0_LINK10G |
12387                                 NIG_MASK_SERDES0_LINK_STATUS |
12388                                 NIG_MASK_MI_INT));
12389
12390
12391                 /* Reset the phy */
12392                 bnx2x_cl45_write(bp, &phy[port],
12393                                  MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 1<<15);
12394         }
12395
12396         /* Add delay of 150ms after reset */
12397         msleep(150);
12398         if (phy[PORT_0].addr & 0x1) {
12399                 phy_blk[PORT_0] = &(phy[PORT_1]);
12400                 phy_blk[PORT_1] = &(phy[PORT_0]);
12401         } else {
12402                 phy_blk[PORT_0] = &(phy[PORT_0]);
12403                 phy_blk[PORT_1] = &(phy[PORT_1]);
12404         }
12405         /* PART2 - Download firmware to both phys */
12406         for (port = PORT_MAX - 1; port >= PORT_0; port--) {
12407                 if (CHIP_IS_E1x(bp))
12408                         port_of_path = port;
12409                 else
12410                         port_of_path = 0;
12411                 DP(NETIF_MSG_LINK, "Loading spirom for phy address 0x%x\n",
12412                            phy_blk[port]->addr);
12413                 if (bnx2x_8073_8727_external_rom_boot(bp, phy_blk[port],
12414                                                       port_of_path))
12415                         return -EINVAL;
12416                 /* Disable PHY transmitter output */
12417                 bnx2x_cl45_write(bp, phy_blk[port],
12418                                  MDIO_PMA_DEVAD,
12419                                  MDIO_PMA_REG_TX_DISABLE, 1);
12420
12421         }
12422         return 0;
12423 }
12424
12425 static int bnx2x_84833_common_init_phy(struct bnx2x *bp,
12426                                                 u32 shmem_base_path[],
12427                                                 u32 shmem2_base_path[],
12428                                                 u8 phy_index,
12429                                                 u32 chip_id)
12430 {
12431         u8 reset_gpios;
12432         reset_gpios = bnx2x_84833_get_reset_gpios(bp, shmem_base_path, chip_id);
12433         bnx2x_set_mult_gpio(bp, reset_gpios, MISC_REGISTERS_GPIO_OUTPUT_LOW);
12434         udelay(10);
12435         bnx2x_set_mult_gpio(bp, reset_gpios, MISC_REGISTERS_GPIO_OUTPUT_HIGH);
12436         DP(NETIF_MSG_LINK, "84833 reset pulse on pin values 0x%x\n",
12437                 reset_gpios);
12438         return 0;
12439 }
12440
12441 static int bnx2x_84833_pre_init_phy(struct bnx2x *bp,
12442                                                struct bnx2x_phy *phy)
12443 {
12444         u16 val, cnt;
12445         /* Wait for FW completing its initialization. */
12446         for (cnt = 0; cnt < 1500; cnt++) {
12447                 bnx2x_cl45_read(bp, phy,
12448                                 MDIO_PMA_DEVAD,
12449                                 MDIO_PMA_REG_CTRL, &val);
12450                 if (!(val & (1<<15)))
12451                         break;
12452                 msleep(1);
12453         }
12454         if (cnt >= 1500) {
12455                 DP(NETIF_MSG_LINK, "84833 reset timeout\n");
12456                 return -EINVAL;
12457         }
12458
12459         /* Put the port in super isolate mode. */
12460         bnx2x_cl45_read(bp, phy,
12461                         MDIO_CTL_DEVAD,
12462                         MDIO_84833_TOP_CFG_XGPHY_STRAP1, &val);
12463         val |= MDIO_84833_SUPER_ISOLATE;
12464         bnx2x_cl45_write(bp, phy,
12465                          MDIO_CTL_DEVAD,
12466                          MDIO_84833_TOP_CFG_XGPHY_STRAP1, val);
12467
12468         /* Save spirom version */
12469         bnx2x_save_848xx_spirom_version(phy, bp, PORT_0);
12470         return 0;
12471 }
12472
12473 int bnx2x_pre_init_phy(struct bnx2x *bp,
12474                                   u32 shmem_base,
12475                                   u32 shmem2_base,
12476                                   u32 chip_id)
12477 {
12478         int rc = 0;
12479         struct bnx2x_phy phy;
12480         bnx2x_set_mdio_clk(bp, chip_id, PORT_0);
12481         if (bnx2x_populate_phy(bp, EXT_PHY1, shmem_base, shmem2_base,
12482                                PORT_0, &phy)) {
12483                 DP(NETIF_MSG_LINK, "populate_phy failed\n");
12484                 return -EINVAL;
12485         }
12486         switch (phy.type) {
12487         case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84833:
12488                 rc = bnx2x_84833_pre_init_phy(bp, &phy);
12489                 break;
12490         default:
12491                 break;
12492         }
12493         return rc;
12494 }
12495
12496 static int bnx2x_ext_phy_common_init(struct bnx2x *bp, u32 shmem_base_path[],
12497                                      u32 shmem2_base_path[], u8 phy_index,
12498                                      u32 ext_phy_type, u32 chip_id)
12499 {
12500         int rc = 0;
12501
12502         switch (ext_phy_type) {
12503         case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073:
12504                 rc = bnx2x_8073_common_init_phy(bp, shmem_base_path,
12505                                                 shmem2_base_path,
12506                                                 phy_index, chip_id);
12507                 break;
12508         case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8722:
12509         case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727:
12510         case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727_NOC:
12511                 rc = bnx2x_8727_common_init_phy(bp, shmem_base_path,
12512                                                 shmem2_base_path,
12513                                                 phy_index, chip_id);
12514                 break;
12515
12516         case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8726:
12517                 /* GPIO1 affects both ports, so there's need to pull
12518                  * it for single port alone
12519                  */
12520                 rc = bnx2x_8726_common_init_phy(bp, shmem_base_path,
12521                                                 shmem2_base_path,
12522                                                 phy_index, chip_id);
12523                 break;
12524         case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84833:
12525                 /* GPIO3's are linked, and so both need to be toggled
12526                  * to obtain required 2us pulse.
12527                  */
12528                 rc = bnx2x_84833_common_init_phy(bp, shmem_base_path,
12529                                                 shmem2_base_path,
12530                                                 phy_index, chip_id);
12531                 break;
12532         case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_FAILURE:
12533                 rc = -EINVAL;
12534                 break;
12535         default:
12536                 DP(NETIF_MSG_LINK,
12537                            "ext_phy 0x%x common init not required\n",
12538                            ext_phy_type);
12539                 break;
12540         }
12541
12542         if (rc != 0)
12543                 netdev_err(bp->dev,  "Warning: PHY was not initialized,"
12544                                       " Port %d\n",
12545                          0);
12546         return rc;
12547 }
12548
12549 int bnx2x_common_init_phy(struct bnx2x *bp, u32 shmem_base_path[],
12550                           u32 shmem2_base_path[], u32 chip_id)
12551 {
12552         int rc = 0;
12553         u32 phy_ver, val;
12554         u8 phy_index = 0;
12555         u32 ext_phy_type, ext_phy_config;
12556         bnx2x_set_mdio_clk(bp, chip_id, PORT_0);
12557         bnx2x_set_mdio_clk(bp, chip_id, PORT_1);
12558         DP(NETIF_MSG_LINK, "Begin common phy init\n");
12559         if (CHIP_IS_E3(bp)) {
12560                 /* Enable EPIO */
12561                 val = REG_RD(bp, MISC_REG_GEN_PURP_HWG);
12562                 REG_WR(bp, MISC_REG_GEN_PURP_HWG, val | 1);
12563         }
12564         /* Check if common init was already done */
12565         phy_ver = REG_RD(bp, shmem_base_path[0] +
12566                          offsetof(struct shmem_region,
12567                                   port_mb[PORT_0].ext_phy_fw_version));
12568         if (phy_ver) {
12569                 DP(NETIF_MSG_LINK, "Not doing common init; phy ver is 0x%x\n",
12570                                phy_ver);
12571                 return 0;
12572         }
12573
12574         /* Read the ext_phy_type for arbitrary port(0) */
12575         for (phy_index = EXT_PHY1; phy_index < MAX_PHYS;
12576               phy_index++) {
12577                 ext_phy_config = bnx2x_get_ext_phy_config(bp,
12578                                                           shmem_base_path[0],
12579                                                           phy_index, 0);
12580                 ext_phy_type = XGXS_EXT_PHY_TYPE(ext_phy_config);
12581                 rc |= bnx2x_ext_phy_common_init(bp, shmem_base_path,
12582                                                 shmem2_base_path,
12583                                                 phy_index, ext_phy_type,
12584                                                 chip_id);
12585         }
12586         return rc;
12587 }
12588
12589 static void bnx2x_check_over_curr(struct link_params *params,
12590                                   struct link_vars *vars)
12591 {
12592         struct bnx2x *bp = params->bp;
12593         u32 cfg_pin;
12594         u8 port = params->port;
12595         u32 pin_val;
12596
12597         cfg_pin = (REG_RD(bp, params->shmem_base +
12598                           offsetof(struct shmem_region,
12599                                dev_info.port_hw_config[port].e3_cmn_pin_cfg1)) &
12600                    PORT_HW_CFG_E3_OVER_CURRENT_MASK) >>
12601                 PORT_HW_CFG_E3_OVER_CURRENT_SHIFT;
12602
12603         /* Ignore check if no external input PIN available */
12604         if (bnx2x_get_cfg_pin(bp, cfg_pin, &pin_val) != 0)
12605                 return;
12606
12607         if (!pin_val) {
12608                 if ((vars->phy_flags & PHY_OVER_CURRENT_FLAG) == 0) {
12609                         netdev_err(bp->dev, "Error:  Power fault on Port %d has"
12610                                             " been detected and the power to "
12611                                             "that SFP+ module has been removed"
12612                                             " to prevent failure of the card."
12613                                             " Please remove the SFP+ module and"
12614                                             " restart the system to clear this"
12615                                             " error.\n",
12616                          params->port);
12617                         vars->phy_flags |= PHY_OVER_CURRENT_FLAG;
12618                 }
12619         } else
12620                 vars->phy_flags &= ~PHY_OVER_CURRENT_FLAG;
12621 }
12622
12623 static void bnx2x_analyze_link_error(struct link_params *params,
12624                                      struct link_vars *vars, u32 lss_status,
12625                                      u8 notify)
12626 {
12627         struct bnx2x *bp = params->bp;
12628         /* Compare new value with previous value */
12629         u8 led_mode;
12630         u32 half_open_conn = (vars->phy_flags & PHY_HALF_OPEN_CONN_FLAG) > 0;
12631
12632         if ((lss_status ^ half_open_conn) == 0)
12633                 return;
12634
12635         /* If values differ */
12636         DP(NETIF_MSG_LINK, "Link changed:%x %x->%x\n", vars->link_up,
12637                        half_open_conn, lss_status);
12638
12639         /* a. Update shmem->link_status accordingly
12640          * b. Update link_vars->link_up
12641          */
12642         if (lss_status) {
12643                 DP(NETIF_MSG_LINK, "Remote Fault detected !!!\n");
12644                 vars->link_status &= ~LINK_STATUS_LINK_UP;
12645                 vars->link_up = 0;
12646                 vars->phy_flags |= PHY_HALF_OPEN_CONN_FLAG;
12647
12648                 /* activate nig drain */
12649                 REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE + params->port*4, 1);
12650                 /* Set LED mode to off since the PHY doesn't know about these
12651                  * errors
12652                  */
12653                 led_mode = LED_MODE_OFF;
12654         } else {
12655                 DP(NETIF_MSG_LINK, "Remote Fault cleared\n");
12656                 vars->link_status |= LINK_STATUS_LINK_UP;
12657                 vars->link_up = 1;
12658                 vars->phy_flags &= ~PHY_HALF_OPEN_CONN_FLAG;
12659                 led_mode = LED_MODE_OPER;
12660
12661                 /* Clear nig drain */
12662                 REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE + params->port*4, 0);
12663         }
12664         bnx2x_sync_link(params, vars);
12665         /* Update the LED according to the link state */
12666         bnx2x_set_led(params, vars, led_mode, SPEED_10000);
12667
12668         /* Update link status in the shared memory */
12669         bnx2x_update_mng(params, vars->link_status);
12670
12671         /* C. Trigger General Attention */
12672         vars->periodic_flags |= PERIODIC_FLAGS_LINK_EVENT;
12673         if (notify)
12674                 bnx2x_notify_link_changed(bp);
12675 }
12676
12677 /******************************************************************************
12678 * Description:
12679 *       This function checks for half opened connection change indication.
12680 *       When such change occurs, it calls the bnx2x_analyze_link_error
12681 *       to check if Remote Fault is set or cleared. Reception of remote fault
12682 *       status message in the MAC indicates that the peer's MAC has detected
12683 *       a fault, for example, due to break in the TX side of fiber.
12684 *
12685 ******************************************************************************/
12686 int bnx2x_check_half_open_conn(struct link_params *params,
12687                                 struct link_vars *vars,
12688                                 u8 notify)
12689 {
12690         struct bnx2x *bp = params->bp;
12691         u32 lss_status = 0;
12692         u32 mac_base;
12693         /* In case link status is physically up @ 10G do */
12694         if (((vars->phy_flags & PHY_PHYSICAL_LINK_FLAG) == 0) ||
12695             (REG_RD(bp, NIG_REG_EGRESS_EMAC0_PORT + params->port*4)))
12696                 return 0;
12697
12698         if (CHIP_IS_E3(bp) &&
12699             (REG_RD(bp, MISC_REG_RESET_REG_2) &
12700               (MISC_REGISTERS_RESET_REG_2_XMAC))) {
12701                 /* Check E3 XMAC */
12702                 /* Note that link speed cannot be queried here, since it may be
12703                  * zero while link is down. In case UMAC is active, LSS will
12704                  * simply not be set
12705                  */
12706                 mac_base = (params->port) ? GRCBASE_XMAC1 : GRCBASE_XMAC0;
12707
12708                 /* Clear stick bits (Requires rising edge) */
12709                 REG_WR(bp, mac_base + XMAC_REG_CLEAR_RX_LSS_STATUS, 0);
12710                 REG_WR(bp, mac_base + XMAC_REG_CLEAR_RX_LSS_STATUS,
12711                        XMAC_CLEAR_RX_LSS_STATUS_REG_CLEAR_LOCAL_FAULT_STATUS |
12712                        XMAC_CLEAR_RX_LSS_STATUS_REG_CLEAR_REMOTE_FAULT_STATUS);
12713                 if (REG_RD(bp, mac_base + XMAC_REG_RX_LSS_STATUS))
12714                         lss_status = 1;
12715
12716                 bnx2x_analyze_link_error(params, vars, lss_status, notify);
12717         } else if (REG_RD(bp, MISC_REG_RESET_REG_2) &
12718                    (MISC_REGISTERS_RESET_REG_2_RST_BMAC0 << params->port)) {
12719                 /* Check E1X / E2 BMAC */
12720                 u32 lss_status_reg;
12721                 u32 wb_data[2];
12722                 mac_base = params->port ? NIG_REG_INGRESS_BMAC1_MEM :
12723                         NIG_REG_INGRESS_BMAC0_MEM;
12724                 /*  Read BIGMAC_REGISTER_RX_LSS_STATUS */
12725                 if (CHIP_IS_E2(bp))
12726                         lss_status_reg = BIGMAC2_REGISTER_RX_LSS_STAT;
12727                 else
12728                         lss_status_reg = BIGMAC_REGISTER_RX_LSS_STATUS;
12729
12730                 REG_RD_DMAE(bp, mac_base + lss_status_reg, wb_data, 2);
12731                 lss_status = (wb_data[0] > 0);
12732
12733                 bnx2x_analyze_link_error(params, vars, lss_status, notify);
12734         }
12735         return 0;
12736 }
12737
12738 void bnx2x_period_func(struct link_params *params, struct link_vars *vars)
12739 {
12740         u16 phy_idx;
12741         struct bnx2x *bp = params->bp;
12742         for (phy_idx = INT_PHY; phy_idx < MAX_PHYS; phy_idx++) {
12743                 if (params->phy[phy_idx].flags & FLAGS_TX_ERROR_CHECK) {
12744                         bnx2x_set_aer_mmd(params, &params->phy[phy_idx]);
12745                         if (bnx2x_check_half_open_conn(params, vars, 1) !=
12746                             0)
12747                                 DP(NETIF_MSG_LINK, "Fault detection failed\n");
12748                         break;
12749                 }
12750         }
12751
12752         if (CHIP_IS_E3(bp)) {
12753                 struct bnx2x_phy *phy = &params->phy[INT_PHY];
12754                 bnx2x_set_aer_mmd(params, phy);
12755                 bnx2x_check_over_curr(params, vars);
12756                 bnx2x_warpcore_config_runtime(phy, params, vars);
12757         }
12758
12759 }
12760
12761 u8 bnx2x_hw_lock_required(struct bnx2x *bp, u32 shmem_base, u32 shmem2_base)
12762 {
12763         u8 phy_index;
12764         struct bnx2x_phy phy;
12765         for (phy_index = INT_PHY; phy_index < MAX_PHYS;
12766               phy_index++) {
12767                 if (bnx2x_populate_phy(bp, phy_index, shmem_base, shmem2_base,
12768                                        0, &phy) != 0) {
12769                         DP(NETIF_MSG_LINK, "populate phy failed\n");
12770                         return 0;
12771                 }
12772
12773                 if (phy.flags & FLAGS_HW_LOCK_REQUIRED)
12774                         return 1;
12775         }
12776         return 0;
12777 }
12778
12779 u8 bnx2x_fan_failure_det_req(struct bnx2x *bp,
12780                              u32 shmem_base,
12781                              u32 shmem2_base,
12782                              u8 port)
12783 {
12784         u8 phy_index, fan_failure_det_req = 0;
12785         struct bnx2x_phy phy;
12786         for (phy_index = EXT_PHY1; phy_index < MAX_PHYS;
12787               phy_index++) {
12788                 if (bnx2x_populate_phy(bp, phy_index, shmem_base, shmem2_base,
12789                                        port, &phy)
12790                     != 0) {
12791                         DP(NETIF_MSG_LINK, "populate phy failed\n");
12792                         return 0;
12793                 }
12794                 fan_failure_det_req |= (phy.flags &
12795                                         FLAGS_FAN_FAILURE_DET_REQ);
12796         }
12797         return fan_failure_det_req;
12798 }
12799
12800 void bnx2x_hw_reset_phy(struct link_params *params)
12801 {
12802         u8 phy_index;
12803         struct bnx2x *bp = params->bp;
12804         bnx2x_update_mng(params, 0);
12805         bnx2x_bits_dis(bp, NIG_REG_MASK_INTERRUPT_PORT0 + params->port*4,
12806                        (NIG_MASK_XGXS0_LINK_STATUS |
12807                         NIG_MASK_XGXS0_LINK10G |
12808                         NIG_MASK_SERDES0_LINK_STATUS |
12809                         NIG_MASK_MI_INT));
12810
12811         for (phy_index = INT_PHY; phy_index < MAX_PHYS;
12812               phy_index++) {
12813                 if (params->phy[phy_index].hw_reset) {
12814                         params->phy[phy_index].hw_reset(
12815                                 &params->phy[phy_index],
12816                                 params);
12817                         params->phy[phy_index] = phy_null;
12818                 }
12819         }
12820 }
12821
12822 void bnx2x_init_mod_abs_int(struct bnx2x *bp, struct link_vars *vars,
12823                             u32 chip_id, u32 shmem_base, u32 shmem2_base,
12824                             u8 port)
12825 {
12826         u8 gpio_num = 0xff, gpio_port = 0xff, phy_index;
12827         u32 val;
12828         u32 offset, aeu_mask, swap_val, swap_override, sync_offset;
12829         if (CHIP_IS_E3(bp)) {
12830                 if (bnx2x_get_mod_abs_int_cfg(bp, chip_id,
12831                                               shmem_base,
12832                                               port,
12833                                               &gpio_num,
12834                                               &gpio_port) != 0)
12835                         return;
12836         } else {
12837                 struct bnx2x_phy phy;
12838                 for (phy_index = EXT_PHY1; phy_index < MAX_PHYS;
12839                       phy_index++) {
12840                         if (bnx2x_populate_phy(bp, phy_index, shmem_base,
12841                                                shmem2_base, port, &phy)
12842                             != 0) {
12843                                 DP(NETIF_MSG_LINK, "populate phy failed\n");
12844                                 return;
12845                         }
12846                         if (phy.type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8726) {
12847                                 gpio_num = MISC_REGISTERS_GPIO_3;
12848                                 gpio_port = port;
12849                                 break;
12850                         }
12851                 }
12852         }
12853
12854         if (gpio_num == 0xff)
12855                 return;
12856
12857         /* Set GPIO3 to trigger SFP+ module insertion/removal */
12858         bnx2x_set_gpio(bp, gpio_num, MISC_REGISTERS_GPIO_INPUT_HI_Z, gpio_port);
12859
12860         swap_val = REG_RD(bp, NIG_REG_PORT_SWAP);
12861         swap_override = REG_RD(bp, NIG_REG_STRAP_OVERRIDE);
12862         gpio_port ^= (swap_val && swap_override);
12863
12864         vars->aeu_int_mask = AEU_INPUTS_ATTN_BITS_GPIO0_FUNCTION_0 <<
12865                 (gpio_num + (gpio_port << 2));
12866
12867         sync_offset = shmem_base +
12868                 offsetof(struct shmem_region,
12869                          dev_info.port_hw_config[port].aeu_int_mask);
12870         REG_WR(bp, sync_offset, vars->aeu_int_mask);
12871
12872         DP(NETIF_MSG_LINK, "Setting MOD_ABS (GPIO%d_P%d) AEU to 0x%x\n",
12873                        gpio_num, gpio_port, vars->aeu_int_mask);
12874
12875         if (port == 0)
12876                 offset = MISC_REG_AEU_ENABLE1_FUNC_0_OUT_0;
12877         else
12878                 offset = MISC_REG_AEU_ENABLE1_FUNC_1_OUT_0;
12879
12880         /* Open appropriate AEU for interrupts */
12881         aeu_mask = REG_RD(bp, offset);
12882         aeu_mask |= vars->aeu_int_mask;
12883         REG_WR(bp, offset, aeu_mask);
12884
12885         /* Enable the GPIO to trigger interrupt */
12886         val = REG_RD(bp, MISC_REG_GPIO_EVENT_EN);
12887         val |= 1 << (gpio_num + (gpio_port << 2));
12888         REG_WR(bp, MISC_REG_GPIO_EVENT_EN, val);
12889 }