1 /* bnx2x_hsi.h: Qlogic Everest network driver.
3 * Copyright (c) 2007-2013 Broadcom Corporation
4 * Copyright (c) 2014 QLogic Corporation
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation.
14 #include "bnx2x_fw_defs.h"
15 #include "bnx2x_mfw_req.h"
17 #define FW_ENCODE_32BIT_PATTERN 0x1e1e1e1e
23 #define BNX2X_MAX_ISCSI_TRGT_CONN_MASK 0xFFFF
24 #define BNX2X_MAX_ISCSI_TRGT_CONN_SHIFT 0
25 #define BNX2X_MAX_ISCSI_INIT_CONN_MASK 0xFFFF0000
26 #define BNX2X_MAX_ISCSI_INIT_CONN_SHIFT 16
31 #define BNX2X_MAX_FCOE_TRGT_CONN_MASK 0xFFFF
32 #define BNX2X_MAX_FCOE_TRGT_CONN_SHIFT 0
33 #define BNX2X_MAX_FCOE_INIT_CONN_MASK 0xFFFF0000
34 #define BNX2X_MAX_FCOE_INIT_CONN_SHIFT 16
39 /****************************************************************************
40 * Shared HW configuration *
41 ****************************************************************************/
42 #define PIN_CFG_NA 0x00000000
43 #define PIN_CFG_GPIO0_P0 0x00000001
44 #define PIN_CFG_GPIO1_P0 0x00000002
45 #define PIN_CFG_GPIO2_P0 0x00000003
46 #define PIN_CFG_GPIO3_P0 0x00000004
47 #define PIN_CFG_GPIO0_P1 0x00000005
48 #define PIN_CFG_GPIO1_P1 0x00000006
49 #define PIN_CFG_GPIO2_P1 0x00000007
50 #define PIN_CFG_GPIO3_P1 0x00000008
51 #define PIN_CFG_EPIO0 0x00000009
52 #define PIN_CFG_EPIO1 0x0000000a
53 #define PIN_CFG_EPIO2 0x0000000b
54 #define PIN_CFG_EPIO3 0x0000000c
55 #define PIN_CFG_EPIO4 0x0000000d
56 #define PIN_CFG_EPIO5 0x0000000e
57 #define PIN_CFG_EPIO6 0x0000000f
58 #define PIN_CFG_EPIO7 0x00000010
59 #define PIN_CFG_EPIO8 0x00000011
60 #define PIN_CFG_EPIO9 0x00000012
61 #define PIN_CFG_EPIO10 0x00000013
62 #define PIN_CFG_EPIO11 0x00000014
63 #define PIN_CFG_EPIO12 0x00000015
64 #define PIN_CFG_EPIO13 0x00000016
65 #define PIN_CFG_EPIO14 0x00000017
66 #define PIN_CFG_EPIO15 0x00000018
67 #define PIN_CFG_EPIO16 0x00000019
68 #define PIN_CFG_EPIO17 0x0000001a
69 #define PIN_CFG_EPIO18 0x0000001b
70 #define PIN_CFG_EPIO19 0x0000001c
71 #define PIN_CFG_EPIO20 0x0000001d
72 #define PIN_CFG_EPIO21 0x0000001e
73 #define PIN_CFG_EPIO22 0x0000001f
74 #define PIN_CFG_EPIO23 0x00000020
75 #define PIN_CFG_EPIO24 0x00000021
76 #define PIN_CFG_EPIO25 0x00000022
77 #define PIN_CFG_EPIO26 0x00000023
78 #define PIN_CFG_EPIO27 0x00000024
79 #define PIN_CFG_EPIO28 0x00000025
80 #define PIN_CFG_EPIO29 0x00000026
81 #define PIN_CFG_EPIO30 0x00000027
82 #define PIN_CFG_EPIO31 0x00000028
85 #define EPIO_CFG_NA 0x00000000
86 #define EPIO_CFG_EPIO0 0x00000001
87 #define EPIO_CFG_EPIO1 0x00000002
88 #define EPIO_CFG_EPIO2 0x00000003
89 #define EPIO_CFG_EPIO3 0x00000004
90 #define EPIO_CFG_EPIO4 0x00000005
91 #define EPIO_CFG_EPIO5 0x00000006
92 #define EPIO_CFG_EPIO6 0x00000007
93 #define EPIO_CFG_EPIO7 0x00000008
94 #define EPIO_CFG_EPIO8 0x00000009
95 #define EPIO_CFG_EPIO9 0x0000000a
96 #define EPIO_CFG_EPIO10 0x0000000b
97 #define EPIO_CFG_EPIO11 0x0000000c
98 #define EPIO_CFG_EPIO12 0x0000000d
99 #define EPIO_CFG_EPIO13 0x0000000e
100 #define EPIO_CFG_EPIO14 0x0000000f
101 #define EPIO_CFG_EPIO15 0x00000010
102 #define EPIO_CFG_EPIO16 0x00000011
103 #define EPIO_CFG_EPIO17 0x00000012
104 #define EPIO_CFG_EPIO18 0x00000013
105 #define EPIO_CFG_EPIO19 0x00000014
106 #define EPIO_CFG_EPIO20 0x00000015
107 #define EPIO_CFG_EPIO21 0x00000016
108 #define EPIO_CFG_EPIO22 0x00000017
109 #define EPIO_CFG_EPIO23 0x00000018
110 #define EPIO_CFG_EPIO24 0x00000019
111 #define EPIO_CFG_EPIO25 0x0000001a
112 #define EPIO_CFG_EPIO26 0x0000001b
113 #define EPIO_CFG_EPIO27 0x0000001c
114 #define EPIO_CFG_EPIO28 0x0000001d
115 #define EPIO_CFG_EPIO29 0x0000001e
116 #define EPIO_CFG_EPIO30 0x0000001f
117 #define EPIO_CFG_EPIO31 0x00000020
124 struct shared_hw_cfg { /* NVRAM Offset */
125 /* Up to 16 bytes of NULL-terminated string */
126 u8 part_num[16]; /* 0x104 */
128 u32 config; /* 0x114 */
129 #define SHARED_HW_CFG_MDIO_VOLTAGE_MASK 0x00000001
130 #define SHARED_HW_CFG_MDIO_VOLTAGE_SHIFT 0
131 #define SHARED_HW_CFG_MDIO_VOLTAGE_1_2V 0x00000000
132 #define SHARED_HW_CFG_MDIO_VOLTAGE_2_5V 0x00000001
133 #define SHARED_HW_CFG_MCP_RST_ON_CORE_RST_EN 0x00000002
135 #define SHARED_HW_CFG_PORT_SWAP 0x00000004
137 #define SHARED_HW_CFG_BEACON_WOL_EN 0x00000008
139 #define SHARED_HW_CFG_PCIE_GEN3_DISABLED 0x00000000
140 #define SHARED_HW_CFG_PCIE_GEN3_ENABLED 0x00000010
142 #define SHARED_HW_CFG_MFW_SELECT_MASK 0x00000700
143 #define SHARED_HW_CFG_MFW_SELECT_SHIFT 8
144 /* Whatever MFW found in NVM
145 (if multiple found, priority order is: NC-SI, UMP, IPMI) */
146 #define SHARED_HW_CFG_MFW_SELECT_DEFAULT 0x00000000
147 #define SHARED_HW_CFG_MFW_SELECT_NC_SI 0x00000100
148 #define SHARED_HW_CFG_MFW_SELECT_UMP 0x00000200
149 #define SHARED_HW_CFG_MFW_SELECT_IPMI 0x00000300
150 /* Use SPIO4 as an arbiter between: 0-NC_SI, 1-IPMI
151 (can only be used when an add-in board, not BMC, pulls-down SPIO4) */
152 #define SHARED_HW_CFG_MFW_SELECT_SPIO4_NC_SI_IPMI 0x00000400
153 /* Use SPIO4 as an arbiter between: 0-UMP, 1-IPMI
154 (can only be used when an add-in board, not BMC, pulls-down SPIO4) */
155 #define SHARED_HW_CFG_MFW_SELECT_SPIO4_UMP_IPMI 0x00000500
156 /* Use SPIO4 as an arbiter between: 0-NC-SI, 1-UMP
157 (can only be used when an add-in board, not BMC, pulls-down SPIO4) */
158 #define SHARED_HW_CFG_MFW_SELECT_SPIO4_NC_SI_UMP 0x00000600
160 #define SHARED_HW_CFG_LED_MODE_MASK 0x000f0000
161 #define SHARED_HW_CFG_LED_MODE_SHIFT 16
162 #define SHARED_HW_CFG_LED_MAC1 0x00000000
163 #define SHARED_HW_CFG_LED_PHY1 0x00010000
164 #define SHARED_HW_CFG_LED_PHY2 0x00020000
165 #define SHARED_HW_CFG_LED_PHY3 0x00030000
166 #define SHARED_HW_CFG_LED_MAC2 0x00040000
167 #define SHARED_HW_CFG_LED_PHY4 0x00050000
168 #define SHARED_HW_CFG_LED_PHY5 0x00060000
169 #define SHARED_HW_CFG_LED_PHY6 0x00070000
170 #define SHARED_HW_CFG_LED_MAC3 0x00080000
171 #define SHARED_HW_CFG_LED_PHY7 0x00090000
172 #define SHARED_HW_CFG_LED_PHY9 0x000a0000
173 #define SHARED_HW_CFG_LED_PHY11 0x000b0000
174 #define SHARED_HW_CFG_LED_MAC4 0x000c0000
175 #define SHARED_HW_CFG_LED_PHY8 0x000d0000
176 #define SHARED_HW_CFG_LED_EXTPHY1 0x000e0000
177 #define SHARED_HW_CFG_LED_EXTPHY2 0x000f0000
180 #define SHARED_HW_CFG_AN_ENABLE_MASK 0x3f000000
181 #define SHARED_HW_CFG_AN_ENABLE_SHIFT 24
182 #define SHARED_HW_CFG_AN_ENABLE_CL37 0x01000000
183 #define SHARED_HW_CFG_AN_ENABLE_CL73 0x02000000
184 #define SHARED_HW_CFG_AN_ENABLE_BAM 0x04000000
185 #define SHARED_HW_CFG_AN_ENABLE_PARALLEL_DETECTION 0x08000000
186 #define SHARED_HW_CFG_AN_EN_SGMII_FIBER_AUTO_DETECT 0x10000000
187 #define SHARED_HW_CFG_AN_ENABLE_REMOTE_PHY 0x20000000
189 #define SHARED_HW_CFG_SRIOV_MASK 0x40000000
190 #define SHARED_HW_CFG_SRIOV_DISABLED 0x00000000
191 #define SHARED_HW_CFG_SRIOV_ENABLED 0x40000000
193 #define SHARED_HW_CFG_ATC_MASK 0x80000000
194 #define SHARED_HW_CFG_ATC_DISABLED 0x00000000
195 #define SHARED_HW_CFG_ATC_ENABLED 0x80000000
197 u32 config2; /* 0x118 */
198 /* one time auto detect grace period (in sec) */
199 #define SHARED_HW_CFG_GRACE_PERIOD_MASK 0x000000ff
200 #define SHARED_HW_CFG_GRACE_PERIOD_SHIFT 0
202 #define SHARED_HW_CFG_PCIE_GEN2_ENABLED 0x00000100
203 #define SHARED_HW_CFG_PCIE_GEN2_DISABLED 0x00000000
205 /* The default value for the core clock is 250MHz and it is
206 achieved by setting the clock change to 4 */
207 #define SHARED_HW_CFG_CLOCK_CHANGE_MASK 0x00000e00
208 #define SHARED_HW_CFG_CLOCK_CHANGE_SHIFT 9
210 #define SHARED_HW_CFG_SMBUS_TIMING_MASK 0x00001000
211 #define SHARED_HW_CFG_SMBUS_TIMING_100KHZ 0x00000000
212 #define SHARED_HW_CFG_SMBUS_TIMING_400KHZ 0x00001000
214 #define SHARED_HW_CFG_HIDE_PORT1 0x00002000
216 #define SHARED_HW_CFG_WOL_CAPABLE_MASK 0x00004000
217 #define SHARED_HW_CFG_WOL_CAPABLE_DISABLED 0x00000000
218 #define SHARED_HW_CFG_WOL_CAPABLE_ENABLED 0x00004000
220 /* Output low when PERST is asserted */
221 #define SHARED_HW_CFG_SPIO4_FOLLOW_PERST_MASK 0x00008000
222 #define SHARED_HW_CFG_SPIO4_FOLLOW_PERST_DISABLED 0x00000000
223 #define SHARED_HW_CFG_SPIO4_FOLLOW_PERST_ENABLED 0x00008000
225 #define SHARED_HW_CFG_PCIE_GEN2_PREEMPHASIS_MASK 0x00070000
226 #define SHARED_HW_CFG_PCIE_GEN2_PREEMPHASIS_SHIFT 16
227 #define SHARED_HW_CFG_PCIE_GEN2_PREEMPHASIS_HW 0x00000000
228 #define SHARED_HW_CFG_PCIE_GEN2_PREEMPHASIS_0DB 0x00010000
229 #define SHARED_HW_CFG_PCIE_GEN2_PREEMPHASIS_3_5DB 0x00020000
230 #define SHARED_HW_CFG_PCIE_GEN2_PREEMPHASIS_6_0DB 0x00030000
232 /* The fan failure mechanism is usually related to the PHY type
233 since the power consumption of the board is determined by the PHY.
234 Currently, fan is required for most designs with SFX7101, BCM8727
235 and BCM8481. If a fan is not required for a board which uses one
236 of those PHYs, this field should be set to "Disabled". If a fan is
237 required for a different PHY type, this option should be set to
238 "Enabled". The fan failure indication is expected on SPIO5 */
239 #define SHARED_HW_CFG_FAN_FAILURE_MASK 0x00180000
240 #define SHARED_HW_CFG_FAN_FAILURE_SHIFT 19
241 #define SHARED_HW_CFG_FAN_FAILURE_PHY_TYPE 0x00000000
242 #define SHARED_HW_CFG_FAN_FAILURE_DISABLED 0x00080000
243 #define SHARED_HW_CFG_FAN_FAILURE_ENABLED 0x00100000
245 /* ASPM Power Management support */
246 #define SHARED_HW_CFG_ASPM_SUPPORT_MASK 0x00600000
247 #define SHARED_HW_CFG_ASPM_SUPPORT_SHIFT 21
248 #define SHARED_HW_CFG_ASPM_SUPPORT_L0S_L1_ENABLED 0x00000000
249 #define SHARED_HW_CFG_ASPM_SUPPORT_L0S_DISABLED 0x00200000
250 #define SHARED_HW_CFG_ASPM_SUPPORT_L1_DISABLED 0x00400000
251 #define SHARED_HW_CFG_ASPM_SUPPORT_L0S_L1_DISABLED 0x00600000
253 /* The value of PM_TL_IGNORE_REQS (bit0) in PCI register
254 tl_control_0 (register 0x2800) */
255 #define SHARED_HW_CFG_PREVENT_L1_ENTRY_MASK 0x00800000
256 #define SHARED_HW_CFG_PREVENT_L1_ENTRY_DISABLED 0x00000000
257 #define SHARED_HW_CFG_PREVENT_L1_ENTRY_ENABLED 0x00800000
259 #define SHARED_HW_CFG_PORT_MODE_MASK 0x01000000
260 #define SHARED_HW_CFG_PORT_MODE_2 0x00000000
261 #define SHARED_HW_CFG_PORT_MODE_4 0x01000000
263 #define SHARED_HW_CFG_PATH_SWAP_MASK 0x02000000
264 #define SHARED_HW_CFG_PATH_SWAP_DISABLED 0x00000000
265 #define SHARED_HW_CFG_PATH_SWAP_ENABLED 0x02000000
267 /* Set the MDC/MDIO access for the first external phy */
268 #define SHARED_HW_CFG_MDC_MDIO_ACCESS1_MASK 0x1C000000
269 #define SHARED_HW_CFG_MDC_MDIO_ACCESS1_SHIFT 26
270 #define SHARED_HW_CFG_MDC_MDIO_ACCESS1_PHY_TYPE 0x00000000
271 #define SHARED_HW_CFG_MDC_MDIO_ACCESS1_EMAC0 0x04000000
272 #define SHARED_HW_CFG_MDC_MDIO_ACCESS1_EMAC1 0x08000000
273 #define SHARED_HW_CFG_MDC_MDIO_ACCESS1_BOTH 0x0c000000
274 #define SHARED_HW_CFG_MDC_MDIO_ACCESS1_SWAPPED 0x10000000
276 /* Set the MDC/MDIO access for the second external phy */
277 #define SHARED_HW_CFG_MDC_MDIO_ACCESS2_MASK 0xE0000000
278 #define SHARED_HW_CFG_MDC_MDIO_ACCESS2_SHIFT 29
279 #define SHARED_HW_CFG_MDC_MDIO_ACCESS2_PHY_TYPE 0x00000000
280 #define SHARED_HW_CFG_MDC_MDIO_ACCESS2_EMAC0 0x20000000
281 #define SHARED_HW_CFG_MDC_MDIO_ACCESS2_EMAC1 0x40000000
282 #define SHARED_HW_CFG_MDC_MDIO_ACCESS2_BOTH 0x60000000
283 #define SHARED_HW_CFG_MDC_MDIO_ACCESS2_SWAPPED 0x80000000
285 u32 config_3; /* 0x11C */
286 #define SHARED_HW_CFG_EXTENDED_MF_MODE_MASK 0x00000F00
287 #define SHARED_HW_CFG_EXTENDED_MF_MODE_SHIFT 8
288 #define SHARED_HW_CFG_EXTENDED_MF_MODE_NPAR1_DOT_5 0x00000000
289 #define SHARED_HW_CFG_EXTENDED_MF_MODE_NPAR2_DOT_0 0x00000100
291 u32 ump_nc_si_config; /* 0x120 */
292 #define SHARED_HW_CFG_UMP_NC_SI_MII_MODE_MASK 0x00000003
293 #define SHARED_HW_CFG_UMP_NC_SI_MII_MODE_SHIFT 0
294 #define SHARED_HW_CFG_UMP_NC_SI_MII_MODE_MAC 0x00000000
295 #define SHARED_HW_CFG_UMP_NC_SI_MII_MODE_PHY 0x00000001
296 #define SHARED_HW_CFG_UMP_NC_SI_MII_MODE_MII 0x00000000
297 #define SHARED_HW_CFG_UMP_NC_SI_MII_MODE_RMII 0x00000002
299 #define SHARED_HW_CFG_UMP_NC_SI_NUM_DEVS_MASK 0x00000f00
300 #define SHARED_HW_CFG_UMP_NC_SI_NUM_DEVS_SHIFT 8
302 #define SHARED_HW_CFG_UMP_NC_SI_EXT_PHY_TYPE_MASK 0x00ff0000
303 #define SHARED_HW_CFG_UMP_NC_SI_EXT_PHY_TYPE_SHIFT 16
304 #define SHARED_HW_CFG_UMP_NC_SI_EXT_PHY_TYPE_NONE 0x00000000
305 #define SHARED_HW_CFG_UMP_NC_SI_EXT_PHY_TYPE_BCM5221 0x00010000
307 u32 board; /* 0x124 */
308 #define SHARED_HW_CFG_E3_I2C_MUX0_MASK 0x0000003F
309 #define SHARED_HW_CFG_E3_I2C_MUX0_SHIFT 0
310 #define SHARED_HW_CFG_E3_I2C_MUX1_MASK 0x00000FC0
311 #define SHARED_HW_CFG_E3_I2C_MUX1_SHIFT 6
312 /* Use the PIN_CFG_XXX defines on top */
313 #define SHARED_HW_CFG_BOARD_REV_MASK 0x00ff0000
314 #define SHARED_HW_CFG_BOARD_REV_SHIFT 16
316 #define SHARED_HW_CFG_BOARD_MAJOR_VER_MASK 0x0f000000
317 #define SHARED_HW_CFG_BOARD_MAJOR_VER_SHIFT 24
319 #define SHARED_HW_CFG_BOARD_MINOR_VER_MASK 0xf0000000
320 #define SHARED_HW_CFG_BOARD_MINOR_VER_SHIFT 28
322 u32 wc_lane_config; /* 0x128 */
323 #define SHARED_HW_CFG_LANE_SWAP_CFG_MASK 0x0000FFFF
324 #define SHARED_HW_CFG_LANE_SWAP_CFG_SHIFT 0
325 #define SHARED_HW_CFG_LANE_SWAP_CFG_32103210 0x00001b1b
326 #define SHARED_HW_CFG_LANE_SWAP_CFG_32100123 0x00001be4
327 #define SHARED_HW_CFG_LANE_SWAP_CFG_01233210 0x0000e41b
328 #define SHARED_HW_CFG_LANE_SWAP_CFG_01230123 0x0000e4e4
329 #define SHARED_HW_CFG_LANE_SWAP_CFG_TX_MASK 0x000000FF
330 #define SHARED_HW_CFG_LANE_SWAP_CFG_TX_SHIFT 0
331 #define SHARED_HW_CFG_LANE_SWAP_CFG_RX_MASK 0x0000FF00
332 #define SHARED_HW_CFG_LANE_SWAP_CFG_RX_SHIFT 8
334 /* TX lane Polarity swap */
335 #define SHARED_HW_CFG_TX_LANE0_POL_FLIP_ENABLED 0x00010000
336 #define SHARED_HW_CFG_TX_LANE1_POL_FLIP_ENABLED 0x00020000
337 #define SHARED_HW_CFG_TX_LANE2_POL_FLIP_ENABLED 0x00040000
338 #define SHARED_HW_CFG_TX_LANE3_POL_FLIP_ENABLED 0x00080000
339 /* TX lane Polarity swap */
340 #define SHARED_HW_CFG_RX_LANE0_POL_FLIP_ENABLED 0x00100000
341 #define SHARED_HW_CFG_RX_LANE1_POL_FLIP_ENABLED 0x00200000
342 #define SHARED_HW_CFG_RX_LANE2_POL_FLIP_ENABLED 0x00400000
343 #define SHARED_HW_CFG_RX_LANE3_POL_FLIP_ENABLED 0x00800000
345 /* Selects the port layout of the board */
346 #define SHARED_HW_CFG_E3_PORT_LAYOUT_MASK 0x0F000000
347 #define SHARED_HW_CFG_E3_PORT_LAYOUT_SHIFT 24
348 #define SHARED_HW_CFG_E3_PORT_LAYOUT_2P_01 0x00000000
349 #define SHARED_HW_CFG_E3_PORT_LAYOUT_2P_10 0x01000000
350 #define SHARED_HW_CFG_E3_PORT_LAYOUT_4P_0123 0x02000000
351 #define SHARED_HW_CFG_E3_PORT_LAYOUT_4P_1032 0x03000000
352 #define SHARED_HW_CFG_E3_PORT_LAYOUT_4P_2301 0x04000000
353 #define SHARED_HW_CFG_E3_PORT_LAYOUT_4P_3210 0x05000000
357 /****************************************************************************
358 * Port HW configuration *
359 ****************************************************************************/
360 struct port_hw_cfg { /* port 0: 0x12c port 1: 0x2bc */
363 #define PORT_HW_CFG_PCI_VENDOR_ID_MASK 0xffff0000
364 #define PORT_HW_CFG_PCI_DEVICE_ID_MASK 0x0000ffff
367 #define PORT_HW_CFG_PCI_SUBSYS_DEVICE_ID_MASK 0xffff0000
368 #define PORT_HW_CFG_PCI_SUBSYS_VENDOR_ID_MASK 0x0000ffff
370 u32 power_dissipated;
371 #define PORT_HW_CFG_POWER_DIS_D0_MASK 0x000000ff
372 #define PORT_HW_CFG_POWER_DIS_D0_SHIFT 0
373 #define PORT_HW_CFG_POWER_DIS_D1_MASK 0x0000ff00
374 #define PORT_HW_CFG_POWER_DIS_D1_SHIFT 8
375 #define PORT_HW_CFG_POWER_DIS_D2_MASK 0x00ff0000
376 #define PORT_HW_CFG_POWER_DIS_D2_SHIFT 16
377 #define PORT_HW_CFG_POWER_DIS_D3_MASK 0xff000000
378 #define PORT_HW_CFG_POWER_DIS_D3_SHIFT 24
381 #define PORT_HW_CFG_POWER_CONS_D0_MASK 0x000000ff
382 #define PORT_HW_CFG_POWER_CONS_D0_SHIFT 0
383 #define PORT_HW_CFG_POWER_CONS_D1_MASK 0x0000ff00
384 #define PORT_HW_CFG_POWER_CONS_D1_SHIFT 8
385 #define PORT_HW_CFG_POWER_CONS_D2_MASK 0x00ff0000
386 #define PORT_HW_CFG_POWER_CONS_D2_SHIFT 16
387 #define PORT_HW_CFG_POWER_CONS_D3_MASK 0xff000000
388 #define PORT_HW_CFG_POWER_CONS_D3_SHIFT 24
391 #define PORT_HW_CFG_UPPERMAC_MASK 0x0000ffff
392 #define PORT_HW_CFG_UPPERMAC_SHIFT 0
395 u32 iscsi_mac_upper; /* Upper 16 bits are always zeroes */
398 u32 rdma_mac_upper; /* Upper 16 bits are always zeroes */
402 #define PORT_HW_CFG_SERDES_TX_DRV_PRE_EMPHASIS_MASK 0x0000ffff
403 #define PORT_HW_CFG_SERDES_TX_DRV_PRE_EMPHASIS_SHIFT 0
405 #define PORT_HW_CFG_SERDES_RX_DRV_EQUALIZER_MASK 0xffff0000
406 #define PORT_HW_CFG_SERDES_RX_DRV_EQUALIZER_SHIFT 16
409 /* Default values: 2P-64, 4P-32 */
410 u32 pf_config; /* 0x158 */
411 #define PORT_HW_CFG_PF_NUM_VF_MASK 0x0000007F
412 #define PORT_HW_CFG_PF_NUM_VF_SHIFT 0
414 /* Default values: 17 */
415 #define PORT_HW_CFG_PF_NUM_MSIX_VECTORS_MASK 0x00007F00
416 #define PORT_HW_CFG_PF_NUM_MSIX_VECTORS_SHIFT 8
418 #define PORT_HW_CFG_ENABLE_FLR_MASK 0x00010000
419 #define PORT_HW_CFG_FLR_ENABLED 0x00010000
421 u32 vf_config; /* 0x15C */
422 #define PORT_HW_CFG_VF_NUM_MSIX_VECTORS_MASK 0x0000007F
423 #define PORT_HW_CFG_VF_NUM_MSIX_VECTORS_SHIFT 0
425 #define PORT_HW_CFG_VF_PCI_DEVICE_ID_MASK 0xFFFF0000
426 #define PORT_HW_CFG_VF_PCI_DEVICE_ID_SHIFT 16
428 u32 mf_pci_id; /* 0x160 */
429 #define PORT_HW_CFG_MF_PCI_DEVICE_ID_MASK 0x0000FFFF
430 #define PORT_HW_CFG_MF_PCI_DEVICE_ID_SHIFT 0
432 /* Controls the TX laser of the SFP+ module */
433 u32 sfp_ctrl; /* 0x164 */
434 #define PORT_HW_CFG_TX_LASER_MASK 0x000000FF
435 #define PORT_HW_CFG_TX_LASER_SHIFT 0
436 #define PORT_HW_CFG_TX_LASER_MDIO 0x00000000
437 #define PORT_HW_CFG_TX_LASER_GPIO0 0x00000001
438 #define PORT_HW_CFG_TX_LASER_GPIO1 0x00000002
439 #define PORT_HW_CFG_TX_LASER_GPIO2 0x00000003
440 #define PORT_HW_CFG_TX_LASER_GPIO3 0x00000004
442 /* Controls the fault module LED of the SFP+ */
443 #define PORT_HW_CFG_FAULT_MODULE_LED_MASK 0x0000FF00
444 #define PORT_HW_CFG_FAULT_MODULE_LED_SHIFT 8
445 #define PORT_HW_CFG_FAULT_MODULE_LED_GPIO0 0x00000000
446 #define PORT_HW_CFG_FAULT_MODULE_LED_GPIO1 0x00000100
447 #define PORT_HW_CFG_FAULT_MODULE_LED_GPIO2 0x00000200
448 #define PORT_HW_CFG_FAULT_MODULE_LED_GPIO3 0x00000300
449 #define PORT_HW_CFG_FAULT_MODULE_LED_DISABLED 0x00000400
451 /* The output pin TX_DIS that controls the TX laser of the SFP+
452 module. Use the PIN_CFG_XXX defines on top */
453 u32 e3_sfp_ctrl; /* 0x168 */
454 #define PORT_HW_CFG_E3_TX_LASER_MASK 0x000000FF
455 #define PORT_HW_CFG_E3_TX_LASER_SHIFT 0
457 /* The output pin for SFPP_TYPE which turns on the Fault module LED */
458 #define PORT_HW_CFG_E3_FAULT_MDL_LED_MASK 0x0000FF00
459 #define PORT_HW_CFG_E3_FAULT_MDL_LED_SHIFT 8
461 /* The input pin MOD_ABS that indicates whether SFP+ module is
462 present or not. Use the PIN_CFG_XXX defines on top */
463 #define PORT_HW_CFG_E3_MOD_ABS_MASK 0x00FF0000
464 #define PORT_HW_CFG_E3_MOD_ABS_SHIFT 16
466 /* The output pin PWRDIS_SFP_X which disable the power of the SFP+
467 module. Use the PIN_CFG_XXX defines on top */
468 #define PORT_HW_CFG_E3_PWR_DIS_MASK 0xFF000000
469 #define PORT_HW_CFG_E3_PWR_DIS_SHIFT 24
472 * The input pin which signals module transmit fault. Use the
473 * PIN_CFG_XXX defines on top
475 u32 e3_cmn_pin_cfg; /* 0x16C */
476 #define PORT_HW_CFG_E3_TX_FAULT_MASK 0x000000FF
477 #define PORT_HW_CFG_E3_TX_FAULT_SHIFT 0
479 /* The output pin which reset the PHY. Use the PIN_CFG_XXX defines on
481 #define PORT_HW_CFG_E3_PHY_RESET_MASK 0x0000FF00
482 #define PORT_HW_CFG_E3_PHY_RESET_SHIFT 8
485 * The output pin which powers down the PHY. Use the PIN_CFG_XXX
488 #define PORT_HW_CFG_E3_PWR_DOWN_MASK 0x00FF0000
489 #define PORT_HW_CFG_E3_PWR_DOWN_SHIFT 16
491 /* The output pin values BSC_SEL which selects the I2C for this port
493 #define PORT_HW_CFG_E3_I2C_MUX0_MASK 0x01000000
494 #define PORT_HW_CFG_E3_I2C_MUX1_MASK 0x02000000
498 * The input pin I_FAULT which indicate over-current has occurred.
499 * Use the PIN_CFG_XXX defines on top
501 u32 e3_cmn_pin_cfg1; /* 0x170 */
502 #define PORT_HW_CFG_E3_OVER_CURRENT_MASK 0x000000FF
503 #define PORT_HW_CFG_E3_OVER_CURRENT_SHIFT 0
505 /* pause on host ring */
506 u32 generic_features; /* 0x174 */
507 #define PORT_HW_CFG_PAUSE_ON_HOST_RING_MASK 0x00000001
508 #define PORT_HW_CFG_PAUSE_ON_HOST_RING_SHIFT 0
509 #define PORT_HW_CFG_PAUSE_ON_HOST_RING_DISABLED 0x00000000
510 #define PORT_HW_CFG_PAUSE_ON_HOST_RING_ENABLED 0x00000001
512 /* SFP+ Tx Equalization: NIC recommended and tested value is 0xBEB2
513 * LOM recommended and tested value is 0xBEB2. Using a different
514 * value means using a value not tested by BRCM
516 u32 sfi_tap_values; /* 0x178 */
517 #define PORT_HW_CFG_TX_EQUALIZATION_MASK 0x0000FFFF
518 #define PORT_HW_CFG_TX_EQUALIZATION_SHIFT 0
520 /* SFP+ Tx driver broadcast IDRIVER: NIC recommended and tested
521 * value is 0x2. LOM recommended and tested value is 0x2. Using a
522 * different value means using a value not tested by BRCM
524 #define PORT_HW_CFG_TX_DRV_BROADCAST_MASK 0x000F0000
525 #define PORT_HW_CFG_TX_DRV_BROADCAST_SHIFT 16
526 /* Set non-default values for TXFIR in SFP mode. */
527 #define PORT_HW_CFG_TX_DRV_IFIR_MASK 0x00F00000
528 #define PORT_HW_CFG_TX_DRV_IFIR_SHIFT 20
530 /* Set non-default values for IPREDRIVER in SFP mode. */
531 #define PORT_HW_CFG_TX_DRV_IPREDRIVER_MASK 0x0F000000
532 #define PORT_HW_CFG_TX_DRV_IPREDRIVER_SHIFT 24
534 /* Set non-default values for POST2 in SFP mode. */
535 #define PORT_HW_CFG_TX_DRV_POST2_MASK 0xF0000000
536 #define PORT_HW_CFG_TX_DRV_POST2_SHIFT 28
538 u32 reserved0[5]; /* 0x17c */
540 u32 aeu_int_mask; /* 0x190 */
542 u32 media_type; /* 0x194 */
543 #define PORT_HW_CFG_MEDIA_TYPE_PHY0_MASK 0x000000FF
544 #define PORT_HW_CFG_MEDIA_TYPE_PHY0_SHIFT 0
546 #define PORT_HW_CFG_MEDIA_TYPE_PHY1_MASK 0x0000FF00
547 #define PORT_HW_CFG_MEDIA_TYPE_PHY1_SHIFT 8
549 #define PORT_HW_CFG_MEDIA_TYPE_PHY2_MASK 0x00FF0000
550 #define PORT_HW_CFG_MEDIA_TYPE_PHY2_SHIFT 16
552 /* 4 times 16 bits for all 4 lanes. In case external PHY is present
553 (not direct mode), those values will not take effect on the 4 XGXS
554 lanes. For some external PHYs (such as 8706 and 8726) the values
555 will be used to configure the external PHY in those cases, not
556 all 4 values are needed. */
557 u16 xgxs_config_rx[4]; /* 0x198 */
558 u16 xgxs_config_tx[4]; /* 0x1A0 */
560 /* For storing FCOE mac on shared memory */
561 u32 fcoe_fip_mac_upper;
562 #define PORT_HW_CFG_FCOE_UPPERMAC_MASK 0x0000ffff
563 #define PORT_HW_CFG_FCOE_UPPERMAC_SHIFT 0
564 u32 fcoe_fip_mac_lower;
566 u32 fcoe_wwn_port_name_upper;
567 u32 fcoe_wwn_port_name_lower;
569 u32 fcoe_wwn_node_name_upper;
570 u32 fcoe_wwn_node_name_lower;
572 u32 Reserved1[49]; /* 0x1C0 */
574 /* Enable RJ45 magjack pair swapping on 10GBase-T PHY (0=default),
576 u32 xgbt_phy_cfg; /* 0x284 */
577 #define PORT_HW_CFG_RJ45_PAIR_SWAP_MASK 0x000000FF
578 #define PORT_HW_CFG_RJ45_PAIR_SWAP_SHIFT 0
580 u32 default_cfg; /* 0x288 */
581 #define PORT_HW_CFG_GPIO0_CONFIG_MASK 0x00000003
582 #define PORT_HW_CFG_GPIO0_CONFIG_SHIFT 0
583 #define PORT_HW_CFG_GPIO0_CONFIG_NA 0x00000000
584 #define PORT_HW_CFG_GPIO0_CONFIG_LOW 0x00000001
585 #define PORT_HW_CFG_GPIO0_CONFIG_HIGH 0x00000002
586 #define PORT_HW_CFG_GPIO0_CONFIG_INPUT 0x00000003
588 #define PORT_HW_CFG_GPIO1_CONFIG_MASK 0x0000000C
589 #define PORT_HW_CFG_GPIO1_CONFIG_SHIFT 2
590 #define PORT_HW_CFG_GPIO1_CONFIG_NA 0x00000000
591 #define PORT_HW_CFG_GPIO1_CONFIG_LOW 0x00000004
592 #define PORT_HW_CFG_GPIO1_CONFIG_HIGH 0x00000008
593 #define PORT_HW_CFG_GPIO1_CONFIG_INPUT 0x0000000c
595 #define PORT_HW_CFG_GPIO2_CONFIG_MASK 0x00000030
596 #define PORT_HW_CFG_GPIO2_CONFIG_SHIFT 4
597 #define PORT_HW_CFG_GPIO2_CONFIG_NA 0x00000000
598 #define PORT_HW_CFG_GPIO2_CONFIG_LOW 0x00000010
599 #define PORT_HW_CFG_GPIO2_CONFIG_HIGH 0x00000020
600 #define PORT_HW_CFG_GPIO2_CONFIG_INPUT 0x00000030
602 #define PORT_HW_CFG_GPIO3_CONFIG_MASK 0x000000C0
603 #define PORT_HW_CFG_GPIO3_CONFIG_SHIFT 6
604 #define PORT_HW_CFG_GPIO3_CONFIG_NA 0x00000000
605 #define PORT_HW_CFG_GPIO3_CONFIG_LOW 0x00000040
606 #define PORT_HW_CFG_GPIO3_CONFIG_HIGH 0x00000080
607 #define PORT_HW_CFG_GPIO3_CONFIG_INPUT 0x000000c0
609 /* When KR link is required to be set to force which is not
610 KR-compliant, this parameter determine what is the trigger for it.
611 When GPIO is selected, low input will force the speed. Currently
612 default speed is 1G. In the future, it may be widen to select the
613 forced speed in with another parameter. Note when force-1G is
614 enabled, it override option 56: Link Speed option. */
615 #define PORT_HW_CFG_FORCE_KR_ENABLER_MASK 0x00000F00
616 #define PORT_HW_CFG_FORCE_KR_ENABLER_SHIFT 8
617 #define PORT_HW_CFG_FORCE_KR_ENABLER_NOT_FORCED 0x00000000
618 #define PORT_HW_CFG_FORCE_KR_ENABLER_GPIO0_P0 0x00000100
619 #define PORT_HW_CFG_FORCE_KR_ENABLER_GPIO1_P0 0x00000200
620 #define PORT_HW_CFG_FORCE_KR_ENABLER_GPIO2_P0 0x00000300
621 #define PORT_HW_CFG_FORCE_KR_ENABLER_GPIO3_P0 0x00000400
622 #define PORT_HW_CFG_FORCE_KR_ENABLER_GPIO0_P1 0x00000500
623 #define PORT_HW_CFG_FORCE_KR_ENABLER_GPIO1_P1 0x00000600
624 #define PORT_HW_CFG_FORCE_KR_ENABLER_GPIO2_P1 0x00000700
625 #define PORT_HW_CFG_FORCE_KR_ENABLER_GPIO3_P1 0x00000800
626 #define PORT_HW_CFG_FORCE_KR_ENABLER_FORCED 0x00000900
627 /* Enable to determine with which GPIO to reset the external phy */
628 #define PORT_HW_CFG_EXT_PHY_GPIO_RST_MASK 0x000F0000
629 #define PORT_HW_CFG_EXT_PHY_GPIO_RST_SHIFT 16
630 #define PORT_HW_CFG_EXT_PHY_GPIO_RST_PHY_TYPE 0x00000000
631 #define PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO0_P0 0x00010000
632 #define PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO1_P0 0x00020000
633 #define PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO2_P0 0x00030000
634 #define PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO3_P0 0x00040000
635 #define PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO0_P1 0x00050000
636 #define PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO1_P1 0x00060000
637 #define PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO2_P1 0x00070000
638 #define PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO3_P1 0x00080000
640 /* Enable BAM on KR */
641 #define PORT_HW_CFG_ENABLE_BAM_ON_KR_MASK 0x00100000
642 #define PORT_HW_CFG_ENABLE_BAM_ON_KR_SHIFT 20
643 #define PORT_HW_CFG_ENABLE_BAM_ON_KR_DISABLED 0x00000000
644 #define PORT_HW_CFG_ENABLE_BAM_ON_KR_ENABLED 0x00100000
646 /* Enable Common Mode Sense */
647 #define PORT_HW_CFG_ENABLE_CMS_MASK 0x00200000
648 #define PORT_HW_CFG_ENABLE_CMS_SHIFT 21
649 #define PORT_HW_CFG_ENABLE_CMS_DISABLED 0x00000000
650 #define PORT_HW_CFG_ENABLE_CMS_ENABLED 0x00200000
652 /* Determine the Serdes electrical interface */
653 #define PORT_HW_CFG_NET_SERDES_IF_MASK 0x0F000000
654 #define PORT_HW_CFG_NET_SERDES_IF_SHIFT 24
655 #define PORT_HW_CFG_NET_SERDES_IF_SGMII 0x00000000
656 #define PORT_HW_CFG_NET_SERDES_IF_XFI 0x01000000
657 #define PORT_HW_CFG_NET_SERDES_IF_SFI 0x02000000
658 #define PORT_HW_CFG_NET_SERDES_IF_KR 0x03000000
659 #define PORT_HW_CFG_NET_SERDES_IF_DXGXS 0x04000000
660 #define PORT_HW_CFG_NET_SERDES_IF_KR2 0x05000000
663 u32 speed_capability_mask2; /* 0x28C */
664 #define PORT_HW_CFG_SPEED_CAPABILITY2_D3_MASK 0x0000FFFF
665 #define PORT_HW_CFG_SPEED_CAPABILITY2_D3_SHIFT 0
666 #define PORT_HW_CFG_SPEED_CAPABILITY2_D3_10M_FULL 0x00000001
667 #define PORT_HW_CFG_SPEED_CAPABILITY2_D3__ 0x00000002
668 #define PORT_HW_CFG_SPEED_CAPABILITY2_D3___ 0x00000004
669 #define PORT_HW_CFG_SPEED_CAPABILITY2_D3_100M_FULL 0x00000008
670 #define PORT_HW_CFG_SPEED_CAPABILITY2_D3_1G 0x00000010
671 #define PORT_HW_CFG_SPEED_CAPABILITY2_D3_2_DOT_5G 0x00000020
672 #define PORT_HW_CFG_SPEED_CAPABILITY2_D3_10G 0x00000040
673 #define PORT_HW_CFG_SPEED_CAPABILITY2_D3_20G 0x00000080
675 #define PORT_HW_CFG_SPEED_CAPABILITY2_D0_MASK 0xFFFF0000
676 #define PORT_HW_CFG_SPEED_CAPABILITY2_D0_SHIFT 16
677 #define PORT_HW_CFG_SPEED_CAPABILITY2_D0_10M_FULL 0x00010000
678 #define PORT_HW_CFG_SPEED_CAPABILITY2_D0__ 0x00020000
679 #define PORT_HW_CFG_SPEED_CAPABILITY2_D0___ 0x00040000
680 #define PORT_HW_CFG_SPEED_CAPABILITY2_D0_100M_FULL 0x00080000
681 #define PORT_HW_CFG_SPEED_CAPABILITY2_D0_1G 0x00100000
682 #define PORT_HW_CFG_SPEED_CAPABILITY2_D0_2_DOT_5G 0x00200000
683 #define PORT_HW_CFG_SPEED_CAPABILITY2_D0_10G 0x00400000
684 #define PORT_HW_CFG_SPEED_CAPABILITY2_D0_20G 0x00800000
687 /* In the case where two media types (e.g. copper and fiber) are
688 present and electrically active at the same time, PHY Selection
689 will determine which of the two PHYs will be designated as the
690 Active PHY and used for a connection to the network. */
691 u32 multi_phy_config; /* 0x290 */
692 #define PORT_HW_CFG_PHY_SELECTION_MASK 0x00000007
693 #define PORT_HW_CFG_PHY_SELECTION_SHIFT 0
694 #define PORT_HW_CFG_PHY_SELECTION_HARDWARE_DEFAULT 0x00000000
695 #define PORT_HW_CFG_PHY_SELECTION_FIRST_PHY 0x00000001
696 #define PORT_HW_CFG_PHY_SELECTION_SECOND_PHY 0x00000002
697 #define PORT_HW_CFG_PHY_SELECTION_FIRST_PHY_PRIORITY 0x00000003
698 #define PORT_HW_CFG_PHY_SELECTION_SECOND_PHY_PRIORITY 0x00000004
700 /* When enabled, all second phy nvram parameters will be swapped
701 with the first phy parameters */
702 #define PORT_HW_CFG_PHY_SWAPPED_MASK 0x00000008
703 #define PORT_HW_CFG_PHY_SWAPPED_SHIFT 3
704 #define PORT_HW_CFG_PHY_SWAPPED_DISABLED 0x00000000
705 #define PORT_HW_CFG_PHY_SWAPPED_ENABLED 0x00000008
708 /* Address of the second external phy */
709 u32 external_phy_config2; /* 0x294 */
710 #define PORT_HW_CFG_XGXS_EXT_PHY2_ADDR_MASK 0x000000FF
711 #define PORT_HW_CFG_XGXS_EXT_PHY2_ADDR_SHIFT 0
713 /* The second XGXS external PHY type */
714 #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_MASK 0x0000FF00
715 #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_SHIFT 8
716 #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_DIRECT 0x00000000
717 #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_BCM8071 0x00000100
718 #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_BCM8072 0x00000200
719 #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_BCM8073 0x00000300
720 #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_BCM8705 0x00000400
721 #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_BCM8706 0x00000500
722 #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_BCM8726 0x00000600
723 #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_BCM8481 0x00000700
724 #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_SFX7101 0x00000800
725 #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_BCM8727 0x00000900
726 #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_BCM8727_NOC 0x00000a00
727 #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_BCM84823 0x00000b00
728 #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_BCM54640 0x00000c00
729 #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_BCM84833 0x00000d00
730 #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_BCM54618SE 0x00000e00
731 #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_BCM8722 0x00000f00
732 #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_BCM54616 0x00001000
733 #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_BCM84834 0x00001100
734 #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_FAILURE 0x0000fd00
735 #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_NOT_CONN 0x0000ff00
738 /* 4 times 16 bits for all 4 lanes. For some external PHYs (such as
739 8706, 8726 and 8727) not all 4 values are needed. */
740 u16 xgxs_config2_rx[4]; /* 0x296 */
741 u16 xgxs_config2_tx[4]; /* 0x2A0 */
744 #define PORT_HW_CFG_LANE_SWAP_CFG_MASK 0x0000ffff
745 #define PORT_HW_CFG_LANE_SWAP_CFG_SHIFT 0
747 #define PORT_HW_CFG_LANE_SWAP_CFG_01230123 0x00001b1b
749 #define PORT_HW_CFG_LANE_SWAP_CFG_01233210 0x00001be4
751 #define PORT_HW_CFG_LANE_SWAP_CFG_31203120 0x0000d8d8
753 #define PORT_HW_CFG_LANE_SWAP_CFG_32103210 0x0000e4e4
754 #define PORT_HW_CFG_LANE_SWAP_CFG_TX_MASK 0x000000ff
755 #define PORT_HW_CFG_LANE_SWAP_CFG_TX_SHIFT 0
756 #define PORT_HW_CFG_LANE_SWAP_CFG_RX_MASK 0x0000ff00
757 #define PORT_HW_CFG_LANE_SWAP_CFG_RX_SHIFT 8
758 #define PORT_HW_CFG_LANE_SWAP_CFG_MASTER_MASK 0x0000c000
759 #define PORT_HW_CFG_LANE_SWAP_CFG_MASTER_SHIFT 14
761 /* Indicate whether to swap the external phy polarity */
762 #define PORT_HW_CFG_SWAP_PHY_POLARITY_MASK 0x00010000
763 #define PORT_HW_CFG_SWAP_PHY_POLARITY_DISABLED 0x00000000
764 #define PORT_HW_CFG_SWAP_PHY_POLARITY_ENABLED 0x00010000
767 u32 external_phy_config;
768 #define PORT_HW_CFG_XGXS_EXT_PHY_ADDR_MASK 0x000000ff
769 #define PORT_HW_CFG_XGXS_EXT_PHY_ADDR_SHIFT 0
771 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_MASK 0x0000ff00
772 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_SHIFT 8
773 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT 0x00000000
774 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8071 0x00000100
775 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8072 0x00000200
776 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073 0x00000300
777 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8705 0x00000400
778 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8706 0x00000500
779 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8726 0x00000600
780 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8481 0x00000700
781 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_SFX7101 0x00000800
782 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727 0x00000900
783 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727_NOC 0x00000a00
784 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84823 0x00000b00
785 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM54640 0x00000c00
786 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84833 0x00000d00
787 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM54618SE 0x00000e00
788 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8722 0x00000f00
789 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM54616 0x00001000
790 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84834 0x00001100
791 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT_WC 0x0000fc00
792 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_FAILURE 0x0000fd00
793 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_NOT_CONN 0x0000ff00
795 #define PORT_HW_CFG_SERDES_EXT_PHY_ADDR_MASK 0x00ff0000
796 #define PORT_HW_CFG_SERDES_EXT_PHY_ADDR_SHIFT 16
798 #define PORT_HW_CFG_SERDES_EXT_PHY_TYPE_MASK 0xff000000
799 #define PORT_HW_CFG_SERDES_EXT_PHY_TYPE_SHIFT 24
800 #define PORT_HW_CFG_SERDES_EXT_PHY_TYPE_DIRECT 0x00000000
801 #define PORT_HW_CFG_SERDES_EXT_PHY_TYPE_BCM5482 0x01000000
802 #define PORT_HW_CFG_SERDES_EXT_PHY_TYPE_DIRECT_SD 0x02000000
803 #define PORT_HW_CFG_SERDES_EXT_PHY_TYPE_NOT_CONN 0xff000000
805 u32 speed_capability_mask;
806 #define PORT_HW_CFG_SPEED_CAPABILITY_D3_MASK 0x0000ffff
807 #define PORT_HW_CFG_SPEED_CAPABILITY_D3_SHIFT 0
808 #define PORT_HW_CFG_SPEED_CAPABILITY_D3_10M_FULL 0x00000001
809 #define PORT_HW_CFG_SPEED_CAPABILITY_D3_10M_HALF 0x00000002
810 #define PORT_HW_CFG_SPEED_CAPABILITY_D3_100M_HALF 0x00000004
811 #define PORT_HW_CFG_SPEED_CAPABILITY_D3_100M_FULL 0x00000008
812 #define PORT_HW_CFG_SPEED_CAPABILITY_D3_1G 0x00000010
813 #define PORT_HW_CFG_SPEED_CAPABILITY_D3_2_5G 0x00000020
814 #define PORT_HW_CFG_SPEED_CAPABILITY_D3_10G 0x00000040
815 #define PORT_HW_CFG_SPEED_CAPABILITY_D3_20G 0x00000080
816 #define PORT_HW_CFG_SPEED_CAPABILITY_D3_RESERVED 0x0000f000
818 #define PORT_HW_CFG_SPEED_CAPABILITY_D0_MASK 0xffff0000
819 #define PORT_HW_CFG_SPEED_CAPABILITY_D0_SHIFT 16
820 #define PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_FULL 0x00010000
821 #define PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_HALF 0x00020000
822 #define PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_HALF 0x00040000
823 #define PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_FULL 0x00080000
824 #define PORT_HW_CFG_SPEED_CAPABILITY_D0_1G 0x00100000
825 #define PORT_HW_CFG_SPEED_CAPABILITY_D0_2_5G 0x00200000
826 #define PORT_HW_CFG_SPEED_CAPABILITY_D0_10G 0x00400000
827 #define PORT_HW_CFG_SPEED_CAPABILITY_D0_20G 0x00800000
828 #define PORT_HW_CFG_SPEED_CAPABILITY_D0_RESERVED 0xf0000000
830 /* A place to hold the original MAC address as a backup */
831 u32 backup_mac_upper; /* 0x2B4 */
832 u32 backup_mac_lower; /* 0x2B8 */
837 /****************************************************************************
838 * Shared Feature configuration *
839 ****************************************************************************/
840 struct shared_feat_cfg { /* NVRAM Offset */
842 u32 config; /* 0x450 */
843 #define SHARED_FEATURE_BMC_ECHO_MODE_EN 0x00000001
845 /* Use NVRAM values instead of HW default values */
846 #define SHARED_FEAT_CFG_OVERRIDE_PREEMPHASIS_CFG_MASK \
848 #define SHARED_FEAT_CFG_OVERRIDE_PREEMPHASIS_CFG_DISABLED \
850 #define SHARED_FEAT_CFG_OVERRIDE_PREEMPHASIS_CFG_ENABLED \
853 #define SHARED_FEAT_CFG_NCSI_ID_METHOD_MASK 0x00000008
854 #define SHARED_FEAT_CFG_NCSI_ID_METHOD_SPIO 0x00000000
855 #define SHARED_FEAT_CFG_NCSI_ID_METHOD_NVRAM 0x00000008
857 #define SHARED_FEAT_CFG_NCSI_ID_MASK 0x00000030
858 #define SHARED_FEAT_CFG_NCSI_ID_SHIFT 4
860 /* Override the OTP back to single function mode. When using GPIO,
861 high means only SF, 0 is according to CLP configuration */
862 #define SHARED_FEAT_CFG_FORCE_SF_MODE_MASK 0x00000700
863 #define SHARED_FEAT_CFG_FORCE_SF_MODE_SHIFT 8
864 #define SHARED_FEAT_CFG_FORCE_SF_MODE_MF_ALLOWED 0x00000000
865 #define SHARED_FEAT_CFG_FORCE_SF_MODE_FORCED_SF 0x00000100
866 #define SHARED_FEAT_CFG_FORCE_SF_MODE_SPIO4 0x00000200
867 #define SHARED_FEAT_CFG_FORCE_SF_MODE_SWITCH_INDEPT 0x00000300
868 #define SHARED_FEAT_CFG_FORCE_SF_MODE_AFEX_MODE 0x00000400
869 #define SHARED_FEAT_CFG_FORCE_SF_MODE_UFP_MODE 0x00000600
870 #define SHARED_FEAT_CFG_FORCE_SF_MODE_EXTENDED_MODE 0x00000700
872 /* The interval in seconds between sending LLDP packets. Set to zero
873 to disable the feature */
874 #define SHARED_FEAT_CFG_LLDP_XMIT_INTERVAL_MASK 0x00ff0000
875 #define SHARED_FEAT_CFG_LLDP_XMIT_INTERVAL_SHIFT 16
877 /* The assigned device type ID for LLDP usage */
878 #define SHARED_FEAT_CFG_LLDP_DEVICE_TYPE_ID_MASK 0xff000000
879 #define SHARED_FEAT_CFG_LLDP_DEVICE_TYPE_ID_SHIFT 24
884 /****************************************************************************
885 * Port Feature configuration *
886 ****************************************************************************/
887 struct port_feat_cfg { /* port 0: 0x454 port 1: 0x4c8 */
890 #define PORT_FEATURE_BAR1_SIZE_MASK 0x0000000f
891 #define PORT_FEATURE_BAR1_SIZE_SHIFT 0
892 #define PORT_FEATURE_BAR1_SIZE_DISABLED 0x00000000
893 #define PORT_FEATURE_BAR1_SIZE_64K 0x00000001
894 #define PORT_FEATURE_BAR1_SIZE_128K 0x00000002
895 #define PORT_FEATURE_BAR1_SIZE_256K 0x00000003
896 #define PORT_FEATURE_BAR1_SIZE_512K 0x00000004
897 #define PORT_FEATURE_BAR1_SIZE_1M 0x00000005
898 #define PORT_FEATURE_BAR1_SIZE_2M 0x00000006
899 #define PORT_FEATURE_BAR1_SIZE_4M 0x00000007
900 #define PORT_FEATURE_BAR1_SIZE_8M 0x00000008
901 #define PORT_FEATURE_BAR1_SIZE_16M 0x00000009
902 #define PORT_FEATURE_BAR1_SIZE_32M 0x0000000a
903 #define PORT_FEATURE_BAR1_SIZE_64M 0x0000000b
904 #define PORT_FEATURE_BAR1_SIZE_128M 0x0000000c
905 #define PORT_FEATURE_BAR1_SIZE_256M 0x0000000d
906 #define PORT_FEATURE_BAR1_SIZE_512M 0x0000000e
907 #define PORT_FEATURE_BAR1_SIZE_1G 0x0000000f
908 #define PORT_FEATURE_BAR2_SIZE_MASK 0x000000f0
909 #define PORT_FEATURE_BAR2_SIZE_SHIFT 4
910 #define PORT_FEATURE_BAR2_SIZE_DISABLED 0x00000000
911 #define PORT_FEATURE_BAR2_SIZE_64K 0x00000010
912 #define PORT_FEATURE_BAR2_SIZE_128K 0x00000020
913 #define PORT_FEATURE_BAR2_SIZE_256K 0x00000030
914 #define PORT_FEATURE_BAR2_SIZE_512K 0x00000040
915 #define PORT_FEATURE_BAR2_SIZE_1M 0x00000050
916 #define PORT_FEATURE_BAR2_SIZE_2M 0x00000060
917 #define PORT_FEATURE_BAR2_SIZE_4M 0x00000070
918 #define PORT_FEATURE_BAR2_SIZE_8M 0x00000080
919 #define PORT_FEATURE_BAR2_SIZE_16M 0x00000090
920 #define PORT_FEATURE_BAR2_SIZE_32M 0x000000a0
921 #define PORT_FEATURE_BAR2_SIZE_64M 0x000000b0
922 #define PORT_FEATURE_BAR2_SIZE_128M 0x000000c0
923 #define PORT_FEATURE_BAR2_SIZE_256M 0x000000d0
924 #define PORT_FEATURE_BAR2_SIZE_512M 0x000000e0
925 #define PORT_FEATURE_BAR2_SIZE_1G 0x000000f0
927 #define PORT_FEAT_CFG_DCBX_MASK 0x00000100
928 #define PORT_FEAT_CFG_DCBX_DISABLED 0x00000000
929 #define PORT_FEAT_CFG_DCBX_ENABLED 0x00000100
931 #define PORT_FEAT_CFG_STORAGE_PERSONALITY_MASK 0x00000C00
932 #define PORT_FEAT_CFG_STORAGE_PERSONALITY_FCOE 0x00000400
933 #define PORT_FEAT_CFG_STORAGE_PERSONALITY_ISCSI 0x00000800
935 #define PORT_FEATURE_EN_SIZE_MASK 0x0f000000
936 #define PORT_FEATURE_EN_SIZE_SHIFT 24
937 #define PORT_FEATURE_WOL_ENABLED 0x01000000
938 #define PORT_FEATURE_MBA_ENABLED 0x02000000
939 #define PORT_FEATURE_MFW_ENABLED 0x04000000
941 /* Advertise expansion ROM even if MBA is disabled */
942 #define PORT_FEAT_CFG_FORCE_EXP_ROM_ADV_MASK 0x08000000
943 #define PORT_FEAT_CFG_FORCE_EXP_ROM_ADV_DISABLED 0x00000000
944 #define PORT_FEAT_CFG_FORCE_EXP_ROM_ADV_ENABLED 0x08000000
946 /* Check the optic vendor via i2c against a list of approved modules
947 in a separate nvram image */
948 #define PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_MASK 0xe0000000
949 #define PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_SHIFT 29
950 #define PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_NO_ENFORCEMENT \
952 #define PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_DISABLE_TX_LASER \
954 #define PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_WARNING_MSG 0x40000000
955 #define PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_POWER_DOWN 0x60000000
958 /* Default is used when driver sets to "auto" mode */
959 #define PORT_FEATURE_WOL_DEFAULT_MASK 0x00000003
960 #define PORT_FEATURE_WOL_DEFAULT_SHIFT 0
961 #define PORT_FEATURE_WOL_DEFAULT_DISABLE 0x00000000
962 #define PORT_FEATURE_WOL_DEFAULT_MAGIC 0x00000001
963 #define PORT_FEATURE_WOL_DEFAULT_ACPI 0x00000002
964 #define PORT_FEATURE_WOL_DEFAULT_MAGIC_AND_ACPI 0x00000003
965 #define PORT_FEATURE_WOL_RES_PAUSE_CAP 0x00000004
966 #define PORT_FEATURE_WOL_RES_ASYM_PAUSE_CAP 0x00000008
967 #define PORT_FEATURE_WOL_ACPI_UPON_MGMT 0x00000010
970 #define PORT_FEATURE_MBA_BOOT_AGENT_TYPE_MASK 0x00000007
971 #define PORT_FEATURE_MBA_BOOT_AGENT_TYPE_SHIFT 0
972 #define PORT_FEATURE_MBA_BOOT_AGENT_TYPE_PXE 0x00000000
973 #define PORT_FEATURE_MBA_BOOT_AGENT_TYPE_RPL 0x00000001
974 #define PORT_FEATURE_MBA_BOOT_AGENT_TYPE_BOOTP 0x00000002
975 #define PORT_FEATURE_MBA_BOOT_AGENT_TYPE_ISCSIB 0x00000003
976 #define PORT_FEATURE_MBA_BOOT_AGENT_TYPE_FCOE_BOOT 0x00000004
977 #define PORT_FEATURE_MBA_BOOT_AGENT_TYPE_NONE 0x00000007
979 #define PORT_FEATURE_MBA_BOOT_RETRY_MASK 0x00000038
980 #define PORT_FEATURE_MBA_BOOT_RETRY_SHIFT 3
982 #define PORT_FEATURE_MBA_RES_PAUSE_CAP 0x00000100
983 #define PORT_FEATURE_MBA_RES_ASYM_PAUSE_CAP 0x00000200
984 #define PORT_FEATURE_MBA_SETUP_PROMPT_ENABLE 0x00000400
985 #define PORT_FEATURE_MBA_HOTKEY_MASK 0x00000800
986 #define PORT_FEATURE_MBA_HOTKEY_CTRL_S 0x00000000
987 #define PORT_FEATURE_MBA_HOTKEY_CTRL_B 0x00000800
988 #define PORT_FEATURE_MBA_EXP_ROM_SIZE_MASK 0x000ff000
989 #define PORT_FEATURE_MBA_EXP_ROM_SIZE_SHIFT 12
990 #define PORT_FEATURE_MBA_EXP_ROM_SIZE_DISABLED 0x00000000
991 #define PORT_FEATURE_MBA_EXP_ROM_SIZE_2K 0x00001000
992 #define PORT_FEATURE_MBA_EXP_ROM_SIZE_4K 0x00002000
993 #define PORT_FEATURE_MBA_EXP_ROM_SIZE_8K 0x00003000
994 #define PORT_FEATURE_MBA_EXP_ROM_SIZE_16K 0x00004000
995 #define PORT_FEATURE_MBA_EXP_ROM_SIZE_32K 0x00005000
996 #define PORT_FEATURE_MBA_EXP_ROM_SIZE_64K 0x00006000
997 #define PORT_FEATURE_MBA_EXP_ROM_SIZE_128K 0x00007000
998 #define PORT_FEATURE_MBA_EXP_ROM_SIZE_256K 0x00008000
999 #define PORT_FEATURE_MBA_EXP_ROM_SIZE_512K 0x00009000
1000 #define PORT_FEATURE_MBA_EXP_ROM_SIZE_1M 0x0000a000
1001 #define PORT_FEATURE_MBA_EXP_ROM_SIZE_2M 0x0000b000
1002 #define PORT_FEATURE_MBA_EXP_ROM_SIZE_4M 0x0000c000
1003 #define PORT_FEATURE_MBA_EXP_ROM_SIZE_8M 0x0000d000
1004 #define PORT_FEATURE_MBA_EXP_ROM_SIZE_16M 0x0000e000
1005 #define PORT_FEATURE_MBA_EXP_ROM_SIZE_32M 0x0000f000
1006 #define PORT_FEATURE_MBA_MSG_TIMEOUT_MASK 0x00f00000
1007 #define PORT_FEATURE_MBA_MSG_TIMEOUT_SHIFT 20
1008 #define PORT_FEATURE_MBA_BIOS_BOOTSTRAP_MASK 0x03000000
1009 #define PORT_FEATURE_MBA_BIOS_BOOTSTRAP_SHIFT 24
1010 #define PORT_FEATURE_MBA_BIOS_BOOTSTRAP_AUTO 0x00000000
1011 #define PORT_FEATURE_MBA_BIOS_BOOTSTRAP_BBS 0x01000000
1012 #define PORT_FEATURE_MBA_BIOS_BOOTSTRAP_INT18H 0x02000000
1013 #define PORT_FEATURE_MBA_BIOS_BOOTSTRAP_INT19H 0x03000000
1014 #define PORT_FEATURE_MBA_LINK_SPEED_MASK 0x3c000000
1015 #define PORT_FEATURE_MBA_LINK_SPEED_SHIFT 26
1016 #define PORT_FEATURE_MBA_LINK_SPEED_AUTO 0x00000000
1017 #define PORT_FEATURE_MBA_LINK_SPEED_10HD 0x04000000
1018 #define PORT_FEATURE_MBA_LINK_SPEED_10FD 0x08000000
1019 #define PORT_FEATURE_MBA_LINK_SPEED_100HD 0x0c000000
1020 #define PORT_FEATURE_MBA_LINK_SPEED_100FD 0x10000000
1021 #define PORT_FEATURE_MBA_LINK_SPEED_1GBPS 0x14000000
1022 #define PORT_FEATURE_MBA_LINK_SPEED_2_5GBPS 0x18000000
1023 #define PORT_FEATURE_MBA_LINK_SPEED_10GBPS_CX4 0x1c000000
1024 #define PORT_FEATURE_MBA_LINK_SPEED_20GBPS 0x20000000
1026 #define PORT_FEATURE_BMC_LINK_OVERRIDE_MASK 0x00000001
1027 #define PORT_FEATURE_BMC_LINK_OVERRIDE_DEFAULT 0x00000000
1028 #define PORT_FEATURE_BMC_LINK_OVERRIDE_EN 0x00000001
1031 #define PORT_FEATURE_MBA_VLAN_TAG_MASK 0x0000ffff
1032 #define PORT_FEATURE_MBA_VLAN_TAG_SHIFT 0
1033 #define PORT_FEATURE_MBA_VLAN_EN 0x00010000
1036 #define PORT_FEATURE_RESOURCE_CFG_VALID 0x00000001
1037 #define PORT_FEATURE_RESOURCE_CFG_DIAG 0x00000002
1038 #define PORT_FEATURE_RESOURCE_CFG_L2 0x00000004
1039 #define PORT_FEATURE_RESOURCE_CFG_ISCSI 0x00000008
1040 #define PORT_FEATURE_RESOURCE_CFG_RDMA 0x00000010
1043 #define PORT_FEATURE_SMBUS_ADDR_MASK 0x000000fe
1044 #define PORT_FEATURE_SMBUS_ADDR_SHIFT 1
1047 #define PORT_FEAT_CFG_VF_BAR2_SIZE_MASK 0x0000000f
1048 #define PORT_FEAT_CFG_VF_BAR2_SIZE_SHIFT 0
1049 #define PORT_FEAT_CFG_VF_BAR2_SIZE_DISABLED 0x00000000
1050 #define PORT_FEAT_CFG_VF_BAR2_SIZE_4K 0x00000001
1051 #define PORT_FEAT_CFG_VF_BAR2_SIZE_8K 0x00000002
1052 #define PORT_FEAT_CFG_VF_BAR2_SIZE_16K 0x00000003
1053 #define PORT_FEAT_CFG_VF_BAR2_SIZE_32K 0x00000004
1054 #define PORT_FEAT_CFG_VF_BAR2_SIZE_64K 0x00000005
1055 #define PORT_FEAT_CFG_VF_BAR2_SIZE_128K 0x00000006
1056 #define PORT_FEAT_CFG_VF_BAR2_SIZE_256K 0x00000007
1057 #define PORT_FEAT_CFG_VF_BAR2_SIZE_512K 0x00000008
1058 #define PORT_FEAT_CFG_VF_BAR2_SIZE_1M 0x00000009
1059 #define PORT_FEAT_CFG_VF_BAR2_SIZE_2M 0x0000000a
1060 #define PORT_FEAT_CFG_VF_BAR2_SIZE_4M 0x0000000b
1061 #define PORT_FEAT_CFG_VF_BAR2_SIZE_8M 0x0000000c
1062 #define PORT_FEAT_CFG_VF_BAR2_SIZE_16M 0x0000000d
1063 #define PORT_FEAT_CFG_VF_BAR2_SIZE_32M 0x0000000e
1064 #define PORT_FEAT_CFG_VF_BAR2_SIZE_64M 0x0000000f
1066 u32 link_config; /* Used as HW defaults for the driver */
1067 #define PORT_FEATURE_CONNECTED_SWITCH_MASK 0x03000000
1068 #define PORT_FEATURE_CONNECTED_SWITCH_SHIFT 24
1069 /* (forced) low speed switch (< 10G) */
1070 #define PORT_FEATURE_CON_SWITCH_1G_SWITCH 0x00000000
1071 /* (forced) high speed switch (>= 10G) */
1072 #define PORT_FEATURE_CON_SWITCH_10G_SWITCH 0x01000000
1073 #define PORT_FEATURE_CON_SWITCH_AUTO_DETECT 0x02000000
1074 #define PORT_FEATURE_CON_SWITCH_ONE_TIME_DETECT 0x03000000
1076 #define PORT_FEATURE_LINK_SPEED_MASK 0x000f0000
1077 #define PORT_FEATURE_LINK_SPEED_SHIFT 16
1078 #define PORT_FEATURE_LINK_SPEED_AUTO 0x00000000
1079 #define PORT_FEATURE_LINK_SPEED_10M_FULL 0x00010000
1080 #define PORT_FEATURE_LINK_SPEED_10M_HALF 0x00020000
1081 #define PORT_FEATURE_LINK_SPEED_100M_HALF 0x00030000
1082 #define PORT_FEATURE_LINK_SPEED_100M_FULL 0x00040000
1083 #define PORT_FEATURE_LINK_SPEED_1G 0x00050000
1084 #define PORT_FEATURE_LINK_SPEED_2_5G 0x00060000
1085 #define PORT_FEATURE_LINK_SPEED_10G_CX4 0x00070000
1086 #define PORT_FEATURE_LINK_SPEED_20G 0x00080000
1088 #define PORT_FEATURE_FLOW_CONTROL_MASK 0x00000700
1089 #define PORT_FEATURE_FLOW_CONTROL_SHIFT 8
1090 #define PORT_FEATURE_FLOW_CONTROL_AUTO 0x00000000
1091 #define PORT_FEATURE_FLOW_CONTROL_TX 0x00000100
1092 #define PORT_FEATURE_FLOW_CONTROL_RX 0x00000200
1093 #define PORT_FEATURE_FLOW_CONTROL_BOTH 0x00000300
1094 #define PORT_FEATURE_FLOW_CONTROL_NONE 0x00000400
1096 /* The default for MCP link configuration,
1097 uses the same defines as link_config */
1098 u32 mfw_wol_link_cfg;
1100 /* The default for the driver of the second external phy,
1101 uses the same defines as link_config */
1102 u32 link_config2; /* 0x47C */
1104 /* The default for MCP of the second external phy,
1105 uses the same defines as link_config */
1106 u32 mfw_wol_link_cfg2; /* 0x480 */
1109 /* EEE power saving mode */
1110 u32 eee_power_mode; /* 0x484 */
1111 #define PORT_FEAT_CFG_EEE_POWER_MODE_MASK 0x000000FF
1112 #define PORT_FEAT_CFG_EEE_POWER_MODE_SHIFT 0
1113 #define PORT_FEAT_CFG_EEE_POWER_MODE_DISABLED 0x00000000
1114 #define PORT_FEAT_CFG_EEE_POWER_MODE_BALANCED 0x00000001
1115 #define PORT_FEAT_CFG_EEE_POWER_MODE_AGGRESSIVE 0x00000002
1116 #define PORT_FEAT_CFG_EEE_POWER_MODE_LOW_LATENCY 0x00000003
1119 u32 Reserved2[16]; /* 0x488 */
1123 /****************************************************************************
1124 * Device Information *
1125 ****************************************************************************/
1126 struct shm_dev_info { /* size */
1128 u32 bc_rev; /* 8 bits each: major, minor, build */ /* 4 */
1130 struct shared_hw_cfg shared_hw_config; /* 40 */
1132 struct port_hw_cfg port_hw_config[PORT_MAX]; /* 400*2=800 */
1134 struct shared_feat_cfg shared_feature_config; /* 4 */
1136 struct port_feat_cfg port_feature_config[PORT_MAX];/* 116*2=232 */
1141 #if !defined(__LITTLE_ENDIAN) && !defined(__BIG_ENDIAN)
1142 #error "Missing either LITTLE_ENDIAN or BIG_ENDIAN definition."
1153 #define E1_FUNC_MAX 2
1154 #define E1H_FUNC_MAX 8
1155 #define E2_FUNC_MAX 4 /* per path */
1164 #define E2_VF_MAX 64 /* HC_REG_VF_CONFIGURATION_SIZE */
1165 /* This value (in milliseconds) determines the frequency of the driver
1166 * issuing the PULSE message code. The firmware monitors this periodic
1167 * pulse to determine when to switch to an OS-absent mode. */
1168 #define DRV_PULSE_PERIOD_MS 250
1170 /* This value (in milliseconds) determines how long the driver should
1171 * wait for an acknowledgement from the firmware before timing out. Once
1172 * the firmware has timed out, the driver will assume there is no firmware
1173 * running and there won't be any firmware-driver synchronization during a
1175 #define FW_ACK_TIME_OUT_MS 5000
1177 #define FW_ACK_POLL_TIME_MS 1
1179 #define FW_ACK_NUM_OF_POLL (FW_ACK_TIME_OUT_MS/FW_ACK_POLL_TIME_MS)
1181 #define MFW_TRACE_SIGNATURE 0x54524342
1183 /****************************************************************************
1184 * Driver <-> FW Mailbox *
1185 ****************************************************************************/
1186 struct drv_port_mb {
1189 /* Driver should update this field on any link change event */
1191 #define LINK_STATUS_NONE (0<<0)
1192 #define LINK_STATUS_LINK_FLAG_MASK 0x00000001
1193 #define LINK_STATUS_LINK_UP 0x00000001
1194 #define LINK_STATUS_SPEED_AND_DUPLEX_MASK 0x0000001E
1195 #define LINK_STATUS_SPEED_AND_DUPLEX_AN_NOT_COMPLETE (0<<1)
1196 #define LINK_STATUS_SPEED_AND_DUPLEX_10THD (1<<1)
1197 #define LINK_STATUS_SPEED_AND_DUPLEX_10TFD (2<<1)
1198 #define LINK_STATUS_SPEED_AND_DUPLEX_100TXHD (3<<1)
1199 #define LINK_STATUS_SPEED_AND_DUPLEX_100T4 (4<<1)
1200 #define LINK_STATUS_SPEED_AND_DUPLEX_100TXFD (5<<1)
1201 #define LINK_STATUS_SPEED_AND_DUPLEX_1000THD (6<<1)
1202 #define LINK_STATUS_SPEED_AND_DUPLEX_1000TFD (7<<1)
1203 #define LINK_STATUS_SPEED_AND_DUPLEX_1000XFD (7<<1)
1204 #define LINK_STATUS_SPEED_AND_DUPLEX_2500THD (8<<1)
1205 #define LINK_STATUS_SPEED_AND_DUPLEX_2500TFD (9<<1)
1206 #define LINK_STATUS_SPEED_AND_DUPLEX_2500XFD (9<<1)
1207 #define LINK_STATUS_SPEED_AND_DUPLEX_10GTFD (10<<1)
1208 #define LINK_STATUS_SPEED_AND_DUPLEX_10GXFD (10<<1)
1209 #define LINK_STATUS_SPEED_AND_DUPLEX_20GTFD (11<<1)
1210 #define LINK_STATUS_SPEED_AND_DUPLEX_20GXFD (11<<1)
1212 #define LINK_STATUS_AUTO_NEGOTIATE_FLAG_MASK 0x00000020
1213 #define LINK_STATUS_AUTO_NEGOTIATE_ENABLED 0x00000020
1215 #define LINK_STATUS_AUTO_NEGOTIATE_COMPLETE 0x00000040
1216 #define LINK_STATUS_PARALLEL_DETECTION_FLAG_MASK 0x00000080
1217 #define LINK_STATUS_PARALLEL_DETECTION_USED 0x00000080
1219 #define LINK_STATUS_LINK_PARTNER_1000TFD_CAPABLE 0x00000200
1220 #define LINK_STATUS_LINK_PARTNER_1000THD_CAPABLE 0x00000400
1221 #define LINK_STATUS_LINK_PARTNER_100T4_CAPABLE 0x00000800
1222 #define LINK_STATUS_LINK_PARTNER_100TXFD_CAPABLE 0x00001000
1223 #define LINK_STATUS_LINK_PARTNER_100TXHD_CAPABLE 0x00002000
1224 #define LINK_STATUS_LINK_PARTNER_10TFD_CAPABLE 0x00004000
1225 #define LINK_STATUS_LINK_PARTNER_10THD_CAPABLE 0x00008000
1227 #define LINK_STATUS_TX_FLOW_CONTROL_FLAG_MASK 0x00010000
1228 #define LINK_STATUS_TX_FLOW_CONTROL_ENABLED 0x00010000
1230 #define LINK_STATUS_RX_FLOW_CONTROL_FLAG_MASK 0x00020000
1231 #define LINK_STATUS_RX_FLOW_CONTROL_ENABLED 0x00020000
1233 #define LINK_STATUS_LINK_PARTNER_FLOW_CONTROL_MASK 0x000C0000
1234 #define LINK_STATUS_LINK_PARTNER_NOT_PAUSE_CAPABLE (0<<18)
1235 #define LINK_STATUS_LINK_PARTNER_SYMMETRIC_PAUSE (1<<18)
1236 #define LINK_STATUS_LINK_PARTNER_ASYMMETRIC_PAUSE (2<<18)
1237 #define LINK_STATUS_LINK_PARTNER_BOTH_PAUSE (3<<18)
1239 #define LINK_STATUS_SERDES_LINK 0x00100000
1241 #define LINK_STATUS_LINK_PARTNER_2500XFD_CAPABLE 0x00200000
1242 #define LINK_STATUS_LINK_PARTNER_2500XHD_CAPABLE 0x00400000
1243 #define LINK_STATUS_LINK_PARTNER_10GXFD_CAPABLE 0x00800000
1244 #define LINK_STATUS_LINK_PARTNER_20GXFD_CAPABLE 0x10000000
1246 #define LINK_STATUS_PFC_ENABLED 0x20000000
1248 #define LINK_STATUS_PHYSICAL_LINK_FLAG 0x40000000
1249 #define LINK_STATUS_SFP_TX_FAULT 0x80000000
1255 /* MCP firmware does not use this field */
1256 u32 ext_phy_fw_version;
1261 struct drv_func_mb {
1264 #define DRV_MSG_CODE_MASK 0xffff0000
1265 #define DRV_MSG_CODE_LOAD_REQ 0x10000000
1266 #define DRV_MSG_CODE_LOAD_DONE 0x11000000
1267 #define DRV_MSG_CODE_UNLOAD_REQ_WOL_EN 0x20000000
1268 #define DRV_MSG_CODE_UNLOAD_REQ_WOL_DIS 0x20010000
1269 #define DRV_MSG_CODE_UNLOAD_REQ_WOL_MCP 0x20020000
1270 #define DRV_MSG_CODE_UNLOAD_DONE 0x21000000
1271 #define DRV_MSG_CODE_DCC_OK 0x30000000
1272 #define DRV_MSG_CODE_DCC_FAILURE 0x31000000
1273 #define DRV_MSG_CODE_DIAG_ENTER_REQ 0x50000000
1274 #define DRV_MSG_CODE_DIAG_EXIT_REQ 0x60000000
1275 #define DRV_MSG_CODE_VALIDATE_KEY 0x70000000
1276 #define DRV_MSG_CODE_GET_CURR_KEY 0x80000000
1277 #define DRV_MSG_CODE_GET_UPGRADE_KEY 0x81000000
1278 #define DRV_MSG_CODE_GET_MANUF_KEY 0x82000000
1279 #define DRV_MSG_CODE_LOAD_L2B_PRAM 0x90000000
1280 #define DRV_MSG_CODE_OEM_OK 0x00010000
1281 #define DRV_MSG_CODE_OEM_FAILURE 0x00020000
1282 #define DRV_MSG_CODE_OEM_UPDATE_SVID_OK 0x00030000
1283 #define DRV_MSG_CODE_OEM_UPDATE_SVID_FAILURE 0x00040000
1285 * The optic module verification command requires bootcode
1286 * v5.0.6 or later, te specific optic module verification command
1287 * requires bootcode v5.2.12 or later
1289 #define DRV_MSG_CODE_VRFY_FIRST_PHY_OPT_MDL 0xa0000000
1290 #define REQ_BC_VER_4_VRFY_FIRST_PHY_OPT_MDL 0x00050006
1291 #define DRV_MSG_CODE_VRFY_SPECIFIC_PHY_OPT_MDL 0xa1000000
1292 #define REQ_BC_VER_4_VRFY_SPECIFIC_PHY_OPT_MDL 0x00050234
1293 #define DRV_MSG_CODE_VRFY_AFEX_SUPPORTED 0xa2000000
1294 #define REQ_BC_VER_4_VRFY_AFEX_SUPPORTED 0x00070002
1295 #define REQ_BC_VER_4_SFP_TX_DISABLE_SUPPORTED 0x00070014
1296 #define REQ_BC_VER_4_MT_SUPPORTED 0x00070201
1297 #define REQ_BC_VER_4_PFC_STATS_SUPPORTED 0x00070201
1298 #define REQ_BC_VER_4_FCOE_FEATURES 0x00070209
1300 #define DRV_MSG_CODE_DCBX_ADMIN_PMF_MSG 0xb0000000
1301 #define DRV_MSG_CODE_DCBX_PMF_DRV_OK 0xb2000000
1302 #define REQ_BC_VER_4_DCBX_ADMIN_MSG_NON_PMF 0x00070401
1304 #define DRV_MSG_CODE_VF_DISABLED_DONE 0xc0000000
1306 #define DRV_MSG_CODE_AFEX_DRIVER_SETMAC 0xd0000000
1307 #define DRV_MSG_CODE_AFEX_LISTGET_ACK 0xd1000000
1308 #define DRV_MSG_CODE_AFEX_LISTSET_ACK 0xd2000000
1309 #define DRV_MSG_CODE_AFEX_STATSGET_ACK 0xd3000000
1310 #define DRV_MSG_CODE_AFEX_VIFSET_ACK 0xd4000000
1312 #define DRV_MSG_CODE_DRV_INFO_ACK 0xd8000000
1313 #define DRV_MSG_CODE_DRV_INFO_NACK 0xd9000000
1315 #define DRV_MSG_CODE_EEE_RESULTS_ACK 0xda000000
1317 #define DRV_MSG_CODE_RMMOD 0xdb000000
1318 #define REQ_BC_VER_4_RMMOD_CMD 0x0007080f
1320 #define DRV_MSG_CODE_SET_MF_BW 0xe0000000
1321 #define REQ_BC_VER_4_SET_MF_BW 0x00060202
1322 #define DRV_MSG_CODE_SET_MF_BW_ACK 0xe1000000
1324 #define DRV_MSG_CODE_LINK_STATUS_CHANGED 0x01000000
1326 #define DRV_MSG_CODE_INITIATE_FLR 0x02000000
1327 #define REQ_BC_VER_4_INITIATE_FLR 0x00070213
1329 #define BIOS_MSG_CODE_LIC_CHALLENGE 0xff010000
1330 #define BIOS_MSG_CODE_LIC_RESPONSE 0xff020000
1331 #define BIOS_MSG_CODE_VIRT_MAC_PRIM 0xff030000
1332 #define BIOS_MSG_CODE_VIRT_MAC_ISCSI 0xff040000
1334 #define DRV_MSG_SEQ_NUMBER_MASK 0x0000ffff
1337 #define DRV_MSG_CODE_SET_MF_BW_MIN_MASK 0x00ff0000
1338 #define DRV_MSG_CODE_SET_MF_BW_MAX_MASK 0xff000000
1340 #define DRV_MSG_CODE_UNLOAD_SKIP_LINK_RESET 0x00000002
1342 #define DRV_MSG_CODE_LOAD_REQ_WITH_LFA 0x0000100a
1343 #define DRV_MSG_CODE_LOAD_REQ_FORCE_LFA 0x00002000
1346 #define FW_MSG_CODE_MASK 0xffff0000
1347 #define FW_MSG_CODE_DRV_LOAD_COMMON 0x10100000
1348 #define FW_MSG_CODE_DRV_LOAD_PORT 0x10110000
1349 #define FW_MSG_CODE_DRV_LOAD_FUNCTION 0x10120000
1350 /* Load common chip is supported from bc 6.0.0 */
1351 #define REQ_BC_VER_4_DRV_LOAD_COMMON_CHIP 0x00060000
1352 #define FW_MSG_CODE_DRV_LOAD_COMMON_CHIP 0x10130000
1354 #define FW_MSG_CODE_DRV_LOAD_REFUSED 0x10200000
1355 #define FW_MSG_CODE_DRV_LOAD_DONE 0x11100000
1356 #define FW_MSG_CODE_DRV_UNLOAD_COMMON 0x20100000
1357 #define FW_MSG_CODE_DRV_UNLOAD_PORT 0x20110000
1358 #define FW_MSG_CODE_DRV_UNLOAD_FUNCTION 0x20120000
1359 #define FW_MSG_CODE_DRV_UNLOAD_DONE 0x21100000
1360 #define FW_MSG_CODE_DCC_DONE 0x30100000
1361 #define FW_MSG_CODE_LLDP_DONE 0x40100000
1362 #define FW_MSG_CODE_DIAG_ENTER_DONE 0x50100000
1363 #define FW_MSG_CODE_DIAG_REFUSE 0x50200000
1364 #define FW_MSG_CODE_DIAG_EXIT_DONE 0x60100000
1365 #define FW_MSG_CODE_VALIDATE_KEY_SUCCESS 0x70100000
1366 #define FW_MSG_CODE_VALIDATE_KEY_FAILURE 0x70200000
1367 #define FW_MSG_CODE_GET_KEY_DONE 0x80100000
1368 #define FW_MSG_CODE_NO_KEY 0x80f00000
1369 #define FW_MSG_CODE_LIC_INFO_NOT_READY 0x80f80000
1370 #define FW_MSG_CODE_L2B_PRAM_LOADED 0x90100000
1371 #define FW_MSG_CODE_L2B_PRAM_T_LOAD_FAILURE 0x90210000
1372 #define FW_MSG_CODE_L2B_PRAM_C_LOAD_FAILURE 0x90220000
1373 #define FW_MSG_CODE_L2B_PRAM_X_LOAD_FAILURE 0x90230000
1374 #define FW_MSG_CODE_L2B_PRAM_U_LOAD_FAILURE 0x90240000
1375 #define FW_MSG_CODE_VRFY_OPT_MDL_SUCCESS 0xa0100000
1376 #define FW_MSG_CODE_VRFY_OPT_MDL_INVLD_IMG 0xa0200000
1377 #define FW_MSG_CODE_VRFY_OPT_MDL_UNAPPROVED 0xa0300000
1378 #define FW_MSG_CODE_VF_DISABLED_DONE 0xb0000000
1379 #define FW_MSG_CODE_HW_SET_INVALID_IMAGE 0xb0100000
1381 #define FW_MSG_CODE_AFEX_DRIVER_SETMAC_DONE 0xd0100000
1382 #define FW_MSG_CODE_AFEX_LISTGET_ACK 0xd1100000
1383 #define FW_MSG_CODE_AFEX_LISTSET_ACK 0xd2100000
1384 #define FW_MSG_CODE_AFEX_STATSGET_ACK 0xd3100000
1385 #define FW_MSG_CODE_AFEX_VIFSET_ACK 0xd4100000
1387 #define FW_MSG_CODE_DRV_INFO_ACK 0xd8100000
1388 #define FW_MSG_CODE_DRV_INFO_NACK 0xd9100000
1390 #define FW_MSG_CODE_EEE_RESULS_ACK 0xda100000
1392 #define FW_MSG_CODE_RMMOD_ACK 0xdb100000
1394 #define FW_MSG_CODE_SET_MF_BW_SENT 0xe0000000
1395 #define FW_MSG_CODE_SET_MF_BW_DONE 0xe1000000
1397 #define FW_MSG_CODE_LINK_CHANGED_ACK 0x01100000
1399 #define FW_MSG_CODE_LIC_CHALLENGE 0xff010000
1400 #define FW_MSG_CODE_LIC_RESPONSE 0xff020000
1401 #define FW_MSG_CODE_VIRT_MAC_PRIM 0xff030000
1402 #define FW_MSG_CODE_VIRT_MAC_ISCSI 0xff040000
1404 #define FW_MSG_SEQ_NUMBER_MASK 0x0000ffff
1409 #define DRV_PULSE_SEQ_MASK 0x00007fff
1410 #define DRV_PULSE_SYSTEM_TIME_MASK 0xffff0000
1412 * The system time is in the format of
1413 * (year-2001)*12*32 + month*32 + day.
1415 #define DRV_PULSE_ALWAYS_ALIVE 0x00008000
1417 * Indicate to the firmware not to go into the
1418 * OS-absent when it is not getting driver pulse.
1419 * This is used for debugging as well for PXE(MBA).
1423 #define MCP_PULSE_SEQ_MASK 0x00007fff
1424 #define MCP_PULSE_ALWAYS_ALIVE 0x00008000
1425 /* Indicates to the driver not to assert due to lack
1426 * of MCP response */
1427 #define MCP_EVENT_MASK 0xffff0000
1428 #define MCP_EVENT_OTHER_DRIVER_RESET_REQ 0x00010000
1430 u32 iscsi_boot_signature;
1431 u32 iscsi_boot_block_offset;
1434 #define DRV_STATUS_PMF 0x00000001
1435 #define DRV_STATUS_VF_DISABLED 0x00000002
1436 #define DRV_STATUS_SET_MF_BW 0x00000004
1437 #define DRV_STATUS_LINK_EVENT 0x00000008
1439 #define DRV_STATUS_OEM_EVENT_MASK 0x00000070
1440 #define DRV_STATUS_OEM_DISABLE_ENABLE_PF 0x00000010
1441 #define DRV_STATUS_OEM_BANDWIDTH_ALLOCATION 0x00000020
1443 #define DRV_STATUS_OEM_UPDATE_SVID 0x00000080
1445 #define DRV_STATUS_DCC_EVENT_MASK 0x0000ff00
1446 #define DRV_STATUS_DCC_DISABLE_ENABLE_PF 0x00000100
1447 #define DRV_STATUS_DCC_BANDWIDTH_ALLOCATION 0x00000200
1448 #define DRV_STATUS_DCC_CHANGE_MAC_ADDRESS 0x00000400
1449 #define DRV_STATUS_DCC_RESERVED1 0x00000800
1450 #define DRV_STATUS_DCC_SET_PROTOCOL 0x00001000
1451 #define DRV_STATUS_DCC_SET_PRIORITY 0x00002000
1453 #define DRV_STATUS_DCBX_EVENT_MASK 0x000f0000
1454 #define DRV_STATUS_DCBX_NEGOTIATION_RESULTS 0x00010000
1455 #define DRV_STATUS_AFEX_EVENT_MASK 0x03f00000
1456 #define DRV_STATUS_AFEX_LISTGET_REQ 0x00100000
1457 #define DRV_STATUS_AFEX_LISTSET_REQ 0x00200000
1458 #define DRV_STATUS_AFEX_STATSGET_REQ 0x00400000
1459 #define DRV_STATUS_AFEX_VIFSET_REQ 0x00800000
1461 #define DRV_STATUS_DRV_INFO_REQ 0x04000000
1463 #define DRV_STATUS_EEE_NEGOTIATION_RESULTS 0x08000000
1466 #define VIRT_MAC_SIGN_MASK 0xffff0000
1467 #define VIRT_MAC_SIGNATURE 0x564d0000
1473 /****************************************************************************
1474 * Management firmware state *
1475 ****************************************************************************/
1476 /* Allocate 440 bytes for management firmware */
1477 #define MGMTFW_STATE_WORD_SIZE 110
1479 struct mgmtfw_state {
1480 u32 opaque[MGMTFW_STATE_WORD_SIZE];
1484 /****************************************************************************
1485 * Multi-Function configuration *
1486 ****************************************************************************/
1487 struct shared_mf_cfg {
1490 #define SHARED_MF_CLP_SET_DEFAULT 0x00000000
1492 #define SHARED_MF_CLP_EXIT 0x00000001
1494 #define SHARED_MF_CLP_EXIT_DONE 0x00010000
1498 struct port_mf_cfg {
1500 u32 dynamic_cfg; /* device control channel */
1501 #define PORT_MF_CFG_E1HOV_TAG_MASK 0x0000ffff
1502 #define PORT_MF_CFG_E1HOV_TAG_SHIFT 0
1503 #define PORT_MF_CFG_E1HOV_TAG_DEFAULT PORT_MF_CFG_E1HOV_TAG_MASK
1509 struct func_mf_cfg {
1513 /* function 0 of each port cannot be hidden */
1514 #define FUNC_MF_CFG_FUNC_HIDE 0x00000001
1516 #define FUNC_MF_CFG_PROTOCOL_MASK 0x00000006
1517 #define FUNC_MF_CFG_PROTOCOL_FCOE 0x00000000
1518 #define FUNC_MF_CFG_PROTOCOL_ETHERNET 0x00000002
1519 #define FUNC_MF_CFG_PROTOCOL_ETHERNET_WITH_RDMA 0x00000004
1520 #define FUNC_MF_CFG_PROTOCOL_ISCSI 0x00000006
1521 #define FUNC_MF_CFG_PROTOCOL_DEFAULT \
1522 FUNC_MF_CFG_PROTOCOL_ETHERNET_WITH_RDMA
1524 #define FUNC_MF_CFG_FUNC_DISABLED 0x00000008
1525 #define FUNC_MF_CFG_FUNC_DELETED 0x00000010
1528 /* 0 - low priority, 3 - high priority */
1529 #define FUNC_MF_CFG_TRANSMIT_PRIORITY_MASK 0x00000300
1530 #define FUNC_MF_CFG_TRANSMIT_PRIORITY_SHIFT 8
1531 #define FUNC_MF_CFG_TRANSMIT_PRIORITY_DEFAULT 0x00000000
1534 /* value range - 0..100, increments in 100Mbps */
1535 #define FUNC_MF_CFG_MIN_BW_MASK 0x00ff0000
1536 #define FUNC_MF_CFG_MIN_BW_SHIFT 16
1537 #define FUNC_MF_CFG_MIN_BW_DEFAULT 0x00000000
1538 #define FUNC_MF_CFG_MAX_BW_MASK 0xff000000
1539 #define FUNC_MF_CFG_MAX_BW_SHIFT 24
1540 #define FUNC_MF_CFG_MAX_BW_DEFAULT 0x64000000
1542 u32 mac_upper; /* MAC */
1543 #define FUNC_MF_CFG_UPPERMAC_MASK 0x0000ffff
1544 #define FUNC_MF_CFG_UPPERMAC_SHIFT 0
1545 #define FUNC_MF_CFG_UPPERMAC_DEFAULT FUNC_MF_CFG_UPPERMAC_MASK
1547 #define FUNC_MF_CFG_LOWERMAC_DEFAULT 0xffffffff
1549 u32 e1hov_tag; /* VNI */
1550 #define FUNC_MF_CFG_E1HOV_TAG_MASK 0x0000ffff
1551 #define FUNC_MF_CFG_E1HOV_TAG_SHIFT 0
1552 #define FUNC_MF_CFG_E1HOV_TAG_DEFAULT FUNC_MF_CFG_E1HOV_TAG_MASK
1554 /* afex default VLAN ID - 12 bits */
1555 #define FUNC_MF_CFG_AFEX_VLAN_MASK 0x0fff0000
1556 #define FUNC_MF_CFG_AFEX_VLAN_SHIFT 16
1559 #define FUNC_MF_CFG_AFEX_COS_FILTER_MASK 0x000000ff
1560 #define FUNC_MF_CFG_AFEX_COS_FILTER_SHIFT 0
1561 #define FUNC_MF_CFG_AFEX_MBA_ENABLED_MASK 0x0000ff00
1562 #define FUNC_MF_CFG_AFEX_MBA_ENABLED_SHIFT 8
1563 #define FUNC_MF_CFG_AFEX_MBA_ENABLED_VAL 0x00000100
1564 #define FUNC_MF_CFG_AFEX_VLAN_MODE_MASK 0x000f0000
1565 #define FUNC_MF_CFG_AFEX_VLAN_MODE_SHIFT 16
1570 enum mf_cfg_afex_vlan_mode {
1571 FUNC_MF_CFG_AFEX_VLAN_TRUNK_MODE = 0,
1572 FUNC_MF_CFG_AFEX_VLAN_ACCESS_MODE,
1573 FUNC_MF_CFG_AFEX_VLAN_TRUNK_TAG_NATIVE_MODE
1576 /* This structure is not applicable and should not be accessed on 57711 */
1577 struct func_ext_cfg {
1579 #define MACP_FUNC_CFG_FLAGS_MASK 0x0000007F
1580 #define MACP_FUNC_CFG_FLAGS_SHIFT 0
1581 #define MACP_FUNC_CFG_FLAGS_ENABLED 0x00000001
1582 #define MACP_FUNC_CFG_FLAGS_ETHERNET 0x00000002
1583 #define MACP_FUNC_CFG_FLAGS_ISCSI_OFFLOAD 0x00000004
1584 #define MACP_FUNC_CFG_FLAGS_FCOE_OFFLOAD 0x00000008
1585 #define MACP_FUNC_CFG_PAUSE_ON_HOST_RING 0x00000080
1587 u32 iscsi_mac_addr_upper;
1588 u32 iscsi_mac_addr_lower;
1590 u32 fcoe_mac_addr_upper;
1591 u32 fcoe_mac_addr_lower;
1593 u32 fcoe_wwn_port_name_upper;
1594 u32 fcoe_wwn_port_name_lower;
1596 u32 fcoe_wwn_node_name_upper;
1597 u32 fcoe_wwn_node_name_lower;
1600 #define MF_FUNC_CFG_PRESERVE_L2_MAC (1<<0)
1601 #define MF_FUNC_CFG_PRESERVE_ISCSI_MAC (1<<1)
1602 #define MF_FUNC_CFG_PRESERVE_FCOE_MAC (1<<2)
1603 #define MF_FUNC_CFG_PRESERVE_FCOE_WWN_P (1<<3)
1604 #define MF_FUNC_CFG_PRESERVE_FCOE_WWN_N (1<<4)
1605 #define MF_FUNC_CFG_PRESERVE_TX_BW (1<<5)
1610 struct shared_mf_cfg shared_mf_config; /* 0x4 */
1612 struct port_mf_cfg port_mf_config[NVM_PATH_MAX][PORT_MAX];
1613 /* for all chips, there are 8 mf functions */
1614 struct func_mf_cfg func_mf_config[E1H_FUNC_MAX]; /* 0x18 * 8 = 0xc0 */
1616 * Extended configuration per function - this array does not exist and
1617 * should not be accessed on 57711
1619 struct func_ext_cfg func_ext_config[E1H_FUNC_MAX]; /* 0x28 * 8 = 0x140*/
1622 /****************************************************************************
1623 * Shared Memory Region *
1624 ****************************************************************************/
1625 struct shmem_region { /* SharedMem Offset (size) */
1627 u32 validity_map[PORT_MAX]; /* 0x0 (4*2 = 0x8) */
1628 #define SHR_MEM_FORMAT_REV_MASK 0xff000000
1629 #define SHR_MEM_FORMAT_REV_ID ('A'<<24)
1631 #define SHR_MEM_VALIDITY_PCI_CFG 0x00100000
1632 #define SHR_MEM_VALIDITY_MB 0x00200000
1633 #define SHR_MEM_VALIDITY_DEV_INFO 0x00400000
1634 #define SHR_MEM_VALIDITY_RESERVED 0x00000007
1635 /* One licensing bit should be set */
1636 #define SHR_MEM_VALIDITY_LIC_KEY_IN_EFFECT_MASK 0x00000038
1637 #define SHR_MEM_VALIDITY_LIC_MANUF_KEY_IN_EFFECT 0x00000008
1638 #define SHR_MEM_VALIDITY_LIC_UPGRADE_KEY_IN_EFFECT 0x00000010
1639 #define SHR_MEM_VALIDITY_LIC_NO_KEY_IN_EFFECT 0x00000020
1641 #define SHR_MEM_VALIDITY_ACTIVE_MFW_UNKNOWN 0x00000000
1642 #define SHR_MEM_VALIDITY_ACTIVE_MFW_MASK 0x000001c0
1643 #define SHR_MEM_VALIDITY_ACTIVE_MFW_IPMI 0x00000040
1644 #define SHR_MEM_VALIDITY_ACTIVE_MFW_UMP 0x00000080
1645 #define SHR_MEM_VALIDITY_ACTIVE_MFW_NCSI 0x000000c0
1646 #define SHR_MEM_VALIDITY_ACTIVE_MFW_NONE 0x000001c0
1648 struct shm_dev_info dev_info; /* 0x8 (0x438) */
1650 struct license_key drv_lic_key[PORT_MAX]; /* 0x440 (52*2=0x68) */
1652 /* FW information (for internal FW use) */
1653 u32 fw_info_fio_offset; /* 0x4a8 (0x4) */
1654 struct mgmtfw_state mgmtfw_state; /* 0x4ac (0x1b8) */
1656 struct drv_port_mb port_mb[PORT_MAX]; /* 0x664 (16*2=0x20) */
1659 /* This is a variable length array */
1660 /* the number of function depends on the chip type */
1661 struct drv_func_mb func_mb[1]; /* 0x684 (44*2/4/8=0x58/0xb0/0x160) */
1663 /* the number of function depends on the chip type */
1664 struct drv_func_mb func_mb[]; /* 0x684 (44*2/4/8=0x58/0xb0/0x160) */
1667 }; /* 57710 = 0x6dc | 57711 = 0x7E4 | 57712 = 0x734 */
1669 /****************************************************************************
1670 * Shared Memory 2 Region *
1671 ****************************************************************************/
1672 /* The fw_flr_ack is actually built in the following way: */
1674 /* 64 bit: VF ack */
1675 /* 8 bit: ios_dis_ack */
1676 /* In order to maintain endianity in the mailbox hsi, we want to keep using */
1677 /* u32. The fw must have the VF right after the PF since this is how it */
1678 /* access arrays(it expects always the VF to reside after the PF, and that */
1679 /* makes the calculation much easier for it. ) */
1680 /* In order to answer both limitations, and keep the struct small, the code */
1681 /* will abuse the structure defined here to achieve the actual partition */
1683 /****************************************************************************/
1693 struct fw_flr_ack ack;
1696 struct eee_remote_vals {
1701 /**** SUPPORT FOR SHMEM ARRRAYS ***
1702 * The SHMEM HSI is aligned on 32 bit boundaries which makes it difficult to
1703 * define arrays with storage types smaller then unsigned dwords.
1704 * The macros below add generic support for SHMEM arrays with numeric elements
1705 * that can span 2,4,8 or 16 bits. The array underlying type is a 32 bit dword
1706 * array with individual bit-filed elements accessed using shifts and masks.
1710 /* eb is the bitwidth of a single element */
1711 #define SHMEM_ARRAY_MASK(eb) ((1<<(eb))-1)
1712 #define SHMEM_ARRAY_ENTRY(i, eb) ((i)/(32/(eb)))
1714 /* the bit-position macro allows the used to flip the order of the arrays
1715 * elements on a per byte or word boundary.
1717 * example: an array with 8 entries each 4 bit wide. This array will fit into
1718 * a single dword. The diagrmas below show the array order of the nibbles.
1720 * SHMEM_ARRAY_BITPOS(i, 4, 4) defines the stadard ordering:
1723 * 0 | 1 | 2 | 3 | 4 | 5 | 6 | 7 |
1726 * SHMEM_ARRAY_BITPOS(i, 4, 8) defines a flip ordering per byte:
1729 * 1 | 0 | 3 | 2 | 5 | 4 | 7 | 6 |
1732 * SHMEM_ARRAY_BITPOS(i, 4, 16) defines a flip ordering per word:
1735 * 3 | 2 | 1 | 0 | 7 | 6 | 5 | 4 |
1738 #define SHMEM_ARRAY_BITPOS(i, eb, fb) \
1739 ((((32/(fb)) - 1 - ((i)/((fb)/(eb))) % (32/(fb))) * (fb)) + \
1740 (((i)%((fb)/(eb))) * (eb)))
1742 #define SHMEM_ARRAY_GET(a, i, eb, fb) \
1743 ((a[SHMEM_ARRAY_ENTRY(i, eb)] >> SHMEM_ARRAY_BITPOS(i, eb, fb)) & \
1744 SHMEM_ARRAY_MASK(eb))
1746 #define SHMEM_ARRAY_SET(a, i, eb, fb, val) \
1748 a[SHMEM_ARRAY_ENTRY(i, eb)] &= ~(SHMEM_ARRAY_MASK(eb) << \
1749 SHMEM_ARRAY_BITPOS(i, eb, fb)); \
1750 a[SHMEM_ARRAY_ENTRY(i, eb)] |= (((val) & SHMEM_ARRAY_MASK(eb)) << \
1751 SHMEM_ARRAY_BITPOS(i, eb, fb)); \
1755 /****START OF DCBX STRUCTURES DECLARATIONS****/
1756 #define DCBX_MAX_NUM_PRI_PG_ENTRIES 8
1757 #define DCBX_PRI_PG_BITWIDTH 4
1758 #define DCBX_PRI_PG_FBITS 8
1759 #define DCBX_PRI_PG_GET(a, i) \
1760 SHMEM_ARRAY_GET(a, i, DCBX_PRI_PG_BITWIDTH, DCBX_PRI_PG_FBITS)
1761 #define DCBX_PRI_PG_SET(a, i, val) \
1762 SHMEM_ARRAY_SET(a, i, DCBX_PRI_PG_BITWIDTH, DCBX_PRI_PG_FBITS, val)
1763 #define DCBX_MAX_NUM_PG_BW_ENTRIES 8
1764 #define DCBX_BW_PG_BITWIDTH 8
1765 #define DCBX_PG_BW_GET(a, i) \
1766 SHMEM_ARRAY_GET(a, i, DCBX_BW_PG_BITWIDTH, DCBX_BW_PG_BITWIDTH)
1767 #define DCBX_PG_BW_SET(a, i, val) \
1768 SHMEM_ARRAY_SET(a, i, DCBX_BW_PG_BITWIDTH, DCBX_BW_PG_BITWIDTH, val)
1769 #define DCBX_STRICT_PRI_PG 15
1770 #define DCBX_MAX_APP_PROTOCOL 16
1771 #define FCOE_APP_IDX 0
1772 #define ISCSI_APP_IDX 1
1773 #define PREDEFINED_APP_IDX_MAX 2
1776 /* Big/Little endian have the same representation. */
1777 struct dcbx_ets_feature {
1779 * For Admin MIB - is this feature supported by the
1780 * driver | For Local MIB - should this feature be enabled.
1787 /* Driver structure in LE */
1788 struct dcbx_pfc_feature {
1791 #define DCBX_PFC_PRI_0 0x01
1792 #define DCBX_PFC_PRI_1 0x02
1793 #define DCBX_PFC_PRI_2 0x04
1794 #define DCBX_PFC_PRI_3 0x08
1795 #define DCBX_PFC_PRI_4 0x10
1796 #define DCBX_PFC_PRI_5 0x20
1797 #define DCBX_PFC_PRI_6 0x40
1798 #define DCBX_PFC_PRI_7 0x80
1802 #elif defined(__LITTLE_ENDIAN)
1807 #define DCBX_PFC_PRI_0 0x01
1808 #define DCBX_PFC_PRI_1 0x02
1809 #define DCBX_PFC_PRI_2 0x04
1810 #define DCBX_PFC_PRI_3 0x08
1811 #define DCBX_PFC_PRI_4 0x10
1812 #define DCBX_PFC_PRI_5 0x20
1813 #define DCBX_PFC_PRI_6 0x40
1814 #define DCBX_PFC_PRI_7 0x80
1818 struct dcbx_app_priority_entry {
1823 #define DCBX_APP_ENTRY_VALID 0x01
1824 #define DCBX_APP_ENTRY_SF_MASK 0x30
1825 #define DCBX_APP_ENTRY_SF_SHIFT 4
1826 #define DCBX_APP_SF_ETH_TYPE 0x10
1827 #define DCBX_APP_SF_PORT 0x20
1828 #elif defined(__LITTLE_ENDIAN)
1830 #define DCBX_APP_ENTRY_VALID 0x01
1831 #define DCBX_APP_ENTRY_SF_MASK 0x30
1832 #define DCBX_APP_ENTRY_SF_SHIFT 4
1833 #define DCBX_APP_SF_ETH_TYPE 0x10
1834 #define DCBX_APP_SF_PORT 0x20
1841 /* FW structure in BE */
1842 struct dcbx_app_priority_feature {
1848 #elif defined(__LITTLE_ENDIAN)
1854 struct dcbx_app_priority_entry app_pri_tbl[DCBX_MAX_APP_PROTOCOL];
1857 /* FW structure in BE */
1858 struct dcbx_features {
1860 struct dcbx_ets_feature ets;
1862 struct dcbx_pfc_feature pfc;
1864 struct dcbx_app_priority_feature app;
1867 /* LLDP protocol parameters */
1868 /* FW structure in BE */
1869 struct lldp_params {
1871 u8 msg_fast_tx_interval;
1875 #define LLDP_TX_ONLY 0x01
1876 #define LLDP_RX_ONLY 0x02
1877 #define LLDP_TX_RX 0x03
1878 #define LLDP_DISABLED 0x04
1883 #elif defined(__LITTLE_ENDIAN)
1885 #define LLDP_TX_ONLY 0x01
1886 #define LLDP_RX_ONLY 0x02
1887 #define LLDP_TX_RX 0x03
1888 #define LLDP_DISABLED 0x04
1891 u8 msg_fast_tx_interval;
1897 #define REM_CHASSIS_ID_STAT_LEN 4
1898 #define REM_PORT_ID_STAT_LEN 4
1899 /* Holds remote Chassis ID TLV header, subtype and 9B of payload. */
1900 u32 peer_chassis_id[REM_CHASSIS_ID_STAT_LEN];
1901 /* Holds remote Port ID TLV header, subtype and 9B of payload. */
1902 u32 peer_port_id[REM_PORT_ID_STAT_LEN];
1905 struct lldp_dcbx_stat {
1906 #define LOCAL_CHASSIS_ID_STAT_LEN 2
1907 #define LOCAL_PORT_ID_STAT_LEN 2
1908 /* Holds local Chassis ID 8B payload of constant subtype 4. */
1909 u32 local_chassis_id[LOCAL_CHASSIS_ID_STAT_LEN];
1910 /* Holds local Port ID 8B payload of constant subtype 3. */
1911 u32 local_port_id[LOCAL_PORT_ID_STAT_LEN];
1912 /* Number of DCBX frames transmitted. */
1913 u32 num_tx_dcbx_pkts;
1914 /* Number of DCBX frames received. */
1915 u32 num_rx_dcbx_pkts;
1918 /* ADMIN MIB - DCBX local machine default configuration. */
1919 struct lldp_admin_mib {
1921 #define DCBX_ETS_CONFIG_TX_ENABLED 0x00000001
1922 #define DCBX_PFC_CONFIG_TX_ENABLED 0x00000002
1923 #define DCBX_APP_CONFIG_TX_ENABLED 0x00000004
1924 #define DCBX_ETS_RECO_TX_ENABLED 0x00000008
1925 #define DCBX_ETS_RECO_VALID 0x00000010
1926 #define DCBX_ETS_WILLING 0x00000020
1927 #define DCBX_PFC_WILLING 0x00000040
1928 #define DCBX_APP_WILLING 0x00000080
1929 #define DCBX_VERSION_CEE 0x00000100
1930 #define DCBX_VERSION_IEEE 0x00000200
1931 #define DCBX_DCBX_ENABLED 0x00000400
1932 #define DCBX_CEE_VERSION_MASK 0x0000f000
1933 #define DCBX_CEE_VERSION_SHIFT 12
1934 #define DCBX_CEE_MAX_VERSION_MASK 0x000f0000
1935 #define DCBX_CEE_MAX_VERSION_SHIFT 16
1936 struct dcbx_features features;
1939 /* REMOTE MIB - remote machine DCBX configuration. */
1940 struct lldp_remote_mib {
1943 #define DCBX_ETS_TLV_RX 0x00000001
1944 #define DCBX_PFC_TLV_RX 0x00000002
1945 #define DCBX_APP_TLV_RX 0x00000004
1946 #define DCBX_ETS_RX_ERROR 0x00000010
1947 #define DCBX_PFC_RX_ERROR 0x00000020
1948 #define DCBX_APP_RX_ERROR 0x00000040
1949 #define DCBX_ETS_REM_WILLING 0x00000100
1950 #define DCBX_PFC_REM_WILLING 0x00000200
1951 #define DCBX_APP_REM_WILLING 0x00000400
1952 #define DCBX_REMOTE_ETS_RECO_VALID 0x00001000
1953 #define DCBX_REMOTE_MIB_VALID 0x00002000
1954 struct dcbx_features features;
1958 /* LOCAL MIB - operational DCBX configuration - transmitted on Tx LLDPDU. */
1959 struct lldp_local_mib {
1961 /* Indicates if there is mismatch with negotiation results. */
1963 #define DCBX_LOCAL_ETS_ERROR 0x00000001
1964 #define DCBX_LOCAL_PFC_ERROR 0x00000002
1965 #define DCBX_LOCAL_APP_ERROR 0x00000004
1966 #define DCBX_LOCAL_PFC_MISMATCH 0x00000010
1967 #define DCBX_LOCAL_APP_MISMATCH 0x00000020
1968 #define DCBX_REMOTE_MIB_ERROR 0x00000040
1969 #define DCBX_REMOTE_ETS_TLV_NOT_FOUND 0x00000080
1970 #define DCBX_REMOTE_PFC_TLV_NOT_FOUND 0x00000100
1971 #define DCBX_REMOTE_APP_TLV_NOT_FOUND 0x00000200
1972 struct dcbx_features features;
1975 /***END OF DCBX STRUCTURES DECLARATIONS***/
1977 /***********************************************************/
1979 /***********************************************************/
1980 #define SHMEM_LINK_CONFIG_SIZE 2
1983 #define REQ_DUPLEX_PHY0_MASK 0x0000ffff
1984 #define REQ_DUPLEX_PHY0_SHIFT 0
1985 #define REQ_DUPLEX_PHY1_MASK 0xffff0000
1986 #define REQ_DUPLEX_PHY1_SHIFT 16
1988 #define REQ_FLOW_CTRL_PHY0_MASK 0x0000ffff
1989 #define REQ_FLOW_CTRL_PHY0_SHIFT 0
1990 #define REQ_FLOW_CTRL_PHY1_MASK 0xffff0000
1991 #define REQ_FLOW_CTRL_PHY1_SHIFT 16
1992 u32 req_line_speed; /* Also determine AutoNeg */
1993 #define REQ_LINE_SPD_PHY0_MASK 0x0000ffff
1994 #define REQ_LINE_SPD_PHY0_SHIFT 0
1995 #define REQ_LINE_SPD_PHY1_MASK 0xffff0000
1996 #define REQ_LINE_SPD_PHY1_SHIFT 16
1997 u32 speed_cap_mask[SHMEM_LINK_CONFIG_SIZE];
1998 u32 additional_config;
1999 #define REQ_FC_AUTO_ADV_MASK 0x0000ffff
2000 #define REQ_FC_AUTO_ADV0_SHIFT 0
2001 #define NO_LFA_DUE_TO_DCC_MASK 0x00010000
2003 #define LFA_LINK_FLAP_REASON_OFFSET 0
2004 #define LFA_LINK_FLAP_REASON_MASK 0x000000ff
2005 #define LFA_LINK_DOWN 0x1
2006 #define LFA_LOOPBACK_ENABLED 0x2
2007 #define LFA_DUPLEX_MISMATCH 0x3
2008 #define LFA_MFW_IS_TOO_OLD 0x4
2009 #define LFA_LINK_SPEED_MISMATCH 0x5
2010 #define LFA_FLOW_CTRL_MISMATCH 0x6
2011 #define LFA_SPEED_CAP_MISMATCH 0x7
2012 #define LFA_DCC_LFA_DISABLED 0x8
2013 #define LFA_EEE_MISMATCH 0x9
2015 #define LINK_FLAP_AVOIDANCE_COUNT_OFFSET 8
2016 #define LINK_FLAP_AVOIDANCE_COUNT_MASK 0x0000ff00
2018 #define LINK_FLAP_COUNT_OFFSET 16
2019 #define LINK_FLAP_COUNT_MASK 0x00ff0000
2021 #define LFA_FLAGS_MASK 0xff000000
2022 #define SHMEM_LFA_DONT_CLEAR_STAT (1<<24)
2025 /* Used to support NSCI get OS driver version
2026 * on driver load the version value will be set
2027 * on driver unload driver value of 0x0 will be set.
2030 #define DRV_VER_NOT_LOADED 0
2032 /* personalties order is important */
2033 #define DRV_PERS_ETHERNET 0
2034 #define DRV_PERS_ISCSI 1
2035 #define DRV_PERS_FCOE 2
2037 /* shmem2 struct is constant can't add more personalties here */
2038 #define MAX_DRV_PERS 3
2039 u32 versions[MAX_DRV_PERS];
2042 struct ncsi_oem_fcoe_features {
2044 #define FCOE_FEATURES1_IOS_PER_CONNECTION_MASK 0x0000FFFF
2045 #define FCOE_FEATURES1_IOS_PER_CONNECTION_OFFSET 0
2047 #define FCOE_FEATURES1_LOGINS_PER_PORT_MASK 0xFFFF0000
2048 #define FCOE_FEATURES1_LOGINS_PER_PORT_OFFSET 16
2051 #define FCOE_FEATURES2_EXCHANGES_MASK 0x0000FFFF
2052 #define FCOE_FEATURES2_EXCHANGES_OFFSET 0
2054 #define FCOE_FEATURES2_NPIV_WWN_PER_PORT_MASK 0xFFFF0000
2055 #define FCOE_FEATURES2_NPIV_WWN_PER_PORT_OFFSET 16
2058 #define FCOE_FEATURES3_TARGETS_SUPPORTED_MASK 0x0000FFFF
2059 #define FCOE_FEATURES3_TARGETS_SUPPORTED_OFFSET 0
2061 #define FCOE_FEATURES3_OUTSTANDING_COMMANDS_MASK 0xFFFF0000
2062 #define FCOE_FEATURES3_OUTSTANDING_COMMANDS_OFFSET 16
2065 #define FCOE_FEATURES4_FEATURE_SETTINGS_MASK 0x0000000F
2066 #define FCOE_FEATURES4_FEATURE_SETTINGS_OFFSET 0
2069 struct ncsi_oem_data {
2070 u32 driver_version[4];
2071 struct ncsi_oem_fcoe_features ncsi_oem_fcoe_features;
2074 struct shmem2_region {
2076 u32 size; /* 0x0000 */
2078 u32 dcc_support; /* 0x0004 */
2079 #define SHMEM_DCC_SUPPORT_NONE 0x00000000
2080 #define SHMEM_DCC_SUPPORT_DISABLE_ENABLE_PF_TLV 0x00000001
2081 #define SHMEM_DCC_SUPPORT_BANDWIDTH_ALLOCATION_TLV 0x00000004
2082 #define SHMEM_DCC_SUPPORT_CHANGE_MAC_ADDRESS_TLV 0x00000008
2083 #define SHMEM_DCC_SUPPORT_SET_PROTOCOL_TLV 0x00000040
2084 #define SHMEM_DCC_SUPPORT_SET_PRIORITY_TLV 0x00000080
2086 u32 ext_phy_fw_version2[PORT_MAX]; /* 0x0008 */
2088 * For backwards compatibility, if the mf_cfg_addr does not exist
2089 * (the size filed is smaller than 0xc) the mf_cfg resides at the
2090 * end of struct shmem_region
2092 u32 mf_cfg_addr; /* 0x0010 */
2093 #define SHMEM_MF_CFG_ADDR_NONE 0x00000000
2095 struct fw_flr_mb flr_mb; /* 0x0014 */
2096 u32 dcbx_lldp_params_offset; /* 0x0028 */
2097 #define SHMEM_LLDP_DCBX_PARAMS_NONE 0x00000000
2098 u32 dcbx_neg_res_offset; /* 0x002c */
2099 #define SHMEM_DCBX_NEG_RES_NONE 0x00000000
2100 u32 dcbx_remote_mib_offset; /* 0x0030 */
2101 #define SHMEM_DCBX_REMOTE_MIB_NONE 0x00000000
2103 * The other shmemX_base_addr holds the other path's shmem address
2104 * required for example in case of common phy init, or for path1 to know
2105 * the address of mcp debug trace which is located in offset from shmem
2108 u32 other_shmem_base_addr; /* 0x0034 */
2109 u32 other_shmem2_base_addr; /* 0x0038 */
2111 * mcp_vf_disabled is set by the MCP to indicate the driver about VFs
2112 * which were disabled/flred
2114 u32 mcp_vf_disabled[E2_VF_MAX / 32]; /* 0x003c */
2117 * drv_ack_vf_disabled is set by the PF driver to ack handled disabled
2120 u32 drv_ack_vf_disabled[E2_FUNC_MAX][E2_VF_MAX / 32]; /* 0x0044 */
2122 u32 dcbx_lldp_dcbx_stat_offset; /* 0x0064 */
2123 #define SHMEM_LLDP_DCBX_STAT_NONE 0x00000000
2126 * edebug_driver_if field is used to transfer messages between edebug
2127 * app to the driver through shmem2.
2130 * bits 0-2 - function number / instance of driver to perform request
2131 * bits 3-5 - op code / is_ack?
2134 u32 edebug_driver_if[2]; /* 0x0068 */
2135 #define EDEBUG_DRIVER_IF_OP_CODE_GET_PHYS_ADDR 1
2136 #define EDEBUG_DRIVER_IF_OP_CODE_GET_BUS_ADDR 2
2137 #define EDEBUG_DRIVER_IF_OP_CODE_DISABLE_STAT 3
2139 u32 nvm_retain_bitmap_addr; /* 0x0070 */
2141 /* afex support of that driver */
2142 u32 afex_driver_support; /* 0x0074 */
2143 #define SHMEM_AFEX_VERSION_MASK 0x100f
2144 #define SHMEM_AFEX_SUPPORTED_VERSION_ONE 0x1001
2145 #define SHMEM_AFEX_REDUCED_DRV_LOADED 0x8000
2147 /* driver receives addr in scratchpad to which it should respond */
2148 u32 afex_scratchpad_addr_to_write[E2_FUNC_MAX];
2150 /* generic params from MCP to driver (value depends on the msg sent
2153 u32 afex_param1_to_driver[E2_FUNC_MAX]; /* 0x0088 */
2154 u32 afex_param2_to_driver[E2_FUNC_MAX]; /* 0x0098 */
2156 u32 swim_base_addr; /* 0x0108 */
2160 /* bitmap notifying which VIF profiles stored in nvram are enabled by
2163 u32 afex_profiles_enabled[2];
2165 /* generic flags controlled by the driver */
2167 #define DRV_FLAGS_DCB_CONFIGURED 0x0
2168 #define DRV_FLAGS_DCB_CONFIGURATION_ABORTED 0x1
2169 #define DRV_FLAGS_DCB_MFW_CONFIGURED 0x2
2171 #define DRV_FLAGS_PORT_MASK ((1 << DRV_FLAGS_DCB_CONFIGURED) | \
2172 (1 << DRV_FLAGS_DCB_CONFIGURATION_ABORTED) | \
2173 (1 << DRV_FLAGS_DCB_MFW_CONFIGURED))
2174 /* pointer to extended dev_info shared data copied from nvm image */
2175 u32 extended_dev_info_shared_addr;
2176 u32 ncsi_oem_data_addr;
2178 u32 ocsd_host_addr; /* initialized by option ROM */
2179 u32 ocbb_host_addr; /* initialized by option ROM */
2180 u32 ocsd_req_update_interval; /* initialized by option ROM */
2181 u32 temperature_in_half_celsius;
2182 u32 glob_struct_in_host;
2184 u32 dcbx_neg_res_ext_offset;
2185 #define SHMEM_DCBX_NEG_RES_EXT_NONE 0x00000000
2187 u32 drv_capabilities_flag[E2_FUNC_MAX];
2188 #define DRV_FLAGS_CAPABILITIES_LOADED_SUPPORTED 0x00000001
2189 #define DRV_FLAGS_CAPABILITIES_LOADED_L2 0x00000002
2190 #define DRV_FLAGS_CAPABILITIES_LOADED_FCOE 0x00000004
2191 #define DRV_FLAGS_CAPABILITIES_LOADED_ISCSI 0x00000008
2193 u32 extended_dev_info_shared_cfg_size;
2195 u32 dcbx_en[PORT_MAX];
2197 /* The offset points to the multi threaded meta structure */
2198 u32 multi_thread_data_offset;
2200 /* address of DMAable host address holding values from the drivers */
2201 u32 drv_info_host_addr_lo;
2202 u32 drv_info_host_addr_hi;
2204 /* general values written by the MFW (such as current version) */
2205 u32 drv_info_control;
2206 #define DRV_INFO_CONTROL_VER_MASK 0x000000ff
2207 #define DRV_INFO_CONTROL_VER_SHIFT 0
2208 #define DRV_INFO_CONTROL_OP_CODE_MASK 0x0000ff00
2209 #define DRV_INFO_CONTROL_OP_CODE_SHIFT 8
2210 u32 ibft_host_addr; /* initialized by option ROM */
2211 struct eee_remote_vals eee_remote_vals[PORT_MAX];
2212 u32 reserved[E2_FUNC_MAX];
2215 /* the status of EEE auto-negotiation
2216 * bits 15:0 the configured tx-lpi entry timer value. Depends on bit 31.
2217 * bits 19:16 the supported modes for EEE.
2218 * bits 23:20 the speeds advertised for EEE.
2219 * bits 27:24 the speeds the Link partner advertised for EEE.
2220 * The supported/adv. modes in bits 27:19 originate from the
2221 * SHMEM_EEE_XXX_ADV definitions (where XXX is replaced by speed).
2222 * bit 28 when 1'b1 EEE was requested.
2223 * bit 29 when 1'b1 tx lpi was requested.
2224 * bit 30 when 1'b1 EEE was negotiated. Tx lpi will be asserted iff
2226 * bit 31 when 1'b0 bits 15:0 contain a PORT_FEAT_CFG_EEE_ define as
2227 * value. When 1'b1 those bits contains a value times 16 microseconds.
2229 u32 eee_status[PORT_MAX];
2230 #define SHMEM_EEE_TIMER_MASK 0x0000ffff
2231 #define SHMEM_EEE_SUPPORTED_MASK 0x000f0000
2232 #define SHMEM_EEE_SUPPORTED_SHIFT 16
2233 #define SHMEM_EEE_ADV_STATUS_MASK 0x00f00000
2234 #define SHMEM_EEE_100M_ADV (1<<0)
2235 #define SHMEM_EEE_1G_ADV (1<<1)
2236 #define SHMEM_EEE_10G_ADV (1<<2)
2237 #define SHMEM_EEE_ADV_STATUS_SHIFT 20
2238 #define SHMEM_EEE_LP_ADV_STATUS_MASK 0x0f000000
2239 #define SHMEM_EEE_LP_ADV_STATUS_SHIFT 24
2240 #define SHMEM_EEE_REQUESTED_BIT 0x10000000
2241 #define SHMEM_EEE_LPI_REQUESTED_BIT 0x20000000
2242 #define SHMEM_EEE_ACTIVE_BIT 0x40000000
2243 #define SHMEM_EEE_TIME_OUTPUT_BIT 0x80000000
2245 u32 sizeof_port_stats;
2247 /* Link Flap Avoidance */
2248 u32 lfa_host_addr[PORT_MAX];
2251 u32 reserved2; /* Offset 0x148 */
2252 u32 reserved3; /* Offset 0x14C */
2253 u32 reserved4; /* Offset 0x150 */
2254 u32 link_attr_sync[PORT_MAX]; /* Offset 0x154 */
2255 #define LINK_ATTR_SYNC_KR2_ENABLE 0x00000001
2256 #define LINK_SFP_EEPROM_COMP_CODE_MASK 0x0000ff00
2257 #define LINK_SFP_EEPROM_COMP_CODE_SHIFT 8
2258 #define LINK_SFP_EEPROM_COMP_CODE_SR 0x00001000
2259 #define LINK_SFP_EEPROM_COMP_CODE_LR 0x00002000
2260 #define LINK_SFP_EEPROM_COMP_CODE_LRM 0x00004000
2263 u32 link_change_count[PORT_MAX]; /* Offset 0x160-0x164 */
2264 #define LINK_CHANGE_COUNT_MASK 0xff /* Offset 0x168 */
2265 /* driver version for each personality */
2266 struct os_drv_ver func_os_drv_ver[E2_FUNC_MAX]; /* Offset 0x16c */
2268 /* Flag to the driver that PF's drv_info_host_addr buffer was read */
2269 u32 mfw_drv_indication;
2271 /* We use indication for each PF (0..3) */
2272 #define MFW_DRV_IND_READ_DONE_OFFSET(_pf_) (1 << (_pf_))
2277 u32 rx_stat_ifhcinoctets;
2278 u32 rx_stat_ifhcinbadoctets;
2279 u32 rx_stat_etherstatsfragments;
2280 u32 rx_stat_ifhcinucastpkts;
2281 u32 rx_stat_ifhcinmulticastpkts;
2282 u32 rx_stat_ifhcinbroadcastpkts;
2283 u32 rx_stat_dot3statsfcserrors;
2284 u32 rx_stat_dot3statsalignmenterrors;
2285 u32 rx_stat_dot3statscarriersenseerrors;
2286 u32 rx_stat_xonpauseframesreceived;
2287 u32 rx_stat_xoffpauseframesreceived;
2288 u32 rx_stat_maccontrolframesreceived;
2289 u32 rx_stat_xoffstateentered;
2290 u32 rx_stat_dot3statsframestoolong;
2291 u32 rx_stat_etherstatsjabbers;
2292 u32 rx_stat_etherstatsundersizepkts;
2293 u32 rx_stat_etherstatspkts64octets;
2294 u32 rx_stat_etherstatspkts65octetsto127octets;
2295 u32 rx_stat_etherstatspkts128octetsto255octets;
2296 u32 rx_stat_etherstatspkts256octetsto511octets;
2297 u32 rx_stat_etherstatspkts512octetsto1023octets;
2298 u32 rx_stat_etherstatspkts1024octetsto1522octets;
2299 u32 rx_stat_etherstatspktsover1522octets;
2301 u32 rx_stat_falsecarriererrors;
2303 u32 tx_stat_ifhcoutoctets;
2304 u32 tx_stat_ifhcoutbadoctets;
2305 u32 tx_stat_etherstatscollisions;
2306 u32 tx_stat_outxonsent;
2307 u32 tx_stat_outxoffsent;
2308 u32 tx_stat_flowcontroldone;
2309 u32 tx_stat_dot3statssinglecollisionframes;
2310 u32 tx_stat_dot3statsmultiplecollisionframes;
2311 u32 tx_stat_dot3statsdeferredtransmissions;
2312 u32 tx_stat_dot3statsexcessivecollisions;
2313 u32 tx_stat_dot3statslatecollisions;
2314 u32 tx_stat_ifhcoutucastpkts;
2315 u32 tx_stat_ifhcoutmulticastpkts;
2316 u32 tx_stat_ifhcoutbroadcastpkts;
2317 u32 tx_stat_etherstatspkts64octets;
2318 u32 tx_stat_etherstatspkts65octetsto127octets;
2319 u32 tx_stat_etherstatspkts128octetsto255octets;
2320 u32 tx_stat_etherstatspkts256octetsto511octets;
2321 u32 tx_stat_etherstatspkts512octetsto1023octets;
2322 u32 tx_stat_etherstatspkts1024octetsto1522octets;
2323 u32 tx_stat_etherstatspktsover1522octets;
2324 u32 tx_stat_dot3statsinternalmactransmiterrors;
2328 struct bmac1_stats {
2329 u32 tx_stat_gtpkt_lo;
2330 u32 tx_stat_gtpkt_hi;
2331 u32 tx_stat_gtxpf_lo;
2332 u32 tx_stat_gtxpf_hi;
2333 u32 tx_stat_gtfcs_lo;
2334 u32 tx_stat_gtfcs_hi;
2335 u32 tx_stat_gtmca_lo;
2336 u32 tx_stat_gtmca_hi;
2337 u32 tx_stat_gtbca_lo;
2338 u32 tx_stat_gtbca_hi;
2339 u32 tx_stat_gtfrg_lo;
2340 u32 tx_stat_gtfrg_hi;
2341 u32 tx_stat_gtovr_lo;
2342 u32 tx_stat_gtovr_hi;
2343 u32 tx_stat_gt64_lo;
2344 u32 tx_stat_gt64_hi;
2345 u32 tx_stat_gt127_lo;
2346 u32 tx_stat_gt127_hi;
2347 u32 tx_stat_gt255_lo;
2348 u32 tx_stat_gt255_hi;
2349 u32 tx_stat_gt511_lo;
2350 u32 tx_stat_gt511_hi;
2351 u32 tx_stat_gt1023_lo;
2352 u32 tx_stat_gt1023_hi;
2353 u32 tx_stat_gt1518_lo;
2354 u32 tx_stat_gt1518_hi;
2355 u32 tx_stat_gt2047_lo;
2356 u32 tx_stat_gt2047_hi;
2357 u32 tx_stat_gt4095_lo;
2358 u32 tx_stat_gt4095_hi;
2359 u32 tx_stat_gt9216_lo;
2360 u32 tx_stat_gt9216_hi;
2361 u32 tx_stat_gt16383_lo;
2362 u32 tx_stat_gt16383_hi;
2363 u32 tx_stat_gtmax_lo;
2364 u32 tx_stat_gtmax_hi;
2365 u32 tx_stat_gtufl_lo;
2366 u32 tx_stat_gtufl_hi;
2367 u32 tx_stat_gterr_lo;
2368 u32 tx_stat_gterr_hi;
2369 u32 tx_stat_gtbyt_lo;
2370 u32 tx_stat_gtbyt_hi;
2372 u32 rx_stat_gr64_lo;
2373 u32 rx_stat_gr64_hi;
2374 u32 rx_stat_gr127_lo;
2375 u32 rx_stat_gr127_hi;
2376 u32 rx_stat_gr255_lo;
2377 u32 rx_stat_gr255_hi;
2378 u32 rx_stat_gr511_lo;
2379 u32 rx_stat_gr511_hi;
2380 u32 rx_stat_gr1023_lo;
2381 u32 rx_stat_gr1023_hi;
2382 u32 rx_stat_gr1518_lo;
2383 u32 rx_stat_gr1518_hi;
2384 u32 rx_stat_gr2047_lo;
2385 u32 rx_stat_gr2047_hi;
2386 u32 rx_stat_gr4095_lo;
2387 u32 rx_stat_gr4095_hi;
2388 u32 rx_stat_gr9216_lo;
2389 u32 rx_stat_gr9216_hi;
2390 u32 rx_stat_gr16383_lo;
2391 u32 rx_stat_gr16383_hi;
2392 u32 rx_stat_grmax_lo;
2393 u32 rx_stat_grmax_hi;
2394 u32 rx_stat_grpkt_lo;
2395 u32 rx_stat_grpkt_hi;
2396 u32 rx_stat_grfcs_lo;
2397 u32 rx_stat_grfcs_hi;
2398 u32 rx_stat_grmca_lo;
2399 u32 rx_stat_grmca_hi;
2400 u32 rx_stat_grbca_lo;
2401 u32 rx_stat_grbca_hi;
2402 u32 rx_stat_grxcf_lo;
2403 u32 rx_stat_grxcf_hi;
2404 u32 rx_stat_grxpf_lo;
2405 u32 rx_stat_grxpf_hi;
2406 u32 rx_stat_grxuo_lo;
2407 u32 rx_stat_grxuo_hi;
2408 u32 rx_stat_grjbr_lo;
2409 u32 rx_stat_grjbr_hi;
2410 u32 rx_stat_grovr_lo;
2411 u32 rx_stat_grovr_hi;
2412 u32 rx_stat_grflr_lo;
2413 u32 rx_stat_grflr_hi;
2414 u32 rx_stat_grmeg_lo;
2415 u32 rx_stat_grmeg_hi;
2416 u32 rx_stat_grmeb_lo;
2417 u32 rx_stat_grmeb_hi;
2418 u32 rx_stat_grbyt_lo;
2419 u32 rx_stat_grbyt_hi;
2420 u32 rx_stat_grund_lo;
2421 u32 rx_stat_grund_hi;
2422 u32 rx_stat_grfrg_lo;
2423 u32 rx_stat_grfrg_hi;
2424 u32 rx_stat_grerb_lo;
2425 u32 rx_stat_grerb_hi;
2426 u32 rx_stat_grfre_lo;
2427 u32 rx_stat_grfre_hi;
2428 u32 rx_stat_gripj_lo;
2429 u32 rx_stat_gripj_hi;
2432 struct bmac2_stats {
2433 u32 tx_stat_gtpk_lo; /* gtpok */
2434 u32 tx_stat_gtpk_hi; /* gtpok */
2435 u32 tx_stat_gtxpf_lo; /* gtpf */
2436 u32 tx_stat_gtxpf_hi; /* gtpf */
2437 u32 tx_stat_gtpp_lo; /* NEW BMAC2 */
2438 u32 tx_stat_gtpp_hi; /* NEW BMAC2 */
2439 u32 tx_stat_gtfcs_lo;
2440 u32 tx_stat_gtfcs_hi;
2441 u32 tx_stat_gtuca_lo; /* NEW BMAC2 */
2442 u32 tx_stat_gtuca_hi; /* NEW BMAC2 */
2443 u32 tx_stat_gtmca_lo;
2444 u32 tx_stat_gtmca_hi;
2445 u32 tx_stat_gtbca_lo;
2446 u32 tx_stat_gtbca_hi;
2447 u32 tx_stat_gtovr_lo;
2448 u32 tx_stat_gtovr_hi;
2449 u32 tx_stat_gtfrg_lo;
2450 u32 tx_stat_gtfrg_hi;
2451 u32 tx_stat_gtpkt1_lo; /* gtpkt */
2452 u32 tx_stat_gtpkt1_hi; /* gtpkt */
2453 u32 tx_stat_gt64_lo;
2454 u32 tx_stat_gt64_hi;
2455 u32 tx_stat_gt127_lo;
2456 u32 tx_stat_gt127_hi;
2457 u32 tx_stat_gt255_lo;
2458 u32 tx_stat_gt255_hi;
2459 u32 tx_stat_gt511_lo;
2460 u32 tx_stat_gt511_hi;
2461 u32 tx_stat_gt1023_lo;
2462 u32 tx_stat_gt1023_hi;
2463 u32 tx_stat_gt1518_lo;
2464 u32 tx_stat_gt1518_hi;
2465 u32 tx_stat_gt2047_lo;
2466 u32 tx_stat_gt2047_hi;
2467 u32 tx_stat_gt4095_lo;
2468 u32 tx_stat_gt4095_hi;
2469 u32 tx_stat_gt9216_lo;
2470 u32 tx_stat_gt9216_hi;
2471 u32 tx_stat_gt16383_lo;
2472 u32 tx_stat_gt16383_hi;
2473 u32 tx_stat_gtmax_lo;
2474 u32 tx_stat_gtmax_hi;
2475 u32 tx_stat_gtufl_lo;
2476 u32 tx_stat_gtufl_hi;
2477 u32 tx_stat_gterr_lo;
2478 u32 tx_stat_gterr_hi;
2479 u32 tx_stat_gtbyt_lo;
2480 u32 tx_stat_gtbyt_hi;
2482 u32 rx_stat_gr64_lo;
2483 u32 rx_stat_gr64_hi;
2484 u32 rx_stat_gr127_lo;
2485 u32 rx_stat_gr127_hi;
2486 u32 rx_stat_gr255_lo;
2487 u32 rx_stat_gr255_hi;
2488 u32 rx_stat_gr511_lo;
2489 u32 rx_stat_gr511_hi;
2490 u32 rx_stat_gr1023_lo;
2491 u32 rx_stat_gr1023_hi;
2492 u32 rx_stat_gr1518_lo;
2493 u32 rx_stat_gr1518_hi;
2494 u32 rx_stat_gr2047_lo;
2495 u32 rx_stat_gr2047_hi;
2496 u32 rx_stat_gr4095_lo;
2497 u32 rx_stat_gr4095_hi;
2498 u32 rx_stat_gr9216_lo;
2499 u32 rx_stat_gr9216_hi;
2500 u32 rx_stat_gr16383_lo;
2501 u32 rx_stat_gr16383_hi;
2502 u32 rx_stat_grmax_lo;
2503 u32 rx_stat_grmax_hi;
2504 u32 rx_stat_grpkt_lo;
2505 u32 rx_stat_grpkt_hi;
2506 u32 rx_stat_grfcs_lo;
2507 u32 rx_stat_grfcs_hi;
2508 u32 rx_stat_gruca_lo;
2509 u32 rx_stat_gruca_hi;
2510 u32 rx_stat_grmca_lo;
2511 u32 rx_stat_grmca_hi;
2512 u32 rx_stat_grbca_lo;
2513 u32 rx_stat_grbca_hi;
2514 u32 rx_stat_grxpf_lo; /* grpf */
2515 u32 rx_stat_grxpf_hi; /* grpf */
2516 u32 rx_stat_grpp_lo;
2517 u32 rx_stat_grpp_hi;
2518 u32 rx_stat_grxuo_lo; /* gruo */
2519 u32 rx_stat_grxuo_hi; /* gruo */
2520 u32 rx_stat_grjbr_lo;
2521 u32 rx_stat_grjbr_hi;
2522 u32 rx_stat_grovr_lo;
2523 u32 rx_stat_grovr_hi;
2524 u32 rx_stat_grxcf_lo; /* grcf */
2525 u32 rx_stat_grxcf_hi; /* grcf */
2526 u32 rx_stat_grflr_lo;
2527 u32 rx_stat_grflr_hi;
2528 u32 rx_stat_grpok_lo;
2529 u32 rx_stat_grpok_hi;
2530 u32 rx_stat_grmeg_lo;
2531 u32 rx_stat_grmeg_hi;
2532 u32 rx_stat_grmeb_lo;
2533 u32 rx_stat_grmeb_hi;
2534 u32 rx_stat_grbyt_lo;
2535 u32 rx_stat_grbyt_hi;
2536 u32 rx_stat_grund_lo;
2537 u32 rx_stat_grund_hi;
2538 u32 rx_stat_grfrg_lo;
2539 u32 rx_stat_grfrg_hi;
2540 u32 rx_stat_grerb_lo; /* grerrbyt */
2541 u32 rx_stat_grerb_hi; /* grerrbyt */
2542 u32 rx_stat_grfre_lo; /* grfrerr */
2543 u32 rx_stat_grfre_hi; /* grfrerr */
2544 u32 rx_stat_gripj_lo;
2545 u32 rx_stat_gripj_hi;
2548 struct mstat_stats {
2550 /* OTE MSTAT on E3 has a bug where this register's contents are
2551 * actually tx_gtxpok + tx_gtxpf + (possibly)tx_gtxpp
2595 u32 tx_collisions_lo;
2596 u32 tx_collisions_hi;
2597 u32 tx_singlecollision_lo;
2598 u32 tx_singlecollision_hi;
2599 u32 tx_multiplecollisions_lo;
2600 u32 tx_multiplecollisions_hi;
2603 u32 tx_excessivecollisions_lo;
2604 u32 tx_excessivecollisions_hi;
2605 u32 tx_latecollisions_lo;
2606 u32 tx_latecollisions_hi;
2665 u32 rx_alignmenterrors_lo;
2666 u32 rx_alignmenterrors_hi;
2667 u32 rx_falsecarrier_lo;
2668 u32 rx_falsecarrier_hi;
2669 u32 rx_llfcmsgcnt_lo;
2670 u32 rx_llfcmsgcnt_hi;
2675 struct emac_stats emac_stats;
2676 struct bmac1_stats bmac1_stats;
2677 struct bmac2_stats bmac2_stats;
2678 struct mstat_stats mstat_stats;
2684 u32 rx_stat_ifhcinbadoctets_hi;
2685 u32 rx_stat_ifhcinbadoctets_lo;
2687 /* out_bad_octets */
2688 u32 tx_stat_ifhcoutbadoctets_hi;
2689 u32 tx_stat_ifhcoutbadoctets_lo;
2691 /* crc_receive_errors */
2692 u32 rx_stat_dot3statsfcserrors_hi;
2693 u32 rx_stat_dot3statsfcserrors_lo;
2694 /* alignment_errors */
2695 u32 rx_stat_dot3statsalignmenterrors_hi;
2696 u32 rx_stat_dot3statsalignmenterrors_lo;
2697 /* carrier_sense_errors */
2698 u32 rx_stat_dot3statscarriersenseerrors_hi;
2699 u32 rx_stat_dot3statscarriersenseerrors_lo;
2700 /* false_carrier_detections */
2701 u32 rx_stat_falsecarriererrors_hi;
2702 u32 rx_stat_falsecarriererrors_lo;
2704 /* runt_packets_received */
2705 u32 rx_stat_etherstatsundersizepkts_hi;
2706 u32 rx_stat_etherstatsundersizepkts_lo;
2707 /* jabber_packets_received */
2708 u32 rx_stat_dot3statsframestoolong_hi;
2709 u32 rx_stat_dot3statsframestoolong_lo;
2711 /* error_runt_packets_received */
2712 u32 rx_stat_etherstatsfragments_hi;
2713 u32 rx_stat_etherstatsfragments_lo;
2714 /* error_jabber_packets_received */
2715 u32 rx_stat_etherstatsjabbers_hi;
2716 u32 rx_stat_etherstatsjabbers_lo;
2718 /* control_frames_received */
2719 u32 rx_stat_maccontrolframesreceived_hi;
2720 u32 rx_stat_maccontrolframesreceived_lo;
2721 u32 rx_stat_mac_xpf_hi;
2722 u32 rx_stat_mac_xpf_lo;
2723 u32 rx_stat_mac_xcf_hi;
2724 u32 rx_stat_mac_xcf_lo;
2726 /* xoff_state_entered */
2727 u32 rx_stat_xoffstateentered_hi;
2728 u32 rx_stat_xoffstateentered_lo;
2729 /* pause_xon_frames_received */
2730 u32 rx_stat_xonpauseframesreceived_hi;
2731 u32 rx_stat_xonpauseframesreceived_lo;
2732 /* pause_xoff_frames_received */
2733 u32 rx_stat_xoffpauseframesreceived_hi;
2734 u32 rx_stat_xoffpauseframesreceived_lo;
2735 /* pause_xon_frames_transmitted */
2736 u32 tx_stat_outxonsent_hi;
2737 u32 tx_stat_outxonsent_lo;
2738 /* pause_xoff_frames_transmitted */
2739 u32 tx_stat_outxoffsent_hi;
2740 u32 tx_stat_outxoffsent_lo;
2741 /* flow_control_done */
2742 u32 tx_stat_flowcontroldone_hi;
2743 u32 tx_stat_flowcontroldone_lo;
2745 /* ether_stats_collisions */
2746 u32 tx_stat_etherstatscollisions_hi;
2747 u32 tx_stat_etherstatscollisions_lo;
2748 /* single_collision_transmit_frames */
2749 u32 tx_stat_dot3statssinglecollisionframes_hi;
2750 u32 tx_stat_dot3statssinglecollisionframes_lo;
2751 /* multiple_collision_transmit_frames */
2752 u32 tx_stat_dot3statsmultiplecollisionframes_hi;
2753 u32 tx_stat_dot3statsmultiplecollisionframes_lo;
2754 /* deferred_transmissions */
2755 u32 tx_stat_dot3statsdeferredtransmissions_hi;
2756 u32 tx_stat_dot3statsdeferredtransmissions_lo;
2757 /* excessive_collision_frames */
2758 u32 tx_stat_dot3statsexcessivecollisions_hi;
2759 u32 tx_stat_dot3statsexcessivecollisions_lo;
2760 /* late_collision_frames */
2761 u32 tx_stat_dot3statslatecollisions_hi;
2762 u32 tx_stat_dot3statslatecollisions_lo;
2764 /* frames_transmitted_64_bytes */
2765 u32 tx_stat_etherstatspkts64octets_hi;
2766 u32 tx_stat_etherstatspkts64octets_lo;
2767 /* frames_transmitted_65_127_bytes */
2768 u32 tx_stat_etherstatspkts65octetsto127octets_hi;
2769 u32 tx_stat_etherstatspkts65octetsto127octets_lo;
2770 /* frames_transmitted_128_255_bytes */
2771 u32 tx_stat_etherstatspkts128octetsto255octets_hi;
2772 u32 tx_stat_etherstatspkts128octetsto255octets_lo;
2773 /* frames_transmitted_256_511_bytes */
2774 u32 tx_stat_etherstatspkts256octetsto511octets_hi;
2775 u32 tx_stat_etherstatspkts256octetsto511octets_lo;
2776 /* frames_transmitted_512_1023_bytes */
2777 u32 tx_stat_etherstatspkts512octetsto1023octets_hi;
2778 u32 tx_stat_etherstatspkts512octetsto1023octets_lo;
2779 /* frames_transmitted_1024_1522_bytes */
2780 u32 tx_stat_etherstatspkts1024octetsto1522octets_hi;
2781 u32 tx_stat_etherstatspkts1024octetsto1522octets_lo;
2782 /* frames_transmitted_1523_9022_bytes */
2783 u32 tx_stat_etherstatspktsover1522octets_hi;
2784 u32 tx_stat_etherstatspktsover1522octets_lo;
2785 u32 tx_stat_mac_2047_hi;
2786 u32 tx_stat_mac_2047_lo;
2787 u32 tx_stat_mac_4095_hi;
2788 u32 tx_stat_mac_4095_lo;
2789 u32 tx_stat_mac_9216_hi;
2790 u32 tx_stat_mac_9216_lo;
2791 u32 tx_stat_mac_16383_hi;
2792 u32 tx_stat_mac_16383_lo;
2794 /* internal_mac_transmit_errors */
2795 u32 tx_stat_dot3statsinternalmactransmiterrors_hi;
2796 u32 tx_stat_dot3statsinternalmactransmiterrors_lo;
2798 /* if_out_discards */
2799 u32 tx_stat_mac_ufl_hi;
2800 u32 tx_stat_mac_ufl_lo;
2804 #define MAC_STX_IDX_MAX 2
2806 struct host_port_stats {
2807 u32 host_port_stats_counter;
2809 struct mac_stx mac_stx[MAC_STX_IDX_MAX];
2814 u32 not_used; /* obsolete */
2815 u32 pfc_frames_tx_hi;
2816 u32 pfc_frames_tx_lo;
2817 u32 pfc_frames_rx_hi;
2818 u32 pfc_frames_rx_lo;
2820 u32 eee_lpi_count_hi;
2821 u32 eee_lpi_count_lo;
2825 struct host_func_stats {
2826 u32 host_func_stats_start;
2828 u32 total_bytes_received_hi;
2829 u32 total_bytes_received_lo;
2831 u32 total_bytes_transmitted_hi;
2832 u32 total_bytes_transmitted_lo;
2834 u32 total_unicast_packets_received_hi;
2835 u32 total_unicast_packets_received_lo;
2837 u32 total_multicast_packets_received_hi;
2838 u32 total_multicast_packets_received_lo;
2840 u32 total_broadcast_packets_received_hi;
2841 u32 total_broadcast_packets_received_lo;
2843 u32 total_unicast_packets_transmitted_hi;
2844 u32 total_unicast_packets_transmitted_lo;
2846 u32 total_multicast_packets_transmitted_hi;
2847 u32 total_multicast_packets_transmitted_lo;
2849 u32 total_broadcast_packets_transmitted_hi;
2850 u32 total_broadcast_packets_transmitted_lo;
2852 u32 valid_bytes_received_hi;
2853 u32 valid_bytes_received_lo;
2855 u32 host_func_stats_end;
2858 /* VIC definitions */
2859 #define VICSTATST_UIF_INDEX 2
2862 /* stats collected for afex.
2863 * NOTE: structure is exactly as expected to be received by the switch.
2864 * order must remain exactly as is unless protocol changes !
2867 u32 tx_unicast_frames_hi;
2868 u32 tx_unicast_frames_lo;
2869 u32 tx_unicast_bytes_hi;
2870 u32 tx_unicast_bytes_lo;
2871 u32 tx_multicast_frames_hi;
2872 u32 tx_multicast_frames_lo;
2873 u32 tx_multicast_bytes_hi;
2874 u32 tx_multicast_bytes_lo;
2875 u32 tx_broadcast_frames_hi;
2876 u32 tx_broadcast_frames_lo;
2877 u32 tx_broadcast_bytes_hi;
2878 u32 tx_broadcast_bytes_lo;
2879 u32 tx_frames_discarded_hi;
2880 u32 tx_frames_discarded_lo;
2881 u32 tx_frames_dropped_hi;
2882 u32 tx_frames_dropped_lo;
2884 u32 rx_unicast_frames_hi;
2885 u32 rx_unicast_frames_lo;
2886 u32 rx_unicast_bytes_hi;
2887 u32 rx_unicast_bytes_lo;
2888 u32 rx_multicast_frames_hi;
2889 u32 rx_multicast_frames_lo;
2890 u32 rx_multicast_bytes_hi;
2891 u32 rx_multicast_bytes_lo;
2892 u32 rx_broadcast_frames_hi;
2893 u32 rx_broadcast_frames_lo;
2894 u32 rx_broadcast_bytes_hi;
2895 u32 rx_broadcast_bytes_lo;
2896 u32 rx_frames_discarded_hi;
2897 u32 rx_frames_discarded_lo;
2898 u32 rx_frames_dropped_hi;
2899 u32 rx_frames_dropped_lo;
2902 #define BCM_5710_FW_MAJOR_VERSION 7
2903 #define BCM_5710_FW_MINOR_VERSION 12
2904 #define BCM_5710_FW_REVISION_VERSION 30
2905 #define BCM_5710_FW_ENGINEERING_VERSION 0
2906 #define BCM_5710_FW_COMPILE_FLAGS 1
2912 struct atten_sp_status_block {
2914 __le32 attn_bits_ack;
2917 __le16 attn_bits_index;
2923 * The eth aggregative context of Cstorm
2925 struct cstorm_eth_ag_context {
2926 u32 __reserved0[10];
2931 * dmae command structure
2933 struct dmae_command {
2935 #define DMAE_COMMAND_SRC (0x1<<0)
2936 #define DMAE_COMMAND_SRC_SHIFT 0
2937 #define DMAE_COMMAND_DST (0x3<<1)
2938 #define DMAE_COMMAND_DST_SHIFT 1
2939 #define DMAE_COMMAND_C_DST (0x1<<3)
2940 #define DMAE_COMMAND_C_DST_SHIFT 3
2941 #define DMAE_COMMAND_C_TYPE_ENABLE (0x1<<4)
2942 #define DMAE_COMMAND_C_TYPE_ENABLE_SHIFT 4
2943 #define DMAE_COMMAND_C_TYPE_CRC_ENABLE (0x1<<5)
2944 #define DMAE_COMMAND_C_TYPE_CRC_ENABLE_SHIFT 5
2945 #define DMAE_COMMAND_C_TYPE_CRC_OFFSET (0x7<<6)
2946 #define DMAE_COMMAND_C_TYPE_CRC_OFFSET_SHIFT 6
2947 #define DMAE_COMMAND_ENDIANITY (0x3<<9)
2948 #define DMAE_COMMAND_ENDIANITY_SHIFT 9
2949 #define DMAE_COMMAND_PORT (0x1<<11)
2950 #define DMAE_COMMAND_PORT_SHIFT 11
2951 #define DMAE_COMMAND_CRC_RESET (0x1<<12)
2952 #define DMAE_COMMAND_CRC_RESET_SHIFT 12
2953 #define DMAE_COMMAND_SRC_RESET (0x1<<13)
2954 #define DMAE_COMMAND_SRC_RESET_SHIFT 13
2955 #define DMAE_COMMAND_DST_RESET (0x1<<14)
2956 #define DMAE_COMMAND_DST_RESET_SHIFT 14
2957 #define DMAE_COMMAND_E1HVN (0x3<<15)
2958 #define DMAE_COMMAND_E1HVN_SHIFT 15
2959 #define DMAE_COMMAND_DST_VN (0x3<<17)
2960 #define DMAE_COMMAND_DST_VN_SHIFT 17
2961 #define DMAE_COMMAND_C_FUNC (0x1<<19)
2962 #define DMAE_COMMAND_C_FUNC_SHIFT 19
2963 #define DMAE_COMMAND_ERR_POLICY (0x3<<20)
2964 #define DMAE_COMMAND_ERR_POLICY_SHIFT 20
2965 #define DMAE_COMMAND_RESERVED0 (0x3FF<<22)
2966 #define DMAE_COMMAND_RESERVED0_SHIFT 22
2971 #if defined(__BIG_ENDIAN)
2973 #define DMAE_COMMAND_SRC_VFID (0x3F<<0)
2974 #define DMAE_COMMAND_SRC_VFID_SHIFT 0
2975 #define DMAE_COMMAND_SRC_VFPF (0x1<<6)
2976 #define DMAE_COMMAND_SRC_VFPF_SHIFT 6
2977 #define DMAE_COMMAND_RESERVED1 (0x1<<7)
2978 #define DMAE_COMMAND_RESERVED1_SHIFT 7
2979 #define DMAE_COMMAND_DST_VFID (0x3F<<8)
2980 #define DMAE_COMMAND_DST_VFID_SHIFT 8
2981 #define DMAE_COMMAND_DST_VFPF (0x1<<14)
2982 #define DMAE_COMMAND_DST_VFPF_SHIFT 14
2983 #define DMAE_COMMAND_RESERVED2 (0x1<<15)
2984 #define DMAE_COMMAND_RESERVED2_SHIFT 15
2986 #elif defined(__LITTLE_ENDIAN)
2989 #define DMAE_COMMAND_SRC_VFID (0x3F<<0)
2990 #define DMAE_COMMAND_SRC_VFID_SHIFT 0
2991 #define DMAE_COMMAND_SRC_VFPF (0x1<<6)
2992 #define DMAE_COMMAND_SRC_VFPF_SHIFT 6
2993 #define DMAE_COMMAND_RESERVED1 (0x1<<7)
2994 #define DMAE_COMMAND_RESERVED1_SHIFT 7
2995 #define DMAE_COMMAND_DST_VFID (0x3F<<8)
2996 #define DMAE_COMMAND_DST_VFID_SHIFT 8
2997 #define DMAE_COMMAND_DST_VFPF (0x1<<14)
2998 #define DMAE_COMMAND_DST_VFPF_SHIFT 14
2999 #define DMAE_COMMAND_RESERVED2 (0x1<<15)
3000 #define DMAE_COMMAND_RESERVED2_SHIFT 15
3007 #if defined(__BIG_ENDIAN)
3010 #elif defined(__LITTLE_ENDIAN)
3014 #if defined(__BIG_ENDIAN)
3017 #elif defined(__LITTLE_ENDIAN)
3021 #if defined(__BIG_ENDIAN)
3024 #elif defined(__LITTLE_ENDIAN)
3032 * common data for all protocols
3034 struct doorbell_hdr {
3036 #define DOORBELL_HDR_RX (0x1<<0)
3037 #define DOORBELL_HDR_RX_SHIFT 0
3038 #define DOORBELL_HDR_DB_TYPE (0x1<<1)
3039 #define DOORBELL_HDR_DB_TYPE_SHIFT 1
3040 #define DOORBELL_HDR_DPM_SIZE (0x3<<2)
3041 #define DOORBELL_HDR_DPM_SIZE_SHIFT 2
3042 #define DOORBELL_HDR_CONN_TYPE (0xF<<4)
3043 #define DOORBELL_HDR_CONN_TYPE_SHIFT 4
3049 struct eth_tx_doorbell {
3050 #if defined(__BIG_ENDIAN)
3053 #define ETH_TX_DOORBELL_NUM_BDS (0x3F<<0)
3054 #define ETH_TX_DOORBELL_NUM_BDS_SHIFT 0
3055 #define ETH_TX_DOORBELL_RESERVED_TX_FIN_FLAG (0x1<<6)
3056 #define ETH_TX_DOORBELL_RESERVED_TX_FIN_FLAG_SHIFT 6
3057 #define ETH_TX_DOORBELL_SPARE (0x1<<7)
3058 #define ETH_TX_DOORBELL_SPARE_SHIFT 7
3059 struct doorbell_hdr hdr;
3060 #elif defined(__LITTLE_ENDIAN)
3061 struct doorbell_hdr hdr;
3063 #define ETH_TX_DOORBELL_NUM_BDS (0x3F<<0)
3064 #define ETH_TX_DOORBELL_NUM_BDS_SHIFT 0
3065 #define ETH_TX_DOORBELL_RESERVED_TX_FIN_FLAG (0x1<<6)
3066 #define ETH_TX_DOORBELL_RESERVED_TX_FIN_FLAG_SHIFT 6
3067 #define ETH_TX_DOORBELL_SPARE (0x1<<7)
3068 #define ETH_TX_DOORBELL_SPARE_SHIFT 7
3075 * 3 lines. status block
3077 struct hc_status_block_e1x {
3078 __le16 index_values[HC_SB_MAX_INDICES_E1X];
3079 __le16 running_index[HC_SB_MAX_SM];
3086 struct host_hc_status_block_e1x {
3087 struct hc_status_block_e1x sb;
3092 * 3 lines. status block
3094 struct hc_status_block_e2 {
3095 __le16 index_values[HC_SB_MAX_INDICES_E2];
3096 __le16 running_index[HC_SB_MAX_SM];
3097 __le32 reserved[11];
3103 struct host_hc_status_block_e2 {
3104 struct hc_status_block_e2 sb;
3109 * 5 lines. slow-path status block
3111 struct hc_sp_status_block {
3112 __le16 index_values[HC_SP_SB_MAX_INDICES];
3113 __le16 running_index;
3121 struct host_sp_status_block {
3122 struct atten_sp_status_block atten_status_block;
3123 struct hc_sp_status_block sp_sb;
3128 * IGU driver acknowledgment register
3130 struct igu_ack_register {
3131 #if defined(__BIG_ENDIAN)
3132 u16 sb_id_and_flags;
3133 #define IGU_ACK_REGISTER_STATUS_BLOCK_ID (0x1F<<0)
3134 #define IGU_ACK_REGISTER_STATUS_BLOCK_ID_SHIFT 0
3135 #define IGU_ACK_REGISTER_STORM_ID (0x7<<5)
3136 #define IGU_ACK_REGISTER_STORM_ID_SHIFT 5
3137 #define IGU_ACK_REGISTER_UPDATE_INDEX (0x1<<8)
3138 #define IGU_ACK_REGISTER_UPDATE_INDEX_SHIFT 8
3139 #define IGU_ACK_REGISTER_INTERRUPT_MODE (0x3<<9)
3140 #define IGU_ACK_REGISTER_INTERRUPT_MODE_SHIFT 9
3141 #define IGU_ACK_REGISTER_RESERVED (0x1F<<11)
3142 #define IGU_ACK_REGISTER_RESERVED_SHIFT 11
3143 u16 status_block_index;
3144 #elif defined(__LITTLE_ENDIAN)
3145 u16 status_block_index;
3146 u16 sb_id_and_flags;
3147 #define IGU_ACK_REGISTER_STATUS_BLOCK_ID (0x1F<<0)
3148 #define IGU_ACK_REGISTER_STATUS_BLOCK_ID_SHIFT 0
3149 #define IGU_ACK_REGISTER_STORM_ID (0x7<<5)
3150 #define IGU_ACK_REGISTER_STORM_ID_SHIFT 5
3151 #define IGU_ACK_REGISTER_UPDATE_INDEX (0x1<<8)
3152 #define IGU_ACK_REGISTER_UPDATE_INDEX_SHIFT 8
3153 #define IGU_ACK_REGISTER_INTERRUPT_MODE (0x3<<9)
3154 #define IGU_ACK_REGISTER_INTERRUPT_MODE_SHIFT 9
3155 #define IGU_ACK_REGISTER_RESERVED (0x1F<<11)
3156 #define IGU_ACK_REGISTER_RESERVED_SHIFT 11
3162 * IGU driver acknowledgement register
3164 struct igu_backward_compatible {
3165 u32 sb_id_and_flags;
3166 #define IGU_BACKWARD_COMPATIBLE_SB_INDEX (0xFFFF<<0)
3167 #define IGU_BACKWARD_COMPATIBLE_SB_INDEX_SHIFT 0
3168 #define IGU_BACKWARD_COMPATIBLE_SB_SELECT (0x1F<<16)
3169 #define IGU_BACKWARD_COMPATIBLE_SB_SELECT_SHIFT 16
3170 #define IGU_BACKWARD_COMPATIBLE_SEGMENT_ACCESS (0x7<<21)
3171 #define IGU_BACKWARD_COMPATIBLE_SEGMENT_ACCESS_SHIFT 21
3172 #define IGU_BACKWARD_COMPATIBLE_BUPDATE (0x1<<24)
3173 #define IGU_BACKWARD_COMPATIBLE_BUPDATE_SHIFT 24
3174 #define IGU_BACKWARD_COMPATIBLE_ENABLE_INT (0x3<<25)
3175 #define IGU_BACKWARD_COMPATIBLE_ENABLE_INT_SHIFT 25
3176 #define IGU_BACKWARD_COMPATIBLE_RESERVED_0 (0x1F<<27)
3177 #define IGU_BACKWARD_COMPATIBLE_RESERVED_0_SHIFT 27
3183 * IGU driver acknowledgement register
3185 struct igu_regular {
3186 u32 sb_id_and_flags;
3187 #define IGU_REGULAR_SB_INDEX (0xFFFFF<<0)
3188 #define IGU_REGULAR_SB_INDEX_SHIFT 0
3189 #define IGU_REGULAR_RESERVED0 (0x1<<20)
3190 #define IGU_REGULAR_RESERVED0_SHIFT 20
3191 #define IGU_REGULAR_SEGMENT_ACCESS (0x7<<21)
3192 #define IGU_REGULAR_SEGMENT_ACCESS_SHIFT 21
3193 #define IGU_REGULAR_BUPDATE (0x1<<24)
3194 #define IGU_REGULAR_BUPDATE_SHIFT 24
3195 #define IGU_REGULAR_ENABLE_INT (0x3<<25)
3196 #define IGU_REGULAR_ENABLE_INT_SHIFT 25
3197 #define IGU_REGULAR_RESERVED_1 (0x1<<27)
3198 #define IGU_REGULAR_RESERVED_1_SHIFT 27
3199 #define IGU_REGULAR_CLEANUP_TYPE (0x3<<28)
3200 #define IGU_REGULAR_CLEANUP_TYPE_SHIFT 28
3201 #define IGU_REGULAR_CLEANUP_SET (0x1<<30)
3202 #define IGU_REGULAR_CLEANUP_SET_SHIFT 30
3203 #define IGU_REGULAR_BCLEANUP (0x1<<31)
3204 #define IGU_REGULAR_BCLEANUP_SHIFT 31
3209 * IGU driver acknowledgement register
3211 union igu_consprod_reg {
3212 struct igu_regular regular;
3213 struct igu_backward_compatible backward_compatible;
3218 * Igu control commands
3221 IGU_CTRL_CMD_TYPE_RD,
3222 IGU_CTRL_CMD_TYPE_WR,
3228 * Control register for the IGU command register
3230 struct igu_ctrl_reg {
3232 #define IGU_CTRL_REG_ADDRESS (0xFFF<<0)
3233 #define IGU_CTRL_REG_ADDRESS_SHIFT 0
3234 #define IGU_CTRL_REG_FID (0x7F<<12)
3235 #define IGU_CTRL_REG_FID_SHIFT 12
3236 #define IGU_CTRL_REG_RESERVED (0x1<<19)
3237 #define IGU_CTRL_REG_RESERVED_SHIFT 19
3238 #define IGU_CTRL_REG_TYPE (0x1<<20)
3239 #define IGU_CTRL_REG_TYPE_SHIFT 20
3240 #define IGU_CTRL_REG_UNUSED (0x7FF<<21)
3241 #define IGU_CTRL_REG_UNUSED_SHIFT 21
3246 * Igu interrupt command
3260 enum igu_seg_access {
3261 IGU_SEG_ACCESS_NORM,
3263 IGU_SEG_ACCESS_ATTN,
3269 * Parser parsing flags field
3271 struct parsing_flags {
3273 #define PARSING_FLAGS_ETHERNET_ADDRESS_TYPE (0x1<<0)
3274 #define PARSING_FLAGS_ETHERNET_ADDRESS_TYPE_SHIFT 0
3275 #define PARSING_FLAGS_VLAN (0x1<<1)
3276 #define PARSING_FLAGS_VLAN_SHIFT 1
3277 #define PARSING_FLAGS_EXTRA_VLAN (0x1<<2)
3278 #define PARSING_FLAGS_EXTRA_VLAN_SHIFT 2
3279 #define PARSING_FLAGS_OVER_ETHERNET_PROTOCOL (0x3<<3)
3280 #define PARSING_FLAGS_OVER_ETHERNET_PROTOCOL_SHIFT 3
3281 #define PARSING_FLAGS_IP_OPTIONS (0x1<<5)
3282 #define PARSING_FLAGS_IP_OPTIONS_SHIFT 5
3283 #define PARSING_FLAGS_FRAGMENTATION_STATUS (0x1<<6)
3284 #define PARSING_FLAGS_FRAGMENTATION_STATUS_SHIFT 6
3285 #define PARSING_FLAGS_OVER_IP_PROTOCOL (0x3<<7)
3286 #define PARSING_FLAGS_OVER_IP_PROTOCOL_SHIFT 7
3287 #define PARSING_FLAGS_PURE_ACK_INDICATION (0x1<<9)
3288 #define PARSING_FLAGS_PURE_ACK_INDICATION_SHIFT 9
3289 #define PARSING_FLAGS_TCP_OPTIONS_EXIST (0x1<<10)
3290 #define PARSING_FLAGS_TCP_OPTIONS_EXIST_SHIFT 10
3291 #define PARSING_FLAGS_TIME_STAMP_EXIST_FLAG (0x1<<11)
3292 #define PARSING_FLAGS_TIME_STAMP_EXIST_FLAG_SHIFT 11
3293 #define PARSING_FLAGS_CONNECTION_MATCH (0x1<<12)
3294 #define PARSING_FLAGS_CONNECTION_MATCH_SHIFT 12
3295 #define PARSING_FLAGS_LLC_SNAP (0x1<<13)
3296 #define PARSING_FLAGS_LLC_SNAP_SHIFT 13
3297 #define PARSING_FLAGS_RESERVED0 (0x3<<14)
3298 #define PARSING_FLAGS_RESERVED0_SHIFT 14
3303 * Parsing flags for TCP ACK type
3305 enum prs_flags_ack_type {
3306 PRS_FLAG_PUREACK_PIGGY,
3307 PRS_FLAG_PUREACK_PURE,
3308 MAX_PRS_FLAGS_ACK_TYPE
3313 * Parsing flags for Ethernet address type
3315 enum prs_flags_eth_addr_type {
3316 PRS_FLAG_ETHTYPE_NON_UNICAST,
3317 PRS_FLAG_ETHTYPE_UNICAST,
3318 MAX_PRS_FLAGS_ETH_ADDR_TYPE
3323 * Parsing flags for over-ethernet protocol
3325 enum prs_flags_over_eth {
3326 PRS_FLAG_OVERETH_UNKNOWN,
3327 PRS_FLAG_OVERETH_IPV4,
3328 PRS_FLAG_OVERETH_IPV6,
3329 PRS_FLAG_OVERETH_LLCSNAP_UNKNOWN,
3330 MAX_PRS_FLAGS_OVER_ETH
3335 * Parsing flags for over-IP protocol
3337 enum prs_flags_over_ip {
3338 PRS_FLAG_OVERIP_UNKNOWN,
3339 PRS_FLAG_OVERIP_TCP,
3340 PRS_FLAG_OVERIP_UDP,
3341 MAX_PRS_FLAGS_OVER_IP
3346 * SDM operation gen command (generate aggregative interrupt)
3350 #define SDM_OP_GEN_COMP_PARAM (0x1F<<0)
3351 #define SDM_OP_GEN_COMP_PARAM_SHIFT 0
3352 #define SDM_OP_GEN_COMP_TYPE (0x7<<5)
3353 #define SDM_OP_GEN_COMP_TYPE_SHIFT 5
3354 #define SDM_OP_GEN_AGG_VECT_IDX (0xFF<<8)
3355 #define SDM_OP_GEN_AGG_VECT_IDX_SHIFT 8
3356 #define SDM_OP_GEN_AGG_VECT_IDX_VALID (0x1<<16)
3357 #define SDM_OP_GEN_AGG_VECT_IDX_VALID_SHIFT 16
3358 #define SDM_OP_GEN_RESERVED (0x7FFF<<17)
3359 #define SDM_OP_GEN_RESERVED_SHIFT 17
3364 * Timers connection context
3366 struct timers_block_context {
3371 #define __TIMERS_BLOCK_CONTEXT_NUM_OF_ACTIVE_TIMERS (0x3<<0)
3372 #define __TIMERS_BLOCK_CONTEXT_NUM_OF_ACTIVE_TIMERS_SHIFT 0
3373 #define TIMERS_BLOCK_CONTEXT_CONN_VALID_FLG (0x1<<2)
3374 #define TIMERS_BLOCK_CONTEXT_CONN_VALID_FLG_SHIFT 2
3375 #define __TIMERS_BLOCK_CONTEXT_RESERVED0 (0x1FFFFFFF<<3)
3376 #define __TIMERS_BLOCK_CONTEXT_RESERVED0_SHIFT 3
3381 * The eth aggregative context of Tstorm
3383 struct tstorm_eth_ag_context {
3384 u32 __reserved0[14];
3389 * The eth aggregative context of Ustorm
3391 struct ustorm_eth_ag_context {
3393 #if defined(__BIG_ENDIAN)
3397 #elif defined(__LITTLE_ENDIAN)
3407 * The eth aggregative context of Xstorm
3409 struct xstorm_eth_ag_context {
3411 #if defined(__BIG_ENDIAN)
3415 #elif defined(__LITTLE_ENDIAN)
3425 * doorbell message sent to the chip
3428 #if defined(__BIG_ENDIAN)
3431 struct doorbell_hdr header;
3432 #elif defined(__LITTLE_ENDIAN)
3433 struct doorbell_hdr header;
3441 * doorbell message sent to the chip
3443 struct doorbell_set_prod {
3444 #if defined(__BIG_ENDIAN)
3447 struct doorbell_hdr header;
3448 #elif defined(__LITTLE_ENDIAN)
3449 struct doorbell_hdr header;
3461 struct regpair_native {
3467 * Classify rule opcodes in E2/E3
3469 enum classify_rule {
3470 CLASSIFY_RULE_OPCODE_MAC,
3471 CLASSIFY_RULE_OPCODE_VLAN,
3472 CLASSIFY_RULE_OPCODE_PAIR,
3473 CLASSIFY_RULE_OPCODE_VXLAN,
3479 * Classify rule types in E2/E3
3481 enum classify_rule_action_type {
3482 CLASSIFY_RULE_REMOVE,
3484 MAX_CLASSIFY_RULE_ACTION_TYPE
3489 * client init ramrod data
3491 struct client_init_general_data {
3493 u8 statistics_counter_id;
3494 u8 statistics_en_flg;
3499 u8 statistics_zero_flg;
3509 * client init rx data
3511 struct client_init_rx_data {
3513 #define CLIENT_INIT_RX_DATA_TPA_EN_IPV4 (0x1<<0)
3514 #define CLIENT_INIT_RX_DATA_TPA_EN_IPV4_SHIFT 0
3515 #define CLIENT_INIT_RX_DATA_TPA_EN_IPV6 (0x1<<1)
3516 #define CLIENT_INIT_RX_DATA_TPA_EN_IPV6_SHIFT 1
3517 #define CLIENT_INIT_RX_DATA_TPA_MODE (0x1<<2)
3518 #define CLIENT_INIT_RX_DATA_TPA_MODE_SHIFT 2
3519 #define CLIENT_INIT_RX_DATA_RESERVED5 (0x1F<<3)
3520 #define CLIENT_INIT_RX_DATA_RESERVED5_SHIFT 3
3521 u8 vmqueue_mode_en_flg;
3522 u8 extra_data_over_sgl_en_flg;
3523 u8 cache_line_alignment_log_size;
3524 u8 enable_dynamic_hc;
3525 u8 max_sges_for_packet;
3527 u8 drop_ip_cs_err_flg;
3528 u8 drop_tcp_cs_err_flg;
3530 u8 drop_udp_cs_err_flg;
3531 u8 inner_vlan_removal_enable_flg;
3532 u8 outer_vlan_removal_enable_flg;
3534 u8 rx_sb_index_number;
3535 u8 dont_verify_rings_pause_thr_flg;
3537 u8 silent_vlan_removal_flg;
3538 __le16 max_bytes_on_bd;
3539 __le16 sge_buff_size;
3540 u8 approx_mcast_engine_id;
3542 struct regpair bd_page_base;
3543 struct regpair sge_page_base;
3544 struct regpair cqe_page_base;
3547 __le16 max_agg_size;
3549 #define CLIENT_INIT_RX_DATA_UCAST_DROP_ALL (0x1<<0)
3550 #define CLIENT_INIT_RX_DATA_UCAST_DROP_ALL_SHIFT 0
3551 #define CLIENT_INIT_RX_DATA_UCAST_ACCEPT_ALL (0x1<<1)
3552 #define CLIENT_INIT_RX_DATA_UCAST_ACCEPT_ALL_SHIFT 1
3553 #define CLIENT_INIT_RX_DATA_UCAST_ACCEPT_UNMATCHED (0x1<<2)
3554 #define CLIENT_INIT_RX_DATA_UCAST_ACCEPT_UNMATCHED_SHIFT 2
3555 #define CLIENT_INIT_RX_DATA_MCAST_DROP_ALL (0x1<<3)
3556 #define CLIENT_INIT_RX_DATA_MCAST_DROP_ALL_SHIFT 3
3557 #define CLIENT_INIT_RX_DATA_MCAST_ACCEPT_ALL (0x1<<4)
3558 #define CLIENT_INIT_RX_DATA_MCAST_ACCEPT_ALL_SHIFT 4
3559 #define CLIENT_INIT_RX_DATA_BCAST_ACCEPT_ALL (0x1<<5)
3560 #define CLIENT_INIT_RX_DATA_BCAST_ACCEPT_ALL_SHIFT 5
3561 #define CLIENT_INIT_RX_DATA_ACCEPT_ANY_VLAN (0x1<<6)
3562 #define CLIENT_INIT_RX_DATA_ACCEPT_ANY_VLAN_SHIFT 6
3563 #define CLIENT_INIT_RX_DATA_RESERVED2 (0x1FF<<7)
3564 #define CLIENT_INIT_RX_DATA_RESERVED2_SHIFT 7
3565 __le16 cqe_pause_thr_low;
3566 __le16 cqe_pause_thr_high;
3567 __le16 bd_pause_thr_low;
3568 __le16 bd_pause_thr_high;
3569 __le16 sge_pause_thr_low;
3570 __le16 sge_pause_thr_high;
3572 __le16 silent_vlan_value;
3573 __le16 silent_vlan_mask;
3574 u8 handle_ptp_pkts_flg;
3580 * client init tx data
3582 struct client_init_tx_data {
3583 u8 enforce_security_flg;
3584 u8 tx_status_block_id;
3585 u8 tx_sb_index_number;
3586 u8 tss_leading_client_id;
3587 u8 tx_switching_flg;
3588 u8 anti_spoofing_flg;
3589 __le16 default_vlan;
3590 struct regpair tx_bd_page_base;
3592 #define CLIENT_INIT_TX_DATA_UCAST_ACCEPT_ALL (0x1<<0)
3593 #define CLIENT_INIT_TX_DATA_UCAST_ACCEPT_ALL_SHIFT 0
3594 #define CLIENT_INIT_TX_DATA_MCAST_ACCEPT_ALL (0x1<<1)
3595 #define CLIENT_INIT_TX_DATA_MCAST_ACCEPT_ALL_SHIFT 1
3596 #define CLIENT_INIT_TX_DATA_BCAST_ACCEPT_ALL (0x1<<2)
3597 #define CLIENT_INIT_TX_DATA_BCAST_ACCEPT_ALL_SHIFT 2
3598 #define CLIENT_INIT_TX_DATA_ACCEPT_ANY_VLAN (0x1<<3)
3599 #define CLIENT_INIT_TX_DATA_ACCEPT_ANY_VLAN_SHIFT 3
3600 #define CLIENT_INIT_TX_DATA_RESERVED0 (0xFFF<<4)
3601 #define CLIENT_INIT_TX_DATA_RESERVED0_SHIFT 4
3602 u8 default_vlan_flg;
3603 u8 force_default_pri_flg;
3604 u8 tunnel_lso_inc_ip_id;
3605 u8 refuse_outband_vlan_flg;
3606 u8 tunnel_non_lso_pcsum_location;
3607 u8 tunnel_non_lso_outer_ip_csum_location;
3611 * client init ramrod data
3613 struct client_init_ramrod_data {
3614 struct client_init_general_data general;
3615 struct client_init_rx_data rx;
3616 struct client_init_tx_data tx;
3621 * client update ramrod data
3623 struct client_update_ramrod_data {
3626 u8 inner_vlan_removal_enable_flg;
3627 u8 inner_vlan_removal_change_flg;
3628 u8 outer_vlan_removal_enable_flg;
3629 u8 outer_vlan_removal_change_flg;
3630 u8 anti_spoofing_enable_flg;
3631 u8 anti_spoofing_change_flg;
3633 u8 activate_change_flg;
3634 __le16 default_vlan;
3635 u8 default_vlan_enable_flg;
3636 u8 default_vlan_change_flg;
3637 __le16 silent_vlan_value;
3638 __le16 silent_vlan_mask;
3639 u8 silent_vlan_removal_flg;
3640 u8 silent_vlan_change_flg;
3641 u8 refuse_outband_vlan_flg;
3642 u8 refuse_outband_vlan_change_flg;
3643 u8 tx_switching_flg;
3644 u8 tx_switching_change_flg;
3645 u8 handle_ptp_pkts_flg;
3646 u8 handle_ptp_pkts_change_flg;
3653 * The eth storm context of Cstorm
3655 struct cstorm_eth_st_context {
3660 struct double_regpair {
3667 /* 2nd parse bd type used in ethernet tx BDs */
3668 enum eth_2nd_parse_bd_type {
3669 ETH_2ND_PARSE_BD_TYPE_LSO_TUNNEL,
3670 MAX_ETH_2ND_PARSE_BD_TYPE
3674 * Ethernet address typesm used in ethernet tx BDs
3676 enum eth_addr_type {
3688 struct eth_classify_cmd_header {
3689 u8 cmd_general_data;
3690 #define ETH_CLASSIFY_CMD_HEADER_RX_CMD (0x1<<0)
3691 #define ETH_CLASSIFY_CMD_HEADER_RX_CMD_SHIFT 0
3692 #define ETH_CLASSIFY_CMD_HEADER_TX_CMD (0x1<<1)
3693 #define ETH_CLASSIFY_CMD_HEADER_TX_CMD_SHIFT 1
3694 #define ETH_CLASSIFY_CMD_HEADER_OPCODE (0x3<<2)
3695 #define ETH_CLASSIFY_CMD_HEADER_OPCODE_SHIFT 2
3696 #define ETH_CLASSIFY_CMD_HEADER_IS_ADD (0x1<<4)
3697 #define ETH_CLASSIFY_CMD_HEADER_IS_ADD_SHIFT 4
3698 #define ETH_CLASSIFY_CMD_HEADER_RESERVED0 (0x7<<5)
3699 #define ETH_CLASSIFY_CMD_HEADER_RESERVED0_SHIFT 5
3707 * header for eth classification config ramrod
3709 struct eth_classify_header {
3718 * Command for adding/removing a MAC classification rule
3720 struct eth_classify_mac_cmd {
3721 struct eth_classify_cmd_header header;
3732 * Command for adding/removing a MAC-VLAN pair classification rule
3734 struct eth_classify_pair_cmd {
3735 struct eth_classify_cmd_header header;
3746 * Command for adding/removing a VLAN classification rule
3748 struct eth_classify_vlan_cmd {
3749 struct eth_classify_cmd_header header;
3757 * Command for adding/removing a VXLAN classification rule
3759 struct eth_classify_vxlan_cmd {
3760 struct eth_classify_cmd_header header;
3762 __le16 inner_mac_lsb;
3763 __le16 inner_mac_mid;
3764 __le16 inner_mac_msb;
3769 * union for eth classification rule
3771 union eth_classify_rule_cmd {
3772 struct eth_classify_mac_cmd mac;
3773 struct eth_classify_vlan_cmd vlan;
3774 struct eth_classify_pair_cmd pair;
3775 struct eth_classify_vxlan_cmd vxlan;
3779 * parameters for eth classification configuration ramrod
3781 struct eth_classify_rules_ramrod_data {
3782 struct eth_classify_header header;
3783 union eth_classify_rule_cmd rules[CLASSIFY_RULES_COUNT];
3788 * The data contain client ID need to the ramrod
3790 struct eth_common_ramrod_data {
3797 * The eth storm context of Ustorm
3799 struct ustorm_eth_st_context {
3804 * The eth storm context of Tstorm
3806 struct tstorm_eth_st_context {
3807 u32 __reserved0[28];
3811 * The eth storm context of Xstorm
3813 struct xstorm_eth_st_context {
3818 * Ethernet connection context
3820 struct eth_context {
3821 struct ustorm_eth_st_context ustorm_st_context;
3822 struct tstorm_eth_st_context tstorm_st_context;
3823 struct xstorm_eth_ag_context xstorm_ag_context;
3824 struct tstorm_eth_ag_context tstorm_ag_context;
3825 struct cstorm_eth_ag_context cstorm_ag_context;
3826 struct ustorm_eth_ag_context ustorm_ag_context;
3827 struct timers_block_context timers_context;
3828 struct xstorm_eth_st_context xstorm_st_context;
3829 struct cstorm_eth_st_context cstorm_st_context;
3834 * union for sgl and raw data.
3836 union eth_sgl_or_raw_data {
3842 * eth FP end aggregation CQE parameters struct
3844 struct eth_end_agg_rx_cqe {
3845 u8 type_error_flags;
3846 #define ETH_END_AGG_RX_CQE_TYPE (0x3<<0)
3847 #define ETH_END_AGG_RX_CQE_TYPE_SHIFT 0
3848 #define ETH_END_AGG_RX_CQE_SGL_RAW_SEL (0x1<<2)
3849 #define ETH_END_AGG_RX_CQE_SGL_RAW_SEL_SHIFT 2
3850 #define ETH_END_AGG_RX_CQE_RESERVED0 (0x1F<<3)
3851 #define ETH_END_AGG_RX_CQE_RESERVED0_SHIFT 3
3855 __le32 timestamp_delta;
3856 __le16 num_of_coalesced_segs;
3861 union eth_sgl_or_raw_data sgl_or_raw_data;
3862 __le32 reserved5[8];
3867 * regular eth FP CQE parameters struct
3869 struct eth_fast_path_rx_cqe {
3870 u8 type_error_flags;
3871 #define ETH_FAST_PATH_RX_CQE_TYPE (0x3<<0)
3872 #define ETH_FAST_PATH_RX_CQE_TYPE_SHIFT 0
3873 #define ETH_FAST_PATH_RX_CQE_SGL_RAW_SEL (0x1<<2)
3874 #define ETH_FAST_PATH_RX_CQE_SGL_RAW_SEL_SHIFT 2
3875 #define ETH_FAST_PATH_RX_CQE_PHY_DECODE_ERR_FLG (0x1<<3)
3876 #define ETH_FAST_PATH_RX_CQE_PHY_DECODE_ERR_FLG_SHIFT 3
3877 #define ETH_FAST_PATH_RX_CQE_IP_BAD_XSUM_FLG (0x1<<4)
3878 #define ETH_FAST_PATH_RX_CQE_IP_BAD_XSUM_FLG_SHIFT 4
3879 #define ETH_FAST_PATH_RX_CQE_L4_BAD_XSUM_FLG (0x1<<5)
3880 #define ETH_FAST_PATH_RX_CQE_L4_BAD_XSUM_FLG_SHIFT 5
3881 #define ETH_FAST_PATH_RX_CQE_PTP_PKT (0x1<<6)
3882 #define ETH_FAST_PATH_RX_CQE_PTP_PKT_SHIFT 6
3883 #define ETH_FAST_PATH_RX_CQE_RESERVED0 (0x1<<7)
3884 #define ETH_FAST_PATH_RX_CQE_RESERVED0_SHIFT 7
3886 #define ETH_FAST_PATH_RX_CQE_RSS_HASH_TYPE (0x7<<0)
3887 #define ETH_FAST_PATH_RX_CQE_RSS_HASH_TYPE_SHIFT 0
3888 #define ETH_FAST_PATH_RX_CQE_RSS_HASH_FLG (0x1<<3)
3889 #define ETH_FAST_PATH_RX_CQE_RSS_HASH_FLG_SHIFT 3
3890 #define ETH_FAST_PATH_RX_CQE_BROADCAST_FLG (0x1<<4)
3891 #define ETH_FAST_PATH_RX_CQE_BROADCAST_FLG_SHIFT 4
3892 #define ETH_FAST_PATH_RX_CQE_MAC_MATCH_FLG (0x1<<5)
3893 #define ETH_FAST_PATH_RX_CQE_MAC_MATCH_FLG_SHIFT 5
3894 #define ETH_FAST_PATH_RX_CQE_IP_XSUM_NO_VALIDATION_FLG (0x1<<6)
3895 #define ETH_FAST_PATH_RX_CQE_IP_XSUM_NO_VALIDATION_FLG_SHIFT 6
3896 #define ETH_FAST_PATH_RX_CQE_L4_XSUM_NO_VALIDATION_FLG (0x1<<7)
3897 #define ETH_FAST_PATH_RX_CQE_L4_XSUM_NO_VALIDATION_FLG_SHIFT 7
3899 u8 placement_offset;
3900 __le32 rss_hash_result;
3902 __le16 pkt_len_or_gro_seg_len;
3904 struct parsing_flags pars_flags;
3905 union eth_sgl_or_raw_data sgl_or_raw_data;
3907 u8 tunn_inner_hdrs_offset;
3909 __le32 tunn_tenant_id;
3916 * Command for setting classification flags for a client
3918 struct eth_filter_rules_cmd {
3919 u8 cmd_general_data;
3920 #define ETH_FILTER_RULES_CMD_RX_CMD (0x1<<0)
3921 #define ETH_FILTER_RULES_CMD_RX_CMD_SHIFT 0
3922 #define ETH_FILTER_RULES_CMD_TX_CMD (0x1<<1)
3923 #define ETH_FILTER_RULES_CMD_TX_CMD_SHIFT 1
3924 #define ETH_FILTER_RULES_CMD_RESERVED0 (0x3F<<2)
3925 #define ETH_FILTER_RULES_CMD_RESERVED0_SHIFT 2
3930 #define ETH_FILTER_RULES_CMD_UCAST_DROP_ALL (0x1<<0)
3931 #define ETH_FILTER_RULES_CMD_UCAST_DROP_ALL_SHIFT 0
3932 #define ETH_FILTER_RULES_CMD_UCAST_ACCEPT_ALL (0x1<<1)
3933 #define ETH_FILTER_RULES_CMD_UCAST_ACCEPT_ALL_SHIFT 1
3934 #define ETH_FILTER_RULES_CMD_UCAST_ACCEPT_UNMATCHED (0x1<<2)
3935 #define ETH_FILTER_RULES_CMD_UCAST_ACCEPT_UNMATCHED_SHIFT 2
3936 #define ETH_FILTER_RULES_CMD_MCAST_DROP_ALL (0x1<<3)
3937 #define ETH_FILTER_RULES_CMD_MCAST_DROP_ALL_SHIFT 3
3938 #define ETH_FILTER_RULES_CMD_MCAST_ACCEPT_ALL (0x1<<4)
3939 #define ETH_FILTER_RULES_CMD_MCAST_ACCEPT_ALL_SHIFT 4
3940 #define ETH_FILTER_RULES_CMD_BCAST_ACCEPT_ALL (0x1<<5)
3941 #define ETH_FILTER_RULES_CMD_BCAST_ACCEPT_ALL_SHIFT 5
3942 #define ETH_FILTER_RULES_CMD_ACCEPT_ANY_VLAN (0x1<<6)
3943 #define ETH_FILTER_RULES_CMD_ACCEPT_ANY_VLAN_SHIFT 6
3944 #define ETH_FILTER_RULES_CMD_RESERVED2 (0x1FF<<7)
3945 #define ETH_FILTER_RULES_CMD_RESERVED2_SHIFT 7
3947 struct regpair reserved4;
3952 * parameters for eth classification filters ramrod
3954 struct eth_filter_rules_ramrod_data {
3955 struct eth_classify_header header;
3956 struct eth_filter_rules_cmd rules[FILTER_RULES_COUNT];
3960 enum eth_fp_hsi_ver {
3968 * parameters for eth classification configuration ramrod
3970 struct eth_general_rules_ramrod_data {
3971 struct eth_classify_header header;
3972 union eth_classify_rule_cmd rules[CLASSIFY_RULES_COUNT];
3977 * The data for Halt ramrod
3979 struct eth_halt_ramrod_data {
3986 * destination and source mac address.
3988 struct eth_mac_addresses {
3989 #if defined(__BIG_ENDIAN)
3992 #elif defined(__LITTLE_ENDIAN)
3996 #if defined(__BIG_ENDIAN)
3999 #elif defined(__LITTLE_ENDIAN)
4003 #if defined(__BIG_ENDIAN)
4006 #elif defined(__LITTLE_ENDIAN)
4012 /* tunneling related data */
4013 struct eth_tunnel_data {
4017 __le16 fw_ip_hdr_csum;
4019 u8 ip_hdr_start_inner_w;
4021 #define ETH_TUNNEL_DATA_IPV6_OUTER (0x1<<0)
4022 #define ETH_TUNNEL_DATA_IPV6_OUTER_SHIFT 0
4023 #define ETH_TUNNEL_DATA_RESERVED (0x7F<<1)
4024 #define ETH_TUNNEL_DATA_RESERVED_SHIFT 1
4027 /* union for mac addresses and for tunneling data.
4028 * considered as tunneling data only if (tunnel_exist == 1).
4030 union eth_mac_addr_or_tunnel_data {
4031 struct eth_mac_addresses mac_addr;
4032 struct eth_tunnel_data tunnel_data;
4035 /*Command for setting multicast classification for a client */
4036 struct eth_multicast_rules_cmd {
4037 u8 cmd_general_data;
4038 #define ETH_MULTICAST_RULES_CMD_RX_CMD (0x1<<0)
4039 #define ETH_MULTICAST_RULES_CMD_RX_CMD_SHIFT 0
4040 #define ETH_MULTICAST_RULES_CMD_TX_CMD (0x1<<1)
4041 #define ETH_MULTICAST_RULES_CMD_TX_CMD_SHIFT 1
4042 #define ETH_MULTICAST_RULES_CMD_IS_ADD (0x1<<2)
4043 #define ETH_MULTICAST_RULES_CMD_IS_ADD_SHIFT 2
4044 #define ETH_MULTICAST_RULES_CMD_RESERVED0 (0x1F<<3)
4045 #define ETH_MULTICAST_RULES_CMD_RESERVED0_SHIFT 3
4050 struct regpair reserved3;
4054 * parameters for multicast classification ramrod
4056 struct eth_multicast_rules_ramrod_data {
4057 struct eth_classify_header header;
4058 struct eth_multicast_rules_cmd rules[MULTICAST_RULES_COUNT];
4062 * Place holder for ramrods protocol specific data
4064 struct ramrod_data {
4070 * union for ramrod data for Ethernet protocol (CQE) (force size of 16 bits)
4072 union eth_ramrod_data {
4073 struct ramrod_data general;
4078 * RSS toeplitz hash type, as reported in CQE
4080 enum eth_rss_hash_type {
4087 E1HOV_PRI_HASH_TYPE,
4089 MAX_ETH_RSS_HASH_TYPE
4097 ETH_RSS_MODE_DISABLED,
4098 ETH_RSS_MODE_REGULAR,
4099 ETH_RSS_MODE_VLAN_PRI,
4100 ETH_RSS_MODE_E1HOV_PRI,
4101 ETH_RSS_MODE_IP_DSCP,
4107 * parameters for RSS update ramrod (E2)
4109 struct eth_rss_update_ramrod_data {
4112 __le16 capabilities;
4113 #define ETH_RSS_UPDATE_RAMROD_DATA_IPV4_CAPABILITY (0x1<<0)
4114 #define ETH_RSS_UPDATE_RAMROD_DATA_IPV4_CAPABILITY_SHIFT 0
4115 #define ETH_RSS_UPDATE_RAMROD_DATA_IPV4_TCP_CAPABILITY (0x1<<1)
4116 #define ETH_RSS_UPDATE_RAMROD_DATA_IPV4_TCP_CAPABILITY_SHIFT 1
4117 #define ETH_RSS_UPDATE_RAMROD_DATA_IPV4_UDP_CAPABILITY (0x1<<2)
4118 #define ETH_RSS_UPDATE_RAMROD_DATA_IPV4_UDP_CAPABILITY_SHIFT 2
4119 #define ETH_RSS_UPDATE_RAMROD_DATA_IPV4_VXLAN_CAPABILITY (0x1<<3)
4120 #define ETH_RSS_UPDATE_RAMROD_DATA_IPV4_VXLAN_CAPABILITY_SHIFT 3
4121 #define ETH_RSS_UPDATE_RAMROD_DATA_IPV6_CAPABILITY (0x1<<4)
4122 #define ETH_RSS_UPDATE_RAMROD_DATA_IPV6_CAPABILITY_SHIFT 4
4123 #define ETH_RSS_UPDATE_RAMROD_DATA_IPV6_TCP_CAPABILITY (0x1<<5)
4124 #define ETH_RSS_UPDATE_RAMROD_DATA_IPV6_TCP_CAPABILITY_SHIFT 5
4125 #define ETH_RSS_UPDATE_RAMROD_DATA_IPV6_UDP_CAPABILITY (0x1<<6)
4126 #define ETH_RSS_UPDATE_RAMROD_DATA_IPV6_UDP_CAPABILITY_SHIFT 6
4127 #define ETH_RSS_UPDATE_RAMROD_DATA_IPV6_VXLAN_CAPABILITY (0x1<<7)
4128 #define ETH_RSS_UPDATE_RAMROD_DATA_IPV6_VXLAN_CAPABILITY_SHIFT 7
4129 #define ETH_RSS_UPDATE_RAMROD_DATA_TUNN_INNER_HDRS_CAPABILITY (0x1<<8)
4130 #define ETH_RSS_UPDATE_RAMROD_DATA_TUNN_INNER_HDRS_CAPABILITY_SHIFT 8
4131 #define ETH_RSS_UPDATE_RAMROD_DATA_UPDATE_RSS_KEY (0x1<<9)
4132 #define ETH_RSS_UPDATE_RAMROD_DATA_UPDATE_RSS_KEY_SHIFT 9
4133 #define ETH_RSS_UPDATE_RAMROD_DATA_RESERVED (0x3F<<10)
4134 #define ETH_RSS_UPDATE_RAMROD_DATA_RESERVED_SHIFT 10
4138 u8 indirection_table[T_ETH_INDIRECTION_TABLE_SIZE];
4139 __le32 rss_key[T_ETH_RSS_KEY];
4146 * The eth Rx Buffer Descriptor
4155 * Eth Rx Cqe structure- general structure for ramrods
4157 struct common_ramrod_eth_rx_cqe {
4159 #define COMMON_RAMROD_ETH_RX_CQE_TYPE (0x3<<0)
4160 #define COMMON_RAMROD_ETH_RX_CQE_TYPE_SHIFT 0
4161 #define COMMON_RAMROD_ETH_RX_CQE_ERROR (0x1<<2)
4162 #define COMMON_RAMROD_ETH_RX_CQE_ERROR_SHIFT 2
4163 #define COMMON_RAMROD_ETH_RX_CQE_RESERVED0 (0x1F<<3)
4164 #define COMMON_RAMROD_ETH_RX_CQE_RESERVED0_SHIFT 3
4167 __le32 conn_and_cmd_data;
4168 #define COMMON_RAMROD_ETH_RX_CQE_CID (0xFFFFFF<<0)
4169 #define COMMON_RAMROD_ETH_RX_CQE_CID_SHIFT 0
4170 #define COMMON_RAMROD_ETH_RX_CQE_CMD_ID (0xFF<<24)
4171 #define COMMON_RAMROD_ETH_RX_CQE_CMD_ID_SHIFT 24
4172 struct ramrod_data protocol_data;
4174 __le32 reserved2[11];
4178 * Rx Last CQE in page (in ETH)
4180 struct eth_rx_cqe_next_page {
4183 __le32 reserved[14];
4187 * union for all eth rx cqe types (fix their sizes)
4190 struct eth_fast_path_rx_cqe fast_path_cqe;
4191 struct common_ramrod_eth_rx_cqe ramrod_cqe;
4192 struct eth_rx_cqe_next_page next_page_cqe;
4193 struct eth_end_agg_rx_cqe end_agg_cqe;
4198 * Values for RX ETH CQE type field
4200 enum eth_rx_cqe_type {
4201 RX_ETH_CQE_TYPE_ETH_FASTPATH,
4202 RX_ETH_CQE_TYPE_ETH_RAMROD,
4203 RX_ETH_CQE_TYPE_ETH_START_AGG,
4204 RX_ETH_CQE_TYPE_ETH_STOP_AGG,
4210 * Type of SGL/Raw field in ETH RX fast path CQE
4212 enum eth_rx_fp_sel {
4220 * The eth Rx SGE Descriptor
4229 * common data for all protocols
4232 __le32 conn_and_cmd_data;
4233 #define SPE_HDR_CID (0xFFFFFF<<0)
4234 #define SPE_HDR_CID_SHIFT 0
4235 #define SPE_HDR_CMD_ID (0xFF<<24)
4236 #define SPE_HDR_CMD_ID_SHIFT 24
4238 #define SPE_HDR_CONN_TYPE (0xFF<<0)
4239 #define SPE_HDR_CONN_TYPE_SHIFT 0
4240 #define SPE_HDR_FUNCTION_ID (0xFF<<8)
4241 #define SPE_HDR_FUNCTION_ID_SHIFT 8
4246 * specific data for ethernet slow path element
4248 union eth_specific_data {
4249 u8 protocol_data[8];
4250 struct regpair client_update_ramrod_data;
4251 struct regpair client_init_ramrod_init_data;
4252 struct eth_halt_ramrod_data halt_ramrod_data;
4253 struct regpair update_data_addr;
4254 struct eth_common_ramrod_data common_ramrod_data;
4255 struct regpair classify_cfg_addr;
4256 struct regpair filter_cfg_addr;
4257 struct regpair mcast_cfg_addr;
4261 * Ethernet slow path element
4265 union eth_specific_data data;
4270 * Ethernet command ID for slow path elements
4272 enum eth_spqe_cmd_id {
4273 RAMROD_CMD_ID_ETH_UNUSED,
4274 RAMROD_CMD_ID_ETH_CLIENT_SETUP,
4275 RAMROD_CMD_ID_ETH_HALT,
4276 RAMROD_CMD_ID_ETH_FORWARD_SETUP,
4277 RAMROD_CMD_ID_ETH_TX_QUEUE_SETUP,
4278 RAMROD_CMD_ID_ETH_CLIENT_UPDATE,
4279 RAMROD_CMD_ID_ETH_EMPTY,
4280 RAMROD_CMD_ID_ETH_TERMINATE,
4281 RAMROD_CMD_ID_ETH_TPA_UPDATE,
4282 RAMROD_CMD_ID_ETH_CLASSIFICATION_RULES,
4283 RAMROD_CMD_ID_ETH_FILTER_RULES,
4284 RAMROD_CMD_ID_ETH_MULTICAST_RULES,
4285 RAMROD_CMD_ID_ETH_RSS_UPDATE,
4286 RAMROD_CMD_ID_ETH_SET_MAC,
4292 * eth tpa update command
4294 enum eth_tpa_update_command {
4295 TPA_UPDATE_NONE_COMMAND,
4296 TPA_UPDATE_ENABLE_COMMAND,
4297 TPA_UPDATE_DISABLE_COMMAND,
4298 MAX_ETH_TPA_UPDATE_COMMAND
4301 /* In case of LSO over IPv4 tunnel, whether to increment
4302 * IP ID on external IP header or internal IP header
4304 enum eth_tunnel_lso_inc_ip_id {
4307 MAX_ETH_TUNNEL_LSO_INC_IP_ID
4310 /* In case tunnel exist and L4 checksum offload,
4311 * the pseudo checksum location, on packet or on BD.
4313 enum eth_tunnel_non_lso_csum_location {
4316 MAX_ETH_TUNNEL_NON_LSO_CSUM_LOCATION
4319 enum eth_tunn_type {
4325 TUNN_TYPE_L2_GENEVE,
4326 TUNN_TYPE_IPV4_GENEVE,
4327 TUNN_TYPE_IPV6_GENEVE,
4332 * Tx regular BD structure
4337 __le16 total_pkt_bytes;
4344 * structure for easy accessibility to assembler
4346 struct eth_tx_bd_flags {
4348 #define ETH_TX_BD_FLAGS_IP_CSUM (0x1<<0)
4349 #define ETH_TX_BD_FLAGS_IP_CSUM_SHIFT 0
4350 #define ETH_TX_BD_FLAGS_L4_CSUM (0x1<<1)
4351 #define ETH_TX_BD_FLAGS_L4_CSUM_SHIFT 1
4352 #define ETH_TX_BD_FLAGS_VLAN_MODE (0x3<<2)
4353 #define ETH_TX_BD_FLAGS_VLAN_MODE_SHIFT 2
4354 #define ETH_TX_BD_FLAGS_START_BD (0x1<<4)
4355 #define ETH_TX_BD_FLAGS_START_BD_SHIFT 4
4356 #define ETH_TX_BD_FLAGS_IS_UDP (0x1<<5)
4357 #define ETH_TX_BD_FLAGS_IS_UDP_SHIFT 5
4358 #define ETH_TX_BD_FLAGS_SW_LSO (0x1<<6)
4359 #define ETH_TX_BD_FLAGS_SW_LSO_SHIFT 6
4360 #define ETH_TX_BD_FLAGS_IPV6 (0x1<<7)
4361 #define ETH_TX_BD_FLAGS_IPV6_SHIFT 7
4365 * The eth Tx Buffer Descriptor
4367 struct eth_tx_start_bd {
4372 __le16 vlan_or_ethertype;
4373 struct eth_tx_bd_flags bd_flags;
4375 #define ETH_TX_START_BD_HDR_NBDS (0x7<<0)
4376 #define ETH_TX_START_BD_HDR_NBDS_SHIFT 0
4377 #define ETH_TX_START_BD_NO_ADDED_TAGS (0x1<<3)
4378 #define ETH_TX_START_BD_NO_ADDED_TAGS_SHIFT 3
4379 #define ETH_TX_START_BD_FORCE_VLAN_MODE (0x1<<4)
4380 #define ETH_TX_START_BD_FORCE_VLAN_MODE_SHIFT 4
4381 #define ETH_TX_START_BD_PARSE_NBDS (0x3<<5)
4382 #define ETH_TX_START_BD_PARSE_NBDS_SHIFT 5
4383 #define ETH_TX_START_BD_TUNNEL_EXIST (0x1<<7)
4384 #define ETH_TX_START_BD_TUNNEL_EXIST_SHIFT 7
4388 * Tx parsing BD structure for ETH E1/E1h
4390 struct eth_tx_parse_bd_e1x {
4392 #define ETH_TX_PARSE_BD_E1X_IP_HDR_START_OFFSET_W (0xF<<0)
4393 #define ETH_TX_PARSE_BD_E1X_IP_HDR_START_OFFSET_W_SHIFT 0
4394 #define ETH_TX_PARSE_BD_E1X_ETH_ADDR_TYPE (0x3<<4)
4395 #define ETH_TX_PARSE_BD_E1X_ETH_ADDR_TYPE_SHIFT 4
4396 #define ETH_TX_PARSE_BD_E1X_PSEUDO_CS_WITHOUT_LEN (0x1<<6)
4397 #define ETH_TX_PARSE_BD_E1X_PSEUDO_CS_WITHOUT_LEN_SHIFT 6
4398 #define ETH_TX_PARSE_BD_E1X_LLC_SNAP_EN (0x1<<7)
4399 #define ETH_TX_PARSE_BD_E1X_LLC_SNAP_EN_SHIFT 7
4400 #define ETH_TX_PARSE_BD_E1X_NS_FLG (0x1<<8)
4401 #define ETH_TX_PARSE_BD_E1X_NS_FLG_SHIFT 8
4402 #define ETH_TX_PARSE_BD_E1X_RESERVED0 (0x7F<<9)
4403 #define ETH_TX_PARSE_BD_E1X_RESERVED0_SHIFT 9
4405 #define ETH_TX_PARSE_BD_E1X_FIN_FLG (0x1<<0)
4406 #define ETH_TX_PARSE_BD_E1X_FIN_FLG_SHIFT 0
4407 #define ETH_TX_PARSE_BD_E1X_SYN_FLG (0x1<<1)
4408 #define ETH_TX_PARSE_BD_E1X_SYN_FLG_SHIFT 1
4409 #define ETH_TX_PARSE_BD_E1X_RST_FLG (0x1<<2)
4410 #define ETH_TX_PARSE_BD_E1X_RST_FLG_SHIFT 2
4411 #define ETH_TX_PARSE_BD_E1X_PSH_FLG (0x1<<3)
4412 #define ETH_TX_PARSE_BD_E1X_PSH_FLG_SHIFT 3
4413 #define ETH_TX_PARSE_BD_E1X_ACK_FLG (0x1<<4)
4414 #define ETH_TX_PARSE_BD_E1X_ACK_FLG_SHIFT 4
4415 #define ETH_TX_PARSE_BD_E1X_URG_FLG (0x1<<5)
4416 #define ETH_TX_PARSE_BD_E1X_URG_FLG_SHIFT 5
4417 #define ETH_TX_PARSE_BD_E1X_ECE_FLG (0x1<<6)
4418 #define ETH_TX_PARSE_BD_E1X_ECE_FLG_SHIFT 6
4419 #define ETH_TX_PARSE_BD_E1X_CWR_FLG (0x1<<7)
4420 #define ETH_TX_PARSE_BD_E1X_CWR_FLG_SHIFT 7
4422 __le16 total_hlen_w;
4423 __le16 tcp_pseudo_csum;
4426 __le32 tcp_send_seq;
4430 * Tx parsing BD structure for ETH E2
4432 struct eth_tx_parse_bd_e2 {
4433 union eth_mac_addr_or_tunnel_data data;
4434 __le32 parsing_data;
4435 #define ETH_TX_PARSE_BD_E2_L4_HDR_START_OFFSET_W (0x7FF<<0)
4436 #define ETH_TX_PARSE_BD_E2_L4_HDR_START_OFFSET_W_SHIFT 0
4437 #define ETH_TX_PARSE_BD_E2_TCP_HDR_LENGTH_DW (0xF<<11)
4438 #define ETH_TX_PARSE_BD_E2_TCP_HDR_LENGTH_DW_SHIFT 11
4439 #define ETH_TX_PARSE_BD_E2_IPV6_WITH_EXT_HDR (0x1<<15)
4440 #define ETH_TX_PARSE_BD_E2_IPV6_WITH_EXT_HDR_SHIFT 15
4441 #define ETH_TX_PARSE_BD_E2_LSO_MSS (0x3FFF<<16)
4442 #define ETH_TX_PARSE_BD_E2_LSO_MSS_SHIFT 16
4443 #define ETH_TX_PARSE_BD_E2_ETH_ADDR_TYPE (0x3<<30)
4444 #define ETH_TX_PARSE_BD_E2_ETH_ADDR_TYPE_SHIFT 30
4448 * Tx 2nd parsing BD structure for ETH packet
4450 struct eth_tx_parse_2nd_bd {
4452 #define ETH_TX_PARSE_2ND_BD_IP_HDR_START_OUTER_W (0xF<<0)
4453 #define ETH_TX_PARSE_2ND_BD_IP_HDR_START_OUTER_W_SHIFT 0
4454 #define ETH_TX_PARSE_2ND_BD_RESERVED0 (0x1<<4)
4455 #define ETH_TX_PARSE_2ND_BD_RESERVED0_SHIFT 4
4456 #define ETH_TX_PARSE_2ND_BD_LLC_SNAP_EN (0x1<<5)
4457 #define ETH_TX_PARSE_2ND_BD_LLC_SNAP_EN_SHIFT 5
4458 #define ETH_TX_PARSE_2ND_BD_NS_FLG (0x1<<6)
4459 #define ETH_TX_PARSE_2ND_BD_NS_FLG_SHIFT 6
4460 #define ETH_TX_PARSE_2ND_BD_TUNNEL_UDP_EXIST (0x1<<7)
4461 #define ETH_TX_PARSE_2ND_BD_TUNNEL_UDP_EXIST_SHIFT 7
4462 #define ETH_TX_PARSE_2ND_BD_IP_HDR_LEN_OUTER_W (0x1F<<8)
4463 #define ETH_TX_PARSE_2ND_BD_IP_HDR_LEN_OUTER_W_SHIFT 8
4464 #define ETH_TX_PARSE_2ND_BD_RESERVED1 (0x7<<13)
4465 #define ETH_TX_PARSE_2ND_BD_RESERVED1_SHIFT 13
4467 #define ETH_TX_PARSE_2ND_BD_TYPE (0xF<<0)
4468 #define ETH_TX_PARSE_2ND_BD_TYPE_SHIFT 0
4469 #define ETH_TX_PARSE_2ND_BD_RESERVED2 (0xF<<4)
4470 #define ETH_TX_PARSE_2ND_BD_RESERVED2_SHIFT 4
4473 #define ETH_TX_PARSE_2ND_BD_FIN_FLG (0x1<<0)
4474 #define ETH_TX_PARSE_2ND_BD_FIN_FLG_SHIFT 0
4475 #define ETH_TX_PARSE_2ND_BD_SYN_FLG (0x1<<1)
4476 #define ETH_TX_PARSE_2ND_BD_SYN_FLG_SHIFT 1
4477 #define ETH_TX_PARSE_2ND_BD_RST_FLG (0x1<<2)
4478 #define ETH_TX_PARSE_2ND_BD_RST_FLG_SHIFT 2
4479 #define ETH_TX_PARSE_2ND_BD_PSH_FLG (0x1<<3)
4480 #define ETH_TX_PARSE_2ND_BD_PSH_FLG_SHIFT 3
4481 #define ETH_TX_PARSE_2ND_BD_ACK_FLG (0x1<<4)
4482 #define ETH_TX_PARSE_2ND_BD_ACK_FLG_SHIFT 4
4483 #define ETH_TX_PARSE_2ND_BD_URG_FLG (0x1<<5)
4484 #define ETH_TX_PARSE_2ND_BD_URG_FLG_SHIFT 5
4485 #define ETH_TX_PARSE_2ND_BD_ECE_FLG (0x1<<6)
4486 #define ETH_TX_PARSE_2ND_BD_ECE_FLG_SHIFT 6
4487 #define ETH_TX_PARSE_2ND_BD_CWR_FLG (0x1<<7)
4488 #define ETH_TX_PARSE_2ND_BD_CWR_FLG_SHIFT 7
4490 u8 tunnel_udp_hdr_start_w;
4491 u8 fw_ip_hdr_to_payload_w;
4492 __le16 fw_ip_csum_wo_len_flags_frag;
4494 __le32 tcp_send_seq;
4497 /* The last BD in the BD memory will hold a pointer to the next BD memory */
4498 struct eth_tx_next_bd {
4505 * union for 4 Bd types
4507 union eth_tx_bd_types {
4508 struct eth_tx_start_bd start_bd;
4509 struct eth_tx_bd reg_bd;
4510 struct eth_tx_parse_bd_e1x parse_bd_e1x;
4511 struct eth_tx_parse_bd_e2 parse_bd_e2;
4512 struct eth_tx_parse_2nd_bd parse_2nd_bd;
4513 struct eth_tx_next_bd next_bd;
4517 * array of 13 bds as appears in the eth xstorm context
4519 struct eth_tx_bds_array {
4520 union eth_tx_bd_types bds[13];
4525 * VLAN mode on TX BDs
4527 enum eth_tx_vlan_type {
4531 X_ETH_FW_ADDED_VLAN,
4532 MAX_ETH_TX_VLAN_TYPE
4537 * Ethernet VLAN filtering mode in E1x
4539 enum eth_vlan_filter_mode {
4540 ETH_VLAN_FILTER_ANY_VLAN,
4541 ETH_VLAN_FILTER_SPECIFIC_VLAN,
4542 ETH_VLAN_FILTER_CLASSIFY,
4543 MAX_ETH_VLAN_FILTER_MODE
4548 * MAC filtering configuration command header
4550 struct mac_configuration_hdr {
4558 * MAC address in list for ramrod
4560 struct mac_configuration_entry {
4561 __le16 lsb_mac_addr;
4562 __le16 middle_mac_addr;
4563 __le16 msb_mac_addr;
4567 #define MAC_CONFIGURATION_ENTRY_ACTION_TYPE (0x1<<0)
4568 #define MAC_CONFIGURATION_ENTRY_ACTION_TYPE_SHIFT 0
4569 #define MAC_CONFIGURATION_ENTRY_RDMA_MAC (0x1<<1)
4570 #define MAC_CONFIGURATION_ENTRY_RDMA_MAC_SHIFT 1
4571 #define MAC_CONFIGURATION_ENTRY_VLAN_FILTERING_MODE (0x3<<2)
4572 #define MAC_CONFIGURATION_ENTRY_VLAN_FILTERING_MODE_SHIFT 2
4573 #define MAC_CONFIGURATION_ENTRY_OVERRIDE_VLAN_REMOVAL (0x1<<4)
4574 #define MAC_CONFIGURATION_ENTRY_OVERRIDE_VLAN_REMOVAL_SHIFT 4
4575 #define MAC_CONFIGURATION_ENTRY_BROADCAST (0x1<<5)
4576 #define MAC_CONFIGURATION_ENTRY_BROADCAST_SHIFT 5
4577 #define MAC_CONFIGURATION_ENTRY_RESERVED1 (0x3<<6)
4578 #define MAC_CONFIGURATION_ENTRY_RESERVED1_SHIFT 6
4580 __le32 clients_bit_vector;
4584 * MAC filtering configuration command
4586 struct mac_configuration_cmd {
4587 struct mac_configuration_hdr hdr;
4588 struct mac_configuration_entry config_table[64];
4593 * Set-MAC command type (in E1x)
4595 enum set_mac_action_type {
4596 T_ETH_MAC_COMMAND_INVALIDATE,
4597 T_ETH_MAC_COMMAND_SET,
4598 MAX_SET_MAC_ACTION_TYPE
4603 * Ethernet TPA Modes
4612 * tpa update ramrod data
4614 struct tpa_update_ramrod_data {
4619 u8 max_sges_for_packet;
4620 u8 complete_on_both_clients;
4621 u8 dont_verify_rings_pause_thr_flg;
4623 __le16 sge_buff_size;
4624 __le16 max_agg_size;
4625 __le32 sge_page_base_lo;
4626 __le32 sge_page_base_hi;
4627 __le16 sge_pause_thr_low;
4628 __le16 sge_pause_thr_high;
4633 * approximate-match multicast filtering for E1H per function in Tstorm
4635 struct tstorm_eth_approximate_match_multicast_filtering {
4636 u32 mcast_add_hash_bit_array[8];
4641 * Common configuration parameters per function in Tstorm
4643 struct tstorm_eth_function_common_config {
4644 __le16 config_flags;
4645 #define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV4_CAPABILITY (0x1<<0)
4646 #define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV4_CAPABILITY_SHIFT 0
4647 #define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV4_TCP_CAPABILITY (0x1<<1)
4648 #define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV4_TCP_CAPABILITY_SHIFT 1
4649 #define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV6_CAPABILITY (0x1<<2)
4650 #define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV6_CAPABILITY_SHIFT 2
4651 #define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV6_TCP_CAPABILITY (0x1<<3)
4652 #define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV6_TCP_CAPABILITY_SHIFT 3
4653 #define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_MODE (0x7<<4)
4654 #define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_MODE_SHIFT 4
4655 #define TSTORM_ETH_FUNCTION_COMMON_CONFIG_VLAN_FILTERING_ENABLE (0x1<<7)
4656 #define TSTORM_ETH_FUNCTION_COMMON_CONFIG_VLAN_FILTERING_ENABLE_SHIFT 7
4657 #define __TSTORM_ETH_FUNCTION_COMMON_CONFIG_RESERVED0 (0xFF<<8)
4658 #define __TSTORM_ETH_FUNCTION_COMMON_CONFIG_RESERVED0_SHIFT 8
4666 * MAC filtering configuration parameters per port in Tstorm
4668 struct tstorm_eth_mac_filter_config {
4670 u32 ucast_accept_all;
4672 u32 mcast_accept_all;
4673 u32 bcast_accept_all;
4675 u32 unmatched_unicast;
4680 * tx only queue init ramrod data
4682 struct tx_queue_init_ramrod_data {
4683 struct client_init_general_data general;
4684 struct client_init_tx_data tx;
4689 * Three RX producers for ETH
4691 struct ustorm_eth_rx_producers {
4692 #if defined(__BIG_ENDIAN)
4695 #elif defined(__LITTLE_ENDIAN)
4699 #if defined(__BIG_ENDIAN)
4702 #elif defined(__LITTLE_ENDIAN)
4710 * FCoE RX statistics parameters section#0
4712 struct fcoe_rx_stat_params_section0 {
4713 __le32 fcoe_rx_pkt_cnt;
4714 __le32 fcoe_rx_byte_cnt;
4719 * FCoE RX statistics parameters section#1
4721 struct fcoe_rx_stat_params_section1 {
4722 __le32 fcoe_ver_cnt;
4723 __le32 fcoe_rx_drop_pkt_cnt;
4728 * FCoE RX statistics parameters section#2
4730 struct fcoe_rx_stat_params_section2 {
4732 __le32 eofa_del_cnt;
4733 __le32 miss_frame_cnt;
4734 __le32 seq_timeout_cnt;
4735 __le32 drop_seq_cnt;
4736 __le32 fcoe_rx_drop_pkt_cnt;
4737 __le32 fcp_rx_pkt_cnt;
4743 * FCoE TX statistics parameters
4745 struct fcoe_tx_stat_params {
4746 __le32 fcoe_tx_pkt_cnt;
4747 __le32 fcoe_tx_byte_cnt;
4748 __le32 fcp_tx_pkt_cnt;
4753 * FCoE statistics parameters
4755 struct fcoe_statistics_params {
4756 struct fcoe_tx_stat_params tx_stat;
4757 struct fcoe_rx_stat_params_section0 rx_stat0;
4758 struct fcoe_rx_stat_params_section1 rx_stat1;
4759 struct fcoe_rx_stat_params_section2 rx_stat2;
4764 * The data afex vif list ramrod need
4766 struct afex_vif_list_ramrod_data {
4767 u8 afex_vif_list_command;
4769 __le16 vif_list_index;
4775 struct c2s_pri_trans_table_entry {
4776 u8 val[MAX_VLAN_PRIORITIES];
4780 * cfc delete event data
4782 struct cfc_del_event_data {
4790 * per-port SAFC demo variables
4792 struct cmng_flags_per_port {
4794 #define CMNG_FLAGS_PER_PORT_FAIRNESS_VN (0x1<<0)
4795 #define CMNG_FLAGS_PER_PORT_FAIRNESS_VN_SHIFT 0
4796 #define CMNG_FLAGS_PER_PORT_RATE_SHAPING_VN (0x1<<1)
4797 #define CMNG_FLAGS_PER_PORT_RATE_SHAPING_VN_SHIFT 1
4798 #define CMNG_FLAGS_PER_PORT_FAIRNESS_COS (0x1<<2)
4799 #define CMNG_FLAGS_PER_PORT_FAIRNESS_COS_SHIFT 2
4800 #define CMNG_FLAGS_PER_PORT_FAIRNESS_COS_MODE (0x1<<3)
4801 #define CMNG_FLAGS_PER_PORT_FAIRNESS_COS_MODE_SHIFT 3
4802 #define __CMNG_FLAGS_PER_PORT_RESERVED0 (0xFFFFFFF<<4)
4803 #define __CMNG_FLAGS_PER_PORT_RESERVED0_SHIFT 4
4809 * per-port rate shaping variables
4811 struct rate_shaping_vars_per_port {
4812 u32 rs_periodic_timeout;
4817 * per-port fairness variables
4819 struct fairness_vars_per_port {
4822 u32 fairness_timeout;
4827 * per-port SAFC variables
4829 struct safc_struct_per_port {
4830 #if defined(__BIG_ENDIAN)
4833 u8 safc_timeout_usec;
4834 #elif defined(__LITTLE_ENDIAN)
4835 u8 safc_timeout_usec;
4839 u8 cos_to_traffic_types[MAX_COS_NUMBER];
4840 u16 cos_to_pause_mask[NUM_OF_SAFC_BITS];
4844 * Per-port congestion management variables
4846 struct cmng_struct_per_port {
4847 struct rate_shaping_vars_per_port rs_vars;
4848 struct fairness_vars_per_port fair_vars;
4849 struct safc_struct_per_port safc_vars;
4850 struct cmng_flags_per_port flags;
4854 * a single rate shaping counter. can be used as protocol or vnic counter
4856 struct rate_shaping_counter {
4858 #if defined(__BIG_ENDIAN)
4861 #elif defined(__LITTLE_ENDIAN)
4868 * per-vnic rate shaping variables
4870 struct rate_shaping_vars_per_vn {
4871 struct rate_shaping_counter vn_counter;
4875 * per-vnic fairness variables
4877 struct fairness_vars_per_vn {
4878 u32 cos_credit_delta[MAX_COS_NUMBER];
4879 u32 vn_credit_delta;
4884 * cmng port init state
4887 struct rate_shaping_vars_per_vn vnic_max_rate[4];
4888 struct fairness_vars_per_vn vnic_min_rate[4];
4892 * cmng port init state
4895 struct cmng_struct_per_port port;
4896 struct cmng_vnic vnic;
4901 * driver parameters for congestion management init, all rates are in Mbps
4903 struct cmng_init_input {
4905 u16 vnic_min_rate[4];
4906 u16 vnic_max_rate[4];
4907 u16 cos_min_rate[MAX_COS_NUMBER];
4908 u16 cos_to_pause_mask[MAX_COS_NUMBER];
4909 struct cmng_flags_per_port flags;
4914 * Protocol-common command ID for slow path elements
4916 enum common_spqe_cmd_id {
4917 RAMROD_CMD_ID_COMMON_UNUSED,
4918 RAMROD_CMD_ID_COMMON_FUNCTION_START,
4919 RAMROD_CMD_ID_COMMON_FUNCTION_STOP,
4920 RAMROD_CMD_ID_COMMON_FUNCTION_UPDATE,
4921 RAMROD_CMD_ID_COMMON_CFC_DEL,
4922 RAMROD_CMD_ID_COMMON_CFC_DEL_WB,
4923 RAMROD_CMD_ID_COMMON_STAT_QUERY,
4924 RAMROD_CMD_ID_COMMON_STOP_TRAFFIC,
4925 RAMROD_CMD_ID_COMMON_START_TRAFFIC,
4926 RAMROD_CMD_ID_COMMON_AFEX_VIF_LISTS,
4927 RAMROD_CMD_ID_COMMON_SET_TIMESYNC,
4928 MAX_COMMON_SPQE_CMD_ID
4932 * Per-protocol connection types
4934 enum connection_type {
4935 ETH_CONNECTION_TYPE,
4936 TOE_CONNECTION_TYPE,
4937 RDMA_CONNECTION_TYPE,
4938 ISCSI_CONNECTION_TYPE,
4939 FCOE_CONNECTION_TYPE,
4940 RESERVED_CONNECTION_TYPE_0,
4941 RESERVED_CONNECTION_TYPE_1,
4942 RESERVED_CONNECTION_TYPE_2,
4943 NONE_CONNECTION_TYPE,
4960 * Dynamic HC counters set by the driver
4962 struct hc_dynamic_drv_counter {
4963 u32 val[HC_SB_MAX_DYNAMIC_INDICES];
4967 * zone A per-queue data
4969 struct cstorm_queue_zone_data {
4970 struct hc_dynamic_drv_counter hc_dyn_drv_cnt;
4971 struct regpair reserved[2];
4976 * Vf-PF channel data in cstorm ram (non-triggered zone)
4978 struct vf_pf_channel_zone_data {
4984 * zone for VF non-triggered data
4986 struct non_trigger_vf_zone {
4987 struct vf_pf_channel_zone_data vf_pf_channel;
4991 * Vf-PF channel trigger zone in cstorm ram
4993 struct vf_pf_channel_zone_trigger {
4998 * zone that triggers the in-bound interrupt
5000 struct trigger_vf_zone {
5001 #if defined(__BIG_ENDIAN)
5004 struct vf_pf_channel_zone_trigger vf_pf_channel;
5005 #elif defined(__LITTLE_ENDIAN)
5006 struct vf_pf_channel_zone_trigger vf_pf_channel;
5014 * zone B per-VF data
5016 struct cstorm_vf_zone_data {
5017 struct non_trigger_vf_zone non_trigger;
5018 struct trigger_vf_zone trigger;
5023 * Dynamic host coalescing init parameters, per state machine
5025 struct dynamic_hc_sm_config {
5027 u8 shift_per_protocol[HC_SB_MAX_DYNAMIC_INDICES];
5028 u8 hc_timeout0[HC_SB_MAX_DYNAMIC_INDICES];
5029 u8 hc_timeout1[HC_SB_MAX_DYNAMIC_INDICES];
5030 u8 hc_timeout2[HC_SB_MAX_DYNAMIC_INDICES];
5031 u8 hc_timeout3[HC_SB_MAX_DYNAMIC_INDICES];
5035 * Dynamic host coalescing init parameters
5037 struct dynamic_hc_config {
5038 struct dynamic_hc_sm_config sm_config[HC_SB_MAX_SM];
5042 struct e2_integ_data {
5043 #if defined(__BIG_ENDIAN)
5045 #define E2_INTEG_DATA_TESTING_EN (0x1<<0)
5046 #define E2_INTEG_DATA_TESTING_EN_SHIFT 0
5047 #define E2_INTEG_DATA_LB_TX (0x1<<1)
5048 #define E2_INTEG_DATA_LB_TX_SHIFT 1
5049 #define E2_INTEG_DATA_COS_TX (0x1<<2)
5050 #define E2_INTEG_DATA_COS_TX_SHIFT 2
5051 #define E2_INTEG_DATA_OPPORTUNISTICQM (0x1<<3)
5052 #define E2_INTEG_DATA_OPPORTUNISTICQM_SHIFT 3
5053 #define E2_INTEG_DATA_DPMTESTRELEASEDQ (0x1<<4)
5054 #define E2_INTEG_DATA_DPMTESTRELEASEDQ_SHIFT 4
5055 #define E2_INTEG_DATA_RESERVED (0x7<<5)
5056 #define E2_INTEG_DATA_RESERVED_SHIFT 5
5060 #elif defined(__LITTLE_ENDIAN)
5065 #define E2_INTEG_DATA_TESTING_EN (0x1<<0)
5066 #define E2_INTEG_DATA_TESTING_EN_SHIFT 0
5067 #define E2_INTEG_DATA_LB_TX (0x1<<1)
5068 #define E2_INTEG_DATA_LB_TX_SHIFT 1
5069 #define E2_INTEG_DATA_COS_TX (0x1<<2)
5070 #define E2_INTEG_DATA_COS_TX_SHIFT 2
5071 #define E2_INTEG_DATA_OPPORTUNISTICQM (0x1<<3)
5072 #define E2_INTEG_DATA_OPPORTUNISTICQM_SHIFT 3
5073 #define E2_INTEG_DATA_DPMTESTRELEASEDQ (0x1<<4)
5074 #define E2_INTEG_DATA_DPMTESTRELEASEDQ_SHIFT 4
5075 #define E2_INTEG_DATA_RESERVED (0x7<<5)
5076 #define E2_INTEG_DATA_RESERVED_SHIFT 5
5078 #if defined(__BIG_ENDIAN)
5082 #elif defined(__LITTLE_ENDIAN)
5091 * set mac event data
5093 struct eth_event_data {
5103 struct vf_pf_event_data {
5114 struct vf_flr_event_data {
5123 * malicious VF event data
5125 struct malicious_vf_event_data {
5134 * vif list event data
5136 struct vif_list_event_data {
5144 /* function update event data */
5145 struct function_update_event_data {
5154 /* union for all event ring message types */
5156 struct vf_pf_event_data vf_pf_event;
5157 struct eth_event_data eth_event;
5158 struct cfc_del_event_data cfc_del_event;
5159 struct vf_flr_event_data vf_flr_event;
5160 struct malicious_vf_event_data malicious_vf_event;
5161 struct vif_list_event_data vif_list_event;
5162 struct function_update_event_data function_update_event;
5167 * per PF event ring data
5169 struct event_ring_data {
5170 struct regpair_native base_addr;
5171 #if defined(__BIG_ENDIAN)
5175 #elif defined(__LITTLE_ENDIAN)
5185 * event ring message element (each element is 128 bits)
5187 struct event_ring_msg {
5191 union event_data data;
5195 * event ring next page element (128 bits)
5197 struct event_ring_next {
5198 struct regpair addr;
5203 * union for event ring element types (each element is 128 bits)
5205 union event_ring_elem {
5206 struct event_ring_msg message;
5207 struct event_ring_next next_page;
5212 * Common event ring opcodes
5214 enum event_ring_opcode {
5215 EVENT_RING_OPCODE_VF_PF_CHANNEL,
5216 EVENT_RING_OPCODE_FUNCTION_START,
5217 EVENT_RING_OPCODE_FUNCTION_STOP,
5218 EVENT_RING_OPCODE_CFC_DEL,
5219 EVENT_RING_OPCODE_CFC_DEL_WB,
5220 EVENT_RING_OPCODE_STAT_QUERY,
5221 EVENT_RING_OPCODE_STOP_TRAFFIC,
5222 EVENT_RING_OPCODE_START_TRAFFIC,
5223 EVENT_RING_OPCODE_VF_FLR,
5224 EVENT_RING_OPCODE_MALICIOUS_VF,
5225 EVENT_RING_OPCODE_FORWARD_SETUP,
5226 EVENT_RING_OPCODE_RSS_UPDATE_RULES,
5227 EVENT_RING_OPCODE_FUNCTION_UPDATE,
5228 EVENT_RING_OPCODE_AFEX_VIF_LISTS,
5229 EVENT_RING_OPCODE_SET_MAC,
5230 EVENT_RING_OPCODE_CLASSIFICATION_RULES,
5231 EVENT_RING_OPCODE_FILTERS_RULES,
5232 EVENT_RING_OPCODE_MULTICAST_RULES,
5233 EVENT_RING_OPCODE_SET_TIMESYNC,
5234 MAX_EVENT_RING_OPCODE
5238 * Modes for fairness algorithm
5240 enum fairness_mode {
5241 FAIRNESS_COS_WRR_MODE,
5242 FAIRNESS_COS_ETS_MODE,
5250 struct priority_cos {
5257 * The data for flow control configuration
5259 struct flow_control_configuration {
5260 struct priority_cos traffic_type_to_priority_cos[MAX_TRAFFIC_TYPES];
5263 u8 dont_add_pri_0_en;
5266 u8 dcb_outer_pri[MAX_TRAFFIC_TYPES];
5273 struct function_start_data {
5275 u8 allow_npar_tx_switching;
5279 u8 network_cos_mode;
5284 u8 inner_clss_vxlan;
5285 u8 inner_clss_l2gre;
5286 u8 inner_clss_l2geneve;
5288 __le16 vxlan_dst_port;
5289 __le16 geneve_dst_port;
5290 u8 sd_accept_mf_clss_fail;
5291 u8 sd_accept_mf_clss_fail_match_ethtype;
5292 __le16 sd_accept_mf_clss_fail_ethtype;
5293 __le16 sd_vlan_eth_type;
5294 u8 sd_vlan_force_pri_flg;
5295 u8 sd_vlan_force_pri_val;
5296 u8 c2s_pri_tt_valid;
5299 struct c2s_pri_trans_table_entry c2s_pri_trans_table;
5302 struct function_update_data {
5303 u8 vif_id_change_flg;
5304 u8 afex_default_vlan_change_flg;
5305 u8 allowed_priorities_change_flg;
5306 u8 network_cos_mode_change_flg;
5308 __le16 afex_default_vlan;
5309 u8 allowed_priorities;
5310 u8 network_cos_mode;
5311 u8 lb_mode_en_change_flg;
5313 u8 tx_switch_suspend_change_flg;
5314 u8 tx_switch_suspend;
5316 u8 update_tunn_cfg_flg;
5317 u8 inner_clss_vxlan;
5318 u8 inner_clss_l2gre;
5319 u8 inner_clss_l2geneve;
5321 __le16 vxlan_dst_port;
5322 __le16 geneve_dst_port;
5323 u8 sd_vlan_force_pri_change_flg;
5324 u8 sd_vlan_force_pri_flg;
5325 u8 sd_vlan_force_pri_val;
5326 u8 sd_vlan_tag_change_flg;
5327 u8 sd_vlan_eth_type_change_flg;
5330 __le16 sd_vlan_eth_type;
5336 * FW version stored in the Xstorm RAM
5339 #if defined(__BIG_ENDIAN)
5344 #elif defined(__LITTLE_ENDIAN)
5351 #define FW_VERSION_OPTIMIZED (0x1<<0)
5352 #define FW_VERSION_OPTIMIZED_SHIFT 0
5353 #define FW_VERSION_BIG_ENDIEN (0x1<<1)
5354 #define FW_VERSION_BIG_ENDIEN_SHIFT 1
5355 #define FW_VERSION_CHIP_VERSION (0x3<<2)
5356 #define FW_VERSION_CHIP_VERSION_SHIFT 2
5357 #define __FW_VERSION_RESERVED (0xFFFFFFF<<4)
5358 #define __FW_VERSION_RESERVED_SHIFT 4
5362 * Dynamic Host-Coalescing - Driver(host) counters
5364 struct hc_dynamic_sb_drv_counters {
5365 u32 dynamic_hc_drv_counter[HC_SB_MAX_DYNAMIC_INDICES];
5370 * 2 bytes. configuration/state parameters for a single protocol index
5372 struct hc_index_data {
5373 #if defined(__BIG_ENDIAN)
5375 #define HC_INDEX_DATA_SM_ID (0x1<<0)
5376 #define HC_INDEX_DATA_SM_ID_SHIFT 0
5377 #define HC_INDEX_DATA_HC_ENABLED (0x1<<1)
5378 #define HC_INDEX_DATA_HC_ENABLED_SHIFT 1
5379 #define HC_INDEX_DATA_DYNAMIC_HC_ENABLED (0x1<<2)
5380 #define HC_INDEX_DATA_DYNAMIC_HC_ENABLED_SHIFT 2
5381 #define HC_INDEX_DATA_RESERVE (0x1F<<3)
5382 #define HC_INDEX_DATA_RESERVE_SHIFT 3
5384 #elif defined(__LITTLE_ENDIAN)
5387 #define HC_INDEX_DATA_SM_ID (0x1<<0)
5388 #define HC_INDEX_DATA_SM_ID_SHIFT 0
5389 #define HC_INDEX_DATA_HC_ENABLED (0x1<<1)
5390 #define HC_INDEX_DATA_HC_ENABLED_SHIFT 1
5391 #define HC_INDEX_DATA_DYNAMIC_HC_ENABLED (0x1<<2)
5392 #define HC_INDEX_DATA_DYNAMIC_HC_ENABLED_SHIFT 2
5393 #define HC_INDEX_DATA_RESERVE (0x1F<<3)
5394 #define HC_INDEX_DATA_RESERVE_SHIFT 3
5402 struct hc_status_block_sm {
5403 #if defined(__BIG_ENDIAN)
5408 #elif defined(__LITTLE_ENDIAN)
5418 * hold PCI identification variables- used in various places in firmware
5421 #if defined(__BIG_ENDIAN)
5426 #elif defined(__LITTLE_ENDIAN)
5435 * The fast-path status block meta-data, common to all chips
5438 struct regpair_native host_sb_addr;
5439 struct hc_status_block_sm state_machine[HC_SB_MAX_SM];
5440 struct pci_entity p_func;
5441 #if defined(__BIG_ENDIAN)
5446 #elif defined(__LITTLE_ENDIAN)
5452 struct regpair_native rsrv1[2];
5457 * Segment types for host coaslescing
5467 * The fast-path status block meta-data
5469 struct hc_sp_status_block_data {
5470 struct regpair_native host_sb_addr;
5471 #if defined(__BIG_ENDIAN)
5476 #elif defined(__LITTLE_ENDIAN)
5482 struct pci_entity p_func;
5487 * The fast-path status block meta-data
5489 struct hc_status_block_data_e1x {
5490 struct hc_index_data index_data[HC_SB_MAX_INDICES_E1X];
5491 struct hc_sb_data common;
5496 * The fast-path status block meta-data
5498 struct hc_status_block_data_e2 {
5499 struct hc_index_data index_data[HC_SB_MAX_INDICES_E2];
5500 struct hc_sb_data common;
5505 * IGU block operartion modes (in Everest2)
5524 * Malicious VF error ID
5526 enum malicious_vf_error_id {
5527 MALICIOUS_VF_NO_ERROR,
5528 VF_PF_CHANNEL_NOT_READY,
5529 ETH_ILLEGAL_BD_LENGTHS,
5530 ETH_PACKET_TOO_SHORT,
5531 ETH_PAYLOAD_TOO_BIG,
5532 ETH_ILLEGAL_ETH_TYPE,
5533 ETH_ILLEGAL_LSO_HDR_LEN,
5536 ETH_START_BD_NOT_SET,
5537 ETH_ILLEGAL_PARSE_NBDS,
5538 ETH_IPV6_AND_CHECKSUM,
5539 ETH_VLAN_FLG_INCORRECT,
5540 ETH_ILLEGAL_LSO_MSS,
5541 ETH_TUNNEL_NOT_SUPPORTED,
5542 MAX_MALICIOUS_VF_ERROR_ID
5546 * Multi-function modes
5552 MULTI_FUNCTION_AFEX,
5557 * Protocol-common statistics collected by the Tstorm (per pf)
5559 struct tstorm_per_pf_stats {
5560 struct regpair rcv_error_bytes;
5566 struct per_pf_stats {
5567 struct tstorm_per_pf_stats tstorm_pf_statistics;
5572 * Protocol-common statistics collected by the Tstorm (per port)
5574 struct tstorm_per_port_stats {
5576 __le32 mac_filter_discard;
5577 __le32 brb_truncate_discard;
5578 __le32 mf_tag_discard;
5586 struct per_port_stats {
5587 struct tstorm_per_port_stats tstorm_port_statistics;
5592 * Protocol-common statistics collected by the Tstorm (per client)
5594 struct tstorm_per_queue_stats {
5595 struct regpair rcv_ucast_bytes;
5596 __le32 rcv_ucast_pkts;
5597 __le32 checksum_discard;
5598 struct regpair rcv_bcast_bytes;
5599 __le32 rcv_bcast_pkts;
5600 __le32 pkts_too_big_discard;
5601 struct regpair rcv_mcast_bytes;
5602 __le32 rcv_mcast_pkts;
5603 __le32 ttl0_discard;
5604 __le16 no_buff_discard;
5610 * Protocol-common statistics collected by the Ustorm (per client)
5612 struct ustorm_per_queue_stats {
5613 struct regpair ucast_no_buff_bytes;
5614 struct regpair mcast_no_buff_bytes;
5615 struct regpair bcast_no_buff_bytes;
5616 __le32 ucast_no_buff_pkts;
5617 __le32 mcast_no_buff_pkts;
5618 __le32 bcast_no_buff_pkts;
5619 __le32 coalesced_pkts;
5620 struct regpair coalesced_bytes;
5621 __le32 coalesced_events;
5622 __le32 coalesced_aborts;
5626 * Protocol-common statistics collected by the Xstorm (per client)
5628 struct xstorm_per_queue_stats {
5629 struct regpair ucast_bytes_sent;
5630 struct regpair mcast_bytes_sent;
5631 struct regpair bcast_bytes_sent;
5632 __le32 ucast_pkts_sent;
5633 __le32 mcast_pkts_sent;
5634 __le32 bcast_pkts_sent;
5635 __le32 error_drop_pkts;
5641 struct per_queue_stats {
5642 struct tstorm_per_queue_stats tstorm_queue_statistics;
5643 struct ustorm_per_queue_stats ustorm_queue_statistics;
5644 struct xstorm_per_queue_stats xstorm_queue_statistics;
5649 * FW version stored in first line of pram
5651 struct pram_fw_version {
5657 #define PRAM_FW_VERSION_OPTIMIZED (0x1<<0)
5658 #define PRAM_FW_VERSION_OPTIMIZED_SHIFT 0
5659 #define PRAM_FW_VERSION_STORM_ID (0x3<<1)
5660 #define PRAM_FW_VERSION_STORM_ID_SHIFT 1
5661 #define PRAM_FW_VERSION_BIG_ENDIEN (0x1<<3)
5662 #define PRAM_FW_VERSION_BIG_ENDIEN_SHIFT 3
5663 #define PRAM_FW_VERSION_CHIP_VERSION (0x3<<4)
5664 #define PRAM_FW_VERSION_CHIP_VERSION_SHIFT 4
5665 #define __PRAM_FW_VERSION_RESERVED0 (0x3<<6)
5666 #define __PRAM_FW_VERSION_RESERVED0_SHIFT 6
5671 * Ethernet slow path element
5673 union protocol_common_specific_data {
5674 u8 protocol_data[8];
5675 struct regpair phy_address;
5676 struct regpair mac_config_addr;
5677 struct afex_vif_list_ramrod_data afex_vif_list_data;
5681 * The send queue element
5683 struct protocol_common_spe {
5685 union protocol_common_specific_data data;
5688 /* The data for the Set Timesync Ramrod */
5689 struct set_timesync_ramrod_data {
5690 u8 drift_adjust_cmd;
5692 u8 add_sub_drift_adjust_value;
5693 u8 drift_adjust_value;
5694 u32 drift_adjust_period;
5695 struct regpair offset_delta;
5699 * The send queue element
5701 struct slow_path_element {
5703 struct regpair protocol_data;
5708 * Protocol-common statistics counter
5710 struct stats_counter {
5711 __le16 xstats_counter;
5714 __le16 tstats_counter;
5717 __le16 ustats_counter;
5720 __le16 cstats_counter;
5729 struct stats_query_entry {
5734 struct regpair address;
5740 struct stats_query_cmd_group {
5741 struct stats_query_entry query[STATS_QUERY_CMD_COUNT];
5746 * statistic command header
5748 struct stats_query_header {
5751 __le16 drv_stats_counter;
5753 struct regpair stats_counters_addrs;
5758 * Types of statistcis query entry
5760 enum stats_query_type {
5766 MAX_STATS_QUERY_TYPE
5771 * Indicate of the function status block state
5773 enum status_block_state {
5777 MAX_STATUS_BLOCK_STATE
5782 * Storm IDs (including attentions for IGU related enums)
5795 * Taffic types used in ETS and flow control algorithms
5798 LLFC_TRAFFIC_TYPE_NW,
5799 LLFC_TRAFFIC_TYPE_FCOE,
5800 LLFC_TRAFFIC_TYPE_ISCSI,
5806 * zone A per-queue data
5808 struct tstorm_queue_zone_data {
5809 struct regpair reserved[4];
5814 * zone B per-VF data
5816 struct tstorm_vf_zone_data {
5817 struct regpair reserved;
5820 /* Add or Subtract Value for Set Timesync Ramrod */
5821 enum ts_add_sub_value {
5824 MAX_TS_ADD_SUB_VALUE
5827 /* Drift-Adjust Commands for Set Timesync Ramrod */
5828 enum ts_drift_adjust_cmd {
5829 TS_DRIFT_ADJUST_KEEP,
5830 TS_DRIFT_ADJUST_SET,
5831 TS_DRIFT_ADJUST_RESET,
5832 MAX_TS_DRIFT_ADJUST_CMD
5835 /* Offset Commands for Set Timesync Ramrod */
5836 enum ts_offset_cmd {
5851 /* zone A per-queue data */
5852 struct ustorm_queue_zone_data {
5853 struct ustorm_eth_rx_producers eth_rx_producers;
5854 struct regpair reserved[3];
5859 * zone B per-VF data
5861 struct ustorm_vf_zone_data {
5862 struct regpair reserved;
5867 * data per VF-PF channel
5869 struct vf_pf_channel_data {
5870 #if defined(__BIG_ENDIAN)
5874 #elif defined(__LITTLE_ENDIAN)
5884 * State of VF-PF channel
5886 enum vf_pf_channel_state {
5887 VF_PF_CHANNEL_STATE_READY,
5888 VF_PF_CHANNEL_STATE_WAITING_FOR_ACK,
5889 MAX_VF_PF_CHANNEL_STATE
5894 * vif_list_rule_kind
5896 enum vif_list_rule_kind {
5899 VIF_LIST_RULE_CLEAR_ALL,
5900 VIF_LIST_RULE_CLEAR_FUNC,
5901 MAX_VIF_LIST_RULE_KIND
5906 * zone A per-queue data
5908 struct xstorm_queue_zone_data {
5909 struct regpair reserved[4];
5914 * zone B per-VF data
5916 struct xstorm_vf_zone_data {
5917 struct regpair reserved;
5920 #endif /* BNX2X_HSI_H */
projects / linux-2.6-microblaze.git / blob