1 /* bnx2x_ethtool.c: QLogic Everest network driver.
3 * Copyright (c) 2007-2013 Broadcom Corporation
4 * Copyright (c) 2014 QLogic Corporation
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation.
11 * Maintained by: Ariel Elior <ariel.elior@qlogic.com>
12 * Written by: Eliezer Tamir
13 * Based on code from Michael Chan's bnx2 driver
14 * UDP CSUM errata workaround by Arik Gendelman
15 * Slowpath and fastpath rework by Vladislav Zolotarov
16 * Statistics and Link management by Yitchak Gertner
20 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
22 #include <linux/ethtool.h>
23 #include <linux/netdevice.h>
24 #include <linux/types.h>
25 #include <linux/sched.h>
26 #include <linux/crc32.h>
28 #include "bnx2x_cmn.h"
29 #include "bnx2x_dump.h"
30 #include "bnx2x_init.h"
32 /* Note: in the format strings below %s is replaced by the queue-name which is
33 * either its index or 'fcoe' for the fcoe queue. Make sure the format string
34 * length does not exceed ETH_GSTRING_LEN - MAX_QUEUE_NAME_LEN + 2
36 #define MAX_QUEUE_NAME_LEN 4
40 char string[ETH_GSTRING_LEN];
41 } bnx2x_q_stats_arr[] = {
42 /* 1 */ { Q_STATS_OFFSET32(total_bytes_received_hi), 8, "[%s]: rx_bytes" },
43 { Q_STATS_OFFSET32(total_unicast_packets_received_hi),
44 8, "[%s]: rx_ucast_packets" },
45 { Q_STATS_OFFSET32(total_multicast_packets_received_hi),
46 8, "[%s]: rx_mcast_packets" },
47 { Q_STATS_OFFSET32(total_broadcast_packets_received_hi),
48 8, "[%s]: rx_bcast_packets" },
49 { Q_STATS_OFFSET32(no_buff_discard_hi), 8, "[%s]: rx_discards" },
50 { Q_STATS_OFFSET32(rx_err_discard_pkt),
51 4, "[%s]: rx_phy_ip_err_discards"},
52 { Q_STATS_OFFSET32(rx_skb_alloc_failed),
53 4, "[%s]: rx_skb_alloc_discard" },
54 { Q_STATS_OFFSET32(hw_csum_err), 4, "[%s]: rx_csum_offload_errors" },
55 { Q_STATS_OFFSET32(driver_xoff), 4, "[%s]: tx_exhaustion_events" },
56 { Q_STATS_OFFSET32(total_bytes_transmitted_hi), 8, "[%s]: tx_bytes" },
57 /* 10 */{ Q_STATS_OFFSET32(total_unicast_packets_transmitted_hi),
58 8, "[%s]: tx_ucast_packets" },
59 { Q_STATS_OFFSET32(total_multicast_packets_transmitted_hi),
60 8, "[%s]: tx_mcast_packets" },
61 { Q_STATS_OFFSET32(total_broadcast_packets_transmitted_hi),
62 8, "[%s]: tx_bcast_packets" },
63 { Q_STATS_OFFSET32(total_tpa_aggregations_hi),
64 8, "[%s]: tpa_aggregations" },
65 { Q_STATS_OFFSET32(total_tpa_aggregated_frames_hi),
66 8, "[%s]: tpa_aggregated_frames"},
67 { Q_STATS_OFFSET32(total_tpa_bytes_hi), 8, "[%s]: tpa_bytes"},
68 { Q_STATS_OFFSET32(driver_filtered_tx_pkt),
69 4, "[%s]: driver_filtered_tx_pkt" }
72 #define BNX2X_NUM_Q_STATS ARRAY_SIZE(bnx2x_q_stats_arr)
78 char string[ETH_GSTRING_LEN];
79 } bnx2x_stats_arr[] = {
80 /* 1 */ { STATS_OFFSET32(total_bytes_received_hi),
81 8, false, "rx_bytes" },
82 { STATS_OFFSET32(error_bytes_received_hi),
83 8, false, "rx_error_bytes" },
84 { STATS_OFFSET32(total_unicast_packets_received_hi),
85 8, false, "rx_ucast_packets" },
86 { STATS_OFFSET32(total_multicast_packets_received_hi),
87 8, false, "rx_mcast_packets" },
88 { STATS_OFFSET32(total_broadcast_packets_received_hi),
89 8, false, "rx_bcast_packets" },
90 { STATS_OFFSET32(rx_stat_dot3statsfcserrors_hi),
91 8, true, "rx_crc_errors" },
92 { STATS_OFFSET32(rx_stat_dot3statsalignmenterrors_hi),
93 8, true, "rx_align_errors" },
94 { STATS_OFFSET32(rx_stat_etherstatsundersizepkts_hi),
95 8, true, "rx_undersize_packets" },
96 { STATS_OFFSET32(etherstatsoverrsizepkts_hi),
97 8, true, "rx_oversize_packets" },
98 /* 10 */{ STATS_OFFSET32(rx_stat_etherstatsfragments_hi),
99 8, true, "rx_fragments" },
100 { STATS_OFFSET32(rx_stat_etherstatsjabbers_hi),
101 8, true, "rx_jabbers" },
102 { STATS_OFFSET32(no_buff_discard_hi),
103 8, false, "rx_discards" },
104 { STATS_OFFSET32(mac_filter_discard),
105 4, true, "rx_filtered_packets" },
106 { STATS_OFFSET32(mf_tag_discard),
107 4, true, "rx_mf_tag_discard" },
108 { STATS_OFFSET32(pfc_frames_received_hi),
109 8, true, "pfc_frames_received" },
110 { STATS_OFFSET32(pfc_frames_sent_hi),
111 8, true, "pfc_frames_sent" },
112 { STATS_OFFSET32(brb_drop_hi),
113 8, true, "rx_brb_discard" },
114 { STATS_OFFSET32(brb_truncate_hi),
115 8, true, "rx_brb_truncate" },
116 { STATS_OFFSET32(pause_frames_received_hi),
117 8, true, "rx_pause_frames" },
118 { STATS_OFFSET32(rx_stat_maccontrolframesreceived_hi),
119 8, true, "rx_mac_ctrl_frames" },
120 { STATS_OFFSET32(nig_timer_max),
121 4, true, "rx_constant_pause_events" },
122 /* 20 */{ STATS_OFFSET32(rx_err_discard_pkt),
123 4, false, "rx_phy_ip_err_discards"},
124 { STATS_OFFSET32(rx_skb_alloc_failed),
125 4, false, "rx_skb_alloc_discard" },
126 { STATS_OFFSET32(hw_csum_err),
127 4, false, "rx_csum_offload_errors" },
128 { STATS_OFFSET32(driver_xoff),
129 4, false, "tx_exhaustion_events" },
130 { STATS_OFFSET32(total_bytes_transmitted_hi),
131 8, false, "tx_bytes" },
132 { STATS_OFFSET32(tx_stat_ifhcoutbadoctets_hi),
133 8, true, "tx_error_bytes" },
134 { STATS_OFFSET32(total_unicast_packets_transmitted_hi),
135 8, false, "tx_ucast_packets" },
136 { STATS_OFFSET32(total_multicast_packets_transmitted_hi),
137 8, false, "tx_mcast_packets" },
138 { STATS_OFFSET32(total_broadcast_packets_transmitted_hi),
139 8, false, "tx_bcast_packets" },
140 { STATS_OFFSET32(tx_stat_dot3statsinternalmactransmiterrors_hi),
141 8, true, "tx_mac_errors" },
142 { STATS_OFFSET32(rx_stat_dot3statscarriersenseerrors_hi),
143 8, true, "tx_carrier_errors" },
144 /* 30 */{ STATS_OFFSET32(tx_stat_dot3statssinglecollisionframes_hi),
145 8, true, "tx_single_collisions" },
146 { STATS_OFFSET32(tx_stat_dot3statsmultiplecollisionframes_hi),
147 8, true, "tx_multi_collisions" },
148 { STATS_OFFSET32(tx_stat_dot3statsdeferredtransmissions_hi),
149 8, true, "tx_deferred" },
150 { STATS_OFFSET32(tx_stat_dot3statsexcessivecollisions_hi),
151 8, true, "tx_excess_collisions" },
152 { STATS_OFFSET32(tx_stat_dot3statslatecollisions_hi),
153 8, true, "tx_late_collisions" },
154 { STATS_OFFSET32(tx_stat_etherstatscollisions_hi),
155 8, true, "tx_total_collisions" },
156 { STATS_OFFSET32(tx_stat_etherstatspkts64octets_hi),
157 8, true, "tx_64_byte_packets" },
158 { STATS_OFFSET32(tx_stat_etherstatspkts65octetsto127octets_hi),
159 8, true, "tx_65_to_127_byte_packets" },
160 { STATS_OFFSET32(tx_stat_etherstatspkts128octetsto255octets_hi),
161 8, true, "tx_128_to_255_byte_packets" },
162 { STATS_OFFSET32(tx_stat_etherstatspkts256octetsto511octets_hi),
163 8, true, "tx_256_to_511_byte_packets" },
164 /* 40 */{ STATS_OFFSET32(tx_stat_etherstatspkts512octetsto1023octets_hi),
165 8, true, "tx_512_to_1023_byte_packets" },
166 { STATS_OFFSET32(etherstatspkts1024octetsto1522octets_hi),
167 8, true, "tx_1024_to_1522_byte_packets" },
168 { STATS_OFFSET32(etherstatspktsover1522octets_hi),
169 8, true, "tx_1523_to_9022_byte_packets" },
170 { STATS_OFFSET32(pause_frames_sent_hi),
171 8, true, "tx_pause_frames" },
172 { STATS_OFFSET32(total_tpa_aggregations_hi),
173 8, false, "tpa_aggregations" },
174 { STATS_OFFSET32(total_tpa_aggregated_frames_hi),
175 8, false, "tpa_aggregated_frames"},
176 { STATS_OFFSET32(total_tpa_bytes_hi),
177 8, false, "tpa_bytes"},
178 { STATS_OFFSET32(recoverable_error),
179 4, false, "recoverable_errors" },
180 { STATS_OFFSET32(unrecoverable_error),
181 4, false, "unrecoverable_errors" },
182 { STATS_OFFSET32(driver_filtered_tx_pkt),
183 4, false, "driver_filtered_tx_pkt" },
184 { STATS_OFFSET32(eee_tx_lpi),
185 4, true, "Tx LPI entry count"},
186 { STATS_OFFSET32(ptp_skip_tx_ts),
187 4, false, "ptp_skipped_tx_tstamp" },
190 #define BNX2X_NUM_STATS ARRAY_SIZE(bnx2x_stats_arr)
192 static int bnx2x_get_port_type(struct bnx2x *bp)
195 u32 phy_idx = bnx2x_get_cur_phy_idx(bp);
196 switch (bp->link_params.phy[phy_idx].media_type) {
197 case ETH_PHY_SFPP_10G_FIBER:
198 case ETH_PHY_SFP_1G_FIBER:
199 case ETH_PHY_XFP_FIBER:
202 port_type = PORT_FIBRE;
204 case ETH_PHY_DA_TWINAX:
210 case ETH_PHY_NOT_PRESENT:
211 port_type = PORT_NONE;
213 case ETH_PHY_UNSPECIFIED:
215 port_type = PORT_OTHER;
221 static int bnx2x_get_vf_link_ksettings(struct net_device *dev,
222 struct ethtool_link_ksettings *cmd)
224 struct bnx2x *bp = netdev_priv(dev);
225 u32 supported, advertising;
227 ethtool_convert_link_mode_to_legacy_u32(&supported,
228 cmd->link_modes.supported);
229 ethtool_convert_link_mode_to_legacy_u32(&advertising,
230 cmd->link_modes.advertising);
232 if (bp->state == BNX2X_STATE_OPEN) {
233 if (test_bit(BNX2X_LINK_REPORT_FD,
234 &bp->vf_link_vars.link_report_flags))
235 cmd->base.duplex = DUPLEX_FULL;
237 cmd->base.duplex = DUPLEX_HALF;
239 cmd->base.speed = bp->vf_link_vars.line_speed;
241 cmd->base.duplex = DUPLEX_UNKNOWN;
242 cmd->base.speed = SPEED_UNKNOWN;
245 cmd->base.port = PORT_OTHER;
246 cmd->base.phy_address = 0;
247 cmd->base.autoneg = AUTONEG_DISABLE;
249 DP(BNX2X_MSG_ETHTOOL, "ethtool_cmd: cmd %d\n"
250 " supported 0x%x advertising 0x%x speed %u\n"
251 " duplex %d port %d phy_address %d\n"
253 cmd->base.cmd, supported, advertising,
255 cmd->base.duplex, cmd->base.port, cmd->base.phy_address,
261 static int bnx2x_get_link_ksettings(struct net_device *dev,
262 struct ethtool_link_ksettings *cmd)
264 struct bnx2x *bp = netdev_priv(dev);
265 int cfg_idx = bnx2x_get_link_cfg_idx(bp);
267 u32 supported, advertising, lp_advertising;
269 ethtool_convert_link_mode_to_legacy_u32(&lp_advertising,
270 cmd->link_modes.lp_advertising);
272 /* Dual Media boards present all available port types */
273 supported = bp->port.supported[cfg_idx] |
274 (bp->port.supported[cfg_idx ^ 1] &
275 (SUPPORTED_TP | SUPPORTED_FIBRE));
276 advertising = bp->port.advertising[cfg_idx];
277 media_type = bp->link_params.phy[bnx2x_get_cur_phy_idx(bp)].media_type;
278 if (media_type == ETH_PHY_SFP_1G_FIBER) {
279 supported &= ~(SUPPORTED_10000baseT_Full);
280 advertising &= ~(ADVERTISED_10000baseT_Full);
283 if ((bp->state == BNX2X_STATE_OPEN) && bp->link_vars.link_up &&
284 !(bp->flags & MF_FUNC_DIS)) {
285 cmd->base.duplex = bp->link_vars.duplex;
287 if (IS_MF(bp) && !BP_NOMCP(bp))
288 cmd->base.speed = bnx2x_get_mf_speed(bp);
290 cmd->base.speed = bp->link_vars.line_speed;
292 cmd->base.duplex = DUPLEX_UNKNOWN;
293 cmd->base.speed = SPEED_UNKNOWN;
296 cmd->base.port = bnx2x_get_port_type(bp);
298 cmd->base.phy_address = bp->mdio.prtad;
300 if (bp->link_params.req_line_speed[cfg_idx] == SPEED_AUTO_NEG)
301 cmd->base.autoneg = AUTONEG_ENABLE;
303 cmd->base.autoneg = AUTONEG_DISABLE;
305 /* Publish LP advertised speeds and FC */
306 if (bp->link_vars.link_status & LINK_STATUS_AUTO_NEGOTIATE_COMPLETE) {
307 u32 status = bp->link_vars.link_status;
309 lp_advertising |= ADVERTISED_Autoneg;
310 if (status & LINK_STATUS_LINK_PARTNER_SYMMETRIC_PAUSE)
311 lp_advertising |= ADVERTISED_Pause;
312 if (status & LINK_STATUS_LINK_PARTNER_ASYMMETRIC_PAUSE)
313 lp_advertising |= ADVERTISED_Asym_Pause;
315 if (status & LINK_STATUS_LINK_PARTNER_10THD_CAPABLE)
316 lp_advertising |= ADVERTISED_10baseT_Half;
317 if (status & LINK_STATUS_LINK_PARTNER_10TFD_CAPABLE)
318 lp_advertising |= ADVERTISED_10baseT_Full;
319 if (status & LINK_STATUS_LINK_PARTNER_100TXHD_CAPABLE)
320 lp_advertising |= ADVERTISED_100baseT_Half;
321 if (status & LINK_STATUS_LINK_PARTNER_100TXFD_CAPABLE)
322 lp_advertising |= ADVERTISED_100baseT_Full;
323 if (status & LINK_STATUS_LINK_PARTNER_1000THD_CAPABLE)
324 lp_advertising |= ADVERTISED_1000baseT_Half;
325 if (status & LINK_STATUS_LINK_PARTNER_1000TFD_CAPABLE) {
326 if (media_type == ETH_PHY_KR) {
328 ADVERTISED_1000baseKX_Full;
331 ADVERTISED_1000baseT_Full;
334 if (status & LINK_STATUS_LINK_PARTNER_2500XFD_CAPABLE)
335 lp_advertising |= ADVERTISED_2500baseX_Full;
336 if (status & LINK_STATUS_LINK_PARTNER_10GXFD_CAPABLE) {
337 if (media_type == ETH_PHY_KR) {
339 ADVERTISED_10000baseKR_Full;
342 ADVERTISED_10000baseT_Full;
345 if (status & LINK_STATUS_LINK_PARTNER_20GXFD_CAPABLE)
346 lp_advertising |= ADVERTISED_20000baseKR2_Full;
349 ethtool_convert_legacy_u32_to_link_mode(cmd->link_modes.supported,
351 ethtool_convert_legacy_u32_to_link_mode(cmd->link_modes.advertising,
353 ethtool_convert_legacy_u32_to_link_mode(cmd->link_modes.lp_advertising,
356 DP(BNX2X_MSG_ETHTOOL, "ethtool_cmd: cmd %d\n"
357 " supported 0x%x advertising 0x%x speed %u\n"
358 " duplex %d port %d phy_address %d\n"
360 cmd->base.cmd, supported, advertising,
362 cmd->base.duplex, cmd->base.port, cmd->base.phy_address,
368 static int bnx2x_set_link_ksettings(struct net_device *dev,
369 const struct ethtool_link_ksettings *cmd)
371 struct bnx2x *bp = netdev_priv(dev);
372 u32 advertising, cfg_idx, old_multi_phy_config, new_multi_phy_config;
375 u8 duplex = cmd->base.duplex;
377 ethtool_convert_link_mode_to_legacy_u32(&supported,
378 cmd->link_modes.supported);
379 ethtool_convert_link_mode_to_legacy_u32(&advertising,
380 cmd->link_modes.advertising);
385 DP(BNX2X_MSG_ETHTOOL, "ethtool_cmd: cmd %d\n"
386 " supported 0x%x advertising 0x%x speed %u\n"
387 " duplex %d port %d phy_address %d\n"
389 cmd->base.cmd, supported, advertising,
391 cmd->base.duplex, cmd->base.port, cmd->base.phy_address,
394 speed = cmd->base.speed;
396 /* If received a request for an unknown duplex, assume full*/
397 if (duplex == DUPLEX_UNKNOWN)
398 duplex = DUPLEX_FULL;
402 u32 line_speed = bp->link_vars.line_speed;
404 /* use 10G if no link detected */
408 if (bp->common.bc_ver < REQ_BC_VER_4_SET_MF_BW) {
409 DP(BNX2X_MSG_ETHTOOL,
410 "To set speed BC %X or higher is required, please upgrade BC\n",
411 REQ_BC_VER_4_SET_MF_BW);
415 part = (speed * 100) / line_speed;
417 if (line_speed < speed || !part) {
418 DP(BNX2X_MSG_ETHTOOL,
419 "Speed setting should be in a range from 1%% to 100%% of actual line speed\n");
423 if (bp->state != BNX2X_STATE_OPEN)
424 /* store value for following "load" */
425 bp->pending_max = part;
427 bnx2x_update_max_mf_config(bp, part);
432 cfg_idx = bnx2x_get_link_cfg_idx(bp);
433 old_multi_phy_config = bp->link_params.multi_phy_config;
434 if (cmd->base.port != bnx2x_get_port_type(bp)) {
435 switch (cmd->base.port) {
437 if (!(bp->port.supported[0] & SUPPORTED_TP ||
438 bp->port.supported[1] & SUPPORTED_TP)) {
439 DP(BNX2X_MSG_ETHTOOL,
440 "Unsupported port type\n");
443 bp->link_params.multi_phy_config &=
444 ~PORT_HW_CFG_PHY_SELECTION_MASK;
445 if (bp->link_params.multi_phy_config &
446 PORT_HW_CFG_PHY_SWAPPED_ENABLED)
447 bp->link_params.multi_phy_config |=
448 PORT_HW_CFG_PHY_SELECTION_SECOND_PHY;
450 bp->link_params.multi_phy_config |=
451 PORT_HW_CFG_PHY_SELECTION_FIRST_PHY;
456 if (!(bp->port.supported[0] & SUPPORTED_FIBRE ||
457 bp->port.supported[1] & SUPPORTED_FIBRE)) {
458 DP(BNX2X_MSG_ETHTOOL,
459 "Unsupported port type\n");
462 bp->link_params.multi_phy_config &=
463 ~PORT_HW_CFG_PHY_SELECTION_MASK;
464 if (bp->link_params.multi_phy_config &
465 PORT_HW_CFG_PHY_SWAPPED_ENABLED)
466 bp->link_params.multi_phy_config |=
467 PORT_HW_CFG_PHY_SELECTION_FIRST_PHY;
469 bp->link_params.multi_phy_config |=
470 PORT_HW_CFG_PHY_SELECTION_SECOND_PHY;
473 DP(BNX2X_MSG_ETHTOOL, "Unsupported port type\n");
477 /* Save new config in case command complete successfully */
478 new_multi_phy_config = bp->link_params.multi_phy_config;
479 /* Get the new cfg_idx */
480 cfg_idx = bnx2x_get_link_cfg_idx(bp);
481 /* Restore old config in case command failed */
482 bp->link_params.multi_phy_config = old_multi_phy_config;
483 DP(BNX2X_MSG_ETHTOOL, "cfg_idx = %x\n", cfg_idx);
485 if (cmd->base.autoneg == AUTONEG_ENABLE) {
486 u32 an_supported_speed = bp->port.supported[cfg_idx];
487 if (bp->link_params.phy[EXT_PHY1].type ==
488 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84833)
489 an_supported_speed |= (SUPPORTED_100baseT_Half |
490 SUPPORTED_100baseT_Full);
491 if (!(bp->port.supported[cfg_idx] & SUPPORTED_Autoneg)) {
492 DP(BNX2X_MSG_ETHTOOL, "Autoneg not supported\n");
496 /* advertise the requested speed and duplex if supported */
497 if (advertising & ~an_supported_speed) {
498 DP(BNX2X_MSG_ETHTOOL,
499 "Advertisement parameters are not supported\n");
503 bp->link_params.req_line_speed[cfg_idx] = SPEED_AUTO_NEG;
504 bp->link_params.req_duplex[cfg_idx] = duplex;
505 bp->port.advertising[cfg_idx] = (ADVERTISED_Autoneg |
509 bp->link_params.speed_cap_mask[cfg_idx] = 0;
510 if (advertising & ADVERTISED_10baseT_Half) {
511 bp->link_params.speed_cap_mask[cfg_idx] |=
512 PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_HALF;
514 if (advertising & ADVERTISED_10baseT_Full)
515 bp->link_params.speed_cap_mask[cfg_idx] |=
516 PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_FULL;
518 if (advertising & ADVERTISED_100baseT_Full)
519 bp->link_params.speed_cap_mask[cfg_idx] |=
520 PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_FULL;
522 if (advertising & ADVERTISED_100baseT_Half) {
523 bp->link_params.speed_cap_mask[cfg_idx] |=
524 PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_HALF;
526 if (advertising & ADVERTISED_1000baseT_Half) {
527 bp->link_params.speed_cap_mask[cfg_idx] |=
528 PORT_HW_CFG_SPEED_CAPABILITY_D0_1G;
530 if (advertising & (ADVERTISED_1000baseT_Full |
531 ADVERTISED_1000baseKX_Full))
532 bp->link_params.speed_cap_mask[cfg_idx] |=
533 PORT_HW_CFG_SPEED_CAPABILITY_D0_1G;
535 if (advertising & (ADVERTISED_10000baseT_Full |
536 ADVERTISED_10000baseKX4_Full |
537 ADVERTISED_10000baseKR_Full))
538 bp->link_params.speed_cap_mask[cfg_idx] |=
539 PORT_HW_CFG_SPEED_CAPABILITY_D0_10G;
541 if (advertising & ADVERTISED_20000baseKR2_Full)
542 bp->link_params.speed_cap_mask[cfg_idx] |=
543 PORT_HW_CFG_SPEED_CAPABILITY_D0_20G;
545 } else { /* forced speed */
546 /* advertise the requested speed and duplex if supported */
549 if (duplex == DUPLEX_FULL) {
550 if (!(bp->port.supported[cfg_idx] &
551 SUPPORTED_10baseT_Full)) {
552 DP(BNX2X_MSG_ETHTOOL,
553 "10M full not supported\n");
557 advertising = (ADVERTISED_10baseT_Full |
560 if (!(bp->port.supported[cfg_idx] &
561 SUPPORTED_10baseT_Half)) {
562 DP(BNX2X_MSG_ETHTOOL,
563 "10M half not supported\n");
567 advertising = (ADVERTISED_10baseT_Half |
573 if (duplex == DUPLEX_FULL) {
574 if (!(bp->port.supported[cfg_idx] &
575 SUPPORTED_100baseT_Full)) {
576 DP(BNX2X_MSG_ETHTOOL,
577 "100M full not supported\n");
581 advertising = (ADVERTISED_100baseT_Full |
584 if (!(bp->port.supported[cfg_idx] &
585 SUPPORTED_100baseT_Half)) {
586 DP(BNX2X_MSG_ETHTOOL,
587 "100M half not supported\n");
591 advertising = (ADVERTISED_100baseT_Half |
597 if (duplex != DUPLEX_FULL) {
598 DP(BNX2X_MSG_ETHTOOL,
599 "1G half not supported\n");
603 if (bp->port.supported[cfg_idx] &
604 SUPPORTED_1000baseT_Full) {
605 advertising = (ADVERTISED_1000baseT_Full |
608 } else if (bp->port.supported[cfg_idx] &
609 SUPPORTED_1000baseKX_Full) {
610 advertising = ADVERTISED_1000baseKX_Full;
612 DP(BNX2X_MSG_ETHTOOL,
613 "1G full not supported\n");
620 if (duplex != DUPLEX_FULL) {
621 DP(BNX2X_MSG_ETHTOOL,
622 "2.5G half not supported\n");
626 if (!(bp->port.supported[cfg_idx]
627 & SUPPORTED_2500baseX_Full)) {
628 DP(BNX2X_MSG_ETHTOOL,
629 "2.5G full not supported\n");
633 advertising = (ADVERTISED_2500baseX_Full |
638 if (duplex != DUPLEX_FULL) {
639 DP(BNX2X_MSG_ETHTOOL,
640 "10G half not supported\n");
643 phy_idx = bnx2x_get_cur_phy_idx(bp);
644 if ((bp->port.supported[cfg_idx] &
645 SUPPORTED_10000baseT_Full) &&
646 (bp->link_params.phy[phy_idx].media_type !=
647 ETH_PHY_SFP_1G_FIBER)) {
648 advertising = (ADVERTISED_10000baseT_Full |
650 } else if (bp->port.supported[cfg_idx] &
651 SUPPORTED_10000baseKR_Full) {
652 advertising = (ADVERTISED_10000baseKR_Full |
655 DP(BNX2X_MSG_ETHTOOL,
656 "10G full not supported\n");
663 DP(BNX2X_MSG_ETHTOOL, "Unsupported speed %u\n", speed);
667 bp->link_params.req_line_speed[cfg_idx] = speed;
668 bp->link_params.req_duplex[cfg_idx] = duplex;
669 bp->port.advertising[cfg_idx] = advertising;
672 DP(BNX2X_MSG_ETHTOOL, "req_line_speed %d\n"
673 " req_duplex %d advertising 0x%x\n",
674 bp->link_params.req_line_speed[cfg_idx],
675 bp->link_params.req_duplex[cfg_idx],
676 bp->port.advertising[cfg_idx]);
679 bp->link_params.multi_phy_config = new_multi_phy_config;
680 if (netif_running(dev)) {
681 bnx2x_stats_handle(bp, STATS_EVENT_STOP);
682 bnx2x_force_link_reset(bp);
689 #define DUMP_ALL_PRESETS 0x1FFF
690 #define DUMP_MAX_PRESETS 13
692 static int __bnx2x_get_preset_regs_len(struct bnx2x *bp, u32 preset)
695 return dump_num_registers[0][preset-1];
696 else if (CHIP_IS_E1H(bp))
697 return dump_num_registers[1][preset-1];
698 else if (CHIP_IS_E2(bp))
699 return dump_num_registers[2][preset-1];
700 else if (CHIP_IS_E3A0(bp))
701 return dump_num_registers[3][preset-1];
702 else if (CHIP_IS_E3B0(bp))
703 return dump_num_registers[4][preset-1];
708 static int __bnx2x_get_regs_len(struct bnx2x *bp)
713 /* Calculate the total preset regs length */
714 for (preset_idx = 1; preset_idx <= DUMP_MAX_PRESETS; preset_idx++)
715 regdump_len += __bnx2x_get_preset_regs_len(bp, preset_idx);
720 static int bnx2x_get_regs_len(struct net_device *dev)
722 struct bnx2x *bp = netdev_priv(dev);
728 regdump_len = __bnx2x_get_regs_len(bp);
730 regdump_len += sizeof(struct dump_header);
735 #define IS_E1_REG(chips) ((chips & DUMP_CHIP_E1) == DUMP_CHIP_E1)
736 #define IS_E1H_REG(chips) ((chips & DUMP_CHIP_E1H) == DUMP_CHIP_E1H)
737 #define IS_E2_REG(chips) ((chips & DUMP_CHIP_E2) == DUMP_CHIP_E2)
738 #define IS_E3A0_REG(chips) ((chips & DUMP_CHIP_E3A0) == DUMP_CHIP_E3A0)
739 #define IS_E3B0_REG(chips) ((chips & DUMP_CHIP_E3B0) == DUMP_CHIP_E3B0)
741 #define IS_REG_IN_PRESET(presets, idx) \
742 ((presets & (1 << (idx-1))) == (1 << (idx-1)))
744 /******* Paged registers info selectors ********/
745 static const u32 *__bnx2x_get_page_addr_ar(struct bnx2x *bp)
749 else if (CHIP_IS_E3(bp))
755 static u32 __bnx2x_get_page_reg_num(struct bnx2x *bp)
758 return PAGE_MODE_VALUES_E2;
759 else if (CHIP_IS_E3(bp))
760 return PAGE_MODE_VALUES_E3;
765 static const u32 *__bnx2x_get_page_write_ar(struct bnx2x *bp)
768 return page_write_regs_e2;
769 else if (CHIP_IS_E3(bp))
770 return page_write_regs_e3;
775 static u32 __bnx2x_get_page_write_num(struct bnx2x *bp)
778 return PAGE_WRITE_REGS_E2;
779 else if (CHIP_IS_E3(bp))
780 return PAGE_WRITE_REGS_E3;
785 static const struct reg_addr *__bnx2x_get_page_read_ar(struct bnx2x *bp)
788 return page_read_regs_e2;
789 else if (CHIP_IS_E3(bp))
790 return page_read_regs_e3;
795 static u32 __bnx2x_get_page_read_num(struct bnx2x *bp)
798 return PAGE_READ_REGS_E2;
799 else if (CHIP_IS_E3(bp))
800 return PAGE_READ_REGS_E3;
805 static bool bnx2x_is_reg_in_chip(struct bnx2x *bp,
806 const struct reg_addr *reg_info)
809 return IS_E1_REG(reg_info->chips);
810 else if (CHIP_IS_E1H(bp))
811 return IS_E1H_REG(reg_info->chips);
812 else if (CHIP_IS_E2(bp))
813 return IS_E2_REG(reg_info->chips);
814 else if (CHIP_IS_E3A0(bp))
815 return IS_E3A0_REG(reg_info->chips);
816 else if (CHIP_IS_E3B0(bp))
817 return IS_E3B0_REG(reg_info->chips);
822 static bool bnx2x_is_wreg_in_chip(struct bnx2x *bp,
823 const struct wreg_addr *wreg_info)
826 return IS_E1_REG(wreg_info->chips);
827 else if (CHIP_IS_E1H(bp))
828 return IS_E1H_REG(wreg_info->chips);
829 else if (CHIP_IS_E2(bp))
830 return IS_E2_REG(wreg_info->chips);
831 else if (CHIP_IS_E3A0(bp))
832 return IS_E3A0_REG(wreg_info->chips);
833 else if (CHIP_IS_E3B0(bp))
834 return IS_E3B0_REG(wreg_info->chips);
840 * bnx2x_read_pages_regs - read "paged" registers
844 * @preset: the preset value
846 * Reads "paged" memories: memories that may only be read by first writing to a
847 * specific address ("write address") and then reading from a specific address
848 * ("read address"). There may be more than one write address per "page" and
849 * more than one read address per write address.
851 static void bnx2x_read_pages_regs(struct bnx2x *bp, u32 *p, u32 preset)
855 /* addresses of the paged registers */
856 const u32 *page_addr = __bnx2x_get_page_addr_ar(bp);
857 /* number of paged registers */
858 int num_pages = __bnx2x_get_page_reg_num(bp);
859 /* write addresses */
860 const u32 *write_addr = __bnx2x_get_page_write_ar(bp);
861 /* number of write addresses */
862 int write_num = __bnx2x_get_page_write_num(bp);
863 /* read addresses info */
864 const struct reg_addr *read_addr = __bnx2x_get_page_read_ar(bp);
865 /* number of read addresses */
866 int read_num = __bnx2x_get_page_read_num(bp);
869 for (i = 0; i < num_pages; i++) {
870 for (j = 0; j < write_num; j++) {
871 REG_WR(bp, write_addr[j], page_addr[i]);
873 for (k = 0; k < read_num; k++) {
874 if (IS_REG_IN_PRESET(read_addr[k].presets,
876 size = read_addr[k].size;
877 for (n = 0; n < size; n++) {
878 addr = read_addr[k].addr + n*4;
879 *p++ = REG_RD(bp, addr);
887 static int __bnx2x_get_preset_regs(struct bnx2x *bp, u32 *p, u32 preset)
890 const struct wreg_addr *wreg_addr_p = NULL;
893 wreg_addr_p = &wreg_addr_e1;
894 else if (CHIP_IS_E1H(bp))
895 wreg_addr_p = &wreg_addr_e1h;
896 else if (CHIP_IS_E2(bp))
897 wreg_addr_p = &wreg_addr_e2;
898 else if (CHIP_IS_E3A0(bp))
899 wreg_addr_p = &wreg_addr_e3;
900 else if (CHIP_IS_E3B0(bp))
901 wreg_addr_p = &wreg_addr_e3b0;
903 /* Read the idle_chk registers */
904 for (i = 0; i < IDLE_REGS_COUNT; i++) {
905 if (bnx2x_is_reg_in_chip(bp, &idle_reg_addrs[i]) &&
906 IS_REG_IN_PRESET(idle_reg_addrs[i].presets, preset)) {
907 for (j = 0; j < idle_reg_addrs[i].size; j++)
908 *p++ = REG_RD(bp, idle_reg_addrs[i].addr + j*4);
912 /* Read the regular registers */
913 for (i = 0; i < REGS_COUNT; i++) {
914 if (bnx2x_is_reg_in_chip(bp, ®_addrs[i]) &&
915 IS_REG_IN_PRESET(reg_addrs[i].presets, preset)) {
916 for (j = 0; j < reg_addrs[i].size; j++)
917 *p++ = REG_RD(bp, reg_addrs[i].addr + j*4);
921 /* Read the CAM registers */
922 if (bnx2x_is_wreg_in_chip(bp, wreg_addr_p) &&
923 IS_REG_IN_PRESET(wreg_addr_p->presets, preset)) {
924 for (i = 0; i < wreg_addr_p->size; i++) {
925 *p++ = REG_RD(bp, wreg_addr_p->addr + i*4);
927 /* In case of wreg_addr register, read additional
928 registers from read_regs array
930 for (j = 0; j < wreg_addr_p->read_regs_count; j++) {
931 addr = *(wreg_addr_p->read_regs);
932 *p++ = REG_RD(bp, addr + j*4);
937 /* Paged registers are supported in E2 & E3 only */
938 if (CHIP_IS_E2(bp) || CHIP_IS_E3(bp)) {
939 /* Read "paged" registers */
940 bnx2x_read_pages_regs(bp, p, preset);
946 static void __bnx2x_get_regs(struct bnx2x *bp, u32 *p)
950 /* Read all registers, by reading all preset registers */
951 for (preset_idx = 1; preset_idx <= DUMP_MAX_PRESETS; preset_idx++) {
952 /* Skip presets with IOR */
953 if ((preset_idx == 2) ||
958 __bnx2x_get_preset_regs(bp, p, preset_idx);
959 p += __bnx2x_get_preset_regs_len(bp, preset_idx);
963 static void bnx2x_get_regs(struct net_device *dev,
964 struct ethtool_regs *regs, void *_p)
967 struct bnx2x *bp = netdev_priv(dev);
968 struct dump_header dump_hdr = {0};
971 memset(p, 0, regs->len);
973 if (!netif_running(bp->dev))
976 /* Disable parity attentions as long as following dump may
977 * cause false alarms by reading never written registers. We
978 * will re-enable parity attentions right after the dump.
981 bnx2x_disable_blocks_parity(bp);
983 dump_hdr.header_size = (sizeof(struct dump_header) / 4) - 1;
984 dump_hdr.preset = DUMP_ALL_PRESETS;
985 dump_hdr.version = BNX2X_DUMP_VERSION;
987 /* dump_meta_data presents OR of CHIP and PATH. */
988 if (CHIP_IS_E1(bp)) {
989 dump_hdr.dump_meta_data = DUMP_CHIP_E1;
990 } else if (CHIP_IS_E1H(bp)) {
991 dump_hdr.dump_meta_data = DUMP_CHIP_E1H;
992 } else if (CHIP_IS_E2(bp)) {
993 dump_hdr.dump_meta_data = DUMP_CHIP_E2 |
994 (BP_PATH(bp) ? DUMP_PATH_1 : DUMP_PATH_0);
995 } else if (CHIP_IS_E3A0(bp)) {
996 dump_hdr.dump_meta_data = DUMP_CHIP_E3A0 |
997 (BP_PATH(bp) ? DUMP_PATH_1 : DUMP_PATH_0);
998 } else if (CHIP_IS_E3B0(bp)) {
999 dump_hdr.dump_meta_data = DUMP_CHIP_E3B0 |
1000 (BP_PATH(bp) ? DUMP_PATH_1 : DUMP_PATH_0);
1003 memcpy(p, &dump_hdr, sizeof(struct dump_header));
1004 p += dump_hdr.header_size + 1;
1006 /* This isn't really an error, but since attention handling is going
1007 * to print the GRC timeouts using this macro, we use the same.
1009 BNX2X_ERR("Generating register dump. Might trigger harmless GRC timeouts\n");
1011 /* Actually read the registers */
1012 __bnx2x_get_regs(bp, p);
1014 /* Re-enable parity attentions */
1015 bnx2x_clear_blocks_parity(bp);
1016 bnx2x_enable_blocks_parity(bp);
1019 static int bnx2x_get_preset_regs_len(struct net_device *dev, u32 preset)
1021 struct bnx2x *bp = netdev_priv(dev);
1022 int regdump_len = 0;
1024 regdump_len = __bnx2x_get_preset_regs_len(bp, preset);
1026 regdump_len += sizeof(struct dump_header);
1031 static int bnx2x_set_dump(struct net_device *dev, struct ethtool_dump *val)
1033 struct bnx2x *bp = netdev_priv(dev);
1035 /* Use the ethtool_dump "flag" field as the dump preset index */
1036 if (val->flag < 1 || val->flag > DUMP_MAX_PRESETS)
1039 bp->dump_preset_idx = val->flag;
1043 static int bnx2x_get_dump_flag(struct net_device *dev,
1044 struct ethtool_dump *dump)
1046 struct bnx2x *bp = netdev_priv(dev);
1048 dump->version = BNX2X_DUMP_VERSION;
1049 dump->flag = bp->dump_preset_idx;
1050 /* Calculate the requested preset idx length */
1051 dump->len = bnx2x_get_preset_regs_len(dev, bp->dump_preset_idx);
1052 DP(BNX2X_MSG_ETHTOOL, "Get dump preset %d length=%d\n",
1053 bp->dump_preset_idx, dump->len);
1057 static int bnx2x_get_dump_data(struct net_device *dev,
1058 struct ethtool_dump *dump,
1062 struct bnx2x *bp = netdev_priv(dev);
1063 struct dump_header dump_hdr = {0};
1065 /* Disable parity attentions as long as following dump may
1066 * cause false alarms by reading never written registers. We
1067 * will re-enable parity attentions right after the dump.
1070 bnx2x_disable_blocks_parity(bp);
1072 dump_hdr.header_size = (sizeof(struct dump_header) / 4) - 1;
1073 dump_hdr.preset = bp->dump_preset_idx;
1074 dump_hdr.version = BNX2X_DUMP_VERSION;
1076 DP(BNX2X_MSG_ETHTOOL, "Get dump data of preset %d\n", dump_hdr.preset);
1078 /* dump_meta_data presents OR of CHIP and PATH. */
1079 if (CHIP_IS_E1(bp)) {
1080 dump_hdr.dump_meta_data = DUMP_CHIP_E1;
1081 } else if (CHIP_IS_E1H(bp)) {
1082 dump_hdr.dump_meta_data = DUMP_CHIP_E1H;
1083 } else if (CHIP_IS_E2(bp)) {
1084 dump_hdr.dump_meta_data = DUMP_CHIP_E2 |
1085 (BP_PATH(bp) ? DUMP_PATH_1 : DUMP_PATH_0);
1086 } else if (CHIP_IS_E3A0(bp)) {
1087 dump_hdr.dump_meta_data = DUMP_CHIP_E3A0 |
1088 (BP_PATH(bp) ? DUMP_PATH_1 : DUMP_PATH_0);
1089 } else if (CHIP_IS_E3B0(bp)) {
1090 dump_hdr.dump_meta_data = DUMP_CHIP_E3B0 |
1091 (BP_PATH(bp) ? DUMP_PATH_1 : DUMP_PATH_0);
1094 memcpy(p, &dump_hdr, sizeof(struct dump_header));
1095 p += dump_hdr.header_size + 1;
1097 /* Actually read the registers */
1098 __bnx2x_get_preset_regs(bp, p, dump_hdr.preset);
1100 /* Re-enable parity attentions */
1101 bnx2x_clear_blocks_parity(bp);
1102 bnx2x_enable_blocks_parity(bp);
1107 static void bnx2x_get_drvinfo(struct net_device *dev,
1108 struct ethtool_drvinfo *info)
1110 struct bnx2x *bp = netdev_priv(dev);
1111 char version[ETHTOOL_FWVERS_LEN];
1112 int ext_dev_info_offset;
1115 strlcpy(info->driver, DRV_MODULE_NAME, sizeof(info->driver));
1117 if (SHMEM2_HAS(bp, extended_dev_info_shared_addr)) {
1118 ext_dev_info_offset = SHMEM2_RD(bp,
1119 extended_dev_info_shared_addr);
1120 mbi = REG_RD(bp, ext_dev_info_offset +
1121 offsetof(struct extended_dev_info_shared_cfg,
1124 memset(version, 0, sizeof(version));
1125 snprintf(version, ETHTOOL_FWVERS_LEN, "mbi %d.%d.%d ",
1126 (mbi & 0xff000000) >> 24,
1127 (mbi & 0x00ff0000) >> 16,
1128 (mbi & 0x0000ff00) >> 8);
1129 strlcpy(info->fw_version, version,
1130 sizeof(info->fw_version));
1134 memset(version, 0, sizeof(version));
1135 bnx2x_fill_fw_str(bp, version, ETHTOOL_FWVERS_LEN);
1136 strlcat(info->fw_version, version, sizeof(info->fw_version));
1138 strlcpy(info->bus_info, pci_name(bp->pdev), sizeof(info->bus_info));
1141 static void bnx2x_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
1143 struct bnx2x *bp = netdev_priv(dev);
1145 if (bp->flags & NO_WOL_FLAG) {
1149 wol->supported = WAKE_MAGIC;
1151 wol->wolopts = WAKE_MAGIC;
1155 memset(&wol->sopass, 0, sizeof(wol->sopass));
1158 static int bnx2x_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
1160 struct bnx2x *bp = netdev_priv(dev);
1162 if (wol->wolopts & ~WAKE_MAGIC) {
1163 DP(BNX2X_MSG_ETHTOOL, "WOL not supported\n");
1167 if (wol->wolopts & WAKE_MAGIC) {
1168 if (bp->flags & NO_WOL_FLAG) {
1169 DP(BNX2X_MSG_ETHTOOL, "WOL not supported\n");
1176 if (SHMEM2_HAS(bp, curr_cfg))
1177 SHMEM2_WR(bp, curr_cfg, CURR_CFG_MET_OS);
1182 static u32 bnx2x_get_msglevel(struct net_device *dev)
1184 struct bnx2x *bp = netdev_priv(dev);
1186 return bp->msg_enable;
1189 static void bnx2x_set_msglevel(struct net_device *dev, u32 level)
1191 struct bnx2x *bp = netdev_priv(dev);
1193 if (capable(CAP_NET_ADMIN)) {
1194 /* dump MCP trace */
1195 if (IS_PF(bp) && (level & BNX2X_MSG_MCP))
1196 bnx2x_fw_dump_lvl(bp, KERN_INFO);
1197 bp->msg_enable = level;
1201 static int bnx2x_nway_reset(struct net_device *dev)
1203 struct bnx2x *bp = netdev_priv(dev);
1208 if (netif_running(dev)) {
1209 bnx2x_stats_handle(bp, STATS_EVENT_STOP);
1210 bnx2x_force_link_reset(bp);
1217 static u32 bnx2x_get_link(struct net_device *dev)
1219 struct bnx2x *bp = netdev_priv(dev);
1221 if (bp->flags & MF_FUNC_DIS || (bp->state != BNX2X_STATE_OPEN))
1225 return !test_bit(BNX2X_LINK_REPORT_LINK_DOWN,
1226 &bp->vf_link_vars.link_report_flags);
1228 return bp->link_vars.link_up;
1231 static int bnx2x_get_eeprom_len(struct net_device *dev)
1233 struct bnx2x *bp = netdev_priv(dev);
1235 return bp->common.flash_size;
1238 /* Per pf misc lock must be acquired before the per port mcp lock. Otherwise,
1239 * had we done things the other way around, if two pfs from the same port would
1240 * attempt to access nvram at the same time, we could run into a scenario such
1242 * pf A takes the port lock.
1243 * pf B succeeds in taking the same lock since they are from the same port.
1244 * pf A takes the per pf misc lock. Performs eeprom access.
1245 * pf A finishes. Unlocks the per pf misc lock.
1246 * Pf B takes the lock and proceeds to perform it's own access.
1247 * pf A unlocks the per port lock, while pf B is still working (!).
1248 * mcp takes the per port lock and corrupts pf B's access (and/or has it's own
1249 * access corrupted by pf B)
1251 static int bnx2x_acquire_nvram_lock(struct bnx2x *bp)
1253 int port = BP_PORT(bp);
1257 /* acquire HW lock: protect against other PFs in PF Direct Assignment */
1258 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_NVRAM);
1260 /* adjust timeout for emulation/FPGA */
1261 count = BNX2X_NVRAM_TIMEOUT_COUNT;
1262 if (CHIP_REV_IS_SLOW(bp))
1265 /* request access to nvram interface */
1266 REG_WR(bp, MCP_REG_MCPR_NVM_SW_ARB,
1267 (MCPR_NVM_SW_ARB_ARB_REQ_SET1 << port));
1269 for (i = 0; i < count*10; i++) {
1270 val = REG_RD(bp, MCP_REG_MCPR_NVM_SW_ARB);
1271 if (val & (MCPR_NVM_SW_ARB_ARB_ARB1 << port))
1277 if (!(val & (MCPR_NVM_SW_ARB_ARB_ARB1 << port))) {
1278 DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM,
1279 "cannot get access to nvram interface\n");
1280 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_NVRAM);
1287 static int bnx2x_release_nvram_lock(struct bnx2x *bp)
1289 int port = BP_PORT(bp);
1293 /* adjust timeout for emulation/FPGA */
1294 count = BNX2X_NVRAM_TIMEOUT_COUNT;
1295 if (CHIP_REV_IS_SLOW(bp))
1298 /* relinquish nvram interface */
1299 REG_WR(bp, MCP_REG_MCPR_NVM_SW_ARB,
1300 (MCPR_NVM_SW_ARB_ARB_REQ_CLR1 << port));
1302 for (i = 0; i < count*10; i++) {
1303 val = REG_RD(bp, MCP_REG_MCPR_NVM_SW_ARB);
1304 if (!(val & (MCPR_NVM_SW_ARB_ARB_ARB1 << port)))
1310 if (val & (MCPR_NVM_SW_ARB_ARB_ARB1 << port)) {
1311 DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM,
1312 "cannot free access to nvram interface\n");
1316 /* release HW lock: protect against other PFs in PF Direct Assignment */
1317 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_NVRAM);
1321 static void bnx2x_enable_nvram_access(struct bnx2x *bp)
1325 val = REG_RD(bp, MCP_REG_MCPR_NVM_ACCESS_ENABLE);
1327 /* enable both bits, even on read */
1328 REG_WR(bp, MCP_REG_MCPR_NVM_ACCESS_ENABLE,
1329 (val | MCPR_NVM_ACCESS_ENABLE_EN |
1330 MCPR_NVM_ACCESS_ENABLE_WR_EN));
1333 static void bnx2x_disable_nvram_access(struct bnx2x *bp)
1337 val = REG_RD(bp, MCP_REG_MCPR_NVM_ACCESS_ENABLE);
1339 /* disable both bits, even after read */
1340 REG_WR(bp, MCP_REG_MCPR_NVM_ACCESS_ENABLE,
1341 (val & ~(MCPR_NVM_ACCESS_ENABLE_EN |
1342 MCPR_NVM_ACCESS_ENABLE_WR_EN)));
1345 static int bnx2x_nvram_read_dword(struct bnx2x *bp, u32 offset, __be32 *ret_val,
1351 /* build the command word */
1352 cmd_flags |= MCPR_NVM_COMMAND_DOIT;
1354 /* need to clear DONE bit separately */
1355 REG_WR(bp, MCP_REG_MCPR_NVM_COMMAND, MCPR_NVM_COMMAND_DONE);
1357 /* address of the NVRAM to read from */
1358 REG_WR(bp, MCP_REG_MCPR_NVM_ADDR,
1359 (offset & MCPR_NVM_ADDR_NVM_ADDR_VALUE));
1361 /* issue a read command */
1362 REG_WR(bp, MCP_REG_MCPR_NVM_COMMAND, cmd_flags);
1364 /* adjust timeout for emulation/FPGA */
1365 count = BNX2X_NVRAM_TIMEOUT_COUNT;
1366 if (CHIP_REV_IS_SLOW(bp))
1369 /* wait for completion */
1372 for (i = 0; i < count; i++) {
1374 val = REG_RD(bp, MCP_REG_MCPR_NVM_COMMAND);
1376 if (val & MCPR_NVM_COMMAND_DONE) {
1377 val = REG_RD(bp, MCP_REG_MCPR_NVM_READ);
1378 /* we read nvram data in cpu order
1379 * but ethtool sees it as an array of bytes
1380 * converting to big-endian will do the work
1382 *ret_val = cpu_to_be32(val);
1388 DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM,
1389 "nvram read timeout expired\n");
1393 int bnx2x_nvram_read(struct bnx2x *bp, u32 offset, u8 *ret_buf,
1400 if ((offset & 0x03) || (buf_size & 0x03) || (buf_size == 0)) {
1401 DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM,
1402 "Invalid parameter: offset 0x%x buf_size 0x%x\n",
1407 if (offset + buf_size > bp->common.flash_size) {
1408 DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM,
1409 "Invalid parameter: offset (0x%x) + buf_size (0x%x) > flash_size (0x%x)\n",
1410 offset, buf_size, bp->common.flash_size);
1414 /* request access to nvram interface */
1415 rc = bnx2x_acquire_nvram_lock(bp);
1419 /* enable access to nvram interface */
1420 bnx2x_enable_nvram_access(bp);
1422 /* read the first word(s) */
1423 cmd_flags = MCPR_NVM_COMMAND_FIRST;
1424 while ((buf_size > sizeof(u32)) && (rc == 0)) {
1425 rc = bnx2x_nvram_read_dword(bp, offset, &val, cmd_flags);
1426 memcpy(ret_buf, &val, 4);
1428 /* advance to the next dword */
1429 offset += sizeof(u32);
1430 ret_buf += sizeof(u32);
1431 buf_size -= sizeof(u32);
1436 cmd_flags |= MCPR_NVM_COMMAND_LAST;
1437 rc = bnx2x_nvram_read_dword(bp, offset, &val, cmd_flags);
1438 memcpy(ret_buf, &val, 4);
1441 /* disable access to nvram interface */
1442 bnx2x_disable_nvram_access(bp);
1443 bnx2x_release_nvram_lock(bp);
1448 static int bnx2x_nvram_read32(struct bnx2x *bp, u32 offset, u32 *buf,
1453 rc = bnx2x_nvram_read(bp, offset, (u8 *)buf, buf_size);
1456 __be32 *be = (__be32 *)buf;
1458 while ((buf_size -= 4) >= 0)
1459 *buf++ = be32_to_cpu(*be++);
1465 static bool bnx2x_is_nvm_accessible(struct bnx2x *bp)
1469 struct net_device *dev = pci_get_drvdata(bp->pdev);
1471 if (bp->pdev->pm_cap)
1472 rc = pci_read_config_word(bp->pdev,
1473 bp->pdev->pm_cap + PCI_PM_CTRL, &pm);
1475 if ((rc && !netif_running(dev)) ||
1476 (!rc && ((pm & PCI_PM_CTRL_STATE_MASK) != (__force u16)PCI_D0)))
1482 static int bnx2x_get_eeprom(struct net_device *dev,
1483 struct ethtool_eeprom *eeprom, u8 *eebuf)
1485 struct bnx2x *bp = netdev_priv(dev);
1487 if (!bnx2x_is_nvm_accessible(bp)) {
1488 DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM,
1489 "cannot access eeprom when the interface is down\n");
1493 DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM, "ethtool_eeprom: cmd %d\n"
1494 " magic 0x%x offset 0x%x (%d) len 0x%x (%d)\n",
1495 eeprom->cmd, eeprom->magic, eeprom->offset, eeprom->offset,
1496 eeprom->len, eeprom->len);
1498 /* parameters already validated in ethtool_get_eeprom */
1500 return bnx2x_nvram_read(bp, eeprom->offset, eebuf, eeprom->len);
1503 static int bnx2x_get_module_eeprom(struct net_device *dev,
1504 struct ethtool_eeprom *ee,
1507 struct bnx2x *bp = netdev_priv(dev);
1508 int rc = -EINVAL, phy_idx;
1509 u8 *user_data = data;
1510 unsigned int start_addr = ee->offset, xfer_size = 0;
1512 if (!bnx2x_is_nvm_accessible(bp)) {
1513 DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM,
1514 "cannot access eeprom when the interface is down\n");
1518 phy_idx = bnx2x_get_cur_phy_idx(bp);
1520 /* Read A0 section */
1521 if (start_addr < ETH_MODULE_SFF_8079_LEN) {
1522 /* Limit transfer size to the A0 section boundary */
1523 if (start_addr + ee->len > ETH_MODULE_SFF_8079_LEN)
1524 xfer_size = ETH_MODULE_SFF_8079_LEN - start_addr;
1526 xfer_size = ee->len;
1527 bnx2x_acquire_phy_lock(bp);
1528 rc = bnx2x_read_sfp_module_eeprom(&bp->link_params.phy[phy_idx],
1534 bnx2x_release_phy_lock(bp);
1536 DP(BNX2X_MSG_ETHTOOL, "Failed reading A0 section\n");
1540 user_data += xfer_size;
1541 start_addr += xfer_size;
1544 /* Read A2 section */
1545 if ((start_addr >= ETH_MODULE_SFF_8079_LEN) &&
1546 (start_addr < ETH_MODULE_SFF_8472_LEN)) {
1547 xfer_size = ee->len - xfer_size;
1548 /* Limit transfer size to the A2 section boundary */
1549 if (start_addr + xfer_size > ETH_MODULE_SFF_8472_LEN)
1550 xfer_size = ETH_MODULE_SFF_8472_LEN - start_addr;
1551 start_addr -= ETH_MODULE_SFF_8079_LEN;
1552 bnx2x_acquire_phy_lock(bp);
1553 rc = bnx2x_read_sfp_module_eeprom(&bp->link_params.phy[phy_idx],
1559 bnx2x_release_phy_lock(bp);
1561 DP(BNX2X_MSG_ETHTOOL, "Failed reading A2 section\n");
1568 static int bnx2x_get_module_info(struct net_device *dev,
1569 struct ethtool_modinfo *modinfo)
1571 struct bnx2x *bp = netdev_priv(dev);
1573 u8 sff8472_comp, diag_type;
1575 if (!bnx2x_is_nvm_accessible(bp)) {
1576 DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM,
1577 "cannot access eeprom when the interface is down\n");
1580 phy_idx = bnx2x_get_cur_phy_idx(bp);
1581 bnx2x_acquire_phy_lock(bp);
1582 rc = bnx2x_read_sfp_module_eeprom(&bp->link_params.phy[phy_idx],
1585 SFP_EEPROM_SFF_8472_COMP_ADDR,
1586 SFP_EEPROM_SFF_8472_COMP_SIZE,
1588 bnx2x_release_phy_lock(bp);
1590 DP(BNX2X_MSG_ETHTOOL, "Failed reading SFF-8472 comp field\n");
1594 bnx2x_acquire_phy_lock(bp);
1595 rc = bnx2x_read_sfp_module_eeprom(&bp->link_params.phy[phy_idx],
1598 SFP_EEPROM_DIAG_TYPE_ADDR,
1599 SFP_EEPROM_DIAG_TYPE_SIZE,
1601 bnx2x_release_phy_lock(bp);
1603 DP(BNX2X_MSG_ETHTOOL, "Failed reading Diag Type field\n");
1607 if (!sff8472_comp ||
1608 (diag_type & SFP_EEPROM_DIAG_ADDR_CHANGE_REQ) ||
1609 !(diag_type & SFP_EEPROM_DDM_IMPLEMENTED)) {
1610 modinfo->type = ETH_MODULE_SFF_8079;
1611 modinfo->eeprom_len = ETH_MODULE_SFF_8079_LEN;
1613 modinfo->type = ETH_MODULE_SFF_8472;
1614 modinfo->eeprom_len = ETH_MODULE_SFF_8472_LEN;
1619 static int bnx2x_nvram_write_dword(struct bnx2x *bp, u32 offset, u32 val,
1624 /* build the command word */
1625 cmd_flags |= MCPR_NVM_COMMAND_DOIT | MCPR_NVM_COMMAND_WR;
1627 /* need to clear DONE bit separately */
1628 REG_WR(bp, MCP_REG_MCPR_NVM_COMMAND, MCPR_NVM_COMMAND_DONE);
1630 /* write the data */
1631 REG_WR(bp, MCP_REG_MCPR_NVM_WRITE, val);
1633 /* address of the NVRAM to write to */
1634 REG_WR(bp, MCP_REG_MCPR_NVM_ADDR,
1635 (offset & MCPR_NVM_ADDR_NVM_ADDR_VALUE));
1637 /* issue the write command */
1638 REG_WR(bp, MCP_REG_MCPR_NVM_COMMAND, cmd_flags);
1640 /* adjust timeout for emulation/FPGA */
1641 count = BNX2X_NVRAM_TIMEOUT_COUNT;
1642 if (CHIP_REV_IS_SLOW(bp))
1645 /* wait for completion */
1647 for (i = 0; i < count; i++) {
1649 val = REG_RD(bp, MCP_REG_MCPR_NVM_COMMAND);
1650 if (val & MCPR_NVM_COMMAND_DONE) {
1657 DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM,
1658 "nvram write timeout expired\n");
1662 #define BYTE_OFFSET(offset) (8 * (offset & 0x03))
1664 static int bnx2x_nvram_write1(struct bnx2x *bp, u32 offset, u8 *data_buf,
1668 u32 cmd_flags, align_offset, val;
1671 if (offset + buf_size > bp->common.flash_size) {
1672 DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM,
1673 "Invalid parameter: offset (0x%x) + buf_size (0x%x) > flash_size (0x%x)\n",
1674 offset, buf_size, bp->common.flash_size);
1678 /* request access to nvram interface */
1679 rc = bnx2x_acquire_nvram_lock(bp);
1683 /* enable access to nvram interface */
1684 bnx2x_enable_nvram_access(bp);
1686 cmd_flags = (MCPR_NVM_COMMAND_FIRST | MCPR_NVM_COMMAND_LAST);
1687 align_offset = (offset & ~0x03);
1688 rc = bnx2x_nvram_read_dword(bp, align_offset, &val_be, cmd_flags);
1691 /* nvram data is returned as an array of bytes
1692 * convert it back to cpu order
1694 val = be32_to_cpu(val_be);
1696 val &= ~le32_to_cpu((__force __le32)
1697 (0xff << BYTE_OFFSET(offset)));
1698 val |= le32_to_cpu((__force __le32)
1699 (*data_buf << BYTE_OFFSET(offset)));
1701 rc = bnx2x_nvram_write_dword(bp, align_offset, val,
1705 /* disable access to nvram interface */
1706 bnx2x_disable_nvram_access(bp);
1707 bnx2x_release_nvram_lock(bp);
1712 static int bnx2x_nvram_write(struct bnx2x *bp, u32 offset, u8 *data_buf,
1720 if (buf_size == 1) /* ethtool */
1721 return bnx2x_nvram_write1(bp, offset, data_buf, buf_size);
1723 if ((offset & 0x03) || (buf_size & 0x03) || (buf_size == 0)) {
1724 DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM,
1725 "Invalid parameter: offset 0x%x buf_size 0x%x\n",
1730 if (offset + buf_size > bp->common.flash_size) {
1731 DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM,
1732 "Invalid parameter: offset (0x%x) + buf_size (0x%x) > flash_size (0x%x)\n",
1733 offset, buf_size, bp->common.flash_size);
1737 /* request access to nvram interface */
1738 rc = bnx2x_acquire_nvram_lock(bp);
1742 /* enable access to nvram interface */
1743 bnx2x_enable_nvram_access(bp);
1746 cmd_flags = MCPR_NVM_COMMAND_FIRST;
1747 while ((written_so_far < buf_size) && (rc == 0)) {
1748 if (written_so_far == (buf_size - sizeof(u32)))
1749 cmd_flags |= MCPR_NVM_COMMAND_LAST;
1750 else if (((offset + 4) % BNX2X_NVRAM_PAGE_SIZE) == 0)
1751 cmd_flags |= MCPR_NVM_COMMAND_LAST;
1752 else if ((offset % BNX2X_NVRAM_PAGE_SIZE) == 0)
1753 cmd_flags |= MCPR_NVM_COMMAND_FIRST;
1755 memcpy(&val, data_buf, 4);
1757 /* Notice unlike bnx2x_nvram_read_dword() this will not
1758 * change val using be32_to_cpu(), which causes data to flip
1759 * if the eeprom is read and then written back. This is due
1760 * to tools utilizing this functionality that would break
1761 * if this would be resolved.
1763 rc = bnx2x_nvram_write_dword(bp, offset, val, cmd_flags);
1765 /* advance to the next dword */
1766 offset += sizeof(u32);
1767 data_buf += sizeof(u32);
1768 written_so_far += sizeof(u32);
1770 /* At end of each 4Kb page, release nvram lock to allow MFW
1771 * chance to take it for its own use.
1773 if ((cmd_flags & MCPR_NVM_COMMAND_LAST) &&
1774 (written_so_far < buf_size)) {
1775 DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM,
1776 "Releasing NVM lock after offset 0x%x\n",
1777 (u32)(offset - sizeof(u32)));
1778 bnx2x_release_nvram_lock(bp);
1779 usleep_range(1000, 2000);
1780 rc = bnx2x_acquire_nvram_lock(bp);
1788 /* disable access to nvram interface */
1789 bnx2x_disable_nvram_access(bp);
1790 bnx2x_release_nvram_lock(bp);
1795 static int bnx2x_set_eeprom(struct net_device *dev,
1796 struct ethtool_eeprom *eeprom, u8 *eebuf)
1798 struct bnx2x *bp = netdev_priv(dev);
1799 int port = BP_PORT(bp);
1803 if (!bnx2x_is_nvm_accessible(bp)) {
1804 DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM,
1805 "cannot access eeprom when the interface is down\n");
1809 DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM, "ethtool_eeprom: cmd %d\n"
1810 " magic 0x%x offset 0x%x (%d) len 0x%x (%d)\n",
1811 eeprom->cmd, eeprom->magic, eeprom->offset, eeprom->offset,
1812 eeprom->len, eeprom->len);
1814 /* parameters already validated in ethtool_set_eeprom */
1816 /* PHY eeprom can be accessed only by the PMF */
1817 if ((eeprom->magic >= 0x50485900) && (eeprom->magic <= 0x504859FF) &&
1819 DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM,
1820 "wrong magic or interface is not pmf\n");
1826 dev_info.port_hw_config[port].external_phy_config);
1828 if (eeprom->magic == 0x50485950) {
1829 /* 'PHYP' (0x50485950): prepare phy for FW upgrade */
1830 bnx2x_stats_handle(bp, STATS_EVENT_STOP);
1832 bnx2x_acquire_phy_lock(bp);
1833 rc |= bnx2x_link_reset(&bp->link_params,
1835 if (XGXS_EXT_PHY_TYPE(ext_phy_config) ==
1836 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_SFX7101)
1837 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_0,
1838 MISC_REGISTERS_GPIO_HIGH, port);
1839 bnx2x_release_phy_lock(bp);
1840 bnx2x_link_report(bp);
1842 } else if (eeprom->magic == 0x50485952) {
1843 /* 'PHYR' (0x50485952): re-init link after FW upgrade */
1844 if (bp->state == BNX2X_STATE_OPEN) {
1845 bnx2x_acquire_phy_lock(bp);
1846 rc |= bnx2x_link_reset(&bp->link_params,
1849 rc |= bnx2x_phy_init(&bp->link_params,
1851 bnx2x_release_phy_lock(bp);
1852 bnx2x_calc_fc_adv(bp);
1854 } else if (eeprom->magic == 0x53985943) {
1855 /* 'PHYC' (0x53985943): PHY FW upgrade completed */
1856 if (XGXS_EXT_PHY_TYPE(ext_phy_config) ==
1857 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_SFX7101) {
1859 /* DSP Remove Download Mode */
1860 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_0,
1861 MISC_REGISTERS_GPIO_LOW, port);
1863 bnx2x_acquire_phy_lock(bp);
1865 bnx2x_sfx7101_sp_sw_reset(bp,
1866 &bp->link_params.phy[EXT_PHY1]);
1868 /* wait 0.5 sec to allow it to run */
1870 bnx2x_ext_phy_hw_reset(bp, port);
1872 bnx2x_release_phy_lock(bp);
1875 rc = bnx2x_nvram_write(bp, eeprom->offset, eebuf, eeprom->len);
1880 static int bnx2x_get_coalesce(struct net_device *dev,
1881 struct ethtool_coalesce *coal,
1882 struct kernel_ethtool_coalesce *kernel_coal,
1883 struct netlink_ext_ack *extack)
1885 struct bnx2x *bp = netdev_priv(dev);
1887 memset(coal, 0, sizeof(struct ethtool_coalesce));
1889 coal->rx_coalesce_usecs = bp->rx_ticks;
1890 coal->tx_coalesce_usecs = bp->tx_ticks;
1895 static int bnx2x_set_coalesce(struct net_device *dev,
1896 struct ethtool_coalesce *coal,
1897 struct kernel_ethtool_coalesce *kernel_coal,
1898 struct netlink_ext_ack *extack)
1900 struct bnx2x *bp = netdev_priv(dev);
1902 bp->rx_ticks = (u16)coal->rx_coalesce_usecs;
1903 if (bp->rx_ticks > BNX2X_MAX_COALESCE_TOUT)
1904 bp->rx_ticks = BNX2X_MAX_COALESCE_TOUT;
1906 bp->tx_ticks = (u16)coal->tx_coalesce_usecs;
1907 if (bp->tx_ticks > BNX2X_MAX_COALESCE_TOUT)
1908 bp->tx_ticks = BNX2X_MAX_COALESCE_TOUT;
1910 if (netif_running(dev))
1911 bnx2x_update_coalesce(bp);
1916 static void bnx2x_get_ringparam(struct net_device *dev,
1917 struct ethtool_ringparam *ering)
1919 struct bnx2x *bp = netdev_priv(dev);
1921 ering->rx_max_pending = MAX_RX_AVAIL;
1923 /* If size isn't already set, we give an estimation of the number
1924 * of buffers we'll have. We're neglecting some possible conditions
1925 * [we couldn't know for certain at this point if number of queues
1926 * might shrink] but the number would be correct for the likely
1929 if (bp->rx_ring_size)
1930 ering->rx_pending = bp->rx_ring_size;
1931 else if (BNX2X_NUM_RX_QUEUES(bp))
1932 ering->rx_pending = MAX_RX_AVAIL / BNX2X_NUM_RX_QUEUES(bp);
1934 ering->rx_pending = MAX_RX_AVAIL;
1936 ering->tx_max_pending = IS_MF_FCOE_AFEX(bp) ? 0 : MAX_TX_AVAIL;
1937 ering->tx_pending = bp->tx_ring_size;
1940 static int bnx2x_set_ringparam(struct net_device *dev,
1941 struct ethtool_ringparam *ering)
1943 struct bnx2x *bp = netdev_priv(dev);
1945 DP(BNX2X_MSG_ETHTOOL,
1946 "set ring params command parameters: rx_pending = %d, tx_pending = %d\n",
1947 ering->rx_pending, ering->tx_pending);
1949 if (pci_num_vf(bp->pdev)) {
1951 "VFs are enabled, can not change ring parameters\n");
1955 if (bp->recovery_state != BNX2X_RECOVERY_DONE) {
1956 DP(BNX2X_MSG_ETHTOOL,
1957 "Handling parity error recovery. Try again later\n");
1961 if ((ering->rx_pending > MAX_RX_AVAIL) ||
1962 (ering->rx_pending < (bp->disable_tpa ? MIN_RX_SIZE_NONTPA :
1963 MIN_RX_SIZE_TPA)) ||
1964 (ering->tx_pending > (IS_MF_STORAGE_ONLY(bp) ? 0 : MAX_TX_AVAIL)) ||
1965 (ering->tx_pending <= MAX_SKB_FRAGS + 4)) {
1966 DP(BNX2X_MSG_ETHTOOL, "Command parameters not supported\n");
1970 bp->rx_ring_size = ering->rx_pending;
1971 bp->tx_ring_size = ering->tx_pending;
1973 return bnx2x_reload_if_running(dev);
1976 static void bnx2x_get_pauseparam(struct net_device *dev,
1977 struct ethtool_pauseparam *epause)
1979 struct bnx2x *bp = netdev_priv(dev);
1980 int cfg_idx = bnx2x_get_link_cfg_idx(bp);
1983 epause->autoneg = (bp->link_params.req_flow_ctrl[cfg_idx] ==
1984 BNX2X_FLOW_CTRL_AUTO);
1986 if (!epause->autoneg)
1987 cfg_reg = bp->link_params.req_flow_ctrl[cfg_idx];
1989 cfg_reg = bp->link_params.req_fc_auto_adv;
1991 epause->rx_pause = ((cfg_reg & BNX2X_FLOW_CTRL_RX) ==
1992 BNX2X_FLOW_CTRL_RX);
1993 epause->tx_pause = ((cfg_reg & BNX2X_FLOW_CTRL_TX) ==
1994 BNX2X_FLOW_CTRL_TX);
1996 DP(BNX2X_MSG_ETHTOOL, "ethtool_pauseparam: cmd %d\n"
1997 " autoneg %d rx_pause %d tx_pause %d\n",
1998 epause->cmd, epause->autoneg, epause->rx_pause, epause->tx_pause);
2001 static int bnx2x_set_pauseparam(struct net_device *dev,
2002 struct ethtool_pauseparam *epause)
2004 struct bnx2x *bp = netdev_priv(dev);
2005 u32 cfg_idx = bnx2x_get_link_cfg_idx(bp);
2009 DP(BNX2X_MSG_ETHTOOL, "ethtool_pauseparam: cmd %d\n"
2010 " autoneg %d rx_pause %d tx_pause %d\n",
2011 epause->cmd, epause->autoneg, epause->rx_pause, epause->tx_pause);
2013 bp->link_params.req_flow_ctrl[cfg_idx] = BNX2X_FLOW_CTRL_AUTO;
2015 if (epause->rx_pause)
2016 bp->link_params.req_flow_ctrl[cfg_idx] |= BNX2X_FLOW_CTRL_RX;
2018 if (epause->tx_pause)
2019 bp->link_params.req_flow_ctrl[cfg_idx] |= BNX2X_FLOW_CTRL_TX;
2021 if (bp->link_params.req_flow_ctrl[cfg_idx] == BNX2X_FLOW_CTRL_AUTO)
2022 bp->link_params.req_flow_ctrl[cfg_idx] = BNX2X_FLOW_CTRL_NONE;
2024 if (epause->autoneg) {
2025 if (!(bp->port.supported[cfg_idx] & SUPPORTED_Autoneg)) {
2026 DP(BNX2X_MSG_ETHTOOL, "autoneg not supported\n");
2030 if (bp->link_params.req_line_speed[cfg_idx] == SPEED_AUTO_NEG) {
2031 bp->link_params.req_flow_ctrl[cfg_idx] =
2032 BNX2X_FLOW_CTRL_AUTO;
2034 bp->link_params.req_fc_auto_adv = 0;
2035 if (epause->rx_pause)
2036 bp->link_params.req_fc_auto_adv |= BNX2X_FLOW_CTRL_RX;
2038 if (epause->tx_pause)
2039 bp->link_params.req_fc_auto_adv |= BNX2X_FLOW_CTRL_TX;
2041 if (!bp->link_params.req_fc_auto_adv)
2042 bp->link_params.req_fc_auto_adv |= BNX2X_FLOW_CTRL_NONE;
2045 DP(BNX2X_MSG_ETHTOOL,
2046 "req_flow_ctrl 0x%x\n", bp->link_params.req_flow_ctrl[cfg_idx]);
2048 if (netif_running(dev)) {
2049 bnx2x_stats_handle(bp, STATS_EVENT_STOP);
2050 bnx2x_force_link_reset(bp);
2057 static const char bnx2x_tests_str_arr[BNX2X_NUM_TESTS_SF][ETH_GSTRING_LEN] = {
2058 "register_test (offline) ",
2059 "memory_test (offline) ",
2060 "int_loopback_test (offline)",
2061 "ext_loopback_test (offline)",
2062 "nvram_test (online) ",
2063 "interrupt_test (online) ",
2064 "link_test (online) "
2068 BNX2X_PRI_FLAG_ISCSI,
2069 BNX2X_PRI_FLAG_FCOE,
2070 BNX2X_PRI_FLAG_STORAGE,
2074 static const char bnx2x_private_arr[BNX2X_PRI_FLAG_LEN][ETH_GSTRING_LEN] = {
2075 "iSCSI offload support",
2076 "FCoE offload support",
2077 "Storage only interface"
2080 static u32 bnx2x_eee_to_adv(u32 eee_adv)
2084 if (eee_adv & SHMEM_EEE_100M_ADV)
2085 modes |= ADVERTISED_100baseT_Full;
2086 if (eee_adv & SHMEM_EEE_1G_ADV)
2087 modes |= ADVERTISED_1000baseT_Full;
2088 if (eee_adv & SHMEM_EEE_10G_ADV)
2089 modes |= ADVERTISED_10000baseT_Full;
2094 static u32 bnx2x_adv_to_eee(u32 modes, u32 shift)
2097 if (modes & ADVERTISED_100baseT_Full)
2098 eee_adv |= SHMEM_EEE_100M_ADV;
2099 if (modes & ADVERTISED_1000baseT_Full)
2100 eee_adv |= SHMEM_EEE_1G_ADV;
2101 if (modes & ADVERTISED_10000baseT_Full)
2102 eee_adv |= SHMEM_EEE_10G_ADV;
2104 return eee_adv << shift;
2107 static int bnx2x_get_eee(struct net_device *dev, struct ethtool_eee *edata)
2109 struct bnx2x *bp = netdev_priv(dev);
2112 if (!SHMEM2_HAS(bp, eee_status[BP_PORT(bp)])) {
2113 DP(BNX2X_MSG_ETHTOOL, "BC Version does not support EEE\n");
2117 eee_cfg = bp->link_vars.eee_status;
2120 bnx2x_eee_to_adv((eee_cfg & SHMEM_EEE_SUPPORTED_MASK) >>
2121 SHMEM_EEE_SUPPORTED_SHIFT);
2124 bnx2x_eee_to_adv((eee_cfg & SHMEM_EEE_ADV_STATUS_MASK) >>
2125 SHMEM_EEE_ADV_STATUS_SHIFT);
2126 edata->lp_advertised =
2127 bnx2x_eee_to_adv((eee_cfg & SHMEM_EEE_LP_ADV_STATUS_MASK) >>
2128 SHMEM_EEE_LP_ADV_STATUS_SHIFT);
2130 /* SHMEM value is in 16u units --> Convert to 1u units. */
2131 edata->tx_lpi_timer = (eee_cfg & SHMEM_EEE_TIMER_MASK) << 4;
2133 edata->eee_enabled = (eee_cfg & SHMEM_EEE_REQUESTED_BIT) ? 1 : 0;
2134 edata->eee_active = (eee_cfg & SHMEM_EEE_ACTIVE_BIT) ? 1 : 0;
2135 edata->tx_lpi_enabled = (eee_cfg & SHMEM_EEE_LPI_REQUESTED_BIT) ? 1 : 0;
2140 static int bnx2x_set_eee(struct net_device *dev, struct ethtool_eee *edata)
2142 struct bnx2x *bp = netdev_priv(dev);
2149 if (!SHMEM2_HAS(bp, eee_status[BP_PORT(bp)])) {
2150 DP(BNX2X_MSG_ETHTOOL, "BC Version does not support EEE\n");
2154 eee_cfg = bp->link_vars.eee_status;
2156 if (!(eee_cfg & SHMEM_EEE_SUPPORTED_MASK)) {
2157 DP(BNX2X_MSG_ETHTOOL, "Board does not support EEE!\n");
2161 advertised = bnx2x_adv_to_eee(edata->advertised,
2162 SHMEM_EEE_ADV_STATUS_SHIFT);
2163 if ((advertised != (eee_cfg & SHMEM_EEE_ADV_STATUS_MASK))) {
2164 DP(BNX2X_MSG_ETHTOOL,
2165 "Direct manipulation of EEE advertisement is not supported\n");
2169 if (edata->tx_lpi_timer > EEE_MODE_TIMER_MASK) {
2170 DP(BNX2X_MSG_ETHTOOL,
2171 "Maximal Tx Lpi timer supported is %x(u)\n",
2172 EEE_MODE_TIMER_MASK);
2175 if (edata->tx_lpi_enabled &&
2176 (edata->tx_lpi_timer < EEE_MODE_NVRAM_AGGRESSIVE_TIME)) {
2177 DP(BNX2X_MSG_ETHTOOL,
2178 "Minimal Tx Lpi timer supported is %d(u)\n",
2179 EEE_MODE_NVRAM_AGGRESSIVE_TIME);
2183 /* All is well; Apply changes*/
2184 if (edata->eee_enabled)
2185 bp->link_params.eee_mode |= EEE_MODE_ADV_LPI;
2187 bp->link_params.eee_mode &= ~EEE_MODE_ADV_LPI;
2189 if (edata->tx_lpi_enabled)
2190 bp->link_params.eee_mode |= EEE_MODE_ENABLE_LPI;
2192 bp->link_params.eee_mode &= ~EEE_MODE_ENABLE_LPI;
2194 bp->link_params.eee_mode &= ~EEE_MODE_TIMER_MASK;
2195 bp->link_params.eee_mode |= (edata->tx_lpi_timer &
2196 EEE_MODE_TIMER_MASK) |
2197 EEE_MODE_OVERRIDE_NVRAM |
2198 EEE_MODE_OUTPUT_TIME;
2200 /* Restart link to propagate changes */
2201 if (netif_running(dev)) {
2202 bnx2x_stats_handle(bp, STATS_EVENT_STOP);
2203 bnx2x_force_link_reset(bp);
2211 BNX2X_CHIP_E1_OFST = 0,
2212 BNX2X_CHIP_E1H_OFST,
2215 BNX2X_CHIP_E3B0_OFST,
2219 #define BNX2X_CHIP_MASK_E1 (1 << BNX2X_CHIP_E1_OFST)
2220 #define BNX2X_CHIP_MASK_E1H (1 << BNX2X_CHIP_E1H_OFST)
2221 #define BNX2X_CHIP_MASK_E2 (1 << BNX2X_CHIP_E2_OFST)
2222 #define BNX2X_CHIP_MASK_E3 (1 << BNX2X_CHIP_E3_OFST)
2223 #define BNX2X_CHIP_MASK_E3B0 (1 << BNX2X_CHIP_E3B0_OFST)
2225 #define BNX2X_CHIP_MASK_ALL ((1 << BNX2X_CHIP_MAX_OFST) - 1)
2226 #define BNX2X_CHIP_MASK_E1X (BNX2X_CHIP_MASK_E1 | BNX2X_CHIP_MASK_E1H)
2228 static int bnx2x_test_registers(struct bnx2x *bp)
2230 int idx, i, rc = -ENODEV;
2232 int port = BP_PORT(bp);
2233 static const struct {
2239 /* 0 */ { BNX2X_CHIP_MASK_ALL,
2240 BRB1_REG_PAUSE_LOW_THRESHOLD_0, 4, 0x000003ff },
2241 { BNX2X_CHIP_MASK_ALL,
2242 DORQ_REG_DB_ADDR0, 4, 0xffffffff },
2243 { BNX2X_CHIP_MASK_E1X,
2244 HC_REG_AGG_INT_0, 4, 0x000003ff },
2245 { BNX2X_CHIP_MASK_ALL,
2246 PBF_REG_MAC_IF0_ENABLE, 4, 0x00000001 },
2247 { BNX2X_CHIP_MASK_E1X | BNX2X_CHIP_MASK_E2 | BNX2X_CHIP_MASK_E3,
2248 PBF_REG_P0_INIT_CRD, 4, 0x000007ff },
2249 { BNX2X_CHIP_MASK_E3B0,
2250 PBF_REG_INIT_CRD_Q0, 4, 0x000007ff },
2251 { BNX2X_CHIP_MASK_ALL,
2252 PRS_REG_CID_PORT_0, 4, 0x00ffffff },
2253 { BNX2X_CHIP_MASK_ALL,
2254 PXP2_REG_PSWRQ_CDU0_L2P, 4, 0x000fffff },
2255 { BNX2X_CHIP_MASK_ALL,
2256 PXP2_REG_RQ_CDU0_EFIRST_MEM_ADDR, 8, 0x0003ffff },
2257 { BNX2X_CHIP_MASK_ALL,
2258 PXP2_REG_PSWRQ_TM0_L2P, 4, 0x000fffff },
2259 /* 10 */ { BNX2X_CHIP_MASK_ALL,
2260 PXP2_REG_RQ_USDM0_EFIRST_MEM_ADDR, 8, 0x0003ffff },
2261 { BNX2X_CHIP_MASK_ALL,
2262 PXP2_REG_PSWRQ_TSDM0_L2P, 4, 0x000fffff },
2263 { BNX2X_CHIP_MASK_ALL,
2264 QM_REG_CONNNUM_0, 4, 0x000fffff },
2265 { BNX2X_CHIP_MASK_ALL,
2266 TM_REG_LIN0_MAX_ACTIVE_CID, 4, 0x0003ffff },
2267 { BNX2X_CHIP_MASK_ALL,
2268 SRC_REG_KEYRSS0_0, 40, 0xffffffff },
2269 { BNX2X_CHIP_MASK_ALL,
2270 SRC_REG_KEYRSS0_7, 40, 0xffffffff },
2271 { BNX2X_CHIP_MASK_ALL,
2272 XCM_REG_WU_DA_SET_TMR_CNT_FLG_CMD00, 4, 0x00000001 },
2273 { BNX2X_CHIP_MASK_ALL,
2274 XCM_REG_WU_DA_CNT_CMD00, 4, 0x00000003 },
2275 { BNX2X_CHIP_MASK_ALL,
2276 XCM_REG_GLB_DEL_ACK_MAX_CNT_0, 4, 0x000000ff },
2277 { BNX2X_CHIP_MASK_ALL,
2278 NIG_REG_LLH0_T_BIT, 4, 0x00000001 },
2279 /* 20 */ { BNX2X_CHIP_MASK_E1X | BNX2X_CHIP_MASK_E2,
2280 NIG_REG_EMAC0_IN_EN, 4, 0x00000001 },
2281 { BNX2X_CHIP_MASK_E1X | BNX2X_CHIP_MASK_E2,
2282 NIG_REG_BMAC0_IN_EN, 4, 0x00000001 },
2283 { BNX2X_CHIP_MASK_ALL,
2284 NIG_REG_XCM0_OUT_EN, 4, 0x00000001 },
2285 { BNX2X_CHIP_MASK_ALL,
2286 NIG_REG_BRB0_OUT_EN, 4, 0x00000001 },
2287 { BNX2X_CHIP_MASK_ALL,
2288 NIG_REG_LLH0_XCM_MASK, 4, 0x00000007 },
2289 { BNX2X_CHIP_MASK_ALL,
2290 NIG_REG_LLH0_ACPI_PAT_6_LEN, 68, 0x000000ff },
2291 { BNX2X_CHIP_MASK_ALL,
2292 NIG_REG_LLH0_ACPI_PAT_0_CRC, 68, 0xffffffff },
2293 { BNX2X_CHIP_MASK_ALL,
2294 NIG_REG_LLH0_DEST_MAC_0_0, 160, 0xffffffff },
2295 { BNX2X_CHIP_MASK_ALL,
2296 NIG_REG_LLH0_DEST_IP_0_1, 160, 0xffffffff },
2297 { BNX2X_CHIP_MASK_ALL,
2298 NIG_REG_LLH0_IPV4_IPV6_0, 160, 0x00000001 },
2299 /* 30 */ { BNX2X_CHIP_MASK_ALL,
2300 NIG_REG_LLH0_DEST_UDP_0, 160, 0x0000ffff },
2301 { BNX2X_CHIP_MASK_ALL,
2302 NIG_REG_LLH0_DEST_TCP_0, 160, 0x0000ffff },
2303 { BNX2X_CHIP_MASK_ALL,
2304 NIG_REG_LLH0_VLAN_ID_0, 160, 0x00000fff },
2305 { BNX2X_CHIP_MASK_E1X | BNX2X_CHIP_MASK_E2,
2306 NIG_REG_XGXS_SERDES0_MODE_SEL, 4, 0x00000001 },
2307 { BNX2X_CHIP_MASK_ALL,
2308 NIG_REG_LED_CONTROL_OVERRIDE_TRAFFIC_P0, 4, 0x00000001},
2309 { BNX2X_CHIP_MASK_ALL,
2310 NIG_REG_STATUS_INTERRUPT_PORT0, 4, 0x07ffffff },
2311 { BNX2X_CHIP_MASK_E1X | BNX2X_CHIP_MASK_E2,
2312 NIG_REG_XGXS0_CTRL_EXTREMOTEMDIOST, 24, 0x00000001 },
2313 { BNX2X_CHIP_MASK_E1X | BNX2X_CHIP_MASK_E2,
2314 NIG_REG_SERDES0_CTRL_PHY_ADDR, 16, 0x0000001f },
2316 { BNX2X_CHIP_MASK_ALL, 0xffffffff, 0, 0x00000000 }
2319 if (!bnx2x_is_nvm_accessible(bp)) {
2320 DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM,
2321 "cannot access eeprom when the interface is down\n");
2326 hw = BNX2X_CHIP_MASK_E1;
2327 else if (CHIP_IS_E1H(bp))
2328 hw = BNX2X_CHIP_MASK_E1H;
2329 else if (CHIP_IS_E2(bp))
2330 hw = BNX2X_CHIP_MASK_E2;
2331 else if (CHIP_IS_E3B0(bp))
2332 hw = BNX2X_CHIP_MASK_E3B0;
2334 hw = BNX2X_CHIP_MASK_E3;
2336 /* Repeat the test twice:
2337 * First by writing 0x00000000, second by writing 0xffffffff
2339 for (idx = 0; idx < 2; idx++) {
2346 wr_val = 0xffffffff;
2350 for (i = 0; reg_tbl[i].offset0 != 0xffffffff; i++) {
2351 u32 offset, mask, save_val, val;
2352 if (!(hw & reg_tbl[i].hw))
2355 offset = reg_tbl[i].offset0 + port*reg_tbl[i].offset1;
2356 mask = reg_tbl[i].mask;
2358 save_val = REG_RD(bp, offset);
2360 REG_WR(bp, offset, wr_val & mask);
2362 val = REG_RD(bp, offset);
2364 /* Restore the original register's value */
2365 REG_WR(bp, offset, save_val);
2367 /* verify value is as expected */
2368 if ((val & mask) != (wr_val & mask)) {
2369 DP(BNX2X_MSG_ETHTOOL,
2370 "offset 0x%x: val 0x%x != 0x%x mask 0x%x\n",
2371 offset, val, wr_val, mask);
2383 static int bnx2x_test_memory(struct bnx2x *bp)
2385 int i, j, rc = -ENODEV;
2387 static const struct {
2391 { CCM_REG_XX_DESCR_TABLE, CCM_REG_XX_DESCR_TABLE_SIZE },
2392 { CFC_REG_ACTIVITY_COUNTER, CFC_REG_ACTIVITY_COUNTER_SIZE },
2393 { CFC_REG_LINK_LIST, CFC_REG_LINK_LIST_SIZE },
2394 { DMAE_REG_CMD_MEM, DMAE_REG_CMD_MEM_SIZE },
2395 { TCM_REG_XX_DESCR_TABLE, TCM_REG_XX_DESCR_TABLE_SIZE },
2396 { UCM_REG_XX_DESCR_TABLE, UCM_REG_XX_DESCR_TABLE_SIZE },
2397 { XCM_REG_XX_DESCR_TABLE, XCM_REG_XX_DESCR_TABLE_SIZE },
2402 static const struct {
2405 u32 hw_mask[BNX2X_CHIP_MAX_OFST];
2407 { "CCM_PRTY_STS", CCM_REG_CCM_PRTY_STS,
2408 {0x3ffc0, 0, 0, 0} },
2409 { "CFC_PRTY_STS", CFC_REG_CFC_PRTY_STS,
2411 { "DMAE_PRTY_STS", DMAE_REG_DMAE_PRTY_STS,
2413 { "TCM_PRTY_STS", TCM_REG_TCM_PRTY_STS,
2414 {0x3ffc0, 0, 0, 0} },
2415 { "UCM_PRTY_STS", UCM_REG_UCM_PRTY_STS,
2416 {0x3ffc0, 0, 0, 0} },
2417 { "XCM_PRTY_STS", XCM_REG_XCM_PRTY_STS,
2418 {0x3ffc1, 0, 0, 0} },
2420 { NULL, 0xffffffff, {0, 0, 0, 0} }
2423 if (!bnx2x_is_nvm_accessible(bp)) {
2424 DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM,
2425 "cannot access eeprom when the interface is down\n");
2430 index = BNX2X_CHIP_E1_OFST;
2431 else if (CHIP_IS_E1H(bp))
2432 index = BNX2X_CHIP_E1H_OFST;
2433 else if (CHIP_IS_E2(bp))
2434 index = BNX2X_CHIP_E2_OFST;
2436 index = BNX2X_CHIP_E3_OFST;
2438 /* pre-Check the parity status */
2439 for (i = 0; prty_tbl[i].offset != 0xffffffff; i++) {
2440 val = REG_RD(bp, prty_tbl[i].offset);
2441 if (val & ~(prty_tbl[i].hw_mask[index])) {
2442 DP(BNX2X_MSG_ETHTOOL,
2443 "%s is 0x%x\n", prty_tbl[i].name, val);
2448 /* Go through all the memories */
2449 for (i = 0; mem_tbl[i].offset != 0xffffffff; i++)
2450 for (j = 0; j < mem_tbl[i].size; j++)
2451 REG_RD(bp, mem_tbl[i].offset + j*4);
2453 /* Check the parity status */
2454 for (i = 0; prty_tbl[i].offset != 0xffffffff; i++) {
2455 val = REG_RD(bp, prty_tbl[i].offset);
2456 if (val & ~(prty_tbl[i].hw_mask[index])) {
2457 DP(BNX2X_MSG_ETHTOOL,
2458 "%s is 0x%x\n", prty_tbl[i].name, val);
2469 static void bnx2x_wait_for_link(struct bnx2x *bp, u8 link_up, u8 is_serdes)
2474 while (bnx2x_link_test(bp, is_serdes) && cnt--)
2477 if (cnt <= 0 && bnx2x_link_test(bp, is_serdes))
2478 DP(BNX2X_MSG_ETHTOOL, "Timeout waiting for link up\n");
2481 while (!bp->link_vars.link_up && cnt--)
2484 if (cnt <= 0 && !bp->link_vars.link_up)
2485 DP(BNX2X_MSG_ETHTOOL,
2486 "Timeout waiting for link init\n");
2490 static int bnx2x_run_loopback(struct bnx2x *bp, int loopback_mode)
2492 unsigned int pkt_size, num_pkts, i;
2493 struct sk_buff *skb;
2494 unsigned char *packet;
2495 struct bnx2x_fastpath *fp_rx = &bp->fp[0];
2496 struct bnx2x_fastpath *fp_tx = &bp->fp[0];
2497 struct bnx2x_fp_txdata *txdata = fp_tx->txdata_ptr[0];
2498 u16 tx_start_idx, tx_idx;
2499 u16 rx_start_idx, rx_idx;
2500 u16 pkt_prod, bd_prod;
2501 struct sw_tx_bd *tx_buf;
2502 struct eth_tx_start_bd *tx_start_bd;
2504 union eth_rx_cqe *cqe;
2505 u8 cqe_fp_flags, cqe_fp_type;
2506 struct sw_rx_bd *rx_buf;
2510 struct netdev_queue *txq = netdev_get_tx_queue(bp->dev,
2513 /* check the loopback mode */
2514 switch (loopback_mode) {
2515 case BNX2X_PHY_LOOPBACK:
2516 if (bp->link_params.loopback_mode != LOOPBACK_XGXS) {
2517 DP(BNX2X_MSG_ETHTOOL, "PHY loopback not supported\n");
2521 case BNX2X_MAC_LOOPBACK:
2522 if (CHIP_IS_E3(bp)) {
2523 int cfg_idx = bnx2x_get_link_cfg_idx(bp);
2524 if (bp->port.supported[cfg_idx] &
2525 (SUPPORTED_10000baseT_Full |
2526 SUPPORTED_20000baseMLD2_Full |
2527 SUPPORTED_20000baseKR2_Full))
2528 bp->link_params.loopback_mode = LOOPBACK_XMAC;
2530 bp->link_params.loopback_mode = LOOPBACK_UMAC;
2532 bp->link_params.loopback_mode = LOOPBACK_BMAC;
2534 bnx2x_phy_init(&bp->link_params, &bp->link_vars);
2536 case BNX2X_EXT_LOOPBACK:
2537 if (bp->link_params.loopback_mode != LOOPBACK_EXT) {
2538 DP(BNX2X_MSG_ETHTOOL,
2539 "Can't configure external loopback\n");
2544 DP(BNX2X_MSG_ETHTOOL, "Command parameters not supported\n");
2548 /* prepare the loopback packet */
2549 pkt_size = (((bp->dev->mtu < ETH_MAX_PACKET_SIZE) ?
2550 bp->dev->mtu : ETH_MAX_PACKET_SIZE) + ETH_HLEN);
2551 skb = netdev_alloc_skb(bp->dev, fp_rx->rx_buf_size);
2553 DP(BNX2X_MSG_ETHTOOL, "Can't allocate skb\n");
2555 goto test_loopback_exit;
2557 packet = skb_put(skb, pkt_size);
2558 memcpy(packet, bp->dev->dev_addr, ETH_ALEN);
2559 eth_zero_addr(packet + ETH_ALEN);
2560 memset(packet + 2*ETH_ALEN, 0x77, (ETH_HLEN - 2*ETH_ALEN));
2561 for (i = ETH_HLEN; i < pkt_size; i++)
2562 packet[i] = (unsigned char) (i & 0xff);
2563 mapping = dma_map_single(&bp->pdev->dev, skb->data,
2564 skb_headlen(skb), DMA_TO_DEVICE);
2565 if (unlikely(dma_mapping_error(&bp->pdev->dev, mapping))) {
2568 DP(BNX2X_MSG_ETHTOOL, "Unable to map SKB\n");
2569 goto test_loopback_exit;
2572 /* send the loopback packet */
2574 tx_start_idx = le16_to_cpu(*txdata->tx_cons_sb);
2575 rx_start_idx = le16_to_cpu(*fp_rx->rx_cons_sb);
2577 netdev_tx_sent_queue(txq, skb->len);
2579 pkt_prod = txdata->tx_pkt_prod++;
2580 tx_buf = &txdata->tx_buf_ring[TX_BD(pkt_prod)];
2581 tx_buf->first_bd = txdata->tx_bd_prod;
2585 bd_prod = TX_BD(txdata->tx_bd_prod);
2586 tx_start_bd = &txdata->tx_desc_ring[bd_prod].start_bd;
2587 tx_start_bd->addr_hi = cpu_to_le32(U64_HI(mapping));
2588 tx_start_bd->addr_lo = cpu_to_le32(U64_LO(mapping));
2589 tx_start_bd->nbd = cpu_to_le16(2); /* start + pbd */
2590 tx_start_bd->nbytes = cpu_to_le16(skb_headlen(skb));
2591 tx_start_bd->vlan_or_ethertype = cpu_to_le16(pkt_prod);
2592 tx_start_bd->bd_flags.as_bitfield = ETH_TX_BD_FLAGS_START_BD;
2593 SET_FLAG(tx_start_bd->general_data,
2594 ETH_TX_START_BD_HDR_NBDS,
2596 SET_FLAG(tx_start_bd->general_data,
2597 ETH_TX_START_BD_PARSE_NBDS,
2600 /* turn on parsing and get a BD */
2601 bd_prod = TX_BD(NEXT_TX_IDX(bd_prod));
2603 if (CHIP_IS_E1x(bp)) {
2604 u16 global_data = 0;
2605 struct eth_tx_parse_bd_e1x *pbd_e1x =
2606 &txdata->tx_desc_ring[bd_prod].parse_bd_e1x;
2607 memset(pbd_e1x, 0, sizeof(struct eth_tx_parse_bd_e1x));
2608 SET_FLAG(global_data,
2609 ETH_TX_PARSE_BD_E1X_ETH_ADDR_TYPE, UNICAST_ADDRESS);
2610 pbd_e1x->global_data = cpu_to_le16(global_data);
2612 u32 parsing_data = 0;
2613 struct eth_tx_parse_bd_e2 *pbd_e2 =
2614 &txdata->tx_desc_ring[bd_prod].parse_bd_e2;
2615 memset(pbd_e2, 0, sizeof(struct eth_tx_parse_bd_e2));
2616 SET_FLAG(parsing_data,
2617 ETH_TX_PARSE_BD_E2_ETH_ADDR_TYPE, UNICAST_ADDRESS);
2618 pbd_e2->parsing_data = cpu_to_le32(parsing_data);
2622 txdata->tx_db.data.prod += 2;
2623 /* make sure descriptor update is observed by the HW */
2625 DOORBELL_RELAXED(bp, txdata->cid, txdata->tx_db.raw);
2630 txdata->tx_bd_prod += 2; /* start + pbd */
2634 tx_idx = le16_to_cpu(*txdata->tx_cons_sb);
2635 if (tx_idx != tx_start_idx + num_pkts)
2636 goto test_loopback_exit;
2638 /* Unlike HC IGU won't generate an interrupt for status block
2639 * updates that have been performed while interrupts were
2642 if (bp->common.int_block == INT_BLOCK_IGU) {
2643 /* Disable local BHes to prevent a dead-lock situation between
2644 * sch_direct_xmit() and bnx2x_run_loopback() (calling
2645 * bnx2x_tx_int()), as both are taking netif_tx_lock().
2648 bnx2x_tx_int(bp, txdata);
2652 rx_idx = le16_to_cpu(*fp_rx->rx_cons_sb);
2653 if (rx_idx != rx_start_idx + num_pkts)
2654 goto test_loopback_exit;
2656 cqe = &fp_rx->rx_comp_ring[RCQ_BD(fp_rx->rx_comp_cons)];
2657 cqe_fp_flags = cqe->fast_path_cqe.type_error_flags;
2658 cqe_fp_type = cqe_fp_flags & ETH_FAST_PATH_RX_CQE_TYPE;
2659 if (!CQE_TYPE_FAST(cqe_fp_type) || (cqe_fp_flags & ETH_RX_ERROR_FALGS))
2660 goto test_loopback_rx_exit;
2662 len = le16_to_cpu(cqe->fast_path_cqe.pkt_len_or_gro_seg_len);
2663 if (len != pkt_size)
2664 goto test_loopback_rx_exit;
2666 rx_buf = &fp_rx->rx_buf_ring[RX_BD(fp_rx->rx_bd_cons)];
2667 dma_sync_single_for_cpu(&bp->pdev->dev,
2668 dma_unmap_addr(rx_buf, mapping),
2669 fp_rx->rx_buf_size, DMA_FROM_DEVICE);
2670 data = rx_buf->data + NET_SKB_PAD + cqe->fast_path_cqe.placement_offset;
2671 for (i = ETH_HLEN; i < pkt_size; i++)
2672 if (*(data + i) != (unsigned char) (i & 0xff))
2673 goto test_loopback_rx_exit;
2677 test_loopback_rx_exit:
2679 fp_rx->rx_bd_cons = NEXT_RX_IDX(fp_rx->rx_bd_cons);
2680 fp_rx->rx_bd_prod = NEXT_RX_IDX(fp_rx->rx_bd_prod);
2681 fp_rx->rx_comp_cons = NEXT_RCQ_IDX(fp_rx->rx_comp_cons);
2682 fp_rx->rx_comp_prod = NEXT_RCQ_IDX(fp_rx->rx_comp_prod);
2684 /* Update producers */
2685 bnx2x_update_rx_prod(bp, fp_rx, fp_rx->rx_bd_prod, fp_rx->rx_comp_prod,
2686 fp_rx->rx_sge_prod);
2689 bp->link_params.loopback_mode = LOOPBACK_NONE;
2694 static int bnx2x_test_loopback(struct bnx2x *bp)
2701 if (!netif_running(bp->dev))
2702 return BNX2X_LOOPBACK_FAILED;
2704 bnx2x_netif_stop(bp, 1);
2705 bnx2x_acquire_phy_lock(bp);
2707 res = bnx2x_run_loopback(bp, BNX2X_PHY_LOOPBACK);
2709 DP(BNX2X_MSG_ETHTOOL, " PHY loopback failed (res %d)\n", res);
2710 rc |= BNX2X_PHY_LOOPBACK_FAILED;
2713 res = bnx2x_run_loopback(bp, BNX2X_MAC_LOOPBACK);
2715 DP(BNX2X_MSG_ETHTOOL, " MAC loopback failed (res %d)\n", res);
2716 rc |= BNX2X_MAC_LOOPBACK_FAILED;
2719 bnx2x_release_phy_lock(bp);
2720 bnx2x_netif_start(bp);
2725 static int bnx2x_test_ext_loopback(struct bnx2x *bp)
2729 (bp->link_vars.link_status & LINK_STATUS_SERDES_LINK) > 0;
2734 if (!netif_running(bp->dev))
2735 return BNX2X_EXT_LOOPBACK_FAILED;
2737 bnx2x_nic_unload(bp, UNLOAD_NORMAL, false);
2738 rc = bnx2x_nic_load(bp, LOAD_LOOPBACK_EXT);
2740 DP(BNX2X_MSG_ETHTOOL,
2741 "Can't perform self-test, nic_load (for external lb) failed\n");
2744 bnx2x_wait_for_link(bp, 1, is_serdes);
2746 bnx2x_netif_stop(bp, 1);
2748 rc = bnx2x_run_loopback(bp, BNX2X_EXT_LOOPBACK);
2750 DP(BNX2X_MSG_ETHTOOL, "EXT loopback failed (res %d)\n", rc);
2752 bnx2x_netif_start(bp);
2758 u32 sram_start_addr;
2760 #define CODE_IMAGE_TYPE_MASK 0xf0800003
2761 #define CODE_IMAGE_VNTAG_PROFILES_DATA 0xd0000003
2762 #define CODE_IMAGE_LENGTH_MASK 0x007ffffc
2763 #define CODE_IMAGE_TYPE_EXTENDED_DIR 0xe0000000
2767 #define CODE_ENTRY_MAX 16
2768 #define CODE_ENTRY_EXTENDED_DIR_IDX 15
2769 #define MAX_IMAGES_IN_EXTENDED_DIR 64
2770 #define NVRAM_DIR_OFFSET 0x14
2772 #define EXTENDED_DIR_EXISTS(code) \
2773 ((code & CODE_IMAGE_TYPE_MASK) == CODE_IMAGE_TYPE_EXTENDED_DIR && \
2774 (code & CODE_IMAGE_LENGTH_MASK) != 0)
2776 #define CRC32_RESIDUAL 0xdebb20e3
2777 #define CRC_BUFF_SIZE 256
2779 static int bnx2x_nvram_crc(struct bnx2x *bp,
2785 int rc = 0, done = 0;
2787 DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM,
2788 "NVRAM CRC from 0x%08x to 0x%08x\n", offset, offset + size);
2790 while (done < size) {
2791 int count = min_t(int, size - done, CRC_BUFF_SIZE);
2793 rc = bnx2x_nvram_read(bp, offset + done, buff, count);
2798 crc = crc32_le(crc, buff, count);
2802 if (crc != CRC32_RESIDUAL)
2808 static int bnx2x_test_nvram_dir(struct bnx2x *bp,
2809 struct code_entry *entry,
2812 size_t size = entry->code_attribute & CODE_IMAGE_LENGTH_MASK;
2813 u32 type = entry->code_attribute & CODE_IMAGE_TYPE_MASK;
2816 /* Zero-length images and AFEX profiles do not have CRC */
2817 if (size == 0 || type == CODE_IMAGE_VNTAG_PROFILES_DATA)
2820 rc = bnx2x_nvram_crc(bp, entry->nvm_start_addr, size, buff);
2822 DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM,
2823 "image %x has failed crc test (rc %d)\n", type, rc);
2828 static int bnx2x_test_dir_entry(struct bnx2x *bp, u32 addr, u8 *buff)
2831 struct code_entry entry;
2833 rc = bnx2x_nvram_read32(bp, addr, (u32 *)&entry, sizeof(entry));
2837 return bnx2x_test_nvram_dir(bp, &entry, buff);
2840 static int bnx2x_test_nvram_ext_dirs(struct bnx2x *bp, u8 *buff)
2842 u32 rc, cnt, dir_offset = NVRAM_DIR_OFFSET;
2843 struct code_entry entry;
2846 rc = bnx2x_nvram_read32(bp,
2848 sizeof(entry) * CODE_ENTRY_EXTENDED_DIR_IDX,
2849 (u32 *)&entry, sizeof(entry));
2853 if (!EXTENDED_DIR_EXISTS(entry.code_attribute))
2856 rc = bnx2x_nvram_read32(bp, entry.nvm_start_addr,
2861 dir_offset = entry.nvm_start_addr + 8;
2863 for (i = 0; i < cnt && i < MAX_IMAGES_IN_EXTENDED_DIR; i++) {
2864 rc = bnx2x_test_dir_entry(bp, dir_offset +
2865 sizeof(struct code_entry) * i,
2874 static int bnx2x_test_nvram_dirs(struct bnx2x *bp, u8 *buff)
2876 u32 rc, dir_offset = NVRAM_DIR_OFFSET;
2879 DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM, "NVRAM DIRS CRC test-set\n");
2881 for (i = 0; i < CODE_ENTRY_EXTENDED_DIR_IDX; i++) {
2882 rc = bnx2x_test_dir_entry(bp, dir_offset +
2883 sizeof(struct code_entry) * i,
2889 return bnx2x_test_nvram_ext_dirs(bp, buff);
2897 static int bnx2x_test_nvram_tbl(struct bnx2x *bp,
2898 const struct crc_pair *nvram_tbl, u8 *buf)
2902 for (i = 0; nvram_tbl[i].size; i++) {
2903 int rc = bnx2x_nvram_crc(bp, nvram_tbl[i].offset,
2904 nvram_tbl[i].size, buf);
2906 DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM,
2907 "nvram_tbl[%d] has failed crc test (rc %d)\n",
2916 static int bnx2x_test_nvram(struct bnx2x *bp)
2918 static const struct crc_pair nvram_tbl[] = {
2919 { 0, 0x14 }, /* bootstrap */
2920 { 0x14, 0xec }, /* dir */
2921 { 0x100, 0x350 }, /* manuf_info */
2922 { 0x450, 0xf0 }, /* feature_info */
2923 { 0x640, 0x64 }, /* upgrade_key_info */
2924 { 0x708, 0x70 }, /* manuf_key_info */
2927 static const struct crc_pair nvram_tbl2[] = {
2928 { 0x7e8, 0x350 }, /* manuf_info2 */
2929 { 0xb38, 0xf0 }, /* feature_info */
2940 buf = kmalloc(CRC_BUFF_SIZE, GFP_KERNEL);
2942 DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM, "kmalloc failed\n");
2944 goto test_nvram_exit;
2947 rc = bnx2x_nvram_read32(bp, 0, &magic, sizeof(magic));
2949 DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM,
2950 "magic value read (rc %d)\n", rc);
2951 goto test_nvram_exit;
2954 if (magic != 0x669955aa) {
2955 DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM,
2956 "wrong magic value (0x%08x)\n", magic);
2958 goto test_nvram_exit;
2961 DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM, "Port 0 CRC test-set\n");
2962 rc = bnx2x_test_nvram_tbl(bp, nvram_tbl, buf);
2964 goto test_nvram_exit;
2966 if (!CHIP_IS_E1x(bp) && !CHIP_IS_57811xx(bp)) {
2967 u32 hide = SHMEM_RD(bp, dev_info.shared_hw_config.config2) &
2968 SHARED_HW_CFG_HIDE_PORT1;
2971 DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM,
2972 "Port 1 CRC test-set\n");
2973 rc = bnx2x_test_nvram_tbl(bp, nvram_tbl2, buf);
2975 goto test_nvram_exit;
2979 rc = bnx2x_test_nvram_dirs(bp, buf);
2986 /* Send an EMPTY ramrod on the first queue */
2987 static int bnx2x_test_intr(struct bnx2x *bp)
2989 struct bnx2x_queue_state_params params = {NULL};
2991 if (!netif_running(bp->dev)) {
2992 DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM,
2993 "cannot access eeprom when the interface is down\n");
2997 params.q_obj = &bp->sp_objs->q_obj;
2998 params.cmd = BNX2X_Q_CMD_EMPTY;
3000 __set_bit(RAMROD_COMP_WAIT, ¶ms.ramrod_flags);
3002 return bnx2x_queue_state_change(bp, ¶ms);
3005 static void bnx2x_self_test(struct net_device *dev,
3006 struct ethtool_test *etest, u64 *buf)
3008 struct bnx2x *bp = netdev_priv(dev);
3009 u8 is_serdes, link_up;
3012 if (pci_num_vf(bp->pdev)) {
3014 "VFs are enabled, can not perform self test\n");
3018 if (bp->recovery_state != BNX2X_RECOVERY_DONE) {
3020 "Handling parity error recovery. Try again later\n");
3021 etest->flags |= ETH_TEST_FL_FAILED;
3025 DP(BNX2X_MSG_ETHTOOL,
3026 "Self-test command parameters: offline = %d, external_lb = %d\n",
3027 (etest->flags & ETH_TEST_FL_OFFLINE),
3028 (etest->flags & ETH_TEST_FL_EXTERNAL_LB)>>2);
3030 memset(buf, 0, sizeof(u64) * BNX2X_NUM_TESTS(bp));
3032 if (bnx2x_test_nvram(bp) != 0) {
3037 etest->flags |= ETH_TEST_FL_FAILED;
3040 if (!netif_running(dev)) {
3041 DP(BNX2X_MSG_ETHTOOL, "Interface is down\n");
3045 is_serdes = (bp->link_vars.link_status & LINK_STATUS_SERDES_LINK) > 0;
3046 link_up = bp->link_vars.link_up;
3047 /* offline tests are not supported in MF mode */
3048 if ((etest->flags & ETH_TEST_FL_OFFLINE) && !IS_MF(bp)) {
3049 int port = BP_PORT(bp);
3052 /* save current value of input enable for TX port IF */
3053 val = REG_RD(bp, NIG_REG_EGRESS_UMP0_IN_EN + port*4);
3054 /* disable input for TX port IF */
3055 REG_WR(bp, NIG_REG_EGRESS_UMP0_IN_EN + port*4, 0);
3057 bnx2x_nic_unload(bp, UNLOAD_NORMAL, false);
3058 rc = bnx2x_nic_load(bp, LOAD_DIAG);
3060 etest->flags |= ETH_TEST_FL_FAILED;
3061 DP(BNX2X_MSG_ETHTOOL,
3062 "Can't perform self-test, nic_load (for offline) failed\n");
3066 /* wait until link state is restored */
3067 bnx2x_wait_for_link(bp, 1, is_serdes);
3069 if (bnx2x_test_registers(bp) != 0) {
3071 etest->flags |= ETH_TEST_FL_FAILED;
3073 if (bnx2x_test_memory(bp) != 0) {
3075 etest->flags |= ETH_TEST_FL_FAILED;
3078 buf[2] = bnx2x_test_loopback(bp); /* internal LB */
3080 etest->flags |= ETH_TEST_FL_FAILED;
3082 if (etest->flags & ETH_TEST_FL_EXTERNAL_LB) {
3083 buf[3] = bnx2x_test_ext_loopback(bp); /* external LB */
3085 etest->flags |= ETH_TEST_FL_FAILED;
3086 etest->flags |= ETH_TEST_FL_EXTERNAL_LB_DONE;
3089 bnx2x_nic_unload(bp, UNLOAD_NORMAL, false);
3091 /* restore input for TX port IF */
3092 REG_WR(bp, NIG_REG_EGRESS_UMP0_IN_EN + port*4, val);
3093 rc = bnx2x_nic_load(bp, LOAD_NORMAL);
3095 etest->flags |= ETH_TEST_FL_FAILED;
3096 DP(BNX2X_MSG_ETHTOOL,
3097 "Can't perform self-test, nic_load (for online) failed\n");
3100 /* wait until link state is restored */
3101 bnx2x_wait_for_link(bp, link_up, is_serdes);
3104 if (bnx2x_test_intr(bp) != 0) {
3109 etest->flags |= ETH_TEST_FL_FAILED;
3114 while (bnx2x_link_test(bp, is_serdes) && --cnt)
3123 etest->flags |= ETH_TEST_FL_FAILED;
3127 #define IS_PORT_STAT(i) (bnx2x_stats_arr[i].is_port_stat)
3128 #define HIDE_PORT_STAT(bp) IS_VF(bp)
3130 /* ethtool statistics are displayed for all regular ethernet queues and the
3131 * fcoe L2 queue if not disabled
3133 static int bnx2x_num_stat_queues(struct bnx2x *bp)
3135 return BNX2X_NUM_ETH_QUEUES(bp);
3138 static int bnx2x_get_sset_count(struct net_device *dev, int stringset)
3140 struct bnx2x *bp = netdev_priv(dev);
3141 int i, num_strings = 0;
3143 switch (stringset) {
3146 num_strings = bnx2x_num_stat_queues(bp) *
3150 if (HIDE_PORT_STAT(bp)) {
3151 for (i = 0; i < BNX2X_NUM_STATS; i++)
3152 if (!IS_PORT_STAT(i))
3155 num_strings += BNX2X_NUM_STATS;
3160 return BNX2X_NUM_TESTS(bp);
3162 case ETH_SS_PRIV_FLAGS:
3163 return BNX2X_PRI_FLAG_LEN;
3170 static u32 bnx2x_get_private_flags(struct net_device *dev)
3172 struct bnx2x *bp = netdev_priv(dev);
3175 flags |= (!(bp->flags & NO_ISCSI_FLAG) ? 1 : 0) << BNX2X_PRI_FLAG_ISCSI;
3176 flags |= (!(bp->flags & NO_FCOE_FLAG) ? 1 : 0) << BNX2X_PRI_FLAG_FCOE;
3177 flags |= (!!IS_MF_STORAGE_ONLY(bp)) << BNX2X_PRI_FLAG_STORAGE;
3182 static void bnx2x_get_strings(struct net_device *dev, u32 stringset, u8 *buf)
3184 struct bnx2x *bp = netdev_priv(dev);
3186 char queue_name[MAX_QUEUE_NAME_LEN+1];
3188 switch (stringset) {
3192 for_each_eth_queue(bp, i) {
3193 memset(queue_name, 0, sizeof(queue_name));
3194 snprintf(queue_name, sizeof(queue_name),
3196 for (j = 0; j < BNX2X_NUM_Q_STATS; j++)
3197 snprintf(buf + (k + j)*ETH_GSTRING_LEN,
3199 bnx2x_q_stats_arr[j].string,
3201 k += BNX2X_NUM_Q_STATS;
3205 for (i = 0, j = 0; i < BNX2X_NUM_STATS; i++) {
3206 if (HIDE_PORT_STAT(bp) && IS_PORT_STAT(i))
3208 strcpy(buf + (k + j)*ETH_GSTRING_LEN,
3209 bnx2x_stats_arr[i].string);
3216 /* First 4 tests cannot be done in MF mode */
3221 memcpy(buf, bnx2x_tests_str_arr + start,
3222 ETH_GSTRING_LEN * BNX2X_NUM_TESTS(bp));
3225 case ETH_SS_PRIV_FLAGS:
3226 memcpy(buf, bnx2x_private_arr,
3227 ETH_GSTRING_LEN * BNX2X_PRI_FLAG_LEN);
3232 static void bnx2x_get_ethtool_stats(struct net_device *dev,
3233 struct ethtool_stats *stats, u64 *buf)
3235 struct bnx2x *bp = netdev_priv(dev);
3236 u32 *hw_stats, *offset;
3240 for_each_eth_queue(bp, i) {
3241 hw_stats = (u32 *)&bp->fp_stats[i].eth_q_stats;
3242 for (j = 0; j < BNX2X_NUM_Q_STATS; j++) {
3243 if (bnx2x_q_stats_arr[j].size == 0) {
3244 /* skip this counter */
3248 offset = (hw_stats +
3249 bnx2x_q_stats_arr[j].offset);
3250 if (bnx2x_q_stats_arr[j].size == 4) {
3251 /* 4-byte counter */
3252 buf[k + j] = (u64) *offset;
3255 /* 8-byte counter */
3256 buf[k + j] = HILO_U64(*offset, *(offset + 1));
3258 k += BNX2X_NUM_Q_STATS;
3262 hw_stats = (u32 *)&bp->eth_stats;
3263 for (i = 0, j = 0; i < BNX2X_NUM_STATS; i++) {
3264 if (HIDE_PORT_STAT(bp) && IS_PORT_STAT(i))
3266 if (bnx2x_stats_arr[i].size == 0) {
3267 /* skip this counter */
3272 offset = (hw_stats + bnx2x_stats_arr[i].offset);
3273 if (bnx2x_stats_arr[i].size == 4) {
3274 /* 4-byte counter */
3275 buf[k + j] = (u64) *offset;
3279 /* 8-byte counter */
3280 buf[k + j] = HILO_U64(*offset, *(offset + 1));
3285 static int bnx2x_set_phys_id(struct net_device *dev,
3286 enum ethtool_phys_id_state state)
3288 struct bnx2x *bp = netdev_priv(dev);
3290 if (!bnx2x_is_nvm_accessible(bp)) {
3291 DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM,
3292 "cannot access eeprom when the interface is down\n");
3297 case ETHTOOL_ID_ACTIVE:
3298 return 1; /* cycle on/off once per second */
3301 bnx2x_acquire_phy_lock(bp);
3302 bnx2x_set_led(&bp->link_params, &bp->link_vars,
3303 LED_MODE_ON, SPEED_1000);
3304 bnx2x_release_phy_lock(bp);
3307 case ETHTOOL_ID_OFF:
3308 bnx2x_acquire_phy_lock(bp);
3309 bnx2x_set_led(&bp->link_params, &bp->link_vars,
3310 LED_MODE_FRONT_PANEL_OFF, 0);
3311 bnx2x_release_phy_lock(bp);
3314 case ETHTOOL_ID_INACTIVE:
3315 bnx2x_acquire_phy_lock(bp);
3316 bnx2x_set_led(&bp->link_params, &bp->link_vars,
3318 bp->link_vars.line_speed);
3319 bnx2x_release_phy_lock(bp);
3325 static int bnx2x_get_rss_flags(struct bnx2x *bp, struct ethtool_rxnfc *info)
3327 switch (info->flow_type) {
3330 info->data = RXH_IP_SRC | RXH_IP_DST |
3331 RXH_L4_B_0_1 | RXH_L4_B_2_3;
3334 if (bp->rss_conf_obj.udp_rss_v4)
3335 info->data = RXH_IP_SRC | RXH_IP_DST |
3336 RXH_L4_B_0_1 | RXH_L4_B_2_3;
3338 info->data = RXH_IP_SRC | RXH_IP_DST;
3341 if (bp->rss_conf_obj.udp_rss_v6)
3342 info->data = RXH_IP_SRC | RXH_IP_DST |
3343 RXH_L4_B_0_1 | RXH_L4_B_2_3;
3345 info->data = RXH_IP_SRC | RXH_IP_DST;
3349 info->data = RXH_IP_SRC | RXH_IP_DST;
3359 static int bnx2x_get_rxnfc(struct net_device *dev, struct ethtool_rxnfc *info,
3360 u32 *rules __always_unused)
3362 struct bnx2x *bp = netdev_priv(dev);
3364 switch (info->cmd) {
3365 case ETHTOOL_GRXRINGS:
3366 info->data = BNX2X_NUM_ETH_QUEUES(bp);
3369 return bnx2x_get_rss_flags(bp, info);
3371 DP(BNX2X_MSG_ETHTOOL, "Command parameters not supported\n");
3376 static int bnx2x_set_rss_flags(struct bnx2x *bp, struct ethtool_rxnfc *info)
3378 int udp_rss_requested;
3380 DP(BNX2X_MSG_ETHTOOL,
3381 "Set rss flags command parameters: flow type = %d, data = %llu\n",
3382 info->flow_type, info->data);
3384 switch (info->flow_type) {
3387 /* For TCP only 4-tupple hash is supported */
3388 if (info->data ^ (RXH_IP_SRC | RXH_IP_DST |
3389 RXH_L4_B_0_1 | RXH_L4_B_2_3)) {
3390 DP(BNX2X_MSG_ETHTOOL,
3391 "Command parameters not supported\n");
3398 /* For UDP either 2-tupple hash or 4-tupple hash is supported */
3399 if (info->data == (RXH_IP_SRC | RXH_IP_DST |
3400 RXH_L4_B_0_1 | RXH_L4_B_2_3))
3401 udp_rss_requested = 1;
3402 else if (info->data == (RXH_IP_SRC | RXH_IP_DST))
3403 udp_rss_requested = 0;
3407 if (CHIP_IS_E1x(bp) && udp_rss_requested) {
3408 DP(BNX2X_MSG_ETHTOOL,
3409 "57710, 57711 boards don't support RSS according to UDP 4-tuple\n");
3413 if ((info->flow_type == UDP_V4_FLOW) &&
3414 (bp->rss_conf_obj.udp_rss_v4 != udp_rss_requested)) {
3415 bp->rss_conf_obj.udp_rss_v4 = udp_rss_requested;
3416 DP(BNX2X_MSG_ETHTOOL,
3417 "rss re-configured, UDP 4-tupple %s\n",
3418 udp_rss_requested ? "enabled" : "disabled");
3419 if (bp->state == BNX2X_STATE_OPEN)
3420 return bnx2x_rss(bp, &bp->rss_conf_obj, false,
3422 } else if ((info->flow_type == UDP_V6_FLOW) &&
3423 (bp->rss_conf_obj.udp_rss_v6 != udp_rss_requested)) {
3424 bp->rss_conf_obj.udp_rss_v6 = udp_rss_requested;
3425 DP(BNX2X_MSG_ETHTOOL,
3426 "rss re-configured, UDP 4-tupple %s\n",
3427 udp_rss_requested ? "enabled" : "disabled");
3428 if (bp->state == BNX2X_STATE_OPEN)
3429 return bnx2x_rss(bp, &bp->rss_conf_obj, false,
3436 /* For IP only 2-tupple hash is supported */
3437 if (info->data ^ (RXH_IP_SRC | RXH_IP_DST)) {
3438 DP(BNX2X_MSG_ETHTOOL,
3439 "Command parameters not supported\n");
3445 case AH_ESP_V4_FLOW:
3449 case AH_ESP_V6_FLOW:
3454 /* RSS is not supported for these protocols */
3456 DP(BNX2X_MSG_ETHTOOL,
3457 "Command parameters not supported\n");
3467 static int bnx2x_set_rxnfc(struct net_device *dev, struct ethtool_rxnfc *info)
3469 struct bnx2x *bp = netdev_priv(dev);
3471 switch (info->cmd) {
3473 return bnx2x_set_rss_flags(bp, info);
3475 DP(BNX2X_MSG_ETHTOOL, "Command parameters not supported\n");
3480 static u32 bnx2x_get_rxfh_indir_size(struct net_device *dev)
3482 return T_ETH_INDIRECTION_TABLE_SIZE;
3485 static int bnx2x_get_rxfh(struct net_device *dev, u32 *indir, u8 *key,
3488 struct bnx2x *bp = netdev_priv(dev);
3489 u8 ind_table[T_ETH_INDIRECTION_TABLE_SIZE] = {0};
3493 *hfunc = ETH_RSS_HASH_TOP;
3497 /* Get the current configuration of the RSS indirection table */
3498 bnx2x_get_rss_ind_table(&bp->rss_conf_obj, ind_table);
3501 * We can't use a memcpy() as an internal storage of an
3502 * indirection table is a u8 array while indir->ring_index
3503 * points to an array of u32.
3505 * Indirection table contains the FW Client IDs, so we need to
3506 * align the returned table to the Client ID of the leading RSS
3509 for (i = 0; i < T_ETH_INDIRECTION_TABLE_SIZE; i++)
3510 indir[i] = ind_table[i] - bp->fp->cl_id;
3515 static int bnx2x_set_rxfh(struct net_device *dev, const u32 *indir,
3516 const u8 *key, const u8 hfunc)
3518 struct bnx2x *bp = netdev_priv(dev);
3521 /* We require at least one supported parameter to be changed and no
3522 * change in any of the unsupported parameters
3525 (hfunc != ETH_RSS_HASH_NO_CHANGE && hfunc != ETH_RSS_HASH_TOP))
3531 for (i = 0; i < T_ETH_INDIRECTION_TABLE_SIZE; i++) {
3533 * The same as in bnx2x_get_rxfh: we can't use a memcpy()
3534 * as an internal storage of an indirection table is a u8 array
3535 * while indir->ring_index points to an array of u32.
3537 * Indirection table contains the FW Client IDs, so we need to
3538 * align the received table to the Client ID of the leading RSS
3541 bp->rss_conf_obj.ind_table[i] = indir[i] + bp->fp->cl_id;
3544 if (bp->state == BNX2X_STATE_OPEN)
3545 return bnx2x_config_rss_eth(bp, false);
3551 * bnx2x_get_channels - gets the number of RSS queues.
3554 * @channels: returns the number of max / current queues
3556 static void bnx2x_get_channels(struct net_device *dev,
3557 struct ethtool_channels *channels)
3559 struct bnx2x *bp = netdev_priv(dev);
3561 channels->max_combined = BNX2X_MAX_RSS_COUNT(bp);
3562 channels->combined_count = BNX2X_NUM_ETH_QUEUES(bp);
3566 * bnx2x_change_num_queues - change the number of RSS queues.
3568 * @bp: bnx2x private structure
3569 * @num_rss: rss count
3571 * Re-configure interrupt mode to get the new number of MSI-X
3572 * vectors and re-add NAPI objects.
3574 static void bnx2x_change_num_queues(struct bnx2x *bp, int num_rss)
3576 bnx2x_disable_msi(bp);
3577 bp->num_ethernet_queues = num_rss;
3578 bp->num_queues = bp->num_ethernet_queues + bp->num_cnic_queues;
3579 BNX2X_DEV_INFO("set number of queues to %d\n", bp->num_queues);
3580 bnx2x_set_int_mode(bp);
3584 * bnx2x_set_channels - sets the number of RSS queues.
3587 * @channels: includes the number of queues requested
3589 static int bnx2x_set_channels(struct net_device *dev,
3590 struct ethtool_channels *channels)
3592 struct bnx2x *bp = netdev_priv(dev);
3594 DP(BNX2X_MSG_ETHTOOL,
3595 "set-channels command parameters: rx = %d, tx = %d, other = %d, combined = %d\n",
3596 channels->rx_count, channels->tx_count, channels->other_count,
3597 channels->combined_count);
3599 if (pci_num_vf(bp->pdev)) {
3600 DP(BNX2X_MSG_IOV, "VFs are enabled, can not set channels\n");
3604 /* We don't support separate rx / tx channels.
3605 * We don't allow setting 'other' channels.
3607 if (channels->rx_count || channels->tx_count || channels->other_count
3608 || (channels->combined_count == 0) ||
3609 (channels->combined_count > BNX2X_MAX_RSS_COUNT(bp))) {
3610 DP(BNX2X_MSG_ETHTOOL, "command parameters not supported\n");
3614 /* Check if there was a change in the active parameters */
3615 if (channels->combined_count == BNX2X_NUM_ETH_QUEUES(bp)) {
3616 DP(BNX2X_MSG_ETHTOOL, "No change in active parameters\n");
3620 /* Set the requested number of queues in bp context.
3621 * Note that the actual number of queues created during load may be
3622 * less than requested if memory is low.
3624 if (unlikely(!netif_running(dev))) {
3625 bnx2x_change_num_queues(bp, channels->combined_count);
3628 bnx2x_nic_unload(bp, UNLOAD_NORMAL, true);
3629 bnx2x_change_num_queues(bp, channels->combined_count);
3630 return bnx2x_nic_load(bp, LOAD_NORMAL);
3633 static int bnx2x_get_ts_info(struct net_device *dev,
3634 struct ethtool_ts_info *info)
3636 struct bnx2x *bp = netdev_priv(dev);
3638 if (bp->flags & PTP_SUPPORTED) {
3639 info->so_timestamping = SOF_TIMESTAMPING_TX_SOFTWARE |
3640 SOF_TIMESTAMPING_RX_SOFTWARE |
3641 SOF_TIMESTAMPING_SOFTWARE |
3642 SOF_TIMESTAMPING_TX_HARDWARE |
3643 SOF_TIMESTAMPING_RX_HARDWARE |
3644 SOF_TIMESTAMPING_RAW_HARDWARE;
3647 info->phc_index = ptp_clock_index(bp->ptp_clock);
3649 info->phc_index = -1;
3651 info->rx_filters = (1 << HWTSTAMP_FILTER_NONE) |
3652 (1 << HWTSTAMP_FILTER_PTP_V1_L4_EVENT) |
3653 (1 << HWTSTAMP_FILTER_PTP_V2_L4_EVENT) |
3654 (1 << HWTSTAMP_FILTER_PTP_V2_EVENT);
3656 info->tx_types = (1 << HWTSTAMP_TX_OFF)|(1 << HWTSTAMP_TX_ON);
3661 return ethtool_op_get_ts_info(dev, info);
3664 static const struct ethtool_ops bnx2x_ethtool_ops = {
3665 .supported_coalesce_params = ETHTOOL_COALESCE_USECS,
3666 .get_drvinfo = bnx2x_get_drvinfo,
3667 .get_regs_len = bnx2x_get_regs_len,
3668 .get_regs = bnx2x_get_regs,
3669 .get_dump_flag = bnx2x_get_dump_flag,
3670 .get_dump_data = bnx2x_get_dump_data,
3671 .set_dump = bnx2x_set_dump,
3672 .get_wol = bnx2x_get_wol,
3673 .set_wol = bnx2x_set_wol,
3674 .get_msglevel = bnx2x_get_msglevel,
3675 .set_msglevel = bnx2x_set_msglevel,
3676 .nway_reset = bnx2x_nway_reset,
3677 .get_link = bnx2x_get_link,
3678 .get_eeprom_len = bnx2x_get_eeprom_len,
3679 .get_eeprom = bnx2x_get_eeprom,
3680 .set_eeprom = bnx2x_set_eeprom,
3681 .get_coalesce = bnx2x_get_coalesce,
3682 .set_coalesce = bnx2x_set_coalesce,
3683 .get_ringparam = bnx2x_get_ringparam,
3684 .set_ringparam = bnx2x_set_ringparam,
3685 .get_pauseparam = bnx2x_get_pauseparam,
3686 .set_pauseparam = bnx2x_set_pauseparam,
3687 .self_test = bnx2x_self_test,
3688 .get_sset_count = bnx2x_get_sset_count,
3689 .get_priv_flags = bnx2x_get_private_flags,
3690 .get_strings = bnx2x_get_strings,
3691 .set_phys_id = bnx2x_set_phys_id,
3692 .get_ethtool_stats = bnx2x_get_ethtool_stats,
3693 .get_rxnfc = bnx2x_get_rxnfc,
3694 .set_rxnfc = bnx2x_set_rxnfc,
3695 .get_rxfh_indir_size = bnx2x_get_rxfh_indir_size,
3696 .get_rxfh = bnx2x_get_rxfh,
3697 .set_rxfh = bnx2x_set_rxfh,
3698 .get_channels = bnx2x_get_channels,
3699 .set_channels = bnx2x_set_channels,
3700 .get_module_info = bnx2x_get_module_info,
3701 .get_module_eeprom = bnx2x_get_module_eeprom,
3702 .get_eee = bnx2x_get_eee,
3703 .set_eee = bnx2x_set_eee,
3704 .get_ts_info = bnx2x_get_ts_info,
3705 .get_link_ksettings = bnx2x_get_link_ksettings,
3706 .set_link_ksettings = bnx2x_set_link_ksettings,
3709 static const struct ethtool_ops bnx2x_vf_ethtool_ops = {
3710 .get_drvinfo = bnx2x_get_drvinfo,
3711 .get_msglevel = bnx2x_get_msglevel,
3712 .set_msglevel = bnx2x_set_msglevel,
3713 .get_link = bnx2x_get_link,
3714 .get_coalesce = bnx2x_get_coalesce,
3715 .get_ringparam = bnx2x_get_ringparam,
3716 .set_ringparam = bnx2x_set_ringparam,
3717 .get_sset_count = bnx2x_get_sset_count,
3718 .get_strings = bnx2x_get_strings,
3719 .get_ethtool_stats = bnx2x_get_ethtool_stats,
3720 .get_rxnfc = bnx2x_get_rxnfc,
3721 .set_rxnfc = bnx2x_set_rxnfc,
3722 .get_rxfh_indir_size = bnx2x_get_rxfh_indir_size,
3723 .get_rxfh = bnx2x_get_rxfh,
3724 .set_rxfh = bnx2x_set_rxfh,
3725 .get_channels = bnx2x_get_channels,
3726 .set_channels = bnx2x_set_channels,
3727 .get_link_ksettings = bnx2x_get_vf_link_ksettings,
3730 void bnx2x_set_ethtool_ops(struct bnx2x *bp, struct net_device *netdev)
3732 netdev->ethtool_ops = (IS_PF(bp)) ?
3733 &bnx2x_ethtool_ops : &bnx2x_vf_ethtool_ops;