1 /* bnx2x.h: Broadcom Everest network driver.
3 * Copyright (c) 2007-2013 Broadcom Corporation
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation.
9 * Maintained by: Eilon Greenstein <eilong@broadcom.com>
10 * Written by: Eliezer Tamir
11 * Based on code from Michael Chan's bnx2 driver
17 #include <linux/pci.h>
18 #include <linux/netdevice.h>
19 #include <linux/dma-mapping.h>
20 #include <linux/types.h>
21 #include <linux/pci_regs.h>
23 /* compilation time flags */
25 /* define this to make the driver freeze on error to allow getting debug info
26 * (you will need to reboot afterwards) */
27 /* #define BNX2X_STOP_ON_ERROR */
29 #define DRV_MODULE_VERSION "1.78.17-0"
30 #define DRV_MODULE_RELDATE "2013/04/11"
31 #define BNX2X_BC_VER 0x040200
33 #if defined(CONFIG_DCB)
37 #include "bnx2x_hsi.h"
39 #include "../cnic_if.h"
41 #define BNX2X_MIN_MSIX_VEC_CNT(bp) ((bp)->min_msix_vec_cnt)
43 #include <linux/mdio.h>
45 #include "bnx2x_reg.h"
46 #include "bnx2x_fw_defs.h"
47 #include "bnx2x_mfw_req.h"
48 #include "bnx2x_link.h"
50 #include "bnx2x_dcb.h"
51 #include "bnx2x_stats.h"
52 #include "bnx2x_vfpf.h"
60 /* error/debug prints */
62 #define DRV_MODULE_NAME "bnx2x"
64 /* for messages that are currently off */
65 #define BNX2X_MSG_OFF 0x0
66 #define BNX2X_MSG_MCP 0x0010000 /* was: NETIF_MSG_HW */
67 #define BNX2X_MSG_STATS 0x0020000 /* was: NETIF_MSG_TIMER */
68 #define BNX2X_MSG_NVM 0x0040000 /* was: NETIF_MSG_HW */
69 #define BNX2X_MSG_DMAE 0x0080000 /* was: NETIF_MSG_HW */
70 #define BNX2X_MSG_SP 0x0100000 /* was: NETIF_MSG_INTR */
71 #define BNX2X_MSG_FP 0x0200000 /* was: NETIF_MSG_INTR */
72 #define BNX2X_MSG_IOV 0x0800000
73 #define BNX2X_MSG_IDLE 0x2000000 /* used for idle check*/
74 #define BNX2X_MSG_ETHTOOL 0x4000000
75 #define BNX2X_MSG_DCB 0x8000000
77 /* regular debug print */
78 #define DP(__mask, fmt, ...) \
80 if (unlikely(bp->msg_enable & (__mask))) \
81 pr_notice("[%s:%d(%s)]" fmt, \
83 bp->dev ? (bp->dev->name) : "?", \
87 #define DP_CONT(__mask, fmt, ...) \
89 if (unlikely(bp->msg_enable & (__mask))) \
90 pr_cont(fmt, ##__VA_ARGS__); \
93 /* errors debug print */
94 #define BNX2X_DBG_ERR(fmt, ...) \
96 if (unlikely(netif_msg_probe(bp))) \
97 pr_err("[%s:%d(%s)]" fmt, \
99 bp->dev ? (bp->dev->name) : "?", \
103 /* for errors (never masked) */
104 #define BNX2X_ERR(fmt, ...) \
106 pr_err("[%s:%d(%s)]" fmt, \
107 __func__, __LINE__, \
108 bp->dev ? (bp->dev->name) : "?", \
112 #define BNX2X_ERROR(fmt, ...) \
113 pr_err("[%s:%d]" fmt, __func__, __LINE__, ##__VA_ARGS__)
115 /* before we have a dev->name use dev_info() */
116 #define BNX2X_DEV_INFO(fmt, ...) \
118 if (unlikely(netif_msg_probe(bp))) \
119 dev_info(&bp->pdev->dev, fmt, ##__VA_ARGS__); \
123 void bnx2x_panic_dump(struct bnx2x *bp, bool disable_int);
124 #ifdef BNX2X_STOP_ON_ERROR
125 #define bnx2x_panic() \
128 BNX2X_ERR("driver assert\n"); \
129 bnx2x_panic_dump(bp, true); \
132 #define bnx2x_panic() \
135 BNX2X_ERR("driver assert\n"); \
136 bnx2x_panic_dump(bp, false); \
140 #define bnx2x_mc_addr(ha) ((ha)->addr)
141 #define bnx2x_uc_addr(ha) ((ha)->addr)
143 #define U64_LO(x) ((u32)(((u64)(x)) & 0xffffffff))
144 #define U64_HI(x) ((u32)(((u64)(x)) >> 32))
145 #define HILO_U64(hi, lo) ((((u64)(hi)) << 32) + (lo))
147 #define REG_ADDR(bp, offset) ((bp->regview) + (offset))
149 #define REG_RD(bp, offset) readl(REG_ADDR(bp, offset))
150 #define REG_RD8(bp, offset) readb(REG_ADDR(bp, offset))
151 #define REG_RD16(bp, offset) readw(REG_ADDR(bp, offset))
153 #define REG_WR(bp, offset, val) writel((u32)val, REG_ADDR(bp, offset))
154 #define REG_WR8(bp, offset, val) writeb((u8)val, REG_ADDR(bp, offset))
155 #define REG_WR16(bp, offset, val) writew((u16)val, REG_ADDR(bp, offset))
157 #define REG_RD_IND(bp, offset) bnx2x_reg_rd_ind(bp, offset)
158 #define REG_WR_IND(bp, offset, val) bnx2x_reg_wr_ind(bp, offset, val)
160 #define REG_RD_DMAE(bp, offset, valp, len32) \
162 bnx2x_read_dmae(bp, offset, len32);\
163 memcpy(valp, bnx2x_sp(bp, wb_data[0]), (len32) * 4); \
166 #define REG_WR_DMAE(bp, offset, valp, len32) \
168 memcpy(bnx2x_sp(bp, wb_data[0]), valp, (len32) * 4); \
169 bnx2x_write_dmae(bp, bnx2x_sp_mapping(bp, wb_data), \
173 #define REG_WR_DMAE_LEN(bp, offset, valp, len32) \
174 REG_WR_DMAE(bp, offset, valp, len32)
176 #define VIRT_WR_DMAE_LEN(bp, data, addr, len32, le32_swap) \
178 memcpy(GUNZIP_BUF(bp), data, (len32) * 4); \
179 bnx2x_write_big_buf_wb(bp, addr, len32); \
182 #define SHMEM_ADDR(bp, field) (bp->common.shmem_base + \
183 offsetof(struct shmem_region, field))
184 #define SHMEM_RD(bp, field) REG_RD(bp, SHMEM_ADDR(bp, field))
185 #define SHMEM_WR(bp, field, val) REG_WR(bp, SHMEM_ADDR(bp, field), val)
187 #define SHMEM2_ADDR(bp, field) (bp->common.shmem2_base + \
188 offsetof(struct shmem2_region, field))
189 #define SHMEM2_RD(bp, field) REG_RD(bp, SHMEM2_ADDR(bp, field))
190 #define SHMEM2_WR(bp, field, val) REG_WR(bp, SHMEM2_ADDR(bp, field), val)
191 #define MF_CFG_ADDR(bp, field) (bp->common.mf_cfg_base + \
192 offsetof(struct mf_cfg, field))
193 #define MF2_CFG_ADDR(bp, field) (bp->common.mf2_cfg_base + \
194 offsetof(struct mf2_cfg, field))
196 #define MF_CFG_RD(bp, field) REG_RD(bp, MF_CFG_ADDR(bp, field))
197 #define MF_CFG_WR(bp, field, val) REG_WR(bp,\
198 MF_CFG_ADDR(bp, field), (val))
199 #define MF2_CFG_RD(bp, field) REG_RD(bp, MF2_CFG_ADDR(bp, field))
201 #define SHMEM2_HAS(bp, field) ((bp)->common.shmem2_base && \
202 (SHMEM2_RD((bp), size) > \
203 offsetof(struct shmem2_region, field)))
205 #define EMAC_RD(bp, reg) REG_RD(bp, emac_base + reg)
206 #define EMAC_WR(bp, reg, val) REG_WR(bp, emac_base + reg, val)
210 /* General SP events - stats query, cfc delete, etc */
211 #define HC_SP_INDEX_ETH_DEF_CONS 3
214 #define HC_SP_INDEX_EQ_CONS 7
216 /* FCoE L2 connection completions */
217 #define HC_SP_INDEX_ETH_FCOE_TX_CQ_CONS 6
218 #define HC_SP_INDEX_ETH_FCOE_RX_CQ_CONS 4
220 #define HC_SP_INDEX_ETH_ISCSI_CQ_CONS 5
221 #define HC_SP_INDEX_ETH_ISCSI_RX_CQ_CONS 1
223 /* Special clients parameters */
227 #define BNX2X_FCOE_L2_RX_INDEX \
228 (&bp->def_status_blk->sp_sb.\
229 index_values[HC_SP_INDEX_ETH_FCOE_RX_CQ_CONS])
231 #define BNX2X_FCOE_L2_TX_INDEX \
232 (&bp->def_status_blk->sp_sb.\
233 index_values[HC_SP_INDEX_ETH_FCOE_TX_CQ_CONS])
237 * CLIDs below is a CLID for func 0, then the CLID for other
238 * functions will be calculated by the formula:
240 * FUNC_N_CLID_X = N * NUM_SPECIAL_CLIENTS + FUNC_0_CLID_X
244 BNX2X_ISCSI_ETH_CL_ID_IDX,
245 BNX2X_FCOE_ETH_CL_ID_IDX,
246 BNX2X_MAX_CNIC_ETH_CL_ID_IDX,
249 /* use a value high enough to be above all the PFs, which has least significant
250 * nibble as 8, so when cnic needs to come up with a CID for UIO to use to
251 * calculate doorbell address according to old doorbell configuration scheme
252 * (db_msg_sz 1 << 7 * cid + 0x40 DPM offset) it can come up with a valid number
253 * We must avoid coming up with cid 8 for iscsi since according to this method
254 * the designated UIO cid will come out 0 and it has a special handling for that
255 * case which doesn't suit us. Therefore will will cieling to closes cid which
256 * has least signigifcant nibble 8 and if it is 8 we will move forward to 0x18.
259 #define BNX2X_1st_NON_L2_ETH_CID(bp) (BNX2X_NUM_NON_CNIC_QUEUES(bp) * \
261 /* amount of cids traversed by UIO's DPM addition to doorbell */
263 /* roundup to DPM offset */
264 #define UIO_ROUNDUP(bp) (roundup(BNX2X_1st_NON_L2_ETH_CID(bp), \
266 /* offset to nearest value which has lsb nibble matching DPM */
267 #define UIO_CID_OFFSET(bp) ((UIO_ROUNDUP(bp) + UIO_DPM) % \
269 /* add offset to rounded-up cid to get a value which could be used with UIO */
270 #define UIO_DPM_ALIGN(bp) (UIO_ROUNDUP(bp) + UIO_CID_OFFSET(bp))
271 /* but wait - avoid UIO special case for cid 0 */
272 #define UIO_DPM_CID0_OFFSET(bp) ((UIO_DPM * 2) * \
273 (UIO_DPM_ALIGN(bp) == UIO_DPM))
274 /* Properly DPM aligned CID dajusted to cid 0 secal case */
275 #define BNX2X_CNIC_START_ETH_CID(bp) (UIO_DPM_ALIGN(bp) + \
276 (UIO_DPM_CID0_OFFSET(bp)))
277 /* how many cids were wasted - need this value for cid allocation */
278 #define UIO_CID_PAD(bp) (BNX2X_CNIC_START_ETH_CID(bp) - \
279 BNX2X_1st_NON_L2_ETH_CID(bp))
281 #define BNX2X_ISCSI_ETH_CID(bp) (BNX2X_CNIC_START_ETH_CID(bp))
283 #define BNX2X_FCOE_ETH_CID(bp) (BNX2X_CNIC_START_ETH_CID(bp) + 1)
285 #define CNIC_SUPPORT(bp) ((bp)->cnic_support)
286 #define CNIC_ENABLED(bp) ((bp)->cnic_enabled)
287 #define CNIC_LOADED(bp) ((bp)->cnic_loaded)
288 #define FCOE_INIT(bp) ((bp)->fcoe_init)
290 #define AEU_IN_ATTN_BITS_PXPPCICLOCKCLIENT_PARITY_ERROR \
291 AEU_INPUTS_ATTN_BITS_PXPPCICLOCKCLIENT_PARITY_ERROR
296 /* defines for multiple tx priority indices */
297 #define FIRST_TX_ONLY_COS_INDEX 1
298 #define FIRST_TX_COS_INDEX 0
300 /* rules for calculating the cids of tx-only connections */
301 #define CID_TO_FP(cid, bp) ((cid) % BNX2X_NUM_NON_CNIC_QUEUES(bp))
302 #define CID_COS_TO_TX_ONLY_CID(cid, cos, bp) \
303 (cid + cos * BNX2X_NUM_NON_CNIC_QUEUES(bp))
305 /* fp index inside class of service range */
306 #define FP_COS_TO_TXQ(fp, cos, bp) \
307 ((fp)->index + cos * BNX2X_NUM_NON_CNIC_QUEUES(bp))
309 /* Indexes for transmission queues array:
310 * txdata for RSS i CoS j is at location i + (j * num of RSS)
311 * txdata for FCoE (if exist) is at location max cos * num of RSS
312 * txdata for FWD (if exist) is one location after FCoE
313 * txdata for OOO (if exist) is one location after FWD
320 #define MAX_ETH_TXQ_IDX(bp) (BNX2X_NUM_NON_CNIC_QUEUES(bp) * (bp)->max_cos)
321 #define FCOE_TXQ_IDX(bp) (MAX_ETH_TXQ_IDX(bp) + FCOE_TXQ_IDX_OFFSET)
325 * This driver uses new build_skb() API :
326 * RX ring buffer contains pointer to kmalloc() data only,
327 * skb are built only after Hardware filled the frame.
331 DEFINE_DMA_UNMAP_ADDR(mapping);
338 /* Set on the first BD descriptor when there is a split BD */
339 #define BNX2X_TSO_SPLIT_BD (1<<0)
344 DEFINE_DMA_UNMAP_ADDR(mapping);
348 struct doorbell_set_prod data;
352 /* dropless fc FW/HW related params */
353 #define BRB_SIZE(bp) (CHIP_IS_E3(bp) ? 1024 : 512)
354 #define MAX_AGG_QS(bp) (CHIP_IS_E1(bp) ? \
355 ETH_MAX_AGGREGATION_QUEUES_E1 :\
356 ETH_MAX_AGGREGATION_QUEUES_E1H_E2)
357 #define FW_DROP_LEVEL(bp) (3 + MAX_SPQ_PENDING + MAX_AGG_QS(bp))
358 #define FW_PREFETCH_CNT 16
359 #define DROPLESS_FC_HEADROOM 100
362 #define BCM_PAGE_SHIFT 12
363 #define BCM_PAGE_SIZE (1 << BCM_PAGE_SHIFT)
364 #define BCM_PAGE_MASK (~(BCM_PAGE_SIZE - 1))
365 #define BCM_PAGE_ALIGN(addr) (((addr) + BCM_PAGE_SIZE - 1) & BCM_PAGE_MASK)
367 #define PAGES_PER_SGE_SHIFT 0
368 #define PAGES_PER_SGE (1 << PAGES_PER_SGE_SHIFT)
369 #define SGE_PAGE_SIZE PAGE_SIZE
370 #define SGE_PAGE_SHIFT PAGE_SHIFT
371 #define SGE_PAGE_ALIGN(addr) PAGE_ALIGN((typeof(PAGE_SIZE))(addr))
372 #define SGE_PAGES (SGE_PAGE_SIZE * PAGES_PER_SGE)
373 #define TPA_AGG_SIZE min_t(u32, (min_t(u32, 8, MAX_SKB_FRAGS) * \
376 /* SGE ring related macros */
377 #define NUM_RX_SGE_PAGES 2
378 #define RX_SGE_CNT (BCM_PAGE_SIZE / sizeof(struct eth_rx_sge))
379 #define NEXT_PAGE_SGE_DESC_CNT 2
380 #define MAX_RX_SGE_CNT (RX_SGE_CNT - NEXT_PAGE_SGE_DESC_CNT)
381 /* RX_SGE_CNT is promised to be a power of 2 */
382 #define RX_SGE_MASK (RX_SGE_CNT - 1)
383 #define NUM_RX_SGE (RX_SGE_CNT * NUM_RX_SGE_PAGES)
384 #define MAX_RX_SGE (NUM_RX_SGE - 1)
385 #define NEXT_SGE_IDX(x) ((((x) & RX_SGE_MASK) == \
386 (MAX_RX_SGE_CNT - 1)) ? \
387 (x) + 1 + NEXT_PAGE_SGE_DESC_CNT : \
389 #define RX_SGE(x) ((x) & MAX_RX_SGE)
392 * Number of required SGEs is the sum of two:
393 * 1. Number of possible opened aggregations (next packet for
394 * these aggregations will probably consume SGE immediately)
395 * 2. Rest of BRB blocks divided by 2 (block will consume new SGE only
396 * after placement on BD for new TPA aggregation)
398 * Takes into account NEXT_PAGE_SGE_DESC_CNT "next" elements on each page
400 #define NUM_SGE_REQ (MAX_AGG_QS(bp) + \
401 (BRB_SIZE(bp) - MAX_AGG_QS(bp)) / 2)
402 #define NUM_SGE_PG_REQ ((NUM_SGE_REQ + MAX_RX_SGE_CNT - 1) / \
404 #define SGE_TH_LO(bp) (NUM_SGE_REQ + \
405 NUM_SGE_PG_REQ * NEXT_PAGE_SGE_DESC_CNT)
406 #define SGE_TH_HI(bp) (SGE_TH_LO(bp) + DROPLESS_FC_HEADROOM)
408 /* Manipulate a bit vector defined as an array of u64 */
410 /* Number of bits in one sge_mask array element */
411 #define BIT_VEC64_ELEM_SZ 64
412 #define BIT_VEC64_ELEM_SHIFT 6
413 #define BIT_VEC64_ELEM_MASK ((u64)BIT_VEC64_ELEM_SZ - 1)
415 #define __BIT_VEC64_SET_BIT(el, bit) \
417 el = ((el) | ((u64)0x1 << (bit))); \
420 #define __BIT_VEC64_CLEAR_BIT(el, bit) \
422 el = ((el) & (~((u64)0x1 << (bit)))); \
425 #define BIT_VEC64_SET_BIT(vec64, idx) \
426 __BIT_VEC64_SET_BIT((vec64)[(idx) >> BIT_VEC64_ELEM_SHIFT], \
427 (idx) & BIT_VEC64_ELEM_MASK)
429 #define BIT_VEC64_CLEAR_BIT(vec64, idx) \
430 __BIT_VEC64_CLEAR_BIT((vec64)[(idx) >> BIT_VEC64_ELEM_SHIFT], \
431 (idx) & BIT_VEC64_ELEM_MASK)
433 #define BIT_VEC64_TEST_BIT(vec64, idx) \
434 (((vec64)[(idx) >> BIT_VEC64_ELEM_SHIFT] >> \
435 ((idx) & BIT_VEC64_ELEM_MASK)) & 0x1)
437 /* Creates a bitmask of all ones in less significant bits.
438 idx - index of the most significant bit in the created mask */
439 #define BIT_VEC64_ONES_MASK(idx) \
440 (((u64)0x1 << (((idx) & BIT_VEC64_ELEM_MASK) + 1)) - 1)
441 #define BIT_VEC64_ELEM_ONE_MASK ((u64)(~0))
443 /*******************************************************/
445 /* Number of u64 elements in SGE mask array */
446 #define RX_SGE_MASK_LEN (NUM_RX_SGE / BIT_VEC64_ELEM_SZ)
447 #define RX_SGE_MASK_LEN_MASK (RX_SGE_MASK_LEN - 1)
448 #define NEXT_SGE_MASK_ELEM(el) (((el) + 1) & RX_SGE_MASK_LEN_MASK)
450 union host_hc_status_block {
451 /* pointer to fp status block e1x */
452 struct host_hc_status_block_e1x *e1x_sb;
453 /* pointer to fp status block e2 */
454 struct host_hc_status_block_e2 *e2_sb;
457 struct bnx2x_agg_info {
459 * First aggregation buffer is a data buffer, the following - are pages.
460 * We will preallocate the data buffer for each aggregation when
461 * we open the interface and will replace the BD at the consumer
462 * with this one when we receive the TPA_START CQE in order to
463 * keep the Rx BD ring consistent.
465 struct sw_rx_bd first_buf;
467 #define BNX2X_TPA_START 1
468 #define BNX2X_TPA_STOP 2
469 #define BNX2X_TPA_ERROR 3
480 #define Q_STATS_OFFSET32(stat_name) \
481 (offsetof(struct bnx2x_eth_q_stats, stat_name) / 4)
483 struct bnx2x_fp_txdata {
485 struct sw_tx_bd *tx_buf_ring;
487 union eth_tx_bd_types *tx_desc_ring;
488 dma_addr_t tx_desc_mapping;
499 unsigned long tx_pkt;
504 struct bnx2x_fastpath *parent_fp;
508 enum bnx2x_tpa_mode_t {
513 struct bnx2x_fastpath {
514 struct bnx2x *bp; /* parent */
516 struct napi_struct napi;
518 #ifdef CONFIG_NET_RX_BUSY_POLL
520 #define BNX2X_FP_STATE_IDLE 0
521 #define BNX2X_FP_STATE_NAPI (1 << 0) /* NAPI owns this FP */
522 #define BNX2X_FP_STATE_POLL (1 << 1) /* poll owns this FP */
523 #define BNX2X_FP_STATE_DISABLED (1 << 2)
524 #define BNX2X_FP_STATE_NAPI_YIELD (1 << 3) /* NAPI yielded this FP */
525 #define BNX2X_FP_STATE_POLL_YIELD (1 << 4) /* poll yielded this FP */
526 #define BNX2X_FP_OWNED (BNX2X_FP_STATE_NAPI | BNX2X_FP_STATE_POLL)
527 #define BNX2X_FP_YIELD (BNX2X_FP_STATE_NAPI_YIELD | BNX2X_FP_STATE_POLL_YIELD)
528 #define BNX2X_FP_LOCKED (BNX2X_FP_OWNED | BNX2X_FP_STATE_DISABLED)
529 #define BNX2X_FP_USER_PEND (BNX2X_FP_STATE_POLL | BNX2X_FP_STATE_POLL_YIELD)
532 #endif /* CONFIG_NET_RX_BUSY_POLL */
534 union host_hc_status_block status_blk;
535 /* chip independent shortcuts into sb structure */
536 __le16 *sb_index_values;
537 __le16 *sb_running_index;
538 /* chip independent shortcut into rx_prods_offset memory */
539 u32 ustorm_rx_prods_offset;
542 u32 rx_frag_size; /* 0 if kmalloced(), or rx_buf_size + NET_SKB_PAD */
543 dma_addr_t status_blk_mapping;
545 enum bnx2x_tpa_mode_t mode;
547 u8 max_cos; /* actual number of active tx coses */
548 struct bnx2x_fp_txdata *txdata_ptr[BNX2X_MULTI_TX_COS];
550 struct sw_rx_bd *rx_buf_ring; /* BDs mappings ring */
551 struct sw_rx_page *rx_page_ring; /* SGE pages mappings ring */
553 struct eth_rx_bd *rx_desc_ring;
554 dma_addr_t rx_desc_mapping;
556 union eth_rx_cqe *rx_comp_ring;
557 dma_addr_t rx_comp_mapping;
560 struct eth_rx_sge *rx_sge_ring;
561 dma_addr_t rx_sge_mapping;
563 u64 sge_mask[RX_SGE_MASK_LEN];
569 u8 index; /* number in fp array */
570 u8 rx_queue; /* index for skb_record */
571 u8 cl_id; /* eth client id */
573 u8 fw_sb_id; /* status block number in FW */
574 u8 igu_sb_id; /* status block number in HW */
581 /* The last maximal completed SGE */
584 unsigned long rx_pkt,
588 struct bnx2x_agg_info *tpa_info;
590 #ifdef BNX2X_STOP_ON_ERROR
593 /* The size is calculated using the following:
594 sizeof name field from netdev structure +
596 4 (for the digits and to make it DWORD aligned) */
597 #define FP_NAME_SIZE (sizeof(((struct net_device *)0)->name) + 8)
598 char name[FP_NAME_SIZE];
601 #define bnx2x_fp(bp, nr, var) ((bp)->fp[(nr)].var)
602 #define bnx2x_sp_obj(bp, fp) ((bp)->sp_objs[(fp)->index])
603 #define bnx2x_fp_stats(bp, fp) (&((bp)->fp_stats[(fp)->index]))
604 #define bnx2x_fp_qstats(bp, fp) (&((bp)->fp_stats[(fp)->index].eth_q_stats))
606 #ifdef CONFIG_NET_RX_BUSY_POLL
607 static inline void bnx2x_fp_init_lock(struct bnx2x_fastpath *fp)
609 spin_lock_init(&fp->lock);
610 fp->state = BNX2X_FP_STATE_IDLE;
613 /* called from the device poll routine to get ownership of a FP */
614 static inline bool bnx2x_fp_lock_napi(struct bnx2x_fastpath *fp)
618 spin_lock_bh(&fp->lock);
619 if (fp->state & BNX2X_FP_LOCKED) {
620 WARN_ON(fp->state & BNX2X_FP_STATE_NAPI);
621 fp->state |= BNX2X_FP_STATE_NAPI_YIELD;
624 /* we don't care if someone yielded */
625 fp->state = BNX2X_FP_STATE_NAPI;
627 spin_unlock_bh(&fp->lock);
631 /* returns true is someone tried to get the FP while napi had it */
632 static inline bool bnx2x_fp_unlock_napi(struct bnx2x_fastpath *fp)
636 spin_lock_bh(&fp->lock);
638 (BNX2X_FP_STATE_POLL | BNX2X_FP_STATE_NAPI_YIELD));
640 if (fp->state & BNX2X_FP_STATE_POLL_YIELD)
643 /* state ==> idle, unless currently disabled */
644 fp->state &= BNX2X_FP_STATE_DISABLED;
645 spin_unlock_bh(&fp->lock);
649 /* called from bnx2x_low_latency_poll() */
650 static inline bool bnx2x_fp_lock_poll(struct bnx2x_fastpath *fp)
654 spin_lock_bh(&fp->lock);
655 if ((fp->state & BNX2X_FP_LOCKED)) {
656 fp->state |= BNX2X_FP_STATE_POLL_YIELD;
659 /* preserve yield marks */
660 fp->state |= BNX2X_FP_STATE_POLL;
662 spin_unlock_bh(&fp->lock);
666 /* returns true if someone tried to get the FP while it was locked */
667 static inline bool bnx2x_fp_unlock_poll(struct bnx2x_fastpath *fp)
671 spin_lock_bh(&fp->lock);
672 WARN_ON(fp->state & BNX2X_FP_STATE_NAPI);
674 if (fp->state & BNX2X_FP_STATE_POLL_YIELD)
677 /* state ==> idle, unless currently disabled */
678 fp->state &= BNX2X_FP_STATE_DISABLED;
679 spin_unlock_bh(&fp->lock);
683 /* true if a socket is polling, even if it did not get the lock */
684 static inline bool bnx2x_fp_ll_polling(struct bnx2x_fastpath *fp)
686 WARN_ON(!(fp->state & BNX2X_FP_OWNED));
687 return fp->state & BNX2X_FP_USER_PEND;
690 /* false if fp is currently owned */
691 static inline bool bnx2x_fp_ll_disable(struct bnx2x_fastpath *fp)
695 spin_lock_bh(&fp->lock);
696 if (fp->state & BNX2X_FP_OWNED)
698 fp->state |= BNX2X_FP_STATE_DISABLED;
699 spin_unlock_bh(&fp->lock);
704 static inline void bnx2x_fp_init_lock(struct bnx2x_fastpath *fp)
708 static inline bool bnx2x_fp_lock_napi(struct bnx2x_fastpath *fp)
713 static inline bool bnx2x_fp_unlock_napi(struct bnx2x_fastpath *fp)
718 static inline bool bnx2x_fp_lock_poll(struct bnx2x_fastpath *fp)
723 static inline bool bnx2x_fp_unlock_poll(struct bnx2x_fastpath *fp)
728 static inline bool bnx2x_fp_ll_polling(struct bnx2x_fastpath *fp)
732 static inline bool bnx2x_fp_ll_disable(struct bnx2x_fastpath *fp)
736 #endif /* CONFIG_NET_RX_BUSY_POLL */
738 /* Use 2500 as a mini-jumbo MTU for FCoE */
739 #define BNX2X_FCOE_MINI_JUMBO_MTU 2500
741 #define FCOE_IDX_OFFSET 0
743 #define FCOE_IDX(bp) (BNX2X_NUM_NON_CNIC_QUEUES(bp) + \
745 #define bnx2x_fcoe_fp(bp) (&bp->fp[FCOE_IDX(bp)])
746 #define bnx2x_fcoe(bp, var) (bnx2x_fcoe_fp(bp)->var)
747 #define bnx2x_fcoe_inner_sp_obj(bp) (&bp->sp_objs[FCOE_IDX(bp)])
748 #define bnx2x_fcoe_sp_obj(bp, var) (bnx2x_fcoe_inner_sp_obj(bp)->var)
749 #define bnx2x_fcoe_tx(bp, var) (bnx2x_fcoe_fp(bp)-> \
750 txdata_ptr[FIRST_TX_COS_INDEX] \
753 #define IS_ETH_FP(fp) ((fp)->index < BNX2X_NUM_ETH_QUEUES((fp)->bp))
754 #define IS_FCOE_FP(fp) ((fp)->index == FCOE_IDX((fp)->bp))
755 #define IS_FCOE_IDX(idx) ((idx) == FCOE_IDX(bp))
758 #define MAX_FETCH_BD 13 /* HW max BDs per packet */
759 #define RX_COPY_THRESH 92
761 #define NUM_TX_RINGS 16
762 #define TX_DESC_CNT (BCM_PAGE_SIZE / sizeof(union eth_tx_bd_types))
763 #define NEXT_PAGE_TX_DESC_CNT 1
764 #define MAX_TX_DESC_CNT (TX_DESC_CNT - NEXT_PAGE_TX_DESC_CNT)
765 #define NUM_TX_BD (TX_DESC_CNT * NUM_TX_RINGS)
766 #define MAX_TX_BD (NUM_TX_BD - 1)
767 #define MAX_TX_AVAIL (MAX_TX_DESC_CNT * NUM_TX_RINGS - 2)
768 #define NEXT_TX_IDX(x) ((((x) & MAX_TX_DESC_CNT) == \
769 (MAX_TX_DESC_CNT - 1)) ? \
770 (x) + 1 + NEXT_PAGE_TX_DESC_CNT : \
772 #define TX_BD(x) ((x) & MAX_TX_BD)
773 #define TX_BD_POFF(x) ((x) & MAX_TX_DESC_CNT)
775 /* number of NEXT_PAGE descriptors may be required during placement */
776 #define NEXT_CNT_PER_TX_PKT(bds) \
777 (((bds) + MAX_TX_DESC_CNT - 1) / \
778 MAX_TX_DESC_CNT * NEXT_PAGE_TX_DESC_CNT)
779 /* max BDs per tx packet w/o next_pages:
780 * START_BD - describes packed
781 * START_BD(splitted) - includes unpaged data segment for GSO
782 * PARSING_BD - for TSO and CSUM data
783 * PARSING_BD2 - for encapsulation data
784 * Frag BDs - describes pages for frags
786 #define BDS_PER_TX_PKT 4
787 #define MAX_BDS_PER_TX_PKT (MAX_SKB_FRAGS + BDS_PER_TX_PKT)
788 /* max BDs per tx packet including next pages */
789 #define MAX_DESC_PER_TX_PKT (MAX_BDS_PER_TX_PKT + \
790 NEXT_CNT_PER_TX_PKT(MAX_BDS_PER_TX_PKT))
792 /* The RX BD ring is special, each bd is 8 bytes but the last one is 16 */
793 #define NUM_RX_RINGS 8
794 #define RX_DESC_CNT (BCM_PAGE_SIZE / sizeof(struct eth_rx_bd))
795 #define NEXT_PAGE_RX_DESC_CNT 2
796 #define MAX_RX_DESC_CNT (RX_DESC_CNT - NEXT_PAGE_RX_DESC_CNT)
797 #define RX_DESC_MASK (RX_DESC_CNT - 1)
798 #define NUM_RX_BD (RX_DESC_CNT * NUM_RX_RINGS)
799 #define MAX_RX_BD (NUM_RX_BD - 1)
800 #define MAX_RX_AVAIL (MAX_RX_DESC_CNT * NUM_RX_RINGS - 2)
802 /* dropless fc calculations for BDs
804 * Number of BDs should as number of buffers in BRB:
805 * Low threshold takes into account NEXT_PAGE_RX_DESC_CNT
806 * "next" elements on each page
808 #define NUM_BD_REQ BRB_SIZE(bp)
809 #define NUM_BD_PG_REQ ((NUM_BD_REQ + MAX_RX_DESC_CNT - 1) / \
811 #define BD_TH_LO(bp) (NUM_BD_REQ + \
812 NUM_BD_PG_REQ * NEXT_PAGE_RX_DESC_CNT + \
814 #define BD_TH_HI(bp) (BD_TH_LO(bp) + DROPLESS_FC_HEADROOM)
816 #define MIN_RX_AVAIL ((bp)->dropless_fc ? BD_TH_HI(bp) + 128 : 128)
818 #define MIN_RX_SIZE_TPA_HW (CHIP_IS_E1(bp) ? \
819 ETH_MIN_RX_CQES_WITH_TPA_E1 : \
820 ETH_MIN_RX_CQES_WITH_TPA_E1H_E2)
821 #define MIN_RX_SIZE_NONTPA_HW ETH_MIN_RX_CQES_WITHOUT_TPA
822 #define MIN_RX_SIZE_TPA (max_t(u32, MIN_RX_SIZE_TPA_HW, MIN_RX_AVAIL))
823 #define MIN_RX_SIZE_NONTPA (max_t(u32, MIN_RX_SIZE_NONTPA_HW,\
826 #define NEXT_RX_IDX(x) ((((x) & RX_DESC_MASK) == \
827 (MAX_RX_DESC_CNT - 1)) ? \
828 (x) + 1 + NEXT_PAGE_RX_DESC_CNT : \
830 #define RX_BD(x) ((x) & MAX_RX_BD)
833 * As long as CQE is X times bigger than BD entry we have to allocate X times
834 * more pages for CQ ring in order to keep it balanced with BD ring
836 #define CQE_BD_REL (sizeof(union eth_rx_cqe) / sizeof(struct eth_rx_bd))
837 #define NUM_RCQ_RINGS (NUM_RX_RINGS * CQE_BD_REL)
838 #define RCQ_DESC_CNT (BCM_PAGE_SIZE / sizeof(union eth_rx_cqe))
839 #define NEXT_PAGE_RCQ_DESC_CNT 1
840 #define MAX_RCQ_DESC_CNT (RCQ_DESC_CNT - NEXT_PAGE_RCQ_DESC_CNT)
841 #define NUM_RCQ_BD (RCQ_DESC_CNT * NUM_RCQ_RINGS)
842 #define MAX_RCQ_BD (NUM_RCQ_BD - 1)
843 #define MAX_RCQ_AVAIL (MAX_RCQ_DESC_CNT * NUM_RCQ_RINGS - 2)
844 #define NEXT_RCQ_IDX(x) ((((x) & MAX_RCQ_DESC_CNT) == \
845 (MAX_RCQ_DESC_CNT - 1)) ? \
846 (x) + 1 + NEXT_PAGE_RCQ_DESC_CNT : \
848 #define RCQ_BD(x) ((x) & MAX_RCQ_BD)
850 /* dropless fc calculations for RCQs
852 * Number of RCQs should be as number of buffers in BRB:
853 * Low threshold takes into account NEXT_PAGE_RCQ_DESC_CNT
854 * "next" elements on each page
856 #define NUM_RCQ_REQ BRB_SIZE(bp)
857 #define NUM_RCQ_PG_REQ ((NUM_BD_REQ + MAX_RCQ_DESC_CNT - 1) / \
859 #define RCQ_TH_LO(bp) (NUM_RCQ_REQ + \
860 NUM_RCQ_PG_REQ * NEXT_PAGE_RCQ_DESC_CNT + \
862 #define RCQ_TH_HI(bp) (RCQ_TH_LO(bp) + DROPLESS_FC_HEADROOM)
864 /* This is needed for determining of last_max */
865 #define SUB_S16(a, b) (s16)((s16)(a) - (s16)(b))
866 #define SUB_S32(a, b) (s32)((s32)(a) - (s32)(b))
868 #define BNX2X_SWCID_SHIFT 17
869 #define BNX2X_SWCID_MASK ((0x1 << BNX2X_SWCID_SHIFT) - 1)
871 /* used on a CID received from the HW */
872 #define SW_CID(x) (le32_to_cpu(x) & BNX2X_SWCID_MASK)
873 #define CQE_CMD(x) (le32_to_cpu(x) >> \
874 COMMON_RAMROD_ETH_RX_CQE_CMD_ID_SHIFT)
876 #define BD_UNMAP_ADDR(bd) HILO_U64(le32_to_cpu((bd)->addr_hi), \
877 le32_to_cpu((bd)->addr_lo))
878 #define BD_UNMAP_LEN(bd) (le16_to_cpu((bd)->nbytes))
880 #define BNX2X_DB_MIN_SHIFT 3 /* 8 bytes */
881 #define BNX2X_DB_SHIFT 3 /* 8 bytes*/
882 #if (BNX2X_DB_SHIFT < BNX2X_DB_MIN_SHIFT)
883 #error "Min DB doorbell stride is 8"
885 #define DOORBELL(bp, cid, val) \
887 writel((u32)(val), bp->doorbells + (bp->db_size * (cid))); \
890 /* TX CSUM helpers */
891 #define SKB_CS_OFF(skb) (offsetof(struct tcphdr, check) - \
893 #define SKB_CS(skb) (*(u16 *)(skb_transport_header(skb) + \
896 #define pbd_tcp_flags(tcp_hdr) (ntohl(tcp_flag_word(tcp_hdr))>>16 & 0xff)
899 #define XMIT_CSUM_V4 (1 << 0)
900 #define XMIT_CSUM_V6 (1 << 1)
901 #define XMIT_CSUM_TCP (1 << 2)
902 #define XMIT_GSO_V4 (1 << 3)
903 #define XMIT_GSO_V6 (1 << 4)
904 #define XMIT_CSUM_ENC_V4 (1 << 5)
905 #define XMIT_CSUM_ENC_V6 (1 << 6)
906 #define XMIT_GSO_ENC_V4 (1 << 7)
907 #define XMIT_GSO_ENC_V6 (1 << 8)
909 #define XMIT_CSUM_ENC (XMIT_CSUM_ENC_V4 | XMIT_CSUM_ENC_V6)
910 #define XMIT_GSO_ENC (XMIT_GSO_ENC_V4 | XMIT_GSO_ENC_V6)
912 #define XMIT_CSUM (XMIT_CSUM_V4 | XMIT_CSUM_V6 | XMIT_CSUM_ENC)
913 #define XMIT_GSO (XMIT_GSO_V4 | XMIT_GSO_V6 | XMIT_GSO_ENC)
915 /* stuff added to make the code fit 80Col */
916 #define CQE_TYPE(cqe_fp_flags) ((cqe_fp_flags) & ETH_FAST_PATH_RX_CQE_TYPE)
917 #define CQE_TYPE_START(cqe_type) ((cqe_type) == RX_ETH_CQE_TYPE_ETH_START_AGG)
918 #define CQE_TYPE_STOP(cqe_type) ((cqe_type) == RX_ETH_CQE_TYPE_ETH_STOP_AGG)
919 #define CQE_TYPE_SLOW(cqe_type) ((cqe_type) == RX_ETH_CQE_TYPE_ETH_RAMROD)
920 #define CQE_TYPE_FAST(cqe_type) ((cqe_type) == RX_ETH_CQE_TYPE_ETH_FASTPATH)
922 #define ETH_RX_ERROR_FALGS ETH_FAST_PATH_RX_CQE_PHY_DECODE_ERR_FLG
924 #define BNX2X_PRS_FLAG_OVERETH_IPV4(flags) \
925 (((le16_to_cpu(flags) & \
926 PARSING_FLAGS_OVER_ETHERNET_PROTOCOL) >> \
927 PARSING_FLAGS_OVER_ETHERNET_PROTOCOL_SHIFT) \
928 == PRS_FLAG_OVERETH_IPV4)
929 #define BNX2X_RX_SUM_FIX(cqe) \
930 BNX2X_PRS_FLAG_OVERETH_IPV4(cqe->fast_path_cqe.pars_flags.flags)
932 #define FP_USB_FUNC_OFF \
933 offsetof(struct cstorm_status_block_u, func)
934 #define FP_CSB_FUNC_OFF \
935 offsetof(struct cstorm_status_block_c, func)
937 #define HC_INDEX_ETH_RX_CQ_CONS 1
939 #define HC_INDEX_OOO_TX_CQ_CONS 4
941 #define HC_INDEX_ETH_TX_CQ_CONS_COS0 5
943 #define HC_INDEX_ETH_TX_CQ_CONS_COS1 6
945 #define HC_INDEX_ETH_TX_CQ_CONS_COS2 7
947 #define HC_INDEX_ETH_FIRST_TX_CQ_CONS HC_INDEX_ETH_TX_CQ_CONS_COS0
949 #define BNX2X_RX_SB_INDEX \
950 (&fp->sb_index_values[HC_INDEX_ETH_RX_CQ_CONS])
952 #define BNX2X_TX_SB_INDEX_BASE BNX2X_TX_SB_INDEX_COS0
954 #define BNX2X_TX_SB_INDEX_COS0 \
955 (&fp->sb_index_values[HC_INDEX_ETH_TX_CQ_CONS_COS0])
957 /* end of fast path */
961 struct bnx2x_common {
964 /* chip num:16-31, rev:12-15, metal:4-11, bond_id:0-3 */
965 #define CHIP_ID(bp) (bp->common.chip_id & 0xfffffff0)
967 #define CHIP_NUM(bp) (bp->common.chip_id >> 16)
968 #define CHIP_NUM_57710 0x164e
969 #define CHIP_NUM_57711 0x164f
970 #define CHIP_NUM_57711E 0x1650
971 #define CHIP_NUM_57712 0x1662
972 #define CHIP_NUM_57712_MF 0x1663
973 #define CHIP_NUM_57712_VF 0x166f
974 #define CHIP_NUM_57713 0x1651
975 #define CHIP_NUM_57713E 0x1652
976 #define CHIP_NUM_57800 0x168a
977 #define CHIP_NUM_57800_MF 0x16a5
978 #define CHIP_NUM_57800_VF 0x16a9
979 #define CHIP_NUM_57810 0x168e
980 #define CHIP_NUM_57810_MF 0x16ae
981 #define CHIP_NUM_57810_VF 0x16af
982 #define CHIP_NUM_57811 0x163d
983 #define CHIP_NUM_57811_MF 0x163e
984 #define CHIP_NUM_57811_VF 0x163f
985 #define CHIP_NUM_57840_OBSOLETE 0x168d
986 #define CHIP_NUM_57840_MF_OBSOLETE 0x16ab
987 #define CHIP_NUM_57840_4_10 0x16a1
988 #define CHIP_NUM_57840_2_20 0x16a2
989 #define CHIP_NUM_57840_MF 0x16a4
990 #define CHIP_NUM_57840_VF 0x16ad
991 #define CHIP_IS_E1(bp) (CHIP_NUM(bp) == CHIP_NUM_57710)
992 #define CHIP_IS_57711(bp) (CHIP_NUM(bp) == CHIP_NUM_57711)
993 #define CHIP_IS_57711E(bp) (CHIP_NUM(bp) == CHIP_NUM_57711E)
994 #define CHIP_IS_57712(bp) (CHIP_NUM(bp) == CHIP_NUM_57712)
995 #define CHIP_IS_57712_VF(bp) (CHIP_NUM(bp) == CHIP_NUM_57712_VF)
996 #define CHIP_IS_57712_MF(bp) (CHIP_NUM(bp) == CHIP_NUM_57712_MF)
997 #define CHIP_IS_57800(bp) (CHIP_NUM(bp) == CHIP_NUM_57800)
998 #define CHIP_IS_57800_MF(bp) (CHIP_NUM(bp) == CHIP_NUM_57800_MF)
999 #define CHIP_IS_57800_VF(bp) (CHIP_NUM(bp) == CHIP_NUM_57800_VF)
1000 #define CHIP_IS_57810(bp) (CHIP_NUM(bp) == CHIP_NUM_57810)
1001 #define CHIP_IS_57810_MF(bp) (CHIP_NUM(bp) == CHIP_NUM_57810_MF)
1002 #define CHIP_IS_57810_VF(bp) (CHIP_NUM(bp) == CHIP_NUM_57810_VF)
1003 #define CHIP_IS_57811(bp) (CHIP_NUM(bp) == CHIP_NUM_57811)
1004 #define CHIP_IS_57811_MF(bp) (CHIP_NUM(bp) == CHIP_NUM_57811_MF)
1005 #define CHIP_IS_57811_VF(bp) (CHIP_NUM(bp) == CHIP_NUM_57811_VF)
1006 #define CHIP_IS_57840(bp) \
1007 ((CHIP_NUM(bp) == CHIP_NUM_57840_4_10) || \
1008 (CHIP_NUM(bp) == CHIP_NUM_57840_2_20) || \
1009 (CHIP_NUM(bp) == CHIP_NUM_57840_OBSOLETE))
1010 #define CHIP_IS_57840_MF(bp) ((CHIP_NUM(bp) == CHIP_NUM_57840_MF) || \
1011 (CHIP_NUM(bp) == CHIP_NUM_57840_MF_OBSOLETE))
1012 #define CHIP_IS_57840_VF(bp) (CHIP_NUM(bp) == CHIP_NUM_57840_VF)
1013 #define CHIP_IS_E1H(bp) (CHIP_IS_57711(bp) || \
1015 #define CHIP_IS_57811xx(bp) (CHIP_IS_57811(bp) || \
1016 CHIP_IS_57811_MF(bp) || \
1017 CHIP_IS_57811_VF(bp))
1018 #define CHIP_IS_E2(bp) (CHIP_IS_57712(bp) || \
1019 CHIP_IS_57712_MF(bp) || \
1020 CHIP_IS_57712_VF(bp))
1021 #define CHIP_IS_E3(bp) (CHIP_IS_57800(bp) || \
1022 CHIP_IS_57800_MF(bp) || \
1023 CHIP_IS_57800_VF(bp) || \
1024 CHIP_IS_57810(bp) || \
1025 CHIP_IS_57810_MF(bp) || \
1026 CHIP_IS_57810_VF(bp) || \
1027 CHIP_IS_57811xx(bp) || \
1028 CHIP_IS_57840(bp) || \
1029 CHIP_IS_57840_MF(bp) || \
1030 CHIP_IS_57840_VF(bp))
1031 #define CHIP_IS_E1x(bp) (CHIP_IS_E1((bp)) || CHIP_IS_E1H((bp)))
1032 #define USES_WARPCORE(bp) (CHIP_IS_E3(bp))
1033 #define IS_E1H_OFFSET (!CHIP_IS_E1(bp))
1035 #define CHIP_REV_SHIFT 12
1036 #define CHIP_REV_MASK (0xF << CHIP_REV_SHIFT)
1037 #define CHIP_REV_VAL(bp) (bp->common.chip_id & CHIP_REV_MASK)
1038 #define CHIP_REV_Ax (0x0 << CHIP_REV_SHIFT)
1039 #define CHIP_REV_Bx (0x1 << CHIP_REV_SHIFT)
1040 /* assume maximum 5 revisions */
1041 #define CHIP_REV_IS_SLOW(bp) (CHIP_REV_VAL(bp) > 0x00005000)
1042 /* Emul versions are A=>0xe, B=>0xc, C=>0xa, D=>8, E=>6 */
1043 #define CHIP_REV_IS_EMUL(bp) ((CHIP_REV_IS_SLOW(bp)) && \
1044 !(CHIP_REV_VAL(bp) & 0x00001000))
1045 /* FPGA versions are A=>0xf, B=>0xd, C=>0xb, D=>9, E=>7 */
1046 #define CHIP_REV_IS_FPGA(bp) ((CHIP_REV_IS_SLOW(bp)) && \
1047 (CHIP_REV_VAL(bp) & 0x00001000))
1049 #define CHIP_TIME(bp) ((CHIP_REV_IS_EMUL(bp)) ? 2000 : \
1050 ((CHIP_REV_IS_FPGA(bp)) ? 200 : 1))
1052 #define CHIP_METAL(bp) (bp->common.chip_id & 0x00000ff0)
1053 #define CHIP_BOND_ID(bp) (bp->common.chip_id & 0x0000000f)
1054 #define CHIP_REV_SIM(bp) (((CHIP_REV_MASK - CHIP_REV_VAL(bp)) >>\
1055 (CHIP_REV_SHIFT + 1)) \
1057 #define CHIP_REV(bp) (CHIP_REV_IS_SLOW(bp) ? \
1060 #define CHIP_IS_E3B0(bp) (CHIP_IS_E3(bp) && \
1061 (CHIP_REV(bp) == CHIP_REV_Bx))
1062 #define CHIP_IS_E3A0(bp) (CHIP_IS_E3(bp) && \
1063 (CHIP_REV(bp) == CHIP_REV_Ax))
1064 /* This define is used in two main places:
1065 * 1. In the early stages of nic_load, to know if to configure Parser / Searcher
1066 * to nic-only mode or to offload mode. Offload mode is configured if either the
1067 * chip is E1x (where MIC_MODE register is not applicable), or if cnic already
1068 * registered for this port (which means that the user wants storage services).
1069 * 2. During cnic-related load, to know if offload mode is already configured in
1070 * the HW or needs to be configured.
1071 * Since the transition from nic-mode to offload-mode in HW causes traffic
1072 * corruption, nic-mode is configured only in ports on which storage services
1073 * where never requested.
1075 #define CONFIGURE_NIC_MODE(bp) (!CHIP_IS_E1x(bp) && !CNIC_ENABLED(bp))
1078 #define BNX2X_NVRAM_1MB_SIZE 0x20000 /* 1M bit in bytes */
1079 #define BNX2X_NVRAM_TIMEOUT_COUNT 30000
1080 #define BNX2X_NVRAM_PAGE_SIZE 256
1092 #define INT_BLOCK_HC 0
1093 #define INT_BLOCK_IGU 1
1094 #define INT_BLOCK_MODE_NORMAL 0
1095 #define INT_BLOCK_MODE_BW_COMP 2
1096 #define CHIP_INT_MODE_IS_NBC(bp) \
1097 (!CHIP_IS_E1x(bp) && \
1098 !((bp)->common.int_block & INT_BLOCK_MODE_BW_COMP))
1099 #define CHIP_INT_MODE_IS_BC(bp) (!CHIP_INT_MODE_IS_NBC(bp))
1102 #define CHIP_4_PORT_MODE 0x0
1103 #define CHIP_2_PORT_MODE 0x1
1104 #define CHIP_PORT_MODE_NONE 0x2
1105 #define CHIP_MODE(bp) (bp->common.chip_port_mode)
1106 #define CHIP_MODE_IS_4_PORT(bp) (CHIP_MODE(bp) == CHIP_4_PORT_MODE)
1111 /* IGU MSIX STATISTICS on 57712: 64 for VFs; 4 for PFs; 4 for Attentions */
1112 #define BNX2X_IGU_STAS_MSG_VF_CNT 64
1113 #define BNX2X_IGU_STAS_MSG_PF_CNT 4
1115 #define MAX_IGU_ATTN_ACK_TO 100
1123 u32 link_config[LINK_CONFIG_SIZE];
1125 u32 supported[LINK_CONFIG_SIZE];
1126 /* link settings - missing defines */
1127 #define SUPPORTED_2500baseX_Full (1 << 15)
1129 u32 advertising[LINK_CONFIG_SIZE];
1130 /* link settings - missing defines */
1131 #define ADVERTISED_2500baseX_Full (1 << 15)
1135 /* used to synchronize phy accesses */
1136 struct mutex phy_mutex;
1140 struct nig_stats old_nig_stats;
1145 #define STATS_OFFSET32(stat_name) \
1146 (offsetof(struct bnx2x_eth_stats, stat_name) / 4)
1150 /* slow path work-queue */
1151 extern struct workqueue_struct *bnx2x_wq;
1153 #define BNX2X_MAX_NUM_OF_VFS 64
1154 #define BNX2X_VF_CID_WND 4 /* log num of queues per VF. HW config. */
1155 #define BNX2X_CIDS_PER_VF (1 << BNX2X_VF_CID_WND)
1157 /* We need to reserve doorbell addresses for all VF and queue combinations */
1158 #define BNX2X_VF_CIDS (BNX2X_MAX_NUM_OF_VFS * BNX2X_CIDS_PER_VF)
1160 /* The doorbell is configured to have the same number of CIDs for PFs and for
1161 * VFs. For this reason the PF CID zone is as large as the VF zone.
1163 #define BNX2X_FIRST_VF_CID BNX2X_VF_CIDS
1164 #define BNX2X_MAX_NUM_VF_QUEUES 64
1165 #define BNX2X_VF_ID_INVALID 0xFF
1167 /* the number of VF CIDS multiplied by the amount of bytes reserved for each
1168 * cid must not exceed the size of the VF doorbell
1170 #define BNX2X_VF_BAR_SIZE 512
1171 #if (BNX2X_VF_BAR_SIZE < BNX2X_CIDS_PER_VF * (1 << BNX2X_DB_SHIFT))
1172 #error "VF doorbell bar size is 512"
1176 * The total number of L2 queues, MSIX vectors and HW contexts (CIDs) is
1177 * control by the number of fast-path status blocks supported by the
1178 * device (HW/FW). Each fast-path status block (FP-SB) aka non-default
1179 * status block represents an independent interrupts context that can
1180 * serve a regular L2 networking queue. However special L2 queues such
1181 * as the FCoE queue do not require a FP-SB and other components like
1182 * the CNIC may consume FP-SB reducing the number of possible L2 queues
1184 * If the maximum number of FP-SB available is X then:
1185 * a. If CNIC is supported it consumes 1 FP-SB thus the max number of
1186 * regular L2 queues is Y=X-1
1187 * b. In MF mode the actual number of L2 queues is Y= (X-1/MF_factor)
1188 * c. If the FCoE L2 queue is supported the actual number of L2 queues
1190 * d. The number of irqs (MSIX vectors) is either Y+1 (one extra for
1191 * slow-path interrupts) or Y+2 if CNIC is supported (one additional
1192 * FP interrupt context for the CNIC).
1193 * e. The number of HW context (CID count) is always X or X+1 if FCoE
1194 * L2 queue is supported. The cid for the FCoE L2 queue is always X.
1197 /* fast-path interrupt contexts E1x */
1198 #define FP_SB_MAX_E1x 16
1199 /* fast-path interrupt contexts E2 */
1200 #define FP_SB_MAX_E2 HC_SB_MAX_SB_E2
1203 struct eth_context eth;
1207 /* CDU host DB constants */
1208 #define CDU_ILT_PAGE_SZ_HW 2
1209 #define CDU_ILT_PAGE_SZ (8192 << CDU_ILT_PAGE_SZ_HW) /* 32K */
1210 #define ILT_PAGE_CIDS (CDU_ILT_PAGE_SZ / sizeof(union cdu_context))
1212 #define CNIC_ISCSI_CID_MAX 256
1213 #define CNIC_FCOE_CID_MAX 2048
1214 #define CNIC_CID_MAX (CNIC_ISCSI_CID_MAX + CNIC_FCOE_CID_MAX)
1215 #define CNIC_ILT_LINES DIV_ROUND_UP(CNIC_CID_MAX, ILT_PAGE_CIDS)
1217 #define QM_ILT_PAGE_SZ_HW 0
1218 #define QM_ILT_PAGE_SZ (4096 << QM_ILT_PAGE_SZ_HW) /* 4K */
1219 #define QM_CID_ROUND 1024
1221 /* TM (timers) host DB constants */
1222 #define TM_ILT_PAGE_SZ_HW 0
1223 #define TM_ILT_PAGE_SZ (4096 << TM_ILT_PAGE_SZ_HW) /* 4K */
1224 #define TM_CONN_NUM (BNX2X_FIRST_VF_CID + \
1227 #define TM_ILT_SZ (8 * TM_CONN_NUM)
1228 #define TM_ILT_LINES DIV_ROUND_UP(TM_ILT_SZ, TM_ILT_PAGE_SZ)
1230 /* SRC (Searcher) host DB constants */
1231 #define SRC_ILT_PAGE_SZ_HW 0
1232 #define SRC_ILT_PAGE_SZ (4096 << SRC_ILT_PAGE_SZ_HW) /* 4K */
1233 #define SRC_HASH_BITS 10
1234 #define SRC_CONN_NUM (1 << SRC_HASH_BITS) /* 1024 */
1235 #define SRC_ILT_SZ (sizeof(struct src_ent) * SRC_CONN_NUM)
1236 #define SRC_T2_SZ SRC_ILT_SZ
1237 #define SRC_ILT_LINES DIV_ROUND_UP(SRC_ILT_SZ, SRC_ILT_PAGE_SZ)
1239 #define MAX_DMAE_C 8
1241 /* DMA memory not used in fastpath */
1242 struct bnx2x_slowpath {
1244 struct mac_configuration_cmd e1x;
1245 struct eth_classify_rules_ramrod_data e2;
1249 struct tstorm_eth_mac_filter_config e1x;
1250 struct eth_filter_rules_ramrod_data e2;
1254 struct mac_configuration_cmd e1;
1255 struct eth_multicast_rules_ramrod_data e2;
1258 struct eth_rss_update_ramrod_data rss_rdata;
1260 /* Queue State related ramrods are always sent under rtnl_lock */
1262 struct client_init_ramrod_data init_data;
1263 struct client_update_ramrod_data update_data;
1267 struct function_start_data func_start;
1268 /* pfc configuration for DCBX ramrod */
1269 struct flow_control_configuration pfc_config;
1272 /* afex ramrod can not be a part of func_rdata union because these
1273 * events might arrive in parallel to other events from func_rdata.
1274 * Therefore, if they would have been defined in the same union,
1275 * data can get corrupted.
1278 struct afex_vif_list_ramrod_data viflist_data;
1279 struct function_update_data func_update;
1282 /* used by dmae command executer */
1283 struct dmae_command dmae[MAX_DMAE_C];
1286 union mac_stats mac_stats;
1287 struct nig_stats nig_stats;
1288 struct host_port_stats port_stats;
1289 struct host_func_stats func_stats;
1294 union drv_info_to_mcp drv_info_to_mcp;
1297 #define bnx2x_sp(bp, var) (&bp->slowpath->var)
1298 #define bnx2x_sp_mapping(bp, var) \
1299 (bp->slowpath_mapping + offsetof(struct bnx2x_slowpath, var))
1301 /* attn group wiring */
1302 #define MAX_DYNAMIC_ATTN_GRPS 8
1317 union cdu_context *vcxt;
1318 dma_addr_t cxt_mapping;
1327 enum bnx2x_recovery_state {
1328 BNX2X_RECOVERY_DONE,
1329 BNX2X_RECOVERY_INIT,
1330 BNX2X_RECOVERY_WAIT,
1331 BNX2X_RECOVERY_FAILED,
1332 BNX2X_RECOVERY_NIC_LOADING
1336 * Event queue (EQ or event ring) MC hsi
1337 * NUM_EQ_PAGES and EQ_DESC_CNT_PAGE must be power of 2
1339 #define NUM_EQ_PAGES 1
1340 #define EQ_DESC_CNT_PAGE (BCM_PAGE_SIZE / sizeof(union event_ring_elem))
1341 #define EQ_DESC_MAX_PAGE (EQ_DESC_CNT_PAGE - 1)
1342 #define NUM_EQ_DESC (EQ_DESC_CNT_PAGE * NUM_EQ_PAGES)
1343 #define EQ_DESC_MASK (NUM_EQ_DESC - 1)
1344 #define MAX_EQ_AVAIL (EQ_DESC_MAX_PAGE * NUM_EQ_PAGES - 2)
1346 /* depends on EQ_DESC_CNT_PAGE being a power of 2 */
1347 #define NEXT_EQ_IDX(x) ((((x) & EQ_DESC_MAX_PAGE) == \
1348 (EQ_DESC_MAX_PAGE - 1)) ? (x) + 2 : (x) + 1)
1350 /* depends on the above and on NUM_EQ_PAGES being a power of 2 */
1351 #define EQ_DESC(x) ((x) & EQ_DESC_MASK)
1353 #define BNX2X_EQ_INDEX \
1354 (&bp->def_status_blk->sp_sb.\
1355 index_values[HC_SP_INDEX_EQ_CONS])
1357 /* This is a data that will be used to create a link report message.
1358 * We will keep the data used for the last link report in order
1359 * to prevent reporting the same link parameters twice.
1361 struct bnx2x_link_report_data {
1362 u16 line_speed; /* Effective line speed */
1363 unsigned long link_report_flags;/* BNX2X_LINK_REPORT_XXX flags */
1367 BNX2X_LINK_REPORT_FD, /* Full DUPLEX */
1368 BNX2X_LINK_REPORT_LINK_DOWN,
1369 BNX2X_LINK_REPORT_RX_FC_ON,
1370 BNX2X_LINK_REPORT_TX_FC_ON,
1374 BNX2X_PORT_QUERY_IDX,
1376 BNX2X_FCOE_QUERY_IDX,
1377 BNX2X_FIRST_QUEUE_QUERY_IDX,
1380 struct bnx2x_fw_stats_req {
1381 struct stats_query_header hdr;
1382 struct stats_query_entry query[FP_SB_MAX_E1x+
1383 BNX2X_FIRST_QUEUE_QUERY_IDX];
1386 struct bnx2x_fw_stats_data {
1387 struct stats_counter storm_counters;
1388 struct per_port_stats port;
1389 struct per_pf_stats pf;
1390 struct fcoe_statistics_params fcoe;
1391 struct per_queue_stats queue_stats[1];
1394 /* Public slow path states */
1396 BNX2X_SP_RTNL_SETUP_TC,
1397 BNX2X_SP_RTNL_TX_TIMEOUT,
1398 BNX2X_SP_RTNL_FAN_FAILURE,
1399 BNX2X_SP_RTNL_AFEX_F_UPDATE,
1400 BNX2X_SP_RTNL_ENABLE_SRIOV,
1401 BNX2X_SP_RTNL_VFPF_MCAST,
1402 BNX2X_SP_RTNL_VFPF_CHANNEL_DOWN,
1403 BNX2X_SP_RTNL_RX_MODE,
1404 BNX2X_SP_RTNL_HYPERVISOR_VLAN,
1405 BNX2X_SP_RTNL_TX_STOP,
1408 struct bnx2x_prev_path_list {
1409 struct list_head list;
1417 struct bnx2x_sp_objs {
1419 struct bnx2x_vlan_mac_obj mac_obj;
1421 /* Queue State object */
1422 struct bnx2x_queue_sp_obj q_obj;
1425 struct bnx2x_fp_stats {
1426 struct tstorm_per_queue_stats old_tclient;
1427 struct ustorm_per_queue_stats old_uclient;
1428 struct xstorm_per_queue_stats old_xclient;
1429 struct bnx2x_eth_q_stats eth_q_stats;
1430 struct bnx2x_eth_q_stats_old eth_q_stats_old;
1434 /* Fields used in the tx and intr/napi performance paths
1435 * are grouped together in the beginning of the structure
1437 struct bnx2x_fastpath *fp;
1438 struct bnx2x_sp_objs *sp_objs;
1439 struct bnx2x_fp_stats *fp_stats;
1440 struct bnx2x_fp_txdata *bnx2x_txq;
1441 void __iomem *regview;
1442 void __iomem *doorbells;
1445 u8 pf_num; /* absolute PF number */
1446 u8 pfid; /* per-path PF number */
1447 int base_fw_ndsb; /**/
1448 #define BP_PATH(bp) (CHIP_IS_E1x(bp) ? 0 : (bp->pf_num & 1))
1449 #define BP_PORT(bp) (bp->pfid & 1)
1450 #define BP_FUNC(bp) (bp->pfid)
1451 #define BP_ABS_FUNC(bp) (bp->pf_num)
1452 #define BP_VN(bp) ((bp)->pfid >> 1)
1453 #define BP_MAX_VN_NUM(bp) (CHIP_MODE_IS_4_PORT(bp) ? 2 : 4)
1454 #define BP_L_ID(bp) (BP_VN(bp) << 2)
1455 #define BP_FW_MB_IDX_VN(bp, vn) (BP_PORT(bp) +\
1456 (vn) * ((CHIP_IS_E1x(bp) || (CHIP_MODE_IS_4_PORT(bp))) ? 2 : 1))
1457 #define BP_FW_MB_IDX(bp) BP_FW_MB_IDX_VN(bp, BP_VN(bp))
1459 #ifdef CONFIG_BNX2X_SRIOV
1460 /* protects vf2pf mailbox from simultaneous access */
1461 struct mutex vf2pf_mutex;
1462 /* vf pf channel mailbox contains request and response buffers */
1463 struct bnx2x_vf_mbx_msg *vf2pf_mbox;
1464 dma_addr_t vf2pf_mbox_mapping;
1466 /* we set aside a copy of the acquire response */
1467 struct pfvf_acquire_resp_tlv acquire_resp;
1469 /* bulletin board for messages from pf to vf */
1470 union pf_vf_bulletin *pf2vf_bulletin;
1471 dma_addr_t pf2vf_bulletin_mapping;
1473 struct pf_vf_bulletin_content old_bulletin;
1475 u16 requested_nr_virtfn;
1476 #endif /* CONFIG_BNX2X_SRIOV */
1478 struct net_device *dev;
1479 struct pci_dev *pdev;
1481 const struct iro *iro_arr;
1482 #define IRO (bp->iro_arr)
1484 enum bnx2x_recovery_state recovery_state;
1486 struct msix_entry *msix_table;
1490 /* L2 header size + 2*VLANs (8 bytes) + LLC SNAP (8 bytes) */
1491 #define ETH_OVREHEAD (ETH_HLEN + 8 + 8)
1492 #define ETH_MIN_PACKET_SIZE 60
1493 #define ETH_MAX_PACKET_SIZE 1500
1494 #define ETH_MAX_JUMBO_PACKET_SIZE 9600
1495 /* TCP with Timestamp Option (32) + IPv6 (40) */
1496 #define ETH_MAX_TPA_HEADER_SIZE 72
1498 /* Max supported alignment is 256 (8 shift) */
1499 #define BNX2X_RX_ALIGN_SHIFT min(8, L1_CACHE_SHIFT)
1501 /* FW uses 2 Cache lines Alignment for start packet and size
1503 * We assume skb_build() uses sizeof(struct skb_shared_info) bytes
1504 * at the end of skb->data, to avoid wasting a full cache line.
1505 * This reduces memory use (skb->truesize).
1507 #define BNX2X_FW_RX_ALIGN_START (1UL << BNX2X_RX_ALIGN_SHIFT)
1509 #define BNX2X_FW_RX_ALIGN_END \
1510 max_t(u64, 1UL << BNX2X_RX_ALIGN_SHIFT, \
1511 SKB_DATA_ALIGN(sizeof(struct skb_shared_info)))
1513 #define BNX2X_PXP_DRAM_ALIGN (BNX2X_RX_ALIGN_SHIFT - 5)
1515 struct host_sp_status_block *def_status_blk;
1516 #define DEF_SB_IGU_ID 16
1517 #define DEF_SB_ID HC_SP_SB_ID
1521 struct attn_route attn_group[MAX_DYNAMIC_ATTN_GRPS];
1523 /* slow path ring */
1524 struct eth_spe *spq;
1525 dma_addr_t spq_mapping;
1527 struct eth_spe *spq_prod_bd;
1528 struct eth_spe *spq_last_bd;
1529 __le16 *dsb_sp_prod;
1530 atomic_t cq_spq_left; /* ETH_XXX ramrods credit */
1531 /* used to synchronize spq accesses */
1532 spinlock_t spq_lock;
1535 union event_ring_elem *eq_ring;
1536 dma_addr_t eq_mapping;
1540 atomic_t eq_spq_left; /* COMMON_XXX ramrods credit */
1542 /* Counter for marking that there is a STAT_QUERY ramrod pending */
1544 /* Counter for completed statistics ramrods */
1547 /* End of fields used in the performance code paths */
1553 #define PCIX_FLAG (1 << 0)
1554 #define PCI_32BIT_FLAG (1 << 1)
1555 #define ONE_PORT_FLAG (1 << 2)
1556 #define NO_WOL_FLAG (1 << 3)
1557 #define USING_MSIX_FLAG (1 << 5)
1558 #define USING_MSI_FLAG (1 << 6)
1559 #define DISABLE_MSI_FLAG (1 << 7)
1560 #define TPA_ENABLE_FLAG (1 << 8)
1561 #define NO_MCP_FLAG (1 << 9)
1562 #define GRO_ENABLE_FLAG (1 << 10)
1563 #define MF_FUNC_DIS (1 << 11)
1564 #define OWN_CNIC_IRQ (1 << 12)
1565 #define NO_ISCSI_OOO_FLAG (1 << 13)
1566 #define NO_ISCSI_FLAG (1 << 14)
1567 #define NO_FCOE_FLAG (1 << 15)
1568 #define BC_SUPPORTS_PFC_STATS (1 << 17)
1569 #define BC_SUPPORTS_FCOE_FEATURES (1 << 19)
1570 #define USING_SINGLE_MSIX_FLAG (1 << 20)
1571 #define BC_SUPPORTS_DCBX_MSG_NON_PMF (1 << 21)
1572 #define IS_VF_FLAG (1 << 22)
1573 #define INTERRUPTS_ENABLED_FLAG (1 << 23)
1574 #define BC_SUPPORTS_RMMOD_CMD (1 << 24)
1575 #define HAS_PHYS_PORT_ID (1 << 25)
1577 #define BP_NOMCP(bp) ((bp)->flags & NO_MCP_FLAG)
1579 #ifdef CONFIG_BNX2X_SRIOV
1580 #define IS_VF(bp) ((bp)->flags & IS_VF_FLAG)
1581 #define IS_PF(bp) (!((bp)->flags & IS_VF_FLAG))
1583 #define IS_VF(bp) false
1584 #define IS_PF(bp) true
1587 #define NO_ISCSI(bp) ((bp)->flags & NO_ISCSI_FLAG)
1588 #define NO_ISCSI_OOO(bp) ((bp)->flags & NO_ISCSI_OOO_FLAG)
1589 #define NO_FCOE(bp) ((bp)->flags & NO_FCOE_FLAG)
1594 struct cnic_eth_dev *(*cnic_probe)(struct net_device *);
1596 /* Flag that indicates that we can start looking for FCoE L2 queue
1597 * completions in the default status block.
1603 struct delayed_work sp_task;
1604 atomic_t interrupt_occurred;
1605 struct delayed_work sp_rtnl_task;
1607 struct delayed_work period_task;
1608 struct timer_list timer;
1609 int current_interval;
1612 u16 fw_drv_pulse_wr_seq;
1615 struct link_params link_params;
1616 struct link_vars link_vars;
1618 struct bnx2x_link_report_data last_reported_link;
1620 struct mdio_if_info mdio;
1622 struct bnx2x_common common;
1623 struct bnx2x_port port;
1625 struct cmng_init cmng;
1627 u32 mf_config[E1HVN_MAX];
1629 u32 path_has_ovlan; /* E3 */
1632 #define IS_MF(bp) (bp->mf_mode != 0)
1633 #define IS_MF_SI(bp) (bp->mf_mode == MULTI_FUNCTION_SI)
1634 #define IS_MF_SD(bp) (bp->mf_mode == MULTI_FUNCTION_SD)
1635 #define IS_MF_AFEX(bp) (bp->mf_mode == MULTI_FUNCTION_AFEX)
1641 u16 tx_quick_cons_trip_int;
1642 u16 tx_quick_cons_trip;
1646 u16 rx_quick_cons_trip_int;
1647 u16 rx_quick_cons_trip;
1650 /* Maximal coalescing timeout in us */
1651 #define BNX2X_MAX_COALESCE_TOUT (0xff*BNX2X_BTR)
1656 #define BNX2X_STATE_CLOSED 0
1657 #define BNX2X_STATE_OPENING_WAIT4_LOAD 0x1000
1658 #define BNX2X_STATE_OPENING_WAIT4_PORT 0x2000
1659 #define BNX2X_STATE_OPEN 0x3000
1660 #define BNX2X_STATE_CLOSING_WAIT4_HALT 0x4000
1661 #define BNX2X_STATE_CLOSING_WAIT4_DELETE 0x5000
1663 #define BNX2X_STATE_DIAG 0xe000
1664 #define BNX2X_STATE_ERROR 0xf000
1666 #define BNX2X_MAX_PRIORITY 8
1667 #define BNX2X_MAX_ENTRIES_PER_PRI 16
1668 #define BNX2X_MAX_COS 3
1669 #define BNX2X_MAX_TX_COS 2
1671 uint num_ethernet_queues;
1672 uint num_cnic_queues;
1673 int num_napi_queues;
1677 #define BNX2X_RX_MODE_NONE 0
1678 #define BNX2X_RX_MODE_NORMAL 1
1679 #define BNX2X_RX_MODE_ALLMULTI 2
1680 #define BNX2X_RX_MODE_PROMISC 3
1681 #define BNX2X_MAX_MULTICAST 64
1686 u8 min_msix_vec_cnt;
1689 dma_addr_t def_status_blk_mapping;
1691 struct bnx2x_slowpath *slowpath;
1692 dma_addr_t slowpath_mapping;
1694 /* Total number of FW statistics requests */
1698 * This is a memory buffer that will contain both statistics
1699 * ramrod request and data.
1702 dma_addr_t fw_stats_mapping;
1705 * FW statistics request shortcut (points at the
1706 * beginning of fw_stats buffer).
1708 struct bnx2x_fw_stats_req *fw_stats_req;
1709 dma_addr_t fw_stats_req_mapping;
1710 int fw_stats_req_sz;
1713 * FW statistics data shortcut (points at the beginning of
1714 * fw_stats buffer + fw_stats_req_sz).
1716 struct bnx2x_fw_stats_data *fw_stats_data;
1717 dma_addr_t fw_stats_data_mapping;
1718 int fw_stats_data_sz;
1720 /* For max 1024 cids (VF RSS), 32KB ILT page size and 1KB
1721 * context size we need 8 ILT entries.
1723 #define ILT_MAX_L2_LINES 32
1724 struct hw_context context[ILT_MAX_L2_LINES];
1726 struct bnx2x_ilt *ilt;
1727 #define BP_ILT(bp) ((bp)->ilt)
1728 #define ILT_MAX_LINES 256
1730 * Maximum supported number of RSS queues: number of IGU SBs minus one that goes
1733 #define BNX2X_MAX_RSS_COUNT(bp) ((bp)->igu_sb_cnt - CNIC_SUPPORT(bp))
1736 * Maximum CID count that might be required by the bnx2x:
1737 * Max RSS * Max_Tx_Multi_Cos + FCoE + iSCSI
1740 #define BNX2X_L2_CID_COUNT(bp) (BNX2X_NUM_ETH_QUEUES(bp) * BNX2X_MULTI_TX_COS \
1741 + CNIC_SUPPORT(bp) * (2 + UIO_CID_PAD(bp)))
1742 #define BNX2X_L2_MAX_CID(bp) (BNX2X_MAX_RSS_COUNT(bp) * BNX2X_MULTI_TX_COS \
1743 + CNIC_SUPPORT(bp) * (2 + UIO_CID_PAD(bp)))
1744 #define L2_ILT_LINES(bp) (DIV_ROUND_UP(BNX2X_L2_CID_COUNT(bp),\
1752 dma_addr_t t2_mapping;
1753 struct cnic_ops __rcu *cnic_ops;
1756 struct cnic_eth_dev cnic_eth_dev;
1757 union host_hc_status_block cnic_sb;
1758 dma_addr_t cnic_sb_mapping;
1759 struct eth_spe *cnic_kwq;
1760 struct eth_spe *cnic_kwq_prod;
1761 struct eth_spe *cnic_kwq_cons;
1762 struct eth_spe *cnic_kwq_last;
1763 u16 cnic_kwq_pending;
1764 u16 cnic_spq_pending;
1765 u8 fip_mac[ETH_ALEN];
1766 struct mutex cnic_mutex;
1767 struct bnx2x_vlan_mac_obj iscsi_l2_mac_obj;
1769 /* Start index of the "special" (CNIC related) L2 clients */
1773 /* used to synchronize dmae accesses */
1774 spinlock_t dmae_lock;
1776 /* used to protect the FW mail box */
1777 struct mutex fw_mb_mutex;
1779 /* used to synchronize stats collecting */
1782 /* used for synchronization of concurrent threads statistics handling */
1783 spinlock_t stats_lock;
1785 /* used by dmae command loader */
1786 struct dmae_command stats_dmae;
1790 struct bnx2x_eth_stats eth_stats;
1791 struct host_func_stats func_stats;
1792 struct bnx2x_eth_stats_old eth_stats_old;
1793 struct bnx2x_net_stats_old net_stats_old;
1794 struct bnx2x_fw_port_stats_old fw_stats_old;
1797 struct z_stream_s *strm;
1799 dma_addr_t gunzip_mapping;
1801 #define FW_BUF_SIZE 0x8000
1802 #define GUNZIP_BUF(bp) (bp->gunzip_buf)
1803 #define GUNZIP_PHYS(bp) (bp->gunzip_mapping)
1804 #define GUNZIP_OUTLEN(bp) (bp->gunzip_outlen)
1806 struct raw_op *init_ops;
1807 /* Init blocks offsets inside init_ops */
1808 u16 *init_ops_offsets;
1809 /* Data blob - has 32 bit granularity */
1811 u32 init_mode_flags;
1812 #define INIT_MODE_FLAGS(bp) (bp->init_mode_flags)
1813 /* Zipped PRAM blobs - raw data */
1814 const u8 *tsem_int_table_data;
1815 const u8 *tsem_pram_data;
1816 const u8 *usem_int_table_data;
1817 const u8 *usem_pram_data;
1818 const u8 *xsem_int_table_data;
1819 const u8 *xsem_pram_data;
1820 const u8 *csem_int_table_data;
1821 const u8 *csem_pram_data;
1822 #define INIT_OPS(bp) (bp->init_ops)
1823 #define INIT_OPS_OFFSETS(bp) (bp->init_ops_offsets)
1824 #define INIT_DATA(bp) (bp->init_data)
1825 #define INIT_TSEM_INT_TABLE_DATA(bp) (bp->tsem_int_table_data)
1826 #define INIT_TSEM_PRAM_DATA(bp) (bp->tsem_pram_data)
1827 #define INIT_USEM_INT_TABLE_DATA(bp) (bp->usem_int_table_data)
1828 #define INIT_USEM_PRAM_DATA(bp) (bp->usem_pram_data)
1829 #define INIT_XSEM_INT_TABLE_DATA(bp) (bp->xsem_int_table_data)
1830 #define INIT_XSEM_PRAM_DATA(bp) (bp->xsem_pram_data)
1831 #define INIT_CSEM_INT_TABLE_DATA(bp) (bp->csem_int_table_data)
1832 #define INIT_CSEM_PRAM_DATA(bp) (bp->csem_pram_data)
1834 #define PHY_FW_VER_LEN 20
1836 const struct firmware *firmware;
1838 struct bnx2x_vfdb *vfdb;
1839 #define IS_SRIOV(bp) ((bp)->vfdb)
1841 /* DCB support on/off */
1843 #define BNX2X_DCB_STATE_OFF 0
1844 #define BNX2X_DCB_STATE_ON 1
1846 /* DCBX engine mode */
1848 #define BNX2X_DCBX_ENABLED_OFF 0
1849 #define BNX2X_DCBX_ENABLED_ON_NEG_OFF 1
1850 #define BNX2X_DCBX_ENABLED_ON_NEG_ON 2
1851 #define BNX2X_DCBX_ENABLED_INVALID (-1)
1853 bool dcbx_mode_uset;
1855 struct bnx2x_config_dcbx_params dcbx_config_params;
1856 struct bnx2x_dcbx_port_params dcbx_port_params;
1859 /* CAM credit pools */
1861 /* used only in sriov */
1862 struct bnx2x_credit_pool_obj vlans_pool;
1864 struct bnx2x_credit_pool_obj macs_pool;
1866 /* RX_MODE object */
1867 struct bnx2x_rx_mode_obj rx_mode_obj;
1870 struct bnx2x_mcast_obj mcast_obj;
1872 /* RSS configuration object */
1873 struct bnx2x_rss_config_obj rss_conf_obj;
1875 /* Function State controlling object */
1876 struct bnx2x_func_sp_obj func_obj;
1878 unsigned long sp_state;
1880 /* operation indication for the sp_rtnl task */
1881 unsigned long sp_rtnl_state;
1883 /* DCBX Negotiation results */
1884 struct dcbx_features dcbx_local_feat;
1888 struct dcbx_features dcbx_remote_feat;
1889 u32 dcbx_remote_flags;
1891 /* AFEX: store default vlan used */
1892 int afex_def_vlan_tag;
1893 enum mf_cfg_afex_vlan_mode afex_vlan_mode;
1896 /* multiple tx classes of service */
1899 /* priority to cos mapping */
1903 u32 dump_preset_idx;
1905 struct semaphore stats_sema;
1907 u8 phys_port_id[ETH_ALEN];
1910 /* Tx queues may be less or equal to Rx queues */
1911 extern int num_queues;
1912 #define BNX2X_NUM_QUEUES(bp) (bp->num_queues)
1913 #define BNX2X_NUM_ETH_QUEUES(bp) ((bp)->num_ethernet_queues)
1914 #define BNX2X_NUM_NON_CNIC_QUEUES(bp) (BNX2X_NUM_QUEUES(bp) - \
1915 (bp)->num_cnic_queues)
1916 #define BNX2X_NUM_RX_QUEUES(bp) BNX2X_NUM_QUEUES(bp)
1918 #define is_multi(bp) (BNX2X_NUM_QUEUES(bp) > 1)
1920 #define BNX2X_MAX_QUEUES(bp) BNX2X_MAX_RSS_COUNT(bp)
1921 /* #define is_eth_multi(bp) (BNX2X_NUM_ETH_QUEUES(bp) > 1) */
1923 #define RSS_IPV4_CAP_MASK \
1924 TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV4_CAPABILITY
1926 #define RSS_IPV4_TCP_CAP_MASK \
1927 TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV4_TCP_CAPABILITY
1929 #define RSS_IPV6_CAP_MASK \
1930 TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV6_CAPABILITY
1932 #define RSS_IPV6_TCP_CAP_MASK \
1933 TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV6_TCP_CAPABILITY
1935 /* func init flags */
1936 #define FUNC_FLG_RSS 0x0001
1937 #define FUNC_FLG_STATS 0x0002
1938 /* removed FUNC_FLG_UNMATCHED 0x0004 */
1939 #define FUNC_FLG_TPA 0x0008
1940 #define FUNC_FLG_SPQ 0x0010
1941 #define FUNC_FLG_LEADING 0x0020 /* PF only */
1942 #define FUNC_FLG_LEADING_STATS 0x0040
1943 struct bnx2x_func_init_params {
1945 dma_addr_t fw_stat_map; /* valid iff FUNC_FLG_STATS */
1946 dma_addr_t spq_map; /* valid iff FUNC_FLG_SPQ */
1949 u16 func_id; /* abs fid */
1951 u16 spq_prod; /* valid iff FUNC_FLG_SPQ */
1954 #define for_each_cnic_queue(bp, var) \
1955 for ((var) = BNX2X_NUM_ETH_QUEUES(bp); (var) < BNX2X_NUM_QUEUES(bp); \
1957 if (skip_queue(bp, var)) \
1961 #define for_each_eth_queue(bp, var) \
1962 for ((var) = 0; (var) < BNX2X_NUM_ETH_QUEUES(bp); (var)++)
1964 #define for_each_nondefault_eth_queue(bp, var) \
1965 for ((var) = 1; (var) < BNX2X_NUM_ETH_QUEUES(bp); (var)++)
1967 #define for_each_queue(bp, var) \
1968 for ((var) = 0; (var) < BNX2X_NUM_QUEUES(bp); (var)++) \
1969 if (skip_queue(bp, var)) \
1973 /* Skip forwarding FP */
1974 #define for_each_valid_rx_queue(bp, var) \
1976 (var) < (CNIC_LOADED(bp) ? BNX2X_NUM_QUEUES(bp) : \
1977 BNX2X_NUM_ETH_QUEUES(bp)); \
1979 if (skip_rx_queue(bp, var)) \
1983 #define for_each_rx_queue_cnic(bp, var) \
1984 for ((var) = BNX2X_NUM_ETH_QUEUES(bp); (var) < BNX2X_NUM_QUEUES(bp); \
1986 if (skip_rx_queue(bp, var)) \
1990 #define for_each_rx_queue(bp, var) \
1991 for ((var) = 0; (var) < BNX2X_NUM_QUEUES(bp); (var)++) \
1992 if (skip_rx_queue(bp, var)) \
1997 #define for_each_valid_tx_queue(bp, var) \
1999 (var) < (CNIC_LOADED(bp) ? BNX2X_NUM_QUEUES(bp) : \
2000 BNX2X_NUM_ETH_QUEUES(bp)); \
2002 if (skip_tx_queue(bp, var)) \
2006 #define for_each_tx_queue_cnic(bp, var) \
2007 for ((var) = BNX2X_NUM_ETH_QUEUES(bp); (var) < BNX2X_NUM_QUEUES(bp); \
2009 if (skip_tx_queue(bp, var)) \
2013 #define for_each_tx_queue(bp, var) \
2014 for ((var) = 0; (var) < BNX2X_NUM_QUEUES(bp); (var)++) \
2015 if (skip_tx_queue(bp, var)) \
2019 #define for_each_nondefault_queue(bp, var) \
2020 for ((var) = 1; (var) < BNX2X_NUM_QUEUES(bp); (var)++) \
2021 if (skip_queue(bp, var)) \
2025 #define for_each_cos_in_tx_queue(fp, var) \
2026 for ((var) = 0; (var) < (fp)->max_cos; (var)++)
2029 * if FCOE l2 support is disabled and this is the fcoe L2 queue
2031 #define skip_rx_queue(bp, idx) (NO_FCOE(bp) && IS_FCOE_IDX(idx))
2034 * if FCOE l2 support is disabled and this is the fcoe L2 queue
2036 #define skip_tx_queue(bp, idx) (NO_FCOE(bp) && IS_FCOE_IDX(idx))
2038 #define skip_queue(bp, idx) (NO_FCOE(bp) && IS_FCOE_IDX(idx))
2041 * bnx2x_set_mac_one - configure a single MAC address
2043 * @bp: driver handle
2044 * @mac: MAC to configure
2045 * @obj: MAC object handle
2046 * @set: if 'true' add a new MAC, otherwise - delete
2047 * @mac_type: the type of the MAC to configure (e.g. ETH, UC list)
2048 * @ramrod_flags: RAMROD_XXX flags (e.g. RAMROD_CONT, RAMROD_COMP_WAIT)
2050 * Configures one MAC according to provided parameters or continues the
2051 * execution of previously scheduled commands if RAMROD_CONT is set in
2054 * Returns zero if operation has successfully completed, a positive value if the
2055 * operation has been successfully scheduled and a negative - if a requested
2056 * operations has failed.
2058 int bnx2x_set_mac_one(struct bnx2x *bp, u8 *mac,
2059 struct bnx2x_vlan_mac_obj *obj, bool set,
2060 int mac_type, unsigned long *ramrod_flags);
2062 * bnx2x_del_all_macs - delete all MACs configured for the specific MAC object
2064 * @bp: driver handle
2065 * @mac_obj: MAC object handle
2066 * @mac_type: type of the MACs to clear (BNX2X_XXX_MAC)
2067 * @wait_for_comp: if 'true' block until completion
2069 * Deletes all MACs of the specific type (e.g. ETH, UC list).
2071 * Returns zero if operation has successfully completed, a positive value if the
2072 * operation has been successfully scheduled and a negative - if a requested
2073 * operations has failed.
2075 int bnx2x_del_all_macs(struct bnx2x *bp,
2076 struct bnx2x_vlan_mac_obj *mac_obj,
2077 int mac_type, bool wait_for_comp);
2079 /* Init Function API */
2080 void bnx2x_func_init(struct bnx2x *bp, struct bnx2x_func_init_params *p);
2081 void bnx2x_init_sb(struct bnx2x *bp, dma_addr_t mapping, int vfid,
2082 u8 vf_valid, int fw_sb_id, int igu_sb_id);
2083 u32 bnx2x_get_pretend_reg(struct bnx2x *bp);
2084 int bnx2x_get_gpio(struct bnx2x *bp, int gpio_num, u8 port);
2085 int bnx2x_set_gpio(struct bnx2x *bp, int gpio_num, u32 mode, u8 port);
2086 int bnx2x_set_mult_gpio(struct bnx2x *bp, u8 pins, u32 mode);
2087 int bnx2x_set_gpio_int(struct bnx2x *bp, int gpio_num, u32 mode, u8 port);
2088 void bnx2x_read_mf_cfg(struct bnx2x *bp);
2090 int bnx2x_pretend_func(struct bnx2x *bp, u16 pretend_func_val);
2093 void bnx2x_read_dmae(struct bnx2x *bp, u32 src_addr, u32 len32);
2094 void bnx2x_write_dmae(struct bnx2x *bp, dma_addr_t dma_addr, u32 dst_addr,
2096 void bnx2x_post_dmae(struct bnx2x *bp, struct dmae_command *dmae, int idx);
2097 u32 bnx2x_dmae_opcode_add_comp(u32 opcode, u8 comp_type);
2098 u32 bnx2x_dmae_opcode_clr_src_reset(u32 opcode);
2099 u32 bnx2x_dmae_opcode(struct bnx2x *bp, u8 src_type, u8 dst_type,
2100 bool with_comp, u8 comp_type);
2102 void bnx2x_prep_dmae_with_comp(struct bnx2x *bp, struct dmae_command *dmae,
2103 u8 src_type, u8 dst_type);
2104 int bnx2x_issue_dmae_with_comp(struct bnx2x *bp, struct dmae_command *dmae,
2107 /* FLR related routines */
2108 u32 bnx2x_flr_clnup_poll_count(struct bnx2x *bp);
2109 void bnx2x_tx_hw_flushed(struct bnx2x *bp, u32 poll_count);
2110 int bnx2x_send_final_clnup(struct bnx2x *bp, u8 clnup_func, u32 poll_cnt);
2111 u8 bnx2x_is_pcie_pending(struct pci_dev *dev);
2112 int bnx2x_flr_clnup_poll_hw_counter(struct bnx2x *bp, u32 reg,
2113 char *msg, u32 poll_cnt);
2115 void bnx2x_calc_fc_adv(struct bnx2x *bp);
2116 int bnx2x_sp_post(struct bnx2x *bp, int command, int cid,
2117 u32 data_hi, u32 data_lo, int cmd_type);
2118 void bnx2x_update_coalesce(struct bnx2x *bp);
2119 int bnx2x_get_cur_phy_idx(struct bnx2x *bp);
2121 bool bnx2x_port_after_undi(struct bnx2x *bp);
2123 static inline u32 reg_poll(struct bnx2x *bp, u32 reg, u32 expected, int ms,
2129 val = REG_RD(bp, reg);
2130 if (val == expected)
2140 void bnx2x_igu_clear_sb_gen(struct bnx2x *bp, u8 func, u8 idu_sb_id,
2143 #define BNX2X_ILT_ZALLOC(x, y, size) \
2144 x = dma_zalloc_coherent(&bp->pdev->dev, size, y, GFP_KERNEL)
2146 #define BNX2X_ILT_FREE(x, y, size) \
2149 dma_free_coherent(&bp->pdev->dev, size, x, y); \
2155 #define ILOG2(x) (ilog2((x)))
2157 #define ILT_NUM_PAGE_ENTRIES (3072)
2158 /* In 57710/11 we use whole table since we have 8 func
2159 * In 57712 we have only 4 func, but use same size per func, then only half of
2162 #define ILT_PER_FUNC (ILT_NUM_PAGE_ENTRIES/8)
2164 #define FUNC_ILT_BASE(func) (func * ILT_PER_FUNC)
2166 * the phys address is shifted right 12 bits and has an added
2167 * 1=valid bit added to the 53rd bit
2168 * then since this is a wide register(TM)
2169 * we split it into two 32 bit writes
2171 #define ONCHIP_ADDR1(x) ((u32)(((u64)x >> 12) & 0xFFFFFFFF))
2172 #define ONCHIP_ADDR2(x) ((u32)((1 << 20) | ((u64)x >> 44)))
2174 /* load/unload mode */
2175 #define LOAD_NORMAL 0
2178 #define LOAD_LOOPBACK_EXT 3
2179 #define UNLOAD_NORMAL 0
2180 #define UNLOAD_CLOSE 1
2181 #define UNLOAD_RECOVERY 2
2183 /* DMAE command defines */
2184 #define DMAE_TIMEOUT -1
2185 #define DMAE_PCI_ERROR -2 /* E2 and onward */
2186 #define DMAE_NOT_RDY -3
2187 #define DMAE_PCI_ERR_FLAG 0x80000000
2189 #define DMAE_SRC_PCI 0
2190 #define DMAE_SRC_GRC 1
2192 #define DMAE_DST_NONE 0
2193 #define DMAE_DST_PCI 1
2194 #define DMAE_DST_GRC 2
2196 #define DMAE_COMP_PCI 0
2197 #define DMAE_COMP_GRC 1
2199 /* E2 and onward - PCI error handling in the completion */
2201 #define DMAE_COMP_REGULAR 0
2202 #define DMAE_COM_SET_ERR 1
2204 #define DMAE_CMD_SRC_PCI (DMAE_SRC_PCI << \
2205 DMAE_COMMAND_SRC_SHIFT)
2206 #define DMAE_CMD_SRC_GRC (DMAE_SRC_GRC << \
2207 DMAE_COMMAND_SRC_SHIFT)
2209 #define DMAE_CMD_DST_PCI (DMAE_DST_PCI << \
2210 DMAE_COMMAND_DST_SHIFT)
2211 #define DMAE_CMD_DST_GRC (DMAE_DST_GRC << \
2212 DMAE_COMMAND_DST_SHIFT)
2214 #define DMAE_CMD_C_DST_PCI (DMAE_COMP_PCI << \
2215 DMAE_COMMAND_C_DST_SHIFT)
2216 #define DMAE_CMD_C_DST_GRC (DMAE_COMP_GRC << \
2217 DMAE_COMMAND_C_DST_SHIFT)
2219 #define DMAE_CMD_C_ENABLE DMAE_COMMAND_C_TYPE_ENABLE
2221 #define DMAE_CMD_ENDIANITY_NO_SWAP (0 << DMAE_COMMAND_ENDIANITY_SHIFT)
2222 #define DMAE_CMD_ENDIANITY_B_SWAP (1 << DMAE_COMMAND_ENDIANITY_SHIFT)
2223 #define DMAE_CMD_ENDIANITY_DW_SWAP (2 << DMAE_COMMAND_ENDIANITY_SHIFT)
2224 #define DMAE_CMD_ENDIANITY_B_DW_SWAP (3 << DMAE_COMMAND_ENDIANITY_SHIFT)
2226 #define DMAE_CMD_PORT_0 0
2227 #define DMAE_CMD_PORT_1 DMAE_COMMAND_PORT
2229 #define DMAE_CMD_SRC_RESET DMAE_COMMAND_SRC_RESET
2230 #define DMAE_CMD_DST_RESET DMAE_COMMAND_DST_RESET
2231 #define DMAE_CMD_E1HVN_SHIFT DMAE_COMMAND_E1HVN_SHIFT
2233 #define DMAE_SRC_PF 0
2234 #define DMAE_SRC_VF 1
2236 #define DMAE_DST_PF 0
2237 #define DMAE_DST_VF 1
2239 #define DMAE_C_SRC 0
2240 #define DMAE_C_DST 1
2242 #define DMAE_LEN32_RD_MAX 0x80
2243 #define DMAE_LEN32_WR_MAX(bp) (CHIP_IS_E1(bp) ? 0x400 : 0x2000)
2245 #define DMAE_COMP_VAL 0x60d0d0ae /* E2 and on - upper bit
2249 #define MAX_DMAE_C_PER_PORT 8
2250 #define INIT_DMAE_C(bp) (BP_PORT(bp) * MAX_DMAE_C_PER_PORT + \
2252 #define PMF_DMAE_C(bp) (BP_PORT(bp) * MAX_DMAE_C_PER_PORT + \
2255 /* PCIE link and speed */
2256 #define PCICFG_LINK_WIDTH 0x1f00000
2257 #define PCICFG_LINK_WIDTH_SHIFT 20
2258 #define PCICFG_LINK_SPEED 0xf0000
2259 #define PCICFG_LINK_SPEED_SHIFT 16
2261 #define BNX2X_NUM_TESTS_SF 7
2262 #define BNX2X_NUM_TESTS_MF 3
2263 #define BNX2X_NUM_TESTS(bp) (IS_MF(bp) ? BNX2X_NUM_TESTS_MF : \
2264 IS_VF(bp) ? 0 : BNX2X_NUM_TESTS_SF)
2266 #define BNX2X_PHY_LOOPBACK 0
2267 #define BNX2X_MAC_LOOPBACK 1
2268 #define BNX2X_EXT_LOOPBACK 2
2269 #define BNX2X_PHY_LOOPBACK_FAILED 1
2270 #define BNX2X_MAC_LOOPBACK_FAILED 2
2271 #define BNX2X_EXT_LOOPBACK_FAILED 3
2272 #define BNX2X_LOOPBACK_FAILED (BNX2X_MAC_LOOPBACK_FAILED | \
2273 BNX2X_PHY_LOOPBACK_FAILED)
2275 #define STROM_ASSERT_ARRAY_SIZE 50
2277 /* must be used on a CID before placing it on a HW ring */
2278 #define HW_CID(bp, x) ((BP_PORT(bp) << 23) | \
2279 (BP_VN(bp) << BNX2X_SWCID_SHIFT) | \
2282 #define SP_DESC_CNT (BCM_PAGE_SIZE / sizeof(struct eth_spe))
2283 #define MAX_SP_DESC_CNT (SP_DESC_CNT - 1)
2286 #define MAX_SPQ_PENDING 8
2288 /* CMNG constants, as derived from system spec calculations */
2289 /* default MIN rate in case VNIC min rate is configured to zero - 100Mbps */
2290 #define DEF_MIN_RATE 100
2291 /* resolution of the rate shaping timer - 400 usec */
2292 #define RS_PERIODIC_TIMEOUT_USEC 400
2293 /* number of bytes in single QM arbitration cycle -
2294 * coefficient for calculating the fairness timer */
2295 #define QM_ARB_BYTES 160000
2296 /* resolution of Min algorithm 1:100 */
2298 /* how many bytes above threshold for the minimal credit of Min algorithm*/
2299 #define MIN_ABOVE_THRESH 32768
2300 /* Fairness algorithm integration time coefficient -
2301 * for calculating the actual Tfair */
2302 #define T_FAIR_COEF ((MIN_ABOVE_THRESH + QM_ARB_BYTES) * 8 * MIN_RES)
2303 /* Memory of fairness algorithm . 2 cycles */
2306 #define ATTN_NIG_FOR_FUNC (1L << 8)
2307 #define ATTN_SW_TIMER_4_FUNC (1L << 9)
2308 #define GPIO_2_FUNC (1L << 10)
2309 #define GPIO_3_FUNC (1L << 11)
2310 #define GPIO_4_FUNC (1L << 12)
2311 #define ATTN_GENERAL_ATTN_1 (1L << 13)
2312 #define ATTN_GENERAL_ATTN_2 (1L << 14)
2313 #define ATTN_GENERAL_ATTN_3 (1L << 15)
2314 #define ATTN_GENERAL_ATTN_4 (1L << 13)
2315 #define ATTN_GENERAL_ATTN_5 (1L << 14)
2316 #define ATTN_GENERAL_ATTN_6 (1L << 15)
2318 #define ATTN_HARD_WIRED_MASK 0xff00
2319 #define ATTENTION_ID 4
2321 #define IS_MF_STORAGE_ONLY(bp) (IS_MF_STORAGE_SD(bp) || \
2322 IS_MF_FCOE_AFEX(bp))
2324 /* stuff added to make the code fit 80Col */
2326 #define BNX2X_PMF_LINK_ASSERT \
2327 GENERAL_ATTEN_OFFSET(LINK_SYNC_ATTENTION_BIT_FUNC_0 + BP_FUNC(bp))
2329 #define BNX2X_MC_ASSERT_BITS \
2330 (GENERAL_ATTEN_OFFSET(TSTORM_FATAL_ASSERT_ATTENTION_BIT) | \
2331 GENERAL_ATTEN_OFFSET(USTORM_FATAL_ASSERT_ATTENTION_BIT) | \
2332 GENERAL_ATTEN_OFFSET(CSTORM_FATAL_ASSERT_ATTENTION_BIT) | \
2333 GENERAL_ATTEN_OFFSET(XSTORM_FATAL_ASSERT_ATTENTION_BIT))
2335 #define BNX2X_MCP_ASSERT \
2336 GENERAL_ATTEN_OFFSET(MCP_FATAL_ASSERT_ATTENTION_BIT)
2338 #define BNX2X_GRC_TIMEOUT GENERAL_ATTEN_OFFSET(LATCHED_ATTN_TIMEOUT_GRC)
2339 #define BNX2X_GRC_RSV (GENERAL_ATTEN_OFFSET(LATCHED_ATTN_RBCR) | \
2340 GENERAL_ATTEN_OFFSET(LATCHED_ATTN_RBCT) | \
2341 GENERAL_ATTEN_OFFSET(LATCHED_ATTN_RBCN) | \
2342 GENERAL_ATTEN_OFFSET(LATCHED_ATTN_RBCU) | \
2343 GENERAL_ATTEN_OFFSET(LATCHED_ATTN_RBCP) | \
2344 GENERAL_ATTEN_OFFSET(LATCHED_ATTN_RSVD_GRC))
2346 #define HW_INTERRUT_ASSERT_SET_0 \
2347 (AEU_INPUTS_ATTN_BITS_TSDM_HW_INTERRUPT | \
2348 AEU_INPUTS_ATTN_BITS_TCM_HW_INTERRUPT | \
2349 AEU_INPUTS_ATTN_BITS_TSEMI_HW_INTERRUPT | \
2350 AEU_INPUTS_ATTN_BITS_BRB_HW_INTERRUPT | \
2351 AEU_INPUTS_ATTN_BITS_PBCLIENT_HW_INTERRUPT)
2352 #define HW_PRTY_ASSERT_SET_0 (AEU_INPUTS_ATTN_BITS_BRB_PARITY_ERROR | \
2353 AEU_INPUTS_ATTN_BITS_PARSER_PARITY_ERROR | \
2354 AEU_INPUTS_ATTN_BITS_TSDM_PARITY_ERROR | \
2355 AEU_INPUTS_ATTN_BITS_SEARCHER_PARITY_ERROR |\
2356 AEU_INPUTS_ATTN_BITS_TSEMI_PARITY_ERROR |\
2357 AEU_INPUTS_ATTN_BITS_TCM_PARITY_ERROR |\
2358 AEU_INPUTS_ATTN_BITS_PBCLIENT_PARITY_ERROR)
2359 #define HW_INTERRUT_ASSERT_SET_1 \
2360 (AEU_INPUTS_ATTN_BITS_QM_HW_INTERRUPT | \
2361 AEU_INPUTS_ATTN_BITS_TIMERS_HW_INTERRUPT | \
2362 AEU_INPUTS_ATTN_BITS_XSDM_HW_INTERRUPT | \
2363 AEU_INPUTS_ATTN_BITS_XCM_HW_INTERRUPT | \
2364 AEU_INPUTS_ATTN_BITS_XSEMI_HW_INTERRUPT | \
2365 AEU_INPUTS_ATTN_BITS_USDM_HW_INTERRUPT | \
2366 AEU_INPUTS_ATTN_BITS_UCM_HW_INTERRUPT | \
2367 AEU_INPUTS_ATTN_BITS_USEMI_HW_INTERRUPT | \
2368 AEU_INPUTS_ATTN_BITS_UPB_HW_INTERRUPT | \
2369 AEU_INPUTS_ATTN_BITS_CSDM_HW_INTERRUPT | \
2370 AEU_INPUTS_ATTN_BITS_CCM_HW_INTERRUPT)
2371 #define HW_PRTY_ASSERT_SET_1 (AEU_INPUTS_ATTN_BITS_PBF_PARITY_ERROR |\
2372 AEU_INPUTS_ATTN_BITS_QM_PARITY_ERROR | \
2373 AEU_INPUTS_ATTN_BITS_TIMERS_PARITY_ERROR |\
2374 AEU_INPUTS_ATTN_BITS_XSDM_PARITY_ERROR | \
2375 AEU_INPUTS_ATTN_BITS_XCM_PARITY_ERROR |\
2376 AEU_INPUTS_ATTN_BITS_XSEMI_PARITY_ERROR | \
2377 AEU_INPUTS_ATTN_BITS_DOORBELLQ_PARITY_ERROR |\
2378 AEU_INPUTS_ATTN_BITS_NIG_PARITY_ERROR |\
2379 AEU_INPUTS_ATTN_BITS_VAUX_PCI_CORE_PARITY_ERROR |\
2380 AEU_INPUTS_ATTN_BITS_DEBUG_PARITY_ERROR | \
2381 AEU_INPUTS_ATTN_BITS_USDM_PARITY_ERROR | \
2382 AEU_INPUTS_ATTN_BITS_UCM_PARITY_ERROR |\
2383 AEU_INPUTS_ATTN_BITS_USEMI_PARITY_ERROR | \
2384 AEU_INPUTS_ATTN_BITS_UPB_PARITY_ERROR | \
2385 AEU_INPUTS_ATTN_BITS_CSDM_PARITY_ERROR |\
2386 AEU_INPUTS_ATTN_BITS_CCM_PARITY_ERROR)
2387 #define HW_INTERRUT_ASSERT_SET_2 \
2388 (AEU_INPUTS_ATTN_BITS_CSEMI_HW_INTERRUPT | \
2389 AEU_INPUTS_ATTN_BITS_CDU_HW_INTERRUPT | \
2390 AEU_INPUTS_ATTN_BITS_DMAE_HW_INTERRUPT | \
2391 AEU_INPUTS_ATTN_BITS_PXPPCICLOCKCLIENT_HW_INTERRUPT |\
2392 AEU_INPUTS_ATTN_BITS_MISC_HW_INTERRUPT)
2393 #define HW_PRTY_ASSERT_SET_2 (AEU_INPUTS_ATTN_BITS_CSEMI_PARITY_ERROR | \
2394 AEU_INPUTS_ATTN_BITS_PXP_PARITY_ERROR | \
2395 AEU_INPUTS_ATTN_BITS_PXPPCICLOCKCLIENT_PARITY_ERROR |\
2396 AEU_INPUTS_ATTN_BITS_CFC_PARITY_ERROR | \
2397 AEU_INPUTS_ATTN_BITS_CDU_PARITY_ERROR | \
2398 AEU_INPUTS_ATTN_BITS_DMAE_PARITY_ERROR |\
2399 AEU_INPUTS_ATTN_BITS_IGU_PARITY_ERROR | \
2400 AEU_INPUTS_ATTN_BITS_MISC_PARITY_ERROR)
2402 #define HW_PRTY_ASSERT_SET_3 (AEU_INPUTS_ATTN_BITS_MCP_LATCHED_ROM_PARITY | \
2403 AEU_INPUTS_ATTN_BITS_MCP_LATCHED_UMP_RX_PARITY | \
2404 AEU_INPUTS_ATTN_BITS_MCP_LATCHED_UMP_TX_PARITY | \
2405 AEU_INPUTS_ATTN_BITS_MCP_LATCHED_SCPAD_PARITY)
2407 #define HW_PRTY_ASSERT_SET_4 (AEU_INPUTS_ATTN_BITS_PGLUE_PARITY_ERROR | \
2408 AEU_INPUTS_ATTN_BITS_ATC_PARITY_ERROR)
2410 #define MULTI_MASK 0x7f
2412 #define DEF_USB_FUNC_OFF offsetof(struct cstorm_def_status_block_u, func)
2413 #define DEF_CSB_FUNC_OFF offsetof(struct cstorm_def_status_block_c, func)
2414 #define DEF_XSB_FUNC_OFF offsetof(struct xstorm_def_status_block, func)
2415 #define DEF_TSB_FUNC_OFF offsetof(struct tstorm_def_status_block, func)
2417 #define DEF_USB_IGU_INDEX_OFF \
2418 offsetof(struct cstorm_def_status_block_u, igu_index)
2419 #define DEF_CSB_IGU_INDEX_OFF \
2420 offsetof(struct cstorm_def_status_block_c, igu_index)
2421 #define DEF_XSB_IGU_INDEX_OFF \
2422 offsetof(struct xstorm_def_status_block, igu_index)
2423 #define DEF_TSB_IGU_INDEX_OFF \
2424 offsetof(struct tstorm_def_status_block, igu_index)
2426 #define DEF_USB_SEGMENT_OFF \
2427 offsetof(struct cstorm_def_status_block_u, segment)
2428 #define DEF_CSB_SEGMENT_OFF \
2429 offsetof(struct cstorm_def_status_block_c, segment)
2430 #define DEF_XSB_SEGMENT_OFF \
2431 offsetof(struct xstorm_def_status_block, segment)
2432 #define DEF_TSB_SEGMENT_OFF \
2433 offsetof(struct tstorm_def_status_block, segment)
2435 #define BNX2X_SP_DSB_INDEX \
2436 (&bp->def_status_blk->sp_sb.\
2437 index_values[HC_SP_INDEX_ETH_DEF_CONS])
2439 #define CAM_IS_INVALID(x) \
2440 (GET_FLAG(x.flags, \
2441 MAC_CONFIGURATION_ENTRY_ACTION_TYPE) == \
2442 (T_ETH_MAC_COMMAND_INVALIDATE))
2444 /* Number of u32 elements in MC hash array */
2445 #define MC_HASH_SIZE 8
2446 #define MC_HASH_OFFSET(bp, i) (BAR_TSTRORM_INTMEM + \
2447 TSTORM_APPROXIMATE_MATCH_MULTICAST_FILTERING_OFFSET(BP_FUNC(bp)) + i*4)
2449 #ifndef PXP2_REG_PXP2_INT_STS
2450 #define PXP2_REG_PXP2_INT_STS PXP2_REG_PXP2_INT_STS_0
2453 #ifndef ETH_MAX_RX_CLIENTS_E2
2454 #define ETH_MAX_RX_CLIENTS_E2 ETH_MAX_RX_CLIENTS_E1H
2457 #define BNX2X_VPD_LEN 128
2458 #define VENDOR_ID_LEN 4
2460 #define VF_ACQUIRE_THRESH 3
2461 #define VF_ACQUIRE_MAC_FILTERS 1
2462 #define VF_ACQUIRE_MC_FILTERS 10
2464 #define GOOD_ME_REG(me_reg) (((me_reg) & ME_REG_VF_VALID) && \
2465 (!((me_reg) & ME_REG_VF_ERR)))
2466 int bnx2x_nic_load_analyze_req(struct bnx2x *bp, u32 load_code);
2467 /* Congestion management fairness mode */
2468 #define CMNG_FNS_NONE 0
2469 #define CMNG_FNS_MINMAX 1
2471 #define HC_SEG_ACCESS_DEF 0 /*Driver decision 0-3*/
2472 #define HC_SEG_ACCESS_ATTN 4
2473 #define HC_SEG_ACCESS_NORM 0 /*Driver decision 0-1*/
2475 static const u32 dmae_reg_go_c[] = {
2476 DMAE_REG_GO_C0, DMAE_REG_GO_C1, DMAE_REG_GO_C2, DMAE_REG_GO_C3,
2477 DMAE_REG_GO_C4, DMAE_REG_GO_C5, DMAE_REG_GO_C6, DMAE_REG_GO_C7,
2478 DMAE_REG_GO_C8, DMAE_REG_GO_C9, DMAE_REG_GO_C10, DMAE_REG_GO_C11,
2479 DMAE_REG_GO_C12, DMAE_REG_GO_C13, DMAE_REG_GO_C14, DMAE_REG_GO_C15
2482 void bnx2x_set_ethtool_ops(struct bnx2x *bp, struct net_device *netdev);
2483 void bnx2x_notify_link_changed(struct bnx2x *bp);
2485 #define BNX2X_MF_SD_PROTOCOL(bp) \
2486 ((bp)->mf_config[BP_VN(bp)] & FUNC_MF_CFG_PROTOCOL_MASK)
2488 #define BNX2X_IS_MF_SD_PROTOCOL_ISCSI(bp) \
2489 (BNX2X_MF_SD_PROTOCOL(bp) == FUNC_MF_CFG_PROTOCOL_ISCSI)
2491 #define BNX2X_IS_MF_SD_PROTOCOL_FCOE(bp) \
2492 (BNX2X_MF_SD_PROTOCOL(bp) == FUNC_MF_CFG_PROTOCOL_FCOE)
2494 #define IS_MF_ISCSI_SD(bp) (IS_MF_SD(bp) && BNX2X_IS_MF_SD_PROTOCOL_ISCSI(bp))
2495 #define IS_MF_FCOE_SD(bp) (IS_MF_SD(bp) && BNX2X_IS_MF_SD_PROTOCOL_FCOE(bp))
2497 #define BNX2X_MF_EXT_PROTOCOL_FCOE(bp) ((bp)->mf_ext_config & \
2498 MACP_FUNC_CFG_FLAGS_FCOE_OFFLOAD)
2500 #define IS_MF_FCOE_AFEX(bp) (IS_MF_AFEX(bp) && BNX2X_MF_EXT_PROTOCOL_FCOE(bp))
2501 #define IS_MF_STORAGE_SD(bp) (IS_MF_SD(bp) && \
2502 (BNX2X_IS_MF_SD_PROTOCOL_ISCSI(bp) || \
2503 BNX2X_IS_MF_SD_PROTOCOL_FCOE(bp)))
2505 #define SET_FLAG(value, mask, flag) \
2507 (value) &= ~(mask);\
2508 (value) |= ((flag) << (mask##_SHIFT));\
2511 #define GET_FLAG(value, mask) \
2512 (((value) & (mask)) >> (mask##_SHIFT))
2514 #define GET_FIELD(value, fname) \
2515 (((value) & (fname##_MASK)) >> (fname##_SHIFT))
2524 void bnx2x_set_local_cmng(struct bnx2x *bp);
2526 #define MCPR_SCRATCH_BASE(bp) \
2527 (CHIP_IS_E1x(bp) ? MCP_REG_MCPR_SCRATCH : MCP_A_REG_MCPR_SCRATCH)
2529 #define E1H_MAX_MF_SB_COUNT (HC_SB_MAX_SB_E1X/(E1HVN_MAX * PORT_MAX))
2531 #endif /* bnx2x.h */