1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * Driver for BCM963xx builtin Ethernet mac
5 * Copyright (C) 2008 Maxime Bizon <mbizon@freebox.fr>
7 #include <linux/init.h>
8 #include <linux/interrupt.h>
9 #include <linux/module.h>
10 #include <linux/clk.h>
11 #include <linux/etherdevice.h>
12 #include <linux/slab.h>
13 #include <linux/delay.h>
14 #include <linux/ethtool.h>
15 #include <linux/crc32.h>
16 #include <linux/err.h>
17 #include <linux/dma-mapping.h>
18 #include <linux/platform_device.h>
19 #include <linux/if_vlan.h>
21 #include <bcm63xx_dev_enet.h>
22 #include "bcm63xx_enet.h"
24 static char bcm_enet_driver_name[] = "bcm63xx_enet";
26 static int copybreak __read_mostly = 128;
27 module_param(copybreak, int, 0);
28 MODULE_PARM_DESC(copybreak, "Receive copy threshold");
30 /* io registers memory shared between all devices */
31 static void __iomem *bcm_enet_shared_base[3];
34 * io helpers to access mac registers
36 static inline u32 enet_readl(struct bcm_enet_priv *priv, u32 off)
38 return bcm_readl(priv->base + off);
41 static inline void enet_writel(struct bcm_enet_priv *priv,
44 bcm_writel(val, priv->base + off);
48 * io helpers to access switch registers
50 static inline u32 enetsw_readl(struct bcm_enet_priv *priv, u32 off)
52 return bcm_readl(priv->base + off);
55 static inline void enetsw_writel(struct bcm_enet_priv *priv,
58 bcm_writel(val, priv->base + off);
61 static inline u16 enetsw_readw(struct bcm_enet_priv *priv, u32 off)
63 return bcm_readw(priv->base + off);
66 static inline void enetsw_writew(struct bcm_enet_priv *priv,
69 bcm_writew(val, priv->base + off);
72 static inline u8 enetsw_readb(struct bcm_enet_priv *priv, u32 off)
74 return bcm_readb(priv->base + off);
77 static inline void enetsw_writeb(struct bcm_enet_priv *priv,
80 bcm_writeb(val, priv->base + off);
84 /* io helpers to access shared registers */
85 static inline u32 enet_dma_readl(struct bcm_enet_priv *priv, u32 off)
87 return bcm_readl(bcm_enet_shared_base[0] + off);
90 static inline void enet_dma_writel(struct bcm_enet_priv *priv,
93 bcm_writel(val, bcm_enet_shared_base[0] + off);
96 static inline u32 enet_dmac_readl(struct bcm_enet_priv *priv, u32 off, int chan)
98 return bcm_readl(bcm_enet_shared_base[1] +
99 bcm63xx_enetdmacreg(off) + chan * priv->dma_chan_width);
102 static inline void enet_dmac_writel(struct bcm_enet_priv *priv,
103 u32 val, u32 off, int chan)
105 bcm_writel(val, bcm_enet_shared_base[1] +
106 bcm63xx_enetdmacreg(off) + chan * priv->dma_chan_width);
109 static inline u32 enet_dmas_readl(struct bcm_enet_priv *priv, u32 off, int chan)
111 return bcm_readl(bcm_enet_shared_base[2] + off + chan * priv->dma_chan_width);
114 static inline void enet_dmas_writel(struct bcm_enet_priv *priv,
115 u32 val, u32 off, int chan)
117 bcm_writel(val, bcm_enet_shared_base[2] + off + chan * priv->dma_chan_width);
121 * write given data into mii register and wait for transfer to end
122 * with timeout (average measured transfer time is 25us)
124 static int do_mdio_op(struct bcm_enet_priv *priv, unsigned int data)
128 /* make sure mii interrupt status is cleared */
129 enet_writel(priv, ENET_IR_MII, ENET_IR_REG);
131 enet_writel(priv, data, ENET_MIIDATA_REG);
134 /* busy wait on mii interrupt bit, with timeout */
137 if (enet_readl(priv, ENET_IR_REG) & ENET_IR_MII)
140 } while (limit-- > 0);
142 return (limit < 0) ? 1 : 0;
146 * MII internal read callback
148 static int bcm_enet_mdio_read(struct bcm_enet_priv *priv, int mii_id,
153 tmp = regnum << ENET_MIIDATA_REG_SHIFT;
154 tmp |= 0x2 << ENET_MIIDATA_TA_SHIFT;
155 tmp |= mii_id << ENET_MIIDATA_PHYID_SHIFT;
156 tmp |= ENET_MIIDATA_OP_READ_MASK;
158 if (do_mdio_op(priv, tmp))
161 val = enet_readl(priv, ENET_MIIDATA_REG);
167 * MII internal write callback
169 static int bcm_enet_mdio_write(struct bcm_enet_priv *priv, int mii_id,
170 int regnum, u16 value)
174 tmp = (value & 0xffff) << ENET_MIIDATA_DATA_SHIFT;
175 tmp |= 0x2 << ENET_MIIDATA_TA_SHIFT;
176 tmp |= regnum << ENET_MIIDATA_REG_SHIFT;
177 tmp |= mii_id << ENET_MIIDATA_PHYID_SHIFT;
178 tmp |= ENET_MIIDATA_OP_WRITE_MASK;
180 (void)do_mdio_op(priv, tmp);
185 * MII read callback from phylib
187 static int bcm_enet_mdio_read_phylib(struct mii_bus *bus, int mii_id,
190 return bcm_enet_mdio_read(bus->priv, mii_id, regnum);
194 * MII write callback from phylib
196 static int bcm_enet_mdio_write_phylib(struct mii_bus *bus, int mii_id,
197 int regnum, u16 value)
199 return bcm_enet_mdio_write(bus->priv, mii_id, regnum, value);
203 * MII read callback from mii core
205 static int bcm_enet_mdio_read_mii(struct net_device *dev, int mii_id,
208 return bcm_enet_mdio_read(netdev_priv(dev), mii_id, regnum);
212 * MII write callback from mii core
214 static void bcm_enet_mdio_write_mii(struct net_device *dev, int mii_id,
215 int regnum, int value)
217 bcm_enet_mdio_write(netdev_priv(dev), mii_id, regnum, value);
223 static int bcm_enet_refill_rx(struct net_device *dev, bool napi_mode)
225 struct bcm_enet_priv *priv;
227 priv = netdev_priv(dev);
229 while (priv->rx_desc_count < priv->rx_ring_size) {
230 struct bcm_enet_desc *desc;
234 desc_idx = priv->rx_dirty_desc;
235 desc = &priv->rx_desc_cpu[desc_idx];
237 if (!priv->rx_buf[desc_idx]) {
240 if (likely(napi_mode))
241 buf = napi_alloc_frag(priv->rx_frag_size);
243 buf = netdev_alloc_frag(priv->rx_frag_size);
246 priv->rx_buf[desc_idx] = buf;
247 desc->address = dma_map_single(&priv->pdev->dev,
248 buf + priv->rx_buf_offset,
253 len_stat = priv->rx_buf_size << DMADESC_LENGTH_SHIFT;
254 len_stat |= DMADESC_OWNER_MASK;
255 if (priv->rx_dirty_desc == priv->rx_ring_size - 1) {
256 len_stat |= (DMADESC_WRAP_MASK >> priv->dma_desc_shift);
257 priv->rx_dirty_desc = 0;
259 priv->rx_dirty_desc++;
262 desc->len_stat = len_stat;
264 priv->rx_desc_count++;
266 /* tell dma engine we allocated one buffer */
267 if (priv->dma_has_sram)
268 enet_dma_writel(priv, 1, ENETDMA_BUFALLOC_REG(priv->rx_chan));
270 enet_dmac_writel(priv, 1, ENETDMAC_BUFALLOC, priv->rx_chan);
273 /* If rx ring is still empty, set a timer to try allocating
274 * again at a later time. */
275 if (priv->rx_desc_count == 0 && netif_running(dev)) {
276 dev_warn(&priv->pdev->dev, "unable to refill rx ring\n");
277 priv->rx_timeout.expires = jiffies + HZ;
278 add_timer(&priv->rx_timeout);
285 * timer callback to defer refill rx queue in case we're OOM
287 static void bcm_enet_refill_rx_timer(struct timer_list *t)
289 struct bcm_enet_priv *priv = from_timer(priv, t, rx_timeout);
290 struct net_device *dev = priv->net_dev;
292 spin_lock(&priv->rx_lock);
293 bcm_enet_refill_rx(dev, false);
294 spin_unlock(&priv->rx_lock);
298 * extract packet from rx queue
300 static int bcm_enet_receive_queue(struct net_device *dev, int budget)
302 struct bcm_enet_priv *priv;
303 struct list_head rx_list;
307 priv = netdev_priv(dev);
308 INIT_LIST_HEAD(&rx_list);
309 kdev = &priv->pdev->dev;
312 /* don't scan ring further than number of refilled
314 if (budget > priv->rx_desc_count)
315 budget = priv->rx_desc_count;
318 struct bcm_enet_desc *desc;
325 desc_idx = priv->rx_curr_desc;
326 desc = &priv->rx_desc_cpu[desc_idx];
328 /* make sure we actually read the descriptor status at
332 len_stat = desc->len_stat;
334 /* break if dma ownership belongs to hw */
335 if (len_stat & DMADESC_OWNER_MASK)
339 priv->rx_curr_desc++;
340 if (priv->rx_curr_desc == priv->rx_ring_size)
341 priv->rx_curr_desc = 0;
343 /* if the packet does not have start of packet _and_
344 * end of packet flag set, then just recycle it */
345 if ((len_stat & (DMADESC_ESOP_MASK >> priv->dma_desc_shift)) !=
346 (DMADESC_ESOP_MASK >> priv->dma_desc_shift)) {
347 dev->stats.rx_dropped++;
351 /* recycle packet if it's marked as bad */
352 if (!priv->enet_is_sw &&
353 unlikely(len_stat & DMADESC_ERR_MASK)) {
354 dev->stats.rx_errors++;
356 if (len_stat & DMADESC_OVSIZE_MASK)
357 dev->stats.rx_length_errors++;
358 if (len_stat & DMADESC_CRC_MASK)
359 dev->stats.rx_crc_errors++;
360 if (len_stat & DMADESC_UNDER_MASK)
361 dev->stats.rx_frame_errors++;
362 if (len_stat & DMADESC_OV_MASK)
363 dev->stats.rx_fifo_errors++;
368 buf = priv->rx_buf[desc_idx];
369 len = (len_stat & DMADESC_LENGTH_MASK) >> DMADESC_LENGTH_SHIFT;
370 /* don't include FCS */
373 if (len < copybreak) {
374 skb = napi_alloc_skb(&priv->napi, len);
375 if (unlikely(!skb)) {
376 /* forget packet, just rearm desc */
377 dev->stats.rx_dropped++;
381 dma_sync_single_for_cpu(kdev, desc->address,
382 len, DMA_FROM_DEVICE);
383 memcpy(skb->data, buf + priv->rx_buf_offset, len);
384 dma_sync_single_for_device(kdev, desc->address,
385 len, DMA_FROM_DEVICE);
387 dma_unmap_single(kdev, desc->address,
388 priv->rx_buf_size, DMA_FROM_DEVICE);
389 priv->rx_buf[desc_idx] = NULL;
391 skb = build_skb(buf, priv->rx_frag_size);
392 if (unlikely(!skb)) {
394 dev->stats.rx_dropped++;
397 skb_reserve(skb, priv->rx_buf_offset);
401 skb->protocol = eth_type_trans(skb, dev);
402 dev->stats.rx_packets++;
403 dev->stats.rx_bytes += len;
404 list_add_tail(&skb->list, &rx_list);
406 } while (processed < budget);
408 netif_receive_skb_list(&rx_list);
409 priv->rx_desc_count -= processed;
411 if (processed || !priv->rx_desc_count) {
412 bcm_enet_refill_rx(dev, true);
415 enet_dmac_writel(priv, priv->dma_chan_en_mask,
416 ENETDMAC_CHANCFG, priv->rx_chan);
424 * try to or force reclaim of transmitted buffers
426 static int bcm_enet_tx_reclaim(struct net_device *dev, int force)
428 struct bcm_enet_priv *priv;
432 priv = netdev_priv(dev);
436 while (priv->tx_desc_count < priv->tx_ring_size) {
437 struct bcm_enet_desc *desc;
440 /* We run in a bh and fight against start_xmit, which
441 * is called with bh disabled */
442 spin_lock(&priv->tx_lock);
444 desc = &priv->tx_desc_cpu[priv->tx_dirty_desc];
446 if (!force && (desc->len_stat & DMADESC_OWNER_MASK)) {
447 spin_unlock(&priv->tx_lock);
451 /* ensure other field of the descriptor were not read
452 * before we checked ownership */
455 skb = priv->tx_skb[priv->tx_dirty_desc];
456 priv->tx_skb[priv->tx_dirty_desc] = NULL;
457 dma_unmap_single(&priv->pdev->dev, desc->address, skb->len,
460 priv->tx_dirty_desc++;
461 if (priv->tx_dirty_desc == priv->tx_ring_size)
462 priv->tx_dirty_desc = 0;
463 priv->tx_desc_count++;
465 spin_unlock(&priv->tx_lock);
467 if (desc->len_stat & DMADESC_UNDER_MASK)
468 dev->stats.tx_errors++;
475 netdev_completed_queue(dev, released, bytes);
477 if (netif_queue_stopped(dev) && released)
478 netif_wake_queue(dev);
484 * poll func, called by network core
486 static int bcm_enet_poll(struct napi_struct *napi, int budget)
488 struct bcm_enet_priv *priv;
489 struct net_device *dev;
492 priv = container_of(napi, struct bcm_enet_priv, napi);
496 enet_dmac_writel(priv, priv->dma_chan_int_mask,
497 ENETDMAC_IR, priv->rx_chan);
498 enet_dmac_writel(priv, priv->dma_chan_int_mask,
499 ENETDMAC_IR, priv->tx_chan);
501 /* reclaim sent skb */
502 bcm_enet_tx_reclaim(dev, 0);
504 spin_lock(&priv->rx_lock);
505 rx_work_done = bcm_enet_receive_queue(dev, budget);
506 spin_unlock(&priv->rx_lock);
508 if (rx_work_done >= budget) {
509 /* rx queue is not yet empty/clean */
513 /* no more packet in rx/tx queue, remove device from poll
515 napi_complete_done(napi, rx_work_done);
517 /* restore rx/tx interrupt */
518 enet_dmac_writel(priv, priv->dma_chan_int_mask,
519 ENETDMAC_IRMASK, priv->rx_chan);
520 enet_dmac_writel(priv, priv->dma_chan_int_mask,
521 ENETDMAC_IRMASK, priv->tx_chan);
527 * mac interrupt handler
529 static irqreturn_t bcm_enet_isr_mac(int irq, void *dev_id)
531 struct net_device *dev;
532 struct bcm_enet_priv *priv;
536 priv = netdev_priv(dev);
538 stat = enet_readl(priv, ENET_IR_REG);
539 if (!(stat & ENET_IR_MIB))
542 /* clear & mask interrupt */
543 enet_writel(priv, ENET_IR_MIB, ENET_IR_REG);
544 enet_writel(priv, 0, ENET_IRMASK_REG);
546 /* read mib registers in workqueue */
547 schedule_work(&priv->mib_update_task);
553 * rx/tx dma interrupt handler
555 static irqreturn_t bcm_enet_isr_dma(int irq, void *dev_id)
557 struct net_device *dev;
558 struct bcm_enet_priv *priv;
561 priv = netdev_priv(dev);
563 /* mask rx/tx interrupts */
564 enet_dmac_writel(priv, 0, ENETDMAC_IRMASK, priv->rx_chan);
565 enet_dmac_writel(priv, 0, ENETDMAC_IRMASK, priv->tx_chan);
567 napi_schedule(&priv->napi);
573 * tx request callback
576 bcm_enet_start_xmit(struct sk_buff *skb, struct net_device *dev)
578 struct bcm_enet_priv *priv;
579 struct bcm_enet_desc *desc;
583 priv = netdev_priv(dev);
585 /* lock against tx reclaim */
586 spin_lock(&priv->tx_lock);
588 /* make sure the tx hw queue is not full, should not happen
589 * since we stop queue before it's the case */
590 if (unlikely(!priv->tx_desc_count)) {
591 netif_stop_queue(dev);
592 dev_err(&priv->pdev->dev, "xmit called with no tx desc "
594 ret = NETDEV_TX_BUSY;
598 /* pad small packets sent on a switch device */
599 if (priv->enet_is_sw && skb->len < 64) {
600 int needed = 64 - skb->len;
603 if (unlikely(skb_tailroom(skb) < needed)) {
604 struct sk_buff *nskb;
606 nskb = skb_copy_expand(skb, 0, needed, GFP_ATOMIC);
608 ret = NETDEV_TX_BUSY;
614 data = skb_put_zero(skb, needed);
617 /* point to the next available desc */
618 desc = &priv->tx_desc_cpu[priv->tx_curr_desc];
619 priv->tx_skb[priv->tx_curr_desc] = skb;
621 /* fill descriptor */
622 desc->address = dma_map_single(&priv->pdev->dev, skb->data, skb->len,
625 len_stat = (skb->len << DMADESC_LENGTH_SHIFT) & DMADESC_LENGTH_MASK;
626 len_stat |= (DMADESC_ESOP_MASK >> priv->dma_desc_shift) |
630 priv->tx_curr_desc++;
631 if (priv->tx_curr_desc == priv->tx_ring_size) {
632 priv->tx_curr_desc = 0;
633 len_stat |= (DMADESC_WRAP_MASK >> priv->dma_desc_shift);
635 priv->tx_desc_count--;
637 /* dma might be already polling, make sure we update desc
638 * fields in correct order */
640 desc->len_stat = len_stat;
643 netdev_sent_queue(dev, skb->len);
646 if (!netdev_xmit_more() || !priv->tx_desc_count)
647 enet_dmac_writel(priv, priv->dma_chan_en_mask,
648 ENETDMAC_CHANCFG, priv->tx_chan);
650 /* stop queue if no more desc available */
651 if (!priv->tx_desc_count)
652 netif_stop_queue(dev);
654 dev->stats.tx_bytes += skb->len;
655 dev->stats.tx_packets++;
659 spin_unlock(&priv->tx_lock);
664 * Change the interface's mac address.
666 static int bcm_enet_set_mac_address(struct net_device *dev, void *p)
668 struct bcm_enet_priv *priv;
669 struct sockaddr *addr = p;
672 priv = netdev_priv(dev);
673 memcpy(dev->dev_addr, addr->sa_data, ETH_ALEN);
675 /* use perfect match register 0 to store my mac address */
676 val = (dev->dev_addr[2] << 24) | (dev->dev_addr[3] << 16) |
677 (dev->dev_addr[4] << 8) | dev->dev_addr[5];
678 enet_writel(priv, val, ENET_PML_REG(0));
680 val = (dev->dev_addr[0] << 8 | dev->dev_addr[1]);
681 val |= ENET_PMH_DATAVALID_MASK;
682 enet_writel(priv, val, ENET_PMH_REG(0));
688 * Change rx mode (promiscuous/allmulti) and update multicast list
690 static void bcm_enet_set_multicast_list(struct net_device *dev)
692 struct bcm_enet_priv *priv;
693 struct netdev_hw_addr *ha;
697 priv = netdev_priv(dev);
699 val = enet_readl(priv, ENET_RXCFG_REG);
701 if (dev->flags & IFF_PROMISC)
702 val |= ENET_RXCFG_PROMISC_MASK;
704 val &= ~ENET_RXCFG_PROMISC_MASK;
706 /* only 3 perfect match registers left, first one is used for
708 if ((dev->flags & IFF_ALLMULTI) || netdev_mc_count(dev) > 3)
709 val |= ENET_RXCFG_ALLMCAST_MASK;
711 val &= ~ENET_RXCFG_ALLMCAST_MASK;
713 /* no need to set perfect match registers if we catch all
715 if (val & ENET_RXCFG_ALLMCAST_MASK) {
716 enet_writel(priv, val, ENET_RXCFG_REG);
721 netdev_for_each_mc_addr(ha, dev) {
727 /* update perfect match registers */
729 tmp = (dmi_addr[2] << 24) | (dmi_addr[3] << 16) |
730 (dmi_addr[4] << 8) | dmi_addr[5];
731 enet_writel(priv, tmp, ENET_PML_REG(i + 1));
733 tmp = (dmi_addr[0] << 8 | dmi_addr[1]);
734 tmp |= ENET_PMH_DATAVALID_MASK;
735 enet_writel(priv, tmp, ENET_PMH_REG(i++ + 1));
739 enet_writel(priv, 0, ENET_PML_REG(i + 1));
740 enet_writel(priv, 0, ENET_PMH_REG(i + 1));
743 enet_writel(priv, val, ENET_RXCFG_REG);
747 * set mac duplex parameters
749 static void bcm_enet_set_duplex(struct bcm_enet_priv *priv, int fullduplex)
753 val = enet_readl(priv, ENET_TXCTL_REG);
755 val |= ENET_TXCTL_FD_MASK;
757 val &= ~ENET_TXCTL_FD_MASK;
758 enet_writel(priv, val, ENET_TXCTL_REG);
762 * set mac flow control parameters
764 static void bcm_enet_set_flow(struct bcm_enet_priv *priv, int rx_en, int tx_en)
768 /* rx flow control (pause frame handling) */
769 val = enet_readl(priv, ENET_RXCFG_REG);
771 val |= ENET_RXCFG_ENFLOW_MASK;
773 val &= ~ENET_RXCFG_ENFLOW_MASK;
774 enet_writel(priv, val, ENET_RXCFG_REG);
776 if (!priv->dma_has_sram)
779 /* tx flow control (pause frame generation) */
780 val = enet_dma_readl(priv, ENETDMA_CFG_REG);
782 val |= ENETDMA_CFG_FLOWCH_MASK(priv->rx_chan);
784 val &= ~ENETDMA_CFG_FLOWCH_MASK(priv->rx_chan);
785 enet_dma_writel(priv, val, ENETDMA_CFG_REG);
789 * link changed callback (from phylib)
791 static void bcm_enet_adjust_phy_link(struct net_device *dev)
793 struct bcm_enet_priv *priv;
794 struct phy_device *phydev;
797 priv = netdev_priv(dev);
798 phydev = dev->phydev;
801 if (priv->old_link != phydev->link) {
803 priv->old_link = phydev->link;
806 /* reflect duplex change in mac configuration */
807 if (phydev->link && phydev->duplex != priv->old_duplex) {
808 bcm_enet_set_duplex(priv,
809 (phydev->duplex == DUPLEX_FULL) ? 1 : 0);
811 priv->old_duplex = phydev->duplex;
814 /* enable flow control if remote advertise it (trust phylib to
815 * check that duplex is full */
816 if (phydev->link && phydev->pause != priv->old_pause) {
817 int rx_pause_en, tx_pause_en;
820 /* pause was advertised by lpa and us */
823 } else if (!priv->pause_auto) {
824 /* pause setting overridden by user */
825 rx_pause_en = priv->pause_rx;
826 tx_pause_en = priv->pause_tx;
832 bcm_enet_set_flow(priv, rx_pause_en, tx_pause_en);
834 priv->old_pause = phydev->pause;
837 if (status_changed) {
838 pr_info("%s: link %s", dev->name, phydev->link ?
841 pr_cont(" - %d/%s - flow control %s", phydev->speed,
842 DUPLEX_FULL == phydev->duplex ? "full" : "half",
843 phydev->pause == 1 ? "rx&tx" : "off");
850 * link changed callback (if phylib is not used)
852 static void bcm_enet_adjust_link(struct net_device *dev)
854 struct bcm_enet_priv *priv;
856 priv = netdev_priv(dev);
857 bcm_enet_set_duplex(priv, priv->force_duplex_full);
858 bcm_enet_set_flow(priv, priv->pause_rx, priv->pause_tx);
859 netif_carrier_on(dev);
861 pr_info("%s: link forced UP - %d/%s - flow control %s/%s\n",
863 priv->force_speed_100 ? 100 : 10,
864 priv->force_duplex_full ? "full" : "half",
865 priv->pause_rx ? "rx" : "off",
866 priv->pause_tx ? "tx" : "off");
869 static void bcm_enet_free_rx_buf_ring(struct device *kdev, struct bcm_enet_priv *priv)
873 for (i = 0; i < priv->rx_ring_size; i++) {
874 struct bcm_enet_desc *desc;
876 if (!priv->rx_buf[i])
879 desc = &priv->rx_desc_cpu[i];
880 dma_unmap_single(kdev, desc->address, priv->rx_buf_size,
882 skb_free_frag(priv->rx_buf[i]);
888 * open callback, allocate dma rings & buffers and start rx operation
890 static int bcm_enet_open(struct net_device *dev)
892 struct bcm_enet_priv *priv;
893 struct sockaddr addr;
895 struct phy_device *phydev;
898 char phy_id[MII_BUS_ID_SIZE + 3];
902 priv = netdev_priv(dev);
903 kdev = &priv->pdev->dev;
907 snprintf(phy_id, sizeof(phy_id), PHY_ID_FMT,
908 priv->mii_bus->id, priv->phy_id);
910 phydev = phy_connect(dev, phy_id, bcm_enet_adjust_phy_link,
911 PHY_INTERFACE_MODE_MII);
913 if (IS_ERR(phydev)) {
914 dev_err(kdev, "could not attach to PHY\n");
915 return PTR_ERR(phydev);
918 /* mask with MAC supported features */
919 phy_support_sym_pause(phydev);
920 phy_set_max_speed(phydev, SPEED_100);
921 phy_set_sym_pause(phydev, priv->pause_rx, priv->pause_rx,
924 phy_attached_info(phydev);
927 priv->old_duplex = -1;
928 priv->old_pause = -1;
933 /* mask all interrupts and request them */
934 enet_writel(priv, 0, ENET_IRMASK_REG);
935 enet_dmac_writel(priv, 0, ENETDMAC_IRMASK, priv->rx_chan);
936 enet_dmac_writel(priv, 0, ENETDMAC_IRMASK, priv->tx_chan);
938 ret = request_irq(dev->irq, bcm_enet_isr_mac, 0, dev->name, dev);
940 goto out_phy_disconnect;
942 ret = request_irq(priv->irq_rx, bcm_enet_isr_dma, 0,
947 ret = request_irq(priv->irq_tx, bcm_enet_isr_dma,
952 /* initialize perfect match registers */
953 for (i = 0; i < 4; i++) {
954 enet_writel(priv, 0, ENET_PML_REG(i));
955 enet_writel(priv, 0, ENET_PMH_REG(i));
958 /* write device mac address */
959 memcpy(addr.sa_data, dev->dev_addr, ETH_ALEN);
960 bcm_enet_set_mac_address(dev, &addr);
962 /* allocate rx dma ring */
963 size = priv->rx_ring_size * sizeof(struct bcm_enet_desc);
964 p = dma_alloc_coherent(kdev, size, &priv->rx_desc_dma, GFP_KERNEL);
970 priv->rx_desc_alloc_size = size;
971 priv->rx_desc_cpu = p;
973 /* allocate tx dma ring */
974 size = priv->tx_ring_size * sizeof(struct bcm_enet_desc);
975 p = dma_alloc_coherent(kdev, size, &priv->tx_desc_dma, GFP_KERNEL);
978 goto out_free_rx_ring;
981 priv->tx_desc_alloc_size = size;
982 priv->tx_desc_cpu = p;
984 priv->tx_skb = kcalloc(priv->tx_ring_size, sizeof(struct sk_buff *),
988 goto out_free_tx_ring;
991 priv->tx_desc_count = priv->tx_ring_size;
992 priv->tx_dirty_desc = 0;
993 priv->tx_curr_desc = 0;
994 spin_lock_init(&priv->tx_lock);
996 /* init & fill rx ring with buffers */
997 priv->rx_buf = kcalloc(priv->rx_ring_size, sizeof(void *),
1001 goto out_free_tx_skb;
1004 priv->rx_desc_count = 0;
1005 priv->rx_dirty_desc = 0;
1006 priv->rx_curr_desc = 0;
1008 /* initialize flow control buffer allocation */
1009 if (priv->dma_has_sram)
1010 enet_dma_writel(priv, ENETDMA_BUFALLOC_FORCE_MASK | 0,
1011 ENETDMA_BUFALLOC_REG(priv->rx_chan));
1013 enet_dmac_writel(priv, ENETDMA_BUFALLOC_FORCE_MASK | 0,
1014 ENETDMAC_BUFALLOC, priv->rx_chan);
1016 if (bcm_enet_refill_rx(dev, false)) {
1017 dev_err(kdev, "cannot allocate rx buffer queue\n");
1022 /* write rx & tx ring addresses */
1023 if (priv->dma_has_sram) {
1024 enet_dmas_writel(priv, priv->rx_desc_dma,
1025 ENETDMAS_RSTART_REG, priv->rx_chan);
1026 enet_dmas_writel(priv, priv->tx_desc_dma,
1027 ENETDMAS_RSTART_REG, priv->tx_chan);
1029 enet_dmac_writel(priv, priv->rx_desc_dma,
1030 ENETDMAC_RSTART, priv->rx_chan);
1031 enet_dmac_writel(priv, priv->tx_desc_dma,
1032 ENETDMAC_RSTART, priv->tx_chan);
1035 /* clear remaining state ram for rx & tx channel */
1036 if (priv->dma_has_sram) {
1037 enet_dmas_writel(priv, 0, ENETDMAS_SRAM2_REG, priv->rx_chan);
1038 enet_dmas_writel(priv, 0, ENETDMAS_SRAM2_REG, priv->tx_chan);
1039 enet_dmas_writel(priv, 0, ENETDMAS_SRAM3_REG, priv->rx_chan);
1040 enet_dmas_writel(priv, 0, ENETDMAS_SRAM3_REG, priv->tx_chan);
1041 enet_dmas_writel(priv, 0, ENETDMAS_SRAM4_REG, priv->rx_chan);
1042 enet_dmas_writel(priv, 0, ENETDMAS_SRAM4_REG, priv->tx_chan);
1044 enet_dmac_writel(priv, 0, ENETDMAC_FC, priv->rx_chan);
1045 enet_dmac_writel(priv, 0, ENETDMAC_FC, priv->tx_chan);
1048 /* set max rx/tx length */
1049 enet_writel(priv, priv->hw_mtu, ENET_RXMAXLEN_REG);
1050 enet_writel(priv, priv->hw_mtu, ENET_TXMAXLEN_REG);
1052 /* set dma maximum burst len */
1053 enet_dmac_writel(priv, priv->dma_maxburst,
1054 ENETDMAC_MAXBURST, priv->rx_chan);
1055 enet_dmac_writel(priv, priv->dma_maxburst,
1056 ENETDMAC_MAXBURST, priv->tx_chan);
1058 /* set correct transmit fifo watermark */
1059 enet_writel(priv, BCMENET_TX_FIFO_TRESH, ENET_TXWMARK_REG);
1061 /* set flow control low/high threshold to 1/3 / 2/3 */
1062 if (priv->dma_has_sram) {
1063 val = priv->rx_ring_size / 3;
1064 enet_dma_writel(priv, val, ENETDMA_FLOWCL_REG(priv->rx_chan));
1065 val = (priv->rx_ring_size * 2) / 3;
1066 enet_dma_writel(priv, val, ENETDMA_FLOWCH_REG(priv->rx_chan));
1068 enet_dmac_writel(priv, 5, ENETDMAC_FC, priv->rx_chan);
1069 enet_dmac_writel(priv, priv->rx_ring_size, ENETDMAC_LEN, priv->rx_chan);
1070 enet_dmac_writel(priv, priv->tx_ring_size, ENETDMAC_LEN, priv->tx_chan);
1073 /* all set, enable mac and interrupts, start dma engine and
1074 * kick rx dma channel */
1076 val = enet_readl(priv, ENET_CTL_REG);
1077 val |= ENET_CTL_ENABLE_MASK;
1078 enet_writel(priv, val, ENET_CTL_REG);
1079 if (priv->dma_has_sram)
1080 enet_dma_writel(priv, ENETDMA_CFG_EN_MASK, ENETDMA_CFG_REG);
1081 enet_dmac_writel(priv, priv->dma_chan_en_mask,
1082 ENETDMAC_CHANCFG, priv->rx_chan);
1084 /* watch "mib counters about to overflow" interrupt */
1085 enet_writel(priv, ENET_IR_MIB, ENET_IR_REG);
1086 enet_writel(priv, ENET_IR_MIB, ENET_IRMASK_REG);
1088 /* watch "packet transferred" interrupt in rx and tx */
1089 enet_dmac_writel(priv, priv->dma_chan_int_mask,
1090 ENETDMAC_IR, priv->rx_chan);
1091 enet_dmac_writel(priv, priv->dma_chan_int_mask,
1092 ENETDMAC_IR, priv->tx_chan);
1094 /* make sure we enable napi before rx interrupt */
1095 napi_enable(&priv->napi);
1097 enet_dmac_writel(priv, priv->dma_chan_int_mask,
1098 ENETDMAC_IRMASK, priv->rx_chan);
1099 enet_dmac_writel(priv, priv->dma_chan_int_mask,
1100 ENETDMAC_IRMASK, priv->tx_chan);
1105 bcm_enet_adjust_link(dev);
1107 netif_start_queue(dev);
1111 bcm_enet_free_rx_buf_ring(kdev, priv);
1114 kfree(priv->tx_skb);
1117 dma_free_coherent(kdev, priv->tx_desc_alloc_size,
1118 priv->tx_desc_cpu, priv->tx_desc_dma);
1121 dma_free_coherent(kdev, priv->rx_desc_alloc_size,
1122 priv->rx_desc_cpu, priv->rx_desc_dma);
1125 free_irq(priv->irq_tx, dev);
1128 free_irq(priv->irq_rx, dev);
1131 free_irq(dev->irq, dev);
1135 phy_disconnect(phydev);
1143 static void bcm_enet_disable_mac(struct bcm_enet_priv *priv)
1148 val = enet_readl(priv, ENET_CTL_REG);
1149 val |= ENET_CTL_DISABLE_MASK;
1150 enet_writel(priv, val, ENET_CTL_REG);
1156 val = enet_readl(priv, ENET_CTL_REG);
1157 if (!(val & ENET_CTL_DISABLE_MASK))
1164 * disable dma in given channel
1166 static void bcm_enet_disable_dma(struct bcm_enet_priv *priv, int chan)
1170 enet_dmac_writel(priv, 0, ENETDMAC_CHANCFG, chan);
1176 val = enet_dmac_readl(priv, ENETDMAC_CHANCFG, chan);
1177 if (!(val & ENETDMAC_CHANCFG_EN_MASK))
1186 static int bcm_enet_stop(struct net_device *dev)
1188 struct bcm_enet_priv *priv;
1189 struct device *kdev;
1191 priv = netdev_priv(dev);
1192 kdev = &priv->pdev->dev;
1194 netif_stop_queue(dev);
1195 napi_disable(&priv->napi);
1197 phy_stop(dev->phydev);
1198 del_timer_sync(&priv->rx_timeout);
1200 /* mask all interrupts */
1201 enet_writel(priv, 0, ENET_IRMASK_REG);
1202 enet_dmac_writel(priv, 0, ENETDMAC_IRMASK, priv->rx_chan);
1203 enet_dmac_writel(priv, 0, ENETDMAC_IRMASK, priv->tx_chan);
1205 /* make sure no mib update is scheduled */
1206 cancel_work_sync(&priv->mib_update_task);
1208 /* disable dma & mac */
1209 bcm_enet_disable_dma(priv, priv->tx_chan);
1210 bcm_enet_disable_dma(priv, priv->rx_chan);
1211 bcm_enet_disable_mac(priv);
1213 /* force reclaim of all tx buffers */
1214 bcm_enet_tx_reclaim(dev, 1);
1216 /* free the rx buffer ring */
1217 bcm_enet_free_rx_buf_ring(kdev, priv);
1219 /* free remaining allocated memory */
1220 kfree(priv->tx_skb);
1221 dma_free_coherent(kdev, priv->rx_desc_alloc_size,
1222 priv->rx_desc_cpu, priv->rx_desc_dma);
1223 dma_free_coherent(kdev, priv->tx_desc_alloc_size,
1224 priv->tx_desc_cpu, priv->tx_desc_dma);
1225 free_irq(priv->irq_tx, dev);
1226 free_irq(priv->irq_rx, dev);
1227 free_irq(dev->irq, dev);
1231 phy_disconnect(dev->phydev);
1233 /* reset BQL after forced tx reclaim to prevent kernel panic */
1234 netdev_reset_queue(dev);
1242 struct bcm_enet_stats {
1243 char stat_string[ETH_GSTRING_LEN];
1249 #define GEN_STAT(m) sizeof(((struct bcm_enet_priv *)0)->m), \
1250 offsetof(struct bcm_enet_priv, m)
1251 #define DEV_STAT(m) sizeof(((struct net_device_stats *)0)->m), \
1252 offsetof(struct net_device_stats, m)
1254 static const struct bcm_enet_stats bcm_enet_gstrings_stats[] = {
1255 { "rx_packets", DEV_STAT(rx_packets), -1 },
1256 { "tx_packets", DEV_STAT(tx_packets), -1 },
1257 { "rx_bytes", DEV_STAT(rx_bytes), -1 },
1258 { "tx_bytes", DEV_STAT(tx_bytes), -1 },
1259 { "rx_errors", DEV_STAT(rx_errors), -1 },
1260 { "tx_errors", DEV_STAT(tx_errors), -1 },
1261 { "rx_dropped", DEV_STAT(rx_dropped), -1 },
1262 { "tx_dropped", DEV_STAT(tx_dropped), -1 },
1264 { "rx_good_octets", GEN_STAT(mib.rx_gd_octets), ETH_MIB_RX_GD_OCTETS},
1265 { "rx_good_pkts", GEN_STAT(mib.rx_gd_pkts), ETH_MIB_RX_GD_PKTS },
1266 { "rx_broadcast", GEN_STAT(mib.rx_brdcast), ETH_MIB_RX_BRDCAST },
1267 { "rx_multicast", GEN_STAT(mib.rx_mult), ETH_MIB_RX_MULT },
1268 { "rx_64_octets", GEN_STAT(mib.rx_64), ETH_MIB_RX_64 },
1269 { "rx_65_127_oct", GEN_STAT(mib.rx_65_127), ETH_MIB_RX_65_127 },
1270 { "rx_128_255_oct", GEN_STAT(mib.rx_128_255), ETH_MIB_RX_128_255 },
1271 { "rx_256_511_oct", GEN_STAT(mib.rx_256_511), ETH_MIB_RX_256_511 },
1272 { "rx_512_1023_oct", GEN_STAT(mib.rx_512_1023), ETH_MIB_RX_512_1023 },
1273 { "rx_1024_max_oct", GEN_STAT(mib.rx_1024_max), ETH_MIB_RX_1024_MAX },
1274 { "rx_jabber", GEN_STAT(mib.rx_jab), ETH_MIB_RX_JAB },
1275 { "rx_oversize", GEN_STAT(mib.rx_ovr), ETH_MIB_RX_OVR },
1276 { "rx_fragment", GEN_STAT(mib.rx_frag), ETH_MIB_RX_FRAG },
1277 { "rx_dropped", GEN_STAT(mib.rx_drop), ETH_MIB_RX_DROP },
1278 { "rx_crc_align", GEN_STAT(mib.rx_crc_align), ETH_MIB_RX_CRC_ALIGN },
1279 { "rx_undersize", GEN_STAT(mib.rx_und), ETH_MIB_RX_UND },
1280 { "rx_crc", GEN_STAT(mib.rx_crc), ETH_MIB_RX_CRC },
1281 { "rx_align", GEN_STAT(mib.rx_align), ETH_MIB_RX_ALIGN },
1282 { "rx_symbol_error", GEN_STAT(mib.rx_sym), ETH_MIB_RX_SYM },
1283 { "rx_pause", GEN_STAT(mib.rx_pause), ETH_MIB_RX_PAUSE },
1284 { "rx_control", GEN_STAT(mib.rx_cntrl), ETH_MIB_RX_CNTRL },
1286 { "tx_good_octets", GEN_STAT(mib.tx_gd_octets), ETH_MIB_TX_GD_OCTETS },
1287 { "tx_good_pkts", GEN_STAT(mib.tx_gd_pkts), ETH_MIB_TX_GD_PKTS },
1288 { "tx_broadcast", GEN_STAT(mib.tx_brdcast), ETH_MIB_TX_BRDCAST },
1289 { "tx_multicast", GEN_STAT(mib.tx_mult), ETH_MIB_TX_MULT },
1290 { "tx_64_oct", GEN_STAT(mib.tx_64), ETH_MIB_TX_64 },
1291 { "tx_65_127_oct", GEN_STAT(mib.tx_65_127), ETH_MIB_TX_65_127 },
1292 { "tx_128_255_oct", GEN_STAT(mib.tx_128_255), ETH_MIB_TX_128_255 },
1293 { "tx_256_511_oct", GEN_STAT(mib.tx_256_511), ETH_MIB_TX_256_511 },
1294 { "tx_512_1023_oct", GEN_STAT(mib.tx_512_1023), ETH_MIB_TX_512_1023},
1295 { "tx_1024_max_oct", GEN_STAT(mib.tx_1024_max), ETH_MIB_TX_1024_MAX },
1296 { "tx_jabber", GEN_STAT(mib.tx_jab), ETH_MIB_TX_JAB },
1297 { "tx_oversize", GEN_STAT(mib.tx_ovr), ETH_MIB_TX_OVR },
1298 { "tx_fragment", GEN_STAT(mib.tx_frag), ETH_MIB_TX_FRAG },
1299 { "tx_underrun", GEN_STAT(mib.tx_underrun), ETH_MIB_TX_UNDERRUN },
1300 { "tx_collisions", GEN_STAT(mib.tx_col), ETH_MIB_TX_COL },
1301 { "tx_single_collision", GEN_STAT(mib.tx_1_col), ETH_MIB_TX_1_COL },
1302 { "tx_multiple_collision", GEN_STAT(mib.tx_m_col), ETH_MIB_TX_M_COL },
1303 { "tx_excess_collision", GEN_STAT(mib.tx_ex_col), ETH_MIB_TX_EX_COL },
1304 { "tx_late_collision", GEN_STAT(mib.tx_late), ETH_MIB_TX_LATE },
1305 { "tx_deferred", GEN_STAT(mib.tx_def), ETH_MIB_TX_DEF },
1306 { "tx_carrier_sense", GEN_STAT(mib.tx_crs), ETH_MIB_TX_CRS },
1307 { "tx_pause", GEN_STAT(mib.tx_pause), ETH_MIB_TX_PAUSE },
1311 #define BCM_ENET_STATS_LEN ARRAY_SIZE(bcm_enet_gstrings_stats)
1313 static const u32 unused_mib_regs[] = {
1314 ETH_MIB_TX_ALL_OCTETS,
1315 ETH_MIB_TX_ALL_PKTS,
1316 ETH_MIB_RX_ALL_OCTETS,
1317 ETH_MIB_RX_ALL_PKTS,
1321 static void bcm_enet_get_drvinfo(struct net_device *netdev,
1322 struct ethtool_drvinfo *drvinfo)
1324 strlcpy(drvinfo->driver, bcm_enet_driver_name, sizeof(drvinfo->driver));
1325 strlcpy(drvinfo->bus_info, "bcm63xx", sizeof(drvinfo->bus_info));
1328 static int bcm_enet_get_sset_count(struct net_device *netdev,
1331 switch (string_set) {
1333 return BCM_ENET_STATS_LEN;
1339 static void bcm_enet_get_strings(struct net_device *netdev,
1340 u32 stringset, u8 *data)
1344 switch (stringset) {
1346 for (i = 0; i < BCM_ENET_STATS_LEN; i++) {
1347 memcpy(data + i * ETH_GSTRING_LEN,
1348 bcm_enet_gstrings_stats[i].stat_string,
1355 static void update_mib_counters(struct bcm_enet_priv *priv)
1359 for (i = 0; i < BCM_ENET_STATS_LEN; i++) {
1360 const struct bcm_enet_stats *s;
1364 s = &bcm_enet_gstrings_stats[i];
1365 if (s->mib_reg == -1)
1368 val = enet_readl(priv, ENET_MIB_REG(s->mib_reg));
1369 p = (char *)priv + s->stat_offset;
1371 if (s->sizeof_stat == sizeof(u64))
1377 /* also empty unused mib counters to make sure mib counter
1378 * overflow interrupt is cleared */
1379 for (i = 0; i < ARRAY_SIZE(unused_mib_regs); i++)
1380 (void)enet_readl(priv, ENET_MIB_REG(unused_mib_regs[i]));
1383 static void bcm_enet_update_mib_counters_defer(struct work_struct *t)
1385 struct bcm_enet_priv *priv;
1387 priv = container_of(t, struct bcm_enet_priv, mib_update_task);
1388 mutex_lock(&priv->mib_update_lock);
1389 update_mib_counters(priv);
1390 mutex_unlock(&priv->mib_update_lock);
1392 /* reenable mib interrupt */
1393 if (netif_running(priv->net_dev))
1394 enet_writel(priv, ENET_IR_MIB, ENET_IRMASK_REG);
1397 static void bcm_enet_get_ethtool_stats(struct net_device *netdev,
1398 struct ethtool_stats *stats,
1401 struct bcm_enet_priv *priv;
1404 priv = netdev_priv(netdev);
1406 mutex_lock(&priv->mib_update_lock);
1407 update_mib_counters(priv);
1409 for (i = 0; i < BCM_ENET_STATS_LEN; i++) {
1410 const struct bcm_enet_stats *s;
1413 s = &bcm_enet_gstrings_stats[i];
1414 if (s->mib_reg == -1)
1415 p = (char *)&netdev->stats;
1418 p += s->stat_offset;
1419 data[i] = (s->sizeof_stat == sizeof(u64)) ?
1420 *(u64 *)p : *(u32 *)p;
1422 mutex_unlock(&priv->mib_update_lock);
1425 static int bcm_enet_nway_reset(struct net_device *dev)
1427 struct bcm_enet_priv *priv;
1429 priv = netdev_priv(dev);
1431 return phy_ethtool_nway_reset(dev);
1436 static int bcm_enet_get_link_ksettings(struct net_device *dev,
1437 struct ethtool_link_ksettings *cmd)
1439 struct bcm_enet_priv *priv;
1440 u32 supported, advertising;
1442 priv = netdev_priv(dev);
1444 if (priv->has_phy) {
1448 phy_ethtool_ksettings_get(dev->phydev, cmd);
1452 cmd->base.autoneg = 0;
1453 cmd->base.speed = (priv->force_speed_100) ?
1454 SPEED_100 : SPEED_10;
1455 cmd->base.duplex = (priv->force_duplex_full) ?
1456 DUPLEX_FULL : DUPLEX_HALF;
1457 supported = ADVERTISED_10baseT_Half |
1458 ADVERTISED_10baseT_Full |
1459 ADVERTISED_100baseT_Half |
1460 ADVERTISED_100baseT_Full;
1462 ethtool_convert_legacy_u32_to_link_mode(
1463 cmd->link_modes.supported, supported);
1464 ethtool_convert_legacy_u32_to_link_mode(
1465 cmd->link_modes.advertising, advertising);
1466 cmd->base.port = PORT_MII;
1471 static int bcm_enet_set_link_ksettings(struct net_device *dev,
1472 const struct ethtool_link_ksettings *cmd)
1474 struct bcm_enet_priv *priv;
1476 priv = netdev_priv(dev);
1477 if (priv->has_phy) {
1480 return phy_ethtool_ksettings_set(dev->phydev, cmd);
1483 if (cmd->base.autoneg ||
1484 (cmd->base.speed != SPEED_100 &&
1485 cmd->base.speed != SPEED_10) ||
1486 cmd->base.port != PORT_MII)
1489 priv->force_speed_100 =
1490 (cmd->base.speed == SPEED_100) ? 1 : 0;
1491 priv->force_duplex_full =
1492 (cmd->base.duplex == DUPLEX_FULL) ? 1 : 0;
1494 if (netif_running(dev))
1495 bcm_enet_adjust_link(dev);
1500 static void bcm_enet_get_ringparam(struct net_device *dev,
1501 struct ethtool_ringparam *ering)
1503 struct bcm_enet_priv *priv;
1505 priv = netdev_priv(dev);
1507 /* rx/tx ring is actually only limited by memory */
1508 ering->rx_max_pending = 8192;
1509 ering->tx_max_pending = 8192;
1510 ering->rx_pending = priv->rx_ring_size;
1511 ering->tx_pending = priv->tx_ring_size;
1514 static int bcm_enet_set_ringparam(struct net_device *dev,
1515 struct ethtool_ringparam *ering)
1517 struct bcm_enet_priv *priv;
1520 priv = netdev_priv(dev);
1523 if (netif_running(dev)) {
1528 priv->rx_ring_size = ering->rx_pending;
1529 priv->tx_ring_size = ering->tx_pending;
1534 err = bcm_enet_open(dev);
1538 bcm_enet_set_multicast_list(dev);
1543 static void bcm_enet_get_pauseparam(struct net_device *dev,
1544 struct ethtool_pauseparam *ecmd)
1546 struct bcm_enet_priv *priv;
1548 priv = netdev_priv(dev);
1549 ecmd->autoneg = priv->pause_auto;
1550 ecmd->rx_pause = priv->pause_rx;
1551 ecmd->tx_pause = priv->pause_tx;
1554 static int bcm_enet_set_pauseparam(struct net_device *dev,
1555 struct ethtool_pauseparam *ecmd)
1557 struct bcm_enet_priv *priv;
1559 priv = netdev_priv(dev);
1561 if (priv->has_phy) {
1562 if (ecmd->autoneg && (ecmd->rx_pause != ecmd->tx_pause)) {
1563 /* asymetric pause mode not supported,
1564 * actually possible but integrated PHY has RO
1569 /* no pause autoneg on direct mii connection */
1574 priv->pause_auto = ecmd->autoneg;
1575 priv->pause_rx = ecmd->rx_pause;
1576 priv->pause_tx = ecmd->tx_pause;
1581 static const struct ethtool_ops bcm_enet_ethtool_ops = {
1582 .get_strings = bcm_enet_get_strings,
1583 .get_sset_count = bcm_enet_get_sset_count,
1584 .get_ethtool_stats = bcm_enet_get_ethtool_stats,
1585 .nway_reset = bcm_enet_nway_reset,
1586 .get_drvinfo = bcm_enet_get_drvinfo,
1587 .get_link = ethtool_op_get_link,
1588 .get_ringparam = bcm_enet_get_ringparam,
1589 .set_ringparam = bcm_enet_set_ringparam,
1590 .get_pauseparam = bcm_enet_get_pauseparam,
1591 .set_pauseparam = bcm_enet_set_pauseparam,
1592 .get_link_ksettings = bcm_enet_get_link_ksettings,
1593 .set_link_ksettings = bcm_enet_set_link_ksettings,
1596 static int bcm_enet_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
1598 struct bcm_enet_priv *priv;
1600 priv = netdev_priv(dev);
1601 if (priv->has_phy) {
1604 return phy_mii_ioctl(dev->phydev, rq, cmd);
1606 struct mii_if_info mii;
1609 mii.mdio_read = bcm_enet_mdio_read_mii;
1610 mii.mdio_write = bcm_enet_mdio_write_mii;
1612 mii.phy_id_mask = 0x3f;
1613 mii.reg_num_mask = 0x1f;
1614 return generic_mii_ioctl(&mii, if_mii(rq), cmd, NULL);
1619 * adjust mtu, can't be called while device is running
1621 static int bcm_enet_change_mtu(struct net_device *dev, int new_mtu)
1623 struct bcm_enet_priv *priv = netdev_priv(dev);
1624 int actual_mtu = new_mtu;
1626 if (netif_running(dev))
1629 /* add ethernet header + vlan tag size */
1630 actual_mtu += VLAN_ETH_HLEN;
1633 * setup maximum size before we get overflow mark in
1634 * descriptor, note that this will not prevent reception of
1635 * big frames, they will be split into multiple buffers
1638 priv->hw_mtu = actual_mtu;
1641 * align rx buffer size to dma burst len, account FCS since
1644 priv->rx_buf_size = ALIGN(actual_mtu + ETH_FCS_LEN,
1645 priv->dma_maxburst * 4);
1647 priv->rx_frag_size = SKB_DATA_ALIGN(priv->rx_buf_offset + priv->rx_buf_size) +
1648 SKB_DATA_ALIGN(sizeof(struct skb_shared_info));
1655 * preinit hardware to allow mii operation while device is down
1657 static void bcm_enet_hw_preinit(struct bcm_enet_priv *priv)
1662 /* make sure mac is disabled */
1663 bcm_enet_disable_mac(priv);
1665 /* soft reset mac */
1666 val = ENET_CTL_SRESET_MASK;
1667 enet_writel(priv, val, ENET_CTL_REG);
1672 val = enet_readl(priv, ENET_CTL_REG);
1673 if (!(val & ENET_CTL_SRESET_MASK))
1678 /* select correct mii interface */
1679 val = enet_readl(priv, ENET_CTL_REG);
1680 if (priv->use_external_mii)
1681 val |= ENET_CTL_EPHYSEL_MASK;
1683 val &= ~ENET_CTL_EPHYSEL_MASK;
1684 enet_writel(priv, val, ENET_CTL_REG);
1686 /* turn on mdc clock */
1687 enet_writel(priv, (0x1f << ENET_MIISC_MDCFREQDIV_SHIFT) |
1688 ENET_MIISC_PREAMBLEEN_MASK, ENET_MIISC_REG);
1690 /* set mib counters to self-clear when read */
1691 val = enet_readl(priv, ENET_MIBCTL_REG);
1692 val |= ENET_MIBCTL_RDCLEAR_MASK;
1693 enet_writel(priv, val, ENET_MIBCTL_REG);
1696 static const struct net_device_ops bcm_enet_ops = {
1697 .ndo_open = bcm_enet_open,
1698 .ndo_stop = bcm_enet_stop,
1699 .ndo_start_xmit = bcm_enet_start_xmit,
1700 .ndo_set_mac_address = bcm_enet_set_mac_address,
1701 .ndo_set_rx_mode = bcm_enet_set_multicast_list,
1702 .ndo_do_ioctl = bcm_enet_ioctl,
1703 .ndo_change_mtu = bcm_enet_change_mtu,
1707 * allocate netdevice, request register memory and register device.
1709 static int bcm_enet_probe(struct platform_device *pdev)
1711 struct bcm_enet_priv *priv;
1712 struct net_device *dev;
1713 struct bcm63xx_enet_platform_data *pd;
1714 struct resource *res_irq, *res_irq_rx, *res_irq_tx;
1715 struct mii_bus *bus;
1718 if (!bcm_enet_shared_base[0])
1719 return -EPROBE_DEFER;
1721 res_irq = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
1722 res_irq_rx = platform_get_resource(pdev, IORESOURCE_IRQ, 1);
1723 res_irq_tx = platform_get_resource(pdev, IORESOURCE_IRQ, 2);
1724 if (!res_irq || !res_irq_rx || !res_irq_tx)
1727 dev = alloc_etherdev(sizeof(*priv));
1730 priv = netdev_priv(dev);
1732 priv->enet_is_sw = false;
1733 priv->dma_maxburst = BCMENET_DMA_MAXBURST;
1734 priv->rx_buf_offset = NET_SKB_PAD;
1736 ret = bcm_enet_change_mtu(dev, dev->mtu);
1740 priv->base = devm_platform_ioremap_resource(pdev, 0);
1741 if (IS_ERR(priv->base)) {
1742 ret = PTR_ERR(priv->base);
1746 dev->irq = priv->irq = res_irq->start;
1747 priv->irq_rx = res_irq_rx->start;
1748 priv->irq_tx = res_irq_tx->start;
1750 priv->mac_clk = devm_clk_get(&pdev->dev, "enet");
1751 if (IS_ERR(priv->mac_clk)) {
1752 ret = PTR_ERR(priv->mac_clk);
1755 ret = clk_prepare_enable(priv->mac_clk);
1759 /* initialize default and fetch platform data */
1760 priv->rx_ring_size = BCMENET_DEF_RX_DESC;
1761 priv->tx_ring_size = BCMENET_DEF_TX_DESC;
1763 pd = dev_get_platdata(&pdev->dev);
1765 memcpy(dev->dev_addr, pd->mac_addr, ETH_ALEN);
1766 priv->has_phy = pd->has_phy;
1767 priv->phy_id = pd->phy_id;
1768 priv->has_phy_interrupt = pd->has_phy_interrupt;
1769 priv->phy_interrupt = pd->phy_interrupt;
1770 priv->use_external_mii = !pd->use_internal_phy;
1771 priv->pause_auto = pd->pause_auto;
1772 priv->pause_rx = pd->pause_rx;
1773 priv->pause_tx = pd->pause_tx;
1774 priv->force_duplex_full = pd->force_duplex_full;
1775 priv->force_speed_100 = pd->force_speed_100;
1776 priv->dma_chan_en_mask = pd->dma_chan_en_mask;
1777 priv->dma_chan_int_mask = pd->dma_chan_int_mask;
1778 priv->dma_chan_width = pd->dma_chan_width;
1779 priv->dma_has_sram = pd->dma_has_sram;
1780 priv->dma_desc_shift = pd->dma_desc_shift;
1781 priv->rx_chan = pd->rx_chan;
1782 priv->tx_chan = pd->tx_chan;
1785 if (priv->has_phy && !priv->use_external_mii) {
1786 /* using internal PHY, enable clock */
1787 priv->phy_clk = devm_clk_get(&pdev->dev, "ephy");
1788 if (IS_ERR(priv->phy_clk)) {
1789 ret = PTR_ERR(priv->phy_clk);
1790 priv->phy_clk = NULL;
1791 goto out_disable_clk_mac;
1793 ret = clk_prepare_enable(priv->phy_clk);
1795 goto out_disable_clk_mac;
1798 /* do minimal hardware init to be able to probe mii bus */
1799 bcm_enet_hw_preinit(priv);
1801 /* MII bus registration */
1802 if (priv->has_phy) {
1804 priv->mii_bus = mdiobus_alloc();
1805 if (!priv->mii_bus) {
1810 bus = priv->mii_bus;
1811 bus->name = "bcm63xx_enet MII bus";
1812 bus->parent = &pdev->dev;
1814 bus->read = bcm_enet_mdio_read_phylib;
1815 bus->write = bcm_enet_mdio_write_phylib;
1816 sprintf(bus->id, "%s-%d", pdev->name, pdev->id);
1818 /* only probe bus where we think the PHY is, because
1819 * the mdio read operation return 0 instead of 0xffff
1820 * if a slave is not present on hw */
1821 bus->phy_mask = ~(1 << priv->phy_id);
1823 if (priv->has_phy_interrupt)
1824 bus->irq[priv->phy_id] = priv->phy_interrupt;
1826 ret = mdiobus_register(bus);
1828 dev_err(&pdev->dev, "unable to register mdio bus\n");
1833 /* run platform code to initialize PHY device */
1834 if (pd && pd->mii_config &&
1835 pd->mii_config(dev, 1, bcm_enet_mdio_read_mii,
1836 bcm_enet_mdio_write_mii)) {
1837 dev_err(&pdev->dev, "unable to configure mdio bus\n");
1842 spin_lock_init(&priv->rx_lock);
1844 /* init rx timeout (used for oom) */
1845 timer_setup(&priv->rx_timeout, bcm_enet_refill_rx_timer, 0);
1847 /* init the mib update lock&work */
1848 mutex_init(&priv->mib_update_lock);
1849 INIT_WORK(&priv->mib_update_task, bcm_enet_update_mib_counters_defer);
1851 /* zero mib counters */
1852 for (i = 0; i < ENET_MIB_REG_COUNT; i++)
1853 enet_writel(priv, 0, ENET_MIB_REG(i));
1855 /* register netdevice */
1856 dev->netdev_ops = &bcm_enet_ops;
1857 netif_napi_add(dev, &priv->napi, bcm_enet_poll, 16);
1859 dev->ethtool_ops = &bcm_enet_ethtool_ops;
1860 /* MTU range: 46 - 2028 */
1861 dev->min_mtu = ETH_ZLEN - ETH_HLEN;
1862 dev->max_mtu = BCMENET_MAX_MTU - VLAN_ETH_HLEN;
1863 SET_NETDEV_DEV(dev, &pdev->dev);
1865 ret = register_netdev(dev);
1867 goto out_unregister_mdio;
1869 netif_carrier_off(dev);
1870 platform_set_drvdata(pdev, dev);
1872 priv->net_dev = dev;
1876 out_unregister_mdio:
1878 mdiobus_unregister(priv->mii_bus);
1882 mdiobus_free(priv->mii_bus);
1885 /* turn off mdc clock */
1886 enet_writel(priv, 0, ENET_MIISC_REG);
1887 clk_disable_unprepare(priv->phy_clk);
1889 out_disable_clk_mac:
1890 clk_disable_unprepare(priv->mac_clk);
1898 * exit func, stops hardware and unregisters netdevice
1900 static int bcm_enet_remove(struct platform_device *pdev)
1902 struct bcm_enet_priv *priv;
1903 struct net_device *dev;
1905 /* stop netdevice */
1906 dev = platform_get_drvdata(pdev);
1907 priv = netdev_priv(dev);
1908 unregister_netdev(dev);
1910 /* turn off mdc clock */
1911 enet_writel(priv, 0, ENET_MIISC_REG);
1913 if (priv->has_phy) {
1914 mdiobus_unregister(priv->mii_bus);
1915 mdiobus_free(priv->mii_bus);
1917 struct bcm63xx_enet_platform_data *pd;
1919 pd = dev_get_platdata(&pdev->dev);
1920 if (pd && pd->mii_config)
1921 pd->mii_config(dev, 0, bcm_enet_mdio_read_mii,
1922 bcm_enet_mdio_write_mii);
1925 /* disable hw block clocks */
1926 clk_disable_unprepare(priv->phy_clk);
1927 clk_disable_unprepare(priv->mac_clk);
1933 struct platform_driver bcm63xx_enet_driver = {
1934 .probe = bcm_enet_probe,
1935 .remove = bcm_enet_remove,
1937 .name = "bcm63xx_enet",
1938 .owner = THIS_MODULE,
1943 * switch mii access callbacks
1945 static int bcmenet_sw_mdio_read(struct bcm_enet_priv *priv,
1946 int ext, int phy_id, int location)
1951 spin_lock_bh(&priv->enetsw_mdio_lock);
1952 enetsw_writel(priv, 0, ENETSW_MDIOC_REG);
1954 reg = ENETSW_MDIOC_RD_MASK |
1955 (phy_id << ENETSW_MDIOC_PHYID_SHIFT) |
1956 (location << ENETSW_MDIOC_REG_SHIFT);
1959 reg |= ENETSW_MDIOC_EXT_MASK;
1961 enetsw_writel(priv, reg, ENETSW_MDIOC_REG);
1963 ret = enetsw_readw(priv, ENETSW_MDIOD_REG);
1964 spin_unlock_bh(&priv->enetsw_mdio_lock);
1968 static void bcmenet_sw_mdio_write(struct bcm_enet_priv *priv,
1969 int ext, int phy_id, int location,
1974 spin_lock_bh(&priv->enetsw_mdio_lock);
1975 enetsw_writel(priv, 0, ENETSW_MDIOC_REG);
1977 reg = ENETSW_MDIOC_WR_MASK |
1978 (phy_id << ENETSW_MDIOC_PHYID_SHIFT) |
1979 (location << ENETSW_MDIOC_REG_SHIFT);
1982 reg |= ENETSW_MDIOC_EXT_MASK;
1986 enetsw_writel(priv, reg, ENETSW_MDIOC_REG);
1988 spin_unlock_bh(&priv->enetsw_mdio_lock);
1991 static inline int bcm_enet_port_is_rgmii(int portid)
1993 return portid >= ENETSW_RGMII_PORT0;
1997 * enet sw PHY polling
1999 static void swphy_poll_timer(struct timer_list *t)
2001 struct bcm_enet_priv *priv = from_timer(priv, t, swphy_poll);
2004 for (i = 0; i < priv->num_ports; i++) {
2005 struct bcm63xx_enetsw_port *port;
2006 int val, j, up, advertise, lpa, speed, duplex, media;
2007 int external_phy = bcm_enet_port_is_rgmii(i);
2010 port = &priv->used_ports[i];
2014 if (port->bypass_link)
2017 /* dummy read to clear */
2018 for (j = 0; j < 2; j++)
2019 val = bcmenet_sw_mdio_read(priv, external_phy,
2020 port->phy_id, MII_BMSR);
2025 up = (val & BMSR_LSTATUS) ? 1 : 0;
2026 if (!(up ^ priv->sw_port_link[i]))
2029 priv->sw_port_link[i] = up;
2033 dev_info(&priv->pdev->dev, "link DOWN on %s\n",
2035 enetsw_writeb(priv, ENETSW_PORTOV_ENABLE_MASK,
2036 ENETSW_PORTOV_REG(i));
2037 enetsw_writeb(priv, ENETSW_PTCTRL_RXDIS_MASK |
2038 ENETSW_PTCTRL_TXDIS_MASK,
2039 ENETSW_PTCTRL_REG(i));
2043 advertise = bcmenet_sw_mdio_read(priv, external_phy,
2044 port->phy_id, MII_ADVERTISE);
2046 lpa = bcmenet_sw_mdio_read(priv, external_phy, port->phy_id,
2049 /* figure out media and duplex from advertise and LPA values */
2050 media = mii_nway_result(lpa & advertise);
2051 duplex = (media & ADVERTISE_FULL) ? 1 : 0;
2053 if (media & (ADVERTISE_100FULL | ADVERTISE_100HALF))
2058 if (val & BMSR_ESTATEN) {
2059 advertise = bcmenet_sw_mdio_read(priv, external_phy,
2060 port->phy_id, MII_CTRL1000);
2062 lpa = bcmenet_sw_mdio_read(priv, external_phy,
2063 port->phy_id, MII_STAT1000);
2065 if (advertise & (ADVERTISE_1000FULL | ADVERTISE_1000HALF)
2066 && lpa & (LPA_1000FULL | LPA_1000HALF)) {
2068 duplex = (lpa & LPA_1000FULL);
2072 dev_info(&priv->pdev->dev,
2073 "link UP on %s, %dMbps, %s-duplex\n",
2074 port->name, speed, duplex ? "full" : "half");
2076 override = ENETSW_PORTOV_ENABLE_MASK |
2077 ENETSW_PORTOV_LINKUP_MASK;
2080 override |= ENETSW_IMPOV_1000_MASK;
2081 else if (speed == 100)
2082 override |= ENETSW_IMPOV_100_MASK;
2084 override |= ENETSW_IMPOV_FDX_MASK;
2086 enetsw_writeb(priv, override, ENETSW_PORTOV_REG(i));
2087 enetsw_writeb(priv, 0, ENETSW_PTCTRL_REG(i));
2090 priv->swphy_poll.expires = jiffies + HZ;
2091 add_timer(&priv->swphy_poll);
2095 * open callback, allocate dma rings & buffers and start rx operation
2097 static int bcm_enetsw_open(struct net_device *dev)
2099 struct bcm_enet_priv *priv;
2100 struct device *kdev;
2106 priv = netdev_priv(dev);
2107 kdev = &priv->pdev->dev;
2109 /* mask all interrupts and request them */
2110 enet_dmac_writel(priv, 0, ENETDMAC_IRMASK, priv->rx_chan);
2111 enet_dmac_writel(priv, 0, ENETDMAC_IRMASK, priv->tx_chan);
2113 ret = request_irq(priv->irq_rx, bcm_enet_isr_dma,
2118 if (priv->irq_tx != -1) {
2119 ret = request_irq(priv->irq_tx, bcm_enet_isr_dma,
2122 goto out_freeirq_rx;
2125 /* allocate rx dma ring */
2126 size = priv->rx_ring_size * sizeof(struct bcm_enet_desc);
2127 p = dma_alloc_coherent(kdev, size, &priv->rx_desc_dma, GFP_KERNEL);
2129 dev_err(kdev, "cannot allocate rx ring %u\n", size);
2131 goto out_freeirq_tx;
2134 priv->rx_desc_alloc_size = size;
2135 priv->rx_desc_cpu = p;
2137 /* allocate tx dma ring */
2138 size = priv->tx_ring_size * sizeof(struct bcm_enet_desc);
2139 p = dma_alloc_coherent(kdev, size, &priv->tx_desc_dma, GFP_KERNEL);
2141 dev_err(kdev, "cannot allocate tx ring\n");
2143 goto out_free_rx_ring;
2146 priv->tx_desc_alloc_size = size;
2147 priv->tx_desc_cpu = p;
2149 priv->tx_skb = kcalloc(priv->tx_ring_size, sizeof(struct sk_buff *),
2151 if (!priv->tx_skb) {
2152 dev_err(kdev, "cannot allocate tx skb queue\n");
2154 goto out_free_tx_ring;
2157 priv->tx_desc_count = priv->tx_ring_size;
2158 priv->tx_dirty_desc = 0;
2159 priv->tx_curr_desc = 0;
2160 spin_lock_init(&priv->tx_lock);
2162 /* init & fill rx ring with buffers */
2163 priv->rx_buf = kcalloc(priv->rx_ring_size, sizeof(void *),
2165 if (!priv->rx_buf) {
2166 dev_err(kdev, "cannot allocate rx buffer queue\n");
2168 goto out_free_tx_skb;
2171 priv->rx_desc_count = 0;
2172 priv->rx_dirty_desc = 0;
2173 priv->rx_curr_desc = 0;
2175 /* disable all ports */
2176 for (i = 0; i < priv->num_ports; i++) {
2177 enetsw_writeb(priv, ENETSW_PORTOV_ENABLE_MASK,
2178 ENETSW_PORTOV_REG(i));
2179 enetsw_writeb(priv, ENETSW_PTCTRL_RXDIS_MASK |
2180 ENETSW_PTCTRL_TXDIS_MASK,
2181 ENETSW_PTCTRL_REG(i));
2183 priv->sw_port_link[i] = 0;
2187 val = enetsw_readb(priv, ENETSW_GMCR_REG);
2188 val |= ENETSW_GMCR_RST_MIB_MASK;
2189 enetsw_writeb(priv, val, ENETSW_GMCR_REG);
2191 val &= ~ENETSW_GMCR_RST_MIB_MASK;
2192 enetsw_writeb(priv, val, ENETSW_GMCR_REG);
2195 /* force CPU port state */
2196 val = enetsw_readb(priv, ENETSW_IMPOV_REG);
2197 val |= ENETSW_IMPOV_FORCE_MASK | ENETSW_IMPOV_LINKUP_MASK;
2198 enetsw_writeb(priv, val, ENETSW_IMPOV_REG);
2200 /* enable switch forward engine */
2201 val = enetsw_readb(priv, ENETSW_SWMODE_REG);
2202 val |= ENETSW_SWMODE_FWD_EN_MASK;
2203 enetsw_writeb(priv, val, ENETSW_SWMODE_REG);
2205 /* enable jumbo on all ports */
2206 enetsw_writel(priv, 0x1ff, ENETSW_JMBCTL_PORT_REG);
2207 enetsw_writew(priv, 9728, ENETSW_JMBCTL_MAXSIZE_REG);
2209 /* initialize flow control buffer allocation */
2210 enet_dma_writel(priv, ENETDMA_BUFALLOC_FORCE_MASK | 0,
2211 ENETDMA_BUFALLOC_REG(priv->rx_chan));
2213 if (bcm_enet_refill_rx(dev, false)) {
2214 dev_err(kdev, "cannot allocate rx buffer queue\n");
2219 /* write rx & tx ring addresses */
2220 enet_dmas_writel(priv, priv->rx_desc_dma,
2221 ENETDMAS_RSTART_REG, priv->rx_chan);
2222 enet_dmas_writel(priv, priv->tx_desc_dma,
2223 ENETDMAS_RSTART_REG, priv->tx_chan);
2225 /* clear remaining state ram for rx & tx channel */
2226 enet_dmas_writel(priv, 0, ENETDMAS_SRAM2_REG, priv->rx_chan);
2227 enet_dmas_writel(priv, 0, ENETDMAS_SRAM2_REG, priv->tx_chan);
2228 enet_dmas_writel(priv, 0, ENETDMAS_SRAM3_REG, priv->rx_chan);
2229 enet_dmas_writel(priv, 0, ENETDMAS_SRAM3_REG, priv->tx_chan);
2230 enet_dmas_writel(priv, 0, ENETDMAS_SRAM4_REG, priv->rx_chan);
2231 enet_dmas_writel(priv, 0, ENETDMAS_SRAM4_REG, priv->tx_chan);
2233 /* set dma maximum burst len */
2234 enet_dmac_writel(priv, priv->dma_maxburst,
2235 ENETDMAC_MAXBURST, priv->rx_chan);
2236 enet_dmac_writel(priv, priv->dma_maxburst,
2237 ENETDMAC_MAXBURST, priv->tx_chan);
2239 /* set flow control low/high threshold to 1/3 / 2/3 */
2240 val = priv->rx_ring_size / 3;
2241 enet_dma_writel(priv, val, ENETDMA_FLOWCL_REG(priv->rx_chan));
2242 val = (priv->rx_ring_size * 2) / 3;
2243 enet_dma_writel(priv, val, ENETDMA_FLOWCH_REG(priv->rx_chan));
2245 /* all set, enable mac and interrupts, start dma engine and
2246 * kick rx dma channel
2249 enet_dma_writel(priv, ENETDMA_CFG_EN_MASK, ENETDMA_CFG_REG);
2250 enet_dmac_writel(priv, ENETDMAC_CHANCFG_EN_MASK,
2251 ENETDMAC_CHANCFG, priv->rx_chan);
2253 /* watch "packet transferred" interrupt in rx and tx */
2254 enet_dmac_writel(priv, ENETDMAC_IR_PKTDONE_MASK,
2255 ENETDMAC_IR, priv->rx_chan);
2256 enet_dmac_writel(priv, ENETDMAC_IR_PKTDONE_MASK,
2257 ENETDMAC_IR, priv->tx_chan);
2259 /* make sure we enable napi before rx interrupt */
2260 napi_enable(&priv->napi);
2262 enet_dmac_writel(priv, ENETDMAC_IR_PKTDONE_MASK,
2263 ENETDMAC_IRMASK, priv->rx_chan);
2264 enet_dmac_writel(priv, ENETDMAC_IR_PKTDONE_MASK,
2265 ENETDMAC_IRMASK, priv->tx_chan);
2267 netif_carrier_on(dev);
2268 netif_start_queue(dev);
2270 /* apply override config for bypass_link ports here. */
2271 for (i = 0; i < priv->num_ports; i++) {
2272 struct bcm63xx_enetsw_port *port;
2274 port = &priv->used_ports[i];
2278 if (!port->bypass_link)
2281 override = ENETSW_PORTOV_ENABLE_MASK |
2282 ENETSW_PORTOV_LINKUP_MASK;
2284 switch (port->force_speed) {
2286 override |= ENETSW_IMPOV_1000_MASK;
2289 override |= ENETSW_IMPOV_100_MASK;
2294 pr_warn("invalid forced speed on port %s: assume 10\n",
2299 if (port->force_duplex_full)
2300 override |= ENETSW_IMPOV_FDX_MASK;
2303 enetsw_writeb(priv, override, ENETSW_PORTOV_REG(i));
2304 enetsw_writeb(priv, 0, ENETSW_PTCTRL_REG(i));
2307 /* start phy polling timer */
2308 timer_setup(&priv->swphy_poll, swphy_poll_timer, 0);
2309 mod_timer(&priv->swphy_poll, jiffies);
2313 bcm_enet_free_rx_buf_ring(kdev, priv);
2316 kfree(priv->tx_skb);
2319 dma_free_coherent(kdev, priv->tx_desc_alloc_size,
2320 priv->tx_desc_cpu, priv->tx_desc_dma);
2323 dma_free_coherent(kdev, priv->rx_desc_alloc_size,
2324 priv->rx_desc_cpu, priv->rx_desc_dma);
2327 if (priv->irq_tx != -1)
2328 free_irq(priv->irq_tx, dev);
2331 free_irq(priv->irq_rx, dev);
2338 static int bcm_enetsw_stop(struct net_device *dev)
2340 struct bcm_enet_priv *priv;
2341 struct device *kdev;
2343 priv = netdev_priv(dev);
2344 kdev = &priv->pdev->dev;
2346 del_timer_sync(&priv->swphy_poll);
2347 netif_stop_queue(dev);
2348 napi_disable(&priv->napi);
2349 del_timer_sync(&priv->rx_timeout);
2351 /* mask all interrupts */
2352 enet_dmac_writel(priv, 0, ENETDMAC_IRMASK, priv->rx_chan);
2353 enet_dmac_writel(priv, 0, ENETDMAC_IRMASK, priv->tx_chan);
2355 /* disable dma & mac */
2356 bcm_enet_disable_dma(priv, priv->tx_chan);
2357 bcm_enet_disable_dma(priv, priv->rx_chan);
2359 /* force reclaim of all tx buffers */
2360 bcm_enet_tx_reclaim(dev, 1);
2362 /* free the rx buffer ring */
2363 bcm_enet_free_rx_buf_ring(kdev, priv);
2365 /* free remaining allocated memory */
2366 kfree(priv->tx_skb);
2367 dma_free_coherent(kdev, priv->rx_desc_alloc_size,
2368 priv->rx_desc_cpu, priv->rx_desc_dma);
2369 dma_free_coherent(kdev, priv->tx_desc_alloc_size,
2370 priv->tx_desc_cpu, priv->tx_desc_dma);
2371 if (priv->irq_tx != -1)
2372 free_irq(priv->irq_tx, dev);
2373 free_irq(priv->irq_rx, dev);
2375 /* reset BQL after forced tx reclaim to prevent kernel panic */
2376 netdev_reset_queue(dev);
2381 /* try to sort out phy external status by walking the used_port field
2382 * in the bcm_enet_priv structure. in case the phy address is not
2383 * assigned to any physical port on the switch, assume it is external
2384 * (and yell at the user).
2386 static int bcm_enetsw_phy_is_external(struct bcm_enet_priv *priv, int phy_id)
2390 for (i = 0; i < priv->num_ports; ++i) {
2391 if (!priv->used_ports[i].used)
2393 if (priv->used_ports[i].phy_id == phy_id)
2394 return bcm_enet_port_is_rgmii(i);
2397 printk_once(KERN_WARNING "bcm63xx_enet: could not find a used port with phy_id %i, assuming phy is external\n",
2402 /* can't use bcmenet_sw_mdio_read directly as we need to sort out
2403 * external/internal status of the given phy_id first.
2405 static int bcm_enetsw_mii_mdio_read(struct net_device *dev, int phy_id,
2408 struct bcm_enet_priv *priv;
2410 priv = netdev_priv(dev);
2411 return bcmenet_sw_mdio_read(priv,
2412 bcm_enetsw_phy_is_external(priv, phy_id),
2416 /* can't use bcmenet_sw_mdio_write directly as we need to sort out
2417 * external/internal status of the given phy_id first.
2419 static void bcm_enetsw_mii_mdio_write(struct net_device *dev, int phy_id,
2423 struct bcm_enet_priv *priv;
2425 priv = netdev_priv(dev);
2426 bcmenet_sw_mdio_write(priv, bcm_enetsw_phy_is_external(priv, phy_id),
2427 phy_id, location, val);
2430 static int bcm_enetsw_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
2432 struct mii_if_info mii;
2435 mii.mdio_read = bcm_enetsw_mii_mdio_read;
2436 mii.mdio_write = bcm_enetsw_mii_mdio_write;
2438 mii.phy_id_mask = 0x3f;
2439 mii.reg_num_mask = 0x1f;
2440 return generic_mii_ioctl(&mii, if_mii(rq), cmd, NULL);
2444 static const struct net_device_ops bcm_enetsw_ops = {
2445 .ndo_open = bcm_enetsw_open,
2446 .ndo_stop = bcm_enetsw_stop,
2447 .ndo_start_xmit = bcm_enet_start_xmit,
2448 .ndo_change_mtu = bcm_enet_change_mtu,
2449 .ndo_do_ioctl = bcm_enetsw_ioctl,
2453 static const struct bcm_enet_stats bcm_enetsw_gstrings_stats[] = {
2454 { "rx_packets", DEV_STAT(rx_packets), -1 },
2455 { "tx_packets", DEV_STAT(tx_packets), -1 },
2456 { "rx_bytes", DEV_STAT(rx_bytes), -1 },
2457 { "tx_bytes", DEV_STAT(tx_bytes), -1 },
2458 { "rx_errors", DEV_STAT(rx_errors), -1 },
2459 { "tx_errors", DEV_STAT(tx_errors), -1 },
2460 { "rx_dropped", DEV_STAT(rx_dropped), -1 },
2461 { "tx_dropped", DEV_STAT(tx_dropped), -1 },
2463 { "tx_good_octets", GEN_STAT(mib.tx_gd_octets), ETHSW_MIB_RX_GD_OCT },
2464 { "tx_unicast", GEN_STAT(mib.tx_unicast), ETHSW_MIB_RX_BRDCAST },
2465 { "tx_broadcast", GEN_STAT(mib.tx_brdcast), ETHSW_MIB_RX_BRDCAST },
2466 { "tx_multicast", GEN_STAT(mib.tx_mult), ETHSW_MIB_RX_MULT },
2467 { "tx_64_octets", GEN_STAT(mib.tx_64), ETHSW_MIB_RX_64 },
2468 { "tx_65_127_oct", GEN_STAT(mib.tx_65_127), ETHSW_MIB_RX_65_127 },
2469 { "tx_128_255_oct", GEN_STAT(mib.tx_128_255), ETHSW_MIB_RX_128_255 },
2470 { "tx_256_511_oct", GEN_STAT(mib.tx_256_511), ETHSW_MIB_RX_256_511 },
2471 { "tx_512_1023_oct", GEN_STAT(mib.tx_512_1023), ETHSW_MIB_RX_512_1023},
2472 { "tx_1024_1522_oct", GEN_STAT(mib.tx_1024_max),
2473 ETHSW_MIB_RX_1024_1522 },
2474 { "tx_1523_2047_oct", GEN_STAT(mib.tx_1523_2047),
2475 ETHSW_MIB_RX_1523_2047 },
2476 { "tx_2048_4095_oct", GEN_STAT(mib.tx_2048_4095),
2477 ETHSW_MIB_RX_2048_4095 },
2478 { "tx_4096_8191_oct", GEN_STAT(mib.tx_4096_8191),
2479 ETHSW_MIB_RX_4096_8191 },
2480 { "tx_8192_9728_oct", GEN_STAT(mib.tx_8192_9728),
2481 ETHSW_MIB_RX_8192_9728 },
2482 { "tx_oversize", GEN_STAT(mib.tx_ovr), ETHSW_MIB_RX_OVR },
2483 { "tx_oversize_drop", GEN_STAT(mib.tx_ovr), ETHSW_MIB_RX_OVR_DISC },
2484 { "tx_dropped", GEN_STAT(mib.tx_drop), ETHSW_MIB_RX_DROP },
2485 { "tx_undersize", GEN_STAT(mib.tx_underrun), ETHSW_MIB_RX_UND },
2486 { "tx_pause", GEN_STAT(mib.tx_pause), ETHSW_MIB_RX_PAUSE },
2488 { "rx_good_octets", GEN_STAT(mib.rx_gd_octets), ETHSW_MIB_TX_ALL_OCT },
2489 { "rx_broadcast", GEN_STAT(mib.rx_brdcast), ETHSW_MIB_TX_BRDCAST },
2490 { "rx_multicast", GEN_STAT(mib.rx_mult), ETHSW_MIB_TX_MULT },
2491 { "rx_unicast", GEN_STAT(mib.rx_unicast), ETHSW_MIB_TX_MULT },
2492 { "rx_pause", GEN_STAT(mib.rx_pause), ETHSW_MIB_TX_PAUSE },
2493 { "rx_dropped", GEN_STAT(mib.rx_drop), ETHSW_MIB_TX_DROP_PKTS },
2497 #define BCM_ENETSW_STATS_LEN \
2498 (sizeof(bcm_enetsw_gstrings_stats) / sizeof(struct bcm_enet_stats))
2500 static void bcm_enetsw_get_strings(struct net_device *netdev,
2501 u32 stringset, u8 *data)
2505 switch (stringset) {
2507 for (i = 0; i < BCM_ENETSW_STATS_LEN; i++) {
2508 memcpy(data + i * ETH_GSTRING_LEN,
2509 bcm_enetsw_gstrings_stats[i].stat_string,
2516 static int bcm_enetsw_get_sset_count(struct net_device *netdev,
2519 switch (string_set) {
2521 return BCM_ENETSW_STATS_LEN;
2527 static void bcm_enetsw_get_drvinfo(struct net_device *netdev,
2528 struct ethtool_drvinfo *drvinfo)
2530 strncpy(drvinfo->driver, bcm_enet_driver_name, sizeof(drvinfo->driver));
2531 strncpy(drvinfo->bus_info, "bcm63xx", sizeof(drvinfo->bus_info));
2534 static void bcm_enetsw_get_ethtool_stats(struct net_device *netdev,
2535 struct ethtool_stats *stats,
2538 struct bcm_enet_priv *priv;
2541 priv = netdev_priv(netdev);
2543 for (i = 0; i < BCM_ENETSW_STATS_LEN; i++) {
2544 const struct bcm_enet_stats *s;
2549 s = &bcm_enetsw_gstrings_stats[i];
2555 lo = enetsw_readl(priv, ENETSW_MIB_REG(reg));
2556 p = (char *)priv + s->stat_offset;
2558 if (s->sizeof_stat == sizeof(u64)) {
2559 hi = enetsw_readl(priv, ENETSW_MIB_REG(reg + 1));
2560 *(u64 *)p = ((u64)hi << 32 | lo);
2566 for (i = 0; i < BCM_ENETSW_STATS_LEN; i++) {
2567 const struct bcm_enet_stats *s;
2570 s = &bcm_enetsw_gstrings_stats[i];
2572 if (s->mib_reg == -1)
2573 p = (char *)&netdev->stats + s->stat_offset;
2575 p = (char *)priv + s->stat_offset;
2577 data[i] = (s->sizeof_stat == sizeof(u64)) ?
2578 *(u64 *)p : *(u32 *)p;
2582 static void bcm_enetsw_get_ringparam(struct net_device *dev,
2583 struct ethtool_ringparam *ering)
2585 struct bcm_enet_priv *priv;
2587 priv = netdev_priv(dev);
2589 /* rx/tx ring is actually only limited by memory */
2590 ering->rx_max_pending = 8192;
2591 ering->tx_max_pending = 8192;
2592 ering->rx_mini_max_pending = 0;
2593 ering->rx_jumbo_max_pending = 0;
2594 ering->rx_pending = priv->rx_ring_size;
2595 ering->tx_pending = priv->tx_ring_size;
2598 static int bcm_enetsw_set_ringparam(struct net_device *dev,
2599 struct ethtool_ringparam *ering)
2601 struct bcm_enet_priv *priv;
2604 priv = netdev_priv(dev);
2607 if (netif_running(dev)) {
2608 bcm_enetsw_stop(dev);
2612 priv->rx_ring_size = ering->rx_pending;
2613 priv->tx_ring_size = ering->tx_pending;
2618 err = bcm_enetsw_open(dev);
2625 static const struct ethtool_ops bcm_enetsw_ethtool_ops = {
2626 .get_strings = bcm_enetsw_get_strings,
2627 .get_sset_count = bcm_enetsw_get_sset_count,
2628 .get_ethtool_stats = bcm_enetsw_get_ethtool_stats,
2629 .get_drvinfo = bcm_enetsw_get_drvinfo,
2630 .get_ringparam = bcm_enetsw_get_ringparam,
2631 .set_ringparam = bcm_enetsw_set_ringparam,
2634 /* allocate netdevice, request register memory and register device. */
2635 static int bcm_enetsw_probe(struct platform_device *pdev)
2637 struct bcm_enet_priv *priv;
2638 struct net_device *dev;
2639 struct bcm63xx_enetsw_platform_data *pd;
2640 struct resource *res_mem;
2641 int ret, irq_rx, irq_tx;
2643 if (!bcm_enet_shared_base[0])
2644 return -EPROBE_DEFER;
2646 res_mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2647 irq_rx = platform_get_irq(pdev, 0);
2648 irq_tx = platform_get_irq(pdev, 1);
2649 if (!res_mem || irq_rx < 0)
2653 dev = alloc_etherdev(sizeof(*priv));
2656 priv = netdev_priv(dev);
2658 /* initialize default and fetch platform data */
2659 priv->enet_is_sw = true;
2660 priv->irq_rx = irq_rx;
2661 priv->irq_tx = irq_tx;
2662 priv->rx_ring_size = BCMENET_DEF_RX_DESC;
2663 priv->tx_ring_size = BCMENET_DEF_TX_DESC;
2664 priv->dma_maxburst = BCMENETSW_DMA_MAXBURST;
2665 priv->rx_buf_offset = NET_SKB_PAD + NET_IP_ALIGN;
2667 pd = dev_get_platdata(&pdev->dev);
2669 memcpy(dev->dev_addr, pd->mac_addr, ETH_ALEN);
2670 memcpy(priv->used_ports, pd->used_ports,
2671 sizeof(pd->used_ports));
2672 priv->num_ports = pd->num_ports;
2673 priv->dma_has_sram = pd->dma_has_sram;
2674 priv->dma_chan_en_mask = pd->dma_chan_en_mask;
2675 priv->dma_chan_int_mask = pd->dma_chan_int_mask;
2676 priv->dma_chan_width = pd->dma_chan_width;
2679 ret = bcm_enet_change_mtu(dev, dev->mtu);
2683 priv->base = devm_ioremap_resource(&pdev->dev, res_mem);
2684 if (IS_ERR(priv->base)) {
2685 ret = PTR_ERR(priv->base);
2689 priv->mac_clk = devm_clk_get(&pdev->dev, "enetsw");
2690 if (IS_ERR(priv->mac_clk)) {
2691 ret = PTR_ERR(priv->mac_clk);
2694 ret = clk_prepare_enable(priv->mac_clk);
2700 spin_lock_init(&priv->rx_lock);
2702 /* init rx timeout (used for oom) */
2703 timer_setup(&priv->rx_timeout, bcm_enet_refill_rx_timer, 0);
2705 /* register netdevice */
2706 dev->netdev_ops = &bcm_enetsw_ops;
2707 netif_napi_add(dev, &priv->napi, bcm_enet_poll, 16);
2708 dev->ethtool_ops = &bcm_enetsw_ethtool_ops;
2709 SET_NETDEV_DEV(dev, &pdev->dev);
2711 spin_lock_init(&priv->enetsw_mdio_lock);
2713 ret = register_netdev(dev);
2715 goto out_disable_clk;
2717 netif_carrier_off(dev);
2718 platform_set_drvdata(pdev, dev);
2720 priv->net_dev = dev;
2725 clk_disable_unprepare(priv->mac_clk);
2732 /* exit func, stops hardware and unregisters netdevice */
2733 static int bcm_enetsw_remove(struct platform_device *pdev)
2735 struct bcm_enet_priv *priv;
2736 struct net_device *dev;
2738 /* stop netdevice */
2739 dev = platform_get_drvdata(pdev);
2740 priv = netdev_priv(dev);
2741 unregister_netdev(dev);
2743 clk_disable_unprepare(priv->mac_clk);
2749 struct platform_driver bcm63xx_enetsw_driver = {
2750 .probe = bcm_enetsw_probe,
2751 .remove = bcm_enetsw_remove,
2753 .name = "bcm63xx_enetsw",
2754 .owner = THIS_MODULE,
2758 /* reserve & remap memory space shared between all macs */
2759 static int bcm_enet_shared_probe(struct platform_device *pdev)
2764 memset(bcm_enet_shared_base, 0, sizeof(bcm_enet_shared_base));
2766 for (i = 0; i < 3; i++) {
2767 p[i] = devm_platform_ioremap_resource(pdev, i);
2769 return PTR_ERR(p[i]);
2772 memcpy(bcm_enet_shared_base, p, sizeof(bcm_enet_shared_base));
2777 static int bcm_enet_shared_remove(struct platform_device *pdev)
2782 /* this "shared" driver is needed because both macs share a single
2785 struct platform_driver bcm63xx_enet_shared_driver = {
2786 .probe = bcm_enet_shared_probe,
2787 .remove = bcm_enet_shared_remove,
2789 .name = "bcm63xx_enet_shared",
2790 .owner = THIS_MODULE,
2794 static struct platform_driver * const drivers[] = {
2795 &bcm63xx_enet_shared_driver,
2796 &bcm63xx_enet_driver,
2797 &bcm63xx_enetsw_driver,
2801 static int __init bcm_enet_init(void)
2803 return platform_register_drivers(drivers, ARRAY_SIZE(drivers));
2806 static void __exit bcm_enet_exit(void)
2808 platform_unregister_drivers(drivers, ARRAY_SIZE(drivers));
2812 module_init(bcm_enet_init);
2813 module_exit(bcm_enet_exit);
2815 MODULE_DESCRIPTION("BCM63xx internal ethernet mac driver");
2816 MODULE_AUTHOR("Maxime Bizon <mbizon@freebox.fr>");
2817 MODULE_LICENSE("GPL");