drivers/net/ethernet/broadcom/bcm63xx_enet.c

   1 /*
   2  * Driver for BCM963xx builtin Ethernet mac
   3  *
   4  * Copyright (C) 2008 Maxime Bizon <mbizon@freebox.fr>
   5  *
   6  * This program is free software; you can redistribute it and/or modify
   7  * it under the terms of the GNU General Public License as published by
   8  * the Free Software Foundation; either version 2 of the License, or
   9  * (at your option) any later version.
  10  *
  11  * This program is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  14  * GNU General Public License for more details.
  15  *
  16  * You should have received a copy of the GNU General Public License
  17  * along with this program; if not, write to the Free Software
  18  * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
  19  */
  20 #include <linux/init.h>
  21 #include <linux/interrupt.h>
  22 #include <linux/module.h>
  23 #include <linux/clk.h>
  24 #include <linux/etherdevice.h>
  25 #include <linux/slab.h>
  26 #include <linux/delay.h>
  27 #include <linux/ethtool.h>
  28 #include <linux/crc32.h>
  29 #include <linux/err.h>
  30 #include <linux/dma-mapping.h>
  31 #include <linux/platform_device.h>
  32 #include <linux/if_vlan.h>
  33
  34 #include <bcm63xx_dev_enet.h>
  35 #include "bcm63xx_enet.h"
  36
  37 static char bcm_enet_driver_name[] = "bcm63xx_enet";
  38 static char bcm_enet_driver_version[] = "1.0";
  39
  40 static int copybreak __read_mostly = 128;
  41 module_param(copybreak, int, 0);
  42 MODULE_PARM_DESC(copybreak, "Receive copy threshold");
  43
  44 /* io registers memory shared between all devices */
  45 static void __iomem *bcm_enet_shared_base[3];
  46
  47 /*
  48  * io helpers to access mac registers
  49  */
  50 static inline u32 enet_readl(struct bcm_enet_priv *priv, u32 off)
  51 {
  52         return bcm_readl(priv->base + off);
  53 }
  54
  55 static inline void enet_writel(struct bcm_enet_priv *priv,
  56                                u32 val, u32 off)
  57 {
  58         bcm_writel(val, priv->base + off);
  59 }
  60
  61 /*
  62  * io helpers to access switch registers
  63  */
  64 static inline u32 enetsw_readl(struct bcm_enet_priv *priv, u32 off)
  65 {
  66         return bcm_readl(priv->base + off);
  67 }
  68
  69 static inline void enetsw_writel(struct bcm_enet_priv *priv,
  70                                  u32 val, u32 off)
  71 {
  72         bcm_writel(val, priv->base + off);
  73 }
  74
  75 static inline u16 enetsw_readw(struct bcm_enet_priv *priv, u32 off)
  76 {
  77         return bcm_readw(priv->base + off);
  78 }
  79
  80 static inline void enetsw_writew(struct bcm_enet_priv *priv,
  81                                  u16 val, u32 off)
  82 {
  83         bcm_writew(val, priv->base + off);
  84 }
  85
  86 static inline u8 enetsw_readb(struct bcm_enet_priv *priv, u32 off)
  87 {
  88         return bcm_readb(priv->base + off);
  89 }
  90
  91 static inline void enetsw_writeb(struct bcm_enet_priv *priv,
  92                                  u8 val, u32 off)
  93 {
  94         bcm_writeb(val, priv->base + off);
  95 }
  96
  97
  98 /* io helpers to access shared registers */
  99 static inline u32 enet_dma_readl(struct bcm_enet_priv *priv, u32 off)
 100 {
 101         return bcm_readl(bcm_enet_shared_base[0] + off);
 102 }
 103
 104 static inline void enet_dma_writel(struct bcm_enet_priv *priv,
 105                                        u32 val, u32 off)
 106 {
 107         bcm_writel(val, bcm_enet_shared_base[0] + off);
 108 }
 109
 110 static inline u32 enet_dmac_readl(struct bcm_enet_priv *priv, u32 off, int chan)
 111 {
 112         return bcm_readl(bcm_enet_shared_base[1] +
 113                 bcm63xx_enetdmacreg(off) + chan * priv->dma_chan_width);
 114 }
 115
 116 static inline void enet_dmac_writel(struct bcm_enet_priv *priv,
 117                                        u32 val, u32 off, int chan)
 118 {
 119         bcm_writel(val, bcm_enet_shared_base[1] +
 120                 bcm63xx_enetdmacreg(off) + chan * priv->dma_chan_width);
 121 }
 122
 123 static inline u32 enet_dmas_readl(struct bcm_enet_priv *priv, u32 off, int chan)
 124 {
 125         return bcm_readl(bcm_enet_shared_base[2] + off + chan * priv->dma_chan_width);
 126 }
 127
 128 static inline void enet_dmas_writel(struct bcm_enet_priv *priv,
 129                                        u32 val, u32 off, int chan)
 130 {
 131         bcm_writel(val, bcm_enet_shared_base[2] + off + chan * priv->dma_chan_width);
 132 }
 133
 134 /*
 135  * write given data into mii register and wait for transfer to end
 136  * with timeout (average measured transfer time is 25us)
 137  */
 138 static int do_mdio_op(struct bcm_enet_priv *priv, unsigned int data)
 139 {
 140         int limit;
 141
 142         /* make sure mii interrupt status is cleared */
 143         enet_writel(priv, ENET_IR_MII, ENET_IR_REG);
 144
 145         enet_writel(priv, data, ENET_MIIDATA_REG);
 146         wmb();
 147
 148         /* busy wait on mii interrupt bit, with timeout */
 149         limit = 1000;
 150         do {
 151                 if (enet_readl(priv, ENET_IR_REG) & ENET_IR_MII)
 152                         break;
 153                 udelay(1);
 154         } while (limit-- > 0);
 155
 156         return (limit < 0) ? 1 : 0;
 157 }
 158
 159 /*
 160  * MII internal read callback
 161  */
 162 static int bcm_enet_mdio_read(struct bcm_enet_priv *priv, int mii_id,
 163                               int regnum)
 164 {
 165         u32 tmp, val;
 166
 167         tmp = regnum << ENET_MIIDATA_REG_SHIFT;
 168         tmp |= 0x2 << ENET_MIIDATA_TA_SHIFT;
 169         tmp |= mii_id << ENET_MIIDATA_PHYID_SHIFT;
 170         tmp |= ENET_MIIDATA_OP_READ_MASK;
 171
 172         if (do_mdio_op(priv, tmp))
 173                 return -1;
 174
 175         val = enet_readl(priv, ENET_MIIDATA_REG);
 176         val &= 0xffff;
 177         return val;
 178 }
 179
 180 /*
 181  * MII internal write callback
 182  */
 183 static int bcm_enet_mdio_write(struct bcm_enet_priv *priv, int mii_id,
 184                                int regnum, u16 value)
 185 {
 186         u32 tmp;
 187
 188         tmp = (value & 0xffff) << ENET_MIIDATA_DATA_SHIFT;
 189         tmp |= 0x2 << ENET_MIIDATA_TA_SHIFT;
 190         tmp |= regnum << ENET_MIIDATA_REG_SHIFT;
 191         tmp |= mii_id << ENET_MIIDATA_PHYID_SHIFT;
 192         tmp |= ENET_MIIDATA_OP_WRITE_MASK;
 193
 194         (void)do_mdio_op(priv, tmp);
 195         return 0;
 196 }
 197
 198 /*
 199  * MII read callback from phylib
 200  */
 201 static int bcm_enet_mdio_read_phylib(struct mii_bus *bus, int mii_id,
 202                                      int regnum)
 203 {
 204         return bcm_enet_mdio_read(bus->priv, mii_id, regnum);
 205 }
 206
 207 /*
 208  * MII write callback from phylib
 209  */
 210 static int bcm_enet_mdio_write_phylib(struct mii_bus *bus, int mii_id,
 211                                       int regnum, u16 value)
 212 {
 213         return bcm_enet_mdio_write(bus->priv, mii_id, regnum, value);
 214 }
 215
 216 /*
 217  * MII read callback from mii core
 218  */
 219 static int bcm_enet_mdio_read_mii(struct net_device *dev, int mii_id,
 220                                   int regnum)
 221 {
 222         return bcm_enet_mdio_read(netdev_priv(dev), mii_id, regnum);
 223 }
 224
 225 /*
 226  * MII write callback from mii core
 227  */
 228 static void bcm_enet_mdio_write_mii(struct net_device *dev, int mii_id,
 229                                     int regnum, int value)
 230 {
 231         bcm_enet_mdio_write(netdev_priv(dev), mii_id, regnum, value);
 232 }
 233
 234 /*
 235  * refill rx queue
 236  */
 237 static int bcm_enet_refill_rx(struct net_device *dev)
 238 {
 239         struct bcm_enet_priv *priv;
 240
 241         priv = netdev_priv(dev);
 242
 243         while (priv->rx_desc_count < priv->rx_ring_size) {
 244                 struct bcm_enet_desc *desc;
 245                 struct sk_buff *skb;
 246                 dma_addr_t p;
 247                 int desc_idx;
 248                 u32 len_stat;
 249
 250                 desc_idx = priv->rx_dirty_desc;
 251                 desc = &priv->rx_desc_cpu[desc_idx];
 252
 253                 if (!priv->rx_skb[desc_idx]) {
 254                         skb = netdev_alloc_skb(dev, priv->rx_skb_size);
 255                         if (!skb)
 256                                 break;
 257                         priv->rx_skb[desc_idx] = skb;
 258                         p = dma_map_single(&priv->pdev->dev, skb->data,
 259                                            priv->rx_skb_size,
 260                                            DMA_FROM_DEVICE);
 261                         desc->address = p;
 262                 }
 263
 264                 len_stat = priv->rx_skb_size << DMADESC_LENGTH_SHIFT;
 265                 len_stat |= DMADESC_OWNER_MASK;
 266                 if (priv->rx_dirty_desc == priv->rx_ring_size - 1) {
 267                         len_stat |= (DMADESC_WRAP_MASK >> priv->dma_desc_shift);
 268                         priv->rx_dirty_desc = 0;
 269                 } else {
 270                         priv->rx_dirty_desc++;
 271                 }
 272                 wmb();
 273                 desc->len_stat = len_stat;
 274
 275                 priv->rx_desc_count++;
 276
 277                 /* tell dma engine we allocated one buffer */
 278                 if (priv->dma_has_sram)
 279                         enet_dma_writel(priv, 1, ENETDMA_BUFALLOC_REG(priv->rx_chan));
 280                 else
 281                         enet_dmac_writel(priv, 1, ENETDMAC_BUFALLOC, priv->rx_chan);
 282         }
 283
 284         /* If rx ring is still empty, set a timer to try allocating
 285          * again at a later time. */
 286         if (priv->rx_desc_count == 0 && netif_running(dev)) {
 287                 dev_warn(&priv->pdev->dev, "unable to refill rx ring\n");
 288                 priv->rx_timeout.expires = jiffies + HZ;
 289                 add_timer(&priv->rx_timeout);
 290         }
 291
 292         return 0;
 293 }
 294
 295 /*
 296  * timer callback to defer refill rx queue in case we're OOM
 297  */
 298 static void bcm_enet_refill_rx_timer(unsigned long data)
 299 {
 300         struct net_device *dev;
 301         struct bcm_enet_priv *priv;
 302
 303         dev = (struct net_device *)data;
 304         priv = netdev_priv(dev);
 305
 306         spin_lock(&priv->rx_lock);
 307         bcm_enet_refill_rx((struct net_device *)data);
 308         spin_unlock(&priv->rx_lock);
 309 }
 310
 311 /*
 312  * extract packet from rx queue
 313  */
 314 static int bcm_enet_receive_queue(struct net_device *dev, int budget)
 315 {
 316         struct bcm_enet_priv *priv;
 317         struct device *kdev;
 318         int processed;
 319
 320         priv = netdev_priv(dev);
 321         kdev = &priv->pdev->dev;
 322         processed = 0;
 323
 324         /* don't scan ring further than number of refilled
 325          * descriptor */
 326         if (budget > priv->rx_desc_count)
 327                 budget = priv->rx_desc_count;
 328
 329         do {
 330                 struct bcm_enet_desc *desc;
 331                 struct sk_buff *skb;
 332                 int desc_idx;
 333                 u32 len_stat;
 334                 unsigned int len;
 335
 336                 desc_idx = priv->rx_curr_desc;
 337                 desc = &priv->rx_desc_cpu[desc_idx];
 338
 339                 /* make sure we actually read the descriptor status at
 340                  * each loop */
 341                 rmb();
 342
 343                 len_stat = desc->len_stat;
 344
 345                 /* break if dma ownership belongs to hw */
 346                 if (len_stat & DMADESC_OWNER_MASK)
 347                         break;
 348
 349                 processed++;
 350                 priv->rx_curr_desc++;
 351                 if (priv->rx_curr_desc == priv->rx_ring_size)
 352                         priv->rx_curr_desc = 0;
 353                 priv->rx_desc_count--;
 354
 355                 /* if the packet does not have start of packet _and_
 356                  * end of packet flag set, then just recycle it */
 357                 if ((len_stat & (DMADESC_ESOP_MASK >> priv->dma_desc_shift)) !=
 358                         (DMADESC_ESOP_MASK >> priv->dma_desc_shift)) {
 359                         dev->stats.rx_dropped++;
 360                         continue;
 361                 }
 362
 363                 /* recycle packet if it's marked as bad */
 364                 if (!priv->enet_is_sw &&
 365                     unlikely(len_stat & DMADESC_ERR_MASK)) {
 366                         dev->stats.rx_errors++;
 367
 368                         if (len_stat & DMADESC_OVSIZE_MASK)
 369                                 dev->stats.rx_length_errors++;
 370                         if (len_stat & DMADESC_CRC_MASK)
 371                                 dev->stats.rx_crc_errors++;
 372                         if (len_stat & DMADESC_UNDER_MASK)
 373                                 dev->stats.rx_frame_errors++;
 374                         if (len_stat & DMADESC_OV_MASK)
 375                                 dev->stats.rx_fifo_errors++;
 376                         continue;
 377                 }
 378
 379                 /* valid packet */
 380                 skb = priv->rx_skb[desc_idx];
 381                 len = (len_stat & DMADESC_LENGTH_MASK) >> DMADESC_LENGTH_SHIFT;
 382                 /* don't include FCS */
 383                 len -= 4;
 384
 385                 if (len < copybreak) {
 386                         struct sk_buff *nskb;
 387
 388                         nskb = napi_alloc_skb(&priv->napi, len);
 389                         if (!nskb) {
 390                                 /* forget packet, just rearm desc */
 391                                 dev->stats.rx_dropped++;
 392                                 continue;
 393                         }
 394
 395                         dma_sync_single_for_cpu(kdev, desc->address,
 396                                                 len, DMA_FROM_DEVICE);
 397                         memcpy(nskb->data, skb->data, len);
 398                         dma_sync_single_for_device(kdev, desc->address,
 399                                                    len, DMA_FROM_DEVICE);
 400                         skb = nskb;
 401                 } else {
 402                         dma_unmap_single(&priv->pdev->dev, desc->address,
 403                                          priv->rx_skb_size, DMA_FROM_DEVICE);
 404                         priv->rx_skb[desc_idx] = NULL;
 405                 }
 406
 407                 skb_put(skb, len);
 408                 skb->protocol = eth_type_trans(skb, dev);
 409                 dev->stats.rx_packets++;
 410                 dev->stats.rx_bytes += len;
 411                 netif_receive_skb(skb);
 412
 413         } while (--budget > 0);
 414
 415         if (processed || !priv->rx_desc_count) {
 416                 bcm_enet_refill_rx(dev);
 417
 418                 /* kick rx dma */
 419                 enet_dmac_writel(priv, priv->dma_chan_en_mask,
 420                                          ENETDMAC_CHANCFG, priv->rx_chan);
 421         }
 422
 423         return processed;
 424 }
 425
 426
 427 /*
 428  * try to or force reclaim of transmitted buffers
 429  */
 430 static int bcm_enet_tx_reclaim(struct net_device *dev, int force)
 431 {
 432         struct bcm_enet_priv *priv;
 433         int released;
 434
 435         priv = netdev_priv(dev);
 436         released = 0;
 437
 438         while (priv->tx_desc_count < priv->tx_ring_size) {
 439                 struct bcm_enet_desc *desc;
 440                 struct sk_buff *skb;
 441
 442                 /* We run in a bh and fight against start_xmit, which
 443                  * is called with bh disabled  */
 444                 spin_lock(&priv->tx_lock);
 445
 446                 desc = &priv->tx_desc_cpu[priv->tx_dirty_desc];
 447
 448                 if (!force && (desc->len_stat & DMADESC_OWNER_MASK)) {
 449                         spin_unlock(&priv->tx_lock);
 450                         break;
 451                 }
 452
 453                 /* ensure other field of the descriptor were not read
 454                  * before we checked ownership */
 455                 rmb();
 456
 457                 skb = priv->tx_skb[priv->tx_dirty_desc];
 458                 priv->tx_skb[priv->tx_dirty_desc] = NULL;
 459                 dma_unmap_single(&priv->pdev->dev, desc->address, skb->len,
 460                                  DMA_TO_DEVICE);
 461
 462                 priv->tx_dirty_desc++;
 463                 if (priv->tx_dirty_desc == priv->tx_ring_size)
 464                         priv->tx_dirty_desc = 0;
 465                 priv->tx_desc_count++;
 466
 467                 spin_unlock(&priv->tx_lock);
 468
 469                 if (desc->len_stat & DMADESC_UNDER_MASK)
 470                         dev->stats.tx_errors++;
 471
 472                 dev_kfree_skb(skb);
 473                 released++;
 474         }
 475
 476         if (netif_queue_stopped(dev) && released)
 477                 netif_wake_queue(dev);
 478
 479         return released;
 480 }
 481
 482 /*
 483  * poll func, called by network core
 484  */
 485 static int bcm_enet_poll(struct napi_struct *napi, int budget)
 486 {
 487         struct bcm_enet_priv *priv;
 488         struct net_device *dev;
 489         int rx_work_done;
 490
 491         priv = container_of(napi, struct bcm_enet_priv, napi);
 492         dev = priv->net_dev;
 493
 494         /* ack interrupts */
 495         enet_dmac_writel(priv, priv->dma_chan_int_mask,
 496                          ENETDMAC_IR, priv->rx_chan);
 497         enet_dmac_writel(priv, priv->dma_chan_int_mask,
 498                          ENETDMAC_IR, priv->tx_chan);
 499
 500         /* reclaim sent skb */
 501         bcm_enet_tx_reclaim(dev, 0);
 502
 503         spin_lock(&priv->rx_lock);
 504         rx_work_done = bcm_enet_receive_queue(dev, budget);
 505         spin_unlock(&priv->rx_lock);
 506
 507         if (rx_work_done >= budget) {
 508                 /* rx queue is not yet empty/clean */
 509                 return rx_work_done;
 510         }
 511
 512         /* no more packet in rx/tx queue, remove device from poll
 513          * queue */
 514         napi_complete_done(napi, rx_work_done);
 515
 516         /* restore rx/tx interrupt */
 517         enet_dmac_writel(priv, priv->dma_chan_int_mask,
 518                          ENETDMAC_IRMASK, priv->rx_chan);
 519         enet_dmac_writel(priv, priv->dma_chan_int_mask,
 520                          ENETDMAC_IRMASK, priv->tx_chan);
 521
 522         return rx_work_done;
 523 }
 524
 525 /*
 526  * mac interrupt handler
 527  */
 528 static irqreturn_t bcm_enet_isr_mac(int irq, void *dev_id)
 529 {
 530         struct net_device *dev;
 531         struct bcm_enet_priv *priv;
 532         u32 stat;
 533
 534         dev = dev_id;
 535         priv = netdev_priv(dev);
 536
 537         stat = enet_readl(priv, ENET_IR_REG);
 538         if (!(stat & ENET_IR_MIB))
 539                 return IRQ_NONE;
 540
 541         /* clear & mask interrupt */
 542         enet_writel(priv, ENET_IR_MIB, ENET_IR_REG);
 543         enet_writel(priv, 0, ENET_IRMASK_REG);
 544
 545         /* read mib registers in workqueue */
 546         schedule_work(&priv->mib_update_task);
 547
 548         return IRQ_HANDLED;
 549 }
 550
 551 /*
 552  * rx/tx dma interrupt handler
 553  */
 554 static irqreturn_t bcm_enet_isr_dma(int irq, void *dev_id)
 555 {
 556         struct net_device *dev;
 557         struct bcm_enet_priv *priv;
 558
 559         dev = dev_id;
 560         priv = netdev_priv(dev);
 561
 562         /* mask rx/tx interrupts */
 563         enet_dmac_writel(priv, 0, ENETDMAC_IRMASK, priv->rx_chan);
 564         enet_dmac_writel(priv, 0, ENETDMAC_IRMASK, priv->tx_chan);
 565
 566         napi_schedule(&priv->napi);
 567
 568         return IRQ_HANDLED;
 569 }
 570
 571 /*
 572  * tx request callback
 573  */
 574 static int bcm_enet_start_xmit(struct sk_buff *skb, struct net_device *dev)
 575 {
 576         struct bcm_enet_priv *priv;
 577         struct bcm_enet_desc *desc;
 578         u32 len_stat;
 579         int ret;
 580
 581         priv = netdev_priv(dev);
 582
 583         /* lock against tx reclaim */
 584         spin_lock(&priv->tx_lock);
 585
 586         /* make sure  the tx hw queue  is not full,  should not happen
 587          * since we stop queue before it's the case */
 588         if (unlikely(!priv->tx_desc_count)) {
 589                 netif_stop_queue(dev);
 590                 dev_err(&priv->pdev->dev, "xmit called with no tx desc "
 591                         "available?\n");
 592                 ret = NETDEV_TX_BUSY;
 593                 goto out_unlock;
 594         }
 595
 596         /* pad small packets sent on a switch device */
 597         if (priv->enet_is_sw && skb->len < 64) {
 598                 int needed = 64 - skb->len;
 599                 char *data;
 600
 601                 if (unlikely(skb_tailroom(skb) < needed)) {
 602                         struct sk_buff *nskb;
 603
 604                         nskb = skb_copy_expand(skb, 0, needed, GFP_ATOMIC);
 605                         if (!nskb) {
 606                                 ret = NETDEV_TX_BUSY;
 607                                 goto out_unlock;
 608                         }
 609                         dev_kfree_skb(skb);
 610                         skb = nskb;
 611                 }
 612                 data = skb_put_zero(skb, needed);
 613         }
 614
 615         /* point to the next available desc */
 616         desc = &priv->tx_desc_cpu[priv->tx_curr_desc];
 617         priv->tx_skb[priv->tx_curr_desc] = skb;
 618
 619         /* fill descriptor */
 620         desc->address = dma_map_single(&priv->pdev->dev, skb->data, skb->len,
 621                                        DMA_TO_DEVICE);
 622
 623         len_stat = (skb->len << DMADESC_LENGTH_SHIFT) & DMADESC_LENGTH_MASK;
 624         len_stat |= (DMADESC_ESOP_MASK >> priv->dma_desc_shift) |
 625                 DMADESC_APPEND_CRC |
 626                 DMADESC_OWNER_MASK;
 627
 628         priv->tx_curr_desc++;
 629         if (priv->tx_curr_desc == priv->tx_ring_size) {
 630                 priv->tx_curr_desc = 0;
 631                 len_stat |= (DMADESC_WRAP_MASK >> priv->dma_desc_shift);
 632         }
 633         priv->tx_desc_count--;
 634
 635         /* dma might be already polling, make sure we update desc
 636          * fields in correct order */
 637         wmb();
 638         desc->len_stat = len_stat;
 639         wmb();
 640
 641         /* kick tx dma */
 642         enet_dmac_writel(priv, priv->dma_chan_en_mask,
 643                                  ENETDMAC_CHANCFG, priv->tx_chan);
 644
 645         /* stop queue if no more desc available */
 646         if (!priv->tx_desc_count)
 647                 netif_stop_queue(dev);
 648
 649         dev->stats.tx_bytes += skb->len;
 650         dev->stats.tx_packets++;
 651         ret = NETDEV_TX_OK;
 652
 653 out_unlock:
 654         spin_unlock(&priv->tx_lock);
 655         return ret;
 656 }
 657
 658 /*
 659  * Change the interface's mac address.
 660  */
 661 static int bcm_enet_set_mac_address(struct net_device *dev, void *p)
 662 {
 663         struct bcm_enet_priv *priv;
 664         struct sockaddr *addr = p;
 665         u32 val;
 666
 667         priv = netdev_priv(dev);
 668         memcpy(dev->dev_addr, addr->sa_data, ETH_ALEN);
 669
 670         /* use perfect match register 0 to store my mac address */
 671         val = (dev->dev_addr[2] << 24) | (dev->dev_addr[3] << 16) |
 672                 (dev->dev_addr[4] << 8) | dev->dev_addr[5];
 673         enet_writel(priv, val, ENET_PML_REG(0));
 674
 675         val = (dev->dev_addr[0] << 8 | dev->dev_addr[1]);
 676         val |= ENET_PMH_DATAVALID_MASK;
 677         enet_writel(priv, val, ENET_PMH_REG(0));
 678
 679         return 0;
 680 }
 681
 682 /*
 683  * Change rx mode (promiscuous/allmulti) and update multicast list
 684  */
 685 static void bcm_enet_set_multicast_list(struct net_device *dev)
 686 {
 687         struct bcm_enet_priv *priv;
 688         struct netdev_hw_addr *ha;
 689         u32 val;
 690         int i;
 691
 692         priv = netdev_priv(dev);
 693
 694         val = enet_readl(priv, ENET_RXCFG_REG);
 695
 696         if (dev->flags & IFF_PROMISC)
 697                 val |= ENET_RXCFG_PROMISC_MASK;
 698         else
 699                 val &= ~ENET_RXCFG_PROMISC_MASK;
 700
 701         /* only 3 perfect match registers left, first one is used for
 702          * own mac address */
 703         if ((dev->flags & IFF_ALLMULTI) || netdev_mc_count(dev) > 3)
 704                 val |= ENET_RXCFG_ALLMCAST_MASK;
 705         else
 706                 val &= ~ENET_RXCFG_ALLMCAST_MASK;
 707
 708         /* no need to set perfect match registers if we catch all
 709          * multicast */
 710         if (val & ENET_RXCFG_ALLMCAST_MASK) {
 711                 enet_writel(priv, val, ENET_RXCFG_REG);
 712                 return;
 713         }
 714
 715         i = 0;
 716         netdev_for_each_mc_addr(ha, dev) {
 717                 u8 *dmi_addr;
 718                 u32 tmp;
 719
 720                 if (i == 3)
 721                         break;
 722                 /* update perfect match registers */
 723                 dmi_addr = ha->addr;
 724                 tmp = (dmi_addr[2] << 24) | (dmi_addr[3] << 16) |
 725                         (dmi_addr[4] << 8) | dmi_addr[5];
 726                 enet_writel(priv, tmp, ENET_PML_REG(i + 1));
 727
 728                 tmp = (dmi_addr[0] << 8 | dmi_addr[1]);
 729                 tmp |= ENET_PMH_DATAVALID_MASK;
 730                 enet_writel(priv, tmp, ENET_PMH_REG(i++ + 1));
 731         }
 732
 733         for (; i < 3; i++) {
 734                 enet_writel(priv, 0, ENET_PML_REG(i + 1));
 735                 enet_writel(priv, 0, ENET_PMH_REG(i + 1));
 736         }
 737
 738         enet_writel(priv, val, ENET_RXCFG_REG);
 739 }
 740
 741 /*
 742  * set mac duplex parameters
 743  */
 744 static void bcm_enet_set_duplex(struct bcm_enet_priv *priv, int fullduplex)
 745 {
 746         u32 val;
 747
 748         val = enet_readl(priv, ENET_TXCTL_REG);
 749         if (fullduplex)
 750                 val |= ENET_TXCTL_FD_MASK;
 751         else
 752                 val &= ~ENET_TXCTL_FD_MASK;
 753         enet_writel(priv, val, ENET_TXCTL_REG);
 754 }
 755
 756 /*
 757  * set mac flow control parameters
 758  */
 759 static void bcm_enet_set_flow(struct bcm_enet_priv *priv, int rx_en, int tx_en)
 760 {
 761         u32 val;
 762
 763         /* rx flow control (pause frame handling) */
 764         val = enet_readl(priv, ENET_RXCFG_REG);
 765         if (rx_en)
 766                 val |= ENET_RXCFG_ENFLOW_MASK;
 767         else
 768                 val &= ~ENET_RXCFG_ENFLOW_MASK;
 769         enet_writel(priv, val, ENET_RXCFG_REG);
 770
 771         if (!priv->dma_has_sram)
 772                 return;
 773
 774         /* tx flow control (pause frame generation) */
 775         val = enet_dma_readl(priv, ENETDMA_CFG_REG);
 776         if (tx_en)
 777                 val |= ENETDMA_CFG_FLOWCH_MASK(priv->rx_chan);
 778         else
 779                 val &= ~ENETDMA_CFG_FLOWCH_MASK(priv->rx_chan);
 780         enet_dma_writel(priv, val, ENETDMA_CFG_REG);
 781 }
 782
 783 /*
 784  * link changed callback (from phylib)
 785  */
 786 static void bcm_enet_adjust_phy_link(struct net_device *dev)
 787 {
 788         struct bcm_enet_priv *priv;
 789         struct phy_device *phydev;
 790         int status_changed;
 791
 792         priv = netdev_priv(dev);
 793         phydev = dev->phydev;
 794         status_changed = 0;
 795
 796         if (priv->old_link != phydev->link) {
 797                 status_changed = 1;
 798                 priv->old_link = phydev->link;
 799         }
 800
 801         /* reflect duplex change in mac configuration */
 802         if (phydev->link && phydev->duplex != priv->old_duplex) {
 803                 bcm_enet_set_duplex(priv,
 804                                     (phydev->duplex == DUPLEX_FULL) ? 1 : 0);
 805                 status_changed = 1;
 806                 priv->old_duplex = phydev->duplex;
 807         }
 808
 809         /* enable flow control if remote advertise it (trust phylib to
 810          * check that duplex is full */
 811         if (phydev->link && phydev->pause != priv->old_pause) {
 812                 int rx_pause_en, tx_pause_en;
 813
 814                 if (phydev->pause) {
 815                         /* pause was advertised by lpa and us */
 816                         rx_pause_en = 1;
 817                         tx_pause_en = 1;
 818                 } else if (!priv->pause_auto) {
 819                         /* pause setting overridden by user */
 820                         rx_pause_en = priv->pause_rx;
 821                         tx_pause_en = priv->pause_tx;
 822                 } else {
 823                         rx_pause_en = 0;
 824                         tx_pause_en = 0;
 825                 }
 826
 827                 bcm_enet_set_flow(priv, rx_pause_en, tx_pause_en);
 828                 status_changed = 1;
 829                 priv->old_pause = phydev->pause;
 830         }
 831
 832         if (status_changed) {
 833                 pr_info("%s: link %s", dev->name, phydev->link ?
 834                         "UP" : "DOWN");
 835                 if (phydev->link)
 836                         pr_cont(" - %d/%s - flow control %s", phydev->speed,
 837                                DUPLEX_FULL == phydev->duplex ? "full" : "half",
 838                                phydev->pause == 1 ? "rx&tx" : "off");
 839
 840                 pr_cont("\n");
 841         }
 842 }
 843
 844 /*
 845  * link changed callback (if phylib is not used)
 846  */
 847 static void bcm_enet_adjust_link(struct net_device *dev)
 848 {
 849         struct bcm_enet_priv *priv;
 850
 851         priv = netdev_priv(dev);
 852         bcm_enet_set_duplex(priv, priv->force_duplex_full);
 853         bcm_enet_set_flow(priv, priv->pause_rx, priv->pause_tx);
 854         netif_carrier_on(dev);
 855
 856         pr_info("%s: link forced UP - %d/%s - flow control %s/%s\n",
 857                 dev->name,
 858                 priv->force_speed_100 ? 100 : 10,
 859                 priv->force_duplex_full ? "full" : "half",
 860                 priv->pause_rx ? "rx" : "off",
 861                 priv->pause_tx ? "tx" : "off");
 862 }
 863
 864 /*
 865  * open callback, allocate dma rings & buffers and start rx operation
 866  */
 867 static int bcm_enet_open(struct net_device *dev)
 868 {
 869         struct bcm_enet_priv *priv;
 870         struct sockaddr addr;
 871         struct device *kdev;
 872         struct phy_device *phydev;
 873         int i, ret;
 874         unsigned int size;
 875         char phy_id[MII_BUS_ID_SIZE + 3];
 876         void *p;
 877         u32 val;
 878
 879         priv = netdev_priv(dev);
 880         kdev = &priv->pdev->dev;
 881
 882         if (priv->has_phy) {
 883                 /* connect to PHY */
 884                 snprintf(phy_id, sizeof(phy_id), PHY_ID_FMT,
 885                          priv->mii_bus->id, priv->phy_id);
 886
 887                 phydev = phy_connect(dev, phy_id, bcm_enet_adjust_phy_link,
 888                                      PHY_INTERFACE_MODE_MII);
 889
 890                 if (IS_ERR(phydev)) {
 891                         dev_err(kdev, "could not attach to PHY\n");
 892                         return PTR_ERR(phydev);
 893                 }
 894
 895                 /* mask with MAC supported features */
 896                 phydev->supported &= (SUPPORTED_10baseT_Half |
 897                                       SUPPORTED_10baseT_Full |
 898                                       SUPPORTED_100baseT_Half |
 899                                       SUPPORTED_100baseT_Full |
 900                                       SUPPORTED_Autoneg |
 901                                       SUPPORTED_Pause |
 902                                       SUPPORTED_MII);
 903                 phydev->advertising = phydev->supported;
 904
 905                 if (priv->pause_auto && priv->pause_rx && priv->pause_tx)
 906                         phydev->advertising |= SUPPORTED_Pause;
 907                 else
 908                         phydev->advertising &= ~SUPPORTED_Pause;
 909
 910                 phy_attached_info(phydev);
 911
 912                 priv->old_link = 0;
 913                 priv->old_duplex = -1;
 914                 priv->old_pause = -1;
 915         } else {
 916                 phydev = NULL;
 917         }
 918
 919         /* mask all interrupts and request them */
 920         enet_writel(priv, 0, ENET_IRMASK_REG);
 921         enet_dmac_writel(priv, 0, ENETDMAC_IRMASK, priv->rx_chan);
 922         enet_dmac_writel(priv, 0, ENETDMAC_IRMASK, priv->tx_chan);
 923
 924         ret = request_irq(dev->irq, bcm_enet_isr_mac, 0, dev->name, dev);
 925         if (ret)
 926                 goto out_phy_disconnect;
 927
 928         ret = request_irq(priv->irq_rx, bcm_enet_isr_dma, 0,
 929                           dev->name, dev);
 930         if (ret)
 931                 goto out_freeirq;
 932
 933         ret = request_irq(priv->irq_tx, bcm_enet_isr_dma,
 934                           0, dev->name, dev);
 935         if (ret)
 936                 goto out_freeirq_rx;
 937
 938         /* initialize perfect match registers */
 939         for (i = 0; i < 4; i++) {
 940                 enet_writel(priv, 0, ENET_PML_REG(i));
 941                 enet_writel(priv, 0, ENET_PMH_REG(i));
 942         }
 943
 944         /* write device mac address */
 945         memcpy(addr.sa_data, dev->dev_addr, ETH_ALEN);
 946         bcm_enet_set_mac_address(dev, &addr);
 947
 948         /* allocate rx dma ring */
 949         size = priv->rx_ring_size * sizeof(struct bcm_enet_desc);
 950         p = dma_zalloc_coherent(kdev, size, &priv->rx_desc_dma, GFP_KERNEL);
 951         if (!p) {
 952                 ret = -ENOMEM;
 953                 goto out_freeirq_tx;
 954         }
 955
 956         priv->rx_desc_alloc_size = size;
 957         priv->rx_desc_cpu = p;
 958
 959         /* allocate tx dma ring */
 960         size = priv->tx_ring_size * sizeof(struct bcm_enet_desc);
 961         p = dma_zalloc_coherent(kdev, size, &priv->tx_desc_dma, GFP_KERNEL);
 962         if (!p) {
 963                 ret = -ENOMEM;
 964                 goto out_free_rx_ring;
 965         }
 966
 967         priv->tx_desc_alloc_size = size;
 968         priv->tx_desc_cpu = p;
 969
 970         priv->tx_skb = kcalloc(priv->tx_ring_size, sizeof(struct sk_buff *),
 971                                GFP_KERNEL);
 972         if (!priv->tx_skb) {
 973                 ret = -ENOMEM;
 974                 goto out_free_tx_ring;
 975         }
 976
 977         priv->tx_desc_count = priv->tx_ring_size;
 978         priv->tx_dirty_desc = 0;
 979         priv->tx_curr_desc = 0;
 980         spin_lock_init(&priv->tx_lock);
 981
 982         /* init & fill rx ring with skbs */
 983         priv->rx_skb = kcalloc(priv->rx_ring_size, sizeof(struct sk_buff *),
 984                                GFP_KERNEL);
 985         if (!priv->rx_skb) {
 986                 ret = -ENOMEM;
 987                 goto out_free_tx_skb;
 988         }
 989
 990         priv->rx_desc_count = 0;
 991         priv->rx_dirty_desc = 0;
 992         priv->rx_curr_desc = 0;
 993
 994         /* initialize flow control buffer allocation */
 995         if (priv->dma_has_sram)
 996                 enet_dma_writel(priv, ENETDMA_BUFALLOC_FORCE_MASK | 0,
 997                                 ENETDMA_BUFALLOC_REG(priv->rx_chan));
 998         else
 999                 enet_dmac_writel(priv, ENETDMA_BUFALLOC_FORCE_MASK | 0,
1000                                 ENETDMAC_BUFALLOC, priv->rx_chan);
1001
1002         if (bcm_enet_refill_rx(dev)) {
1003                 dev_err(kdev, "cannot allocate rx skb queue\n");
1004                 ret = -ENOMEM;
1005                 goto out;
1006         }
1007
1008         /* write rx & tx ring addresses */
1009         if (priv->dma_has_sram) {
1010                 enet_dmas_writel(priv, priv->rx_desc_dma,
1011                                  ENETDMAS_RSTART_REG, priv->rx_chan);
1012                 enet_dmas_writel(priv, priv->tx_desc_dma,
1013                          ENETDMAS_RSTART_REG, priv->tx_chan);
1014         } else {
1015                 enet_dmac_writel(priv, priv->rx_desc_dma,
1016                                 ENETDMAC_RSTART, priv->rx_chan);
1017                 enet_dmac_writel(priv, priv->tx_desc_dma,
1018                                 ENETDMAC_RSTART, priv->tx_chan);
1019         }
1020
1021         /* clear remaining state ram for rx & tx channel */
1022         if (priv->dma_has_sram) {
1023                 enet_dmas_writel(priv, 0, ENETDMAS_SRAM2_REG, priv->rx_chan);
1024                 enet_dmas_writel(priv, 0, ENETDMAS_SRAM2_REG, priv->tx_chan);
1025                 enet_dmas_writel(priv, 0, ENETDMAS_SRAM3_REG, priv->rx_chan);
1026                 enet_dmas_writel(priv, 0, ENETDMAS_SRAM3_REG, priv->tx_chan);
1027                 enet_dmas_writel(priv, 0, ENETDMAS_SRAM4_REG, priv->rx_chan);
1028                 enet_dmas_writel(priv, 0, ENETDMAS_SRAM4_REG, priv->tx_chan);
1029         } else {
1030                 enet_dmac_writel(priv, 0, ENETDMAC_FC, priv->rx_chan);
1031                 enet_dmac_writel(priv, 0, ENETDMAC_FC, priv->tx_chan);
1032         }
1033
1034         /* set max rx/tx length */
1035         enet_writel(priv, priv->hw_mtu, ENET_RXMAXLEN_REG);
1036         enet_writel(priv, priv->hw_mtu, ENET_TXMAXLEN_REG);
1037
1038         /* set dma maximum burst len */
1039         enet_dmac_writel(priv, priv->dma_maxburst,
1040                          ENETDMAC_MAXBURST, priv->rx_chan);
1041         enet_dmac_writel(priv, priv->dma_maxburst,
1042                          ENETDMAC_MAXBURST, priv->tx_chan);
1043
1044         /* set correct transmit fifo watermark */
1045         enet_writel(priv, BCMENET_TX_FIFO_TRESH, ENET_TXWMARK_REG);
1046
1047         /* set flow control low/high threshold to 1/3 / 2/3 */
1048         if (priv->dma_has_sram) {
1049                 val = priv->rx_ring_size / 3;
1050                 enet_dma_writel(priv, val, ENETDMA_FLOWCL_REG(priv->rx_chan));
1051                 val = (priv->rx_ring_size * 2) / 3;
1052                 enet_dma_writel(priv, val, ENETDMA_FLOWCH_REG(priv->rx_chan));
1053         } else {
1054                 enet_dmac_writel(priv, 5, ENETDMAC_FC, priv->rx_chan);
1055                 enet_dmac_writel(priv, priv->rx_ring_size, ENETDMAC_LEN, priv->rx_chan);
1056                 enet_dmac_writel(priv, priv->tx_ring_size, ENETDMAC_LEN, priv->tx_chan);
1057         }
1058
1059         /* all set, enable mac and interrupts, start dma engine and
1060          * kick rx dma channel */
1061         wmb();
1062         val = enet_readl(priv, ENET_CTL_REG);
1063         val |= ENET_CTL_ENABLE_MASK;
1064         enet_writel(priv, val, ENET_CTL_REG);
1065         enet_dma_writel(priv, ENETDMA_CFG_EN_MASK, ENETDMA_CFG_REG);
1066         enet_dmac_writel(priv, priv->dma_chan_en_mask,
1067                          ENETDMAC_CHANCFG, priv->rx_chan);
1068
1069         /* watch "mib counters about to overflow" interrupt */
1070         enet_writel(priv, ENET_IR_MIB, ENET_IR_REG);
1071         enet_writel(priv, ENET_IR_MIB, ENET_IRMASK_REG);
1072
1073         /* watch "packet transferred" interrupt in rx and tx */
1074         enet_dmac_writel(priv, priv->dma_chan_int_mask,
1075                          ENETDMAC_IR, priv->rx_chan);
1076         enet_dmac_writel(priv, priv->dma_chan_int_mask,
1077                          ENETDMAC_IR, priv->tx_chan);
1078
1079         /* make sure we enable napi before rx interrupt  */
1080         napi_enable(&priv->napi);
1081
1082         enet_dmac_writel(priv, priv->dma_chan_int_mask,
1083                          ENETDMAC_IRMASK, priv->rx_chan);
1084         enet_dmac_writel(priv, priv->dma_chan_int_mask,
1085                          ENETDMAC_IRMASK, priv->tx_chan);
1086
1087         if (phydev)
1088                 phy_start(phydev);
1089         else
1090                 bcm_enet_adjust_link(dev);
1091
1092         netif_start_queue(dev);
1093         return 0;
1094
1095 out:
1096         for (i = 0; i < priv->rx_ring_size; i++) {
1097                 struct bcm_enet_desc *desc;
1098
1099                 if (!priv->rx_skb[i])
1100                         continue;
1101
1102                 desc = &priv->rx_desc_cpu[i];
1103                 dma_unmap_single(kdev, desc->address, priv->rx_skb_size,
1104                                  DMA_FROM_DEVICE);
1105                 kfree_skb(priv->rx_skb[i]);
1106         }
1107         kfree(priv->rx_skb);
1108
1109 out_free_tx_skb:
1110         kfree(priv->tx_skb);
1111
1112 out_free_tx_ring:
1113         dma_free_coherent(kdev, priv->tx_desc_alloc_size,
1114                           priv->tx_desc_cpu, priv->tx_desc_dma);
1115
1116 out_free_rx_ring:
1117         dma_free_coherent(kdev, priv->rx_desc_alloc_size,
1118                           priv->rx_desc_cpu, priv->rx_desc_dma);
1119
1120 out_freeirq_tx:
1121         free_irq(priv->irq_tx, dev);
1122
1123 out_freeirq_rx:
1124         free_irq(priv->irq_rx, dev);
1125
1126 out_freeirq:
1127         free_irq(dev->irq, dev);
1128
1129 out_phy_disconnect:
1130         if (phydev)
1131                 phy_disconnect(phydev);
1132
1133         return ret;
1134 }
1135
1136 /*
1137  * disable mac
1138  */
1139 static void bcm_enet_disable_mac(struct bcm_enet_priv *priv)
1140 {
1141         int limit;
1142         u32 val;
1143
1144         val = enet_readl(priv, ENET_CTL_REG);
1145         val |= ENET_CTL_DISABLE_MASK;
1146         enet_writel(priv, val, ENET_CTL_REG);
1147
1148         limit = 1000;
1149         do {
1150                 u32 val;
1151
1152                 val = enet_readl(priv, ENET_CTL_REG);
1153                 if (!(val & ENET_CTL_DISABLE_MASK))
1154                         break;
1155                 udelay(1);
1156         } while (limit--);
1157 }
1158
1159 /*
1160  * disable dma in given channel
1161  */
1162 static void bcm_enet_disable_dma(struct bcm_enet_priv *priv, int chan)
1163 {
1164         int limit;
1165
1166         enet_dmac_writel(priv, 0, ENETDMAC_CHANCFG, chan);
1167
1168         limit = 1000;
1169         do {
1170                 u32 val;
1171
1172                 val = enet_dmac_readl(priv, ENETDMAC_CHANCFG, chan);
1173                 if (!(val & ENETDMAC_CHANCFG_EN_MASK))
1174                         break;
1175                 udelay(1);
1176         } while (limit--);
1177 }
1178
1179 /*
1180  * stop callback
1181  */
1182 static int bcm_enet_stop(struct net_device *dev)
1183 {
1184         struct bcm_enet_priv *priv;
1185         struct device *kdev;
1186         int i;
1187
1188         priv = netdev_priv(dev);
1189         kdev = &priv->pdev->dev;
1190
1191         netif_stop_queue(dev);
1192         napi_disable(&priv->napi);
1193         if (priv->has_phy)
1194                 phy_stop(dev->phydev);
1195         del_timer_sync(&priv->rx_timeout);
1196
1197         /* mask all interrupts */
1198         enet_writel(priv, 0, ENET_IRMASK_REG);
1199         enet_dmac_writel(priv, 0, ENETDMAC_IRMASK, priv->rx_chan);
1200         enet_dmac_writel(priv, 0, ENETDMAC_IRMASK, priv->tx_chan);
1201
1202         /* make sure no mib update is scheduled */
1203         cancel_work_sync(&priv->mib_update_task);
1204
1205         /* disable dma & mac */
1206         bcm_enet_disable_dma(priv, priv->tx_chan);
1207         bcm_enet_disable_dma(priv, priv->rx_chan);
1208         bcm_enet_disable_mac(priv);
1209
1210         /* force reclaim of all tx buffers */
1211         bcm_enet_tx_reclaim(dev, 1);
1212
1213         /* free the rx skb ring */
1214         for (i = 0; i < priv->rx_ring_size; i++) {
1215                 struct bcm_enet_desc *desc;
1216
1217                 if (!priv->rx_skb[i])
1218                         continue;
1219
1220                 desc = &priv->rx_desc_cpu[i];
1221                 dma_unmap_single(kdev, desc->address, priv->rx_skb_size,
1222                                  DMA_FROM_DEVICE);
1223                 kfree_skb(priv->rx_skb[i]);
1224         }
1225
1226         /* free remaining allocated memory */
1227         kfree(priv->rx_skb);
1228         kfree(priv->tx_skb);
1229         dma_free_coherent(kdev, priv->rx_desc_alloc_size,
1230                           priv->rx_desc_cpu, priv->rx_desc_dma);
1231         dma_free_coherent(kdev, priv->tx_desc_alloc_size,
1232                           priv->tx_desc_cpu, priv->tx_desc_dma);
1233         free_irq(priv->irq_tx, dev);
1234         free_irq(priv->irq_rx, dev);
1235         free_irq(dev->irq, dev);
1236
1237         /* release phy */
1238         if (priv->has_phy)
1239                 phy_disconnect(dev->phydev);
1240
1241         return 0;
1242 }
1243
1244 /*
1245  * ethtool callbacks
1246  */
1247 struct bcm_enet_stats {
1248         char stat_string[ETH_GSTRING_LEN];
1249         int sizeof_stat;
1250         int stat_offset;
1251         int mib_reg;
1252 };
1253
1254 #define GEN_STAT(m) sizeof(((struct bcm_enet_priv *)0)->m),             \
1255                      offsetof(struct bcm_enet_priv, m)
1256 #define DEV_STAT(m) sizeof(((struct net_device_stats *)0)->m),          \
1257                      offsetof(struct net_device_stats, m)
1258
1259 static const struct bcm_enet_stats bcm_enet_gstrings_stats[] = {
1260         { "rx_packets", DEV_STAT(rx_packets), -1 },
1261         { "tx_packets", DEV_STAT(tx_packets), -1 },
1262         { "rx_bytes", DEV_STAT(rx_bytes), -1 },
1263         { "tx_bytes", DEV_STAT(tx_bytes), -1 },
1264         { "rx_errors", DEV_STAT(rx_errors), -1 },
1265         { "tx_errors", DEV_STAT(tx_errors), -1 },
1266         { "rx_dropped", DEV_STAT(rx_dropped), -1 },
1267         { "tx_dropped", DEV_STAT(tx_dropped), -1 },
1268
1269         { "rx_good_octets", GEN_STAT(mib.rx_gd_octets), ETH_MIB_RX_GD_OCTETS},
1270         { "rx_good_pkts", GEN_STAT(mib.rx_gd_pkts), ETH_MIB_RX_GD_PKTS },
1271         { "rx_broadcast", GEN_STAT(mib.rx_brdcast), ETH_MIB_RX_BRDCAST },
1272         { "rx_multicast", GEN_STAT(mib.rx_mult), ETH_MIB_RX_MULT },
1273         { "rx_64_octets", GEN_STAT(mib.rx_64), ETH_MIB_RX_64 },
1274         { "rx_65_127_oct", GEN_STAT(mib.rx_65_127), ETH_MIB_RX_65_127 },
1275         { "rx_128_255_oct", GEN_STAT(mib.rx_128_255), ETH_MIB_RX_128_255 },
1276         { "rx_256_511_oct", GEN_STAT(mib.rx_256_511), ETH_MIB_RX_256_511 },
1277         { "rx_512_1023_oct", GEN_STAT(mib.rx_512_1023), ETH_MIB_RX_512_1023 },
1278         { "rx_1024_max_oct", GEN_STAT(mib.rx_1024_max), ETH_MIB_RX_1024_MAX },
1279         { "rx_jabber", GEN_STAT(mib.rx_jab), ETH_MIB_RX_JAB },
1280         { "rx_oversize", GEN_STAT(mib.rx_ovr), ETH_MIB_RX_OVR },
1281         { "rx_fragment", GEN_STAT(mib.rx_frag), ETH_MIB_RX_FRAG },
1282         { "rx_dropped", GEN_STAT(mib.rx_drop), ETH_MIB_RX_DROP },
1283         { "rx_crc_align", GEN_STAT(mib.rx_crc_align), ETH_MIB_RX_CRC_ALIGN },
1284         { "rx_undersize", GEN_STAT(mib.rx_und), ETH_MIB_RX_UND },
1285         { "rx_crc", GEN_STAT(mib.rx_crc), ETH_MIB_RX_CRC },
1286         { "rx_align", GEN_STAT(mib.rx_align), ETH_MIB_RX_ALIGN },
1287         { "rx_symbol_error", GEN_STAT(mib.rx_sym), ETH_MIB_RX_SYM },
1288         { "rx_pause", GEN_STAT(mib.rx_pause), ETH_MIB_RX_PAUSE },
1289         { "rx_control", GEN_STAT(mib.rx_cntrl), ETH_MIB_RX_CNTRL },
1290
1291         { "tx_good_octets", GEN_STAT(mib.tx_gd_octets), ETH_MIB_TX_GD_OCTETS },
1292         { "tx_good_pkts", GEN_STAT(mib.tx_gd_pkts), ETH_MIB_TX_GD_PKTS },
1293         { "tx_broadcast", GEN_STAT(mib.tx_brdcast), ETH_MIB_TX_BRDCAST },
1294         { "tx_multicast", GEN_STAT(mib.tx_mult), ETH_MIB_TX_MULT },
1295         { "tx_64_oct", GEN_STAT(mib.tx_64), ETH_MIB_TX_64 },
1296         { "tx_65_127_oct", GEN_STAT(mib.tx_65_127), ETH_MIB_TX_65_127 },
1297         { "tx_128_255_oct", GEN_STAT(mib.tx_128_255), ETH_MIB_TX_128_255 },
1298         { "tx_256_511_oct", GEN_STAT(mib.tx_256_511), ETH_MIB_TX_256_511 },
1299         { "tx_512_1023_oct", GEN_STAT(mib.tx_512_1023), ETH_MIB_TX_512_1023},
1300         { "tx_1024_max_oct", GEN_STAT(mib.tx_1024_max), ETH_MIB_TX_1024_MAX },
1301         { "tx_jabber", GEN_STAT(mib.tx_jab), ETH_MIB_TX_JAB },
1302         { "tx_oversize", GEN_STAT(mib.tx_ovr), ETH_MIB_TX_OVR },
1303         { "tx_fragment", GEN_STAT(mib.tx_frag), ETH_MIB_TX_FRAG },
1304         { "tx_underrun", GEN_STAT(mib.tx_underrun), ETH_MIB_TX_UNDERRUN },
1305         { "tx_collisions", GEN_STAT(mib.tx_col), ETH_MIB_TX_COL },
1306         { "tx_single_collision", GEN_STAT(mib.tx_1_col), ETH_MIB_TX_1_COL },
1307         { "tx_multiple_collision", GEN_STAT(mib.tx_m_col), ETH_MIB_TX_M_COL },
1308         { "tx_excess_collision", GEN_STAT(mib.tx_ex_col), ETH_MIB_TX_EX_COL },
1309         { "tx_late_collision", GEN_STAT(mib.tx_late), ETH_MIB_TX_LATE },
1310         { "tx_deferred", GEN_STAT(mib.tx_def), ETH_MIB_TX_DEF },
1311         { "tx_carrier_sense", GEN_STAT(mib.tx_crs), ETH_MIB_TX_CRS },
1312         { "tx_pause", GEN_STAT(mib.tx_pause), ETH_MIB_TX_PAUSE },
1313
1314 };
1315
1316 #define BCM_ENET_STATS_LEN      ARRAY_SIZE(bcm_enet_gstrings_stats)
1317
1318 static const u32 unused_mib_regs[] = {
1319         ETH_MIB_TX_ALL_OCTETS,
1320         ETH_MIB_TX_ALL_PKTS,
1321         ETH_MIB_RX_ALL_OCTETS,
1322         ETH_MIB_RX_ALL_PKTS,
1323 };
1324
1325
1326 static void bcm_enet_get_drvinfo(struct net_device *netdev,
1327                                  struct ethtool_drvinfo *drvinfo)
1328 {
1329         strlcpy(drvinfo->driver, bcm_enet_driver_name, sizeof(drvinfo->driver));
1330         strlcpy(drvinfo->version, bcm_enet_driver_version,
1331                 sizeof(drvinfo->version));
1332         strlcpy(drvinfo->fw_version, "N/A", sizeof(drvinfo->fw_version));
1333         strlcpy(drvinfo->bus_info, "bcm63xx", sizeof(drvinfo->bus_info));
1334 }
1335
1336 static int bcm_enet_get_sset_count(struct net_device *netdev,
1337                                         int string_set)
1338 {
1339         switch (string_set) {
1340         case ETH_SS_STATS:
1341                 return BCM_ENET_STATS_LEN;
1342         default:
1343                 return -EINVAL;
1344         }
1345 }
1346
1347 static void bcm_enet_get_strings(struct net_device *netdev,
1348                                  u32 stringset, u8 *data)
1349 {
1350         int i;
1351
1352         switch (stringset) {
1353         case ETH_SS_STATS:
1354                 for (i = 0; i < BCM_ENET_STATS_LEN; i++) {
1355                         memcpy(data + i * ETH_GSTRING_LEN,
1356                                bcm_enet_gstrings_stats[i].stat_string,
1357                                ETH_GSTRING_LEN);
1358                 }
1359                 break;
1360         }
1361 }
1362
1363 static void update_mib_counters(struct bcm_enet_priv *priv)
1364 {
1365         int i;
1366
1367         for (i = 0; i < BCM_ENET_STATS_LEN; i++) {
1368                 const struct bcm_enet_stats *s;
1369                 u32 val;
1370                 char *p;
1371
1372                 s = &bcm_enet_gstrings_stats[i];
1373                 if (s->mib_reg == -1)
1374                         continue;
1375
1376                 val = enet_readl(priv, ENET_MIB_REG(s->mib_reg));
1377                 p = (char *)priv + s->stat_offset;
1378
1379                 if (s->sizeof_stat == sizeof(u64))
1380                         *(u64 *)p += val;
1381                 else
1382                         *(u32 *)p += val;
1383         }
1384
1385         /* also empty unused mib counters to make sure mib counter
1386          * overflow interrupt is cleared */
1387         for (i = 0; i < ARRAY_SIZE(unused_mib_regs); i++)
1388                 (void)enet_readl(priv, ENET_MIB_REG(unused_mib_regs[i]));
1389 }
1390
1391 static void bcm_enet_update_mib_counters_defer(struct work_struct *t)
1392 {
1393         struct bcm_enet_priv *priv;
1394
1395         priv = container_of(t, struct bcm_enet_priv, mib_update_task);
1396         mutex_lock(&priv->mib_update_lock);
1397         update_mib_counters(priv);
1398         mutex_unlock(&priv->mib_update_lock);
1399
1400         /* reenable mib interrupt */
1401         if (netif_running(priv->net_dev))
1402                 enet_writel(priv, ENET_IR_MIB, ENET_IRMASK_REG);
1403 }
1404
1405 static void bcm_enet_get_ethtool_stats(struct net_device *netdev,
1406                                        struct ethtool_stats *stats,
1407                                        u64 *data)
1408 {
1409         struct bcm_enet_priv *priv;
1410         int i;
1411
1412         priv = netdev_priv(netdev);
1413
1414         mutex_lock(&priv->mib_update_lock);
1415         update_mib_counters(priv);
1416
1417         for (i = 0; i < BCM_ENET_STATS_LEN; i++) {
1418                 const struct bcm_enet_stats *s;
1419                 char *p;
1420
1421                 s = &bcm_enet_gstrings_stats[i];
1422                 if (s->mib_reg == -1)
1423                         p = (char *)&netdev->stats;
1424                 else
1425                         p = (char *)priv;
1426                 p += s->stat_offset;
1427                 data[i] = (s->sizeof_stat == sizeof(u64)) ?
1428                         *(u64 *)p : *(u32 *)p;
1429         }
1430         mutex_unlock(&priv->mib_update_lock);
1431 }
1432
1433 static int bcm_enet_nway_reset(struct net_device *dev)
1434 {
1435         struct bcm_enet_priv *priv;
1436
1437         priv = netdev_priv(dev);
1438         if (priv->has_phy)
1439                 return phy_ethtool_nway_reset(dev);
1440
1441         return -EOPNOTSUPP;
1442 }
1443
1444 static int bcm_enet_get_link_ksettings(struct net_device *dev,
1445                                        struct ethtool_link_ksettings *cmd)
1446 {
1447         struct bcm_enet_priv *priv;
1448         u32 supported, advertising;
1449
1450         priv = netdev_priv(dev);
1451
1452         if (priv->has_phy) {
1453                 if (!dev->phydev)
1454                         return -ENODEV;
1455
1456                 phy_ethtool_ksettings_get(dev->phydev, cmd);
1457
1458                 return 0;
1459         } else {
1460                 cmd->base.autoneg = 0;
1461                 cmd->base.speed = (priv->force_speed_100) ?
1462                         SPEED_100 : SPEED_10;
1463                 cmd->base.duplex = (priv->force_duplex_full) ?
1464                         DUPLEX_FULL : DUPLEX_HALF;
1465                 supported = ADVERTISED_10baseT_Half |
1466                         ADVERTISED_10baseT_Full |
1467                         ADVERTISED_100baseT_Half |
1468                         ADVERTISED_100baseT_Full;
1469                 advertising = 0;
1470                 ethtool_convert_legacy_u32_to_link_mode(
1471                         cmd->link_modes.supported, supported);
1472                 ethtool_convert_legacy_u32_to_link_mode(
1473                         cmd->link_modes.advertising, advertising);
1474                 cmd->base.port = PORT_MII;
1475         }
1476         return 0;
1477 }
1478
1479 static int bcm_enet_set_link_ksettings(struct net_device *dev,
1480                                        const struct ethtool_link_ksettings *cmd)
1481 {
1482         struct bcm_enet_priv *priv;
1483
1484         priv = netdev_priv(dev);
1485         if (priv->has_phy) {
1486                 if (!dev->phydev)
1487                         return -ENODEV;
1488                 return phy_ethtool_ksettings_set(dev->phydev, cmd);
1489         } else {
1490
1491                 if (cmd->base.autoneg ||
1492                     (cmd->base.speed != SPEED_100 &&
1493                      cmd->base.speed != SPEED_10) ||
1494                     cmd->base.port != PORT_MII)
1495                         return -EINVAL;
1496
1497                 priv->force_speed_100 =
1498                         (cmd->base.speed == SPEED_100) ? 1 : 0;
1499                 priv->force_duplex_full =
1500                         (cmd->base.duplex == DUPLEX_FULL) ? 1 : 0;
1501
1502                 if (netif_running(dev))
1503                         bcm_enet_adjust_link(dev);
1504                 return 0;
1505         }
1506 }
1507
1508 static void bcm_enet_get_ringparam(struct net_device *dev,
1509                                    struct ethtool_ringparam *ering)
1510 {
1511         struct bcm_enet_priv *priv;
1512
1513         priv = netdev_priv(dev);
1514
1515         /* rx/tx ring is actually only limited by memory */
1516         ering->rx_max_pending = 8192;
1517         ering->tx_max_pending = 8192;
1518         ering->rx_pending = priv->rx_ring_size;
1519         ering->tx_pending = priv->tx_ring_size;
1520 }
1521
1522 static int bcm_enet_set_ringparam(struct net_device *dev,
1523                                   struct ethtool_ringparam *ering)
1524 {
1525         struct bcm_enet_priv *priv;
1526         int was_running;
1527
1528         priv = netdev_priv(dev);
1529
1530         was_running = 0;
1531         if (netif_running(dev)) {
1532                 bcm_enet_stop(dev);
1533                 was_running = 1;
1534         }
1535
1536         priv->rx_ring_size = ering->rx_pending;
1537         priv->tx_ring_size = ering->tx_pending;
1538
1539         if (was_running) {
1540                 int err;
1541
1542                 err = bcm_enet_open(dev);
1543                 if (err)
1544                         dev_close(dev);
1545                 else
1546                         bcm_enet_set_multicast_list(dev);
1547         }
1548         return 0;
1549 }
1550
1551 static void bcm_enet_get_pauseparam(struct net_device *dev,
1552                                     struct ethtool_pauseparam *ecmd)
1553 {
1554         struct bcm_enet_priv *priv;
1555
1556         priv = netdev_priv(dev);
1557         ecmd->autoneg = priv->pause_auto;
1558         ecmd->rx_pause = priv->pause_rx;
1559         ecmd->tx_pause = priv->pause_tx;
1560 }
1561
1562 static int bcm_enet_set_pauseparam(struct net_device *dev,
1563                                    struct ethtool_pauseparam *ecmd)
1564 {
1565         struct bcm_enet_priv *priv;
1566
1567         priv = netdev_priv(dev);
1568
1569         if (priv->has_phy) {
1570                 if (ecmd->autoneg && (ecmd->rx_pause != ecmd->tx_pause)) {
1571                         /* asymetric pause mode not supported,
1572                          * actually possible but integrated PHY has RO
1573                          * asym_pause bit */
1574                         return -EINVAL;
1575                 }
1576         } else {
1577                 /* no pause autoneg on direct mii connection */
1578                 if (ecmd->autoneg)
1579                         return -EINVAL;
1580         }
1581
1582         priv->pause_auto = ecmd->autoneg;
1583         priv->pause_rx = ecmd->rx_pause;
1584         priv->pause_tx = ecmd->tx_pause;
1585
1586         return 0;
1587 }
1588
1589 static const struct ethtool_ops bcm_enet_ethtool_ops = {
1590         .get_strings            = bcm_enet_get_strings,
1591         .get_sset_count         = bcm_enet_get_sset_count,
1592         .get_ethtool_stats      = bcm_enet_get_ethtool_stats,
1593         .nway_reset             = bcm_enet_nway_reset,
1594         .get_drvinfo            = bcm_enet_get_drvinfo,
1595         .get_link               = ethtool_op_get_link,
1596         .get_ringparam          = bcm_enet_get_ringparam,
1597         .set_ringparam          = bcm_enet_set_ringparam,
1598         .get_pauseparam         = bcm_enet_get_pauseparam,
1599         .set_pauseparam         = bcm_enet_set_pauseparam,
1600         .get_link_ksettings     = bcm_enet_get_link_ksettings,
1601         .set_link_ksettings     = bcm_enet_set_link_ksettings,
1602 };
1603
1604 static int bcm_enet_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
1605 {
1606         struct bcm_enet_priv *priv;
1607
1608         priv = netdev_priv(dev);
1609         if (priv->has_phy) {
1610                 if (!dev->phydev)
1611                         return -ENODEV;
1612                 return phy_mii_ioctl(dev->phydev, rq, cmd);
1613         } else {
1614                 struct mii_if_info mii;
1615
1616                 mii.dev = dev;
1617                 mii.mdio_read = bcm_enet_mdio_read_mii;
1618                 mii.mdio_write = bcm_enet_mdio_write_mii;
1619                 mii.phy_id = 0;
1620                 mii.phy_id_mask = 0x3f;
1621                 mii.reg_num_mask = 0x1f;
1622                 return generic_mii_ioctl(&mii, if_mii(rq), cmd, NULL);
1623         }
1624 }
1625
1626 /*
1627  * adjust mtu, can't be called while device is running
1628  */
1629 static int bcm_enet_change_mtu(struct net_device *dev, int new_mtu)
1630 {
1631         struct bcm_enet_priv *priv = netdev_priv(dev);
1632         int actual_mtu = new_mtu;
1633
1634         if (netif_running(dev))
1635                 return -EBUSY;
1636
1637         /* add ethernet header + vlan tag size */
1638         actual_mtu += VLAN_ETH_HLEN;
1639
1640         /*
1641          * setup maximum size before we get overflow mark in
1642          * descriptor, note that this will not prevent reception of
1643          * big frames, they will be split into multiple buffers
1644          * anyway
1645          */
1646         priv->hw_mtu = actual_mtu;
1647
1648         /*
1649          * align rx buffer size to dma burst len, account FCS since
1650          * it's appended
1651          */
1652         priv->rx_skb_size = ALIGN(actual_mtu + ETH_FCS_LEN,
1653                                   priv->dma_maxburst * 4);
1654
1655         dev->mtu = new_mtu;
1656         return 0;
1657 }
1658
1659 /*
1660  * preinit hardware to allow mii operation while device is down
1661  */
1662 static void bcm_enet_hw_preinit(struct bcm_enet_priv *priv)
1663 {
1664         u32 val;
1665         int limit;
1666
1667         /* make sure mac is disabled */
1668         bcm_enet_disable_mac(priv);
1669
1670         /* soft reset mac */
1671         val = ENET_CTL_SRESET_MASK;
1672         enet_writel(priv, val, ENET_CTL_REG);
1673         wmb();
1674
1675         limit = 1000;
1676         do {
1677                 val = enet_readl(priv, ENET_CTL_REG);
1678                 if (!(val & ENET_CTL_SRESET_MASK))
1679                         break;
1680                 udelay(1);
1681         } while (limit--);
1682
1683         /* select correct mii interface */
1684         val = enet_readl(priv, ENET_CTL_REG);
1685         if (priv->use_external_mii)
1686                 val |= ENET_CTL_EPHYSEL_MASK;
1687         else
1688                 val &= ~ENET_CTL_EPHYSEL_MASK;
1689         enet_writel(priv, val, ENET_CTL_REG);
1690
1691         /* turn on mdc clock */
1692         enet_writel(priv, (0x1f << ENET_MIISC_MDCFREQDIV_SHIFT) |
1693                     ENET_MIISC_PREAMBLEEN_MASK, ENET_MIISC_REG);
1694
1695         /* set mib counters to self-clear when read */
1696         val = enet_readl(priv, ENET_MIBCTL_REG);
1697         val |= ENET_MIBCTL_RDCLEAR_MASK;
1698         enet_writel(priv, val, ENET_MIBCTL_REG);
1699 }
1700
1701 static const struct net_device_ops bcm_enet_ops = {
1702         .ndo_open               = bcm_enet_open,
1703         .ndo_stop               = bcm_enet_stop,
1704         .ndo_start_xmit         = bcm_enet_start_xmit,
1705         .ndo_set_mac_address    = bcm_enet_set_mac_address,
1706         .ndo_set_rx_mode        = bcm_enet_set_multicast_list,
1707         .ndo_do_ioctl           = bcm_enet_ioctl,
1708         .ndo_change_mtu         = bcm_enet_change_mtu,
1709 };
1710
1711 /*
1712  * allocate netdevice, request register memory and register device.
1713  */
1714 static int bcm_enet_probe(struct platform_device *pdev)
1715 {
1716         struct bcm_enet_priv *priv;
1717         struct net_device *dev;
1718         struct bcm63xx_enet_platform_data *pd;
1719         struct resource *res_mem, *res_irq, *res_irq_rx, *res_irq_tx;
1720         struct mii_bus *bus;
1721         const char *clk_name;
1722         int i, ret;
1723
1724         /* stop if shared driver failed, assume driver->probe will be
1725          * called in the same order we register devices (correct ?) */
1726         if (!bcm_enet_shared_base[0])
1727                 return -ENODEV;
1728
1729         res_irq = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
1730         res_irq_rx = platform_get_resource(pdev, IORESOURCE_IRQ, 1);
1731         res_irq_tx = platform_get_resource(pdev, IORESOURCE_IRQ, 2);
1732         if (!res_irq || !res_irq_rx || !res_irq_tx)
1733                 return -ENODEV;
1734
1735         ret = 0;
1736         dev = alloc_etherdev(sizeof(*priv));
1737         if (!dev)
1738                 return -ENOMEM;
1739         priv = netdev_priv(dev);
1740
1741         priv->enet_is_sw = false;
1742         priv->dma_maxburst = BCMENET_DMA_MAXBURST;
1743
1744         ret = bcm_enet_change_mtu(dev, dev->mtu);
1745         if (ret)
1746                 goto out;
1747
1748         res_mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1749         priv->base = devm_ioremap_resource(&pdev->dev, res_mem);
1750         if (IS_ERR(priv->base)) {
1751                 ret = PTR_ERR(priv->base);
1752                 goto out;
1753         }
1754
1755         dev->irq = priv->irq = res_irq->start;
1756         priv->irq_rx = res_irq_rx->start;
1757         priv->irq_tx = res_irq_tx->start;
1758         priv->mac_id = pdev->id;
1759
1760         /* get rx & tx dma channel id for this mac */
1761         if (priv->mac_id == 0) {
1762                 priv->rx_chan = 0;
1763                 priv->tx_chan = 1;
1764                 clk_name = "enet0";
1765         } else {
1766                 priv->rx_chan = 2;
1767                 priv->tx_chan = 3;
1768                 clk_name = "enet1";
1769         }
1770
1771         priv->mac_clk = clk_get(&pdev->dev, clk_name);
1772         if (IS_ERR(priv->mac_clk)) {
1773                 ret = PTR_ERR(priv->mac_clk);
1774                 goto out;
1775         }
1776         clk_prepare_enable(priv->mac_clk);
1777
1778         /* initialize default and fetch platform data */
1779         priv->rx_ring_size = BCMENET_DEF_RX_DESC;
1780         priv->tx_ring_size = BCMENET_DEF_TX_DESC;
1781
1782         pd = dev_get_platdata(&pdev->dev);
1783         if (pd) {
1784                 memcpy(dev->dev_addr, pd->mac_addr, ETH_ALEN);
1785                 priv->has_phy = pd->has_phy;
1786                 priv->phy_id = pd->phy_id;
1787                 priv->has_phy_interrupt = pd->has_phy_interrupt;
1788                 priv->phy_interrupt = pd->phy_interrupt;
1789                 priv->use_external_mii = !pd->use_internal_phy;
1790                 priv->pause_auto = pd->pause_auto;
1791                 priv->pause_rx = pd->pause_rx;
1792                 priv->pause_tx = pd->pause_tx;
1793                 priv->force_duplex_full = pd->force_duplex_full;
1794                 priv->force_speed_100 = pd->force_speed_100;
1795                 priv->dma_chan_en_mask = pd->dma_chan_en_mask;
1796                 priv->dma_chan_int_mask = pd->dma_chan_int_mask;
1797                 priv->dma_chan_width = pd->dma_chan_width;
1798                 priv->dma_has_sram = pd->dma_has_sram;
1799                 priv->dma_desc_shift = pd->dma_desc_shift;
1800         }
1801
1802         if (priv->mac_id == 0 && priv->has_phy && !priv->use_external_mii) {
1803                 /* using internal PHY, enable clock */
1804                 priv->phy_clk = clk_get(&pdev->dev, "ephy");
1805                 if (IS_ERR(priv->phy_clk)) {
1806                         ret = PTR_ERR(priv->phy_clk);
1807                         priv->phy_clk = NULL;
1808                         goto out_put_clk_mac;
1809                 }
1810                 clk_prepare_enable(priv->phy_clk);
1811         }
1812
1813         /* do minimal hardware init to be able to probe mii bus */
1814         bcm_enet_hw_preinit(priv);
1815
1816         /* MII bus registration */
1817         if (priv->has_phy) {
1818
1819                 priv->mii_bus = mdiobus_alloc();
1820                 if (!priv->mii_bus) {
1821                         ret = -ENOMEM;
1822                         goto out_uninit_hw;
1823                 }
1824
1825                 bus = priv->mii_bus;
1826                 bus->name = "bcm63xx_enet MII bus";
1827                 bus->parent = &pdev->dev;
1828                 bus->priv = priv;
1829                 bus->read = bcm_enet_mdio_read_phylib;
1830                 bus->write = bcm_enet_mdio_write_phylib;
1831                 sprintf(bus->id, "%s-%d", pdev->name, priv->mac_id);
1832
1833                 /* only probe bus where we think the PHY is, because
1834                  * the mdio read operation return 0 instead of 0xffff
1835                  * if a slave is not present on hw */
1836                 bus->phy_mask = ~(1 << priv->phy_id);
1837
1838                 if (priv->has_phy_interrupt)
1839                         bus->irq[priv->phy_id] = priv->phy_interrupt;
1840
1841                 ret = mdiobus_register(bus);
1842                 if (ret) {
1843                         dev_err(&pdev->dev, "unable to register mdio bus\n");
1844                         goto out_free_mdio;
1845                 }
1846         } else {
1847
1848                 /* run platform code to initialize PHY device */
1849                 if (pd && pd->mii_config &&
1850                     pd->mii_config(dev, 1, bcm_enet_mdio_read_mii,
1851                                    bcm_enet_mdio_write_mii)) {
1852                         dev_err(&pdev->dev, "unable to configure mdio bus\n");
1853                         goto out_uninit_hw;
1854                 }
1855         }
1856
1857         spin_lock_init(&priv->rx_lock);
1858
1859         /* init rx timeout (used for oom) */
1860         init_timer(&priv->rx_timeout);
1861         priv->rx_timeout.function = bcm_enet_refill_rx_timer;
1862         priv->rx_timeout.data = (unsigned long)dev;
1863
1864         /* init the mib update lock&work */
1865         mutex_init(&priv->mib_update_lock);
1866         INIT_WORK(&priv->mib_update_task, bcm_enet_update_mib_counters_defer);
1867
1868         /* zero mib counters */
1869         for (i = 0; i < ENET_MIB_REG_COUNT; i++)
1870                 enet_writel(priv, 0, ENET_MIB_REG(i));
1871
1872         /* register netdevice */
1873         dev->netdev_ops = &bcm_enet_ops;
1874         netif_napi_add(dev, &priv->napi, bcm_enet_poll, 16);
1875
1876         dev->ethtool_ops = &bcm_enet_ethtool_ops;
1877         /* MTU range: 46 - 2028 */
1878         dev->min_mtu = ETH_ZLEN - ETH_HLEN;
1879         dev->max_mtu = BCMENET_MAX_MTU - VLAN_ETH_HLEN;
1880         SET_NETDEV_DEV(dev, &pdev->dev);
1881
1882         ret = register_netdev(dev);
1883         if (ret)
1884                 goto out_unregister_mdio;
1885
1886         netif_carrier_off(dev);
1887         platform_set_drvdata(pdev, dev);
1888         priv->pdev = pdev;
1889         priv->net_dev = dev;
1890
1891         return 0;
1892
1893 out_unregister_mdio:
1894         if (priv->mii_bus)
1895                 mdiobus_unregister(priv->mii_bus);
1896
1897 out_free_mdio:
1898         if (priv->mii_bus)
1899                 mdiobus_free(priv->mii_bus);
1900
1901 out_uninit_hw:
1902         /* turn off mdc clock */
1903         enet_writel(priv, 0, ENET_MIISC_REG);
1904         if (priv->phy_clk) {
1905                 clk_disable_unprepare(priv->phy_clk);
1906                 clk_put(priv->phy_clk);
1907         }
1908
1909 out_put_clk_mac:
1910         clk_disable_unprepare(priv->mac_clk);
1911         clk_put(priv->mac_clk);
1912 out:
1913         free_netdev(dev);
1914         return ret;
1915 }
1916
1917
1918 /*
1919  * exit func, stops hardware and unregisters netdevice
1920  */
1921 static int bcm_enet_remove(struct platform_device *pdev)
1922 {
1923         struct bcm_enet_priv *priv;
1924         struct net_device *dev;
1925
1926         /* stop netdevice */
1927         dev = platform_get_drvdata(pdev);
1928         priv = netdev_priv(dev);
1929         unregister_netdev(dev);
1930
1931         /* turn off mdc clock */
1932         enet_writel(priv, 0, ENET_MIISC_REG);
1933
1934         if (priv->has_phy) {
1935                 mdiobus_unregister(priv->mii_bus);
1936                 mdiobus_free(priv->mii_bus);
1937         } else {
1938                 struct bcm63xx_enet_platform_data *pd;
1939
1940                 pd = dev_get_platdata(&pdev->dev);
1941                 if (pd && pd->mii_config)
1942                         pd->mii_config(dev, 0, bcm_enet_mdio_read_mii,
1943                                        bcm_enet_mdio_write_mii);
1944         }
1945
1946         /* disable hw block clocks */
1947         if (priv->phy_clk) {
1948                 clk_disable_unprepare(priv->phy_clk);
1949                 clk_put(priv->phy_clk);
1950         }
1951         clk_disable_unprepare(priv->mac_clk);
1952         clk_put(priv->mac_clk);
1953
1954         free_netdev(dev);
1955         return 0;
1956 }
1957
1958 struct platform_driver bcm63xx_enet_driver = {
1959         .probe  = bcm_enet_probe,
1960         .remove = bcm_enet_remove,
1961         .driver = {
1962                 .name   = "bcm63xx_enet",
1963                 .owner  = THIS_MODULE,
1964         },
1965 };
1966
1967 /*
1968  * switch mii access callbacks
1969  */
1970 static int bcmenet_sw_mdio_read(struct bcm_enet_priv *priv,
1971                                 int ext, int phy_id, int location)
1972 {
1973         u32 reg;
1974         int ret;
1975
1976         spin_lock_bh(&priv->enetsw_mdio_lock);
1977         enetsw_writel(priv, 0, ENETSW_MDIOC_REG);
1978
1979         reg = ENETSW_MDIOC_RD_MASK |
1980                 (phy_id << ENETSW_MDIOC_PHYID_SHIFT) |
1981                 (location << ENETSW_MDIOC_REG_SHIFT);
1982
1983         if (ext)
1984                 reg |= ENETSW_MDIOC_EXT_MASK;
1985
1986         enetsw_writel(priv, reg, ENETSW_MDIOC_REG);
1987         udelay(50);
1988         ret = enetsw_readw(priv, ENETSW_MDIOD_REG);
1989         spin_unlock_bh(&priv->enetsw_mdio_lock);
1990         return ret;
1991 }
1992
1993 static void bcmenet_sw_mdio_write(struct bcm_enet_priv *priv,
1994                                  int ext, int phy_id, int location,
1995                                  uint16_t data)
1996 {
1997         u32 reg;
1998
1999         spin_lock_bh(&priv->enetsw_mdio_lock);
2000         enetsw_writel(priv, 0, ENETSW_MDIOC_REG);
2001
2002         reg = ENETSW_MDIOC_WR_MASK |
2003                 (phy_id << ENETSW_MDIOC_PHYID_SHIFT) |
2004                 (location << ENETSW_MDIOC_REG_SHIFT);
2005
2006         if (ext)
2007                 reg |= ENETSW_MDIOC_EXT_MASK;
2008
2009         reg |= data;
2010
2011         enetsw_writel(priv, reg, ENETSW_MDIOC_REG);
2012         udelay(50);
2013         spin_unlock_bh(&priv->enetsw_mdio_lock);
2014 }
2015
2016 static inline int bcm_enet_port_is_rgmii(int portid)
2017 {
2018         return portid >= ENETSW_RGMII_PORT0;
2019 }
2020
2021 /*
2022  * enet sw PHY polling
2023  */
2024 static void swphy_poll_timer(unsigned long data)
2025 {
2026         struct bcm_enet_priv *priv = (struct bcm_enet_priv *)data;
2027         unsigned int i;
2028
2029         for (i = 0; i < priv->num_ports; i++) {
2030                 struct bcm63xx_enetsw_port *port;
2031                 int val, j, up, advertise, lpa, speed, duplex, media;
2032                 int external_phy = bcm_enet_port_is_rgmii(i);
2033                 u8 override;
2034
2035                 port = &priv->used_ports[i];
2036                 if (!port->used)
2037                         continue;
2038
2039                 if (port->bypass_link)
2040                         continue;
2041
2042                 /* dummy read to clear */
2043                 for (j = 0; j < 2; j++)
2044                         val = bcmenet_sw_mdio_read(priv, external_phy,
2045                                                    port->phy_id, MII_BMSR);
2046
2047                 if (val == 0xffff)
2048                         continue;
2049
2050                 up = (val & BMSR_LSTATUS) ? 1 : 0;
2051                 if (!(up ^ priv->sw_port_link[i]))
2052                         continue;
2053
2054                 priv->sw_port_link[i] = up;
2055
2056                 /* link changed */
2057                 if (!up) {
2058                         dev_info(&priv->pdev->dev, "link DOWN on %s\n",
2059                                  port->name);
2060                         enetsw_writeb(priv, ENETSW_PORTOV_ENABLE_MASK,
2061                                       ENETSW_PORTOV_REG(i));
2062                         enetsw_writeb(priv, ENETSW_PTCTRL_RXDIS_MASK |
2063                                       ENETSW_PTCTRL_TXDIS_MASK,
2064                                       ENETSW_PTCTRL_REG(i));
2065                         continue;
2066                 }
2067
2068                 advertise = bcmenet_sw_mdio_read(priv, external_phy,
2069                                                  port->phy_id, MII_ADVERTISE);
2070
2071                 lpa = bcmenet_sw_mdio_read(priv, external_phy, port->phy_id,
2072                                            MII_LPA);
2073
2074                 /* figure out media and duplex from advertise and LPA values */
2075                 media = mii_nway_result(lpa & advertise);
2076                 duplex = (media & ADVERTISE_FULL) ? 1 : 0;
2077
2078                 if (media & (ADVERTISE_100FULL | ADVERTISE_100HALF))
2079                         speed = 100;
2080                 else
2081                         speed = 10;
2082
2083                 if (val & BMSR_ESTATEN) {
2084                         advertise = bcmenet_sw_mdio_read(priv, external_phy,
2085                                                 port->phy_id, MII_CTRL1000);
2086
2087                         lpa = bcmenet_sw_mdio_read(priv, external_phy,
2088                                                 port->phy_id, MII_STAT1000);
2089
2090                         if (advertise & (ADVERTISE_1000FULL | ADVERTISE_1000HALF)
2091                                         && lpa & (LPA_1000FULL | LPA_1000HALF)) {
2092                                 speed = 1000;
2093                                 duplex = (lpa & LPA_1000FULL);
2094                         }
2095                 }
2096
2097                 dev_info(&priv->pdev->dev,
2098                          "link UP on %s, %dMbps, %s-duplex\n",
2099                          port->name, speed, duplex ? "full" : "half");
2100
2101                 override = ENETSW_PORTOV_ENABLE_MASK |
2102                         ENETSW_PORTOV_LINKUP_MASK;
2103
2104                 if (speed == 1000)
2105                         override |= ENETSW_IMPOV_1000_MASK;
2106                 else if (speed == 100)
2107                         override |= ENETSW_IMPOV_100_MASK;
2108                 if (duplex)
2109                         override |= ENETSW_IMPOV_FDX_MASK;
2110
2111                 enetsw_writeb(priv, override, ENETSW_PORTOV_REG(i));
2112                 enetsw_writeb(priv, 0, ENETSW_PTCTRL_REG(i));
2113         }
2114
2115         priv->swphy_poll.expires = jiffies + HZ;
2116         add_timer(&priv->swphy_poll);
2117 }
2118
2119 /*
2120  * open callback, allocate dma rings & buffers and start rx operation
2121  */
2122 static int bcm_enetsw_open(struct net_device *dev)
2123 {
2124         struct bcm_enet_priv *priv;
2125         struct device *kdev;
2126         int i, ret;
2127         unsigned int size;
2128         void *p;
2129         u32 val;
2130
2131         priv = netdev_priv(dev);
2132         kdev = &priv->pdev->dev;
2133
2134         /* mask all interrupts and request them */
2135         enet_dmac_writel(priv, 0, ENETDMAC_IRMASK, priv->rx_chan);
2136         enet_dmac_writel(priv, 0, ENETDMAC_IRMASK, priv->tx_chan);
2137
2138         ret = request_irq(priv->irq_rx, bcm_enet_isr_dma,
2139                           0, dev->name, dev);
2140         if (ret)
2141                 goto out_freeirq;
2142
2143         if (priv->irq_tx != -1) {
2144                 ret = request_irq(priv->irq_tx, bcm_enet_isr_dma,
2145                                   0, dev->name, dev);
2146                 if (ret)
2147                         goto out_freeirq_rx;
2148         }
2149
2150         /* allocate rx dma ring */
2151         size = priv->rx_ring_size * sizeof(struct bcm_enet_desc);
2152         p = dma_alloc_coherent(kdev, size, &priv->rx_desc_dma, GFP_KERNEL);
2153         if (!p) {
2154                 dev_err(kdev, "cannot allocate rx ring %u\n", size);
2155                 ret = -ENOMEM;
2156                 goto out_freeirq_tx;
2157         }
2158
2159         memset(p, 0, size);
2160         priv->rx_desc_alloc_size = size;
2161         priv->rx_desc_cpu = p;
2162
2163         /* allocate tx dma ring */
2164         size = priv->tx_ring_size * sizeof(struct bcm_enet_desc);
2165         p = dma_alloc_coherent(kdev, size, &priv->tx_desc_dma, GFP_KERNEL);
2166         if (!p) {
2167                 dev_err(kdev, "cannot allocate tx ring\n");
2168                 ret = -ENOMEM;
2169                 goto out_free_rx_ring;
2170         }
2171
2172         memset(p, 0, size);
2173         priv->tx_desc_alloc_size = size;
2174         priv->tx_desc_cpu = p;
2175
2176         priv->tx_skb = kzalloc(sizeof(struct sk_buff *) * priv->tx_ring_size,
2177                                GFP_KERNEL);
2178         if (!priv->tx_skb) {
2179                 dev_err(kdev, "cannot allocate rx skb queue\n");
2180                 ret = -ENOMEM;
2181                 goto out_free_tx_ring;
2182         }
2183
2184         priv->tx_desc_count = priv->tx_ring_size;
2185         priv->tx_dirty_desc = 0;
2186         priv->tx_curr_desc = 0;
2187         spin_lock_init(&priv->tx_lock);
2188
2189         /* init & fill rx ring with skbs */
2190         priv->rx_skb = kzalloc(sizeof(struct sk_buff *) * priv->rx_ring_size,
2191                                GFP_KERNEL);
2192         if (!priv->rx_skb) {
2193                 dev_err(kdev, "cannot allocate rx skb queue\n");
2194                 ret = -ENOMEM;
2195                 goto out_free_tx_skb;
2196         }
2197
2198         priv->rx_desc_count = 0;
2199         priv->rx_dirty_desc = 0;
2200         priv->rx_curr_desc = 0;
2201
2202         /* disable all ports */
2203         for (i = 0; i < priv->num_ports; i++) {
2204                 enetsw_writeb(priv, ENETSW_PORTOV_ENABLE_MASK,
2205                               ENETSW_PORTOV_REG(i));
2206                 enetsw_writeb(priv, ENETSW_PTCTRL_RXDIS_MASK |
2207                               ENETSW_PTCTRL_TXDIS_MASK,
2208                               ENETSW_PTCTRL_REG(i));
2209
2210                 priv->sw_port_link[i] = 0;
2211         }
2212
2213         /* reset mib */
2214         val = enetsw_readb(priv, ENETSW_GMCR_REG);
2215         val |= ENETSW_GMCR_RST_MIB_MASK;
2216         enetsw_writeb(priv, val, ENETSW_GMCR_REG);
2217         mdelay(1);
2218         val &= ~ENETSW_GMCR_RST_MIB_MASK;
2219         enetsw_writeb(priv, val, ENETSW_GMCR_REG);
2220         mdelay(1);
2221
2222         /* force CPU port state */
2223         val = enetsw_readb(priv, ENETSW_IMPOV_REG);
2224         val |= ENETSW_IMPOV_FORCE_MASK | ENETSW_IMPOV_LINKUP_MASK;
2225         enetsw_writeb(priv, val, ENETSW_IMPOV_REG);
2226
2227         /* enable switch forward engine */
2228         val = enetsw_readb(priv, ENETSW_SWMODE_REG);
2229         val |= ENETSW_SWMODE_FWD_EN_MASK;
2230         enetsw_writeb(priv, val, ENETSW_SWMODE_REG);
2231
2232         /* enable jumbo on all ports */
2233         enetsw_writel(priv, 0x1ff, ENETSW_JMBCTL_PORT_REG);
2234         enetsw_writew(priv, 9728, ENETSW_JMBCTL_MAXSIZE_REG);
2235
2236         /* initialize flow control buffer allocation */
2237         enet_dma_writel(priv, ENETDMA_BUFALLOC_FORCE_MASK | 0,
2238                         ENETDMA_BUFALLOC_REG(priv->rx_chan));
2239
2240         if (bcm_enet_refill_rx(dev)) {
2241                 dev_err(kdev, "cannot allocate rx skb queue\n");
2242                 ret = -ENOMEM;
2243                 goto out;
2244         }
2245
2246         /* write rx & tx ring addresses */
2247         enet_dmas_writel(priv, priv->rx_desc_dma,
2248                          ENETDMAS_RSTART_REG, priv->rx_chan);
2249         enet_dmas_writel(priv, priv->tx_desc_dma,
2250                          ENETDMAS_RSTART_REG, priv->tx_chan);
2251
2252         /* clear remaining state ram for rx & tx channel */
2253         enet_dmas_writel(priv, 0, ENETDMAS_SRAM2_REG, priv->rx_chan);
2254         enet_dmas_writel(priv, 0, ENETDMAS_SRAM2_REG, priv->tx_chan);
2255         enet_dmas_writel(priv, 0, ENETDMAS_SRAM3_REG, priv->rx_chan);
2256         enet_dmas_writel(priv, 0, ENETDMAS_SRAM3_REG, priv->tx_chan);
2257         enet_dmas_writel(priv, 0, ENETDMAS_SRAM4_REG, priv->rx_chan);
2258         enet_dmas_writel(priv, 0, ENETDMAS_SRAM4_REG, priv->tx_chan);
2259
2260         /* set dma maximum burst len */
2261         enet_dmac_writel(priv, priv->dma_maxburst,
2262                          ENETDMAC_MAXBURST, priv->rx_chan);
2263         enet_dmac_writel(priv, priv->dma_maxburst,
2264                          ENETDMAC_MAXBURST, priv->tx_chan);
2265
2266         /* set flow control low/high threshold to 1/3 / 2/3 */
2267         val = priv->rx_ring_size / 3;
2268         enet_dma_writel(priv, val, ENETDMA_FLOWCL_REG(priv->rx_chan));
2269         val = (priv->rx_ring_size * 2) / 3;
2270         enet_dma_writel(priv, val, ENETDMA_FLOWCH_REG(priv->rx_chan));
2271
2272         /* all set, enable mac and interrupts, start dma engine and
2273          * kick rx dma channel
2274          */
2275         wmb();
2276         enet_dma_writel(priv, ENETDMA_CFG_EN_MASK, ENETDMA_CFG_REG);
2277         enet_dmac_writel(priv, ENETDMAC_CHANCFG_EN_MASK,
2278                          ENETDMAC_CHANCFG, priv->rx_chan);
2279
2280         /* watch "packet transferred" interrupt in rx and tx */
2281         enet_dmac_writel(priv, ENETDMAC_IR_PKTDONE_MASK,
2282                          ENETDMAC_IR, priv->rx_chan);
2283         enet_dmac_writel(priv, ENETDMAC_IR_PKTDONE_MASK,
2284                          ENETDMAC_IR, priv->tx_chan);
2285
2286         /* make sure we enable napi before rx interrupt  */
2287         napi_enable(&priv->napi);
2288
2289         enet_dmac_writel(priv, ENETDMAC_IR_PKTDONE_MASK,
2290                          ENETDMAC_IRMASK, priv->rx_chan);
2291         enet_dmac_writel(priv, ENETDMAC_IR_PKTDONE_MASK,
2292                          ENETDMAC_IRMASK, priv->tx_chan);
2293
2294         netif_carrier_on(dev);
2295         netif_start_queue(dev);
2296
2297         /* apply override config for bypass_link ports here. */
2298         for (i = 0; i < priv->num_ports; i++) {
2299                 struct bcm63xx_enetsw_port *port;
2300                 u8 override;
2301                 port = &priv->used_ports[i];
2302                 if (!port->used)
2303                         continue;
2304
2305                 if (!port->bypass_link)
2306                         continue;
2307
2308                 override = ENETSW_PORTOV_ENABLE_MASK |
2309                         ENETSW_PORTOV_LINKUP_MASK;
2310
2311                 switch (port->force_speed) {
2312                 case 1000:
2313                         override |= ENETSW_IMPOV_1000_MASK;
2314                         break;
2315                 case 100:
2316                         override |= ENETSW_IMPOV_100_MASK;
2317                         break;
2318                 case 10:
2319                         break;
2320                 default:
2321                         pr_warn("invalid forced speed on port %s: assume 10\n",
2322                                port->name);
2323                         break;
2324                 }
2325
2326                 if (port->force_duplex_full)
2327                         override |= ENETSW_IMPOV_FDX_MASK;
2328
2329
2330                 enetsw_writeb(priv, override, ENETSW_PORTOV_REG(i));
2331                 enetsw_writeb(priv, 0, ENETSW_PTCTRL_REG(i));
2332         }
2333
2334         /* start phy polling timer */
2335         init_timer(&priv->swphy_poll);
2336         priv->swphy_poll.function = swphy_poll_timer;
2337         priv->swphy_poll.data = (unsigned long)priv;
2338         priv->swphy_poll.expires = jiffies;
2339         add_timer(&priv->swphy_poll);
2340         return 0;
2341
2342 out:
2343         for (i = 0; i < priv->rx_ring_size; i++) {
2344                 struct bcm_enet_desc *desc;
2345
2346                 if (!priv->rx_skb[i])
2347                         continue;
2348
2349                 desc = &priv->rx_desc_cpu[i];
2350                 dma_unmap_single(kdev, desc->address, priv->rx_skb_size,
2351                                  DMA_FROM_DEVICE);
2352                 kfree_skb(priv->rx_skb[i]);
2353         }
2354         kfree(priv->rx_skb);
2355
2356 out_free_tx_skb:
2357         kfree(priv->tx_skb);
2358
2359 out_free_tx_ring:
2360         dma_free_coherent(kdev, priv->tx_desc_alloc_size,
2361                           priv->tx_desc_cpu, priv->tx_desc_dma);
2362
2363 out_free_rx_ring:
2364         dma_free_coherent(kdev, priv->rx_desc_alloc_size,
2365                           priv->rx_desc_cpu, priv->rx_desc_dma);
2366
2367 out_freeirq_tx:
2368         if (priv->irq_tx != -1)
2369                 free_irq(priv->irq_tx, dev);
2370
2371 out_freeirq_rx:
2372         free_irq(priv->irq_rx, dev);
2373
2374 out_freeirq:
2375         return ret;
2376 }
2377
2378 /* stop callback */
2379 static int bcm_enetsw_stop(struct net_device *dev)
2380 {
2381         struct bcm_enet_priv *priv;
2382         struct device *kdev;
2383         int i;
2384
2385         priv = netdev_priv(dev);
2386         kdev = &priv->pdev->dev;
2387
2388         del_timer_sync(&priv->swphy_poll);
2389         netif_stop_queue(dev);
2390         napi_disable(&priv->napi);
2391         del_timer_sync(&priv->rx_timeout);
2392
2393         /* mask all interrupts */
2394         enet_dmac_writel(priv, 0, ENETDMAC_IRMASK, priv->rx_chan);
2395         enet_dmac_writel(priv, 0, ENETDMAC_IRMASK, priv->tx_chan);
2396
2397         /* disable dma & mac */
2398         bcm_enet_disable_dma(priv, priv->tx_chan);
2399         bcm_enet_disable_dma(priv, priv->rx_chan);
2400
2401         /* force reclaim of all tx buffers */
2402         bcm_enet_tx_reclaim(dev, 1);
2403
2404         /* free the rx skb ring */
2405         for (i = 0; i < priv->rx_ring_size; i++) {
2406                 struct bcm_enet_desc *desc;
2407
2408                 if (!priv->rx_skb[i])
2409                         continue;
2410
2411                 desc = &priv->rx_desc_cpu[i];
2412                 dma_unmap_single(kdev, desc->address, priv->rx_skb_size,
2413                                  DMA_FROM_DEVICE);
2414                 kfree_skb(priv->rx_skb[i]);
2415         }
2416
2417         /* free remaining allocated memory */
2418         kfree(priv->rx_skb);
2419         kfree(priv->tx_skb);
2420         dma_free_coherent(kdev, priv->rx_desc_alloc_size,
2421                           priv->rx_desc_cpu, priv->rx_desc_dma);
2422         dma_free_coherent(kdev, priv->tx_desc_alloc_size,
2423                           priv->tx_desc_cpu, priv->tx_desc_dma);
2424         if (priv->irq_tx != -1)
2425                 free_irq(priv->irq_tx, dev);
2426         free_irq(priv->irq_rx, dev);
2427
2428         return 0;
2429 }
2430
2431 /* try to sort out phy external status by walking the used_port field
2432  * in the bcm_enet_priv structure. in case the phy address is not
2433  * assigned to any physical port on the switch, assume it is external
2434  * (and yell at the user).
2435  */
2436 static int bcm_enetsw_phy_is_external(struct bcm_enet_priv *priv, int phy_id)
2437 {
2438         int i;
2439
2440         for (i = 0; i < priv->num_ports; ++i) {
2441                 if (!priv->used_ports[i].used)
2442                         continue;
2443                 if (priv->used_ports[i].phy_id == phy_id)
2444                         return bcm_enet_port_is_rgmii(i);
2445         }
2446
2447         printk_once(KERN_WARNING  "bcm63xx_enet: could not find a used port with phy_id %i, assuming phy is external\n",
2448                     phy_id);
2449         return 1;
2450 }
2451
2452 /* can't use bcmenet_sw_mdio_read directly as we need to sort out
2453  * external/internal status of the given phy_id first.
2454  */
2455 static int bcm_enetsw_mii_mdio_read(struct net_device *dev, int phy_id,
2456                                     int location)
2457 {
2458         struct bcm_enet_priv *priv;
2459
2460         priv = netdev_priv(dev);
2461         return bcmenet_sw_mdio_read(priv,
2462                                     bcm_enetsw_phy_is_external(priv, phy_id),
2463                                     phy_id, location);
2464 }
2465
2466 /* can't use bcmenet_sw_mdio_write directly as we need to sort out
2467  * external/internal status of the given phy_id first.
2468  */
2469 static void bcm_enetsw_mii_mdio_write(struct net_device *dev, int phy_id,
2470                                       int location,
2471                                       int val)
2472 {
2473         struct bcm_enet_priv *priv;
2474
2475         priv = netdev_priv(dev);
2476         bcmenet_sw_mdio_write(priv, bcm_enetsw_phy_is_external(priv, phy_id),
2477                               phy_id, location, val);
2478 }
2479
2480 static int bcm_enetsw_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
2481 {
2482         struct mii_if_info mii;
2483
2484         mii.dev = dev;
2485         mii.mdio_read = bcm_enetsw_mii_mdio_read;
2486         mii.mdio_write = bcm_enetsw_mii_mdio_write;
2487         mii.phy_id = 0;
2488         mii.phy_id_mask = 0x3f;
2489         mii.reg_num_mask = 0x1f;
2490         return generic_mii_ioctl(&mii, if_mii(rq), cmd, NULL);
2491
2492 }
2493
2494 static const struct net_device_ops bcm_enetsw_ops = {
2495         .ndo_open               = bcm_enetsw_open,
2496         .ndo_stop               = bcm_enetsw_stop,
2497         .ndo_start_xmit         = bcm_enet_start_xmit,
2498         .ndo_change_mtu         = bcm_enet_change_mtu,
2499         .ndo_do_ioctl           = bcm_enetsw_ioctl,
2500 };
2501
2502
2503 static const struct bcm_enet_stats bcm_enetsw_gstrings_stats[] = {
2504         { "rx_packets", DEV_STAT(rx_packets), -1 },
2505         { "tx_packets", DEV_STAT(tx_packets), -1 },
2506         { "rx_bytes", DEV_STAT(rx_bytes), -1 },
2507         { "tx_bytes", DEV_STAT(tx_bytes), -1 },
2508         { "rx_errors", DEV_STAT(rx_errors), -1 },
2509         { "tx_errors", DEV_STAT(tx_errors), -1 },
2510         { "rx_dropped", DEV_STAT(rx_dropped), -1 },
2511         { "tx_dropped", DEV_STAT(tx_dropped), -1 },
2512
2513         { "tx_good_octets", GEN_STAT(mib.tx_gd_octets), ETHSW_MIB_RX_GD_OCT },
2514         { "tx_unicast", GEN_STAT(mib.tx_unicast), ETHSW_MIB_RX_BRDCAST },
2515         { "tx_broadcast", GEN_STAT(mib.tx_brdcast), ETHSW_MIB_RX_BRDCAST },
2516         { "tx_multicast", GEN_STAT(mib.tx_mult), ETHSW_MIB_RX_MULT },
2517         { "tx_64_octets", GEN_STAT(mib.tx_64), ETHSW_MIB_RX_64 },
2518         { "tx_65_127_oct", GEN_STAT(mib.tx_65_127), ETHSW_MIB_RX_65_127 },
2519         { "tx_128_255_oct", GEN_STAT(mib.tx_128_255), ETHSW_MIB_RX_128_255 },
2520         { "tx_256_511_oct", GEN_STAT(mib.tx_256_511), ETHSW_MIB_RX_256_511 },
2521         { "tx_512_1023_oct", GEN_STAT(mib.tx_512_1023), ETHSW_MIB_RX_512_1023},
2522         { "tx_1024_1522_oct", GEN_STAT(mib.tx_1024_max),
2523           ETHSW_MIB_RX_1024_1522 },
2524         { "tx_1523_2047_oct", GEN_STAT(mib.tx_1523_2047),
2525           ETHSW_MIB_RX_1523_2047 },
2526         { "tx_2048_4095_oct", GEN_STAT(mib.tx_2048_4095),
2527           ETHSW_MIB_RX_2048_4095 },
2528         { "tx_4096_8191_oct", GEN_STAT(mib.tx_4096_8191),
2529           ETHSW_MIB_RX_4096_8191 },
2530         { "tx_8192_9728_oct", GEN_STAT(mib.tx_8192_9728),
2531           ETHSW_MIB_RX_8192_9728 },
2532         { "tx_oversize", GEN_STAT(mib.tx_ovr), ETHSW_MIB_RX_OVR },
2533         { "tx_oversize_drop", GEN_STAT(mib.tx_ovr), ETHSW_MIB_RX_OVR_DISC },
2534         { "tx_dropped", GEN_STAT(mib.tx_drop), ETHSW_MIB_RX_DROP },
2535         { "tx_undersize", GEN_STAT(mib.tx_underrun), ETHSW_MIB_RX_UND },
2536         { "tx_pause", GEN_STAT(mib.tx_pause), ETHSW_MIB_RX_PAUSE },
2537
2538         { "rx_good_octets", GEN_STAT(mib.rx_gd_octets), ETHSW_MIB_TX_ALL_OCT },
2539         { "rx_broadcast", GEN_STAT(mib.rx_brdcast), ETHSW_MIB_TX_BRDCAST },
2540         { "rx_multicast", GEN_STAT(mib.rx_mult), ETHSW_MIB_TX_MULT },
2541         { "rx_unicast", GEN_STAT(mib.rx_unicast), ETHSW_MIB_TX_MULT },
2542         { "rx_pause", GEN_STAT(mib.rx_pause), ETHSW_MIB_TX_PAUSE },
2543         { "rx_dropped", GEN_STAT(mib.rx_drop), ETHSW_MIB_TX_DROP_PKTS },
2544
2545 };
2546
2547 #define BCM_ENETSW_STATS_LEN    \
2548         (sizeof(bcm_enetsw_gstrings_stats) / sizeof(struct bcm_enet_stats))
2549
2550 static void bcm_enetsw_get_strings(struct net_device *netdev,
2551                                    u32 stringset, u8 *data)
2552 {
2553         int i;
2554
2555         switch (stringset) {
2556         case ETH_SS_STATS:
2557                 for (i = 0; i < BCM_ENETSW_STATS_LEN; i++) {
2558                         memcpy(data + i * ETH_GSTRING_LEN,
2559                                bcm_enetsw_gstrings_stats[i].stat_string,
2560                                ETH_GSTRING_LEN);
2561                 }
2562                 break;
2563         }
2564 }
2565
2566 static int bcm_enetsw_get_sset_count(struct net_device *netdev,
2567                                      int string_set)
2568 {
2569         switch (string_set) {
2570         case ETH_SS_STATS:
2571                 return BCM_ENETSW_STATS_LEN;
2572         default:
2573                 return -EINVAL;
2574         }
2575 }
2576
2577 static void bcm_enetsw_get_drvinfo(struct net_device *netdev,
2578                                    struct ethtool_drvinfo *drvinfo)
2579 {
2580         strncpy(drvinfo->driver, bcm_enet_driver_name, 32);
2581         strncpy(drvinfo->version, bcm_enet_driver_version, 32);
2582         strncpy(drvinfo->fw_version, "N/A", 32);
2583         strncpy(drvinfo->bus_info, "bcm63xx", 32);
2584 }
2585
2586 static void bcm_enetsw_get_ethtool_stats(struct net_device *netdev,
2587                                          struct ethtool_stats *stats,
2588                                          u64 *data)
2589 {
2590         struct bcm_enet_priv *priv;
2591         int i;
2592
2593         priv = netdev_priv(netdev);
2594
2595         for (i = 0; i < BCM_ENETSW_STATS_LEN; i++) {
2596                 const struct bcm_enet_stats *s;
2597                 u32 lo, hi;
2598                 char *p;
2599                 int reg;
2600
2601                 s = &bcm_enetsw_gstrings_stats[i];
2602
2603                 reg = s->mib_reg;
2604                 if (reg == -1)
2605                         continue;
2606
2607                 lo = enetsw_readl(priv, ENETSW_MIB_REG(reg));
2608                 p = (char *)priv + s->stat_offset;
2609
2610                 if (s->sizeof_stat == sizeof(u64)) {
2611                         hi = enetsw_readl(priv, ENETSW_MIB_REG(reg + 1));
2612                         *(u64 *)p = ((u64)hi << 32 | lo);
2613                 } else {
2614                         *(u32 *)p = lo;
2615                 }
2616         }
2617
2618         for (i = 0; i < BCM_ENETSW_STATS_LEN; i++) {
2619                 const struct bcm_enet_stats *s;
2620                 char *p;
2621
2622                 s = &bcm_enetsw_gstrings_stats[i];
2623
2624                 if (s->mib_reg == -1)
2625                         p = (char *)&netdev->stats + s->stat_offset;
2626                 else
2627                         p = (char *)priv + s->stat_offset;
2628
2629                 data[i] = (s->sizeof_stat == sizeof(u64)) ?
2630                         *(u64 *)p : *(u32 *)p;
2631         }
2632 }
2633
2634 static void bcm_enetsw_get_ringparam(struct net_device *dev,
2635                                      struct ethtool_ringparam *ering)
2636 {
2637         struct bcm_enet_priv *priv;
2638
2639         priv = netdev_priv(dev);
2640
2641         /* rx/tx ring is actually only limited by memory */
2642         ering->rx_max_pending = 8192;
2643         ering->tx_max_pending = 8192;
2644         ering->rx_mini_max_pending = 0;
2645         ering->rx_jumbo_max_pending = 0;
2646         ering->rx_pending = priv->rx_ring_size;
2647         ering->tx_pending = priv->tx_ring_size;
2648 }
2649
2650 static int bcm_enetsw_set_ringparam(struct net_device *dev,
2651                                     struct ethtool_ringparam *ering)
2652 {
2653         struct bcm_enet_priv *priv;
2654         int was_running;
2655
2656         priv = netdev_priv(dev);
2657
2658         was_running = 0;
2659         if (netif_running(dev)) {
2660                 bcm_enetsw_stop(dev);
2661                 was_running = 1;
2662         }
2663
2664         priv->rx_ring_size = ering->rx_pending;
2665         priv->tx_ring_size = ering->tx_pending;
2666
2667         if (was_running) {
2668                 int err;
2669
2670                 err = bcm_enetsw_open(dev);
2671                 if (err)
2672                         dev_close(dev);
2673         }
2674         return 0;
2675 }
2676
2677 static const struct ethtool_ops bcm_enetsw_ethtool_ops = {
2678         .get_strings            = bcm_enetsw_get_strings,
2679         .get_sset_count         = bcm_enetsw_get_sset_count,
2680         .get_ethtool_stats      = bcm_enetsw_get_ethtool_stats,
2681         .get_drvinfo            = bcm_enetsw_get_drvinfo,
2682         .get_ringparam          = bcm_enetsw_get_ringparam,
2683         .set_ringparam          = bcm_enetsw_set_ringparam,
2684 };
2685
2686 /* allocate netdevice, request register memory and register device. */
2687 static int bcm_enetsw_probe(struct platform_device *pdev)
2688 {
2689         struct bcm_enet_priv *priv;
2690         struct net_device *dev;
2691         struct bcm63xx_enetsw_platform_data *pd;
2692         struct resource *res_mem;
2693         int ret, irq_rx, irq_tx;
2694
2695         /* stop if shared driver failed, assume driver->probe will be
2696          * called in the same order we register devices (correct ?)
2697          */
2698         if (!bcm_enet_shared_base[0])
2699                 return -ENODEV;
2700
2701         res_mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2702         irq_rx = platform_get_irq(pdev, 0);
2703         irq_tx = platform_get_irq(pdev, 1);
2704         if (!res_mem || irq_rx < 0)
2705                 return -ENODEV;
2706
2707         ret = 0;
2708         dev = alloc_etherdev(sizeof(*priv));
2709         if (!dev)
2710                 return -ENOMEM;
2711         priv = netdev_priv(dev);
2712         memset(priv, 0, sizeof(*priv));
2713
2714         /* initialize default and fetch platform data */
2715         priv->enet_is_sw = true;
2716         priv->irq_rx = irq_rx;
2717         priv->irq_tx = irq_tx;
2718         priv->rx_ring_size = BCMENET_DEF_RX_DESC;
2719         priv->tx_ring_size = BCMENET_DEF_TX_DESC;
2720         priv->dma_maxburst = BCMENETSW_DMA_MAXBURST;
2721
2722         pd = dev_get_platdata(&pdev->dev);
2723         if (pd) {
2724                 memcpy(dev->dev_addr, pd->mac_addr, ETH_ALEN);
2725                 memcpy(priv->used_ports, pd->used_ports,
2726                        sizeof(pd->used_ports));
2727                 priv->num_ports = pd->num_ports;
2728                 priv->dma_has_sram = pd->dma_has_sram;
2729                 priv->dma_chan_en_mask = pd->dma_chan_en_mask;
2730                 priv->dma_chan_int_mask = pd->dma_chan_int_mask;
2731                 priv->dma_chan_width = pd->dma_chan_width;
2732         }
2733
2734         ret = bcm_enet_change_mtu(dev, dev->mtu);
2735         if (ret)
2736                 goto out;
2737
2738         if (!request_mem_region(res_mem->start, resource_size(res_mem),
2739                                 "bcm63xx_enetsw")) {
2740                 ret = -EBUSY;
2741                 goto out;
2742         }
2743
2744         priv->base = ioremap(res_mem->start, resource_size(res_mem));
2745         if (priv->base == NULL) {
2746                 ret = -ENOMEM;
2747                 goto out_release_mem;
2748         }
2749
2750         priv->mac_clk = clk_get(&pdev->dev, "enetsw");
2751         if (IS_ERR(priv->mac_clk)) {
2752                 ret = PTR_ERR(priv->mac_clk);
2753                 goto out_unmap;
2754         }
2755         clk_enable(priv->mac_clk);
2756
2757         priv->rx_chan = 0;
2758         priv->tx_chan = 1;
2759         spin_lock_init(&priv->rx_lock);
2760
2761         /* init rx timeout (used for oom) */
2762         init_timer(&priv->rx_timeout);
2763         priv->rx_timeout.function = bcm_enet_refill_rx_timer;
2764         priv->rx_timeout.data = (unsigned long)dev;
2765
2766         /* register netdevice */
2767         dev->netdev_ops = &bcm_enetsw_ops;
2768         netif_napi_add(dev, &priv->napi, bcm_enet_poll, 16);
2769         dev->ethtool_ops = &bcm_enetsw_ethtool_ops;
2770         SET_NETDEV_DEV(dev, &pdev->dev);
2771
2772         spin_lock_init(&priv->enetsw_mdio_lock);
2773
2774         ret = register_netdev(dev);
2775         if (ret)
2776                 goto out_put_clk;
2777
2778         netif_carrier_off(dev);
2779         platform_set_drvdata(pdev, dev);
2780         priv->pdev = pdev;
2781         priv->net_dev = dev;
2782
2783         return 0;
2784
2785 out_put_clk:
2786         clk_put(priv->mac_clk);
2787
2788 out_unmap:
2789         iounmap(priv->base);
2790
2791 out_release_mem:
2792         release_mem_region(res_mem->start, resource_size(res_mem));
2793 out:
2794         free_netdev(dev);
2795         return ret;
2796 }
2797
2798
2799 /* exit func, stops hardware and unregisters netdevice */
2800 static int bcm_enetsw_remove(struct platform_device *pdev)
2801 {
2802         struct bcm_enet_priv *priv;
2803         struct net_device *dev;
2804         struct resource *res;
2805
2806         /* stop netdevice */
2807         dev = platform_get_drvdata(pdev);
2808         priv = netdev_priv(dev);
2809         unregister_netdev(dev);
2810
2811         /* release device resources */
2812         iounmap(priv->base);
2813         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2814         release_mem_region(res->start, resource_size(res));
2815
2816         free_netdev(dev);
2817         return 0;
2818 }
2819
2820 struct platform_driver bcm63xx_enetsw_driver = {
2821         .probe  = bcm_enetsw_probe,
2822         .remove = bcm_enetsw_remove,
2823         .driver = {
2824                 .name   = "bcm63xx_enetsw",
2825                 .owner  = THIS_MODULE,
2826         },
2827 };
2828
2829 /* reserve & remap memory space shared between all macs */
2830 static int bcm_enet_shared_probe(struct platform_device *pdev)
2831 {
2832         struct resource *res;
2833         void __iomem *p[3];
2834         unsigned int i;
2835
2836         memset(bcm_enet_shared_base, 0, sizeof(bcm_enet_shared_base));
2837
2838         for (i = 0; i < 3; i++) {
2839                 res = platform_get_resource(pdev, IORESOURCE_MEM, i);
2840                 p[i] = devm_ioremap_resource(&pdev->dev, res);
2841                 if (IS_ERR(p[i]))
2842                         return PTR_ERR(p[i]);
2843         }
2844
2845         memcpy(bcm_enet_shared_base, p, sizeof(bcm_enet_shared_base));
2846
2847         return 0;
2848 }
2849
2850 static int bcm_enet_shared_remove(struct platform_device *pdev)
2851 {
2852         return 0;
2853 }
2854
2855 /* this "shared" driver is needed because both macs share a single
2856  * address space
2857  */
2858 struct platform_driver bcm63xx_enet_shared_driver = {
2859         .probe  = bcm_enet_shared_probe,
2860         .remove = bcm_enet_shared_remove,
2861         .driver = {
2862                 .name   = "bcm63xx_enet_shared",
2863                 .owner  = THIS_MODULE,
2864         },
2865 };
2866
2867 static struct platform_driver * const drivers[] = {
2868         &bcm63xx_enet_shared_driver,
2869         &bcm63xx_enet_driver,
2870         &bcm63xx_enetsw_driver,
2871 };
2872
2873 /* entry point */
2874 static int __init bcm_enet_init(void)
2875 {
2876         return platform_register_drivers(drivers, ARRAY_SIZE(drivers));
2877 }
2878
2879 static void __exit bcm_enet_exit(void)
2880 {
2881         platform_unregister_drivers(drivers, ARRAY_SIZE(drivers));
2882 }
2883
2884
2885 module_init(bcm_enet_init);
2886 module_exit(bcm_enet_exit);
2887
2888 MODULE_DESCRIPTION("BCM63xx internal ethernet mac driver");
2889 MODULE_AUTHOR("Maxime Bizon <mbizon@freebox.fr>");
2890 MODULE_LICENSE("GPL");