drivers/net/ethernet/broadcom/bcm63xx_enet.c

   1 /*
   2  * Driver for BCM963xx builtin Ethernet mac
   3  *
   4  * Copyright (C) 2008 Maxime Bizon <mbizon@freebox.fr>
   5  *
   6  * This program is free software; you can redistribute it and/or modify
   7  * it under the terms of the GNU General Public License as published by
   8  * the Free Software Foundation; either version 2 of the License, or
   9  * (at your option) any later version.
  10  *
  11  * This program is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  14  * GNU General Public License for more details.
  15  *
  16  * You should have received a copy of the GNU General Public License
  17  * along with this program; if not, write to the Free Software
  18  * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
  19  */
  20 #include <linux/init.h>
  21 #include <linux/interrupt.h>
  22 #include <linux/module.h>
  23 #include <linux/clk.h>
  24 #include <linux/etherdevice.h>
  25 #include <linux/slab.h>
  26 #include <linux/delay.h>
  27 #include <linux/ethtool.h>
  28 #include <linux/crc32.h>
  29 #include <linux/err.h>
  30 #include <linux/dma-mapping.h>
  31 #include <linux/platform_device.h>
  32 #include <linux/if_vlan.h>
  33
  34 #include <bcm63xx_dev_enet.h>
  35 #include "bcm63xx_enet.h"
  36
  37 static char bcm_enet_driver_name[] = "bcm63xx_enet";
  38 static char bcm_enet_driver_version[] = "1.0";
  39
  40 static int copybreak __read_mostly = 128;
  41 module_param(copybreak, int, 0);
  42 MODULE_PARM_DESC(copybreak, "Receive copy threshold");
  43
  44 /* io registers memory shared between all devices */
  45 static void __iomem *bcm_enet_shared_base[3];
  46
  47 /*
  48  * io helpers to access mac registers
  49  */
  50 static inline u32 enet_readl(struct bcm_enet_priv *priv, u32 off)
  51 {
  52         return bcm_readl(priv->base + off);
  53 }
  54
  55 static inline void enet_writel(struct bcm_enet_priv *priv,
  56                                u32 val, u32 off)
  57 {
  58         bcm_writel(val, priv->base + off);
  59 }
  60
  61 /*
  62  * io helpers to access switch registers
  63  */
  64 static inline u32 enetsw_readl(struct bcm_enet_priv *priv, u32 off)
  65 {
  66         return bcm_readl(priv->base + off);
  67 }
  68
  69 static inline void enetsw_writel(struct bcm_enet_priv *priv,
  70                                  u32 val, u32 off)
  71 {
  72         bcm_writel(val, priv->base + off);
  73 }
  74
  75 static inline u16 enetsw_readw(struct bcm_enet_priv *priv, u32 off)
  76 {
  77         return bcm_readw(priv->base + off);
  78 }
  79
  80 static inline void enetsw_writew(struct bcm_enet_priv *priv,
  81                                  u16 val, u32 off)
  82 {
  83         bcm_writew(val, priv->base + off);
  84 }
  85
  86 static inline u8 enetsw_readb(struct bcm_enet_priv *priv, u32 off)
  87 {
  88         return bcm_readb(priv->base + off);
  89 }
  90
  91 static inline void enetsw_writeb(struct bcm_enet_priv *priv,
  92                                  u8 val, u32 off)
  93 {
  94         bcm_writeb(val, priv->base + off);
  95 }
  96
  97
  98 /* io helpers to access shared registers */
  99 static inline u32 enet_dma_readl(struct bcm_enet_priv *priv, u32 off)
 100 {
 101         return bcm_readl(bcm_enet_shared_base[0] + off);
 102 }
 103
 104 static inline void enet_dma_writel(struct bcm_enet_priv *priv,
 105                                        u32 val, u32 off)
 106 {
 107         bcm_writel(val, bcm_enet_shared_base[0] + off);
 108 }
 109
 110 static inline u32 enet_dmac_readl(struct bcm_enet_priv *priv, u32 off, int chan)
 111 {
 112         return bcm_readl(bcm_enet_shared_base[1] +
 113                 bcm63xx_enetdmacreg(off) + chan * priv->dma_chan_width);
 114 }
 115
 116 static inline void enet_dmac_writel(struct bcm_enet_priv *priv,
 117                                        u32 val, u32 off, int chan)
 118 {
 119         bcm_writel(val, bcm_enet_shared_base[1] +
 120                 bcm63xx_enetdmacreg(off) + chan * priv->dma_chan_width);
 121 }
 122
 123 static inline u32 enet_dmas_readl(struct bcm_enet_priv *priv, u32 off, int chan)
 124 {
 125         return bcm_readl(bcm_enet_shared_base[2] + off + chan * priv->dma_chan_width);
 126 }
 127
 128 static inline void enet_dmas_writel(struct bcm_enet_priv *priv,
 129                                        u32 val, u32 off, int chan)
 130 {
 131         bcm_writel(val, bcm_enet_shared_base[2] + off + chan * priv->dma_chan_width);
 132 }
 133
 134 /*
 135  * write given data into mii register and wait for transfer to end
 136  * with timeout (average measured transfer time is 25us)
 137  */
 138 static int do_mdio_op(struct bcm_enet_priv *priv, unsigned int data)
 139 {
 140         int limit;
 141
 142         /* make sure mii interrupt status is cleared */
 143         enet_writel(priv, ENET_IR_MII, ENET_IR_REG);
 144
 145         enet_writel(priv, data, ENET_MIIDATA_REG);
 146         wmb();
 147
 148         /* busy wait on mii interrupt bit, with timeout */
 149         limit = 1000;
 150         do {
 151                 if (enet_readl(priv, ENET_IR_REG) & ENET_IR_MII)
 152                         break;
 153                 udelay(1);
 154         } while (limit-- > 0);
 155
 156         return (limit < 0) ? 1 : 0;
 157 }
 158
 159 /*
 160  * MII internal read callback
 161  */
 162 static int bcm_enet_mdio_read(struct bcm_enet_priv *priv, int mii_id,
 163                               int regnum)
 164 {
 165         u32 tmp, val;
 166
 167         tmp = regnum << ENET_MIIDATA_REG_SHIFT;
 168         tmp |= 0x2 << ENET_MIIDATA_TA_SHIFT;
 169         tmp |= mii_id << ENET_MIIDATA_PHYID_SHIFT;
 170         tmp |= ENET_MIIDATA_OP_READ_MASK;
 171
 172         if (do_mdio_op(priv, tmp))
 173                 return -1;
 174
 175         val = enet_readl(priv, ENET_MIIDATA_REG);
 176         val &= 0xffff;
 177         return val;
 178 }
 179
 180 /*
 181  * MII internal write callback
 182  */
 183 static int bcm_enet_mdio_write(struct bcm_enet_priv *priv, int mii_id,
 184                                int regnum, u16 value)
 185 {
 186         u32 tmp;
 187
 188         tmp = (value & 0xffff) << ENET_MIIDATA_DATA_SHIFT;
 189         tmp |= 0x2 << ENET_MIIDATA_TA_SHIFT;
 190         tmp |= regnum << ENET_MIIDATA_REG_SHIFT;
 191         tmp |= mii_id << ENET_MIIDATA_PHYID_SHIFT;
 192         tmp |= ENET_MIIDATA_OP_WRITE_MASK;
 193
 194         (void)do_mdio_op(priv, tmp);
 195         return 0;
 196 }
 197
 198 /*
 199  * MII read callback from phylib
 200  */
 201 static int bcm_enet_mdio_read_phylib(struct mii_bus *bus, int mii_id,
 202                                      int regnum)
 203 {
 204         return bcm_enet_mdio_read(bus->priv, mii_id, regnum);
 205 }
 206
 207 /*
 208  * MII write callback from phylib
 209  */
 210 static int bcm_enet_mdio_write_phylib(struct mii_bus *bus, int mii_id,
 211                                       int regnum, u16 value)
 212 {
 213         return bcm_enet_mdio_write(bus->priv, mii_id, regnum, value);
 214 }
 215
 216 /*
 217  * MII read callback from mii core
 218  */
 219 static int bcm_enet_mdio_read_mii(struct net_device *dev, int mii_id,
 220                                   int regnum)
 221 {
 222         return bcm_enet_mdio_read(netdev_priv(dev), mii_id, regnum);
 223 }
 224
 225 /*
 226  * MII write callback from mii core
 227  */
 228 static void bcm_enet_mdio_write_mii(struct net_device *dev, int mii_id,
 229                                     int regnum, int value)
 230 {
 231         bcm_enet_mdio_write(netdev_priv(dev), mii_id, regnum, value);
 232 }
 233
 234 /*
 235  * refill rx queue
 236  */
 237 static int bcm_enet_refill_rx(struct net_device *dev)
 238 {
 239         struct bcm_enet_priv *priv;
 240
 241         priv = netdev_priv(dev);
 242
 243         while (priv->rx_desc_count < priv->rx_ring_size) {
 244                 struct bcm_enet_desc *desc;
 245                 struct sk_buff *skb;
 246                 dma_addr_t p;
 247                 int desc_idx;
 248                 u32 len_stat;
 249
 250                 desc_idx = priv->rx_dirty_desc;
 251                 desc = &priv->rx_desc_cpu[desc_idx];
 252
 253                 if (!priv->rx_skb[desc_idx]) {
 254                         skb = netdev_alloc_skb(dev, priv->rx_skb_size);
 255                         if (!skb)
 256                                 break;
 257                         priv->rx_skb[desc_idx] = skb;
 258                         p = dma_map_single(&priv->pdev->dev, skb->data,
 259                                            priv->rx_skb_size,
 260                                            DMA_FROM_DEVICE);
 261                         desc->address = p;
 262                 }
 263
 264                 len_stat = priv->rx_skb_size << DMADESC_LENGTH_SHIFT;
 265                 len_stat |= DMADESC_OWNER_MASK;
 266                 if (priv->rx_dirty_desc == priv->rx_ring_size - 1) {
 267                         len_stat |= (DMADESC_WRAP_MASK >> priv->dma_desc_shift);
 268                         priv->rx_dirty_desc = 0;
 269                 } else {
 270                         priv->rx_dirty_desc++;
 271                 }
 272                 wmb();
 273                 desc->len_stat = len_stat;
 274
 275                 priv->rx_desc_count++;
 276
 277                 /* tell dma engine we allocated one buffer */
 278                 if (priv->dma_has_sram)
 279                         enet_dma_writel(priv, 1, ENETDMA_BUFALLOC_REG(priv->rx_chan));
 280                 else
 281                         enet_dmac_writel(priv, 1, ENETDMAC_BUFALLOC, priv->rx_chan);
 282         }
 283
 284         /* If rx ring is still empty, set a timer to try allocating
 285          * again at a later time. */
 286         if (priv->rx_desc_count == 0 && netif_running(dev)) {
 287                 dev_warn(&priv->pdev->dev, "unable to refill rx ring\n");
 288                 priv->rx_timeout.expires = jiffies + HZ;
 289                 add_timer(&priv->rx_timeout);
 290         }
 291
 292         return 0;
 293 }
 294
 295 /*
 296  * timer callback to defer refill rx queue in case we're OOM
 297  */
 298 static void bcm_enet_refill_rx_timer(struct timer_list *t)
 299 {
 300         struct bcm_enet_priv *priv = from_timer(priv, t, rx_timeout);
 301         struct net_device *dev = priv->net_dev;
 302
 303         spin_lock(&priv->rx_lock);
 304         bcm_enet_refill_rx(dev);
 305         spin_unlock(&priv->rx_lock);
 306 }
 307
 308 /*
 309  * extract packet from rx queue
 310  */
 311 static int bcm_enet_receive_queue(struct net_device *dev, int budget)
 312 {
 313         struct bcm_enet_priv *priv;
 314         struct device *kdev;
 315         int processed;
 316
 317         priv = netdev_priv(dev);
 318         kdev = &priv->pdev->dev;
 319         processed = 0;
 320
 321         /* don't scan ring further than number of refilled
 322          * descriptor */
 323         if (budget > priv->rx_desc_count)
 324                 budget = priv->rx_desc_count;
 325
 326         do {
 327                 struct bcm_enet_desc *desc;
 328                 struct sk_buff *skb;
 329                 int desc_idx;
 330                 u32 len_stat;
 331                 unsigned int len;
 332
 333                 desc_idx = priv->rx_curr_desc;
 334                 desc = &priv->rx_desc_cpu[desc_idx];
 335
 336                 /* make sure we actually read the descriptor status at
 337                  * each loop */
 338                 rmb();
 339
 340                 len_stat = desc->len_stat;
 341
 342                 /* break if dma ownership belongs to hw */
 343                 if (len_stat & DMADESC_OWNER_MASK)
 344                         break;
 345
 346                 processed++;
 347                 priv->rx_curr_desc++;
 348                 if (priv->rx_curr_desc == priv->rx_ring_size)
 349                         priv->rx_curr_desc = 0;
 350                 priv->rx_desc_count--;
 351
 352                 /* if the packet does not have start of packet _and_
 353                  * end of packet flag set, then just recycle it */
 354                 if ((len_stat & (DMADESC_ESOP_MASK >> priv->dma_desc_shift)) !=
 355                         (DMADESC_ESOP_MASK >> priv->dma_desc_shift)) {
 356                         dev->stats.rx_dropped++;
 357                         continue;
 358                 }
 359
 360                 /* recycle packet if it's marked as bad */
 361                 if (!priv->enet_is_sw &&
 362                     unlikely(len_stat & DMADESC_ERR_MASK)) {
 363                         dev->stats.rx_errors++;
 364
 365                         if (len_stat & DMADESC_OVSIZE_MASK)
 366                                 dev->stats.rx_length_errors++;
 367                         if (len_stat & DMADESC_CRC_MASK)
 368                                 dev->stats.rx_crc_errors++;
 369                         if (len_stat & DMADESC_UNDER_MASK)
 370                                 dev->stats.rx_frame_errors++;
 371                         if (len_stat & DMADESC_OV_MASK)
 372                                 dev->stats.rx_fifo_errors++;
 373                         continue;
 374                 }
 375
 376                 /* valid packet */
 377                 skb = priv->rx_skb[desc_idx];
 378                 len = (len_stat & DMADESC_LENGTH_MASK) >> DMADESC_LENGTH_SHIFT;
 379                 /* don't include FCS */
 380                 len -= 4;
 381
 382                 if (len < copybreak) {
 383                         struct sk_buff *nskb;
 384
 385                         nskb = napi_alloc_skb(&priv->napi, len);
 386                         if (!nskb) {
 387                                 /* forget packet, just rearm desc */
 388                                 dev->stats.rx_dropped++;
 389                                 continue;
 390                         }
 391
 392                         dma_sync_single_for_cpu(kdev, desc->address,
 393                                                 len, DMA_FROM_DEVICE);
 394                         memcpy(nskb->data, skb->data, len);
 395                         dma_sync_single_for_device(kdev, desc->address,
 396                                                    len, DMA_FROM_DEVICE);
 397                         skb = nskb;
 398                 } else {
 399                         dma_unmap_single(&priv->pdev->dev, desc->address,
 400                                          priv->rx_skb_size, DMA_FROM_DEVICE);
 401                         priv->rx_skb[desc_idx] = NULL;
 402                 }
 403
 404                 skb_put(skb, len);
 405                 skb->protocol = eth_type_trans(skb, dev);
 406                 dev->stats.rx_packets++;
 407                 dev->stats.rx_bytes += len;
 408                 netif_receive_skb(skb);
 409
 410         } while (--budget > 0);
 411
 412         if (processed || !priv->rx_desc_count) {
 413                 bcm_enet_refill_rx(dev);
 414
 415                 /* kick rx dma */
 416                 enet_dmac_writel(priv, priv->dma_chan_en_mask,
 417                                          ENETDMAC_CHANCFG, priv->rx_chan);
 418         }
 419
 420         return processed;
 421 }
 422
 423
 424 /*
 425  * try to or force reclaim of transmitted buffers
 426  */
 427 static int bcm_enet_tx_reclaim(struct net_device *dev, int force)
 428 {
 429         struct bcm_enet_priv *priv;
 430         int released;
 431
 432         priv = netdev_priv(dev);
 433         released = 0;
 434
 435         while (priv->tx_desc_count < priv->tx_ring_size) {
 436                 struct bcm_enet_desc *desc;
 437                 struct sk_buff *skb;
 438
 439                 /* We run in a bh and fight against start_xmit, which
 440                  * is called with bh disabled  */
 441                 spin_lock(&priv->tx_lock);
 442
 443                 desc = &priv->tx_desc_cpu[priv->tx_dirty_desc];
 444
 445                 if (!force && (desc->len_stat & DMADESC_OWNER_MASK)) {
 446                         spin_unlock(&priv->tx_lock);
 447                         break;
 448                 }
 449
 450                 /* ensure other field of the descriptor were not read
 451                  * before we checked ownership */
 452                 rmb();
 453
 454                 skb = priv->tx_skb[priv->tx_dirty_desc];
 455                 priv->tx_skb[priv->tx_dirty_desc] = NULL;
 456                 dma_unmap_single(&priv->pdev->dev, desc->address, skb->len,
 457                                  DMA_TO_DEVICE);
 458
 459                 priv->tx_dirty_desc++;
 460                 if (priv->tx_dirty_desc == priv->tx_ring_size)
 461                         priv->tx_dirty_desc = 0;
 462                 priv->tx_desc_count++;
 463
 464                 spin_unlock(&priv->tx_lock);
 465
 466                 if (desc->len_stat & DMADESC_UNDER_MASK)
 467                         dev->stats.tx_errors++;
 468
 469                 dev_kfree_skb(skb);
 470                 released++;
 471         }
 472
 473         if (netif_queue_stopped(dev) && released)
 474                 netif_wake_queue(dev);
 475
 476         return released;
 477 }
 478
 479 /*
 480  * poll func, called by network core
 481  */
 482 static int bcm_enet_poll(struct napi_struct *napi, int budget)
 483 {
 484         struct bcm_enet_priv *priv;
 485         struct net_device *dev;
 486         int rx_work_done;
 487
 488         priv = container_of(napi, struct bcm_enet_priv, napi);
 489         dev = priv->net_dev;
 490
 491         /* ack interrupts */
 492         enet_dmac_writel(priv, priv->dma_chan_int_mask,
 493                          ENETDMAC_IR, priv->rx_chan);
 494         enet_dmac_writel(priv, priv->dma_chan_int_mask,
 495                          ENETDMAC_IR, priv->tx_chan);
 496
 497         /* reclaim sent skb */
 498         bcm_enet_tx_reclaim(dev, 0);
 499
 500         spin_lock(&priv->rx_lock);
 501         rx_work_done = bcm_enet_receive_queue(dev, budget);
 502         spin_unlock(&priv->rx_lock);
 503
 504         if (rx_work_done >= budget) {
 505                 /* rx queue is not yet empty/clean */
 506                 return rx_work_done;
 507         }
 508
 509         /* no more packet in rx/tx queue, remove device from poll
 510          * queue */
 511         napi_complete_done(napi, rx_work_done);
 512
 513         /* restore rx/tx interrupt */
 514         enet_dmac_writel(priv, priv->dma_chan_int_mask,
 515                          ENETDMAC_IRMASK, priv->rx_chan);
 516         enet_dmac_writel(priv, priv->dma_chan_int_mask,
 517                          ENETDMAC_IRMASK, priv->tx_chan);
 518
 519         return rx_work_done;
 520 }
 521
 522 /*
 523  * mac interrupt handler
 524  */
 525 static irqreturn_t bcm_enet_isr_mac(int irq, void *dev_id)
 526 {
 527         struct net_device *dev;
 528         struct bcm_enet_priv *priv;
 529         u32 stat;
 530
 531         dev = dev_id;
 532         priv = netdev_priv(dev);
 533
 534         stat = enet_readl(priv, ENET_IR_REG);
 535         if (!(stat & ENET_IR_MIB))
 536                 return IRQ_NONE;
 537
 538         /* clear & mask interrupt */
 539         enet_writel(priv, ENET_IR_MIB, ENET_IR_REG);
 540         enet_writel(priv, 0, ENET_IRMASK_REG);
 541
 542         /* read mib registers in workqueue */
 543         schedule_work(&priv->mib_update_task);
 544
 545         return IRQ_HANDLED;
 546 }
 547
 548 /*
 549  * rx/tx dma interrupt handler
 550  */
 551 static irqreturn_t bcm_enet_isr_dma(int irq, void *dev_id)
 552 {
 553         struct net_device *dev;
 554         struct bcm_enet_priv *priv;
 555
 556         dev = dev_id;
 557         priv = netdev_priv(dev);
 558
 559         /* mask rx/tx interrupts */
 560         enet_dmac_writel(priv, 0, ENETDMAC_IRMASK, priv->rx_chan);
 561         enet_dmac_writel(priv, 0, ENETDMAC_IRMASK, priv->tx_chan);
 562
 563         napi_schedule(&priv->napi);
 564
 565         return IRQ_HANDLED;
 566 }
 567
 568 /*
 569  * tx request callback
 570  */
 571 static int bcm_enet_start_xmit(struct sk_buff *skb, struct net_device *dev)
 572 {
 573         struct bcm_enet_priv *priv;
 574         struct bcm_enet_desc *desc;
 575         u32 len_stat;
 576         int ret;
 577
 578         priv = netdev_priv(dev);
 579
 580         /* lock against tx reclaim */
 581         spin_lock(&priv->tx_lock);
 582
 583         /* make sure  the tx hw queue  is not full,  should not happen
 584          * since we stop queue before it's the case */
 585         if (unlikely(!priv->tx_desc_count)) {
 586                 netif_stop_queue(dev);
 587                 dev_err(&priv->pdev->dev, "xmit called with no tx desc "
 588                         "available?\n");
 589                 ret = NETDEV_TX_BUSY;
 590                 goto out_unlock;
 591         }
 592
 593         /* pad small packets sent on a switch device */
 594         if (priv->enet_is_sw && skb->len < 64) {
 595                 int needed = 64 - skb->len;
 596                 char *data;
 597
 598                 if (unlikely(skb_tailroom(skb) < needed)) {
 599                         struct sk_buff *nskb;
 600
 601                         nskb = skb_copy_expand(skb, 0, needed, GFP_ATOMIC);
 602                         if (!nskb) {
 603                                 ret = NETDEV_TX_BUSY;
 604                                 goto out_unlock;
 605                         }
 606                         dev_kfree_skb(skb);
 607                         skb = nskb;
 608                 }
 609                 data = skb_put_zero(skb, needed);
 610         }
 611
 612         /* point to the next available desc */
 613         desc = &priv->tx_desc_cpu[priv->tx_curr_desc];
 614         priv->tx_skb[priv->tx_curr_desc] = skb;
 615
 616         /* fill descriptor */
 617         desc->address = dma_map_single(&priv->pdev->dev, skb->data, skb->len,
 618                                        DMA_TO_DEVICE);
 619
 620         len_stat = (skb->len << DMADESC_LENGTH_SHIFT) & DMADESC_LENGTH_MASK;
 621         len_stat |= (DMADESC_ESOP_MASK >> priv->dma_desc_shift) |
 622                 DMADESC_APPEND_CRC |
 623                 DMADESC_OWNER_MASK;
 624
 625         priv->tx_curr_desc++;
 626         if (priv->tx_curr_desc == priv->tx_ring_size) {
 627                 priv->tx_curr_desc = 0;
 628                 len_stat |= (DMADESC_WRAP_MASK >> priv->dma_desc_shift);
 629         }
 630         priv->tx_desc_count--;
 631
 632         /* dma might be already polling, make sure we update desc
 633          * fields in correct order */
 634         wmb();
 635         desc->len_stat = len_stat;
 636         wmb();
 637
 638         /* kick tx dma */
 639         enet_dmac_writel(priv, priv->dma_chan_en_mask,
 640                                  ENETDMAC_CHANCFG, priv->tx_chan);
 641
 642         /* stop queue if no more desc available */
 643         if (!priv->tx_desc_count)
 644                 netif_stop_queue(dev);
 645
 646         dev->stats.tx_bytes += skb->len;
 647         dev->stats.tx_packets++;
 648         ret = NETDEV_TX_OK;
 649
 650 out_unlock:
 651         spin_unlock(&priv->tx_lock);
 652         return ret;
 653 }
 654
 655 /*
 656  * Change the interface's mac address.
 657  */
 658 static int bcm_enet_set_mac_address(struct net_device *dev, void *p)
 659 {
 660         struct bcm_enet_priv *priv;
 661         struct sockaddr *addr = p;
 662         u32 val;
 663
 664         priv = netdev_priv(dev);
 665         memcpy(dev->dev_addr, addr->sa_data, ETH_ALEN);
 666
 667         /* use perfect match register 0 to store my mac address */
 668         val = (dev->dev_addr[2] << 24) | (dev->dev_addr[3] << 16) |
 669                 (dev->dev_addr[4] << 8) | dev->dev_addr[5];
 670         enet_writel(priv, val, ENET_PML_REG(0));
 671
 672         val = (dev->dev_addr[0] << 8 | dev->dev_addr[1]);
 673         val |= ENET_PMH_DATAVALID_MASK;
 674         enet_writel(priv, val, ENET_PMH_REG(0));
 675
 676         return 0;
 677 }
 678
 679 /*
 680  * Change rx mode (promiscuous/allmulti) and update multicast list
 681  */
 682 static void bcm_enet_set_multicast_list(struct net_device *dev)
 683 {
 684         struct bcm_enet_priv *priv;
 685         struct netdev_hw_addr *ha;
 686         u32 val;
 687         int i;
 688
 689         priv = netdev_priv(dev);
 690
 691         val = enet_readl(priv, ENET_RXCFG_REG);
 692
 693         if (dev->flags & IFF_PROMISC)
 694                 val |= ENET_RXCFG_PROMISC_MASK;
 695         else
 696                 val &= ~ENET_RXCFG_PROMISC_MASK;
 697
 698         /* only 3 perfect match registers left, first one is used for
 699          * own mac address */
 700         if ((dev->flags & IFF_ALLMULTI) || netdev_mc_count(dev) > 3)
 701                 val |= ENET_RXCFG_ALLMCAST_MASK;
 702         else
 703                 val &= ~ENET_RXCFG_ALLMCAST_MASK;
 704
 705         /* no need to set perfect match registers if we catch all
 706          * multicast */
 707         if (val & ENET_RXCFG_ALLMCAST_MASK) {
 708                 enet_writel(priv, val, ENET_RXCFG_REG);
 709                 return;
 710         }
 711
 712         i = 0;
 713         netdev_for_each_mc_addr(ha, dev) {
 714                 u8 *dmi_addr;
 715                 u32 tmp;
 716
 717                 if (i == 3)
 718                         break;
 719                 /* update perfect match registers */
 720                 dmi_addr = ha->addr;
 721                 tmp = (dmi_addr[2] << 24) | (dmi_addr[3] << 16) |
 722                         (dmi_addr[4] << 8) | dmi_addr[5];
 723                 enet_writel(priv, tmp, ENET_PML_REG(i + 1));
 724
 725                 tmp = (dmi_addr[0] << 8 | dmi_addr[1]);
 726                 tmp |= ENET_PMH_DATAVALID_MASK;
 727                 enet_writel(priv, tmp, ENET_PMH_REG(i++ + 1));
 728         }
 729
 730         for (; i < 3; i++) {
 731                 enet_writel(priv, 0, ENET_PML_REG(i + 1));
 732                 enet_writel(priv, 0, ENET_PMH_REG(i + 1));
 733         }
 734
 735         enet_writel(priv, val, ENET_RXCFG_REG);
 736 }
 737
 738 /*
 739  * set mac duplex parameters
 740  */
 741 static void bcm_enet_set_duplex(struct bcm_enet_priv *priv, int fullduplex)
 742 {
 743         u32 val;
 744
 745         val = enet_readl(priv, ENET_TXCTL_REG);
 746         if (fullduplex)
 747                 val |= ENET_TXCTL_FD_MASK;
 748         else
 749                 val &= ~ENET_TXCTL_FD_MASK;
 750         enet_writel(priv, val, ENET_TXCTL_REG);
 751 }
 752
 753 /*
 754  * set mac flow control parameters
 755  */
 756 static void bcm_enet_set_flow(struct bcm_enet_priv *priv, int rx_en, int tx_en)
 757 {
 758         u32 val;
 759
 760         /* rx flow control (pause frame handling) */
 761         val = enet_readl(priv, ENET_RXCFG_REG);
 762         if (rx_en)
 763                 val |= ENET_RXCFG_ENFLOW_MASK;
 764         else
 765                 val &= ~ENET_RXCFG_ENFLOW_MASK;
 766         enet_writel(priv, val, ENET_RXCFG_REG);
 767
 768         if (!priv->dma_has_sram)
 769                 return;
 770
 771         /* tx flow control (pause frame generation) */
 772         val = enet_dma_readl(priv, ENETDMA_CFG_REG);
 773         if (tx_en)
 774                 val |= ENETDMA_CFG_FLOWCH_MASK(priv->rx_chan);
 775         else
 776                 val &= ~ENETDMA_CFG_FLOWCH_MASK(priv->rx_chan);
 777         enet_dma_writel(priv, val, ENETDMA_CFG_REG);
 778 }
 779
 780 /*
 781  * link changed callback (from phylib)
 782  */
 783 static void bcm_enet_adjust_phy_link(struct net_device *dev)
 784 {
 785         struct bcm_enet_priv *priv;
 786         struct phy_device *phydev;
 787         int status_changed;
 788
 789         priv = netdev_priv(dev);
 790         phydev = dev->phydev;
 791         status_changed = 0;
 792
 793         if (priv->old_link != phydev->link) {
 794                 status_changed = 1;
 795                 priv->old_link = phydev->link;
 796         }
 797
 798         /* reflect duplex change in mac configuration */
 799         if (phydev->link && phydev->duplex != priv->old_duplex) {
 800                 bcm_enet_set_duplex(priv,
 801                                     (phydev->duplex == DUPLEX_FULL) ? 1 : 0);
 802                 status_changed = 1;
 803                 priv->old_duplex = phydev->duplex;
 804         }
 805
 806         /* enable flow control if remote advertise it (trust phylib to
 807          * check that duplex is full */
 808         if (phydev->link && phydev->pause != priv->old_pause) {
 809                 int rx_pause_en, tx_pause_en;
 810
 811                 if (phydev->pause) {
 812                         /* pause was advertised by lpa and us */
 813                         rx_pause_en = 1;
 814                         tx_pause_en = 1;
 815                 } else if (!priv->pause_auto) {
 816                         /* pause setting overridden by user */
 817                         rx_pause_en = priv->pause_rx;
 818                         tx_pause_en = priv->pause_tx;
 819                 } else {
 820                         rx_pause_en = 0;
 821                         tx_pause_en = 0;
 822                 }
 823
 824                 bcm_enet_set_flow(priv, rx_pause_en, tx_pause_en);
 825                 status_changed = 1;
 826                 priv->old_pause = phydev->pause;
 827         }
 828
 829         if (status_changed) {
 830                 pr_info("%s: link %s", dev->name, phydev->link ?
 831                         "UP" : "DOWN");
 832                 if (phydev->link)
 833                         pr_cont(" - %d/%s - flow control %s", phydev->speed,
 834                                DUPLEX_FULL == phydev->duplex ? "full" : "half",
 835                                phydev->pause == 1 ? "rx&tx" : "off");
 836
 837                 pr_cont("\n");
 838         }
 839 }
 840
 841 /*
 842  * link changed callback (if phylib is not used)
 843  */
 844 static void bcm_enet_adjust_link(struct net_device *dev)
 845 {
 846         struct bcm_enet_priv *priv;
 847
 848         priv = netdev_priv(dev);
 849         bcm_enet_set_duplex(priv, priv->force_duplex_full);
 850         bcm_enet_set_flow(priv, priv->pause_rx, priv->pause_tx);
 851         netif_carrier_on(dev);
 852
 853         pr_info("%s: link forced UP - %d/%s - flow control %s/%s\n",
 854                 dev->name,
 855                 priv->force_speed_100 ? 100 : 10,
 856                 priv->force_duplex_full ? "full" : "half",
 857                 priv->pause_rx ? "rx" : "off",
 858                 priv->pause_tx ? "tx" : "off");
 859 }
 860
 861 /*
 862  * open callback, allocate dma rings & buffers and start rx operation
 863  */
 864 static int bcm_enet_open(struct net_device *dev)
 865 {
 866         struct bcm_enet_priv *priv;
 867         struct sockaddr addr;
 868         struct device *kdev;
 869         struct phy_device *phydev;
 870         int i, ret;
 871         unsigned int size;
 872         char phy_id[MII_BUS_ID_SIZE + 3];
 873         void *p;
 874         u32 val;
 875
 876         priv = netdev_priv(dev);
 877         kdev = &priv->pdev->dev;
 878
 879         if (priv->has_phy) {
 880                 /* connect to PHY */
 881                 snprintf(phy_id, sizeof(phy_id), PHY_ID_FMT,
 882                          priv->mii_bus->id, priv->phy_id);
 883
 884                 phydev = phy_connect(dev, phy_id, bcm_enet_adjust_phy_link,
 885                                      PHY_INTERFACE_MODE_MII);
 886
 887                 if (IS_ERR(phydev)) {
 888                         dev_err(kdev, "could not attach to PHY\n");
 889                         return PTR_ERR(phydev);
 890                 }
 891
 892                 /* mask with MAC supported features */
 893                 phydev->supported &= (SUPPORTED_10baseT_Half |
 894                                       SUPPORTED_10baseT_Full |
 895                                       SUPPORTED_100baseT_Half |
 896                                       SUPPORTED_100baseT_Full |
 897                                       SUPPORTED_Autoneg |
 898                                       SUPPORTED_Pause |
 899                                       SUPPORTED_MII);
 900                 phydev->advertising = phydev->supported;
 901
 902                 if (priv->pause_auto && priv->pause_rx && priv->pause_tx)
 903                         phydev->advertising |= SUPPORTED_Pause;
 904                 else
 905                         phydev->advertising &= ~SUPPORTED_Pause;
 906
 907                 phy_attached_info(phydev);
 908
 909                 priv->old_link = 0;
 910                 priv->old_duplex = -1;
 911                 priv->old_pause = -1;
 912         } else {
 913                 phydev = NULL;
 914         }
 915
 916         /* mask all interrupts and request them */
 917         enet_writel(priv, 0, ENET_IRMASK_REG);
 918         enet_dmac_writel(priv, 0, ENETDMAC_IRMASK, priv->rx_chan);
 919         enet_dmac_writel(priv, 0, ENETDMAC_IRMASK, priv->tx_chan);
 920
 921         ret = request_irq(dev->irq, bcm_enet_isr_mac, 0, dev->name, dev);
 922         if (ret)
 923                 goto out_phy_disconnect;
 924
 925         ret = request_irq(priv->irq_rx, bcm_enet_isr_dma, 0,
 926                           dev->name, dev);
 927         if (ret)
 928                 goto out_freeirq;
 929
 930         ret = request_irq(priv->irq_tx, bcm_enet_isr_dma,
 931                           0, dev->name, dev);
 932         if (ret)
 933                 goto out_freeirq_rx;
 934
 935         /* initialize perfect match registers */
 936         for (i = 0; i < 4; i++) {
 937                 enet_writel(priv, 0, ENET_PML_REG(i));
 938                 enet_writel(priv, 0, ENET_PMH_REG(i));
 939         }
 940
 941         /* write device mac address */
 942         memcpy(addr.sa_data, dev->dev_addr, ETH_ALEN);
 943         bcm_enet_set_mac_address(dev, &addr);
 944
 945         /* allocate rx dma ring */
 946         size = priv->rx_ring_size * sizeof(struct bcm_enet_desc);
 947         p = dma_zalloc_coherent(kdev, size, &priv->rx_desc_dma, GFP_KERNEL);
 948         if (!p) {
 949                 ret = -ENOMEM;
 950                 goto out_freeirq_tx;
 951         }
 952
 953         priv->rx_desc_alloc_size = size;
 954         priv->rx_desc_cpu = p;
 955
 956         /* allocate tx dma ring */
 957         size = priv->tx_ring_size * sizeof(struct bcm_enet_desc);
 958         p = dma_zalloc_coherent(kdev, size, &priv->tx_desc_dma, GFP_KERNEL);
 959         if (!p) {
 960                 ret = -ENOMEM;
 961                 goto out_free_rx_ring;
 962         }
 963
 964         priv->tx_desc_alloc_size = size;
 965         priv->tx_desc_cpu = p;
 966
 967         priv->tx_skb = kcalloc(priv->tx_ring_size, sizeof(struct sk_buff *),
 968                                GFP_KERNEL);
 969         if (!priv->tx_skb) {
 970                 ret = -ENOMEM;
 971                 goto out_free_tx_ring;
 972         }
 973
 974         priv->tx_desc_count = priv->tx_ring_size;
 975         priv->tx_dirty_desc = 0;
 976         priv->tx_curr_desc = 0;
 977         spin_lock_init(&priv->tx_lock);
 978
 979         /* init & fill rx ring with skbs */
 980         priv->rx_skb = kcalloc(priv->rx_ring_size, sizeof(struct sk_buff *),
 981                                GFP_KERNEL);
 982         if (!priv->rx_skb) {
 983                 ret = -ENOMEM;
 984                 goto out_free_tx_skb;
 985         }
 986
 987         priv->rx_desc_count = 0;
 988         priv->rx_dirty_desc = 0;
 989         priv->rx_curr_desc = 0;
 990
 991         /* initialize flow control buffer allocation */
 992         if (priv->dma_has_sram)
 993                 enet_dma_writel(priv, ENETDMA_BUFALLOC_FORCE_MASK | 0,
 994                                 ENETDMA_BUFALLOC_REG(priv->rx_chan));
 995         else
 996                 enet_dmac_writel(priv, ENETDMA_BUFALLOC_FORCE_MASK | 0,
 997                                 ENETDMAC_BUFALLOC, priv->rx_chan);
 998
 999         if (bcm_enet_refill_rx(dev)) {
1000                 dev_err(kdev, "cannot allocate rx skb queue\n");
1001                 ret = -ENOMEM;
1002                 goto out;
1003         }
1004
1005         /* write rx & tx ring addresses */
1006         if (priv->dma_has_sram) {
1007                 enet_dmas_writel(priv, priv->rx_desc_dma,
1008                                  ENETDMAS_RSTART_REG, priv->rx_chan);
1009                 enet_dmas_writel(priv, priv->tx_desc_dma,
1010                          ENETDMAS_RSTART_REG, priv->tx_chan);
1011         } else {
1012                 enet_dmac_writel(priv, priv->rx_desc_dma,
1013                                 ENETDMAC_RSTART, priv->rx_chan);
1014                 enet_dmac_writel(priv, priv->tx_desc_dma,
1015                                 ENETDMAC_RSTART, priv->tx_chan);
1016         }
1017
1018         /* clear remaining state ram for rx & tx channel */
1019         if (priv->dma_has_sram) {
1020                 enet_dmas_writel(priv, 0, ENETDMAS_SRAM2_REG, priv->rx_chan);
1021                 enet_dmas_writel(priv, 0, ENETDMAS_SRAM2_REG, priv->tx_chan);
1022                 enet_dmas_writel(priv, 0, ENETDMAS_SRAM3_REG, priv->rx_chan);
1023                 enet_dmas_writel(priv, 0, ENETDMAS_SRAM3_REG, priv->tx_chan);
1024                 enet_dmas_writel(priv, 0, ENETDMAS_SRAM4_REG, priv->rx_chan);
1025                 enet_dmas_writel(priv, 0, ENETDMAS_SRAM4_REG, priv->tx_chan);
1026         } else {
1027                 enet_dmac_writel(priv, 0, ENETDMAC_FC, priv->rx_chan);
1028                 enet_dmac_writel(priv, 0, ENETDMAC_FC, priv->tx_chan);
1029         }
1030
1031         /* set max rx/tx length */
1032         enet_writel(priv, priv->hw_mtu, ENET_RXMAXLEN_REG);
1033         enet_writel(priv, priv->hw_mtu, ENET_TXMAXLEN_REG);
1034
1035         /* set dma maximum burst len */
1036         enet_dmac_writel(priv, priv->dma_maxburst,
1037                          ENETDMAC_MAXBURST, priv->rx_chan);
1038         enet_dmac_writel(priv, priv->dma_maxburst,
1039                          ENETDMAC_MAXBURST, priv->tx_chan);
1040
1041         /* set correct transmit fifo watermark */
1042         enet_writel(priv, BCMENET_TX_FIFO_TRESH, ENET_TXWMARK_REG);
1043
1044         /* set flow control low/high threshold to 1/3 / 2/3 */
1045         if (priv->dma_has_sram) {
1046                 val = priv->rx_ring_size / 3;
1047                 enet_dma_writel(priv, val, ENETDMA_FLOWCL_REG(priv->rx_chan));
1048                 val = (priv->rx_ring_size * 2) / 3;
1049                 enet_dma_writel(priv, val, ENETDMA_FLOWCH_REG(priv->rx_chan));
1050         } else {
1051                 enet_dmac_writel(priv, 5, ENETDMAC_FC, priv->rx_chan);
1052                 enet_dmac_writel(priv, priv->rx_ring_size, ENETDMAC_LEN, priv->rx_chan);
1053                 enet_dmac_writel(priv, priv->tx_ring_size, ENETDMAC_LEN, priv->tx_chan);
1054         }
1055
1056         /* all set, enable mac and interrupts, start dma engine and
1057          * kick rx dma channel */
1058         wmb();
1059         val = enet_readl(priv, ENET_CTL_REG);
1060         val |= ENET_CTL_ENABLE_MASK;
1061         enet_writel(priv, val, ENET_CTL_REG);
1062         if (priv->dma_has_sram)
1063                 enet_dma_writel(priv, ENETDMA_CFG_EN_MASK, ENETDMA_CFG_REG);
1064         enet_dmac_writel(priv, priv->dma_chan_en_mask,
1065                          ENETDMAC_CHANCFG, priv->rx_chan);
1066
1067         /* watch "mib counters about to overflow" interrupt */
1068         enet_writel(priv, ENET_IR_MIB, ENET_IR_REG);
1069         enet_writel(priv, ENET_IR_MIB, ENET_IRMASK_REG);
1070
1071         /* watch "packet transferred" interrupt in rx and tx */
1072         enet_dmac_writel(priv, priv->dma_chan_int_mask,
1073                          ENETDMAC_IR, priv->rx_chan);
1074         enet_dmac_writel(priv, priv->dma_chan_int_mask,
1075                          ENETDMAC_IR, priv->tx_chan);
1076
1077         /* make sure we enable napi before rx interrupt  */
1078         napi_enable(&priv->napi);
1079
1080         enet_dmac_writel(priv, priv->dma_chan_int_mask,
1081                          ENETDMAC_IRMASK, priv->rx_chan);
1082         enet_dmac_writel(priv, priv->dma_chan_int_mask,
1083                          ENETDMAC_IRMASK, priv->tx_chan);
1084
1085         if (phydev)
1086                 phy_start(phydev);
1087         else
1088                 bcm_enet_adjust_link(dev);
1089
1090         netif_start_queue(dev);
1091         return 0;
1092
1093 out:
1094         for (i = 0; i < priv->rx_ring_size; i++) {
1095                 struct bcm_enet_desc *desc;
1096
1097                 if (!priv->rx_skb[i])
1098                         continue;
1099
1100                 desc = &priv->rx_desc_cpu[i];
1101                 dma_unmap_single(kdev, desc->address, priv->rx_skb_size,
1102                                  DMA_FROM_DEVICE);
1103                 kfree_skb(priv->rx_skb[i]);
1104         }
1105         kfree(priv->rx_skb);
1106
1107 out_free_tx_skb:
1108         kfree(priv->tx_skb);
1109
1110 out_free_tx_ring:
1111         dma_free_coherent(kdev, priv->tx_desc_alloc_size,
1112                           priv->tx_desc_cpu, priv->tx_desc_dma);
1113
1114 out_free_rx_ring:
1115         dma_free_coherent(kdev, priv->rx_desc_alloc_size,
1116                           priv->rx_desc_cpu, priv->rx_desc_dma);
1117
1118 out_freeirq_tx:
1119         free_irq(priv->irq_tx, dev);
1120
1121 out_freeirq_rx:
1122         free_irq(priv->irq_rx, dev);
1123
1124 out_freeirq:
1125         free_irq(dev->irq, dev);
1126
1127 out_phy_disconnect:
1128         if (phydev)
1129                 phy_disconnect(phydev);
1130
1131         return ret;
1132 }
1133
1134 /*
1135  * disable mac
1136  */
1137 static void bcm_enet_disable_mac(struct bcm_enet_priv *priv)
1138 {
1139         int limit;
1140         u32 val;
1141
1142         val = enet_readl(priv, ENET_CTL_REG);
1143         val |= ENET_CTL_DISABLE_MASK;
1144         enet_writel(priv, val, ENET_CTL_REG);
1145
1146         limit = 1000;
1147         do {
1148                 u32 val;
1149
1150                 val = enet_readl(priv, ENET_CTL_REG);
1151                 if (!(val & ENET_CTL_DISABLE_MASK))
1152                         break;
1153                 udelay(1);
1154         } while (limit--);
1155 }
1156
1157 /*
1158  * disable dma in given channel
1159  */
1160 static void bcm_enet_disable_dma(struct bcm_enet_priv *priv, int chan)
1161 {
1162         int limit;
1163
1164         enet_dmac_writel(priv, 0, ENETDMAC_CHANCFG, chan);
1165
1166         limit = 1000;
1167         do {
1168                 u32 val;
1169
1170                 val = enet_dmac_readl(priv, ENETDMAC_CHANCFG, chan);
1171                 if (!(val & ENETDMAC_CHANCFG_EN_MASK))
1172                         break;
1173                 udelay(1);
1174         } while (limit--);
1175 }
1176
1177 /*
1178  * stop callback
1179  */
1180 static int bcm_enet_stop(struct net_device *dev)
1181 {
1182         struct bcm_enet_priv *priv;
1183         struct device *kdev;
1184         int i;
1185
1186         priv = netdev_priv(dev);
1187         kdev = &priv->pdev->dev;
1188
1189         netif_stop_queue(dev);
1190         napi_disable(&priv->napi);
1191         if (priv->has_phy)
1192                 phy_stop(dev->phydev);
1193         del_timer_sync(&priv->rx_timeout);
1194
1195         /* mask all interrupts */
1196         enet_writel(priv, 0, ENET_IRMASK_REG);
1197         enet_dmac_writel(priv, 0, ENETDMAC_IRMASK, priv->rx_chan);
1198         enet_dmac_writel(priv, 0, ENETDMAC_IRMASK, priv->tx_chan);
1199
1200         /* make sure no mib update is scheduled */
1201         cancel_work_sync(&priv->mib_update_task);
1202
1203         /* disable dma & mac */
1204         bcm_enet_disable_dma(priv, priv->tx_chan);
1205         bcm_enet_disable_dma(priv, priv->rx_chan);
1206         bcm_enet_disable_mac(priv);
1207
1208         /* force reclaim of all tx buffers */
1209         bcm_enet_tx_reclaim(dev, 1);
1210
1211         /* free the rx skb ring */
1212         for (i = 0; i < priv->rx_ring_size; i++) {
1213                 struct bcm_enet_desc *desc;
1214
1215                 if (!priv->rx_skb[i])
1216                         continue;
1217
1218                 desc = &priv->rx_desc_cpu[i];
1219                 dma_unmap_single(kdev, desc->address, priv->rx_skb_size,
1220                                  DMA_FROM_DEVICE);
1221                 kfree_skb(priv->rx_skb[i]);
1222         }
1223
1224         /* free remaining allocated memory */
1225         kfree(priv->rx_skb);
1226         kfree(priv->tx_skb);
1227         dma_free_coherent(kdev, priv->rx_desc_alloc_size,
1228                           priv->rx_desc_cpu, priv->rx_desc_dma);
1229         dma_free_coherent(kdev, priv->tx_desc_alloc_size,
1230                           priv->tx_desc_cpu, priv->tx_desc_dma);
1231         free_irq(priv->irq_tx, dev);
1232         free_irq(priv->irq_rx, dev);
1233         free_irq(dev->irq, dev);
1234
1235         /* release phy */
1236         if (priv->has_phy)
1237                 phy_disconnect(dev->phydev);
1238
1239         return 0;
1240 }
1241
1242 /*
1243  * ethtool callbacks
1244  */
1245 struct bcm_enet_stats {
1246         char stat_string[ETH_GSTRING_LEN];
1247         int sizeof_stat;
1248         int stat_offset;
1249         int mib_reg;
1250 };
1251
1252 #define GEN_STAT(m) sizeof(((struct bcm_enet_priv *)0)->m),             \
1253                      offsetof(struct bcm_enet_priv, m)
1254 #define DEV_STAT(m) sizeof(((struct net_device_stats *)0)->m),          \
1255                      offsetof(struct net_device_stats, m)
1256
1257 static const struct bcm_enet_stats bcm_enet_gstrings_stats[] = {
1258         { "rx_packets", DEV_STAT(rx_packets), -1 },
1259         { "tx_packets", DEV_STAT(tx_packets), -1 },
1260         { "rx_bytes", DEV_STAT(rx_bytes), -1 },
1261         { "tx_bytes", DEV_STAT(tx_bytes), -1 },
1262         { "rx_errors", DEV_STAT(rx_errors), -1 },
1263         { "tx_errors", DEV_STAT(tx_errors), -1 },
1264         { "rx_dropped", DEV_STAT(rx_dropped), -1 },
1265         { "tx_dropped", DEV_STAT(tx_dropped), -1 },
1266
1267         { "rx_good_octets", GEN_STAT(mib.rx_gd_octets), ETH_MIB_RX_GD_OCTETS},
1268         { "rx_good_pkts", GEN_STAT(mib.rx_gd_pkts), ETH_MIB_RX_GD_PKTS },
1269         { "rx_broadcast", GEN_STAT(mib.rx_brdcast), ETH_MIB_RX_BRDCAST },
1270         { "rx_multicast", GEN_STAT(mib.rx_mult), ETH_MIB_RX_MULT },
1271         { "rx_64_octets", GEN_STAT(mib.rx_64), ETH_MIB_RX_64 },
1272         { "rx_65_127_oct", GEN_STAT(mib.rx_65_127), ETH_MIB_RX_65_127 },
1273         { "rx_128_255_oct", GEN_STAT(mib.rx_128_255), ETH_MIB_RX_128_255 },
1274         { "rx_256_511_oct", GEN_STAT(mib.rx_256_511), ETH_MIB_RX_256_511 },
1275         { "rx_512_1023_oct", GEN_STAT(mib.rx_512_1023), ETH_MIB_RX_512_1023 },
1276         { "rx_1024_max_oct", GEN_STAT(mib.rx_1024_max), ETH_MIB_RX_1024_MAX },
1277         { "rx_jabber", GEN_STAT(mib.rx_jab), ETH_MIB_RX_JAB },
1278         { "rx_oversize", GEN_STAT(mib.rx_ovr), ETH_MIB_RX_OVR },
1279         { "rx_fragment", GEN_STAT(mib.rx_frag), ETH_MIB_RX_FRAG },
1280         { "rx_dropped", GEN_STAT(mib.rx_drop), ETH_MIB_RX_DROP },
1281         { "rx_crc_align", GEN_STAT(mib.rx_crc_align), ETH_MIB_RX_CRC_ALIGN },
1282         { "rx_undersize", GEN_STAT(mib.rx_und), ETH_MIB_RX_UND },
1283         { "rx_crc", GEN_STAT(mib.rx_crc), ETH_MIB_RX_CRC },
1284         { "rx_align", GEN_STAT(mib.rx_align), ETH_MIB_RX_ALIGN },
1285         { "rx_symbol_error", GEN_STAT(mib.rx_sym), ETH_MIB_RX_SYM },
1286         { "rx_pause", GEN_STAT(mib.rx_pause), ETH_MIB_RX_PAUSE },
1287         { "rx_control", GEN_STAT(mib.rx_cntrl), ETH_MIB_RX_CNTRL },
1288
1289         { "tx_good_octets", GEN_STAT(mib.tx_gd_octets), ETH_MIB_TX_GD_OCTETS },
1290         { "tx_good_pkts", GEN_STAT(mib.tx_gd_pkts), ETH_MIB_TX_GD_PKTS },
1291         { "tx_broadcast", GEN_STAT(mib.tx_brdcast), ETH_MIB_TX_BRDCAST },
1292         { "tx_multicast", GEN_STAT(mib.tx_mult), ETH_MIB_TX_MULT },
1293         { "tx_64_oct", GEN_STAT(mib.tx_64), ETH_MIB_TX_64 },
1294         { "tx_65_127_oct", GEN_STAT(mib.tx_65_127), ETH_MIB_TX_65_127 },
1295         { "tx_128_255_oct", GEN_STAT(mib.tx_128_255), ETH_MIB_TX_128_255 },
1296         { "tx_256_511_oct", GEN_STAT(mib.tx_256_511), ETH_MIB_TX_256_511 },
1297         { "tx_512_1023_oct", GEN_STAT(mib.tx_512_1023), ETH_MIB_TX_512_1023},
1298         { "tx_1024_max_oct", GEN_STAT(mib.tx_1024_max), ETH_MIB_TX_1024_MAX },
1299         { "tx_jabber", GEN_STAT(mib.tx_jab), ETH_MIB_TX_JAB },
1300         { "tx_oversize", GEN_STAT(mib.tx_ovr), ETH_MIB_TX_OVR },
1301         { "tx_fragment", GEN_STAT(mib.tx_frag), ETH_MIB_TX_FRAG },
1302         { "tx_underrun", GEN_STAT(mib.tx_underrun), ETH_MIB_TX_UNDERRUN },
1303         { "tx_collisions", GEN_STAT(mib.tx_col), ETH_MIB_TX_COL },
1304         { "tx_single_collision", GEN_STAT(mib.tx_1_col), ETH_MIB_TX_1_COL },
1305         { "tx_multiple_collision", GEN_STAT(mib.tx_m_col), ETH_MIB_TX_M_COL },
1306         { "tx_excess_collision", GEN_STAT(mib.tx_ex_col), ETH_MIB_TX_EX_COL },
1307         { "tx_late_collision", GEN_STAT(mib.tx_late), ETH_MIB_TX_LATE },
1308         { "tx_deferred", GEN_STAT(mib.tx_def), ETH_MIB_TX_DEF },
1309         { "tx_carrier_sense", GEN_STAT(mib.tx_crs), ETH_MIB_TX_CRS },
1310         { "tx_pause", GEN_STAT(mib.tx_pause), ETH_MIB_TX_PAUSE },
1311
1312 };
1313
1314 #define BCM_ENET_STATS_LEN      ARRAY_SIZE(bcm_enet_gstrings_stats)
1315
1316 static const u32 unused_mib_regs[] = {
1317         ETH_MIB_TX_ALL_OCTETS,
1318         ETH_MIB_TX_ALL_PKTS,
1319         ETH_MIB_RX_ALL_OCTETS,
1320         ETH_MIB_RX_ALL_PKTS,
1321 };
1322
1323
1324 static void bcm_enet_get_drvinfo(struct net_device *netdev,
1325                                  struct ethtool_drvinfo *drvinfo)
1326 {
1327         strlcpy(drvinfo->driver, bcm_enet_driver_name, sizeof(drvinfo->driver));
1328         strlcpy(drvinfo->version, bcm_enet_driver_version,
1329                 sizeof(drvinfo->version));
1330         strlcpy(drvinfo->fw_version, "N/A", sizeof(drvinfo->fw_version));
1331         strlcpy(drvinfo->bus_info, "bcm63xx", sizeof(drvinfo->bus_info));
1332 }
1333
1334 static int bcm_enet_get_sset_count(struct net_device *netdev,
1335                                         int string_set)
1336 {
1337         switch (string_set) {
1338         case ETH_SS_STATS:
1339                 return BCM_ENET_STATS_LEN;
1340         default:
1341                 return -EINVAL;
1342         }
1343 }
1344
1345 static void bcm_enet_get_strings(struct net_device *netdev,
1346                                  u32 stringset, u8 *data)
1347 {
1348         int i;
1349
1350         switch (stringset) {
1351         case ETH_SS_STATS:
1352                 for (i = 0; i < BCM_ENET_STATS_LEN; i++) {
1353                         memcpy(data + i * ETH_GSTRING_LEN,
1354                                bcm_enet_gstrings_stats[i].stat_string,
1355                                ETH_GSTRING_LEN);
1356                 }
1357                 break;
1358         }
1359 }
1360
1361 static void update_mib_counters(struct bcm_enet_priv *priv)
1362 {
1363         int i;
1364
1365         for (i = 0; i < BCM_ENET_STATS_LEN; i++) {
1366                 const struct bcm_enet_stats *s;
1367                 u32 val;
1368                 char *p;
1369
1370                 s = &bcm_enet_gstrings_stats[i];
1371                 if (s->mib_reg == -1)
1372                         continue;
1373
1374                 val = enet_readl(priv, ENET_MIB_REG(s->mib_reg));
1375                 p = (char *)priv + s->stat_offset;
1376
1377                 if (s->sizeof_stat == sizeof(u64))
1378                         *(u64 *)p += val;
1379                 else
1380                         *(u32 *)p += val;
1381         }
1382
1383         /* also empty unused mib counters to make sure mib counter
1384          * overflow interrupt is cleared */
1385         for (i = 0; i < ARRAY_SIZE(unused_mib_regs); i++)
1386                 (void)enet_readl(priv, ENET_MIB_REG(unused_mib_regs[i]));
1387 }
1388
1389 static void bcm_enet_update_mib_counters_defer(struct work_struct *t)
1390 {
1391         struct bcm_enet_priv *priv;
1392
1393         priv = container_of(t, struct bcm_enet_priv, mib_update_task);
1394         mutex_lock(&priv->mib_update_lock);
1395         update_mib_counters(priv);
1396         mutex_unlock(&priv->mib_update_lock);
1397
1398         /* reenable mib interrupt */
1399         if (netif_running(priv->net_dev))
1400                 enet_writel(priv, ENET_IR_MIB, ENET_IRMASK_REG);
1401 }
1402
1403 static void bcm_enet_get_ethtool_stats(struct net_device *netdev,
1404                                        struct ethtool_stats *stats,
1405                                        u64 *data)
1406 {
1407         struct bcm_enet_priv *priv;
1408         int i;
1409
1410         priv = netdev_priv(netdev);
1411
1412         mutex_lock(&priv->mib_update_lock);
1413         update_mib_counters(priv);
1414
1415         for (i = 0; i < BCM_ENET_STATS_LEN; i++) {
1416                 const struct bcm_enet_stats *s;
1417                 char *p;
1418
1419                 s = &bcm_enet_gstrings_stats[i];
1420                 if (s->mib_reg == -1)
1421                         p = (char *)&netdev->stats;
1422                 else
1423                         p = (char *)priv;
1424                 p += s->stat_offset;
1425                 data[i] = (s->sizeof_stat == sizeof(u64)) ?
1426                         *(u64 *)p : *(u32 *)p;
1427         }
1428         mutex_unlock(&priv->mib_update_lock);
1429 }
1430
1431 static int bcm_enet_nway_reset(struct net_device *dev)
1432 {
1433         struct bcm_enet_priv *priv;
1434
1435         priv = netdev_priv(dev);
1436         if (priv->has_phy)
1437                 return phy_ethtool_nway_reset(dev);
1438
1439         return -EOPNOTSUPP;
1440 }
1441
1442 static int bcm_enet_get_link_ksettings(struct net_device *dev,
1443                                        struct ethtool_link_ksettings *cmd)
1444 {
1445         struct bcm_enet_priv *priv;
1446         u32 supported, advertising;
1447
1448         priv = netdev_priv(dev);
1449
1450         if (priv->has_phy) {
1451                 if (!dev->phydev)
1452                         return -ENODEV;
1453
1454                 phy_ethtool_ksettings_get(dev->phydev, cmd);
1455
1456                 return 0;
1457         } else {
1458                 cmd->base.autoneg = 0;
1459                 cmd->base.speed = (priv->force_speed_100) ?
1460                         SPEED_100 : SPEED_10;
1461                 cmd->base.duplex = (priv->force_duplex_full) ?
1462                         DUPLEX_FULL : DUPLEX_HALF;
1463                 supported = ADVERTISED_10baseT_Half |
1464                         ADVERTISED_10baseT_Full |
1465                         ADVERTISED_100baseT_Half |
1466                         ADVERTISED_100baseT_Full;
1467                 advertising = 0;
1468                 ethtool_convert_legacy_u32_to_link_mode(
1469                         cmd->link_modes.supported, supported);
1470                 ethtool_convert_legacy_u32_to_link_mode(
1471                         cmd->link_modes.advertising, advertising);
1472                 cmd->base.port = PORT_MII;
1473         }
1474         return 0;
1475 }
1476
1477 static int bcm_enet_set_link_ksettings(struct net_device *dev,
1478                                        const struct ethtool_link_ksettings *cmd)
1479 {
1480         struct bcm_enet_priv *priv;
1481
1482         priv = netdev_priv(dev);
1483         if (priv->has_phy) {
1484                 if (!dev->phydev)
1485                         return -ENODEV;
1486                 return phy_ethtool_ksettings_set(dev->phydev, cmd);
1487         } else {
1488
1489                 if (cmd->base.autoneg ||
1490                     (cmd->base.speed != SPEED_100 &&
1491                      cmd->base.speed != SPEED_10) ||
1492                     cmd->base.port != PORT_MII)
1493                         return -EINVAL;
1494
1495                 priv->force_speed_100 =
1496                         (cmd->base.speed == SPEED_100) ? 1 : 0;
1497                 priv->force_duplex_full =
1498                         (cmd->base.duplex == DUPLEX_FULL) ? 1 : 0;
1499
1500                 if (netif_running(dev))
1501                         bcm_enet_adjust_link(dev);
1502                 return 0;
1503         }
1504 }
1505
1506 static void bcm_enet_get_ringparam(struct net_device *dev,
1507                                    struct ethtool_ringparam *ering)
1508 {
1509         struct bcm_enet_priv *priv;
1510
1511         priv = netdev_priv(dev);
1512
1513         /* rx/tx ring is actually only limited by memory */
1514         ering->rx_max_pending = 8192;
1515         ering->tx_max_pending = 8192;
1516         ering->rx_pending = priv->rx_ring_size;
1517         ering->tx_pending = priv->tx_ring_size;
1518 }
1519
1520 static int bcm_enet_set_ringparam(struct net_device *dev,
1521                                   struct ethtool_ringparam *ering)
1522 {
1523         struct bcm_enet_priv *priv;
1524         int was_running;
1525
1526         priv = netdev_priv(dev);
1527
1528         was_running = 0;
1529         if (netif_running(dev)) {
1530                 bcm_enet_stop(dev);
1531                 was_running = 1;
1532         }
1533
1534         priv->rx_ring_size = ering->rx_pending;
1535         priv->tx_ring_size = ering->tx_pending;
1536
1537         if (was_running) {
1538                 int err;
1539
1540                 err = bcm_enet_open(dev);
1541                 if (err)
1542                         dev_close(dev);
1543                 else
1544                         bcm_enet_set_multicast_list(dev);
1545         }
1546         return 0;
1547 }
1548
1549 static void bcm_enet_get_pauseparam(struct net_device *dev,
1550                                     struct ethtool_pauseparam *ecmd)
1551 {
1552         struct bcm_enet_priv *priv;
1553
1554         priv = netdev_priv(dev);
1555         ecmd->autoneg = priv->pause_auto;
1556         ecmd->rx_pause = priv->pause_rx;
1557         ecmd->tx_pause = priv->pause_tx;
1558 }
1559
1560 static int bcm_enet_set_pauseparam(struct net_device *dev,
1561                                    struct ethtool_pauseparam *ecmd)
1562 {
1563         struct bcm_enet_priv *priv;
1564
1565         priv = netdev_priv(dev);
1566
1567         if (priv->has_phy) {
1568                 if (ecmd->autoneg && (ecmd->rx_pause != ecmd->tx_pause)) {
1569                         /* asymetric pause mode not supported,
1570                          * actually possible but integrated PHY has RO
1571                          * asym_pause bit */
1572                         return -EINVAL;
1573                 }
1574         } else {
1575                 /* no pause autoneg on direct mii connection */
1576                 if (ecmd->autoneg)
1577                         return -EINVAL;
1578         }
1579
1580         priv->pause_auto = ecmd->autoneg;
1581         priv->pause_rx = ecmd->rx_pause;
1582         priv->pause_tx = ecmd->tx_pause;
1583
1584         return 0;
1585 }
1586
1587 static const struct ethtool_ops bcm_enet_ethtool_ops = {
1588         .get_strings            = bcm_enet_get_strings,
1589         .get_sset_count         = bcm_enet_get_sset_count,
1590         .get_ethtool_stats      = bcm_enet_get_ethtool_stats,
1591         .nway_reset             = bcm_enet_nway_reset,
1592         .get_drvinfo            = bcm_enet_get_drvinfo,
1593         .get_link               = ethtool_op_get_link,
1594         .get_ringparam          = bcm_enet_get_ringparam,
1595         .set_ringparam          = bcm_enet_set_ringparam,
1596         .get_pauseparam         = bcm_enet_get_pauseparam,
1597         .set_pauseparam         = bcm_enet_set_pauseparam,
1598         .get_link_ksettings     = bcm_enet_get_link_ksettings,
1599         .set_link_ksettings     = bcm_enet_set_link_ksettings,
1600 };
1601
1602 static int bcm_enet_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
1603 {
1604         struct bcm_enet_priv *priv;
1605
1606         priv = netdev_priv(dev);
1607         if (priv->has_phy) {
1608                 if (!dev->phydev)
1609                         return -ENODEV;
1610                 return phy_mii_ioctl(dev->phydev, rq, cmd);
1611         } else {
1612                 struct mii_if_info mii;
1613
1614                 mii.dev = dev;
1615                 mii.mdio_read = bcm_enet_mdio_read_mii;
1616                 mii.mdio_write = bcm_enet_mdio_write_mii;
1617                 mii.phy_id = 0;
1618                 mii.phy_id_mask = 0x3f;
1619                 mii.reg_num_mask = 0x1f;
1620                 return generic_mii_ioctl(&mii, if_mii(rq), cmd, NULL);
1621         }
1622 }
1623
1624 /*
1625  * adjust mtu, can't be called while device is running
1626  */
1627 static int bcm_enet_change_mtu(struct net_device *dev, int new_mtu)
1628 {
1629         struct bcm_enet_priv *priv = netdev_priv(dev);
1630         int actual_mtu = new_mtu;
1631
1632         if (netif_running(dev))
1633                 return -EBUSY;
1634
1635         /* add ethernet header + vlan tag size */
1636         actual_mtu += VLAN_ETH_HLEN;
1637
1638         /*
1639          * setup maximum size before we get overflow mark in
1640          * descriptor, note that this will not prevent reception of
1641          * big frames, they will be split into multiple buffers
1642          * anyway
1643          */
1644         priv->hw_mtu = actual_mtu;
1645
1646         /*
1647          * align rx buffer size to dma burst len, account FCS since
1648          * it's appended
1649          */
1650         priv->rx_skb_size = ALIGN(actual_mtu + ETH_FCS_LEN,
1651                                   priv->dma_maxburst * 4);
1652
1653         dev->mtu = new_mtu;
1654         return 0;
1655 }
1656
1657 /*
1658  * preinit hardware to allow mii operation while device is down
1659  */
1660 static void bcm_enet_hw_preinit(struct bcm_enet_priv *priv)
1661 {
1662         u32 val;
1663         int limit;
1664
1665         /* make sure mac is disabled */
1666         bcm_enet_disable_mac(priv);
1667
1668         /* soft reset mac */
1669         val = ENET_CTL_SRESET_MASK;
1670         enet_writel(priv, val, ENET_CTL_REG);
1671         wmb();
1672
1673         limit = 1000;
1674         do {
1675                 val = enet_readl(priv, ENET_CTL_REG);
1676                 if (!(val & ENET_CTL_SRESET_MASK))
1677                         break;
1678                 udelay(1);
1679         } while (limit--);
1680
1681         /* select correct mii interface */
1682         val = enet_readl(priv, ENET_CTL_REG);
1683         if (priv->use_external_mii)
1684                 val |= ENET_CTL_EPHYSEL_MASK;
1685         else
1686                 val &= ~ENET_CTL_EPHYSEL_MASK;
1687         enet_writel(priv, val, ENET_CTL_REG);
1688
1689         /* turn on mdc clock */
1690         enet_writel(priv, (0x1f << ENET_MIISC_MDCFREQDIV_SHIFT) |
1691                     ENET_MIISC_PREAMBLEEN_MASK, ENET_MIISC_REG);
1692
1693         /* set mib counters to self-clear when read */
1694         val = enet_readl(priv, ENET_MIBCTL_REG);
1695         val |= ENET_MIBCTL_RDCLEAR_MASK;
1696         enet_writel(priv, val, ENET_MIBCTL_REG);
1697 }
1698
1699 static const struct net_device_ops bcm_enet_ops = {
1700         .ndo_open               = bcm_enet_open,
1701         .ndo_stop               = bcm_enet_stop,
1702         .ndo_start_xmit         = bcm_enet_start_xmit,
1703         .ndo_set_mac_address    = bcm_enet_set_mac_address,
1704         .ndo_set_rx_mode        = bcm_enet_set_multicast_list,
1705         .ndo_do_ioctl           = bcm_enet_ioctl,
1706         .ndo_change_mtu         = bcm_enet_change_mtu,
1707 };
1708
1709 /*
1710  * allocate netdevice, request register memory and register device.
1711  */
1712 static int bcm_enet_probe(struct platform_device *pdev)
1713 {
1714         struct bcm_enet_priv *priv;
1715         struct net_device *dev;
1716         struct bcm63xx_enet_platform_data *pd;
1717         struct resource *res_mem, *res_irq, *res_irq_rx, *res_irq_tx;
1718         struct mii_bus *bus;
1719         int i, ret;
1720
1721         if (!bcm_enet_shared_base[0])
1722                 return -EPROBE_DEFER;
1723
1724         res_irq = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
1725         res_irq_rx = platform_get_resource(pdev, IORESOURCE_IRQ, 1);
1726         res_irq_tx = platform_get_resource(pdev, IORESOURCE_IRQ, 2);
1727         if (!res_irq || !res_irq_rx || !res_irq_tx)
1728                 return -ENODEV;
1729
1730         ret = 0;
1731         dev = alloc_etherdev(sizeof(*priv));
1732         if (!dev)
1733                 return -ENOMEM;
1734         priv = netdev_priv(dev);
1735
1736         priv->enet_is_sw = false;
1737         priv->dma_maxburst = BCMENET_DMA_MAXBURST;
1738
1739         ret = bcm_enet_change_mtu(dev, dev->mtu);
1740         if (ret)
1741                 goto out;
1742
1743         res_mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1744         priv->base = devm_ioremap_resource(&pdev->dev, res_mem);
1745         if (IS_ERR(priv->base)) {
1746                 ret = PTR_ERR(priv->base);
1747                 goto out;
1748         }
1749
1750         dev->irq = priv->irq = res_irq->start;
1751         priv->irq_rx = res_irq_rx->start;
1752         priv->irq_tx = res_irq_tx->start;
1753
1754         priv->mac_clk = devm_clk_get(&pdev->dev, "enet");
1755         if (IS_ERR(priv->mac_clk)) {
1756                 ret = PTR_ERR(priv->mac_clk);
1757                 goto out;
1758         }
1759         ret = clk_prepare_enable(priv->mac_clk);
1760         if (ret)
1761                 goto out;
1762
1763         /* initialize default and fetch platform data */
1764         priv->rx_ring_size = BCMENET_DEF_RX_DESC;
1765         priv->tx_ring_size = BCMENET_DEF_TX_DESC;
1766
1767         pd = dev_get_platdata(&pdev->dev);
1768         if (pd) {
1769                 memcpy(dev->dev_addr, pd->mac_addr, ETH_ALEN);
1770                 priv->has_phy = pd->has_phy;
1771                 priv->phy_id = pd->phy_id;
1772                 priv->has_phy_interrupt = pd->has_phy_interrupt;
1773                 priv->phy_interrupt = pd->phy_interrupt;
1774                 priv->use_external_mii = !pd->use_internal_phy;
1775                 priv->pause_auto = pd->pause_auto;
1776                 priv->pause_rx = pd->pause_rx;
1777                 priv->pause_tx = pd->pause_tx;
1778                 priv->force_duplex_full = pd->force_duplex_full;
1779                 priv->force_speed_100 = pd->force_speed_100;
1780                 priv->dma_chan_en_mask = pd->dma_chan_en_mask;
1781                 priv->dma_chan_int_mask = pd->dma_chan_int_mask;
1782                 priv->dma_chan_width = pd->dma_chan_width;
1783                 priv->dma_has_sram = pd->dma_has_sram;
1784                 priv->dma_desc_shift = pd->dma_desc_shift;
1785                 priv->rx_chan = pd->rx_chan;
1786                 priv->tx_chan = pd->tx_chan;
1787         }
1788
1789         if (priv->has_phy && !priv->use_external_mii) {
1790                 /* using internal PHY, enable clock */
1791                 priv->phy_clk = devm_clk_get(&pdev->dev, "ephy");
1792                 if (IS_ERR(priv->phy_clk)) {
1793                         ret = PTR_ERR(priv->phy_clk);
1794                         priv->phy_clk = NULL;
1795                         goto out_disable_clk_mac;
1796                 }
1797                 ret = clk_prepare_enable(priv->phy_clk);
1798                 if (ret)
1799                         goto out_disable_clk_mac;
1800         }
1801
1802         /* do minimal hardware init to be able to probe mii bus */
1803         bcm_enet_hw_preinit(priv);
1804
1805         /* MII bus registration */
1806         if (priv->has_phy) {
1807
1808                 priv->mii_bus = mdiobus_alloc();
1809                 if (!priv->mii_bus) {
1810                         ret = -ENOMEM;
1811                         goto out_uninit_hw;
1812                 }
1813
1814                 bus = priv->mii_bus;
1815                 bus->name = "bcm63xx_enet MII bus";
1816                 bus->parent = &pdev->dev;
1817                 bus->priv = priv;
1818                 bus->read = bcm_enet_mdio_read_phylib;
1819                 bus->write = bcm_enet_mdio_write_phylib;
1820                 sprintf(bus->id, "%s-%d", pdev->name, pdev->id);
1821
1822                 /* only probe bus where we think the PHY is, because
1823                  * the mdio read operation return 0 instead of 0xffff
1824                  * if a slave is not present on hw */
1825                 bus->phy_mask = ~(1 << priv->phy_id);
1826
1827                 if (priv->has_phy_interrupt)
1828                         bus->irq[priv->phy_id] = priv->phy_interrupt;
1829
1830                 ret = mdiobus_register(bus);
1831                 if (ret) {
1832                         dev_err(&pdev->dev, "unable to register mdio bus\n");
1833                         goto out_free_mdio;
1834                 }
1835         } else {
1836
1837                 /* run platform code to initialize PHY device */
1838                 if (pd && pd->mii_config &&
1839                     pd->mii_config(dev, 1, bcm_enet_mdio_read_mii,
1840                                    bcm_enet_mdio_write_mii)) {
1841                         dev_err(&pdev->dev, "unable to configure mdio bus\n");
1842                         goto out_uninit_hw;
1843                 }
1844         }
1845
1846         spin_lock_init(&priv->rx_lock);
1847
1848         /* init rx timeout (used for oom) */
1849         timer_setup(&priv->rx_timeout, bcm_enet_refill_rx_timer, 0);
1850
1851         /* init the mib update lock&work */
1852         mutex_init(&priv->mib_update_lock);
1853         INIT_WORK(&priv->mib_update_task, bcm_enet_update_mib_counters_defer);
1854
1855         /* zero mib counters */
1856         for (i = 0; i < ENET_MIB_REG_COUNT; i++)
1857                 enet_writel(priv, 0, ENET_MIB_REG(i));
1858
1859         /* register netdevice */
1860         dev->netdev_ops = &bcm_enet_ops;
1861         netif_napi_add(dev, &priv->napi, bcm_enet_poll, 16);
1862
1863         dev->ethtool_ops = &bcm_enet_ethtool_ops;
1864         /* MTU range: 46 - 2028 */
1865         dev->min_mtu = ETH_ZLEN - ETH_HLEN;
1866         dev->max_mtu = BCMENET_MAX_MTU - VLAN_ETH_HLEN;
1867         SET_NETDEV_DEV(dev, &pdev->dev);
1868
1869         ret = register_netdev(dev);
1870         if (ret)
1871                 goto out_unregister_mdio;
1872
1873         netif_carrier_off(dev);
1874         platform_set_drvdata(pdev, dev);
1875         priv->pdev = pdev;
1876         priv->net_dev = dev;
1877
1878         return 0;
1879
1880 out_unregister_mdio:
1881         if (priv->mii_bus)
1882                 mdiobus_unregister(priv->mii_bus);
1883
1884 out_free_mdio:
1885         if (priv->mii_bus)
1886                 mdiobus_free(priv->mii_bus);
1887
1888 out_uninit_hw:
1889         /* turn off mdc clock */
1890         enet_writel(priv, 0, ENET_MIISC_REG);
1891         clk_disable_unprepare(priv->phy_clk);
1892
1893 out_disable_clk_mac:
1894         clk_disable_unprepare(priv->mac_clk);
1895 out:
1896         free_netdev(dev);
1897         return ret;
1898 }
1899
1900
1901 /*
1902  * exit func, stops hardware and unregisters netdevice
1903  */
1904 static int bcm_enet_remove(struct platform_device *pdev)
1905 {
1906         struct bcm_enet_priv *priv;
1907         struct net_device *dev;
1908
1909         /* stop netdevice */
1910         dev = platform_get_drvdata(pdev);
1911         priv = netdev_priv(dev);
1912         unregister_netdev(dev);
1913
1914         /* turn off mdc clock */
1915         enet_writel(priv, 0, ENET_MIISC_REG);
1916
1917         if (priv->has_phy) {
1918                 mdiobus_unregister(priv->mii_bus);
1919                 mdiobus_free(priv->mii_bus);
1920         } else {
1921                 struct bcm63xx_enet_platform_data *pd;
1922
1923                 pd = dev_get_platdata(&pdev->dev);
1924                 if (pd && pd->mii_config)
1925                         pd->mii_config(dev, 0, bcm_enet_mdio_read_mii,
1926                                        bcm_enet_mdio_write_mii);
1927         }
1928
1929         /* disable hw block clocks */
1930         clk_disable_unprepare(priv->phy_clk);
1931         clk_disable_unprepare(priv->mac_clk);
1932
1933         free_netdev(dev);
1934         return 0;
1935 }
1936
1937 struct platform_driver bcm63xx_enet_driver = {
1938         .probe  = bcm_enet_probe,
1939         .remove = bcm_enet_remove,
1940         .driver = {
1941                 .name   = "bcm63xx_enet",
1942                 .owner  = THIS_MODULE,
1943         },
1944 };
1945
1946 /*
1947  * switch mii access callbacks
1948  */
1949 static int bcmenet_sw_mdio_read(struct bcm_enet_priv *priv,
1950                                 int ext, int phy_id, int location)
1951 {
1952         u32 reg;
1953         int ret;
1954
1955         spin_lock_bh(&priv->enetsw_mdio_lock);
1956         enetsw_writel(priv, 0, ENETSW_MDIOC_REG);
1957
1958         reg = ENETSW_MDIOC_RD_MASK |
1959                 (phy_id << ENETSW_MDIOC_PHYID_SHIFT) |
1960                 (location << ENETSW_MDIOC_REG_SHIFT);
1961
1962         if (ext)
1963                 reg |= ENETSW_MDIOC_EXT_MASK;
1964
1965         enetsw_writel(priv, reg, ENETSW_MDIOC_REG);
1966         udelay(50);
1967         ret = enetsw_readw(priv, ENETSW_MDIOD_REG);
1968         spin_unlock_bh(&priv->enetsw_mdio_lock);
1969         return ret;
1970 }
1971
1972 static void bcmenet_sw_mdio_write(struct bcm_enet_priv *priv,
1973                                  int ext, int phy_id, int location,
1974                                  uint16_t data)
1975 {
1976         u32 reg;
1977
1978         spin_lock_bh(&priv->enetsw_mdio_lock);
1979         enetsw_writel(priv, 0, ENETSW_MDIOC_REG);
1980
1981         reg = ENETSW_MDIOC_WR_MASK |
1982                 (phy_id << ENETSW_MDIOC_PHYID_SHIFT) |
1983                 (location << ENETSW_MDIOC_REG_SHIFT);
1984
1985         if (ext)
1986                 reg |= ENETSW_MDIOC_EXT_MASK;
1987
1988         reg |= data;
1989
1990         enetsw_writel(priv, reg, ENETSW_MDIOC_REG);
1991         udelay(50);
1992         spin_unlock_bh(&priv->enetsw_mdio_lock);
1993 }
1994
1995 static inline int bcm_enet_port_is_rgmii(int portid)
1996 {
1997         return portid >= ENETSW_RGMII_PORT0;
1998 }
1999
2000 /*
2001  * enet sw PHY polling
2002  */
2003 static void swphy_poll_timer(struct timer_list *t)
2004 {
2005         struct bcm_enet_priv *priv = from_timer(priv, t, swphy_poll);
2006         unsigned int i;
2007
2008         for (i = 0; i < priv->num_ports; i++) {
2009                 struct bcm63xx_enetsw_port *port;
2010                 int val, j, up, advertise, lpa, speed, duplex, media;
2011                 int external_phy = bcm_enet_port_is_rgmii(i);
2012                 u8 override;
2013
2014                 port = &priv->used_ports[i];
2015                 if (!port->used)
2016                         continue;
2017
2018                 if (port->bypass_link)
2019                         continue;
2020
2021                 /* dummy read to clear */
2022                 for (j = 0; j < 2; j++)
2023                         val = bcmenet_sw_mdio_read(priv, external_phy,
2024                                                    port->phy_id, MII_BMSR);
2025
2026                 if (val == 0xffff)
2027                         continue;
2028
2029                 up = (val & BMSR_LSTATUS) ? 1 : 0;
2030                 if (!(up ^ priv->sw_port_link[i]))
2031                         continue;
2032
2033                 priv->sw_port_link[i] = up;
2034
2035                 /* link changed */
2036                 if (!up) {
2037                         dev_info(&priv->pdev->dev, "link DOWN on %s\n",
2038                                  port->name);
2039                         enetsw_writeb(priv, ENETSW_PORTOV_ENABLE_MASK,
2040                                       ENETSW_PORTOV_REG(i));
2041                         enetsw_writeb(priv, ENETSW_PTCTRL_RXDIS_MASK |
2042                                       ENETSW_PTCTRL_TXDIS_MASK,
2043                                       ENETSW_PTCTRL_REG(i));
2044                         continue;
2045                 }
2046
2047                 advertise = bcmenet_sw_mdio_read(priv, external_phy,
2048                                                  port->phy_id, MII_ADVERTISE);
2049
2050                 lpa = bcmenet_sw_mdio_read(priv, external_phy, port->phy_id,
2051                                            MII_LPA);
2052
2053                 /* figure out media and duplex from advertise and LPA values */
2054                 media = mii_nway_result(lpa & advertise);
2055                 duplex = (media & ADVERTISE_FULL) ? 1 : 0;
2056
2057                 if (media & (ADVERTISE_100FULL | ADVERTISE_100HALF))
2058                         speed = 100;
2059                 else
2060                         speed = 10;
2061
2062                 if (val & BMSR_ESTATEN) {
2063                         advertise = bcmenet_sw_mdio_read(priv, external_phy,
2064                                                 port->phy_id, MII_CTRL1000);
2065
2066                         lpa = bcmenet_sw_mdio_read(priv, external_phy,
2067                                                 port->phy_id, MII_STAT1000);
2068
2069                         if (advertise & (ADVERTISE_1000FULL | ADVERTISE_1000HALF)
2070                                         && lpa & (LPA_1000FULL | LPA_1000HALF)) {
2071                                 speed = 1000;
2072                                 duplex = (lpa & LPA_1000FULL);
2073                         }
2074                 }
2075
2076                 dev_info(&priv->pdev->dev,
2077                          "link UP on %s, %dMbps, %s-duplex\n",
2078                          port->name, speed, duplex ? "full" : "half");
2079
2080                 override = ENETSW_PORTOV_ENABLE_MASK |
2081                         ENETSW_PORTOV_LINKUP_MASK;
2082
2083                 if (speed == 1000)
2084                         override |= ENETSW_IMPOV_1000_MASK;
2085                 else if (speed == 100)
2086                         override |= ENETSW_IMPOV_100_MASK;
2087                 if (duplex)
2088                         override |= ENETSW_IMPOV_FDX_MASK;
2089
2090                 enetsw_writeb(priv, override, ENETSW_PORTOV_REG(i));
2091                 enetsw_writeb(priv, 0, ENETSW_PTCTRL_REG(i));
2092         }
2093
2094         priv->swphy_poll.expires = jiffies + HZ;
2095         add_timer(&priv->swphy_poll);
2096 }
2097
2098 /*
2099  * open callback, allocate dma rings & buffers and start rx operation
2100  */
2101 static int bcm_enetsw_open(struct net_device *dev)
2102 {
2103         struct bcm_enet_priv *priv;
2104         struct device *kdev;
2105         int i, ret;
2106         unsigned int size;
2107         void *p;
2108         u32 val;
2109
2110         priv = netdev_priv(dev);
2111         kdev = &priv->pdev->dev;
2112
2113         /* mask all interrupts and request them */
2114         enet_dmac_writel(priv, 0, ENETDMAC_IRMASK, priv->rx_chan);
2115         enet_dmac_writel(priv, 0, ENETDMAC_IRMASK, priv->tx_chan);
2116
2117         ret = request_irq(priv->irq_rx, bcm_enet_isr_dma,
2118                           0, dev->name, dev);
2119         if (ret)
2120                 goto out_freeirq;
2121
2122         if (priv->irq_tx != -1) {
2123                 ret = request_irq(priv->irq_tx, bcm_enet_isr_dma,
2124                                   0, dev->name, dev);
2125                 if (ret)
2126                         goto out_freeirq_rx;
2127         }
2128
2129         /* allocate rx dma ring */
2130         size = priv->rx_ring_size * sizeof(struct bcm_enet_desc);
2131         p = dma_zalloc_coherent(kdev, size, &priv->rx_desc_dma, GFP_KERNEL);
2132         if (!p) {
2133                 dev_err(kdev, "cannot allocate rx ring %u\n", size);
2134                 ret = -ENOMEM;
2135                 goto out_freeirq_tx;
2136         }
2137
2138         priv->rx_desc_alloc_size = size;
2139         priv->rx_desc_cpu = p;
2140
2141         /* allocate tx dma ring */
2142         size = priv->tx_ring_size * sizeof(struct bcm_enet_desc);
2143         p = dma_zalloc_coherent(kdev, size, &priv->tx_desc_dma, GFP_KERNEL);
2144         if (!p) {
2145                 dev_err(kdev, "cannot allocate tx ring\n");
2146                 ret = -ENOMEM;
2147                 goto out_free_rx_ring;
2148         }
2149
2150         priv->tx_desc_alloc_size = size;
2151         priv->tx_desc_cpu = p;
2152
2153         priv->tx_skb = kzalloc(sizeof(struct sk_buff *) * priv->tx_ring_size,
2154                                GFP_KERNEL);
2155         if (!priv->tx_skb) {
2156                 dev_err(kdev, "cannot allocate rx skb queue\n");
2157                 ret = -ENOMEM;
2158                 goto out_free_tx_ring;
2159         }
2160
2161         priv->tx_desc_count = priv->tx_ring_size;
2162         priv->tx_dirty_desc = 0;
2163         priv->tx_curr_desc = 0;
2164         spin_lock_init(&priv->tx_lock);
2165
2166         /* init & fill rx ring with skbs */
2167         priv->rx_skb = kzalloc(sizeof(struct sk_buff *) * priv->rx_ring_size,
2168                                GFP_KERNEL);
2169         if (!priv->rx_skb) {
2170                 dev_err(kdev, "cannot allocate rx skb queue\n");
2171                 ret = -ENOMEM;
2172                 goto out_free_tx_skb;
2173         }
2174
2175         priv->rx_desc_count = 0;
2176         priv->rx_dirty_desc = 0;
2177         priv->rx_curr_desc = 0;
2178
2179         /* disable all ports */
2180         for (i = 0; i < priv->num_ports; i++) {
2181                 enetsw_writeb(priv, ENETSW_PORTOV_ENABLE_MASK,
2182                               ENETSW_PORTOV_REG(i));
2183                 enetsw_writeb(priv, ENETSW_PTCTRL_RXDIS_MASK |
2184                               ENETSW_PTCTRL_TXDIS_MASK,
2185                               ENETSW_PTCTRL_REG(i));
2186
2187                 priv->sw_port_link[i] = 0;
2188         }
2189
2190         /* reset mib */
2191         val = enetsw_readb(priv, ENETSW_GMCR_REG);
2192         val |= ENETSW_GMCR_RST_MIB_MASK;
2193         enetsw_writeb(priv, val, ENETSW_GMCR_REG);
2194         mdelay(1);
2195         val &= ~ENETSW_GMCR_RST_MIB_MASK;
2196         enetsw_writeb(priv, val, ENETSW_GMCR_REG);
2197         mdelay(1);
2198
2199         /* force CPU port state */
2200         val = enetsw_readb(priv, ENETSW_IMPOV_REG);
2201         val |= ENETSW_IMPOV_FORCE_MASK | ENETSW_IMPOV_LINKUP_MASK;
2202         enetsw_writeb(priv, val, ENETSW_IMPOV_REG);
2203
2204         /* enable switch forward engine */
2205         val = enetsw_readb(priv, ENETSW_SWMODE_REG);
2206         val |= ENETSW_SWMODE_FWD_EN_MASK;
2207         enetsw_writeb(priv, val, ENETSW_SWMODE_REG);
2208
2209         /* enable jumbo on all ports */
2210         enetsw_writel(priv, 0x1ff, ENETSW_JMBCTL_PORT_REG);
2211         enetsw_writew(priv, 9728, ENETSW_JMBCTL_MAXSIZE_REG);
2212
2213         /* initialize flow control buffer allocation */
2214         enet_dma_writel(priv, ENETDMA_BUFALLOC_FORCE_MASK | 0,
2215                         ENETDMA_BUFALLOC_REG(priv->rx_chan));
2216
2217         if (bcm_enet_refill_rx(dev)) {
2218                 dev_err(kdev, "cannot allocate rx skb queue\n");
2219                 ret = -ENOMEM;
2220                 goto out;
2221         }
2222
2223         /* write rx & tx ring addresses */
2224         enet_dmas_writel(priv, priv->rx_desc_dma,
2225                          ENETDMAS_RSTART_REG, priv->rx_chan);
2226         enet_dmas_writel(priv, priv->tx_desc_dma,
2227                          ENETDMAS_RSTART_REG, priv->tx_chan);
2228
2229         /* clear remaining state ram for rx & tx channel */
2230         enet_dmas_writel(priv, 0, ENETDMAS_SRAM2_REG, priv->rx_chan);
2231         enet_dmas_writel(priv, 0, ENETDMAS_SRAM2_REG, priv->tx_chan);
2232         enet_dmas_writel(priv, 0, ENETDMAS_SRAM3_REG, priv->rx_chan);
2233         enet_dmas_writel(priv, 0, ENETDMAS_SRAM3_REG, priv->tx_chan);
2234         enet_dmas_writel(priv, 0, ENETDMAS_SRAM4_REG, priv->rx_chan);
2235         enet_dmas_writel(priv, 0, ENETDMAS_SRAM4_REG, priv->tx_chan);
2236
2237         /* set dma maximum burst len */
2238         enet_dmac_writel(priv, priv->dma_maxburst,
2239                          ENETDMAC_MAXBURST, priv->rx_chan);
2240         enet_dmac_writel(priv, priv->dma_maxburst,
2241                          ENETDMAC_MAXBURST, priv->tx_chan);
2242
2243         /* set flow control low/high threshold to 1/3 / 2/3 */
2244         val = priv->rx_ring_size / 3;
2245         enet_dma_writel(priv, val, ENETDMA_FLOWCL_REG(priv->rx_chan));
2246         val = (priv->rx_ring_size * 2) / 3;
2247         enet_dma_writel(priv, val, ENETDMA_FLOWCH_REG(priv->rx_chan));
2248
2249         /* all set, enable mac and interrupts, start dma engine and
2250          * kick rx dma channel
2251          */
2252         wmb();
2253         enet_dma_writel(priv, ENETDMA_CFG_EN_MASK, ENETDMA_CFG_REG);
2254         enet_dmac_writel(priv, ENETDMAC_CHANCFG_EN_MASK,
2255                          ENETDMAC_CHANCFG, priv->rx_chan);
2256
2257         /* watch "packet transferred" interrupt in rx and tx */
2258         enet_dmac_writel(priv, ENETDMAC_IR_PKTDONE_MASK,
2259                          ENETDMAC_IR, priv->rx_chan);
2260         enet_dmac_writel(priv, ENETDMAC_IR_PKTDONE_MASK,
2261                          ENETDMAC_IR, priv->tx_chan);
2262
2263         /* make sure we enable napi before rx interrupt  */
2264         napi_enable(&priv->napi);
2265
2266         enet_dmac_writel(priv, ENETDMAC_IR_PKTDONE_MASK,
2267                          ENETDMAC_IRMASK, priv->rx_chan);
2268         enet_dmac_writel(priv, ENETDMAC_IR_PKTDONE_MASK,
2269                          ENETDMAC_IRMASK, priv->tx_chan);
2270
2271         netif_carrier_on(dev);
2272         netif_start_queue(dev);
2273
2274         /* apply override config for bypass_link ports here. */
2275         for (i = 0; i < priv->num_ports; i++) {
2276                 struct bcm63xx_enetsw_port *port;
2277                 u8 override;
2278                 port = &priv->used_ports[i];
2279                 if (!port->used)
2280                         continue;
2281
2282                 if (!port->bypass_link)
2283                         continue;
2284
2285                 override = ENETSW_PORTOV_ENABLE_MASK |
2286                         ENETSW_PORTOV_LINKUP_MASK;
2287
2288                 switch (port->force_speed) {
2289                 case 1000:
2290                         override |= ENETSW_IMPOV_1000_MASK;
2291                         break;
2292                 case 100:
2293                         override |= ENETSW_IMPOV_100_MASK;
2294                         break;
2295                 case 10:
2296                         break;
2297                 default:
2298                         pr_warn("invalid forced speed on port %s: assume 10\n",
2299                                port->name);
2300                         break;
2301                 }
2302
2303                 if (port->force_duplex_full)
2304                         override |= ENETSW_IMPOV_FDX_MASK;
2305
2306
2307                 enetsw_writeb(priv, override, ENETSW_PORTOV_REG(i));
2308                 enetsw_writeb(priv, 0, ENETSW_PTCTRL_REG(i));
2309         }
2310
2311         /* start phy polling timer */
2312         timer_setup(&priv->swphy_poll, swphy_poll_timer, 0);
2313         mod_timer(&priv->swphy_poll, jiffies);
2314         return 0;
2315
2316 out:
2317         for (i = 0; i < priv->rx_ring_size; i++) {
2318                 struct bcm_enet_desc *desc;
2319
2320                 if (!priv->rx_skb[i])
2321                         continue;
2322
2323                 desc = &priv->rx_desc_cpu[i];
2324                 dma_unmap_single(kdev, desc->address, priv->rx_skb_size,
2325                                  DMA_FROM_DEVICE);
2326                 kfree_skb(priv->rx_skb[i]);
2327         }
2328         kfree(priv->rx_skb);
2329
2330 out_free_tx_skb:
2331         kfree(priv->tx_skb);
2332
2333 out_free_tx_ring:
2334         dma_free_coherent(kdev, priv->tx_desc_alloc_size,
2335                           priv->tx_desc_cpu, priv->tx_desc_dma);
2336
2337 out_free_rx_ring:
2338         dma_free_coherent(kdev, priv->rx_desc_alloc_size,
2339                           priv->rx_desc_cpu, priv->rx_desc_dma);
2340
2341 out_freeirq_tx:
2342         if (priv->irq_tx != -1)
2343                 free_irq(priv->irq_tx, dev);
2344
2345 out_freeirq_rx:
2346         free_irq(priv->irq_rx, dev);
2347
2348 out_freeirq:
2349         return ret;
2350 }
2351
2352 /* stop callback */
2353 static int bcm_enetsw_stop(struct net_device *dev)
2354 {
2355         struct bcm_enet_priv *priv;
2356         struct device *kdev;
2357         int i;
2358
2359         priv = netdev_priv(dev);
2360         kdev = &priv->pdev->dev;
2361
2362         del_timer_sync(&priv->swphy_poll);
2363         netif_stop_queue(dev);
2364         napi_disable(&priv->napi);
2365         del_timer_sync(&priv->rx_timeout);
2366
2367         /* mask all interrupts */
2368         enet_dmac_writel(priv, 0, ENETDMAC_IRMASK, priv->rx_chan);
2369         enet_dmac_writel(priv, 0, ENETDMAC_IRMASK, priv->tx_chan);
2370
2371         /* disable dma & mac */
2372         bcm_enet_disable_dma(priv, priv->tx_chan);
2373         bcm_enet_disable_dma(priv, priv->rx_chan);
2374
2375         /* force reclaim of all tx buffers */
2376         bcm_enet_tx_reclaim(dev, 1);
2377
2378         /* free the rx skb ring */
2379         for (i = 0; i < priv->rx_ring_size; i++) {
2380                 struct bcm_enet_desc *desc;
2381
2382                 if (!priv->rx_skb[i])
2383                         continue;
2384
2385                 desc = &priv->rx_desc_cpu[i];
2386                 dma_unmap_single(kdev, desc->address, priv->rx_skb_size,
2387                                  DMA_FROM_DEVICE);
2388                 kfree_skb(priv->rx_skb[i]);
2389         }
2390
2391         /* free remaining allocated memory */
2392         kfree(priv->rx_skb);
2393         kfree(priv->tx_skb);
2394         dma_free_coherent(kdev, priv->rx_desc_alloc_size,
2395                           priv->rx_desc_cpu, priv->rx_desc_dma);
2396         dma_free_coherent(kdev, priv->tx_desc_alloc_size,
2397                           priv->tx_desc_cpu, priv->tx_desc_dma);
2398         if (priv->irq_tx != -1)
2399                 free_irq(priv->irq_tx, dev);
2400         free_irq(priv->irq_rx, dev);
2401
2402         return 0;
2403 }
2404
2405 /* try to sort out phy external status by walking the used_port field
2406  * in the bcm_enet_priv structure. in case the phy address is not
2407  * assigned to any physical port on the switch, assume it is external
2408  * (and yell at the user).
2409  */
2410 static int bcm_enetsw_phy_is_external(struct bcm_enet_priv *priv, int phy_id)
2411 {
2412         int i;
2413
2414         for (i = 0; i < priv->num_ports; ++i) {
2415                 if (!priv->used_ports[i].used)
2416                         continue;
2417                 if (priv->used_ports[i].phy_id == phy_id)
2418                         return bcm_enet_port_is_rgmii(i);
2419         }
2420
2421         printk_once(KERN_WARNING  "bcm63xx_enet: could not find a used port with phy_id %i, assuming phy is external\n",
2422                     phy_id);
2423         return 1;
2424 }
2425
2426 /* can't use bcmenet_sw_mdio_read directly as we need to sort out
2427  * external/internal status of the given phy_id first.
2428  */
2429 static int bcm_enetsw_mii_mdio_read(struct net_device *dev, int phy_id,
2430                                     int location)
2431 {
2432         struct bcm_enet_priv *priv;
2433
2434         priv = netdev_priv(dev);
2435         return bcmenet_sw_mdio_read(priv,
2436                                     bcm_enetsw_phy_is_external(priv, phy_id),
2437                                     phy_id, location);
2438 }
2439
2440 /* can't use bcmenet_sw_mdio_write directly as we need to sort out
2441  * external/internal status of the given phy_id first.
2442  */
2443 static void bcm_enetsw_mii_mdio_write(struct net_device *dev, int phy_id,
2444                                       int location,
2445                                       int val)
2446 {
2447         struct bcm_enet_priv *priv;
2448
2449         priv = netdev_priv(dev);
2450         bcmenet_sw_mdio_write(priv, bcm_enetsw_phy_is_external(priv, phy_id),
2451                               phy_id, location, val);
2452 }
2453
2454 static int bcm_enetsw_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
2455 {
2456         struct mii_if_info mii;
2457
2458         mii.dev = dev;
2459         mii.mdio_read = bcm_enetsw_mii_mdio_read;
2460         mii.mdio_write = bcm_enetsw_mii_mdio_write;
2461         mii.phy_id = 0;
2462         mii.phy_id_mask = 0x3f;
2463         mii.reg_num_mask = 0x1f;
2464         return generic_mii_ioctl(&mii, if_mii(rq), cmd, NULL);
2465
2466 }
2467
2468 static const struct net_device_ops bcm_enetsw_ops = {
2469         .ndo_open               = bcm_enetsw_open,
2470         .ndo_stop               = bcm_enetsw_stop,
2471         .ndo_start_xmit         = bcm_enet_start_xmit,
2472         .ndo_change_mtu         = bcm_enet_change_mtu,
2473         .ndo_do_ioctl           = bcm_enetsw_ioctl,
2474 };
2475
2476
2477 static const struct bcm_enet_stats bcm_enetsw_gstrings_stats[] = {
2478         { "rx_packets", DEV_STAT(rx_packets), -1 },
2479         { "tx_packets", DEV_STAT(tx_packets), -1 },
2480         { "rx_bytes", DEV_STAT(rx_bytes), -1 },
2481         { "tx_bytes", DEV_STAT(tx_bytes), -1 },
2482         { "rx_errors", DEV_STAT(rx_errors), -1 },
2483         { "tx_errors", DEV_STAT(tx_errors), -1 },
2484         { "rx_dropped", DEV_STAT(rx_dropped), -1 },
2485         { "tx_dropped", DEV_STAT(tx_dropped), -1 },
2486
2487         { "tx_good_octets", GEN_STAT(mib.tx_gd_octets), ETHSW_MIB_RX_GD_OCT },
2488         { "tx_unicast", GEN_STAT(mib.tx_unicast), ETHSW_MIB_RX_BRDCAST },
2489         { "tx_broadcast", GEN_STAT(mib.tx_brdcast), ETHSW_MIB_RX_BRDCAST },
2490         { "tx_multicast", GEN_STAT(mib.tx_mult), ETHSW_MIB_RX_MULT },
2491         { "tx_64_octets", GEN_STAT(mib.tx_64), ETHSW_MIB_RX_64 },
2492         { "tx_65_127_oct", GEN_STAT(mib.tx_65_127), ETHSW_MIB_RX_65_127 },
2493         { "tx_128_255_oct", GEN_STAT(mib.tx_128_255), ETHSW_MIB_RX_128_255 },
2494         { "tx_256_511_oct", GEN_STAT(mib.tx_256_511), ETHSW_MIB_RX_256_511 },
2495         { "tx_512_1023_oct", GEN_STAT(mib.tx_512_1023), ETHSW_MIB_RX_512_1023},
2496         { "tx_1024_1522_oct", GEN_STAT(mib.tx_1024_max),
2497           ETHSW_MIB_RX_1024_1522 },
2498         { "tx_1523_2047_oct", GEN_STAT(mib.tx_1523_2047),
2499           ETHSW_MIB_RX_1523_2047 },
2500         { "tx_2048_4095_oct", GEN_STAT(mib.tx_2048_4095),
2501           ETHSW_MIB_RX_2048_4095 },
2502         { "tx_4096_8191_oct", GEN_STAT(mib.tx_4096_8191),
2503           ETHSW_MIB_RX_4096_8191 },
2504         { "tx_8192_9728_oct", GEN_STAT(mib.tx_8192_9728),
2505           ETHSW_MIB_RX_8192_9728 },
2506         { "tx_oversize", GEN_STAT(mib.tx_ovr), ETHSW_MIB_RX_OVR },
2507         { "tx_oversize_drop", GEN_STAT(mib.tx_ovr), ETHSW_MIB_RX_OVR_DISC },
2508         { "tx_dropped", GEN_STAT(mib.tx_drop), ETHSW_MIB_RX_DROP },
2509         { "tx_undersize", GEN_STAT(mib.tx_underrun), ETHSW_MIB_RX_UND },
2510         { "tx_pause", GEN_STAT(mib.tx_pause), ETHSW_MIB_RX_PAUSE },
2511
2512         { "rx_good_octets", GEN_STAT(mib.rx_gd_octets), ETHSW_MIB_TX_ALL_OCT },
2513         { "rx_broadcast", GEN_STAT(mib.rx_brdcast), ETHSW_MIB_TX_BRDCAST },
2514         { "rx_multicast", GEN_STAT(mib.rx_mult), ETHSW_MIB_TX_MULT },
2515         { "rx_unicast", GEN_STAT(mib.rx_unicast), ETHSW_MIB_TX_MULT },
2516         { "rx_pause", GEN_STAT(mib.rx_pause), ETHSW_MIB_TX_PAUSE },
2517         { "rx_dropped", GEN_STAT(mib.rx_drop), ETHSW_MIB_TX_DROP_PKTS },
2518
2519 };
2520
2521 #define BCM_ENETSW_STATS_LEN    \
2522         (sizeof(bcm_enetsw_gstrings_stats) / sizeof(struct bcm_enet_stats))
2523
2524 static void bcm_enetsw_get_strings(struct net_device *netdev,
2525                                    u32 stringset, u8 *data)
2526 {
2527         int i;
2528
2529         switch (stringset) {
2530         case ETH_SS_STATS:
2531                 for (i = 0; i < BCM_ENETSW_STATS_LEN; i++) {
2532                         memcpy(data + i * ETH_GSTRING_LEN,
2533                                bcm_enetsw_gstrings_stats[i].stat_string,
2534                                ETH_GSTRING_LEN);
2535                 }
2536                 break;
2537         }
2538 }
2539
2540 static int bcm_enetsw_get_sset_count(struct net_device *netdev,
2541                                      int string_set)
2542 {
2543         switch (string_set) {
2544         case ETH_SS_STATS:
2545                 return BCM_ENETSW_STATS_LEN;
2546         default:
2547                 return -EINVAL;
2548         }
2549 }
2550
2551 static void bcm_enetsw_get_drvinfo(struct net_device *netdev,
2552                                    struct ethtool_drvinfo *drvinfo)
2553 {
2554         strncpy(drvinfo->driver, bcm_enet_driver_name, 32);
2555         strncpy(drvinfo->version, bcm_enet_driver_version, 32);
2556         strncpy(drvinfo->fw_version, "N/A", 32);
2557         strncpy(drvinfo->bus_info, "bcm63xx", 32);
2558 }
2559
2560 static void bcm_enetsw_get_ethtool_stats(struct net_device *netdev,
2561                                          struct ethtool_stats *stats,
2562                                          u64 *data)
2563 {
2564         struct bcm_enet_priv *priv;
2565         int i;
2566
2567         priv = netdev_priv(netdev);
2568
2569         for (i = 0; i < BCM_ENETSW_STATS_LEN; i++) {
2570                 const struct bcm_enet_stats *s;
2571                 u32 lo, hi;
2572                 char *p;
2573                 int reg;
2574
2575                 s = &bcm_enetsw_gstrings_stats[i];
2576
2577                 reg = s->mib_reg;
2578                 if (reg == -1)
2579                         continue;
2580
2581                 lo = enetsw_readl(priv, ENETSW_MIB_REG(reg));
2582                 p = (char *)priv + s->stat_offset;
2583
2584                 if (s->sizeof_stat == sizeof(u64)) {
2585                         hi = enetsw_readl(priv, ENETSW_MIB_REG(reg + 1));
2586                         *(u64 *)p = ((u64)hi << 32 | lo);
2587                 } else {
2588                         *(u32 *)p = lo;
2589                 }
2590         }
2591
2592         for (i = 0; i < BCM_ENETSW_STATS_LEN; i++) {
2593                 const struct bcm_enet_stats *s;
2594                 char *p;
2595
2596                 s = &bcm_enetsw_gstrings_stats[i];
2597
2598                 if (s->mib_reg == -1)
2599                         p = (char *)&netdev->stats + s->stat_offset;
2600                 else
2601                         p = (char *)priv + s->stat_offset;
2602
2603                 data[i] = (s->sizeof_stat == sizeof(u64)) ?
2604                         *(u64 *)p : *(u32 *)p;
2605         }
2606 }
2607
2608 static void bcm_enetsw_get_ringparam(struct net_device *dev,
2609                                      struct ethtool_ringparam *ering)
2610 {
2611         struct bcm_enet_priv *priv;
2612
2613         priv = netdev_priv(dev);
2614
2615         /* rx/tx ring is actually only limited by memory */
2616         ering->rx_max_pending = 8192;
2617         ering->tx_max_pending = 8192;
2618         ering->rx_mini_max_pending = 0;
2619         ering->rx_jumbo_max_pending = 0;
2620         ering->rx_pending = priv->rx_ring_size;
2621         ering->tx_pending = priv->tx_ring_size;
2622 }
2623
2624 static int bcm_enetsw_set_ringparam(struct net_device *dev,
2625                                     struct ethtool_ringparam *ering)
2626 {
2627         struct bcm_enet_priv *priv;
2628         int was_running;
2629
2630         priv = netdev_priv(dev);
2631
2632         was_running = 0;
2633         if (netif_running(dev)) {
2634                 bcm_enetsw_stop(dev);
2635                 was_running = 1;
2636         }
2637
2638         priv->rx_ring_size = ering->rx_pending;
2639         priv->tx_ring_size = ering->tx_pending;
2640
2641         if (was_running) {
2642                 int err;
2643
2644                 err = bcm_enetsw_open(dev);
2645                 if (err)
2646                         dev_close(dev);
2647         }
2648         return 0;
2649 }
2650
2651 static const struct ethtool_ops bcm_enetsw_ethtool_ops = {
2652         .get_strings            = bcm_enetsw_get_strings,
2653         .get_sset_count         = bcm_enetsw_get_sset_count,
2654         .get_ethtool_stats      = bcm_enetsw_get_ethtool_stats,
2655         .get_drvinfo            = bcm_enetsw_get_drvinfo,
2656         .get_ringparam          = bcm_enetsw_get_ringparam,
2657         .set_ringparam          = bcm_enetsw_set_ringparam,
2658 };
2659
2660 /* allocate netdevice, request register memory and register device. */
2661 static int bcm_enetsw_probe(struct platform_device *pdev)
2662 {
2663         struct bcm_enet_priv *priv;
2664         struct net_device *dev;
2665         struct bcm63xx_enetsw_platform_data *pd;
2666         struct resource *res_mem;
2667         int ret, irq_rx, irq_tx;
2668
2669         if (!bcm_enet_shared_base[0])
2670                 return -EPROBE_DEFER;
2671
2672         res_mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2673         irq_rx = platform_get_irq(pdev, 0);
2674         irq_tx = platform_get_irq(pdev, 1);
2675         if (!res_mem || irq_rx < 0)
2676                 return -ENODEV;
2677
2678         ret = 0;
2679         dev = alloc_etherdev(sizeof(*priv));
2680         if (!dev)
2681                 return -ENOMEM;
2682         priv = netdev_priv(dev);
2683         memset(priv, 0, sizeof(*priv));
2684
2685         /* initialize default and fetch platform data */
2686         priv->enet_is_sw = true;
2687         priv->irq_rx = irq_rx;
2688         priv->irq_tx = irq_tx;
2689         priv->rx_ring_size = BCMENET_DEF_RX_DESC;
2690         priv->tx_ring_size = BCMENET_DEF_TX_DESC;
2691         priv->dma_maxburst = BCMENETSW_DMA_MAXBURST;
2692
2693         pd = dev_get_platdata(&pdev->dev);
2694         if (pd) {
2695                 memcpy(dev->dev_addr, pd->mac_addr, ETH_ALEN);
2696                 memcpy(priv->used_ports, pd->used_ports,
2697                        sizeof(pd->used_ports));
2698                 priv->num_ports = pd->num_ports;
2699                 priv->dma_has_sram = pd->dma_has_sram;
2700                 priv->dma_chan_en_mask = pd->dma_chan_en_mask;
2701                 priv->dma_chan_int_mask = pd->dma_chan_int_mask;
2702                 priv->dma_chan_width = pd->dma_chan_width;
2703         }
2704
2705         ret = bcm_enet_change_mtu(dev, dev->mtu);
2706         if (ret)
2707                 goto out;
2708
2709         priv->base = devm_ioremap_resource(&pdev->dev, res_mem);
2710         if (IS_ERR(priv->base)) {
2711                 ret = PTR_ERR(priv->base);
2712                 goto out;
2713         }
2714
2715         priv->mac_clk = devm_clk_get(&pdev->dev, "enetsw");
2716         if (IS_ERR(priv->mac_clk)) {
2717                 ret = PTR_ERR(priv->mac_clk);
2718                 goto out;
2719         }
2720         ret = clk_prepare_enable(priv->mac_clk);
2721         if (ret)
2722                 goto out;
2723
2724         priv->rx_chan = 0;
2725         priv->tx_chan = 1;
2726         spin_lock_init(&priv->rx_lock);
2727
2728         /* init rx timeout (used for oom) */
2729         timer_setup(&priv->rx_timeout, bcm_enet_refill_rx_timer, 0);
2730
2731         /* register netdevice */
2732         dev->netdev_ops = &bcm_enetsw_ops;
2733         netif_napi_add(dev, &priv->napi, bcm_enet_poll, 16);
2734         dev->ethtool_ops = &bcm_enetsw_ethtool_ops;
2735         SET_NETDEV_DEV(dev, &pdev->dev);
2736
2737         spin_lock_init(&priv->enetsw_mdio_lock);
2738
2739         ret = register_netdev(dev);
2740         if (ret)
2741                 goto out_disable_clk;
2742
2743         netif_carrier_off(dev);
2744         platform_set_drvdata(pdev, dev);
2745         priv->pdev = pdev;
2746         priv->net_dev = dev;
2747
2748         return 0;
2749
2750 out_disable_clk:
2751         clk_disable_unprepare(priv->mac_clk);
2752 out:
2753         free_netdev(dev);
2754         return ret;
2755 }
2756
2757
2758 /* exit func, stops hardware and unregisters netdevice */
2759 static int bcm_enetsw_remove(struct platform_device *pdev)
2760 {
2761         struct bcm_enet_priv *priv;
2762         struct net_device *dev;
2763
2764         /* stop netdevice */
2765         dev = platform_get_drvdata(pdev);
2766         priv = netdev_priv(dev);
2767         unregister_netdev(dev);
2768
2769         clk_disable_unprepare(priv->mac_clk);
2770
2771         free_netdev(dev);
2772         return 0;
2773 }
2774
2775 struct platform_driver bcm63xx_enetsw_driver = {
2776         .probe  = bcm_enetsw_probe,
2777         .remove = bcm_enetsw_remove,
2778         .driver = {
2779                 .name   = "bcm63xx_enetsw",
2780                 .owner  = THIS_MODULE,
2781         },
2782 };
2783
2784 /* reserve & remap memory space shared between all macs */
2785 static int bcm_enet_shared_probe(struct platform_device *pdev)
2786 {
2787         struct resource *res;
2788         void __iomem *p[3];
2789         unsigned int i;
2790
2791         memset(bcm_enet_shared_base, 0, sizeof(bcm_enet_shared_base));
2792
2793         for (i = 0; i < 3; i++) {
2794                 res = platform_get_resource(pdev, IORESOURCE_MEM, i);
2795                 p[i] = devm_ioremap_resource(&pdev->dev, res);
2796                 if (IS_ERR(p[i]))
2797                         return PTR_ERR(p[i]);
2798         }
2799
2800         memcpy(bcm_enet_shared_base, p, sizeof(bcm_enet_shared_base));
2801
2802         return 0;
2803 }
2804
2805 static int bcm_enet_shared_remove(struct platform_device *pdev)
2806 {
2807         return 0;
2808 }
2809
2810 /* this "shared" driver is needed because both macs share a single
2811  * address space
2812  */
2813 struct platform_driver bcm63xx_enet_shared_driver = {
2814         .probe  = bcm_enet_shared_probe,
2815         .remove = bcm_enet_shared_remove,
2816         .driver = {
2817                 .name   = "bcm63xx_enet_shared",
2818                 .owner  = THIS_MODULE,
2819         },
2820 };
2821
2822 static struct platform_driver * const drivers[] = {
2823         &bcm63xx_enet_shared_driver,
2824         &bcm63xx_enet_driver,
2825         &bcm63xx_enetsw_driver,
2826 };
2827
2828 /* entry point */
2829 static int __init bcm_enet_init(void)
2830 {
2831         return platform_register_drivers(drivers, ARRAY_SIZE(drivers));
2832 }
2833
2834 static void __exit bcm_enet_exit(void)
2835 {
2836         platform_unregister_drivers(drivers, ARRAY_SIZE(drivers));
2837 }
2838
2839
2840 module_init(bcm_enet_init);
2841 module_exit(bcm_enet_exit);
2842
2843 MODULE_DESCRIPTION("BCM63xx internal ethernet mac driver");
2844 MODULE_AUTHOR("Maxime Bizon <mbizon@freebox.fr>");
2845 MODULE_LICENSE("GPL");