2 * Copyright (c) 2013 Johannes Berg <johannes@sipsolutions.net>
4 * This file is free software: you may copy, redistribute and/or modify it
5 * under the terms of the GNU General Public License as published by the
6 * Free Software Foundation, either version 2 of the License, or (at your
7 * option) any later version.
9 * This file is distributed in the hope that it will be useful, but
10 * WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
12 * General Public License for more details.
14 * You should have received a copy of the GNU General Public License
15 * along with this program. If not, see <http://www.gnu.org/licenses/>.
17 * This file incorporates work covered by the following copyright and
20 * Copyright (c) 2012 Qualcomm Atheros, Inc.
22 * Permission to use, copy, modify, and/or distribute this software for any
23 * purpose with or without fee is hereby granted, provided that the above
24 * copyright notice and this permission notice appear in all copies.
26 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
27 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
28 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
29 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
30 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
31 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
32 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
35 #include <linux/module.h>
36 #include <linux/pci.h>
37 #include <linux/interrupt.h>
39 #include <linux/ipv6.h>
40 #include <linux/if_vlan.h>
41 #include <linux/mdio.h>
42 #include <linux/aer.h>
43 #include <linux/bitops.h>
44 #include <linux/netdevice.h>
45 #include <linux/etherdevice.h>
46 #include <net/ip6_checksum.h>
47 #include <linux/crc32.h>
52 const char alx_drv_name[] = "alx";
54 static void alx_free_txbuf(struct alx_tx_queue *txq, int entry)
56 struct alx_buffer *txb = &txq->bufs[entry];
58 if (dma_unmap_len(txb, size)) {
59 dma_unmap_single(txq->dev,
60 dma_unmap_addr(txb, dma),
61 dma_unmap_len(txb, size),
63 dma_unmap_len_set(txb, size, 0);
67 dev_kfree_skb_any(txb->skb);
72 static int alx_refill_rx_ring(struct alx_priv *alx, gfp_t gfp)
74 struct alx_rx_queue *rxq = alx->qnapi[0]->rxq;
76 struct alx_buffer *cur_buf;
78 u16 cur, next, count = 0;
80 next = cur = rxq->write_idx;
81 if (++next == alx->rx_ringsz)
83 cur_buf = &rxq->bufs[cur];
85 while (!cur_buf->skb && next != rxq->read_idx) {
86 struct alx_rfd *rfd = &rxq->rfd[cur];
89 * When DMA RX address is set to something like
90 * 0x....fc0, it will be very likely to cause DMA
93 * To work around it, we apply rx skb with 64 bytes
94 * longer space, and offset the address whenever
95 * 0x....fc0 is detected.
97 skb = __netdev_alloc_skb(alx->dev, alx->rxbuf_size + 64, gfp);
101 if (((unsigned long)skb->data & 0xfff) == 0xfc0)
102 skb_reserve(skb, 64);
104 dma = dma_map_single(&alx->hw.pdev->dev,
105 skb->data, alx->rxbuf_size,
107 if (dma_mapping_error(&alx->hw.pdev->dev, dma)) {
112 /* Unfortunately, RX descriptor buffers must be 4-byte
113 * aligned, so we can't use IP alignment.
115 if (WARN_ON(dma & 3)) {
121 dma_unmap_len_set(cur_buf, size, alx->rxbuf_size);
122 dma_unmap_addr_set(cur_buf, dma, dma);
123 rfd->addr = cpu_to_le64(dma);
126 if (++next == alx->rx_ringsz)
128 cur_buf = &rxq->bufs[cur];
133 /* flush all updates before updating hardware */
135 rxq->write_idx = cur;
136 alx_write_mem16(&alx->hw, ALX_RFD_PIDX, cur);
142 static struct alx_tx_queue *alx_tx_queue_mapping(struct alx_priv *alx,
145 unsigned int r_idx = skb->queue_mapping;
147 if (r_idx >= alx->num_txq)
148 r_idx = r_idx % alx->num_txq;
150 return alx->qnapi[r_idx]->txq;
153 static struct netdev_queue *alx_get_tx_queue(const struct alx_tx_queue *txq)
155 return netdev_get_tx_queue(txq->netdev, txq->queue_idx);
158 static inline int alx_tpd_avail(struct alx_tx_queue *txq)
160 if (txq->write_idx >= txq->read_idx)
161 return txq->count + txq->read_idx - txq->write_idx - 1;
162 return txq->read_idx - txq->write_idx - 1;
165 static bool alx_clean_tx_irq(struct alx_tx_queue *txq)
167 struct alx_priv *alx;
168 struct netdev_queue *tx_queue;
169 u16 hw_read_idx, sw_read_idx;
170 unsigned int total_bytes = 0, total_packets = 0;
171 int budget = ALX_DEFAULT_TX_WORK;
173 alx = netdev_priv(txq->netdev);
174 tx_queue = alx_get_tx_queue(txq);
176 sw_read_idx = txq->read_idx;
177 hw_read_idx = alx_read_mem16(&alx->hw, txq->c_reg);
179 if (sw_read_idx != hw_read_idx) {
180 while (sw_read_idx != hw_read_idx && budget > 0) {
183 skb = txq->bufs[sw_read_idx].skb;
185 total_bytes += skb->len;
190 alx_free_txbuf(txq, sw_read_idx);
192 if (++sw_read_idx == txq->count)
195 txq->read_idx = sw_read_idx;
197 netdev_tx_completed_queue(tx_queue, total_packets, total_bytes);
200 if (netif_tx_queue_stopped(tx_queue) && netif_carrier_ok(alx->dev) &&
201 alx_tpd_avail(txq) > txq->count / 4)
202 netif_tx_wake_queue(tx_queue);
204 return sw_read_idx == hw_read_idx;
207 static void alx_schedule_link_check(struct alx_priv *alx)
209 schedule_work(&alx->link_check_wk);
212 static void alx_schedule_reset(struct alx_priv *alx)
214 schedule_work(&alx->reset_wk);
217 static int alx_clean_rx_irq(struct alx_rx_queue *rxq, int budget)
219 struct alx_priv *alx;
221 struct alx_buffer *rxb;
223 u16 length, rfd_cleaned = 0;
226 alx = netdev_priv(rxq->netdev);
228 while (work < budget) {
229 rrd = &rxq->rrd[rxq->rrd_read_idx];
230 if (!(rrd->word3 & cpu_to_le32(1 << RRD_UPDATED_SHIFT)))
232 rrd->word3 &= ~cpu_to_le32(1 << RRD_UPDATED_SHIFT);
234 if (ALX_GET_FIELD(le32_to_cpu(rrd->word0),
235 RRD_SI) != rxq->read_idx ||
236 ALX_GET_FIELD(le32_to_cpu(rrd->word0),
238 alx_schedule_reset(alx);
242 rxb = &rxq->bufs[rxq->read_idx];
243 dma_unmap_single(rxq->dev,
244 dma_unmap_addr(rxb, dma),
245 dma_unmap_len(rxb, size),
247 dma_unmap_len_set(rxb, size, 0);
251 if (rrd->word3 & cpu_to_le32(1 << RRD_ERR_RES_SHIFT) ||
252 rrd->word3 & cpu_to_le32(1 << RRD_ERR_LEN_SHIFT)) {
254 dev_kfree_skb_any(skb);
258 length = ALX_GET_FIELD(le32_to_cpu(rrd->word3),
259 RRD_PKTLEN) - ETH_FCS_LEN;
260 skb_put(skb, length);
261 skb->protocol = eth_type_trans(skb, rxq->netdev);
263 skb_checksum_none_assert(skb);
264 if (alx->dev->features & NETIF_F_RXCSUM &&
265 !(rrd->word3 & (cpu_to_le32(1 << RRD_ERR_L4_SHIFT) |
266 cpu_to_le32(1 << RRD_ERR_IPV4_SHIFT)))) {
267 switch (ALX_GET_FIELD(le32_to_cpu(rrd->word2),
269 case RRD_PID_IPV6UDP:
270 case RRD_PID_IPV4UDP:
271 case RRD_PID_IPV4TCP:
272 case RRD_PID_IPV6TCP:
273 skb->ip_summed = CHECKSUM_UNNECESSARY;
278 napi_gro_receive(&rxq->np->napi, skb);
282 if (++rxq->read_idx == rxq->count)
284 if (++rxq->rrd_read_idx == rxq->count)
285 rxq->rrd_read_idx = 0;
287 if (++rfd_cleaned > ALX_RX_ALLOC_THRESH)
288 rfd_cleaned -= alx_refill_rx_ring(alx, GFP_ATOMIC);
292 alx_refill_rx_ring(alx, GFP_ATOMIC);
297 static int alx_poll(struct napi_struct *napi, int budget)
299 struct alx_napi *np = container_of(napi, struct alx_napi, napi);
300 struct alx_priv *alx = np->alx;
301 struct alx_hw *hw = &alx->hw;
303 bool tx_complete = true;
307 tx_complete = alx_clean_tx_irq(np->txq);
309 work = alx_clean_rx_irq(np->rxq, budget);
311 if (!tx_complete || work == budget)
314 napi_complete(&np->napi);
316 /* enable interrupt */
317 if (alx->flags & ALX_FLAG_USING_MSIX) {
318 alx_mask_msix(hw, np->vec_idx, false);
320 spin_lock_irqsave(&alx->irq_lock, flags);
321 alx->int_mask |= ALX_ISR_TX_Q0 | ALX_ISR_RX_Q0;
322 alx_write_mem32(hw, ALX_IMR, alx->int_mask);
323 spin_unlock_irqrestore(&alx->irq_lock, flags);
331 static bool alx_intr_handle_misc(struct alx_priv *alx, u32 intr)
333 struct alx_hw *hw = &alx->hw;
335 if (intr & ALX_ISR_FATAL) {
336 netif_warn(alx, hw, alx->dev,
337 "fatal interrupt 0x%x, resetting\n", intr);
338 alx_schedule_reset(alx);
342 if (intr & ALX_ISR_ALERT)
343 netdev_warn(alx->dev, "alert interrupt: 0x%x\n", intr);
345 if (intr & ALX_ISR_PHY) {
346 /* suppress PHY interrupt, because the source
347 * is from PHY internal. only the internal status
348 * is cleared, the interrupt status could be cleared.
350 alx->int_mask &= ~ALX_ISR_PHY;
351 alx_write_mem32(hw, ALX_IMR, alx->int_mask);
352 alx_schedule_link_check(alx);
358 static irqreturn_t alx_intr_handle(struct alx_priv *alx, u32 intr)
360 struct alx_hw *hw = &alx->hw;
362 spin_lock(&alx->irq_lock);
365 alx_write_mem32(hw, ALX_ISR, intr | ALX_ISR_DIS);
366 intr &= alx->int_mask;
368 if (alx_intr_handle_misc(alx, intr))
371 if (intr & (ALX_ISR_TX_Q0 | ALX_ISR_RX_Q0)) {
372 napi_schedule(&alx->qnapi[0]->napi);
373 /* mask rx/tx interrupt, enable them when napi complete */
374 alx->int_mask &= ~ALX_ISR_ALL_QUEUES;
375 alx_write_mem32(hw, ALX_IMR, alx->int_mask);
378 alx_write_mem32(hw, ALX_ISR, 0);
381 spin_unlock(&alx->irq_lock);
385 static irqreturn_t alx_intr_msix_ring(int irq, void *data)
387 struct alx_napi *np = data;
388 struct alx_hw *hw = &np->alx->hw;
390 /* mask interrupt to ACK chip */
391 alx_mask_msix(hw, np->vec_idx, true);
392 /* clear interrupt status */
393 alx_write_mem32(hw, ALX_ISR, np->vec_mask);
395 napi_schedule(&np->napi);
400 static irqreturn_t alx_intr_msix_misc(int irq, void *data)
402 struct alx_priv *alx = data;
403 struct alx_hw *hw = &alx->hw;
406 /* mask interrupt to ACK chip */
407 alx_mask_msix(hw, 0, true);
409 /* read interrupt status */
410 intr = alx_read_mem32(hw, ALX_ISR);
411 intr &= (alx->int_mask & ~ALX_ISR_ALL_QUEUES);
413 if (alx_intr_handle_misc(alx, intr))
416 /* clear interrupt status */
417 alx_write_mem32(hw, ALX_ISR, intr);
419 /* enable interrupt again */
420 alx_mask_msix(hw, 0, false);
425 static irqreturn_t alx_intr_msi(int irq, void *data)
427 struct alx_priv *alx = data;
429 return alx_intr_handle(alx, alx_read_mem32(&alx->hw, ALX_ISR));
432 static irqreturn_t alx_intr_legacy(int irq, void *data)
434 struct alx_priv *alx = data;
435 struct alx_hw *hw = &alx->hw;
438 intr = alx_read_mem32(hw, ALX_ISR);
440 if (intr & ALX_ISR_DIS || !(intr & alx->int_mask))
443 return alx_intr_handle(alx, intr);
446 static const u16 txring_header_reg[] = {ALX_TPD_PRI0_ADDR_LO,
447 ALX_TPD_PRI1_ADDR_LO,
448 ALX_TPD_PRI2_ADDR_LO,
449 ALX_TPD_PRI3_ADDR_LO};
451 static void alx_init_ring_ptrs(struct alx_priv *alx)
453 struct alx_hw *hw = &alx->hw;
454 u32 addr_hi = ((u64)alx->descmem.dma) >> 32;
458 for (i = 0; i < alx->num_napi; i++) {
461 np->txq->read_idx = 0;
462 np->txq->write_idx = 0;
464 txring_header_reg[np->txq->queue_idx],
469 np->rxq->read_idx = 0;
470 np->rxq->write_idx = 0;
471 np->rxq->rrd_read_idx = 0;
472 alx_write_mem32(hw, ALX_RRD_ADDR_LO, np->rxq->rrd_dma);
473 alx_write_mem32(hw, ALX_RFD_ADDR_LO, np->rxq->rfd_dma);
477 alx_write_mem32(hw, ALX_TX_BASE_ADDR_HI, addr_hi);
478 alx_write_mem32(hw, ALX_TPD_RING_SZ, alx->tx_ringsz);
480 alx_write_mem32(hw, ALX_RX_BASE_ADDR_HI, addr_hi);
481 alx_write_mem32(hw, ALX_RRD_RING_SZ, alx->rx_ringsz);
482 alx_write_mem32(hw, ALX_RFD_RING_SZ, alx->rx_ringsz);
483 alx_write_mem32(hw, ALX_RFD_BUF_SZ, alx->rxbuf_size);
485 /* load these pointers into the chip */
486 alx_write_mem32(hw, ALX_SRAM9, ALX_SRAM_LOAD_PTR);
489 static void alx_free_txring_buf(struct alx_tx_queue *txq)
496 for (i = 0; i < txq->count; i++)
497 alx_free_txbuf(txq, i);
499 memset(txq->bufs, 0, txq->count * sizeof(struct alx_buffer));
500 memset(txq->tpd, 0, txq->count * sizeof(struct alx_txd));
504 netdev_tx_reset_queue(alx_get_tx_queue(txq));
507 static void alx_free_rxring_buf(struct alx_rx_queue *rxq)
509 struct alx_buffer *cur_buf;
515 for (i = 0; i < rxq->count; i++) {
516 cur_buf = rxq->bufs + i;
518 dma_unmap_single(rxq->dev,
519 dma_unmap_addr(cur_buf, dma),
520 dma_unmap_len(cur_buf, size),
522 dev_kfree_skb(cur_buf->skb);
524 dma_unmap_len_set(cur_buf, size, 0);
525 dma_unmap_addr_set(cur_buf, dma, 0);
531 rxq->rrd_read_idx = 0;
534 static void alx_free_buffers(struct alx_priv *alx)
538 for (i = 0; i < alx->num_txq; i++)
539 if (alx->qnapi[i] && alx->qnapi[i]->txq)
540 alx_free_txring_buf(alx->qnapi[i]->txq);
542 if (alx->qnapi[0] && alx->qnapi[0]->rxq)
543 alx_free_rxring_buf(alx->qnapi[0]->rxq);
546 static int alx_reinit_rings(struct alx_priv *alx)
548 alx_free_buffers(alx);
550 alx_init_ring_ptrs(alx);
552 if (!alx_refill_rx_ring(alx, GFP_KERNEL))
558 static void alx_add_mc_addr(struct alx_hw *hw, const u8 *addr, u32 *mc_hash)
562 crc32 = ether_crc(ETH_ALEN, addr);
563 reg = (crc32 >> 31) & 0x1;
564 bit = (crc32 >> 26) & 0x1F;
566 mc_hash[reg] |= BIT(bit);
569 static void __alx_set_rx_mode(struct net_device *netdev)
571 struct alx_priv *alx = netdev_priv(netdev);
572 struct alx_hw *hw = &alx->hw;
573 struct netdev_hw_addr *ha;
576 if (!(netdev->flags & IFF_ALLMULTI)) {
577 netdev_for_each_mc_addr(ha, netdev)
578 alx_add_mc_addr(hw, ha->addr, mc_hash);
580 alx_write_mem32(hw, ALX_HASH_TBL0, mc_hash[0]);
581 alx_write_mem32(hw, ALX_HASH_TBL1, mc_hash[1]);
584 hw->rx_ctrl &= ~(ALX_MAC_CTRL_MULTIALL_EN | ALX_MAC_CTRL_PROMISC_EN);
585 if (netdev->flags & IFF_PROMISC)
586 hw->rx_ctrl |= ALX_MAC_CTRL_PROMISC_EN;
587 if (netdev->flags & IFF_ALLMULTI)
588 hw->rx_ctrl |= ALX_MAC_CTRL_MULTIALL_EN;
590 alx_write_mem32(hw, ALX_MAC_CTRL, hw->rx_ctrl);
593 static void alx_set_rx_mode(struct net_device *netdev)
595 __alx_set_rx_mode(netdev);
598 static int alx_set_mac_address(struct net_device *netdev, void *data)
600 struct alx_priv *alx = netdev_priv(netdev);
601 struct alx_hw *hw = &alx->hw;
602 struct sockaddr *addr = data;
604 if (!is_valid_ether_addr(addr->sa_data))
605 return -EADDRNOTAVAIL;
607 if (netdev->addr_assign_type & NET_ADDR_RANDOM)
608 netdev->addr_assign_type ^= NET_ADDR_RANDOM;
610 memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len);
611 memcpy(hw->mac_addr, addr->sa_data, netdev->addr_len);
612 alx_set_macaddr(hw, hw->mac_addr);
617 static int alx_alloc_tx_ring(struct alx_priv *alx, struct alx_tx_queue *txq,
620 txq->bufs = kcalloc(txq->count, sizeof(struct alx_buffer), GFP_KERNEL);
624 txq->tpd = alx->descmem.virt + offset;
625 txq->tpd_dma = alx->descmem.dma + offset;
626 offset += sizeof(struct alx_txd) * txq->count;
631 static int alx_alloc_rx_ring(struct alx_priv *alx, struct alx_rx_queue *rxq,
634 rxq->bufs = kcalloc(rxq->count, sizeof(struct alx_buffer), GFP_KERNEL);
638 rxq->rrd = alx->descmem.virt + offset;
639 rxq->rrd_dma = alx->descmem.dma + offset;
640 offset += sizeof(struct alx_rrd) * rxq->count;
642 rxq->rfd = alx->descmem.virt + offset;
643 rxq->rfd_dma = alx->descmem.dma + offset;
644 offset += sizeof(struct alx_rfd) * rxq->count;
649 static int alx_alloc_rings(struct alx_priv *alx)
653 /* physical tx/rx ring descriptors
655 * Allocate them as a single chunk because they must not cross a
656 * 4G boundary (hardware has a single register for high 32 bits
659 alx->descmem.size = sizeof(struct alx_txd) * alx->tx_ringsz *
661 sizeof(struct alx_rrd) * alx->rx_ringsz +
662 sizeof(struct alx_rfd) * alx->rx_ringsz;
663 alx->descmem.virt = dma_zalloc_coherent(&alx->hw.pdev->dev,
667 if (!alx->descmem.virt)
670 /* alignment requirements */
671 BUILD_BUG_ON(sizeof(struct alx_txd) % 8);
672 BUILD_BUG_ON(sizeof(struct alx_rrd) % 8);
674 for (i = 0; i < alx->num_txq; i++) {
675 offset = alx_alloc_tx_ring(alx, alx->qnapi[i]->txq, offset);
677 netdev_err(alx->dev, "Allocation of tx buffer failed!\n");
682 offset = alx_alloc_rx_ring(alx, alx->qnapi[0]->rxq, offset);
684 netdev_err(alx->dev, "Allocation of rx buffer failed!\n");
688 alx_reinit_rings(alx);
693 static void alx_free_rings(struct alx_priv *alx)
697 alx_free_buffers(alx);
699 for (i = 0; i < alx->num_txq; i++)
700 if (alx->qnapi[i] && alx->qnapi[i]->txq)
701 kfree(alx->qnapi[i]->txq->bufs);
703 if (alx->qnapi[0] && alx->qnapi[0]->rxq)
704 kfree(alx->qnapi[0]->rxq->bufs);
706 if (!alx->descmem.virt)
707 dma_free_coherent(&alx->hw.pdev->dev,
713 static void alx_free_napis(struct alx_priv *alx)
718 for (i = 0; i < alx->num_napi; i++) {
723 netif_napi_del(&np->napi);
727 alx->qnapi[i] = NULL;
731 static const u16 tx_pidx_reg[] = {ALX_TPD_PRI0_PIDX, ALX_TPD_PRI1_PIDX,
732 ALX_TPD_PRI2_PIDX, ALX_TPD_PRI3_PIDX};
733 static const u16 tx_cidx_reg[] = {ALX_TPD_PRI0_CIDX, ALX_TPD_PRI1_CIDX,
734 ALX_TPD_PRI2_CIDX, ALX_TPD_PRI3_CIDX};
735 static const u32 tx_vect_mask[] = {ALX_ISR_TX_Q0, ALX_ISR_TX_Q1,
736 ALX_ISR_TX_Q2, ALX_ISR_TX_Q3};
737 static const u32 rx_vect_mask[] = {ALX_ISR_RX_Q0, ALX_ISR_RX_Q1,
738 ALX_ISR_RX_Q2, ALX_ISR_RX_Q3,
739 ALX_ISR_RX_Q4, ALX_ISR_RX_Q5,
740 ALX_ISR_RX_Q6, ALX_ISR_RX_Q7};
742 static int alx_alloc_napis(struct alx_priv *alx)
745 struct alx_rx_queue *rxq;
746 struct alx_tx_queue *txq;
749 alx->int_mask &= ~ALX_ISR_ALL_QUEUES;
751 /* allocate alx_napi structures */
752 for (i = 0; i < alx->num_napi; i++) {
753 np = kzalloc(sizeof(struct alx_napi), GFP_KERNEL);
758 netif_napi_add(alx->dev, &np->napi, alx_poll, 64);
762 /* allocate tx queues */
763 for (i = 0; i < alx->num_txq; i++) {
765 txq = kzalloc(sizeof(*txq), GFP_KERNEL);
770 txq->p_reg = tx_pidx_reg[i];
771 txq->c_reg = tx_cidx_reg[i];
773 txq->count = alx->tx_ringsz;
774 txq->netdev = alx->dev;
775 txq->dev = &alx->hw.pdev->dev;
776 np->vec_mask |= tx_vect_mask[i];
777 alx->int_mask |= tx_vect_mask[i];
780 /* allocate rx queues */
782 rxq = kzalloc(sizeof(*rxq), GFP_KERNEL);
787 rxq->np = alx->qnapi[0];
789 rxq->count = alx->rx_ringsz;
790 rxq->netdev = alx->dev;
791 rxq->dev = &alx->hw.pdev->dev;
792 np->vec_mask |= rx_vect_mask[0];
793 alx->int_mask |= rx_vect_mask[0];
798 netdev_err(alx->dev, "error allocating internal structures\n");
803 static const int txq_vec_mapping_shift[] = {
804 0, ALX_MSI_MAP_TBL1_TXQ0_SHIFT,
805 0, ALX_MSI_MAP_TBL1_TXQ1_SHIFT,
806 1, ALX_MSI_MAP_TBL2_TXQ2_SHIFT,
807 1, ALX_MSI_MAP_TBL2_TXQ3_SHIFT,
810 static void alx_config_vector_mapping(struct alx_priv *alx)
812 struct alx_hw *hw = &alx->hw;
814 int i, vector, idx, shift;
816 if (alx->flags & ALX_FLAG_USING_MSIX) {
818 for (i = 0, vector = 1; i < alx->num_txq; i++, vector++) {
819 idx = txq_vec_mapping_shift[i * 2];
820 shift = txq_vec_mapping_shift[i * 2 + 1];
821 tbl[idx] |= vector << shift;
825 tbl[0] |= 1 << ALX_MSI_MAP_TBL1_RXQ0_SHIFT;
828 alx_write_mem32(hw, ALX_MSI_MAP_TBL1, tbl[0]);
829 alx_write_mem32(hw, ALX_MSI_MAP_TBL2, tbl[1]);
830 alx_write_mem32(hw, ALX_MSI_ID_MAP, 0);
833 static bool alx_enable_msix(struct alx_priv *alx)
835 int i, err, num_vec, num_txq, num_rxq;
837 num_txq = min_t(int, num_online_cpus(), ALX_MAX_TX_QUEUES);
839 num_vec = max_t(int, num_txq, num_rxq) + 1;
841 alx->msix_entries = kcalloc(num_vec, sizeof(struct msix_entry),
843 if (!alx->msix_entries) {
844 netdev_warn(alx->dev, "Allocation of msix entries failed!\n");
848 for (i = 0; i < num_vec; i++)
849 alx->msix_entries[i].entry = i;
851 err = pci_enable_msix(alx->hw.pdev, alx->msix_entries, num_vec);
853 kfree(alx->msix_entries);
854 netdev_warn(alx->dev, "Enabling MSI-X interrupts failed!\n");
858 alx->num_vec = num_vec;
859 alx->num_napi = num_vec - 1;
860 alx->num_txq = num_txq;
861 alx->num_rxq = num_rxq;
866 static int alx_request_msix(struct alx_priv *alx)
868 struct net_device *netdev = alx->dev;
869 int i, err, vector = 0, free_vector = 0;
871 err = request_irq(alx->msix_entries[0].vector, alx_intr_msix_misc,
872 0, netdev->name, alx);
876 for (i = 0; i < alx->num_napi; i++) {
877 struct alx_napi *np = alx->qnapi[i];
881 if (np->txq && np->rxq)
882 sprintf(np->irq_lbl, "%s-TxRx-%u", netdev->name,
885 sprintf(np->irq_lbl, "%s-tx-%u", netdev->name,
888 sprintf(np->irq_lbl, "%s-rx-%u", netdev->name,
891 sprintf(np->irq_lbl, "%s-unused", netdev->name);
893 np->vec_idx = vector;
894 err = request_irq(alx->msix_entries[vector].vector,
895 alx_intr_msix_ring, 0, np->irq_lbl, np);
902 free_irq(alx->msix_entries[free_vector++].vector, alx);
905 for (i = 0; i < vector; i++)
906 free_irq(alx->msix_entries[free_vector++].vector,
913 static void alx_init_intr(struct alx_priv *alx, bool msix)
916 if (alx_enable_msix(alx))
917 alx->flags |= ALX_FLAG_USING_MSIX;
920 if (!(alx->flags & ALX_FLAG_USING_MSIX)) {
926 if (!pci_enable_msi(alx->hw.pdev))
927 alx->flags |= ALX_FLAG_USING_MSI;
931 static void alx_disable_advanced_intr(struct alx_priv *alx)
933 if (alx->flags & ALX_FLAG_USING_MSIX) {
934 kfree(alx->msix_entries);
935 pci_disable_msix(alx->hw.pdev);
936 alx->flags &= ~ALX_FLAG_USING_MSIX;
939 if (alx->flags & ALX_FLAG_USING_MSI) {
940 pci_disable_msi(alx->hw.pdev);
941 alx->flags &= ~ALX_FLAG_USING_MSI;
945 static void alx_irq_enable(struct alx_priv *alx)
947 struct alx_hw *hw = &alx->hw;
950 /* level-1 interrupt switch */
951 alx_write_mem32(hw, ALX_ISR, 0);
952 alx_write_mem32(hw, ALX_IMR, alx->int_mask);
955 if (alx->flags & ALX_FLAG_USING_MSIX)
956 /* enable all msix irqs */
957 for (i = 0; i < alx->num_vec; i++)
958 alx_mask_msix(hw, i, false);
961 static void alx_irq_disable(struct alx_priv *alx)
963 struct alx_hw *hw = &alx->hw;
966 alx_write_mem32(hw, ALX_ISR, ALX_ISR_DIS);
967 alx_write_mem32(hw, ALX_IMR, 0);
970 if (alx->flags & ALX_FLAG_USING_MSIX) {
971 for (i = 0; i < alx->num_vec; i++) {
972 alx_mask_msix(hw, i, true);
973 synchronize_irq(alx->msix_entries[i].vector);
976 synchronize_irq(alx->hw.pdev->irq);
980 static int alx_realloc_resources(struct alx_priv *alx)
986 alx_disable_advanced_intr(alx);
988 err = alx_alloc_napis(alx);
992 err = alx_alloc_rings(alx);
999 static int alx_request_irq(struct alx_priv *alx)
1001 struct pci_dev *pdev = alx->hw.pdev;
1002 struct alx_hw *hw = &alx->hw;
1006 msi_ctrl = (hw->imt >> 1) << ALX_MSI_RETRANS_TM_SHIFT;
1008 if (alx->flags & ALX_FLAG_USING_MSIX) {
1009 alx_write_mem32(hw, ALX_MSI_RETRANS_TIMER, msi_ctrl);
1010 err = alx_request_msix(alx);
1014 /* msix request failed, realloc resources */
1015 err = alx_realloc_resources(alx);
1020 if (alx->flags & ALX_FLAG_USING_MSI) {
1021 alx_write_mem32(hw, ALX_MSI_RETRANS_TIMER,
1022 msi_ctrl | ALX_MSI_MASK_SEL_LINE);
1023 err = request_irq(pdev->irq, alx_intr_msi, 0,
1024 alx->dev->name, alx);
1027 /* fall back to legacy interrupt */
1028 alx->flags &= ~ALX_FLAG_USING_MSI;
1029 pci_disable_msi(alx->hw.pdev);
1032 alx_write_mem32(hw, ALX_MSI_RETRANS_TIMER, 0);
1033 err = request_irq(pdev->irq, alx_intr_legacy, IRQF_SHARED,
1034 alx->dev->name, alx);
1037 alx_config_vector_mapping(alx);
1039 netdev_err(alx->dev, "IRQ registration failed!\n");
1043 static void alx_free_irq(struct alx_priv *alx)
1045 struct pci_dev *pdev = alx->hw.pdev;
1048 if (alx->flags & ALX_FLAG_USING_MSIX) {
1049 free_irq(alx->msix_entries[vector++].vector, alx);
1050 for (i = 0; i < alx->num_napi; i++)
1051 free_irq(alx->msix_entries[vector++].vector,
1054 free_irq(pdev->irq, alx);
1057 alx_disable_advanced_intr(alx);
1060 static int alx_identify_hw(struct alx_priv *alx)
1062 struct alx_hw *hw = &alx->hw;
1063 int rev = alx_hw_revision(hw);
1065 if (rev > ALX_REV_C0)
1068 hw->max_dma_chnl = rev >= ALX_REV_B0 ? 4 : 2;
1073 static int alx_init_sw(struct alx_priv *alx)
1075 struct pci_dev *pdev = alx->hw.pdev;
1076 struct alx_hw *hw = &alx->hw;
1079 err = alx_identify_hw(alx);
1081 dev_err(&pdev->dev, "unrecognized chip, aborting\n");
1086 pdev->device == ALX_DEV_ID_AR8161 &&
1087 pdev->subsystem_vendor == PCI_VENDOR_ID_ATTANSIC &&
1088 pdev->subsystem_device == 0x0091 &&
1089 pdev->revision == 0;
1091 hw->smb_timer = 400;
1092 hw->mtu = alx->dev->mtu;
1093 alx->rxbuf_size = ALX_MAX_FRAME_LEN(hw->mtu);
1094 /* MTU range: 34 - 9256 */
1095 alx->dev->min_mtu = 34;
1096 alx->dev->max_mtu = ALX_MAX_FRAME_LEN(ALX_MAX_FRAME_SIZE);
1097 alx->tx_ringsz = 256;
1098 alx->rx_ringsz = 512;
1100 alx->int_mask = ALX_ISR_MISC;
1101 hw->dma_chnl = hw->max_dma_chnl;
1102 hw->ith_tpd = alx->tx_ringsz / 3;
1103 hw->link_speed = SPEED_UNKNOWN;
1104 hw->duplex = DUPLEX_UNKNOWN;
1105 hw->adv_cfg = ADVERTISED_Autoneg |
1106 ADVERTISED_10baseT_Half |
1107 ADVERTISED_10baseT_Full |
1108 ADVERTISED_100baseT_Full |
1109 ADVERTISED_100baseT_Half |
1110 ADVERTISED_1000baseT_Full;
1111 hw->flowctrl = ALX_FC_ANEG | ALX_FC_RX | ALX_FC_TX;
1113 hw->rx_ctrl = ALX_MAC_CTRL_WOLSPED_SWEN |
1114 ALX_MAC_CTRL_MHASH_ALG_HI5B |
1115 ALX_MAC_CTRL_BRD_EN |
1116 ALX_MAC_CTRL_PCRCE |
1118 ALX_MAC_CTRL_RXFC_EN |
1119 ALX_MAC_CTRL_TXFC_EN |
1120 7 << ALX_MAC_CTRL_PRMBLEN_SHIFT;
1126 static netdev_features_t alx_fix_features(struct net_device *netdev,
1127 netdev_features_t features)
1129 if (netdev->mtu > ALX_MAX_TSO_PKT_SIZE)
1130 features &= ~(NETIF_F_TSO | NETIF_F_TSO6);
1135 static void alx_netif_stop(struct alx_priv *alx)
1139 netif_trans_update(alx->dev);
1140 if (netif_carrier_ok(alx->dev)) {
1141 netif_carrier_off(alx->dev);
1142 netif_tx_disable(alx->dev);
1143 for (i = 0; i < alx->num_napi; i++)
1144 napi_disable(&alx->qnapi[i]->napi);
1148 static void alx_halt(struct alx_priv *alx)
1150 struct alx_hw *hw = &alx->hw;
1152 alx_netif_stop(alx);
1153 hw->link_speed = SPEED_UNKNOWN;
1154 hw->duplex = DUPLEX_UNKNOWN;
1158 /* disable l0s/l1 */
1159 alx_enable_aspm(hw, false, false);
1160 alx_irq_disable(alx);
1161 alx_free_buffers(alx);
1164 static void alx_configure(struct alx_priv *alx)
1166 struct alx_hw *hw = &alx->hw;
1168 alx_configure_basic(hw);
1169 alx_disable_rss(hw);
1170 __alx_set_rx_mode(alx->dev);
1172 alx_write_mem32(hw, ALX_MAC_CTRL, hw->rx_ctrl);
1175 static void alx_activate(struct alx_priv *alx)
1177 /* hardware setting lost, restore it */
1178 alx_reinit_rings(alx);
1181 /* clear old interrupts */
1182 alx_write_mem32(&alx->hw, ALX_ISR, ~(u32)ALX_ISR_DIS);
1184 alx_irq_enable(alx);
1186 alx_schedule_link_check(alx);
1189 static void alx_reinit(struct alx_priv *alx)
1197 static int alx_change_mtu(struct net_device *netdev, int mtu)
1199 struct alx_priv *alx = netdev_priv(netdev);
1200 int max_frame = ALX_MAX_FRAME_LEN(mtu);
1204 alx->rxbuf_size = max(max_frame, ALX_DEF_RXBUF_SIZE);
1205 netdev_update_features(netdev);
1206 if (netif_running(netdev))
1211 static void alx_netif_start(struct alx_priv *alx)
1215 netif_tx_wake_all_queues(alx->dev);
1216 for (i = 0; i < alx->num_napi; i++)
1217 napi_enable(&alx->qnapi[i]->napi);
1218 netif_carrier_on(alx->dev);
1221 static int __alx_open(struct alx_priv *alx, bool resume)
1225 alx_init_intr(alx, true);
1228 netif_carrier_off(alx->dev);
1230 err = alx_alloc_napis(alx);
1232 goto out_disable_adv_intr;
1234 err = alx_alloc_rings(alx);
1236 goto out_free_rings;
1240 err = alx_request_irq(alx);
1242 goto out_free_rings;
1244 netif_set_real_num_tx_queues(alx->dev, alx->num_txq);
1245 netif_set_real_num_rx_queues(alx->dev, alx->num_rxq);
1247 /* clear old interrupts */
1248 alx_write_mem32(&alx->hw, ALX_ISR, ~(u32)ALX_ISR_DIS);
1250 alx_irq_enable(alx);
1253 netif_tx_start_all_queues(alx->dev);
1255 alx_schedule_link_check(alx);
1259 alx_free_rings(alx);
1260 alx_free_napis(alx);
1261 out_disable_adv_intr:
1262 alx_disable_advanced_intr(alx);
1266 static void __alx_stop(struct alx_priv *alx)
1270 alx_free_rings(alx);
1271 alx_free_napis(alx);
1274 static const char *alx_speed_desc(struct alx_hw *hw)
1276 switch (alx_speed_to_ethadv(hw->link_speed, hw->duplex)) {
1277 case ADVERTISED_1000baseT_Full:
1278 return "1 Gbps Full";
1279 case ADVERTISED_100baseT_Full:
1280 return "100 Mbps Full";
1281 case ADVERTISED_100baseT_Half:
1282 return "100 Mbps Half";
1283 case ADVERTISED_10baseT_Full:
1284 return "10 Mbps Full";
1285 case ADVERTISED_10baseT_Half:
1286 return "10 Mbps Half";
1288 return "Unknown speed";
1292 static void alx_check_link(struct alx_priv *alx)
1294 struct alx_hw *hw = &alx->hw;
1295 unsigned long flags;
1300 /* clear PHY internal interrupt status, otherwise the main
1301 * interrupt status will be asserted forever
1303 alx_clear_phy_intr(hw);
1305 old_speed = hw->link_speed;
1306 old_duplex = hw->duplex;
1307 err = alx_read_phy_link(hw);
1311 spin_lock_irqsave(&alx->irq_lock, flags);
1312 alx->int_mask |= ALX_ISR_PHY;
1313 alx_write_mem32(hw, ALX_IMR, alx->int_mask);
1314 spin_unlock_irqrestore(&alx->irq_lock, flags);
1316 if (old_speed == hw->link_speed)
1319 if (hw->link_speed != SPEED_UNKNOWN) {
1320 netif_info(alx, link, alx->dev,
1321 "NIC Up: %s\n", alx_speed_desc(hw));
1322 alx_post_phy_link(hw);
1323 alx_enable_aspm(hw, true, true);
1326 if (old_speed == SPEED_UNKNOWN)
1327 alx_netif_start(alx);
1329 /* link is now down */
1330 alx_netif_stop(alx);
1331 netif_info(alx, link, alx->dev, "Link Down\n");
1332 err = alx_reset_mac(hw);
1335 alx_irq_disable(alx);
1337 /* MAC reset causes all HW settings to be lost, restore all */
1338 err = alx_reinit_rings(alx);
1342 alx_enable_aspm(hw, false, true);
1343 alx_post_phy_link(hw);
1344 alx_irq_enable(alx);
1350 alx_schedule_reset(alx);
1353 static int alx_open(struct net_device *netdev)
1355 return __alx_open(netdev_priv(netdev), false);
1358 static int alx_stop(struct net_device *netdev)
1360 __alx_stop(netdev_priv(netdev));
1364 static void alx_link_check(struct work_struct *work)
1366 struct alx_priv *alx;
1368 alx = container_of(work, struct alx_priv, link_check_wk);
1371 alx_check_link(alx);
1375 static void alx_reset(struct work_struct *work)
1377 struct alx_priv *alx = container_of(work, struct alx_priv, reset_wk);
1384 static int alx_tpd_req(struct sk_buff *skb)
1388 num = skb_shinfo(skb)->nr_frags + 1;
1389 /* we need one extra descriptor for LSOv2 */
1390 if (skb_is_gso(skb) && skb_shinfo(skb)->gso_type & SKB_GSO_TCPV6)
1396 static int alx_tx_csum(struct sk_buff *skb, struct alx_txd *first)
1400 if (skb->ip_summed != CHECKSUM_PARTIAL)
1403 cso = skb_checksum_start_offset(skb);
1407 css = cso + skb->csum_offset;
1408 first->word1 |= cpu_to_le32((cso >> 1) << TPD_CXSUMSTART_SHIFT);
1409 first->word1 |= cpu_to_le32((css >> 1) << TPD_CXSUMOFFSET_SHIFT);
1410 first->word1 |= cpu_to_le32(1 << TPD_CXSUM_EN_SHIFT);
1415 static int alx_tso(struct sk_buff *skb, struct alx_txd *first)
1419 if (skb->ip_summed != CHECKSUM_PARTIAL)
1422 if (!skb_is_gso(skb))
1425 err = skb_cow_head(skb, 0);
1429 if (skb->protocol == htons(ETH_P_IP)) {
1430 struct iphdr *iph = ip_hdr(skb);
1433 tcp_hdr(skb)->check = ~csum_tcpudp_magic(iph->saddr, iph->daddr,
1435 first->word1 |= 1 << TPD_IPV4_SHIFT;
1436 } else if (skb_is_gso_v6(skb)) {
1437 ipv6_hdr(skb)->payload_len = 0;
1438 tcp_hdr(skb)->check = ~csum_ipv6_magic(&ipv6_hdr(skb)->saddr,
1439 &ipv6_hdr(skb)->daddr,
1441 /* LSOv2: the first TPD only provides the packet length */
1442 first->adrl.l.pkt_len = skb->len;
1443 first->word1 |= 1 << TPD_LSO_V2_SHIFT;
1446 first->word1 |= 1 << TPD_LSO_EN_SHIFT;
1447 first->word1 |= (skb_transport_offset(skb) &
1448 TPD_L4HDROFFSET_MASK) << TPD_L4HDROFFSET_SHIFT;
1449 first->word1 |= (skb_shinfo(skb)->gso_size &
1450 TPD_MSS_MASK) << TPD_MSS_SHIFT;
1454 static int alx_map_tx_skb(struct alx_tx_queue *txq, struct sk_buff *skb)
1456 struct alx_txd *tpd, *first_tpd;
1458 int maplen, f, first_idx = txq->write_idx;
1460 first_tpd = &txq->tpd[txq->write_idx];
1463 if (tpd->word1 & (1 << TPD_LSO_V2_SHIFT)) {
1464 if (++txq->write_idx == txq->count)
1467 tpd = &txq->tpd[txq->write_idx];
1468 tpd->len = first_tpd->len;
1469 tpd->vlan_tag = first_tpd->vlan_tag;
1470 tpd->word1 = first_tpd->word1;
1473 maplen = skb_headlen(skb);
1474 dma = dma_map_single(txq->dev, skb->data, maplen,
1476 if (dma_mapping_error(txq->dev, dma))
1479 dma_unmap_len_set(&txq->bufs[txq->write_idx], size, maplen);
1480 dma_unmap_addr_set(&txq->bufs[txq->write_idx], dma, dma);
1482 tpd->adrl.addr = cpu_to_le64(dma);
1483 tpd->len = cpu_to_le16(maplen);
1485 for (f = 0; f < skb_shinfo(skb)->nr_frags; f++) {
1486 struct skb_frag_struct *frag;
1488 frag = &skb_shinfo(skb)->frags[f];
1490 if (++txq->write_idx == txq->count)
1492 tpd = &txq->tpd[txq->write_idx];
1494 tpd->word1 = first_tpd->word1;
1496 maplen = skb_frag_size(frag);
1497 dma = skb_frag_dma_map(txq->dev, frag, 0,
1498 maplen, DMA_TO_DEVICE);
1499 if (dma_mapping_error(txq->dev, dma))
1501 dma_unmap_len_set(&txq->bufs[txq->write_idx], size, maplen);
1502 dma_unmap_addr_set(&txq->bufs[txq->write_idx], dma, dma);
1504 tpd->adrl.addr = cpu_to_le64(dma);
1505 tpd->len = cpu_to_le16(maplen);
1508 /* last TPD, set EOP flag and store skb */
1509 tpd->word1 |= cpu_to_le32(1 << TPD_EOP_SHIFT);
1510 txq->bufs[txq->write_idx].skb = skb;
1512 if (++txq->write_idx == txq->count)
1519 while (f != txq->write_idx) {
1520 alx_free_txbuf(txq, f);
1521 if (++f == txq->count)
1527 static netdev_tx_t alx_start_xmit_ring(struct sk_buff *skb,
1528 struct alx_tx_queue *txq)
1530 struct alx_priv *alx;
1531 struct alx_txd *first;
1534 alx = netdev_priv(txq->netdev);
1536 if (alx_tpd_avail(txq) < alx_tpd_req(skb)) {
1537 netif_tx_stop_queue(alx_get_tx_queue(txq));
1541 first = &txq->tpd[txq->write_idx];
1542 memset(first, 0, sizeof(*first));
1544 tso = alx_tso(skb, first);
1547 else if (!tso && alx_tx_csum(skb, first))
1550 if (alx_map_tx_skb(txq, skb) < 0)
1553 netdev_tx_sent_queue(alx_get_tx_queue(txq), skb->len);
1555 /* flush updates before updating hardware */
1557 alx_write_mem16(&alx->hw, txq->p_reg, txq->write_idx);
1559 if (alx_tpd_avail(txq) < txq->count / 8)
1560 netif_tx_stop_queue(alx_get_tx_queue(txq));
1562 return NETDEV_TX_OK;
1565 dev_kfree_skb_any(skb);
1566 return NETDEV_TX_OK;
1569 static netdev_tx_t alx_start_xmit(struct sk_buff *skb,
1570 struct net_device *netdev)
1572 struct alx_priv *alx = netdev_priv(netdev);
1573 return alx_start_xmit_ring(skb, alx_tx_queue_mapping(alx, skb));
1576 static void alx_tx_timeout(struct net_device *dev)
1578 struct alx_priv *alx = netdev_priv(dev);
1580 alx_schedule_reset(alx);
1583 static int alx_mdio_read(struct net_device *netdev,
1584 int prtad, int devad, u16 addr)
1586 struct alx_priv *alx = netdev_priv(netdev);
1587 struct alx_hw *hw = &alx->hw;
1591 if (prtad != hw->mdio.prtad)
1594 if (devad == MDIO_DEVAD_NONE)
1595 err = alx_read_phy_reg(hw, addr, &val);
1597 err = alx_read_phy_ext(hw, devad, addr, &val);
1604 static int alx_mdio_write(struct net_device *netdev,
1605 int prtad, int devad, u16 addr, u16 val)
1607 struct alx_priv *alx = netdev_priv(netdev);
1608 struct alx_hw *hw = &alx->hw;
1610 if (prtad != hw->mdio.prtad)
1613 if (devad == MDIO_DEVAD_NONE)
1614 return alx_write_phy_reg(hw, addr, val);
1616 return alx_write_phy_ext(hw, devad, addr, val);
1619 static int alx_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd)
1621 struct alx_priv *alx = netdev_priv(netdev);
1623 if (!netif_running(netdev))
1626 return mdio_mii_ioctl(&alx->hw.mdio, if_mii(ifr), cmd);
1629 #ifdef CONFIG_NET_POLL_CONTROLLER
1630 static void alx_poll_controller(struct net_device *netdev)
1632 struct alx_priv *alx = netdev_priv(netdev);
1635 if (alx->flags & ALX_FLAG_USING_MSIX) {
1636 alx_intr_msix_misc(0, alx);
1637 for (i = 0; i < alx->num_txq; i++)
1638 alx_intr_msix_ring(0, alx->qnapi[i]);
1639 } else if (alx->flags & ALX_FLAG_USING_MSI)
1640 alx_intr_msi(0, alx);
1642 alx_intr_legacy(0, alx);
1646 static struct rtnl_link_stats64 *alx_get_stats64(struct net_device *dev,
1647 struct rtnl_link_stats64 *net_stats)
1649 struct alx_priv *alx = netdev_priv(dev);
1650 struct alx_hw_stats *hw_stats = &alx->hw.stats;
1652 spin_lock(&alx->stats_lock);
1654 alx_update_hw_stats(&alx->hw);
1656 net_stats->tx_bytes = hw_stats->tx_byte_cnt;
1657 net_stats->rx_bytes = hw_stats->rx_byte_cnt;
1658 net_stats->multicast = hw_stats->rx_mcast;
1659 net_stats->collisions = hw_stats->tx_single_col +
1660 hw_stats->tx_multi_col +
1661 hw_stats->tx_late_col +
1662 hw_stats->tx_abort_col;
1664 net_stats->rx_errors = hw_stats->rx_frag +
1665 hw_stats->rx_fcs_err +
1666 hw_stats->rx_len_err +
1667 hw_stats->rx_ov_sz +
1668 hw_stats->rx_ov_rrd +
1669 hw_stats->rx_align_err +
1670 hw_stats->rx_ov_rxf;
1672 net_stats->rx_fifo_errors = hw_stats->rx_ov_rxf;
1673 net_stats->rx_length_errors = hw_stats->rx_len_err;
1674 net_stats->rx_crc_errors = hw_stats->rx_fcs_err;
1675 net_stats->rx_frame_errors = hw_stats->rx_align_err;
1676 net_stats->rx_dropped = hw_stats->rx_ov_rrd;
1678 net_stats->tx_errors = hw_stats->tx_late_col +
1679 hw_stats->tx_abort_col +
1680 hw_stats->tx_underrun +
1683 net_stats->tx_aborted_errors = hw_stats->tx_abort_col;
1684 net_stats->tx_fifo_errors = hw_stats->tx_underrun;
1685 net_stats->tx_window_errors = hw_stats->tx_late_col;
1687 net_stats->tx_packets = hw_stats->tx_ok + net_stats->tx_errors;
1688 net_stats->rx_packets = hw_stats->rx_ok + net_stats->rx_errors;
1690 spin_unlock(&alx->stats_lock);
1695 static const struct net_device_ops alx_netdev_ops = {
1696 .ndo_open = alx_open,
1697 .ndo_stop = alx_stop,
1698 .ndo_start_xmit = alx_start_xmit,
1699 .ndo_get_stats64 = alx_get_stats64,
1700 .ndo_set_rx_mode = alx_set_rx_mode,
1701 .ndo_validate_addr = eth_validate_addr,
1702 .ndo_set_mac_address = alx_set_mac_address,
1703 .ndo_change_mtu = alx_change_mtu,
1704 .ndo_do_ioctl = alx_ioctl,
1705 .ndo_tx_timeout = alx_tx_timeout,
1706 .ndo_fix_features = alx_fix_features,
1707 #ifdef CONFIG_NET_POLL_CONTROLLER
1708 .ndo_poll_controller = alx_poll_controller,
1712 static int alx_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
1714 struct net_device *netdev;
1715 struct alx_priv *alx;
1717 bool phy_configured;
1720 err = pci_enable_device_mem(pdev);
1724 /* The alx chip can DMA to 64-bit addresses, but it uses a single
1725 * shared register for the high 32 bits, so only a single, aligned,
1726 * 4 GB physical address range can be used for descriptors.
1728 if (!dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64))) {
1729 dev_dbg(&pdev->dev, "DMA to 64-BIT addresses\n");
1731 err = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32));
1733 dev_err(&pdev->dev, "No usable DMA config, aborting\n");
1734 goto out_pci_disable;
1738 err = pci_request_mem_regions(pdev, alx_drv_name);
1741 "pci_request_mem_regions failed\n");
1742 goto out_pci_disable;
1745 pci_enable_pcie_error_reporting(pdev);
1746 pci_set_master(pdev);
1748 if (!pdev->pm_cap) {
1750 "Can't find power management capability, aborting\n");
1752 goto out_pci_release;
1755 netdev = alloc_etherdev_mqs(sizeof(*alx),
1756 ALX_MAX_TX_QUEUES, 1);
1759 goto out_pci_release;
1762 SET_NETDEV_DEV(netdev, &pdev->dev);
1763 alx = netdev_priv(netdev);
1764 spin_lock_init(&alx->hw.mdio_lock);
1765 spin_lock_init(&alx->irq_lock);
1766 spin_lock_init(&alx->stats_lock);
1768 alx->hw.pdev = pdev;
1769 alx->msg_enable = NETIF_MSG_LINK | NETIF_MSG_HW | NETIF_MSG_IFUP |
1770 NETIF_MSG_TX_ERR | NETIF_MSG_RX_ERR | NETIF_MSG_WOL;
1772 pci_set_drvdata(pdev, alx);
1774 hw->hw_addr = pci_ioremap_bar(pdev, 0);
1776 dev_err(&pdev->dev, "cannot map device registers\n");
1778 goto out_free_netdev;
1781 netdev->netdev_ops = &alx_netdev_ops;
1782 netdev->ethtool_ops = &alx_ethtool_ops;
1783 netdev->irq = pdev->irq;
1784 netdev->watchdog_timeo = ALX_WATCHDOG_TIME;
1786 if (ent->driver_data & ALX_DEV_QUIRK_MSI_INTX_DISABLE_BUG)
1787 pdev->dev_flags |= PCI_DEV_FLAGS_MSI_INTX_DISABLE_BUG;
1789 err = alx_init_sw(alx);
1791 dev_err(&pdev->dev, "net device private data init failed\n");
1797 phy_configured = alx_phy_configured(hw);
1799 if (!phy_configured)
1802 err = alx_reset_mac(hw);
1804 dev_err(&pdev->dev, "MAC Reset failed, error = %d\n", err);
1808 /* setup link to put it in a known good starting state */
1809 if (!phy_configured) {
1810 err = alx_setup_speed_duplex(hw, hw->adv_cfg, hw->flowctrl);
1813 "failed to configure PHY speed/duplex (err=%d)\n",
1819 netdev->hw_features = NETIF_F_SG |
1824 if (alx_get_perm_macaddr(hw, hw->perm_addr)) {
1825 dev_warn(&pdev->dev,
1826 "Invalid permanent address programmed, using random one\n");
1827 eth_hw_addr_random(netdev);
1828 memcpy(hw->perm_addr, netdev->dev_addr, netdev->addr_len);
1831 memcpy(hw->mac_addr, hw->perm_addr, ETH_ALEN);
1832 memcpy(netdev->dev_addr, hw->mac_addr, ETH_ALEN);
1833 memcpy(netdev->perm_addr, hw->perm_addr, ETH_ALEN);
1837 hw->mdio.dev = netdev;
1838 hw->mdio.mode_support = MDIO_SUPPORTS_C45 |
1841 hw->mdio.mdio_read = alx_mdio_read;
1842 hw->mdio.mdio_write = alx_mdio_write;
1844 if (!alx_get_phy_info(hw)) {
1845 dev_err(&pdev->dev, "failed to identify PHY\n");
1850 INIT_WORK(&alx->link_check_wk, alx_link_check);
1851 INIT_WORK(&alx->reset_wk, alx_reset);
1852 netif_carrier_off(netdev);
1854 err = register_netdev(netdev);
1856 dev_err(&pdev->dev, "register netdevice failed\n");
1861 "Qualcomm Atheros AR816x/AR817x Ethernet [%pM]\n",
1867 iounmap(hw->hw_addr);
1869 free_netdev(netdev);
1871 pci_release_mem_regions(pdev);
1873 pci_disable_device(pdev);
1877 static void alx_remove(struct pci_dev *pdev)
1879 struct alx_priv *alx = pci_get_drvdata(pdev);
1880 struct alx_hw *hw = &alx->hw;
1882 cancel_work_sync(&alx->link_check_wk);
1883 cancel_work_sync(&alx->reset_wk);
1885 /* restore permanent mac address */
1886 alx_set_macaddr(hw, hw->perm_addr);
1888 unregister_netdev(alx->dev);
1889 iounmap(hw->hw_addr);
1890 pci_release_mem_regions(pdev);
1892 pci_disable_pcie_error_reporting(pdev);
1893 pci_disable_device(pdev);
1895 free_netdev(alx->dev);
1898 #ifdef CONFIG_PM_SLEEP
1899 static int alx_suspend(struct device *dev)
1901 struct pci_dev *pdev = to_pci_dev(dev);
1902 struct alx_priv *alx = pci_get_drvdata(pdev);
1904 if (!netif_running(alx->dev))
1906 netif_device_detach(alx->dev);
1911 static int alx_resume(struct device *dev)
1913 struct pci_dev *pdev = to_pci_dev(dev);
1914 struct alx_priv *alx = pci_get_drvdata(pdev);
1915 struct alx_hw *hw = &alx->hw;
1919 if (!netif_running(alx->dev))
1921 netif_device_attach(alx->dev);
1922 return __alx_open(alx, true);
1925 static SIMPLE_DEV_PM_OPS(alx_pm_ops, alx_suspend, alx_resume);
1926 #define ALX_PM_OPS (&alx_pm_ops)
1928 #define ALX_PM_OPS NULL
1932 static pci_ers_result_t alx_pci_error_detected(struct pci_dev *pdev,
1933 pci_channel_state_t state)
1935 struct alx_priv *alx = pci_get_drvdata(pdev);
1936 struct net_device *netdev = alx->dev;
1937 pci_ers_result_t rc = PCI_ERS_RESULT_NEED_RESET;
1939 dev_info(&pdev->dev, "pci error detected\n");
1943 if (netif_running(netdev)) {
1944 netif_device_detach(netdev);
1948 if (state == pci_channel_io_perm_failure)
1949 rc = PCI_ERS_RESULT_DISCONNECT;
1951 pci_disable_device(pdev);
1958 static pci_ers_result_t alx_pci_error_slot_reset(struct pci_dev *pdev)
1960 struct alx_priv *alx = pci_get_drvdata(pdev);
1961 struct alx_hw *hw = &alx->hw;
1962 pci_ers_result_t rc = PCI_ERS_RESULT_DISCONNECT;
1964 dev_info(&pdev->dev, "pci error slot reset\n");
1968 if (pci_enable_device(pdev)) {
1969 dev_err(&pdev->dev, "Failed to re-enable PCI device after reset\n");
1973 pci_set_master(pdev);
1976 if (!alx_reset_mac(hw))
1977 rc = PCI_ERS_RESULT_RECOVERED;
1979 pci_cleanup_aer_uncorrect_error_status(pdev);
1986 static void alx_pci_error_resume(struct pci_dev *pdev)
1988 struct alx_priv *alx = pci_get_drvdata(pdev);
1989 struct net_device *netdev = alx->dev;
1991 dev_info(&pdev->dev, "pci error resume\n");
1995 if (netif_running(netdev)) {
1997 netif_device_attach(netdev);
2003 static const struct pci_error_handlers alx_err_handlers = {
2004 .error_detected = alx_pci_error_detected,
2005 .slot_reset = alx_pci_error_slot_reset,
2006 .resume = alx_pci_error_resume,
2009 static const struct pci_device_id alx_pci_tbl[] = {
2010 { PCI_VDEVICE(ATTANSIC, ALX_DEV_ID_AR8161),
2011 .driver_data = ALX_DEV_QUIRK_MSI_INTX_DISABLE_BUG },
2012 { PCI_VDEVICE(ATTANSIC, ALX_DEV_ID_E2200),
2013 .driver_data = ALX_DEV_QUIRK_MSI_INTX_DISABLE_BUG },
2014 { PCI_VDEVICE(ATTANSIC, ALX_DEV_ID_E2400),
2015 .driver_data = ALX_DEV_QUIRK_MSI_INTX_DISABLE_BUG },
2016 { PCI_VDEVICE(ATTANSIC, ALX_DEV_ID_E2500),
2017 .driver_data = ALX_DEV_QUIRK_MSI_INTX_DISABLE_BUG },
2018 { PCI_VDEVICE(ATTANSIC, ALX_DEV_ID_AR8162),
2019 .driver_data = ALX_DEV_QUIRK_MSI_INTX_DISABLE_BUG },
2020 { PCI_VDEVICE(ATTANSIC, ALX_DEV_ID_AR8171) },
2021 { PCI_VDEVICE(ATTANSIC, ALX_DEV_ID_AR8172) },
2025 static struct pci_driver alx_driver = {
2026 .name = alx_drv_name,
2027 .id_table = alx_pci_tbl,
2029 .remove = alx_remove,
2030 .err_handler = &alx_err_handlers,
2031 .driver.pm = ALX_PM_OPS,
2034 module_pci_driver(alx_driver);
2035 MODULE_DEVICE_TABLE(pci, alx_pci_tbl);
2036 MODULE_AUTHOR("Johannes Berg <johannes@sipsolutions.net>");
2037 MODULE_AUTHOR("Qualcomm Corporation, <nic-devel@qualcomm.com>");
2039 "Qualcomm Atheros(R) AR816x/AR817x PCI-E Ethernet Network Driver");
2040 MODULE_LICENSE("GPL");