1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * aQuantia Corporation Network Driver
4 * Copyright (C) 2014-2017 aQuantia Corporation. All rights reserved
7 /* File hw_atl_llh_internal.h: Preprocessor definitions
8 * for Atlantic registers.
11 #ifndef HW_ATL_LLH_INTERNAL_H
12 #define HW_ATL_LLH_INTERNAL_H
14 /* global microprocessor semaphore definitions
15 * base address: 0x000003a0
16 * parameter: semaphore {s} | stride size 0x4 | range [0, 15]
18 #define HW_ATL_GLB_CPU_SEM_ADR(semaphore) (0x000003a0u + (semaphore) * 0x4)
19 /* register address for bitfield rx dma good octet counter lsw [1f:0] */
20 #define HW_ATL_STATS_RX_DMA_GOOD_OCTET_COUNTERLSW 0x00006808
21 /* register address for bitfield rx dma good packet counter lsw [1f:0] */
22 #define HW_ATL_STATS_RX_DMA_GOOD_PKT_COUNTERLSW 0x00006800
23 /* register address for bitfield tx dma good octet counter lsw [1f:0] */
24 #define HW_ATL_STATS_TX_DMA_GOOD_OCTET_COUNTERLSW 0x00008808
25 /* register address for bitfield tx dma good packet counter lsw [1f:0] */
26 #define HW_ATL_STATS_TX_DMA_GOOD_PKT_COUNTERLSW 0x00008800
28 /* register address for bitfield rx dma good octet counter msw [3f:20] */
29 #define HW_ATL_STATS_RX_DMA_GOOD_OCTET_COUNTERMSW 0x0000680c
30 /* register address for bitfield rx dma good packet counter msw [3f:20] */
31 #define HW_ATL_STATS_RX_DMA_GOOD_PKT_COUNTERMSW 0x00006804
32 /* register address for bitfield tx dma good octet counter msw [3f:20] */
33 #define HW_ATL_STATS_TX_DMA_GOOD_OCTET_COUNTERMSW 0x0000880c
34 /* register address for bitfield tx dma good packet counter msw [3f:20] */
35 #define HW_ATL_STATS_TX_DMA_GOOD_PKT_COUNTERMSW 0x00008804
37 /* preprocessor definitions for msm rx errors counter register */
38 #define HW_ATL_MAC_MSM_RX_ERRS_CNT_ADR 0x00000120u
40 /* preprocessor definitions for msm rx unicast frames counter register */
41 #define HW_ATL_MAC_MSM_RX_UCST_FRM_CNT_ADR 0x000000e0u
43 /* preprocessor definitions for msm rx multicast frames counter register */
44 #define HW_ATL_MAC_MSM_RX_MCST_FRM_CNT_ADR 0x000000e8u
46 /* preprocessor definitions for msm rx broadcast frames counter register */
47 #define HW_ATL_MAC_MSM_RX_BCST_FRM_CNT_ADR 0x000000f0u
49 /* preprocessor definitions for msm rx broadcast octets counter register 1 */
50 #define HW_ATL_MAC_MSM_RX_BCST_OCTETS_COUNTER1_ADR 0x000001b0u
52 /* preprocessor definitions for msm rx broadcast octets counter register 2 */
53 #define HW_ATL_MAC_MSM_RX_BCST_OCTETS_COUNTER2_ADR 0x000001b4u
55 /* preprocessor definitions for msm rx unicast octets counter register 0 */
56 #define HW_ATL_MAC_MSM_RX_UCST_OCTETS_COUNTER0_ADR 0x000001b8u
58 /* preprocessor definitions for msm tx unicast frames counter register */
59 #define HW_ATL_MAC_MSM_TX_UCST_FRM_CNT_ADR 0x00000108u
61 /* preprocessor definitions for msm tx multicast frames counter register */
62 #define HW_ATL_MAC_MSM_TX_MCST_FRM_CNT_ADR 0x00000110u
64 /* preprocessor definitions for global mif identification */
65 #define HW_ATL_GLB_MIF_ID_ADR 0x0000001cu
67 /* register address for bitfield iamr_lsw[1f:0] */
68 #define HW_ATL_ITR_IAMRLSW_ADR 0x00002090
69 /* register address for bitfield rx dma drop packet counter [1f:0] */
70 #define HW_ATL_RPB_RX_DMA_DROP_PKT_CNT_ADR 0x00006818
72 /* register address for bitfield imcr_lsw[1f:0] */
73 #define HW_ATL_ITR_IMCRLSW_ADR 0x00002070
74 /* register address for bitfield imsr_lsw[1f:0] */
75 #define HW_ATL_ITR_IMSRLSW_ADR 0x00002060
76 /* register address for bitfield itr_reg_res_dsbl */
77 #define HW_ATL_ITR_REG_RES_DSBL_ADR 0x00002300
78 /* bitmask for bitfield itr_reg_res_dsbl */
79 #define HW_ATL_ITR_REG_RES_DSBL_MSK 0x20000000
80 /* lower bit position of bitfield itr_reg_res_dsbl */
81 #define HW_ATL_ITR_REG_RES_DSBL_SHIFT 29
82 /* register address for bitfield iscr_lsw[1f:0] */
83 #define HW_ATL_ITR_ISCRLSW_ADR 0x00002050
84 /* register address for bitfield isr_lsw[1f:0] */
85 #define HW_ATL_ITR_ISRLSW_ADR 0x00002000
86 /* register address for bitfield itr_reset */
87 #define HW_ATL_ITR_RES_ADR 0x00002300
88 /* bitmask for bitfield itr_reset */
89 #define HW_ATL_ITR_RES_MSK 0x80000000
90 /* lower bit position of bitfield itr_reset */
91 #define HW_ATL_ITR_RES_SHIFT 31
93 /* register address for bitfield rsc_en */
94 #define HW_ATL_ITR_RSC_EN_ADR 0x00002200
96 /* register address for bitfield rsc_delay */
97 #define HW_ATL_ITR_RSC_DELAY_ADR 0x00002204
98 /* bitmask for bitfield rsc_delay */
99 #define HW_ATL_ITR_RSC_DELAY_MSK 0x0000000f
100 /* width of bitfield rsc_delay */
101 #define HW_ATL_ITR_RSC_DELAY_WIDTH 4
102 /* lower bit position of bitfield rsc_delay */
103 #define HW_ATL_ITR_RSC_DELAY_SHIFT 0
105 /* register address for bitfield dca{d}_cpuid[7:0] */
106 #define HW_ATL_RDM_DCADCPUID_ADR(dca) (0x00006100 + (dca) * 0x4)
107 /* bitmask for bitfield dca{d}_cpuid[7:0] */
108 #define HW_ATL_RDM_DCADCPUID_MSK 0x000000ff
109 /* lower bit position of bitfield dca{d}_cpuid[7:0] */
110 #define HW_ATL_RDM_DCADCPUID_SHIFT 0
111 /* register address for bitfield dca_en */
112 #define HW_ATL_RDM_DCA_EN_ADR 0x00006180
114 /* rx dca_en bitfield definitions
115 * preprocessor definitions for the bitfield "dca_en".
116 * port="pif_rdm_dca_en_i"
119 /* register address for bitfield dca_en */
120 #define HW_ATL_RDM_DCA_EN_ADR 0x00006180
121 /* bitmask for bitfield dca_en */
122 #define HW_ATL_RDM_DCA_EN_MSK 0x80000000
123 /* inverted bitmask for bitfield dca_en */
124 #define HW_ATL_RDM_DCA_EN_MSKN 0x7fffffff
125 /* lower bit position of bitfield dca_en */
126 #define HW_ATL_RDM_DCA_EN_SHIFT 31
127 /* width of bitfield dca_en */
128 #define HW_ATL_RDM_DCA_EN_WIDTH 1
129 /* default value of bitfield dca_en */
130 #define HW_ATL_RDM_DCA_EN_DEFAULT 0x1
132 /* rx dca_mode[3:0] bitfield definitions
133 * preprocessor definitions for the bitfield "dca_mode[3:0]".
134 * port="pif_rdm_dca_mode_i[3:0]"
137 /* register address for bitfield dca_mode[3:0] */
138 #define HW_ATL_RDM_DCA_MODE_ADR 0x00006180
139 /* bitmask for bitfield dca_mode[3:0] */
140 #define HW_ATL_RDM_DCA_MODE_MSK 0x0000000f
141 /* inverted bitmask for bitfield dca_mode[3:0] */
142 #define HW_ATL_RDM_DCA_MODE_MSKN 0xfffffff0
143 /* lower bit position of bitfield dca_mode[3:0] */
144 #define HW_ATL_RDM_DCA_MODE_SHIFT 0
145 /* width of bitfield dca_mode[3:0] */
146 #define HW_ATL_RDM_DCA_MODE_WIDTH 4
147 /* default value of bitfield dca_mode[3:0] */
148 #define HW_ATL_RDM_DCA_MODE_DEFAULT 0x0
150 /* rx desc{d}_data_size[4:0] bitfield definitions
151 * preprocessor definitions for the bitfield "desc{d}_data_size[4:0]".
152 * parameter: descriptor {d} | stride size 0x20 | range [0, 31]
153 * port="pif_rdm_desc0_data_size_i[4:0]"
156 /* register address for bitfield desc{d}_data_size[4:0] */
157 #define HW_ATL_RDM_DESCDDATA_SIZE_ADR(descriptor) \
158 (0x00005b18 + (descriptor) * 0x20)
159 /* bitmask for bitfield desc{d}_data_size[4:0] */
160 #define HW_ATL_RDM_DESCDDATA_SIZE_MSK 0x0000001f
161 /* inverted bitmask for bitfield desc{d}_data_size[4:0] */
162 #define HW_ATL_RDM_DESCDDATA_SIZE_MSKN 0xffffffe0
163 /* lower bit position of bitfield desc{d}_data_size[4:0] */
164 #define HW_ATL_RDM_DESCDDATA_SIZE_SHIFT 0
165 /* width of bitfield desc{d}_data_size[4:0] */
166 #define HW_ATL_RDM_DESCDDATA_SIZE_WIDTH 5
167 /* default value of bitfield desc{d}_data_size[4:0] */
168 #define HW_ATL_RDM_DESCDDATA_SIZE_DEFAULT 0x0
170 /* rx dca{d}_desc_en bitfield definitions
171 * preprocessor definitions for the bitfield "dca{d}_desc_en".
172 * parameter: dca {d} | stride size 0x4 | range [0, 31]
173 * port="pif_rdm_dca_desc_en_i[0]"
176 /* register address for bitfield dca{d}_desc_en */
177 #define HW_ATL_RDM_DCADDESC_EN_ADR(dca) (0x00006100 + (dca) * 0x4)
178 /* bitmask for bitfield dca{d}_desc_en */
179 #define HW_ATL_RDM_DCADDESC_EN_MSK 0x80000000
180 /* inverted bitmask for bitfield dca{d}_desc_en */
181 #define HW_ATL_RDM_DCADDESC_EN_MSKN 0x7fffffff
182 /* lower bit position of bitfield dca{d}_desc_en */
183 #define HW_ATL_RDM_DCADDESC_EN_SHIFT 31
184 /* width of bitfield dca{d}_desc_en */
185 #define HW_ATL_RDM_DCADDESC_EN_WIDTH 1
186 /* default value of bitfield dca{d}_desc_en */
187 #define HW_ATL_RDM_DCADDESC_EN_DEFAULT 0x0
189 /* rx desc{d}_en bitfield definitions
190 * preprocessor definitions for the bitfield "desc{d}_en".
191 * parameter: descriptor {d} | stride size 0x20 | range [0, 31]
192 * port="pif_rdm_desc_en_i[0]"
195 /* register address for bitfield desc{d}_en */
196 #define HW_ATL_RDM_DESCDEN_ADR(descriptor) (0x00005b08 + (descriptor) * 0x20)
197 /* bitmask for bitfield desc{d}_en */
198 #define HW_ATL_RDM_DESCDEN_MSK 0x80000000
199 /* inverted bitmask for bitfield desc{d}_en */
200 #define HW_ATL_RDM_DESCDEN_MSKN 0x7fffffff
201 /* lower bit position of bitfield desc{d}_en */
202 #define HW_ATL_RDM_DESCDEN_SHIFT 31
203 /* width of bitfield desc{d}_en */
204 #define HW_ATL_RDM_DESCDEN_WIDTH 1
205 /* default value of bitfield desc{d}_en */
206 #define HW_ATL_RDM_DESCDEN_DEFAULT 0x0
208 /* rx desc{d}_hdr_size[4:0] bitfield definitions
209 * preprocessor definitions for the bitfield "desc{d}_hdr_size[4:0]".
210 * parameter: descriptor {d} | stride size 0x20 | range [0, 31]
211 * port="pif_rdm_desc0_hdr_size_i[4:0]"
214 /* register address for bitfield desc{d}_hdr_size[4:0] */
215 #define HW_ATL_RDM_DESCDHDR_SIZE_ADR(descriptor) \
216 (0x00005b18 + (descriptor) * 0x20)
217 /* bitmask for bitfield desc{d}_hdr_size[4:0] */
218 #define HW_ATL_RDM_DESCDHDR_SIZE_MSK 0x00001f00
219 /* inverted bitmask for bitfield desc{d}_hdr_size[4:0] */
220 #define HW_ATL_RDM_DESCDHDR_SIZE_MSKN 0xffffe0ff
221 /* lower bit position of bitfield desc{d}_hdr_size[4:0] */
222 #define HW_ATL_RDM_DESCDHDR_SIZE_SHIFT 8
223 /* width of bitfield desc{d}_hdr_size[4:0] */
224 #define HW_ATL_RDM_DESCDHDR_SIZE_WIDTH 5
225 /* default value of bitfield desc{d}_hdr_size[4:0] */
226 #define HW_ATL_RDM_DESCDHDR_SIZE_DEFAULT 0x0
228 /* rx desc{d}_hdr_split bitfield definitions
229 * preprocessor definitions for the bitfield "desc{d}_hdr_split".
230 * parameter: descriptor {d} | stride size 0x20 | range [0, 31]
231 * port="pif_rdm_desc_hdr_split_i[0]"
234 /* register address for bitfield desc{d}_hdr_split */
235 #define HW_ATL_RDM_DESCDHDR_SPLIT_ADR(descriptor) \
236 (0x00005b08 + (descriptor) * 0x20)
237 /* bitmask for bitfield desc{d}_hdr_split */
238 #define HW_ATL_RDM_DESCDHDR_SPLIT_MSK 0x10000000
239 /* inverted bitmask for bitfield desc{d}_hdr_split */
240 #define HW_ATL_RDM_DESCDHDR_SPLIT_MSKN 0xefffffff
241 /* lower bit position of bitfield desc{d}_hdr_split */
242 #define HW_ATL_RDM_DESCDHDR_SPLIT_SHIFT 28
243 /* width of bitfield desc{d}_hdr_split */
244 #define HW_ATL_RDM_DESCDHDR_SPLIT_WIDTH 1
245 /* default value of bitfield desc{d}_hdr_split */
246 #define HW_ATL_RDM_DESCDHDR_SPLIT_DEFAULT 0x0
248 /* rx desc{d}_hd[c:0] bitfield definitions
249 * preprocessor definitions for the bitfield "desc{d}_hd[c:0]".
250 * parameter: descriptor {d} | stride size 0x20 | range [0, 31]
251 * port="rdm_pif_desc0_hd_o[12:0]"
254 /* register address for bitfield desc{d}_hd[c:0] */
255 #define HW_ATL_RDM_DESCDHD_ADR(descriptor) (0x00005b0c + (descriptor) * 0x20)
256 /* bitmask for bitfield desc{d}_hd[c:0] */
257 #define HW_ATL_RDM_DESCDHD_MSK 0x00001fff
258 /* inverted bitmask for bitfield desc{d}_hd[c:0] */
259 #define HW_ATL_RDM_DESCDHD_MSKN 0xffffe000
260 /* lower bit position of bitfield desc{d}_hd[c:0] */
261 #define HW_ATL_RDM_DESCDHD_SHIFT 0
262 /* width of bitfield desc{d}_hd[c:0] */
263 #define HW_ATL_RDM_DESCDHD_WIDTH 13
265 /* rx desc{d}_len[9:0] bitfield definitions
266 * preprocessor definitions for the bitfield "desc{d}_len[9:0]".
267 * parameter: descriptor {d} | stride size 0x20 | range [0, 31]
268 * port="pif_rdm_desc0_len_i[9:0]"
271 /* register address for bitfield desc{d}_len[9:0] */
272 #define HW_ATL_RDM_DESCDLEN_ADR(descriptor) (0x00005b08 + (descriptor) * 0x20)
273 /* bitmask for bitfield desc{d}_len[9:0] */
274 #define HW_ATL_RDM_DESCDLEN_MSK 0x00001ff8
275 /* inverted bitmask for bitfield desc{d}_len[9:0] */
276 #define HW_ATL_RDM_DESCDLEN_MSKN 0xffffe007
277 /* lower bit position of bitfield desc{d}_len[9:0] */
278 #define HW_ATL_RDM_DESCDLEN_SHIFT 3
279 /* width of bitfield desc{d}_len[9:0] */
280 #define HW_ATL_RDM_DESCDLEN_WIDTH 10
281 /* default value of bitfield desc{d}_len[9:0] */
282 #define HW_ATL_RDM_DESCDLEN_DEFAULT 0x0
284 /* rx desc{d}_reset bitfield definitions
285 * preprocessor definitions for the bitfield "desc{d}_reset".
286 * parameter: descriptor {d} | stride size 0x20 | range [0, 31]
287 * port="pif_rdm_q_pf_res_i[0]"
290 /* register address for bitfield desc{d}_reset */
291 #define HW_ATL_RDM_DESCDRESET_ADR(descriptor) (0x00005b08 + (descriptor) * 0x20)
292 /* bitmask for bitfield desc{d}_reset */
293 #define HW_ATL_RDM_DESCDRESET_MSK 0x02000000
294 /* inverted bitmask for bitfield desc{d}_reset */
295 #define HW_ATL_RDM_DESCDRESET_MSKN 0xfdffffff
296 /* lower bit position of bitfield desc{d}_reset */
297 #define HW_ATL_RDM_DESCDRESET_SHIFT 25
298 /* width of bitfield desc{d}_reset */
299 #define HW_ATL_RDM_DESCDRESET_WIDTH 1
300 /* default value of bitfield desc{d}_reset */
301 #define HW_ATL_RDM_DESCDRESET_DEFAULT 0x0
303 /* rdm_desc_init_i bitfield definitions
304 * preprocessor definitions for the bitfield rdm_desc_init_i.
305 * port="pif_rdm_desc_init_i"
308 /* register address for bitfield rdm_desc_init_i */
309 #define HW_ATL_RDM_RX_DMA_DESC_CACHE_INIT_ADR 0x00005a00
310 /* bitmask for bitfield rdm_desc_init_i */
311 #define HW_ATL_RDM_RX_DMA_DESC_CACHE_INIT_MSK 0xffffffff
312 /* inverted bitmask for bitfield rdm_desc_init_i */
313 #define HW_ATL_RDM_RX_DMA_DESC_CACHE_INIT_MSKN 0x00000000
314 /* lower bit position of bitfield rdm_desc_init_i */
315 #define HW_ATL_RDM_RX_DMA_DESC_CACHE_INIT_SHIFT 0
316 /* width of bitfield rdm_desc_init_i */
317 #define HW_ATL_RDM_RX_DMA_DESC_CACHE_INIT_WIDTH 32
318 /* default value of bitfield rdm_desc_init_i */
319 #define HW_ATL_RDM_RX_DMA_DESC_CACHE_INIT_DEFAULT 0x0
321 /* rx int_desc_wrb_en bitfield definitions
322 * preprocessor definitions for the bitfield "int_desc_wrb_en".
323 * port="pif_rdm_int_desc_wrb_en_i"
326 /* register address for bitfield int_desc_wrb_en */
327 #define HW_ATL_RDM_INT_DESC_WRB_EN_ADR 0x00005a30
328 /* bitmask for bitfield int_desc_wrb_en */
329 #define HW_ATL_RDM_INT_DESC_WRB_EN_MSK 0x00000004
330 /* inverted bitmask for bitfield int_desc_wrb_en */
331 #define HW_ATL_RDM_INT_DESC_WRB_EN_MSKN 0xfffffffb
332 /* lower bit position of bitfield int_desc_wrb_en */
333 #define HW_ATL_RDM_INT_DESC_WRB_EN_SHIFT 2
334 /* width of bitfield int_desc_wrb_en */
335 #define HW_ATL_RDM_INT_DESC_WRB_EN_WIDTH 1
336 /* default value of bitfield int_desc_wrb_en */
337 #define HW_ATL_RDM_INT_DESC_WRB_EN_DEFAULT 0x0
339 /* rx dca{d}_hdr_en bitfield definitions
340 * preprocessor definitions for the bitfield "dca{d}_hdr_en".
341 * parameter: dca {d} | stride size 0x4 | range [0, 31]
342 * port="pif_rdm_dca_hdr_en_i[0]"
345 /* register address for bitfield dca{d}_hdr_en */
346 #define HW_ATL_RDM_DCADHDR_EN_ADR(dca) (0x00006100 + (dca) * 0x4)
347 /* bitmask for bitfield dca{d}_hdr_en */
348 #define HW_ATL_RDM_DCADHDR_EN_MSK 0x40000000
349 /* inverted bitmask for bitfield dca{d}_hdr_en */
350 #define HW_ATL_RDM_DCADHDR_EN_MSKN 0xbfffffff
351 /* lower bit position of bitfield dca{d}_hdr_en */
352 #define HW_ATL_RDM_DCADHDR_EN_SHIFT 30
353 /* width of bitfield dca{d}_hdr_en */
354 #define HW_ATL_RDM_DCADHDR_EN_WIDTH 1
355 /* default value of bitfield dca{d}_hdr_en */
356 #define HW_ATL_RDM_DCADHDR_EN_DEFAULT 0x0
358 /* rx dca{d}_pay_en bitfield definitions
359 * preprocessor definitions for the bitfield "dca{d}_pay_en".
360 * parameter: dca {d} | stride size 0x4 | range [0, 31]
361 * port="pif_rdm_dca_pay_en_i[0]"
364 /* register address for bitfield dca{d}_pay_en */
365 #define HW_ATL_RDM_DCADPAY_EN_ADR(dca) (0x00006100 + (dca) * 0x4)
366 /* bitmask for bitfield dca{d}_pay_en */
367 #define HW_ATL_RDM_DCADPAY_EN_MSK 0x20000000
368 /* inverted bitmask for bitfield dca{d}_pay_en */
369 #define HW_ATL_RDM_DCADPAY_EN_MSKN 0xdfffffff
370 /* lower bit position of bitfield dca{d}_pay_en */
371 #define HW_ATL_RDM_DCADPAY_EN_SHIFT 29
372 /* width of bitfield dca{d}_pay_en */
373 #define HW_ATL_RDM_DCADPAY_EN_WIDTH 1
374 /* default value of bitfield dca{d}_pay_en */
375 #define HW_ATL_RDM_DCADPAY_EN_DEFAULT 0x0
377 /* RX rdm_int_rim_en Bitfield Definitions
378 * Preprocessor definitions for the bitfield "rdm_int_rim_en".
379 * PORT="pif_rdm_int_rim_en_i"
382 /* Register address for bitfield rdm_int_rim_en */
383 #define HW_ATL_RDM_INT_RIM_EN_ADR 0x00005A30
384 /* Bitmask for bitfield rdm_int_rim_en */
385 #define HW_ATL_RDM_INT_RIM_EN_MSK 0x00000008
386 /* Inverted bitmask for bitfield rdm_int_rim_en */
387 #define HW_ATL_RDM_INT_RIM_EN_MSKN 0xFFFFFFF7
388 /* Lower bit position of bitfield rdm_int_rim_en */
389 #define HW_ATL_RDM_INT_RIM_EN_SHIFT 3
390 /* Width of bitfield rdm_int_rim_en */
391 #define HW_ATL_RDM_INT_RIM_EN_WIDTH 1
392 /* Default value of bitfield rdm_int_rim_en */
393 #define HW_ATL_RDM_INT_RIM_EN_DEFAULT 0x0
395 /* general interrupt mapping register definitions
396 * preprocessor definitions for general interrupt mapping register
397 * base address: 0x00002180
398 * parameter: regidx {f} | stride size 0x4 | range [0, 3]
400 #define HW_ATL_GEN_INTR_MAP_ADR(regidx) (0x00002180u + (regidx) * 0x4)
402 /* general interrupt status register definitions
403 * preprocessor definitions for general interrupt status register
404 * address: 0x000021A0
407 #define HW_ATL_GEN_INTR_STAT_ADR 0x000021A4U
409 /* interrupt global control register definitions
410 * preprocessor definitions for interrupt global control register
411 * address: 0x00002300
413 #define HW_ATL_INTR_GLB_CTL_ADR 0x00002300u
415 /* interrupt throttle register definitions
416 * preprocessor definitions for interrupt throttle register
417 * base address: 0x00002800
418 * parameter: throttle {t} | stride size 0x4 | range [0, 31]
420 #define HW_ATL_INTR_THR_ADR(throttle) (0x00002800u + (throttle) * 0x4)
422 /* rx dma descriptor base address lsw definitions
423 * preprocessor definitions for rx dma descriptor base address lsw
424 * base address: 0x00005b00
425 * parameter: descriptor {d} | stride size 0x20 | range [0, 31]
427 #define HW_ATL_RX_DMA_DESC_BASE_ADDRLSW_ADR(descriptor) \
428 (0x00005b00u + (descriptor) * 0x20)
430 /* rx dma descriptor base address msw definitions
431 * preprocessor definitions for rx dma descriptor base address msw
432 * base address: 0x00005b04
433 * parameter: descriptor {d} | stride size 0x20 | range [0, 31]
435 #define HW_ATL_RX_DMA_DESC_BASE_ADDRMSW_ADR(descriptor) \
436 (0x00005b04u + (descriptor) * 0x20)
438 /* rx dma descriptor status register definitions
439 * preprocessor definitions for rx dma descriptor status register
440 * base address: 0x00005b14
441 * parameter: descriptor {d} | stride size 0x20 | range [0, 31]
443 #define HW_ATL_RX_DMA_DESC_STAT_ADR(descriptor) \
444 (0x00005b14u + (descriptor) * 0x20)
446 /* rx dma descriptor tail pointer register definitions
447 * preprocessor definitions for rx dma descriptor tail pointer register
448 * base address: 0x00005b10
449 * parameter: descriptor {d} | stride size 0x20 | range [0, 31]
451 #define HW_ATL_RX_DMA_DESC_TAIL_PTR_ADR(descriptor) \
452 (0x00005b10u + (descriptor) * 0x20)
454 /* rx interrupt moderation control register definitions
455 * Preprocessor definitions for RX Interrupt Moderation Control Register
456 * Base Address: 0x00005A40
457 * Parameter: RIM {R} | stride size 0x4 | range [0, 31]
459 #define HW_ATL_RX_INTR_MODERATION_CTL_ADR(rim) (0x00005A40u + (rim) * 0x4)
461 /* rx filter multicast filter mask register definitions
462 * preprocessor definitions for rx filter multicast filter mask register
463 * address: 0x00005270
465 #define HW_ATL_RX_FLR_MCST_FLR_MSK_ADR 0x00005270u
467 /* rx filter multicast filter register definitions
468 * preprocessor definitions for rx filter multicast filter register
469 * base address: 0x00005250
470 * parameter: filter {f} | stride size 0x4 | range [0, 7]
472 #define HW_ATL_RX_FLR_MCST_FLR_ADR(filter) (0x00005250u + (filter) * 0x4)
474 /* RX Filter RSS Control Register 1 Definitions
475 * Preprocessor definitions for RX Filter RSS Control Register 1
476 * Address: 0x000054C0
478 #define HW_ATL_RX_FLR_RSS_CONTROL1_ADR 0x000054C0u
480 /* RX Filter Control Register 2 Definitions
481 * Preprocessor definitions for RX Filter Control Register 2
482 * Address: 0x00005104
484 #define HW_ATL_RX_FLR_CONTROL2_ADR 0x00005104u
486 /* tx tx dma debug control [1f:0] bitfield definitions
487 * preprocessor definitions for the bitfield "tx dma debug control [1f:0]".
488 * port="pif_tdm_debug_cntl_i[31:0]"
491 /* register address for bitfield tx dma debug control [1f:0] */
492 #define HW_ATL_TDM_TX_DMA_DEBUG_CTL_ADR 0x00008920
493 /* bitmask for bitfield tx dma debug control [1f:0] */
494 #define HW_ATL_TDM_TX_DMA_DEBUG_CTL_MSK 0xffffffff
495 /* inverted bitmask for bitfield tx dma debug control [1f:0] */
496 #define HW_ATL_TDM_TX_DMA_DEBUG_CTL_MSKN 0x00000000
497 /* lower bit position of bitfield tx dma debug control [1f:0] */
498 #define HW_ATL_TDM_TX_DMA_DEBUG_CTL_SHIFT 0
499 /* width of bitfield tx dma debug control [1f:0] */
500 #define HW_ATL_TDM_TX_DMA_DEBUG_CTL_WIDTH 32
501 /* default value of bitfield tx dma debug control [1f:0] */
502 #define HW_ATL_TDM_TX_DMA_DEBUG_CTL_DEFAULT 0x0
504 /* tx dma descriptor base address lsw definitions
505 * preprocessor definitions for tx dma descriptor base address lsw
506 * base address: 0x00007c00
507 * parameter: descriptor {d} | stride size 0x40 | range [0, 31]
509 #define HW_ATL_TX_DMA_DESC_BASE_ADDRLSW_ADR(descriptor) \
510 (0x00007c00u + (descriptor) * 0x40)
512 /* tx dma descriptor tail pointer register definitions
513 * preprocessor definitions for tx dma descriptor tail pointer register
514 * base address: 0x00007c10
515 * parameter: descriptor {d} | stride size 0x40 | range [0, 31]
517 #define HW_ATL_TX_DMA_DESC_TAIL_PTR_ADR(descriptor) \
518 (0x00007c10u + (descriptor) * 0x40)
520 /* rx dma_sys_loopback bitfield definitions
521 * preprocessor definitions for the bitfield "dma_sys_loopback".
522 * port="pif_rpb_dma_sys_lbk_i"
525 /* register address for bitfield dma_sys_loopback */
526 #define HW_ATL_RPB_DMA_SYS_LBK_ADR 0x00005000
527 /* bitmask for bitfield dma_sys_loopback */
528 #define HW_ATL_RPB_DMA_SYS_LBK_MSK 0x00000040
529 /* inverted bitmask for bitfield dma_sys_loopback */
530 #define HW_ATL_RPB_DMA_SYS_LBK_MSKN 0xffffffbf
531 /* lower bit position of bitfield dma_sys_loopback */
532 #define HW_ATL_RPB_DMA_SYS_LBK_SHIFT 6
533 /* width of bitfield dma_sys_loopback */
534 #define HW_ATL_RPB_DMA_SYS_LBK_WIDTH 1
535 /* default value of bitfield dma_sys_loopback */
536 #define HW_ATL_RPB_DMA_SYS_LBK_DEFAULT 0x0
538 /* rx rx_tc_mode bitfield definitions
539 * preprocessor definitions for the bitfield "rx_tc_mode".
540 * port="pif_rpb_rx_tc_mode_i,pif_rpf_rx_tc_mode_i"
543 /* register address for bitfield rx_tc_mode */
544 #define HW_ATL_RPB_RPF_RX_TC_MODE_ADR 0x00005700
545 /* bitmask for bitfield rx_tc_mode */
546 #define HW_ATL_RPB_RPF_RX_TC_MODE_MSK 0x00000100
547 /* inverted bitmask for bitfield rx_tc_mode */
548 #define HW_ATL_RPB_RPF_RX_TC_MODE_MSKN 0xfffffeff
549 /* lower bit position of bitfield rx_tc_mode */
550 #define HW_ATL_RPB_RPF_RX_TC_MODE_SHIFT 8
551 /* width of bitfield rx_tc_mode */
552 #define HW_ATL_RPB_RPF_RX_TC_MODE_WIDTH 1
553 /* default value of bitfield rx_tc_mode */
554 #define HW_ATL_RPB_RPF_RX_TC_MODE_DEFAULT 0x0
556 /* rx rx_buf_en bitfield definitions
557 * preprocessor definitions for the bitfield "rx_buf_en".
558 * port="pif_rpb_rx_buf_en_i"
561 /* register address for bitfield rx_buf_en */
562 #define HW_ATL_RPB_RX_BUF_EN_ADR 0x00005700
563 /* bitmask for bitfield rx_buf_en */
564 #define HW_ATL_RPB_RX_BUF_EN_MSK 0x00000001
565 /* inverted bitmask for bitfield rx_buf_en */
566 #define HW_ATL_RPB_RX_BUF_EN_MSKN 0xfffffffe
567 /* lower bit position of bitfield rx_buf_en */
568 #define HW_ATL_RPB_RX_BUF_EN_SHIFT 0
569 /* width of bitfield rx_buf_en */
570 #define HW_ATL_RPB_RX_BUF_EN_WIDTH 1
571 /* default value of bitfield rx_buf_en */
572 #define HW_ATL_RPB_RX_BUF_EN_DEFAULT 0x0
574 /* rx rx{b}_hi_thresh[d:0] bitfield definitions
575 * preprocessor definitions for the bitfield "rx{b}_hi_thresh[d:0]".
576 * parameter: buffer {b} | stride size 0x10 | range [0, 7]
577 * port="pif_rpb_rx0_hi_thresh_i[13:0]"
580 /* register address for bitfield rx{b}_hi_thresh[d:0] */
581 #define HW_ATL_RPB_RXBHI_THRESH_ADR(buffer) (0x00005714 + (buffer) * 0x10)
582 /* bitmask for bitfield rx{b}_hi_thresh[d:0] */
583 #define HW_ATL_RPB_RXBHI_THRESH_MSK 0x3fff0000
584 /* inverted bitmask for bitfield rx{b}_hi_thresh[d:0] */
585 #define HW_ATL_RPB_RXBHI_THRESH_MSKN 0xc000ffff
586 /* lower bit position of bitfield rx{b}_hi_thresh[d:0] */
587 #define HW_ATL_RPB_RXBHI_THRESH_SHIFT 16
588 /* width of bitfield rx{b}_hi_thresh[d:0] */
589 #define HW_ATL_RPB_RXBHI_THRESH_WIDTH 14
590 /* default value of bitfield rx{b}_hi_thresh[d:0] */
591 #define HW_ATL_RPB_RXBHI_THRESH_DEFAULT 0x0
593 /* rx rx{b}_lo_thresh[d:0] bitfield definitions
594 * preprocessor definitions for the bitfield "rx{b}_lo_thresh[d:0]".
595 * parameter: buffer {b} | stride size 0x10 | range [0, 7]
596 * port="pif_rpb_rx0_lo_thresh_i[13:0]"
599 /* register address for bitfield rx{b}_lo_thresh[d:0] */
600 #define HW_ATL_RPB_RXBLO_THRESH_ADR(buffer) (0x00005714 + (buffer) * 0x10)
601 /* bitmask for bitfield rx{b}_lo_thresh[d:0] */
602 #define HW_ATL_RPB_RXBLO_THRESH_MSK 0x00003fff
603 /* inverted bitmask for bitfield rx{b}_lo_thresh[d:0] */
604 #define HW_ATL_RPB_RXBLO_THRESH_MSKN 0xffffc000
605 /* lower bit position of bitfield rx{b}_lo_thresh[d:0] */
606 #define HW_ATL_RPB_RXBLO_THRESH_SHIFT 0
607 /* width of bitfield rx{b}_lo_thresh[d:0] */
608 #define HW_ATL_RPB_RXBLO_THRESH_WIDTH 14
609 /* default value of bitfield rx{b}_lo_thresh[d:0] */
610 #define HW_ATL_RPB_RXBLO_THRESH_DEFAULT 0x0
612 /* rx rx_fc_mode[1:0] bitfield definitions
613 * preprocessor definitions for the bitfield "rx_fc_mode[1:0]".
614 * port="pif_rpb_rx_fc_mode_i[1:0]"
617 /* register address for bitfield rx_fc_mode[1:0] */
618 #define HW_ATL_RPB_RX_FC_MODE_ADR 0x00005700
619 /* bitmask for bitfield rx_fc_mode[1:0] */
620 #define HW_ATL_RPB_RX_FC_MODE_MSK 0x00000030
621 /* inverted bitmask for bitfield rx_fc_mode[1:0] */
622 #define HW_ATL_RPB_RX_FC_MODE_MSKN 0xffffffcf
623 /* lower bit position of bitfield rx_fc_mode[1:0] */
624 #define HW_ATL_RPB_RX_FC_MODE_SHIFT 4
625 /* width of bitfield rx_fc_mode[1:0] */
626 #define HW_ATL_RPB_RX_FC_MODE_WIDTH 2
627 /* default value of bitfield rx_fc_mode[1:0] */
628 #define HW_ATL_RPB_RX_FC_MODE_DEFAULT 0x0
630 /* rx rx{b}_buf_size[8:0] bitfield definitions
631 * preprocessor definitions for the bitfield "rx{b}_buf_size[8:0]".
632 * parameter: buffer {b} | stride size 0x10 | range [0, 7]
633 * port="pif_rpb_rx0_buf_size_i[8:0]"
636 /* register address for bitfield rx{b}_buf_size[8:0] */
637 #define HW_ATL_RPB_RXBBUF_SIZE_ADR(buffer) (0x00005710 + (buffer) * 0x10)
638 /* bitmask for bitfield rx{b}_buf_size[8:0] */
639 #define HW_ATL_RPB_RXBBUF_SIZE_MSK 0x000001ff
640 /* inverted bitmask for bitfield rx{b}_buf_size[8:0] */
641 #define HW_ATL_RPB_RXBBUF_SIZE_MSKN 0xfffffe00
642 /* lower bit position of bitfield rx{b}_buf_size[8:0] */
643 #define HW_ATL_RPB_RXBBUF_SIZE_SHIFT 0
644 /* width of bitfield rx{b}_buf_size[8:0] */
645 #define HW_ATL_RPB_RXBBUF_SIZE_WIDTH 9
646 /* default value of bitfield rx{b}_buf_size[8:0] */
647 #define HW_ATL_RPB_RXBBUF_SIZE_DEFAULT 0x0
649 /* rx rx{b}_xoff_en bitfield definitions
650 * preprocessor definitions for the bitfield "rx{b}_xoff_en".
651 * parameter: buffer {b} | stride size 0x10 | range [0, 7]
652 * port="pif_rpb_rx_xoff_en_i[0]"
655 /* register address for bitfield rx{b}_xoff_en */
656 #define HW_ATL_RPB_RXBXOFF_EN_ADR(buffer) (0x00005714 + (buffer) * 0x10)
657 /* bitmask for bitfield rx{b}_xoff_en */
658 #define HW_ATL_RPB_RXBXOFF_EN_MSK 0x80000000
659 /* inverted bitmask for bitfield rx{b}_xoff_en */
660 #define HW_ATL_RPB_RXBXOFF_EN_MSKN 0x7fffffff
661 /* lower bit position of bitfield rx{b}_xoff_en */
662 #define HW_ATL_RPB_RXBXOFF_EN_SHIFT 31
663 /* width of bitfield rx{b}_xoff_en */
664 #define HW_ATL_RPB_RXBXOFF_EN_WIDTH 1
665 /* default value of bitfield rx{b}_xoff_en */
666 #define HW_ATL_RPB_RXBXOFF_EN_DEFAULT 0x0
668 /* rx l2_bc_thresh[f:0] bitfield definitions
669 * preprocessor definitions for the bitfield "l2_bc_thresh[f:0]".
670 * port="pif_rpf_l2_bc_thresh_i[15:0]"
673 /* register address for bitfield l2_bc_thresh[f:0] */
674 #define HW_ATL_RPFL2BC_THRESH_ADR 0x00005100
675 /* bitmask for bitfield l2_bc_thresh[f:0] */
676 #define HW_ATL_RPFL2BC_THRESH_MSK 0xffff0000
677 /* inverted bitmask for bitfield l2_bc_thresh[f:0] */
678 #define HW_ATL_RPFL2BC_THRESH_MSKN 0x0000ffff
679 /* lower bit position of bitfield l2_bc_thresh[f:0] */
680 #define HW_ATL_RPFL2BC_THRESH_SHIFT 16
681 /* width of bitfield l2_bc_thresh[f:0] */
682 #define HW_ATL_RPFL2BC_THRESH_WIDTH 16
683 /* default value of bitfield l2_bc_thresh[f:0] */
684 #define HW_ATL_RPFL2BC_THRESH_DEFAULT 0x0
686 /* rx l2_bc_en bitfield definitions
687 * preprocessor definitions for the bitfield "l2_bc_en".
688 * port="pif_rpf_l2_bc_en_i"
691 /* register address for bitfield l2_bc_en */
692 #define HW_ATL_RPFL2BC_EN_ADR 0x00005100
693 /* bitmask for bitfield l2_bc_en */
694 #define HW_ATL_RPFL2BC_EN_MSK 0x00000001
695 /* inverted bitmask for bitfield l2_bc_en */
696 #define HW_ATL_RPFL2BC_EN_MSKN 0xfffffffe
697 /* lower bit position of bitfield l2_bc_en */
698 #define HW_ATL_RPFL2BC_EN_SHIFT 0
699 /* width of bitfield l2_bc_en */
700 #define HW_ATL_RPFL2BC_EN_WIDTH 1
701 /* default value of bitfield l2_bc_en */
702 #define HW_ATL_RPFL2BC_EN_DEFAULT 0x0
704 /* rx l2_bc_act[2:0] bitfield definitions
705 * preprocessor definitions for the bitfield "l2_bc_act[2:0]".
706 * port="pif_rpf_l2_bc_act_i[2:0]"
709 /* register address for bitfield l2_bc_act[2:0] */
710 #define HW_ATL_RPFL2BC_ACT_ADR 0x00005100
711 /* bitmask for bitfield l2_bc_act[2:0] */
712 #define HW_ATL_RPFL2BC_ACT_MSK 0x00007000
713 /* inverted bitmask for bitfield l2_bc_act[2:0] */
714 #define HW_ATL_RPFL2BC_ACT_MSKN 0xffff8fff
715 /* lower bit position of bitfield l2_bc_act[2:0] */
716 #define HW_ATL_RPFL2BC_ACT_SHIFT 12
717 /* width of bitfield l2_bc_act[2:0] */
718 #define HW_ATL_RPFL2BC_ACT_WIDTH 3
719 /* default value of bitfield l2_bc_act[2:0] */
720 #define HW_ATL_RPFL2BC_ACT_DEFAULT 0x0
722 /* rx l2_mc_en{f} bitfield definitions
723 * preprocessor definitions for the bitfield "l2_mc_en{f}".
724 * parameter: filter {f} | stride size 0x4 | range [0, 7]
725 * port="pif_rpf_l2_mc_en_i[0]"
728 /* register address for bitfield l2_mc_en{f} */
729 #define HW_ATL_RPFL2MC_ENF_ADR(filter) (0x00005250 + (filter) * 0x4)
730 /* bitmask for bitfield l2_mc_en{f} */
731 #define HW_ATL_RPFL2MC_ENF_MSK 0x80000000
732 /* inverted bitmask for bitfield l2_mc_en{f} */
733 #define HW_ATL_RPFL2MC_ENF_MSKN 0x7fffffff
734 /* lower bit position of bitfield l2_mc_en{f} */
735 #define HW_ATL_RPFL2MC_ENF_SHIFT 31
736 /* width of bitfield l2_mc_en{f} */
737 #define HW_ATL_RPFL2MC_ENF_WIDTH 1
738 /* default value of bitfield l2_mc_en{f} */
739 #define HW_ATL_RPFL2MC_ENF_DEFAULT 0x0
741 /* rx l2_promis_mode bitfield definitions
742 * preprocessor definitions for the bitfield "l2_promis_mode".
743 * port="pif_rpf_l2_promis_mode_i"
746 /* register address for bitfield l2_promis_mode */
747 #define HW_ATL_RPFL2PROMIS_MODE_ADR 0x00005100
748 /* bitmask for bitfield l2_promis_mode */
749 #define HW_ATL_RPFL2PROMIS_MODE_MSK 0x00000008
750 /* inverted bitmask for bitfield l2_promis_mode */
751 #define HW_ATL_RPFL2PROMIS_MODE_MSKN 0xfffffff7
752 /* lower bit position of bitfield l2_promis_mode */
753 #define HW_ATL_RPFL2PROMIS_MODE_SHIFT 3
754 /* width of bitfield l2_promis_mode */
755 #define HW_ATL_RPFL2PROMIS_MODE_WIDTH 1
756 /* default value of bitfield l2_promis_mode */
757 #define HW_ATL_RPFL2PROMIS_MODE_DEFAULT 0x0
759 /* rx l2_uc_act{f}[2:0] bitfield definitions
760 * preprocessor definitions for the bitfield "l2_uc_act{f}[2:0]".
761 * parameter: filter {f} | stride size 0x8 | range [0, 37]
762 * port="pif_rpf_l2_uc_act0_i[2:0]"
765 /* register address for bitfield l2_uc_act{f}[2:0] */
766 #define HW_ATL_RPFL2UC_ACTF_ADR(filter) (0x00005114 + (filter) * 0x8)
767 /* bitmask for bitfield l2_uc_act{f}[2:0] */
768 #define HW_ATL_RPFL2UC_ACTF_MSK 0x00070000
769 /* inverted bitmask for bitfield l2_uc_act{f}[2:0] */
770 #define HW_ATL_RPFL2UC_ACTF_MSKN 0xfff8ffff
771 /* lower bit position of bitfield l2_uc_act{f}[2:0] */
772 #define HW_ATL_RPFL2UC_ACTF_SHIFT 16
773 /* width of bitfield l2_uc_act{f}[2:0] */
774 #define HW_ATL_RPFL2UC_ACTF_WIDTH 3
775 /* default value of bitfield l2_uc_act{f}[2:0] */
776 #define HW_ATL_RPFL2UC_ACTF_DEFAULT 0x0
778 /* rx l2_uc_en{f} bitfield definitions
779 * preprocessor definitions for the bitfield "l2_uc_en{f}".
780 * parameter: filter {f} | stride size 0x8 | range [0, 37]
781 * port="pif_rpf_l2_uc_en_i[0]"
784 /* register address for bitfield l2_uc_en{f} */
785 #define HW_ATL_RPFL2UC_ENF_ADR(filter) (0x00005114 + (filter) * 0x8)
786 /* bitmask for bitfield l2_uc_en{f} */
787 #define HW_ATL_RPFL2UC_ENF_MSK 0x80000000
788 /* inverted bitmask for bitfield l2_uc_en{f} */
789 #define HW_ATL_RPFL2UC_ENF_MSKN 0x7fffffff
790 /* lower bit position of bitfield l2_uc_en{f} */
791 #define HW_ATL_RPFL2UC_ENF_SHIFT 31
792 /* width of bitfield l2_uc_en{f} */
793 #define HW_ATL_RPFL2UC_ENF_WIDTH 1
794 /* default value of bitfield l2_uc_en{f} */
795 #define HW_ATL_RPFL2UC_ENF_DEFAULT 0x0
797 /* register address for bitfield l2_uc_da{f}_lsw[1f:0] */
798 #define HW_ATL_RPFL2UC_DAFLSW_ADR(filter) (0x00005110 + (filter) * 0x8)
799 /* register address for bitfield l2_uc_da{f}_msw[f:0] */
800 #define HW_ATL_RPFL2UC_DAFMSW_ADR(filter) (0x00005114 + (filter) * 0x8)
801 /* bitmask for bitfield l2_uc_da{f}_msw[f:0] */
802 #define HW_ATL_RPFL2UC_DAFMSW_MSK 0x0000ffff
803 /* lower bit position of bitfield l2_uc_da{f}_msw[f:0] */
804 #define HW_ATL_RPFL2UC_DAFMSW_SHIFT 0
806 /* rx l2_mc_accept_all bitfield definitions
807 * Preprocessor definitions for the bitfield "l2_mc_accept_all".
808 * PORT="pif_rpf_l2_mc_all_accept_i"
811 /* Register address for bitfield l2_mc_accept_all */
812 #define HW_ATL_RPFL2MC_ACCEPT_ALL_ADR 0x00005270
813 /* Bitmask for bitfield l2_mc_accept_all */
814 #define HW_ATL_RPFL2MC_ACCEPT_ALL_MSK 0x00004000
815 /* Inverted bitmask for bitfield l2_mc_accept_all */
816 #define HW_ATL_RPFL2MC_ACCEPT_ALL_MSKN 0xFFFFBFFF
817 /* Lower bit position of bitfield l2_mc_accept_all */
818 #define HW_ATL_RPFL2MC_ACCEPT_ALL_SHIFT 14
819 /* Width of bitfield l2_mc_accept_all */
820 #define HW_ATL_RPFL2MC_ACCEPT_ALL_WIDTH 1
821 /* Default value of bitfield l2_mc_accept_all */
822 #define HW_ATL_RPFL2MC_ACCEPT_ALL_DEFAULT 0x0
824 /* width of bitfield rx_tc_up{t}[2:0] */
825 #define HW_ATL_RPF_RPB_RX_TC_UPT_WIDTH 3
826 /* default value of bitfield rx_tc_up{t}[2:0] */
827 #define HW_ATL_RPF_RPB_RX_TC_UPT_DEFAULT 0x0
829 /* rx rss_key_addr[4:0] bitfield definitions
830 * preprocessor definitions for the bitfield "rss_key_addr[4:0]".
831 * port="pif_rpf_rss_key_addr_i[4:0]"
834 /* register address for bitfield rss_key_addr[4:0] */
835 #define HW_ATL_RPF_RSS_KEY_ADDR_ADR 0x000054d0
836 /* bitmask for bitfield rss_key_addr[4:0] */
837 #define HW_ATL_RPF_RSS_KEY_ADDR_MSK 0x0000001f
838 /* inverted bitmask for bitfield rss_key_addr[4:0] */
839 #define HW_ATL_RPF_RSS_KEY_ADDR_MSKN 0xffffffe0
840 /* lower bit position of bitfield rss_key_addr[4:0] */
841 #define HW_ATL_RPF_RSS_KEY_ADDR_SHIFT 0
842 /* width of bitfield rss_key_addr[4:0] */
843 #define HW_ATL_RPF_RSS_KEY_ADDR_WIDTH 5
844 /* default value of bitfield rss_key_addr[4:0] */
845 #define HW_ATL_RPF_RSS_KEY_ADDR_DEFAULT 0x0
847 /* rx rss_key_wr_data[1f:0] bitfield definitions
848 * preprocessor definitions for the bitfield "rss_key_wr_data[1f:0]".
849 * port="pif_rpf_rss_key_wr_data_i[31:0]"
852 /* register address for bitfield rss_key_wr_data[1f:0] */
853 #define HW_ATL_RPF_RSS_KEY_WR_DATA_ADR 0x000054d4
854 /* bitmask for bitfield rss_key_wr_data[1f:0] */
855 #define HW_ATL_RPF_RSS_KEY_WR_DATA_MSK 0xffffffff
856 /* inverted bitmask for bitfield rss_key_wr_data[1f:0] */
857 #define HW_ATL_RPF_RSS_KEY_WR_DATA_MSKN 0x00000000
858 /* lower bit position of bitfield rss_key_wr_data[1f:0] */
859 #define HW_ATL_RPF_RSS_KEY_WR_DATA_SHIFT 0
860 /* width of bitfield rss_key_wr_data[1f:0] */
861 #define HW_ATL_RPF_RSS_KEY_WR_DATA_WIDTH 32
862 /* default value of bitfield rss_key_wr_data[1f:0] */
863 #define HW_ATL_RPF_RSS_KEY_WR_DATA_DEFAULT 0x0
865 /* rx rss_key_wr_en_i bitfield definitions
866 * preprocessor definitions for the bitfield "rss_key_wr_en_i".
867 * port="pif_rpf_rss_key_wr_en_i"
870 /* register address for bitfield rss_key_wr_en_i */
871 #define HW_ATL_RPF_RSS_KEY_WR_ENI_ADR 0x000054d0
872 /* bitmask for bitfield rss_key_wr_en_i */
873 #define HW_ATL_RPF_RSS_KEY_WR_ENI_MSK 0x00000020
874 /* inverted bitmask for bitfield rss_key_wr_en_i */
875 #define HW_ATL_RPF_RSS_KEY_WR_ENI_MSKN 0xffffffdf
876 /* lower bit position of bitfield rss_key_wr_en_i */
877 #define HW_ATL_RPF_RSS_KEY_WR_ENI_SHIFT 5
878 /* width of bitfield rss_key_wr_en_i */
879 #define HW_ATL_RPF_RSS_KEY_WR_ENI_WIDTH 1
880 /* default value of bitfield rss_key_wr_en_i */
881 #define HW_ATL_RPF_RSS_KEY_WR_ENI_DEFAULT 0x0
883 /* rx rss_redir_addr[3:0] bitfield definitions
884 * preprocessor definitions for the bitfield "rss_redir_addr[3:0]".
885 * port="pif_rpf_rss_redir_addr_i[3:0]"
888 /* register address for bitfield rss_redir_addr[3:0] */
889 #define HW_ATL_RPF_RSS_REDIR_ADDR_ADR 0x000054e0
890 /* bitmask for bitfield rss_redir_addr[3:0] */
891 #define HW_ATL_RPF_RSS_REDIR_ADDR_MSK 0x0000000f
892 /* inverted bitmask for bitfield rss_redir_addr[3:0] */
893 #define HW_ATL_RPF_RSS_REDIR_ADDR_MSKN 0xfffffff0
894 /* lower bit position of bitfield rss_redir_addr[3:0] */
895 #define HW_ATL_RPF_RSS_REDIR_ADDR_SHIFT 0
896 /* width of bitfield rss_redir_addr[3:0] */
897 #define HW_ATL_RPF_RSS_REDIR_ADDR_WIDTH 4
898 /* default value of bitfield rss_redir_addr[3:0] */
899 #define HW_ATL_RPF_RSS_REDIR_ADDR_DEFAULT 0x0
901 /* rx rss_redir_wr_data[f:0] bitfield definitions
902 * preprocessor definitions for the bitfield "rss_redir_wr_data[f:0]".
903 * port="pif_rpf_rss_redir_wr_data_i[15:0]"
906 /* register address for bitfield rss_redir_wr_data[f:0] */
907 #define HW_ATL_RPF_RSS_REDIR_WR_DATA_ADR 0x000054e4
908 /* bitmask for bitfield rss_redir_wr_data[f:0] */
909 #define HW_ATL_RPF_RSS_REDIR_WR_DATA_MSK 0x0000ffff
910 /* inverted bitmask for bitfield rss_redir_wr_data[f:0] */
911 #define HW_ATL_RPF_RSS_REDIR_WR_DATA_MSKN 0xffff0000
912 /* lower bit position of bitfield rss_redir_wr_data[f:0] */
913 #define HW_ATL_RPF_RSS_REDIR_WR_DATA_SHIFT 0
914 /* width of bitfield rss_redir_wr_data[f:0] */
915 #define HW_ATL_RPF_RSS_REDIR_WR_DATA_WIDTH 16
916 /* default value of bitfield rss_redir_wr_data[f:0] */
917 #define HW_ATL_RPF_RSS_REDIR_WR_DATA_DEFAULT 0x0
919 /* rx rss_redir_wr_en_i bitfield definitions
920 * preprocessor definitions for the bitfield "rss_redir_wr_en_i".
921 * port="pif_rpf_rss_redir_wr_en_i"
924 /* register address for bitfield rss_redir_wr_en_i */
925 #define HW_ATL_RPF_RSS_REDIR_WR_ENI_ADR 0x000054e0
926 /* bitmask for bitfield rss_redir_wr_en_i */
927 #define HW_ATL_RPF_RSS_REDIR_WR_ENI_MSK 0x00000010
928 /* inverted bitmask for bitfield rss_redir_wr_en_i */
929 #define HW_ATL_RPF_RSS_REDIR_WR_ENI_MSKN 0xffffffef
930 /* lower bit position of bitfield rss_redir_wr_en_i */
931 #define HW_ATL_RPF_RSS_REDIR_WR_ENI_SHIFT 4
932 /* width of bitfield rss_redir_wr_en_i */
933 #define HW_ATL_RPF_RSS_REDIR_WR_ENI_WIDTH 1
934 /* default value of bitfield rss_redir_wr_en_i */
935 #define HW_ATL_RPF_RSS_REDIR_WR_ENI_DEFAULT 0x0
937 /* rx tpo_rpf_sys_loopback bitfield definitions
938 * preprocessor definitions for the bitfield "tpo_rpf_sys_loopback".
939 * port="pif_rpf_tpo_pkt_sys_lbk_i"
942 /* register address for bitfield tpo_rpf_sys_loopback */
943 #define HW_ATL_RPF_TPO_RPF_SYS_LBK_ADR 0x00005000
944 /* bitmask for bitfield tpo_rpf_sys_loopback */
945 #define HW_ATL_RPF_TPO_RPF_SYS_LBK_MSK 0x00000100
946 /* inverted bitmask for bitfield tpo_rpf_sys_loopback */
947 #define HW_ATL_RPF_TPO_RPF_SYS_LBK_MSKN 0xfffffeff
948 /* lower bit position of bitfield tpo_rpf_sys_loopback */
949 #define HW_ATL_RPF_TPO_RPF_SYS_LBK_SHIFT 8
950 /* width of bitfield tpo_rpf_sys_loopback */
951 #define HW_ATL_RPF_TPO_RPF_SYS_LBK_WIDTH 1
952 /* default value of bitfield tpo_rpf_sys_loopback */
953 #define HW_ATL_RPF_TPO_RPF_SYS_LBK_DEFAULT 0x0
955 /* rx vl_inner_tpid[f:0] bitfield definitions
956 * preprocessor definitions for the bitfield "vl_inner_tpid[f:0]".
957 * port="pif_rpf_vl_inner_tpid_i[15:0]"
960 /* register address for bitfield vl_inner_tpid[f:0] */
961 #define HW_ATL_RPF_VL_INNER_TPID_ADR 0x00005284
962 /* bitmask for bitfield vl_inner_tpid[f:0] */
963 #define HW_ATL_RPF_VL_INNER_TPID_MSK 0x0000ffff
964 /* inverted bitmask for bitfield vl_inner_tpid[f:0] */
965 #define HW_ATL_RPF_VL_INNER_TPID_MSKN 0xffff0000
966 /* lower bit position of bitfield vl_inner_tpid[f:0] */
967 #define HW_ATL_RPF_VL_INNER_TPID_SHIFT 0
968 /* width of bitfield vl_inner_tpid[f:0] */
969 #define HW_ATL_RPF_VL_INNER_TPID_WIDTH 16
970 /* default value of bitfield vl_inner_tpid[f:0] */
971 #define HW_ATL_RPF_VL_INNER_TPID_DEFAULT 0x8100
973 /* rx vl_outer_tpid[f:0] bitfield definitions
974 * preprocessor definitions for the bitfield "vl_outer_tpid[f:0]".
975 * port="pif_rpf_vl_outer_tpid_i[15:0]"
978 /* register address for bitfield vl_outer_tpid[f:0] */
979 #define HW_ATL_RPF_VL_OUTER_TPID_ADR 0x00005284
980 /* bitmask for bitfield vl_outer_tpid[f:0] */
981 #define HW_ATL_RPF_VL_OUTER_TPID_MSK 0xffff0000
982 /* inverted bitmask for bitfield vl_outer_tpid[f:0] */
983 #define HW_ATL_RPF_VL_OUTER_TPID_MSKN 0x0000ffff
984 /* lower bit position of bitfield vl_outer_tpid[f:0] */
985 #define HW_ATL_RPF_VL_OUTER_TPID_SHIFT 16
986 /* width of bitfield vl_outer_tpid[f:0] */
987 #define HW_ATL_RPF_VL_OUTER_TPID_WIDTH 16
988 /* default value of bitfield vl_outer_tpid[f:0] */
989 #define HW_ATL_RPF_VL_OUTER_TPID_DEFAULT 0x88a8
991 /* rx vl_promis_mode bitfield definitions
992 * preprocessor definitions for the bitfield "vl_promis_mode".
993 * port="pif_rpf_vl_promis_mode_i"
996 /* register address for bitfield vl_promis_mode */
997 #define HW_ATL_RPF_VL_PROMIS_MODE_ADR 0x00005280
998 /* bitmask for bitfield vl_promis_mode */
999 #define HW_ATL_RPF_VL_PROMIS_MODE_MSK 0x00000002
1000 /* inverted bitmask for bitfield vl_promis_mode */
1001 #define HW_ATL_RPF_VL_PROMIS_MODE_MSKN 0xfffffffd
1002 /* lower bit position of bitfield vl_promis_mode */
1003 #define HW_ATL_RPF_VL_PROMIS_MODE_SHIFT 1
1004 /* width of bitfield vl_promis_mode */
1005 #define HW_ATL_RPF_VL_PROMIS_MODE_WIDTH 1
1006 /* default value of bitfield vl_promis_mode */
1007 #define HW_ATL_RPF_VL_PROMIS_MODE_DEFAULT 0x0
1009 /* RX vl_accept_untagged_mode Bitfield Definitions
1010 * Preprocessor definitions for the bitfield "vl_accept_untagged_mode".
1011 * PORT="pif_rpf_vl_accept_untagged_i"
1014 /* Register address for bitfield vl_accept_untagged_mode */
1015 #define HW_ATL_RPF_VL_ACCEPT_UNTAGGED_MODE_ADR 0x00005280
1016 /* Bitmask for bitfield vl_accept_untagged_mode */
1017 #define HW_ATL_RPF_VL_ACCEPT_UNTAGGED_MODE_MSK 0x00000004
1018 /* Inverted bitmask for bitfield vl_accept_untagged_mode */
1019 #define HW_ATL_RPF_VL_ACCEPT_UNTAGGED_MODE_MSKN 0xFFFFFFFB
1020 /* Lower bit position of bitfield vl_accept_untagged_mode */
1021 #define HW_ATL_RPF_VL_ACCEPT_UNTAGGED_MODE_SHIFT 2
1022 /* Width of bitfield vl_accept_untagged_mode */
1023 #define HW_ATL_RPF_VL_ACCEPT_UNTAGGED_MODE_WIDTH 1
1024 /* Default value of bitfield vl_accept_untagged_mode */
1025 #define HW_ATL_RPF_VL_ACCEPT_UNTAGGED_MODE_DEFAULT 0x0
1027 /* rX vl_untagged_act[2:0] Bitfield Definitions
1028 * Preprocessor definitions for the bitfield "vl_untagged_act[2:0]".
1029 * PORT="pif_rpf_vl_untagged_act_i[2:0]"
1032 /* Register address for bitfield vl_untagged_act[2:0] */
1033 #define HW_ATL_RPF_VL_UNTAGGED_ACT_ADR 0x00005280
1034 /* Bitmask for bitfield vl_untagged_act[2:0] */
1035 #define HW_ATL_RPF_VL_UNTAGGED_ACT_MSK 0x00000038
1036 /* Inverted bitmask for bitfield vl_untagged_act[2:0] */
1037 #define HW_ATL_RPF_VL_UNTAGGED_ACT_MSKN 0xFFFFFFC7
1038 /* Lower bit position of bitfield vl_untagged_act[2:0] */
1039 #define HW_ATL_RPF_VL_UNTAGGED_ACT_SHIFT 3
1040 /* Width of bitfield vl_untagged_act[2:0] */
1041 #define HW_ATL_RPF_VL_UNTAGGED_ACT_WIDTH 3
1042 /* Default value of bitfield vl_untagged_act[2:0] */
1043 #define HW_ATL_RPF_VL_UNTAGGED_ACT_DEFAULT 0x0
1045 /* RX vl_en{F} Bitfield Definitions
1046 * Preprocessor definitions for the bitfield "vl_en{F}".
1047 * Parameter: filter {F} | stride size 0x4 | range [0, 15]
1048 * PORT="pif_rpf_vl_en_i[0]"
1051 /* Register address for bitfield vl_en{F} */
1052 #define HW_ATL_RPF_VL_EN_F_ADR(filter) (0x00005290 + (filter) * 0x4)
1053 /* Bitmask for bitfield vl_en{F} */
1054 #define HW_ATL_RPF_VL_EN_F_MSK 0x80000000
1055 /* Inverted bitmask for bitfield vl_en{F} */
1056 #define HW_ATL_RPF_VL_EN_F_MSKN 0x7FFFFFFF
1057 /* Lower bit position of bitfield vl_en{F} */
1058 #define HW_ATL_RPF_VL_EN_F_SHIFT 31
1059 /* Width of bitfield vl_en{F} */
1060 #define HW_ATL_RPF_VL_EN_F_WIDTH 1
1061 /* Default value of bitfield vl_en{F} */
1062 #define HW_ATL_RPF_VL_EN_F_DEFAULT 0x0
1064 /* RX vl_act{F}[2:0] Bitfield Definitions
1065 * Preprocessor definitions for the bitfield "vl_act{F}[2:0]".
1066 * Parameter: filter {F} | stride size 0x4 | range [0, 15]
1067 * PORT="pif_rpf_vl_act0_i[2:0]"
1070 /* Register address for bitfield vl_act{F}[2:0] */
1071 #define HW_ATL_RPF_VL_ACT_F_ADR(filter) (0x00005290 + (filter) * 0x4)
1072 /* Bitmask for bitfield vl_act{F}[2:0] */
1073 #define HW_ATL_RPF_VL_ACT_F_MSK 0x00070000
1074 /* Inverted bitmask for bitfield vl_act{F}[2:0] */
1075 #define HW_ATL_RPF_VL_ACT_F_MSKN 0xFFF8FFFF
1076 /* Lower bit position of bitfield vl_act{F}[2:0] */
1077 #define HW_ATL_RPF_VL_ACT_F_SHIFT 16
1078 /* Width of bitfield vl_act{F}[2:0] */
1079 #define HW_ATL_RPF_VL_ACT_F_WIDTH 3
1080 /* Default value of bitfield vl_act{F}[2:0] */
1081 #define HW_ATL_RPF_VL_ACT_F_DEFAULT 0x0
1083 /* RX vl_id{F}[B:0] Bitfield Definitions
1084 * Preprocessor definitions for the bitfield "vl_id{F}[B:0]".
1085 * Parameter: filter {F} | stride size 0x4 | range [0, 15]
1086 * PORT="pif_rpf_vl_id0_i[11:0]"
1089 /* Register address for bitfield vl_id{F}[B:0] */
1090 #define HW_ATL_RPF_VL_ID_F_ADR(filter) (0x00005290 + (filter) * 0x4)
1091 /* Bitmask for bitfield vl_id{F}[B:0] */
1092 #define HW_ATL_RPF_VL_ID_F_MSK 0x00000FFF
1093 /* Inverted bitmask for bitfield vl_id{F}[B:0] */
1094 #define HW_ATL_RPF_VL_ID_F_MSKN 0xFFFFF000
1095 /* Lower bit position of bitfield vl_id{F}[B:0] */
1096 #define HW_ATL_RPF_VL_ID_F_SHIFT 0
1097 /* Width of bitfield vl_id{F}[B:0] */
1098 #define HW_ATL_RPF_VL_ID_F_WIDTH 12
1099 /* Default value of bitfield vl_id{F}[B:0] */
1100 #define HW_ATL_RPF_VL_ID_F_DEFAULT 0x0
1102 /* RX vl_rxq_en{F} Bitfield Definitions
1103 * Preprocessor definitions for the bitfield "vl_rxq{F}".
1104 * Parameter: filter {F} | stride size 0x4 | range [0, 15]
1105 * PORT="pif_rpf_vl_rxq_en_i"
1108 /* Register address for bitfield vl_rxq_en{F} */
1109 #define HW_ATL_RPF_VL_RXQ_EN_F_ADR(filter) (0x00005290 + (filter) * 0x4)
1110 /* Bitmask for bitfield vl_rxq_en{F} */
1111 #define HW_ATL_RPF_VL_RXQ_EN_F_MSK 0x10000000
1112 /* Inverted bitmask for bitfield vl_rxq_en{F}[ */
1113 #define HW_ATL_RPF_VL_RXQ_EN_F_MSKN 0xEFFFFFFF
1114 /* Lower bit position of bitfield vl_rxq_en{F} */
1115 #define HW_ATL_RPF_VL_RXQ_EN_F_SHIFT 28
1116 /* Width of bitfield vl_rxq_en{F} */
1117 #define HW_ATL_RPF_VL_RXQ_EN_F_WIDTH 1
1118 /* Default value of bitfield vl_rxq_en{F} */
1119 #define HW_ATL_RPF_VL_RXQ_EN_F_DEFAULT 0x0
1121 /* RX vl_rxq{F}[4:0] Bitfield Definitions
1122 * Preprocessor definitions for the bitfield "vl_rxq{F}[4:0]".
1123 * Parameter: filter {F} | stride size 0x4 | range [0, 15]
1124 * PORT="pif_rpf_vl_rxq0_i[4:0]"
1127 /* Register address for bitfield vl_rxq{F}[4:0] */
1128 #define HW_ATL_RPF_VL_RXQ_F_ADR(filter) (0x00005290 + (filter) * 0x4)
1129 /* Bitmask for bitfield vl_rxq{F}[4:0] */
1130 #define HW_ATL_RPF_VL_RXQ_F_MSK 0x01F00000
1131 /* Inverted bitmask for bitfield vl_rxq{F}[4:0] */
1132 #define HW_ATL_RPF_VL_RXQ_F_MSKN 0xFE0FFFFF
1133 /* Lower bit position of bitfield vl_rxq{F}[4:0] */
1134 #define HW_ATL_RPF_VL_RXQ_F_SHIFT 20
1135 /* Width of bitfield vl_rxw{F}[4:0] */
1136 #define HW_ATL_RPF_VL_RXQ_F_WIDTH 5
1137 /* Default value of bitfield vl_rxq{F}[4:0] */
1138 #define HW_ATL_RPF_VL_RXQ_F_DEFAULT 0x0
1140 /* rx et_en{f} bitfield definitions
1141 * preprocessor definitions for the bitfield "et_en{f}".
1142 * parameter: filter {f} | stride size 0x4 | range [0, 15]
1143 * port="pif_rpf_et_en_i[0]"
1146 /* register address for bitfield et_en{f} */
1147 #define HW_ATL_RPF_ET_ENF_ADR(filter) (0x00005300 + (filter) * 0x4)
1148 /* bitmask for bitfield et_en{f} */
1149 #define HW_ATL_RPF_ET_ENF_MSK 0x80000000
1150 /* inverted bitmask for bitfield et_en{f} */
1151 #define HW_ATL_RPF_ET_ENF_MSKN 0x7fffffff
1152 /* lower bit position of bitfield et_en{f} */
1153 #define HW_ATL_RPF_ET_ENF_SHIFT 31
1154 /* width of bitfield et_en{f} */
1155 #define HW_ATL_RPF_ET_ENF_WIDTH 1
1156 /* default value of bitfield et_en{f} */
1157 #define HW_ATL_RPF_ET_ENF_DEFAULT 0x0
1159 /* rx et_up{f}_en bitfield definitions
1160 * preprocessor definitions for the bitfield "et_up{f}_en".
1161 * parameter: filter {f} | stride size 0x4 | range [0, 15]
1162 * port="pif_rpf_et_up_en_i[0]"
1165 /* register address for bitfield et_up{f}_en */
1166 #define HW_ATL_RPF_ET_UPFEN_ADR(filter) (0x00005300 + (filter) * 0x4)
1167 /* bitmask for bitfield et_up{f}_en */
1168 #define HW_ATL_RPF_ET_UPFEN_MSK 0x40000000
1169 /* inverted bitmask for bitfield et_up{f}_en */
1170 #define HW_ATL_RPF_ET_UPFEN_MSKN 0xbfffffff
1171 /* lower bit position of bitfield et_up{f}_en */
1172 #define HW_ATL_RPF_ET_UPFEN_SHIFT 30
1173 /* width of bitfield et_up{f}_en */
1174 #define HW_ATL_RPF_ET_UPFEN_WIDTH 1
1175 /* default value of bitfield et_up{f}_en */
1176 #define HW_ATL_RPF_ET_UPFEN_DEFAULT 0x0
1178 /* rx et_rxq{f}_en bitfield definitions
1179 * preprocessor definitions for the bitfield "et_rxq{f}_en".
1180 * parameter: filter {f} | stride size 0x4 | range [0, 15]
1181 * port="pif_rpf_et_rxq_en_i[0]"
1184 /* register address for bitfield et_rxq{f}_en */
1185 #define HW_ATL_RPF_ET_RXQFEN_ADR(filter) (0x00005300 + (filter) * 0x4)
1186 /* bitmask for bitfield et_rxq{f}_en */
1187 #define HW_ATL_RPF_ET_RXQFEN_MSK 0x20000000
1188 /* inverted bitmask for bitfield et_rxq{f}_en */
1189 #define HW_ATL_RPF_ET_RXQFEN_MSKN 0xdfffffff
1190 /* lower bit position of bitfield et_rxq{f}_en */
1191 #define HW_ATL_RPF_ET_RXQFEN_SHIFT 29
1192 /* width of bitfield et_rxq{f}_en */
1193 #define HW_ATL_RPF_ET_RXQFEN_WIDTH 1
1194 /* default value of bitfield et_rxq{f}_en */
1195 #define HW_ATL_RPF_ET_RXQFEN_DEFAULT 0x0
1197 /* rx et_up{f}[2:0] bitfield definitions
1198 * preprocessor definitions for the bitfield "et_up{f}[2:0]".
1199 * parameter: filter {f} | stride size 0x4 | range [0, 15]
1200 * port="pif_rpf_et_up0_i[2:0]"
1203 /* register address for bitfield et_up{f}[2:0] */
1204 #define HW_ATL_RPF_ET_UPF_ADR(filter) (0x00005300 + (filter) * 0x4)
1205 /* bitmask for bitfield et_up{f}[2:0] */
1206 #define HW_ATL_RPF_ET_UPF_MSK 0x1c000000
1207 /* inverted bitmask for bitfield et_up{f}[2:0] */
1208 #define HW_ATL_RPF_ET_UPF_MSKN 0xe3ffffff
1209 /* lower bit position of bitfield et_up{f}[2:0] */
1210 #define HW_ATL_RPF_ET_UPF_SHIFT 26
1211 /* width of bitfield et_up{f}[2:0] */
1212 #define HW_ATL_RPF_ET_UPF_WIDTH 3
1213 /* default value of bitfield et_up{f}[2:0] */
1214 #define HW_ATL_RPF_ET_UPF_DEFAULT 0x0
1216 /* rx et_rxq{f}[4:0] bitfield definitions
1217 * preprocessor definitions for the bitfield "et_rxq{f}[4:0]".
1218 * parameter: filter {f} | stride size 0x4 | range [0, 15]
1219 * port="pif_rpf_et_rxq0_i[4:0]"
1222 /* register address for bitfield et_rxq{f}[4:0] */
1223 #define HW_ATL_RPF_ET_RXQF_ADR(filter) (0x00005300 + (filter) * 0x4)
1224 /* bitmask for bitfield et_rxq{f}[4:0] */
1225 #define HW_ATL_RPF_ET_RXQF_MSK 0x01f00000
1226 /* inverted bitmask for bitfield et_rxq{f}[4:0] */
1227 #define HW_ATL_RPF_ET_RXQF_MSKN 0xfe0fffff
1228 /* lower bit position of bitfield et_rxq{f}[4:0] */
1229 #define HW_ATL_RPF_ET_RXQF_SHIFT 20
1230 /* width of bitfield et_rxq{f}[4:0] */
1231 #define HW_ATL_RPF_ET_RXQF_WIDTH 5
1232 /* default value of bitfield et_rxq{f}[4:0] */
1233 #define HW_ATL_RPF_ET_RXQF_DEFAULT 0x0
1235 /* rx et_mng_rxq{f} bitfield definitions
1236 * preprocessor definitions for the bitfield "et_mng_rxq{f}".
1237 * parameter: filter {f} | stride size 0x4 | range [0, 15]
1238 * port="pif_rpf_et_mng_rxq_i[0]"
1241 /* register address for bitfield et_mng_rxq{f} */
1242 #define HW_ATL_RPF_ET_MNG_RXQF_ADR(filter) (0x00005300 + (filter) * 0x4)
1243 /* bitmask for bitfield et_mng_rxq{f} */
1244 #define HW_ATL_RPF_ET_MNG_RXQF_MSK 0x00080000
1245 /* inverted bitmask for bitfield et_mng_rxq{f} */
1246 #define HW_ATL_RPF_ET_MNG_RXQF_MSKN 0xfff7ffff
1247 /* lower bit position of bitfield et_mng_rxq{f} */
1248 #define HW_ATL_RPF_ET_MNG_RXQF_SHIFT 19
1249 /* width of bitfield et_mng_rxq{f} */
1250 #define HW_ATL_RPF_ET_MNG_RXQF_WIDTH 1
1251 /* default value of bitfield et_mng_rxq{f} */
1252 #define HW_ATL_RPF_ET_MNG_RXQF_DEFAULT 0x0
1254 /* rx et_act{f}[2:0] bitfield definitions
1255 * preprocessor definitions for the bitfield "et_act{f}[2:0]".
1256 * parameter: filter {f} | stride size 0x4 | range [0, 15]
1257 * port="pif_rpf_et_act0_i[2:0]"
1260 /* register address for bitfield et_act{f}[2:0] */
1261 #define HW_ATL_RPF_ET_ACTF_ADR(filter) (0x00005300 + (filter) * 0x4)
1262 /* bitmask for bitfield et_act{f}[2:0] */
1263 #define HW_ATL_RPF_ET_ACTF_MSK 0x00070000
1264 /* inverted bitmask for bitfield et_act{f}[2:0] */
1265 #define HW_ATL_RPF_ET_ACTF_MSKN 0xfff8ffff
1266 /* lower bit position of bitfield et_act{f}[2:0] */
1267 #define HW_ATL_RPF_ET_ACTF_SHIFT 16
1268 /* width of bitfield et_act{f}[2:0] */
1269 #define HW_ATL_RPF_ET_ACTF_WIDTH 3
1270 /* default value of bitfield et_act{f}[2:0] */
1271 #define HW_ATL_RPF_ET_ACTF_DEFAULT 0x0
1273 /* rx et_val{f}[f:0] bitfield definitions
1274 * preprocessor definitions for the bitfield "et_val{f}[f:0]".
1275 * parameter: filter {f} | stride size 0x4 | range [0, 15]
1276 * port="pif_rpf_et_val0_i[15:0]"
1279 /* register address for bitfield et_val{f}[f:0] */
1280 #define HW_ATL_RPF_ET_VALF_ADR(filter) (0x00005300 + (filter) * 0x4)
1281 /* bitmask for bitfield et_val{f}[f:0] */
1282 #define HW_ATL_RPF_ET_VALF_MSK 0x0000ffff
1283 /* inverted bitmask for bitfield et_val{f}[f:0] */
1284 #define HW_ATL_RPF_ET_VALF_MSKN 0xffff0000
1285 /* lower bit position of bitfield et_val{f}[f:0] */
1286 #define HW_ATL_RPF_ET_VALF_SHIFT 0
1287 /* width of bitfield et_val{f}[f:0] */
1288 #define HW_ATL_RPF_ET_VALF_WIDTH 16
1289 /* default value of bitfield et_val{f}[f:0] */
1290 #define HW_ATL_RPF_ET_VALF_DEFAULT 0x0
1292 /* RX l4_sp{D}[F:0] Bitfield Definitions
1293 * Preprocessor definitions for the bitfield "l4_sp{D}[F:0]".
1294 * Parameter: srcport {D} | stride size 0x4 | range [0, 7]
1295 * PORT="pif_rpf_l4_sp0_i[15:0]"
1298 /* Register address for bitfield l4_sp{D}[F:0] */
1299 #define HW_ATL_RPF_L4_SPD_ADR(srcport) (0x00005400u + (srcport) * 0x4)
1300 /* Bitmask for bitfield l4_sp{D}[F:0] */
1301 #define HW_ATL_RPF_L4_SPD_MSK 0x0000FFFFu
1302 /* Inverted bitmask for bitfield l4_sp{D}[F:0] */
1303 #define HW_ATL_RPF_L4_SPD_MSKN 0xFFFF0000u
1304 /* Lower bit position of bitfield l4_sp{D}[F:0] */
1305 #define HW_ATL_RPF_L4_SPD_SHIFT 0
1306 /* Width of bitfield l4_sp{D}[F:0] */
1307 #define HW_ATL_RPF_L4_SPD_WIDTH 16
1308 /* Default value of bitfield l4_sp{D}[F:0] */
1309 #define HW_ATL_RPF_L4_SPD_DEFAULT 0x0
1311 /* RX l4_dp{D}[F:0] Bitfield Definitions
1312 * Preprocessor definitions for the bitfield "l4_dp{D}[F:0]".
1313 * Parameter: destport {D} | stride size 0x4 | range [0, 7]
1314 * PORT="pif_rpf_l4_dp0_i[15:0]"
1317 /* Register address for bitfield l4_dp{D}[F:0] */
1318 #define HW_ATL_RPF_L4_DPD_ADR(destport) (0x00005420u + (destport) * 0x4)
1319 /* Bitmask for bitfield l4_dp{D}[F:0] */
1320 #define HW_ATL_RPF_L4_DPD_MSK 0x0000FFFFu
1321 /* Inverted bitmask for bitfield l4_dp{D}[F:0] */
1322 #define HW_ATL_RPF_L4_DPD_MSKN 0xFFFF0000u
1323 /* Lower bit position of bitfield l4_dp{D}[F:0] */
1324 #define HW_ATL_RPF_L4_DPD_SHIFT 0
1325 /* Width of bitfield l4_dp{D}[F:0] */
1326 #define HW_ATL_RPF_L4_DPD_WIDTH 16
1327 /* Default value of bitfield l4_dp{D}[F:0] */
1328 #define HW_ATL_RPF_L4_DPD_DEFAULT 0x0
1330 /* rx ipv4_chk_en bitfield definitions
1331 * preprocessor definitions for the bitfield "ipv4_chk_en".
1332 * port="pif_rpo_ipv4_chk_en_i"
1335 /* register address for bitfield ipv4_chk_en */
1336 #define HW_ATL_RPO_IPV4CHK_EN_ADR 0x00005580
1337 /* bitmask for bitfield ipv4_chk_en */
1338 #define HW_ATL_RPO_IPV4CHK_EN_MSK 0x00000002
1339 /* inverted bitmask for bitfield ipv4_chk_en */
1340 #define HW_ATL_RPO_IPV4CHK_EN_MSKN 0xfffffffd
1341 /* lower bit position of bitfield ipv4_chk_en */
1342 #define HW_ATL_RPO_IPV4CHK_EN_SHIFT 1
1343 /* width of bitfield ipv4_chk_en */
1344 #define HW_ATL_RPO_IPV4CHK_EN_WIDTH 1
1345 /* default value of bitfield ipv4_chk_en */
1346 #define HW_ATL_RPO_IPV4CHK_EN_DEFAULT 0x0
1348 /* rx desc{d}_vl_strip bitfield definitions
1349 * preprocessor definitions for the bitfield "desc{d}_vl_strip".
1350 * parameter: descriptor {d} | stride size 0x20 | range [0, 31]
1351 * port="pif_rpo_desc_vl_strip_i[0]"
1354 /* register address for bitfield desc{d}_vl_strip */
1355 #define HW_ATL_RPO_DESCDVL_STRIP_ADR(descriptor) \
1356 (0x00005b08 + (descriptor) * 0x20)
1357 /* bitmask for bitfield desc{d}_vl_strip */
1358 #define HW_ATL_RPO_DESCDVL_STRIP_MSK 0x20000000
1359 /* inverted bitmask for bitfield desc{d}_vl_strip */
1360 #define HW_ATL_RPO_DESCDVL_STRIP_MSKN 0xdfffffff
1361 /* lower bit position of bitfield desc{d}_vl_strip */
1362 #define HW_ATL_RPO_DESCDVL_STRIP_SHIFT 29
1363 /* width of bitfield desc{d}_vl_strip */
1364 #define HW_ATL_RPO_DESCDVL_STRIP_WIDTH 1
1365 /* default value of bitfield desc{d}_vl_strip */
1366 #define HW_ATL_RPO_DESCDVL_STRIP_DEFAULT 0x0
1368 /* rx l4_chk_en bitfield definitions
1369 * preprocessor definitions for the bitfield "l4_chk_en".
1370 * port="pif_rpo_l4_chk_en_i"
1373 /* register address for bitfield l4_chk_en */
1374 #define HW_ATL_RPOL4CHK_EN_ADR 0x00005580
1375 /* bitmask for bitfield l4_chk_en */
1376 #define HW_ATL_RPOL4CHK_EN_MSK 0x00000001
1377 /* inverted bitmask for bitfield l4_chk_en */
1378 #define HW_ATL_RPOL4CHK_EN_MSKN 0xfffffffe
1379 /* lower bit position of bitfield l4_chk_en */
1380 #define HW_ATL_RPOL4CHK_EN_SHIFT 0
1381 /* width of bitfield l4_chk_en */
1382 #define HW_ATL_RPOL4CHK_EN_WIDTH 1
1383 /* default value of bitfield l4_chk_en */
1384 #define HW_ATL_RPOL4CHK_EN_DEFAULT 0x0
1386 /* RX outer_vl_ins_mode Bitfield Definitions
1387 * Preprocessor definitions for the bitfield "outer_vl_ins_mode".
1388 * PORT="pif_rpo_outer_vl_mode_i"
1391 /* Register address for bitfield outer_vl_ins_mode */
1392 #define HW_ATL_RPO_OUTER_VL_INS_MODE_ADR 0x00005580
1393 /* Bitmask for bitfield outer_vl_ins_mode */
1394 #define HW_ATL_RPO_OUTER_VL_INS_MODE_MSK 0x00000004
1395 /* Inverted bitmask for bitfield outer_vl_ins_mode */
1396 #define HW_ATL_RPO_OUTER_VL_INS_MODE_MSKN 0xFFFFFFFB
1397 /* Lower bit position of bitfield outer_vl_ins_mode */
1398 #define HW_ATL_RPO_OUTER_VL_INS_MODE_SHIFT 2
1399 /* Width of bitfield outer_vl_ins_mode */
1400 #define HW_ATL_RPO_OUTER_VL_INS_MODE_WIDTH 1
1401 /* Default value of bitfield outer_vl_ins_mode */
1402 #define HW_ATL_RPO_OUTER_VL_INS_MODE_DEFAULT 0x0
1404 /* rx reg_res_dsbl bitfield definitions
1405 * preprocessor definitions for the bitfield "reg_res_dsbl".
1406 * port="pif_rx_reg_res_dsbl_i"
1409 /* register address for bitfield reg_res_dsbl */
1410 #define HW_ATL_RX_REG_RES_DSBL_ADR 0x00005000
1411 /* bitmask for bitfield reg_res_dsbl */
1412 #define HW_ATL_RX_REG_RES_DSBL_MSK 0x20000000
1413 /* inverted bitmask for bitfield reg_res_dsbl */
1414 #define HW_ATL_RX_REG_RES_DSBL_MSKN 0xdfffffff
1415 /* lower bit position of bitfield reg_res_dsbl */
1416 #define HW_ATL_RX_REG_RES_DSBL_SHIFT 29
1417 /* width of bitfield reg_res_dsbl */
1418 #define HW_ATL_RX_REG_RES_DSBL_WIDTH 1
1419 /* default value of bitfield reg_res_dsbl */
1420 #define HW_ATL_RX_REG_RES_DSBL_DEFAULT 0x1
1422 /* tx dca{d}_cpuid[7:0] bitfield definitions
1423 * preprocessor definitions for the bitfield "dca{d}_cpuid[7:0]".
1424 * parameter: dca {d} | stride size 0x4 | range [0, 31]
1425 * port="pif_tdm_dca0_cpuid_i[7:0]"
1428 /* register address for bitfield dca{d}_cpuid[7:0] */
1429 #define HW_ATL_TDM_DCADCPUID_ADR(dca) (0x00008400 + (dca) * 0x4)
1430 /* bitmask for bitfield dca{d}_cpuid[7:0] */
1431 #define HW_ATL_TDM_DCADCPUID_MSK 0x000000ff
1432 /* inverted bitmask for bitfield dca{d}_cpuid[7:0] */
1433 #define HW_ATL_TDM_DCADCPUID_MSKN 0xffffff00
1434 /* lower bit position of bitfield dca{d}_cpuid[7:0] */
1435 #define HW_ATL_TDM_DCADCPUID_SHIFT 0
1436 /* width of bitfield dca{d}_cpuid[7:0] */
1437 #define HW_ATL_TDM_DCADCPUID_WIDTH 8
1438 /* default value of bitfield dca{d}_cpuid[7:0] */
1439 #define HW_ATL_TDM_DCADCPUID_DEFAULT 0x0
1441 /* tx lso_en[1f:0] bitfield definitions
1442 * preprocessor definitions for the bitfield "lso_en[1f:0]".
1443 * port="pif_tdm_lso_en_i[31:0]"
1446 /* register address for bitfield lso_en[1f:0] */
1447 #define HW_ATL_TDM_LSO_EN_ADR 0x00007810
1448 /* bitmask for bitfield lso_en[1f:0] */
1449 #define HW_ATL_TDM_LSO_EN_MSK 0xffffffff
1450 /* inverted bitmask for bitfield lso_en[1f:0] */
1451 #define HW_ATL_TDM_LSO_EN_MSKN 0x00000000
1452 /* lower bit position of bitfield lso_en[1f:0] */
1453 #define HW_ATL_TDM_LSO_EN_SHIFT 0
1454 /* width of bitfield lso_en[1f:0] */
1455 #define HW_ATL_TDM_LSO_EN_WIDTH 32
1456 /* default value of bitfield lso_en[1f:0] */
1457 #define HW_ATL_TDM_LSO_EN_DEFAULT 0x0
1459 /* tx dca_en bitfield definitions
1460 * preprocessor definitions for the bitfield "dca_en".
1461 * port="pif_tdm_dca_en_i"
1464 /* register address for bitfield dca_en */
1465 #define HW_ATL_TDM_DCA_EN_ADR 0x00008480
1466 /* bitmask for bitfield dca_en */
1467 #define HW_ATL_TDM_DCA_EN_MSK 0x80000000
1468 /* inverted bitmask for bitfield dca_en */
1469 #define HW_ATL_TDM_DCA_EN_MSKN 0x7fffffff
1470 /* lower bit position of bitfield dca_en */
1471 #define HW_ATL_TDM_DCA_EN_SHIFT 31
1472 /* width of bitfield dca_en */
1473 #define HW_ATL_TDM_DCA_EN_WIDTH 1
1474 /* default value of bitfield dca_en */
1475 #define HW_ATL_TDM_DCA_EN_DEFAULT 0x1
1477 /* tx dca_mode[3:0] bitfield definitions
1478 * preprocessor definitions for the bitfield "dca_mode[3:0]".
1479 * port="pif_tdm_dca_mode_i[3:0]"
1482 /* register address for bitfield dca_mode[3:0] */
1483 #define HW_ATL_TDM_DCA_MODE_ADR 0x00008480
1484 /* bitmask for bitfield dca_mode[3:0] */
1485 #define HW_ATL_TDM_DCA_MODE_MSK 0x0000000f
1486 /* inverted bitmask for bitfield dca_mode[3:0] */
1487 #define HW_ATL_TDM_DCA_MODE_MSKN 0xfffffff0
1488 /* lower bit position of bitfield dca_mode[3:0] */
1489 #define HW_ATL_TDM_DCA_MODE_SHIFT 0
1490 /* width of bitfield dca_mode[3:0] */
1491 #define HW_ATL_TDM_DCA_MODE_WIDTH 4
1492 /* default value of bitfield dca_mode[3:0] */
1493 #define HW_ATL_TDM_DCA_MODE_DEFAULT 0x0
1495 /* tx dca{d}_desc_en bitfield definitions
1496 * preprocessor definitions for the bitfield "dca{d}_desc_en".
1497 * parameter: dca {d} | stride size 0x4 | range [0, 31]
1498 * port="pif_tdm_dca_desc_en_i[0]"
1501 /* register address for bitfield dca{d}_desc_en */
1502 #define HW_ATL_TDM_DCADDESC_EN_ADR(dca) (0x00008400 + (dca) * 0x4)
1503 /* bitmask for bitfield dca{d}_desc_en */
1504 #define HW_ATL_TDM_DCADDESC_EN_MSK 0x80000000
1505 /* inverted bitmask for bitfield dca{d}_desc_en */
1506 #define HW_ATL_TDM_DCADDESC_EN_MSKN 0x7fffffff
1507 /* lower bit position of bitfield dca{d}_desc_en */
1508 #define HW_ATL_TDM_DCADDESC_EN_SHIFT 31
1509 /* width of bitfield dca{d}_desc_en */
1510 #define HW_ATL_TDM_DCADDESC_EN_WIDTH 1
1511 /* default value of bitfield dca{d}_desc_en */
1512 #define HW_ATL_TDM_DCADDESC_EN_DEFAULT 0x0
1514 /* tx desc{d}_en bitfield definitions
1515 * preprocessor definitions for the bitfield "desc{d}_en".
1516 * parameter: descriptor {d} | stride size 0x40 | range [0, 31]
1517 * port="pif_tdm_desc_en_i[0]"
1520 /* register address for bitfield desc{d}_en */
1521 #define HW_ATL_TDM_DESCDEN_ADR(descriptor) (0x00007c08 + (descriptor) * 0x40)
1522 /* bitmask for bitfield desc{d}_en */
1523 #define HW_ATL_TDM_DESCDEN_MSK 0x80000000
1524 /* inverted bitmask for bitfield desc{d}_en */
1525 #define HW_ATL_TDM_DESCDEN_MSKN 0x7fffffff
1526 /* lower bit position of bitfield desc{d}_en */
1527 #define HW_ATL_TDM_DESCDEN_SHIFT 31
1528 /* width of bitfield desc{d}_en */
1529 #define HW_ATL_TDM_DESCDEN_WIDTH 1
1530 /* default value of bitfield desc{d}_en */
1531 #define HW_ATL_TDM_DESCDEN_DEFAULT 0x0
1533 /* tx desc{d}_hd[c:0] bitfield definitions
1534 * preprocessor definitions for the bitfield "desc{d}_hd[c:0]".
1535 * parameter: descriptor {d} | stride size 0x40 | range [0, 31]
1536 * port="tdm_pif_desc0_hd_o[12:0]"
1539 /* register address for bitfield desc{d}_hd[c:0] */
1540 #define HW_ATL_TDM_DESCDHD_ADR(descriptor) (0x00007c0c + (descriptor) * 0x40)
1541 /* bitmask for bitfield desc{d}_hd[c:0] */
1542 #define HW_ATL_TDM_DESCDHD_MSK 0x00001fff
1543 /* inverted bitmask for bitfield desc{d}_hd[c:0] */
1544 #define HW_ATL_TDM_DESCDHD_MSKN 0xffffe000
1545 /* lower bit position of bitfield desc{d}_hd[c:0] */
1546 #define HW_ATL_TDM_DESCDHD_SHIFT 0
1547 /* width of bitfield desc{d}_hd[c:0] */
1548 #define HW_ATL_TDM_DESCDHD_WIDTH 13
1550 /* tx desc{d}_len[9:0] bitfield definitions
1551 * preprocessor definitions for the bitfield "desc{d}_len[9:0]".
1552 * parameter: descriptor {d} | stride size 0x40 | range [0, 31]
1553 * port="pif_tdm_desc0_len_i[9:0]"
1556 /* register address for bitfield desc{d}_len[9:0] */
1557 #define HW_ATL_TDM_DESCDLEN_ADR(descriptor) (0x00007c08 + (descriptor) * 0x40)
1558 /* bitmask for bitfield desc{d}_len[9:0] */
1559 #define HW_ATL_TDM_DESCDLEN_MSK 0x00001ff8
1560 /* inverted bitmask for bitfield desc{d}_len[9:0] */
1561 #define HW_ATL_TDM_DESCDLEN_MSKN 0xffffe007
1562 /* lower bit position of bitfield desc{d}_len[9:0] */
1563 #define HW_ATL_TDM_DESCDLEN_SHIFT 3
1564 /* width of bitfield desc{d}_len[9:0] */
1565 #define HW_ATL_TDM_DESCDLEN_WIDTH 10
1566 /* default value of bitfield desc{d}_len[9:0] */
1567 #define HW_ATL_TDM_DESCDLEN_DEFAULT 0x0
1569 /* tx int_desc_wrb_en bitfield definitions
1570 * preprocessor definitions for the bitfield "int_desc_wrb_en".
1571 * port="pif_tdm_int_desc_wrb_en_i"
1574 /* register address for bitfield int_desc_wrb_en */
1575 #define HW_ATL_TDM_INT_DESC_WRB_EN_ADR 0x00007b40
1576 /* bitmask for bitfield int_desc_wrb_en */
1577 #define HW_ATL_TDM_INT_DESC_WRB_EN_MSK 0x00000002
1578 /* inverted bitmask for bitfield int_desc_wrb_en */
1579 #define HW_ATL_TDM_INT_DESC_WRB_EN_MSKN 0xfffffffd
1580 /* lower bit position of bitfield int_desc_wrb_en */
1581 #define HW_ATL_TDM_INT_DESC_WRB_EN_SHIFT 1
1582 /* width of bitfield int_desc_wrb_en */
1583 #define HW_ATL_TDM_INT_DESC_WRB_EN_WIDTH 1
1584 /* default value of bitfield int_desc_wrb_en */
1585 #define HW_ATL_TDM_INT_DESC_WRB_EN_DEFAULT 0x0
1587 /* tx desc{d}_wrb_thresh[6:0] bitfield definitions
1588 * preprocessor definitions for the bitfield "desc{d}_wrb_thresh[6:0]".
1589 * parameter: descriptor {d} | stride size 0x40 | range [0, 31]
1590 * port="pif_tdm_desc0_wrb_thresh_i[6:0]"
1593 /* register address for bitfield desc{d}_wrb_thresh[6:0] */
1594 #define HW_ATL_TDM_DESCDWRB_THRESH_ADR(descriptor) \
1595 (0x00007c18 + (descriptor) * 0x40)
1596 /* bitmask for bitfield desc{d}_wrb_thresh[6:0] */
1597 #define HW_ATL_TDM_DESCDWRB_THRESH_MSK 0x00007f00
1598 /* inverted bitmask for bitfield desc{d}_wrb_thresh[6:0] */
1599 #define HW_ATL_TDM_DESCDWRB_THRESH_MSKN 0xffff80ff
1600 /* lower bit position of bitfield desc{d}_wrb_thresh[6:0] */
1601 #define HW_ATL_TDM_DESCDWRB_THRESH_SHIFT 8
1602 /* width of bitfield desc{d}_wrb_thresh[6:0] */
1603 #define HW_ATL_TDM_DESCDWRB_THRESH_WIDTH 7
1604 /* default value of bitfield desc{d}_wrb_thresh[6:0] */
1605 #define HW_ATL_TDM_DESCDWRB_THRESH_DEFAULT 0x0
1607 /* tx lso_tcp_flag_first[b:0] bitfield definitions
1608 * preprocessor definitions for the bitfield "lso_tcp_flag_first[b:0]".
1609 * port="pif_thm_lso_tcp_flag_first_i[11:0]"
1612 /* register address for bitfield lso_tcp_flag_first[b:0] */
1613 #define HW_ATL_THM_LSO_TCP_FLAG_FIRST_ADR 0x00007820
1614 /* bitmask for bitfield lso_tcp_flag_first[b:0] */
1615 #define HW_ATL_THM_LSO_TCP_FLAG_FIRST_MSK 0x00000fff
1616 /* inverted bitmask for bitfield lso_tcp_flag_first[b:0] */
1617 #define HW_ATL_THM_LSO_TCP_FLAG_FIRST_MSKN 0xfffff000
1618 /* lower bit position of bitfield lso_tcp_flag_first[b:0] */
1619 #define HW_ATL_THM_LSO_TCP_FLAG_FIRST_SHIFT 0
1620 /* width of bitfield lso_tcp_flag_first[b:0] */
1621 #define HW_ATL_THM_LSO_TCP_FLAG_FIRST_WIDTH 12
1622 /* default value of bitfield lso_tcp_flag_first[b:0] */
1623 #define HW_ATL_THM_LSO_TCP_FLAG_FIRST_DEFAULT 0x0
1625 /* tx lso_tcp_flag_last[b:0] bitfield definitions
1626 * preprocessor definitions for the bitfield "lso_tcp_flag_last[b:0]".
1627 * port="pif_thm_lso_tcp_flag_last_i[11:0]"
1630 /* register address for bitfield lso_tcp_flag_last[b:0] */
1631 #define HW_ATL_THM_LSO_TCP_FLAG_LAST_ADR 0x00007824
1632 /* bitmask for bitfield lso_tcp_flag_last[b:0] */
1633 #define HW_ATL_THM_LSO_TCP_FLAG_LAST_MSK 0x00000fff
1634 /* inverted bitmask for bitfield lso_tcp_flag_last[b:0] */
1635 #define HW_ATL_THM_LSO_TCP_FLAG_LAST_MSKN 0xfffff000
1636 /* lower bit position of bitfield lso_tcp_flag_last[b:0] */
1637 #define HW_ATL_THM_LSO_TCP_FLAG_LAST_SHIFT 0
1638 /* width of bitfield lso_tcp_flag_last[b:0] */
1639 #define HW_ATL_THM_LSO_TCP_FLAG_LAST_WIDTH 12
1640 /* default value of bitfield lso_tcp_flag_last[b:0] */
1641 #define HW_ATL_THM_LSO_TCP_FLAG_LAST_DEFAULT 0x0
1643 /* tx lso_tcp_flag_mid[b:0] bitfield definitions
1644 * preprocessor definitions for the bitfield "lso_tcp_flag_mid[b:0]".
1645 * port="pif_thm_lso_tcp_flag_mid_i[11:0]"
1648 /* Register address for bitfield lro_rsc_max[1F:0] */
1649 #define HW_ATL_RPO_LRO_RSC_MAX_ADR 0x00005598
1650 /* Bitmask for bitfield lro_rsc_max[1F:0] */
1651 #define HW_ATL_RPO_LRO_RSC_MAX_MSK 0xFFFFFFFF
1652 /* Inverted bitmask for bitfield lro_rsc_max[1F:0] */
1653 #define HW_ATL_RPO_LRO_RSC_MAX_MSKN 0x00000000
1654 /* Lower bit position of bitfield lro_rsc_max[1F:0] */
1655 #define HW_ATL_RPO_LRO_RSC_MAX_SHIFT 0
1656 /* Width of bitfield lro_rsc_max[1F:0] */
1657 #define HW_ATL_RPO_LRO_RSC_MAX_WIDTH 32
1658 /* Default value of bitfield lro_rsc_max[1F:0] */
1659 #define HW_ATL_RPO_LRO_RSC_MAX_DEFAULT 0x0
1661 /* RX lro_en[1F:0] Bitfield Definitions
1662 * Preprocessor definitions for the bitfield "lro_en[1F:0]".
1663 * PORT="pif_rpo_lro_en_i[31:0]"
1666 /* Register address for bitfield lro_en[1F:0] */
1667 #define HW_ATL_RPO_LRO_EN_ADR 0x00005590
1668 /* Bitmask for bitfield lro_en[1F:0] */
1669 #define HW_ATL_RPO_LRO_EN_MSK 0xFFFFFFFF
1670 /* Inverted bitmask for bitfield lro_en[1F:0] */
1671 #define HW_ATL_RPO_LRO_EN_MSKN 0x00000000
1672 /* Lower bit position of bitfield lro_en[1F:0] */
1673 #define HW_ATL_RPO_LRO_EN_SHIFT 0
1674 /* Width of bitfield lro_en[1F:0] */
1675 #define HW_ATL_RPO_LRO_EN_WIDTH 32
1676 /* Default value of bitfield lro_en[1F:0] */
1677 #define HW_ATL_RPO_LRO_EN_DEFAULT 0x0
1679 /* RX lro_ptopt_en Bitfield Definitions
1680 * Preprocessor definitions for the bitfield "lro_ptopt_en".
1681 * PORT="pif_rpo_lro_ptopt_en_i"
1684 /* Register address for bitfield lro_ptopt_en */
1685 #define HW_ATL_RPO_LRO_PTOPT_EN_ADR 0x00005594
1686 /* Bitmask for bitfield lro_ptopt_en */
1687 #define HW_ATL_RPO_LRO_PTOPT_EN_MSK 0x00008000
1688 /* Inverted bitmask for bitfield lro_ptopt_en */
1689 #define HW_ATL_RPO_LRO_PTOPT_EN_MSKN 0xFFFF7FFF
1690 /* Lower bit position of bitfield lro_ptopt_en */
1691 #define HW_ATL_RPO_LRO_PTOPT_EN_SHIFT 15
1692 /* Width of bitfield lro_ptopt_en */
1693 #define HW_ATL_RPO_LRO_PTOPT_EN_WIDTH 1
1694 /* Default value of bitfield lro_ptopt_en */
1695 #define HW_ATL_RPO_LRO_PTOPT_EN_DEFALT 0x1
1697 /* RX lro_q_ses_lmt Bitfield Definitions
1698 * Preprocessor definitions for the bitfield "lro_q_ses_lmt".
1699 * PORT="pif_rpo_lro_q_ses_lmt_i[1:0]"
1702 /* Register address for bitfield lro_q_ses_lmt */
1703 #define HW_ATL_RPO_LRO_QSES_LMT_ADR 0x00005594
1704 /* Bitmask for bitfield lro_q_ses_lmt */
1705 #define HW_ATL_RPO_LRO_QSES_LMT_MSK 0x00003000
1706 /* Inverted bitmask for bitfield lro_q_ses_lmt */
1707 #define HW_ATL_RPO_LRO_QSES_LMT_MSKN 0xFFFFCFFF
1708 /* Lower bit position of bitfield lro_q_ses_lmt */
1709 #define HW_ATL_RPO_LRO_QSES_LMT_SHIFT 12
1710 /* Width of bitfield lro_q_ses_lmt */
1711 #define HW_ATL_RPO_LRO_QSES_LMT_WIDTH 2
1712 /* Default value of bitfield lro_q_ses_lmt */
1713 #define HW_ATL_RPO_LRO_QSES_LMT_DEFAULT 0x1
1715 /* RX lro_tot_dsc_lmt[1:0] Bitfield Definitions
1716 * Preprocessor definitions for the bitfield "lro_tot_dsc_lmt[1:0]".
1717 * PORT="pif_rpo_lro_tot_dsc_lmt_i[1:0]"
1720 /* Register address for bitfield lro_tot_dsc_lmt[1:0] */
1721 #define HW_ATL_RPO_LRO_TOT_DSC_LMT_ADR 0x00005594
1722 /* Bitmask for bitfield lro_tot_dsc_lmt[1:0] */
1723 #define HW_ATL_RPO_LRO_TOT_DSC_LMT_MSK 0x00000060
1724 /* Inverted bitmask for bitfield lro_tot_dsc_lmt[1:0] */
1725 #define HW_ATL_RPO_LRO_TOT_DSC_LMT_MSKN 0xFFFFFF9F
1726 /* Lower bit position of bitfield lro_tot_dsc_lmt[1:0] */
1727 #define HW_ATL_RPO_LRO_TOT_DSC_LMT_SHIFT 5
1728 /* Width of bitfield lro_tot_dsc_lmt[1:0] */
1729 #define HW_ATL_RPO_LRO_TOT_DSC_LMT_WIDTH 2
1730 /* Default value of bitfield lro_tot_dsc_lmt[1:0] */
1731 #define HW_ATL_RPO_LRO_TOT_DSC_LMT_DEFALT 0x1
1733 /* RX lro_pkt_min[4:0] Bitfield Definitions
1734 * Preprocessor definitions for the bitfield "lro_pkt_min[4:0]".
1735 * PORT="pif_rpo_lro_pkt_min_i[4:0]"
1738 /* Register address for bitfield lro_pkt_min[4:0] */
1739 #define HW_ATL_RPO_LRO_PKT_MIN_ADR 0x00005594
1740 /* Bitmask for bitfield lro_pkt_min[4:0] */
1741 #define HW_ATL_RPO_LRO_PKT_MIN_MSK 0x0000001F
1742 /* Inverted bitmask for bitfield lro_pkt_min[4:0] */
1743 #define HW_ATL_RPO_LRO_PKT_MIN_MSKN 0xFFFFFFE0
1744 /* Lower bit position of bitfield lro_pkt_min[4:0] */
1745 #define HW_ATL_RPO_LRO_PKT_MIN_SHIFT 0
1746 /* Width of bitfield lro_pkt_min[4:0] */
1747 #define HW_ATL_RPO_LRO_PKT_MIN_WIDTH 5
1748 /* Default value of bitfield lro_pkt_min[4:0] */
1749 #define HW_ATL_RPO_LRO_PKT_MIN_DEFAULT 0x8
1751 /* Width of bitfield lro{L}_des_max[1:0] */
1752 #define HW_ATL_RPO_LRO_LDES_MAX_WIDTH 2
1753 /* Default value of bitfield lro{L}_des_max[1:0] */
1754 #define HW_ATL_RPO_LRO_LDES_MAX_DEFAULT 0x0
1756 /* RX lro_tb_div[11:0] Bitfield Definitions
1757 * Preprocessor definitions for the bitfield "lro_tb_div[11:0]".
1758 * PORT="pif_rpo_lro_tb_div_i[11:0]"
1761 /* Register address for bitfield lro_tb_div[11:0] */
1762 #define HW_ATL_RPO_LRO_TB_DIV_ADR 0x00005620
1763 /* Bitmask for bitfield lro_tb_div[11:0] */
1764 #define HW_ATL_RPO_LRO_TB_DIV_MSK 0xFFF00000
1765 /* Inverted bitmask for bitfield lro_tb_div[11:0] */
1766 #define HW_ATL_RPO_LRO_TB_DIV_MSKN 0x000FFFFF
1767 /* Lower bit position of bitfield lro_tb_div[11:0] */
1768 #define HW_ATL_RPO_LRO_TB_DIV_SHIFT 20
1769 /* Width of bitfield lro_tb_div[11:0] */
1770 #define HW_ATL_RPO_LRO_TB_DIV_WIDTH 12
1771 /* Default value of bitfield lro_tb_div[11:0] */
1772 #define HW_ATL_RPO_LRO_TB_DIV_DEFAULT 0xC35
1774 /* RX lro_ina_ival[9:0] Bitfield Definitions
1775 * Preprocessor definitions for the bitfield "lro_ina_ival[9:0]".
1776 * PORT="pif_rpo_lro_ina_ival_i[9:0]"
1779 /* Register address for bitfield lro_ina_ival[9:0] */
1780 #define HW_ATL_RPO_LRO_INA_IVAL_ADR 0x00005620
1781 /* Bitmask for bitfield lro_ina_ival[9:0] */
1782 #define HW_ATL_RPO_LRO_INA_IVAL_MSK 0x000FFC00
1783 /* Inverted bitmask for bitfield lro_ina_ival[9:0] */
1784 #define HW_ATL_RPO_LRO_INA_IVAL_MSKN 0xFFF003FF
1785 /* Lower bit position of bitfield lro_ina_ival[9:0] */
1786 #define HW_ATL_RPO_LRO_INA_IVAL_SHIFT 10
1787 /* Width of bitfield lro_ina_ival[9:0] */
1788 #define HW_ATL_RPO_LRO_INA_IVAL_WIDTH 10
1789 /* Default value of bitfield lro_ina_ival[9:0] */
1790 #define HW_ATL_RPO_LRO_INA_IVAL_DEFAULT 0xA
1792 /* RX lro_max_ival[9:0] Bitfield Definitions
1793 * Preprocessor definitions for the bitfield "lro_max_ival[9:0]".
1794 * PORT="pif_rpo_lro_max_ival_i[9:0]"
1797 /* Register address for bitfield lro_max_ival[9:0] */
1798 #define HW_ATL_RPO_LRO_MAX_IVAL_ADR 0x00005620
1799 /* Bitmask for bitfield lro_max_ival[9:0] */
1800 #define HW_ATL_RPO_LRO_MAX_IVAL_MSK 0x000003FF
1801 /* Inverted bitmask for bitfield lro_max_ival[9:0] */
1802 #define HW_ATL_RPO_LRO_MAX_IVAL_MSKN 0xFFFFFC00
1803 /* Lower bit position of bitfield lro_max_ival[9:0] */
1804 #define HW_ATL_RPO_LRO_MAX_IVAL_SHIFT 0
1805 /* Width of bitfield lro_max_ival[9:0] */
1806 #define HW_ATL_RPO_LRO_MAX_IVAL_WIDTH 10
1807 /* Default value of bitfield lro_max_ival[9:0] */
1808 #define HW_ATL_RPO_LRO_MAX_IVAL_DEFAULT 0x19
1810 /* TX dca{D}_cpuid[7:0] Bitfield Definitions
1811 * Preprocessor definitions for the bitfield "dca{D}_cpuid[7:0]".
1812 * Parameter: DCA {D} | stride size 0x4 | range [0, 31]
1813 * PORT="pif_tdm_dca0_cpuid_i[7:0]"
1816 /* Register address for bitfield dca{D}_cpuid[7:0] */
1817 #define HW_ATL_TDM_DCA_DCPUID_ADR(dca) (0x00008400 + (dca) * 0x4)
1818 /* Bitmask for bitfield dca{D}_cpuid[7:0] */
1819 #define HW_ATL_TDM_DCA_DCPUID_MSK 0x000000FF
1820 /* Inverted bitmask for bitfield dca{D}_cpuid[7:0] */
1821 #define HW_ATL_TDM_DCA_DCPUID_MSKN 0xFFFFFF00
1822 /* Lower bit position of bitfield dca{D}_cpuid[7:0] */
1823 #define HW_ATL_TDM_DCA_DCPUID_SHIFT 0
1824 /* Width of bitfield dca{D}_cpuid[7:0] */
1825 #define HW_ATL_TDM_DCA_DCPUID_WIDTH 8
1826 /* Default value of bitfield dca{D}_cpuid[7:0] */
1827 #define HW_ATL_TDM_DCA_DCPUID_DEFAULT 0x0
1829 /* TX dca{D}_desc_en Bitfield Definitions
1830 * Preprocessor definitions for the bitfield "dca{D}_desc_en".
1831 * Parameter: DCA {D} | stride size 0x4 | range [0, 31]
1832 * PORT="pif_tdm_dca_desc_en_i[0]"
1835 /* Register address for bitfield dca{D}_desc_en */
1836 #define HW_ATL_TDM_DCA_DDESC_EN_ADR(dca) (0x00008400 + (dca) * 0x4)
1837 /* Bitmask for bitfield dca{D}_desc_en */
1838 #define HW_ATL_TDM_DCA_DDESC_EN_MSK 0x80000000
1839 /* Inverted bitmask for bitfield dca{D}_desc_en */
1840 #define HW_ATL_TDM_DCA_DDESC_EN_MSKN 0x7FFFFFFF
1841 /* Lower bit position of bitfield dca{D}_desc_en */
1842 #define HW_ATL_TDM_DCA_DDESC_EN_SHIFT 31
1843 /* Width of bitfield dca{D}_desc_en */
1844 #define HW_ATL_TDM_DCA_DDESC_EN_WIDTH 1
1845 /* Default value of bitfield dca{D}_desc_en */
1846 #define HW_ATL_TDM_DCA_DDESC_EN_DEFAULT 0x0
1848 /* TX desc{D}_en Bitfield Definitions
1849 * Preprocessor definitions for the bitfield "desc{D}_en".
1850 * Parameter: descriptor {D} | stride size 0x40 | range [0, 31]
1851 * PORT="pif_tdm_desc_en_i[0]"
1854 /* Register address for bitfield desc{D}_en */
1855 #define HW_ATL_TDM_DESC_DEN_ADR(descriptor) (0x00007C08 + (descriptor) * 0x40)
1856 /* Bitmask for bitfield desc{D}_en */
1857 #define HW_ATL_TDM_DESC_DEN_MSK 0x80000000
1858 /* Inverted bitmask for bitfield desc{D}_en */
1859 #define HW_ATL_TDM_DESC_DEN_MSKN 0x7FFFFFFF
1860 /* Lower bit position of bitfield desc{D}_en */
1861 #define HW_ATL_TDM_DESC_DEN_SHIFT 31
1862 /* Width of bitfield desc{D}_en */
1863 #define HW_ATL_TDM_DESC_DEN_WIDTH 1
1864 /* Default value of bitfield desc{D}_en */
1865 #define HW_ATL_TDM_DESC_DEN_DEFAULT 0x0
1867 /* TX desc{D}_hd[C:0] Bitfield Definitions
1868 * Preprocessor definitions for the bitfield "desc{D}_hd[C:0]".
1869 * Parameter: descriptor {D} | stride size 0x40 | range [0, 31]
1870 * PORT="tdm_pif_desc0_hd_o[12:0]"
1873 /* Register address for bitfield desc{D}_hd[C:0] */
1874 #define HW_ATL_TDM_DESC_DHD_ADR(descriptor) (0x00007C0C + (descriptor) * 0x40)
1875 /* Bitmask for bitfield desc{D}_hd[C:0] */
1876 #define HW_ATL_TDM_DESC_DHD_MSK 0x00001FFF
1877 /* Inverted bitmask for bitfield desc{D}_hd[C:0] */
1878 #define HW_ATL_TDM_DESC_DHD_MSKN 0xFFFFE000
1879 /* Lower bit position of bitfield desc{D}_hd[C:0] */
1880 #define HW_ATL_TDM_DESC_DHD_SHIFT 0
1881 /* Width of bitfield desc{D}_hd[C:0] */
1882 #define HW_ATL_TDM_DESC_DHD_WIDTH 13
1884 /* TX desc{D}_len[9:0] Bitfield Definitions
1885 * Preprocessor definitions for the bitfield "desc{D}_len[9:0]".
1886 * Parameter: descriptor {D} | stride size 0x40 | range [0, 31]
1887 * PORT="pif_tdm_desc0_len_i[9:0]"
1890 /* Register address for bitfield desc{D}_len[9:0] */
1891 #define HW_ATL_TDM_DESC_DLEN_ADR(descriptor) (0x00007C08 + (descriptor) * 0x40)
1892 /* Bitmask for bitfield desc{D}_len[9:0] */
1893 #define HW_ATL_TDM_DESC_DLEN_MSK 0x00001FF8
1894 /* Inverted bitmask for bitfield desc{D}_len[9:0] */
1895 #define HW_ATL_TDM_DESC_DLEN_MSKN 0xFFFFE007
1896 /* Lower bit position of bitfield desc{D}_len[9:0] */
1897 #define HW_ATL_TDM_DESC_DLEN_SHIFT 3
1898 /* Width of bitfield desc{D}_len[9:0] */
1899 #define HW_ATL_TDM_DESC_DLEN_WIDTH 10
1900 /* Default value of bitfield desc{D}_len[9:0] */
1901 #define HW_ATL_TDM_DESC_DLEN_DEFAULT 0x0
1903 /* TX desc{D}_wrb_thresh[6:0] Bitfield Definitions
1904 * Preprocessor definitions for the bitfield "desc{D}_wrb_thresh[6:0]".
1905 * Parameter: descriptor {D} | stride size 0x40 | range [0, 31]
1906 * PORT="pif_tdm_desc0_wrb_thresh_i[6:0]"
1909 /* Register address for bitfield desc{D}_wrb_thresh[6:0] */
1910 #define HW_ATL_TDM_DESC_DWRB_THRESH_ADR(descriptor) \
1911 (0x00007C18 + (descriptor) * 0x40)
1912 /* Bitmask for bitfield desc{D}_wrb_thresh[6:0] */
1913 #define HW_ATL_TDM_DESC_DWRB_THRESH_MSK 0x00007F00
1914 /* Inverted bitmask for bitfield desc{D}_wrb_thresh[6:0] */
1915 #define HW_ATL_TDM_DESC_DWRB_THRESH_MSKN 0xFFFF80FF
1916 /* Lower bit position of bitfield desc{D}_wrb_thresh[6:0] */
1917 #define HW_ATL_TDM_DESC_DWRB_THRESH_SHIFT 8
1918 /* Width of bitfield desc{D}_wrb_thresh[6:0] */
1919 #define HW_ATL_TDM_DESC_DWRB_THRESH_WIDTH 7
1920 /* Default value of bitfield desc{D}_wrb_thresh[6:0] */
1921 #define HW_ATL_TDM_DESC_DWRB_THRESH_DEFAULT 0x0
1923 /* TX tdm_int_mod_en Bitfield Definitions
1924 * Preprocessor definitions for the bitfield "tdm_int_mod_en".
1925 * PORT="pif_tdm_int_mod_en_i"
1928 /* Register address for bitfield tdm_int_mod_en */
1929 #define HW_ATL_TDM_INT_MOD_EN_ADR 0x00007B40
1930 /* Bitmask for bitfield tdm_int_mod_en */
1931 #define HW_ATL_TDM_INT_MOD_EN_MSK 0x00000010
1932 /* Inverted bitmask for bitfield tdm_int_mod_en */
1933 #define HW_ATL_TDM_INT_MOD_EN_MSKN 0xFFFFFFEF
1934 /* Lower bit position of bitfield tdm_int_mod_en */
1935 #define HW_ATL_TDM_INT_MOD_EN_SHIFT 4
1936 /* Width of bitfield tdm_int_mod_en */
1937 #define HW_ATL_TDM_INT_MOD_EN_WIDTH 1
1938 /* Default value of bitfield tdm_int_mod_en */
1939 #define HW_ATL_TDM_INT_MOD_EN_DEFAULT 0x0
1941 /* TX lso_tcp_flag_mid[B:0] Bitfield Definitions
1942 * Preprocessor definitions for the bitfield "lso_tcp_flag_mid[B:0]".
1943 * PORT="pif_thm_lso_tcp_flag_mid_i[11:0]"
1945 /* register address for bitfield lso_tcp_flag_mid[b:0] */
1946 #define HW_ATL_THM_LSO_TCP_FLAG_MID_ADR 0x00007820
1947 /* bitmask for bitfield lso_tcp_flag_mid[b:0] */
1948 #define HW_ATL_THM_LSO_TCP_FLAG_MID_MSK 0x0fff0000
1949 /* inverted bitmask for bitfield lso_tcp_flag_mid[b:0] */
1950 #define HW_ATL_THM_LSO_TCP_FLAG_MID_MSKN 0xf000ffff
1951 /* lower bit position of bitfield lso_tcp_flag_mid[b:0] */
1952 #define HW_ATL_THM_LSO_TCP_FLAG_MID_SHIFT 16
1953 /* width of bitfield lso_tcp_flag_mid[b:0] */
1954 #define HW_ATL_THM_LSO_TCP_FLAG_MID_WIDTH 12
1955 /* default value of bitfield lso_tcp_flag_mid[b:0] */
1956 #define HW_ATL_THM_LSO_TCP_FLAG_MID_DEFAULT 0x0
1958 /* tx tx_buf_en bitfield definitions
1959 * preprocessor definitions for the bitfield "tx_buf_en".
1960 * port="pif_tpb_tx_buf_en_i"
1963 /* register address for bitfield tx_buf_en */
1964 #define HW_ATL_TPB_TX_BUF_EN_ADR 0x00007900
1965 /* bitmask for bitfield tx_buf_en */
1966 #define HW_ATL_TPB_TX_BUF_EN_MSK 0x00000001
1967 /* inverted bitmask for bitfield tx_buf_en */
1968 #define HW_ATL_TPB_TX_BUF_EN_MSKN 0xfffffffe
1969 /* lower bit position of bitfield tx_buf_en */
1970 #define HW_ATL_TPB_TX_BUF_EN_SHIFT 0
1971 /* width of bitfield tx_buf_en */
1972 #define HW_ATL_TPB_TX_BUF_EN_WIDTH 1
1973 /* default value of bitfield tx_buf_en */
1974 #define HW_ATL_TPB_TX_BUF_EN_DEFAULT 0x0
1976 /* register address for bitfield tx_tc_mode */
1977 #define HW_ATL_TPB_TX_TC_MODE_ADDR 0x00007900
1978 /* bitmask for bitfield tx_tc_mode */
1979 #define HW_ATL_TPB_TX_TC_MODE_MSK 0x00000100
1980 /* inverted bitmask for bitfield tx_tc_mode */
1981 #define HW_ATL_TPB_TX_TC_MODE_MSKN 0xFFFFFEFF
1982 /* lower bit position of bitfield tx_tc_mode */
1983 #define HW_ATL_TPB_TX_TC_MODE_SHIFT 8
1984 /* width of bitfield tx_tc_mode */
1985 #define HW_ATL_TPB_TX_TC_MODE_WIDTH 1
1986 /* default value of bitfield tx_tc_mode */
1987 #define HW_ATL_TPB_TX_TC_MODE_DEFAULT 0x0
1989 /* tx tx{b}_hi_thresh[c:0] bitfield definitions
1990 * preprocessor definitions for the bitfield "tx{b}_hi_thresh[c:0]".
1991 * parameter: buffer {b} | stride size 0x10 | range [0, 7]
1992 * port="pif_tpb_tx0_hi_thresh_i[12:0]"
1995 /* register address for bitfield tx{b}_hi_thresh[c:0] */
1996 #define HW_ATL_TPB_TXBHI_THRESH_ADR(buffer) (0x00007914 + (buffer) * 0x10)
1997 /* bitmask for bitfield tx{b}_hi_thresh[c:0] */
1998 #define HW_ATL_TPB_TXBHI_THRESH_MSK 0x1fff0000
1999 /* inverted bitmask for bitfield tx{b}_hi_thresh[c:0] */
2000 #define HW_ATL_TPB_TXBHI_THRESH_MSKN 0xe000ffff
2001 /* lower bit position of bitfield tx{b}_hi_thresh[c:0] */
2002 #define HW_ATL_TPB_TXBHI_THRESH_SHIFT 16
2003 /* width of bitfield tx{b}_hi_thresh[c:0] */
2004 #define HW_ATL_TPB_TXBHI_THRESH_WIDTH 13
2005 /* default value of bitfield tx{b}_hi_thresh[c:0] */
2006 #define HW_ATL_TPB_TXBHI_THRESH_DEFAULT 0x0
2008 /* tx tx{b}_lo_thresh[c:0] bitfield definitions
2009 * preprocessor definitions for the bitfield "tx{b}_lo_thresh[c:0]".
2010 * parameter: buffer {b} | stride size 0x10 | range [0, 7]
2011 * port="pif_tpb_tx0_lo_thresh_i[12:0]"
2014 /* register address for bitfield tx{b}_lo_thresh[c:0] */
2015 #define HW_ATL_TPB_TXBLO_THRESH_ADR(buffer) (0x00007914 + (buffer) * 0x10)
2016 /* bitmask for bitfield tx{b}_lo_thresh[c:0] */
2017 #define HW_ATL_TPB_TXBLO_THRESH_MSK 0x00001fff
2018 /* inverted bitmask for bitfield tx{b}_lo_thresh[c:0] */
2019 #define HW_ATL_TPB_TXBLO_THRESH_MSKN 0xffffe000
2020 /* lower bit position of bitfield tx{b}_lo_thresh[c:0] */
2021 #define HW_ATL_TPB_TXBLO_THRESH_SHIFT 0
2022 /* width of bitfield tx{b}_lo_thresh[c:0] */
2023 #define HW_ATL_TPB_TXBLO_THRESH_WIDTH 13
2024 /* default value of bitfield tx{b}_lo_thresh[c:0] */
2025 #define HW_ATL_TPB_TXBLO_THRESH_DEFAULT 0x0
2027 /* tx dma_sys_loopback bitfield definitions
2028 * preprocessor definitions for the bitfield "dma_sys_loopback".
2029 * port="pif_tpb_dma_sys_lbk_i"
2032 /* register address for bitfield dma_sys_loopback */
2033 #define HW_ATL_TPB_DMA_SYS_LBK_ADR 0x00007000
2034 /* bitmask for bitfield dma_sys_loopback */
2035 #define HW_ATL_TPB_DMA_SYS_LBK_MSK 0x00000040
2036 /* inverted bitmask for bitfield dma_sys_loopback */
2037 #define HW_ATL_TPB_DMA_SYS_LBK_MSKN 0xffffffbf
2038 /* lower bit position of bitfield dma_sys_loopback */
2039 #define HW_ATL_TPB_DMA_SYS_LBK_SHIFT 6
2040 /* width of bitfield dma_sys_loopback */
2041 #define HW_ATL_TPB_DMA_SYS_LBK_WIDTH 1
2042 /* default value of bitfield dma_sys_loopback */
2043 #define HW_ATL_TPB_DMA_SYS_LBK_DEFAULT 0x0
2045 /* tx tx{b}_buf_size[7:0] bitfield definitions
2046 * preprocessor definitions for the bitfield "tx{b}_buf_size[7:0]".
2047 * parameter: buffer {b} | stride size 0x10 | range [0, 7]
2048 * port="pif_tpb_tx0_buf_size_i[7:0]"
2051 /* register address for bitfield tx{b}_buf_size[7:0] */
2052 #define HW_ATL_TPB_TXBBUF_SIZE_ADR(buffer) (0x00007910 + (buffer) * 0x10)
2053 /* bitmask for bitfield tx{b}_buf_size[7:0] */
2054 #define HW_ATL_TPB_TXBBUF_SIZE_MSK 0x000000ff
2055 /* inverted bitmask for bitfield tx{b}_buf_size[7:0] */
2056 #define HW_ATL_TPB_TXBBUF_SIZE_MSKN 0xffffff00
2057 /* lower bit position of bitfield tx{b}_buf_size[7:0] */
2058 #define HW_ATL_TPB_TXBBUF_SIZE_SHIFT 0
2059 /* width of bitfield tx{b}_buf_size[7:0] */
2060 #define HW_ATL_TPB_TXBBUF_SIZE_WIDTH 8
2061 /* default value of bitfield tx{b}_buf_size[7:0] */
2062 #define HW_ATL_TPB_TXBBUF_SIZE_DEFAULT 0x0
2064 /* tx tx_scp_ins_en bitfield definitions
2065 * preprocessor definitions for the bitfield "tx_scp_ins_en".
2066 * port="pif_tpb_scp_ins_en_i"
2069 /* register address for bitfield tx_scp_ins_en */
2070 #define HW_ATL_TPB_TX_SCP_INS_EN_ADR 0x00007900
2071 /* bitmask for bitfield tx_scp_ins_en */
2072 #define HW_ATL_TPB_TX_SCP_INS_EN_MSK 0x00000004
2073 /* inverted bitmask for bitfield tx_scp_ins_en */
2074 #define HW_ATL_TPB_TX_SCP_INS_EN_MSKN 0xfffffffb
2075 /* lower bit position of bitfield tx_scp_ins_en */
2076 #define HW_ATL_TPB_TX_SCP_INS_EN_SHIFT 2
2077 /* width of bitfield tx_scp_ins_en */
2078 #define HW_ATL_TPB_TX_SCP_INS_EN_WIDTH 1
2079 /* default value of bitfield tx_scp_ins_en */
2080 #define HW_ATL_TPB_TX_SCP_INS_EN_DEFAULT 0x0
2082 /* tx ipv4_chk_en bitfield definitions
2083 * preprocessor definitions for the bitfield "ipv4_chk_en".
2084 * port="pif_tpo_ipv4_chk_en_i"
2087 /* register address for bitfield ipv4_chk_en */
2088 #define HW_ATL_TPO_IPV4CHK_EN_ADR 0x00007800
2089 /* bitmask for bitfield ipv4_chk_en */
2090 #define HW_ATL_TPO_IPV4CHK_EN_MSK 0x00000002
2091 /* inverted bitmask for bitfield ipv4_chk_en */
2092 #define HW_ATL_TPO_IPV4CHK_EN_MSKN 0xfffffffd
2093 /* lower bit position of bitfield ipv4_chk_en */
2094 #define HW_ATL_TPO_IPV4CHK_EN_SHIFT 1
2095 /* width of bitfield ipv4_chk_en */
2096 #define HW_ATL_TPO_IPV4CHK_EN_WIDTH 1
2097 /* default value of bitfield ipv4_chk_en */
2098 #define HW_ATL_TPO_IPV4CHK_EN_DEFAULT 0x0
2100 /* tx l4_chk_en bitfield definitions
2101 * preprocessor definitions for the bitfield "l4_chk_en".
2102 * port="pif_tpo_l4_chk_en_i"
2105 /* register address for bitfield l4_chk_en */
2106 #define HW_ATL_TPOL4CHK_EN_ADR 0x00007800
2107 /* bitmask for bitfield l4_chk_en */
2108 #define HW_ATL_TPOL4CHK_EN_MSK 0x00000001
2109 /* inverted bitmask for bitfield l4_chk_en */
2110 #define HW_ATL_TPOL4CHK_EN_MSKN 0xfffffffe
2111 /* lower bit position of bitfield l4_chk_en */
2112 #define HW_ATL_TPOL4CHK_EN_SHIFT 0
2113 /* width of bitfield l4_chk_en */
2114 #define HW_ATL_TPOL4CHK_EN_WIDTH 1
2115 /* default value of bitfield l4_chk_en */
2116 #define HW_ATL_TPOL4CHK_EN_DEFAULT 0x0
2118 /* tx pkt_sys_loopback bitfield definitions
2119 * preprocessor definitions for the bitfield "pkt_sys_loopback".
2120 * port="pif_tpo_pkt_sys_lbk_i"
2123 /* register address for bitfield pkt_sys_loopback */
2124 #define HW_ATL_TPO_PKT_SYS_LBK_ADR 0x00007000
2125 /* bitmask for bitfield pkt_sys_loopback */
2126 #define HW_ATL_TPO_PKT_SYS_LBK_MSK 0x00000080
2127 /* inverted bitmask for bitfield pkt_sys_loopback */
2128 #define HW_ATL_TPO_PKT_SYS_LBK_MSKN 0xffffff7f
2129 /* lower bit position of bitfield pkt_sys_loopback */
2130 #define HW_ATL_TPO_PKT_SYS_LBK_SHIFT 7
2131 /* width of bitfield pkt_sys_loopback */
2132 #define HW_ATL_TPO_PKT_SYS_LBK_WIDTH 1
2133 /* default value of bitfield pkt_sys_loopback */
2134 #define HW_ATL_TPO_PKT_SYS_LBK_DEFAULT 0x0
2136 /* tx data_tc_arb_mode bitfield definitions
2137 * preprocessor definitions for the bitfield "data_tc_arb_mode".
2138 * port="pif_tps_data_tc_arb_mode_i"
2141 /* register address for bitfield data_tc_arb_mode */
2142 #define HW_ATL_TPS_DATA_TC_ARB_MODE_ADR 0x00007100
2143 /* bitmask for bitfield data_tc_arb_mode */
2144 #define HW_ATL_TPS_DATA_TC_ARB_MODE_MSK 0x00000001
2145 /* inverted bitmask for bitfield data_tc_arb_mode */
2146 #define HW_ATL_TPS_DATA_TC_ARB_MODE_MSKN 0xfffffffe
2147 /* lower bit position of bitfield data_tc_arb_mode */
2148 #define HW_ATL_TPS_DATA_TC_ARB_MODE_SHIFT 0
2149 /* width of bitfield data_tc_arb_mode */
2150 #define HW_ATL_TPS_DATA_TC_ARB_MODE_WIDTH 1
2151 /* default value of bitfield data_tc_arb_mode */
2152 #define HW_ATL_TPS_DATA_TC_ARB_MODE_DEFAULT 0x0
2154 /* tx desc_rate_ta_rst bitfield definitions
2155 * preprocessor definitions for the bitfield "desc_rate_ta_rst".
2156 * port="pif_tps_desc_rate_ta_rst_i"
2159 /* register address for bitfield desc_rate_ta_rst */
2160 #define HW_ATL_TPS_DESC_RATE_TA_RST_ADR 0x00007310
2161 /* bitmask for bitfield desc_rate_ta_rst */
2162 #define HW_ATL_TPS_DESC_RATE_TA_RST_MSK 0x80000000
2163 /* inverted bitmask for bitfield desc_rate_ta_rst */
2164 #define HW_ATL_TPS_DESC_RATE_TA_RST_MSKN 0x7fffffff
2165 /* lower bit position of bitfield desc_rate_ta_rst */
2166 #define HW_ATL_TPS_DESC_RATE_TA_RST_SHIFT 31
2167 /* width of bitfield desc_rate_ta_rst */
2168 #define HW_ATL_TPS_DESC_RATE_TA_RST_WIDTH 1
2169 /* default value of bitfield desc_rate_ta_rst */
2170 #define HW_ATL_TPS_DESC_RATE_TA_RST_DEFAULT 0x0
2172 /* tx desc_rate_limit[a:0] bitfield definitions
2173 * preprocessor definitions for the bitfield "desc_rate_limit[a:0]".
2174 * port="pif_tps_desc_rate_lim_i[10:0]"
2177 /* register address for bitfield desc_rate_limit[a:0] */
2178 #define HW_ATL_TPS_DESC_RATE_LIM_ADR 0x00007310
2179 /* bitmask for bitfield desc_rate_limit[a:0] */
2180 #define HW_ATL_TPS_DESC_RATE_LIM_MSK 0x000007ff
2181 /* inverted bitmask for bitfield desc_rate_limit[a:0] */
2182 #define HW_ATL_TPS_DESC_RATE_LIM_MSKN 0xfffff800
2183 /* lower bit position of bitfield desc_rate_limit[a:0] */
2184 #define HW_ATL_TPS_DESC_RATE_LIM_SHIFT 0
2185 /* width of bitfield desc_rate_limit[a:0] */
2186 #define HW_ATL_TPS_DESC_RATE_LIM_WIDTH 11
2187 /* default value of bitfield desc_rate_limit[a:0] */
2188 #define HW_ATL_TPS_DESC_RATE_LIM_DEFAULT 0x0
2190 /* tx desc_tc_arb_mode[1:0] bitfield definitions
2191 * preprocessor definitions for the bitfield "desc_tc_arb_mode[1:0]".
2192 * port="pif_tps_desc_tc_arb_mode_i[1:0]"
2195 /* register address for bitfield desc_tc_arb_mode[1:0] */
2196 #define HW_ATL_TPS_DESC_TC_ARB_MODE_ADR 0x00007200
2197 /* bitmask for bitfield desc_tc_arb_mode[1:0] */
2198 #define HW_ATL_TPS_DESC_TC_ARB_MODE_MSK 0x00000003
2199 /* inverted bitmask for bitfield desc_tc_arb_mode[1:0] */
2200 #define HW_ATL_TPS_DESC_TC_ARB_MODE_MSKN 0xfffffffc
2201 /* lower bit position of bitfield desc_tc_arb_mode[1:0] */
2202 #define HW_ATL_TPS_DESC_TC_ARB_MODE_SHIFT 0
2203 /* width of bitfield desc_tc_arb_mode[1:0] */
2204 #define HW_ATL_TPS_DESC_TC_ARB_MODE_WIDTH 2
2205 /* default value of bitfield desc_tc_arb_mode[1:0] */
2206 #define HW_ATL_TPS_DESC_TC_ARB_MODE_DEFAULT 0x0
2208 /* tx desc_tc{t}_credit_max[b:0] bitfield definitions
2209 * preprocessor definitions for the bitfield "desc_tc{t}_credit_max[b:0]".
2210 * parameter: tc {t} | stride size 0x4 | range [0, 7]
2211 * port="pif_tps_desc_tc0_credit_max_i[11:0]"
2214 /* register address for bitfield desc_tc{t}_credit_max[b:0] */
2215 #define HW_ATL_TPS_DESC_TCTCREDIT_MAX_ADR(tc) (0x00007210 + (tc) * 0x4)
2216 /* bitmask for bitfield desc_tc{t}_credit_max[b:0] */
2217 #define HW_ATL_TPS_DESC_TCTCREDIT_MAX_MSK 0x0fff0000
2218 /* inverted bitmask for bitfield desc_tc{t}_credit_max[b:0] */
2219 #define HW_ATL_TPS_DESC_TCTCREDIT_MAX_MSKN 0xf000ffff
2220 /* lower bit position of bitfield desc_tc{t}_credit_max[b:0] */
2221 #define HW_ATL_TPS_DESC_TCTCREDIT_MAX_SHIFT 16
2222 /* width of bitfield desc_tc{t}_credit_max[b:0] */
2223 #define HW_ATL_TPS_DESC_TCTCREDIT_MAX_WIDTH 12
2224 /* default value of bitfield desc_tc{t}_credit_max[b:0] */
2225 #define HW_ATL_TPS_DESC_TCTCREDIT_MAX_DEFAULT 0x0
2227 /* tx desc_tc{t}_weight[8:0] bitfield definitions
2228 * preprocessor definitions for the bitfield "desc_tc{t}_weight[8:0]".
2229 * parameter: tc {t} | stride size 0x4 | range [0, 7]
2230 * port="pif_tps_desc_tc0_weight_i[8:0]"
2233 /* register address for bitfield desc_tc{t}_weight[8:0] */
2234 #define HW_ATL_TPS_DESC_TCTWEIGHT_ADR(tc) (0x00007210 + (tc) * 0x4)
2235 /* bitmask for bitfield desc_tc{t}_weight[8:0] */
2236 #define HW_ATL_TPS_DESC_TCTWEIGHT_MSK 0x000001ff
2237 /* inverted bitmask for bitfield desc_tc{t}_weight[8:0] */
2238 #define HW_ATL_TPS_DESC_TCTWEIGHT_MSKN 0xfffffe00
2239 /* lower bit position of bitfield desc_tc{t}_weight[8:0] */
2240 #define HW_ATL_TPS_DESC_TCTWEIGHT_SHIFT 0
2241 /* width of bitfield desc_tc{t}_weight[8:0] */
2242 #define HW_ATL_TPS_DESC_TCTWEIGHT_WIDTH 9
2243 /* default value of bitfield desc_tc{t}_weight[8:0] */
2244 #define HW_ATL_TPS_DESC_TCTWEIGHT_DEFAULT 0x0
2246 /* tx desc_vm_arb_mode bitfield definitions
2247 * preprocessor definitions for the bitfield "desc_vm_arb_mode".
2248 * port="pif_tps_desc_vm_arb_mode_i"
2251 /* register address for bitfield desc_vm_arb_mode */
2252 #define HW_ATL_TPS_DESC_VM_ARB_MODE_ADR 0x00007300
2253 /* bitmask for bitfield desc_vm_arb_mode */
2254 #define HW_ATL_TPS_DESC_VM_ARB_MODE_MSK 0x00000001
2255 /* inverted bitmask for bitfield desc_vm_arb_mode */
2256 #define HW_ATL_TPS_DESC_VM_ARB_MODE_MSKN 0xfffffffe
2257 /* lower bit position of bitfield desc_vm_arb_mode */
2258 #define HW_ATL_TPS_DESC_VM_ARB_MODE_SHIFT 0
2259 /* width of bitfield desc_vm_arb_mode */
2260 #define HW_ATL_TPS_DESC_VM_ARB_MODE_WIDTH 1
2261 /* default value of bitfield desc_vm_arb_mode */
2262 #define HW_ATL_TPS_DESC_VM_ARB_MODE_DEFAULT 0x0
2264 /* tx data_tc{t}_credit_max[b:0] bitfield definitions
2265 * preprocessor definitions for the bitfield "data_tc{t}_credit_max[b:0]".
2266 * parameter: tc {t} | stride size 0x4 | range [0, 7]
2267 * port="pif_tps_data_tc0_credit_max_i[11:0]"
2270 /* register address for bitfield data_tc{t}_credit_max[b:0] */
2271 #define HW_ATL_TPS_DATA_TCTCREDIT_MAX_ADR(tc) (0x00007110 + (tc) * 0x4)
2272 /* bitmask for bitfield data_tc{t}_credit_max[b:0] */
2273 #define HW_ATL_TPS_DATA_TCTCREDIT_MAX_MSK 0x0fff0000
2274 /* inverted bitmask for bitfield data_tc{t}_credit_max[b:0] */
2275 #define HW_ATL_TPS_DATA_TCTCREDIT_MAX_MSKN 0xf000ffff
2276 /* lower bit position of bitfield data_tc{t}_credit_max[b:0] */
2277 #define HW_ATL_TPS_DATA_TCTCREDIT_MAX_SHIFT 16
2278 /* width of bitfield data_tc{t}_credit_max[b:0] */
2279 #define HW_ATL_TPS_DATA_TCTCREDIT_MAX_WIDTH 12
2280 /* default value of bitfield data_tc{t}_credit_max[b:0] */
2281 #define HW_ATL_TPS_DATA_TCTCREDIT_MAX_DEFAULT 0x0
2283 /* tx data_tc{t}_weight[8:0] bitfield definitions
2284 * preprocessor definitions for the bitfield "data_tc{t}_weight[8:0]".
2285 * parameter: tc {t} | stride size 0x4 | range [0, 7]
2286 * port="pif_tps_data_tc0_weight_i[8:0]"
2289 /* register address for bitfield data_tc{t}_weight[8:0] */
2290 #define HW_ATL_TPS_DATA_TCTWEIGHT_ADR(tc) (0x00007110 + (tc) * 0x4)
2291 /* bitmask for bitfield data_tc{t}_weight[8:0] */
2292 #define HW_ATL_TPS_DATA_TCTWEIGHT_MSK 0x000001ff
2293 /* inverted bitmask for bitfield data_tc{t}_weight[8:0] */
2294 #define HW_ATL_TPS_DATA_TCTWEIGHT_MSKN 0xfffffe00
2295 /* lower bit position of bitfield data_tc{t}_weight[8:0] */
2296 #define HW_ATL_TPS_DATA_TCTWEIGHT_SHIFT 0
2297 /* width of bitfield data_tc{t}_weight[8:0] */
2298 #define HW_ATL_TPS_DATA_TCTWEIGHT_WIDTH 9
2299 /* default value of bitfield data_tc{t}_weight[8:0] */
2300 #define HW_ATL_TPS_DATA_TCTWEIGHT_DEFAULT 0x0
2302 /* tx reg_res_dsbl bitfield definitions
2303 * preprocessor definitions for the bitfield "reg_res_dsbl".
2304 * port="pif_tx_reg_res_dsbl_i"
2307 /* register address for bitfield reg_res_dsbl */
2308 #define HW_ATL_TX_REG_RES_DSBL_ADR 0x00007000
2309 /* bitmask for bitfield reg_res_dsbl */
2310 #define HW_ATL_TX_REG_RES_DSBL_MSK 0x20000000
2311 /* inverted bitmask for bitfield reg_res_dsbl */
2312 #define HW_ATL_TX_REG_RES_DSBL_MSKN 0xdfffffff
2313 /* lower bit position of bitfield reg_res_dsbl */
2314 #define HW_ATL_TX_REG_RES_DSBL_SHIFT 29
2315 /* width of bitfield reg_res_dsbl */
2316 #define HW_ATL_TX_REG_RES_DSBL_WIDTH 1
2317 /* default value of bitfield reg_res_dsbl */
2318 #define HW_ATL_TX_REG_RES_DSBL_DEFAULT 0x1
2320 /* mac_phy register access busy bitfield definitions
2321 * preprocessor definitions for the bitfield "register access busy".
2322 * port="msm_pif_reg_busy_o"
2325 /* register address for bitfield register access busy */
2326 #define HW_ATL_MSM_REG_ACCESS_BUSY_ADR 0x00004400
2327 /* bitmask for bitfield register access busy */
2328 #define HW_ATL_MSM_REG_ACCESS_BUSY_MSK 0x00001000
2329 /* inverted bitmask for bitfield register access busy */
2330 #define HW_ATL_MSM_REG_ACCESS_BUSY_MSKN 0xffffefff
2331 /* lower bit position of bitfield register access busy */
2332 #define HW_ATL_MSM_REG_ACCESS_BUSY_SHIFT 12
2333 /* width of bitfield register access busy */
2334 #define HW_ATL_MSM_REG_ACCESS_BUSY_WIDTH 1
2336 /* mac_phy msm register address[7:0] bitfield definitions
2337 * preprocessor definitions for the bitfield "msm register address[7:0]".
2338 * port="pif_msm_reg_addr_i[7:0]"
2341 /* register address for bitfield msm register address[7:0] */
2342 #define HW_ATL_MSM_REG_ADDR_ADR 0x00004400
2343 /* bitmask for bitfield msm register address[7:0] */
2344 #define HW_ATL_MSM_REG_ADDR_MSK 0x000000ff
2345 /* inverted bitmask for bitfield msm register address[7:0] */
2346 #define HW_ATL_MSM_REG_ADDR_MSKN 0xffffff00
2347 /* lower bit position of bitfield msm register address[7:0] */
2348 #define HW_ATL_MSM_REG_ADDR_SHIFT 0
2349 /* width of bitfield msm register address[7:0] */
2350 #define HW_ATL_MSM_REG_ADDR_WIDTH 8
2351 /* default value of bitfield msm register address[7:0] */
2352 #define HW_ATL_MSM_REG_ADDR_DEFAULT 0x0
2354 /* mac_phy register read strobe bitfield definitions
2355 * preprocessor definitions for the bitfield "register read strobe".
2356 * port="pif_msm_reg_rden_i"
2359 /* register address for bitfield register read strobe */
2360 #define HW_ATL_MSM_REG_RD_STROBE_ADR 0x00004400
2361 /* bitmask for bitfield register read strobe */
2362 #define HW_ATL_MSM_REG_RD_STROBE_MSK 0x00000200
2363 /* inverted bitmask for bitfield register read strobe */
2364 #define HW_ATL_MSM_REG_RD_STROBE_MSKN 0xfffffdff
2365 /* lower bit position of bitfield register read strobe */
2366 #define HW_ATL_MSM_REG_RD_STROBE_SHIFT 9
2367 /* width of bitfield register read strobe */
2368 #define HW_ATL_MSM_REG_RD_STROBE_WIDTH 1
2369 /* default value of bitfield register read strobe */
2370 #define HW_ATL_MSM_REG_RD_STROBE_DEFAULT 0x0
2372 /* mac_phy msm register read data[31:0] bitfield definitions
2373 * preprocessor definitions for the bitfield "msm register read data[31:0]".
2374 * port="msm_pif_reg_rd_data_o[31:0]"
2377 /* register address for bitfield msm register read data[31:0] */
2378 #define HW_ATL_MSM_REG_RD_DATA_ADR 0x00004408
2379 /* bitmask for bitfield msm register read data[31:0] */
2380 #define HW_ATL_MSM_REG_RD_DATA_MSK 0xffffffff
2381 /* inverted bitmask for bitfield msm register read data[31:0] */
2382 #define HW_ATL_MSM_REG_RD_DATA_MSKN 0x00000000
2383 /* lower bit position of bitfield msm register read data[31:0] */
2384 #define HW_ATL_MSM_REG_RD_DATA_SHIFT 0
2385 /* width of bitfield msm register read data[31:0] */
2386 #define HW_ATL_MSM_REG_RD_DATA_WIDTH 32
2388 /* mac_phy msm register write data[31:0] bitfield definitions
2389 * preprocessor definitions for the bitfield "msm register write data[31:0]".
2390 * port="pif_msm_reg_wr_data_i[31:0]"
2393 /* register address for bitfield msm register write data[31:0] */
2394 #define HW_ATL_MSM_REG_WR_DATA_ADR 0x00004404
2395 /* bitmask for bitfield msm register write data[31:0] */
2396 #define HW_ATL_MSM_REG_WR_DATA_MSK 0xffffffff
2397 /* inverted bitmask for bitfield msm register write data[31:0] */
2398 #define HW_ATL_MSM_REG_WR_DATA_MSKN 0x00000000
2399 /* lower bit position of bitfield msm register write data[31:0] */
2400 #define HW_ATL_MSM_REG_WR_DATA_SHIFT 0
2401 /* width of bitfield msm register write data[31:0] */
2402 #define HW_ATL_MSM_REG_WR_DATA_WIDTH 32
2403 /* default value of bitfield msm register write data[31:0] */
2404 #define HW_ATL_MSM_REG_WR_DATA_DEFAULT 0x0
2406 /* mac_phy register write strobe bitfield definitions
2407 * preprocessor definitions for the bitfield "register write strobe".
2408 * port="pif_msm_reg_wren_i"
2411 /* register address for bitfield register write strobe */
2412 #define HW_ATL_MSM_REG_WR_STROBE_ADR 0x00004400
2413 /* bitmask for bitfield register write strobe */
2414 #define HW_ATL_MSM_REG_WR_STROBE_MSK 0x00000100
2415 /* inverted bitmask for bitfield register write strobe */
2416 #define HW_ATL_MSM_REG_WR_STROBE_MSKN 0xfffffeff
2417 /* lower bit position of bitfield register write strobe */
2418 #define HW_ATL_MSM_REG_WR_STROBE_SHIFT 8
2419 /* width of bitfield register write strobe */
2420 #define HW_ATL_MSM_REG_WR_STROBE_WIDTH 1
2421 /* default value of bitfield register write strobe */
2422 #define HW_ATL_MSM_REG_WR_STROBE_DEFAULT 0x0
2424 /* mif soft reset bitfield definitions
2425 * preprocessor definitions for the bitfield "soft reset".
2426 * port="pif_glb_res_i"
2429 /* register address for bitfield soft reset */
2430 #define HW_ATL_GLB_SOFT_RES_ADR 0x00000000
2431 /* bitmask for bitfield soft reset */
2432 #define HW_ATL_GLB_SOFT_RES_MSK 0x00008000
2433 /* inverted bitmask for bitfield soft reset */
2434 #define HW_ATL_GLB_SOFT_RES_MSKN 0xffff7fff
2435 /* lower bit position of bitfield soft reset */
2436 #define HW_ATL_GLB_SOFT_RES_SHIFT 15
2437 /* width of bitfield soft reset */
2438 #define HW_ATL_GLB_SOFT_RES_WIDTH 1
2439 /* default value of bitfield soft reset */
2440 #define HW_ATL_GLB_SOFT_RES_DEFAULT 0x0
2442 /* mif register reset disable bitfield definitions
2443 * preprocessor definitions for the bitfield "register reset disable".
2444 * port="pif_glb_reg_res_dsbl_i"
2447 /* register address for bitfield register reset disable */
2448 #define HW_ATL_GLB_REG_RES_DIS_ADR 0x00000000
2449 /* bitmask for bitfield register reset disable */
2450 #define HW_ATL_GLB_REG_RES_DIS_MSK 0x00004000
2451 /* inverted bitmask for bitfield register reset disable */
2452 #define HW_ATL_GLB_REG_RES_DIS_MSKN 0xffffbfff
2453 /* lower bit position of bitfield register reset disable */
2454 #define HW_ATL_GLB_REG_RES_DIS_SHIFT 14
2455 /* width of bitfield register reset disable */
2456 #define HW_ATL_GLB_REG_RES_DIS_WIDTH 1
2457 /* default value of bitfield register reset disable */
2458 #define HW_ATL_GLB_REG_RES_DIS_DEFAULT 0x1
2460 /* tx dma debug control definitions */
2461 #define HW_ATL_TX_DMA_DEBUG_CTL_ADR 0x00008920u
2463 /* tx dma descriptor base address msw definitions */
2464 #define HW_ATL_TX_DMA_DESC_BASE_ADDRMSW_ADR(descriptor) \
2465 (0x00007c04u + (descriptor) * 0x40)
2467 /* tx dma total request limit */
2468 #define HW_ATL_TX_DMA_TOTAL_REQ_LIMIT_ADR 0x00007b20u
2470 /* tx interrupt moderation control register definitions
2471 * Preprocessor definitions for TX Interrupt Moderation Control Register
2472 * Base Address: 0x00008980
2473 * Parameter: queue {Q} | stride size 0x4 | range [0, 31]
2476 #define HW_ATL_TX_INTR_MODERATION_CTL_ADR(queue) (0x00008980u + (queue) * 0x4)
2478 /* pcie reg_res_dsbl bitfield definitions
2479 * preprocessor definitions for the bitfield "reg_res_dsbl".
2480 * port="pif_pci_reg_res_dsbl_i"
2483 /* register address for bitfield reg_res_dsbl */
2484 #define HW_ATL_PCI_REG_RES_DSBL_ADR 0x00001000
2485 /* bitmask for bitfield reg_res_dsbl */
2486 #define HW_ATL_PCI_REG_RES_DSBL_MSK 0x20000000
2487 /* inverted bitmask for bitfield reg_res_dsbl */
2488 #define HW_ATL_PCI_REG_RES_DSBL_MSKN 0xdfffffff
2489 /* lower bit position of bitfield reg_res_dsbl */
2490 #define HW_ATL_PCI_REG_RES_DSBL_SHIFT 29
2491 /* width of bitfield reg_res_dsbl */
2492 #define HW_ATL_PCI_REG_RES_DSBL_WIDTH 1
2493 /* default value of bitfield reg_res_dsbl */
2494 #define HW_ATL_PCI_REG_RES_DSBL_DEFAULT 0x1
2496 /* PCI core control register */
2497 #define HW_ATL_PCI_REG_CONTROL6_ADR 0x1014u
2499 /* global microprocessor scratch pad definitions */
2500 #define HW_ATL_GLB_CPU_SCRATCH_SCP_ADR(scratch_scp) \
2501 (0x00000300u + (scratch_scp) * 0x4)
2503 /* register address for bitfield uP Force Interrupt */
2504 #define HW_ATL_MCP_UP_FORCE_INTERRUPT_ADR 0x00000404
2505 /* bitmask for bitfield uP Force Interrupt */
2506 #define HW_ATL_MCP_UP_FORCE_INTERRUPT_MSK 0x00000002
2507 /* inverted bitmask for bitfield uP Force Interrupt */
2508 #define HW_ATL_MCP_UP_FORCE_INTERRUPT_MSKN 0xFFFFFFFD
2509 /* lower bit position of bitfield uP Force Interrupt */
2510 #define HW_ATL_MCP_UP_FORCE_INTERRUPT_SHIFT 1
2511 /* width of bitfield uP Force Interrupt */
2512 #define HW_ATL_MCP_UP_FORCE_INTERRUPT_WIDTH 1
2513 /* default value of bitfield uP Force Interrupt */
2514 #define HW_ATL_MCP_UP_FORCE_INTERRUPT_DEFAULT 0x0
2516 #define HW_ATL_RX_CTRL_ADDR_BEGIN_FL3L4 0x00005380
2517 #define HW_ATL_RX_SRCA_ADDR_BEGIN_FL3L4 0x000053B0
2518 #define HW_ATL_RX_DESTA_ADDR_BEGIN_FL3L4 0x000053D0
2520 #define HW_ATL_RPF_L3_REG_CTRL_ADR(location) (0x00005380 + (location) * 0x4)
2522 /* RX rpf_l3_sa{D}[1F:0] Bitfield Definitions
2523 * Preprocessor definitions for the bitfield "l3_sa{D}[1F:0]".
2524 * Parameter: location {D} | stride size 0x4 | range [0, 7]
2525 * PORT="pif_rpf_l3_sa0_i[31:0]"
2528 /* Register address for bitfield pif_rpf_l3_sa0_i[31:0] */
2529 #define HW_ATL_RPF_L3_SRCA_ADR(location) (0x000053B0 + (location) * 0x4)
2530 /* Bitmask for bitfield l3_sa0[1F:0] */
2531 #define HW_ATL_RPF_L3_SRCA_MSK 0xFFFFFFFFu
2532 /* Inverted bitmask for bitfield l3_sa0[1F:0] */
2533 #define HW_ATL_RPF_L3_SRCA_MSKN 0xFFFFFFFFu
2534 /* Lower bit position of bitfield l3_sa0[1F:0] */
2535 #define HW_ATL_RPF_L3_SRCA_SHIFT 0
2536 /* Width of bitfield l3_sa0[1F:0] */
2537 #define HW_ATL_RPF_L3_SRCA_WIDTH 32
2538 /* Default value of bitfield l3_sa0[1F:0] */
2539 #define HW_ATL_RPF_L3_SRCA_DEFAULT 0x0
2541 /* RX rpf_l3_da{D}[1F:0] Bitfield Definitions
2542 * Preprocessor definitions for the bitfield "l3_da{D}[1F:0]".
2543 * Parameter: location {D} | stride size 0x4 | range [0, 7]
2544 * PORT="pif_rpf_l3_da0_i[31:0]"
2547 /* Register address for bitfield pif_rpf_l3_da0_i[31:0] */
2548 #define HW_ATL_RPF_L3_DSTA_ADR(location) (0x000053B0 + (location) * 0x4)
2549 /* Bitmask for bitfield l3_da0[1F:0] */
2550 #define HW_ATL_RPF_L3_DSTA_MSK 0xFFFFFFFFu
2551 /* Inverted bitmask for bitfield l3_da0[1F:0] */
2552 #define HW_ATL_RPF_L3_DSTA_MSKN 0xFFFFFFFFu
2553 /* Lower bit position of bitfield l3_da0[1F:0] */
2554 #define HW_ATL_RPF_L3_DSTA_SHIFT 0
2555 /* Width of bitfield l3_da0[1F:0] */
2556 #define HW_ATL_RPF_L3_DSTA_WIDTH 32
2557 /* Default value of bitfield l3_da0[1F:0] */
2558 #define HW_ATL_RPF_L3_DSTA_DEFAULT 0x0
2560 #define HW_ATL_FW_SM_RAM 0x2U
2562 #endif /* HW_ATL_LLH_INTERNAL_H */