2 * aQuantia Corporation Network Driver
3 * Copyright (C) 2014-2017 aQuantia Corporation. All rights reserved
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms and conditions of the GNU General Public License,
7 * version 2, as published by the Free Software Foundation.
10 /* File hw_atl_llh.c: Definitions of bitfield and register access functions for
14 #include "hw_atl_llh.h"
15 #include "hw_atl_llh_internal.h"
16 #include "../aq_hw_utils.h"
19 void hw_atl_reg_glb_cpu_sem_set(struct aq_hw_s *aq_hw, u32 glb_cpu_sem,
22 aq_hw_write_reg(aq_hw, HW_ATL_GLB_CPU_SEM_ADR(semaphore), glb_cpu_sem);
25 u32 hw_atl_reg_glb_cpu_sem_get(struct aq_hw_s *aq_hw, u32 semaphore)
27 return aq_hw_read_reg(aq_hw, HW_ATL_GLB_CPU_SEM_ADR(semaphore));
30 void hw_atl_glb_glb_reg_res_dis_set(struct aq_hw_s *aq_hw, u32 glb_reg_res_dis)
32 aq_hw_write_reg_bit(aq_hw, HW_ATL_GLB_REG_RES_DIS_ADR,
33 HW_ATL_GLB_REG_RES_DIS_MSK,
34 HW_ATL_GLB_REG_RES_DIS_SHIFT,
38 void hw_atl_glb_soft_res_set(struct aq_hw_s *aq_hw, u32 soft_res)
40 aq_hw_write_reg_bit(aq_hw, HW_ATL_GLB_SOFT_RES_ADR,
41 HW_ATL_GLB_SOFT_RES_MSK,
42 HW_ATL_GLB_SOFT_RES_SHIFT, soft_res);
45 u32 hw_atl_glb_soft_res_get(struct aq_hw_s *aq_hw)
47 return aq_hw_read_reg_bit(aq_hw, HW_ATL_GLB_SOFT_RES_ADR,
48 HW_ATL_GLB_SOFT_RES_MSK,
49 HW_ATL_GLB_SOFT_RES_SHIFT);
52 u32 hw_atl_reg_rx_dma_stat_counter7get(struct aq_hw_s *aq_hw)
54 return aq_hw_read_reg(aq_hw, HW_ATL_RX_DMA_STAT_COUNTER7_ADR);
57 u32 hw_atl_reg_glb_mif_id_get(struct aq_hw_s *aq_hw)
59 return aq_hw_read_reg(aq_hw, HW_ATL_GLB_MIF_ID_ADR);
63 u32 hw_atl_rpb_rx_dma_drop_pkt_cnt_get(struct aq_hw_s *aq_hw)
65 return aq_hw_read_reg(aq_hw, HW_ATL_RPB_RX_DMA_DROP_PKT_CNT_ADR);
68 u32 hw_atl_stats_rx_dma_good_octet_counterlsw_get(struct aq_hw_s *aq_hw)
70 return aq_hw_read_reg(aq_hw, HW_ATL_STATS_RX_DMA_GOOD_OCTET_COUNTERLSW);
73 u32 hw_atl_stats_rx_dma_good_pkt_counterlsw_get(struct aq_hw_s *aq_hw)
75 return aq_hw_read_reg(aq_hw, HW_ATL_STATS_RX_DMA_GOOD_PKT_COUNTERLSW);
78 u32 hw_atl_stats_tx_dma_good_octet_counterlsw_get(struct aq_hw_s *aq_hw)
80 return aq_hw_read_reg(aq_hw, HW_ATL_STATS_TX_DMA_GOOD_OCTET_COUNTERLSW);
83 u32 hw_atl_stats_tx_dma_good_pkt_counterlsw_get(struct aq_hw_s *aq_hw)
85 return aq_hw_read_reg(aq_hw, HW_ATL_STATS_TX_DMA_GOOD_PKT_COUNTERLSW);
88 u32 hw_atl_stats_rx_dma_good_octet_countermsw_get(struct aq_hw_s *aq_hw)
90 return aq_hw_read_reg(aq_hw, HW_ATL_STATS_RX_DMA_GOOD_OCTET_COUNTERMSW);
93 u32 hw_atl_stats_rx_dma_good_pkt_countermsw_get(struct aq_hw_s *aq_hw)
95 return aq_hw_read_reg(aq_hw, HW_ATL_STATS_RX_DMA_GOOD_PKT_COUNTERMSW);
98 u32 hw_atl_stats_tx_dma_good_octet_countermsw_get(struct aq_hw_s *aq_hw)
100 return aq_hw_read_reg(aq_hw, HW_ATL_STATS_TX_DMA_GOOD_OCTET_COUNTERMSW);
103 u32 hw_atl_stats_tx_dma_good_pkt_countermsw_get(struct aq_hw_s *aq_hw)
105 return aq_hw_read_reg(aq_hw, HW_ATL_STATS_TX_DMA_GOOD_PKT_COUNTERMSW);
109 void hw_atl_itr_irq_auto_masklsw_set(struct aq_hw_s *aq_hw,
110 u32 irq_auto_masklsw)
112 aq_hw_write_reg(aq_hw, HW_ATL_ITR_IAMRLSW_ADR, irq_auto_masklsw);
115 void hw_atl_itr_irq_map_en_rx_set(struct aq_hw_s *aq_hw, u32 irq_map_en_rx,
118 /* register address for bitfield imr_rx{r}_en */
119 static u32 itr_imr_rxren_adr[32] = {
120 0x00002100U, 0x00002100U, 0x00002104U, 0x00002104U,
121 0x00002108U, 0x00002108U, 0x0000210CU, 0x0000210CU,
122 0x00002110U, 0x00002110U, 0x00002114U, 0x00002114U,
123 0x00002118U, 0x00002118U, 0x0000211CU, 0x0000211CU,
124 0x00002120U, 0x00002120U, 0x00002124U, 0x00002124U,
125 0x00002128U, 0x00002128U, 0x0000212CU, 0x0000212CU,
126 0x00002130U, 0x00002130U, 0x00002134U, 0x00002134U,
127 0x00002138U, 0x00002138U, 0x0000213CU, 0x0000213CU
130 /* bitmask for bitfield imr_rx{r}_en */
131 static u32 itr_imr_rxren_msk[32] = {
132 0x00008000U, 0x00000080U, 0x00008000U, 0x00000080U,
133 0x00008000U, 0x00000080U, 0x00008000U, 0x00000080U,
134 0x00008000U, 0x00000080U, 0x00008000U, 0x00000080U,
135 0x00008000U, 0x00000080U, 0x00008000U, 0x00000080U,
136 0x00008000U, 0x00000080U, 0x00008000U, 0x00000080U,
137 0x00008000U, 0x00000080U, 0x00008000U, 0x00000080U,
138 0x00008000U, 0x00000080U, 0x00008000U, 0x00000080U,
139 0x00008000U, 0x00000080U, 0x00008000U, 0x00000080U
142 /* lower bit position of bitfield imr_rx{r}_en */
143 static u32 itr_imr_rxren_shift[32] = {
144 15U, 7U, 15U, 7U, 15U, 7U, 15U, 7U,
145 15U, 7U, 15U, 7U, 15U, 7U, 15U, 7U,
146 15U, 7U, 15U, 7U, 15U, 7U, 15U, 7U,
147 15U, 7U, 15U, 7U, 15U, 7U, 15U, 7U
150 aq_hw_write_reg_bit(aq_hw, itr_imr_rxren_adr[rx],
151 itr_imr_rxren_msk[rx],
152 itr_imr_rxren_shift[rx],
156 void hw_atl_itr_irq_map_en_tx_set(struct aq_hw_s *aq_hw, u32 irq_map_en_tx,
159 /* register address for bitfield imr_tx{t}_en */
160 static u32 itr_imr_txten_adr[32] = {
161 0x00002100U, 0x00002100U, 0x00002104U, 0x00002104U,
162 0x00002108U, 0x00002108U, 0x0000210CU, 0x0000210CU,
163 0x00002110U, 0x00002110U, 0x00002114U, 0x00002114U,
164 0x00002118U, 0x00002118U, 0x0000211CU, 0x0000211CU,
165 0x00002120U, 0x00002120U, 0x00002124U, 0x00002124U,
166 0x00002128U, 0x00002128U, 0x0000212CU, 0x0000212CU,
167 0x00002130U, 0x00002130U, 0x00002134U, 0x00002134U,
168 0x00002138U, 0x00002138U, 0x0000213CU, 0x0000213CU
171 /* bitmask for bitfield imr_tx{t}_en */
172 static u32 itr_imr_txten_msk[32] = {
173 0x80000000U, 0x00800000U, 0x80000000U, 0x00800000U,
174 0x80000000U, 0x00800000U, 0x80000000U, 0x00800000U,
175 0x80000000U, 0x00800000U, 0x80000000U, 0x00800000U,
176 0x80000000U, 0x00800000U, 0x80000000U, 0x00800000U,
177 0x80000000U, 0x00800000U, 0x80000000U, 0x00800000U,
178 0x80000000U, 0x00800000U, 0x80000000U, 0x00800000U,
179 0x80000000U, 0x00800000U, 0x80000000U, 0x00800000U,
180 0x80000000U, 0x00800000U, 0x80000000U, 0x00800000U
183 /* lower bit position of bitfield imr_tx{t}_en */
184 static u32 itr_imr_txten_shift[32] = {
185 31U, 23U, 31U, 23U, 31U, 23U, 31U, 23U,
186 31U, 23U, 31U, 23U, 31U, 23U, 31U, 23U,
187 31U, 23U, 31U, 23U, 31U, 23U, 31U, 23U,
188 31U, 23U, 31U, 23U, 31U, 23U, 31U, 23U
191 aq_hw_write_reg_bit(aq_hw, itr_imr_txten_adr[tx],
192 itr_imr_txten_msk[tx],
193 itr_imr_txten_shift[tx],
197 void hw_atl_itr_irq_map_rx_set(struct aq_hw_s *aq_hw, u32 irq_map_rx, u32 rx)
199 /* register address for bitfield imr_rx{r}[4:0] */
200 static u32 itr_imr_rxr_adr[32] = {
201 0x00002100U, 0x00002100U, 0x00002104U, 0x00002104U,
202 0x00002108U, 0x00002108U, 0x0000210CU, 0x0000210CU,
203 0x00002110U, 0x00002110U, 0x00002114U, 0x00002114U,
204 0x00002118U, 0x00002118U, 0x0000211CU, 0x0000211CU,
205 0x00002120U, 0x00002120U, 0x00002124U, 0x00002124U,
206 0x00002128U, 0x00002128U, 0x0000212CU, 0x0000212CU,
207 0x00002130U, 0x00002130U, 0x00002134U, 0x00002134U,
208 0x00002138U, 0x00002138U, 0x0000213CU, 0x0000213CU
211 /* bitmask for bitfield imr_rx{r}[4:0] */
212 static u32 itr_imr_rxr_msk[32] = {
213 0x00001f00U, 0x0000001FU, 0x00001F00U, 0x0000001FU,
214 0x00001f00U, 0x0000001FU, 0x00001F00U, 0x0000001FU,
215 0x00001f00U, 0x0000001FU, 0x00001F00U, 0x0000001FU,
216 0x00001f00U, 0x0000001FU, 0x00001F00U, 0x0000001FU,
217 0x00001f00U, 0x0000001FU, 0x00001F00U, 0x0000001FU,
218 0x00001f00U, 0x0000001FU, 0x00001F00U, 0x0000001FU,
219 0x00001f00U, 0x0000001FU, 0x00001F00U, 0x0000001FU,
220 0x00001f00U, 0x0000001FU, 0x00001F00U, 0x0000001FU
223 /* lower bit position of bitfield imr_rx{r}[4:0] */
224 static u32 itr_imr_rxr_shift[32] = {
225 8U, 0U, 8U, 0U, 8U, 0U, 8U, 0U,
226 8U, 0U, 8U, 0U, 8U, 0U, 8U, 0U,
227 8U, 0U, 8U, 0U, 8U, 0U, 8U, 0U,
228 8U, 0U, 8U, 0U, 8U, 0U, 8U, 0U
231 aq_hw_write_reg_bit(aq_hw, itr_imr_rxr_adr[rx],
233 itr_imr_rxr_shift[rx],
237 void hw_atl_itr_irq_map_tx_set(struct aq_hw_s *aq_hw, u32 irq_map_tx, u32 tx)
239 /* register address for bitfield imr_tx{t}[4:0] */
240 static u32 itr_imr_txt_adr[32] = {
241 0x00002100U, 0x00002100U, 0x00002104U, 0x00002104U,
242 0x00002108U, 0x00002108U, 0x0000210CU, 0x0000210CU,
243 0x00002110U, 0x00002110U, 0x00002114U, 0x00002114U,
244 0x00002118U, 0x00002118U, 0x0000211CU, 0x0000211CU,
245 0x00002120U, 0x00002120U, 0x00002124U, 0x00002124U,
246 0x00002128U, 0x00002128U, 0x0000212CU, 0x0000212CU,
247 0x00002130U, 0x00002130U, 0x00002134U, 0x00002134U,
248 0x00002138U, 0x00002138U, 0x0000213CU, 0x0000213CU
251 /* bitmask for bitfield imr_tx{t}[4:0] */
252 static u32 itr_imr_txt_msk[32] = {
253 0x1f000000U, 0x001F0000U, 0x1F000000U, 0x001F0000U,
254 0x1f000000U, 0x001F0000U, 0x1F000000U, 0x001F0000U,
255 0x1f000000U, 0x001F0000U, 0x1F000000U, 0x001F0000U,
256 0x1f000000U, 0x001F0000U, 0x1F000000U, 0x001F0000U,
257 0x1f000000U, 0x001F0000U, 0x1F000000U, 0x001F0000U,
258 0x1f000000U, 0x001F0000U, 0x1F000000U, 0x001F0000U,
259 0x1f000000U, 0x001F0000U, 0x1F000000U, 0x001F0000U,
260 0x1f000000U, 0x001F0000U, 0x1F000000U, 0x001F0000U
263 /* lower bit position of bitfield imr_tx{t}[4:0] */
264 static u32 itr_imr_txt_shift[32] = {
265 24U, 16U, 24U, 16U, 24U, 16U, 24U, 16U,
266 24U, 16U, 24U, 16U, 24U, 16U, 24U, 16U,
267 24U, 16U, 24U, 16U, 24U, 16U, 24U, 16U,
268 24U, 16U, 24U, 16U, 24U, 16U, 24U, 16U
271 aq_hw_write_reg_bit(aq_hw, itr_imr_txt_adr[tx],
273 itr_imr_txt_shift[tx],
277 void hw_atl_itr_irq_msk_clearlsw_set(struct aq_hw_s *aq_hw,
278 u32 irq_msk_clearlsw)
280 aq_hw_write_reg(aq_hw, HW_ATL_ITR_IMCRLSW_ADR, irq_msk_clearlsw);
283 void hw_atl_itr_irq_msk_setlsw_set(struct aq_hw_s *aq_hw, u32 irq_msk_setlsw)
285 aq_hw_write_reg(aq_hw, HW_ATL_ITR_IMSRLSW_ADR, irq_msk_setlsw);
288 void hw_atl_itr_irq_reg_res_dis_set(struct aq_hw_s *aq_hw, u32 irq_reg_res_dis)
290 aq_hw_write_reg_bit(aq_hw, HW_ATL_ITR_REG_RES_DSBL_ADR,
291 HW_ATL_ITR_REG_RES_DSBL_MSK,
292 HW_ATL_ITR_REG_RES_DSBL_SHIFT, irq_reg_res_dis);
295 void hw_atl_itr_irq_status_clearlsw_set(struct aq_hw_s *aq_hw,
296 u32 irq_status_clearlsw)
298 aq_hw_write_reg(aq_hw, HW_ATL_ITR_ISCRLSW_ADR, irq_status_clearlsw);
301 u32 hw_atl_itr_irq_statuslsw_get(struct aq_hw_s *aq_hw)
303 return aq_hw_read_reg(aq_hw, HW_ATL_ITR_ISRLSW_ADR);
306 u32 hw_atl_itr_res_irq_get(struct aq_hw_s *aq_hw)
308 return aq_hw_read_reg_bit(aq_hw, HW_ATL_ITR_RES_ADR, HW_ATL_ITR_RES_MSK,
309 HW_ATL_ITR_RES_SHIFT);
312 void hw_atl_itr_res_irq_set(struct aq_hw_s *aq_hw, u32 res_irq)
314 aq_hw_write_reg_bit(aq_hw, HW_ATL_ITR_RES_ADR, HW_ATL_ITR_RES_MSK,
315 HW_ATL_ITR_RES_SHIFT, res_irq);
319 void hw_atl_rdm_cpu_id_set(struct aq_hw_s *aq_hw, u32 cpuid, u32 dca)
321 aq_hw_write_reg_bit(aq_hw, HW_ATL_RDM_DCADCPUID_ADR(dca),
322 HW_ATL_RDM_DCADCPUID_MSK,
323 HW_ATL_RDM_DCADCPUID_SHIFT, cpuid);
326 void hw_atl_rdm_rx_dca_en_set(struct aq_hw_s *aq_hw, u32 rx_dca_en)
328 aq_hw_write_reg_bit(aq_hw, HW_ATL_RDM_DCA_EN_ADR, HW_ATL_RDM_DCA_EN_MSK,
329 HW_ATL_RDM_DCA_EN_SHIFT, rx_dca_en);
332 void hw_atl_rdm_rx_dca_mode_set(struct aq_hw_s *aq_hw, u32 rx_dca_mode)
334 aq_hw_write_reg_bit(aq_hw, HW_ATL_RDM_DCA_MODE_ADR,
335 HW_ATL_RDM_DCA_MODE_MSK,
336 HW_ATL_RDM_DCA_MODE_SHIFT, rx_dca_mode);
339 void hw_atl_rdm_rx_desc_data_buff_size_set(struct aq_hw_s *aq_hw,
340 u32 rx_desc_data_buff_size,
343 aq_hw_write_reg_bit(aq_hw, HW_ATL_RDM_DESCDDATA_SIZE_ADR(descriptor),
344 HW_ATL_RDM_DESCDDATA_SIZE_MSK,
345 HW_ATL_RDM_DESCDDATA_SIZE_SHIFT,
346 rx_desc_data_buff_size);
349 void hw_atl_rdm_rx_desc_dca_en_set(struct aq_hw_s *aq_hw, u32 rx_desc_dca_en,
352 aq_hw_write_reg_bit(aq_hw, HW_ATL_RDM_DCADDESC_EN_ADR(dca),
353 HW_ATL_RDM_DCADDESC_EN_MSK,
354 HW_ATL_RDM_DCADDESC_EN_SHIFT,
358 void hw_atl_rdm_rx_desc_en_set(struct aq_hw_s *aq_hw, u32 rx_desc_en,
361 aq_hw_write_reg_bit(aq_hw, HW_ATL_RDM_DESCDEN_ADR(descriptor),
362 HW_ATL_RDM_DESCDEN_MSK,
363 HW_ATL_RDM_DESCDEN_SHIFT,
367 void hw_atl_rdm_rx_desc_head_buff_size_set(struct aq_hw_s *aq_hw,
368 u32 rx_desc_head_buff_size,
371 aq_hw_write_reg_bit(aq_hw, HW_ATL_RDM_DESCDHDR_SIZE_ADR(descriptor),
372 HW_ATL_RDM_DESCDHDR_SIZE_MSK,
373 HW_ATL_RDM_DESCDHDR_SIZE_SHIFT,
374 rx_desc_head_buff_size);
377 void hw_atl_rdm_rx_desc_head_splitting_set(struct aq_hw_s *aq_hw,
378 u32 rx_desc_head_splitting,
381 aq_hw_write_reg_bit(aq_hw, HW_ATL_RDM_DESCDHDR_SPLIT_ADR(descriptor),
382 HW_ATL_RDM_DESCDHDR_SPLIT_MSK,
383 HW_ATL_RDM_DESCDHDR_SPLIT_SHIFT,
384 rx_desc_head_splitting);
387 u32 hw_atl_rdm_rx_desc_head_ptr_get(struct aq_hw_s *aq_hw, u32 descriptor)
389 return aq_hw_read_reg_bit(aq_hw, HW_ATL_RDM_DESCDHD_ADR(descriptor),
390 HW_ATL_RDM_DESCDHD_MSK,
391 HW_ATL_RDM_DESCDHD_SHIFT);
394 void hw_atl_rdm_rx_desc_len_set(struct aq_hw_s *aq_hw, u32 rx_desc_len,
397 aq_hw_write_reg_bit(aq_hw, HW_ATL_RDM_DESCDLEN_ADR(descriptor),
398 HW_ATL_RDM_DESCDLEN_MSK, HW_ATL_RDM_DESCDLEN_SHIFT,
402 void hw_atl_rdm_rx_desc_res_set(struct aq_hw_s *aq_hw, u32 rx_desc_res,
405 aq_hw_write_reg_bit(aq_hw, HW_ATL_RDM_DESCDRESET_ADR(descriptor),
406 HW_ATL_RDM_DESCDRESET_MSK,
407 HW_ATL_RDM_DESCDRESET_SHIFT,
411 void hw_atl_rdm_rx_desc_wr_wb_irq_en_set(struct aq_hw_s *aq_hw,
412 u32 rx_desc_wr_wb_irq_en)
414 aq_hw_write_reg_bit(aq_hw, HW_ATL_RDM_INT_DESC_WRB_EN_ADR,
415 HW_ATL_RDM_INT_DESC_WRB_EN_MSK,
416 HW_ATL_RDM_INT_DESC_WRB_EN_SHIFT,
417 rx_desc_wr_wb_irq_en);
420 void hw_atl_rdm_rx_head_dca_en_set(struct aq_hw_s *aq_hw, u32 rx_head_dca_en,
423 aq_hw_write_reg_bit(aq_hw, HW_ATL_RDM_DCADHDR_EN_ADR(dca),
424 HW_ATL_RDM_DCADHDR_EN_MSK,
425 HW_ATL_RDM_DCADHDR_EN_SHIFT,
429 void hw_atl_rdm_rx_pld_dca_en_set(struct aq_hw_s *aq_hw, u32 rx_pld_dca_en,
432 aq_hw_write_reg_bit(aq_hw, HW_ATL_RDM_DCADPAY_EN_ADR(dca),
433 HW_ATL_RDM_DCADPAY_EN_MSK,
434 HW_ATL_RDM_DCADPAY_EN_SHIFT,
438 void hw_atl_rdm_rdm_intr_moder_en_set(struct aq_hw_s *aq_hw,
439 u32 rdm_intr_moder_en)
441 aq_hw_write_reg_bit(aq_hw, HW_ATL_RDM_INT_RIM_EN_ADR,
442 HW_ATL_RDM_INT_RIM_EN_MSK,
443 HW_ATL_RDM_INT_RIM_EN_SHIFT,
448 void hw_atl_reg_gen_irq_map_set(struct aq_hw_s *aq_hw, u32 gen_intr_map,
451 aq_hw_write_reg(aq_hw, HW_ATL_GEN_INTR_MAP_ADR(regidx), gen_intr_map);
454 u32 hw_atl_reg_gen_irq_status_get(struct aq_hw_s *aq_hw)
456 return aq_hw_read_reg(aq_hw, HW_ATL_GEN_INTR_STAT_ADR);
459 void hw_atl_reg_irq_glb_ctl_set(struct aq_hw_s *aq_hw, u32 intr_glb_ctl)
461 aq_hw_write_reg(aq_hw, HW_ATL_INTR_GLB_CTL_ADR, intr_glb_ctl);
464 void hw_atl_reg_irq_thr_set(struct aq_hw_s *aq_hw, u32 intr_thr, u32 throttle)
466 aq_hw_write_reg(aq_hw, HW_ATL_INTR_THR_ADR(throttle), intr_thr);
469 void hw_atl_reg_rx_dma_desc_base_addresslswset(struct aq_hw_s *aq_hw,
470 u32 rx_dma_desc_base_addrlsw,
473 aq_hw_write_reg(aq_hw, HW_ATL_RX_DMA_DESC_BASE_ADDRLSW_ADR(descriptor),
474 rx_dma_desc_base_addrlsw);
477 void hw_atl_reg_rx_dma_desc_base_addressmswset(struct aq_hw_s *aq_hw,
478 u32 rx_dma_desc_base_addrmsw,
481 aq_hw_write_reg(aq_hw, HW_ATL_RX_DMA_DESC_BASE_ADDRMSW_ADR(descriptor),
482 rx_dma_desc_base_addrmsw);
485 u32 hw_atl_reg_rx_dma_desc_status_get(struct aq_hw_s *aq_hw, u32 descriptor)
487 return aq_hw_read_reg(aq_hw, HW_ATL_RX_DMA_DESC_STAT_ADR(descriptor));
490 void hw_atl_reg_rx_dma_desc_tail_ptr_set(struct aq_hw_s *aq_hw,
491 u32 rx_dma_desc_tail_ptr,
494 aq_hw_write_reg(aq_hw, HW_ATL_RX_DMA_DESC_TAIL_PTR_ADR(descriptor),
495 rx_dma_desc_tail_ptr);
498 void hw_atl_reg_rx_flr_mcst_flr_msk_set(struct aq_hw_s *aq_hw,
499 u32 rx_flr_mcst_flr_msk)
501 aq_hw_write_reg(aq_hw, HW_ATL_RX_FLR_MCST_FLR_MSK_ADR,
502 rx_flr_mcst_flr_msk);
505 void hw_atl_reg_rx_flr_mcst_flr_set(struct aq_hw_s *aq_hw, u32 rx_flr_mcst_flr,
508 aq_hw_write_reg(aq_hw, HW_ATL_RX_FLR_MCST_FLR_ADR(filter),
512 void hw_atl_reg_rx_flr_rss_control1set(struct aq_hw_s *aq_hw,
513 u32 rx_flr_rss_control1)
515 aq_hw_write_reg(aq_hw, HW_ATL_RX_FLR_RSS_CONTROL1_ADR,
516 rx_flr_rss_control1);
519 void hw_atl_reg_rx_flr_control2_set(struct aq_hw_s *aq_hw,
520 u32 rx_filter_control2)
522 aq_hw_write_reg(aq_hw, HW_ATL_RX_FLR_CONTROL2_ADR, rx_filter_control2);
525 void hw_atl_reg_rx_intr_moder_ctrl_set(struct aq_hw_s *aq_hw,
526 u32 rx_intr_moderation_ctl,
529 aq_hw_write_reg(aq_hw, HW_ATL_RX_INTR_MODERATION_CTL_ADR(queue),
530 rx_intr_moderation_ctl);
533 void hw_atl_reg_tx_dma_debug_ctl_set(struct aq_hw_s *aq_hw,
534 u32 tx_dma_debug_ctl)
536 aq_hw_write_reg(aq_hw, HW_ATL_TX_DMA_DEBUG_CTL_ADR, tx_dma_debug_ctl);
539 void hw_atl_reg_tx_dma_desc_base_addresslswset(struct aq_hw_s *aq_hw,
540 u32 tx_dma_desc_base_addrlsw,
543 aq_hw_write_reg(aq_hw, HW_ATL_TX_DMA_DESC_BASE_ADDRLSW_ADR(descriptor),
544 tx_dma_desc_base_addrlsw);
547 void hw_atl_reg_tx_dma_desc_base_addressmswset(struct aq_hw_s *aq_hw,
548 u32 tx_dma_desc_base_addrmsw,
551 aq_hw_write_reg(aq_hw, HW_ATL_TX_DMA_DESC_BASE_ADDRMSW_ADR(descriptor),
552 tx_dma_desc_base_addrmsw);
555 void hw_atl_reg_tx_dma_desc_tail_ptr_set(struct aq_hw_s *aq_hw,
556 u32 tx_dma_desc_tail_ptr,
559 aq_hw_write_reg(aq_hw, HW_ATL_TX_DMA_DESC_TAIL_PTR_ADR(descriptor),
560 tx_dma_desc_tail_ptr);
563 void hw_atl_reg_tx_intr_moder_ctrl_set(struct aq_hw_s *aq_hw,
564 u32 tx_intr_moderation_ctl,
567 aq_hw_write_reg(aq_hw, HW_ATL_TX_INTR_MODERATION_CTL_ADR(queue),
568 tx_intr_moderation_ctl);
571 /* RPB: rx packet buffer */
572 void hw_atl_rpb_dma_sys_lbk_set(struct aq_hw_s *aq_hw, u32 dma_sys_lbk)
574 aq_hw_write_reg_bit(aq_hw, HW_ATL_RPB_DMA_SYS_LBK_ADR,
575 HW_ATL_RPB_DMA_SYS_LBK_MSK,
576 HW_ATL_RPB_DMA_SYS_LBK_SHIFT, dma_sys_lbk);
579 void hw_atl_rpb_rpf_rx_traf_class_mode_set(struct aq_hw_s *aq_hw,
580 u32 rx_traf_class_mode)
582 aq_hw_write_reg_bit(aq_hw, HW_ATL_RPB_RPF_RX_TC_MODE_ADR,
583 HW_ATL_RPB_RPF_RX_TC_MODE_MSK,
584 HW_ATL_RPB_RPF_RX_TC_MODE_SHIFT,
588 void hw_atl_rpb_rx_buff_en_set(struct aq_hw_s *aq_hw, u32 rx_buff_en)
590 aq_hw_write_reg_bit(aq_hw, HW_ATL_RPB_RX_BUF_EN_ADR,
591 HW_ATL_RPB_RX_BUF_EN_MSK,
592 HW_ATL_RPB_RX_BUF_EN_SHIFT, rx_buff_en);
595 void hw_atl_rpb_rx_buff_hi_threshold_per_tc_set(struct aq_hw_s *aq_hw,
596 u32 rx_buff_hi_threshold_per_tc,
599 aq_hw_write_reg_bit(aq_hw, HW_ATL_RPB_RXBHI_THRESH_ADR(buffer),
600 HW_ATL_RPB_RXBHI_THRESH_MSK,
601 HW_ATL_RPB_RXBHI_THRESH_SHIFT,
602 rx_buff_hi_threshold_per_tc);
605 void hw_atl_rpb_rx_buff_lo_threshold_per_tc_set(struct aq_hw_s *aq_hw,
606 u32 rx_buff_lo_threshold_per_tc,
609 aq_hw_write_reg_bit(aq_hw, HW_ATL_RPB_RXBLO_THRESH_ADR(buffer),
610 HW_ATL_RPB_RXBLO_THRESH_MSK,
611 HW_ATL_RPB_RXBLO_THRESH_SHIFT,
612 rx_buff_lo_threshold_per_tc);
615 void hw_atl_rpb_rx_flow_ctl_mode_set(struct aq_hw_s *aq_hw, u32 rx_flow_ctl_mode)
617 aq_hw_write_reg_bit(aq_hw, HW_ATL_RPB_RX_FC_MODE_ADR,
618 HW_ATL_RPB_RX_FC_MODE_MSK,
619 HW_ATL_RPB_RX_FC_MODE_SHIFT, rx_flow_ctl_mode);
622 void hw_atl_rdm_rx_dma_desc_cache_init_set(struct aq_hw_s *aq_hw, u32 init)
624 aq_hw_write_reg_bit(aq_hw, HW_ATL_RDM_RX_DMA_DESC_CACHE_INIT_ADR,
625 HW_ATL_RDM_RX_DMA_DESC_CACHE_INIT_MSK,
626 HW_ATL_RDM_RX_DMA_DESC_CACHE_INIT_SHIFT,
630 void hw_atl_rpb_rx_pkt_buff_size_per_tc_set(struct aq_hw_s *aq_hw,
631 u32 rx_pkt_buff_size_per_tc, u32 buffer)
633 aq_hw_write_reg_bit(aq_hw, HW_ATL_RPB_RXBBUF_SIZE_ADR(buffer),
634 HW_ATL_RPB_RXBBUF_SIZE_MSK,
635 HW_ATL_RPB_RXBBUF_SIZE_SHIFT,
636 rx_pkt_buff_size_per_tc);
639 void hw_atl_rpb_rx_xoff_en_per_tc_set(struct aq_hw_s *aq_hw, u32 rx_xoff_en_per_tc,
642 aq_hw_write_reg_bit(aq_hw, HW_ATL_RPB_RXBXOFF_EN_ADR(buffer),
643 HW_ATL_RPB_RXBXOFF_EN_MSK,
644 HW_ATL_RPB_RXBXOFF_EN_SHIFT,
650 void hw_atl_rpfl2broadcast_count_threshold_set(struct aq_hw_s *aq_hw,
651 u32 l2broadcast_count_threshold)
653 aq_hw_write_reg_bit(aq_hw, HW_ATL_RPFL2BC_THRESH_ADR,
654 HW_ATL_RPFL2BC_THRESH_MSK,
655 HW_ATL_RPFL2BC_THRESH_SHIFT,
656 l2broadcast_count_threshold);
659 void hw_atl_rpfl2broadcast_en_set(struct aq_hw_s *aq_hw, u32 l2broadcast_en)
661 aq_hw_write_reg_bit(aq_hw, HW_ATL_RPFL2BC_EN_ADR, HW_ATL_RPFL2BC_EN_MSK,
662 HW_ATL_RPFL2BC_EN_SHIFT, l2broadcast_en);
665 void hw_atl_rpfl2broadcast_flr_act_set(struct aq_hw_s *aq_hw,
666 u32 l2broadcast_flr_act)
668 aq_hw_write_reg_bit(aq_hw, HW_ATL_RPFL2BC_ACT_ADR,
669 HW_ATL_RPFL2BC_ACT_MSK,
670 HW_ATL_RPFL2BC_ACT_SHIFT, l2broadcast_flr_act);
673 void hw_atl_rpfl2multicast_flr_en_set(struct aq_hw_s *aq_hw,
674 u32 l2multicast_flr_en,
677 aq_hw_write_reg_bit(aq_hw, HW_ATL_RPFL2MC_ENF_ADR(filter),
678 HW_ATL_RPFL2MC_ENF_MSK,
679 HW_ATL_RPFL2MC_ENF_SHIFT, l2multicast_flr_en);
682 void hw_atl_rpfl2promiscuous_mode_en_set(struct aq_hw_s *aq_hw,
683 u32 l2promiscuous_mode_en)
685 aq_hw_write_reg_bit(aq_hw, HW_ATL_RPFL2PROMIS_MODE_ADR,
686 HW_ATL_RPFL2PROMIS_MODE_MSK,
687 HW_ATL_RPFL2PROMIS_MODE_SHIFT,
688 l2promiscuous_mode_en);
691 void hw_atl_rpfl2unicast_flr_act_set(struct aq_hw_s *aq_hw,
692 u32 l2unicast_flr_act,
695 aq_hw_write_reg_bit(aq_hw, HW_ATL_RPFL2UC_ACTF_ADR(filter),
696 HW_ATL_RPFL2UC_ACTF_MSK, HW_ATL_RPFL2UC_ACTF_SHIFT,
700 void hw_atl_rpfl2_uc_flr_en_set(struct aq_hw_s *aq_hw, u32 l2unicast_flr_en,
703 aq_hw_write_reg_bit(aq_hw, HW_ATL_RPFL2UC_ENF_ADR(filter),
704 HW_ATL_RPFL2UC_ENF_MSK,
705 HW_ATL_RPFL2UC_ENF_SHIFT, l2unicast_flr_en);
708 void hw_atl_rpfl2unicast_dest_addresslsw_set(struct aq_hw_s *aq_hw,
709 u32 l2unicast_dest_addresslsw,
712 aq_hw_write_reg(aq_hw, HW_ATL_RPFL2UC_DAFLSW_ADR(filter),
713 l2unicast_dest_addresslsw);
716 void hw_atl_rpfl2unicast_dest_addressmsw_set(struct aq_hw_s *aq_hw,
717 u32 l2unicast_dest_addressmsw,
720 aq_hw_write_reg_bit(aq_hw, HW_ATL_RPFL2UC_DAFMSW_ADR(filter),
721 HW_ATL_RPFL2UC_DAFMSW_MSK,
722 HW_ATL_RPFL2UC_DAFMSW_SHIFT,
723 l2unicast_dest_addressmsw);
726 void hw_atl_rpfl2_accept_all_mc_packets_set(struct aq_hw_s *aq_hw,
727 u32 l2_accept_all_mc_packets)
729 aq_hw_write_reg_bit(aq_hw, HW_ATL_RPFL2MC_ACCEPT_ALL_ADR,
730 HW_ATL_RPFL2MC_ACCEPT_ALL_MSK,
731 HW_ATL_RPFL2MC_ACCEPT_ALL_SHIFT,
732 l2_accept_all_mc_packets);
735 void hw_atl_rpf_rpb_user_priority_tc_map_set(struct aq_hw_s *aq_hw,
736 u32 user_priority_tc_map, u32 tc)
738 /* register address for bitfield rx_tc_up{t}[2:0] */
739 static u32 rpf_rpb_rx_tc_upt_adr[8] = {
740 0x000054c4U, 0x000054C4U, 0x000054C4U, 0x000054C4U,
741 0x000054c4U, 0x000054C4U, 0x000054C4U, 0x000054C4U
744 /* bitmask for bitfield rx_tc_up{t}[2:0] */
745 static u32 rpf_rpb_rx_tc_upt_msk[8] = {
746 0x00000007U, 0x00000070U, 0x00000700U, 0x00007000U,
747 0x00070000U, 0x00700000U, 0x07000000U, 0x70000000U
750 /* lower bit position of bitfield rx_tc_up{t}[2:0] */
751 static u32 rpf_rpb_rx_tc_upt_shft[8] = {
752 0U, 4U, 8U, 12U, 16U, 20U, 24U, 28U
755 aq_hw_write_reg_bit(aq_hw, rpf_rpb_rx_tc_upt_adr[tc],
756 rpf_rpb_rx_tc_upt_msk[tc],
757 rpf_rpb_rx_tc_upt_shft[tc],
758 user_priority_tc_map);
761 void hw_atl_rpf_rss_key_addr_set(struct aq_hw_s *aq_hw, u32 rss_key_addr)
763 aq_hw_write_reg_bit(aq_hw, HW_ATL_RPF_RSS_KEY_ADDR_ADR,
764 HW_ATL_RPF_RSS_KEY_ADDR_MSK,
765 HW_ATL_RPF_RSS_KEY_ADDR_SHIFT,
769 void hw_atl_rpf_rss_key_wr_data_set(struct aq_hw_s *aq_hw, u32 rss_key_wr_data)
771 aq_hw_write_reg(aq_hw, HW_ATL_RPF_RSS_KEY_WR_DATA_ADR,
775 u32 hw_atl_rpf_rss_key_wr_en_get(struct aq_hw_s *aq_hw)
777 return aq_hw_read_reg_bit(aq_hw, HW_ATL_RPF_RSS_KEY_WR_ENI_ADR,
778 HW_ATL_RPF_RSS_KEY_WR_ENI_MSK,
779 HW_ATL_RPF_RSS_KEY_WR_ENI_SHIFT);
782 void hw_atl_rpf_rss_key_wr_en_set(struct aq_hw_s *aq_hw, u32 rss_key_wr_en)
784 aq_hw_write_reg_bit(aq_hw, HW_ATL_RPF_RSS_KEY_WR_ENI_ADR,
785 HW_ATL_RPF_RSS_KEY_WR_ENI_MSK,
786 HW_ATL_RPF_RSS_KEY_WR_ENI_SHIFT,
790 void hw_atl_rpf_rss_redir_tbl_addr_set(struct aq_hw_s *aq_hw,
791 u32 rss_redir_tbl_addr)
793 aq_hw_write_reg_bit(aq_hw, HW_ATL_RPF_RSS_REDIR_ADDR_ADR,
794 HW_ATL_RPF_RSS_REDIR_ADDR_MSK,
795 HW_ATL_RPF_RSS_REDIR_ADDR_SHIFT,
799 void hw_atl_rpf_rss_redir_tbl_wr_data_set(struct aq_hw_s *aq_hw,
800 u32 rss_redir_tbl_wr_data)
802 aq_hw_write_reg_bit(aq_hw, HW_ATL_RPF_RSS_REDIR_WR_DATA_ADR,
803 HW_ATL_RPF_RSS_REDIR_WR_DATA_MSK,
804 HW_ATL_RPF_RSS_REDIR_WR_DATA_SHIFT,
805 rss_redir_tbl_wr_data);
808 u32 hw_atl_rpf_rss_redir_wr_en_get(struct aq_hw_s *aq_hw)
810 return aq_hw_read_reg_bit(aq_hw, HW_ATL_RPF_RSS_REDIR_WR_ENI_ADR,
811 HW_ATL_RPF_RSS_REDIR_WR_ENI_MSK,
812 HW_ATL_RPF_RSS_REDIR_WR_ENI_SHIFT);
815 void hw_atl_rpf_rss_redir_wr_en_set(struct aq_hw_s *aq_hw, u32 rss_redir_wr_en)
817 aq_hw_write_reg_bit(aq_hw, HW_ATL_RPF_RSS_REDIR_WR_ENI_ADR,
818 HW_ATL_RPF_RSS_REDIR_WR_ENI_MSK,
819 HW_ATL_RPF_RSS_REDIR_WR_ENI_SHIFT, rss_redir_wr_en);
822 void hw_atl_rpf_tpo_to_rpf_sys_lbk_set(struct aq_hw_s *aq_hw,
823 u32 tpo_to_rpf_sys_lbk)
825 aq_hw_write_reg_bit(aq_hw, HW_ATL_RPF_TPO_RPF_SYS_LBK_ADR,
826 HW_ATL_RPF_TPO_RPF_SYS_LBK_MSK,
827 HW_ATL_RPF_TPO_RPF_SYS_LBK_SHIFT,
831 void hw_atl_rpf_vlan_inner_etht_set(struct aq_hw_s *aq_hw, u32 vlan_inner_etht)
833 aq_hw_write_reg_bit(aq_hw, HW_ATL_RPF_VL_INNER_TPID_ADR,
834 HW_ATL_RPF_VL_INNER_TPID_MSK,
835 HW_ATL_RPF_VL_INNER_TPID_SHIFT,
839 void hw_atl_rpf_vlan_outer_etht_set(struct aq_hw_s *aq_hw, u32 vlan_outer_etht)
841 aq_hw_write_reg_bit(aq_hw, HW_ATL_RPF_VL_OUTER_TPID_ADR,
842 HW_ATL_RPF_VL_OUTER_TPID_MSK,
843 HW_ATL_RPF_VL_OUTER_TPID_SHIFT,
847 void hw_atl_rpf_vlan_prom_mode_en_set(struct aq_hw_s *aq_hw,
848 u32 vlan_prom_mode_en)
850 aq_hw_write_reg_bit(aq_hw, HW_ATL_RPF_VL_PROMIS_MODE_ADR,
851 HW_ATL_RPF_VL_PROMIS_MODE_MSK,
852 HW_ATL_RPF_VL_PROMIS_MODE_SHIFT,
856 void hw_atl_rpf_vlan_accept_untagged_packets_set(struct aq_hw_s *aq_hw,
857 u32 vlan_acc_untagged_packets)
859 aq_hw_write_reg_bit(aq_hw, HW_ATL_RPF_VL_ACCEPT_UNTAGGED_MODE_ADR,
860 HW_ATL_RPF_VL_ACCEPT_UNTAGGED_MODE_MSK,
861 HW_ATL_RPF_VL_ACCEPT_UNTAGGED_MODE_SHIFT,
862 vlan_acc_untagged_packets);
865 void hw_atl_rpf_vlan_untagged_act_set(struct aq_hw_s *aq_hw,
866 u32 vlan_untagged_act)
868 aq_hw_write_reg_bit(aq_hw, HW_ATL_RPF_VL_UNTAGGED_ACT_ADR,
869 HW_ATL_RPF_VL_UNTAGGED_ACT_MSK,
870 HW_ATL_RPF_VL_UNTAGGED_ACT_SHIFT,
874 void hw_atl_rpf_vlan_flr_en_set(struct aq_hw_s *aq_hw, u32 vlan_flr_en,
877 aq_hw_write_reg_bit(aq_hw, HW_ATL_RPF_VL_EN_F_ADR(filter),
878 HW_ATL_RPF_VL_EN_F_MSK,
879 HW_ATL_RPF_VL_EN_F_SHIFT,
883 void hw_atl_rpf_vlan_flr_act_set(struct aq_hw_s *aq_hw, u32 vlan_flr_act,
886 aq_hw_write_reg_bit(aq_hw, HW_ATL_RPF_VL_ACT_F_ADR(filter),
887 HW_ATL_RPF_VL_ACT_F_MSK,
888 HW_ATL_RPF_VL_ACT_F_SHIFT,
892 void hw_atl_rpf_vlan_id_flr_set(struct aq_hw_s *aq_hw, u32 vlan_id_flr,
895 aq_hw_write_reg_bit(aq_hw, HW_ATL_RPF_VL_ID_F_ADR(filter),
896 HW_ATL_RPF_VL_ID_F_MSK,
897 HW_ATL_RPF_VL_ID_F_SHIFT,
901 void hw_atl_rpf_vlan_rxq_en_flr_set(struct aq_hw_s *aq_hw, u32 vlan_rxq_en,
904 aq_hw_write_reg_bit(aq_hw, HW_ATL_RPF_VL_RXQ_EN_F_ADR(filter),
905 HW_ATL_RPF_VL_RXQ_EN_F_MSK,
906 HW_ATL_RPF_VL_RXQ_EN_F_SHIFT,
910 void hw_atl_rpf_vlan_rxq_flr_set(struct aq_hw_s *aq_hw, u32 vlan_rxq,
913 aq_hw_write_reg_bit(aq_hw, HW_ATL_RPF_VL_RXQ_F_ADR(filter),
914 HW_ATL_RPF_VL_RXQ_F_MSK,
915 HW_ATL_RPF_VL_RXQ_F_SHIFT,
919 void hw_atl_rpf_etht_flr_en_set(struct aq_hw_s *aq_hw, u32 etht_flr_en,
922 aq_hw_write_reg_bit(aq_hw, HW_ATL_RPF_ET_ENF_ADR(filter),
923 HW_ATL_RPF_ET_ENF_MSK,
924 HW_ATL_RPF_ET_ENF_SHIFT, etht_flr_en);
927 void hw_atl_rpf_etht_user_priority_en_set(struct aq_hw_s *aq_hw,
928 u32 etht_user_priority_en, u32 filter)
930 aq_hw_write_reg_bit(aq_hw, HW_ATL_RPF_ET_UPFEN_ADR(filter),
931 HW_ATL_RPF_ET_UPFEN_MSK, HW_ATL_RPF_ET_UPFEN_SHIFT,
932 etht_user_priority_en);
935 void hw_atl_rpf_etht_rx_queue_en_set(struct aq_hw_s *aq_hw,
936 u32 etht_rx_queue_en,
939 aq_hw_write_reg_bit(aq_hw, HW_ATL_RPF_ET_RXQFEN_ADR(filter),
940 HW_ATL_RPF_ET_RXQFEN_MSK,
941 HW_ATL_RPF_ET_RXQFEN_SHIFT,
945 void hw_atl_rpf_etht_user_priority_set(struct aq_hw_s *aq_hw,
946 u32 etht_user_priority,
949 aq_hw_write_reg_bit(aq_hw, HW_ATL_RPF_ET_UPF_ADR(filter),
950 HW_ATL_RPF_ET_UPF_MSK,
951 HW_ATL_RPF_ET_UPF_SHIFT, etht_user_priority);
954 void hw_atl_rpf_etht_rx_queue_set(struct aq_hw_s *aq_hw, u32 etht_rx_queue,
957 aq_hw_write_reg_bit(aq_hw, HW_ATL_RPF_ET_RXQF_ADR(filter),
958 HW_ATL_RPF_ET_RXQF_MSK,
959 HW_ATL_RPF_ET_RXQF_SHIFT, etht_rx_queue);
962 void hw_atl_rpf_etht_mgt_queue_set(struct aq_hw_s *aq_hw, u32 etht_mgt_queue,
965 aq_hw_write_reg_bit(aq_hw, HW_ATL_RPF_ET_MNG_RXQF_ADR(filter),
966 HW_ATL_RPF_ET_MNG_RXQF_MSK,
967 HW_ATL_RPF_ET_MNG_RXQF_SHIFT,
971 void hw_atl_rpf_etht_flr_act_set(struct aq_hw_s *aq_hw, u32 etht_flr_act,
974 aq_hw_write_reg_bit(aq_hw, HW_ATL_RPF_ET_ACTF_ADR(filter),
975 HW_ATL_RPF_ET_ACTF_MSK,
976 HW_ATL_RPF_ET_ACTF_SHIFT, etht_flr_act);
979 void hw_atl_rpf_etht_flr_set(struct aq_hw_s *aq_hw, u32 etht_flr, u32 filter)
981 aq_hw_write_reg_bit(aq_hw, HW_ATL_RPF_ET_VALF_ADR(filter),
982 HW_ATL_RPF_ET_VALF_MSK,
983 HW_ATL_RPF_ET_VALF_SHIFT, etht_flr);
986 void hw_atl_rpf_l4_spd_set(struct aq_hw_s *aq_hw, u32 val, u32 filter)
988 aq_hw_write_reg_bit(aq_hw, HW_ATL_RPF_L4_SPD_ADR(filter),
989 HW_ATL_RPF_L4_SPD_MSK,
990 HW_ATL_RPF_L4_SPD_SHIFT, val);
993 void hw_atl_rpf_l4_dpd_set(struct aq_hw_s *aq_hw, u32 val, u32 filter)
995 aq_hw_write_reg_bit(aq_hw, HW_ATL_RPF_L4_DPD_ADR(filter),
996 HW_ATL_RPF_L4_DPD_MSK,
997 HW_ATL_RPF_L4_DPD_SHIFT, val);
1000 /* RPO: rx packet offload */
1001 void hw_atl_rpo_ipv4header_crc_offload_en_set(struct aq_hw_s *aq_hw,
1002 u32 ipv4header_crc_offload_en)
1004 aq_hw_write_reg_bit(aq_hw, HW_ATL_RPO_IPV4CHK_EN_ADR,
1005 HW_ATL_RPO_IPV4CHK_EN_MSK,
1006 HW_ATL_RPO_IPV4CHK_EN_SHIFT,
1007 ipv4header_crc_offload_en);
1010 void hw_atl_rpo_rx_desc_vlan_stripping_set(struct aq_hw_s *aq_hw,
1011 u32 rx_desc_vlan_stripping,
1014 aq_hw_write_reg_bit(aq_hw, HW_ATL_RPO_DESCDVL_STRIP_ADR(descriptor),
1015 HW_ATL_RPO_DESCDVL_STRIP_MSK,
1016 HW_ATL_RPO_DESCDVL_STRIP_SHIFT,
1017 rx_desc_vlan_stripping);
1020 void hw_atl_rpo_tcp_udp_crc_offload_en_set(struct aq_hw_s *aq_hw,
1021 u32 tcp_udp_crc_offload_en)
1023 aq_hw_write_reg_bit(aq_hw, HW_ATL_RPOL4CHK_EN_ADR,
1024 HW_ATL_RPOL4CHK_EN_MSK,
1025 HW_ATL_RPOL4CHK_EN_SHIFT, tcp_udp_crc_offload_en);
1028 void hw_atl_rpo_lro_en_set(struct aq_hw_s *aq_hw, u32 lro_en)
1030 aq_hw_write_reg(aq_hw, HW_ATL_RPO_LRO_EN_ADR, lro_en);
1033 void hw_atl_rpo_lro_patch_optimization_en_set(struct aq_hw_s *aq_hw,
1034 u32 lro_patch_optimization_en)
1036 aq_hw_write_reg_bit(aq_hw, HW_ATL_RPO_LRO_PTOPT_EN_ADR,
1037 HW_ATL_RPO_LRO_PTOPT_EN_MSK,
1038 HW_ATL_RPO_LRO_PTOPT_EN_SHIFT,
1039 lro_patch_optimization_en);
1042 void hw_atl_rpo_lro_qsessions_lim_set(struct aq_hw_s *aq_hw,
1043 u32 lro_qsessions_lim)
1045 aq_hw_write_reg_bit(aq_hw, HW_ATL_RPO_LRO_QSES_LMT_ADR,
1046 HW_ATL_RPO_LRO_QSES_LMT_MSK,
1047 HW_ATL_RPO_LRO_QSES_LMT_SHIFT,
1051 void hw_atl_rpo_lro_total_desc_lim_set(struct aq_hw_s *aq_hw,
1052 u32 lro_total_desc_lim)
1054 aq_hw_write_reg_bit(aq_hw, HW_ATL_RPO_LRO_TOT_DSC_LMT_ADR,
1055 HW_ATL_RPO_LRO_TOT_DSC_LMT_MSK,
1056 HW_ATL_RPO_LRO_TOT_DSC_LMT_SHIFT,
1057 lro_total_desc_lim);
1060 void hw_atl_rpo_lro_min_pay_of_first_pkt_set(struct aq_hw_s *aq_hw,
1061 u32 lro_min_pld_of_first_pkt)
1063 aq_hw_write_reg_bit(aq_hw, HW_ATL_RPO_LRO_PKT_MIN_ADR,
1064 HW_ATL_RPO_LRO_PKT_MIN_MSK,
1065 HW_ATL_RPO_LRO_PKT_MIN_SHIFT,
1066 lro_min_pld_of_first_pkt);
1069 void hw_atl_rpo_lro_pkt_lim_set(struct aq_hw_s *aq_hw, u32 lro_pkt_lim)
1071 aq_hw_write_reg(aq_hw, HW_ATL_RPO_LRO_RSC_MAX_ADR, lro_pkt_lim);
1074 void hw_atl_rpo_lro_max_num_of_descriptors_set(struct aq_hw_s *aq_hw,
1075 u32 lro_max_number_of_descriptors,
1078 /* Register address for bitfield lro{L}_des_max[1:0] */
1079 static u32 rpo_lro_ldes_max_adr[32] = {
1080 0x000055A0U, 0x000055A0U, 0x000055A0U, 0x000055A0U,
1081 0x000055A0U, 0x000055A0U, 0x000055A0U, 0x000055A0U,
1082 0x000055A4U, 0x000055A4U, 0x000055A4U, 0x000055A4U,
1083 0x000055A4U, 0x000055A4U, 0x000055A4U, 0x000055A4U,
1084 0x000055A8U, 0x000055A8U, 0x000055A8U, 0x000055A8U,
1085 0x000055A8U, 0x000055A8U, 0x000055A8U, 0x000055A8U,
1086 0x000055ACU, 0x000055ACU, 0x000055ACU, 0x000055ACU,
1087 0x000055ACU, 0x000055ACU, 0x000055ACU, 0x000055ACU
1090 /* Bitmask for bitfield lro{L}_des_max[1:0] */
1091 static u32 rpo_lro_ldes_max_msk[32] = {
1092 0x00000003U, 0x00000030U, 0x00000300U, 0x00003000U,
1093 0x00030000U, 0x00300000U, 0x03000000U, 0x30000000U,
1094 0x00000003U, 0x00000030U, 0x00000300U, 0x00003000U,
1095 0x00030000U, 0x00300000U, 0x03000000U, 0x30000000U,
1096 0x00000003U, 0x00000030U, 0x00000300U, 0x00003000U,
1097 0x00030000U, 0x00300000U, 0x03000000U, 0x30000000U,
1098 0x00000003U, 0x00000030U, 0x00000300U, 0x00003000U,
1099 0x00030000U, 0x00300000U, 0x03000000U, 0x30000000U
1102 /* Lower bit position of bitfield lro{L}_des_max[1:0] */
1103 static u32 rpo_lro_ldes_max_shift[32] = {
1104 0U, 4U, 8U, 12U, 16U, 20U, 24U, 28U,
1105 0U, 4U, 8U, 12U, 16U, 20U, 24U, 28U,
1106 0U, 4U, 8U, 12U, 16U, 20U, 24U, 28U,
1107 0U, 4U, 8U, 12U, 16U, 20U, 24U, 28U
1110 aq_hw_write_reg_bit(aq_hw, rpo_lro_ldes_max_adr[lro],
1111 rpo_lro_ldes_max_msk[lro],
1112 rpo_lro_ldes_max_shift[lro],
1113 lro_max_number_of_descriptors);
1116 void hw_atl_rpo_lro_time_base_divider_set(struct aq_hw_s *aq_hw,
1117 u32 lro_time_base_divider)
1119 aq_hw_write_reg_bit(aq_hw, HW_ATL_RPO_LRO_TB_DIV_ADR,
1120 HW_ATL_RPO_LRO_TB_DIV_MSK,
1121 HW_ATL_RPO_LRO_TB_DIV_SHIFT,
1122 lro_time_base_divider);
1125 void hw_atl_rpo_lro_inactive_interval_set(struct aq_hw_s *aq_hw,
1126 u32 lro_inactive_interval)
1128 aq_hw_write_reg_bit(aq_hw, HW_ATL_RPO_LRO_INA_IVAL_ADR,
1129 HW_ATL_RPO_LRO_INA_IVAL_MSK,
1130 HW_ATL_RPO_LRO_INA_IVAL_SHIFT,
1131 lro_inactive_interval);
1134 void hw_atl_rpo_lro_max_coalescing_interval_set(struct aq_hw_s *aq_hw,
1135 u32 lro_max_coal_interval)
1137 aq_hw_write_reg_bit(aq_hw, HW_ATL_RPO_LRO_MAX_IVAL_ADR,
1138 HW_ATL_RPO_LRO_MAX_IVAL_MSK,
1139 HW_ATL_RPO_LRO_MAX_IVAL_SHIFT,
1140 lro_max_coal_interval);
1144 void hw_atl_rx_rx_reg_res_dis_set(struct aq_hw_s *aq_hw, u32 rx_reg_res_dis)
1146 aq_hw_write_reg_bit(aq_hw, HW_ATL_RX_REG_RES_DSBL_ADR,
1147 HW_ATL_RX_REG_RES_DSBL_MSK,
1148 HW_ATL_RX_REG_RES_DSBL_SHIFT,
1153 void hw_atl_tdm_cpu_id_set(struct aq_hw_s *aq_hw, u32 cpuid, u32 dca)
1155 aq_hw_write_reg_bit(aq_hw, HW_ATL_TDM_DCADCPUID_ADR(dca),
1156 HW_ATL_TDM_DCADCPUID_MSK,
1157 HW_ATL_TDM_DCADCPUID_SHIFT, cpuid);
1160 void hw_atl_tdm_large_send_offload_en_set(struct aq_hw_s *aq_hw,
1161 u32 large_send_offload_en)
1163 aq_hw_write_reg(aq_hw, HW_ATL_TDM_LSO_EN_ADR, large_send_offload_en);
1166 void hw_atl_tdm_tx_dca_en_set(struct aq_hw_s *aq_hw, u32 tx_dca_en)
1168 aq_hw_write_reg_bit(aq_hw, HW_ATL_TDM_DCA_EN_ADR, HW_ATL_TDM_DCA_EN_MSK,
1169 HW_ATL_TDM_DCA_EN_SHIFT, tx_dca_en);
1172 void hw_atl_tdm_tx_dca_mode_set(struct aq_hw_s *aq_hw, u32 tx_dca_mode)
1174 aq_hw_write_reg_bit(aq_hw, HW_ATL_TDM_DCA_MODE_ADR,
1175 HW_ATL_TDM_DCA_MODE_MSK,
1176 HW_ATL_TDM_DCA_MODE_SHIFT, tx_dca_mode);
1179 void hw_atl_tdm_tx_desc_dca_en_set(struct aq_hw_s *aq_hw, u32 tx_desc_dca_en,
1182 aq_hw_write_reg_bit(aq_hw, HW_ATL_TDM_DCADDESC_EN_ADR(dca),
1183 HW_ATL_TDM_DCADDESC_EN_MSK,
1184 HW_ATL_TDM_DCADDESC_EN_SHIFT,
1188 void hw_atl_tdm_tx_desc_en_set(struct aq_hw_s *aq_hw, u32 tx_desc_en,
1191 aq_hw_write_reg_bit(aq_hw, HW_ATL_TDM_DESCDEN_ADR(descriptor),
1192 HW_ATL_TDM_DESCDEN_MSK,
1193 HW_ATL_TDM_DESCDEN_SHIFT,
1197 u32 hw_atl_tdm_tx_desc_head_ptr_get(struct aq_hw_s *aq_hw, u32 descriptor)
1199 return aq_hw_read_reg_bit(aq_hw, HW_ATL_TDM_DESCDHD_ADR(descriptor),
1200 HW_ATL_TDM_DESCDHD_MSK,
1201 HW_ATL_TDM_DESCDHD_SHIFT);
1204 void hw_atl_tdm_tx_desc_len_set(struct aq_hw_s *aq_hw, u32 tx_desc_len,
1207 aq_hw_write_reg_bit(aq_hw, HW_ATL_TDM_DESCDLEN_ADR(descriptor),
1208 HW_ATL_TDM_DESCDLEN_MSK,
1209 HW_ATL_TDM_DESCDLEN_SHIFT,
1213 void hw_atl_tdm_tx_desc_wr_wb_irq_en_set(struct aq_hw_s *aq_hw,
1214 u32 tx_desc_wr_wb_irq_en)
1216 aq_hw_write_reg_bit(aq_hw, HW_ATL_TDM_INT_DESC_WRB_EN_ADR,
1217 HW_ATL_TDM_INT_DESC_WRB_EN_MSK,
1218 HW_ATL_TDM_INT_DESC_WRB_EN_SHIFT,
1219 tx_desc_wr_wb_irq_en);
1222 void hw_atl_tdm_tx_desc_wr_wb_threshold_set(struct aq_hw_s *aq_hw,
1223 u32 tx_desc_wr_wb_threshold,
1226 aq_hw_write_reg_bit(aq_hw, HW_ATL_TDM_DESCDWRB_THRESH_ADR(descriptor),
1227 HW_ATL_TDM_DESCDWRB_THRESH_MSK,
1228 HW_ATL_TDM_DESCDWRB_THRESH_SHIFT,
1229 tx_desc_wr_wb_threshold);
1232 void hw_atl_tdm_tdm_intr_moder_en_set(struct aq_hw_s *aq_hw,
1233 u32 tdm_irq_moderation_en)
1235 aq_hw_write_reg_bit(aq_hw, HW_ATL_TDM_INT_MOD_EN_ADR,
1236 HW_ATL_TDM_INT_MOD_EN_MSK,
1237 HW_ATL_TDM_INT_MOD_EN_SHIFT,
1238 tdm_irq_moderation_en);
1242 void hw_atl_thm_lso_tcp_flag_of_first_pkt_set(struct aq_hw_s *aq_hw,
1243 u32 lso_tcp_flag_of_first_pkt)
1245 aq_hw_write_reg_bit(aq_hw, HW_ATL_THM_LSO_TCP_FLAG_FIRST_ADR,
1246 HW_ATL_THM_LSO_TCP_FLAG_FIRST_MSK,
1247 HW_ATL_THM_LSO_TCP_FLAG_FIRST_SHIFT,
1248 lso_tcp_flag_of_first_pkt);
1251 void hw_atl_thm_lso_tcp_flag_of_last_pkt_set(struct aq_hw_s *aq_hw,
1252 u32 lso_tcp_flag_of_last_pkt)
1254 aq_hw_write_reg_bit(aq_hw, HW_ATL_THM_LSO_TCP_FLAG_LAST_ADR,
1255 HW_ATL_THM_LSO_TCP_FLAG_LAST_MSK,
1256 HW_ATL_THM_LSO_TCP_FLAG_LAST_SHIFT,
1257 lso_tcp_flag_of_last_pkt);
1260 void hw_atl_thm_lso_tcp_flag_of_middle_pkt_set(struct aq_hw_s *aq_hw,
1261 u32 lso_tcp_flag_of_middle_pkt)
1263 aq_hw_write_reg_bit(aq_hw, HW_ATL_THM_LSO_TCP_FLAG_MID_ADR,
1264 HW_ATL_THM_LSO_TCP_FLAG_MID_MSK,
1265 HW_ATL_THM_LSO_TCP_FLAG_MID_SHIFT,
1266 lso_tcp_flag_of_middle_pkt);
1269 /* TPB: tx packet buffer */
1270 void hw_atl_tpb_tx_buff_en_set(struct aq_hw_s *aq_hw, u32 tx_buff_en)
1272 aq_hw_write_reg_bit(aq_hw, HW_ATL_TPB_TX_BUF_EN_ADR,
1273 HW_ATL_TPB_TX_BUF_EN_MSK,
1274 HW_ATL_TPB_TX_BUF_EN_SHIFT, tx_buff_en);
1277 void hw_atl_tpb_tx_buff_hi_threshold_per_tc_set(struct aq_hw_s *aq_hw,
1278 u32 tx_buff_hi_threshold_per_tc,
1281 aq_hw_write_reg_bit(aq_hw, HW_ATL_TPB_TXBHI_THRESH_ADR(buffer),
1282 HW_ATL_TPB_TXBHI_THRESH_MSK,
1283 HW_ATL_TPB_TXBHI_THRESH_SHIFT,
1284 tx_buff_hi_threshold_per_tc);
1287 void hw_atl_tpb_tx_buff_lo_threshold_per_tc_set(struct aq_hw_s *aq_hw,
1288 u32 tx_buff_lo_threshold_per_tc,
1291 aq_hw_write_reg_bit(aq_hw, HW_ATL_TPB_TXBLO_THRESH_ADR(buffer),
1292 HW_ATL_TPB_TXBLO_THRESH_MSK,
1293 HW_ATL_TPB_TXBLO_THRESH_SHIFT,
1294 tx_buff_lo_threshold_per_tc);
1297 void hw_atl_tpb_tx_dma_sys_lbk_en_set(struct aq_hw_s *aq_hw, u32 tx_dma_sys_lbk_en)
1299 aq_hw_write_reg_bit(aq_hw, HW_ATL_TPB_DMA_SYS_LBK_ADR,
1300 HW_ATL_TPB_DMA_SYS_LBK_MSK,
1301 HW_ATL_TPB_DMA_SYS_LBK_SHIFT,
1305 void hw_atl_tpb_tx_pkt_buff_size_per_tc_set(struct aq_hw_s *aq_hw,
1306 u32 tx_pkt_buff_size_per_tc, u32 buffer)
1308 aq_hw_write_reg_bit(aq_hw, HW_ATL_TPB_TXBBUF_SIZE_ADR(buffer),
1309 HW_ATL_TPB_TXBBUF_SIZE_MSK,
1310 HW_ATL_TPB_TXBBUF_SIZE_SHIFT,
1311 tx_pkt_buff_size_per_tc);
1314 void hw_atl_tpb_tx_path_scp_ins_en_set(struct aq_hw_s *aq_hw, u32 tx_path_scp_ins_en)
1316 aq_hw_write_reg_bit(aq_hw, HW_ATL_TPB_TX_SCP_INS_EN_ADR,
1317 HW_ATL_TPB_TX_SCP_INS_EN_MSK,
1318 HW_ATL_TPB_TX_SCP_INS_EN_SHIFT,
1319 tx_path_scp_ins_en);
1322 /* TPO: tx packet offload */
1323 void hw_atl_tpo_ipv4header_crc_offload_en_set(struct aq_hw_s *aq_hw,
1324 u32 ipv4header_crc_offload_en)
1326 aq_hw_write_reg_bit(aq_hw, HW_ATL_TPO_IPV4CHK_EN_ADR,
1327 HW_ATL_TPO_IPV4CHK_EN_MSK,
1328 HW_ATL_TPO_IPV4CHK_EN_SHIFT,
1329 ipv4header_crc_offload_en);
1332 void hw_atl_tpo_tcp_udp_crc_offload_en_set(struct aq_hw_s *aq_hw,
1333 u32 tcp_udp_crc_offload_en)
1335 aq_hw_write_reg_bit(aq_hw, HW_ATL_TPOL4CHK_EN_ADR,
1336 HW_ATL_TPOL4CHK_EN_MSK,
1337 HW_ATL_TPOL4CHK_EN_SHIFT,
1338 tcp_udp_crc_offload_en);
1341 void hw_atl_tpo_tx_pkt_sys_lbk_en_set(struct aq_hw_s *aq_hw,
1342 u32 tx_pkt_sys_lbk_en)
1344 aq_hw_write_reg_bit(aq_hw, HW_ATL_TPO_PKT_SYS_LBK_ADR,
1345 HW_ATL_TPO_PKT_SYS_LBK_MSK,
1346 HW_ATL_TPO_PKT_SYS_LBK_SHIFT,
1350 /* TPS: tx packet scheduler */
1351 void hw_atl_tps_tx_pkt_shed_data_arb_mode_set(struct aq_hw_s *aq_hw,
1352 u32 tx_pkt_shed_data_arb_mode)
1354 aq_hw_write_reg_bit(aq_hw, HW_ATL_TPS_DATA_TC_ARB_MODE_ADR,
1355 HW_ATL_TPS_DATA_TC_ARB_MODE_MSK,
1356 HW_ATL_TPS_DATA_TC_ARB_MODE_SHIFT,
1357 tx_pkt_shed_data_arb_mode);
1360 void hw_atl_tps_tx_pkt_shed_desc_rate_curr_time_res_set(struct aq_hw_s *aq_hw,
1363 aq_hw_write_reg_bit(aq_hw, HW_ATL_TPS_DESC_RATE_TA_RST_ADR,
1364 HW_ATL_TPS_DESC_RATE_TA_RST_MSK,
1365 HW_ATL_TPS_DESC_RATE_TA_RST_SHIFT,
1369 void hw_atl_tps_tx_pkt_shed_desc_rate_lim_set(struct aq_hw_s *aq_hw,
1370 u32 tx_pkt_shed_desc_rate_lim)
1372 aq_hw_write_reg_bit(aq_hw, HW_ATL_TPS_DESC_RATE_LIM_ADR,
1373 HW_ATL_TPS_DESC_RATE_LIM_MSK,
1374 HW_ATL_TPS_DESC_RATE_LIM_SHIFT,
1375 tx_pkt_shed_desc_rate_lim);
1378 void hw_atl_tps_tx_pkt_shed_desc_tc_arb_mode_set(struct aq_hw_s *aq_hw,
1381 aq_hw_write_reg_bit(aq_hw, HW_ATL_TPS_DESC_TC_ARB_MODE_ADR,
1382 HW_ATL_TPS_DESC_TC_ARB_MODE_MSK,
1383 HW_ATL_TPS_DESC_TC_ARB_MODE_SHIFT,
1387 void hw_atl_tps_tx_pkt_shed_desc_tc_max_credit_set(struct aq_hw_s *aq_hw,
1391 aq_hw_write_reg_bit(aq_hw, HW_ATL_TPS_DESC_TCTCREDIT_MAX_ADR(tc),
1392 HW_ATL_TPS_DESC_TCTCREDIT_MAX_MSK,
1393 HW_ATL_TPS_DESC_TCTCREDIT_MAX_SHIFT,
1397 void hw_atl_tps_tx_pkt_shed_desc_tc_weight_set(struct aq_hw_s *aq_hw,
1398 u32 tx_pkt_shed_desc_tc_weight,
1401 aq_hw_write_reg_bit(aq_hw, HW_ATL_TPS_DESC_TCTWEIGHT_ADR(tc),
1402 HW_ATL_TPS_DESC_TCTWEIGHT_MSK,
1403 HW_ATL_TPS_DESC_TCTWEIGHT_SHIFT,
1404 tx_pkt_shed_desc_tc_weight);
1407 void hw_atl_tps_tx_pkt_shed_desc_vm_arb_mode_set(struct aq_hw_s *aq_hw,
1410 aq_hw_write_reg_bit(aq_hw, HW_ATL_TPS_DESC_VM_ARB_MODE_ADR,
1411 HW_ATL_TPS_DESC_VM_ARB_MODE_MSK,
1412 HW_ATL_TPS_DESC_VM_ARB_MODE_SHIFT,
1416 void hw_atl_tps_tx_pkt_shed_tc_data_max_credit_set(struct aq_hw_s *aq_hw,
1420 aq_hw_write_reg_bit(aq_hw, HW_ATL_TPS_DATA_TCTCREDIT_MAX_ADR(tc),
1421 HW_ATL_TPS_DATA_TCTCREDIT_MAX_MSK,
1422 HW_ATL_TPS_DATA_TCTCREDIT_MAX_SHIFT,
1426 void hw_atl_tps_tx_pkt_shed_tc_data_weight_set(struct aq_hw_s *aq_hw,
1427 u32 tx_pkt_shed_tc_data_weight,
1430 aq_hw_write_reg_bit(aq_hw, HW_ATL_TPS_DATA_TCTWEIGHT_ADR(tc),
1431 HW_ATL_TPS_DATA_TCTWEIGHT_MSK,
1432 HW_ATL_TPS_DATA_TCTWEIGHT_SHIFT,
1433 tx_pkt_shed_tc_data_weight);
1437 void hw_atl_tx_tx_reg_res_dis_set(struct aq_hw_s *aq_hw, u32 tx_reg_res_dis)
1439 aq_hw_write_reg_bit(aq_hw, HW_ATL_TX_REG_RES_DSBL_ADR,
1440 HW_ATL_TX_REG_RES_DSBL_MSK,
1441 HW_ATL_TX_REG_RES_DSBL_SHIFT, tx_reg_res_dis);
1445 u32 hw_atl_msm_reg_access_status_get(struct aq_hw_s *aq_hw)
1447 return aq_hw_read_reg_bit(aq_hw, HW_ATL_MSM_REG_ACCESS_BUSY_ADR,
1448 HW_ATL_MSM_REG_ACCESS_BUSY_MSK,
1449 HW_ATL_MSM_REG_ACCESS_BUSY_SHIFT);
1452 void hw_atl_msm_reg_addr_for_indirect_addr_set(struct aq_hw_s *aq_hw,
1453 u32 reg_addr_for_indirect_addr)
1455 aq_hw_write_reg_bit(aq_hw, HW_ATL_MSM_REG_ADDR_ADR,
1456 HW_ATL_MSM_REG_ADDR_MSK,
1457 HW_ATL_MSM_REG_ADDR_SHIFT,
1458 reg_addr_for_indirect_addr);
1461 void hw_atl_msm_reg_rd_strobe_set(struct aq_hw_s *aq_hw, u32 reg_rd_strobe)
1463 aq_hw_write_reg_bit(aq_hw, HW_ATL_MSM_REG_RD_STROBE_ADR,
1464 HW_ATL_MSM_REG_RD_STROBE_MSK,
1465 HW_ATL_MSM_REG_RD_STROBE_SHIFT,
1469 u32 hw_atl_msm_reg_rd_data_get(struct aq_hw_s *aq_hw)
1471 return aq_hw_read_reg(aq_hw, HW_ATL_MSM_REG_RD_DATA_ADR);
1474 void hw_atl_msm_reg_wr_data_set(struct aq_hw_s *aq_hw, u32 reg_wr_data)
1476 aq_hw_write_reg(aq_hw, HW_ATL_MSM_REG_WR_DATA_ADR, reg_wr_data);
1479 void hw_atl_msm_reg_wr_strobe_set(struct aq_hw_s *aq_hw, u32 reg_wr_strobe)
1481 aq_hw_write_reg_bit(aq_hw, HW_ATL_MSM_REG_WR_STROBE_ADR,
1482 HW_ATL_MSM_REG_WR_STROBE_MSK,
1483 HW_ATL_MSM_REG_WR_STROBE_SHIFT,
1488 void hw_atl_pci_pci_reg_res_dis_set(struct aq_hw_s *aq_hw, u32 pci_reg_res_dis)
1490 aq_hw_write_reg_bit(aq_hw, HW_ATL_PCI_REG_RES_DSBL_ADR,
1491 HW_ATL_PCI_REG_RES_DSBL_MSK,
1492 HW_ATL_PCI_REG_RES_DSBL_SHIFT,
1496 void hw_atl_reg_glb_cpu_scratch_scp_set(struct aq_hw_s *aq_hw,
1497 u32 glb_cpu_scratch_scp,
1500 aq_hw_write_reg(aq_hw, HW_ATL_GLB_CPU_SCRATCH_SCP_ADR(scratch_scp),
1501 glb_cpu_scratch_scp);
1504 void hw_atl_mcp_up_force_intr_set(struct aq_hw_s *aq_hw, u32 up_force_intr)
1506 aq_hw_write_reg_bit(aq_hw, HW_ATL_MCP_UP_FORCE_INTERRUPT_ADR,
1507 HW_ATL_MCP_UP_FORCE_INTERRUPT_MSK,
1508 HW_ATL_MCP_UP_FORCE_INTERRUPT_SHIFT,
1512 void hw_atl_rpfl3l4_ipv4_dest_addr_clear(struct aq_hw_s *aq_hw, u8 location)
1514 aq_hw_write_reg(aq_hw, HW_ATL_RPF_L3_DSTA_ADR(location), 0U);
1517 void hw_atl_rpfl3l4_ipv4_src_addr_clear(struct aq_hw_s *aq_hw, u8 location)
1519 aq_hw_write_reg(aq_hw, HW_ATL_RPF_L3_SRCA_ADR(location), 0U);
1522 void hw_atl_rpfl3l4_cmd_clear(struct aq_hw_s *aq_hw, u8 location)
1524 aq_hw_write_reg(aq_hw, HW_ATL_RPF_L3_REG_CTRL_ADR(location), 0U);
1527 void hw_atl_rpfl3l4_ipv6_dest_addr_clear(struct aq_hw_s *aq_hw, u8 location)
1531 for (i = 0; i < 4; ++i)
1532 aq_hw_write_reg(aq_hw,
1533 HW_ATL_RPF_L3_DSTA_ADR(location + i),
1537 void hw_atl_rpfl3l4_ipv6_src_addr_clear(struct aq_hw_s *aq_hw, u8 location)
1541 for (i = 0; i < 4; ++i)
1542 aq_hw_write_reg(aq_hw,
1543 HW_ATL_RPF_L3_SRCA_ADR(location + i),
1547 void hw_atl_rpfl3l4_ipv4_dest_addr_set(struct aq_hw_s *aq_hw, u8 location,
1550 aq_hw_write_reg(aq_hw, HW_ATL_RPF_L3_DSTA_ADR(location),
1554 void hw_atl_rpfl3l4_ipv4_src_addr_set(struct aq_hw_s *aq_hw, u8 location,
1557 aq_hw_write_reg(aq_hw,
1558 HW_ATL_RPF_L3_SRCA_ADR(location),
1562 void hw_atl_rpfl3l4_cmd_set(struct aq_hw_s *aq_hw, u8 location, u32 cmd)
1564 aq_hw_write_reg(aq_hw, HW_ATL_RPF_L3_REG_CTRL_ADR(location), cmd);
1567 void hw_atl_rpfl3l4_ipv6_src_addr_set(struct aq_hw_s *aq_hw, u8 location,
1572 for (i = 0; i < 4; ++i)
1573 aq_hw_write_reg(aq_hw,
1574 HW_ATL_RPF_L3_SRCA_ADR(location + i),
1578 void hw_atl_rpfl3l4_ipv6_dest_addr_set(struct aq_hw_s *aq_hw, u8 location,
1583 for (i = 0; i < 4; ++i)
1584 aq_hw_write_reg(aq_hw,
1585 HW_ATL_RPF_L3_DSTA_ADR(location + i),