2 * AMD 10Gb Ethernet driver
4 * This file is available to you under your choice of the following two
9 * Copyright (c) 2016 Advanced Micro Devices, Inc.
11 * This file is free software; you may copy, redistribute and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation, either version 2 of the License, or (at
14 * your option) any later version.
16 * This file is distributed in the hope that it will be useful, but
17 * WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
19 * General Public License for more details.
21 * You should have received a copy of the GNU General Public License
22 * along with this program. If not, see <http://www.gnu.org/licenses/>.
24 * This file incorporates work covered by the following copyright and
26 * The Synopsys DWC ETHER XGMAC Software Driver and documentation
27 * (hereinafter "Software") is an unsupported proprietary work of Synopsys,
28 * Inc. unless otherwise expressly agreed to in writing between Synopsys
31 * The Software IS NOT an item of Licensed Software or Licensed Product
32 * under any End User Software License Agreement or Agreement for Licensed
33 * Product with Synopsys or any supplement thereto. Permission is hereby
34 * granted, free of charge, to any person obtaining a copy of this software
35 * annotated with this license and the Software, to deal in the Software
36 * without restriction, including without limitation the rights to use,
37 * copy, modify, merge, publish, distribute, sublicense, and/or sell copies
38 * of the Software, and to permit persons to whom the Software is furnished
39 * to do so, subject to the following conditions:
41 * The above copyright notice and this permission notice shall be included
42 * in all copies or substantial portions of the Software.
44 * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS"
45 * BASIS AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
46 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
47 * PARTICULAR PURPOSE ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS
48 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
49 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
50 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
51 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
52 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
53 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
54 * THE POSSIBILITY OF SUCH DAMAGE.
57 * License 2: Modified BSD
59 * Copyright (c) 2016 Advanced Micro Devices, Inc.
60 * All rights reserved.
62 * Redistribution and use in source and binary forms, with or without
63 * modification, are permitted provided that the following conditions are met:
64 * * Redistributions of source code must retain the above copyright
65 * notice, this list of conditions and the following disclaimer.
66 * * Redistributions in binary form must reproduce the above copyright
67 * notice, this list of conditions and the following disclaimer in the
68 * documentation and/or other materials provided with the distribution.
69 * * Neither the name of Advanced Micro Devices, Inc. nor the
70 * names of its contributors may be used to endorse or promote products
71 * derived from this software without specific prior written permission.
73 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
74 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
75 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
76 * ARE DISCLAIMED. IN NO EVENT SHALL <COPYRIGHT HOLDER> BE LIABLE FOR ANY
77 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
78 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
79 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
80 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
81 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
82 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
84 * This file incorporates work covered by the following copyright and
86 * The Synopsys DWC ETHER XGMAC Software Driver and documentation
87 * (hereinafter "Software") is an unsupported proprietary work of Synopsys,
88 * Inc. unless otherwise expressly agreed to in writing between Synopsys
91 * The Software IS NOT an item of Licensed Software or Licensed Product
92 * under any End User Software License Agreement or Agreement for Licensed
93 * Product with Synopsys or any supplement thereto. Permission is hereby
94 * granted, free of charge, to any person obtaining a copy of this software
95 * annotated with this license and the Software, to deal in the Software
96 * without restriction, including without limitation the rights to use,
97 * copy, modify, merge, publish, distribute, sublicense, and/or sell copies
98 * of the Software, and to permit persons to whom the Software is furnished
99 * to do so, subject to the following conditions:
101 * The above copyright notice and this permission notice shall be included
102 * in all copies or substantial portions of the Software.
104 * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS"
105 * BASIS AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
106 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
107 * PARTICULAR PURPOSE ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS
108 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
109 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
110 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
111 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
112 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
113 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
114 * THE POSSIBILITY OF SUCH DAMAGE.
117 #include <linux/module.h>
118 #include <linux/device.h>
119 #include <linux/kmod.h>
120 #include <linux/mdio.h>
121 #include <linux/phy.h>
122 #include <linux/ethtool.h>
125 #include "xgbe-common.h"
127 #define XGBE_PHY_PORT_SPEED_100 BIT(0)
128 #define XGBE_PHY_PORT_SPEED_1000 BIT(1)
129 #define XGBE_PHY_PORT_SPEED_2500 BIT(2)
130 #define XGBE_PHY_PORT_SPEED_10000 BIT(3)
132 #define XGBE_MUTEX_RELEASE 0x80000000
134 #define XGBE_SFP_DIRECT 7
136 /* I2C target addresses */
137 #define XGBE_SFP_SERIAL_ID_ADDRESS 0x50
138 #define XGBE_SFP_DIAG_INFO_ADDRESS 0x51
139 #define XGBE_SFP_PHY_ADDRESS 0x56
140 #define XGBE_GPIO_ADDRESS_PCA9555 0x20
142 /* SFP sideband signal indicators */
143 #define XGBE_GPIO_NO_TX_FAULT BIT(0)
144 #define XGBE_GPIO_NO_RATE_SELECT BIT(1)
145 #define XGBE_GPIO_NO_MOD_ABSENT BIT(2)
146 #define XGBE_GPIO_NO_RX_LOS BIT(3)
148 /* Rate-change complete wait/retry count */
149 #define XGBE_RATECHANGE_COUNT 500
151 /* CDR delay values for KR support (in usec) */
152 #define XGBE_CDR_DELAY_INIT 10000
153 #define XGBE_CDR_DELAY_INC 10000
154 #define XGBE_CDR_DELAY_MAX 100000
156 /* RRC frequency during link status check */
157 #define XGBE_RRC_FREQUENCY 10
159 enum xgbe_port_mode {
160 XGBE_PORT_MODE_RSVD = 0,
161 XGBE_PORT_MODE_BACKPLANE,
162 XGBE_PORT_MODE_BACKPLANE_2500,
163 XGBE_PORT_MODE_1000BASE_T,
164 XGBE_PORT_MODE_1000BASE_X,
165 XGBE_PORT_MODE_NBASE_T,
166 XGBE_PORT_MODE_10GBASE_T,
167 XGBE_PORT_MODE_10GBASE_R,
169 XGBE_PORT_MODE_BACKPLANE_NO_AUTONEG,
173 enum xgbe_conn_type {
174 XGBE_CONN_TYPE_NONE = 0,
177 XGBE_CONN_TYPE_RSVD1,
178 XGBE_CONN_TYPE_BACKPLANE,
182 /* SFP/SFP+ related definitions */
184 XGBE_SFP_COMM_DIRECT = 0,
185 XGBE_SFP_COMM_PCA9545,
188 enum xgbe_sfp_cable {
189 XGBE_SFP_CABLE_UNKNOWN = 0,
190 XGBE_SFP_CABLE_ACTIVE,
191 XGBE_SFP_CABLE_PASSIVE,
195 XGBE_SFP_BASE_UNKNOWN = 0,
196 XGBE_SFP_BASE_1000_T,
197 XGBE_SFP_BASE_1000_SX,
198 XGBE_SFP_BASE_1000_LX,
199 XGBE_SFP_BASE_1000_CX,
200 XGBE_SFP_BASE_10000_SR,
201 XGBE_SFP_BASE_10000_LR,
202 XGBE_SFP_BASE_10000_LRM,
203 XGBE_SFP_BASE_10000_ER,
204 XGBE_SFP_BASE_10000_CR,
207 enum xgbe_sfp_speed {
208 XGBE_SFP_SPEED_UNKNOWN = 0,
209 XGBE_SFP_SPEED_100_1000,
211 XGBE_SFP_SPEED_10000,
214 /* SFP Serial ID Base ID values relative to an offset of 0 */
215 #define XGBE_SFP_BASE_ID 0
216 #define XGBE_SFP_ID_SFP 0x03
218 #define XGBE_SFP_BASE_EXT_ID 1
219 #define XGBE_SFP_EXT_ID_SFP 0x04
221 #define XGBE_SFP_BASE_10GBE_CC 3
222 #define XGBE_SFP_BASE_10GBE_CC_SR BIT(4)
223 #define XGBE_SFP_BASE_10GBE_CC_LR BIT(5)
224 #define XGBE_SFP_BASE_10GBE_CC_LRM BIT(6)
225 #define XGBE_SFP_BASE_10GBE_CC_ER BIT(7)
227 #define XGBE_SFP_BASE_1GBE_CC 6
228 #define XGBE_SFP_BASE_1GBE_CC_SX BIT(0)
229 #define XGBE_SFP_BASE_1GBE_CC_LX BIT(1)
230 #define XGBE_SFP_BASE_1GBE_CC_CX BIT(2)
231 #define XGBE_SFP_BASE_1GBE_CC_T BIT(3)
233 #define XGBE_SFP_BASE_CABLE 8
234 #define XGBE_SFP_BASE_CABLE_PASSIVE BIT(2)
235 #define XGBE_SFP_BASE_CABLE_ACTIVE BIT(3)
237 #define XGBE_SFP_BASE_BR 12
238 #define XGBE_SFP_BASE_BR_1GBE_MIN 0x0a
239 #define XGBE_SFP_BASE_BR_1GBE_MAX 0x0d
240 #define XGBE_SFP_BASE_BR_10GBE_MIN 0x64
241 #define XGBE_SFP_BASE_BR_10GBE_MAX 0x68
243 #define XGBE_SFP_BASE_CU_CABLE_LEN 18
245 #define XGBE_SFP_BASE_VENDOR_NAME 20
246 #define XGBE_SFP_BASE_VENDOR_NAME_LEN 16
247 #define XGBE_SFP_BASE_VENDOR_PN 40
248 #define XGBE_SFP_BASE_VENDOR_PN_LEN 16
249 #define XGBE_SFP_BASE_VENDOR_REV 56
250 #define XGBE_SFP_BASE_VENDOR_REV_LEN 4
252 #define XGBE_SFP_BASE_CC 63
254 /* SFP Serial ID Extended ID values relative to an offset of 64 */
255 #define XGBE_SFP_BASE_VENDOR_SN 4
256 #define XGBE_SFP_BASE_VENDOR_SN_LEN 16
258 #define XGBE_SFP_EXTD_OPT1 1
259 #define XGBE_SFP_EXTD_OPT1_RX_LOS BIT(1)
260 #define XGBE_SFP_EXTD_OPT1_TX_FAULT BIT(3)
262 #define XGBE_SFP_EXTD_DIAG 28
263 #define XGBE_SFP_EXTD_DIAG_ADDR_CHANGE BIT(2)
265 #define XGBE_SFP_EXTD_SFF_8472 30
267 #define XGBE_SFP_EXTD_CC 31
269 struct xgbe_sfp_eeprom {
275 #define XGBE_SFP_DIAGS_SUPPORTED(_x) \
276 ((_x)->extd[XGBE_SFP_EXTD_SFF_8472] && \
277 !((_x)->extd[XGBE_SFP_EXTD_DIAG] & XGBE_SFP_EXTD_DIAG_ADDR_CHANGE))
279 #define XGBE_SFP_EEPROM_BASE_LEN 256
280 #define XGBE_SFP_EEPROM_DIAG_LEN 256
281 #define XGBE_SFP_EEPROM_MAX (XGBE_SFP_EEPROM_BASE_LEN + \
282 XGBE_SFP_EEPROM_DIAG_LEN)
284 #define XGBE_BEL_FUSE_VENDOR "BEL-FUSE "
285 #define XGBE_BEL_FUSE_PARTNO "1GBT-SFP06 "
287 struct xgbe_sfp_ascii {
289 char vendor[XGBE_SFP_BASE_VENDOR_NAME_LEN + 1];
290 char partno[XGBE_SFP_BASE_VENDOR_PN_LEN + 1];
291 char rev[XGBE_SFP_BASE_VENDOR_REV_LEN + 1];
292 char serno[XGBE_SFP_BASE_VENDOR_SN_LEN + 1];
296 /* MDIO PHY reset types */
297 enum xgbe_mdio_reset {
298 XGBE_MDIO_RESET_NONE = 0,
299 XGBE_MDIO_RESET_I2C_GPIO,
300 XGBE_MDIO_RESET_INT_GPIO,
304 /* Re-driver related definitions */
305 enum xgbe_phy_redrv_if {
306 XGBE_PHY_REDRV_IF_MDIO = 0,
307 XGBE_PHY_REDRV_IF_I2C,
308 XGBE_PHY_REDRV_IF_MAX,
311 enum xgbe_phy_redrv_model {
312 XGBE_PHY_REDRV_MODEL_4223 = 0,
313 XGBE_PHY_REDRV_MODEL_4227,
314 XGBE_PHY_REDRV_MODEL_MAX,
317 enum xgbe_phy_redrv_mode {
318 XGBE_PHY_REDRV_MODE_CX = 5,
319 XGBE_PHY_REDRV_MODE_SR = 9,
322 #define XGBE_PHY_REDRV_MODE_REG 0x12b0
324 /* PHY related configuration information */
325 struct xgbe_phy_data {
326 enum xgbe_port_mode port_mode;
328 unsigned int port_id;
330 unsigned int port_speeds;
332 enum xgbe_conn_type conn_type;
334 enum xgbe_mode cur_mode;
335 enum xgbe_mode start_mode;
337 unsigned int rrc_count;
339 unsigned int mdio_addr;
342 enum xgbe_sfp_comm sfp_comm;
343 unsigned int sfp_mux_address;
344 unsigned int sfp_mux_channel;
346 unsigned int sfp_gpio_address;
347 unsigned int sfp_gpio_mask;
348 unsigned int sfp_gpio_inputs;
349 unsigned int sfp_gpio_rx_los;
350 unsigned int sfp_gpio_tx_fault;
351 unsigned int sfp_gpio_mod_absent;
352 unsigned int sfp_gpio_rate_select;
354 unsigned int sfp_rx_los;
355 unsigned int sfp_tx_fault;
356 unsigned int sfp_mod_absent;
357 unsigned int sfp_changed;
358 unsigned int sfp_phy_avail;
359 unsigned int sfp_cable_len;
360 enum xgbe_sfp_base sfp_base;
361 enum xgbe_sfp_cable sfp_cable;
362 enum xgbe_sfp_speed sfp_speed;
363 struct xgbe_sfp_eeprom sfp_eeprom;
365 /* External PHY support */
366 enum xgbe_mdio_mode phydev_mode;
368 struct phy_device *phydev;
369 enum xgbe_mdio_reset mdio_reset;
370 unsigned int mdio_reset_addr;
371 unsigned int mdio_reset_gpio;
373 /* Re-driver support */
375 unsigned int redrv_if;
376 unsigned int redrv_addr;
377 unsigned int redrv_lane;
378 unsigned int redrv_model;
381 unsigned int phy_cdr_notrack;
382 unsigned int phy_cdr_delay;
385 /* I2C, MDIO and GPIO lines are muxed, so only one device at a time */
386 static DEFINE_MUTEX(xgbe_phy_comm_lock);
388 static enum xgbe_an_mode xgbe_phy_an_mode(struct xgbe_prv_data *pdata);
390 static int xgbe_phy_i2c_xfer(struct xgbe_prv_data *pdata,
391 struct xgbe_i2c_op *i2c_op)
393 return pdata->i2c_if.i2c_xfer(pdata, i2c_op);
396 static int xgbe_phy_redrv_write(struct xgbe_prv_data *pdata, unsigned int reg,
399 struct xgbe_phy_data *phy_data = pdata->phy_data;
400 struct xgbe_i2c_op i2c_op;
402 u8 redrv_data[5], csum;
403 unsigned int i, retry;
406 /* High byte of register contains read/write indicator */
407 redrv_data[0] = ((reg >> 8) & 0xff) << 1;
408 redrv_data[1] = reg & 0xff;
409 redrv_val = (__be16 *)&redrv_data[2];
410 *redrv_val = cpu_to_be16(val);
412 /* Calculate 1 byte checksum */
414 for (i = 0; i < 4; i++) {
415 csum += redrv_data[i];
416 if (redrv_data[i] > csum)
419 redrv_data[4] = ~csum;
423 i2c_op.cmd = XGBE_I2C_CMD_WRITE;
424 i2c_op.target = phy_data->redrv_addr;
425 i2c_op.len = sizeof(redrv_data);
426 i2c_op.buf = redrv_data;
427 ret = xgbe_phy_i2c_xfer(pdata, &i2c_op);
429 if ((ret == -EAGAIN) && retry--)
437 i2c_op.cmd = XGBE_I2C_CMD_READ;
438 i2c_op.target = phy_data->redrv_addr;
440 i2c_op.buf = redrv_data;
441 ret = xgbe_phy_i2c_xfer(pdata, &i2c_op);
443 if ((ret == -EAGAIN) && retry--)
449 if (redrv_data[0] != 0xff) {
450 netif_dbg(pdata, drv, pdata->netdev,
451 "Redriver write checksum error\n");
458 static int xgbe_phy_i2c_write(struct xgbe_prv_data *pdata, unsigned int target,
459 void *val, unsigned int val_len)
461 struct xgbe_i2c_op i2c_op;
466 /* Write the specfied register */
467 i2c_op.cmd = XGBE_I2C_CMD_WRITE;
468 i2c_op.target = target;
469 i2c_op.len = val_len;
471 ret = xgbe_phy_i2c_xfer(pdata, &i2c_op);
472 if ((ret == -EAGAIN) && retry--)
478 static int xgbe_phy_i2c_read(struct xgbe_prv_data *pdata, unsigned int target,
479 void *reg, unsigned int reg_len,
480 void *val, unsigned int val_len)
482 struct xgbe_i2c_op i2c_op;
487 /* Set the specified register to read */
488 i2c_op.cmd = XGBE_I2C_CMD_WRITE;
489 i2c_op.target = target;
490 i2c_op.len = reg_len;
492 ret = xgbe_phy_i2c_xfer(pdata, &i2c_op);
494 if ((ret == -EAGAIN) && retry--)
502 /* Read the specfied register */
503 i2c_op.cmd = XGBE_I2C_CMD_READ;
504 i2c_op.target = target;
505 i2c_op.len = val_len;
507 ret = xgbe_phy_i2c_xfer(pdata, &i2c_op);
508 if ((ret == -EAGAIN) && retry--)
514 static int xgbe_phy_sfp_put_mux(struct xgbe_prv_data *pdata)
516 struct xgbe_phy_data *phy_data = pdata->phy_data;
517 struct xgbe_i2c_op i2c_op;
520 if (phy_data->sfp_comm == XGBE_SFP_COMM_DIRECT)
523 /* Select no mux channels */
525 i2c_op.cmd = XGBE_I2C_CMD_WRITE;
526 i2c_op.target = phy_data->sfp_mux_address;
527 i2c_op.len = sizeof(mux_channel);
528 i2c_op.buf = &mux_channel;
530 return xgbe_phy_i2c_xfer(pdata, &i2c_op);
533 static int xgbe_phy_sfp_get_mux(struct xgbe_prv_data *pdata)
535 struct xgbe_phy_data *phy_data = pdata->phy_data;
536 struct xgbe_i2c_op i2c_op;
539 if (phy_data->sfp_comm == XGBE_SFP_COMM_DIRECT)
542 /* Select desired mux channel */
543 mux_channel = 1 << phy_data->sfp_mux_channel;
544 i2c_op.cmd = XGBE_I2C_CMD_WRITE;
545 i2c_op.target = phy_data->sfp_mux_address;
546 i2c_op.len = sizeof(mux_channel);
547 i2c_op.buf = &mux_channel;
549 return xgbe_phy_i2c_xfer(pdata, &i2c_op);
552 static void xgbe_phy_put_comm_ownership(struct xgbe_prv_data *pdata)
554 mutex_unlock(&xgbe_phy_comm_lock);
557 static int xgbe_phy_get_comm_ownership(struct xgbe_prv_data *pdata)
559 struct xgbe_phy_data *phy_data = pdata->phy_data;
560 unsigned long timeout;
561 unsigned int mutex_id;
563 /* The I2C and MDIO/GPIO bus is multiplexed between multiple devices,
564 * the driver needs to take the software mutex and then the hardware
565 * mutexes before being able to use the busses.
567 mutex_lock(&xgbe_phy_comm_lock);
569 /* Clear the mutexes */
570 XP_IOWRITE(pdata, XP_I2C_MUTEX, XGBE_MUTEX_RELEASE);
571 XP_IOWRITE(pdata, XP_MDIO_MUTEX, XGBE_MUTEX_RELEASE);
573 /* Mutex formats are the same for I2C and MDIO/GPIO */
575 XP_SET_BITS(mutex_id, XP_I2C_MUTEX, ID, phy_data->port_id);
576 XP_SET_BITS(mutex_id, XP_I2C_MUTEX, ACTIVE, 1);
578 timeout = jiffies + (5 * HZ);
579 while (time_before(jiffies, timeout)) {
580 /* Must be all zeroes in order to obtain the mutex */
581 if (XP_IOREAD(pdata, XP_I2C_MUTEX) ||
582 XP_IOREAD(pdata, XP_MDIO_MUTEX)) {
583 usleep_range(100, 200);
587 /* Obtain the mutex */
588 XP_IOWRITE(pdata, XP_I2C_MUTEX, mutex_id);
589 XP_IOWRITE(pdata, XP_MDIO_MUTEX, mutex_id);
594 mutex_unlock(&xgbe_phy_comm_lock);
596 netdev_err(pdata->netdev, "unable to obtain hardware mutexes\n");
601 static int xgbe_phy_mdio_mii_write(struct xgbe_prv_data *pdata, int addr,
604 struct xgbe_phy_data *phy_data = pdata->phy_data;
606 if (reg & MII_ADDR_C45) {
607 if (phy_data->phydev_mode != XGBE_MDIO_MODE_CL45)
610 if (phy_data->phydev_mode != XGBE_MDIO_MODE_CL22)
614 return pdata->hw_if.write_ext_mii_regs(pdata, addr, reg, val);
617 static int xgbe_phy_i2c_mii_write(struct xgbe_prv_data *pdata, int reg, u16 val)
623 ret = xgbe_phy_sfp_get_mux(pdata);
627 mii_data[0] = reg & 0xff;
628 mii_val = (__be16 *)&mii_data[1];
629 *mii_val = cpu_to_be16(val);
631 ret = xgbe_phy_i2c_write(pdata, XGBE_SFP_PHY_ADDRESS,
632 mii_data, sizeof(mii_data));
634 xgbe_phy_sfp_put_mux(pdata);
639 static int xgbe_phy_mii_write(struct mii_bus *mii, int addr, int reg, u16 val)
641 struct xgbe_prv_data *pdata = mii->priv;
642 struct xgbe_phy_data *phy_data = pdata->phy_data;
645 ret = xgbe_phy_get_comm_ownership(pdata);
649 if (phy_data->conn_type == XGBE_CONN_TYPE_SFP)
650 ret = xgbe_phy_i2c_mii_write(pdata, reg, val);
651 else if (phy_data->conn_type & XGBE_CONN_TYPE_MDIO)
652 ret = xgbe_phy_mdio_mii_write(pdata, addr, reg, val);
656 xgbe_phy_put_comm_ownership(pdata);
661 static int xgbe_phy_mdio_mii_read(struct xgbe_prv_data *pdata, int addr,
664 struct xgbe_phy_data *phy_data = pdata->phy_data;
666 if (reg & MII_ADDR_C45) {
667 if (phy_data->phydev_mode != XGBE_MDIO_MODE_CL45)
670 if (phy_data->phydev_mode != XGBE_MDIO_MODE_CL22)
674 return pdata->hw_if.read_ext_mii_regs(pdata, addr, reg);
677 static int xgbe_phy_i2c_mii_read(struct xgbe_prv_data *pdata, int reg)
683 ret = xgbe_phy_sfp_get_mux(pdata);
688 ret = xgbe_phy_i2c_read(pdata, XGBE_SFP_PHY_ADDRESS,
689 &mii_reg, sizeof(mii_reg),
690 &mii_val, sizeof(mii_val));
692 ret = be16_to_cpu(mii_val);
694 xgbe_phy_sfp_put_mux(pdata);
699 static int xgbe_phy_mii_read(struct mii_bus *mii, int addr, int reg)
701 struct xgbe_prv_data *pdata = mii->priv;
702 struct xgbe_phy_data *phy_data = pdata->phy_data;
705 ret = xgbe_phy_get_comm_ownership(pdata);
709 if (phy_data->conn_type == XGBE_CONN_TYPE_SFP)
710 ret = xgbe_phy_i2c_mii_read(pdata, reg);
711 else if (phy_data->conn_type & XGBE_CONN_TYPE_MDIO)
712 ret = xgbe_phy_mdio_mii_read(pdata, addr, reg);
716 xgbe_phy_put_comm_ownership(pdata);
721 static void xgbe_phy_sfp_phy_settings(struct xgbe_prv_data *pdata)
723 struct ethtool_link_ksettings *lks = &pdata->phy.lks;
724 struct xgbe_phy_data *phy_data = pdata->phy_data;
726 if (!phy_data->sfp_mod_absent && !phy_data->sfp_changed)
731 if (phy_data->sfp_mod_absent) {
732 pdata->phy.speed = SPEED_UNKNOWN;
733 pdata->phy.duplex = DUPLEX_UNKNOWN;
734 pdata->phy.autoneg = AUTONEG_ENABLE;
735 pdata->phy.pause_autoneg = AUTONEG_ENABLE;
737 XGBE_SET_SUP(lks, Autoneg);
738 XGBE_SET_SUP(lks, Pause);
739 XGBE_SET_SUP(lks, Asym_Pause);
740 XGBE_SET_SUP(lks, TP);
741 XGBE_SET_SUP(lks, FIBRE);
743 XGBE_LM_COPY(lks, advertising, lks, supported);
748 switch (phy_data->sfp_base) {
749 case XGBE_SFP_BASE_1000_T:
750 case XGBE_SFP_BASE_1000_SX:
751 case XGBE_SFP_BASE_1000_LX:
752 case XGBE_SFP_BASE_1000_CX:
753 pdata->phy.speed = SPEED_UNKNOWN;
754 pdata->phy.duplex = DUPLEX_UNKNOWN;
755 pdata->phy.autoneg = AUTONEG_ENABLE;
756 pdata->phy.pause_autoneg = AUTONEG_ENABLE;
757 XGBE_SET_SUP(lks, Autoneg);
758 XGBE_SET_SUP(lks, Pause);
759 XGBE_SET_SUP(lks, Asym_Pause);
760 if (phy_data->sfp_base == XGBE_SFP_BASE_1000_T) {
761 if (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_100)
762 XGBE_SET_SUP(lks, 100baseT_Full);
763 if (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_1000)
764 XGBE_SET_SUP(lks, 1000baseT_Full);
766 if (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_1000)
767 XGBE_SET_SUP(lks, 1000baseX_Full);
770 case XGBE_SFP_BASE_10000_SR:
771 case XGBE_SFP_BASE_10000_LR:
772 case XGBE_SFP_BASE_10000_LRM:
773 case XGBE_SFP_BASE_10000_ER:
774 case XGBE_SFP_BASE_10000_CR:
775 pdata->phy.speed = SPEED_10000;
776 pdata->phy.duplex = DUPLEX_FULL;
777 pdata->phy.autoneg = AUTONEG_DISABLE;
778 pdata->phy.pause_autoneg = AUTONEG_DISABLE;
779 if (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_10000) {
780 switch (phy_data->sfp_base) {
781 case XGBE_SFP_BASE_10000_SR:
782 XGBE_SET_SUP(lks, 10000baseSR_Full);
784 case XGBE_SFP_BASE_10000_LR:
785 XGBE_SET_SUP(lks, 10000baseLR_Full);
787 case XGBE_SFP_BASE_10000_LRM:
788 XGBE_SET_SUP(lks, 10000baseLRM_Full);
790 case XGBE_SFP_BASE_10000_ER:
791 XGBE_SET_SUP(lks, 10000baseER_Full);
793 case XGBE_SFP_BASE_10000_CR:
794 XGBE_SET_SUP(lks, 10000baseCR_Full);
802 pdata->phy.speed = SPEED_UNKNOWN;
803 pdata->phy.duplex = DUPLEX_UNKNOWN;
804 pdata->phy.autoneg = AUTONEG_DISABLE;
805 pdata->phy.pause_autoneg = AUTONEG_DISABLE;
809 switch (phy_data->sfp_base) {
810 case XGBE_SFP_BASE_1000_T:
811 case XGBE_SFP_BASE_1000_CX:
812 case XGBE_SFP_BASE_10000_CR:
813 XGBE_SET_SUP(lks, TP);
816 XGBE_SET_SUP(lks, FIBRE);
820 XGBE_LM_COPY(lks, advertising, lks, supported);
823 static bool xgbe_phy_sfp_bit_rate(struct xgbe_sfp_eeprom *sfp_eeprom,
824 enum xgbe_sfp_speed sfp_speed)
826 u8 *sfp_base, min, max;
828 sfp_base = sfp_eeprom->base;
831 case XGBE_SFP_SPEED_1000:
832 min = XGBE_SFP_BASE_BR_1GBE_MIN;
833 max = XGBE_SFP_BASE_BR_1GBE_MAX;
835 case XGBE_SFP_SPEED_10000:
836 min = XGBE_SFP_BASE_BR_10GBE_MIN;
837 max = XGBE_SFP_BASE_BR_10GBE_MAX;
843 return ((sfp_base[XGBE_SFP_BASE_BR] >= min) &&
844 (sfp_base[XGBE_SFP_BASE_BR] <= max));
847 static void xgbe_phy_free_phy_device(struct xgbe_prv_data *pdata)
849 struct xgbe_phy_data *phy_data = pdata->phy_data;
851 if (phy_data->phydev) {
852 phy_detach(phy_data->phydev);
853 phy_device_remove(phy_data->phydev);
854 phy_device_free(phy_data->phydev);
855 phy_data->phydev = NULL;
859 static bool xgbe_phy_finisar_phy_quirks(struct xgbe_prv_data *pdata)
861 __ETHTOOL_DECLARE_LINK_MODE_MASK(supported) = { 0, };
862 struct xgbe_phy_data *phy_data = pdata->phy_data;
863 unsigned int phy_id = phy_data->phydev->phy_id;
865 if (phy_data->port_mode != XGBE_PORT_MODE_SFP)
868 if ((phy_id & 0xfffffff0) != 0x01ff0cc0)
871 /* Enable Base-T AN */
872 phy_write(phy_data->phydev, 0x16, 0x0001);
873 phy_write(phy_data->phydev, 0x00, 0x9140);
874 phy_write(phy_data->phydev, 0x16, 0x0000);
876 /* Enable SGMII at 100Base-T/1000Base-T Full Duplex */
877 phy_write(phy_data->phydev, 0x1b, 0x9084);
878 phy_write(phy_data->phydev, 0x09, 0x0e00);
879 phy_write(phy_data->phydev, 0x00, 0x8140);
880 phy_write(phy_data->phydev, 0x04, 0x0d01);
881 phy_write(phy_data->phydev, 0x00, 0x9140);
883 linkmode_set_bit_array(phy_10_100_features_array,
884 ARRAY_SIZE(phy_10_100_features_array),
886 linkmode_set_bit_array(phy_gbit_features_array,
887 ARRAY_SIZE(phy_gbit_features_array),
890 linkmode_copy(phy_data->phydev->supported, supported);
892 phy_support_asym_pause(phy_data->phydev);
894 netif_dbg(pdata, drv, pdata->netdev,
895 "Finisar PHY quirk in place\n");
900 static bool xgbe_phy_belfuse_phy_quirks(struct xgbe_prv_data *pdata)
902 __ETHTOOL_DECLARE_LINK_MODE_MASK(supported) = { 0, };
903 struct xgbe_phy_data *phy_data = pdata->phy_data;
904 struct xgbe_sfp_eeprom *sfp_eeprom = &phy_data->sfp_eeprom;
905 unsigned int phy_id = phy_data->phydev->phy_id;
908 if (phy_data->port_mode != XGBE_PORT_MODE_SFP)
911 if (memcmp(&sfp_eeprom->base[XGBE_SFP_BASE_VENDOR_NAME],
912 XGBE_BEL_FUSE_VENDOR, XGBE_SFP_BASE_VENDOR_NAME_LEN))
915 /* For Bel-Fuse, use the extra AN flag */
918 if (memcmp(&sfp_eeprom->base[XGBE_SFP_BASE_VENDOR_PN],
919 XGBE_BEL_FUSE_PARTNO, XGBE_SFP_BASE_VENDOR_PN_LEN))
922 if ((phy_id & 0xfffffff0) != 0x03625d10)
925 /* Disable RGMII mode */
926 phy_write(phy_data->phydev, 0x18, 0x7007);
927 reg = phy_read(phy_data->phydev, 0x18);
928 phy_write(phy_data->phydev, 0x18, reg & ~0x0080);
930 /* Enable fiber register bank */
931 phy_write(phy_data->phydev, 0x1c, 0x7c00);
932 reg = phy_read(phy_data->phydev, 0x1c);
935 phy_write(phy_data->phydev, 0x1c, 0x8000 | 0x7c00 | reg | 0x0001);
937 /* Power down SerDes */
938 reg = phy_read(phy_data->phydev, 0x00);
939 phy_write(phy_data->phydev, 0x00, reg | 0x00800);
941 /* Configure SGMII-to-Copper mode */
942 phy_write(phy_data->phydev, 0x1c, 0x7c00);
943 reg = phy_read(phy_data->phydev, 0x1c);
946 phy_write(phy_data->phydev, 0x1c, 0x8000 | 0x7c00 | reg | 0x0004);
948 /* Power up SerDes */
949 reg = phy_read(phy_data->phydev, 0x00);
950 phy_write(phy_data->phydev, 0x00, reg & ~0x00800);
952 /* Enable copper register bank */
953 phy_write(phy_data->phydev, 0x1c, 0x7c00);
954 reg = phy_read(phy_data->phydev, 0x1c);
957 phy_write(phy_data->phydev, 0x1c, 0x8000 | 0x7c00 | reg);
959 /* Power up SerDes */
960 reg = phy_read(phy_data->phydev, 0x00);
961 phy_write(phy_data->phydev, 0x00, reg & ~0x00800);
963 linkmode_set_bit_array(phy_10_100_features_array,
964 ARRAY_SIZE(phy_10_100_features_array),
966 linkmode_set_bit_array(phy_gbit_features_array,
967 ARRAY_SIZE(phy_gbit_features_array),
969 linkmode_copy(phy_data->phydev->supported, supported);
970 phy_support_asym_pause(phy_data->phydev);
972 netif_dbg(pdata, drv, pdata->netdev,
973 "BelFuse PHY quirk in place\n");
978 static void xgbe_phy_external_phy_quirks(struct xgbe_prv_data *pdata)
980 if (xgbe_phy_belfuse_phy_quirks(pdata))
983 if (xgbe_phy_finisar_phy_quirks(pdata))
987 static int xgbe_phy_find_phy_device(struct xgbe_prv_data *pdata)
989 struct ethtool_link_ksettings *lks = &pdata->phy.lks;
990 struct xgbe_phy_data *phy_data = pdata->phy_data;
991 struct phy_device *phydev;
994 /* If we already have a PHY, just return */
995 if (phy_data->phydev)
998 /* Clear the extra AN flag */
1001 /* Check for the use of an external PHY */
1002 if (phy_data->phydev_mode == XGBE_MDIO_MODE_NONE)
1005 /* For SFP, only use an external PHY if available */
1006 if ((phy_data->port_mode == XGBE_PORT_MODE_SFP) &&
1007 !phy_data->sfp_phy_avail)
1010 /* Set the proper MDIO mode for the PHY */
1011 ret = pdata->hw_if.set_ext_mii_mode(pdata, phy_data->mdio_addr,
1012 phy_data->phydev_mode);
1014 netdev_err(pdata->netdev,
1015 "mdio port/clause not compatible (%u/%u)\n",
1016 phy_data->mdio_addr, phy_data->phydev_mode);
1020 /* Create and connect to the PHY device */
1021 phydev = get_phy_device(phy_data->mii, phy_data->mdio_addr,
1022 (phy_data->phydev_mode == XGBE_MDIO_MODE_CL45));
1023 if (IS_ERR(phydev)) {
1024 netdev_err(pdata->netdev, "get_phy_device failed\n");
1027 netif_dbg(pdata, drv, pdata->netdev, "external PHY id is %#010x\n",
1030 /*TODO: If c45, add request_module based on one of the MMD ids? */
1032 ret = phy_device_register(phydev);
1034 netdev_err(pdata->netdev, "phy_device_register failed\n");
1035 phy_device_free(phydev);
1039 ret = phy_attach_direct(pdata->netdev, phydev, phydev->dev_flags,
1040 PHY_INTERFACE_MODE_SGMII);
1042 netdev_err(pdata->netdev, "phy_attach_direct failed\n");
1043 phy_device_remove(phydev);
1044 phy_device_free(phydev);
1047 phy_data->phydev = phydev;
1049 xgbe_phy_external_phy_quirks(pdata);
1051 linkmode_and(phydev->advertising, phydev->advertising,
1052 lks->link_modes.advertising);
1054 phy_start_aneg(phy_data->phydev);
1059 static void xgbe_phy_sfp_external_phy(struct xgbe_prv_data *pdata)
1061 struct xgbe_phy_data *phy_data = pdata->phy_data;
1064 if (!phy_data->sfp_changed)
1067 phy_data->sfp_phy_avail = 0;
1069 if (phy_data->sfp_base != XGBE_SFP_BASE_1000_T)
1072 /* Check access to the PHY by reading CTRL1 */
1073 ret = xgbe_phy_i2c_mii_read(pdata, MII_BMCR);
1077 /* Successfully accessed the PHY */
1078 phy_data->sfp_phy_avail = 1;
1081 static bool xgbe_phy_check_sfp_rx_los(struct xgbe_phy_data *phy_data)
1083 u8 *sfp_extd = phy_data->sfp_eeprom.extd;
1085 if (!(sfp_extd[XGBE_SFP_EXTD_OPT1] & XGBE_SFP_EXTD_OPT1_RX_LOS))
1088 if (phy_data->sfp_gpio_mask & XGBE_GPIO_NO_RX_LOS)
1091 if (phy_data->sfp_gpio_inputs & (1 << phy_data->sfp_gpio_rx_los))
1097 static bool xgbe_phy_check_sfp_tx_fault(struct xgbe_phy_data *phy_data)
1099 u8 *sfp_extd = phy_data->sfp_eeprom.extd;
1101 if (!(sfp_extd[XGBE_SFP_EXTD_OPT1] & XGBE_SFP_EXTD_OPT1_TX_FAULT))
1104 if (phy_data->sfp_gpio_mask & XGBE_GPIO_NO_TX_FAULT)
1107 if (phy_data->sfp_gpio_inputs & (1 << phy_data->sfp_gpio_tx_fault))
1113 static bool xgbe_phy_check_sfp_mod_absent(struct xgbe_phy_data *phy_data)
1115 if (phy_data->sfp_gpio_mask & XGBE_GPIO_NO_MOD_ABSENT)
1118 if (phy_data->sfp_gpio_inputs & (1 << phy_data->sfp_gpio_mod_absent))
1124 static void xgbe_phy_sfp_parse_eeprom(struct xgbe_prv_data *pdata)
1126 struct xgbe_phy_data *phy_data = pdata->phy_data;
1127 struct xgbe_sfp_eeprom *sfp_eeprom = &phy_data->sfp_eeprom;
1130 sfp_base = sfp_eeprom->base;
1132 if (sfp_base[XGBE_SFP_BASE_ID] != XGBE_SFP_ID_SFP)
1135 if (sfp_base[XGBE_SFP_BASE_EXT_ID] != XGBE_SFP_EXT_ID_SFP)
1138 /* Update transceiver signals (eeprom extd/options) */
1139 phy_data->sfp_tx_fault = xgbe_phy_check_sfp_tx_fault(phy_data);
1140 phy_data->sfp_rx_los = xgbe_phy_check_sfp_rx_los(phy_data);
1142 /* Assume ACTIVE cable unless told it is PASSIVE */
1143 if (sfp_base[XGBE_SFP_BASE_CABLE] & XGBE_SFP_BASE_CABLE_PASSIVE) {
1144 phy_data->sfp_cable = XGBE_SFP_CABLE_PASSIVE;
1145 phy_data->sfp_cable_len = sfp_base[XGBE_SFP_BASE_CU_CABLE_LEN];
1147 phy_data->sfp_cable = XGBE_SFP_CABLE_ACTIVE;
1150 /* Determine the type of SFP */
1151 if (sfp_base[XGBE_SFP_BASE_10GBE_CC] & XGBE_SFP_BASE_10GBE_CC_SR)
1152 phy_data->sfp_base = XGBE_SFP_BASE_10000_SR;
1153 else if (sfp_base[XGBE_SFP_BASE_10GBE_CC] & XGBE_SFP_BASE_10GBE_CC_LR)
1154 phy_data->sfp_base = XGBE_SFP_BASE_10000_LR;
1155 else if (sfp_base[XGBE_SFP_BASE_10GBE_CC] & XGBE_SFP_BASE_10GBE_CC_LRM)
1156 phy_data->sfp_base = XGBE_SFP_BASE_10000_LRM;
1157 else if (sfp_base[XGBE_SFP_BASE_10GBE_CC] & XGBE_SFP_BASE_10GBE_CC_ER)
1158 phy_data->sfp_base = XGBE_SFP_BASE_10000_ER;
1159 else if (sfp_base[XGBE_SFP_BASE_1GBE_CC] & XGBE_SFP_BASE_1GBE_CC_SX)
1160 phy_data->sfp_base = XGBE_SFP_BASE_1000_SX;
1161 else if (sfp_base[XGBE_SFP_BASE_1GBE_CC] & XGBE_SFP_BASE_1GBE_CC_LX)
1162 phy_data->sfp_base = XGBE_SFP_BASE_1000_LX;
1163 else if (sfp_base[XGBE_SFP_BASE_1GBE_CC] & XGBE_SFP_BASE_1GBE_CC_CX)
1164 phy_data->sfp_base = XGBE_SFP_BASE_1000_CX;
1165 else if (sfp_base[XGBE_SFP_BASE_1GBE_CC] & XGBE_SFP_BASE_1GBE_CC_T)
1166 phy_data->sfp_base = XGBE_SFP_BASE_1000_T;
1167 else if ((phy_data->sfp_cable == XGBE_SFP_CABLE_PASSIVE) &&
1168 xgbe_phy_sfp_bit_rate(sfp_eeprom, XGBE_SFP_SPEED_10000))
1169 phy_data->sfp_base = XGBE_SFP_BASE_10000_CR;
1171 switch (phy_data->sfp_base) {
1172 case XGBE_SFP_BASE_1000_T:
1173 phy_data->sfp_speed = XGBE_SFP_SPEED_100_1000;
1175 case XGBE_SFP_BASE_1000_SX:
1176 case XGBE_SFP_BASE_1000_LX:
1177 case XGBE_SFP_BASE_1000_CX:
1178 phy_data->sfp_speed = XGBE_SFP_SPEED_1000;
1180 case XGBE_SFP_BASE_10000_SR:
1181 case XGBE_SFP_BASE_10000_LR:
1182 case XGBE_SFP_BASE_10000_LRM:
1183 case XGBE_SFP_BASE_10000_ER:
1184 case XGBE_SFP_BASE_10000_CR:
1185 phy_data->sfp_speed = XGBE_SFP_SPEED_10000;
1192 static void xgbe_phy_sfp_eeprom_info(struct xgbe_prv_data *pdata,
1193 struct xgbe_sfp_eeprom *sfp_eeprom)
1195 struct xgbe_sfp_ascii sfp_ascii;
1196 char *sfp_data = (char *)&sfp_ascii;
1198 netif_dbg(pdata, drv, pdata->netdev, "SFP detected:\n");
1199 memcpy(sfp_data, &sfp_eeprom->base[XGBE_SFP_BASE_VENDOR_NAME],
1200 XGBE_SFP_BASE_VENDOR_NAME_LEN);
1201 sfp_data[XGBE_SFP_BASE_VENDOR_NAME_LEN] = '\0';
1202 netif_dbg(pdata, drv, pdata->netdev, " vendor: %s\n",
1205 memcpy(sfp_data, &sfp_eeprom->base[XGBE_SFP_BASE_VENDOR_PN],
1206 XGBE_SFP_BASE_VENDOR_PN_LEN);
1207 sfp_data[XGBE_SFP_BASE_VENDOR_PN_LEN] = '\0';
1208 netif_dbg(pdata, drv, pdata->netdev, " part number: %s\n",
1211 memcpy(sfp_data, &sfp_eeprom->base[XGBE_SFP_BASE_VENDOR_REV],
1212 XGBE_SFP_BASE_VENDOR_REV_LEN);
1213 sfp_data[XGBE_SFP_BASE_VENDOR_REV_LEN] = '\0';
1214 netif_dbg(pdata, drv, pdata->netdev, " revision level: %s\n",
1217 memcpy(sfp_data, &sfp_eeprom->extd[XGBE_SFP_BASE_VENDOR_SN],
1218 XGBE_SFP_BASE_VENDOR_SN_LEN);
1219 sfp_data[XGBE_SFP_BASE_VENDOR_SN_LEN] = '\0';
1220 netif_dbg(pdata, drv, pdata->netdev, " serial number: %s\n",
1224 static bool xgbe_phy_sfp_verify_eeprom(u8 cc_in, u8 *buf, unsigned int len)
1228 for (cc = 0; len; buf++, len--)
1234 static int xgbe_phy_sfp_read_eeprom(struct xgbe_prv_data *pdata)
1236 struct xgbe_phy_data *phy_data = pdata->phy_data;
1237 struct xgbe_sfp_eeprom sfp_eeprom;
1241 ret = xgbe_phy_sfp_get_mux(pdata);
1243 dev_err_once(pdata->dev, "%s: I2C error setting SFP MUX\n",
1244 netdev_name(pdata->netdev));
1248 /* Read the SFP serial ID eeprom */
1250 ret = xgbe_phy_i2c_read(pdata, XGBE_SFP_SERIAL_ID_ADDRESS,
1251 &eeprom_addr, sizeof(eeprom_addr),
1252 &sfp_eeprom, sizeof(sfp_eeprom));
1254 dev_err_once(pdata->dev, "%s: I2C error reading SFP EEPROM\n",
1255 netdev_name(pdata->netdev));
1259 /* Validate the contents read */
1260 if (!xgbe_phy_sfp_verify_eeprom(sfp_eeprom.base[XGBE_SFP_BASE_CC],
1262 sizeof(sfp_eeprom.base) - 1)) {
1267 if (!xgbe_phy_sfp_verify_eeprom(sfp_eeprom.extd[XGBE_SFP_EXTD_CC],
1269 sizeof(sfp_eeprom.extd) - 1)) {
1274 /* Check for an added or changed SFP */
1275 if (memcmp(&phy_data->sfp_eeprom, &sfp_eeprom, sizeof(sfp_eeprom))) {
1276 phy_data->sfp_changed = 1;
1278 if (netif_msg_drv(pdata))
1279 xgbe_phy_sfp_eeprom_info(pdata, &sfp_eeprom);
1281 memcpy(&phy_data->sfp_eeprom, &sfp_eeprom, sizeof(sfp_eeprom));
1283 xgbe_phy_free_phy_device(pdata);
1285 phy_data->sfp_changed = 0;
1289 xgbe_phy_sfp_put_mux(pdata);
1294 static void xgbe_phy_sfp_signals(struct xgbe_prv_data *pdata)
1296 struct xgbe_phy_data *phy_data = pdata->phy_data;
1297 u8 gpio_reg, gpio_ports[2];
1300 /* Read the input port registers */
1302 ret = xgbe_phy_i2c_read(pdata, phy_data->sfp_gpio_address,
1303 &gpio_reg, sizeof(gpio_reg),
1304 gpio_ports, sizeof(gpio_ports));
1306 dev_err_once(pdata->dev, "%s: I2C error reading SFP GPIOs\n",
1307 netdev_name(pdata->netdev));
1311 phy_data->sfp_gpio_inputs = (gpio_ports[1] << 8) | gpio_ports[0];
1313 phy_data->sfp_mod_absent = xgbe_phy_check_sfp_mod_absent(phy_data);
1316 static void xgbe_phy_sfp_mod_absent(struct xgbe_prv_data *pdata)
1318 struct xgbe_phy_data *phy_data = pdata->phy_data;
1320 xgbe_phy_free_phy_device(pdata);
1322 phy_data->sfp_mod_absent = 1;
1323 phy_data->sfp_phy_avail = 0;
1324 memset(&phy_data->sfp_eeprom, 0, sizeof(phy_data->sfp_eeprom));
1327 static void xgbe_phy_sfp_reset(struct xgbe_phy_data *phy_data)
1329 phy_data->sfp_rx_los = 0;
1330 phy_data->sfp_tx_fault = 0;
1331 phy_data->sfp_mod_absent = 1;
1332 phy_data->sfp_base = XGBE_SFP_BASE_UNKNOWN;
1333 phy_data->sfp_cable = XGBE_SFP_CABLE_UNKNOWN;
1334 phy_data->sfp_speed = XGBE_SFP_SPEED_UNKNOWN;
1337 static void xgbe_phy_sfp_detect(struct xgbe_prv_data *pdata)
1339 struct xgbe_phy_data *phy_data = pdata->phy_data;
1342 /* Reset the SFP signals and info */
1343 xgbe_phy_sfp_reset(phy_data);
1345 ret = xgbe_phy_get_comm_ownership(pdata);
1349 /* Read the SFP signals and check for module presence */
1350 xgbe_phy_sfp_signals(pdata);
1351 if (phy_data->sfp_mod_absent) {
1352 xgbe_phy_sfp_mod_absent(pdata);
1356 ret = xgbe_phy_sfp_read_eeprom(pdata);
1358 /* Treat any error as if there isn't an SFP plugged in */
1359 xgbe_phy_sfp_reset(phy_data);
1360 xgbe_phy_sfp_mod_absent(pdata);
1364 xgbe_phy_sfp_parse_eeprom(pdata);
1366 xgbe_phy_sfp_external_phy(pdata);
1369 xgbe_phy_sfp_phy_settings(pdata);
1371 xgbe_phy_put_comm_ownership(pdata);
1374 static int xgbe_phy_module_eeprom(struct xgbe_prv_data *pdata,
1375 struct ethtool_eeprom *eeprom, u8 *data)
1377 struct xgbe_phy_data *phy_data = pdata->phy_data;
1378 u8 eeprom_addr, eeprom_data[XGBE_SFP_EEPROM_MAX];
1379 struct xgbe_sfp_eeprom *sfp_eeprom;
1380 unsigned int i, j, rem;
1390 if ((eeprom->offset + eeprom->len) > XGBE_SFP_EEPROM_MAX) {
1395 if (phy_data->port_mode != XGBE_PORT_MODE_SFP) {
1400 if (!netif_running(pdata->netdev)) {
1405 if (phy_data->sfp_mod_absent) {
1410 ret = xgbe_phy_get_comm_ownership(pdata);
1416 ret = xgbe_phy_sfp_get_mux(pdata);
1418 netdev_err(pdata->netdev, "I2C error setting SFP MUX\n");
1423 /* Read the SFP serial ID eeprom */
1425 ret = xgbe_phy_i2c_read(pdata, XGBE_SFP_SERIAL_ID_ADDRESS,
1426 &eeprom_addr, sizeof(eeprom_addr),
1427 eeprom_data, XGBE_SFP_EEPROM_BASE_LEN);
1429 netdev_err(pdata->netdev,
1430 "I2C error reading SFP EEPROM\n");
1435 sfp_eeprom = (struct xgbe_sfp_eeprom *)eeprom_data;
1437 if (XGBE_SFP_DIAGS_SUPPORTED(sfp_eeprom)) {
1438 /* Read the SFP diagnostic eeprom */
1440 ret = xgbe_phy_i2c_read(pdata, XGBE_SFP_DIAG_INFO_ADDRESS,
1441 &eeprom_addr, sizeof(eeprom_addr),
1442 eeprom_data + XGBE_SFP_EEPROM_BASE_LEN,
1443 XGBE_SFP_EEPROM_DIAG_LEN);
1445 netdev_err(pdata->netdev,
1446 "I2C error reading SFP DIAGS\n");
1452 for (i = 0, j = eeprom->offset; i < eeprom->len; i++, j++) {
1453 if ((j >= XGBE_SFP_EEPROM_BASE_LEN) &&
1454 !XGBE_SFP_DIAGS_SUPPORTED(sfp_eeprom))
1457 data[i] = eeprom_data[j];
1462 xgbe_phy_sfp_put_mux(pdata);
1465 xgbe_phy_put_comm_ownership(pdata);
1473 static int xgbe_phy_module_info(struct xgbe_prv_data *pdata,
1474 struct ethtool_modinfo *modinfo)
1476 struct xgbe_phy_data *phy_data = pdata->phy_data;
1478 if (phy_data->port_mode != XGBE_PORT_MODE_SFP)
1481 if (!netif_running(pdata->netdev))
1484 if (phy_data->sfp_mod_absent)
1487 if (XGBE_SFP_DIAGS_SUPPORTED(&phy_data->sfp_eeprom)) {
1488 modinfo->type = ETH_MODULE_SFF_8472;
1489 modinfo->eeprom_len = ETH_MODULE_SFF_8472_LEN;
1491 modinfo->type = ETH_MODULE_SFF_8079;
1492 modinfo->eeprom_len = ETH_MODULE_SFF_8079_LEN;
1498 static void xgbe_phy_phydev_flowctrl(struct xgbe_prv_data *pdata)
1500 struct ethtool_link_ksettings *lks = &pdata->phy.lks;
1501 struct xgbe_phy_data *phy_data = pdata->phy_data;
1502 u16 lcl_adv = 0, rmt_adv = 0;
1505 pdata->phy.tx_pause = 0;
1506 pdata->phy.rx_pause = 0;
1508 if (!phy_data->phydev)
1511 lcl_adv = linkmode_adv_to_lcl_adv_t(phy_data->phydev->advertising);
1513 if (phy_data->phydev->pause) {
1514 XGBE_SET_LP_ADV(lks, Pause);
1515 rmt_adv |= LPA_PAUSE_CAP;
1517 if (phy_data->phydev->asym_pause) {
1518 XGBE_SET_LP_ADV(lks, Asym_Pause);
1519 rmt_adv |= LPA_PAUSE_ASYM;
1522 fc = mii_resolve_flowctrl_fdx(lcl_adv, rmt_adv);
1523 if (fc & FLOW_CTRL_TX)
1524 pdata->phy.tx_pause = 1;
1525 if (fc & FLOW_CTRL_RX)
1526 pdata->phy.rx_pause = 1;
1529 static enum xgbe_mode xgbe_phy_an37_sgmii_outcome(struct xgbe_prv_data *pdata)
1531 struct ethtool_link_ksettings *lks = &pdata->phy.lks;
1532 enum xgbe_mode mode;
1534 XGBE_SET_LP_ADV(lks, Autoneg);
1535 XGBE_SET_LP_ADV(lks, TP);
1537 /* Use external PHY to determine flow control */
1538 if (pdata->phy.pause_autoneg)
1539 xgbe_phy_phydev_flowctrl(pdata);
1541 switch (pdata->an_status & XGBE_SGMII_AN_LINK_SPEED) {
1542 case XGBE_SGMII_AN_LINK_SPEED_100:
1543 if (pdata->an_status & XGBE_SGMII_AN_LINK_DUPLEX) {
1544 XGBE_SET_LP_ADV(lks, 100baseT_Full);
1545 mode = XGBE_MODE_SGMII_100;
1547 /* Half-duplex not supported */
1548 XGBE_SET_LP_ADV(lks, 100baseT_Half);
1549 mode = XGBE_MODE_UNKNOWN;
1552 case XGBE_SGMII_AN_LINK_SPEED_1000:
1553 if (pdata->an_status & XGBE_SGMII_AN_LINK_DUPLEX) {
1554 XGBE_SET_LP_ADV(lks, 1000baseT_Full);
1555 mode = XGBE_MODE_SGMII_1000;
1557 /* Half-duplex not supported */
1558 XGBE_SET_LP_ADV(lks, 1000baseT_Half);
1559 mode = XGBE_MODE_UNKNOWN;
1563 mode = XGBE_MODE_UNKNOWN;
1569 static enum xgbe_mode xgbe_phy_an37_outcome(struct xgbe_prv_data *pdata)
1571 struct ethtool_link_ksettings *lks = &pdata->phy.lks;
1572 enum xgbe_mode mode;
1573 unsigned int ad_reg, lp_reg;
1575 XGBE_SET_LP_ADV(lks, Autoneg);
1576 XGBE_SET_LP_ADV(lks, FIBRE);
1578 /* Compare Advertisement and Link Partner register */
1579 ad_reg = XMDIO_READ(pdata, MDIO_MMD_VEND2, MDIO_VEND2_AN_ADVERTISE);
1580 lp_reg = XMDIO_READ(pdata, MDIO_MMD_VEND2, MDIO_VEND2_AN_LP_ABILITY);
1582 XGBE_SET_LP_ADV(lks, Pause);
1584 XGBE_SET_LP_ADV(lks, Asym_Pause);
1586 if (pdata->phy.pause_autoneg) {
1587 /* Set flow control based on auto-negotiation result */
1588 pdata->phy.tx_pause = 0;
1589 pdata->phy.rx_pause = 0;
1591 if (ad_reg & lp_reg & 0x100) {
1592 pdata->phy.tx_pause = 1;
1593 pdata->phy.rx_pause = 1;
1594 } else if (ad_reg & lp_reg & 0x80) {
1596 pdata->phy.rx_pause = 1;
1597 else if (lp_reg & 0x100)
1598 pdata->phy.tx_pause = 1;
1603 XGBE_SET_LP_ADV(lks, 1000baseX_Full);
1605 /* Half duplex is not supported */
1607 mode = (ad_reg & 0x20) ? XGBE_MODE_X : XGBE_MODE_UNKNOWN;
1612 static enum xgbe_mode xgbe_phy_an73_redrv_outcome(struct xgbe_prv_data *pdata)
1614 struct ethtool_link_ksettings *lks = &pdata->phy.lks;
1615 struct xgbe_phy_data *phy_data = pdata->phy_data;
1616 enum xgbe_mode mode;
1617 unsigned int ad_reg, lp_reg;
1619 XGBE_SET_LP_ADV(lks, Autoneg);
1620 XGBE_SET_LP_ADV(lks, Backplane);
1622 /* Use external PHY to determine flow control */
1623 if (pdata->phy.pause_autoneg)
1624 xgbe_phy_phydev_flowctrl(pdata);
1626 /* Compare Advertisement and Link Partner register 2 */
1627 ad_reg = XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_ADVERTISE + 1);
1628 lp_reg = XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_LPA + 1);
1630 XGBE_SET_LP_ADV(lks, 10000baseKR_Full);
1632 XGBE_SET_LP_ADV(lks, 1000baseKX_Full);
1635 if (ad_reg & 0x80) {
1636 switch (phy_data->port_mode) {
1637 case XGBE_PORT_MODE_BACKPLANE:
1638 case XGBE_PORT_MODE_BACKPLANE_NO_AUTONEG:
1639 mode = XGBE_MODE_KR;
1642 mode = XGBE_MODE_SFI;
1645 } else if (ad_reg & 0x20) {
1646 switch (phy_data->port_mode) {
1647 case XGBE_PORT_MODE_BACKPLANE:
1648 case XGBE_PORT_MODE_BACKPLANE_NO_AUTONEG:
1649 mode = XGBE_MODE_KX_1000;
1651 case XGBE_PORT_MODE_1000BASE_X:
1654 case XGBE_PORT_MODE_SFP:
1655 switch (phy_data->sfp_base) {
1656 case XGBE_SFP_BASE_1000_T:
1657 if (phy_data->phydev &&
1658 (phy_data->phydev->speed == SPEED_100))
1659 mode = XGBE_MODE_SGMII_100;
1661 mode = XGBE_MODE_SGMII_1000;
1663 case XGBE_SFP_BASE_1000_SX:
1664 case XGBE_SFP_BASE_1000_LX:
1665 case XGBE_SFP_BASE_1000_CX:
1672 if (phy_data->phydev &&
1673 (phy_data->phydev->speed == SPEED_100))
1674 mode = XGBE_MODE_SGMII_100;
1676 mode = XGBE_MODE_SGMII_1000;
1680 mode = XGBE_MODE_UNKNOWN;
1683 /* Compare Advertisement and Link Partner register 3 */
1684 ad_reg = XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_ADVERTISE + 2);
1685 lp_reg = XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_LPA + 2);
1686 if (lp_reg & 0xc000)
1687 XGBE_SET_LP_ADV(lks, 10000baseR_FEC);
1692 static enum xgbe_mode xgbe_phy_an73_outcome(struct xgbe_prv_data *pdata)
1694 struct ethtool_link_ksettings *lks = &pdata->phy.lks;
1695 enum xgbe_mode mode;
1696 unsigned int ad_reg, lp_reg;
1698 XGBE_SET_LP_ADV(lks, Autoneg);
1699 XGBE_SET_LP_ADV(lks, Backplane);
1701 /* Compare Advertisement and Link Partner register 1 */
1702 ad_reg = XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_ADVERTISE);
1703 lp_reg = XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_LPA);
1705 XGBE_SET_LP_ADV(lks, Pause);
1707 XGBE_SET_LP_ADV(lks, Asym_Pause);
1709 if (pdata->phy.pause_autoneg) {
1710 /* Set flow control based on auto-negotiation result */
1711 pdata->phy.tx_pause = 0;
1712 pdata->phy.rx_pause = 0;
1714 if (ad_reg & lp_reg & 0x400) {
1715 pdata->phy.tx_pause = 1;
1716 pdata->phy.rx_pause = 1;
1717 } else if (ad_reg & lp_reg & 0x800) {
1719 pdata->phy.rx_pause = 1;
1720 else if (lp_reg & 0x400)
1721 pdata->phy.tx_pause = 1;
1725 /* Compare Advertisement and Link Partner register 2 */
1726 ad_reg = XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_ADVERTISE + 1);
1727 lp_reg = XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_LPA + 1);
1729 XGBE_SET_LP_ADV(lks, 10000baseKR_Full);
1731 XGBE_SET_LP_ADV(lks, 1000baseKX_Full);
1735 mode = XGBE_MODE_KR;
1736 else if (ad_reg & 0x20)
1737 mode = XGBE_MODE_KX_1000;
1739 mode = XGBE_MODE_UNKNOWN;
1741 /* Compare Advertisement and Link Partner register 3 */
1742 ad_reg = XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_ADVERTISE + 2);
1743 lp_reg = XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_LPA + 2);
1744 if (lp_reg & 0xc000)
1745 XGBE_SET_LP_ADV(lks, 10000baseR_FEC);
1750 static enum xgbe_mode xgbe_phy_an_outcome(struct xgbe_prv_data *pdata)
1752 switch (pdata->an_mode) {
1753 case XGBE_AN_MODE_CL73:
1754 return xgbe_phy_an73_outcome(pdata);
1755 case XGBE_AN_MODE_CL73_REDRV:
1756 return xgbe_phy_an73_redrv_outcome(pdata);
1757 case XGBE_AN_MODE_CL37:
1758 return xgbe_phy_an37_outcome(pdata);
1759 case XGBE_AN_MODE_CL37_SGMII:
1760 return xgbe_phy_an37_sgmii_outcome(pdata);
1762 return XGBE_MODE_UNKNOWN;
1766 static void xgbe_phy_an_advertising(struct xgbe_prv_data *pdata,
1767 struct ethtool_link_ksettings *dlks)
1769 struct ethtool_link_ksettings *slks = &pdata->phy.lks;
1770 struct xgbe_phy_data *phy_data = pdata->phy_data;
1772 XGBE_LM_COPY(dlks, advertising, slks, advertising);
1774 /* Without a re-driver, just return current advertising */
1775 if (!phy_data->redrv)
1778 /* With the KR re-driver we need to advertise a single speed */
1779 XGBE_CLR_ADV(dlks, 1000baseKX_Full);
1780 XGBE_CLR_ADV(dlks, 10000baseKR_Full);
1782 /* Advertise FEC support is present */
1783 if (pdata->fec_ability & MDIO_PMA_10GBR_FECABLE_ABLE)
1784 XGBE_SET_ADV(dlks, 10000baseR_FEC);
1786 switch (phy_data->port_mode) {
1787 case XGBE_PORT_MODE_BACKPLANE:
1788 case XGBE_PORT_MODE_BACKPLANE_NO_AUTONEG:
1789 XGBE_SET_ADV(dlks, 10000baseKR_Full);
1791 case XGBE_PORT_MODE_BACKPLANE_2500:
1792 XGBE_SET_ADV(dlks, 1000baseKX_Full);
1794 case XGBE_PORT_MODE_1000BASE_T:
1795 case XGBE_PORT_MODE_1000BASE_X:
1796 case XGBE_PORT_MODE_NBASE_T:
1797 XGBE_SET_ADV(dlks, 1000baseKX_Full);
1799 case XGBE_PORT_MODE_10GBASE_T:
1800 if (phy_data->phydev &&
1801 (phy_data->phydev->speed == SPEED_10000))
1802 XGBE_SET_ADV(dlks, 10000baseKR_Full);
1804 XGBE_SET_ADV(dlks, 1000baseKX_Full);
1806 case XGBE_PORT_MODE_10GBASE_R:
1807 XGBE_SET_ADV(dlks, 10000baseKR_Full);
1809 case XGBE_PORT_MODE_SFP:
1810 switch (phy_data->sfp_base) {
1811 case XGBE_SFP_BASE_1000_T:
1812 case XGBE_SFP_BASE_1000_SX:
1813 case XGBE_SFP_BASE_1000_LX:
1814 case XGBE_SFP_BASE_1000_CX:
1815 XGBE_SET_ADV(dlks, 1000baseKX_Full);
1818 XGBE_SET_ADV(dlks, 10000baseKR_Full);
1823 XGBE_SET_ADV(dlks, 10000baseKR_Full);
1828 static int xgbe_phy_an_config(struct xgbe_prv_data *pdata)
1830 struct ethtool_link_ksettings *lks = &pdata->phy.lks;
1831 struct xgbe_phy_data *phy_data = pdata->phy_data;
1834 ret = xgbe_phy_find_phy_device(pdata);
1838 if (!phy_data->phydev)
1841 phy_data->phydev->autoneg = pdata->phy.autoneg;
1842 linkmode_and(phy_data->phydev->advertising,
1843 phy_data->phydev->supported,
1844 lks->link_modes.advertising);
1846 if (pdata->phy.autoneg != AUTONEG_ENABLE) {
1847 phy_data->phydev->speed = pdata->phy.speed;
1848 phy_data->phydev->duplex = pdata->phy.duplex;
1851 ret = phy_start_aneg(phy_data->phydev);
1856 static enum xgbe_an_mode xgbe_phy_an_sfp_mode(struct xgbe_phy_data *phy_data)
1858 switch (phy_data->sfp_base) {
1859 case XGBE_SFP_BASE_1000_T:
1860 return XGBE_AN_MODE_CL37_SGMII;
1861 case XGBE_SFP_BASE_1000_SX:
1862 case XGBE_SFP_BASE_1000_LX:
1863 case XGBE_SFP_BASE_1000_CX:
1864 return XGBE_AN_MODE_CL37;
1866 return XGBE_AN_MODE_NONE;
1870 static enum xgbe_an_mode xgbe_phy_an_mode(struct xgbe_prv_data *pdata)
1872 struct xgbe_phy_data *phy_data = pdata->phy_data;
1874 /* A KR re-driver will always require CL73 AN */
1875 if (phy_data->redrv)
1876 return XGBE_AN_MODE_CL73_REDRV;
1878 switch (phy_data->port_mode) {
1879 case XGBE_PORT_MODE_BACKPLANE:
1880 return XGBE_AN_MODE_CL73;
1881 case XGBE_PORT_MODE_BACKPLANE_NO_AUTONEG:
1882 case XGBE_PORT_MODE_BACKPLANE_2500:
1883 return XGBE_AN_MODE_NONE;
1884 case XGBE_PORT_MODE_1000BASE_T:
1885 return XGBE_AN_MODE_CL37_SGMII;
1886 case XGBE_PORT_MODE_1000BASE_X:
1887 return XGBE_AN_MODE_CL37;
1888 case XGBE_PORT_MODE_NBASE_T:
1889 return XGBE_AN_MODE_CL37_SGMII;
1890 case XGBE_PORT_MODE_10GBASE_T:
1891 return XGBE_AN_MODE_CL73;
1892 case XGBE_PORT_MODE_10GBASE_R:
1893 return XGBE_AN_MODE_NONE;
1894 case XGBE_PORT_MODE_SFP:
1895 return xgbe_phy_an_sfp_mode(phy_data);
1897 return XGBE_AN_MODE_NONE;
1901 static int xgbe_phy_set_redrv_mode_mdio(struct xgbe_prv_data *pdata,
1902 enum xgbe_phy_redrv_mode mode)
1904 struct xgbe_phy_data *phy_data = pdata->phy_data;
1905 u16 redrv_reg, redrv_val;
1907 redrv_reg = XGBE_PHY_REDRV_MODE_REG + (phy_data->redrv_lane * 0x1000);
1908 redrv_val = (u16)mode;
1910 return pdata->hw_if.write_ext_mii_regs(pdata, phy_data->redrv_addr,
1911 redrv_reg, redrv_val);
1914 static int xgbe_phy_set_redrv_mode_i2c(struct xgbe_prv_data *pdata,
1915 enum xgbe_phy_redrv_mode mode)
1917 struct xgbe_phy_data *phy_data = pdata->phy_data;
1918 unsigned int redrv_reg;
1921 /* Calculate the register to write */
1922 redrv_reg = XGBE_PHY_REDRV_MODE_REG + (phy_data->redrv_lane * 0x1000);
1924 ret = xgbe_phy_redrv_write(pdata, redrv_reg, mode);
1929 static void xgbe_phy_set_redrv_mode(struct xgbe_prv_data *pdata)
1931 struct xgbe_phy_data *phy_data = pdata->phy_data;
1932 enum xgbe_phy_redrv_mode mode;
1935 if (!phy_data->redrv)
1938 mode = XGBE_PHY_REDRV_MODE_CX;
1939 if ((phy_data->port_mode == XGBE_PORT_MODE_SFP) &&
1940 (phy_data->sfp_base != XGBE_SFP_BASE_1000_CX) &&
1941 (phy_data->sfp_base != XGBE_SFP_BASE_10000_CR))
1942 mode = XGBE_PHY_REDRV_MODE_SR;
1944 ret = xgbe_phy_get_comm_ownership(pdata);
1948 if (phy_data->redrv_if)
1949 xgbe_phy_set_redrv_mode_i2c(pdata, mode);
1951 xgbe_phy_set_redrv_mode_mdio(pdata, mode);
1953 xgbe_phy_put_comm_ownership(pdata);
1956 static void xgbe_phy_perform_ratechange(struct xgbe_prv_data *pdata,
1957 unsigned int cmd, unsigned int sub_cmd)
1959 unsigned int s0 = 0;
1962 /* Log if a previous command did not complete */
1963 if (XP_IOREAD_BITS(pdata, XP_DRIVER_INT_RO, STATUS))
1964 netif_dbg(pdata, link, pdata->netdev,
1965 "firmware mailbox not ready for command\n");
1967 /* Construct the command */
1968 XP_SET_BITS(s0, XP_DRIVER_SCRATCH_0, COMMAND, cmd);
1969 XP_SET_BITS(s0, XP_DRIVER_SCRATCH_0, SUB_COMMAND, sub_cmd);
1971 /* Issue the command */
1972 XP_IOWRITE(pdata, XP_DRIVER_SCRATCH_0, s0);
1973 XP_IOWRITE(pdata, XP_DRIVER_SCRATCH_1, 0);
1974 XP_IOWRITE_BITS(pdata, XP_DRIVER_INT_REQ, REQUEST, 1);
1976 /* Wait for command to complete */
1977 wait = XGBE_RATECHANGE_COUNT;
1979 if (!XP_IOREAD_BITS(pdata, XP_DRIVER_INT_RO, STATUS))
1982 usleep_range(1000, 2000);
1985 netif_dbg(pdata, link, pdata->netdev,
1986 "firmware mailbox command did not complete\n");
1989 static void xgbe_phy_rrc(struct xgbe_prv_data *pdata)
1991 /* Receiver Reset Cycle */
1992 xgbe_phy_perform_ratechange(pdata, 5, 0);
1994 netif_dbg(pdata, link, pdata->netdev, "receiver reset complete\n");
1997 static void xgbe_phy_power_off(struct xgbe_prv_data *pdata)
1999 struct xgbe_phy_data *phy_data = pdata->phy_data;
2002 xgbe_phy_perform_ratechange(pdata, 0, 0);
2004 phy_data->cur_mode = XGBE_MODE_UNKNOWN;
2006 netif_dbg(pdata, link, pdata->netdev, "phy powered off\n");
2009 static void xgbe_phy_sfi_mode(struct xgbe_prv_data *pdata)
2011 struct xgbe_phy_data *phy_data = pdata->phy_data;
2013 xgbe_phy_set_redrv_mode(pdata);
2016 if (phy_data->sfp_cable != XGBE_SFP_CABLE_PASSIVE) {
2017 xgbe_phy_perform_ratechange(pdata, 3, 0);
2019 if (phy_data->sfp_cable_len <= 1)
2020 xgbe_phy_perform_ratechange(pdata, 3, 1);
2021 else if (phy_data->sfp_cable_len <= 3)
2022 xgbe_phy_perform_ratechange(pdata, 3, 2);
2024 xgbe_phy_perform_ratechange(pdata, 3, 3);
2027 phy_data->cur_mode = XGBE_MODE_SFI;
2029 netif_dbg(pdata, link, pdata->netdev, "10GbE SFI mode set\n");
2032 static void xgbe_phy_x_mode(struct xgbe_prv_data *pdata)
2034 struct xgbe_phy_data *phy_data = pdata->phy_data;
2036 xgbe_phy_set_redrv_mode(pdata);
2039 xgbe_phy_perform_ratechange(pdata, 1, 3);
2041 phy_data->cur_mode = XGBE_MODE_X;
2043 netif_dbg(pdata, link, pdata->netdev, "1GbE X mode set\n");
2046 static void xgbe_phy_sgmii_1000_mode(struct xgbe_prv_data *pdata)
2048 struct xgbe_phy_data *phy_data = pdata->phy_data;
2050 xgbe_phy_set_redrv_mode(pdata);
2053 xgbe_phy_perform_ratechange(pdata, 1, 2);
2055 phy_data->cur_mode = XGBE_MODE_SGMII_1000;
2057 netif_dbg(pdata, link, pdata->netdev, "1GbE SGMII mode set\n");
2060 static void xgbe_phy_sgmii_100_mode(struct xgbe_prv_data *pdata)
2062 struct xgbe_phy_data *phy_data = pdata->phy_data;
2064 xgbe_phy_set_redrv_mode(pdata);
2067 xgbe_phy_perform_ratechange(pdata, 1, 1);
2069 phy_data->cur_mode = XGBE_MODE_SGMII_100;
2071 netif_dbg(pdata, link, pdata->netdev, "100MbE SGMII mode set\n");
2074 static void xgbe_phy_kr_mode(struct xgbe_prv_data *pdata)
2076 struct xgbe_phy_data *phy_data = pdata->phy_data;
2078 xgbe_phy_set_redrv_mode(pdata);
2081 xgbe_phy_perform_ratechange(pdata, 4, 0);
2083 phy_data->cur_mode = XGBE_MODE_KR;
2085 netif_dbg(pdata, link, pdata->netdev, "10GbE KR mode set\n");
2088 static void xgbe_phy_kx_2500_mode(struct xgbe_prv_data *pdata)
2090 struct xgbe_phy_data *phy_data = pdata->phy_data;
2092 xgbe_phy_set_redrv_mode(pdata);
2095 xgbe_phy_perform_ratechange(pdata, 2, 0);
2097 phy_data->cur_mode = XGBE_MODE_KX_2500;
2099 netif_dbg(pdata, link, pdata->netdev, "2.5GbE KX mode set\n");
2102 static void xgbe_phy_kx_1000_mode(struct xgbe_prv_data *pdata)
2104 struct xgbe_phy_data *phy_data = pdata->phy_data;
2106 xgbe_phy_set_redrv_mode(pdata);
2109 xgbe_phy_perform_ratechange(pdata, 1, 3);
2111 phy_data->cur_mode = XGBE_MODE_KX_1000;
2113 netif_dbg(pdata, link, pdata->netdev, "1GbE KX mode set\n");
2116 static enum xgbe_mode xgbe_phy_cur_mode(struct xgbe_prv_data *pdata)
2118 struct xgbe_phy_data *phy_data = pdata->phy_data;
2120 return phy_data->cur_mode;
2123 static enum xgbe_mode xgbe_phy_switch_baset_mode(struct xgbe_prv_data *pdata)
2125 struct xgbe_phy_data *phy_data = pdata->phy_data;
2127 /* No switching if not 10GBase-T */
2128 if (phy_data->port_mode != XGBE_PORT_MODE_10GBASE_T)
2129 return xgbe_phy_cur_mode(pdata);
2131 switch (xgbe_phy_cur_mode(pdata)) {
2132 case XGBE_MODE_SGMII_100:
2133 case XGBE_MODE_SGMII_1000:
2134 return XGBE_MODE_KR;
2137 return XGBE_MODE_SGMII_1000;
2141 static enum xgbe_mode xgbe_phy_switch_bp_2500_mode(struct xgbe_prv_data *pdata)
2143 return XGBE_MODE_KX_2500;
2146 static enum xgbe_mode xgbe_phy_switch_bp_mode(struct xgbe_prv_data *pdata)
2148 /* If we are in KR switch to KX, and vice-versa */
2149 switch (xgbe_phy_cur_mode(pdata)) {
2150 case XGBE_MODE_KX_1000:
2151 return XGBE_MODE_KR;
2154 return XGBE_MODE_KX_1000;
2158 static enum xgbe_mode xgbe_phy_switch_mode(struct xgbe_prv_data *pdata)
2160 struct xgbe_phy_data *phy_data = pdata->phy_data;
2162 switch (phy_data->port_mode) {
2163 case XGBE_PORT_MODE_BACKPLANE:
2164 case XGBE_PORT_MODE_BACKPLANE_NO_AUTONEG:
2165 return xgbe_phy_switch_bp_mode(pdata);
2166 case XGBE_PORT_MODE_BACKPLANE_2500:
2167 return xgbe_phy_switch_bp_2500_mode(pdata);
2168 case XGBE_PORT_MODE_1000BASE_T:
2169 case XGBE_PORT_MODE_NBASE_T:
2170 case XGBE_PORT_MODE_10GBASE_T:
2171 return xgbe_phy_switch_baset_mode(pdata);
2172 case XGBE_PORT_MODE_1000BASE_X:
2173 case XGBE_PORT_MODE_10GBASE_R:
2174 case XGBE_PORT_MODE_SFP:
2175 /* No switching, so just return current mode */
2176 return xgbe_phy_cur_mode(pdata);
2178 return XGBE_MODE_UNKNOWN;
2182 static enum xgbe_mode xgbe_phy_get_basex_mode(struct xgbe_phy_data *phy_data,
2189 return XGBE_MODE_KR;
2191 return XGBE_MODE_UNKNOWN;
2195 static enum xgbe_mode xgbe_phy_get_baset_mode(struct xgbe_phy_data *phy_data,
2200 return XGBE_MODE_SGMII_100;
2202 return XGBE_MODE_SGMII_1000;
2204 return XGBE_MODE_KX_2500;
2206 return XGBE_MODE_KR;
2208 return XGBE_MODE_UNKNOWN;
2212 static enum xgbe_mode xgbe_phy_get_sfp_mode(struct xgbe_phy_data *phy_data,
2217 return XGBE_MODE_SGMII_100;
2219 if (phy_data->sfp_base == XGBE_SFP_BASE_1000_T)
2220 return XGBE_MODE_SGMII_1000;
2225 return XGBE_MODE_SFI;
2227 return XGBE_MODE_UNKNOWN;
2231 static enum xgbe_mode xgbe_phy_get_bp_2500_mode(int speed)
2235 return XGBE_MODE_KX_2500;
2237 return XGBE_MODE_UNKNOWN;
2241 static enum xgbe_mode xgbe_phy_get_bp_mode(int speed)
2245 return XGBE_MODE_KX_1000;
2247 return XGBE_MODE_KR;
2249 return XGBE_MODE_UNKNOWN;
2253 static enum xgbe_mode xgbe_phy_get_mode(struct xgbe_prv_data *pdata,
2256 struct xgbe_phy_data *phy_data = pdata->phy_data;
2258 switch (phy_data->port_mode) {
2259 case XGBE_PORT_MODE_BACKPLANE:
2260 case XGBE_PORT_MODE_BACKPLANE_NO_AUTONEG:
2261 return xgbe_phy_get_bp_mode(speed);
2262 case XGBE_PORT_MODE_BACKPLANE_2500:
2263 return xgbe_phy_get_bp_2500_mode(speed);
2264 case XGBE_PORT_MODE_1000BASE_T:
2265 case XGBE_PORT_MODE_NBASE_T:
2266 case XGBE_PORT_MODE_10GBASE_T:
2267 return xgbe_phy_get_baset_mode(phy_data, speed);
2268 case XGBE_PORT_MODE_1000BASE_X:
2269 case XGBE_PORT_MODE_10GBASE_R:
2270 return xgbe_phy_get_basex_mode(phy_data, speed);
2271 case XGBE_PORT_MODE_SFP:
2272 return xgbe_phy_get_sfp_mode(phy_data, speed);
2274 return XGBE_MODE_UNKNOWN;
2278 static void xgbe_phy_set_mode(struct xgbe_prv_data *pdata, enum xgbe_mode mode)
2281 case XGBE_MODE_KX_1000:
2282 xgbe_phy_kx_1000_mode(pdata);
2284 case XGBE_MODE_KX_2500:
2285 xgbe_phy_kx_2500_mode(pdata);
2288 xgbe_phy_kr_mode(pdata);
2290 case XGBE_MODE_SGMII_100:
2291 xgbe_phy_sgmii_100_mode(pdata);
2293 case XGBE_MODE_SGMII_1000:
2294 xgbe_phy_sgmii_1000_mode(pdata);
2297 xgbe_phy_x_mode(pdata);
2300 xgbe_phy_sfi_mode(pdata);
2307 static bool xgbe_phy_check_mode(struct xgbe_prv_data *pdata,
2308 enum xgbe_mode mode, bool advert)
2310 if (pdata->phy.autoneg == AUTONEG_ENABLE) {
2313 enum xgbe_mode cur_mode;
2315 cur_mode = xgbe_phy_get_mode(pdata, pdata->phy.speed);
2316 if (cur_mode == mode)
2323 static bool xgbe_phy_use_basex_mode(struct xgbe_prv_data *pdata,
2324 enum xgbe_mode mode)
2326 struct ethtool_link_ksettings *lks = &pdata->phy.lks;
2330 return xgbe_phy_check_mode(pdata, mode,
2331 XGBE_ADV(lks, 1000baseX_Full));
2333 return xgbe_phy_check_mode(pdata, mode,
2334 XGBE_ADV(lks, 10000baseKR_Full));
2340 static bool xgbe_phy_use_baset_mode(struct xgbe_prv_data *pdata,
2341 enum xgbe_mode mode)
2343 struct ethtool_link_ksettings *lks = &pdata->phy.lks;
2346 case XGBE_MODE_SGMII_100:
2347 return xgbe_phy_check_mode(pdata, mode,
2348 XGBE_ADV(lks, 100baseT_Full));
2349 case XGBE_MODE_SGMII_1000:
2350 return xgbe_phy_check_mode(pdata, mode,
2351 XGBE_ADV(lks, 1000baseT_Full));
2352 case XGBE_MODE_KX_2500:
2353 return xgbe_phy_check_mode(pdata, mode,
2354 XGBE_ADV(lks, 2500baseT_Full));
2356 return xgbe_phy_check_mode(pdata, mode,
2357 XGBE_ADV(lks, 10000baseT_Full));
2363 static bool xgbe_phy_use_sfp_mode(struct xgbe_prv_data *pdata,
2364 enum xgbe_mode mode)
2366 struct ethtool_link_ksettings *lks = &pdata->phy.lks;
2367 struct xgbe_phy_data *phy_data = pdata->phy_data;
2371 if (phy_data->sfp_base == XGBE_SFP_BASE_1000_T)
2373 return xgbe_phy_check_mode(pdata, mode,
2374 XGBE_ADV(lks, 1000baseX_Full));
2375 case XGBE_MODE_SGMII_100:
2376 if (phy_data->sfp_base != XGBE_SFP_BASE_1000_T)
2378 return xgbe_phy_check_mode(pdata, mode,
2379 XGBE_ADV(lks, 100baseT_Full));
2380 case XGBE_MODE_SGMII_1000:
2381 if (phy_data->sfp_base != XGBE_SFP_BASE_1000_T)
2383 return xgbe_phy_check_mode(pdata, mode,
2384 XGBE_ADV(lks, 1000baseT_Full));
2386 if (phy_data->sfp_mod_absent)
2388 return xgbe_phy_check_mode(pdata, mode,
2389 XGBE_ADV(lks, 10000baseSR_Full) ||
2390 XGBE_ADV(lks, 10000baseLR_Full) ||
2391 XGBE_ADV(lks, 10000baseLRM_Full) ||
2392 XGBE_ADV(lks, 10000baseER_Full) ||
2393 XGBE_ADV(lks, 10000baseCR_Full));
2399 static bool xgbe_phy_use_bp_2500_mode(struct xgbe_prv_data *pdata,
2400 enum xgbe_mode mode)
2402 struct ethtool_link_ksettings *lks = &pdata->phy.lks;
2405 case XGBE_MODE_KX_2500:
2406 return xgbe_phy_check_mode(pdata, mode,
2407 XGBE_ADV(lks, 2500baseX_Full));
2413 static bool xgbe_phy_use_bp_mode(struct xgbe_prv_data *pdata,
2414 enum xgbe_mode mode)
2416 struct ethtool_link_ksettings *lks = &pdata->phy.lks;
2419 case XGBE_MODE_KX_1000:
2420 return xgbe_phy_check_mode(pdata, mode,
2421 XGBE_ADV(lks, 1000baseKX_Full));
2423 return xgbe_phy_check_mode(pdata, mode,
2424 XGBE_ADV(lks, 10000baseKR_Full));
2430 static bool xgbe_phy_use_mode(struct xgbe_prv_data *pdata, enum xgbe_mode mode)
2432 struct xgbe_phy_data *phy_data = pdata->phy_data;
2434 switch (phy_data->port_mode) {
2435 case XGBE_PORT_MODE_BACKPLANE:
2436 case XGBE_PORT_MODE_BACKPLANE_NO_AUTONEG:
2437 return xgbe_phy_use_bp_mode(pdata, mode);
2438 case XGBE_PORT_MODE_BACKPLANE_2500:
2439 return xgbe_phy_use_bp_2500_mode(pdata, mode);
2440 case XGBE_PORT_MODE_1000BASE_T:
2441 case XGBE_PORT_MODE_NBASE_T:
2442 case XGBE_PORT_MODE_10GBASE_T:
2443 return xgbe_phy_use_baset_mode(pdata, mode);
2444 case XGBE_PORT_MODE_1000BASE_X:
2445 case XGBE_PORT_MODE_10GBASE_R:
2446 return xgbe_phy_use_basex_mode(pdata, mode);
2447 case XGBE_PORT_MODE_SFP:
2448 return xgbe_phy_use_sfp_mode(pdata, mode);
2454 static bool xgbe_phy_valid_speed_basex_mode(struct xgbe_phy_data *phy_data,
2459 return (phy_data->port_mode == XGBE_PORT_MODE_1000BASE_X);
2461 return (phy_data->port_mode == XGBE_PORT_MODE_10GBASE_R);
2467 static bool xgbe_phy_valid_speed_baset_mode(struct xgbe_phy_data *phy_data,
2475 return (phy_data->port_mode == XGBE_PORT_MODE_NBASE_T);
2477 return (phy_data->port_mode == XGBE_PORT_MODE_10GBASE_T);
2483 static bool xgbe_phy_valid_speed_sfp_mode(struct xgbe_phy_data *phy_data,
2488 return (phy_data->sfp_speed == XGBE_SFP_SPEED_100_1000);
2490 return ((phy_data->sfp_speed == XGBE_SFP_SPEED_100_1000) ||
2491 (phy_data->sfp_speed == XGBE_SFP_SPEED_1000));
2493 return (phy_data->sfp_speed == XGBE_SFP_SPEED_10000);
2499 static bool xgbe_phy_valid_speed_bp_2500_mode(int speed)
2509 static bool xgbe_phy_valid_speed_bp_mode(int speed)
2520 static bool xgbe_phy_valid_speed(struct xgbe_prv_data *pdata, int speed)
2522 struct xgbe_phy_data *phy_data = pdata->phy_data;
2524 switch (phy_data->port_mode) {
2525 case XGBE_PORT_MODE_BACKPLANE:
2526 case XGBE_PORT_MODE_BACKPLANE_NO_AUTONEG:
2527 return xgbe_phy_valid_speed_bp_mode(speed);
2528 case XGBE_PORT_MODE_BACKPLANE_2500:
2529 return xgbe_phy_valid_speed_bp_2500_mode(speed);
2530 case XGBE_PORT_MODE_1000BASE_T:
2531 case XGBE_PORT_MODE_NBASE_T:
2532 case XGBE_PORT_MODE_10GBASE_T:
2533 return xgbe_phy_valid_speed_baset_mode(phy_data, speed);
2534 case XGBE_PORT_MODE_1000BASE_X:
2535 case XGBE_PORT_MODE_10GBASE_R:
2536 return xgbe_phy_valid_speed_basex_mode(phy_data, speed);
2537 case XGBE_PORT_MODE_SFP:
2538 return xgbe_phy_valid_speed_sfp_mode(phy_data, speed);
2544 static int xgbe_phy_link_status(struct xgbe_prv_data *pdata, int *an_restart)
2546 struct xgbe_phy_data *phy_data = pdata->phy_data;
2552 if (phy_data->port_mode == XGBE_PORT_MODE_SFP) {
2553 /* Check SFP signals */
2554 xgbe_phy_sfp_detect(pdata);
2556 if (phy_data->sfp_changed) {
2561 if (phy_data->sfp_mod_absent || phy_data->sfp_rx_los)
2565 if (phy_data->phydev) {
2566 /* Check external PHY */
2567 ret = phy_read_status(phy_data->phydev);
2571 if ((pdata->phy.autoneg == AUTONEG_ENABLE) &&
2572 !phy_aneg_done(phy_data->phydev))
2575 if (!phy_data->phydev->link)
2579 /* Link status is latched low, so read once to clear
2580 * and then read again to get current state
2582 reg = XMDIO_READ(pdata, MDIO_MMD_PCS, MDIO_STAT1);
2583 reg = XMDIO_READ(pdata, MDIO_MMD_PCS, MDIO_STAT1);
2584 if (reg & MDIO_STAT1_LSTATUS)
2587 /* No link, attempt a receiver reset cycle */
2588 if (phy_data->rrc_count++ > XGBE_RRC_FREQUENCY) {
2589 phy_data->rrc_count = 0;
2590 xgbe_phy_rrc(pdata);
2596 static void xgbe_phy_sfp_gpio_setup(struct xgbe_prv_data *pdata)
2598 struct xgbe_phy_data *phy_data = pdata->phy_data;
2600 phy_data->sfp_gpio_address = XGBE_GPIO_ADDRESS_PCA9555 +
2601 XP_GET_BITS(pdata->pp3, XP_PROP_3,
2604 phy_data->sfp_gpio_mask = XP_GET_BITS(pdata->pp3, XP_PROP_3,
2607 phy_data->sfp_gpio_rx_los = XP_GET_BITS(pdata->pp3, XP_PROP_3,
2609 phy_data->sfp_gpio_tx_fault = XP_GET_BITS(pdata->pp3, XP_PROP_3,
2611 phy_data->sfp_gpio_mod_absent = XP_GET_BITS(pdata->pp3, XP_PROP_3,
2613 phy_data->sfp_gpio_rate_select = XP_GET_BITS(pdata->pp3, XP_PROP_3,
2616 if (netif_msg_probe(pdata)) {
2617 dev_dbg(pdata->dev, "SFP: gpio_address=%#x\n",
2618 phy_data->sfp_gpio_address);
2619 dev_dbg(pdata->dev, "SFP: gpio_mask=%#x\n",
2620 phy_data->sfp_gpio_mask);
2621 dev_dbg(pdata->dev, "SFP: gpio_rx_los=%u\n",
2622 phy_data->sfp_gpio_rx_los);
2623 dev_dbg(pdata->dev, "SFP: gpio_tx_fault=%u\n",
2624 phy_data->sfp_gpio_tx_fault);
2625 dev_dbg(pdata->dev, "SFP: gpio_mod_absent=%u\n",
2626 phy_data->sfp_gpio_mod_absent);
2627 dev_dbg(pdata->dev, "SFP: gpio_rate_select=%u\n",
2628 phy_data->sfp_gpio_rate_select);
2632 static void xgbe_phy_sfp_comm_setup(struct xgbe_prv_data *pdata)
2634 struct xgbe_phy_data *phy_data = pdata->phy_data;
2635 unsigned int mux_addr_hi, mux_addr_lo;
2637 mux_addr_hi = XP_GET_BITS(pdata->pp4, XP_PROP_4, MUX_ADDR_HI);
2638 mux_addr_lo = XP_GET_BITS(pdata->pp4, XP_PROP_4, MUX_ADDR_LO);
2639 if (mux_addr_lo == XGBE_SFP_DIRECT)
2642 phy_data->sfp_comm = XGBE_SFP_COMM_PCA9545;
2643 phy_data->sfp_mux_address = (mux_addr_hi << 2) + mux_addr_lo;
2644 phy_data->sfp_mux_channel = XP_GET_BITS(pdata->pp4, XP_PROP_4,
2647 if (netif_msg_probe(pdata)) {
2648 dev_dbg(pdata->dev, "SFP: mux_address=%#x\n",
2649 phy_data->sfp_mux_address);
2650 dev_dbg(pdata->dev, "SFP: mux_channel=%u\n",
2651 phy_data->sfp_mux_channel);
2655 static void xgbe_phy_sfp_setup(struct xgbe_prv_data *pdata)
2657 xgbe_phy_sfp_comm_setup(pdata);
2658 xgbe_phy_sfp_gpio_setup(pdata);
2661 static int xgbe_phy_int_mdio_reset(struct xgbe_prv_data *pdata)
2663 struct xgbe_phy_data *phy_data = pdata->phy_data;
2666 ret = pdata->hw_if.set_gpio(pdata, phy_data->mdio_reset_gpio);
2670 ret = pdata->hw_if.clr_gpio(pdata, phy_data->mdio_reset_gpio);
2675 static int xgbe_phy_i2c_mdio_reset(struct xgbe_prv_data *pdata)
2677 struct xgbe_phy_data *phy_data = pdata->phy_data;
2678 u8 gpio_reg, gpio_ports[2], gpio_data[3];
2681 /* Read the output port registers */
2683 ret = xgbe_phy_i2c_read(pdata, phy_data->mdio_reset_addr,
2684 &gpio_reg, sizeof(gpio_reg),
2685 gpio_ports, sizeof(gpio_ports));
2689 /* Prepare to write the GPIO data */
2691 gpio_data[1] = gpio_ports[0];
2692 gpio_data[2] = gpio_ports[1];
2694 /* Set the GPIO pin */
2695 if (phy_data->mdio_reset_gpio < 8)
2696 gpio_data[1] |= (1 << (phy_data->mdio_reset_gpio % 8));
2698 gpio_data[2] |= (1 << (phy_data->mdio_reset_gpio % 8));
2700 /* Write the output port registers */
2701 ret = xgbe_phy_i2c_write(pdata, phy_data->mdio_reset_addr,
2702 gpio_data, sizeof(gpio_data));
2706 /* Clear the GPIO pin */
2707 if (phy_data->mdio_reset_gpio < 8)
2708 gpio_data[1] &= ~(1 << (phy_data->mdio_reset_gpio % 8));
2710 gpio_data[2] &= ~(1 << (phy_data->mdio_reset_gpio % 8));
2712 /* Write the output port registers */
2713 ret = xgbe_phy_i2c_write(pdata, phy_data->mdio_reset_addr,
2714 gpio_data, sizeof(gpio_data));
2719 static int xgbe_phy_mdio_reset(struct xgbe_prv_data *pdata)
2721 struct xgbe_phy_data *phy_data = pdata->phy_data;
2724 if (phy_data->conn_type != XGBE_CONN_TYPE_MDIO)
2727 ret = xgbe_phy_get_comm_ownership(pdata);
2731 if (phy_data->mdio_reset == XGBE_MDIO_RESET_I2C_GPIO)
2732 ret = xgbe_phy_i2c_mdio_reset(pdata);
2733 else if (phy_data->mdio_reset == XGBE_MDIO_RESET_INT_GPIO)
2734 ret = xgbe_phy_int_mdio_reset(pdata);
2736 xgbe_phy_put_comm_ownership(pdata);
2741 static bool xgbe_phy_redrv_error(struct xgbe_phy_data *phy_data)
2743 if (!phy_data->redrv)
2746 if (phy_data->redrv_if >= XGBE_PHY_REDRV_IF_MAX)
2749 switch (phy_data->redrv_model) {
2750 case XGBE_PHY_REDRV_MODEL_4223:
2751 if (phy_data->redrv_lane > 3)
2754 case XGBE_PHY_REDRV_MODEL_4227:
2755 if (phy_data->redrv_lane > 1)
2765 static int xgbe_phy_mdio_reset_setup(struct xgbe_prv_data *pdata)
2767 struct xgbe_phy_data *phy_data = pdata->phy_data;
2769 if (phy_data->conn_type != XGBE_CONN_TYPE_MDIO)
2772 phy_data->mdio_reset = XP_GET_BITS(pdata->pp3, XP_PROP_3, MDIO_RESET);
2773 switch (phy_data->mdio_reset) {
2774 case XGBE_MDIO_RESET_NONE:
2775 case XGBE_MDIO_RESET_I2C_GPIO:
2776 case XGBE_MDIO_RESET_INT_GPIO:
2779 dev_err(pdata->dev, "unsupported MDIO reset (%#x)\n",
2780 phy_data->mdio_reset);
2784 if (phy_data->mdio_reset == XGBE_MDIO_RESET_I2C_GPIO) {
2785 phy_data->mdio_reset_addr = XGBE_GPIO_ADDRESS_PCA9555 +
2786 XP_GET_BITS(pdata->pp3, XP_PROP_3,
2787 MDIO_RESET_I2C_ADDR);
2788 phy_data->mdio_reset_gpio = XP_GET_BITS(pdata->pp3, XP_PROP_3,
2789 MDIO_RESET_I2C_GPIO);
2790 } else if (phy_data->mdio_reset == XGBE_MDIO_RESET_INT_GPIO) {
2791 phy_data->mdio_reset_gpio = XP_GET_BITS(pdata->pp3, XP_PROP_3,
2792 MDIO_RESET_INT_GPIO);
2798 static bool xgbe_phy_port_mode_mismatch(struct xgbe_prv_data *pdata)
2800 struct xgbe_phy_data *phy_data = pdata->phy_data;
2802 switch (phy_data->port_mode) {
2803 case XGBE_PORT_MODE_BACKPLANE:
2804 case XGBE_PORT_MODE_BACKPLANE_NO_AUTONEG:
2805 if ((phy_data->port_speeds & XGBE_PHY_PORT_SPEED_1000) ||
2806 (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_10000))
2809 case XGBE_PORT_MODE_BACKPLANE_2500:
2810 if (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_2500)
2813 case XGBE_PORT_MODE_1000BASE_T:
2814 if ((phy_data->port_speeds & XGBE_PHY_PORT_SPEED_100) ||
2815 (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_1000))
2818 case XGBE_PORT_MODE_1000BASE_X:
2819 if (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_1000)
2822 case XGBE_PORT_MODE_NBASE_T:
2823 if ((phy_data->port_speeds & XGBE_PHY_PORT_SPEED_100) ||
2824 (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_1000) ||
2825 (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_2500))
2828 case XGBE_PORT_MODE_10GBASE_T:
2829 if ((phy_data->port_speeds & XGBE_PHY_PORT_SPEED_100) ||
2830 (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_1000) ||
2831 (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_10000))
2834 case XGBE_PORT_MODE_10GBASE_R:
2835 if (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_10000)
2838 case XGBE_PORT_MODE_SFP:
2839 if ((phy_data->port_speeds & XGBE_PHY_PORT_SPEED_100) ||
2840 (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_1000) ||
2841 (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_10000))
2851 static bool xgbe_phy_conn_type_mismatch(struct xgbe_prv_data *pdata)
2853 struct xgbe_phy_data *phy_data = pdata->phy_data;
2855 switch (phy_data->port_mode) {
2856 case XGBE_PORT_MODE_BACKPLANE:
2857 case XGBE_PORT_MODE_BACKPLANE_NO_AUTONEG:
2858 case XGBE_PORT_MODE_BACKPLANE_2500:
2859 if (phy_data->conn_type == XGBE_CONN_TYPE_BACKPLANE)
2862 case XGBE_PORT_MODE_1000BASE_T:
2863 case XGBE_PORT_MODE_1000BASE_X:
2864 case XGBE_PORT_MODE_NBASE_T:
2865 case XGBE_PORT_MODE_10GBASE_T:
2866 case XGBE_PORT_MODE_10GBASE_R:
2867 if (phy_data->conn_type == XGBE_CONN_TYPE_MDIO)
2870 case XGBE_PORT_MODE_SFP:
2871 if (phy_data->conn_type == XGBE_CONN_TYPE_SFP)
2881 static bool xgbe_phy_port_enabled(struct xgbe_prv_data *pdata)
2883 if (!XP_GET_BITS(pdata->pp0, XP_PROP_0, PORT_SPEEDS))
2885 if (!XP_GET_BITS(pdata->pp0, XP_PROP_0, CONN_TYPE))
2891 static void xgbe_phy_cdr_track(struct xgbe_prv_data *pdata)
2893 struct xgbe_phy_data *phy_data = pdata->phy_data;
2895 if (!pdata->debugfs_an_cdr_workaround)
2898 if (!phy_data->phy_cdr_notrack)
2901 usleep_range(phy_data->phy_cdr_delay,
2902 phy_data->phy_cdr_delay + 500);
2904 XMDIO_WRITE_BITS(pdata, MDIO_MMD_PMAPMD, MDIO_VEND2_PMA_CDR_CONTROL,
2905 XGBE_PMA_CDR_TRACK_EN_MASK,
2906 XGBE_PMA_CDR_TRACK_EN_ON);
2908 phy_data->phy_cdr_notrack = 0;
2911 static void xgbe_phy_cdr_notrack(struct xgbe_prv_data *pdata)
2913 struct xgbe_phy_data *phy_data = pdata->phy_data;
2915 if (!pdata->debugfs_an_cdr_workaround)
2918 if (phy_data->phy_cdr_notrack)
2921 XMDIO_WRITE_BITS(pdata, MDIO_MMD_PMAPMD, MDIO_VEND2_PMA_CDR_CONTROL,
2922 XGBE_PMA_CDR_TRACK_EN_MASK,
2923 XGBE_PMA_CDR_TRACK_EN_OFF);
2925 xgbe_phy_rrc(pdata);
2927 phy_data->phy_cdr_notrack = 1;
2930 static void xgbe_phy_kr_training_post(struct xgbe_prv_data *pdata)
2932 if (!pdata->debugfs_an_cdr_track_early)
2933 xgbe_phy_cdr_track(pdata);
2936 static void xgbe_phy_kr_training_pre(struct xgbe_prv_data *pdata)
2938 if (pdata->debugfs_an_cdr_track_early)
2939 xgbe_phy_cdr_track(pdata);
2942 static void xgbe_phy_an_post(struct xgbe_prv_data *pdata)
2944 struct xgbe_phy_data *phy_data = pdata->phy_data;
2946 switch (pdata->an_mode) {
2947 case XGBE_AN_MODE_CL73:
2948 case XGBE_AN_MODE_CL73_REDRV:
2949 if (phy_data->cur_mode != XGBE_MODE_KR)
2952 xgbe_phy_cdr_track(pdata);
2954 switch (pdata->an_result) {
2956 case XGBE_AN_COMPLETE:
2959 if (phy_data->phy_cdr_delay < XGBE_CDR_DELAY_MAX)
2960 phy_data->phy_cdr_delay += XGBE_CDR_DELAY_INC;
2962 phy_data->phy_cdr_delay = XGBE_CDR_DELAY_INIT;
2971 static void xgbe_phy_an_pre(struct xgbe_prv_data *pdata)
2973 struct xgbe_phy_data *phy_data = pdata->phy_data;
2975 switch (pdata->an_mode) {
2976 case XGBE_AN_MODE_CL73:
2977 case XGBE_AN_MODE_CL73_REDRV:
2978 if (phy_data->cur_mode != XGBE_MODE_KR)
2981 xgbe_phy_cdr_notrack(pdata);
2988 static void xgbe_phy_stop(struct xgbe_prv_data *pdata)
2990 struct xgbe_phy_data *phy_data = pdata->phy_data;
2992 /* If we have an external PHY, free it */
2993 xgbe_phy_free_phy_device(pdata);
2995 /* Reset SFP data */
2996 xgbe_phy_sfp_reset(phy_data);
2997 xgbe_phy_sfp_mod_absent(pdata);
2999 /* Reset CDR support */
3000 xgbe_phy_cdr_track(pdata);
3002 /* Power off the PHY */
3003 xgbe_phy_power_off(pdata);
3005 /* Stop the I2C controller */
3006 pdata->i2c_if.i2c_stop(pdata);
3009 static int xgbe_phy_start(struct xgbe_prv_data *pdata)
3011 struct xgbe_phy_data *phy_data = pdata->phy_data;
3014 /* Start the I2C controller */
3015 ret = pdata->i2c_if.i2c_start(pdata);
3019 /* Set the proper MDIO mode for the re-driver */
3020 if (phy_data->redrv && !phy_data->redrv_if) {
3021 ret = pdata->hw_if.set_ext_mii_mode(pdata, phy_data->redrv_addr,
3022 XGBE_MDIO_MODE_CL22);
3024 netdev_err(pdata->netdev,
3025 "redriver mdio port not compatible (%u)\n",
3026 phy_data->redrv_addr);
3031 /* Start in highest supported mode */
3032 xgbe_phy_set_mode(pdata, phy_data->start_mode);
3034 /* Reset CDR support */
3035 xgbe_phy_cdr_track(pdata);
3037 /* After starting the I2C controller, we can check for an SFP */
3038 switch (phy_data->port_mode) {
3039 case XGBE_PORT_MODE_SFP:
3040 xgbe_phy_sfp_detect(pdata);
3046 /* If we have an external PHY, start it */
3047 ret = xgbe_phy_find_phy_device(pdata);
3054 pdata->i2c_if.i2c_stop(pdata);
3059 static int xgbe_phy_reset(struct xgbe_prv_data *pdata)
3061 struct xgbe_phy_data *phy_data = pdata->phy_data;
3062 enum xgbe_mode cur_mode;
3065 /* Reset by power cycling the PHY */
3066 cur_mode = phy_data->cur_mode;
3067 xgbe_phy_power_off(pdata);
3068 xgbe_phy_set_mode(pdata, cur_mode);
3070 if (!phy_data->phydev)
3073 /* Reset the external PHY */
3074 ret = xgbe_phy_mdio_reset(pdata);
3078 return phy_init_hw(phy_data->phydev);
3081 static void xgbe_phy_exit(struct xgbe_prv_data *pdata)
3083 struct xgbe_phy_data *phy_data = pdata->phy_data;
3085 /* Unregister for driving external PHYs */
3086 mdiobus_unregister(phy_data->mii);
3089 static int xgbe_phy_init(struct xgbe_prv_data *pdata)
3091 struct ethtool_link_ksettings *lks = &pdata->phy.lks;
3092 struct xgbe_phy_data *phy_data;
3093 struct mii_bus *mii;
3096 /* Check if enabled */
3097 if (!xgbe_phy_port_enabled(pdata)) {
3098 dev_info(pdata->dev, "device is not enabled\n");
3102 /* Initialize the I2C controller */
3103 ret = pdata->i2c_if.i2c_init(pdata);
3107 phy_data = devm_kzalloc(pdata->dev, sizeof(*phy_data), GFP_KERNEL);
3110 pdata->phy_data = phy_data;
3112 phy_data->port_mode = XP_GET_BITS(pdata->pp0, XP_PROP_0, PORT_MODE);
3113 phy_data->port_id = XP_GET_BITS(pdata->pp0, XP_PROP_0, PORT_ID);
3114 phy_data->port_speeds = XP_GET_BITS(pdata->pp0, XP_PROP_0, PORT_SPEEDS);
3115 phy_data->conn_type = XP_GET_BITS(pdata->pp0, XP_PROP_0, CONN_TYPE);
3116 phy_data->mdio_addr = XP_GET_BITS(pdata->pp0, XP_PROP_0, MDIO_ADDR);
3117 if (netif_msg_probe(pdata)) {
3118 dev_dbg(pdata->dev, "port mode=%u\n", phy_data->port_mode);
3119 dev_dbg(pdata->dev, "port id=%u\n", phy_data->port_id);
3120 dev_dbg(pdata->dev, "port speeds=%#x\n", phy_data->port_speeds);
3121 dev_dbg(pdata->dev, "conn type=%u\n", phy_data->conn_type);
3122 dev_dbg(pdata->dev, "mdio addr=%u\n", phy_data->mdio_addr);
3125 phy_data->redrv = XP_GET_BITS(pdata->pp4, XP_PROP_4, REDRV_PRESENT);
3126 phy_data->redrv_if = XP_GET_BITS(pdata->pp4, XP_PROP_4, REDRV_IF);
3127 phy_data->redrv_addr = XP_GET_BITS(pdata->pp4, XP_PROP_4, REDRV_ADDR);
3128 phy_data->redrv_lane = XP_GET_BITS(pdata->pp4, XP_PROP_4, REDRV_LANE);
3129 phy_data->redrv_model = XP_GET_BITS(pdata->pp4, XP_PROP_4, REDRV_MODEL);
3130 if (phy_data->redrv && netif_msg_probe(pdata)) {
3131 dev_dbg(pdata->dev, "redrv present\n");
3132 dev_dbg(pdata->dev, "redrv i/f=%u\n", phy_data->redrv_if);
3133 dev_dbg(pdata->dev, "redrv addr=%#x\n", phy_data->redrv_addr);
3134 dev_dbg(pdata->dev, "redrv lane=%u\n", phy_data->redrv_lane);
3135 dev_dbg(pdata->dev, "redrv model=%u\n", phy_data->redrv_model);
3138 /* Validate the connection requested */
3139 if (xgbe_phy_conn_type_mismatch(pdata)) {
3140 dev_err(pdata->dev, "phy mode/connection mismatch (%#x/%#x)\n",
3141 phy_data->port_mode, phy_data->conn_type);
3145 /* Validate the mode requested */
3146 if (xgbe_phy_port_mode_mismatch(pdata)) {
3147 dev_err(pdata->dev, "phy mode/speed mismatch (%#x/%#x)\n",
3148 phy_data->port_mode, phy_data->port_speeds);
3152 /* Check for and validate MDIO reset support */
3153 ret = xgbe_phy_mdio_reset_setup(pdata);
3157 /* Validate the re-driver information */
3158 if (xgbe_phy_redrv_error(phy_data)) {
3159 dev_err(pdata->dev, "phy re-driver settings error\n");
3162 pdata->kr_redrv = phy_data->redrv;
3164 /* Indicate current mode is unknown */
3165 phy_data->cur_mode = XGBE_MODE_UNKNOWN;
3167 /* Initialize supported features */
3170 switch (phy_data->port_mode) {
3171 /* Backplane support */
3172 case XGBE_PORT_MODE_BACKPLANE:
3173 XGBE_SET_SUP(lks, Autoneg);
3175 case XGBE_PORT_MODE_BACKPLANE_NO_AUTONEG:
3176 XGBE_SET_SUP(lks, Pause);
3177 XGBE_SET_SUP(lks, Asym_Pause);
3178 XGBE_SET_SUP(lks, Backplane);
3179 if (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_1000) {
3180 XGBE_SET_SUP(lks, 1000baseKX_Full);
3181 phy_data->start_mode = XGBE_MODE_KX_1000;
3183 if (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_10000) {
3184 XGBE_SET_SUP(lks, 10000baseKR_Full);
3185 if (pdata->fec_ability & MDIO_PMA_10GBR_FECABLE_ABLE)
3186 XGBE_SET_SUP(lks, 10000baseR_FEC);
3187 phy_data->start_mode = XGBE_MODE_KR;
3190 phy_data->phydev_mode = XGBE_MDIO_MODE_NONE;
3192 case XGBE_PORT_MODE_BACKPLANE_2500:
3193 XGBE_SET_SUP(lks, Pause);
3194 XGBE_SET_SUP(lks, Asym_Pause);
3195 XGBE_SET_SUP(lks, Backplane);
3196 XGBE_SET_SUP(lks, 2500baseX_Full);
3197 phy_data->start_mode = XGBE_MODE_KX_2500;
3199 phy_data->phydev_mode = XGBE_MDIO_MODE_NONE;
3202 /* MDIO 1GBase-T support */
3203 case XGBE_PORT_MODE_1000BASE_T:
3204 XGBE_SET_SUP(lks, Autoneg);
3205 XGBE_SET_SUP(lks, Pause);
3206 XGBE_SET_SUP(lks, Asym_Pause);
3207 XGBE_SET_SUP(lks, TP);
3208 if (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_100) {
3209 XGBE_SET_SUP(lks, 100baseT_Full);
3210 phy_data->start_mode = XGBE_MODE_SGMII_100;
3212 if (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_1000) {
3213 XGBE_SET_SUP(lks, 1000baseT_Full);
3214 phy_data->start_mode = XGBE_MODE_SGMII_1000;
3217 phy_data->phydev_mode = XGBE_MDIO_MODE_CL22;
3220 /* MDIO Base-X support */
3221 case XGBE_PORT_MODE_1000BASE_X:
3222 XGBE_SET_SUP(lks, Autoneg);
3223 XGBE_SET_SUP(lks, Pause);
3224 XGBE_SET_SUP(lks, Asym_Pause);
3225 XGBE_SET_SUP(lks, FIBRE);
3226 XGBE_SET_SUP(lks, 1000baseX_Full);
3227 phy_data->start_mode = XGBE_MODE_X;
3229 phy_data->phydev_mode = XGBE_MDIO_MODE_CL22;
3232 /* MDIO NBase-T support */
3233 case XGBE_PORT_MODE_NBASE_T:
3234 XGBE_SET_SUP(lks, Autoneg);
3235 XGBE_SET_SUP(lks, Pause);
3236 XGBE_SET_SUP(lks, Asym_Pause);
3237 XGBE_SET_SUP(lks, TP);
3238 if (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_100) {
3239 XGBE_SET_SUP(lks, 100baseT_Full);
3240 phy_data->start_mode = XGBE_MODE_SGMII_100;
3242 if (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_1000) {
3243 XGBE_SET_SUP(lks, 1000baseT_Full);
3244 phy_data->start_mode = XGBE_MODE_SGMII_1000;
3246 if (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_2500) {
3247 XGBE_SET_SUP(lks, 2500baseT_Full);
3248 phy_data->start_mode = XGBE_MODE_KX_2500;
3251 phy_data->phydev_mode = XGBE_MDIO_MODE_CL45;
3254 /* 10GBase-T support */
3255 case XGBE_PORT_MODE_10GBASE_T:
3256 XGBE_SET_SUP(lks, Autoneg);
3257 XGBE_SET_SUP(lks, Pause);
3258 XGBE_SET_SUP(lks, Asym_Pause);
3259 XGBE_SET_SUP(lks, TP);
3260 if (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_100) {
3261 XGBE_SET_SUP(lks, 100baseT_Full);
3262 phy_data->start_mode = XGBE_MODE_SGMII_100;
3264 if (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_1000) {
3265 XGBE_SET_SUP(lks, 1000baseT_Full);
3266 phy_data->start_mode = XGBE_MODE_SGMII_1000;
3268 if (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_10000) {
3269 XGBE_SET_SUP(lks, 10000baseT_Full);
3270 phy_data->start_mode = XGBE_MODE_KR;
3273 phy_data->phydev_mode = XGBE_MDIO_MODE_CL45;
3276 /* 10GBase-R support */
3277 case XGBE_PORT_MODE_10GBASE_R:
3278 XGBE_SET_SUP(lks, Autoneg);
3279 XGBE_SET_SUP(lks, Pause);
3280 XGBE_SET_SUP(lks, Asym_Pause);
3281 XGBE_SET_SUP(lks, FIBRE);
3282 XGBE_SET_SUP(lks, 10000baseSR_Full);
3283 XGBE_SET_SUP(lks, 10000baseLR_Full);
3284 XGBE_SET_SUP(lks, 10000baseLRM_Full);
3285 XGBE_SET_SUP(lks, 10000baseER_Full);
3286 if (pdata->fec_ability & MDIO_PMA_10GBR_FECABLE_ABLE)
3287 XGBE_SET_SUP(lks, 10000baseR_FEC);
3288 phy_data->start_mode = XGBE_MODE_SFI;
3290 phy_data->phydev_mode = XGBE_MDIO_MODE_NONE;
3294 case XGBE_PORT_MODE_SFP:
3295 XGBE_SET_SUP(lks, Autoneg);
3296 XGBE_SET_SUP(lks, Pause);
3297 XGBE_SET_SUP(lks, Asym_Pause);
3298 XGBE_SET_SUP(lks, TP);
3299 XGBE_SET_SUP(lks, FIBRE);
3300 if (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_100)
3301 phy_data->start_mode = XGBE_MODE_SGMII_100;
3302 if (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_1000)
3303 phy_data->start_mode = XGBE_MODE_SGMII_1000;
3304 if (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_10000)
3305 phy_data->start_mode = XGBE_MODE_SFI;
3307 phy_data->phydev_mode = XGBE_MDIO_MODE_CL22;
3309 xgbe_phy_sfp_setup(pdata);
3315 if (netif_msg_probe(pdata))
3316 dev_dbg(pdata->dev, "phy supported=0x%*pb\n",
3317 __ETHTOOL_LINK_MODE_MASK_NBITS,
3318 lks->link_modes.supported);
3320 if ((phy_data->conn_type & XGBE_CONN_TYPE_MDIO) &&
3321 (phy_data->phydev_mode != XGBE_MDIO_MODE_NONE)) {
3322 ret = pdata->hw_if.set_ext_mii_mode(pdata, phy_data->mdio_addr,
3323 phy_data->phydev_mode);
3326 "mdio port/clause not compatible (%d/%u)\n",
3327 phy_data->mdio_addr, phy_data->phydev_mode);
3332 if (phy_data->redrv && !phy_data->redrv_if) {
3333 ret = pdata->hw_if.set_ext_mii_mode(pdata, phy_data->redrv_addr,
3334 XGBE_MDIO_MODE_CL22);
3337 "redriver mdio port not compatible (%u)\n",
3338 phy_data->redrv_addr);
3343 phy_data->phy_cdr_delay = XGBE_CDR_DELAY_INIT;
3345 /* Register for driving external PHYs */
3346 mii = devm_mdiobus_alloc(pdata->dev);
3348 dev_err(pdata->dev, "mdiobus_alloc failed\n");
3353 mii->name = "amd-xgbe-mii";
3354 mii->read = xgbe_phy_mii_read;
3355 mii->write = xgbe_phy_mii_write;
3356 mii->parent = pdata->dev;
3358 snprintf(mii->id, sizeof(mii->id), "%s", dev_name(pdata->dev));
3359 ret = mdiobus_register(mii);
3361 dev_err(pdata->dev, "mdiobus_register failed\n");
3364 phy_data->mii = mii;
3369 void xgbe_init_function_ptrs_phy_v2(struct xgbe_phy_if *phy_if)
3371 struct xgbe_phy_impl_if *phy_impl = &phy_if->phy_impl;
3373 phy_impl->init = xgbe_phy_init;
3374 phy_impl->exit = xgbe_phy_exit;
3376 phy_impl->reset = xgbe_phy_reset;
3377 phy_impl->start = xgbe_phy_start;
3378 phy_impl->stop = xgbe_phy_stop;
3380 phy_impl->link_status = xgbe_phy_link_status;
3382 phy_impl->valid_speed = xgbe_phy_valid_speed;
3384 phy_impl->use_mode = xgbe_phy_use_mode;
3385 phy_impl->set_mode = xgbe_phy_set_mode;
3386 phy_impl->get_mode = xgbe_phy_get_mode;
3387 phy_impl->switch_mode = xgbe_phy_switch_mode;
3388 phy_impl->cur_mode = xgbe_phy_cur_mode;
3390 phy_impl->an_mode = xgbe_phy_an_mode;
3392 phy_impl->an_config = xgbe_phy_an_config;
3394 phy_impl->an_advertising = xgbe_phy_an_advertising;
3396 phy_impl->an_outcome = xgbe_phy_an_outcome;
3398 phy_impl->an_pre = xgbe_phy_an_pre;
3399 phy_impl->an_post = xgbe_phy_an_post;
3401 phy_impl->kr_training_pre = xgbe_phy_kr_training_pre;
3402 phy_impl->kr_training_post = xgbe_phy_kr_training_post;
3404 phy_impl->module_info = xgbe_phy_module_info;
3405 phy_impl->module_eeprom = xgbe_phy_module_eeprom;