2 * AMD 10Gb Ethernet driver
4 * This file is available to you under your choice of the following two
9 * Copyright (c) 2014-2016 Advanced Micro Devices, Inc.
11 * This file is free software; you may copy, redistribute and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation, either version 2 of the License, or (at
14 * your option) any later version.
16 * This file is distributed in the hope that it will be useful, but
17 * WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
19 * General Public License for more details.
21 * You should have received a copy of the GNU General Public License
22 * along with this program. If not, see <http://www.gnu.org/licenses/>.
24 * This file incorporates work covered by the following copyright and
26 * The Synopsys DWC ETHER XGMAC Software Driver and documentation
27 * (hereinafter "Software") is an unsupported proprietary work of Synopsys,
28 * Inc. unless otherwise expressly agreed to in writing between Synopsys
31 * The Software IS NOT an item of Licensed Software or Licensed Product
32 * under any End User Software License Agreement or Agreement for Licensed
33 * Product with Synopsys or any supplement thereto. Permission is hereby
34 * granted, free of charge, to any person obtaining a copy of this software
35 * annotated with this license and the Software, to deal in the Software
36 * without restriction, including without limitation the rights to use,
37 * copy, modify, merge, publish, distribute, sublicense, and/or sell copies
38 * of the Software, and to permit persons to whom the Software is furnished
39 * to do so, subject to the following conditions:
41 * The above copyright notice and this permission notice shall be included
42 * in all copies or substantial portions of the Software.
44 * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS"
45 * BASIS AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
46 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
47 * PARTICULAR PURPOSE ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS
48 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
49 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
50 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
51 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
52 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
53 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
54 * THE POSSIBILITY OF SUCH DAMAGE.
57 * License 2: Modified BSD
59 * Copyright (c) 2014-2016 Advanced Micro Devices, Inc.
60 * All rights reserved.
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63 * modification, are permitted provided that the following conditions are met:
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65 * notice, this list of conditions and the following disclaimer.
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68 * documentation and/or other materials provided with the distribution.
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70 * names of its contributors may be used to endorse or promote products
71 * derived from this software without specific prior written permission.
73 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
74 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
75 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
76 * ARE DISCLAIMED. IN NO EVENT SHALL <COPYRIGHT HOLDER> BE LIABLE FOR ANY
77 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
78 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
79 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
80 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
81 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
82 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
84 * This file incorporates work covered by the following copyright and
86 * The Synopsys DWC ETHER XGMAC Software Driver and documentation
87 * (hereinafter "Software") is an unsupported proprietary work of Synopsys,
88 * Inc. unless otherwise expressly agreed to in writing between Synopsys
91 * The Software IS NOT an item of Licensed Software or Licensed Product
92 * under any End User Software License Agreement or Agreement for Licensed
93 * Product with Synopsys or any supplement thereto. Permission is hereby
94 * granted, free of charge, to any person obtaining a copy of this software
95 * annotated with this license and the Software, to deal in the Software
96 * without restriction, including without limitation the rights to use,
97 * copy, modify, merge, publish, distribute, sublicense, and/or sell copies
98 * of the Software, and to permit persons to whom the Software is furnished
99 * to do so, subject to the following conditions:
101 * The above copyright notice and this permission notice shall be included
102 * in all copies or substantial portions of the Software.
104 * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS"
105 * BASIS AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
106 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
107 * PARTICULAR PURPOSE ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS
108 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
109 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
110 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
111 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
112 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
113 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
114 * THE POSSIBILITY OF SUCH DAMAGE.
117 #include <linux/interrupt.h>
118 #include <linux/module.h>
119 #include <linux/kmod.h>
120 #include <linux/mdio.h>
121 #include <linux/phy.h>
122 #include <linux/of.h>
123 #include <linux/bitops.h>
124 #include <linux/jiffies.h>
127 #include "xgbe-common.h"
129 static int xgbe_phy_module_eeprom(struct xgbe_prv_data *pdata,
130 struct ethtool_eeprom *eeprom, u8 *data)
132 if (!pdata->phy_if.phy_impl.module_eeprom)
135 return pdata->phy_if.phy_impl.module_eeprom(pdata, eeprom, data);
138 static int xgbe_phy_module_info(struct xgbe_prv_data *pdata,
139 struct ethtool_modinfo *modinfo)
141 if (!pdata->phy_if.phy_impl.module_info)
144 return pdata->phy_if.phy_impl.module_info(pdata, modinfo);
147 static void xgbe_an37_clear_interrupts(struct xgbe_prv_data *pdata)
151 reg = XMDIO_READ(pdata, MDIO_MMD_VEND2, MDIO_VEND2_AN_STAT);
152 reg &= ~XGBE_AN_CL37_INT_MASK;
153 XMDIO_WRITE(pdata, MDIO_MMD_VEND2, MDIO_VEND2_AN_STAT, reg);
156 static void xgbe_an37_disable_interrupts(struct xgbe_prv_data *pdata)
160 reg = XMDIO_READ(pdata, MDIO_MMD_VEND2, MDIO_VEND2_AN_CTRL);
161 reg &= ~XGBE_AN_CL37_INT_MASK;
162 XMDIO_WRITE(pdata, MDIO_MMD_VEND2, MDIO_VEND2_AN_CTRL, reg);
164 reg = XMDIO_READ(pdata, MDIO_MMD_PCS, MDIO_PCS_DIG_CTRL);
165 reg &= ~XGBE_PCS_CL37_BP;
166 XMDIO_WRITE(pdata, MDIO_MMD_PCS, MDIO_PCS_DIG_CTRL, reg);
169 static void xgbe_an37_enable_interrupts(struct xgbe_prv_data *pdata)
173 reg = XMDIO_READ(pdata, MDIO_MMD_PCS, MDIO_PCS_DIG_CTRL);
174 reg |= XGBE_PCS_CL37_BP;
175 XMDIO_WRITE(pdata, MDIO_MMD_PCS, MDIO_PCS_DIG_CTRL, reg);
177 reg = XMDIO_READ(pdata, MDIO_MMD_VEND2, MDIO_VEND2_AN_CTRL);
178 reg |= XGBE_AN_CL37_INT_MASK;
179 XMDIO_WRITE(pdata, MDIO_MMD_VEND2, MDIO_VEND2_AN_CTRL, reg);
182 static void xgbe_an73_clear_interrupts(struct xgbe_prv_data *pdata)
184 XMDIO_WRITE(pdata, MDIO_MMD_AN, MDIO_AN_INT, 0);
187 static void xgbe_an73_disable_interrupts(struct xgbe_prv_data *pdata)
189 XMDIO_WRITE(pdata, MDIO_MMD_AN, MDIO_AN_INTMASK, 0);
192 static void xgbe_an73_enable_interrupts(struct xgbe_prv_data *pdata)
194 XMDIO_WRITE(pdata, MDIO_MMD_AN, MDIO_AN_INTMASK, XGBE_AN_CL73_INT_MASK);
197 static void xgbe_an_enable_interrupts(struct xgbe_prv_data *pdata)
199 switch (pdata->an_mode) {
200 case XGBE_AN_MODE_CL73:
201 case XGBE_AN_MODE_CL73_REDRV:
202 xgbe_an73_enable_interrupts(pdata);
204 case XGBE_AN_MODE_CL37:
205 case XGBE_AN_MODE_CL37_SGMII:
206 xgbe_an37_enable_interrupts(pdata);
213 static void xgbe_an_clear_interrupts_all(struct xgbe_prv_data *pdata)
215 xgbe_an73_clear_interrupts(pdata);
216 xgbe_an37_clear_interrupts(pdata);
219 static void xgbe_an73_enable_kr_training(struct xgbe_prv_data *pdata)
223 reg = XMDIO_READ(pdata, MDIO_MMD_PMAPMD, MDIO_PMA_10GBR_PMD_CTRL);
225 reg |= XGBE_KR_TRAINING_ENABLE;
226 XMDIO_WRITE(pdata, MDIO_MMD_PMAPMD, MDIO_PMA_10GBR_PMD_CTRL, reg);
229 static void xgbe_an73_disable_kr_training(struct xgbe_prv_data *pdata)
233 reg = XMDIO_READ(pdata, MDIO_MMD_PMAPMD, MDIO_PMA_10GBR_PMD_CTRL);
235 reg &= ~XGBE_KR_TRAINING_ENABLE;
236 XMDIO_WRITE(pdata, MDIO_MMD_PMAPMD, MDIO_PMA_10GBR_PMD_CTRL, reg);
239 static void xgbe_kr_mode(struct xgbe_prv_data *pdata)
241 /* Enable KR training */
242 xgbe_an73_enable_kr_training(pdata);
244 /* Set MAC to 10G speed */
245 pdata->hw_if.set_speed(pdata, SPEED_10000);
247 /* Call PHY implementation support to complete rate change */
248 pdata->phy_if.phy_impl.set_mode(pdata, XGBE_MODE_KR);
251 static void xgbe_kx_2500_mode(struct xgbe_prv_data *pdata)
253 /* Disable KR training */
254 xgbe_an73_disable_kr_training(pdata);
256 /* Set MAC to 2.5G speed */
257 pdata->hw_if.set_speed(pdata, SPEED_2500);
259 /* Call PHY implementation support to complete rate change */
260 pdata->phy_if.phy_impl.set_mode(pdata, XGBE_MODE_KX_2500);
263 static void xgbe_kx_1000_mode(struct xgbe_prv_data *pdata)
265 /* Disable KR training */
266 xgbe_an73_disable_kr_training(pdata);
268 /* Set MAC to 1G speed */
269 pdata->hw_if.set_speed(pdata, SPEED_1000);
271 /* Call PHY implementation support to complete rate change */
272 pdata->phy_if.phy_impl.set_mode(pdata, XGBE_MODE_KX_1000);
275 static void xgbe_sfi_mode(struct xgbe_prv_data *pdata)
277 /* If a KR re-driver is present, change to KR mode instead */
279 return xgbe_kr_mode(pdata);
281 /* Disable KR training */
282 xgbe_an73_disable_kr_training(pdata);
284 /* Set MAC to 10G speed */
285 pdata->hw_if.set_speed(pdata, SPEED_10000);
287 /* Call PHY implementation support to complete rate change */
288 pdata->phy_if.phy_impl.set_mode(pdata, XGBE_MODE_SFI);
291 static void xgbe_x_mode(struct xgbe_prv_data *pdata)
293 /* Disable KR training */
294 xgbe_an73_disable_kr_training(pdata);
296 /* Set MAC to 1G speed */
297 pdata->hw_if.set_speed(pdata, SPEED_1000);
299 /* Call PHY implementation support to complete rate change */
300 pdata->phy_if.phy_impl.set_mode(pdata, XGBE_MODE_X);
303 static void xgbe_sgmii_1000_mode(struct xgbe_prv_data *pdata)
305 /* Disable KR training */
306 xgbe_an73_disable_kr_training(pdata);
308 /* Set MAC to 1G speed */
309 pdata->hw_if.set_speed(pdata, SPEED_1000);
311 /* Call PHY implementation support to complete rate change */
312 pdata->phy_if.phy_impl.set_mode(pdata, XGBE_MODE_SGMII_1000);
315 static void xgbe_sgmii_100_mode(struct xgbe_prv_data *pdata)
317 /* Disable KR training */
318 xgbe_an73_disable_kr_training(pdata);
320 /* Set MAC to 1G speed */
321 pdata->hw_if.set_speed(pdata, SPEED_1000);
323 /* Call PHY implementation support to complete rate change */
324 pdata->phy_if.phy_impl.set_mode(pdata, XGBE_MODE_SGMII_100);
327 static enum xgbe_mode xgbe_cur_mode(struct xgbe_prv_data *pdata)
329 return pdata->phy_if.phy_impl.cur_mode(pdata);
332 static bool xgbe_in_kr_mode(struct xgbe_prv_data *pdata)
334 return (xgbe_cur_mode(pdata) == XGBE_MODE_KR);
337 static void xgbe_change_mode(struct xgbe_prv_data *pdata,
341 case XGBE_MODE_KX_1000:
342 xgbe_kx_1000_mode(pdata);
344 case XGBE_MODE_KX_2500:
345 xgbe_kx_2500_mode(pdata);
350 case XGBE_MODE_SGMII_100:
351 xgbe_sgmii_100_mode(pdata);
353 case XGBE_MODE_SGMII_1000:
354 xgbe_sgmii_1000_mode(pdata);
360 xgbe_sfi_mode(pdata);
362 case XGBE_MODE_UNKNOWN:
365 netif_dbg(pdata, link, pdata->netdev,
366 "invalid operation mode requested (%u)\n", mode);
370 static void xgbe_switch_mode(struct xgbe_prv_data *pdata)
372 xgbe_change_mode(pdata, pdata->phy_if.phy_impl.switch_mode(pdata));
375 static void xgbe_set_mode(struct xgbe_prv_data *pdata,
378 if (mode == xgbe_cur_mode(pdata))
381 xgbe_change_mode(pdata, mode);
384 static bool xgbe_use_mode(struct xgbe_prv_data *pdata,
387 return pdata->phy_if.phy_impl.use_mode(pdata, mode);
390 static void xgbe_an37_set(struct xgbe_prv_data *pdata, bool enable,
395 reg = XMDIO_READ(pdata, MDIO_MMD_VEND2, MDIO_CTRL1);
396 reg &= ~MDIO_VEND2_CTRL1_AN_ENABLE;
399 reg |= MDIO_VEND2_CTRL1_AN_ENABLE;
402 reg |= MDIO_VEND2_CTRL1_AN_RESTART;
404 XMDIO_WRITE(pdata, MDIO_MMD_VEND2, MDIO_CTRL1, reg);
407 static void xgbe_an37_restart(struct xgbe_prv_data *pdata)
409 xgbe_an37_enable_interrupts(pdata);
410 xgbe_an37_set(pdata, true, true);
412 netif_dbg(pdata, link, pdata->netdev, "CL37 AN enabled/restarted\n");
415 static void xgbe_an37_disable(struct xgbe_prv_data *pdata)
417 xgbe_an37_set(pdata, false, false);
418 xgbe_an37_disable_interrupts(pdata);
420 netif_dbg(pdata, link, pdata->netdev, "CL37 AN disabled\n");
423 static void xgbe_an73_set(struct xgbe_prv_data *pdata, bool enable,
428 reg = XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_CTRL1);
429 reg &= ~MDIO_AN_CTRL1_ENABLE;
432 reg |= MDIO_AN_CTRL1_ENABLE;
435 reg |= MDIO_AN_CTRL1_RESTART;
437 XMDIO_WRITE(pdata, MDIO_MMD_AN, MDIO_CTRL1, reg);
440 static void xgbe_an73_restart(struct xgbe_prv_data *pdata)
442 xgbe_an73_enable_interrupts(pdata);
443 xgbe_an73_set(pdata, true, true);
445 netif_dbg(pdata, link, pdata->netdev, "CL73 AN enabled/restarted\n");
448 static void xgbe_an73_disable(struct xgbe_prv_data *pdata)
450 xgbe_an73_set(pdata, false, false);
451 xgbe_an73_disable_interrupts(pdata);
455 netif_dbg(pdata, link, pdata->netdev, "CL73 AN disabled\n");
458 static void xgbe_an_restart(struct xgbe_prv_data *pdata)
460 if (pdata->phy_if.phy_impl.an_pre)
461 pdata->phy_if.phy_impl.an_pre(pdata);
463 switch (pdata->an_mode) {
464 case XGBE_AN_MODE_CL73:
465 case XGBE_AN_MODE_CL73_REDRV:
466 xgbe_an73_restart(pdata);
468 case XGBE_AN_MODE_CL37:
469 case XGBE_AN_MODE_CL37_SGMII:
470 xgbe_an37_restart(pdata);
477 static void xgbe_an_disable(struct xgbe_prv_data *pdata)
479 if (pdata->phy_if.phy_impl.an_post)
480 pdata->phy_if.phy_impl.an_post(pdata);
482 switch (pdata->an_mode) {
483 case XGBE_AN_MODE_CL73:
484 case XGBE_AN_MODE_CL73_REDRV:
485 xgbe_an73_disable(pdata);
487 case XGBE_AN_MODE_CL37:
488 case XGBE_AN_MODE_CL37_SGMII:
489 xgbe_an37_disable(pdata);
496 static void xgbe_an_disable_all(struct xgbe_prv_data *pdata)
498 xgbe_an73_disable(pdata);
499 xgbe_an37_disable(pdata);
502 static enum xgbe_an xgbe_an73_tx_training(struct xgbe_prv_data *pdata,
505 unsigned int ad_reg, lp_reg, reg;
507 *state = XGBE_RX_COMPLETE;
509 /* If we're not in KR mode then we're done */
510 if (!xgbe_in_kr_mode(pdata))
511 return XGBE_AN_PAGE_RECEIVED;
513 /* Enable/Disable FEC */
514 ad_reg = XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_ADVERTISE + 2);
515 lp_reg = XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_LPA + 2);
517 reg = XMDIO_READ(pdata, MDIO_MMD_PMAPMD, MDIO_PMA_10GBR_FECCTRL);
518 reg &= ~(MDIO_PMA_10GBR_FECABLE_ABLE | MDIO_PMA_10GBR_FECABLE_ERRABLE);
519 if ((ad_reg & 0xc000) && (lp_reg & 0xc000))
520 reg |= pdata->fec_ability;
522 XMDIO_WRITE(pdata, MDIO_MMD_PMAPMD, MDIO_PMA_10GBR_FECCTRL, reg);
524 /* Start KR training */
525 reg = XMDIO_READ(pdata, MDIO_MMD_PMAPMD, MDIO_PMA_10GBR_PMD_CTRL);
526 if (reg & XGBE_KR_TRAINING_ENABLE) {
527 if (pdata->phy_if.phy_impl.kr_training_pre)
528 pdata->phy_if.phy_impl.kr_training_pre(pdata);
530 reg |= XGBE_KR_TRAINING_START;
531 XMDIO_WRITE(pdata, MDIO_MMD_PMAPMD, MDIO_PMA_10GBR_PMD_CTRL,
534 netif_dbg(pdata, link, pdata->netdev,
535 "KR training initiated\n");
537 if (pdata->phy_if.phy_impl.kr_training_post)
538 pdata->phy_if.phy_impl.kr_training_post(pdata);
541 return XGBE_AN_PAGE_RECEIVED;
544 static enum xgbe_an xgbe_an73_tx_xnp(struct xgbe_prv_data *pdata,
549 *state = XGBE_RX_XNP;
551 msg = XGBE_XNP_MCF_NULL_MESSAGE;
552 msg |= XGBE_XNP_MP_FORMATTED;
554 XMDIO_WRITE(pdata, MDIO_MMD_AN, MDIO_AN_XNP + 2, 0);
555 XMDIO_WRITE(pdata, MDIO_MMD_AN, MDIO_AN_XNP + 1, 0);
556 XMDIO_WRITE(pdata, MDIO_MMD_AN, MDIO_AN_XNP, msg);
558 return XGBE_AN_PAGE_RECEIVED;
561 static enum xgbe_an xgbe_an73_rx_bpa(struct xgbe_prv_data *pdata,
564 unsigned int link_support;
565 unsigned int reg, ad_reg, lp_reg;
567 /* Read Base Ability register 2 first */
568 reg = XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_LPA + 1);
570 /* Check for a supported mode, otherwise restart in a different one */
571 link_support = xgbe_in_kr_mode(pdata) ? 0x80 : 0x20;
572 if (!(reg & link_support))
573 return XGBE_AN_INCOMPAT_LINK;
575 /* Check Extended Next Page support */
576 ad_reg = XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_ADVERTISE);
577 lp_reg = XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_LPA);
579 return ((ad_reg & XGBE_XNP_NP_EXCHANGE) ||
580 (lp_reg & XGBE_XNP_NP_EXCHANGE))
581 ? xgbe_an73_tx_xnp(pdata, state)
582 : xgbe_an73_tx_training(pdata, state);
585 static enum xgbe_an xgbe_an73_rx_xnp(struct xgbe_prv_data *pdata,
588 unsigned int ad_reg, lp_reg;
590 /* Check Extended Next Page support */
591 ad_reg = XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_XNP);
592 lp_reg = XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_LPX);
594 return ((ad_reg & XGBE_XNP_NP_EXCHANGE) ||
595 (lp_reg & XGBE_XNP_NP_EXCHANGE))
596 ? xgbe_an73_tx_xnp(pdata, state)
597 : xgbe_an73_tx_training(pdata, state);
600 static enum xgbe_an xgbe_an73_page_received(struct xgbe_prv_data *pdata)
603 unsigned long an_timeout;
606 if (!pdata->an_start) {
607 pdata->an_start = jiffies;
609 an_timeout = pdata->an_start +
610 msecs_to_jiffies(XGBE_AN_MS_TIMEOUT);
611 if (time_after(jiffies, an_timeout)) {
612 /* Auto-negotiation timed out, reset state */
613 pdata->kr_state = XGBE_RX_BPA;
614 pdata->kx_state = XGBE_RX_BPA;
616 pdata->an_start = jiffies;
618 netif_dbg(pdata, link, pdata->netdev,
619 "CL73 AN timed out, resetting state\n");
623 state = xgbe_in_kr_mode(pdata) ? &pdata->kr_state
628 ret = xgbe_an73_rx_bpa(pdata, state);
632 ret = xgbe_an73_rx_xnp(pdata, state);
642 static enum xgbe_an xgbe_an73_incompat_link(struct xgbe_prv_data *pdata)
644 struct ethtool_link_ksettings *lks = &pdata->phy.lks;
646 /* Be sure we aren't looping trying to negotiate */
647 if (xgbe_in_kr_mode(pdata)) {
648 pdata->kr_state = XGBE_RX_ERROR;
650 if (!XGBE_ADV(lks, 1000baseKX_Full) &&
651 !XGBE_ADV(lks, 2500baseX_Full))
652 return XGBE_AN_NO_LINK;
654 if (pdata->kx_state != XGBE_RX_BPA)
655 return XGBE_AN_NO_LINK;
657 pdata->kx_state = XGBE_RX_ERROR;
659 if (!XGBE_ADV(lks, 10000baseKR_Full))
660 return XGBE_AN_NO_LINK;
662 if (pdata->kr_state != XGBE_RX_BPA)
663 return XGBE_AN_NO_LINK;
666 xgbe_an_disable(pdata);
668 xgbe_switch_mode(pdata);
670 xgbe_an_restart(pdata);
672 return XGBE_AN_INCOMPAT_LINK;
675 static void xgbe_an37_isr(struct xgbe_prv_data *pdata)
679 /* Disable AN interrupts */
680 xgbe_an37_disable_interrupts(pdata);
682 /* Save the interrupt(s) that fired */
683 reg = XMDIO_READ(pdata, MDIO_MMD_VEND2, MDIO_VEND2_AN_STAT);
684 pdata->an_int = reg & XGBE_AN_CL37_INT_MASK;
685 pdata->an_status = reg & ~XGBE_AN_CL37_INT_MASK;
688 /* Clear the interrupt(s) that fired and process them */
689 reg &= ~XGBE_AN_CL37_INT_MASK;
690 XMDIO_WRITE(pdata, MDIO_MMD_VEND2, MDIO_VEND2_AN_STAT, reg);
692 queue_work(pdata->an_workqueue, &pdata->an_irq_work);
694 /* Enable AN interrupts */
695 xgbe_an37_enable_interrupts(pdata);
697 /* Reissue interrupt if status is not clear */
698 if (pdata->vdata->irq_reissue_support)
699 XP_IOWRITE(pdata, XP_INT_REISSUE_EN, 1 << 3);
703 static void xgbe_an73_isr(struct xgbe_prv_data *pdata)
705 /* Disable AN interrupts */
706 xgbe_an73_disable_interrupts(pdata);
708 /* Save the interrupt(s) that fired */
709 pdata->an_int = XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_INT);
712 /* Clear the interrupt(s) that fired and process them */
713 XMDIO_WRITE(pdata, MDIO_MMD_AN, MDIO_AN_INT, ~pdata->an_int);
715 queue_work(pdata->an_workqueue, &pdata->an_irq_work);
717 /* Enable AN interrupts */
718 xgbe_an73_enable_interrupts(pdata);
720 /* Reissue interrupt if status is not clear */
721 if (pdata->vdata->irq_reissue_support)
722 XP_IOWRITE(pdata, XP_INT_REISSUE_EN, 1 << 3);
726 static void xgbe_an_isr_task(unsigned long data)
728 struct xgbe_prv_data *pdata = (struct xgbe_prv_data *)data;
730 netif_dbg(pdata, intr, pdata->netdev, "AN interrupt received\n");
732 switch (pdata->an_mode) {
733 case XGBE_AN_MODE_CL73:
734 case XGBE_AN_MODE_CL73_REDRV:
735 xgbe_an73_isr(pdata);
737 case XGBE_AN_MODE_CL37:
738 case XGBE_AN_MODE_CL37_SGMII:
739 xgbe_an37_isr(pdata);
746 static irqreturn_t xgbe_an_isr(int irq, void *data)
748 struct xgbe_prv_data *pdata = (struct xgbe_prv_data *)data;
750 if (pdata->isr_as_tasklet)
751 tasklet_schedule(&pdata->tasklet_an);
753 xgbe_an_isr_task((unsigned long)pdata);
758 static irqreturn_t xgbe_an_combined_isr(struct xgbe_prv_data *pdata)
760 xgbe_an_isr_task((unsigned long)pdata);
765 static void xgbe_an_irq_work(struct work_struct *work)
767 struct xgbe_prv_data *pdata = container_of(work,
768 struct xgbe_prv_data,
771 /* Avoid a race between enabling the IRQ and exiting the work by
772 * waiting for the work to finish and then queueing it
774 flush_work(&pdata->an_work);
775 queue_work(pdata->an_workqueue, &pdata->an_work);
778 static const char *xgbe_state_as_string(enum xgbe_an state)
783 case XGBE_AN_PAGE_RECEIVED:
784 return "Page-Received";
785 case XGBE_AN_INCOMPAT_LINK:
786 return "Incompatible-Link";
787 case XGBE_AN_COMPLETE:
789 case XGBE_AN_NO_LINK:
798 static void xgbe_an37_state_machine(struct xgbe_prv_data *pdata)
800 enum xgbe_an cur_state = pdata->an_state;
805 if (pdata->an_int & XGBE_AN_CL37_INT_CMPLT) {
806 pdata->an_state = XGBE_AN_COMPLETE;
807 pdata->an_int &= ~XGBE_AN_CL37_INT_CMPLT;
809 /* If SGMII is enabled, check the link status */
810 if ((pdata->an_mode == XGBE_AN_MODE_CL37_SGMII) &&
811 !(pdata->an_status & XGBE_SGMII_AN_LINK_STATUS))
812 pdata->an_state = XGBE_AN_NO_LINK;
815 netif_dbg(pdata, link, pdata->netdev, "CL37 AN %s\n",
816 xgbe_state_as_string(pdata->an_state));
818 cur_state = pdata->an_state;
820 switch (pdata->an_state) {
824 case XGBE_AN_COMPLETE:
825 netif_dbg(pdata, link, pdata->netdev,
826 "Auto negotiation successful\n");
829 case XGBE_AN_NO_LINK:
833 pdata->an_state = XGBE_AN_ERROR;
836 if (pdata->an_state == XGBE_AN_ERROR) {
837 netdev_err(pdata->netdev,
838 "error during auto-negotiation, state=%u\n",
842 xgbe_an37_clear_interrupts(pdata);
845 if (pdata->an_state >= XGBE_AN_COMPLETE) {
846 pdata->an_result = pdata->an_state;
847 pdata->an_state = XGBE_AN_READY;
849 if (pdata->phy_if.phy_impl.an_post)
850 pdata->phy_if.phy_impl.an_post(pdata);
852 netif_dbg(pdata, link, pdata->netdev, "CL37 AN result: %s\n",
853 xgbe_state_as_string(pdata->an_result));
856 xgbe_an37_enable_interrupts(pdata);
859 static void xgbe_an73_state_machine(struct xgbe_prv_data *pdata)
861 enum xgbe_an cur_state = pdata->an_state;
867 if (pdata->an_int & XGBE_AN_CL73_PG_RCV) {
868 pdata->an_state = XGBE_AN_PAGE_RECEIVED;
869 pdata->an_int &= ~XGBE_AN_CL73_PG_RCV;
870 } else if (pdata->an_int & XGBE_AN_CL73_INC_LINK) {
871 pdata->an_state = XGBE_AN_INCOMPAT_LINK;
872 pdata->an_int &= ~XGBE_AN_CL73_INC_LINK;
873 } else if (pdata->an_int & XGBE_AN_CL73_INT_CMPLT) {
874 pdata->an_state = XGBE_AN_COMPLETE;
875 pdata->an_int &= ~XGBE_AN_CL73_INT_CMPLT;
877 pdata->an_state = XGBE_AN_ERROR;
881 netif_dbg(pdata, link, pdata->netdev, "CL73 AN %s\n",
882 xgbe_state_as_string(pdata->an_state));
884 cur_state = pdata->an_state;
886 switch (pdata->an_state) {
888 pdata->an_supported = 0;
891 case XGBE_AN_PAGE_RECEIVED:
892 pdata->an_state = xgbe_an73_page_received(pdata);
893 pdata->an_supported++;
896 case XGBE_AN_INCOMPAT_LINK:
897 pdata->an_supported = 0;
898 pdata->parallel_detect = 0;
899 pdata->an_state = xgbe_an73_incompat_link(pdata);
902 case XGBE_AN_COMPLETE:
903 pdata->parallel_detect = pdata->an_supported ? 0 : 1;
904 netif_dbg(pdata, link, pdata->netdev, "%s successful\n",
905 pdata->an_supported ? "Auto negotiation"
906 : "Parallel detection");
909 case XGBE_AN_NO_LINK:
913 pdata->an_state = XGBE_AN_ERROR;
916 if (pdata->an_state == XGBE_AN_NO_LINK) {
918 xgbe_an73_clear_interrupts(pdata);
919 } else if (pdata->an_state == XGBE_AN_ERROR) {
920 netdev_err(pdata->netdev,
921 "error during auto-negotiation, state=%u\n",
925 xgbe_an73_clear_interrupts(pdata);
928 if (pdata->an_state >= XGBE_AN_COMPLETE) {
929 pdata->an_result = pdata->an_state;
930 pdata->an_state = XGBE_AN_READY;
931 pdata->kr_state = XGBE_RX_BPA;
932 pdata->kx_state = XGBE_RX_BPA;
935 if (pdata->phy_if.phy_impl.an_post)
936 pdata->phy_if.phy_impl.an_post(pdata);
938 netif_dbg(pdata, link, pdata->netdev, "CL73 AN result: %s\n",
939 xgbe_state_as_string(pdata->an_result));
942 if (cur_state != pdata->an_state)
948 xgbe_an73_enable_interrupts(pdata);
951 static void xgbe_an_state_machine(struct work_struct *work)
953 struct xgbe_prv_data *pdata = container_of(work,
954 struct xgbe_prv_data,
957 mutex_lock(&pdata->an_mutex);
959 switch (pdata->an_mode) {
960 case XGBE_AN_MODE_CL73:
961 case XGBE_AN_MODE_CL73_REDRV:
962 xgbe_an73_state_machine(pdata);
964 case XGBE_AN_MODE_CL37:
965 case XGBE_AN_MODE_CL37_SGMII:
966 xgbe_an37_state_machine(pdata);
972 /* Reissue interrupt if status is not clear */
973 if (pdata->vdata->irq_reissue_support)
974 XP_IOWRITE(pdata, XP_INT_REISSUE_EN, 1 << 3);
976 mutex_unlock(&pdata->an_mutex);
979 static void xgbe_an37_init(struct xgbe_prv_data *pdata)
981 struct ethtool_link_ksettings lks;
984 pdata->phy_if.phy_impl.an_advertising(pdata, &lks);
986 /* Set up Advertisement register */
987 reg = XMDIO_READ(pdata, MDIO_MMD_VEND2, MDIO_VEND2_AN_ADVERTISE);
988 if (XGBE_ADV(&lks, Pause))
993 if (XGBE_ADV(&lks, Asym_Pause))
998 /* Full duplex, but not half */
999 reg |= XGBE_AN_CL37_FD_MASK;
1000 reg &= ~XGBE_AN_CL37_HD_MASK;
1002 XMDIO_WRITE(pdata, MDIO_MMD_VEND2, MDIO_VEND2_AN_ADVERTISE, reg);
1004 /* Set up the Control register */
1005 reg = XMDIO_READ(pdata, MDIO_MMD_VEND2, MDIO_VEND2_AN_CTRL);
1006 reg &= ~XGBE_AN_CL37_TX_CONFIG_MASK;
1007 reg &= ~XGBE_AN_CL37_PCS_MODE_MASK;
1009 switch (pdata->an_mode) {
1010 case XGBE_AN_MODE_CL37:
1011 reg |= XGBE_AN_CL37_PCS_MODE_BASEX;
1013 case XGBE_AN_MODE_CL37_SGMII:
1014 reg |= XGBE_AN_CL37_PCS_MODE_SGMII;
1020 reg |= XGBE_AN_CL37_MII_CTRL_8BIT;
1022 XMDIO_WRITE(pdata, MDIO_MMD_VEND2, MDIO_VEND2_AN_CTRL, reg);
1024 netif_dbg(pdata, link, pdata->netdev, "CL37 AN (%s) initialized\n",
1025 (pdata->an_mode == XGBE_AN_MODE_CL37) ? "BaseX" : "SGMII");
1028 static void xgbe_an73_init(struct xgbe_prv_data *pdata)
1030 struct ethtool_link_ksettings lks;
1033 pdata->phy_if.phy_impl.an_advertising(pdata, &lks);
1035 /* Set up Advertisement register 3 first */
1036 reg = XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_ADVERTISE + 2);
1037 if (XGBE_ADV(&lks, 10000baseR_FEC))
1042 XMDIO_WRITE(pdata, MDIO_MMD_AN, MDIO_AN_ADVERTISE + 2, reg);
1044 /* Set up Advertisement register 2 next */
1045 reg = XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_ADVERTISE + 1);
1046 if (XGBE_ADV(&lks, 10000baseKR_Full))
1051 if (XGBE_ADV(&lks, 1000baseKX_Full) ||
1052 XGBE_ADV(&lks, 2500baseX_Full))
1057 XMDIO_WRITE(pdata, MDIO_MMD_AN, MDIO_AN_ADVERTISE + 1, reg);
1059 /* Set up Advertisement register 1 last */
1060 reg = XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_ADVERTISE);
1061 if (XGBE_ADV(&lks, Pause))
1066 if (XGBE_ADV(&lks, Asym_Pause))
1071 /* We don't intend to perform XNP */
1072 reg &= ~XGBE_XNP_NP_EXCHANGE;
1074 XMDIO_WRITE(pdata, MDIO_MMD_AN, MDIO_AN_ADVERTISE, reg);
1076 netif_dbg(pdata, link, pdata->netdev, "CL73 AN initialized\n");
1079 static void xgbe_an_init(struct xgbe_prv_data *pdata)
1081 /* Set up advertisement registers based on current settings */
1082 pdata->an_mode = pdata->phy_if.phy_impl.an_mode(pdata);
1083 switch (pdata->an_mode) {
1084 case XGBE_AN_MODE_CL73:
1085 case XGBE_AN_MODE_CL73_REDRV:
1086 xgbe_an73_init(pdata);
1088 case XGBE_AN_MODE_CL37:
1089 case XGBE_AN_MODE_CL37_SGMII:
1090 xgbe_an37_init(pdata);
1097 static const char *xgbe_phy_fc_string(struct xgbe_prv_data *pdata)
1099 if (pdata->tx_pause && pdata->rx_pause)
1101 else if (pdata->rx_pause)
1103 else if (pdata->tx_pause)
1109 static const char *xgbe_phy_speed_string(int speed)
1123 return "Unsupported";
1127 static void xgbe_phy_print_status(struct xgbe_prv_data *pdata)
1129 if (pdata->phy.link)
1130 netdev_info(pdata->netdev,
1131 "Link is Up - %s/%s - flow control %s\n",
1132 xgbe_phy_speed_string(pdata->phy.speed),
1133 pdata->phy.duplex == DUPLEX_FULL ? "Full" : "Half",
1134 xgbe_phy_fc_string(pdata));
1136 netdev_info(pdata->netdev, "Link is Down\n");
1139 static void xgbe_phy_adjust_link(struct xgbe_prv_data *pdata)
1143 if (pdata->phy.link) {
1144 /* Flow control support */
1145 pdata->pause_autoneg = pdata->phy.pause_autoneg;
1147 if (pdata->tx_pause != pdata->phy.tx_pause) {
1149 pdata->hw_if.config_tx_flow_control(pdata);
1150 pdata->tx_pause = pdata->phy.tx_pause;
1153 if (pdata->rx_pause != pdata->phy.rx_pause) {
1155 pdata->hw_if.config_rx_flow_control(pdata);
1156 pdata->rx_pause = pdata->phy.rx_pause;
1160 if (pdata->phy_speed != pdata->phy.speed) {
1162 pdata->phy_speed = pdata->phy.speed;
1165 if (pdata->phy_link != pdata->phy.link) {
1167 pdata->phy_link = pdata->phy.link;
1169 } else if (pdata->phy_link) {
1171 pdata->phy_link = 0;
1172 pdata->phy_speed = SPEED_UNKNOWN;
1175 if (new_state && netif_msg_link(pdata))
1176 xgbe_phy_print_status(pdata);
1179 static bool xgbe_phy_valid_speed(struct xgbe_prv_data *pdata, int speed)
1181 return pdata->phy_if.phy_impl.valid_speed(pdata, speed);
1184 static int xgbe_phy_config_fixed(struct xgbe_prv_data *pdata)
1186 enum xgbe_mode mode;
1188 netif_dbg(pdata, link, pdata->netdev, "fixed PHY configuration\n");
1190 /* Disable auto-negotiation */
1191 xgbe_an_disable(pdata);
1193 /* Set specified mode for specified speed */
1194 mode = pdata->phy_if.phy_impl.get_mode(pdata, pdata->phy.speed);
1196 case XGBE_MODE_KX_1000:
1197 case XGBE_MODE_KX_2500:
1199 case XGBE_MODE_SGMII_100:
1200 case XGBE_MODE_SGMII_1000:
1204 case XGBE_MODE_UNKNOWN:
1209 /* Validate duplex mode */
1210 if (pdata->phy.duplex != DUPLEX_FULL)
1213 xgbe_set_mode(pdata, mode);
1218 static int __xgbe_phy_config_aneg(struct xgbe_prv_data *pdata)
1222 set_bit(XGBE_LINK_INIT, &pdata->dev_state);
1223 pdata->link_check = jiffies;
1225 ret = pdata->phy_if.phy_impl.an_config(pdata);
1229 if (pdata->phy.autoneg != AUTONEG_ENABLE) {
1230 ret = xgbe_phy_config_fixed(pdata);
1231 if (ret || !pdata->kr_redrv)
1234 netif_dbg(pdata, link, pdata->netdev, "AN redriver support\n");
1236 netif_dbg(pdata, link, pdata->netdev, "AN PHY configuration\n");
1239 /* Disable auto-negotiation interrupt */
1240 disable_irq(pdata->an_irq);
1242 /* Start auto-negotiation in a supported mode */
1243 if (xgbe_use_mode(pdata, XGBE_MODE_KR)) {
1244 xgbe_set_mode(pdata, XGBE_MODE_KR);
1245 } else if (xgbe_use_mode(pdata, XGBE_MODE_KX_2500)) {
1246 xgbe_set_mode(pdata, XGBE_MODE_KX_2500);
1247 } else if (xgbe_use_mode(pdata, XGBE_MODE_KX_1000)) {
1248 xgbe_set_mode(pdata, XGBE_MODE_KX_1000);
1249 } else if (xgbe_use_mode(pdata, XGBE_MODE_SFI)) {
1250 xgbe_set_mode(pdata, XGBE_MODE_SFI);
1251 } else if (xgbe_use_mode(pdata, XGBE_MODE_X)) {
1252 xgbe_set_mode(pdata, XGBE_MODE_X);
1253 } else if (xgbe_use_mode(pdata, XGBE_MODE_SGMII_1000)) {
1254 xgbe_set_mode(pdata, XGBE_MODE_SGMII_1000);
1255 } else if (xgbe_use_mode(pdata, XGBE_MODE_SGMII_100)) {
1256 xgbe_set_mode(pdata, XGBE_MODE_SGMII_100);
1258 enable_irq(pdata->an_irq);
1262 /* Disable and stop any in progress auto-negotiation */
1263 xgbe_an_disable_all(pdata);
1265 /* Clear any auto-negotitation interrupts */
1266 xgbe_an_clear_interrupts_all(pdata);
1268 pdata->an_result = XGBE_AN_READY;
1269 pdata->an_state = XGBE_AN_READY;
1270 pdata->kr_state = XGBE_RX_BPA;
1271 pdata->kx_state = XGBE_RX_BPA;
1273 /* Re-enable auto-negotiation interrupt */
1274 enable_irq(pdata->an_irq);
1276 xgbe_an_init(pdata);
1277 xgbe_an_restart(pdata);
1282 static int xgbe_phy_config_aneg(struct xgbe_prv_data *pdata)
1286 mutex_lock(&pdata->an_mutex);
1288 ret = __xgbe_phy_config_aneg(pdata);
1290 set_bit(XGBE_LINK_ERR, &pdata->dev_state);
1292 clear_bit(XGBE_LINK_ERR, &pdata->dev_state);
1294 mutex_unlock(&pdata->an_mutex);
1299 static bool xgbe_phy_aneg_done(struct xgbe_prv_data *pdata)
1301 return (pdata->an_result == XGBE_AN_COMPLETE);
1304 static void xgbe_check_link_timeout(struct xgbe_prv_data *pdata)
1306 unsigned long link_timeout;
1308 link_timeout = pdata->link_check + (XGBE_LINK_TIMEOUT * HZ);
1309 if (time_after(jiffies, link_timeout)) {
1310 netif_dbg(pdata, link, pdata->netdev, "AN link timeout\n");
1311 xgbe_phy_config_aneg(pdata);
1315 static enum xgbe_mode xgbe_phy_status_aneg(struct xgbe_prv_data *pdata)
1317 return pdata->phy_if.phy_impl.an_outcome(pdata);
1320 static void xgbe_phy_status_result(struct xgbe_prv_data *pdata)
1322 struct ethtool_link_ksettings *lks = &pdata->phy.lks;
1323 enum xgbe_mode mode;
1325 XGBE_ZERO_LP_ADV(lks);
1327 if ((pdata->phy.autoneg != AUTONEG_ENABLE) || pdata->parallel_detect)
1328 mode = xgbe_cur_mode(pdata);
1330 mode = xgbe_phy_status_aneg(pdata);
1333 case XGBE_MODE_SGMII_100:
1334 pdata->phy.speed = SPEED_100;
1337 case XGBE_MODE_KX_1000:
1338 case XGBE_MODE_SGMII_1000:
1339 pdata->phy.speed = SPEED_1000;
1341 case XGBE_MODE_KX_2500:
1342 pdata->phy.speed = SPEED_2500;
1346 pdata->phy.speed = SPEED_10000;
1348 case XGBE_MODE_UNKNOWN:
1350 pdata->phy.speed = SPEED_UNKNOWN;
1353 pdata->phy.duplex = DUPLEX_FULL;
1355 xgbe_set_mode(pdata, mode);
1358 static void xgbe_phy_status(struct xgbe_prv_data *pdata)
1360 unsigned int link_aneg;
1363 if (test_bit(XGBE_LINK_ERR, &pdata->dev_state)) {
1364 netif_carrier_off(pdata->netdev);
1366 pdata->phy.link = 0;
1370 link_aneg = (pdata->phy.autoneg == AUTONEG_ENABLE);
1372 pdata->phy.link = pdata->phy_if.phy_impl.link_status(pdata,
1375 xgbe_phy_config_aneg(pdata);
1379 if (pdata->phy.link) {
1380 if (link_aneg && !xgbe_phy_aneg_done(pdata)) {
1381 xgbe_check_link_timeout(pdata);
1385 xgbe_phy_status_result(pdata);
1387 if (test_bit(XGBE_LINK_INIT, &pdata->dev_state))
1388 clear_bit(XGBE_LINK_INIT, &pdata->dev_state);
1390 netif_carrier_on(pdata->netdev);
1392 if (test_bit(XGBE_LINK_INIT, &pdata->dev_state)) {
1393 xgbe_check_link_timeout(pdata);
1399 xgbe_phy_status_result(pdata);
1401 netif_carrier_off(pdata->netdev);
1405 xgbe_phy_adjust_link(pdata);
1408 static void xgbe_phy_stop(struct xgbe_prv_data *pdata)
1410 netif_dbg(pdata, link, pdata->netdev, "stopping PHY\n");
1412 if (!pdata->phy_started)
1415 /* Indicate the PHY is down */
1416 pdata->phy_started = 0;
1418 /* Disable auto-negotiation */
1419 xgbe_an_disable_all(pdata);
1421 if (pdata->dev_irq != pdata->an_irq)
1422 devm_free_irq(pdata->dev, pdata->an_irq, pdata);
1424 pdata->phy_if.phy_impl.stop(pdata);
1426 pdata->phy.link = 0;
1427 netif_carrier_off(pdata->netdev);
1429 xgbe_phy_adjust_link(pdata);
1432 static int xgbe_phy_start(struct xgbe_prv_data *pdata)
1434 struct net_device *netdev = pdata->netdev;
1437 netif_dbg(pdata, link, pdata->netdev, "starting PHY\n");
1439 ret = pdata->phy_if.phy_impl.start(pdata);
1443 /* If we have a separate AN irq, enable it */
1444 if (pdata->dev_irq != pdata->an_irq) {
1445 tasklet_init(&pdata->tasklet_an, xgbe_an_isr_task,
1446 (unsigned long)pdata);
1448 ret = devm_request_irq(pdata->dev, pdata->an_irq,
1449 xgbe_an_isr, 0, pdata->an_name,
1452 netdev_err(netdev, "phy irq request failed\n");
1457 /* Set initial mode - call the mode setting routines
1458 * directly to insure we are properly configured
1460 if (xgbe_use_mode(pdata, XGBE_MODE_KR)) {
1461 xgbe_kr_mode(pdata);
1462 } else if (xgbe_use_mode(pdata, XGBE_MODE_KX_2500)) {
1463 xgbe_kx_2500_mode(pdata);
1464 } else if (xgbe_use_mode(pdata, XGBE_MODE_KX_1000)) {
1465 xgbe_kx_1000_mode(pdata);
1466 } else if (xgbe_use_mode(pdata, XGBE_MODE_SFI)) {
1467 xgbe_sfi_mode(pdata);
1468 } else if (xgbe_use_mode(pdata, XGBE_MODE_X)) {
1470 } else if (xgbe_use_mode(pdata, XGBE_MODE_SGMII_1000)) {
1471 xgbe_sgmii_1000_mode(pdata);
1472 } else if (xgbe_use_mode(pdata, XGBE_MODE_SGMII_100)) {
1473 xgbe_sgmii_100_mode(pdata);
1479 /* Indicate the PHY is up and running */
1480 pdata->phy_started = 1;
1482 xgbe_an_init(pdata);
1483 xgbe_an_enable_interrupts(pdata);
1485 return xgbe_phy_config_aneg(pdata);
1488 if (pdata->dev_irq != pdata->an_irq)
1489 devm_free_irq(pdata->dev, pdata->an_irq, pdata);
1492 pdata->phy_if.phy_impl.stop(pdata);
1497 static int xgbe_phy_reset(struct xgbe_prv_data *pdata)
1501 ret = pdata->phy_if.phy_impl.reset(pdata);
1505 /* Disable auto-negotiation for now */
1506 xgbe_an_disable_all(pdata);
1508 /* Clear auto-negotiation interrupts */
1509 xgbe_an_clear_interrupts_all(pdata);
1514 static void xgbe_dump_phy_registers(struct xgbe_prv_data *pdata)
1516 struct device *dev = pdata->dev;
1518 dev_dbg(dev, "\n************* PHY Reg dump **********************\n");
1520 dev_dbg(dev, "PCS Control Reg (%#06x) = %#06x\n", MDIO_CTRL1,
1521 XMDIO_READ(pdata, MDIO_MMD_PCS, MDIO_CTRL1));
1522 dev_dbg(dev, "PCS Status Reg (%#06x) = %#06x\n", MDIO_STAT1,
1523 XMDIO_READ(pdata, MDIO_MMD_PCS, MDIO_STAT1));
1524 dev_dbg(dev, "Phy Id (PHYS ID 1 %#06x)= %#06x\n", MDIO_DEVID1,
1525 XMDIO_READ(pdata, MDIO_MMD_PCS, MDIO_DEVID1));
1526 dev_dbg(dev, "Phy Id (PHYS ID 2 %#06x)= %#06x\n", MDIO_DEVID2,
1527 XMDIO_READ(pdata, MDIO_MMD_PCS, MDIO_DEVID2));
1528 dev_dbg(dev, "Devices in Package (%#06x)= %#06x\n", MDIO_DEVS1,
1529 XMDIO_READ(pdata, MDIO_MMD_PCS, MDIO_DEVS1));
1530 dev_dbg(dev, "Devices in Package (%#06x)= %#06x\n", MDIO_DEVS2,
1531 XMDIO_READ(pdata, MDIO_MMD_PCS, MDIO_DEVS2));
1533 dev_dbg(dev, "Auto-Neg Control Reg (%#06x) = %#06x\n", MDIO_CTRL1,
1534 XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_CTRL1));
1535 dev_dbg(dev, "Auto-Neg Status Reg (%#06x) = %#06x\n", MDIO_STAT1,
1536 XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_STAT1));
1537 dev_dbg(dev, "Auto-Neg Ad Reg 1 (%#06x) = %#06x\n",
1539 XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_ADVERTISE));
1540 dev_dbg(dev, "Auto-Neg Ad Reg 2 (%#06x) = %#06x\n",
1541 MDIO_AN_ADVERTISE + 1,
1542 XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_ADVERTISE + 1));
1543 dev_dbg(dev, "Auto-Neg Ad Reg 3 (%#06x) = %#06x\n",
1544 MDIO_AN_ADVERTISE + 2,
1545 XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_ADVERTISE + 2));
1546 dev_dbg(dev, "Auto-Neg Completion Reg (%#06x) = %#06x\n",
1548 XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_COMP_STAT));
1550 dev_dbg(dev, "\n*************************************************\n");
1553 static int xgbe_phy_best_advertised_speed(struct xgbe_prv_data *pdata)
1555 struct ethtool_link_ksettings *lks = &pdata->phy.lks;
1557 if (XGBE_ADV(lks, 10000baseKR_Full))
1559 else if (XGBE_ADV(lks, 10000baseT_Full))
1561 else if (XGBE_ADV(lks, 2500baseX_Full))
1563 else if (XGBE_ADV(lks, 2500baseT_Full))
1565 else if (XGBE_ADV(lks, 1000baseKX_Full))
1567 else if (XGBE_ADV(lks, 1000baseT_Full))
1569 else if (XGBE_ADV(lks, 100baseT_Full))
1572 return SPEED_UNKNOWN;
1575 static void xgbe_phy_exit(struct xgbe_prv_data *pdata)
1577 pdata->phy_if.phy_impl.exit(pdata);
1580 static int xgbe_phy_init(struct xgbe_prv_data *pdata)
1582 struct ethtool_link_ksettings *lks = &pdata->phy.lks;
1585 mutex_init(&pdata->an_mutex);
1586 INIT_WORK(&pdata->an_irq_work, xgbe_an_irq_work);
1587 INIT_WORK(&pdata->an_work, xgbe_an_state_machine);
1588 pdata->mdio_mmd = MDIO_MMD_PCS;
1590 /* Check for FEC support */
1591 pdata->fec_ability = XMDIO_READ(pdata, MDIO_MMD_PMAPMD,
1592 MDIO_PMA_10GBR_FECABLE);
1593 pdata->fec_ability &= (MDIO_PMA_10GBR_FECABLE_ABLE |
1594 MDIO_PMA_10GBR_FECABLE_ERRABLE);
1596 /* Setup the phy (including supported features) */
1597 ret = pdata->phy_if.phy_impl.init(pdata);
1601 /* Copy supported link modes to advertising link modes */
1602 XGBE_LM_COPY(lks, advertising, lks, supported);
1604 pdata->phy.address = 0;
1606 if (XGBE_ADV(lks, Autoneg)) {
1607 pdata->phy.autoneg = AUTONEG_ENABLE;
1608 pdata->phy.speed = SPEED_UNKNOWN;
1609 pdata->phy.duplex = DUPLEX_UNKNOWN;
1611 pdata->phy.autoneg = AUTONEG_DISABLE;
1612 pdata->phy.speed = xgbe_phy_best_advertised_speed(pdata);
1613 pdata->phy.duplex = DUPLEX_FULL;
1616 pdata->phy.link = 0;
1618 pdata->phy.pause_autoneg = pdata->pause_autoneg;
1619 pdata->phy.tx_pause = pdata->tx_pause;
1620 pdata->phy.rx_pause = pdata->rx_pause;
1622 /* Fix up Flow Control advertising */
1623 XGBE_CLR_ADV(lks, Pause);
1624 XGBE_CLR_ADV(lks, Asym_Pause);
1626 if (pdata->rx_pause) {
1627 XGBE_SET_ADV(lks, Pause);
1628 XGBE_SET_ADV(lks, Asym_Pause);
1631 if (pdata->tx_pause) {
1632 /* Equivalent to XOR of Asym_Pause */
1633 if (XGBE_ADV(lks, Asym_Pause))
1634 XGBE_CLR_ADV(lks, Asym_Pause);
1636 XGBE_SET_ADV(lks, Asym_Pause);
1639 if (netif_msg_drv(pdata))
1640 xgbe_dump_phy_registers(pdata);
1645 void xgbe_init_function_ptrs_phy(struct xgbe_phy_if *phy_if)
1647 phy_if->phy_init = xgbe_phy_init;
1648 phy_if->phy_exit = xgbe_phy_exit;
1650 phy_if->phy_reset = xgbe_phy_reset;
1651 phy_if->phy_start = xgbe_phy_start;
1652 phy_if->phy_stop = xgbe_phy_stop;
1654 phy_if->phy_status = xgbe_phy_status;
1655 phy_if->phy_config_aneg = xgbe_phy_config_aneg;
1657 phy_if->phy_valid_speed = xgbe_phy_valid_speed;
1659 phy_if->an_isr = xgbe_an_combined_isr;
1661 phy_if->module_info = xgbe_phy_module_info;
1662 phy_if->module_eeprom = xgbe_phy_module_eeprom;