drivers/net/ethernet/amd/pcnet32.c

   1 /* pcnet32.c: An AMD PCnet32 ethernet driver for linux. */
   2 /*
   3  *      Copyright 1996-1999 Thomas Bogendoerfer
   4  *
   5  *      Derived from the lance driver written 1993,1994,1995 by Donald Becker.
   6  *
   7  *      Copyright 1993 United States Government as represented by the
   8  *      Director, National Security Agency.
   9  *
  10  *      This software may be used and distributed according to the terms
  11  *      of the GNU General Public License, incorporated herein by reference.
  12  *
  13  *      This driver is for PCnet32 and PCnetPCI based ethercards
  14  */
  15 /**************************************************************************
  16  *  23 Oct, 2000.
  17  *  Fixed a few bugs, related to running the controller in 32bit mode.
  18  *
  19  *  Carsten Langgaard, carstenl@mips.com
  20  *  Copyright (C) 2000 MIPS Technologies, Inc.  All rights reserved.
  21  *
  22  *************************************************************************/
  23
  24 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
  25
  26 #define DRV_NAME        "pcnet32"
  27 #define DRV_RELDATE     "21.Apr.2008"
  28 #define PFX             DRV_NAME ": "
  29
  30 #include <linux/module.h>
  31 #include <linux/kernel.h>
  32 #include <linux/sched.h>
  33 #include <linux/string.h>
  34 #include <linux/errno.h>
  35 #include <linux/ioport.h>
  36 #include <linux/slab.h>
  37 #include <linux/interrupt.h>
  38 #include <linux/pci.h>
  39 #include <linux/delay.h>
  40 #include <linux/init.h>
  41 #include <linux/ethtool.h>
  42 #include <linux/mii.h>
  43 #include <linux/crc32.h>
  44 #include <linux/netdevice.h>
  45 #include <linux/etherdevice.h>
  46 #include <linux/if_ether.h>
  47 #include <linux/skbuff.h>
  48 #include <linux/spinlock.h>
  49 #include <linux/moduleparam.h>
  50 #include <linux/bitops.h>
  51 #include <linux/io.h>
  52 #include <linux/uaccess.h>
  53
  54 #include <asm/dma.h>
  55 #include <asm/irq.h>
  56
  57 /*
  58  * PCI device identifiers for "new style" Linux PCI Device Drivers
  59  */
  60 static const struct pci_device_id pcnet32_pci_tbl[] = {
  61         { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_LANCE_HOME), },
  62         { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_LANCE), },
  63
  64         /*
  65          * Adapters that were sold with IBM's RS/6000 or pSeries hardware have
  66          * the incorrect vendor id.
  67          */
  68         { PCI_DEVICE(PCI_VENDOR_ID_TRIDENT, PCI_DEVICE_ID_AMD_LANCE),
  69           .class = (PCI_CLASS_NETWORK_ETHERNET << 8), .class_mask = 0xffff00, },
  70
  71         { }     /* terminate list */
  72 };
  73
  74 MODULE_DEVICE_TABLE(pci, pcnet32_pci_tbl);
  75
  76 static int cards_found;
  77
  78 /*
  79  * VLB I/O addresses
  80  */
  81 static unsigned int pcnet32_portlist[] =
  82     { 0x300, 0x320, 0x340, 0x360, 0 };
  83
  84 static int pcnet32_debug;
  85 static int tx_start = 1;        /* Mapping -- 0:20, 1:64, 2:128, 3:~220 (depends on chip vers) */
  86 static int pcnet32vlb;          /* check for VLB cards ? */
  87
  88 static struct net_device *pcnet32_dev;
  89
  90 static int max_interrupt_work = 2;
  91 static int rx_copybreak = 200;
  92
  93 #define PCNET32_PORT_AUI      0x00
  94 #define PCNET32_PORT_10BT     0x01
  95 #define PCNET32_PORT_GPSI     0x02
  96 #define PCNET32_PORT_MII      0x03
  97
  98 #define PCNET32_PORT_PORTSEL  0x03
  99 #define PCNET32_PORT_ASEL     0x04
 100 #define PCNET32_PORT_100      0x40
 101 #define PCNET32_PORT_FD       0x80
 102
 103 #define PCNET32_DMA_MASK 0xffffffff
 104
 105 #define PCNET32_WATCHDOG_TIMEOUT (jiffies + (2 * HZ))
 106 #define PCNET32_BLINK_TIMEOUT   (jiffies + (HZ/4))
 107
 108 /*
 109  * table to translate option values from tulip
 110  * to internal options
 111  */
 112 static const unsigned char options_mapping[] = {
 113         PCNET32_PORT_ASEL,                      /*  0 Auto-select      */
 114         PCNET32_PORT_AUI,                       /*  1 BNC/AUI          */
 115         PCNET32_PORT_AUI,                       /*  2 AUI/BNC          */
 116         PCNET32_PORT_ASEL,                      /*  3 not supported    */
 117         PCNET32_PORT_10BT | PCNET32_PORT_FD,    /*  4 10baseT-FD       */
 118         PCNET32_PORT_ASEL,                      /*  5 not supported    */
 119         PCNET32_PORT_ASEL,                      /*  6 not supported    */
 120         PCNET32_PORT_ASEL,                      /*  7 not supported    */
 121         PCNET32_PORT_ASEL,                      /*  8 not supported    */
 122         PCNET32_PORT_MII,                       /*  9 MII 10baseT      */
 123         PCNET32_PORT_MII | PCNET32_PORT_FD,     /* 10 MII 10baseT-FD   */
 124         PCNET32_PORT_MII,                       /* 11 MII (autosel)    */
 125         PCNET32_PORT_10BT,                      /* 12 10BaseT          */
 126         PCNET32_PORT_MII | PCNET32_PORT_100,    /* 13 MII 100BaseTx    */
 127                                                 /* 14 MII 100BaseTx-FD */
 128         PCNET32_PORT_MII | PCNET32_PORT_100 | PCNET32_PORT_FD,
 129         PCNET32_PORT_ASEL                       /* 15 not supported    */
 130 };
 131
 132 static const char pcnet32_gstrings_test[][ETH_GSTRING_LEN] = {
 133         "Loopback test  (offline)"
 134 };
 135
 136 #define PCNET32_TEST_LEN        ARRAY_SIZE(pcnet32_gstrings_test)
 137
 138 #define PCNET32_NUM_REGS 136
 139
 140 #define MAX_UNITS 8             /* More are supported, limit only on options */
 141 static int options[MAX_UNITS];
 142 static int full_duplex[MAX_UNITS];
 143 static int homepna[MAX_UNITS];
 144
 145 /*
 146  *                              Theory of Operation
 147  *
 148  * This driver uses the same software structure as the normal lance
 149  * driver. So look for a verbose description in lance.c. The differences
 150  * to the normal lance driver is the use of the 32bit mode of PCnet32
 151  * and PCnetPCI chips. Because these chips are 32bit chips, there is no
 152  * 16MB limitation and we don't need bounce buffers.
 153  */
 154
 155 /*
 156  * Set the number of Tx and Rx buffers, using Log_2(# buffers).
 157  * Reasonable default values are 4 Tx buffers, and 16 Rx buffers.
 158  * That translates to 2 (4 == 2^^2) and 4 (16 == 2^^4).
 159  */
 160 #ifndef PCNET32_LOG_TX_BUFFERS
 161 #define PCNET32_LOG_TX_BUFFERS          4
 162 #define PCNET32_LOG_RX_BUFFERS          5
 163 #define PCNET32_LOG_MAX_TX_BUFFERS      9       /* 2^9 == 512 */
 164 #define PCNET32_LOG_MAX_RX_BUFFERS      9
 165 #endif
 166
 167 #define TX_RING_SIZE            (1 << (PCNET32_LOG_TX_BUFFERS))
 168 #define TX_MAX_RING_SIZE        (1 << (PCNET32_LOG_MAX_TX_BUFFERS))
 169
 170 #define RX_RING_SIZE            (1 << (PCNET32_LOG_RX_BUFFERS))
 171 #define RX_MAX_RING_SIZE        (1 << (PCNET32_LOG_MAX_RX_BUFFERS))
 172
 173 #define PKT_BUF_SKB             1544
 174 /* actual buffer length after being aligned */
 175 #define PKT_BUF_SIZE            (PKT_BUF_SKB - NET_IP_ALIGN)
 176 /* chip wants twos complement of the (aligned) buffer length */
 177 #define NEG_BUF_SIZE            (NET_IP_ALIGN - PKT_BUF_SKB)
 178
 179 /* Offsets from base I/O address. */
 180 #define PCNET32_WIO_RDP         0x10
 181 #define PCNET32_WIO_RAP         0x12
 182 #define PCNET32_WIO_RESET       0x14
 183 #define PCNET32_WIO_BDP         0x16
 184
 185 #define PCNET32_DWIO_RDP        0x10
 186 #define PCNET32_DWIO_RAP        0x14
 187 #define PCNET32_DWIO_RESET      0x18
 188 #define PCNET32_DWIO_BDP        0x1C
 189
 190 #define PCNET32_TOTAL_SIZE      0x20
 191
 192 #define CSR0            0
 193 #define CSR0_INIT       0x1
 194 #define CSR0_START      0x2
 195 #define CSR0_STOP       0x4
 196 #define CSR0_TXPOLL     0x8
 197 #define CSR0_INTEN      0x40
 198 #define CSR0_IDON       0x0100
 199 #define CSR0_NORMAL     (CSR0_START | CSR0_INTEN)
 200 #define PCNET32_INIT_LOW        1
 201 #define PCNET32_INIT_HIGH       2
 202 #define CSR3            3
 203 #define CSR4            4
 204 #define CSR5            5
 205 #define CSR5_SUSPEND    0x0001
 206 #define CSR15           15
 207 #define PCNET32_MC_FILTER       8
 208
 209 #define PCNET32_79C970A 0x2621
 210
 211 /* The PCNET32 Rx and Tx ring descriptors. */
 212 struct pcnet32_rx_head {
 213         __le32  base;
 214         __le16  buf_length;     /* two`s complement of length */
 215         __le16  status;
 216         __le32  msg_length;
 217         __le32  reserved;
 218 };
 219
 220 struct pcnet32_tx_head {
 221         __le32  base;
 222         __le16  length;         /* two`s complement of length */
 223         __le16  status;
 224         __le32  misc;
 225         __le32  reserved;
 226 };
 227
 228 /* The PCNET32 32-Bit initialization block, described in databook. */
 229 struct pcnet32_init_block {
 230         __le16  mode;
 231         __le16  tlen_rlen;
 232         u8      phys_addr[6];
 233         __le16  reserved;
 234         __le32  filter[2];
 235         /* Receive and transmit ring base, along with extra bits. */
 236         __le32  rx_ring;
 237         __le32  tx_ring;
 238 };
 239
 240 /* PCnet32 access functions */
 241 struct pcnet32_access {
 242         u16     (*read_csr) (unsigned long, int);
 243         void    (*write_csr) (unsigned long, int, u16);
 244         u16     (*read_bcr) (unsigned long, int);
 245         void    (*write_bcr) (unsigned long, int, u16);
 246         u16     (*read_rap) (unsigned long);
 247         void    (*write_rap) (unsigned long, u16);
 248         void    (*reset) (unsigned long);
 249 };
 250
 251 /*
 252  * The first field of pcnet32_private is read by the ethernet device
 253  * so the structure should be allocated using dma_alloc_coherent().
 254  */
 255 struct pcnet32_private {
 256         struct pcnet32_init_block *init_block;
 257         /* The Tx and Rx ring entries must be aligned on 16-byte boundaries in 32bit mode. */
 258         struct pcnet32_rx_head  *rx_ring;
 259         struct pcnet32_tx_head  *tx_ring;
 260         dma_addr_t              init_dma_addr;/* DMA address of beginning of the init block,
 261                                    returned by dma_alloc_coherent */
 262         struct pci_dev          *pci_dev;
 263         const char              *name;
 264         /* The saved address of a sent-in-place packet/buffer, for skfree(). */
 265         struct sk_buff          **tx_skbuff;
 266         struct sk_buff          **rx_skbuff;
 267         dma_addr_t              *tx_dma_addr;
 268         dma_addr_t              *rx_dma_addr;
 269         const struct pcnet32_access *a;
 270         spinlock_t              lock;           /* Guard lock */
 271         unsigned int            cur_rx, cur_tx; /* The next free ring entry */
 272         unsigned int            rx_ring_size;   /* current rx ring size */
 273         unsigned int            tx_ring_size;   /* current tx ring size */
 274         unsigned int            rx_mod_mask;    /* rx ring modular mask */
 275         unsigned int            tx_mod_mask;    /* tx ring modular mask */
 276         unsigned short          rx_len_bits;
 277         unsigned short          tx_len_bits;
 278         dma_addr_t              rx_ring_dma_addr;
 279         dma_addr_t              tx_ring_dma_addr;
 280         unsigned int            dirty_rx,       /* ring entries to be freed. */
 281                                 dirty_tx;
 282
 283         struct net_device       *dev;
 284         struct napi_struct      napi;
 285         char                    tx_full;
 286         char                    phycount;       /* number of phys found */
 287         int                     options;
 288         unsigned int            shared_irq:1,   /* shared irq possible */
 289                                 dxsuflo:1,   /* disable transmit stop on uflo */
 290                                 mii:1,          /* mii port available */
 291                                 autoneg:1,      /* autoneg enabled */
 292                                 port_tp:1,      /* port set to TP */
 293                                 fdx:1;          /* full duplex enabled */
 294         struct net_device       *next;
 295         struct mii_if_info      mii_if;
 296         struct timer_list       watchdog_timer;
 297         u32                     msg_enable;     /* debug message level */
 298
 299         /* each bit indicates an available PHY */
 300         u32                     phymask;
 301         unsigned short          chip_version;   /* which variant this is */
 302
 303         /* saved registers during ethtool blink */
 304         u16                     save_regs[4];
 305 };
 306
 307 static int pcnet32_probe_pci(struct pci_dev *, const struct pci_device_id *);
 308 static int pcnet32_probe1(unsigned long, int, struct pci_dev *);
 309 static int pcnet32_open(struct net_device *);
 310 static int pcnet32_init_ring(struct net_device *);
 311 static netdev_tx_t pcnet32_start_xmit(struct sk_buff *,
 312                                       struct net_device *);
 313 static void pcnet32_tx_timeout(struct net_device *dev, unsigned int txqueue);
 314 static irqreturn_t pcnet32_interrupt(int, void *);
 315 static int pcnet32_close(struct net_device *);
 316 static struct net_device_stats *pcnet32_get_stats(struct net_device *);
 317 static void pcnet32_load_multicast(struct net_device *dev);
 318 static void pcnet32_set_multicast_list(struct net_device *);
 319 static int pcnet32_ioctl(struct net_device *, struct ifreq *, int);
 320 static void pcnet32_watchdog(struct timer_list *);
 321 static int mdio_read(struct net_device *dev, int phy_id, int reg_num);
 322 static void mdio_write(struct net_device *dev, int phy_id, int reg_num,
 323                        int val);
 324 static void pcnet32_restart(struct net_device *dev, unsigned int csr0_bits);
 325 static void pcnet32_ethtool_test(struct net_device *dev,
 326                                  struct ethtool_test *eth_test, u64 * data);
 327 static int pcnet32_loopback_test(struct net_device *dev, uint64_t * data1);
 328 static int pcnet32_get_regs_len(struct net_device *dev);
 329 static void pcnet32_get_regs(struct net_device *dev, struct ethtool_regs *regs,
 330                              void *ptr);
 331 static void pcnet32_purge_tx_ring(struct net_device *dev);
 332 static int pcnet32_alloc_ring(struct net_device *dev, const char *name);
 333 static void pcnet32_free_ring(struct net_device *dev);
 334 static void pcnet32_check_media(struct net_device *dev, int verbose);
 335
 336 static u16 pcnet32_wio_read_csr(unsigned long addr, int index)
 337 {
 338         outw(index, addr + PCNET32_WIO_RAP);
 339         return inw(addr + PCNET32_WIO_RDP);
 340 }
 341
 342 static void pcnet32_wio_write_csr(unsigned long addr, int index, u16 val)
 343 {
 344         outw(index, addr + PCNET32_WIO_RAP);
 345         outw(val, addr + PCNET32_WIO_RDP);
 346 }
 347
 348 static u16 pcnet32_wio_read_bcr(unsigned long addr, int index)
 349 {
 350         outw(index, addr + PCNET32_WIO_RAP);
 351         return inw(addr + PCNET32_WIO_BDP);
 352 }
 353
 354 static void pcnet32_wio_write_bcr(unsigned long addr, int index, u16 val)
 355 {
 356         outw(index, addr + PCNET32_WIO_RAP);
 357         outw(val, addr + PCNET32_WIO_BDP);
 358 }
 359
 360 static u16 pcnet32_wio_read_rap(unsigned long addr)
 361 {
 362         return inw(addr + PCNET32_WIO_RAP);
 363 }
 364
 365 static void pcnet32_wio_write_rap(unsigned long addr, u16 val)
 366 {
 367         outw(val, addr + PCNET32_WIO_RAP);
 368 }
 369
 370 static void pcnet32_wio_reset(unsigned long addr)
 371 {
 372         inw(addr + PCNET32_WIO_RESET);
 373 }
 374
 375 static int pcnet32_wio_check(unsigned long addr)
 376 {
 377         outw(88, addr + PCNET32_WIO_RAP);
 378         return inw(addr + PCNET32_WIO_RAP) == 88;
 379 }
 380
 381 static const struct pcnet32_access pcnet32_wio = {
 382         .read_csr = pcnet32_wio_read_csr,
 383         .write_csr = pcnet32_wio_write_csr,
 384         .read_bcr = pcnet32_wio_read_bcr,
 385         .write_bcr = pcnet32_wio_write_bcr,
 386         .read_rap = pcnet32_wio_read_rap,
 387         .write_rap = pcnet32_wio_write_rap,
 388         .reset = pcnet32_wio_reset
 389 };
 390
 391 static u16 pcnet32_dwio_read_csr(unsigned long addr, int index)
 392 {
 393         outl(index, addr + PCNET32_DWIO_RAP);
 394         return inl(addr + PCNET32_DWIO_RDP) & 0xffff;
 395 }
 396
 397 static void pcnet32_dwio_write_csr(unsigned long addr, int index, u16 val)
 398 {
 399         outl(index, addr + PCNET32_DWIO_RAP);
 400         outl(val, addr + PCNET32_DWIO_RDP);
 401 }
 402
 403 static u16 pcnet32_dwio_read_bcr(unsigned long addr, int index)
 404 {
 405         outl(index, addr + PCNET32_DWIO_RAP);
 406         return inl(addr + PCNET32_DWIO_BDP) & 0xffff;
 407 }
 408
 409 static void pcnet32_dwio_write_bcr(unsigned long addr, int index, u16 val)
 410 {
 411         outl(index, addr + PCNET32_DWIO_RAP);
 412         outl(val, addr + PCNET32_DWIO_BDP);
 413 }
 414
 415 static u16 pcnet32_dwio_read_rap(unsigned long addr)
 416 {
 417         return inl(addr + PCNET32_DWIO_RAP) & 0xffff;
 418 }
 419
 420 static void pcnet32_dwio_write_rap(unsigned long addr, u16 val)
 421 {
 422         outl(val, addr + PCNET32_DWIO_RAP);
 423 }
 424
 425 static void pcnet32_dwio_reset(unsigned long addr)
 426 {
 427         inl(addr + PCNET32_DWIO_RESET);
 428 }
 429
 430 static int pcnet32_dwio_check(unsigned long addr)
 431 {
 432         outl(88, addr + PCNET32_DWIO_RAP);
 433         return (inl(addr + PCNET32_DWIO_RAP) & 0xffff) == 88;
 434 }
 435
 436 static const struct pcnet32_access pcnet32_dwio = {
 437         .read_csr = pcnet32_dwio_read_csr,
 438         .write_csr = pcnet32_dwio_write_csr,
 439         .read_bcr = pcnet32_dwio_read_bcr,
 440         .write_bcr = pcnet32_dwio_write_bcr,
 441         .read_rap = pcnet32_dwio_read_rap,
 442         .write_rap = pcnet32_dwio_write_rap,
 443         .reset = pcnet32_dwio_reset
 444 };
 445
 446 static void pcnet32_netif_stop(struct net_device *dev)
 447 {
 448         struct pcnet32_private *lp = netdev_priv(dev);
 449
 450         netif_trans_update(dev); /* prevent tx timeout */
 451         napi_disable(&lp->napi);
 452         netif_tx_disable(dev);
 453 }
 454
 455 static void pcnet32_netif_start(struct net_device *dev)
 456 {
 457         struct pcnet32_private *lp = netdev_priv(dev);
 458         ulong ioaddr = dev->base_addr;
 459         u16 val;
 460
 461         netif_wake_queue(dev);
 462         val = lp->a->read_csr(ioaddr, CSR3);
 463         val &= 0x00ff;
 464         lp->a->write_csr(ioaddr, CSR3, val);
 465         napi_enable(&lp->napi);
 466 }
 467
 468 /*
 469  * Allocate space for the new sized tx ring.
 470  * Free old resources
 471  * Save new resources.
 472  * Any failure keeps old resources.
 473  * Must be called with lp->lock held.
 474  */
 475 static void pcnet32_realloc_tx_ring(struct net_device *dev,
 476                                     struct pcnet32_private *lp,
 477                                     unsigned int size)
 478 {
 479         dma_addr_t new_ring_dma_addr;
 480         dma_addr_t *new_dma_addr_list;
 481         struct pcnet32_tx_head *new_tx_ring;
 482         struct sk_buff **new_skb_list;
 483         unsigned int entries = BIT(size);
 484
 485         pcnet32_purge_tx_ring(dev);
 486
 487         new_tx_ring =
 488                 dma_alloc_coherent(&lp->pci_dev->dev,
 489                                    sizeof(struct pcnet32_tx_head) * entries,
 490                                    &new_ring_dma_addr, GFP_ATOMIC);
 491         if (new_tx_ring == NULL)
 492                 return;
 493
 494         new_dma_addr_list = kcalloc(entries, sizeof(dma_addr_t), GFP_ATOMIC);
 495         if (!new_dma_addr_list)
 496                 goto free_new_tx_ring;
 497
 498         new_skb_list = kcalloc(entries, sizeof(struct sk_buff *), GFP_ATOMIC);
 499         if (!new_skb_list)
 500                 goto free_new_lists;
 501
 502         kfree(lp->tx_skbuff);
 503         kfree(lp->tx_dma_addr);
 504         dma_free_coherent(&lp->pci_dev->dev,
 505                           sizeof(struct pcnet32_tx_head) * lp->tx_ring_size,
 506                           lp->tx_ring, lp->tx_ring_dma_addr);
 507
 508         lp->tx_ring_size = entries;
 509         lp->tx_mod_mask = lp->tx_ring_size - 1;
 510         lp->tx_len_bits = (size << 12);
 511         lp->tx_ring = new_tx_ring;
 512         lp->tx_ring_dma_addr = new_ring_dma_addr;
 513         lp->tx_dma_addr = new_dma_addr_list;
 514         lp->tx_skbuff = new_skb_list;
 515         return;
 516
 517 free_new_lists:
 518         kfree(new_dma_addr_list);
 519 free_new_tx_ring:
 520         dma_free_coherent(&lp->pci_dev->dev,
 521                           sizeof(struct pcnet32_tx_head) * entries,
 522                           new_tx_ring, new_ring_dma_addr);
 523 }
 524
 525 /*
 526  * Allocate space for the new sized rx ring.
 527  * Re-use old receive buffers.
 528  *   alloc extra buffers
 529  *   free unneeded buffers
 530  *   free unneeded buffers
 531  * Save new resources.
 532  * Any failure keeps old resources.
 533  * Must be called with lp->lock held.
 534  */
 535 static void pcnet32_realloc_rx_ring(struct net_device *dev,
 536                                     struct pcnet32_private *lp,
 537                                     unsigned int size)
 538 {
 539         dma_addr_t new_ring_dma_addr;
 540         dma_addr_t *new_dma_addr_list;
 541         struct pcnet32_rx_head *new_rx_ring;
 542         struct sk_buff **new_skb_list;
 543         int new, overlap;
 544         unsigned int entries = BIT(size);
 545
 546         new_rx_ring =
 547                 dma_alloc_coherent(&lp->pci_dev->dev,
 548                                    sizeof(struct pcnet32_rx_head) * entries,
 549                                    &new_ring_dma_addr, GFP_ATOMIC);
 550         if (new_rx_ring == NULL)
 551                 return;
 552
 553         new_dma_addr_list = kcalloc(entries, sizeof(dma_addr_t), GFP_ATOMIC);
 554         if (!new_dma_addr_list)
 555                 goto free_new_rx_ring;
 556
 557         new_skb_list = kcalloc(entries, sizeof(struct sk_buff *), GFP_ATOMIC);
 558         if (!new_skb_list)
 559                 goto free_new_lists;
 560
 561         /* first copy the current receive buffers */
 562         overlap = min(entries, lp->rx_ring_size);
 563         for (new = 0; new < overlap; new++) {
 564                 new_rx_ring[new] = lp->rx_ring[new];
 565                 new_dma_addr_list[new] = lp->rx_dma_addr[new];
 566                 new_skb_list[new] = lp->rx_skbuff[new];
 567         }
 568         /* now allocate any new buffers needed */
 569         for (; new < entries; new++) {
 570                 struct sk_buff *rx_skbuff;
 571                 new_skb_list[new] = netdev_alloc_skb(dev, PKT_BUF_SKB);
 572                 rx_skbuff = new_skb_list[new];
 573                 if (!rx_skbuff) {
 574                         /* keep the original lists and buffers */
 575                         netif_err(lp, drv, dev, "%s netdev_alloc_skb failed\n",
 576                                   __func__);
 577                         goto free_all_new;
 578                 }
 579                 skb_reserve(rx_skbuff, NET_IP_ALIGN);
 580
 581                 new_dma_addr_list[new] =
 582                             dma_map_single(&lp->pci_dev->dev, rx_skbuff->data,
 583                                            PKT_BUF_SIZE, DMA_FROM_DEVICE);
 584                 if (dma_mapping_error(&lp->pci_dev->dev, new_dma_addr_list[new])) {
 585                         netif_err(lp, drv, dev, "%s dma mapping failed\n",
 586                                   __func__);
 587                         dev_kfree_skb(new_skb_list[new]);
 588                         goto free_all_new;
 589                 }
 590                 new_rx_ring[new].base = cpu_to_le32(new_dma_addr_list[new]);
 591                 new_rx_ring[new].buf_length = cpu_to_le16(NEG_BUF_SIZE);
 592                 new_rx_ring[new].status = cpu_to_le16(0x8000);
 593         }
 594         /* and free any unneeded buffers */
 595         for (; new < lp->rx_ring_size; new++) {
 596                 if (lp->rx_skbuff[new]) {
 597                         if (!dma_mapping_error(&lp->pci_dev->dev, lp->rx_dma_addr[new]))
 598                                 dma_unmap_single(&lp->pci_dev->dev,
 599                                                  lp->rx_dma_addr[new],
 600                                                  PKT_BUF_SIZE,
 601                                                  DMA_FROM_DEVICE);
 602                         dev_kfree_skb(lp->rx_skbuff[new]);
 603                 }
 604         }
 605
 606         kfree(lp->rx_skbuff);
 607         kfree(lp->rx_dma_addr);
 608         dma_free_coherent(&lp->pci_dev->dev,
 609                           sizeof(struct pcnet32_rx_head) * lp->rx_ring_size,
 610                           lp->rx_ring, lp->rx_ring_dma_addr);
 611
 612         lp->rx_ring_size = entries;
 613         lp->rx_mod_mask = lp->rx_ring_size - 1;
 614         lp->rx_len_bits = (size << 4);
 615         lp->rx_ring = new_rx_ring;
 616         lp->rx_ring_dma_addr = new_ring_dma_addr;
 617         lp->rx_dma_addr = new_dma_addr_list;
 618         lp->rx_skbuff = new_skb_list;
 619         return;
 620
 621 free_all_new:
 622         while (--new >= lp->rx_ring_size) {
 623                 if (new_skb_list[new]) {
 624                         if (!dma_mapping_error(&lp->pci_dev->dev, new_dma_addr_list[new]))
 625                                 dma_unmap_single(&lp->pci_dev->dev,
 626                                                  new_dma_addr_list[new],
 627                                                  PKT_BUF_SIZE,
 628                                                  DMA_FROM_DEVICE);
 629                         dev_kfree_skb(new_skb_list[new]);
 630                 }
 631         }
 632         kfree(new_skb_list);
 633 free_new_lists:
 634         kfree(new_dma_addr_list);
 635 free_new_rx_ring:
 636         dma_free_coherent(&lp->pci_dev->dev,
 637                           sizeof(struct pcnet32_rx_head) * entries,
 638                           new_rx_ring, new_ring_dma_addr);
 639 }
 640
 641 static void pcnet32_purge_rx_ring(struct net_device *dev)
 642 {
 643         struct pcnet32_private *lp = netdev_priv(dev);
 644         int i;
 645
 646         /* free all allocated skbuffs */
 647         for (i = 0; i < lp->rx_ring_size; i++) {
 648                 lp->rx_ring[i].status = 0;      /* CPU owns buffer */
 649                 wmb();          /* Make sure adapter sees owner change */
 650                 if (lp->rx_skbuff[i]) {
 651                         if (!dma_mapping_error(&lp->pci_dev->dev, lp->rx_dma_addr[i]))
 652                                 dma_unmap_single(&lp->pci_dev->dev,
 653                                                  lp->rx_dma_addr[i],
 654                                                  PKT_BUF_SIZE,
 655                                                  DMA_FROM_DEVICE);
 656                         dev_kfree_skb_any(lp->rx_skbuff[i]);
 657                 }
 658                 lp->rx_skbuff[i] = NULL;
 659                 lp->rx_dma_addr[i] = 0;
 660         }
 661 }
 662
 663 #ifdef CONFIG_NET_POLL_CONTROLLER
 664 static void pcnet32_poll_controller(struct net_device *dev)
 665 {
 666         disable_irq(dev->irq);
 667         pcnet32_interrupt(0, dev);
 668         enable_irq(dev->irq);
 669 }
 670 #endif
 671
 672 /*
 673  * lp->lock must be held.
 674  */
 675 static int pcnet32_suspend(struct net_device *dev, unsigned long *flags,
 676                            int can_sleep)
 677 {
 678         int csr5;
 679         struct pcnet32_private *lp = netdev_priv(dev);
 680         const struct pcnet32_access *a = lp->a;
 681         ulong ioaddr = dev->base_addr;
 682         int ticks;
 683
 684         /* really old chips have to be stopped. */
 685         if (lp->chip_version < PCNET32_79C970A)
 686                 return 0;
 687
 688         /* set SUSPEND (SPND) - CSR5 bit 0 */
 689         csr5 = a->read_csr(ioaddr, CSR5);
 690         a->write_csr(ioaddr, CSR5, csr5 | CSR5_SUSPEND);
 691
 692         /* poll waiting for bit to be set */
 693         ticks = 0;
 694         while (!(a->read_csr(ioaddr, CSR5) & CSR5_SUSPEND)) {
 695                 spin_unlock_irqrestore(&lp->lock, *flags);
 696                 if (can_sleep)
 697                         msleep(1);
 698                 else
 699                         mdelay(1);
 700                 spin_lock_irqsave(&lp->lock, *flags);
 701                 ticks++;
 702                 if (ticks > 200) {
 703                         netif_printk(lp, hw, KERN_DEBUG, dev,
 704                                      "Error getting into suspend!\n");
 705                         return 0;
 706                 }
 707         }
 708         return 1;
 709 }
 710
 711 static void pcnet32_clr_suspend(struct pcnet32_private *lp, ulong ioaddr)
 712 {
 713         int csr5 = lp->a->read_csr(ioaddr, CSR5);
 714         /* clear SUSPEND (SPND) - CSR5 bit 0 */
 715         lp->a->write_csr(ioaddr, CSR5, csr5 & ~CSR5_SUSPEND);
 716 }
 717
 718 static int pcnet32_get_link_ksettings(struct net_device *dev,
 719                                       struct ethtool_link_ksettings *cmd)
 720 {
 721         struct pcnet32_private *lp = netdev_priv(dev);
 722         unsigned long flags;
 723
 724         spin_lock_irqsave(&lp->lock, flags);
 725         if (lp->mii) {
 726                 mii_ethtool_get_link_ksettings(&lp->mii_if, cmd);
 727         } else if (lp->chip_version == PCNET32_79C970A) {
 728                 if (lp->autoneg) {
 729                         cmd->base.autoneg = AUTONEG_ENABLE;
 730                         if (lp->a->read_bcr(dev->base_addr, 4) == 0xc0)
 731                                 cmd->base.port = PORT_AUI;
 732                         else
 733                                 cmd->base.port = PORT_TP;
 734                 } else {
 735                         cmd->base.autoneg = AUTONEG_DISABLE;
 736                         cmd->base.port = lp->port_tp ? PORT_TP : PORT_AUI;
 737                 }
 738                 cmd->base.duplex = lp->fdx ? DUPLEX_FULL : DUPLEX_HALF;
 739                 cmd->base.speed = SPEED_10;
 740                 ethtool_convert_legacy_u32_to_link_mode(
 741                                                 cmd->link_modes.supported,
 742                                                 SUPPORTED_TP | SUPPORTED_AUI);
 743         }
 744         spin_unlock_irqrestore(&lp->lock, flags);
 745         return 0;
 746 }
 747
 748 static int pcnet32_set_link_ksettings(struct net_device *dev,
 749                                       const struct ethtool_link_ksettings *cmd)
 750 {
 751         struct pcnet32_private *lp = netdev_priv(dev);
 752         ulong ioaddr = dev->base_addr;
 753         unsigned long flags;
 754         int r = -EOPNOTSUPP;
 755         int suspended, bcr2, bcr9, csr15;
 756
 757         spin_lock_irqsave(&lp->lock, flags);
 758         if (lp->mii) {
 759                 r = mii_ethtool_set_link_ksettings(&lp->mii_if, cmd);
 760         } else if (lp->chip_version == PCNET32_79C970A) {
 761                 suspended = pcnet32_suspend(dev, &flags, 0);
 762                 if (!suspended)
 763                         lp->a->write_csr(ioaddr, CSR0, CSR0_STOP);
 764
 765                 lp->autoneg = cmd->base.autoneg == AUTONEG_ENABLE;
 766                 bcr2 = lp->a->read_bcr(ioaddr, 2);
 767                 if (cmd->base.autoneg == AUTONEG_ENABLE) {
 768                         lp->a->write_bcr(ioaddr, 2, bcr2 | 0x0002);
 769                 } else {
 770                         lp->a->write_bcr(ioaddr, 2, bcr2 & ~0x0002);
 771
 772                         lp->port_tp = cmd->base.port == PORT_TP;
 773                         csr15 = lp->a->read_csr(ioaddr, CSR15) & ~0x0180;
 774                         if (cmd->base.port == PORT_TP)
 775                                 csr15 |= 0x0080;
 776                         lp->a->write_csr(ioaddr, CSR15, csr15);
 777                         lp->init_block->mode = cpu_to_le16(csr15);
 778
 779                         lp->fdx = cmd->base.duplex == DUPLEX_FULL;
 780                         bcr9 = lp->a->read_bcr(ioaddr, 9) & ~0x0003;
 781                         if (cmd->base.duplex == DUPLEX_FULL)
 782                                 bcr9 |= 0x0003;
 783                         lp->a->write_bcr(ioaddr, 9, bcr9);
 784                 }
 785                 if (suspended)
 786                         pcnet32_clr_suspend(lp, ioaddr);
 787                 else if (netif_running(dev))
 788                         pcnet32_restart(dev, CSR0_NORMAL);
 789                 r = 0;
 790         }
 791         spin_unlock_irqrestore(&lp->lock, flags);
 792         return r;
 793 }
 794
 795 static void pcnet32_get_drvinfo(struct net_device *dev,
 796                                 struct ethtool_drvinfo *info)
 797 {
 798         struct pcnet32_private *lp = netdev_priv(dev);
 799
 800         strlcpy(info->driver, DRV_NAME, sizeof(info->driver));
 801         if (lp->pci_dev)
 802                 strlcpy(info->bus_info, pci_name(lp->pci_dev),
 803                         sizeof(info->bus_info));
 804         else
 805                 snprintf(info->bus_info, sizeof(info->bus_info),
 806                         "VLB 0x%lx", dev->base_addr);
 807 }
 808
 809 static u32 pcnet32_get_link(struct net_device *dev)
 810 {
 811         struct pcnet32_private *lp = netdev_priv(dev);
 812         unsigned long flags;
 813         int r;
 814
 815         spin_lock_irqsave(&lp->lock, flags);
 816         if (lp->mii) {
 817                 r = mii_link_ok(&lp->mii_if);
 818         } else if (lp->chip_version == PCNET32_79C970A) {
 819                 ulong ioaddr = dev->base_addr;  /* card base I/O address */
 820                 /* only read link if port is set to TP */
 821                 if (!lp->autoneg && lp->port_tp)
 822                         r = (lp->a->read_bcr(ioaddr, 4) != 0xc0);
 823                 else /* link always up for AUI port or port auto select */
 824                         r = 1;
 825         } else if (lp->chip_version > PCNET32_79C970A) {
 826                 ulong ioaddr = dev->base_addr;  /* card base I/O address */
 827                 r = (lp->a->read_bcr(ioaddr, 4) != 0xc0);
 828         } else {        /* can not detect link on really old chips */
 829                 r = 1;
 830         }
 831         spin_unlock_irqrestore(&lp->lock, flags);
 832
 833         return r;
 834 }
 835
 836 static u32 pcnet32_get_msglevel(struct net_device *dev)
 837 {
 838         struct pcnet32_private *lp = netdev_priv(dev);
 839         return lp->msg_enable;
 840 }
 841
 842 static void pcnet32_set_msglevel(struct net_device *dev, u32 value)
 843 {
 844         struct pcnet32_private *lp = netdev_priv(dev);
 845         lp->msg_enable = value;
 846 }
 847
 848 static int pcnet32_nway_reset(struct net_device *dev)
 849 {
 850         struct pcnet32_private *lp = netdev_priv(dev);
 851         unsigned long flags;
 852         int r = -EOPNOTSUPP;
 853
 854         if (lp->mii) {
 855                 spin_lock_irqsave(&lp->lock, flags);
 856                 r = mii_nway_restart(&lp->mii_if);
 857                 spin_unlock_irqrestore(&lp->lock, flags);
 858         }
 859         return r;
 860 }
 861
 862 static void pcnet32_get_ringparam(struct net_device *dev,
 863                                   struct ethtool_ringparam *ering)
 864 {
 865         struct pcnet32_private *lp = netdev_priv(dev);
 866
 867         ering->tx_max_pending = TX_MAX_RING_SIZE;
 868         ering->tx_pending = lp->tx_ring_size;
 869         ering->rx_max_pending = RX_MAX_RING_SIZE;
 870         ering->rx_pending = lp->rx_ring_size;
 871 }
 872
 873 static int pcnet32_set_ringparam(struct net_device *dev,
 874                                  struct ethtool_ringparam *ering)
 875 {
 876         struct pcnet32_private *lp = netdev_priv(dev);
 877         unsigned long flags;
 878         unsigned int size;
 879         ulong ioaddr = dev->base_addr;
 880         int i;
 881
 882         if (ering->rx_mini_pending || ering->rx_jumbo_pending)
 883                 return -EINVAL;
 884
 885         if (netif_running(dev))
 886                 pcnet32_netif_stop(dev);
 887
 888         spin_lock_irqsave(&lp->lock, flags);
 889         lp->a->write_csr(ioaddr, CSR0, CSR0_STOP);      /* stop the chip */
 890
 891         size = min(ering->tx_pending, (unsigned int)TX_MAX_RING_SIZE);
 892
 893         /* set the minimum ring size to 4, to allow the loopback test to work
 894          * unchanged.
 895          */
 896         for (i = 2; i <= PCNET32_LOG_MAX_TX_BUFFERS; i++) {
 897                 if (size <= (1 << i))
 898                         break;
 899         }
 900         if ((1 << i) != lp->tx_ring_size)
 901                 pcnet32_realloc_tx_ring(dev, lp, i);
 902
 903         size = min(ering->rx_pending, (unsigned int)RX_MAX_RING_SIZE);
 904         for (i = 2; i <= PCNET32_LOG_MAX_RX_BUFFERS; i++) {
 905                 if (size <= (1 << i))
 906                         break;
 907         }
 908         if ((1 << i) != lp->rx_ring_size)
 909                 pcnet32_realloc_rx_ring(dev, lp, i);
 910
 911         lp->napi.weight = lp->rx_ring_size / 2;
 912
 913         if (netif_running(dev)) {
 914                 pcnet32_netif_start(dev);
 915                 pcnet32_restart(dev, CSR0_NORMAL);
 916         }
 917
 918         spin_unlock_irqrestore(&lp->lock, flags);
 919
 920         netif_info(lp, drv, dev, "Ring Param Settings: RX: %d, TX: %d\n",
 921                    lp->rx_ring_size, lp->tx_ring_size);
 922
 923         return 0;
 924 }
 925
 926 static void pcnet32_get_strings(struct net_device *dev, u32 stringset,
 927                                 u8 *data)
 928 {
 929         memcpy(data, pcnet32_gstrings_test, sizeof(pcnet32_gstrings_test));
 930 }
 931
 932 static int pcnet32_get_sset_count(struct net_device *dev, int sset)
 933 {
 934         switch (sset) {
 935         case ETH_SS_TEST:
 936                 return PCNET32_TEST_LEN;
 937         default:
 938                 return -EOPNOTSUPP;
 939         }
 940 }
 941
 942 static void pcnet32_ethtool_test(struct net_device *dev,
 943                                  struct ethtool_test *test, u64 * data)
 944 {
 945         struct pcnet32_private *lp = netdev_priv(dev);
 946         int rc;
 947
 948         if (test->flags == ETH_TEST_FL_OFFLINE) {
 949                 rc = pcnet32_loopback_test(dev, data);
 950                 if (rc) {
 951                         netif_printk(lp, hw, KERN_DEBUG, dev,
 952                                      "Loopback test failed\n");
 953                         test->flags |= ETH_TEST_FL_FAILED;
 954                 } else
 955                         netif_printk(lp, hw, KERN_DEBUG, dev,
 956                                      "Loopback test passed\n");
 957         } else
 958                 netif_printk(lp, hw, KERN_DEBUG, dev,
 959                              "No tests to run (specify 'Offline' on ethtool)\n");
 960 }                               /* end pcnet32_ethtool_test */
 961
 962 static int pcnet32_loopback_test(struct net_device *dev, uint64_t * data1)
 963 {
 964         struct pcnet32_private *lp = netdev_priv(dev);
 965         const struct pcnet32_access *a = lp->a; /* access to registers */
 966         ulong ioaddr = dev->base_addr;  /* card base I/O address */
 967         struct sk_buff *skb;    /* sk buff */
 968         int x, i;               /* counters */
 969         int numbuffs = 4;       /* number of TX/RX buffers and descs */
 970         u16 status = 0x8300;    /* TX ring status */
 971         __le16 teststatus;      /* test of ring status */
 972         int rc;                 /* return code */
 973         int size;               /* size of packets */
 974         unsigned char *packet;  /* source packet data */
 975         static const int data_len = 60; /* length of source packets */
 976         unsigned long flags;
 977         unsigned long ticks;
 978
 979         rc = 1;                 /* default to fail */
 980
 981         if (netif_running(dev))
 982                 pcnet32_netif_stop(dev);
 983
 984         spin_lock_irqsave(&lp->lock, flags);
 985         lp->a->write_csr(ioaddr, CSR0, CSR0_STOP);      /* stop the chip */
 986
 987         numbuffs = min(numbuffs, (int)min(lp->rx_ring_size, lp->tx_ring_size));
 988
 989         /* Reset the PCNET32 */
 990         lp->a->reset(ioaddr);
 991         lp->a->write_csr(ioaddr, CSR4, 0x0915); /* auto tx pad */
 992
 993         /* switch pcnet32 to 32bit mode */
 994         lp->a->write_bcr(ioaddr, 20, 2);
 995
 996         /* purge & init rings but don't actually restart */
 997         pcnet32_restart(dev, 0x0000);
 998
 999         lp->a->write_csr(ioaddr, CSR0, CSR0_STOP);      /* Set STOP bit */
1000
1001         /* Initialize Transmit buffers. */
1002         size = data_len + 15;
1003         for (x = 0; x < numbuffs; x++) {
1004                 skb = netdev_alloc_skb(dev, size);
1005                 if (!skb) {
1006                         netif_printk(lp, hw, KERN_DEBUG, dev,
1007                                      "Cannot allocate skb at line: %d!\n",
1008                                      __LINE__);
1009                         goto clean_up;
1010                 }
1011                 packet = skb->data;
1012                 skb_put(skb, size);     /* create space for data */
1013                 lp->tx_skbuff[x] = skb;
1014                 lp->tx_ring[x].length = cpu_to_le16(-skb->len);
1015                 lp->tx_ring[x].misc = 0;
1016
1017                 /* put DA and SA into the skb */
1018                 for (i = 0; i < 6; i++)
1019                         *packet++ = dev->dev_addr[i];
1020                 for (i = 0; i < 6; i++)
1021                         *packet++ = dev->dev_addr[i];
1022                 /* type */
1023                 *packet++ = 0x08;
1024                 *packet++ = 0x06;
1025                 /* packet number */
1026                 *packet++ = x;
1027                 /* fill packet with data */
1028                 for (i = 0; i < data_len; i++)
1029                         *packet++ = i;
1030
1031                 lp->tx_dma_addr[x] =
1032                         dma_map_single(&lp->pci_dev->dev, skb->data, skb->len,
1033                                        DMA_TO_DEVICE);
1034                 if (dma_mapping_error(&lp->pci_dev->dev, lp->tx_dma_addr[x])) {
1035                         netif_printk(lp, hw, KERN_DEBUG, dev,
1036                                      "DMA mapping error at line: %d!\n",
1037                                      __LINE__);
1038                         goto clean_up;
1039                 }
1040                 lp->tx_ring[x].base = cpu_to_le32(lp->tx_dma_addr[x]);
1041                 wmb();  /* Make sure owner changes after all others are visible */
1042                 lp->tx_ring[x].status = cpu_to_le16(status);
1043         }
1044
1045         x = a->read_bcr(ioaddr, 32);    /* set internal loopback in BCR32 */
1046         a->write_bcr(ioaddr, 32, x | 0x0002);
1047
1048         /* set int loopback in CSR15 */
1049         x = a->read_csr(ioaddr, CSR15) & 0xfffc;
1050         lp->a->write_csr(ioaddr, CSR15, x | 0x0044);
1051
1052         teststatus = cpu_to_le16(0x8000);
1053         lp->a->write_csr(ioaddr, CSR0, CSR0_START);     /* Set STRT bit */
1054
1055         /* Check status of descriptors */
1056         for (x = 0; x < numbuffs; x++) {
1057                 ticks = 0;
1058                 rmb();
1059                 while ((lp->rx_ring[x].status & teststatus) && (ticks < 200)) {
1060                         spin_unlock_irqrestore(&lp->lock, flags);
1061                         msleep(1);
1062                         spin_lock_irqsave(&lp->lock, flags);
1063                         rmb();
1064                         ticks++;
1065                 }
1066                 if (ticks == 200) {
1067                         netif_err(lp, hw, dev, "Desc %d failed to reset!\n", x);
1068                         break;
1069                 }
1070         }
1071
1072         lp->a->write_csr(ioaddr, CSR0, CSR0_STOP);      /* Set STOP bit */
1073         wmb();
1074         if (netif_msg_hw(lp) && netif_msg_pktdata(lp)) {
1075                 netdev_printk(KERN_DEBUG, dev, "RX loopback packets:\n");
1076
1077                 for (x = 0; x < numbuffs; x++) {
1078                         netdev_printk(KERN_DEBUG, dev, "Packet %d: ", x);
1079                         skb = lp->rx_skbuff[x];
1080                         for (i = 0; i < size; i++)
1081                                 pr_cont(" %02x", *(skb->data + i));
1082                         pr_cont("\n");
1083                 }
1084         }
1085
1086         x = 0;
1087         rc = 0;
1088         while (x < numbuffs && !rc) {
1089                 skb = lp->rx_skbuff[x];
1090                 packet = lp->tx_skbuff[x]->data;
1091                 for (i = 0; i < size; i++) {
1092                         if (*(skb->data + i) != packet[i]) {
1093                                 netif_printk(lp, hw, KERN_DEBUG, dev,
1094                                              "Error in compare! %2x - %02x %02x\n",
1095                                              i, *(skb->data + i), packet[i]);
1096                                 rc = 1;
1097                                 break;
1098                         }
1099                 }
1100                 x++;
1101         }
1102
1103 clean_up:
1104         *data1 = rc;
1105         pcnet32_purge_tx_ring(dev);
1106
1107         x = a->read_csr(ioaddr, CSR15);
1108         a->write_csr(ioaddr, CSR15, (x & ~0x0044));     /* reset bits 6 and 2 */
1109
1110         x = a->read_bcr(ioaddr, 32);    /* reset internal loopback */
1111         a->write_bcr(ioaddr, 32, (x & ~0x0002));
1112
1113         if (netif_running(dev)) {
1114                 pcnet32_netif_start(dev);
1115                 pcnet32_restart(dev, CSR0_NORMAL);
1116         } else {
1117                 pcnet32_purge_rx_ring(dev);
1118                 lp->a->write_bcr(ioaddr, 20, 4);        /* return to 16bit mode */
1119         }
1120         spin_unlock_irqrestore(&lp->lock, flags);
1121
1122         return rc;
1123 }                               /* end pcnet32_loopback_test  */
1124
1125 static int pcnet32_set_phys_id(struct net_device *dev,
1126                                enum ethtool_phys_id_state state)
1127 {
1128         struct pcnet32_private *lp = netdev_priv(dev);
1129         const struct pcnet32_access *a = lp->a;
1130         ulong ioaddr = dev->base_addr;
1131         unsigned long flags;
1132         int i;
1133
1134         switch (state) {
1135         case ETHTOOL_ID_ACTIVE:
1136                 /* Save the current value of the bcrs */
1137                 spin_lock_irqsave(&lp->lock, flags);
1138                 for (i = 4; i < 8; i++)
1139                         lp->save_regs[i - 4] = a->read_bcr(ioaddr, i);
1140                 spin_unlock_irqrestore(&lp->lock, flags);
1141                 return 2;       /* cycle on/off twice per second */
1142
1143         case ETHTOOL_ID_ON:
1144         case ETHTOOL_ID_OFF:
1145                 /* Blink the led */
1146                 spin_lock_irqsave(&lp->lock, flags);
1147                 for (i = 4; i < 8; i++)
1148                         a->write_bcr(ioaddr, i, a->read_bcr(ioaddr, i) ^ 0x4000);
1149                 spin_unlock_irqrestore(&lp->lock, flags);
1150                 break;
1151
1152         case ETHTOOL_ID_INACTIVE:
1153                 /* Restore the original value of the bcrs */
1154                 spin_lock_irqsave(&lp->lock, flags);
1155                 for (i = 4; i < 8; i++)
1156                         a->write_bcr(ioaddr, i, lp->save_regs[i - 4]);
1157                 spin_unlock_irqrestore(&lp->lock, flags);
1158         }
1159         return 0;
1160 }
1161
1162 /*
1163  * process one receive descriptor entry
1164  */
1165
1166 static void pcnet32_rx_entry(struct net_device *dev,
1167                              struct pcnet32_private *lp,
1168                              struct pcnet32_rx_head *rxp,
1169                              int entry)
1170 {
1171         int status = (short)le16_to_cpu(rxp->status) >> 8;
1172         int rx_in_place = 0;
1173         struct sk_buff *skb;
1174         short pkt_len;
1175
1176         if (status != 0x03) {   /* There was an error. */
1177                 /*
1178                  * There is a tricky error noted by John Murphy,
1179                  * <murf@perftech.com> to Russ Nelson: Even with full-sized
1180                  * buffers it's possible for a jabber packet to use two
1181                  * buffers, with only the last correctly noting the error.
1182                  */
1183                 if (status & 0x01)      /* Only count a general error at the */
1184                         dev->stats.rx_errors++; /* end of a packet. */
1185                 if (status & 0x20)
1186                         dev->stats.rx_frame_errors++;
1187                 if (status & 0x10)
1188                         dev->stats.rx_over_errors++;
1189                 if (status & 0x08)
1190                         dev->stats.rx_crc_errors++;
1191                 if (status & 0x04)
1192                         dev->stats.rx_fifo_errors++;
1193                 return;
1194         }
1195
1196         pkt_len = (le32_to_cpu(rxp->msg_length) & 0xfff) - 4;
1197
1198         /* Discard oversize frames. */
1199         if (unlikely(pkt_len > PKT_BUF_SIZE)) {
1200                 netif_err(lp, drv, dev, "Impossible packet size %d!\n",
1201                           pkt_len);
1202                 dev->stats.rx_errors++;
1203                 return;
1204         }
1205         if (pkt_len < 60) {
1206                 netif_err(lp, rx_err, dev, "Runt packet!\n");
1207                 dev->stats.rx_errors++;
1208                 return;
1209         }
1210
1211         if (pkt_len > rx_copybreak) {
1212                 struct sk_buff *newskb;
1213                 dma_addr_t new_dma_addr;
1214
1215                 newskb = netdev_alloc_skb(dev, PKT_BUF_SKB);
1216                 /*
1217                  * map the new buffer, if mapping fails, drop the packet and
1218                  * reuse the old buffer
1219                  */
1220                 if (newskb) {
1221                         skb_reserve(newskb, NET_IP_ALIGN);
1222                         new_dma_addr = dma_map_single(&lp->pci_dev->dev,
1223                                                       newskb->data,
1224                                                       PKT_BUF_SIZE,
1225                                                       DMA_FROM_DEVICE);
1226                         if (dma_mapping_error(&lp->pci_dev->dev, new_dma_addr)) {
1227                                 netif_err(lp, rx_err, dev,
1228                                           "DMA mapping error.\n");
1229                                 dev_kfree_skb(newskb);
1230                                 skb = NULL;
1231                         } else {
1232                                 skb = lp->rx_skbuff[entry];
1233                                 dma_unmap_single(&lp->pci_dev->dev,
1234                                                  lp->rx_dma_addr[entry],
1235                                                  PKT_BUF_SIZE,
1236                                                  DMA_FROM_DEVICE);
1237                                 skb_put(skb, pkt_len);
1238                                 lp->rx_skbuff[entry] = newskb;
1239                                 lp->rx_dma_addr[entry] = new_dma_addr;
1240                                 rxp->base = cpu_to_le32(new_dma_addr);
1241                                 rx_in_place = 1;
1242                         }
1243                 } else
1244                         skb = NULL;
1245         } else
1246                 skb = netdev_alloc_skb(dev, pkt_len + NET_IP_ALIGN);
1247
1248         if (skb == NULL) {
1249                 dev->stats.rx_dropped++;
1250                 return;
1251         }
1252         if (!rx_in_place) {
1253                 skb_reserve(skb, NET_IP_ALIGN);
1254                 skb_put(skb, pkt_len);  /* Make room */
1255                 dma_sync_single_for_cpu(&lp->pci_dev->dev,
1256                                         lp->rx_dma_addr[entry], pkt_len,
1257                                         DMA_FROM_DEVICE);
1258                 skb_copy_to_linear_data(skb,
1259                                  (unsigned char *)(lp->rx_skbuff[entry]->data),
1260                                  pkt_len);
1261                 dma_sync_single_for_device(&lp->pci_dev->dev,
1262                                            lp->rx_dma_addr[entry], pkt_len,
1263                                            DMA_FROM_DEVICE);
1264         }
1265         dev->stats.rx_bytes += skb->len;
1266         skb->protocol = eth_type_trans(skb, dev);
1267         netif_receive_skb(skb);
1268         dev->stats.rx_packets++;
1269 }
1270
1271 static int pcnet32_rx(struct net_device *dev, int budget)
1272 {
1273         struct pcnet32_private *lp = netdev_priv(dev);
1274         int entry = lp->cur_rx & lp->rx_mod_mask;
1275         struct pcnet32_rx_head *rxp = &lp->rx_ring[entry];
1276         int npackets = 0;
1277
1278         /* If we own the next entry, it's a new packet. Send it up. */
1279         while (npackets < budget && (short)le16_to_cpu(rxp->status) >= 0) {
1280                 pcnet32_rx_entry(dev, lp, rxp, entry);
1281                 npackets += 1;
1282                 /*
1283                  * The docs say that the buffer length isn't touched, but Andrew
1284                  * Boyd of QNX reports that some revs of the 79C965 clear it.
1285                  */
1286                 rxp->buf_length = cpu_to_le16(NEG_BUF_SIZE);
1287                 wmb();  /* Make sure owner changes after others are visible */
1288                 rxp->status = cpu_to_le16(0x8000);
1289                 entry = (++lp->cur_rx) & lp->rx_mod_mask;
1290                 rxp = &lp->rx_ring[entry];
1291         }
1292
1293         return npackets;
1294 }
1295
1296 static int pcnet32_tx(struct net_device *dev)
1297 {
1298         struct pcnet32_private *lp = netdev_priv(dev);
1299         unsigned int dirty_tx = lp->dirty_tx;
1300         int delta;
1301         int must_restart = 0;
1302
1303         while (dirty_tx != lp->cur_tx) {
1304                 int entry = dirty_tx & lp->tx_mod_mask;
1305                 int status = (short)le16_to_cpu(lp->tx_ring[entry].status);
1306
1307                 if (status < 0)
1308                         break;  /* It still hasn't been Txed */
1309
1310                 lp->tx_ring[entry].base = 0;
1311
1312                 if (status & 0x4000) {
1313                         /* There was a major error, log it. */
1314                         int err_status = le32_to_cpu(lp->tx_ring[entry].misc);
1315                         dev->stats.tx_errors++;
1316                         netif_err(lp, tx_err, dev,
1317                                   "Tx error status=%04x err_status=%08x\n",
1318                                   status, err_status);
1319                         if (err_status & 0x04000000)
1320                                 dev->stats.tx_aborted_errors++;
1321                         if (err_status & 0x08000000)
1322                                 dev->stats.tx_carrier_errors++;
1323                         if (err_status & 0x10000000)
1324                                 dev->stats.tx_window_errors++;
1325 #ifndef DO_DXSUFLO
1326                         if (err_status & 0x40000000) {
1327                                 dev->stats.tx_fifo_errors++;
1328                                 /* Ackk!  On FIFO errors the Tx unit is turned off! */
1329                                 /* Remove this verbosity later! */
1330                                 netif_err(lp, tx_err, dev, "Tx FIFO error!\n");
1331                                 must_restart = 1;
1332                         }
1333 #else
1334                         if (err_status & 0x40000000) {
1335                                 dev->stats.tx_fifo_errors++;
1336                                 if (!lp->dxsuflo) {     /* If controller doesn't recover ... */
1337                                         /* Ackk!  On FIFO errors the Tx unit is turned off! */
1338                                         /* Remove this verbosity later! */
1339                                         netif_err(lp, tx_err, dev, "Tx FIFO error!\n");
1340                                         must_restart = 1;
1341                                 }
1342                         }
1343 #endif
1344                 } else {
1345                         if (status & 0x1800)
1346                                 dev->stats.collisions++;
1347                         dev->stats.tx_packets++;
1348                 }
1349
1350                 /* We must free the original skb */
1351                 if (lp->tx_skbuff[entry]) {
1352                         dma_unmap_single(&lp->pci_dev->dev,
1353                                          lp->tx_dma_addr[entry],
1354                                          lp->tx_skbuff[entry]->len,
1355                                          DMA_TO_DEVICE);
1356                         dev_kfree_skb_any(lp->tx_skbuff[entry]);
1357                         lp->tx_skbuff[entry] = NULL;
1358                         lp->tx_dma_addr[entry] = 0;
1359                 }
1360                 dirty_tx++;
1361         }
1362
1363         delta = (lp->cur_tx - dirty_tx) & (lp->tx_mod_mask + lp->tx_ring_size);
1364         if (delta > lp->tx_ring_size) {
1365                 netif_err(lp, drv, dev, "out-of-sync dirty pointer, %d vs. %d, full=%d\n",
1366                           dirty_tx, lp->cur_tx, lp->tx_full);
1367                 dirty_tx += lp->tx_ring_size;
1368                 delta -= lp->tx_ring_size;
1369         }
1370
1371         if (lp->tx_full &&
1372             netif_queue_stopped(dev) &&
1373             delta < lp->tx_ring_size - 2) {
1374                 /* The ring is no longer full, clear tbusy. */
1375                 lp->tx_full = 0;
1376                 netif_wake_queue(dev);
1377         }
1378         lp->dirty_tx = dirty_tx;
1379
1380         return must_restart;
1381 }
1382
1383 static int pcnet32_poll(struct napi_struct *napi, int budget)
1384 {
1385         struct pcnet32_private *lp = container_of(napi, struct pcnet32_private, napi);
1386         struct net_device *dev = lp->dev;
1387         unsigned long ioaddr = dev->base_addr;
1388         unsigned long flags;
1389         int work_done;
1390         u16 val;
1391
1392         work_done = pcnet32_rx(dev, budget);
1393
1394         spin_lock_irqsave(&lp->lock, flags);
1395         if (pcnet32_tx(dev)) {
1396                 /* reset the chip to clear the error condition, then restart */
1397                 lp->a->reset(ioaddr);
1398                 lp->a->write_csr(ioaddr, CSR4, 0x0915); /* auto tx pad */
1399                 pcnet32_restart(dev, CSR0_START);
1400                 netif_wake_queue(dev);
1401         }
1402
1403         if (work_done < budget && napi_complete_done(napi, work_done)) {
1404                 /* clear interrupt masks */
1405                 val = lp->a->read_csr(ioaddr, CSR3);
1406                 val &= 0x00ff;
1407                 lp->a->write_csr(ioaddr, CSR3, val);
1408
1409                 /* Set interrupt enable. */
1410                 lp->a->write_csr(ioaddr, CSR0, CSR0_INTEN);
1411         }
1412
1413         spin_unlock_irqrestore(&lp->lock, flags);
1414         return work_done;
1415 }
1416
1417 #define PCNET32_REGS_PER_PHY    32
1418 #define PCNET32_MAX_PHYS        32
1419 static int pcnet32_get_regs_len(struct net_device *dev)
1420 {
1421         struct pcnet32_private *lp = netdev_priv(dev);
1422         int j = lp->phycount * PCNET32_REGS_PER_PHY;
1423
1424         return (PCNET32_NUM_REGS + j) * sizeof(u16);
1425 }
1426
1427 static void pcnet32_get_regs(struct net_device *dev, struct ethtool_regs *regs,
1428                              void *ptr)
1429 {
1430         int i, csr0;
1431         u16 *buff = ptr;
1432         struct pcnet32_private *lp = netdev_priv(dev);
1433         const struct pcnet32_access *a = lp->a;
1434         ulong ioaddr = dev->base_addr;
1435         unsigned long flags;
1436
1437         spin_lock_irqsave(&lp->lock, flags);
1438
1439         csr0 = a->read_csr(ioaddr, CSR0);
1440         if (!(csr0 & CSR0_STOP))        /* If not stopped */
1441                 pcnet32_suspend(dev, &flags, 1);
1442
1443         /* read address PROM */
1444         for (i = 0; i < 16; i += 2)
1445                 *buff++ = inw(ioaddr + i);
1446
1447         /* read control and status registers */
1448         for (i = 0; i < 90; i++)
1449                 *buff++ = a->read_csr(ioaddr, i);
1450
1451         *buff++ = a->read_csr(ioaddr, 112);
1452         *buff++ = a->read_csr(ioaddr, 114);
1453
1454         /* read bus configuration registers */
1455         for (i = 0; i < 30; i++)
1456                 *buff++ = a->read_bcr(ioaddr, i);
1457
1458         *buff++ = 0;            /* skip bcr30 so as not to hang 79C976 */
1459
1460         for (i = 31; i < 36; i++)
1461                 *buff++ = a->read_bcr(ioaddr, i);
1462
1463         /* read mii phy registers */
1464         if (lp->mii) {
1465                 int j;
1466                 for (j = 0; j < PCNET32_MAX_PHYS; j++) {
1467                         if (lp->phymask & (1 << j)) {
1468                                 for (i = 0; i < PCNET32_REGS_PER_PHY; i++) {
1469                                         lp->a->write_bcr(ioaddr, 33,
1470                                                         (j << 5) | i);
1471                                         *buff++ = lp->a->read_bcr(ioaddr, 34);
1472                                 }
1473                         }
1474                 }
1475         }
1476
1477         if (!(csr0 & CSR0_STOP))        /* If not stopped */
1478                 pcnet32_clr_suspend(lp, ioaddr);
1479
1480         spin_unlock_irqrestore(&lp->lock, flags);
1481 }
1482
1483 static const struct ethtool_ops pcnet32_ethtool_ops = {
1484         .get_drvinfo            = pcnet32_get_drvinfo,
1485         .get_msglevel           = pcnet32_get_msglevel,
1486         .set_msglevel           = pcnet32_set_msglevel,
1487         .nway_reset             = pcnet32_nway_reset,
1488         .get_link               = pcnet32_get_link,
1489         .get_ringparam          = pcnet32_get_ringparam,
1490         .set_ringparam          = pcnet32_set_ringparam,
1491         .get_strings            = pcnet32_get_strings,
1492         .self_test              = pcnet32_ethtool_test,
1493         .set_phys_id            = pcnet32_set_phys_id,
1494         .get_regs_len           = pcnet32_get_regs_len,
1495         .get_regs               = pcnet32_get_regs,
1496         .get_sset_count         = pcnet32_get_sset_count,
1497         .get_link_ksettings     = pcnet32_get_link_ksettings,
1498         .set_link_ksettings     = pcnet32_set_link_ksettings,
1499 };
1500
1501 /* only probes for non-PCI devices, the rest are handled by
1502  * pci_register_driver via pcnet32_probe_pci */
1503
1504 static void pcnet32_probe_vlbus(unsigned int *pcnet32_portlist)
1505 {
1506         unsigned int *port, ioaddr;
1507
1508         /* search for PCnet32 VLB cards at known addresses */
1509         for (port = pcnet32_portlist; (ioaddr = *port); port++) {
1510                 if (request_region
1511                     (ioaddr, PCNET32_TOTAL_SIZE, "pcnet32_probe_vlbus")) {
1512                         /* check if there is really a pcnet chip on that ioaddr */
1513                         if ((inb(ioaddr + 14) == 0x57) &&
1514                             (inb(ioaddr + 15) == 0x57)) {
1515                                 pcnet32_probe1(ioaddr, 0, NULL);
1516                         } else {
1517                                 release_region(ioaddr, PCNET32_TOTAL_SIZE);
1518                         }
1519                 }
1520         }
1521 }
1522
1523 static int
1524 pcnet32_probe_pci(struct pci_dev *pdev, const struct pci_device_id *ent)
1525 {
1526         unsigned long ioaddr;
1527         int err;
1528
1529         err = pci_enable_device(pdev);
1530         if (err < 0) {
1531                 if (pcnet32_debug & NETIF_MSG_PROBE)
1532                         pr_err("failed to enable device -- err=%d\n", err);
1533                 return err;
1534         }
1535         pci_set_master(pdev);
1536
1537         if (!pci_resource_len(pdev, 0)) {
1538                 if (pcnet32_debug & NETIF_MSG_PROBE)
1539                         pr_err("card has no PCI IO resources, aborting\n");
1540                 err = -ENODEV;
1541                 goto err_disable_dev;
1542         }
1543
1544         err = dma_set_mask(&pdev->dev, PCNET32_DMA_MASK);
1545         if (err) {
1546                 if (pcnet32_debug & NETIF_MSG_PROBE)
1547                         pr_err("architecture does not support 32bit PCI busmaster DMA\n");
1548                 goto err_disable_dev;
1549         }
1550
1551         ioaddr = pci_resource_start(pdev, 0);
1552         if (!request_region(ioaddr, PCNET32_TOTAL_SIZE, "pcnet32_probe_pci")) {
1553                 if (pcnet32_debug & NETIF_MSG_PROBE)
1554                         pr_err("io address range already allocated\n");
1555                 err = -EBUSY;
1556                 goto err_disable_dev;
1557         }
1558
1559         err = pcnet32_probe1(ioaddr, 1, pdev);
1560
1561 err_disable_dev:
1562         if (err < 0)
1563                 pci_disable_device(pdev);
1564
1565         return err;
1566 }
1567
1568 static const struct net_device_ops pcnet32_netdev_ops = {
1569         .ndo_open               = pcnet32_open,
1570         .ndo_stop               = pcnet32_close,
1571         .ndo_start_xmit         = pcnet32_start_xmit,
1572         .ndo_tx_timeout         = pcnet32_tx_timeout,
1573         .ndo_get_stats          = pcnet32_get_stats,
1574         .ndo_set_rx_mode        = pcnet32_set_multicast_list,
1575         .ndo_do_ioctl           = pcnet32_ioctl,
1576         .ndo_set_mac_address    = eth_mac_addr,
1577         .ndo_validate_addr      = eth_validate_addr,
1578 #ifdef CONFIG_NET_POLL_CONTROLLER
1579         .ndo_poll_controller    = pcnet32_poll_controller,
1580 #endif
1581 };
1582
1583 /* pcnet32_probe1
1584  *  Called from both pcnet32_probe_vlbus and pcnet_probe_pci.
1585  *  pdev will be NULL when called from pcnet32_probe_vlbus.
1586  */
1587 static int
1588 pcnet32_probe1(unsigned long ioaddr, int shared, struct pci_dev *pdev)
1589 {
1590         struct pcnet32_private *lp;
1591         int i, media;
1592         int fdx, mii, fset, dxsuflo, sram;
1593         int chip_version;
1594         char *chipname;
1595         struct net_device *dev;
1596         const struct pcnet32_access *a = NULL;
1597         u8 promaddr[ETH_ALEN];
1598         int ret = -ENODEV;
1599
1600         /* reset the chip */
1601         pcnet32_wio_reset(ioaddr);
1602
1603         /* NOTE: 16-bit check is first, otherwise some older PCnet chips fail */
1604         if (pcnet32_wio_read_csr(ioaddr, 0) == 4 && pcnet32_wio_check(ioaddr)) {
1605                 a = &pcnet32_wio;
1606         } else {
1607                 pcnet32_dwio_reset(ioaddr);
1608                 if (pcnet32_dwio_read_csr(ioaddr, 0) == 4 &&
1609                     pcnet32_dwio_check(ioaddr)) {
1610                         a = &pcnet32_dwio;
1611                 } else {
1612                         if (pcnet32_debug & NETIF_MSG_PROBE)
1613                                 pr_err("No access methods\n");
1614                         goto err_release_region;
1615                 }
1616         }
1617
1618         chip_version =
1619             a->read_csr(ioaddr, 88) | (a->read_csr(ioaddr, 89) << 16);
1620         if ((pcnet32_debug & NETIF_MSG_PROBE) && (pcnet32_debug & NETIF_MSG_HW))
1621                 pr_info("  PCnet chip version is %#x\n", chip_version);
1622         if ((chip_version & 0xfff) != 0x003) {
1623                 if (pcnet32_debug & NETIF_MSG_PROBE)
1624                         pr_info("Unsupported chip version\n");
1625                 goto err_release_region;
1626         }
1627
1628         /* initialize variables */
1629         fdx = mii = fset = dxsuflo = sram = 0;
1630         chip_version = (chip_version >> 12) & 0xffff;
1631
1632         switch (chip_version) {
1633         case 0x2420:
1634                 chipname = "PCnet/PCI 79C970";  /* PCI */
1635                 break;
1636         case 0x2430:
1637                 if (shared)
1638                         chipname = "PCnet/PCI 79C970";  /* 970 gives the wrong chip id back */
1639                 else
1640                         chipname = "PCnet/32 79C965";   /* 486/VL bus */
1641                 break;
1642         case 0x2621:
1643                 chipname = "PCnet/PCI II 79C970A";      /* PCI */
1644                 fdx = 1;
1645                 break;
1646         case 0x2623:
1647                 chipname = "PCnet/FAST 79C971"; /* PCI */
1648                 fdx = 1;
1649                 mii = 1;
1650                 fset = 1;
1651                 break;
1652         case 0x2624:
1653                 chipname = "PCnet/FAST+ 79C972";        /* PCI */
1654                 fdx = 1;
1655                 mii = 1;
1656                 fset = 1;
1657                 break;
1658         case 0x2625:
1659                 chipname = "PCnet/FAST III 79C973";     /* PCI */
1660                 fdx = 1;
1661                 mii = 1;
1662                 sram = 1;
1663                 break;
1664         case 0x2626:
1665                 chipname = "PCnet/Home 79C978"; /* PCI */
1666                 fdx = 1;
1667                 /*
1668                  * This is based on specs published at www.amd.com.  This section
1669                  * assumes that a card with a 79C978 wants to go into standard
1670                  * ethernet mode.  The 79C978 can also go into 1Mb HomePNA mode,
1671                  * and the module option homepna=1 can select this instead.
1672                  */
1673                 media = a->read_bcr(ioaddr, 49);
1674                 media &= ~3;    /* default to 10Mb ethernet */
1675                 if (cards_found < MAX_UNITS && homepna[cards_found])
1676                         media |= 1;     /* switch to home wiring mode */
1677                 if (pcnet32_debug & NETIF_MSG_PROBE)
1678                         printk(KERN_DEBUG PFX "media set to %sMbit mode\n",
1679                                (media & 1) ? "1" : "10");
1680                 a->write_bcr(ioaddr, 49, media);
1681                 break;
1682         case 0x2627:
1683                 chipname = "PCnet/FAST III 79C975";     /* PCI */
1684                 fdx = 1;
1685                 mii = 1;
1686                 sram = 1;
1687                 break;
1688         case 0x2628:
1689                 chipname = "PCnet/PRO 79C976";
1690                 fdx = 1;
1691                 mii = 1;
1692                 break;
1693         default:
1694                 if (pcnet32_debug & NETIF_MSG_PROBE)
1695                         pr_info("PCnet version %#x, no PCnet32 chip\n",
1696                                 chip_version);
1697                 goto err_release_region;
1698         }
1699
1700         /*
1701          *  On selected chips turn on the BCR18:NOUFLO bit. This stops transmit
1702          *  starting until the packet is loaded. Strike one for reliability, lose
1703          *  one for latency - although on PCI this isn't a big loss. Older chips
1704          *  have FIFO's smaller than a packet, so you can't do this.
1705          *  Turn on BCR18:BurstRdEn and BCR18:BurstWrEn.
1706          */
1707
1708         if (fset) {
1709                 a->write_bcr(ioaddr, 18, (a->read_bcr(ioaddr, 18) | 0x0860));
1710                 a->write_csr(ioaddr, 80,
1711                              (a->read_csr(ioaddr, 80) & 0x0C00) | 0x0c00);
1712                 dxsuflo = 1;
1713         }
1714
1715         /*
1716          * The Am79C973/Am79C975 controllers come with 12K of SRAM
1717          * which we can use for the Tx/Rx buffers but most importantly,
1718          * the use of SRAM allow us to use the BCR18:NOUFLO bit to avoid
1719          * Tx fifo underflows.
1720          */
1721         if (sram) {
1722                 /*
1723                  * The SRAM is being configured in two steps. First we
1724                  * set the SRAM size in the BCR25:SRAM_SIZE bits. According
1725                  * to the datasheet, each bit corresponds to a 512-byte
1726                  * page so we can have at most 24 pages. The SRAM_SIZE
1727                  * holds the value of the upper 8 bits of the 16-bit SRAM size.
1728                  * The low 8-bits start at 0x00 and end at 0xff. So the
1729                  * address range is from 0x0000 up to 0x17ff. Therefore,
1730                  * the SRAM_SIZE is set to 0x17. The next step is to set
1731                  * the BCR26:SRAM_BND midway through so the Tx and Rx
1732                  * buffers can share the SRAM equally.
1733                  */
1734                 a->write_bcr(ioaddr, 25, 0x17);
1735                 a->write_bcr(ioaddr, 26, 0xc);
1736                 /* And finally enable the NOUFLO bit */
1737                 a->write_bcr(ioaddr, 18, a->read_bcr(ioaddr, 18) | (1 << 11));
1738         }
1739
1740         dev = alloc_etherdev(sizeof(*lp));
1741         if (!dev) {
1742                 ret = -ENOMEM;
1743                 goto err_release_region;
1744         }
1745
1746         if (pdev)
1747                 SET_NETDEV_DEV(dev, &pdev->dev);
1748
1749         if (pcnet32_debug & NETIF_MSG_PROBE)
1750                 pr_info("%s at %#3lx,", chipname, ioaddr);
1751
1752         /* In most chips, after a chip reset, the ethernet address is read from the
1753          * station address PROM at the base address and programmed into the
1754          * "Physical Address Registers" CSR12-14.
1755          * As a precautionary measure, we read the PROM values and complain if
1756          * they disagree with the CSRs.  If they miscompare, and the PROM addr
1757          * is valid, then the PROM addr is used.
1758          */
1759         for (i = 0; i < 3; i++) {
1760                 unsigned int val;
1761                 val = a->read_csr(ioaddr, i + 12) & 0x0ffff;
1762                 /* There may be endianness issues here. */
1763                 dev->dev_addr[2 * i] = val & 0x0ff;
1764                 dev->dev_addr[2 * i + 1] = (val >> 8) & 0x0ff;
1765         }
1766
1767         /* read PROM address and compare with CSR address */
1768         for (i = 0; i < ETH_ALEN; i++)
1769                 promaddr[i] = inb(ioaddr + i);
1770
1771         if (!ether_addr_equal(promaddr, dev->dev_addr) ||
1772             !is_valid_ether_addr(dev->dev_addr)) {
1773                 if (is_valid_ether_addr(promaddr)) {
1774                         if (pcnet32_debug & NETIF_MSG_PROBE) {
1775                                 pr_cont(" warning: CSR address invalid,\n");
1776                                 pr_info("    using instead PROM address of");
1777                         }
1778                         memcpy(dev->dev_addr, promaddr, ETH_ALEN);
1779                 }
1780         }
1781
1782         /* if the ethernet address is not valid, force to 00:00:00:00:00:00 */
1783         if (!is_valid_ether_addr(dev->dev_addr))
1784                 eth_zero_addr(dev->dev_addr);
1785
1786         if (pcnet32_debug & NETIF_MSG_PROBE) {
1787                 pr_cont(" %pM", dev->dev_addr);
1788
1789                 /* Version 0x2623 and 0x2624 */
1790                 if (((chip_version + 1) & 0xfffe) == 0x2624) {
1791                         i = a->read_csr(ioaddr, 80) & 0x0C00;   /* Check tx_start_pt */
1792                         pr_info("    tx_start_pt(0x%04x):", i);
1793                         switch (i >> 10) {
1794                         case 0:
1795                                 pr_cont("  20 bytes,");
1796                                 break;
1797                         case 1:
1798                                 pr_cont("  64 bytes,");
1799                                 break;
1800                         case 2:
1801                                 pr_cont(" 128 bytes,");
1802                                 break;
1803                         case 3:
1804                                 pr_cont("~220 bytes,");
1805                                 break;
1806                         }
1807                         i = a->read_bcr(ioaddr, 18);    /* Check Burst/Bus control */
1808                         pr_cont(" BCR18(%x):", i & 0xffff);
1809                         if (i & (1 << 5))
1810                                 pr_cont("BurstWrEn ");
1811                         if (i & (1 << 6))
1812                                 pr_cont("BurstRdEn ");
1813                         if (i & (1 << 7))
1814                                 pr_cont("DWordIO ");
1815                         if (i & (1 << 11))
1816                                 pr_cont("NoUFlow ");
1817                         i = a->read_bcr(ioaddr, 25);
1818                         pr_info("    SRAMSIZE=0x%04x,", i << 8);
1819                         i = a->read_bcr(ioaddr, 26);
1820                         pr_cont(" SRAM_BND=0x%04x,", i << 8);
1821                         i = a->read_bcr(ioaddr, 27);
1822                         if (i & (1 << 14))
1823                                 pr_cont("LowLatRx");
1824                 }
1825         }
1826
1827         dev->base_addr = ioaddr;
1828         lp = netdev_priv(dev);
1829         /* dma_alloc_coherent returns page-aligned memory, so we do not have to check the alignment */
1830         lp->init_block = dma_alloc_coherent(&pdev->dev,
1831                                             sizeof(*lp->init_block),
1832                                             &lp->init_dma_addr, GFP_KERNEL);
1833         if (!lp->init_block) {
1834                 if (pcnet32_debug & NETIF_MSG_PROBE)
1835                         pr_err("Coherent memory allocation failed\n");
1836                 ret = -ENOMEM;
1837                 goto err_free_netdev;
1838         }
1839         lp->pci_dev = pdev;
1840
1841         lp->dev = dev;
1842
1843         spin_lock_init(&lp->lock);
1844
1845         lp->name = chipname;
1846         lp->shared_irq = shared;
1847         lp->tx_ring_size = TX_RING_SIZE;        /* default tx ring size */
1848         lp->rx_ring_size = RX_RING_SIZE;        /* default rx ring size */
1849         lp->tx_mod_mask = lp->tx_ring_size - 1;
1850         lp->rx_mod_mask = lp->rx_ring_size - 1;
1851         lp->tx_len_bits = (PCNET32_LOG_TX_BUFFERS << 12);
1852         lp->rx_len_bits = (PCNET32_LOG_RX_BUFFERS << 4);
1853         lp->mii_if.full_duplex = fdx;
1854         lp->mii_if.phy_id_mask = 0x1f;
1855         lp->mii_if.reg_num_mask = 0x1f;
1856         lp->dxsuflo = dxsuflo;
1857         lp->mii = mii;
1858         lp->chip_version = chip_version;
1859         lp->msg_enable = pcnet32_debug;
1860         if ((cards_found >= MAX_UNITS) ||
1861             (options[cards_found] >= sizeof(options_mapping)))
1862                 lp->options = PCNET32_PORT_ASEL;
1863         else
1864                 lp->options = options_mapping[options[cards_found]];
1865         /* force default port to TP on 79C970A so link detection can work */
1866         if (lp->chip_version == PCNET32_79C970A)
1867                 lp->options = PCNET32_PORT_10BT;
1868         lp->mii_if.dev = dev;
1869         lp->mii_if.mdio_read = mdio_read;
1870         lp->mii_if.mdio_write = mdio_write;
1871
1872         /* napi.weight is used in both the napi and non-napi cases */
1873         lp->napi.weight = lp->rx_ring_size / 2;
1874
1875         netif_napi_add(dev, &lp->napi, pcnet32_poll, lp->rx_ring_size / 2);
1876
1877         if (fdx && !(lp->options & PCNET32_PORT_ASEL) &&
1878             ((cards_found >= MAX_UNITS) || full_duplex[cards_found]))
1879                 lp->options |= PCNET32_PORT_FD;
1880
1881         lp->a = a;
1882
1883         /* prior to register_netdev, dev->name is not yet correct */
1884         if (pcnet32_alloc_ring(dev, pci_name(lp->pci_dev))) {
1885                 ret = -ENOMEM;
1886                 goto err_free_ring;
1887         }
1888         /* detect special T1/E1 WAN card by checking for MAC address */
1889         if (dev->dev_addr[0] == 0x00 && dev->dev_addr[1] == 0xe0 &&
1890             dev->dev_addr[2] == 0x75)
1891                 lp->options = PCNET32_PORT_FD | PCNET32_PORT_GPSI;
1892
1893         lp->init_block->mode = cpu_to_le16(0x0003);     /* Disable Rx and Tx. */
1894         lp->init_block->tlen_rlen =
1895             cpu_to_le16(lp->tx_len_bits | lp->rx_len_bits);
1896         for (i = 0; i < 6; i++)
1897                 lp->init_block->phys_addr[i] = dev->dev_addr[i];
1898         lp->init_block->filter[0] = 0x00000000;
1899         lp->init_block->filter[1] = 0x00000000;
1900         lp->init_block->rx_ring = cpu_to_le32(lp->rx_ring_dma_addr);
1901         lp->init_block->tx_ring = cpu_to_le32(lp->tx_ring_dma_addr);
1902
1903         /* switch pcnet32 to 32bit mode */
1904         a->write_bcr(ioaddr, 20, 2);
1905
1906         a->write_csr(ioaddr, 1, (lp->init_dma_addr & 0xffff));
1907         a->write_csr(ioaddr, 2, (lp->init_dma_addr >> 16));
1908
1909         if (pdev) {             /* use the IRQ provided by PCI */
1910                 dev->irq = pdev->irq;
1911                 if (pcnet32_debug & NETIF_MSG_PROBE)
1912                         pr_cont(" assigned IRQ %d\n", dev->irq);
1913         } else {
1914                 unsigned long irq_mask = probe_irq_on();
1915
1916                 /*
1917                  * To auto-IRQ we enable the initialization-done and DMA error
1918                  * interrupts. For ISA boards we get a DMA error, but VLB and PCI
1919                  * boards will work.
1920                  */
1921                 /* Trigger an initialization just for the interrupt. */
1922                 a->write_csr(ioaddr, CSR0, CSR0_INTEN | CSR0_INIT);
1923                 mdelay(1);
1924
1925                 dev->irq = probe_irq_off(irq_mask);
1926                 if (!dev->irq) {
1927                         if (pcnet32_debug & NETIF_MSG_PROBE)
1928                                 pr_cont(", failed to detect IRQ line\n");
1929                         ret = -ENODEV;
1930                         goto err_free_ring;
1931                 }
1932                 if (pcnet32_debug & NETIF_MSG_PROBE)
1933                         pr_cont(", probed IRQ %d\n", dev->irq);
1934         }
1935
1936         /* Set the mii phy_id so that we can query the link state */
1937         if (lp->mii) {
1938                 /* lp->phycount and lp->phymask are set to 0 by memset above */
1939
1940                 lp->mii_if.phy_id = ((lp->a->read_bcr(ioaddr, 33)) >> 5) & 0x1f;
1941                 /* scan for PHYs */
1942                 for (i = 0; i < PCNET32_MAX_PHYS; i++) {
1943                         unsigned short id1, id2;
1944
1945                         id1 = mdio_read(dev, i, MII_PHYSID1);
1946                         if (id1 == 0xffff)
1947                                 continue;
1948                         id2 = mdio_read(dev, i, MII_PHYSID2);
1949                         if (id2 == 0xffff)
1950                                 continue;
1951                         if (i == 31 && ((chip_version + 1) & 0xfffe) == 0x2624)
1952                                 continue;       /* 79C971 & 79C972 have phantom phy at id 31 */
1953                         lp->phycount++;
1954                         lp->phymask |= (1 << i);
1955                         lp->mii_if.phy_id = i;
1956                         if (pcnet32_debug & NETIF_MSG_PROBE)
1957                                 pr_info("Found PHY %04x:%04x at address %d\n",
1958                                         id1, id2, i);
1959                 }
1960                 lp->a->write_bcr(ioaddr, 33, (lp->mii_if.phy_id) << 5);
1961                 if (lp->phycount > 1)
1962                         lp->options |= PCNET32_PORT_MII;
1963         }
1964
1965         timer_setup(&lp->watchdog_timer, pcnet32_watchdog, 0);
1966
1967         /* The PCNET32-specific entries in the device structure. */
1968         dev->netdev_ops = &pcnet32_netdev_ops;
1969         dev->ethtool_ops = &pcnet32_ethtool_ops;
1970         dev->watchdog_timeo = (5 * HZ);
1971
1972         /* Fill in the generic fields of the device structure. */
1973         if (register_netdev(dev))
1974                 goto err_free_ring;
1975
1976         if (pdev) {
1977                 pci_set_drvdata(pdev, dev);
1978         } else {
1979                 lp->next = pcnet32_dev;
1980                 pcnet32_dev = dev;
1981         }
1982
1983         if (pcnet32_debug & NETIF_MSG_PROBE)
1984                 pr_info("%s: registered as %s\n", dev->name, lp->name);
1985         cards_found++;
1986
1987         /* enable LED writes */
1988         a->write_bcr(ioaddr, 2, a->read_bcr(ioaddr, 2) | 0x1000);
1989
1990         return 0;
1991
1992 err_free_ring:
1993         pcnet32_free_ring(dev);
1994         dma_free_coherent(&lp->pci_dev->dev, sizeof(*lp->init_block),
1995                           lp->init_block, lp->init_dma_addr);
1996 err_free_netdev:
1997         free_netdev(dev);
1998 err_release_region:
1999         release_region(ioaddr, PCNET32_TOTAL_SIZE);
2000         return ret;
2001 }
2002
2003 /* if any allocation fails, caller must also call pcnet32_free_ring */
2004 static int pcnet32_alloc_ring(struct net_device *dev, const char *name)
2005 {
2006         struct pcnet32_private *lp = netdev_priv(dev);
2007
2008         lp->tx_ring = dma_alloc_coherent(&lp->pci_dev->dev,
2009                                          sizeof(struct pcnet32_tx_head) * lp->tx_ring_size,
2010                                          &lp->tx_ring_dma_addr, GFP_KERNEL);
2011         if (lp->tx_ring == NULL) {
2012                 netif_err(lp, drv, dev, "Coherent memory allocation failed\n");
2013                 return -ENOMEM;
2014         }
2015
2016         lp->rx_ring = dma_alloc_coherent(&lp->pci_dev->dev,
2017                                          sizeof(struct pcnet32_rx_head) * lp->rx_ring_size,
2018                                          &lp->rx_ring_dma_addr, GFP_KERNEL);
2019         if (lp->rx_ring == NULL) {
2020                 netif_err(lp, drv, dev, "Coherent memory allocation failed\n");
2021                 return -ENOMEM;
2022         }
2023
2024         lp->tx_dma_addr = kcalloc(lp->tx_ring_size, sizeof(dma_addr_t),
2025                                   GFP_KERNEL);
2026         if (!lp->tx_dma_addr)
2027                 return -ENOMEM;
2028
2029         lp->rx_dma_addr = kcalloc(lp->rx_ring_size, sizeof(dma_addr_t),
2030                                   GFP_KERNEL);
2031         if (!lp->rx_dma_addr)
2032                 return -ENOMEM;
2033
2034         lp->tx_skbuff = kcalloc(lp->tx_ring_size, sizeof(struct sk_buff *),
2035                                 GFP_KERNEL);
2036         if (!lp->tx_skbuff)
2037                 return -ENOMEM;
2038
2039         lp->rx_skbuff = kcalloc(lp->rx_ring_size, sizeof(struct sk_buff *),
2040                                 GFP_KERNEL);
2041         if (!lp->rx_skbuff)
2042                 return -ENOMEM;
2043
2044         return 0;
2045 }
2046
2047 static void pcnet32_free_ring(struct net_device *dev)
2048 {
2049         struct pcnet32_private *lp = netdev_priv(dev);
2050
2051         kfree(lp->tx_skbuff);
2052         lp->tx_skbuff = NULL;
2053
2054         kfree(lp->rx_skbuff);
2055         lp->rx_skbuff = NULL;
2056
2057         kfree(lp->tx_dma_addr);
2058         lp->tx_dma_addr = NULL;
2059
2060         kfree(lp->rx_dma_addr);
2061         lp->rx_dma_addr = NULL;
2062
2063         if (lp->tx_ring) {
2064                 dma_free_coherent(&lp->pci_dev->dev,
2065                                   sizeof(struct pcnet32_tx_head) * lp->tx_ring_size,
2066                                   lp->tx_ring, lp->tx_ring_dma_addr);
2067                 lp->tx_ring = NULL;
2068         }
2069
2070         if (lp->rx_ring) {
2071                 dma_free_coherent(&lp->pci_dev->dev,
2072                                   sizeof(struct pcnet32_rx_head) * lp->rx_ring_size,
2073                                   lp->rx_ring, lp->rx_ring_dma_addr);
2074                 lp->rx_ring = NULL;
2075         }
2076 }
2077
2078 static int pcnet32_open(struct net_device *dev)
2079 {
2080         struct pcnet32_private *lp = netdev_priv(dev);
2081         struct pci_dev *pdev = lp->pci_dev;
2082         unsigned long ioaddr = dev->base_addr;
2083         u16 val;
2084         int i;
2085         int rc;
2086         unsigned long flags;
2087
2088         if (request_irq(dev->irq, pcnet32_interrupt,
2089                         lp->shared_irq ? IRQF_SHARED : 0, dev->name,
2090                         (void *)dev)) {
2091                 return -EAGAIN;
2092         }
2093
2094         spin_lock_irqsave(&lp->lock, flags);
2095         /* Check for a valid station address */
2096         if (!is_valid_ether_addr(dev->dev_addr)) {
2097                 rc = -EINVAL;
2098                 goto err_free_irq;
2099         }
2100
2101         /* Reset the PCNET32 */
2102         lp->a->reset(ioaddr);
2103
2104         /* switch pcnet32 to 32bit mode */
2105         lp->a->write_bcr(ioaddr, 20, 2);
2106
2107         netif_printk(lp, ifup, KERN_DEBUG, dev,
2108                      "%s() irq %d tx/rx rings %#x/%#x init %#x\n",
2109                      __func__, dev->irq, (u32) (lp->tx_ring_dma_addr),
2110                      (u32) (lp->rx_ring_dma_addr),
2111                      (u32) (lp->init_dma_addr));
2112
2113         lp->autoneg = !!(lp->options & PCNET32_PORT_ASEL);
2114         lp->port_tp = !!(lp->options & PCNET32_PORT_10BT);
2115         lp->fdx = !!(lp->options & PCNET32_PORT_FD);
2116
2117         /* set/reset autoselect bit */
2118         val = lp->a->read_bcr(ioaddr, 2) & ~2;
2119         if (lp->options & PCNET32_PORT_ASEL)
2120                 val |= 2;
2121         lp->a->write_bcr(ioaddr, 2, val);
2122
2123         /* handle full duplex setting */
2124         if (lp->mii_if.full_duplex) {
2125                 val = lp->a->read_bcr(ioaddr, 9) & ~3;
2126                 if (lp->options & PCNET32_PORT_FD) {
2127                         val |= 1;
2128                         if (lp->options == (PCNET32_PORT_FD | PCNET32_PORT_AUI))
2129                                 val |= 2;
2130                 } else if (lp->options & PCNET32_PORT_ASEL) {
2131                         /* workaround of xSeries250, turn on for 79C975 only */
2132                         if (lp->chip_version == 0x2627)
2133                                 val |= 3;
2134                 }
2135                 lp->a->write_bcr(ioaddr, 9, val);
2136         }
2137
2138         /* set/reset GPSI bit in test register */
2139         val = lp->a->read_csr(ioaddr, 124) & ~0x10;
2140         if ((lp->options & PCNET32_PORT_PORTSEL) == PCNET32_PORT_GPSI)
2141                 val |= 0x10;
2142         lp->a->write_csr(ioaddr, 124, val);
2143
2144         /* Allied Telesyn AT 2700/2701 FX are 100Mbit only and do not negotiate */
2145         if (pdev && pdev->subsystem_vendor == PCI_VENDOR_ID_AT &&
2146             (pdev->subsystem_device == PCI_SUBDEVICE_ID_AT_2700FX ||
2147              pdev->subsystem_device == PCI_SUBDEVICE_ID_AT_2701FX)) {
2148                 if (lp->options & PCNET32_PORT_ASEL) {
2149                         lp->options = PCNET32_PORT_FD | PCNET32_PORT_100;
2150                         netif_printk(lp, link, KERN_DEBUG, dev,
2151                                      "Setting 100Mb-Full Duplex\n");
2152                 }
2153         }
2154         if (lp->phycount < 2) {
2155                 /*
2156                  * 24 Jun 2004 according AMD, in order to change the PHY,
2157                  * DANAS (or DISPM for 79C976) must be set; then select the speed,
2158                  * duplex, and/or enable auto negotiation, and clear DANAS
2159                  */
2160                 if (lp->mii && !(lp->options & PCNET32_PORT_ASEL)) {
2161                         lp->a->write_bcr(ioaddr, 32,
2162                                         lp->a->read_bcr(ioaddr, 32) | 0x0080);
2163                         /* disable Auto Negotiation, set 10Mpbs, HD */
2164                         val = lp->a->read_bcr(ioaddr, 32) & ~0xb8;
2165                         if (lp->options & PCNET32_PORT_FD)
2166                                 val |= 0x10;
2167                         if (lp->options & PCNET32_PORT_100)
2168                                 val |= 0x08;
2169                         lp->a->write_bcr(ioaddr, 32, val);
2170                 } else {
2171                         if (lp->options & PCNET32_PORT_ASEL) {
2172                                 lp->a->write_bcr(ioaddr, 32,
2173                                                 lp->a->read_bcr(ioaddr,
2174                                                                32) | 0x0080);
2175                                 /* enable auto negotiate, setup, disable fd */
2176                                 val = lp->a->read_bcr(ioaddr, 32) & ~0x98;
2177                                 val |= 0x20;
2178                                 lp->a->write_bcr(ioaddr, 32, val);
2179                         }
2180                 }
2181         } else {
2182                 int first_phy = -1;
2183                 u16 bmcr;
2184                 u32 bcr9;
2185                 struct ethtool_cmd ecmd = { .cmd = ETHTOOL_GSET };
2186
2187                 /*
2188                  * There is really no good other way to handle multiple PHYs
2189                  * other than turning off all automatics
2190                  */
2191                 val = lp->a->read_bcr(ioaddr, 2);
2192                 lp->a->write_bcr(ioaddr, 2, val & ~2);
2193                 val = lp->a->read_bcr(ioaddr, 32);
2194                 lp->a->write_bcr(ioaddr, 32, val & ~(1 << 7));  /* stop MII manager */
2195
2196                 if (!(lp->options & PCNET32_PORT_ASEL)) {
2197                         /* setup ecmd */
2198                         ecmd.port = PORT_MII;
2199                         ecmd.transceiver = XCVR_INTERNAL;
2200                         ecmd.autoneg = AUTONEG_DISABLE;
2201                         ethtool_cmd_speed_set(&ecmd,
2202                                               (lp->options & PCNET32_PORT_100) ?
2203                                               SPEED_100 : SPEED_10);
2204                         bcr9 = lp->a->read_bcr(ioaddr, 9);
2205
2206                         if (lp->options & PCNET32_PORT_FD) {
2207                                 ecmd.duplex = DUPLEX_FULL;
2208                                 bcr9 |= (1 << 0);
2209                         } else {
2210                                 ecmd.duplex = DUPLEX_HALF;
2211                                 bcr9 |= ~(1 << 0);
2212                         }
2213                         lp->a->write_bcr(ioaddr, 9, bcr9);
2214                 }
2215
2216                 for (i = 0; i < PCNET32_MAX_PHYS; i++) {
2217                         if (lp->phymask & (1 << i)) {
2218                                 /* isolate all but the first PHY */
2219                                 bmcr = mdio_read(dev, i, MII_BMCR);
2220                                 if (first_phy == -1) {
2221                                         first_phy = i;
2222                                         mdio_write(dev, i, MII_BMCR,
2223                                                    bmcr & ~BMCR_ISOLATE);
2224                                 } else {
2225                                         mdio_write(dev, i, MII_BMCR,
2226                                                    bmcr | BMCR_ISOLATE);
2227                                 }
2228                                 /* use mii_ethtool_sset to setup PHY */
2229                                 lp->mii_if.phy_id = i;
2230                                 ecmd.phy_address = i;
2231                                 if (lp->options & PCNET32_PORT_ASEL) {
2232                                         mii_ethtool_gset(&lp->mii_if, &ecmd);
2233                                         ecmd.autoneg = AUTONEG_ENABLE;
2234                                 }
2235                                 mii_ethtool_sset(&lp->mii_if, &ecmd);
2236                         }
2237                 }
2238                 lp->mii_if.phy_id = first_phy;
2239                 netif_info(lp, link, dev, "Using PHY number %d\n", first_phy);
2240         }
2241
2242 #ifdef DO_DXSUFLO
2243         if (lp->dxsuflo) {      /* Disable transmit stop on underflow */
2244                 val = lp->a->read_csr(ioaddr, CSR3);
2245                 val |= 0x40;
2246                 lp->a->write_csr(ioaddr, CSR3, val);
2247         }
2248 #endif
2249
2250         lp->init_block->mode =
2251             cpu_to_le16((lp->options & PCNET32_PORT_PORTSEL) << 7);
2252         pcnet32_load_multicast(dev);
2253
2254         if (pcnet32_init_ring(dev)) {
2255                 rc = -ENOMEM;
2256                 goto err_free_ring;
2257         }
2258
2259         napi_enable(&lp->napi);
2260
2261         /* Re-initialize the PCNET32, and start it when done. */
2262         lp->a->write_csr(ioaddr, 1, (lp->init_dma_addr & 0xffff));
2263         lp->a->write_csr(ioaddr, 2, (lp->init_dma_addr >> 16));
2264
2265         lp->a->write_csr(ioaddr, CSR4, 0x0915); /* auto tx pad */
2266         lp->a->write_csr(ioaddr, CSR0, CSR0_INIT);
2267
2268         netif_start_queue(dev);
2269
2270         if (lp->chip_version >= PCNET32_79C970A) {
2271                 /* Print the link status and start the watchdog */
2272                 pcnet32_check_media(dev, 1);
2273                 mod_timer(&lp->watchdog_timer, PCNET32_WATCHDOG_TIMEOUT);
2274         }
2275
2276         i = 0;
2277         while (i++ < 100)
2278                 if (lp->a->read_csr(ioaddr, CSR0) & CSR0_IDON)
2279                         break;
2280         /*
2281          * We used to clear the InitDone bit, 0x0100, here but Mark Stockton
2282          * reports that doing so triggers a bug in the '974.
2283          */
2284         lp->a->write_csr(ioaddr, CSR0, CSR0_NORMAL);
2285
2286         netif_printk(lp, ifup, KERN_DEBUG, dev,
2287                      "pcnet32 open after %d ticks, init block %#x csr0 %4.4x\n",
2288                      i,
2289                      (u32) (lp->init_dma_addr),
2290                      lp->a->read_csr(ioaddr, CSR0));
2291
2292         spin_unlock_irqrestore(&lp->lock, flags);
2293
2294         return 0;               /* Always succeed */
2295
2296 err_free_ring:
2297         /* free any allocated skbuffs */
2298         pcnet32_purge_rx_ring(dev);
2299
2300         /*
2301          * Switch back to 16bit mode to avoid problems with dumb
2302          * DOS packet driver after a warm reboot
2303          */
2304         lp->a->write_bcr(ioaddr, 20, 4);
2305
2306 err_free_irq:
2307         spin_unlock_irqrestore(&lp->lock, flags);
2308         free_irq(dev->irq, dev);
2309         return rc;
2310 }
2311
2312 /*
2313  * The LANCE has been halted for one reason or another (busmaster memory
2314  * arbitration error, Tx FIFO underflow, driver stopped it to reconfigure,
2315  * etc.).  Modern LANCE variants always reload their ring-buffer
2316  * configuration when restarted, so we must reinitialize our ring
2317  * context before restarting.  As part of this reinitialization,
2318  * find all packets still on the Tx ring and pretend that they had been
2319  * sent (in effect, drop the packets on the floor) - the higher-level
2320  * protocols will time out and retransmit.  It'd be better to shuffle
2321  * these skbs to a temp list and then actually re-Tx them after
2322  * restarting the chip, but I'm too lazy to do so right now.  dplatt@3do.com
2323  */
2324
2325 static void pcnet32_purge_tx_ring(struct net_device *dev)
2326 {
2327         struct pcnet32_private *lp = netdev_priv(dev);
2328         int i;
2329
2330         for (i = 0; i < lp->tx_ring_size; i++) {
2331                 lp->tx_ring[i].status = 0;      /* CPU owns buffer */
2332                 wmb();          /* Make sure adapter sees owner change */
2333                 if (lp->tx_skbuff[i]) {
2334                         if (!dma_mapping_error(&lp->pci_dev->dev, lp->tx_dma_addr[i]))
2335                                 dma_unmap_single(&lp->pci_dev->dev,
2336                                                  lp->tx_dma_addr[i],
2337                                                  lp->tx_skbuff[i]->len,
2338                                                  DMA_TO_DEVICE);
2339                         dev_kfree_skb_any(lp->tx_skbuff[i]);
2340                 }
2341                 lp->tx_skbuff[i] = NULL;
2342                 lp->tx_dma_addr[i] = 0;
2343         }
2344 }
2345
2346 /* Initialize the PCNET32 Rx and Tx rings. */
2347 static int pcnet32_init_ring(struct net_device *dev)
2348 {
2349         struct pcnet32_private *lp = netdev_priv(dev);
2350         int i;
2351
2352         lp->tx_full = 0;
2353         lp->cur_rx = lp->cur_tx = 0;
2354         lp->dirty_rx = lp->dirty_tx = 0;
2355
2356         for (i = 0; i < lp->rx_ring_size; i++) {
2357                 struct sk_buff *rx_skbuff = lp->rx_skbuff[i];
2358                 if (rx_skbuff == NULL) {
2359                         lp->rx_skbuff[i] = netdev_alloc_skb(dev, PKT_BUF_SKB);
2360                         rx_skbuff = lp->rx_skbuff[i];
2361                         if (!rx_skbuff) {
2362                                 /* there is not much we can do at this point */
2363                                 netif_err(lp, drv, dev, "%s netdev_alloc_skb failed\n",
2364                                           __func__);
2365                                 return -1;
2366                         }
2367                         skb_reserve(rx_skbuff, NET_IP_ALIGN);
2368                 }
2369
2370                 rmb();
2371                 if (lp->rx_dma_addr[i] == 0) {
2372                         lp->rx_dma_addr[i] =
2373                             dma_map_single(&lp->pci_dev->dev, rx_skbuff->data,
2374                                            PKT_BUF_SIZE, DMA_FROM_DEVICE);
2375                         if (dma_mapping_error(&lp->pci_dev->dev, lp->rx_dma_addr[i])) {
2376                                 /* there is not much we can do at this point */
2377                                 netif_err(lp, drv, dev,
2378                                           "%s pci dma mapping error\n",
2379                                           __func__);
2380                                 return -1;
2381                         }
2382                 }
2383                 lp->rx_ring[i].base = cpu_to_le32(lp->rx_dma_addr[i]);
2384                 lp->rx_ring[i].buf_length = cpu_to_le16(NEG_BUF_SIZE);
2385                 wmb();          /* Make sure owner changes after all others are visible */
2386                 lp->rx_ring[i].status = cpu_to_le16(0x8000);
2387         }
2388         /* The Tx buffer address is filled in as needed, but we do need to clear
2389          * the upper ownership bit. */
2390         for (i = 0; i < lp->tx_ring_size; i++) {
2391                 lp->tx_ring[i].status = 0;      /* CPU owns buffer */
2392                 wmb();          /* Make sure adapter sees owner change */
2393                 lp->tx_ring[i].base = 0;
2394                 lp->tx_dma_addr[i] = 0;
2395         }
2396
2397         lp->init_block->tlen_rlen =
2398             cpu_to_le16(lp->tx_len_bits | lp->rx_len_bits);
2399         for (i = 0; i < 6; i++)
2400                 lp->init_block->phys_addr[i] = dev->dev_addr[i];
2401         lp->init_block->rx_ring = cpu_to_le32(lp->rx_ring_dma_addr);
2402         lp->init_block->tx_ring = cpu_to_le32(lp->tx_ring_dma_addr);
2403         wmb();                  /* Make sure all changes are visible */
2404         return 0;
2405 }
2406
2407 /* the pcnet32 has been issued a stop or reset.  Wait for the stop bit
2408  * then flush the pending transmit operations, re-initialize the ring,
2409  * and tell the chip to initialize.
2410  */
2411 static void pcnet32_restart(struct net_device *dev, unsigned int csr0_bits)
2412 {
2413         struct pcnet32_private *lp = netdev_priv(dev);
2414         unsigned long ioaddr = dev->base_addr;
2415         int i;
2416
2417         /* wait for stop */
2418         for (i = 0; i < 100; i++)
2419                 if (lp->a->read_csr(ioaddr, CSR0) & CSR0_STOP)
2420                         break;
2421
2422         if (i >= 100)
2423                 netif_err(lp, drv, dev, "%s timed out waiting for stop\n",
2424                           __func__);
2425
2426         pcnet32_purge_tx_ring(dev);
2427         if (pcnet32_init_ring(dev))
2428                 return;
2429
2430         /* ReInit Ring */
2431         lp->a->write_csr(ioaddr, CSR0, CSR0_INIT);
2432         i = 0;
2433         while (i++ < 1000)
2434                 if (lp->a->read_csr(ioaddr, CSR0) & CSR0_IDON)
2435                         break;
2436
2437         lp->a->write_csr(ioaddr, CSR0, csr0_bits);
2438 }
2439
2440 static void pcnet32_tx_timeout(struct net_device *dev, unsigned int txqueue)
2441 {
2442         struct pcnet32_private *lp = netdev_priv(dev);
2443         unsigned long ioaddr = dev->base_addr, flags;
2444
2445         spin_lock_irqsave(&lp->lock, flags);
2446         /* Transmitter timeout, serious problems. */
2447         if (pcnet32_debug & NETIF_MSG_DRV)
2448                 pr_err("%s: transmit timed out, status %4.4x, resetting\n",
2449                        dev->name, lp->a->read_csr(ioaddr, CSR0));
2450         lp->a->write_csr(ioaddr, CSR0, CSR0_STOP);
2451         dev->stats.tx_errors++;
2452         if (netif_msg_tx_err(lp)) {
2453                 int i;
2454                 printk(KERN_DEBUG
2455                        " Ring data dump: dirty_tx %d cur_tx %d%s cur_rx %d.",
2456                        lp->dirty_tx, lp->cur_tx, lp->tx_full ? " (full)" : "",
2457                        lp->cur_rx);
2458                 for (i = 0; i < lp->rx_ring_size; i++)
2459                         printk("%s %08x %04x %08x %04x", i & 1 ? "" : "\n ",
2460                                le32_to_cpu(lp->rx_ring[i].base),
2461                                (-le16_to_cpu(lp->rx_ring[i].buf_length)) &
2462                                0xffff, le32_to_cpu(lp->rx_ring[i].msg_length),
2463                                le16_to_cpu(lp->rx_ring[i].status));
2464                 for (i = 0; i < lp->tx_ring_size; i++)
2465                         printk("%s %08x %04x %08x %04x", i & 1 ? "" : "\n ",
2466                                le32_to_cpu(lp->tx_ring[i].base),
2467                                (-le16_to_cpu(lp->tx_ring[i].length)) & 0xffff,
2468                                le32_to_cpu(lp->tx_ring[i].misc),
2469                                le16_to_cpu(lp->tx_ring[i].status));
2470                 printk("\n");
2471         }
2472         pcnet32_restart(dev, CSR0_NORMAL);
2473
2474         netif_trans_update(dev); /* prevent tx timeout */
2475         netif_wake_queue(dev);
2476
2477         spin_unlock_irqrestore(&lp->lock, flags);
2478 }
2479
2480 static netdev_tx_t pcnet32_start_xmit(struct sk_buff *skb,
2481                                       struct net_device *dev)
2482 {
2483         struct pcnet32_private *lp = netdev_priv(dev);
2484         unsigned long ioaddr = dev->base_addr;
2485         u16 status;
2486         int entry;
2487         unsigned long flags;
2488
2489         spin_lock_irqsave(&lp->lock, flags);
2490
2491         netif_printk(lp, tx_queued, KERN_DEBUG, dev,
2492                      "%s() called, csr0 %4.4x\n",
2493                      __func__, lp->a->read_csr(ioaddr, CSR0));
2494
2495         /* Default status -- will not enable Successful-TxDone
2496          * interrupt when that option is available to us.
2497          */
2498         status = 0x8300;
2499
2500         /* Fill in a Tx ring entry */
2501
2502         /* Mask to ring buffer boundary. */
2503         entry = lp->cur_tx & lp->tx_mod_mask;
2504
2505         /* Caution: the write order is important here, set the status
2506          * with the "ownership" bits last. */
2507
2508         lp->tx_ring[entry].length = cpu_to_le16(-skb->len);
2509
2510         lp->tx_ring[entry].misc = 0x00000000;
2511
2512         lp->tx_dma_addr[entry] =
2513             dma_map_single(&lp->pci_dev->dev, skb->data, skb->len,
2514                            DMA_TO_DEVICE);
2515         if (dma_mapping_error(&lp->pci_dev->dev, lp->tx_dma_addr[entry])) {
2516                 dev_kfree_skb_any(skb);
2517                 dev->stats.tx_dropped++;
2518                 goto drop_packet;
2519         }
2520         lp->tx_skbuff[entry] = skb;
2521         lp->tx_ring[entry].base = cpu_to_le32(lp->tx_dma_addr[entry]);
2522         wmb();                  /* Make sure owner changes after all others are visible */
2523         lp->tx_ring[entry].status = cpu_to_le16(status);
2524
2525         lp->cur_tx++;
2526         dev->stats.tx_bytes += skb->len;
2527
2528         /* Trigger an immediate send poll. */
2529         lp->a->write_csr(ioaddr, CSR0, CSR0_INTEN | CSR0_TXPOLL);
2530
2531         if (lp->tx_ring[(entry + 1) & lp->tx_mod_mask].base != 0) {
2532                 lp->tx_full = 1;
2533                 netif_stop_queue(dev);
2534         }
2535 drop_packet:
2536         spin_unlock_irqrestore(&lp->lock, flags);
2537         return NETDEV_TX_OK;
2538 }
2539
2540 /* The PCNET32 interrupt handler. */
2541 static irqreturn_t
2542 pcnet32_interrupt(int irq, void *dev_id)
2543 {
2544         struct net_device *dev = dev_id;
2545         struct pcnet32_private *lp;
2546         unsigned long ioaddr;
2547         u16 csr0;
2548         int boguscnt = max_interrupt_work;
2549
2550         ioaddr = dev->base_addr;
2551         lp = netdev_priv(dev);
2552
2553         spin_lock(&lp->lock);
2554
2555         csr0 = lp->a->read_csr(ioaddr, CSR0);
2556         while ((csr0 & 0x8f00) && --boguscnt >= 0) {
2557                 if (csr0 == 0xffff)
2558                         break;  /* PCMCIA remove happened */
2559                 /* Acknowledge all of the current interrupt sources ASAP. */
2560                 lp->a->write_csr(ioaddr, CSR0, csr0 & ~0x004f);
2561
2562                 netif_printk(lp, intr, KERN_DEBUG, dev,
2563                              "interrupt  csr0=%#2.2x new csr=%#2.2x\n",
2564                              csr0, lp->a->read_csr(ioaddr, CSR0));
2565
2566                 /* Log misc errors. */
2567                 if (csr0 & 0x4000)
2568                         dev->stats.tx_errors++; /* Tx babble. */
2569                 if (csr0 & 0x1000) {
2570                         /*
2571                          * This happens when our receive ring is full. This
2572                          * shouldn't be a problem as we will see normal rx
2573                          * interrupts for the frames in the receive ring.  But
2574                          * there are some PCI chipsets (I can reproduce this
2575                          * on SP3G with Intel saturn chipset) which have
2576                          * sometimes problems and will fill up the receive
2577                          * ring with error descriptors.  In this situation we
2578                          * don't get a rx interrupt, but a missed frame
2579                          * interrupt sooner or later.
2580                          */
2581                         dev->stats.rx_errors++; /* Missed a Rx frame. */
2582                 }
2583                 if (csr0 & 0x0800) {
2584                         netif_err(lp, drv, dev, "Bus master arbitration failure, status %4.4x\n",
2585                                   csr0);
2586                         /* unlike for the lance, there is no restart needed */
2587                 }
2588                 if (napi_schedule_prep(&lp->napi)) {
2589                         u16 val;
2590                         /* set interrupt masks */
2591                         val = lp->a->read_csr(ioaddr, CSR3);
2592                         val |= 0x5f00;
2593                         lp->a->write_csr(ioaddr, CSR3, val);
2594
2595                         __napi_schedule(&lp->napi);
2596                         break;
2597                 }
2598                 csr0 = lp->a->read_csr(ioaddr, CSR0);
2599         }
2600
2601         netif_printk(lp, intr, KERN_DEBUG, dev,
2602                      "exiting interrupt, csr0=%#4.4x\n",
2603                      lp->a->read_csr(ioaddr, CSR0));
2604
2605         spin_unlock(&lp->lock);
2606
2607         return IRQ_HANDLED;
2608 }
2609
2610 static int pcnet32_close(struct net_device *dev)
2611 {
2612         unsigned long ioaddr = dev->base_addr;
2613         struct pcnet32_private *lp = netdev_priv(dev);
2614         unsigned long flags;
2615
2616         del_timer_sync(&lp->watchdog_timer);
2617
2618         netif_stop_queue(dev);
2619         napi_disable(&lp->napi);
2620
2621         spin_lock_irqsave(&lp->lock, flags);
2622
2623         dev->stats.rx_missed_errors = lp->a->read_csr(ioaddr, 112);
2624
2625         netif_printk(lp, ifdown, KERN_DEBUG, dev,
2626                      "Shutting down ethercard, status was %2.2x\n",
2627                      lp->a->read_csr(ioaddr, CSR0));
2628
2629         /* We stop the PCNET32 here -- it occasionally polls memory if we don't. */
2630         lp->a->write_csr(ioaddr, CSR0, CSR0_STOP);
2631
2632         /*
2633          * Switch back to 16bit mode to avoid problems with dumb
2634          * DOS packet driver after a warm reboot
2635          */
2636         lp->a->write_bcr(ioaddr, 20, 4);
2637
2638         spin_unlock_irqrestore(&lp->lock, flags);
2639
2640         free_irq(dev->irq, dev);
2641
2642         spin_lock_irqsave(&lp->lock, flags);
2643
2644         pcnet32_purge_rx_ring(dev);
2645         pcnet32_purge_tx_ring(dev);
2646
2647         spin_unlock_irqrestore(&lp->lock, flags);
2648
2649         return 0;
2650 }
2651
2652 static struct net_device_stats *pcnet32_get_stats(struct net_device *dev)
2653 {
2654         struct pcnet32_private *lp = netdev_priv(dev);
2655         unsigned long ioaddr = dev->base_addr;
2656         unsigned long flags;
2657
2658         spin_lock_irqsave(&lp->lock, flags);
2659         dev->stats.rx_missed_errors = lp->a->read_csr(ioaddr, 112);
2660         spin_unlock_irqrestore(&lp->lock, flags);
2661
2662         return &dev->stats;
2663 }
2664
2665 /* taken from the sunlance driver, which it took from the depca driver */
2666 static void pcnet32_load_multicast(struct net_device *dev)
2667 {
2668         struct pcnet32_private *lp = netdev_priv(dev);
2669         volatile struct pcnet32_init_block *ib = lp->init_block;
2670         volatile __le16 *mcast_table = (__le16 *)ib->filter;
2671         struct netdev_hw_addr *ha;
2672         unsigned long ioaddr = dev->base_addr;
2673         int i;
2674         u32 crc;
2675
2676         /* set all multicast bits */
2677         if (dev->flags & IFF_ALLMULTI) {
2678                 ib->filter[0] = cpu_to_le32(~0U);
2679                 ib->filter[1] = cpu_to_le32(~0U);
2680                 lp->a->write_csr(ioaddr, PCNET32_MC_FILTER, 0xffff);
2681                 lp->a->write_csr(ioaddr, PCNET32_MC_FILTER+1, 0xffff);
2682                 lp->a->write_csr(ioaddr, PCNET32_MC_FILTER+2, 0xffff);
2683                 lp->a->write_csr(ioaddr, PCNET32_MC_FILTER+3, 0xffff);
2684                 return;
2685         }
2686         /* clear the multicast filter */
2687         ib->filter[0] = 0;
2688         ib->filter[1] = 0;
2689
2690         /* Add addresses */
2691         netdev_for_each_mc_addr(ha, dev) {
2692                 crc = ether_crc_le(6, ha->addr);
2693                 crc = crc >> 26;
2694                 mcast_table[crc >> 4] |= cpu_to_le16(1 << (crc & 0xf));
2695         }
2696         for (i = 0; i < 4; i++)
2697                 lp->a->write_csr(ioaddr, PCNET32_MC_FILTER + i,
2698                                 le16_to_cpu(mcast_table[i]));
2699 }
2700
2701 /*
2702  * Set or clear the multicast filter for this adaptor.
2703  */
2704 static void pcnet32_set_multicast_list(struct net_device *dev)
2705 {
2706         unsigned long ioaddr = dev->base_addr, flags;
2707         struct pcnet32_private *lp = netdev_priv(dev);
2708         int csr15, suspended;
2709
2710         spin_lock_irqsave(&lp->lock, flags);
2711         suspended = pcnet32_suspend(dev, &flags, 0);
2712         csr15 = lp->a->read_csr(ioaddr, CSR15);
2713         if (dev->flags & IFF_PROMISC) {
2714                 /* Log any net taps. */
2715                 netif_info(lp, hw, dev, "Promiscuous mode enabled\n");
2716                 lp->init_block->mode =
2717                     cpu_to_le16(0x8000 | (lp->options & PCNET32_PORT_PORTSEL) <<
2718                                 7);
2719                 lp->a->write_csr(ioaddr, CSR15, csr15 | 0x8000);
2720         } else {
2721                 lp->init_block->mode =
2722                     cpu_to_le16((lp->options & PCNET32_PORT_PORTSEL) << 7);
2723                 lp->a->write_csr(ioaddr, CSR15, csr15 & 0x7fff);
2724                 pcnet32_load_multicast(dev);
2725         }
2726
2727         if (suspended) {
2728                 pcnet32_clr_suspend(lp, ioaddr);
2729         } else {
2730                 lp->a->write_csr(ioaddr, CSR0, CSR0_STOP);
2731                 pcnet32_restart(dev, CSR0_NORMAL);
2732                 netif_wake_queue(dev);
2733         }
2734
2735         spin_unlock_irqrestore(&lp->lock, flags);
2736 }
2737
2738 /* This routine assumes that the lp->lock is held */
2739 static int mdio_read(struct net_device *dev, int phy_id, int reg_num)
2740 {
2741         struct pcnet32_private *lp = netdev_priv(dev);
2742         unsigned long ioaddr = dev->base_addr;
2743         u16 val_out;
2744
2745         if (!lp->mii)
2746                 return 0;
2747
2748         lp->a->write_bcr(ioaddr, 33, ((phy_id & 0x1f) << 5) | (reg_num & 0x1f));
2749         val_out = lp->a->read_bcr(ioaddr, 34);
2750
2751         return val_out;
2752 }
2753
2754 /* This routine assumes that the lp->lock is held */
2755 static void mdio_write(struct net_device *dev, int phy_id, int reg_num, int val)
2756 {
2757         struct pcnet32_private *lp = netdev_priv(dev);
2758         unsigned long ioaddr = dev->base_addr;
2759
2760         if (!lp->mii)
2761                 return;
2762
2763         lp->a->write_bcr(ioaddr, 33, ((phy_id & 0x1f) << 5) | (reg_num & 0x1f));
2764         lp->a->write_bcr(ioaddr, 34, val);
2765 }
2766
2767 static int pcnet32_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
2768 {
2769         struct pcnet32_private *lp = netdev_priv(dev);
2770         int rc;
2771         unsigned long flags;
2772
2773         /* SIOC[GS]MIIxxx ioctls */
2774         if (lp->mii) {
2775                 spin_lock_irqsave(&lp->lock, flags);
2776                 rc = generic_mii_ioctl(&lp->mii_if, if_mii(rq), cmd, NULL);
2777                 spin_unlock_irqrestore(&lp->lock, flags);
2778         } else {
2779                 rc = -EOPNOTSUPP;
2780         }
2781
2782         return rc;
2783 }
2784
2785 static int pcnet32_check_otherphy(struct net_device *dev)
2786 {
2787         struct pcnet32_private *lp = netdev_priv(dev);
2788         struct mii_if_info mii = lp->mii_if;
2789         u16 bmcr;
2790         int i;
2791
2792         for (i = 0; i < PCNET32_MAX_PHYS; i++) {
2793                 if (i == lp->mii_if.phy_id)
2794                         continue;       /* skip active phy */
2795                 if (lp->phymask & (1 << i)) {
2796                         mii.phy_id = i;
2797                         if (mii_link_ok(&mii)) {
2798                                 /* found PHY with active link */
2799                                 netif_info(lp, link, dev, "Using PHY number %d\n",
2800                                            i);
2801
2802                                 /* isolate inactive phy */
2803                                 bmcr =
2804                                     mdio_read(dev, lp->mii_if.phy_id, MII_BMCR);
2805                                 mdio_write(dev, lp->mii_if.phy_id, MII_BMCR,
2806                                            bmcr | BMCR_ISOLATE);
2807
2808                                 /* de-isolate new phy */
2809                                 bmcr = mdio_read(dev, i, MII_BMCR);
2810                                 mdio_write(dev, i, MII_BMCR,
2811                                            bmcr & ~BMCR_ISOLATE);
2812
2813                                 /* set new phy address */
2814                                 lp->mii_if.phy_id = i;
2815                                 return 1;
2816                         }
2817                 }
2818         }
2819         return 0;
2820 }
2821
2822 /*
2823  * Show the status of the media.  Similar to mii_check_media however it
2824  * correctly shows the link speed for all (tested) pcnet32 variants.
2825  * Devices with no mii just report link state without speed.
2826  *
2827  * Caller is assumed to hold and release the lp->lock.
2828  */
2829
2830 static void pcnet32_check_media(struct net_device *dev, int verbose)
2831 {
2832         struct pcnet32_private *lp = netdev_priv(dev);
2833         int curr_link;
2834         int prev_link = netif_carrier_ok(dev) ? 1 : 0;
2835         u32 bcr9;
2836
2837         if (lp->mii) {
2838                 curr_link = mii_link_ok(&lp->mii_if);
2839         } else if (lp->chip_version == PCNET32_79C970A) {
2840                 ulong ioaddr = dev->base_addr;  /* card base I/O address */
2841                 /* only read link if port is set to TP */
2842                 if (!lp->autoneg && lp->port_tp)
2843                         curr_link = (lp->a->read_bcr(ioaddr, 4) != 0xc0);
2844                 else /* link always up for AUI port or port auto select */
2845                         curr_link = 1;
2846         } else {
2847                 ulong ioaddr = dev->base_addr;  /* card base I/O address */
2848                 curr_link = (lp->a->read_bcr(ioaddr, 4) != 0xc0);
2849         }
2850         if (!curr_link) {
2851                 if (prev_link || verbose) {
2852                         netif_carrier_off(dev);
2853                         netif_info(lp, link, dev, "link down\n");
2854                 }
2855                 if (lp->phycount > 1) {
2856                         pcnet32_check_otherphy(dev);
2857                 }
2858         } else if (verbose || !prev_link) {
2859                 netif_carrier_on(dev);
2860                 if (lp->mii) {
2861                         if (netif_msg_link(lp)) {
2862                                 struct ethtool_cmd ecmd = {
2863                                         .cmd = ETHTOOL_GSET };
2864                                 mii_ethtool_gset(&lp->mii_if, &ecmd);
2865                                 netdev_info(dev, "link up, %uMbps, %s-duplex\n",
2866                                             ethtool_cmd_speed(&ecmd),
2867                                             (ecmd.duplex == DUPLEX_FULL)
2868                                             ? "full" : "half");
2869                         }
2870                         bcr9 = lp->a->read_bcr(dev->base_addr, 9);
2871                         if ((bcr9 & (1 << 0)) != lp->mii_if.full_duplex) {
2872                                 if (lp->mii_if.full_duplex)
2873                                         bcr9 |= (1 << 0);
2874                                 else
2875                                         bcr9 &= ~(1 << 0);
2876                                 lp->a->write_bcr(dev->base_addr, 9, bcr9);
2877                         }
2878                 } else {
2879                         netif_info(lp, link, dev, "link up\n");
2880                 }
2881         }
2882 }
2883
2884 /*
2885  * Check for loss of link and link establishment.
2886  * Could possibly be changed to use mii_check_media instead.
2887  */
2888
2889 static void pcnet32_watchdog(struct timer_list *t)
2890 {
2891         struct pcnet32_private *lp = from_timer(lp, t, watchdog_timer);
2892         struct net_device *dev = lp->dev;
2893         unsigned long flags;
2894
2895         /* Print the link status if it has changed */
2896         spin_lock_irqsave(&lp->lock, flags);
2897         pcnet32_check_media(dev, 0);
2898         spin_unlock_irqrestore(&lp->lock, flags);
2899
2900         mod_timer(&lp->watchdog_timer, round_jiffies(PCNET32_WATCHDOG_TIMEOUT));
2901 }
2902
2903 static int __maybe_unused pcnet32_pm_suspend(struct device *device_d)
2904 {
2905         struct net_device *dev = dev_get_drvdata(device_d);
2906
2907         if (netif_running(dev)) {
2908                 netif_device_detach(dev);
2909                 pcnet32_close(dev);
2910         }
2911
2912         return 0;
2913 }
2914
2915 static int __maybe_unused pcnet32_pm_resume(struct device *device_d)
2916 {
2917         struct net_device *dev = dev_get_drvdata(device_d);
2918
2919         if (netif_running(dev)) {
2920                 pcnet32_open(dev);
2921                 netif_device_attach(dev);
2922         }
2923
2924         return 0;
2925 }
2926
2927 static void pcnet32_remove_one(struct pci_dev *pdev)
2928 {
2929         struct net_device *dev = pci_get_drvdata(pdev);
2930
2931         if (dev) {
2932                 struct pcnet32_private *lp = netdev_priv(dev);
2933
2934                 unregister_netdev(dev);
2935                 pcnet32_free_ring(dev);
2936                 release_region(dev->base_addr, PCNET32_TOTAL_SIZE);
2937                 dma_free_coherent(&lp->pci_dev->dev, sizeof(*lp->init_block),
2938                                   lp->init_block, lp->init_dma_addr);
2939                 free_netdev(dev);
2940                 pci_disable_device(pdev);
2941         }
2942 }
2943
2944 static SIMPLE_DEV_PM_OPS(pcnet32_pm_ops, pcnet32_pm_suspend, pcnet32_pm_resume);
2945
2946 static struct pci_driver pcnet32_driver = {
2947         .name = DRV_NAME,
2948         .probe = pcnet32_probe_pci,
2949         .remove = pcnet32_remove_one,
2950         .id_table = pcnet32_pci_tbl,
2951         .driver = {
2952                 .pm = &pcnet32_pm_ops,
2953         },
2954 };
2955
2956 /* An additional parameter that may be passed in... */
2957 static int debug = -1;
2958 static int tx_start_pt = -1;
2959 static int pcnet32_have_pci;
2960
2961 module_param(debug, int, 0);
2962 MODULE_PARM_DESC(debug, DRV_NAME " debug level");
2963 module_param(max_interrupt_work, int, 0);
2964 MODULE_PARM_DESC(max_interrupt_work,
2965                  DRV_NAME " maximum events handled per interrupt");
2966 module_param(rx_copybreak, int, 0);
2967 MODULE_PARM_DESC(rx_copybreak,
2968                  DRV_NAME " copy breakpoint for copy-only-tiny-frames");
2969 module_param(tx_start_pt, int, 0);
2970 MODULE_PARM_DESC(tx_start_pt, DRV_NAME " transmit start point (0-3)");
2971 module_param(pcnet32vlb, int, 0);
2972 MODULE_PARM_DESC(pcnet32vlb, DRV_NAME " Vesa local bus (VLB) support (0/1)");
2973 module_param_array(options, int, NULL, 0);
2974 MODULE_PARM_DESC(options, DRV_NAME " initial option setting(s) (0-15)");
2975 module_param_array(full_duplex, int, NULL, 0);
2976 MODULE_PARM_DESC(full_duplex, DRV_NAME " full duplex setting(s) (1)");
2977 /* Module Parameter for HomePNA cards added by Patrick Simmons, 2004 */
2978 module_param_array(homepna, int, NULL, 0);
2979 MODULE_PARM_DESC(homepna,
2980                  DRV_NAME
2981                  " mode for 79C978 cards (1 for HomePNA, 0 for Ethernet, default Ethernet");
2982
2983 MODULE_AUTHOR("Thomas Bogendoerfer");
2984 MODULE_DESCRIPTION("Driver for PCnet32 and PCnetPCI based ethercards");
2985 MODULE_LICENSE("GPL");
2986
2987 #define PCNET32_MSG_DEFAULT (NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_LINK)
2988
2989 static int __init pcnet32_init_module(void)
2990 {
2991         pcnet32_debug = netif_msg_init(debug, PCNET32_MSG_DEFAULT);
2992
2993         if ((tx_start_pt >= 0) && (tx_start_pt <= 3))
2994                 tx_start = tx_start_pt;
2995
2996         /* find the PCI devices */
2997         if (!pci_register_driver(&pcnet32_driver))
2998                 pcnet32_have_pci = 1;
2999
3000         /* should we find any remaining VLbus devices ? */
3001         if (pcnet32vlb)
3002                 pcnet32_probe_vlbus(pcnet32_portlist);
3003
3004         if (cards_found && (pcnet32_debug & NETIF_MSG_PROBE))
3005                 pr_info("%d cards_found\n", cards_found);
3006
3007         return (pcnet32_have_pci + cards_found) ? 0 : -ENODEV;
3008 }
3009
3010 static void __exit pcnet32_cleanup_module(void)
3011 {
3012         struct net_device *next_dev;
3013
3014         while (pcnet32_dev) {
3015                 struct pcnet32_private *lp = netdev_priv(pcnet32_dev);
3016                 next_dev = lp->next;
3017                 unregister_netdev(pcnet32_dev);
3018                 pcnet32_free_ring(pcnet32_dev);
3019                 release_region(pcnet32_dev->base_addr, PCNET32_TOTAL_SIZE);
3020                 dma_free_coherent(&lp->pci_dev->dev, sizeof(*lp->init_block),
3021                                   lp->init_block, lp->init_dma_addr);
3022                 free_netdev(pcnet32_dev);
3023                 pcnet32_dev = next_dev;
3024         }
3025
3026         if (pcnet32_have_pci)
3027                 pci_unregister_driver(&pcnet32_driver);
3028 }
3029
3030 module_init(pcnet32_init_module);
3031 module_exit(pcnet32_cleanup_module);