1 /* SPDX-License-Identifier: GPL-2.0-only */
4 * Alchemy Au1x00 ethernet driver include file
6 * Author: Pete Popov <ppopov@mvista.com>
8 * Copyright 2001 MontaVista Software Inc.
12 #define MAC_IOSIZE 0x10000
13 #define NUM_RX_DMA 4 /* Au1x00 has 4 rx hardware descriptors */
14 #define NUM_TX_DMA 4 /* Au1x00 has 4 tx hardware descriptors */
16 #define NUM_RX_BUFFS 4
17 #define NUM_TX_BUFFS 4
18 #define MAX_BUF_SIZE 2048
20 #define ETH_TX_TIMEOUT (HZ/4)
21 #define MAC_MIN_PKT_SIZE 64
23 #define MULTICAST_FILTER_LIMIT 64
26 * Data Buffer Descriptor. Data buffers must be aligned on 32 byte
27 * boundary for both, receive and transmit.
30 struct db_dest *pnext;
36 * The transmit and receive descriptors are memory
54 * MAC control registers, memory mapped.
70 struct au1000_private {
71 struct db_dest *pDBfree;
72 struct db_dest db[NUM_RX_BUFFS+NUM_TX_BUFFS];
73 struct rx_dma *rx_dma_ring[NUM_RX_DMA];
74 struct tx_dma *tx_dma_ring[NUM_TX_DMA];
75 struct db_dest *rx_db_inuse[NUM_RX_DMA];
76 struct db_dest *tx_db_inuse[NUM_TX_DMA];
84 int mac_enabled; /* whether MAC is currently enabled and running
88 int old_link; /* used by au1000_adjust_link */
92 struct mii_bus *mii_bus;
94 /* PHY configuration */
95 int phy_static_config;
96 int phy_search_highest_addr;
103 /* These variables are just for quick access
104 * to certain regs addresses.
106 struct mac_reg *mac; /* mac registers */
107 u32 *enable; /* address of MAC Enable Register */
108 void __iomem *macdma; /* base of MAC DMA port */
109 u32 vaddr; /* virtual address of rx/tx buffers */
110 dma_addr_t dma_addr; /* dma address of rx/tx buffers */
112 spinlock_t lock; /* Serialise access to device */