drivers/net/e1000e/ich8lan.c

   1 /*******************************************************************************
   2
   3   Intel PRO/1000 Linux driver
   4   Copyright(c) 1999 - 2010 Intel Corporation.
   5
   6   This program is free software; you can redistribute it and/or modify it
   7   under the terms and conditions of the GNU General Public License,
   8   version 2, as published by the Free Software Foundation.
   9
  10   This program is distributed in the hope it will be useful, but WITHOUT
  11   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  12   FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  13   more details.
  14
  15   You should have received a copy of the GNU General Public License along with
  16   this program; if not, write to the Free Software Foundation, Inc.,
  17   51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
  18
  19   The full GNU General Public License is included in this distribution in
  20   the file called "COPYING".
  21
  22   Contact Information:
  23   Linux NICS <linux.nics@intel.com>
  24   e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
  25   Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
  26
  27 *******************************************************************************/
  28
  29 /*
  30  * 82562G 10/100 Network Connection
  31  * 82562G-2 10/100 Network Connection
  32  * 82562GT 10/100 Network Connection
  33  * 82562GT-2 10/100 Network Connection
  34  * 82562V 10/100 Network Connection
  35  * 82562V-2 10/100 Network Connection
  36  * 82566DC-2 Gigabit Network Connection
  37  * 82566DC Gigabit Network Connection
  38  * 82566DM-2 Gigabit Network Connection
  39  * 82566DM Gigabit Network Connection
  40  * 82566MC Gigabit Network Connection
  41  * 82566MM Gigabit Network Connection
  42  * 82567LM Gigabit Network Connection
  43  * 82567LF Gigabit Network Connection
  44  * 82567V Gigabit Network Connection
  45  * 82567LM-2 Gigabit Network Connection
  46  * 82567LF-2 Gigabit Network Connection
  47  * 82567V-2 Gigabit Network Connection
  48  * 82567LF-3 Gigabit Network Connection
  49  * 82567LM-3 Gigabit Network Connection
  50  * 82567LM-4 Gigabit Network Connection
  51  * 82577LM Gigabit Network Connection
  52  * 82577LC Gigabit Network Connection
  53  * 82578DM Gigabit Network Connection
  54  * 82578DC Gigabit Network Connection
  55  * 82579LM Gigabit Network Connection
  56  * 82579V Gigabit Network Connection
  57  */
  58
  59 #include "e1000.h"
  60
  61 #define ICH_FLASH_GFPREG                0x0000
  62 #define ICH_FLASH_HSFSTS                0x0004
  63 #define ICH_FLASH_HSFCTL                0x0006
  64 #define ICH_FLASH_FADDR                 0x0008
  65 #define ICH_FLASH_FDATA0                0x0010
  66 #define ICH_FLASH_PR0                   0x0074
  67
  68 #define ICH_FLASH_READ_COMMAND_TIMEOUT  500
  69 #define ICH_FLASH_WRITE_COMMAND_TIMEOUT 500
  70 #define ICH_FLASH_ERASE_COMMAND_TIMEOUT 3000000
  71 #define ICH_FLASH_LINEAR_ADDR_MASK      0x00FFFFFF
  72 #define ICH_FLASH_CYCLE_REPEAT_COUNT    10
  73
  74 #define ICH_CYCLE_READ                  0
  75 #define ICH_CYCLE_WRITE                 2
  76 #define ICH_CYCLE_ERASE                 3
  77
  78 #define FLASH_GFPREG_BASE_MASK          0x1FFF
  79 #define FLASH_SECTOR_ADDR_SHIFT         12
  80
  81 #define ICH_FLASH_SEG_SIZE_256          256
  82 #define ICH_FLASH_SEG_SIZE_4K           4096
  83 #define ICH_FLASH_SEG_SIZE_8K           8192
  84 #define ICH_FLASH_SEG_SIZE_64K          65536
  85
  86
  87 #define E1000_ICH_FWSM_RSPCIPHY 0x00000040 /* Reset PHY on PCI Reset */
  88 /* FW established a valid mode */
  89 #define E1000_ICH_FWSM_FW_VALID         0x00008000
  90
  91 #define E1000_ICH_MNG_IAMT_MODE         0x2
  92
  93 #define ID_LED_DEFAULT_ICH8LAN  ((ID_LED_DEF1_DEF2 << 12) | \
  94                                  (ID_LED_DEF1_OFF2 <<  8) | \
  95                                  (ID_LED_DEF1_ON2  <<  4) | \
  96                                  (ID_LED_DEF1_DEF2))
  97
  98 #define E1000_ICH_NVM_SIG_WORD          0x13
  99 #define E1000_ICH_NVM_SIG_MASK          0xC000
 100 #define E1000_ICH_NVM_VALID_SIG_MASK    0xC0
 101 #define E1000_ICH_NVM_SIG_VALUE         0x80
 102
 103 #define E1000_ICH8_LAN_INIT_TIMEOUT     1500
 104
 105 #define E1000_FEXTNVM_SW_CONFIG         1
 106 #define E1000_FEXTNVM_SW_CONFIG_ICH8M (1 << 27) /* Bit redefined for ICH8M :/ */
 107
 108 #define PCIE_ICH8_SNOOP_ALL             PCIE_NO_SNOOP_ALL
 109
 110 #define E1000_ICH_RAR_ENTRIES           7
 111
 112 #define PHY_PAGE_SHIFT 5
 113 #define PHY_REG(page, reg) (((page) << PHY_PAGE_SHIFT) | \
 114                            ((reg) & MAX_PHY_REG_ADDRESS))
 115 #define IGP3_KMRN_DIAG  PHY_REG(770, 19) /* KMRN Diagnostic */
 116 #define IGP3_VR_CTRL    PHY_REG(776, 18) /* Voltage Regulator Control */
 117
 118 #define IGP3_KMRN_DIAG_PCS_LOCK_LOSS    0x0002
 119 #define IGP3_VR_CTRL_DEV_POWERDOWN_MODE_MASK 0x0300
 120 #define IGP3_VR_CTRL_MODE_SHUTDOWN      0x0200
 121
 122 #define HV_LED_CONFIG           PHY_REG(768, 30) /* LED Configuration */
 123
 124 #define SW_FLAG_TIMEOUT    1000 /* SW Semaphore flag timeout in milliseconds */
 125
 126 /* SMBus Address Phy Register */
 127 #define HV_SMB_ADDR            PHY_REG(768, 26)
 128 #define HV_SMB_ADDR_PEC_EN     0x0200
 129 #define HV_SMB_ADDR_VALID      0x0080
 130
 131 /* PHY Power Management Control */
 132 #define HV_PM_CTRL              PHY_REG(770, 17)
 133
 134 /* PHY Low Power Idle Control */
 135 #define I82579_LPI_CTRL                 PHY_REG(772, 20)
 136 #define I82579_LPI_CTRL_ENABLE_MASK     0x6000
 137
 138 /* Strapping Option Register - RO */
 139 #define E1000_STRAP                     0x0000C
 140 #define E1000_STRAP_SMBUS_ADDRESS_MASK  0x00FE0000
 141 #define E1000_STRAP_SMBUS_ADDRESS_SHIFT 17
 142
 143 /* OEM Bits Phy Register */
 144 #define HV_OEM_BITS            PHY_REG(768, 25)
 145 #define HV_OEM_BITS_LPLU       0x0004 /* Low Power Link Up */
 146 #define HV_OEM_BITS_GBE_DIS    0x0040 /* Gigabit Disable */
 147 #define HV_OEM_BITS_RESTART_AN 0x0400 /* Restart Auto-negotiation */
 148
 149 #define E1000_NVM_K1_CONFIG 0x1B /* NVM K1 Config Word */
 150 #define E1000_NVM_K1_ENABLE 0x1  /* NVM Enable K1 bit */
 151
 152 /* KMRN Mode Control */
 153 #define HV_KMRN_MODE_CTRL      PHY_REG(769, 16)
 154 #define HV_KMRN_MDIO_SLOW      0x0400
 155
 156 /* ICH GbE Flash Hardware Sequencing Flash Status Register bit breakdown */
 157 /* Offset 04h HSFSTS */
 158 union ich8_hws_flash_status {
 159         struct ich8_hsfsts {
 160                 u16 flcdone    :1; /* bit 0 Flash Cycle Done */
 161                 u16 flcerr     :1; /* bit 1 Flash Cycle Error */
 162                 u16 dael       :1; /* bit 2 Direct Access error Log */
 163                 u16 berasesz   :2; /* bit 4:3 Sector Erase Size */
 164                 u16 flcinprog  :1; /* bit 5 flash cycle in Progress */
 165                 u16 reserved1  :2; /* bit 13:6 Reserved */
 166                 u16 reserved2  :6; /* bit 13:6 Reserved */
 167                 u16 fldesvalid :1; /* bit 14 Flash Descriptor Valid */
 168                 u16 flockdn    :1; /* bit 15 Flash Config Lock-Down */
 169         } hsf_status;
 170         u16 regval;
 171 };
 172
 173 /* ICH GbE Flash Hardware Sequencing Flash control Register bit breakdown */
 174 /* Offset 06h FLCTL */
 175 union ich8_hws_flash_ctrl {
 176         struct ich8_hsflctl {
 177                 u16 flcgo      :1;   /* 0 Flash Cycle Go */
 178                 u16 flcycle    :2;   /* 2:1 Flash Cycle */
 179                 u16 reserved   :5;   /* 7:3 Reserved  */
 180                 u16 fldbcount  :2;   /* 9:8 Flash Data Byte Count */
 181                 u16 flockdn    :6;   /* 15:10 Reserved */
 182         } hsf_ctrl;
 183         u16 regval;
 184 };
 185
 186 /* ICH Flash Region Access Permissions */
 187 union ich8_hws_flash_regacc {
 188         struct ich8_flracc {
 189                 u32 grra      :8; /* 0:7 GbE region Read Access */
 190                 u32 grwa      :8; /* 8:15 GbE region Write Access */
 191                 u32 gmrag     :8; /* 23:16 GbE Master Read Access Grant */
 192                 u32 gmwag     :8; /* 31:24 GbE Master Write Access Grant */
 193         } hsf_flregacc;
 194         u16 regval;
 195 };
 196
 197 /* ICH Flash Protected Region */
 198 union ich8_flash_protected_range {
 199         struct ich8_pr {
 200                 u32 base:13;     /* 0:12 Protected Range Base */
 201                 u32 reserved1:2; /* 13:14 Reserved */
 202                 u32 rpe:1;       /* 15 Read Protection Enable */
 203                 u32 limit:13;    /* 16:28 Protected Range Limit */
 204                 u32 reserved2:2; /* 29:30 Reserved */
 205                 u32 wpe:1;       /* 31 Write Protection Enable */
 206         } range;
 207         u32 regval;
 208 };
 209
 210 static s32 e1000_setup_link_ich8lan(struct e1000_hw *hw);
 211 static void e1000_clear_hw_cntrs_ich8lan(struct e1000_hw *hw);
 212 static void e1000_initialize_hw_bits_ich8lan(struct e1000_hw *hw);
 213 static s32 e1000_erase_flash_bank_ich8lan(struct e1000_hw *hw, u32 bank);
 214 static s32 e1000_retry_write_flash_byte_ich8lan(struct e1000_hw *hw,
 215                                                 u32 offset, u8 byte);
 216 static s32 e1000_read_flash_byte_ich8lan(struct e1000_hw *hw, u32 offset,
 217                                          u8 *data);
 218 static s32 e1000_read_flash_word_ich8lan(struct e1000_hw *hw, u32 offset,
 219                                          u16 *data);
 220 static s32 e1000_read_flash_data_ich8lan(struct e1000_hw *hw, u32 offset,
 221                                          u8 size, u16 *data);
 222 static s32 e1000_setup_copper_link_ich8lan(struct e1000_hw *hw);
 223 static s32 e1000_kmrn_lock_loss_workaround_ich8lan(struct e1000_hw *hw);
 224 static s32 e1000_get_cfg_done_ich8lan(struct e1000_hw *hw);
 225 static s32 e1000_cleanup_led_ich8lan(struct e1000_hw *hw);
 226 static s32 e1000_led_on_ich8lan(struct e1000_hw *hw);
 227 static s32 e1000_led_off_ich8lan(struct e1000_hw *hw);
 228 static s32 e1000_id_led_init_pchlan(struct e1000_hw *hw);
 229 static s32 e1000_setup_led_pchlan(struct e1000_hw *hw);
 230 static s32 e1000_cleanup_led_pchlan(struct e1000_hw *hw);
 231 static s32 e1000_led_on_pchlan(struct e1000_hw *hw);
 232 static s32 e1000_led_off_pchlan(struct e1000_hw *hw);
 233 static s32 e1000_set_lplu_state_pchlan(struct e1000_hw *hw, bool active);
 234 static void e1000_power_down_phy_copper_ich8lan(struct e1000_hw *hw);
 235 static void e1000_lan_init_done_ich8lan(struct e1000_hw *hw);
 236 static s32  e1000_k1_gig_workaround_hv(struct e1000_hw *hw, bool link);
 237 static s32 e1000_set_mdio_slow_mode_hv(struct e1000_hw *hw);
 238 static bool e1000_check_mng_mode_ich8lan(struct e1000_hw *hw);
 239 static bool e1000_check_mng_mode_pchlan(struct e1000_hw *hw);
 240
 241 static inline u16 __er16flash(struct e1000_hw *hw, unsigned long reg)
 242 {
 243         return readw(hw->flash_address + reg);
 244 }
 245
 246 static inline u32 __er32flash(struct e1000_hw *hw, unsigned long reg)
 247 {
 248         return readl(hw->flash_address + reg);
 249 }
 250
 251 static inline void __ew16flash(struct e1000_hw *hw, unsigned long reg, u16 val)
 252 {
 253         writew(val, hw->flash_address + reg);
 254 }
 255
 256 static inline void __ew32flash(struct e1000_hw *hw, unsigned long reg, u32 val)
 257 {
 258         writel(val, hw->flash_address + reg);
 259 }
 260
 261 #define er16flash(reg)          __er16flash(hw, (reg))
 262 #define er32flash(reg)          __er32flash(hw, (reg))
 263 #define ew16flash(reg,val)      __ew16flash(hw, (reg), (val))
 264 #define ew32flash(reg,val)      __ew32flash(hw, (reg), (val))
 265
 266 /**
 267  *  e1000_init_phy_params_pchlan - Initialize PHY function pointers
 268  *  @hw: pointer to the HW structure
 269  *
 270  *  Initialize family-specific PHY parameters and function pointers.
 271  **/
 272 static s32 e1000_init_phy_params_pchlan(struct e1000_hw *hw)
 273 {
 274         struct e1000_phy_info *phy = &hw->phy;
 275         u32 ctrl;
 276         s32 ret_val = 0;
 277
 278         phy->addr                     = 1;
 279         phy->reset_delay_us           = 100;
 280
 281         phy->ops.read_reg             = e1000_read_phy_reg_hv;
 282         phy->ops.read_reg_locked      = e1000_read_phy_reg_hv_locked;
 283         phy->ops.set_d0_lplu_state    = e1000_set_lplu_state_pchlan;
 284         phy->ops.set_d3_lplu_state    = e1000_set_lplu_state_pchlan;
 285         phy->ops.write_reg            = e1000_write_phy_reg_hv;
 286         phy->ops.write_reg_locked     = e1000_write_phy_reg_hv_locked;
 287         phy->ops.power_up             = e1000_power_up_phy_copper;
 288         phy->ops.power_down           = e1000_power_down_phy_copper_ich8lan;
 289         phy->autoneg_mask             = AUTONEG_ADVERTISE_SPEED_DEFAULT;
 290
 291         /*
 292          * The MAC-PHY interconnect may still be in SMBus mode
 293          * after Sx->S0.  If the manageability engine (ME) is
 294          * disabled, then toggle the LANPHYPC Value bit to force
 295          * the interconnect to PCIe mode.
 296          */
 297         if (!(er32(FWSM) & E1000_ICH_FWSM_FW_VALID)) {
 298                 ctrl = er32(CTRL);
 299                 ctrl |=  E1000_CTRL_LANPHYPC_OVERRIDE;
 300                 ctrl &= ~E1000_CTRL_LANPHYPC_VALUE;
 301                 ew32(CTRL, ctrl);
 302                 udelay(10);
 303                 ctrl &= ~E1000_CTRL_LANPHYPC_OVERRIDE;
 304                 ew32(CTRL, ctrl);
 305                 msleep(50);
 306         }
 307
 308         /*
 309          * Reset the PHY before any acccess to it.  Doing so, ensures that
 310          * the PHY is in a known good state before we read/write PHY registers.
 311          * The generic reset is sufficient here, because we haven't determined
 312          * the PHY type yet.
 313          */
 314         ret_val = e1000e_phy_hw_reset_generic(hw);
 315         if (ret_val)
 316                 goto out;
 317
 318         phy->id = e1000_phy_unknown;
 319         ret_val = e1000e_get_phy_id(hw);
 320         if (ret_val)
 321                 goto out;
 322         if ((phy->id == 0) || (phy->id == PHY_REVISION_MASK)) {
 323                 /*
 324                  * In case the PHY needs to be in mdio slow mode (eg. 82577),
 325                  * set slow mode and try to get the PHY id again.
 326                  */
 327                 ret_val = e1000_set_mdio_slow_mode_hv(hw);
 328                 if (ret_val)
 329                         goto out;
 330                 ret_val = e1000e_get_phy_id(hw);
 331                 if (ret_val)
 332                         goto out;
 333         }
 334         phy->type = e1000e_get_phy_type_from_id(phy->id);
 335
 336         switch (phy->type) {
 337         case e1000_phy_82577:
 338         case e1000_phy_82579:
 339                 phy->ops.check_polarity = e1000_check_polarity_82577;
 340                 phy->ops.force_speed_duplex =
 341                         e1000_phy_force_speed_duplex_82577;
 342                 phy->ops.get_cable_length = e1000_get_cable_length_82577;
 343                 phy->ops.get_info = e1000_get_phy_info_82577;
 344                 phy->ops.commit = e1000e_phy_sw_reset;
 345                 break;
 346         case e1000_phy_82578:
 347                 phy->ops.check_polarity = e1000_check_polarity_m88;
 348                 phy->ops.force_speed_duplex = e1000e_phy_force_speed_duplex_m88;
 349                 phy->ops.get_cable_length = e1000e_get_cable_length_m88;
 350                 phy->ops.get_info = e1000e_get_phy_info_m88;
 351                 break;
 352         default:
 353                 ret_val = -E1000_ERR_PHY;
 354                 break;
 355         }
 356
 357 out:
 358         return ret_val;
 359 }
 360
 361 /**
 362  *  e1000_init_phy_params_ich8lan - Initialize PHY function pointers
 363  *  @hw: pointer to the HW structure
 364  *
 365  *  Initialize family-specific PHY parameters and function pointers.
 366  **/
 367 static s32 e1000_init_phy_params_ich8lan(struct e1000_hw *hw)
 368 {
 369         struct e1000_phy_info *phy = &hw->phy;
 370         s32 ret_val;
 371         u16 i = 0;
 372
 373         phy->addr                       = 1;
 374         phy->reset_delay_us             = 100;
 375
 376         phy->ops.power_up               = e1000_power_up_phy_copper;
 377         phy->ops.power_down             = e1000_power_down_phy_copper_ich8lan;
 378
 379         /*
 380          * We may need to do this twice - once for IGP and if that fails,
 381          * we'll set BM func pointers and try again
 382          */
 383         ret_val = e1000e_determine_phy_address(hw);
 384         if (ret_val) {
 385                 phy->ops.write_reg = e1000e_write_phy_reg_bm;
 386                 phy->ops.read_reg  = e1000e_read_phy_reg_bm;
 387                 ret_val = e1000e_determine_phy_address(hw);
 388                 if (ret_val) {
 389                         e_dbg("Cannot determine PHY addr. Erroring out\n");
 390                         return ret_val;
 391                 }
 392         }
 393
 394         phy->id = 0;
 395         while ((e1000_phy_unknown == e1000e_get_phy_type_from_id(phy->id)) &&
 396                (i++ < 100)) {
 397                 msleep(1);
 398                 ret_val = e1000e_get_phy_id(hw);
 399                 if (ret_val)
 400                         return ret_val;
 401         }
 402
 403         /* Verify phy id */
 404         switch (phy->id) {
 405         case IGP03E1000_E_PHY_ID:
 406                 phy->type = e1000_phy_igp_3;
 407                 phy->autoneg_mask = AUTONEG_ADVERTISE_SPEED_DEFAULT;
 408                 phy->ops.read_reg_locked = e1000e_read_phy_reg_igp_locked;
 409                 phy->ops.write_reg_locked = e1000e_write_phy_reg_igp_locked;
 410                 phy->ops.get_info = e1000e_get_phy_info_igp;
 411                 phy->ops.check_polarity = e1000_check_polarity_igp;
 412                 phy->ops.force_speed_duplex = e1000e_phy_force_speed_duplex_igp;
 413                 break;
 414         case IFE_E_PHY_ID:
 415         case IFE_PLUS_E_PHY_ID:
 416         case IFE_C_E_PHY_ID:
 417                 phy->type = e1000_phy_ife;
 418                 phy->autoneg_mask = E1000_ALL_NOT_GIG;
 419                 phy->ops.get_info = e1000_get_phy_info_ife;
 420                 phy->ops.check_polarity = e1000_check_polarity_ife;
 421                 phy->ops.force_speed_duplex = e1000_phy_force_speed_duplex_ife;
 422                 break;
 423         case BME1000_E_PHY_ID:
 424                 phy->type = e1000_phy_bm;
 425                 phy->autoneg_mask = AUTONEG_ADVERTISE_SPEED_DEFAULT;
 426                 phy->ops.read_reg = e1000e_read_phy_reg_bm;
 427                 phy->ops.write_reg = e1000e_write_phy_reg_bm;
 428                 phy->ops.commit = e1000e_phy_sw_reset;
 429                 phy->ops.get_info = e1000e_get_phy_info_m88;
 430                 phy->ops.check_polarity = e1000_check_polarity_m88;
 431                 phy->ops.force_speed_duplex = e1000e_phy_force_speed_duplex_m88;
 432                 break;
 433         default:
 434                 return -E1000_ERR_PHY;
 435                 break;
 436         }
 437
 438         return 0;
 439 }
 440
 441 /**
 442  *  e1000_init_nvm_params_ich8lan - Initialize NVM function pointers
 443  *  @hw: pointer to the HW structure
 444  *
 445  *  Initialize family-specific NVM parameters and function
 446  *  pointers.
 447  **/
 448 static s32 e1000_init_nvm_params_ich8lan(struct e1000_hw *hw)
 449 {
 450         struct e1000_nvm_info *nvm = &hw->nvm;
 451         struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
 452         u32 gfpreg, sector_base_addr, sector_end_addr;
 453         u16 i;
 454
 455         /* Can't read flash registers if the register set isn't mapped. */
 456         if (!hw->flash_address) {
 457                 e_dbg("ERROR: Flash registers not mapped\n");
 458                 return -E1000_ERR_CONFIG;
 459         }
 460
 461         nvm->type = e1000_nvm_flash_sw;
 462
 463         gfpreg = er32flash(ICH_FLASH_GFPREG);
 464
 465         /*
 466          * sector_X_addr is a "sector"-aligned address (4096 bytes)
 467          * Add 1 to sector_end_addr since this sector is included in
 468          * the overall size.
 469          */
 470         sector_base_addr = gfpreg & FLASH_GFPREG_BASE_MASK;
 471         sector_end_addr = ((gfpreg >> 16) & FLASH_GFPREG_BASE_MASK) + 1;
 472
 473         /* flash_base_addr is byte-aligned */
 474         nvm->flash_base_addr = sector_base_addr << FLASH_SECTOR_ADDR_SHIFT;
 475
 476         /*
 477          * find total size of the NVM, then cut in half since the total
 478          * size represents two separate NVM banks.
 479          */
 480         nvm->flash_bank_size = (sector_end_addr - sector_base_addr)
 481                                 << FLASH_SECTOR_ADDR_SHIFT;
 482         nvm->flash_bank_size /= 2;
 483         /* Adjust to word count */
 484         nvm->flash_bank_size /= sizeof(u16);
 485
 486         nvm->word_size = E1000_ICH8_SHADOW_RAM_WORDS;
 487
 488         /* Clear shadow ram */
 489         for (i = 0; i < nvm->word_size; i++) {
 490                 dev_spec->shadow_ram[i].modified = false;
 491                 dev_spec->shadow_ram[i].value    = 0xFFFF;
 492         }
 493
 494         return 0;
 495 }
 496
 497 /**
 498  *  e1000_init_mac_params_ich8lan - Initialize MAC function pointers
 499  *  @hw: pointer to the HW structure
 500  *
 501  *  Initialize family-specific MAC parameters and function
 502  *  pointers.
 503  **/
 504 static s32 e1000_init_mac_params_ich8lan(struct e1000_adapter *adapter)
 505 {
 506         struct e1000_hw *hw = &adapter->hw;
 507         struct e1000_mac_info *mac = &hw->mac;
 508
 509         /* Set media type function pointer */
 510         hw->phy.media_type = e1000_media_type_copper;
 511
 512         /* Set mta register count */
 513         mac->mta_reg_count = 32;
 514         /* Set rar entry count */
 515         mac->rar_entry_count = E1000_ICH_RAR_ENTRIES;
 516         if (mac->type == e1000_ich8lan)
 517                 mac->rar_entry_count--;
 518         /* FWSM register */
 519         mac->has_fwsm = true;
 520         /* ARC subsystem not supported */
 521         mac->arc_subsystem_valid = false;
 522         /* Adaptive IFS supported */
 523         mac->adaptive_ifs = true;
 524
 525         /* LED operations */
 526         switch (mac->type) {
 527         case e1000_ich8lan:
 528         case e1000_ich9lan:
 529         case e1000_ich10lan:
 530                 /* check management mode */
 531                 mac->ops.check_mng_mode = e1000_check_mng_mode_ich8lan;
 532                 /* ID LED init */
 533                 mac->ops.id_led_init = e1000e_id_led_init;
 534                 /* setup LED */
 535                 mac->ops.setup_led = e1000e_setup_led_generic;
 536                 /* cleanup LED */
 537                 mac->ops.cleanup_led = e1000_cleanup_led_ich8lan;
 538                 /* turn on/off LED */
 539                 mac->ops.led_on = e1000_led_on_ich8lan;
 540                 mac->ops.led_off = e1000_led_off_ich8lan;
 541                 break;
 542         case e1000_pchlan:
 543         case e1000_pch2lan:
 544                 /* check management mode */
 545                 mac->ops.check_mng_mode = e1000_check_mng_mode_pchlan;
 546                 /* ID LED init */
 547                 mac->ops.id_led_init = e1000_id_led_init_pchlan;
 548                 /* setup LED */
 549                 mac->ops.setup_led = e1000_setup_led_pchlan;
 550                 /* cleanup LED */
 551                 mac->ops.cleanup_led = e1000_cleanup_led_pchlan;
 552                 /* turn on/off LED */
 553                 mac->ops.led_on = e1000_led_on_pchlan;
 554                 mac->ops.led_off = e1000_led_off_pchlan;
 555                 break;
 556         default:
 557                 break;
 558         }
 559
 560         /* Enable PCS Lock-loss workaround for ICH8 */
 561         if (mac->type == e1000_ich8lan)
 562                 e1000e_set_kmrn_lock_loss_workaround_ich8lan(hw, true);
 563
 564         /* Disable PHY configuration by hardware, config by software */
 565         if (mac->type == e1000_pch2lan) {
 566                 u32 extcnf_ctrl = er32(EXTCNF_CTRL);
 567
 568                 extcnf_ctrl |= E1000_EXTCNF_CTRL_GATE_PHY_CFG;
 569                 ew32(EXTCNF_CTRL, extcnf_ctrl);
 570         }
 571
 572         return 0;
 573 }
 574
 575 /**
 576  *  e1000_set_eee_pchlan - Enable/disable EEE support
 577  *  @hw: pointer to the HW structure
 578  *
 579  *  Enable/disable EEE based on setting in dev_spec structure.  The bits in
 580  *  the LPI Control register will remain set only if/when link is up.
 581  **/
 582 static s32 e1000_set_eee_pchlan(struct e1000_hw *hw)
 583 {
 584         s32 ret_val = 0;
 585         u16 phy_reg;
 586
 587         if (hw->phy.type != e1000_phy_82579)
 588                 goto out;
 589
 590         ret_val = e1e_rphy(hw, I82579_LPI_CTRL, &phy_reg);
 591         if (ret_val)
 592                 goto out;
 593
 594         if (hw->dev_spec.ich8lan.eee_disable)
 595                 phy_reg &= ~I82579_LPI_CTRL_ENABLE_MASK;
 596         else
 597                 phy_reg |= I82579_LPI_CTRL_ENABLE_MASK;
 598
 599         ret_val = e1e_wphy(hw, I82579_LPI_CTRL, phy_reg);
 600 out:
 601         return ret_val;
 602 }
 603
 604 /**
 605  *  e1000_check_for_copper_link_ich8lan - Check for link (Copper)
 606  *  @hw: pointer to the HW structure
 607  *
 608  *  Checks to see of the link status of the hardware has changed.  If a
 609  *  change in link status has been detected, then we read the PHY registers
 610  *  to get the current speed/duplex if link exists.
 611  **/
 612 static s32 e1000_check_for_copper_link_ich8lan(struct e1000_hw *hw)
 613 {
 614         struct e1000_mac_info *mac = &hw->mac;
 615         s32 ret_val;
 616         bool link;
 617
 618         /*
 619          * We only want to go out to the PHY registers to see if Auto-Neg
 620          * has completed and/or if our link status has changed.  The
 621          * get_link_status flag is set upon receiving a Link Status
 622          * Change or Rx Sequence Error interrupt.
 623          */
 624         if (!mac->get_link_status) {
 625                 ret_val = 0;
 626                 goto out;
 627         }
 628
 629         /*
 630          * First we want to see if the MII Status Register reports
 631          * link.  If so, then we want to get the current speed/duplex
 632          * of the PHY.
 633          */
 634         ret_val = e1000e_phy_has_link_generic(hw, 1, 0, &link);
 635         if (ret_val)
 636                 goto out;
 637
 638         if (hw->mac.type == e1000_pchlan) {
 639                 ret_val = e1000_k1_gig_workaround_hv(hw, link);
 640                 if (ret_val)
 641                         goto out;
 642         }
 643
 644         if (!link)
 645                 goto out; /* No link detected */
 646
 647         mac->get_link_status = false;
 648
 649         if (hw->phy.type == e1000_phy_82578) {
 650                 ret_val = e1000_link_stall_workaround_hv(hw);
 651                 if (ret_val)
 652                         goto out;
 653         }
 654
 655         /*
 656          * Check if there was DownShift, must be checked
 657          * immediately after link-up
 658          */
 659         e1000e_check_downshift(hw);
 660
 661         /* Enable/Disable EEE after link up */
 662         ret_val = e1000_set_eee_pchlan(hw);
 663         if (ret_val)
 664                 goto out;
 665
 666         /*
 667          * If we are forcing speed/duplex, then we simply return since
 668          * we have already determined whether we have link or not.
 669          */
 670         if (!mac->autoneg) {
 671                 ret_val = -E1000_ERR_CONFIG;
 672                 goto out;
 673         }
 674
 675         /*
 676          * Auto-Neg is enabled.  Auto Speed Detection takes care
 677          * of MAC speed/duplex configuration.  So we only need to
 678          * configure Collision Distance in the MAC.
 679          */
 680         e1000e_config_collision_dist(hw);
 681
 682         /*
 683          * Configure Flow Control now that Auto-Neg has completed.
 684          * First, we need to restore the desired flow control
 685          * settings because we may have had to re-autoneg with a
 686          * different link partner.
 687          */
 688         ret_val = e1000e_config_fc_after_link_up(hw);
 689         if (ret_val)
 690                 e_dbg("Error configuring flow control\n");
 691
 692 out:
 693         return ret_val;
 694 }
 695
 696 static s32 e1000_get_variants_ich8lan(struct e1000_adapter *adapter)
 697 {
 698         struct e1000_hw *hw = &adapter->hw;
 699         s32 rc;
 700
 701         rc = e1000_init_mac_params_ich8lan(adapter);
 702         if (rc)
 703                 return rc;
 704
 705         rc = e1000_init_nvm_params_ich8lan(hw);
 706         if (rc)
 707                 return rc;
 708
 709         switch (hw->mac.type) {
 710         case e1000_ich8lan:
 711         case e1000_ich9lan:
 712         case e1000_ich10lan:
 713                 rc = e1000_init_phy_params_ich8lan(hw);
 714                 break;
 715         case e1000_pchlan:
 716         case e1000_pch2lan:
 717                 rc = e1000_init_phy_params_pchlan(hw);
 718                 break;
 719         default:
 720                 break;
 721         }
 722         if (rc)
 723                 return rc;
 724
 725         if (adapter->hw.phy.type == e1000_phy_ife) {
 726                 adapter->flags &= ~FLAG_HAS_JUMBO_FRAMES;
 727                 adapter->max_hw_frame_size = ETH_FRAME_LEN + ETH_FCS_LEN;
 728         }
 729
 730         if ((adapter->hw.mac.type == e1000_ich8lan) &&
 731             (adapter->hw.phy.type == e1000_phy_igp_3))
 732                 adapter->flags |= FLAG_LSC_GIG_SPEED_DROP;
 733
 734         return 0;
 735 }
 736
 737 static DEFINE_MUTEX(nvm_mutex);
 738
 739 /**
 740  *  e1000_acquire_nvm_ich8lan - Acquire NVM mutex
 741  *  @hw: pointer to the HW structure
 742  *
 743  *  Acquires the mutex for performing NVM operations.
 744  **/
 745 static s32 e1000_acquire_nvm_ich8lan(struct e1000_hw *hw)
 746 {
 747         mutex_lock(&nvm_mutex);
 748
 749         return 0;
 750 }
 751
 752 /**
 753  *  e1000_release_nvm_ich8lan - Release NVM mutex
 754  *  @hw: pointer to the HW structure
 755  *
 756  *  Releases the mutex used while performing NVM operations.
 757  **/
 758 static void e1000_release_nvm_ich8lan(struct e1000_hw *hw)
 759 {
 760         mutex_unlock(&nvm_mutex);
 761 }
 762
 763 static DEFINE_MUTEX(swflag_mutex);
 764
 765 /**
 766  *  e1000_acquire_swflag_ich8lan - Acquire software control flag
 767  *  @hw: pointer to the HW structure
 768  *
 769  *  Acquires the software control flag for performing PHY and select
 770  *  MAC CSR accesses.
 771  **/
 772 static s32 e1000_acquire_swflag_ich8lan(struct e1000_hw *hw)
 773 {
 774         u32 extcnf_ctrl, timeout = PHY_CFG_TIMEOUT;
 775         s32 ret_val = 0;
 776
 777         mutex_lock(&swflag_mutex);
 778
 779         while (timeout) {
 780                 extcnf_ctrl = er32(EXTCNF_CTRL);
 781                 if (!(extcnf_ctrl & E1000_EXTCNF_CTRL_SWFLAG))
 782                         break;
 783
 784                 mdelay(1);
 785                 timeout--;
 786         }
 787
 788         if (!timeout) {
 789                 e_dbg("SW/FW/HW has locked the resource for too long.\n");
 790                 ret_val = -E1000_ERR_CONFIG;
 791                 goto out;
 792         }
 793
 794         timeout = SW_FLAG_TIMEOUT;
 795
 796         extcnf_ctrl |= E1000_EXTCNF_CTRL_SWFLAG;
 797         ew32(EXTCNF_CTRL, extcnf_ctrl);
 798
 799         while (timeout) {
 800                 extcnf_ctrl = er32(EXTCNF_CTRL);
 801                 if (extcnf_ctrl & E1000_EXTCNF_CTRL_SWFLAG)
 802                         break;
 803
 804                 mdelay(1);
 805                 timeout--;
 806         }
 807
 808         if (!timeout) {
 809                 e_dbg("Failed to acquire the semaphore.\n");
 810                 extcnf_ctrl &= ~E1000_EXTCNF_CTRL_SWFLAG;
 811                 ew32(EXTCNF_CTRL, extcnf_ctrl);
 812                 ret_val = -E1000_ERR_CONFIG;
 813                 goto out;
 814         }
 815
 816 out:
 817         if (ret_val)
 818                 mutex_unlock(&swflag_mutex);
 819
 820         return ret_val;
 821 }
 822
 823 /**
 824  *  e1000_release_swflag_ich8lan - Release software control flag
 825  *  @hw: pointer to the HW structure
 826  *
 827  *  Releases the software control flag for performing PHY and select
 828  *  MAC CSR accesses.
 829  **/
 830 static void e1000_release_swflag_ich8lan(struct e1000_hw *hw)
 831 {
 832         u32 extcnf_ctrl;
 833
 834         extcnf_ctrl = er32(EXTCNF_CTRL);
 835         extcnf_ctrl &= ~E1000_EXTCNF_CTRL_SWFLAG;
 836         ew32(EXTCNF_CTRL, extcnf_ctrl);
 837
 838         mutex_unlock(&swflag_mutex);
 839 }
 840
 841 /**
 842  *  e1000_check_mng_mode_ich8lan - Checks management mode
 843  *  @hw: pointer to the HW structure
 844  *
 845  *  This checks if the adapter has any manageability enabled.
 846  *  This is a function pointer entry point only called by read/write
 847  *  routines for the PHY and NVM parts.
 848  **/
 849 static bool e1000_check_mng_mode_ich8lan(struct e1000_hw *hw)
 850 {
 851         u32 fwsm;
 852
 853         fwsm = er32(FWSM);
 854         return (fwsm & E1000_ICH_FWSM_FW_VALID) &&
 855                ((fwsm & E1000_FWSM_MODE_MASK) ==
 856                 (E1000_ICH_MNG_IAMT_MODE << E1000_FWSM_MODE_SHIFT));
 857 }
 858
 859 /**
 860  *  e1000_check_mng_mode_pchlan - Checks management mode
 861  *  @hw: pointer to the HW structure
 862  *
 863  *  This checks if the adapter has iAMT enabled.
 864  *  This is a function pointer entry point only called by read/write
 865  *  routines for the PHY and NVM parts.
 866  **/
 867 static bool e1000_check_mng_mode_pchlan(struct e1000_hw *hw)
 868 {
 869         u32 fwsm;
 870
 871         fwsm = er32(FWSM);
 872         return (fwsm & E1000_ICH_FWSM_FW_VALID) &&
 873                (fwsm & (E1000_ICH_MNG_IAMT_MODE << E1000_FWSM_MODE_SHIFT));
 874 }
 875
 876 /**
 877  *  e1000_check_reset_block_ich8lan - Check if PHY reset is blocked
 878  *  @hw: pointer to the HW structure
 879  *
 880  *  Checks if firmware is blocking the reset of the PHY.
 881  *  This is a function pointer entry point only called by
 882  *  reset routines.
 883  **/
 884 static s32 e1000_check_reset_block_ich8lan(struct e1000_hw *hw)
 885 {
 886         u32 fwsm;
 887
 888         fwsm = er32(FWSM);
 889
 890         return (fwsm & E1000_ICH_FWSM_RSPCIPHY) ? 0 : E1000_BLK_PHY_RESET;
 891 }
 892
 893 /**
 894  *  e1000_sw_lcd_config_ich8lan - SW-based LCD Configuration
 895  *  @hw:   pointer to the HW structure
 896  *
 897  *  SW should configure the LCD from the NVM extended configuration region
 898  *  as a workaround for certain parts.
 899  **/
 900 static s32 e1000_sw_lcd_config_ich8lan(struct e1000_hw *hw)
 901 {
 902         struct e1000_adapter *adapter = hw->adapter;
 903         struct e1000_phy_info *phy = &hw->phy;
 904         u32 i, data, cnf_size, cnf_base_addr, sw_cfg_mask;
 905         s32 ret_val = 0;
 906         u16 word_addr, reg_data, reg_addr, phy_page = 0;
 907
 908         /*
 909          * Initialize the PHY from the NVM on ICH platforms.  This
 910          * is needed due to an issue where the NVM configuration is
 911          * not properly autoloaded after power transitions.
 912          * Therefore, after each PHY reset, we will load the
 913          * configuration data out of the NVM manually.
 914          */
 915         switch (hw->mac.type) {
 916         case e1000_ich8lan:
 917                 if (phy->type != e1000_phy_igp_3)
 918                         return ret_val;
 919
 920                 if (adapter->pdev->device == E1000_DEV_ID_ICH8_IGP_AMT) {
 921                         sw_cfg_mask = E1000_FEXTNVM_SW_CONFIG;
 922                         break;
 923                 }
 924                 /* Fall-thru */
 925         case e1000_pchlan:
 926         case e1000_pch2lan:
 927                 sw_cfg_mask = E1000_FEXTNVM_SW_CONFIG_ICH8M;
 928                 break;
 929         default:
 930                 return ret_val;
 931         }
 932
 933         ret_val = hw->phy.ops.acquire(hw);
 934         if (ret_val)
 935                 return ret_val;
 936
 937         data = er32(FEXTNVM);
 938         if (!(data & sw_cfg_mask))
 939                 goto out;
 940
 941         /*
 942          * Make sure HW does not configure LCD from PHY
 943          * extended configuration before SW configuration
 944          */
 945         data = er32(EXTCNF_CTRL);
 946         if (!(hw->mac.type == e1000_pch2lan)) {
 947                 if (data & E1000_EXTCNF_CTRL_LCD_WRITE_ENABLE)
 948                         goto out;
 949         }
 950
 951         cnf_size = er32(EXTCNF_SIZE);
 952         cnf_size &= E1000_EXTCNF_SIZE_EXT_PCIE_LENGTH_MASK;
 953         cnf_size >>= E1000_EXTCNF_SIZE_EXT_PCIE_LENGTH_SHIFT;
 954         if (!cnf_size)
 955                 goto out;
 956
 957         cnf_base_addr = data & E1000_EXTCNF_CTRL_EXT_CNF_POINTER_MASK;
 958         cnf_base_addr >>= E1000_EXTCNF_CTRL_EXT_CNF_POINTER_SHIFT;
 959
 960         if (!(data & E1000_EXTCNF_CTRL_OEM_WRITE_ENABLE) &&
 961             ((hw->mac.type == e1000_pchlan) ||
 962              (hw->mac.type == e1000_pch2lan))) {
 963                 /*
 964                  * HW configures the SMBus address and LEDs when the
 965                  * OEM and LCD Write Enable bits are set in the NVM.
 966                  * When both NVM bits are cleared, SW will configure
 967                  * them instead.
 968                  */
 969                 data = er32(STRAP);
 970                 data &= E1000_STRAP_SMBUS_ADDRESS_MASK;
 971                 reg_data = data >> E1000_STRAP_SMBUS_ADDRESS_SHIFT;
 972                 reg_data |= HV_SMB_ADDR_PEC_EN | HV_SMB_ADDR_VALID;
 973                 ret_val = e1000_write_phy_reg_hv_locked(hw, HV_SMB_ADDR,
 974                                                         reg_data);
 975                 if (ret_val)
 976                         goto out;
 977
 978                 data = er32(LEDCTL);
 979                 ret_val = e1000_write_phy_reg_hv_locked(hw, HV_LED_CONFIG,
 980                                                         (u16)data);
 981                 if (ret_val)
 982                         goto out;
 983         }
 984
 985         /* Configure LCD from extended configuration region. */
 986
 987         /* cnf_base_addr is in DWORD */
 988         word_addr = (u16)(cnf_base_addr << 1);
 989
 990         for (i = 0; i < cnf_size; i++) {
 991                 ret_val = e1000_read_nvm(hw, (word_addr + i * 2), 1,
 992                                          &reg_data);
 993                 if (ret_val)
 994                         goto out;
 995
 996                 ret_val = e1000_read_nvm(hw, (word_addr + i * 2 + 1),
 997                                          1, &reg_addr);
 998                 if (ret_val)
 999                         goto out;
1000
1001                 /* Save off the PHY page for future writes. */
1002                 if (reg_addr == IGP01E1000_PHY_PAGE_SELECT) {
1003                         phy_page = reg_data;
1004                         continue;
1005                 }
1006
1007                 reg_addr &= PHY_REG_MASK;
1008                 reg_addr |= phy_page;
1009
1010                 ret_val = phy->ops.write_reg_locked(hw, (u32)reg_addr,
1011                                                     reg_data);
1012                 if (ret_val)
1013                         goto out;
1014         }
1015
1016 out:
1017         hw->phy.ops.release(hw);
1018         return ret_val;
1019 }
1020
1021 /**
1022  *  e1000_k1_gig_workaround_hv - K1 Si workaround
1023  *  @hw:   pointer to the HW structure
1024  *  @link: link up bool flag
1025  *
1026  *  If K1 is enabled for 1Gbps, the MAC might stall when transitioning
1027  *  from a lower speed.  This workaround disables K1 whenever link is at 1Gig
1028  *  If link is down, the function will restore the default K1 setting located
1029  *  in the NVM.
1030  **/
1031 static s32 e1000_k1_gig_workaround_hv(struct e1000_hw *hw, bool link)
1032 {
1033         s32 ret_val = 0;
1034         u16 status_reg = 0;
1035         bool k1_enable = hw->dev_spec.ich8lan.nvm_k1_enabled;
1036
1037         if (hw->mac.type != e1000_pchlan)
1038                 goto out;
1039
1040         /* Wrap the whole flow with the sw flag */
1041         ret_val = hw->phy.ops.acquire(hw);
1042         if (ret_val)
1043                 goto out;
1044
1045         /* Disable K1 when link is 1Gbps, otherwise use the NVM setting */
1046         if (link) {
1047                 if (hw->phy.type == e1000_phy_82578) {
1048                         ret_val = hw->phy.ops.read_reg_locked(hw, BM_CS_STATUS,
1049                                                                   &status_reg);
1050                         if (ret_val)
1051                                 goto release;
1052
1053                         status_reg &= BM_CS_STATUS_LINK_UP |
1054                                       BM_CS_STATUS_RESOLVED |
1055                                       BM_CS_STATUS_SPEED_MASK;
1056
1057                         if (status_reg == (BM_CS_STATUS_LINK_UP |
1058                                            BM_CS_STATUS_RESOLVED |
1059                                            BM_CS_STATUS_SPEED_1000))
1060                                 k1_enable = false;
1061                 }
1062
1063                 if (hw->phy.type == e1000_phy_82577) {
1064                         ret_val = hw->phy.ops.read_reg_locked(hw, HV_M_STATUS,
1065                                                                   &status_reg);
1066                         if (ret_val)
1067                                 goto release;
1068
1069                         status_reg &= HV_M_STATUS_LINK_UP |
1070                                       HV_M_STATUS_AUTONEG_COMPLETE |
1071                                       HV_M_STATUS_SPEED_MASK;
1072
1073                         if (status_reg == (HV_M_STATUS_LINK_UP |
1074                                            HV_M_STATUS_AUTONEG_COMPLETE |
1075                                            HV_M_STATUS_SPEED_1000))
1076                                 k1_enable = false;
1077                 }
1078
1079                 /* Link stall fix for link up */
1080                 ret_val = hw->phy.ops.write_reg_locked(hw, PHY_REG(770, 19),
1081                                                            0x0100);
1082                 if (ret_val)
1083                         goto release;
1084
1085         } else {
1086                 /* Link stall fix for link down */
1087                 ret_val = hw->phy.ops.write_reg_locked(hw, PHY_REG(770, 19),
1088                                                            0x4100);
1089                 if (ret_val)
1090                         goto release;
1091         }
1092
1093         ret_val = e1000_configure_k1_ich8lan(hw, k1_enable);
1094
1095 release:
1096         hw->phy.ops.release(hw);
1097 out:
1098         return ret_val;
1099 }
1100
1101 /**
1102  *  e1000_configure_k1_ich8lan - Configure K1 power state
1103  *  @hw: pointer to the HW structure
1104  *  @enable: K1 state to configure
1105  *
1106  *  Configure the K1 power state based on the provided parameter.
1107  *  Assumes semaphore already acquired.
1108  *
1109  *  Success returns 0, Failure returns -E1000_ERR_PHY (-2)
1110  **/
1111 s32 e1000_configure_k1_ich8lan(struct e1000_hw *hw, bool k1_enable)
1112 {
1113         s32 ret_val = 0;
1114         u32 ctrl_reg = 0;
1115         u32 ctrl_ext = 0;
1116         u32 reg = 0;
1117         u16 kmrn_reg = 0;
1118
1119         ret_val = e1000e_read_kmrn_reg_locked(hw,
1120                                              E1000_KMRNCTRLSTA_K1_CONFIG,
1121                                              &kmrn_reg);
1122         if (ret_val)
1123                 goto out;
1124
1125         if (k1_enable)
1126                 kmrn_reg |= E1000_KMRNCTRLSTA_K1_ENABLE;
1127         else
1128                 kmrn_reg &= ~E1000_KMRNCTRLSTA_K1_ENABLE;
1129
1130         ret_val = e1000e_write_kmrn_reg_locked(hw,
1131                                               E1000_KMRNCTRLSTA_K1_CONFIG,
1132                                               kmrn_reg);
1133         if (ret_val)
1134                 goto out;
1135
1136         udelay(20);
1137         ctrl_ext = er32(CTRL_EXT);
1138         ctrl_reg = er32(CTRL);
1139
1140         reg = ctrl_reg & ~(E1000_CTRL_SPD_1000 | E1000_CTRL_SPD_100);
1141         reg |= E1000_CTRL_FRCSPD;
1142         ew32(CTRL, reg);
1143
1144         ew32(CTRL_EXT, ctrl_ext | E1000_CTRL_EXT_SPD_BYPS);
1145         udelay(20);
1146         ew32(CTRL, ctrl_reg);
1147         ew32(CTRL_EXT, ctrl_ext);
1148         udelay(20);
1149
1150 out:
1151         return ret_val;
1152 }
1153
1154 /**
1155  *  e1000_oem_bits_config_ich8lan - SW-based LCD Configuration
1156  *  @hw:       pointer to the HW structure
1157  *  @d0_state: boolean if entering d0 or d3 device state
1158  *
1159  *  SW will configure Gbe Disable and LPLU based on the NVM. The four bits are
1160  *  collectively called OEM bits.  The OEM Write Enable bit and SW Config bit
1161  *  in NVM determines whether HW should configure LPLU and Gbe Disable.
1162  **/
1163 static s32 e1000_oem_bits_config_ich8lan(struct e1000_hw *hw, bool d0_state)
1164 {
1165         s32 ret_val = 0;
1166         u32 mac_reg;
1167         u16 oem_reg;
1168
1169         if ((hw->mac.type != e1000_pch2lan) && (hw->mac.type != e1000_pchlan))
1170                 return ret_val;
1171
1172         ret_val = hw->phy.ops.acquire(hw);
1173         if (ret_val)
1174                 return ret_val;
1175
1176         if (!(hw->mac.type == e1000_pch2lan)) {
1177                 mac_reg = er32(EXTCNF_CTRL);
1178                 if (mac_reg & E1000_EXTCNF_CTRL_OEM_WRITE_ENABLE)
1179                         goto out;
1180         }
1181
1182         mac_reg = er32(FEXTNVM);
1183         if (!(mac_reg & E1000_FEXTNVM_SW_CONFIG_ICH8M))
1184                 goto out;
1185
1186         mac_reg = er32(PHY_CTRL);
1187
1188         ret_val = hw->phy.ops.read_reg_locked(hw, HV_OEM_BITS, &oem_reg);
1189         if (ret_val)
1190                 goto out;
1191
1192         oem_reg &= ~(HV_OEM_BITS_GBE_DIS | HV_OEM_BITS_LPLU);
1193
1194         if (d0_state) {
1195                 if (mac_reg & E1000_PHY_CTRL_GBE_DISABLE)
1196                         oem_reg |= HV_OEM_BITS_GBE_DIS;
1197
1198                 if (mac_reg & E1000_PHY_CTRL_D0A_LPLU)
1199                         oem_reg |= HV_OEM_BITS_LPLU;
1200         } else {
1201                 if (mac_reg & E1000_PHY_CTRL_NOND0A_GBE_DISABLE)
1202                         oem_reg |= HV_OEM_BITS_GBE_DIS;
1203
1204                 if (mac_reg & E1000_PHY_CTRL_NOND0A_LPLU)
1205                         oem_reg |= HV_OEM_BITS_LPLU;
1206         }
1207         /* Restart auto-neg to activate the bits */
1208         if (!e1000_check_reset_block(hw))
1209                 oem_reg |= HV_OEM_BITS_RESTART_AN;
1210         ret_val = hw->phy.ops.write_reg_locked(hw, HV_OEM_BITS, oem_reg);
1211
1212 out:
1213         hw->phy.ops.release(hw);
1214
1215         return ret_val;
1216 }
1217
1218
1219 /**
1220  *  e1000_set_mdio_slow_mode_hv - Set slow MDIO access mode
1221  *  @hw:   pointer to the HW structure
1222  **/
1223 static s32 e1000_set_mdio_slow_mode_hv(struct e1000_hw *hw)
1224 {
1225         s32 ret_val;
1226         u16 data;
1227
1228         ret_val = e1e_rphy(hw, HV_KMRN_MODE_CTRL, &data);
1229         if (ret_val)
1230                 return ret_val;
1231
1232         data |= HV_KMRN_MDIO_SLOW;
1233
1234         ret_val = e1e_wphy(hw, HV_KMRN_MODE_CTRL, data);
1235
1236         return ret_val;
1237 }
1238
1239 /**
1240  *  e1000_hv_phy_workarounds_ich8lan - A series of Phy workarounds to be
1241  *  done after every PHY reset.
1242  **/
1243 static s32 e1000_hv_phy_workarounds_ich8lan(struct e1000_hw *hw)
1244 {
1245         s32 ret_val = 0;
1246         u16 phy_data;
1247
1248         if (hw->mac.type != e1000_pchlan)
1249                 return ret_val;
1250
1251         /* Set MDIO slow mode before any other MDIO access */
1252         if (hw->phy.type == e1000_phy_82577) {
1253                 ret_val = e1000_set_mdio_slow_mode_hv(hw);
1254                 if (ret_val)
1255                         goto out;
1256         }
1257
1258         if (((hw->phy.type == e1000_phy_82577) &&
1259              ((hw->phy.revision == 1) || (hw->phy.revision == 2))) ||
1260             ((hw->phy.type == e1000_phy_82578) && (hw->phy.revision == 1))) {
1261                 /* Disable generation of early preamble */
1262                 ret_val = e1e_wphy(hw, PHY_REG(769, 25), 0x4431);
1263                 if (ret_val)
1264                         return ret_val;
1265
1266                 /* Preamble tuning for SSC */
1267                 ret_val = e1e_wphy(hw, PHY_REG(770, 16), 0xA204);
1268                 if (ret_val)
1269                         return ret_val;
1270         }
1271
1272         if (hw->phy.type == e1000_phy_82578) {
1273                 /*
1274                  * Return registers to default by doing a soft reset then
1275                  * writing 0x3140 to the control register.
1276                  */
1277                 if (hw->phy.revision < 2) {
1278                         e1000e_phy_sw_reset(hw);
1279                         ret_val = e1e_wphy(hw, PHY_CONTROL, 0x3140);
1280                 }
1281         }
1282
1283         /* Select page 0 */
1284         ret_val = hw->phy.ops.acquire(hw);
1285         if (ret_val)
1286                 return ret_val;
1287
1288         hw->phy.addr = 1;
1289         ret_val = e1000e_write_phy_reg_mdic(hw, IGP01E1000_PHY_PAGE_SELECT, 0);
1290         hw->phy.ops.release(hw);
1291         if (ret_val)
1292                 goto out;
1293
1294         /*
1295          * Configure the K1 Si workaround during phy reset assuming there is
1296          * link so that it disables K1 if link is in 1Gbps.
1297          */
1298         ret_val = e1000_k1_gig_workaround_hv(hw, true);
1299         if (ret_val)
1300                 goto out;
1301
1302         /* Workaround for link disconnects on a busy hub in half duplex */
1303         ret_val = hw->phy.ops.acquire(hw);
1304         if (ret_val)
1305                 goto out;
1306         ret_val = hw->phy.ops.read_reg_locked(hw,
1307                                               PHY_REG(BM_PORT_CTRL_PAGE, 17),
1308                                               &phy_data);
1309         if (ret_val)
1310                 goto release;
1311         ret_val = hw->phy.ops.write_reg_locked(hw,
1312                                                PHY_REG(BM_PORT_CTRL_PAGE, 17),
1313                                                phy_data & 0x00FF);
1314 release:
1315         hw->phy.ops.release(hw);
1316 out:
1317         return ret_val;
1318 }
1319
1320 /**
1321  *  e1000_copy_rx_addrs_to_phy_ich8lan - Copy Rx addresses from MAC to PHY
1322  *  @hw:   pointer to the HW structure
1323  **/
1324 void e1000_copy_rx_addrs_to_phy_ich8lan(struct e1000_hw *hw)
1325 {
1326         u32 mac_reg;
1327         u16 i;
1328
1329         /* Copy both RAL/H (rar_entry_count) and SHRAL/H (+4) to PHY */
1330         for (i = 0; i < (hw->mac.rar_entry_count + 4); i++) {
1331                 mac_reg = er32(RAL(i));
1332                 e1e_wphy(hw, BM_RAR_L(i), (u16)(mac_reg & 0xFFFF));
1333                 e1e_wphy(hw, BM_RAR_M(i), (u16)((mac_reg >> 16) & 0xFFFF));
1334                 mac_reg = er32(RAH(i));
1335                 e1e_wphy(hw, BM_RAR_H(i), (u16)(mac_reg & 0xFFFF));
1336                 e1e_wphy(hw, BM_RAR_CTRL(i), (u16)((mac_reg >> 16) & 0x8000));
1337         }
1338 }
1339
1340 static u32 e1000_calc_rx_da_crc(u8 mac[])
1341 {
1342         u32 poly = 0xEDB88320;  /* Polynomial for 802.3 CRC calculation */
1343         u32 i, j, mask, crc;
1344
1345         crc = 0xffffffff;
1346         for (i = 0; i < 6; i++) {
1347                 crc = crc ^ mac[i];
1348                 for (j = 8; j > 0; j--) {
1349                         mask = (crc & 1) * (-1);
1350                         crc = (crc >> 1) ^ (poly & mask);
1351                 }
1352         }
1353         return ~crc;
1354 }
1355
1356 /**
1357  *  e1000_lv_jumbo_workaround_ich8lan - required for jumbo frame operation
1358  *  with 82579 PHY
1359  *  @hw: pointer to the HW structure
1360  *  @enable: flag to enable/disable workaround when enabling/disabling jumbos
1361  **/
1362 s32 e1000_lv_jumbo_workaround_ich8lan(struct e1000_hw *hw, bool enable)
1363 {
1364         s32 ret_val = 0;
1365         u16 phy_reg, data;
1366         u32 mac_reg;
1367         u16 i;
1368
1369         if (hw->mac.type != e1000_pch2lan)
1370                 goto out;
1371
1372         /* disable Rx path while enabling/disabling workaround */
1373         e1e_rphy(hw, PHY_REG(769, 20), &phy_reg);
1374         ret_val = e1e_wphy(hw, PHY_REG(769, 20), phy_reg | (1 << 14));
1375         if (ret_val)
1376                 goto out;
1377
1378         if (enable) {
1379                 /*
1380                  * Write Rx addresses (rar_entry_count for RAL/H, +4 for
1381                  * SHRAL/H) and initial CRC values to the MAC
1382                  */
1383                 for (i = 0; i < (hw->mac.rar_entry_count + 4); i++) {
1384                         u8 mac_addr[ETH_ALEN] = {0};
1385                         u32 addr_high, addr_low;
1386
1387                         addr_high = er32(RAH(i));
1388                         if (!(addr_high & E1000_RAH_AV))
1389                                 continue;
1390                         addr_low = er32(RAL(i));
1391                         mac_addr[0] = (addr_low & 0xFF);
1392                         mac_addr[1] = ((addr_low >> 8) & 0xFF);
1393                         mac_addr[2] = ((addr_low >> 16) & 0xFF);
1394                         mac_addr[3] = ((addr_low >> 24) & 0xFF);
1395                         mac_addr[4] = (addr_high & 0xFF);
1396                         mac_addr[5] = ((addr_high >> 8) & 0xFF);
1397
1398                         ew32(PCH_RAICC(i),
1399                                         e1000_calc_rx_da_crc(mac_addr));
1400                 }
1401
1402                 /* Write Rx addresses to the PHY */
1403                 e1000_copy_rx_addrs_to_phy_ich8lan(hw);
1404
1405                 /* Enable jumbo frame workaround in the MAC */
1406                 mac_reg = er32(FFLT_DBG);
1407                 mac_reg &= ~(1 << 14);
1408                 mac_reg |= (7 << 15);
1409                 ew32(FFLT_DBG, mac_reg);
1410
1411                 mac_reg = er32(RCTL);
1412                 mac_reg |= E1000_RCTL_SECRC;
1413                 ew32(RCTL, mac_reg);
1414
1415                 ret_val = e1000e_read_kmrn_reg(hw,
1416                                                 E1000_KMRNCTRLSTA_CTRL_OFFSET,
1417                                                 &data);
1418                 if (ret_val)
1419                         goto out;
1420                 ret_val = e1000e_write_kmrn_reg(hw,
1421                                                 E1000_KMRNCTRLSTA_CTRL_OFFSET,
1422                                                 data | (1 << 0));
1423                 if (ret_val)
1424                         goto out;
1425                 ret_val = e1000e_read_kmrn_reg(hw,
1426                                                 E1000_KMRNCTRLSTA_HD_CTRL,
1427                                                 &data);
1428                 if (ret_val)
1429                         goto out;
1430                 data &= ~(0xF << 8);
1431                 data |= (0xB << 8);
1432                 ret_val = e1000e_write_kmrn_reg(hw,
1433                                                 E1000_KMRNCTRLSTA_HD_CTRL,
1434                                                 data);
1435                 if (ret_val)
1436                         goto out;
1437
1438                 /* Enable jumbo frame workaround in the PHY */
1439                 e1e_rphy(hw, PHY_REG(769, 20), &data);
1440                 ret_val = e1e_wphy(hw, PHY_REG(769, 20), data & ~(1 << 14));
1441                 if (ret_val)
1442                         goto out;
1443                 e1e_rphy(hw, PHY_REG(769, 23), &data);
1444                 data &= ~(0x7F << 5);
1445                 data |= (0x37 << 5);
1446                 ret_val = e1e_wphy(hw, PHY_REG(769, 23), data);
1447                 if (ret_val)
1448                         goto out;
1449                 e1e_rphy(hw, PHY_REG(769, 16), &data);
1450                 data &= ~(1 << 13);
1451                 data |= (1 << 12);
1452                 ret_val = e1e_wphy(hw, PHY_REG(769, 16), data);
1453                 if (ret_val)
1454                         goto out;
1455                 e1e_rphy(hw, PHY_REG(776, 20), &data);
1456                 data &= ~(0x3FF << 2);
1457                 data |= (0x1A << 2);
1458                 ret_val = e1e_wphy(hw, PHY_REG(776, 20), data);
1459                 if (ret_val)
1460                         goto out;
1461                 ret_val = e1e_wphy(hw, PHY_REG(776, 23), 0xFE00);
1462                 if (ret_val)
1463                         goto out;
1464                 e1e_rphy(hw, HV_PM_CTRL, &data);
1465                 ret_val = e1e_wphy(hw, HV_PM_CTRL, data | (1 << 10));
1466                 if (ret_val)
1467                         goto out;
1468         } else {
1469                 /* Write MAC register values back to h/w defaults */
1470                 mac_reg = er32(FFLT_DBG);
1471                 mac_reg &= ~(0xF << 14);
1472                 ew32(FFLT_DBG, mac_reg);
1473
1474                 mac_reg = er32(RCTL);
1475                 mac_reg &= ~E1000_RCTL_SECRC;
1476                 ew32(FFLT_DBG, mac_reg);
1477
1478                 ret_val = e1000e_read_kmrn_reg(hw,
1479                                                 E1000_KMRNCTRLSTA_CTRL_OFFSET,
1480                                                 &data);
1481                 if (ret_val)
1482                         goto out;
1483                 ret_val = e1000e_write_kmrn_reg(hw,
1484                                                 E1000_KMRNCTRLSTA_CTRL_OFFSET,
1485                                                 data & ~(1 << 0));
1486                 if (ret_val)
1487                         goto out;
1488                 ret_val = e1000e_read_kmrn_reg(hw,
1489                                                 E1000_KMRNCTRLSTA_HD_CTRL,
1490                                                 &data);
1491                 if (ret_val)
1492                         goto out;
1493                 data &= ~(0xF << 8);
1494                 data |= (0xB << 8);
1495                 ret_val = e1000e_write_kmrn_reg(hw,
1496                                                 E1000_KMRNCTRLSTA_HD_CTRL,
1497                                                 data);
1498                 if (ret_val)
1499                         goto out;
1500
1501                 /* Write PHY register values back to h/w defaults */
1502                 e1e_rphy(hw, PHY_REG(769, 20), &data);
1503                 ret_val = e1e_wphy(hw, PHY_REG(769, 20), data & ~(1 << 14));
1504                 if (ret_val)
1505                         goto out;
1506                 e1e_rphy(hw, PHY_REG(769, 23), &data);
1507                 data &= ~(0x7F << 5);
1508                 ret_val = e1e_wphy(hw, PHY_REG(769, 23), data);
1509                 if (ret_val)
1510                         goto out;
1511                 e1e_rphy(hw, PHY_REG(769, 16), &data);
1512                 data &= ~(1 << 12);
1513                 data |= (1 << 13);
1514                 ret_val = e1e_wphy(hw, PHY_REG(769, 16), data);
1515                 if (ret_val)
1516                         goto out;
1517                 e1e_rphy(hw, PHY_REG(776, 20), &data);
1518                 data &= ~(0x3FF << 2);
1519                 data |= (0x8 << 2);
1520                 ret_val = e1e_wphy(hw, PHY_REG(776, 20), data);
1521                 if (ret_val)
1522                         goto out;
1523                 ret_val = e1e_wphy(hw, PHY_REG(776, 23), 0x7E00);
1524                 if (ret_val)
1525                         goto out;
1526                 e1e_rphy(hw, HV_PM_CTRL, &data);
1527                 ret_val = e1e_wphy(hw, HV_PM_CTRL, data & ~(1 << 10));
1528                 if (ret_val)
1529                         goto out;
1530         }
1531
1532         /* re-enable Rx path after enabling/disabling workaround */
1533         ret_val = e1e_wphy(hw, PHY_REG(769, 20), phy_reg & ~(1 << 14));
1534
1535 out:
1536         return ret_val;
1537 }
1538
1539 /**
1540  *  e1000_lv_phy_workarounds_ich8lan - A series of Phy workarounds to be
1541  *  done after every PHY reset.
1542  **/
1543 static s32 e1000_lv_phy_workarounds_ich8lan(struct e1000_hw *hw)
1544 {
1545         s32 ret_val = 0;
1546
1547         if (hw->mac.type != e1000_pch2lan)
1548                 goto out;
1549
1550         /* Set MDIO slow mode before any other MDIO access */
1551         ret_val = e1000_set_mdio_slow_mode_hv(hw);
1552
1553 out:
1554         return ret_val;
1555 }
1556
1557 /**
1558  *  e1000_lan_init_done_ich8lan - Check for PHY config completion
1559  *  @hw: pointer to the HW structure
1560  *
1561  *  Check the appropriate indication the MAC has finished configuring the
1562  *  PHY after a software reset.
1563  **/
1564 static void e1000_lan_init_done_ich8lan(struct e1000_hw *hw)
1565 {
1566         u32 data, loop = E1000_ICH8_LAN_INIT_TIMEOUT;
1567
1568         /* Wait for basic configuration completes before proceeding */
1569         do {
1570                 data = er32(STATUS);
1571                 data &= E1000_STATUS_LAN_INIT_DONE;
1572                 udelay(100);
1573         } while ((!data) && --loop);
1574
1575         /*
1576          * If basic configuration is incomplete before the above loop
1577          * count reaches 0, loading the configuration from NVM will
1578          * leave the PHY in a bad state possibly resulting in no link.
1579          */
1580         if (loop == 0)
1581                 e_dbg("LAN_INIT_DONE not set, increase timeout\n");
1582
1583         /* Clear the Init Done bit for the next init event */
1584         data = er32(STATUS);
1585         data &= ~E1000_STATUS_LAN_INIT_DONE;
1586         ew32(STATUS, data);
1587 }
1588
1589 /**
1590  *  e1000_post_phy_reset_ich8lan - Perform steps required after a PHY reset
1591  *  @hw: pointer to the HW structure
1592  **/
1593 static s32 e1000_post_phy_reset_ich8lan(struct e1000_hw *hw)
1594 {
1595         s32 ret_val = 0;
1596         u16 reg;
1597
1598         if (e1000_check_reset_block(hw))
1599                 goto out;
1600
1601         /* Perform any necessary post-reset workarounds */
1602         switch (hw->mac.type) {
1603         case e1000_pchlan:
1604                 ret_val = e1000_hv_phy_workarounds_ich8lan(hw);
1605                 if (ret_val)
1606                         goto out;
1607                 break;
1608         case e1000_pch2lan:
1609                 ret_val = e1000_lv_phy_workarounds_ich8lan(hw);
1610                 if (ret_val)
1611                         goto out;
1612                 break;
1613         default:
1614                 break;
1615         }
1616
1617         /* Dummy read to clear the phy wakeup bit after lcd reset */
1618         if (hw->mac.type >= e1000_pchlan)
1619                 e1e_rphy(hw, BM_WUC, &reg);
1620
1621         /* Configure the LCD with the extended configuration region in NVM */
1622         ret_val = e1000_sw_lcd_config_ich8lan(hw);
1623         if (ret_val)
1624                 goto out;
1625
1626         /* Configure the LCD with the OEM bits in NVM */
1627         ret_val = e1000_oem_bits_config_ich8lan(hw, true);
1628
1629 out:
1630         return ret_val;
1631 }
1632
1633 /**
1634  *  e1000_phy_hw_reset_ich8lan - Performs a PHY reset
1635  *  @hw: pointer to the HW structure
1636  *
1637  *  Resets the PHY
1638  *  This is a function pointer entry point called by drivers
1639  *  or other shared routines.
1640  **/
1641 static s32 e1000_phy_hw_reset_ich8lan(struct e1000_hw *hw)
1642 {
1643         s32 ret_val = 0;
1644
1645         ret_val = e1000e_phy_hw_reset_generic(hw);
1646         if (ret_val)
1647                 goto out;
1648
1649         ret_val = e1000_post_phy_reset_ich8lan(hw);
1650
1651 out:
1652         return ret_val;
1653 }
1654
1655 /**
1656  *  e1000_set_lplu_state_pchlan - Set Low Power Link Up state
1657  *  @hw: pointer to the HW structure
1658  *  @active: true to enable LPLU, false to disable
1659  *
1660  *  Sets the LPLU state according to the active flag.  For PCH, if OEM write
1661  *  bit are disabled in the NVM, writing the LPLU bits in the MAC will not set
1662  *  the phy speed. This function will manually set the LPLU bit and restart
1663  *  auto-neg as hw would do. D3 and D0 LPLU will call the same function
1664  *  since it configures the same bit.
1665  **/
1666 static s32 e1000_set_lplu_state_pchlan(struct e1000_hw *hw, bool active)
1667 {
1668         s32 ret_val = 0;
1669         u16 oem_reg;
1670
1671         ret_val = e1e_rphy(hw, HV_OEM_BITS, &oem_reg);
1672         if (ret_val)
1673                 goto out;
1674
1675         if (active)
1676                 oem_reg |= HV_OEM_BITS_LPLU;
1677         else
1678                 oem_reg &= ~HV_OEM_BITS_LPLU;
1679
1680         oem_reg |= HV_OEM_BITS_RESTART_AN;
1681         ret_val = e1e_wphy(hw, HV_OEM_BITS, oem_reg);
1682
1683 out:
1684         return ret_val;
1685 }
1686
1687 /**
1688  *  e1000_set_d0_lplu_state_ich8lan - Set Low Power Linkup D0 state
1689  *  @hw: pointer to the HW structure
1690  *  @active: true to enable LPLU, false to disable
1691  *
1692  *  Sets the LPLU D0 state according to the active flag.  When
1693  *  activating LPLU this function also disables smart speed
1694  *  and vice versa.  LPLU will not be activated unless the
1695  *  device autonegotiation advertisement meets standards of
1696  *  either 10 or 10/100 or 10/100/1000 at all duplexes.
1697  *  This is a function pointer entry point only called by
1698  *  PHY setup routines.
1699  **/
1700 static s32 e1000_set_d0_lplu_state_ich8lan(struct e1000_hw *hw, bool active)
1701 {
1702         struct e1000_phy_info *phy = &hw->phy;
1703         u32 phy_ctrl;
1704         s32 ret_val = 0;
1705         u16 data;
1706
1707         if (phy->type == e1000_phy_ife)
1708                 return ret_val;
1709
1710         phy_ctrl = er32(PHY_CTRL);
1711
1712         if (active) {
1713                 phy_ctrl |= E1000_PHY_CTRL_D0A_LPLU;
1714                 ew32(PHY_CTRL, phy_ctrl);
1715
1716                 if (phy->type != e1000_phy_igp_3)
1717                         return 0;
1718
1719                 /*
1720                  * Call gig speed drop workaround on LPLU before accessing
1721                  * any PHY registers
1722                  */
1723                 if (hw->mac.type == e1000_ich8lan)
1724                         e1000e_gig_downshift_workaround_ich8lan(hw);
1725
1726                 /* When LPLU is enabled, we should disable SmartSpeed */
1727                 ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG, &data);
1728                 data &= ~IGP01E1000_PSCFR_SMART_SPEED;
1729                 ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG, data);
1730                 if (ret_val)
1731                         return ret_val;
1732         } else {
1733                 phy_ctrl &= ~E1000_PHY_CTRL_D0A_LPLU;
1734                 ew32(PHY_CTRL, phy_ctrl);
1735
1736                 if (phy->type != e1000_phy_igp_3)
1737                         return 0;
1738
1739                 /*
1740                  * LPLU and SmartSpeed are mutually exclusive.  LPLU is used
1741                  * during Dx states where the power conservation is most
1742                  * important.  During driver activity we should enable
1743                  * SmartSpeed, so performance is maintained.
1744                  */
1745                 if (phy->smart_speed == e1000_smart_speed_on) {
1746                         ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG,
1747                                            &data);
1748                         if (ret_val)
1749                                 return ret_val;
1750
1751                         data |= IGP01E1000_PSCFR_SMART_SPEED;
1752                         ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG,
1753                                            data);
1754                         if (ret_val)
1755                                 return ret_val;
1756                 } else if (phy->smart_speed == e1000_smart_speed_off) {
1757                         ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG,
1758                                            &data);
1759                         if (ret_val)
1760                                 return ret_val;
1761
1762                         data &= ~IGP01E1000_PSCFR_SMART_SPEED;
1763                         ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG,
1764                                            data);
1765                         if (ret_val)
1766                                 return ret_val;
1767                 }
1768         }
1769
1770         return 0;
1771 }
1772
1773 /**
1774  *  e1000_set_d3_lplu_state_ich8lan - Set Low Power Linkup D3 state
1775  *  @hw: pointer to the HW structure
1776  *  @active: true to enable LPLU, false to disable
1777  *
1778  *  Sets the LPLU D3 state according to the active flag.  When
1779  *  activating LPLU this function also disables smart speed
1780  *  and vice versa.  LPLU will not be activated unless the
1781  *  device autonegotiation advertisement meets standards of
1782  *  either 10 or 10/100 or 10/100/1000 at all duplexes.
1783  *  This is a function pointer entry point only called by
1784  *  PHY setup routines.
1785  **/
1786 static s32 e1000_set_d3_lplu_state_ich8lan(struct e1000_hw *hw, bool active)
1787 {
1788         struct e1000_phy_info *phy = &hw->phy;
1789         u32 phy_ctrl;
1790         s32 ret_val;
1791         u16 data;
1792
1793         phy_ctrl = er32(PHY_CTRL);
1794
1795         if (!active) {
1796                 phy_ctrl &= ~E1000_PHY_CTRL_NOND0A_LPLU;
1797                 ew32(PHY_CTRL, phy_ctrl);
1798
1799                 if (phy->type != e1000_phy_igp_3)
1800                         return 0;
1801
1802                 /*
1803                  * LPLU and SmartSpeed are mutually exclusive.  LPLU is used
1804                  * during Dx states where the power conservation is most
1805                  * important.  During driver activity we should enable
1806                  * SmartSpeed, so performance is maintained.
1807                  */
1808                 if (phy->smart_speed == e1000_smart_speed_on) {
1809                         ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG,
1810                                            &data);
1811                         if (ret_val)
1812                                 return ret_val;
1813
1814                         data |= IGP01E1000_PSCFR_SMART_SPEED;
1815                         ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG,
1816                                            data);
1817                         if (ret_val)
1818                                 return ret_val;
1819                 } else if (phy->smart_speed == e1000_smart_speed_off) {
1820                         ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG,
1821                                            &data);
1822                         if (ret_val)
1823                                 return ret_val;
1824
1825                         data &= ~IGP01E1000_PSCFR_SMART_SPEED;
1826                         ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG,
1827                                            data);
1828                         if (ret_val)
1829                                 return ret_val;
1830                 }
1831         } else if ((phy->autoneg_advertised == E1000_ALL_SPEED_DUPLEX) ||
1832                    (phy->autoneg_advertised == E1000_ALL_NOT_GIG) ||
1833                    (phy->autoneg_advertised == E1000_ALL_10_SPEED)) {
1834                 phy_ctrl |= E1000_PHY_CTRL_NOND0A_LPLU;
1835                 ew32(PHY_CTRL, phy_ctrl);
1836
1837                 if (phy->type != e1000_phy_igp_3)
1838                         return 0;
1839
1840                 /*
1841                  * Call gig speed drop workaround on LPLU before accessing
1842                  * any PHY registers
1843                  */
1844                 if (hw->mac.type == e1000_ich8lan)
1845                         e1000e_gig_downshift_workaround_ich8lan(hw);
1846
1847                 /* When LPLU is enabled, we should disable SmartSpeed */
1848                 ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG, &data);
1849                 if (ret_val)
1850                         return ret_val;
1851
1852                 data &= ~IGP01E1000_PSCFR_SMART_SPEED;
1853                 ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG, data);
1854         }
1855
1856         return 0;
1857 }
1858
1859 /**
1860  *  e1000_valid_nvm_bank_detect_ich8lan - finds out the valid bank 0 or 1
1861  *  @hw: pointer to the HW structure
1862  *  @bank:  pointer to the variable that returns the active bank
1863  *
1864  *  Reads signature byte from the NVM using the flash access registers.
1865  *  Word 0x13 bits 15:14 = 10b indicate a valid signature for that bank.
1866  **/
1867 static s32 e1000_valid_nvm_bank_detect_ich8lan(struct e1000_hw *hw, u32 *bank)
1868 {
1869         u32 eecd;
1870         struct e1000_nvm_info *nvm = &hw->nvm;
1871         u32 bank1_offset = nvm->flash_bank_size * sizeof(u16);
1872         u32 act_offset = E1000_ICH_NVM_SIG_WORD * 2 + 1;
1873         u8 sig_byte = 0;
1874         s32 ret_val = 0;
1875
1876         switch (hw->mac.type) {
1877         case e1000_ich8lan:
1878         case e1000_ich9lan:
1879                 eecd = er32(EECD);
1880                 if ((eecd & E1000_EECD_SEC1VAL_VALID_MASK) ==
1881                     E1000_EECD_SEC1VAL_VALID_MASK) {
1882                         if (eecd & E1000_EECD_SEC1VAL)
1883                                 *bank = 1;
1884                         else
1885                                 *bank = 0;
1886
1887                         return 0;
1888                 }
1889                 e_dbg("Unable to determine valid NVM bank via EEC - "
1890                        "reading flash signature\n");
1891                 /* fall-thru */
1892         default:
1893                 /* set bank to 0 in case flash read fails */
1894                 *bank = 0;
1895
1896                 /* Check bank 0 */
1897                 ret_val = e1000_read_flash_byte_ich8lan(hw, act_offset,
1898                                                         &sig_byte);
1899                 if (ret_val)
1900                         return ret_val;
1901                 if ((sig_byte & E1000_ICH_NVM_VALID_SIG_MASK) ==
1902                     E1000_ICH_NVM_SIG_VALUE) {
1903                         *bank = 0;
1904                         return 0;
1905                 }
1906
1907                 /* Check bank 1 */
1908                 ret_val = e1000_read_flash_byte_ich8lan(hw, act_offset +
1909                                                         bank1_offset,
1910                                                         &sig_byte);
1911                 if (ret_val)
1912                         return ret_val;
1913                 if ((sig_byte & E1000_ICH_NVM_VALID_SIG_MASK) ==
1914                     E1000_ICH_NVM_SIG_VALUE) {
1915                         *bank = 1;
1916                         return 0;
1917                 }
1918
1919                 e_dbg("ERROR: No valid NVM bank present\n");
1920                 return -E1000_ERR_NVM;
1921         }
1922
1923         return 0;
1924 }
1925
1926 /**
1927  *  e1000_read_nvm_ich8lan - Read word(s) from the NVM
1928  *  @hw: pointer to the HW structure
1929  *  @offset: The offset (in bytes) of the word(s) to read.
1930  *  @words: Size of data to read in words
1931  *  @data: Pointer to the word(s) to read at offset.
1932  *
1933  *  Reads a word(s) from the NVM using the flash access registers.
1934  **/
1935 static s32 e1000_read_nvm_ich8lan(struct e1000_hw *hw, u16 offset, u16 words,
1936                                   u16 *data)
1937 {
1938         struct e1000_nvm_info *nvm = &hw->nvm;
1939         struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
1940         u32 act_offset;
1941         s32 ret_val = 0;
1942         u32 bank = 0;
1943         u16 i, word;
1944
1945         if ((offset >= nvm->word_size) || (words > nvm->word_size - offset) ||
1946             (words == 0)) {
1947                 e_dbg("nvm parameter(s) out of bounds\n");
1948                 ret_val = -E1000_ERR_NVM;
1949                 goto out;
1950         }
1951
1952         nvm->ops.acquire(hw);
1953
1954         ret_val = e1000_valid_nvm_bank_detect_ich8lan(hw, &bank);
1955         if (ret_val) {
1956                 e_dbg("Could not detect valid bank, assuming bank 0\n");
1957                 bank = 0;
1958         }
1959
1960         act_offset = (bank) ? nvm->flash_bank_size : 0;
1961         act_offset += offset;
1962
1963         ret_val = 0;
1964         for (i = 0; i < words; i++) {
1965                 if ((dev_spec->shadow_ram) &&
1966                     (dev_spec->shadow_ram[offset+i].modified)) {
1967                         data[i] = dev_spec->shadow_ram[offset+i].value;
1968                 } else {
1969                         ret_val = e1000_read_flash_word_ich8lan(hw,
1970                                                                 act_offset + i,
1971                                                                 &word);
1972                         if (ret_val)
1973                                 break;
1974                         data[i] = word;
1975                 }
1976         }
1977
1978         nvm->ops.release(hw);
1979
1980 out:
1981         if (ret_val)
1982                 e_dbg("NVM read error: %d\n", ret_val);
1983
1984         return ret_val;
1985 }
1986
1987 /**
1988  *  e1000_flash_cycle_init_ich8lan - Initialize flash
1989  *  @hw: pointer to the HW structure
1990  *
1991  *  This function does initial flash setup so that a new read/write/erase cycle
1992  *  can be started.
1993  **/
1994 static s32 e1000_flash_cycle_init_ich8lan(struct e1000_hw *hw)
1995 {
1996         union ich8_hws_flash_status hsfsts;
1997         s32 ret_val = -E1000_ERR_NVM;
1998         s32 i = 0;
1999
2000         hsfsts.regval = er16flash(ICH_FLASH_HSFSTS);
2001
2002         /* Check if the flash descriptor is valid */
2003         if (hsfsts.hsf_status.fldesvalid == 0) {
2004                 e_dbg("Flash descriptor invalid.  "
2005                          "SW Sequencing must be used.\n");
2006                 return -E1000_ERR_NVM;
2007         }
2008
2009         /* Clear FCERR and DAEL in hw status by writing 1 */
2010         hsfsts.hsf_status.flcerr = 1;
2011         hsfsts.hsf_status.dael = 1;
2012
2013         ew16flash(ICH_FLASH_HSFSTS, hsfsts.regval);
2014
2015         /*
2016          * Either we should have a hardware SPI cycle in progress
2017          * bit to check against, in order to start a new cycle or
2018          * FDONE bit should be changed in the hardware so that it
2019          * is 1 after hardware reset, which can then be used as an
2020          * indication whether a cycle is in progress or has been
2021          * completed.
2022          */
2023
2024         if (hsfsts.hsf_status.flcinprog == 0) {
2025                 /*
2026                  * There is no cycle running at present,
2027                  * so we can start a cycle.
2028                  * Begin by setting Flash Cycle Done.
2029                  */
2030                 hsfsts.hsf_status.flcdone = 1;
2031                 ew16flash(ICH_FLASH_HSFSTS, hsfsts.regval);
2032                 ret_val = 0;
2033         } else {
2034                 /*
2035                  * Otherwise poll for sometime so the current
2036                  * cycle has a chance to end before giving up.
2037                  */
2038                 for (i = 0; i < ICH_FLASH_READ_COMMAND_TIMEOUT; i++) {
2039                         hsfsts.regval = __er16flash(hw, ICH_FLASH_HSFSTS);
2040                         if (hsfsts.hsf_status.flcinprog == 0) {
2041                                 ret_val = 0;
2042                                 break;
2043                         }
2044                         udelay(1);
2045                 }
2046                 if (ret_val == 0) {
2047                         /*
2048                          * Successful in waiting for previous cycle to timeout,
2049                          * now set the Flash Cycle Done.
2050                          */
2051                         hsfsts.hsf_status.flcdone = 1;
2052                         ew16flash(ICH_FLASH_HSFSTS, hsfsts.regval);
2053                 } else {
2054                         e_dbg("Flash controller busy, cannot get access\n");
2055                 }
2056         }
2057
2058         return ret_val;
2059 }
2060
2061 /**
2062  *  e1000_flash_cycle_ich8lan - Starts flash cycle (read/write/erase)
2063  *  @hw: pointer to the HW structure
2064  *  @timeout: maximum time to wait for completion
2065  *
2066  *  This function starts a flash cycle and waits for its completion.
2067  **/
2068 static s32 e1000_flash_cycle_ich8lan(struct e1000_hw *hw, u32 timeout)
2069 {
2070         union ich8_hws_flash_ctrl hsflctl;
2071         union ich8_hws_flash_status hsfsts;
2072         s32 ret_val = -E1000_ERR_NVM;
2073         u32 i = 0;
2074
2075         /* Start a cycle by writing 1 in Flash Cycle Go in Hw Flash Control */
2076         hsflctl.regval = er16flash(ICH_FLASH_HSFCTL);
2077         hsflctl.hsf_ctrl.flcgo = 1;
2078         ew16flash(ICH_FLASH_HSFCTL, hsflctl.regval);
2079
2080         /* wait till FDONE bit is set to 1 */
2081         do {
2082                 hsfsts.regval = er16flash(ICH_FLASH_HSFSTS);
2083                 if (hsfsts.hsf_status.flcdone == 1)
2084                         break;
2085                 udelay(1);
2086         } while (i++ < timeout);
2087
2088         if (hsfsts.hsf_status.flcdone == 1 && hsfsts.hsf_status.flcerr == 0)
2089                 return 0;
2090
2091         return ret_val;
2092 }
2093
2094 /**
2095  *  e1000_read_flash_word_ich8lan - Read word from flash
2096  *  @hw: pointer to the HW structure
2097  *  @offset: offset to data location
2098  *  @data: pointer to the location for storing the data
2099  *
2100  *  Reads the flash word at offset into data.  Offset is converted
2101  *  to bytes before read.
2102  **/
2103 static s32 e1000_read_flash_word_ich8lan(struct e1000_hw *hw, u32 offset,
2104                                          u16 *data)
2105 {
2106         /* Must convert offset into bytes. */
2107         offset <<= 1;
2108
2109         return e1000_read_flash_data_ich8lan(hw, offset, 2, data);
2110 }
2111
2112 /**
2113  *  e1000_read_flash_byte_ich8lan - Read byte from flash
2114  *  @hw: pointer to the HW structure
2115  *  @offset: The offset of the byte to read.
2116  *  @data: Pointer to a byte to store the value read.
2117  *
2118  *  Reads a single byte from the NVM using the flash access registers.
2119  **/
2120 static s32 e1000_read_flash_byte_ich8lan(struct e1000_hw *hw, u32 offset,
2121                                          u8 *data)
2122 {
2123         s32 ret_val;
2124         u16 word = 0;
2125
2126         ret_val = e1000_read_flash_data_ich8lan(hw, offset, 1, &word);
2127         if (ret_val)
2128                 return ret_val;
2129
2130         *data = (u8)word;
2131
2132         return 0;
2133 }
2134
2135 /**
2136  *  e1000_read_flash_data_ich8lan - Read byte or word from NVM
2137  *  @hw: pointer to the HW structure
2138  *  @offset: The offset (in bytes) of the byte or word to read.
2139  *  @size: Size of data to read, 1=byte 2=word
2140  *  @data: Pointer to the word to store the value read.
2141  *
2142  *  Reads a byte or word from the NVM using the flash access registers.
2143  **/
2144 static s32 e1000_read_flash_data_ich8lan(struct e1000_hw *hw, u32 offset,
2145                                          u8 size, u16 *data)
2146 {
2147         union ich8_hws_flash_status hsfsts;
2148         union ich8_hws_flash_ctrl hsflctl;
2149         u32 flash_linear_addr;
2150         u32 flash_data = 0;
2151         s32 ret_val = -E1000_ERR_NVM;
2152         u8 count = 0;
2153
2154         if (size < 1  || size > 2 || offset > ICH_FLASH_LINEAR_ADDR_MASK)
2155                 return -E1000_ERR_NVM;
2156
2157         flash_linear_addr = (ICH_FLASH_LINEAR_ADDR_MASK & offset) +
2158                             hw->nvm.flash_base_addr;
2159
2160         do {
2161                 udelay(1);
2162                 /* Steps */
2163                 ret_val = e1000_flash_cycle_init_ich8lan(hw);
2164                 if (ret_val != 0)
2165                         break;
2166
2167                 hsflctl.regval = er16flash(ICH_FLASH_HSFCTL);
2168                 /* 0b/1b corresponds to 1 or 2 byte size, respectively. */
2169                 hsflctl.hsf_ctrl.fldbcount = size - 1;
2170                 hsflctl.hsf_ctrl.flcycle = ICH_CYCLE_READ;
2171                 ew16flash(ICH_FLASH_HSFCTL, hsflctl.regval);
2172
2173                 ew32flash(ICH_FLASH_FADDR, flash_linear_addr);
2174
2175                 ret_val = e1000_flash_cycle_ich8lan(hw,
2176                                                 ICH_FLASH_READ_COMMAND_TIMEOUT);
2177
2178                 /*
2179                  * Check if FCERR is set to 1, if set to 1, clear it
2180                  * and try the whole sequence a few more times, else
2181                  * read in (shift in) the Flash Data0, the order is
2182                  * least significant byte first msb to lsb
2183                  */
2184                 if (ret_val == 0) {
2185                         flash_data = er32flash(ICH_FLASH_FDATA0);
2186                         if (size == 1) {
2187                                 *data = (u8)(flash_data & 0x000000FF);
2188                         } else if (size == 2) {
2189                                 *data = (u16)(flash_data & 0x0000FFFF);
2190                         }
2191                         break;
2192                 } else {
2193                         /*
2194                          * If we've gotten here, then things are probably
2195                          * completely hosed, but if the error condition is
2196                          * detected, it won't hurt to give it another try...
2197                          * ICH_FLASH_CYCLE_REPEAT_COUNT times.
2198                          */
2199                         hsfsts.regval = er16flash(ICH_FLASH_HSFSTS);
2200                         if (hsfsts.hsf_status.flcerr == 1) {
2201                                 /* Repeat for some time before giving up. */
2202                                 continue;
2203                         } else if (hsfsts.hsf_status.flcdone == 0) {
2204                                 e_dbg("Timeout error - flash cycle "
2205                                          "did not complete.\n");
2206                                 break;
2207                         }
2208                 }
2209         } while (count++ < ICH_FLASH_CYCLE_REPEAT_COUNT);
2210
2211         return ret_val;
2212 }
2213
2214 /**
2215  *  e1000_write_nvm_ich8lan - Write word(s) to the NVM
2216  *  @hw: pointer to the HW structure
2217  *  @offset: The offset (in bytes) of the word(s) to write.
2218  *  @words: Size of data to write in words
2219  *  @data: Pointer to the word(s) to write at offset.
2220  *
2221  *  Writes a byte or word to the NVM using the flash access registers.
2222  **/
2223 static s32 e1000_write_nvm_ich8lan(struct e1000_hw *hw, u16 offset, u16 words,
2224                                    u16 *data)
2225 {
2226         struct e1000_nvm_info *nvm = &hw->nvm;
2227         struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
2228         u16 i;
2229
2230         if ((offset >= nvm->word_size) || (words > nvm->word_size - offset) ||
2231             (words == 0)) {
2232                 e_dbg("nvm parameter(s) out of bounds\n");
2233                 return -E1000_ERR_NVM;
2234         }
2235
2236         nvm->ops.acquire(hw);
2237
2238         for (i = 0; i < words; i++) {
2239                 dev_spec->shadow_ram[offset+i].modified = true;
2240                 dev_spec->shadow_ram[offset+i].value = data[i];
2241         }
2242
2243         nvm->ops.release(hw);
2244
2245         return 0;
2246 }
2247
2248 /**
2249  *  e1000_update_nvm_checksum_ich8lan - Update the checksum for NVM
2250  *  @hw: pointer to the HW structure
2251  *
2252  *  The NVM checksum is updated by calling the generic update_nvm_checksum,
2253  *  which writes the checksum to the shadow ram.  The changes in the shadow
2254  *  ram are then committed to the EEPROM by processing each bank at a time
2255  *  checking for the modified bit and writing only the pending changes.
2256  *  After a successful commit, the shadow ram is cleared and is ready for
2257  *  future writes.
2258  **/
2259 static s32 e1000_update_nvm_checksum_ich8lan(struct e1000_hw *hw)
2260 {
2261         struct e1000_nvm_info *nvm = &hw->nvm;
2262         struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
2263         u32 i, act_offset, new_bank_offset, old_bank_offset, bank;
2264         s32 ret_val;
2265         u16 data;
2266
2267         ret_val = e1000e_update_nvm_checksum_generic(hw);
2268         if (ret_val)
2269                 goto out;
2270
2271         if (nvm->type != e1000_nvm_flash_sw)
2272                 goto out;
2273
2274         nvm->ops.acquire(hw);
2275
2276         /*
2277          * We're writing to the opposite bank so if we're on bank 1,
2278          * write to bank 0 etc.  We also need to erase the segment that
2279          * is going to be written
2280          */
2281         ret_val =  e1000_valid_nvm_bank_detect_ich8lan(hw, &bank);
2282         if (ret_val) {
2283                 e_dbg("Could not detect valid bank, assuming bank 0\n");
2284                 bank = 0;
2285         }
2286
2287         if (bank == 0) {
2288                 new_bank_offset = nvm->flash_bank_size;
2289                 old_bank_offset = 0;
2290                 ret_val = e1000_erase_flash_bank_ich8lan(hw, 1);
2291                 if (ret_val)
2292                         goto release;
2293         } else {
2294                 old_bank_offset = nvm->flash_bank_size;
2295                 new_bank_offset = 0;
2296                 ret_val = e1000_erase_flash_bank_ich8lan(hw, 0);
2297                 if (ret_val)
2298                         goto release;
2299         }
2300
2301         for (i = 0; i < E1000_ICH8_SHADOW_RAM_WORDS; i++) {
2302                 /*
2303                  * Determine whether to write the value stored
2304                  * in the other NVM bank or a modified value stored
2305                  * in the shadow RAM
2306                  */
2307                 if (dev_spec->shadow_ram[i].modified) {
2308                         data = dev_spec->shadow_ram[i].value;
2309                 } else {
2310                         ret_val = e1000_read_flash_word_ich8lan(hw, i +
2311                                                                 old_bank_offset,
2312                                                                 &data);
2313                         if (ret_val)
2314                                 break;
2315                 }
2316
2317                 /*
2318                  * If the word is 0x13, then make sure the signature bits
2319                  * (15:14) are 11b until the commit has completed.
2320                  * This will allow us to write 10b which indicates the
2321                  * signature is valid.  We want to do this after the write
2322                  * has completed so that we don't mark the segment valid
2323                  * while the write is still in progress
2324                  */
2325                 if (i == E1000_ICH_NVM_SIG_WORD)
2326                         data |= E1000_ICH_NVM_SIG_MASK;
2327
2328                 /* Convert offset to bytes. */
2329                 act_offset = (i + new_bank_offset) << 1;
2330
2331                 udelay(100);
2332                 /* Write the bytes to the new bank. */
2333                 ret_val = e1000_retry_write_flash_byte_ich8lan(hw,
2334                                                                act_offset,
2335                                                                (u8)data);
2336                 if (ret_val)
2337                         break;
2338
2339                 udelay(100);
2340                 ret_val = e1000_retry_write_flash_byte_ich8lan(hw,
2341                                                           act_offset + 1,
2342                                                           (u8)(data >> 8));
2343                 if (ret_val)
2344                         break;
2345         }
2346
2347         /*
2348          * Don't bother writing the segment valid bits if sector
2349          * programming failed.
2350          */
2351         if (ret_val) {
2352                 /* Possibly read-only, see e1000e_write_protect_nvm_ich8lan() */
2353                 e_dbg("Flash commit failed.\n");
2354                 goto release;
2355         }
2356
2357         /*
2358          * Finally validate the new segment by setting bit 15:14
2359          * to 10b in word 0x13 , this can be done without an
2360          * erase as well since these bits are 11 to start with
2361          * and we need to change bit 14 to 0b
2362          */
2363         act_offset = new_bank_offset + E1000_ICH_NVM_SIG_WORD;
2364         ret_val = e1000_read_flash_word_ich8lan(hw, act_offset, &data);
2365         if (ret_val)
2366                 goto release;
2367
2368         data &= 0xBFFF;
2369         ret_val = e1000_retry_write_flash_byte_ich8lan(hw,
2370                                                        act_offset * 2 + 1,
2371                                                        (u8)(data >> 8));
2372         if (ret_val)
2373                 goto release;
2374
2375         /*
2376          * And invalidate the previously valid segment by setting
2377          * its signature word (0x13) high_byte to 0b. This can be
2378          * done without an erase because flash erase sets all bits
2379          * to 1's. We can write 1's to 0's without an erase
2380          */
2381         act_offset = (old_bank_offset + E1000_ICH_NVM_SIG_WORD) * 2 + 1;
2382         ret_val = e1000_retry_write_flash_byte_ich8lan(hw, act_offset, 0);
2383         if (ret_val)
2384                 goto release;
2385
2386         /* Great!  Everything worked, we can now clear the cached entries. */
2387         for (i = 0; i < E1000_ICH8_SHADOW_RAM_WORDS; i++) {
2388                 dev_spec->shadow_ram[i].modified = false;
2389                 dev_spec->shadow_ram[i].value = 0xFFFF;
2390         }
2391
2392 release:
2393         nvm->ops.release(hw);
2394
2395         /*
2396          * Reload the EEPROM, or else modifications will not appear
2397          * until after the next adapter reset.
2398          */
2399         if (!ret_val) {
2400                 e1000e_reload_nvm(hw);
2401                 msleep(10);
2402         }
2403
2404 out:
2405         if (ret_val)
2406                 e_dbg("NVM update error: %d\n", ret_val);
2407
2408         return ret_val;
2409 }
2410
2411 /**
2412  *  e1000_validate_nvm_checksum_ich8lan - Validate EEPROM checksum
2413  *  @hw: pointer to the HW structure
2414  *
2415  *  Check to see if checksum needs to be fixed by reading bit 6 in word 0x19.
2416  *  If the bit is 0, that the EEPROM had been modified, but the checksum was not
2417  *  calculated, in which case we need to calculate the checksum and set bit 6.
2418  **/
2419 static s32 e1000_validate_nvm_checksum_ich8lan(struct e1000_hw *hw)
2420 {
2421         s32 ret_val;
2422         u16 data;
2423
2424         /*
2425          * Read 0x19 and check bit 6.  If this bit is 0, the checksum
2426          * needs to be fixed.  This bit is an indication that the NVM
2427          * was prepared by OEM software and did not calculate the
2428          * checksum...a likely scenario.
2429          */
2430         ret_val = e1000_read_nvm(hw, 0x19, 1, &data);
2431         if (ret_val)
2432                 return ret_val;
2433
2434         if ((data & 0x40) == 0) {
2435                 data |= 0x40;
2436                 ret_val = e1000_write_nvm(hw, 0x19, 1, &data);
2437                 if (ret_val)
2438                         return ret_val;
2439                 ret_val = e1000e_update_nvm_checksum(hw);
2440                 if (ret_val)
2441                         return ret_val;
2442         }
2443
2444         return e1000e_validate_nvm_checksum_generic(hw);
2445 }
2446
2447 /**
2448  *  e1000e_write_protect_nvm_ich8lan - Make the NVM read-only
2449  *  @hw: pointer to the HW structure
2450  *
2451  *  To prevent malicious write/erase of the NVM, set it to be read-only
2452  *  so that the hardware ignores all write/erase cycles of the NVM via
2453  *  the flash control registers.  The shadow-ram copy of the NVM will
2454  *  still be updated, however any updates to this copy will not stick
2455  *  across driver reloads.
2456  **/
2457 void e1000e_write_protect_nvm_ich8lan(struct e1000_hw *hw)
2458 {
2459         struct e1000_nvm_info *nvm = &hw->nvm;
2460         union ich8_flash_protected_range pr0;
2461         union ich8_hws_flash_status hsfsts;
2462         u32 gfpreg;
2463
2464         nvm->ops.acquire(hw);
2465
2466         gfpreg = er32flash(ICH_FLASH_GFPREG);
2467
2468         /* Write-protect GbE Sector of NVM */
2469         pr0.regval = er32flash(ICH_FLASH_PR0);
2470         pr0.range.base = gfpreg & FLASH_GFPREG_BASE_MASK;
2471         pr0.range.limit = ((gfpreg >> 16) & FLASH_GFPREG_BASE_MASK);
2472         pr0.range.wpe = true;
2473         ew32flash(ICH_FLASH_PR0, pr0.regval);
2474
2475         /*
2476          * Lock down a subset of GbE Flash Control Registers, e.g.
2477          * PR0 to prevent the write-protection from being lifted.
2478          * Once FLOCKDN is set, the registers protected by it cannot
2479          * be written until FLOCKDN is cleared by a hardware reset.
2480          */
2481         hsfsts.regval = er16flash(ICH_FLASH_HSFSTS);
2482         hsfsts.hsf_status.flockdn = true;
2483         ew32flash(ICH_FLASH_HSFSTS, hsfsts.regval);
2484
2485         nvm->ops.release(hw);
2486 }
2487
2488 /**
2489  *  e1000_write_flash_data_ich8lan - Writes bytes to the NVM
2490  *  @hw: pointer to the HW structure
2491  *  @offset: The offset (in bytes) of the byte/word to read.
2492  *  @size: Size of data to read, 1=byte 2=word
2493  *  @data: The byte(s) to write to the NVM.
2494  *
2495  *  Writes one/two bytes to the NVM using the flash access registers.
2496  **/
2497 static s32 e1000_write_flash_data_ich8lan(struct e1000_hw *hw, u32 offset,
2498                                           u8 size, u16 data)
2499 {
2500         union ich8_hws_flash_status hsfsts;
2501         union ich8_hws_flash_ctrl hsflctl;
2502         u32 flash_linear_addr;
2503         u32 flash_data = 0;
2504         s32 ret_val;
2505         u8 count = 0;
2506
2507         if (size < 1 || size > 2 || data > size * 0xff ||
2508             offset > ICH_FLASH_LINEAR_ADDR_MASK)
2509                 return -E1000_ERR_NVM;
2510
2511         flash_linear_addr = (ICH_FLASH_LINEAR_ADDR_MASK & offset) +
2512                             hw->nvm.flash_base_addr;
2513
2514         do {
2515                 udelay(1);
2516                 /* Steps */
2517                 ret_val = e1000_flash_cycle_init_ich8lan(hw);
2518                 if (ret_val)
2519                         break;
2520
2521                 hsflctl.regval = er16flash(ICH_FLASH_HSFCTL);
2522                 /* 0b/1b corresponds to 1 or 2 byte size, respectively. */
2523                 hsflctl.hsf_ctrl.fldbcount = size -1;
2524                 hsflctl.hsf_ctrl.flcycle = ICH_CYCLE_WRITE;
2525                 ew16flash(ICH_FLASH_HSFCTL, hsflctl.regval);
2526
2527                 ew32flash(ICH_FLASH_FADDR, flash_linear_addr);
2528
2529                 if (size == 1)
2530                         flash_data = (u32)data & 0x00FF;
2531                 else
2532                         flash_data = (u32)data;
2533
2534                 ew32flash(ICH_FLASH_FDATA0, flash_data);
2535
2536                 /*
2537                  * check if FCERR is set to 1 , if set to 1, clear it
2538                  * and try the whole sequence a few more times else done
2539                  */
2540                 ret_val = e1000_flash_cycle_ich8lan(hw,
2541                                                ICH_FLASH_WRITE_COMMAND_TIMEOUT);
2542                 if (!ret_val)
2543                         break;
2544
2545                 /*
2546                  * If we're here, then things are most likely
2547                  * completely hosed, but if the error condition
2548                  * is detected, it won't hurt to give it another
2549                  * try...ICH_FLASH_CYCLE_REPEAT_COUNT times.
2550                  */
2551                 hsfsts.regval = er16flash(ICH_FLASH_HSFSTS);
2552                 if (hsfsts.hsf_status.flcerr == 1)
2553                         /* Repeat for some time before giving up. */
2554                         continue;
2555                 if (hsfsts.hsf_status.flcdone == 0) {
2556                         e_dbg("Timeout error - flash cycle "
2557                                  "did not complete.");
2558                         break;
2559                 }
2560         } while (count++ < ICH_FLASH_CYCLE_REPEAT_COUNT);
2561
2562         return ret_val;
2563 }
2564
2565 /**
2566  *  e1000_write_flash_byte_ich8lan - Write a single byte to NVM
2567  *  @hw: pointer to the HW structure
2568  *  @offset: The index of the byte to read.
2569  *  @data: The byte to write to the NVM.
2570  *
2571  *  Writes a single byte to the NVM using the flash access registers.
2572  **/
2573 static s32 e1000_write_flash_byte_ich8lan(struct e1000_hw *hw, u32 offset,
2574                                           u8 data)
2575 {
2576         u16 word = (u16)data;
2577
2578         return e1000_write_flash_data_ich8lan(hw, offset, 1, word);
2579 }
2580
2581 /**
2582  *  e1000_retry_write_flash_byte_ich8lan - Writes a single byte to NVM
2583  *  @hw: pointer to the HW structure
2584  *  @offset: The offset of the byte to write.
2585  *  @byte: The byte to write to the NVM.
2586  *
2587  *  Writes a single byte to the NVM using the flash access registers.
2588  *  Goes through a retry algorithm before giving up.
2589  **/
2590 static s32 e1000_retry_write_flash_byte_ich8lan(struct e1000_hw *hw,
2591                                                 u32 offset, u8 byte)
2592 {
2593         s32 ret_val;
2594         u16 program_retries;
2595
2596         ret_val = e1000_write_flash_byte_ich8lan(hw, offset, byte);
2597         if (!ret_val)
2598                 return ret_val;
2599
2600         for (program_retries = 0; program_retries < 100; program_retries++) {
2601                 e_dbg("Retrying Byte %2.2X at offset %u\n", byte, offset);
2602                 udelay(100);
2603                 ret_val = e1000_write_flash_byte_ich8lan(hw, offset, byte);
2604                 if (!ret_val)
2605                         break;
2606         }
2607         if (program_retries == 100)
2608                 return -E1000_ERR_NVM;
2609
2610         return 0;
2611 }
2612
2613 /**
2614  *  e1000_erase_flash_bank_ich8lan - Erase a bank (4k) from NVM
2615  *  @hw: pointer to the HW structure
2616  *  @bank: 0 for first bank, 1 for second bank, etc.
2617  *
2618  *  Erases the bank specified. Each bank is a 4k block. Banks are 0 based.
2619  *  bank N is 4096 * N + flash_reg_addr.
2620  **/
2621 static s32 e1000_erase_flash_bank_ich8lan(struct e1000_hw *hw, u32 bank)
2622 {
2623         struct e1000_nvm_info *nvm = &hw->nvm;
2624         union ich8_hws_flash_status hsfsts;
2625         union ich8_hws_flash_ctrl hsflctl;
2626         u32 flash_linear_addr;
2627         /* bank size is in 16bit words - adjust to bytes */
2628         u32 flash_bank_size = nvm->flash_bank_size * 2;
2629         s32 ret_val;
2630         s32 count = 0;
2631         s32 j, iteration, sector_size;
2632
2633         hsfsts.regval = er16flash(ICH_FLASH_HSFSTS);
2634
2635         /*
2636          * Determine HW Sector size: Read BERASE bits of hw flash status
2637          * register
2638          * 00: The Hw sector is 256 bytes, hence we need to erase 16
2639          *     consecutive sectors.  The start index for the nth Hw sector
2640          *     can be calculated as = bank * 4096 + n * 256
2641          * 01: The Hw sector is 4K bytes, hence we need to erase 1 sector.
2642          *     The start index for the nth Hw sector can be calculated
2643          *     as = bank * 4096
2644          * 10: The Hw sector is 8K bytes, nth sector = bank * 8192
2645          *     (ich9 only, otherwise error condition)
2646          * 11: The Hw sector is 64K bytes, nth sector = bank * 65536
2647          */
2648         switch (hsfsts.hsf_status.berasesz) {
2649         case 0:
2650                 /* Hw sector size 256 */
2651                 sector_size = ICH_FLASH_SEG_SIZE_256;
2652                 iteration = flash_bank_size / ICH_FLASH_SEG_SIZE_256;
2653                 break;
2654         case 1:
2655                 sector_size = ICH_FLASH_SEG_SIZE_4K;
2656                 iteration = 1;
2657                 break;
2658         case 2:
2659                 sector_size = ICH_FLASH_SEG_SIZE_8K;
2660                 iteration = 1;
2661                 break;
2662         case 3:
2663                 sector_size = ICH_FLASH_SEG_SIZE_64K;
2664                 iteration = 1;
2665                 break;
2666         default:
2667                 return -E1000_ERR_NVM;
2668         }
2669
2670         /* Start with the base address, then add the sector offset. */
2671         flash_linear_addr = hw->nvm.flash_base_addr;
2672         flash_linear_addr += (bank) ? flash_bank_size : 0;
2673
2674         for (j = 0; j < iteration ; j++) {
2675                 do {
2676                         /* Steps */
2677                         ret_val = e1000_flash_cycle_init_ich8lan(hw);
2678                         if (ret_val)
2679                                 return ret_val;
2680
2681                         /*
2682                          * Write a value 11 (block Erase) in Flash
2683                          * Cycle field in hw flash control
2684                          */
2685                         hsflctl.regval = er16flash(ICH_FLASH_HSFCTL);
2686                         hsflctl.hsf_ctrl.flcycle = ICH_CYCLE_ERASE;
2687                         ew16flash(ICH_FLASH_HSFCTL, hsflctl.regval);
2688
2689                         /*
2690                          * Write the last 24 bits of an index within the
2691                          * block into Flash Linear address field in Flash
2692                          * Address.
2693                          */
2694                         flash_linear_addr += (j * sector_size);
2695                         ew32flash(ICH_FLASH_FADDR, flash_linear_addr);
2696
2697                         ret_val = e1000_flash_cycle_ich8lan(hw,
2698                                                ICH_FLASH_ERASE_COMMAND_TIMEOUT);
2699                         if (ret_val == 0)
2700                                 break;
2701
2702                         /*
2703                          * Check if FCERR is set to 1.  If 1,
2704                          * clear it and try the whole sequence
2705                          * a few more times else Done
2706                          */
2707                         hsfsts.regval = er16flash(ICH_FLASH_HSFSTS);
2708                         if (hsfsts.hsf_status.flcerr == 1)
2709                                 /* repeat for some time before giving up */
2710                                 continue;
2711                         else if (hsfsts.hsf_status.flcdone == 0)
2712                                 return ret_val;
2713                 } while (++count < ICH_FLASH_CYCLE_REPEAT_COUNT);
2714         }
2715
2716         return 0;
2717 }
2718
2719 /**
2720  *  e1000_valid_led_default_ich8lan - Set the default LED settings
2721  *  @hw: pointer to the HW structure
2722  *  @data: Pointer to the LED settings
2723  *
2724  *  Reads the LED default settings from the NVM to data.  If the NVM LED
2725  *  settings is all 0's or F's, set the LED default to a valid LED default
2726  *  setting.
2727  **/
2728 static s32 e1000_valid_led_default_ich8lan(struct e1000_hw *hw, u16 *data)
2729 {
2730         s32 ret_val;
2731
2732         ret_val = e1000_read_nvm(hw, NVM_ID_LED_SETTINGS, 1, data);
2733         if (ret_val) {
2734                 e_dbg("NVM Read Error\n");
2735                 return ret_val;
2736         }
2737
2738         if (*data == ID_LED_RESERVED_0000 ||
2739             *data == ID_LED_RESERVED_FFFF)
2740                 *data = ID_LED_DEFAULT_ICH8LAN;
2741
2742         return 0;
2743 }
2744
2745 /**
2746  *  e1000_id_led_init_pchlan - store LED configurations
2747  *  @hw: pointer to the HW structure
2748  *
2749  *  PCH does not control LEDs via the LEDCTL register, rather it uses
2750  *  the PHY LED configuration register.
2751  *
2752  *  PCH also does not have an "always on" or "always off" mode which
2753  *  complicates the ID feature.  Instead of using the "on" mode to indicate
2754  *  in ledctl_mode2 the LEDs to use for ID (see e1000e_id_led_init()),
2755  *  use "link_up" mode.  The LEDs will still ID on request if there is no
2756  *  link based on logic in e1000_led_[on|off]_pchlan().
2757  **/
2758 static s32 e1000_id_led_init_pchlan(struct e1000_hw *hw)
2759 {
2760         struct e1000_mac_info *mac = &hw->mac;
2761         s32 ret_val;
2762         const u32 ledctl_on = E1000_LEDCTL_MODE_LINK_UP;
2763         const u32 ledctl_off = E1000_LEDCTL_MODE_LINK_UP | E1000_PHY_LED0_IVRT;
2764         u16 data, i, temp, shift;
2765
2766         /* Get default ID LED modes */
2767         ret_val = hw->nvm.ops.valid_led_default(hw, &data);
2768         if (ret_val)
2769                 goto out;
2770
2771         mac->ledctl_default = er32(LEDCTL);
2772         mac->ledctl_mode1 = mac->ledctl_default;
2773         mac->ledctl_mode2 = mac->ledctl_default;
2774
2775         for (i = 0; i < 4; i++) {
2776                 temp = (data >> (i << 2)) & E1000_LEDCTL_LED0_MODE_MASK;
2777                 shift = (i * 5);
2778                 switch (temp) {
2779                 case ID_LED_ON1_DEF2:
2780                 case ID_LED_ON1_ON2:
2781                 case ID_LED_ON1_OFF2:
2782                         mac->ledctl_mode1 &= ~(E1000_PHY_LED0_MASK << shift);
2783                         mac->ledctl_mode1 |= (ledctl_on << shift);
2784                         break;
2785                 case ID_LED_OFF1_DEF2:
2786                 case ID_LED_OFF1_ON2:
2787                 case ID_LED_OFF1_OFF2:
2788                         mac->ledctl_mode1 &= ~(E1000_PHY_LED0_MASK << shift);
2789                         mac->ledctl_mode1 |= (ledctl_off << shift);
2790                         break;
2791                 default:
2792                         /* Do nothing */
2793                         break;
2794                 }
2795                 switch (temp) {
2796                 case ID_LED_DEF1_ON2:
2797                 case ID_LED_ON1_ON2:
2798                 case ID_LED_OFF1_ON2:
2799                         mac->ledctl_mode2 &= ~(E1000_PHY_LED0_MASK << shift);
2800                         mac->ledctl_mode2 |= (ledctl_on << shift);
2801                         break;
2802                 case ID_LED_DEF1_OFF2:
2803                 case ID_LED_ON1_OFF2:
2804                 case ID_LED_OFF1_OFF2:
2805                         mac->ledctl_mode2 &= ~(E1000_PHY_LED0_MASK << shift);
2806                         mac->ledctl_mode2 |= (ledctl_off << shift);
2807                         break;
2808                 default:
2809                         /* Do nothing */
2810                         break;
2811                 }
2812         }
2813
2814 out:
2815         return ret_val;
2816 }
2817
2818 /**
2819  *  e1000_get_bus_info_ich8lan - Get/Set the bus type and width
2820  *  @hw: pointer to the HW structure
2821  *
2822  *  ICH8 use the PCI Express bus, but does not contain a PCI Express Capability
2823  *  register, so the the bus width is hard coded.
2824  **/
2825 static s32 e1000_get_bus_info_ich8lan(struct e1000_hw *hw)
2826 {
2827         struct e1000_bus_info *bus = &hw->bus;
2828         s32 ret_val;
2829
2830         ret_val = e1000e_get_bus_info_pcie(hw);
2831
2832         /*
2833          * ICH devices are "PCI Express"-ish.  They have
2834          * a configuration space, but do not contain
2835          * PCI Express Capability registers, so bus width
2836          * must be hardcoded.
2837          */
2838         if (bus->width == e1000_bus_width_unknown)
2839                 bus->width = e1000_bus_width_pcie_x1;
2840
2841         return ret_val;
2842 }
2843
2844 /**
2845  *  e1000_reset_hw_ich8lan - Reset the hardware
2846  *  @hw: pointer to the HW structure
2847  *
2848  *  Does a full reset of the hardware which includes a reset of the PHY and
2849  *  MAC.
2850  **/
2851 static s32 e1000_reset_hw_ich8lan(struct e1000_hw *hw)
2852 {
2853         struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
2854         u16 reg;
2855         u32 ctrl, icr, kab;
2856         s32 ret_val;
2857
2858         /*
2859          * Prevent the PCI-E bus from sticking if there is no TLP connection
2860          * on the last TLP read/write transaction when MAC is reset.
2861          */
2862         ret_val = e1000e_disable_pcie_master(hw);
2863         if (ret_val)
2864                 e_dbg("PCI-E Master disable polling has failed.\n");
2865
2866         e_dbg("Masking off all interrupts\n");
2867         ew32(IMC, 0xffffffff);
2868
2869         /*
2870          * Disable the Transmit and Receive units.  Then delay to allow
2871          * any pending transactions to complete before we hit the MAC
2872          * with the global reset.
2873          */
2874         ew32(RCTL, 0);
2875         ew32(TCTL, E1000_TCTL_PSP);
2876         e1e_flush();
2877
2878         msleep(10);
2879
2880         /* Workaround for ICH8 bit corruption issue in FIFO memory */
2881         if (hw->mac.type == e1000_ich8lan) {
2882                 /* Set Tx and Rx buffer allocation to 8k apiece. */
2883                 ew32(PBA, E1000_PBA_8K);
2884                 /* Set Packet Buffer Size to 16k. */
2885                 ew32(PBS, E1000_PBS_16K);
2886         }
2887
2888         if (hw->mac.type == e1000_pchlan) {
2889                 /* Save the NVM K1 bit setting*/
2890                 ret_val = e1000_read_nvm(hw, E1000_NVM_K1_CONFIG, 1, &reg);
2891                 if (ret_val)
2892                         return ret_val;
2893
2894                 if (reg & E1000_NVM_K1_ENABLE)
2895                         dev_spec->nvm_k1_enabled = true;
2896                 else
2897                         dev_spec->nvm_k1_enabled = false;
2898         }
2899
2900         ctrl = er32(CTRL);
2901
2902         if (!e1000_check_reset_block(hw)) {
2903                 /*
2904                  * Full-chip reset requires MAC and PHY reset at the same
2905                  * time to make sure the interface between MAC and the
2906                  * external PHY is reset.
2907                  */
2908                 ctrl |= E1000_CTRL_PHY_RST;
2909         }
2910         ret_val = e1000_acquire_swflag_ich8lan(hw);
2911         e_dbg("Issuing a global reset to ich8lan\n");
2912         ew32(CTRL, (ctrl | E1000_CTRL_RST));
2913         msleep(20);
2914
2915         if (!ret_val)
2916                 e1000_release_swflag_ich8lan(hw);
2917
2918         if (ctrl & E1000_CTRL_PHY_RST) {
2919                 ret_val = hw->phy.ops.get_cfg_done(hw);
2920                 if (ret_val)
2921                         goto out;
2922
2923                 ret_val = e1000_post_phy_reset_ich8lan(hw);
2924                 if (ret_val)
2925                         goto out;
2926         }
2927
2928         /*
2929          * For PCH, this write will make sure that any noise
2930          * will be detected as a CRC error and be dropped rather than show up
2931          * as a bad packet to the DMA engine.
2932          */
2933         if (hw->mac.type == e1000_pchlan)
2934                 ew32(CRC_OFFSET, 0x65656565);
2935
2936         ew32(IMC, 0xffffffff);
2937         icr = er32(ICR);
2938
2939         kab = er32(KABGTXD);
2940         kab |= E1000_KABGTXD_BGSQLBIAS;
2941         ew32(KABGTXD, kab);
2942
2943 out:
2944         return ret_val;
2945 }
2946
2947 /**
2948  *  e1000_init_hw_ich8lan - Initialize the hardware
2949  *  @hw: pointer to the HW structure
2950  *
2951  *  Prepares the hardware for transmit and receive by doing the following:
2952  *   - initialize hardware bits
2953  *   - initialize LED identification
2954  *   - setup receive address registers
2955  *   - setup flow control
2956  *   - setup transmit descriptors
2957  *   - clear statistics
2958  **/
2959 static s32 e1000_init_hw_ich8lan(struct e1000_hw *hw)
2960 {
2961         struct e1000_mac_info *mac = &hw->mac;
2962         u32 ctrl_ext, txdctl, snoop;
2963         s32 ret_val;
2964         u16 i;
2965
2966         e1000_initialize_hw_bits_ich8lan(hw);
2967
2968         /* Initialize identification LED */
2969         ret_val = mac->ops.id_led_init(hw);
2970         if (ret_val)
2971                 e_dbg("Error initializing identification LED\n");
2972                 /* This is not fatal and we should not stop init due to this */
2973
2974         /* Setup the receive address. */
2975         e1000e_init_rx_addrs(hw, mac->rar_entry_count);
2976
2977         /* Zero out the Multicast HASH table */
2978         e_dbg("Zeroing the MTA\n");
2979         for (i = 0; i < mac->mta_reg_count; i++)
2980                 E1000_WRITE_REG_ARRAY(hw, E1000_MTA, i, 0);
2981
2982         /*
2983          * The 82578 Rx buffer will stall if wakeup is enabled in host and
2984          * the ME.  Reading the BM_WUC register will clear the host wakeup bit.
2985          * Reset the phy after disabling host wakeup to reset the Rx buffer.
2986          */
2987         if (hw->phy.type == e1000_phy_82578) {
2988                 hw->phy.ops.read_reg(hw, BM_WUC, &i);
2989                 ret_val = e1000_phy_hw_reset_ich8lan(hw);
2990                 if (ret_val)
2991                         return ret_val;
2992         }
2993
2994         /* Setup link and flow control */
2995         ret_val = e1000_setup_link_ich8lan(hw);
2996
2997         /* Set the transmit descriptor write-back policy for both queues */
2998         txdctl = er32(TXDCTL(0));
2999         txdctl = (txdctl & ~E1000_TXDCTL_WTHRESH) |
3000                  E1000_TXDCTL_FULL_TX_DESC_WB;
3001         txdctl = (txdctl & ~E1000_TXDCTL_PTHRESH) |
3002                  E1000_TXDCTL_MAX_TX_DESC_PREFETCH;
3003         ew32(TXDCTL(0), txdctl);
3004         txdctl = er32(TXDCTL(1));
3005         txdctl = (txdctl & ~E1000_TXDCTL_WTHRESH) |
3006                  E1000_TXDCTL_FULL_TX_DESC_WB;
3007         txdctl = (txdctl & ~E1000_TXDCTL_PTHRESH) |
3008                  E1000_TXDCTL_MAX_TX_DESC_PREFETCH;
3009         ew32(TXDCTL(1), txdctl);
3010
3011         /*
3012          * ICH8 has opposite polarity of no_snoop bits.
3013          * By default, we should use snoop behavior.
3014          */
3015         if (mac->type == e1000_ich8lan)
3016                 snoop = PCIE_ICH8_SNOOP_ALL;
3017         else
3018                 snoop = (u32) ~(PCIE_NO_SNOOP_ALL);
3019         e1000e_set_pcie_no_snoop(hw, snoop);
3020
3021         ctrl_ext = er32(CTRL_EXT);
3022         ctrl_ext |= E1000_CTRL_EXT_RO_DIS;
3023         ew32(CTRL_EXT, ctrl_ext);
3024
3025         /*
3026          * Clear all of the statistics registers (clear on read).  It is
3027          * important that we do this after we have tried to establish link
3028          * because the symbol error count will increment wildly if there
3029          * is no link.
3030          */
3031         e1000_clear_hw_cntrs_ich8lan(hw);
3032
3033         return 0;
3034 }
3035 /**
3036  *  e1000_initialize_hw_bits_ich8lan - Initialize required hardware bits
3037  *  @hw: pointer to the HW structure
3038  *
3039  *  Sets/Clears required hardware bits necessary for correctly setting up the
3040  *  hardware for transmit and receive.
3041  **/
3042 static void e1000_initialize_hw_bits_ich8lan(struct e1000_hw *hw)
3043 {
3044         u32 reg;
3045
3046         /* Extended Device Control */
3047         reg = er32(CTRL_EXT);
3048         reg |= (1 << 22);
3049         /* Enable PHY low-power state when MAC is at D3 w/o WoL */
3050         if (hw->mac.type >= e1000_pchlan)
3051                 reg |= E1000_CTRL_EXT_PHYPDEN;
3052         ew32(CTRL_EXT, reg);
3053
3054         /* Transmit Descriptor Control 0 */
3055         reg = er32(TXDCTL(0));
3056         reg |= (1 << 22);
3057         ew32(TXDCTL(0), reg);
3058
3059         /* Transmit Descriptor Control 1 */
3060         reg = er32(TXDCTL(1));
3061         reg |= (1 << 22);
3062         ew32(TXDCTL(1), reg);
3063
3064         /* Transmit Arbitration Control 0 */
3065         reg = er32(TARC(0));
3066         if (hw->mac.type == e1000_ich8lan)
3067                 reg |= (1 << 28) | (1 << 29);
3068         reg |= (1 << 23) | (1 << 24) | (1 << 26) | (1 << 27);
3069         ew32(TARC(0), reg);
3070
3071         /* Transmit Arbitration Control 1 */
3072         reg = er32(TARC(1));
3073         if (er32(TCTL) & E1000_TCTL_MULR)
3074                 reg &= ~(1 << 28);
3075         else
3076                 reg |= (1 << 28);
3077         reg |= (1 << 24) | (1 << 26) | (1 << 30);
3078         ew32(TARC(1), reg);
3079
3080         /* Device Status */
3081         if (hw->mac.type == e1000_ich8lan) {
3082                 reg = er32(STATUS);
3083                 reg &= ~(1 << 31);
3084                 ew32(STATUS, reg);
3085         }
3086
3087         /*
3088          * work-around descriptor data corruption issue during nfs v2 udp
3089          * traffic, just disable the nfs filtering capability
3090          */
3091         reg = er32(RFCTL);
3092         reg |= (E1000_RFCTL_NFSW_DIS | E1000_RFCTL_NFSR_DIS);
3093         ew32(RFCTL, reg);
3094 }
3095
3096 /**
3097  *  e1000_setup_link_ich8lan - Setup flow control and link settings
3098  *  @hw: pointer to the HW structure
3099  *
3100  *  Determines which flow control settings to use, then configures flow
3101  *  control.  Calls the appropriate media-specific link configuration
3102  *  function.  Assuming the adapter has a valid link partner, a valid link
3103  *  should be established.  Assumes the hardware has previously been reset
3104  *  and the transmitter and receiver are not enabled.
3105  **/
3106 static s32 e1000_setup_link_ich8lan(struct e1000_hw *hw)
3107 {
3108         s32 ret_val;
3109
3110         if (e1000_check_reset_block(hw))
3111                 return 0;
3112
3113         /*
3114          * ICH parts do not have a word in the NVM to determine
3115          * the default flow control setting, so we explicitly
3116          * set it to full.
3117          */
3118         if (hw->fc.requested_mode == e1000_fc_default) {
3119                 /* Workaround h/w hang when Tx flow control enabled */
3120                 if (hw->mac.type == e1000_pchlan)
3121                         hw->fc.requested_mode = e1000_fc_rx_pause;
3122                 else
3123                         hw->fc.requested_mode = e1000_fc_full;
3124         }
3125
3126         /*
3127          * Save off the requested flow control mode for use later.  Depending
3128          * on the link partner's capabilities, we may or may not use this mode.
3129          */
3130         hw->fc.current_mode = hw->fc.requested_mode;
3131
3132         e_dbg("After fix-ups FlowControl is now = %x\n",
3133                 hw->fc.current_mode);
3134
3135         /* Continue to configure the copper link. */
3136         ret_val = e1000_setup_copper_link_ich8lan(hw);
3137         if (ret_val)
3138                 return ret_val;
3139
3140         ew32(FCTTV, hw->fc.pause_time);
3141         if ((hw->phy.type == e1000_phy_82578) ||
3142             (hw->phy.type == e1000_phy_82579) ||
3143             (hw->phy.type == e1000_phy_82577)) {
3144                 ew32(FCRTV_PCH, hw->fc.refresh_time);
3145
3146                 ret_val = hw->phy.ops.write_reg(hw,
3147                                              PHY_REG(BM_PORT_CTRL_PAGE, 27),
3148                                              hw->fc.pause_time);
3149                 if (ret_val)
3150                         return ret_val;
3151         }
3152
3153         return e1000e_set_fc_watermarks(hw);
3154 }
3155
3156 /**
3157  *  e1000_setup_copper_link_ich8lan - Configure MAC/PHY interface
3158  *  @hw: pointer to the HW structure
3159  *
3160  *  Configures the kumeran interface to the PHY to wait the appropriate time
3161  *  when polling the PHY, then call the generic setup_copper_link to finish
3162  *  configuring the copper link.
3163  **/
3164 static s32 e1000_setup_copper_link_ich8lan(struct e1000_hw *hw)
3165 {
3166         u32 ctrl;
3167         s32 ret_val;
3168         u16 reg_data;
3169
3170         ctrl = er32(CTRL);
3171         ctrl |= E1000_CTRL_SLU;
3172         ctrl &= ~(E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX);
3173         ew32(CTRL, ctrl);
3174
3175         /*
3176          * Set the mac to wait the maximum time between each iteration
3177          * and increase the max iterations when polling the phy;
3178          * this fixes erroneous timeouts at 10Mbps.
3179          */
3180         ret_val = e1000e_write_kmrn_reg(hw, E1000_KMRNCTRLSTA_TIMEOUTS, 0xFFFF);
3181         if (ret_val)
3182                 return ret_val;
3183         ret_val = e1000e_read_kmrn_reg(hw, E1000_KMRNCTRLSTA_INBAND_PARAM,
3184                                        &reg_data);
3185         if (ret_val)
3186                 return ret_val;
3187         reg_data |= 0x3F;
3188         ret_val = e1000e_write_kmrn_reg(hw, E1000_KMRNCTRLSTA_INBAND_PARAM,
3189                                         reg_data);
3190         if (ret_val)
3191                 return ret_val;
3192
3193         switch (hw->phy.type) {
3194         case e1000_phy_igp_3:
3195                 ret_val = e1000e_copper_link_setup_igp(hw);
3196                 if (ret_val)
3197                         return ret_val;
3198                 break;
3199         case e1000_phy_bm:
3200         case e1000_phy_82578:
3201                 ret_val = e1000e_copper_link_setup_m88(hw);
3202                 if (ret_val)
3203                         return ret_val;
3204                 break;
3205         case e1000_phy_82577:
3206         case e1000_phy_82579:
3207                 ret_val = e1000_copper_link_setup_82577(hw);
3208                 if (ret_val)
3209                         return ret_val;
3210                 break;
3211         case e1000_phy_ife:
3212                 ret_val = hw->phy.ops.read_reg(hw, IFE_PHY_MDIX_CONTROL,
3213                                                &reg_data);
3214                 if (ret_val)
3215                         return ret_val;
3216
3217                 reg_data &= ~IFE_PMC_AUTO_MDIX;
3218
3219                 switch (hw->phy.mdix) {
3220                 case 1:
3221                         reg_data &= ~IFE_PMC_FORCE_MDIX;
3222                         break;
3223                 case 2:
3224                         reg_data |= IFE_PMC_FORCE_MDIX;
3225                         break;
3226                 case 0:
3227                 default:
3228                         reg_data |= IFE_PMC_AUTO_MDIX;
3229                         break;
3230                 }
3231                 ret_val = hw->phy.ops.write_reg(hw, IFE_PHY_MDIX_CONTROL,
3232                                                 reg_data);
3233                 if (ret_val)
3234                         return ret_val;
3235                 break;
3236         default:
3237                 break;
3238         }
3239         return e1000e_setup_copper_link(hw);
3240 }
3241
3242 /**
3243  *  e1000_get_link_up_info_ich8lan - Get current link speed and duplex
3244  *  @hw: pointer to the HW structure
3245  *  @speed: pointer to store current link speed
3246  *  @duplex: pointer to store the current link duplex
3247  *
3248  *  Calls the generic get_speed_and_duplex to retrieve the current link
3249  *  information and then calls the Kumeran lock loss workaround for links at
3250  *  gigabit speeds.
3251  **/
3252 static s32 e1000_get_link_up_info_ich8lan(struct e1000_hw *hw, u16 *speed,
3253                                           u16 *duplex)
3254 {
3255         s32 ret_val;
3256
3257         ret_val = e1000e_get_speed_and_duplex_copper(hw, speed, duplex);
3258         if (ret_val)
3259                 return ret_val;
3260
3261         if ((hw->mac.type == e1000_ich8lan) &&
3262             (hw->phy.type == e1000_phy_igp_3) &&
3263             (*speed == SPEED_1000)) {
3264                 ret_val = e1000_kmrn_lock_loss_workaround_ich8lan(hw);
3265         }
3266
3267         return ret_val;
3268 }
3269
3270 /**
3271  *  e1000_kmrn_lock_loss_workaround_ich8lan - Kumeran workaround
3272  *  @hw: pointer to the HW structure
3273  *
3274  *  Work-around for 82566 Kumeran PCS lock loss:
3275  *  On link status change (i.e. PCI reset, speed change) and link is up and
3276  *  speed is gigabit-
3277  *    0) if workaround is optionally disabled do nothing
3278  *    1) wait 1ms for Kumeran link to come up
3279  *    2) check Kumeran Diagnostic register PCS lock loss bit
3280  *    3) if not set the link is locked (all is good), otherwise...
3281  *    4) reset the PHY
3282  *    5) repeat up to 10 times
3283  *  Note: this is only called for IGP3 copper when speed is 1gb.
3284  **/
3285 static s32 e1000_kmrn_lock_loss_workaround_ich8lan(struct e1000_hw *hw)
3286 {
3287         struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
3288         u32 phy_ctrl;
3289         s32 ret_val;
3290         u16 i, data;
3291         bool link;
3292
3293         if (!dev_spec->kmrn_lock_loss_workaround_enabled)
3294                 return 0;
3295
3296         /*
3297          * Make sure link is up before proceeding.  If not just return.
3298          * Attempting this while link is negotiating fouled up link
3299          * stability
3300          */
3301         ret_val = e1000e_phy_has_link_generic(hw, 1, 0, &link);
3302         if (!link)
3303                 return 0;
3304
3305         for (i = 0; i < 10; i++) {
3306                 /* read once to clear */
3307                 ret_val = e1e_rphy(hw, IGP3_KMRN_DIAG, &data);
3308                 if (ret_val)
3309                         return ret_val;
3310                 /* and again to get new status */
3311                 ret_val = e1e_rphy(hw, IGP3_KMRN_DIAG, &data);
3312                 if (ret_val)
3313                         return ret_val;
3314
3315                 /* check for PCS lock */
3316                 if (!(data & IGP3_KMRN_DIAG_PCS_LOCK_LOSS))
3317                         return 0;
3318
3319                 /* Issue PHY reset */
3320                 e1000_phy_hw_reset(hw);
3321                 mdelay(5);
3322         }
3323         /* Disable GigE link negotiation */
3324         phy_ctrl = er32(PHY_CTRL);
3325         phy_ctrl |= (E1000_PHY_CTRL_GBE_DISABLE |
3326                      E1000_PHY_CTRL_NOND0A_GBE_DISABLE);
3327         ew32(PHY_CTRL, phy_ctrl);
3328
3329         /*
3330          * Call gig speed drop workaround on Gig disable before accessing
3331          * any PHY registers
3332          */
3333         e1000e_gig_downshift_workaround_ich8lan(hw);
3334
3335         /* unable to acquire PCS lock */
3336         return -E1000_ERR_PHY;
3337 }
3338
3339 /**
3340  *  e1000_set_kmrn_lock_loss_workaround_ich8lan - Set Kumeran workaround state
3341  *  @hw: pointer to the HW structure
3342  *  @state: boolean value used to set the current Kumeran workaround state
3343  *
3344  *  If ICH8, set the current Kumeran workaround state (enabled - true
3345  *  /disabled - false).
3346  **/
3347 void e1000e_set_kmrn_lock_loss_workaround_ich8lan(struct e1000_hw *hw,
3348                                                  bool state)
3349 {
3350         struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
3351
3352         if (hw->mac.type != e1000_ich8lan) {
3353                 e_dbg("Workaround applies to ICH8 only.\n");
3354                 return;
3355         }
3356
3357         dev_spec->kmrn_lock_loss_workaround_enabled = state;
3358 }
3359
3360 /**
3361  *  e1000_ipg3_phy_powerdown_workaround_ich8lan - Power down workaround on D3
3362  *  @hw: pointer to the HW structure
3363  *
3364  *  Workaround for 82566 power-down on D3 entry:
3365  *    1) disable gigabit link
3366  *    2) write VR power-down enable
3367  *    3) read it back
3368  *  Continue if successful, else issue LCD reset and repeat
3369  **/
3370 void e1000e_igp3_phy_powerdown_workaround_ich8lan(struct e1000_hw *hw)
3371 {
3372         u32 reg;
3373         u16 data;
3374         u8  retry = 0;
3375
3376         if (hw->phy.type != e1000_phy_igp_3)
3377                 return;
3378
3379         /* Try the workaround twice (if needed) */
3380         do {
3381                 /* Disable link */
3382                 reg = er32(PHY_CTRL);
3383                 reg |= (E1000_PHY_CTRL_GBE_DISABLE |
3384                         E1000_PHY_CTRL_NOND0A_GBE_DISABLE);
3385                 ew32(PHY_CTRL, reg);
3386
3387                 /*
3388                  * Call gig speed drop workaround on Gig disable before
3389                  * accessing any PHY registers
3390                  */
3391                 if (hw->mac.type == e1000_ich8lan)
3392                         e1000e_gig_downshift_workaround_ich8lan(hw);
3393
3394                 /* Write VR power-down enable */
3395                 e1e_rphy(hw, IGP3_VR_CTRL, &data);
3396                 data &= ~IGP3_VR_CTRL_DEV_POWERDOWN_MODE_MASK;
3397                 e1e_wphy(hw, IGP3_VR_CTRL, data | IGP3_VR_CTRL_MODE_SHUTDOWN);
3398
3399                 /* Read it back and test */
3400                 e1e_rphy(hw, IGP3_VR_CTRL, &data);
3401                 data &= IGP3_VR_CTRL_DEV_POWERDOWN_MODE_MASK;
3402                 if ((data == IGP3_VR_CTRL_MODE_SHUTDOWN) || retry)
3403                         break;
3404
3405                 /* Issue PHY reset and repeat at most one more time */
3406                 reg = er32(CTRL);
3407                 ew32(CTRL, reg | E1000_CTRL_PHY_RST);
3408                 retry++;
3409         } while (retry);
3410 }
3411
3412 /**
3413  *  e1000e_gig_downshift_workaround_ich8lan - WoL from S5 stops working
3414  *  @hw: pointer to the HW structure
3415  *
3416  *  Steps to take when dropping from 1Gb/s (eg. link cable removal (LSC),
3417  *  LPLU, Gig disable, MDIC PHY reset):
3418  *    1) Set Kumeran Near-end loopback
3419  *    2) Clear Kumeran Near-end loopback
3420  *  Should only be called for ICH8[m] devices with IGP_3 Phy.
3421  **/
3422 void e1000e_gig_downshift_workaround_ich8lan(struct e1000_hw *hw)
3423 {
3424         s32 ret_val;
3425         u16 reg_data;
3426
3427         if ((hw->mac.type != e1000_ich8lan) ||
3428             (hw->phy.type != e1000_phy_igp_3))
3429                 return;
3430
3431         ret_val = e1000e_read_kmrn_reg(hw, E1000_KMRNCTRLSTA_DIAG_OFFSET,
3432                                       &reg_data);
3433         if (ret_val)
3434                 return;
3435         reg_data |= E1000_KMRNCTRLSTA_DIAG_NELPBK;
3436         ret_val = e1000e_write_kmrn_reg(hw, E1000_KMRNCTRLSTA_DIAG_OFFSET,
3437                                        reg_data);
3438         if (ret_val)
3439                 return;
3440         reg_data &= ~E1000_KMRNCTRLSTA_DIAG_NELPBK;
3441         ret_val = e1000e_write_kmrn_reg(hw, E1000_KMRNCTRLSTA_DIAG_OFFSET,
3442                                        reg_data);
3443 }
3444
3445 /**
3446  *  e1000e_disable_gig_wol_ich8lan - disable gig during WoL
3447  *  @hw: pointer to the HW structure
3448  *
3449  *  During S0 to Sx transition, it is possible the link remains at gig
3450  *  instead of negotiating to a lower speed.  Before going to Sx, set
3451  *  'LPLU Enabled' and 'Gig Disable' to force link speed negotiation
3452  *  to a lower speed.
3453  *
3454  *  Should only be called for applicable parts.
3455  **/
3456 void e1000e_disable_gig_wol_ich8lan(struct e1000_hw *hw)
3457 {
3458         u32 phy_ctrl;
3459
3460         phy_ctrl = er32(PHY_CTRL);
3461         phy_ctrl |= E1000_PHY_CTRL_D0A_LPLU | E1000_PHY_CTRL_GBE_DISABLE;
3462         ew32(PHY_CTRL, phy_ctrl);
3463
3464         if (hw->mac.type >= e1000_pchlan)
3465                 e1000_phy_hw_reset_ich8lan(hw);
3466 }
3467
3468 /**
3469  *  e1000_cleanup_led_ich8lan - Restore the default LED operation
3470  *  @hw: pointer to the HW structure
3471  *
3472  *  Return the LED back to the default configuration.
3473  **/
3474 static s32 e1000_cleanup_led_ich8lan(struct e1000_hw *hw)
3475 {
3476         if (hw->phy.type == e1000_phy_ife)
3477                 return e1e_wphy(hw, IFE_PHY_SPECIAL_CONTROL_LED, 0);
3478
3479         ew32(LEDCTL, hw->mac.ledctl_default);
3480         return 0;
3481 }
3482
3483 /**
3484  *  e1000_led_on_ich8lan - Turn LEDs on
3485  *  @hw: pointer to the HW structure
3486  *
3487  *  Turn on the LEDs.
3488  **/
3489 static s32 e1000_led_on_ich8lan(struct e1000_hw *hw)
3490 {
3491         if (hw->phy.type == e1000_phy_ife)
3492                 return e1e_wphy(hw, IFE_PHY_SPECIAL_CONTROL_LED,
3493                                 (IFE_PSCL_PROBE_MODE | IFE_PSCL_PROBE_LEDS_ON));
3494
3495         ew32(LEDCTL, hw->mac.ledctl_mode2);
3496         return 0;
3497 }
3498
3499 /**
3500  *  e1000_led_off_ich8lan - Turn LEDs off
3501  *  @hw: pointer to the HW structure
3502  *
3503  *  Turn off the LEDs.
3504  **/
3505 static s32 e1000_led_off_ich8lan(struct e1000_hw *hw)
3506 {
3507         if (hw->phy.type == e1000_phy_ife)
3508                 return e1e_wphy(hw, IFE_PHY_SPECIAL_CONTROL_LED,
3509                                (IFE_PSCL_PROBE_MODE | IFE_PSCL_PROBE_LEDS_OFF));
3510
3511         ew32(LEDCTL, hw->mac.ledctl_mode1);
3512         return 0;
3513 }
3514
3515 /**
3516  *  e1000_setup_led_pchlan - Configures SW controllable LED
3517  *  @hw: pointer to the HW structure
3518  *
3519  *  This prepares the SW controllable LED for use.
3520  **/
3521 static s32 e1000_setup_led_pchlan(struct e1000_hw *hw)
3522 {
3523         return hw->phy.ops.write_reg(hw, HV_LED_CONFIG,
3524                                         (u16)hw->mac.ledctl_mode1);
3525 }
3526
3527 /**
3528  *  e1000_cleanup_led_pchlan - Restore the default LED operation
3529  *  @hw: pointer to the HW structure
3530  *
3531  *  Return the LED back to the default configuration.
3532  **/
3533 static s32 e1000_cleanup_led_pchlan(struct e1000_hw *hw)
3534 {
3535         return hw->phy.ops.write_reg(hw, HV_LED_CONFIG,
3536                                         (u16)hw->mac.ledctl_default);
3537 }
3538
3539 /**
3540  *  e1000_led_on_pchlan - Turn LEDs on
3541  *  @hw: pointer to the HW structure
3542  *
3543  *  Turn on the LEDs.
3544  **/
3545 static s32 e1000_led_on_pchlan(struct e1000_hw *hw)
3546 {
3547         u16 data = (u16)hw->mac.ledctl_mode2;
3548         u32 i, led;
3549
3550         /*
3551          * If no link, then turn LED on by setting the invert bit
3552          * for each LED that's mode is "link_up" in ledctl_mode2.
3553          */
3554         if (!(er32(STATUS) & E1000_STATUS_LU)) {
3555                 for (i = 0; i < 3; i++) {
3556                         led = (data >> (i * 5)) & E1000_PHY_LED0_MASK;
3557                         if ((led & E1000_PHY_LED0_MODE_MASK) !=
3558                             E1000_LEDCTL_MODE_LINK_UP)
3559                                 continue;
3560                         if (led & E1000_PHY_LED0_IVRT)
3561                                 data &= ~(E1000_PHY_LED0_IVRT << (i * 5));
3562                         else
3563                                 data |= (E1000_PHY_LED0_IVRT << (i * 5));
3564                 }
3565         }
3566
3567         return hw->phy.ops.write_reg(hw, HV_LED_CONFIG, data);
3568 }
3569
3570 /**
3571  *  e1000_led_off_pchlan - Turn LEDs off
3572  *  @hw: pointer to the HW structure
3573  *
3574  *  Turn off the LEDs.
3575  **/
3576 static s32 e1000_led_off_pchlan(struct e1000_hw *hw)
3577 {
3578         u16 data = (u16)hw->mac.ledctl_mode1;
3579         u32 i, led;
3580
3581         /*
3582          * If no link, then turn LED off by clearing the invert bit
3583          * for each LED that's mode is "link_up" in ledctl_mode1.
3584          */
3585         if (!(er32(STATUS) & E1000_STATUS_LU)) {
3586                 for (i = 0; i < 3; i++) {
3587                         led = (data >> (i * 5)) & E1000_PHY_LED0_MASK;
3588                         if ((led & E1000_PHY_LED0_MODE_MASK) !=
3589                             E1000_LEDCTL_MODE_LINK_UP)
3590                                 continue;
3591                         if (led & E1000_PHY_LED0_IVRT)
3592                                 data &= ~(E1000_PHY_LED0_IVRT << (i * 5));
3593                         else
3594                                 data |= (E1000_PHY_LED0_IVRT << (i * 5));
3595                 }
3596         }
3597
3598         return hw->phy.ops.write_reg(hw, HV_LED_CONFIG, data);
3599 }
3600
3601 /**
3602  *  e1000_get_cfg_done_ich8lan - Read config done bit after Full or PHY reset
3603  *  @hw: pointer to the HW structure
3604  *
3605  *  Read appropriate register for the config done bit for completion status
3606  *  and configure the PHY through s/w for EEPROM-less parts.
3607  *
3608  *  NOTE: some silicon which is EEPROM-less will fail trying to read the
3609  *  config done bit, so only an error is logged and continues.  If we were
3610  *  to return with error, EEPROM-less silicon would not be able to be reset
3611  *  or change link.
3612  **/
3613 static s32 e1000_get_cfg_done_ich8lan(struct e1000_hw *hw)
3614 {
3615         s32 ret_val = 0;
3616         u32 bank = 0;
3617         u32 status;
3618
3619         e1000e_get_cfg_done(hw);
3620
3621         /* Wait for indication from h/w that it has completed basic config */
3622         if (hw->mac.type >= e1000_ich10lan) {
3623                 e1000_lan_init_done_ich8lan(hw);
3624         } else {
3625                 ret_val = e1000e_get_auto_rd_done(hw);
3626                 if (ret_val) {
3627                         /*
3628                          * When auto config read does not complete, do not
3629                          * return with an error. This can happen in situations
3630                          * where there is no eeprom and prevents getting link.
3631                          */
3632                         e_dbg("Auto Read Done did not complete\n");
3633                         ret_val = 0;
3634                 }
3635         }
3636
3637         /* Clear PHY Reset Asserted bit */
3638         status = er32(STATUS);
3639         if (status & E1000_STATUS_PHYRA)
3640                 ew32(STATUS, status & ~E1000_STATUS_PHYRA);
3641         else
3642                 e_dbg("PHY Reset Asserted not set - needs delay\n");
3643
3644         /* If EEPROM is not marked present, init the IGP 3 PHY manually */
3645         if (hw->mac.type <= e1000_ich9lan) {
3646                 if (((er32(EECD) & E1000_EECD_PRES) == 0) &&
3647                     (hw->phy.type == e1000_phy_igp_3)) {
3648                         e1000e_phy_init_script_igp3(hw);
3649                 }
3650         } else {
3651                 if (e1000_valid_nvm_bank_detect_ich8lan(hw, &bank)) {
3652                         /* Maybe we should do a basic PHY config */
3653                         e_dbg("EEPROM not present\n");
3654                         ret_val = -E1000_ERR_CONFIG;
3655                 }
3656         }
3657
3658         return ret_val;
3659 }
3660
3661 /**
3662  * e1000_power_down_phy_copper_ich8lan - Remove link during PHY power down
3663  * @hw: pointer to the HW structure
3664  *
3665  * In the case of a PHY power down to save power, or to turn off link during a
3666  * driver unload, or wake on lan is not enabled, remove the link.
3667  **/
3668 static void e1000_power_down_phy_copper_ich8lan(struct e1000_hw *hw)
3669 {
3670         /* If the management interface is not enabled, then power down */
3671         if (!(hw->mac.ops.check_mng_mode(hw) ||
3672               hw->phy.ops.check_reset_block(hw)))
3673                 e1000_power_down_phy_copper(hw);
3674 }
3675
3676 /**
3677  *  e1000_clear_hw_cntrs_ich8lan - Clear statistical counters
3678  *  @hw: pointer to the HW structure
3679  *
3680  *  Clears hardware counters specific to the silicon family and calls
3681  *  clear_hw_cntrs_generic to clear all general purpose counters.
3682  **/
3683 static void e1000_clear_hw_cntrs_ich8lan(struct e1000_hw *hw)
3684 {
3685         u16 phy_data;
3686
3687         e1000e_clear_hw_cntrs_base(hw);
3688
3689         er32(ALGNERRC);
3690         er32(RXERRC);
3691         er32(TNCRS);
3692         er32(CEXTERR);
3693         er32(TSCTC);
3694         er32(TSCTFC);
3695
3696         er32(MGTPRC);
3697         er32(MGTPDC);
3698         er32(MGTPTC);
3699
3700         er32(IAC);
3701         er32(ICRXOC);
3702
3703         /* Clear PHY statistics registers */
3704         if ((hw->phy.type == e1000_phy_82578) ||
3705             (hw->phy.type == e1000_phy_82579) ||
3706             (hw->phy.type == e1000_phy_82577)) {
3707                 hw->phy.ops.read_reg(hw, HV_SCC_UPPER, &phy_data);
3708                 hw->phy.ops.read_reg(hw, HV_SCC_LOWER, &phy_data);
3709                 hw->phy.ops.read_reg(hw, HV_ECOL_UPPER, &phy_data);
3710                 hw->phy.ops.read_reg(hw, HV_ECOL_LOWER, &phy_data);
3711                 hw->phy.ops.read_reg(hw, HV_MCC_UPPER, &phy_data);
3712                 hw->phy.ops.read_reg(hw, HV_MCC_LOWER, &phy_data);
3713                 hw->phy.ops.read_reg(hw, HV_LATECOL_UPPER, &phy_data);
3714                 hw->phy.ops.read_reg(hw, HV_LATECOL_LOWER, &phy_data);
3715                 hw->phy.ops.read_reg(hw, HV_COLC_UPPER, &phy_data);
3716                 hw->phy.ops.read_reg(hw, HV_COLC_LOWER, &phy_data);
3717                 hw->phy.ops.read_reg(hw, HV_DC_UPPER, &phy_data);
3718                 hw->phy.ops.read_reg(hw, HV_DC_LOWER, &phy_data);
3719                 hw->phy.ops.read_reg(hw, HV_TNCRS_UPPER, &phy_data);
3720                 hw->phy.ops.read_reg(hw, HV_TNCRS_LOWER, &phy_data);
3721         }
3722 }
3723
3724 static struct e1000_mac_operations ich8_mac_ops = {
3725         .id_led_init            = e1000e_id_led_init,
3726         /* check_mng_mode dependent on mac type */
3727         .check_for_link         = e1000_check_for_copper_link_ich8lan,
3728         /* cleanup_led dependent on mac type */
3729         .clear_hw_cntrs         = e1000_clear_hw_cntrs_ich8lan,
3730         .get_bus_info           = e1000_get_bus_info_ich8lan,
3731         .set_lan_id             = e1000_set_lan_id_single_port,
3732         .get_link_up_info       = e1000_get_link_up_info_ich8lan,
3733         /* led_on dependent on mac type */
3734         /* led_off dependent on mac type */
3735         .update_mc_addr_list    = e1000e_update_mc_addr_list_generic,
3736         .reset_hw               = e1000_reset_hw_ich8lan,
3737         .init_hw                = e1000_init_hw_ich8lan,
3738         .setup_link             = e1000_setup_link_ich8lan,
3739         .setup_physical_interface= e1000_setup_copper_link_ich8lan,
3740         /* id_led_init dependent on mac type */
3741 };
3742
3743 static struct e1000_phy_operations ich8_phy_ops = {
3744         .acquire                = e1000_acquire_swflag_ich8lan,
3745         .check_reset_block      = e1000_check_reset_block_ich8lan,
3746         .commit                 = NULL,
3747         .get_cfg_done           = e1000_get_cfg_done_ich8lan,
3748         .get_cable_length       = e1000e_get_cable_length_igp_2,
3749         .read_reg               = e1000e_read_phy_reg_igp,
3750         .release                = e1000_release_swflag_ich8lan,
3751         .reset                  = e1000_phy_hw_reset_ich8lan,
3752         .set_d0_lplu_state      = e1000_set_d0_lplu_state_ich8lan,
3753         .set_d3_lplu_state      = e1000_set_d3_lplu_state_ich8lan,
3754         .write_reg              = e1000e_write_phy_reg_igp,
3755 };
3756
3757 static struct e1000_nvm_operations ich8_nvm_ops = {
3758         .acquire                = e1000_acquire_nvm_ich8lan,
3759         .read                   = e1000_read_nvm_ich8lan,
3760         .release                = e1000_release_nvm_ich8lan,
3761         .update                 = e1000_update_nvm_checksum_ich8lan,
3762         .valid_led_default      = e1000_valid_led_default_ich8lan,
3763         .validate               = e1000_validate_nvm_checksum_ich8lan,
3764         .write                  = e1000_write_nvm_ich8lan,
3765 };
3766
3767 struct e1000_info e1000_ich8_info = {
3768         .mac                    = e1000_ich8lan,
3769         .flags                  = FLAG_HAS_WOL
3770                                   | FLAG_IS_ICH
3771                                   | FLAG_RX_CSUM_ENABLED
3772                                   | FLAG_HAS_CTRLEXT_ON_LOAD
3773                                   | FLAG_HAS_AMT
3774                                   | FLAG_HAS_FLASH
3775                                   | FLAG_APME_IN_WUC,
3776         .pba                    = 8,
3777         .max_hw_frame_size      = ETH_FRAME_LEN + ETH_FCS_LEN,
3778         .get_variants           = e1000_get_variants_ich8lan,
3779         .mac_ops                = &ich8_mac_ops,
3780         .phy_ops                = &ich8_phy_ops,
3781         .nvm_ops                = &ich8_nvm_ops,
3782 };
3783
3784 struct e1000_info e1000_ich9_info = {
3785         .mac                    = e1000_ich9lan,
3786         .flags                  = FLAG_HAS_JUMBO_FRAMES
3787                                   | FLAG_IS_ICH
3788                                   | FLAG_HAS_WOL
3789                                   | FLAG_RX_CSUM_ENABLED
3790                                   | FLAG_HAS_CTRLEXT_ON_LOAD
3791                                   | FLAG_HAS_AMT
3792                                   | FLAG_HAS_ERT
3793                                   | FLAG_HAS_FLASH
3794                                   | FLAG_APME_IN_WUC,
3795         .pba                    = 10,
3796         .max_hw_frame_size      = DEFAULT_JUMBO,
3797         .get_variants           = e1000_get_variants_ich8lan,
3798         .mac_ops                = &ich8_mac_ops,
3799         .phy_ops                = &ich8_phy_ops,
3800         .nvm_ops                = &ich8_nvm_ops,
3801 };
3802
3803 struct e1000_info e1000_ich10_info = {
3804         .mac                    = e1000_ich10lan,
3805         .flags                  = FLAG_HAS_JUMBO_FRAMES
3806                                   | FLAG_IS_ICH
3807                                   | FLAG_HAS_WOL
3808                                   | FLAG_RX_CSUM_ENABLED
3809                                   | FLAG_HAS_CTRLEXT_ON_LOAD
3810                                   | FLAG_HAS_AMT
3811                                   | FLAG_HAS_ERT
3812                                   | FLAG_HAS_FLASH
3813                                   | FLAG_APME_IN_WUC,
3814         .pba                    = 10,
3815         .max_hw_frame_size      = DEFAULT_JUMBO,
3816         .get_variants           = e1000_get_variants_ich8lan,
3817         .mac_ops                = &ich8_mac_ops,
3818         .phy_ops                = &ich8_phy_ops,
3819         .nvm_ops                = &ich8_nvm_ops,
3820 };
3821
3822 struct e1000_info e1000_pch_info = {
3823         .mac                    = e1000_pchlan,
3824         .flags                  = FLAG_IS_ICH
3825                                   | FLAG_HAS_WOL
3826                                   | FLAG_RX_CSUM_ENABLED
3827                                   | FLAG_HAS_CTRLEXT_ON_LOAD
3828                                   | FLAG_HAS_AMT
3829                                   | FLAG_HAS_FLASH
3830                                   | FLAG_HAS_JUMBO_FRAMES
3831                                   | FLAG_DISABLE_FC_PAUSE_TIME /* errata */
3832                                   | FLAG_APME_IN_WUC,
3833         .flags2                 = FLAG2_HAS_PHY_STATS,
3834         .pba                    = 26,
3835         .max_hw_frame_size      = 4096,
3836         .get_variants           = e1000_get_variants_ich8lan,
3837         .mac_ops                = &ich8_mac_ops,
3838         .phy_ops                = &ich8_phy_ops,
3839         .nvm_ops                = &ich8_nvm_ops,
3840 };
3841
3842 struct e1000_info e1000_pch2_info = {
3843         .mac                    = e1000_pch2lan,
3844         .flags                  = FLAG_IS_ICH
3845                                   | FLAG_HAS_WOL
3846                                   | FLAG_RX_CSUM_ENABLED
3847                                   | FLAG_HAS_CTRLEXT_ON_LOAD
3848                                   | FLAG_HAS_AMT
3849                                   | FLAG_HAS_FLASH
3850                                   | FLAG_HAS_JUMBO_FRAMES
3851                                   | FLAG_APME_IN_WUC,
3852         .flags2                 = FLAG2_HAS_PHY_STATS
3853                                   | FLAG2_HAS_EEE,
3854         .pba                    = 18,
3855         .max_hw_frame_size      = DEFAULT_JUMBO,
3856         .get_variants           = e1000_get_variants_ich8lan,
3857         .mac_ops                = &ich8_mac_ops,
3858         .phy_ops                = &ich8_phy_ops,
3859         .nvm_ops                = &ich8_nvm_ops,
3860 };