drivers/net/dsa/sja1105/sja1105_spi.c

   1 // SPDX-License-Identifier: BSD-3-Clause
   2 /* Copyright (c) 2016-2018, NXP Semiconductors
   3  * Copyright (c) 2018, Sensor-Technik Wiedemann GmbH
   4  * Copyright (c) 2018-2019, Vladimir Oltean <olteanv@gmail.com>
   5  */
   6 #include <linux/spi/spi.h>
   7 #include <linux/packing.h>
   8 #include "sja1105.h"
   9
  10 struct sja1105_chunk {
  11         u8      *buf;
  12         size_t  len;
  13         u64     reg_addr;
  14 };
  15
  16 static void
  17 sja1105_spi_message_pack(void *buf, const struct sja1105_spi_message *msg)
  18 {
  19         const int size = SJA1105_SIZE_SPI_MSG_HEADER;
  20
  21         memset(buf, 0, size);
  22
  23         sja1105_pack(buf, &msg->access,     31, 31, size);
  24         sja1105_pack(buf, &msg->read_count, 30, 25, size);
  25         sja1105_pack(buf, &msg->address,    24,  4, size);
  26 }
  27
  28 /* If @rw is:
  29  * - SPI_WRITE: creates and sends an SPI write message at absolute
  30  *              address reg_addr, taking @len bytes from *buf
  31  * - SPI_READ:  creates and sends an SPI read message from absolute
  32  *              address reg_addr, writing @len bytes into *buf
  33  */
  34 static int sja1105_xfer(const struct sja1105_private *priv,
  35                         sja1105_spi_rw_mode_t rw, u64 reg_addr, u8 *buf,
  36                         size_t len, struct ptp_system_timestamp *ptp_sts)
  37 {
  38         u8 hdr_buf[SJA1105_SIZE_SPI_MSG_HEADER] = {0};
  39         struct spi_device *spi = priv->spidev;
  40         struct spi_transfer xfers[2] = {0};
  41         struct spi_transfer *chunk_xfer;
  42         struct spi_transfer *hdr_xfer;
  43         struct sja1105_chunk chunk;
  44         int num_chunks;
  45         int rc, i = 0;
  46
  47         num_chunks = DIV_ROUND_UP(len, priv->max_xfer_len);
  48
  49         chunk.reg_addr = reg_addr;
  50         chunk.buf = buf;
  51         chunk.len = min_t(size_t, len, priv->max_xfer_len);
  52
  53         hdr_xfer = &xfers[0];
  54         chunk_xfer = &xfers[1];
  55
  56         for (i = 0; i < num_chunks; i++) {
  57                 struct spi_transfer *ptp_sts_xfer;
  58                 struct sja1105_spi_message msg;
  59
  60                 /* Populate the transfer's header buffer */
  61                 msg.address = chunk.reg_addr;
  62                 msg.access = rw;
  63                 if (rw == SPI_READ)
  64                         msg.read_count = chunk.len / 4;
  65                 else
  66                         /* Ignored */
  67                         msg.read_count = 0;
  68                 sja1105_spi_message_pack(hdr_buf, &msg);
  69                 hdr_xfer->tx_buf = hdr_buf;
  70                 hdr_xfer->len = SJA1105_SIZE_SPI_MSG_HEADER;
  71
  72                 /* Populate the transfer's data buffer */
  73                 if (rw == SPI_READ)
  74                         chunk_xfer->rx_buf = chunk.buf;
  75                 else
  76                         chunk_xfer->tx_buf = chunk.buf;
  77                 chunk_xfer->len = chunk.len;
  78
  79                 /* Request timestamping for the transfer. Instead of letting
  80                  * callers specify which byte they want to timestamp, we can
  81                  * make certain assumptions:
  82                  * - A read operation will request a software timestamp when
  83                  *   what's being read is the PTP time. That is snapshotted by
  84                  *   the switch hardware at the end of the command portion
  85                  *   (hdr_xfer).
  86                  * - A write operation will request a software timestamp on
  87                  *   actions that modify the PTP time. Taking clock stepping as
  88                  *   an example, the switch writes the PTP time at the end of
  89                  *   the data portion (chunk_xfer).
  90                  */
  91                 if (rw == SPI_READ)
  92                         ptp_sts_xfer = hdr_xfer;
  93                 else
  94                         ptp_sts_xfer = chunk_xfer;
  95                 ptp_sts_xfer->ptp_sts_word_pre = ptp_sts_xfer->len - 1;
  96                 ptp_sts_xfer->ptp_sts_word_post = ptp_sts_xfer->len - 1;
  97                 ptp_sts_xfer->ptp_sts = ptp_sts;
  98
  99                 /* Calculate next chunk */
 100                 chunk.buf += chunk.len;
 101                 chunk.reg_addr += chunk.len / 4;
 102                 chunk.len = min_t(size_t, (ptrdiff_t)(buf + len - chunk.buf),
 103                                   priv->max_xfer_len);
 104
 105                 rc = spi_sync_transfer(spi, xfers, 2);
 106                 if (rc < 0) {
 107                         dev_err(&spi->dev, "SPI transfer failed: %d\n", rc);
 108                         return rc;
 109                 }
 110         }
 111
 112         return 0;
 113 }
 114
 115 int sja1105_xfer_buf(const struct sja1105_private *priv,
 116                      sja1105_spi_rw_mode_t rw, u64 reg_addr,
 117                      u8 *buf, size_t len)
 118 {
 119         return sja1105_xfer(priv, rw, reg_addr, buf, len, NULL);
 120 }
 121
 122 /* If @rw is:
 123  * - SPI_WRITE: creates and sends an SPI write message at absolute
 124  *              address reg_addr
 125  * - SPI_READ:  creates and sends an SPI read message from absolute
 126  *              address reg_addr
 127  *
 128  * The u64 *value is unpacked, meaning that it's stored in the native
 129  * CPU endianness and directly usable by software running on the core.
 130  */
 131 int sja1105_xfer_u64(const struct sja1105_private *priv,
 132                      sja1105_spi_rw_mode_t rw, u64 reg_addr, u64 *value,
 133                      struct ptp_system_timestamp *ptp_sts)
 134 {
 135         u8 packed_buf[8];
 136         int rc;
 137
 138         if (rw == SPI_WRITE)
 139                 sja1105_pack(packed_buf, value, 63, 0, 8);
 140
 141         rc = sja1105_xfer(priv, rw, reg_addr, packed_buf, 8, ptp_sts);
 142
 143         if (rw == SPI_READ)
 144                 sja1105_unpack(packed_buf, value, 63, 0, 8);
 145
 146         return rc;
 147 }
 148
 149 /* Same as above, but transfers only a 4 byte word */
 150 int sja1105_xfer_u32(const struct sja1105_private *priv,
 151                      sja1105_spi_rw_mode_t rw, u64 reg_addr, u32 *value,
 152                      struct ptp_system_timestamp *ptp_sts)
 153 {
 154         u8 packed_buf[4];
 155         u64 tmp;
 156         int rc;
 157
 158         if (rw == SPI_WRITE) {
 159                 /* The packing API only supports u64 as CPU word size,
 160                  * so we need to convert.
 161                  */
 162                 tmp = *value;
 163                 sja1105_pack(packed_buf, &tmp, 31, 0, 4);
 164         }
 165
 166         rc = sja1105_xfer(priv, rw, reg_addr, packed_buf, 4, ptp_sts);
 167
 168         if (rw == SPI_READ) {
 169                 sja1105_unpack(packed_buf, &tmp, 31, 0, 4);
 170                 *value = tmp;
 171         }
 172
 173         return rc;
 174 }
 175
 176 static int sja1105et_reset_cmd(struct dsa_switch *ds)
 177 {
 178         struct sja1105_private *priv = ds->priv;
 179         const struct sja1105_regs *regs = priv->info->regs;
 180         u32 cold_reset = BIT(3);
 181
 182         /* Cold reset */
 183         return sja1105_xfer_u32(priv, SPI_WRITE, regs->rgu, &cold_reset, NULL);
 184 }
 185
 186 static int sja1105pqrs_reset_cmd(struct dsa_switch *ds)
 187 {
 188         struct sja1105_private *priv = ds->priv;
 189         const struct sja1105_regs *regs = priv->info->regs;
 190         u32 cold_reset = BIT(2);
 191
 192         /* Cold reset */
 193         return sja1105_xfer_u32(priv, SPI_WRITE, regs->rgu, &cold_reset, NULL);
 194 }
 195
 196 int sja1105_inhibit_tx(const struct sja1105_private *priv,
 197                        unsigned long port_bitmap, bool tx_inhibited)
 198 {
 199         const struct sja1105_regs *regs = priv->info->regs;
 200         u32 inhibit_cmd;
 201         int rc;
 202
 203         rc = sja1105_xfer_u32(priv, SPI_READ, regs->port_control,
 204                               &inhibit_cmd, NULL);
 205         if (rc < 0)
 206                 return rc;
 207
 208         if (tx_inhibited)
 209                 inhibit_cmd |= port_bitmap;
 210         else
 211                 inhibit_cmd &= ~port_bitmap;
 212
 213         return sja1105_xfer_u32(priv, SPI_WRITE, regs->port_control,
 214                                 &inhibit_cmd, NULL);
 215 }
 216
 217 struct sja1105_status {
 218         u64 configs;
 219         u64 crcchkl;
 220         u64 ids;
 221         u64 crcchkg;
 222 };
 223
 224 /* This is not reading the entire General Status area, which is also
 225  * divergent between E/T and P/Q/R/S, but only the relevant bits for
 226  * ensuring that the static config upload procedure was successful.
 227  */
 228 static void sja1105_status_unpack(void *buf, struct sja1105_status *status)
 229 {
 230         /* So that addition translates to 4 bytes */
 231         u32 *p = buf;
 232
 233         /* device_id is missing from the buffer, but we don't
 234          * want to diverge from the manual definition of the
 235          * register addresses, so we'll back off one step with
 236          * the register pointer, and never access p[0].
 237          */
 238         p--;
 239         sja1105_unpack(p + 0x1, &status->configs,   31, 31, 4);
 240         sja1105_unpack(p + 0x1, &status->crcchkl,   30, 30, 4);
 241         sja1105_unpack(p + 0x1, &status->ids,       29, 29, 4);
 242         sja1105_unpack(p + 0x1, &status->crcchkg,   28, 28, 4);
 243 }
 244
 245 static int sja1105_status_get(struct sja1105_private *priv,
 246                               struct sja1105_status *status)
 247 {
 248         const struct sja1105_regs *regs = priv->info->regs;
 249         u8 packed_buf[4];
 250         int rc;
 251
 252         rc = sja1105_xfer_buf(priv, SPI_READ, regs->status, packed_buf, 4);
 253         if (rc < 0)
 254                 return rc;
 255
 256         sja1105_status_unpack(packed_buf, status);
 257
 258         return 0;
 259 }
 260
 261 /* Not const because unpacking priv->static_config into buffers and preparing
 262  * for upload requires the recalculation of table CRCs and updating the
 263  * structures with these.
 264  */
 265 int static_config_buf_prepare_for_upload(struct sja1105_private *priv,
 266                                          void *config_buf, int buf_len)
 267 {
 268         struct sja1105_static_config *config = &priv->static_config;
 269         struct sja1105_table_header final_header;
 270         sja1105_config_valid_t valid;
 271         char *final_header_ptr;
 272         int crc_len;
 273
 274         valid = sja1105_static_config_check_valid(config,
 275                                                   priv->info->max_frame_mem);
 276         if (valid != SJA1105_CONFIG_OK) {
 277                 dev_err(&priv->spidev->dev,
 278                         sja1105_static_config_error_msg[valid]);
 279                 return -EINVAL;
 280         }
 281
 282         /* Write Device ID and config tables to config_buf */
 283         sja1105_static_config_pack(config_buf, config);
 284         /* Recalculate CRC of the last header (right now 0xDEADBEEF).
 285          * Don't include the CRC field itself.
 286          */
 287         crc_len = buf_len - 4;
 288         /* Read the whole table header */
 289         final_header_ptr = config_buf + buf_len - SJA1105_SIZE_TABLE_HEADER;
 290         sja1105_table_header_packing(final_header_ptr, &final_header, UNPACK);
 291         /* Modify */
 292         final_header.crc = sja1105_crc32(config_buf, crc_len);
 293         /* Rewrite */
 294         sja1105_table_header_packing(final_header_ptr, &final_header, PACK);
 295
 296         return 0;
 297 }
 298
 299 #define RETRIES 10
 300
 301 int sja1105_static_config_upload(struct sja1105_private *priv)
 302 {
 303         struct sja1105_static_config *config = &priv->static_config;
 304         const struct sja1105_regs *regs = priv->info->regs;
 305         struct device *dev = &priv->spidev->dev;
 306         struct dsa_switch *ds = priv->ds;
 307         struct sja1105_status status;
 308         int rc, retries = RETRIES;
 309         u8 *config_buf;
 310         int buf_len;
 311
 312         buf_len = sja1105_static_config_get_length(config);
 313         config_buf = kcalloc(buf_len, sizeof(char), GFP_KERNEL);
 314         if (!config_buf)
 315                 return -ENOMEM;
 316
 317         rc = static_config_buf_prepare_for_upload(priv, config_buf, buf_len);
 318         if (rc < 0) {
 319                 dev_err(dev, "Invalid config, cannot upload\n");
 320                 rc = -EINVAL;
 321                 goto out;
 322         }
 323         /* Prevent PHY jabbering during switch reset by inhibiting
 324          * Tx on all ports and waiting for current packet to drain.
 325          * Otherwise, the PHY will see an unterminated Ethernet packet.
 326          */
 327         rc = sja1105_inhibit_tx(priv, GENMASK_ULL(ds->num_ports - 1, 0), true);
 328         if (rc < 0) {
 329                 dev_err(dev, "Failed to inhibit Tx on ports\n");
 330                 rc = -ENXIO;
 331                 goto out;
 332         }
 333         /* Wait for an eventual egress packet to finish transmission
 334          * (reach IFG). It is guaranteed that a second one will not
 335          * follow, and that switch cold reset is thus safe
 336          */
 337         usleep_range(500, 1000);
 338         do {
 339                 /* Put the SJA1105 in programming mode */
 340                 rc = priv->info->reset_cmd(priv->ds);
 341                 if (rc < 0) {
 342                         dev_err(dev, "Failed to reset switch, retrying...\n");
 343                         continue;
 344                 }
 345                 /* Wait for the switch to come out of reset */
 346                 usleep_range(1000, 5000);
 347                 /* Upload the static config to the device */
 348                 rc = sja1105_xfer_buf(priv, SPI_WRITE, regs->config,
 349                                       config_buf, buf_len);
 350                 if (rc < 0) {
 351                         dev_err(dev, "Failed to upload config, retrying...\n");
 352                         continue;
 353                 }
 354                 /* Check that SJA1105 responded well to the config upload */
 355                 rc = sja1105_status_get(priv, &status);
 356                 if (rc < 0)
 357                         continue;
 358
 359                 if (status.ids == 1) {
 360                         dev_err(dev, "Mismatch between hardware and static config "
 361                                 "device id. Wrote 0x%llx, wants 0x%llx\n",
 362                                 config->device_id, priv->info->device_id);
 363                         continue;
 364                 }
 365                 if (status.crcchkl == 1) {
 366                         dev_err(dev, "Switch reported invalid local CRC on "
 367                                 "the uploaded config, retrying...\n");
 368                         continue;
 369                 }
 370                 if (status.crcchkg == 1) {
 371                         dev_err(dev, "Switch reported invalid global CRC on "
 372                                 "the uploaded config, retrying...\n");
 373                         continue;
 374                 }
 375                 if (status.configs == 0) {
 376                         dev_err(dev, "Switch reported that configuration is "
 377                                 "invalid, retrying...\n");
 378                         continue;
 379                 }
 380                 /* Success! */
 381                 break;
 382         } while (--retries);
 383
 384         if (!retries) {
 385                 rc = -EIO;
 386                 dev_err(dev, "Failed to upload config to device, giving up\n");
 387                 goto out;
 388         } else if (retries != RETRIES) {
 389                 dev_info(dev, "Succeeded after %d tried\n", RETRIES - retries);
 390         }
 391
 392 out:
 393         kfree(config_buf);
 394         return rc;
 395 }
 396
 397 static struct sja1105_regs sja1105et_regs = {
 398         .device_id = 0x0,
 399         .prod_id = 0x100BC3,
 400         .status = 0x1,
 401         .port_control = 0x11,
 402         .vl_status = 0x10000,
 403         .config = 0x020000,
 404         .rgu = 0x100440,
 405         /* UM10944.pdf, Table 86, ACU Register overview */
 406         .pad_mii_tx = {0x100800, 0x100802, 0x100804, 0x100806, 0x100808},
 407         .pad_mii_rx = {0x100801, 0x100803, 0x100805, 0x100807, 0x100809},
 408         .rmii_pll1 = 0x10000A,
 409         .cgu_idiv = {0x10000B, 0x10000C, 0x10000D, 0x10000E, 0x10000F},
 410         .stats[MAC] = {0x200, 0x202, 0x204, 0x206, 0x208},
 411         .stats[HL1] = {0x400, 0x410, 0x420, 0x430, 0x440},
 412         .stats[HL2] = {0x600, 0x610, 0x620, 0x630, 0x640},
 413         /* UM10944.pdf, Table 78, CGU Register overview */
 414         .mii_tx_clk = {0x100013, 0x10001A, 0x100021, 0x100028, 0x10002F},
 415         .mii_rx_clk = {0x100014, 0x10001B, 0x100022, 0x100029, 0x100030},
 416         .mii_ext_tx_clk = {0x100018, 0x10001F, 0x100026, 0x10002D, 0x100034},
 417         .mii_ext_rx_clk = {0x100019, 0x100020, 0x100027, 0x10002E, 0x100035},
 418         .rgmii_tx_clk = {0x100016, 0x10001D, 0x100024, 0x10002B, 0x100032},
 419         .rmii_ref_clk = {0x100015, 0x10001C, 0x100023, 0x10002A, 0x100031},
 420         .rmii_ext_tx_clk = {0x100018, 0x10001F, 0x100026, 0x10002D, 0x100034},
 421         .ptpegr_ts = {0xC0, 0xC2, 0xC4, 0xC6, 0xC8},
 422         .ptpschtm = 0x12, /* Spans 0x12 to 0x13 */
 423         .ptppinst = 0x14,
 424         .ptppindur = 0x16,
 425         .ptp_control = 0x17,
 426         .ptpclkval = 0x18, /* Spans 0x18 to 0x19 */
 427         .ptpclkrate = 0x1A,
 428         .ptpclkcorp = 0x1D,
 429 };
 430
 431 static struct sja1105_regs sja1105pqrs_regs = {
 432         .device_id = 0x0,
 433         .prod_id = 0x100BC3,
 434         .status = 0x1,
 435         .port_control = 0x12,
 436         .vl_status = 0x10000,
 437         .config = 0x020000,
 438         .rgu = 0x100440,
 439         /* UM10944.pdf, Table 86, ACU Register overview */
 440         .pad_mii_tx = {0x100800, 0x100802, 0x100804, 0x100806, 0x100808},
 441         .pad_mii_rx = {0x100801, 0x100803, 0x100805, 0x100807, 0x100809},
 442         .pad_mii_id = {0x100810, 0x100811, 0x100812, 0x100813, 0x100814},
 443         .rmii_pll1 = 0x10000A,
 444         .cgu_idiv = {0x10000B, 0x10000C, 0x10000D, 0x10000E, 0x10000F},
 445         .stats[MAC] = {0x200, 0x202, 0x204, 0x206, 0x208},
 446         .stats[HL1] = {0x400, 0x410, 0x420, 0x430, 0x440},
 447         .stats[HL2] = {0x600, 0x610, 0x620, 0x630, 0x640},
 448         .stats[ETHER] = {0x1400, 0x1418, 0x1430, 0x1448, 0x1460},
 449         /* UM11040.pdf, Table 114 */
 450         .mii_tx_clk = {0x100013, 0x100019, 0x10001F, 0x100025, 0x10002B},
 451         .mii_rx_clk = {0x100014, 0x10001A, 0x100020, 0x100026, 0x10002C},
 452         .mii_ext_tx_clk = {0x100017, 0x10001D, 0x100023, 0x100029, 0x10002F},
 453         .mii_ext_rx_clk = {0x100018, 0x10001E, 0x100024, 0x10002A, 0x100030},
 454         .rgmii_tx_clk = {0x100016, 0x10001C, 0x100022, 0x100028, 0x10002E},
 455         .rmii_ref_clk = {0x100015, 0x10001B, 0x100021, 0x100027, 0x10002D},
 456         .rmii_ext_tx_clk = {0x100017, 0x10001D, 0x100023, 0x100029, 0x10002F},
 457         .ptpegr_ts = {0xC0, 0xC4, 0xC8, 0xCC, 0xD0},
 458         .ptpschtm = 0x13, /* Spans 0x13 to 0x14 */
 459         .ptppinst = 0x15,
 460         .ptppindur = 0x17,
 461         .ptp_control = 0x18,
 462         .ptpclkval = 0x19,
 463         .ptpclkrate = 0x1B,
 464         .ptpclkcorp = 0x1E,
 465         .ptpsyncts = 0x1F,
 466 };
 467
 468 const struct sja1105_info sja1105e_info = {
 469         .device_id              = SJA1105E_DEVICE_ID,
 470         .part_no                = SJA1105ET_PART_NO,
 471         .static_ops             = sja1105e_table_ops,
 472         .dyn_ops                = sja1105et_dyn_ops,
 473         .qinq_tpid              = ETH_P_8021Q,
 474         .can_limit_mcast_flood  = false,
 475         .ptp_ts_bits            = 24,
 476         .ptpegr_ts_bytes        = 4,
 477         .max_frame_mem          = SJA1105_MAX_FRAME_MEMORY,
 478         .num_cbs_shapers        = SJA1105ET_MAX_CBS_COUNT,
 479         .reset_cmd              = sja1105et_reset_cmd,
 480         .fdb_add_cmd            = sja1105et_fdb_add,
 481         .fdb_del_cmd            = sja1105et_fdb_del,
 482         .ptp_cmd_packing        = sja1105et_ptp_cmd_packing,
 483         .clocking_setup         = sja1105_clocking_setup,
 484         .regs                   = &sja1105et_regs,
 485         .port_speed             = {
 486                 [SJA1105_SPEED_AUTO] = 0,
 487                 [SJA1105_SPEED_10MBPS] = 3,
 488                 [SJA1105_SPEED_100MBPS] = 2,
 489                 [SJA1105_SPEED_1000MBPS] = 1,
 490                 [SJA1105_SPEED_2500MBPS] = 0, /* Not supported */
 491         },
 492         .supports_mii           = {true, true, true, true, true},
 493         .supports_rmii          = {true, true, true, true, true},
 494         .supports_rgmii         = {true, true, true, true, true},
 495         .name                   = "SJA1105E",
 496 };
 497
 498 const struct sja1105_info sja1105t_info = {
 499         .device_id              = SJA1105T_DEVICE_ID,
 500         .part_no                = SJA1105ET_PART_NO,
 501         .static_ops             = sja1105t_table_ops,
 502         .dyn_ops                = sja1105et_dyn_ops,
 503         .qinq_tpid              = ETH_P_8021Q,
 504         .can_limit_mcast_flood  = false,
 505         .ptp_ts_bits            = 24,
 506         .ptpegr_ts_bytes        = 4,
 507         .max_frame_mem          = SJA1105_MAX_FRAME_MEMORY,
 508         .num_cbs_shapers        = SJA1105ET_MAX_CBS_COUNT,
 509         .reset_cmd              = sja1105et_reset_cmd,
 510         .fdb_add_cmd            = sja1105et_fdb_add,
 511         .fdb_del_cmd            = sja1105et_fdb_del,
 512         .ptp_cmd_packing        = sja1105et_ptp_cmd_packing,
 513         .clocking_setup         = sja1105_clocking_setup,
 514         .regs                   = &sja1105et_regs,
 515         .port_speed             = {
 516                 [SJA1105_SPEED_AUTO] = 0,
 517                 [SJA1105_SPEED_10MBPS] = 3,
 518                 [SJA1105_SPEED_100MBPS] = 2,
 519                 [SJA1105_SPEED_1000MBPS] = 1,
 520                 [SJA1105_SPEED_2500MBPS] = 0, /* Not supported */
 521         },
 522         .supports_mii           = {true, true, true, true, true},
 523         .supports_rmii          = {true, true, true, true, true},
 524         .supports_rgmii         = {true, true, true, true, true},
 525         .name                   = "SJA1105T",
 526 };
 527
 528 const struct sja1105_info sja1105p_info = {
 529         .device_id              = SJA1105PR_DEVICE_ID,
 530         .part_no                = SJA1105P_PART_NO,
 531         .static_ops             = sja1105p_table_ops,
 532         .dyn_ops                = sja1105pqrs_dyn_ops,
 533         .qinq_tpid              = ETH_P_8021AD,
 534         .can_limit_mcast_flood  = true,
 535         .ptp_ts_bits            = 32,
 536         .ptpegr_ts_bytes        = 8,
 537         .max_frame_mem          = SJA1105_MAX_FRAME_MEMORY,
 538         .num_cbs_shapers        = SJA1105PQRS_MAX_CBS_COUNT,
 539         .setup_rgmii_delay      = sja1105pqrs_setup_rgmii_delay,
 540         .reset_cmd              = sja1105pqrs_reset_cmd,
 541         .fdb_add_cmd            = sja1105pqrs_fdb_add,
 542         .fdb_del_cmd            = sja1105pqrs_fdb_del,
 543         .ptp_cmd_packing        = sja1105pqrs_ptp_cmd_packing,
 544         .clocking_setup         = sja1105_clocking_setup,
 545         .regs                   = &sja1105pqrs_regs,
 546         .port_speed             = {
 547                 [SJA1105_SPEED_AUTO] = 0,
 548                 [SJA1105_SPEED_10MBPS] = 3,
 549                 [SJA1105_SPEED_100MBPS] = 2,
 550                 [SJA1105_SPEED_1000MBPS] = 1,
 551                 [SJA1105_SPEED_2500MBPS] = 0, /* Not supported */
 552         },
 553         .supports_mii           = {true, true, true, true, true},
 554         .supports_rmii          = {true, true, true, true, true},
 555         .supports_rgmii         = {true, true, true, true, true},
 556         .name                   = "SJA1105P",
 557 };
 558
 559 const struct sja1105_info sja1105q_info = {
 560         .device_id              = SJA1105QS_DEVICE_ID,
 561         .part_no                = SJA1105Q_PART_NO,
 562         .static_ops             = sja1105q_table_ops,
 563         .dyn_ops                = sja1105pqrs_dyn_ops,
 564         .qinq_tpid              = ETH_P_8021AD,
 565         .can_limit_mcast_flood  = true,
 566         .ptp_ts_bits            = 32,
 567         .ptpegr_ts_bytes        = 8,
 568         .max_frame_mem          = SJA1105_MAX_FRAME_MEMORY,
 569         .num_cbs_shapers        = SJA1105PQRS_MAX_CBS_COUNT,
 570         .setup_rgmii_delay      = sja1105pqrs_setup_rgmii_delay,
 571         .reset_cmd              = sja1105pqrs_reset_cmd,
 572         .fdb_add_cmd            = sja1105pqrs_fdb_add,
 573         .fdb_del_cmd            = sja1105pqrs_fdb_del,
 574         .ptp_cmd_packing        = sja1105pqrs_ptp_cmd_packing,
 575         .clocking_setup         = sja1105_clocking_setup,
 576         .regs                   = &sja1105pqrs_regs,
 577         .port_speed             = {
 578                 [SJA1105_SPEED_AUTO] = 0,
 579                 [SJA1105_SPEED_10MBPS] = 3,
 580                 [SJA1105_SPEED_100MBPS] = 2,
 581                 [SJA1105_SPEED_1000MBPS] = 1,
 582                 [SJA1105_SPEED_2500MBPS] = 0, /* Not supported */
 583         },
 584         .supports_mii           = {true, true, true, true, true},
 585         .supports_rmii          = {true, true, true, true, true},
 586         .supports_rgmii         = {true, true, true, true, true},
 587         .name                   = "SJA1105Q",
 588 };
 589
 590 const struct sja1105_info sja1105r_info = {
 591         .device_id              = SJA1105PR_DEVICE_ID,
 592         .part_no                = SJA1105R_PART_NO,
 593         .static_ops             = sja1105r_table_ops,
 594         .dyn_ops                = sja1105pqrs_dyn_ops,
 595         .qinq_tpid              = ETH_P_8021AD,
 596         .can_limit_mcast_flood  = true,
 597         .ptp_ts_bits            = 32,
 598         .ptpegr_ts_bytes        = 8,
 599         .max_frame_mem          = SJA1105_MAX_FRAME_MEMORY,
 600         .num_cbs_shapers        = SJA1105PQRS_MAX_CBS_COUNT,
 601         .setup_rgmii_delay      = sja1105pqrs_setup_rgmii_delay,
 602         .reset_cmd              = sja1105pqrs_reset_cmd,
 603         .fdb_add_cmd            = sja1105pqrs_fdb_add,
 604         .fdb_del_cmd            = sja1105pqrs_fdb_del,
 605         .ptp_cmd_packing        = sja1105pqrs_ptp_cmd_packing,
 606         .clocking_setup         = sja1105_clocking_setup,
 607         .regs                   = &sja1105pqrs_regs,
 608         .port_speed             = {
 609                 [SJA1105_SPEED_AUTO] = 0,
 610                 [SJA1105_SPEED_10MBPS] = 3,
 611                 [SJA1105_SPEED_100MBPS] = 2,
 612                 [SJA1105_SPEED_1000MBPS] = 1,
 613                 [SJA1105_SPEED_2500MBPS] = 0, /* Not supported */
 614         },
 615         .supports_mii           = {true, true, true, true, true},
 616         .supports_rmii          = {true, true, true, true, true},
 617         .supports_rgmii         = {true, true, true, true, true},
 618         .supports_sgmii         = {false, false, false, false, true},
 619         .name                   = "SJA1105R",
 620 };
 621
 622 const struct sja1105_info sja1105s_info = {
 623         .device_id              = SJA1105QS_DEVICE_ID,
 624         .part_no                = SJA1105S_PART_NO,
 625         .static_ops             = sja1105s_table_ops,
 626         .dyn_ops                = sja1105pqrs_dyn_ops,
 627         .regs                   = &sja1105pqrs_regs,
 628         .qinq_tpid              = ETH_P_8021AD,
 629         .can_limit_mcast_flood  = true,
 630         .ptp_ts_bits            = 32,
 631         .ptpegr_ts_bytes        = 8,
 632         .max_frame_mem          = SJA1105_MAX_FRAME_MEMORY,
 633         .num_cbs_shapers        = SJA1105PQRS_MAX_CBS_COUNT,
 634         .setup_rgmii_delay      = sja1105pqrs_setup_rgmii_delay,
 635         .reset_cmd              = sja1105pqrs_reset_cmd,
 636         .fdb_add_cmd            = sja1105pqrs_fdb_add,
 637         .fdb_del_cmd            = sja1105pqrs_fdb_del,
 638         .ptp_cmd_packing        = sja1105pqrs_ptp_cmd_packing,
 639         .clocking_setup         = sja1105_clocking_setup,
 640         .port_speed             = {
 641                 [SJA1105_SPEED_AUTO] = 0,
 642                 [SJA1105_SPEED_10MBPS] = 3,
 643                 [SJA1105_SPEED_100MBPS] = 2,
 644                 [SJA1105_SPEED_1000MBPS] = 1,
 645                 [SJA1105_SPEED_2500MBPS] = 0, /* Not supported */
 646         },
 647         .supports_mii           = {true, true, true, true, true},
 648         .supports_rmii          = {true, true, true, true, true},
 649         .supports_rgmii         = {true, true, true, true, true},
 650         .supports_sgmii         = {false, false, false, false, true},
 651         .name                   = "SJA1105S",
 652 };