1 // SPDX-License-Identifier: BSD-3-Clause
2 /* Copyright (c) 2016-2018, NXP Semiconductors
3 * Copyright (c) 2018, Sensor-Technik Wiedemann GmbH
4 * Copyright (c) 2018-2019, Vladimir Oltean <olteanv@gmail.com>
6 #include <linux/spi/spi.h>
7 #include <linux/packing.h>
10 struct sja1105_chunk {
17 sja1105_spi_message_pack(void *buf, const struct sja1105_spi_message *msg)
19 const int size = SJA1105_SIZE_SPI_MSG_HEADER;
23 sja1105_pack(buf, &msg->access, 31, 31, size);
24 sja1105_pack(buf, &msg->read_count, 30, 25, size);
25 sja1105_pack(buf, &msg->address, 24, 4, size);
29 * - SPI_WRITE: creates and sends an SPI write message at absolute
30 * address reg_addr, taking @len bytes from *buf
31 * - SPI_READ: creates and sends an SPI read message from absolute
32 * address reg_addr, writing @len bytes into *buf
34 static int sja1105_xfer(const struct sja1105_private *priv,
35 sja1105_spi_rw_mode_t rw, u64 reg_addr, u8 *buf,
36 size_t len, struct ptp_system_timestamp *ptp_sts)
38 u8 hdr_buf[SJA1105_SIZE_SPI_MSG_HEADER] = {0};
39 struct spi_device *spi = priv->spidev;
40 struct spi_transfer xfers[2] = {0};
41 struct spi_transfer *chunk_xfer;
42 struct spi_transfer *hdr_xfer;
43 struct sja1105_chunk chunk;
47 num_chunks = DIV_ROUND_UP(len, priv->max_xfer_len);
49 chunk.reg_addr = reg_addr;
51 chunk.len = min_t(size_t, len, priv->max_xfer_len);
54 chunk_xfer = &xfers[1];
56 for (i = 0; i < num_chunks; i++) {
57 struct spi_transfer *ptp_sts_xfer;
58 struct sja1105_spi_message msg;
60 /* Populate the transfer's header buffer */
61 msg.address = chunk.reg_addr;
64 msg.read_count = chunk.len / 4;
68 sja1105_spi_message_pack(hdr_buf, &msg);
69 hdr_xfer->tx_buf = hdr_buf;
70 hdr_xfer->len = SJA1105_SIZE_SPI_MSG_HEADER;
72 /* Populate the transfer's data buffer */
74 chunk_xfer->rx_buf = chunk.buf;
76 chunk_xfer->tx_buf = chunk.buf;
77 chunk_xfer->len = chunk.len;
79 /* Request timestamping for the transfer. Instead of letting
80 * callers specify which byte they want to timestamp, we can
81 * make certain assumptions:
82 * - A read operation will request a software timestamp when
83 * what's being read is the PTP time. That is snapshotted by
84 * the switch hardware at the end of the command portion
86 * - A write operation will request a software timestamp on
87 * actions that modify the PTP time. Taking clock stepping as
88 * an example, the switch writes the PTP time at the end of
89 * the data portion (chunk_xfer).
92 ptp_sts_xfer = hdr_xfer;
94 ptp_sts_xfer = chunk_xfer;
95 ptp_sts_xfer->ptp_sts_word_pre = ptp_sts_xfer->len - 1;
96 ptp_sts_xfer->ptp_sts_word_post = ptp_sts_xfer->len - 1;
97 ptp_sts_xfer->ptp_sts = ptp_sts;
99 /* Calculate next chunk */
100 chunk.buf += chunk.len;
101 chunk.reg_addr += chunk.len / 4;
102 chunk.len = min_t(size_t, (ptrdiff_t)(buf + len - chunk.buf),
105 rc = spi_sync_transfer(spi, xfers, 2);
107 dev_err(&spi->dev, "SPI transfer failed: %d\n", rc);
115 int sja1105_xfer_buf(const struct sja1105_private *priv,
116 sja1105_spi_rw_mode_t rw, u64 reg_addr,
119 return sja1105_xfer(priv, rw, reg_addr, buf, len, NULL);
123 * - SPI_WRITE: creates and sends an SPI write message at absolute
125 * - SPI_READ: creates and sends an SPI read message from absolute
128 * The u64 *value is unpacked, meaning that it's stored in the native
129 * CPU endianness and directly usable by software running on the core.
131 int sja1105_xfer_u64(const struct sja1105_private *priv,
132 sja1105_spi_rw_mode_t rw, u64 reg_addr, u64 *value,
133 struct ptp_system_timestamp *ptp_sts)
139 sja1105_pack(packed_buf, value, 63, 0, 8);
141 rc = sja1105_xfer(priv, rw, reg_addr, packed_buf, 8, ptp_sts);
144 sja1105_unpack(packed_buf, value, 63, 0, 8);
149 /* Same as above, but transfers only a 4 byte word */
150 int sja1105_xfer_u32(const struct sja1105_private *priv,
151 sja1105_spi_rw_mode_t rw, u64 reg_addr, u32 *value,
152 struct ptp_system_timestamp *ptp_sts)
158 if (rw == SPI_WRITE) {
159 /* The packing API only supports u64 as CPU word size,
160 * so we need to convert.
163 sja1105_pack(packed_buf, &tmp, 31, 0, 4);
166 rc = sja1105_xfer(priv, rw, reg_addr, packed_buf, 4, ptp_sts);
168 if (rw == SPI_READ) {
169 sja1105_unpack(packed_buf, &tmp, 31, 0, 4);
176 static int sja1105et_reset_cmd(struct dsa_switch *ds)
178 struct sja1105_private *priv = ds->priv;
179 const struct sja1105_regs *regs = priv->info->regs;
180 u32 cold_reset = BIT(3);
183 return sja1105_xfer_u32(priv, SPI_WRITE, regs->rgu, &cold_reset, NULL);
186 static int sja1105pqrs_reset_cmd(struct dsa_switch *ds)
188 struct sja1105_private *priv = ds->priv;
189 const struct sja1105_regs *regs = priv->info->regs;
190 u32 cold_reset = BIT(2);
193 return sja1105_xfer_u32(priv, SPI_WRITE, regs->rgu, &cold_reset, NULL);
196 static int sja1110_reset_cmd(struct dsa_switch *ds)
198 struct sja1105_private *priv = ds->priv;
199 const struct sja1105_regs *regs = priv->info->regs;
200 u32 switch_reset = BIT(20);
202 /* Switch core reset */
203 return sja1105_xfer_u32(priv, SPI_WRITE, regs->rgu, &switch_reset, NULL);
206 int sja1105_inhibit_tx(const struct sja1105_private *priv,
207 unsigned long port_bitmap, bool tx_inhibited)
209 const struct sja1105_regs *regs = priv->info->regs;
213 rc = sja1105_xfer_u32(priv, SPI_READ, regs->port_control,
219 inhibit_cmd |= port_bitmap;
221 inhibit_cmd &= ~port_bitmap;
223 return sja1105_xfer_u32(priv, SPI_WRITE, regs->port_control,
227 struct sja1105_status {
234 /* This is not reading the entire General Status area, which is also
235 * divergent between E/T and P/Q/R/S, but only the relevant bits for
236 * ensuring that the static config upload procedure was successful.
238 static void sja1105_status_unpack(void *buf, struct sja1105_status *status)
240 /* So that addition translates to 4 bytes */
243 /* device_id is missing from the buffer, but we don't
244 * want to diverge from the manual definition of the
245 * register addresses, so we'll back off one step with
246 * the register pointer, and never access p[0].
249 sja1105_unpack(p + 0x1, &status->configs, 31, 31, 4);
250 sja1105_unpack(p + 0x1, &status->crcchkl, 30, 30, 4);
251 sja1105_unpack(p + 0x1, &status->ids, 29, 29, 4);
252 sja1105_unpack(p + 0x1, &status->crcchkg, 28, 28, 4);
255 static int sja1105_status_get(struct sja1105_private *priv,
256 struct sja1105_status *status)
258 const struct sja1105_regs *regs = priv->info->regs;
262 rc = sja1105_xfer_buf(priv, SPI_READ, regs->status, packed_buf, 4);
266 sja1105_status_unpack(packed_buf, status);
271 /* Not const because unpacking priv->static_config into buffers and preparing
272 * for upload requires the recalculation of table CRCs and updating the
273 * structures with these.
275 int static_config_buf_prepare_for_upload(struct sja1105_private *priv,
276 void *config_buf, int buf_len)
278 struct sja1105_static_config *config = &priv->static_config;
279 struct sja1105_table_header final_header;
280 sja1105_config_valid_t valid;
281 char *final_header_ptr;
284 valid = sja1105_static_config_check_valid(config,
285 priv->info->max_frame_mem);
286 if (valid != SJA1105_CONFIG_OK) {
287 dev_err(&priv->spidev->dev,
288 sja1105_static_config_error_msg[valid]);
292 /* Write Device ID and config tables to config_buf */
293 sja1105_static_config_pack(config_buf, config);
294 /* Recalculate CRC of the last header (right now 0xDEADBEEF).
295 * Don't include the CRC field itself.
297 crc_len = buf_len - 4;
298 /* Read the whole table header */
299 final_header_ptr = config_buf + buf_len - SJA1105_SIZE_TABLE_HEADER;
300 sja1105_table_header_packing(final_header_ptr, &final_header, UNPACK);
302 final_header.crc = sja1105_crc32(config_buf, crc_len);
304 sja1105_table_header_packing(final_header_ptr, &final_header, PACK);
311 int sja1105_static_config_upload(struct sja1105_private *priv)
313 struct sja1105_static_config *config = &priv->static_config;
314 const struct sja1105_regs *regs = priv->info->regs;
315 struct device *dev = &priv->spidev->dev;
316 struct dsa_switch *ds = priv->ds;
317 struct sja1105_status status;
318 int rc, retries = RETRIES;
322 buf_len = sja1105_static_config_get_length(config);
323 config_buf = kcalloc(buf_len, sizeof(char), GFP_KERNEL);
327 rc = static_config_buf_prepare_for_upload(priv, config_buf, buf_len);
329 dev_err(dev, "Invalid config, cannot upload\n");
333 /* Prevent PHY jabbering during switch reset by inhibiting
334 * Tx on all ports and waiting for current packet to drain.
335 * Otherwise, the PHY will see an unterminated Ethernet packet.
337 rc = sja1105_inhibit_tx(priv, GENMASK_ULL(ds->num_ports - 1, 0), true);
339 dev_err(dev, "Failed to inhibit Tx on ports\n");
343 /* Wait for an eventual egress packet to finish transmission
344 * (reach IFG). It is guaranteed that a second one will not
345 * follow, and that switch cold reset is thus safe
347 usleep_range(500, 1000);
349 /* Put the SJA1105 in programming mode */
350 rc = priv->info->reset_cmd(priv->ds);
352 dev_err(dev, "Failed to reset switch, retrying...\n");
355 /* Wait for the switch to come out of reset */
356 usleep_range(1000, 5000);
357 /* Upload the static config to the device */
358 rc = sja1105_xfer_buf(priv, SPI_WRITE, regs->config,
359 config_buf, buf_len);
361 dev_err(dev, "Failed to upload config, retrying...\n");
364 /* Check that SJA1105 responded well to the config upload */
365 rc = sja1105_status_get(priv, &status);
369 if (status.ids == 1) {
370 dev_err(dev, "Mismatch between hardware and static config "
371 "device id. Wrote 0x%llx, wants 0x%llx\n",
372 config->device_id, priv->info->device_id);
375 if (status.crcchkl == 1) {
376 dev_err(dev, "Switch reported invalid local CRC on "
377 "the uploaded config, retrying...\n");
380 if (status.crcchkg == 1) {
381 dev_err(dev, "Switch reported invalid global CRC on "
382 "the uploaded config, retrying...\n");
385 if (status.configs == 0) {
386 dev_err(dev, "Switch reported that configuration is "
387 "invalid, retrying...\n");
396 dev_err(dev, "Failed to upload config to device, giving up\n");
398 } else if (retries != RETRIES) {
399 dev_info(dev, "Succeeded after %d tried\n", RETRIES - retries);
407 static struct sja1105_regs sja1105et_regs = {
411 .port_control = 0x11,
412 .vl_status = 0x10000,
415 /* UM10944.pdf, Table 86, ACU Register overview */
416 .pad_mii_tx = {0x100800, 0x100802, 0x100804, 0x100806, 0x100808},
417 .pad_mii_rx = {0x100801, 0x100803, 0x100805, 0x100807, 0x100809},
418 .rmii_pll1 = 0x10000A,
419 .cgu_idiv = {0x10000B, 0x10000C, 0x10000D, 0x10000E, 0x10000F},
420 .stats[MAC] = {0x200, 0x202, 0x204, 0x206, 0x208},
421 .stats[HL1] = {0x400, 0x410, 0x420, 0x430, 0x440},
422 .stats[HL2] = {0x600, 0x610, 0x620, 0x630, 0x640},
423 /* UM10944.pdf, Table 78, CGU Register overview */
424 .mii_tx_clk = {0x100013, 0x10001A, 0x100021, 0x100028, 0x10002F},
425 .mii_rx_clk = {0x100014, 0x10001B, 0x100022, 0x100029, 0x100030},
426 .mii_ext_tx_clk = {0x100018, 0x10001F, 0x100026, 0x10002D, 0x100034},
427 .mii_ext_rx_clk = {0x100019, 0x100020, 0x100027, 0x10002E, 0x100035},
428 .rgmii_tx_clk = {0x100016, 0x10001D, 0x100024, 0x10002B, 0x100032},
429 .rmii_ref_clk = {0x100015, 0x10001C, 0x100023, 0x10002A, 0x100031},
430 .rmii_ext_tx_clk = {0x100018, 0x10001F, 0x100026, 0x10002D, 0x100034},
431 .ptpegr_ts = {0xC0, 0xC2, 0xC4, 0xC6, 0xC8},
432 .ptpschtm = 0x12, /* Spans 0x12 to 0x13 */
436 .ptpclkval = 0x18, /* Spans 0x18 to 0x19 */
439 .mdio_100base_tx = SJA1105_RSV_ADDR,
440 .mdio_100base_t1 = SJA1105_RSV_ADDR,
443 static struct sja1105_regs sja1105pqrs_regs = {
447 .port_control = 0x12,
448 .vl_status = 0x10000,
451 /* UM10944.pdf, Table 86, ACU Register overview */
452 .pad_mii_tx = {0x100800, 0x100802, 0x100804, 0x100806, 0x100808},
453 .pad_mii_rx = {0x100801, 0x100803, 0x100805, 0x100807, 0x100809},
454 .pad_mii_id = {0x100810, 0x100811, 0x100812, 0x100813, 0x100814},
455 .rmii_pll1 = 0x10000A,
456 .cgu_idiv = {0x10000B, 0x10000C, 0x10000D, 0x10000E, 0x10000F},
457 .stats[MAC] = {0x200, 0x202, 0x204, 0x206, 0x208},
458 .stats[HL1] = {0x400, 0x410, 0x420, 0x430, 0x440},
459 .stats[HL2] = {0x600, 0x610, 0x620, 0x630, 0x640},
460 .stats[ETHER] = {0x1400, 0x1418, 0x1430, 0x1448, 0x1460},
461 /* UM11040.pdf, Table 114 */
462 .mii_tx_clk = {0x100013, 0x100019, 0x10001F, 0x100025, 0x10002B},
463 .mii_rx_clk = {0x100014, 0x10001A, 0x100020, 0x100026, 0x10002C},
464 .mii_ext_tx_clk = {0x100017, 0x10001D, 0x100023, 0x100029, 0x10002F},
465 .mii_ext_rx_clk = {0x100018, 0x10001E, 0x100024, 0x10002A, 0x100030},
466 .rgmii_tx_clk = {0x100016, 0x10001C, 0x100022, 0x100028, 0x10002E},
467 .rmii_ref_clk = {0x100015, 0x10001B, 0x100021, 0x100027, 0x10002D},
468 .rmii_ext_tx_clk = {0x100017, 0x10001D, 0x100023, 0x100029, 0x10002F},
469 .ptpegr_ts = {0xC0, 0xC4, 0xC8, 0xCC, 0xD0},
470 .ptpschtm = 0x13, /* Spans 0x13 to 0x14 */
478 .mdio_100base_tx = SJA1105_RSV_ADDR,
479 .mdio_100base_t1 = SJA1105_RSV_ADDR,
482 static struct sja1105_regs sja1110_regs = {
483 .device_id = SJA1110_SPI_ADDR(0x0),
484 .prod_id = SJA1110_ACU_ADDR(0xf00),
485 .status = SJA1110_SPI_ADDR(0x4),
486 .port_control = SJA1110_SPI_ADDR(0x50), /* actually INHIB_TX */
487 .vl_status = 0x10000,
489 .rgu = SJA1110_RGU_ADDR(0x100), /* Reset Control Register 0 */
490 /* Ports 2 and 3 are capable of xMII, but there isn't anything to
491 * configure in the CGU/ACU for them.
493 .pad_mii_tx = {SJA1105_RSV_ADDR, SJA1105_RSV_ADDR,
494 SJA1105_RSV_ADDR, SJA1105_RSV_ADDR,
495 SJA1105_RSV_ADDR, SJA1105_RSV_ADDR,
496 SJA1105_RSV_ADDR, SJA1105_RSV_ADDR,
497 SJA1105_RSV_ADDR, SJA1105_RSV_ADDR,
499 .pad_mii_rx = {SJA1105_RSV_ADDR, SJA1105_RSV_ADDR,
500 SJA1105_RSV_ADDR, SJA1105_RSV_ADDR,
501 SJA1105_RSV_ADDR, SJA1105_RSV_ADDR,
502 SJA1105_RSV_ADDR, SJA1105_RSV_ADDR,
503 SJA1105_RSV_ADDR, SJA1105_RSV_ADDR,
505 .pad_mii_id = {SJA1105_RSV_ADDR, SJA1105_RSV_ADDR,
506 SJA1110_ACU_ADDR(0x18), SJA1110_ACU_ADDR(0x28),
507 SJA1105_RSV_ADDR, SJA1105_RSV_ADDR,
508 SJA1105_RSV_ADDR, SJA1105_RSV_ADDR,
509 SJA1105_RSV_ADDR, SJA1105_RSV_ADDR,
511 .rmii_pll1 = SJA1105_RSV_ADDR,
512 .cgu_idiv = {SJA1105_RSV_ADDR, SJA1105_RSV_ADDR, SJA1105_RSV_ADDR,
513 SJA1105_RSV_ADDR, SJA1105_RSV_ADDR, SJA1105_RSV_ADDR,
514 SJA1105_RSV_ADDR, SJA1105_RSV_ADDR, SJA1105_RSV_ADDR,
515 SJA1105_RSV_ADDR, SJA1105_RSV_ADDR},
516 .stats[MAC] = {0x200, 0x202, 0x204, 0x206, 0x208, 0x20a,
517 0x20c, 0x20e, 0x210, 0x212, 0x214},
518 .stats[HL1] = {0x400, 0x410, 0x420, 0x430, 0x440, 0x450,
519 0x460, 0x470, 0x480, 0x490, 0x4a0},
520 .stats[HL2] = {0x600, 0x610, 0x620, 0x630, 0x640, 0x650,
521 0x660, 0x670, 0x680, 0x690, 0x6a0},
522 .stats[ETHER] = {0x1400, 0x1418, 0x1430, 0x1448, 0x1460, 0x1478,
523 0x1490, 0x14a8, 0x14c0, 0x14d8, 0x14f0},
524 .mii_tx_clk = {SJA1105_RSV_ADDR, SJA1105_RSV_ADDR, SJA1105_RSV_ADDR,
525 SJA1105_RSV_ADDR, SJA1105_RSV_ADDR, SJA1105_RSV_ADDR,
526 SJA1105_RSV_ADDR, SJA1105_RSV_ADDR, SJA1105_RSV_ADDR,
527 SJA1105_RSV_ADDR, SJA1105_RSV_ADDR},
528 .mii_rx_clk = {SJA1105_RSV_ADDR, SJA1105_RSV_ADDR, SJA1105_RSV_ADDR,
529 SJA1105_RSV_ADDR, SJA1105_RSV_ADDR, SJA1105_RSV_ADDR,
530 SJA1105_RSV_ADDR, SJA1105_RSV_ADDR, SJA1105_RSV_ADDR,
531 SJA1105_RSV_ADDR, SJA1105_RSV_ADDR},
532 .mii_ext_tx_clk = {SJA1105_RSV_ADDR, SJA1105_RSV_ADDR, SJA1105_RSV_ADDR,
533 SJA1105_RSV_ADDR, SJA1105_RSV_ADDR, SJA1105_RSV_ADDR,
534 SJA1105_RSV_ADDR, SJA1105_RSV_ADDR, SJA1105_RSV_ADDR,
535 SJA1105_RSV_ADDR, SJA1105_RSV_ADDR},
536 .mii_ext_rx_clk = {SJA1105_RSV_ADDR, SJA1105_RSV_ADDR, SJA1105_RSV_ADDR,
537 SJA1105_RSV_ADDR, SJA1105_RSV_ADDR, SJA1105_RSV_ADDR,
538 SJA1105_RSV_ADDR, SJA1105_RSV_ADDR, SJA1105_RSV_ADDR,
539 SJA1105_RSV_ADDR, SJA1105_RSV_ADDR},
540 .rgmii_tx_clk = {SJA1105_RSV_ADDR, SJA1105_RSV_ADDR, SJA1105_RSV_ADDR,
541 SJA1105_RSV_ADDR, SJA1105_RSV_ADDR, SJA1105_RSV_ADDR,
542 SJA1105_RSV_ADDR, SJA1105_RSV_ADDR, SJA1105_RSV_ADDR,
543 SJA1105_RSV_ADDR, SJA1105_RSV_ADDR},
544 .rmii_ref_clk = {SJA1105_RSV_ADDR, SJA1105_RSV_ADDR, SJA1105_RSV_ADDR,
545 SJA1105_RSV_ADDR, SJA1105_RSV_ADDR, SJA1105_RSV_ADDR,
546 SJA1105_RSV_ADDR, SJA1105_RSV_ADDR, SJA1105_RSV_ADDR,
547 SJA1105_RSV_ADDR, SJA1105_RSV_ADDR},
548 .rmii_ext_tx_clk = {SJA1105_RSV_ADDR, SJA1105_RSV_ADDR,
549 SJA1105_RSV_ADDR, SJA1105_RSV_ADDR,
550 SJA1105_RSV_ADDR, SJA1105_RSV_ADDR,
551 SJA1105_RSV_ADDR, SJA1105_RSV_ADDR,
552 SJA1105_RSV_ADDR, SJA1105_RSV_ADDR,
554 .ptpschtm = SJA1110_SPI_ADDR(0x54),
555 .ptppinst = SJA1110_SPI_ADDR(0x5c),
556 .ptppindur = SJA1110_SPI_ADDR(0x64),
557 .ptp_control = SJA1110_SPI_ADDR(0x68),
558 .ptpclkval = SJA1110_SPI_ADDR(0x6c),
559 .ptpclkrate = SJA1110_SPI_ADDR(0x74),
560 .ptpclkcorp = SJA1110_SPI_ADDR(0x80),
561 .ptpsyncts = SJA1110_SPI_ADDR(0x84),
562 .mdio_100base_tx = 0x1c2400,
563 .mdio_100base_t1 = 0x1c1000,
566 const struct sja1105_info sja1105e_info = {
567 .device_id = SJA1105E_DEVICE_ID,
568 .part_no = SJA1105ET_PART_NO,
569 .static_ops = sja1105e_table_ops,
570 .dyn_ops = sja1105et_dyn_ops,
571 .qinq_tpid = ETH_P_8021Q,
572 .tag_proto = DSA_TAG_PROTO_SJA1105,
573 .can_limit_mcast_flood = false,
575 .ptpegr_ts_bytes = 4,
576 .max_frame_mem = SJA1105_MAX_FRAME_MEMORY,
577 .num_ports = SJA1105_NUM_PORTS,
578 .num_cbs_shapers = SJA1105ET_MAX_CBS_COUNT,
579 .reset_cmd = sja1105et_reset_cmd,
580 .fdb_add_cmd = sja1105et_fdb_add,
581 .fdb_del_cmd = sja1105et_fdb_del,
582 .ptp_cmd_packing = sja1105et_ptp_cmd_packing,
583 .rxtstamp = sja1105_rxtstamp,
584 .clocking_setup = sja1105_clocking_setup,
585 .regs = &sja1105et_regs,
587 [SJA1105_SPEED_AUTO] = 0,
588 [SJA1105_SPEED_10MBPS] = 3,
589 [SJA1105_SPEED_100MBPS] = 2,
590 [SJA1105_SPEED_1000MBPS] = 1,
591 [SJA1105_SPEED_2500MBPS] = 0, /* Not supported */
593 .supports_mii = {true, true, true, true, true},
594 .supports_rmii = {true, true, true, true, true},
595 .supports_rgmii = {true, true, true, true, true},
599 const struct sja1105_info sja1105t_info = {
600 .device_id = SJA1105T_DEVICE_ID,
601 .part_no = SJA1105ET_PART_NO,
602 .static_ops = sja1105t_table_ops,
603 .dyn_ops = sja1105et_dyn_ops,
604 .qinq_tpid = ETH_P_8021Q,
605 .tag_proto = DSA_TAG_PROTO_SJA1105,
606 .can_limit_mcast_flood = false,
608 .ptpegr_ts_bytes = 4,
609 .max_frame_mem = SJA1105_MAX_FRAME_MEMORY,
610 .num_ports = SJA1105_NUM_PORTS,
611 .num_cbs_shapers = SJA1105ET_MAX_CBS_COUNT,
612 .reset_cmd = sja1105et_reset_cmd,
613 .fdb_add_cmd = sja1105et_fdb_add,
614 .fdb_del_cmd = sja1105et_fdb_del,
615 .ptp_cmd_packing = sja1105et_ptp_cmd_packing,
616 .rxtstamp = sja1105_rxtstamp,
617 .clocking_setup = sja1105_clocking_setup,
618 .regs = &sja1105et_regs,
620 [SJA1105_SPEED_AUTO] = 0,
621 [SJA1105_SPEED_10MBPS] = 3,
622 [SJA1105_SPEED_100MBPS] = 2,
623 [SJA1105_SPEED_1000MBPS] = 1,
624 [SJA1105_SPEED_2500MBPS] = 0, /* Not supported */
626 .supports_mii = {true, true, true, true, true},
627 .supports_rmii = {true, true, true, true, true},
628 .supports_rgmii = {true, true, true, true, true},
632 const struct sja1105_info sja1105p_info = {
633 .device_id = SJA1105PR_DEVICE_ID,
634 .part_no = SJA1105P_PART_NO,
635 .static_ops = sja1105p_table_ops,
636 .dyn_ops = sja1105pqrs_dyn_ops,
637 .qinq_tpid = ETH_P_8021AD,
638 .tag_proto = DSA_TAG_PROTO_SJA1105,
639 .can_limit_mcast_flood = true,
641 .ptpegr_ts_bytes = 8,
642 .max_frame_mem = SJA1105_MAX_FRAME_MEMORY,
643 .num_ports = SJA1105_NUM_PORTS,
644 .num_cbs_shapers = SJA1105PQRS_MAX_CBS_COUNT,
645 .setup_rgmii_delay = sja1105pqrs_setup_rgmii_delay,
646 .reset_cmd = sja1105pqrs_reset_cmd,
647 .fdb_add_cmd = sja1105pqrs_fdb_add,
648 .fdb_del_cmd = sja1105pqrs_fdb_del,
649 .ptp_cmd_packing = sja1105pqrs_ptp_cmd_packing,
650 .rxtstamp = sja1105_rxtstamp,
651 .clocking_setup = sja1105_clocking_setup,
652 .regs = &sja1105pqrs_regs,
654 [SJA1105_SPEED_AUTO] = 0,
655 [SJA1105_SPEED_10MBPS] = 3,
656 [SJA1105_SPEED_100MBPS] = 2,
657 [SJA1105_SPEED_1000MBPS] = 1,
658 [SJA1105_SPEED_2500MBPS] = 0, /* Not supported */
660 .supports_mii = {true, true, true, true, true},
661 .supports_rmii = {true, true, true, true, true},
662 .supports_rgmii = {true, true, true, true, true},
666 const struct sja1105_info sja1105q_info = {
667 .device_id = SJA1105QS_DEVICE_ID,
668 .part_no = SJA1105Q_PART_NO,
669 .static_ops = sja1105q_table_ops,
670 .dyn_ops = sja1105pqrs_dyn_ops,
671 .qinq_tpid = ETH_P_8021AD,
672 .tag_proto = DSA_TAG_PROTO_SJA1105,
673 .can_limit_mcast_flood = true,
675 .ptpegr_ts_bytes = 8,
676 .max_frame_mem = SJA1105_MAX_FRAME_MEMORY,
677 .num_ports = SJA1105_NUM_PORTS,
678 .num_cbs_shapers = SJA1105PQRS_MAX_CBS_COUNT,
679 .setup_rgmii_delay = sja1105pqrs_setup_rgmii_delay,
680 .reset_cmd = sja1105pqrs_reset_cmd,
681 .fdb_add_cmd = sja1105pqrs_fdb_add,
682 .fdb_del_cmd = sja1105pqrs_fdb_del,
683 .ptp_cmd_packing = sja1105pqrs_ptp_cmd_packing,
684 .rxtstamp = sja1105_rxtstamp,
685 .clocking_setup = sja1105_clocking_setup,
686 .regs = &sja1105pqrs_regs,
688 [SJA1105_SPEED_AUTO] = 0,
689 [SJA1105_SPEED_10MBPS] = 3,
690 [SJA1105_SPEED_100MBPS] = 2,
691 [SJA1105_SPEED_1000MBPS] = 1,
692 [SJA1105_SPEED_2500MBPS] = 0, /* Not supported */
694 .supports_mii = {true, true, true, true, true},
695 .supports_rmii = {true, true, true, true, true},
696 .supports_rgmii = {true, true, true, true, true},
700 const struct sja1105_info sja1105r_info = {
701 .device_id = SJA1105PR_DEVICE_ID,
702 .part_no = SJA1105R_PART_NO,
703 .static_ops = sja1105r_table_ops,
704 .dyn_ops = sja1105pqrs_dyn_ops,
705 .qinq_tpid = ETH_P_8021AD,
706 .tag_proto = DSA_TAG_PROTO_SJA1105,
707 .can_limit_mcast_flood = true,
709 .ptpegr_ts_bytes = 8,
710 .max_frame_mem = SJA1105_MAX_FRAME_MEMORY,
711 .num_ports = SJA1105_NUM_PORTS,
712 .num_cbs_shapers = SJA1105PQRS_MAX_CBS_COUNT,
713 .setup_rgmii_delay = sja1105pqrs_setup_rgmii_delay,
714 .reset_cmd = sja1105pqrs_reset_cmd,
715 .fdb_add_cmd = sja1105pqrs_fdb_add,
716 .fdb_del_cmd = sja1105pqrs_fdb_del,
717 .ptp_cmd_packing = sja1105pqrs_ptp_cmd_packing,
718 .rxtstamp = sja1105_rxtstamp,
719 .clocking_setup = sja1105_clocking_setup,
720 .regs = &sja1105pqrs_regs,
722 [SJA1105_SPEED_AUTO] = 0,
723 [SJA1105_SPEED_10MBPS] = 3,
724 [SJA1105_SPEED_100MBPS] = 2,
725 [SJA1105_SPEED_1000MBPS] = 1,
726 [SJA1105_SPEED_2500MBPS] = 0, /* Not supported */
728 .supports_mii = {true, true, true, true, true},
729 .supports_rmii = {true, true, true, true, true},
730 .supports_rgmii = {true, true, true, true, true},
731 .supports_sgmii = {false, false, false, false, true},
735 const struct sja1105_info sja1105s_info = {
736 .device_id = SJA1105QS_DEVICE_ID,
737 .part_no = SJA1105S_PART_NO,
738 .static_ops = sja1105s_table_ops,
739 .dyn_ops = sja1105pqrs_dyn_ops,
740 .regs = &sja1105pqrs_regs,
741 .qinq_tpid = ETH_P_8021AD,
742 .tag_proto = DSA_TAG_PROTO_SJA1105,
743 .can_limit_mcast_flood = true,
745 .ptpegr_ts_bytes = 8,
746 .max_frame_mem = SJA1105_MAX_FRAME_MEMORY,
747 .num_ports = SJA1105_NUM_PORTS,
748 .num_cbs_shapers = SJA1105PQRS_MAX_CBS_COUNT,
749 .setup_rgmii_delay = sja1105pqrs_setup_rgmii_delay,
750 .reset_cmd = sja1105pqrs_reset_cmd,
751 .fdb_add_cmd = sja1105pqrs_fdb_add,
752 .fdb_del_cmd = sja1105pqrs_fdb_del,
753 .ptp_cmd_packing = sja1105pqrs_ptp_cmd_packing,
754 .rxtstamp = sja1105_rxtstamp,
755 .clocking_setup = sja1105_clocking_setup,
757 [SJA1105_SPEED_AUTO] = 0,
758 [SJA1105_SPEED_10MBPS] = 3,
759 [SJA1105_SPEED_100MBPS] = 2,
760 [SJA1105_SPEED_1000MBPS] = 1,
761 [SJA1105_SPEED_2500MBPS] = 0, /* Not supported */
763 .supports_mii = {true, true, true, true, true},
764 .supports_rmii = {true, true, true, true, true},
765 .supports_rgmii = {true, true, true, true, true},
766 .supports_sgmii = {false, false, false, false, true},
770 const struct sja1105_info sja1110a_info = {
771 .device_id = SJA1110_DEVICE_ID,
772 .part_no = SJA1110A_PART_NO,
773 .static_ops = sja1110_table_ops,
774 .dyn_ops = sja1110_dyn_ops,
775 .regs = &sja1110_regs,
776 .qinq_tpid = ETH_P_8021AD,
777 .tag_proto = DSA_TAG_PROTO_SJA1110,
778 .can_limit_mcast_flood = true,
779 .multiple_cascade_ports = true,
781 .ptpegr_ts_bytes = 8,
782 .max_frame_mem = SJA1110_MAX_FRAME_MEMORY,
783 .num_ports = SJA1110_NUM_PORTS,
784 .num_cbs_shapers = SJA1110_MAX_CBS_COUNT,
785 .setup_rgmii_delay = sja1110_setup_rgmii_delay,
786 .reset_cmd = sja1110_reset_cmd,
787 .fdb_add_cmd = sja1105pqrs_fdb_add,
788 .fdb_del_cmd = sja1105pqrs_fdb_del,
789 .ptp_cmd_packing = sja1105pqrs_ptp_cmd_packing,
790 .rxtstamp = sja1110_rxtstamp,
791 .txtstamp = sja1110_txtstamp,
792 .clocking_setup = sja1110_clocking_setup,
794 [SJA1105_SPEED_AUTO] = 0,
795 [SJA1105_SPEED_10MBPS] = 4,
796 [SJA1105_SPEED_100MBPS] = 3,
797 [SJA1105_SPEED_1000MBPS] = 2,
798 [SJA1105_SPEED_2500MBPS] = 1,
800 .supports_mii = {true, true, true, true, false,
801 true, true, true, true, true, true},
802 .supports_rmii = {false, false, true, true, false,
803 false, false, false, false, false, false},
804 .supports_rgmii = {false, false, true, true, false,
805 false, false, false, false, false, false},
806 .supports_sgmii = {false, true, true, true, true,
807 false, false, false, false, false, false},
808 .supports_2500basex = {false, false, false, true, true,
809 false, false, false, false, false, false},
810 .internal_phy = {SJA1105_NO_PHY, SJA1105_PHY_BASE_TX,
811 SJA1105_NO_PHY, SJA1105_NO_PHY,
812 SJA1105_NO_PHY, SJA1105_PHY_BASE_T1,
813 SJA1105_PHY_BASE_T1, SJA1105_PHY_BASE_T1,
814 SJA1105_PHY_BASE_T1, SJA1105_PHY_BASE_T1,
815 SJA1105_PHY_BASE_T1},
819 const struct sja1105_info sja1110b_info = {
820 .device_id = SJA1110_DEVICE_ID,
821 .part_no = SJA1110B_PART_NO,
822 .static_ops = sja1110_table_ops,
823 .dyn_ops = sja1110_dyn_ops,
824 .regs = &sja1110_regs,
825 .qinq_tpid = ETH_P_8021AD,
826 .tag_proto = DSA_TAG_PROTO_SJA1110,
827 .can_limit_mcast_flood = true,
828 .multiple_cascade_ports = true,
830 .ptpegr_ts_bytes = 8,
831 .max_frame_mem = SJA1110_MAX_FRAME_MEMORY,
832 .num_ports = SJA1110_NUM_PORTS,
833 .num_cbs_shapers = SJA1110_MAX_CBS_COUNT,
834 .setup_rgmii_delay = sja1110_setup_rgmii_delay,
835 .reset_cmd = sja1110_reset_cmd,
836 .fdb_add_cmd = sja1105pqrs_fdb_add,
837 .fdb_del_cmd = sja1105pqrs_fdb_del,
838 .ptp_cmd_packing = sja1105pqrs_ptp_cmd_packing,
839 .rxtstamp = sja1110_rxtstamp,
840 .txtstamp = sja1110_txtstamp,
841 .clocking_setup = sja1110_clocking_setup,
843 [SJA1105_SPEED_AUTO] = 0,
844 [SJA1105_SPEED_10MBPS] = 4,
845 [SJA1105_SPEED_100MBPS] = 3,
846 [SJA1105_SPEED_1000MBPS] = 2,
847 [SJA1105_SPEED_2500MBPS] = 1,
849 .supports_mii = {true, true, true, true, false,
850 true, true, true, true, true, false},
851 .supports_rmii = {false, false, true, true, false,
852 false, false, false, false, false, false},
853 .supports_rgmii = {false, false, true, true, false,
854 false, false, false, false, false, false},
855 .supports_sgmii = {false, false, false, true, true,
856 false, false, false, false, false, false},
857 .supports_2500basex = {false, false, false, true, true,
858 false, false, false, false, false, false},
859 .internal_phy = {SJA1105_NO_PHY, SJA1105_PHY_BASE_TX,
860 SJA1105_NO_PHY, SJA1105_NO_PHY,
861 SJA1105_NO_PHY, SJA1105_PHY_BASE_T1,
862 SJA1105_PHY_BASE_T1, SJA1105_PHY_BASE_T1,
863 SJA1105_PHY_BASE_T1, SJA1105_PHY_BASE_T1,
868 const struct sja1105_info sja1110c_info = {
869 .device_id = SJA1110_DEVICE_ID,
870 .part_no = SJA1110C_PART_NO,
871 .static_ops = sja1110_table_ops,
872 .dyn_ops = sja1110_dyn_ops,
873 .regs = &sja1110_regs,
874 .qinq_tpid = ETH_P_8021AD,
875 .tag_proto = DSA_TAG_PROTO_SJA1110,
876 .can_limit_mcast_flood = true,
877 .multiple_cascade_ports = true,
879 .ptpegr_ts_bytes = 8,
880 .max_frame_mem = SJA1110_MAX_FRAME_MEMORY,
881 .num_ports = SJA1110_NUM_PORTS,
882 .num_cbs_shapers = SJA1110_MAX_CBS_COUNT,
883 .setup_rgmii_delay = sja1110_setup_rgmii_delay,
884 .reset_cmd = sja1110_reset_cmd,
885 .fdb_add_cmd = sja1105pqrs_fdb_add,
886 .fdb_del_cmd = sja1105pqrs_fdb_del,
887 .ptp_cmd_packing = sja1105pqrs_ptp_cmd_packing,
888 .rxtstamp = sja1110_rxtstamp,
889 .txtstamp = sja1110_txtstamp,
890 .clocking_setup = sja1110_clocking_setup,
892 [SJA1105_SPEED_AUTO] = 0,
893 [SJA1105_SPEED_10MBPS] = 4,
894 [SJA1105_SPEED_100MBPS] = 3,
895 [SJA1105_SPEED_1000MBPS] = 2,
896 [SJA1105_SPEED_2500MBPS] = 1,
898 .supports_mii = {true, true, true, true, false,
899 true, true, true, false, false, false},
900 .supports_rmii = {false, false, true, true, false,
901 false, false, false, false, false, false},
902 .supports_rgmii = {false, false, true, true, false,
903 false, false, false, false, false, false},
904 .supports_sgmii = {false, false, false, false, true,
905 false, false, false, false, false, false},
906 .supports_2500basex = {false, false, false, false, true,
907 false, false, false, false, false, false},
908 .internal_phy = {SJA1105_NO_PHY, SJA1105_PHY_BASE_TX,
909 SJA1105_NO_PHY, SJA1105_NO_PHY,
910 SJA1105_NO_PHY, SJA1105_PHY_BASE_T1,
911 SJA1105_PHY_BASE_T1, SJA1105_PHY_BASE_T1,
912 SJA1105_NO_PHY, SJA1105_NO_PHY,
917 const struct sja1105_info sja1110d_info = {
918 .device_id = SJA1110_DEVICE_ID,
919 .part_no = SJA1110D_PART_NO,
920 .static_ops = sja1110_table_ops,
921 .dyn_ops = sja1110_dyn_ops,
922 .regs = &sja1110_regs,
923 .qinq_tpid = ETH_P_8021AD,
924 .tag_proto = DSA_TAG_PROTO_SJA1110,
925 .can_limit_mcast_flood = true,
926 .multiple_cascade_ports = true,
928 .ptpegr_ts_bytes = 8,
929 .max_frame_mem = SJA1110_MAX_FRAME_MEMORY,
930 .num_ports = SJA1110_NUM_PORTS,
931 .num_cbs_shapers = SJA1110_MAX_CBS_COUNT,
932 .setup_rgmii_delay = sja1110_setup_rgmii_delay,
933 .reset_cmd = sja1110_reset_cmd,
934 .fdb_add_cmd = sja1105pqrs_fdb_add,
935 .fdb_del_cmd = sja1105pqrs_fdb_del,
936 .ptp_cmd_packing = sja1105pqrs_ptp_cmd_packing,
937 .rxtstamp = sja1110_rxtstamp,
938 .txtstamp = sja1110_txtstamp,
939 .clocking_setup = sja1110_clocking_setup,
941 [SJA1105_SPEED_AUTO] = 0,
942 [SJA1105_SPEED_10MBPS] = 4,
943 [SJA1105_SPEED_100MBPS] = 3,
944 [SJA1105_SPEED_1000MBPS] = 2,
945 [SJA1105_SPEED_2500MBPS] = 1,
947 .supports_mii = {true, false, true, false, false,
948 true, true, true, false, false, false},
949 .supports_rmii = {false, false, true, false, false,
950 false, false, false, false, false, false},
951 .supports_rgmii = {false, false, true, false, false,
952 false, false, false, false, false, false},
953 .supports_sgmii = {false, true, true, true, true,
954 false, false, false, false, false, false},
955 .internal_phy = {SJA1105_NO_PHY, SJA1105_NO_PHY,
956 SJA1105_NO_PHY, SJA1105_NO_PHY,
957 SJA1105_NO_PHY, SJA1105_PHY_BASE_T1,
958 SJA1105_PHY_BASE_T1, SJA1105_PHY_BASE_T1,
959 SJA1105_NO_PHY, SJA1105_NO_PHY,