1 // SPDX-License-Identifier: BSD-3-Clause
2 /* Copyright (c) 2016-2018, NXP Semiconductors
3 * Copyright (c) 2018, Sensor-Technik Wiedemann GmbH
4 * Copyright (c) 2018-2019, Vladimir Oltean <olteanv@gmail.com>
6 #include <linux/spi/spi.h>
7 #include <linux/packing.h>
10 struct sja1105_chunk {
17 sja1105_spi_message_pack(void *buf, const struct sja1105_spi_message *msg)
19 const int size = SJA1105_SIZE_SPI_MSG_HEADER;
23 sja1105_pack(buf, &msg->access, 31, 31, size);
24 sja1105_pack(buf, &msg->read_count, 30, 25, size);
25 sja1105_pack(buf, &msg->address, 24, 4, size);
29 * - SPI_WRITE: creates and sends an SPI write message at absolute
30 * address reg_addr, taking @len bytes from *buf
31 * - SPI_READ: creates and sends an SPI read message from absolute
32 * address reg_addr, writing @len bytes into *buf
34 static int sja1105_xfer(const struct sja1105_private *priv,
35 sja1105_spi_rw_mode_t rw, u64 reg_addr, u8 *buf,
36 size_t len, struct ptp_system_timestamp *ptp_sts)
38 u8 hdr_buf[SJA1105_SIZE_SPI_MSG_HEADER] = {0};
39 struct spi_device *spi = priv->spidev;
40 struct spi_transfer xfers[2] = {0};
41 struct spi_transfer *chunk_xfer;
42 struct spi_transfer *hdr_xfer;
43 struct sja1105_chunk chunk;
47 num_chunks = DIV_ROUND_UP(len, priv->max_xfer_len);
49 chunk.reg_addr = reg_addr;
51 chunk.len = min_t(size_t, len, priv->max_xfer_len);
54 chunk_xfer = &xfers[1];
56 for (i = 0; i < num_chunks; i++) {
57 struct spi_transfer *ptp_sts_xfer;
58 struct sja1105_spi_message msg;
60 /* Populate the transfer's header buffer */
61 msg.address = chunk.reg_addr;
64 msg.read_count = chunk.len / 4;
68 sja1105_spi_message_pack(hdr_buf, &msg);
69 hdr_xfer->tx_buf = hdr_buf;
70 hdr_xfer->len = SJA1105_SIZE_SPI_MSG_HEADER;
72 /* Populate the transfer's data buffer */
74 chunk_xfer->rx_buf = chunk.buf;
76 chunk_xfer->tx_buf = chunk.buf;
77 chunk_xfer->len = chunk.len;
79 /* Request timestamping for the transfer. Instead of letting
80 * callers specify which byte they want to timestamp, we can
81 * make certain assumptions:
82 * - A read operation will request a software timestamp when
83 * what's being read is the PTP time. That is snapshotted by
84 * the switch hardware at the end of the command portion
86 * - A write operation will request a software timestamp on
87 * actions that modify the PTP time. Taking clock stepping as
88 * an example, the switch writes the PTP time at the end of
89 * the data portion (chunk_xfer).
92 ptp_sts_xfer = hdr_xfer;
94 ptp_sts_xfer = chunk_xfer;
95 ptp_sts_xfer->ptp_sts_word_pre = ptp_sts_xfer->len - 1;
96 ptp_sts_xfer->ptp_sts_word_post = ptp_sts_xfer->len - 1;
97 ptp_sts_xfer->ptp_sts = ptp_sts;
99 /* Calculate next chunk */
100 chunk.buf += chunk.len;
101 chunk.reg_addr += chunk.len / 4;
102 chunk.len = min_t(size_t, (ptrdiff_t)(buf + len - chunk.buf),
105 rc = spi_sync_transfer(spi, xfers, 2);
107 dev_err(&spi->dev, "SPI transfer failed: %d\n", rc);
115 int sja1105_xfer_buf(const struct sja1105_private *priv,
116 sja1105_spi_rw_mode_t rw, u64 reg_addr,
119 return sja1105_xfer(priv, rw, reg_addr, buf, len, NULL);
123 * - SPI_WRITE: creates and sends an SPI write message at absolute
125 * - SPI_READ: creates and sends an SPI read message from absolute
128 * The u64 *value is unpacked, meaning that it's stored in the native
129 * CPU endianness and directly usable by software running on the core.
131 int sja1105_xfer_u64(const struct sja1105_private *priv,
132 sja1105_spi_rw_mode_t rw, u64 reg_addr, u64 *value,
133 struct ptp_system_timestamp *ptp_sts)
139 sja1105_pack(packed_buf, value, 63, 0, 8);
141 rc = sja1105_xfer(priv, rw, reg_addr, packed_buf, 8, ptp_sts);
144 sja1105_unpack(packed_buf, value, 63, 0, 8);
149 /* Same as above, but transfers only a 4 byte word */
150 int sja1105_xfer_u32(const struct sja1105_private *priv,
151 sja1105_spi_rw_mode_t rw, u64 reg_addr, u32 *value,
152 struct ptp_system_timestamp *ptp_sts)
158 if (rw == SPI_WRITE) {
159 /* The packing API only supports u64 as CPU word size,
160 * so we need to convert.
163 sja1105_pack(packed_buf, &tmp, 31, 0, 4);
166 rc = sja1105_xfer(priv, rw, reg_addr, packed_buf, 4, ptp_sts);
168 if (rw == SPI_READ) {
169 sja1105_unpack(packed_buf, &tmp, 31, 0, 4);
176 static int sja1105et_reset_cmd(struct dsa_switch *ds)
178 struct sja1105_private *priv = ds->priv;
179 const struct sja1105_regs *regs = priv->info->regs;
180 u32 cold_reset = BIT(3);
183 return sja1105_xfer_u32(priv, SPI_WRITE, regs->rgu, &cold_reset, NULL);
186 static int sja1105pqrs_reset_cmd(struct dsa_switch *ds)
188 struct sja1105_private *priv = ds->priv;
189 const struct sja1105_regs *regs = priv->info->regs;
190 u32 cold_reset = BIT(2);
193 return sja1105_xfer_u32(priv, SPI_WRITE, regs->rgu, &cold_reset, NULL);
196 static int sja1110_reset_cmd(struct dsa_switch *ds)
198 struct sja1105_private *priv = ds->priv;
199 const struct sja1105_regs *regs = priv->info->regs;
200 u32 switch_reset = BIT(20);
202 /* Switch core reset */
203 return sja1105_xfer_u32(priv, SPI_WRITE, regs->rgu, &switch_reset, NULL);
206 int sja1105_inhibit_tx(const struct sja1105_private *priv,
207 unsigned long port_bitmap, bool tx_inhibited)
209 const struct sja1105_regs *regs = priv->info->regs;
213 rc = sja1105_xfer_u32(priv, SPI_READ, regs->port_control,
219 inhibit_cmd |= port_bitmap;
221 inhibit_cmd &= ~port_bitmap;
223 return sja1105_xfer_u32(priv, SPI_WRITE, regs->port_control,
227 struct sja1105_status {
234 /* This is not reading the entire General Status area, which is also
235 * divergent between E/T and P/Q/R/S, but only the relevant bits for
236 * ensuring that the static config upload procedure was successful.
238 static void sja1105_status_unpack(void *buf, struct sja1105_status *status)
240 /* So that addition translates to 4 bytes */
243 /* device_id is missing from the buffer, but we don't
244 * want to diverge from the manual definition of the
245 * register addresses, so we'll back off one step with
246 * the register pointer, and never access p[0].
249 sja1105_unpack(p + 0x1, &status->configs, 31, 31, 4);
250 sja1105_unpack(p + 0x1, &status->crcchkl, 30, 30, 4);
251 sja1105_unpack(p + 0x1, &status->ids, 29, 29, 4);
252 sja1105_unpack(p + 0x1, &status->crcchkg, 28, 28, 4);
255 static int sja1105_status_get(struct sja1105_private *priv,
256 struct sja1105_status *status)
258 const struct sja1105_regs *regs = priv->info->regs;
262 rc = sja1105_xfer_buf(priv, SPI_READ, regs->status, packed_buf, 4);
266 sja1105_status_unpack(packed_buf, status);
271 /* Not const because unpacking priv->static_config into buffers and preparing
272 * for upload requires the recalculation of table CRCs and updating the
273 * structures with these.
275 int static_config_buf_prepare_for_upload(struct sja1105_private *priv,
276 void *config_buf, int buf_len)
278 struct sja1105_static_config *config = &priv->static_config;
279 struct sja1105_table_header final_header;
280 sja1105_config_valid_t valid;
281 char *final_header_ptr;
284 valid = sja1105_static_config_check_valid(config,
285 priv->info->max_frame_mem);
286 if (valid != SJA1105_CONFIG_OK) {
287 dev_err(&priv->spidev->dev,
288 sja1105_static_config_error_msg[valid]);
292 /* Write Device ID and config tables to config_buf */
293 sja1105_static_config_pack(config_buf, config);
294 /* Recalculate CRC of the last header (right now 0xDEADBEEF).
295 * Don't include the CRC field itself.
297 crc_len = buf_len - 4;
298 /* Read the whole table header */
299 final_header_ptr = config_buf + buf_len - SJA1105_SIZE_TABLE_HEADER;
300 sja1105_table_header_packing(final_header_ptr, &final_header, UNPACK);
302 final_header.crc = sja1105_crc32(config_buf, crc_len);
304 sja1105_table_header_packing(final_header_ptr, &final_header, PACK);
311 int sja1105_static_config_upload(struct sja1105_private *priv)
313 struct sja1105_static_config *config = &priv->static_config;
314 const struct sja1105_regs *regs = priv->info->regs;
315 struct device *dev = &priv->spidev->dev;
316 struct dsa_switch *ds = priv->ds;
317 struct sja1105_status status;
318 int rc, retries = RETRIES;
322 buf_len = sja1105_static_config_get_length(config);
323 config_buf = kcalloc(buf_len, sizeof(char), GFP_KERNEL);
327 rc = static_config_buf_prepare_for_upload(priv, config_buf, buf_len);
329 dev_err(dev, "Invalid config, cannot upload\n");
333 /* Prevent PHY jabbering during switch reset by inhibiting
334 * Tx on all ports and waiting for current packet to drain.
335 * Otherwise, the PHY will see an unterminated Ethernet packet.
337 rc = sja1105_inhibit_tx(priv, GENMASK_ULL(ds->num_ports - 1, 0), true);
339 dev_err(dev, "Failed to inhibit Tx on ports\n");
343 /* Wait for an eventual egress packet to finish transmission
344 * (reach IFG). It is guaranteed that a second one will not
345 * follow, and that switch cold reset is thus safe
347 usleep_range(500, 1000);
349 /* Put the SJA1105 in programming mode */
350 rc = priv->info->reset_cmd(priv->ds);
352 dev_err(dev, "Failed to reset switch, retrying...\n");
355 /* Wait for the switch to come out of reset */
356 usleep_range(1000, 5000);
357 /* Upload the static config to the device */
358 rc = sja1105_xfer_buf(priv, SPI_WRITE, regs->config,
359 config_buf, buf_len);
361 dev_err(dev, "Failed to upload config, retrying...\n");
364 /* Check that SJA1105 responded well to the config upload */
365 rc = sja1105_status_get(priv, &status);
369 if (status.ids == 1) {
370 dev_err(dev, "Mismatch between hardware and static config "
371 "device id. Wrote 0x%llx, wants 0x%llx\n",
372 config->device_id, priv->info->device_id);
375 if (status.crcchkl == 1) {
376 dev_err(dev, "Switch reported invalid local CRC on "
377 "the uploaded config, retrying...\n");
380 if (status.crcchkg == 1) {
381 dev_err(dev, "Switch reported invalid global CRC on "
382 "the uploaded config, retrying...\n");
385 if (status.configs == 0) {
386 dev_err(dev, "Switch reported that configuration is "
387 "invalid, retrying...\n");
396 dev_err(dev, "Failed to upload config to device, giving up\n");
398 } else if (retries != RETRIES) {
399 dev_info(dev, "Succeeded after %d tried\n", RETRIES - retries);
407 static struct sja1105_regs sja1105et_regs = {
411 .port_control = 0x11,
412 .vl_status = 0x10000,
415 /* UM10944.pdf, Table 86, ACU Register overview */
416 .pad_mii_tx = {0x100800, 0x100802, 0x100804, 0x100806, 0x100808},
417 .pad_mii_rx = {0x100801, 0x100803, 0x100805, 0x100807, 0x100809},
418 .rmii_pll1 = 0x10000A,
419 .cgu_idiv = {0x10000B, 0x10000C, 0x10000D, 0x10000E, 0x10000F},
420 .stats[MAC] = {0x200, 0x202, 0x204, 0x206, 0x208},
421 .stats[HL1] = {0x400, 0x410, 0x420, 0x430, 0x440},
422 .stats[HL2] = {0x600, 0x610, 0x620, 0x630, 0x640},
423 /* UM10944.pdf, Table 78, CGU Register overview */
424 .mii_tx_clk = {0x100013, 0x10001A, 0x100021, 0x100028, 0x10002F},
425 .mii_rx_clk = {0x100014, 0x10001B, 0x100022, 0x100029, 0x100030},
426 .mii_ext_tx_clk = {0x100018, 0x10001F, 0x100026, 0x10002D, 0x100034},
427 .mii_ext_rx_clk = {0x100019, 0x100020, 0x100027, 0x10002E, 0x100035},
428 .rgmii_tx_clk = {0x100016, 0x10001D, 0x100024, 0x10002B, 0x100032},
429 .rmii_ref_clk = {0x100015, 0x10001C, 0x100023, 0x10002A, 0x100031},
430 .rmii_ext_tx_clk = {0x100018, 0x10001F, 0x100026, 0x10002D, 0x100034},
431 .ptpegr_ts = {0xC0, 0xC2, 0xC4, 0xC6, 0xC8},
432 .ptpschtm = 0x12, /* Spans 0x12 to 0x13 */
436 .ptpclkval = 0x18, /* Spans 0x18 to 0x19 */
441 static struct sja1105_regs sja1105pqrs_regs = {
445 .port_control = 0x12,
446 .vl_status = 0x10000,
449 /* UM10944.pdf, Table 86, ACU Register overview */
450 .pad_mii_tx = {0x100800, 0x100802, 0x100804, 0x100806, 0x100808},
451 .pad_mii_rx = {0x100801, 0x100803, 0x100805, 0x100807, 0x100809},
452 .pad_mii_id = {0x100810, 0x100811, 0x100812, 0x100813, 0x100814},
453 .rmii_pll1 = 0x10000A,
454 .cgu_idiv = {0x10000B, 0x10000C, 0x10000D, 0x10000E, 0x10000F},
455 .stats[MAC] = {0x200, 0x202, 0x204, 0x206, 0x208},
456 .stats[HL1] = {0x400, 0x410, 0x420, 0x430, 0x440},
457 .stats[HL2] = {0x600, 0x610, 0x620, 0x630, 0x640},
458 .stats[ETHER] = {0x1400, 0x1418, 0x1430, 0x1448, 0x1460},
459 /* UM11040.pdf, Table 114 */
460 .mii_tx_clk = {0x100013, 0x100019, 0x10001F, 0x100025, 0x10002B},
461 .mii_rx_clk = {0x100014, 0x10001A, 0x100020, 0x100026, 0x10002C},
462 .mii_ext_tx_clk = {0x100017, 0x10001D, 0x100023, 0x100029, 0x10002F},
463 .mii_ext_rx_clk = {0x100018, 0x10001E, 0x100024, 0x10002A, 0x100030},
464 .rgmii_tx_clk = {0x100016, 0x10001C, 0x100022, 0x100028, 0x10002E},
465 .rmii_ref_clk = {0x100015, 0x10001B, 0x100021, 0x100027, 0x10002D},
466 .rmii_ext_tx_clk = {0x100017, 0x10001D, 0x100023, 0x100029, 0x10002F},
467 .ptpegr_ts = {0xC0, 0xC4, 0xC8, 0xCC, 0xD0},
468 .ptpschtm = 0x13, /* Spans 0x13 to 0x14 */
478 static struct sja1105_regs sja1110_regs = {
479 .device_id = SJA1110_SPI_ADDR(0x0),
480 .prod_id = SJA1110_ACU_ADDR(0xf00),
481 .status = SJA1110_SPI_ADDR(0x4),
482 .port_control = SJA1110_SPI_ADDR(0x50), /* actually INHIB_TX */
483 .vl_status = 0x10000,
485 .rgu = SJA1110_RGU_ADDR(0x100), /* Reset Control Register 0 */
486 /* Ports 2 and 3 are capable of xMII, but there isn't anything to
487 * configure in the CGU/ACU for them.
489 .pad_mii_tx = {SJA1105_RSV_ADDR, SJA1105_RSV_ADDR,
490 SJA1105_RSV_ADDR, SJA1105_RSV_ADDR,
491 SJA1105_RSV_ADDR, SJA1105_RSV_ADDR,
492 SJA1105_RSV_ADDR, SJA1105_RSV_ADDR,
493 SJA1105_RSV_ADDR, SJA1105_RSV_ADDR,
495 .pad_mii_rx = {SJA1105_RSV_ADDR, SJA1105_RSV_ADDR,
496 SJA1105_RSV_ADDR, SJA1105_RSV_ADDR,
497 SJA1105_RSV_ADDR, SJA1105_RSV_ADDR,
498 SJA1105_RSV_ADDR, SJA1105_RSV_ADDR,
499 SJA1105_RSV_ADDR, SJA1105_RSV_ADDR,
501 .pad_mii_id = {SJA1105_RSV_ADDR, SJA1105_RSV_ADDR,
502 SJA1110_ACU_ADDR(0x18), SJA1110_ACU_ADDR(0x28),
503 SJA1105_RSV_ADDR, SJA1105_RSV_ADDR,
504 SJA1105_RSV_ADDR, SJA1105_RSV_ADDR,
505 SJA1105_RSV_ADDR, SJA1105_RSV_ADDR,
507 .rmii_pll1 = SJA1105_RSV_ADDR,
508 .cgu_idiv = {SJA1105_RSV_ADDR, SJA1105_RSV_ADDR, SJA1105_RSV_ADDR,
509 SJA1105_RSV_ADDR, SJA1105_RSV_ADDR, SJA1105_RSV_ADDR,
510 SJA1105_RSV_ADDR, SJA1105_RSV_ADDR, SJA1105_RSV_ADDR,
511 SJA1105_RSV_ADDR, SJA1105_RSV_ADDR},
512 .stats[MAC] = {0x200, 0x202, 0x204, 0x206, 0x208, 0x20a,
513 0x20c, 0x20e, 0x210, 0x212, 0x214},
514 .stats[HL1] = {0x400, 0x410, 0x420, 0x430, 0x440, 0x450,
515 0x460, 0x470, 0x480, 0x490, 0x4a0},
516 .stats[HL2] = {0x600, 0x610, 0x620, 0x630, 0x640, 0x650,
517 0x660, 0x670, 0x680, 0x690, 0x6a0},
518 .stats[ETHER] = {0x1400, 0x1418, 0x1430, 0x1448, 0x1460, 0x1478,
519 0x1490, 0x14a8, 0x14c0, 0x14d8, 0x14f0},
520 .mii_tx_clk = {SJA1105_RSV_ADDR, SJA1105_RSV_ADDR, SJA1105_RSV_ADDR,
521 SJA1105_RSV_ADDR, SJA1105_RSV_ADDR, SJA1105_RSV_ADDR,
522 SJA1105_RSV_ADDR, SJA1105_RSV_ADDR, SJA1105_RSV_ADDR,
523 SJA1105_RSV_ADDR, SJA1105_RSV_ADDR},
524 .mii_rx_clk = {SJA1105_RSV_ADDR, SJA1105_RSV_ADDR, SJA1105_RSV_ADDR,
525 SJA1105_RSV_ADDR, SJA1105_RSV_ADDR, SJA1105_RSV_ADDR,
526 SJA1105_RSV_ADDR, SJA1105_RSV_ADDR, SJA1105_RSV_ADDR,
527 SJA1105_RSV_ADDR, SJA1105_RSV_ADDR},
528 .mii_ext_tx_clk = {SJA1105_RSV_ADDR, SJA1105_RSV_ADDR, SJA1105_RSV_ADDR,
529 SJA1105_RSV_ADDR, SJA1105_RSV_ADDR, SJA1105_RSV_ADDR,
530 SJA1105_RSV_ADDR, SJA1105_RSV_ADDR, SJA1105_RSV_ADDR,
531 SJA1105_RSV_ADDR, SJA1105_RSV_ADDR},
532 .mii_ext_rx_clk = {SJA1105_RSV_ADDR, SJA1105_RSV_ADDR, SJA1105_RSV_ADDR,
533 SJA1105_RSV_ADDR, SJA1105_RSV_ADDR, SJA1105_RSV_ADDR,
534 SJA1105_RSV_ADDR, SJA1105_RSV_ADDR, SJA1105_RSV_ADDR,
535 SJA1105_RSV_ADDR, SJA1105_RSV_ADDR},
536 .rgmii_tx_clk = {SJA1105_RSV_ADDR, SJA1105_RSV_ADDR, SJA1105_RSV_ADDR,
537 SJA1105_RSV_ADDR, SJA1105_RSV_ADDR, SJA1105_RSV_ADDR,
538 SJA1105_RSV_ADDR, SJA1105_RSV_ADDR, SJA1105_RSV_ADDR,
539 SJA1105_RSV_ADDR, SJA1105_RSV_ADDR},
540 .rmii_ref_clk = {SJA1105_RSV_ADDR, SJA1105_RSV_ADDR, SJA1105_RSV_ADDR,
541 SJA1105_RSV_ADDR, SJA1105_RSV_ADDR, SJA1105_RSV_ADDR,
542 SJA1105_RSV_ADDR, SJA1105_RSV_ADDR, SJA1105_RSV_ADDR,
543 SJA1105_RSV_ADDR, SJA1105_RSV_ADDR},
544 .rmii_ext_tx_clk = {SJA1105_RSV_ADDR, SJA1105_RSV_ADDR,
545 SJA1105_RSV_ADDR, SJA1105_RSV_ADDR,
546 SJA1105_RSV_ADDR, SJA1105_RSV_ADDR,
547 SJA1105_RSV_ADDR, SJA1105_RSV_ADDR,
548 SJA1105_RSV_ADDR, SJA1105_RSV_ADDR,
550 .ptpschtm = SJA1110_SPI_ADDR(0x54),
551 .ptppinst = SJA1110_SPI_ADDR(0x5c),
552 .ptppindur = SJA1110_SPI_ADDR(0x64),
553 .ptp_control = SJA1110_SPI_ADDR(0x68),
554 .ptpclkval = SJA1110_SPI_ADDR(0x6c),
555 .ptpclkrate = SJA1110_SPI_ADDR(0x74),
556 .ptpclkcorp = SJA1110_SPI_ADDR(0x80),
557 .ptpsyncts = SJA1110_SPI_ADDR(0x84),
560 const struct sja1105_info sja1105e_info = {
561 .device_id = SJA1105E_DEVICE_ID,
562 .part_no = SJA1105ET_PART_NO,
563 .static_ops = sja1105e_table_ops,
564 .dyn_ops = sja1105et_dyn_ops,
565 .qinq_tpid = ETH_P_8021Q,
566 .can_limit_mcast_flood = false,
568 .ptpegr_ts_bytes = 4,
569 .max_frame_mem = SJA1105_MAX_FRAME_MEMORY,
570 .num_ports = SJA1105_NUM_PORTS,
571 .num_cbs_shapers = SJA1105ET_MAX_CBS_COUNT,
572 .reset_cmd = sja1105et_reset_cmd,
573 .fdb_add_cmd = sja1105et_fdb_add,
574 .fdb_del_cmd = sja1105et_fdb_del,
575 .ptp_cmd_packing = sja1105et_ptp_cmd_packing,
576 .clocking_setup = sja1105_clocking_setup,
577 .regs = &sja1105et_regs,
579 [SJA1105_SPEED_AUTO] = 0,
580 [SJA1105_SPEED_10MBPS] = 3,
581 [SJA1105_SPEED_100MBPS] = 2,
582 [SJA1105_SPEED_1000MBPS] = 1,
583 [SJA1105_SPEED_2500MBPS] = 0, /* Not supported */
585 .supports_mii = {true, true, true, true, true},
586 .supports_rmii = {true, true, true, true, true},
587 .supports_rgmii = {true, true, true, true, true},
591 const struct sja1105_info sja1105t_info = {
592 .device_id = SJA1105T_DEVICE_ID,
593 .part_no = SJA1105ET_PART_NO,
594 .static_ops = sja1105t_table_ops,
595 .dyn_ops = sja1105et_dyn_ops,
596 .qinq_tpid = ETH_P_8021Q,
597 .can_limit_mcast_flood = false,
599 .ptpegr_ts_bytes = 4,
600 .max_frame_mem = SJA1105_MAX_FRAME_MEMORY,
601 .num_ports = SJA1105_NUM_PORTS,
602 .num_cbs_shapers = SJA1105ET_MAX_CBS_COUNT,
603 .reset_cmd = sja1105et_reset_cmd,
604 .fdb_add_cmd = sja1105et_fdb_add,
605 .fdb_del_cmd = sja1105et_fdb_del,
606 .ptp_cmd_packing = sja1105et_ptp_cmd_packing,
607 .clocking_setup = sja1105_clocking_setup,
608 .regs = &sja1105et_regs,
610 [SJA1105_SPEED_AUTO] = 0,
611 [SJA1105_SPEED_10MBPS] = 3,
612 [SJA1105_SPEED_100MBPS] = 2,
613 [SJA1105_SPEED_1000MBPS] = 1,
614 [SJA1105_SPEED_2500MBPS] = 0, /* Not supported */
616 .supports_mii = {true, true, true, true, true},
617 .supports_rmii = {true, true, true, true, true},
618 .supports_rgmii = {true, true, true, true, true},
622 const struct sja1105_info sja1105p_info = {
623 .device_id = SJA1105PR_DEVICE_ID,
624 .part_no = SJA1105P_PART_NO,
625 .static_ops = sja1105p_table_ops,
626 .dyn_ops = sja1105pqrs_dyn_ops,
627 .qinq_tpid = ETH_P_8021AD,
628 .can_limit_mcast_flood = true,
630 .ptpegr_ts_bytes = 8,
631 .max_frame_mem = SJA1105_MAX_FRAME_MEMORY,
632 .num_ports = SJA1105_NUM_PORTS,
633 .num_cbs_shapers = SJA1105PQRS_MAX_CBS_COUNT,
634 .setup_rgmii_delay = sja1105pqrs_setup_rgmii_delay,
635 .reset_cmd = sja1105pqrs_reset_cmd,
636 .fdb_add_cmd = sja1105pqrs_fdb_add,
637 .fdb_del_cmd = sja1105pqrs_fdb_del,
638 .ptp_cmd_packing = sja1105pqrs_ptp_cmd_packing,
639 .clocking_setup = sja1105_clocking_setup,
640 .regs = &sja1105pqrs_regs,
642 [SJA1105_SPEED_AUTO] = 0,
643 [SJA1105_SPEED_10MBPS] = 3,
644 [SJA1105_SPEED_100MBPS] = 2,
645 [SJA1105_SPEED_1000MBPS] = 1,
646 [SJA1105_SPEED_2500MBPS] = 0, /* Not supported */
648 .supports_mii = {true, true, true, true, true},
649 .supports_rmii = {true, true, true, true, true},
650 .supports_rgmii = {true, true, true, true, true},
654 const struct sja1105_info sja1105q_info = {
655 .device_id = SJA1105QS_DEVICE_ID,
656 .part_no = SJA1105Q_PART_NO,
657 .static_ops = sja1105q_table_ops,
658 .dyn_ops = sja1105pqrs_dyn_ops,
659 .qinq_tpid = ETH_P_8021AD,
660 .can_limit_mcast_flood = true,
662 .ptpegr_ts_bytes = 8,
663 .max_frame_mem = SJA1105_MAX_FRAME_MEMORY,
664 .num_ports = SJA1105_NUM_PORTS,
665 .num_cbs_shapers = SJA1105PQRS_MAX_CBS_COUNT,
666 .setup_rgmii_delay = sja1105pqrs_setup_rgmii_delay,
667 .reset_cmd = sja1105pqrs_reset_cmd,
668 .fdb_add_cmd = sja1105pqrs_fdb_add,
669 .fdb_del_cmd = sja1105pqrs_fdb_del,
670 .ptp_cmd_packing = sja1105pqrs_ptp_cmd_packing,
671 .clocking_setup = sja1105_clocking_setup,
672 .regs = &sja1105pqrs_regs,
674 [SJA1105_SPEED_AUTO] = 0,
675 [SJA1105_SPEED_10MBPS] = 3,
676 [SJA1105_SPEED_100MBPS] = 2,
677 [SJA1105_SPEED_1000MBPS] = 1,
678 [SJA1105_SPEED_2500MBPS] = 0, /* Not supported */
680 .supports_mii = {true, true, true, true, true},
681 .supports_rmii = {true, true, true, true, true},
682 .supports_rgmii = {true, true, true, true, true},
686 const struct sja1105_info sja1105r_info = {
687 .device_id = SJA1105PR_DEVICE_ID,
688 .part_no = SJA1105R_PART_NO,
689 .static_ops = sja1105r_table_ops,
690 .dyn_ops = sja1105pqrs_dyn_ops,
691 .qinq_tpid = ETH_P_8021AD,
692 .can_limit_mcast_flood = true,
694 .ptpegr_ts_bytes = 8,
695 .max_frame_mem = SJA1105_MAX_FRAME_MEMORY,
696 .num_ports = SJA1105_NUM_PORTS,
697 .num_cbs_shapers = SJA1105PQRS_MAX_CBS_COUNT,
698 .setup_rgmii_delay = sja1105pqrs_setup_rgmii_delay,
699 .reset_cmd = sja1105pqrs_reset_cmd,
700 .fdb_add_cmd = sja1105pqrs_fdb_add,
701 .fdb_del_cmd = sja1105pqrs_fdb_del,
702 .ptp_cmd_packing = sja1105pqrs_ptp_cmd_packing,
703 .clocking_setup = sja1105_clocking_setup,
704 .regs = &sja1105pqrs_regs,
706 [SJA1105_SPEED_AUTO] = 0,
707 [SJA1105_SPEED_10MBPS] = 3,
708 [SJA1105_SPEED_100MBPS] = 2,
709 [SJA1105_SPEED_1000MBPS] = 1,
710 [SJA1105_SPEED_2500MBPS] = 0, /* Not supported */
712 .supports_mii = {true, true, true, true, true},
713 .supports_rmii = {true, true, true, true, true},
714 .supports_rgmii = {true, true, true, true, true},
715 .supports_sgmii = {false, false, false, false, true},
719 const struct sja1105_info sja1105s_info = {
720 .device_id = SJA1105QS_DEVICE_ID,
721 .part_no = SJA1105S_PART_NO,
722 .static_ops = sja1105s_table_ops,
723 .dyn_ops = sja1105pqrs_dyn_ops,
724 .regs = &sja1105pqrs_regs,
725 .qinq_tpid = ETH_P_8021AD,
726 .can_limit_mcast_flood = true,
728 .ptpegr_ts_bytes = 8,
729 .max_frame_mem = SJA1105_MAX_FRAME_MEMORY,
730 .num_ports = SJA1105_NUM_PORTS,
731 .num_cbs_shapers = SJA1105PQRS_MAX_CBS_COUNT,
732 .setup_rgmii_delay = sja1105pqrs_setup_rgmii_delay,
733 .reset_cmd = sja1105pqrs_reset_cmd,
734 .fdb_add_cmd = sja1105pqrs_fdb_add,
735 .fdb_del_cmd = sja1105pqrs_fdb_del,
736 .ptp_cmd_packing = sja1105pqrs_ptp_cmd_packing,
737 .clocking_setup = sja1105_clocking_setup,
739 [SJA1105_SPEED_AUTO] = 0,
740 [SJA1105_SPEED_10MBPS] = 3,
741 [SJA1105_SPEED_100MBPS] = 2,
742 [SJA1105_SPEED_1000MBPS] = 1,
743 [SJA1105_SPEED_2500MBPS] = 0, /* Not supported */
745 .supports_mii = {true, true, true, true, true},
746 .supports_rmii = {true, true, true, true, true},
747 .supports_rgmii = {true, true, true, true, true},
748 .supports_sgmii = {false, false, false, false, true},
752 const struct sja1105_info sja1110a_info = {
753 .device_id = SJA1110_DEVICE_ID,
754 .part_no = SJA1110A_PART_NO,
755 .static_ops = sja1110_table_ops,
756 .dyn_ops = sja1110_dyn_ops,
757 .regs = &sja1110_regs,
758 .qinq_tpid = ETH_P_8021AD,
759 .can_limit_mcast_flood = true,
761 .ptpegr_ts_bytes = 8,
762 .max_frame_mem = SJA1110_MAX_FRAME_MEMORY,
763 .num_ports = SJA1110_NUM_PORTS,
764 .num_cbs_shapers = SJA1110_MAX_CBS_COUNT,
765 .setup_rgmii_delay = sja1110_setup_rgmii_delay,
766 .reset_cmd = sja1110_reset_cmd,
767 .fdb_add_cmd = sja1105pqrs_fdb_add,
768 .fdb_del_cmd = sja1105pqrs_fdb_del,
769 .ptp_cmd_packing = sja1105pqrs_ptp_cmd_packing,
770 .clocking_setup = sja1110_clocking_setup,
772 [SJA1105_SPEED_AUTO] = 0,
773 [SJA1105_SPEED_10MBPS] = 4,
774 [SJA1105_SPEED_100MBPS] = 3,
775 [SJA1105_SPEED_1000MBPS] = 2,
776 [SJA1105_SPEED_2500MBPS] = 1,
778 .supports_mii = {true, true, true, true, false,
779 true, true, true, true, true, true},
780 .supports_rmii = {false, false, true, true, false,
781 false, false, false, false, false, false},
782 .supports_rgmii = {false, false, true, true, false,
783 false, false, false, false, false, false},
784 .supports_sgmii = {false, true, true, true, true,
785 false, false, false, false, false, false},
786 .supports_2500basex = {false, false, false, true, true,
787 false, false, false, false, false, false},
791 const struct sja1105_info sja1110b_info = {
792 .device_id = SJA1110_DEVICE_ID,
793 .part_no = SJA1110B_PART_NO,
794 .static_ops = sja1110_table_ops,
795 .dyn_ops = sja1110_dyn_ops,
796 .regs = &sja1110_regs,
797 .qinq_tpid = ETH_P_8021AD,
798 .can_limit_mcast_flood = true,
800 .ptpegr_ts_bytes = 8,
801 .max_frame_mem = SJA1110_MAX_FRAME_MEMORY,
802 .num_ports = SJA1110_NUM_PORTS,
803 .num_cbs_shapers = SJA1110_MAX_CBS_COUNT,
804 .setup_rgmii_delay = sja1110_setup_rgmii_delay,
805 .reset_cmd = sja1110_reset_cmd,
806 .fdb_add_cmd = sja1105pqrs_fdb_add,
807 .fdb_del_cmd = sja1105pqrs_fdb_del,
808 .ptp_cmd_packing = sja1105pqrs_ptp_cmd_packing,
809 .clocking_setup = sja1110_clocking_setup,
811 [SJA1105_SPEED_AUTO] = 0,
812 [SJA1105_SPEED_10MBPS] = 4,
813 [SJA1105_SPEED_100MBPS] = 3,
814 [SJA1105_SPEED_1000MBPS] = 2,
815 [SJA1105_SPEED_2500MBPS] = 1,
817 .supports_mii = {true, true, true, true, false,
818 true, true, true, true, true, false},
819 .supports_rmii = {false, false, true, true, false,
820 false, false, false, false, false, false},
821 .supports_rgmii = {false, false, true, true, false,
822 false, false, false, false, false, false},
823 .supports_sgmii = {false, false, false, true, true,
824 false, false, false, false, false, false},
825 .supports_2500basex = {false, false, false, true, true,
826 false, false, false, false, false, false},
830 const struct sja1105_info sja1110c_info = {
831 .device_id = SJA1110_DEVICE_ID,
832 .part_no = SJA1110C_PART_NO,
833 .static_ops = sja1110_table_ops,
834 .dyn_ops = sja1110_dyn_ops,
835 .regs = &sja1110_regs,
836 .qinq_tpid = ETH_P_8021AD,
837 .can_limit_mcast_flood = true,
839 .ptpegr_ts_bytes = 8,
840 .max_frame_mem = SJA1110_MAX_FRAME_MEMORY,
841 .num_ports = SJA1110_NUM_PORTS,
842 .num_cbs_shapers = SJA1110_MAX_CBS_COUNT,
843 .setup_rgmii_delay = sja1110_setup_rgmii_delay,
844 .reset_cmd = sja1110_reset_cmd,
845 .fdb_add_cmd = sja1105pqrs_fdb_add,
846 .fdb_del_cmd = sja1105pqrs_fdb_del,
847 .ptp_cmd_packing = sja1105pqrs_ptp_cmd_packing,
848 .clocking_setup = sja1110_clocking_setup,
850 [SJA1105_SPEED_AUTO] = 0,
851 [SJA1105_SPEED_10MBPS] = 4,
852 [SJA1105_SPEED_100MBPS] = 3,
853 [SJA1105_SPEED_1000MBPS] = 2,
854 [SJA1105_SPEED_2500MBPS] = 1,
856 .supports_mii = {true, true, true, true, false,
857 true, true, true, false, false, false},
858 .supports_rmii = {false, false, true, true, false,
859 false, false, false, false, false, false},
860 .supports_rgmii = {false, false, true, true, false,
861 false, false, false, false, false, false},
862 .supports_sgmii = {false, false, false, false, true,
863 false, false, false, false, false, false},
864 .supports_2500basex = {false, false, false, false, true,
865 false, false, false, false, false, false},
869 const struct sja1105_info sja1110d_info = {
870 .device_id = SJA1110_DEVICE_ID,
871 .part_no = SJA1110D_PART_NO,
872 .static_ops = sja1110_table_ops,
873 .dyn_ops = sja1110_dyn_ops,
874 .regs = &sja1110_regs,
875 .qinq_tpid = ETH_P_8021AD,
876 .can_limit_mcast_flood = true,
878 .ptpegr_ts_bytes = 8,
879 .max_frame_mem = SJA1110_MAX_FRAME_MEMORY,
880 .num_ports = SJA1110_NUM_PORTS,
881 .num_cbs_shapers = SJA1110_MAX_CBS_COUNT,
882 .setup_rgmii_delay = sja1110_setup_rgmii_delay,
883 .reset_cmd = sja1110_reset_cmd,
884 .fdb_add_cmd = sja1105pqrs_fdb_add,
885 .fdb_del_cmd = sja1105pqrs_fdb_del,
886 .ptp_cmd_packing = sja1105pqrs_ptp_cmd_packing,
887 .clocking_setup = sja1110_clocking_setup,
889 [SJA1105_SPEED_AUTO] = 0,
890 [SJA1105_SPEED_10MBPS] = 4,
891 [SJA1105_SPEED_100MBPS] = 3,
892 [SJA1105_SPEED_1000MBPS] = 2,
893 [SJA1105_SPEED_2500MBPS] = 1,
895 .supports_mii = {true, false, true, false, false,
896 true, true, true, false, false, false},
897 .supports_rmii = {false, false, true, false, false,
898 false, false, false, false, false, false},
899 .supports_rgmii = {false, false, true, false, false,
900 false, false, false, false, false, false},
901 .supports_sgmii = {false, true, true, true, true,
902 false, false, false, false, false, false},