drivers/net/dsa/sja1105/sja1105_main.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /* Copyright (c) 2018, Sensor-Technik Wiedemann GmbH
   3  * Copyright (c) 2018-2019, Vladimir Oltean <olteanv@gmail.com>
   4  */
   5
   6 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
   7
   8 #include <linux/delay.h>
   9 #include <linux/module.h>
  10 #include <linux/printk.h>
  11 #include <linux/spi/spi.h>
  12 #include <linux/errno.h>
  13 #include <linux/gpio/consumer.h>
  14 #include <linux/phylink.h>
  15 #include <linux/of.h>
  16 #include <linux/of_net.h>
  17 #include <linux/of_mdio.h>
  18 #include <linux/of_device.h>
  19 #include <linux/pcs/pcs-xpcs.h>
  20 #include <linux/netdev_features.h>
  21 #include <linux/netdevice.h>
  22 #include <linux/if_bridge.h>
  23 #include <linux/if_ether.h>
  24 #include <linux/dsa/8021q.h>
  25 #include "sja1105.h"
  26 #include "sja1105_tas.h"
  27
  28 #define SJA1105_UNKNOWN_MULTICAST       0x010000000000ull
  29
  30 /* Configure the optional reset pin and bring up switch */
  31 static int sja1105_hw_reset(struct device *dev, unsigned int pulse_len,
  32                             unsigned int startup_delay)
  33 {
  34         struct gpio_desc *gpio;
  35
  36         gpio = gpiod_get_optional(dev, "reset", GPIOD_OUT_HIGH);
  37         if (IS_ERR(gpio))
  38                 return PTR_ERR(gpio);
  39
  40         if (!gpio)
  41                 return 0;
  42
  43         gpiod_set_value_cansleep(gpio, 1);
  44         /* Wait for minimum reset pulse length */
  45         msleep(pulse_len);
  46         gpiod_set_value_cansleep(gpio, 0);
  47         /* Wait until chip is ready after reset */
  48         msleep(startup_delay);
  49
  50         gpiod_put(gpio);
  51
  52         return 0;
  53 }
  54
  55 static void
  56 sja1105_port_allow_traffic(struct sja1105_l2_forwarding_entry *l2_fwd,
  57                            int from, int to, bool allow)
  58 {
  59         if (allow)
  60                 l2_fwd[from].reach_port |= BIT(to);
  61         else
  62                 l2_fwd[from].reach_port &= ~BIT(to);
  63 }
  64
  65 static bool sja1105_can_forward(struct sja1105_l2_forwarding_entry *l2_fwd,
  66                                 int from, int to)
  67 {
  68         return !!(l2_fwd[from].reach_port & BIT(to));
  69 }
  70
  71 static int sja1105_is_vlan_configured(struct sja1105_private *priv, u16 vid)
  72 {
  73         struct sja1105_vlan_lookup_entry *vlan;
  74         int count, i;
  75
  76         vlan = priv->static_config.tables[BLK_IDX_VLAN_LOOKUP].entries;
  77         count = priv->static_config.tables[BLK_IDX_VLAN_LOOKUP].entry_count;
  78
  79         for (i = 0; i < count; i++)
  80                 if (vlan[i].vlanid == vid)
  81                         return i;
  82
  83         /* Return an invalid entry index if not found */
  84         return -1;
  85 }
  86
  87 static int sja1105_drop_untagged(struct dsa_switch *ds, int port, bool drop)
  88 {
  89         struct sja1105_private *priv = ds->priv;
  90         struct sja1105_mac_config_entry *mac;
  91
  92         mac = priv->static_config.tables[BLK_IDX_MAC_CONFIG].entries;
  93
  94         if (mac[port].drpuntag == drop)
  95                 return 0;
  96
  97         mac[port].drpuntag = drop;
  98
  99         return sja1105_dynamic_config_write(priv, BLK_IDX_MAC_CONFIG, port,
 100                                             &mac[port], true);
 101 }
 102
 103 static int sja1105_pvid_apply(struct sja1105_private *priv, int port, u16 pvid)
 104 {
 105         struct sja1105_mac_config_entry *mac;
 106
 107         mac = priv->static_config.tables[BLK_IDX_MAC_CONFIG].entries;
 108
 109         if (mac[port].vlanid == pvid)
 110                 return 0;
 111
 112         mac[port].vlanid = pvid;
 113
 114         return sja1105_dynamic_config_write(priv, BLK_IDX_MAC_CONFIG, port,
 115                                             &mac[port], true);
 116 }
 117
 118 static int sja1105_commit_pvid(struct dsa_switch *ds, int port)
 119 {
 120         struct dsa_port *dp = dsa_to_port(ds, port);
 121         struct sja1105_private *priv = ds->priv;
 122         struct sja1105_vlan_lookup_entry *vlan;
 123         bool drop_untagged = false;
 124         int match, rc;
 125         u16 pvid;
 126
 127         if (dp->bridge_dev && br_vlan_enabled(dp->bridge_dev))
 128                 pvid = priv->bridge_pvid[port];
 129         else
 130                 pvid = priv->tag_8021q_pvid[port];
 131
 132         rc = sja1105_pvid_apply(priv, port, pvid);
 133         if (rc)
 134                 return rc;
 135
 136         /* Only force dropping of untagged packets when the port is under a
 137          * VLAN-aware bridge. When the tag_8021q pvid is used, we are
 138          * deliberately removing the RX VLAN from the port's VMEMB_PORT list,
 139          * to prevent DSA tag spoofing from the link partner. Untagged packets
 140          * are the only ones that should be received with tag_8021q, so
 141          * definitely don't drop them.
 142          */
 143         if (pvid == priv->bridge_pvid[port]) {
 144                 vlan = priv->static_config.tables[BLK_IDX_VLAN_LOOKUP].entries;
 145
 146                 match = sja1105_is_vlan_configured(priv, pvid);
 147
 148                 if (match < 0 || !(vlan[match].vmemb_port & BIT(port)))
 149                         drop_untagged = true;
 150         }
 151
 152         if (dsa_is_cpu_port(ds, port) || dsa_is_dsa_port(ds, port))
 153                 drop_untagged = true;
 154
 155         return sja1105_drop_untagged(ds, port, drop_untagged);
 156 }
 157
 158 static int sja1105_init_mac_settings(struct sja1105_private *priv)
 159 {
 160         struct sja1105_mac_config_entry default_mac = {
 161                 /* Enable all 8 priority queues on egress.
 162                  * Every queue i holds top[i] - base[i] frames.
 163                  * Sum of top[i] - base[i] is 511 (max hardware limit).
 164                  */
 165                 .top  = {0x3F, 0x7F, 0xBF, 0xFF, 0x13F, 0x17F, 0x1BF, 0x1FF},
 166                 .base = {0x0, 0x40, 0x80, 0xC0, 0x100, 0x140, 0x180, 0x1C0},
 167                 .enabled = {true, true, true, true, true, true, true, true},
 168                 /* Keep standard IFG of 12 bytes on egress. */
 169                 .ifg = 0,
 170                 /* Always put the MAC speed in automatic mode, where it can be
 171                  * adjusted at runtime by PHYLINK.
 172                  */
 173                 .speed = priv->info->port_speed[SJA1105_SPEED_AUTO],
 174                 /* No static correction for 1-step 1588 events */
 175                 .tp_delin = 0,
 176                 .tp_delout = 0,
 177                 /* Disable aging for critical TTEthernet traffic */
 178                 .maxage = 0xFF,
 179                 /* Internal VLAN (pvid) to apply to untagged ingress */
 180                 .vlanprio = 0,
 181                 .vlanid = 1,
 182                 .ing_mirr = false,
 183                 .egr_mirr = false,
 184                 /* Don't drop traffic with other EtherType than ETH_P_IP */
 185                 .drpnona664 = false,
 186                 /* Don't drop double-tagged traffic */
 187                 .drpdtag = false,
 188                 /* Don't drop untagged traffic */
 189                 .drpuntag = false,
 190                 /* Don't retag 802.1p (VID 0) traffic with the pvid */
 191                 .retag = false,
 192                 /* Disable learning and I/O on user ports by default -
 193                  * STP will enable it.
 194                  */
 195                 .dyn_learn = false,
 196                 .egress = false,
 197                 .ingress = false,
 198         };
 199         struct sja1105_mac_config_entry *mac;
 200         struct dsa_switch *ds = priv->ds;
 201         struct sja1105_table *table;
 202         struct dsa_port *dp;
 203
 204         table = &priv->static_config.tables[BLK_IDX_MAC_CONFIG];
 205
 206         /* Discard previous MAC Configuration Table */
 207         if (table->entry_count) {
 208                 kfree(table->entries);
 209                 table->entry_count = 0;
 210         }
 211
 212         table->entries = kcalloc(table->ops->max_entry_count,
 213                                  table->ops->unpacked_entry_size, GFP_KERNEL);
 214         if (!table->entries)
 215                 return -ENOMEM;
 216
 217         table->entry_count = table->ops->max_entry_count;
 218
 219         mac = table->entries;
 220
 221         list_for_each_entry(dp, &ds->dst->ports, list) {
 222                 if (dp->ds != ds)
 223                         continue;
 224
 225                 mac[dp->index] = default_mac;
 226
 227                 /* Let sja1105_bridge_stp_state_set() keep address learning
 228                  * enabled for the DSA ports. CPU ports use software-assisted
 229                  * learning to ensure that only FDB entries belonging to the
 230                  * bridge are learned, and that they are learned towards all
 231                  * CPU ports in a cross-chip topology if multiple CPU ports
 232                  * exist.
 233                  */
 234                 if (dsa_port_is_dsa(dp))
 235                         dp->learning = true;
 236
 237                 /* Disallow untagged packets from being received on the
 238                  * CPU and DSA ports.
 239                  */
 240                 if (dsa_port_is_cpu(dp) || dsa_port_is_dsa(dp))
 241                         mac[dp->index].drpuntag = true;
 242         }
 243
 244         return 0;
 245 }
 246
 247 static int sja1105_init_mii_settings(struct sja1105_private *priv)
 248 {
 249         struct device *dev = &priv->spidev->dev;
 250         struct sja1105_xmii_params_entry *mii;
 251         struct dsa_switch *ds = priv->ds;
 252         struct sja1105_table *table;
 253         int i;
 254
 255         table = &priv->static_config.tables[BLK_IDX_XMII_PARAMS];
 256
 257         /* Discard previous xMII Mode Parameters Table */
 258         if (table->entry_count) {
 259                 kfree(table->entries);
 260                 table->entry_count = 0;
 261         }
 262
 263         table->entries = kcalloc(table->ops->max_entry_count,
 264                                  table->ops->unpacked_entry_size, GFP_KERNEL);
 265         if (!table->entries)
 266                 return -ENOMEM;
 267
 268         /* Override table based on PHYLINK DT bindings */
 269         table->entry_count = table->ops->max_entry_count;
 270
 271         mii = table->entries;
 272
 273         for (i = 0; i < ds->num_ports; i++) {
 274                 sja1105_mii_role_t role = XMII_MAC;
 275
 276                 if (dsa_is_unused_port(priv->ds, i))
 277                         continue;
 278
 279                 switch (priv->phy_mode[i]) {
 280                 case PHY_INTERFACE_MODE_INTERNAL:
 281                         if (priv->info->internal_phy[i] == SJA1105_NO_PHY)
 282                                 goto unsupported;
 283
 284                         mii->xmii_mode[i] = XMII_MODE_MII;
 285                         if (priv->info->internal_phy[i] == SJA1105_PHY_BASE_TX)
 286                                 mii->special[i] = true;
 287
 288                         break;
 289                 case PHY_INTERFACE_MODE_REVMII:
 290                         role = XMII_PHY;
 291                         fallthrough;
 292                 case PHY_INTERFACE_MODE_MII:
 293                         if (!priv->info->supports_mii[i])
 294                                 goto unsupported;
 295
 296                         mii->xmii_mode[i] = XMII_MODE_MII;
 297                         break;
 298                 case PHY_INTERFACE_MODE_REVRMII:
 299                         role = XMII_PHY;
 300                         fallthrough;
 301                 case PHY_INTERFACE_MODE_RMII:
 302                         if (!priv->info->supports_rmii[i])
 303                                 goto unsupported;
 304
 305                         mii->xmii_mode[i] = XMII_MODE_RMII;
 306                         break;
 307                 case PHY_INTERFACE_MODE_RGMII:
 308                 case PHY_INTERFACE_MODE_RGMII_ID:
 309                 case PHY_INTERFACE_MODE_RGMII_RXID:
 310                 case PHY_INTERFACE_MODE_RGMII_TXID:
 311                         if (!priv->info->supports_rgmii[i])
 312                                 goto unsupported;
 313
 314                         mii->xmii_mode[i] = XMII_MODE_RGMII;
 315                         break;
 316                 case PHY_INTERFACE_MODE_SGMII:
 317                         if (!priv->info->supports_sgmii[i])
 318                                 goto unsupported;
 319
 320                         mii->xmii_mode[i] = XMII_MODE_SGMII;
 321                         mii->special[i] = true;
 322                         break;
 323                 case PHY_INTERFACE_MODE_2500BASEX:
 324                         if (!priv->info->supports_2500basex[i])
 325                                 goto unsupported;
 326
 327                         mii->xmii_mode[i] = XMII_MODE_SGMII;
 328                         mii->special[i] = true;
 329                         break;
 330 unsupported:
 331                 default:
 332                         dev_err(dev, "Unsupported PHY mode %s on port %d!\n",
 333                                 phy_modes(priv->phy_mode[i]), i);
 334                         return -EINVAL;
 335                 }
 336
 337                 mii->phy_mac[i] = role;
 338         }
 339         return 0;
 340 }
 341
 342 static int sja1105_init_static_fdb(struct sja1105_private *priv)
 343 {
 344         struct sja1105_l2_lookup_entry *l2_lookup;
 345         struct sja1105_table *table;
 346         int port;
 347
 348         table = &priv->static_config.tables[BLK_IDX_L2_LOOKUP];
 349
 350         /* We only populate the FDB table through dynamic L2 Address Lookup
 351          * entries, except for a special entry at the end which is a catch-all
 352          * for unknown multicast and will be used to control flooding domain.
 353          */
 354         if (table->entry_count) {
 355                 kfree(table->entries);
 356                 table->entry_count = 0;
 357         }
 358
 359         if (!priv->info->can_limit_mcast_flood)
 360                 return 0;
 361
 362         table->entries = kcalloc(1, table->ops->unpacked_entry_size,
 363                                  GFP_KERNEL);
 364         if (!table->entries)
 365                 return -ENOMEM;
 366
 367         table->entry_count = 1;
 368         l2_lookup = table->entries;
 369
 370         /* All L2 multicast addresses have an odd first octet */
 371         l2_lookup[0].macaddr = SJA1105_UNKNOWN_MULTICAST;
 372         l2_lookup[0].mask_macaddr = SJA1105_UNKNOWN_MULTICAST;
 373         l2_lookup[0].lockeds = true;
 374         l2_lookup[0].index = SJA1105_MAX_L2_LOOKUP_COUNT - 1;
 375
 376         /* Flood multicast to every port by default */
 377         for (port = 0; port < priv->ds->num_ports; port++)
 378                 if (!dsa_is_unused_port(priv->ds, port))
 379                         l2_lookup[0].destports |= BIT(port);
 380
 381         return 0;
 382 }
 383
 384 static int sja1105_init_l2_lookup_params(struct sja1105_private *priv)
 385 {
 386         struct sja1105_l2_lookup_params_entry default_l2_lookup_params = {
 387                 /* Learned FDB entries are forgotten after 300 seconds */
 388                 .maxage = SJA1105_AGEING_TIME_MS(300000),
 389                 /* All entries within a FDB bin are available for learning */
 390                 .dyn_tbsz = SJA1105ET_FDB_BIN_SIZE,
 391                 /* And the P/Q/R/S equivalent setting: */
 392                 .start_dynspc = 0,
 393                 /* 2^8 + 2^5 + 2^3 + 2^2 + 2^1 + 1 in Koopman notation */
 394                 .poly = 0x97,
 395                 /* This selects between Independent VLAN Learning (IVL) and
 396                  * Shared VLAN Learning (SVL)
 397                  */
 398                 .shared_learn = true,
 399                 /* Don't discard management traffic based on ENFPORT -
 400                  * we don't perform SMAC port enforcement anyway, so
 401                  * what we are setting here doesn't matter.
 402                  */
 403                 .no_enf_hostprt = false,
 404                 /* Don't learn SMAC for mac_fltres1 and mac_fltres0.
 405                  * Maybe correlate with no_linklocal_learn from bridge driver?
 406                  */
 407                 .no_mgmt_learn = true,
 408                 /* P/Q/R/S only */
 409                 .use_static = true,
 410                 /* Dynamically learned FDB entries can overwrite other (older)
 411                  * dynamic FDB entries
 412                  */
 413                 .owr_dyn = true,
 414                 .drpnolearn = true,
 415         };
 416         struct dsa_switch *ds = priv->ds;
 417         int port, num_used_ports = 0;
 418         struct sja1105_table *table;
 419         u64 max_fdb_entries;
 420
 421         for (port = 0; port < ds->num_ports; port++)
 422                 if (!dsa_is_unused_port(ds, port))
 423                         num_used_ports++;
 424
 425         max_fdb_entries = SJA1105_MAX_L2_LOOKUP_COUNT / num_used_ports;
 426
 427         for (port = 0; port < ds->num_ports; port++) {
 428                 if (dsa_is_unused_port(ds, port))
 429                         continue;
 430
 431                 default_l2_lookup_params.maxaddrp[port] = max_fdb_entries;
 432         }
 433
 434         table = &priv->static_config.tables[BLK_IDX_L2_LOOKUP_PARAMS];
 435
 436         if (table->entry_count) {
 437                 kfree(table->entries);
 438                 table->entry_count = 0;
 439         }
 440
 441         table->entries = kcalloc(table->ops->max_entry_count,
 442                                  table->ops->unpacked_entry_size, GFP_KERNEL);
 443         if (!table->entries)
 444                 return -ENOMEM;
 445
 446         table->entry_count = table->ops->max_entry_count;
 447
 448         /* This table only has a single entry */
 449         ((struct sja1105_l2_lookup_params_entry *)table->entries)[0] =
 450                                 default_l2_lookup_params;
 451
 452         return 0;
 453 }
 454
 455 /* Set up a default VLAN for untagged traffic injected from the CPU
 456  * using management routes (e.g. STP, PTP) as opposed to tag_8021q.
 457  * All DT-defined ports are members of this VLAN, and there are no
 458  * restrictions on forwarding (since the CPU selects the destination).
 459  * Frames from this VLAN will always be transmitted as untagged, and
 460  * neither the bridge nor the 8021q module cannot create this VLAN ID.
 461  */
 462 static int sja1105_init_static_vlan(struct sja1105_private *priv)
 463 {
 464         struct sja1105_table *table;
 465         struct sja1105_vlan_lookup_entry pvid = {
 466                 .type_entry = SJA1110_VLAN_D_TAG,
 467                 .ving_mirr = 0,
 468                 .vegr_mirr = 0,
 469                 .vmemb_port = 0,
 470                 .vlan_bc = 0,
 471                 .tag_port = 0,
 472                 .vlanid = SJA1105_DEFAULT_VLAN,
 473         };
 474         struct dsa_switch *ds = priv->ds;
 475         int port;
 476
 477         table = &priv->static_config.tables[BLK_IDX_VLAN_LOOKUP];
 478
 479         if (table->entry_count) {
 480                 kfree(table->entries);
 481                 table->entry_count = 0;
 482         }
 483
 484         table->entries = kzalloc(table->ops->unpacked_entry_size,
 485                                  GFP_KERNEL);
 486         if (!table->entries)
 487                 return -ENOMEM;
 488
 489         table->entry_count = 1;
 490
 491         for (port = 0; port < ds->num_ports; port++) {
 492                 if (dsa_is_unused_port(ds, port))
 493                         continue;
 494
 495                 pvid.vmemb_port |= BIT(port);
 496                 pvid.vlan_bc |= BIT(port);
 497                 pvid.tag_port &= ~BIT(port);
 498
 499                 if (dsa_is_cpu_port(ds, port) || dsa_is_dsa_port(ds, port)) {
 500                         priv->tag_8021q_pvid[port] = SJA1105_DEFAULT_VLAN;
 501                         priv->bridge_pvid[port] = SJA1105_DEFAULT_VLAN;
 502                 }
 503         }
 504
 505         ((struct sja1105_vlan_lookup_entry *)table->entries)[0] = pvid;
 506         return 0;
 507 }
 508
 509 static int sja1105_init_l2_forwarding(struct sja1105_private *priv)
 510 {
 511         struct sja1105_l2_forwarding_entry *l2fwd;
 512         struct dsa_switch *ds = priv->ds;
 513         struct dsa_switch_tree *dst;
 514         struct sja1105_table *table;
 515         struct dsa_link *dl;
 516         int port, tc;
 517         int from, to;
 518
 519         table = &priv->static_config.tables[BLK_IDX_L2_FORWARDING];
 520
 521         if (table->entry_count) {
 522                 kfree(table->entries);
 523                 table->entry_count = 0;
 524         }
 525
 526         table->entries = kcalloc(table->ops->max_entry_count,
 527                                  table->ops->unpacked_entry_size, GFP_KERNEL);
 528         if (!table->entries)
 529                 return -ENOMEM;
 530
 531         table->entry_count = table->ops->max_entry_count;
 532
 533         l2fwd = table->entries;
 534
 535         /* First 5 entries in the L2 Forwarding Table define the forwarding
 536          * rules and the VLAN PCP to ingress queue mapping.
 537          * Set up the ingress queue mapping first.
 538          */
 539         for (port = 0; port < ds->num_ports; port++) {
 540                 if (dsa_is_unused_port(ds, port))
 541                         continue;
 542
 543                 for (tc = 0; tc < SJA1105_NUM_TC; tc++)
 544                         l2fwd[port].vlan_pmap[tc] = tc;
 545         }
 546
 547         /* Then manage the forwarding domain for user ports. These can forward
 548          * only to the always-on domain (CPU port and DSA links)
 549          */
 550         for (from = 0; from < ds->num_ports; from++) {
 551                 if (!dsa_is_user_port(ds, from))
 552                         continue;
 553
 554                 for (to = 0; to < ds->num_ports; to++) {
 555                         if (!dsa_is_cpu_port(ds, to) &&
 556                             !dsa_is_dsa_port(ds, to))
 557                                 continue;
 558
 559                         l2fwd[from].bc_domain |= BIT(to);
 560                         l2fwd[from].fl_domain |= BIT(to);
 561
 562                         sja1105_port_allow_traffic(l2fwd, from, to, true);
 563                 }
 564         }
 565
 566         /* Then manage the forwarding domain for DSA links and CPU ports (the
 567          * always-on domain). These can send packets to any enabled port except
 568          * themselves.
 569          */
 570         for (from = 0; from < ds->num_ports; from++) {
 571                 if (!dsa_is_cpu_port(ds, from) && !dsa_is_dsa_port(ds, from))
 572                         continue;
 573
 574                 for (to = 0; to < ds->num_ports; to++) {
 575                         if (dsa_is_unused_port(ds, to))
 576                                 continue;
 577
 578                         if (from == to)
 579                                 continue;
 580
 581                         l2fwd[from].bc_domain |= BIT(to);
 582                         l2fwd[from].fl_domain |= BIT(to);
 583
 584                         sja1105_port_allow_traffic(l2fwd, from, to, true);
 585                 }
 586         }
 587
 588         /* In odd topologies ("H" connections where there is a DSA link to
 589          * another switch which also has its own CPU port), TX packets can loop
 590          * back into the system (they are flooded from CPU port 1 to the DSA
 591          * link, and from there to CPU port 2). Prevent this from happening by
 592          * cutting RX from DSA links towards our CPU port, if the remote switch
 593          * has its own CPU port and therefore doesn't need ours for network
 594          * stack termination.
 595          */
 596         dst = ds->dst;
 597
 598         list_for_each_entry(dl, &dst->rtable, list) {
 599                 if (dl->dp->ds != ds || dl->link_dp->cpu_dp == dl->dp->cpu_dp)
 600                         continue;
 601
 602                 from = dl->dp->index;
 603                 to = dsa_upstream_port(ds, from);
 604
 605                 dev_warn(ds->dev,
 606                          "H topology detected, cutting RX from DSA link %d to CPU port %d to prevent TX packet loops\n",
 607                          from, to);
 608
 609                 sja1105_port_allow_traffic(l2fwd, from, to, false);
 610
 611                 l2fwd[from].bc_domain &= ~BIT(to);
 612                 l2fwd[from].fl_domain &= ~BIT(to);
 613         }
 614
 615         /* Finally, manage the egress flooding domain. All ports start up with
 616          * flooding enabled, including the CPU port and DSA links.
 617          */
 618         for (port = 0; port < ds->num_ports; port++) {
 619                 if (dsa_is_unused_port(ds, port))
 620                         continue;
 621
 622                 priv->ucast_egress_floods |= BIT(port);
 623                 priv->bcast_egress_floods |= BIT(port);
 624         }
 625
 626         /* Next 8 entries define VLAN PCP mapping from ingress to egress.
 627          * Create a one-to-one mapping.
 628          */
 629         for (tc = 0; tc < SJA1105_NUM_TC; tc++) {
 630                 for (port = 0; port < ds->num_ports; port++) {
 631                         if (dsa_is_unused_port(ds, port))
 632                                 continue;
 633
 634                         l2fwd[ds->num_ports + tc].vlan_pmap[port] = tc;
 635                 }
 636
 637                 l2fwd[ds->num_ports + tc].type_egrpcp2outputq = true;
 638         }
 639
 640         return 0;
 641 }
 642
 643 static int sja1110_init_pcp_remapping(struct sja1105_private *priv)
 644 {
 645         struct sja1110_pcp_remapping_entry *pcp_remap;
 646         struct dsa_switch *ds = priv->ds;
 647         struct sja1105_table *table;
 648         int port, tc;
 649
 650         table = &priv->static_config.tables[BLK_IDX_PCP_REMAPPING];
 651
 652         /* Nothing to do for SJA1105 */
 653         if (!table->ops->max_entry_count)
 654                 return 0;
 655
 656         if (table->entry_count) {
 657                 kfree(table->entries);
 658                 table->entry_count = 0;
 659         }
 660
 661         table->entries = kcalloc(table->ops->max_entry_count,
 662                                  table->ops->unpacked_entry_size, GFP_KERNEL);
 663         if (!table->entries)
 664                 return -ENOMEM;
 665
 666         table->entry_count = table->ops->max_entry_count;
 667
 668         pcp_remap = table->entries;
 669
 670         /* Repeat the configuration done for vlan_pmap */
 671         for (port = 0; port < ds->num_ports; port++) {
 672                 if (dsa_is_unused_port(ds, port))
 673                         continue;
 674
 675                 for (tc = 0; tc < SJA1105_NUM_TC; tc++)
 676                         pcp_remap[port].egrpcp[tc] = tc;
 677         }
 678
 679         return 0;
 680 }
 681
 682 static int sja1105_init_l2_forwarding_params(struct sja1105_private *priv)
 683 {
 684         struct sja1105_l2_forwarding_params_entry *l2fwd_params;
 685         struct sja1105_table *table;
 686
 687         table = &priv->static_config.tables[BLK_IDX_L2_FORWARDING_PARAMS];
 688
 689         if (table->entry_count) {
 690                 kfree(table->entries);
 691                 table->entry_count = 0;
 692         }
 693
 694         table->entries = kcalloc(table->ops->max_entry_count,
 695                                  table->ops->unpacked_entry_size, GFP_KERNEL);
 696         if (!table->entries)
 697                 return -ENOMEM;
 698
 699         table->entry_count = table->ops->max_entry_count;
 700
 701         /* This table only has a single entry */
 702         l2fwd_params = table->entries;
 703
 704         /* Disallow dynamic reconfiguration of vlan_pmap */
 705         l2fwd_params->max_dynp = 0;
 706         /* Use a single memory partition for all ingress queues */
 707         l2fwd_params->part_spc[0] = priv->info->max_frame_mem;
 708
 709         return 0;
 710 }
 711
 712 void sja1105_frame_memory_partitioning(struct sja1105_private *priv)
 713 {
 714         struct sja1105_l2_forwarding_params_entry *l2_fwd_params;
 715         struct sja1105_vl_forwarding_params_entry *vl_fwd_params;
 716         struct sja1105_table *table;
 717
 718         table = &priv->static_config.tables[BLK_IDX_L2_FORWARDING_PARAMS];
 719         l2_fwd_params = table->entries;
 720         l2_fwd_params->part_spc[0] = SJA1105_MAX_FRAME_MEMORY;
 721
 722         /* If we have any critical-traffic virtual links, we need to reserve
 723          * some frame buffer memory for them. At the moment, hardcode the value
 724          * at 100 blocks of 128 bytes of memory each. This leaves 829 blocks
 725          * remaining for best-effort traffic. TODO: figure out a more flexible
 726          * way to perform the frame buffer partitioning.
 727          */
 728         if (!priv->static_config.tables[BLK_IDX_VL_FORWARDING].entry_count)
 729                 return;
 730
 731         table = &priv->static_config.tables[BLK_IDX_VL_FORWARDING_PARAMS];
 732         vl_fwd_params = table->entries;
 733
 734         l2_fwd_params->part_spc[0] -= SJA1105_VL_FRAME_MEMORY;
 735         vl_fwd_params->partspc[0] = SJA1105_VL_FRAME_MEMORY;
 736 }
 737
 738 /* SJA1110 TDMACONFIGIDX values:
 739  *
 740  *      | 100 Mbps ports |  1Gbps ports  | 2.5Gbps ports | Disabled ports
 741  * -----+----------------+---------------+---------------+---------------
 742  *   0  |   0, [5:10]    |     [1:2]     |     [3:4]     |     retag
 743  *   1  |0, [5:10], retag|     [1:2]     |     [3:4]     |       -
 744  *   2  |   0, [5:10]    |  [1:3], retag |       4       |       -
 745  *   3  |   0, [5:10]    |[1:2], 4, retag|       3       |       -
 746  *   4  |  0, 2, [5:10]  |    1, retag   |     [3:4]     |       -
 747  *   5  |  0, 1, [5:10]  |    2, retag   |     [3:4]     |       -
 748  *  14  |   0, [5:10]    | [1:4], retag  |       -       |       -
 749  *  15  |     [5:10]     | [0:4], retag  |       -       |       -
 750  */
 751 static void sja1110_select_tdmaconfigidx(struct sja1105_private *priv)
 752 {
 753         struct sja1105_general_params_entry *general_params;
 754         struct sja1105_table *table;
 755         bool port_1_is_base_tx;
 756         bool port_3_is_2500;
 757         bool port_4_is_2500;
 758         u64 tdmaconfigidx;
 759
 760         if (priv->info->device_id != SJA1110_DEVICE_ID)
 761                 return;
 762
 763         table = &priv->static_config.tables[BLK_IDX_GENERAL_PARAMS];
 764         general_params = table->entries;
 765
 766         /* All the settings below are "as opposed to SGMII", which is the
 767          * other pinmuxing option.
 768          */
 769         port_1_is_base_tx = priv->phy_mode[1] == PHY_INTERFACE_MODE_INTERNAL;
 770         port_3_is_2500 = priv->phy_mode[3] == PHY_INTERFACE_MODE_2500BASEX;
 771         port_4_is_2500 = priv->phy_mode[4] == PHY_INTERFACE_MODE_2500BASEX;
 772
 773         if (port_1_is_base_tx)
 774                 /* Retagging port will operate at 1 Gbps */
 775                 tdmaconfigidx = 5;
 776         else if (port_3_is_2500 && port_4_is_2500)
 777                 /* Retagging port will operate at 100 Mbps */
 778                 tdmaconfigidx = 1;
 779         else if (port_3_is_2500)
 780                 /* Retagging port will operate at 1 Gbps */
 781                 tdmaconfigidx = 3;
 782         else if (port_4_is_2500)
 783                 /* Retagging port will operate at 1 Gbps */
 784                 tdmaconfigidx = 2;
 785         else
 786                 /* Retagging port will operate at 1 Gbps */
 787                 tdmaconfigidx = 14;
 788
 789         general_params->tdmaconfigidx = tdmaconfigidx;
 790 }
 791
 792 static int sja1105_init_topology(struct sja1105_private *priv,
 793                                  struct sja1105_general_params_entry *general_params)
 794 {
 795         struct dsa_switch *ds = priv->ds;
 796         int port;
 797
 798         /* The host port is the destination for traffic matching mac_fltres1
 799          * and mac_fltres0 on all ports except itself. Default to an invalid
 800          * value.
 801          */
 802         general_params->host_port = ds->num_ports;
 803
 804         /* Link-local traffic received on casc_port will be forwarded
 805          * to host_port without embedding the source port and device ID
 806          * info in the destination MAC address, and no RX timestamps will be
 807          * taken either (presumably because it is a cascaded port and a
 808          * downstream SJA switch already did that).
 809          * To disable the feature, we need to do different things depending on
 810          * switch generation. On SJA1105 we need to set an invalid port, while
 811          * on SJA1110 which support multiple cascaded ports, this field is a
 812          * bitmask so it must be left zero.
 813          */
 814         if (!priv->info->multiple_cascade_ports)
 815                 general_params->casc_port = ds->num_ports;
 816
 817         for (port = 0; port < ds->num_ports; port++) {
 818                 bool is_upstream = dsa_is_upstream_port(ds, port);
 819                 bool is_dsa_link = dsa_is_dsa_port(ds, port);
 820
 821                 /* Upstream ports can be dedicated CPU ports or
 822                  * upstream-facing DSA links
 823                  */
 824                 if (is_upstream) {
 825                         if (general_params->host_port == ds->num_ports) {
 826                                 general_params->host_port = port;
 827                         } else {
 828                                 dev_err(ds->dev,
 829                                         "Port %llu is already a host port, configuring %d as one too is not supported\n",
 830                                         general_params->host_port, port);
 831                                 return -EINVAL;
 832                         }
 833                 }
 834
 835                 /* Cascade ports are downstream-facing DSA links */
 836                 if (is_dsa_link && !is_upstream) {
 837                         if (priv->info->multiple_cascade_ports) {
 838                                 general_params->casc_port |= BIT(port);
 839                         } else if (general_params->casc_port == ds->num_ports) {
 840                                 general_params->casc_port = port;
 841                         } else {
 842                                 dev_err(ds->dev,
 843                                         "Port %llu is already a cascade port, configuring %d as one too is not supported\n",
 844                                         general_params->casc_port, port);
 845                                 return -EINVAL;
 846                         }
 847                 }
 848         }
 849
 850         if (general_params->host_port == ds->num_ports) {
 851                 dev_err(ds->dev, "No host port configured\n");
 852                 return -EINVAL;
 853         }
 854
 855         return 0;
 856 }
 857
 858 static int sja1105_init_general_params(struct sja1105_private *priv)
 859 {
 860         struct sja1105_general_params_entry default_general_params = {
 861                 /* Allow dynamic changing of the mirror port */
 862                 .mirr_ptacu = true,
 863                 .switchid = priv->ds->index,
 864                 /* Priority queue for link-local management frames
 865                  * (both ingress to and egress from CPU - PTP, STP etc)
 866                  */
 867                 .hostprio = 7,
 868                 .mac_fltres1 = SJA1105_LINKLOCAL_FILTER_A,
 869                 .mac_flt1    = SJA1105_LINKLOCAL_FILTER_A_MASK,
 870                 .incl_srcpt1 = false,
 871                 .send_meta1  = false,
 872                 .mac_fltres0 = SJA1105_LINKLOCAL_FILTER_B,
 873                 .mac_flt0    = SJA1105_LINKLOCAL_FILTER_B_MASK,
 874                 .incl_srcpt0 = false,
 875                 .send_meta0  = false,
 876                 /* Default to an invalid value */
 877                 .mirr_port = priv->ds->num_ports,
 878                 /* No TTEthernet */
 879                 .vllupformat = SJA1105_VL_FORMAT_PSFP,
 880                 .vlmarker = 0,
 881                 .vlmask = 0,
 882                 /* Only update correctionField for 1-step PTP (L2 transport) */
 883                 .ignore2stf = 0,
 884                 /* Forcefully disable VLAN filtering by telling
 885                  * the switch that VLAN has a different EtherType.
 886                  */
 887                 .tpid = ETH_P_SJA1105,
 888                 .tpid2 = ETH_P_SJA1105,
 889                 /* Enable the TTEthernet engine on SJA1110 */
 890                 .tte_en = true,
 891                 /* Set up the EtherType for control packets on SJA1110 */
 892                 .header_type = ETH_P_SJA1110,
 893         };
 894         struct sja1105_general_params_entry *general_params;
 895         struct sja1105_table *table;
 896         int rc;
 897
 898         rc = sja1105_init_topology(priv, &default_general_params);
 899         if (rc)
 900                 return rc;
 901
 902         table = &priv->static_config.tables[BLK_IDX_GENERAL_PARAMS];
 903
 904         if (table->entry_count) {
 905                 kfree(table->entries);
 906                 table->entry_count = 0;
 907         }
 908
 909         table->entries = kcalloc(table->ops->max_entry_count,
 910                                  table->ops->unpacked_entry_size, GFP_KERNEL);
 911         if (!table->entries)
 912                 return -ENOMEM;
 913
 914         table->entry_count = table->ops->max_entry_count;
 915
 916         general_params = table->entries;
 917
 918         /* This table only has a single entry */
 919         general_params[0] = default_general_params;
 920
 921         sja1110_select_tdmaconfigidx(priv);
 922
 923         return 0;
 924 }
 925
 926 static int sja1105_init_avb_params(struct sja1105_private *priv)
 927 {
 928         struct sja1105_avb_params_entry *avb;
 929         struct sja1105_table *table;
 930
 931         table = &priv->static_config.tables[BLK_IDX_AVB_PARAMS];
 932
 933         /* Discard previous AVB Parameters Table */
 934         if (table->entry_count) {
 935                 kfree(table->entries);
 936                 table->entry_count = 0;
 937         }
 938
 939         table->entries = kcalloc(table->ops->max_entry_count,
 940                                  table->ops->unpacked_entry_size, GFP_KERNEL);
 941         if (!table->entries)
 942                 return -ENOMEM;
 943
 944         table->entry_count = table->ops->max_entry_count;
 945
 946         avb = table->entries;
 947
 948         /* Configure the MAC addresses for meta frames */
 949         avb->destmeta = SJA1105_META_DMAC;
 950         avb->srcmeta  = SJA1105_META_SMAC;
 951         /* On P/Q/R/S, configure the direction of the PTP_CLK pin as input by
 952          * default. This is because there might be boards with a hardware
 953          * layout where enabling the pin as output might cause an electrical
 954          * clash. On E/T the pin is always an output, which the board designers
 955          * probably already knew, so even if there are going to be electrical
 956          * issues, there's nothing we can do.
 957          */
 958         avb->cas_master = false;
 959
 960         return 0;
 961 }
 962
 963 /* The L2 policing table is 2-stage. The table is looked up for each frame
 964  * according to the ingress port, whether it was broadcast or not, and the
 965  * classified traffic class (given by VLAN PCP). This portion of the lookup is
 966  * fixed, and gives access to the SHARINDX, an indirection register pointing
 967  * within the policing table itself, which is used to resolve the policer that
 968  * will be used for this frame.
 969  *
 970  *  Stage 1                              Stage 2
 971  * +------------+--------+              +---------------------------------+
 972  * |Port 0 TC 0 |SHARINDX|              | Policer 0: Rate, Burst, MTU     |
 973  * +------------+--------+              +---------------------------------+
 974  * |Port 0 TC 1 |SHARINDX|              | Policer 1: Rate, Burst, MTU     |
 975  * +------------+--------+              +---------------------------------+
 976  *    ...                               | Policer 2: Rate, Burst, MTU     |
 977  * +------------+--------+              +---------------------------------+
 978  * |Port 0 TC 7 |SHARINDX|              | Policer 3: Rate, Burst, MTU     |
 979  * +------------+--------+              +---------------------------------+
 980  * |Port 1 TC 0 |SHARINDX|              | Policer 4: Rate, Burst, MTU     |
 981  * +------------+--------+              +---------------------------------+
 982  *    ...                               | Policer 5: Rate, Burst, MTU     |
 983  * +------------+--------+              +---------------------------------+
 984  * |Port 1 TC 7 |SHARINDX|              | Policer 6: Rate, Burst, MTU     |
 985  * +------------+--------+              +---------------------------------+
 986  *    ...                               | Policer 7: Rate, Burst, MTU     |
 987  * +------------+--------+              +---------------------------------+
 988  * |Port 4 TC 7 |SHARINDX|                 ...
 989  * +------------+--------+
 990  * |Port 0 BCAST|SHARINDX|                 ...
 991  * +------------+--------+
 992  * |Port 1 BCAST|SHARINDX|                 ...
 993  * +------------+--------+
 994  *    ...                                  ...
 995  * +------------+--------+              +---------------------------------+
 996  * |Port 4 BCAST|SHARINDX|              | Policer 44: Rate, Burst, MTU    |
 997  * +------------+--------+              +---------------------------------+
 998  *
 999  * In this driver, we shall use policers 0-4 as statically alocated port
1000  * (matchall) policers. So we need to make the SHARINDX for all lookups
1001  * corresponding to this ingress port (8 VLAN PCP lookups and 1 broadcast
1002  * lookup) equal.
1003  * The remaining policers (40) shall be dynamically allocated for flower
1004  * policers, where the key is either vlan_prio or dst_mac ff:ff:ff:ff:ff:ff.
1005  */
1006 #define SJA1105_RATE_MBPS(speed) (((speed) * 64000) / 1000)
1007
1008 static int sja1105_init_l2_policing(struct sja1105_private *priv)
1009 {
1010         struct sja1105_l2_policing_entry *policing;
1011         struct dsa_switch *ds = priv->ds;
1012         struct sja1105_table *table;
1013         int port, tc;
1014
1015         table = &priv->static_config.tables[BLK_IDX_L2_POLICING];
1016
1017         /* Discard previous L2 Policing Table */
1018         if (table->entry_count) {
1019                 kfree(table->entries);
1020                 table->entry_count = 0;
1021         }
1022
1023         table->entries = kcalloc(table->ops->max_entry_count,
1024                                  table->ops->unpacked_entry_size, GFP_KERNEL);
1025         if (!table->entries)
1026                 return -ENOMEM;
1027
1028         table->entry_count = table->ops->max_entry_count;
1029
1030         policing = table->entries;
1031
1032         /* Setup shared indices for the matchall policers */
1033         for (port = 0; port < ds->num_ports; port++) {
1034                 int mcast = (ds->num_ports * (SJA1105_NUM_TC + 1)) + port;
1035                 int bcast = (ds->num_ports * SJA1105_NUM_TC) + port;
1036
1037                 for (tc = 0; tc < SJA1105_NUM_TC; tc++)
1038                         policing[port * SJA1105_NUM_TC + tc].sharindx = port;
1039
1040                 policing[bcast].sharindx = port;
1041                 /* Only SJA1110 has multicast policers */
1042                 if (mcast <= table->ops->max_entry_count)
1043                         policing[mcast].sharindx = port;
1044         }
1045
1046         /* Setup the matchall policer parameters */
1047         for (port = 0; port < ds->num_ports; port++) {
1048                 int mtu = VLAN_ETH_FRAME_LEN + ETH_FCS_LEN;
1049
1050                 if (dsa_is_cpu_port(ds, port) || dsa_is_dsa_port(ds, port))
1051                         mtu += VLAN_HLEN;
1052
1053                 policing[port].smax = 65535; /* Burst size in bytes */
1054                 policing[port].rate = SJA1105_RATE_MBPS(1000);
1055                 policing[port].maxlen = mtu;
1056                 policing[port].partition = 0;
1057         }
1058
1059         return 0;
1060 }
1061
1062 static int sja1105_static_config_load(struct sja1105_private *priv)
1063 {
1064         int rc;
1065
1066         sja1105_static_config_free(&priv->static_config);
1067         rc = sja1105_static_config_init(&priv->static_config,
1068                                         priv->info->static_ops,
1069                                         priv->info->device_id);
1070         if (rc)
1071                 return rc;
1072
1073         /* Build static configuration */
1074         rc = sja1105_init_mac_settings(priv);
1075         if (rc < 0)
1076                 return rc;
1077         rc = sja1105_init_mii_settings(priv);
1078         if (rc < 0)
1079                 return rc;
1080         rc = sja1105_init_static_fdb(priv);
1081         if (rc < 0)
1082                 return rc;
1083         rc = sja1105_init_static_vlan(priv);
1084         if (rc < 0)
1085                 return rc;
1086         rc = sja1105_init_l2_lookup_params(priv);
1087         if (rc < 0)
1088                 return rc;
1089         rc = sja1105_init_l2_forwarding(priv);
1090         if (rc < 0)
1091                 return rc;
1092         rc = sja1105_init_l2_forwarding_params(priv);
1093         if (rc < 0)
1094                 return rc;
1095         rc = sja1105_init_l2_policing(priv);
1096         if (rc < 0)
1097                 return rc;
1098         rc = sja1105_init_general_params(priv);
1099         if (rc < 0)
1100                 return rc;
1101         rc = sja1105_init_avb_params(priv);
1102         if (rc < 0)
1103                 return rc;
1104         rc = sja1110_init_pcp_remapping(priv);
1105         if (rc < 0)
1106                 return rc;
1107
1108         /* Send initial configuration to hardware via SPI */
1109         return sja1105_static_config_upload(priv);
1110 }
1111
1112 /* This is the "new way" for a MAC driver to configure its RGMII delay lines,
1113  * based on the explicit "rx-internal-delay-ps" and "tx-internal-delay-ps"
1114  * properties. It has the advantage of working with fixed links and with PHYs
1115  * that apply RGMII delays too, and the MAC driver needs not perform any
1116  * special checks.
1117  *
1118  * Previously we were acting upon the "phy-mode" property when we were
1119  * operating in fixed-link, basically acting as a PHY, but with a reversed
1120  * interpretation: PHY_INTERFACE_MODE_RGMII_TXID means that the MAC should
1121  * behave as if it is connected to a PHY which has applied RGMII delays in the
1122  * TX direction. So if anything, RX delays should have been added by the MAC,
1123  * but we were adding TX delays.
1124  *
1125  * If the "{rx,tx}-internal-delay-ps" properties are not specified, we fall
1126  * back to the legacy behavior and apply delays on fixed-link ports based on
1127  * the reverse interpretation of the phy-mode. This is a deviation from the
1128  * expected default behavior which is to simply apply no delays. To achieve
1129  * that behavior with the new bindings, it is mandatory to specify
1130  * "{rx,tx}-internal-delay-ps" with a value of 0.
1131  */
1132 static int sja1105_parse_rgmii_delays(struct sja1105_private *priv, int port,
1133                                       struct device_node *port_dn)
1134 {
1135         phy_interface_t phy_mode = priv->phy_mode[port];
1136         struct device *dev = &priv->spidev->dev;
1137         int rx_delay = -1, tx_delay = -1;
1138
1139         if (!phy_interface_mode_is_rgmii(phy_mode))
1140                 return 0;
1141
1142         of_property_read_u32(port_dn, "rx-internal-delay-ps", &rx_delay);
1143         of_property_read_u32(port_dn, "tx-internal-delay-ps", &tx_delay);
1144
1145         if (rx_delay == -1 && tx_delay == -1 && priv->fixed_link[port]) {
1146                 dev_warn(dev,
1147                          "Port %d interpreting RGMII delay settings based on \"phy-mode\" property, "
1148                          "please update device tree to specify \"rx-internal-delay-ps\" and "
1149                          "\"tx-internal-delay-ps\"",
1150                          port);
1151
1152                 if (phy_mode == PHY_INTERFACE_MODE_RGMII_RXID ||
1153                     phy_mode == PHY_INTERFACE_MODE_RGMII_ID)
1154                         rx_delay = 2000;
1155
1156                 if (phy_mode == PHY_INTERFACE_MODE_RGMII_TXID ||
1157                     phy_mode == PHY_INTERFACE_MODE_RGMII_ID)
1158                         tx_delay = 2000;
1159         }
1160
1161         if (rx_delay < 0)
1162                 rx_delay = 0;
1163         if (tx_delay < 0)
1164                 tx_delay = 0;
1165
1166         if ((rx_delay || tx_delay) && !priv->info->setup_rgmii_delay) {
1167                 dev_err(dev, "Chip cannot apply RGMII delays\n");
1168                 return -EINVAL;
1169         }
1170
1171         if ((rx_delay && rx_delay < SJA1105_RGMII_DELAY_MIN_PS) ||
1172             (tx_delay && tx_delay < SJA1105_RGMII_DELAY_MIN_PS) ||
1173             (rx_delay > SJA1105_RGMII_DELAY_MAX_PS) ||
1174             (tx_delay > SJA1105_RGMII_DELAY_MAX_PS)) {
1175                 dev_err(dev,
1176                         "port %d RGMII delay values out of range, must be between %d and %d ps\n",
1177                         port, SJA1105_RGMII_DELAY_MIN_PS, SJA1105_RGMII_DELAY_MAX_PS);
1178                 return -ERANGE;
1179         }
1180
1181         priv->rgmii_rx_delay_ps[port] = rx_delay;
1182         priv->rgmii_tx_delay_ps[port] = tx_delay;
1183
1184         return 0;
1185 }
1186
1187 static int sja1105_parse_ports_node(struct sja1105_private *priv,
1188                                     struct device_node *ports_node)
1189 {
1190         struct device *dev = &priv->spidev->dev;
1191         struct device_node *child;
1192
1193         for_each_available_child_of_node(ports_node, child) {
1194                 struct device_node *phy_node;
1195                 phy_interface_t phy_mode;
1196                 u32 index;
1197                 int err;
1198
1199                 /* Get switch port number from DT */
1200                 if (of_property_read_u32(child, "reg", &index) < 0) {
1201                         dev_err(dev, "Port number not defined in device tree "
1202                                 "(property \"reg\")\n");
1203                         of_node_put(child);
1204                         return -ENODEV;
1205                 }
1206
1207                 /* Get PHY mode from DT */
1208                 err = of_get_phy_mode(child, &phy_mode);
1209                 if (err) {
1210                         dev_err(dev, "Failed to read phy-mode or "
1211                                 "phy-interface-type property for port %d\n",
1212                                 index);
1213                         of_node_put(child);
1214                         return -ENODEV;
1215                 }
1216
1217                 phy_node = of_parse_phandle(child, "phy-handle", 0);
1218                 if (!phy_node) {
1219                         if (!of_phy_is_fixed_link(child)) {
1220                                 dev_err(dev, "phy-handle or fixed-link "
1221                                         "properties missing!\n");
1222                                 of_node_put(child);
1223                                 return -ENODEV;
1224                         }
1225                         /* phy-handle is missing, but fixed-link isn't.
1226                          * So it's a fixed link. Default to PHY role.
1227                          */
1228                         priv->fixed_link[index] = true;
1229                 } else {
1230                         of_node_put(phy_node);
1231                 }
1232
1233                 priv->phy_mode[index] = phy_mode;
1234
1235                 err = sja1105_parse_rgmii_delays(priv, index, child);
1236                 if (err) {
1237                         of_node_put(child);
1238                         return err;
1239                 }
1240         }
1241
1242         return 0;
1243 }
1244
1245 static int sja1105_parse_dt(struct sja1105_private *priv)
1246 {
1247         struct device *dev = &priv->spidev->dev;
1248         struct device_node *switch_node = dev->of_node;
1249         struct device_node *ports_node;
1250         int rc;
1251
1252         ports_node = of_get_child_by_name(switch_node, "ports");
1253         if (!ports_node)
1254                 ports_node = of_get_child_by_name(switch_node, "ethernet-ports");
1255         if (!ports_node) {
1256                 dev_err(dev, "Incorrect bindings: absent \"ports\" node\n");
1257                 return -ENODEV;
1258         }
1259
1260         rc = sja1105_parse_ports_node(priv, ports_node);
1261         of_node_put(ports_node);
1262
1263         return rc;
1264 }
1265
1266 /* Convert link speed from SJA1105 to ethtool encoding */
1267 static int sja1105_port_speed_to_ethtool(struct sja1105_private *priv,
1268                                          u64 speed)
1269 {
1270         if (speed == priv->info->port_speed[SJA1105_SPEED_10MBPS])
1271                 return SPEED_10;
1272         if (speed == priv->info->port_speed[SJA1105_SPEED_100MBPS])
1273                 return SPEED_100;
1274         if (speed == priv->info->port_speed[SJA1105_SPEED_1000MBPS])
1275                 return SPEED_1000;
1276         if (speed == priv->info->port_speed[SJA1105_SPEED_2500MBPS])
1277                 return SPEED_2500;
1278         return SPEED_UNKNOWN;
1279 }
1280
1281 /* Set link speed in the MAC configuration for a specific port. */
1282 static int sja1105_adjust_port_config(struct sja1105_private *priv, int port,
1283                                       int speed_mbps)
1284 {
1285         struct sja1105_mac_config_entry *mac;
1286         struct device *dev = priv->ds->dev;
1287         u64 speed;
1288         int rc;
1289
1290         /* On P/Q/R/S, one can read from the device via the MAC reconfiguration
1291          * tables. On E/T, MAC reconfig tables are not readable, only writable.
1292          * We have to *know* what the MAC looks like.  For the sake of keeping
1293          * the code common, we'll use the static configuration tables as a
1294          * reasonable approximation for both E/T and P/Q/R/S.
1295          */
1296         mac = priv->static_config.tables[BLK_IDX_MAC_CONFIG].entries;
1297
1298         switch (speed_mbps) {
1299         case SPEED_UNKNOWN:
1300                 /* PHYLINK called sja1105_mac_config() to inform us about
1301                  * the state->interface, but AN has not completed and the
1302                  * speed is not yet valid. UM10944.pdf says that setting
1303                  * SJA1105_SPEED_AUTO at runtime disables the port, so that is
1304                  * ok for power consumption in case AN will never complete -
1305                  * otherwise PHYLINK should come back with a new update.
1306                  */
1307                 speed = priv->info->port_speed[SJA1105_SPEED_AUTO];
1308                 break;
1309         case SPEED_10:
1310                 speed = priv->info->port_speed[SJA1105_SPEED_10MBPS];
1311                 break;
1312         case SPEED_100:
1313                 speed = priv->info->port_speed[SJA1105_SPEED_100MBPS];
1314                 break;
1315         case SPEED_1000:
1316                 speed = priv->info->port_speed[SJA1105_SPEED_1000MBPS];
1317                 break;
1318         case SPEED_2500:
1319                 speed = priv->info->port_speed[SJA1105_SPEED_2500MBPS];
1320                 break;
1321         default:
1322                 dev_err(dev, "Invalid speed %iMbps\n", speed_mbps);
1323                 return -EINVAL;
1324         }
1325
1326         /* Overwrite SJA1105_SPEED_AUTO from the static MAC configuration
1327          * table, since this will be used for the clocking setup, and we no
1328          * longer need to store it in the static config (already told hardware
1329          * we want auto during upload phase).
1330          * Actually for the SGMII port, the MAC is fixed at 1 Gbps and
1331          * we need to configure the PCS only (if even that).
1332          */
1333         if (priv->phy_mode[port] == PHY_INTERFACE_MODE_SGMII)
1334                 mac[port].speed = priv->info->port_speed[SJA1105_SPEED_1000MBPS];
1335         else if (priv->phy_mode[port] == PHY_INTERFACE_MODE_2500BASEX)
1336                 mac[port].speed = priv->info->port_speed[SJA1105_SPEED_2500MBPS];
1337         else
1338                 mac[port].speed = speed;
1339
1340         /* Write to the dynamic reconfiguration tables */
1341         rc = sja1105_dynamic_config_write(priv, BLK_IDX_MAC_CONFIG, port,
1342                                           &mac[port], true);
1343         if (rc < 0) {
1344                 dev_err(dev, "Failed to write MAC config: %d\n", rc);
1345                 return rc;
1346         }
1347
1348         /* Reconfigure the PLLs for the RGMII interfaces (required 125 MHz at
1349          * gigabit, 25 MHz at 100 Mbps and 2.5 MHz at 10 Mbps). For MII and
1350          * RMII no change of the clock setup is required. Actually, changing
1351          * the clock setup does interrupt the clock signal for a certain time
1352          * which causes trouble for all PHYs relying on this signal.
1353          */
1354         if (!phy_interface_mode_is_rgmii(priv->phy_mode[port]))
1355                 return 0;
1356
1357         return sja1105_clocking_setup_port(priv, port);
1358 }
1359
1360 /* The SJA1105 MAC programming model is through the static config (the xMII
1361  * Mode table cannot be dynamically reconfigured), and we have to program
1362  * that early (earlier than PHYLINK calls us, anyway).
1363  * So just error out in case the connected PHY attempts to change the initial
1364  * system interface MII protocol from what is defined in the DT, at least for
1365  * now.
1366  */
1367 static bool sja1105_phy_mode_mismatch(struct sja1105_private *priv, int port,
1368                                       phy_interface_t interface)
1369 {
1370         return priv->phy_mode[port] != interface;
1371 }
1372
1373 static void sja1105_mac_config(struct dsa_switch *ds, int port,
1374                                unsigned int mode,
1375                                const struct phylink_link_state *state)
1376 {
1377         struct dsa_port *dp = dsa_to_port(ds, port);
1378         struct sja1105_private *priv = ds->priv;
1379         struct dw_xpcs *xpcs;
1380
1381         if (sja1105_phy_mode_mismatch(priv, port, state->interface)) {
1382                 dev_err(ds->dev, "Changing PHY mode to %s not supported!\n",
1383                         phy_modes(state->interface));
1384                 return;
1385         }
1386
1387         xpcs = priv->xpcs[port];
1388
1389         if (xpcs)
1390                 phylink_set_pcs(dp->pl, &xpcs->pcs);
1391 }
1392
1393 static void sja1105_mac_link_down(struct dsa_switch *ds, int port,
1394                                   unsigned int mode,
1395                                   phy_interface_t interface)
1396 {
1397         sja1105_inhibit_tx(ds->priv, BIT(port), true);
1398 }
1399
1400 static void sja1105_mac_link_up(struct dsa_switch *ds, int port,
1401                                 unsigned int mode,
1402                                 phy_interface_t interface,
1403                                 struct phy_device *phydev,
1404                                 int speed, int duplex,
1405                                 bool tx_pause, bool rx_pause)
1406 {
1407         struct sja1105_private *priv = ds->priv;
1408
1409         sja1105_adjust_port_config(priv, port, speed);
1410
1411         sja1105_inhibit_tx(priv, BIT(port), false);
1412 }
1413
1414 static void sja1105_phylink_validate(struct dsa_switch *ds, int port,
1415                                      unsigned long *supported,
1416                                      struct phylink_link_state *state)
1417 {
1418         /* Construct a new mask which exhaustively contains all link features
1419          * supported by the MAC, and then apply that (logical AND) to what will
1420          * be sent to the PHY for "marketing".
1421          */
1422         __ETHTOOL_DECLARE_LINK_MODE_MASK(mask) = { 0, };
1423         struct sja1105_private *priv = ds->priv;
1424         struct sja1105_xmii_params_entry *mii;
1425
1426         mii = priv->static_config.tables[BLK_IDX_XMII_PARAMS].entries;
1427
1428         /* include/linux/phylink.h says:
1429          *     When @state->interface is %PHY_INTERFACE_MODE_NA, phylink
1430          *     expects the MAC driver to return all supported link modes.
1431          */
1432         if (state->interface != PHY_INTERFACE_MODE_NA &&
1433             sja1105_phy_mode_mismatch(priv, port, state->interface)) {
1434                 linkmode_zero(supported);
1435                 return;
1436         }
1437
1438         /* The MAC does not support pause frames, and also doesn't
1439          * support half-duplex traffic modes.
1440          */
1441         phylink_set(mask, Autoneg);
1442         phylink_set(mask, MII);
1443         phylink_set(mask, 10baseT_Full);
1444         phylink_set(mask, 100baseT_Full);
1445         phylink_set(mask, 100baseT1_Full);
1446         if (mii->xmii_mode[port] == XMII_MODE_RGMII ||
1447             mii->xmii_mode[port] == XMII_MODE_SGMII)
1448                 phylink_set(mask, 1000baseT_Full);
1449         if (priv->info->supports_2500basex[port]) {
1450                 phylink_set(mask, 2500baseT_Full);
1451                 phylink_set(mask, 2500baseX_Full);
1452         }
1453
1454         linkmode_and(supported, supported, mask);
1455         linkmode_and(state->advertising, state->advertising, mask);
1456 }
1457
1458 static int
1459 sja1105_find_static_fdb_entry(struct sja1105_private *priv, int port,
1460                               const struct sja1105_l2_lookup_entry *requested)
1461 {
1462         struct sja1105_l2_lookup_entry *l2_lookup;
1463         struct sja1105_table *table;
1464         int i;
1465
1466         table = &priv->static_config.tables[BLK_IDX_L2_LOOKUP];
1467         l2_lookup = table->entries;
1468
1469         for (i = 0; i < table->entry_count; i++)
1470                 if (l2_lookup[i].macaddr == requested->macaddr &&
1471                     l2_lookup[i].vlanid == requested->vlanid &&
1472                     l2_lookup[i].destports & BIT(port))
1473                         return i;
1474
1475         return -1;
1476 }
1477
1478 /* We want FDB entries added statically through the bridge command to persist
1479  * across switch resets, which are a common thing during normal SJA1105
1480  * operation. So we have to back them up in the static configuration tables
1481  * and hence apply them on next static config upload... yay!
1482  */
1483 static int
1484 sja1105_static_fdb_change(struct sja1105_private *priv, int port,
1485                           const struct sja1105_l2_lookup_entry *requested,
1486                           bool keep)
1487 {
1488         struct sja1105_l2_lookup_entry *l2_lookup;
1489         struct sja1105_table *table;
1490         int rc, match;
1491
1492         table = &priv->static_config.tables[BLK_IDX_L2_LOOKUP];
1493
1494         match = sja1105_find_static_fdb_entry(priv, port, requested);
1495         if (match < 0) {
1496                 /* Can't delete a missing entry. */
1497                 if (!keep)
1498                         return 0;
1499
1500                 /* No match => new entry */
1501                 rc = sja1105_table_resize(table, table->entry_count + 1);
1502                 if (rc)
1503                         return rc;
1504
1505                 match = table->entry_count - 1;
1506         }
1507
1508         /* Assign pointer after the resize (it may be new memory) */
1509         l2_lookup = table->entries;
1510
1511         /* We have a match.
1512          * If the job was to add this FDB entry, it's already done (mostly
1513          * anyway, since the port forwarding mask may have changed, case in
1514          * which we update it).
1515          * Otherwise we have to delete it.
1516          */
1517         if (keep) {
1518                 l2_lookup[match] = *requested;
1519                 return 0;
1520         }
1521
1522         /* To remove, the strategy is to overwrite the element with
1523          * the last one, and then reduce the array size by 1
1524          */
1525         l2_lookup[match] = l2_lookup[table->entry_count - 1];
1526         return sja1105_table_resize(table, table->entry_count - 1);
1527 }
1528
1529 /* First-generation switches have a 4-way set associative TCAM that
1530  * holds the FDB entries. An FDB index spans from 0 to 1023 and is comprised of
1531  * a "bin" (grouping of 4 entries) and a "way" (an entry within a bin).
1532  * For the placement of a newly learnt FDB entry, the switch selects the bin
1533  * based on a hash function, and the way within that bin incrementally.
1534  */
1535 static int sja1105et_fdb_index(int bin, int way)
1536 {
1537         return bin * SJA1105ET_FDB_BIN_SIZE + way;
1538 }
1539
1540 static int sja1105et_is_fdb_entry_in_bin(struct sja1105_private *priv, int bin,
1541                                          const u8 *addr, u16 vid,
1542                                          struct sja1105_l2_lookup_entry *match,
1543                                          int *last_unused)
1544 {
1545         int way;
1546
1547         for (way = 0; way < SJA1105ET_FDB_BIN_SIZE; way++) {
1548                 struct sja1105_l2_lookup_entry l2_lookup = {0};
1549                 int index = sja1105et_fdb_index(bin, way);
1550
1551                 /* Skip unused entries, optionally marking them
1552                  * into the return value
1553                  */
1554                 if (sja1105_dynamic_config_read(priv, BLK_IDX_L2_LOOKUP,
1555                                                 index, &l2_lookup)) {
1556                         if (last_unused)
1557                                 *last_unused = way;
1558                         continue;
1559                 }
1560
1561                 if (l2_lookup.macaddr == ether_addr_to_u64(addr) &&
1562                     l2_lookup.vlanid == vid) {
1563                         if (match)
1564                                 *match = l2_lookup;
1565                         return way;
1566                 }
1567         }
1568         /* Return an invalid entry index if not found */
1569         return -1;
1570 }
1571
1572 int sja1105et_fdb_add(struct dsa_switch *ds, int port,
1573                       const unsigned char *addr, u16 vid)
1574 {
1575         struct sja1105_l2_lookup_entry l2_lookup = {0}, tmp;
1576         struct sja1105_private *priv = ds->priv;
1577         struct device *dev = ds->dev;
1578         int last_unused = -1;
1579         int start, end, i;
1580         int bin, way, rc;
1581
1582         bin = sja1105et_fdb_hash(priv, addr, vid);
1583
1584         way = sja1105et_is_fdb_entry_in_bin(priv, bin, addr, vid,
1585                                             &l2_lookup, &last_unused);
1586         if (way >= 0) {
1587                 /* We have an FDB entry. Is our port in the destination
1588                  * mask? If yes, we need to do nothing. If not, we need
1589                  * to rewrite the entry by adding this port to it.
1590                  */
1591                 if ((l2_lookup.destports & BIT(port)) && l2_lookup.lockeds)
1592                         return 0;
1593                 l2_lookup.destports |= BIT(port);
1594         } else {
1595                 int index = sja1105et_fdb_index(bin, way);
1596
1597                 /* We don't have an FDB entry. We construct a new one and
1598                  * try to find a place for it within the FDB table.
1599                  */
1600                 l2_lookup.macaddr = ether_addr_to_u64(addr);
1601                 l2_lookup.destports = BIT(port);
1602                 l2_lookup.vlanid = vid;
1603
1604                 if (last_unused >= 0) {
1605                         way = last_unused;
1606                 } else {
1607                         /* Bin is full, need to evict somebody.
1608                          * Choose victim at random. If you get these messages
1609                          * often, you may need to consider changing the
1610                          * distribution function:
1611                          * static_config[BLK_IDX_L2_LOOKUP_PARAMS].entries->poly
1612                          */
1613                         get_random_bytes(&way, sizeof(u8));
1614                         way %= SJA1105ET_FDB_BIN_SIZE;
1615                         dev_warn(dev, "Warning, FDB bin %d full while adding entry for %pM. Evicting entry %u.\n",
1616                                  bin, addr, way);
1617                         /* Evict entry */
1618                         sja1105_dynamic_config_write(priv, BLK_IDX_L2_LOOKUP,
1619                                                      index, NULL, false);
1620                 }
1621         }
1622         l2_lookup.lockeds = true;
1623         l2_lookup.index = sja1105et_fdb_index(bin, way);
1624
1625         rc = sja1105_dynamic_config_write(priv, BLK_IDX_L2_LOOKUP,
1626                                           l2_lookup.index, &l2_lookup,
1627                                           true);
1628         if (rc < 0)
1629                 return rc;
1630
1631         /* Invalidate a dynamically learned entry if that exists */
1632         start = sja1105et_fdb_index(bin, 0);
1633         end = sja1105et_fdb_index(bin, way);
1634
1635         for (i = start; i < end; i++) {
1636                 rc = sja1105_dynamic_config_read(priv, BLK_IDX_L2_LOOKUP,
1637                                                  i, &tmp);
1638                 if (rc == -ENOENT)
1639                         continue;
1640                 if (rc)
1641                         return rc;
1642
1643                 if (tmp.macaddr != ether_addr_to_u64(addr) || tmp.vlanid != vid)
1644                         continue;
1645
1646                 rc = sja1105_dynamic_config_write(priv, BLK_IDX_L2_LOOKUP,
1647                                                   i, NULL, false);
1648                 if (rc)
1649                         return rc;
1650
1651                 break;
1652         }
1653
1654         return sja1105_static_fdb_change(priv, port, &l2_lookup, true);
1655 }
1656
1657 int sja1105et_fdb_del(struct dsa_switch *ds, int port,
1658                       const unsigned char *addr, u16 vid)
1659 {
1660         struct sja1105_l2_lookup_entry l2_lookup = {0};
1661         struct sja1105_private *priv = ds->priv;
1662         int index, bin, way, rc;
1663         bool keep;
1664
1665         bin = sja1105et_fdb_hash(priv, addr, vid);
1666         way = sja1105et_is_fdb_entry_in_bin(priv, bin, addr, vid,
1667                                             &l2_lookup, NULL);
1668         if (way < 0)
1669                 return 0;
1670         index = sja1105et_fdb_index(bin, way);
1671
1672         /* We have an FDB entry. Is our port in the destination mask? If yes,
1673          * we need to remove it. If the resulting port mask becomes empty, we
1674          * need to completely evict the FDB entry.
1675          * Otherwise we just write it back.
1676          */
1677         l2_lookup.destports &= ~BIT(port);
1678
1679         if (l2_lookup.destports)
1680                 keep = true;
1681         else
1682                 keep = false;
1683
1684         rc = sja1105_dynamic_config_write(priv, BLK_IDX_L2_LOOKUP,
1685                                           index, &l2_lookup, keep);
1686         if (rc < 0)
1687                 return rc;
1688
1689         return sja1105_static_fdb_change(priv, port, &l2_lookup, keep);
1690 }
1691
1692 int sja1105pqrs_fdb_add(struct dsa_switch *ds, int port,
1693                         const unsigned char *addr, u16 vid)
1694 {
1695         struct sja1105_l2_lookup_entry l2_lookup = {0}, tmp;
1696         struct sja1105_private *priv = ds->priv;
1697         int rc, i;
1698
1699         /* Search for an existing entry in the FDB table */
1700         l2_lookup.macaddr = ether_addr_to_u64(addr);
1701         l2_lookup.vlanid = vid;
1702         l2_lookup.mask_macaddr = GENMASK_ULL(ETH_ALEN * 8 - 1, 0);
1703         l2_lookup.mask_vlanid = VLAN_VID_MASK;
1704         l2_lookup.destports = BIT(port);
1705
1706         tmp = l2_lookup;
1707
1708         rc = sja1105_dynamic_config_read(priv, BLK_IDX_L2_LOOKUP,
1709                                          SJA1105_SEARCH, &tmp);
1710         if (rc == 0 && tmp.index != SJA1105_MAX_L2_LOOKUP_COUNT - 1) {
1711                 /* Found a static entry and this port is already in the entry's
1712                  * port mask => job done
1713                  */
1714                 if ((tmp.destports & BIT(port)) && tmp.lockeds)
1715                         return 0;
1716
1717                 l2_lookup = tmp;
1718
1719                 /* l2_lookup.index is populated by the switch in case it
1720                  * found something.
1721                  */
1722                 l2_lookup.destports |= BIT(port);
1723                 goto skip_finding_an_index;
1724         }
1725
1726         /* Not found, so try to find an unused spot in the FDB.
1727          * This is slightly inefficient because the strategy is knock-knock at
1728          * every possible position from 0 to 1023.
1729          */
1730         for (i = 0; i < SJA1105_MAX_L2_LOOKUP_COUNT; i++) {
1731                 rc = sja1105_dynamic_config_read(priv, BLK_IDX_L2_LOOKUP,
1732                                                  i, NULL);
1733                 if (rc < 0)
1734                         break;
1735         }
1736         if (i == SJA1105_MAX_L2_LOOKUP_COUNT) {
1737                 dev_err(ds->dev, "FDB is full, cannot add entry.\n");
1738                 return -EINVAL;
1739         }
1740         l2_lookup.index = i;
1741
1742 skip_finding_an_index:
1743         l2_lookup.lockeds = true;
1744
1745         rc = sja1105_dynamic_config_write(priv, BLK_IDX_L2_LOOKUP,
1746                                           l2_lookup.index, &l2_lookup,
1747                                           true);
1748         if (rc < 0)
1749                 return rc;
1750
1751         /* The switch learns dynamic entries and looks up the FDB left to
1752          * right. It is possible that our addition was concurrent with the
1753          * dynamic learning of the same address, so now that the static entry
1754          * has been installed, we are certain that address learning for this
1755          * particular address has been turned off, so the dynamic entry either
1756          * is in the FDB at an index smaller than the static one, or isn't (it
1757          * can also be at a larger index, but in that case it is inactive
1758          * because the static FDB entry will match first, and the dynamic one
1759          * will eventually age out). Search for a dynamically learned address
1760          * prior to our static one and invalidate it.
1761          */
1762         tmp = l2_lookup;
1763
1764         rc = sja1105_dynamic_config_read(priv, BLK_IDX_L2_LOOKUP,
1765                                          SJA1105_SEARCH, &tmp);
1766         if (rc < 0) {
1767                 dev_err(ds->dev,
1768                         "port %d failed to read back entry for %pM vid %d: %pe\n",
1769                         port, addr, vid, ERR_PTR(rc));
1770                 return rc;
1771         }
1772
1773         if (tmp.index < l2_lookup.index) {
1774                 rc = sja1105_dynamic_config_write(priv, BLK_IDX_L2_LOOKUP,
1775                                                   tmp.index, NULL, false);
1776                 if (rc < 0)
1777                         return rc;
1778         }
1779
1780         return sja1105_static_fdb_change(priv, port, &l2_lookup, true);
1781 }
1782
1783 int sja1105pqrs_fdb_del(struct dsa_switch *ds, int port,
1784                         const unsigned char *addr, u16 vid)
1785 {
1786         struct sja1105_l2_lookup_entry l2_lookup = {0};
1787         struct sja1105_private *priv = ds->priv;
1788         bool keep;
1789         int rc;
1790
1791         l2_lookup.macaddr = ether_addr_to_u64(addr);
1792         l2_lookup.vlanid = vid;
1793         l2_lookup.mask_macaddr = GENMASK_ULL(ETH_ALEN * 8 - 1, 0);
1794         l2_lookup.mask_vlanid = VLAN_VID_MASK;
1795         l2_lookup.destports = BIT(port);
1796
1797         rc = sja1105_dynamic_config_read(priv, BLK_IDX_L2_LOOKUP,
1798                                          SJA1105_SEARCH, &l2_lookup);
1799         if (rc < 0)
1800                 return 0;
1801
1802         l2_lookup.destports &= ~BIT(port);
1803
1804         /* Decide whether we remove just this port from the FDB entry,
1805          * or if we remove it completely.
1806          */
1807         if (l2_lookup.destports)
1808                 keep = true;
1809         else
1810                 keep = false;
1811
1812         rc = sja1105_dynamic_config_write(priv, BLK_IDX_L2_LOOKUP,
1813                                           l2_lookup.index, &l2_lookup, keep);
1814         if (rc < 0)
1815                 return rc;
1816
1817         return sja1105_static_fdb_change(priv, port, &l2_lookup, keep);
1818 }
1819
1820 static int sja1105_fdb_add(struct dsa_switch *ds, int port,
1821                            const unsigned char *addr, u16 vid)
1822 {
1823         struct sja1105_private *priv = ds->priv;
1824
1825         return priv->info->fdb_add_cmd(ds, port, addr, vid);
1826 }
1827
1828 static int sja1105_fdb_del(struct dsa_switch *ds, int port,
1829                            const unsigned char *addr, u16 vid)
1830 {
1831         struct sja1105_private *priv = ds->priv;
1832
1833         return priv->info->fdb_del_cmd(ds, port, addr, vid);
1834 }
1835
1836 static int sja1105_fdb_dump(struct dsa_switch *ds, int port,
1837                             dsa_fdb_dump_cb_t *cb, void *data)
1838 {
1839         struct dsa_port *dp = dsa_to_port(ds, port);
1840         struct sja1105_private *priv = ds->priv;
1841         struct device *dev = ds->dev;
1842         int i;
1843
1844         for (i = 0; i < SJA1105_MAX_L2_LOOKUP_COUNT; i++) {
1845                 struct sja1105_l2_lookup_entry l2_lookup = {0};
1846                 u8 macaddr[ETH_ALEN];
1847                 int rc;
1848
1849                 rc = sja1105_dynamic_config_read(priv, BLK_IDX_L2_LOOKUP,
1850                                                  i, &l2_lookup);
1851                 /* No fdb entry at i, not an issue */
1852                 if (rc == -ENOENT)
1853                         continue;
1854                 if (rc) {
1855                         dev_err(dev, "Failed to dump FDB: %d\n", rc);
1856                         return rc;
1857                 }
1858
1859                 /* FDB dump callback is per port. This means we have to
1860                  * disregard a valid entry if it's not for this port, even if
1861                  * only to revisit it later. This is inefficient because the
1862                  * 1024-sized FDB table needs to be traversed 4 times through
1863                  * SPI during a 'bridge fdb show' command.
1864                  */
1865                 if (!(l2_lookup.destports & BIT(port)))
1866                         continue;
1867
1868                 /* We need to hide the FDB entry for unknown multicast */
1869                 if (l2_lookup.macaddr == SJA1105_UNKNOWN_MULTICAST &&
1870                     l2_lookup.mask_macaddr == SJA1105_UNKNOWN_MULTICAST)
1871                         continue;
1872
1873                 u64_to_ether_addr(l2_lookup.macaddr, macaddr);
1874
1875                 /* We need to hide the dsa_8021q VLANs from the user. */
1876                 if (!dsa_port_is_vlan_filtering(dp))
1877                         l2_lookup.vlanid = 0;
1878                 rc = cb(macaddr, l2_lookup.vlanid, l2_lookup.lockeds, data);
1879                 if (rc)
1880                         return rc;
1881         }
1882         return 0;
1883 }
1884
1885 static void sja1105_fast_age(struct dsa_switch *ds, int port)
1886 {
1887         struct sja1105_private *priv = ds->priv;
1888         int i;
1889
1890         for (i = 0; i < SJA1105_MAX_L2_LOOKUP_COUNT; i++) {
1891                 struct sja1105_l2_lookup_entry l2_lookup = {0};
1892                 u8 macaddr[ETH_ALEN];
1893                 int rc;
1894
1895                 rc = sja1105_dynamic_config_read(priv, BLK_IDX_L2_LOOKUP,
1896                                                  i, &l2_lookup);
1897                 /* No fdb entry at i, not an issue */
1898                 if (rc == -ENOENT)
1899                         continue;
1900                 if (rc) {
1901                         dev_err(ds->dev, "Failed to read FDB: %pe\n",
1902                                 ERR_PTR(rc));
1903                         return;
1904                 }
1905
1906                 if (!(l2_lookup.destports & BIT(port)))
1907                         continue;
1908
1909                 /* Don't delete static FDB entries */
1910                 if (l2_lookup.lockeds)
1911                         continue;
1912
1913                 u64_to_ether_addr(l2_lookup.macaddr, macaddr);
1914
1915                 rc = sja1105_fdb_del(ds, port, macaddr, l2_lookup.vlanid);
1916                 if (rc) {
1917                         dev_err(ds->dev,
1918                                 "Failed to delete FDB entry %pM vid %lld: %pe\n",
1919                                 macaddr, l2_lookup.vlanid, ERR_PTR(rc));
1920                         return;
1921                 }
1922         }
1923 }
1924
1925 static int sja1105_mdb_add(struct dsa_switch *ds, int port,
1926                            const struct switchdev_obj_port_mdb *mdb)
1927 {
1928         return sja1105_fdb_add(ds, port, mdb->addr, mdb->vid);
1929 }
1930
1931 static int sja1105_mdb_del(struct dsa_switch *ds, int port,
1932                            const struct switchdev_obj_port_mdb *mdb)
1933 {
1934         return sja1105_fdb_del(ds, port, mdb->addr, mdb->vid);
1935 }
1936
1937 /* Common function for unicast and broadcast flood configuration.
1938  * Flooding is configured between each {ingress, egress} port pair, and since
1939  * the bridge's semantics are those of "egress flooding", it means we must
1940  * enable flooding towards this port from all ingress ports that are in the
1941  * same forwarding domain.
1942  */
1943 static int sja1105_manage_flood_domains(struct sja1105_private *priv)
1944 {
1945         struct sja1105_l2_forwarding_entry *l2_fwd;
1946         struct dsa_switch *ds = priv->ds;
1947         int from, to, rc;
1948
1949         l2_fwd = priv->static_config.tables[BLK_IDX_L2_FORWARDING].entries;
1950
1951         for (from = 0; from < ds->num_ports; from++) {
1952                 u64 fl_domain = 0, bc_domain = 0;
1953
1954                 for (to = 0; to < priv->ds->num_ports; to++) {
1955                         if (!sja1105_can_forward(l2_fwd, from, to))
1956                                 continue;
1957
1958                         if (priv->ucast_egress_floods & BIT(to))
1959                                 fl_domain |= BIT(to);
1960                         if (priv->bcast_egress_floods & BIT(to))
1961                                 bc_domain |= BIT(to);
1962                 }
1963
1964                 /* Nothing changed, nothing to do */
1965                 if (l2_fwd[from].fl_domain == fl_domain &&
1966                     l2_fwd[from].bc_domain == bc_domain)
1967                         continue;
1968
1969                 l2_fwd[from].fl_domain = fl_domain;
1970                 l2_fwd[from].bc_domain = bc_domain;
1971
1972                 rc = sja1105_dynamic_config_write(priv, BLK_IDX_L2_FORWARDING,
1973                                                   from, &l2_fwd[from], true);
1974                 if (rc < 0)
1975                         return rc;
1976         }
1977
1978         return 0;
1979 }
1980
1981 static int sja1105_bridge_member(struct dsa_switch *ds, int port,
1982                                  struct net_device *br, bool member)
1983 {
1984         struct sja1105_l2_forwarding_entry *l2_fwd;
1985         struct sja1105_private *priv = ds->priv;
1986         int i, rc;
1987
1988         l2_fwd = priv->static_config.tables[BLK_IDX_L2_FORWARDING].entries;
1989
1990         for (i = 0; i < ds->num_ports; i++) {
1991                 /* Add this port to the forwarding matrix of the
1992                  * other ports in the same bridge, and viceversa.
1993                  */
1994                 if (!dsa_is_user_port(ds, i))
1995                         continue;
1996                 /* For the ports already under the bridge, only one thing needs
1997                  * to be done, and that is to add this port to their
1998                  * reachability domain. So we can perform the SPI write for
1999                  * them immediately. However, for this port itself (the one
2000                  * that is new to the bridge), we need to add all other ports
2001                  * to its reachability domain. So we do that incrementally in
2002                  * this loop, and perform the SPI write only at the end, once
2003                  * the domain contains all other bridge ports.
2004                  */
2005                 if (i == port)
2006                         continue;
2007                 if (dsa_to_port(ds, i)->bridge_dev != br)
2008                         continue;
2009                 sja1105_port_allow_traffic(l2_fwd, i, port, member);
2010                 sja1105_port_allow_traffic(l2_fwd, port, i, member);
2011
2012                 rc = sja1105_dynamic_config_write(priv, BLK_IDX_L2_FORWARDING,
2013                                                   i, &l2_fwd[i], true);
2014                 if (rc < 0)
2015                         return rc;
2016         }
2017
2018         rc = sja1105_dynamic_config_write(priv, BLK_IDX_L2_FORWARDING,
2019                                           port, &l2_fwd[port], true);
2020         if (rc)
2021                 return rc;
2022
2023         rc = sja1105_commit_pvid(ds, port);
2024         if (rc)
2025                 return rc;
2026
2027         return sja1105_manage_flood_domains(priv);
2028 }
2029
2030 static void sja1105_bridge_stp_state_set(struct dsa_switch *ds, int port,
2031                                          u8 state)
2032 {
2033         struct dsa_port *dp = dsa_to_port(ds, port);
2034         struct sja1105_private *priv = ds->priv;
2035         struct sja1105_mac_config_entry *mac;
2036
2037         mac = priv->static_config.tables[BLK_IDX_MAC_CONFIG].entries;
2038
2039         switch (state) {
2040         case BR_STATE_DISABLED:
2041         case BR_STATE_BLOCKING:
2042                 /* From UM10944 description of DRPDTAG (why put this there?):
2043                  * "Management traffic flows to the port regardless of the state
2044                  * of the INGRESS flag". So BPDUs are still be allowed to pass.
2045                  * At the moment no difference between DISABLED and BLOCKING.
2046                  */
2047                 mac[port].ingress   = false;
2048                 mac[port].egress    = false;
2049                 mac[port].dyn_learn = false;
2050                 break;
2051         case BR_STATE_LISTENING:
2052                 mac[port].ingress   = true;
2053                 mac[port].egress    = false;
2054                 mac[port].dyn_learn = false;
2055                 break;
2056         case BR_STATE_LEARNING:
2057                 mac[port].ingress   = true;
2058                 mac[port].egress    = false;
2059                 mac[port].dyn_learn = dp->learning;
2060                 break;
2061         case BR_STATE_FORWARDING:
2062                 mac[port].ingress   = true;
2063                 mac[port].egress    = true;
2064                 mac[port].dyn_learn = dp->learning;
2065                 break;
2066         default:
2067                 dev_err(ds->dev, "invalid STP state: %d\n", state);
2068                 return;
2069         }
2070
2071         sja1105_dynamic_config_write(priv, BLK_IDX_MAC_CONFIG, port,
2072                                      &mac[port], true);
2073 }
2074
2075 static int sja1105_bridge_join(struct dsa_switch *ds, int port,
2076                                struct net_device *br)
2077 {
2078         return sja1105_bridge_member(ds, port, br, true);
2079 }
2080
2081 static void sja1105_bridge_leave(struct dsa_switch *ds, int port,
2082                                  struct net_device *br)
2083 {
2084         sja1105_bridge_member(ds, port, br, false);
2085 }
2086
2087 #define BYTES_PER_KBIT (1000LL / 8)
2088
2089 static int sja1105_find_unused_cbs_shaper(struct sja1105_private *priv)
2090 {
2091         int i;
2092
2093         for (i = 0; i < priv->info->num_cbs_shapers; i++)
2094                 if (!priv->cbs[i].idle_slope && !priv->cbs[i].send_slope)
2095                         return i;
2096
2097         return -1;
2098 }
2099
2100 static int sja1105_delete_cbs_shaper(struct sja1105_private *priv, int port,
2101                                      int prio)
2102 {
2103         int i;
2104
2105         for (i = 0; i < priv->info->num_cbs_shapers; i++) {
2106                 struct sja1105_cbs_entry *cbs = &priv->cbs[i];
2107
2108                 if (cbs->port == port && cbs->prio == prio) {
2109                         memset(cbs, 0, sizeof(*cbs));
2110                         return sja1105_dynamic_config_write(priv, BLK_IDX_CBS,
2111                                                             i, cbs, true);
2112                 }
2113         }
2114
2115         return 0;
2116 }
2117
2118 static int sja1105_setup_tc_cbs(struct dsa_switch *ds, int port,
2119                                 struct tc_cbs_qopt_offload *offload)
2120 {
2121         struct sja1105_private *priv = ds->priv;
2122         struct sja1105_cbs_entry *cbs;
2123         int index;
2124
2125         if (!offload->enable)
2126                 return sja1105_delete_cbs_shaper(priv, port, offload->queue);
2127
2128         index = sja1105_find_unused_cbs_shaper(priv);
2129         if (index < 0)
2130                 return -ENOSPC;
2131
2132         cbs = &priv->cbs[index];
2133         cbs->port = port;
2134         cbs->prio = offload->queue;
2135         /* locredit and sendslope are negative by definition. In hardware,
2136          * positive values must be provided, and the negative sign is implicit.
2137          */
2138         cbs->credit_hi = offload->hicredit;
2139         cbs->credit_lo = abs(offload->locredit);
2140         /* User space is in kbits/sec, hardware in bytes/sec */
2141         cbs->idle_slope = offload->idleslope * BYTES_PER_KBIT;
2142         cbs->send_slope = abs(offload->sendslope * BYTES_PER_KBIT);
2143         /* Convert the negative values from 64-bit 2's complement
2144          * to 32-bit 2's complement (for the case of 0x80000000 whose
2145          * negative is still negative).
2146          */
2147         cbs->credit_lo &= GENMASK_ULL(31, 0);
2148         cbs->send_slope &= GENMASK_ULL(31, 0);
2149
2150         return sja1105_dynamic_config_write(priv, BLK_IDX_CBS, index, cbs,
2151                                             true);
2152 }
2153
2154 static int sja1105_reload_cbs(struct sja1105_private *priv)
2155 {
2156         int rc = 0, i;
2157
2158         /* The credit based shapers are only allocated if
2159          * CONFIG_NET_SCH_CBS is enabled.
2160          */
2161         if (!priv->cbs)
2162                 return 0;
2163
2164         for (i = 0; i < priv->info->num_cbs_shapers; i++) {
2165                 struct sja1105_cbs_entry *cbs = &priv->cbs[i];
2166
2167                 if (!cbs->idle_slope && !cbs->send_slope)
2168                         continue;
2169
2170                 rc = sja1105_dynamic_config_write(priv, BLK_IDX_CBS, i, cbs,
2171                                                   true);
2172                 if (rc)
2173                         break;
2174         }
2175
2176         return rc;
2177 }
2178
2179 static const char * const sja1105_reset_reasons[] = {
2180         [SJA1105_VLAN_FILTERING] = "VLAN filtering",
2181         [SJA1105_RX_HWTSTAMPING] = "RX timestamping",
2182         [SJA1105_AGEING_TIME] = "Ageing time",
2183         [SJA1105_SCHEDULING] = "Time-aware scheduling",
2184         [SJA1105_BEST_EFFORT_POLICING] = "Best-effort policing",
2185         [SJA1105_VIRTUAL_LINKS] = "Virtual links",
2186 };
2187
2188 /* For situations where we need to change a setting at runtime that is only
2189  * available through the static configuration, resetting the switch in order
2190  * to upload the new static config is unavoidable. Back up the settings we
2191  * modify at runtime (currently only MAC) and restore them after uploading,
2192  * such that this operation is relatively seamless.
2193  */
2194 int sja1105_static_config_reload(struct sja1105_private *priv,
2195                                  enum sja1105_reset_reason reason)
2196 {
2197         struct ptp_system_timestamp ptp_sts_before;
2198         struct ptp_system_timestamp ptp_sts_after;
2199         int speed_mbps[SJA1105_MAX_NUM_PORTS];
2200         u16 bmcr[SJA1105_MAX_NUM_PORTS] = {0};
2201         struct sja1105_mac_config_entry *mac;
2202         struct dsa_switch *ds = priv->ds;
2203         s64 t1, t2, t3, t4;
2204         s64 t12, t34;
2205         int rc, i;
2206         s64 now;
2207
2208         mutex_lock(&priv->mgmt_lock);
2209
2210         mac = priv->static_config.tables[BLK_IDX_MAC_CONFIG].entries;
2211
2212         /* Back up the dynamic link speed changed by sja1105_adjust_port_config
2213          * in order to temporarily restore it to SJA1105_SPEED_AUTO - which the
2214          * switch wants to see in the static config in order to allow us to
2215          * change it through the dynamic interface later.
2216          */
2217         for (i = 0; i < ds->num_ports; i++) {
2218                 u32 reg_addr = mdiobus_c45_addr(MDIO_MMD_VEND2, MDIO_CTRL1);
2219
2220                 speed_mbps[i] = sja1105_port_speed_to_ethtool(priv,
2221                                                               mac[i].speed);
2222                 mac[i].speed = priv->info->port_speed[SJA1105_SPEED_AUTO];
2223
2224                 if (priv->xpcs[i])
2225                         bmcr[i] = mdiobus_read(priv->mdio_pcs, i, reg_addr);
2226         }
2227
2228         /* No PTP operations can run right now */
2229         mutex_lock(&priv->ptp_data.lock);
2230
2231         rc = __sja1105_ptp_gettimex(ds, &now, &ptp_sts_before);
2232         if (rc < 0) {
2233                 mutex_unlock(&priv->ptp_data.lock);
2234                 goto out;
2235         }
2236
2237         /* Reset switch and send updated static configuration */
2238         rc = sja1105_static_config_upload(priv);
2239         if (rc < 0) {
2240                 mutex_unlock(&priv->ptp_data.lock);
2241                 goto out;
2242         }
2243
2244         rc = __sja1105_ptp_settime(ds, 0, &ptp_sts_after);
2245         if (rc < 0) {
2246                 mutex_unlock(&priv->ptp_data.lock);
2247                 goto out;
2248         }
2249
2250         t1 = timespec64_to_ns(&ptp_sts_before.pre_ts);
2251         t2 = timespec64_to_ns(&ptp_sts_before.post_ts);
2252         t3 = timespec64_to_ns(&ptp_sts_after.pre_ts);
2253         t4 = timespec64_to_ns(&ptp_sts_after.post_ts);
2254         /* Mid point, corresponds to pre-reset PTPCLKVAL */
2255         t12 = t1 + (t2 - t1) / 2;
2256         /* Mid point, corresponds to post-reset PTPCLKVAL, aka 0 */
2257         t34 = t3 + (t4 - t3) / 2;
2258         /* Advance PTPCLKVAL by the time it took since its readout */
2259         now += (t34 - t12);
2260
2261         __sja1105_ptp_adjtime(ds, now);
2262
2263         mutex_unlock(&priv->ptp_data.lock);
2264
2265         dev_info(priv->ds->dev,
2266                  "Reset switch and programmed static config. Reason: %s\n",
2267                  sja1105_reset_reasons[reason]);
2268
2269         /* Configure the CGU (PLLs) for MII and RMII PHYs.
2270          * For these interfaces there is no dynamic configuration
2271          * needed, since PLLs have same settings at all speeds.
2272          */
2273         if (priv->info->clocking_setup) {
2274                 rc = priv->info->clocking_setup(priv);
2275                 if (rc < 0)
2276                         goto out;
2277         }
2278
2279         for (i = 0; i < ds->num_ports; i++) {
2280                 struct dw_xpcs *xpcs = priv->xpcs[i];
2281                 unsigned int mode;
2282
2283                 rc = sja1105_adjust_port_config(priv, i, speed_mbps[i]);
2284                 if (rc < 0)
2285                         goto out;
2286
2287                 if (!xpcs)
2288                         continue;
2289
2290                 if (bmcr[i] & BMCR_ANENABLE)
2291                         mode = MLO_AN_INBAND;
2292                 else if (priv->fixed_link[i])
2293                         mode = MLO_AN_FIXED;
2294                 else
2295                         mode = MLO_AN_PHY;
2296
2297                 rc = xpcs_do_config(xpcs, priv->phy_mode[i], mode);
2298                 if (rc < 0)
2299                         goto out;
2300
2301                 if (!phylink_autoneg_inband(mode)) {
2302                         int speed = SPEED_UNKNOWN;
2303
2304                         if (priv->phy_mode[i] == PHY_INTERFACE_MODE_2500BASEX)
2305                                 speed = SPEED_2500;
2306                         else if (bmcr[i] & BMCR_SPEED1000)
2307                                 speed = SPEED_1000;
2308                         else if (bmcr[i] & BMCR_SPEED100)
2309                                 speed = SPEED_100;
2310                         else
2311                                 speed = SPEED_10;
2312
2313                         xpcs_link_up(&xpcs->pcs, mode, priv->phy_mode[i],
2314                                      speed, DUPLEX_FULL);
2315                 }
2316         }
2317
2318         rc = sja1105_reload_cbs(priv);
2319         if (rc < 0)
2320                 goto out;
2321 out:
2322         mutex_unlock(&priv->mgmt_lock);
2323
2324         return rc;
2325 }
2326
2327 static enum dsa_tag_protocol
2328 sja1105_get_tag_protocol(struct dsa_switch *ds, int port,
2329                          enum dsa_tag_protocol mp)
2330 {
2331         struct sja1105_private *priv = ds->priv;
2332
2333         return priv->info->tag_proto;
2334 }
2335
2336 /* The TPID setting belongs to the General Parameters table,
2337  * which can only be partially reconfigured at runtime (and not the TPID).
2338  * So a switch reset is required.
2339  */
2340 int sja1105_vlan_filtering(struct dsa_switch *ds, int port, bool enabled,
2341                            struct netlink_ext_ack *extack)
2342 {
2343         struct sja1105_l2_lookup_params_entry *l2_lookup_params;
2344         struct sja1105_general_params_entry *general_params;
2345         struct sja1105_private *priv = ds->priv;
2346         struct sja1105_table *table;
2347         struct sja1105_rule *rule;
2348         u16 tpid, tpid2;
2349         int rc;
2350
2351         list_for_each_entry(rule, &priv->flow_block.rules, list) {
2352                 if (rule->type == SJA1105_RULE_VL) {
2353                         NL_SET_ERR_MSG_MOD(extack,
2354                                            "Cannot change VLAN filtering with active VL rules");
2355                         return -EBUSY;
2356                 }
2357         }
2358
2359         if (enabled) {
2360                 /* Enable VLAN filtering. */
2361                 tpid  = ETH_P_8021Q;
2362                 tpid2 = ETH_P_8021AD;
2363         } else {
2364                 /* Disable VLAN filtering. */
2365                 tpid  = ETH_P_SJA1105;
2366                 tpid2 = ETH_P_SJA1105;
2367         }
2368
2369         table = &priv->static_config.tables[BLK_IDX_GENERAL_PARAMS];
2370         general_params = table->entries;
2371         /* EtherType used to identify inner tagged (C-tag) VLAN traffic */
2372         general_params->tpid = tpid;
2373         /* EtherType used to identify outer tagged (S-tag) VLAN traffic */
2374         general_params->tpid2 = tpid2;
2375         /* When VLAN filtering is on, we need to at least be able to
2376          * decode management traffic through the "backup plan".
2377          */
2378         general_params->incl_srcpt1 = enabled;
2379         general_params->incl_srcpt0 = enabled;
2380
2381         /* VLAN filtering => independent VLAN learning.
2382          * No VLAN filtering (or best effort) => shared VLAN learning.
2383          *
2384          * In shared VLAN learning mode, untagged traffic still gets
2385          * pvid-tagged, and the FDB table gets populated with entries
2386          * containing the "real" (pvid or from VLAN tag) VLAN ID.
2387          * However the switch performs a masked L2 lookup in the FDB,
2388          * effectively only looking up a frame's DMAC (and not VID) for the
2389          * forwarding decision.
2390          *
2391          * This is extremely convenient for us, because in modes with
2392          * vlan_filtering=0, dsa_8021q actually installs unique pvid's into
2393          * each front panel port. This is good for identification but breaks
2394          * learning badly - the VID of the learnt FDB entry is unique, aka
2395          * no frames coming from any other port are going to have it. So
2396          * for forwarding purposes, this is as though learning was broken
2397          * (all frames get flooded).
2398          */
2399         table = &priv->static_config.tables[BLK_IDX_L2_LOOKUP_PARAMS];
2400         l2_lookup_params = table->entries;
2401         l2_lookup_params->shared_learn = !enabled;
2402
2403         for (port = 0; port < ds->num_ports; port++) {
2404                 if (dsa_is_unused_port(ds, port))
2405                         continue;
2406
2407                 rc = sja1105_commit_pvid(ds, port);
2408                 if (rc)
2409                         return rc;
2410         }
2411
2412         rc = sja1105_static_config_reload(priv, SJA1105_VLAN_FILTERING);
2413         if (rc)
2414                 NL_SET_ERR_MSG_MOD(extack, "Failed to change VLAN Ethertype");
2415
2416         return rc;
2417 }
2418
2419 static int sja1105_vlan_add(struct sja1105_private *priv, int port, u16 vid,
2420                             u16 flags, bool allowed_ingress)
2421 {
2422         struct sja1105_vlan_lookup_entry *vlan;
2423         struct sja1105_table *table;
2424         int match, rc;
2425
2426         table = &priv->static_config.tables[BLK_IDX_VLAN_LOOKUP];
2427
2428         match = sja1105_is_vlan_configured(priv, vid);
2429         if (match < 0) {
2430                 rc = sja1105_table_resize(table, table->entry_count + 1);
2431                 if (rc)
2432                         return rc;
2433                 match = table->entry_count - 1;
2434         }
2435
2436         /* Assign pointer after the resize (it's new memory) */
2437         vlan = table->entries;
2438
2439         vlan[match].type_entry = SJA1110_VLAN_D_TAG;
2440         vlan[match].vlanid = vid;
2441         vlan[match].vlan_bc |= BIT(port);
2442
2443         if (allowed_ingress)
2444                 vlan[match].vmemb_port |= BIT(port);
2445         else
2446                 vlan[match].vmemb_port &= ~BIT(port);
2447
2448         if (flags & BRIDGE_VLAN_INFO_UNTAGGED)
2449                 vlan[match].tag_port &= ~BIT(port);
2450         else
2451                 vlan[match].tag_port |= BIT(port);
2452
2453         return sja1105_dynamic_config_write(priv, BLK_IDX_VLAN_LOOKUP, vid,
2454                                             &vlan[match], true);
2455 }
2456
2457 static int sja1105_vlan_del(struct sja1105_private *priv, int port, u16 vid)
2458 {
2459         struct sja1105_vlan_lookup_entry *vlan;
2460         struct sja1105_table *table;
2461         bool keep = true;
2462         int match, rc;
2463
2464         table = &priv->static_config.tables[BLK_IDX_VLAN_LOOKUP];
2465
2466         match = sja1105_is_vlan_configured(priv, vid);
2467         /* Can't delete a missing entry. */
2468         if (match < 0)
2469                 return 0;
2470
2471         /* Assign pointer after the resize (it's new memory) */
2472         vlan = table->entries;
2473
2474         vlan[match].vlanid = vid;
2475         vlan[match].vlan_bc &= ~BIT(port);
2476         vlan[match].vmemb_port &= ~BIT(port);
2477         /* Also unset tag_port, just so we don't have a confusing bitmap
2478          * (no practical purpose).
2479          */
2480         vlan[match].tag_port &= ~BIT(port);
2481
2482         /* If there's no port left as member of this VLAN,
2483          * it's time for it to go.
2484          */
2485         if (!vlan[match].vmemb_port)
2486                 keep = false;
2487
2488         rc = sja1105_dynamic_config_write(priv, BLK_IDX_VLAN_LOOKUP, vid,
2489                                           &vlan[match], keep);
2490         if (rc < 0)
2491                 return rc;
2492
2493         if (!keep)
2494                 return sja1105_table_delete_entry(table, match);
2495
2496         return 0;
2497 }
2498
2499 static int sja1105_bridge_vlan_add(struct dsa_switch *ds, int port,
2500                                    const struct switchdev_obj_port_vlan *vlan,
2501                                    struct netlink_ext_ack *extack)
2502 {
2503         struct sja1105_private *priv = ds->priv;
2504         u16 flags = vlan->flags;
2505         int rc;
2506
2507         /* Be sure to deny alterations to the configuration done by tag_8021q.
2508          */
2509         if (vid_is_dsa_8021q(vlan->vid)) {
2510                 NL_SET_ERR_MSG_MOD(extack,
2511                                    "Range 1024-3071 reserved for dsa_8021q operation");
2512                 return -EBUSY;
2513         }
2514
2515         /* Always install bridge VLANs as egress-tagged on CPU and DSA ports */
2516         if (dsa_is_cpu_port(ds, port) || dsa_is_dsa_port(ds, port))
2517                 flags = 0;
2518
2519         rc = sja1105_vlan_add(priv, port, vlan->vid, flags, true);
2520         if (rc)
2521                 return rc;
2522
2523         if (vlan->flags & BRIDGE_VLAN_INFO_PVID)
2524                 priv->bridge_pvid[port] = vlan->vid;
2525
2526         return sja1105_commit_pvid(ds, port);
2527 }
2528
2529 static int sja1105_bridge_vlan_del(struct dsa_switch *ds, int port,
2530                                    const struct switchdev_obj_port_vlan *vlan)
2531 {
2532         struct sja1105_private *priv = ds->priv;
2533         int rc;
2534
2535         rc = sja1105_vlan_del(priv, port, vlan->vid);
2536         if (rc)
2537                 return rc;
2538
2539         /* In case the pvid was deleted, make sure that untagged packets will
2540          * be dropped.
2541          */
2542         return sja1105_commit_pvid(ds, port);
2543 }
2544
2545 static int sja1105_dsa_8021q_vlan_add(struct dsa_switch *ds, int port, u16 vid,
2546                                       u16 flags)
2547 {
2548         struct sja1105_private *priv = ds->priv;
2549         bool allowed_ingress = true;
2550         int rc;
2551
2552         /* Prevent attackers from trying to inject a DSA tag from
2553          * the outside world.
2554          */
2555         if (dsa_is_user_port(ds, port))
2556                 allowed_ingress = false;
2557
2558         rc = sja1105_vlan_add(priv, port, vid, flags, allowed_ingress);
2559         if (rc)
2560                 return rc;
2561
2562         if (flags & BRIDGE_VLAN_INFO_PVID)
2563                 priv->tag_8021q_pvid[port] = vid;
2564
2565         return sja1105_commit_pvid(ds, port);
2566 }
2567
2568 static int sja1105_dsa_8021q_vlan_del(struct dsa_switch *ds, int port, u16 vid)
2569 {
2570         struct sja1105_private *priv = ds->priv;
2571
2572         return sja1105_vlan_del(priv, port, vid);
2573 }
2574
2575 static int sja1105_prechangeupper(struct dsa_switch *ds, int port,
2576                                   struct netdev_notifier_changeupper_info *info)
2577 {
2578         struct netlink_ext_ack *extack = info->info.extack;
2579         struct net_device *upper = info->upper_dev;
2580         struct dsa_switch_tree *dst = ds->dst;
2581         struct dsa_port *dp;
2582
2583         if (is_vlan_dev(upper)) {
2584                 NL_SET_ERR_MSG_MOD(extack, "8021q uppers are not supported");
2585                 return -EBUSY;
2586         }
2587
2588         if (netif_is_bridge_master(upper)) {
2589                 list_for_each_entry(dp, &dst->ports, list) {
2590                         if (dp->bridge_dev && dp->bridge_dev != upper &&
2591                             br_vlan_enabled(dp->bridge_dev)) {
2592                                 NL_SET_ERR_MSG_MOD(extack,
2593                                                    "Only one VLAN-aware bridge is supported");
2594                                 return -EBUSY;
2595                         }
2596                 }
2597         }
2598
2599         return 0;
2600 }
2601
2602 static void sja1105_port_disable(struct dsa_switch *ds, int port)
2603 {
2604         struct sja1105_private *priv = ds->priv;
2605         struct sja1105_port *sp = &priv->ports[port];
2606
2607         if (!dsa_is_user_port(ds, port))
2608                 return;
2609
2610         kthread_cancel_work_sync(&sp->xmit_work);
2611         skb_queue_purge(&sp->xmit_queue);
2612 }
2613
2614 static int sja1105_mgmt_xmit(struct dsa_switch *ds, int port, int slot,
2615                              struct sk_buff *skb, bool takets)
2616 {
2617         struct sja1105_mgmt_entry mgmt_route = {0};
2618         struct sja1105_private *priv = ds->priv;
2619         struct ethhdr *hdr;
2620         int timeout = 10;
2621         int rc;
2622
2623         hdr = eth_hdr(skb);
2624
2625         mgmt_route.macaddr = ether_addr_to_u64(hdr->h_dest);
2626         mgmt_route.destports = BIT(port);
2627         mgmt_route.enfport = 1;
2628         mgmt_route.tsreg = 0;
2629         mgmt_route.takets = takets;
2630
2631         rc = sja1105_dynamic_config_write(priv, BLK_IDX_MGMT_ROUTE,
2632                                           slot, &mgmt_route, true);
2633         if (rc < 0) {
2634                 kfree_skb(skb);
2635                 return rc;
2636         }
2637
2638         /* Transfer skb to the host port. */
2639         dsa_enqueue_skb(skb, dsa_to_port(ds, port)->slave);
2640
2641         /* Wait until the switch has processed the frame */
2642         do {
2643                 rc = sja1105_dynamic_config_read(priv, BLK_IDX_MGMT_ROUTE,
2644                                                  slot, &mgmt_route);
2645                 if (rc < 0) {
2646                         dev_err_ratelimited(priv->ds->dev,
2647                                             "failed to poll for mgmt route\n");
2648                         continue;
2649                 }
2650
2651                 /* UM10944: The ENFPORT flag of the respective entry is
2652                  * cleared when a match is found. The host can use this
2653                  * flag as an acknowledgment.
2654                  */
2655                 cpu_relax();
2656         } while (mgmt_route.enfport && --timeout);
2657
2658         if (!timeout) {
2659                 /* Clean up the management route so that a follow-up
2660                  * frame may not match on it by mistake.
2661                  * This is only hardware supported on P/Q/R/S - on E/T it is
2662                  * a no-op and we are silently discarding the -EOPNOTSUPP.
2663                  */
2664                 sja1105_dynamic_config_write(priv, BLK_IDX_MGMT_ROUTE,
2665                                              slot, &mgmt_route, false);
2666                 dev_err_ratelimited(priv->ds->dev, "xmit timed out\n");
2667         }
2668
2669         return NETDEV_TX_OK;
2670 }
2671
2672 #define work_to_port(work) \
2673                 container_of((work), struct sja1105_port, xmit_work)
2674 #define tagger_to_sja1105(t) \
2675                 container_of((t), struct sja1105_private, tagger_data)
2676
2677 /* Deferred work is unfortunately necessary because setting up the management
2678  * route cannot be done from atomit context (SPI transfer takes a sleepable
2679  * lock on the bus)
2680  */
2681 static void sja1105_port_deferred_xmit(struct kthread_work *work)
2682 {
2683         struct sja1105_port *sp = work_to_port(work);
2684         struct sja1105_tagger_data *tagger_data = sp->data;
2685         struct sja1105_private *priv = tagger_to_sja1105(tagger_data);
2686         int port = sp - priv->ports;
2687         struct sk_buff *skb;
2688
2689         while ((skb = skb_dequeue(&sp->xmit_queue)) != NULL) {
2690                 struct sk_buff *clone = SJA1105_SKB_CB(skb)->clone;
2691
2692                 mutex_lock(&priv->mgmt_lock);
2693
2694                 sja1105_mgmt_xmit(priv->ds, port, 0, skb, !!clone);
2695
2696                 /* The clone, if there, was made by dsa_skb_tx_timestamp */
2697                 if (clone)
2698                         sja1105_ptp_txtstamp_skb(priv->ds, port, clone);
2699
2700                 mutex_unlock(&priv->mgmt_lock);
2701         }
2702 }
2703
2704 /* The MAXAGE setting belongs to the L2 Forwarding Parameters table,
2705  * which cannot be reconfigured at runtime. So a switch reset is required.
2706  */
2707 static int sja1105_set_ageing_time(struct dsa_switch *ds,
2708                                    unsigned int ageing_time)
2709 {
2710         struct sja1105_l2_lookup_params_entry *l2_lookup_params;
2711         struct sja1105_private *priv = ds->priv;
2712         struct sja1105_table *table;
2713         unsigned int maxage;
2714
2715         table = &priv->static_config.tables[BLK_IDX_L2_LOOKUP_PARAMS];
2716         l2_lookup_params = table->entries;
2717
2718         maxage = SJA1105_AGEING_TIME_MS(ageing_time);
2719
2720         if (l2_lookup_params->maxage == maxage)
2721                 return 0;
2722
2723         l2_lookup_params->maxage = maxage;
2724
2725         return sja1105_static_config_reload(priv, SJA1105_AGEING_TIME);
2726 }
2727
2728 static int sja1105_change_mtu(struct dsa_switch *ds, int port, int new_mtu)
2729 {
2730         struct sja1105_l2_policing_entry *policing;
2731         struct sja1105_private *priv = ds->priv;
2732
2733         new_mtu += VLAN_ETH_HLEN + ETH_FCS_LEN;
2734
2735         if (dsa_is_cpu_port(ds, port) || dsa_is_dsa_port(ds, port))
2736                 new_mtu += VLAN_HLEN;
2737
2738         policing = priv->static_config.tables[BLK_IDX_L2_POLICING].entries;
2739
2740         if (policing[port].maxlen == new_mtu)
2741                 return 0;
2742
2743         policing[port].maxlen = new_mtu;
2744
2745         return sja1105_static_config_reload(priv, SJA1105_BEST_EFFORT_POLICING);
2746 }
2747
2748 static int sja1105_get_max_mtu(struct dsa_switch *ds, int port)
2749 {
2750         return 2043 - VLAN_ETH_HLEN - ETH_FCS_LEN;
2751 }
2752
2753 static int sja1105_port_setup_tc(struct dsa_switch *ds, int port,
2754                                  enum tc_setup_type type,
2755                                  void *type_data)
2756 {
2757         switch (type) {
2758         case TC_SETUP_QDISC_TAPRIO:
2759                 return sja1105_setup_tc_taprio(ds, port, type_data);
2760         case TC_SETUP_QDISC_CBS:
2761                 return sja1105_setup_tc_cbs(ds, port, type_data);
2762         default:
2763                 return -EOPNOTSUPP;
2764         }
2765 }
2766
2767 /* We have a single mirror (@to) port, but can configure ingress and egress
2768  * mirroring on all other (@from) ports.
2769  * We need to allow mirroring rules only as long as the @to port is always the
2770  * same, and we need to unset the @to port from mirr_port only when there is no
2771  * mirroring rule that references it.
2772  */
2773 static int sja1105_mirror_apply(struct sja1105_private *priv, int from, int to,
2774                                 bool ingress, bool enabled)
2775 {
2776         struct sja1105_general_params_entry *general_params;
2777         struct sja1105_mac_config_entry *mac;
2778         struct dsa_switch *ds = priv->ds;
2779         struct sja1105_table *table;
2780         bool already_enabled;
2781         u64 new_mirr_port;
2782         int rc;
2783
2784         table = &priv->static_config.tables[BLK_IDX_GENERAL_PARAMS];
2785         general_params = table->entries;
2786
2787         mac = priv->static_config.tables[BLK_IDX_MAC_CONFIG].entries;
2788
2789         already_enabled = (general_params->mirr_port != ds->num_ports);
2790         if (already_enabled && enabled && general_params->mirr_port != to) {
2791                 dev_err(priv->ds->dev,
2792                         "Delete mirroring rules towards port %llu first\n",
2793                         general_params->mirr_port);
2794                 return -EBUSY;
2795         }
2796
2797         new_mirr_port = to;
2798         if (!enabled) {
2799                 bool keep = false;
2800                 int port;
2801
2802                 /* Anybody still referencing mirr_port? */
2803                 for (port = 0; port < ds->num_ports; port++) {
2804                         if (mac[port].ing_mirr || mac[port].egr_mirr) {
2805                                 keep = true;
2806                                 break;
2807                         }
2808                 }
2809                 /* Unset already_enabled for next time */
2810                 if (!keep)
2811                         new_mirr_port = ds->num_ports;
2812         }
2813         if (new_mirr_port != general_params->mirr_port) {
2814                 general_params->mirr_port = new_mirr_port;
2815
2816                 rc = sja1105_dynamic_config_write(priv, BLK_IDX_GENERAL_PARAMS,
2817                                                   0, general_params, true);
2818                 if (rc < 0)
2819                         return rc;
2820         }
2821
2822         if (ingress)
2823                 mac[from].ing_mirr = enabled;
2824         else
2825                 mac[from].egr_mirr = enabled;
2826
2827         return sja1105_dynamic_config_write(priv, BLK_IDX_MAC_CONFIG, from,
2828                                             &mac[from], true);
2829 }
2830
2831 static int sja1105_mirror_add(struct dsa_switch *ds, int port,
2832                               struct dsa_mall_mirror_tc_entry *mirror,
2833                               bool ingress)
2834 {
2835         return sja1105_mirror_apply(ds->priv, port, mirror->to_local_port,
2836                                     ingress, true);
2837 }
2838
2839 static void sja1105_mirror_del(struct dsa_switch *ds, int port,
2840                                struct dsa_mall_mirror_tc_entry *mirror)
2841 {
2842         sja1105_mirror_apply(ds->priv, port, mirror->to_local_port,
2843                              mirror->ingress, false);
2844 }
2845
2846 static int sja1105_port_policer_add(struct dsa_switch *ds, int port,
2847                                     struct dsa_mall_policer_tc_entry *policer)
2848 {
2849         struct sja1105_l2_policing_entry *policing;
2850         struct sja1105_private *priv = ds->priv;
2851
2852         policing = priv->static_config.tables[BLK_IDX_L2_POLICING].entries;
2853
2854         /* In hardware, every 8 microseconds the credit level is incremented by
2855          * the value of RATE bytes divided by 64, up to a maximum of SMAX
2856          * bytes.
2857          */
2858         policing[port].rate = div_u64(512 * policer->rate_bytes_per_sec,
2859                                       1000000);
2860         policing[port].smax = policer->burst;
2861
2862         return sja1105_static_config_reload(priv, SJA1105_BEST_EFFORT_POLICING);
2863 }
2864
2865 static void sja1105_port_policer_del(struct dsa_switch *ds, int port)
2866 {
2867         struct sja1105_l2_policing_entry *policing;
2868         struct sja1105_private *priv = ds->priv;
2869
2870         policing = priv->static_config.tables[BLK_IDX_L2_POLICING].entries;
2871
2872         policing[port].rate = SJA1105_RATE_MBPS(1000);
2873         policing[port].smax = 65535;
2874
2875         sja1105_static_config_reload(priv, SJA1105_BEST_EFFORT_POLICING);
2876 }
2877
2878 static int sja1105_port_set_learning(struct sja1105_private *priv, int port,
2879                                      bool enabled)
2880 {
2881         struct sja1105_mac_config_entry *mac;
2882
2883         mac = priv->static_config.tables[BLK_IDX_MAC_CONFIG].entries;
2884
2885         mac[port].dyn_learn = enabled;
2886
2887         return sja1105_dynamic_config_write(priv, BLK_IDX_MAC_CONFIG, port,
2888                                             &mac[port], true);
2889 }
2890
2891 static int sja1105_port_ucast_bcast_flood(struct sja1105_private *priv, int to,
2892                                           struct switchdev_brport_flags flags)
2893 {
2894         if (flags.mask & BR_FLOOD) {
2895                 if (flags.val & BR_FLOOD)
2896                         priv->ucast_egress_floods |= BIT(to);
2897                 else
2898                         priv->ucast_egress_floods &= ~BIT(to);
2899         }
2900
2901         if (flags.mask & BR_BCAST_FLOOD) {
2902                 if (flags.val & BR_BCAST_FLOOD)
2903                         priv->bcast_egress_floods |= BIT(to);
2904                 else
2905                         priv->bcast_egress_floods &= ~BIT(to);
2906         }
2907
2908         return sja1105_manage_flood_domains(priv);
2909 }
2910
2911 static int sja1105_port_mcast_flood(struct sja1105_private *priv, int to,
2912                                     struct switchdev_brport_flags flags,
2913                                     struct netlink_ext_ack *extack)
2914 {
2915         struct sja1105_l2_lookup_entry *l2_lookup;
2916         struct sja1105_table *table;
2917         int match;
2918
2919         table = &priv->static_config.tables[BLK_IDX_L2_LOOKUP];
2920         l2_lookup = table->entries;
2921
2922         for (match = 0; match < table->entry_count; match++)
2923                 if (l2_lookup[match].macaddr == SJA1105_UNKNOWN_MULTICAST &&
2924                     l2_lookup[match].mask_macaddr == SJA1105_UNKNOWN_MULTICAST)
2925                         break;
2926
2927         if (match == table->entry_count) {
2928                 NL_SET_ERR_MSG_MOD(extack,
2929                                    "Could not find FDB entry for unknown multicast");
2930                 return -ENOSPC;
2931         }
2932
2933         if (flags.val & BR_MCAST_FLOOD)
2934                 l2_lookup[match].destports |= BIT(to);
2935         else
2936                 l2_lookup[match].destports &= ~BIT(to);
2937
2938         return sja1105_dynamic_config_write(priv, BLK_IDX_L2_LOOKUP,
2939                                             l2_lookup[match].index,
2940                                             &l2_lookup[match],
2941                                             true);
2942 }
2943
2944 static int sja1105_port_pre_bridge_flags(struct dsa_switch *ds, int port,
2945                                          struct switchdev_brport_flags flags,
2946                                          struct netlink_ext_ack *extack)
2947 {
2948         struct sja1105_private *priv = ds->priv;
2949
2950         if (flags.mask & ~(BR_LEARNING | BR_FLOOD | BR_MCAST_FLOOD |
2951                            BR_BCAST_FLOOD))
2952                 return -EINVAL;
2953
2954         if (flags.mask & (BR_FLOOD | BR_MCAST_FLOOD) &&
2955             !priv->info->can_limit_mcast_flood) {
2956                 bool multicast = !!(flags.val & BR_MCAST_FLOOD);
2957                 bool unicast = !!(flags.val & BR_FLOOD);
2958
2959                 if (unicast != multicast) {
2960                         NL_SET_ERR_MSG_MOD(extack,
2961                                            "This chip cannot configure multicast flooding independently of unicast");
2962                         return -EINVAL;
2963                 }
2964         }
2965
2966         return 0;
2967 }
2968
2969 static int sja1105_port_bridge_flags(struct dsa_switch *ds, int port,
2970                                      struct switchdev_brport_flags flags,
2971                                      struct netlink_ext_ack *extack)
2972 {
2973         struct sja1105_private *priv = ds->priv;
2974         int rc;
2975
2976         if (flags.mask & BR_LEARNING) {
2977                 bool learn_ena = !!(flags.val & BR_LEARNING);
2978
2979                 rc = sja1105_port_set_learning(priv, port, learn_ena);
2980                 if (rc)
2981                         return rc;
2982         }
2983
2984         if (flags.mask & (BR_FLOOD | BR_BCAST_FLOOD)) {
2985                 rc = sja1105_port_ucast_bcast_flood(priv, port, flags);
2986                 if (rc)
2987                         return rc;
2988         }
2989
2990         /* For chips that can't offload BR_MCAST_FLOOD independently, there
2991          * is nothing to do here, we ensured the configuration is in sync by
2992          * offloading BR_FLOOD.
2993          */
2994         if (flags.mask & BR_MCAST_FLOOD && priv->info->can_limit_mcast_flood) {
2995                 rc = sja1105_port_mcast_flood(priv, port, flags,
2996                                               extack);
2997                 if (rc)
2998                         return rc;
2999         }
3000
3001         return 0;
3002 }
3003
3004 static void sja1105_teardown_ports(struct sja1105_private *priv)
3005 {
3006         struct dsa_switch *ds = priv->ds;
3007         int port;
3008
3009         for (port = 0; port < ds->num_ports; port++) {
3010                 struct sja1105_port *sp = &priv->ports[port];
3011
3012                 if (sp->xmit_worker)
3013                         kthread_destroy_worker(sp->xmit_worker);
3014         }
3015 }
3016
3017 static int sja1105_setup_ports(struct sja1105_private *priv)
3018 {
3019         struct sja1105_tagger_data *tagger_data = &priv->tagger_data;
3020         struct dsa_switch *ds = priv->ds;
3021         int port, rc;
3022
3023         /* Connections between dsa_port and sja1105_port */
3024         for (port = 0; port < ds->num_ports; port++) {
3025                 struct sja1105_port *sp = &priv->ports[port];
3026                 struct dsa_port *dp = dsa_to_port(ds, port);
3027                 struct kthread_worker *worker;
3028                 struct net_device *slave;
3029
3030                 if (!dsa_port_is_user(dp))
3031                         continue;
3032
3033                 dp->priv = sp;
3034                 sp->data = tagger_data;
3035                 slave = dp->slave;
3036                 kthread_init_work(&sp->xmit_work, sja1105_port_deferred_xmit);
3037                 worker = kthread_create_worker(0, "%s_xmit", slave->name);
3038                 if (IS_ERR(worker)) {
3039                         rc = PTR_ERR(worker);
3040                         dev_err(ds->dev,
3041                                 "failed to create deferred xmit thread: %d\n",
3042                                 rc);
3043                         goto out_destroy_workers;
3044                 }
3045                 sp->xmit_worker = worker;
3046                 skb_queue_head_init(&sp->xmit_queue);
3047         }
3048
3049         return 0;
3050
3051 out_destroy_workers:
3052         sja1105_teardown_ports(priv);
3053         return rc;
3054 }
3055
3056 /* The programming model for the SJA1105 switch is "all-at-once" via static
3057  * configuration tables. Some of these can be dynamically modified at runtime,
3058  * but not the xMII mode parameters table.
3059  * Furthermode, some PHYs may not have crystals for generating their clocks
3060  * (e.g. RMII). Instead, their 50MHz clock is supplied via the SJA1105 port's
3061  * ref_clk pin. So port clocking needs to be initialized early, before
3062  * connecting to PHYs is attempted, otherwise they won't respond through MDIO.
3063  * Setting correct PHY link speed does not matter now.
3064  * But dsa_slave_phy_setup is called later than sja1105_setup, so the PHY
3065  * bindings are not yet parsed by DSA core. We need to parse early so that we
3066  * can populate the xMII mode parameters table.
3067  */
3068 static int sja1105_setup(struct dsa_switch *ds)
3069 {
3070         struct sja1105_private *priv = ds->priv;
3071         int rc;
3072
3073         if (priv->info->disable_microcontroller) {
3074                 rc = priv->info->disable_microcontroller(priv);
3075                 if (rc < 0) {
3076                         dev_err(ds->dev,
3077                                 "Failed to disable microcontroller: %pe\n",
3078                                 ERR_PTR(rc));
3079                         return rc;
3080                 }
3081         }
3082
3083         /* Create and send configuration down to device */
3084         rc = sja1105_static_config_load(priv);
3085         if (rc < 0) {
3086                 dev_err(ds->dev, "Failed to load static config: %d\n", rc);
3087                 return rc;
3088         }
3089
3090         /* Configure the CGU (PHY link modes and speeds) */
3091         if (priv->info->clocking_setup) {
3092                 rc = priv->info->clocking_setup(priv);
3093                 if (rc < 0) {
3094                         dev_err(ds->dev,
3095                                 "Failed to configure MII clocking: %pe\n",
3096                                 ERR_PTR(rc));
3097                         goto out_static_config_free;
3098                 }
3099         }
3100
3101         rc = sja1105_setup_ports(priv);
3102         if (rc)
3103                 goto out_static_config_free;
3104
3105         sja1105_tas_setup(ds);
3106         sja1105_flower_setup(ds);
3107
3108         rc = sja1105_ptp_clock_register(ds);
3109         if (rc < 0) {
3110                 dev_err(ds->dev, "Failed to register PTP clock: %d\n", rc);
3111                 goto out_flower_teardown;
3112         }
3113
3114         rc = sja1105_mdiobus_register(ds);
3115         if (rc < 0) {
3116                 dev_err(ds->dev, "Failed to register MDIO bus: %pe\n",
3117                         ERR_PTR(rc));
3118                 goto out_ptp_clock_unregister;
3119         }
3120
3121         rc = sja1105_devlink_setup(ds);
3122         if (rc < 0)
3123                 goto out_mdiobus_unregister;
3124
3125         rtnl_lock();
3126         rc = dsa_tag_8021q_register(ds, htons(ETH_P_8021Q));
3127         rtnl_unlock();
3128         if (rc)
3129                 goto out_devlink_teardown;
3130
3131         /* On SJA1105, VLAN filtering per se is always enabled in hardware.
3132          * The only thing we can do to disable it is lie about what the 802.1Q
3133          * EtherType is.
3134          * So it will still try to apply VLAN filtering, but all ingress
3135          * traffic (except frames received with EtherType of ETH_P_SJA1105)
3136          * will be internally tagged with a distorted VLAN header where the
3137          * TPID is ETH_P_SJA1105, and the VLAN ID is the port pvid.
3138          */
3139         ds->vlan_filtering_is_global = true;
3140         ds->untag_bridge_pvid = true;
3141         /* tag_8021q has 3 bits for the VBID, and the value 0 is reserved */
3142         ds->num_fwd_offloading_bridges = 7;
3143
3144         /* Advertise the 8 egress queues */
3145         ds->num_tx_queues = SJA1105_NUM_TC;
3146
3147         ds->mtu_enforcement_ingress = true;
3148         ds->assisted_learning_on_cpu_port = true;
3149
3150         return 0;
3151
3152 out_devlink_teardown:
3153         sja1105_devlink_teardown(ds);
3154 out_mdiobus_unregister:
3155         sja1105_mdiobus_unregister(ds);
3156 out_ptp_clock_unregister:
3157         sja1105_ptp_clock_unregister(ds);
3158 out_flower_teardown:
3159         sja1105_flower_teardown(ds);
3160         sja1105_tas_teardown(ds);
3161         sja1105_teardown_ports(priv);
3162 out_static_config_free:
3163         sja1105_static_config_free(&priv->static_config);
3164
3165         return rc;
3166 }
3167
3168 static void sja1105_teardown(struct dsa_switch *ds)
3169 {
3170         struct sja1105_private *priv = ds->priv;
3171
3172         rtnl_lock();
3173         dsa_tag_8021q_unregister(ds);
3174         rtnl_unlock();
3175
3176         sja1105_devlink_teardown(ds);
3177         sja1105_mdiobus_unregister(ds);
3178         sja1105_ptp_clock_unregister(ds);
3179         sja1105_flower_teardown(ds);
3180         sja1105_tas_teardown(ds);
3181         sja1105_teardown_ports(priv);
3182         sja1105_static_config_free(&priv->static_config);
3183 }
3184
3185 static const struct dsa_switch_ops sja1105_switch_ops = {
3186         .get_tag_protocol       = sja1105_get_tag_protocol,
3187         .setup                  = sja1105_setup,
3188         .teardown               = sja1105_teardown,
3189         .set_ageing_time        = sja1105_set_ageing_time,
3190         .port_change_mtu        = sja1105_change_mtu,
3191         .port_max_mtu           = sja1105_get_max_mtu,
3192         .phylink_validate       = sja1105_phylink_validate,
3193         .phylink_mac_config     = sja1105_mac_config,
3194         .phylink_mac_link_up    = sja1105_mac_link_up,
3195         .phylink_mac_link_down  = sja1105_mac_link_down,
3196         .get_strings            = sja1105_get_strings,
3197         .get_ethtool_stats      = sja1105_get_ethtool_stats,
3198         .get_sset_count         = sja1105_get_sset_count,
3199         .get_ts_info            = sja1105_get_ts_info,
3200         .port_disable           = sja1105_port_disable,
3201         .port_fdb_dump          = sja1105_fdb_dump,
3202         .port_fdb_add           = sja1105_fdb_add,
3203         .port_fdb_del           = sja1105_fdb_del,
3204         .port_fast_age          = sja1105_fast_age,
3205         .port_bridge_join       = sja1105_bridge_join,
3206         .port_bridge_leave      = sja1105_bridge_leave,
3207         .port_pre_bridge_flags  = sja1105_port_pre_bridge_flags,
3208         .port_bridge_flags      = sja1105_port_bridge_flags,
3209         .port_stp_state_set     = sja1105_bridge_stp_state_set,
3210         .port_vlan_filtering    = sja1105_vlan_filtering,
3211         .port_vlan_add          = sja1105_bridge_vlan_add,
3212         .port_vlan_del          = sja1105_bridge_vlan_del,
3213         .port_mdb_add           = sja1105_mdb_add,
3214         .port_mdb_del           = sja1105_mdb_del,
3215         .port_hwtstamp_get      = sja1105_hwtstamp_get,
3216         .port_hwtstamp_set      = sja1105_hwtstamp_set,
3217         .port_rxtstamp          = sja1105_port_rxtstamp,
3218         .port_txtstamp          = sja1105_port_txtstamp,
3219         .port_setup_tc          = sja1105_port_setup_tc,
3220         .port_mirror_add        = sja1105_mirror_add,
3221         .port_mirror_del        = sja1105_mirror_del,
3222         .port_policer_add       = sja1105_port_policer_add,
3223         .port_policer_del       = sja1105_port_policer_del,
3224         .cls_flower_add         = sja1105_cls_flower_add,
3225         .cls_flower_del         = sja1105_cls_flower_del,
3226         .cls_flower_stats       = sja1105_cls_flower_stats,
3227         .devlink_info_get       = sja1105_devlink_info_get,
3228         .tag_8021q_vlan_add     = sja1105_dsa_8021q_vlan_add,
3229         .tag_8021q_vlan_del     = sja1105_dsa_8021q_vlan_del,
3230         .port_prechangeupper    = sja1105_prechangeupper,
3231         .port_bridge_tx_fwd_offload = dsa_tag_8021q_bridge_tx_fwd_offload,
3232         .port_bridge_tx_fwd_unoffload = dsa_tag_8021q_bridge_tx_fwd_unoffload,
3233 };
3234
3235 static const struct of_device_id sja1105_dt_ids[];
3236
3237 static int sja1105_check_device_id(struct sja1105_private *priv)
3238 {
3239         const struct sja1105_regs *regs = priv->info->regs;
3240         u8 prod_id[SJA1105_SIZE_DEVICE_ID] = {0};
3241         struct device *dev = &priv->spidev->dev;
3242         const struct of_device_id *match;
3243         u32 device_id;
3244         u64 part_no;
3245         int rc;
3246
3247         rc = sja1105_xfer_u32(priv, SPI_READ, regs->device_id, &device_id,
3248                               NULL);
3249         if (rc < 0)
3250                 return rc;
3251
3252         rc = sja1105_xfer_buf(priv, SPI_READ, regs->prod_id, prod_id,
3253                               SJA1105_SIZE_DEVICE_ID);
3254         if (rc < 0)
3255                 return rc;
3256
3257         sja1105_unpack(prod_id, &part_no, 19, 4, SJA1105_SIZE_DEVICE_ID);
3258
3259         for (match = sja1105_dt_ids; match->compatible[0]; match++) {
3260                 const struct sja1105_info *info = match->data;
3261
3262                 /* Is what's been probed in our match table at all? */
3263                 if (info->device_id != device_id || info->part_no != part_no)
3264                         continue;
3265
3266                 /* But is it what's in the device tree? */
3267                 if (priv->info->device_id != device_id ||
3268                     priv->info->part_no != part_no) {
3269                         dev_warn(dev, "Device tree specifies chip %s but found %s, please fix it!\n",
3270                                  priv->info->name, info->name);
3271                         /* It isn't. No problem, pick that up. */
3272                         priv->info = info;
3273                 }
3274
3275                 return 0;
3276         }
3277
3278         dev_err(dev, "Unexpected {device ID, part number}: 0x%x 0x%llx\n",
3279                 device_id, part_no);
3280
3281         return -ENODEV;
3282 }
3283
3284 static int sja1105_probe(struct spi_device *spi)
3285 {
3286         struct device *dev = &spi->dev;
3287         struct sja1105_private *priv;
3288         size_t max_xfer, max_msg;
3289         struct dsa_switch *ds;
3290         int rc;
3291
3292         if (!dev->of_node) {
3293                 dev_err(dev, "No DTS bindings for SJA1105 driver\n");
3294                 return -EINVAL;
3295         }
3296
3297         rc = sja1105_hw_reset(dev, 1, 1);
3298         if (rc)
3299                 return rc;
3300
3301         priv = devm_kzalloc(dev, sizeof(struct sja1105_private), GFP_KERNEL);
3302         if (!priv)
3303                 return -ENOMEM;
3304
3305         /* Populate our driver private structure (priv) based on
3306          * the device tree node that was probed (spi)
3307          */
3308         priv->spidev = spi;
3309         spi_set_drvdata(spi, priv);
3310
3311         /* Configure the SPI bus */
3312         spi->bits_per_word = 8;
3313         rc = spi_setup(spi);
3314         if (rc < 0) {
3315                 dev_err(dev, "Could not init SPI\n");
3316                 return rc;
3317         }
3318
3319         /* In sja1105_xfer, we send spi_messages composed of two spi_transfers:
3320          * a small one for the message header and another one for the current
3321          * chunk of the packed buffer.
3322          * Check that the restrictions imposed by the SPI controller are
3323          * respected: the chunk buffer is smaller than the max transfer size,
3324          * and the total length of the chunk plus its message header is smaller
3325          * than the max message size.
3326          * We do that during probe time since the maximum transfer size is a
3327          * runtime invariant.
3328          */
3329         max_xfer = spi_max_transfer_size(spi);
3330         max_msg = spi_max_message_size(spi);
3331
3332         /* We need to send at least one 64-bit word of SPI payload per message
3333          * in order to be able to make useful progress.
3334          */
3335         if (max_msg < SJA1105_SIZE_SPI_MSG_HEADER + 8) {
3336                 dev_err(dev, "SPI master cannot send large enough buffers, aborting\n");
3337                 return -EINVAL;
3338         }
3339
3340         priv->max_xfer_len = SJA1105_SIZE_SPI_MSG_MAXLEN;
3341         if (priv->max_xfer_len > max_xfer)
3342                 priv->max_xfer_len = max_xfer;
3343         if (priv->max_xfer_len > max_msg - SJA1105_SIZE_SPI_MSG_HEADER)
3344                 priv->max_xfer_len = max_msg - SJA1105_SIZE_SPI_MSG_HEADER;
3345
3346         priv->info = of_device_get_match_data(dev);
3347
3348         /* Detect hardware device */
3349         rc = sja1105_check_device_id(priv);
3350         if (rc < 0) {
3351                 dev_err(dev, "Device ID check failed: %d\n", rc);
3352                 return rc;
3353         }
3354
3355         dev_info(dev, "Probed switch chip: %s\n", priv->info->name);
3356
3357         ds = devm_kzalloc(dev, sizeof(*ds), GFP_KERNEL);
3358         if (!ds)
3359                 return -ENOMEM;
3360
3361         ds->dev = dev;
3362         ds->num_ports = priv->info->num_ports;
3363         ds->ops = &sja1105_switch_ops;
3364         ds->priv = priv;
3365         priv->ds = ds;
3366
3367         mutex_init(&priv->ptp_data.lock);
3368         mutex_init(&priv->dynamic_config_lock);
3369         mutex_init(&priv->mgmt_lock);
3370
3371         rc = sja1105_parse_dt(priv);
3372         if (rc < 0) {
3373                 dev_err(ds->dev, "Failed to parse DT: %d\n", rc);
3374                 return rc;
3375         }
3376
3377         if (IS_ENABLED(CONFIG_NET_SCH_CBS)) {
3378                 priv->cbs = devm_kcalloc(dev, priv->info->num_cbs_shapers,
3379                                          sizeof(struct sja1105_cbs_entry),
3380                                          GFP_KERNEL);
3381                 if (!priv->cbs)
3382                         return -ENOMEM;
3383         }
3384
3385         return dsa_register_switch(priv->ds);
3386 }
3387
3388 static int sja1105_remove(struct spi_device *spi)
3389 {
3390         struct sja1105_private *priv = spi_get_drvdata(spi);
3391
3392         if (!priv)
3393                 return 0;
3394
3395         dsa_unregister_switch(priv->ds);
3396
3397         spi_set_drvdata(spi, NULL);
3398
3399         return 0;
3400 }
3401
3402 static void sja1105_shutdown(struct spi_device *spi)
3403 {
3404         struct sja1105_private *priv = spi_get_drvdata(spi);
3405
3406         if (!priv)
3407                 return;
3408
3409         dsa_switch_shutdown(priv->ds);
3410
3411         spi_set_drvdata(spi, NULL);
3412 }
3413
3414 static const struct of_device_id sja1105_dt_ids[] = {
3415         { .compatible = "nxp,sja1105e", .data = &sja1105e_info },
3416         { .compatible = "nxp,sja1105t", .data = &sja1105t_info },
3417         { .compatible = "nxp,sja1105p", .data = &sja1105p_info },
3418         { .compatible = "nxp,sja1105q", .data = &sja1105q_info },
3419         { .compatible = "nxp,sja1105r", .data = &sja1105r_info },
3420         { .compatible = "nxp,sja1105s", .data = &sja1105s_info },
3421         { .compatible = "nxp,sja1110a", .data = &sja1110a_info },
3422         { .compatible = "nxp,sja1110b", .data = &sja1110b_info },
3423         { .compatible = "nxp,sja1110c", .data = &sja1110c_info },
3424         { .compatible = "nxp,sja1110d", .data = &sja1110d_info },
3425         { /* sentinel */ },
3426 };
3427 MODULE_DEVICE_TABLE(of, sja1105_dt_ids);
3428
3429 static struct spi_driver sja1105_driver = {
3430         .driver = {
3431                 .name  = "sja1105",
3432                 .owner = THIS_MODULE,
3433                 .of_match_table = of_match_ptr(sja1105_dt_ids),
3434         },
3435         .probe  = sja1105_probe,
3436         .remove = sja1105_remove,
3437         .shutdown = sja1105_shutdown,
3438 };
3439
3440 module_spi_driver(sja1105_driver);
3441
3442 MODULE_AUTHOR("Vladimir Oltean <olteanv@gmail.com>");
3443 MODULE_AUTHOR("Georg Waibel <georg.waibel@sensor-technik.de>");
3444 MODULE_DESCRIPTION("SJA1105 Driver");
3445 MODULE_LICENSE("GPL v2");