drivers/net/dsa/sja1105/sja1105_main.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /* Copyright (c) 2018, Sensor-Technik Wiedemann GmbH
   3  * Copyright (c) 2018-2019, Vladimir Oltean <olteanv@gmail.com>
   4  */
   5
   6 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
   7
   8 #include <linux/delay.h>
   9 #include <linux/module.h>
  10 #include <linux/printk.h>
  11 #include <linux/spi/spi.h>
  12 #include <linux/errno.h>
  13 #include <linux/gpio/consumer.h>
  14 #include <linux/phylink.h>
  15 #include <linux/of.h>
  16 #include <linux/of_net.h>
  17 #include <linux/of_mdio.h>
  18 #include <linux/of_device.h>
  19 #include <linux/pcs/pcs-xpcs.h>
  20 #include <linux/netdev_features.h>
  21 #include <linux/netdevice.h>
  22 #include <linux/if_bridge.h>
  23 #include <linux/if_ether.h>
  24 #include <linux/dsa/8021q.h>
  25 #include "sja1105.h"
  26 #include "sja1105_tas.h"
  27
  28 #define SJA1105_UNKNOWN_MULTICAST       0x010000000000ull
  29
  30 static void sja1105_hw_reset(struct gpio_desc *gpio, unsigned int pulse_len,
  31                              unsigned int startup_delay)
  32 {
  33         gpiod_set_value_cansleep(gpio, 1);
  34         /* Wait for minimum reset pulse length */
  35         msleep(pulse_len);
  36         gpiod_set_value_cansleep(gpio, 0);
  37         /* Wait until chip is ready after reset */
  38         msleep(startup_delay);
  39 }
  40
  41 static void
  42 sja1105_port_allow_traffic(struct sja1105_l2_forwarding_entry *l2_fwd,
  43                            int from, int to, bool allow)
  44 {
  45         if (allow)
  46                 l2_fwd[from].reach_port |= BIT(to);
  47         else
  48                 l2_fwd[from].reach_port &= ~BIT(to);
  49 }
  50
  51 static bool sja1105_can_forward(struct sja1105_l2_forwarding_entry *l2_fwd,
  52                                 int from, int to)
  53 {
  54         return !!(l2_fwd[from].reach_port & BIT(to));
  55 }
  56
  57 static int sja1105_is_vlan_configured(struct sja1105_private *priv, u16 vid)
  58 {
  59         struct sja1105_vlan_lookup_entry *vlan;
  60         int count, i;
  61
  62         vlan = priv->static_config.tables[BLK_IDX_VLAN_LOOKUP].entries;
  63         count = priv->static_config.tables[BLK_IDX_VLAN_LOOKUP].entry_count;
  64
  65         for (i = 0; i < count; i++)
  66                 if (vlan[i].vlanid == vid)
  67                         return i;
  68
  69         /* Return an invalid entry index if not found */
  70         return -1;
  71 }
  72
  73 static int sja1105_drop_untagged(struct dsa_switch *ds, int port, bool drop)
  74 {
  75         struct sja1105_private *priv = ds->priv;
  76         struct sja1105_mac_config_entry *mac;
  77
  78         mac = priv->static_config.tables[BLK_IDX_MAC_CONFIG].entries;
  79
  80         if (mac[port].drpuntag == drop)
  81                 return 0;
  82
  83         mac[port].drpuntag = drop;
  84
  85         return sja1105_dynamic_config_write(priv, BLK_IDX_MAC_CONFIG, port,
  86                                             &mac[port], true);
  87 }
  88
  89 static int sja1105_pvid_apply(struct sja1105_private *priv, int port, u16 pvid)
  90 {
  91         struct sja1105_mac_config_entry *mac;
  92
  93         mac = priv->static_config.tables[BLK_IDX_MAC_CONFIG].entries;
  94
  95         if (mac[port].vlanid == pvid)
  96                 return 0;
  97
  98         mac[port].vlanid = pvid;
  99
 100         return sja1105_dynamic_config_write(priv, BLK_IDX_MAC_CONFIG, port,
 101                                             &mac[port], true);
 102 }
 103
 104 static int sja1105_commit_pvid(struct dsa_switch *ds, int port)
 105 {
 106         struct dsa_port *dp = dsa_to_port(ds, port);
 107         struct sja1105_private *priv = ds->priv;
 108         struct sja1105_vlan_lookup_entry *vlan;
 109         bool drop_untagged = false;
 110         int match, rc;
 111         u16 pvid;
 112
 113         if (dp->bridge_dev && br_vlan_enabled(dp->bridge_dev))
 114                 pvid = priv->bridge_pvid[port];
 115         else
 116                 pvid = priv->tag_8021q_pvid[port];
 117
 118         rc = sja1105_pvid_apply(priv, port, pvid);
 119         if (rc)
 120                 return rc;
 121
 122         /* Only force dropping of untagged packets when the port is under a
 123          * VLAN-aware bridge. When the tag_8021q pvid is used, we are
 124          * deliberately removing the RX VLAN from the port's VMEMB_PORT list,
 125          * to prevent DSA tag spoofing from the link partner. Untagged packets
 126          * are the only ones that should be received with tag_8021q, so
 127          * definitely don't drop them.
 128          */
 129         if (pvid == priv->bridge_pvid[port]) {
 130                 vlan = priv->static_config.tables[BLK_IDX_VLAN_LOOKUP].entries;
 131
 132                 match = sja1105_is_vlan_configured(priv, pvid);
 133
 134                 if (match < 0 || !(vlan[match].vmemb_port & BIT(port)))
 135                         drop_untagged = true;
 136         }
 137
 138         if (dsa_is_cpu_port(ds, port) || dsa_is_dsa_port(ds, port))
 139                 drop_untagged = true;
 140
 141         return sja1105_drop_untagged(ds, port, drop_untagged);
 142 }
 143
 144 static int sja1105_init_mac_settings(struct sja1105_private *priv)
 145 {
 146         struct sja1105_mac_config_entry default_mac = {
 147                 /* Enable all 8 priority queues on egress.
 148                  * Every queue i holds top[i] - base[i] frames.
 149                  * Sum of top[i] - base[i] is 511 (max hardware limit).
 150                  */
 151                 .top  = {0x3F, 0x7F, 0xBF, 0xFF, 0x13F, 0x17F, 0x1BF, 0x1FF},
 152                 .base = {0x0, 0x40, 0x80, 0xC0, 0x100, 0x140, 0x180, 0x1C0},
 153                 .enabled = {true, true, true, true, true, true, true, true},
 154                 /* Keep standard IFG of 12 bytes on egress. */
 155                 .ifg = 0,
 156                 /* Always put the MAC speed in automatic mode, where it can be
 157                  * adjusted at runtime by PHYLINK.
 158                  */
 159                 .speed = priv->info->port_speed[SJA1105_SPEED_AUTO],
 160                 /* No static correction for 1-step 1588 events */
 161                 .tp_delin = 0,
 162                 .tp_delout = 0,
 163                 /* Disable aging for critical TTEthernet traffic */
 164                 .maxage = 0xFF,
 165                 /* Internal VLAN (pvid) to apply to untagged ingress */
 166                 .vlanprio = 0,
 167                 .vlanid = 1,
 168                 .ing_mirr = false,
 169                 .egr_mirr = false,
 170                 /* Don't drop traffic with other EtherType than ETH_P_IP */
 171                 .drpnona664 = false,
 172                 /* Don't drop double-tagged traffic */
 173                 .drpdtag = false,
 174                 /* Don't drop untagged traffic */
 175                 .drpuntag = false,
 176                 /* Don't retag 802.1p (VID 0) traffic with the pvid */
 177                 .retag = false,
 178                 /* Disable learning and I/O on user ports by default -
 179                  * STP will enable it.
 180                  */
 181                 .dyn_learn = false,
 182                 .egress = false,
 183                 .ingress = false,
 184         };
 185         struct sja1105_mac_config_entry *mac;
 186         struct dsa_switch *ds = priv->ds;
 187         struct sja1105_table *table;
 188         struct dsa_port *dp;
 189
 190         table = &priv->static_config.tables[BLK_IDX_MAC_CONFIG];
 191
 192         /* Discard previous MAC Configuration Table */
 193         if (table->entry_count) {
 194                 kfree(table->entries);
 195                 table->entry_count = 0;
 196         }
 197
 198         table->entries = kcalloc(table->ops->max_entry_count,
 199                                  table->ops->unpacked_entry_size, GFP_KERNEL);
 200         if (!table->entries)
 201                 return -ENOMEM;
 202
 203         table->entry_count = table->ops->max_entry_count;
 204
 205         mac = table->entries;
 206
 207         list_for_each_entry(dp, &ds->dst->ports, list) {
 208                 if (dp->ds != ds)
 209                         continue;
 210
 211                 mac[dp->index] = default_mac;
 212
 213                 /* Let sja1105_bridge_stp_state_set() keep address learning
 214                  * enabled for the DSA ports. CPU ports use software-assisted
 215                  * learning to ensure that only FDB entries belonging to the
 216                  * bridge are learned, and that they are learned towards all
 217                  * CPU ports in a cross-chip topology if multiple CPU ports
 218                  * exist.
 219                  */
 220                 if (dsa_port_is_dsa(dp))
 221                         dp->learning = true;
 222
 223                 /* Disallow untagged packets from being received on the
 224                  * CPU and DSA ports.
 225                  */
 226                 if (dsa_port_is_cpu(dp) || dsa_port_is_dsa(dp))
 227                         mac[dp->index].drpuntag = true;
 228         }
 229
 230         return 0;
 231 }
 232
 233 static int sja1105_init_mii_settings(struct sja1105_private *priv)
 234 {
 235         struct device *dev = &priv->spidev->dev;
 236         struct sja1105_xmii_params_entry *mii;
 237         struct dsa_switch *ds = priv->ds;
 238         struct sja1105_table *table;
 239         int i;
 240
 241         table = &priv->static_config.tables[BLK_IDX_XMII_PARAMS];
 242
 243         /* Discard previous xMII Mode Parameters Table */
 244         if (table->entry_count) {
 245                 kfree(table->entries);
 246                 table->entry_count = 0;
 247         }
 248
 249         table->entries = kcalloc(table->ops->max_entry_count,
 250                                  table->ops->unpacked_entry_size, GFP_KERNEL);
 251         if (!table->entries)
 252                 return -ENOMEM;
 253
 254         /* Override table based on PHYLINK DT bindings */
 255         table->entry_count = table->ops->max_entry_count;
 256
 257         mii = table->entries;
 258
 259         for (i = 0; i < ds->num_ports; i++) {
 260                 sja1105_mii_role_t role = XMII_MAC;
 261
 262                 if (dsa_is_unused_port(priv->ds, i))
 263                         continue;
 264
 265                 switch (priv->phy_mode[i]) {
 266                 case PHY_INTERFACE_MODE_INTERNAL:
 267                         if (priv->info->internal_phy[i] == SJA1105_NO_PHY)
 268                                 goto unsupported;
 269
 270                         mii->xmii_mode[i] = XMII_MODE_MII;
 271                         if (priv->info->internal_phy[i] == SJA1105_PHY_BASE_TX)
 272                                 mii->special[i] = true;
 273
 274                         break;
 275                 case PHY_INTERFACE_MODE_REVMII:
 276                         role = XMII_PHY;
 277                         fallthrough;
 278                 case PHY_INTERFACE_MODE_MII:
 279                         if (!priv->info->supports_mii[i])
 280                                 goto unsupported;
 281
 282                         mii->xmii_mode[i] = XMII_MODE_MII;
 283                         break;
 284                 case PHY_INTERFACE_MODE_REVRMII:
 285                         role = XMII_PHY;
 286                         fallthrough;
 287                 case PHY_INTERFACE_MODE_RMII:
 288                         if (!priv->info->supports_rmii[i])
 289                                 goto unsupported;
 290
 291                         mii->xmii_mode[i] = XMII_MODE_RMII;
 292                         break;
 293                 case PHY_INTERFACE_MODE_RGMII:
 294                 case PHY_INTERFACE_MODE_RGMII_ID:
 295                 case PHY_INTERFACE_MODE_RGMII_RXID:
 296                 case PHY_INTERFACE_MODE_RGMII_TXID:
 297                         if (!priv->info->supports_rgmii[i])
 298                                 goto unsupported;
 299
 300                         mii->xmii_mode[i] = XMII_MODE_RGMII;
 301                         break;
 302                 case PHY_INTERFACE_MODE_SGMII:
 303                         if (!priv->info->supports_sgmii[i])
 304                                 goto unsupported;
 305
 306                         mii->xmii_mode[i] = XMII_MODE_SGMII;
 307                         mii->special[i] = true;
 308                         break;
 309                 case PHY_INTERFACE_MODE_2500BASEX:
 310                         if (!priv->info->supports_2500basex[i])
 311                                 goto unsupported;
 312
 313                         mii->xmii_mode[i] = XMII_MODE_SGMII;
 314                         mii->special[i] = true;
 315                         break;
 316 unsupported:
 317                 default:
 318                         dev_err(dev, "Unsupported PHY mode %s on port %d!\n",
 319                                 phy_modes(priv->phy_mode[i]), i);
 320                         return -EINVAL;
 321                 }
 322
 323                 mii->phy_mac[i] = role;
 324         }
 325         return 0;
 326 }
 327
 328 static int sja1105_init_static_fdb(struct sja1105_private *priv)
 329 {
 330         struct sja1105_l2_lookup_entry *l2_lookup;
 331         struct sja1105_table *table;
 332         int port;
 333
 334         table = &priv->static_config.tables[BLK_IDX_L2_LOOKUP];
 335
 336         /* We only populate the FDB table through dynamic L2 Address Lookup
 337          * entries, except for a special entry at the end which is a catch-all
 338          * for unknown multicast and will be used to control flooding domain.
 339          */
 340         if (table->entry_count) {
 341                 kfree(table->entries);
 342                 table->entry_count = 0;
 343         }
 344
 345         if (!priv->info->can_limit_mcast_flood)
 346                 return 0;
 347
 348         table->entries = kcalloc(1, table->ops->unpacked_entry_size,
 349                                  GFP_KERNEL);
 350         if (!table->entries)
 351                 return -ENOMEM;
 352
 353         table->entry_count = 1;
 354         l2_lookup = table->entries;
 355
 356         /* All L2 multicast addresses have an odd first octet */
 357         l2_lookup[0].macaddr = SJA1105_UNKNOWN_MULTICAST;
 358         l2_lookup[0].mask_macaddr = SJA1105_UNKNOWN_MULTICAST;
 359         l2_lookup[0].lockeds = true;
 360         l2_lookup[0].index = SJA1105_MAX_L2_LOOKUP_COUNT - 1;
 361
 362         /* Flood multicast to every port by default */
 363         for (port = 0; port < priv->ds->num_ports; port++)
 364                 if (!dsa_is_unused_port(priv->ds, port))
 365                         l2_lookup[0].destports |= BIT(port);
 366
 367         return 0;
 368 }
 369
 370 static int sja1105_init_l2_lookup_params(struct sja1105_private *priv)
 371 {
 372         struct sja1105_l2_lookup_params_entry default_l2_lookup_params = {
 373                 /* Learned FDB entries are forgotten after 300 seconds */
 374                 .maxage = SJA1105_AGEING_TIME_MS(300000),
 375                 /* All entries within a FDB bin are available for learning */
 376                 .dyn_tbsz = SJA1105ET_FDB_BIN_SIZE,
 377                 /* And the P/Q/R/S equivalent setting: */
 378                 .start_dynspc = 0,
 379                 /* 2^8 + 2^5 + 2^3 + 2^2 + 2^1 + 1 in Koopman notation */
 380                 .poly = 0x97,
 381                 /* This selects between Independent VLAN Learning (IVL) and
 382                  * Shared VLAN Learning (SVL)
 383                  */
 384                 .shared_learn = true,
 385                 /* Don't discard management traffic based on ENFPORT -
 386                  * we don't perform SMAC port enforcement anyway, so
 387                  * what we are setting here doesn't matter.
 388                  */
 389                 .no_enf_hostprt = false,
 390                 /* Don't learn SMAC for mac_fltres1 and mac_fltres0.
 391                  * Maybe correlate with no_linklocal_learn from bridge driver?
 392                  */
 393                 .no_mgmt_learn = true,
 394                 /* P/Q/R/S only */
 395                 .use_static = true,
 396                 /* Dynamically learned FDB entries can overwrite other (older)
 397                  * dynamic FDB entries
 398                  */
 399                 .owr_dyn = true,
 400                 .drpnolearn = true,
 401         };
 402         struct dsa_switch *ds = priv->ds;
 403         int port, num_used_ports = 0;
 404         struct sja1105_table *table;
 405         u64 max_fdb_entries;
 406
 407         for (port = 0; port < ds->num_ports; port++)
 408                 if (!dsa_is_unused_port(ds, port))
 409                         num_used_ports++;
 410
 411         max_fdb_entries = SJA1105_MAX_L2_LOOKUP_COUNT / num_used_ports;
 412
 413         for (port = 0; port < ds->num_ports; port++) {
 414                 if (dsa_is_unused_port(ds, port))
 415                         continue;
 416
 417                 default_l2_lookup_params.maxaddrp[port] = max_fdb_entries;
 418         }
 419
 420         table = &priv->static_config.tables[BLK_IDX_L2_LOOKUP_PARAMS];
 421
 422         if (table->entry_count) {
 423                 kfree(table->entries);
 424                 table->entry_count = 0;
 425         }
 426
 427         table->entries = kcalloc(table->ops->max_entry_count,
 428                                  table->ops->unpacked_entry_size, GFP_KERNEL);
 429         if (!table->entries)
 430                 return -ENOMEM;
 431
 432         table->entry_count = table->ops->max_entry_count;
 433
 434         /* This table only has a single entry */
 435         ((struct sja1105_l2_lookup_params_entry *)table->entries)[0] =
 436                                 default_l2_lookup_params;
 437
 438         return 0;
 439 }
 440
 441 /* Set up a default VLAN for untagged traffic injected from the CPU
 442  * using management routes (e.g. STP, PTP) as opposed to tag_8021q.
 443  * All DT-defined ports are members of this VLAN, and there are no
 444  * restrictions on forwarding (since the CPU selects the destination).
 445  * Frames from this VLAN will always be transmitted as untagged, and
 446  * neither the bridge nor the 8021q module cannot create this VLAN ID.
 447  */
 448 static int sja1105_init_static_vlan(struct sja1105_private *priv)
 449 {
 450         struct sja1105_table *table;
 451         struct sja1105_vlan_lookup_entry pvid = {
 452                 .type_entry = SJA1110_VLAN_D_TAG,
 453                 .ving_mirr = 0,
 454                 .vegr_mirr = 0,
 455                 .vmemb_port = 0,
 456                 .vlan_bc = 0,
 457                 .tag_port = 0,
 458                 .vlanid = SJA1105_DEFAULT_VLAN,
 459         };
 460         struct dsa_switch *ds = priv->ds;
 461         int port;
 462
 463         table = &priv->static_config.tables[BLK_IDX_VLAN_LOOKUP];
 464
 465         if (table->entry_count) {
 466                 kfree(table->entries);
 467                 table->entry_count = 0;
 468         }
 469
 470         table->entries = kzalloc(table->ops->unpacked_entry_size,
 471                                  GFP_KERNEL);
 472         if (!table->entries)
 473                 return -ENOMEM;
 474
 475         table->entry_count = 1;
 476
 477         for (port = 0; port < ds->num_ports; port++) {
 478                 if (dsa_is_unused_port(ds, port))
 479                         continue;
 480
 481                 pvid.vmemb_port |= BIT(port);
 482                 pvid.vlan_bc |= BIT(port);
 483                 pvid.tag_port &= ~BIT(port);
 484
 485                 if (dsa_is_cpu_port(ds, port) || dsa_is_dsa_port(ds, port)) {
 486                         priv->tag_8021q_pvid[port] = SJA1105_DEFAULT_VLAN;
 487                         priv->bridge_pvid[port] = SJA1105_DEFAULT_VLAN;
 488                 }
 489         }
 490
 491         ((struct sja1105_vlan_lookup_entry *)table->entries)[0] = pvid;
 492         return 0;
 493 }
 494
 495 static int sja1105_init_l2_forwarding(struct sja1105_private *priv)
 496 {
 497         struct sja1105_l2_forwarding_entry *l2fwd;
 498         struct dsa_switch *ds = priv->ds;
 499         struct dsa_switch_tree *dst;
 500         struct sja1105_table *table;
 501         struct dsa_link *dl;
 502         int port, tc;
 503         int from, to;
 504
 505         table = &priv->static_config.tables[BLK_IDX_L2_FORWARDING];
 506
 507         if (table->entry_count) {
 508                 kfree(table->entries);
 509                 table->entry_count = 0;
 510         }
 511
 512         table->entries = kcalloc(table->ops->max_entry_count,
 513                                  table->ops->unpacked_entry_size, GFP_KERNEL);
 514         if (!table->entries)
 515                 return -ENOMEM;
 516
 517         table->entry_count = table->ops->max_entry_count;
 518
 519         l2fwd = table->entries;
 520
 521         /* First 5 entries in the L2 Forwarding Table define the forwarding
 522          * rules and the VLAN PCP to ingress queue mapping.
 523          * Set up the ingress queue mapping first.
 524          */
 525         for (port = 0; port < ds->num_ports; port++) {
 526                 if (dsa_is_unused_port(ds, port))
 527                         continue;
 528
 529                 for (tc = 0; tc < SJA1105_NUM_TC; tc++)
 530                         l2fwd[port].vlan_pmap[tc] = tc;
 531         }
 532
 533         /* Then manage the forwarding domain for user ports. These can forward
 534          * only to the always-on domain (CPU port and DSA links)
 535          */
 536         for (from = 0; from < ds->num_ports; from++) {
 537                 if (!dsa_is_user_port(ds, from))
 538                         continue;
 539
 540                 for (to = 0; to < ds->num_ports; to++) {
 541                         if (!dsa_is_cpu_port(ds, to) &&
 542                             !dsa_is_dsa_port(ds, to))
 543                                 continue;
 544
 545                         l2fwd[from].bc_domain |= BIT(to);
 546                         l2fwd[from].fl_domain |= BIT(to);
 547
 548                         sja1105_port_allow_traffic(l2fwd, from, to, true);
 549                 }
 550         }
 551
 552         /* Then manage the forwarding domain for DSA links and CPU ports (the
 553          * always-on domain). These can send packets to any enabled port except
 554          * themselves.
 555          */
 556         for (from = 0; from < ds->num_ports; from++) {
 557                 if (!dsa_is_cpu_port(ds, from) && !dsa_is_dsa_port(ds, from))
 558                         continue;
 559
 560                 for (to = 0; to < ds->num_ports; to++) {
 561                         if (dsa_is_unused_port(ds, to))
 562                                 continue;
 563
 564                         if (from == to)
 565                                 continue;
 566
 567                         l2fwd[from].bc_domain |= BIT(to);
 568                         l2fwd[from].fl_domain |= BIT(to);
 569
 570                         sja1105_port_allow_traffic(l2fwd, from, to, true);
 571                 }
 572         }
 573
 574         /* In odd topologies ("H" connections where there is a DSA link to
 575          * another switch which also has its own CPU port), TX packets can loop
 576          * back into the system (they are flooded from CPU port 1 to the DSA
 577          * link, and from there to CPU port 2). Prevent this from happening by
 578          * cutting RX from DSA links towards our CPU port, if the remote switch
 579          * has its own CPU port and therefore doesn't need ours for network
 580          * stack termination.
 581          */
 582         dst = ds->dst;
 583
 584         list_for_each_entry(dl, &dst->rtable, list) {
 585                 if (dl->dp->ds != ds || dl->link_dp->cpu_dp == dl->dp->cpu_dp)
 586                         continue;
 587
 588                 from = dl->dp->index;
 589                 to = dsa_upstream_port(ds, from);
 590
 591                 dev_warn(ds->dev,
 592                          "H topology detected, cutting RX from DSA link %d to CPU port %d to prevent TX packet loops\n",
 593                          from, to);
 594
 595                 sja1105_port_allow_traffic(l2fwd, from, to, false);
 596
 597                 l2fwd[from].bc_domain &= ~BIT(to);
 598                 l2fwd[from].fl_domain &= ~BIT(to);
 599         }
 600
 601         /* Finally, manage the egress flooding domain. All ports start up with
 602          * flooding enabled, including the CPU port and DSA links.
 603          */
 604         for (port = 0; port < ds->num_ports; port++) {
 605                 if (dsa_is_unused_port(ds, port))
 606                         continue;
 607
 608                 priv->ucast_egress_floods |= BIT(port);
 609                 priv->bcast_egress_floods |= BIT(port);
 610         }
 611
 612         /* Next 8 entries define VLAN PCP mapping from ingress to egress.
 613          * Create a one-to-one mapping.
 614          */
 615         for (tc = 0; tc < SJA1105_NUM_TC; tc++) {
 616                 for (port = 0; port < ds->num_ports; port++) {
 617                         if (dsa_is_unused_port(ds, port))
 618                                 continue;
 619
 620                         l2fwd[ds->num_ports + tc].vlan_pmap[port] = tc;
 621                 }
 622
 623                 l2fwd[ds->num_ports + tc].type_egrpcp2outputq = true;
 624         }
 625
 626         return 0;
 627 }
 628
 629 static int sja1110_init_pcp_remapping(struct sja1105_private *priv)
 630 {
 631         struct sja1110_pcp_remapping_entry *pcp_remap;
 632         struct dsa_switch *ds = priv->ds;
 633         struct sja1105_table *table;
 634         int port, tc;
 635
 636         table = &priv->static_config.tables[BLK_IDX_PCP_REMAPPING];
 637
 638         /* Nothing to do for SJA1105 */
 639         if (!table->ops->max_entry_count)
 640                 return 0;
 641
 642         if (table->entry_count) {
 643                 kfree(table->entries);
 644                 table->entry_count = 0;
 645         }
 646
 647         table->entries = kcalloc(table->ops->max_entry_count,
 648                                  table->ops->unpacked_entry_size, GFP_KERNEL);
 649         if (!table->entries)
 650                 return -ENOMEM;
 651
 652         table->entry_count = table->ops->max_entry_count;
 653
 654         pcp_remap = table->entries;
 655
 656         /* Repeat the configuration done for vlan_pmap */
 657         for (port = 0; port < ds->num_ports; port++) {
 658                 if (dsa_is_unused_port(ds, port))
 659                         continue;
 660
 661                 for (tc = 0; tc < SJA1105_NUM_TC; tc++)
 662                         pcp_remap[port].egrpcp[tc] = tc;
 663         }
 664
 665         return 0;
 666 }
 667
 668 static int sja1105_init_l2_forwarding_params(struct sja1105_private *priv)
 669 {
 670         struct sja1105_l2_forwarding_params_entry *l2fwd_params;
 671         struct sja1105_table *table;
 672
 673         table = &priv->static_config.tables[BLK_IDX_L2_FORWARDING_PARAMS];
 674
 675         if (table->entry_count) {
 676                 kfree(table->entries);
 677                 table->entry_count = 0;
 678         }
 679
 680         table->entries = kcalloc(table->ops->max_entry_count,
 681                                  table->ops->unpacked_entry_size, GFP_KERNEL);
 682         if (!table->entries)
 683                 return -ENOMEM;
 684
 685         table->entry_count = table->ops->max_entry_count;
 686
 687         /* This table only has a single entry */
 688         l2fwd_params = table->entries;
 689
 690         /* Disallow dynamic reconfiguration of vlan_pmap */
 691         l2fwd_params->max_dynp = 0;
 692         /* Use a single memory partition for all ingress queues */
 693         l2fwd_params->part_spc[0] = priv->info->max_frame_mem;
 694
 695         return 0;
 696 }
 697
 698 void sja1105_frame_memory_partitioning(struct sja1105_private *priv)
 699 {
 700         struct sja1105_l2_forwarding_params_entry *l2_fwd_params;
 701         struct sja1105_vl_forwarding_params_entry *vl_fwd_params;
 702         struct sja1105_table *table;
 703
 704         table = &priv->static_config.tables[BLK_IDX_L2_FORWARDING_PARAMS];
 705         l2_fwd_params = table->entries;
 706         l2_fwd_params->part_spc[0] = SJA1105_MAX_FRAME_MEMORY;
 707
 708         /* If we have any critical-traffic virtual links, we need to reserve
 709          * some frame buffer memory for them. At the moment, hardcode the value
 710          * at 100 blocks of 128 bytes of memory each. This leaves 829 blocks
 711          * remaining for best-effort traffic. TODO: figure out a more flexible
 712          * way to perform the frame buffer partitioning.
 713          */
 714         if (!priv->static_config.tables[BLK_IDX_VL_FORWARDING].entry_count)
 715                 return;
 716
 717         table = &priv->static_config.tables[BLK_IDX_VL_FORWARDING_PARAMS];
 718         vl_fwd_params = table->entries;
 719
 720         l2_fwd_params->part_spc[0] -= SJA1105_VL_FRAME_MEMORY;
 721         vl_fwd_params->partspc[0] = SJA1105_VL_FRAME_MEMORY;
 722 }
 723
 724 /* SJA1110 TDMACONFIGIDX values:
 725  *
 726  *      | 100 Mbps ports |  1Gbps ports  | 2.5Gbps ports | Disabled ports
 727  * -----+----------------+---------------+---------------+---------------
 728  *   0  |   0, [5:10]    |     [1:2]     |     [3:4]     |     retag
 729  *   1  |0, [5:10], retag|     [1:2]     |     [3:4]     |       -
 730  *   2  |   0, [5:10]    |  [1:3], retag |       4       |       -
 731  *   3  |   0, [5:10]    |[1:2], 4, retag|       3       |       -
 732  *   4  |  0, 2, [5:10]  |    1, retag   |     [3:4]     |       -
 733  *   5  |  0, 1, [5:10]  |    2, retag   |     [3:4]     |       -
 734  *  14  |   0, [5:10]    | [1:4], retag  |       -       |       -
 735  *  15  |     [5:10]     | [0:4], retag  |       -       |       -
 736  */
 737 static void sja1110_select_tdmaconfigidx(struct sja1105_private *priv)
 738 {
 739         struct sja1105_general_params_entry *general_params;
 740         struct sja1105_table *table;
 741         bool port_1_is_base_tx;
 742         bool port_3_is_2500;
 743         bool port_4_is_2500;
 744         u64 tdmaconfigidx;
 745
 746         if (priv->info->device_id != SJA1110_DEVICE_ID)
 747                 return;
 748
 749         table = &priv->static_config.tables[BLK_IDX_GENERAL_PARAMS];
 750         general_params = table->entries;
 751
 752         /* All the settings below are "as opposed to SGMII", which is the
 753          * other pinmuxing option.
 754          */
 755         port_1_is_base_tx = priv->phy_mode[1] == PHY_INTERFACE_MODE_INTERNAL;
 756         port_3_is_2500 = priv->phy_mode[3] == PHY_INTERFACE_MODE_2500BASEX;
 757         port_4_is_2500 = priv->phy_mode[4] == PHY_INTERFACE_MODE_2500BASEX;
 758
 759         if (port_1_is_base_tx)
 760                 /* Retagging port will operate at 1 Gbps */
 761                 tdmaconfigidx = 5;
 762         else if (port_3_is_2500 && port_4_is_2500)
 763                 /* Retagging port will operate at 100 Mbps */
 764                 tdmaconfigidx = 1;
 765         else if (port_3_is_2500)
 766                 /* Retagging port will operate at 1 Gbps */
 767                 tdmaconfigidx = 3;
 768         else if (port_4_is_2500)
 769                 /* Retagging port will operate at 1 Gbps */
 770                 tdmaconfigidx = 2;
 771         else
 772                 /* Retagging port will operate at 1 Gbps */
 773                 tdmaconfigidx = 14;
 774
 775         general_params->tdmaconfigidx = tdmaconfigidx;
 776 }
 777
 778 static int sja1105_init_topology(struct sja1105_private *priv,
 779                                  struct sja1105_general_params_entry *general_params)
 780 {
 781         struct dsa_switch *ds = priv->ds;
 782         int port;
 783
 784         /* The host port is the destination for traffic matching mac_fltres1
 785          * and mac_fltres0 on all ports except itself. Default to an invalid
 786          * value.
 787          */
 788         general_params->host_port = ds->num_ports;
 789
 790         /* Link-local traffic received on casc_port will be forwarded
 791          * to host_port without embedding the source port and device ID
 792          * info in the destination MAC address, and no RX timestamps will be
 793          * taken either (presumably because it is a cascaded port and a
 794          * downstream SJA switch already did that).
 795          * To disable the feature, we need to do different things depending on
 796          * switch generation. On SJA1105 we need to set an invalid port, while
 797          * on SJA1110 which support multiple cascaded ports, this field is a
 798          * bitmask so it must be left zero.
 799          */
 800         if (!priv->info->multiple_cascade_ports)
 801                 general_params->casc_port = ds->num_ports;
 802
 803         for (port = 0; port < ds->num_ports; port++) {
 804                 bool is_upstream = dsa_is_upstream_port(ds, port);
 805                 bool is_dsa_link = dsa_is_dsa_port(ds, port);
 806
 807                 /* Upstream ports can be dedicated CPU ports or
 808                  * upstream-facing DSA links
 809                  */
 810                 if (is_upstream) {
 811                         if (general_params->host_port == ds->num_ports) {
 812                                 general_params->host_port = port;
 813                         } else {
 814                                 dev_err(ds->dev,
 815                                         "Port %llu is already a host port, configuring %d as one too is not supported\n",
 816                                         general_params->host_port, port);
 817                                 return -EINVAL;
 818                         }
 819                 }
 820
 821                 /* Cascade ports are downstream-facing DSA links */
 822                 if (is_dsa_link && !is_upstream) {
 823                         if (priv->info->multiple_cascade_ports) {
 824                                 general_params->casc_port |= BIT(port);
 825                         } else if (general_params->casc_port == ds->num_ports) {
 826                                 general_params->casc_port = port;
 827                         } else {
 828                                 dev_err(ds->dev,
 829                                         "Port %llu is already a cascade port, configuring %d as one too is not supported\n",
 830                                         general_params->casc_port, port);
 831                                 return -EINVAL;
 832                         }
 833                 }
 834         }
 835
 836         if (general_params->host_port == ds->num_ports) {
 837                 dev_err(ds->dev, "No host port configured\n");
 838                 return -EINVAL;
 839         }
 840
 841         return 0;
 842 }
 843
 844 static int sja1105_init_general_params(struct sja1105_private *priv)
 845 {
 846         struct sja1105_general_params_entry default_general_params = {
 847                 /* Allow dynamic changing of the mirror port */
 848                 .mirr_ptacu = true,
 849                 .switchid = priv->ds->index,
 850                 /* Priority queue for link-local management frames
 851                  * (both ingress to and egress from CPU - PTP, STP etc)
 852                  */
 853                 .hostprio = 7,
 854                 .mac_fltres1 = SJA1105_LINKLOCAL_FILTER_A,
 855                 .mac_flt1    = SJA1105_LINKLOCAL_FILTER_A_MASK,
 856                 .incl_srcpt1 = false,
 857                 .send_meta1  = false,
 858                 .mac_fltres0 = SJA1105_LINKLOCAL_FILTER_B,
 859                 .mac_flt0    = SJA1105_LINKLOCAL_FILTER_B_MASK,
 860                 .incl_srcpt0 = false,
 861                 .send_meta0  = false,
 862                 /* Default to an invalid value */
 863                 .mirr_port = priv->ds->num_ports,
 864                 /* No TTEthernet */
 865                 .vllupformat = SJA1105_VL_FORMAT_PSFP,
 866                 .vlmarker = 0,
 867                 .vlmask = 0,
 868                 /* Only update correctionField for 1-step PTP (L2 transport) */
 869                 .ignore2stf = 0,
 870                 /* Forcefully disable VLAN filtering by telling
 871                  * the switch that VLAN has a different EtherType.
 872                  */
 873                 .tpid = ETH_P_SJA1105,
 874                 .tpid2 = ETH_P_SJA1105,
 875                 /* Enable the TTEthernet engine on SJA1110 */
 876                 .tte_en = true,
 877                 /* Set up the EtherType for control packets on SJA1110 */
 878                 .header_type = ETH_P_SJA1110,
 879         };
 880         struct sja1105_general_params_entry *general_params;
 881         struct sja1105_table *table;
 882         int rc;
 883
 884         rc = sja1105_init_topology(priv, &default_general_params);
 885         if (rc)
 886                 return rc;
 887
 888         table = &priv->static_config.tables[BLK_IDX_GENERAL_PARAMS];
 889
 890         if (table->entry_count) {
 891                 kfree(table->entries);
 892                 table->entry_count = 0;
 893         }
 894
 895         table->entries = kcalloc(table->ops->max_entry_count,
 896                                  table->ops->unpacked_entry_size, GFP_KERNEL);
 897         if (!table->entries)
 898                 return -ENOMEM;
 899
 900         table->entry_count = table->ops->max_entry_count;
 901
 902         general_params = table->entries;
 903
 904         /* This table only has a single entry */
 905         general_params[0] = default_general_params;
 906
 907         sja1110_select_tdmaconfigidx(priv);
 908
 909         return 0;
 910 }
 911
 912 static int sja1105_init_avb_params(struct sja1105_private *priv)
 913 {
 914         struct sja1105_avb_params_entry *avb;
 915         struct sja1105_table *table;
 916
 917         table = &priv->static_config.tables[BLK_IDX_AVB_PARAMS];
 918
 919         /* Discard previous AVB Parameters Table */
 920         if (table->entry_count) {
 921                 kfree(table->entries);
 922                 table->entry_count = 0;
 923         }
 924
 925         table->entries = kcalloc(table->ops->max_entry_count,
 926                                  table->ops->unpacked_entry_size, GFP_KERNEL);
 927         if (!table->entries)
 928                 return -ENOMEM;
 929
 930         table->entry_count = table->ops->max_entry_count;
 931
 932         avb = table->entries;
 933
 934         /* Configure the MAC addresses for meta frames */
 935         avb->destmeta = SJA1105_META_DMAC;
 936         avb->srcmeta  = SJA1105_META_SMAC;
 937         /* On P/Q/R/S, configure the direction of the PTP_CLK pin as input by
 938          * default. This is because there might be boards with a hardware
 939          * layout where enabling the pin as output might cause an electrical
 940          * clash. On E/T the pin is always an output, which the board designers
 941          * probably already knew, so even if there are going to be electrical
 942          * issues, there's nothing we can do.
 943          */
 944         avb->cas_master = false;
 945
 946         return 0;
 947 }
 948
 949 /* The L2 policing table is 2-stage. The table is looked up for each frame
 950  * according to the ingress port, whether it was broadcast or not, and the
 951  * classified traffic class (given by VLAN PCP). This portion of the lookup is
 952  * fixed, and gives access to the SHARINDX, an indirection register pointing
 953  * within the policing table itself, which is used to resolve the policer that
 954  * will be used for this frame.
 955  *
 956  *  Stage 1                              Stage 2
 957  * +------------+--------+              +---------------------------------+
 958  * |Port 0 TC 0 |SHARINDX|              | Policer 0: Rate, Burst, MTU     |
 959  * +------------+--------+              +---------------------------------+
 960  * |Port 0 TC 1 |SHARINDX|              | Policer 1: Rate, Burst, MTU     |
 961  * +------------+--------+              +---------------------------------+
 962  *    ...                               | Policer 2: Rate, Burst, MTU     |
 963  * +------------+--------+              +---------------------------------+
 964  * |Port 0 TC 7 |SHARINDX|              | Policer 3: Rate, Burst, MTU     |
 965  * +------------+--------+              +---------------------------------+
 966  * |Port 1 TC 0 |SHARINDX|              | Policer 4: Rate, Burst, MTU     |
 967  * +------------+--------+              +---------------------------------+
 968  *    ...                               | Policer 5: Rate, Burst, MTU     |
 969  * +------------+--------+              +---------------------------------+
 970  * |Port 1 TC 7 |SHARINDX|              | Policer 6: Rate, Burst, MTU     |
 971  * +------------+--------+              +---------------------------------+
 972  *    ...                               | Policer 7: Rate, Burst, MTU     |
 973  * +------------+--------+              +---------------------------------+
 974  * |Port 4 TC 7 |SHARINDX|                 ...
 975  * +------------+--------+
 976  * |Port 0 BCAST|SHARINDX|                 ...
 977  * +------------+--------+
 978  * |Port 1 BCAST|SHARINDX|                 ...
 979  * +------------+--------+
 980  *    ...                                  ...
 981  * +------------+--------+              +---------------------------------+
 982  * |Port 4 BCAST|SHARINDX|              | Policer 44: Rate, Burst, MTU    |
 983  * +------------+--------+              +---------------------------------+
 984  *
 985  * In this driver, we shall use policers 0-4 as statically alocated port
 986  * (matchall) policers. So we need to make the SHARINDX for all lookups
 987  * corresponding to this ingress port (8 VLAN PCP lookups and 1 broadcast
 988  * lookup) equal.
 989  * The remaining policers (40) shall be dynamically allocated for flower
 990  * policers, where the key is either vlan_prio or dst_mac ff:ff:ff:ff:ff:ff.
 991  */
 992 #define SJA1105_RATE_MBPS(speed) (((speed) * 64000) / 1000)
 993
 994 static int sja1105_init_l2_policing(struct sja1105_private *priv)
 995 {
 996         struct sja1105_l2_policing_entry *policing;
 997         struct dsa_switch *ds = priv->ds;
 998         struct sja1105_table *table;
 999         int port, tc;
1000
1001         table = &priv->static_config.tables[BLK_IDX_L2_POLICING];
1002
1003         /* Discard previous L2 Policing Table */
1004         if (table->entry_count) {
1005                 kfree(table->entries);
1006                 table->entry_count = 0;
1007         }
1008
1009         table->entries = kcalloc(table->ops->max_entry_count,
1010                                  table->ops->unpacked_entry_size, GFP_KERNEL);
1011         if (!table->entries)
1012                 return -ENOMEM;
1013
1014         table->entry_count = table->ops->max_entry_count;
1015
1016         policing = table->entries;
1017
1018         /* Setup shared indices for the matchall policers */
1019         for (port = 0; port < ds->num_ports; port++) {
1020                 int mcast = (ds->num_ports * (SJA1105_NUM_TC + 1)) + port;
1021                 int bcast = (ds->num_ports * SJA1105_NUM_TC) + port;
1022
1023                 for (tc = 0; tc < SJA1105_NUM_TC; tc++)
1024                         policing[port * SJA1105_NUM_TC + tc].sharindx = port;
1025
1026                 policing[bcast].sharindx = port;
1027                 /* Only SJA1110 has multicast policers */
1028                 if (mcast <= table->ops->max_entry_count)
1029                         policing[mcast].sharindx = port;
1030         }
1031
1032         /* Setup the matchall policer parameters */
1033         for (port = 0; port < ds->num_ports; port++) {
1034                 int mtu = VLAN_ETH_FRAME_LEN + ETH_FCS_LEN;
1035
1036                 if (dsa_is_cpu_port(ds, port) || dsa_is_dsa_port(ds, port))
1037                         mtu += VLAN_HLEN;
1038
1039                 policing[port].smax = 65535; /* Burst size in bytes */
1040                 policing[port].rate = SJA1105_RATE_MBPS(1000);
1041                 policing[port].maxlen = mtu;
1042                 policing[port].partition = 0;
1043         }
1044
1045         return 0;
1046 }
1047
1048 static int sja1105_static_config_load(struct sja1105_private *priv)
1049 {
1050         int rc;
1051
1052         sja1105_static_config_free(&priv->static_config);
1053         rc = sja1105_static_config_init(&priv->static_config,
1054                                         priv->info->static_ops,
1055                                         priv->info->device_id);
1056         if (rc)
1057                 return rc;
1058
1059         /* Build static configuration */
1060         rc = sja1105_init_mac_settings(priv);
1061         if (rc < 0)
1062                 return rc;
1063         rc = sja1105_init_mii_settings(priv);
1064         if (rc < 0)
1065                 return rc;
1066         rc = sja1105_init_static_fdb(priv);
1067         if (rc < 0)
1068                 return rc;
1069         rc = sja1105_init_static_vlan(priv);
1070         if (rc < 0)
1071                 return rc;
1072         rc = sja1105_init_l2_lookup_params(priv);
1073         if (rc < 0)
1074                 return rc;
1075         rc = sja1105_init_l2_forwarding(priv);
1076         if (rc < 0)
1077                 return rc;
1078         rc = sja1105_init_l2_forwarding_params(priv);
1079         if (rc < 0)
1080                 return rc;
1081         rc = sja1105_init_l2_policing(priv);
1082         if (rc < 0)
1083                 return rc;
1084         rc = sja1105_init_general_params(priv);
1085         if (rc < 0)
1086                 return rc;
1087         rc = sja1105_init_avb_params(priv);
1088         if (rc < 0)
1089                 return rc;
1090         rc = sja1110_init_pcp_remapping(priv);
1091         if (rc < 0)
1092                 return rc;
1093
1094         /* Send initial configuration to hardware via SPI */
1095         return sja1105_static_config_upload(priv);
1096 }
1097
1098 static int sja1105_parse_rgmii_delays(struct sja1105_private *priv)
1099 {
1100         struct dsa_switch *ds = priv->ds;
1101         int port;
1102
1103         for (port = 0; port < ds->num_ports; port++) {
1104                 if (!priv->fixed_link[port])
1105                         continue;
1106
1107                 if (priv->phy_mode[port] == PHY_INTERFACE_MODE_RGMII_RXID ||
1108                     priv->phy_mode[port] == PHY_INTERFACE_MODE_RGMII_ID)
1109                         priv->rgmii_rx_delay[port] = true;
1110
1111                 if (priv->phy_mode[port] == PHY_INTERFACE_MODE_RGMII_TXID ||
1112                     priv->phy_mode[port] == PHY_INTERFACE_MODE_RGMII_ID)
1113                         priv->rgmii_tx_delay[port] = true;
1114
1115                 if ((priv->rgmii_rx_delay[port] || priv->rgmii_tx_delay[port]) &&
1116                     !priv->info->setup_rgmii_delay)
1117                         return -EINVAL;
1118         }
1119         return 0;
1120 }
1121
1122 static int sja1105_parse_ports_node(struct sja1105_private *priv,
1123                                     struct device_node *ports_node)
1124 {
1125         struct device *dev = &priv->spidev->dev;
1126         struct device_node *child;
1127
1128         for_each_available_child_of_node(ports_node, child) {
1129                 struct device_node *phy_node;
1130                 phy_interface_t phy_mode;
1131                 u32 index;
1132                 int err;
1133
1134                 /* Get switch port number from DT */
1135                 if (of_property_read_u32(child, "reg", &index) < 0) {
1136                         dev_err(dev, "Port number not defined in device tree "
1137                                 "(property \"reg\")\n");
1138                         of_node_put(child);
1139                         return -ENODEV;
1140                 }
1141
1142                 /* Get PHY mode from DT */
1143                 err = of_get_phy_mode(child, &phy_mode);
1144                 if (err) {
1145                         dev_err(dev, "Failed to read phy-mode or "
1146                                 "phy-interface-type property for port %d\n",
1147                                 index);
1148                         of_node_put(child);
1149                         return -ENODEV;
1150                 }
1151
1152                 phy_node = of_parse_phandle(child, "phy-handle", 0);
1153                 if (!phy_node) {
1154                         if (!of_phy_is_fixed_link(child)) {
1155                                 dev_err(dev, "phy-handle or fixed-link "
1156                                         "properties missing!\n");
1157                                 of_node_put(child);
1158                                 return -ENODEV;
1159                         }
1160                         /* phy-handle is missing, but fixed-link isn't.
1161                          * So it's a fixed link. Default to PHY role.
1162                          */
1163                         priv->fixed_link[index] = true;
1164                 } else {
1165                         of_node_put(phy_node);
1166                 }
1167
1168                 priv->phy_mode[index] = phy_mode;
1169         }
1170
1171         return 0;
1172 }
1173
1174 static int sja1105_parse_dt(struct sja1105_private *priv)
1175 {
1176         struct device *dev = &priv->spidev->dev;
1177         struct device_node *switch_node = dev->of_node;
1178         struct device_node *ports_node;
1179         int rc;
1180
1181         ports_node = of_get_child_by_name(switch_node, "ports");
1182         if (!ports_node)
1183                 ports_node = of_get_child_by_name(switch_node, "ethernet-ports");
1184         if (!ports_node) {
1185                 dev_err(dev, "Incorrect bindings: absent \"ports\" node\n");
1186                 return -ENODEV;
1187         }
1188
1189         rc = sja1105_parse_ports_node(priv, ports_node);
1190         of_node_put(ports_node);
1191
1192         return rc;
1193 }
1194
1195 /* Convert link speed from SJA1105 to ethtool encoding */
1196 static int sja1105_port_speed_to_ethtool(struct sja1105_private *priv,
1197                                          u64 speed)
1198 {
1199         if (speed == priv->info->port_speed[SJA1105_SPEED_10MBPS])
1200                 return SPEED_10;
1201         if (speed == priv->info->port_speed[SJA1105_SPEED_100MBPS])
1202                 return SPEED_100;
1203         if (speed == priv->info->port_speed[SJA1105_SPEED_1000MBPS])
1204                 return SPEED_1000;
1205         if (speed == priv->info->port_speed[SJA1105_SPEED_2500MBPS])
1206                 return SPEED_2500;
1207         return SPEED_UNKNOWN;
1208 }
1209
1210 /* Set link speed in the MAC configuration for a specific port. */
1211 static int sja1105_adjust_port_config(struct sja1105_private *priv, int port,
1212                                       int speed_mbps)
1213 {
1214         struct sja1105_mac_config_entry *mac;
1215         struct device *dev = priv->ds->dev;
1216         u64 speed;
1217         int rc;
1218
1219         /* On P/Q/R/S, one can read from the device via the MAC reconfiguration
1220          * tables. On E/T, MAC reconfig tables are not readable, only writable.
1221          * We have to *know* what the MAC looks like.  For the sake of keeping
1222          * the code common, we'll use the static configuration tables as a
1223          * reasonable approximation for both E/T and P/Q/R/S.
1224          */
1225         mac = priv->static_config.tables[BLK_IDX_MAC_CONFIG].entries;
1226
1227         switch (speed_mbps) {
1228         case SPEED_UNKNOWN:
1229                 /* PHYLINK called sja1105_mac_config() to inform us about
1230                  * the state->interface, but AN has not completed and the
1231                  * speed is not yet valid. UM10944.pdf says that setting
1232                  * SJA1105_SPEED_AUTO at runtime disables the port, so that is
1233                  * ok for power consumption in case AN will never complete -
1234                  * otherwise PHYLINK should come back with a new update.
1235                  */
1236                 speed = priv->info->port_speed[SJA1105_SPEED_AUTO];
1237                 break;
1238         case SPEED_10:
1239                 speed = priv->info->port_speed[SJA1105_SPEED_10MBPS];
1240                 break;
1241         case SPEED_100:
1242                 speed = priv->info->port_speed[SJA1105_SPEED_100MBPS];
1243                 break;
1244         case SPEED_1000:
1245                 speed = priv->info->port_speed[SJA1105_SPEED_1000MBPS];
1246                 break;
1247         case SPEED_2500:
1248                 speed = priv->info->port_speed[SJA1105_SPEED_2500MBPS];
1249                 break;
1250         default:
1251                 dev_err(dev, "Invalid speed %iMbps\n", speed_mbps);
1252                 return -EINVAL;
1253         }
1254
1255         /* Overwrite SJA1105_SPEED_AUTO from the static MAC configuration
1256          * table, since this will be used for the clocking setup, and we no
1257          * longer need to store it in the static config (already told hardware
1258          * we want auto during upload phase).
1259          * Actually for the SGMII port, the MAC is fixed at 1 Gbps and
1260          * we need to configure the PCS only (if even that).
1261          */
1262         if (priv->phy_mode[port] == PHY_INTERFACE_MODE_SGMII)
1263                 mac[port].speed = priv->info->port_speed[SJA1105_SPEED_1000MBPS];
1264         else if (priv->phy_mode[port] == PHY_INTERFACE_MODE_2500BASEX)
1265                 mac[port].speed = priv->info->port_speed[SJA1105_SPEED_2500MBPS];
1266         else
1267                 mac[port].speed = speed;
1268
1269         /* Write to the dynamic reconfiguration tables */
1270         rc = sja1105_dynamic_config_write(priv, BLK_IDX_MAC_CONFIG, port,
1271                                           &mac[port], true);
1272         if (rc < 0) {
1273                 dev_err(dev, "Failed to write MAC config: %d\n", rc);
1274                 return rc;
1275         }
1276
1277         /* Reconfigure the PLLs for the RGMII interfaces (required 125 MHz at
1278          * gigabit, 25 MHz at 100 Mbps and 2.5 MHz at 10 Mbps). For MII and
1279          * RMII no change of the clock setup is required. Actually, changing
1280          * the clock setup does interrupt the clock signal for a certain time
1281          * which causes trouble for all PHYs relying on this signal.
1282          */
1283         if (!phy_interface_mode_is_rgmii(priv->phy_mode[port]))
1284                 return 0;
1285
1286         return sja1105_clocking_setup_port(priv, port);
1287 }
1288
1289 /* The SJA1105 MAC programming model is through the static config (the xMII
1290  * Mode table cannot be dynamically reconfigured), and we have to program
1291  * that early (earlier than PHYLINK calls us, anyway).
1292  * So just error out in case the connected PHY attempts to change the initial
1293  * system interface MII protocol from what is defined in the DT, at least for
1294  * now.
1295  */
1296 static bool sja1105_phy_mode_mismatch(struct sja1105_private *priv, int port,
1297                                       phy_interface_t interface)
1298 {
1299         return priv->phy_mode[port] != interface;
1300 }
1301
1302 static void sja1105_mac_config(struct dsa_switch *ds, int port,
1303                                unsigned int mode,
1304                                const struct phylink_link_state *state)
1305 {
1306         struct dsa_port *dp = dsa_to_port(ds, port);
1307         struct sja1105_private *priv = ds->priv;
1308         struct dw_xpcs *xpcs;
1309
1310         if (sja1105_phy_mode_mismatch(priv, port, state->interface)) {
1311                 dev_err(ds->dev, "Changing PHY mode to %s not supported!\n",
1312                         phy_modes(state->interface));
1313                 return;
1314         }
1315
1316         xpcs = priv->xpcs[port];
1317
1318         if (xpcs)
1319                 phylink_set_pcs(dp->pl, &xpcs->pcs);
1320 }
1321
1322 static void sja1105_mac_link_down(struct dsa_switch *ds, int port,
1323                                   unsigned int mode,
1324                                   phy_interface_t interface)
1325 {
1326         sja1105_inhibit_tx(ds->priv, BIT(port), true);
1327 }
1328
1329 static void sja1105_mac_link_up(struct dsa_switch *ds, int port,
1330                                 unsigned int mode,
1331                                 phy_interface_t interface,
1332                                 struct phy_device *phydev,
1333                                 int speed, int duplex,
1334                                 bool tx_pause, bool rx_pause)
1335 {
1336         struct sja1105_private *priv = ds->priv;
1337
1338         sja1105_adjust_port_config(priv, port, speed);
1339
1340         sja1105_inhibit_tx(priv, BIT(port), false);
1341 }
1342
1343 static void sja1105_phylink_validate(struct dsa_switch *ds, int port,
1344                                      unsigned long *supported,
1345                                      struct phylink_link_state *state)
1346 {
1347         /* Construct a new mask which exhaustively contains all link features
1348          * supported by the MAC, and then apply that (logical AND) to what will
1349          * be sent to the PHY for "marketing".
1350          */
1351         __ETHTOOL_DECLARE_LINK_MODE_MASK(mask) = { 0, };
1352         struct sja1105_private *priv = ds->priv;
1353         struct sja1105_xmii_params_entry *mii;
1354
1355         mii = priv->static_config.tables[BLK_IDX_XMII_PARAMS].entries;
1356
1357         /* include/linux/phylink.h says:
1358          *     When @state->interface is %PHY_INTERFACE_MODE_NA, phylink
1359          *     expects the MAC driver to return all supported link modes.
1360          */
1361         if (state->interface != PHY_INTERFACE_MODE_NA &&
1362             sja1105_phy_mode_mismatch(priv, port, state->interface)) {
1363                 bitmap_zero(supported, __ETHTOOL_LINK_MODE_MASK_NBITS);
1364                 return;
1365         }
1366
1367         /* The MAC does not support pause frames, and also doesn't
1368          * support half-duplex traffic modes.
1369          */
1370         phylink_set(mask, Autoneg);
1371         phylink_set(mask, MII);
1372         phylink_set(mask, 10baseT_Full);
1373         phylink_set(mask, 100baseT_Full);
1374         phylink_set(mask, 100baseT1_Full);
1375         if (mii->xmii_mode[port] == XMII_MODE_RGMII ||
1376             mii->xmii_mode[port] == XMII_MODE_SGMII)
1377                 phylink_set(mask, 1000baseT_Full);
1378         if (priv->info->supports_2500basex[port]) {
1379                 phylink_set(mask, 2500baseT_Full);
1380                 phylink_set(mask, 2500baseX_Full);
1381         }
1382
1383         bitmap_and(supported, supported, mask, __ETHTOOL_LINK_MODE_MASK_NBITS);
1384         bitmap_and(state->advertising, state->advertising, mask,
1385                    __ETHTOOL_LINK_MODE_MASK_NBITS);
1386 }
1387
1388 static int
1389 sja1105_find_static_fdb_entry(struct sja1105_private *priv, int port,
1390                               const struct sja1105_l2_lookup_entry *requested)
1391 {
1392         struct sja1105_l2_lookup_entry *l2_lookup;
1393         struct sja1105_table *table;
1394         int i;
1395
1396         table = &priv->static_config.tables[BLK_IDX_L2_LOOKUP];
1397         l2_lookup = table->entries;
1398
1399         for (i = 0; i < table->entry_count; i++)
1400                 if (l2_lookup[i].macaddr == requested->macaddr &&
1401                     l2_lookup[i].vlanid == requested->vlanid &&
1402                     l2_lookup[i].destports & BIT(port))
1403                         return i;
1404
1405         return -1;
1406 }
1407
1408 /* We want FDB entries added statically through the bridge command to persist
1409  * across switch resets, which are a common thing during normal SJA1105
1410  * operation. So we have to back them up in the static configuration tables
1411  * and hence apply them on next static config upload... yay!
1412  */
1413 static int
1414 sja1105_static_fdb_change(struct sja1105_private *priv, int port,
1415                           const struct sja1105_l2_lookup_entry *requested,
1416                           bool keep)
1417 {
1418         struct sja1105_l2_lookup_entry *l2_lookup;
1419         struct sja1105_table *table;
1420         int rc, match;
1421
1422         table = &priv->static_config.tables[BLK_IDX_L2_LOOKUP];
1423
1424         match = sja1105_find_static_fdb_entry(priv, port, requested);
1425         if (match < 0) {
1426                 /* Can't delete a missing entry. */
1427                 if (!keep)
1428                         return 0;
1429
1430                 /* No match => new entry */
1431                 rc = sja1105_table_resize(table, table->entry_count + 1);
1432                 if (rc)
1433                         return rc;
1434
1435                 match = table->entry_count - 1;
1436         }
1437
1438         /* Assign pointer after the resize (it may be new memory) */
1439         l2_lookup = table->entries;
1440
1441         /* We have a match.
1442          * If the job was to add this FDB entry, it's already done (mostly
1443          * anyway, since the port forwarding mask may have changed, case in
1444          * which we update it).
1445          * Otherwise we have to delete it.
1446          */
1447         if (keep) {
1448                 l2_lookup[match] = *requested;
1449                 return 0;
1450         }
1451
1452         /* To remove, the strategy is to overwrite the element with
1453          * the last one, and then reduce the array size by 1
1454          */
1455         l2_lookup[match] = l2_lookup[table->entry_count - 1];
1456         return sja1105_table_resize(table, table->entry_count - 1);
1457 }
1458
1459 /* First-generation switches have a 4-way set associative TCAM that
1460  * holds the FDB entries. An FDB index spans from 0 to 1023 and is comprised of
1461  * a "bin" (grouping of 4 entries) and a "way" (an entry within a bin).
1462  * For the placement of a newly learnt FDB entry, the switch selects the bin
1463  * based on a hash function, and the way within that bin incrementally.
1464  */
1465 static int sja1105et_fdb_index(int bin, int way)
1466 {
1467         return bin * SJA1105ET_FDB_BIN_SIZE + way;
1468 }
1469
1470 static int sja1105et_is_fdb_entry_in_bin(struct sja1105_private *priv, int bin,
1471                                          const u8 *addr, u16 vid,
1472                                          struct sja1105_l2_lookup_entry *match,
1473                                          int *last_unused)
1474 {
1475         int way;
1476
1477         for (way = 0; way < SJA1105ET_FDB_BIN_SIZE; way++) {
1478                 struct sja1105_l2_lookup_entry l2_lookup = {0};
1479                 int index = sja1105et_fdb_index(bin, way);
1480
1481                 /* Skip unused entries, optionally marking them
1482                  * into the return value
1483                  */
1484                 if (sja1105_dynamic_config_read(priv, BLK_IDX_L2_LOOKUP,
1485                                                 index, &l2_lookup)) {
1486                         if (last_unused)
1487                                 *last_unused = way;
1488                         continue;
1489                 }
1490
1491                 if (l2_lookup.macaddr == ether_addr_to_u64(addr) &&
1492                     l2_lookup.vlanid == vid) {
1493                         if (match)
1494                                 *match = l2_lookup;
1495                         return way;
1496                 }
1497         }
1498         /* Return an invalid entry index if not found */
1499         return -1;
1500 }
1501
1502 int sja1105et_fdb_add(struct dsa_switch *ds, int port,
1503                       const unsigned char *addr, u16 vid)
1504 {
1505         struct sja1105_l2_lookup_entry l2_lookup = {0}, tmp;
1506         struct sja1105_private *priv = ds->priv;
1507         struct device *dev = ds->dev;
1508         int last_unused = -1;
1509         int start, end, i;
1510         int bin, way, rc;
1511
1512         bin = sja1105et_fdb_hash(priv, addr, vid);
1513
1514         way = sja1105et_is_fdb_entry_in_bin(priv, bin, addr, vid,
1515                                             &l2_lookup, &last_unused);
1516         if (way >= 0) {
1517                 /* We have an FDB entry. Is our port in the destination
1518                  * mask? If yes, we need to do nothing. If not, we need
1519                  * to rewrite the entry by adding this port to it.
1520                  */
1521                 if ((l2_lookup.destports & BIT(port)) && l2_lookup.lockeds)
1522                         return 0;
1523                 l2_lookup.destports |= BIT(port);
1524         } else {
1525                 int index = sja1105et_fdb_index(bin, way);
1526
1527                 /* We don't have an FDB entry. We construct a new one and
1528                  * try to find a place for it within the FDB table.
1529                  */
1530                 l2_lookup.macaddr = ether_addr_to_u64(addr);
1531                 l2_lookup.destports = BIT(port);
1532                 l2_lookup.vlanid = vid;
1533
1534                 if (last_unused >= 0) {
1535                         way = last_unused;
1536                 } else {
1537                         /* Bin is full, need to evict somebody.
1538                          * Choose victim at random. If you get these messages
1539                          * often, you may need to consider changing the
1540                          * distribution function:
1541                          * static_config[BLK_IDX_L2_LOOKUP_PARAMS].entries->poly
1542                          */
1543                         get_random_bytes(&way, sizeof(u8));
1544                         way %= SJA1105ET_FDB_BIN_SIZE;
1545                         dev_warn(dev, "Warning, FDB bin %d full while adding entry for %pM. Evicting entry %u.\n",
1546                                  bin, addr, way);
1547                         /* Evict entry */
1548                         sja1105_dynamic_config_write(priv, BLK_IDX_L2_LOOKUP,
1549                                                      index, NULL, false);
1550                 }
1551         }
1552         l2_lookup.lockeds = true;
1553         l2_lookup.index = sja1105et_fdb_index(bin, way);
1554
1555         rc = sja1105_dynamic_config_write(priv, BLK_IDX_L2_LOOKUP,
1556                                           l2_lookup.index, &l2_lookup,
1557                                           true);
1558         if (rc < 0)
1559                 return rc;
1560
1561         /* Invalidate a dynamically learned entry if that exists */
1562         start = sja1105et_fdb_index(bin, 0);
1563         end = sja1105et_fdb_index(bin, way);
1564
1565         for (i = start; i < end; i++) {
1566                 rc = sja1105_dynamic_config_read(priv, BLK_IDX_L2_LOOKUP,
1567                                                  i, &tmp);
1568                 if (rc == -ENOENT)
1569                         continue;
1570                 if (rc)
1571                         return rc;
1572
1573                 if (tmp.macaddr != ether_addr_to_u64(addr) || tmp.vlanid != vid)
1574                         continue;
1575
1576                 rc = sja1105_dynamic_config_write(priv, BLK_IDX_L2_LOOKUP,
1577                                                   i, NULL, false);
1578                 if (rc)
1579                         return rc;
1580
1581                 break;
1582         }
1583
1584         return sja1105_static_fdb_change(priv, port, &l2_lookup, true);
1585 }
1586
1587 int sja1105et_fdb_del(struct dsa_switch *ds, int port,
1588                       const unsigned char *addr, u16 vid)
1589 {
1590         struct sja1105_l2_lookup_entry l2_lookup = {0};
1591         struct sja1105_private *priv = ds->priv;
1592         int index, bin, way, rc;
1593         bool keep;
1594
1595         bin = sja1105et_fdb_hash(priv, addr, vid);
1596         way = sja1105et_is_fdb_entry_in_bin(priv, bin, addr, vid,
1597                                             &l2_lookup, NULL);
1598         if (way < 0)
1599                 return 0;
1600         index = sja1105et_fdb_index(bin, way);
1601
1602         /* We have an FDB entry. Is our port in the destination mask? If yes,
1603          * we need to remove it. If the resulting port mask becomes empty, we
1604          * need to completely evict the FDB entry.
1605          * Otherwise we just write it back.
1606          */
1607         l2_lookup.destports &= ~BIT(port);
1608
1609         if (l2_lookup.destports)
1610                 keep = true;
1611         else
1612                 keep = false;
1613
1614         rc = sja1105_dynamic_config_write(priv, BLK_IDX_L2_LOOKUP,
1615                                           index, &l2_lookup, keep);
1616         if (rc < 0)
1617                 return rc;
1618
1619         return sja1105_static_fdb_change(priv, port, &l2_lookup, keep);
1620 }
1621
1622 int sja1105pqrs_fdb_add(struct dsa_switch *ds, int port,
1623                         const unsigned char *addr, u16 vid)
1624 {
1625         struct sja1105_l2_lookup_entry l2_lookup = {0}, tmp;
1626         struct sja1105_private *priv = ds->priv;
1627         int rc, i;
1628
1629         /* Search for an existing entry in the FDB table */
1630         l2_lookup.macaddr = ether_addr_to_u64(addr);
1631         l2_lookup.vlanid = vid;
1632         l2_lookup.mask_macaddr = GENMASK_ULL(ETH_ALEN * 8 - 1, 0);
1633         l2_lookup.mask_vlanid = VLAN_VID_MASK;
1634         l2_lookup.destports = BIT(port);
1635
1636         tmp = l2_lookup;
1637
1638         rc = sja1105_dynamic_config_read(priv, BLK_IDX_L2_LOOKUP,
1639                                          SJA1105_SEARCH, &tmp);
1640         if (rc == 0 && tmp.index != SJA1105_MAX_L2_LOOKUP_COUNT - 1) {
1641                 /* Found a static entry and this port is already in the entry's
1642                  * port mask => job done
1643                  */
1644                 if ((tmp.destports & BIT(port)) && tmp.lockeds)
1645                         return 0;
1646
1647                 l2_lookup = tmp;
1648
1649                 /* l2_lookup.index is populated by the switch in case it
1650                  * found something.
1651                  */
1652                 l2_lookup.destports |= BIT(port);
1653                 goto skip_finding_an_index;
1654         }
1655
1656         /* Not found, so try to find an unused spot in the FDB.
1657          * This is slightly inefficient because the strategy is knock-knock at
1658          * every possible position from 0 to 1023.
1659          */
1660         for (i = 0; i < SJA1105_MAX_L2_LOOKUP_COUNT; i++) {
1661                 rc = sja1105_dynamic_config_read(priv, BLK_IDX_L2_LOOKUP,
1662                                                  i, NULL);
1663                 if (rc < 0)
1664                         break;
1665         }
1666         if (i == SJA1105_MAX_L2_LOOKUP_COUNT) {
1667                 dev_err(ds->dev, "FDB is full, cannot add entry.\n");
1668                 return -EINVAL;
1669         }
1670         l2_lookup.index = i;
1671
1672 skip_finding_an_index:
1673         l2_lookup.lockeds = true;
1674
1675         rc = sja1105_dynamic_config_write(priv, BLK_IDX_L2_LOOKUP,
1676                                           l2_lookup.index, &l2_lookup,
1677                                           true);
1678         if (rc < 0)
1679                 return rc;
1680
1681         /* The switch learns dynamic entries and looks up the FDB left to
1682          * right. It is possible that our addition was concurrent with the
1683          * dynamic learning of the same address, so now that the static entry
1684          * has been installed, we are certain that address learning for this
1685          * particular address has been turned off, so the dynamic entry either
1686          * is in the FDB at an index smaller than the static one, or isn't (it
1687          * can also be at a larger index, but in that case it is inactive
1688          * because the static FDB entry will match first, and the dynamic one
1689          * will eventually age out). Search for a dynamically learned address
1690          * prior to our static one and invalidate it.
1691          */
1692         tmp = l2_lookup;
1693
1694         rc = sja1105_dynamic_config_read(priv, BLK_IDX_L2_LOOKUP,
1695                                          SJA1105_SEARCH, &tmp);
1696         if (rc < 0) {
1697                 dev_err(ds->dev,
1698                         "port %d failed to read back entry for %pM vid %d: %pe\n",
1699                         port, addr, vid, ERR_PTR(rc));
1700                 return rc;
1701         }
1702
1703         if (tmp.index < l2_lookup.index) {
1704                 rc = sja1105_dynamic_config_write(priv, BLK_IDX_L2_LOOKUP,
1705                                                   tmp.index, NULL, false);
1706                 if (rc < 0)
1707                         return rc;
1708         }
1709
1710         return sja1105_static_fdb_change(priv, port, &l2_lookup, true);
1711 }
1712
1713 int sja1105pqrs_fdb_del(struct dsa_switch *ds, int port,
1714                         const unsigned char *addr, u16 vid)
1715 {
1716         struct sja1105_l2_lookup_entry l2_lookup = {0};
1717         struct sja1105_private *priv = ds->priv;
1718         bool keep;
1719         int rc;
1720
1721         l2_lookup.macaddr = ether_addr_to_u64(addr);
1722         l2_lookup.vlanid = vid;
1723         l2_lookup.mask_macaddr = GENMASK_ULL(ETH_ALEN * 8 - 1, 0);
1724         l2_lookup.mask_vlanid = VLAN_VID_MASK;
1725         l2_lookup.destports = BIT(port);
1726
1727         rc = sja1105_dynamic_config_read(priv, BLK_IDX_L2_LOOKUP,
1728                                          SJA1105_SEARCH, &l2_lookup);
1729         if (rc < 0)
1730                 return 0;
1731
1732         l2_lookup.destports &= ~BIT(port);
1733
1734         /* Decide whether we remove just this port from the FDB entry,
1735          * or if we remove it completely.
1736          */
1737         if (l2_lookup.destports)
1738                 keep = true;
1739         else
1740                 keep = false;
1741
1742         rc = sja1105_dynamic_config_write(priv, BLK_IDX_L2_LOOKUP,
1743                                           l2_lookup.index, &l2_lookup, keep);
1744         if (rc < 0)
1745                 return rc;
1746
1747         return sja1105_static_fdb_change(priv, port, &l2_lookup, keep);
1748 }
1749
1750 static int sja1105_fdb_add(struct dsa_switch *ds, int port,
1751                            const unsigned char *addr, u16 vid)
1752 {
1753         struct sja1105_private *priv = ds->priv;
1754
1755         return priv->info->fdb_add_cmd(ds, port, addr, vid);
1756 }
1757
1758 static int sja1105_fdb_del(struct dsa_switch *ds, int port,
1759                            const unsigned char *addr, u16 vid)
1760 {
1761         struct sja1105_private *priv = ds->priv;
1762
1763         return priv->info->fdb_del_cmd(ds, port, addr, vid);
1764 }
1765
1766 static int sja1105_fdb_dump(struct dsa_switch *ds, int port,
1767                             dsa_fdb_dump_cb_t *cb, void *data)
1768 {
1769         struct sja1105_private *priv = ds->priv;
1770         struct device *dev = ds->dev;
1771         int i;
1772
1773         for (i = 0; i < SJA1105_MAX_L2_LOOKUP_COUNT; i++) {
1774                 struct sja1105_l2_lookup_entry l2_lookup = {0};
1775                 u8 macaddr[ETH_ALEN];
1776                 int rc;
1777
1778                 rc = sja1105_dynamic_config_read(priv, BLK_IDX_L2_LOOKUP,
1779                                                  i, &l2_lookup);
1780                 /* No fdb entry at i, not an issue */
1781                 if (rc == -ENOENT)
1782                         continue;
1783                 if (rc) {
1784                         dev_err(dev, "Failed to dump FDB: %d\n", rc);
1785                         return rc;
1786                 }
1787
1788                 /* FDB dump callback is per port. This means we have to
1789                  * disregard a valid entry if it's not for this port, even if
1790                  * only to revisit it later. This is inefficient because the
1791                  * 1024-sized FDB table needs to be traversed 4 times through
1792                  * SPI during a 'bridge fdb show' command.
1793                  */
1794                 if (!(l2_lookup.destports & BIT(port)))
1795                         continue;
1796
1797                 /* We need to hide the FDB entry for unknown multicast */
1798                 if (l2_lookup.macaddr == SJA1105_UNKNOWN_MULTICAST &&
1799                     l2_lookup.mask_macaddr == SJA1105_UNKNOWN_MULTICAST)
1800                         continue;
1801
1802                 u64_to_ether_addr(l2_lookup.macaddr, macaddr);
1803
1804                 /* We need to hide the dsa_8021q VLANs from the user. */
1805                 if (!priv->vlan_aware)
1806                         l2_lookup.vlanid = 0;
1807                 rc = cb(macaddr, l2_lookup.vlanid, l2_lookup.lockeds, data);
1808                 if (rc)
1809                         return rc;
1810         }
1811         return 0;
1812 }
1813
1814 static void sja1105_fast_age(struct dsa_switch *ds, int port)
1815 {
1816         struct sja1105_private *priv = ds->priv;
1817         int i;
1818
1819         for (i = 0; i < SJA1105_MAX_L2_LOOKUP_COUNT; i++) {
1820                 struct sja1105_l2_lookup_entry l2_lookup = {0};
1821                 u8 macaddr[ETH_ALEN];
1822                 int rc;
1823
1824                 rc = sja1105_dynamic_config_read(priv, BLK_IDX_L2_LOOKUP,
1825                                                  i, &l2_lookup);
1826                 /* No fdb entry at i, not an issue */
1827                 if (rc == -ENOENT)
1828                         continue;
1829                 if (rc) {
1830                         dev_err(ds->dev, "Failed to read FDB: %pe\n",
1831                                 ERR_PTR(rc));
1832                         return;
1833                 }
1834
1835                 if (!(l2_lookup.destports & BIT(port)))
1836                         continue;
1837
1838                 /* Don't delete static FDB entries */
1839                 if (l2_lookup.lockeds)
1840                         continue;
1841
1842                 u64_to_ether_addr(l2_lookup.macaddr, macaddr);
1843
1844                 rc = sja1105_fdb_del(ds, port, macaddr, l2_lookup.vlanid);
1845                 if (rc) {
1846                         dev_err(ds->dev,
1847                                 "Failed to delete FDB entry %pM vid %lld: %pe\n",
1848                                 macaddr, l2_lookup.vlanid, ERR_PTR(rc));
1849                         return;
1850                 }
1851         }
1852 }
1853
1854 static int sja1105_mdb_add(struct dsa_switch *ds, int port,
1855                            const struct switchdev_obj_port_mdb *mdb)
1856 {
1857         return sja1105_fdb_add(ds, port, mdb->addr, mdb->vid);
1858 }
1859
1860 static int sja1105_mdb_del(struct dsa_switch *ds, int port,
1861                            const struct switchdev_obj_port_mdb *mdb)
1862 {
1863         return sja1105_fdb_del(ds, port, mdb->addr, mdb->vid);
1864 }
1865
1866 /* Common function for unicast and broadcast flood configuration.
1867  * Flooding is configured between each {ingress, egress} port pair, and since
1868  * the bridge's semantics are those of "egress flooding", it means we must
1869  * enable flooding towards this port from all ingress ports that are in the
1870  * same forwarding domain.
1871  */
1872 static int sja1105_manage_flood_domains(struct sja1105_private *priv)
1873 {
1874         struct sja1105_l2_forwarding_entry *l2_fwd;
1875         struct dsa_switch *ds = priv->ds;
1876         int from, to, rc;
1877
1878         l2_fwd = priv->static_config.tables[BLK_IDX_L2_FORWARDING].entries;
1879
1880         for (from = 0; from < ds->num_ports; from++) {
1881                 u64 fl_domain = 0, bc_domain = 0;
1882
1883                 for (to = 0; to < priv->ds->num_ports; to++) {
1884                         if (!sja1105_can_forward(l2_fwd, from, to))
1885                                 continue;
1886
1887                         if (priv->ucast_egress_floods & BIT(to))
1888                                 fl_domain |= BIT(to);
1889                         if (priv->bcast_egress_floods & BIT(to))
1890                                 bc_domain |= BIT(to);
1891                 }
1892
1893                 /* Nothing changed, nothing to do */
1894                 if (l2_fwd[from].fl_domain == fl_domain &&
1895                     l2_fwd[from].bc_domain == bc_domain)
1896                         continue;
1897
1898                 l2_fwd[from].fl_domain = fl_domain;
1899                 l2_fwd[from].bc_domain = bc_domain;
1900
1901                 rc = sja1105_dynamic_config_write(priv, BLK_IDX_L2_FORWARDING,
1902                                                   from, &l2_fwd[from], true);
1903                 if (rc < 0)
1904                         return rc;
1905         }
1906
1907         return 0;
1908 }
1909
1910 static int sja1105_bridge_member(struct dsa_switch *ds, int port,
1911                                  struct net_device *br, bool member)
1912 {
1913         struct sja1105_l2_forwarding_entry *l2_fwd;
1914         struct sja1105_private *priv = ds->priv;
1915         int i, rc;
1916
1917         l2_fwd = priv->static_config.tables[BLK_IDX_L2_FORWARDING].entries;
1918
1919         for (i = 0; i < ds->num_ports; i++) {
1920                 /* Add this port to the forwarding matrix of the
1921                  * other ports in the same bridge, and viceversa.
1922                  */
1923                 if (!dsa_is_user_port(ds, i))
1924                         continue;
1925                 /* For the ports already under the bridge, only one thing needs
1926                  * to be done, and that is to add this port to their
1927                  * reachability domain. So we can perform the SPI write for
1928                  * them immediately. However, for this port itself (the one
1929                  * that is new to the bridge), we need to add all other ports
1930                  * to its reachability domain. So we do that incrementally in
1931                  * this loop, and perform the SPI write only at the end, once
1932                  * the domain contains all other bridge ports.
1933                  */
1934                 if (i == port)
1935                         continue;
1936                 if (dsa_to_port(ds, i)->bridge_dev != br)
1937                         continue;
1938                 sja1105_port_allow_traffic(l2_fwd, i, port, member);
1939                 sja1105_port_allow_traffic(l2_fwd, port, i, member);
1940
1941                 rc = sja1105_dynamic_config_write(priv, BLK_IDX_L2_FORWARDING,
1942                                                   i, &l2_fwd[i], true);
1943                 if (rc < 0)
1944                         return rc;
1945         }
1946
1947         rc = sja1105_dynamic_config_write(priv, BLK_IDX_L2_FORWARDING,
1948                                           port, &l2_fwd[port], true);
1949         if (rc)
1950                 return rc;
1951
1952         rc = sja1105_commit_pvid(ds, port);
1953         if (rc)
1954                 return rc;
1955
1956         return sja1105_manage_flood_domains(priv);
1957 }
1958
1959 static void sja1105_bridge_stp_state_set(struct dsa_switch *ds, int port,
1960                                          u8 state)
1961 {
1962         struct dsa_port *dp = dsa_to_port(ds, port);
1963         struct sja1105_private *priv = ds->priv;
1964         struct sja1105_mac_config_entry *mac;
1965
1966         mac = priv->static_config.tables[BLK_IDX_MAC_CONFIG].entries;
1967
1968         switch (state) {
1969         case BR_STATE_DISABLED:
1970         case BR_STATE_BLOCKING:
1971                 /* From UM10944 description of DRPDTAG (why put this there?):
1972                  * "Management traffic flows to the port regardless of the state
1973                  * of the INGRESS flag". So BPDUs are still be allowed to pass.
1974                  * At the moment no difference between DISABLED and BLOCKING.
1975                  */
1976                 mac[port].ingress   = false;
1977                 mac[port].egress    = false;
1978                 mac[port].dyn_learn = false;
1979                 break;
1980         case BR_STATE_LISTENING:
1981                 mac[port].ingress   = true;
1982                 mac[port].egress    = false;
1983                 mac[port].dyn_learn = false;
1984                 break;
1985         case BR_STATE_LEARNING:
1986                 mac[port].ingress   = true;
1987                 mac[port].egress    = false;
1988                 mac[port].dyn_learn = dp->learning;
1989                 break;
1990         case BR_STATE_FORWARDING:
1991                 mac[port].ingress   = true;
1992                 mac[port].egress    = true;
1993                 mac[port].dyn_learn = dp->learning;
1994                 break;
1995         default:
1996                 dev_err(ds->dev, "invalid STP state: %d\n", state);
1997                 return;
1998         }
1999
2000         sja1105_dynamic_config_write(priv, BLK_IDX_MAC_CONFIG, port,
2001                                      &mac[port], true);
2002 }
2003
2004 static int sja1105_bridge_join(struct dsa_switch *ds, int port,
2005                                struct net_device *br)
2006 {
2007         return sja1105_bridge_member(ds, port, br, true);
2008 }
2009
2010 static void sja1105_bridge_leave(struct dsa_switch *ds, int port,
2011                                  struct net_device *br)
2012 {
2013         sja1105_bridge_member(ds, port, br, false);
2014 }
2015
2016 #define BYTES_PER_KBIT (1000LL / 8)
2017
2018 static int sja1105_find_unused_cbs_shaper(struct sja1105_private *priv)
2019 {
2020         int i;
2021
2022         for (i = 0; i < priv->info->num_cbs_shapers; i++)
2023                 if (!priv->cbs[i].idle_slope && !priv->cbs[i].send_slope)
2024                         return i;
2025
2026         return -1;
2027 }
2028
2029 static int sja1105_delete_cbs_shaper(struct sja1105_private *priv, int port,
2030                                      int prio)
2031 {
2032         int i;
2033
2034         for (i = 0; i < priv->info->num_cbs_shapers; i++) {
2035                 struct sja1105_cbs_entry *cbs = &priv->cbs[i];
2036
2037                 if (cbs->port == port && cbs->prio == prio) {
2038                         memset(cbs, 0, sizeof(*cbs));
2039                         return sja1105_dynamic_config_write(priv, BLK_IDX_CBS,
2040                                                             i, cbs, true);
2041                 }
2042         }
2043
2044         return 0;
2045 }
2046
2047 static int sja1105_setup_tc_cbs(struct dsa_switch *ds, int port,
2048                                 struct tc_cbs_qopt_offload *offload)
2049 {
2050         struct sja1105_private *priv = ds->priv;
2051         struct sja1105_cbs_entry *cbs;
2052         int index;
2053
2054         if (!offload->enable)
2055                 return sja1105_delete_cbs_shaper(priv, port, offload->queue);
2056
2057         index = sja1105_find_unused_cbs_shaper(priv);
2058         if (index < 0)
2059                 return -ENOSPC;
2060
2061         cbs = &priv->cbs[index];
2062         cbs->port = port;
2063         cbs->prio = offload->queue;
2064         /* locredit and sendslope are negative by definition. In hardware,
2065          * positive values must be provided, and the negative sign is implicit.
2066          */
2067         cbs->credit_hi = offload->hicredit;
2068         cbs->credit_lo = abs(offload->locredit);
2069         /* User space is in kbits/sec, hardware in bytes/sec */
2070         cbs->idle_slope = offload->idleslope * BYTES_PER_KBIT;
2071         cbs->send_slope = abs(offload->sendslope * BYTES_PER_KBIT);
2072         /* Convert the negative values from 64-bit 2's complement
2073          * to 32-bit 2's complement (for the case of 0x80000000 whose
2074          * negative is still negative).
2075          */
2076         cbs->credit_lo &= GENMASK_ULL(31, 0);
2077         cbs->send_slope &= GENMASK_ULL(31, 0);
2078
2079         return sja1105_dynamic_config_write(priv, BLK_IDX_CBS, index, cbs,
2080                                             true);
2081 }
2082
2083 static int sja1105_reload_cbs(struct sja1105_private *priv)
2084 {
2085         int rc = 0, i;
2086
2087         /* The credit based shapers are only allocated if
2088          * CONFIG_NET_SCH_CBS is enabled.
2089          */
2090         if (!priv->cbs)
2091                 return 0;
2092
2093         for (i = 0; i < priv->info->num_cbs_shapers; i++) {
2094                 struct sja1105_cbs_entry *cbs = &priv->cbs[i];
2095
2096                 if (!cbs->idle_slope && !cbs->send_slope)
2097                         continue;
2098
2099                 rc = sja1105_dynamic_config_write(priv, BLK_IDX_CBS, i, cbs,
2100                                                   true);
2101                 if (rc)
2102                         break;
2103         }
2104
2105         return rc;
2106 }
2107
2108 static const char * const sja1105_reset_reasons[] = {
2109         [SJA1105_VLAN_FILTERING] = "VLAN filtering",
2110         [SJA1105_RX_HWTSTAMPING] = "RX timestamping",
2111         [SJA1105_AGEING_TIME] = "Ageing time",
2112         [SJA1105_SCHEDULING] = "Time-aware scheduling",
2113         [SJA1105_BEST_EFFORT_POLICING] = "Best-effort policing",
2114         [SJA1105_VIRTUAL_LINKS] = "Virtual links",
2115 };
2116
2117 /* For situations where we need to change a setting at runtime that is only
2118  * available through the static configuration, resetting the switch in order
2119  * to upload the new static config is unavoidable. Back up the settings we
2120  * modify at runtime (currently only MAC) and restore them after uploading,
2121  * such that this operation is relatively seamless.
2122  */
2123 int sja1105_static_config_reload(struct sja1105_private *priv,
2124                                  enum sja1105_reset_reason reason)
2125 {
2126         struct ptp_system_timestamp ptp_sts_before;
2127         struct ptp_system_timestamp ptp_sts_after;
2128         int speed_mbps[SJA1105_MAX_NUM_PORTS];
2129         u16 bmcr[SJA1105_MAX_NUM_PORTS] = {0};
2130         struct sja1105_mac_config_entry *mac;
2131         struct dsa_switch *ds = priv->ds;
2132         s64 t1, t2, t3, t4;
2133         s64 t12, t34;
2134         int rc, i;
2135         s64 now;
2136
2137         mutex_lock(&priv->mgmt_lock);
2138
2139         mac = priv->static_config.tables[BLK_IDX_MAC_CONFIG].entries;
2140
2141         /* Back up the dynamic link speed changed by sja1105_adjust_port_config
2142          * in order to temporarily restore it to SJA1105_SPEED_AUTO - which the
2143          * switch wants to see in the static config in order to allow us to
2144          * change it through the dynamic interface later.
2145          */
2146         for (i = 0; i < ds->num_ports; i++) {
2147                 u32 reg_addr = mdiobus_c45_addr(MDIO_MMD_VEND2, MDIO_CTRL1);
2148
2149                 speed_mbps[i] = sja1105_port_speed_to_ethtool(priv,
2150                                                               mac[i].speed);
2151                 mac[i].speed = priv->info->port_speed[SJA1105_SPEED_AUTO];
2152
2153                 if (priv->xpcs[i])
2154                         bmcr[i] = mdiobus_read(priv->mdio_pcs, i, reg_addr);
2155         }
2156
2157         /* No PTP operations can run right now */
2158         mutex_lock(&priv->ptp_data.lock);
2159
2160         rc = __sja1105_ptp_gettimex(ds, &now, &ptp_sts_before);
2161         if (rc < 0) {
2162                 mutex_unlock(&priv->ptp_data.lock);
2163                 goto out;
2164         }
2165
2166         /* Reset switch and send updated static configuration */
2167         rc = sja1105_static_config_upload(priv);
2168         if (rc < 0) {
2169                 mutex_unlock(&priv->ptp_data.lock);
2170                 goto out;
2171         }
2172
2173         rc = __sja1105_ptp_settime(ds, 0, &ptp_sts_after);
2174         if (rc < 0) {
2175                 mutex_unlock(&priv->ptp_data.lock);
2176                 goto out;
2177         }
2178
2179         t1 = timespec64_to_ns(&ptp_sts_before.pre_ts);
2180         t2 = timespec64_to_ns(&ptp_sts_before.post_ts);
2181         t3 = timespec64_to_ns(&ptp_sts_after.pre_ts);
2182         t4 = timespec64_to_ns(&ptp_sts_after.post_ts);
2183         /* Mid point, corresponds to pre-reset PTPCLKVAL */
2184         t12 = t1 + (t2 - t1) / 2;
2185         /* Mid point, corresponds to post-reset PTPCLKVAL, aka 0 */
2186         t34 = t3 + (t4 - t3) / 2;
2187         /* Advance PTPCLKVAL by the time it took since its readout */
2188         now += (t34 - t12);
2189
2190         __sja1105_ptp_adjtime(ds, now);
2191
2192         mutex_unlock(&priv->ptp_data.lock);
2193
2194         dev_info(priv->ds->dev,
2195                  "Reset switch and programmed static config. Reason: %s\n",
2196                  sja1105_reset_reasons[reason]);
2197
2198         /* Configure the CGU (PLLs) for MII and RMII PHYs.
2199          * For these interfaces there is no dynamic configuration
2200          * needed, since PLLs have same settings at all speeds.
2201          */
2202         if (priv->info->clocking_setup) {
2203                 rc = priv->info->clocking_setup(priv);
2204                 if (rc < 0)
2205                         goto out;
2206         }
2207
2208         for (i = 0; i < ds->num_ports; i++) {
2209                 struct dw_xpcs *xpcs = priv->xpcs[i];
2210                 unsigned int mode;
2211
2212                 rc = sja1105_adjust_port_config(priv, i, speed_mbps[i]);
2213                 if (rc < 0)
2214                         goto out;
2215
2216                 if (!xpcs)
2217                         continue;
2218
2219                 if (bmcr[i] & BMCR_ANENABLE)
2220                         mode = MLO_AN_INBAND;
2221                 else if (priv->fixed_link[i])
2222                         mode = MLO_AN_FIXED;
2223                 else
2224                         mode = MLO_AN_PHY;
2225
2226                 rc = xpcs_do_config(xpcs, priv->phy_mode[i], mode);
2227                 if (rc < 0)
2228                         goto out;
2229
2230                 if (!phylink_autoneg_inband(mode)) {
2231                         int speed = SPEED_UNKNOWN;
2232
2233                         if (priv->phy_mode[i] == PHY_INTERFACE_MODE_2500BASEX)
2234                                 speed = SPEED_2500;
2235                         else if (bmcr[i] & BMCR_SPEED1000)
2236                                 speed = SPEED_1000;
2237                         else if (bmcr[i] & BMCR_SPEED100)
2238                                 speed = SPEED_100;
2239                         else
2240                                 speed = SPEED_10;
2241
2242                         xpcs_link_up(&xpcs->pcs, mode, priv->phy_mode[i],
2243                                      speed, DUPLEX_FULL);
2244                 }
2245         }
2246
2247         rc = sja1105_reload_cbs(priv);
2248         if (rc < 0)
2249                 goto out;
2250 out:
2251         mutex_unlock(&priv->mgmt_lock);
2252
2253         return rc;
2254 }
2255
2256 static enum dsa_tag_protocol
2257 sja1105_get_tag_protocol(struct dsa_switch *ds, int port,
2258                          enum dsa_tag_protocol mp)
2259 {
2260         struct sja1105_private *priv = ds->priv;
2261
2262         return priv->info->tag_proto;
2263 }
2264
2265 /* The TPID setting belongs to the General Parameters table,
2266  * which can only be partially reconfigured at runtime (and not the TPID).
2267  * So a switch reset is required.
2268  */
2269 int sja1105_vlan_filtering(struct dsa_switch *ds, int port, bool enabled,
2270                            struct netlink_ext_ack *extack)
2271 {
2272         struct sja1105_l2_lookup_params_entry *l2_lookup_params;
2273         struct sja1105_general_params_entry *general_params;
2274         struct sja1105_private *priv = ds->priv;
2275         struct sja1105_table *table;
2276         struct sja1105_rule *rule;
2277         u16 tpid, tpid2;
2278         int rc;
2279
2280         list_for_each_entry(rule, &priv->flow_block.rules, list) {
2281                 if (rule->type == SJA1105_RULE_VL) {
2282                         NL_SET_ERR_MSG_MOD(extack,
2283                                            "Cannot change VLAN filtering with active VL rules");
2284                         return -EBUSY;
2285                 }
2286         }
2287
2288         if (enabled) {
2289                 /* Enable VLAN filtering. */
2290                 tpid  = ETH_P_8021Q;
2291                 tpid2 = ETH_P_8021AD;
2292         } else {
2293                 /* Disable VLAN filtering. */
2294                 tpid  = ETH_P_SJA1105;
2295                 tpid2 = ETH_P_SJA1105;
2296         }
2297
2298         if (priv->vlan_aware == enabled)
2299                 return 0;
2300
2301         priv->vlan_aware = enabled;
2302
2303         table = &priv->static_config.tables[BLK_IDX_GENERAL_PARAMS];
2304         general_params = table->entries;
2305         /* EtherType used to identify inner tagged (C-tag) VLAN traffic */
2306         general_params->tpid = tpid;
2307         /* EtherType used to identify outer tagged (S-tag) VLAN traffic */
2308         general_params->tpid2 = tpid2;
2309         /* When VLAN filtering is on, we need to at least be able to
2310          * decode management traffic through the "backup plan".
2311          */
2312         general_params->incl_srcpt1 = enabled;
2313         general_params->incl_srcpt0 = enabled;
2314
2315         /* VLAN filtering => independent VLAN learning.
2316          * No VLAN filtering (or best effort) => shared VLAN learning.
2317          *
2318          * In shared VLAN learning mode, untagged traffic still gets
2319          * pvid-tagged, and the FDB table gets populated with entries
2320          * containing the "real" (pvid or from VLAN tag) VLAN ID.
2321          * However the switch performs a masked L2 lookup in the FDB,
2322          * effectively only looking up a frame's DMAC (and not VID) for the
2323          * forwarding decision.
2324          *
2325          * This is extremely convenient for us, because in modes with
2326          * vlan_filtering=0, dsa_8021q actually installs unique pvid's into
2327          * each front panel port. This is good for identification but breaks
2328          * learning badly - the VID of the learnt FDB entry is unique, aka
2329          * no frames coming from any other port are going to have it. So
2330          * for forwarding purposes, this is as though learning was broken
2331          * (all frames get flooded).
2332          */
2333         table = &priv->static_config.tables[BLK_IDX_L2_LOOKUP_PARAMS];
2334         l2_lookup_params = table->entries;
2335         l2_lookup_params->shared_learn = !priv->vlan_aware;
2336
2337         for (port = 0; port < ds->num_ports; port++) {
2338                 if (dsa_is_unused_port(ds, port))
2339                         continue;
2340
2341                 rc = sja1105_commit_pvid(ds, port);
2342                 if (rc)
2343                         return rc;
2344         }
2345
2346         rc = sja1105_static_config_reload(priv, SJA1105_VLAN_FILTERING);
2347         if (rc)
2348                 NL_SET_ERR_MSG_MOD(extack, "Failed to change VLAN Ethertype");
2349
2350         return rc;
2351 }
2352
2353 static int sja1105_vlan_add(struct sja1105_private *priv, int port, u16 vid,
2354                             u16 flags, bool allowed_ingress)
2355 {
2356         struct sja1105_vlan_lookup_entry *vlan;
2357         struct sja1105_table *table;
2358         int match, rc;
2359
2360         table = &priv->static_config.tables[BLK_IDX_VLAN_LOOKUP];
2361
2362         match = sja1105_is_vlan_configured(priv, vid);
2363         if (match < 0) {
2364                 rc = sja1105_table_resize(table, table->entry_count + 1);
2365                 if (rc)
2366                         return rc;
2367                 match = table->entry_count - 1;
2368         }
2369
2370         /* Assign pointer after the resize (it's new memory) */
2371         vlan = table->entries;
2372
2373         vlan[match].type_entry = SJA1110_VLAN_D_TAG;
2374         vlan[match].vlanid = vid;
2375         vlan[match].vlan_bc |= BIT(port);
2376
2377         if (allowed_ingress)
2378                 vlan[match].vmemb_port |= BIT(port);
2379         else
2380                 vlan[match].vmemb_port &= ~BIT(port);
2381
2382         if (flags & BRIDGE_VLAN_INFO_UNTAGGED)
2383                 vlan[match].tag_port &= ~BIT(port);
2384         else
2385                 vlan[match].tag_port |= BIT(port);
2386
2387         return sja1105_dynamic_config_write(priv, BLK_IDX_VLAN_LOOKUP, vid,
2388                                             &vlan[match], true);
2389 }
2390
2391 static int sja1105_vlan_del(struct sja1105_private *priv, int port, u16 vid)
2392 {
2393         struct sja1105_vlan_lookup_entry *vlan;
2394         struct sja1105_table *table;
2395         bool keep = true;
2396         int match, rc;
2397
2398         table = &priv->static_config.tables[BLK_IDX_VLAN_LOOKUP];
2399
2400         match = sja1105_is_vlan_configured(priv, vid);
2401         /* Can't delete a missing entry. */
2402         if (match < 0)
2403                 return 0;
2404
2405         /* Assign pointer after the resize (it's new memory) */
2406         vlan = table->entries;
2407
2408         vlan[match].vlanid = vid;
2409         vlan[match].vlan_bc &= ~BIT(port);
2410         vlan[match].vmemb_port &= ~BIT(port);
2411         /* Also unset tag_port, just so we don't have a confusing bitmap
2412          * (no practical purpose).
2413          */
2414         vlan[match].tag_port &= ~BIT(port);
2415
2416         /* If there's no port left as member of this VLAN,
2417          * it's time for it to go.
2418          */
2419         if (!vlan[match].vmemb_port)
2420                 keep = false;
2421
2422         rc = sja1105_dynamic_config_write(priv, BLK_IDX_VLAN_LOOKUP, vid,
2423                                           &vlan[match], keep);
2424         if (rc < 0)
2425                 return rc;
2426
2427         if (!keep)
2428                 return sja1105_table_delete_entry(table, match);
2429
2430         return 0;
2431 }
2432
2433 static int sja1105_bridge_vlan_add(struct dsa_switch *ds, int port,
2434                                    const struct switchdev_obj_port_vlan *vlan,
2435                                    struct netlink_ext_ack *extack)
2436 {
2437         struct sja1105_private *priv = ds->priv;
2438         u16 flags = vlan->flags;
2439         int rc;
2440
2441         /* Be sure to deny alterations to the configuration done by tag_8021q.
2442          */
2443         if (vid_is_dsa_8021q(vlan->vid)) {
2444                 NL_SET_ERR_MSG_MOD(extack,
2445                                    "Range 1024-3071 reserved for dsa_8021q operation");
2446                 return -EBUSY;
2447         }
2448
2449         /* Always install bridge VLANs as egress-tagged on CPU and DSA ports */
2450         if (dsa_is_cpu_port(ds, port) || dsa_is_dsa_port(ds, port))
2451                 flags = 0;
2452
2453         rc = sja1105_vlan_add(priv, port, vlan->vid, flags, true);
2454         if (rc)
2455                 return rc;
2456
2457         if (vlan->flags & BRIDGE_VLAN_INFO_PVID)
2458                 priv->bridge_pvid[port] = vlan->vid;
2459
2460         return sja1105_commit_pvid(ds, port);
2461 }
2462
2463 static int sja1105_bridge_vlan_del(struct dsa_switch *ds, int port,
2464                                    const struct switchdev_obj_port_vlan *vlan)
2465 {
2466         struct sja1105_private *priv = ds->priv;
2467         int rc;
2468
2469         rc = sja1105_vlan_del(priv, port, vlan->vid);
2470         if (rc)
2471                 return rc;
2472
2473         /* In case the pvid was deleted, make sure that untagged packets will
2474          * be dropped.
2475          */
2476         return sja1105_commit_pvid(ds, port);
2477 }
2478
2479 static int sja1105_dsa_8021q_vlan_add(struct dsa_switch *ds, int port, u16 vid,
2480                                       u16 flags)
2481 {
2482         struct sja1105_private *priv = ds->priv;
2483         bool allowed_ingress = true;
2484         int rc;
2485
2486         /* Prevent attackers from trying to inject a DSA tag from
2487          * the outside world.
2488          */
2489         if (dsa_is_user_port(ds, port))
2490                 allowed_ingress = false;
2491
2492         rc = sja1105_vlan_add(priv, port, vid, flags, allowed_ingress);
2493         if (rc)
2494                 return rc;
2495
2496         if (flags & BRIDGE_VLAN_INFO_PVID)
2497                 priv->tag_8021q_pvid[port] = vid;
2498
2499         return sja1105_commit_pvid(ds, port);
2500 }
2501
2502 static int sja1105_dsa_8021q_vlan_del(struct dsa_switch *ds, int port, u16 vid)
2503 {
2504         struct sja1105_private *priv = ds->priv;
2505
2506         return sja1105_vlan_del(priv, port, vid);
2507 }
2508
2509 static int sja1105_prechangeupper(struct dsa_switch *ds, int port,
2510                                   struct netdev_notifier_changeupper_info *info)
2511 {
2512         struct netlink_ext_ack *extack = info->info.extack;
2513         struct net_device *upper = info->upper_dev;
2514         struct dsa_switch_tree *dst = ds->dst;
2515         struct dsa_port *dp;
2516
2517         if (is_vlan_dev(upper)) {
2518                 NL_SET_ERR_MSG_MOD(extack, "8021q uppers are not supported");
2519                 return -EBUSY;
2520         }
2521
2522         if (netif_is_bridge_master(upper)) {
2523                 list_for_each_entry(dp, &dst->ports, list) {
2524                         if (dp->bridge_dev && dp->bridge_dev != upper &&
2525                             br_vlan_enabled(dp->bridge_dev)) {
2526                                 NL_SET_ERR_MSG_MOD(extack,
2527                                                    "Only one VLAN-aware bridge is supported");
2528                                 return -EBUSY;
2529                         }
2530                 }
2531         }
2532
2533         return 0;
2534 }
2535
2536 static void sja1105_port_disable(struct dsa_switch *ds, int port)
2537 {
2538         struct sja1105_private *priv = ds->priv;
2539         struct sja1105_port *sp = &priv->ports[port];
2540
2541         if (!dsa_is_user_port(ds, port))
2542                 return;
2543
2544         kthread_cancel_work_sync(&sp->xmit_work);
2545         skb_queue_purge(&sp->xmit_queue);
2546 }
2547
2548 static int sja1105_mgmt_xmit(struct dsa_switch *ds, int port, int slot,
2549                              struct sk_buff *skb, bool takets)
2550 {
2551         struct sja1105_mgmt_entry mgmt_route = {0};
2552         struct sja1105_private *priv = ds->priv;
2553         struct ethhdr *hdr;
2554         int timeout = 10;
2555         int rc;
2556
2557         hdr = eth_hdr(skb);
2558
2559         mgmt_route.macaddr = ether_addr_to_u64(hdr->h_dest);
2560         mgmt_route.destports = BIT(port);
2561         mgmt_route.enfport = 1;
2562         mgmt_route.tsreg = 0;
2563         mgmt_route.takets = takets;
2564
2565         rc = sja1105_dynamic_config_write(priv, BLK_IDX_MGMT_ROUTE,
2566                                           slot, &mgmt_route, true);
2567         if (rc < 0) {
2568                 kfree_skb(skb);
2569                 return rc;
2570         }
2571
2572         /* Transfer skb to the host port. */
2573         dsa_enqueue_skb(skb, dsa_to_port(ds, port)->slave);
2574
2575         /* Wait until the switch has processed the frame */
2576         do {
2577                 rc = sja1105_dynamic_config_read(priv, BLK_IDX_MGMT_ROUTE,
2578                                                  slot, &mgmt_route);
2579                 if (rc < 0) {
2580                         dev_err_ratelimited(priv->ds->dev,
2581                                             "failed to poll for mgmt route\n");
2582                         continue;
2583                 }
2584
2585                 /* UM10944: The ENFPORT flag of the respective entry is
2586                  * cleared when a match is found. The host can use this
2587                  * flag as an acknowledgment.
2588                  */
2589                 cpu_relax();
2590         } while (mgmt_route.enfport && --timeout);
2591
2592         if (!timeout) {
2593                 /* Clean up the management route so that a follow-up
2594                  * frame may not match on it by mistake.
2595                  * This is only hardware supported on P/Q/R/S - on E/T it is
2596                  * a no-op and we are silently discarding the -EOPNOTSUPP.
2597                  */
2598                 sja1105_dynamic_config_write(priv, BLK_IDX_MGMT_ROUTE,
2599                                              slot, &mgmt_route, false);
2600                 dev_err_ratelimited(priv->ds->dev, "xmit timed out\n");
2601         }
2602
2603         return NETDEV_TX_OK;
2604 }
2605
2606 #define work_to_port(work) \
2607                 container_of((work), struct sja1105_port, xmit_work)
2608 #define tagger_to_sja1105(t) \
2609                 container_of((t), struct sja1105_private, tagger_data)
2610
2611 /* Deferred work is unfortunately necessary because setting up the management
2612  * route cannot be done from atomit context (SPI transfer takes a sleepable
2613  * lock on the bus)
2614  */
2615 static void sja1105_port_deferred_xmit(struct kthread_work *work)
2616 {
2617         struct sja1105_port *sp = work_to_port(work);
2618         struct sja1105_tagger_data *tagger_data = sp->data;
2619         struct sja1105_private *priv = tagger_to_sja1105(tagger_data);
2620         int port = sp - priv->ports;
2621         struct sk_buff *skb;
2622
2623         while ((skb = skb_dequeue(&sp->xmit_queue)) != NULL) {
2624                 struct sk_buff *clone = SJA1105_SKB_CB(skb)->clone;
2625
2626                 mutex_lock(&priv->mgmt_lock);
2627
2628                 sja1105_mgmt_xmit(priv->ds, port, 0, skb, !!clone);
2629
2630                 /* The clone, if there, was made by dsa_skb_tx_timestamp */
2631                 if (clone)
2632                         sja1105_ptp_txtstamp_skb(priv->ds, port, clone);
2633
2634                 mutex_unlock(&priv->mgmt_lock);
2635         }
2636 }
2637
2638 /* The MAXAGE setting belongs to the L2 Forwarding Parameters table,
2639  * which cannot be reconfigured at runtime. So a switch reset is required.
2640  */
2641 static int sja1105_set_ageing_time(struct dsa_switch *ds,
2642                                    unsigned int ageing_time)
2643 {
2644         struct sja1105_l2_lookup_params_entry *l2_lookup_params;
2645         struct sja1105_private *priv = ds->priv;
2646         struct sja1105_table *table;
2647         unsigned int maxage;
2648
2649         table = &priv->static_config.tables[BLK_IDX_L2_LOOKUP_PARAMS];
2650         l2_lookup_params = table->entries;
2651
2652         maxage = SJA1105_AGEING_TIME_MS(ageing_time);
2653
2654         if (l2_lookup_params->maxage == maxage)
2655                 return 0;
2656
2657         l2_lookup_params->maxage = maxage;
2658
2659         return sja1105_static_config_reload(priv, SJA1105_AGEING_TIME);
2660 }
2661
2662 static int sja1105_change_mtu(struct dsa_switch *ds, int port, int new_mtu)
2663 {
2664         struct sja1105_l2_policing_entry *policing;
2665         struct sja1105_private *priv = ds->priv;
2666
2667         new_mtu += VLAN_ETH_HLEN + ETH_FCS_LEN;
2668
2669         if (dsa_is_cpu_port(ds, port) || dsa_is_dsa_port(ds, port))
2670                 new_mtu += VLAN_HLEN;
2671
2672         policing = priv->static_config.tables[BLK_IDX_L2_POLICING].entries;
2673
2674         if (policing[port].maxlen == new_mtu)
2675                 return 0;
2676
2677         policing[port].maxlen = new_mtu;
2678
2679         return sja1105_static_config_reload(priv, SJA1105_BEST_EFFORT_POLICING);
2680 }
2681
2682 static int sja1105_get_max_mtu(struct dsa_switch *ds, int port)
2683 {
2684         return 2043 - VLAN_ETH_HLEN - ETH_FCS_LEN;
2685 }
2686
2687 static int sja1105_port_setup_tc(struct dsa_switch *ds, int port,
2688                                  enum tc_setup_type type,
2689                                  void *type_data)
2690 {
2691         switch (type) {
2692         case TC_SETUP_QDISC_TAPRIO:
2693                 return sja1105_setup_tc_taprio(ds, port, type_data);
2694         case TC_SETUP_QDISC_CBS:
2695                 return sja1105_setup_tc_cbs(ds, port, type_data);
2696         default:
2697                 return -EOPNOTSUPP;
2698         }
2699 }
2700
2701 /* We have a single mirror (@to) port, but can configure ingress and egress
2702  * mirroring on all other (@from) ports.
2703  * We need to allow mirroring rules only as long as the @to port is always the
2704  * same, and we need to unset the @to port from mirr_port only when there is no
2705  * mirroring rule that references it.
2706  */
2707 static int sja1105_mirror_apply(struct sja1105_private *priv, int from, int to,
2708                                 bool ingress, bool enabled)
2709 {
2710         struct sja1105_general_params_entry *general_params;
2711         struct sja1105_mac_config_entry *mac;
2712         struct dsa_switch *ds = priv->ds;
2713         struct sja1105_table *table;
2714         bool already_enabled;
2715         u64 new_mirr_port;
2716         int rc;
2717
2718         table = &priv->static_config.tables[BLK_IDX_GENERAL_PARAMS];
2719         general_params = table->entries;
2720
2721         mac = priv->static_config.tables[BLK_IDX_MAC_CONFIG].entries;
2722
2723         already_enabled = (general_params->mirr_port != ds->num_ports);
2724         if (already_enabled && enabled && general_params->mirr_port != to) {
2725                 dev_err(priv->ds->dev,
2726                         "Delete mirroring rules towards port %llu first\n",
2727                         general_params->mirr_port);
2728                 return -EBUSY;
2729         }
2730
2731         new_mirr_port = to;
2732         if (!enabled) {
2733                 bool keep = false;
2734                 int port;
2735
2736                 /* Anybody still referencing mirr_port? */
2737                 for (port = 0; port < ds->num_ports; port++) {
2738                         if (mac[port].ing_mirr || mac[port].egr_mirr) {
2739                                 keep = true;
2740                                 break;
2741                         }
2742                 }
2743                 /* Unset already_enabled for next time */
2744                 if (!keep)
2745                         new_mirr_port = ds->num_ports;
2746         }
2747         if (new_mirr_port != general_params->mirr_port) {
2748                 general_params->mirr_port = new_mirr_port;
2749
2750                 rc = sja1105_dynamic_config_write(priv, BLK_IDX_GENERAL_PARAMS,
2751                                                   0, general_params, true);
2752                 if (rc < 0)
2753                         return rc;
2754         }
2755
2756         if (ingress)
2757                 mac[from].ing_mirr = enabled;
2758         else
2759                 mac[from].egr_mirr = enabled;
2760
2761         return sja1105_dynamic_config_write(priv, BLK_IDX_MAC_CONFIG, from,
2762                                             &mac[from], true);
2763 }
2764
2765 static int sja1105_mirror_add(struct dsa_switch *ds, int port,
2766                               struct dsa_mall_mirror_tc_entry *mirror,
2767                               bool ingress)
2768 {
2769         return sja1105_mirror_apply(ds->priv, port, mirror->to_local_port,
2770                                     ingress, true);
2771 }
2772
2773 static void sja1105_mirror_del(struct dsa_switch *ds, int port,
2774                                struct dsa_mall_mirror_tc_entry *mirror)
2775 {
2776         sja1105_mirror_apply(ds->priv, port, mirror->to_local_port,
2777                              mirror->ingress, false);
2778 }
2779
2780 static int sja1105_port_policer_add(struct dsa_switch *ds, int port,
2781                                     struct dsa_mall_policer_tc_entry *policer)
2782 {
2783         struct sja1105_l2_policing_entry *policing;
2784         struct sja1105_private *priv = ds->priv;
2785
2786         policing = priv->static_config.tables[BLK_IDX_L2_POLICING].entries;
2787
2788         /* In hardware, every 8 microseconds the credit level is incremented by
2789          * the value of RATE bytes divided by 64, up to a maximum of SMAX
2790          * bytes.
2791          */
2792         policing[port].rate = div_u64(512 * policer->rate_bytes_per_sec,
2793                                       1000000);
2794         policing[port].smax = policer->burst;
2795
2796         return sja1105_static_config_reload(priv, SJA1105_BEST_EFFORT_POLICING);
2797 }
2798
2799 static void sja1105_port_policer_del(struct dsa_switch *ds, int port)
2800 {
2801         struct sja1105_l2_policing_entry *policing;
2802         struct sja1105_private *priv = ds->priv;
2803
2804         policing = priv->static_config.tables[BLK_IDX_L2_POLICING].entries;
2805
2806         policing[port].rate = SJA1105_RATE_MBPS(1000);
2807         policing[port].smax = 65535;
2808
2809         sja1105_static_config_reload(priv, SJA1105_BEST_EFFORT_POLICING);
2810 }
2811
2812 static int sja1105_port_set_learning(struct sja1105_private *priv, int port,
2813                                      bool enabled)
2814 {
2815         struct sja1105_mac_config_entry *mac;
2816
2817         mac = priv->static_config.tables[BLK_IDX_MAC_CONFIG].entries;
2818
2819         mac[port].dyn_learn = enabled;
2820
2821         return sja1105_dynamic_config_write(priv, BLK_IDX_MAC_CONFIG, port,
2822                                             &mac[port], true);
2823 }
2824
2825 static int sja1105_port_ucast_bcast_flood(struct sja1105_private *priv, int to,
2826                                           struct switchdev_brport_flags flags)
2827 {
2828         if (flags.mask & BR_FLOOD) {
2829                 if (flags.val & BR_FLOOD)
2830                         priv->ucast_egress_floods |= BIT(to);
2831                 else
2832                         priv->ucast_egress_floods &= ~BIT(to);
2833         }
2834
2835         if (flags.mask & BR_BCAST_FLOOD) {
2836                 if (flags.val & BR_BCAST_FLOOD)
2837                         priv->bcast_egress_floods |= BIT(to);
2838                 else
2839                         priv->bcast_egress_floods &= ~BIT(to);
2840         }
2841
2842         return sja1105_manage_flood_domains(priv);
2843 }
2844
2845 static int sja1105_port_mcast_flood(struct sja1105_private *priv, int to,
2846                                     struct switchdev_brport_flags flags,
2847                                     struct netlink_ext_ack *extack)
2848 {
2849         struct sja1105_l2_lookup_entry *l2_lookup;
2850         struct sja1105_table *table;
2851         int match;
2852
2853         table = &priv->static_config.tables[BLK_IDX_L2_LOOKUP];
2854         l2_lookup = table->entries;
2855
2856         for (match = 0; match < table->entry_count; match++)
2857                 if (l2_lookup[match].macaddr == SJA1105_UNKNOWN_MULTICAST &&
2858                     l2_lookup[match].mask_macaddr == SJA1105_UNKNOWN_MULTICAST)
2859                         break;
2860
2861         if (match == table->entry_count) {
2862                 NL_SET_ERR_MSG_MOD(extack,
2863                                    "Could not find FDB entry for unknown multicast");
2864                 return -ENOSPC;
2865         }
2866
2867         if (flags.val & BR_MCAST_FLOOD)
2868                 l2_lookup[match].destports |= BIT(to);
2869         else
2870                 l2_lookup[match].destports &= ~BIT(to);
2871
2872         return sja1105_dynamic_config_write(priv, BLK_IDX_L2_LOOKUP,
2873                                             l2_lookup[match].index,
2874                                             &l2_lookup[match],
2875                                             true);
2876 }
2877
2878 static int sja1105_port_pre_bridge_flags(struct dsa_switch *ds, int port,
2879                                          struct switchdev_brport_flags flags,
2880                                          struct netlink_ext_ack *extack)
2881 {
2882         struct sja1105_private *priv = ds->priv;
2883
2884         if (flags.mask & ~(BR_LEARNING | BR_FLOOD | BR_MCAST_FLOOD |
2885                            BR_BCAST_FLOOD))
2886                 return -EINVAL;
2887
2888         if (flags.mask & (BR_FLOOD | BR_MCAST_FLOOD) &&
2889             !priv->info->can_limit_mcast_flood) {
2890                 bool multicast = !!(flags.val & BR_MCAST_FLOOD);
2891                 bool unicast = !!(flags.val & BR_FLOOD);
2892
2893                 if (unicast != multicast) {
2894                         NL_SET_ERR_MSG_MOD(extack,
2895                                            "This chip cannot configure multicast flooding independently of unicast");
2896                         return -EINVAL;
2897                 }
2898         }
2899
2900         return 0;
2901 }
2902
2903 static int sja1105_port_bridge_flags(struct dsa_switch *ds, int port,
2904                                      struct switchdev_brport_flags flags,
2905                                      struct netlink_ext_ack *extack)
2906 {
2907         struct sja1105_private *priv = ds->priv;
2908         int rc;
2909
2910         if (flags.mask & BR_LEARNING) {
2911                 bool learn_ena = !!(flags.val & BR_LEARNING);
2912
2913                 rc = sja1105_port_set_learning(priv, port, learn_ena);
2914                 if (rc)
2915                         return rc;
2916         }
2917
2918         if (flags.mask & (BR_FLOOD | BR_BCAST_FLOOD)) {
2919                 rc = sja1105_port_ucast_bcast_flood(priv, port, flags);
2920                 if (rc)
2921                         return rc;
2922         }
2923
2924         /* For chips that can't offload BR_MCAST_FLOOD independently, there
2925          * is nothing to do here, we ensured the configuration is in sync by
2926          * offloading BR_FLOOD.
2927          */
2928         if (flags.mask & BR_MCAST_FLOOD && priv->info->can_limit_mcast_flood) {
2929                 rc = sja1105_port_mcast_flood(priv, port, flags,
2930                                               extack);
2931                 if (rc)
2932                         return rc;
2933         }
2934
2935         return 0;
2936 }
2937
2938 static void sja1105_teardown_ports(struct sja1105_private *priv)
2939 {
2940         struct dsa_switch *ds = priv->ds;
2941         int port;
2942
2943         for (port = 0; port < ds->num_ports; port++) {
2944                 struct sja1105_port *sp = &priv->ports[port];
2945
2946                 if (sp->xmit_worker)
2947                         kthread_destroy_worker(sp->xmit_worker);
2948         }
2949 }
2950
2951 static int sja1105_setup_ports(struct sja1105_private *priv)
2952 {
2953         struct sja1105_tagger_data *tagger_data = &priv->tagger_data;
2954         struct dsa_switch *ds = priv->ds;
2955         int port, rc;
2956
2957         /* Connections between dsa_port and sja1105_port */
2958         for (port = 0; port < ds->num_ports; port++) {
2959                 struct sja1105_port *sp = &priv->ports[port];
2960                 struct dsa_port *dp = dsa_to_port(ds, port);
2961                 struct kthread_worker *worker;
2962                 struct net_device *slave;
2963
2964                 if (!dsa_port_is_user(dp))
2965                         continue;
2966
2967                 dp->priv = sp;
2968                 sp->dp = dp;
2969                 sp->data = tagger_data;
2970                 slave = dp->slave;
2971                 kthread_init_work(&sp->xmit_work, sja1105_port_deferred_xmit);
2972                 worker = kthread_create_worker(0, "%s_xmit", slave->name);
2973                 if (IS_ERR(worker)) {
2974                         rc = PTR_ERR(worker);
2975                         dev_err(ds->dev,
2976                                 "failed to create deferred xmit thread: %d\n",
2977                                 rc);
2978                         goto out_destroy_workers;
2979                 }
2980                 sp->xmit_worker = worker;
2981                 skb_queue_head_init(&sp->xmit_queue);
2982         }
2983
2984         return 0;
2985
2986 out_destroy_workers:
2987         sja1105_teardown_ports(priv);
2988         return rc;
2989 }
2990
2991 /* The programming model for the SJA1105 switch is "all-at-once" via static
2992  * configuration tables. Some of these can be dynamically modified at runtime,
2993  * but not the xMII mode parameters table.
2994  * Furthermode, some PHYs may not have crystals for generating their clocks
2995  * (e.g. RMII). Instead, their 50MHz clock is supplied via the SJA1105 port's
2996  * ref_clk pin. So port clocking needs to be initialized early, before
2997  * connecting to PHYs is attempted, otherwise they won't respond through MDIO.
2998  * Setting correct PHY link speed does not matter now.
2999  * But dsa_slave_phy_setup is called later than sja1105_setup, so the PHY
3000  * bindings are not yet parsed by DSA core. We need to parse early so that we
3001  * can populate the xMII mode parameters table.
3002  */
3003 static int sja1105_setup(struct dsa_switch *ds)
3004 {
3005         struct sja1105_private *priv = ds->priv;
3006         int rc;
3007
3008         if (priv->info->disable_microcontroller) {
3009                 rc = priv->info->disable_microcontroller(priv);
3010                 if (rc < 0) {
3011                         dev_err(ds->dev,
3012                                 "Failed to disable microcontroller: %pe\n",
3013                                 ERR_PTR(rc));
3014                         return rc;
3015                 }
3016         }
3017
3018         /* Create and send configuration down to device */
3019         rc = sja1105_static_config_load(priv);
3020         if (rc < 0) {
3021                 dev_err(ds->dev, "Failed to load static config: %d\n", rc);
3022                 return rc;
3023         }
3024
3025         /* Configure the CGU (PHY link modes and speeds) */
3026         if (priv->info->clocking_setup) {
3027                 rc = priv->info->clocking_setup(priv);
3028                 if (rc < 0) {
3029                         dev_err(ds->dev,
3030                                 "Failed to configure MII clocking: %pe\n",
3031                                 ERR_PTR(rc));
3032                         goto out_static_config_free;
3033                 }
3034         }
3035
3036         rc = sja1105_setup_ports(priv);
3037         if (rc)
3038                 goto out_static_config_free;
3039
3040         sja1105_tas_setup(ds);
3041         sja1105_flower_setup(ds);
3042
3043         rc = sja1105_ptp_clock_register(ds);
3044         if (rc < 0) {
3045                 dev_err(ds->dev, "Failed to register PTP clock: %d\n", rc);
3046                 goto out_flower_teardown;
3047         }
3048
3049         rc = sja1105_mdiobus_register(ds);
3050         if (rc < 0) {
3051                 dev_err(ds->dev, "Failed to register MDIO bus: %pe\n",
3052                         ERR_PTR(rc));
3053                 goto out_ptp_clock_unregister;
3054         }
3055
3056         rc = sja1105_devlink_setup(ds);
3057         if (rc < 0)
3058                 goto out_mdiobus_unregister;
3059
3060         rtnl_lock();
3061         rc = dsa_tag_8021q_register(ds, htons(ETH_P_8021Q));
3062         rtnl_unlock();
3063         if (rc)
3064                 goto out_devlink_teardown;
3065
3066         /* On SJA1105, VLAN filtering per se is always enabled in hardware.
3067          * The only thing we can do to disable it is lie about what the 802.1Q
3068          * EtherType is.
3069          * So it will still try to apply VLAN filtering, but all ingress
3070          * traffic (except frames received with EtherType of ETH_P_SJA1105)
3071          * will be internally tagged with a distorted VLAN header where the
3072          * TPID is ETH_P_SJA1105, and the VLAN ID is the port pvid.
3073          */
3074         ds->vlan_filtering_is_global = true;
3075         ds->untag_bridge_pvid = true;
3076         /* tag_8021q has 3 bits for the VBID, and the value 0 is reserved */
3077         ds->num_fwd_offloading_bridges = 7;
3078
3079         /* Advertise the 8 egress queues */
3080         ds->num_tx_queues = SJA1105_NUM_TC;
3081
3082         ds->mtu_enforcement_ingress = true;
3083         ds->assisted_learning_on_cpu_port = true;
3084
3085         return 0;
3086
3087 out_devlink_teardown:
3088         sja1105_devlink_teardown(ds);
3089 out_mdiobus_unregister:
3090         sja1105_mdiobus_unregister(ds);
3091 out_ptp_clock_unregister:
3092         sja1105_ptp_clock_unregister(ds);
3093 out_flower_teardown:
3094         sja1105_flower_teardown(ds);
3095         sja1105_tas_teardown(ds);
3096         sja1105_teardown_ports(priv);
3097 out_static_config_free:
3098         sja1105_static_config_free(&priv->static_config);
3099
3100         return rc;
3101 }
3102
3103 static void sja1105_teardown(struct dsa_switch *ds)
3104 {
3105         struct sja1105_private *priv = ds->priv;
3106
3107         rtnl_lock();
3108         dsa_tag_8021q_unregister(ds);
3109         rtnl_unlock();
3110
3111         sja1105_devlink_teardown(ds);
3112         sja1105_mdiobus_unregister(ds);
3113         sja1105_ptp_clock_unregister(ds);
3114         sja1105_flower_teardown(ds);
3115         sja1105_tas_teardown(ds);
3116         sja1105_teardown_ports(priv);
3117         sja1105_static_config_free(&priv->static_config);
3118 }
3119
3120 const struct dsa_switch_ops sja1105_switch_ops = {
3121         .get_tag_protocol       = sja1105_get_tag_protocol,
3122         .setup                  = sja1105_setup,
3123         .teardown               = sja1105_teardown,
3124         .set_ageing_time        = sja1105_set_ageing_time,
3125         .port_change_mtu        = sja1105_change_mtu,
3126         .port_max_mtu           = sja1105_get_max_mtu,
3127         .phylink_validate       = sja1105_phylink_validate,
3128         .phylink_mac_config     = sja1105_mac_config,
3129         .phylink_mac_link_up    = sja1105_mac_link_up,
3130         .phylink_mac_link_down  = sja1105_mac_link_down,
3131         .get_strings            = sja1105_get_strings,
3132         .get_ethtool_stats      = sja1105_get_ethtool_stats,
3133         .get_sset_count         = sja1105_get_sset_count,
3134         .get_ts_info            = sja1105_get_ts_info,
3135         .port_disable           = sja1105_port_disable,
3136         .port_fdb_dump          = sja1105_fdb_dump,
3137         .port_fdb_add           = sja1105_fdb_add,
3138         .port_fdb_del           = sja1105_fdb_del,
3139         .port_fast_age          = sja1105_fast_age,
3140         .port_bridge_join       = sja1105_bridge_join,
3141         .port_bridge_leave      = sja1105_bridge_leave,
3142         .port_pre_bridge_flags  = sja1105_port_pre_bridge_flags,
3143         .port_bridge_flags      = sja1105_port_bridge_flags,
3144         .port_stp_state_set     = sja1105_bridge_stp_state_set,
3145         .port_vlan_filtering    = sja1105_vlan_filtering,
3146         .port_vlan_add          = sja1105_bridge_vlan_add,
3147         .port_vlan_del          = sja1105_bridge_vlan_del,
3148         .port_mdb_add           = sja1105_mdb_add,
3149         .port_mdb_del           = sja1105_mdb_del,
3150         .port_hwtstamp_get      = sja1105_hwtstamp_get,
3151         .port_hwtstamp_set      = sja1105_hwtstamp_set,
3152         .port_rxtstamp          = sja1105_port_rxtstamp,
3153         .port_txtstamp          = sja1105_port_txtstamp,
3154         .port_setup_tc          = sja1105_port_setup_tc,
3155         .port_mirror_add        = sja1105_mirror_add,
3156         .port_mirror_del        = sja1105_mirror_del,
3157         .port_policer_add       = sja1105_port_policer_add,
3158         .port_policer_del       = sja1105_port_policer_del,
3159         .cls_flower_add         = sja1105_cls_flower_add,
3160         .cls_flower_del         = sja1105_cls_flower_del,
3161         .cls_flower_stats       = sja1105_cls_flower_stats,
3162         .devlink_info_get       = sja1105_devlink_info_get,
3163         .tag_8021q_vlan_add     = sja1105_dsa_8021q_vlan_add,
3164         .tag_8021q_vlan_del     = sja1105_dsa_8021q_vlan_del,
3165         .port_prechangeupper    = sja1105_prechangeupper,
3166         .port_bridge_tx_fwd_offload = dsa_tag_8021q_bridge_tx_fwd_offload,
3167         .port_bridge_tx_fwd_unoffload = dsa_tag_8021q_bridge_tx_fwd_unoffload,
3168 };
3169 EXPORT_SYMBOL_GPL(sja1105_switch_ops);
3170
3171 static const struct of_device_id sja1105_dt_ids[];
3172
3173 static int sja1105_check_device_id(struct sja1105_private *priv)
3174 {
3175         const struct sja1105_regs *regs = priv->info->regs;
3176         u8 prod_id[SJA1105_SIZE_DEVICE_ID] = {0};
3177         struct device *dev = &priv->spidev->dev;
3178         const struct of_device_id *match;
3179         u32 device_id;
3180         u64 part_no;
3181         int rc;
3182
3183         rc = sja1105_xfer_u32(priv, SPI_READ, regs->device_id, &device_id,
3184                               NULL);
3185         if (rc < 0)
3186                 return rc;
3187
3188         rc = sja1105_xfer_buf(priv, SPI_READ, regs->prod_id, prod_id,
3189                               SJA1105_SIZE_DEVICE_ID);
3190         if (rc < 0)
3191                 return rc;
3192
3193         sja1105_unpack(prod_id, &part_no, 19, 4, SJA1105_SIZE_DEVICE_ID);
3194
3195         for (match = sja1105_dt_ids; match->compatible[0]; match++) {
3196                 const struct sja1105_info *info = match->data;
3197
3198                 /* Is what's been probed in our match table at all? */
3199                 if (info->device_id != device_id || info->part_no != part_no)
3200                         continue;
3201
3202                 /* But is it what's in the device tree? */
3203                 if (priv->info->device_id != device_id ||
3204                     priv->info->part_no != part_no) {
3205                         dev_warn(dev, "Device tree specifies chip %s but found %s, please fix it!\n",
3206                                  priv->info->name, info->name);
3207                         /* It isn't. No problem, pick that up. */
3208                         priv->info = info;
3209                 }
3210
3211                 return 0;
3212         }
3213
3214         dev_err(dev, "Unexpected {device ID, part number}: 0x%x 0x%llx\n",
3215                 device_id, part_no);
3216
3217         return -ENODEV;
3218 }
3219
3220 static int sja1105_probe(struct spi_device *spi)
3221 {
3222         struct device *dev = &spi->dev;
3223         struct sja1105_private *priv;
3224         size_t max_xfer, max_msg;
3225         struct dsa_switch *ds;
3226         int rc;
3227
3228         if (!dev->of_node) {
3229                 dev_err(dev, "No DTS bindings for SJA1105 driver\n");
3230                 return -EINVAL;
3231         }
3232
3233         priv = devm_kzalloc(dev, sizeof(struct sja1105_private), GFP_KERNEL);
3234         if (!priv)
3235                 return -ENOMEM;
3236
3237         /* Configure the optional reset pin and bring up switch */
3238         priv->reset_gpio = devm_gpiod_get(dev, "reset", GPIOD_OUT_HIGH);
3239         if (IS_ERR(priv->reset_gpio))
3240                 dev_dbg(dev, "reset-gpios not defined, ignoring\n");
3241         else
3242                 sja1105_hw_reset(priv->reset_gpio, 1, 1);
3243
3244         /* Populate our driver private structure (priv) based on
3245          * the device tree node that was probed (spi)
3246          */
3247         priv->spidev = spi;
3248         spi_set_drvdata(spi, priv);
3249
3250         /* Configure the SPI bus */
3251         spi->bits_per_word = 8;
3252         rc = spi_setup(spi);
3253         if (rc < 0) {
3254                 dev_err(dev, "Could not init SPI\n");
3255                 return rc;
3256         }
3257
3258         /* In sja1105_xfer, we send spi_messages composed of two spi_transfers:
3259          * a small one for the message header and another one for the current
3260          * chunk of the packed buffer.
3261          * Check that the restrictions imposed by the SPI controller are
3262          * respected: the chunk buffer is smaller than the max transfer size,
3263          * and the total length of the chunk plus its message header is smaller
3264          * than the max message size.
3265          * We do that during probe time since the maximum transfer size is a
3266          * runtime invariant.
3267          */
3268         max_xfer = spi_max_transfer_size(spi);
3269         max_msg = spi_max_message_size(spi);
3270
3271         /* We need to send at least one 64-bit word of SPI payload per message
3272          * in order to be able to make useful progress.
3273          */
3274         if (max_msg < SJA1105_SIZE_SPI_MSG_HEADER + 8) {
3275                 dev_err(dev, "SPI master cannot send large enough buffers, aborting\n");
3276                 return -EINVAL;
3277         }
3278
3279         priv->max_xfer_len = SJA1105_SIZE_SPI_MSG_MAXLEN;
3280         if (priv->max_xfer_len > max_xfer)
3281                 priv->max_xfer_len = max_xfer;
3282         if (priv->max_xfer_len > max_msg - SJA1105_SIZE_SPI_MSG_HEADER)
3283                 priv->max_xfer_len = max_msg - SJA1105_SIZE_SPI_MSG_HEADER;
3284
3285         priv->info = of_device_get_match_data(dev);
3286
3287         /* Detect hardware device */
3288         rc = sja1105_check_device_id(priv);
3289         if (rc < 0) {
3290                 dev_err(dev, "Device ID check failed: %d\n", rc);
3291                 return rc;
3292         }
3293
3294         dev_info(dev, "Probed switch chip: %s\n", priv->info->name);
3295
3296         ds = devm_kzalloc(dev, sizeof(*ds), GFP_KERNEL);
3297         if (!ds)
3298                 return -ENOMEM;
3299
3300         ds->dev = dev;
3301         ds->num_ports = priv->info->num_ports;
3302         ds->ops = &sja1105_switch_ops;
3303         ds->priv = priv;
3304         priv->ds = ds;
3305
3306         mutex_init(&priv->ptp_data.lock);
3307         mutex_init(&priv->mgmt_lock);
3308
3309         rc = sja1105_parse_dt(priv);
3310         if (rc < 0) {
3311                 dev_err(ds->dev, "Failed to parse DT: %d\n", rc);
3312                 return rc;
3313         }
3314
3315         /* Error out early if internal delays are required through DT
3316          * and we can't apply them.
3317          */
3318         rc = sja1105_parse_rgmii_delays(priv);
3319         if (rc < 0) {
3320                 dev_err(ds->dev, "RGMII delay not supported\n");
3321                 return rc;
3322         }
3323
3324         if (IS_ENABLED(CONFIG_NET_SCH_CBS)) {
3325                 priv->cbs = devm_kcalloc(dev, priv->info->num_cbs_shapers,
3326                                          sizeof(struct sja1105_cbs_entry),
3327                                          GFP_KERNEL);
3328                 if (!priv->cbs)
3329                         return -ENOMEM;
3330         }
3331
3332         return dsa_register_switch(priv->ds);
3333 }
3334
3335 static int sja1105_remove(struct spi_device *spi)
3336 {
3337         struct sja1105_private *priv = spi_get_drvdata(spi);
3338
3339         if (!priv)
3340                 return 0;
3341
3342         dsa_unregister_switch(priv->ds);
3343
3344         spi_set_drvdata(spi, NULL);
3345
3346         return 0;
3347 }
3348
3349 static void sja1105_shutdown(struct spi_device *spi)
3350 {
3351         struct sja1105_private *priv = spi_get_drvdata(spi);
3352
3353         if (!priv)
3354                 return;
3355
3356         dsa_switch_shutdown(priv->ds);
3357
3358         spi_set_drvdata(spi, NULL);
3359 }
3360
3361 static const struct of_device_id sja1105_dt_ids[] = {
3362         { .compatible = "nxp,sja1105e", .data = &sja1105e_info },
3363         { .compatible = "nxp,sja1105t", .data = &sja1105t_info },
3364         { .compatible = "nxp,sja1105p", .data = &sja1105p_info },
3365         { .compatible = "nxp,sja1105q", .data = &sja1105q_info },
3366         { .compatible = "nxp,sja1105r", .data = &sja1105r_info },
3367         { .compatible = "nxp,sja1105s", .data = &sja1105s_info },
3368         { .compatible = "nxp,sja1110a", .data = &sja1110a_info },
3369         { .compatible = "nxp,sja1110b", .data = &sja1110b_info },
3370         { .compatible = "nxp,sja1110c", .data = &sja1110c_info },
3371         { .compatible = "nxp,sja1110d", .data = &sja1110d_info },
3372         { /* sentinel */ },
3373 };
3374 MODULE_DEVICE_TABLE(of, sja1105_dt_ids);
3375
3376 static struct spi_driver sja1105_driver = {
3377         .driver = {
3378                 .name  = "sja1105",
3379                 .owner = THIS_MODULE,
3380                 .of_match_table = of_match_ptr(sja1105_dt_ids),
3381         },
3382         .probe  = sja1105_probe,
3383         .remove = sja1105_remove,
3384         .shutdown = sja1105_shutdown,
3385 };
3386
3387 module_spi_driver(sja1105_driver);
3388
3389 MODULE_AUTHOR("Vladimir Oltean <olteanv@gmail.com>");
3390 MODULE_AUTHOR("Georg Waibel <georg.waibel@sensor-technik.de>");
3391 MODULE_DESCRIPTION("SJA1105 Driver");
3392 MODULE_LICENSE("GPL v2");