1 // SPDX-License-Identifier: GPL-2.0
2 /* Copyright (c) 2018, Sensor-Technik Wiedemann GmbH
3 * Copyright (c) 2018-2019, Vladimir Oltean <olteanv@gmail.com>
6 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
8 #include <linux/delay.h>
9 #include <linux/module.h>
10 #include <linux/printk.h>
11 #include <linux/spi/spi.h>
12 #include <linux/errno.h>
13 #include <linux/gpio/consumer.h>
14 #include <linux/phylink.h>
16 #include <linux/of_net.h>
17 #include <linux/of_mdio.h>
18 #include <linux/of_device.h>
19 #include <linux/pcs/pcs-xpcs.h>
20 #include <linux/netdev_features.h>
21 #include <linux/netdevice.h>
22 #include <linux/if_bridge.h>
23 #include <linux/if_ether.h>
24 #include <linux/dsa/8021q.h>
26 #include "sja1105_tas.h"
28 #define SJA1105_UNKNOWN_MULTICAST 0x010000000000ull
30 /* Configure the optional reset pin and bring up switch */
31 static int sja1105_hw_reset(struct device *dev, unsigned int pulse_len,
32 unsigned int startup_delay)
34 struct gpio_desc *gpio;
36 gpio = gpiod_get_optional(dev, "reset", GPIOD_OUT_HIGH);
43 gpiod_set_value_cansleep(gpio, 1);
44 /* Wait for minimum reset pulse length */
46 gpiod_set_value_cansleep(gpio, 0);
47 /* Wait until chip is ready after reset */
48 msleep(startup_delay);
56 sja1105_port_allow_traffic(struct sja1105_l2_forwarding_entry *l2_fwd,
57 int from, int to, bool allow)
60 l2_fwd[from].reach_port |= BIT(to);
62 l2_fwd[from].reach_port &= ~BIT(to);
65 static bool sja1105_can_forward(struct sja1105_l2_forwarding_entry *l2_fwd,
68 return !!(l2_fwd[from].reach_port & BIT(to));
71 static int sja1105_is_vlan_configured(struct sja1105_private *priv, u16 vid)
73 struct sja1105_vlan_lookup_entry *vlan;
76 vlan = priv->static_config.tables[BLK_IDX_VLAN_LOOKUP].entries;
77 count = priv->static_config.tables[BLK_IDX_VLAN_LOOKUP].entry_count;
79 for (i = 0; i < count; i++)
80 if (vlan[i].vlanid == vid)
83 /* Return an invalid entry index if not found */
87 static int sja1105_drop_untagged(struct dsa_switch *ds, int port, bool drop)
89 struct sja1105_private *priv = ds->priv;
90 struct sja1105_mac_config_entry *mac;
92 mac = priv->static_config.tables[BLK_IDX_MAC_CONFIG].entries;
94 if (mac[port].drpuntag == drop)
97 mac[port].drpuntag = drop;
99 return sja1105_dynamic_config_write(priv, BLK_IDX_MAC_CONFIG, port,
103 static int sja1105_pvid_apply(struct sja1105_private *priv, int port, u16 pvid)
105 struct sja1105_mac_config_entry *mac;
107 mac = priv->static_config.tables[BLK_IDX_MAC_CONFIG].entries;
109 if (mac[port].vlanid == pvid)
112 mac[port].vlanid = pvid;
114 return sja1105_dynamic_config_write(priv, BLK_IDX_MAC_CONFIG, port,
118 static int sja1105_commit_pvid(struct dsa_switch *ds, int port)
120 struct dsa_port *dp = dsa_to_port(ds, port);
121 struct net_device *br = dsa_port_bridge_dev_get(dp);
122 struct sja1105_private *priv = ds->priv;
123 struct sja1105_vlan_lookup_entry *vlan;
124 bool drop_untagged = false;
128 if (br && br_vlan_enabled(br))
129 pvid = priv->bridge_pvid[port];
131 pvid = priv->tag_8021q_pvid[port];
133 rc = sja1105_pvid_apply(priv, port, pvid);
137 /* Only force dropping of untagged packets when the port is under a
138 * VLAN-aware bridge. When the tag_8021q pvid is used, we are
139 * deliberately removing the RX VLAN from the port's VMEMB_PORT list,
140 * to prevent DSA tag spoofing from the link partner. Untagged packets
141 * are the only ones that should be received with tag_8021q, so
142 * definitely don't drop them.
144 if (pvid == priv->bridge_pvid[port]) {
145 vlan = priv->static_config.tables[BLK_IDX_VLAN_LOOKUP].entries;
147 match = sja1105_is_vlan_configured(priv, pvid);
149 if (match < 0 || !(vlan[match].vmemb_port & BIT(port)))
150 drop_untagged = true;
153 if (dsa_is_cpu_port(ds, port) || dsa_is_dsa_port(ds, port))
154 drop_untagged = true;
156 return sja1105_drop_untagged(ds, port, drop_untagged);
159 static int sja1105_init_mac_settings(struct sja1105_private *priv)
161 struct sja1105_mac_config_entry default_mac = {
162 /* Enable all 8 priority queues on egress.
163 * Every queue i holds top[i] - base[i] frames.
164 * Sum of top[i] - base[i] is 511 (max hardware limit).
166 .top = {0x3F, 0x7F, 0xBF, 0xFF, 0x13F, 0x17F, 0x1BF, 0x1FF},
167 .base = {0x0, 0x40, 0x80, 0xC0, 0x100, 0x140, 0x180, 0x1C0},
168 .enabled = {true, true, true, true, true, true, true, true},
169 /* Keep standard IFG of 12 bytes on egress. */
171 /* Always put the MAC speed in automatic mode, where it can be
172 * adjusted at runtime by PHYLINK.
174 .speed = priv->info->port_speed[SJA1105_SPEED_AUTO],
175 /* No static correction for 1-step 1588 events */
178 /* Disable aging for critical TTEthernet traffic */
180 /* Internal VLAN (pvid) to apply to untagged ingress */
185 /* Don't drop traffic with other EtherType than ETH_P_IP */
187 /* Don't drop double-tagged traffic */
189 /* Don't drop untagged traffic */
191 /* Don't retag 802.1p (VID 0) traffic with the pvid */
193 /* Disable learning and I/O on user ports by default -
194 * STP will enable it.
200 struct sja1105_mac_config_entry *mac;
201 struct dsa_switch *ds = priv->ds;
202 struct sja1105_table *table;
205 table = &priv->static_config.tables[BLK_IDX_MAC_CONFIG];
207 /* Discard previous MAC Configuration Table */
208 if (table->entry_count) {
209 kfree(table->entries);
210 table->entry_count = 0;
213 table->entries = kcalloc(table->ops->max_entry_count,
214 table->ops->unpacked_entry_size, GFP_KERNEL);
218 table->entry_count = table->ops->max_entry_count;
220 mac = table->entries;
222 list_for_each_entry(dp, &ds->dst->ports, list) {
226 mac[dp->index] = default_mac;
228 /* Let sja1105_bridge_stp_state_set() keep address learning
229 * enabled for the DSA ports. CPU ports use software-assisted
230 * learning to ensure that only FDB entries belonging to the
231 * bridge are learned, and that they are learned towards all
232 * CPU ports in a cross-chip topology if multiple CPU ports
235 if (dsa_port_is_dsa(dp))
238 /* Disallow untagged packets from being received on the
241 if (dsa_port_is_cpu(dp) || dsa_port_is_dsa(dp))
242 mac[dp->index].drpuntag = true;
248 static int sja1105_init_mii_settings(struct sja1105_private *priv)
250 struct device *dev = &priv->spidev->dev;
251 struct sja1105_xmii_params_entry *mii;
252 struct dsa_switch *ds = priv->ds;
253 struct sja1105_table *table;
256 table = &priv->static_config.tables[BLK_IDX_XMII_PARAMS];
258 /* Discard previous xMII Mode Parameters Table */
259 if (table->entry_count) {
260 kfree(table->entries);
261 table->entry_count = 0;
264 table->entries = kcalloc(table->ops->max_entry_count,
265 table->ops->unpacked_entry_size, GFP_KERNEL);
269 /* Override table based on PHYLINK DT bindings */
270 table->entry_count = table->ops->max_entry_count;
272 mii = table->entries;
274 for (i = 0; i < ds->num_ports; i++) {
275 sja1105_mii_role_t role = XMII_MAC;
277 if (dsa_is_unused_port(priv->ds, i))
280 switch (priv->phy_mode[i]) {
281 case PHY_INTERFACE_MODE_INTERNAL:
282 if (priv->info->internal_phy[i] == SJA1105_NO_PHY)
285 mii->xmii_mode[i] = XMII_MODE_MII;
286 if (priv->info->internal_phy[i] == SJA1105_PHY_BASE_TX)
287 mii->special[i] = true;
290 case PHY_INTERFACE_MODE_REVMII:
293 case PHY_INTERFACE_MODE_MII:
294 if (!priv->info->supports_mii[i])
297 mii->xmii_mode[i] = XMII_MODE_MII;
299 case PHY_INTERFACE_MODE_REVRMII:
302 case PHY_INTERFACE_MODE_RMII:
303 if (!priv->info->supports_rmii[i])
306 mii->xmii_mode[i] = XMII_MODE_RMII;
308 case PHY_INTERFACE_MODE_RGMII:
309 case PHY_INTERFACE_MODE_RGMII_ID:
310 case PHY_INTERFACE_MODE_RGMII_RXID:
311 case PHY_INTERFACE_MODE_RGMII_TXID:
312 if (!priv->info->supports_rgmii[i])
315 mii->xmii_mode[i] = XMII_MODE_RGMII;
317 case PHY_INTERFACE_MODE_SGMII:
318 if (!priv->info->supports_sgmii[i])
321 mii->xmii_mode[i] = XMII_MODE_SGMII;
322 mii->special[i] = true;
324 case PHY_INTERFACE_MODE_2500BASEX:
325 if (!priv->info->supports_2500basex[i])
328 mii->xmii_mode[i] = XMII_MODE_SGMII;
329 mii->special[i] = true;
333 dev_err(dev, "Unsupported PHY mode %s on port %d!\n",
334 phy_modes(priv->phy_mode[i]), i);
338 mii->phy_mac[i] = role;
343 static int sja1105_init_static_fdb(struct sja1105_private *priv)
345 struct sja1105_l2_lookup_entry *l2_lookup;
346 struct sja1105_table *table;
349 table = &priv->static_config.tables[BLK_IDX_L2_LOOKUP];
351 /* We only populate the FDB table through dynamic L2 Address Lookup
352 * entries, except for a special entry at the end which is a catch-all
353 * for unknown multicast and will be used to control flooding domain.
355 if (table->entry_count) {
356 kfree(table->entries);
357 table->entry_count = 0;
360 if (!priv->info->can_limit_mcast_flood)
363 table->entries = kcalloc(1, table->ops->unpacked_entry_size,
368 table->entry_count = 1;
369 l2_lookup = table->entries;
371 /* All L2 multicast addresses have an odd first octet */
372 l2_lookup[0].macaddr = SJA1105_UNKNOWN_MULTICAST;
373 l2_lookup[0].mask_macaddr = SJA1105_UNKNOWN_MULTICAST;
374 l2_lookup[0].lockeds = true;
375 l2_lookup[0].index = SJA1105_MAX_L2_LOOKUP_COUNT - 1;
377 /* Flood multicast to every port by default */
378 for (port = 0; port < priv->ds->num_ports; port++)
379 if (!dsa_is_unused_port(priv->ds, port))
380 l2_lookup[0].destports |= BIT(port);
385 static int sja1105_init_l2_lookup_params(struct sja1105_private *priv)
387 struct sja1105_l2_lookup_params_entry default_l2_lookup_params = {
388 /* Learned FDB entries are forgotten after 300 seconds */
389 .maxage = SJA1105_AGEING_TIME_MS(300000),
390 /* All entries within a FDB bin are available for learning */
391 .dyn_tbsz = SJA1105ET_FDB_BIN_SIZE,
392 /* And the P/Q/R/S equivalent setting: */
394 /* 2^8 + 2^5 + 2^3 + 2^2 + 2^1 + 1 in Koopman notation */
396 /* Always use Independent VLAN Learning (IVL) */
397 .shared_learn = false,
398 /* Don't discard management traffic based on ENFPORT -
399 * we don't perform SMAC port enforcement anyway, so
400 * what we are setting here doesn't matter.
402 .no_enf_hostprt = false,
403 /* Don't learn SMAC for mac_fltres1 and mac_fltres0.
404 * Maybe correlate with no_linklocal_learn from bridge driver?
406 .no_mgmt_learn = true,
409 /* Dynamically learned FDB entries can overwrite other (older)
410 * dynamic FDB entries
415 struct dsa_switch *ds = priv->ds;
416 int port, num_used_ports = 0;
417 struct sja1105_table *table;
420 for (port = 0; port < ds->num_ports; port++)
421 if (!dsa_is_unused_port(ds, port))
424 max_fdb_entries = SJA1105_MAX_L2_LOOKUP_COUNT / num_used_ports;
426 for (port = 0; port < ds->num_ports; port++) {
427 if (dsa_is_unused_port(ds, port))
430 default_l2_lookup_params.maxaddrp[port] = max_fdb_entries;
433 table = &priv->static_config.tables[BLK_IDX_L2_LOOKUP_PARAMS];
435 if (table->entry_count) {
436 kfree(table->entries);
437 table->entry_count = 0;
440 table->entries = kcalloc(table->ops->max_entry_count,
441 table->ops->unpacked_entry_size, GFP_KERNEL);
445 table->entry_count = table->ops->max_entry_count;
447 /* This table only has a single entry */
448 ((struct sja1105_l2_lookup_params_entry *)table->entries)[0] =
449 default_l2_lookup_params;
454 /* Set up a default VLAN for untagged traffic injected from the CPU
455 * using management routes (e.g. STP, PTP) as opposed to tag_8021q.
456 * All DT-defined ports are members of this VLAN, and there are no
457 * restrictions on forwarding (since the CPU selects the destination).
458 * Frames from this VLAN will always be transmitted as untagged, and
459 * neither the bridge nor the 8021q module cannot create this VLAN ID.
461 static int sja1105_init_static_vlan(struct sja1105_private *priv)
463 struct sja1105_table *table;
464 struct sja1105_vlan_lookup_entry pvid = {
465 .type_entry = SJA1110_VLAN_D_TAG,
471 .vlanid = SJA1105_DEFAULT_VLAN,
473 struct dsa_switch *ds = priv->ds;
476 table = &priv->static_config.tables[BLK_IDX_VLAN_LOOKUP];
478 if (table->entry_count) {
479 kfree(table->entries);
480 table->entry_count = 0;
483 table->entries = kzalloc(table->ops->unpacked_entry_size,
488 table->entry_count = 1;
490 for (port = 0; port < ds->num_ports; port++) {
491 if (dsa_is_unused_port(ds, port))
494 pvid.vmemb_port |= BIT(port);
495 pvid.vlan_bc |= BIT(port);
496 pvid.tag_port &= ~BIT(port);
498 if (dsa_is_cpu_port(ds, port) || dsa_is_dsa_port(ds, port)) {
499 priv->tag_8021q_pvid[port] = SJA1105_DEFAULT_VLAN;
500 priv->bridge_pvid[port] = SJA1105_DEFAULT_VLAN;
504 ((struct sja1105_vlan_lookup_entry *)table->entries)[0] = pvid;
508 static int sja1105_init_l2_forwarding(struct sja1105_private *priv)
510 struct sja1105_l2_forwarding_entry *l2fwd;
511 struct dsa_switch *ds = priv->ds;
512 struct dsa_switch_tree *dst;
513 struct sja1105_table *table;
518 table = &priv->static_config.tables[BLK_IDX_L2_FORWARDING];
520 if (table->entry_count) {
521 kfree(table->entries);
522 table->entry_count = 0;
525 table->entries = kcalloc(table->ops->max_entry_count,
526 table->ops->unpacked_entry_size, GFP_KERNEL);
530 table->entry_count = table->ops->max_entry_count;
532 l2fwd = table->entries;
534 /* First 5 entries in the L2 Forwarding Table define the forwarding
535 * rules and the VLAN PCP to ingress queue mapping.
536 * Set up the ingress queue mapping first.
538 for (port = 0; port < ds->num_ports; port++) {
539 if (dsa_is_unused_port(ds, port))
542 for (tc = 0; tc < SJA1105_NUM_TC; tc++)
543 l2fwd[port].vlan_pmap[tc] = tc;
546 /* Then manage the forwarding domain for user ports. These can forward
547 * only to the always-on domain (CPU port and DSA links)
549 for (from = 0; from < ds->num_ports; from++) {
550 if (!dsa_is_user_port(ds, from))
553 for (to = 0; to < ds->num_ports; to++) {
554 if (!dsa_is_cpu_port(ds, to) &&
555 !dsa_is_dsa_port(ds, to))
558 l2fwd[from].bc_domain |= BIT(to);
559 l2fwd[from].fl_domain |= BIT(to);
561 sja1105_port_allow_traffic(l2fwd, from, to, true);
565 /* Then manage the forwarding domain for DSA links and CPU ports (the
566 * always-on domain). These can send packets to any enabled port except
569 for (from = 0; from < ds->num_ports; from++) {
570 if (!dsa_is_cpu_port(ds, from) && !dsa_is_dsa_port(ds, from))
573 for (to = 0; to < ds->num_ports; to++) {
574 if (dsa_is_unused_port(ds, to))
580 l2fwd[from].bc_domain |= BIT(to);
581 l2fwd[from].fl_domain |= BIT(to);
583 sja1105_port_allow_traffic(l2fwd, from, to, true);
587 /* In odd topologies ("H" connections where there is a DSA link to
588 * another switch which also has its own CPU port), TX packets can loop
589 * back into the system (they are flooded from CPU port 1 to the DSA
590 * link, and from there to CPU port 2). Prevent this from happening by
591 * cutting RX from DSA links towards our CPU port, if the remote switch
592 * has its own CPU port and therefore doesn't need ours for network
597 list_for_each_entry(dl, &dst->rtable, list) {
598 if (dl->dp->ds != ds || dl->link_dp->cpu_dp == dl->dp->cpu_dp)
601 from = dl->dp->index;
602 to = dsa_upstream_port(ds, from);
605 "H topology detected, cutting RX from DSA link %d to CPU port %d to prevent TX packet loops\n",
608 sja1105_port_allow_traffic(l2fwd, from, to, false);
610 l2fwd[from].bc_domain &= ~BIT(to);
611 l2fwd[from].fl_domain &= ~BIT(to);
614 /* Finally, manage the egress flooding domain. All ports start up with
615 * flooding enabled, including the CPU port and DSA links.
617 for (port = 0; port < ds->num_ports; port++) {
618 if (dsa_is_unused_port(ds, port))
621 priv->ucast_egress_floods |= BIT(port);
622 priv->bcast_egress_floods |= BIT(port);
625 /* Next 8 entries define VLAN PCP mapping from ingress to egress.
626 * Create a one-to-one mapping.
628 for (tc = 0; tc < SJA1105_NUM_TC; tc++) {
629 for (port = 0; port < ds->num_ports; port++) {
630 if (dsa_is_unused_port(ds, port))
633 l2fwd[ds->num_ports + tc].vlan_pmap[port] = tc;
636 l2fwd[ds->num_ports + tc].type_egrpcp2outputq = true;
642 static int sja1110_init_pcp_remapping(struct sja1105_private *priv)
644 struct sja1110_pcp_remapping_entry *pcp_remap;
645 struct dsa_switch *ds = priv->ds;
646 struct sja1105_table *table;
649 table = &priv->static_config.tables[BLK_IDX_PCP_REMAPPING];
651 /* Nothing to do for SJA1105 */
652 if (!table->ops->max_entry_count)
655 if (table->entry_count) {
656 kfree(table->entries);
657 table->entry_count = 0;
660 table->entries = kcalloc(table->ops->max_entry_count,
661 table->ops->unpacked_entry_size, GFP_KERNEL);
665 table->entry_count = table->ops->max_entry_count;
667 pcp_remap = table->entries;
669 /* Repeat the configuration done for vlan_pmap */
670 for (port = 0; port < ds->num_ports; port++) {
671 if (dsa_is_unused_port(ds, port))
674 for (tc = 0; tc < SJA1105_NUM_TC; tc++)
675 pcp_remap[port].egrpcp[tc] = tc;
681 static int sja1105_init_l2_forwarding_params(struct sja1105_private *priv)
683 struct sja1105_l2_forwarding_params_entry *l2fwd_params;
684 struct sja1105_table *table;
686 table = &priv->static_config.tables[BLK_IDX_L2_FORWARDING_PARAMS];
688 if (table->entry_count) {
689 kfree(table->entries);
690 table->entry_count = 0;
693 table->entries = kcalloc(table->ops->max_entry_count,
694 table->ops->unpacked_entry_size, GFP_KERNEL);
698 table->entry_count = table->ops->max_entry_count;
700 /* This table only has a single entry */
701 l2fwd_params = table->entries;
703 /* Disallow dynamic reconfiguration of vlan_pmap */
704 l2fwd_params->max_dynp = 0;
705 /* Use a single memory partition for all ingress queues */
706 l2fwd_params->part_spc[0] = priv->info->max_frame_mem;
711 void sja1105_frame_memory_partitioning(struct sja1105_private *priv)
713 struct sja1105_l2_forwarding_params_entry *l2_fwd_params;
714 struct sja1105_vl_forwarding_params_entry *vl_fwd_params;
715 struct sja1105_table *table;
717 table = &priv->static_config.tables[BLK_IDX_L2_FORWARDING_PARAMS];
718 l2_fwd_params = table->entries;
719 l2_fwd_params->part_spc[0] = SJA1105_MAX_FRAME_MEMORY;
721 /* If we have any critical-traffic virtual links, we need to reserve
722 * some frame buffer memory for them. At the moment, hardcode the value
723 * at 100 blocks of 128 bytes of memory each. This leaves 829 blocks
724 * remaining for best-effort traffic. TODO: figure out a more flexible
725 * way to perform the frame buffer partitioning.
727 if (!priv->static_config.tables[BLK_IDX_VL_FORWARDING].entry_count)
730 table = &priv->static_config.tables[BLK_IDX_VL_FORWARDING_PARAMS];
731 vl_fwd_params = table->entries;
733 l2_fwd_params->part_spc[0] -= SJA1105_VL_FRAME_MEMORY;
734 vl_fwd_params->partspc[0] = SJA1105_VL_FRAME_MEMORY;
737 /* SJA1110 TDMACONFIGIDX values:
739 * | 100 Mbps ports | 1Gbps ports | 2.5Gbps ports | Disabled ports
740 * -----+----------------+---------------+---------------+---------------
741 * 0 | 0, [5:10] | [1:2] | [3:4] | retag
742 * 1 |0, [5:10], retag| [1:2] | [3:4] | -
743 * 2 | 0, [5:10] | [1:3], retag | 4 | -
744 * 3 | 0, [5:10] |[1:2], 4, retag| 3 | -
745 * 4 | 0, 2, [5:10] | 1, retag | [3:4] | -
746 * 5 | 0, 1, [5:10] | 2, retag | [3:4] | -
747 * 14 | 0, [5:10] | [1:4], retag | - | -
748 * 15 | [5:10] | [0:4], retag | - | -
750 static void sja1110_select_tdmaconfigidx(struct sja1105_private *priv)
752 struct sja1105_general_params_entry *general_params;
753 struct sja1105_table *table;
754 bool port_1_is_base_tx;
759 if (priv->info->device_id != SJA1110_DEVICE_ID)
762 table = &priv->static_config.tables[BLK_IDX_GENERAL_PARAMS];
763 general_params = table->entries;
765 /* All the settings below are "as opposed to SGMII", which is the
766 * other pinmuxing option.
768 port_1_is_base_tx = priv->phy_mode[1] == PHY_INTERFACE_MODE_INTERNAL;
769 port_3_is_2500 = priv->phy_mode[3] == PHY_INTERFACE_MODE_2500BASEX;
770 port_4_is_2500 = priv->phy_mode[4] == PHY_INTERFACE_MODE_2500BASEX;
772 if (port_1_is_base_tx)
773 /* Retagging port will operate at 1 Gbps */
775 else if (port_3_is_2500 && port_4_is_2500)
776 /* Retagging port will operate at 100 Mbps */
778 else if (port_3_is_2500)
779 /* Retagging port will operate at 1 Gbps */
781 else if (port_4_is_2500)
782 /* Retagging port will operate at 1 Gbps */
785 /* Retagging port will operate at 1 Gbps */
788 general_params->tdmaconfigidx = tdmaconfigidx;
791 static int sja1105_init_topology(struct sja1105_private *priv,
792 struct sja1105_general_params_entry *general_params)
794 struct dsa_switch *ds = priv->ds;
797 /* The host port is the destination for traffic matching mac_fltres1
798 * and mac_fltres0 on all ports except itself. Default to an invalid
801 general_params->host_port = ds->num_ports;
803 /* Link-local traffic received on casc_port will be forwarded
804 * to host_port without embedding the source port and device ID
805 * info in the destination MAC address, and no RX timestamps will be
806 * taken either (presumably because it is a cascaded port and a
807 * downstream SJA switch already did that).
808 * To disable the feature, we need to do different things depending on
809 * switch generation. On SJA1105 we need to set an invalid port, while
810 * on SJA1110 which support multiple cascaded ports, this field is a
811 * bitmask so it must be left zero.
813 if (!priv->info->multiple_cascade_ports)
814 general_params->casc_port = ds->num_ports;
816 for (port = 0; port < ds->num_ports; port++) {
817 bool is_upstream = dsa_is_upstream_port(ds, port);
818 bool is_dsa_link = dsa_is_dsa_port(ds, port);
820 /* Upstream ports can be dedicated CPU ports or
821 * upstream-facing DSA links
824 if (general_params->host_port == ds->num_ports) {
825 general_params->host_port = port;
828 "Port %llu is already a host port, configuring %d as one too is not supported\n",
829 general_params->host_port, port);
834 /* Cascade ports are downstream-facing DSA links */
835 if (is_dsa_link && !is_upstream) {
836 if (priv->info->multiple_cascade_ports) {
837 general_params->casc_port |= BIT(port);
838 } else if (general_params->casc_port == ds->num_ports) {
839 general_params->casc_port = port;
842 "Port %llu is already a cascade port, configuring %d as one too is not supported\n",
843 general_params->casc_port, port);
849 if (general_params->host_port == ds->num_ports) {
850 dev_err(ds->dev, "No host port configured\n");
857 static int sja1105_init_general_params(struct sja1105_private *priv)
859 struct sja1105_general_params_entry default_general_params = {
860 /* Allow dynamic changing of the mirror port */
862 .switchid = priv->ds->index,
863 /* Priority queue for link-local management frames
864 * (both ingress to and egress from CPU - PTP, STP etc)
867 .mac_fltres1 = SJA1105_LINKLOCAL_FILTER_A,
868 .mac_flt1 = SJA1105_LINKLOCAL_FILTER_A_MASK,
869 .incl_srcpt1 = false,
871 .mac_fltres0 = SJA1105_LINKLOCAL_FILTER_B,
872 .mac_flt0 = SJA1105_LINKLOCAL_FILTER_B_MASK,
873 .incl_srcpt0 = false,
875 /* Default to an invalid value */
876 .mirr_port = priv->ds->num_ports,
878 .vllupformat = SJA1105_VL_FORMAT_PSFP,
881 /* Only update correctionField for 1-step PTP (L2 transport) */
883 /* Forcefully disable VLAN filtering by telling
884 * the switch that VLAN has a different EtherType.
886 .tpid = ETH_P_SJA1105,
887 .tpid2 = ETH_P_SJA1105,
888 /* Enable the TTEthernet engine on SJA1110 */
890 /* Set up the EtherType for control packets on SJA1110 */
891 .header_type = ETH_P_SJA1110,
893 struct sja1105_general_params_entry *general_params;
894 struct sja1105_table *table;
897 rc = sja1105_init_topology(priv, &default_general_params);
901 table = &priv->static_config.tables[BLK_IDX_GENERAL_PARAMS];
903 if (table->entry_count) {
904 kfree(table->entries);
905 table->entry_count = 0;
908 table->entries = kcalloc(table->ops->max_entry_count,
909 table->ops->unpacked_entry_size, GFP_KERNEL);
913 table->entry_count = table->ops->max_entry_count;
915 general_params = table->entries;
917 /* This table only has a single entry */
918 general_params[0] = default_general_params;
920 sja1110_select_tdmaconfigidx(priv);
925 static int sja1105_init_avb_params(struct sja1105_private *priv)
927 struct sja1105_avb_params_entry *avb;
928 struct sja1105_table *table;
930 table = &priv->static_config.tables[BLK_IDX_AVB_PARAMS];
932 /* Discard previous AVB Parameters Table */
933 if (table->entry_count) {
934 kfree(table->entries);
935 table->entry_count = 0;
938 table->entries = kcalloc(table->ops->max_entry_count,
939 table->ops->unpacked_entry_size, GFP_KERNEL);
943 table->entry_count = table->ops->max_entry_count;
945 avb = table->entries;
947 /* Configure the MAC addresses for meta frames */
948 avb->destmeta = SJA1105_META_DMAC;
949 avb->srcmeta = SJA1105_META_SMAC;
950 /* On P/Q/R/S, configure the direction of the PTP_CLK pin as input by
951 * default. This is because there might be boards with a hardware
952 * layout where enabling the pin as output might cause an electrical
953 * clash. On E/T the pin is always an output, which the board designers
954 * probably already knew, so even if there are going to be electrical
955 * issues, there's nothing we can do.
957 avb->cas_master = false;
962 /* The L2 policing table is 2-stage. The table is looked up for each frame
963 * according to the ingress port, whether it was broadcast or not, and the
964 * classified traffic class (given by VLAN PCP). This portion of the lookup is
965 * fixed, and gives access to the SHARINDX, an indirection register pointing
966 * within the policing table itself, which is used to resolve the policer that
967 * will be used for this frame.
970 * +------------+--------+ +---------------------------------+
971 * |Port 0 TC 0 |SHARINDX| | Policer 0: Rate, Burst, MTU |
972 * +------------+--------+ +---------------------------------+
973 * |Port 0 TC 1 |SHARINDX| | Policer 1: Rate, Burst, MTU |
974 * +------------+--------+ +---------------------------------+
975 * ... | Policer 2: Rate, Burst, MTU |
976 * +------------+--------+ +---------------------------------+
977 * |Port 0 TC 7 |SHARINDX| | Policer 3: Rate, Burst, MTU |
978 * +------------+--------+ +---------------------------------+
979 * |Port 1 TC 0 |SHARINDX| | Policer 4: Rate, Burst, MTU |
980 * +------------+--------+ +---------------------------------+
981 * ... | Policer 5: Rate, Burst, MTU |
982 * +------------+--------+ +---------------------------------+
983 * |Port 1 TC 7 |SHARINDX| | Policer 6: Rate, Burst, MTU |
984 * +------------+--------+ +---------------------------------+
985 * ... | Policer 7: Rate, Burst, MTU |
986 * +------------+--------+ +---------------------------------+
987 * |Port 4 TC 7 |SHARINDX| ...
988 * +------------+--------+
989 * |Port 0 BCAST|SHARINDX| ...
990 * +------------+--------+
991 * |Port 1 BCAST|SHARINDX| ...
992 * +------------+--------+
994 * +------------+--------+ +---------------------------------+
995 * |Port 4 BCAST|SHARINDX| | Policer 44: Rate, Burst, MTU |
996 * +------------+--------+ +---------------------------------+
998 * In this driver, we shall use policers 0-4 as statically alocated port
999 * (matchall) policers. So we need to make the SHARINDX for all lookups
1000 * corresponding to this ingress port (8 VLAN PCP lookups and 1 broadcast
1002 * The remaining policers (40) shall be dynamically allocated for flower
1003 * policers, where the key is either vlan_prio or dst_mac ff:ff:ff:ff:ff:ff.
1005 #define SJA1105_RATE_MBPS(speed) (((speed) * 64000) / 1000)
1007 static int sja1105_init_l2_policing(struct sja1105_private *priv)
1009 struct sja1105_l2_policing_entry *policing;
1010 struct dsa_switch *ds = priv->ds;
1011 struct sja1105_table *table;
1014 table = &priv->static_config.tables[BLK_IDX_L2_POLICING];
1016 /* Discard previous L2 Policing Table */
1017 if (table->entry_count) {
1018 kfree(table->entries);
1019 table->entry_count = 0;
1022 table->entries = kcalloc(table->ops->max_entry_count,
1023 table->ops->unpacked_entry_size, GFP_KERNEL);
1024 if (!table->entries)
1027 table->entry_count = table->ops->max_entry_count;
1029 policing = table->entries;
1031 /* Setup shared indices for the matchall policers */
1032 for (port = 0; port < ds->num_ports; port++) {
1033 int mcast = (ds->num_ports * (SJA1105_NUM_TC + 1)) + port;
1034 int bcast = (ds->num_ports * SJA1105_NUM_TC) + port;
1036 for (tc = 0; tc < SJA1105_NUM_TC; tc++)
1037 policing[port * SJA1105_NUM_TC + tc].sharindx = port;
1039 policing[bcast].sharindx = port;
1040 /* Only SJA1110 has multicast policers */
1041 if (mcast <= table->ops->max_entry_count)
1042 policing[mcast].sharindx = port;
1045 /* Setup the matchall policer parameters */
1046 for (port = 0; port < ds->num_ports; port++) {
1047 int mtu = VLAN_ETH_FRAME_LEN + ETH_FCS_LEN;
1049 if (dsa_is_cpu_port(ds, port) || dsa_is_dsa_port(ds, port))
1052 policing[port].smax = 65535; /* Burst size in bytes */
1053 policing[port].rate = SJA1105_RATE_MBPS(1000);
1054 policing[port].maxlen = mtu;
1055 policing[port].partition = 0;
1061 static int sja1105_static_config_load(struct sja1105_private *priv)
1065 sja1105_static_config_free(&priv->static_config);
1066 rc = sja1105_static_config_init(&priv->static_config,
1067 priv->info->static_ops,
1068 priv->info->device_id);
1072 /* Build static configuration */
1073 rc = sja1105_init_mac_settings(priv);
1076 rc = sja1105_init_mii_settings(priv);
1079 rc = sja1105_init_static_fdb(priv);
1082 rc = sja1105_init_static_vlan(priv);
1085 rc = sja1105_init_l2_lookup_params(priv);
1088 rc = sja1105_init_l2_forwarding(priv);
1091 rc = sja1105_init_l2_forwarding_params(priv);
1094 rc = sja1105_init_l2_policing(priv);
1097 rc = sja1105_init_general_params(priv);
1100 rc = sja1105_init_avb_params(priv);
1103 rc = sja1110_init_pcp_remapping(priv);
1107 /* Send initial configuration to hardware via SPI */
1108 return sja1105_static_config_upload(priv);
1111 /* This is the "new way" for a MAC driver to configure its RGMII delay lines,
1112 * based on the explicit "rx-internal-delay-ps" and "tx-internal-delay-ps"
1113 * properties. It has the advantage of working with fixed links and with PHYs
1114 * that apply RGMII delays too, and the MAC driver needs not perform any
1117 * Previously we were acting upon the "phy-mode" property when we were
1118 * operating in fixed-link, basically acting as a PHY, but with a reversed
1119 * interpretation: PHY_INTERFACE_MODE_RGMII_TXID means that the MAC should
1120 * behave as if it is connected to a PHY which has applied RGMII delays in the
1121 * TX direction. So if anything, RX delays should have been added by the MAC,
1122 * but we were adding TX delays.
1124 * If the "{rx,tx}-internal-delay-ps" properties are not specified, we fall
1125 * back to the legacy behavior and apply delays on fixed-link ports based on
1126 * the reverse interpretation of the phy-mode. This is a deviation from the
1127 * expected default behavior which is to simply apply no delays. To achieve
1128 * that behavior with the new bindings, it is mandatory to specify
1129 * "{rx,tx}-internal-delay-ps" with a value of 0.
1131 static int sja1105_parse_rgmii_delays(struct sja1105_private *priv, int port,
1132 struct device_node *port_dn)
1134 phy_interface_t phy_mode = priv->phy_mode[port];
1135 struct device *dev = &priv->spidev->dev;
1136 int rx_delay = -1, tx_delay = -1;
1138 if (!phy_interface_mode_is_rgmii(phy_mode))
1141 of_property_read_u32(port_dn, "rx-internal-delay-ps", &rx_delay);
1142 of_property_read_u32(port_dn, "tx-internal-delay-ps", &tx_delay);
1144 if (rx_delay == -1 && tx_delay == -1 && priv->fixed_link[port]) {
1146 "Port %d interpreting RGMII delay settings based on \"phy-mode\" property, "
1147 "please update device tree to specify \"rx-internal-delay-ps\" and "
1148 "\"tx-internal-delay-ps\"",
1151 if (phy_mode == PHY_INTERFACE_MODE_RGMII_RXID ||
1152 phy_mode == PHY_INTERFACE_MODE_RGMII_ID)
1155 if (phy_mode == PHY_INTERFACE_MODE_RGMII_TXID ||
1156 phy_mode == PHY_INTERFACE_MODE_RGMII_ID)
1165 if ((rx_delay || tx_delay) && !priv->info->setup_rgmii_delay) {
1166 dev_err(dev, "Chip cannot apply RGMII delays\n");
1170 if ((rx_delay && rx_delay < SJA1105_RGMII_DELAY_MIN_PS) ||
1171 (tx_delay && tx_delay < SJA1105_RGMII_DELAY_MIN_PS) ||
1172 (rx_delay > SJA1105_RGMII_DELAY_MAX_PS) ||
1173 (tx_delay > SJA1105_RGMII_DELAY_MAX_PS)) {
1175 "port %d RGMII delay values out of range, must be between %d and %d ps\n",
1176 port, SJA1105_RGMII_DELAY_MIN_PS, SJA1105_RGMII_DELAY_MAX_PS);
1180 priv->rgmii_rx_delay_ps[port] = rx_delay;
1181 priv->rgmii_tx_delay_ps[port] = tx_delay;
1186 static int sja1105_parse_ports_node(struct sja1105_private *priv,
1187 struct device_node *ports_node)
1189 struct device *dev = &priv->spidev->dev;
1190 struct device_node *child;
1192 for_each_available_child_of_node(ports_node, child) {
1193 struct device_node *phy_node;
1194 phy_interface_t phy_mode;
1198 /* Get switch port number from DT */
1199 if (of_property_read_u32(child, "reg", &index) < 0) {
1200 dev_err(dev, "Port number not defined in device tree "
1201 "(property \"reg\")\n");
1206 /* Get PHY mode from DT */
1207 err = of_get_phy_mode(child, &phy_mode);
1209 dev_err(dev, "Failed to read phy-mode or "
1210 "phy-interface-type property for port %d\n",
1216 phy_node = of_parse_phandle(child, "phy-handle", 0);
1218 if (!of_phy_is_fixed_link(child)) {
1219 dev_err(dev, "phy-handle or fixed-link "
1220 "properties missing!\n");
1224 /* phy-handle is missing, but fixed-link isn't.
1225 * So it's a fixed link. Default to PHY role.
1227 priv->fixed_link[index] = true;
1229 of_node_put(phy_node);
1232 priv->phy_mode[index] = phy_mode;
1234 err = sja1105_parse_rgmii_delays(priv, index, child);
1244 static int sja1105_parse_dt(struct sja1105_private *priv)
1246 struct device *dev = &priv->spidev->dev;
1247 struct device_node *switch_node = dev->of_node;
1248 struct device_node *ports_node;
1251 ports_node = of_get_child_by_name(switch_node, "ports");
1253 ports_node = of_get_child_by_name(switch_node, "ethernet-ports");
1255 dev_err(dev, "Incorrect bindings: absent \"ports\" node\n");
1259 rc = sja1105_parse_ports_node(priv, ports_node);
1260 of_node_put(ports_node);
1265 /* Convert link speed from SJA1105 to ethtool encoding */
1266 static int sja1105_port_speed_to_ethtool(struct sja1105_private *priv,
1269 if (speed == priv->info->port_speed[SJA1105_SPEED_10MBPS])
1271 if (speed == priv->info->port_speed[SJA1105_SPEED_100MBPS])
1273 if (speed == priv->info->port_speed[SJA1105_SPEED_1000MBPS])
1275 if (speed == priv->info->port_speed[SJA1105_SPEED_2500MBPS])
1277 return SPEED_UNKNOWN;
1280 /* Set link speed in the MAC configuration for a specific port. */
1281 static int sja1105_adjust_port_config(struct sja1105_private *priv, int port,
1284 struct sja1105_mac_config_entry *mac;
1285 struct device *dev = priv->ds->dev;
1289 /* On P/Q/R/S, one can read from the device via the MAC reconfiguration
1290 * tables. On E/T, MAC reconfig tables are not readable, only writable.
1291 * We have to *know* what the MAC looks like. For the sake of keeping
1292 * the code common, we'll use the static configuration tables as a
1293 * reasonable approximation for both E/T and P/Q/R/S.
1295 mac = priv->static_config.tables[BLK_IDX_MAC_CONFIG].entries;
1297 switch (speed_mbps) {
1299 /* PHYLINK called sja1105_mac_config() to inform us about
1300 * the state->interface, but AN has not completed and the
1301 * speed is not yet valid. UM10944.pdf says that setting
1302 * SJA1105_SPEED_AUTO at runtime disables the port, so that is
1303 * ok for power consumption in case AN will never complete -
1304 * otherwise PHYLINK should come back with a new update.
1306 speed = priv->info->port_speed[SJA1105_SPEED_AUTO];
1309 speed = priv->info->port_speed[SJA1105_SPEED_10MBPS];
1312 speed = priv->info->port_speed[SJA1105_SPEED_100MBPS];
1315 speed = priv->info->port_speed[SJA1105_SPEED_1000MBPS];
1318 speed = priv->info->port_speed[SJA1105_SPEED_2500MBPS];
1321 dev_err(dev, "Invalid speed %iMbps\n", speed_mbps);
1325 /* Overwrite SJA1105_SPEED_AUTO from the static MAC configuration
1326 * table, since this will be used for the clocking setup, and we no
1327 * longer need to store it in the static config (already told hardware
1328 * we want auto during upload phase).
1329 * Actually for the SGMII port, the MAC is fixed at 1 Gbps and
1330 * we need to configure the PCS only (if even that).
1332 if (priv->phy_mode[port] == PHY_INTERFACE_MODE_SGMII)
1333 mac[port].speed = priv->info->port_speed[SJA1105_SPEED_1000MBPS];
1334 else if (priv->phy_mode[port] == PHY_INTERFACE_MODE_2500BASEX)
1335 mac[port].speed = priv->info->port_speed[SJA1105_SPEED_2500MBPS];
1337 mac[port].speed = speed;
1339 /* Write to the dynamic reconfiguration tables */
1340 rc = sja1105_dynamic_config_write(priv, BLK_IDX_MAC_CONFIG, port,
1343 dev_err(dev, "Failed to write MAC config: %d\n", rc);
1347 /* Reconfigure the PLLs for the RGMII interfaces (required 125 MHz at
1348 * gigabit, 25 MHz at 100 Mbps and 2.5 MHz at 10 Mbps). For MII and
1349 * RMII no change of the clock setup is required. Actually, changing
1350 * the clock setup does interrupt the clock signal for a certain time
1351 * which causes trouble for all PHYs relying on this signal.
1353 if (!phy_interface_mode_is_rgmii(priv->phy_mode[port]))
1356 return sja1105_clocking_setup_port(priv, port);
1359 static struct phylink_pcs *
1360 sja1105_mac_select_pcs(struct dsa_switch *ds, int port, phy_interface_t iface)
1362 struct sja1105_private *priv = ds->priv;
1363 struct dw_xpcs *xpcs = priv->xpcs[port];
1371 static void sja1105_mac_link_down(struct dsa_switch *ds, int port,
1373 phy_interface_t interface)
1375 sja1105_inhibit_tx(ds->priv, BIT(port), true);
1378 static void sja1105_mac_link_up(struct dsa_switch *ds, int port,
1380 phy_interface_t interface,
1381 struct phy_device *phydev,
1382 int speed, int duplex,
1383 bool tx_pause, bool rx_pause)
1385 struct sja1105_private *priv = ds->priv;
1387 sja1105_adjust_port_config(priv, port, speed);
1389 sja1105_inhibit_tx(priv, BIT(port), false);
1392 static void sja1105_phylink_get_caps(struct dsa_switch *ds, int port,
1393 struct phylink_config *config)
1395 struct sja1105_private *priv = ds->priv;
1396 struct sja1105_xmii_params_entry *mii;
1397 phy_interface_t phy_mode;
1399 /* This driver does not make use of the speed, duplex, pause or the
1400 * advertisement in its mac_config, so it is safe to mark this driver
1403 config->legacy_pre_march2020 = false;
1405 phy_mode = priv->phy_mode[port];
1406 if (phy_mode == PHY_INTERFACE_MODE_SGMII ||
1407 phy_mode == PHY_INTERFACE_MODE_2500BASEX) {
1408 /* Changing the PHY mode on SERDES ports is possible and makes
1409 * sense, because that is done through the XPCS. We allow
1410 * changes between SGMII and 2500base-X.
1412 if (priv->info->supports_sgmii[port])
1413 __set_bit(PHY_INTERFACE_MODE_SGMII,
1414 config->supported_interfaces);
1416 if (priv->info->supports_2500basex[port])
1417 __set_bit(PHY_INTERFACE_MODE_2500BASEX,
1418 config->supported_interfaces);
1420 /* The SJA1105 MAC programming model is through the static
1421 * config (the xMII Mode table cannot be dynamically
1422 * reconfigured), and we have to program that early.
1424 __set_bit(phy_mode, config->supported_interfaces);
1427 /* The MAC does not support pause frames, and also doesn't
1428 * support half-duplex traffic modes.
1430 config->mac_capabilities = MAC_10FD | MAC_100FD;
1432 mii = priv->static_config.tables[BLK_IDX_XMII_PARAMS].entries;
1433 if (mii->xmii_mode[port] == XMII_MODE_RGMII ||
1434 mii->xmii_mode[port] == XMII_MODE_SGMII)
1435 config->mac_capabilities |= MAC_1000FD;
1437 if (priv->info->supports_2500basex[port])
1438 config->mac_capabilities |= MAC_2500FD;
1442 sja1105_find_static_fdb_entry(struct sja1105_private *priv, int port,
1443 const struct sja1105_l2_lookup_entry *requested)
1445 struct sja1105_l2_lookup_entry *l2_lookup;
1446 struct sja1105_table *table;
1449 table = &priv->static_config.tables[BLK_IDX_L2_LOOKUP];
1450 l2_lookup = table->entries;
1452 for (i = 0; i < table->entry_count; i++)
1453 if (l2_lookup[i].macaddr == requested->macaddr &&
1454 l2_lookup[i].vlanid == requested->vlanid &&
1455 l2_lookup[i].destports & BIT(port))
1461 /* We want FDB entries added statically through the bridge command to persist
1462 * across switch resets, which are a common thing during normal SJA1105
1463 * operation. So we have to back them up in the static configuration tables
1464 * and hence apply them on next static config upload... yay!
1467 sja1105_static_fdb_change(struct sja1105_private *priv, int port,
1468 const struct sja1105_l2_lookup_entry *requested,
1471 struct sja1105_l2_lookup_entry *l2_lookup;
1472 struct sja1105_table *table;
1475 table = &priv->static_config.tables[BLK_IDX_L2_LOOKUP];
1477 match = sja1105_find_static_fdb_entry(priv, port, requested);
1479 /* Can't delete a missing entry. */
1483 /* No match => new entry */
1484 rc = sja1105_table_resize(table, table->entry_count + 1);
1488 match = table->entry_count - 1;
1491 /* Assign pointer after the resize (it may be new memory) */
1492 l2_lookup = table->entries;
1495 * If the job was to add this FDB entry, it's already done (mostly
1496 * anyway, since the port forwarding mask may have changed, case in
1497 * which we update it).
1498 * Otherwise we have to delete it.
1501 l2_lookup[match] = *requested;
1505 /* To remove, the strategy is to overwrite the element with
1506 * the last one, and then reduce the array size by 1
1508 l2_lookup[match] = l2_lookup[table->entry_count - 1];
1509 return sja1105_table_resize(table, table->entry_count - 1);
1512 /* First-generation switches have a 4-way set associative TCAM that
1513 * holds the FDB entries. An FDB index spans from 0 to 1023 and is comprised of
1514 * a "bin" (grouping of 4 entries) and a "way" (an entry within a bin).
1515 * For the placement of a newly learnt FDB entry, the switch selects the bin
1516 * based on a hash function, and the way within that bin incrementally.
1518 static int sja1105et_fdb_index(int bin, int way)
1520 return bin * SJA1105ET_FDB_BIN_SIZE + way;
1523 static int sja1105et_is_fdb_entry_in_bin(struct sja1105_private *priv, int bin,
1524 const u8 *addr, u16 vid,
1525 struct sja1105_l2_lookup_entry *match,
1530 for (way = 0; way < SJA1105ET_FDB_BIN_SIZE; way++) {
1531 struct sja1105_l2_lookup_entry l2_lookup = {0};
1532 int index = sja1105et_fdb_index(bin, way);
1534 /* Skip unused entries, optionally marking them
1535 * into the return value
1537 if (sja1105_dynamic_config_read(priv, BLK_IDX_L2_LOOKUP,
1538 index, &l2_lookup)) {
1544 if (l2_lookup.macaddr == ether_addr_to_u64(addr) &&
1545 l2_lookup.vlanid == vid) {
1551 /* Return an invalid entry index if not found */
1555 int sja1105et_fdb_add(struct dsa_switch *ds, int port,
1556 const unsigned char *addr, u16 vid)
1558 struct sja1105_l2_lookup_entry l2_lookup = {0}, tmp;
1559 struct sja1105_private *priv = ds->priv;
1560 struct device *dev = ds->dev;
1561 int last_unused = -1;
1565 bin = sja1105et_fdb_hash(priv, addr, vid);
1567 way = sja1105et_is_fdb_entry_in_bin(priv, bin, addr, vid,
1568 &l2_lookup, &last_unused);
1570 /* We have an FDB entry. Is our port in the destination
1571 * mask? If yes, we need to do nothing. If not, we need
1572 * to rewrite the entry by adding this port to it.
1574 if ((l2_lookup.destports & BIT(port)) && l2_lookup.lockeds)
1576 l2_lookup.destports |= BIT(port);
1578 int index = sja1105et_fdb_index(bin, way);
1580 /* We don't have an FDB entry. We construct a new one and
1581 * try to find a place for it within the FDB table.
1583 l2_lookup.macaddr = ether_addr_to_u64(addr);
1584 l2_lookup.destports = BIT(port);
1585 l2_lookup.vlanid = vid;
1587 if (last_unused >= 0) {
1590 /* Bin is full, need to evict somebody.
1591 * Choose victim at random. If you get these messages
1592 * often, you may need to consider changing the
1593 * distribution function:
1594 * static_config[BLK_IDX_L2_LOOKUP_PARAMS].entries->poly
1596 get_random_bytes(&way, sizeof(u8));
1597 way %= SJA1105ET_FDB_BIN_SIZE;
1598 dev_warn(dev, "Warning, FDB bin %d full while adding entry for %pM. Evicting entry %u.\n",
1601 sja1105_dynamic_config_write(priv, BLK_IDX_L2_LOOKUP,
1602 index, NULL, false);
1605 l2_lookup.lockeds = true;
1606 l2_lookup.index = sja1105et_fdb_index(bin, way);
1608 rc = sja1105_dynamic_config_write(priv, BLK_IDX_L2_LOOKUP,
1609 l2_lookup.index, &l2_lookup,
1614 /* Invalidate a dynamically learned entry if that exists */
1615 start = sja1105et_fdb_index(bin, 0);
1616 end = sja1105et_fdb_index(bin, way);
1618 for (i = start; i < end; i++) {
1619 rc = sja1105_dynamic_config_read(priv, BLK_IDX_L2_LOOKUP,
1626 if (tmp.macaddr != ether_addr_to_u64(addr) || tmp.vlanid != vid)
1629 rc = sja1105_dynamic_config_write(priv, BLK_IDX_L2_LOOKUP,
1637 return sja1105_static_fdb_change(priv, port, &l2_lookup, true);
1640 int sja1105et_fdb_del(struct dsa_switch *ds, int port,
1641 const unsigned char *addr, u16 vid)
1643 struct sja1105_l2_lookup_entry l2_lookup = {0};
1644 struct sja1105_private *priv = ds->priv;
1645 int index, bin, way, rc;
1648 bin = sja1105et_fdb_hash(priv, addr, vid);
1649 way = sja1105et_is_fdb_entry_in_bin(priv, bin, addr, vid,
1653 index = sja1105et_fdb_index(bin, way);
1655 /* We have an FDB entry. Is our port in the destination mask? If yes,
1656 * we need to remove it. If the resulting port mask becomes empty, we
1657 * need to completely evict the FDB entry.
1658 * Otherwise we just write it back.
1660 l2_lookup.destports &= ~BIT(port);
1662 if (l2_lookup.destports)
1667 rc = sja1105_dynamic_config_write(priv, BLK_IDX_L2_LOOKUP,
1668 index, &l2_lookup, keep);
1672 return sja1105_static_fdb_change(priv, port, &l2_lookup, keep);
1675 int sja1105pqrs_fdb_add(struct dsa_switch *ds, int port,
1676 const unsigned char *addr, u16 vid)
1678 struct sja1105_l2_lookup_entry l2_lookup = {0}, tmp;
1679 struct sja1105_private *priv = ds->priv;
1682 /* Search for an existing entry in the FDB table */
1683 l2_lookup.macaddr = ether_addr_to_u64(addr);
1684 l2_lookup.vlanid = vid;
1685 l2_lookup.mask_macaddr = GENMASK_ULL(ETH_ALEN * 8 - 1, 0);
1686 l2_lookup.mask_vlanid = VLAN_VID_MASK;
1687 l2_lookup.destports = BIT(port);
1691 rc = sja1105_dynamic_config_read(priv, BLK_IDX_L2_LOOKUP,
1692 SJA1105_SEARCH, &tmp);
1693 if (rc == 0 && tmp.index != SJA1105_MAX_L2_LOOKUP_COUNT - 1) {
1694 /* Found a static entry and this port is already in the entry's
1695 * port mask => job done
1697 if ((tmp.destports & BIT(port)) && tmp.lockeds)
1702 /* l2_lookup.index is populated by the switch in case it
1705 l2_lookup.destports |= BIT(port);
1706 goto skip_finding_an_index;
1709 /* Not found, so try to find an unused spot in the FDB.
1710 * This is slightly inefficient because the strategy is knock-knock at
1711 * every possible position from 0 to 1023.
1713 for (i = 0; i < SJA1105_MAX_L2_LOOKUP_COUNT; i++) {
1714 rc = sja1105_dynamic_config_read(priv, BLK_IDX_L2_LOOKUP,
1719 if (i == SJA1105_MAX_L2_LOOKUP_COUNT) {
1720 dev_err(ds->dev, "FDB is full, cannot add entry.\n");
1723 l2_lookup.index = i;
1725 skip_finding_an_index:
1726 l2_lookup.lockeds = true;
1728 rc = sja1105_dynamic_config_write(priv, BLK_IDX_L2_LOOKUP,
1729 l2_lookup.index, &l2_lookup,
1734 /* The switch learns dynamic entries and looks up the FDB left to
1735 * right. It is possible that our addition was concurrent with the
1736 * dynamic learning of the same address, so now that the static entry
1737 * has been installed, we are certain that address learning for this
1738 * particular address has been turned off, so the dynamic entry either
1739 * is in the FDB at an index smaller than the static one, or isn't (it
1740 * can also be at a larger index, but in that case it is inactive
1741 * because the static FDB entry will match first, and the dynamic one
1742 * will eventually age out). Search for a dynamically learned address
1743 * prior to our static one and invalidate it.
1747 rc = sja1105_dynamic_config_read(priv, BLK_IDX_L2_LOOKUP,
1748 SJA1105_SEARCH, &tmp);
1751 "port %d failed to read back entry for %pM vid %d: %pe\n",
1752 port, addr, vid, ERR_PTR(rc));
1756 if (tmp.index < l2_lookup.index) {
1757 rc = sja1105_dynamic_config_write(priv, BLK_IDX_L2_LOOKUP,
1758 tmp.index, NULL, false);
1763 return sja1105_static_fdb_change(priv, port, &l2_lookup, true);
1766 int sja1105pqrs_fdb_del(struct dsa_switch *ds, int port,
1767 const unsigned char *addr, u16 vid)
1769 struct sja1105_l2_lookup_entry l2_lookup = {0};
1770 struct sja1105_private *priv = ds->priv;
1774 l2_lookup.macaddr = ether_addr_to_u64(addr);
1775 l2_lookup.vlanid = vid;
1776 l2_lookup.mask_macaddr = GENMASK_ULL(ETH_ALEN * 8 - 1, 0);
1777 l2_lookup.mask_vlanid = VLAN_VID_MASK;
1778 l2_lookup.destports = BIT(port);
1780 rc = sja1105_dynamic_config_read(priv, BLK_IDX_L2_LOOKUP,
1781 SJA1105_SEARCH, &l2_lookup);
1785 l2_lookup.destports &= ~BIT(port);
1787 /* Decide whether we remove just this port from the FDB entry,
1788 * or if we remove it completely.
1790 if (l2_lookup.destports)
1795 rc = sja1105_dynamic_config_write(priv, BLK_IDX_L2_LOOKUP,
1796 l2_lookup.index, &l2_lookup, keep);
1800 return sja1105_static_fdb_change(priv, port, &l2_lookup, keep);
1803 static int sja1105_fdb_add(struct dsa_switch *ds, int port,
1804 const unsigned char *addr, u16 vid,
1807 struct sja1105_private *priv = ds->priv;
1812 vid = dsa_tag_8021q_standalone_vid(db.dp);
1815 vid = dsa_tag_8021q_bridge_vid(db.bridge.num);
1822 return priv->info->fdb_add_cmd(ds, port, addr, vid);
1825 static int sja1105_fdb_del(struct dsa_switch *ds, int port,
1826 const unsigned char *addr, u16 vid,
1829 struct sja1105_private *priv = ds->priv;
1834 vid = dsa_tag_8021q_standalone_vid(db.dp);
1837 vid = dsa_tag_8021q_bridge_vid(db.bridge.num);
1844 return priv->info->fdb_del_cmd(ds, port, addr, vid);
1847 static int sja1105_fdb_dump(struct dsa_switch *ds, int port,
1848 dsa_fdb_dump_cb_t *cb, void *data)
1850 struct sja1105_private *priv = ds->priv;
1851 struct device *dev = ds->dev;
1854 for (i = 0; i < SJA1105_MAX_L2_LOOKUP_COUNT; i++) {
1855 struct sja1105_l2_lookup_entry l2_lookup = {0};
1856 u8 macaddr[ETH_ALEN];
1859 rc = sja1105_dynamic_config_read(priv, BLK_IDX_L2_LOOKUP,
1861 /* No fdb entry at i, not an issue */
1865 dev_err(dev, "Failed to dump FDB: %d\n", rc);
1869 /* FDB dump callback is per port. This means we have to
1870 * disregard a valid entry if it's not for this port, even if
1871 * only to revisit it later. This is inefficient because the
1872 * 1024-sized FDB table needs to be traversed 4 times through
1873 * SPI during a 'bridge fdb show' command.
1875 if (!(l2_lookup.destports & BIT(port)))
1878 /* We need to hide the FDB entry for unknown multicast */
1879 if (l2_lookup.macaddr == SJA1105_UNKNOWN_MULTICAST &&
1880 l2_lookup.mask_macaddr == SJA1105_UNKNOWN_MULTICAST)
1883 u64_to_ether_addr(l2_lookup.macaddr, macaddr);
1885 /* We need to hide the dsa_8021q VLANs from the user. */
1886 if (vid_is_dsa_8021q(l2_lookup.vlanid))
1887 l2_lookup.vlanid = 0;
1888 rc = cb(macaddr, l2_lookup.vlanid, l2_lookup.lockeds, data);
1895 static void sja1105_fast_age(struct dsa_switch *ds, int port)
1897 struct dsa_port *dp = dsa_to_port(ds, port);
1898 struct sja1105_private *priv = ds->priv;
1899 struct dsa_db db = {
1900 .type = DSA_DB_BRIDGE,
1902 .dev = dsa_port_bridge_dev_get(dp),
1903 .num = dsa_port_bridge_num_get(dp),
1908 for (i = 0; i < SJA1105_MAX_L2_LOOKUP_COUNT; i++) {
1909 struct sja1105_l2_lookup_entry l2_lookup = {0};
1910 u8 macaddr[ETH_ALEN];
1913 rc = sja1105_dynamic_config_read(priv, BLK_IDX_L2_LOOKUP,
1915 /* No fdb entry at i, not an issue */
1919 dev_err(ds->dev, "Failed to read FDB: %pe\n",
1924 if (!(l2_lookup.destports & BIT(port)))
1927 /* Don't delete static FDB entries */
1928 if (l2_lookup.lockeds)
1931 u64_to_ether_addr(l2_lookup.macaddr, macaddr);
1933 rc = sja1105_fdb_del(ds, port, macaddr, l2_lookup.vlanid, db);
1936 "Failed to delete FDB entry %pM vid %lld: %pe\n",
1937 macaddr, l2_lookup.vlanid, ERR_PTR(rc));
1943 static int sja1105_mdb_add(struct dsa_switch *ds, int port,
1944 const struct switchdev_obj_port_mdb *mdb,
1947 return sja1105_fdb_add(ds, port, mdb->addr, mdb->vid, db);
1950 static int sja1105_mdb_del(struct dsa_switch *ds, int port,
1951 const struct switchdev_obj_port_mdb *mdb,
1954 return sja1105_fdb_del(ds, port, mdb->addr, mdb->vid, db);
1957 /* Common function for unicast and broadcast flood configuration.
1958 * Flooding is configured between each {ingress, egress} port pair, and since
1959 * the bridge's semantics are those of "egress flooding", it means we must
1960 * enable flooding towards this port from all ingress ports that are in the
1961 * same forwarding domain.
1963 static int sja1105_manage_flood_domains(struct sja1105_private *priv)
1965 struct sja1105_l2_forwarding_entry *l2_fwd;
1966 struct dsa_switch *ds = priv->ds;
1969 l2_fwd = priv->static_config.tables[BLK_IDX_L2_FORWARDING].entries;
1971 for (from = 0; from < ds->num_ports; from++) {
1972 u64 fl_domain = 0, bc_domain = 0;
1974 for (to = 0; to < priv->ds->num_ports; to++) {
1975 if (!sja1105_can_forward(l2_fwd, from, to))
1978 if (priv->ucast_egress_floods & BIT(to))
1979 fl_domain |= BIT(to);
1980 if (priv->bcast_egress_floods & BIT(to))
1981 bc_domain |= BIT(to);
1984 /* Nothing changed, nothing to do */
1985 if (l2_fwd[from].fl_domain == fl_domain &&
1986 l2_fwd[from].bc_domain == bc_domain)
1989 l2_fwd[from].fl_domain = fl_domain;
1990 l2_fwd[from].bc_domain = bc_domain;
1992 rc = sja1105_dynamic_config_write(priv, BLK_IDX_L2_FORWARDING,
1993 from, &l2_fwd[from], true);
2001 static int sja1105_bridge_member(struct dsa_switch *ds, int port,
2002 struct dsa_bridge bridge, bool member)
2004 struct sja1105_l2_forwarding_entry *l2_fwd;
2005 struct sja1105_private *priv = ds->priv;
2008 l2_fwd = priv->static_config.tables[BLK_IDX_L2_FORWARDING].entries;
2010 for (i = 0; i < ds->num_ports; i++) {
2011 /* Add this port to the forwarding matrix of the
2012 * other ports in the same bridge, and viceversa.
2014 if (!dsa_is_user_port(ds, i))
2016 /* For the ports already under the bridge, only one thing needs
2017 * to be done, and that is to add this port to their
2018 * reachability domain. So we can perform the SPI write for
2019 * them immediately. However, for this port itself (the one
2020 * that is new to the bridge), we need to add all other ports
2021 * to its reachability domain. So we do that incrementally in
2022 * this loop, and perform the SPI write only at the end, once
2023 * the domain contains all other bridge ports.
2027 if (!dsa_port_offloads_bridge(dsa_to_port(ds, i), &bridge))
2029 sja1105_port_allow_traffic(l2_fwd, i, port, member);
2030 sja1105_port_allow_traffic(l2_fwd, port, i, member);
2032 rc = sja1105_dynamic_config_write(priv, BLK_IDX_L2_FORWARDING,
2033 i, &l2_fwd[i], true);
2038 rc = sja1105_dynamic_config_write(priv, BLK_IDX_L2_FORWARDING,
2039 port, &l2_fwd[port], true);
2043 rc = sja1105_commit_pvid(ds, port);
2047 return sja1105_manage_flood_domains(priv);
2050 static void sja1105_bridge_stp_state_set(struct dsa_switch *ds, int port,
2053 struct dsa_port *dp = dsa_to_port(ds, port);
2054 struct sja1105_private *priv = ds->priv;
2055 struct sja1105_mac_config_entry *mac;
2057 mac = priv->static_config.tables[BLK_IDX_MAC_CONFIG].entries;
2060 case BR_STATE_DISABLED:
2061 case BR_STATE_BLOCKING:
2062 /* From UM10944 description of DRPDTAG (why put this there?):
2063 * "Management traffic flows to the port regardless of the state
2064 * of the INGRESS flag". So BPDUs are still be allowed to pass.
2065 * At the moment no difference between DISABLED and BLOCKING.
2067 mac[port].ingress = false;
2068 mac[port].egress = false;
2069 mac[port].dyn_learn = false;
2071 case BR_STATE_LISTENING:
2072 mac[port].ingress = true;
2073 mac[port].egress = false;
2074 mac[port].dyn_learn = false;
2076 case BR_STATE_LEARNING:
2077 mac[port].ingress = true;
2078 mac[port].egress = false;
2079 mac[port].dyn_learn = dp->learning;
2081 case BR_STATE_FORWARDING:
2082 mac[port].ingress = true;
2083 mac[port].egress = true;
2084 mac[port].dyn_learn = dp->learning;
2087 dev_err(ds->dev, "invalid STP state: %d\n", state);
2091 sja1105_dynamic_config_write(priv, BLK_IDX_MAC_CONFIG, port,
2095 static int sja1105_bridge_join(struct dsa_switch *ds, int port,
2096 struct dsa_bridge bridge,
2097 bool *tx_fwd_offload,
2098 struct netlink_ext_ack *extack)
2102 rc = sja1105_bridge_member(ds, port, bridge, true);
2106 rc = dsa_tag_8021q_bridge_join(ds, port, bridge);
2108 sja1105_bridge_member(ds, port, bridge, false);
2112 *tx_fwd_offload = true;
2117 static void sja1105_bridge_leave(struct dsa_switch *ds, int port,
2118 struct dsa_bridge bridge)
2120 dsa_tag_8021q_bridge_leave(ds, port, bridge);
2121 sja1105_bridge_member(ds, port, bridge, false);
2124 #define BYTES_PER_KBIT (1000LL / 8)
2126 static int sja1105_find_unused_cbs_shaper(struct sja1105_private *priv)
2130 for (i = 0; i < priv->info->num_cbs_shapers; i++)
2131 if (!priv->cbs[i].idle_slope && !priv->cbs[i].send_slope)
2137 static int sja1105_delete_cbs_shaper(struct sja1105_private *priv, int port,
2142 for (i = 0; i < priv->info->num_cbs_shapers; i++) {
2143 struct sja1105_cbs_entry *cbs = &priv->cbs[i];
2145 if (cbs->port == port && cbs->prio == prio) {
2146 memset(cbs, 0, sizeof(*cbs));
2147 return sja1105_dynamic_config_write(priv, BLK_IDX_CBS,
2155 static int sja1105_setup_tc_cbs(struct dsa_switch *ds, int port,
2156 struct tc_cbs_qopt_offload *offload)
2158 struct sja1105_private *priv = ds->priv;
2159 struct sja1105_cbs_entry *cbs;
2162 if (!offload->enable)
2163 return sja1105_delete_cbs_shaper(priv, port, offload->queue);
2165 index = sja1105_find_unused_cbs_shaper(priv);
2169 cbs = &priv->cbs[index];
2171 cbs->prio = offload->queue;
2172 /* locredit and sendslope are negative by definition. In hardware,
2173 * positive values must be provided, and the negative sign is implicit.
2175 cbs->credit_hi = offload->hicredit;
2176 cbs->credit_lo = abs(offload->locredit);
2177 /* User space is in kbits/sec, hardware in bytes/sec */
2178 cbs->idle_slope = offload->idleslope * BYTES_PER_KBIT;
2179 cbs->send_slope = abs(offload->sendslope * BYTES_PER_KBIT);
2180 /* Convert the negative values from 64-bit 2's complement
2181 * to 32-bit 2's complement (for the case of 0x80000000 whose
2182 * negative is still negative).
2184 cbs->credit_lo &= GENMASK_ULL(31, 0);
2185 cbs->send_slope &= GENMASK_ULL(31, 0);
2187 return sja1105_dynamic_config_write(priv, BLK_IDX_CBS, index, cbs,
2191 static int sja1105_reload_cbs(struct sja1105_private *priv)
2195 /* The credit based shapers are only allocated if
2196 * CONFIG_NET_SCH_CBS is enabled.
2201 for (i = 0; i < priv->info->num_cbs_shapers; i++) {
2202 struct sja1105_cbs_entry *cbs = &priv->cbs[i];
2204 if (!cbs->idle_slope && !cbs->send_slope)
2207 rc = sja1105_dynamic_config_write(priv, BLK_IDX_CBS, i, cbs,
2216 static const char * const sja1105_reset_reasons[] = {
2217 [SJA1105_VLAN_FILTERING] = "VLAN filtering",
2218 [SJA1105_RX_HWTSTAMPING] = "RX timestamping",
2219 [SJA1105_AGEING_TIME] = "Ageing time",
2220 [SJA1105_SCHEDULING] = "Time-aware scheduling",
2221 [SJA1105_BEST_EFFORT_POLICING] = "Best-effort policing",
2222 [SJA1105_VIRTUAL_LINKS] = "Virtual links",
2225 /* For situations where we need to change a setting at runtime that is only
2226 * available through the static configuration, resetting the switch in order
2227 * to upload the new static config is unavoidable. Back up the settings we
2228 * modify at runtime (currently only MAC) and restore them after uploading,
2229 * such that this operation is relatively seamless.
2231 int sja1105_static_config_reload(struct sja1105_private *priv,
2232 enum sja1105_reset_reason reason)
2234 struct ptp_system_timestamp ptp_sts_before;
2235 struct ptp_system_timestamp ptp_sts_after;
2236 int speed_mbps[SJA1105_MAX_NUM_PORTS];
2237 u16 bmcr[SJA1105_MAX_NUM_PORTS] = {0};
2238 struct sja1105_mac_config_entry *mac;
2239 struct dsa_switch *ds = priv->ds;
2245 mutex_lock(&priv->mgmt_lock);
2247 mac = priv->static_config.tables[BLK_IDX_MAC_CONFIG].entries;
2249 /* Back up the dynamic link speed changed by sja1105_adjust_port_config
2250 * in order to temporarily restore it to SJA1105_SPEED_AUTO - which the
2251 * switch wants to see in the static config in order to allow us to
2252 * change it through the dynamic interface later.
2254 for (i = 0; i < ds->num_ports; i++) {
2255 u32 reg_addr = mdiobus_c45_addr(MDIO_MMD_VEND2, MDIO_CTRL1);
2257 speed_mbps[i] = sja1105_port_speed_to_ethtool(priv,
2259 mac[i].speed = priv->info->port_speed[SJA1105_SPEED_AUTO];
2262 bmcr[i] = mdiobus_read(priv->mdio_pcs, i, reg_addr);
2265 /* No PTP operations can run right now */
2266 mutex_lock(&priv->ptp_data.lock);
2268 rc = __sja1105_ptp_gettimex(ds, &now, &ptp_sts_before);
2270 mutex_unlock(&priv->ptp_data.lock);
2274 /* Reset switch and send updated static configuration */
2275 rc = sja1105_static_config_upload(priv);
2277 mutex_unlock(&priv->ptp_data.lock);
2281 rc = __sja1105_ptp_settime(ds, 0, &ptp_sts_after);
2283 mutex_unlock(&priv->ptp_data.lock);
2287 t1 = timespec64_to_ns(&ptp_sts_before.pre_ts);
2288 t2 = timespec64_to_ns(&ptp_sts_before.post_ts);
2289 t3 = timespec64_to_ns(&ptp_sts_after.pre_ts);
2290 t4 = timespec64_to_ns(&ptp_sts_after.post_ts);
2291 /* Mid point, corresponds to pre-reset PTPCLKVAL */
2292 t12 = t1 + (t2 - t1) / 2;
2293 /* Mid point, corresponds to post-reset PTPCLKVAL, aka 0 */
2294 t34 = t3 + (t4 - t3) / 2;
2295 /* Advance PTPCLKVAL by the time it took since its readout */
2298 __sja1105_ptp_adjtime(ds, now);
2300 mutex_unlock(&priv->ptp_data.lock);
2302 dev_info(priv->ds->dev,
2303 "Reset switch and programmed static config. Reason: %s\n",
2304 sja1105_reset_reasons[reason]);
2306 /* Configure the CGU (PLLs) for MII and RMII PHYs.
2307 * For these interfaces there is no dynamic configuration
2308 * needed, since PLLs have same settings at all speeds.
2310 if (priv->info->clocking_setup) {
2311 rc = priv->info->clocking_setup(priv);
2316 for (i = 0; i < ds->num_ports; i++) {
2317 struct dw_xpcs *xpcs = priv->xpcs[i];
2320 rc = sja1105_adjust_port_config(priv, i, speed_mbps[i]);
2327 if (bmcr[i] & BMCR_ANENABLE)
2328 mode = MLO_AN_INBAND;
2329 else if (priv->fixed_link[i])
2330 mode = MLO_AN_FIXED;
2334 rc = xpcs_do_config(xpcs, priv->phy_mode[i], mode);
2338 if (!phylink_autoneg_inband(mode)) {
2339 int speed = SPEED_UNKNOWN;
2341 if (priv->phy_mode[i] == PHY_INTERFACE_MODE_2500BASEX)
2343 else if (bmcr[i] & BMCR_SPEED1000)
2345 else if (bmcr[i] & BMCR_SPEED100)
2350 xpcs_link_up(&xpcs->pcs, mode, priv->phy_mode[i],
2351 speed, DUPLEX_FULL);
2355 rc = sja1105_reload_cbs(priv);
2359 mutex_unlock(&priv->mgmt_lock);
2364 static enum dsa_tag_protocol
2365 sja1105_get_tag_protocol(struct dsa_switch *ds, int port,
2366 enum dsa_tag_protocol mp)
2368 struct sja1105_private *priv = ds->priv;
2370 return priv->info->tag_proto;
2373 /* The TPID setting belongs to the General Parameters table,
2374 * which can only be partially reconfigured at runtime (and not the TPID).
2375 * So a switch reset is required.
2377 int sja1105_vlan_filtering(struct dsa_switch *ds, int port, bool enabled,
2378 struct netlink_ext_ack *extack)
2380 struct sja1105_general_params_entry *general_params;
2381 struct sja1105_private *priv = ds->priv;
2382 struct sja1105_table *table;
2383 struct sja1105_rule *rule;
2387 list_for_each_entry(rule, &priv->flow_block.rules, list) {
2388 if (rule->type == SJA1105_RULE_VL) {
2389 NL_SET_ERR_MSG_MOD(extack,
2390 "Cannot change VLAN filtering with active VL rules");
2396 /* Enable VLAN filtering. */
2398 tpid2 = ETH_P_8021AD;
2400 /* Disable VLAN filtering. */
2401 tpid = ETH_P_SJA1105;
2402 tpid2 = ETH_P_SJA1105;
2405 table = &priv->static_config.tables[BLK_IDX_GENERAL_PARAMS];
2406 general_params = table->entries;
2407 /* EtherType used to identify inner tagged (C-tag) VLAN traffic */
2408 general_params->tpid = tpid;
2409 /* EtherType used to identify outer tagged (S-tag) VLAN traffic */
2410 general_params->tpid2 = tpid2;
2411 /* When VLAN filtering is on, we need to at least be able to
2412 * decode management traffic through the "backup plan".
2414 general_params->incl_srcpt1 = enabled;
2415 general_params->incl_srcpt0 = enabled;
2417 for (port = 0; port < ds->num_ports; port++) {
2418 if (dsa_is_unused_port(ds, port))
2421 rc = sja1105_commit_pvid(ds, port);
2426 rc = sja1105_static_config_reload(priv, SJA1105_VLAN_FILTERING);
2428 NL_SET_ERR_MSG_MOD(extack, "Failed to change VLAN Ethertype");
2433 static int sja1105_vlan_add(struct sja1105_private *priv, int port, u16 vid,
2434 u16 flags, bool allowed_ingress)
2436 struct sja1105_vlan_lookup_entry *vlan;
2437 struct sja1105_table *table;
2440 table = &priv->static_config.tables[BLK_IDX_VLAN_LOOKUP];
2442 match = sja1105_is_vlan_configured(priv, vid);
2444 rc = sja1105_table_resize(table, table->entry_count + 1);
2447 match = table->entry_count - 1;
2450 /* Assign pointer after the resize (it's new memory) */
2451 vlan = table->entries;
2453 vlan[match].type_entry = SJA1110_VLAN_D_TAG;
2454 vlan[match].vlanid = vid;
2455 vlan[match].vlan_bc |= BIT(port);
2457 if (allowed_ingress)
2458 vlan[match].vmemb_port |= BIT(port);
2460 vlan[match].vmemb_port &= ~BIT(port);
2462 if (flags & BRIDGE_VLAN_INFO_UNTAGGED)
2463 vlan[match].tag_port &= ~BIT(port);
2465 vlan[match].tag_port |= BIT(port);
2467 return sja1105_dynamic_config_write(priv, BLK_IDX_VLAN_LOOKUP, vid,
2468 &vlan[match], true);
2471 static int sja1105_vlan_del(struct sja1105_private *priv, int port, u16 vid)
2473 struct sja1105_vlan_lookup_entry *vlan;
2474 struct sja1105_table *table;
2478 table = &priv->static_config.tables[BLK_IDX_VLAN_LOOKUP];
2480 match = sja1105_is_vlan_configured(priv, vid);
2481 /* Can't delete a missing entry. */
2485 /* Assign pointer after the resize (it's new memory) */
2486 vlan = table->entries;
2488 vlan[match].vlanid = vid;
2489 vlan[match].vlan_bc &= ~BIT(port);
2490 vlan[match].vmemb_port &= ~BIT(port);
2491 /* Also unset tag_port, just so we don't have a confusing bitmap
2492 * (no practical purpose).
2494 vlan[match].tag_port &= ~BIT(port);
2496 /* If there's no port left as member of this VLAN,
2497 * it's time for it to go.
2499 if (!vlan[match].vmemb_port)
2502 rc = sja1105_dynamic_config_write(priv, BLK_IDX_VLAN_LOOKUP, vid,
2503 &vlan[match], keep);
2508 return sja1105_table_delete_entry(table, match);
2513 static int sja1105_bridge_vlan_add(struct dsa_switch *ds, int port,
2514 const struct switchdev_obj_port_vlan *vlan,
2515 struct netlink_ext_ack *extack)
2517 struct sja1105_private *priv = ds->priv;
2518 u16 flags = vlan->flags;
2521 /* Be sure to deny alterations to the configuration done by tag_8021q.
2523 if (vid_is_dsa_8021q(vlan->vid)) {
2524 NL_SET_ERR_MSG_MOD(extack,
2525 "Range 3072-4095 reserved for dsa_8021q operation");
2529 /* Always install bridge VLANs as egress-tagged on CPU and DSA ports */
2530 if (dsa_is_cpu_port(ds, port) || dsa_is_dsa_port(ds, port))
2533 rc = sja1105_vlan_add(priv, port, vlan->vid, flags, true);
2537 if (vlan->flags & BRIDGE_VLAN_INFO_PVID)
2538 priv->bridge_pvid[port] = vlan->vid;
2540 return sja1105_commit_pvid(ds, port);
2543 static int sja1105_bridge_vlan_del(struct dsa_switch *ds, int port,
2544 const struct switchdev_obj_port_vlan *vlan)
2546 struct sja1105_private *priv = ds->priv;
2549 rc = sja1105_vlan_del(priv, port, vlan->vid);
2553 /* In case the pvid was deleted, make sure that untagged packets will
2556 return sja1105_commit_pvid(ds, port);
2559 static int sja1105_dsa_8021q_vlan_add(struct dsa_switch *ds, int port, u16 vid,
2562 struct sja1105_private *priv = ds->priv;
2563 bool allowed_ingress = true;
2566 /* Prevent attackers from trying to inject a DSA tag from
2567 * the outside world.
2569 if (dsa_is_user_port(ds, port))
2570 allowed_ingress = false;
2572 rc = sja1105_vlan_add(priv, port, vid, flags, allowed_ingress);
2576 if (flags & BRIDGE_VLAN_INFO_PVID)
2577 priv->tag_8021q_pvid[port] = vid;
2579 return sja1105_commit_pvid(ds, port);
2582 static int sja1105_dsa_8021q_vlan_del(struct dsa_switch *ds, int port, u16 vid)
2584 struct sja1105_private *priv = ds->priv;
2586 return sja1105_vlan_del(priv, port, vid);
2589 static int sja1105_prechangeupper(struct dsa_switch *ds, int port,
2590 struct netdev_notifier_changeupper_info *info)
2592 struct netlink_ext_ack *extack = info->info.extack;
2593 struct net_device *upper = info->upper_dev;
2594 struct dsa_switch_tree *dst = ds->dst;
2595 struct dsa_port *dp;
2597 if (is_vlan_dev(upper)) {
2598 NL_SET_ERR_MSG_MOD(extack, "8021q uppers are not supported");
2602 if (netif_is_bridge_master(upper)) {
2603 list_for_each_entry(dp, &dst->ports, list) {
2604 struct net_device *br = dsa_port_bridge_dev_get(dp);
2606 if (br && br != upper && br_vlan_enabled(br)) {
2607 NL_SET_ERR_MSG_MOD(extack,
2608 "Only one VLAN-aware bridge is supported");
2617 static int sja1105_mgmt_xmit(struct dsa_switch *ds, int port, int slot,
2618 struct sk_buff *skb, bool takets)
2620 struct sja1105_mgmt_entry mgmt_route = {0};
2621 struct sja1105_private *priv = ds->priv;
2628 mgmt_route.macaddr = ether_addr_to_u64(hdr->h_dest);
2629 mgmt_route.destports = BIT(port);
2630 mgmt_route.enfport = 1;
2631 mgmt_route.tsreg = 0;
2632 mgmt_route.takets = takets;
2634 rc = sja1105_dynamic_config_write(priv, BLK_IDX_MGMT_ROUTE,
2635 slot, &mgmt_route, true);
2641 /* Transfer skb to the host port. */
2642 dsa_enqueue_skb(skb, dsa_to_port(ds, port)->slave);
2644 /* Wait until the switch has processed the frame */
2646 rc = sja1105_dynamic_config_read(priv, BLK_IDX_MGMT_ROUTE,
2649 dev_err_ratelimited(priv->ds->dev,
2650 "failed to poll for mgmt route\n");
2654 /* UM10944: The ENFPORT flag of the respective entry is
2655 * cleared when a match is found. The host can use this
2656 * flag as an acknowledgment.
2659 } while (mgmt_route.enfport && --timeout);
2662 /* Clean up the management route so that a follow-up
2663 * frame may not match on it by mistake.
2664 * This is only hardware supported on P/Q/R/S - on E/T it is
2665 * a no-op and we are silently discarding the -EOPNOTSUPP.
2667 sja1105_dynamic_config_write(priv, BLK_IDX_MGMT_ROUTE,
2668 slot, &mgmt_route, false);
2669 dev_err_ratelimited(priv->ds->dev, "xmit timed out\n");
2672 return NETDEV_TX_OK;
2675 #define work_to_xmit_work(w) \
2676 container_of((w), struct sja1105_deferred_xmit_work, work)
2678 /* Deferred work is unfortunately necessary because setting up the management
2679 * route cannot be done from atomit context (SPI transfer takes a sleepable
2682 static void sja1105_port_deferred_xmit(struct kthread_work *work)
2684 struct sja1105_deferred_xmit_work *xmit_work = work_to_xmit_work(work);
2685 struct sk_buff *clone, *skb = xmit_work->skb;
2686 struct dsa_switch *ds = xmit_work->dp->ds;
2687 struct sja1105_private *priv = ds->priv;
2688 int port = xmit_work->dp->index;
2690 clone = SJA1105_SKB_CB(skb)->clone;
2692 mutex_lock(&priv->mgmt_lock);
2694 sja1105_mgmt_xmit(ds, port, 0, skb, !!clone);
2696 /* The clone, if there, was made by dsa_skb_tx_timestamp */
2698 sja1105_ptp_txtstamp_skb(ds, port, clone);
2700 mutex_unlock(&priv->mgmt_lock);
2705 static int sja1105_connect_tag_protocol(struct dsa_switch *ds,
2706 enum dsa_tag_protocol proto)
2708 struct sja1105_private *priv = ds->priv;
2709 struct sja1105_tagger_data *tagger_data;
2711 if (proto != priv->info->tag_proto)
2712 return -EPROTONOSUPPORT;
2714 tagger_data = sja1105_tagger_data(ds);
2715 tagger_data->xmit_work_fn = sja1105_port_deferred_xmit;
2716 tagger_data->meta_tstamp_handler = sja1110_process_meta_tstamp;
2721 /* The MAXAGE setting belongs to the L2 Forwarding Parameters table,
2722 * which cannot be reconfigured at runtime. So a switch reset is required.
2724 static int sja1105_set_ageing_time(struct dsa_switch *ds,
2725 unsigned int ageing_time)
2727 struct sja1105_l2_lookup_params_entry *l2_lookup_params;
2728 struct sja1105_private *priv = ds->priv;
2729 struct sja1105_table *table;
2730 unsigned int maxage;
2732 table = &priv->static_config.tables[BLK_IDX_L2_LOOKUP_PARAMS];
2733 l2_lookup_params = table->entries;
2735 maxage = SJA1105_AGEING_TIME_MS(ageing_time);
2737 if (l2_lookup_params->maxage == maxage)
2740 l2_lookup_params->maxage = maxage;
2742 return sja1105_static_config_reload(priv, SJA1105_AGEING_TIME);
2745 static int sja1105_change_mtu(struct dsa_switch *ds, int port, int new_mtu)
2747 struct sja1105_l2_policing_entry *policing;
2748 struct sja1105_private *priv = ds->priv;
2750 new_mtu += VLAN_ETH_HLEN + ETH_FCS_LEN;
2752 if (dsa_is_cpu_port(ds, port) || dsa_is_dsa_port(ds, port))
2753 new_mtu += VLAN_HLEN;
2755 policing = priv->static_config.tables[BLK_IDX_L2_POLICING].entries;
2757 if (policing[port].maxlen == new_mtu)
2760 policing[port].maxlen = new_mtu;
2762 return sja1105_static_config_reload(priv, SJA1105_BEST_EFFORT_POLICING);
2765 static int sja1105_get_max_mtu(struct dsa_switch *ds, int port)
2767 return 2043 - VLAN_ETH_HLEN - ETH_FCS_LEN;
2770 static int sja1105_port_setup_tc(struct dsa_switch *ds, int port,
2771 enum tc_setup_type type,
2775 case TC_SETUP_QDISC_TAPRIO:
2776 return sja1105_setup_tc_taprio(ds, port, type_data);
2777 case TC_SETUP_QDISC_CBS:
2778 return sja1105_setup_tc_cbs(ds, port, type_data);
2784 /* We have a single mirror (@to) port, but can configure ingress and egress
2785 * mirroring on all other (@from) ports.
2786 * We need to allow mirroring rules only as long as the @to port is always the
2787 * same, and we need to unset the @to port from mirr_port only when there is no
2788 * mirroring rule that references it.
2790 static int sja1105_mirror_apply(struct sja1105_private *priv, int from, int to,
2791 bool ingress, bool enabled)
2793 struct sja1105_general_params_entry *general_params;
2794 struct sja1105_mac_config_entry *mac;
2795 struct dsa_switch *ds = priv->ds;
2796 struct sja1105_table *table;
2797 bool already_enabled;
2801 table = &priv->static_config.tables[BLK_IDX_GENERAL_PARAMS];
2802 general_params = table->entries;
2804 mac = priv->static_config.tables[BLK_IDX_MAC_CONFIG].entries;
2806 already_enabled = (general_params->mirr_port != ds->num_ports);
2807 if (already_enabled && enabled && general_params->mirr_port != to) {
2808 dev_err(priv->ds->dev,
2809 "Delete mirroring rules towards port %llu first\n",
2810 general_params->mirr_port);
2819 /* Anybody still referencing mirr_port? */
2820 for (port = 0; port < ds->num_ports; port++) {
2821 if (mac[port].ing_mirr || mac[port].egr_mirr) {
2826 /* Unset already_enabled for next time */
2828 new_mirr_port = ds->num_ports;
2830 if (new_mirr_port != general_params->mirr_port) {
2831 general_params->mirr_port = new_mirr_port;
2833 rc = sja1105_dynamic_config_write(priv, BLK_IDX_GENERAL_PARAMS,
2834 0, general_params, true);
2840 mac[from].ing_mirr = enabled;
2842 mac[from].egr_mirr = enabled;
2844 return sja1105_dynamic_config_write(priv, BLK_IDX_MAC_CONFIG, from,
2848 static int sja1105_mirror_add(struct dsa_switch *ds, int port,
2849 struct dsa_mall_mirror_tc_entry *mirror,
2852 return sja1105_mirror_apply(ds->priv, port, mirror->to_local_port,
2856 static void sja1105_mirror_del(struct dsa_switch *ds, int port,
2857 struct dsa_mall_mirror_tc_entry *mirror)
2859 sja1105_mirror_apply(ds->priv, port, mirror->to_local_port,
2860 mirror->ingress, false);
2863 static int sja1105_port_policer_add(struct dsa_switch *ds, int port,
2864 struct dsa_mall_policer_tc_entry *policer)
2866 struct sja1105_l2_policing_entry *policing;
2867 struct sja1105_private *priv = ds->priv;
2869 policing = priv->static_config.tables[BLK_IDX_L2_POLICING].entries;
2871 /* In hardware, every 8 microseconds the credit level is incremented by
2872 * the value of RATE bytes divided by 64, up to a maximum of SMAX
2875 policing[port].rate = div_u64(512 * policer->rate_bytes_per_sec,
2877 policing[port].smax = policer->burst;
2879 return sja1105_static_config_reload(priv, SJA1105_BEST_EFFORT_POLICING);
2882 static void sja1105_port_policer_del(struct dsa_switch *ds, int port)
2884 struct sja1105_l2_policing_entry *policing;
2885 struct sja1105_private *priv = ds->priv;
2887 policing = priv->static_config.tables[BLK_IDX_L2_POLICING].entries;
2889 policing[port].rate = SJA1105_RATE_MBPS(1000);
2890 policing[port].smax = 65535;
2892 sja1105_static_config_reload(priv, SJA1105_BEST_EFFORT_POLICING);
2895 static int sja1105_port_set_learning(struct sja1105_private *priv, int port,
2898 struct sja1105_mac_config_entry *mac;
2900 mac = priv->static_config.tables[BLK_IDX_MAC_CONFIG].entries;
2902 mac[port].dyn_learn = enabled;
2904 return sja1105_dynamic_config_write(priv, BLK_IDX_MAC_CONFIG, port,
2908 static int sja1105_port_ucast_bcast_flood(struct sja1105_private *priv, int to,
2909 struct switchdev_brport_flags flags)
2911 if (flags.mask & BR_FLOOD) {
2912 if (flags.val & BR_FLOOD)
2913 priv->ucast_egress_floods |= BIT(to);
2915 priv->ucast_egress_floods &= ~BIT(to);
2918 if (flags.mask & BR_BCAST_FLOOD) {
2919 if (flags.val & BR_BCAST_FLOOD)
2920 priv->bcast_egress_floods |= BIT(to);
2922 priv->bcast_egress_floods &= ~BIT(to);
2925 return sja1105_manage_flood_domains(priv);
2928 static int sja1105_port_mcast_flood(struct sja1105_private *priv, int to,
2929 struct switchdev_brport_flags flags,
2930 struct netlink_ext_ack *extack)
2932 struct sja1105_l2_lookup_entry *l2_lookup;
2933 struct sja1105_table *table;
2936 table = &priv->static_config.tables[BLK_IDX_L2_LOOKUP];
2937 l2_lookup = table->entries;
2939 for (match = 0; match < table->entry_count; match++)
2940 if (l2_lookup[match].macaddr == SJA1105_UNKNOWN_MULTICAST &&
2941 l2_lookup[match].mask_macaddr == SJA1105_UNKNOWN_MULTICAST)
2944 if (match == table->entry_count) {
2945 NL_SET_ERR_MSG_MOD(extack,
2946 "Could not find FDB entry for unknown multicast");
2950 if (flags.val & BR_MCAST_FLOOD)
2951 l2_lookup[match].destports |= BIT(to);
2953 l2_lookup[match].destports &= ~BIT(to);
2955 return sja1105_dynamic_config_write(priv, BLK_IDX_L2_LOOKUP,
2956 l2_lookup[match].index,
2961 static int sja1105_port_pre_bridge_flags(struct dsa_switch *ds, int port,
2962 struct switchdev_brport_flags flags,
2963 struct netlink_ext_ack *extack)
2965 struct sja1105_private *priv = ds->priv;
2967 if (flags.mask & ~(BR_LEARNING | BR_FLOOD | BR_MCAST_FLOOD |
2971 if (flags.mask & (BR_FLOOD | BR_MCAST_FLOOD) &&
2972 !priv->info->can_limit_mcast_flood) {
2973 bool multicast = !!(flags.val & BR_MCAST_FLOOD);
2974 bool unicast = !!(flags.val & BR_FLOOD);
2976 if (unicast != multicast) {
2977 NL_SET_ERR_MSG_MOD(extack,
2978 "This chip cannot configure multicast flooding independently of unicast");
2986 static int sja1105_port_bridge_flags(struct dsa_switch *ds, int port,
2987 struct switchdev_brport_flags flags,
2988 struct netlink_ext_ack *extack)
2990 struct sja1105_private *priv = ds->priv;
2993 if (flags.mask & BR_LEARNING) {
2994 bool learn_ena = !!(flags.val & BR_LEARNING);
2996 rc = sja1105_port_set_learning(priv, port, learn_ena);
3001 if (flags.mask & (BR_FLOOD | BR_BCAST_FLOOD)) {
3002 rc = sja1105_port_ucast_bcast_flood(priv, port, flags);
3007 /* For chips that can't offload BR_MCAST_FLOOD independently, there
3008 * is nothing to do here, we ensured the configuration is in sync by
3009 * offloading BR_FLOOD.
3011 if (flags.mask & BR_MCAST_FLOOD && priv->info->can_limit_mcast_flood) {
3012 rc = sja1105_port_mcast_flood(priv, port, flags,
3021 /* The programming model for the SJA1105 switch is "all-at-once" via static
3022 * configuration tables. Some of these can be dynamically modified at runtime,
3023 * but not the xMII mode parameters table.
3024 * Furthermode, some PHYs may not have crystals for generating their clocks
3025 * (e.g. RMII). Instead, their 50MHz clock is supplied via the SJA1105 port's
3026 * ref_clk pin. So port clocking needs to be initialized early, before
3027 * connecting to PHYs is attempted, otherwise they won't respond through MDIO.
3028 * Setting correct PHY link speed does not matter now.
3029 * But dsa_slave_phy_setup is called later than sja1105_setup, so the PHY
3030 * bindings are not yet parsed by DSA core. We need to parse early so that we
3031 * can populate the xMII mode parameters table.
3033 static int sja1105_setup(struct dsa_switch *ds)
3035 struct sja1105_private *priv = ds->priv;
3038 if (priv->info->disable_microcontroller) {
3039 rc = priv->info->disable_microcontroller(priv);
3042 "Failed to disable microcontroller: %pe\n",
3048 /* Create and send configuration down to device */
3049 rc = sja1105_static_config_load(priv);
3051 dev_err(ds->dev, "Failed to load static config: %d\n", rc);
3055 /* Configure the CGU (PHY link modes and speeds) */
3056 if (priv->info->clocking_setup) {
3057 rc = priv->info->clocking_setup(priv);
3060 "Failed to configure MII clocking: %pe\n",
3062 goto out_static_config_free;
3066 sja1105_tas_setup(ds);
3067 sja1105_flower_setup(ds);
3069 rc = sja1105_ptp_clock_register(ds);
3071 dev_err(ds->dev, "Failed to register PTP clock: %d\n", rc);
3072 goto out_flower_teardown;
3075 rc = sja1105_mdiobus_register(ds);
3077 dev_err(ds->dev, "Failed to register MDIO bus: %pe\n",
3079 goto out_ptp_clock_unregister;
3082 rc = sja1105_devlink_setup(ds);
3084 goto out_mdiobus_unregister;
3087 rc = dsa_tag_8021q_register(ds, htons(ETH_P_8021Q));
3090 goto out_devlink_teardown;
3092 /* On SJA1105, VLAN filtering per se is always enabled in hardware.
3093 * The only thing we can do to disable it is lie about what the 802.1Q
3095 * So it will still try to apply VLAN filtering, but all ingress
3096 * traffic (except frames received with EtherType of ETH_P_SJA1105)
3097 * will be internally tagged with a distorted VLAN header where the
3098 * TPID is ETH_P_SJA1105, and the VLAN ID is the port pvid.
3100 ds->vlan_filtering_is_global = true;
3101 ds->untag_bridge_pvid = true;
3102 ds->fdb_isolation = true;
3103 /* tag_8021q has 3 bits for the VBID, and the value 0 is reserved */
3104 ds->max_num_bridges = 7;
3106 /* Advertise the 8 egress queues */
3107 ds->num_tx_queues = SJA1105_NUM_TC;
3109 ds->mtu_enforcement_ingress = true;
3110 ds->assisted_learning_on_cpu_port = true;
3114 out_devlink_teardown:
3115 sja1105_devlink_teardown(ds);
3116 out_mdiobus_unregister:
3117 sja1105_mdiobus_unregister(ds);
3118 out_ptp_clock_unregister:
3119 sja1105_ptp_clock_unregister(ds);
3120 out_flower_teardown:
3121 sja1105_flower_teardown(ds);
3122 sja1105_tas_teardown(ds);
3123 out_static_config_free:
3124 sja1105_static_config_free(&priv->static_config);
3129 static void sja1105_teardown(struct dsa_switch *ds)
3131 struct sja1105_private *priv = ds->priv;
3134 dsa_tag_8021q_unregister(ds);
3137 sja1105_devlink_teardown(ds);
3138 sja1105_mdiobus_unregister(ds);
3139 sja1105_ptp_clock_unregister(ds);
3140 sja1105_flower_teardown(ds);
3141 sja1105_tas_teardown(ds);
3142 sja1105_static_config_free(&priv->static_config);
3145 static const struct dsa_switch_ops sja1105_switch_ops = {
3146 .get_tag_protocol = sja1105_get_tag_protocol,
3147 .connect_tag_protocol = sja1105_connect_tag_protocol,
3148 .setup = sja1105_setup,
3149 .teardown = sja1105_teardown,
3150 .set_ageing_time = sja1105_set_ageing_time,
3151 .port_change_mtu = sja1105_change_mtu,
3152 .port_max_mtu = sja1105_get_max_mtu,
3153 .phylink_get_caps = sja1105_phylink_get_caps,
3154 .phylink_mac_select_pcs = sja1105_mac_select_pcs,
3155 .phylink_mac_link_up = sja1105_mac_link_up,
3156 .phylink_mac_link_down = sja1105_mac_link_down,
3157 .get_strings = sja1105_get_strings,
3158 .get_ethtool_stats = sja1105_get_ethtool_stats,
3159 .get_sset_count = sja1105_get_sset_count,
3160 .get_ts_info = sja1105_get_ts_info,
3161 .port_fdb_dump = sja1105_fdb_dump,
3162 .port_fdb_add = sja1105_fdb_add,
3163 .port_fdb_del = sja1105_fdb_del,
3164 .port_fast_age = sja1105_fast_age,
3165 .port_bridge_join = sja1105_bridge_join,
3166 .port_bridge_leave = sja1105_bridge_leave,
3167 .port_pre_bridge_flags = sja1105_port_pre_bridge_flags,
3168 .port_bridge_flags = sja1105_port_bridge_flags,
3169 .port_stp_state_set = sja1105_bridge_stp_state_set,
3170 .port_vlan_filtering = sja1105_vlan_filtering,
3171 .port_vlan_add = sja1105_bridge_vlan_add,
3172 .port_vlan_del = sja1105_bridge_vlan_del,
3173 .port_mdb_add = sja1105_mdb_add,
3174 .port_mdb_del = sja1105_mdb_del,
3175 .port_hwtstamp_get = sja1105_hwtstamp_get,
3176 .port_hwtstamp_set = sja1105_hwtstamp_set,
3177 .port_rxtstamp = sja1105_port_rxtstamp,
3178 .port_txtstamp = sja1105_port_txtstamp,
3179 .port_setup_tc = sja1105_port_setup_tc,
3180 .port_mirror_add = sja1105_mirror_add,
3181 .port_mirror_del = sja1105_mirror_del,
3182 .port_policer_add = sja1105_port_policer_add,
3183 .port_policer_del = sja1105_port_policer_del,
3184 .cls_flower_add = sja1105_cls_flower_add,
3185 .cls_flower_del = sja1105_cls_flower_del,
3186 .cls_flower_stats = sja1105_cls_flower_stats,
3187 .devlink_info_get = sja1105_devlink_info_get,
3188 .tag_8021q_vlan_add = sja1105_dsa_8021q_vlan_add,
3189 .tag_8021q_vlan_del = sja1105_dsa_8021q_vlan_del,
3190 .port_prechangeupper = sja1105_prechangeupper,
3193 static const struct of_device_id sja1105_dt_ids[];
3195 static int sja1105_check_device_id(struct sja1105_private *priv)
3197 const struct sja1105_regs *regs = priv->info->regs;
3198 u8 prod_id[SJA1105_SIZE_DEVICE_ID] = {0};
3199 struct device *dev = &priv->spidev->dev;
3200 const struct of_device_id *match;
3205 rc = sja1105_xfer_u32(priv, SPI_READ, regs->device_id, &device_id,
3210 rc = sja1105_xfer_buf(priv, SPI_READ, regs->prod_id, prod_id,
3211 SJA1105_SIZE_DEVICE_ID);
3215 sja1105_unpack(prod_id, &part_no, 19, 4, SJA1105_SIZE_DEVICE_ID);
3217 for (match = sja1105_dt_ids; match->compatible[0]; match++) {
3218 const struct sja1105_info *info = match->data;
3220 /* Is what's been probed in our match table at all? */
3221 if (info->device_id != device_id || info->part_no != part_no)
3224 /* But is it what's in the device tree? */
3225 if (priv->info->device_id != device_id ||
3226 priv->info->part_no != part_no) {
3227 dev_warn(dev, "Device tree specifies chip %s but found %s, please fix it!\n",
3228 priv->info->name, info->name);
3229 /* It isn't. No problem, pick that up. */
3236 dev_err(dev, "Unexpected {device ID, part number}: 0x%x 0x%llx\n",
3237 device_id, part_no);
3242 static int sja1105_probe(struct spi_device *spi)
3244 struct device *dev = &spi->dev;
3245 struct sja1105_private *priv;
3246 size_t max_xfer, max_msg;
3247 struct dsa_switch *ds;
3250 if (!dev->of_node) {
3251 dev_err(dev, "No DTS bindings for SJA1105 driver\n");
3255 rc = sja1105_hw_reset(dev, 1, 1);
3259 priv = devm_kzalloc(dev, sizeof(struct sja1105_private), GFP_KERNEL);
3263 /* Populate our driver private structure (priv) based on
3264 * the device tree node that was probed (spi)
3267 spi_set_drvdata(spi, priv);
3269 /* Configure the SPI bus */
3270 spi->bits_per_word = 8;
3271 rc = spi_setup(spi);
3273 dev_err(dev, "Could not init SPI\n");
3277 /* In sja1105_xfer, we send spi_messages composed of two spi_transfers:
3278 * a small one for the message header and another one for the current
3279 * chunk of the packed buffer.
3280 * Check that the restrictions imposed by the SPI controller are
3281 * respected: the chunk buffer is smaller than the max transfer size,
3282 * and the total length of the chunk plus its message header is smaller
3283 * than the max message size.
3284 * We do that during probe time since the maximum transfer size is a
3285 * runtime invariant.
3287 max_xfer = spi_max_transfer_size(spi);
3288 max_msg = spi_max_message_size(spi);
3290 /* We need to send at least one 64-bit word of SPI payload per message
3291 * in order to be able to make useful progress.
3293 if (max_msg < SJA1105_SIZE_SPI_MSG_HEADER + 8) {
3294 dev_err(dev, "SPI master cannot send large enough buffers, aborting\n");
3298 priv->max_xfer_len = SJA1105_SIZE_SPI_MSG_MAXLEN;
3299 if (priv->max_xfer_len > max_xfer)
3300 priv->max_xfer_len = max_xfer;
3301 if (priv->max_xfer_len > max_msg - SJA1105_SIZE_SPI_MSG_HEADER)
3302 priv->max_xfer_len = max_msg - SJA1105_SIZE_SPI_MSG_HEADER;
3304 priv->info = of_device_get_match_data(dev);
3306 /* Detect hardware device */
3307 rc = sja1105_check_device_id(priv);
3309 dev_err(dev, "Device ID check failed: %d\n", rc);
3313 dev_info(dev, "Probed switch chip: %s\n", priv->info->name);
3315 ds = devm_kzalloc(dev, sizeof(*ds), GFP_KERNEL);
3320 ds->num_ports = priv->info->num_ports;
3321 ds->ops = &sja1105_switch_ops;
3325 mutex_init(&priv->ptp_data.lock);
3326 mutex_init(&priv->dynamic_config_lock);
3327 mutex_init(&priv->mgmt_lock);
3328 spin_lock_init(&priv->ts_id_lock);
3330 rc = sja1105_parse_dt(priv);
3332 dev_err(ds->dev, "Failed to parse DT: %d\n", rc);
3336 if (IS_ENABLED(CONFIG_NET_SCH_CBS)) {
3337 priv->cbs = devm_kcalloc(dev, priv->info->num_cbs_shapers,
3338 sizeof(struct sja1105_cbs_entry),
3344 return dsa_register_switch(priv->ds);
3347 static void sja1105_remove(struct spi_device *spi)
3349 struct sja1105_private *priv = spi_get_drvdata(spi);
3354 dsa_unregister_switch(priv->ds);
3356 spi_set_drvdata(spi, NULL);
3359 static void sja1105_shutdown(struct spi_device *spi)
3361 struct sja1105_private *priv = spi_get_drvdata(spi);
3366 dsa_switch_shutdown(priv->ds);
3368 spi_set_drvdata(spi, NULL);
3371 static const struct of_device_id sja1105_dt_ids[] = {
3372 { .compatible = "nxp,sja1105e", .data = &sja1105e_info },
3373 { .compatible = "nxp,sja1105t", .data = &sja1105t_info },
3374 { .compatible = "nxp,sja1105p", .data = &sja1105p_info },
3375 { .compatible = "nxp,sja1105q", .data = &sja1105q_info },
3376 { .compatible = "nxp,sja1105r", .data = &sja1105r_info },
3377 { .compatible = "nxp,sja1105s", .data = &sja1105s_info },
3378 { .compatible = "nxp,sja1110a", .data = &sja1110a_info },
3379 { .compatible = "nxp,sja1110b", .data = &sja1110b_info },
3380 { .compatible = "nxp,sja1110c", .data = &sja1110c_info },
3381 { .compatible = "nxp,sja1110d", .data = &sja1110d_info },
3384 MODULE_DEVICE_TABLE(of, sja1105_dt_ids);
3386 static struct spi_driver sja1105_driver = {
3389 .owner = THIS_MODULE,
3390 .of_match_table = of_match_ptr(sja1105_dt_ids),
3392 .probe = sja1105_probe,
3393 .remove = sja1105_remove,
3394 .shutdown = sja1105_shutdown,
3397 module_spi_driver(sja1105_driver);
3399 MODULE_AUTHOR("Vladimir Oltean <olteanv@gmail.com>");
3400 MODULE_AUTHOR("Georg Waibel <georg.waibel@sensor-technik.de>");
3401 MODULE_DESCRIPTION("SJA1105 Driver");
3402 MODULE_LICENSE("GPL v2");