drivers/net/dsa/sja1105/sja1105.h

   1 /* SPDX-License-Identifier: GPL-2.0 */
   2 /* Copyright (c) 2018, Sensor-Technik Wiedemann GmbH
   3  * Copyright (c) 2018-2019, Vladimir Oltean <olteanv@gmail.com>
   4  */
   5 #ifndef _SJA1105_H
   6 #define _SJA1105_H
   7
   8 #include <linux/ptp_clock_kernel.h>
   9 #include <linux/timecounter.h>
  10 #include <linux/dsa/sja1105.h>
  11 #include <linux/dsa/8021q.h>
  12 #include <net/dsa.h>
  13 #include <linux/mutex.h>
  14 #include "sja1105_static_config.h"
  15
  16 #define SJA1105ET_FDB_BIN_SIZE          4
  17 /* The hardware value is in multiples of 10 ms.
  18  * The passed parameter is in multiples of 1 ms.
  19  */
  20 #define SJA1105_AGEING_TIME_MS(ms)      ((ms) / 10)
  21 #define SJA1105_NUM_L2_POLICERS         SJA1110_MAX_L2_POLICING_COUNT
  22
  23 typedef enum {
  24         SPI_READ = 0,
  25         SPI_WRITE = 1,
  26 } sja1105_spi_rw_mode_t;
  27
  28 #include "sja1105_tas.h"
  29 #include "sja1105_ptp.h"
  30
  31 enum sja1105_stats_area {
  32         MAC,
  33         HL1,
  34         HL2,
  35         ETHER,
  36         __MAX_SJA1105_STATS_AREA,
  37 };
  38
  39 /* Keeps the different addresses between E/T and P/Q/R/S */
  40 struct sja1105_regs {
  41         u64 device_id;
  42         u64 prod_id;
  43         u64 status;
  44         u64 port_control;
  45         u64 rgu;
  46         u64 vl_status;
  47         u64 config;
  48         u64 rmii_pll1;
  49         u64 ptppinst;
  50         u64 ptppindur;
  51         u64 ptp_control;
  52         u64 ptpclkval;
  53         u64 ptpclkrate;
  54         u64 ptpclkcorp;
  55         u64 ptpsyncts;
  56         u64 ptpschtm;
  57         u64 ptpegr_ts[SJA1105_MAX_NUM_PORTS];
  58         u64 pad_mii_tx[SJA1105_MAX_NUM_PORTS];
  59         u64 pad_mii_rx[SJA1105_MAX_NUM_PORTS];
  60         u64 pad_mii_id[SJA1105_MAX_NUM_PORTS];
  61         u64 cgu_idiv[SJA1105_MAX_NUM_PORTS];
  62         u64 mii_tx_clk[SJA1105_MAX_NUM_PORTS];
  63         u64 mii_rx_clk[SJA1105_MAX_NUM_PORTS];
  64         u64 mii_ext_tx_clk[SJA1105_MAX_NUM_PORTS];
  65         u64 mii_ext_rx_clk[SJA1105_MAX_NUM_PORTS];
  66         u64 rgmii_tx_clk[SJA1105_MAX_NUM_PORTS];
  67         u64 rmii_ref_clk[SJA1105_MAX_NUM_PORTS];
  68         u64 rmii_ext_tx_clk[SJA1105_MAX_NUM_PORTS];
  69         u64 stats[__MAX_SJA1105_STATS_AREA][SJA1105_MAX_NUM_PORTS];
  70         u64 mdio_100base_tx;
  71         u64 mdio_100base_t1;
  72 };
  73
  74 struct sja1105_mdio_private {
  75         struct sja1105_private *priv;
  76 };
  77
  78 enum {
  79         SJA1105_SPEED_AUTO,
  80         SJA1105_SPEED_10MBPS,
  81         SJA1105_SPEED_100MBPS,
  82         SJA1105_SPEED_1000MBPS,
  83         SJA1105_SPEED_2500MBPS,
  84         SJA1105_SPEED_MAX,
  85 };
  86
  87 enum sja1105_internal_phy_t {
  88         SJA1105_NO_PHY          = 0,
  89         SJA1105_PHY_BASE_TX,
  90         SJA1105_PHY_BASE_T1,
  91 };
  92
  93 struct sja1105_info {
  94         u64 device_id;
  95         /* Needed for distinction between P and R, and between Q and S
  96          * (since the parts with/without SGMII share the same
  97          * switch core and device_id)
  98          */
  99         u64 part_no;
 100         /* E/T and P/Q/R/S have partial timestamps of different sizes.
 101          * They must be reconstructed on both families anyway to get the full
 102          * 64-bit values back.
 103          */
 104         int ptp_ts_bits;
 105         /* Also SPI commands are of different sizes to retrieve
 106          * the egress timestamps.
 107          */
 108         int ptpegr_ts_bytes;
 109         int num_cbs_shapers;
 110         int max_frame_mem;
 111         int num_ports;
 112         bool multiple_cascade_ports;
 113         enum dsa_tag_protocol tag_proto;
 114         const struct sja1105_dynamic_table_ops *dyn_ops;
 115         const struct sja1105_table_ops *static_ops;
 116         const struct sja1105_regs *regs;
 117         /* Both E/T and P/Q/R/S have quirks when it comes to popping the S-Tag
 118          * from double-tagged frames. E/T will pop it only when it's equal to
 119          * TPID from the General Parameters Table, while P/Q/R/S will only
 120          * pop it when it's equal to TPID2.
 121          */
 122         u16 qinq_tpid;
 123         bool can_limit_mcast_flood;
 124         int (*reset_cmd)(struct dsa_switch *ds);
 125         int (*setup_rgmii_delay)(const void *ctx, int port);
 126         /* Prototypes from include/net/dsa.h */
 127         int (*fdb_add_cmd)(struct dsa_switch *ds, int port,
 128                            const unsigned char *addr, u16 vid);
 129         int (*fdb_del_cmd)(struct dsa_switch *ds, int port,
 130                            const unsigned char *addr, u16 vid);
 131         void (*ptp_cmd_packing)(u8 *buf, struct sja1105_ptp_cmd *cmd,
 132                                 enum packing_op op);
 133         bool (*rxtstamp)(struct dsa_switch *ds, int port, struct sk_buff *skb);
 134         void (*txtstamp)(struct dsa_switch *ds, int port, struct sk_buff *skb);
 135         int (*clocking_setup)(struct sja1105_private *priv);
 136         const char *name;
 137         bool supports_mii[SJA1105_MAX_NUM_PORTS];
 138         bool supports_rmii[SJA1105_MAX_NUM_PORTS];
 139         bool supports_rgmii[SJA1105_MAX_NUM_PORTS];
 140         bool supports_sgmii[SJA1105_MAX_NUM_PORTS];
 141         bool supports_2500basex[SJA1105_MAX_NUM_PORTS];
 142         enum sja1105_internal_phy_t internal_phy[SJA1105_MAX_NUM_PORTS];
 143         const u64 port_speed[SJA1105_SPEED_MAX];
 144 };
 145
 146 enum sja1105_key_type {
 147         SJA1105_KEY_BCAST,
 148         SJA1105_KEY_TC,
 149         SJA1105_KEY_VLAN_UNAWARE_VL,
 150         SJA1105_KEY_VLAN_AWARE_VL,
 151 };
 152
 153 struct sja1105_key {
 154         enum sja1105_key_type type;
 155
 156         union {
 157                 /* SJA1105_KEY_TC */
 158                 struct {
 159                         int pcp;
 160                 } tc;
 161
 162                 /* SJA1105_KEY_VLAN_UNAWARE_VL */
 163                 /* SJA1105_KEY_VLAN_AWARE_VL */
 164                 struct {
 165                         u64 dmac;
 166                         u16 vid;
 167                         u16 pcp;
 168                 } vl;
 169         };
 170 };
 171
 172 enum sja1105_rule_type {
 173         SJA1105_RULE_BCAST_POLICER,
 174         SJA1105_RULE_TC_POLICER,
 175         SJA1105_RULE_VL,
 176 };
 177
 178 enum sja1105_vl_type {
 179         SJA1105_VL_NONCRITICAL,
 180         SJA1105_VL_RATE_CONSTRAINED,
 181         SJA1105_VL_TIME_TRIGGERED,
 182 };
 183
 184 struct sja1105_rule {
 185         struct list_head list;
 186         unsigned long cookie;
 187         unsigned long port_mask;
 188         struct sja1105_key key;
 189         enum sja1105_rule_type type;
 190
 191         /* Action */
 192         union {
 193                 /* SJA1105_RULE_BCAST_POLICER */
 194                 struct {
 195                         int sharindx;
 196                 } bcast_pol;
 197
 198                 /* SJA1105_RULE_TC_POLICER */
 199                 struct {
 200                         int sharindx;
 201                 } tc_pol;
 202
 203                 /* SJA1105_RULE_VL */
 204                 struct {
 205                         enum sja1105_vl_type type;
 206                         unsigned long destports;
 207                         int sharindx;
 208                         int maxlen;
 209                         int ipv;
 210                         u64 base_time;
 211                         u64 cycle_time;
 212                         int num_entries;
 213                         struct action_gate_entry *entries;
 214                         struct flow_stats stats;
 215                 } vl;
 216         };
 217 };
 218
 219 struct sja1105_flow_block {
 220         struct list_head rules;
 221         bool l2_policer_used[SJA1105_NUM_L2_POLICERS];
 222         int num_virtual_links;
 223 };
 224
 225 struct sja1105_bridge_vlan {
 226         struct list_head list;
 227         int port;
 228         u16 vid;
 229         bool pvid;
 230         bool untagged;
 231 };
 232
 233 enum sja1105_vlan_state {
 234         SJA1105_VLAN_UNAWARE,
 235         SJA1105_VLAN_BEST_EFFORT,
 236         SJA1105_VLAN_FILTERING_FULL,
 237 };
 238
 239 struct sja1105_private {
 240         struct sja1105_static_config static_config;
 241         bool rgmii_rx_delay[SJA1105_MAX_NUM_PORTS];
 242         bool rgmii_tx_delay[SJA1105_MAX_NUM_PORTS];
 243         phy_interface_t phy_mode[SJA1105_MAX_NUM_PORTS];
 244         bool fixed_link[SJA1105_MAX_NUM_PORTS];
 245         bool best_effort_vlan_filtering;
 246         unsigned long learn_ena;
 247         unsigned long ucast_egress_floods;
 248         unsigned long bcast_egress_floods;
 249         const struct sja1105_info *info;
 250         size_t max_xfer_len;
 251         struct gpio_desc *reset_gpio;
 252         struct spi_device *spidev;
 253         struct dsa_switch *ds;
 254         struct list_head dsa_8021q_vlans;
 255         struct list_head bridge_vlans;
 256         struct sja1105_flow_block flow_block;
 257         struct sja1105_port ports[SJA1105_MAX_NUM_PORTS];
 258         /* Serializes transmission of management frames so that
 259          * the switch doesn't confuse them with one another.
 260          */
 261         struct mutex mgmt_lock;
 262         struct dsa_8021q_context *dsa_8021q_ctx;
 263         enum sja1105_vlan_state vlan_state;
 264         struct devlink_region **regions;
 265         struct sja1105_cbs_entry *cbs;
 266         struct mii_bus *mdio_base_t1;
 267         struct mii_bus *mdio_base_tx;
 268         struct sja1105_tagger_data tagger_data;
 269         struct sja1105_ptp_data ptp_data;
 270         struct sja1105_tas_data tas_data;
 271 };
 272
 273 #include "sja1105_dynamic_config.h"
 274
 275 struct sja1105_spi_message {
 276         u64 access;
 277         u64 read_count;
 278         u64 address;
 279 };
 280
 281 /* From sja1105_main.c */
 282 enum sja1105_reset_reason {
 283         SJA1105_VLAN_FILTERING = 0,
 284         SJA1105_RX_HWTSTAMPING,
 285         SJA1105_AGEING_TIME,
 286         SJA1105_SCHEDULING,
 287         SJA1105_BEST_EFFORT_POLICING,
 288         SJA1105_VIRTUAL_LINKS,
 289 };
 290
 291 int sja1105_static_config_reload(struct sja1105_private *priv,
 292                                  enum sja1105_reset_reason reason);
 293 int sja1105_vlan_filtering(struct dsa_switch *ds, int port, bool enabled,
 294                            struct netlink_ext_ack *extack);
 295 void sja1105_frame_memory_partitioning(struct sja1105_private *priv);
 296
 297 /* From sja1105_mdio.c */
 298 int sja1105_mdiobus_register(struct dsa_switch *ds);
 299 void sja1105_mdiobus_unregister(struct dsa_switch *ds);
 300
 301 /* From sja1105_devlink.c */
 302 int sja1105_devlink_setup(struct dsa_switch *ds);
 303 void sja1105_devlink_teardown(struct dsa_switch *ds);
 304 int sja1105_devlink_param_get(struct dsa_switch *ds, u32 id,
 305                               struct devlink_param_gset_ctx *ctx);
 306 int sja1105_devlink_param_set(struct dsa_switch *ds, u32 id,
 307                               struct devlink_param_gset_ctx *ctx);
 308 int sja1105_devlink_info_get(struct dsa_switch *ds,
 309                              struct devlink_info_req *req,
 310                              struct netlink_ext_ack *extack);
 311
 312 /* From sja1105_spi.c */
 313 int sja1105_xfer_buf(const struct sja1105_private *priv,
 314                      sja1105_spi_rw_mode_t rw, u64 reg_addr,
 315                      u8 *buf, size_t len);
 316 int sja1105_xfer_u32(const struct sja1105_private *priv,
 317                      sja1105_spi_rw_mode_t rw, u64 reg_addr, u32 *value,
 318                      struct ptp_system_timestamp *ptp_sts);
 319 int sja1105_xfer_u64(const struct sja1105_private *priv,
 320                      sja1105_spi_rw_mode_t rw, u64 reg_addr, u64 *value,
 321                      struct ptp_system_timestamp *ptp_sts);
 322 int static_config_buf_prepare_for_upload(struct sja1105_private *priv,
 323                                          void *config_buf, int buf_len);
 324 int sja1105_static_config_upload(struct sja1105_private *priv);
 325 int sja1105_inhibit_tx(const struct sja1105_private *priv,
 326                        unsigned long port_bitmap, bool tx_inhibited);
 327
 328 extern const struct sja1105_info sja1105e_info;
 329 extern const struct sja1105_info sja1105t_info;
 330 extern const struct sja1105_info sja1105p_info;
 331 extern const struct sja1105_info sja1105q_info;
 332 extern const struct sja1105_info sja1105r_info;
 333 extern const struct sja1105_info sja1105s_info;
 334 extern const struct sja1105_info sja1110a_info;
 335 extern const struct sja1105_info sja1110b_info;
 336 extern const struct sja1105_info sja1110c_info;
 337 extern const struct sja1105_info sja1110d_info;
 338
 339 /* From sja1105_clocking.c */
 340
 341 typedef enum {
 342         XMII_MAC = 0,
 343         XMII_PHY = 1,
 344 } sja1105_mii_role_t;
 345
 346 typedef enum {
 347         XMII_MODE_MII           = 0,
 348         XMII_MODE_RMII          = 1,
 349         XMII_MODE_RGMII         = 2,
 350         XMII_MODE_SGMII         = 3,
 351 } sja1105_phy_interface_t;
 352
 353 int sja1105pqrs_setup_rgmii_delay(const void *ctx, int port);
 354 int sja1110_setup_rgmii_delay(const void *ctx, int port);
 355 int sja1105_clocking_setup_port(struct sja1105_private *priv, int port);
 356 int sja1105_clocking_setup(struct sja1105_private *priv);
 357 int sja1110_clocking_setup(struct sja1105_private *priv);
 358
 359 /* From sja1105_ethtool.c */
 360 void sja1105_get_ethtool_stats(struct dsa_switch *ds, int port, u64 *data);
 361 void sja1105_get_strings(struct dsa_switch *ds, int port,
 362                          u32 stringset, u8 *data);
 363 int sja1105_get_sset_count(struct dsa_switch *ds, int port, int sset);
 364
 365 /* From sja1105_dynamic_config.c */
 366 int sja1105_dynamic_config_read(struct sja1105_private *priv,
 367                                 enum sja1105_blk_idx blk_idx,
 368                                 int index, void *entry);
 369 int sja1105_dynamic_config_write(struct sja1105_private *priv,
 370                                  enum sja1105_blk_idx blk_idx,
 371                                  int index, void *entry, bool keep);
 372
 373 enum sja1105_iotag {
 374         SJA1105_C_TAG = 0, /* Inner VLAN header */
 375         SJA1105_S_TAG = 1, /* Outer VLAN header */
 376 };
 377
 378 enum sja1110_vlan_type {
 379         SJA1110_VLAN_INVALID = 0,
 380         SJA1110_VLAN_C_TAG = 1, /* Single inner VLAN tag */
 381         SJA1110_VLAN_S_TAG = 2, /* Single outer VLAN tag */
 382         SJA1110_VLAN_D_TAG = 3, /* Double tagged, use outer tag for lookup */
 383 };
 384
 385 enum sja1110_shaper_type {
 386         SJA1110_LEAKY_BUCKET_SHAPER = 0,
 387         SJA1110_CBS_SHAPER = 1,
 388 };
 389
 390 u8 sja1105et_fdb_hash(struct sja1105_private *priv, const u8 *addr, u16 vid);
 391 int sja1105et_fdb_add(struct dsa_switch *ds, int port,
 392                       const unsigned char *addr, u16 vid);
 393 int sja1105et_fdb_del(struct dsa_switch *ds, int port,
 394                       const unsigned char *addr, u16 vid);
 395 int sja1105pqrs_fdb_add(struct dsa_switch *ds, int port,
 396                         const unsigned char *addr, u16 vid);
 397 int sja1105pqrs_fdb_del(struct dsa_switch *ds, int port,
 398                         const unsigned char *addr, u16 vid);
 399
 400 /* From sja1105_flower.c */
 401 int sja1105_cls_flower_del(struct dsa_switch *ds, int port,
 402                            struct flow_cls_offload *cls, bool ingress);
 403 int sja1105_cls_flower_add(struct dsa_switch *ds, int port,
 404                            struct flow_cls_offload *cls, bool ingress);
 405 int sja1105_cls_flower_stats(struct dsa_switch *ds, int port,
 406                              struct flow_cls_offload *cls, bool ingress);
 407 void sja1105_flower_setup(struct dsa_switch *ds);
 408 void sja1105_flower_teardown(struct dsa_switch *ds);
 409 struct sja1105_rule *sja1105_rule_find(struct sja1105_private *priv,
 410                                        unsigned long cookie);
 411
 412 #endif