1 // SPDX-License-Identifier: GPL-2.0
2 /* Realtek SMI subdriver for the Realtek RTL8366RB ethernet switch
4 * This is a sparsely documented chip, the only viable documentation seems
5 * to be a patched up code drop from the vendor that appear in various
8 * Copyright (C) 2017 Linus Walleij <linus.walleij@linaro.org>
9 * Copyright (C) 2009-2010 Gabor Juhos <juhosg@openwrt.org>
10 * Copyright (C) 2010 Antti Seppälä <a.seppala@gmail.com>
11 * Copyright (C) 2010 Roman Yeryomin <roman@advem.lv>
12 * Copyright (C) 2011 Colin Leitner <colin.leitner@googlemail.com>
15 #include <linux/bitops.h>
16 #include <linux/etherdevice.h>
17 #include <linux/interrupt.h>
18 #include <linux/irqdomain.h>
19 #include <linux/irqchip/chained_irq.h>
20 #include <linux/of_irq.h>
21 #include <linux/regmap.h>
23 #include "realtek-smi-core.h"
25 #define RTL8366RB_PORT_NUM_CPU 5
26 #define RTL8366RB_NUM_PORTS 6
27 #define RTL8366RB_PHY_NO_MAX 4
28 #define RTL8366RB_PHY_ADDR_MAX 31
30 /* Switch Global Configuration register */
31 #define RTL8366RB_SGCR 0x0000
32 #define RTL8366RB_SGCR_EN_BC_STORM_CTRL BIT(0)
33 #define RTL8366RB_SGCR_MAX_LENGTH(a) ((a) << 4)
34 #define RTL8366RB_SGCR_MAX_LENGTH_MASK RTL8366RB_SGCR_MAX_LENGTH(0x3)
35 #define RTL8366RB_SGCR_MAX_LENGTH_1522 RTL8366RB_SGCR_MAX_LENGTH(0x0)
36 #define RTL8366RB_SGCR_MAX_LENGTH_1536 RTL8366RB_SGCR_MAX_LENGTH(0x1)
37 #define RTL8366RB_SGCR_MAX_LENGTH_1552 RTL8366RB_SGCR_MAX_LENGTH(0x2)
38 #define RTL8366RB_SGCR_MAX_LENGTH_16000 RTL8366RB_SGCR_MAX_LENGTH(0x3)
39 #define RTL8366RB_SGCR_EN_VLAN BIT(13)
40 #define RTL8366RB_SGCR_EN_VLAN_4KTB BIT(14)
42 /* Port Enable Control register */
43 #define RTL8366RB_PECR 0x0001
45 /* Switch Security Control registers */
46 #define RTL8366RB_SSCR0 0x0002
47 #define RTL8366RB_SSCR1 0x0003
48 #define RTL8366RB_SSCR2 0x0004
49 #define RTL8366RB_SSCR2_DROP_UNKNOWN_DA BIT(0)
51 /* Port Mode Control registers */
52 #define RTL8366RB_PMC0 0x0005
53 #define RTL8366RB_PMC0_SPI BIT(0)
54 #define RTL8366RB_PMC0_EN_AUTOLOAD BIT(1)
55 #define RTL8366RB_PMC0_PROBE BIT(2)
56 #define RTL8366RB_PMC0_DIS_BISR BIT(3)
57 #define RTL8366RB_PMC0_ADCTEST BIT(4)
58 #define RTL8366RB_PMC0_SRAM_DIAG BIT(5)
59 #define RTL8366RB_PMC0_EN_SCAN BIT(6)
60 #define RTL8366RB_PMC0_P4_IOMODE_SHIFT 7
61 #define RTL8366RB_PMC0_P4_IOMODE_MASK GENMASK(9, 7)
62 #define RTL8366RB_PMC0_P5_IOMODE_SHIFT 10
63 #define RTL8366RB_PMC0_P5_IOMODE_MASK GENMASK(12, 10)
64 #define RTL8366RB_PMC0_SDSMODE_SHIFT 13
65 #define RTL8366RB_PMC0_SDSMODE_MASK GENMASK(15, 13)
66 #define RTL8366RB_PMC1 0x0006
68 /* Port Mirror Control Register */
69 #define RTL8366RB_PMCR 0x0007
70 #define RTL8366RB_PMCR_SOURCE_PORT(a) (a)
71 #define RTL8366RB_PMCR_SOURCE_PORT_MASK 0x000f
72 #define RTL8366RB_PMCR_MONITOR_PORT(a) ((a) << 4)
73 #define RTL8366RB_PMCR_MONITOR_PORT_MASK 0x00f0
74 #define RTL8366RB_PMCR_MIRROR_RX BIT(8)
75 #define RTL8366RB_PMCR_MIRROR_TX BIT(9)
76 #define RTL8366RB_PMCR_MIRROR_SPC BIT(10)
77 #define RTL8366RB_PMCR_MIRROR_ISO BIT(11)
79 /* bits 0..7 = port 0, bits 8..15 = port 1 */
80 #define RTL8366RB_PAACR0 0x0010
81 /* bits 0..7 = port 2, bits 8..15 = port 3 */
82 #define RTL8366RB_PAACR1 0x0011
83 /* bits 0..7 = port 4, bits 8..15 = port 5 */
84 #define RTL8366RB_PAACR2 0x0012
85 #define RTL8366RB_PAACR_SPEED_10M 0
86 #define RTL8366RB_PAACR_SPEED_100M 1
87 #define RTL8366RB_PAACR_SPEED_1000M 2
88 #define RTL8366RB_PAACR_FULL_DUPLEX BIT(2)
89 #define RTL8366RB_PAACR_LINK_UP BIT(4)
90 #define RTL8366RB_PAACR_TX_PAUSE BIT(5)
91 #define RTL8366RB_PAACR_RX_PAUSE BIT(6)
92 #define RTL8366RB_PAACR_AN BIT(7)
94 #define RTL8366RB_PAACR_CPU_PORT (RTL8366RB_PAACR_SPEED_1000M | \
95 RTL8366RB_PAACR_FULL_DUPLEX | \
96 RTL8366RB_PAACR_LINK_UP | \
97 RTL8366RB_PAACR_TX_PAUSE | \
98 RTL8366RB_PAACR_RX_PAUSE)
100 /* bits 0..7 = port 0, bits 8..15 = port 1 */
101 #define RTL8366RB_PSTAT0 0x0014
102 /* bits 0..7 = port 2, bits 8..15 = port 3 */
103 #define RTL8366RB_PSTAT1 0x0015
104 /* bits 0..7 = port 4, bits 8..15 = port 5 */
105 #define RTL8366RB_PSTAT2 0x0016
107 #define RTL8366RB_POWER_SAVING_REG 0x0021
109 /* CPU port control reg */
110 #define RTL8368RB_CPU_CTRL_REG 0x0061
111 #define RTL8368RB_CPU_PORTS_MSK 0x00FF
112 /* Disables inserting custom tag length/type 0x8899 */
113 #define RTL8368RB_CPU_NO_TAG BIT(15)
115 #define RTL8366RB_SMAR0 0x0070 /* bits 0..15 */
116 #define RTL8366RB_SMAR1 0x0071 /* bits 16..31 */
117 #define RTL8366RB_SMAR2 0x0072 /* bits 32..47 */
119 #define RTL8366RB_RESET_CTRL_REG 0x0100
120 #define RTL8366RB_CHIP_CTRL_RESET_HW BIT(0)
121 #define RTL8366RB_CHIP_CTRL_RESET_SW BIT(1)
123 #define RTL8366RB_CHIP_ID_REG 0x0509
124 #define RTL8366RB_CHIP_ID_8366 0x5937
125 #define RTL8366RB_CHIP_VERSION_CTRL_REG 0x050A
126 #define RTL8366RB_CHIP_VERSION_MASK 0xf
128 /* PHY registers control */
129 #define RTL8366RB_PHY_ACCESS_CTRL_REG 0x8000
130 #define RTL8366RB_PHY_CTRL_READ BIT(0)
131 #define RTL8366RB_PHY_CTRL_WRITE 0
132 #define RTL8366RB_PHY_ACCESS_BUSY_REG 0x8001
133 #define RTL8366RB_PHY_INT_BUSY BIT(0)
134 #define RTL8366RB_PHY_EXT_BUSY BIT(4)
135 #define RTL8366RB_PHY_ACCESS_DATA_REG 0x8002
136 #define RTL8366RB_PHY_EXT_CTRL_REG 0x8010
137 #define RTL8366RB_PHY_EXT_WRDATA_REG 0x8011
138 #define RTL8366RB_PHY_EXT_RDDATA_REG 0x8012
140 #define RTL8366RB_PHY_REG_MASK 0x1f
141 #define RTL8366RB_PHY_PAGE_OFFSET 5
142 #define RTL8366RB_PHY_PAGE_MASK (0xf << 5)
143 #define RTL8366RB_PHY_NO_OFFSET 9
144 #define RTL8366RB_PHY_NO_MASK (0x1f << 9)
146 #define RTL8366RB_VLAN_INGRESS_CTRL2_REG 0x037f
148 /* LED control registers */
149 #define RTL8366RB_LED_BLINKRATE_REG 0x0430
150 #define RTL8366RB_LED_BLINKRATE_MASK 0x0007
151 #define RTL8366RB_LED_BLINKRATE_28MS 0x0000
152 #define RTL8366RB_LED_BLINKRATE_56MS 0x0001
153 #define RTL8366RB_LED_BLINKRATE_84MS 0x0002
154 #define RTL8366RB_LED_BLINKRATE_111MS 0x0003
155 #define RTL8366RB_LED_BLINKRATE_222MS 0x0004
156 #define RTL8366RB_LED_BLINKRATE_446MS 0x0005
158 #define RTL8366RB_LED_CTRL_REG 0x0431
159 #define RTL8366RB_LED_OFF 0x0
160 #define RTL8366RB_LED_DUP_COL 0x1
161 #define RTL8366RB_LED_LINK_ACT 0x2
162 #define RTL8366RB_LED_SPD1000 0x3
163 #define RTL8366RB_LED_SPD100 0x4
164 #define RTL8366RB_LED_SPD10 0x5
165 #define RTL8366RB_LED_SPD1000_ACT 0x6
166 #define RTL8366RB_LED_SPD100_ACT 0x7
167 #define RTL8366RB_LED_SPD10_ACT 0x8
168 #define RTL8366RB_LED_SPD100_10_ACT 0x9
169 #define RTL8366RB_LED_FIBER 0xa
170 #define RTL8366RB_LED_AN_FAULT 0xb
171 #define RTL8366RB_LED_LINK_RX 0xc
172 #define RTL8366RB_LED_LINK_TX 0xd
173 #define RTL8366RB_LED_MASTER 0xe
174 #define RTL8366RB_LED_FORCE 0xf
175 #define RTL8366RB_LED_0_1_CTRL_REG 0x0432
176 #define RTL8366RB_LED_1_OFFSET 6
177 #define RTL8366RB_LED_2_3_CTRL_REG 0x0433
178 #define RTL8366RB_LED_3_OFFSET 6
180 #define RTL8366RB_MIB_COUNT 33
181 #define RTL8366RB_GLOBAL_MIB_COUNT 1
182 #define RTL8366RB_MIB_COUNTER_PORT_OFFSET 0x0050
183 #define RTL8366RB_MIB_COUNTER_BASE 0x1000
184 #define RTL8366RB_MIB_CTRL_REG 0x13F0
185 #define RTL8366RB_MIB_CTRL_USER_MASK 0x0FFC
186 #define RTL8366RB_MIB_CTRL_BUSY_MASK BIT(0)
187 #define RTL8366RB_MIB_CTRL_RESET_MASK BIT(1)
188 #define RTL8366RB_MIB_CTRL_PORT_RESET(_p) BIT(2 + (_p))
189 #define RTL8366RB_MIB_CTRL_GLOBAL_RESET BIT(11)
191 #define RTL8366RB_PORT_VLAN_CTRL_BASE 0x0063
192 #define RTL8366RB_PORT_VLAN_CTRL_REG(_p) \
193 (RTL8366RB_PORT_VLAN_CTRL_BASE + (_p) / 4)
194 #define RTL8366RB_PORT_VLAN_CTRL_MASK 0xf
195 #define RTL8366RB_PORT_VLAN_CTRL_SHIFT(_p) (4 * ((_p) % 4))
197 #define RTL8366RB_VLAN_TABLE_READ_BASE 0x018C
198 #define RTL8366RB_VLAN_TABLE_WRITE_BASE 0x0185
200 #define RTL8366RB_TABLE_ACCESS_CTRL_REG 0x0180
201 #define RTL8366RB_TABLE_VLAN_READ_CTRL 0x0E01
202 #define RTL8366RB_TABLE_VLAN_WRITE_CTRL 0x0F01
204 #define RTL8366RB_VLAN_MC_BASE(_x) (0x0020 + (_x) * 3)
206 #define RTL8366RB_PORT_LINK_STATUS_BASE 0x0014
207 #define RTL8366RB_PORT_STATUS_SPEED_MASK 0x0003
208 #define RTL8366RB_PORT_STATUS_DUPLEX_MASK 0x0004
209 #define RTL8366RB_PORT_STATUS_LINK_MASK 0x0010
210 #define RTL8366RB_PORT_STATUS_TXPAUSE_MASK 0x0020
211 #define RTL8366RB_PORT_STATUS_RXPAUSE_MASK 0x0040
212 #define RTL8366RB_PORT_STATUS_AN_MASK 0x0080
214 #define RTL8366RB_NUM_VLANS 16
215 #define RTL8366RB_NUM_LEDGROUPS 4
216 #define RTL8366RB_NUM_VIDS 4096
217 #define RTL8366RB_PRIORITYMAX 7
218 #define RTL8366RB_FIDMAX 7
220 #define RTL8366RB_PORT_1 BIT(0) /* In userspace port 0 */
221 #define RTL8366RB_PORT_2 BIT(1) /* In userspace port 1 */
222 #define RTL8366RB_PORT_3 BIT(2) /* In userspace port 2 */
223 #define RTL8366RB_PORT_4 BIT(3) /* In userspace port 3 */
224 #define RTL8366RB_PORT_5 BIT(4) /* In userspace port 4 */
226 #define RTL8366RB_PORT_CPU BIT(5) /* CPU port */
228 #define RTL8366RB_PORT_ALL (RTL8366RB_PORT_1 | \
235 #define RTL8366RB_PORT_ALL_BUT_CPU (RTL8366RB_PORT_1 | \
241 #define RTL8366RB_PORT_ALL_EXTERNAL (RTL8366RB_PORT_1 | \
246 #define RTL8366RB_PORT_ALL_INTERNAL RTL8366RB_PORT_CPU
248 /* First configuration word per member config, VID and prio */
249 #define RTL8366RB_VLAN_VID_MASK 0xfff
250 #define RTL8366RB_VLAN_PRIORITY_SHIFT 12
251 #define RTL8366RB_VLAN_PRIORITY_MASK 0x7
252 /* Second configuration word per member config, member and untagged */
253 #define RTL8366RB_VLAN_UNTAG_SHIFT 8
254 #define RTL8366RB_VLAN_UNTAG_MASK 0xff
255 #define RTL8366RB_VLAN_MEMBER_MASK 0xff
256 /* Third config word per member config, STAG currently unused */
257 #define RTL8366RB_VLAN_STAG_MBR_MASK 0xff
258 #define RTL8366RB_VLAN_STAG_MBR_SHIFT 8
259 #define RTL8366RB_VLAN_STAG_IDX_MASK 0x7
260 #define RTL8366RB_VLAN_STAG_IDX_SHIFT 5
261 #define RTL8366RB_VLAN_FID_MASK 0x7
263 /* Port ingress bandwidth control */
264 #define RTL8366RB_IB_BASE 0x0200
265 #define RTL8366RB_IB_REG(pnum) (RTL8366RB_IB_BASE + (pnum))
266 #define RTL8366RB_IB_BDTH_MASK 0x3fff
267 #define RTL8366RB_IB_PREIFG BIT(14)
269 /* Port egress bandwidth control */
270 #define RTL8366RB_EB_BASE 0x02d1
271 #define RTL8366RB_EB_REG(pnum) (RTL8366RB_EB_BASE + (pnum))
272 #define RTL8366RB_EB_BDTH_MASK 0x3fff
273 #define RTL8366RB_EB_PREIFG_REG 0x02f8
274 #define RTL8366RB_EB_PREIFG BIT(9)
276 #define RTL8366RB_BDTH_SW_MAX 1048512 /* 1048576? */
277 #define RTL8366RB_BDTH_UNIT 64
278 #define RTL8366RB_BDTH_REG_DEFAULT 16383
281 #define RTL8366RB_QOS BIT(15)
282 /* Include/Exclude Preamble and IFG (20 bytes). 0:Exclude, 1:Include. */
283 #define RTL8366RB_QOS_DEFAULT_PREIFG 1
285 /* Interrupt handling */
286 #define RTL8366RB_INTERRUPT_CONTROL_REG 0x0440
287 #define RTL8366RB_INTERRUPT_POLARITY BIT(0)
288 #define RTL8366RB_P4_RGMII_LED BIT(2)
289 #define RTL8366RB_INTERRUPT_MASK_REG 0x0441
290 #define RTL8366RB_INTERRUPT_LINK_CHGALL GENMASK(11, 0)
291 #define RTL8366RB_INTERRUPT_ACLEXCEED BIT(8)
292 #define RTL8366RB_INTERRUPT_STORMEXCEED BIT(9)
293 #define RTL8366RB_INTERRUPT_P4_FIBER BIT(12)
294 #define RTL8366RB_INTERRUPT_P4_UTP BIT(13)
295 #define RTL8366RB_INTERRUPT_VALID (RTL8366RB_INTERRUPT_LINK_CHGALL | \
296 RTL8366RB_INTERRUPT_ACLEXCEED | \
297 RTL8366RB_INTERRUPT_STORMEXCEED | \
298 RTL8366RB_INTERRUPT_P4_FIBER | \
299 RTL8366RB_INTERRUPT_P4_UTP)
300 #define RTL8366RB_INTERRUPT_STATUS_REG 0x0442
301 #define RTL8366RB_NUM_INTERRUPT 14 /* 0..13 */
303 /* bits 0..5 enable force when cleared */
304 #define RTL8366RB_MAC_FORCE_CTRL_REG 0x0F11
306 #define RTL8366RB_OAM_PARSER_REG 0x0F14
307 #define RTL8366RB_OAM_MULTIPLEXER_REG 0x0F15
309 #define RTL8366RB_GREEN_FEATURE_REG 0x0F51
310 #define RTL8366RB_GREEN_FEATURE_MSK 0x0007
311 #define RTL8366RB_GREEN_FEATURE_TX BIT(0)
312 #define RTL8366RB_GREEN_FEATURE_RX BIT(2)
315 * struct rtl8366rb - RTL8366RB-specific data
316 * @max_mtu: per-port max MTU setting
319 unsigned int max_mtu[RTL8366RB_NUM_PORTS];
322 static struct rtl8366_mib_counter rtl8366rb_mib_counters[] = {
323 { 0, 0, 4, "IfInOctets" },
324 { 0, 4, 4, "EtherStatsOctets" },
325 { 0, 8, 2, "EtherStatsUnderSizePkts" },
326 { 0, 10, 2, "EtherFragments" },
327 { 0, 12, 2, "EtherStatsPkts64Octets" },
328 { 0, 14, 2, "EtherStatsPkts65to127Octets" },
329 { 0, 16, 2, "EtherStatsPkts128to255Octets" },
330 { 0, 18, 2, "EtherStatsPkts256to511Octets" },
331 { 0, 20, 2, "EtherStatsPkts512to1023Octets" },
332 { 0, 22, 2, "EtherStatsPkts1024to1518Octets" },
333 { 0, 24, 2, "EtherOversizeStats" },
334 { 0, 26, 2, "EtherStatsJabbers" },
335 { 0, 28, 2, "IfInUcastPkts" },
336 { 0, 30, 2, "EtherStatsMulticastPkts" },
337 { 0, 32, 2, "EtherStatsBroadcastPkts" },
338 { 0, 34, 2, "EtherStatsDropEvents" },
339 { 0, 36, 2, "Dot3StatsFCSErrors" },
340 { 0, 38, 2, "Dot3StatsSymbolErrors" },
341 { 0, 40, 2, "Dot3InPauseFrames" },
342 { 0, 42, 2, "Dot3ControlInUnknownOpcodes" },
343 { 0, 44, 4, "IfOutOctets" },
344 { 0, 48, 2, "Dot3StatsSingleCollisionFrames" },
345 { 0, 50, 2, "Dot3StatMultipleCollisionFrames" },
346 { 0, 52, 2, "Dot3sDeferredTransmissions" },
347 { 0, 54, 2, "Dot3StatsLateCollisions" },
348 { 0, 56, 2, "EtherStatsCollisions" },
349 { 0, 58, 2, "Dot3StatsExcessiveCollisions" },
350 { 0, 60, 2, "Dot3OutPauseFrames" },
351 { 0, 62, 2, "Dot1dBasePortDelayExceededDiscards" },
352 { 0, 64, 2, "Dot1dTpPortInDiscards" },
353 { 0, 66, 2, "IfOutUcastPkts" },
354 { 0, 68, 2, "IfOutMulticastPkts" },
355 { 0, 70, 2, "IfOutBroadcastPkts" },
358 static int rtl8366rb_get_mib_counter(struct realtek_smi *smi,
360 struct rtl8366_mib_counter *mib,
367 addr = RTL8366RB_MIB_COUNTER_BASE +
368 RTL8366RB_MIB_COUNTER_PORT_OFFSET * (port) +
371 /* Writing access counter address first
372 * then ASIC will prepare 64bits counter wait for being retrived
374 ret = regmap_write(smi->map, addr, 0); /* Write whatever */
378 /* Read MIB control register */
379 ret = regmap_read(smi->map, RTL8366RB_MIB_CTRL_REG, &val);
383 if (val & RTL8366RB_MIB_CTRL_BUSY_MASK)
386 if (val & RTL8366RB_MIB_CTRL_RESET_MASK)
389 /* Read each individual MIB 16 bits at the time */
391 for (i = mib->length; i > 0; i--) {
392 ret = regmap_read(smi->map, addr + (i - 1), &val);
395 *mibvalue = (*mibvalue << 16) | (val & 0xFFFF);
400 static u32 rtl8366rb_get_irqmask(struct irq_data *d)
402 int line = irqd_to_hwirq(d);
405 /* For line interrupts we combine link down in bits
406 * 6..11 with link up in bits 0..5 into one interrupt.
409 val = BIT(line) | BIT(line + 6);
415 static void rtl8366rb_mask_irq(struct irq_data *d)
417 struct realtek_smi *smi = irq_data_get_irq_chip_data(d);
420 ret = regmap_update_bits(smi->map, RTL8366RB_INTERRUPT_MASK_REG,
421 rtl8366rb_get_irqmask(d), 0);
423 dev_err(smi->dev, "could not mask IRQ\n");
426 static void rtl8366rb_unmask_irq(struct irq_data *d)
428 struct realtek_smi *smi = irq_data_get_irq_chip_data(d);
431 ret = regmap_update_bits(smi->map, RTL8366RB_INTERRUPT_MASK_REG,
432 rtl8366rb_get_irqmask(d),
433 rtl8366rb_get_irqmask(d));
435 dev_err(smi->dev, "could not unmask IRQ\n");
438 static irqreturn_t rtl8366rb_irq(int irq, void *data)
440 struct realtek_smi *smi = data;
444 /* This clears the IRQ status register */
445 ret = regmap_read(smi->map, RTL8366RB_INTERRUPT_STATUS_REG,
448 dev_err(smi->dev, "can't read interrupt status\n");
451 stat &= RTL8366RB_INTERRUPT_VALID;
455 int line = __ffs(stat);
459 /* For line interrupts we combine link down in bits
460 * 6..11 with link up in bits 0..5 into one interrupt.
462 if (line < 12 && line > 5)
464 child_irq = irq_find_mapping(smi->irqdomain, line);
465 handle_nested_irq(child_irq);
470 static struct irq_chip rtl8366rb_irq_chip = {
472 .irq_mask = rtl8366rb_mask_irq,
473 .irq_unmask = rtl8366rb_unmask_irq,
476 static int rtl8366rb_irq_map(struct irq_domain *domain, unsigned int irq,
477 irq_hw_number_t hwirq)
479 irq_set_chip_data(irq, domain->host_data);
480 irq_set_chip_and_handler(irq, &rtl8366rb_irq_chip, handle_simple_irq);
481 irq_set_nested_thread(irq, 1);
482 irq_set_noprobe(irq);
487 static void rtl8366rb_irq_unmap(struct irq_domain *d, unsigned int irq)
489 irq_set_nested_thread(irq, 0);
490 irq_set_chip_and_handler(irq, NULL, NULL);
491 irq_set_chip_data(irq, NULL);
494 static const struct irq_domain_ops rtl8366rb_irqdomain_ops = {
495 .map = rtl8366rb_irq_map,
496 .unmap = rtl8366rb_irq_unmap,
497 .xlate = irq_domain_xlate_onecell,
500 static int rtl8366rb_setup_cascaded_irq(struct realtek_smi *smi)
502 struct device_node *intc;
503 unsigned long irq_trig;
509 intc = of_get_child_by_name(smi->dev->of_node, "interrupt-controller");
511 dev_err(smi->dev, "missing child interrupt-controller node\n");
514 /* RB8366RB IRQs cascade off this one */
515 irq = of_irq_get(intc, 0);
517 dev_err(smi->dev, "failed to get parent IRQ\n");
518 ret = irq ? irq : -EINVAL;
522 /* This clears the IRQ status register */
523 ret = regmap_read(smi->map, RTL8366RB_INTERRUPT_STATUS_REG,
526 dev_err(smi->dev, "can't read interrupt status\n");
530 /* Fetch IRQ edge information from the descriptor */
531 irq_trig = irqd_get_trigger_type(irq_get_irq_data(irq));
533 case IRQF_TRIGGER_RISING:
534 case IRQF_TRIGGER_HIGH:
535 dev_info(smi->dev, "active high/rising IRQ\n");
538 case IRQF_TRIGGER_FALLING:
539 case IRQF_TRIGGER_LOW:
540 dev_info(smi->dev, "active low/falling IRQ\n");
541 val = RTL8366RB_INTERRUPT_POLARITY;
544 ret = regmap_update_bits(smi->map, RTL8366RB_INTERRUPT_CONTROL_REG,
545 RTL8366RB_INTERRUPT_POLARITY,
548 dev_err(smi->dev, "could not configure IRQ polarity\n");
552 ret = devm_request_threaded_irq(smi->dev, irq, NULL,
553 rtl8366rb_irq, IRQF_ONESHOT,
556 dev_err(smi->dev, "unable to request irq: %d\n", ret);
559 smi->irqdomain = irq_domain_add_linear(intc,
560 RTL8366RB_NUM_INTERRUPT,
561 &rtl8366rb_irqdomain_ops,
563 if (!smi->irqdomain) {
564 dev_err(smi->dev, "failed to create IRQ domain\n");
568 for (i = 0; i < smi->num_ports; i++)
569 irq_set_parent(irq_create_mapping(smi->irqdomain, i), irq);
576 static int rtl8366rb_set_addr(struct realtek_smi *smi)
582 eth_random_addr(addr);
584 dev_info(smi->dev, "set MAC: %02X:%02X:%02X:%02X:%02X:%02X\n",
585 addr[0], addr[1], addr[2], addr[3], addr[4], addr[5]);
586 val = addr[0] << 8 | addr[1];
587 ret = regmap_write(smi->map, RTL8366RB_SMAR0, val);
590 val = addr[2] << 8 | addr[3];
591 ret = regmap_write(smi->map, RTL8366RB_SMAR1, val);
594 val = addr[4] << 8 | addr[5];
595 ret = regmap_write(smi->map, RTL8366RB_SMAR2, val);
602 /* Found in a vendor driver */
604 /* Struct for handling the jam tables' entries */
605 struct rtl8366rb_jam_tbl_entry {
610 /* For the "version 0" early silicon, appear in most source releases */
611 static const struct rtl8366rb_jam_tbl_entry rtl8366rb_init_jam_ver_0[] = {
612 {0x000B, 0x0001}, {0x03A6, 0x0100}, {0x03A7, 0x0001}, {0x02D1, 0x3FFF},
613 {0x02D2, 0x3FFF}, {0x02D3, 0x3FFF}, {0x02D4, 0x3FFF}, {0x02D5, 0x3FFF},
614 {0x02D6, 0x3FFF}, {0x02D7, 0x3FFF}, {0x02D8, 0x3FFF}, {0x022B, 0x0688},
615 {0x022C, 0x0FAC}, {0x03D0, 0x4688}, {0x03D1, 0x01F5}, {0x0000, 0x0830},
616 {0x02F9, 0x0200}, {0x02F7, 0x7FFF}, {0x02F8, 0x03FF}, {0x0080, 0x03E8},
617 {0x0081, 0x00CE}, {0x0082, 0x00DA}, {0x0083, 0x0230}, {0xBE0F, 0x2000},
618 {0x0231, 0x422A}, {0x0232, 0x422A}, {0x0233, 0x422A}, {0x0234, 0x422A},
619 {0x0235, 0x422A}, {0x0236, 0x422A}, {0x0237, 0x422A}, {0x0238, 0x422A},
620 {0x0239, 0x422A}, {0x023A, 0x422A}, {0x023B, 0x422A}, {0x023C, 0x422A},
621 {0x023D, 0x422A}, {0x023E, 0x422A}, {0x023F, 0x422A}, {0x0240, 0x422A},
622 {0x0241, 0x422A}, {0x0242, 0x422A}, {0x0243, 0x422A}, {0x0244, 0x422A},
623 {0x0245, 0x422A}, {0x0246, 0x422A}, {0x0247, 0x422A}, {0x0248, 0x422A},
624 {0x0249, 0x0146}, {0x024A, 0x0146}, {0x024B, 0x0146}, {0xBE03, 0xC961},
625 {0x024D, 0x0146}, {0x024E, 0x0146}, {0x024F, 0x0146}, {0x0250, 0x0146},
626 {0xBE64, 0x0226}, {0x0252, 0x0146}, {0x0253, 0x0146}, {0x024C, 0x0146},
627 {0x0251, 0x0146}, {0x0254, 0x0146}, {0xBE62, 0x3FD0}, {0x0084, 0x0320},
628 {0x0255, 0x0146}, {0x0256, 0x0146}, {0x0257, 0x0146}, {0x0258, 0x0146},
629 {0x0259, 0x0146}, {0x025A, 0x0146}, {0x025B, 0x0146}, {0x025C, 0x0146},
630 {0x025D, 0x0146}, {0x025E, 0x0146}, {0x025F, 0x0146}, {0x0260, 0x0146},
631 {0x0261, 0xA23F}, {0x0262, 0x0294}, {0x0263, 0xA23F}, {0x0264, 0x0294},
632 {0x0265, 0xA23F}, {0x0266, 0x0294}, {0x0267, 0xA23F}, {0x0268, 0x0294},
633 {0x0269, 0xA23F}, {0x026A, 0x0294}, {0x026B, 0xA23F}, {0x026C, 0x0294},
634 {0x026D, 0xA23F}, {0x026E, 0x0294}, {0x026F, 0xA23F}, {0x0270, 0x0294},
635 {0x02F5, 0x0048}, {0xBE09, 0x0E00}, {0xBE1E, 0x0FA0}, {0xBE14, 0x8448},
636 {0xBE15, 0x1007}, {0xBE4A, 0xA284}, {0xC454, 0x3F0B}, {0xC474, 0x3F0B},
637 {0xBE48, 0x3672}, {0xBE4B, 0x17A7}, {0xBE4C, 0x0B15}, {0xBE52, 0x0EDD},
638 {0xBE49, 0x8C00}, {0xBE5B, 0x785C}, {0xBE5C, 0x785C}, {0xBE5D, 0x785C},
639 {0xBE61, 0x368A}, {0xBE63, 0x9B84}, {0xC456, 0xCC13}, {0xC476, 0xCC13},
640 {0xBE65, 0x307D}, {0xBE6D, 0x0005}, {0xBE6E, 0xE120}, {0xBE2E, 0x7BAF},
643 /* This v1 init sequence is from Belkin F5D8235 U-Boot release */
644 static const struct rtl8366rb_jam_tbl_entry rtl8366rb_init_jam_ver_1[] = {
645 {0x0000, 0x0830}, {0x0001, 0x8000}, {0x0400, 0x8130}, {0xBE78, 0x3C3C},
646 {0x0431, 0x5432}, {0xBE37, 0x0CE4}, {0x02FA, 0xFFDF}, {0x02FB, 0xFFE0},
647 {0xC44C, 0x1585}, {0xC44C, 0x1185}, {0xC44C, 0x1585}, {0xC46C, 0x1585},
648 {0xC46C, 0x1185}, {0xC46C, 0x1585}, {0xC451, 0x2135}, {0xC471, 0x2135},
649 {0xBE10, 0x8140}, {0xBE15, 0x0007}, {0xBE6E, 0xE120}, {0xBE69, 0xD20F},
650 {0xBE6B, 0x0320}, {0xBE24, 0xB000}, {0xBE23, 0xFF51}, {0xBE22, 0xDF20},
651 {0xBE21, 0x0140}, {0xBE20, 0x00BB}, {0xBE24, 0xB800}, {0xBE24, 0x0000},
652 {0xBE24, 0x7000}, {0xBE23, 0xFF51}, {0xBE22, 0xDF60}, {0xBE21, 0x0140},
653 {0xBE20, 0x0077}, {0xBE24, 0x7800}, {0xBE24, 0x0000}, {0xBE2E, 0x7B7A},
654 {0xBE36, 0x0CE4}, {0x02F5, 0x0048}, {0xBE77, 0x2940}, {0x000A, 0x83E0},
655 {0xBE79, 0x3C3C}, {0xBE00, 0x1340},
658 /* This v2 init sequence is from Belkin F5D8235 U-Boot release */
659 static const struct rtl8366rb_jam_tbl_entry rtl8366rb_init_jam_ver_2[] = {
660 {0x0450, 0x0000}, {0x0400, 0x8130}, {0x000A, 0x83ED}, {0x0431, 0x5432},
661 {0xC44F, 0x6250}, {0xC46F, 0x6250}, {0xC456, 0x0C14}, {0xC476, 0x0C14},
662 {0xC44C, 0x1C85}, {0xC44C, 0x1885}, {0xC44C, 0x1C85}, {0xC46C, 0x1C85},
663 {0xC46C, 0x1885}, {0xC46C, 0x1C85}, {0xC44C, 0x0885}, {0xC44C, 0x0881},
664 {0xC44C, 0x0885}, {0xC46C, 0x0885}, {0xC46C, 0x0881}, {0xC46C, 0x0885},
665 {0xBE2E, 0x7BA7}, {0xBE36, 0x1000}, {0xBE37, 0x1000}, {0x8000, 0x0001},
666 {0xBE69, 0xD50F}, {0x8000, 0x0000}, {0xBE69, 0xD50F}, {0xBE6E, 0x0320},
667 {0xBE77, 0x2940}, {0xBE78, 0x3C3C}, {0xBE79, 0x3C3C}, {0xBE6E, 0xE120},
668 {0x8000, 0x0001}, {0xBE15, 0x1007}, {0x8000, 0x0000}, {0xBE15, 0x1007},
669 {0xBE14, 0x0448}, {0xBE1E, 0x00A0}, {0xBE10, 0x8160}, {0xBE10, 0x8140},
670 {0xBE00, 0x1340}, {0x0F51, 0x0010},
673 /* Appears in a DDWRT code dump */
674 static const struct rtl8366rb_jam_tbl_entry rtl8366rb_init_jam_ver_3[] = {
675 {0x0000, 0x0830}, {0x0400, 0x8130}, {0x000A, 0x83ED}, {0x0431, 0x5432},
676 {0x0F51, 0x0017}, {0x02F5, 0x0048}, {0x02FA, 0xFFDF}, {0x02FB, 0xFFE0},
677 {0xC456, 0x0C14}, {0xC476, 0x0C14}, {0xC454, 0x3F8B}, {0xC474, 0x3F8B},
678 {0xC450, 0x2071}, {0xC470, 0x2071}, {0xC451, 0x226B}, {0xC471, 0x226B},
679 {0xC452, 0xA293}, {0xC472, 0xA293}, {0xC44C, 0x1585}, {0xC44C, 0x1185},
680 {0xC44C, 0x1585}, {0xC46C, 0x1585}, {0xC46C, 0x1185}, {0xC46C, 0x1585},
681 {0xC44C, 0x0185}, {0xC44C, 0x0181}, {0xC44C, 0x0185}, {0xC46C, 0x0185},
682 {0xC46C, 0x0181}, {0xC46C, 0x0185}, {0xBE24, 0xB000}, {0xBE23, 0xFF51},
683 {0xBE22, 0xDF20}, {0xBE21, 0x0140}, {0xBE20, 0x00BB}, {0xBE24, 0xB800},
684 {0xBE24, 0x0000}, {0xBE24, 0x7000}, {0xBE23, 0xFF51}, {0xBE22, 0xDF60},
685 {0xBE21, 0x0140}, {0xBE20, 0x0077}, {0xBE24, 0x7800}, {0xBE24, 0x0000},
686 {0xBE2E, 0x7BA7}, {0xBE36, 0x1000}, {0xBE37, 0x1000}, {0x8000, 0x0001},
687 {0xBE69, 0xD50F}, {0x8000, 0x0000}, {0xBE69, 0xD50F}, {0xBE6B, 0x0320},
688 {0xBE77, 0x2800}, {0xBE78, 0x3C3C}, {0xBE79, 0x3C3C}, {0xBE6E, 0xE120},
689 {0x8000, 0x0001}, {0xBE10, 0x8140}, {0x8000, 0x0000}, {0xBE10, 0x8140},
690 {0xBE15, 0x1007}, {0xBE14, 0x0448}, {0xBE1E, 0x00A0}, {0xBE10, 0x8160},
691 {0xBE10, 0x8140}, {0xBE00, 0x1340}, {0x0450, 0x0000}, {0x0401, 0x0000},
694 /* Belkin F5D8235 v1, "belkin,f5d8235-v1" */
695 static const struct rtl8366rb_jam_tbl_entry rtl8366rb_init_jam_f5d8235[] = {
696 {0x0242, 0x02BF}, {0x0245, 0x02BF}, {0x0248, 0x02BF}, {0x024B, 0x02BF},
697 {0x024E, 0x02BF}, {0x0251, 0x02BF}, {0x0254, 0x0A3F}, {0x0256, 0x0A3F},
698 {0x0258, 0x0A3F}, {0x025A, 0x0A3F}, {0x025C, 0x0A3F}, {0x025E, 0x0A3F},
699 {0x0263, 0x007C}, {0x0100, 0x0004}, {0xBE5B, 0x3500}, {0x800E, 0x200F},
700 {0xBE1D, 0x0F00}, {0x8001, 0x5011}, {0x800A, 0xA2F4}, {0x800B, 0x17A3},
701 {0xBE4B, 0x17A3}, {0xBE41, 0x5011}, {0xBE17, 0x2100}, {0x8000, 0x8304},
702 {0xBE40, 0x8304}, {0xBE4A, 0xA2F4}, {0x800C, 0xA8D5}, {0x8014, 0x5500},
703 {0x8015, 0x0004}, {0xBE4C, 0xA8D5}, {0xBE59, 0x0008}, {0xBE09, 0x0E00},
704 {0xBE36, 0x1036}, {0xBE37, 0x1036}, {0x800D, 0x00FF}, {0xBE4D, 0x00FF},
707 /* DGN3500, "netgear,dgn3500", "netgear,dgn3500b" */
708 static const struct rtl8366rb_jam_tbl_entry rtl8366rb_init_jam_dgn3500[] = {
709 {0x0000, 0x0830}, {0x0400, 0x8130}, {0x000A, 0x83ED}, {0x0F51, 0x0017},
710 {0x02F5, 0x0048}, {0x02FA, 0xFFDF}, {0x02FB, 0xFFE0}, {0x0450, 0x0000},
711 {0x0401, 0x0000}, {0x0431, 0x0960},
714 /* This jam table activates "green ethernet", which means low power mode
715 * and is claimed to detect the cable length and not use more power than
716 * necessary, and the ports should enter power saving mode 10 seconds after
717 * a cable is disconnected. Seems to always be the same.
719 static const struct rtl8366rb_jam_tbl_entry rtl8366rb_green_jam[] = {
720 {0xBE78, 0x323C}, {0xBE77, 0x5000}, {0xBE2E, 0x7BA7},
721 {0xBE59, 0x3459}, {0xBE5A, 0x745A}, {0xBE5B, 0x785C},
722 {0xBE5C, 0x785C}, {0xBE6E, 0xE120}, {0xBE79, 0x323C},
725 /* Function that jams the tables in the proper registers */
726 static int rtl8366rb_jam_table(const struct rtl8366rb_jam_tbl_entry *jam_table,
727 int jam_size, struct realtek_smi *smi,
734 for (i = 0; i < jam_size; i++) {
735 if ((jam_table[i].reg & 0xBE00) == 0xBE00) {
736 ret = regmap_read(smi->map,
737 RTL8366RB_PHY_ACCESS_BUSY_REG,
741 if (!(val & RTL8366RB_PHY_INT_BUSY)) {
742 ret = regmap_write(smi->map,
743 RTL8366RB_PHY_ACCESS_CTRL_REG,
744 RTL8366RB_PHY_CTRL_WRITE);
750 dev_dbg(smi->dev, "jam %04x into register %04x\n",
753 ret = regmap_write(smi->map,
762 static int rtl8366rb_setup(struct dsa_switch *ds)
764 struct realtek_smi *smi = ds->priv;
765 const struct rtl8366rb_jam_tbl_entry *jam_table;
766 struct rtl8366rb *rb;
776 ret = regmap_read(smi->map, RTL8366RB_CHIP_ID_REG, &chip_id);
778 dev_err(smi->dev, "unable to read chip id\n");
783 case RTL8366RB_CHIP_ID_8366:
786 dev_err(smi->dev, "unknown chip id (%04x)\n", chip_id);
790 ret = regmap_read(smi->map, RTL8366RB_CHIP_VERSION_CTRL_REG,
793 dev_err(smi->dev, "unable to read chip version\n");
797 dev_info(smi->dev, "RTL%04x ver %u chip found\n",
798 chip_id, chip_ver & RTL8366RB_CHIP_VERSION_MASK);
800 /* Do the init dance using the right jam table */
803 jam_table = rtl8366rb_init_jam_ver_0;
804 jam_size = ARRAY_SIZE(rtl8366rb_init_jam_ver_0);
807 jam_table = rtl8366rb_init_jam_ver_1;
808 jam_size = ARRAY_SIZE(rtl8366rb_init_jam_ver_1);
811 jam_table = rtl8366rb_init_jam_ver_2;
812 jam_size = ARRAY_SIZE(rtl8366rb_init_jam_ver_2);
815 jam_table = rtl8366rb_init_jam_ver_3;
816 jam_size = ARRAY_SIZE(rtl8366rb_init_jam_ver_3);
820 /* Special jam tables for special routers
821 * TODO: are these necessary? Maintainers, please test
822 * without them, using just the off-the-shelf tables.
824 if (of_machine_is_compatible("belkin,f5d8235-v1")) {
825 jam_table = rtl8366rb_init_jam_f5d8235;
826 jam_size = ARRAY_SIZE(rtl8366rb_init_jam_f5d8235);
828 if (of_machine_is_compatible("netgear,dgn3500") ||
829 of_machine_is_compatible("netgear,dgn3500b")) {
830 jam_table = rtl8366rb_init_jam_dgn3500;
831 jam_size = ARRAY_SIZE(rtl8366rb_init_jam_dgn3500);
834 ret = rtl8366rb_jam_table(jam_table, jam_size, smi, true);
838 /* Set up the "green ethernet" feature */
839 ret = rtl8366rb_jam_table(rtl8366rb_green_jam,
840 ARRAY_SIZE(rtl8366rb_green_jam), smi, false);
844 ret = regmap_write(smi->map,
845 RTL8366RB_GREEN_FEATURE_REG,
846 (chip_ver == 1) ? 0x0007 : 0x0003);
850 /* Vendor driver sets 0x240 in registers 0xc and 0xd (undocumented) */
851 ret = regmap_write(smi->map, 0x0c, 0x240);
854 ret = regmap_write(smi->map, 0x0d, 0x240);
858 /* Set some random MAC address */
859 ret = rtl8366rb_set_addr(smi);
863 /* Enable CPU port with custom DSA tag 8899.
865 * If you set RTL8368RB_CPU_NO_TAG (bit 15) in this registers
866 * the custom tag is turned off.
868 ret = regmap_update_bits(smi->map, RTL8368RB_CPU_CTRL_REG,
874 /* Make sure we default-enable the fixed CPU port */
875 ret = regmap_update_bits(smi->map, RTL8366RB_PECR,
881 /* Set maximum packet length to 1536 bytes */
882 ret = regmap_update_bits(smi->map, RTL8366RB_SGCR,
883 RTL8366RB_SGCR_MAX_LENGTH_MASK,
884 RTL8366RB_SGCR_MAX_LENGTH_1536);
887 for (i = 0; i < RTL8366RB_NUM_PORTS; i++)
888 /* layer 2 size, see rtl8366rb_change_mtu() */
889 rb->max_mtu[i] = 1532;
891 /* Enable learning for all ports */
892 ret = regmap_write(smi->map, RTL8366RB_SSCR0, 0);
896 /* Enable auto ageing for all ports */
897 ret = regmap_write(smi->map, RTL8366RB_SSCR1, 0);
901 /* Port 4 setup: this enables Port 4, usually the WAN port,
902 * common PHY IO mode is apparently mode 0, and this is not what
903 * the port is initialized to. There is no explanation of the
904 * IO modes in the Realtek source code, if your WAN port is
905 * connected to something exotic such as fiber, then this might
906 * be worth experimenting with.
908 ret = regmap_update_bits(smi->map, RTL8366RB_PMC0,
909 RTL8366RB_PMC0_P4_IOMODE_MASK,
910 0 << RTL8366RB_PMC0_P4_IOMODE_SHIFT);
914 /* Discard VLAN tagged packets if the port is not a member of
915 * the VLAN with which the packets is associated.
917 ret = regmap_write(smi->map, RTL8366RB_VLAN_INGRESS_CTRL2_REG,
922 /* Don't drop packets whose DA has not been learned */
923 ret = regmap_update_bits(smi->map, RTL8366RB_SSCR2,
924 RTL8366RB_SSCR2_DROP_UNKNOWN_DA, 0);
928 /* Set blinking, TODO: make this configurable */
929 ret = regmap_update_bits(smi->map, RTL8366RB_LED_BLINKRATE_REG,
930 RTL8366RB_LED_BLINKRATE_MASK,
931 RTL8366RB_LED_BLINKRATE_56MS);
935 /* Set up LED activity:
936 * Each port has 4 LEDs, we configure all ports to the same
937 * behaviour (no individual config) but we can set up each
940 if (smi->leds_disabled) {
941 /* Turn everything off */
942 regmap_update_bits(smi->map,
943 RTL8366RB_LED_0_1_CTRL_REG,
945 regmap_update_bits(smi->map,
946 RTL8366RB_LED_2_3_CTRL_REG,
948 regmap_update_bits(smi->map,
949 RTL8366RB_INTERRUPT_CONTROL_REG,
950 RTL8366RB_P4_RGMII_LED,
952 val = RTL8366RB_LED_OFF;
954 /* TODO: make this configurable per LED */
955 val = RTL8366RB_LED_FORCE;
957 for (i = 0; i < 4; i++) {
958 ret = regmap_update_bits(smi->map,
959 RTL8366RB_LED_CTRL_REG,
966 ret = rtl8366_init_vlan(smi);
970 ret = rtl8366rb_setup_cascaded_irq(smi);
972 dev_info(smi->dev, "no interrupt support\n");
974 ret = realtek_smi_setup_mdio(smi);
976 dev_info(smi->dev, "could not set up MDIO bus\n");
980 ds->configure_vlan_while_not_filtering = false;
985 static enum dsa_tag_protocol rtl8366_get_tag_protocol(struct dsa_switch *ds,
987 enum dsa_tag_protocol mp)
989 /* This switch uses the 4 byte protocol A Realtek DSA tag */
990 return DSA_TAG_PROTO_RTL4_A;
994 rtl8366rb_mac_link_up(struct dsa_switch *ds, int port, unsigned int mode,
995 phy_interface_t interface, struct phy_device *phydev,
996 int speed, int duplex, bool tx_pause, bool rx_pause)
998 struct realtek_smi *smi = ds->priv;
1001 if (port != smi->cpu_port)
1004 dev_dbg(smi->dev, "MAC link up on CPU port (%d)\n", port);
1006 /* Force the fixed CPU port into 1Gbit mode, no autonegotiation */
1007 ret = regmap_update_bits(smi->map, RTL8366RB_MAC_FORCE_CTRL_REG,
1008 BIT(port), BIT(port));
1010 dev_err(smi->dev, "failed to force 1Gbit on CPU port\n");
1014 ret = regmap_update_bits(smi->map, RTL8366RB_PAACR2,
1016 RTL8366RB_PAACR_CPU_PORT << 8);
1018 dev_err(smi->dev, "failed to set PAACR on CPU port\n");
1022 /* Enable the CPU port */
1023 ret = regmap_update_bits(smi->map, RTL8366RB_PECR, BIT(port),
1026 dev_err(smi->dev, "failed to enable the CPU port\n");
1032 rtl8366rb_mac_link_down(struct dsa_switch *ds, int port, unsigned int mode,
1033 phy_interface_t interface)
1035 struct realtek_smi *smi = ds->priv;
1038 if (port != smi->cpu_port)
1041 dev_dbg(smi->dev, "MAC link down on CPU port (%d)\n", port);
1043 /* Disable the CPU port */
1044 ret = regmap_update_bits(smi->map, RTL8366RB_PECR, BIT(port),
1047 dev_err(smi->dev, "failed to disable the CPU port\n");
1052 static void rb8366rb_set_port_led(struct realtek_smi *smi,
1053 int port, bool enable)
1055 u16 val = enable ? 0x3f : 0;
1058 if (smi->leds_disabled)
1063 ret = regmap_update_bits(smi->map,
1064 RTL8366RB_LED_0_1_CTRL_REG,
1068 ret = regmap_update_bits(smi->map,
1069 RTL8366RB_LED_0_1_CTRL_REG,
1070 0x3F << RTL8366RB_LED_1_OFFSET,
1071 val << RTL8366RB_LED_1_OFFSET);
1074 ret = regmap_update_bits(smi->map,
1075 RTL8366RB_LED_2_3_CTRL_REG,
1079 ret = regmap_update_bits(smi->map,
1080 RTL8366RB_LED_2_3_CTRL_REG,
1081 0x3F << RTL8366RB_LED_3_OFFSET,
1082 val << RTL8366RB_LED_3_OFFSET);
1085 ret = regmap_update_bits(smi->map,
1086 RTL8366RB_INTERRUPT_CONTROL_REG,
1087 RTL8366RB_P4_RGMII_LED,
1088 enable ? RTL8366RB_P4_RGMII_LED : 0);
1091 dev_err(smi->dev, "no LED for port %d\n", port);
1095 dev_err(smi->dev, "error updating LED on port %d\n", port);
1099 rtl8366rb_port_enable(struct dsa_switch *ds, int port,
1100 struct phy_device *phy)
1102 struct realtek_smi *smi = ds->priv;
1105 dev_dbg(smi->dev, "enable port %d\n", port);
1106 ret = regmap_update_bits(smi->map, RTL8366RB_PECR, BIT(port),
1111 rb8366rb_set_port_led(smi, port, true);
1116 rtl8366rb_port_disable(struct dsa_switch *ds, int port)
1118 struct realtek_smi *smi = ds->priv;
1121 dev_dbg(smi->dev, "disable port %d\n", port);
1122 ret = regmap_update_bits(smi->map, RTL8366RB_PECR, BIT(port),
1127 rb8366rb_set_port_led(smi, port, false);
1130 static int rtl8366rb_change_mtu(struct dsa_switch *ds, int port, int new_mtu)
1132 struct realtek_smi *smi = ds->priv;
1133 struct rtl8366rb *rb;
1134 unsigned int max_mtu;
1138 /* Cache the per-port MTU setting */
1139 rb = smi->chip_data;
1140 rb->max_mtu[port] = new_mtu;
1142 /* Roof out the MTU for the entire switch to the greatest
1143 * common denominator: the biggest set for any one port will
1144 * be the biggest MTU for the switch.
1146 * The first setting, 1522 bytes, is max IP packet 1500 bytes,
1147 * plus ethernet header, 1518 bytes, plus CPU tag, 4 bytes.
1148 * This function should consider the parameter an SDU, so the
1149 * MTU passed for this setting is 1518 bytes. The same logic
1150 * of subtracting the DSA tag of 4 bytes apply to the other
1154 for (i = 0; i < RTL8366RB_NUM_PORTS; i++) {
1155 if (rb->max_mtu[i] > max_mtu)
1156 max_mtu = rb->max_mtu[i];
1158 if (max_mtu <= 1518)
1159 len = RTL8366RB_SGCR_MAX_LENGTH_1522;
1160 else if (max_mtu > 1518 && max_mtu <= 1532)
1161 len = RTL8366RB_SGCR_MAX_LENGTH_1536;
1162 else if (max_mtu > 1532 && max_mtu <= 1548)
1163 len = RTL8366RB_SGCR_MAX_LENGTH_1552;
1165 len = RTL8366RB_SGCR_MAX_LENGTH_16000;
1167 return regmap_update_bits(smi->map, RTL8366RB_SGCR,
1168 RTL8366RB_SGCR_MAX_LENGTH_MASK,
1172 static int rtl8366rb_max_mtu(struct dsa_switch *ds, int port)
1174 /* The max MTU is 16000 bytes, so we subtract the CPU tag
1175 * and the max presented to the system is 15996 bytes.
1180 static int rtl8366rb_get_vlan_4k(struct realtek_smi *smi, u32 vid,
1181 struct rtl8366_vlan_4k *vlan4k)
1187 memset(vlan4k, '\0', sizeof(struct rtl8366_vlan_4k));
1189 if (vid >= RTL8366RB_NUM_VIDS)
1193 ret = regmap_write(smi->map, RTL8366RB_VLAN_TABLE_WRITE_BASE,
1194 vid & RTL8366RB_VLAN_VID_MASK);
1198 /* write table access control word */
1199 ret = regmap_write(smi->map, RTL8366RB_TABLE_ACCESS_CTRL_REG,
1200 RTL8366RB_TABLE_VLAN_READ_CTRL);
1204 for (i = 0; i < 3; i++) {
1205 ret = regmap_read(smi->map,
1206 RTL8366RB_VLAN_TABLE_READ_BASE + i,
1213 vlan4k->untag = (data[1] >> RTL8366RB_VLAN_UNTAG_SHIFT) &
1214 RTL8366RB_VLAN_UNTAG_MASK;
1215 vlan4k->member = data[1] & RTL8366RB_VLAN_MEMBER_MASK;
1216 vlan4k->fid = data[2] & RTL8366RB_VLAN_FID_MASK;
1221 static int rtl8366rb_set_vlan_4k(struct realtek_smi *smi,
1222 const struct rtl8366_vlan_4k *vlan4k)
1228 if (vlan4k->vid >= RTL8366RB_NUM_VIDS ||
1229 vlan4k->member > RTL8366RB_VLAN_MEMBER_MASK ||
1230 vlan4k->untag > RTL8366RB_VLAN_UNTAG_MASK ||
1231 vlan4k->fid > RTL8366RB_FIDMAX)
1234 data[0] = vlan4k->vid & RTL8366RB_VLAN_VID_MASK;
1235 data[1] = (vlan4k->member & RTL8366RB_VLAN_MEMBER_MASK) |
1236 ((vlan4k->untag & RTL8366RB_VLAN_UNTAG_MASK) <<
1237 RTL8366RB_VLAN_UNTAG_SHIFT);
1238 data[2] = vlan4k->fid & RTL8366RB_VLAN_FID_MASK;
1240 for (i = 0; i < 3; i++) {
1241 ret = regmap_write(smi->map,
1242 RTL8366RB_VLAN_TABLE_WRITE_BASE + i,
1248 /* write table access control word */
1249 ret = regmap_write(smi->map, RTL8366RB_TABLE_ACCESS_CTRL_REG,
1250 RTL8366RB_TABLE_VLAN_WRITE_CTRL);
1255 static int rtl8366rb_get_vlan_mc(struct realtek_smi *smi, u32 index,
1256 struct rtl8366_vlan_mc *vlanmc)
1262 memset(vlanmc, '\0', sizeof(struct rtl8366_vlan_mc));
1264 if (index >= RTL8366RB_NUM_VLANS)
1267 for (i = 0; i < 3; i++) {
1268 ret = regmap_read(smi->map,
1269 RTL8366RB_VLAN_MC_BASE(index) + i,
1275 vlanmc->vid = data[0] & RTL8366RB_VLAN_VID_MASK;
1276 vlanmc->priority = (data[0] >> RTL8366RB_VLAN_PRIORITY_SHIFT) &
1277 RTL8366RB_VLAN_PRIORITY_MASK;
1278 vlanmc->untag = (data[1] >> RTL8366RB_VLAN_UNTAG_SHIFT) &
1279 RTL8366RB_VLAN_UNTAG_MASK;
1280 vlanmc->member = data[1] & RTL8366RB_VLAN_MEMBER_MASK;
1281 vlanmc->fid = data[2] & RTL8366RB_VLAN_FID_MASK;
1286 static int rtl8366rb_set_vlan_mc(struct realtek_smi *smi, u32 index,
1287 const struct rtl8366_vlan_mc *vlanmc)
1293 if (index >= RTL8366RB_NUM_VLANS ||
1294 vlanmc->vid >= RTL8366RB_NUM_VIDS ||
1295 vlanmc->priority > RTL8366RB_PRIORITYMAX ||
1296 vlanmc->member > RTL8366RB_VLAN_MEMBER_MASK ||
1297 vlanmc->untag > RTL8366RB_VLAN_UNTAG_MASK ||
1298 vlanmc->fid > RTL8366RB_FIDMAX)
1301 data[0] = (vlanmc->vid & RTL8366RB_VLAN_VID_MASK) |
1302 ((vlanmc->priority & RTL8366RB_VLAN_PRIORITY_MASK) <<
1303 RTL8366RB_VLAN_PRIORITY_SHIFT);
1304 data[1] = (vlanmc->member & RTL8366RB_VLAN_MEMBER_MASK) |
1305 ((vlanmc->untag & RTL8366RB_VLAN_UNTAG_MASK) <<
1306 RTL8366RB_VLAN_UNTAG_SHIFT);
1307 data[2] = vlanmc->fid & RTL8366RB_VLAN_FID_MASK;
1309 for (i = 0; i < 3; i++) {
1310 ret = regmap_write(smi->map,
1311 RTL8366RB_VLAN_MC_BASE(index) + i,
1320 static int rtl8366rb_get_mc_index(struct realtek_smi *smi, int port, int *val)
1325 if (port >= smi->num_ports)
1328 ret = regmap_read(smi->map, RTL8366RB_PORT_VLAN_CTRL_REG(port),
1333 *val = (data >> RTL8366RB_PORT_VLAN_CTRL_SHIFT(port)) &
1334 RTL8366RB_PORT_VLAN_CTRL_MASK;
1339 static int rtl8366rb_set_mc_index(struct realtek_smi *smi, int port, int index)
1341 if (port >= smi->num_ports || index >= RTL8366RB_NUM_VLANS)
1344 return regmap_update_bits(smi->map, RTL8366RB_PORT_VLAN_CTRL_REG(port),
1345 RTL8366RB_PORT_VLAN_CTRL_MASK <<
1346 RTL8366RB_PORT_VLAN_CTRL_SHIFT(port),
1347 (index & RTL8366RB_PORT_VLAN_CTRL_MASK) <<
1348 RTL8366RB_PORT_VLAN_CTRL_SHIFT(port));
1351 static bool rtl8366rb_is_vlan_valid(struct realtek_smi *smi, unsigned int vlan)
1353 unsigned int max = RTL8366RB_NUM_VLANS;
1355 if (smi->vlan4k_enabled)
1356 max = RTL8366RB_NUM_VIDS - 1;
1358 if (vlan == 0 || vlan > max)
1364 static int rtl8366rb_enable_vlan(struct realtek_smi *smi, bool enable)
1366 dev_dbg(smi->dev, "%s VLAN\n", enable ? "enable" : "disable");
1367 return regmap_update_bits(smi->map,
1368 RTL8366RB_SGCR, RTL8366RB_SGCR_EN_VLAN,
1369 enable ? RTL8366RB_SGCR_EN_VLAN : 0);
1372 static int rtl8366rb_enable_vlan4k(struct realtek_smi *smi, bool enable)
1374 dev_dbg(smi->dev, "%s VLAN 4k\n", enable ? "enable" : "disable");
1375 return regmap_update_bits(smi->map, RTL8366RB_SGCR,
1376 RTL8366RB_SGCR_EN_VLAN_4KTB,
1377 enable ? RTL8366RB_SGCR_EN_VLAN_4KTB : 0);
1380 static int rtl8366rb_phy_read(struct realtek_smi *smi, int phy, int regnum)
1386 if (phy > RTL8366RB_PHY_NO_MAX)
1389 ret = regmap_write(smi->map, RTL8366RB_PHY_ACCESS_CTRL_REG,
1390 RTL8366RB_PHY_CTRL_READ);
1394 reg = 0x8000 | (1 << (phy + RTL8366RB_PHY_NO_OFFSET)) | regnum;
1396 ret = regmap_write(smi->map, reg, 0);
1399 "failed to write PHY%d reg %04x @ %04x, ret %d\n",
1400 phy, regnum, reg, ret);
1404 ret = regmap_read(smi->map, RTL8366RB_PHY_ACCESS_DATA_REG, &val);
1408 dev_dbg(smi->dev, "read PHY%d register 0x%04x @ %08x, val <- %04x\n",
1409 phy, regnum, reg, val);
1414 static int rtl8366rb_phy_write(struct realtek_smi *smi, int phy, int regnum,
1420 if (phy > RTL8366RB_PHY_NO_MAX)
1423 ret = regmap_write(smi->map, RTL8366RB_PHY_ACCESS_CTRL_REG,
1424 RTL8366RB_PHY_CTRL_WRITE);
1428 reg = 0x8000 | (1 << (phy + RTL8366RB_PHY_NO_OFFSET)) | regnum;
1430 dev_dbg(smi->dev, "write PHY%d register 0x%04x @ %04x, val -> %04x\n",
1431 phy, regnum, reg, val);
1433 ret = regmap_write(smi->map, reg, val);
1440 static int rtl8366rb_reset_chip(struct realtek_smi *smi)
1446 realtek_smi_write_reg_noack(smi, RTL8366RB_RESET_CTRL_REG,
1447 RTL8366RB_CHIP_CTRL_RESET_HW);
1449 usleep_range(20000, 25000);
1450 ret = regmap_read(smi->map, RTL8366RB_RESET_CTRL_REG, &val);
1454 if (!(val & RTL8366RB_CHIP_CTRL_RESET_HW))
1456 } while (--timeout);
1459 dev_err(smi->dev, "timeout waiting for the switch to reset\n");
1466 static int rtl8366rb_detect(struct realtek_smi *smi)
1468 struct device *dev = smi->dev;
1473 ret = regmap_read(smi->map, 0x5c, &val);
1475 dev_err(dev, "can't get chip ID (%d)\n", ret);
1481 dev_info(dev, "found an RTL8366S switch\n");
1482 dev_err(dev, "this switch is not yet supported, submit patches!\n");
1485 dev_info(dev, "found an RTL8366RB switch\n");
1486 smi->cpu_port = RTL8366RB_PORT_NUM_CPU;
1487 smi->num_ports = RTL8366RB_NUM_PORTS;
1488 smi->num_vlan_mc = RTL8366RB_NUM_VLANS;
1489 smi->mib_counters = rtl8366rb_mib_counters;
1490 smi->num_mib_counters = ARRAY_SIZE(rtl8366rb_mib_counters);
1493 dev_info(dev, "found an Unknown Realtek switch (id=0x%04x)\n",
1498 ret = rtl8366rb_reset_chip(smi);
1505 static const struct dsa_switch_ops rtl8366rb_switch_ops = {
1506 .get_tag_protocol = rtl8366_get_tag_protocol,
1507 .setup = rtl8366rb_setup,
1508 .phylink_mac_link_up = rtl8366rb_mac_link_up,
1509 .phylink_mac_link_down = rtl8366rb_mac_link_down,
1510 .get_strings = rtl8366_get_strings,
1511 .get_ethtool_stats = rtl8366_get_ethtool_stats,
1512 .get_sset_count = rtl8366_get_sset_count,
1513 .port_vlan_filtering = rtl8366_vlan_filtering,
1514 .port_vlan_add = rtl8366_vlan_add,
1515 .port_vlan_del = rtl8366_vlan_del,
1516 .port_enable = rtl8366rb_port_enable,
1517 .port_disable = rtl8366rb_port_disable,
1518 .port_change_mtu = rtl8366rb_change_mtu,
1519 .port_max_mtu = rtl8366rb_max_mtu,
1522 static const struct realtek_smi_ops rtl8366rb_smi_ops = {
1523 .detect = rtl8366rb_detect,
1524 .get_vlan_mc = rtl8366rb_get_vlan_mc,
1525 .set_vlan_mc = rtl8366rb_set_vlan_mc,
1526 .get_vlan_4k = rtl8366rb_get_vlan_4k,
1527 .set_vlan_4k = rtl8366rb_set_vlan_4k,
1528 .get_mc_index = rtl8366rb_get_mc_index,
1529 .set_mc_index = rtl8366rb_set_mc_index,
1530 .get_mib_counter = rtl8366rb_get_mib_counter,
1531 .is_vlan_valid = rtl8366rb_is_vlan_valid,
1532 .enable_vlan = rtl8366rb_enable_vlan,
1533 .enable_vlan4k = rtl8366rb_enable_vlan4k,
1534 .phy_read = rtl8366rb_phy_read,
1535 .phy_write = rtl8366rb_phy_write,
1538 const struct realtek_smi_variant rtl8366rb_variant = {
1539 .ds_ops = &rtl8366rb_switch_ops,
1540 .ops = &rtl8366rb_smi_ops,
1544 .chip_data_sz = sizeof(struct rtl8366rb),
1546 EXPORT_SYMBOL_GPL(rtl8366rb_variant);