drivers/net/dsa/realtek/rtl8365mb.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /* Realtek SMI subdriver for the Realtek RTL8365MB-VC ethernet switch.
   3  *
   4  * Copyright (C) 2021 Alvin Šipraga <alsi@bang-olufsen.dk>
   5  * Copyright (C) 2021 Michael Rasmussen <mir@bang-olufsen.dk>
   6  *
   7  * The RTL8365MB-VC is a 4+1 port 10/100/1000M switch controller. It includes 4
   8  * integrated PHYs for the user facing ports, and an extension interface which
   9  * can be connected to the CPU - or another PHY - via either MII, RMII, or
  10  * RGMII. The switch is configured via the Realtek Simple Management Interface
  11  * (SMI), which uses the MDIO/MDC lines.
  12  *
  13  * Below is a simplified block diagram of the chip and its relevant interfaces.
  14  *
  15  *                          .-----------------------------------.
  16  *                          |                                   |
  17  *         UTP <---------------> Giga PHY <-> PCS <-> P0 GMAC   |
  18  *         UTP <---------------> Giga PHY <-> PCS <-> P1 GMAC   |
  19  *         UTP <---------------> Giga PHY <-> PCS <-> P2 GMAC   |
  20  *         UTP <---------------> Giga PHY <-> PCS <-> P3 GMAC   |
  21  *                          |                                   |
  22  *     CPU/PHY <-MII/RMII/RGMII--->  Extension  <---> Extension |
  23  *                          |       interface 1        GMAC 1   |
  24  *                          |                                   |
  25  *     SMI driver/ <-MDC/SCL---> Management    ~~~~~~~~~~~~~~   |
  26  *        EEPROM   <-MDIO/SDA--> interface     ~REALTEK ~~~~~   |
  27  *                          |                  ~RTL8365MB ~~~   |
  28  *                          |                  ~GXXXC TAIWAN~   |
  29  *        GPIO <--------------> Reset          ~~~~~~~~~~~~~~   |
  30  *                          |                                   |
  31  *      Interrupt  <----------> Link UP/DOWN events             |
  32  *      controller          |                                   |
  33  *                          '-----------------------------------'
  34  *
  35  * The driver uses DSA to integrate the 4 user and 1 extension ports into the
  36  * kernel. Netdevices are created for the user ports, as are PHY devices for
  37  * their integrated PHYs. The device tree firmware should also specify the link
  38  * partner of the extension port - either via a fixed-link or other phy-handle.
  39  * See the device tree bindings for more detailed information. Note that the
  40  * driver has only been tested with a fixed-link, but in principle it should not
  41  * matter.
  42  *
  43  * NOTE: Currently, only the RGMII interface is implemented in this driver.
  44  *
  45  * The interrupt line is asserted on link UP/DOWN events. The driver creates a
  46  * custom irqchip to handle this interrupt and demultiplex the events by reading
  47  * the status registers via SMI. Interrupts are then propagated to the relevant
  48  * PHY device.
  49  *
  50  * The EEPROM contains initial register values which the chip will read over I2C
  51  * upon hardware reset. It is also possible to omit the EEPROM. In both cases,
  52  * the driver will manually reprogram some registers using jam tables to reach
  53  * an initial state defined by the vendor driver.
  54  *
  55  * This Linux driver is written based on an OS-agnostic vendor driver from
  56  * Realtek. The reference GPL-licensed sources can be found in the OpenWrt
  57  * source tree under the name rtl8367c. The vendor driver claims to support a
  58  * number of similar switch controllers from Realtek, but the only hardware we
  59  * have is the RTL8365MB-VC. Moreover, there does not seem to be any chip under
  60  * the name RTL8367C. Although one wishes that the 'C' stood for some kind of
  61  * common hardware revision, there exist examples of chips with the suffix -VC
  62  * which are explicitly not supported by the rtl8367c driver and which instead
  63  * require the rtl8367d vendor driver. With all this uncertainty, the driver has
  64  * been modestly named rtl8365mb. Future implementors may wish to rename things
  65  * accordingly.
  66  *
  67  * In the same family of chips, some carry up to 8 user ports and up to 2
  68  * extension ports. Where possible this driver tries to make things generic, but
  69  * more work must be done to support these configurations. According to
  70  * documentation from Realtek, the family should include the following chips:
  71  *
  72  *  - RTL8363NB
  73  *  - RTL8363NB-VB
  74  *  - RTL8363SC
  75  *  - RTL8363SC-VB
  76  *  - RTL8364NB
  77  *  - RTL8364NB-VB
  78  *  - RTL8365MB-VC
  79  *  - RTL8366SC
  80  *  - RTL8367RB-VB
  81  *  - RTL8367SB
  82  *  - RTL8367S
  83  *  - RTL8370MB
  84  *  - RTL8310SR
  85  *
  86  * Some of the register logic for these additional chips has been skipped over
  87  * while implementing this driver. It is therefore not possible to assume that
  88  * things will work out-of-the-box for other chips, and a careful review of the
  89  * vendor driver may be needed to expand support. The RTL8365MB-VC seems to be
  90  * one of the simpler chips.
  91  */
  92
  93 #include <linux/bitfield.h>
  94 #include <linux/bitops.h>
  95 #include <linux/interrupt.h>
  96 #include <linux/irqdomain.h>
  97 #include <linux/mutex.h>
  98 #include <linux/of_irq.h>
  99 #include <linux/regmap.h>
 100 #include <linux/if_bridge.h>
 101
 102 #include "realtek.h"
 103
 104 /* Chip-specific data and limits */
 105 #define RTL8365MB_CHIP_ID_8365MB_VC     0x6367
 106 #define RTL8365MB_CHIP_VER_8365MB_VC    0x0040
 107
 108 #define RTL8365MB_CHIP_ID_8367S         0x6367
 109 #define RTL8365MB_CHIP_VER_8367S        0x00A0
 110
 111 #define RTL8365MB_CHIP_ID_8367RB        0x6367
 112 #define RTL8365MB_CHIP_VER_8367RB       0x0020
 113
 114 /* Family-specific data and limits */
 115 #define RTL8365MB_PHYADDRMAX            7
 116 #define RTL8365MB_NUM_PHYREGS           32
 117 #define RTL8365MB_PHYREGMAX             (RTL8365MB_NUM_PHYREGS - 1)
 118 /* RTL8370MB and RTL8310SR, possibly suportable by this driver, have 10 ports */
 119 #define RTL8365MB_MAX_NUM_PORTS         10
 120 #define RTL8365MB_LEARN_LIMIT_MAX       2112
 121
 122 /* valid for all 6-port or less variants */
 123 static const int rtl8365mb_extint_port_map[]  = { -1, -1, -1, -1, -1, -1, 1, 2, -1, -1};
 124
 125 /* Chip identification registers */
 126 #define RTL8365MB_CHIP_ID_REG           0x1300
 127
 128 #define RTL8365MB_CHIP_VER_REG          0x1301
 129
 130 #define RTL8365MB_MAGIC_REG             0x13C2
 131 #define   RTL8365MB_MAGIC_VALUE         0x0249
 132
 133 /* Chip reset register */
 134 #define RTL8365MB_CHIP_RESET_REG        0x1322
 135 #define RTL8365MB_CHIP_RESET_SW_MASK    0x0002
 136 #define RTL8365MB_CHIP_RESET_HW_MASK    0x0001
 137
 138 /* Interrupt polarity register */
 139 #define RTL8365MB_INTR_POLARITY_REG     0x1100
 140 #define   RTL8365MB_INTR_POLARITY_MASK  0x0001
 141 #define   RTL8365MB_INTR_POLARITY_HIGH  0
 142 #define   RTL8365MB_INTR_POLARITY_LOW   1
 143
 144 /* Interrupt control/status register - enable/check specific interrupt types */
 145 #define RTL8365MB_INTR_CTRL_REG                 0x1101
 146 #define RTL8365MB_INTR_STATUS_REG               0x1102
 147 #define   RTL8365MB_INTR_SLIENT_START_2_MASK    0x1000
 148 #define   RTL8365MB_INTR_SLIENT_START_MASK      0x0800
 149 #define   RTL8365MB_INTR_ACL_ACTION_MASK        0x0200
 150 #define   RTL8365MB_INTR_CABLE_DIAG_FIN_MASK    0x0100
 151 #define   RTL8365MB_INTR_INTERRUPT_8051_MASK    0x0080
 152 #define   RTL8365MB_INTR_LOOP_DETECTION_MASK    0x0040
 153 #define   RTL8365MB_INTR_GREEN_TIMER_MASK       0x0020
 154 #define   RTL8365MB_INTR_SPECIAL_CONGEST_MASK   0x0010
 155 #define   RTL8365MB_INTR_SPEED_CHANGE_MASK      0x0008
 156 #define   RTL8365MB_INTR_LEARN_OVER_MASK        0x0004
 157 #define   RTL8365MB_INTR_METER_EXCEEDED_MASK    0x0002
 158 #define   RTL8365MB_INTR_LINK_CHANGE_MASK       0x0001
 159 #define   RTL8365MB_INTR_ALL_MASK                      \
 160                 (RTL8365MB_INTR_SLIENT_START_2_MASK |  \
 161                  RTL8365MB_INTR_SLIENT_START_MASK |    \
 162                  RTL8365MB_INTR_ACL_ACTION_MASK |      \
 163                  RTL8365MB_INTR_CABLE_DIAG_FIN_MASK |  \
 164                  RTL8365MB_INTR_INTERRUPT_8051_MASK |  \
 165                  RTL8365MB_INTR_LOOP_DETECTION_MASK |  \
 166                  RTL8365MB_INTR_GREEN_TIMER_MASK |     \
 167                  RTL8365MB_INTR_SPECIAL_CONGEST_MASK | \
 168                  RTL8365MB_INTR_SPEED_CHANGE_MASK |    \
 169                  RTL8365MB_INTR_LEARN_OVER_MASK |      \
 170                  RTL8365MB_INTR_METER_EXCEEDED_MASK |  \
 171                  RTL8365MB_INTR_LINK_CHANGE_MASK)
 172
 173 /* Per-port interrupt type status registers */
 174 #define RTL8365MB_PORT_LINKDOWN_IND_REG         0x1106
 175 #define   RTL8365MB_PORT_LINKDOWN_IND_MASK      0x07FF
 176
 177 #define RTL8365MB_PORT_LINKUP_IND_REG           0x1107
 178 #define   RTL8365MB_PORT_LINKUP_IND_MASK        0x07FF
 179
 180 /* PHY indirect access registers */
 181 #define RTL8365MB_INDIRECT_ACCESS_CTRL_REG                      0x1F00
 182 #define   RTL8365MB_INDIRECT_ACCESS_CTRL_RW_MASK                0x0002
 183 #define   RTL8365MB_INDIRECT_ACCESS_CTRL_RW_READ                0
 184 #define   RTL8365MB_INDIRECT_ACCESS_CTRL_RW_WRITE               1
 185 #define   RTL8365MB_INDIRECT_ACCESS_CTRL_CMD_MASK               0x0001
 186 #define   RTL8365MB_INDIRECT_ACCESS_CTRL_CMD_VALUE              1
 187 #define RTL8365MB_INDIRECT_ACCESS_STATUS_REG                    0x1F01
 188 #define RTL8365MB_INDIRECT_ACCESS_ADDRESS_REG                   0x1F02
 189 #define   RTL8365MB_INDIRECT_ACCESS_ADDRESS_OCPADR_5_1_MASK     GENMASK(4, 0)
 190 #define   RTL8365MB_INDIRECT_ACCESS_ADDRESS_PHYNUM_MASK         GENMASK(7, 5)
 191 #define   RTL8365MB_INDIRECT_ACCESS_ADDRESS_OCPADR_9_6_MASK     GENMASK(11, 8)
 192 #define   RTL8365MB_PHY_BASE                                    0x2000
 193 #define RTL8365MB_INDIRECT_ACCESS_WRITE_DATA_REG                0x1F03
 194 #define RTL8365MB_INDIRECT_ACCESS_READ_DATA_REG                 0x1F04
 195
 196 /* PHY OCP address prefix register */
 197 #define RTL8365MB_GPHY_OCP_MSB_0_REG                    0x1D15
 198 #define   RTL8365MB_GPHY_OCP_MSB_0_CFG_CPU_OCPADR_MASK  0x0FC0
 199 #define RTL8365MB_PHY_OCP_ADDR_PREFIX_MASK              0xFC00
 200
 201 /* The PHY OCP addresses of PHY registers 0~31 start here */
 202 #define RTL8365MB_PHY_OCP_ADDR_PHYREG_BASE              0xA400
 203
 204 /* EXT interface port mode values - used in DIGITAL_INTERFACE_SELECT */
 205 #define RTL8365MB_EXT_PORT_MODE_DISABLE         0
 206 #define RTL8365MB_EXT_PORT_MODE_RGMII           1
 207 #define RTL8365MB_EXT_PORT_MODE_MII_MAC         2
 208 #define RTL8365MB_EXT_PORT_MODE_MII_PHY         3
 209 #define RTL8365MB_EXT_PORT_MODE_TMII_MAC        4
 210 #define RTL8365MB_EXT_PORT_MODE_TMII_PHY        5
 211 #define RTL8365MB_EXT_PORT_MODE_GMII            6
 212 #define RTL8365MB_EXT_PORT_MODE_RMII_MAC        7
 213 #define RTL8365MB_EXT_PORT_MODE_RMII_PHY        8
 214 #define RTL8365MB_EXT_PORT_MODE_SGMII           9
 215 #define RTL8365MB_EXT_PORT_MODE_HSGMII          10
 216 #define RTL8365MB_EXT_PORT_MODE_1000X_100FX     11
 217 #define RTL8365MB_EXT_PORT_MODE_1000X           12
 218 #define RTL8365MB_EXT_PORT_MODE_100FX           13
 219
 220 /* Realtek docs and driver uses logic number as EXT_PORT0=16, EXT_PORT1=17,
 221  * EXT_PORT2=18, to interact with switch ports. That logic number is internally
 222  * converted to either a physical port number (0..9) or an external interface id (0..2),
 223  * depending on which function was called. The external interface id is calculated as
 224  * (ext_id=logic_port-15), while the logical to physical map depends on the chip id/version.
 225  *
 226  * EXT_PORT0 mentioned in datasheets and rtl8367c driver is used in this driver
 227  * as extid==1, EXT_PORT2, mentioned in Realtek rtl8367c driver for 10-port switches,
 228  * would have an ext_id of 3 (out of range for most extint macros) and ext_id 0 does
 229  * not seem to be used as well for this family.
 230  */
 231
 232 /* EXT interface mode configuration registers 0~1 */
 233 #define RTL8365MB_DIGITAL_INTERFACE_SELECT_REG0         0x1305 /* EXT1 */
 234 #define RTL8365MB_DIGITAL_INTERFACE_SELECT_REG1         0x13C3 /* EXT2 */
 235 #define RTL8365MB_DIGITAL_INTERFACE_SELECT_REG(_extint) \
 236                 ((_extint) == 1 ? RTL8365MB_DIGITAL_INTERFACE_SELECT_REG0 : \
 237                  (_extint) == 2 ? RTL8365MB_DIGITAL_INTERFACE_SELECT_REG1 : \
 238                  0x0)
 239 #define   RTL8365MB_DIGITAL_INTERFACE_SELECT_MODE_MASK(_extint) \
 240                 (0xF << (((_extint) % 2)))
 241 #define   RTL8365MB_DIGITAL_INTERFACE_SELECT_MODE_OFFSET(_extint) \
 242                 (((_extint) % 2) * 4)
 243
 244 /* EXT interface RGMII TX/RX delay configuration registers 0~2 */
 245 #define RTL8365MB_EXT_RGMXF_REG0                0x1306 /* EXT0 */
 246 #define RTL8365MB_EXT_RGMXF_REG1                0x1307 /* EXT1 */
 247 #define RTL8365MB_EXT_RGMXF_REG2                0x13C5 /* EXT2 */
 248 #define RTL8365MB_EXT_RGMXF_REG(_extint) \
 249                 ((_extint) == 0 ? RTL8365MB_EXT_RGMXF_REG0 : \
 250                  (_extint) == 1 ? RTL8365MB_EXT_RGMXF_REG1 : \
 251                  (_extint) == 2 ? RTL8365MB_EXT_RGMXF_REG2 : \
 252                  0x0)
 253 #define   RTL8365MB_EXT_RGMXF_RXDELAY_MASK      0x0007
 254 #define   RTL8365MB_EXT_RGMXF_TXDELAY_MASK      0x0008
 255
 256 /* External interface port speed values - used in DIGITAL_INTERFACE_FORCE */
 257 #define RTL8365MB_PORT_SPEED_10M        0
 258 #define RTL8365MB_PORT_SPEED_100M       1
 259 #define RTL8365MB_PORT_SPEED_1000M      2
 260
 261 /* EXT interface force configuration registers 0~2 */
 262 #define RTL8365MB_DIGITAL_INTERFACE_FORCE_REG0          0x1310 /* EXT0 */
 263 #define RTL8365MB_DIGITAL_INTERFACE_FORCE_REG1          0x1311 /* EXT1 */
 264 #define RTL8365MB_DIGITAL_INTERFACE_FORCE_REG2          0x13C4 /* EXT2 */
 265 #define RTL8365MB_DIGITAL_INTERFACE_FORCE_REG(_extint) \
 266                 ((_extint) == 0 ? RTL8365MB_DIGITAL_INTERFACE_FORCE_REG0 : \
 267                  (_extint) == 1 ? RTL8365MB_DIGITAL_INTERFACE_FORCE_REG1 : \
 268                  (_extint) == 2 ? RTL8365MB_DIGITAL_INTERFACE_FORCE_REG2 : \
 269                  0x0)
 270 #define   RTL8365MB_DIGITAL_INTERFACE_FORCE_EN_MASK             0x1000
 271 #define   RTL8365MB_DIGITAL_INTERFACE_FORCE_NWAY_MASK           0x0080
 272 #define   RTL8365MB_DIGITAL_INTERFACE_FORCE_TXPAUSE_MASK        0x0040
 273 #define   RTL8365MB_DIGITAL_INTERFACE_FORCE_RXPAUSE_MASK        0x0020
 274 #define   RTL8365MB_DIGITAL_INTERFACE_FORCE_LINK_MASK           0x0010
 275 #define   RTL8365MB_DIGITAL_INTERFACE_FORCE_DUPLEX_MASK         0x0004
 276 #define   RTL8365MB_DIGITAL_INTERFACE_FORCE_SPEED_MASK          0x0003
 277
 278 /* CPU port mask register - controls which ports are treated as CPU ports */
 279 #define RTL8365MB_CPU_PORT_MASK_REG     0x1219
 280 #define   RTL8365MB_CPU_PORT_MASK_MASK  0x07FF
 281
 282 /* CPU control register */
 283 #define RTL8365MB_CPU_CTRL_REG                  0x121A
 284 #define   RTL8365MB_CPU_CTRL_TRAP_PORT_EXT_MASK 0x0400
 285 #define   RTL8365MB_CPU_CTRL_TAG_FORMAT_MASK    0x0200
 286 #define   RTL8365MB_CPU_CTRL_RXBYTECOUNT_MASK   0x0080
 287 #define   RTL8365MB_CPU_CTRL_TAG_POSITION_MASK  0x0040
 288 #define   RTL8365MB_CPU_CTRL_TRAP_PORT_MASK     0x0038
 289 #define   RTL8365MB_CPU_CTRL_INSERTMODE_MASK    0x0006
 290 #define   RTL8365MB_CPU_CTRL_EN_MASK            0x0001
 291
 292 /* Maximum packet length register */
 293 #define RTL8365MB_CFG0_MAX_LEN_REG      0x088C
 294 #define   RTL8365MB_CFG0_MAX_LEN_MASK   0x3FFF
 295
 296 /* Port learning limit registers */
 297 #define RTL8365MB_LUT_PORT_LEARN_LIMIT_BASE             0x0A20
 298 #define RTL8365MB_LUT_PORT_LEARN_LIMIT_REG(_physport) \
 299                 (RTL8365MB_LUT_PORT_LEARN_LIMIT_BASE + (_physport))
 300
 301 /* Port isolation (forwarding mask) registers */
 302 #define RTL8365MB_PORT_ISOLATION_REG_BASE               0x08A2
 303 #define RTL8365MB_PORT_ISOLATION_REG(_physport) \
 304                 (RTL8365MB_PORT_ISOLATION_REG_BASE + (_physport))
 305 #define   RTL8365MB_PORT_ISOLATION_MASK                 0x07FF
 306
 307 /* MSTP port state registers - indexed by tree instance */
 308 #define RTL8365MB_MSTI_CTRL_BASE                        0x0A00
 309 #define RTL8365MB_MSTI_CTRL_REG(_msti, _physport) \
 310                 (RTL8365MB_MSTI_CTRL_BASE + ((_msti) << 1) + ((_physport) >> 3))
 311 #define   RTL8365MB_MSTI_CTRL_PORT_STATE_OFFSET(_physport) ((_physport) << 1)
 312 #define   RTL8365MB_MSTI_CTRL_PORT_STATE_MASK(_physport) \
 313                 (0x3 << RTL8365MB_MSTI_CTRL_PORT_STATE_OFFSET((_physport)))
 314
 315 /* MIB counter value registers */
 316 #define RTL8365MB_MIB_COUNTER_BASE      0x1000
 317 #define RTL8365MB_MIB_COUNTER_REG(_x)   (RTL8365MB_MIB_COUNTER_BASE + (_x))
 318
 319 /* MIB counter address register */
 320 #define RTL8365MB_MIB_ADDRESS_REG               0x1004
 321 #define   RTL8365MB_MIB_ADDRESS_PORT_OFFSET     0x007C
 322 #define   RTL8365MB_MIB_ADDRESS(_p, _x) \
 323                 (((RTL8365MB_MIB_ADDRESS_PORT_OFFSET) * (_p) + (_x)) >> 2)
 324
 325 #define RTL8365MB_MIB_CTRL0_REG                 0x1005
 326 #define   RTL8365MB_MIB_CTRL0_RESET_MASK        0x0002
 327 #define   RTL8365MB_MIB_CTRL0_BUSY_MASK         0x0001
 328
 329 /* The DSA callback .get_stats64 runs in atomic context, so we are not allowed
 330  * to block. On the other hand, accessing MIB counters absolutely requires us to
 331  * block. The solution is thus to schedule work which polls the MIB counters
 332  * asynchronously and updates some private data, which the callback can then
 333  * fetch atomically. Three seconds should be a good enough polling interval.
 334  */
 335 #define RTL8365MB_STATS_INTERVAL_JIFFIES        (3 * HZ)
 336
 337 enum rtl8365mb_mib_counter_index {
 338         RTL8365MB_MIB_ifInOctets,
 339         RTL8365MB_MIB_dot3StatsFCSErrors,
 340         RTL8365MB_MIB_dot3StatsSymbolErrors,
 341         RTL8365MB_MIB_dot3InPauseFrames,
 342         RTL8365MB_MIB_dot3ControlInUnknownOpcodes,
 343         RTL8365MB_MIB_etherStatsFragments,
 344         RTL8365MB_MIB_etherStatsJabbers,
 345         RTL8365MB_MIB_ifInUcastPkts,
 346         RTL8365MB_MIB_etherStatsDropEvents,
 347         RTL8365MB_MIB_ifInMulticastPkts,
 348         RTL8365MB_MIB_ifInBroadcastPkts,
 349         RTL8365MB_MIB_inMldChecksumError,
 350         RTL8365MB_MIB_inIgmpChecksumError,
 351         RTL8365MB_MIB_inMldSpecificQuery,
 352         RTL8365MB_MIB_inMldGeneralQuery,
 353         RTL8365MB_MIB_inIgmpSpecificQuery,
 354         RTL8365MB_MIB_inIgmpGeneralQuery,
 355         RTL8365MB_MIB_inMldLeaves,
 356         RTL8365MB_MIB_inIgmpLeaves,
 357         RTL8365MB_MIB_etherStatsOctets,
 358         RTL8365MB_MIB_etherStatsUnderSizePkts,
 359         RTL8365MB_MIB_etherOversizeStats,
 360         RTL8365MB_MIB_etherStatsPkts64Octets,
 361         RTL8365MB_MIB_etherStatsPkts65to127Octets,
 362         RTL8365MB_MIB_etherStatsPkts128to255Octets,
 363         RTL8365MB_MIB_etherStatsPkts256to511Octets,
 364         RTL8365MB_MIB_etherStatsPkts512to1023Octets,
 365         RTL8365MB_MIB_etherStatsPkts1024to1518Octets,
 366         RTL8365MB_MIB_ifOutOctets,
 367         RTL8365MB_MIB_dot3StatsSingleCollisionFrames,
 368         RTL8365MB_MIB_dot3StatsMultipleCollisionFrames,
 369         RTL8365MB_MIB_dot3StatsDeferredTransmissions,
 370         RTL8365MB_MIB_dot3StatsLateCollisions,
 371         RTL8365MB_MIB_etherStatsCollisions,
 372         RTL8365MB_MIB_dot3StatsExcessiveCollisions,
 373         RTL8365MB_MIB_dot3OutPauseFrames,
 374         RTL8365MB_MIB_ifOutDiscards,
 375         RTL8365MB_MIB_dot1dTpPortInDiscards,
 376         RTL8365MB_MIB_ifOutUcastPkts,
 377         RTL8365MB_MIB_ifOutMulticastPkts,
 378         RTL8365MB_MIB_ifOutBroadcastPkts,
 379         RTL8365MB_MIB_outOampduPkts,
 380         RTL8365MB_MIB_inOampduPkts,
 381         RTL8365MB_MIB_inIgmpJoinsSuccess,
 382         RTL8365MB_MIB_inIgmpJoinsFail,
 383         RTL8365MB_MIB_inMldJoinsSuccess,
 384         RTL8365MB_MIB_inMldJoinsFail,
 385         RTL8365MB_MIB_inReportSuppressionDrop,
 386         RTL8365MB_MIB_inLeaveSuppressionDrop,
 387         RTL8365MB_MIB_outIgmpReports,
 388         RTL8365MB_MIB_outIgmpLeaves,
 389         RTL8365MB_MIB_outIgmpGeneralQuery,
 390         RTL8365MB_MIB_outIgmpSpecificQuery,
 391         RTL8365MB_MIB_outMldReports,
 392         RTL8365MB_MIB_outMldLeaves,
 393         RTL8365MB_MIB_outMldGeneralQuery,
 394         RTL8365MB_MIB_outMldSpecificQuery,
 395         RTL8365MB_MIB_inKnownMulticastPkts,
 396         RTL8365MB_MIB_END,
 397 };
 398
 399 struct rtl8365mb_mib_counter {
 400         u32 offset;
 401         u32 length;
 402         const char *name;
 403 };
 404
 405 #define RTL8365MB_MAKE_MIB_COUNTER(_offset, _length, _name) \
 406                 [RTL8365MB_MIB_ ## _name] = { _offset, _length, #_name }
 407
 408 static struct rtl8365mb_mib_counter rtl8365mb_mib_counters[] = {
 409         RTL8365MB_MAKE_MIB_COUNTER(0, 4, ifInOctets),
 410         RTL8365MB_MAKE_MIB_COUNTER(4, 2, dot3StatsFCSErrors),
 411         RTL8365MB_MAKE_MIB_COUNTER(6, 2, dot3StatsSymbolErrors),
 412         RTL8365MB_MAKE_MIB_COUNTER(8, 2, dot3InPauseFrames),
 413         RTL8365MB_MAKE_MIB_COUNTER(10, 2, dot3ControlInUnknownOpcodes),
 414         RTL8365MB_MAKE_MIB_COUNTER(12, 2, etherStatsFragments),
 415         RTL8365MB_MAKE_MIB_COUNTER(14, 2, etherStatsJabbers),
 416         RTL8365MB_MAKE_MIB_COUNTER(16, 2, ifInUcastPkts),
 417         RTL8365MB_MAKE_MIB_COUNTER(18, 2, etherStatsDropEvents),
 418         RTL8365MB_MAKE_MIB_COUNTER(20, 2, ifInMulticastPkts),
 419         RTL8365MB_MAKE_MIB_COUNTER(22, 2, ifInBroadcastPkts),
 420         RTL8365MB_MAKE_MIB_COUNTER(24, 2, inMldChecksumError),
 421         RTL8365MB_MAKE_MIB_COUNTER(26, 2, inIgmpChecksumError),
 422         RTL8365MB_MAKE_MIB_COUNTER(28, 2, inMldSpecificQuery),
 423         RTL8365MB_MAKE_MIB_COUNTER(30, 2, inMldGeneralQuery),
 424         RTL8365MB_MAKE_MIB_COUNTER(32, 2, inIgmpSpecificQuery),
 425         RTL8365MB_MAKE_MIB_COUNTER(34, 2, inIgmpGeneralQuery),
 426         RTL8365MB_MAKE_MIB_COUNTER(36, 2, inMldLeaves),
 427         RTL8365MB_MAKE_MIB_COUNTER(38, 2, inIgmpLeaves),
 428         RTL8365MB_MAKE_MIB_COUNTER(40, 4, etherStatsOctets),
 429         RTL8365MB_MAKE_MIB_COUNTER(44, 2, etherStatsUnderSizePkts),
 430         RTL8365MB_MAKE_MIB_COUNTER(46, 2, etherOversizeStats),
 431         RTL8365MB_MAKE_MIB_COUNTER(48, 2, etherStatsPkts64Octets),
 432         RTL8365MB_MAKE_MIB_COUNTER(50, 2, etherStatsPkts65to127Octets),
 433         RTL8365MB_MAKE_MIB_COUNTER(52, 2, etherStatsPkts128to255Octets),
 434         RTL8365MB_MAKE_MIB_COUNTER(54, 2, etherStatsPkts256to511Octets),
 435         RTL8365MB_MAKE_MIB_COUNTER(56, 2, etherStatsPkts512to1023Octets),
 436         RTL8365MB_MAKE_MIB_COUNTER(58, 2, etherStatsPkts1024to1518Octets),
 437         RTL8365MB_MAKE_MIB_COUNTER(60, 4, ifOutOctets),
 438         RTL8365MB_MAKE_MIB_COUNTER(64, 2, dot3StatsSingleCollisionFrames),
 439         RTL8365MB_MAKE_MIB_COUNTER(66, 2, dot3StatsMultipleCollisionFrames),
 440         RTL8365MB_MAKE_MIB_COUNTER(68, 2, dot3StatsDeferredTransmissions),
 441         RTL8365MB_MAKE_MIB_COUNTER(70, 2, dot3StatsLateCollisions),
 442         RTL8365MB_MAKE_MIB_COUNTER(72, 2, etherStatsCollisions),
 443         RTL8365MB_MAKE_MIB_COUNTER(74, 2, dot3StatsExcessiveCollisions),
 444         RTL8365MB_MAKE_MIB_COUNTER(76, 2, dot3OutPauseFrames),
 445         RTL8365MB_MAKE_MIB_COUNTER(78, 2, ifOutDiscards),
 446         RTL8365MB_MAKE_MIB_COUNTER(80, 2, dot1dTpPortInDiscards),
 447         RTL8365MB_MAKE_MIB_COUNTER(82, 2, ifOutUcastPkts),
 448         RTL8365MB_MAKE_MIB_COUNTER(84, 2, ifOutMulticastPkts),
 449         RTL8365MB_MAKE_MIB_COUNTER(86, 2, ifOutBroadcastPkts),
 450         RTL8365MB_MAKE_MIB_COUNTER(88, 2, outOampduPkts),
 451         RTL8365MB_MAKE_MIB_COUNTER(90, 2, inOampduPkts),
 452         RTL8365MB_MAKE_MIB_COUNTER(92, 4, inIgmpJoinsSuccess),
 453         RTL8365MB_MAKE_MIB_COUNTER(96, 2, inIgmpJoinsFail),
 454         RTL8365MB_MAKE_MIB_COUNTER(98, 2, inMldJoinsSuccess),
 455         RTL8365MB_MAKE_MIB_COUNTER(100, 2, inMldJoinsFail),
 456         RTL8365MB_MAKE_MIB_COUNTER(102, 2, inReportSuppressionDrop),
 457         RTL8365MB_MAKE_MIB_COUNTER(104, 2, inLeaveSuppressionDrop),
 458         RTL8365MB_MAKE_MIB_COUNTER(106, 2, outIgmpReports),
 459         RTL8365MB_MAKE_MIB_COUNTER(108, 2, outIgmpLeaves),
 460         RTL8365MB_MAKE_MIB_COUNTER(110, 2, outIgmpGeneralQuery),
 461         RTL8365MB_MAKE_MIB_COUNTER(112, 2, outIgmpSpecificQuery),
 462         RTL8365MB_MAKE_MIB_COUNTER(114, 2, outMldReports),
 463         RTL8365MB_MAKE_MIB_COUNTER(116, 2, outMldLeaves),
 464         RTL8365MB_MAKE_MIB_COUNTER(118, 2, outMldGeneralQuery),
 465         RTL8365MB_MAKE_MIB_COUNTER(120, 2, outMldSpecificQuery),
 466         RTL8365MB_MAKE_MIB_COUNTER(122, 2, inKnownMulticastPkts),
 467 };
 468
 469 static_assert(ARRAY_SIZE(rtl8365mb_mib_counters) == RTL8365MB_MIB_END);
 470
 471 struct rtl8365mb_jam_tbl_entry {
 472         u16 reg;
 473         u16 val;
 474 };
 475
 476 /* Lifted from the vendor driver sources */
 477 static const struct rtl8365mb_jam_tbl_entry rtl8365mb_init_jam_8365mb_vc[] = {
 478         { 0x13EB, 0x15BB }, { 0x1303, 0x06D6 }, { 0x1304, 0x0700 },
 479         { 0x13E2, 0x003F }, { 0x13F9, 0x0090 }, { 0x121E, 0x03CA },
 480         { 0x1233, 0x0352 }, { 0x1237, 0x00A0 }, { 0x123A, 0x0030 },
 481         { 0x1239, 0x0084 }, { 0x0301, 0x1000 }, { 0x1349, 0x001F },
 482         { 0x18E0, 0x4004 }, { 0x122B, 0x241C }, { 0x1305, 0xC000 },
 483         { 0x13F0, 0x0000 },
 484 };
 485
 486 static const struct rtl8365mb_jam_tbl_entry rtl8365mb_init_jam_common[] = {
 487         { 0x1200, 0x7FCB }, { 0x0884, 0x0003 }, { 0x06EB, 0x0001 },
 488         { 0x03Fa, 0x0007 }, { 0x08C8, 0x00C0 }, { 0x0A30, 0x020E },
 489         { 0x0800, 0x0000 }, { 0x0802, 0x0000 }, { 0x09DA, 0x0013 },
 490         { 0x1D32, 0x0002 },
 491 };
 492
 493 enum rtl8365mb_stp_state {
 494         RTL8365MB_STP_STATE_DISABLED = 0,
 495         RTL8365MB_STP_STATE_BLOCKING = 1,
 496         RTL8365MB_STP_STATE_LEARNING = 2,
 497         RTL8365MB_STP_STATE_FORWARDING = 3,
 498 };
 499
 500 enum rtl8365mb_cpu_insert {
 501         RTL8365MB_CPU_INSERT_TO_ALL = 0,
 502         RTL8365MB_CPU_INSERT_TO_TRAPPING = 1,
 503         RTL8365MB_CPU_INSERT_TO_NONE = 2,
 504 };
 505
 506 enum rtl8365mb_cpu_position {
 507         RTL8365MB_CPU_POS_AFTER_SA = 0,
 508         RTL8365MB_CPU_POS_BEFORE_CRC = 1,
 509 };
 510
 511 enum rtl8365mb_cpu_format {
 512         RTL8365MB_CPU_FORMAT_8BYTES = 0,
 513         RTL8365MB_CPU_FORMAT_4BYTES = 1,
 514 };
 515
 516 enum rtl8365mb_cpu_rxlen {
 517         RTL8365MB_CPU_RXLEN_72BYTES = 0,
 518         RTL8365MB_CPU_RXLEN_64BYTES = 1,
 519 };
 520
 521 /**
 522  * struct rtl8365mb_cpu - CPU port configuration
 523  * @enable: enable/disable hardware insertion of CPU tag in switch->CPU frames
 524  * @mask: port mask of ports that parse should parse CPU tags
 525  * @trap_port: forward trapped frames to this port
 526  * @insert: CPU tag insertion mode in switch->CPU frames
 527  * @position: position of CPU tag in frame
 528  * @rx_length: minimum CPU RX length
 529  * @format: CPU tag format
 530  *
 531  * Represents the CPU tagging and CPU port configuration of the switch. These
 532  * settings are configurable at runtime.
 533  */
 534 struct rtl8365mb_cpu {
 535         bool enable;
 536         u32 mask;
 537         u32 trap_port;
 538         enum rtl8365mb_cpu_insert insert;
 539         enum rtl8365mb_cpu_position position;
 540         enum rtl8365mb_cpu_rxlen rx_length;
 541         enum rtl8365mb_cpu_format format;
 542 };
 543
 544 /**
 545  * struct rtl8365mb_port - private per-port data
 546  * @priv: pointer to parent realtek_priv data
 547  * @index: DSA port index, same as dsa_port::index
 548  * @stats: link statistics populated by rtl8365mb_stats_poll, ready for atomic
 549  *         access via rtl8365mb_get_stats64
 550  * @stats_lock: protect the stats structure during read/update
 551  * @mib_work: delayed work for polling MIB counters
 552  */
 553 struct rtl8365mb_port {
 554         struct realtek_priv *priv;
 555         unsigned int index;
 556         struct rtnl_link_stats64 stats;
 557         spinlock_t stats_lock;
 558         struct delayed_work mib_work;
 559 };
 560
 561 /**
 562  * struct rtl8365mb - private chip-specific driver data
 563  * @priv: pointer to parent realtek_priv data
 564  * @irq: registered IRQ or zero
 565  * @chip_id: chip identifier
 566  * @chip_ver: chip silicon revision
 567  * @port_mask: mask of all ports
 568  * @learn_limit_max: maximum number of L2 addresses the chip can learn
 569  * @cpu: CPU tagging and CPU port configuration for this chip
 570  * @mib_lock: prevent concurrent reads of MIB counters
 571  * @ports: per-port data
 572  * @jam_table: chip-specific initialization jam table
 573  * @jam_size: size of the chip's jam table
 574  *
 575  * Private data for this driver.
 576  */
 577 struct rtl8365mb {
 578         struct realtek_priv *priv;
 579         int irq;
 580         u32 chip_id;
 581         u32 chip_ver;
 582         u32 port_mask;
 583         u32 learn_limit_max;
 584         struct rtl8365mb_cpu cpu;
 585         struct mutex mib_lock;
 586         struct rtl8365mb_port ports[RTL8365MB_MAX_NUM_PORTS];
 587         const struct rtl8365mb_jam_tbl_entry *jam_table;
 588         size_t jam_size;
 589 };
 590
 591 static int rtl8365mb_phy_poll_busy(struct realtek_priv *priv)
 592 {
 593         u32 val;
 594
 595         return regmap_read_poll_timeout(priv->map_nolock,
 596                                         RTL8365MB_INDIRECT_ACCESS_STATUS_REG,
 597                                         val, !val, 10, 100);
 598 }
 599
 600 static int rtl8365mb_phy_ocp_prepare(struct realtek_priv *priv, int phy,
 601                                      u32 ocp_addr)
 602 {
 603         u32 val;
 604         int ret;
 605
 606         /* Set OCP prefix */
 607         val = FIELD_GET(RTL8365MB_PHY_OCP_ADDR_PREFIX_MASK, ocp_addr);
 608         ret = regmap_update_bits(
 609                 priv->map_nolock, RTL8365MB_GPHY_OCP_MSB_0_REG,
 610                 RTL8365MB_GPHY_OCP_MSB_0_CFG_CPU_OCPADR_MASK,
 611                 FIELD_PREP(RTL8365MB_GPHY_OCP_MSB_0_CFG_CPU_OCPADR_MASK, val));
 612         if (ret)
 613                 return ret;
 614
 615         /* Set PHY register address */
 616         val = RTL8365MB_PHY_BASE;
 617         val |= FIELD_PREP(RTL8365MB_INDIRECT_ACCESS_ADDRESS_PHYNUM_MASK, phy);
 618         val |= FIELD_PREP(RTL8365MB_INDIRECT_ACCESS_ADDRESS_OCPADR_5_1_MASK,
 619                           ocp_addr >> 1);
 620         val |= FIELD_PREP(RTL8365MB_INDIRECT_ACCESS_ADDRESS_OCPADR_9_6_MASK,
 621                           ocp_addr >> 6);
 622         ret = regmap_write(priv->map_nolock,
 623                            RTL8365MB_INDIRECT_ACCESS_ADDRESS_REG, val);
 624         if (ret)
 625                 return ret;
 626
 627         return 0;
 628 }
 629
 630 static int rtl8365mb_phy_ocp_read(struct realtek_priv *priv, int phy,
 631                                   u32 ocp_addr, u16 *data)
 632 {
 633         u32 val;
 634         int ret;
 635
 636         mutex_lock(&priv->map_lock);
 637
 638         ret = rtl8365mb_phy_poll_busy(priv);
 639         if (ret)
 640                 goto out;
 641
 642         ret = rtl8365mb_phy_ocp_prepare(priv, phy, ocp_addr);
 643         if (ret)
 644                 goto out;
 645
 646         /* Execute read operation */
 647         val = FIELD_PREP(RTL8365MB_INDIRECT_ACCESS_CTRL_CMD_MASK,
 648                          RTL8365MB_INDIRECT_ACCESS_CTRL_CMD_VALUE) |
 649               FIELD_PREP(RTL8365MB_INDIRECT_ACCESS_CTRL_RW_MASK,
 650                          RTL8365MB_INDIRECT_ACCESS_CTRL_RW_READ);
 651         ret = regmap_write(priv->map_nolock, RTL8365MB_INDIRECT_ACCESS_CTRL_REG,
 652                            val);
 653         if (ret)
 654                 goto out;
 655
 656         ret = rtl8365mb_phy_poll_busy(priv);
 657         if (ret)
 658                 goto out;
 659
 660         /* Get PHY register data */
 661         ret = regmap_read(priv->map_nolock,
 662                           RTL8365MB_INDIRECT_ACCESS_READ_DATA_REG, &val);
 663         if (ret)
 664                 goto out;
 665
 666         *data = val & 0xFFFF;
 667
 668 out:
 669         mutex_unlock(&priv->map_lock);
 670
 671         return ret;
 672 }
 673
 674 static int rtl8365mb_phy_ocp_write(struct realtek_priv *priv, int phy,
 675                                    u32 ocp_addr, u16 data)
 676 {
 677         u32 val;
 678         int ret;
 679
 680         mutex_lock(&priv->map_lock);
 681
 682         ret = rtl8365mb_phy_poll_busy(priv);
 683         if (ret)
 684                 goto out;
 685
 686         ret = rtl8365mb_phy_ocp_prepare(priv, phy, ocp_addr);
 687         if (ret)
 688                 goto out;
 689
 690         /* Set PHY register data */
 691         ret = regmap_write(priv->map_nolock,
 692                            RTL8365MB_INDIRECT_ACCESS_WRITE_DATA_REG, data);
 693         if (ret)
 694                 goto out;
 695
 696         /* Execute write operation */
 697         val = FIELD_PREP(RTL8365MB_INDIRECT_ACCESS_CTRL_CMD_MASK,
 698                          RTL8365MB_INDIRECT_ACCESS_CTRL_CMD_VALUE) |
 699               FIELD_PREP(RTL8365MB_INDIRECT_ACCESS_CTRL_RW_MASK,
 700                          RTL8365MB_INDIRECT_ACCESS_CTRL_RW_WRITE);
 701         ret = regmap_write(priv->map_nolock, RTL8365MB_INDIRECT_ACCESS_CTRL_REG,
 702                            val);
 703         if (ret)
 704                 goto out;
 705
 706         ret = rtl8365mb_phy_poll_busy(priv);
 707         if (ret)
 708                 goto out;
 709
 710 out:
 711         mutex_unlock(&priv->map_lock);
 712
 713         return 0;
 714 }
 715
 716 static int rtl8365mb_phy_read(struct realtek_priv *priv, int phy, int regnum)
 717 {
 718         u32 ocp_addr;
 719         u16 val;
 720         int ret;
 721
 722         if (phy > RTL8365MB_PHYADDRMAX)
 723                 return -EINVAL;
 724
 725         if (regnum > RTL8365MB_PHYREGMAX)
 726                 return -EINVAL;
 727
 728         ocp_addr = RTL8365MB_PHY_OCP_ADDR_PHYREG_BASE + regnum * 2;
 729
 730         ret = rtl8365mb_phy_ocp_read(priv, phy, ocp_addr, &val);
 731         if (ret) {
 732                 dev_err(priv->dev,
 733                         "failed to read PHY%d reg %02x @ %04x, ret %d\n", phy,
 734                         regnum, ocp_addr, ret);
 735                 return ret;
 736         }
 737
 738         dev_dbg(priv->dev, "read PHY%d register 0x%02x @ %04x, val <- %04x\n",
 739                 phy, regnum, ocp_addr, val);
 740
 741         return val;
 742 }
 743
 744 static int rtl8365mb_phy_write(struct realtek_priv *priv, int phy, int regnum,
 745                                u16 val)
 746 {
 747         u32 ocp_addr;
 748         int ret;
 749
 750         if (phy > RTL8365MB_PHYADDRMAX)
 751                 return -EINVAL;
 752
 753         if (regnum > RTL8365MB_PHYREGMAX)
 754                 return -EINVAL;
 755
 756         ocp_addr = RTL8365MB_PHY_OCP_ADDR_PHYREG_BASE + regnum * 2;
 757
 758         ret = rtl8365mb_phy_ocp_write(priv, phy, ocp_addr, val);
 759         if (ret) {
 760                 dev_err(priv->dev,
 761                         "failed to write PHY%d reg %02x @ %04x, ret %d\n", phy,
 762                         regnum, ocp_addr, ret);
 763                 return ret;
 764         }
 765
 766         dev_dbg(priv->dev, "write PHY%d register 0x%02x @ %04x, val -> %04x\n",
 767                 phy, regnum, ocp_addr, val);
 768
 769         return 0;
 770 }
 771
 772 static int rtl8365mb_dsa_phy_read(struct dsa_switch *ds, int phy, int regnum)
 773 {
 774         return rtl8365mb_phy_read(ds->priv, phy, regnum);
 775 }
 776
 777 static int rtl8365mb_dsa_phy_write(struct dsa_switch *ds, int phy, int regnum,
 778                                    u16 val)
 779 {
 780         return rtl8365mb_phy_write(ds->priv, phy, regnum, val);
 781 }
 782
 783 static enum dsa_tag_protocol
 784 rtl8365mb_get_tag_protocol(struct dsa_switch *ds, int port,
 785                            enum dsa_tag_protocol mp)
 786 {
 787         struct realtek_priv *priv = ds->priv;
 788         struct rtl8365mb_cpu *cpu;
 789         struct rtl8365mb *mb;
 790
 791         mb = priv->chip_data;
 792         cpu = &mb->cpu;
 793
 794         if (cpu->position == RTL8365MB_CPU_POS_BEFORE_CRC)
 795                 return DSA_TAG_PROTO_RTL8_4T;
 796
 797         return DSA_TAG_PROTO_RTL8_4;
 798 }
 799
 800 static int rtl8365mb_ext_config_rgmii(struct realtek_priv *priv, int port,
 801                                       phy_interface_t interface)
 802 {
 803         struct device_node *dn;
 804         struct dsa_port *dp;
 805         int tx_delay = 0;
 806         int rx_delay = 0;
 807         int ext_int;
 808         u32 val;
 809         int ret;
 810
 811         ext_int = rtl8365mb_extint_port_map[port];
 812
 813         if (ext_int <= 0) {
 814                 dev_err(priv->dev, "Port %d is not an external interface port\n", port);
 815                 return -EINVAL;
 816         }
 817
 818         dp = dsa_to_port(priv->ds, port);
 819         dn = dp->dn;
 820
 821         /* Set the RGMII TX/RX delay
 822          *
 823          * The Realtek vendor driver indicates the following possible
 824          * configuration settings:
 825          *
 826          *   TX delay:
 827          *     0 = no delay, 1 = 2 ns delay
 828          *   RX delay:
 829          *     0 = no delay, 7 = maximum delay
 830          *     Each step is approximately 0.3 ns, so the maximum delay is about
 831          *     2.1 ns.
 832          *
 833          * The vendor driver also states that this must be configured *before*
 834          * forcing the external interface into a particular mode, which is done
 835          * in the rtl8365mb_phylink_mac_link_{up,down} functions.
 836          *
 837          * Only configure an RGMII TX (resp. RX) delay if the
 838          * tx-internal-delay-ps (resp. rx-internal-delay-ps) OF property is
 839          * specified. We ignore the detail of the RGMII interface mode
 840          * (RGMII_{RXID, TXID, etc.}), as this is considered to be a PHY-only
 841          * property.
 842          */
 843         if (!of_property_read_u32(dn, "tx-internal-delay-ps", &val)) {
 844                 val = val / 1000; /* convert to ns */
 845
 846                 if (val == 0 || val == 2)
 847                         tx_delay = val / 2;
 848                 else
 849                         dev_warn(priv->dev,
 850                                  "EXT interface TX delay must be 0 or 2 ns\n");
 851         }
 852
 853         if (!of_property_read_u32(dn, "rx-internal-delay-ps", &val)) {
 854                 val = DIV_ROUND_CLOSEST(val, 300); /* convert to 0.3 ns step */
 855
 856                 if (val <= 7)
 857                         rx_delay = val;
 858                 else
 859                         dev_warn(priv->dev,
 860                                  "EXT interface RX delay must be 0 to 2.1 ns\n");
 861         }
 862
 863         ret = regmap_update_bits(
 864                 priv->map, RTL8365MB_EXT_RGMXF_REG(ext_int),
 865                 RTL8365MB_EXT_RGMXF_TXDELAY_MASK |
 866                         RTL8365MB_EXT_RGMXF_RXDELAY_MASK,
 867                 FIELD_PREP(RTL8365MB_EXT_RGMXF_TXDELAY_MASK, tx_delay) |
 868                         FIELD_PREP(RTL8365MB_EXT_RGMXF_RXDELAY_MASK, rx_delay));
 869         if (ret)
 870                 return ret;
 871
 872         ret = regmap_update_bits(
 873                 priv->map, RTL8365MB_DIGITAL_INTERFACE_SELECT_REG(ext_int),
 874                 RTL8365MB_DIGITAL_INTERFACE_SELECT_MODE_MASK(ext_int),
 875                 RTL8365MB_EXT_PORT_MODE_RGMII
 876                         << RTL8365MB_DIGITAL_INTERFACE_SELECT_MODE_OFFSET(
 877                                    ext_int));
 878         if (ret)
 879                 return ret;
 880
 881         return 0;
 882 }
 883
 884 static int rtl8365mb_ext_config_forcemode(struct realtek_priv *priv, int port,
 885                                           bool link, int speed, int duplex,
 886                                           bool tx_pause, bool rx_pause)
 887 {
 888         u32 r_tx_pause;
 889         u32 r_rx_pause;
 890         u32 r_duplex;
 891         u32 r_speed;
 892         u32 r_link;
 893         int ext_int;
 894         int val;
 895         int ret;
 896
 897         ext_int = rtl8365mb_extint_port_map[port];
 898
 899         if (ext_int <= 0) {
 900                 dev_err(priv->dev, "Port %d is not an external interface port\n", port);
 901                 return -EINVAL;
 902         }
 903
 904         if (link) {
 905                 /* Force the link up with the desired configuration */
 906                 r_link = 1;
 907                 r_rx_pause = rx_pause ? 1 : 0;
 908                 r_tx_pause = tx_pause ? 1 : 0;
 909
 910                 if (speed == SPEED_1000) {
 911                         r_speed = RTL8365MB_PORT_SPEED_1000M;
 912                 } else if (speed == SPEED_100) {
 913                         r_speed = RTL8365MB_PORT_SPEED_100M;
 914                 } else if (speed == SPEED_10) {
 915                         r_speed = RTL8365MB_PORT_SPEED_10M;
 916                 } else {
 917                         dev_err(priv->dev, "unsupported port speed %s\n",
 918                                 phy_speed_to_str(speed));
 919                         return -EINVAL;
 920                 }
 921
 922                 if (duplex == DUPLEX_FULL) {
 923                         r_duplex = 1;
 924                 } else if (duplex == DUPLEX_HALF) {
 925                         r_duplex = 0;
 926                 } else {
 927                         dev_err(priv->dev, "unsupported duplex %s\n",
 928                                 phy_duplex_to_str(duplex));
 929                         return -EINVAL;
 930                 }
 931         } else {
 932                 /* Force the link down and reset any programmed configuration */
 933                 r_link = 0;
 934                 r_tx_pause = 0;
 935                 r_rx_pause = 0;
 936                 r_speed = 0;
 937                 r_duplex = 0;
 938         }
 939
 940         val = FIELD_PREP(RTL8365MB_DIGITAL_INTERFACE_FORCE_EN_MASK, 1) |
 941               FIELD_PREP(RTL8365MB_DIGITAL_INTERFACE_FORCE_TXPAUSE_MASK,
 942                          r_tx_pause) |
 943               FIELD_PREP(RTL8365MB_DIGITAL_INTERFACE_FORCE_RXPAUSE_MASK,
 944                          r_rx_pause) |
 945               FIELD_PREP(RTL8365MB_DIGITAL_INTERFACE_FORCE_LINK_MASK, r_link) |
 946               FIELD_PREP(RTL8365MB_DIGITAL_INTERFACE_FORCE_DUPLEX_MASK,
 947                          r_duplex) |
 948               FIELD_PREP(RTL8365MB_DIGITAL_INTERFACE_FORCE_SPEED_MASK, r_speed);
 949         ret = regmap_write(priv->map,
 950                            RTL8365MB_DIGITAL_INTERFACE_FORCE_REG(ext_int),
 951                            val);
 952         if (ret)
 953                 return ret;
 954
 955         return 0;
 956 }
 957
 958 static bool rtl8365mb_phy_mode_supported(struct dsa_switch *ds, int port,
 959                                          phy_interface_t interface)
 960 {
 961         int ext_int;
 962
 963         ext_int = rtl8365mb_extint_port_map[port];
 964
 965         if (ext_int < 0 &&
 966             (interface == PHY_INTERFACE_MODE_NA ||
 967              interface == PHY_INTERFACE_MODE_INTERNAL ||
 968              interface == PHY_INTERFACE_MODE_GMII))
 969                 /* Internal PHY */
 970                 return true;
 971         else if ((ext_int >= 1) &&
 972                  phy_interface_mode_is_rgmii(interface))
 973                 /* Extension MAC */
 974                 return true;
 975
 976         return false;
 977 }
 978
 979 static void rtl8365mb_phylink_get_caps(struct dsa_switch *ds, int port,
 980                                        struct phylink_config *config)
 981 {
 982         if (dsa_is_user_port(ds, port))
 983                 __set_bit(PHY_INTERFACE_MODE_INTERNAL,
 984                           config->supported_interfaces);
 985         else if (dsa_is_cpu_port(ds, port))
 986                 phy_interface_set_rgmii(config->supported_interfaces);
 987
 988         config->mac_capabilities = MAC_SYM_PAUSE | MAC_ASYM_PAUSE |
 989                                    MAC_10 | MAC_100 | MAC_1000FD;
 990 }
 991
 992 static void rtl8365mb_phylink_mac_config(struct dsa_switch *ds, int port,
 993                                          unsigned int mode,
 994                                          const struct phylink_link_state *state)
 995 {
 996         struct realtek_priv *priv = ds->priv;
 997         int ret;
 998
 999         if (!rtl8365mb_phy_mode_supported(ds, port, state->interface)) {
1000                 dev_err(priv->dev, "phy mode %s is unsupported on port %d\n",
1001                         phy_modes(state->interface), port);
1002                 return;
1003         }
1004
1005         if (mode != MLO_AN_PHY && mode != MLO_AN_FIXED) {
1006                 dev_err(priv->dev,
1007                         "port %d supports only conventional PHY or fixed-link\n",
1008                         port);
1009                 return;
1010         }
1011
1012         if (phy_interface_mode_is_rgmii(state->interface)) {
1013                 ret = rtl8365mb_ext_config_rgmii(priv, port, state->interface);
1014                 if (ret)
1015                         dev_err(priv->dev,
1016                                 "failed to configure RGMII mode on port %d: %d\n",
1017                                 port, ret);
1018                 return;
1019         }
1020
1021         /* TODO: Implement MII and RMII modes, which the RTL8365MB-VC also
1022          * supports
1023          */
1024 }
1025
1026 static void rtl8365mb_phylink_mac_link_down(struct dsa_switch *ds, int port,
1027                                             unsigned int mode,
1028                                             phy_interface_t interface)
1029 {
1030         struct realtek_priv *priv = ds->priv;
1031         struct rtl8365mb_port *p;
1032         struct rtl8365mb *mb;
1033         int ret;
1034
1035         mb = priv->chip_data;
1036         p = &mb->ports[port];
1037         cancel_delayed_work_sync(&p->mib_work);
1038
1039         if (phy_interface_mode_is_rgmii(interface)) {
1040                 ret = rtl8365mb_ext_config_forcemode(priv, port, false, 0, 0,
1041                                                      false, false);
1042                 if (ret)
1043                         dev_err(priv->dev,
1044                                 "failed to reset forced mode on port %d: %d\n",
1045                                 port, ret);
1046
1047                 return;
1048         }
1049 }
1050
1051 static void rtl8365mb_phylink_mac_link_up(struct dsa_switch *ds, int port,
1052                                           unsigned int mode,
1053                                           phy_interface_t interface,
1054                                           struct phy_device *phydev, int speed,
1055                                           int duplex, bool tx_pause,
1056                                           bool rx_pause)
1057 {
1058         struct realtek_priv *priv = ds->priv;
1059         struct rtl8365mb_port *p;
1060         struct rtl8365mb *mb;
1061         int ret;
1062
1063         mb = priv->chip_data;
1064         p = &mb->ports[port];
1065         schedule_delayed_work(&p->mib_work, 0);
1066
1067         if (phy_interface_mode_is_rgmii(interface)) {
1068                 ret = rtl8365mb_ext_config_forcemode(priv, port, true, speed,
1069                                                      duplex, tx_pause,
1070                                                      rx_pause);
1071                 if (ret)
1072                         dev_err(priv->dev,
1073                                 "failed to force mode on port %d: %d\n", port,
1074                                 ret);
1075
1076                 return;
1077         }
1078 }
1079
1080 static void rtl8365mb_port_stp_state_set(struct dsa_switch *ds, int port,
1081                                          u8 state)
1082 {
1083         struct realtek_priv *priv = ds->priv;
1084         enum rtl8365mb_stp_state val;
1085         int msti = 0;
1086
1087         switch (state) {
1088         case BR_STATE_DISABLED:
1089                 val = RTL8365MB_STP_STATE_DISABLED;
1090                 break;
1091         case BR_STATE_BLOCKING:
1092         case BR_STATE_LISTENING:
1093                 val = RTL8365MB_STP_STATE_BLOCKING;
1094                 break;
1095         case BR_STATE_LEARNING:
1096                 val = RTL8365MB_STP_STATE_LEARNING;
1097                 break;
1098         case BR_STATE_FORWARDING:
1099                 val = RTL8365MB_STP_STATE_FORWARDING;
1100                 break;
1101         default:
1102                 dev_err(priv->dev, "invalid STP state: %u\n", state);
1103                 return;
1104         }
1105
1106         regmap_update_bits(priv->map, RTL8365MB_MSTI_CTRL_REG(msti, port),
1107                            RTL8365MB_MSTI_CTRL_PORT_STATE_MASK(port),
1108                            val << RTL8365MB_MSTI_CTRL_PORT_STATE_OFFSET(port));
1109 }
1110
1111 static int rtl8365mb_port_set_learning(struct realtek_priv *priv, int port,
1112                                        bool enable)
1113 {
1114         struct rtl8365mb *mb = priv->chip_data;
1115
1116         /* Enable/disable learning by limiting the number of L2 addresses the
1117          * port can learn. Realtek documentation states that a limit of zero
1118          * disables learning. When enabling learning, set it to the chip's
1119          * maximum.
1120          */
1121         return regmap_write(priv->map, RTL8365MB_LUT_PORT_LEARN_LIMIT_REG(port),
1122                             enable ? mb->learn_limit_max : 0);
1123 }
1124
1125 static int rtl8365mb_port_set_isolation(struct realtek_priv *priv, int port,
1126                                         u32 mask)
1127 {
1128         return regmap_write(priv->map, RTL8365MB_PORT_ISOLATION_REG(port), mask);
1129 }
1130
1131 static int rtl8365mb_mib_counter_read(struct realtek_priv *priv, int port,
1132                                       u32 offset, u32 length, u64 *mibvalue)
1133 {
1134         u64 tmpvalue = 0;
1135         u32 val;
1136         int ret;
1137         int i;
1138
1139         /* The MIB address is an SRAM address. We request a particular address
1140          * and then poll the control register before reading the value from some
1141          * counter registers.
1142          */
1143         ret = regmap_write(priv->map, RTL8365MB_MIB_ADDRESS_REG,
1144                            RTL8365MB_MIB_ADDRESS(port, offset));
1145         if (ret)
1146                 return ret;
1147
1148         /* Poll for completion */
1149         ret = regmap_read_poll_timeout(priv->map, RTL8365MB_MIB_CTRL0_REG, val,
1150                                        !(val & RTL8365MB_MIB_CTRL0_BUSY_MASK),
1151                                        10, 100);
1152         if (ret)
1153                 return ret;
1154
1155         /* Presumably this indicates a MIB counter read failure */
1156         if (val & RTL8365MB_MIB_CTRL0_RESET_MASK)
1157                 return -EIO;
1158
1159         /* There are four MIB counter registers each holding a 16 bit word of a
1160          * MIB counter. Depending on the offset, we should read from the upper
1161          * two or lower two registers. In case the MIB counter is 4 words, we
1162          * read from all four registers.
1163          */
1164         if (length == 4)
1165                 offset = 3;
1166         else
1167                 offset = (offset + 1) % 4;
1168
1169         /* Read the MIB counter 16 bits at a time */
1170         for (i = 0; i < length; i++) {
1171                 ret = regmap_read(priv->map,
1172                                   RTL8365MB_MIB_COUNTER_REG(offset - i), &val);
1173                 if (ret)
1174                         return ret;
1175
1176                 tmpvalue = ((tmpvalue) << 16) | (val & 0xFFFF);
1177         }
1178
1179         /* Only commit the result if no error occurred */
1180         *mibvalue = tmpvalue;
1181
1182         return 0;
1183 }
1184
1185 static void rtl8365mb_get_ethtool_stats(struct dsa_switch *ds, int port, u64 *data)
1186 {
1187         struct realtek_priv *priv = ds->priv;
1188         struct rtl8365mb *mb;
1189         int ret;
1190         int i;
1191
1192         mb = priv->chip_data;
1193
1194         mutex_lock(&mb->mib_lock);
1195         for (i = 0; i < RTL8365MB_MIB_END; i++) {
1196                 struct rtl8365mb_mib_counter *mib = &rtl8365mb_mib_counters[i];
1197
1198                 ret = rtl8365mb_mib_counter_read(priv, port, mib->offset,
1199                                                  mib->length, &data[i]);
1200                 if (ret) {
1201                         dev_err(priv->dev,
1202                                 "failed to read port %d counters: %d\n", port,
1203                                 ret);
1204                         break;
1205                 }
1206         }
1207         mutex_unlock(&mb->mib_lock);
1208 }
1209
1210 static void rtl8365mb_get_strings(struct dsa_switch *ds, int port, u32 stringset, u8 *data)
1211 {
1212         int i;
1213
1214         if (stringset != ETH_SS_STATS)
1215                 return;
1216
1217         for (i = 0; i < RTL8365MB_MIB_END; i++) {
1218                 struct rtl8365mb_mib_counter *mib = &rtl8365mb_mib_counters[i];
1219
1220                 strncpy(data + i * ETH_GSTRING_LEN, mib->name, ETH_GSTRING_LEN);
1221         }
1222 }
1223
1224 static int rtl8365mb_get_sset_count(struct dsa_switch *ds, int port, int sset)
1225 {
1226         if (sset != ETH_SS_STATS)
1227                 return -EOPNOTSUPP;
1228
1229         return RTL8365MB_MIB_END;
1230 }
1231
1232 static void rtl8365mb_get_phy_stats(struct dsa_switch *ds, int port,
1233                                     struct ethtool_eth_phy_stats *phy_stats)
1234 {
1235         struct realtek_priv *priv = ds->priv;
1236         struct rtl8365mb_mib_counter *mib;
1237         struct rtl8365mb *mb;
1238
1239         mb = priv->chip_data;
1240         mib = &rtl8365mb_mib_counters[RTL8365MB_MIB_dot3StatsSymbolErrors];
1241
1242         mutex_lock(&mb->mib_lock);
1243         rtl8365mb_mib_counter_read(priv, port, mib->offset, mib->length,
1244                                    &phy_stats->SymbolErrorDuringCarrier);
1245         mutex_unlock(&mb->mib_lock);
1246 }
1247
1248 static void rtl8365mb_get_mac_stats(struct dsa_switch *ds, int port,
1249                                     struct ethtool_eth_mac_stats *mac_stats)
1250 {
1251         u64 cnt[RTL8365MB_MIB_END] = {
1252                 [RTL8365MB_MIB_ifOutOctets] = 1,
1253                 [RTL8365MB_MIB_ifOutUcastPkts] = 1,
1254                 [RTL8365MB_MIB_ifOutMulticastPkts] = 1,
1255                 [RTL8365MB_MIB_ifOutBroadcastPkts] = 1,
1256                 [RTL8365MB_MIB_dot3OutPauseFrames] = 1,
1257                 [RTL8365MB_MIB_ifOutDiscards] = 1,
1258                 [RTL8365MB_MIB_ifInOctets] = 1,
1259                 [RTL8365MB_MIB_ifInUcastPkts] = 1,
1260                 [RTL8365MB_MIB_ifInMulticastPkts] = 1,
1261                 [RTL8365MB_MIB_ifInBroadcastPkts] = 1,
1262                 [RTL8365MB_MIB_dot3InPauseFrames] = 1,
1263                 [RTL8365MB_MIB_dot3StatsSingleCollisionFrames] = 1,
1264                 [RTL8365MB_MIB_dot3StatsMultipleCollisionFrames] = 1,
1265                 [RTL8365MB_MIB_dot3StatsFCSErrors] = 1,
1266                 [RTL8365MB_MIB_dot3StatsDeferredTransmissions] = 1,
1267                 [RTL8365MB_MIB_dot3StatsLateCollisions] = 1,
1268                 [RTL8365MB_MIB_dot3StatsExcessiveCollisions] = 1,
1269
1270         };
1271         struct realtek_priv *priv = ds->priv;
1272         struct rtl8365mb *mb;
1273         int ret;
1274         int i;
1275
1276         mb = priv->chip_data;
1277
1278         mutex_lock(&mb->mib_lock);
1279         for (i = 0; i < RTL8365MB_MIB_END; i++) {
1280                 struct rtl8365mb_mib_counter *mib = &rtl8365mb_mib_counters[i];
1281
1282                 /* Only fetch required MIB counters (marked = 1 above) */
1283                 if (!cnt[i])
1284                         continue;
1285
1286                 ret = rtl8365mb_mib_counter_read(priv, port, mib->offset,
1287                                                  mib->length, &cnt[i]);
1288                 if (ret)
1289                         break;
1290         }
1291         mutex_unlock(&mb->mib_lock);
1292
1293         /* The RTL8365MB-VC exposes MIB objects, which we have to translate into
1294          * IEEE 802.3 Managed Objects. This is not always completely faithful,
1295          * but we try out best. See RFC 3635 for a detailed treatment of the
1296          * subject.
1297          */
1298
1299         mac_stats->FramesTransmittedOK = cnt[RTL8365MB_MIB_ifOutUcastPkts] +
1300                                          cnt[RTL8365MB_MIB_ifOutMulticastPkts] +
1301                                          cnt[RTL8365MB_MIB_ifOutBroadcastPkts] +
1302                                          cnt[RTL8365MB_MIB_dot3OutPauseFrames] -
1303                                          cnt[RTL8365MB_MIB_ifOutDiscards];
1304         mac_stats->SingleCollisionFrames =
1305                 cnt[RTL8365MB_MIB_dot3StatsSingleCollisionFrames];
1306         mac_stats->MultipleCollisionFrames =
1307                 cnt[RTL8365MB_MIB_dot3StatsMultipleCollisionFrames];
1308         mac_stats->FramesReceivedOK = cnt[RTL8365MB_MIB_ifInUcastPkts] +
1309                                       cnt[RTL8365MB_MIB_ifInMulticastPkts] +
1310                                       cnt[RTL8365MB_MIB_ifInBroadcastPkts] +
1311                                       cnt[RTL8365MB_MIB_dot3InPauseFrames];
1312         mac_stats->FrameCheckSequenceErrors =
1313                 cnt[RTL8365MB_MIB_dot3StatsFCSErrors];
1314         mac_stats->OctetsTransmittedOK = cnt[RTL8365MB_MIB_ifOutOctets] -
1315                                          18 * mac_stats->FramesTransmittedOK;
1316         mac_stats->FramesWithDeferredXmissions =
1317                 cnt[RTL8365MB_MIB_dot3StatsDeferredTransmissions];
1318         mac_stats->LateCollisions = cnt[RTL8365MB_MIB_dot3StatsLateCollisions];
1319         mac_stats->FramesAbortedDueToXSColls =
1320                 cnt[RTL8365MB_MIB_dot3StatsExcessiveCollisions];
1321         mac_stats->OctetsReceivedOK = cnt[RTL8365MB_MIB_ifInOctets] -
1322                                       18 * mac_stats->FramesReceivedOK;
1323         mac_stats->MulticastFramesXmittedOK =
1324                 cnt[RTL8365MB_MIB_ifOutMulticastPkts];
1325         mac_stats->BroadcastFramesXmittedOK =
1326                 cnt[RTL8365MB_MIB_ifOutBroadcastPkts];
1327         mac_stats->MulticastFramesReceivedOK =
1328                 cnt[RTL8365MB_MIB_ifInMulticastPkts];
1329         mac_stats->BroadcastFramesReceivedOK =
1330                 cnt[RTL8365MB_MIB_ifInBroadcastPkts];
1331 }
1332
1333 static void rtl8365mb_get_ctrl_stats(struct dsa_switch *ds, int port,
1334                                      struct ethtool_eth_ctrl_stats *ctrl_stats)
1335 {
1336         struct realtek_priv *priv = ds->priv;
1337         struct rtl8365mb_mib_counter *mib;
1338         struct rtl8365mb *mb;
1339
1340         mb = priv->chip_data;
1341         mib = &rtl8365mb_mib_counters[RTL8365MB_MIB_dot3ControlInUnknownOpcodes];
1342
1343         mutex_lock(&mb->mib_lock);
1344         rtl8365mb_mib_counter_read(priv, port, mib->offset, mib->length,
1345                                    &ctrl_stats->UnsupportedOpcodesReceived);
1346         mutex_unlock(&mb->mib_lock);
1347 }
1348
1349 static void rtl8365mb_stats_update(struct realtek_priv *priv, int port)
1350 {
1351         u64 cnt[RTL8365MB_MIB_END] = {
1352                 [RTL8365MB_MIB_ifOutOctets] = 1,
1353                 [RTL8365MB_MIB_ifOutUcastPkts] = 1,
1354                 [RTL8365MB_MIB_ifOutMulticastPkts] = 1,
1355                 [RTL8365MB_MIB_ifOutBroadcastPkts] = 1,
1356                 [RTL8365MB_MIB_ifOutDiscards] = 1,
1357                 [RTL8365MB_MIB_ifInOctets] = 1,
1358                 [RTL8365MB_MIB_ifInUcastPkts] = 1,
1359                 [RTL8365MB_MIB_ifInMulticastPkts] = 1,
1360                 [RTL8365MB_MIB_ifInBroadcastPkts] = 1,
1361                 [RTL8365MB_MIB_etherStatsDropEvents] = 1,
1362                 [RTL8365MB_MIB_etherStatsCollisions] = 1,
1363                 [RTL8365MB_MIB_etherStatsFragments] = 1,
1364                 [RTL8365MB_MIB_etherStatsJabbers] = 1,
1365                 [RTL8365MB_MIB_dot3StatsFCSErrors] = 1,
1366                 [RTL8365MB_MIB_dot3StatsLateCollisions] = 1,
1367         };
1368         struct rtl8365mb *mb = priv->chip_data;
1369         struct rtnl_link_stats64 *stats;
1370         int ret;
1371         int i;
1372
1373         stats = &mb->ports[port].stats;
1374
1375         mutex_lock(&mb->mib_lock);
1376         for (i = 0; i < RTL8365MB_MIB_END; i++) {
1377                 struct rtl8365mb_mib_counter *c = &rtl8365mb_mib_counters[i];
1378
1379                 /* Only fetch required MIB counters (marked = 1 above) */
1380                 if (!cnt[i])
1381                         continue;
1382
1383                 ret = rtl8365mb_mib_counter_read(priv, port, c->offset,
1384                                                  c->length, &cnt[i]);
1385                 if (ret)
1386                         break;
1387         }
1388         mutex_unlock(&mb->mib_lock);
1389
1390         /* Don't update statistics if there was an error reading the counters */
1391         if (ret)
1392                 return;
1393
1394         spin_lock(&mb->ports[port].stats_lock);
1395
1396         stats->rx_packets = cnt[RTL8365MB_MIB_ifInUcastPkts] +
1397                             cnt[RTL8365MB_MIB_ifInMulticastPkts] +
1398                             cnt[RTL8365MB_MIB_ifInBroadcastPkts] -
1399                             cnt[RTL8365MB_MIB_ifOutDiscards];
1400
1401         stats->tx_packets = cnt[RTL8365MB_MIB_ifOutUcastPkts] +
1402                             cnt[RTL8365MB_MIB_ifOutMulticastPkts] +
1403                             cnt[RTL8365MB_MIB_ifOutBroadcastPkts];
1404
1405         /* if{In,Out}Octets includes FCS - remove it */
1406         stats->rx_bytes = cnt[RTL8365MB_MIB_ifInOctets] - 4 * stats->rx_packets;
1407         stats->tx_bytes =
1408                 cnt[RTL8365MB_MIB_ifOutOctets] - 4 * stats->tx_packets;
1409
1410         stats->rx_dropped = cnt[RTL8365MB_MIB_etherStatsDropEvents];
1411         stats->tx_dropped = cnt[RTL8365MB_MIB_ifOutDiscards];
1412
1413         stats->multicast = cnt[RTL8365MB_MIB_ifInMulticastPkts];
1414         stats->collisions = cnt[RTL8365MB_MIB_etherStatsCollisions];
1415
1416         stats->rx_length_errors = cnt[RTL8365MB_MIB_etherStatsFragments] +
1417                                   cnt[RTL8365MB_MIB_etherStatsJabbers];
1418         stats->rx_crc_errors = cnt[RTL8365MB_MIB_dot3StatsFCSErrors];
1419         stats->rx_errors = stats->rx_length_errors + stats->rx_crc_errors;
1420
1421         stats->tx_aborted_errors = cnt[RTL8365MB_MIB_ifOutDiscards];
1422         stats->tx_window_errors = cnt[RTL8365MB_MIB_dot3StatsLateCollisions];
1423         stats->tx_errors = stats->tx_aborted_errors + stats->tx_window_errors;
1424
1425         spin_unlock(&mb->ports[port].stats_lock);
1426 }
1427
1428 static void rtl8365mb_stats_poll(struct work_struct *work)
1429 {
1430         struct rtl8365mb_port *p = container_of(to_delayed_work(work),
1431                                                 struct rtl8365mb_port,
1432                                                 mib_work);
1433         struct realtek_priv *priv = p->priv;
1434
1435         rtl8365mb_stats_update(priv, p->index);
1436
1437         schedule_delayed_work(&p->mib_work, RTL8365MB_STATS_INTERVAL_JIFFIES);
1438 }
1439
1440 static void rtl8365mb_get_stats64(struct dsa_switch *ds, int port,
1441                                   struct rtnl_link_stats64 *s)
1442 {
1443         struct realtek_priv *priv = ds->priv;
1444         struct rtl8365mb_port *p;
1445         struct rtl8365mb *mb;
1446
1447         mb = priv->chip_data;
1448         p = &mb->ports[port];
1449
1450         spin_lock(&p->stats_lock);
1451         memcpy(s, &p->stats, sizeof(*s));
1452         spin_unlock(&p->stats_lock);
1453 }
1454
1455 static void rtl8365mb_stats_setup(struct realtek_priv *priv)
1456 {
1457         struct rtl8365mb *mb = priv->chip_data;
1458         int i;
1459
1460         /* Per-chip global mutex to protect MIB counter access, since doing
1461          * so requires accessing a series of registers in a particular order.
1462          */
1463         mutex_init(&mb->mib_lock);
1464
1465         for (i = 0; i < priv->num_ports; i++) {
1466                 struct rtl8365mb_port *p = &mb->ports[i];
1467
1468                 if (dsa_is_unused_port(priv->ds, i))
1469                         continue;
1470
1471                 /* Per-port spinlock to protect the stats64 data */
1472                 spin_lock_init(&p->stats_lock);
1473
1474                 /* This work polls the MIB counters and keeps the stats64 data
1475                  * up-to-date.
1476                  */
1477                 INIT_DELAYED_WORK(&p->mib_work, rtl8365mb_stats_poll);
1478         }
1479 }
1480
1481 static void rtl8365mb_stats_teardown(struct realtek_priv *priv)
1482 {
1483         struct rtl8365mb *mb = priv->chip_data;
1484         int i;
1485
1486         for (i = 0; i < priv->num_ports; i++) {
1487                 struct rtl8365mb_port *p = &mb->ports[i];
1488
1489                 if (dsa_is_unused_port(priv->ds, i))
1490                         continue;
1491
1492                 cancel_delayed_work_sync(&p->mib_work);
1493         }
1494 }
1495
1496 static int rtl8365mb_get_and_clear_status_reg(struct realtek_priv *priv, u32 reg,
1497                                               u32 *val)
1498 {
1499         int ret;
1500
1501         ret = regmap_read(priv->map, reg, val);
1502         if (ret)
1503                 return ret;
1504
1505         return regmap_write(priv->map, reg, *val);
1506 }
1507
1508 static irqreturn_t rtl8365mb_irq(int irq, void *data)
1509 {
1510         struct realtek_priv *priv = data;
1511         unsigned long line_changes = 0;
1512         struct rtl8365mb *mb;
1513         u32 stat;
1514         int line;
1515         int ret;
1516
1517         mb = priv->chip_data;
1518
1519         ret = rtl8365mb_get_and_clear_status_reg(priv, RTL8365MB_INTR_STATUS_REG,
1520                                                  &stat);
1521         if (ret)
1522                 goto out_error;
1523
1524         if (stat & RTL8365MB_INTR_LINK_CHANGE_MASK) {
1525                 u32 linkdown_ind;
1526                 u32 linkup_ind;
1527                 u32 val;
1528
1529                 ret = rtl8365mb_get_and_clear_status_reg(
1530                         priv, RTL8365MB_PORT_LINKUP_IND_REG, &val);
1531                 if (ret)
1532                         goto out_error;
1533
1534                 linkup_ind = FIELD_GET(RTL8365MB_PORT_LINKUP_IND_MASK, val);
1535
1536                 ret = rtl8365mb_get_and_clear_status_reg(
1537                         priv, RTL8365MB_PORT_LINKDOWN_IND_REG, &val);
1538                 if (ret)
1539                         goto out_error;
1540
1541                 linkdown_ind = FIELD_GET(RTL8365MB_PORT_LINKDOWN_IND_MASK, val);
1542
1543                 line_changes = (linkup_ind | linkdown_ind) & mb->port_mask;
1544         }
1545
1546         if (!line_changes)
1547                 goto out_none;
1548
1549         for_each_set_bit(line, &line_changes, priv->num_ports) {
1550                 int child_irq = irq_find_mapping(priv->irqdomain, line);
1551
1552                 handle_nested_irq(child_irq);
1553         }
1554
1555         return IRQ_HANDLED;
1556
1557 out_error:
1558         dev_err(priv->dev, "failed to read interrupt status: %d\n", ret);
1559
1560 out_none:
1561         return IRQ_NONE;
1562 }
1563
1564 static struct irq_chip rtl8365mb_irq_chip = {
1565         .name = "rtl8365mb",
1566         /* The hardware doesn't support masking IRQs on a per-port basis */
1567 };
1568
1569 static int rtl8365mb_irq_map(struct irq_domain *domain, unsigned int irq,
1570                              irq_hw_number_t hwirq)
1571 {
1572         irq_set_chip_data(irq, domain->host_data);
1573         irq_set_chip_and_handler(irq, &rtl8365mb_irq_chip, handle_simple_irq);
1574         irq_set_nested_thread(irq, 1);
1575         irq_set_noprobe(irq);
1576
1577         return 0;
1578 }
1579
1580 static void rtl8365mb_irq_unmap(struct irq_domain *d, unsigned int irq)
1581 {
1582         irq_set_nested_thread(irq, 0);
1583         irq_set_chip_and_handler(irq, NULL, NULL);
1584         irq_set_chip_data(irq, NULL);
1585 }
1586
1587 static const struct irq_domain_ops rtl8365mb_irqdomain_ops = {
1588         .map = rtl8365mb_irq_map,
1589         .unmap = rtl8365mb_irq_unmap,
1590         .xlate = irq_domain_xlate_onecell,
1591 };
1592
1593 static int rtl8365mb_set_irq_enable(struct realtek_priv *priv, bool enable)
1594 {
1595         return regmap_update_bits(priv->map, RTL8365MB_INTR_CTRL_REG,
1596                                   RTL8365MB_INTR_LINK_CHANGE_MASK,
1597                                   FIELD_PREP(RTL8365MB_INTR_LINK_CHANGE_MASK,
1598                                              enable ? 1 : 0));
1599 }
1600
1601 static int rtl8365mb_irq_enable(struct realtek_priv *priv)
1602 {
1603         return rtl8365mb_set_irq_enable(priv, true);
1604 }
1605
1606 static int rtl8365mb_irq_disable(struct realtek_priv *priv)
1607 {
1608         return rtl8365mb_set_irq_enable(priv, false);
1609 }
1610
1611 static int rtl8365mb_irq_setup(struct realtek_priv *priv)
1612 {
1613         struct rtl8365mb *mb = priv->chip_data;
1614         struct device_node *intc;
1615         u32 irq_trig;
1616         int virq;
1617         int irq;
1618         u32 val;
1619         int ret;
1620         int i;
1621
1622         intc = of_get_child_by_name(priv->dev->of_node, "interrupt-controller");
1623         if (!intc) {
1624                 dev_err(priv->dev, "missing child interrupt-controller node\n");
1625                 return -EINVAL;
1626         }
1627
1628         /* rtl8365mb IRQs cascade off this one */
1629         irq = of_irq_get(intc, 0);
1630         if (irq <= 0) {
1631                 if (irq != -EPROBE_DEFER)
1632                         dev_err(priv->dev, "failed to get parent irq: %d\n",
1633                                 irq);
1634                 ret = irq ? irq : -EINVAL;
1635                 goto out_put_node;
1636         }
1637
1638         priv->irqdomain = irq_domain_add_linear(intc, priv->num_ports,
1639                                                 &rtl8365mb_irqdomain_ops, priv);
1640         if (!priv->irqdomain) {
1641                 dev_err(priv->dev, "failed to add irq domain\n");
1642                 ret = -ENOMEM;
1643                 goto out_put_node;
1644         }
1645
1646         for (i = 0; i < priv->num_ports; i++) {
1647                 virq = irq_create_mapping(priv->irqdomain, i);
1648                 if (!virq) {
1649                         dev_err(priv->dev,
1650                                 "failed to create irq domain mapping\n");
1651                         ret = -EINVAL;
1652                         goto out_remove_irqdomain;
1653                 }
1654
1655                 irq_set_parent(virq, irq);
1656         }
1657
1658         /* Configure chip interrupt signal polarity */
1659         irq_trig = irqd_get_trigger_type(irq_get_irq_data(irq));
1660         switch (irq_trig) {
1661         case IRQF_TRIGGER_RISING:
1662         case IRQF_TRIGGER_HIGH:
1663                 val = RTL8365MB_INTR_POLARITY_HIGH;
1664                 break;
1665         case IRQF_TRIGGER_FALLING:
1666         case IRQF_TRIGGER_LOW:
1667                 val = RTL8365MB_INTR_POLARITY_LOW;
1668                 break;
1669         default:
1670                 dev_err(priv->dev, "unsupported irq trigger type %u\n",
1671                         irq_trig);
1672                 ret = -EINVAL;
1673                 goto out_remove_irqdomain;
1674         }
1675
1676         ret = regmap_update_bits(priv->map, RTL8365MB_INTR_POLARITY_REG,
1677                                  RTL8365MB_INTR_POLARITY_MASK,
1678                                  FIELD_PREP(RTL8365MB_INTR_POLARITY_MASK, val));
1679         if (ret)
1680                 goto out_remove_irqdomain;
1681
1682         /* Disable the interrupt in case the chip has it enabled on reset */
1683         ret = rtl8365mb_irq_disable(priv);
1684         if (ret)
1685                 goto out_remove_irqdomain;
1686
1687         /* Clear the interrupt status register */
1688         ret = regmap_write(priv->map, RTL8365MB_INTR_STATUS_REG,
1689                            RTL8365MB_INTR_ALL_MASK);
1690         if (ret)
1691                 goto out_remove_irqdomain;
1692
1693         ret = request_threaded_irq(irq, NULL, rtl8365mb_irq, IRQF_ONESHOT,
1694                                    "rtl8365mb", priv);
1695         if (ret) {
1696                 dev_err(priv->dev, "failed to request irq: %d\n", ret);
1697                 goto out_remove_irqdomain;
1698         }
1699
1700         /* Store the irq so that we know to free it during teardown */
1701         mb->irq = irq;
1702
1703         ret = rtl8365mb_irq_enable(priv);
1704         if (ret)
1705                 goto out_free_irq;
1706
1707         of_node_put(intc);
1708
1709         return 0;
1710
1711 out_free_irq:
1712         free_irq(mb->irq, priv);
1713         mb->irq = 0;
1714
1715 out_remove_irqdomain:
1716         for (i = 0; i < priv->num_ports; i++) {
1717                 virq = irq_find_mapping(priv->irqdomain, i);
1718                 irq_dispose_mapping(virq);
1719         }
1720
1721         irq_domain_remove(priv->irqdomain);
1722         priv->irqdomain = NULL;
1723
1724 out_put_node:
1725         of_node_put(intc);
1726
1727         return ret;
1728 }
1729
1730 static void rtl8365mb_irq_teardown(struct realtek_priv *priv)
1731 {
1732         struct rtl8365mb *mb = priv->chip_data;
1733         int virq;
1734         int i;
1735
1736         if (mb->irq) {
1737                 free_irq(mb->irq, priv);
1738                 mb->irq = 0;
1739         }
1740
1741         if (priv->irqdomain) {
1742                 for (i = 0; i < priv->num_ports; i++) {
1743                         virq = irq_find_mapping(priv->irqdomain, i);
1744                         irq_dispose_mapping(virq);
1745                 }
1746
1747                 irq_domain_remove(priv->irqdomain);
1748                 priv->irqdomain = NULL;
1749         }
1750 }
1751
1752 static int rtl8365mb_cpu_config(struct realtek_priv *priv)
1753 {
1754         struct rtl8365mb *mb = priv->chip_data;
1755         struct rtl8365mb_cpu *cpu = &mb->cpu;
1756         u32 val;
1757         int ret;
1758
1759         ret = regmap_update_bits(priv->map, RTL8365MB_CPU_PORT_MASK_REG,
1760                                  RTL8365MB_CPU_PORT_MASK_MASK,
1761                                  FIELD_PREP(RTL8365MB_CPU_PORT_MASK_MASK,
1762                                             cpu->mask));
1763         if (ret)
1764                 return ret;
1765
1766         val = FIELD_PREP(RTL8365MB_CPU_CTRL_EN_MASK, cpu->enable ? 1 : 0) |
1767               FIELD_PREP(RTL8365MB_CPU_CTRL_INSERTMODE_MASK, cpu->insert) |
1768               FIELD_PREP(RTL8365MB_CPU_CTRL_TAG_POSITION_MASK, cpu->position) |
1769               FIELD_PREP(RTL8365MB_CPU_CTRL_RXBYTECOUNT_MASK, cpu->rx_length) |
1770               FIELD_PREP(RTL8365MB_CPU_CTRL_TAG_FORMAT_MASK, cpu->format) |
1771               FIELD_PREP(RTL8365MB_CPU_CTRL_TRAP_PORT_MASK, cpu->trap_port & 0x7) |
1772               FIELD_PREP(RTL8365MB_CPU_CTRL_TRAP_PORT_EXT_MASK,
1773                          cpu->trap_port >> 3 & 0x1);
1774         ret = regmap_write(priv->map, RTL8365MB_CPU_CTRL_REG, val);
1775         if (ret)
1776                 return ret;
1777
1778         return 0;
1779 }
1780
1781 static int rtl8365mb_change_tag_protocol(struct dsa_switch *ds,
1782                                          enum dsa_tag_protocol proto)
1783 {
1784         struct realtek_priv *priv = ds->priv;
1785         struct rtl8365mb_cpu *cpu;
1786         struct rtl8365mb *mb;
1787
1788         mb = priv->chip_data;
1789         cpu = &mb->cpu;
1790
1791         switch (proto) {
1792         case DSA_TAG_PROTO_RTL8_4:
1793                 cpu->format = RTL8365MB_CPU_FORMAT_8BYTES;
1794                 cpu->position = RTL8365MB_CPU_POS_AFTER_SA;
1795                 break;
1796         case DSA_TAG_PROTO_RTL8_4T:
1797                 cpu->format = RTL8365MB_CPU_FORMAT_8BYTES;
1798                 cpu->position = RTL8365MB_CPU_POS_BEFORE_CRC;
1799                 break;
1800         /* The switch also supports a 4-byte format, similar to rtl4a but with
1801          * the same 0x04 8-bit version and probably 8-bit port source/dest.
1802          * There is no public doc about it. Not supported yet and it will probably
1803          * never be.
1804          */
1805         default:
1806                 return -EPROTONOSUPPORT;
1807         }
1808
1809         return rtl8365mb_cpu_config(priv);
1810 }
1811
1812 static int rtl8365mb_switch_init(struct realtek_priv *priv)
1813 {
1814         struct rtl8365mb *mb = priv->chip_data;
1815         int ret;
1816         int i;
1817
1818         /* Do any chip-specific init jam before getting to the common stuff */
1819         if (mb->jam_table) {
1820                 for (i = 0; i < mb->jam_size; i++) {
1821                         ret = regmap_write(priv->map, mb->jam_table[i].reg,
1822                                            mb->jam_table[i].val);
1823                         if (ret)
1824                                 return ret;
1825                 }
1826         }
1827
1828         /* Common init jam */
1829         for (i = 0; i < ARRAY_SIZE(rtl8365mb_init_jam_common); i++) {
1830                 ret = regmap_write(priv->map, rtl8365mb_init_jam_common[i].reg,
1831                                    rtl8365mb_init_jam_common[i].val);
1832                 if (ret)
1833                         return ret;
1834         }
1835
1836         return 0;
1837 }
1838
1839 static int rtl8365mb_reset_chip(struct realtek_priv *priv)
1840 {
1841         u32 val;
1842
1843         priv->write_reg_noack(priv, RTL8365MB_CHIP_RESET_REG,
1844                               FIELD_PREP(RTL8365MB_CHIP_RESET_HW_MASK, 1));
1845
1846         /* Realtek documentation says the chip needs 1 second to reset. Sleep
1847          * for 100 ms before accessing any registers to prevent ACK timeouts.
1848          */
1849         msleep(100);
1850         return regmap_read_poll_timeout(priv->map, RTL8365MB_CHIP_RESET_REG, val,
1851                                         !(val & RTL8365MB_CHIP_RESET_HW_MASK),
1852                                         20000, 1e6);
1853 }
1854
1855 static int rtl8365mb_setup(struct dsa_switch *ds)
1856 {
1857         struct realtek_priv *priv = ds->priv;
1858         struct rtl8365mb_cpu *cpu;
1859         struct dsa_port *cpu_dp;
1860         struct rtl8365mb *mb;
1861         int ret;
1862         int i;
1863
1864         mb = priv->chip_data;
1865         cpu = &mb->cpu;
1866
1867         ret = rtl8365mb_reset_chip(priv);
1868         if (ret) {
1869                 dev_err(priv->dev, "failed to reset chip: %d\n", ret);
1870                 goto out_error;
1871         }
1872
1873         /* Configure switch to vendor-defined initial state */
1874         ret = rtl8365mb_switch_init(priv);
1875         if (ret) {
1876                 dev_err(priv->dev, "failed to initialize switch: %d\n", ret);
1877                 goto out_error;
1878         }
1879
1880         /* Set up cascading IRQs */
1881         ret = rtl8365mb_irq_setup(priv);
1882         if (ret == -EPROBE_DEFER)
1883                 return ret;
1884         else if (ret)
1885                 dev_info(priv->dev, "no interrupt support\n");
1886
1887         /* Configure CPU tagging */
1888         dsa_switch_for_each_cpu_port(cpu_dp, priv->ds) {
1889                 cpu->mask |= BIT(cpu_dp->index);
1890
1891                 if (cpu->trap_port == RTL8365MB_MAX_NUM_PORTS)
1892                         cpu->trap_port = cpu_dp->index;
1893         }
1894         cpu->enable = cpu->mask > 0;
1895         ret = rtl8365mb_cpu_config(priv);
1896         if (ret)
1897                 goto out_teardown_irq;
1898
1899         /* Configure ports */
1900         for (i = 0; i < priv->num_ports; i++) {
1901                 struct rtl8365mb_port *p = &mb->ports[i];
1902
1903                 if (dsa_is_unused_port(priv->ds, i))
1904                         continue;
1905
1906                 /* Forward only to the CPU */
1907                 ret = rtl8365mb_port_set_isolation(priv, i, cpu->mask);
1908                 if (ret)
1909                         goto out_teardown_irq;
1910
1911                 /* Disable learning */
1912                 ret = rtl8365mb_port_set_learning(priv, i, false);
1913                 if (ret)
1914                         goto out_teardown_irq;
1915
1916                 /* Set the initial STP state of all ports to DISABLED, otherwise
1917                  * ports will still forward frames to the CPU despite being
1918                  * administratively down by default.
1919                  */
1920                 rtl8365mb_port_stp_state_set(priv->ds, i, BR_STATE_DISABLED);
1921
1922                 /* Set up per-port private data */
1923                 p->priv = priv;
1924                 p->index = i;
1925         }
1926
1927         /* Set maximum packet length to 1536 bytes */
1928         ret = regmap_update_bits(priv->map, RTL8365MB_CFG0_MAX_LEN_REG,
1929                                  RTL8365MB_CFG0_MAX_LEN_MASK,
1930                                  FIELD_PREP(RTL8365MB_CFG0_MAX_LEN_MASK, 1536));
1931         if (ret)
1932                 goto out_teardown_irq;
1933
1934         if (priv->setup_interface) {
1935                 ret = priv->setup_interface(ds);
1936                 if (ret) {
1937                         dev_err(priv->dev, "could not set up MDIO bus\n");
1938                         goto out_teardown_irq;
1939                 }
1940         }
1941
1942         /* Start statistics counter polling */
1943         rtl8365mb_stats_setup(priv);
1944
1945         return 0;
1946
1947 out_teardown_irq:
1948         rtl8365mb_irq_teardown(priv);
1949
1950 out_error:
1951         return ret;
1952 }
1953
1954 static void rtl8365mb_teardown(struct dsa_switch *ds)
1955 {
1956         struct realtek_priv *priv = ds->priv;
1957
1958         rtl8365mb_stats_teardown(priv);
1959         rtl8365mb_irq_teardown(priv);
1960 }
1961
1962 static int rtl8365mb_get_chip_id_and_ver(struct regmap *map, u32 *id, u32 *ver)
1963 {
1964         int ret;
1965
1966         /* For some reason we have to write a magic value to an arbitrary
1967          * register whenever accessing the chip ID/version registers.
1968          */
1969         ret = regmap_write(map, RTL8365MB_MAGIC_REG, RTL8365MB_MAGIC_VALUE);
1970         if (ret)
1971                 return ret;
1972
1973         ret = regmap_read(map, RTL8365MB_CHIP_ID_REG, id);
1974         if (ret)
1975                 return ret;
1976
1977         ret = regmap_read(map, RTL8365MB_CHIP_VER_REG, ver);
1978         if (ret)
1979                 return ret;
1980
1981         /* Reset magic register */
1982         ret = regmap_write(map, RTL8365MB_MAGIC_REG, 0);
1983         if (ret)
1984                 return ret;
1985
1986         return 0;
1987 }
1988
1989 static int rtl8365mb_detect(struct realtek_priv *priv)
1990 {
1991         struct rtl8365mb *mb = priv->chip_data;
1992         u32 chip_id;
1993         u32 chip_ver;
1994         int ret;
1995
1996         ret = rtl8365mb_get_chip_id_and_ver(priv->map, &chip_id, &chip_ver);
1997         if (ret) {
1998                 dev_err(priv->dev, "failed to read chip id and version: %d\n",
1999                         ret);
2000                 return ret;
2001         }
2002
2003         switch (chip_id) {
2004         case RTL8365MB_CHIP_ID_8365MB_VC:
2005                 switch (chip_ver) {
2006                 case RTL8365MB_CHIP_VER_8365MB_VC:
2007                         dev_info(priv->dev,
2008                                  "found an RTL8365MB-VC switch (ver=0x%04x)\n",
2009                                  chip_ver);
2010                         break;
2011                 case RTL8365MB_CHIP_VER_8367RB:
2012                         dev_info(priv->dev,
2013                                  "found an RTL8367RB-VB switch (ver=0x%04x)\n",
2014                                  chip_ver);
2015                         break;
2016                 case RTL8365MB_CHIP_VER_8367S:
2017                         dev_info(priv->dev,
2018                                  "found an RTL8367S switch (ver=0x%04x)\n",
2019                                  chip_ver);
2020                         break;
2021                 default:
2022                         dev_err(priv->dev, "unrecognized switch version (ver=0x%04x)",
2023                                 chip_ver);
2024                         return -ENODEV;
2025                 }
2026
2027                 priv->num_ports = RTL8365MB_MAX_NUM_PORTS;
2028
2029                 mb->priv = priv;
2030                 mb->chip_id = chip_id;
2031                 mb->chip_ver = chip_ver;
2032                 mb->port_mask = GENMASK(priv->num_ports - 1, 0);
2033                 mb->learn_limit_max = RTL8365MB_LEARN_LIMIT_MAX;
2034                 mb->jam_table = rtl8365mb_init_jam_8365mb_vc;
2035                 mb->jam_size = ARRAY_SIZE(rtl8365mb_init_jam_8365mb_vc);
2036
2037                 mb->cpu.trap_port = RTL8365MB_MAX_NUM_PORTS;
2038                 mb->cpu.insert = RTL8365MB_CPU_INSERT_TO_ALL;
2039                 mb->cpu.position = RTL8365MB_CPU_POS_AFTER_SA;
2040                 mb->cpu.rx_length = RTL8365MB_CPU_RXLEN_64BYTES;
2041                 mb->cpu.format = RTL8365MB_CPU_FORMAT_8BYTES;
2042
2043                 break;
2044         default:
2045                 dev_err(priv->dev,
2046                         "found an unknown Realtek switch (id=0x%04x, ver=0x%04x)\n",
2047                         chip_id, chip_ver);
2048                 return -ENODEV;
2049         }
2050
2051         return 0;
2052 }
2053
2054 static const struct dsa_switch_ops rtl8365mb_switch_ops_smi = {
2055         .get_tag_protocol = rtl8365mb_get_tag_protocol,
2056         .change_tag_protocol = rtl8365mb_change_tag_protocol,
2057         .setup = rtl8365mb_setup,
2058         .teardown = rtl8365mb_teardown,
2059         .phylink_get_caps = rtl8365mb_phylink_get_caps,
2060         .phylink_mac_config = rtl8365mb_phylink_mac_config,
2061         .phylink_mac_link_down = rtl8365mb_phylink_mac_link_down,
2062         .phylink_mac_link_up = rtl8365mb_phylink_mac_link_up,
2063         .port_stp_state_set = rtl8365mb_port_stp_state_set,
2064         .get_strings = rtl8365mb_get_strings,
2065         .get_ethtool_stats = rtl8365mb_get_ethtool_stats,
2066         .get_sset_count = rtl8365mb_get_sset_count,
2067         .get_eth_phy_stats = rtl8365mb_get_phy_stats,
2068         .get_eth_mac_stats = rtl8365mb_get_mac_stats,
2069         .get_eth_ctrl_stats = rtl8365mb_get_ctrl_stats,
2070         .get_stats64 = rtl8365mb_get_stats64,
2071 };
2072
2073 static const struct dsa_switch_ops rtl8365mb_switch_ops_mdio = {
2074         .get_tag_protocol = rtl8365mb_get_tag_protocol,
2075         .change_tag_protocol = rtl8365mb_change_tag_protocol,
2076         .setup = rtl8365mb_setup,
2077         .teardown = rtl8365mb_teardown,
2078         .phylink_get_caps = rtl8365mb_phylink_get_caps,
2079         .phylink_mac_config = rtl8365mb_phylink_mac_config,
2080         .phylink_mac_link_down = rtl8365mb_phylink_mac_link_down,
2081         .phylink_mac_link_up = rtl8365mb_phylink_mac_link_up,
2082         .phy_read = rtl8365mb_dsa_phy_read,
2083         .phy_write = rtl8365mb_dsa_phy_write,
2084         .port_stp_state_set = rtl8365mb_port_stp_state_set,
2085         .get_strings = rtl8365mb_get_strings,
2086         .get_ethtool_stats = rtl8365mb_get_ethtool_stats,
2087         .get_sset_count = rtl8365mb_get_sset_count,
2088         .get_eth_phy_stats = rtl8365mb_get_phy_stats,
2089         .get_eth_mac_stats = rtl8365mb_get_mac_stats,
2090         .get_eth_ctrl_stats = rtl8365mb_get_ctrl_stats,
2091         .get_stats64 = rtl8365mb_get_stats64,
2092 };
2093
2094 static const struct realtek_ops rtl8365mb_ops = {
2095         .detect = rtl8365mb_detect,
2096         .phy_read = rtl8365mb_phy_read,
2097         .phy_write = rtl8365mb_phy_write,
2098 };
2099
2100 const struct realtek_variant rtl8365mb_variant = {
2101         .ds_ops_smi = &rtl8365mb_switch_ops_smi,
2102         .ds_ops_mdio = &rtl8365mb_switch_ops_mdio,
2103         .ops = &rtl8365mb_ops,
2104         .clk_delay = 10,
2105         .cmd_read = 0xb9,
2106         .cmd_write = 0xb8,
2107         .chip_data_sz = sizeof(struct rtl8365mb),
2108 };
2109 EXPORT_SYMBOL_GPL(rtl8365mb_variant);
2110
2111 MODULE_AUTHOR("Alvin Šipraga <alsi@bang-olufsen.dk>");
2112 MODULE_DESCRIPTION("Driver for RTL8365MB-VC ethernet switch");
2113 MODULE_LICENSE("GPL");