drivers/net/dsa/qca8k.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * Copyright (C) 2009 Felix Fietkau <nbd@nbd.name>
   4  * Copyright (C) 2011-2012 Gabor Juhos <juhosg@openwrt.org>
   5  * Copyright (c) 2015, 2019, The Linux Foundation. All rights reserved.
   6  * Copyright (c) 2016 John Crispin <john@phrozen.org>
   7  */
   8
   9 #include <linux/module.h>
  10 #include <linux/phy.h>
  11 #include <linux/netdevice.h>
  12 #include <net/dsa.h>
  13 #include <linux/of_net.h>
  14 #include <linux/of_platform.h>
  15 #include <linux/if_bridge.h>
  16 #include <linux/mdio.h>
  17 #include <linux/phylink.h>
  18 #include <linux/gpio/consumer.h>
  19 #include <linux/etherdevice.h>
  20
  21 #include "qca8k.h"
  22
  23 #define MIB_DESC(_s, _o, _n)    \
  24         {                       \
  25                 .size = (_s),   \
  26                 .offset = (_o), \
  27                 .name = (_n),   \
  28         }
  29
  30 static const struct qca8k_mib_desc ar8327_mib[] = {
  31         MIB_DESC(1, 0x00, "RxBroad"),
  32         MIB_DESC(1, 0x04, "RxPause"),
  33         MIB_DESC(1, 0x08, "RxMulti"),
  34         MIB_DESC(1, 0x0c, "RxFcsErr"),
  35         MIB_DESC(1, 0x10, "RxAlignErr"),
  36         MIB_DESC(1, 0x14, "RxRunt"),
  37         MIB_DESC(1, 0x18, "RxFragment"),
  38         MIB_DESC(1, 0x1c, "Rx64Byte"),
  39         MIB_DESC(1, 0x20, "Rx128Byte"),
  40         MIB_DESC(1, 0x24, "Rx256Byte"),
  41         MIB_DESC(1, 0x28, "Rx512Byte"),
  42         MIB_DESC(1, 0x2c, "Rx1024Byte"),
  43         MIB_DESC(1, 0x30, "Rx1518Byte"),
  44         MIB_DESC(1, 0x34, "RxMaxByte"),
  45         MIB_DESC(1, 0x38, "RxTooLong"),
  46         MIB_DESC(2, 0x3c, "RxGoodByte"),
  47         MIB_DESC(2, 0x44, "RxBadByte"),
  48         MIB_DESC(1, 0x4c, "RxOverFlow"),
  49         MIB_DESC(1, 0x50, "Filtered"),
  50         MIB_DESC(1, 0x54, "TxBroad"),
  51         MIB_DESC(1, 0x58, "TxPause"),
  52         MIB_DESC(1, 0x5c, "TxMulti"),
  53         MIB_DESC(1, 0x60, "TxUnderRun"),
  54         MIB_DESC(1, 0x64, "Tx64Byte"),
  55         MIB_DESC(1, 0x68, "Tx128Byte"),
  56         MIB_DESC(1, 0x6c, "Tx256Byte"),
  57         MIB_DESC(1, 0x70, "Tx512Byte"),
  58         MIB_DESC(1, 0x74, "Tx1024Byte"),
  59         MIB_DESC(1, 0x78, "Tx1518Byte"),
  60         MIB_DESC(1, 0x7c, "TxMaxByte"),
  61         MIB_DESC(1, 0x80, "TxOverSize"),
  62         MIB_DESC(2, 0x84, "TxByte"),
  63         MIB_DESC(1, 0x8c, "TxCollision"),
  64         MIB_DESC(1, 0x90, "TxAbortCol"),
  65         MIB_DESC(1, 0x94, "TxMultiCol"),
  66         MIB_DESC(1, 0x98, "TxSingleCol"),
  67         MIB_DESC(1, 0x9c, "TxExcDefer"),
  68         MIB_DESC(1, 0xa0, "TxDefer"),
  69         MIB_DESC(1, 0xa4, "TxLateCol"),
  70 };
  71
  72 /* The 32bit switch registers are accessed indirectly. To achieve this we need
  73  * to set the page of the register. Track the last page that was set to reduce
  74  * mdio writes
  75  */
  76 static u16 qca8k_current_page = 0xffff;
  77
  78 static void
  79 qca8k_split_addr(u32 regaddr, u16 *r1, u16 *r2, u16 *page)
  80 {
  81         regaddr >>= 1;
  82         *r1 = regaddr & 0x1e;
  83
  84         regaddr >>= 5;
  85         *r2 = regaddr & 0x7;
  86
  87         regaddr >>= 3;
  88         *page = regaddr & 0x3ff;
  89 }
  90
  91 static u32
  92 qca8k_mii_read32(struct mii_bus *bus, int phy_id, u32 regnum)
  93 {
  94         u32 val;
  95         int ret;
  96
  97         ret = bus->read(bus, phy_id, regnum);
  98         if (ret >= 0) {
  99                 val = ret;
 100                 ret = bus->read(bus, phy_id, regnum + 1);
 101                 val |= ret << 16;
 102         }
 103
 104         if (ret < 0) {
 105                 dev_err_ratelimited(&bus->dev,
 106                                     "failed to read qca8k 32bit register\n");
 107                 return ret;
 108         }
 109
 110         return val;
 111 }
 112
 113 static void
 114 qca8k_mii_write32(struct mii_bus *bus, int phy_id, u32 regnum, u32 val)
 115 {
 116         u16 lo, hi;
 117         int ret;
 118
 119         lo = val & 0xffff;
 120         hi = (u16)(val >> 16);
 121
 122         ret = bus->write(bus, phy_id, regnum, lo);
 123         if (ret >= 0)
 124                 ret = bus->write(bus, phy_id, regnum + 1, hi);
 125         if (ret < 0)
 126                 dev_err_ratelimited(&bus->dev,
 127                                     "failed to write qca8k 32bit register\n");
 128 }
 129
 130 static void
 131 qca8k_set_page(struct mii_bus *bus, u16 page)
 132 {
 133         if (page == qca8k_current_page)
 134                 return;
 135
 136         if (bus->write(bus, 0x18, 0, page) < 0)
 137                 dev_err_ratelimited(&bus->dev,
 138                                     "failed to set qca8k page\n");
 139         qca8k_current_page = page;
 140 }
 141
 142 static u32
 143 qca8k_read(struct qca8k_priv *priv, u32 reg)
 144 {
 145         u16 r1, r2, page;
 146         u32 val;
 147
 148         qca8k_split_addr(reg, &r1, &r2, &page);
 149
 150         mutex_lock_nested(&priv->bus->mdio_lock, MDIO_MUTEX_NESTED);
 151
 152         qca8k_set_page(priv->bus, page);
 153         val = qca8k_mii_read32(priv->bus, 0x10 | r2, r1);
 154
 155         mutex_unlock(&priv->bus->mdio_lock);
 156
 157         return val;
 158 }
 159
 160 static void
 161 qca8k_write(struct qca8k_priv *priv, u32 reg, u32 val)
 162 {
 163         u16 r1, r2, page;
 164
 165         qca8k_split_addr(reg, &r1, &r2, &page);
 166
 167         mutex_lock_nested(&priv->bus->mdio_lock, MDIO_MUTEX_NESTED);
 168
 169         qca8k_set_page(priv->bus, page);
 170         qca8k_mii_write32(priv->bus, 0x10 | r2, r1, val);
 171
 172         mutex_unlock(&priv->bus->mdio_lock);
 173 }
 174
 175 static u32
 176 qca8k_rmw(struct qca8k_priv *priv, u32 reg, u32 mask, u32 val)
 177 {
 178         u16 r1, r2, page;
 179         u32 ret;
 180
 181         qca8k_split_addr(reg, &r1, &r2, &page);
 182
 183         mutex_lock_nested(&priv->bus->mdio_lock, MDIO_MUTEX_NESTED);
 184
 185         qca8k_set_page(priv->bus, page);
 186         ret = qca8k_mii_read32(priv->bus, 0x10 | r2, r1);
 187         ret &= ~mask;
 188         ret |= val;
 189         qca8k_mii_write32(priv->bus, 0x10 | r2, r1, ret);
 190
 191         mutex_unlock(&priv->bus->mdio_lock);
 192
 193         return ret;
 194 }
 195
 196 static void
 197 qca8k_reg_set(struct qca8k_priv *priv, u32 reg, u32 val)
 198 {
 199         qca8k_rmw(priv, reg, 0, val);
 200 }
 201
 202 static void
 203 qca8k_reg_clear(struct qca8k_priv *priv, u32 reg, u32 val)
 204 {
 205         qca8k_rmw(priv, reg, val, 0);
 206 }
 207
 208 static int
 209 qca8k_regmap_read(void *ctx, uint32_t reg, uint32_t *val)
 210 {
 211         struct qca8k_priv *priv = (struct qca8k_priv *)ctx;
 212
 213         *val = qca8k_read(priv, reg);
 214
 215         return 0;
 216 }
 217
 218 static int
 219 qca8k_regmap_write(void *ctx, uint32_t reg, uint32_t val)
 220 {
 221         struct qca8k_priv *priv = (struct qca8k_priv *)ctx;
 222
 223         qca8k_write(priv, reg, val);
 224
 225         return 0;
 226 }
 227
 228 static const struct regmap_range qca8k_readable_ranges[] = {
 229         regmap_reg_range(0x0000, 0x00e4), /* Global control */
 230         regmap_reg_range(0x0100, 0x0168), /* EEE control */
 231         regmap_reg_range(0x0200, 0x0270), /* Parser control */
 232         regmap_reg_range(0x0400, 0x0454), /* ACL */
 233         regmap_reg_range(0x0600, 0x0718), /* Lookup */
 234         regmap_reg_range(0x0800, 0x0b70), /* QM */
 235         regmap_reg_range(0x0c00, 0x0c80), /* PKT */
 236         regmap_reg_range(0x0e00, 0x0e98), /* L3 */
 237         regmap_reg_range(0x1000, 0x10ac), /* MIB - Port0 */
 238         regmap_reg_range(0x1100, 0x11ac), /* MIB - Port1 */
 239         regmap_reg_range(0x1200, 0x12ac), /* MIB - Port2 */
 240         regmap_reg_range(0x1300, 0x13ac), /* MIB - Port3 */
 241         regmap_reg_range(0x1400, 0x14ac), /* MIB - Port4 */
 242         regmap_reg_range(0x1500, 0x15ac), /* MIB - Port5 */
 243         regmap_reg_range(0x1600, 0x16ac), /* MIB - Port6 */
 244
 245 };
 246
 247 static const struct regmap_access_table qca8k_readable_table = {
 248         .yes_ranges = qca8k_readable_ranges,
 249         .n_yes_ranges = ARRAY_SIZE(qca8k_readable_ranges),
 250 };
 251
 252 static struct regmap_config qca8k_regmap_config = {
 253         .reg_bits = 16,
 254         .val_bits = 32,
 255         .reg_stride = 4,
 256         .max_register = 0x16ac, /* end MIB - Port6 range */
 257         .reg_read = qca8k_regmap_read,
 258         .reg_write = qca8k_regmap_write,
 259         .rd_table = &qca8k_readable_table,
 260 };
 261
 262 static int
 263 qca8k_busy_wait(struct qca8k_priv *priv, u32 reg, u32 mask)
 264 {
 265         unsigned long timeout;
 266
 267         timeout = jiffies + msecs_to_jiffies(20);
 268
 269         /* loop until the busy flag has cleared */
 270         do {
 271                 u32 val = qca8k_read(priv, reg);
 272                 int busy = val & mask;
 273
 274                 if (!busy)
 275                         break;
 276                 cond_resched();
 277         } while (!time_after_eq(jiffies, timeout));
 278
 279         return time_after_eq(jiffies, timeout);
 280 }
 281
 282 static void
 283 qca8k_fdb_read(struct qca8k_priv *priv, struct qca8k_fdb *fdb)
 284 {
 285         u32 reg[4];
 286         int i;
 287
 288         /* load the ARL table into an array */
 289         for (i = 0; i < 4; i++)
 290                 reg[i] = qca8k_read(priv, QCA8K_REG_ATU_DATA0 + (i * 4));
 291
 292         /* vid - 83:72 */
 293         fdb->vid = (reg[2] >> QCA8K_ATU_VID_S) & QCA8K_ATU_VID_M;
 294         /* aging - 67:64 */
 295         fdb->aging = reg[2] & QCA8K_ATU_STATUS_M;
 296         /* portmask - 54:48 */
 297         fdb->port_mask = (reg[1] >> QCA8K_ATU_PORT_S) & QCA8K_ATU_PORT_M;
 298         /* mac - 47:0 */
 299         fdb->mac[0] = (reg[1] >> QCA8K_ATU_ADDR0_S) & 0xff;
 300         fdb->mac[1] = reg[1] & 0xff;
 301         fdb->mac[2] = (reg[0] >> QCA8K_ATU_ADDR2_S) & 0xff;
 302         fdb->mac[3] = (reg[0] >> QCA8K_ATU_ADDR3_S) & 0xff;
 303         fdb->mac[4] = (reg[0] >> QCA8K_ATU_ADDR4_S) & 0xff;
 304         fdb->mac[5] = reg[0] & 0xff;
 305 }
 306
 307 static void
 308 qca8k_fdb_write(struct qca8k_priv *priv, u16 vid, u8 port_mask, const u8 *mac,
 309                 u8 aging)
 310 {
 311         u32 reg[3] = { 0 };
 312         int i;
 313
 314         /* vid - 83:72 */
 315         reg[2] = (vid & QCA8K_ATU_VID_M) << QCA8K_ATU_VID_S;
 316         /* aging - 67:64 */
 317         reg[2] |= aging & QCA8K_ATU_STATUS_M;
 318         /* portmask - 54:48 */
 319         reg[1] = (port_mask & QCA8K_ATU_PORT_M) << QCA8K_ATU_PORT_S;
 320         /* mac - 47:0 */
 321         reg[1] |= mac[0] << QCA8K_ATU_ADDR0_S;
 322         reg[1] |= mac[1];
 323         reg[0] |= mac[2] << QCA8K_ATU_ADDR2_S;
 324         reg[0] |= mac[3] << QCA8K_ATU_ADDR3_S;
 325         reg[0] |= mac[4] << QCA8K_ATU_ADDR4_S;
 326         reg[0] |= mac[5];
 327
 328         /* load the array into the ARL table */
 329         for (i = 0; i < 3; i++)
 330                 qca8k_write(priv, QCA8K_REG_ATU_DATA0 + (i * 4), reg[i]);
 331 }
 332
 333 static int
 334 qca8k_fdb_access(struct qca8k_priv *priv, enum qca8k_fdb_cmd cmd, int port)
 335 {
 336         u32 reg;
 337
 338         /* Set the command and FDB index */
 339         reg = QCA8K_ATU_FUNC_BUSY;
 340         reg |= cmd;
 341         if (port >= 0) {
 342                 reg |= QCA8K_ATU_FUNC_PORT_EN;
 343                 reg |= (port & QCA8K_ATU_FUNC_PORT_M) << QCA8K_ATU_FUNC_PORT_S;
 344         }
 345
 346         /* Write the function register triggering the table access */
 347         qca8k_write(priv, QCA8K_REG_ATU_FUNC, reg);
 348
 349         /* wait for completion */
 350         if (qca8k_busy_wait(priv, QCA8K_REG_ATU_FUNC, QCA8K_ATU_FUNC_BUSY))
 351                 return -1;
 352
 353         /* Check for table full violation when adding an entry */
 354         if (cmd == QCA8K_FDB_LOAD) {
 355                 reg = qca8k_read(priv, QCA8K_REG_ATU_FUNC);
 356                 if (reg & QCA8K_ATU_FUNC_FULL)
 357                         return -1;
 358         }
 359
 360         return 0;
 361 }
 362
 363 static int
 364 qca8k_fdb_next(struct qca8k_priv *priv, struct qca8k_fdb *fdb, int port)
 365 {
 366         int ret;
 367
 368         qca8k_fdb_write(priv, fdb->vid, fdb->port_mask, fdb->mac, fdb->aging);
 369         ret = qca8k_fdb_access(priv, QCA8K_FDB_NEXT, port);
 370         if (ret >= 0)
 371                 qca8k_fdb_read(priv, fdb);
 372
 373         return ret;
 374 }
 375
 376 static int
 377 qca8k_fdb_add(struct qca8k_priv *priv, const u8 *mac, u16 port_mask,
 378               u16 vid, u8 aging)
 379 {
 380         int ret;
 381
 382         mutex_lock(&priv->reg_mutex);
 383         qca8k_fdb_write(priv, vid, port_mask, mac, aging);
 384         ret = qca8k_fdb_access(priv, QCA8K_FDB_LOAD, -1);
 385         mutex_unlock(&priv->reg_mutex);
 386
 387         return ret;
 388 }
 389
 390 static int
 391 qca8k_fdb_del(struct qca8k_priv *priv, const u8 *mac, u16 port_mask, u16 vid)
 392 {
 393         int ret;
 394
 395         mutex_lock(&priv->reg_mutex);
 396         qca8k_fdb_write(priv, vid, port_mask, mac, 0);
 397         ret = qca8k_fdb_access(priv, QCA8K_FDB_PURGE, -1);
 398         mutex_unlock(&priv->reg_mutex);
 399
 400         return ret;
 401 }
 402
 403 static void
 404 qca8k_fdb_flush(struct qca8k_priv *priv)
 405 {
 406         mutex_lock(&priv->reg_mutex);
 407         qca8k_fdb_access(priv, QCA8K_FDB_FLUSH, -1);
 408         mutex_unlock(&priv->reg_mutex);
 409 }
 410
 411 static int
 412 qca8k_vlan_access(struct qca8k_priv *priv, enum qca8k_vlan_cmd cmd, u16 vid)
 413 {
 414         u32 reg;
 415
 416         /* Set the command and VLAN index */
 417         reg = QCA8K_VTU_FUNC1_BUSY;
 418         reg |= cmd;
 419         reg |= vid << QCA8K_VTU_FUNC1_VID_S;
 420
 421         /* Write the function register triggering the table access */
 422         qca8k_write(priv, QCA8K_REG_VTU_FUNC1, reg);
 423
 424         /* wait for completion */
 425         if (qca8k_busy_wait(priv, QCA8K_REG_VTU_FUNC1, QCA8K_VTU_FUNC1_BUSY))
 426                 return -ETIMEDOUT;
 427
 428         /* Check for table full violation when adding an entry */
 429         if (cmd == QCA8K_VLAN_LOAD) {
 430                 reg = qca8k_read(priv, QCA8K_REG_VTU_FUNC1);
 431                 if (reg & QCA8K_VTU_FUNC1_FULL)
 432                         return -ENOMEM;
 433         }
 434
 435         return 0;
 436 }
 437
 438 static int
 439 qca8k_vlan_add(struct qca8k_priv *priv, u8 port, u16 vid, bool untagged)
 440 {
 441         u32 reg;
 442         int ret;
 443
 444         /*
 445            We do the right thing with VLAN 0 and treat it as untagged while
 446            preserving the tag on egress.
 447          */
 448         if (vid == 0)
 449                 return 0;
 450
 451         mutex_lock(&priv->reg_mutex);
 452         ret = qca8k_vlan_access(priv, QCA8K_VLAN_READ, vid);
 453         if (ret < 0)
 454                 goto out;
 455
 456         reg = qca8k_read(priv, QCA8K_REG_VTU_FUNC0);
 457         reg |= QCA8K_VTU_FUNC0_VALID | QCA8K_VTU_FUNC0_IVL_EN;
 458         reg &= ~(QCA8K_VTU_FUNC0_EG_MODE_MASK << QCA8K_VTU_FUNC0_EG_MODE_S(port));
 459         if (untagged)
 460                 reg |= QCA8K_VTU_FUNC0_EG_MODE_UNTAG <<
 461                                 QCA8K_VTU_FUNC0_EG_MODE_S(port);
 462         else
 463                 reg |= QCA8K_VTU_FUNC0_EG_MODE_TAG <<
 464                                 QCA8K_VTU_FUNC0_EG_MODE_S(port);
 465
 466         qca8k_write(priv, QCA8K_REG_VTU_FUNC0, reg);
 467         ret = qca8k_vlan_access(priv, QCA8K_VLAN_LOAD, vid);
 468
 469 out:
 470         mutex_unlock(&priv->reg_mutex);
 471
 472         return ret;
 473 }
 474
 475 static int
 476 qca8k_vlan_del(struct qca8k_priv *priv, u8 port, u16 vid)
 477 {
 478         u32 reg, mask;
 479         int ret, i;
 480         bool del;
 481
 482         mutex_lock(&priv->reg_mutex);
 483         ret = qca8k_vlan_access(priv, QCA8K_VLAN_READ, vid);
 484         if (ret < 0)
 485                 goto out;
 486
 487         reg = qca8k_read(priv, QCA8K_REG_VTU_FUNC0);
 488         reg &= ~(3 << QCA8K_VTU_FUNC0_EG_MODE_S(port));
 489         reg |= QCA8K_VTU_FUNC0_EG_MODE_NOT <<
 490                         QCA8K_VTU_FUNC0_EG_MODE_S(port);
 491
 492         /* Check if we're the last member to be removed */
 493         del = true;
 494         for (i = 0; i < QCA8K_NUM_PORTS; i++) {
 495                 mask = QCA8K_VTU_FUNC0_EG_MODE_NOT;
 496                 mask <<= QCA8K_VTU_FUNC0_EG_MODE_S(i);
 497
 498                 if ((reg & mask) != mask) {
 499                         del = false;
 500                         break;
 501                 }
 502         }
 503
 504         if (del) {
 505                 ret = qca8k_vlan_access(priv, QCA8K_VLAN_PURGE, vid);
 506         } else {
 507                 qca8k_write(priv, QCA8K_REG_VTU_FUNC0, reg);
 508                 ret = qca8k_vlan_access(priv, QCA8K_VLAN_LOAD, vid);
 509         }
 510
 511 out:
 512         mutex_unlock(&priv->reg_mutex);
 513
 514         return ret;
 515 }
 516
 517 static void
 518 qca8k_mib_init(struct qca8k_priv *priv)
 519 {
 520         mutex_lock(&priv->reg_mutex);
 521         qca8k_reg_set(priv, QCA8K_REG_MIB, QCA8K_MIB_FLUSH | QCA8K_MIB_BUSY);
 522         qca8k_busy_wait(priv, QCA8K_REG_MIB, QCA8K_MIB_BUSY);
 523         qca8k_reg_set(priv, QCA8K_REG_MIB, QCA8K_MIB_CPU_KEEP);
 524         qca8k_write(priv, QCA8K_REG_MODULE_EN, QCA8K_MODULE_EN_MIB);
 525         mutex_unlock(&priv->reg_mutex);
 526 }
 527
 528 static void
 529 qca8k_port_set_status(struct qca8k_priv *priv, int port, int enable)
 530 {
 531         u32 mask = QCA8K_PORT_STATUS_TXMAC | QCA8K_PORT_STATUS_RXMAC;
 532
 533         /* Port 0 and 6 have no internal PHY */
 534         if (port > 0 && port < 6)
 535                 mask |= QCA8K_PORT_STATUS_LINK_AUTO;
 536
 537         if (enable)
 538                 qca8k_reg_set(priv, QCA8K_REG_PORT_STATUS(port), mask);
 539         else
 540                 qca8k_reg_clear(priv, QCA8K_REG_PORT_STATUS(port), mask);
 541 }
 542
 543 static u32
 544 qca8k_port_to_phy(int port)
 545 {
 546         /* From Andrew Lunn:
 547          * Port 0 has no internal phy.
 548          * Port 1 has an internal PHY at MDIO address 0.
 549          * Port 2 has an internal PHY at MDIO address 1.
 550          * ...
 551          * Port 5 has an internal PHY at MDIO address 4.
 552          * Port 6 has no internal PHY.
 553          */
 554
 555         return port - 1;
 556 }
 557
 558 static int
 559 qca8k_mdio_write(struct qca8k_priv *priv, int port, u32 regnum, u16 data)
 560 {
 561         u32 phy, val;
 562
 563         if (regnum >= QCA8K_MDIO_MASTER_MAX_REG)
 564                 return -EINVAL;
 565
 566         /* callee is responsible for not passing bad ports,
 567          * but we still would like to make spills impossible.
 568          */
 569         phy = qca8k_port_to_phy(port) % PHY_MAX_ADDR;
 570         val = QCA8K_MDIO_MASTER_BUSY | QCA8K_MDIO_MASTER_EN |
 571               QCA8K_MDIO_MASTER_WRITE | QCA8K_MDIO_MASTER_PHY_ADDR(phy) |
 572               QCA8K_MDIO_MASTER_REG_ADDR(regnum) |
 573               QCA8K_MDIO_MASTER_DATA(data);
 574
 575         qca8k_write(priv, QCA8K_MDIO_MASTER_CTRL, val);
 576
 577         return qca8k_busy_wait(priv, QCA8K_MDIO_MASTER_CTRL,
 578                 QCA8K_MDIO_MASTER_BUSY);
 579 }
 580
 581 static int
 582 qca8k_mdio_read(struct qca8k_priv *priv, int port, u32 regnum)
 583 {
 584         u32 phy, val;
 585
 586         if (regnum >= QCA8K_MDIO_MASTER_MAX_REG)
 587                 return -EINVAL;
 588
 589         /* callee is responsible for not passing bad ports,
 590          * but we still would like to make spills impossible.
 591          */
 592         phy = qca8k_port_to_phy(port) % PHY_MAX_ADDR;
 593         val = QCA8K_MDIO_MASTER_BUSY | QCA8K_MDIO_MASTER_EN |
 594               QCA8K_MDIO_MASTER_READ | QCA8K_MDIO_MASTER_PHY_ADDR(phy) |
 595               QCA8K_MDIO_MASTER_REG_ADDR(regnum);
 596
 597         qca8k_write(priv, QCA8K_MDIO_MASTER_CTRL, val);
 598
 599         if (qca8k_busy_wait(priv, QCA8K_MDIO_MASTER_CTRL,
 600                             QCA8K_MDIO_MASTER_BUSY))
 601                 return -ETIMEDOUT;
 602
 603         val = (qca8k_read(priv, QCA8K_MDIO_MASTER_CTRL) &
 604                 QCA8K_MDIO_MASTER_DATA_MASK);
 605
 606         return val;
 607 }
 608
 609 static int
 610 qca8k_phy_write(struct dsa_switch *ds, int port, int regnum, u16 data)
 611 {
 612         struct qca8k_priv *priv = ds->priv;
 613
 614         return qca8k_mdio_write(priv, port, regnum, data);
 615 }
 616
 617 static int
 618 qca8k_phy_read(struct dsa_switch *ds, int port, int regnum)
 619 {
 620         struct qca8k_priv *priv = ds->priv;
 621         int ret;
 622
 623         ret = qca8k_mdio_read(priv, port, regnum);
 624
 625         if (ret < 0)
 626                 return 0xffff;
 627
 628         return ret;
 629 }
 630
 631 static int
 632 qca8k_setup_mdio_bus(struct qca8k_priv *priv)
 633 {
 634         u32 internal_mdio_mask = 0, external_mdio_mask = 0, reg;
 635         struct device_node *ports, *port;
 636         int err;
 637
 638         ports = of_get_child_by_name(priv->dev->of_node, "ports");
 639         if (!ports)
 640                 return -EINVAL;
 641
 642         for_each_available_child_of_node(ports, port) {
 643                 err = of_property_read_u32(port, "reg", &reg);
 644                 if (err) {
 645                         of_node_put(port);
 646                         of_node_put(ports);
 647                         return err;
 648                 }
 649
 650                 if (!dsa_is_user_port(priv->ds, reg))
 651                         continue;
 652
 653                 if (of_property_read_bool(port, "phy-handle"))
 654                         external_mdio_mask |= BIT(reg);
 655                 else
 656                         internal_mdio_mask |= BIT(reg);
 657         }
 658
 659         of_node_put(ports);
 660         if (!external_mdio_mask && !internal_mdio_mask) {
 661                 dev_err(priv->dev, "no PHYs are defined.\n");
 662                 return -EINVAL;
 663         }
 664
 665         /* The QCA8K_MDIO_MASTER_EN Bit, which grants access to PHYs through
 666          * the MDIO_MASTER register also _disconnects_ the external MDC
 667          * passthrough to the internal PHYs. It's not possible to use both
 668          * configurations at the same time!
 669          *
 670          * Because this came up during the review process:
 671          * If the external mdio-bus driver is capable magically disabling
 672          * the QCA8K_MDIO_MASTER_EN and mutex/spin-locking out the qca8k's
 673          * accessors for the time being, it would be possible to pull this
 674          * off.
 675          */
 676         if (!!external_mdio_mask && !!internal_mdio_mask) {
 677                 dev_err(priv->dev, "either internal or external mdio bus configuration is supported.\n");
 678                 return -EINVAL;
 679         }
 680
 681         if (external_mdio_mask) {
 682                 /* Make sure to disable the internal mdio bus in cases
 683                  * a dt-overlay and driver reload changed the configuration
 684                  */
 685
 686                 qca8k_reg_clear(priv, QCA8K_MDIO_MASTER_CTRL,
 687                                 QCA8K_MDIO_MASTER_EN);
 688                 return 0;
 689         }
 690
 691         priv->ops.phy_read = qca8k_phy_read;
 692         priv->ops.phy_write = qca8k_phy_write;
 693         return 0;
 694 }
 695
 696 static int
 697 qca8k_setup(struct dsa_switch *ds)
 698 {
 699         struct qca8k_priv *priv = (struct qca8k_priv *)ds->priv;
 700         int ret, i;
 701
 702         /* Make sure that port 0 is the cpu port */
 703         if (!dsa_is_cpu_port(ds, 0)) {
 704                 pr_err("port 0 is not the CPU port\n");
 705                 return -EINVAL;
 706         }
 707
 708         mutex_init(&priv->reg_mutex);
 709
 710         /* Start by setting up the register mapping */
 711         priv->regmap = devm_regmap_init(ds->dev, NULL, priv,
 712                                         &qca8k_regmap_config);
 713         if (IS_ERR(priv->regmap))
 714                 pr_warn("regmap initialization failed");
 715
 716         ret = qca8k_setup_mdio_bus(priv);
 717         if (ret)
 718                 return ret;
 719
 720         /* Enable CPU Port */
 721         qca8k_reg_set(priv, QCA8K_REG_GLOBAL_FW_CTRL0,
 722                       QCA8K_GLOBAL_FW_CTRL0_CPU_PORT_EN);
 723
 724         /* Enable MIB counters */
 725         qca8k_mib_init(priv);
 726
 727         /* Enable QCA header mode on the cpu port */
 728         qca8k_write(priv, QCA8K_REG_PORT_HDR_CTRL(QCA8K_CPU_PORT),
 729                     QCA8K_PORT_HDR_CTRL_ALL << QCA8K_PORT_HDR_CTRL_TX_S |
 730                     QCA8K_PORT_HDR_CTRL_ALL << QCA8K_PORT_HDR_CTRL_RX_S);
 731
 732         /* Disable forwarding by default on all ports */
 733         for (i = 0; i < QCA8K_NUM_PORTS; i++)
 734                 qca8k_rmw(priv, QCA8K_PORT_LOOKUP_CTRL(i),
 735                           QCA8K_PORT_LOOKUP_MEMBER, 0);
 736
 737         /* Disable MAC by default on all ports */
 738         for (i = 1; i < QCA8K_NUM_PORTS; i++)
 739                 qca8k_port_set_status(priv, i, 0);
 740
 741         /* Forward all unknown frames to CPU port for Linux processing */
 742         qca8k_write(priv, QCA8K_REG_GLOBAL_FW_CTRL1,
 743                     BIT(0) << QCA8K_GLOBAL_FW_CTRL1_IGMP_DP_S |
 744                     BIT(0) << QCA8K_GLOBAL_FW_CTRL1_BC_DP_S |
 745                     BIT(0) << QCA8K_GLOBAL_FW_CTRL1_MC_DP_S |
 746                     BIT(0) << QCA8K_GLOBAL_FW_CTRL1_UC_DP_S);
 747
 748         /* Setup connection between CPU port & user ports */
 749         for (i = 0; i < QCA8K_NUM_PORTS; i++) {
 750                 /* CPU port gets connected to all user ports of the switch */
 751                 if (dsa_is_cpu_port(ds, i)) {
 752                         qca8k_rmw(priv, QCA8K_PORT_LOOKUP_CTRL(QCA8K_CPU_PORT),
 753                                   QCA8K_PORT_LOOKUP_MEMBER, dsa_user_ports(ds));
 754                 }
 755
 756                 /* Individual user ports get connected to CPU port only */
 757                 if (dsa_is_user_port(ds, i)) {
 758                         int shift = 16 * (i % 2);
 759
 760                         qca8k_rmw(priv, QCA8K_PORT_LOOKUP_CTRL(i),
 761                                   QCA8K_PORT_LOOKUP_MEMBER,
 762                                   BIT(QCA8K_CPU_PORT));
 763
 764                         /* Enable ARP Auto-learning by default */
 765                         qca8k_reg_set(priv, QCA8K_PORT_LOOKUP_CTRL(i),
 766                                       QCA8K_PORT_LOOKUP_LEARN);
 767
 768                         /* For port based vlans to work we need to set the
 769                          * default egress vid
 770                          */
 771                         qca8k_rmw(priv, QCA8K_EGRESS_VLAN(i),
 772                                   0xfff << shift,
 773                                   QCA8K_PORT_VID_DEF << shift);
 774                         qca8k_write(priv, QCA8K_REG_PORT_VLAN_CTRL0(i),
 775                                     QCA8K_PORT_VLAN_CVID(QCA8K_PORT_VID_DEF) |
 776                                     QCA8K_PORT_VLAN_SVID(QCA8K_PORT_VID_DEF));
 777                 }
 778         }
 779
 780         /* Setup our port MTUs to match power on defaults */
 781         for (i = 0; i < QCA8K_NUM_PORTS; i++)
 782                 priv->port_mtu[i] = ETH_FRAME_LEN + ETH_FCS_LEN;
 783         qca8k_write(priv, QCA8K_MAX_FRAME_SIZE, ETH_FRAME_LEN + ETH_FCS_LEN);
 784
 785         /* Flush the FDB table */
 786         qca8k_fdb_flush(priv);
 787
 788         /* We don't have interrupts for link changes, so we need to poll */
 789         ds->pcs_poll = true;
 790
 791         return 0;
 792 }
 793
 794 static void
 795 qca8k_phylink_mac_config(struct dsa_switch *ds, int port, unsigned int mode,
 796                          const struct phylink_link_state *state)
 797 {
 798         struct qca8k_priv *priv = ds->priv;
 799         u32 reg, val;
 800
 801         switch (port) {
 802         case 0: /* 1st CPU port */
 803                 if (state->interface != PHY_INTERFACE_MODE_RGMII &&
 804                     state->interface != PHY_INTERFACE_MODE_RGMII_ID &&
 805                     state->interface != PHY_INTERFACE_MODE_SGMII)
 806                         return;
 807
 808                 reg = QCA8K_REG_PORT0_PAD_CTRL;
 809                 break;
 810         case 1:
 811         case 2:
 812         case 3:
 813         case 4:
 814         case 5:
 815                 /* Internal PHY, nothing to do */
 816                 return;
 817         case 6: /* 2nd CPU port / external PHY */
 818                 if (state->interface != PHY_INTERFACE_MODE_RGMII &&
 819                     state->interface != PHY_INTERFACE_MODE_RGMII_ID &&
 820                     state->interface != PHY_INTERFACE_MODE_SGMII &&
 821                     state->interface != PHY_INTERFACE_MODE_1000BASEX)
 822                         return;
 823
 824                 reg = QCA8K_REG_PORT6_PAD_CTRL;
 825                 break;
 826         default:
 827                 dev_err(ds->dev, "%s: unsupported port: %i\n", __func__, port);
 828                 return;
 829         }
 830
 831         if (port != 6 && phylink_autoneg_inband(mode)) {
 832                 dev_err(ds->dev, "%s: in-band negotiation unsupported\n",
 833                         __func__);
 834                 return;
 835         }
 836
 837         switch (state->interface) {
 838         case PHY_INTERFACE_MODE_RGMII:
 839                 /* RGMII mode means no delay so don't enable the delay */
 840                 qca8k_write(priv, reg, QCA8K_PORT_PAD_RGMII_EN);
 841                 break;
 842         case PHY_INTERFACE_MODE_RGMII_ID:
 843                 /* RGMII_ID needs internal delay. This is enabled through
 844                  * PORT5_PAD_CTRL for all ports, rather than individual port
 845                  * registers
 846                  */
 847                 qca8k_write(priv, reg,
 848                             QCA8K_PORT_PAD_RGMII_EN |
 849                             QCA8K_PORT_PAD_RGMII_TX_DELAY(QCA8K_MAX_DELAY) |
 850                             QCA8K_PORT_PAD_RGMII_RX_DELAY(QCA8K_MAX_DELAY));
 851                 qca8k_write(priv, QCA8K_REG_PORT5_PAD_CTRL,
 852                             QCA8K_PORT_PAD_RGMII_RX_DELAY_EN);
 853                 break;
 854         case PHY_INTERFACE_MODE_SGMII:
 855         case PHY_INTERFACE_MODE_1000BASEX:
 856                 /* Enable SGMII on the port */
 857                 qca8k_write(priv, reg, QCA8K_PORT_PAD_SGMII_EN);
 858
 859                 /* Enable/disable SerDes auto-negotiation as necessary */
 860                 val = qca8k_read(priv, QCA8K_REG_PWS);
 861                 if (phylink_autoneg_inband(mode))
 862                         val &= ~QCA8K_PWS_SERDES_AEN_DIS;
 863                 else
 864                         val |= QCA8K_PWS_SERDES_AEN_DIS;
 865                 qca8k_write(priv, QCA8K_REG_PWS, val);
 866
 867                 /* Configure the SGMII parameters */
 868                 val = qca8k_read(priv, QCA8K_REG_SGMII_CTRL);
 869
 870                 val |= QCA8K_SGMII_EN_PLL | QCA8K_SGMII_EN_RX |
 871                         QCA8K_SGMII_EN_TX | QCA8K_SGMII_EN_SD;
 872
 873                 if (dsa_is_cpu_port(ds, port)) {
 874                         /* CPU port, we're talking to the CPU MAC, be a PHY */
 875                         val &= ~QCA8K_SGMII_MODE_CTRL_MASK;
 876                         val |= QCA8K_SGMII_MODE_CTRL_PHY;
 877                 } else if (state->interface == PHY_INTERFACE_MODE_SGMII) {
 878                         val &= ~QCA8K_SGMII_MODE_CTRL_MASK;
 879                         val |= QCA8K_SGMII_MODE_CTRL_MAC;
 880                 } else if (state->interface == PHY_INTERFACE_MODE_1000BASEX) {
 881                         val &= ~QCA8K_SGMII_MODE_CTRL_MASK;
 882                         val |= QCA8K_SGMII_MODE_CTRL_BASEX;
 883                 }
 884
 885                 qca8k_write(priv, QCA8K_REG_SGMII_CTRL, val);
 886                 break;
 887         default:
 888                 dev_err(ds->dev, "xMII mode %s not supported for port %d\n",
 889                         phy_modes(state->interface), port);
 890                 return;
 891         }
 892 }
 893
 894 static void
 895 qca8k_phylink_validate(struct dsa_switch *ds, int port,
 896                        unsigned long *supported,
 897                        struct phylink_link_state *state)
 898 {
 899         __ETHTOOL_DECLARE_LINK_MODE_MASK(mask) = { 0, };
 900
 901         switch (port) {
 902         case 0: /* 1st CPU port */
 903                 if (state->interface != PHY_INTERFACE_MODE_NA &&
 904                     state->interface != PHY_INTERFACE_MODE_RGMII &&
 905                     state->interface != PHY_INTERFACE_MODE_RGMII_ID &&
 906                     state->interface != PHY_INTERFACE_MODE_SGMII)
 907                         goto unsupported;
 908                 break;
 909         case 1:
 910         case 2:
 911         case 3:
 912         case 4:
 913         case 5:
 914                 /* Internal PHY */
 915                 if (state->interface != PHY_INTERFACE_MODE_NA &&
 916                     state->interface != PHY_INTERFACE_MODE_GMII)
 917                         goto unsupported;
 918                 break;
 919         case 6: /* 2nd CPU port / external PHY */
 920                 if (state->interface != PHY_INTERFACE_MODE_NA &&
 921                     state->interface != PHY_INTERFACE_MODE_RGMII &&
 922                     state->interface != PHY_INTERFACE_MODE_RGMII_ID &&
 923                     state->interface != PHY_INTERFACE_MODE_SGMII &&
 924                     state->interface != PHY_INTERFACE_MODE_1000BASEX)
 925                         goto unsupported;
 926                 break;
 927         default:
 928 unsupported:
 929                 linkmode_zero(supported);
 930                 return;
 931         }
 932
 933         phylink_set_port_modes(mask);
 934         phylink_set(mask, Autoneg);
 935
 936         phylink_set(mask, 1000baseT_Full);
 937         phylink_set(mask, 10baseT_Half);
 938         phylink_set(mask, 10baseT_Full);
 939         phylink_set(mask, 100baseT_Half);
 940         phylink_set(mask, 100baseT_Full);
 941
 942         if (state->interface == PHY_INTERFACE_MODE_1000BASEX)
 943                 phylink_set(mask, 1000baseX_Full);
 944
 945         phylink_set(mask, Pause);
 946         phylink_set(mask, Asym_Pause);
 947
 948         linkmode_and(supported, supported, mask);
 949         linkmode_and(state->advertising, state->advertising, mask);
 950 }
 951
 952 static int
 953 qca8k_phylink_mac_link_state(struct dsa_switch *ds, int port,
 954                              struct phylink_link_state *state)
 955 {
 956         struct qca8k_priv *priv = ds->priv;
 957         u32 reg;
 958
 959         reg = qca8k_read(priv, QCA8K_REG_PORT_STATUS(port));
 960
 961         state->link = !!(reg & QCA8K_PORT_STATUS_LINK_UP);
 962         state->an_complete = state->link;
 963         state->an_enabled = !!(reg & QCA8K_PORT_STATUS_LINK_AUTO);
 964         state->duplex = (reg & QCA8K_PORT_STATUS_DUPLEX) ? DUPLEX_FULL :
 965                                                            DUPLEX_HALF;
 966
 967         switch (reg & QCA8K_PORT_STATUS_SPEED) {
 968         case QCA8K_PORT_STATUS_SPEED_10:
 969                 state->speed = SPEED_10;
 970                 break;
 971         case QCA8K_PORT_STATUS_SPEED_100:
 972                 state->speed = SPEED_100;
 973                 break;
 974         case QCA8K_PORT_STATUS_SPEED_1000:
 975                 state->speed = SPEED_1000;
 976                 break;
 977         default:
 978                 state->speed = SPEED_UNKNOWN;
 979                 break;
 980         }
 981
 982         state->pause = MLO_PAUSE_NONE;
 983         if (reg & QCA8K_PORT_STATUS_RXFLOW)
 984                 state->pause |= MLO_PAUSE_RX;
 985         if (reg & QCA8K_PORT_STATUS_TXFLOW)
 986                 state->pause |= MLO_PAUSE_TX;
 987
 988         return 1;
 989 }
 990
 991 static void
 992 qca8k_phylink_mac_link_down(struct dsa_switch *ds, int port, unsigned int mode,
 993                             phy_interface_t interface)
 994 {
 995         struct qca8k_priv *priv = ds->priv;
 996
 997         qca8k_port_set_status(priv, port, 0);
 998 }
 999
1000 static void
1001 qca8k_phylink_mac_link_up(struct dsa_switch *ds, int port, unsigned int mode,
1002                           phy_interface_t interface, struct phy_device *phydev,
1003                           int speed, int duplex, bool tx_pause, bool rx_pause)
1004 {
1005         struct qca8k_priv *priv = ds->priv;
1006         u32 reg;
1007
1008         if (phylink_autoneg_inband(mode)) {
1009                 reg = QCA8K_PORT_STATUS_LINK_AUTO;
1010         } else {
1011                 switch (speed) {
1012                 case SPEED_10:
1013                         reg = QCA8K_PORT_STATUS_SPEED_10;
1014                         break;
1015                 case SPEED_100:
1016                         reg = QCA8K_PORT_STATUS_SPEED_100;
1017                         break;
1018                 case SPEED_1000:
1019                         reg = QCA8K_PORT_STATUS_SPEED_1000;
1020                         break;
1021                 default:
1022                         reg = QCA8K_PORT_STATUS_LINK_AUTO;
1023                         break;
1024                 }
1025
1026                 if (duplex == DUPLEX_FULL)
1027                         reg |= QCA8K_PORT_STATUS_DUPLEX;
1028
1029                 if (rx_pause || dsa_is_cpu_port(ds, port))
1030                         reg |= QCA8K_PORT_STATUS_RXFLOW;
1031
1032                 if (tx_pause || dsa_is_cpu_port(ds, port))
1033                         reg |= QCA8K_PORT_STATUS_TXFLOW;
1034         }
1035
1036         reg |= QCA8K_PORT_STATUS_TXMAC | QCA8K_PORT_STATUS_RXMAC;
1037
1038         qca8k_write(priv, QCA8K_REG_PORT_STATUS(port), reg);
1039 }
1040
1041 static void
1042 qca8k_get_strings(struct dsa_switch *ds, int port, u32 stringset, uint8_t *data)
1043 {
1044         int i;
1045
1046         if (stringset != ETH_SS_STATS)
1047                 return;
1048
1049         for (i = 0; i < ARRAY_SIZE(ar8327_mib); i++)
1050                 strncpy(data + i * ETH_GSTRING_LEN, ar8327_mib[i].name,
1051                         ETH_GSTRING_LEN);
1052 }
1053
1054 static void
1055 qca8k_get_ethtool_stats(struct dsa_switch *ds, int port,
1056                         uint64_t *data)
1057 {
1058         struct qca8k_priv *priv = (struct qca8k_priv *)ds->priv;
1059         const struct qca8k_mib_desc *mib;
1060         u32 reg, i;
1061         u64 hi;
1062
1063         for (i = 0; i < ARRAY_SIZE(ar8327_mib); i++) {
1064                 mib = &ar8327_mib[i];
1065                 reg = QCA8K_PORT_MIB_COUNTER(port) + mib->offset;
1066
1067                 data[i] = qca8k_read(priv, reg);
1068                 if (mib->size == 2) {
1069                         hi = qca8k_read(priv, reg + 4);
1070                         data[i] |= hi << 32;
1071                 }
1072         }
1073 }
1074
1075 static int
1076 qca8k_get_sset_count(struct dsa_switch *ds, int port, int sset)
1077 {
1078         if (sset != ETH_SS_STATS)
1079                 return 0;
1080
1081         return ARRAY_SIZE(ar8327_mib);
1082 }
1083
1084 static int
1085 qca8k_set_mac_eee(struct dsa_switch *ds, int port, struct ethtool_eee *eee)
1086 {
1087         struct qca8k_priv *priv = (struct qca8k_priv *)ds->priv;
1088         u32 lpi_en = QCA8K_REG_EEE_CTRL_LPI_EN(port);
1089         u32 reg;
1090
1091         mutex_lock(&priv->reg_mutex);
1092         reg = qca8k_read(priv, QCA8K_REG_EEE_CTRL);
1093         if (eee->eee_enabled)
1094                 reg |= lpi_en;
1095         else
1096                 reg &= ~lpi_en;
1097         qca8k_write(priv, QCA8K_REG_EEE_CTRL, reg);
1098         mutex_unlock(&priv->reg_mutex);
1099
1100         return 0;
1101 }
1102
1103 static int
1104 qca8k_get_mac_eee(struct dsa_switch *ds, int port, struct ethtool_eee *e)
1105 {
1106         /* Nothing to do on the port's MAC */
1107         return 0;
1108 }
1109
1110 static void
1111 qca8k_port_stp_state_set(struct dsa_switch *ds, int port, u8 state)
1112 {
1113         struct qca8k_priv *priv = (struct qca8k_priv *)ds->priv;
1114         u32 stp_state;
1115
1116         switch (state) {
1117         case BR_STATE_DISABLED:
1118                 stp_state = QCA8K_PORT_LOOKUP_STATE_DISABLED;
1119                 break;
1120         case BR_STATE_BLOCKING:
1121                 stp_state = QCA8K_PORT_LOOKUP_STATE_BLOCKING;
1122                 break;
1123         case BR_STATE_LISTENING:
1124                 stp_state = QCA8K_PORT_LOOKUP_STATE_LISTENING;
1125                 break;
1126         case BR_STATE_LEARNING:
1127                 stp_state = QCA8K_PORT_LOOKUP_STATE_LEARNING;
1128                 break;
1129         case BR_STATE_FORWARDING:
1130         default:
1131                 stp_state = QCA8K_PORT_LOOKUP_STATE_FORWARD;
1132                 break;
1133         }
1134
1135         qca8k_rmw(priv, QCA8K_PORT_LOOKUP_CTRL(port),
1136                   QCA8K_PORT_LOOKUP_STATE_MASK, stp_state);
1137 }
1138
1139 static int
1140 qca8k_port_bridge_join(struct dsa_switch *ds, int port, struct net_device *br)
1141 {
1142         struct qca8k_priv *priv = (struct qca8k_priv *)ds->priv;
1143         int port_mask = BIT(QCA8K_CPU_PORT);
1144         int i;
1145
1146         for (i = 1; i < QCA8K_NUM_PORTS; i++) {
1147                 if (dsa_to_port(ds, i)->bridge_dev != br)
1148                         continue;
1149                 /* Add this port to the portvlan mask of the other ports
1150                  * in the bridge
1151                  */
1152                 qca8k_reg_set(priv,
1153                               QCA8K_PORT_LOOKUP_CTRL(i),
1154                               BIT(port));
1155                 if (i != port)
1156                         port_mask |= BIT(i);
1157         }
1158         /* Add all other ports to this ports portvlan mask */
1159         qca8k_rmw(priv, QCA8K_PORT_LOOKUP_CTRL(port),
1160                   QCA8K_PORT_LOOKUP_MEMBER, port_mask);
1161
1162         return 0;
1163 }
1164
1165 static void
1166 qca8k_port_bridge_leave(struct dsa_switch *ds, int port, struct net_device *br)
1167 {
1168         struct qca8k_priv *priv = (struct qca8k_priv *)ds->priv;
1169         int i;
1170
1171         for (i = 1; i < QCA8K_NUM_PORTS; i++) {
1172                 if (dsa_to_port(ds, i)->bridge_dev != br)
1173                         continue;
1174                 /* Remove this port to the portvlan mask of the other ports
1175                  * in the bridge
1176                  */
1177                 qca8k_reg_clear(priv,
1178                                 QCA8K_PORT_LOOKUP_CTRL(i),
1179                                 BIT(port));
1180         }
1181
1182         /* Set the cpu port to be the only one in the portvlan mask of
1183          * this port
1184          */
1185         qca8k_rmw(priv, QCA8K_PORT_LOOKUP_CTRL(port),
1186                   QCA8K_PORT_LOOKUP_MEMBER, BIT(QCA8K_CPU_PORT));
1187 }
1188
1189 static int
1190 qca8k_port_enable(struct dsa_switch *ds, int port,
1191                   struct phy_device *phy)
1192 {
1193         struct qca8k_priv *priv = (struct qca8k_priv *)ds->priv;
1194
1195         qca8k_port_set_status(priv, port, 1);
1196         priv->port_sts[port].enabled = 1;
1197
1198         if (dsa_is_user_port(ds, port))
1199                 phy_support_asym_pause(phy);
1200
1201         return 0;
1202 }
1203
1204 static void
1205 qca8k_port_disable(struct dsa_switch *ds, int port)
1206 {
1207         struct qca8k_priv *priv = (struct qca8k_priv *)ds->priv;
1208
1209         qca8k_port_set_status(priv, port, 0);
1210         priv->port_sts[port].enabled = 0;
1211 }
1212
1213 static int
1214 qca8k_port_change_mtu(struct dsa_switch *ds, int port, int new_mtu)
1215 {
1216         struct qca8k_priv *priv = ds->priv;
1217         int i, mtu = 0;
1218
1219         priv->port_mtu[port] = new_mtu;
1220
1221         for (i = 0; i < QCA8K_NUM_PORTS; i++)
1222                 if (priv->port_mtu[port] > mtu)
1223                         mtu = priv->port_mtu[port];
1224
1225         /* Include L2 header / FCS length */
1226         qca8k_write(priv, QCA8K_MAX_FRAME_SIZE, mtu + ETH_HLEN + ETH_FCS_LEN);
1227
1228         return 0;
1229 }
1230
1231 static int
1232 qca8k_port_max_mtu(struct dsa_switch *ds, int port)
1233 {
1234         return QCA8K_MAX_MTU;
1235 }
1236
1237 static int
1238 qca8k_port_fdb_insert(struct qca8k_priv *priv, const u8 *addr,
1239                       u16 port_mask, u16 vid)
1240 {
1241         /* Set the vid to the port vlan id if no vid is set */
1242         if (!vid)
1243                 vid = QCA8K_PORT_VID_DEF;
1244
1245         return qca8k_fdb_add(priv, addr, port_mask, vid,
1246                              QCA8K_ATU_STATUS_STATIC);
1247 }
1248
1249 static int
1250 qca8k_port_fdb_add(struct dsa_switch *ds, int port,
1251                    const unsigned char *addr, u16 vid)
1252 {
1253         struct qca8k_priv *priv = (struct qca8k_priv *)ds->priv;
1254         u16 port_mask = BIT(port);
1255
1256         return qca8k_port_fdb_insert(priv, addr, port_mask, vid);
1257 }
1258
1259 static int
1260 qca8k_port_fdb_del(struct dsa_switch *ds, int port,
1261                    const unsigned char *addr, u16 vid)
1262 {
1263         struct qca8k_priv *priv = (struct qca8k_priv *)ds->priv;
1264         u16 port_mask = BIT(port);
1265
1266         if (!vid)
1267                 vid = QCA8K_PORT_VID_DEF;
1268
1269         return qca8k_fdb_del(priv, addr, port_mask, vid);
1270 }
1271
1272 static int
1273 qca8k_port_fdb_dump(struct dsa_switch *ds, int port,
1274                     dsa_fdb_dump_cb_t *cb, void *data)
1275 {
1276         struct qca8k_priv *priv = (struct qca8k_priv *)ds->priv;
1277         struct qca8k_fdb _fdb = { 0 };
1278         int cnt = QCA8K_NUM_FDB_RECORDS;
1279         bool is_static;
1280         int ret = 0;
1281
1282         mutex_lock(&priv->reg_mutex);
1283         while (cnt-- && !qca8k_fdb_next(priv, &_fdb, port)) {
1284                 if (!_fdb.aging)
1285                         break;
1286                 is_static = (_fdb.aging == QCA8K_ATU_STATUS_STATIC);
1287                 ret = cb(_fdb.mac, _fdb.vid, is_static, data);
1288                 if (ret)
1289                         break;
1290         }
1291         mutex_unlock(&priv->reg_mutex);
1292
1293         return 0;
1294 }
1295
1296 static int
1297 qca8k_port_vlan_filtering(struct dsa_switch *ds, int port, bool vlan_filtering,
1298                           struct switchdev_trans *trans)
1299 {
1300         struct qca8k_priv *priv = ds->priv;
1301
1302         if (switchdev_trans_ph_prepare(trans))
1303                 return 0;
1304
1305         if (vlan_filtering) {
1306                 qca8k_rmw(priv, QCA8K_PORT_LOOKUP_CTRL(port),
1307                           QCA8K_PORT_LOOKUP_VLAN_MODE,
1308                           QCA8K_PORT_LOOKUP_VLAN_MODE_SECURE);
1309         } else {
1310                 qca8k_rmw(priv, QCA8K_PORT_LOOKUP_CTRL(port),
1311                           QCA8K_PORT_LOOKUP_VLAN_MODE,
1312                           QCA8K_PORT_LOOKUP_VLAN_MODE_NONE);
1313         }
1314
1315         return 0;
1316 }
1317
1318 static int
1319 qca8k_port_vlan_prepare(struct dsa_switch *ds, int port,
1320                         const struct switchdev_obj_port_vlan *vlan)
1321 {
1322         return 0;
1323 }
1324
1325 static void
1326 qca8k_port_vlan_add(struct dsa_switch *ds, int port,
1327                     const struct switchdev_obj_port_vlan *vlan)
1328 {
1329         bool untagged = vlan->flags & BRIDGE_VLAN_INFO_UNTAGGED;
1330         bool pvid = vlan->flags & BRIDGE_VLAN_INFO_PVID;
1331         struct qca8k_priv *priv = ds->priv;
1332         int ret = 0;
1333         u16 vid;
1334
1335         for (vid = vlan->vid_begin; vid <= vlan->vid_end && !ret; ++vid)
1336                 ret = qca8k_vlan_add(priv, port, vid, untagged);
1337
1338         if (ret)
1339                 dev_err(priv->dev, "Failed to add VLAN to port %d (%d)", port, ret);
1340
1341         if (pvid) {
1342                 int shift = 16 * (port % 2);
1343
1344                 qca8k_rmw(priv, QCA8K_EGRESS_VLAN(port),
1345                           0xfff << shift,
1346                           vlan->vid_end << shift);
1347                 qca8k_write(priv, QCA8K_REG_PORT_VLAN_CTRL0(port),
1348                             QCA8K_PORT_VLAN_CVID(vlan->vid_end) |
1349                             QCA8K_PORT_VLAN_SVID(vlan->vid_end));
1350         }
1351 }
1352
1353 static int
1354 qca8k_port_vlan_del(struct dsa_switch *ds, int port,
1355                     const struct switchdev_obj_port_vlan *vlan)
1356 {
1357         struct qca8k_priv *priv = ds->priv;
1358         int ret = 0;
1359         u16 vid;
1360
1361         for (vid = vlan->vid_begin; vid <= vlan->vid_end && !ret; ++vid)
1362                 ret = qca8k_vlan_del(priv, port, vid);
1363
1364         if (ret)
1365                 dev_err(priv->dev, "Failed to delete VLAN from port %d (%d)", port, ret);
1366
1367         return ret;
1368 }
1369
1370 static enum dsa_tag_protocol
1371 qca8k_get_tag_protocol(struct dsa_switch *ds, int port,
1372                        enum dsa_tag_protocol mp)
1373 {
1374         return DSA_TAG_PROTO_QCA;
1375 }
1376
1377 static const struct dsa_switch_ops qca8k_switch_ops = {
1378         .get_tag_protocol       = qca8k_get_tag_protocol,
1379         .setup                  = qca8k_setup,
1380         .get_strings            = qca8k_get_strings,
1381         .get_ethtool_stats      = qca8k_get_ethtool_stats,
1382         .get_sset_count         = qca8k_get_sset_count,
1383         .get_mac_eee            = qca8k_get_mac_eee,
1384         .set_mac_eee            = qca8k_set_mac_eee,
1385         .port_enable            = qca8k_port_enable,
1386         .port_disable           = qca8k_port_disable,
1387         .port_change_mtu        = qca8k_port_change_mtu,
1388         .port_max_mtu           = qca8k_port_max_mtu,
1389         .port_stp_state_set     = qca8k_port_stp_state_set,
1390         .port_bridge_join       = qca8k_port_bridge_join,
1391         .port_bridge_leave      = qca8k_port_bridge_leave,
1392         .port_fdb_add           = qca8k_port_fdb_add,
1393         .port_fdb_del           = qca8k_port_fdb_del,
1394         .port_fdb_dump          = qca8k_port_fdb_dump,
1395         .port_vlan_filtering    = qca8k_port_vlan_filtering,
1396         .port_vlan_prepare      = qca8k_port_vlan_prepare,
1397         .port_vlan_add          = qca8k_port_vlan_add,
1398         .port_vlan_del          = qca8k_port_vlan_del,
1399         .phylink_validate       = qca8k_phylink_validate,
1400         .phylink_mac_link_state = qca8k_phylink_mac_link_state,
1401         .phylink_mac_config     = qca8k_phylink_mac_config,
1402         .phylink_mac_link_down  = qca8k_phylink_mac_link_down,
1403         .phylink_mac_link_up    = qca8k_phylink_mac_link_up,
1404 };
1405
1406 static int
1407 qca8k_sw_probe(struct mdio_device *mdiodev)
1408 {
1409         struct qca8k_priv *priv;
1410         u32 id;
1411
1412         /* allocate the private data struct so that we can probe the switches
1413          * ID register
1414          */
1415         priv = devm_kzalloc(&mdiodev->dev, sizeof(*priv), GFP_KERNEL);
1416         if (!priv)
1417                 return -ENOMEM;
1418
1419         priv->bus = mdiodev->bus;
1420         priv->dev = &mdiodev->dev;
1421
1422         priv->reset_gpio = devm_gpiod_get_optional(priv->dev, "reset",
1423                                                    GPIOD_ASIS);
1424         if (IS_ERR(priv->reset_gpio))
1425                 return PTR_ERR(priv->reset_gpio);
1426
1427         if (priv->reset_gpio) {
1428                 gpiod_set_value_cansleep(priv->reset_gpio, 1);
1429                 /* The active low duration must be greater than 10 ms
1430                  * and checkpatch.pl wants 20 ms.
1431                  */
1432                 msleep(20);
1433                 gpiod_set_value_cansleep(priv->reset_gpio, 0);
1434         }
1435
1436         /* read the switches ID register */
1437         id = qca8k_read(priv, QCA8K_REG_MASK_CTRL);
1438         id >>= QCA8K_MASK_CTRL_ID_S;
1439         id &= QCA8K_MASK_CTRL_ID_M;
1440         if (id != QCA8K_ID_QCA8337)
1441                 return -ENODEV;
1442
1443         priv->ds = devm_kzalloc(&mdiodev->dev, sizeof(*priv->ds), GFP_KERNEL);
1444         if (!priv->ds)
1445                 return -ENOMEM;
1446
1447         priv->ds->dev = &mdiodev->dev;
1448         priv->ds->num_ports = QCA8K_NUM_PORTS;
1449         priv->ds->configure_vlan_while_not_filtering = true;
1450         priv->ds->priv = priv;
1451         priv->ops = qca8k_switch_ops;
1452         priv->ds->ops = &priv->ops;
1453         mutex_init(&priv->reg_mutex);
1454         dev_set_drvdata(&mdiodev->dev, priv);
1455
1456         return dsa_register_switch(priv->ds);
1457 }
1458
1459 static void
1460 qca8k_sw_remove(struct mdio_device *mdiodev)
1461 {
1462         struct qca8k_priv *priv = dev_get_drvdata(&mdiodev->dev);
1463         int i;
1464
1465         for (i = 0; i < QCA8K_NUM_PORTS; i++)
1466                 qca8k_port_set_status(priv, i, 0);
1467
1468         dsa_unregister_switch(priv->ds);
1469 }
1470
1471 #ifdef CONFIG_PM_SLEEP
1472 static void
1473 qca8k_set_pm(struct qca8k_priv *priv, int enable)
1474 {
1475         int i;
1476
1477         for (i = 0; i < QCA8K_NUM_PORTS; i++) {
1478                 if (!priv->port_sts[i].enabled)
1479                         continue;
1480
1481                 qca8k_port_set_status(priv, i, enable);
1482         }
1483 }
1484
1485 static int qca8k_suspend(struct device *dev)
1486 {
1487         struct qca8k_priv *priv = dev_get_drvdata(dev);
1488
1489         qca8k_set_pm(priv, 0);
1490
1491         return dsa_switch_suspend(priv->ds);
1492 }
1493
1494 static int qca8k_resume(struct device *dev)
1495 {
1496         struct qca8k_priv *priv = dev_get_drvdata(dev);
1497
1498         qca8k_set_pm(priv, 1);
1499
1500         return dsa_switch_resume(priv->ds);
1501 }
1502 #endif /* CONFIG_PM_SLEEP */
1503
1504 static SIMPLE_DEV_PM_OPS(qca8k_pm_ops,
1505                          qca8k_suspend, qca8k_resume);
1506
1507 static const struct of_device_id qca8k_of_match[] = {
1508         { .compatible = "qca,qca8334" },
1509         { .compatible = "qca,qca8337" },
1510         { /* sentinel */ },
1511 };
1512
1513 static struct mdio_driver qca8kmdio_driver = {
1514         .probe  = qca8k_sw_probe,
1515         .remove = qca8k_sw_remove,
1516         .mdiodrv.driver = {
1517                 .name = "qca8k",
1518                 .of_match_table = qca8k_of_match,
1519                 .pm = &qca8k_pm_ops,
1520         },
1521 };
1522
1523 mdio_module_driver(qca8kmdio_driver);
1524
1525 MODULE_AUTHOR("Mathieu Olivari, John Crispin <john@phrozen.org>");
1526 MODULE_DESCRIPTION("Driver for QCA8K ethernet switch family");
1527 MODULE_LICENSE("GPL v2");
1528 MODULE_ALIAS("platform:qca8k");