drivers/net/dsa/qca8k.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * Copyright (C) 2009 Felix Fietkau <nbd@nbd.name>
   4  * Copyright (C) 2011-2012 Gabor Juhos <juhosg@openwrt.org>
   5  * Copyright (c) 2015, 2019, The Linux Foundation. All rights reserved.
   6  * Copyright (c) 2016 John Crispin <john@phrozen.org>
   7  */
   8
   9 #include <linux/module.h>
  10 #include <linux/phy.h>
  11 #include <linux/netdevice.h>
  12 #include <net/dsa.h>
  13 #include <linux/of_net.h>
  14 #include <linux/of_mdio.h>
  15 #include <linux/of_platform.h>
  16 #include <linux/if_bridge.h>
  17 #include <linux/mdio.h>
  18 #include <linux/phylink.h>
  19 #include <linux/gpio/consumer.h>
  20 #include <linux/etherdevice.h>
  21
  22 #include "qca8k.h"
  23
  24 #define MIB_DESC(_s, _o, _n)    \
  25         {                       \
  26                 .size = (_s),   \
  27                 .offset = (_o), \
  28                 .name = (_n),   \
  29         }
  30
  31 static const struct qca8k_mib_desc ar8327_mib[] = {
  32         MIB_DESC(1, 0x00, "RxBroad"),
  33         MIB_DESC(1, 0x04, "RxPause"),
  34         MIB_DESC(1, 0x08, "RxMulti"),
  35         MIB_DESC(1, 0x0c, "RxFcsErr"),
  36         MIB_DESC(1, 0x10, "RxAlignErr"),
  37         MIB_DESC(1, 0x14, "RxRunt"),
  38         MIB_DESC(1, 0x18, "RxFragment"),
  39         MIB_DESC(1, 0x1c, "Rx64Byte"),
  40         MIB_DESC(1, 0x20, "Rx128Byte"),
  41         MIB_DESC(1, 0x24, "Rx256Byte"),
  42         MIB_DESC(1, 0x28, "Rx512Byte"),
  43         MIB_DESC(1, 0x2c, "Rx1024Byte"),
  44         MIB_DESC(1, 0x30, "Rx1518Byte"),
  45         MIB_DESC(1, 0x34, "RxMaxByte"),
  46         MIB_DESC(1, 0x38, "RxTooLong"),
  47         MIB_DESC(2, 0x3c, "RxGoodByte"),
  48         MIB_DESC(2, 0x44, "RxBadByte"),
  49         MIB_DESC(1, 0x4c, "RxOverFlow"),
  50         MIB_DESC(1, 0x50, "Filtered"),
  51         MIB_DESC(1, 0x54, "TxBroad"),
  52         MIB_DESC(1, 0x58, "TxPause"),
  53         MIB_DESC(1, 0x5c, "TxMulti"),
  54         MIB_DESC(1, 0x60, "TxUnderRun"),
  55         MIB_DESC(1, 0x64, "Tx64Byte"),
  56         MIB_DESC(1, 0x68, "Tx128Byte"),
  57         MIB_DESC(1, 0x6c, "Tx256Byte"),
  58         MIB_DESC(1, 0x70, "Tx512Byte"),
  59         MIB_DESC(1, 0x74, "Tx1024Byte"),
  60         MIB_DESC(1, 0x78, "Tx1518Byte"),
  61         MIB_DESC(1, 0x7c, "TxMaxByte"),
  62         MIB_DESC(1, 0x80, "TxOverSize"),
  63         MIB_DESC(2, 0x84, "TxByte"),
  64         MIB_DESC(1, 0x8c, "TxCollision"),
  65         MIB_DESC(1, 0x90, "TxAbortCol"),
  66         MIB_DESC(1, 0x94, "TxMultiCol"),
  67         MIB_DESC(1, 0x98, "TxSingleCol"),
  68         MIB_DESC(1, 0x9c, "TxExcDefer"),
  69         MIB_DESC(1, 0xa0, "TxDefer"),
  70         MIB_DESC(1, 0xa4, "TxLateCol"),
  71 };
  72
  73 /* The 32bit switch registers are accessed indirectly. To achieve this we need
  74  * to set the page of the register. Track the last page that was set to reduce
  75  * mdio writes
  76  */
  77 static u16 qca8k_current_page = 0xffff;
  78
  79 static void
  80 qca8k_split_addr(u32 regaddr, u16 *r1, u16 *r2, u16 *page)
  81 {
  82         regaddr >>= 1;
  83         *r1 = regaddr & 0x1e;
  84
  85         regaddr >>= 5;
  86         *r2 = regaddr & 0x7;
  87
  88         regaddr >>= 3;
  89         *page = regaddr & 0x3ff;
  90 }
  91
  92 static int
  93 qca8k_mii_read32(struct mii_bus *bus, int phy_id, u32 regnum, u32 *val)
  94 {
  95         int ret;
  96
  97         ret = bus->read(bus, phy_id, regnum);
  98         if (ret >= 0) {
  99                 *val = ret;
 100                 ret = bus->read(bus, phy_id, regnum + 1);
 101                 *val |= ret << 16;
 102         }
 103
 104         if (ret < 0) {
 105                 dev_err_ratelimited(&bus->dev,
 106                                     "failed to read qca8k 32bit register\n");
 107                 *val = 0;
 108                 return ret;
 109         }
 110
 111         return 0;
 112 }
 113
 114 static void
 115 qca8k_mii_write32(struct mii_bus *bus, int phy_id, u32 regnum, u32 val)
 116 {
 117         u16 lo, hi;
 118         int ret;
 119
 120         lo = val & 0xffff;
 121         hi = (u16)(val >> 16);
 122
 123         ret = bus->write(bus, phy_id, regnum, lo);
 124         if (ret >= 0)
 125                 ret = bus->write(bus, phy_id, regnum + 1, hi);
 126         if (ret < 0)
 127                 dev_err_ratelimited(&bus->dev,
 128                                     "failed to write qca8k 32bit register\n");
 129 }
 130
 131 static int
 132 qca8k_set_page(struct mii_bus *bus, u16 page)
 133 {
 134         int ret;
 135
 136         if (page == qca8k_current_page)
 137                 return 0;
 138
 139         ret = bus->write(bus, 0x18, 0, page);
 140         if (ret < 0) {
 141                 dev_err_ratelimited(&bus->dev,
 142                                     "failed to set qca8k page\n");
 143                 return ret;
 144         }
 145
 146         qca8k_current_page = page;
 147         usleep_range(1000, 2000);
 148         return 0;
 149 }
 150
 151 static int
 152 qca8k_read(struct qca8k_priv *priv, u32 reg, u32 *val)
 153 {
 154         struct mii_bus *bus = priv->bus;
 155         u16 r1, r2, page;
 156         int ret;
 157
 158         qca8k_split_addr(reg, &r1, &r2, &page);
 159
 160         mutex_lock_nested(&bus->mdio_lock, MDIO_MUTEX_NESTED);
 161
 162         ret = qca8k_set_page(bus, page);
 163         if (ret < 0)
 164                 goto exit;
 165
 166         ret = qca8k_mii_read32(bus, 0x10 | r2, r1, val);
 167
 168 exit:
 169         mutex_unlock(&bus->mdio_lock);
 170         return ret;
 171 }
 172
 173 static int
 174 qca8k_write(struct qca8k_priv *priv, u32 reg, u32 val)
 175 {
 176         struct mii_bus *bus = priv->bus;
 177         u16 r1, r2, page;
 178         int ret;
 179
 180         qca8k_split_addr(reg, &r1, &r2, &page);
 181
 182         mutex_lock_nested(&bus->mdio_lock, MDIO_MUTEX_NESTED);
 183
 184         ret = qca8k_set_page(bus, page);
 185         if (ret < 0)
 186                 goto exit;
 187
 188         qca8k_mii_write32(bus, 0x10 | r2, r1, val);
 189
 190 exit:
 191         mutex_unlock(&bus->mdio_lock);
 192         return ret;
 193 }
 194
 195 static int
 196 qca8k_rmw(struct qca8k_priv *priv, u32 reg, u32 mask, u32 write_val)
 197 {
 198         struct mii_bus *bus = priv->bus;
 199         u16 r1, r2, page;
 200         u32 val;
 201         int ret;
 202
 203         qca8k_split_addr(reg, &r1, &r2, &page);
 204
 205         mutex_lock_nested(&bus->mdio_lock, MDIO_MUTEX_NESTED);
 206
 207         ret = qca8k_set_page(bus, page);
 208         if (ret < 0)
 209                 goto exit;
 210
 211         ret = qca8k_mii_read32(bus, 0x10 | r2, r1, &val);
 212         if (ret < 0)
 213                 goto exit;
 214
 215         val &= ~mask;
 216         val |= write_val;
 217         qca8k_mii_write32(bus, 0x10 | r2, r1, val);
 218
 219 exit:
 220         mutex_unlock(&bus->mdio_lock);
 221
 222         return ret;
 223 }
 224
 225 static int
 226 qca8k_reg_set(struct qca8k_priv *priv, u32 reg, u32 val)
 227 {
 228         return qca8k_rmw(priv, reg, 0, val);
 229 }
 230
 231 static int
 232 qca8k_reg_clear(struct qca8k_priv *priv, u32 reg, u32 val)
 233 {
 234         return qca8k_rmw(priv, reg, val, 0);
 235 }
 236
 237 static int
 238 qca8k_regmap_read(void *ctx, uint32_t reg, uint32_t *val)
 239 {
 240         struct qca8k_priv *priv = (struct qca8k_priv *)ctx;
 241
 242         return qca8k_read(priv, reg, val);
 243 }
 244
 245 static int
 246 qca8k_regmap_write(void *ctx, uint32_t reg, uint32_t val)
 247 {
 248         struct qca8k_priv *priv = (struct qca8k_priv *)ctx;
 249
 250         return qca8k_write(priv, reg, val);
 251 }
 252
 253 static const struct regmap_range qca8k_readable_ranges[] = {
 254         regmap_reg_range(0x0000, 0x00e4), /* Global control */
 255         regmap_reg_range(0x0100, 0x0168), /* EEE control */
 256         regmap_reg_range(0x0200, 0x0270), /* Parser control */
 257         regmap_reg_range(0x0400, 0x0454), /* ACL */
 258         regmap_reg_range(0x0600, 0x0718), /* Lookup */
 259         regmap_reg_range(0x0800, 0x0b70), /* QM */
 260         regmap_reg_range(0x0c00, 0x0c80), /* PKT */
 261         regmap_reg_range(0x0e00, 0x0e98), /* L3 */
 262         regmap_reg_range(0x1000, 0x10ac), /* MIB - Port0 */
 263         regmap_reg_range(0x1100, 0x11ac), /* MIB - Port1 */
 264         regmap_reg_range(0x1200, 0x12ac), /* MIB - Port2 */
 265         regmap_reg_range(0x1300, 0x13ac), /* MIB - Port3 */
 266         regmap_reg_range(0x1400, 0x14ac), /* MIB - Port4 */
 267         regmap_reg_range(0x1500, 0x15ac), /* MIB - Port5 */
 268         regmap_reg_range(0x1600, 0x16ac), /* MIB - Port6 */
 269
 270 };
 271
 272 static const struct regmap_access_table qca8k_readable_table = {
 273         .yes_ranges = qca8k_readable_ranges,
 274         .n_yes_ranges = ARRAY_SIZE(qca8k_readable_ranges),
 275 };
 276
 277 static struct regmap_config qca8k_regmap_config = {
 278         .reg_bits = 16,
 279         .val_bits = 32,
 280         .reg_stride = 4,
 281         .max_register = 0x16ac, /* end MIB - Port6 range */
 282         .reg_read = qca8k_regmap_read,
 283         .reg_write = qca8k_regmap_write,
 284         .rd_table = &qca8k_readable_table,
 285 };
 286
 287 static int
 288 qca8k_busy_wait(struct qca8k_priv *priv, u32 reg, u32 mask)
 289 {
 290         int ret, ret1;
 291         u32 val;
 292
 293         ret = read_poll_timeout(qca8k_read, ret1, !(val & mask),
 294                                 0, QCA8K_BUSY_WAIT_TIMEOUT * USEC_PER_MSEC, false,
 295                                 priv, reg, &val);
 296
 297         /* Check if qca8k_read has failed for a different reason
 298          * before returning -ETIMEDOUT
 299          */
 300         if (ret < 0 && ret1 < 0)
 301                 return ret1;
 302
 303         return ret;
 304 }
 305
 306 static int
 307 qca8k_fdb_read(struct qca8k_priv *priv, struct qca8k_fdb *fdb)
 308 {
 309         u32 reg[4], val;
 310         int i, ret;
 311
 312         /* load the ARL table into an array */
 313         for (i = 0; i < 4; i++) {
 314                 ret = qca8k_read(priv, QCA8K_REG_ATU_DATA0 + (i * 4), &val);
 315                 if (ret < 0)
 316                         return ret;
 317
 318                 reg[i] = val;
 319         }
 320
 321         /* vid - 83:72 */
 322         fdb->vid = (reg[2] >> QCA8K_ATU_VID_S) & QCA8K_ATU_VID_M;
 323         /* aging - 67:64 */
 324         fdb->aging = reg[2] & QCA8K_ATU_STATUS_M;
 325         /* portmask - 54:48 */
 326         fdb->port_mask = (reg[1] >> QCA8K_ATU_PORT_S) & QCA8K_ATU_PORT_M;
 327         /* mac - 47:0 */
 328         fdb->mac[0] = (reg[1] >> QCA8K_ATU_ADDR0_S) & 0xff;
 329         fdb->mac[1] = reg[1] & 0xff;
 330         fdb->mac[2] = (reg[0] >> QCA8K_ATU_ADDR2_S) & 0xff;
 331         fdb->mac[3] = (reg[0] >> QCA8K_ATU_ADDR3_S) & 0xff;
 332         fdb->mac[4] = (reg[0] >> QCA8K_ATU_ADDR4_S) & 0xff;
 333         fdb->mac[5] = reg[0] & 0xff;
 334
 335         return 0;
 336 }
 337
 338 static void
 339 qca8k_fdb_write(struct qca8k_priv *priv, u16 vid, u8 port_mask, const u8 *mac,
 340                 u8 aging)
 341 {
 342         u32 reg[3] = { 0 };
 343         int i;
 344
 345         /* vid - 83:72 */
 346         reg[2] = (vid & QCA8K_ATU_VID_M) << QCA8K_ATU_VID_S;
 347         /* aging - 67:64 */
 348         reg[2] |= aging & QCA8K_ATU_STATUS_M;
 349         /* portmask - 54:48 */
 350         reg[1] = (port_mask & QCA8K_ATU_PORT_M) << QCA8K_ATU_PORT_S;
 351         /* mac - 47:0 */
 352         reg[1] |= mac[0] << QCA8K_ATU_ADDR0_S;
 353         reg[1] |= mac[1];
 354         reg[0] |= mac[2] << QCA8K_ATU_ADDR2_S;
 355         reg[0] |= mac[3] << QCA8K_ATU_ADDR3_S;
 356         reg[0] |= mac[4] << QCA8K_ATU_ADDR4_S;
 357         reg[0] |= mac[5];
 358
 359         /* load the array into the ARL table */
 360         for (i = 0; i < 3; i++)
 361                 qca8k_write(priv, QCA8K_REG_ATU_DATA0 + (i * 4), reg[i]);
 362 }
 363
 364 static int
 365 qca8k_fdb_access(struct qca8k_priv *priv, enum qca8k_fdb_cmd cmd, int port)
 366 {
 367         u32 reg;
 368         int ret;
 369
 370         /* Set the command and FDB index */
 371         reg = QCA8K_ATU_FUNC_BUSY;
 372         reg |= cmd;
 373         if (port >= 0) {
 374                 reg |= QCA8K_ATU_FUNC_PORT_EN;
 375                 reg |= (port & QCA8K_ATU_FUNC_PORT_M) << QCA8K_ATU_FUNC_PORT_S;
 376         }
 377
 378         /* Write the function register triggering the table access */
 379         ret = qca8k_write(priv, QCA8K_REG_ATU_FUNC, reg);
 380         if (ret)
 381                 return ret;
 382
 383         /* wait for completion */
 384         ret = qca8k_busy_wait(priv, QCA8K_REG_ATU_FUNC, QCA8K_ATU_FUNC_BUSY);
 385         if (ret)
 386                 return ret;
 387
 388         /* Check for table full violation when adding an entry */
 389         if (cmd == QCA8K_FDB_LOAD) {
 390                 ret = qca8k_read(priv, QCA8K_REG_ATU_FUNC, &reg);
 391                 if (ret < 0)
 392                         return ret;
 393                 if (reg & QCA8K_ATU_FUNC_FULL)
 394                         return -1;
 395         }
 396
 397         return 0;
 398 }
 399
 400 static int
 401 qca8k_fdb_next(struct qca8k_priv *priv, struct qca8k_fdb *fdb, int port)
 402 {
 403         int ret;
 404
 405         qca8k_fdb_write(priv, fdb->vid, fdb->port_mask, fdb->mac, fdb->aging);
 406         ret = qca8k_fdb_access(priv, QCA8K_FDB_NEXT, port);
 407         if (ret < 0)
 408                 return ret;
 409
 410         return qca8k_fdb_read(priv, fdb);
 411 }
 412
 413 static int
 414 qca8k_fdb_add(struct qca8k_priv *priv, const u8 *mac, u16 port_mask,
 415               u16 vid, u8 aging)
 416 {
 417         int ret;
 418
 419         mutex_lock(&priv->reg_mutex);
 420         qca8k_fdb_write(priv, vid, port_mask, mac, aging);
 421         ret = qca8k_fdb_access(priv, QCA8K_FDB_LOAD, -1);
 422         mutex_unlock(&priv->reg_mutex);
 423
 424         return ret;
 425 }
 426
 427 static int
 428 qca8k_fdb_del(struct qca8k_priv *priv, const u8 *mac, u16 port_mask, u16 vid)
 429 {
 430         int ret;
 431
 432         mutex_lock(&priv->reg_mutex);
 433         qca8k_fdb_write(priv, vid, port_mask, mac, 0);
 434         ret = qca8k_fdb_access(priv, QCA8K_FDB_PURGE, -1);
 435         mutex_unlock(&priv->reg_mutex);
 436
 437         return ret;
 438 }
 439
 440 static void
 441 qca8k_fdb_flush(struct qca8k_priv *priv)
 442 {
 443         mutex_lock(&priv->reg_mutex);
 444         qca8k_fdb_access(priv, QCA8K_FDB_FLUSH, -1);
 445         mutex_unlock(&priv->reg_mutex);
 446 }
 447
 448 static int
 449 qca8k_vlan_access(struct qca8k_priv *priv, enum qca8k_vlan_cmd cmd, u16 vid)
 450 {
 451         u32 reg;
 452         int ret;
 453
 454         /* Set the command and VLAN index */
 455         reg = QCA8K_VTU_FUNC1_BUSY;
 456         reg |= cmd;
 457         reg |= vid << QCA8K_VTU_FUNC1_VID_S;
 458
 459         /* Write the function register triggering the table access */
 460         ret = qca8k_write(priv, QCA8K_REG_VTU_FUNC1, reg);
 461         if (ret)
 462                 return ret;
 463
 464         /* wait for completion */
 465         ret = qca8k_busy_wait(priv, QCA8K_REG_VTU_FUNC1, QCA8K_VTU_FUNC1_BUSY);
 466         if (ret)
 467                 return ret;
 468
 469         /* Check for table full violation when adding an entry */
 470         if (cmd == QCA8K_VLAN_LOAD) {
 471                 ret = qca8k_read(priv, QCA8K_REG_VTU_FUNC1, &reg);
 472                 if (ret < 0)
 473                         return ret;
 474                 if (reg & QCA8K_VTU_FUNC1_FULL)
 475                         return -ENOMEM;
 476         }
 477
 478         return 0;
 479 }
 480
 481 static int
 482 qca8k_vlan_add(struct qca8k_priv *priv, u8 port, u16 vid, bool untagged)
 483 {
 484         u32 reg;
 485         int ret;
 486
 487         /*
 488            We do the right thing with VLAN 0 and treat it as untagged while
 489            preserving the tag on egress.
 490          */
 491         if (vid == 0)
 492                 return 0;
 493
 494         mutex_lock(&priv->reg_mutex);
 495         ret = qca8k_vlan_access(priv, QCA8K_VLAN_READ, vid);
 496         if (ret < 0)
 497                 goto out;
 498
 499         ret = qca8k_read(priv, QCA8K_REG_VTU_FUNC0, &reg);
 500         if (ret < 0)
 501                 goto out;
 502         reg |= QCA8K_VTU_FUNC0_VALID | QCA8K_VTU_FUNC0_IVL_EN;
 503         reg &= ~(QCA8K_VTU_FUNC0_EG_MODE_MASK << QCA8K_VTU_FUNC0_EG_MODE_S(port));
 504         if (untagged)
 505                 reg |= QCA8K_VTU_FUNC0_EG_MODE_UNTAG <<
 506                                 QCA8K_VTU_FUNC0_EG_MODE_S(port);
 507         else
 508                 reg |= QCA8K_VTU_FUNC0_EG_MODE_TAG <<
 509                                 QCA8K_VTU_FUNC0_EG_MODE_S(port);
 510
 511         ret = qca8k_write(priv, QCA8K_REG_VTU_FUNC0, reg);
 512         if (ret)
 513                 goto out;
 514         ret = qca8k_vlan_access(priv, QCA8K_VLAN_LOAD, vid);
 515
 516 out:
 517         mutex_unlock(&priv->reg_mutex);
 518
 519         return ret;
 520 }
 521
 522 static int
 523 qca8k_vlan_del(struct qca8k_priv *priv, u8 port, u16 vid)
 524 {
 525         u32 reg, mask;
 526         int ret, i;
 527         bool del;
 528
 529         mutex_lock(&priv->reg_mutex);
 530         ret = qca8k_vlan_access(priv, QCA8K_VLAN_READ, vid);
 531         if (ret < 0)
 532                 goto out;
 533
 534         ret = qca8k_read(priv, QCA8K_REG_VTU_FUNC0, &reg);
 535         if (ret < 0)
 536                 goto out;
 537         reg &= ~(3 << QCA8K_VTU_FUNC0_EG_MODE_S(port));
 538         reg |= QCA8K_VTU_FUNC0_EG_MODE_NOT <<
 539                         QCA8K_VTU_FUNC0_EG_MODE_S(port);
 540
 541         /* Check if we're the last member to be removed */
 542         del = true;
 543         for (i = 0; i < QCA8K_NUM_PORTS; i++) {
 544                 mask = QCA8K_VTU_FUNC0_EG_MODE_NOT;
 545                 mask <<= QCA8K_VTU_FUNC0_EG_MODE_S(i);
 546
 547                 if ((reg & mask) != mask) {
 548                         del = false;
 549                         break;
 550                 }
 551         }
 552
 553         if (del) {
 554                 ret = qca8k_vlan_access(priv, QCA8K_VLAN_PURGE, vid);
 555         } else {
 556                 ret = qca8k_write(priv, QCA8K_REG_VTU_FUNC0, reg);
 557                 if (ret)
 558                         goto out;
 559                 ret = qca8k_vlan_access(priv, QCA8K_VLAN_LOAD, vid);
 560         }
 561
 562 out:
 563         mutex_unlock(&priv->reg_mutex);
 564
 565         return ret;
 566 }
 567
 568 static int
 569 qca8k_mib_init(struct qca8k_priv *priv)
 570 {
 571         int ret;
 572
 573         mutex_lock(&priv->reg_mutex);
 574         ret = qca8k_reg_set(priv, QCA8K_REG_MIB, QCA8K_MIB_FLUSH | QCA8K_MIB_BUSY);
 575         if (ret)
 576                 goto exit;
 577
 578         ret = qca8k_busy_wait(priv, QCA8K_REG_MIB, QCA8K_MIB_BUSY);
 579         if (ret)
 580                 goto exit;
 581
 582         ret = qca8k_reg_set(priv, QCA8K_REG_MIB, QCA8K_MIB_CPU_KEEP);
 583         if (ret)
 584                 goto exit;
 585
 586         ret = qca8k_write(priv, QCA8K_REG_MODULE_EN, QCA8K_MODULE_EN_MIB);
 587
 588 exit:
 589         mutex_unlock(&priv->reg_mutex);
 590         return ret;
 591 }
 592
 593 static void
 594 qca8k_port_set_status(struct qca8k_priv *priv, int port, int enable)
 595 {
 596         u32 mask = QCA8K_PORT_STATUS_TXMAC | QCA8K_PORT_STATUS_RXMAC;
 597
 598         /* Port 0 and 6 have no internal PHY */
 599         if (port > 0 && port < 6)
 600                 mask |= QCA8K_PORT_STATUS_LINK_AUTO;
 601
 602         if (enable)
 603                 qca8k_reg_set(priv, QCA8K_REG_PORT_STATUS(port), mask);
 604         else
 605                 qca8k_reg_clear(priv, QCA8K_REG_PORT_STATUS(port), mask);
 606 }
 607
 608 static u32
 609 qca8k_port_to_phy(int port)
 610 {
 611         /* From Andrew Lunn:
 612          * Port 0 has no internal phy.
 613          * Port 1 has an internal PHY at MDIO address 0.
 614          * Port 2 has an internal PHY at MDIO address 1.
 615          * ...
 616          * Port 5 has an internal PHY at MDIO address 4.
 617          * Port 6 has no internal PHY.
 618          */
 619
 620         return port - 1;
 621 }
 622
 623 static int
 624 qca8k_mdio_busy_wait(struct mii_bus *bus, u32 reg, u32 mask)
 625 {
 626         u16 r1, r2, page;
 627         u32 val;
 628         int ret, ret1;
 629
 630         qca8k_split_addr(reg, &r1, &r2, &page);
 631
 632         ret = read_poll_timeout(qca8k_mii_read32, ret1, !(val & mask), 0,
 633                                 QCA8K_BUSY_WAIT_TIMEOUT * USEC_PER_MSEC, false,
 634                                 bus, 0x10 | r2, r1, &val);
 635
 636         /* Check if qca8k_read has failed for a different reason
 637          * before returnting -ETIMEDOUT
 638          */
 639         if (ret < 0 && ret1 < 0)
 640                 return ret1;
 641
 642         return ret;
 643 }
 644
 645 static int
 646 qca8k_mdio_write(struct mii_bus *salve_bus, int phy, int regnum, u16 data)
 647 {
 648         struct qca8k_priv *priv = salve_bus->priv;
 649         struct mii_bus *bus = priv->bus;
 650         u16 r1, r2, page;
 651         u32 val;
 652         int ret;
 653
 654         if (regnum >= QCA8K_MDIO_MASTER_MAX_REG)
 655                 return -EINVAL;
 656
 657         val = QCA8K_MDIO_MASTER_BUSY | QCA8K_MDIO_MASTER_EN |
 658               QCA8K_MDIO_MASTER_WRITE | QCA8K_MDIO_MASTER_PHY_ADDR(phy) |
 659               QCA8K_MDIO_MASTER_REG_ADDR(regnum) |
 660               QCA8K_MDIO_MASTER_DATA(data);
 661
 662         qca8k_split_addr(QCA8K_MDIO_MASTER_CTRL, &r1, &r2, &page);
 663
 664         mutex_lock_nested(&bus->mdio_lock, MDIO_MUTEX_NESTED);
 665
 666         ret = qca8k_set_page(bus, page);
 667         if (ret)
 668                 goto exit;
 669
 670         qca8k_mii_write32(bus, 0x10 | r2, r1, val);
 671
 672         ret = qca8k_mdio_busy_wait(bus, QCA8K_MDIO_MASTER_CTRL,
 673                                    QCA8K_MDIO_MASTER_BUSY);
 674
 675 exit:
 676         /* even if the busy_wait timeouts try to clear the MASTER_EN */
 677         qca8k_mii_write32(bus, 0x10 | r2, r1, 0);
 678
 679         mutex_unlock(&bus->mdio_lock);
 680
 681         return ret;
 682 }
 683
 684 static int
 685 qca8k_mdio_read(struct mii_bus *salve_bus, int phy, int regnum)
 686 {
 687         struct qca8k_priv *priv = salve_bus->priv;
 688         struct mii_bus *bus = priv->bus;
 689         u16 r1, r2, page;
 690         u32 val;
 691         int ret;
 692
 693         if (regnum >= QCA8K_MDIO_MASTER_MAX_REG)
 694                 return -EINVAL;
 695
 696         val = QCA8K_MDIO_MASTER_BUSY | QCA8K_MDIO_MASTER_EN |
 697               QCA8K_MDIO_MASTER_READ | QCA8K_MDIO_MASTER_PHY_ADDR(phy) |
 698               QCA8K_MDIO_MASTER_REG_ADDR(regnum);
 699
 700         qca8k_split_addr(QCA8K_MDIO_MASTER_CTRL, &r1, &r2, &page);
 701
 702         mutex_lock_nested(&bus->mdio_lock, MDIO_MUTEX_NESTED);
 703
 704         ret = qca8k_set_page(bus, page);
 705         if (ret)
 706                 goto exit;
 707
 708         qca8k_mii_write32(bus, 0x10 | r2, r1, val);
 709
 710         ret = qca8k_mdio_busy_wait(bus, QCA8K_MDIO_MASTER_CTRL,
 711                                    QCA8K_MDIO_MASTER_BUSY);
 712         if (ret)
 713                 goto exit;
 714
 715         ret = qca8k_mii_read32(bus, 0x10 | r2, r1, &val);
 716
 717 exit:
 718         /* even if the busy_wait timeouts try to clear the MASTER_EN */
 719         qca8k_mii_write32(bus, 0x10 | r2, r1, 0);
 720
 721         mutex_unlock(&bus->mdio_lock);
 722
 723         if (ret >= 0)
 724                 ret = val & QCA8K_MDIO_MASTER_DATA_MASK;
 725
 726         return ret;
 727 }
 728
 729 static int
 730 qca8k_phy_write(struct dsa_switch *ds, int port, int regnum, u16 data)
 731 {
 732         struct qca8k_priv *priv = ds->priv;
 733
 734         /* Check if the legacy mapping should be used and the
 735          * port is not correctly mapped to the right PHY in the
 736          * devicetree
 737          */
 738         if (priv->legacy_phy_port_mapping)
 739                 port = qca8k_port_to_phy(port) % PHY_MAX_ADDR;
 740
 741         return qca8k_mdio_write(priv->bus, port, regnum, data);
 742 }
 743
 744 static int
 745 qca8k_phy_read(struct dsa_switch *ds, int port, int regnum)
 746 {
 747         struct qca8k_priv *priv = ds->priv;
 748         int ret;
 749
 750         /* Check if the legacy mapping should be used and the
 751          * port is not correctly mapped to the right PHY in the
 752          * devicetree
 753          */
 754         if (priv->legacy_phy_port_mapping)
 755                 port = qca8k_port_to_phy(port) % PHY_MAX_ADDR;
 756
 757         ret = qca8k_mdio_read(priv->bus, port, regnum);
 758
 759         if (ret < 0)
 760                 return 0xffff;
 761
 762         return ret;
 763 }
 764
 765 static int
 766 qca8k_mdio_register(struct qca8k_priv *priv, struct device_node *mdio)
 767 {
 768         struct dsa_switch *ds = priv->ds;
 769         struct mii_bus *bus;
 770
 771         bus = devm_mdiobus_alloc(ds->dev);
 772
 773         if (!bus)
 774                 return -ENOMEM;
 775
 776         bus->priv = (void *)priv;
 777         bus->name = "qca8k slave mii";
 778         bus->read = qca8k_mdio_read;
 779         bus->write = qca8k_mdio_write;
 780         snprintf(bus->id, MII_BUS_ID_SIZE, "qca8k-%d",
 781                  ds->index);
 782
 783         bus->parent = ds->dev;
 784         bus->phy_mask = ~ds->phys_mii_mask;
 785
 786         ds->slave_mii_bus = bus;
 787
 788         return devm_of_mdiobus_register(priv->dev, bus, mdio);
 789 }
 790
 791 static int
 792 qca8k_setup_mdio_bus(struct qca8k_priv *priv)
 793 {
 794         u32 internal_mdio_mask = 0, external_mdio_mask = 0, reg;
 795         struct device_node *ports, *port, *mdio;
 796         phy_interface_t mode;
 797         int err;
 798
 799         ports = of_get_child_by_name(priv->dev->of_node, "ports");
 800         if (!ports)
 801                 ports = of_get_child_by_name(priv->dev->of_node, "ethernet-ports");
 802
 803         if (!ports)
 804                 return -EINVAL;
 805
 806         for_each_available_child_of_node(ports, port) {
 807                 err = of_property_read_u32(port, "reg", &reg);
 808                 if (err) {
 809                         of_node_put(port);
 810                         of_node_put(ports);
 811                         return err;
 812                 }
 813
 814                 if (!dsa_is_user_port(priv->ds, reg))
 815                         continue;
 816
 817                 of_get_phy_mode(port, &mode);
 818
 819                 if (of_property_read_bool(port, "phy-handle") &&
 820                     mode != PHY_INTERFACE_MODE_INTERNAL)
 821                         external_mdio_mask |= BIT(reg);
 822                 else
 823                         internal_mdio_mask |= BIT(reg);
 824         }
 825
 826         of_node_put(ports);
 827         if (!external_mdio_mask && !internal_mdio_mask) {
 828                 dev_err(priv->dev, "no PHYs are defined.\n");
 829                 return -EINVAL;
 830         }
 831
 832         /* The QCA8K_MDIO_MASTER_EN Bit, which grants access to PHYs through
 833          * the MDIO_MASTER register also _disconnects_ the external MDC
 834          * passthrough to the internal PHYs. It's not possible to use both
 835          * configurations at the same time!
 836          *
 837          * Because this came up during the review process:
 838          * If the external mdio-bus driver is capable magically disabling
 839          * the QCA8K_MDIO_MASTER_EN and mutex/spin-locking out the qca8k's
 840          * accessors for the time being, it would be possible to pull this
 841          * off.
 842          */
 843         if (!!external_mdio_mask && !!internal_mdio_mask) {
 844                 dev_err(priv->dev, "either internal or external mdio bus configuration is supported.\n");
 845                 return -EINVAL;
 846         }
 847
 848         if (external_mdio_mask) {
 849                 /* Make sure to disable the internal mdio bus in cases
 850                  * a dt-overlay and driver reload changed the configuration
 851                  */
 852
 853                 return qca8k_reg_clear(priv, QCA8K_MDIO_MASTER_CTRL,
 854                                        QCA8K_MDIO_MASTER_EN);
 855         }
 856
 857         /* Check if the devicetree declare the port:phy mapping */
 858         mdio = of_get_child_by_name(priv->dev->of_node, "mdio");
 859         if (of_device_is_available(mdio)) {
 860                 err = qca8k_mdio_register(priv, mdio);
 861                 if (err)
 862                         of_node_put(mdio);
 863
 864                 return err;
 865         }
 866
 867         /* If a mapping can't be found the legacy mapping is used,
 868          * using the qca8k_port_to_phy function
 869          */
 870         priv->legacy_phy_port_mapping = true;
 871         priv->ops.phy_read = qca8k_phy_read;
 872         priv->ops.phy_write = qca8k_phy_write;
 873
 874         return 0;
 875 }
 876
 877 static int
 878 qca8k_setup_of_rgmii_delay(struct qca8k_priv *priv)
 879 {
 880         struct device_node *port_dn;
 881         phy_interface_t mode;
 882         struct dsa_port *dp;
 883         u32 val;
 884
 885         /* CPU port is already checked */
 886         dp = dsa_to_port(priv->ds, 0);
 887
 888         port_dn = dp->dn;
 889
 890         /* Check if port 0 is set to the correct type */
 891         of_get_phy_mode(port_dn, &mode);
 892         if (mode != PHY_INTERFACE_MODE_RGMII_ID &&
 893             mode != PHY_INTERFACE_MODE_RGMII_RXID &&
 894             mode != PHY_INTERFACE_MODE_RGMII_TXID) {
 895                 return 0;
 896         }
 897
 898         switch (mode) {
 899         case PHY_INTERFACE_MODE_RGMII_ID:
 900         case PHY_INTERFACE_MODE_RGMII_RXID:
 901                 if (of_property_read_u32(port_dn, "rx-internal-delay-ps", &val))
 902                         val = 2;
 903                 else
 904                         /* Switch regs accept value in ns, convert ps to ns */
 905                         val = val / 1000;
 906
 907                 if (val > QCA8K_MAX_DELAY) {
 908                         dev_err(priv->dev, "rgmii rx delay is limited to a max value of 3ns, setting to the max value");
 909                         val = 3;
 910                 }
 911
 912                 priv->rgmii_rx_delay = val;
 913                 /* Stop here if we need to check only for rx delay */
 914                 if (mode != PHY_INTERFACE_MODE_RGMII_ID)
 915                         break;
 916
 917                 fallthrough;
 918         case PHY_INTERFACE_MODE_RGMII_TXID:
 919                 if (of_property_read_u32(port_dn, "tx-internal-delay-ps", &val))
 920                         val = 1;
 921                 else
 922                         /* Switch regs accept value in ns, convert ps to ns */
 923                         val = val / 1000;
 924
 925                 if (val > QCA8K_MAX_DELAY) {
 926                         dev_err(priv->dev, "rgmii tx delay is limited to a max value of 3ns, setting to the max value");
 927                         val = 3;
 928                 }
 929
 930                 priv->rgmii_tx_delay = val;
 931                 break;
 932         default:
 933                 return 0;
 934         }
 935
 936         return 0;
 937 }
 938
 939 static int
 940 qca8k_setup(struct dsa_switch *ds)
 941 {
 942         struct qca8k_priv *priv = (struct qca8k_priv *)ds->priv;
 943         int ret, i;
 944         u32 mask;
 945
 946         /* Make sure that port 0 is the cpu port */
 947         if (!dsa_is_cpu_port(ds, 0)) {
 948                 dev_err(priv->dev, "port 0 is not the CPU port");
 949                 return -EINVAL;
 950         }
 951
 952         mutex_init(&priv->reg_mutex);
 953
 954         /* Start by setting up the register mapping */
 955         priv->regmap = devm_regmap_init(ds->dev, NULL, priv,
 956                                         &qca8k_regmap_config);
 957         if (IS_ERR(priv->regmap))
 958                 dev_warn(priv->dev, "regmap initialization failed");
 959
 960         ret = qca8k_setup_mdio_bus(priv);
 961         if (ret)
 962                 return ret;
 963
 964         ret = qca8k_setup_of_rgmii_delay(priv);
 965         if (ret)
 966                 return ret;
 967
 968         /* Enable CPU Port */
 969         ret = qca8k_reg_set(priv, QCA8K_REG_GLOBAL_FW_CTRL0,
 970                             QCA8K_GLOBAL_FW_CTRL0_CPU_PORT_EN);
 971         if (ret) {
 972                 dev_err(priv->dev, "failed enabling CPU port");
 973                 return ret;
 974         }
 975
 976         /* Enable MIB counters */
 977         ret = qca8k_mib_init(priv);
 978         if (ret)
 979                 dev_warn(priv->dev, "mib init failed");
 980
 981         /* Enable QCA header mode on the cpu port */
 982         ret = qca8k_write(priv, QCA8K_REG_PORT_HDR_CTRL(QCA8K_CPU_PORT),
 983                           QCA8K_PORT_HDR_CTRL_ALL << QCA8K_PORT_HDR_CTRL_TX_S |
 984                           QCA8K_PORT_HDR_CTRL_ALL << QCA8K_PORT_HDR_CTRL_RX_S);
 985         if (ret) {
 986                 dev_err(priv->dev, "failed enabling QCA header mode");
 987                 return ret;
 988         }
 989
 990         /* Disable forwarding by default on all ports */
 991         for (i = 0; i < QCA8K_NUM_PORTS; i++) {
 992                 ret = qca8k_rmw(priv, QCA8K_PORT_LOOKUP_CTRL(i),
 993                                 QCA8K_PORT_LOOKUP_MEMBER, 0);
 994                 if (ret)
 995                         return ret;
 996         }
 997
 998         /* Disable MAC by default on all ports */
 999         for (i = 1; i < QCA8K_NUM_PORTS; i++)
1000                 qca8k_port_set_status(priv, i, 0);
1001
1002         /* Forward all unknown frames to CPU port for Linux processing */
1003         ret = qca8k_write(priv, QCA8K_REG_GLOBAL_FW_CTRL1,
1004                           BIT(0) << QCA8K_GLOBAL_FW_CTRL1_IGMP_DP_S |
1005                           BIT(0) << QCA8K_GLOBAL_FW_CTRL1_BC_DP_S |
1006                           BIT(0) << QCA8K_GLOBAL_FW_CTRL1_MC_DP_S |
1007                           BIT(0) << QCA8K_GLOBAL_FW_CTRL1_UC_DP_S);
1008         if (ret)
1009                 return ret;
1010
1011         /* Setup connection between CPU port & user ports */
1012         for (i = 0; i < QCA8K_NUM_PORTS; i++) {
1013                 /* CPU port gets connected to all user ports of the switch */
1014                 if (dsa_is_cpu_port(ds, i)) {
1015                         ret = qca8k_rmw(priv, QCA8K_PORT_LOOKUP_CTRL(QCA8K_CPU_PORT),
1016                                         QCA8K_PORT_LOOKUP_MEMBER, dsa_user_ports(ds));
1017                         if (ret)
1018                                 return ret;
1019                 }
1020
1021                 /* Individual user ports get connected to CPU port only */
1022                 if (dsa_is_user_port(ds, i)) {
1023                         int shift = 16 * (i % 2);
1024
1025                         ret = qca8k_rmw(priv, QCA8K_PORT_LOOKUP_CTRL(i),
1026                                         QCA8K_PORT_LOOKUP_MEMBER,
1027                                         BIT(QCA8K_CPU_PORT));
1028                         if (ret)
1029                                 return ret;
1030
1031                         /* Enable ARP Auto-learning by default */
1032                         ret = qca8k_reg_set(priv, QCA8K_PORT_LOOKUP_CTRL(i),
1033                                             QCA8K_PORT_LOOKUP_LEARN);
1034                         if (ret)
1035                                 return ret;
1036
1037                         /* For port based vlans to work we need to set the
1038                          * default egress vid
1039                          */
1040                         ret = qca8k_rmw(priv, QCA8K_EGRESS_VLAN(i),
1041                                         0xfff << shift,
1042                                         QCA8K_PORT_VID_DEF << shift);
1043                         if (ret)
1044                                 return ret;
1045
1046                         ret = qca8k_write(priv, QCA8K_REG_PORT_VLAN_CTRL0(i),
1047                                           QCA8K_PORT_VLAN_CVID(QCA8K_PORT_VID_DEF) |
1048                                           QCA8K_PORT_VLAN_SVID(QCA8K_PORT_VID_DEF));
1049                         if (ret)
1050                                 return ret;
1051                 }
1052         }
1053
1054         /* The port 5 of the qca8337 have some problem in flood condition. The
1055          * original legacy driver had some specific buffer and priority settings
1056          * for the different port suggested by the QCA switch team. Add this
1057          * missing settings to improve switch stability under load condition.
1058          * This problem is limited to qca8337 and other qca8k switch are not affected.
1059          */
1060         if (priv->switch_id == QCA8K_ID_QCA8337) {
1061                 for (i = 0; i < QCA8K_NUM_PORTS; i++) {
1062                         switch (i) {
1063                         /* The 2 CPU port and port 5 requires some different
1064                          * priority than any other ports.
1065                          */
1066                         case 0:
1067                         case 5:
1068                         case 6:
1069                                 mask = QCA8K_PORT_HOL_CTRL0_EG_PRI0(0x3) |
1070                                         QCA8K_PORT_HOL_CTRL0_EG_PRI1(0x4) |
1071                                         QCA8K_PORT_HOL_CTRL0_EG_PRI2(0x4) |
1072                                         QCA8K_PORT_HOL_CTRL0_EG_PRI3(0x4) |
1073                                         QCA8K_PORT_HOL_CTRL0_EG_PRI4(0x6) |
1074                                         QCA8K_PORT_HOL_CTRL0_EG_PRI5(0x8) |
1075                                         QCA8K_PORT_HOL_CTRL0_EG_PORT(0x1e);
1076                                 break;
1077                         default:
1078                                 mask = QCA8K_PORT_HOL_CTRL0_EG_PRI0(0x3) |
1079                                         QCA8K_PORT_HOL_CTRL0_EG_PRI1(0x4) |
1080                                         QCA8K_PORT_HOL_CTRL0_EG_PRI2(0x6) |
1081                                         QCA8K_PORT_HOL_CTRL0_EG_PRI3(0x8) |
1082                                         QCA8K_PORT_HOL_CTRL0_EG_PORT(0x19);
1083                         }
1084                         qca8k_write(priv, QCA8K_REG_PORT_HOL_CTRL0(i), mask);
1085
1086                         mask = QCA8K_PORT_HOL_CTRL1_ING(0x6) |
1087                         QCA8K_PORT_HOL_CTRL1_EG_PRI_BUF_EN |
1088                         QCA8K_PORT_HOL_CTRL1_EG_PORT_BUF_EN |
1089                         QCA8K_PORT_HOL_CTRL1_WRED_EN;
1090                         qca8k_rmw(priv, QCA8K_REG_PORT_HOL_CTRL1(i),
1091                                   QCA8K_PORT_HOL_CTRL1_ING_BUF |
1092                                   QCA8K_PORT_HOL_CTRL1_EG_PRI_BUF_EN |
1093                                   QCA8K_PORT_HOL_CTRL1_EG_PORT_BUF_EN |
1094                                   QCA8K_PORT_HOL_CTRL1_WRED_EN,
1095                                   mask);
1096                 }
1097         }
1098
1099         /* Special GLOBAL_FC_THRESH value are needed for ar8327 switch */
1100         if (priv->switch_id == QCA8K_ID_QCA8327) {
1101                 mask = QCA8K_GLOBAL_FC_GOL_XON_THRES(288) |
1102                        QCA8K_GLOBAL_FC_GOL_XOFF_THRES(496);
1103                 qca8k_rmw(priv, QCA8K_REG_GLOBAL_FC_THRESH,
1104                           QCA8K_GLOBAL_FC_GOL_XON_THRES_S |
1105                           QCA8K_GLOBAL_FC_GOL_XOFF_THRES_S,
1106                           mask);
1107         }
1108
1109         /* Setup our port MTUs to match power on defaults */
1110         for (i = 0; i < QCA8K_NUM_PORTS; i++)
1111                 priv->port_mtu[i] = ETH_FRAME_LEN + ETH_FCS_LEN;
1112         ret = qca8k_write(priv, QCA8K_MAX_FRAME_SIZE, ETH_FRAME_LEN + ETH_FCS_LEN);
1113         if (ret)
1114                 dev_warn(priv->dev, "failed setting MTU settings");
1115
1116         /* Flush the FDB table */
1117         qca8k_fdb_flush(priv);
1118
1119         /* We don't have interrupts for link changes, so we need to poll */
1120         ds->pcs_poll = true;
1121
1122         return 0;
1123 }
1124
1125 static void
1126 qca8k_phylink_mac_config(struct dsa_switch *ds, int port, unsigned int mode,
1127                          const struct phylink_link_state *state)
1128 {
1129         struct qca8k_priv *priv = ds->priv;
1130         u32 reg, val;
1131         int ret;
1132
1133         switch (port) {
1134         case 0: /* 1st CPU port */
1135                 if (state->interface != PHY_INTERFACE_MODE_RGMII &&
1136                     state->interface != PHY_INTERFACE_MODE_RGMII_ID &&
1137                     state->interface != PHY_INTERFACE_MODE_RGMII_TXID &&
1138                     state->interface != PHY_INTERFACE_MODE_RGMII_RXID &&
1139                     state->interface != PHY_INTERFACE_MODE_SGMII)
1140                         return;
1141
1142                 reg = QCA8K_REG_PORT0_PAD_CTRL;
1143                 break;
1144         case 1:
1145         case 2:
1146         case 3:
1147         case 4:
1148         case 5:
1149                 /* Internal PHY, nothing to do */
1150                 return;
1151         case 6: /* 2nd CPU port / external PHY */
1152                 if (state->interface != PHY_INTERFACE_MODE_RGMII &&
1153                     state->interface != PHY_INTERFACE_MODE_RGMII_ID &&
1154                     state->interface != PHY_INTERFACE_MODE_RGMII_TXID &&
1155                     state->interface != PHY_INTERFACE_MODE_RGMII_RXID &&
1156                     state->interface != PHY_INTERFACE_MODE_SGMII &&
1157                     state->interface != PHY_INTERFACE_MODE_1000BASEX)
1158                         return;
1159
1160                 reg = QCA8K_REG_PORT6_PAD_CTRL;
1161                 break;
1162         default:
1163                 dev_err(ds->dev, "%s: unsupported port: %i\n", __func__, port);
1164                 return;
1165         }
1166
1167         if (port != 6 && phylink_autoneg_inband(mode)) {
1168                 dev_err(ds->dev, "%s: in-band negotiation unsupported\n",
1169                         __func__);
1170                 return;
1171         }
1172
1173         switch (state->interface) {
1174         case PHY_INTERFACE_MODE_RGMII:
1175                 /* RGMII mode means no delay so don't enable the delay */
1176                 qca8k_write(priv, reg, QCA8K_PORT_PAD_RGMII_EN);
1177                 break;
1178         case PHY_INTERFACE_MODE_RGMII_ID:
1179         case PHY_INTERFACE_MODE_RGMII_TXID:
1180         case PHY_INTERFACE_MODE_RGMII_RXID:
1181                 /* RGMII_ID needs internal delay. This is enabled through
1182                  * PORT5_PAD_CTRL for all ports, rather than individual port
1183                  * registers
1184                  */
1185                 qca8k_write(priv, reg,
1186                             QCA8K_PORT_PAD_RGMII_EN |
1187                             QCA8K_PORT_PAD_RGMII_TX_DELAY(priv->rgmii_tx_delay) |
1188                             QCA8K_PORT_PAD_RGMII_RX_DELAY(priv->rgmii_rx_delay) |
1189                             QCA8K_PORT_PAD_RGMII_TX_DELAY_EN |
1190                             QCA8K_PORT_PAD_RGMII_RX_DELAY_EN);
1191                 /* QCA8337 requires to set rgmii rx delay */
1192                 if (priv->switch_id == QCA8K_ID_QCA8337)
1193                         qca8k_write(priv, QCA8K_REG_PORT5_PAD_CTRL,
1194                                     QCA8K_PORT_PAD_RGMII_RX_DELAY_EN);
1195                 break;
1196         case PHY_INTERFACE_MODE_SGMII:
1197         case PHY_INTERFACE_MODE_1000BASEX:
1198                 /* Enable SGMII on the port */
1199                 qca8k_write(priv, reg, QCA8K_PORT_PAD_SGMII_EN);
1200
1201                 /* Enable/disable SerDes auto-negotiation as necessary */
1202                 ret = qca8k_read(priv, QCA8K_REG_PWS, &val);
1203                 if (ret)
1204                         return;
1205                 if (phylink_autoneg_inband(mode))
1206                         val &= ~QCA8K_PWS_SERDES_AEN_DIS;
1207                 else
1208                         val |= QCA8K_PWS_SERDES_AEN_DIS;
1209                 qca8k_write(priv, QCA8K_REG_PWS, val);
1210
1211                 /* Configure the SGMII parameters */
1212                 ret = qca8k_read(priv, QCA8K_REG_SGMII_CTRL, &val);
1213                 if (ret)
1214                         return;
1215
1216                 val |= QCA8K_SGMII_EN_PLL | QCA8K_SGMII_EN_RX |
1217                         QCA8K_SGMII_EN_TX | QCA8K_SGMII_EN_SD;
1218
1219                 if (dsa_is_cpu_port(ds, port)) {
1220                         /* CPU port, we're talking to the CPU MAC, be a PHY */
1221                         val &= ~QCA8K_SGMII_MODE_CTRL_MASK;
1222                         val |= QCA8K_SGMII_MODE_CTRL_PHY;
1223                 } else if (state->interface == PHY_INTERFACE_MODE_SGMII) {
1224                         val &= ~QCA8K_SGMII_MODE_CTRL_MASK;
1225                         val |= QCA8K_SGMII_MODE_CTRL_MAC;
1226                 } else if (state->interface == PHY_INTERFACE_MODE_1000BASEX) {
1227                         val &= ~QCA8K_SGMII_MODE_CTRL_MASK;
1228                         val |= QCA8K_SGMII_MODE_CTRL_BASEX;
1229                 }
1230
1231                 qca8k_write(priv, QCA8K_REG_SGMII_CTRL, val);
1232                 break;
1233         default:
1234                 dev_err(ds->dev, "xMII mode %s not supported for port %d\n",
1235                         phy_modes(state->interface), port);
1236                 return;
1237         }
1238 }
1239
1240 static void
1241 qca8k_phylink_validate(struct dsa_switch *ds, int port,
1242                        unsigned long *supported,
1243                        struct phylink_link_state *state)
1244 {
1245         __ETHTOOL_DECLARE_LINK_MODE_MASK(mask) = { 0, };
1246
1247         switch (port) {
1248         case 0: /* 1st CPU port */
1249                 if (state->interface != PHY_INTERFACE_MODE_NA &&
1250                     state->interface != PHY_INTERFACE_MODE_RGMII &&
1251                     state->interface != PHY_INTERFACE_MODE_RGMII_ID &&
1252                     state->interface != PHY_INTERFACE_MODE_RGMII_TXID &&
1253                     state->interface != PHY_INTERFACE_MODE_RGMII_RXID &&
1254                     state->interface != PHY_INTERFACE_MODE_SGMII)
1255                         goto unsupported;
1256                 break;
1257         case 1:
1258         case 2:
1259         case 3:
1260         case 4:
1261         case 5:
1262                 /* Internal PHY */
1263                 if (state->interface != PHY_INTERFACE_MODE_NA &&
1264                     state->interface != PHY_INTERFACE_MODE_GMII &&
1265                     state->interface != PHY_INTERFACE_MODE_INTERNAL)
1266                         goto unsupported;
1267                 break;
1268         case 6: /* 2nd CPU port / external PHY */
1269                 if (state->interface != PHY_INTERFACE_MODE_NA &&
1270                     state->interface != PHY_INTERFACE_MODE_RGMII &&
1271                     state->interface != PHY_INTERFACE_MODE_RGMII_ID &&
1272                     state->interface != PHY_INTERFACE_MODE_RGMII_TXID &&
1273                     state->interface != PHY_INTERFACE_MODE_RGMII_RXID &&
1274                     state->interface != PHY_INTERFACE_MODE_SGMII &&
1275                     state->interface != PHY_INTERFACE_MODE_1000BASEX)
1276                         goto unsupported;
1277                 break;
1278         default:
1279 unsupported:
1280                 linkmode_zero(supported);
1281                 return;
1282         }
1283
1284         phylink_set_port_modes(mask);
1285         phylink_set(mask, Autoneg);
1286
1287         phylink_set(mask, 1000baseT_Full);
1288         phylink_set(mask, 10baseT_Half);
1289         phylink_set(mask, 10baseT_Full);
1290         phylink_set(mask, 100baseT_Half);
1291         phylink_set(mask, 100baseT_Full);
1292
1293         if (state->interface == PHY_INTERFACE_MODE_1000BASEX)
1294                 phylink_set(mask, 1000baseX_Full);
1295
1296         phylink_set(mask, Pause);
1297         phylink_set(mask, Asym_Pause);
1298
1299         linkmode_and(supported, supported, mask);
1300         linkmode_and(state->advertising, state->advertising, mask);
1301 }
1302
1303 static int
1304 qca8k_phylink_mac_link_state(struct dsa_switch *ds, int port,
1305                              struct phylink_link_state *state)
1306 {
1307         struct qca8k_priv *priv = ds->priv;
1308         u32 reg;
1309         int ret;
1310
1311         ret = qca8k_read(priv, QCA8K_REG_PORT_STATUS(port), &reg);
1312         if (ret < 0)
1313                 return ret;
1314
1315         state->link = !!(reg & QCA8K_PORT_STATUS_LINK_UP);
1316         state->an_complete = state->link;
1317         state->an_enabled = !!(reg & QCA8K_PORT_STATUS_LINK_AUTO);
1318         state->duplex = (reg & QCA8K_PORT_STATUS_DUPLEX) ? DUPLEX_FULL :
1319                                                            DUPLEX_HALF;
1320
1321         switch (reg & QCA8K_PORT_STATUS_SPEED) {
1322         case QCA8K_PORT_STATUS_SPEED_10:
1323                 state->speed = SPEED_10;
1324                 break;
1325         case QCA8K_PORT_STATUS_SPEED_100:
1326                 state->speed = SPEED_100;
1327                 break;
1328         case QCA8K_PORT_STATUS_SPEED_1000:
1329                 state->speed = SPEED_1000;
1330                 break;
1331         default:
1332                 state->speed = SPEED_UNKNOWN;
1333                 break;
1334         }
1335
1336         state->pause = MLO_PAUSE_NONE;
1337         if (reg & QCA8K_PORT_STATUS_RXFLOW)
1338                 state->pause |= MLO_PAUSE_RX;
1339         if (reg & QCA8K_PORT_STATUS_TXFLOW)
1340                 state->pause |= MLO_PAUSE_TX;
1341
1342         return 1;
1343 }
1344
1345 static void
1346 qca8k_phylink_mac_link_down(struct dsa_switch *ds, int port, unsigned int mode,
1347                             phy_interface_t interface)
1348 {
1349         struct qca8k_priv *priv = ds->priv;
1350
1351         qca8k_port_set_status(priv, port, 0);
1352 }
1353
1354 static void
1355 qca8k_phylink_mac_link_up(struct dsa_switch *ds, int port, unsigned int mode,
1356                           phy_interface_t interface, struct phy_device *phydev,
1357                           int speed, int duplex, bool tx_pause, bool rx_pause)
1358 {
1359         struct qca8k_priv *priv = ds->priv;
1360         u32 reg;
1361
1362         if (phylink_autoneg_inband(mode)) {
1363                 reg = QCA8K_PORT_STATUS_LINK_AUTO;
1364         } else {
1365                 switch (speed) {
1366                 case SPEED_10:
1367                         reg = QCA8K_PORT_STATUS_SPEED_10;
1368                         break;
1369                 case SPEED_100:
1370                         reg = QCA8K_PORT_STATUS_SPEED_100;
1371                         break;
1372                 case SPEED_1000:
1373                         reg = QCA8K_PORT_STATUS_SPEED_1000;
1374                         break;
1375                 default:
1376                         reg = QCA8K_PORT_STATUS_LINK_AUTO;
1377                         break;
1378                 }
1379
1380                 if (duplex == DUPLEX_FULL)
1381                         reg |= QCA8K_PORT_STATUS_DUPLEX;
1382
1383                 if (rx_pause || dsa_is_cpu_port(ds, port))
1384                         reg |= QCA8K_PORT_STATUS_RXFLOW;
1385
1386                 if (tx_pause || dsa_is_cpu_port(ds, port))
1387                         reg |= QCA8K_PORT_STATUS_TXFLOW;
1388         }
1389
1390         reg |= QCA8K_PORT_STATUS_TXMAC | QCA8K_PORT_STATUS_RXMAC;
1391
1392         qca8k_write(priv, QCA8K_REG_PORT_STATUS(port), reg);
1393 }
1394
1395 static void
1396 qca8k_get_strings(struct dsa_switch *ds, int port, u32 stringset, uint8_t *data)
1397 {
1398         int i;
1399
1400         if (stringset != ETH_SS_STATS)
1401                 return;
1402
1403         for (i = 0; i < ARRAY_SIZE(ar8327_mib); i++)
1404                 strncpy(data + i * ETH_GSTRING_LEN, ar8327_mib[i].name,
1405                         ETH_GSTRING_LEN);
1406 }
1407
1408 static void
1409 qca8k_get_ethtool_stats(struct dsa_switch *ds, int port,
1410                         uint64_t *data)
1411 {
1412         struct qca8k_priv *priv = (struct qca8k_priv *)ds->priv;
1413         const struct qca8k_mib_desc *mib;
1414         u32 reg, i, val;
1415         u32 hi = 0;
1416         int ret;
1417
1418         for (i = 0; i < ARRAY_SIZE(ar8327_mib); i++) {
1419                 mib = &ar8327_mib[i];
1420                 reg = QCA8K_PORT_MIB_COUNTER(port) + mib->offset;
1421
1422                 ret = qca8k_read(priv, reg, &val);
1423                 if (ret < 0)
1424                         continue;
1425
1426                 if (mib->size == 2) {
1427                         ret = qca8k_read(priv, reg + 4, &hi);
1428                         if (ret < 0)
1429                                 continue;
1430                 }
1431
1432                 data[i] = val;
1433                 if (mib->size == 2)
1434                         data[i] |= (u64)hi << 32;
1435         }
1436 }
1437
1438 static int
1439 qca8k_get_sset_count(struct dsa_switch *ds, int port, int sset)
1440 {
1441         if (sset != ETH_SS_STATS)
1442                 return 0;
1443
1444         return ARRAY_SIZE(ar8327_mib);
1445 }
1446
1447 static int
1448 qca8k_set_mac_eee(struct dsa_switch *ds, int port, struct ethtool_eee *eee)
1449 {
1450         struct qca8k_priv *priv = (struct qca8k_priv *)ds->priv;
1451         u32 lpi_en = QCA8K_REG_EEE_CTRL_LPI_EN(port);
1452         u32 reg;
1453         int ret;
1454
1455         mutex_lock(&priv->reg_mutex);
1456         ret = qca8k_read(priv, QCA8K_REG_EEE_CTRL, &reg);
1457         if (ret < 0)
1458                 goto exit;
1459
1460         if (eee->eee_enabled)
1461                 reg |= lpi_en;
1462         else
1463                 reg &= ~lpi_en;
1464         ret = qca8k_write(priv, QCA8K_REG_EEE_CTRL, reg);
1465
1466 exit:
1467         mutex_unlock(&priv->reg_mutex);
1468         return ret;
1469 }
1470
1471 static int
1472 qca8k_get_mac_eee(struct dsa_switch *ds, int port, struct ethtool_eee *e)
1473 {
1474         /* Nothing to do on the port's MAC */
1475         return 0;
1476 }
1477
1478 static void
1479 qca8k_port_stp_state_set(struct dsa_switch *ds, int port, u8 state)
1480 {
1481         struct qca8k_priv *priv = (struct qca8k_priv *)ds->priv;
1482         u32 stp_state;
1483
1484         switch (state) {
1485         case BR_STATE_DISABLED:
1486                 stp_state = QCA8K_PORT_LOOKUP_STATE_DISABLED;
1487                 break;
1488         case BR_STATE_BLOCKING:
1489                 stp_state = QCA8K_PORT_LOOKUP_STATE_BLOCKING;
1490                 break;
1491         case BR_STATE_LISTENING:
1492                 stp_state = QCA8K_PORT_LOOKUP_STATE_LISTENING;
1493                 break;
1494         case BR_STATE_LEARNING:
1495                 stp_state = QCA8K_PORT_LOOKUP_STATE_LEARNING;
1496                 break;
1497         case BR_STATE_FORWARDING:
1498         default:
1499                 stp_state = QCA8K_PORT_LOOKUP_STATE_FORWARD;
1500                 break;
1501         }
1502
1503         qca8k_rmw(priv, QCA8K_PORT_LOOKUP_CTRL(port),
1504                   QCA8K_PORT_LOOKUP_STATE_MASK, stp_state);
1505 }
1506
1507 static int
1508 qca8k_port_bridge_join(struct dsa_switch *ds, int port, struct net_device *br)
1509 {
1510         struct qca8k_priv *priv = (struct qca8k_priv *)ds->priv;
1511         int port_mask = BIT(QCA8K_CPU_PORT);
1512         int i, ret;
1513
1514         for (i = 1; i < QCA8K_NUM_PORTS; i++) {
1515                 if (dsa_to_port(ds, i)->bridge_dev != br)
1516                         continue;
1517                 /* Add this port to the portvlan mask of the other ports
1518                  * in the bridge
1519                  */
1520                 ret = qca8k_reg_set(priv,
1521                                     QCA8K_PORT_LOOKUP_CTRL(i),
1522                                     BIT(port));
1523                 if (ret)
1524                         return ret;
1525                 if (i != port)
1526                         port_mask |= BIT(i);
1527         }
1528
1529         /* Add all other ports to this ports portvlan mask */
1530         ret = qca8k_rmw(priv, QCA8K_PORT_LOOKUP_CTRL(port),
1531                         QCA8K_PORT_LOOKUP_MEMBER, port_mask);
1532
1533         return ret;
1534 }
1535
1536 static void
1537 qca8k_port_bridge_leave(struct dsa_switch *ds, int port, struct net_device *br)
1538 {
1539         struct qca8k_priv *priv = (struct qca8k_priv *)ds->priv;
1540         int i;
1541
1542         for (i = 1; i < QCA8K_NUM_PORTS; i++) {
1543                 if (dsa_to_port(ds, i)->bridge_dev != br)
1544                         continue;
1545                 /* Remove this port to the portvlan mask of the other ports
1546                  * in the bridge
1547                  */
1548                 qca8k_reg_clear(priv,
1549                                 QCA8K_PORT_LOOKUP_CTRL(i),
1550                                 BIT(port));
1551         }
1552
1553         /* Set the cpu port to be the only one in the portvlan mask of
1554          * this port
1555          */
1556         qca8k_rmw(priv, QCA8K_PORT_LOOKUP_CTRL(port),
1557                   QCA8K_PORT_LOOKUP_MEMBER, BIT(QCA8K_CPU_PORT));
1558 }
1559
1560 static int
1561 qca8k_port_enable(struct dsa_switch *ds, int port,
1562                   struct phy_device *phy)
1563 {
1564         struct qca8k_priv *priv = (struct qca8k_priv *)ds->priv;
1565
1566         qca8k_port_set_status(priv, port, 1);
1567         priv->port_sts[port].enabled = 1;
1568
1569         if (dsa_is_user_port(ds, port))
1570                 phy_support_asym_pause(phy);
1571
1572         return 0;
1573 }
1574
1575 static void
1576 qca8k_port_disable(struct dsa_switch *ds, int port)
1577 {
1578         struct qca8k_priv *priv = (struct qca8k_priv *)ds->priv;
1579
1580         qca8k_port_set_status(priv, port, 0);
1581         priv->port_sts[port].enabled = 0;
1582 }
1583
1584 static int
1585 qca8k_port_change_mtu(struct dsa_switch *ds, int port, int new_mtu)
1586 {
1587         struct qca8k_priv *priv = ds->priv;
1588         int i, mtu = 0;
1589
1590         priv->port_mtu[port] = new_mtu;
1591
1592         for (i = 0; i < QCA8K_NUM_PORTS; i++)
1593                 if (priv->port_mtu[i] > mtu)
1594                         mtu = priv->port_mtu[i];
1595
1596         /* Include L2 header / FCS length */
1597         return qca8k_write(priv, QCA8K_MAX_FRAME_SIZE, mtu + ETH_HLEN + ETH_FCS_LEN);
1598 }
1599
1600 static int
1601 qca8k_port_max_mtu(struct dsa_switch *ds, int port)
1602 {
1603         return QCA8K_MAX_MTU;
1604 }
1605
1606 static int
1607 qca8k_port_fdb_insert(struct qca8k_priv *priv, const u8 *addr,
1608                       u16 port_mask, u16 vid)
1609 {
1610         /* Set the vid to the port vlan id if no vid is set */
1611         if (!vid)
1612                 vid = QCA8K_PORT_VID_DEF;
1613
1614         return qca8k_fdb_add(priv, addr, port_mask, vid,
1615                              QCA8K_ATU_STATUS_STATIC);
1616 }
1617
1618 static int
1619 qca8k_port_fdb_add(struct dsa_switch *ds, int port,
1620                    const unsigned char *addr, u16 vid)
1621 {
1622         struct qca8k_priv *priv = (struct qca8k_priv *)ds->priv;
1623         u16 port_mask = BIT(port);
1624
1625         return qca8k_port_fdb_insert(priv, addr, port_mask, vid);
1626 }
1627
1628 static int
1629 qca8k_port_fdb_del(struct dsa_switch *ds, int port,
1630                    const unsigned char *addr, u16 vid)
1631 {
1632         struct qca8k_priv *priv = (struct qca8k_priv *)ds->priv;
1633         u16 port_mask = BIT(port);
1634
1635         if (!vid)
1636                 vid = QCA8K_PORT_VID_DEF;
1637
1638         return qca8k_fdb_del(priv, addr, port_mask, vid);
1639 }
1640
1641 static int
1642 qca8k_port_fdb_dump(struct dsa_switch *ds, int port,
1643                     dsa_fdb_dump_cb_t *cb, void *data)
1644 {
1645         struct qca8k_priv *priv = (struct qca8k_priv *)ds->priv;
1646         struct qca8k_fdb _fdb = { 0 };
1647         int cnt = QCA8K_NUM_FDB_RECORDS;
1648         bool is_static;
1649         int ret = 0;
1650
1651         mutex_lock(&priv->reg_mutex);
1652         while (cnt-- && !qca8k_fdb_next(priv, &_fdb, port)) {
1653                 if (!_fdb.aging)
1654                         break;
1655                 is_static = (_fdb.aging == QCA8K_ATU_STATUS_STATIC);
1656                 ret = cb(_fdb.mac, _fdb.vid, is_static, data);
1657                 if (ret)
1658                         break;
1659         }
1660         mutex_unlock(&priv->reg_mutex);
1661
1662         return 0;
1663 }
1664
1665 static int
1666 qca8k_port_vlan_filtering(struct dsa_switch *ds, int port, bool vlan_filtering,
1667                           struct netlink_ext_ack *extack)
1668 {
1669         struct qca8k_priv *priv = ds->priv;
1670         int ret;
1671
1672         if (vlan_filtering) {
1673                 ret = qca8k_rmw(priv, QCA8K_PORT_LOOKUP_CTRL(port),
1674                                 QCA8K_PORT_LOOKUP_VLAN_MODE,
1675                                 QCA8K_PORT_LOOKUP_VLAN_MODE_SECURE);
1676         } else {
1677                 ret = qca8k_rmw(priv, QCA8K_PORT_LOOKUP_CTRL(port),
1678                                 QCA8K_PORT_LOOKUP_VLAN_MODE,
1679                                 QCA8K_PORT_LOOKUP_VLAN_MODE_NONE);
1680         }
1681
1682         return ret;
1683 }
1684
1685 static int
1686 qca8k_port_vlan_add(struct dsa_switch *ds, int port,
1687                     const struct switchdev_obj_port_vlan *vlan,
1688                     struct netlink_ext_ack *extack)
1689 {
1690         bool untagged = vlan->flags & BRIDGE_VLAN_INFO_UNTAGGED;
1691         bool pvid = vlan->flags & BRIDGE_VLAN_INFO_PVID;
1692         struct qca8k_priv *priv = ds->priv;
1693         int ret;
1694
1695         ret = qca8k_vlan_add(priv, port, vlan->vid, untagged);
1696         if (ret) {
1697                 dev_err(priv->dev, "Failed to add VLAN to port %d (%d)", port, ret);
1698                 return ret;
1699         }
1700
1701         if (pvid) {
1702                 int shift = 16 * (port % 2);
1703
1704                 ret = qca8k_rmw(priv, QCA8K_EGRESS_VLAN(port),
1705                                 0xfff << shift, vlan->vid << shift);
1706                 if (ret)
1707                         return ret;
1708
1709                 ret = qca8k_write(priv, QCA8K_REG_PORT_VLAN_CTRL0(port),
1710                                   QCA8K_PORT_VLAN_CVID(vlan->vid) |
1711                                   QCA8K_PORT_VLAN_SVID(vlan->vid));
1712         }
1713
1714         return ret;
1715 }
1716
1717 static int
1718 qca8k_port_vlan_del(struct dsa_switch *ds, int port,
1719                     const struct switchdev_obj_port_vlan *vlan)
1720 {
1721         struct qca8k_priv *priv = ds->priv;
1722         int ret;
1723
1724         ret = qca8k_vlan_del(priv, port, vlan->vid);
1725         if (ret)
1726                 dev_err(priv->dev, "Failed to delete VLAN from port %d (%d)", port, ret);
1727
1728         return ret;
1729 }
1730
1731 static u32 qca8k_get_phy_flags(struct dsa_switch *ds, int port)
1732 {
1733         struct qca8k_priv *priv = ds->priv;
1734
1735         /* Communicate to the phy internal driver the switch revision.
1736          * Based on the switch revision different values needs to be
1737          * set to the dbg and mmd reg on the phy.
1738          * The first 2 bit are used to communicate the switch revision
1739          * to the phy driver.
1740          */
1741         if (port > 0 && port < 6)
1742                 return priv->switch_revision;
1743
1744         return 0;
1745 }
1746
1747 static enum dsa_tag_protocol
1748 qca8k_get_tag_protocol(struct dsa_switch *ds, int port,
1749                        enum dsa_tag_protocol mp)
1750 {
1751         return DSA_TAG_PROTO_QCA;
1752 }
1753
1754 static const struct dsa_switch_ops qca8k_switch_ops = {
1755         .get_tag_protocol       = qca8k_get_tag_protocol,
1756         .setup                  = qca8k_setup,
1757         .get_strings            = qca8k_get_strings,
1758         .get_ethtool_stats      = qca8k_get_ethtool_stats,
1759         .get_sset_count         = qca8k_get_sset_count,
1760         .get_mac_eee            = qca8k_get_mac_eee,
1761         .set_mac_eee            = qca8k_set_mac_eee,
1762         .port_enable            = qca8k_port_enable,
1763         .port_disable           = qca8k_port_disable,
1764         .port_change_mtu        = qca8k_port_change_mtu,
1765         .port_max_mtu           = qca8k_port_max_mtu,
1766         .port_stp_state_set     = qca8k_port_stp_state_set,
1767         .port_bridge_join       = qca8k_port_bridge_join,
1768         .port_bridge_leave      = qca8k_port_bridge_leave,
1769         .port_fdb_add           = qca8k_port_fdb_add,
1770         .port_fdb_del           = qca8k_port_fdb_del,
1771         .port_fdb_dump          = qca8k_port_fdb_dump,
1772         .port_vlan_filtering    = qca8k_port_vlan_filtering,
1773         .port_vlan_add          = qca8k_port_vlan_add,
1774         .port_vlan_del          = qca8k_port_vlan_del,
1775         .phylink_validate       = qca8k_phylink_validate,
1776         .phylink_mac_link_state = qca8k_phylink_mac_link_state,
1777         .phylink_mac_config     = qca8k_phylink_mac_config,
1778         .phylink_mac_link_down  = qca8k_phylink_mac_link_down,
1779         .phylink_mac_link_up    = qca8k_phylink_mac_link_up,
1780         .get_phy_flags          = qca8k_get_phy_flags,
1781 };
1782
1783 static int qca8k_read_switch_id(struct qca8k_priv *priv)
1784 {
1785         const struct qca8k_match_data *data;
1786         u32 val;
1787         u8 id;
1788         int ret;
1789
1790         /* get the switches ID from the compatible */
1791         data = of_device_get_match_data(priv->dev);
1792         if (!data)
1793                 return -ENODEV;
1794
1795         ret = qca8k_read(priv, QCA8K_REG_MASK_CTRL, &val);
1796         if (ret < 0)
1797                 return -ENODEV;
1798
1799         id = QCA8K_MASK_CTRL_DEVICE_ID(val & QCA8K_MASK_CTRL_DEVICE_ID_MASK);
1800         if (id != data->id) {
1801                 dev_err(priv->dev, "Switch id detected %x but expected %x", id, data->id);
1802                 return -ENODEV;
1803         }
1804
1805         priv->switch_id = id;
1806
1807         /* Save revision to communicate to the internal PHY driver */
1808         priv->switch_revision = (val & QCA8K_MASK_CTRL_REV_ID_MASK);
1809
1810         return 0;
1811 }
1812
1813 static int
1814 qca8k_sw_probe(struct mdio_device *mdiodev)
1815 {
1816         struct qca8k_priv *priv;
1817         int ret;
1818
1819         /* allocate the private data struct so that we can probe the switches
1820          * ID register
1821          */
1822         priv = devm_kzalloc(&mdiodev->dev, sizeof(*priv), GFP_KERNEL);
1823         if (!priv)
1824                 return -ENOMEM;
1825
1826         priv->bus = mdiodev->bus;
1827         priv->dev = &mdiodev->dev;
1828
1829         priv->reset_gpio = devm_gpiod_get_optional(priv->dev, "reset",
1830                                                    GPIOD_ASIS);
1831         if (IS_ERR(priv->reset_gpio))
1832                 return PTR_ERR(priv->reset_gpio);
1833
1834         if (priv->reset_gpio) {
1835                 gpiod_set_value_cansleep(priv->reset_gpio, 1);
1836                 /* The active low duration must be greater than 10 ms
1837                  * and checkpatch.pl wants 20 ms.
1838                  */
1839                 msleep(20);
1840                 gpiod_set_value_cansleep(priv->reset_gpio, 0);
1841         }
1842
1843         /* Check the detected switch id */
1844         ret = qca8k_read_switch_id(priv);
1845         if (ret)
1846                 return ret;
1847
1848         priv->ds = devm_kzalloc(&mdiodev->dev, sizeof(*priv->ds), GFP_KERNEL);
1849         if (!priv->ds)
1850                 return -ENOMEM;
1851
1852         priv->ds->dev = &mdiodev->dev;
1853         priv->ds->num_ports = QCA8K_NUM_PORTS;
1854         priv->ds->priv = priv;
1855         priv->ops = qca8k_switch_ops;
1856         priv->ds->ops = &priv->ops;
1857         mutex_init(&priv->reg_mutex);
1858         dev_set_drvdata(&mdiodev->dev, priv);
1859
1860         return dsa_register_switch(priv->ds);
1861 }
1862
1863 static void
1864 qca8k_sw_remove(struct mdio_device *mdiodev)
1865 {
1866         struct qca8k_priv *priv = dev_get_drvdata(&mdiodev->dev);
1867         int i;
1868
1869         for (i = 0; i < QCA8K_NUM_PORTS; i++)
1870                 qca8k_port_set_status(priv, i, 0);
1871
1872         dsa_unregister_switch(priv->ds);
1873 }
1874
1875 #ifdef CONFIG_PM_SLEEP
1876 static void
1877 qca8k_set_pm(struct qca8k_priv *priv, int enable)
1878 {
1879         int i;
1880
1881         for (i = 0; i < QCA8K_NUM_PORTS; i++) {
1882                 if (!priv->port_sts[i].enabled)
1883                         continue;
1884
1885                 qca8k_port_set_status(priv, i, enable);
1886         }
1887 }
1888
1889 static int qca8k_suspend(struct device *dev)
1890 {
1891         struct qca8k_priv *priv = dev_get_drvdata(dev);
1892
1893         qca8k_set_pm(priv, 0);
1894
1895         return dsa_switch_suspend(priv->ds);
1896 }
1897
1898 static int qca8k_resume(struct device *dev)
1899 {
1900         struct qca8k_priv *priv = dev_get_drvdata(dev);
1901
1902         qca8k_set_pm(priv, 1);
1903
1904         return dsa_switch_resume(priv->ds);
1905 }
1906 #endif /* CONFIG_PM_SLEEP */
1907
1908 static SIMPLE_DEV_PM_OPS(qca8k_pm_ops,
1909                          qca8k_suspend, qca8k_resume);
1910
1911 static const struct qca8k_match_data qca832x = {
1912         .id = QCA8K_ID_QCA8327,
1913 };
1914
1915 static const struct qca8k_match_data qca833x = {
1916         .id = QCA8K_ID_QCA8337,
1917 };
1918
1919 static const struct of_device_id qca8k_of_match[] = {
1920         { .compatible = "qca,qca8327", .data = &qca832x },
1921         { .compatible = "qca,qca8334", .data = &qca833x },
1922         { .compatible = "qca,qca8337", .data = &qca833x },
1923         { /* sentinel */ },
1924 };
1925
1926 static struct mdio_driver qca8kmdio_driver = {
1927         .probe  = qca8k_sw_probe,
1928         .remove = qca8k_sw_remove,
1929         .mdiodrv.driver = {
1930                 .name = "qca8k",
1931                 .of_match_table = qca8k_of_match,
1932                 .pm = &qca8k_pm_ops,
1933         },
1934 };
1935
1936 mdio_module_driver(qca8kmdio_driver);
1937
1938 MODULE_AUTHOR("Mathieu Olivari, John Crispin <john@phrozen.org>");
1939 MODULE_DESCRIPTION("Driver for QCA8K ethernet switch family");
1940 MODULE_LICENSE("GPL v2");
1941 MODULE_ALIAS("platform:qca8k");