drivers/net/dsa/ocelot/felix_vsc9959.c

   1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
   2 /* Copyright 2017 Microsemi Corporation
   3  * Copyright 2018-2019 NXP
   4  */
   5 #include <linux/fsl/enetc_mdio.h>
   6 #include <soc/mscc/ocelot_qsys.h>
   7 #include <soc/mscc/ocelot_vcap.h>
   8 #include <soc/mscc/ocelot_ana.h>
   9 #include <soc/mscc/ocelot_ptp.h>
  10 #include <soc/mscc/ocelot_sys.h>
  11 #include <net/tc_act/tc_gate.h>
  12 #include <soc/mscc/ocelot.h>
  13 #include <linux/dsa/ocelot.h>
  14 #include <linux/pcs-lynx.h>
  15 #include <net/pkt_sched.h>
  16 #include <linux/iopoll.h>
  17 #include <linux/mdio.h>
  18 #include <linux/pci.h>
  19 #include "felix.h"
  20
  21 #define VSC9959_TAS_GCL_ENTRY_MAX       63
  22 #define VSC9959_VCAP_POLICER_BASE       63
  23 #define VSC9959_VCAP_POLICER_MAX        383
  24 #define VSC9959_SWITCH_PCI_BAR          4
  25 #define VSC9959_IMDIO_PCI_BAR           0
  26
  27 static const u32 vsc9959_ana_regmap[] = {
  28         REG(ANA_ADVLEARN,                       0x0089a0),
  29         REG(ANA_VLANMASK,                       0x0089a4),
  30         REG_RESERVED(ANA_PORT_B_DOMAIN),
  31         REG(ANA_ANAGEFIL,                       0x0089ac),
  32         REG(ANA_ANEVENTS,                       0x0089b0),
  33         REG(ANA_STORMLIMIT_BURST,               0x0089b4),
  34         REG(ANA_STORMLIMIT_CFG,                 0x0089b8),
  35         REG(ANA_ISOLATED_PORTS,                 0x0089c8),
  36         REG(ANA_COMMUNITY_PORTS,                0x0089cc),
  37         REG(ANA_AUTOAGE,                        0x0089d0),
  38         REG(ANA_MACTOPTIONS,                    0x0089d4),
  39         REG(ANA_LEARNDISC,                      0x0089d8),
  40         REG(ANA_AGENCTRL,                       0x0089dc),
  41         REG(ANA_MIRRORPORTS,                    0x0089e0),
  42         REG(ANA_EMIRRORPORTS,                   0x0089e4),
  43         REG(ANA_FLOODING,                       0x0089e8),
  44         REG(ANA_FLOODING_IPMC,                  0x008a08),
  45         REG(ANA_SFLOW_CFG,                      0x008a0c),
  46         REG(ANA_PORT_MODE,                      0x008a28),
  47         REG(ANA_CUT_THRU_CFG,                   0x008a48),
  48         REG(ANA_PGID_PGID,                      0x008400),
  49         REG(ANA_TABLES_ANMOVED,                 0x007f1c),
  50         REG(ANA_TABLES_MACHDATA,                0x007f20),
  51         REG(ANA_TABLES_MACLDATA,                0x007f24),
  52         REG(ANA_TABLES_STREAMDATA,              0x007f28),
  53         REG(ANA_TABLES_MACACCESS,               0x007f2c),
  54         REG(ANA_TABLES_MACTINDX,                0x007f30),
  55         REG(ANA_TABLES_VLANACCESS,              0x007f34),
  56         REG(ANA_TABLES_VLANTIDX,                0x007f38),
  57         REG(ANA_TABLES_ISDXACCESS,              0x007f3c),
  58         REG(ANA_TABLES_ISDXTIDX,                0x007f40),
  59         REG(ANA_TABLES_ENTRYLIM,                0x007f00),
  60         REG(ANA_TABLES_PTP_ID_HIGH,             0x007f44),
  61         REG(ANA_TABLES_PTP_ID_LOW,              0x007f48),
  62         REG(ANA_TABLES_STREAMACCESS,            0x007f4c),
  63         REG(ANA_TABLES_STREAMTIDX,              0x007f50),
  64         REG(ANA_TABLES_SEQ_HISTORY,             0x007f54),
  65         REG(ANA_TABLES_SEQ_MASK,                0x007f58),
  66         REG(ANA_TABLES_SFID_MASK,               0x007f5c),
  67         REG(ANA_TABLES_SFIDACCESS,              0x007f60),
  68         REG(ANA_TABLES_SFIDTIDX,                0x007f64),
  69         REG(ANA_MSTI_STATE,                     0x008600),
  70         REG(ANA_OAM_UPM_LM_CNT,                 0x008000),
  71         REG(ANA_SG_ACCESS_CTRL,                 0x008a64),
  72         REG(ANA_SG_CONFIG_REG_1,                0x007fb0),
  73         REG(ANA_SG_CONFIG_REG_2,                0x007fb4),
  74         REG(ANA_SG_CONFIG_REG_3,                0x007fb8),
  75         REG(ANA_SG_CONFIG_REG_4,                0x007fbc),
  76         REG(ANA_SG_CONFIG_REG_5,                0x007fc0),
  77         REG(ANA_SG_GCL_GS_CONFIG,               0x007f80),
  78         REG(ANA_SG_GCL_TI_CONFIG,               0x007f90),
  79         REG(ANA_SG_STATUS_REG_1,                0x008980),
  80         REG(ANA_SG_STATUS_REG_2,                0x008984),
  81         REG(ANA_SG_STATUS_REG_3,                0x008988),
  82         REG(ANA_PORT_VLAN_CFG,                  0x007800),
  83         REG(ANA_PORT_DROP_CFG,                  0x007804),
  84         REG(ANA_PORT_QOS_CFG,                   0x007808),
  85         REG(ANA_PORT_VCAP_CFG,                  0x00780c),
  86         REG(ANA_PORT_VCAP_S1_KEY_CFG,           0x007810),
  87         REG(ANA_PORT_VCAP_S2_CFG,               0x00781c),
  88         REG(ANA_PORT_PCP_DEI_MAP,               0x007820),
  89         REG(ANA_PORT_CPU_FWD_CFG,               0x007860),
  90         REG(ANA_PORT_CPU_FWD_BPDU_CFG,          0x007864),
  91         REG(ANA_PORT_CPU_FWD_GARP_CFG,          0x007868),
  92         REG(ANA_PORT_CPU_FWD_CCM_CFG,           0x00786c),
  93         REG(ANA_PORT_PORT_CFG,                  0x007870),
  94         REG(ANA_PORT_POL_CFG,                   0x007874),
  95         REG(ANA_PORT_PTP_CFG,                   0x007878),
  96         REG(ANA_PORT_PTP_DLY1_CFG,              0x00787c),
  97         REG(ANA_PORT_PTP_DLY2_CFG,              0x007880),
  98         REG(ANA_PORT_SFID_CFG,                  0x007884),
  99         REG(ANA_PFC_PFC_CFG,                    0x008800),
 100         REG_RESERVED(ANA_PFC_PFC_TIMER),
 101         REG_RESERVED(ANA_IPT_OAM_MEP_CFG),
 102         REG_RESERVED(ANA_IPT_IPT),
 103         REG_RESERVED(ANA_PPT_PPT),
 104         REG_RESERVED(ANA_FID_MAP_FID_MAP),
 105         REG(ANA_AGGR_CFG,                       0x008a68),
 106         REG(ANA_CPUQ_CFG,                       0x008a6c),
 107         REG_RESERVED(ANA_CPUQ_CFG2),
 108         REG(ANA_CPUQ_8021_CFG,                  0x008a74),
 109         REG(ANA_DSCP_CFG,                       0x008ab4),
 110         REG(ANA_DSCP_REWR_CFG,                  0x008bb4),
 111         REG(ANA_VCAP_RNG_TYPE_CFG,              0x008bf4),
 112         REG(ANA_VCAP_RNG_VAL_CFG,               0x008c14),
 113         REG_RESERVED(ANA_VRAP_CFG),
 114         REG_RESERVED(ANA_VRAP_HDR_DATA),
 115         REG_RESERVED(ANA_VRAP_HDR_MASK),
 116         REG(ANA_DISCARD_CFG,                    0x008c40),
 117         REG(ANA_FID_CFG,                        0x008c44),
 118         REG(ANA_POL_PIR_CFG,                    0x004000),
 119         REG(ANA_POL_CIR_CFG,                    0x004004),
 120         REG(ANA_POL_MODE_CFG,                   0x004008),
 121         REG(ANA_POL_PIR_STATE,                  0x00400c),
 122         REG(ANA_POL_CIR_STATE,                  0x004010),
 123         REG_RESERVED(ANA_POL_STATE),
 124         REG(ANA_POL_FLOWC,                      0x008c48),
 125         REG(ANA_POL_HYST,                       0x008cb4),
 126         REG_RESERVED(ANA_POL_MISC_CFG),
 127 };
 128
 129 static const u32 vsc9959_qs_regmap[] = {
 130         REG(QS_XTR_GRP_CFG,                     0x000000),
 131         REG(QS_XTR_RD,                          0x000008),
 132         REG(QS_XTR_FRM_PRUNING,                 0x000010),
 133         REG(QS_XTR_FLUSH,                       0x000018),
 134         REG(QS_XTR_DATA_PRESENT,                0x00001c),
 135         REG(QS_XTR_CFG,                         0x000020),
 136         REG(QS_INJ_GRP_CFG,                     0x000024),
 137         REG(QS_INJ_WR,                          0x00002c),
 138         REG(QS_INJ_CTRL,                        0x000034),
 139         REG(QS_INJ_STATUS,                      0x00003c),
 140         REG(QS_INJ_ERR,                         0x000040),
 141         REG_RESERVED(QS_INH_DBG),
 142 };
 143
 144 static const u32 vsc9959_vcap_regmap[] = {
 145         /* VCAP_CORE_CFG */
 146         REG(VCAP_CORE_UPDATE_CTRL,              0x000000),
 147         REG(VCAP_CORE_MV_CFG,                   0x000004),
 148         /* VCAP_CORE_CACHE */
 149         REG(VCAP_CACHE_ENTRY_DAT,               0x000008),
 150         REG(VCAP_CACHE_MASK_DAT,                0x000108),
 151         REG(VCAP_CACHE_ACTION_DAT,              0x000208),
 152         REG(VCAP_CACHE_CNT_DAT,                 0x000308),
 153         REG(VCAP_CACHE_TG_DAT,                  0x000388),
 154         /* VCAP_CONST */
 155         REG(VCAP_CONST_VCAP_VER,                0x000398),
 156         REG(VCAP_CONST_ENTRY_WIDTH,             0x00039c),
 157         REG(VCAP_CONST_ENTRY_CNT,               0x0003a0),
 158         REG(VCAP_CONST_ENTRY_SWCNT,             0x0003a4),
 159         REG(VCAP_CONST_ENTRY_TG_WIDTH,          0x0003a8),
 160         REG(VCAP_CONST_ACTION_DEF_CNT,          0x0003ac),
 161         REG(VCAP_CONST_ACTION_WIDTH,            0x0003b0),
 162         REG(VCAP_CONST_CNT_WIDTH,               0x0003b4),
 163         REG(VCAP_CONST_CORE_CNT,                0x0003b8),
 164         REG(VCAP_CONST_IF_CNT,                  0x0003bc),
 165 };
 166
 167 static const u32 vsc9959_qsys_regmap[] = {
 168         REG(QSYS_PORT_MODE,                     0x00f460),
 169         REG(QSYS_SWITCH_PORT_MODE,              0x00f480),
 170         REG(QSYS_STAT_CNT_CFG,                  0x00f49c),
 171         REG(QSYS_EEE_CFG,                       0x00f4a0),
 172         REG(QSYS_EEE_THRES,                     0x00f4b8),
 173         REG(QSYS_IGR_NO_SHARING,                0x00f4bc),
 174         REG(QSYS_EGR_NO_SHARING,                0x00f4c0),
 175         REG(QSYS_SW_STATUS,                     0x00f4c4),
 176         REG(QSYS_EXT_CPU_CFG,                   0x00f4e0),
 177         REG_RESERVED(QSYS_PAD_CFG),
 178         REG(QSYS_CPU_GROUP_MAP,                 0x00f4e8),
 179         REG_RESERVED(QSYS_QMAP),
 180         REG_RESERVED(QSYS_ISDX_SGRP),
 181         REG_RESERVED(QSYS_TIMED_FRAME_ENTRY),
 182         REG(QSYS_TFRM_MISC,                     0x00f50c),
 183         REG(QSYS_TFRM_PORT_DLY,                 0x00f510),
 184         REG(QSYS_TFRM_TIMER_CFG_1,              0x00f514),
 185         REG(QSYS_TFRM_TIMER_CFG_2,              0x00f518),
 186         REG(QSYS_TFRM_TIMER_CFG_3,              0x00f51c),
 187         REG(QSYS_TFRM_TIMER_CFG_4,              0x00f520),
 188         REG(QSYS_TFRM_TIMER_CFG_5,              0x00f524),
 189         REG(QSYS_TFRM_TIMER_CFG_6,              0x00f528),
 190         REG(QSYS_TFRM_TIMER_CFG_7,              0x00f52c),
 191         REG(QSYS_TFRM_TIMER_CFG_8,              0x00f530),
 192         REG(QSYS_RED_PROFILE,                   0x00f534),
 193         REG(QSYS_RES_QOS_MODE,                  0x00f574),
 194         REG(QSYS_RES_CFG,                       0x00c000),
 195         REG(QSYS_RES_STAT,                      0x00c004),
 196         REG(QSYS_EGR_DROP_MODE,                 0x00f578),
 197         REG(QSYS_EQ_CTRL,                       0x00f57c),
 198         REG_RESERVED(QSYS_EVENTS_CORE),
 199         REG(QSYS_QMAXSDU_CFG_0,                 0x00f584),
 200         REG(QSYS_QMAXSDU_CFG_1,                 0x00f5a0),
 201         REG(QSYS_QMAXSDU_CFG_2,                 0x00f5bc),
 202         REG(QSYS_QMAXSDU_CFG_3,                 0x00f5d8),
 203         REG(QSYS_QMAXSDU_CFG_4,                 0x00f5f4),
 204         REG(QSYS_QMAXSDU_CFG_5,                 0x00f610),
 205         REG(QSYS_QMAXSDU_CFG_6,                 0x00f62c),
 206         REG(QSYS_QMAXSDU_CFG_7,                 0x00f648),
 207         REG(QSYS_PREEMPTION_CFG,                0x00f664),
 208         REG(QSYS_CIR_CFG,                       0x000000),
 209         REG(QSYS_EIR_CFG,                       0x000004),
 210         REG(QSYS_SE_CFG,                        0x000008),
 211         REG(QSYS_SE_DWRR_CFG,                   0x00000c),
 212         REG_RESERVED(QSYS_SE_CONNECT),
 213         REG(QSYS_SE_DLB_SENSE,                  0x000040),
 214         REG(QSYS_CIR_STATE,                     0x000044),
 215         REG(QSYS_EIR_STATE,                     0x000048),
 216         REG_RESERVED(QSYS_SE_STATE),
 217         REG(QSYS_HSCH_MISC_CFG,                 0x00f67c),
 218         REG(QSYS_TAG_CONFIG,                    0x00f680),
 219         REG(QSYS_TAS_PARAM_CFG_CTRL,            0x00f698),
 220         REG(QSYS_PORT_MAX_SDU,                  0x00f69c),
 221         REG(QSYS_PARAM_CFG_REG_1,               0x00f440),
 222         REG(QSYS_PARAM_CFG_REG_2,               0x00f444),
 223         REG(QSYS_PARAM_CFG_REG_3,               0x00f448),
 224         REG(QSYS_PARAM_CFG_REG_4,               0x00f44c),
 225         REG(QSYS_PARAM_CFG_REG_5,               0x00f450),
 226         REG(QSYS_GCL_CFG_REG_1,                 0x00f454),
 227         REG(QSYS_GCL_CFG_REG_2,                 0x00f458),
 228         REG(QSYS_PARAM_STATUS_REG_1,            0x00f400),
 229         REG(QSYS_PARAM_STATUS_REG_2,            0x00f404),
 230         REG(QSYS_PARAM_STATUS_REG_3,            0x00f408),
 231         REG(QSYS_PARAM_STATUS_REG_4,            0x00f40c),
 232         REG(QSYS_PARAM_STATUS_REG_5,            0x00f410),
 233         REG(QSYS_PARAM_STATUS_REG_6,            0x00f414),
 234         REG(QSYS_PARAM_STATUS_REG_7,            0x00f418),
 235         REG(QSYS_PARAM_STATUS_REG_8,            0x00f41c),
 236         REG(QSYS_PARAM_STATUS_REG_9,            0x00f420),
 237         REG(QSYS_GCL_STATUS_REG_1,              0x00f424),
 238         REG(QSYS_GCL_STATUS_REG_2,              0x00f428),
 239 };
 240
 241 static const u32 vsc9959_rew_regmap[] = {
 242         REG(REW_PORT_VLAN_CFG,                  0x000000),
 243         REG(REW_TAG_CFG,                        0x000004),
 244         REG(REW_PORT_CFG,                       0x000008),
 245         REG(REW_DSCP_CFG,                       0x00000c),
 246         REG(REW_PCP_DEI_QOS_MAP_CFG,            0x000010),
 247         REG(REW_PTP_CFG,                        0x000050),
 248         REG(REW_PTP_DLY1_CFG,                   0x000054),
 249         REG(REW_RED_TAG_CFG,                    0x000058),
 250         REG(REW_DSCP_REMAP_DP1_CFG,             0x000410),
 251         REG(REW_DSCP_REMAP_CFG,                 0x000510),
 252         REG_RESERVED(REW_STAT_CFG),
 253         REG_RESERVED(REW_REW_STICKY),
 254         REG_RESERVED(REW_PPT),
 255 };
 256
 257 static const u32 vsc9959_sys_regmap[] = {
 258         REG(SYS_COUNT_RX_OCTETS,                0x000000),
 259         REG(SYS_COUNT_RX_MULTICAST,             0x000008),
 260         REG(SYS_COUNT_RX_SHORTS,                0x000010),
 261         REG(SYS_COUNT_RX_FRAGMENTS,             0x000014),
 262         REG(SYS_COUNT_RX_JABBERS,               0x000018),
 263         REG(SYS_COUNT_RX_64,                    0x000024),
 264         REG(SYS_COUNT_RX_65_127,                0x000028),
 265         REG(SYS_COUNT_RX_128_255,               0x00002c),
 266         REG(SYS_COUNT_RX_256_1023,              0x000030),
 267         REG(SYS_COUNT_RX_1024_1526,             0x000034),
 268         REG(SYS_COUNT_RX_1527_MAX,              0x000038),
 269         REG(SYS_COUNT_RX_LONGS,                 0x000044),
 270         REG(SYS_COUNT_TX_OCTETS,                0x000200),
 271         REG(SYS_COUNT_TX_COLLISION,             0x000210),
 272         REG(SYS_COUNT_TX_DROPS,                 0x000214),
 273         REG(SYS_COUNT_TX_64,                    0x00021c),
 274         REG(SYS_COUNT_TX_65_127,                0x000220),
 275         REG(SYS_COUNT_TX_128_511,               0x000224),
 276         REG(SYS_COUNT_TX_512_1023,              0x000228),
 277         REG(SYS_COUNT_TX_1024_1526,             0x00022c),
 278         REG(SYS_COUNT_TX_1527_MAX,              0x000230),
 279         REG(SYS_COUNT_TX_AGING,                 0x000278),
 280         REG(SYS_RESET_CFG,                      0x000e00),
 281         REG(SYS_SR_ETYPE_CFG,                   0x000e04),
 282         REG(SYS_VLAN_ETYPE_CFG,                 0x000e08),
 283         REG(SYS_PORT_MODE,                      0x000e0c),
 284         REG(SYS_FRONT_PORT_MODE,                0x000e2c),
 285         REG(SYS_FRM_AGING,                      0x000e44),
 286         REG(SYS_STAT_CFG,                       0x000e48),
 287         REG(SYS_SW_STATUS,                      0x000e4c),
 288         REG_RESERVED(SYS_MISC_CFG),
 289         REG(SYS_REW_MAC_HIGH_CFG,               0x000e6c),
 290         REG(SYS_REW_MAC_LOW_CFG,                0x000e84),
 291         REG(SYS_TIMESTAMP_OFFSET,               0x000e9c),
 292         REG(SYS_PAUSE_CFG,                      0x000ea0),
 293         REG(SYS_PAUSE_TOT_CFG,                  0x000ebc),
 294         REG(SYS_ATOP,                           0x000ec0),
 295         REG(SYS_ATOP_TOT_CFG,                   0x000edc),
 296         REG(SYS_MAC_FC_CFG,                     0x000ee0),
 297         REG(SYS_MMGT,                           0x000ef8),
 298         REG_RESERVED(SYS_MMGT_FAST),
 299         REG_RESERVED(SYS_EVENTS_DIF),
 300         REG_RESERVED(SYS_EVENTS_CORE),
 301         REG(SYS_CNT,                            0x000000),
 302         REG(SYS_PTP_STATUS,                     0x000f14),
 303         REG(SYS_PTP_TXSTAMP,                    0x000f18),
 304         REG(SYS_PTP_NXT,                        0x000f1c),
 305         REG(SYS_PTP_CFG,                        0x000f20),
 306         REG(SYS_RAM_INIT,                       0x000f24),
 307         REG_RESERVED(SYS_CM_ADDR),
 308         REG_RESERVED(SYS_CM_DATA_WR),
 309         REG_RESERVED(SYS_CM_DATA_RD),
 310         REG_RESERVED(SYS_CM_OP),
 311         REG_RESERVED(SYS_CM_DATA),
 312 };
 313
 314 static const u32 vsc9959_ptp_regmap[] = {
 315         REG(PTP_PIN_CFG,                        0x000000),
 316         REG(PTP_PIN_TOD_SEC_MSB,                0x000004),
 317         REG(PTP_PIN_TOD_SEC_LSB,                0x000008),
 318         REG(PTP_PIN_TOD_NSEC,                   0x00000c),
 319         REG(PTP_PIN_WF_HIGH_PERIOD,             0x000014),
 320         REG(PTP_PIN_WF_LOW_PERIOD,              0x000018),
 321         REG(PTP_CFG_MISC,                       0x0000a0),
 322         REG(PTP_CLK_CFG_ADJ_CFG,                0x0000a4),
 323         REG(PTP_CLK_CFG_ADJ_FREQ,               0x0000a8),
 324 };
 325
 326 static const u32 vsc9959_gcb_regmap[] = {
 327         REG(GCB_SOFT_RST,                       0x000004),
 328 };
 329
 330 static const u32 vsc9959_dev_gmii_regmap[] = {
 331         REG(DEV_CLOCK_CFG,                      0x0),
 332         REG(DEV_PORT_MISC,                      0x4),
 333         REG(DEV_EVENTS,                         0x8),
 334         REG(DEV_EEE_CFG,                        0xc),
 335         REG(DEV_RX_PATH_DELAY,                  0x10),
 336         REG(DEV_TX_PATH_DELAY,                  0x14),
 337         REG(DEV_PTP_PREDICT_CFG,                0x18),
 338         REG(DEV_MAC_ENA_CFG,                    0x1c),
 339         REG(DEV_MAC_MODE_CFG,                   0x20),
 340         REG(DEV_MAC_MAXLEN_CFG,                 0x24),
 341         REG(DEV_MAC_TAGS_CFG,                   0x28),
 342         REG(DEV_MAC_ADV_CHK_CFG,                0x2c),
 343         REG(DEV_MAC_IFG_CFG,                    0x30),
 344         REG(DEV_MAC_HDX_CFG,                    0x34),
 345         REG(DEV_MAC_DBG_CFG,                    0x38),
 346         REG(DEV_MAC_FC_MAC_LOW_CFG,             0x3c),
 347         REG(DEV_MAC_FC_MAC_HIGH_CFG,            0x40),
 348         REG(DEV_MAC_STICKY,                     0x44),
 349         REG_RESERVED(PCS1G_CFG),
 350         REG_RESERVED(PCS1G_MODE_CFG),
 351         REG_RESERVED(PCS1G_SD_CFG),
 352         REG_RESERVED(PCS1G_ANEG_CFG),
 353         REG_RESERVED(PCS1G_ANEG_NP_CFG),
 354         REG_RESERVED(PCS1G_LB_CFG),
 355         REG_RESERVED(PCS1G_DBG_CFG),
 356         REG_RESERVED(PCS1G_CDET_CFG),
 357         REG_RESERVED(PCS1G_ANEG_STATUS),
 358         REG_RESERVED(PCS1G_ANEG_NP_STATUS),
 359         REG_RESERVED(PCS1G_LINK_STATUS),
 360         REG_RESERVED(PCS1G_LINK_DOWN_CNT),
 361         REG_RESERVED(PCS1G_STICKY),
 362         REG_RESERVED(PCS1G_DEBUG_STATUS),
 363         REG_RESERVED(PCS1G_LPI_CFG),
 364         REG_RESERVED(PCS1G_LPI_WAKE_ERROR_CNT),
 365         REG_RESERVED(PCS1G_LPI_STATUS),
 366         REG_RESERVED(PCS1G_TSTPAT_MODE_CFG),
 367         REG_RESERVED(PCS1G_TSTPAT_STATUS),
 368         REG_RESERVED(DEV_PCS_FX100_CFG),
 369         REG_RESERVED(DEV_PCS_FX100_STATUS),
 370 };
 371
 372 static const u32 *vsc9959_regmap[TARGET_MAX] = {
 373         [ANA]   = vsc9959_ana_regmap,
 374         [QS]    = vsc9959_qs_regmap,
 375         [QSYS]  = vsc9959_qsys_regmap,
 376         [REW]   = vsc9959_rew_regmap,
 377         [SYS]   = vsc9959_sys_regmap,
 378         [S0]    = vsc9959_vcap_regmap,
 379         [S1]    = vsc9959_vcap_regmap,
 380         [S2]    = vsc9959_vcap_regmap,
 381         [PTP]   = vsc9959_ptp_regmap,
 382         [GCB]   = vsc9959_gcb_regmap,
 383         [DEV_GMII] = vsc9959_dev_gmii_regmap,
 384 };
 385
 386 /* Addresses are relative to the PCI device's base address */
 387 static const struct resource vsc9959_target_io_res[TARGET_MAX] = {
 388         [ANA] = {
 389                 .start  = 0x0280000,
 390                 .end    = 0x028ffff,
 391                 .name   = "ana",
 392         },
 393         [QS] = {
 394                 .start  = 0x0080000,
 395                 .end    = 0x00800ff,
 396                 .name   = "qs",
 397         },
 398         [QSYS] = {
 399                 .start  = 0x0200000,
 400                 .end    = 0x021ffff,
 401                 .name   = "qsys",
 402         },
 403         [REW] = {
 404                 .start  = 0x0030000,
 405                 .end    = 0x003ffff,
 406                 .name   = "rew",
 407         },
 408         [SYS] = {
 409                 .start  = 0x0010000,
 410                 .end    = 0x001ffff,
 411                 .name   = "sys",
 412         },
 413         [S0] = {
 414                 .start  = 0x0040000,
 415                 .end    = 0x00403ff,
 416                 .name   = "s0",
 417         },
 418         [S1] = {
 419                 .start  = 0x0050000,
 420                 .end    = 0x00503ff,
 421                 .name   = "s1",
 422         },
 423         [S2] = {
 424                 .start  = 0x0060000,
 425                 .end    = 0x00603ff,
 426                 .name   = "s2",
 427         },
 428         [PTP] = {
 429                 .start  = 0x0090000,
 430                 .end    = 0x00900cb,
 431                 .name   = "ptp",
 432         },
 433         [GCB] = {
 434                 .start  = 0x0070000,
 435                 .end    = 0x00701ff,
 436                 .name   = "devcpu_gcb",
 437         },
 438 };
 439
 440 static const struct resource vsc9959_port_io_res[] = {
 441         {
 442                 .start  = 0x0100000,
 443                 .end    = 0x010ffff,
 444                 .name   = "port0",
 445         },
 446         {
 447                 .start  = 0x0110000,
 448                 .end    = 0x011ffff,
 449                 .name   = "port1",
 450         },
 451         {
 452                 .start  = 0x0120000,
 453                 .end    = 0x012ffff,
 454                 .name   = "port2",
 455         },
 456         {
 457                 .start  = 0x0130000,
 458                 .end    = 0x013ffff,
 459                 .name   = "port3",
 460         },
 461         {
 462                 .start  = 0x0140000,
 463                 .end    = 0x014ffff,
 464                 .name   = "port4",
 465         },
 466         {
 467                 .start  = 0x0150000,
 468                 .end    = 0x015ffff,
 469                 .name   = "port5",
 470         },
 471 };
 472
 473 /* Port MAC 0 Internal MDIO bus through which the SerDes acting as an
 474  * SGMII/QSGMII MAC PCS can be found.
 475  */
 476 static const struct resource vsc9959_imdio_res = {
 477         .start          = 0x8030,
 478         .end            = 0x8040,
 479         .name           = "imdio",
 480 };
 481
 482 static const struct reg_field vsc9959_regfields[REGFIELD_MAX] = {
 483         [ANA_ADVLEARN_VLAN_CHK] = REG_FIELD(ANA_ADVLEARN, 6, 6),
 484         [ANA_ADVLEARN_LEARN_MIRROR] = REG_FIELD(ANA_ADVLEARN, 0, 5),
 485         [ANA_ANEVENTS_FLOOD_DISCARD] = REG_FIELD(ANA_ANEVENTS, 30, 30),
 486         [ANA_ANEVENTS_AUTOAGE] = REG_FIELD(ANA_ANEVENTS, 26, 26),
 487         [ANA_ANEVENTS_STORM_DROP] = REG_FIELD(ANA_ANEVENTS, 24, 24),
 488         [ANA_ANEVENTS_LEARN_DROP] = REG_FIELD(ANA_ANEVENTS, 23, 23),
 489         [ANA_ANEVENTS_AGED_ENTRY] = REG_FIELD(ANA_ANEVENTS, 22, 22),
 490         [ANA_ANEVENTS_CPU_LEARN_FAILED] = REG_FIELD(ANA_ANEVENTS, 21, 21),
 491         [ANA_ANEVENTS_AUTO_LEARN_FAILED] = REG_FIELD(ANA_ANEVENTS, 20, 20),
 492         [ANA_ANEVENTS_LEARN_REMOVE] = REG_FIELD(ANA_ANEVENTS, 19, 19),
 493         [ANA_ANEVENTS_AUTO_LEARNED] = REG_FIELD(ANA_ANEVENTS, 18, 18),
 494         [ANA_ANEVENTS_AUTO_MOVED] = REG_FIELD(ANA_ANEVENTS, 17, 17),
 495         [ANA_ANEVENTS_CLASSIFIED_DROP] = REG_FIELD(ANA_ANEVENTS, 15, 15),
 496         [ANA_ANEVENTS_CLASSIFIED_COPY] = REG_FIELD(ANA_ANEVENTS, 14, 14),
 497         [ANA_ANEVENTS_VLAN_DISCARD] = REG_FIELD(ANA_ANEVENTS, 13, 13),
 498         [ANA_ANEVENTS_FWD_DISCARD] = REG_FIELD(ANA_ANEVENTS, 12, 12),
 499         [ANA_ANEVENTS_MULTICAST_FLOOD] = REG_FIELD(ANA_ANEVENTS, 11, 11),
 500         [ANA_ANEVENTS_UNICAST_FLOOD] = REG_FIELD(ANA_ANEVENTS, 10, 10),
 501         [ANA_ANEVENTS_DEST_KNOWN] = REG_FIELD(ANA_ANEVENTS, 9, 9),
 502         [ANA_ANEVENTS_BUCKET3_MATCH] = REG_FIELD(ANA_ANEVENTS, 8, 8),
 503         [ANA_ANEVENTS_BUCKET2_MATCH] = REG_FIELD(ANA_ANEVENTS, 7, 7),
 504         [ANA_ANEVENTS_BUCKET1_MATCH] = REG_FIELD(ANA_ANEVENTS, 6, 6),
 505         [ANA_ANEVENTS_BUCKET0_MATCH] = REG_FIELD(ANA_ANEVENTS, 5, 5),
 506         [ANA_ANEVENTS_CPU_OPERATION] = REG_FIELD(ANA_ANEVENTS, 4, 4),
 507         [ANA_ANEVENTS_DMAC_LOOKUP] = REG_FIELD(ANA_ANEVENTS, 3, 3),
 508         [ANA_ANEVENTS_SMAC_LOOKUP] = REG_FIELD(ANA_ANEVENTS, 2, 2),
 509         [ANA_ANEVENTS_SEQ_GEN_ERR_0] = REG_FIELD(ANA_ANEVENTS, 1, 1),
 510         [ANA_ANEVENTS_SEQ_GEN_ERR_1] = REG_FIELD(ANA_ANEVENTS, 0, 0),
 511         [ANA_TABLES_MACACCESS_B_DOM] = REG_FIELD(ANA_TABLES_MACACCESS, 16, 16),
 512         [ANA_TABLES_MACTINDX_BUCKET] = REG_FIELD(ANA_TABLES_MACTINDX, 11, 12),
 513         [ANA_TABLES_MACTINDX_M_INDEX] = REG_FIELD(ANA_TABLES_MACTINDX, 0, 10),
 514         [SYS_RESET_CFG_CORE_ENA] = REG_FIELD(SYS_RESET_CFG, 0, 0),
 515         [GCB_SOFT_RST_SWC_RST] = REG_FIELD(GCB_SOFT_RST, 0, 0),
 516         /* Replicated per number of ports (7), register size 4 per port */
 517         [QSYS_SWITCH_PORT_MODE_PORT_ENA] = REG_FIELD_ID(QSYS_SWITCH_PORT_MODE, 14, 14, 7, 4),
 518         [QSYS_SWITCH_PORT_MODE_SCH_NEXT_CFG] = REG_FIELD_ID(QSYS_SWITCH_PORT_MODE, 11, 13, 7, 4),
 519         [QSYS_SWITCH_PORT_MODE_YEL_RSRVD] = REG_FIELD_ID(QSYS_SWITCH_PORT_MODE, 10, 10, 7, 4),
 520         [QSYS_SWITCH_PORT_MODE_INGRESS_DROP_MODE] = REG_FIELD_ID(QSYS_SWITCH_PORT_MODE, 9, 9, 7, 4),
 521         [QSYS_SWITCH_PORT_MODE_TX_PFC_ENA] = REG_FIELD_ID(QSYS_SWITCH_PORT_MODE, 1, 8, 7, 4),
 522         [QSYS_SWITCH_PORT_MODE_TX_PFC_MODE] = REG_FIELD_ID(QSYS_SWITCH_PORT_MODE, 0, 0, 7, 4),
 523         [SYS_PORT_MODE_DATA_WO_TS] = REG_FIELD_ID(SYS_PORT_MODE, 5, 6, 7, 4),
 524         [SYS_PORT_MODE_INCL_INJ_HDR] = REG_FIELD_ID(SYS_PORT_MODE, 3, 4, 7, 4),
 525         [SYS_PORT_MODE_INCL_XTR_HDR] = REG_FIELD_ID(SYS_PORT_MODE, 1, 2, 7, 4),
 526         [SYS_PORT_MODE_INCL_HDR_ERR] = REG_FIELD_ID(SYS_PORT_MODE, 0, 0, 7, 4),
 527         [SYS_PAUSE_CFG_PAUSE_START] = REG_FIELD_ID(SYS_PAUSE_CFG, 10, 18, 7, 4),
 528         [SYS_PAUSE_CFG_PAUSE_STOP] = REG_FIELD_ID(SYS_PAUSE_CFG, 1, 9, 7, 4),
 529         [SYS_PAUSE_CFG_PAUSE_ENA] = REG_FIELD_ID(SYS_PAUSE_CFG, 0, 1, 7, 4),
 530 };
 531
 532 static const struct ocelot_stat_layout vsc9959_stats_layout[] = {
 533         { .offset = 0x00,       .name = "rx_octets", },
 534         { .offset = 0x01,       .name = "rx_unicast", },
 535         { .offset = 0x02,       .name = "rx_multicast", },
 536         { .offset = 0x03,       .name = "rx_broadcast", },
 537         { .offset = 0x04,       .name = "rx_shorts", },
 538         { .offset = 0x05,       .name = "rx_fragments", },
 539         { .offset = 0x06,       .name = "rx_jabbers", },
 540         { .offset = 0x07,       .name = "rx_crc_align_errs", },
 541         { .offset = 0x08,       .name = "rx_sym_errs", },
 542         { .offset = 0x09,       .name = "rx_frames_below_65_octets", },
 543         { .offset = 0x0A,       .name = "rx_frames_65_to_127_octets", },
 544         { .offset = 0x0B,       .name = "rx_frames_128_to_255_octets", },
 545         { .offset = 0x0C,       .name = "rx_frames_256_to_511_octets", },
 546         { .offset = 0x0D,       .name = "rx_frames_512_to_1023_octets", },
 547         { .offset = 0x0E,       .name = "rx_frames_1024_to_1526_octets", },
 548         { .offset = 0x0F,       .name = "rx_frames_over_1526_octets", },
 549         { .offset = 0x10,       .name = "rx_pause", },
 550         { .offset = 0x11,       .name = "rx_control", },
 551         { .offset = 0x12,       .name = "rx_longs", },
 552         { .offset = 0x13,       .name = "rx_classified_drops", },
 553         { .offset = 0x14,       .name = "rx_red_prio_0", },
 554         { .offset = 0x15,       .name = "rx_red_prio_1", },
 555         { .offset = 0x16,       .name = "rx_red_prio_2", },
 556         { .offset = 0x17,       .name = "rx_red_prio_3", },
 557         { .offset = 0x18,       .name = "rx_red_prio_4", },
 558         { .offset = 0x19,       .name = "rx_red_prio_5", },
 559         { .offset = 0x1A,       .name = "rx_red_prio_6", },
 560         { .offset = 0x1B,       .name = "rx_red_prio_7", },
 561         { .offset = 0x1C,       .name = "rx_yellow_prio_0", },
 562         { .offset = 0x1D,       .name = "rx_yellow_prio_1", },
 563         { .offset = 0x1E,       .name = "rx_yellow_prio_2", },
 564         { .offset = 0x1F,       .name = "rx_yellow_prio_3", },
 565         { .offset = 0x20,       .name = "rx_yellow_prio_4", },
 566         { .offset = 0x21,       .name = "rx_yellow_prio_5", },
 567         { .offset = 0x22,       .name = "rx_yellow_prio_6", },
 568         { .offset = 0x23,       .name = "rx_yellow_prio_7", },
 569         { .offset = 0x24,       .name = "rx_green_prio_0", },
 570         { .offset = 0x25,       .name = "rx_green_prio_1", },
 571         { .offset = 0x26,       .name = "rx_green_prio_2", },
 572         { .offset = 0x27,       .name = "rx_green_prio_3", },
 573         { .offset = 0x28,       .name = "rx_green_prio_4", },
 574         { .offset = 0x29,       .name = "rx_green_prio_5", },
 575         { .offset = 0x2A,       .name = "rx_green_prio_6", },
 576         { .offset = 0x2B,       .name = "rx_green_prio_7", },
 577         { .offset = 0x80,       .name = "tx_octets", },
 578         { .offset = 0x81,       .name = "tx_unicast", },
 579         { .offset = 0x82,       .name = "tx_multicast", },
 580         { .offset = 0x83,       .name = "tx_broadcast", },
 581         { .offset = 0x84,       .name = "tx_collision", },
 582         { .offset = 0x85,       .name = "tx_drops", },
 583         { .offset = 0x86,       .name = "tx_pause", },
 584         { .offset = 0x87,       .name = "tx_frames_below_65_octets", },
 585         { .offset = 0x88,       .name = "tx_frames_65_to_127_octets", },
 586         { .offset = 0x89,       .name = "tx_frames_128_255_octets", },
 587         { .offset = 0x8B,       .name = "tx_frames_256_511_octets", },
 588         { .offset = 0x8C,       .name = "tx_frames_1024_1526_octets", },
 589         { .offset = 0x8D,       .name = "tx_frames_over_1526_octets", },
 590         { .offset = 0x8E,       .name = "tx_yellow_prio_0", },
 591         { .offset = 0x8F,       .name = "tx_yellow_prio_1", },
 592         { .offset = 0x90,       .name = "tx_yellow_prio_2", },
 593         { .offset = 0x91,       .name = "tx_yellow_prio_3", },
 594         { .offset = 0x92,       .name = "tx_yellow_prio_4", },
 595         { .offset = 0x93,       .name = "tx_yellow_prio_5", },
 596         { .offset = 0x94,       .name = "tx_yellow_prio_6", },
 597         { .offset = 0x95,       .name = "tx_yellow_prio_7", },
 598         { .offset = 0x96,       .name = "tx_green_prio_0", },
 599         { .offset = 0x97,       .name = "tx_green_prio_1", },
 600         { .offset = 0x98,       .name = "tx_green_prio_2", },
 601         { .offset = 0x99,       .name = "tx_green_prio_3", },
 602         { .offset = 0x9A,       .name = "tx_green_prio_4", },
 603         { .offset = 0x9B,       .name = "tx_green_prio_5", },
 604         { .offset = 0x9C,       .name = "tx_green_prio_6", },
 605         { .offset = 0x9D,       .name = "tx_green_prio_7", },
 606         { .offset = 0x9E,       .name = "tx_aged", },
 607         { .offset = 0x100,      .name = "drop_local", },
 608         { .offset = 0x101,      .name = "drop_tail", },
 609         { .offset = 0x102,      .name = "drop_yellow_prio_0", },
 610         { .offset = 0x103,      .name = "drop_yellow_prio_1", },
 611         { .offset = 0x104,      .name = "drop_yellow_prio_2", },
 612         { .offset = 0x105,      .name = "drop_yellow_prio_3", },
 613         { .offset = 0x106,      .name = "drop_yellow_prio_4", },
 614         { .offset = 0x107,      .name = "drop_yellow_prio_5", },
 615         { .offset = 0x108,      .name = "drop_yellow_prio_6", },
 616         { .offset = 0x109,      .name = "drop_yellow_prio_7", },
 617         { .offset = 0x10A,      .name = "drop_green_prio_0", },
 618         { .offset = 0x10B,      .name = "drop_green_prio_1", },
 619         { .offset = 0x10C,      .name = "drop_green_prio_2", },
 620         { .offset = 0x10D,      .name = "drop_green_prio_3", },
 621         { .offset = 0x10E,      .name = "drop_green_prio_4", },
 622         { .offset = 0x10F,      .name = "drop_green_prio_5", },
 623         { .offset = 0x110,      .name = "drop_green_prio_6", },
 624         { .offset = 0x111,      .name = "drop_green_prio_7", },
 625 };
 626
 627 static const struct vcap_field vsc9959_vcap_es0_keys[] = {
 628         [VCAP_ES0_EGR_PORT]                     = {  0,  3},
 629         [VCAP_ES0_IGR_PORT]                     = {  3,  3},
 630         [VCAP_ES0_RSV]                          = {  6,  2},
 631         [VCAP_ES0_L2_MC]                        = {  8,  1},
 632         [VCAP_ES0_L2_BC]                        = {  9,  1},
 633         [VCAP_ES0_VID]                          = { 10, 12},
 634         [VCAP_ES0_DP]                           = { 22,  1},
 635         [VCAP_ES0_PCP]                          = { 23,  3},
 636 };
 637
 638 static const struct vcap_field vsc9959_vcap_es0_actions[] = {
 639         [VCAP_ES0_ACT_PUSH_OUTER_TAG]           = {  0,  2},
 640         [VCAP_ES0_ACT_PUSH_INNER_TAG]           = {  2,  1},
 641         [VCAP_ES0_ACT_TAG_A_TPID_SEL]           = {  3,  2},
 642         [VCAP_ES0_ACT_TAG_A_VID_SEL]            = {  5,  1},
 643         [VCAP_ES0_ACT_TAG_A_PCP_SEL]            = {  6,  2},
 644         [VCAP_ES0_ACT_TAG_A_DEI_SEL]            = {  8,  2},
 645         [VCAP_ES0_ACT_TAG_B_TPID_SEL]           = { 10,  2},
 646         [VCAP_ES0_ACT_TAG_B_VID_SEL]            = { 12,  1},
 647         [VCAP_ES0_ACT_TAG_B_PCP_SEL]            = { 13,  2},
 648         [VCAP_ES0_ACT_TAG_B_DEI_SEL]            = { 15,  2},
 649         [VCAP_ES0_ACT_VID_A_VAL]                = { 17, 12},
 650         [VCAP_ES0_ACT_PCP_A_VAL]                = { 29,  3},
 651         [VCAP_ES0_ACT_DEI_A_VAL]                = { 32,  1},
 652         [VCAP_ES0_ACT_VID_B_VAL]                = { 33, 12},
 653         [VCAP_ES0_ACT_PCP_B_VAL]                = { 45,  3},
 654         [VCAP_ES0_ACT_DEI_B_VAL]                = { 48,  1},
 655         [VCAP_ES0_ACT_RSV]                      = { 49, 23},
 656         [VCAP_ES0_ACT_HIT_STICKY]               = { 72,  1},
 657 };
 658
 659 static const struct vcap_field vsc9959_vcap_is1_keys[] = {
 660         [VCAP_IS1_HK_TYPE]                      = {  0,   1},
 661         [VCAP_IS1_HK_LOOKUP]                    = {  1,   2},
 662         [VCAP_IS1_HK_IGR_PORT_MASK]             = {  3,   7},
 663         [VCAP_IS1_HK_RSV]                       = { 10,   9},
 664         [VCAP_IS1_HK_OAM_Y1731]                 = { 19,   1},
 665         [VCAP_IS1_HK_L2_MC]                     = { 20,   1},
 666         [VCAP_IS1_HK_L2_BC]                     = { 21,   1},
 667         [VCAP_IS1_HK_IP_MC]                     = { 22,   1},
 668         [VCAP_IS1_HK_VLAN_TAGGED]               = { 23,   1},
 669         [VCAP_IS1_HK_VLAN_DBL_TAGGED]           = { 24,   1},
 670         [VCAP_IS1_HK_TPID]                      = { 25,   1},
 671         [VCAP_IS1_HK_VID]                       = { 26,  12},
 672         [VCAP_IS1_HK_DEI]                       = { 38,   1},
 673         [VCAP_IS1_HK_PCP]                       = { 39,   3},
 674         /* Specific Fields for IS1 Half Key S1_NORMAL */
 675         [VCAP_IS1_HK_L2_SMAC]                   = { 42,  48},
 676         [VCAP_IS1_HK_ETYPE_LEN]                 = { 90,   1},
 677         [VCAP_IS1_HK_ETYPE]                     = { 91,  16},
 678         [VCAP_IS1_HK_IP_SNAP]                   = {107,   1},
 679         [VCAP_IS1_HK_IP4]                       = {108,   1},
 680         /* Layer-3 Information */
 681         [VCAP_IS1_HK_L3_FRAGMENT]               = {109,   1},
 682         [VCAP_IS1_HK_L3_FRAG_OFS_GT0]           = {110,   1},
 683         [VCAP_IS1_HK_L3_OPTIONS]                = {111,   1},
 684         [VCAP_IS1_HK_L3_DSCP]                   = {112,   6},
 685         [VCAP_IS1_HK_L3_IP4_SIP]                = {118,  32},
 686         /* Layer-4 Information */
 687         [VCAP_IS1_HK_TCP_UDP]                   = {150,   1},
 688         [VCAP_IS1_HK_TCP]                       = {151,   1},
 689         [VCAP_IS1_HK_L4_SPORT]                  = {152,  16},
 690         [VCAP_IS1_HK_L4_RNG]                    = {168,   8},
 691         /* Specific Fields for IS1 Half Key S1_5TUPLE_IP4 */
 692         [VCAP_IS1_HK_IP4_INNER_TPID]            = { 42,   1},
 693         [VCAP_IS1_HK_IP4_INNER_VID]             = { 43,  12},
 694         [VCAP_IS1_HK_IP4_INNER_DEI]             = { 55,   1},
 695         [VCAP_IS1_HK_IP4_INNER_PCP]             = { 56,   3},
 696         [VCAP_IS1_HK_IP4_IP4]                   = { 59,   1},
 697         [VCAP_IS1_HK_IP4_L3_FRAGMENT]           = { 60,   1},
 698         [VCAP_IS1_HK_IP4_L3_FRAG_OFS_GT0]       = { 61,   1},
 699         [VCAP_IS1_HK_IP4_L3_OPTIONS]            = { 62,   1},
 700         [VCAP_IS1_HK_IP4_L3_DSCP]               = { 63,   6},
 701         [VCAP_IS1_HK_IP4_L3_IP4_DIP]            = { 69,  32},
 702         [VCAP_IS1_HK_IP4_L3_IP4_SIP]            = {101,  32},
 703         [VCAP_IS1_HK_IP4_L3_PROTO]              = {133,   8},
 704         [VCAP_IS1_HK_IP4_TCP_UDP]               = {141,   1},
 705         [VCAP_IS1_HK_IP4_TCP]                   = {142,   1},
 706         [VCAP_IS1_HK_IP4_L4_RNG]                = {143,   8},
 707         [VCAP_IS1_HK_IP4_IP_PAYLOAD_S1_5TUPLE]  = {151,  32},
 708 };
 709
 710 static const struct vcap_field vsc9959_vcap_is1_actions[] = {
 711         [VCAP_IS1_ACT_DSCP_ENA]                 = {  0,  1},
 712         [VCAP_IS1_ACT_DSCP_VAL]                 = {  1,  6},
 713         [VCAP_IS1_ACT_QOS_ENA]                  = {  7,  1},
 714         [VCAP_IS1_ACT_QOS_VAL]                  = {  8,  3},
 715         [VCAP_IS1_ACT_DP_ENA]                   = { 11,  1},
 716         [VCAP_IS1_ACT_DP_VAL]                   = { 12,  1},
 717         [VCAP_IS1_ACT_PAG_OVERRIDE_MASK]        = { 13,  8},
 718         [VCAP_IS1_ACT_PAG_VAL]                  = { 21,  8},
 719         [VCAP_IS1_ACT_RSV]                      = { 29,  9},
 720         /* The fields below are incorrectly shifted by 2 in the manual */
 721         [VCAP_IS1_ACT_VID_REPLACE_ENA]          = { 38,  1},
 722         [VCAP_IS1_ACT_VID_ADD_VAL]              = { 39, 12},
 723         [VCAP_IS1_ACT_FID_SEL]                  = { 51,  2},
 724         [VCAP_IS1_ACT_FID_VAL]                  = { 53, 13},
 725         [VCAP_IS1_ACT_PCP_DEI_ENA]              = { 66,  1},
 726         [VCAP_IS1_ACT_PCP_VAL]                  = { 67,  3},
 727         [VCAP_IS1_ACT_DEI_VAL]                  = { 70,  1},
 728         [VCAP_IS1_ACT_VLAN_POP_CNT_ENA]         = { 71,  1},
 729         [VCAP_IS1_ACT_VLAN_POP_CNT]             = { 72,  2},
 730         [VCAP_IS1_ACT_CUSTOM_ACE_TYPE_ENA]      = { 74,  4},
 731         [VCAP_IS1_ACT_HIT_STICKY]               = { 78,  1},
 732 };
 733
 734 static struct vcap_field vsc9959_vcap_is2_keys[] = {
 735         /* Common: 41 bits */
 736         [VCAP_IS2_TYPE]                         = {  0,   4},
 737         [VCAP_IS2_HK_FIRST]                     = {  4,   1},
 738         [VCAP_IS2_HK_PAG]                       = {  5,   8},
 739         [VCAP_IS2_HK_IGR_PORT_MASK]             = { 13,   7},
 740         [VCAP_IS2_HK_RSV2]                      = { 20,   1},
 741         [VCAP_IS2_HK_HOST_MATCH]                = { 21,   1},
 742         [VCAP_IS2_HK_L2_MC]                     = { 22,   1},
 743         [VCAP_IS2_HK_L2_BC]                     = { 23,   1},
 744         [VCAP_IS2_HK_VLAN_TAGGED]               = { 24,   1},
 745         [VCAP_IS2_HK_VID]                       = { 25,  12},
 746         [VCAP_IS2_HK_DEI]                       = { 37,   1},
 747         [VCAP_IS2_HK_PCP]                       = { 38,   3},
 748         /* MAC_ETYPE / MAC_LLC / MAC_SNAP / OAM common */
 749         [VCAP_IS2_HK_L2_DMAC]                   = { 41,  48},
 750         [VCAP_IS2_HK_L2_SMAC]                   = { 89,  48},
 751         /* MAC_ETYPE (TYPE=000) */
 752         [VCAP_IS2_HK_MAC_ETYPE_ETYPE]           = {137,  16},
 753         [VCAP_IS2_HK_MAC_ETYPE_L2_PAYLOAD0]     = {153,  16},
 754         [VCAP_IS2_HK_MAC_ETYPE_L2_PAYLOAD1]     = {169,   8},
 755         [VCAP_IS2_HK_MAC_ETYPE_L2_PAYLOAD2]     = {177,   3},
 756         /* MAC_LLC (TYPE=001) */
 757         [VCAP_IS2_HK_MAC_LLC_L2_LLC]            = {137,  40},
 758         /* MAC_SNAP (TYPE=010) */
 759         [VCAP_IS2_HK_MAC_SNAP_L2_SNAP]          = {137,  40},
 760         /* MAC_ARP (TYPE=011) */
 761         [VCAP_IS2_HK_MAC_ARP_SMAC]              = { 41,  48},
 762         [VCAP_IS2_HK_MAC_ARP_ADDR_SPACE_OK]     = { 89,   1},
 763         [VCAP_IS2_HK_MAC_ARP_PROTO_SPACE_OK]    = { 90,   1},
 764         [VCAP_IS2_HK_MAC_ARP_LEN_OK]            = { 91,   1},
 765         [VCAP_IS2_HK_MAC_ARP_TARGET_MATCH]      = { 92,   1},
 766         [VCAP_IS2_HK_MAC_ARP_SENDER_MATCH]      = { 93,   1},
 767         [VCAP_IS2_HK_MAC_ARP_OPCODE_UNKNOWN]    = { 94,   1},
 768         [VCAP_IS2_HK_MAC_ARP_OPCODE]            = { 95,   2},
 769         [VCAP_IS2_HK_MAC_ARP_L3_IP4_DIP]        = { 97,  32},
 770         [VCAP_IS2_HK_MAC_ARP_L3_IP4_SIP]        = {129,  32},
 771         [VCAP_IS2_HK_MAC_ARP_DIP_EQ_SIP]        = {161,   1},
 772         /* IP4_TCP_UDP / IP4_OTHER common */
 773         [VCAP_IS2_HK_IP4]                       = { 41,   1},
 774         [VCAP_IS2_HK_L3_FRAGMENT]               = { 42,   1},
 775         [VCAP_IS2_HK_L3_FRAG_OFS_GT0]           = { 43,   1},
 776         [VCAP_IS2_HK_L3_OPTIONS]                = { 44,   1},
 777         [VCAP_IS2_HK_IP4_L3_TTL_GT0]            = { 45,   1},
 778         [VCAP_IS2_HK_L3_TOS]                    = { 46,   8},
 779         [VCAP_IS2_HK_L3_IP4_DIP]                = { 54,  32},
 780         [VCAP_IS2_HK_L3_IP4_SIP]                = { 86,  32},
 781         [VCAP_IS2_HK_DIP_EQ_SIP]                = {118,   1},
 782         /* IP4_TCP_UDP (TYPE=100) */
 783         [VCAP_IS2_HK_TCP]                       = {119,   1},
 784         [VCAP_IS2_HK_L4_DPORT]                  = {120,  16},
 785         [VCAP_IS2_HK_L4_SPORT]                  = {136,  16},
 786         [VCAP_IS2_HK_L4_RNG]                    = {152,   8},
 787         [VCAP_IS2_HK_L4_SPORT_EQ_DPORT]         = {160,   1},
 788         [VCAP_IS2_HK_L4_SEQUENCE_EQ0]           = {161,   1},
 789         [VCAP_IS2_HK_L4_FIN]                    = {162,   1},
 790         [VCAP_IS2_HK_L4_SYN]                    = {163,   1},
 791         [VCAP_IS2_HK_L4_RST]                    = {164,   1},
 792         [VCAP_IS2_HK_L4_PSH]                    = {165,   1},
 793         [VCAP_IS2_HK_L4_ACK]                    = {166,   1},
 794         [VCAP_IS2_HK_L4_URG]                    = {167,   1},
 795         [VCAP_IS2_HK_L4_1588_DOM]               = {168,   8},
 796         [VCAP_IS2_HK_L4_1588_VER]               = {176,   4},
 797         /* IP4_OTHER (TYPE=101) */
 798         [VCAP_IS2_HK_IP4_L3_PROTO]              = {119,   8},
 799         [VCAP_IS2_HK_L3_PAYLOAD]                = {127,  56},
 800         /* IP6_STD (TYPE=110) */
 801         [VCAP_IS2_HK_IP6_L3_TTL_GT0]            = { 41,   1},
 802         [VCAP_IS2_HK_L3_IP6_SIP]                = { 42, 128},
 803         [VCAP_IS2_HK_IP6_L3_PROTO]              = {170,   8},
 804         /* OAM (TYPE=111) */
 805         [VCAP_IS2_HK_OAM_MEL_FLAGS]             = {137,   7},
 806         [VCAP_IS2_HK_OAM_VER]                   = {144,   5},
 807         [VCAP_IS2_HK_OAM_OPCODE]                = {149,   8},
 808         [VCAP_IS2_HK_OAM_FLAGS]                 = {157,   8},
 809         [VCAP_IS2_HK_OAM_MEPID]                 = {165,  16},
 810         [VCAP_IS2_HK_OAM_CCM_CNTS_EQ0]          = {181,   1},
 811         [VCAP_IS2_HK_OAM_IS_Y1731]              = {182,   1},
 812 };
 813
 814 static struct vcap_field vsc9959_vcap_is2_actions[] = {
 815         [VCAP_IS2_ACT_HIT_ME_ONCE]              = {  0,  1},
 816         [VCAP_IS2_ACT_CPU_COPY_ENA]             = {  1,  1},
 817         [VCAP_IS2_ACT_CPU_QU_NUM]               = {  2,  3},
 818         [VCAP_IS2_ACT_MASK_MODE]                = {  5,  2},
 819         [VCAP_IS2_ACT_MIRROR_ENA]               = {  7,  1},
 820         [VCAP_IS2_ACT_LRN_DIS]                  = {  8,  1},
 821         [VCAP_IS2_ACT_POLICE_ENA]               = {  9,  1},
 822         [VCAP_IS2_ACT_POLICE_IDX]               = { 10,  9},
 823         [VCAP_IS2_ACT_POLICE_VCAP_ONLY]         = { 19,  1},
 824         [VCAP_IS2_ACT_PORT_MASK]                = { 20,  6},
 825         [VCAP_IS2_ACT_REW_OP]                   = { 26,  9},
 826         [VCAP_IS2_ACT_SMAC_REPLACE_ENA]         = { 35,  1},
 827         [VCAP_IS2_ACT_RSV]                      = { 36,  2},
 828         [VCAP_IS2_ACT_ACL_ID]                   = { 38,  6},
 829         [VCAP_IS2_ACT_HIT_CNT]                  = { 44, 32},
 830 };
 831
 832 static struct vcap_props vsc9959_vcap_props[] = {
 833         [VCAP_ES0] = {
 834                 .action_type_width = 0,
 835                 .action_table = {
 836                         [ES0_ACTION_TYPE_NORMAL] = {
 837                                 .width = 72, /* HIT_STICKY not included */
 838                                 .count = 1,
 839                         },
 840                 },
 841                 .target = S0,
 842                 .keys = vsc9959_vcap_es0_keys,
 843                 .actions = vsc9959_vcap_es0_actions,
 844         },
 845         [VCAP_IS1] = {
 846                 .action_type_width = 0,
 847                 .action_table = {
 848                         [IS1_ACTION_TYPE_NORMAL] = {
 849                                 .width = 78, /* HIT_STICKY not included */
 850                                 .count = 4,
 851                         },
 852                 },
 853                 .target = S1,
 854                 .keys = vsc9959_vcap_is1_keys,
 855                 .actions = vsc9959_vcap_is1_actions,
 856         },
 857         [VCAP_IS2] = {
 858                 .action_type_width = 1,
 859                 .action_table = {
 860                         [IS2_ACTION_TYPE_NORMAL] = {
 861                                 .width = 44,
 862                                 .count = 2
 863                         },
 864                         [IS2_ACTION_TYPE_SMAC_SIP] = {
 865                                 .width = 6,
 866                                 .count = 4
 867                         },
 868                 },
 869                 .target = S2,
 870                 .keys = vsc9959_vcap_is2_keys,
 871                 .actions = vsc9959_vcap_is2_actions,
 872         },
 873 };
 874
 875 static const struct ptp_clock_info vsc9959_ptp_caps = {
 876         .owner          = THIS_MODULE,
 877         .name           = "felix ptp",
 878         .max_adj        = 0x7fffffff,
 879         .n_alarm        = 0,
 880         .n_ext_ts       = 0,
 881         .n_per_out      = OCELOT_PTP_PINS_NUM,
 882         .n_pins         = OCELOT_PTP_PINS_NUM,
 883         .pps            = 0,
 884         .gettime64      = ocelot_ptp_gettime64,
 885         .settime64      = ocelot_ptp_settime64,
 886         .adjtime        = ocelot_ptp_adjtime,
 887         .adjfine        = ocelot_ptp_adjfine,
 888         .verify         = ocelot_ptp_verify,
 889         .enable         = ocelot_ptp_enable,
 890 };
 891
 892 #define VSC9959_INIT_TIMEOUT                    50000
 893 #define VSC9959_GCB_RST_SLEEP                   100
 894 #define VSC9959_SYS_RAMINIT_SLEEP               80
 895
 896 static int vsc9959_gcb_soft_rst_status(struct ocelot *ocelot)
 897 {
 898         int val;
 899
 900         ocelot_field_read(ocelot, GCB_SOFT_RST_SWC_RST, &val);
 901
 902         return val;
 903 }
 904
 905 static int vsc9959_sys_ram_init_status(struct ocelot *ocelot)
 906 {
 907         return ocelot_read(ocelot, SYS_RAM_INIT);
 908 }
 909
 910 /* CORE_ENA is in SYS:SYSTEM:RESET_CFG
 911  * RAM_INIT is in SYS:RAM_CTRL:RAM_INIT
 912  */
 913 static int vsc9959_reset(struct ocelot *ocelot)
 914 {
 915         int val, err;
 916
 917         /* soft-reset the switch core */
 918         ocelot_field_write(ocelot, GCB_SOFT_RST_SWC_RST, 1);
 919
 920         err = readx_poll_timeout(vsc9959_gcb_soft_rst_status, ocelot, val, !val,
 921                                  VSC9959_GCB_RST_SLEEP, VSC9959_INIT_TIMEOUT);
 922         if (err) {
 923                 dev_err(ocelot->dev, "timeout: switch core reset\n");
 924                 return err;
 925         }
 926
 927         /* initialize switch mem ~40us */
 928         ocelot_write(ocelot, SYS_RAM_INIT_RAM_INIT, SYS_RAM_INIT);
 929         err = readx_poll_timeout(vsc9959_sys_ram_init_status, ocelot, val, !val,
 930                                  VSC9959_SYS_RAMINIT_SLEEP,
 931                                  VSC9959_INIT_TIMEOUT);
 932         if (err) {
 933                 dev_err(ocelot->dev, "timeout: switch sram init\n");
 934                 return err;
 935         }
 936
 937         /* enable switch core */
 938         ocelot_field_write(ocelot, SYS_RESET_CFG_CORE_ENA, 1);
 939
 940         return 0;
 941 }
 942
 943 static void vsc9959_phylink_validate(struct ocelot *ocelot, int port,
 944                                      unsigned long *supported,
 945                                      struct phylink_link_state *state)
 946 {
 947         struct ocelot_port *ocelot_port = ocelot->ports[port];
 948         __ETHTOOL_DECLARE_LINK_MODE_MASK(mask) = { 0, };
 949
 950         if (state->interface != PHY_INTERFACE_MODE_NA &&
 951             state->interface != ocelot_port->phy_mode) {
 952                 linkmode_zero(supported);
 953                 return;
 954         }
 955
 956         phylink_set_port_modes(mask);
 957         phylink_set(mask, Autoneg);
 958         phylink_set(mask, Pause);
 959         phylink_set(mask, Asym_Pause);
 960         phylink_set(mask, 10baseT_Half);
 961         phylink_set(mask, 10baseT_Full);
 962         phylink_set(mask, 100baseT_Half);
 963         phylink_set(mask, 100baseT_Full);
 964         phylink_set(mask, 1000baseT_Half);
 965         phylink_set(mask, 1000baseT_Full);
 966
 967         if (state->interface == PHY_INTERFACE_MODE_INTERNAL ||
 968             state->interface == PHY_INTERFACE_MODE_2500BASEX ||
 969             state->interface == PHY_INTERFACE_MODE_USXGMII) {
 970                 phylink_set(mask, 2500baseT_Full);
 971                 phylink_set(mask, 2500baseX_Full);
 972         }
 973
 974         linkmode_and(supported, supported, mask);
 975         linkmode_and(state->advertising, state->advertising, mask);
 976 }
 977
 978 static int vsc9959_prevalidate_phy_mode(struct ocelot *ocelot, int port,
 979                                         phy_interface_t phy_mode)
 980 {
 981         switch (phy_mode) {
 982         case PHY_INTERFACE_MODE_INTERNAL:
 983                 if (port != 4 && port != 5)
 984                         return -ENOTSUPP;
 985                 return 0;
 986         case PHY_INTERFACE_MODE_SGMII:
 987         case PHY_INTERFACE_MODE_QSGMII:
 988         case PHY_INTERFACE_MODE_USXGMII:
 989         case PHY_INTERFACE_MODE_2500BASEX:
 990                 /* Not supported on internal to-CPU ports */
 991                 if (port == 4 || port == 5)
 992                         return -ENOTSUPP;
 993                 return 0;
 994         default:
 995                 return -ENOTSUPP;
 996         }
 997 }
 998
 999 /* Watermark encode
1000  * Bit 8:   Unit; 0:1, 1:16
1001  * Bit 7-0: Value to be multiplied with unit
1002  */
1003 static u16 vsc9959_wm_enc(u16 value)
1004 {
1005         WARN_ON(value >= 16 * BIT(8));
1006
1007         if (value >= BIT(8))
1008                 return BIT(8) | (value / 16);
1009
1010         return value;
1011 }
1012
1013 static u16 vsc9959_wm_dec(u16 wm)
1014 {
1015         WARN_ON(wm & ~GENMASK(8, 0));
1016
1017         if (wm & BIT(8))
1018                 return (wm & GENMASK(7, 0)) * 16;
1019
1020         return wm;
1021 }
1022
1023 static void vsc9959_wm_stat(u32 val, u32 *inuse, u32 *maxuse)
1024 {
1025         *inuse = (val & GENMASK(23, 12)) >> 12;
1026         *maxuse = val & GENMASK(11, 0);
1027 }
1028
1029 static int vsc9959_mdio_bus_alloc(struct ocelot *ocelot)
1030 {
1031         struct felix *felix = ocelot_to_felix(ocelot);
1032         struct enetc_mdio_priv *mdio_priv;
1033         struct device *dev = ocelot->dev;
1034         void __iomem *imdio_regs;
1035         struct resource res;
1036         struct enetc_hw *hw;
1037         struct mii_bus *bus;
1038         int port;
1039         int rc;
1040
1041         felix->pcs = devm_kcalloc(dev, felix->info->num_ports,
1042                                   sizeof(struct phylink_pcs *),
1043                                   GFP_KERNEL);
1044         if (!felix->pcs) {
1045                 dev_err(dev, "failed to allocate array for PCS PHYs\n");
1046                 return -ENOMEM;
1047         }
1048
1049         memcpy(&res, felix->info->imdio_res, sizeof(res));
1050         res.flags = IORESOURCE_MEM;
1051         res.start += felix->imdio_base;
1052         res.end += felix->imdio_base;
1053
1054         imdio_regs = devm_ioremap_resource(dev, &res);
1055         if (IS_ERR(imdio_regs))
1056                 return PTR_ERR(imdio_regs);
1057
1058         hw = enetc_hw_alloc(dev, imdio_regs);
1059         if (IS_ERR(hw)) {
1060                 dev_err(dev, "failed to allocate ENETC HW structure\n");
1061                 return PTR_ERR(hw);
1062         }
1063
1064         bus = devm_mdiobus_alloc_size(dev, sizeof(*mdio_priv));
1065         if (!bus)
1066                 return -ENOMEM;
1067
1068         bus->name = "VSC9959 internal MDIO bus";
1069         bus->read = enetc_mdio_read;
1070         bus->write = enetc_mdio_write;
1071         bus->parent = dev;
1072         mdio_priv = bus->priv;
1073         mdio_priv->hw = hw;
1074         /* This gets added to imdio_regs, which already maps addresses
1075          * starting with the proper offset.
1076          */
1077         mdio_priv->mdio_base = 0;
1078         snprintf(bus->id, MII_BUS_ID_SIZE, "%s-imdio", dev_name(dev));
1079
1080         /* Needed in order to initialize the bus mutex lock */
1081         rc = mdiobus_register(bus);
1082         if (rc < 0) {
1083                 dev_err(dev, "failed to register MDIO bus\n");
1084                 return rc;
1085         }
1086
1087         felix->imdio = bus;
1088
1089         for (port = 0; port < felix->info->num_ports; port++) {
1090                 struct ocelot_port *ocelot_port = ocelot->ports[port];
1091                 struct phylink_pcs *phylink_pcs;
1092                 struct mdio_device *mdio_device;
1093
1094                 if (dsa_is_unused_port(felix->ds, port))
1095                         continue;
1096
1097                 if (ocelot_port->phy_mode == PHY_INTERFACE_MODE_INTERNAL)
1098                         continue;
1099
1100                 mdio_device = mdio_device_create(felix->imdio, port);
1101                 if (IS_ERR(mdio_device))
1102                         continue;
1103
1104                 phylink_pcs = lynx_pcs_create(mdio_device);
1105                 if (!phylink_pcs) {
1106                         mdio_device_free(mdio_device);
1107                         continue;
1108                 }
1109
1110                 felix->pcs[port] = phylink_pcs;
1111
1112                 dev_info(dev, "Found PCS at internal MDIO address %d\n", port);
1113         }
1114
1115         return 0;
1116 }
1117
1118 static void vsc9959_mdio_bus_free(struct ocelot *ocelot)
1119 {
1120         struct felix *felix = ocelot_to_felix(ocelot);
1121         int port;
1122
1123         for (port = 0; port < ocelot->num_phys_ports; port++) {
1124                 struct phylink_pcs *phylink_pcs = felix->pcs[port];
1125                 struct mdio_device *mdio_device;
1126
1127                 if (!phylink_pcs)
1128                         continue;
1129
1130                 mdio_device = lynx_get_mdio_device(phylink_pcs);
1131                 mdio_device_free(mdio_device);
1132                 lynx_pcs_destroy(phylink_pcs);
1133         }
1134         mdiobus_unregister(felix->imdio);
1135 }
1136
1137 static void vsc9959_sched_speed_set(struct ocelot *ocelot, int port,
1138                                     u32 speed)
1139 {
1140         u8 tas_speed;
1141
1142         switch (speed) {
1143         case SPEED_10:
1144                 tas_speed = OCELOT_SPEED_10;
1145                 break;
1146         case SPEED_100:
1147                 tas_speed = OCELOT_SPEED_100;
1148                 break;
1149         case SPEED_1000:
1150                 tas_speed = OCELOT_SPEED_1000;
1151                 break;
1152         case SPEED_2500:
1153                 tas_speed = OCELOT_SPEED_2500;
1154                 break;
1155         default:
1156                 tas_speed = OCELOT_SPEED_1000;
1157                 break;
1158         }
1159
1160         ocelot_rmw_rix(ocelot,
1161                        QSYS_TAG_CONFIG_LINK_SPEED(tas_speed),
1162                        QSYS_TAG_CONFIG_LINK_SPEED_M,
1163                        QSYS_TAG_CONFIG, port);
1164 }
1165
1166 static void vsc9959_new_base_time(struct ocelot *ocelot, ktime_t base_time,
1167                                   u64 cycle_time,
1168                                   struct timespec64 *new_base_ts)
1169 {
1170         struct timespec64 ts;
1171         ktime_t new_base_time;
1172         ktime_t current_time;
1173
1174         ocelot_ptp_gettime64(&ocelot->ptp_info, &ts);
1175         current_time = timespec64_to_ktime(ts);
1176         new_base_time = base_time;
1177
1178         if (base_time < current_time) {
1179                 u64 nr_of_cycles = current_time - base_time;
1180
1181                 do_div(nr_of_cycles, cycle_time);
1182                 new_base_time += cycle_time * (nr_of_cycles + 1);
1183         }
1184
1185         *new_base_ts = ktime_to_timespec64(new_base_time);
1186 }
1187
1188 static u32 vsc9959_tas_read_cfg_status(struct ocelot *ocelot)
1189 {
1190         return ocelot_read(ocelot, QSYS_TAS_PARAM_CFG_CTRL);
1191 }
1192
1193 static void vsc9959_tas_gcl_set(struct ocelot *ocelot, const u32 gcl_ix,
1194                                 struct tc_taprio_sched_entry *entry)
1195 {
1196         ocelot_write(ocelot,
1197                      QSYS_GCL_CFG_REG_1_GCL_ENTRY_NUM(gcl_ix) |
1198                      QSYS_GCL_CFG_REG_1_GATE_STATE(entry->gate_mask),
1199                      QSYS_GCL_CFG_REG_1);
1200         ocelot_write(ocelot, entry->interval, QSYS_GCL_CFG_REG_2);
1201 }
1202
1203 static int vsc9959_qos_port_tas_set(struct ocelot *ocelot, int port,
1204                                     struct tc_taprio_qopt_offload *taprio)
1205 {
1206         struct timespec64 base_ts;
1207         int ret, i;
1208         u32 val;
1209
1210         if (!taprio->enable) {
1211                 ocelot_rmw_rix(ocelot,
1212                                QSYS_TAG_CONFIG_INIT_GATE_STATE(0xFF),
1213                                QSYS_TAG_CONFIG_ENABLE |
1214                                QSYS_TAG_CONFIG_INIT_GATE_STATE_M,
1215                                QSYS_TAG_CONFIG, port);
1216
1217                 return 0;
1218         }
1219
1220         if (taprio->cycle_time > NSEC_PER_SEC ||
1221             taprio->cycle_time_extension >= NSEC_PER_SEC)
1222                 return -EINVAL;
1223
1224         if (taprio->num_entries > VSC9959_TAS_GCL_ENTRY_MAX)
1225                 return -ERANGE;
1226
1227         /* Enable guard band. The switch will schedule frames without taking
1228          * their length into account. Thus we'll always need to enable the
1229          * guard band which reserves the time of a maximum sized frame at the
1230          * end of the time window.
1231          *
1232          * Although the ALWAYS_GUARD_BAND_SCH_Q bit is global for all ports, we
1233          * need to set PORT_NUM, because subsequent writes to PARAM_CFG_REG_n
1234          * operate on the port number.
1235          */
1236         ocelot_rmw(ocelot, QSYS_TAS_PARAM_CFG_CTRL_PORT_NUM(port) |
1237                    QSYS_TAS_PARAM_CFG_CTRL_ALWAYS_GUARD_BAND_SCH_Q,
1238                    QSYS_TAS_PARAM_CFG_CTRL_PORT_NUM_M |
1239                    QSYS_TAS_PARAM_CFG_CTRL_ALWAYS_GUARD_BAND_SCH_Q,
1240                    QSYS_TAS_PARAM_CFG_CTRL);
1241
1242         /* Hardware errata -  Admin config could not be overwritten if
1243          * config is pending, need reset the TAS module
1244          */
1245         val = ocelot_read(ocelot, QSYS_PARAM_STATUS_REG_8);
1246         if (val & QSYS_PARAM_STATUS_REG_8_CONFIG_PENDING)
1247                 return  -EBUSY;
1248
1249         ocelot_rmw_rix(ocelot,
1250                        QSYS_TAG_CONFIG_ENABLE |
1251                        QSYS_TAG_CONFIG_INIT_GATE_STATE(0xFF) |
1252                        QSYS_TAG_CONFIG_SCH_TRAFFIC_QUEUES(0xFF),
1253                        QSYS_TAG_CONFIG_ENABLE |
1254                        QSYS_TAG_CONFIG_INIT_GATE_STATE_M |
1255                        QSYS_TAG_CONFIG_SCH_TRAFFIC_QUEUES_M,
1256                        QSYS_TAG_CONFIG, port);
1257
1258         vsc9959_new_base_time(ocelot, taprio->base_time,
1259                               taprio->cycle_time, &base_ts);
1260         ocelot_write(ocelot, base_ts.tv_nsec, QSYS_PARAM_CFG_REG_1);
1261         ocelot_write(ocelot, lower_32_bits(base_ts.tv_sec), QSYS_PARAM_CFG_REG_2);
1262         val = upper_32_bits(base_ts.tv_sec);
1263         ocelot_write(ocelot,
1264                      QSYS_PARAM_CFG_REG_3_BASE_TIME_SEC_MSB(val) |
1265                      QSYS_PARAM_CFG_REG_3_LIST_LENGTH(taprio->num_entries),
1266                      QSYS_PARAM_CFG_REG_3);
1267         ocelot_write(ocelot, taprio->cycle_time, QSYS_PARAM_CFG_REG_4);
1268         ocelot_write(ocelot, taprio->cycle_time_extension, QSYS_PARAM_CFG_REG_5);
1269
1270         for (i = 0; i < taprio->num_entries; i++)
1271                 vsc9959_tas_gcl_set(ocelot, i, &taprio->entries[i]);
1272
1273         ocelot_rmw(ocelot, QSYS_TAS_PARAM_CFG_CTRL_CONFIG_CHANGE,
1274                    QSYS_TAS_PARAM_CFG_CTRL_CONFIG_CHANGE,
1275                    QSYS_TAS_PARAM_CFG_CTRL);
1276
1277         ret = readx_poll_timeout(vsc9959_tas_read_cfg_status, ocelot, val,
1278                                  !(val & QSYS_TAS_PARAM_CFG_CTRL_CONFIG_CHANGE),
1279                                  10, 100000);
1280
1281         return ret;
1282 }
1283
1284 static int vsc9959_qos_port_cbs_set(struct dsa_switch *ds, int port,
1285                                     struct tc_cbs_qopt_offload *cbs_qopt)
1286 {
1287         struct ocelot *ocelot = ds->priv;
1288         int port_ix = port * 8 + cbs_qopt->queue;
1289         u32 rate, burst;
1290
1291         if (cbs_qopt->queue >= ds->num_tx_queues)
1292                 return -EINVAL;
1293
1294         if (!cbs_qopt->enable) {
1295                 ocelot_write_gix(ocelot, QSYS_CIR_CFG_CIR_RATE(0) |
1296                                  QSYS_CIR_CFG_CIR_BURST(0),
1297                                  QSYS_CIR_CFG, port_ix);
1298
1299                 ocelot_rmw_gix(ocelot, 0, QSYS_SE_CFG_SE_AVB_ENA,
1300                                QSYS_SE_CFG, port_ix);
1301
1302                 return 0;
1303         }
1304
1305         /* Rate unit is 100 kbps */
1306         rate = DIV_ROUND_UP(cbs_qopt->idleslope, 100);
1307         /* Avoid using zero rate */
1308         rate = clamp_t(u32, rate, 1, GENMASK(14, 0));
1309         /* Burst unit is 4kB */
1310         burst = DIV_ROUND_UP(cbs_qopt->hicredit, 4096);
1311         /* Avoid using zero burst size */
1312         burst = clamp_t(u32, burst, 1, GENMASK(5, 0));
1313         ocelot_write_gix(ocelot,
1314                          QSYS_CIR_CFG_CIR_RATE(rate) |
1315                          QSYS_CIR_CFG_CIR_BURST(burst),
1316                          QSYS_CIR_CFG,
1317                          port_ix);
1318
1319         ocelot_rmw_gix(ocelot,
1320                        QSYS_SE_CFG_SE_FRM_MODE(0) |
1321                        QSYS_SE_CFG_SE_AVB_ENA,
1322                        QSYS_SE_CFG_SE_AVB_ENA |
1323                        QSYS_SE_CFG_SE_FRM_MODE_M,
1324                        QSYS_SE_CFG,
1325                        port_ix);
1326
1327         return 0;
1328 }
1329
1330 static int vsc9959_port_setup_tc(struct dsa_switch *ds, int port,
1331                                  enum tc_setup_type type,
1332                                  void *type_data)
1333 {
1334         struct ocelot *ocelot = ds->priv;
1335
1336         switch (type) {
1337         case TC_SETUP_QDISC_TAPRIO:
1338                 return vsc9959_qos_port_tas_set(ocelot, port, type_data);
1339         case TC_SETUP_QDISC_CBS:
1340                 return vsc9959_qos_port_cbs_set(ds, port, type_data);
1341         default:
1342                 return -EOPNOTSUPP;
1343         }
1344 }
1345
1346 #define VSC9959_PSFP_SFID_MAX                   175
1347 #define VSC9959_PSFP_GATE_ID_MAX                183
1348 #define VSC9959_PSFP_POLICER_BASE               63
1349 #define VSC9959_PSFP_POLICER_MAX                383
1350 #define VSC9959_PSFP_GATE_LIST_NUM              4
1351 #define VSC9959_PSFP_GATE_CYCLETIME_MIN         5000
1352
1353 struct felix_stream {
1354         struct list_head list;
1355         unsigned long id;
1356         bool dummy;
1357         int ports;
1358         int port;
1359         u8 dmac[ETH_ALEN];
1360         u16 vid;
1361         s8 prio;
1362         u8 sfid_valid;
1363         u8 ssid_valid;
1364         u32 sfid;
1365         u32 ssid;
1366 };
1367
1368 struct felix_stream_filter {
1369         struct list_head list;
1370         refcount_t refcount;
1371         u32 index;
1372         u8 enable;
1373         int portmask;
1374         u8 sg_valid;
1375         u32 sgid;
1376         u8 fm_valid;
1377         u32 fmid;
1378         u8 prio_valid;
1379         u8 prio;
1380         u32 maxsdu;
1381 };
1382
1383 struct felix_stream_filter_counters {
1384         u32 match;
1385         u32 not_pass_gate;
1386         u32 not_pass_sdu;
1387         u32 red;
1388 };
1389
1390 struct felix_stream_gate {
1391         u32 index;
1392         u8 enable;
1393         u8 ipv_valid;
1394         u8 init_ipv;
1395         u64 basetime;
1396         u64 cycletime;
1397         u64 cycletime_ext;
1398         u32 num_entries;
1399         struct action_gate_entry entries[];
1400 };
1401
1402 struct felix_stream_gate_entry {
1403         struct list_head list;
1404         refcount_t refcount;
1405         u32 index;
1406 };
1407
1408 static int vsc9959_stream_identify(struct flow_cls_offload *f,
1409                                    struct felix_stream *stream)
1410 {
1411         struct flow_rule *rule = flow_cls_offload_flow_rule(f);
1412         struct flow_dissector *dissector = rule->match.dissector;
1413
1414         if (dissector->used_keys &
1415             ~(BIT(FLOW_DISSECTOR_KEY_CONTROL) |
1416               BIT(FLOW_DISSECTOR_KEY_BASIC) |
1417               BIT(FLOW_DISSECTOR_KEY_VLAN) |
1418               BIT(FLOW_DISSECTOR_KEY_ETH_ADDRS)))
1419                 return -EOPNOTSUPP;
1420
1421         if (flow_rule_match_key(rule, FLOW_DISSECTOR_KEY_ETH_ADDRS)) {
1422                 struct flow_match_eth_addrs match;
1423
1424                 flow_rule_match_eth_addrs(rule, &match);
1425                 ether_addr_copy(stream->dmac, match.key->dst);
1426                 if (!is_zero_ether_addr(match.mask->src))
1427                         return -EOPNOTSUPP;
1428         } else {
1429                 return -EOPNOTSUPP;
1430         }
1431
1432         if (flow_rule_match_key(rule, FLOW_DISSECTOR_KEY_VLAN)) {
1433                 struct flow_match_vlan match;
1434
1435                 flow_rule_match_vlan(rule, &match);
1436                 if (match.mask->vlan_priority)
1437                         stream->prio = match.key->vlan_priority;
1438                 else
1439                         stream->prio = -1;
1440
1441                 if (!match.mask->vlan_id)
1442                         return -EOPNOTSUPP;
1443                 stream->vid = match.key->vlan_id;
1444         } else {
1445                 return -EOPNOTSUPP;
1446         }
1447
1448         stream->id = f->cookie;
1449
1450         return 0;
1451 }
1452
1453 static int vsc9959_mact_stream_set(struct ocelot *ocelot,
1454                                    struct felix_stream *stream,
1455                                    struct netlink_ext_ack *extack)
1456 {
1457         enum macaccess_entry_type type;
1458         int ret, sfid, ssid;
1459         u32 vid, dst_idx;
1460         u8 mac[ETH_ALEN];
1461
1462         ether_addr_copy(mac, stream->dmac);
1463         vid = stream->vid;
1464
1465         /* Stream identification desn't support to add a stream with non
1466          * existent MAC (The MAC entry has not been learned in MAC table).
1467          */
1468         ret = ocelot_mact_lookup(ocelot, &dst_idx, mac, vid, &type);
1469         if (ret) {
1470                 if (extack)
1471                         NL_SET_ERR_MSG_MOD(extack, "Stream is not learned in MAC table");
1472                 return -EOPNOTSUPP;
1473         }
1474
1475         if ((stream->sfid_valid || stream->ssid_valid) &&
1476             type == ENTRYTYPE_NORMAL)
1477                 type = ENTRYTYPE_LOCKED;
1478
1479         sfid = stream->sfid_valid ? stream->sfid : -1;
1480         ssid = stream->ssid_valid ? stream->ssid : -1;
1481
1482         ret = ocelot_mact_learn_streamdata(ocelot, dst_idx, mac, vid, type,
1483                                            sfid, ssid);
1484
1485         return ret;
1486 }
1487
1488 static struct felix_stream *
1489 vsc9959_stream_table_lookup(struct list_head *stream_list,
1490                             struct felix_stream *stream)
1491 {
1492         struct felix_stream *tmp;
1493
1494         list_for_each_entry(tmp, stream_list, list)
1495                 if (ether_addr_equal(tmp->dmac, stream->dmac) &&
1496                     tmp->vid == stream->vid)
1497                         return tmp;
1498
1499         return NULL;
1500 }
1501
1502 static int vsc9959_stream_table_add(struct ocelot *ocelot,
1503                                     struct list_head *stream_list,
1504                                     struct felix_stream *stream,
1505                                     struct netlink_ext_ack *extack)
1506 {
1507         struct felix_stream *stream_entry;
1508         int ret;
1509
1510         stream_entry = kmemdup(stream, sizeof(*stream_entry), GFP_KERNEL);
1511         if (!stream_entry)
1512                 return -ENOMEM;
1513
1514         if (!stream->dummy) {
1515                 ret = vsc9959_mact_stream_set(ocelot, stream_entry, extack);
1516                 if (ret) {
1517                         kfree(stream_entry);
1518                         return ret;
1519                 }
1520         }
1521
1522         list_add_tail(&stream_entry->list, stream_list);
1523
1524         return 0;
1525 }
1526
1527 static struct felix_stream *
1528 vsc9959_stream_table_get(struct list_head *stream_list, unsigned long id)
1529 {
1530         struct felix_stream *tmp;
1531
1532         list_for_each_entry(tmp, stream_list, list)
1533                 if (tmp->id == id)
1534                         return tmp;
1535
1536         return NULL;
1537 }
1538
1539 static void vsc9959_stream_table_del(struct ocelot *ocelot,
1540                                      struct felix_stream *stream)
1541 {
1542         if (!stream->dummy)
1543                 vsc9959_mact_stream_set(ocelot, stream, NULL);
1544
1545         list_del(&stream->list);
1546         kfree(stream);
1547 }
1548
1549 static u32 vsc9959_sfi_access_status(struct ocelot *ocelot)
1550 {
1551         return ocelot_read(ocelot, ANA_TABLES_SFIDACCESS);
1552 }
1553
1554 static int vsc9959_psfp_sfi_set(struct ocelot *ocelot,
1555                                 struct felix_stream_filter *sfi)
1556 {
1557         u32 val;
1558
1559         if (sfi->index > VSC9959_PSFP_SFID_MAX)
1560                 return -EINVAL;
1561
1562         if (!sfi->enable) {
1563                 ocelot_write(ocelot, ANA_TABLES_SFIDTIDX_SFID_INDEX(sfi->index),
1564                              ANA_TABLES_SFIDTIDX);
1565
1566                 val = ANA_TABLES_SFIDACCESS_SFID_TBL_CMD(SFIDACCESS_CMD_WRITE);
1567                 ocelot_write(ocelot, val, ANA_TABLES_SFIDACCESS);
1568
1569                 return readx_poll_timeout(vsc9959_sfi_access_status, ocelot, val,
1570                                           (!ANA_TABLES_SFIDACCESS_SFID_TBL_CMD(val)),
1571                                           10, 100000);
1572         }
1573
1574         if (sfi->sgid > VSC9959_PSFP_GATE_ID_MAX ||
1575             sfi->fmid > VSC9959_PSFP_POLICER_MAX)
1576                 return -EINVAL;
1577
1578         ocelot_write(ocelot,
1579                      (sfi->sg_valid ? ANA_TABLES_SFIDTIDX_SGID_VALID : 0) |
1580                      ANA_TABLES_SFIDTIDX_SGID(sfi->sgid) |
1581                      (sfi->fm_valid ? ANA_TABLES_SFIDTIDX_POL_ENA : 0) |
1582                      ANA_TABLES_SFIDTIDX_POL_IDX(sfi->fmid) |
1583                      ANA_TABLES_SFIDTIDX_SFID_INDEX(sfi->index),
1584                      ANA_TABLES_SFIDTIDX);
1585
1586         ocelot_write(ocelot,
1587                      (sfi->prio_valid ? ANA_TABLES_SFIDACCESS_IGR_PRIO_MATCH_ENA : 0) |
1588                      ANA_TABLES_SFIDACCESS_IGR_PRIO(sfi->prio) |
1589                      ANA_TABLES_SFIDACCESS_MAX_SDU_LEN(sfi->maxsdu) |
1590                      ANA_TABLES_SFIDACCESS_SFID_TBL_CMD(SFIDACCESS_CMD_WRITE),
1591                      ANA_TABLES_SFIDACCESS);
1592
1593         return readx_poll_timeout(vsc9959_sfi_access_status, ocelot, val,
1594                                   (!ANA_TABLES_SFIDACCESS_SFID_TBL_CMD(val)),
1595                                   10, 100000);
1596 }
1597
1598 static int vsc9959_psfp_sfidmask_set(struct ocelot *ocelot, u32 sfid, int ports)
1599 {
1600         u32 val;
1601
1602         ocelot_rmw(ocelot,
1603                    ANA_TABLES_SFIDTIDX_SFID_INDEX(sfid),
1604                    ANA_TABLES_SFIDTIDX_SFID_INDEX_M,
1605                    ANA_TABLES_SFIDTIDX);
1606
1607         ocelot_write(ocelot,
1608                      ANA_TABLES_SFID_MASK_IGR_PORT_MASK(ports) |
1609                      ANA_TABLES_SFID_MASK_IGR_SRCPORT_MATCH_ENA,
1610                      ANA_TABLES_SFID_MASK);
1611
1612         ocelot_rmw(ocelot,
1613                    ANA_TABLES_SFIDACCESS_SFID_TBL_CMD(SFIDACCESS_CMD_WRITE),
1614                    ANA_TABLES_SFIDACCESS_SFID_TBL_CMD_M,
1615                    ANA_TABLES_SFIDACCESS);
1616
1617         return readx_poll_timeout(vsc9959_sfi_access_status, ocelot, val,
1618                                   (!ANA_TABLES_SFIDACCESS_SFID_TBL_CMD(val)),
1619                                   10, 100000);
1620 }
1621
1622 static int vsc9959_psfp_sfi_list_add(struct ocelot *ocelot,
1623                                      struct felix_stream_filter *sfi,
1624                                      struct list_head *pos)
1625 {
1626         struct felix_stream_filter *sfi_entry;
1627         int ret;
1628
1629         sfi_entry = kmemdup(sfi, sizeof(*sfi_entry), GFP_KERNEL);
1630         if (!sfi_entry)
1631                 return -ENOMEM;
1632
1633         refcount_set(&sfi_entry->refcount, 1);
1634
1635         ret = vsc9959_psfp_sfi_set(ocelot, sfi_entry);
1636         if (ret) {
1637                 kfree(sfi_entry);
1638                 return ret;
1639         }
1640
1641         vsc9959_psfp_sfidmask_set(ocelot, sfi->index, sfi->portmask);
1642
1643         list_add(&sfi_entry->list, pos);
1644
1645         return 0;
1646 }
1647
1648 static int vsc9959_psfp_sfi_table_add(struct ocelot *ocelot,
1649                                       struct felix_stream_filter *sfi)
1650 {
1651         struct list_head *pos, *q, *last;
1652         struct felix_stream_filter *tmp;
1653         struct ocelot_psfp_list *psfp;
1654         u32 insert = 0;
1655
1656         psfp = &ocelot->psfp;
1657         last = &psfp->sfi_list;
1658
1659         list_for_each_safe(pos, q, &psfp->sfi_list) {
1660                 tmp = list_entry(pos, struct felix_stream_filter, list);
1661                 if (sfi->sg_valid == tmp->sg_valid &&
1662                     sfi->fm_valid == tmp->fm_valid &&
1663                     sfi->portmask == tmp->portmask &&
1664                     tmp->sgid == sfi->sgid &&
1665                     tmp->fmid == sfi->fmid) {
1666                         sfi->index = tmp->index;
1667                         refcount_inc(&tmp->refcount);
1668                         return 0;
1669                 }
1670                 /* Make sure that the index is increasing in order. */
1671                 if (tmp->index == insert) {
1672                         last = pos;
1673                         insert++;
1674                 }
1675         }
1676         sfi->index = insert;
1677
1678         return vsc9959_psfp_sfi_list_add(ocelot, sfi, last);
1679 }
1680
1681 static int vsc9959_psfp_sfi_table_add2(struct ocelot *ocelot,
1682                                        struct felix_stream_filter *sfi,
1683                                        struct felix_stream_filter *sfi2)
1684 {
1685         struct felix_stream_filter *tmp;
1686         struct list_head *pos, *q, *last;
1687         struct ocelot_psfp_list *psfp;
1688         u32 insert = 0;
1689         int ret;
1690
1691         psfp = &ocelot->psfp;
1692         last = &psfp->sfi_list;
1693
1694         list_for_each_safe(pos, q, &psfp->sfi_list) {
1695                 tmp = list_entry(pos, struct felix_stream_filter, list);
1696                 /* Make sure that the index is increasing in order. */
1697                 if (tmp->index >= insert + 2)
1698                         break;
1699
1700                 insert = tmp->index + 1;
1701                 last = pos;
1702         }
1703         sfi->index = insert;
1704
1705         ret = vsc9959_psfp_sfi_list_add(ocelot, sfi, last);
1706         if (ret)
1707                 return ret;
1708
1709         sfi2->index = insert + 1;
1710
1711         return vsc9959_psfp_sfi_list_add(ocelot, sfi2, last->next);
1712 }
1713
1714 static struct felix_stream_filter *
1715 vsc9959_psfp_sfi_table_get(struct list_head *sfi_list, u32 index)
1716 {
1717         struct felix_stream_filter *tmp;
1718
1719         list_for_each_entry(tmp, sfi_list, list)
1720                 if (tmp->index == index)
1721                         return tmp;
1722
1723         return NULL;
1724 }
1725
1726 static void vsc9959_psfp_sfi_table_del(struct ocelot *ocelot, u32 index)
1727 {
1728         struct felix_stream_filter *tmp, *n;
1729         struct ocelot_psfp_list *psfp;
1730         u8 z;
1731
1732         psfp = &ocelot->psfp;
1733
1734         list_for_each_entry_safe(tmp, n, &psfp->sfi_list, list)
1735                 if (tmp->index == index) {
1736                         z = refcount_dec_and_test(&tmp->refcount);
1737                         if (z) {
1738                                 tmp->enable = 0;
1739                                 vsc9959_psfp_sfi_set(ocelot, tmp);
1740                                 list_del(&tmp->list);
1741                                 kfree(tmp);
1742                         }
1743                         break;
1744                 }
1745 }
1746
1747 static void vsc9959_psfp_parse_gate(const struct flow_action_entry *entry,
1748                                     struct felix_stream_gate *sgi)
1749 {
1750         sgi->index = entry->hw_index;
1751         sgi->ipv_valid = (entry->gate.prio < 0) ? 0 : 1;
1752         sgi->init_ipv = (sgi->ipv_valid) ? entry->gate.prio : 0;
1753         sgi->basetime = entry->gate.basetime;
1754         sgi->cycletime = entry->gate.cycletime;
1755         sgi->num_entries = entry->gate.num_entries;
1756         sgi->enable = 1;
1757
1758         memcpy(sgi->entries, entry->gate.entries,
1759                entry->gate.num_entries * sizeof(struct action_gate_entry));
1760 }
1761
1762 static u32 vsc9959_sgi_cfg_status(struct ocelot *ocelot)
1763 {
1764         return ocelot_read(ocelot, ANA_SG_ACCESS_CTRL);
1765 }
1766
1767 static int vsc9959_psfp_sgi_set(struct ocelot *ocelot,
1768                                 struct felix_stream_gate *sgi)
1769 {
1770         struct action_gate_entry *e;
1771         struct timespec64 base_ts;
1772         u32 interval_sum = 0;
1773         u32 val;
1774         int i;
1775
1776         if (sgi->index > VSC9959_PSFP_GATE_ID_MAX)
1777                 return -EINVAL;
1778
1779         ocelot_write(ocelot, ANA_SG_ACCESS_CTRL_SGID(sgi->index),
1780                      ANA_SG_ACCESS_CTRL);
1781
1782         if (!sgi->enable) {
1783                 ocelot_rmw(ocelot, ANA_SG_CONFIG_REG_3_INIT_GATE_STATE,
1784                            ANA_SG_CONFIG_REG_3_INIT_GATE_STATE |
1785                            ANA_SG_CONFIG_REG_3_GATE_ENABLE,
1786                            ANA_SG_CONFIG_REG_3);
1787
1788                 return 0;
1789         }
1790
1791         if (sgi->cycletime < VSC9959_PSFP_GATE_CYCLETIME_MIN ||
1792             sgi->cycletime > NSEC_PER_SEC)
1793                 return -EINVAL;
1794
1795         if (sgi->num_entries > VSC9959_PSFP_GATE_LIST_NUM)
1796                 return -EINVAL;
1797
1798         vsc9959_new_base_time(ocelot, sgi->basetime, sgi->cycletime, &base_ts);
1799         ocelot_write(ocelot, base_ts.tv_nsec, ANA_SG_CONFIG_REG_1);
1800         val = lower_32_bits(base_ts.tv_sec);
1801         ocelot_write(ocelot, val, ANA_SG_CONFIG_REG_2);
1802
1803         val = upper_32_bits(base_ts.tv_sec);
1804         ocelot_write(ocelot,
1805                      (sgi->ipv_valid ? ANA_SG_CONFIG_REG_3_IPV_VALID : 0) |
1806                      ANA_SG_CONFIG_REG_3_INIT_IPV(sgi->init_ipv) |
1807                      ANA_SG_CONFIG_REG_3_GATE_ENABLE |
1808                      ANA_SG_CONFIG_REG_3_LIST_LENGTH(sgi->num_entries) |
1809                      ANA_SG_CONFIG_REG_3_INIT_GATE_STATE |
1810                      ANA_SG_CONFIG_REG_3_BASE_TIME_SEC_MSB(val),
1811                      ANA_SG_CONFIG_REG_3);
1812
1813         ocelot_write(ocelot, sgi->cycletime, ANA_SG_CONFIG_REG_4);
1814
1815         e = sgi->entries;
1816         for (i = 0; i < sgi->num_entries; i++) {
1817                 u32 ips = (e[i].ipv < 0) ? 0 : (e[i].ipv + 8);
1818
1819                 ocelot_write_rix(ocelot, ANA_SG_GCL_GS_CONFIG_IPS(ips) |
1820                                  (e[i].gate_state ?
1821                                   ANA_SG_GCL_GS_CONFIG_GATE_STATE : 0),
1822                                  ANA_SG_GCL_GS_CONFIG, i);
1823
1824                 interval_sum += e[i].interval;
1825                 ocelot_write_rix(ocelot, interval_sum, ANA_SG_GCL_TI_CONFIG, i);
1826         }
1827
1828         ocelot_rmw(ocelot, ANA_SG_ACCESS_CTRL_CONFIG_CHANGE,
1829                    ANA_SG_ACCESS_CTRL_CONFIG_CHANGE,
1830                    ANA_SG_ACCESS_CTRL);
1831
1832         return readx_poll_timeout(vsc9959_sgi_cfg_status, ocelot, val,
1833                                   (!(ANA_SG_ACCESS_CTRL_CONFIG_CHANGE & val)),
1834                                   10, 100000);
1835 }
1836
1837 static int vsc9959_psfp_sgi_table_add(struct ocelot *ocelot,
1838                                       struct felix_stream_gate *sgi)
1839 {
1840         struct felix_stream_gate_entry *tmp;
1841         struct ocelot_psfp_list *psfp;
1842         int ret;
1843
1844         psfp = &ocelot->psfp;
1845
1846         list_for_each_entry(tmp, &psfp->sgi_list, list)
1847                 if (tmp->index == sgi->index) {
1848                         refcount_inc(&tmp->refcount);
1849                         return 0;
1850                 }
1851
1852         tmp = kzalloc(sizeof(*tmp), GFP_KERNEL);
1853         if (!tmp)
1854                 return -ENOMEM;
1855
1856         ret = vsc9959_psfp_sgi_set(ocelot, sgi);
1857         if (ret) {
1858                 kfree(tmp);
1859                 return ret;
1860         }
1861
1862         tmp->index = sgi->index;
1863         refcount_set(&tmp->refcount, 1);
1864         list_add_tail(&tmp->list, &psfp->sgi_list);
1865
1866         return 0;
1867 }
1868
1869 static void vsc9959_psfp_sgi_table_del(struct ocelot *ocelot,
1870                                        u32 index)
1871 {
1872         struct felix_stream_gate_entry *tmp, *n;
1873         struct felix_stream_gate sgi = {0};
1874         struct ocelot_psfp_list *psfp;
1875         u8 z;
1876
1877         psfp = &ocelot->psfp;
1878
1879         list_for_each_entry_safe(tmp, n, &psfp->sgi_list, list)
1880                 if (tmp->index == index) {
1881                         z = refcount_dec_and_test(&tmp->refcount);
1882                         if (z) {
1883                                 sgi.index = index;
1884                                 sgi.enable = 0;
1885                                 vsc9959_psfp_sgi_set(ocelot, &sgi);
1886                                 list_del(&tmp->list);
1887                                 kfree(tmp);
1888                         }
1889                         break;
1890                 }
1891 }
1892
1893 static void vsc9959_psfp_counters_get(struct ocelot *ocelot, u32 index,
1894                                       struct felix_stream_filter_counters *counters)
1895 {
1896         ocelot_rmw(ocelot, SYS_STAT_CFG_STAT_VIEW(index),
1897                    SYS_STAT_CFG_STAT_VIEW_M,
1898                    SYS_STAT_CFG);
1899
1900         counters->match = ocelot_read_gix(ocelot, SYS_CNT, 0x200);
1901         counters->not_pass_gate = ocelot_read_gix(ocelot, SYS_CNT, 0x201);
1902         counters->not_pass_sdu = ocelot_read_gix(ocelot, SYS_CNT, 0x202);
1903         counters->red = ocelot_read_gix(ocelot, SYS_CNT, 0x203);
1904
1905         /* Clear the PSFP counter. */
1906         ocelot_write(ocelot,
1907                      SYS_STAT_CFG_STAT_VIEW(index) |
1908                      SYS_STAT_CFG_STAT_CLEAR_SHOT(0x10),
1909                      SYS_STAT_CFG);
1910 }
1911
1912 static int vsc9959_psfp_filter_add(struct ocelot *ocelot, int port,
1913                                    struct flow_cls_offload *f)
1914 {
1915         struct netlink_ext_ack *extack = f->common.extack;
1916         struct felix_stream_filter old_sfi, *sfi_entry;
1917         struct felix_stream_filter sfi = {0};
1918         const struct flow_action_entry *a;
1919         struct felix_stream *stream_entry;
1920         struct felix_stream stream = {0};
1921         struct felix_stream_gate *sgi;
1922         struct ocelot_psfp_list *psfp;
1923         struct ocelot_policer pol;
1924         int ret, i, size;
1925         u64 rate, burst;
1926         u32 index;
1927
1928         psfp = &ocelot->psfp;
1929
1930         ret = vsc9959_stream_identify(f, &stream);
1931         if (ret) {
1932                 NL_SET_ERR_MSG_MOD(extack, "Only can match on VID, PCP, and dest MAC");
1933                 return ret;
1934         }
1935
1936         flow_action_for_each(i, a, &f->rule->action) {
1937                 switch (a->id) {
1938                 case FLOW_ACTION_GATE:
1939                         size = struct_size(sgi, entries, a->gate.num_entries);
1940                         sgi = kzalloc(size, GFP_KERNEL);
1941                         vsc9959_psfp_parse_gate(a, sgi);
1942                         ret = vsc9959_psfp_sgi_table_add(ocelot, sgi);
1943                         if (ret) {
1944                                 kfree(sgi);
1945                                 goto err;
1946                         }
1947                         sfi.sg_valid = 1;
1948                         sfi.sgid = sgi->index;
1949                         kfree(sgi);
1950                         break;
1951                 case FLOW_ACTION_POLICE:
1952                         index = a->hw_index + VSC9959_PSFP_POLICER_BASE;
1953                         if (index > VSC9959_PSFP_POLICER_MAX) {
1954                                 ret = -EINVAL;
1955                                 goto err;
1956                         }
1957
1958                         rate = a->police.rate_bytes_ps;
1959                         burst = rate * PSCHED_NS2TICKS(a->police.burst);
1960                         pol = (struct ocelot_policer) {
1961                                 .burst = div_u64(burst, PSCHED_TICKS_PER_SEC),
1962                                 .rate = div_u64(rate, 1000) * 8,
1963                         };
1964                         ret = ocelot_vcap_policer_add(ocelot, index, &pol);
1965                         if (ret)
1966                                 goto err;
1967
1968                         sfi.fm_valid = 1;
1969                         sfi.fmid = index;
1970                         sfi.maxsdu = a->police.mtu;
1971                         break;
1972                 default:
1973                         return -EOPNOTSUPP;
1974                 }
1975         }
1976
1977         stream.ports = BIT(port);
1978         stream.port = port;
1979
1980         sfi.portmask = stream.ports;
1981         sfi.prio_valid = (stream.prio < 0 ? 0 : 1);
1982         sfi.prio = (sfi.prio_valid ? stream.prio : 0);
1983         sfi.enable = 1;
1984
1985         /* Check if stream is set. */
1986         stream_entry = vsc9959_stream_table_lookup(&psfp->stream_list, &stream);
1987         if (stream_entry) {
1988                 if (stream_entry->ports & BIT(port)) {
1989                         NL_SET_ERR_MSG_MOD(extack,
1990                                            "The stream is added on this port");
1991                         ret = -EEXIST;
1992                         goto err;
1993                 }
1994
1995                 if (stream_entry->ports != BIT(stream_entry->port)) {
1996                         NL_SET_ERR_MSG_MOD(extack,
1997                                            "The stream is added on two ports");
1998                         ret = -EEXIST;
1999                         goto err;
2000                 }
2001
2002                 stream_entry->ports |= BIT(port);
2003                 stream.ports = stream_entry->ports;
2004
2005                 sfi_entry = vsc9959_psfp_sfi_table_get(&psfp->sfi_list,
2006                                                        stream_entry->sfid);
2007                 memcpy(&old_sfi, sfi_entry, sizeof(old_sfi));
2008
2009                 vsc9959_psfp_sfi_table_del(ocelot, stream_entry->sfid);
2010
2011                 old_sfi.portmask = stream_entry->ports;
2012                 sfi.portmask = stream.ports;
2013
2014                 if (stream_entry->port > port) {
2015                         ret = vsc9959_psfp_sfi_table_add2(ocelot, &sfi,
2016                                                           &old_sfi);
2017                         stream_entry->dummy = true;
2018                 } else {
2019                         ret = vsc9959_psfp_sfi_table_add2(ocelot, &old_sfi,
2020                                                           &sfi);
2021                         stream.dummy = true;
2022                 }
2023                 if (ret)
2024                         goto err;
2025
2026                 stream_entry->sfid = old_sfi.index;
2027         } else {
2028                 ret = vsc9959_psfp_sfi_table_add(ocelot, &sfi);
2029                 if (ret)
2030                         goto err;
2031         }
2032
2033         stream.sfid = sfi.index;
2034         stream.sfid_valid = 1;
2035         ret = vsc9959_stream_table_add(ocelot, &psfp->stream_list,
2036                                        &stream, extack);
2037         if (ret) {
2038                 vsc9959_psfp_sfi_table_del(ocelot, stream.sfid);
2039                 goto err;
2040         }
2041
2042         return 0;
2043
2044 err:
2045         if (sfi.sg_valid)
2046                 vsc9959_psfp_sgi_table_del(ocelot, sfi.sgid);
2047
2048         if (sfi.fm_valid)
2049                 ocelot_vcap_policer_del(ocelot, sfi.fmid);
2050
2051         return ret;
2052 }
2053
2054 static int vsc9959_psfp_filter_del(struct ocelot *ocelot,
2055                                    struct flow_cls_offload *f)
2056 {
2057         struct felix_stream *stream, tmp, *stream_entry;
2058         static struct felix_stream_filter *sfi;
2059         struct ocelot_psfp_list *psfp;
2060
2061         psfp = &ocelot->psfp;
2062
2063         stream = vsc9959_stream_table_get(&psfp->stream_list, f->cookie);
2064         if (!stream)
2065                 return -ENOMEM;
2066
2067         sfi = vsc9959_psfp_sfi_table_get(&psfp->sfi_list, stream->sfid);
2068         if (!sfi)
2069                 return -ENOMEM;
2070
2071         if (sfi->sg_valid)
2072                 vsc9959_psfp_sgi_table_del(ocelot, sfi->sgid);
2073
2074         if (sfi->fm_valid)
2075                 ocelot_vcap_policer_del(ocelot, sfi->fmid);
2076
2077         vsc9959_psfp_sfi_table_del(ocelot, stream->sfid);
2078
2079         memcpy(&tmp, stream, sizeof(tmp));
2080
2081         stream->sfid_valid = 0;
2082         vsc9959_stream_table_del(ocelot, stream);
2083
2084         stream_entry = vsc9959_stream_table_lookup(&psfp->stream_list, &tmp);
2085         if (stream_entry) {
2086                 stream_entry->ports = BIT(stream_entry->port);
2087                 if (stream_entry->dummy) {
2088                         stream_entry->dummy = false;
2089                         vsc9959_mact_stream_set(ocelot, stream_entry, NULL);
2090                 }
2091                 vsc9959_psfp_sfidmask_set(ocelot, stream_entry->sfid,
2092                                           stream_entry->ports);
2093         }
2094
2095         return 0;
2096 }
2097
2098 static int vsc9959_psfp_stats_get(struct ocelot *ocelot,
2099                                   struct flow_cls_offload *f,
2100                                   struct flow_stats *stats)
2101 {
2102         struct felix_stream_filter_counters counters;
2103         struct ocelot_psfp_list *psfp;
2104         struct felix_stream *stream;
2105
2106         psfp = &ocelot->psfp;
2107         stream = vsc9959_stream_table_get(&psfp->stream_list, f->cookie);
2108         if (!stream)
2109                 return -ENOMEM;
2110
2111         vsc9959_psfp_counters_get(ocelot, stream->sfid, &counters);
2112
2113         stats->pkts = counters.match;
2114         stats->drops = counters.not_pass_gate + counters.not_pass_sdu +
2115                        counters.red;
2116
2117         return 0;
2118 }
2119
2120 static void vsc9959_psfp_init(struct ocelot *ocelot)
2121 {
2122         struct ocelot_psfp_list *psfp = &ocelot->psfp;
2123
2124         INIT_LIST_HEAD(&psfp->stream_list);
2125         INIT_LIST_HEAD(&psfp->sfi_list);
2126         INIT_LIST_HEAD(&psfp->sgi_list);
2127 }
2128
2129 /* When using cut-through forwarding and the egress port runs at a higher data
2130  * rate than the ingress port, the packet currently under transmission would
2131  * suffer an underrun since it would be transmitted faster than it is received.
2132  * The Felix switch implementation of cut-through forwarding does not check in
2133  * hardware whether this condition is satisfied or not, so we must restrict the
2134  * list of ports that have cut-through forwarding enabled on egress to only be
2135  * the ports operating at the lowest link speed within their respective
2136  * forwarding domain.
2137  */
2138 static void vsc9959_cut_through_fwd(struct ocelot *ocelot)
2139 {
2140         struct felix *felix = ocelot_to_felix(ocelot);
2141         struct dsa_switch *ds = felix->ds;
2142         int port, other_port;
2143
2144         lockdep_assert_held(&ocelot->fwd_domain_lock);
2145
2146         for (port = 0; port < ocelot->num_phys_ports; port++) {
2147                 struct ocelot_port *ocelot_port = ocelot->ports[port];
2148                 int min_speed = ocelot_port->speed;
2149                 unsigned long mask = 0;
2150                 u32 tmp, val = 0;
2151
2152                 /* Disable cut-through on ports that are down */
2153                 if (ocelot_port->speed <= 0)
2154                         goto set;
2155
2156                 if (dsa_is_cpu_port(ds, port)) {
2157                         /* Ocelot switches forward from the NPI port towards
2158                          * any port, regardless of it being in the NPI port's
2159                          * forwarding domain or not.
2160                          */
2161                         mask = dsa_user_ports(ds);
2162                 } else {
2163                         mask = ocelot_get_bridge_fwd_mask(ocelot, port);
2164                         mask &= ~BIT(port);
2165                         if (ocelot->npi >= 0)
2166                                 mask |= BIT(ocelot->npi);
2167                         else
2168                                 mask |= ocelot_get_dsa_8021q_cpu_mask(ocelot);
2169                 }
2170
2171                 /* Calculate the minimum link speed, among the ports that are
2172                  * up, of this source port's forwarding domain.
2173                  */
2174                 for_each_set_bit(other_port, &mask, ocelot->num_phys_ports) {
2175                         struct ocelot_port *other_ocelot_port;
2176
2177                         other_ocelot_port = ocelot->ports[other_port];
2178                         if (other_ocelot_port->speed <= 0)
2179                                 continue;
2180
2181                         if (min_speed > other_ocelot_port->speed)
2182                                 min_speed = other_ocelot_port->speed;
2183                 }
2184
2185                 /* Enable cut-through forwarding for all traffic classes. */
2186                 if (ocelot_port->speed == min_speed)
2187                         val = GENMASK(7, 0);
2188
2189 set:
2190                 tmp = ocelot_read_rix(ocelot, ANA_CUT_THRU_CFG, port);
2191                 if (tmp == val)
2192                         continue;
2193
2194                 dev_dbg(ocelot->dev,
2195                         "port %d fwd mask 0x%lx speed %d min_speed %d, %s cut-through forwarding\n",
2196                         port, mask, ocelot_port->speed, min_speed,
2197                         val ? "enabling" : "disabling");
2198
2199                 ocelot_write_rix(ocelot, val, ANA_CUT_THRU_CFG, port);
2200         }
2201 }
2202
2203 static const struct ocelot_ops vsc9959_ops = {
2204         .reset                  = vsc9959_reset,
2205         .wm_enc                 = vsc9959_wm_enc,
2206         .wm_dec                 = vsc9959_wm_dec,
2207         .wm_stat                = vsc9959_wm_stat,
2208         .port_to_netdev         = felix_port_to_netdev,
2209         .netdev_to_port         = felix_netdev_to_port,
2210         .psfp_init              = vsc9959_psfp_init,
2211         .psfp_filter_add        = vsc9959_psfp_filter_add,
2212         .psfp_filter_del        = vsc9959_psfp_filter_del,
2213         .psfp_stats_get         = vsc9959_psfp_stats_get,
2214         .cut_through_fwd        = vsc9959_cut_through_fwd,
2215 };
2216
2217 static const struct felix_info felix_info_vsc9959 = {
2218         .target_io_res          = vsc9959_target_io_res,
2219         .port_io_res            = vsc9959_port_io_res,
2220         .imdio_res              = &vsc9959_imdio_res,
2221         .regfields              = vsc9959_regfields,
2222         .map                    = vsc9959_regmap,
2223         .ops                    = &vsc9959_ops,
2224         .stats_layout           = vsc9959_stats_layout,
2225         .num_stats              = ARRAY_SIZE(vsc9959_stats_layout),
2226         .vcap                   = vsc9959_vcap_props,
2227         .vcap_pol_base          = VSC9959_VCAP_POLICER_BASE,
2228         .vcap_pol_max           = VSC9959_VCAP_POLICER_MAX,
2229         .vcap_pol_base2         = 0,
2230         .vcap_pol_max2          = 0,
2231         .num_mact_rows          = 2048,
2232         .num_ports              = 6,
2233         .num_tx_queues          = OCELOT_NUM_TC,
2234         .quirk_no_xtr_irq       = true,
2235         .ptp_caps               = &vsc9959_ptp_caps,
2236         .mdio_bus_alloc         = vsc9959_mdio_bus_alloc,
2237         .mdio_bus_free          = vsc9959_mdio_bus_free,
2238         .phylink_validate       = vsc9959_phylink_validate,
2239         .prevalidate_phy_mode   = vsc9959_prevalidate_phy_mode,
2240         .port_setup_tc          = vsc9959_port_setup_tc,
2241         .port_sched_speed_set   = vsc9959_sched_speed_set,
2242         .init_regmap            = ocelot_regmap_init,
2243 };
2244
2245 static irqreturn_t felix_irq_handler(int irq, void *data)
2246 {
2247         struct ocelot *ocelot = (struct ocelot *)data;
2248
2249         /* The INTB interrupt is used for both PTP TX timestamp interrupt
2250          * and preemption status change interrupt on each port.
2251          *
2252          * - Get txtstamp if have
2253          * - TODO: handle preemption. Without handling it, driver may get
2254          *   interrupt storm.
2255          */
2256
2257         ocelot_get_txtstamp(ocelot);
2258
2259         return IRQ_HANDLED;
2260 }
2261
2262 static int felix_pci_probe(struct pci_dev *pdev,
2263                            const struct pci_device_id *id)
2264 {
2265         struct dsa_switch *ds;
2266         struct ocelot *ocelot;
2267         struct felix *felix;
2268         int err;
2269
2270         if (pdev->dev.of_node && !of_device_is_available(pdev->dev.of_node)) {
2271                 dev_info(&pdev->dev, "device is disabled, skipping\n");
2272                 return -ENODEV;
2273         }
2274
2275         err = pci_enable_device(pdev);
2276         if (err) {
2277                 dev_err(&pdev->dev, "device enable failed\n");
2278                 goto err_pci_enable;
2279         }
2280
2281         felix = kzalloc(sizeof(struct felix), GFP_KERNEL);
2282         if (!felix) {
2283                 err = -ENOMEM;
2284                 dev_err(&pdev->dev, "Failed to allocate driver memory\n");
2285                 goto err_alloc_felix;
2286         }
2287
2288         pci_set_drvdata(pdev, felix);
2289         ocelot = &felix->ocelot;
2290         ocelot->dev = &pdev->dev;
2291         ocelot->num_flooding_pgids = OCELOT_NUM_TC;
2292         felix->info = &felix_info_vsc9959;
2293         felix->switch_base = pci_resource_start(pdev, VSC9959_SWITCH_PCI_BAR);
2294         felix->imdio_base = pci_resource_start(pdev, VSC9959_IMDIO_PCI_BAR);
2295
2296         pci_set_master(pdev);
2297
2298         err = devm_request_threaded_irq(&pdev->dev, pdev->irq, NULL,
2299                                         &felix_irq_handler, IRQF_ONESHOT,
2300                                         "felix-intb", ocelot);
2301         if (err) {
2302                 dev_err(&pdev->dev, "Failed to request irq\n");
2303                 goto err_alloc_irq;
2304         }
2305
2306         ocelot->ptp = 1;
2307
2308         ds = kzalloc(sizeof(struct dsa_switch), GFP_KERNEL);
2309         if (!ds) {
2310                 err = -ENOMEM;
2311                 dev_err(&pdev->dev, "Failed to allocate DSA switch\n");
2312                 goto err_alloc_ds;
2313         }
2314
2315         ds->dev = &pdev->dev;
2316         ds->num_ports = felix->info->num_ports;
2317         ds->num_tx_queues = felix->info->num_tx_queues;
2318         ds->ops = &felix_switch_ops;
2319         ds->priv = ocelot;
2320         felix->ds = ds;
2321         felix->tag_proto = DSA_TAG_PROTO_OCELOT;
2322
2323         err = dsa_register_switch(ds);
2324         if (err) {
2325                 dev_err(&pdev->dev, "Failed to register DSA switch: %d\n", err);
2326                 goto err_register_ds;
2327         }
2328
2329         return 0;
2330
2331 err_register_ds:
2332         kfree(ds);
2333 err_alloc_ds:
2334 err_alloc_irq:
2335         kfree(felix);
2336 err_alloc_felix:
2337         pci_disable_device(pdev);
2338 err_pci_enable:
2339         return err;
2340 }
2341
2342 static void felix_pci_remove(struct pci_dev *pdev)
2343 {
2344         struct felix *felix = pci_get_drvdata(pdev);
2345
2346         if (!felix)
2347                 return;
2348
2349         dsa_unregister_switch(felix->ds);
2350
2351         kfree(felix->ds);
2352         kfree(felix);
2353
2354         pci_disable_device(pdev);
2355
2356         pci_set_drvdata(pdev, NULL);
2357 }
2358
2359 static void felix_pci_shutdown(struct pci_dev *pdev)
2360 {
2361         struct felix *felix = pci_get_drvdata(pdev);
2362
2363         if (!felix)
2364                 return;
2365
2366         dsa_switch_shutdown(felix->ds);
2367
2368         pci_set_drvdata(pdev, NULL);
2369 }
2370
2371 static struct pci_device_id felix_ids[] = {
2372         {
2373                 /* NXP LS1028A */
2374                 PCI_DEVICE(PCI_VENDOR_ID_FREESCALE, 0xEEF0),
2375         },
2376         { 0, }
2377 };
2378 MODULE_DEVICE_TABLE(pci, felix_ids);
2379
2380 static struct pci_driver felix_vsc9959_pci_driver = {
2381         .name           = "mscc_felix",
2382         .id_table       = felix_ids,
2383         .probe          = felix_pci_probe,
2384         .remove         = felix_pci_remove,
2385         .shutdown       = felix_pci_shutdown,
2386 };
2387 module_pci_driver(felix_vsc9959_pci_driver);
2388
2389 MODULE_DESCRIPTION("Felix Switch driver");
2390 MODULE_LICENSE("GPL v2");