1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
2 /* Copyright 2017 Microsemi Corporation
3 * Copyright 2018-2019 NXP
5 #include <linux/fsl/enetc_mdio.h>
6 #include <soc/mscc/ocelot_qsys.h>
7 #include <soc/mscc/ocelot_vcap.h>
8 #include <soc/mscc/ocelot_ana.h>
9 #include <soc/mscc/ocelot_ptp.h>
10 #include <soc/mscc/ocelot_sys.h>
11 #include <net/tc_act/tc_gate.h>
12 #include <soc/mscc/ocelot.h>
13 #include <linux/dsa/ocelot.h>
14 #include <linux/pcs-lynx.h>
15 #include <net/pkt_sched.h>
16 #include <linux/iopoll.h>
17 #include <linux/mdio.h>
18 #include <linux/pci.h>
21 #define VSC9959_NUM_PORTS 6
23 #define VSC9959_TAS_GCL_ENTRY_MAX 63
24 #define VSC9959_VCAP_POLICER_BASE 63
25 #define VSC9959_VCAP_POLICER_MAX 383
26 #define VSC9959_SWITCH_PCI_BAR 4
27 #define VSC9959_IMDIO_PCI_BAR 0
29 #define VSC9959_PORT_MODE_SERDES (OCELOT_PORT_MODE_SGMII | \
30 OCELOT_PORT_MODE_QSGMII | \
31 OCELOT_PORT_MODE_2500BASEX | \
32 OCELOT_PORT_MODE_USXGMII)
34 static const u32 vsc9959_port_modes[VSC9959_NUM_PORTS] = {
35 VSC9959_PORT_MODE_SERDES,
36 VSC9959_PORT_MODE_SERDES,
37 VSC9959_PORT_MODE_SERDES,
38 VSC9959_PORT_MODE_SERDES,
39 OCELOT_PORT_MODE_INTERNAL,
40 OCELOT_PORT_MODE_INTERNAL,
43 static const u32 vsc9959_ana_regmap[] = {
44 REG(ANA_ADVLEARN, 0x0089a0),
45 REG(ANA_VLANMASK, 0x0089a4),
46 REG_RESERVED(ANA_PORT_B_DOMAIN),
47 REG(ANA_ANAGEFIL, 0x0089ac),
48 REG(ANA_ANEVENTS, 0x0089b0),
49 REG(ANA_STORMLIMIT_BURST, 0x0089b4),
50 REG(ANA_STORMLIMIT_CFG, 0x0089b8),
51 REG(ANA_ISOLATED_PORTS, 0x0089c8),
52 REG(ANA_COMMUNITY_PORTS, 0x0089cc),
53 REG(ANA_AUTOAGE, 0x0089d0),
54 REG(ANA_MACTOPTIONS, 0x0089d4),
55 REG(ANA_LEARNDISC, 0x0089d8),
56 REG(ANA_AGENCTRL, 0x0089dc),
57 REG(ANA_MIRRORPORTS, 0x0089e0),
58 REG(ANA_EMIRRORPORTS, 0x0089e4),
59 REG(ANA_FLOODING, 0x0089e8),
60 REG(ANA_FLOODING_IPMC, 0x008a08),
61 REG(ANA_SFLOW_CFG, 0x008a0c),
62 REG(ANA_PORT_MODE, 0x008a28),
63 REG(ANA_CUT_THRU_CFG, 0x008a48),
64 REG(ANA_PGID_PGID, 0x008400),
65 REG(ANA_TABLES_ANMOVED, 0x007f1c),
66 REG(ANA_TABLES_MACHDATA, 0x007f20),
67 REG(ANA_TABLES_MACLDATA, 0x007f24),
68 REG(ANA_TABLES_STREAMDATA, 0x007f28),
69 REG(ANA_TABLES_MACACCESS, 0x007f2c),
70 REG(ANA_TABLES_MACTINDX, 0x007f30),
71 REG(ANA_TABLES_VLANACCESS, 0x007f34),
72 REG(ANA_TABLES_VLANTIDX, 0x007f38),
73 REG(ANA_TABLES_ISDXACCESS, 0x007f3c),
74 REG(ANA_TABLES_ISDXTIDX, 0x007f40),
75 REG(ANA_TABLES_ENTRYLIM, 0x007f00),
76 REG(ANA_TABLES_PTP_ID_HIGH, 0x007f44),
77 REG(ANA_TABLES_PTP_ID_LOW, 0x007f48),
78 REG(ANA_TABLES_STREAMACCESS, 0x007f4c),
79 REG(ANA_TABLES_STREAMTIDX, 0x007f50),
80 REG(ANA_TABLES_SEQ_HISTORY, 0x007f54),
81 REG(ANA_TABLES_SEQ_MASK, 0x007f58),
82 REG(ANA_TABLES_SFID_MASK, 0x007f5c),
83 REG(ANA_TABLES_SFIDACCESS, 0x007f60),
84 REG(ANA_TABLES_SFIDTIDX, 0x007f64),
85 REG(ANA_MSTI_STATE, 0x008600),
86 REG(ANA_OAM_UPM_LM_CNT, 0x008000),
87 REG(ANA_SG_ACCESS_CTRL, 0x008a64),
88 REG(ANA_SG_CONFIG_REG_1, 0x007fb0),
89 REG(ANA_SG_CONFIG_REG_2, 0x007fb4),
90 REG(ANA_SG_CONFIG_REG_3, 0x007fb8),
91 REG(ANA_SG_CONFIG_REG_4, 0x007fbc),
92 REG(ANA_SG_CONFIG_REG_5, 0x007fc0),
93 REG(ANA_SG_GCL_GS_CONFIG, 0x007f80),
94 REG(ANA_SG_GCL_TI_CONFIG, 0x007f90),
95 REG(ANA_SG_STATUS_REG_1, 0x008980),
96 REG(ANA_SG_STATUS_REG_2, 0x008984),
97 REG(ANA_SG_STATUS_REG_3, 0x008988),
98 REG(ANA_PORT_VLAN_CFG, 0x007800),
99 REG(ANA_PORT_DROP_CFG, 0x007804),
100 REG(ANA_PORT_QOS_CFG, 0x007808),
101 REG(ANA_PORT_VCAP_CFG, 0x00780c),
102 REG(ANA_PORT_VCAP_S1_KEY_CFG, 0x007810),
103 REG(ANA_PORT_VCAP_S2_CFG, 0x00781c),
104 REG(ANA_PORT_PCP_DEI_MAP, 0x007820),
105 REG(ANA_PORT_CPU_FWD_CFG, 0x007860),
106 REG(ANA_PORT_CPU_FWD_BPDU_CFG, 0x007864),
107 REG(ANA_PORT_CPU_FWD_GARP_CFG, 0x007868),
108 REG(ANA_PORT_CPU_FWD_CCM_CFG, 0x00786c),
109 REG(ANA_PORT_PORT_CFG, 0x007870),
110 REG(ANA_PORT_POL_CFG, 0x007874),
111 REG(ANA_PORT_PTP_CFG, 0x007878),
112 REG(ANA_PORT_PTP_DLY1_CFG, 0x00787c),
113 REG(ANA_PORT_PTP_DLY2_CFG, 0x007880),
114 REG(ANA_PORT_SFID_CFG, 0x007884),
115 REG(ANA_PFC_PFC_CFG, 0x008800),
116 REG_RESERVED(ANA_PFC_PFC_TIMER),
117 REG_RESERVED(ANA_IPT_OAM_MEP_CFG),
118 REG_RESERVED(ANA_IPT_IPT),
119 REG_RESERVED(ANA_PPT_PPT),
120 REG_RESERVED(ANA_FID_MAP_FID_MAP),
121 REG(ANA_AGGR_CFG, 0x008a68),
122 REG(ANA_CPUQ_CFG, 0x008a6c),
123 REG_RESERVED(ANA_CPUQ_CFG2),
124 REG(ANA_CPUQ_8021_CFG, 0x008a74),
125 REG(ANA_DSCP_CFG, 0x008ab4),
126 REG(ANA_DSCP_REWR_CFG, 0x008bb4),
127 REG(ANA_VCAP_RNG_TYPE_CFG, 0x008bf4),
128 REG(ANA_VCAP_RNG_VAL_CFG, 0x008c14),
129 REG_RESERVED(ANA_VRAP_CFG),
130 REG_RESERVED(ANA_VRAP_HDR_DATA),
131 REG_RESERVED(ANA_VRAP_HDR_MASK),
132 REG(ANA_DISCARD_CFG, 0x008c40),
133 REG(ANA_FID_CFG, 0x008c44),
134 REG(ANA_POL_PIR_CFG, 0x004000),
135 REG(ANA_POL_CIR_CFG, 0x004004),
136 REG(ANA_POL_MODE_CFG, 0x004008),
137 REG(ANA_POL_PIR_STATE, 0x00400c),
138 REG(ANA_POL_CIR_STATE, 0x004010),
139 REG_RESERVED(ANA_POL_STATE),
140 REG(ANA_POL_FLOWC, 0x008c48),
141 REG(ANA_POL_HYST, 0x008cb4),
142 REG_RESERVED(ANA_POL_MISC_CFG),
145 static const u32 vsc9959_qs_regmap[] = {
146 REG(QS_XTR_GRP_CFG, 0x000000),
147 REG(QS_XTR_RD, 0x000008),
148 REG(QS_XTR_FRM_PRUNING, 0x000010),
149 REG(QS_XTR_FLUSH, 0x000018),
150 REG(QS_XTR_DATA_PRESENT, 0x00001c),
151 REG(QS_XTR_CFG, 0x000020),
152 REG(QS_INJ_GRP_CFG, 0x000024),
153 REG(QS_INJ_WR, 0x00002c),
154 REG(QS_INJ_CTRL, 0x000034),
155 REG(QS_INJ_STATUS, 0x00003c),
156 REG(QS_INJ_ERR, 0x000040),
157 REG_RESERVED(QS_INH_DBG),
160 static const u32 vsc9959_vcap_regmap[] = {
162 REG(VCAP_CORE_UPDATE_CTRL, 0x000000),
163 REG(VCAP_CORE_MV_CFG, 0x000004),
164 /* VCAP_CORE_CACHE */
165 REG(VCAP_CACHE_ENTRY_DAT, 0x000008),
166 REG(VCAP_CACHE_MASK_DAT, 0x000108),
167 REG(VCAP_CACHE_ACTION_DAT, 0x000208),
168 REG(VCAP_CACHE_CNT_DAT, 0x000308),
169 REG(VCAP_CACHE_TG_DAT, 0x000388),
171 REG(VCAP_CONST_VCAP_VER, 0x000398),
172 REG(VCAP_CONST_ENTRY_WIDTH, 0x00039c),
173 REG(VCAP_CONST_ENTRY_CNT, 0x0003a0),
174 REG(VCAP_CONST_ENTRY_SWCNT, 0x0003a4),
175 REG(VCAP_CONST_ENTRY_TG_WIDTH, 0x0003a8),
176 REG(VCAP_CONST_ACTION_DEF_CNT, 0x0003ac),
177 REG(VCAP_CONST_ACTION_WIDTH, 0x0003b0),
178 REG(VCAP_CONST_CNT_WIDTH, 0x0003b4),
179 REG(VCAP_CONST_CORE_CNT, 0x0003b8),
180 REG(VCAP_CONST_IF_CNT, 0x0003bc),
183 static const u32 vsc9959_qsys_regmap[] = {
184 REG(QSYS_PORT_MODE, 0x00f460),
185 REG(QSYS_SWITCH_PORT_MODE, 0x00f480),
186 REG(QSYS_STAT_CNT_CFG, 0x00f49c),
187 REG(QSYS_EEE_CFG, 0x00f4a0),
188 REG(QSYS_EEE_THRES, 0x00f4b8),
189 REG(QSYS_IGR_NO_SHARING, 0x00f4bc),
190 REG(QSYS_EGR_NO_SHARING, 0x00f4c0),
191 REG(QSYS_SW_STATUS, 0x00f4c4),
192 REG(QSYS_EXT_CPU_CFG, 0x00f4e0),
193 REG_RESERVED(QSYS_PAD_CFG),
194 REG(QSYS_CPU_GROUP_MAP, 0x00f4e8),
195 REG_RESERVED(QSYS_QMAP),
196 REG_RESERVED(QSYS_ISDX_SGRP),
197 REG_RESERVED(QSYS_TIMED_FRAME_ENTRY),
198 REG(QSYS_TFRM_MISC, 0x00f50c),
199 REG(QSYS_TFRM_PORT_DLY, 0x00f510),
200 REG(QSYS_TFRM_TIMER_CFG_1, 0x00f514),
201 REG(QSYS_TFRM_TIMER_CFG_2, 0x00f518),
202 REG(QSYS_TFRM_TIMER_CFG_3, 0x00f51c),
203 REG(QSYS_TFRM_TIMER_CFG_4, 0x00f520),
204 REG(QSYS_TFRM_TIMER_CFG_5, 0x00f524),
205 REG(QSYS_TFRM_TIMER_CFG_6, 0x00f528),
206 REG(QSYS_TFRM_TIMER_CFG_7, 0x00f52c),
207 REG(QSYS_TFRM_TIMER_CFG_8, 0x00f530),
208 REG(QSYS_RED_PROFILE, 0x00f534),
209 REG(QSYS_RES_QOS_MODE, 0x00f574),
210 REG(QSYS_RES_CFG, 0x00c000),
211 REG(QSYS_RES_STAT, 0x00c004),
212 REG(QSYS_EGR_DROP_MODE, 0x00f578),
213 REG(QSYS_EQ_CTRL, 0x00f57c),
214 REG_RESERVED(QSYS_EVENTS_CORE),
215 REG(QSYS_QMAXSDU_CFG_0, 0x00f584),
216 REG(QSYS_QMAXSDU_CFG_1, 0x00f5a0),
217 REG(QSYS_QMAXSDU_CFG_2, 0x00f5bc),
218 REG(QSYS_QMAXSDU_CFG_3, 0x00f5d8),
219 REG(QSYS_QMAXSDU_CFG_4, 0x00f5f4),
220 REG(QSYS_QMAXSDU_CFG_5, 0x00f610),
221 REG(QSYS_QMAXSDU_CFG_6, 0x00f62c),
222 REG(QSYS_QMAXSDU_CFG_7, 0x00f648),
223 REG(QSYS_PREEMPTION_CFG, 0x00f664),
224 REG(QSYS_CIR_CFG, 0x000000),
225 REG(QSYS_EIR_CFG, 0x000004),
226 REG(QSYS_SE_CFG, 0x000008),
227 REG(QSYS_SE_DWRR_CFG, 0x00000c),
228 REG_RESERVED(QSYS_SE_CONNECT),
229 REG(QSYS_SE_DLB_SENSE, 0x000040),
230 REG(QSYS_CIR_STATE, 0x000044),
231 REG(QSYS_EIR_STATE, 0x000048),
232 REG_RESERVED(QSYS_SE_STATE),
233 REG(QSYS_HSCH_MISC_CFG, 0x00f67c),
234 REG(QSYS_TAG_CONFIG, 0x00f680),
235 REG(QSYS_TAS_PARAM_CFG_CTRL, 0x00f698),
236 REG(QSYS_PORT_MAX_SDU, 0x00f69c),
237 REG(QSYS_PARAM_CFG_REG_1, 0x00f440),
238 REG(QSYS_PARAM_CFG_REG_2, 0x00f444),
239 REG(QSYS_PARAM_CFG_REG_3, 0x00f448),
240 REG(QSYS_PARAM_CFG_REG_4, 0x00f44c),
241 REG(QSYS_PARAM_CFG_REG_5, 0x00f450),
242 REG(QSYS_GCL_CFG_REG_1, 0x00f454),
243 REG(QSYS_GCL_CFG_REG_2, 0x00f458),
244 REG(QSYS_PARAM_STATUS_REG_1, 0x00f400),
245 REG(QSYS_PARAM_STATUS_REG_2, 0x00f404),
246 REG(QSYS_PARAM_STATUS_REG_3, 0x00f408),
247 REG(QSYS_PARAM_STATUS_REG_4, 0x00f40c),
248 REG(QSYS_PARAM_STATUS_REG_5, 0x00f410),
249 REG(QSYS_PARAM_STATUS_REG_6, 0x00f414),
250 REG(QSYS_PARAM_STATUS_REG_7, 0x00f418),
251 REG(QSYS_PARAM_STATUS_REG_8, 0x00f41c),
252 REG(QSYS_PARAM_STATUS_REG_9, 0x00f420),
253 REG(QSYS_GCL_STATUS_REG_1, 0x00f424),
254 REG(QSYS_GCL_STATUS_REG_2, 0x00f428),
257 static const u32 vsc9959_rew_regmap[] = {
258 REG(REW_PORT_VLAN_CFG, 0x000000),
259 REG(REW_TAG_CFG, 0x000004),
260 REG(REW_PORT_CFG, 0x000008),
261 REG(REW_DSCP_CFG, 0x00000c),
262 REG(REW_PCP_DEI_QOS_MAP_CFG, 0x000010),
263 REG(REW_PTP_CFG, 0x000050),
264 REG(REW_PTP_DLY1_CFG, 0x000054),
265 REG(REW_RED_TAG_CFG, 0x000058),
266 REG(REW_DSCP_REMAP_DP1_CFG, 0x000410),
267 REG(REW_DSCP_REMAP_CFG, 0x000510),
268 REG_RESERVED(REW_STAT_CFG),
269 REG_RESERVED(REW_REW_STICKY),
270 REG_RESERVED(REW_PPT),
273 static const u32 vsc9959_sys_regmap[] = {
274 REG(SYS_COUNT_RX_OCTETS, 0x000000),
275 REG(SYS_COUNT_RX_MULTICAST, 0x000008),
276 REG(SYS_COUNT_RX_SHORTS, 0x000010),
277 REG(SYS_COUNT_RX_FRAGMENTS, 0x000014),
278 REG(SYS_COUNT_RX_JABBERS, 0x000018),
279 REG(SYS_COUNT_RX_64, 0x000024),
280 REG(SYS_COUNT_RX_65_127, 0x000028),
281 REG(SYS_COUNT_RX_128_255, 0x00002c),
282 REG(SYS_COUNT_RX_256_1023, 0x000030),
283 REG(SYS_COUNT_RX_1024_1526, 0x000034),
284 REG(SYS_COUNT_RX_1527_MAX, 0x000038),
285 REG(SYS_COUNT_RX_LONGS, 0x000044),
286 REG(SYS_COUNT_TX_OCTETS, 0x000200),
287 REG(SYS_COUNT_TX_COLLISION, 0x000210),
288 REG(SYS_COUNT_TX_DROPS, 0x000214),
289 REG(SYS_COUNT_TX_64, 0x00021c),
290 REG(SYS_COUNT_TX_65_127, 0x000220),
291 REG(SYS_COUNT_TX_128_511, 0x000224),
292 REG(SYS_COUNT_TX_512_1023, 0x000228),
293 REG(SYS_COUNT_TX_1024_1526, 0x00022c),
294 REG(SYS_COUNT_TX_1527_MAX, 0x000230),
295 REG(SYS_COUNT_TX_AGING, 0x000278),
296 REG(SYS_RESET_CFG, 0x000e00),
297 REG(SYS_SR_ETYPE_CFG, 0x000e04),
298 REG(SYS_VLAN_ETYPE_CFG, 0x000e08),
299 REG(SYS_PORT_MODE, 0x000e0c),
300 REG(SYS_FRONT_PORT_MODE, 0x000e2c),
301 REG(SYS_FRM_AGING, 0x000e44),
302 REG(SYS_STAT_CFG, 0x000e48),
303 REG(SYS_SW_STATUS, 0x000e4c),
304 REG_RESERVED(SYS_MISC_CFG),
305 REG(SYS_REW_MAC_HIGH_CFG, 0x000e6c),
306 REG(SYS_REW_MAC_LOW_CFG, 0x000e84),
307 REG(SYS_TIMESTAMP_OFFSET, 0x000e9c),
308 REG(SYS_PAUSE_CFG, 0x000ea0),
309 REG(SYS_PAUSE_TOT_CFG, 0x000ebc),
310 REG(SYS_ATOP, 0x000ec0),
311 REG(SYS_ATOP_TOT_CFG, 0x000edc),
312 REG(SYS_MAC_FC_CFG, 0x000ee0),
313 REG(SYS_MMGT, 0x000ef8),
314 REG_RESERVED(SYS_MMGT_FAST),
315 REG_RESERVED(SYS_EVENTS_DIF),
316 REG_RESERVED(SYS_EVENTS_CORE),
317 REG(SYS_CNT, 0x000000),
318 REG(SYS_PTP_STATUS, 0x000f14),
319 REG(SYS_PTP_TXSTAMP, 0x000f18),
320 REG(SYS_PTP_NXT, 0x000f1c),
321 REG(SYS_PTP_CFG, 0x000f20),
322 REG(SYS_RAM_INIT, 0x000f24),
323 REG_RESERVED(SYS_CM_ADDR),
324 REG_RESERVED(SYS_CM_DATA_WR),
325 REG_RESERVED(SYS_CM_DATA_RD),
326 REG_RESERVED(SYS_CM_OP),
327 REG_RESERVED(SYS_CM_DATA),
330 static const u32 vsc9959_ptp_regmap[] = {
331 REG(PTP_PIN_CFG, 0x000000),
332 REG(PTP_PIN_TOD_SEC_MSB, 0x000004),
333 REG(PTP_PIN_TOD_SEC_LSB, 0x000008),
334 REG(PTP_PIN_TOD_NSEC, 0x00000c),
335 REG(PTP_PIN_WF_HIGH_PERIOD, 0x000014),
336 REG(PTP_PIN_WF_LOW_PERIOD, 0x000018),
337 REG(PTP_CFG_MISC, 0x0000a0),
338 REG(PTP_CLK_CFG_ADJ_CFG, 0x0000a4),
339 REG(PTP_CLK_CFG_ADJ_FREQ, 0x0000a8),
342 static const u32 vsc9959_gcb_regmap[] = {
343 REG(GCB_SOFT_RST, 0x000004),
346 static const u32 vsc9959_dev_gmii_regmap[] = {
347 REG(DEV_CLOCK_CFG, 0x0),
348 REG(DEV_PORT_MISC, 0x4),
349 REG(DEV_EVENTS, 0x8),
350 REG(DEV_EEE_CFG, 0xc),
351 REG(DEV_RX_PATH_DELAY, 0x10),
352 REG(DEV_TX_PATH_DELAY, 0x14),
353 REG(DEV_PTP_PREDICT_CFG, 0x18),
354 REG(DEV_MAC_ENA_CFG, 0x1c),
355 REG(DEV_MAC_MODE_CFG, 0x20),
356 REG(DEV_MAC_MAXLEN_CFG, 0x24),
357 REG(DEV_MAC_TAGS_CFG, 0x28),
358 REG(DEV_MAC_ADV_CHK_CFG, 0x2c),
359 REG(DEV_MAC_IFG_CFG, 0x30),
360 REG(DEV_MAC_HDX_CFG, 0x34),
361 REG(DEV_MAC_DBG_CFG, 0x38),
362 REG(DEV_MAC_FC_MAC_LOW_CFG, 0x3c),
363 REG(DEV_MAC_FC_MAC_HIGH_CFG, 0x40),
364 REG(DEV_MAC_STICKY, 0x44),
365 REG_RESERVED(PCS1G_CFG),
366 REG_RESERVED(PCS1G_MODE_CFG),
367 REG_RESERVED(PCS1G_SD_CFG),
368 REG_RESERVED(PCS1G_ANEG_CFG),
369 REG_RESERVED(PCS1G_ANEG_NP_CFG),
370 REG_RESERVED(PCS1G_LB_CFG),
371 REG_RESERVED(PCS1G_DBG_CFG),
372 REG_RESERVED(PCS1G_CDET_CFG),
373 REG_RESERVED(PCS1G_ANEG_STATUS),
374 REG_RESERVED(PCS1G_ANEG_NP_STATUS),
375 REG_RESERVED(PCS1G_LINK_STATUS),
376 REG_RESERVED(PCS1G_LINK_DOWN_CNT),
377 REG_RESERVED(PCS1G_STICKY),
378 REG_RESERVED(PCS1G_DEBUG_STATUS),
379 REG_RESERVED(PCS1G_LPI_CFG),
380 REG_RESERVED(PCS1G_LPI_WAKE_ERROR_CNT),
381 REG_RESERVED(PCS1G_LPI_STATUS),
382 REG_RESERVED(PCS1G_TSTPAT_MODE_CFG),
383 REG_RESERVED(PCS1G_TSTPAT_STATUS),
384 REG_RESERVED(DEV_PCS_FX100_CFG),
385 REG_RESERVED(DEV_PCS_FX100_STATUS),
388 static const u32 *vsc9959_regmap[TARGET_MAX] = {
389 [ANA] = vsc9959_ana_regmap,
390 [QS] = vsc9959_qs_regmap,
391 [QSYS] = vsc9959_qsys_regmap,
392 [REW] = vsc9959_rew_regmap,
393 [SYS] = vsc9959_sys_regmap,
394 [S0] = vsc9959_vcap_regmap,
395 [S1] = vsc9959_vcap_regmap,
396 [S2] = vsc9959_vcap_regmap,
397 [PTP] = vsc9959_ptp_regmap,
398 [GCB] = vsc9959_gcb_regmap,
399 [DEV_GMII] = vsc9959_dev_gmii_regmap,
402 /* Addresses are relative to the PCI device's base address */
403 static const struct resource vsc9959_target_io_res[TARGET_MAX] = {
452 .name = "devcpu_gcb",
456 static const struct resource vsc9959_port_io_res[] = {
489 /* Port MAC 0 Internal MDIO bus through which the SerDes acting as an
490 * SGMII/QSGMII MAC PCS can be found.
492 static const struct resource vsc9959_imdio_res = {
498 static const struct reg_field vsc9959_regfields[REGFIELD_MAX] = {
499 [ANA_ADVLEARN_VLAN_CHK] = REG_FIELD(ANA_ADVLEARN, 6, 6),
500 [ANA_ADVLEARN_LEARN_MIRROR] = REG_FIELD(ANA_ADVLEARN, 0, 5),
501 [ANA_ANEVENTS_FLOOD_DISCARD] = REG_FIELD(ANA_ANEVENTS, 30, 30),
502 [ANA_ANEVENTS_AUTOAGE] = REG_FIELD(ANA_ANEVENTS, 26, 26),
503 [ANA_ANEVENTS_STORM_DROP] = REG_FIELD(ANA_ANEVENTS, 24, 24),
504 [ANA_ANEVENTS_LEARN_DROP] = REG_FIELD(ANA_ANEVENTS, 23, 23),
505 [ANA_ANEVENTS_AGED_ENTRY] = REG_FIELD(ANA_ANEVENTS, 22, 22),
506 [ANA_ANEVENTS_CPU_LEARN_FAILED] = REG_FIELD(ANA_ANEVENTS, 21, 21),
507 [ANA_ANEVENTS_AUTO_LEARN_FAILED] = REG_FIELD(ANA_ANEVENTS, 20, 20),
508 [ANA_ANEVENTS_LEARN_REMOVE] = REG_FIELD(ANA_ANEVENTS, 19, 19),
509 [ANA_ANEVENTS_AUTO_LEARNED] = REG_FIELD(ANA_ANEVENTS, 18, 18),
510 [ANA_ANEVENTS_AUTO_MOVED] = REG_FIELD(ANA_ANEVENTS, 17, 17),
511 [ANA_ANEVENTS_CLASSIFIED_DROP] = REG_FIELD(ANA_ANEVENTS, 15, 15),
512 [ANA_ANEVENTS_CLASSIFIED_COPY] = REG_FIELD(ANA_ANEVENTS, 14, 14),
513 [ANA_ANEVENTS_VLAN_DISCARD] = REG_FIELD(ANA_ANEVENTS, 13, 13),
514 [ANA_ANEVENTS_FWD_DISCARD] = REG_FIELD(ANA_ANEVENTS, 12, 12),
515 [ANA_ANEVENTS_MULTICAST_FLOOD] = REG_FIELD(ANA_ANEVENTS, 11, 11),
516 [ANA_ANEVENTS_UNICAST_FLOOD] = REG_FIELD(ANA_ANEVENTS, 10, 10),
517 [ANA_ANEVENTS_DEST_KNOWN] = REG_FIELD(ANA_ANEVENTS, 9, 9),
518 [ANA_ANEVENTS_BUCKET3_MATCH] = REG_FIELD(ANA_ANEVENTS, 8, 8),
519 [ANA_ANEVENTS_BUCKET2_MATCH] = REG_FIELD(ANA_ANEVENTS, 7, 7),
520 [ANA_ANEVENTS_BUCKET1_MATCH] = REG_FIELD(ANA_ANEVENTS, 6, 6),
521 [ANA_ANEVENTS_BUCKET0_MATCH] = REG_FIELD(ANA_ANEVENTS, 5, 5),
522 [ANA_ANEVENTS_CPU_OPERATION] = REG_FIELD(ANA_ANEVENTS, 4, 4),
523 [ANA_ANEVENTS_DMAC_LOOKUP] = REG_FIELD(ANA_ANEVENTS, 3, 3),
524 [ANA_ANEVENTS_SMAC_LOOKUP] = REG_FIELD(ANA_ANEVENTS, 2, 2),
525 [ANA_ANEVENTS_SEQ_GEN_ERR_0] = REG_FIELD(ANA_ANEVENTS, 1, 1),
526 [ANA_ANEVENTS_SEQ_GEN_ERR_1] = REG_FIELD(ANA_ANEVENTS, 0, 0),
527 [ANA_TABLES_MACACCESS_B_DOM] = REG_FIELD(ANA_TABLES_MACACCESS, 16, 16),
528 [ANA_TABLES_MACTINDX_BUCKET] = REG_FIELD(ANA_TABLES_MACTINDX, 11, 12),
529 [ANA_TABLES_MACTINDX_M_INDEX] = REG_FIELD(ANA_TABLES_MACTINDX, 0, 10),
530 [SYS_RESET_CFG_CORE_ENA] = REG_FIELD(SYS_RESET_CFG, 0, 0),
531 [GCB_SOFT_RST_SWC_RST] = REG_FIELD(GCB_SOFT_RST, 0, 0),
532 /* Replicated per number of ports (7), register size 4 per port */
533 [QSYS_SWITCH_PORT_MODE_PORT_ENA] = REG_FIELD_ID(QSYS_SWITCH_PORT_MODE, 14, 14, 7, 4),
534 [QSYS_SWITCH_PORT_MODE_SCH_NEXT_CFG] = REG_FIELD_ID(QSYS_SWITCH_PORT_MODE, 11, 13, 7, 4),
535 [QSYS_SWITCH_PORT_MODE_YEL_RSRVD] = REG_FIELD_ID(QSYS_SWITCH_PORT_MODE, 10, 10, 7, 4),
536 [QSYS_SWITCH_PORT_MODE_INGRESS_DROP_MODE] = REG_FIELD_ID(QSYS_SWITCH_PORT_MODE, 9, 9, 7, 4),
537 [QSYS_SWITCH_PORT_MODE_TX_PFC_ENA] = REG_FIELD_ID(QSYS_SWITCH_PORT_MODE, 1, 8, 7, 4),
538 [QSYS_SWITCH_PORT_MODE_TX_PFC_MODE] = REG_FIELD_ID(QSYS_SWITCH_PORT_MODE, 0, 0, 7, 4),
539 [SYS_PORT_MODE_DATA_WO_TS] = REG_FIELD_ID(SYS_PORT_MODE, 5, 6, 7, 4),
540 [SYS_PORT_MODE_INCL_INJ_HDR] = REG_FIELD_ID(SYS_PORT_MODE, 3, 4, 7, 4),
541 [SYS_PORT_MODE_INCL_XTR_HDR] = REG_FIELD_ID(SYS_PORT_MODE, 1, 2, 7, 4),
542 [SYS_PORT_MODE_INCL_HDR_ERR] = REG_FIELD_ID(SYS_PORT_MODE, 0, 0, 7, 4),
543 [SYS_PAUSE_CFG_PAUSE_START] = REG_FIELD_ID(SYS_PAUSE_CFG, 10, 18, 7, 4),
544 [SYS_PAUSE_CFG_PAUSE_STOP] = REG_FIELD_ID(SYS_PAUSE_CFG, 1, 9, 7, 4),
545 [SYS_PAUSE_CFG_PAUSE_ENA] = REG_FIELD_ID(SYS_PAUSE_CFG, 0, 1, 7, 4),
548 static const struct ocelot_stat_layout vsc9959_stats_layout[] = {
549 { .offset = 0x00, .name = "rx_octets", },
550 { .offset = 0x01, .name = "rx_unicast", },
551 { .offset = 0x02, .name = "rx_multicast", },
552 { .offset = 0x03, .name = "rx_broadcast", },
553 { .offset = 0x04, .name = "rx_shorts", },
554 { .offset = 0x05, .name = "rx_fragments", },
555 { .offset = 0x06, .name = "rx_jabbers", },
556 { .offset = 0x07, .name = "rx_crc_align_errs", },
557 { .offset = 0x08, .name = "rx_sym_errs", },
558 { .offset = 0x09, .name = "rx_frames_below_65_octets", },
559 { .offset = 0x0A, .name = "rx_frames_65_to_127_octets", },
560 { .offset = 0x0B, .name = "rx_frames_128_to_255_octets", },
561 { .offset = 0x0C, .name = "rx_frames_256_to_511_octets", },
562 { .offset = 0x0D, .name = "rx_frames_512_to_1023_octets", },
563 { .offset = 0x0E, .name = "rx_frames_1024_to_1526_octets", },
564 { .offset = 0x0F, .name = "rx_frames_over_1526_octets", },
565 { .offset = 0x10, .name = "rx_pause", },
566 { .offset = 0x11, .name = "rx_control", },
567 { .offset = 0x12, .name = "rx_longs", },
568 { .offset = 0x13, .name = "rx_classified_drops", },
569 { .offset = 0x14, .name = "rx_red_prio_0", },
570 { .offset = 0x15, .name = "rx_red_prio_1", },
571 { .offset = 0x16, .name = "rx_red_prio_2", },
572 { .offset = 0x17, .name = "rx_red_prio_3", },
573 { .offset = 0x18, .name = "rx_red_prio_4", },
574 { .offset = 0x19, .name = "rx_red_prio_5", },
575 { .offset = 0x1A, .name = "rx_red_prio_6", },
576 { .offset = 0x1B, .name = "rx_red_prio_7", },
577 { .offset = 0x1C, .name = "rx_yellow_prio_0", },
578 { .offset = 0x1D, .name = "rx_yellow_prio_1", },
579 { .offset = 0x1E, .name = "rx_yellow_prio_2", },
580 { .offset = 0x1F, .name = "rx_yellow_prio_3", },
581 { .offset = 0x20, .name = "rx_yellow_prio_4", },
582 { .offset = 0x21, .name = "rx_yellow_prio_5", },
583 { .offset = 0x22, .name = "rx_yellow_prio_6", },
584 { .offset = 0x23, .name = "rx_yellow_prio_7", },
585 { .offset = 0x24, .name = "rx_green_prio_0", },
586 { .offset = 0x25, .name = "rx_green_prio_1", },
587 { .offset = 0x26, .name = "rx_green_prio_2", },
588 { .offset = 0x27, .name = "rx_green_prio_3", },
589 { .offset = 0x28, .name = "rx_green_prio_4", },
590 { .offset = 0x29, .name = "rx_green_prio_5", },
591 { .offset = 0x2A, .name = "rx_green_prio_6", },
592 { .offset = 0x2B, .name = "rx_green_prio_7", },
593 { .offset = 0x80, .name = "tx_octets", },
594 { .offset = 0x81, .name = "tx_unicast", },
595 { .offset = 0x82, .name = "tx_multicast", },
596 { .offset = 0x83, .name = "tx_broadcast", },
597 { .offset = 0x84, .name = "tx_collision", },
598 { .offset = 0x85, .name = "tx_drops", },
599 { .offset = 0x86, .name = "tx_pause", },
600 { .offset = 0x87, .name = "tx_frames_below_65_octets", },
601 { .offset = 0x88, .name = "tx_frames_65_to_127_octets", },
602 { .offset = 0x89, .name = "tx_frames_128_255_octets", },
603 { .offset = 0x8B, .name = "tx_frames_256_511_octets", },
604 { .offset = 0x8C, .name = "tx_frames_1024_1526_octets", },
605 { .offset = 0x8D, .name = "tx_frames_over_1526_octets", },
606 { .offset = 0x8E, .name = "tx_yellow_prio_0", },
607 { .offset = 0x8F, .name = "tx_yellow_prio_1", },
608 { .offset = 0x90, .name = "tx_yellow_prio_2", },
609 { .offset = 0x91, .name = "tx_yellow_prio_3", },
610 { .offset = 0x92, .name = "tx_yellow_prio_4", },
611 { .offset = 0x93, .name = "tx_yellow_prio_5", },
612 { .offset = 0x94, .name = "tx_yellow_prio_6", },
613 { .offset = 0x95, .name = "tx_yellow_prio_7", },
614 { .offset = 0x96, .name = "tx_green_prio_0", },
615 { .offset = 0x97, .name = "tx_green_prio_1", },
616 { .offset = 0x98, .name = "tx_green_prio_2", },
617 { .offset = 0x99, .name = "tx_green_prio_3", },
618 { .offset = 0x9A, .name = "tx_green_prio_4", },
619 { .offset = 0x9B, .name = "tx_green_prio_5", },
620 { .offset = 0x9C, .name = "tx_green_prio_6", },
621 { .offset = 0x9D, .name = "tx_green_prio_7", },
622 { .offset = 0x9E, .name = "tx_aged", },
623 { .offset = 0x100, .name = "drop_local", },
624 { .offset = 0x101, .name = "drop_tail", },
625 { .offset = 0x102, .name = "drop_yellow_prio_0", },
626 { .offset = 0x103, .name = "drop_yellow_prio_1", },
627 { .offset = 0x104, .name = "drop_yellow_prio_2", },
628 { .offset = 0x105, .name = "drop_yellow_prio_3", },
629 { .offset = 0x106, .name = "drop_yellow_prio_4", },
630 { .offset = 0x107, .name = "drop_yellow_prio_5", },
631 { .offset = 0x108, .name = "drop_yellow_prio_6", },
632 { .offset = 0x109, .name = "drop_yellow_prio_7", },
633 { .offset = 0x10A, .name = "drop_green_prio_0", },
634 { .offset = 0x10B, .name = "drop_green_prio_1", },
635 { .offset = 0x10C, .name = "drop_green_prio_2", },
636 { .offset = 0x10D, .name = "drop_green_prio_3", },
637 { .offset = 0x10E, .name = "drop_green_prio_4", },
638 { .offset = 0x10F, .name = "drop_green_prio_5", },
639 { .offset = 0x110, .name = "drop_green_prio_6", },
640 { .offset = 0x111, .name = "drop_green_prio_7", },
643 static const struct vcap_field vsc9959_vcap_es0_keys[] = {
644 [VCAP_ES0_EGR_PORT] = { 0, 3},
645 [VCAP_ES0_IGR_PORT] = { 3, 3},
646 [VCAP_ES0_RSV] = { 6, 2},
647 [VCAP_ES0_L2_MC] = { 8, 1},
648 [VCAP_ES0_L2_BC] = { 9, 1},
649 [VCAP_ES0_VID] = { 10, 12},
650 [VCAP_ES0_DP] = { 22, 1},
651 [VCAP_ES0_PCP] = { 23, 3},
654 static const struct vcap_field vsc9959_vcap_es0_actions[] = {
655 [VCAP_ES0_ACT_PUSH_OUTER_TAG] = { 0, 2},
656 [VCAP_ES0_ACT_PUSH_INNER_TAG] = { 2, 1},
657 [VCAP_ES0_ACT_TAG_A_TPID_SEL] = { 3, 2},
658 [VCAP_ES0_ACT_TAG_A_VID_SEL] = { 5, 1},
659 [VCAP_ES0_ACT_TAG_A_PCP_SEL] = { 6, 2},
660 [VCAP_ES0_ACT_TAG_A_DEI_SEL] = { 8, 2},
661 [VCAP_ES0_ACT_TAG_B_TPID_SEL] = { 10, 2},
662 [VCAP_ES0_ACT_TAG_B_VID_SEL] = { 12, 1},
663 [VCAP_ES0_ACT_TAG_B_PCP_SEL] = { 13, 2},
664 [VCAP_ES0_ACT_TAG_B_DEI_SEL] = { 15, 2},
665 [VCAP_ES0_ACT_VID_A_VAL] = { 17, 12},
666 [VCAP_ES0_ACT_PCP_A_VAL] = { 29, 3},
667 [VCAP_ES0_ACT_DEI_A_VAL] = { 32, 1},
668 [VCAP_ES0_ACT_VID_B_VAL] = { 33, 12},
669 [VCAP_ES0_ACT_PCP_B_VAL] = { 45, 3},
670 [VCAP_ES0_ACT_DEI_B_VAL] = { 48, 1},
671 [VCAP_ES0_ACT_RSV] = { 49, 23},
672 [VCAP_ES0_ACT_HIT_STICKY] = { 72, 1},
675 static const struct vcap_field vsc9959_vcap_is1_keys[] = {
676 [VCAP_IS1_HK_TYPE] = { 0, 1},
677 [VCAP_IS1_HK_LOOKUP] = { 1, 2},
678 [VCAP_IS1_HK_IGR_PORT_MASK] = { 3, 7},
679 [VCAP_IS1_HK_RSV] = { 10, 9},
680 [VCAP_IS1_HK_OAM_Y1731] = { 19, 1},
681 [VCAP_IS1_HK_L2_MC] = { 20, 1},
682 [VCAP_IS1_HK_L2_BC] = { 21, 1},
683 [VCAP_IS1_HK_IP_MC] = { 22, 1},
684 [VCAP_IS1_HK_VLAN_TAGGED] = { 23, 1},
685 [VCAP_IS1_HK_VLAN_DBL_TAGGED] = { 24, 1},
686 [VCAP_IS1_HK_TPID] = { 25, 1},
687 [VCAP_IS1_HK_VID] = { 26, 12},
688 [VCAP_IS1_HK_DEI] = { 38, 1},
689 [VCAP_IS1_HK_PCP] = { 39, 3},
690 /* Specific Fields for IS1 Half Key S1_NORMAL */
691 [VCAP_IS1_HK_L2_SMAC] = { 42, 48},
692 [VCAP_IS1_HK_ETYPE_LEN] = { 90, 1},
693 [VCAP_IS1_HK_ETYPE] = { 91, 16},
694 [VCAP_IS1_HK_IP_SNAP] = {107, 1},
695 [VCAP_IS1_HK_IP4] = {108, 1},
696 /* Layer-3 Information */
697 [VCAP_IS1_HK_L3_FRAGMENT] = {109, 1},
698 [VCAP_IS1_HK_L3_FRAG_OFS_GT0] = {110, 1},
699 [VCAP_IS1_HK_L3_OPTIONS] = {111, 1},
700 [VCAP_IS1_HK_L3_DSCP] = {112, 6},
701 [VCAP_IS1_HK_L3_IP4_SIP] = {118, 32},
702 /* Layer-4 Information */
703 [VCAP_IS1_HK_TCP_UDP] = {150, 1},
704 [VCAP_IS1_HK_TCP] = {151, 1},
705 [VCAP_IS1_HK_L4_SPORT] = {152, 16},
706 [VCAP_IS1_HK_L4_RNG] = {168, 8},
707 /* Specific Fields for IS1 Half Key S1_5TUPLE_IP4 */
708 [VCAP_IS1_HK_IP4_INNER_TPID] = { 42, 1},
709 [VCAP_IS1_HK_IP4_INNER_VID] = { 43, 12},
710 [VCAP_IS1_HK_IP4_INNER_DEI] = { 55, 1},
711 [VCAP_IS1_HK_IP4_INNER_PCP] = { 56, 3},
712 [VCAP_IS1_HK_IP4_IP4] = { 59, 1},
713 [VCAP_IS1_HK_IP4_L3_FRAGMENT] = { 60, 1},
714 [VCAP_IS1_HK_IP4_L3_FRAG_OFS_GT0] = { 61, 1},
715 [VCAP_IS1_HK_IP4_L3_OPTIONS] = { 62, 1},
716 [VCAP_IS1_HK_IP4_L3_DSCP] = { 63, 6},
717 [VCAP_IS1_HK_IP4_L3_IP4_DIP] = { 69, 32},
718 [VCAP_IS1_HK_IP4_L3_IP4_SIP] = {101, 32},
719 [VCAP_IS1_HK_IP4_L3_PROTO] = {133, 8},
720 [VCAP_IS1_HK_IP4_TCP_UDP] = {141, 1},
721 [VCAP_IS1_HK_IP4_TCP] = {142, 1},
722 [VCAP_IS1_HK_IP4_L4_RNG] = {143, 8},
723 [VCAP_IS1_HK_IP4_IP_PAYLOAD_S1_5TUPLE] = {151, 32},
726 static const struct vcap_field vsc9959_vcap_is1_actions[] = {
727 [VCAP_IS1_ACT_DSCP_ENA] = { 0, 1},
728 [VCAP_IS1_ACT_DSCP_VAL] = { 1, 6},
729 [VCAP_IS1_ACT_QOS_ENA] = { 7, 1},
730 [VCAP_IS1_ACT_QOS_VAL] = { 8, 3},
731 [VCAP_IS1_ACT_DP_ENA] = { 11, 1},
732 [VCAP_IS1_ACT_DP_VAL] = { 12, 1},
733 [VCAP_IS1_ACT_PAG_OVERRIDE_MASK] = { 13, 8},
734 [VCAP_IS1_ACT_PAG_VAL] = { 21, 8},
735 [VCAP_IS1_ACT_RSV] = { 29, 9},
736 /* The fields below are incorrectly shifted by 2 in the manual */
737 [VCAP_IS1_ACT_VID_REPLACE_ENA] = { 38, 1},
738 [VCAP_IS1_ACT_VID_ADD_VAL] = { 39, 12},
739 [VCAP_IS1_ACT_FID_SEL] = { 51, 2},
740 [VCAP_IS1_ACT_FID_VAL] = { 53, 13},
741 [VCAP_IS1_ACT_PCP_DEI_ENA] = { 66, 1},
742 [VCAP_IS1_ACT_PCP_VAL] = { 67, 3},
743 [VCAP_IS1_ACT_DEI_VAL] = { 70, 1},
744 [VCAP_IS1_ACT_VLAN_POP_CNT_ENA] = { 71, 1},
745 [VCAP_IS1_ACT_VLAN_POP_CNT] = { 72, 2},
746 [VCAP_IS1_ACT_CUSTOM_ACE_TYPE_ENA] = { 74, 4},
747 [VCAP_IS1_ACT_HIT_STICKY] = { 78, 1},
750 static struct vcap_field vsc9959_vcap_is2_keys[] = {
751 /* Common: 41 bits */
752 [VCAP_IS2_TYPE] = { 0, 4},
753 [VCAP_IS2_HK_FIRST] = { 4, 1},
754 [VCAP_IS2_HK_PAG] = { 5, 8},
755 [VCAP_IS2_HK_IGR_PORT_MASK] = { 13, 7},
756 [VCAP_IS2_HK_RSV2] = { 20, 1},
757 [VCAP_IS2_HK_HOST_MATCH] = { 21, 1},
758 [VCAP_IS2_HK_L2_MC] = { 22, 1},
759 [VCAP_IS2_HK_L2_BC] = { 23, 1},
760 [VCAP_IS2_HK_VLAN_TAGGED] = { 24, 1},
761 [VCAP_IS2_HK_VID] = { 25, 12},
762 [VCAP_IS2_HK_DEI] = { 37, 1},
763 [VCAP_IS2_HK_PCP] = { 38, 3},
764 /* MAC_ETYPE / MAC_LLC / MAC_SNAP / OAM common */
765 [VCAP_IS2_HK_L2_DMAC] = { 41, 48},
766 [VCAP_IS2_HK_L2_SMAC] = { 89, 48},
767 /* MAC_ETYPE (TYPE=000) */
768 [VCAP_IS2_HK_MAC_ETYPE_ETYPE] = {137, 16},
769 [VCAP_IS2_HK_MAC_ETYPE_L2_PAYLOAD0] = {153, 16},
770 [VCAP_IS2_HK_MAC_ETYPE_L2_PAYLOAD1] = {169, 8},
771 [VCAP_IS2_HK_MAC_ETYPE_L2_PAYLOAD2] = {177, 3},
772 /* MAC_LLC (TYPE=001) */
773 [VCAP_IS2_HK_MAC_LLC_L2_LLC] = {137, 40},
774 /* MAC_SNAP (TYPE=010) */
775 [VCAP_IS2_HK_MAC_SNAP_L2_SNAP] = {137, 40},
776 /* MAC_ARP (TYPE=011) */
777 [VCAP_IS2_HK_MAC_ARP_SMAC] = { 41, 48},
778 [VCAP_IS2_HK_MAC_ARP_ADDR_SPACE_OK] = { 89, 1},
779 [VCAP_IS2_HK_MAC_ARP_PROTO_SPACE_OK] = { 90, 1},
780 [VCAP_IS2_HK_MAC_ARP_LEN_OK] = { 91, 1},
781 [VCAP_IS2_HK_MAC_ARP_TARGET_MATCH] = { 92, 1},
782 [VCAP_IS2_HK_MAC_ARP_SENDER_MATCH] = { 93, 1},
783 [VCAP_IS2_HK_MAC_ARP_OPCODE_UNKNOWN] = { 94, 1},
784 [VCAP_IS2_HK_MAC_ARP_OPCODE] = { 95, 2},
785 [VCAP_IS2_HK_MAC_ARP_L3_IP4_DIP] = { 97, 32},
786 [VCAP_IS2_HK_MAC_ARP_L3_IP4_SIP] = {129, 32},
787 [VCAP_IS2_HK_MAC_ARP_DIP_EQ_SIP] = {161, 1},
788 /* IP4_TCP_UDP / IP4_OTHER common */
789 [VCAP_IS2_HK_IP4] = { 41, 1},
790 [VCAP_IS2_HK_L3_FRAGMENT] = { 42, 1},
791 [VCAP_IS2_HK_L3_FRAG_OFS_GT0] = { 43, 1},
792 [VCAP_IS2_HK_L3_OPTIONS] = { 44, 1},
793 [VCAP_IS2_HK_IP4_L3_TTL_GT0] = { 45, 1},
794 [VCAP_IS2_HK_L3_TOS] = { 46, 8},
795 [VCAP_IS2_HK_L3_IP4_DIP] = { 54, 32},
796 [VCAP_IS2_HK_L3_IP4_SIP] = { 86, 32},
797 [VCAP_IS2_HK_DIP_EQ_SIP] = {118, 1},
798 /* IP4_TCP_UDP (TYPE=100) */
799 [VCAP_IS2_HK_TCP] = {119, 1},
800 [VCAP_IS2_HK_L4_DPORT] = {120, 16},
801 [VCAP_IS2_HK_L4_SPORT] = {136, 16},
802 [VCAP_IS2_HK_L4_RNG] = {152, 8},
803 [VCAP_IS2_HK_L4_SPORT_EQ_DPORT] = {160, 1},
804 [VCAP_IS2_HK_L4_SEQUENCE_EQ0] = {161, 1},
805 [VCAP_IS2_HK_L4_FIN] = {162, 1},
806 [VCAP_IS2_HK_L4_SYN] = {163, 1},
807 [VCAP_IS2_HK_L4_RST] = {164, 1},
808 [VCAP_IS2_HK_L4_PSH] = {165, 1},
809 [VCAP_IS2_HK_L4_ACK] = {166, 1},
810 [VCAP_IS2_HK_L4_URG] = {167, 1},
811 [VCAP_IS2_HK_L4_1588_DOM] = {168, 8},
812 [VCAP_IS2_HK_L4_1588_VER] = {176, 4},
813 /* IP4_OTHER (TYPE=101) */
814 [VCAP_IS2_HK_IP4_L3_PROTO] = {119, 8},
815 [VCAP_IS2_HK_L3_PAYLOAD] = {127, 56},
816 /* IP6_STD (TYPE=110) */
817 [VCAP_IS2_HK_IP6_L3_TTL_GT0] = { 41, 1},
818 [VCAP_IS2_HK_L3_IP6_SIP] = { 42, 128},
819 [VCAP_IS2_HK_IP6_L3_PROTO] = {170, 8},
821 [VCAP_IS2_HK_OAM_MEL_FLAGS] = {137, 7},
822 [VCAP_IS2_HK_OAM_VER] = {144, 5},
823 [VCAP_IS2_HK_OAM_OPCODE] = {149, 8},
824 [VCAP_IS2_HK_OAM_FLAGS] = {157, 8},
825 [VCAP_IS2_HK_OAM_MEPID] = {165, 16},
826 [VCAP_IS2_HK_OAM_CCM_CNTS_EQ0] = {181, 1},
827 [VCAP_IS2_HK_OAM_IS_Y1731] = {182, 1},
830 static struct vcap_field vsc9959_vcap_is2_actions[] = {
831 [VCAP_IS2_ACT_HIT_ME_ONCE] = { 0, 1},
832 [VCAP_IS2_ACT_CPU_COPY_ENA] = { 1, 1},
833 [VCAP_IS2_ACT_CPU_QU_NUM] = { 2, 3},
834 [VCAP_IS2_ACT_MASK_MODE] = { 5, 2},
835 [VCAP_IS2_ACT_MIRROR_ENA] = { 7, 1},
836 [VCAP_IS2_ACT_LRN_DIS] = { 8, 1},
837 [VCAP_IS2_ACT_POLICE_ENA] = { 9, 1},
838 [VCAP_IS2_ACT_POLICE_IDX] = { 10, 9},
839 [VCAP_IS2_ACT_POLICE_VCAP_ONLY] = { 19, 1},
840 [VCAP_IS2_ACT_PORT_MASK] = { 20, 6},
841 [VCAP_IS2_ACT_REW_OP] = { 26, 9},
842 [VCAP_IS2_ACT_SMAC_REPLACE_ENA] = { 35, 1},
843 [VCAP_IS2_ACT_RSV] = { 36, 2},
844 [VCAP_IS2_ACT_ACL_ID] = { 38, 6},
845 [VCAP_IS2_ACT_HIT_CNT] = { 44, 32},
848 static struct vcap_props vsc9959_vcap_props[] = {
850 .action_type_width = 0,
852 [ES0_ACTION_TYPE_NORMAL] = {
853 .width = 72, /* HIT_STICKY not included */
858 .keys = vsc9959_vcap_es0_keys,
859 .actions = vsc9959_vcap_es0_actions,
862 .action_type_width = 0,
864 [IS1_ACTION_TYPE_NORMAL] = {
865 .width = 78, /* HIT_STICKY not included */
870 .keys = vsc9959_vcap_is1_keys,
871 .actions = vsc9959_vcap_is1_actions,
874 .action_type_width = 1,
876 [IS2_ACTION_TYPE_NORMAL] = {
880 [IS2_ACTION_TYPE_SMAC_SIP] = {
886 .keys = vsc9959_vcap_is2_keys,
887 .actions = vsc9959_vcap_is2_actions,
891 static const struct ptp_clock_info vsc9959_ptp_caps = {
892 .owner = THIS_MODULE,
894 .max_adj = 0x7fffffff,
897 .n_per_out = OCELOT_PTP_PINS_NUM,
898 .n_pins = OCELOT_PTP_PINS_NUM,
900 .gettime64 = ocelot_ptp_gettime64,
901 .settime64 = ocelot_ptp_settime64,
902 .adjtime = ocelot_ptp_adjtime,
903 .adjfine = ocelot_ptp_adjfine,
904 .verify = ocelot_ptp_verify,
905 .enable = ocelot_ptp_enable,
908 #define VSC9959_INIT_TIMEOUT 50000
909 #define VSC9959_GCB_RST_SLEEP 100
910 #define VSC9959_SYS_RAMINIT_SLEEP 80
912 static int vsc9959_gcb_soft_rst_status(struct ocelot *ocelot)
916 ocelot_field_read(ocelot, GCB_SOFT_RST_SWC_RST, &val);
921 static int vsc9959_sys_ram_init_status(struct ocelot *ocelot)
923 return ocelot_read(ocelot, SYS_RAM_INIT);
926 /* CORE_ENA is in SYS:SYSTEM:RESET_CFG
927 * RAM_INIT is in SYS:RAM_CTRL:RAM_INIT
929 static int vsc9959_reset(struct ocelot *ocelot)
933 /* soft-reset the switch core */
934 ocelot_field_write(ocelot, GCB_SOFT_RST_SWC_RST, 1);
936 err = readx_poll_timeout(vsc9959_gcb_soft_rst_status, ocelot, val, !val,
937 VSC9959_GCB_RST_SLEEP, VSC9959_INIT_TIMEOUT);
939 dev_err(ocelot->dev, "timeout: switch core reset\n");
943 /* initialize switch mem ~40us */
944 ocelot_write(ocelot, SYS_RAM_INIT_RAM_INIT, SYS_RAM_INIT);
945 err = readx_poll_timeout(vsc9959_sys_ram_init_status, ocelot, val, !val,
946 VSC9959_SYS_RAMINIT_SLEEP,
947 VSC9959_INIT_TIMEOUT);
949 dev_err(ocelot->dev, "timeout: switch sram init\n");
953 /* enable switch core */
954 ocelot_field_write(ocelot, SYS_RESET_CFG_CORE_ENA, 1);
959 static void vsc9959_phylink_validate(struct ocelot *ocelot, int port,
960 unsigned long *supported,
961 struct phylink_link_state *state)
963 __ETHTOOL_DECLARE_LINK_MODE_MASK(mask) = { 0, };
965 phylink_set_port_modes(mask);
966 phylink_set(mask, Autoneg);
967 phylink_set(mask, Pause);
968 phylink_set(mask, Asym_Pause);
969 phylink_set(mask, 10baseT_Half);
970 phylink_set(mask, 10baseT_Full);
971 phylink_set(mask, 100baseT_Half);
972 phylink_set(mask, 100baseT_Full);
973 phylink_set(mask, 1000baseT_Half);
974 phylink_set(mask, 1000baseT_Full);
976 if (state->interface == PHY_INTERFACE_MODE_INTERNAL ||
977 state->interface == PHY_INTERFACE_MODE_2500BASEX ||
978 state->interface == PHY_INTERFACE_MODE_USXGMII) {
979 phylink_set(mask, 2500baseT_Full);
980 phylink_set(mask, 2500baseX_Full);
983 linkmode_and(supported, supported, mask);
984 linkmode_and(state->advertising, state->advertising, mask);
988 * Bit 8: Unit; 0:1, 1:16
989 * Bit 7-0: Value to be multiplied with unit
991 static u16 vsc9959_wm_enc(u16 value)
993 WARN_ON(value >= 16 * BIT(8));
996 return BIT(8) | (value / 16);
1001 static u16 vsc9959_wm_dec(u16 wm)
1003 WARN_ON(wm & ~GENMASK(8, 0));
1006 return (wm & GENMASK(7, 0)) * 16;
1011 static void vsc9959_wm_stat(u32 val, u32 *inuse, u32 *maxuse)
1013 *inuse = (val & GENMASK(23, 12)) >> 12;
1014 *maxuse = val & GENMASK(11, 0);
1017 static int vsc9959_mdio_bus_alloc(struct ocelot *ocelot)
1019 struct felix *felix = ocelot_to_felix(ocelot);
1020 struct enetc_mdio_priv *mdio_priv;
1021 struct device *dev = ocelot->dev;
1022 void __iomem *imdio_regs;
1023 struct resource res;
1024 struct enetc_hw *hw;
1025 struct mii_bus *bus;
1029 felix->pcs = devm_kcalloc(dev, felix->info->num_ports,
1030 sizeof(struct phylink_pcs *),
1033 dev_err(dev, "failed to allocate array for PCS PHYs\n");
1037 memcpy(&res, felix->info->imdio_res, sizeof(res));
1038 res.flags = IORESOURCE_MEM;
1039 res.start += felix->imdio_base;
1040 res.end += felix->imdio_base;
1042 imdio_regs = devm_ioremap_resource(dev, &res);
1043 if (IS_ERR(imdio_regs))
1044 return PTR_ERR(imdio_regs);
1046 hw = enetc_hw_alloc(dev, imdio_regs);
1048 dev_err(dev, "failed to allocate ENETC HW structure\n");
1052 bus = mdiobus_alloc_size(sizeof(*mdio_priv));
1056 bus->name = "VSC9959 internal MDIO bus";
1057 bus->read = enetc_mdio_read;
1058 bus->write = enetc_mdio_write;
1060 mdio_priv = bus->priv;
1062 /* This gets added to imdio_regs, which already maps addresses
1063 * starting with the proper offset.
1065 mdio_priv->mdio_base = 0;
1066 snprintf(bus->id, MII_BUS_ID_SIZE, "%s-imdio", dev_name(dev));
1068 /* Needed in order to initialize the bus mutex lock */
1069 rc = mdiobus_register(bus);
1071 dev_err(dev, "failed to register MDIO bus\n");
1078 for (port = 0; port < felix->info->num_ports; port++) {
1079 struct ocelot_port *ocelot_port = ocelot->ports[port];
1080 struct phylink_pcs *phylink_pcs;
1081 struct mdio_device *mdio_device;
1083 if (dsa_is_unused_port(felix->ds, port))
1086 if (ocelot_port->phy_mode == PHY_INTERFACE_MODE_INTERNAL)
1089 mdio_device = mdio_device_create(felix->imdio, port);
1090 if (IS_ERR(mdio_device))
1093 phylink_pcs = lynx_pcs_create(mdio_device);
1095 mdio_device_free(mdio_device);
1099 felix->pcs[port] = phylink_pcs;
1101 dev_info(dev, "Found PCS at internal MDIO address %d\n", port);
1107 static void vsc9959_mdio_bus_free(struct ocelot *ocelot)
1109 struct felix *felix = ocelot_to_felix(ocelot);
1112 for (port = 0; port < ocelot->num_phys_ports; port++) {
1113 struct phylink_pcs *phylink_pcs = felix->pcs[port];
1114 struct mdio_device *mdio_device;
1119 mdio_device = lynx_get_mdio_device(phylink_pcs);
1120 mdio_device_free(mdio_device);
1121 lynx_pcs_destroy(phylink_pcs);
1123 mdiobus_unregister(felix->imdio);
1124 mdiobus_free(felix->imdio);
1127 static void vsc9959_sched_speed_set(struct ocelot *ocelot, int port,
1134 tas_speed = OCELOT_SPEED_10;
1137 tas_speed = OCELOT_SPEED_100;
1140 tas_speed = OCELOT_SPEED_1000;
1143 tas_speed = OCELOT_SPEED_2500;
1146 tas_speed = OCELOT_SPEED_1000;
1150 ocelot_rmw_rix(ocelot,
1151 QSYS_TAG_CONFIG_LINK_SPEED(tas_speed),
1152 QSYS_TAG_CONFIG_LINK_SPEED_M,
1153 QSYS_TAG_CONFIG, port);
1156 static void vsc9959_new_base_time(struct ocelot *ocelot, ktime_t base_time,
1158 struct timespec64 *new_base_ts)
1160 struct timespec64 ts;
1161 ktime_t new_base_time;
1162 ktime_t current_time;
1164 ocelot_ptp_gettime64(&ocelot->ptp_info, &ts);
1165 current_time = timespec64_to_ktime(ts);
1166 new_base_time = base_time;
1168 if (base_time < current_time) {
1169 u64 nr_of_cycles = current_time - base_time;
1171 do_div(nr_of_cycles, cycle_time);
1172 new_base_time += cycle_time * (nr_of_cycles + 1);
1175 *new_base_ts = ktime_to_timespec64(new_base_time);
1178 static u32 vsc9959_tas_read_cfg_status(struct ocelot *ocelot)
1180 return ocelot_read(ocelot, QSYS_TAS_PARAM_CFG_CTRL);
1183 static void vsc9959_tas_gcl_set(struct ocelot *ocelot, const u32 gcl_ix,
1184 struct tc_taprio_sched_entry *entry)
1186 ocelot_write(ocelot,
1187 QSYS_GCL_CFG_REG_1_GCL_ENTRY_NUM(gcl_ix) |
1188 QSYS_GCL_CFG_REG_1_GATE_STATE(entry->gate_mask),
1189 QSYS_GCL_CFG_REG_1);
1190 ocelot_write(ocelot, entry->interval, QSYS_GCL_CFG_REG_2);
1193 static int vsc9959_qos_port_tas_set(struct ocelot *ocelot, int port,
1194 struct tc_taprio_qopt_offload *taprio)
1196 struct timespec64 base_ts;
1200 if (!taprio->enable) {
1201 ocelot_rmw_rix(ocelot,
1202 QSYS_TAG_CONFIG_INIT_GATE_STATE(0xFF),
1203 QSYS_TAG_CONFIG_ENABLE |
1204 QSYS_TAG_CONFIG_INIT_GATE_STATE_M,
1205 QSYS_TAG_CONFIG, port);
1210 if (taprio->cycle_time > NSEC_PER_SEC ||
1211 taprio->cycle_time_extension >= NSEC_PER_SEC)
1214 if (taprio->num_entries > VSC9959_TAS_GCL_ENTRY_MAX)
1217 /* Enable guard band. The switch will schedule frames without taking
1218 * their length into account. Thus we'll always need to enable the
1219 * guard band which reserves the time of a maximum sized frame at the
1220 * end of the time window.
1222 * Although the ALWAYS_GUARD_BAND_SCH_Q bit is global for all ports, we
1223 * need to set PORT_NUM, because subsequent writes to PARAM_CFG_REG_n
1224 * operate on the port number.
1226 ocelot_rmw(ocelot, QSYS_TAS_PARAM_CFG_CTRL_PORT_NUM(port) |
1227 QSYS_TAS_PARAM_CFG_CTRL_ALWAYS_GUARD_BAND_SCH_Q,
1228 QSYS_TAS_PARAM_CFG_CTRL_PORT_NUM_M |
1229 QSYS_TAS_PARAM_CFG_CTRL_ALWAYS_GUARD_BAND_SCH_Q,
1230 QSYS_TAS_PARAM_CFG_CTRL);
1232 /* Hardware errata - Admin config could not be overwritten if
1233 * config is pending, need reset the TAS module
1235 val = ocelot_read(ocelot, QSYS_PARAM_STATUS_REG_8);
1236 if (val & QSYS_PARAM_STATUS_REG_8_CONFIG_PENDING)
1239 ocelot_rmw_rix(ocelot,
1240 QSYS_TAG_CONFIG_ENABLE |
1241 QSYS_TAG_CONFIG_INIT_GATE_STATE(0xFF) |
1242 QSYS_TAG_CONFIG_SCH_TRAFFIC_QUEUES(0xFF),
1243 QSYS_TAG_CONFIG_ENABLE |
1244 QSYS_TAG_CONFIG_INIT_GATE_STATE_M |
1245 QSYS_TAG_CONFIG_SCH_TRAFFIC_QUEUES_M,
1246 QSYS_TAG_CONFIG, port);
1248 vsc9959_new_base_time(ocelot, taprio->base_time,
1249 taprio->cycle_time, &base_ts);
1250 ocelot_write(ocelot, base_ts.tv_nsec, QSYS_PARAM_CFG_REG_1);
1251 ocelot_write(ocelot, lower_32_bits(base_ts.tv_sec), QSYS_PARAM_CFG_REG_2);
1252 val = upper_32_bits(base_ts.tv_sec);
1253 ocelot_write(ocelot,
1254 QSYS_PARAM_CFG_REG_3_BASE_TIME_SEC_MSB(val) |
1255 QSYS_PARAM_CFG_REG_3_LIST_LENGTH(taprio->num_entries),
1256 QSYS_PARAM_CFG_REG_3);
1257 ocelot_write(ocelot, taprio->cycle_time, QSYS_PARAM_CFG_REG_4);
1258 ocelot_write(ocelot, taprio->cycle_time_extension, QSYS_PARAM_CFG_REG_5);
1260 for (i = 0; i < taprio->num_entries; i++)
1261 vsc9959_tas_gcl_set(ocelot, i, &taprio->entries[i]);
1263 ocelot_rmw(ocelot, QSYS_TAS_PARAM_CFG_CTRL_CONFIG_CHANGE,
1264 QSYS_TAS_PARAM_CFG_CTRL_CONFIG_CHANGE,
1265 QSYS_TAS_PARAM_CFG_CTRL);
1267 ret = readx_poll_timeout(vsc9959_tas_read_cfg_status, ocelot, val,
1268 !(val & QSYS_TAS_PARAM_CFG_CTRL_CONFIG_CHANGE),
1274 static int vsc9959_qos_port_cbs_set(struct dsa_switch *ds, int port,
1275 struct tc_cbs_qopt_offload *cbs_qopt)
1277 struct ocelot *ocelot = ds->priv;
1278 int port_ix = port * 8 + cbs_qopt->queue;
1281 if (cbs_qopt->queue >= ds->num_tx_queues)
1284 if (!cbs_qopt->enable) {
1285 ocelot_write_gix(ocelot, QSYS_CIR_CFG_CIR_RATE(0) |
1286 QSYS_CIR_CFG_CIR_BURST(0),
1287 QSYS_CIR_CFG, port_ix);
1289 ocelot_rmw_gix(ocelot, 0, QSYS_SE_CFG_SE_AVB_ENA,
1290 QSYS_SE_CFG, port_ix);
1295 /* Rate unit is 100 kbps */
1296 rate = DIV_ROUND_UP(cbs_qopt->idleslope, 100);
1297 /* Avoid using zero rate */
1298 rate = clamp_t(u32, rate, 1, GENMASK(14, 0));
1299 /* Burst unit is 4kB */
1300 burst = DIV_ROUND_UP(cbs_qopt->hicredit, 4096);
1301 /* Avoid using zero burst size */
1302 burst = clamp_t(u32, burst, 1, GENMASK(5, 0));
1303 ocelot_write_gix(ocelot,
1304 QSYS_CIR_CFG_CIR_RATE(rate) |
1305 QSYS_CIR_CFG_CIR_BURST(burst),
1309 ocelot_rmw_gix(ocelot,
1310 QSYS_SE_CFG_SE_FRM_MODE(0) |
1311 QSYS_SE_CFG_SE_AVB_ENA,
1312 QSYS_SE_CFG_SE_AVB_ENA |
1313 QSYS_SE_CFG_SE_FRM_MODE_M,
1320 static int vsc9959_port_setup_tc(struct dsa_switch *ds, int port,
1321 enum tc_setup_type type,
1324 struct ocelot *ocelot = ds->priv;
1327 case TC_SETUP_QDISC_TAPRIO:
1328 return vsc9959_qos_port_tas_set(ocelot, port, type_data);
1329 case TC_SETUP_QDISC_CBS:
1330 return vsc9959_qos_port_cbs_set(ds, port, type_data);
1336 #define VSC9959_PSFP_SFID_MAX 175
1337 #define VSC9959_PSFP_GATE_ID_MAX 183
1338 #define VSC9959_PSFP_POLICER_BASE 63
1339 #define VSC9959_PSFP_POLICER_MAX 383
1340 #define VSC9959_PSFP_GATE_LIST_NUM 4
1341 #define VSC9959_PSFP_GATE_CYCLETIME_MIN 5000
1343 struct felix_stream {
1344 struct list_head list;
1358 struct felix_stream_filter {
1359 struct list_head list;
1360 refcount_t refcount;
1373 struct felix_stream_filter_counters {
1380 struct felix_stream_gate {
1389 struct action_gate_entry entries[];
1392 struct felix_stream_gate_entry {
1393 struct list_head list;
1394 refcount_t refcount;
1398 static int vsc9959_stream_identify(struct flow_cls_offload *f,
1399 struct felix_stream *stream)
1401 struct flow_rule *rule = flow_cls_offload_flow_rule(f);
1402 struct flow_dissector *dissector = rule->match.dissector;
1404 if (dissector->used_keys &
1405 ~(BIT(FLOW_DISSECTOR_KEY_CONTROL) |
1406 BIT(FLOW_DISSECTOR_KEY_BASIC) |
1407 BIT(FLOW_DISSECTOR_KEY_VLAN) |
1408 BIT(FLOW_DISSECTOR_KEY_ETH_ADDRS)))
1411 if (flow_rule_match_key(rule, FLOW_DISSECTOR_KEY_ETH_ADDRS)) {
1412 struct flow_match_eth_addrs match;
1414 flow_rule_match_eth_addrs(rule, &match);
1415 ether_addr_copy(stream->dmac, match.key->dst);
1416 if (!is_zero_ether_addr(match.mask->src))
1422 if (flow_rule_match_key(rule, FLOW_DISSECTOR_KEY_VLAN)) {
1423 struct flow_match_vlan match;
1425 flow_rule_match_vlan(rule, &match);
1426 if (match.mask->vlan_priority)
1427 stream->prio = match.key->vlan_priority;
1431 if (!match.mask->vlan_id)
1433 stream->vid = match.key->vlan_id;
1438 stream->id = f->cookie;
1443 static int vsc9959_mact_stream_set(struct ocelot *ocelot,
1444 struct felix_stream *stream,
1445 struct netlink_ext_ack *extack)
1447 enum macaccess_entry_type type;
1448 int ret, sfid, ssid;
1452 ether_addr_copy(mac, stream->dmac);
1455 /* Stream identification desn't support to add a stream with non
1456 * existent MAC (The MAC entry has not been learned in MAC table).
1458 ret = ocelot_mact_lookup(ocelot, &dst_idx, mac, vid, &type);
1461 NL_SET_ERR_MSG_MOD(extack, "Stream is not learned in MAC table");
1465 if ((stream->sfid_valid || stream->ssid_valid) &&
1466 type == ENTRYTYPE_NORMAL)
1467 type = ENTRYTYPE_LOCKED;
1469 sfid = stream->sfid_valid ? stream->sfid : -1;
1470 ssid = stream->ssid_valid ? stream->ssid : -1;
1472 ret = ocelot_mact_learn_streamdata(ocelot, dst_idx, mac, vid, type,
1478 static struct felix_stream *
1479 vsc9959_stream_table_lookup(struct list_head *stream_list,
1480 struct felix_stream *stream)
1482 struct felix_stream *tmp;
1484 list_for_each_entry(tmp, stream_list, list)
1485 if (ether_addr_equal(tmp->dmac, stream->dmac) &&
1486 tmp->vid == stream->vid)
1492 static int vsc9959_stream_table_add(struct ocelot *ocelot,
1493 struct list_head *stream_list,
1494 struct felix_stream *stream,
1495 struct netlink_ext_ack *extack)
1497 struct felix_stream *stream_entry;
1500 stream_entry = kmemdup(stream, sizeof(*stream_entry), GFP_KERNEL);
1504 if (!stream->dummy) {
1505 ret = vsc9959_mact_stream_set(ocelot, stream_entry, extack);
1507 kfree(stream_entry);
1512 list_add_tail(&stream_entry->list, stream_list);
1517 static struct felix_stream *
1518 vsc9959_stream_table_get(struct list_head *stream_list, unsigned long id)
1520 struct felix_stream *tmp;
1522 list_for_each_entry(tmp, stream_list, list)
1529 static void vsc9959_stream_table_del(struct ocelot *ocelot,
1530 struct felix_stream *stream)
1533 vsc9959_mact_stream_set(ocelot, stream, NULL);
1535 list_del(&stream->list);
1539 static u32 vsc9959_sfi_access_status(struct ocelot *ocelot)
1541 return ocelot_read(ocelot, ANA_TABLES_SFIDACCESS);
1544 static int vsc9959_psfp_sfi_set(struct ocelot *ocelot,
1545 struct felix_stream_filter *sfi)
1549 if (sfi->index > VSC9959_PSFP_SFID_MAX)
1553 ocelot_write(ocelot, ANA_TABLES_SFIDTIDX_SFID_INDEX(sfi->index),
1554 ANA_TABLES_SFIDTIDX);
1556 val = ANA_TABLES_SFIDACCESS_SFID_TBL_CMD(SFIDACCESS_CMD_WRITE);
1557 ocelot_write(ocelot, val, ANA_TABLES_SFIDACCESS);
1559 return readx_poll_timeout(vsc9959_sfi_access_status, ocelot, val,
1560 (!ANA_TABLES_SFIDACCESS_SFID_TBL_CMD(val)),
1564 if (sfi->sgid > VSC9959_PSFP_GATE_ID_MAX ||
1565 sfi->fmid > VSC9959_PSFP_POLICER_MAX)
1568 ocelot_write(ocelot,
1569 (sfi->sg_valid ? ANA_TABLES_SFIDTIDX_SGID_VALID : 0) |
1570 ANA_TABLES_SFIDTIDX_SGID(sfi->sgid) |
1571 (sfi->fm_valid ? ANA_TABLES_SFIDTIDX_POL_ENA : 0) |
1572 ANA_TABLES_SFIDTIDX_POL_IDX(sfi->fmid) |
1573 ANA_TABLES_SFIDTIDX_SFID_INDEX(sfi->index),
1574 ANA_TABLES_SFIDTIDX);
1576 ocelot_write(ocelot,
1577 (sfi->prio_valid ? ANA_TABLES_SFIDACCESS_IGR_PRIO_MATCH_ENA : 0) |
1578 ANA_TABLES_SFIDACCESS_IGR_PRIO(sfi->prio) |
1579 ANA_TABLES_SFIDACCESS_MAX_SDU_LEN(sfi->maxsdu) |
1580 ANA_TABLES_SFIDACCESS_SFID_TBL_CMD(SFIDACCESS_CMD_WRITE),
1581 ANA_TABLES_SFIDACCESS);
1583 return readx_poll_timeout(vsc9959_sfi_access_status, ocelot, val,
1584 (!ANA_TABLES_SFIDACCESS_SFID_TBL_CMD(val)),
1588 static int vsc9959_psfp_sfidmask_set(struct ocelot *ocelot, u32 sfid, int ports)
1593 ANA_TABLES_SFIDTIDX_SFID_INDEX(sfid),
1594 ANA_TABLES_SFIDTIDX_SFID_INDEX_M,
1595 ANA_TABLES_SFIDTIDX);
1597 ocelot_write(ocelot,
1598 ANA_TABLES_SFID_MASK_IGR_PORT_MASK(ports) |
1599 ANA_TABLES_SFID_MASK_IGR_SRCPORT_MATCH_ENA,
1600 ANA_TABLES_SFID_MASK);
1603 ANA_TABLES_SFIDACCESS_SFID_TBL_CMD(SFIDACCESS_CMD_WRITE),
1604 ANA_TABLES_SFIDACCESS_SFID_TBL_CMD_M,
1605 ANA_TABLES_SFIDACCESS);
1607 return readx_poll_timeout(vsc9959_sfi_access_status, ocelot, val,
1608 (!ANA_TABLES_SFIDACCESS_SFID_TBL_CMD(val)),
1612 static int vsc9959_psfp_sfi_list_add(struct ocelot *ocelot,
1613 struct felix_stream_filter *sfi,
1614 struct list_head *pos)
1616 struct felix_stream_filter *sfi_entry;
1619 sfi_entry = kmemdup(sfi, sizeof(*sfi_entry), GFP_KERNEL);
1623 refcount_set(&sfi_entry->refcount, 1);
1625 ret = vsc9959_psfp_sfi_set(ocelot, sfi_entry);
1631 vsc9959_psfp_sfidmask_set(ocelot, sfi->index, sfi->portmask);
1633 list_add(&sfi_entry->list, pos);
1638 static int vsc9959_psfp_sfi_table_add(struct ocelot *ocelot,
1639 struct felix_stream_filter *sfi)
1641 struct list_head *pos, *q, *last;
1642 struct felix_stream_filter *tmp;
1643 struct ocelot_psfp_list *psfp;
1646 psfp = &ocelot->psfp;
1647 last = &psfp->sfi_list;
1649 list_for_each_safe(pos, q, &psfp->sfi_list) {
1650 tmp = list_entry(pos, struct felix_stream_filter, list);
1651 if (sfi->sg_valid == tmp->sg_valid &&
1652 sfi->fm_valid == tmp->fm_valid &&
1653 sfi->portmask == tmp->portmask &&
1654 tmp->sgid == sfi->sgid &&
1655 tmp->fmid == sfi->fmid) {
1656 sfi->index = tmp->index;
1657 refcount_inc(&tmp->refcount);
1660 /* Make sure that the index is increasing in order. */
1661 if (tmp->index == insert) {
1666 sfi->index = insert;
1668 return vsc9959_psfp_sfi_list_add(ocelot, sfi, last);
1671 static int vsc9959_psfp_sfi_table_add2(struct ocelot *ocelot,
1672 struct felix_stream_filter *sfi,
1673 struct felix_stream_filter *sfi2)
1675 struct felix_stream_filter *tmp;
1676 struct list_head *pos, *q, *last;
1677 struct ocelot_psfp_list *psfp;
1681 psfp = &ocelot->psfp;
1682 last = &psfp->sfi_list;
1684 list_for_each_safe(pos, q, &psfp->sfi_list) {
1685 tmp = list_entry(pos, struct felix_stream_filter, list);
1686 /* Make sure that the index is increasing in order. */
1687 if (tmp->index >= insert + 2)
1690 insert = tmp->index + 1;
1693 sfi->index = insert;
1695 ret = vsc9959_psfp_sfi_list_add(ocelot, sfi, last);
1699 sfi2->index = insert + 1;
1701 return vsc9959_psfp_sfi_list_add(ocelot, sfi2, last->next);
1704 static struct felix_stream_filter *
1705 vsc9959_psfp_sfi_table_get(struct list_head *sfi_list, u32 index)
1707 struct felix_stream_filter *tmp;
1709 list_for_each_entry(tmp, sfi_list, list)
1710 if (tmp->index == index)
1716 static void vsc9959_psfp_sfi_table_del(struct ocelot *ocelot, u32 index)
1718 struct felix_stream_filter *tmp, *n;
1719 struct ocelot_psfp_list *psfp;
1722 psfp = &ocelot->psfp;
1724 list_for_each_entry_safe(tmp, n, &psfp->sfi_list, list)
1725 if (tmp->index == index) {
1726 z = refcount_dec_and_test(&tmp->refcount);
1729 vsc9959_psfp_sfi_set(ocelot, tmp);
1730 list_del(&tmp->list);
1737 static void vsc9959_psfp_parse_gate(const struct flow_action_entry *entry,
1738 struct felix_stream_gate *sgi)
1740 sgi->index = entry->hw_index;
1741 sgi->ipv_valid = (entry->gate.prio < 0) ? 0 : 1;
1742 sgi->init_ipv = (sgi->ipv_valid) ? entry->gate.prio : 0;
1743 sgi->basetime = entry->gate.basetime;
1744 sgi->cycletime = entry->gate.cycletime;
1745 sgi->num_entries = entry->gate.num_entries;
1748 memcpy(sgi->entries, entry->gate.entries,
1749 entry->gate.num_entries * sizeof(struct action_gate_entry));
1752 static u32 vsc9959_sgi_cfg_status(struct ocelot *ocelot)
1754 return ocelot_read(ocelot, ANA_SG_ACCESS_CTRL);
1757 static int vsc9959_psfp_sgi_set(struct ocelot *ocelot,
1758 struct felix_stream_gate *sgi)
1760 struct action_gate_entry *e;
1761 struct timespec64 base_ts;
1762 u32 interval_sum = 0;
1766 if (sgi->index > VSC9959_PSFP_GATE_ID_MAX)
1769 ocelot_write(ocelot, ANA_SG_ACCESS_CTRL_SGID(sgi->index),
1770 ANA_SG_ACCESS_CTRL);
1773 ocelot_rmw(ocelot, ANA_SG_CONFIG_REG_3_INIT_GATE_STATE,
1774 ANA_SG_CONFIG_REG_3_INIT_GATE_STATE |
1775 ANA_SG_CONFIG_REG_3_GATE_ENABLE,
1776 ANA_SG_CONFIG_REG_3);
1781 if (sgi->cycletime < VSC9959_PSFP_GATE_CYCLETIME_MIN ||
1782 sgi->cycletime > NSEC_PER_SEC)
1785 if (sgi->num_entries > VSC9959_PSFP_GATE_LIST_NUM)
1788 vsc9959_new_base_time(ocelot, sgi->basetime, sgi->cycletime, &base_ts);
1789 ocelot_write(ocelot, base_ts.tv_nsec, ANA_SG_CONFIG_REG_1);
1790 val = lower_32_bits(base_ts.tv_sec);
1791 ocelot_write(ocelot, val, ANA_SG_CONFIG_REG_2);
1793 val = upper_32_bits(base_ts.tv_sec);
1794 ocelot_write(ocelot,
1795 (sgi->ipv_valid ? ANA_SG_CONFIG_REG_3_IPV_VALID : 0) |
1796 ANA_SG_CONFIG_REG_3_INIT_IPV(sgi->init_ipv) |
1797 ANA_SG_CONFIG_REG_3_GATE_ENABLE |
1798 ANA_SG_CONFIG_REG_3_LIST_LENGTH(sgi->num_entries) |
1799 ANA_SG_CONFIG_REG_3_INIT_GATE_STATE |
1800 ANA_SG_CONFIG_REG_3_BASE_TIME_SEC_MSB(val),
1801 ANA_SG_CONFIG_REG_3);
1803 ocelot_write(ocelot, sgi->cycletime, ANA_SG_CONFIG_REG_4);
1806 for (i = 0; i < sgi->num_entries; i++) {
1807 u32 ips = (e[i].ipv < 0) ? 0 : (e[i].ipv + 8);
1809 ocelot_write_rix(ocelot, ANA_SG_GCL_GS_CONFIG_IPS(ips) |
1811 ANA_SG_GCL_GS_CONFIG_GATE_STATE : 0),
1812 ANA_SG_GCL_GS_CONFIG, i);
1814 interval_sum += e[i].interval;
1815 ocelot_write_rix(ocelot, interval_sum, ANA_SG_GCL_TI_CONFIG, i);
1818 ocelot_rmw(ocelot, ANA_SG_ACCESS_CTRL_CONFIG_CHANGE,
1819 ANA_SG_ACCESS_CTRL_CONFIG_CHANGE,
1820 ANA_SG_ACCESS_CTRL);
1822 return readx_poll_timeout(vsc9959_sgi_cfg_status, ocelot, val,
1823 (!(ANA_SG_ACCESS_CTRL_CONFIG_CHANGE & val)),
1827 static int vsc9959_psfp_sgi_table_add(struct ocelot *ocelot,
1828 struct felix_stream_gate *sgi)
1830 struct felix_stream_gate_entry *tmp;
1831 struct ocelot_psfp_list *psfp;
1834 psfp = &ocelot->psfp;
1836 list_for_each_entry(tmp, &psfp->sgi_list, list)
1837 if (tmp->index == sgi->index) {
1838 refcount_inc(&tmp->refcount);
1842 tmp = kzalloc(sizeof(*tmp), GFP_KERNEL);
1846 ret = vsc9959_psfp_sgi_set(ocelot, sgi);
1852 tmp->index = sgi->index;
1853 refcount_set(&tmp->refcount, 1);
1854 list_add_tail(&tmp->list, &psfp->sgi_list);
1859 static void vsc9959_psfp_sgi_table_del(struct ocelot *ocelot,
1862 struct felix_stream_gate_entry *tmp, *n;
1863 struct felix_stream_gate sgi = {0};
1864 struct ocelot_psfp_list *psfp;
1867 psfp = &ocelot->psfp;
1869 list_for_each_entry_safe(tmp, n, &psfp->sgi_list, list)
1870 if (tmp->index == index) {
1871 z = refcount_dec_and_test(&tmp->refcount);
1875 vsc9959_psfp_sgi_set(ocelot, &sgi);
1876 list_del(&tmp->list);
1883 static void vsc9959_psfp_counters_get(struct ocelot *ocelot, u32 index,
1884 struct felix_stream_filter_counters *counters)
1886 ocelot_rmw(ocelot, SYS_STAT_CFG_STAT_VIEW(index),
1887 SYS_STAT_CFG_STAT_VIEW_M,
1890 counters->match = ocelot_read_gix(ocelot, SYS_CNT, 0x200);
1891 counters->not_pass_gate = ocelot_read_gix(ocelot, SYS_CNT, 0x201);
1892 counters->not_pass_sdu = ocelot_read_gix(ocelot, SYS_CNT, 0x202);
1893 counters->red = ocelot_read_gix(ocelot, SYS_CNT, 0x203);
1895 /* Clear the PSFP counter. */
1896 ocelot_write(ocelot,
1897 SYS_STAT_CFG_STAT_VIEW(index) |
1898 SYS_STAT_CFG_STAT_CLEAR_SHOT(0x10),
1902 static int vsc9959_psfp_filter_add(struct ocelot *ocelot, int port,
1903 struct flow_cls_offload *f)
1905 struct netlink_ext_ack *extack = f->common.extack;
1906 struct felix_stream_filter old_sfi, *sfi_entry;
1907 struct felix_stream_filter sfi = {0};
1908 const struct flow_action_entry *a;
1909 struct felix_stream *stream_entry;
1910 struct felix_stream stream = {0};
1911 struct felix_stream_gate *sgi;
1912 struct ocelot_psfp_list *psfp;
1913 struct ocelot_policer pol;
1918 psfp = &ocelot->psfp;
1920 ret = vsc9959_stream_identify(f, &stream);
1922 NL_SET_ERR_MSG_MOD(extack, "Only can match on VID, PCP, and dest MAC");
1926 flow_action_for_each(i, a, &f->rule->action) {
1928 case FLOW_ACTION_GATE:
1929 size = struct_size(sgi, entries, a->gate.num_entries);
1930 sgi = kzalloc(size, GFP_KERNEL);
1935 vsc9959_psfp_parse_gate(a, sgi);
1936 ret = vsc9959_psfp_sgi_table_add(ocelot, sgi);
1942 sfi.sgid = sgi->index;
1945 case FLOW_ACTION_POLICE:
1946 index = a->hw_index + VSC9959_PSFP_POLICER_BASE;
1947 if (index > VSC9959_PSFP_POLICER_MAX) {
1952 rate = a->police.rate_bytes_ps;
1953 burst = rate * PSCHED_NS2TICKS(a->police.burst);
1954 pol = (struct ocelot_policer) {
1955 .burst = div_u64(burst, PSCHED_TICKS_PER_SEC),
1956 .rate = div_u64(rate, 1000) * 8,
1958 ret = ocelot_vcap_policer_add(ocelot, index, &pol);
1964 sfi.maxsdu = a->police.mtu;
1971 stream.ports = BIT(port);
1974 sfi.portmask = stream.ports;
1975 sfi.prio_valid = (stream.prio < 0 ? 0 : 1);
1976 sfi.prio = (sfi.prio_valid ? stream.prio : 0);
1979 /* Check if stream is set. */
1980 stream_entry = vsc9959_stream_table_lookup(&psfp->stream_list, &stream);
1982 if (stream_entry->ports & BIT(port)) {
1983 NL_SET_ERR_MSG_MOD(extack,
1984 "The stream is added on this port");
1989 if (stream_entry->ports != BIT(stream_entry->port)) {
1990 NL_SET_ERR_MSG_MOD(extack,
1991 "The stream is added on two ports");
1996 stream_entry->ports |= BIT(port);
1997 stream.ports = stream_entry->ports;
1999 sfi_entry = vsc9959_psfp_sfi_table_get(&psfp->sfi_list,
2000 stream_entry->sfid);
2001 memcpy(&old_sfi, sfi_entry, sizeof(old_sfi));
2003 vsc9959_psfp_sfi_table_del(ocelot, stream_entry->sfid);
2005 old_sfi.portmask = stream_entry->ports;
2006 sfi.portmask = stream.ports;
2008 if (stream_entry->port > port) {
2009 ret = vsc9959_psfp_sfi_table_add2(ocelot, &sfi,
2011 stream_entry->dummy = true;
2013 ret = vsc9959_psfp_sfi_table_add2(ocelot, &old_sfi,
2015 stream.dummy = true;
2020 stream_entry->sfid = old_sfi.index;
2022 ret = vsc9959_psfp_sfi_table_add(ocelot, &sfi);
2027 stream.sfid = sfi.index;
2028 stream.sfid_valid = 1;
2029 ret = vsc9959_stream_table_add(ocelot, &psfp->stream_list,
2032 vsc9959_psfp_sfi_table_del(ocelot, stream.sfid);
2040 vsc9959_psfp_sgi_table_del(ocelot, sfi.sgid);
2043 ocelot_vcap_policer_del(ocelot, sfi.fmid);
2048 static int vsc9959_psfp_filter_del(struct ocelot *ocelot,
2049 struct flow_cls_offload *f)
2051 struct felix_stream *stream, tmp, *stream_entry;
2052 static struct felix_stream_filter *sfi;
2053 struct ocelot_psfp_list *psfp;
2055 psfp = &ocelot->psfp;
2057 stream = vsc9959_stream_table_get(&psfp->stream_list, f->cookie);
2061 sfi = vsc9959_psfp_sfi_table_get(&psfp->sfi_list, stream->sfid);
2066 vsc9959_psfp_sgi_table_del(ocelot, sfi->sgid);
2069 ocelot_vcap_policer_del(ocelot, sfi->fmid);
2071 vsc9959_psfp_sfi_table_del(ocelot, stream->sfid);
2073 memcpy(&tmp, stream, sizeof(tmp));
2075 stream->sfid_valid = 0;
2076 vsc9959_stream_table_del(ocelot, stream);
2078 stream_entry = vsc9959_stream_table_lookup(&psfp->stream_list, &tmp);
2080 stream_entry->ports = BIT(stream_entry->port);
2081 if (stream_entry->dummy) {
2082 stream_entry->dummy = false;
2083 vsc9959_mact_stream_set(ocelot, stream_entry, NULL);
2085 vsc9959_psfp_sfidmask_set(ocelot, stream_entry->sfid,
2086 stream_entry->ports);
2092 static int vsc9959_psfp_stats_get(struct ocelot *ocelot,
2093 struct flow_cls_offload *f,
2094 struct flow_stats *stats)
2096 struct felix_stream_filter_counters counters;
2097 struct ocelot_psfp_list *psfp;
2098 struct felix_stream *stream;
2100 psfp = &ocelot->psfp;
2101 stream = vsc9959_stream_table_get(&psfp->stream_list, f->cookie);
2105 vsc9959_psfp_counters_get(ocelot, stream->sfid, &counters);
2107 stats->pkts = counters.match;
2108 stats->drops = counters.not_pass_gate + counters.not_pass_sdu +
2114 static void vsc9959_psfp_init(struct ocelot *ocelot)
2116 struct ocelot_psfp_list *psfp = &ocelot->psfp;
2118 INIT_LIST_HEAD(&psfp->stream_list);
2119 INIT_LIST_HEAD(&psfp->sfi_list);
2120 INIT_LIST_HEAD(&psfp->sgi_list);
2123 /* When using cut-through forwarding and the egress port runs at a higher data
2124 * rate than the ingress port, the packet currently under transmission would
2125 * suffer an underrun since it would be transmitted faster than it is received.
2126 * The Felix switch implementation of cut-through forwarding does not check in
2127 * hardware whether this condition is satisfied or not, so we must restrict the
2128 * list of ports that have cut-through forwarding enabled on egress to only be
2129 * the ports operating at the lowest link speed within their respective
2130 * forwarding domain.
2132 static void vsc9959_cut_through_fwd(struct ocelot *ocelot)
2134 struct felix *felix = ocelot_to_felix(ocelot);
2135 struct dsa_switch *ds = felix->ds;
2136 int port, other_port;
2138 lockdep_assert_held(&ocelot->fwd_domain_lock);
2140 for (port = 0; port < ocelot->num_phys_ports; port++) {
2141 struct ocelot_port *ocelot_port = ocelot->ports[port];
2142 int min_speed = ocelot_port->speed;
2143 unsigned long mask = 0;
2146 /* Disable cut-through on ports that are down */
2147 if (ocelot_port->speed <= 0)
2150 if (dsa_is_cpu_port(ds, port)) {
2151 /* Ocelot switches forward from the NPI port towards
2152 * any port, regardless of it being in the NPI port's
2153 * forwarding domain or not.
2155 mask = dsa_user_ports(ds);
2157 mask = ocelot_get_bridge_fwd_mask(ocelot, port);
2159 if (ocelot->npi >= 0)
2160 mask |= BIT(ocelot->npi);
2162 mask |= ocelot_get_dsa_8021q_cpu_mask(ocelot);
2165 /* Calculate the minimum link speed, among the ports that are
2166 * up, of this source port's forwarding domain.
2168 for_each_set_bit(other_port, &mask, ocelot->num_phys_ports) {
2169 struct ocelot_port *other_ocelot_port;
2171 other_ocelot_port = ocelot->ports[other_port];
2172 if (other_ocelot_port->speed <= 0)
2175 if (min_speed > other_ocelot_port->speed)
2176 min_speed = other_ocelot_port->speed;
2179 /* Enable cut-through forwarding for all traffic classes. */
2180 if (ocelot_port->speed == min_speed)
2181 val = GENMASK(7, 0);
2184 tmp = ocelot_read_rix(ocelot, ANA_CUT_THRU_CFG, port);
2188 dev_dbg(ocelot->dev,
2189 "port %d fwd mask 0x%lx speed %d min_speed %d, %s cut-through forwarding\n",
2190 port, mask, ocelot_port->speed, min_speed,
2191 val ? "enabling" : "disabling");
2193 ocelot_write_rix(ocelot, val, ANA_CUT_THRU_CFG, port);
2197 static const struct ocelot_ops vsc9959_ops = {
2198 .reset = vsc9959_reset,
2199 .wm_enc = vsc9959_wm_enc,
2200 .wm_dec = vsc9959_wm_dec,
2201 .wm_stat = vsc9959_wm_stat,
2202 .port_to_netdev = felix_port_to_netdev,
2203 .netdev_to_port = felix_netdev_to_port,
2204 .psfp_init = vsc9959_psfp_init,
2205 .psfp_filter_add = vsc9959_psfp_filter_add,
2206 .psfp_filter_del = vsc9959_psfp_filter_del,
2207 .psfp_stats_get = vsc9959_psfp_stats_get,
2208 .cut_through_fwd = vsc9959_cut_through_fwd,
2211 static const struct felix_info felix_info_vsc9959 = {
2212 .target_io_res = vsc9959_target_io_res,
2213 .port_io_res = vsc9959_port_io_res,
2214 .imdio_res = &vsc9959_imdio_res,
2215 .regfields = vsc9959_regfields,
2216 .map = vsc9959_regmap,
2217 .ops = &vsc9959_ops,
2218 .stats_layout = vsc9959_stats_layout,
2219 .num_stats = ARRAY_SIZE(vsc9959_stats_layout),
2220 .vcap = vsc9959_vcap_props,
2221 .vcap_pol_base = VSC9959_VCAP_POLICER_BASE,
2222 .vcap_pol_max = VSC9959_VCAP_POLICER_MAX,
2223 .vcap_pol_base2 = 0,
2225 .num_mact_rows = 2048,
2226 .num_ports = VSC9959_NUM_PORTS,
2227 .num_tx_queues = OCELOT_NUM_TC,
2228 .quirk_no_xtr_irq = true,
2229 .ptp_caps = &vsc9959_ptp_caps,
2230 .mdio_bus_alloc = vsc9959_mdio_bus_alloc,
2231 .mdio_bus_free = vsc9959_mdio_bus_free,
2232 .phylink_validate = vsc9959_phylink_validate,
2233 .port_modes = vsc9959_port_modes,
2234 .port_setup_tc = vsc9959_port_setup_tc,
2235 .port_sched_speed_set = vsc9959_sched_speed_set,
2236 .init_regmap = ocelot_regmap_init,
2239 static irqreturn_t felix_irq_handler(int irq, void *data)
2241 struct ocelot *ocelot = (struct ocelot *)data;
2243 /* The INTB interrupt is used for both PTP TX timestamp interrupt
2244 * and preemption status change interrupt on each port.
2246 * - Get txtstamp if have
2247 * - TODO: handle preemption. Without handling it, driver may get
2251 ocelot_get_txtstamp(ocelot);
2256 static int felix_pci_probe(struct pci_dev *pdev,
2257 const struct pci_device_id *id)
2259 struct dsa_switch *ds;
2260 struct ocelot *ocelot;
2261 struct felix *felix;
2264 if (pdev->dev.of_node && !of_device_is_available(pdev->dev.of_node)) {
2265 dev_info(&pdev->dev, "device is disabled, skipping\n");
2269 err = pci_enable_device(pdev);
2271 dev_err(&pdev->dev, "device enable failed\n");
2272 goto err_pci_enable;
2275 felix = kzalloc(sizeof(struct felix), GFP_KERNEL);
2278 dev_err(&pdev->dev, "Failed to allocate driver memory\n");
2279 goto err_alloc_felix;
2282 pci_set_drvdata(pdev, felix);
2283 ocelot = &felix->ocelot;
2284 ocelot->dev = &pdev->dev;
2285 ocelot->num_flooding_pgids = OCELOT_NUM_TC;
2286 felix->info = &felix_info_vsc9959;
2287 felix->switch_base = pci_resource_start(pdev, VSC9959_SWITCH_PCI_BAR);
2288 felix->imdio_base = pci_resource_start(pdev, VSC9959_IMDIO_PCI_BAR);
2290 pci_set_master(pdev);
2292 err = devm_request_threaded_irq(&pdev->dev, pdev->irq, NULL,
2293 &felix_irq_handler, IRQF_ONESHOT,
2294 "felix-intb", ocelot);
2296 dev_err(&pdev->dev, "Failed to request irq\n");
2302 ds = kzalloc(sizeof(struct dsa_switch), GFP_KERNEL);
2305 dev_err(&pdev->dev, "Failed to allocate DSA switch\n");
2309 ds->dev = &pdev->dev;
2310 ds->num_ports = felix->info->num_ports;
2311 ds->num_tx_queues = felix->info->num_tx_queues;
2312 ds->ops = &felix_switch_ops;
2315 felix->tag_proto = DSA_TAG_PROTO_OCELOT;
2317 err = dsa_register_switch(ds);
2319 dev_err(&pdev->dev, "Failed to register DSA switch: %d\n", err);
2320 goto err_register_ds;
2331 pci_disable_device(pdev);
2336 static void felix_pci_remove(struct pci_dev *pdev)
2338 struct felix *felix = pci_get_drvdata(pdev);
2343 dsa_unregister_switch(felix->ds);
2348 pci_disable_device(pdev);
2350 pci_set_drvdata(pdev, NULL);
2353 static void felix_pci_shutdown(struct pci_dev *pdev)
2355 struct felix *felix = pci_get_drvdata(pdev);
2360 dsa_switch_shutdown(felix->ds);
2362 pci_set_drvdata(pdev, NULL);
2365 static struct pci_device_id felix_ids[] = {
2368 PCI_DEVICE(PCI_VENDOR_ID_FREESCALE, 0xEEF0),
2372 MODULE_DEVICE_TABLE(pci, felix_ids);
2374 static struct pci_driver felix_vsc9959_pci_driver = {
2375 .name = "mscc_felix",
2376 .id_table = felix_ids,
2377 .probe = felix_pci_probe,
2378 .remove = felix_pci_remove,
2379 .shutdown = felix_pci_shutdown,
2381 module_pci_driver(felix_vsc9959_pci_driver);
2383 MODULE_DESCRIPTION("Felix Switch driver");
2384 MODULE_LICENSE("GPL v2");