drivers/net/dsa/ocelot/felix_vsc9959.c

   1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
   2 /* Copyright 2017 Microsemi Corporation
   3  * Copyright 2018-2019 NXP Semiconductors
   4  */
   5 #include <linux/fsl/enetc_mdio.h>
   6 #include <soc/mscc/ocelot_qsys.h>
   7 #include <soc/mscc/ocelot_vcap.h>
   8 #include <soc/mscc/ocelot_ptp.h>
   9 #include <soc/mscc/ocelot_sys.h>
  10 #include <soc/mscc/ocelot.h>
  11 #include <linux/packing.h>
  12 #include <linux/pcs-lynx.h>
  13 #include <net/pkt_sched.h>
  14 #include <linux/iopoll.h>
  15 #include <linux/mdio.h>
  16 #include <linux/pci.h>
  17 #include "felix.h"
  18
  19 #define VSC9959_TAS_GCL_ENTRY_MAX       63
  20
  21 static const u32 vsc9959_ana_regmap[] = {
  22         REG(ANA_ADVLEARN,                       0x0089a0),
  23         REG(ANA_VLANMASK,                       0x0089a4),
  24         REG_RESERVED(ANA_PORT_B_DOMAIN),
  25         REG(ANA_ANAGEFIL,                       0x0089ac),
  26         REG(ANA_ANEVENTS,                       0x0089b0),
  27         REG(ANA_STORMLIMIT_BURST,               0x0089b4),
  28         REG(ANA_STORMLIMIT_CFG,                 0x0089b8),
  29         REG(ANA_ISOLATED_PORTS,                 0x0089c8),
  30         REG(ANA_COMMUNITY_PORTS,                0x0089cc),
  31         REG(ANA_AUTOAGE,                        0x0089d0),
  32         REG(ANA_MACTOPTIONS,                    0x0089d4),
  33         REG(ANA_LEARNDISC,                      0x0089d8),
  34         REG(ANA_AGENCTRL,                       0x0089dc),
  35         REG(ANA_MIRRORPORTS,                    0x0089e0),
  36         REG(ANA_EMIRRORPORTS,                   0x0089e4),
  37         REG(ANA_FLOODING,                       0x0089e8),
  38         REG(ANA_FLOODING_IPMC,                  0x008a08),
  39         REG(ANA_SFLOW_CFG,                      0x008a0c),
  40         REG(ANA_PORT_MODE,                      0x008a28),
  41         REG(ANA_CUT_THRU_CFG,                   0x008a48),
  42         REG(ANA_PGID_PGID,                      0x008400),
  43         REG(ANA_TABLES_ANMOVED,                 0x007f1c),
  44         REG(ANA_TABLES_MACHDATA,                0x007f20),
  45         REG(ANA_TABLES_MACLDATA,                0x007f24),
  46         REG(ANA_TABLES_STREAMDATA,              0x007f28),
  47         REG(ANA_TABLES_MACACCESS,               0x007f2c),
  48         REG(ANA_TABLES_MACTINDX,                0x007f30),
  49         REG(ANA_TABLES_VLANACCESS,              0x007f34),
  50         REG(ANA_TABLES_VLANTIDX,                0x007f38),
  51         REG(ANA_TABLES_ISDXACCESS,              0x007f3c),
  52         REG(ANA_TABLES_ISDXTIDX,                0x007f40),
  53         REG(ANA_TABLES_ENTRYLIM,                0x007f00),
  54         REG(ANA_TABLES_PTP_ID_HIGH,             0x007f44),
  55         REG(ANA_TABLES_PTP_ID_LOW,              0x007f48),
  56         REG(ANA_TABLES_STREAMACCESS,            0x007f4c),
  57         REG(ANA_TABLES_STREAMTIDX,              0x007f50),
  58         REG(ANA_TABLES_SEQ_HISTORY,             0x007f54),
  59         REG(ANA_TABLES_SEQ_MASK,                0x007f58),
  60         REG(ANA_TABLES_SFID_MASK,               0x007f5c),
  61         REG(ANA_TABLES_SFIDACCESS,              0x007f60),
  62         REG(ANA_TABLES_SFIDTIDX,                0x007f64),
  63         REG(ANA_MSTI_STATE,                     0x008600),
  64         REG(ANA_OAM_UPM_LM_CNT,                 0x008000),
  65         REG(ANA_SG_ACCESS_CTRL,                 0x008a64),
  66         REG(ANA_SG_CONFIG_REG_1,                0x007fb0),
  67         REG(ANA_SG_CONFIG_REG_2,                0x007fb4),
  68         REG(ANA_SG_CONFIG_REG_3,                0x007fb8),
  69         REG(ANA_SG_CONFIG_REG_4,                0x007fbc),
  70         REG(ANA_SG_CONFIG_REG_5,                0x007fc0),
  71         REG(ANA_SG_GCL_GS_CONFIG,               0x007f80),
  72         REG(ANA_SG_GCL_TI_CONFIG,               0x007f90),
  73         REG(ANA_SG_STATUS_REG_1,                0x008980),
  74         REG(ANA_SG_STATUS_REG_2,                0x008984),
  75         REG(ANA_SG_STATUS_REG_3,                0x008988),
  76         REG(ANA_PORT_VLAN_CFG,                  0x007800),
  77         REG(ANA_PORT_DROP_CFG,                  0x007804),
  78         REG(ANA_PORT_QOS_CFG,                   0x007808),
  79         REG(ANA_PORT_VCAP_CFG,                  0x00780c),
  80         REG(ANA_PORT_VCAP_S1_KEY_CFG,           0x007810),
  81         REG(ANA_PORT_VCAP_S2_CFG,               0x00781c),
  82         REG(ANA_PORT_PCP_DEI_MAP,               0x007820),
  83         REG(ANA_PORT_CPU_FWD_CFG,               0x007860),
  84         REG(ANA_PORT_CPU_FWD_BPDU_CFG,          0x007864),
  85         REG(ANA_PORT_CPU_FWD_GARP_CFG,          0x007868),
  86         REG(ANA_PORT_CPU_FWD_CCM_CFG,           0x00786c),
  87         REG(ANA_PORT_PORT_CFG,                  0x007870),
  88         REG(ANA_PORT_POL_CFG,                   0x007874),
  89         REG(ANA_PORT_PTP_CFG,                   0x007878),
  90         REG(ANA_PORT_PTP_DLY1_CFG,              0x00787c),
  91         REG(ANA_PORT_PTP_DLY2_CFG,              0x007880),
  92         REG(ANA_PORT_SFID_CFG,                  0x007884),
  93         REG(ANA_PFC_PFC_CFG,                    0x008800),
  94         REG_RESERVED(ANA_PFC_PFC_TIMER),
  95         REG_RESERVED(ANA_IPT_OAM_MEP_CFG),
  96         REG_RESERVED(ANA_IPT_IPT),
  97         REG_RESERVED(ANA_PPT_PPT),
  98         REG_RESERVED(ANA_FID_MAP_FID_MAP),
  99         REG(ANA_AGGR_CFG,                       0x008a68),
 100         REG(ANA_CPUQ_CFG,                       0x008a6c),
 101         REG_RESERVED(ANA_CPUQ_CFG2),
 102         REG(ANA_CPUQ_8021_CFG,                  0x008a74),
 103         REG(ANA_DSCP_CFG,                       0x008ab4),
 104         REG(ANA_DSCP_REWR_CFG,                  0x008bb4),
 105         REG(ANA_VCAP_RNG_TYPE_CFG,              0x008bf4),
 106         REG(ANA_VCAP_RNG_VAL_CFG,               0x008c14),
 107         REG_RESERVED(ANA_VRAP_CFG),
 108         REG_RESERVED(ANA_VRAP_HDR_DATA),
 109         REG_RESERVED(ANA_VRAP_HDR_MASK),
 110         REG(ANA_DISCARD_CFG,                    0x008c40),
 111         REG(ANA_FID_CFG,                        0x008c44),
 112         REG(ANA_POL_PIR_CFG,                    0x004000),
 113         REG(ANA_POL_CIR_CFG,                    0x004004),
 114         REG(ANA_POL_MODE_CFG,                   0x004008),
 115         REG(ANA_POL_PIR_STATE,                  0x00400c),
 116         REG(ANA_POL_CIR_STATE,                  0x004010),
 117         REG_RESERVED(ANA_POL_STATE),
 118         REG(ANA_POL_FLOWC,                      0x008c48),
 119         REG(ANA_POL_HYST,                       0x008cb4),
 120         REG_RESERVED(ANA_POL_MISC_CFG),
 121 };
 122
 123 static const u32 vsc9959_qs_regmap[] = {
 124         REG(QS_XTR_GRP_CFG,                     0x000000),
 125         REG(QS_XTR_RD,                          0x000008),
 126         REG(QS_XTR_FRM_PRUNING,                 0x000010),
 127         REG(QS_XTR_FLUSH,                       0x000018),
 128         REG(QS_XTR_DATA_PRESENT,                0x00001c),
 129         REG(QS_XTR_CFG,                         0x000020),
 130         REG(QS_INJ_GRP_CFG,                     0x000024),
 131         REG(QS_INJ_WR,                          0x00002c),
 132         REG(QS_INJ_CTRL,                        0x000034),
 133         REG(QS_INJ_STATUS,                      0x00003c),
 134         REG(QS_INJ_ERR,                         0x000040),
 135         REG_RESERVED(QS_INH_DBG),
 136 };
 137
 138 static const u32 vsc9959_vcap_regmap[] = {
 139         /* VCAP_CORE_CFG */
 140         REG(VCAP_CORE_UPDATE_CTRL,              0x000000),
 141         REG(VCAP_CORE_MV_CFG,                   0x000004),
 142         /* VCAP_CORE_CACHE */
 143         REG(VCAP_CACHE_ENTRY_DAT,               0x000008),
 144         REG(VCAP_CACHE_MASK_DAT,                0x000108),
 145         REG(VCAP_CACHE_ACTION_DAT,              0x000208),
 146         REG(VCAP_CACHE_CNT_DAT,                 0x000308),
 147         REG(VCAP_CACHE_TG_DAT,                  0x000388),
 148         /* VCAP_CONST */
 149         REG(VCAP_CONST_VCAP_VER,                0x000398),
 150         REG(VCAP_CONST_ENTRY_WIDTH,             0x00039c),
 151         REG(VCAP_CONST_ENTRY_CNT,               0x0003a0),
 152         REG(VCAP_CONST_ENTRY_SWCNT,             0x0003a4),
 153         REG(VCAP_CONST_ENTRY_TG_WIDTH,          0x0003a8),
 154         REG(VCAP_CONST_ACTION_DEF_CNT,          0x0003ac),
 155         REG(VCAP_CONST_ACTION_WIDTH,            0x0003b0),
 156         REG(VCAP_CONST_CNT_WIDTH,               0x0003b4),
 157         REG(VCAP_CONST_CORE_CNT,                0x0003b8),
 158         REG(VCAP_CONST_IF_CNT,                  0x0003bc),
 159 };
 160
 161 static const u32 vsc9959_qsys_regmap[] = {
 162         REG(QSYS_PORT_MODE,                     0x00f460),
 163         REG(QSYS_SWITCH_PORT_MODE,              0x00f480),
 164         REG(QSYS_STAT_CNT_CFG,                  0x00f49c),
 165         REG(QSYS_EEE_CFG,                       0x00f4a0),
 166         REG(QSYS_EEE_THRES,                     0x00f4b8),
 167         REG(QSYS_IGR_NO_SHARING,                0x00f4bc),
 168         REG(QSYS_EGR_NO_SHARING,                0x00f4c0),
 169         REG(QSYS_SW_STATUS,                     0x00f4c4),
 170         REG(QSYS_EXT_CPU_CFG,                   0x00f4e0),
 171         REG_RESERVED(QSYS_PAD_CFG),
 172         REG(QSYS_CPU_GROUP_MAP,                 0x00f4e8),
 173         REG_RESERVED(QSYS_QMAP),
 174         REG_RESERVED(QSYS_ISDX_SGRP),
 175         REG_RESERVED(QSYS_TIMED_FRAME_ENTRY),
 176         REG(QSYS_TFRM_MISC,                     0x00f50c),
 177         REG(QSYS_TFRM_PORT_DLY,                 0x00f510),
 178         REG(QSYS_TFRM_TIMER_CFG_1,              0x00f514),
 179         REG(QSYS_TFRM_TIMER_CFG_2,              0x00f518),
 180         REG(QSYS_TFRM_TIMER_CFG_3,              0x00f51c),
 181         REG(QSYS_TFRM_TIMER_CFG_4,              0x00f520),
 182         REG(QSYS_TFRM_TIMER_CFG_5,              0x00f524),
 183         REG(QSYS_TFRM_TIMER_CFG_6,              0x00f528),
 184         REG(QSYS_TFRM_TIMER_CFG_7,              0x00f52c),
 185         REG(QSYS_TFRM_TIMER_CFG_8,              0x00f530),
 186         REG(QSYS_RED_PROFILE,                   0x00f534),
 187         REG(QSYS_RES_QOS_MODE,                  0x00f574),
 188         REG(QSYS_RES_CFG,                       0x00c000),
 189         REG(QSYS_RES_STAT,                      0x00c004),
 190         REG(QSYS_EGR_DROP_MODE,                 0x00f578),
 191         REG(QSYS_EQ_CTRL,                       0x00f57c),
 192         REG_RESERVED(QSYS_EVENTS_CORE),
 193         REG(QSYS_QMAXSDU_CFG_0,                 0x00f584),
 194         REG(QSYS_QMAXSDU_CFG_1,                 0x00f5a0),
 195         REG(QSYS_QMAXSDU_CFG_2,                 0x00f5bc),
 196         REG(QSYS_QMAXSDU_CFG_3,                 0x00f5d8),
 197         REG(QSYS_QMAXSDU_CFG_4,                 0x00f5f4),
 198         REG(QSYS_QMAXSDU_CFG_5,                 0x00f610),
 199         REG(QSYS_QMAXSDU_CFG_6,                 0x00f62c),
 200         REG(QSYS_QMAXSDU_CFG_7,                 0x00f648),
 201         REG(QSYS_PREEMPTION_CFG,                0x00f664),
 202         REG(QSYS_CIR_CFG,                       0x000000),
 203         REG(QSYS_EIR_CFG,                       0x000004),
 204         REG(QSYS_SE_CFG,                        0x000008),
 205         REG(QSYS_SE_DWRR_CFG,                   0x00000c),
 206         REG_RESERVED(QSYS_SE_CONNECT),
 207         REG(QSYS_SE_DLB_SENSE,                  0x000040),
 208         REG(QSYS_CIR_STATE,                     0x000044),
 209         REG(QSYS_EIR_STATE,                     0x000048),
 210         REG_RESERVED(QSYS_SE_STATE),
 211         REG(QSYS_HSCH_MISC_CFG,                 0x00f67c),
 212         REG(QSYS_TAG_CONFIG,                    0x00f680),
 213         REG(QSYS_TAS_PARAM_CFG_CTRL,            0x00f698),
 214         REG(QSYS_PORT_MAX_SDU,                  0x00f69c),
 215         REG(QSYS_PARAM_CFG_REG_1,               0x00f440),
 216         REG(QSYS_PARAM_CFG_REG_2,               0x00f444),
 217         REG(QSYS_PARAM_CFG_REG_3,               0x00f448),
 218         REG(QSYS_PARAM_CFG_REG_4,               0x00f44c),
 219         REG(QSYS_PARAM_CFG_REG_5,               0x00f450),
 220         REG(QSYS_GCL_CFG_REG_1,                 0x00f454),
 221         REG(QSYS_GCL_CFG_REG_2,                 0x00f458),
 222         REG(QSYS_PARAM_STATUS_REG_1,            0x00f400),
 223         REG(QSYS_PARAM_STATUS_REG_2,            0x00f404),
 224         REG(QSYS_PARAM_STATUS_REG_3,            0x00f408),
 225         REG(QSYS_PARAM_STATUS_REG_4,            0x00f40c),
 226         REG(QSYS_PARAM_STATUS_REG_5,            0x00f410),
 227         REG(QSYS_PARAM_STATUS_REG_6,            0x00f414),
 228         REG(QSYS_PARAM_STATUS_REG_7,            0x00f418),
 229         REG(QSYS_PARAM_STATUS_REG_8,            0x00f41c),
 230         REG(QSYS_PARAM_STATUS_REG_9,            0x00f420),
 231         REG(QSYS_GCL_STATUS_REG_1,              0x00f424),
 232         REG(QSYS_GCL_STATUS_REG_2,              0x00f428),
 233 };
 234
 235 static const u32 vsc9959_rew_regmap[] = {
 236         REG(REW_PORT_VLAN_CFG,                  0x000000),
 237         REG(REW_TAG_CFG,                        0x000004),
 238         REG(REW_PORT_CFG,                       0x000008),
 239         REG(REW_DSCP_CFG,                       0x00000c),
 240         REG(REW_PCP_DEI_QOS_MAP_CFG,            0x000010),
 241         REG(REW_PTP_CFG,                        0x000050),
 242         REG(REW_PTP_DLY1_CFG,                   0x000054),
 243         REG(REW_RED_TAG_CFG,                    0x000058),
 244         REG(REW_DSCP_REMAP_DP1_CFG,             0x000410),
 245         REG(REW_DSCP_REMAP_CFG,                 0x000510),
 246         REG_RESERVED(REW_STAT_CFG),
 247         REG_RESERVED(REW_REW_STICKY),
 248         REG_RESERVED(REW_PPT),
 249 };
 250
 251 static const u32 vsc9959_sys_regmap[] = {
 252         REG(SYS_COUNT_RX_OCTETS,                0x000000),
 253         REG(SYS_COUNT_RX_MULTICAST,             0x000008),
 254         REG(SYS_COUNT_RX_SHORTS,                0x000010),
 255         REG(SYS_COUNT_RX_FRAGMENTS,             0x000014),
 256         REG(SYS_COUNT_RX_JABBERS,               0x000018),
 257         REG(SYS_COUNT_RX_64,                    0x000024),
 258         REG(SYS_COUNT_RX_65_127,                0x000028),
 259         REG(SYS_COUNT_RX_128_255,               0x00002c),
 260         REG(SYS_COUNT_RX_256_1023,              0x000030),
 261         REG(SYS_COUNT_RX_1024_1526,             0x000034),
 262         REG(SYS_COUNT_RX_1527_MAX,              0x000038),
 263         REG(SYS_COUNT_RX_LONGS,                 0x000044),
 264         REG(SYS_COUNT_TX_OCTETS,                0x000200),
 265         REG(SYS_COUNT_TX_COLLISION,             0x000210),
 266         REG(SYS_COUNT_TX_DROPS,                 0x000214),
 267         REG(SYS_COUNT_TX_64,                    0x00021c),
 268         REG(SYS_COUNT_TX_65_127,                0x000220),
 269         REG(SYS_COUNT_TX_128_511,               0x000224),
 270         REG(SYS_COUNT_TX_512_1023,              0x000228),
 271         REG(SYS_COUNT_TX_1024_1526,             0x00022c),
 272         REG(SYS_COUNT_TX_1527_MAX,              0x000230),
 273         REG(SYS_COUNT_TX_AGING,                 0x000278),
 274         REG(SYS_RESET_CFG,                      0x000e00),
 275         REG(SYS_SR_ETYPE_CFG,                   0x000e04),
 276         REG(SYS_VLAN_ETYPE_CFG,                 0x000e08),
 277         REG(SYS_PORT_MODE,                      0x000e0c),
 278         REG(SYS_FRONT_PORT_MODE,                0x000e2c),
 279         REG(SYS_FRM_AGING,                      0x000e44),
 280         REG(SYS_STAT_CFG,                       0x000e48),
 281         REG(SYS_SW_STATUS,                      0x000e4c),
 282         REG_RESERVED(SYS_MISC_CFG),
 283         REG(SYS_REW_MAC_HIGH_CFG,               0x000e6c),
 284         REG(SYS_REW_MAC_LOW_CFG,                0x000e84),
 285         REG(SYS_TIMESTAMP_OFFSET,               0x000e9c),
 286         REG(SYS_PAUSE_CFG,                      0x000ea0),
 287         REG(SYS_PAUSE_TOT_CFG,                  0x000ebc),
 288         REG(SYS_ATOP,                           0x000ec0),
 289         REG(SYS_ATOP_TOT_CFG,                   0x000edc),
 290         REG(SYS_MAC_FC_CFG,                     0x000ee0),
 291         REG(SYS_MMGT,                           0x000ef8),
 292         REG_RESERVED(SYS_MMGT_FAST),
 293         REG_RESERVED(SYS_EVENTS_DIF),
 294         REG_RESERVED(SYS_EVENTS_CORE),
 295         REG_RESERVED(SYS_CNT),
 296         REG(SYS_PTP_STATUS,                     0x000f14),
 297         REG(SYS_PTP_TXSTAMP,                    0x000f18),
 298         REG(SYS_PTP_NXT,                        0x000f1c),
 299         REG(SYS_PTP_CFG,                        0x000f20),
 300         REG(SYS_RAM_INIT,                       0x000f24),
 301         REG_RESERVED(SYS_CM_ADDR),
 302         REG_RESERVED(SYS_CM_DATA_WR),
 303         REG_RESERVED(SYS_CM_DATA_RD),
 304         REG_RESERVED(SYS_CM_OP),
 305         REG_RESERVED(SYS_CM_DATA),
 306 };
 307
 308 static const u32 vsc9959_ptp_regmap[] = {
 309         REG(PTP_PIN_CFG,                        0x000000),
 310         REG(PTP_PIN_TOD_SEC_MSB,                0x000004),
 311         REG(PTP_PIN_TOD_SEC_LSB,                0x000008),
 312         REG(PTP_PIN_TOD_NSEC,                   0x00000c),
 313         REG(PTP_PIN_WF_HIGH_PERIOD,             0x000014),
 314         REG(PTP_PIN_WF_LOW_PERIOD,              0x000018),
 315         REG(PTP_CFG_MISC,                       0x0000a0),
 316         REG(PTP_CLK_CFG_ADJ_CFG,                0x0000a4),
 317         REG(PTP_CLK_CFG_ADJ_FREQ,               0x0000a8),
 318 };
 319
 320 static const u32 vsc9959_gcb_regmap[] = {
 321         REG(GCB_SOFT_RST,                       0x000004),
 322 };
 323
 324 static const u32 vsc9959_dev_gmii_regmap[] = {
 325         REG(DEV_CLOCK_CFG,                      0x0),
 326         REG(DEV_PORT_MISC,                      0x4),
 327         REG(DEV_EVENTS,                         0x8),
 328         REG(DEV_EEE_CFG,                        0xc),
 329         REG(DEV_RX_PATH_DELAY,                  0x10),
 330         REG(DEV_TX_PATH_DELAY,                  0x14),
 331         REG(DEV_PTP_PREDICT_CFG,                0x18),
 332         REG(DEV_MAC_ENA_CFG,                    0x1c),
 333         REG(DEV_MAC_MODE_CFG,                   0x20),
 334         REG(DEV_MAC_MAXLEN_CFG,                 0x24),
 335         REG(DEV_MAC_TAGS_CFG,                   0x28),
 336         REG(DEV_MAC_ADV_CHK_CFG,                0x2c),
 337         REG(DEV_MAC_IFG_CFG,                    0x30),
 338         REG(DEV_MAC_HDX_CFG,                    0x34),
 339         REG(DEV_MAC_DBG_CFG,                    0x38),
 340         REG(DEV_MAC_FC_MAC_LOW_CFG,             0x3c),
 341         REG(DEV_MAC_FC_MAC_HIGH_CFG,            0x40),
 342         REG(DEV_MAC_STICKY,                     0x44),
 343         REG_RESERVED(PCS1G_CFG),
 344         REG_RESERVED(PCS1G_MODE_CFG),
 345         REG_RESERVED(PCS1G_SD_CFG),
 346         REG_RESERVED(PCS1G_ANEG_CFG),
 347         REG_RESERVED(PCS1G_ANEG_NP_CFG),
 348         REG_RESERVED(PCS1G_LB_CFG),
 349         REG_RESERVED(PCS1G_DBG_CFG),
 350         REG_RESERVED(PCS1G_CDET_CFG),
 351         REG_RESERVED(PCS1G_ANEG_STATUS),
 352         REG_RESERVED(PCS1G_ANEG_NP_STATUS),
 353         REG_RESERVED(PCS1G_LINK_STATUS),
 354         REG_RESERVED(PCS1G_LINK_DOWN_CNT),
 355         REG_RESERVED(PCS1G_STICKY),
 356         REG_RESERVED(PCS1G_DEBUG_STATUS),
 357         REG_RESERVED(PCS1G_LPI_CFG),
 358         REG_RESERVED(PCS1G_LPI_WAKE_ERROR_CNT),
 359         REG_RESERVED(PCS1G_LPI_STATUS),
 360         REG_RESERVED(PCS1G_TSTPAT_MODE_CFG),
 361         REG_RESERVED(PCS1G_TSTPAT_STATUS),
 362         REG_RESERVED(DEV_PCS_FX100_CFG),
 363         REG_RESERVED(DEV_PCS_FX100_STATUS),
 364 };
 365
 366 static const u32 *vsc9959_regmap[TARGET_MAX] = {
 367         [ANA]   = vsc9959_ana_regmap,
 368         [QS]    = vsc9959_qs_regmap,
 369         [QSYS]  = vsc9959_qsys_regmap,
 370         [REW]   = vsc9959_rew_regmap,
 371         [SYS]   = vsc9959_sys_regmap,
 372         [S0]    = vsc9959_vcap_regmap,
 373         [S1]    = vsc9959_vcap_regmap,
 374         [S2]    = vsc9959_vcap_regmap,
 375         [PTP]   = vsc9959_ptp_regmap,
 376         [GCB]   = vsc9959_gcb_regmap,
 377         [DEV_GMII] = vsc9959_dev_gmii_regmap,
 378 };
 379
 380 /* Addresses are relative to the PCI device's base address */
 381 static const struct resource vsc9959_target_io_res[TARGET_MAX] = {
 382         [ANA] = {
 383                 .start  = 0x0280000,
 384                 .end    = 0x028ffff,
 385                 .name   = "ana",
 386         },
 387         [QS] = {
 388                 .start  = 0x0080000,
 389                 .end    = 0x00800ff,
 390                 .name   = "qs",
 391         },
 392         [QSYS] = {
 393                 .start  = 0x0200000,
 394                 .end    = 0x021ffff,
 395                 .name   = "qsys",
 396         },
 397         [REW] = {
 398                 .start  = 0x0030000,
 399                 .end    = 0x003ffff,
 400                 .name   = "rew",
 401         },
 402         [SYS] = {
 403                 .start  = 0x0010000,
 404                 .end    = 0x001ffff,
 405                 .name   = "sys",
 406         },
 407         [S0] = {
 408                 .start  = 0x0040000,
 409                 .end    = 0x00403ff,
 410                 .name   = "s0",
 411         },
 412         [S1] = {
 413                 .start  = 0x0050000,
 414                 .end    = 0x00503ff,
 415                 .name   = "s1",
 416         },
 417         [S2] = {
 418                 .start  = 0x0060000,
 419                 .end    = 0x00603ff,
 420                 .name   = "s2",
 421         },
 422         [PTP] = {
 423                 .start  = 0x0090000,
 424                 .end    = 0x00900cb,
 425                 .name   = "ptp",
 426         },
 427         [GCB] = {
 428                 .start  = 0x0070000,
 429                 .end    = 0x00701ff,
 430                 .name   = "devcpu_gcb",
 431         },
 432 };
 433
 434 static const struct resource vsc9959_port_io_res[] = {
 435         {
 436                 .start  = 0x0100000,
 437                 .end    = 0x010ffff,
 438                 .name   = "port0",
 439         },
 440         {
 441                 .start  = 0x0110000,
 442                 .end    = 0x011ffff,
 443                 .name   = "port1",
 444         },
 445         {
 446                 .start  = 0x0120000,
 447                 .end    = 0x012ffff,
 448                 .name   = "port2",
 449         },
 450         {
 451                 .start  = 0x0130000,
 452                 .end    = 0x013ffff,
 453                 .name   = "port3",
 454         },
 455         {
 456                 .start  = 0x0140000,
 457                 .end    = 0x014ffff,
 458                 .name   = "port4",
 459         },
 460         {
 461                 .start  = 0x0150000,
 462                 .end    = 0x015ffff,
 463                 .name   = "port5",
 464         },
 465 };
 466
 467 /* Port MAC 0 Internal MDIO bus through which the SerDes acting as an
 468  * SGMII/QSGMII MAC PCS can be found.
 469  */
 470 static const struct resource vsc9959_imdio_res = {
 471         .start          = 0x8030,
 472         .end            = 0x8040,
 473         .name           = "imdio",
 474 };
 475
 476 static const struct reg_field vsc9959_regfields[REGFIELD_MAX] = {
 477         [ANA_ADVLEARN_VLAN_CHK] = REG_FIELD(ANA_ADVLEARN, 6, 6),
 478         [ANA_ADVLEARN_LEARN_MIRROR] = REG_FIELD(ANA_ADVLEARN, 0, 5),
 479         [ANA_ANEVENTS_FLOOD_DISCARD] = REG_FIELD(ANA_ANEVENTS, 30, 30),
 480         [ANA_ANEVENTS_AUTOAGE] = REG_FIELD(ANA_ANEVENTS, 26, 26),
 481         [ANA_ANEVENTS_STORM_DROP] = REG_FIELD(ANA_ANEVENTS, 24, 24),
 482         [ANA_ANEVENTS_LEARN_DROP] = REG_FIELD(ANA_ANEVENTS, 23, 23),
 483         [ANA_ANEVENTS_AGED_ENTRY] = REG_FIELD(ANA_ANEVENTS, 22, 22),
 484         [ANA_ANEVENTS_CPU_LEARN_FAILED] = REG_FIELD(ANA_ANEVENTS, 21, 21),
 485         [ANA_ANEVENTS_AUTO_LEARN_FAILED] = REG_FIELD(ANA_ANEVENTS, 20, 20),
 486         [ANA_ANEVENTS_LEARN_REMOVE] = REG_FIELD(ANA_ANEVENTS, 19, 19),
 487         [ANA_ANEVENTS_AUTO_LEARNED] = REG_FIELD(ANA_ANEVENTS, 18, 18),
 488         [ANA_ANEVENTS_AUTO_MOVED] = REG_FIELD(ANA_ANEVENTS, 17, 17),
 489         [ANA_ANEVENTS_CLASSIFIED_DROP] = REG_FIELD(ANA_ANEVENTS, 15, 15),
 490         [ANA_ANEVENTS_CLASSIFIED_COPY] = REG_FIELD(ANA_ANEVENTS, 14, 14),
 491         [ANA_ANEVENTS_VLAN_DISCARD] = REG_FIELD(ANA_ANEVENTS, 13, 13),
 492         [ANA_ANEVENTS_FWD_DISCARD] = REG_FIELD(ANA_ANEVENTS, 12, 12),
 493         [ANA_ANEVENTS_MULTICAST_FLOOD] = REG_FIELD(ANA_ANEVENTS, 11, 11),
 494         [ANA_ANEVENTS_UNICAST_FLOOD] = REG_FIELD(ANA_ANEVENTS, 10, 10),
 495         [ANA_ANEVENTS_DEST_KNOWN] = REG_FIELD(ANA_ANEVENTS, 9, 9),
 496         [ANA_ANEVENTS_BUCKET3_MATCH] = REG_FIELD(ANA_ANEVENTS, 8, 8),
 497         [ANA_ANEVENTS_BUCKET2_MATCH] = REG_FIELD(ANA_ANEVENTS, 7, 7),
 498         [ANA_ANEVENTS_BUCKET1_MATCH] = REG_FIELD(ANA_ANEVENTS, 6, 6),
 499         [ANA_ANEVENTS_BUCKET0_MATCH] = REG_FIELD(ANA_ANEVENTS, 5, 5),
 500         [ANA_ANEVENTS_CPU_OPERATION] = REG_FIELD(ANA_ANEVENTS, 4, 4),
 501         [ANA_ANEVENTS_DMAC_LOOKUP] = REG_FIELD(ANA_ANEVENTS, 3, 3),
 502         [ANA_ANEVENTS_SMAC_LOOKUP] = REG_FIELD(ANA_ANEVENTS, 2, 2),
 503         [ANA_ANEVENTS_SEQ_GEN_ERR_0] = REG_FIELD(ANA_ANEVENTS, 1, 1),
 504         [ANA_ANEVENTS_SEQ_GEN_ERR_1] = REG_FIELD(ANA_ANEVENTS, 0, 0),
 505         [ANA_TABLES_MACACCESS_B_DOM] = REG_FIELD(ANA_TABLES_MACACCESS, 16, 16),
 506         [ANA_TABLES_MACTINDX_BUCKET] = REG_FIELD(ANA_TABLES_MACTINDX, 11, 12),
 507         [ANA_TABLES_MACTINDX_M_INDEX] = REG_FIELD(ANA_TABLES_MACTINDX, 0, 10),
 508         [SYS_RESET_CFG_CORE_ENA] = REG_FIELD(SYS_RESET_CFG, 0, 0),
 509         [GCB_SOFT_RST_SWC_RST] = REG_FIELD(GCB_SOFT_RST, 0, 0),
 510         /* Replicated per number of ports (7), register size 4 per port */
 511         [QSYS_SWITCH_PORT_MODE_PORT_ENA] = REG_FIELD_ID(QSYS_SWITCH_PORT_MODE, 14, 14, 7, 4),
 512         [QSYS_SWITCH_PORT_MODE_SCH_NEXT_CFG] = REG_FIELD_ID(QSYS_SWITCH_PORT_MODE, 11, 13, 7, 4),
 513         [QSYS_SWITCH_PORT_MODE_YEL_RSRVD] = REG_FIELD_ID(QSYS_SWITCH_PORT_MODE, 10, 10, 7, 4),
 514         [QSYS_SWITCH_PORT_MODE_INGRESS_DROP_MODE] = REG_FIELD_ID(QSYS_SWITCH_PORT_MODE, 9, 9, 7, 4),
 515         [QSYS_SWITCH_PORT_MODE_TX_PFC_ENA] = REG_FIELD_ID(QSYS_SWITCH_PORT_MODE, 1, 8, 7, 4),
 516         [QSYS_SWITCH_PORT_MODE_TX_PFC_MODE] = REG_FIELD_ID(QSYS_SWITCH_PORT_MODE, 0, 0, 7, 4),
 517         [SYS_PORT_MODE_DATA_WO_TS] = REG_FIELD_ID(SYS_PORT_MODE, 5, 6, 7, 4),
 518         [SYS_PORT_MODE_INCL_INJ_HDR] = REG_FIELD_ID(SYS_PORT_MODE, 3, 4, 7, 4),
 519         [SYS_PORT_MODE_INCL_XTR_HDR] = REG_FIELD_ID(SYS_PORT_MODE, 1, 2, 7, 4),
 520         [SYS_PORT_MODE_INCL_HDR_ERR] = REG_FIELD_ID(SYS_PORT_MODE, 0, 0, 7, 4),
 521         [SYS_PAUSE_CFG_PAUSE_START] = REG_FIELD_ID(SYS_PAUSE_CFG, 10, 18, 7, 4),
 522         [SYS_PAUSE_CFG_PAUSE_STOP] = REG_FIELD_ID(SYS_PAUSE_CFG, 1, 9, 7, 4),
 523         [SYS_PAUSE_CFG_PAUSE_ENA] = REG_FIELD_ID(SYS_PAUSE_CFG, 0, 1, 7, 4),
 524 };
 525
 526 static const struct ocelot_stat_layout vsc9959_stats_layout[] = {
 527         { .offset = 0x00,       .name = "rx_octets", },
 528         { .offset = 0x01,       .name = "rx_unicast", },
 529         { .offset = 0x02,       .name = "rx_multicast", },
 530         { .offset = 0x03,       .name = "rx_broadcast", },
 531         { .offset = 0x04,       .name = "rx_shorts", },
 532         { .offset = 0x05,       .name = "rx_fragments", },
 533         { .offset = 0x06,       .name = "rx_jabbers", },
 534         { .offset = 0x07,       .name = "rx_crc_align_errs", },
 535         { .offset = 0x08,       .name = "rx_sym_errs", },
 536         { .offset = 0x09,       .name = "rx_frames_below_65_octets", },
 537         { .offset = 0x0A,       .name = "rx_frames_65_to_127_octets", },
 538         { .offset = 0x0B,       .name = "rx_frames_128_to_255_octets", },
 539         { .offset = 0x0C,       .name = "rx_frames_256_to_511_octets", },
 540         { .offset = 0x0D,       .name = "rx_frames_512_to_1023_octets", },
 541         { .offset = 0x0E,       .name = "rx_frames_1024_to_1526_octets", },
 542         { .offset = 0x0F,       .name = "rx_frames_over_1526_octets", },
 543         { .offset = 0x10,       .name = "rx_pause", },
 544         { .offset = 0x11,       .name = "rx_control", },
 545         { .offset = 0x12,       .name = "rx_longs", },
 546         { .offset = 0x13,       .name = "rx_classified_drops", },
 547         { .offset = 0x14,       .name = "rx_red_prio_0", },
 548         { .offset = 0x15,       .name = "rx_red_prio_1", },
 549         { .offset = 0x16,       .name = "rx_red_prio_2", },
 550         { .offset = 0x17,       .name = "rx_red_prio_3", },
 551         { .offset = 0x18,       .name = "rx_red_prio_4", },
 552         { .offset = 0x19,       .name = "rx_red_prio_5", },
 553         { .offset = 0x1A,       .name = "rx_red_prio_6", },
 554         { .offset = 0x1B,       .name = "rx_red_prio_7", },
 555         { .offset = 0x1C,       .name = "rx_yellow_prio_0", },
 556         { .offset = 0x1D,       .name = "rx_yellow_prio_1", },
 557         { .offset = 0x1E,       .name = "rx_yellow_prio_2", },
 558         { .offset = 0x1F,       .name = "rx_yellow_prio_3", },
 559         { .offset = 0x20,       .name = "rx_yellow_prio_4", },
 560         { .offset = 0x21,       .name = "rx_yellow_prio_5", },
 561         { .offset = 0x22,       .name = "rx_yellow_prio_6", },
 562         { .offset = 0x23,       .name = "rx_yellow_prio_7", },
 563         { .offset = 0x24,       .name = "rx_green_prio_0", },
 564         { .offset = 0x25,       .name = "rx_green_prio_1", },
 565         { .offset = 0x26,       .name = "rx_green_prio_2", },
 566         { .offset = 0x27,       .name = "rx_green_prio_3", },
 567         { .offset = 0x28,       .name = "rx_green_prio_4", },
 568         { .offset = 0x29,       .name = "rx_green_prio_5", },
 569         { .offset = 0x2A,       .name = "rx_green_prio_6", },
 570         { .offset = 0x2B,       .name = "rx_green_prio_7", },
 571         { .offset = 0x80,       .name = "tx_octets", },
 572         { .offset = 0x81,       .name = "tx_unicast", },
 573         { .offset = 0x82,       .name = "tx_multicast", },
 574         { .offset = 0x83,       .name = "tx_broadcast", },
 575         { .offset = 0x84,       .name = "tx_collision", },
 576         { .offset = 0x85,       .name = "tx_drops", },
 577         { .offset = 0x86,       .name = "tx_pause", },
 578         { .offset = 0x87,       .name = "tx_frames_below_65_octets", },
 579         { .offset = 0x88,       .name = "tx_frames_65_to_127_octets", },
 580         { .offset = 0x89,       .name = "tx_frames_128_255_octets", },
 581         { .offset = 0x8B,       .name = "tx_frames_256_511_octets", },
 582         { .offset = 0x8C,       .name = "tx_frames_1024_1526_octets", },
 583         { .offset = 0x8D,       .name = "tx_frames_over_1526_octets", },
 584         { .offset = 0x8E,       .name = "tx_yellow_prio_0", },
 585         { .offset = 0x8F,       .name = "tx_yellow_prio_1", },
 586         { .offset = 0x90,       .name = "tx_yellow_prio_2", },
 587         { .offset = 0x91,       .name = "tx_yellow_prio_3", },
 588         { .offset = 0x92,       .name = "tx_yellow_prio_4", },
 589         { .offset = 0x93,       .name = "tx_yellow_prio_5", },
 590         { .offset = 0x94,       .name = "tx_yellow_prio_6", },
 591         { .offset = 0x95,       .name = "tx_yellow_prio_7", },
 592         { .offset = 0x96,       .name = "tx_green_prio_0", },
 593         { .offset = 0x97,       .name = "tx_green_prio_1", },
 594         { .offset = 0x98,       .name = "tx_green_prio_2", },
 595         { .offset = 0x99,       .name = "tx_green_prio_3", },
 596         { .offset = 0x9A,       .name = "tx_green_prio_4", },
 597         { .offset = 0x9B,       .name = "tx_green_prio_5", },
 598         { .offset = 0x9C,       .name = "tx_green_prio_6", },
 599         { .offset = 0x9D,       .name = "tx_green_prio_7", },
 600         { .offset = 0x9E,       .name = "tx_aged", },
 601         { .offset = 0x100,      .name = "drop_local", },
 602         { .offset = 0x101,      .name = "drop_tail", },
 603         { .offset = 0x102,      .name = "drop_yellow_prio_0", },
 604         { .offset = 0x103,      .name = "drop_yellow_prio_1", },
 605         { .offset = 0x104,      .name = "drop_yellow_prio_2", },
 606         { .offset = 0x105,      .name = "drop_yellow_prio_3", },
 607         { .offset = 0x106,      .name = "drop_yellow_prio_4", },
 608         { .offset = 0x107,      .name = "drop_yellow_prio_5", },
 609         { .offset = 0x108,      .name = "drop_yellow_prio_6", },
 610         { .offset = 0x109,      .name = "drop_yellow_prio_7", },
 611         { .offset = 0x10A,      .name = "drop_green_prio_0", },
 612         { .offset = 0x10B,      .name = "drop_green_prio_1", },
 613         { .offset = 0x10C,      .name = "drop_green_prio_2", },
 614         { .offset = 0x10D,      .name = "drop_green_prio_3", },
 615         { .offset = 0x10E,      .name = "drop_green_prio_4", },
 616         { .offset = 0x10F,      .name = "drop_green_prio_5", },
 617         { .offset = 0x110,      .name = "drop_green_prio_6", },
 618         { .offset = 0x111,      .name = "drop_green_prio_7", },
 619 };
 620
 621 static const struct vcap_field vsc9959_vcap_es0_keys[] = {
 622         [VCAP_ES0_EGR_PORT]                     = {  0,  3},
 623         [VCAP_ES0_IGR_PORT]                     = {  3,  3},
 624         [VCAP_ES0_RSV]                          = {  6,  2},
 625         [VCAP_ES0_L2_MC]                        = {  8,  1},
 626         [VCAP_ES0_L2_BC]                        = {  9,  1},
 627         [VCAP_ES0_VID]                          = { 10, 12},
 628         [VCAP_ES0_DP]                           = { 22,  1},
 629         [VCAP_ES0_PCP]                          = { 23,  3},
 630 };
 631
 632 static const struct vcap_field vsc9959_vcap_es0_actions[] = {
 633         [VCAP_ES0_ACT_PUSH_OUTER_TAG]           = {  0,  2},
 634         [VCAP_ES0_ACT_PUSH_INNER_TAG]           = {  2,  1},
 635         [VCAP_ES0_ACT_TAG_A_TPID_SEL]           = {  3,  2},
 636         [VCAP_ES0_ACT_TAG_A_VID_SEL]            = {  5,  1},
 637         [VCAP_ES0_ACT_TAG_A_PCP_SEL]            = {  6,  2},
 638         [VCAP_ES0_ACT_TAG_A_DEI_SEL]            = {  8,  2},
 639         [VCAP_ES0_ACT_TAG_B_TPID_SEL]           = { 10,  2},
 640         [VCAP_ES0_ACT_TAG_B_VID_SEL]            = { 12,  1},
 641         [VCAP_ES0_ACT_TAG_B_PCP_SEL]            = { 13,  2},
 642         [VCAP_ES0_ACT_TAG_B_DEI_SEL]            = { 15,  2},
 643         [VCAP_ES0_ACT_VID_A_VAL]                = { 17, 12},
 644         [VCAP_ES0_ACT_PCP_A_VAL]                = { 29,  3},
 645         [VCAP_ES0_ACT_DEI_A_VAL]                = { 32,  1},
 646         [VCAP_ES0_ACT_VID_B_VAL]                = { 33, 12},
 647         [VCAP_ES0_ACT_PCP_B_VAL]                = { 45,  3},
 648         [VCAP_ES0_ACT_DEI_B_VAL]                = { 48,  1},
 649         [VCAP_ES0_ACT_RSV]                      = { 49, 23},
 650         [VCAP_ES0_ACT_HIT_STICKY]               = { 72,  1},
 651 };
 652
 653 static const struct vcap_field vsc9959_vcap_is1_keys[] = {
 654         [VCAP_IS1_HK_TYPE]                      = {  0,   1},
 655         [VCAP_IS1_HK_LOOKUP]                    = {  1,   2},
 656         [VCAP_IS1_HK_IGR_PORT_MASK]             = {  3,   7},
 657         [VCAP_IS1_HK_RSV]                       = { 10,   9},
 658         [VCAP_IS1_HK_OAM_Y1731]                 = { 19,   1},
 659         [VCAP_IS1_HK_L2_MC]                     = { 20,   1},
 660         [VCAP_IS1_HK_L2_BC]                     = { 21,   1},
 661         [VCAP_IS1_HK_IP_MC]                     = { 22,   1},
 662         [VCAP_IS1_HK_VLAN_TAGGED]               = { 23,   1},
 663         [VCAP_IS1_HK_VLAN_DBL_TAGGED]           = { 24,   1},
 664         [VCAP_IS1_HK_TPID]                      = { 25,   1},
 665         [VCAP_IS1_HK_VID]                       = { 26,  12},
 666         [VCAP_IS1_HK_DEI]                       = { 38,   1},
 667         [VCAP_IS1_HK_PCP]                       = { 39,   3},
 668         /* Specific Fields for IS1 Half Key S1_NORMAL */
 669         [VCAP_IS1_HK_L2_SMAC]                   = { 42,  48},
 670         [VCAP_IS1_HK_ETYPE_LEN]                 = { 90,   1},
 671         [VCAP_IS1_HK_ETYPE]                     = { 91,  16},
 672         [VCAP_IS1_HK_IP_SNAP]                   = {107,   1},
 673         [VCAP_IS1_HK_IP4]                       = {108,   1},
 674         /* Layer-3 Information */
 675         [VCAP_IS1_HK_L3_FRAGMENT]               = {109,   1},
 676         [VCAP_IS1_HK_L3_FRAG_OFS_GT0]           = {110,   1},
 677         [VCAP_IS1_HK_L3_OPTIONS]                = {111,   1},
 678         [VCAP_IS1_HK_L3_DSCP]                   = {112,   6},
 679         [VCAP_IS1_HK_L3_IP4_SIP]                = {118,  32},
 680         /* Layer-4 Information */
 681         [VCAP_IS1_HK_TCP_UDP]                   = {150,   1},
 682         [VCAP_IS1_HK_TCP]                       = {151,   1},
 683         [VCAP_IS1_HK_L4_SPORT]                  = {152,  16},
 684         [VCAP_IS1_HK_L4_RNG]                    = {168,   8},
 685         /* Specific Fields for IS1 Half Key S1_5TUPLE_IP4 */
 686         [VCAP_IS1_HK_IP4_INNER_TPID]            = { 42,   1},
 687         [VCAP_IS1_HK_IP4_INNER_VID]             = { 43,  12},
 688         [VCAP_IS1_HK_IP4_INNER_DEI]             = { 55,   1},
 689         [VCAP_IS1_HK_IP4_INNER_PCP]             = { 56,   3},
 690         [VCAP_IS1_HK_IP4_IP4]                   = { 59,   1},
 691         [VCAP_IS1_HK_IP4_L3_FRAGMENT]           = { 60,   1},
 692         [VCAP_IS1_HK_IP4_L3_FRAG_OFS_GT0]       = { 61,   1},
 693         [VCAP_IS1_HK_IP4_L3_OPTIONS]            = { 62,   1},
 694         [VCAP_IS1_HK_IP4_L3_DSCP]               = { 63,   6},
 695         [VCAP_IS1_HK_IP4_L3_IP4_DIP]            = { 69,  32},
 696         [VCAP_IS1_HK_IP4_L3_IP4_SIP]            = {101,  32},
 697         [VCAP_IS1_HK_IP4_L3_PROTO]              = {133,   8},
 698         [VCAP_IS1_HK_IP4_TCP_UDP]               = {141,   1},
 699         [VCAP_IS1_HK_IP4_TCP]                   = {142,   1},
 700         [VCAP_IS1_HK_IP4_L4_RNG]                = {143,   8},
 701         [VCAP_IS1_HK_IP4_IP_PAYLOAD_S1_5TUPLE]  = {151,  32},
 702 };
 703
 704 static const struct vcap_field vsc9959_vcap_is1_actions[] = {
 705         [VCAP_IS1_ACT_DSCP_ENA]                 = {  0,  1},
 706         [VCAP_IS1_ACT_DSCP_VAL]                 = {  1,  6},
 707         [VCAP_IS1_ACT_QOS_ENA]                  = {  7,  1},
 708         [VCAP_IS1_ACT_QOS_VAL]                  = {  8,  3},
 709         [VCAP_IS1_ACT_DP_ENA]                   = { 11,  1},
 710         [VCAP_IS1_ACT_DP_VAL]                   = { 12,  1},
 711         [VCAP_IS1_ACT_PAG_OVERRIDE_MASK]        = { 13,  8},
 712         [VCAP_IS1_ACT_PAG_VAL]                  = { 21,  8},
 713         [VCAP_IS1_ACT_RSV]                      = { 29,  9},
 714         /* The fields below are incorrectly shifted by 2 in the manual */
 715         [VCAP_IS1_ACT_VID_REPLACE_ENA]          = { 38,  1},
 716         [VCAP_IS1_ACT_VID_ADD_VAL]              = { 39, 12},
 717         [VCAP_IS1_ACT_FID_SEL]                  = { 51,  2},
 718         [VCAP_IS1_ACT_FID_VAL]                  = { 53, 13},
 719         [VCAP_IS1_ACT_PCP_DEI_ENA]              = { 66,  1},
 720         [VCAP_IS1_ACT_PCP_VAL]                  = { 67,  3},
 721         [VCAP_IS1_ACT_DEI_VAL]                  = { 70,  1},
 722         [VCAP_IS1_ACT_VLAN_POP_CNT_ENA]         = { 71,  1},
 723         [VCAP_IS1_ACT_VLAN_POP_CNT]             = { 72,  2},
 724         [VCAP_IS1_ACT_CUSTOM_ACE_TYPE_ENA]      = { 74,  4},
 725         [VCAP_IS1_ACT_HIT_STICKY]               = { 78,  1},
 726 };
 727
 728 static struct vcap_field vsc9959_vcap_is2_keys[] = {
 729         /* Common: 41 bits */
 730         [VCAP_IS2_TYPE]                         = {  0,   4},
 731         [VCAP_IS2_HK_FIRST]                     = {  4,   1},
 732         [VCAP_IS2_HK_PAG]                       = {  5,   8},
 733         [VCAP_IS2_HK_IGR_PORT_MASK]             = { 13,   7},
 734         [VCAP_IS2_HK_RSV2]                      = { 20,   1},
 735         [VCAP_IS2_HK_HOST_MATCH]                = { 21,   1},
 736         [VCAP_IS2_HK_L2_MC]                     = { 22,   1},
 737         [VCAP_IS2_HK_L2_BC]                     = { 23,   1},
 738         [VCAP_IS2_HK_VLAN_TAGGED]               = { 24,   1},
 739         [VCAP_IS2_HK_VID]                       = { 25,  12},
 740         [VCAP_IS2_HK_DEI]                       = { 37,   1},
 741         [VCAP_IS2_HK_PCP]                       = { 38,   3},
 742         /* MAC_ETYPE / MAC_LLC / MAC_SNAP / OAM common */
 743         [VCAP_IS2_HK_L2_DMAC]                   = { 41,  48},
 744         [VCAP_IS2_HK_L2_SMAC]                   = { 89,  48},
 745         /* MAC_ETYPE (TYPE=000) */
 746         [VCAP_IS2_HK_MAC_ETYPE_ETYPE]           = {137,  16},
 747         [VCAP_IS2_HK_MAC_ETYPE_L2_PAYLOAD0]     = {153,  16},
 748         [VCAP_IS2_HK_MAC_ETYPE_L2_PAYLOAD1]     = {169,   8},
 749         [VCAP_IS2_HK_MAC_ETYPE_L2_PAYLOAD2]     = {177,   3},
 750         /* MAC_LLC (TYPE=001) */
 751         [VCAP_IS2_HK_MAC_LLC_L2_LLC]            = {137,  40},
 752         /* MAC_SNAP (TYPE=010) */
 753         [VCAP_IS2_HK_MAC_SNAP_L2_SNAP]          = {137,  40},
 754         /* MAC_ARP (TYPE=011) */
 755         [VCAP_IS2_HK_MAC_ARP_SMAC]              = { 41,  48},
 756         [VCAP_IS2_HK_MAC_ARP_ADDR_SPACE_OK]     = { 89,   1},
 757         [VCAP_IS2_HK_MAC_ARP_PROTO_SPACE_OK]    = { 90,   1},
 758         [VCAP_IS2_HK_MAC_ARP_LEN_OK]            = { 91,   1},
 759         [VCAP_IS2_HK_MAC_ARP_TARGET_MATCH]      = { 92,   1},
 760         [VCAP_IS2_HK_MAC_ARP_SENDER_MATCH]      = { 93,   1},
 761         [VCAP_IS2_HK_MAC_ARP_OPCODE_UNKNOWN]    = { 94,   1},
 762         [VCAP_IS2_HK_MAC_ARP_OPCODE]            = { 95,   2},
 763         [VCAP_IS2_HK_MAC_ARP_L3_IP4_DIP]        = { 97,  32},
 764         [VCAP_IS2_HK_MAC_ARP_L3_IP4_SIP]        = {129,  32},
 765         [VCAP_IS2_HK_MAC_ARP_DIP_EQ_SIP]        = {161,   1},
 766         /* IP4_TCP_UDP / IP4_OTHER common */
 767         [VCAP_IS2_HK_IP4]                       = { 41,   1},
 768         [VCAP_IS2_HK_L3_FRAGMENT]               = { 42,   1},
 769         [VCAP_IS2_HK_L3_FRAG_OFS_GT0]           = { 43,   1},
 770         [VCAP_IS2_HK_L3_OPTIONS]                = { 44,   1},
 771         [VCAP_IS2_HK_IP4_L3_TTL_GT0]            = { 45,   1},
 772         [VCAP_IS2_HK_L3_TOS]                    = { 46,   8},
 773         [VCAP_IS2_HK_L3_IP4_DIP]                = { 54,  32},
 774         [VCAP_IS2_HK_L3_IP4_SIP]                = { 86,  32},
 775         [VCAP_IS2_HK_DIP_EQ_SIP]                = {118,   1},
 776         /* IP4_TCP_UDP (TYPE=100) */
 777         [VCAP_IS2_HK_TCP]                       = {119,   1},
 778         [VCAP_IS2_HK_L4_DPORT]                  = {120,  16},
 779         [VCAP_IS2_HK_L4_SPORT]                  = {136,  16},
 780         [VCAP_IS2_HK_L4_RNG]                    = {152,   8},
 781         [VCAP_IS2_HK_L4_SPORT_EQ_DPORT]         = {160,   1},
 782         [VCAP_IS2_HK_L4_SEQUENCE_EQ0]           = {161,   1},
 783         [VCAP_IS2_HK_L4_FIN]                    = {162,   1},
 784         [VCAP_IS2_HK_L4_SYN]                    = {163,   1},
 785         [VCAP_IS2_HK_L4_RST]                    = {164,   1},
 786         [VCAP_IS2_HK_L4_PSH]                    = {165,   1},
 787         [VCAP_IS2_HK_L4_ACK]                    = {166,   1},
 788         [VCAP_IS2_HK_L4_URG]                    = {167,   1},
 789         [VCAP_IS2_HK_L4_1588_DOM]               = {168,   8},
 790         [VCAP_IS2_HK_L4_1588_VER]               = {176,   4},
 791         /* IP4_OTHER (TYPE=101) */
 792         [VCAP_IS2_HK_IP4_L3_PROTO]              = {119,   8},
 793         [VCAP_IS2_HK_L3_PAYLOAD]                = {127,  56},
 794         /* IP6_STD (TYPE=110) */
 795         [VCAP_IS2_HK_IP6_L3_TTL_GT0]            = { 41,   1},
 796         [VCAP_IS2_HK_L3_IP6_SIP]                = { 42, 128},
 797         [VCAP_IS2_HK_IP6_L3_PROTO]              = {170,   8},
 798         /* OAM (TYPE=111) */
 799         [VCAP_IS2_HK_OAM_MEL_FLAGS]             = {137,   7},
 800         [VCAP_IS2_HK_OAM_VER]                   = {144,   5},
 801         [VCAP_IS2_HK_OAM_OPCODE]                = {149,   8},
 802         [VCAP_IS2_HK_OAM_FLAGS]                 = {157,   8},
 803         [VCAP_IS2_HK_OAM_MEPID]                 = {165,  16},
 804         [VCAP_IS2_HK_OAM_CCM_CNTS_EQ0]          = {181,   1},
 805         [VCAP_IS2_HK_OAM_IS_Y1731]              = {182,   1},
 806 };
 807
 808 static struct vcap_field vsc9959_vcap_is2_actions[] = {
 809         [VCAP_IS2_ACT_HIT_ME_ONCE]              = {  0,  1},
 810         [VCAP_IS2_ACT_CPU_COPY_ENA]             = {  1,  1},
 811         [VCAP_IS2_ACT_CPU_QU_NUM]               = {  2,  3},
 812         [VCAP_IS2_ACT_MASK_MODE]                = {  5,  2},
 813         [VCAP_IS2_ACT_MIRROR_ENA]               = {  7,  1},
 814         [VCAP_IS2_ACT_LRN_DIS]                  = {  8,  1},
 815         [VCAP_IS2_ACT_POLICE_ENA]               = {  9,  1},
 816         [VCAP_IS2_ACT_POLICE_IDX]               = { 10,  9},
 817         [VCAP_IS2_ACT_POLICE_VCAP_ONLY]         = { 19,  1},
 818         [VCAP_IS2_ACT_PORT_MASK]                = { 20,  6},
 819         [VCAP_IS2_ACT_REW_OP]                   = { 26,  9},
 820         [VCAP_IS2_ACT_SMAC_REPLACE_ENA]         = { 35,  1},
 821         [VCAP_IS2_ACT_RSV]                      = { 36,  2},
 822         [VCAP_IS2_ACT_ACL_ID]                   = { 38,  6},
 823         [VCAP_IS2_ACT_HIT_CNT]                  = { 44, 32},
 824 };
 825
 826 static struct vcap_props vsc9959_vcap_props[] = {
 827         [VCAP_ES0] = {
 828                 .action_type_width = 0,
 829                 .action_table = {
 830                         [ES0_ACTION_TYPE_NORMAL] = {
 831                                 .width = 72, /* HIT_STICKY not included */
 832                                 .count = 1,
 833                         },
 834                 },
 835                 .target = S0,
 836                 .keys = vsc9959_vcap_es0_keys,
 837                 .actions = vsc9959_vcap_es0_actions,
 838         },
 839         [VCAP_IS1] = {
 840                 .action_type_width = 0,
 841                 .action_table = {
 842                         [IS1_ACTION_TYPE_NORMAL] = {
 843                                 .width = 78, /* HIT_STICKY not included */
 844                                 .count = 4,
 845                         },
 846                 },
 847                 .target = S1,
 848                 .keys = vsc9959_vcap_is1_keys,
 849                 .actions = vsc9959_vcap_is1_actions,
 850         },
 851         [VCAP_IS2] = {
 852                 .action_type_width = 1,
 853                 .action_table = {
 854                         [IS2_ACTION_TYPE_NORMAL] = {
 855                                 .width = 44,
 856                                 .count = 2
 857                         },
 858                         [IS2_ACTION_TYPE_SMAC_SIP] = {
 859                                 .width = 6,
 860                                 .count = 4
 861                         },
 862                 },
 863                 .target = S2,
 864                 .keys = vsc9959_vcap_is2_keys,
 865                 .actions = vsc9959_vcap_is2_actions,
 866         },
 867 };
 868
 869 static const struct ptp_clock_info vsc9959_ptp_caps = {
 870         .owner          = THIS_MODULE,
 871         .name           = "felix ptp",
 872         .max_adj        = 0x7fffffff,
 873         .n_alarm        = 0,
 874         .n_ext_ts       = 0,
 875         .n_per_out      = OCELOT_PTP_PINS_NUM,
 876         .n_pins         = OCELOT_PTP_PINS_NUM,
 877         .pps            = 0,
 878         .gettime64      = ocelot_ptp_gettime64,
 879         .settime64      = ocelot_ptp_settime64,
 880         .adjtime        = ocelot_ptp_adjtime,
 881         .adjfine        = ocelot_ptp_adjfine,
 882         .verify         = ocelot_ptp_verify,
 883         .enable         = ocelot_ptp_enable,
 884 };
 885
 886 #define VSC9959_INIT_TIMEOUT                    50000
 887 #define VSC9959_GCB_RST_SLEEP                   100
 888 #define VSC9959_SYS_RAMINIT_SLEEP               80
 889
 890 static int vsc9959_gcb_soft_rst_status(struct ocelot *ocelot)
 891 {
 892         int val;
 893
 894         ocelot_field_read(ocelot, GCB_SOFT_RST_SWC_RST, &val);
 895
 896         return val;
 897 }
 898
 899 static int vsc9959_sys_ram_init_status(struct ocelot *ocelot)
 900 {
 901         return ocelot_read(ocelot, SYS_RAM_INIT);
 902 }
 903
 904 /* CORE_ENA is in SYS:SYSTEM:RESET_CFG
 905  * RAM_INIT is in SYS:RAM_CTRL:RAM_INIT
 906  */
 907 static int vsc9959_reset(struct ocelot *ocelot)
 908 {
 909         int val, err;
 910
 911         /* soft-reset the switch core */
 912         ocelot_field_write(ocelot, GCB_SOFT_RST_SWC_RST, 1);
 913
 914         err = readx_poll_timeout(vsc9959_gcb_soft_rst_status, ocelot, val, !val,
 915                                  VSC9959_GCB_RST_SLEEP, VSC9959_INIT_TIMEOUT);
 916         if (err) {
 917                 dev_err(ocelot->dev, "timeout: switch core reset\n");
 918                 return err;
 919         }
 920
 921         /* initialize switch mem ~40us */
 922         ocelot_write(ocelot, SYS_RAM_INIT_RAM_INIT, SYS_RAM_INIT);
 923         err = readx_poll_timeout(vsc9959_sys_ram_init_status, ocelot, val, !val,
 924                                  VSC9959_SYS_RAMINIT_SLEEP,
 925                                  VSC9959_INIT_TIMEOUT);
 926         if (err) {
 927                 dev_err(ocelot->dev, "timeout: switch sram init\n");
 928                 return err;
 929         }
 930
 931         /* enable switch core */
 932         ocelot_field_write(ocelot, SYS_RESET_CFG_CORE_ENA, 1);
 933
 934         return 0;
 935 }
 936
 937 static void vsc9959_phylink_validate(struct ocelot *ocelot, int port,
 938                                      unsigned long *supported,
 939                                      struct phylink_link_state *state)
 940 {
 941         struct ocelot_port *ocelot_port = ocelot->ports[port];
 942         __ETHTOOL_DECLARE_LINK_MODE_MASK(mask) = { 0, };
 943
 944         if (state->interface != PHY_INTERFACE_MODE_NA &&
 945             state->interface != ocelot_port->phy_mode) {
 946                 bitmap_zero(supported, __ETHTOOL_LINK_MODE_MASK_NBITS);
 947                 return;
 948         }
 949
 950         phylink_set_port_modes(mask);
 951         phylink_set(mask, Autoneg);
 952         phylink_set(mask, Pause);
 953         phylink_set(mask, Asym_Pause);
 954         phylink_set(mask, 10baseT_Half);
 955         phylink_set(mask, 10baseT_Full);
 956         phylink_set(mask, 100baseT_Half);
 957         phylink_set(mask, 100baseT_Full);
 958         phylink_set(mask, 1000baseT_Half);
 959         phylink_set(mask, 1000baseT_Full);
 960
 961         if (state->interface == PHY_INTERFACE_MODE_INTERNAL ||
 962             state->interface == PHY_INTERFACE_MODE_2500BASEX ||
 963             state->interface == PHY_INTERFACE_MODE_USXGMII) {
 964                 phylink_set(mask, 2500baseT_Full);
 965                 phylink_set(mask, 2500baseX_Full);
 966         }
 967
 968         bitmap_and(supported, supported, mask,
 969                    __ETHTOOL_LINK_MODE_MASK_NBITS);
 970         bitmap_and(state->advertising, state->advertising, mask,
 971                    __ETHTOOL_LINK_MODE_MASK_NBITS);
 972 }
 973
 974 static int vsc9959_prevalidate_phy_mode(struct ocelot *ocelot, int port,
 975                                         phy_interface_t phy_mode)
 976 {
 977         switch (phy_mode) {
 978         case PHY_INTERFACE_MODE_INTERNAL:
 979                 if (port != 4 && port != 5)
 980                         return -ENOTSUPP;
 981                 return 0;
 982         case PHY_INTERFACE_MODE_SGMII:
 983         case PHY_INTERFACE_MODE_QSGMII:
 984         case PHY_INTERFACE_MODE_USXGMII:
 985         case PHY_INTERFACE_MODE_2500BASEX:
 986                 /* Not supported on internal to-CPU ports */
 987                 if (port == 4 || port == 5)
 988                         return -ENOTSUPP;
 989                 return 0;
 990         default:
 991                 return -ENOTSUPP;
 992         }
 993 }
 994
 995 /* Watermark encode
 996  * Bit 8:   Unit; 0:1, 1:16
 997  * Bit 7-0: Value to be multiplied with unit
 998  */
 999 static u16 vsc9959_wm_enc(u16 value)
1000 {
1001         WARN_ON(value >= 16 * BIT(8));
1002
1003         if (value >= BIT(8))
1004                 return BIT(8) | (value / 16);
1005
1006         return value;
1007 }
1008
1009 static const struct ocelot_ops vsc9959_ops = {
1010         .reset                  = vsc9959_reset,
1011         .wm_enc                 = vsc9959_wm_enc,
1012         .port_to_netdev         = felix_port_to_netdev,
1013         .netdev_to_port         = felix_netdev_to_port,
1014 };
1015
1016 static int vsc9959_mdio_bus_alloc(struct ocelot *ocelot)
1017 {
1018         struct felix *felix = ocelot_to_felix(ocelot);
1019         struct enetc_mdio_priv *mdio_priv;
1020         struct device *dev = ocelot->dev;
1021         void __iomem *imdio_regs;
1022         struct resource res;
1023         struct enetc_hw *hw;
1024         struct mii_bus *bus;
1025         int port;
1026         int rc;
1027
1028         felix->pcs = devm_kcalloc(dev, felix->info->num_ports,
1029                                   sizeof(struct lynx_pcs *),
1030                                   GFP_KERNEL);
1031         if (!felix->pcs) {
1032                 dev_err(dev, "failed to allocate array for PCS PHYs\n");
1033                 return -ENOMEM;
1034         }
1035
1036         memcpy(&res, felix->info->imdio_res, sizeof(res));
1037         res.flags = IORESOURCE_MEM;
1038         res.start += felix->imdio_base;
1039         res.end += felix->imdio_base;
1040
1041         imdio_regs = devm_ioremap_resource(dev, &res);
1042         if (IS_ERR(imdio_regs)) {
1043                 dev_err(dev, "failed to map internal MDIO registers\n");
1044                 return PTR_ERR(imdio_regs);
1045         }
1046
1047         hw = enetc_hw_alloc(dev, imdio_regs);
1048         if (IS_ERR(hw)) {
1049                 dev_err(dev, "failed to allocate ENETC HW structure\n");
1050                 return PTR_ERR(hw);
1051         }
1052
1053         bus = devm_mdiobus_alloc_size(dev, sizeof(*mdio_priv));
1054         if (!bus)
1055                 return -ENOMEM;
1056
1057         bus->name = "VSC9959 internal MDIO bus";
1058         bus->read = enetc_mdio_read;
1059         bus->write = enetc_mdio_write;
1060         bus->parent = dev;
1061         mdio_priv = bus->priv;
1062         mdio_priv->hw = hw;
1063         /* This gets added to imdio_regs, which already maps addresses
1064          * starting with the proper offset.
1065          */
1066         mdio_priv->mdio_base = 0;
1067         snprintf(bus->id, MII_BUS_ID_SIZE, "%s-imdio", dev_name(dev));
1068
1069         /* Needed in order to initialize the bus mutex lock */
1070         rc = mdiobus_register(bus);
1071         if (rc < 0) {
1072                 dev_err(dev, "failed to register MDIO bus\n");
1073                 return rc;
1074         }
1075
1076         felix->imdio = bus;
1077
1078         for (port = 0; port < felix->info->num_ports; port++) {
1079                 struct ocelot_port *ocelot_port = ocelot->ports[port];
1080                 struct mdio_device *pcs;
1081                 struct lynx_pcs *lynx;
1082
1083                 if (dsa_is_unused_port(felix->ds, port))
1084                         continue;
1085
1086                 if (ocelot_port->phy_mode == PHY_INTERFACE_MODE_INTERNAL)
1087                         continue;
1088
1089                 pcs = mdio_device_create(felix->imdio, port);
1090                 if (IS_ERR(pcs))
1091                         continue;
1092
1093                 lynx = lynx_pcs_create(pcs);
1094                 if (!lynx) {
1095                         mdio_device_free(pcs);
1096                         continue;
1097                 }
1098
1099                 felix->pcs[port] = lynx;
1100
1101                 dev_info(dev, "Found PCS at internal MDIO address %d\n", port);
1102         }
1103
1104         return 0;
1105 }
1106
1107 static void vsc9959_mdio_bus_free(struct ocelot *ocelot)
1108 {
1109         struct felix *felix = ocelot_to_felix(ocelot);
1110         int port;
1111
1112         for (port = 0; port < ocelot->num_phys_ports; port++) {
1113                 struct lynx_pcs *pcs = felix->pcs[port];
1114
1115                 if (!pcs)
1116                         continue;
1117
1118                 mdio_device_free(pcs->mdio);
1119                 lynx_pcs_destroy(pcs);
1120         }
1121         mdiobus_unregister(felix->imdio);
1122 }
1123
1124 static void vsc9959_sched_speed_set(struct ocelot *ocelot, int port,
1125                                     u32 speed)
1126 {
1127         u8 tas_speed;
1128
1129         switch (speed) {
1130         case SPEED_10:
1131                 tas_speed = OCELOT_SPEED_10;
1132                 break;
1133         case SPEED_100:
1134                 tas_speed = OCELOT_SPEED_100;
1135                 break;
1136         case SPEED_1000:
1137                 tas_speed = OCELOT_SPEED_1000;
1138                 break;
1139         case SPEED_2500:
1140                 tas_speed = OCELOT_SPEED_2500;
1141                 break;
1142         default:
1143                 tas_speed = OCELOT_SPEED_1000;
1144                 break;
1145         }
1146
1147         ocelot_rmw_rix(ocelot,
1148                        QSYS_TAG_CONFIG_LINK_SPEED(tas_speed),
1149                        QSYS_TAG_CONFIG_LINK_SPEED_M,
1150                        QSYS_TAG_CONFIG, port);
1151 }
1152
1153 static void vsc9959_new_base_time(struct ocelot *ocelot, ktime_t base_time,
1154                                   u64 cycle_time,
1155                                   struct timespec64 *new_base_ts)
1156 {
1157         struct timespec64 ts;
1158         ktime_t new_base_time;
1159         ktime_t current_time;
1160
1161         ocelot_ptp_gettime64(&ocelot->ptp_info, &ts);
1162         current_time = timespec64_to_ktime(ts);
1163         new_base_time = base_time;
1164
1165         if (base_time < current_time) {
1166                 u64 nr_of_cycles = current_time - base_time;
1167
1168                 do_div(nr_of_cycles, cycle_time);
1169                 new_base_time += cycle_time * (nr_of_cycles + 1);
1170         }
1171
1172         *new_base_ts = ktime_to_timespec64(new_base_time);
1173 }
1174
1175 static u32 vsc9959_tas_read_cfg_status(struct ocelot *ocelot)
1176 {
1177         return ocelot_read(ocelot, QSYS_TAS_PARAM_CFG_CTRL);
1178 }
1179
1180 static void vsc9959_tas_gcl_set(struct ocelot *ocelot, const u32 gcl_ix,
1181                                 struct tc_taprio_sched_entry *entry)
1182 {
1183         ocelot_write(ocelot,
1184                      QSYS_GCL_CFG_REG_1_GCL_ENTRY_NUM(gcl_ix) |
1185                      QSYS_GCL_CFG_REG_1_GATE_STATE(entry->gate_mask),
1186                      QSYS_GCL_CFG_REG_1);
1187         ocelot_write(ocelot, entry->interval, QSYS_GCL_CFG_REG_2);
1188 }
1189
1190 static int vsc9959_qos_port_tas_set(struct ocelot *ocelot, int port,
1191                                     struct tc_taprio_qopt_offload *taprio)
1192 {
1193         struct timespec64 base_ts;
1194         int ret, i;
1195         u32 val;
1196
1197         if (!taprio->enable) {
1198                 ocelot_rmw_rix(ocelot,
1199                                QSYS_TAG_CONFIG_INIT_GATE_STATE(0xFF),
1200                                QSYS_TAG_CONFIG_ENABLE |
1201                                QSYS_TAG_CONFIG_INIT_GATE_STATE_M,
1202                                QSYS_TAG_CONFIG, port);
1203
1204                 return 0;
1205         }
1206
1207         if (taprio->cycle_time > NSEC_PER_SEC ||
1208             taprio->cycle_time_extension >= NSEC_PER_SEC)
1209                 return -EINVAL;
1210
1211         if (taprio->num_entries > VSC9959_TAS_GCL_ENTRY_MAX)
1212                 return -ERANGE;
1213
1214         ocelot_rmw(ocelot, QSYS_TAS_PARAM_CFG_CTRL_PORT_NUM(port) |
1215                    QSYS_TAS_PARAM_CFG_CTRL_ALWAYS_GUARD_BAND_SCH_Q,
1216                    QSYS_TAS_PARAM_CFG_CTRL_PORT_NUM_M |
1217                    QSYS_TAS_PARAM_CFG_CTRL_ALWAYS_GUARD_BAND_SCH_Q,
1218                    QSYS_TAS_PARAM_CFG_CTRL);
1219
1220         /* Hardware errata -  Admin config could not be overwritten if
1221          * config is pending, need reset the TAS module
1222          */
1223         val = ocelot_read(ocelot, QSYS_PARAM_STATUS_REG_8);
1224         if (val & QSYS_PARAM_STATUS_REG_8_CONFIG_PENDING)
1225                 return  -EBUSY;
1226
1227         ocelot_rmw_rix(ocelot,
1228                        QSYS_TAG_CONFIG_ENABLE |
1229                        QSYS_TAG_CONFIG_INIT_GATE_STATE(0xFF) |
1230                        QSYS_TAG_CONFIG_SCH_TRAFFIC_QUEUES(0xFF),
1231                        QSYS_TAG_CONFIG_ENABLE |
1232                        QSYS_TAG_CONFIG_INIT_GATE_STATE_M |
1233                        QSYS_TAG_CONFIG_SCH_TRAFFIC_QUEUES_M,
1234                        QSYS_TAG_CONFIG, port);
1235
1236         vsc9959_new_base_time(ocelot, taprio->base_time,
1237                               taprio->cycle_time, &base_ts);
1238         ocelot_write(ocelot, base_ts.tv_nsec, QSYS_PARAM_CFG_REG_1);
1239         ocelot_write(ocelot, lower_32_bits(base_ts.tv_sec), QSYS_PARAM_CFG_REG_2);
1240         val = upper_32_bits(base_ts.tv_sec);
1241         ocelot_write(ocelot,
1242                      QSYS_PARAM_CFG_REG_3_BASE_TIME_SEC_MSB(val) |
1243                      QSYS_PARAM_CFG_REG_3_LIST_LENGTH(taprio->num_entries),
1244                      QSYS_PARAM_CFG_REG_3);
1245         ocelot_write(ocelot, taprio->cycle_time, QSYS_PARAM_CFG_REG_4);
1246         ocelot_write(ocelot, taprio->cycle_time_extension, QSYS_PARAM_CFG_REG_5);
1247
1248         for (i = 0; i < taprio->num_entries; i++)
1249                 vsc9959_tas_gcl_set(ocelot, i, &taprio->entries[i]);
1250
1251         ocelot_rmw(ocelot, QSYS_TAS_PARAM_CFG_CTRL_CONFIG_CHANGE,
1252                    QSYS_TAS_PARAM_CFG_CTRL_CONFIG_CHANGE,
1253                    QSYS_TAS_PARAM_CFG_CTRL);
1254
1255         ret = readx_poll_timeout(vsc9959_tas_read_cfg_status, ocelot, val,
1256                                  !(val & QSYS_TAS_PARAM_CFG_CTRL_CONFIG_CHANGE),
1257                                  10, 100000);
1258
1259         return ret;
1260 }
1261
1262 static int vsc9959_qos_port_cbs_set(struct dsa_switch *ds, int port,
1263                                     struct tc_cbs_qopt_offload *cbs_qopt)
1264 {
1265         struct ocelot *ocelot = ds->priv;
1266         int port_ix = port * 8 + cbs_qopt->queue;
1267         u32 rate, burst;
1268
1269         if (cbs_qopt->queue >= ds->num_tx_queues)
1270                 return -EINVAL;
1271
1272         if (!cbs_qopt->enable) {
1273                 ocelot_write_gix(ocelot, QSYS_CIR_CFG_CIR_RATE(0) |
1274                                  QSYS_CIR_CFG_CIR_BURST(0),
1275                                  QSYS_CIR_CFG, port_ix);
1276
1277                 ocelot_rmw_gix(ocelot, 0, QSYS_SE_CFG_SE_AVB_ENA,
1278                                QSYS_SE_CFG, port_ix);
1279
1280                 return 0;
1281         }
1282
1283         /* Rate unit is 100 kbps */
1284         rate = DIV_ROUND_UP(cbs_qopt->idleslope, 100);
1285         /* Avoid using zero rate */
1286         rate = clamp_t(u32, rate, 1, GENMASK(14, 0));
1287         /* Burst unit is 4kB */
1288         burst = DIV_ROUND_UP(cbs_qopt->hicredit, 4096);
1289         /* Avoid using zero burst size */
1290         burst = clamp_t(u32, burst, 1, GENMASK(5, 0));
1291         ocelot_write_gix(ocelot,
1292                          QSYS_CIR_CFG_CIR_RATE(rate) |
1293                          QSYS_CIR_CFG_CIR_BURST(burst),
1294                          QSYS_CIR_CFG,
1295                          port_ix);
1296
1297         ocelot_rmw_gix(ocelot,
1298                        QSYS_SE_CFG_SE_FRM_MODE(0) |
1299                        QSYS_SE_CFG_SE_AVB_ENA,
1300                        QSYS_SE_CFG_SE_AVB_ENA |
1301                        QSYS_SE_CFG_SE_FRM_MODE_M,
1302                        QSYS_SE_CFG,
1303                        port_ix);
1304
1305         return 0;
1306 }
1307
1308 static int vsc9959_port_setup_tc(struct dsa_switch *ds, int port,
1309                                  enum tc_setup_type type,
1310                                  void *type_data)
1311 {
1312         struct ocelot *ocelot = ds->priv;
1313
1314         switch (type) {
1315         case TC_SETUP_QDISC_TAPRIO:
1316                 return vsc9959_qos_port_tas_set(ocelot, port, type_data);
1317         case TC_SETUP_QDISC_CBS:
1318                 return vsc9959_qos_port_cbs_set(ds, port, type_data);
1319         default:
1320                 return -EOPNOTSUPP;
1321         }
1322 }
1323
1324 static void vsc9959_xmit_template_populate(struct ocelot *ocelot, int port)
1325 {
1326         struct ocelot_port *ocelot_port = ocelot->ports[port];
1327         u8 *template = ocelot_port->xmit_template;
1328         u64 bypass, dest, src;
1329         __be32 *prefix;
1330         u8 *injection;
1331
1332         /* Set the source port as the CPU port module and not the
1333          * NPI port
1334          */
1335         src = ocelot->num_phys_ports;
1336         dest = BIT(port);
1337         bypass = true;
1338
1339         injection = template + OCELOT_SHORT_PREFIX_LEN;
1340         prefix = (__be32 *)template;
1341
1342         packing(injection, &bypass, 127, 127, OCELOT_TAG_LEN, PACK, 0);
1343         packing(injection, &dest,    68,  56, OCELOT_TAG_LEN, PACK, 0);
1344         packing(injection, &src,     46,  43, OCELOT_TAG_LEN, PACK, 0);
1345
1346         *prefix = cpu_to_be32(0x8880000a);
1347 }
1348
1349 static const struct felix_info felix_info_vsc9959 = {
1350         .target_io_res          = vsc9959_target_io_res,
1351         .port_io_res            = vsc9959_port_io_res,
1352         .imdio_res              = &vsc9959_imdio_res,
1353         .regfields              = vsc9959_regfields,
1354         .map                    = vsc9959_regmap,
1355         .ops                    = &vsc9959_ops,
1356         .stats_layout           = vsc9959_stats_layout,
1357         .num_stats              = ARRAY_SIZE(vsc9959_stats_layout),
1358         .vcap                   = vsc9959_vcap_props,
1359         .shared_queue_sz        = 128 * 1024,
1360         .num_mact_rows          = 2048,
1361         .num_ports              = 6,
1362         .num_tx_queues          = FELIX_NUM_TC,
1363         .switch_pci_bar         = 4,
1364         .imdio_pci_bar          = 0,
1365         .ptp_caps               = &vsc9959_ptp_caps,
1366         .mdio_bus_alloc         = vsc9959_mdio_bus_alloc,
1367         .mdio_bus_free          = vsc9959_mdio_bus_free,
1368         .phylink_validate       = vsc9959_phylink_validate,
1369         .prevalidate_phy_mode   = vsc9959_prevalidate_phy_mode,
1370         .port_setup_tc          = vsc9959_port_setup_tc,
1371         .port_sched_speed_set   = vsc9959_sched_speed_set,
1372         .xmit_template_populate = vsc9959_xmit_template_populate,
1373 };
1374
1375 static irqreturn_t felix_irq_handler(int irq, void *data)
1376 {
1377         struct ocelot *ocelot = (struct ocelot *)data;
1378
1379         /* The INTB interrupt is used for both PTP TX timestamp interrupt
1380          * and preemption status change interrupt on each port.
1381          *
1382          * - Get txtstamp if have
1383          * - TODO: handle preemption. Without handling it, driver may get
1384          *   interrupt storm.
1385          */
1386
1387         ocelot_get_txtstamp(ocelot);
1388
1389         return IRQ_HANDLED;
1390 }
1391
1392 static int felix_pci_probe(struct pci_dev *pdev,
1393                            const struct pci_device_id *id)
1394 {
1395         struct dsa_switch *ds;
1396         struct ocelot *ocelot;
1397         struct felix *felix;
1398         int err;
1399
1400         if (pdev->dev.of_node && !of_device_is_available(pdev->dev.of_node)) {
1401                 dev_info(&pdev->dev, "device is disabled, skipping\n");
1402                 return -ENODEV;
1403         }
1404
1405         err = pci_enable_device(pdev);
1406         if (err) {
1407                 dev_err(&pdev->dev, "device enable failed\n");
1408                 goto err_pci_enable;
1409         }
1410
1411         /* set up for high or low dma */
1412         err = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64));
1413         if (err) {
1414                 err = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32));
1415                 if (err) {
1416                         dev_err(&pdev->dev,
1417                                 "DMA configuration failed: 0x%x\n", err);
1418                         goto err_dma;
1419                 }
1420         }
1421
1422         felix = kzalloc(sizeof(struct felix), GFP_KERNEL);
1423         if (!felix) {
1424                 err = -ENOMEM;
1425                 dev_err(&pdev->dev, "Failed to allocate driver memory\n");
1426                 goto err_alloc_felix;
1427         }
1428
1429         pci_set_drvdata(pdev, felix);
1430         ocelot = &felix->ocelot;
1431         ocelot->dev = &pdev->dev;
1432         ocelot->num_flooding_pgids = FELIX_NUM_TC;
1433         felix->info = &felix_info_vsc9959;
1434         felix->switch_base = pci_resource_start(pdev,
1435                                                 felix->info->switch_pci_bar);
1436         felix->imdio_base = pci_resource_start(pdev,
1437                                                felix->info->imdio_pci_bar);
1438
1439         pci_set_master(pdev);
1440
1441         err = devm_request_threaded_irq(&pdev->dev, pdev->irq, NULL,
1442                                         &felix_irq_handler, IRQF_ONESHOT,
1443                                         "felix-intb", ocelot);
1444         if (err) {
1445                 dev_err(&pdev->dev, "Failed to request irq\n");
1446                 goto err_alloc_irq;
1447         }
1448
1449         ocelot->ptp = 1;
1450
1451         ds = kzalloc(sizeof(struct dsa_switch), GFP_KERNEL);
1452         if (!ds) {
1453                 err = -ENOMEM;
1454                 dev_err(&pdev->dev, "Failed to allocate DSA switch\n");
1455                 goto err_alloc_ds;
1456         }
1457
1458         ds->dev = &pdev->dev;
1459         ds->num_ports = felix->info->num_ports;
1460         ds->num_tx_queues = felix->info->num_tx_queues;
1461         ds->ops = &felix_switch_ops;
1462         ds->priv = ocelot;
1463         felix->ds = ds;
1464
1465         err = dsa_register_switch(ds);
1466         if (err) {
1467                 dev_err(&pdev->dev, "Failed to register DSA switch: %d\n", err);
1468                 goto err_register_ds;
1469         }
1470
1471         return 0;
1472
1473 err_register_ds:
1474         kfree(ds);
1475 err_alloc_ds:
1476 err_alloc_irq:
1477 err_alloc_felix:
1478         kfree(felix);
1479 err_dma:
1480         pci_disable_device(pdev);
1481 err_pci_enable:
1482         return err;
1483 }
1484
1485 static void felix_pci_remove(struct pci_dev *pdev)
1486 {
1487         struct felix *felix;
1488
1489         felix = pci_get_drvdata(pdev);
1490
1491         dsa_unregister_switch(felix->ds);
1492
1493         kfree(felix->ds);
1494         kfree(felix);
1495
1496         pci_disable_device(pdev);
1497 }
1498
1499 static struct pci_device_id felix_ids[] = {
1500         {
1501                 /* NXP LS1028A */
1502                 PCI_DEVICE(PCI_VENDOR_ID_FREESCALE, 0xEEF0),
1503         },
1504         { 0, }
1505 };
1506 MODULE_DEVICE_TABLE(pci, felix_ids);
1507
1508 static struct pci_driver felix_vsc9959_pci_driver = {
1509         .name           = "mscc_felix",
1510         .id_table       = felix_ids,
1511         .probe          = felix_pci_probe,
1512         .remove         = felix_pci_remove,
1513 };
1514 module_pci_driver(felix_vsc9959_pci_driver);
1515
1516 MODULE_DESCRIPTION("Felix Switch driver");
1517 MODULE_LICENSE("GPL v2");