drivers/net/dsa/ocelot/felix_vsc9959.c

   1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
   2 /* Copyright 2017 Microsemi Corporation
   3  * Copyright 2018-2019 NXP Semiconductors
   4  */
   5 #include <linux/fsl/enetc_mdio.h>
   6 #include <soc/mscc/ocelot_qsys.h>
   7 #include <soc/mscc/ocelot_vcap.h>
   8 #include <soc/mscc/ocelot_ptp.h>
   9 #include <soc/mscc/ocelot_sys.h>
  10 #include <soc/mscc/ocelot.h>
  11 #include <net/pkt_sched.h>
  12 #include <linux/iopoll.h>
  13 #include <linux/pci.h>
  14 #include "felix.h"
  15
  16 #define VSC9959_VCAP_IS2_CNT            1024
  17 #define VSC9959_VCAP_IS2_ENTRY_WIDTH    376
  18 #define VSC9959_VCAP_PORT_CNT           6
  19
  20 /* TODO: should find a better place for these */
  21 #define USXGMII_BMCR_RESET              BIT(15)
  22 #define USXGMII_BMCR_AN_EN              BIT(12)
  23 #define USXGMII_BMCR_RST_AN             BIT(9)
  24 #define USXGMII_BMSR_LNKS(status)       (((status) & GENMASK(2, 2)) >> 2)
  25 #define USXGMII_BMSR_AN_CMPL(status)    (((status) & GENMASK(5, 5)) >> 5)
  26 #define USXGMII_ADVERTISE_LNKS(x)       (((x) << 15) & BIT(15))
  27 #define USXGMII_ADVERTISE_FDX           BIT(12)
  28 #define USXGMII_ADVERTISE_SPEED(x)      (((x) << 9) & GENMASK(11, 9))
  29 #define USXGMII_LPA_LNKS(lpa)           ((lpa) >> 15)
  30 #define USXGMII_LPA_DUPLEX(lpa)         (((lpa) & GENMASK(12, 12)) >> 12)
  31 #define USXGMII_LPA_SPEED(lpa)          (((lpa) & GENMASK(11, 9)) >> 9)
  32
  33 #define VSC9959_TAS_GCL_ENTRY_MAX       63
  34
  35 enum usxgmii_speed {
  36         USXGMII_SPEED_10        = 0,
  37         USXGMII_SPEED_100       = 1,
  38         USXGMII_SPEED_1000      = 2,
  39         USXGMII_SPEED_2500      = 4,
  40 };
  41
  42 static const u32 vsc9959_ana_regmap[] = {
  43         REG(ANA_ADVLEARN,                       0x0089a0),
  44         REG(ANA_VLANMASK,                       0x0089a4),
  45         REG_RESERVED(ANA_PORT_B_DOMAIN),
  46         REG(ANA_ANAGEFIL,                       0x0089ac),
  47         REG(ANA_ANEVENTS,                       0x0089b0),
  48         REG(ANA_STORMLIMIT_BURST,               0x0089b4),
  49         REG(ANA_STORMLIMIT_CFG,                 0x0089b8),
  50         REG(ANA_ISOLATED_PORTS,                 0x0089c8),
  51         REG(ANA_COMMUNITY_PORTS,                0x0089cc),
  52         REG(ANA_AUTOAGE,                        0x0089d0),
  53         REG(ANA_MACTOPTIONS,                    0x0089d4),
  54         REG(ANA_LEARNDISC,                      0x0089d8),
  55         REG(ANA_AGENCTRL,                       0x0089dc),
  56         REG(ANA_MIRRORPORTS,                    0x0089e0),
  57         REG(ANA_EMIRRORPORTS,                   0x0089e4),
  58         REG(ANA_FLOODING,                       0x0089e8),
  59         REG(ANA_FLOODING_IPMC,                  0x008a08),
  60         REG(ANA_SFLOW_CFG,                      0x008a0c),
  61         REG(ANA_PORT_MODE,                      0x008a28),
  62         REG(ANA_CUT_THRU_CFG,                   0x008a48),
  63         REG(ANA_PGID_PGID,                      0x008400),
  64         REG(ANA_TABLES_ANMOVED,                 0x007f1c),
  65         REG(ANA_TABLES_MACHDATA,                0x007f20),
  66         REG(ANA_TABLES_MACLDATA,                0x007f24),
  67         REG(ANA_TABLES_STREAMDATA,              0x007f28),
  68         REG(ANA_TABLES_MACACCESS,               0x007f2c),
  69         REG(ANA_TABLES_MACTINDX,                0x007f30),
  70         REG(ANA_TABLES_VLANACCESS,              0x007f34),
  71         REG(ANA_TABLES_VLANTIDX,                0x007f38),
  72         REG(ANA_TABLES_ISDXACCESS,              0x007f3c),
  73         REG(ANA_TABLES_ISDXTIDX,                0x007f40),
  74         REG(ANA_TABLES_ENTRYLIM,                0x007f00),
  75         REG(ANA_TABLES_PTP_ID_HIGH,             0x007f44),
  76         REG(ANA_TABLES_PTP_ID_LOW,              0x007f48),
  77         REG(ANA_TABLES_STREAMACCESS,            0x007f4c),
  78         REG(ANA_TABLES_STREAMTIDX,              0x007f50),
  79         REG(ANA_TABLES_SEQ_HISTORY,             0x007f54),
  80         REG(ANA_TABLES_SEQ_MASK,                0x007f58),
  81         REG(ANA_TABLES_SFID_MASK,               0x007f5c),
  82         REG(ANA_TABLES_SFIDACCESS,              0x007f60),
  83         REG(ANA_TABLES_SFIDTIDX,                0x007f64),
  84         REG(ANA_MSTI_STATE,                     0x008600),
  85         REG(ANA_OAM_UPM_LM_CNT,                 0x008000),
  86         REG(ANA_SG_ACCESS_CTRL,                 0x008a64),
  87         REG(ANA_SG_CONFIG_REG_1,                0x007fb0),
  88         REG(ANA_SG_CONFIG_REG_2,                0x007fb4),
  89         REG(ANA_SG_CONFIG_REG_3,                0x007fb8),
  90         REG(ANA_SG_CONFIG_REG_4,                0x007fbc),
  91         REG(ANA_SG_CONFIG_REG_5,                0x007fc0),
  92         REG(ANA_SG_GCL_GS_CONFIG,               0x007f80),
  93         REG(ANA_SG_GCL_TI_CONFIG,               0x007f90),
  94         REG(ANA_SG_STATUS_REG_1,                0x008980),
  95         REG(ANA_SG_STATUS_REG_2,                0x008984),
  96         REG(ANA_SG_STATUS_REG_3,                0x008988),
  97         REG(ANA_PORT_VLAN_CFG,                  0x007800),
  98         REG(ANA_PORT_DROP_CFG,                  0x007804),
  99         REG(ANA_PORT_QOS_CFG,                   0x007808),
 100         REG(ANA_PORT_VCAP_CFG,                  0x00780c),
 101         REG(ANA_PORT_VCAP_S1_KEY_CFG,           0x007810),
 102         REG(ANA_PORT_VCAP_S2_CFG,               0x00781c),
 103         REG(ANA_PORT_PCP_DEI_MAP,               0x007820),
 104         REG(ANA_PORT_CPU_FWD_CFG,               0x007860),
 105         REG(ANA_PORT_CPU_FWD_BPDU_CFG,          0x007864),
 106         REG(ANA_PORT_CPU_FWD_GARP_CFG,          0x007868),
 107         REG(ANA_PORT_CPU_FWD_CCM_CFG,           0x00786c),
 108         REG(ANA_PORT_PORT_CFG,                  0x007870),
 109         REG(ANA_PORT_POL_CFG,                   0x007874),
 110         REG(ANA_PORT_PTP_CFG,                   0x007878),
 111         REG(ANA_PORT_PTP_DLY1_CFG,              0x00787c),
 112         REG(ANA_PORT_PTP_DLY2_CFG,              0x007880),
 113         REG(ANA_PORT_SFID_CFG,                  0x007884),
 114         REG(ANA_PFC_PFC_CFG,                    0x008800),
 115         REG_RESERVED(ANA_PFC_PFC_TIMER),
 116         REG_RESERVED(ANA_IPT_OAM_MEP_CFG),
 117         REG_RESERVED(ANA_IPT_IPT),
 118         REG_RESERVED(ANA_PPT_PPT),
 119         REG_RESERVED(ANA_FID_MAP_FID_MAP),
 120         REG(ANA_AGGR_CFG,                       0x008a68),
 121         REG(ANA_CPUQ_CFG,                       0x008a6c),
 122         REG_RESERVED(ANA_CPUQ_CFG2),
 123         REG(ANA_CPUQ_8021_CFG,                  0x008a74),
 124         REG(ANA_DSCP_CFG,                       0x008ab4),
 125         REG(ANA_DSCP_REWR_CFG,                  0x008bb4),
 126         REG(ANA_VCAP_RNG_TYPE_CFG,              0x008bf4),
 127         REG(ANA_VCAP_RNG_VAL_CFG,               0x008c14),
 128         REG_RESERVED(ANA_VRAP_CFG),
 129         REG_RESERVED(ANA_VRAP_HDR_DATA),
 130         REG_RESERVED(ANA_VRAP_HDR_MASK),
 131         REG(ANA_DISCARD_CFG,                    0x008c40),
 132         REG(ANA_FID_CFG,                        0x008c44),
 133         REG(ANA_POL_PIR_CFG,                    0x004000),
 134         REG(ANA_POL_CIR_CFG,                    0x004004),
 135         REG(ANA_POL_MODE_CFG,                   0x004008),
 136         REG(ANA_POL_PIR_STATE,                  0x00400c),
 137         REG(ANA_POL_CIR_STATE,                  0x004010),
 138         REG_RESERVED(ANA_POL_STATE),
 139         REG(ANA_POL_FLOWC,                      0x008c48),
 140         REG(ANA_POL_HYST,                       0x008cb4),
 141         REG_RESERVED(ANA_POL_MISC_CFG),
 142 };
 143
 144 static const u32 vsc9959_qs_regmap[] = {
 145         REG(QS_XTR_GRP_CFG,                     0x000000),
 146         REG(QS_XTR_RD,                          0x000008),
 147         REG(QS_XTR_FRM_PRUNING,                 0x000010),
 148         REG(QS_XTR_FLUSH,                       0x000018),
 149         REG(QS_XTR_DATA_PRESENT,                0x00001c),
 150         REG(QS_XTR_CFG,                         0x000020),
 151         REG(QS_INJ_GRP_CFG,                     0x000024),
 152         REG(QS_INJ_WR,                          0x00002c),
 153         REG(QS_INJ_CTRL,                        0x000034),
 154         REG(QS_INJ_STATUS,                      0x00003c),
 155         REG(QS_INJ_ERR,                         0x000040),
 156         REG_RESERVED(QS_INH_DBG),
 157 };
 158
 159 static const u32 vsc9959_s2_regmap[] = {
 160         REG(S2_CORE_UPDATE_CTRL,                0x000000),
 161         REG(S2_CORE_MV_CFG,                     0x000004),
 162         REG(S2_CACHE_ENTRY_DAT,                 0x000008),
 163         REG(S2_CACHE_MASK_DAT,                  0x000108),
 164         REG(S2_CACHE_ACTION_DAT,                0x000208),
 165         REG(S2_CACHE_CNT_DAT,                   0x000308),
 166         REG(S2_CACHE_TG_DAT,                    0x000388),
 167 };
 168
 169 static const u32 vsc9959_qsys_regmap[] = {
 170         REG(QSYS_PORT_MODE,                     0x00f460),
 171         REG(QSYS_SWITCH_PORT_MODE,              0x00f480),
 172         REG(QSYS_STAT_CNT_CFG,                  0x00f49c),
 173         REG(QSYS_EEE_CFG,                       0x00f4a0),
 174         REG(QSYS_EEE_THRES,                     0x00f4b8),
 175         REG(QSYS_IGR_NO_SHARING,                0x00f4bc),
 176         REG(QSYS_EGR_NO_SHARING,                0x00f4c0),
 177         REG(QSYS_SW_STATUS,                     0x00f4c4),
 178         REG(QSYS_EXT_CPU_CFG,                   0x00f4e0),
 179         REG_RESERVED(QSYS_PAD_CFG),
 180         REG(QSYS_CPU_GROUP_MAP,                 0x00f4e8),
 181         REG_RESERVED(QSYS_QMAP),
 182         REG_RESERVED(QSYS_ISDX_SGRP),
 183         REG_RESERVED(QSYS_TIMED_FRAME_ENTRY),
 184         REG(QSYS_TFRM_MISC,                     0x00f50c),
 185         REG(QSYS_TFRM_PORT_DLY,                 0x00f510),
 186         REG(QSYS_TFRM_TIMER_CFG_1,              0x00f514),
 187         REG(QSYS_TFRM_TIMER_CFG_2,              0x00f518),
 188         REG(QSYS_TFRM_TIMER_CFG_3,              0x00f51c),
 189         REG(QSYS_TFRM_TIMER_CFG_4,              0x00f520),
 190         REG(QSYS_TFRM_TIMER_CFG_5,              0x00f524),
 191         REG(QSYS_TFRM_TIMER_CFG_6,              0x00f528),
 192         REG(QSYS_TFRM_TIMER_CFG_7,              0x00f52c),
 193         REG(QSYS_TFRM_TIMER_CFG_8,              0x00f530),
 194         REG(QSYS_RED_PROFILE,                   0x00f534),
 195         REG(QSYS_RES_QOS_MODE,                  0x00f574),
 196         REG(QSYS_RES_CFG,                       0x00c000),
 197         REG(QSYS_RES_STAT,                      0x00c004),
 198         REG(QSYS_EGR_DROP_MODE,                 0x00f578),
 199         REG(QSYS_EQ_CTRL,                       0x00f57c),
 200         REG_RESERVED(QSYS_EVENTS_CORE),
 201         REG(QSYS_QMAXSDU_CFG_0,                 0x00f584),
 202         REG(QSYS_QMAXSDU_CFG_1,                 0x00f5a0),
 203         REG(QSYS_QMAXSDU_CFG_2,                 0x00f5bc),
 204         REG(QSYS_QMAXSDU_CFG_3,                 0x00f5d8),
 205         REG(QSYS_QMAXSDU_CFG_4,                 0x00f5f4),
 206         REG(QSYS_QMAXSDU_CFG_5,                 0x00f610),
 207         REG(QSYS_QMAXSDU_CFG_6,                 0x00f62c),
 208         REG(QSYS_QMAXSDU_CFG_7,                 0x00f648),
 209         REG(QSYS_PREEMPTION_CFG,                0x00f664),
 210         REG(QSYS_CIR_CFG,                       0x000000),
 211         REG(QSYS_EIR_CFG,                       0x000004),
 212         REG(QSYS_SE_CFG,                        0x000008),
 213         REG(QSYS_SE_DWRR_CFG,                   0x00000c),
 214         REG_RESERVED(QSYS_SE_CONNECT),
 215         REG(QSYS_SE_DLB_SENSE,                  0x000040),
 216         REG(QSYS_CIR_STATE,                     0x000044),
 217         REG(QSYS_EIR_STATE,                     0x000048),
 218         REG_RESERVED(QSYS_SE_STATE),
 219         REG(QSYS_HSCH_MISC_CFG,                 0x00f67c),
 220         REG(QSYS_TAG_CONFIG,                    0x00f680),
 221         REG(QSYS_TAS_PARAM_CFG_CTRL,            0x00f698),
 222         REG(QSYS_PORT_MAX_SDU,                  0x00f69c),
 223         REG(QSYS_PARAM_CFG_REG_1,               0x00f440),
 224         REG(QSYS_PARAM_CFG_REG_2,               0x00f444),
 225         REG(QSYS_PARAM_CFG_REG_3,               0x00f448),
 226         REG(QSYS_PARAM_CFG_REG_4,               0x00f44c),
 227         REG(QSYS_PARAM_CFG_REG_5,               0x00f450),
 228         REG(QSYS_GCL_CFG_REG_1,                 0x00f454),
 229         REG(QSYS_GCL_CFG_REG_2,                 0x00f458),
 230         REG(QSYS_PARAM_STATUS_REG_1,            0x00f400),
 231         REG(QSYS_PARAM_STATUS_REG_2,            0x00f404),
 232         REG(QSYS_PARAM_STATUS_REG_3,            0x00f408),
 233         REG(QSYS_PARAM_STATUS_REG_4,            0x00f40c),
 234         REG(QSYS_PARAM_STATUS_REG_5,            0x00f410),
 235         REG(QSYS_PARAM_STATUS_REG_6,            0x00f414),
 236         REG(QSYS_PARAM_STATUS_REG_7,            0x00f418),
 237         REG(QSYS_PARAM_STATUS_REG_8,            0x00f41c),
 238         REG(QSYS_PARAM_STATUS_REG_9,            0x00f420),
 239         REG(QSYS_GCL_STATUS_REG_1,              0x00f424),
 240         REG(QSYS_GCL_STATUS_REG_2,              0x00f428),
 241 };
 242
 243 static const u32 vsc9959_rew_regmap[] = {
 244         REG(REW_PORT_VLAN_CFG,                  0x000000),
 245         REG(REW_TAG_CFG,                        0x000004),
 246         REG(REW_PORT_CFG,                       0x000008),
 247         REG(REW_DSCP_CFG,                       0x00000c),
 248         REG(REW_PCP_DEI_QOS_MAP_CFG,            0x000010),
 249         REG(REW_PTP_CFG,                        0x000050),
 250         REG(REW_PTP_DLY1_CFG,                   0x000054),
 251         REG(REW_RED_TAG_CFG,                    0x000058),
 252         REG(REW_DSCP_REMAP_DP1_CFG,             0x000410),
 253         REG(REW_DSCP_REMAP_CFG,                 0x000510),
 254         REG_RESERVED(REW_STAT_CFG),
 255         REG_RESERVED(REW_REW_STICKY),
 256         REG_RESERVED(REW_PPT),
 257 };
 258
 259 static const u32 vsc9959_sys_regmap[] = {
 260         REG(SYS_COUNT_RX_OCTETS,                0x000000),
 261         REG(SYS_COUNT_RX_MULTICAST,             0x000008),
 262         REG(SYS_COUNT_RX_SHORTS,                0x000010),
 263         REG(SYS_COUNT_RX_FRAGMENTS,             0x000014),
 264         REG(SYS_COUNT_RX_JABBERS,               0x000018),
 265         REG(SYS_COUNT_RX_64,                    0x000024),
 266         REG(SYS_COUNT_RX_65_127,                0x000028),
 267         REG(SYS_COUNT_RX_128_255,               0x00002c),
 268         REG(SYS_COUNT_RX_256_1023,              0x000030),
 269         REG(SYS_COUNT_RX_1024_1526,             0x000034),
 270         REG(SYS_COUNT_RX_1527_MAX,              0x000038),
 271         REG(SYS_COUNT_RX_LONGS,                 0x000044),
 272         REG(SYS_COUNT_TX_OCTETS,                0x000200),
 273         REG(SYS_COUNT_TX_COLLISION,             0x000210),
 274         REG(SYS_COUNT_TX_DROPS,                 0x000214),
 275         REG(SYS_COUNT_TX_64,                    0x00021c),
 276         REG(SYS_COUNT_TX_65_127,                0x000220),
 277         REG(SYS_COUNT_TX_128_511,               0x000224),
 278         REG(SYS_COUNT_TX_512_1023,              0x000228),
 279         REG(SYS_COUNT_TX_1024_1526,             0x00022c),
 280         REG(SYS_COUNT_TX_1527_MAX,              0x000230),
 281         REG(SYS_COUNT_TX_AGING,                 0x000278),
 282         REG(SYS_RESET_CFG,                      0x000e00),
 283         REG(SYS_SR_ETYPE_CFG,                   0x000e04),
 284         REG(SYS_VLAN_ETYPE_CFG,                 0x000e08),
 285         REG(SYS_PORT_MODE,                      0x000e0c),
 286         REG(SYS_FRONT_PORT_MODE,                0x000e2c),
 287         REG(SYS_FRM_AGING,                      0x000e44),
 288         REG(SYS_STAT_CFG,                       0x000e48),
 289         REG(SYS_SW_STATUS,                      0x000e4c),
 290         REG_RESERVED(SYS_MISC_CFG),
 291         REG(SYS_REW_MAC_HIGH_CFG,               0x000e6c),
 292         REG(SYS_REW_MAC_LOW_CFG,                0x000e84),
 293         REG(SYS_TIMESTAMP_OFFSET,               0x000e9c),
 294         REG(SYS_PAUSE_CFG,                      0x000ea0),
 295         REG(SYS_PAUSE_TOT_CFG,                  0x000ebc),
 296         REG(SYS_ATOP,                           0x000ec0),
 297         REG(SYS_ATOP_TOT_CFG,                   0x000edc),
 298         REG(SYS_MAC_FC_CFG,                     0x000ee0),
 299         REG(SYS_MMGT,                           0x000ef8),
 300         REG_RESERVED(SYS_MMGT_FAST),
 301         REG_RESERVED(SYS_EVENTS_DIF),
 302         REG_RESERVED(SYS_EVENTS_CORE),
 303         REG_RESERVED(SYS_CNT),
 304         REG(SYS_PTP_STATUS,                     0x000f14),
 305         REG(SYS_PTP_TXSTAMP,                    0x000f18),
 306         REG(SYS_PTP_NXT,                        0x000f1c),
 307         REG(SYS_PTP_CFG,                        0x000f20),
 308         REG(SYS_RAM_INIT,                       0x000f24),
 309         REG_RESERVED(SYS_CM_ADDR),
 310         REG_RESERVED(SYS_CM_DATA_WR),
 311         REG_RESERVED(SYS_CM_DATA_RD),
 312         REG_RESERVED(SYS_CM_OP),
 313         REG_RESERVED(SYS_CM_DATA),
 314 };
 315
 316 static const u32 vsc9959_ptp_regmap[] = {
 317         REG(PTP_PIN_CFG,                   0x000000),
 318         REG(PTP_PIN_TOD_SEC_MSB,           0x000004),
 319         REG(PTP_PIN_TOD_SEC_LSB,           0x000008),
 320         REG(PTP_PIN_TOD_NSEC,              0x00000c),
 321         REG(PTP_PIN_WF_HIGH_PERIOD,        0x000014),
 322         REG(PTP_PIN_WF_LOW_PERIOD,         0x000018),
 323         REG(PTP_CFG_MISC,                  0x0000a0),
 324         REG(PTP_CLK_CFG_ADJ_CFG,           0x0000a4),
 325         REG(PTP_CLK_CFG_ADJ_FREQ,          0x0000a8),
 326 };
 327
 328 static const u32 vsc9959_gcb_regmap[] = {
 329         REG(GCB_SOFT_RST,                       0x000004),
 330 };
 331
 332 static const u32 *vsc9959_regmap[] = {
 333         [ANA]   = vsc9959_ana_regmap,
 334         [QS]    = vsc9959_qs_regmap,
 335         [QSYS]  = vsc9959_qsys_regmap,
 336         [REW]   = vsc9959_rew_regmap,
 337         [SYS]   = vsc9959_sys_regmap,
 338         [S2]    = vsc9959_s2_regmap,
 339         [PTP]   = vsc9959_ptp_regmap,
 340         [GCB]   = vsc9959_gcb_regmap,
 341 };
 342
 343 /* Addresses are relative to the PCI device's base address */
 344 static const struct resource vsc9959_target_io_res[] = {
 345         [ANA] = {
 346                 .start  = 0x0280000,
 347                 .end    = 0x028ffff,
 348                 .name   = "ana",
 349         },
 350         [QS] = {
 351                 .start  = 0x0080000,
 352                 .end    = 0x00800ff,
 353                 .name   = "qs",
 354         },
 355         [QSYS] = {
 356                 .start  = 0x0200000,
 357                 .end    = 0x021ffff,
 358                 .name   = "qsys",
 359         },
 360         [REW] = {
 361                 .start  = 0x0030000,
 362                 .end    = 0x003ffff,
 363                 .name   = "rew",
 364         },
 365         [SYS] = {
 366                 .start  = 0x0010000,
 367                 .end    = 0x001ffff,
 368                 .name   = "sys",
 369         },
 370         [S2] = {
 371                 .start  = 0x0060000,
 372                 .end    = 0x00603ff,
 373                 .name   = "s2",
 374         },
 375         [PTP] = {
 376                 .start  = 0x0090000,
 377                 .end    = 0x00900cb,
 378                 .name   = "ptp",
 379         },
 380         [GCB] = {
 381                 .start  = 0x0070000,
 382                 .end    = 0x00701ff,
 383                 .name   = "devcpu_gcb",
 384         },
 385 };
 386
 387 static const struct resource vsc9959_port_io_res[] = {
 388         {
 389                 .start  = 0x0100000,
 390                 .end    = 0x010ffff,
 391                 .name   = "port0",
 392         },
 393         {
 394                 .start  = 0x0110000,
 395                 .end    = 0x011ffff,
 396                 .name   = "port1",
 397         },
 398         {
 399                 .start  = 0x0120000,
 400                 .end    = 0x012ffff,
 401                 .name   = "port2",
 402         },
 403         {
 404                 .start  = 0x0130000,
 405                 .end    = 0x013ffff,
 406                 .name   = "port3",
 407         },
 408         {
 409                 .start  = 0x0140000,
 410                 .end    = 0x014ffff,
 411                 .name   = "port4",
 412         },
 413         {
 414                 .start  = 0x0150000,
 415                 .end    = 0x015ffff,
 416                 .name   = "port5",
 417         },
 418 };
 419
 420 /* Port MAC 0 Internal MDIO bus through which the SerDes acting as an
 421  * SGMII/QSGMII MAC PCS can be found.
 422  */
 423 static const struct resource vsc9959_imdio_res = {
 424         .start          = 0x8030,
 425         .end            = 0x8040,
 426         .name           = "imdio",
 427 };
 428
 429 static const struct reg_field vsc9959_regfields[] = {
 430         [ANA_ADVLEARN_VLAN_CHK] = REG_FIELD(ANA_ADVLEARN, 6, 6),
 431         [ANA_ADVLEARN_LEARN_MIRROR] = REG_FIELD(ANA_ADVLEARN, 0, 5),
 432         [ANA_ANEVENTS_FLOOD_DISCARD] = REG_FIELD(ANA_ANEVENTS, 30, 30),
 433         [ANA_ANEVENTS_AUTOAGE] = REG_FIELD(ANA_ANEVENTS, 26, 26),
 434         [ANA_ANEVENTS_STORM_DROP] = REG_FIELD(ANA_ANEVENTS, 24, 24),
 435         [ANA_ANEVENTS_LEARN_DROP] = REG_FIELD(ANA_ANEVENTS, 23, 23),
 436         [ANA_ANEVENTS_AGED_ENTRY] = REG_FIELD(ANA_ANEVENTS, 22, 22),
 437         [ANA_ANEVENTS_CPU_LEARN_FAILED] = REG_FIELD(ANA_ANEVENTS, 21, 21),
 438         [ANA_ANEVENTS_AUTO_LEARN_FAILED] = REG_FIELD(ANA_ANEVENTS, 20, 20),
 439         [ANA_ANEVENTS_LEARN_REMOVE] = REG_FIELD(ANA_ANEVENTS, 19, 19),
 440         [ANA_ANEVENTS_AUTO_LEARNED] = REG_FIELD(ANA_ANEVENTS, 18, 18),
 441         [ANA_ANEVENTS_AUTO_MOVED] = REG_FIELD(ANA_ANEVENTS, 17, 17),
 442         [ANA_ANEVENTS_CLASSIFIED_DROP] = REG_FIELD(ANA_ANEVENTS, 15, 15),
 443         [ANA_ANEVENTS_CLASSIFIED_COPY] = REG_FIELD(ANA_ANEVENTS, 14, 14),
 444         [ANA_ANEVENTS_VLAN_DISCARD] = REG_FIELD(ANA_ANEVENTS, 13, 13),
 445         [ANA_ANEVENTS_FWD_DISCARD] = REG_FIELD(ANA_ANEVENTS, 12, 12),
 446         [ANA_ANEVENTS_MULTICAST_FLOOD] = REG_FIELD(ANA_ANEVENTS, 11, 11),
 447         [ANA_ANEVENTS_UNICAST_FLOOD] = REG_FIELD(ANA_ANEVENTS, 10, 10),
 448         [ANA_ANEVENTS_DEST_KNOWN] = REG_FIELD(ANA_ANEVENTS, 9, 9),
 449         [ANA_ANEVENTS_BUCKET3_MATCH] = REG_FIELD(ANA_ANEVENTS, 8, 8),
 450         [ANA_ANEVENTS_BUCKET2_MATCH] = REG_FIELD(ANA_ANEVENTS, 7, 7),
 451         [ANA_ANEVENTS_BUCKET1_MATCH] = REG_FIELD(ANA_ANEVENTS, 6, 6),
 452         [ANA_ANEVENTS_BUCKET0_MATCH] = REG_FIELD(ANA_ANEVENTS, 5, 5),
 453         [ANA_ANEVENTS_CPU_OPERATION] = REG_FIELD(ANA_ANEVENTS, 4, 4),
 454         [ANA_ANEVENTS_DMAC_LOOKUP] = REG_FIELD(ANA_ANEVENTS, 3, 3),
 455         [ANA_ANEVENTS_SMAC_LOOKUP] = REG_FIELD(ANA_ANEVENTS, 2, 2),
 456         [ANA_ANEVENTS_SEQ_GEN_ERR_0] = REG_FIELD(ANA_ANEVENTS, 1, 1),
 457         [ANA_ANEVENTS_SEQ_GEN_ERR_1] = REG_FIELD(ANA_ANEVENTS, 0, 0),
 458         [ANA_TABLES_MACACCESS_B_DOM] = REG_FIELD(ANA_TABLES_MACACCESS, 16, 16),
 459         [ANA_TABLES_MACTINDX_BUCKET] = REG_FIELD(ANA_TABLES_MACTINDX, 11, 12),
 460         [ANA_TABLES_MACTINDX_M_INDEX] = REG_FIELD(ANA_TABLES_MACTINDX, 0, 10),
 461         [SYS_RESET_CFG_CORE_ENA] = REG_FIELD(SYS_RESET_CFG, 0, 0),
 462         [GCB_SOFT_RST_SWC_RST] = REG_FIELD(GCB_SOFT_RST, 0, 0),
 463 };
 464
 465 static const struct ocelot_stat_layout vsc9959_stats_layout[] = {
 466         { .offset = 0x00,       .name = "rx_octets", },
 467         { .offset = 0x01,       .name = "rx_unicast", },
 468         { .offset = 0x02,       .name = "rx_multicast", },
 469         { .offset = 0x03,       .name = "rx_broadcast", },
 470         { .offset = 0x04,       .name = "rx_shorts", },
 471         { .offset = 0x05,       .name = "rx_fragments", },
 472         { .offset = 0x06,       .name = "rx_jabbers", },
 473         { .offset = 0x07,       .name = "rx_crc_align_errs", },
 474         { .offset = 0x08,       .name = "rx_sym_errs", },
 475         { .offset = 0x09,       .name = "rx_frames_below_65_octets", },
 476         { .offset = 0x0A,       .name = "rx_frames_65_to_127_octets", },
 477         { .offset = 0x0B,       .name = "rx_frames_128_to_255_octets", },
 478         { .offset = 0x0C,       .name = "rx_frames_256_to_511_octets", },
 479         { .offset = 0x0D,       .name = "rx_frames_512_to_1023_octets", },
 480         { .offset = 0x0E,       .name = "rx_frames_1024_to_1526_octets", },
 481         { .offset = 0x0F,       .name = "rx_frames_over_1526_octets", },
 482         { .offset = 0x10,       .name = "rx_pause", },
 483         { .offset = 0x11,       .name = "rx_control", },
 484         { .offset = 0x12,       .name = "rx_longs", },
 485         { .offset = 0x13,       .name = "rx_classified_drops", },
 486         { .offset = 0x14,       .name = "rx_red_prio_0", },
 487         { .offset = 0x15,       .name = "rx_red_prio_1", },
 488         { .offset = 0x16,       .name = "rx_red_prio_2", },
 489         { .offset = 0x17,       .name = "rx_red_prio_3", },
 490         { .offset = 0x18,       .name = "rx_red_prio_4", },
 491         { .offset = 0x19,       .name = "rx_red_prio_5", },
 492         { .offset = 0x1A,       .name = "rx_red_prio_6", },
 493         { .offset = 0x1B,       .name = "rx_red_prio_7", },
 494         { .offset = 0x1C,       .name = "rx_yellow_prio_0", },
 495         { .offset = 0x1D,       .name = "rx_yellow_prio_1", },
 496         { .offset = 0x1E,       .name = "rx_yellow_prio_2", },
 497         { .offset = 0x1F,       .name = "rx_yellow_prio_3", },
 498         { .offset = 0x20,       .name = "rx_yellow_prio_4", },
 499         { .offset = 0x21,       .name = "rx_yellow_prio_5", },
 500         { .offset = 0x22,       .name = "rx_yellow_prio_6", },
 501         { .offset = 0x23,       .name = "rx_yellow_prio_7", },
 502         { .offset = 0x24,       .name = "rx_green_prio_0", },
 503         { .offset = 0x25,       .name = "rx_green_prio_1", },
 504         { .offset = 0x26,       .name = "rx_green_prio_2", },
 505         { .offset = 0x27,       .name = "rx_green_prio_3", },
 506         { .offset = 0x28,       .name = "rx_green_prio_4", },
 507         { .offset = 0x29,       .name = "rx_green_prio_5", },
 508         { .offset = 0x2A,       .name = "rx_green_prio_6", },
 509         { .offset = 0x2B,       .name = "rx_green_prio_7", },
 510         { .offset = 0x80,       .name = "tx_octets", },
 511         { .offset = 0x81,       .name = "tx_unicast", },
 512         { .offset = 0x82,       .name = "tx_multicast", },
 513         { .offset = 0x83,       .name = "tx_broadcast", },
 514         { .offset = 0x84,       .name = "tx_collision", },
 515         { .offset = 0x85,       .name = "tx_drops", },
 516         { .offset = 0x86,       .name = "tx_pause", },
 517         { .offset = 0x87,       .name = "tx_frames_below_65_octets", },
 518         { .offset = 0x88,       .name = "tx_frames_65_to_127_octets", },
 519         { .offset = 0x89,       .name = "tx_frames_128_255_octets", },
 520         { .offset = 0x8B,       .name = "tx_frames_256_511_octets", },
 521         { .offset = 0x8C,       .name = "tx_frames_1024_1526_octets", },
 522         { .offset = 0x8D,       .name = "tx_frames_over_1526_octets", },
 523         { .offset = 0x8E,       .name = "tx_yellow_prio_0", },
 524         { .offset = 0x8F,       .name = "tx_yellow_prio_1", },
 525         { .offset = 0x90,       .name = "tx_yellow_prio_2", },
 526         { .offset = 0x91,       .name = "tx_yellow_prio_3", },
 527         { .offset = 0x92,       .name = "tx_yellow_prio_4", },
 528         { .offset = 0x93,       .name = "tx_yellow_prio_5", },
 529         { .offset = 0x94,       .name = "tx_yellow_prio_6", },
 530         { .offset = 0x95,       .name = "tx_yellow_prio_7", },
 531         { .offset = 0x96,       .name = "tx_green_prio_0", },
 532         { .offset = 0x97,       .name = "tx_green_prio_1", },
 533         { .offset = 0x98,       .name = "tx_green_prio_2", },
 534         { .offset = 0x99,       .name = "tx_green_prio_3", },
 535         { .offset = 0x9A,       .name = "tx_green_prio_4", },
 536         { .offset = 0x9B,       .name = "tx_green_prio_5", },
 537         { .offset = 0x9C,       .name = "tx_green_prio_6", },
 538         { .offset = 0x9D,       .name = "tx_green_prio_7", },
 539         { .offset = 0x9E,       .name = "tx_aged", },
 540         { .offset = 0x100,      .name = "drop_local", },
 541         { .offset = 0x101,      .name = "drop_tail", },
 542         { .offset = 0x102,      .name = "drop_yellow_prio_0", },
 543         { .offset = 0x103,      .name = "drop_yellow_prio_1", },
 544         { .offset = 0x104,      .name = "drop_yellow_prio_2", },
 545         { .offset = 0x105,      .name = "drop_yellow_prio_3", },
 546         { .offset = 0x106,      .name = "drop_yellow_prio_4", },
 547         { .offset = 0x107,      .name = "drop_yellow_prio_5", },
 548         { .offset = 0x108,      .name = "drop_yellow_prio_6", },
 549         { .offset = 0x109,      .name = "drop_yellow_prio_7", },
 550         { .offset = 0x10A,      .name = "drop_green_prio_0", },
 551         { .offset = 0x10B,      .name = "drop_green_prio_1", },
 552         { .offset = 0x10C,      .name = "drop_green_prio_2", },
 553         { .offset = 0x10D,      .name = "drop_green_prio_3", },
 554         { .offset = 0x10E,      .name = "drop_green_prio_4", },
 555         { .offset = 0x10F,      .name = "drop_green_prio_5", },
 556         { .offset = 0x110,      .name = "drop_green_prio_6", },
 557         { .offset = 0x111,      .name = "drop_green_prio_7", },
 558 };
 559
 560 static struct vcap_field vsc9959_vcap_is2_keys[] = {
 561         /* Common: 41 bits */
 562         [VCAP_IS2_TYPE]                         = {  0,   4},
 563         [VCAP_IS2_HK_FIRST]                     = {  4,   1},
 564         [VCAP_IS2_HK_PAG]                       = {  5,   8},
 565         [VCAP_IS2_HK_IGR_PORT_MASK]             = { 13,   7},
 566         [VCAP_IS2_HK_RSV2]                      = { 20,   1},
 567         [VCAP_IS2_HK_HOST_MATCH]                = { 21,   1},
 568         [VCAP_IS2_HK_L2_MC]                     = { 22,   1},
 569         [VCAP_IS2_HK_L2_BC]                     = { 23,   1},
 570         [VCAP_IS2_HK_VLAN_TAGGED]               = { 24,   1},
 571         [VCAP_IS2_HK_VID]                       = { 25,  12},
 572         [VCAP_IS2_HK_DEI]                       = { 37,   1},
 573         [VCAP_IS2_HK_PCP]                       = { 38,   3},
 574         /* MAC_ETYPE / MAC_LLC / MAC_SNAP / OAM common */
 575         [VCAP_IS2_HK_L2_DMAC]                   = { 41,  48},
 576         [VCAP_IS2_HK_L2_SMAC]                   = { 89,  48},
 577         /* MAC_ETYPE (TYPE=000) */
 578         [VCAP_IS2_HK_MAC_ETYPE_ETYPE]           = {137,  16},
 579         [VCAP_IS2_HK_MAC_ETYPE_L2_PAYLOAD0]     = {153,  16},
 580         [VCAP_IS2_HK_MAC_ETYPE_L2_PAYLOAD1]     = {169,   8},
 581         [VCAP_IS2_HK_MAC_ETYPE_L2_PAYLOAD2]     = {177,   3},
 582         /* MAC_LLC (TYPE=001) */
 583         [VCAP_IS2_HK_MAC_LLC_L2_LLC]            = {137,  40},
 584         /* MAC_SNAP (TYPE=010) */
 585         [VCAP_IS2_HK_MAC_SNAP_L2_SNAP]          = {137,  40},
 586         /* MAC_ARP (TYPE=011) */
 587         [VCAP_IS2_HK_MAC_ARP_SMAC]              = { 41,  48},
 588         [VCAP_IS2_HK_MAC_ARP_ADDR_SPACE_OK]     = { 89,   1},
 589         [VCAP_IS2_HK_MAC_ARP_PROTO_SPACE_OK]    = { 90,   1},
 590         [VCAP_IS2_HK_MAC_ARP_LEN_OK]            = { 91,   1},
 591         [VCAP_IS2_HK_MAC_ARP_TARGET_MATCH]      = { 92,   1},
 592         [VCAP_IS2_HK_MAC_ARP_SENDER_MATCH]      = { 93,   1},
 593         [VCAP_IS2_HK_MAC_ARP_OPCODE_UNKNOWN]    = { 94,   1},
 594         [VCAP_IS2_HK_MAC_ARP_OPCODE]            = { 95,   2},
 595         [VCAP_IS2_HK_MAC_ARP_L3_IP4_DIP]        = { 97,  32},
 596         [VCAP_IS2_HK_MAC_ARP_L3_IP4_SIP]        = {129,  32},
 597         [VCAP_IS2_HK_MAC_ARP_DIP_EQ_SIP]        = {161,   1},
 598         /* IP4_TCP_UDP / IP4_OTHER common */
 599         [VCAP_IS2_HK_IP4]                       = { 41,   1},
 600         [VCAP_IS2_HK_L3_FRAGMENT]               = { 42,   1},
 601         [VCAP_IS2_HK_L3_FRAG_OFS_GT0]           = { 43,   1},
 602         [VCAP_IS2_HK_L3_OPTIONS]                = { 44,   1},
 603         [VCAP_IS2_HK_IP4_L3_TTL_GT0]            = { 45,   1},
 604         [VCAP_IS2_HK_L3_TOS]                    = { 46,   8},
 605         [VCAP_IS2_HK_L3_IP4_DIP]                = { 54,  32},
 606         [VCAP_IS2_HK_L3_IP4_SIP]                = { 86,  32},
 607         [VCAP_IS2_HK_DIP_EQ_SIP]                = {118,   1},
 608         /* IP4_TCP_UDP (TYPE=100) */
 609         [VCAP_IS2_HK_TCP]                       = {119,   1},
 610         [VCAP_IS2_HK_L4_SPORT]                  = {120,  16},
 611         [VCAP_IS2_HK_L4_DPORT]                  = {136,  16},
 612         [VCAP_IS2_HK_L4_RNG]                    = {152,   8},
 613         [VCAP_IS2_HK_L4_SPORT_EQ_DPORT]         = {160,   1},
 614         [VCAP_IS2_HK_L4_SEQUENCE_EQ0]           = {161,   1},
 615         [VCAP_IS2_HK_L4_URG]                    = {162,   1},
 616         [VCAP_IS2_HK_L4_ACK]                    = {163,   1},
 617         [VCAP_IS2_HK_L4_PSH]                    = {164,   1},
 618         [VCAP_IS2_HK_L4_RST]                    = {165,   1},
 619         [VCAP_IS2_HK_L4_SYN]                    = {166,   1},
 620         [VCAP_IS2_HK_L4_FIN]                    = {167,   1},
 621         [VCAP_IS2_HK_L4_1588_DOM]               = {168,   8},
 622         [VCAP_IS2_HK_L4_1588_VER]               = {176,   4},
 623         /* IP4_OTHER (TYPE=101) */
 624         [VCAP_IS2_HK_IP4_L3_PROTO]              = {119,   8},
 625         [VCAP_IS2_HK_L3_PAYLOAD]                = {127,  56},
 626         /* IP6_STD (TYPE=110) */
 627         [VCAP_IS2_HK_IP6_L3_TTL_GT0]            = { 41,   1},
 628         [VCAP_IS2_HK_L3_IP6_SIP]                = { 42, 128},
 629         [VCAP_IS2_HK_IP6_L3_PROTO]              = {170,   8},
 630         /* OAM (TYPE=111) */
 631         [VCAP_IS2_HK_OAM_MEL_FLAGS]             = {137,   7},
 632         [VCAP_IS2_HK_OAM_VER]                   = {144,   5},
 633         [VCAP_IS2_HK_OAM_OPCODE]                = {149,   8},
 634         [VCAP_IS2_HK_OAM_FLAGS]                 = {157,   8},
 635         [VCAP_IS2_HK_OAM_MEPID]                 = {165,  16},
 636         [VCAP_IS2_HK_OAM_CCM_CNTS_EQ0]          = {181,   1},
 637         [VCAP_IS2_HK_OAM_IS_Y1731]              = {182,   1},
 638 };
 639
 640 static struct vcap_field vsc9959_vcap_is2_actions[] = {
 641         [VCAP_IS2_ACT_HIT_ME_ONCE]              = {  0,  1},
 642         [VCAP_IS2_ACT_CPU_COPY_ENA]             = {  1,  1},
 643         [VCAP_IS2_ACT_CPU_QU_NUM]               = {  2,  3},
 644         [VCAP_IS2_ACT_MASK_MODE]                = {  5,  2},
 645         [VCAP_IS2_ACT_MIRROR_ENA]               = {  7,  1},
 646         [VCAP_IS2_ACT_LRN_DIS]                  = {  8,  1},
 647         [VCAP_IS2_ACT_POLICE_ENA]               = {  9,  1},
 648         [VCAP_IS2_ACT_POLICE_IDX]               = { 10,  9},
 649         [VCAP_IS2_ACT_POLICE_VCAP_ONLY]         = { 19,  1},
 650         [VCAP_IS2_ACT_PORT_MASK]                = { 20, 11},
 651         [VCAP_IS2_ACT_REW_OP]                   = { 31,  9},
 652         [VCAP_IS2_ACT_SMAC_REPLACE_ENA]         = { 40,  1},
 653         [VCAP_IS2_ACT_RSV]                      = { 41,  2},
 654         [VCAP_IS2_ACT_ACL_ID]                   = { 43,  6},
 655         [VCAP_IS2_ACT_HIT_CNT]                  = { 49, 32},
 656 };
 657
 658 static const struct vcap_props vsc9959_vcap_props[] = {
 659         [VCAP_IS2] = {
 660                 .tg_width = 2,
 661                 .sw_count = 4,
 662                 .entry_count = VSC9959_VCAP_IS2_CNT,
 663                 .entry_width = VSC9959_VCAP_IS2_ENTRY_WIDTH,
 664                 .action_count = VSC9959_VCAP_IS2_CNT +
 665                                 VSC9959_VCAP_PORT_CNT + 2,
 666                 .action_width = 89,
 667                 .action_type_width = 1,
 668                 .action_table = {
 669                         [IS2_ACTION_TYPE_NORMAL] = {
 670                                 .width = 44,
 671                                 .count = 2
 672                         },
 673                         [IS2_ACTION_TYPE_SMAC_SIP] = {
 674                                 .width = 6,
 675                                 .count = 4
 676                         },
 677                 },
 678                 .counter_words = 4,
 679                 .counter_width = 32,
 680         },
 681 };
 682
 683 #define VSC9959_INIT_TIMEOUT                    50000
 684 #define VSC9959_GCB_RST_SLEEP                   100
 685 #define VSC9959_SYS_RAMINIT_SLEEP               80
 686
 687 static int vsc9959_gcb_soft_rst_status(struct ocelot *ocelot)
 688 {
 689         int val;
 690
 691         regmap_field_read(ocelot->regfields[GCB_SOFT_RST_SWC_RST], &val);
 692
 693         return val;
 694 }
 695
 696 static int vsc9959_sys_ram_init_status(struct ocelot *ocelot)
 697 {
 698         return ocelot_read(ocelot, SYS_RAM_INIT);
 699 }
 700
 701 static int vsc9959_reset(struct ocelot *ocelot)
 702 {
 703         int val, err;
 704
 705         /* soft-reset the switch core */
 706         regmap_field_write(ocelot->regfields[GCB_SOFT_RST_SWC_RST], 1);
 707
 708         err = readx_poll_timeout(vsc9959_gcb_soft_rst_status, ocelot, val, !val,
 709                                  VSC9959_GCB_RST_SLEEP, VSC9959_INIT_TIMEOUT);
 710         if (err) {
 711                 dev_err(ocelot->dev, "timeout: switch core reset\n");
 712                 return err;
 713         }
 714
 715         /* initialize switch mem ~40us */
 716         ocelot_write(ocelot, SYS_RAM_INIT_RAM_INIT, SYS_RAM_INIT);
 717         err = readx_poll_timeout(vsc9959_sys_ram_init_status, ocelot, val, !val,
 718                                  VSC9959_SYS_RAMINIT_SLEEP,
 719                                  VSC9959_INIT_TIMEOUT);
 720         if (err) {
 721                 dev_err(ocelot->dev, "timeout: switch sram init\n");
 722                 return err;
 723         }
 724
 725         /* enable switch core */
 726         regmap_field_write(ocelot->regfields[SYS_RESET_CFG_CORE_ENA], 1);
 727
 728         return 0;
 729 }
 730
 731 /* We enable SGMII AN only when the PHY has managed = "in-band-status" in the
 732  * device tree. If we are in MLO_AN_PHY mode, we program directly state->speed
 733  * into the PCS, which is retrieved out-of-band over MDIO. This also has the
 734  * benefit of working with SGMII fixed-links, like downstream switches, where
 735  * both link partners attempt to operate as AN slaves and therefore AN never
 736  * completes.  But it also has the disadvantage that some PHY chips don't pass
 737  * traffic if SGMII AN is enabled but not completed (acknowledged by us), so
 738  * setting MLO_AN_INBAND is actually required for those.
 739  */
 740 static void vsc9959_pcs_config_sgmii(struct phy_device *pcs,
 741                                      unsigned int link_an_mode,
 742                                      const struct phylink_link_state *state)
 743 {
 744         int bmsr, bmcr;
 745
 746         /* Some PHYs like VSC8234 don't like it when AN restarts on
 747          * their system  side and they restart line side AN too, going
 748          * into an endless link up/down loop.  Don't restart PCS AN if
 749          * link is up already.
 750          * We do check that AN is enabled just in case this is the 1st
 751          * call, PCS detects a carrier but AN is disabled from power on
 752          * or by boot loader.
 753          */
 754         bmcr = phy_read(pcs, MII_BMCR);
 755         if (bmcr < 0)
 756                 return;
 757
 758         bmsr = phy_read(pcs, MII_BMSR);
 759         if (bmsr < 0)
 760                 return;
 761
 762         if ((bmcr & BMCR_ANENABLE) && (bmsr & BMSR_LSTATUS))
 763                 return;
 764
 765         /* SGMII spec requires tx_config_Reg[15:0] to be exactly 0x4001
 766          * for the MAC PCS in order to acknowledge the AN.
 767          */
 768         phy_write(pcs, MII_ADVERTISE, ADVERTISE_SGMII |
 769                                       ADVERTISE_LPACK);
 770
 771         phy_write(pcs, ENETC_PCS_IF_MODE,
 772                   ENETC_PCS_IF_MODE_SGMII_EN |
 773                   ENETC_PCS_IF_MODE_USE_SGMII_AN);
 774
 775         /* Adjust link timer for SGMII */
 776         phy_write(pcs, ENETC_PCS_LINK_TIMER1,
 777                   ENETC_PCS_LINK_TIMER1_VAL);
 778         phy_write(pcs, ENETC_PCS_LINK_TIMER2,
 779                   ENETC_PCS_LINK_TIMER2_VAL);
 780
 781         phy_set_bits(pcs, MII_BMCR, BMCR_ANENABLE);
 782 }
 783
 784 static void vsc9959_pcs_config_usxgmii(struct phy_device *pcs,
 785                                        unsigned int link_an_mode,
 786                                        const struct phylink_link_state *state)
 787 {
 788         /* Configure device ability for the USXGMII Replicator */
 789         phy_write_mmd(pcs, MDIO_MMD_VEND2, MII_ADVERTISE,
 790                       USXGMII_ADVERTISE_SPEED(USXGMII_SPEED_2500) |
 791                       USXGMII_ADVERTISE_LNKS(1) |
 792                       ADVERTISE_SGMII |
 793                       ADVERTISE_LPACK |
 794                       USXGMII_ADVERTISE_FDX);
 795 }
 796
 797 static void vsc9959_pcs_config(struct ocelot *ocelot, int port,
 798                                unsigned int link_an_mode,
 799                                const struct phylink_link_state *state)
 800 {
 801         struct felix *felix = ocelot_to_felix(ocelot);
 802         struct phy_device *pcs = felix->pcs[port];
 803
 804         if (!pcs)
 805                 return;
 806
 807         /* The PCS does not implement the BMSR register fully, so capability
 808          * detection via genphy_read_abilities does not work. Since we can get
 809          * the PHY config word from the LPA register though, there is still
 810          * value in using the generic phy_resolve_aneg_linkmode function. So
 811          * populate the supported and advertising link modes manually here.
 812          */
 813         linkmode_set_bit_array(phy_basic_ports_array,
 814                                ARRAY_SIZE(phy_basic_ports_array),
 815                                pcs->supported);
 816         linkmode_set_bit(ETHTOOL_LINK_MODE_10baseT_Half_BIT, pcs->supported);
 817         linkmode_set_bit(ETHTOOL_LINK_MODE_10baseT_Full_BIT, pcs->supported);
 818         linkmode_set_bit(ETHTOOL_LINK_MODE_100baseT_Half_BIT, pcs->supported);
 819         linkmode_set_bit(ETHTOOL_LINK_MODE_100baseT_Full_BIT, pcs->supported);
 820         linkmode_set_bit(ETHTOOL_LINK_MODE_1000baseT_Half_BIT, pcs->supported);
 821         linkmode_set_bit(ETHTOOL_LINK_MODE_1000baseT_Full_BIT, pcs->supported);
 822         if (pcs->interface == PHY_INTERFACE_MODE_2500BASEX ||
 823             pcs->interface == PHY_INTERFACE_MODE_USXGMII)
 824                 linkmode_set_bit(ETHTOOL_LINK_MODE_2500baseX_Full_BIT,
 825                                  pcs->supported);
 826         if (pcs->interface != PHY_INTERFACE_MODE_2500BASEX)
 827                 linkmode_set_bit(ETHTOOL_LINK_MODE_Autoneg_BIT,
 828                                  pcs->supported);
 829         phy_advertise_supported(pcs);
 830
 831         if (!phylink_autoneg_inband(link_an_mode))
 832                 return;
 833
 834         switch (pcs->interface) {
 835         case PHY_INTERFACE_MODE_SGMII:
 836         case PHY_INTERFACE_MODE_QSGMII:
 837                 vsc9959_pcs_config_sgmii(pcs, link_an_mode, state);
 838                 break;
 839         case PHY_INTERFACE_MODE_2500BASEX:
 840                 phydev_err(pcs, "AN not supported on 3.125GHz SerDes lane\n");
 841                 break;
 842         case PHY_INTERFACE_MODE_USXGMII:
 843                 vsc9959_pcs_config_usxgmii(pcs, link_an_mode, state);
 844                 break;
 845         default:
 846                 dev_err(ocelot->dev, "Unsupported link mode %s\n",
 847                         phy_modes(pcs->interface));
 848         }
 849 }
 850
 851 static void vsc9959_pcs_link_up_sgmii(struct phy_device *pcs,
 852                                       unsigned int link_an_mode,
 853                                       int speed, int duplex)
 854 {
 855         u16 if_mode = ENETC_PCS_IF_MODE_SGMII_EN;
 856
 857         switch (speed) {
 858         case SPEED_1000:
 859                 if_mode |= ENETC_PCS_IF_MODE_SGMII_SPEED(ENETC_PCS_SPEED_1000);
 860                 break;
 861         case SPEED_100:
 862                 if_mode |= ENETC_PCS_IF_MODE_SGMII_SPEED(ENETC_PCS_SPEED_100);
 863                 break;
 864         case SPEED_10:
 865                 if_mode |= ENETC_PCS_IF_MODE_SGMII_SPEED(ENETC_PCS_SPEED_10);
 866                 break;
 867         default:
 868                 phydev_err(pcs, "Invalid PCS speed %d\n", speed);
 869                 return;
 870         }
 871
 872         if (duplex == DUPLEX_HALF)
 873                 if_mode |= ENETC_PCS_IF_MODE_DUPLEX_HALF;
 874
 875         phy_write(pcs, ENETC_PCS_IF_MODE, if_mode);
 876         phy_clear_bits(pcs, MII_BMCR, BMCR_ANENABLE);
 877 }
 878
 879 /* 2500Base-X is SerDes protocol 7 on Felix and 6 on ENETC. It is a SerDes lane
 880  * clocked at 3.125 GHz which encodes symbols with 8b/10b and does not have
 881  * auto-negotiation of any link parameters. Electrically it is compatible with
 882  * a single lane of XAUI.
 883  * The hardware reference manual wants to call this mode SGMII, but it isn't
 884  * really, since the fundamental features of SGMII:
 885  * - Downgrading the link speed by duplicating symbols
 886  * - Auto-negotiation
 887  * are not there.
 888  * The speed is configured at 1000 in the IF_MODE and BMCR MDIO registers
 889  * because the clock frequency is actually given by a PLL configured in the
 890  * Reset Configuration Word (RCW).
 891  * Since there is no difference between fixed speed SGMII w/o AN and 802.3z w/o
 892  * AN, we call this PHY interface type 2500Base-X. In case a PHY negotiates a
 893  * lower link speed on line side, the system-side interface remains fixed at
 894  * 2500 Mbps and we do rate adaptation through pause frames.
 895  */
 896 static void vsc9959_pcs_link_up_2500basex(struct phy_device *pcs,
 897                                           unsigned int link_an_mode,
 898                                           int speed, int duplex)
 899 {
 900         u16 if_mode = ENETC_PCS_IF_MODE_SGMII_SPEED(ENETC_PCS_SPEED_2500) |
 901                       ENETC_PCS_IF_MODE_SGMII_EN;
 902
 903         if (duplex == DUPLEX_HALF)
 904                 if_mode |= ENETC_PCS_IF_MODE_DUPLEX_HALF;
 905
 906         phy_write(pcs, ENETC_PCS_IF_MODE, if_mode);
 907         phy_clear_bits(pcs, MII_BMCR, BMCR_ANENABLE);
 908 }
 909
 910 static void vsc9959_pcs_link_up(struct ocelot *ocelot, int port,
 911                                 unsigned int link_an_mode,
 912                                 phy_interface_t interface,
 913                                 int speed, int duplex)
 914 {
 915         struct felix *felix = ocelot_to_felix(ocelot);
 916         struct phy_device *pcs = felix->pcs[port];
 917
 918         if (!pcs)
 919                 return;
 920
 921         if (phylink_autoneg_inband(link_an_mode))
 922                 return;
 923
 924         switch (interface) {
 925         case PHY_INTERFACE_MODE_SGMII:
 926         case PHY_INTERFACE_MODE_QSGMII:
 927                 vsc9959_pcs_link_up_sgmii(pcs, link_an_mode, speed, duplex);
 928                 break;
 929         case PHY_INTERFACE_MODE_2500BASEX:
 930                 vsc9959_pcs_link_up_2500basex(pcs, link_an_mode, speed,
 931                                               duplex);
 932                 break;
 933         case PHY_INTERFACE_MODE_USXGMII:
 934                 phydev_err(pcs, "USXGMII only supports in-band AN for now\n");
 935                 break;
 936         default:
 937                 dev_err(ocelot->dev, "Unsupported link mode %s\n",
 938                         phy_modes(pcs->interface));
 939         }
 940 }
 941
 942 static void vsc9959_pcs_link_state_resolve(struct phy_device *pcs,
 943                                            struct phylink_link_state *state)
 944 {
 945         state->an_complete = pcs->autoneg_complete;
 946         state->an_enabled = pcs->autoneg;
 947         state->link = pcs->link;
 948         state->duplex = pcs->duplex;
 949         state->speed = pcs->speed;
 950         /* SGMII AN does not negotiate flow control, but that's ok,
 951          * since phylink already knows that, and does:
 952          *      link_state.pause |= pl->phy_state.pause;
 953          */
 954         state->pause = MLO_PAUSE_NONE;
 955
 956         phydev_dbg(pcs,
 957                    "mode=%s/%s/%s adv=%*pb lpa=%*pb link=%u an_enabled=%u an_complete=%u\n",
 958                    phy_modes(pcs->interface),
 959                    phy_speed_to_str(pcs->speed),
 960                    phy_duplex_to_str(pcs->duplex),
 961                    __ETHTOOL_LINK_MODE_MASK_NBITS, pcs->advertising,
 962                    __ETHTOOL_LINK_MODE_MASK_NBITS, pcs->lp_advertising,
 963                    pcs->link, pcs->autoneg, pcs->autoneg_complete);
 964 }
 965
 966 static void vsc9959_pcs_link_state_sgmii(struct phy_device *pcs,
 967                                          struct phylink_link_state *state)
 968 {
 969         int err;
 970
 971         err = genphy_update_link(pcs);
 972         if (err < 0)
 973                 return;
 974
 975         if (pcs->autoneg_complete) {
 976                 u16 lpa = phy_read(pcs, MII_LPA);
 977
 978                 mii_lpa_to_linkmode_lpa_sgmii(pcs->lp_advertising, lpa);
 979
 980                 phy_resolve_aneg_linkmode(pcs);
 981         }
 982 }
 983
 984 static void vsc9959_pcs_link_state_2500basex(struct phy_device *pcs,
 985                                              struct phylink_link_state *state)
 986 {
 987         int err;
 988
 989         err = genphy_update_link(pcs);
 990         if (err < 0)
 991                 return;
 992
 993         pcs->speed = SPEED_2500;
 994         pcs->asym_pause = true;
 995         pcs->pause = true;
 996 }
 997
 998 static void vsc9959_pcs_link_state_usxgmii(struct phy_device *pcs,
 999                                            struct phylink_link_state *state)
1000 {
1001         int status, lpa;
1002
1003         status = phy_read_mmd(pcs, MDIO_MMD_VEND2, MII_BMSR);
1004         if (status < 0)
1005                 return;
1006
1007         pcs->autoneg = true;
1008         pcs->autoneg_complete = USXGMII_BMSR_AN_CMPL(status);
1009         pcs->link = USXGMII_BMSR_LNKS(status);
1010
1011         if (!pcs->link || !pcs->autoneg_complete)
1012                 return;
1013
1014         lpa = phy_read_mmd(pcs, MDIO_MMD_VEND2, MII_LPA);
1015         if (lpa < 0)
1016                 return;
1017
1018         switch (USXGMII_LPA_SPEED(lpa)) {
1019         case USXGMII_SPEED_10:
1020                 pcs->speed = SPEED_10;
1021                 break;
1022         case USXGMII_SPEED_100:
1023                 pcs->speed = SPEED_100;
1024                 break;
1025         case USXGMII_SPEED_1000:
1026                 pcs->speed = SPEED_1000;
1027                 break;
1028         case USXGMII_SPEED_2500:
1029                 pcs->speed = SPEED_2500;
1030                 break;
1031         default:
1032                 break;
1033         }
1034
1035         if (USXGMII_LPA_DUPLEX(lpa))
1036                 pcs->duplex = DUPLEX_FULL;
1037         else
1038                 pcs->duplex = DUPLEX_HALF;
1039 }
1040
1041 static void vsc9959_pcs_link_state(struct ocelot *ocelot, int port,
1042                                    struct phylink_link_state *state)
1043 {
1044         struct felix *felix = ocelot_to_felix(ocelot);
1045         struct phy_device *pcs = felix->pcs[port];
1046
1047         if (!pcs)
1048                 return;
1049
1050         pcs->speed = SPEED_UNKNOWN;
1051         pcs->duplex = DUPLEX_UNKNOWN;
1052         pcs->pause = 0;
1053         pcs->asym_pause = 0;
1054
1055         switch (pcs->interface) {
1056         case PHY_INTERFACE_MODE_SGMII:
1057         case PHY_INTERFACE_MODE_QSGMII:
1058                 vsc9959_pcs_link_state_sgmii(pcs, state);
1059                 break;
1060         case PHY_INTERFACE_MODE_2500BASEX:
1061                 vsc9959_pcs_link_state_2500basex(pcs, state);
1062                 break;
1063         case PHY_INTERFACE_MODE_USXGMII:
1064                 vsc9959_pcs_link_state_usxgmii(pcs, state);
1065                 break;
1066         default:
1067                 return;
1068         }
1069
1070         vsc9959_pcs_link_state_resolve(pcs, state);
1071 }
1072
1073 static int vsc9959_prevalidate_phy_mode(struct ocelot *ocelot, int port,
1074                                         phy_interface_t phy_mode)
1075 {
1076         switch (phy_mode) {
1077         case PHY_INTERFACE_MODE_INTERNAL:
1078                 if (port != 4 && port != 5)
1079                         return -ENOTSUPP;
1080                 return 0;
1081         case PHY_INTERFACE_MODE_SGMII:
1082         case PHY_INTERFACE_MODE_QSGMII:
1083         case PHY_INTERFACE_MODE_USXGMII:
1084         case PHY_INTERFACE_MODE_2500BASEX:
1085                 /* Not supported on internal to-CPU ports */
1086                 if (port == 4 || port == 5)
1087                         return -ENOTSUPP;
1088                 return 0;
1089         default:
1090                 return -ENOTSUPP;
1091         }
1092 }
1093
1094 static const struct ocelot_ops vsc9959_ops = {
1095         .reset                  = vsc9959_reset,
1096 };
1097
1098 static int vsc9959_mdio_bus_alloc(struct ocelot *ocelot)
1099 {
1100         struct felix *felix = ocelot_to_felix(ocelot);
1101         struct enetc_mdio_priv *mdio_priv;
1102         struct device *dev = ocelot->dev;
1103         resource_size_t imdio_base;
1104         void __iomem *imdio_regs;
1105         struct resource res;
1106         struct enetc_hw *hw;
1107         struct mii_bus *bus;
1108         int port;
1109         int rc;
1110
1111         felix->pcs = devm_kcalloc(dev, felix->info->num_ports,
1112                                   sizeof(struct phy_device *),
1113                                   GFP_KERNEL);
1114         if (!felix->pcs) {
1115                 dev_err(dev, "failed to allocate array for PCS PHYs\n");
1116                 return -ENOMEM;
1117         }
1118
1119         imdio_base = pci_resource_start(felix->pdev,
1120                                         felix->info->imdio_pci_bar);
1121
1122         memcpy(&res, felix->info->imdio_res, sizeof(res));
1123         res.flags = IORESOURCE_MEM;
1124         res.start += imdio_base;
1125         res.end += imdio_base;
1126
1127         imdio_regs = devm_ioremap_resource(dev, &res);
1128         if (IS_ERR(imdio_regs)) {
1129                 dev_err(dev, "failed to map internal MDIO registers\n");
1130                 return PTR_ERR(imdio_regs);
1131         }
1132
1133         hw = enetc_hw_alloc(dev, imdio_regs);
1134         if (IS_ERR(hw)) {
1135                 dev_err(dev, "failed to allocate ENETC HW structure\n");
1136                 return PTR_ERR(hw);
1137         }
1138
1139         bus = devm_mdiobus_alloc_size(dev, sizeof(*mdio_priv));
1140         if (!bus)
1141                 return -ENOMEM;
1142
1143         bus->name = "VSC9959 internal MDIO bus";
1144         bus->read = enetc_mdio_read;
1145         bus->write = enetc_mdio_write;
1146         bus->parent = dev;
1147         mdio_priv = bus->priv;
1148         mdio_priv->hw = hw;
1149         /* This gets added to imdio_regs, which already maps addresses
1150          * starting with the proper offset.
1151          */
1152         mdio_priv->mdio_base = 0;
1153         snprintf(bus->id, MII_BUS_ID_SIZE, "%s-imdio", dev_name(dev));
1154
1155         /* Needed in order to initialize the bus mutex lock */
1156         rc = mdiobus_register(bus);
1157         if (rc < 0) {
1158                 dev_err(dev, "failed to register MDIO bus\n");
1159                 return rc;
1160         }
1161
1162         felix->imdio = bus;
1163
1164         for (port = 0; port < felix->info->num_ports; port++) {
1165                 struct ocelot_port *ocelot_port = ocelot->ports[port];
1166                 struct phy_device *pcs;
1167                 bool is_c45 = false;
1168
1169                 if (ocelot_port->phy_mode == PHY_INTERFACE_MODE_USXGMII)
1170                         is_c45 = true;
1171
1172                 pcs = get_phy_device(felix->imdio, port, is_c45);
1173                 if (IS_ERR(pcs))
1174                         continue;
1175
1176                 pcs->interface = ocelot_port->phy_mode;
1177                 felix->pcs[port] = pcs;
1178
1179                 dev_info(dev, "Found PCS at internal MDIO address %d\n", port);
1180         }
1181
1182         return 0;
1183 }
1184
1185 static void vsc9959_mdio_bus_free(struct ocelot *ocelot)
1186 {
1187         struct felix *felix = ocelot_to_felix(ocelot);
1188         int port;
1189
1190         for (port = 0; port < ocelot->num_phys_ports; port++) {
1191                 struct phy_device *pcs = felix->pcs[port];
1192
1193                 if (!pcs)
1194                         continue;
1195
1196                 put_device(&pcs->mdio.dev);
1197         }
1198         mdiobus_unregister(felix->imdio);
1199 }
1200
1201 static void vsc9959_sched_speed_set(struct ocelot *ocelot, int port,
1202                                     u32 speed)
1203 {
1204         ocelot_rmw_rix(ocelot,
1205                        QSYS_TAG_CONFIG_LINK_SPEED(speed),
1206                        QSYS_TAG_CONFIG_LINK_SPEED_M,
1207                        QSYS_TAG_CONFIG, port);
1208 }
1209
1210 static void vsc9959_new_base_time(struct ocelot *ocelot, ktime_t base_time,
1211                                   u64 cycle_time,
1212                                   struct timespec64 *new_base_ts)
1213 {
1214         struct timespec64 ts;
1215         ktime_t new_base_time;
1216         ktime_t current_time;
1217
1218         ocelot_ptp_gettime64(&ocelot->ptp_info, &ts);
1219         current_time = timespec64_to_ktime(ts);
1220         new_base_time = base_time;
1221
1222         if (base_time < current_time) {
1223                 u64 nr_of_cycles = current_time - base_time;
1224
1225                 do_div(nr_of_cycles, cycle_time);
1226                 new_base_time += cycle_time * (nr_of_cycles + 1);
1227         }
1228
1229         *new_base_ts = ktime_to_timespec64(new_base_time);
1230 }
1231
1232 static u32 vsc9959_tas_read_cfg_status(struct ocelot *ocelot)
1233 {
1234         return ocelot_read(ocelot, QSYS_TAS_PARAM_CFG_CTRL);
1235 }
1236
1237 static void vsc9959_tas_gcl_set(struct ocelot *ocelot, const u32 gcl_ix,
1238                                 struct tc_taprio_sched_entry *entry)
1239 {
1240         ocelot_write(ocelot,
1241                      QSYS_GCL_CFG_REG_1_GCL_ENTRY_NUM(gcl_ix) |
1242                      QSYS_GCL_CFG_REG_1_GATE_STATE(entry->gate_mask),
1243                      QSYS_GCL_CFG_REG_1);
1244         ocelot_write(ocelot, entry->interval, QSYS_GCL_CFG_REG_2);
1245 }
1246
1247 static int vsc9959_qos_port_tas_set(struct ocelot *ocelot, int port,
1248                                     struct tc_taprio_qopt_offload *taprio)
1249 {
1250         struct timespec64 base_ts;
1251         int ret, i;
1252         u32 val;
1253
1254         if (!taprio->enable) {
1255                 ocelot_rmw_rix(ocelot,
1256                                QSYS_TAG_CONFIG_INIT_GATE_STATE(0xFF),
1257                                QSYS_TAG_CONFIG_ENABLE |
1258                                QSYS_TAG_CONFIG_INIT_GATE_STATE_M,
1259                                QSYS_TAG_CONFIG, port);
1260
1261                 return 0;
1262         }
1263
1264         if (taprio->cycle_time > NSEC_PER_SEC ||
1265             taprio->cycle_time_extension >= NSEC_PER_SEC)
1266                 return -EINVAL;
1267
1268         if (taprio->num_entries > VSC9959_TAS_GCL_ENTRY_MAX)
1269                 return -ERANGE;
1270
1271         ocelot_rmw(ocelot, QSYS_TAS_PARAM_CFG_CTRL_PORT_NUM(port) |
1272                    QSYS_TAS_PARAM_CFG_CTRL_ALWAYS_GUARD_BAND_SCH_Q,
1273                    QSYS_TAS_PARAM_CFG_CTRL_PORT_NUM_M |
1274                    QSYS_TAS_PARAM_CFG_CTRL_ALWAYS_GUARD_BAND_SCH_Q,
1275                    QSYS_TAS_PARAM_CFG_CTRL);
1276
1277         /* Hardware errata -  Admin config could not be overwritten if
1278          * config is pending, need reset the TAS module
1279          */
1280         val = ocelot_read(ocelot, QSYS_PARAM_STATUS_REG_8);
1281         if (val & QSYS_PARAM_STATUS_REG_8_CONFIG_PENDING)
1282                 return  -EBUSY;
1283
1284         ocelot_rmw_rix(ocelot,
1285                        QSYS_TAG_CONFIG_ENABLE |
1286                        QSYS_TAG_CONFIG_INIT_GATE_STATE(0xFF) |
1287                        QSYS_TAG_CONFIG_SCH_TRAFFIC_QUEUES(0xFF),
1288                        QSYS_TAG_CONFIG_ENABLE |
1289                        QSYS_TAG_CONFIG_INIT_GATE_STATE_M |
1290                        QSYS_TAG_CONFIG_SCH_TRAFFIC_QUEUES_M,
1291                        QSYS_TAG_CONFIG, port);
1292
1293         vsc9959_new_base_time(ocelot, taprio->base_time,
1294                               taprio->cycle_time, &base_ts);
1295         ocelot_write(ocelot, base_ts.tv_nsec, QSYS_PARAM_CFG_REG_1);
1296         ocelot_write(ocelot, lower_32_bits(base_ts.tv_sec), QSYS_PARAM_CFG_REG_2);
1297         val = upper_32_bits(base_ts.tv_sec);
1298         ocelot_write(ocelot,
1299                      QSYS_PARAM_CFG_REG_3_BASE_TIME_SEC_MSB(val) |
1300                      QSYS_PARAM_CFG_REG_3_LIST_LENGTH(taprio->num_entries),
1301                      QSYS_PARAM_CFG_REG_3);
1302         ocelot_write(ocelot, taprio->cycle_time, QSYS_PARAM_CFG_REG_4);
1303         ocelot_write(ocelot, taprio->cycle_time_extension, QSYS_PARAM_CFG_REG_5);
1304
1305         for (i = 0; i < taprio->num_entries; i++)
1306                 vsc9959_tas_gcl_set(ocelot, i, &taprio->entries[i]);
1307
1308         ocelot_rmw(ocelot, QSYS_TAS_PARAM_CFG_CTRL_CONFIG_CHANGE,
1309                    QSYS_TAS_PARAM_CFG_CTRL_CONFIG_CHANGE,
1310                    QSYS_TAS_PARAM_CFG_CTRL);
1311
1312         ret = readx_poll_timeout(vsc9959_tas_read_cfg_status, ocelot, val,
1313                                  !(val & QSYS_TAS_PARAM_CFG_CTRL_CONFIG_CHANGE),
1314                                  10, 100000);
1315
1316         return ret;
1317 }
1318
1319 static int vsc9959_qos_port_cbs_set(struct dsa_switch *ds, int port,
1320                                     struct tc_cbs_qopt_offload *cbs_qopt)
1321 {
1322         struct ocelot *ocelot = ds->priv;
1323         int port_ix = port * 8 + cbs_qopt->queue;
1324         u32 rate, burst;
1325
1326         if (cbs_qopt->queue >= ds->num_tx_queues)
1327                 return -EINVAL;
1328
1329         if (!cbs_qopt->enable) {
1330                 ocelot_write_gix(ocelot, QSYS_CIR_CFG_CIR_RATE(0) |
1331                                  QSYS_CIR_CFG_CIR_BURST(0),
1332                                  QSYS_CIR_CFG, port_ix);
1333
1334                 ocelot_rmw_gix(ocelot, 0, QSYS_SE_CFG_SE_AVB_ENA,
1335                                QSYS_SE_CFG, port_ix);
1336
1337                 return 0;
1338         }
1339
1340         /* Rate unit is 100 kbps */
1341         rate = DIV_ROUND_UP(cbs_qopt->idleslope, 100);
1342         /* Avoid using zero rate */
1343         rate = clamp_t(u32, rate, 1, GENMASK(14, 0));
1344         /* Burst unit is 4kB */
1345         burst = DIV_ROUND_UP(cbs_qopt->hicredit, 4096);
1346         /* Avoid using zero burst size */
1347         burst = clamp_t(u32, burst, 1, GENMASK(5, 0));
1348         ocelot_write_gix(ocelot,
1349                          QSYS_CIR_CFG_CIR_RATE(rate) |
1350                          QSYS_CIR_CFG_CIR_BURST(burst),
1351                          QSYS_CIR_CFG,
1352                          port_ix);
1353
1354         ocelot_rmw_gix(ocelot,
1355                        QSYS_SE_CFG_SE_FRM_MODE(0) |
1356                        QSYS_SE_CFG_SE_AVB_ENA,
1357                        QSYS_SE_CFG_SE_AVB_ENA |
1358                        QSYS_SE_CFG_SE_FRM_MODE_M,
1359                        QSYS_SE_CFG,
1360                        port_ix);
1361
1362         return 0;
1363 }
1364
1365 static int vsc9959_port_setup_tc(struct dsa_switch *ds, int port,
1366                                  enum tc_setup_type type,
1367                                  void *type_data)
1368 {
1369         struct ocelot *ocelot = ds->priv;
1370
1371         switch (type) {
1372         case TC_SETUP_QDISC_TAPRIO:
1373                 return vsc9959_qos_port_tas_set(ocelot, port, type_data);
1374         case TC_SETUP_QDISC_CBS:
1375                 return vsc9959_qos_port_cbs_set(ds, port, type_data);
1376         default:
1377                 return -EOPNOTSUPP;
1378         }
1379 }
1380
1381 struct felix_info felix_info_vsc9959 = {
1382         .target_io_res          = vsc9959_target_io_res,
1383         .port_io_res            = vsc9959_port_io_res,
1384         .imdio_res              = &vsc9959_imdio_res,
1385         .regfields              = vsc9959_regfields,
1386         .map                    = vsc9959_regmap,
1387         .ops                    = &vsc9959_ops,
1388         .stats_layout           = vsc9959_stats_layout,
1389         .num_stats              = ARRAY_SIZE(vsc9959_stats_layout),
1390         .vcap_is2_keys          = vsc9959_vcap_is2_keys,
1391         .vcap_is2_actions       = vsc9959_vcap_is2_actions,
1392         .vcap                   = vsc9959_vcap_props,
1393         .shared_queue_sz        = 128 * 1024,
1394         .num_mact_rows          = 2048,
1395         .num_ports              = 6,
1396         .num_tx_queues          = FELIX_NUM_TC,
1397         .switch_pci_bar         = 4,
1398         .imdio_pci_bar          = 0,
1399         .mdio_bus_alloc         = vsc9959_mdio_bus_alloc,
1400         .mdio_bus_free          = vsc9959_mdio_bus_free,
1401         .pcs_config             = vsc9959_pcs_config,
1402         .pcs_link_up            = vsc9959_pcs_link_up,
1403         .pcs_link_state         = vsc9959_pcs_link_state,
1404         .prevalidate_phy_mode   = vsc9959_prevalidate_phy_mode,
1405         .port_setup_tc          = vsc9959_port_setup_tc,
1406         .port_sched_speed_set   = vsc9959_sched_speed_set,
1407 };