2 * net/dsa/mv88e6xxx.c - Marvell 88e6xxx switch chip support
3 * Copyright (c) 2008 Marvell Semiconductor
5 * Copyright (c) 2015 CMC Electronics, Inc.
6 * Added support for VLAN Table Unit operations
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
14 #include <linux/delay.h>
15 #include <linux/etherdevice.h>
16 #include <linux/ethtool.h>
17 #include <linux/if_bridge.h>
18 #include <linux/jiffies.h>
19 #include <linux/list.h>
20 #include <linux/module.h>
21 #include <linux/netdevice.h>
22 #include <linux/gpio/consumer.h>
23 #include <linux/phy.h>
25 #include <net/switchdev.h>
26 #include "mv88e6xxx.h"
28 static void assert_smi_lock(struct dsa_switch *ds)
30 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
32 if (unlikely(!mutex_is_locked(&ps->smi_mutex))) {
33 dev_err(ds->master_dev, "SMI lock not held!\n");
38 /* If the switch's ADDR[4:0] strap pins are strapped to zero, it will
39 * use all 32 SMI bus addresses on its SMI bus, and all switch registers
40 * will be directly accessible on some {device address,register address}
41 * pair. If the ADDR[4:0] pins are not strapped to zero, the switch
42 * will only respond to SMI transactions to that specific address, and
43 * an indirect addressing mechanism needs to be used to access its
46 static int mv88e6xxx_reg_wait_ready(struct mii_bus *bus, int sw_addr)
51 for (i = 0; i < 16; i++) {
52 ret = mdiobus_read_nested(bus, sw_addr, SMI_CMD);
56 if ((ret & SMI_CMD_BUSY) == 0)
63 static int __mv88e6xxx_reg_read(struct mii_bus *bus, int sw_addr, int addr,
69 return mdiobus_read_nested(bus, addr, reg);
71 /* Wait for the bus to become free. */
72 ret = mv88e6xxx_reg_wait_ready(bus, sw_addr);
76 /* Transmit the read command. */
77 ret = mdiobus_write_nested(bus, sw_addr, SMI_CMD,
78 SMI_CMD_OP_22_READ | (addr << 5) | reg);
82 /* Wait for the read command to complete. */
83 ret = mv88e6xxx_reg_wait_ready(bus, sw_addr);
88 ret = mdiobus_read_nested(bus, sw_addr, SMI_DATA);
95 static int _mv88e6xxx_reg_read(struct dsa_switch *ds, int addr, int reg)
97 struct mii_bus *bus = dsa_host_dev_to_mii_bus(ds->master_dev);
105 ret = __mv88e6xxx_reg_read(bus, ds->pd->sw_addr, addr, reg);
109 dev_dbg(ds->master_dev, "<- addr: 0x%.2x reg: 0x%.2x val: 0x%.4x\n",
115 int mv88e6xxx_reg_read(struct dsa_switch *ds, int addr, int reg)
117 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
120 mutex_lock(&ps->smi_mutex);
121 ret = _mv88e6xxx_reg_read(ds, addr, reg);
122 mutex_unlock(&ps->smi_mutex);
127 static int __mv88e6xxx_reg_write(struct mii_bus *bus, int sw_addr, int addr,
133 return mdiobus_write_nested(bus, addr, reg, val);
135 /* Wait for the bus to become free. */
136 ret = mv88e6xxx_reg_wait_ready(bus, sw_addr);
140 /* Transmit the data to write. */
141 ret = mdiobus_write_nested(bus, sw_addr, SMI_DATA, val);
145 /* Transmit the write command. */
146 ret = mdiobus_write_nested(bus, sw_addr, SMI_CMD,
147 SMI_CMD_OP_22_WRITE | (addr << 5) | reg);
151 /* Wait for the write command to complete. */
152 ret = mv88e6xxx_reg_wait_ready(bus, sw_addr);
159 static int _mv88e6xxx_reg_write(struct dsa_switch *ds, int addr, int reg,
162 struct mii_bus *bus = dsa_host_dev_to_mii_bus(ds->master_dev);
169 dev_dbg(ds->master_dev, "-> addr: 0x%.2x reg: 0x%.2x val: 0x%.4x\n",
172 return __mv88e6xxx_reg_write(bus, ds->pd->sw_addr, addr, reg, val);
175 int mv88e6xxx_reg_write(struct dsa_switch *ds, int addr, int reg, u16 val)
177 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
180 mutex_lock(&ps->smi_mutex);
181 ret = _mv88e6xxx_reg_write(ds, addr, reg, val);
182 mutex_unlock(&ps->smi_mutex);
187 int mv88e6xxx_set_addr_direct(struct dsa_switch *ds, u8 *addr)
189 REG_WRITE(REG_GLOBAL, GLOBAL_MAC_01, (addr[0] << 8) | addr[1]);
190 REG_WRITE(REG_GLOBAL, GLOBAL_MAC_23, (addr[2] << 8) | addr[3]);
191 REG_WRITE(REG_GLOBAL, GLOBAL_MAC_45, (addr[4] << 8) | addr[5]);
196 int mv88e6xxx_set_addr_indirect(struct dsa_switch *ds, u8 *addr)
201 for (i = 0; i < 6; i++) {
204 /* Write the MAC address byte. */
205 REG_WRITE(REG_GLOBAL2, GLOBAL2_SWITCH_MAC,
206 GLOBAL2_SWITCH_MAC_BUSY | (i << 8) | addr[i]);
208 /* Wait for the write to complete. */
209 for (j = 0; j < 16; j++) {
210 ret = REG_READ(REG_GLOBAL2, GLOBAL2_SWITCH_MAC);
211 if ((ret & GLOBAL2_SWITCH_MAC_BUSY) == 0)
221 static int _mv88e6xxx_phy_read(struct dsa_switch *ds, int addr, int regnum)
224 return _mv88e6xxx_reg_read(ds, addr, regnum);
228 static int _mv88e6xxx_phy_write(struct dsa_switch *ds, int addr, int regnum,
232 return _mv88e6xxx_reg_write(ds, addr, regnum, val);
236 #ifdef CONFIG_NET_DSA_MV88E6XXX_NEED_PPU
237 static int mv88e6xxx_ppu_disable(struct dsa_switch *ds)
240 unsigned long timeout;
242 ret = REG_READ(REG_GLOBAL, GLOBAL_CONTROL);
243 REG_WRITE(REG_GLOBAL, GLOBAL_CONTROL,
244 ret & ~GLOBAL_CONTROL_PPU_ENABLE);
246 timeout = jiffies + 1 * HZ;
247 while (time_before(jiffies, timeout)) {
248 ret = REG_READ(REG_GLOBAL, GLOBAL_STATUS);
249 usleep_range(1000, 2000);
250 if ((ret & GLOBAL_STATUS_PPU_MASK) !=
251 GLOBAL_STATUS_PPU_POLLING)
258 static int mv88e6xxx_ppu_enable(struct dsa_switch *ds)
261 unsigned long timeout;
263 ret = REG_READ(REG_GLOBAL, GLOBAL_CONTROL);
264 REG_WRITE(REG_GLOBAL, GLOBAL_CONTROL, ret | GLOBAL_CONTROL_PPU_ENABLE);
266 timeout = jiffies + 1 * HZ;
267 while (time_before(jiffies, timeout)) {
268 ret = REG_READ(REG_GLOBAL, GLOBAL_STATUS);
269 usleep_range(1000, 2000);
270 if ((ret & GLOBAL_STATUS_PPU_MASK) ==
271 GLOBAL_STATUS_PPU_POLLING)
278 static void mv88e6xxx_ppu_reenable_work(struct work_struct *ugly)
280 struct mv88e6xxx_priv_state *ps;
282 ps = container_of(ugly, struct mv88e6xxx_priv_state, ppu_work);
283 if (mutex_trylock(&ps->ppu_mutex)) {
284 struct dsa_switch *ds = ((struct dsa_switch *)ps) - 1;
286 if (mv88e6xxx_ppu_enable(ds) == 0)
287 ps->ppu_disabled = 0;
288 mutex_unlock(&ps->ppu_mutex);
292 static void mv88e6xxx_ppu_reenable_timer(unsigned long _ps)
294 struct mv88e6xxx_priv_state *ps = (void *)_ps;
296 schedule_work(&ps->ppu_work);
299 static int mv88e6xxx_ppu_access_get(struct dsa_switch *ds)
301 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
304 mutex_lock(&ps->ppu_mutex);
306 /* If the PHY polling unit is enabled, disable it so that
307 * we can access the PHY registers. If it was already
308 * disabled, cancel the timer that is going to re-enable
311 if (!ps->ppu_disabled) {
312 ret = mv88e6xxx_ppu_disable(ds);
314 mutex_unlock(&ps->ppu_mutex);
317 ps->ppu_disabled = 1;
319 del_timer(&ps->ppu_timer);
326 static void mv88e6xxx_ppu_access_put(struct dsa_switch *ds)
328 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
330 /* Schedule a timer to re-enable the PHY polling unit. */
331 mod_timer(&ps->ppu_timer, jiffies + msecs_to_jiffies(10));
332 mutex_unlock(&ps->ppu_mutex);
335 void mv88e6xxx_ppu_state_init(struct dsa_switch *ds)
337 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
339 mutex_init(&ps->ppu_mutex);
340 INIT_WORK(&ps->ppu_work, mv88e6xxx_ppu_reenable_work);
341 init_timer(&ps->ppu_timer);
342 ps->ppu_timer.data = (unsigned long)ps;
343 ps->ppu_timer.function = mv88e6xxx_ppu_reenable_timer;
346 int mv88e6xxx_phy_read_ppu(struct dsa_switch *ds, int addr, int regnum)
350 ret = mv88e6xxx_ppu_access_get(ds);
352 ret = mv88e6xxx_reg_read(ds, addr, regnum);
353 mv88e6xxx_ppu_access_put(ds);
359 int mv88e6xxx_phy_write_ppu(struct dsa_switch *ds, int addr,
364 ret = mv88e6xxx_ppu_access_get(ds);
366 ret = mv88e6xxx_reg_write(ds, addr, regnum, val);
367 mv88e6xxx_ppu_access_put(ds);
374 static bool mv88e6xxx_6065_family(struct dsa_switch *ds)
376 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
379 case PORT_SWITCH_ID_6031:
380 case PORT_SWITCH_ID_6061:
381 case PORT_SWITCH_ID_6035:
382 case PORT_SWITCH_ID_6065:
388 static bool mv88e6xxx_6095_family(struct dsa_switch *ds)
390 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
393 case PORT_SWITCH_ID_6092:
394 case PORT_SWITCH_ID_6095:
400 static bool mv88e6xxx_6097_family(struct dsa_switch *ds)
402 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
405 case PORT_SWITCH_ID_6046:
406 case PORT_SWITCH_ID_6085:
407 case PORT_SWITCH_ID_6096:
408 case PORT_SWITCH_ID_6097:
414 static bool mv88e6xxx_6165_family(struct dsa_switch *ds)
416 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
419 case PORT_SWITCH_ID_6123:
420 case PORT_SWITCH_ID_6161:
421 case PORT_SWITCH_ID_6165:
427 static bool mv88e6xxx_6185_family(struct dsa_switch *ds)
429 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
432 case PORT_SWITCH_ID_6121:
433 case PORT_SWITCH_ID_6122:
434 case PORT_SWITCH_ID_6152:
435 case PORT_SWITCH_ID_6155:
436 case PORT_SWITCH_ID_6182:
437 case PORT_SWITCH_ID_6185:
438 case PORT_SWITCH_ID_6108:
439 case PORT_SWITCH_ID_6131:
445 static bool mv88e6xxx_6320_family(struct dsa_switch *ds)
447 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
450 case PORT_SWITCH_ID_6320:
451 case PORT_SWITCH_ID_6321:
457 static bool mv88e6xxx_6351_family(struct dsa_switch *ds)
459 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
462 case PORT_SWITCH_ID_6171:
463 case PORT_SWITCH_ID_6175:
464 case PORT_SWITCH_ID_6350:
465 case PORT_SWITCH_ID_6351:
471 static bool mv88e6xxx_6352_family(struct dsa_switch *ds)
473 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
476 case PORT_SWITCH_ID_6172:
477 case PORT_SWITCH_ID_6176:
478 case PORT_SWITCH_ID_6240:
479 case PORT_SWITCH_ID_6352:
485 /* We expect the switch to perform auto negotiation if there is a real
486 * phy. However, in the case of a fixed link phy, we force the port
487 * settings from the fixed link settings.
489 void mv88e6xxx_adjust_link(struct dsa_switch *ds, int port,
490 struct phy_device *phydev)
492 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
496 if (!phy_is_pseudo_fixed_link(phydev))
499 mutex_lock(&ps->smi_mutex);
501 ret = _mv88e6xxx_reg_read(ds, REG_PORT(port), PORT_PCS_CTRL);
505 reg = ret & ~(PORT_PCS_CTRL_LINK_UP |
506 PORT_PCS_CTRL_FORCE_LINK |
507 PORT_PCS_CTRL_DUPLEX_FULL |
508 PORT_PCS_CTRL_FORCE_DUPLEX |
509 PORT_PCS_CTRL_UNFORCED);
511 reg |= PORT_PCS_CTRL_FORCE_LINK;
513 reg |= PORT_PCS_CTRL_LINK_UP;
515 if (mv88e6xxx_6065_family(ds) && phydev->speed > SPEED_100)
518 switch (phydev->speed) {
520 reg |= PORT_PCS_CTRL_1000;
523 reg |= PORT_PCS_CTRL_100;
526 reg |= PORT_PCS_CTRL_10;
529 pr_info("Unknown speed");
533 reg |= PORT_PCS_CTRL_FORCE_DUPLEX;
534 if (phydev->duplex == DUPLEX_FULL)
535 reg |= PORT_PCS_CTRL_DUPLEX_FULL;
537 if ((mv88e6xxx_6352_family(ds) || mv88e6xxx_6351_family(ds)) &&
538 (port >= ps->num_ports - 2)) {
539 if (phydev->interface == PHY_INTERFACE_MODE_RGMII_RXID)
540 reg |= PORT_PCS_CTRL_RGMII_DELAY_RXCLK;
541 if (phydev->interface == PHY_INTERFACE_MODE_RGMII_TXID)
542 reg |= PORT_PCS_CTRL_RGMII_DELAY_TXCLK;
543 if (phydev->interface == PHY_INTERFACE_MODE_RGMII_ID)
544 reg |= (PORT_PCS_CTRL_RGMII_DELAY_RXCLK |
545 PORT_PCS_CTRL_RGMII_DELAY_TXCLK);
547 _mv88e6xxx_reg_write(ds, REG_PORT(port), PORT_PCS_CTRL, reg);
550 mutex_unlock(&ps->smi_mutex);
553 static int _mv88e6xxx_stats_wait(struct dsa_switch *ds)
558 for (i = 0; i < 10; i++) {
559 ret = _mv88e6xxx_reg_read(ds, REG_GLOBAL, GLOBAL_STATS_OP);
560 if ((ret & GLOBAL_STATS_OP_BUSY) == 0)
567 static int _mv88e6xxx_stats_snapshot(struct dsa_switch *ds, int port)
571 if (mv88e6xxx_6320_family(ds) || mv88e6xxx_6352_family(ds))
572 port = (port + 1) << 5;
574 /* Snapshot the hardware statistics counters for this port. */
575 ret = _mv88e6xxx_reg_write(ds, REG_GLOBAL, GLOBAL_STATS_OP,
576 GLOBAL_STATS_OP_CAPTURE_PORT |
577 GLOBAL_STATS_OP_HIST_RX_TX | port);
581 /* Wait for the snapshotting to complete. */
582 ret = _mv88e6xxx_stats_wait(ds);
589 static void _mv88e6xxx_stats_read(struct dsa_switch *ds, int stat, u32 *val)
596 ret = _mv88e6xxx_reg_write(ds, REG_GLOBAL, GLOBAL_STATS_OP,
597 GLOBAL_STATS_OP_READ_CAPTURED |
598 GLOBAL_STATS_OP_HIST_RX_TX | stat);
602 ret = _mv88e6xxx_stats_wait(ds);
606 ret = _mv88e6xxx_reg_read(ds, REG_GLOBAL, GLOBAL_STATS_COUNTER_32);
612 ret = _mv88e6xxx_reg_read(ds, REG_GLOBAL, GLOBAL_STATS_COUNTER_01);
619 static struct mv88e6xxx_hw_stat mv88e6xxx_hw_stats[] = {
620 { "in_good_octets", 8, 0x00, BANK0, },
621 { "in_bad_octets", 4, 0x02, BANK0, },
622 { "in_unicast", 4, 0x04, BANK0, },
623 { "in_broadcasts", 4, 0x06, BANK0, },
624 { "in_multicasts", 4, 0x07, BANK0, },
625 { "in_pause", 4, 0x16, BANK0, },
626 { "in_undersize", 4, 0x18, BANK0, },
627 { "in_fragments", 4, 0x19, BANK0, },
628 { "in_oversize", 4, 0x1a, BANK0, },
629 { "in_jabber", 4, 0x1b, BANK0, },
630 { "in_rx_error", 4, 0x1c, BANK0, },
631 { "in_fcs_error", 4, 0x1d, BANK0, },
632 { "out_octets", 8, 0x0e, BANK0, },
633 { "out_unicast", 4, 0x10, BANK0, },
634 { "out_broadcasts", 4, 0x13, BANK0, },
635 { "out_multicasts", 4, 0x12, BANK0, },
636 { "out_pause", 4, 0x15, BANK0, },
637 { "excessive", 4, 0x11, BANK0, },
638 { "collisions", 4, 0x1e, BANK0, },
639 { "deferred", 4, 0x05, BANK0, },
640 { "single", 4, 0x14, BANK0, },
641 { "multiple", 4, 0x17, BANK0, },
642 { "out_fcs_error", 4, 0x03, BANK0, },
643 { "late", 4, 0x1f, BANK0, },
644 { "hist_64bytes", 4, 0x08, BANK0, },
645 { "hist_65_127bytes", 4, 0x09, BANK0, },
646 { "hist_128_255bytes", 4, 0x0a, BANK0, },
647 { "hist_256_511bytes", 4, 0x0b, BANK0, },
648 { "hist_512_1023bytes", 4, 0x0c, BANK0, },
649 { "hist_1024_max_bytes", 4, 0x0d, BANK0, },
650 { "sw_in_discards", 4, 0x10, PORT, },
651 { "sw_in_filtered", 2, 0x12, PORT, },
652 { "sw_out_filtered", 2, 0x13, PORT, },
653 { "in_discards", 4, 0x00 | GLOBAL_STATS_OP_BANK_1, BANK1, },
654 { "in_filtered", 4, 0x01 | GLOBAL_STATS_OP_BANK_1, BANK1, },
655 { "in_accepted", 4, 0x02 | GLOBAL_STATS_OP_BANK_1, BANK1, },
656 { "in_bad_accepted", 4, 0x03 | GLOBAL_STATS_OP_BANK_1, BANK1, },
657 { "in_good_avb_class_a", 4, 0x04 | GLOBAL_STATS_OP_BANK_1, BANK1, },
658 { "in_good_avb_class_b", 4, 0x05 | GLOBAL_STATS_OP_BANK_1, BANK1, },
659 { "in_bad_avb_class_a", 4, 0x06 | GLOBAL_STATS_OP_BANK_1, BANK1, },
660 { "in_bad_avb_class_b", 4, 0x07 | GLOBAL_STATS_OP_BANK_1, BANK1, },
661 { "tcam_counter_0", 4, 0x08 | GLOBAL_STATS_OP_BANK_1, BANK1, },
662 { "tcam_counter_1", 4, 0x09 | GLOBAL_STATS_OP_BANK_1, BANK1, },
663 { "tcam_counter_2", 4, 0x0a | GLOBAL_STATS_OP_BANK_1, BANK1, },
664 { "tcam_counter_3", 4, 0x0b | GLOBAL_STATS_OP_BANK_1, BANK1, },
665 { "in_da_unknown", 4, 0x0e | GLOBAL_STATS_OP_BANK_1, BANK1, },
666 { "in_management", 4, 0x0f | GLOBAL_STATS_OP_BANK_1, BANK1, },
667 { "out_queue_0", 4, 0x10 | GLOBAL_STATS_OP_BANK_1, BANK1, },
668 { "out_queue_1", 4, 0x11 | GLOBAL_STATS_OP_BANK_1, BANK1, },
669 { "out_queue_2", 4, 0x12 | GLOBAL_STATS_OP_BANK_1, BANK1, },
670 { "out_queue_3", 4, 0x13 | GLOBAL_STATS_OP_BANK_1, BANK1, },
671 { "out_queue_4", 4, 0x14 | GLOBAL_STATS_OP_BANK_1, BANK1, },
672 { "out_queue_5", 4, 0x15 | GLOBAL_STATS_OP_BANK_1, BANK1, },
673 { "out_queue_6", 4, 0x16 | GLOBAL_STATS_OP_BANK_1, BANK1, },
674 { "out_queue_7", 4, 0x17 | GLOBAL_STATS_OP_BANK_1, BANK1, },
675 { "out_cut_through", 4, 0x18 | GLOBAL_STATS_OP_BANK_1, BANK1, },
676 { "out_octets_a", 4, 0x1a | GLOBAL_STATS_OP_BANK_1, BANK1, },
677 { "out_octets_b", 4, 0x1b | GLOBAL_STATS_OP_BANK_1, BANK1, },
678 { "out_management", 4, 0x1f | GLOBAL_STATS_OP_BANK_1, BANK1, },
681 static bool mv88e6xxx_has_stat(struct dsa_switch *ds,
682 struct mv88e6xxx_hw_stat *stat)
684 switch (stat->type) {
688 return mv88e6xxx_6320_family(ds);
690 return mv88e6xxx_6095_family(ds) ||
691 mv88e6xxx_6185_family(ds) ||
692 mv88e6xxx_6097_family(ds) ||
693 mv88e6xxx_6165_family(ds) ||
694 mv88e6xxx_6351_family(ds) ||
695 mv88e6xxx_6352_family(ds);
700 static uint64_t _mv88e6xxx_get_ethtool_stat(struct dsa_switch *ds,
701 struct mv88e6xxx_hw_stat *s,
711 ret = _mv88e6xxx_reg_read(ds, REG_PORT(port), s->reg);
716 if (s->sizeof_stat == 4) {
717 ret = _mv88e6xxx_reg_read(ds, REG_PORT(port),
726 _mv88e6xxx_stats_read(ds, s->reg, &low);
727 if (s->sizeof_stat == 8)
728 _mv88e6xxx_stats_read(ds, s->reg + 1, &high);
730 value = (((u64)high) << 16) | low;
734 void mv88e6xxx_get_strings(struct dsa_switch *ds, int port, uint8_t *data)
736 struct mv88e6xxx_hw_stat *stat;
739 for (i = 0, j = 0; i < ARRAY_SIZE(mv88e6xxx_hw_stats); i++) {
740 stat = &mv88e6xxx_hw_stats[i];
741 if (mv88e6xxx_has_stat(ds, stat)) {
742 memcpy(data + j * ETH_GSTRING_LEN, stat->string,
749 int mv88e6xxx_get_sset_count(struct dsa_switch *ds)
751 struct mv88e6xxx_hw_stat *stat;
754 for (i = 0, j = 0; i < ARRAY_SIZE(mv88e6xxx_hw_stats); i++) {
755 stat = &mv88e6xxx_hw_stats[i];
756 if (mv88e6xxx_has_stat(ds, stat))
763 mv88e6xxx_get_ethtool_stats(struct dsa_switch *ds,
764 int port, uint64_t *data)
766 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
767 struct mv88e6xxx_hw_stat *stat;
771 mutex_lock(&ps->smi_mutex);
773 ret = _mv88e6xxx_stats_snapshot(ds, port);
775 mutex_unlock(&ps->smi_mutex);
778 for (i = 0, j = 0; i < ARRAY_SIZE(mv88e6xxx_hw_stats); i++) {
779 stat = &mv88e6xxx_hw_stats[i];
780 if (mv88e6xxx_has_stat(ds, stat)) {
781 data[j] = _mv88e6xxx_get_ethtool_stat(ds, stat, port);
786 mutex_unlock(&ps->smi_mutex);
789 int mv88e6xxx_get_regs_len(struct dsa_switch *ds, int port)
791 return 32 * sizeof(u16);
794 void mv88e6xxx_get_regs(struct dsa_switch *ds, int port,
795 struct ethtool_regs *regs, void *_p)
802 memset(p, 0xff, 32 * sizeof(u16));
804 for (i = 0; i < 32; i++) {
807 ret = mv88e6xxx_reg_read(ds, REG_PORT(port), i);
813 static int _mv88e6xxx_wait(struct dsa_switch *ds, int reg, int offset,
816 unsigned long timeout = jiffies + HZ / 10;
818 while (time_before(jiffies, timeout)) {
821 ret = _mv88e6xxx_reg_read(ds, reg, offset);
827 usleep_range(1000, 2000);
832 static int mv88e6xxx_wait(struct dsa_switch *ds, int reg, int offset, u16 mask)
834 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
837 mutex_lock(&ps->smi_mutex);
838 ret = _mv88e6xxx_wait(ds, reg, offset, mask);
839 mutex_unlock(&ps->smi_mutex);
844 static int _mv88e6xxx_phy_wait(struct dsa_switch *ds)
846 return _mv88e6xxx_wait(ds, REG_GLOBAL2, GLOBAL2_SMI_OP,
847 GLOBAL2_SMI_OP_BUSY);
850 int mv88e6xxx_eeprom_load_wait(struct dsa_switch *ds)
852 return mv88e6xxx_wait(ds, REG_GLOBAL2, GLOBAL2_EEPROM_OP,
853 GLOBAL2_EEPROM_OP_LOAD);
856 int mv88e6xxx_eeprom_busy_wait(struct dsa_switch *ds)
858 return mv88e6xxx_wait(ds, REG_GLOBAL2, GLOBAL2_EEPROM_OP,
859 GLOBAL2_EEPROM_OP_BUSY);
862 static int _mv88e6xxx_atu_wait(struct dsa_switch *ds)
864 return _mv88e6xxx_wait(ds, REG_GLOBAL, GLOBAL_ATU_OP,
868 static int _mv88e6xxx_phy_read_indirect(struct dsa_switch *ds, int addr,
873 ret = _mv88e6xxx_reg_write(ds, REG_GLOBAL2, GLOBAL2_SMI_OP,
874 GLOBAL2_SMI_OP_22_READ | (addr << 5) |
879 ret = _mv88e6xxx_phy_wait(ds);
883 return _mv88e6xxx_reg_read(ds, REG_GLOBAL2, GLOBAL2_SMI_DATA);
886 static int _mv88e6xxx_phy_write_indirect(struct dsa_switch *ds, int addr,
891 ret = _mv88e6xxx_reg_write(ds, REG_GLOBAL2, GLOBAL2_SMI_DATA, val);
895 ret = _mv88e6xxx_reg_write(ds, REG_GLOBAL2, GLOBAL2_SMI_OP,
896 GLOBAL2_SMI_OP_22_WRITE | (addr << 5) |
899 return _mv88e6xxx_phy_wait(ds);
902 int mv88e6xxx_get_eee(struct dsa_switch *ds, int port, struct ethtool_eee *e)
904 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
907 mutex_lock(&ps->smi_mutex);
909 reg = _mv88e6xxx_phy_read_indirect(ds, port, 16);
913 e->eee_enabled = !!(reg & 0x0200);
914 e->tx_lpi_enabled = !!(reg & 0x0100);
916 reg = _mv88e6xxx_reg_read(ds, REG_PORT(port), PORT_STATUS);
920 e->eee_active = !!(reg & PORT_STATUS_EEE);
924 mutex_unlock(&ps->smi_mutex);
928 int mv88e6xxx_set_eee(struct dsa_switch *ds, int port,
929 struct phy_device *phydev, struct ethtool_eee *e)
931 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
935 mutex_lock(&ps->smi_mutex);
937 ret = _mv88e6xxx_phy_read_indirect(ds, port, 16);
944 if (e->tx_lpi_enabled)
947 ret = _mv88e6xxx_phy_write_indirect(ds, port, 16, reg);
949 mutex_unlock(&ps->smi_mutex);
954 static int _mv88e6xxx_atu_cmd(struct dsa_switch *ds, u16 cmd)
958 ret = _mv88e6xxx_reg_write(ds, REG_GLOBAL, GLOBAL_ATU_OP, cmd);
962 return _mv88e6xxx_atu_wait(ds);
965 static int _mv88e6xxx_atu_data_write(struct dsa_switch *ds,
966 struct mv88e6xxx_atu_entry *entry)
968 u16 data = entry->state & GLOBAL_ATU_DATA_STATE_MASK;
970 if (entry->state != GLOBAL_ATU_DATA_STATE_UNUSED) {
971 unsigned int mask, shift;
974 data |= GLOBAL_ATU_DATA_TRUNK;
975 mask = GLOBAL_ATU_DATA_TRUNK_ID_MASK;
976 shift = GLOBAL_ATU_DATA_TRUNK_ID_SHIFT;
978 mask = GLOBAL_ATU_DATA_PORT_VECTOR_MASK;
979 shift = GLOBAL_ATU_DATA_PORT_VECTOR_SHIFT;
982 data |= (entry->portv_trunkid << shift) & mask;
985 return _mv88e6xxx_reg_write(ds, REG_GLOBAL, GLOBAL_ATU_DATA, data);
988 static int _mv88e6xxx_atu_flush_move(struct dsa_switch *ds,
989 struct mv88e6xxx_atu_entry *entry,
995 err = _mv88e6xxx_atu_wait(ds);
999 err = _mv88e6xxx_atu_data_write(ds, entry);
1004 err = _mv88e6xxx_reg_write(ds, REG_GLOBAL, GLOBAL_ATU_FID,
1009 op = static_too ? GLOBAL_ATU_OP_FLUSH_MOVE_ALL_DB :
1010 GLOBAL_ATU_OP_FLUSH_MOVE_NON_STATIC_DB;
1012 op = static_too ? GLOBAL_ATU_OP_FLUSH_MOVE_ALL :
1013 GLOBAL_ATU_OP_FLUSH_MOVE_NON_STATIC;
1016 return _mv88e6xxx_atu_cmd(ds, op);
1019 static int _mv88e6xxx_atu_flush(struct dsa_switch *ds, u16 fid, bool static_too)
1021 struct mv88e6xxx_atu_entry entry = {
1023 .state = 0, /* EntryState bits must be 0 */
1026 return _mv88e6xxx_atu_flush_move(ds, &entry, static_too);
1029 static int _mv88e6xxx_atu_move(struct dsa_switch *ds, u16 fid, int from_port,
1030 int to_port, bool static_too)
1032 struct mv88e6xxx_atu_entry entry = {
1037 /* EntryState bits must be 0xF */
1038 entry.state = GLOBAL_ATU_DATA_STATE_MASK;
1040 /* ToPort and FromPort are respectively in PortVec bits 7:4 and 3:0 */
1041 entry.portv_trunkid = (to_port & 0x0f) << 4;
1042 entry.portv_trunkid |= from_port & 0x0f;
1044 return _mv88e6xxx_atu_flush_move(ds, &entry, static_too);
1047 static int _mv88e6xxx_atu_remove(struct dsa_switch *ds, u16 fid, int port,
1050 /* Destination port 0xF means remove the entries */
1051 return _mv88e6xxx_atu_move(ds, fid, port, 0x0f, static_too);
1054 static const char * const mv88e6xxx_port_state_names[] = {
1055 [PORT_CONTROL_STATE_DISABLED] = "Disabled",
1056 [PORT_CONTROL_STATE_BLOCKING] = "Blocking/Listening",
1057 [PORT_CONTROL_STATE_LEARNING] = "Learning",
1058 [PORT_CONTROL_STATE_FORWARDING] = "Forwarding",
1061 static int _mv88e6xxx_port_state(struct dsa_switch *ds, int port, u8 state)
1066 reg = _mv88e6xxx_reg_read(ds, REG_PORT(port), PORT_CONTROL);
1070 oldstate = reg & PORT_CONTROL_STATE_MASK;
1072 if (oldstate != state) {
1073 /* Flush forwarding database if we're moving a port
1074 * from Learning or Forwarding state to Disabled or
1075 * Blocking or Listening state.
1077 if ((oldstate == PORT_CONTROL_STATE_LEARNING ||
1078 oldstate == PORT_CONTROL_STATE_FORWARDING)
1079 && (state == PORT_CONTROL_STATE_DISABLED ||
1080 state == PORT_CONTROL_STATE_BLOCKING)) {
1081 ret = _mv88e6xxx_atu_remove(ds, 0, port, false);
1086 reg = (reg & ~PORT_CONTROL_STATE_MASK) | state;
1087 ret = _mv88e6xxx_reg_write(ds, REG_PORT(port), PORT_CONTROL,
1092 netdev_dbg(ds->ports[port], "PortState %s (was %s)\n",
1093 mv88e6xxx_port_state_names[state],
1094 mv88e6xxx_port_state_names[oldstate]);
1100 static int _mv88e6xxx_port_based_vlan_map(struct dsa_switch *ds, int port)
1102 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
1103 struct net_device *bridge = ps->ports[port].bridge_dev;
1104 const u16 mask = (1 << ps->num_ports) - 1;
1105 u16 output_ports = 0;
1109 /* allow CPU port or DSA link(s) to send frames to every port */
1110 if (dsa_is_cpu_port(ds, port) || dsa_is_dsa_port(ds, port)) {
1111 output_ports = mask;
1113 for (i = 0; i < ps->num_ports; ++i) {
1114 /* allow sending frames to every group member */
1115 if (bridge && ps->ports[i].bridge_dev == bridge)
1116 output_ports |= BIT(i);
1118 /* allow sending frames to CPU port and DSA link(s) */
1119 if (dsa_is_cpu_port(ds, i) || dsa_is_dsa_port(ds, i))
1120 output_ports |= BIT(i);
1124 /* prevent frames from going back out of the port they came in on */
1125 output_ports &= ~BIT(port);
1127 reg = _mv88e6xxx_reg_read(ds, REG_PORT(port), PORT_BASE_VLAN);
1132 reg |= output_ports & mask;
1134 return _mv88e6xxx_reg_write(ds, REG_PORT(port), PORT_BASE_VLAN, reg);
1137 int mv88e6xxx_port_stp_update(struct dsa_switch *ds, int port, u8 state)
1139 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
1143 case BR_STATE_DISABLED:
1144 stp_state = PORT_CONTROL_STATE_DISABLED;
1146 case BR_STATE_BLOCKING:
1147 case BR_STATE_LISTENING:
1148 stp_state = PORT_CONTROL_STATE_BLOCKING;
1150 case BR_STATE_LEARNING:
1151 stp_state = PORT_CONTROL_STATE_LEARNING;
1153 case BR_STATE_FORWARDING:
1155 stp_state = PORT_CONTROL_STATE_FORWARDING;
1159 /* mv88e6xxx_port_stp_update may be called with softirqs disabled,
1160 * so we can not update the port state directly but need to schedule it.
1162 ps->ports[port].state = stp_state;
1163 set_bit(port, ps->port_state_update_mask);
1164 schedule_work(&ps->bridge_work);
1169 static int _mv88e6xxx_port_pvid(struct dsa_switch *ds, int port, u16 *new,
1175 ret = _mv88e6xxx_reg_read(ds, REG_PORT(port), PORT_DEFAULT_VLAN);
1179 pvid = ret & PORT_DEFAULT_VLAN_MASK;
1182 ret &= ~PORT_DEFAULT_VLAN_MASK;
1183 ret |= *new & PORT_DEFAULT_VLAN_MASK;
1185 ret = _mv88e6xxx_reg_write(ds, REG_PORT(port),
1186 PORT_DEFAULT_VLAN, ret);
1190 netdev_dbg(ds->ports[port], "DefaultVID %d (was %d)\n", *new,
1200 static int _mv88e6xxx_port_pvid_get(struct dsa_switch *ds, int port, u16 *pvid)
1202 return _mv88e6xxx_port_pvid(ds, port, NULL, pvid);
1205 static int _mv88e6xxx_port_pvid_set(struct dsa_switch *ds, int port, u16 pvid)
1207 return _mv88e6xxx_port_pvid(ds, port, &pvid, NULL);
1210 static int _mv88e6xxx_vtu_wait(struct dsa_switch *ds)
1212 return _mv88e6xxx_wait(ds, REG_GLOBAL, GLOBAL_VTU_OP,
1213 GLOBAL_VTU_OP_BUSY);
1216 static int _mv88e6xxx_vtu_cmd(struct dsa_switch *ds, u16 op)
1220 ret = _mv88e6xxx_reg_write(ds, REG_GLOBAL, GLOBAL_VTU_OP, op);
1224 return _mv88e6xxx_vtu_wait(ds);
1227 static int _mv88e6xxx_vtu_stu_flush(struct dsa_switch *ds)
1231 ret = _mv88e6xxx_vtu_wait(ds);
1235 return _mv88e6xxx_vtu_cmd(ds, GLOBAL_VTU_OP_FLUSH_ALL);
1238 static int _mv88e6xxx_vtu_stu_data_read(struct dsa_switch *ds,
1239 struct mv88e6xxx_vtu_stu_entry *entry,
1240 unsigned int nibble_offset)
1242 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
1247 for (i = 0; i < 3; ++i) {
1248 ret = _mv88e6xxx_reg_read(ds, REG_GLOBAL,
1249 GLOBAL_VTU_DATA_0_3 + i);
1256 for (i = 0; i < ps->num_ports; ++i) {
1257 unsigned int shift = (i % 4) * 4 + nibble_offset;
1258 u16 reg = regs[i / 4];
1260 entry->data[i] = (reg >> shift) & GLOBAL_VTU_STU_DATA_MASK;
1266 static int _mv88e6xxx_vtu_stu_data_write(struct dsa_switch *ds,
1267 struct mv88e6xxx_vtu_stu_entry *entry,
1268 unsigned int nibble_offset)
1270 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
1271 u16 regs[3] = { 0 };
1275 for (i = 0; i < ps->num_ports; ++i) {
1276 unsigned int shift = (i % 4) * 4 + nibble_offset;
1277 u8 data = entry->data[i];
1279 regs[i / 4] |= (data & GLOBAL_VTU_STU_DATA_MASK) << shift;
1282 for (i = 0; i < 3; ++i) {
1283 ret = _mv88e6xxx_reg_write(ds, REG_GLOBAL,
1284 GLOBAL_VTU_DATA_0_3 + i, regs[i]);
1292 static int _mv88e6xxx_vtu_vid_write(struct dsa_switch *ds, u16 vid)
1294 return _mv88e6xxx_reg_write(ds, REG_GLOBAL, GLOBAL_VTU_VID,
1295 vid & GLOBAL_VTU_VID_MASK);
1298 static int _mv88e6xxx_vtu_getnext(struct dsa_switch *ds,
1299 struct mv88e6xxx_vtu_stu_entry *entry)
1301 struct mv88e6xxx_vtu_stu_entry next = { 0 };
1304 ret = _mv88e6xxx_vtu_wait(ds);
1308 ret = _mv88e6xxx_vtu_cmd(ds, GLOBAL_VTU_OP_VTU_GET_NEXT);
1312 ret = _mv88e6xxx_reg_read(ds, REG_GLOBAL, GLOBAL_VTU_VID);
1316 next.vid = ret & GLOBAL_VTU_VID_MASK;
1317 next.valid = !!(ret & GLOBAL_VTU_VID_VALID);
1320 ret = _mv88e6xxx_vtu_stu_data_read(ds, &next, 0);
1324 if (mv88e6xxx_6097_family(ds) || mv88e6xxx_6165_family(ds) ||
1325 mv88e6xxx_6351_family(ds) || mv88e6xxx_6352_family(ds)) {
1326 ret = _mv88e6xxx_reg_read(ds, REG_GLOBAL,
1331 next.fid = ret & GLOBAL_VTU_FID_MASK;
1333 ret = _mv88e6xxx_reg_read(ds, REG_GLOBAL,
1338 next.sid = ret & GLOBAL_VTU_SID_MASK;
1346 int mv88e6xxx_port_vlan_dump(struct dsa_switch *ds, int port,
1347 struct switchdev_obj_port_vlan *vlan,
1348 int (*cb)(struct switchdev_obj *obj))
1350 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
1351 struct mv88e6xxx_vtu_stu_entry next;
1355 mutex_lock(&ps->smi_mutex);
1357 err = _mv88e6xxx_port_pvid_get(ds, port, &pvid);
1361 err = _mv88e6xxx_vtu_vid_write(ds, GLOBAL_VTU_VID_MASK);
1366 err = _mv88e6xxx_vtu_getnext(ds, &next);
1373 if (next.data[port] == GLOBAL_VTU_DATA_MEMBER_TAG_NON_MEMBER)
1376 /* reinit and dump this VLAN obj */
1377 vlan->vid_begin = vlan->vid_end = next.vid;
1380 if (next.data[port] == GLOBAL_VTU_DATA_MEMBER_TAG_UNTAGGED)
1381 vlan->flags |= BRIDGE_VLAN_INFO_UNTAGGED;
1383 if (next.vid == pvid)
1384 vlan->flags |= BRIDGE_VLAN_INFO_PVID;
1386 err = cb(&vlan->obj);
1389 } while (next.vid < GLOBAL_VTU_VID_MASK);
1392 mutex_unlock(&ps->smi_mutex);
1397 static int _mv88e6xxx_vtu_loadpurge(struct dsa_switch *ds,
1398 struct mv88e6xxx_vtu_stu_entry *entry)
1403 ret = _mv88e6xxx_vtu_wait(ds);
1410 /* Write port member tags */
1411 ret = _mv88e6xxx_vtu_stu_data_write(ds, entry, 0);
1415 if (mv88e6xxx_6097_family(ds) || mv88e6xxx_6165_family(ds) ||
1416 mv88e6xxx_6351_family(ds) || mv88e6xxx_6352_family(ds)) {
1417 reg = entry->sid & GLOBAL_VTU_SID_MASK;
1418 ret = _mv88e6xxx_reg_write(ds, REG_GLOBAL, GLOBAL_VTU_SID, reg);
1422 reg = entry->fid & GLOBAL_VTU_FID_MASK;
1423 ret = _mv88e6xxx_reg_write(ds, REG_GLOBAL, GLOBAL_VTU_FID, reg);
1428 reg = GLOBAL_VTU_VID_VALID;
1430 reg |= entry->vid & GLOBAL_VTU_VID_MASK;
1431 ret = _mv88e6xxx_reg_write(ds, REG_GLOBAL, GLOBAL_VTU_VID, reg);
1435 return _mv88e6xxx_vtu_cmd(ds, GLOBAL_VTU_OP_VTU_LOAD_PURGE);
1438 static int _mv88e6xxx_stu_getnext(struct dsa_switch *ds, u8 sid,
1439 struct mv88e6xxx_vtu_stu_entry *entry)
1441 struct mv88e6xxx_vtu_stu_entry next = { 0 };
1444 ret = _mv88e6xxx_vtu_wait(ds);
1448 ret = _mv88e6xxx_reg_write(ds, REG_GLOBAL, GLOBAL_VTU_SID,
1449 sid & GLOBAL_VTU_SID_MASK);
1453 ret = _mv88e6xxx_vtu_cmd(ds, GLOBAL_VTU_OP_STU_GET_NEXT);
1457 ret = _mv88e6xxx_reg_read(ds, REG_GLOBAL, GLOBAL_VTU_SID);
1461 next.sid = ret & GLOBAL_VTU_SID_MASK;
1463 ret = _mv88e6xxx_reg_read(ds, REG_GLOBAL, GLOBAL_VTU_VID);
1467 next.valid = !!(ret & GLOBAL_VTU_VID_VALID);
1470 ret = _mv88e6xxx_vtu_stu_data_read(ds, &next, 2);
1479 static int _mv88e6xxx_stu_loadpurge(struct dsa_switch *ds,
1480 struct mv88e6xxx_vtu_stu_entry *entry)
1485 ret = _mv88e6xxx_vtu_wait(ds);
1492 /* Write port states */
1493 ret = _mv88e6xxx_vtu_stu_data_write(ds, entry, 2);
1497 reg = GLOBAL_VTU_VID_VALID;
1499 ret = _mv88e6xxx_reg_write(ds, REG_GLOBAL, GLOBAL_VTU_VID, reg);
1503 reg = entry->sid & GLOBAL_VTU_SID_MASK;
1504 ret = _mv88e6xxx_reg_write(ds, REG_GLOBAL, GLOBAL_VTU_SID, reg);
1508 return _mv88e6xxx_vtu_cmd(ds, GLOBAL_VTU_OP_STU_LOAD_PURGE);
1511 static int _mv88e6xxx_port_fid(struct dsa_switch *ds, int port, u16 *new,
1517 /* Port's default FID bits 3:0 are located in reg 0x06, offset 12 */
1518 ret = _mv88e6xxx_reg_read(ds, REG_PORT(port), PORT_BASE_VLAN);
1522 fid = (ret & PORT_BASE_VLAN_FID_3_0_MASK) >> 12;
1525 ret &= ~PORT_BASE_VLAN_FID_3_0_MASK;
1526 ret |= (*new << 12) & PORT_BASE_VLAN_FID_3_0_MASK;
1528 ret = _mv88e6xxx_reg_write(ds, REG_PORT(port), PORT_BASE_VLAN,
1534 /* Port's default FID bits 11:4 are located in reg 0x05, offset 0 */
1535 ret = _mv88e6xxx_reg_read(ds, REG_PORT(port), PORT_CONTROL_1);
1539 fid |= (ret & PORT_CONTROL_1_FID_11_4_MASK) << 4;
1542 ret &= ~PORT_CONTROL_1_FID_11_4_MASK;
1543 ret |= (*new >> 4) & PORT_CONTROL_1_FID_11_4_MASK;
1545 ret = _mv88e6xxx_reg_write(ds, REG_PORT(port), PORT_CONTROL_1,
1550 netdev_dbg(ds->ports[port], "FID %d (was %d)\n", *new, fid);
1559 static int _mv88e6xxx_port_fid_get(struct dsa_switch *ds, int port, u16 *fid)
1561 return _mv88e6xxx_port_fid(ds, port, NULL, fid);
1564 static int _mv88e6xxx_port_fid_set(struct dsa_switch *ds, int port, u16 fid)
1566 return _mv88e6xxx_port_fid(ds, port, &fid, NULL);
1569 static int _mv88e6xxx_fid_new(struct dsa_switch *ds, u16 *fid)
1571 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
1572 DECLARE_BITMAP(fid_bitmap, MV88E6XXX_N_FID);
1573 struct mv88e6xxx_vtu_stu_entry vlan;
1576 bitmap_zero(fid_bitmap, MV88E6XXX_N_FID);
1578 /* Set every FID bit used by the (un)bridged ports */
1579 for (i = 0; i < ps->num_ports; ++i) {
1580 err = _mv88e6xxx_port_fid_get(ds, i, fid);
1584 set_bit(*fid, fid_bitmap);
1587 /* Set every FID bit used by the VLAN entries */
1588 err = _mv88e6xxx_vtu_vid_write(ds, GLOBAL_VTU_VID_MASK);
1593 err = _mv88e6xxx_vtu_getnext(ds, &vlan);
1600 set_bit(vlan.fid, fid_bitmap);
1601 } while (vlan.vid < GLOBAL_VTU_VID_MASK);
1603 /* The reset value 0x000 is used to indicate that multiple address
1604 * databases are not needed. Return the next positive available.
1606 *fid = find_next_zero_bit(fid_bitmap, MV88E6XXX_N_FID, 1);
1607 if (unlikely(*fid == MV88E6XXX_N_FID))
1610 /* Clear the database */
1611 return _mv88e6xxx_atu_flush(ds, *fid, true);
1614 static int _mv88e6xxx_vtu_new(struct dsa_switch *ds, u16 vid,
1615 struct mv88e6xxx_vtu_stu_entry *entry)
1617 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
1618 struct mv88e6xxx_vtu_stu_entry vlan = {
1624 err = _mv88e6xxx_fid_new(ds, &vlan.fid);
1628 /* exclude all ports except the CPU and DSA ports */
1629 for (i = 0; i < ps->num_ports; ++i)
1630 vlan.data[i] = dsa_is_cpu_port(ds, i) || dsa_is_dsa_port(ds, i)
1631 ? GLOBAL_VTU_DATA_MEMBER_TAG_UNMODIFIED
1632 : GLOBAL_VTU_DATA_MEMBER_TAG_NON_MEMBER;
1634 if (mv88e6xxx_6097_family(ds) || mv88e6xxx_6165_family(ds) ||
1635 mv88e6xxx_6351_family(ds) || mv88e6xxx_6352_family(ds)) {
1636 struct mv88e6xxx_vtu_stu_entry vstp;
1638 /* Adding a VTU entry requires a valid STU entry. As VSTP is not
1639 * implemented, only one STU entry is needed to cover all VTU
1640 * entries. Thus, validate the SID 0.
1643 err = _mv88e6xxx_stu_getnext(ds, GLOBAL_VTU_SID_MASK, &vstp);
1647 if (vstp.sid != vlan.sid || !vstp.valid) {
1648 memset(&vstp, 0, sizeof(vstp));
1650 vstp.sid = vlan.sid;
1652 err = _mv88e6xxx_stu_loadpurge(ds, &vstp);
1662 static int _mv88e6xxx_vtu_get(struct dsa_switch *ds, u16 vid,
1663 struct mv88e6xxx_vtu_stu_entry *entry, bool creat)
1670 err = _mv88e6xxx_vtu_vid_write(ds, vid - 1);
1674 err = _mv88e6xxx_vtu_getnext(ds, entry);
1678 if (entry->vid != vid || !entry->valid) {
1681 /* -ENOENT would've been more appropriate, but switchdev expects
1682 * -EOPNOTSUPP to inform bridge about an eventual software VLAN.
1685 err = _mv88e6xxx_vtu_new(ds, vid, entry);
1691 static int mv88e6xxx_port_check_hw_vlan(struct dsa_switch *ds, int port,
1692 u16 vid_begin, u16 vid_end)
1694 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
1695 struct mv88e6xxx_vtu_stu_entry vlan;
1701 mutex_lock(&ps->smi_mutex);
1703 err = _mv88e6xxx_vtu_vid_write(ds, vid_begin - 1);
1708 err = _mv88e6xxx_vtu_getnext(ds, &vlan);
1715 if (vlan.vid > vid_end)
1718 for (i = 0; i < ps->num_ports; ++i) {
1719 if (dsa_is_dsa_port(ds, i) || dsa_is_cpu_port(ds, i))
1723 GLOBAL_VTU_DATA_MEMBER_TAG_NON_MEMBER)
1726 if (ps->ports[i].bridge_dev ==
1727 ps->ports[port].bridge_dev)
1728 break; /* same bridge, check next VLAN */
1730 netdev_warn(ds->ports[port],
1731 "hardware VLAN %d already used by %s\n",
1733 netdev_name(ps->ports[i].bridge_dev));
1737 } while (vlan.vid < vid_end);
1740 mutex_unlock(&ps->smi_mutex);
1745 static const char * const mv88e6xxx_port_8021q_mode_names[] = {
1746 [PORT_CONTROL_2_8021Q_DISABLED] = "Disabled",
1747 [PORT_CONTROL_2_8021Q_FALLBACK] = "Fallback",
1748 [PORT_CONTROL_2_8021Q_CHECK] = "Check",
1749 [PORT_CONTROL_2_8021Q_SECURE] = "Secure",
1752 int mv88e6xxx_port_vlan_filtering(struct dsa_switch *ds, int port,
1753 bool vlan_filtering)
1755 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
1756 u16 old, new = vlan_filtering ? PORT_CONTROL_2_8021Q_SECURE :
1757 PORT_CONTROL_2_8021Q_DISABLED;
1760 mutex_lock(&ps->smi_mutex);
1762 ret = _mv88e6xxx_reg_read(ds, REG_PORT(port), PORT_CONTROL_2);
1766 old = ret & PORT_CONTROL_2_8021Q_MASK;
1769 ret &= ~PORT_CONTROL_2_8021Q_MASK;
1770 ret |= new & PORT_CONTROL_2_8021Q_MASK;
1772 ret = _mv88e6xxx_reg_write(ds, REG_PORT(port), PORT_CONTROL_2,
1777 netdev_dbg(ds->ports[port], "802.1Q Mode %s (was %s)\n",
1778 mv88e6xxx_port_8021q_mode_names[new],
1779 mv88e6xxx_port_8021q_mode_names[old]);
1784 mutex_unlock(&ps->smi_mutex);
1789 int mv88e6xxx_port_vlan_prepare(struct dsa_switch *ds, int port,
1790 const struct switchdev_obj_port_vlan *vlan,
1791 struct switchdev_trans *trans)
1795 /* If the requested port doesn't belong to the same bridge as the VLAN
1796 * members, do not support it (yet) and fallback to software VLAN.
1798 err = mv88e6xxx_port_check_hw_vlan(ds, port, vlan->vid_begin,
1803 /* We don't need any dynamic resource from the kernel (yet),
1804 * so skip the prepare phase.
1809 static int _mv88e6xxx_port_vlan_add(struct dsa_switch *ds, int port, u16 vid,
1812 struct mv88e6xxx_vtu_stu_entry vlan;
1815 err = _mv88e6xxx_vtu_get(ds, vid, &vlan, true);
1819 vlan.data[port] = untagged ?
1820 GLOBAL_VTU_DATA_MEMBER_TAG_UNTAGGED :
1821 GLOBAL_VTU_DATA_MEMBER_TAG_TAGGED;
1823 return _mv88e6xxx_vtu_loadpurge(ds, &vlan);
1826 int mv88e6xxx_port_vlan_add(struct dsa_switch *ds, int port,
1827 const struct switchdev_obj_port_vlan *vlan,
1828 struct switchdev_trans *trans)
1830 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
1831 bool untagged = vlan->flags & BRIDGE_VLAN_INFO_UNTAGGED;
1832 bool pvid = vlan->flags & BRIDGE_VLAN_INFO_PVID;
1836 mutex_lock(&ps->smi_mutex);
1838 for (vid = vlan->vid_begin; vid <= vlan->vid_end; ++vid) {
1839 err = _mv88e6xxx_port_vlan_add(ds, port, vid, untagged);
1844 /* no PVID with ranges, otherwise it's a bug */
1846 err = _mv88e6xxx_port_pvid_set(ds, port, vlan->vid_end);
1848 mutex_unlock(&ps->smi_mutex);
1853 static int _mv88e6xxx_port_vlan_del(struct dsa_switch *ds, int port, u16 vid)
1855 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
1856 struct mv88e6xxx_vtu_stu_entry vlan;
1859 err = _mv88e6xxx_vtu_get(ds, vid, &vlan, false);
1863 /* Tell switchdev if this VLAN is handled in software */
1864 if (vlan.data[port] == GLOBAL_VTU_DATA_MEMBER_TAG_NON_MEMBER)
1867 vlan.data[port] = GLOBAL_VTU_DATA_MEMBER_TAG_NON_MEMBER;
1869 /* keep the VLAN unless all ports are excluded */
1871 for (i = 0; i < ps->num_ports; ++i) {
1872 if (dsa_is_cpu_port(ds, i) || dsa_is_dsa_port(ds, i))
1875 if (vlan.data[i] != GLOBAL_VTU_DATA_MEMBER_TAG_NON_MEMBER) {
1881 err = _mv88e6xxx_vtu_loadpurge(ds, &vlan);
1885 return _mv88e6xxx_atu_remove(ds, vlan.fid, port, false);
1888 int mv88e6xxx_port_vlan_del(struct dsa_switch *ds, int port,
1889 const struct switchdev_obj_port_vlan *vlan)
1891 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
1895 mutex_lock(&ps->smi_mutex);
1897 err = _mv88e6xxx_port_pvid_get(ds, port, &pvid);
1901 for (vid = vlan->vid_begin; vid <= vlan->vid_end; ++vid) {
1902 err = _mv88e6xxx_port_vlan_del(ds, port, vid);
1907 err = _mv88e6xxx_port_pvid_set(ds, port, 0);
1914 mutex_unlock(&ps->smi_mutex);
1919 static int _mv88e6xxx_atu_mac_write(struct dsa_switch *ds,
1920 const unsigned char *addr)
1924 for (i = 0; i < 3; i++) {
1925 ret = _mv88e6xxx_reg_write(
1926 ds, REG_GLOBAL, GLOBAL_ATU_MAC_01 + i,
1927 (addr[i * 2] << 8) | addr[i * 2 + 1]);
1935 static int _mv88e6xxx_atu_mac_read(struct dsa_switch *ds, unsigned char *addr)
1939 for (i = 0; i < 3; i++) {
1940 ret = _mv88e6xxx_reg_read(ds, REG_GLOBAL,
1941 GLOBAL_ATU_MAC_01 + i);
1944 addr[i * 2] = ret >> 8;
1945 addr[i * 2 + 1] = ret & 0xff;
1951 static int _mv88e6xxx_atu_load(struct dsa_switch *ds,
1952 struct mv88e6xxx_atu_entry *entry)
1956 ret = _mv88e6xxx_atu_wait(ds);
1960 ret = _mv88e6xxx_atu_mac_write(ds, entry->mac);
1964 ret = _mv88e6xxx_atu_data_write(ds, entry);
1968 ret = _mv88e6xxx_reg_write(ds, REG_GLOBAL, GLOBAL_ATU_FID, entry->fid);
1972 return _mv88e6xxx_atu_cmd(ds, GLOBAL_ATU_OP_LOAD_DB);
1975 static int _mv88e6xxx_port_fdb_load(struct dsa_switch *ds, int port,
1976 const unsigned char *addr, u16 vid,
1979 struct mv88e6xxx_atu_entry entry = { 0 };
1980 struct mv88e6xxx_vtu_stu_entry vlan;
1983 /* Null VLAN ID corresponds to the port private database */
1985 err = _mv88e6xxx_port_fid_get(ds, port, &vlan.fid);
1987 err = _mv88e6xxx_vtu_get(ds, vid, &vlan, false);
1991 entry.fid = vlan.fid;
1992 entry.state = state;
1993 ether_addr_copy(entry.mac, addr);
1994 if (state != GLOBAL_ATU_DATA_STATE_UNUSED) {
1995 entry.trunk = false;
1996 entry.portv_trunkid = BIT(port);
1999 return _mv88e6xxx_atu_load(ds, &entry);
2002 int mv88e6xxx_port_fdb_prepare(struct dsa_switch *ds, int port,
2003 const struct switchdev_obj_port_fdb *fdb,
2004 struct switchdev_trans *trans)
2006 /* We don't need any dynamic resource from the kernel (yet),
2007 * so skip the prepare phase.
2012 int mv88e6xxx_port_fdb_add(struct dsa_switch *ds, int port,
2013 const struct switchdev_obj_port_fdb *fdb,
2014 struct switchdev_trans *trans)
2016 int state = is_multicast_ether_addr(fdb->addr) ?
2017 GLOBAL_ATU_DATA_STATE_MC_STATIC :
2018 GLOBAL_ATU_DATA_STATE_UC_STATIC;
2019 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
2022 mutex_lock(&ps->smi_mutex);
2023 ret = _mv88e6xxx_port_fdb_load(ds, port, fdb->addr, fdb->vid, state);
2024 mutex_unlock(&ps->smi_mutex);
2029 int mv88e6xxx_port_fdb_del(struct dsa_switch *ds, int port,
2030 const struct switchdev_obj_port_fdb *fdb)
2032 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
2035 mutex_lock(&ps->smi_mutex);
2036 ret = _mv88e6xxx_port_fdb_load(ds, port, fdb->addr, fdb->vid,
2037 GLOBAL_ATU_DATA_STATE_UNUSED);
2038 mutex_unlock(&ps->smi_mutex);
2043 static int _mv88e6xxx_atu_getnext(struct dsa_switch *ds, u16 fid,
2044 struct mv88e6xxx_atu_entry *entry)
2046 struct mv88e6xxx_atu_entry next = { 0 };
2051 ret = _mv88e6xxx_atu_wait(ds);
2055 ret = _mv88e6xxx_reg_write(ds, REG_GLOBAL, GLOBAL_ATU_FID, fid);
2059 ret = _mv88e6xxx_atu_cmd(ds, GLOBAL_ATU_OP_GET_NEXT_DB);
2063 ret = _mv88e6xxx_atu_mac_read(ds, next.mac);
2067 ret = _mv88e6xxx_reg_read(ds, REG_GLOBAL, GLOBAL_ATU_DATA);
2071 next.state = ret & GLOBAL_ATU_DATA_STATE_MASK;
2072 if (next.state != GLOBAL_ATU_DATA_STATE_UNUSED) {
2073 unsigned int mask, shift;
2075 if (ret & GLOBAL_ATU_DATA_TRUNK) {
2077 mask = GLOBAL_ATU_DATA_TRUNK_ID_MASK;
2078 shift = GLOBAL_ATU_DATA_TRUNK_ID_SHIFT;
2081 mask = GLOBAL_ATU_DATA_PORT_VECTOR_MASK;
2082 shift = GLOBAL_ATU_DATA_PORT_VECTOR_SHIFT;
2085 next.portv_trunkid = (ret & mask) >> shift;
2092 static int _mv88e6xxx_port_fdb_dump_one(struct dsa_switch *ds, u16 fid, u16 vid,
2094 struct switchdev_obj_port_fdb *fdb,
2095 int (*cb)(struct switchdev_obj *obj))
2097 struct mv88e6xxx_atu_entry addr = {
2098 .mac = { 0xff, 0xff, 0xff, 0xff, 0xff, 0xff },
2102 err = _mv88e6xxx_atu_mac_write(ds, addr.mac);
2107 err = _mv88e6xxx_atu_getnext(ds, fid, &addr);
2111 if (addr.state == GLOBAL_ATU_DATA_STATE_UNUSED)
2114 if (!addr.trunk && addr.portv_trunkid & BIT(port)) {
2115 bool is_static = addr.state ==
2116 (is_multicast_ether_addr(addr.mac) ?
2117 GLOBAL_ATU_DATA_STATE_MC_STATIC :
2118 GLOBAL_ATU_DATA_STATE_UC_STATIC);
2121 ether_addr_copy(fdb->addr, addr.mac);
2122 fdb->ndm_state = is_static ? NUD_NOARP : NUD_REACHABLE;
2124 err = cb(&fdb->obj);
2128 } while (!is_broadcast_ether_addr(addr.mac));
2133 int mv88e6xxx_port_fdb_dump(struct dsa_switch *ds, int port,
2134 struct switchdev_obj_port_fdb *fdb,
2135 int (*cb)(struct switchdev_obj *obj))
2137 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
2138 struct mv88e6xxx_vtu_stu_entry vlan = {
2139 .vid = GLOBAL_VTU_VID_MASK, /* all ones */
2144 mutex_lock(&ps->smi_mutex);
2146 /* Dump port's default Filtering Information Database (VLAN ID 0) */
2147 err = _mv88e6xxx_port_fid_get(ds, port, &fid);
2151 err = _mv88e6xxx_port_fdb_dump_one(ds, fid, 0, port, fdb, cb);
2155 /* Dump VLANs' Filtering Information Databases */
2156 err = _mv88e6xxx_vtu_vid_write(ds, vlan.vid);
2161 err = _mv88e6xxx_vtu_getnext(ds, &vlan);
2168 err = _mv88e6xxx_port_fdb_dump_one(ds, vlan.fid, vlan.vid, port,
2172 } while (vlan.vid < GLOBAL_VTU_VID_MASK);
2175 mutex_unlock(&ps->smi_mutex);
2180 int mv88e6xxx_port_bridge_join(struct dsa_switch *ds, int port,
2181 struct net_device *bridge)
2183 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
2186 mutex_lock(&ps->smi_mutex);
2188 /* Assign the bridge and remap each port's VLANTable */
2189 ps->ports[port].bridge_dev = bridge;
2191 for (i = 0; i < ps->num_ports; ++i) {
2192 if (ps->ports[i].bridge_dev == bridge) {
2193 err = _mv88e6xxx_port_based_vlan_map(ds, i);
2199 mutex_unlock(&ps->smi_mutex);
2204 void mv88e6xxx_port_bridge_leave(struct dsa_switch *ds, int port)
2206 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
2207 struct net_device *bridge = ps->ports[port].bridge_dev;
2210 mutex_lock(&ps->smi_mutex);
2212 /* Unassign the bridge and remap each port's VLANTable */
2213 ps->ports[port].bridge_dev = NULL;
2215 for (i = 0; i < ps->num_ports; ++i)
2216 if (i == port || ps->ports[i].bridge_dev == bridge)
2217 if (_mv88e6xxx_port_based_vlan_map(ds, i))
2218 netdev_warn(ds->ports[i], "failed to remap\n");
2220 mutex_unlock(&ps->smi_mutex);
2223 static void mv88e6xxx_bridge_work(struct work_struct *work)
2225 struct mv88e6xxx_priv_state *ps;
2226 struct dsa_switch *ds;
2229 ps = container_of(work, struct mv88e6xxx_priv_state, bridge_work);
2230 ds = ((struct dsa_switch *)ps) - 1;
2232 mutex_lock(&ps->smi_mutex);
2234 for (port = 0; port < ps->num_ports; ++port)
2235 if (test_and_clear_bit(port, ps->port_state_update_mask) &&
2236 _mv88e6xxx_port_state(ds, port, ps->ports[port].state))
2237 netdev_warn(ds->ports[port], "failed to update state to %s\n",
2238 mv88e6xxx_port_state_names[ps->ports[port].state]);
2240 mutex_unlock(&ps->smi_mutex);
2243 static int _mv88e6xxx_phy_page_write(struct dsa_switch *ds, int port, int page,
2248 ret = _mv88e6xxx_phy_write_indirect(ds, port, 0x16, page);
2250 goto restore_page_0;
2252 ret = _mv88e6xxx_phy_write_indirect(ds, port, reg, val);
2254 _mv88e6xxx_phy_write_indirect(ds, port, 0x16, 0x0);
2259 static int _mv88e6xxx_phy_page_read(struct dsa_switch *ds, int port, int page,
2264 ret = _mv88e6xxx_phy_write_indirect(ds, port, 0x16, page);
2266 goto restore_page_0;
2268 ret = _mv88e6xxx_phy_read_indirect(ds, port, reg);
2270 _mv88e6xxx_phy_write_indirect(ds, port, 0x16, 0x0);
2275 static int mv88e6xxx_power_on_serdes(struct dsa_switch *ds)
2279 ret = _mv88e6xxx_phy_page_read(ds, REG_FIBER_SERDES, PAGE_FIBER_SERDES,
2284 if (ret & BMCR_PDOWN) {
2286 ret = _mv88e6xxx_phy_page_write(ds, REG_FIBER_SERDES,
2287 PAGE_FIBER_SERDES, MII_BMCR,
2294 static int mv88e6xxx_setup_port(struct dsa_switch *ds, int port)
2296 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
2300 mutex_lock(&ps->smi_mutex);
2302 if (mv88e6xxx_6352_family(ds) || mv88e6xxx_6351_family(ds) ||
2303 mv88e6xxx_6165_family(ds) || mv88e6xxx_6097_family(ds) ||
2304 mv88e6xxx_6185_family(ds) || mv88e6xxx_6095_family(ds) ||
2305 mv88e6xxx_6065_family(ds) || mv88e6xxx_6320_family(ds)) {
2306 /* MAC Forcing register: don't force link, speed,
2307 * duplex or flow control state to any particular
2308 * values on physical ports, but force the CPU port
2309 * and all DSA ports to their maximum bandwidth and
2312 reg = _mv88e6xxx_reg_read(ds, REG_PORT(port), PORT_PCS_CTRL);
2313 if (dsa_is_cpu_port(ds, port) || dsa_is_dsa_port(ds, port)) {
2314 reg &= ~PORT_PCS_CTRL_UNFORCED;
2315 reg |= PORT_PCS_CTRL_FORCE_LINK |
2316 PORT_PCS_CTRL_LINK_UP |
2317 PORT_PCS_CTRL_DUPLEX_FULL |
2318 PORT_PCS_CTRL_FORCE_DUPLEX;
2319 if (mv88e6xxx_6065_family(ds))
2320 reg |= PORT_PCS_CTRL_100;
2322 reg |= PORT_PCS_CTRL_1000;
2324 reg |= PORT_PCS_CTRL_UNFORCED;
2327 ret = _mv88e6xxx_reg_write(ds, REG_PORT(port),
2328 PORT_PCS_CTRL, reg);
2333 /* Port Control: disable Drop-on-Unlock, disable Drop-on-Lock,
2334 * disable Header mode, enable IGMP/MLD snooping, disable VLAN
2335 * tunneling, determine priority by looking at 802.1p and IP
2336 * priority fields (IP prio has precedence), and set STP state
2339 * If this is the CPU link, use DSA or EDSA tagging depending
2340 * on which tagging mode was configured.
2342 * If this is a link to another switch, use DSA tagging mode.
2344 * If this is the upstream port for this switch, enable
2345 * forwarding of unknown unicasts and multicasts.
2348 if (mv88e6xxx_6352_family(ds) || mv88e6xxx_6351_family(ds) ||
2349 mv88e6xxx_6165_family(ds) || mv88e6xxx_6097_family(ds) ||
2350 mv88e6xxx_6095_family(ds) || mv88e6xxx_6065_family(ds) ||
2351 mv88e6xxx_6185_family(ds) || mv88e6xxx_6320_family(ds))
2352 reg = PORT_CONTROL_IGMP_MLD_SNOOP |
2353 PORT_CONTROL_USE_TAG | PORT_CONTROL_USE_IP |
2354 PORT_CONTROL_STATE_FORWARDING;
2355 if (dsa_is_cpu_port(ds, port)) {
2356 if (mv88e6xxx_6095_family(ds) || mv88e6xxx_6185_family(ds))
2357 reg |= PORT_CONTROL_DSA_TAG;
2358 if (mv88e6xxx_6352_family(ds) || mv88e6xxx_6351_family(ds) ||
2359 mv88e6xxx_6165_family(ds) || mv88e6xxx_6097_family(ds) ||
2360 mv88e6xxx_6320_family(ds)) {
2361 if (ds->dst->tag_protocol == DSA_TAG_PROTO_EDSA)
2362 reg |= PORT_CONTROL_FRAME_ETHER_TYPE_DSA;
2364 reg |= PORT_CONTROL_FRAME_MODE_DSA;
2365 reg |= PORT_CONTROL_FORWARD_UNKNOWN |
2366 PORT_CONTROL_FORWARD_UNKNOWN_MC;
2369 if (mv88e6xxx_6352_family(ds) || mv88e6xxx_6351_family(ds) ||
2370 mv88e6xxx_6165_family(ds) || mv88e6xxx_6097_family(ds) ||
2371 mv88e6xxx_6095_family(ds) || mv88e6xxx_6065_family(ds) ||
2372 mv88e6xxx_6185_family(ds) || mv88e6xxx_6320_family(ds)) {
2373 if (ds->dst->tag_protocol == DSA_TAG_PROTO_EDSA)
2374 reg |= PORT_CONTROL_EGRESS_ADD_TAG;
2377 if (dsa_is_dsa_port(ds, port)) {
2378 if (mv88e6xxx_6095_family(ds) || mv88e6xxx_6185_family(ds))
2379 reg |= PORT_CONTROL_DSA_TAG;
2380 if (mv88e6xxx_6352_family(ds) || mv88e6xxx_6351_family(ds) ||
2381 mv88e6xxx_6165_family(ds) || mv88e6xxx_6097_family(ds) ||
2382 mv88e6xxx_6320_family(ds)) {
2383 reg |= PORT_CONTROL_FRAME_MODE_DSA;
2386 if (port == dsa_upstream_port(ds))
2387 reg |= PORT_CONTROL_FORWARD_UNKNOWN |
2388 PORT_CONTROL_FORWARD_UNKNOWN_MC;
2391 ret = _mv88e6xxx_reg_write(ds, REG_PORT(port),
2397 /* If this port is connected to a SerDes, make sure the SerDes is not
2400 if (mv88e6xxx_6352_family(ds)) {
2401 ret = _mv88e6xxx_reg_read(ds, REG_PORT(port), PORT_STATUS);
2404 ret &= PORT_STATUS_CMODE_MASK;
2405 if ((ret == PORT_STATUS_CMODE_100BASE_X) ||
2406 (ret == PORT_STATUS_CMODE_1000BASE_X) ||
2407 (ret == PORT_STATUS_CMODE_SGMII)) {
2408 ret = mv88e6xxx_power_on_serdes(ds);
2414 /* Port Control 2: don't force a good FCS, set the maximum frame size to
2415 * 10240 bytes, disable 802.1q tags checking, don't discard tagged or
2416 * untagged frames on this port, do a destination address lookup on all
2417 * received packets as usual, disable ARP mirroring and don't send a
2418 * copy of all transmitted/received frames on this port to the CPU.
2421 if (mv88e6xxx_6352_family(ds) || mv88e6xxx_6351_family(ds) ||
2422 mv88e6xxx_6165_family(ds) || mv88e6xxx_6097_family(ds) ||
2423 mv88e6xxx_6095_family(ds) || mv88e6xxx_6320_family(ds))
2424 reg = PORT_CONTROL_2_MAP_DA;
2426 if (mv88e6xxx_6352_family(ds) || mv88e6xxx_6351_family(ds) ||
2427 mv88e6xxx_6165_family(ds) || mv88e6xxx_6320_family(ds))
2428 reg |= PORT_CONTROL_2_JUMBO_10240;
2430 if (mv88e6xxx_6095_family(ds) || mv88e6xxx_6185_family(ds)) {
2431 /* Set the upstream port this port should use */
2432 reg |= dsa_upstream_port(ds);
2433 /* enable forwarding of unknown multicast addresses to
2436 if (port == dsa_upstream_port(ds))
2437 reg |= PORT_CONTROL_2_FORWARD_UNKNOWN;
2440 reg |= PORT_CONTROL_2_8021Q_DISABLED;
2443 ret = _mv88e6xxx_reg_write(ds, REG_PORT(port),
2444 PORT_CONTROL_2, reg);
2449 /* Port Association Vector: when learning source addresses
2450 * of packets, add the address to the address database using
2451 * a port bitmap that has only the bit for this port set and
2452 * the other bits clear.
2455 /* Disable learning for CPU port */
2456 if (dsa_is_cpu_port(ds, port))
2459 ret = _mv88e6xxx_reg_write(ds, REG_PORT(port), PORT_ASSOC_VECTOR, reg);
2463 /* Egress rate control 2: disable egress rate control. */
2464 ret = _mv88e6xxx_reg_write(ds, REG_PORT(port), PORT_RATE_CONTROL_2,
2469 if (mv88e6xxx_6352_family(ds) || mv88e6xxx_6351_family(ds) ||
2470 mv88e6xxx_6165_family(ds) || mv88e6xxx_6097_family(ds) ||
2471 mv88e6xxx_6320_family(ds)) {
2472 /* Do not limit the period of time that this port can
2473 * be paused for by the remote end or the period of
2474 * time that this port can pause the remote end.
2476 ret = _mv88e6xxx_reg_write(ds, REG_PORT(port),
2477 PORT_PAUSE_CTRL, 0x0000);
2481 /* Port ATU control: disable limiting the number of
2482 * address database entries that this port is allowed
2485 ret = _mv88e6xxx_reg_write(ds, REG_PORT(port),
2486 PORT_ATU_CONTROL, 0x0000);
2487 /* Priority Override: disable DA, SA and VTU priority
2490 ret = _mv88e6xxx_reg_write(ds, REG_PORT(port),
2491 PORT_PRI_OVERRIDE, 0x0000);
2495 /* Port Ethertype: use the Ethertype DSA Ethertype
2498 ret = _mv88e6xxx_reg_write(ds, REG_PORT(port),
2499 PORT_ETH_TYPE, ETH_P_EDSA);
2502 /* Tag Remap: use an identity 802.1p prio -> switch
2505 ret = _mv88e6xxx_reg_write(ds, REG_PORT(port),
2506 PORT_TAG_REGMAP_0123, 0x3210);
2510 /* Tag Remap 2: use an identity 802.1p prio -> switch
2513 ret = _mv88e6xxx_reg_write(ds, REG_PORT(port),
2514 PORT_TAG_REGMAP_4567, 0x7654);
2519 if (mv88e6xxx_6352_family(ds) || mv88e6xxx_6351_family(ds) ||
2520 mv88e6xxx_6165_family(ds) || mv88e6xxx_6097_family(ds) ||
2521 mv88e6xxx_6185_family(ds) || mv88e6xxx_6095_family(ds) ||
2522 mv88e6xxx_6320_family(ds)) {
2523 /* Rate Control: disable ingress rate limiting. */
2524 ret = _mv88e6xxx_reg_write(ds, REG_PORT(port),
2525 PORT_RATE_CONTROL, 0x0001);
2530 /* Port Control 1: disable trunking, disable sending
2531 * learning messages to this port.
2533 ret = _mv88e6xxx_reg_write(ds, REG_PORT(port), PORT_CONTROL_1, 0x0000);
2537 /* Port based VLAN map: give each port the same default address
2538 * database, and allow bidirectional communication between the
2539 * CPU and DSA port(s), and the other ports.
2541 ret = _mv88e6xxx_port_fid_set(ds, port, 0);
2545 ret = _mv88e6xxx_port_based_vlan_map(ds, port);
2549 /* Default VLAN ID and priority: don't set a default VLAN
2550 * ID, and set the default packet priority to zero.
2552 ret = _mv88e6xxx_reg_write(ds, REG_PORT(port), PORT_DEFAULT_VLAN,
2555 mutex_unlock(&ps->smi_mutex);
2559 int mv88e6xxx_setup_ports(struct dsa_switch *ds)
2561 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
2565 for (i = 0; i < ps->num_ports; i++) {
2566 ret = mv88e6xxx_setup_port(ds, i);
2573 int mv88e6xxx_setup_common(struct dsa_switch *ds)
2575 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
2577 mutex_init(&ps->smi_mutex);
2579 ps->id = REG_READ(REG_PORT(0), PORT_SWITCH_ID) & 0xfff0;
2581 INIT_WORK(&ps->bridge_work, mv88e6xxx_bridge_work);
2586 int mv88e6xxx_setup_global(struct dsa_switch *ds)
2588 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
2592 /* Set the default address aging time to 5 minutes, and
2593 * enable address learn messages to be sent to all message
2596 REG_WRITE(REG_GLOBAL, GLOBAL_ATU_CONTROL,
2597 0x0140 | GLOBAL_ATU_CONTROL_LEARN2ALL);
2599 /* Configure the IP ToS mapping registers. */
2600 REG_WRITE(REG_GLOBAL, GLOBAL_IP_PRI_0, 0x0000);
2601 REG_WRITE(REG_GLOBAL, GLOBAL_IP_PRI_1, 0x0000);
2602 REG_WRITE(REG_GLOBAL, GLOBAL_IP_PRI_2, 0x5555);
2603 REG_WRITE(REG_GLOBAL, GLOBAL_IP_PRI_3, 0x5555);
2604 REG_WRITE(REG_GLOBAL, GLOBAL_IP_PRI_4, 0xaaaa);
2605 REG_WRITE(REG_GLOBAL, GLOBAL_IP_PRI_5, 0xaaaa);
2606 REG_WRITE(REG_GLOBAL, GLOBAL_IP_PRI_6, 0xffff);
2607 REG_WRITE(REG_GLOBAL, GLOBAL_IP_PRI_7, 0xffff);
2609 /* Configure the IEEE 802.1p priority mapping register. */
2610 REG_WRITE(REG_GLOBAL, GLOBAL_IEEE_PRI, 0xfa41);
2612 /* Send all frames with destination addresses matching
2613 * 01:80:c2:00:00:0x to the CPU port.
2615 REG_WRITE(REG_GLOBAL2, GLOBAL2_MGMT_EN_0X, 0xffff);
2617 /* Ignore removed tag data on doubly tagged packets, disable
2618 * flow control messages, force flow control priority to the
2619 * highest, and send all special multicast frames to the CPU
2620 * port at the highest priority.
2622 REG_WRITE(REG_GLOBAL2, GLOBAL2_SWITCH_MGMT,
2623 0x7 | GLOBAL2_SWITCH_MGMT_RSVD2CPU | 0x70 |
2624 GLOBAL2_SWITCH_MGMT_FORCE_FLOW_CTRL_PRI);
2626 /* Program the DSA routing table. */
2627 for (i = 0; i < 32; i++) {
2630 if (ds->pd->rtable &&
2631 i != ds->index && i < ds->dst->pd->nr_chips)
2632 nexthop = ds->pd->rtable[i] & 0x1f;
2634 REG_WRITE(REG_GLOBAL2, GLOBAL2_DEVICE_MAPPING,
2635 GLOBAL2_DEVICE_MAPPING_UPDATE |
2636 (i << GLOBAL2_DEVICE_MAPPING_TARGET_SHIFT) |
2640 /* Clear all trunk masks. */
2641 for (i = 0; i < 8; i++)
2642 REG_WRITE(REG_GLOBAL2, GLOBAL2_TRUNK_MASK,
2643 0x8000 | (i << GLOBAL2_TRUNK_MASK_NUM_SHIFT) |
2644 ((1 << ps->num_ports) - 1));
2646 /* Clear all trunk mappings. */
2647 for (i = 0; i < 16; i++)
2648 REG_WRITE(REG_GLOBAL2, GLOBAL2_TRUNK_MAPPING,
2649 GLOBAL2_TRUNK_MAPPING_UPDATE |
2650 (i << GLOBAL2_TRUNK_MAPPING_ID_SHIFT));
2652 if (mv88e6xxx_6352_family(ds) || mv88e6xxx_6351_family(ds) ||
2653 mv88e6xxx_6165_family(ds) || mv88e6xxx_6097_family(ds) ||
2654 mv88e6xxx_6320_family(ds)) {
2655 /* Send all frames with destination addresses matching
2656 * 01:80:c2:00:00:2x to the CPU port.
2658 REG_WRITE(REG_GLOBAL2, GLOBAL2_MGMT_EN_2X, 0xffff);
2660 /* Initialise cross-chip port VLAN table to reset
2663 REG_WRITE(REG_GLOBAL2, GLOBAL2_PVT_ADDR, 0x9000);
2665 /* Clear the priority override table. */
2666 for (i = 0; i < 16; i++)
2667 REG_WRITE(REG_GLOBAL2, GLOBAL2_PRIO_OVERRIDE,
2671 if (mv88e6xxx_6352_family(ds) || mv88e6xxx_6351_family(ds) ||
2672 mv88e6xxx_6165_family(ds) || mv88e6xxx_6097_family(ds) ||
2673 mv88e6xxx_6185_family(ds) || mv88e6xxx_6095_family(ds) ||
2674 mv88e6xxx_6320_family(ds)) {
2675 /* Disable ingress rate limiting by resetting all
2676 * ingress rate limit registers to their initial
2679 for (i = 0; i < ps->num_ports; i++)
2680 REG_WRITE(REG_GLOBAL2, GLOBAL2_INGRESS_OP,
2684 /* Clear the statistics counters for all ports */
2685 REG_WRITE(REG_GLOBAL, GLOBAL_STATS_OP, GLOBAL_STATS_OP_FLUSH_ALL);
2687 /* Wait for the flush to complete. */
2688 mutex_lock(&ps->smi_mutex);
2689 ret = _mv88e6xxx_stats_wait(ds);
2693 /* Clear all ATU entries */
2694 ret = _mv88e6xxx_atu_flush(ds, 0, true);
2698 /* Clear all the VTU and STU entries */
2699 ret = _mv88e6xxx_vtu_stu_flush(ds);
2701 mutex_unlock(&ps->smi_mutex);
2706 int mv88e6xxx_switch_reset(struct dsa_switch *ds, bool ppu_active)
2708 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
2709 u16 is_reset = (ppu_active ? 0x8800 : 0xc800);
2710 struct gpio_desc *gpiod = ds->pd->reset;
2711 unsigned long timeout;
2715 /* Set all ports to the disabled state. */
2716 for (i = 0; i < ps->num_ports; i++) {
2717 ret = REG_READ(REG_PORT(i), PORT_CONTROL);
2718 REG_WRITE(REG_PORT(i), PORT_CONTROL, ret & 0xfffc);
2721 /* Wait for transmit queues to drain. */
2722 usleep_range(2000, 4000);
2724 /* If there is a gpio connected to the reset pin, toggle it */
2726 gpiod_set_value_cansleep(gpiod, 1);
2727 usleep_range(10000, 20000);
2728 gpiod_set_value_cansleep(gpiod, 0);
2729 usleep_range(10000, 20000);
2732 /* Reset the switch. Keep the PPU active if requested. The PPU
2733 * needs to be active to support indirect phy register access
2734 * through global registers 0x18 and 0x19.
2737 REG_WRITE(REG_GLOBAL, 0x04, 0xc000);
2739 REG_WRITE(REG_GLOBAL, 0x04, 0xc400);
2741 /* Wait up to one second for reset to complete. */
2742 timeout = jiffies + 1 * HZ;
2743 while (time_before(jiffies, timeout)) {
2744 ret = REG_READ(REG_GLOBAL, 0x00);
2745 if ((ret & is_reset) == is_reset)
2747 usleep_range(1000, 2000);
2749 if (time_after(jiffies, timeout))
2755 int mv88e6xxx_phy_page_read(struct dsa_switch *ds, int port, int page, int reg)
2757 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
2760 mutex_lock(&ps->smi_mutex);
2761 ret = _mv88e6xxx_phy_page_read(ds, port, page, reg);
2762 mutex_unlock(&ps->smi_mutex);
2767 int mv88e6xxx_phy_page_write(struct dsa_switch *ds, int port, int page,
2770 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
2773 mutex_lock(&ps->smi_mutex);
2774 ret = _mv88e6xxx_phy_page_write(ds, port, page, reg, val);
2775 mutex_unlock(&ps->smi_mutex);
2780 static int mv88e6xxx_port_to_phy_addr(struct dsa_switch *ds, int port)
2782 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
2784 if (port >= 0 && port < ps->num_ports)
2790 mv88e6xxx_phy_read(struct dsa_switch *ds, int port, int regnum)
2792 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
2793 int addr = mv88e6xxx_port_to_phy_addr(ds, port);
2799 mutex_lock(&ps->smi_mutex);
2800 ret = _mv88e6xxx_phy_read(ds, addr, regnum);
2801 mutex_unlock(&ps->smi_mutex);
2806 mv88e6xxx_phy_write(struct dsa_switch *ds, int port, int regnum, u16 val)
2808 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
2809 int addr = mv88e6xxx_port_to_phy_addr(ds, port);
2815 mutex_lock(&ps->smi_mutex);
2816 ret = _mv88e6xxx_phy_write(ds, addr, regnum, val);
2817 mutex_unlock(&ps->smi_mutex);
2822 mv88e6xxx_phy_read_indirect(struct dsa_switch *ds, int port, int regnum)
2824 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
2825 int addr = mv88e6xxx_port_to_phy_addr(ds, port);
2831 mutex_lock(&ps->smi_mutex);
2832 ret = _mv88e6xxx_phy_read_indirect(ds, addr, regnum);
2833 mutex_unlock(&ps->smi_mutex);
2838 mv88e6xxx_phy_write_indirect(struct dsa_switch *ds, int port, int regnum,
2841 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
2842 int addr = mv88e6xxx_port_to_phy_addr(ds, port);
2848 mutex_lock(&ps->smi_mutex);
2849 ret = _mv88e6xxx_phy_write_indirect(ds, addr, regnum, val);
2850 mutex_unlock(&ps->smi_mutex);
2854 #ifdef CONFIG_NET_DSA_HWMON
2856 static int mv88e61xx_get_temp(struct dsa_switch *ds, int *temp)
2858 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
2864 mutex_lock(&ps->smi_mutex);
2866 ret = _mv88e6xxx_phy_write(ds, 0x0, 0x16, 0x6);
2870 /* Enable temperature sensor */
2871 ret = _mv88e6xxx_phy_read(ds, 0x0, 0x1a);
2875 ret = _mv88e6xxx_phy_write(ds, 0x0, 0x1a, ret | (1 << 5));
2879 /* Wait for temperature to stabilize */
2880 usleep_range(10000, 12000);
2882 val = _mv88e6xxx_phy_read(ds, 0x0, 0x1a);
2888 /* Disable temperature sensor */
2889 ret = _mv88e6xxx_phy_write(ds, 0x0, 0x1a, ret & ~(1 << 5));
2893 *temp = ((val & 0x1f) - 5) * 5;
2896 _mv88e6xxx_phy_write(ds, 0x0, 0x16, 0x0);
2897 mutex_unlock(&ps->smi_mutex);
2901 static int mv88e63xx_get_temp(struct dsa_switch *ds, int *temp)
2903 int phy = mv88e6xxx_6320_family(ds) ? 3 : 0;
2908 ret = mv88e6xxx_phy_page_read(ds, phy, 6, 27);
2912 *temp = (ret & 0xff) - 25;
2917 int mv88e6xxx_get_temp(struct dsa_switch *ds, int *temp)
2919 if (mv88e6xxx_6320_family(ds) || mv88e6xxx_6352_family(ds))
2920 return mv88e63xx_get_temp(ds, temp);
2922 return mv88e61xx_get_temp(ds, temp);
2925 int mv88e6xxx_get_temp_limit(struct dsa_switch *ds, int *temp)
2927 int phy = mv88e6xxx_6320_family(ds) ? 3 : 0;
2930 if (!mv88e6xxx_6320_family(ds) && !mv88e6xxx_6352_family(ds))
2935 ret = mv88e6xxx_phy_page_read(ds, phy, 6, 26);
2939 *temp = (((ret >> 8) & 0x1f) * 5) - 25;
2944 int mv88e6xxx_set_temp_limit(struct dsa_switch *ds, int temp)
2946 int phy = mv88e6xxx_6320_family(ds) ? 3 : 0;
2949 if (!mv88e6xxx_6320_family(ds) && !mv88e6xxx_6352_family(ds))
2952 ret = mv88e6xxx_phy_page_read(ds, phy, 6, 26);
2955 temp = clamp_val(DIV_ROUND_CLOSEST(temp, 5) + 5, 0, 0x1f);
2956 return mv88e6xxx_phy_page_write(ds, phy, 6, 26,
2957 (ret & 0xe0ff) | (temp << 8));
2960 int mv88e6xxx_get_temp_alarm(struct dsa_switch *ds, bool *alarm)
2962 int phy = mv88e6xxx_6320_family(ds) ? 3 : 0;
2965 if (!mv88e6xxx_6320_family(ds) && !mv88e6xxx_6352_family(ds))
2970 ret = mv88e6xxx_phy_page_read(ds, phy, 6, 26);
2974 *alarm = !!(ret & 0x40);
2978 #endif /* CONFIG_NET_DSA_HWMON */
2980 char *mv88e6xxx_lookup_name(struct device *host_dev, int sw_addr,
2981 const struct mv88e6xxx_switch_id *table,
2984 struct mii_bus *bus = dsa_host_dev_to_mii_bus(host_dev);
2990 ret = __mv88e6xxx_reg_read(bus, sw_addr, REG_PORT(0), PORT_SWITCH_ID);
2994 /* Look up the exact switch ID */
2995 for (i = 0; i < num; ++i)
2996 if (table[i].id == ret)
2997 return table[i].name;
2999 /* Look up only the product number */
3000 for (i = 0; i < num; ++i) {
3001 if (table[i].id == (ret & PORT_SWITCH_ID_PROD_NUM_MASK)) {
3002 dev_warn(host_dev, "unknown revision %d, using base switch 0x%x\n",
3003 ret & PORT_SWITCH_ID_REV_MASK,
3004 ret & PORT_SWITCH_ID_PROD_NUM_MASK);
3005 return table[i].name;
3012 static int __init mv88e6xxx_init(void)
3014 #if IS_ENABLED(CONFIG_NET_DSA_MV88E6131)
3015 register_switch_driver(&mv88e6131_switch_driver);
3017 #if IS_ENABLED(CONFIG_NET_DSA_MV88E6123)
3018 register_switch_driver(&mv88e6123_switch_driver);
3020 #if IS_ENABLED(CONFIG_NET_DSA_MV88E6352)
3021 register_switch_driver(&mv88e6352_switch_driver);
3023 #if IS_ENABLED(CONFIG_NET_DSA_MV88E6171)
3024 register_switch_driver(&mv88e6171_switch_driver);
3028 module_init(mv88e6xxx_init);
3030 static void __exit mv88e6xxx_cleanup(void)
3032 #if IS_ENABLED(CONFIG_NET_DSA_MV88E6171)
3033 unregister_switch_driver(&mv88e6171_switch_driver);
3035 #if IS_ENABLED(CONFIG_NET_DSA_MV88E6352)
3036 unregister_switch_driver(&mv88e6352_switch_driver);
3038 #if IS_ENABLED(CONFIG_NET_DSA_MV88E6123)
3039 unregister_switch_driver(&mv88e6123_switch_driver);
3041 #if IS_ENABLED(CONFIG_NET_DSA_MV88E6131)
3042 unregister_switch_driver(&mv88e6131_switch_driver);
3045 module_exit(mv88e6xxx_cleanup);
3047 MODULE_AUTHOR("Lennert Buytenhek <buytenh@wantstofly.org>");
3048 MODULE_DESCRIPTION("Driver for Marvell 88E6XXX ethernet switch chips");
3049 MODULE_LICENSE("GPL");