1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * Marvell 88E6xxx SERDES manipulation, via SMI bus
5 * Copyright (c) 2008 Marvell Semiconductor
7 * Copyright (c) 2017 Andrew Lunn <andrew@lunn.ch>
10 #include <linux/interrupt.h>
11 #include <linux/irqdomain.h>
12 #include <linux/mii.h>
20 static int mv88e6352_serdes_read(struct mv88e6xxx_chip *chip, int reg,
23 return mv88e6xxx_phy_page_read(chip, MV88E6352_ADDR_SERDES,
24 MV88E6352_SERDES_PAGE_FIBER,
28 static int mv88e6352_serdes_write(struct mv88e6xxx_chip *chip, int reg,
31 return mv88e6xxx_phy_page_write(chip, MV88E6352_ADDR_SERDES,
32 MV88E6352_SERDES_PAGE_FIBER,
36 static int mv88e6390_serdes_read(struct mv88e6xxx_chip *chip,
37 int lane, int device, int reg, u16 *val)
39 int reg_c45 = MII_ADDR_C45 | device << 16 | reg;
41 return mv88e6xxx_phy_read(chip, lane, reg_c45, val);
44 static int mv88e6390_serdes_write(struct mv88e6xxx_chip *chip,
45 int lane, int device, int reg, u16 val)
47 int reg_c45 = MII_ADDR_C45 | device << 16 | reg;
49 return mv88e6xxx_phy_write(chip, lane, reg_c45, val);
52 static int mv88e6xxx_serdes_pcs_get_state(struct mv88e6xxx_chip *chip,
54 struct phylink_link_state *state)
56 if (status & MV88E6390_SGMII_PHY_STATUS_SPD_DPL_VALID) {
57 state->link = !!(status & MV88E6390_SGMII_PHY_STATUS_LINK);
58 state->duplex = status &
59 MV88E6390_SGMII_PHY_STATUS_DUPLEX_FULL ?
60 DUPLEX_FULL : DUPLEX_HALF;
62 if (status & MV88E6390_SGMII_PHY_STATUS_TX_PAUSE)
63 state->pause |= MLO_PAUSE_TX;
64 if (status & MV88E6390_SGMII_PHY_STATUS_RX_PAUSE)
65 state->pause |= MLO_PAUSE_RX;
67 switch (status & MV88E6390_SGMII_PHY_STATUS_SPEED_MASK) {
68 case MV88E6390_SGMII_PHY_STATUS_SPEED_1000:
69 if (state->interface == PHY_INTERFACE_MODE_2500BASEX)
70 state->speed = SPEED_2500;
72 state->speed = SPEED_1000;
74 case MV88E6390_SGMII_PHY_STATUS_SPEED_100:
75 state->speed = SPEED_100;
77 case MV88E6390_SGMII_PHY_STATUS_SPEED_10:
78 state->speed = SPEED_10;
81 dev_err(chip->dev, "invalid PHY speed\n");
88 if (state->interface == PHY_INTERFACE_MODE_2500BASEX)
89 mii_lpa_mod_linkmode_x(state->lp_advertising, lpa,
90 ETHTOOL_LINK_MODE_2500baseX_Full_BIT);
91 else if (state->interface == PHY_INTERFACE_MODE_1000BASEX)
92 mii_lpa_mod_linkmode_x(state->lp_advertising, lpa,
93 ETHTOOL_LINK_MODE_1000baseX_Full_BIT);
98 int mv88e6352_serdes_power(struct mv88e6xxx_chip *chip, int port, int lane,
104 err = mv88e6352_serdes_read(chip, MII_BMCR, &val);
109 new_val = val & ~BMCR_PDOWN;
111 new_val = val | BMCR_PDOWN;
114 err = mv88e6352_serdes_write(chip, MII_BMCR, new_val);
119 int mv88e6352_serdes_pcs_config(struct mv88e6xxx_chip *chip, int port,
120 int lane, unsigned int mode,
121 phy_interface_t interface,
122 const unsigned long *advertise)
129 case PHY_INTERFACE_MODE_SGMII:
133 case PHY_INTERFACE_MODE_1000BASEX:
134 adv = linkmode_adv_to_mii_adv_x(advertise,
135 ETHTOOL_LINK_MODE_1000baseX_Full_BIT);
142 err = mv88e6352_serdes_read(chip, MII_ADVERTISE, &val);
146 changed = val != adv;
148 err = mv88e6352_serdes_write(chip, MII_ADVERTISE, adv);
153 err = mv88e6352_serdes_read(chip, MII_BMCR, &val);
157 if (phylink_autoneg_inband(mode))
158 bmcr = val | BMCR_ANENABLE;
160 bmcr = val & ~BMCR_ANENABLE;
165 return mv88e6352_serdes_write(chip, MII_BMCR, bmcr);
168 int mv88e6352_serdes_pcs_get_state(struct mv88e6xxx_chip *chip, int port,
169 int lane, struct phylink_link_state *state)
174 err = mv88e6352_serdes_read(chip, 0x11, &status);
176 dev_err(chip->dev, "can't read Serdes PHY status: %d\n", err);
180 err = mv88e6352_serdes_read(chip, MII_LPA, &lpa);
182 dev_err(chip->dev, "can't read Serdes PHY LPA: %d\n", err);
186 return mv88e6xxx_serdes_pcs_get_state(chip, status, lpa, state);
189 int mv88e6352_serdes_pcs_an_restart(struct mv88e6xxx_chip *chip, int port,
195 err = mv88e6352_serdes_read(chip, MII_BMCR, &bmcr);
199 return mv88e6352_serdes_write(chip, MII_BMCR, bmcr | BMCR_ANRESTART);
202 int mv88e6352_serdes_pcs_link_up(struct mv88e6xxx_chip *chip, int port,
203 int lane, int speed, int duplex)
208 err = mv88e6352_serdes_read(chip, MII_BMCR, &val);
212 bmcr = val & ~(BMCR_SPEED100 | BMCR_FULLDPLX | BMCR_SPEED1000);
215 bmcr |= BMCR_SPEED1000;
218 bmcr |= BMCR_SPEED100;
224 if (duplex == DUPLEX_FULL)
225 bmcr |= BMCR_FULLDPLX;
230 return mv88e6352_serdes_write(chip, MII_BMCR, bmcr);
233 int mv88e6352_serdes_get_lane(struct mv88e6xxx_chip *chip, int port)
235 u8 cmode = chip->ports[port].cmode;
238 if ((cmode == MV88E6XXX_PORT_STS_CMODE_100BASEX) ||
239 (cmode == MV88E6XXX_PORT_STS_CMODE_1000BASEX) ||
240 (cmode == MV88E6XXX_PORT_STS_CMODE_SGMII))
241 lane = 0xff; /* Unused */
246 static bool mv88e6352_port_has_serdes(struct mv88e6xxx_chip *chip, int port)
248 if (mv88e6xxx_serdes_get_lane(chip, port) >= 0)
254 struct mv88e6352_serdes_hw_stat {
255 char string[ETH_GSTRING_LEN];
260 static struct mv88e6352_serdes_hw_stat mv88e6352_serdes_hw_stats[] = {
261 { "serdes_fibre_rx_error", 16, 21 },
262 { "serdes_PRBS_error", 32, 24 },
265 int mv88e6352_serdes_get_sset_count(struct mv88e6xxx_chip *chip, int port)
267 if (mv88e6352_port_has_serdes(chip, port))
268 return ARRAY_SIZE(mv88e6352_serdes_hw_stats);
273 int mv88e6352_serdes_get_strings(struct mv88e6xxx_chip *chip,
274 int port, uint8_t *data)
276 struct mv88e6352_serdes_hw_stat *stat;
279 if (!mv88e6352_port_has_serdes(chip, port))
282 for (i = 0; i < ARRAY_SIZE(mv88e6352_serdes_hw_stats); i++) {
283 stat = &mv88e6352_serdes_hw_stats[i];
284 memcpy(data + i * ETH_GSTRING_LEN, stat->string,
287 return ARRAY_SIZE(mv88e6352_serdes_hw_stats);
290 static uint64_t mv88e6352_serdes_get_stat(struct mv88e6xxx_chip *chip,
291 struct mv88e6352_serdes_hw_stat *stat)
297 err = mv88e6352_serdes_read(chip, stat->reg, ®);
299 dev_err(chip->dev, "failed to read statistic\n");
305 if (stat->sizeof_stat == 32) {
306 err = mv88e6352_serdes_read(chip, stat->reg + 1, ®);
308 dev_err(chip->dev, "failed to read statistic\n");
311 val = val << 16 | reg;
317 int mv88e6352_serdes_get_stats(struct mv88e6xxx_chip *chip, int port,
320 struct mv88e6xxx_port *mv88e6xxx_port = &chip->ports[port];
321 struct mv88e6352_serdes_hw_stat *stat;
325 if (!mv88e6352_port_has_serdes(chip, port))
328 BUILD_BUG_ON(ARRAY_SIZE(mv88e6352_serdes_hw_stats) >
329 ARRAY_SIZE(mv88e6xxx_port->serdes_stats));
331 for (i = 0; i < ARRAY_SIZE(mv88e6352_serdes_hw_stats); i++) {
332 stat = &mv88e6352_serdes_hw_stats[i];
333 value = mv88e6352_serdes_get_stat(chip, stat);
334 mv88e6xxx_port->serdes_stats[i] += value;
335 data[i] = mv88e6xxx_port->serdes_stats[i];
338 return ARRAY_SIZE(mv88e6352_serdes_hw_stats);
341 static void mv88e6352_serdes_irq_link(struct mv88e6xxx_chip *chip, int port)
346 /* If the link has dropped, we want to know about it. */
347 err = mv88e6352_serdes_read(chip, MII_BMSR, &bmsr);
349 dev_err(chip->dev, "can't read Serdes BMSR: %d\n", err);
353 dsa_port_phylink_mac_change(chip->ds, port, !!(bmsr & BMSR_LSTATUS));
356 irqreturn_t mv88e6352_serdes_irq_status(struct mv88e6xxx_chip *chip, int port,
359 irqreturn_t ret = IRQ_NONE;
363 err = mv88e6352_serdes_read(chip, MV88E6352_SERDES_INT_STATUS, &status);
367 if (status & MV88E6352_SERDES_INT_LINK_CHANGE) {
369 mv88e6352_serdes_irq_link(chip, port);
375 int mv88e6352_serdes_irq_enable(struct mv88e6xxx_chip *chip, int port, int lane,
381 val |= MV88E6352_SERDES_INT_LINK_CHANGE;
383 return mv88e6352_serdes_write(chip, MV88E6352_SERDES_INT_ENABLE, val);
386 unsigned int mv88e6352_serdes_irq_mapping(struct mv88e6xxx_chip *chip, int port)
388 return irq_find_mapping(chip->g2_irq.domain, MV88E6352_SERDES_IRQ);
391 int mv88e6352_serdes_get_regs_len(struct mv88e6xxx_chip *chip, int port)
393 if (!mv88e6352_port_has_serdes(chip, port))
396 return 32 * sizeof(u16);
399 void mv88e6352_serdes_get_regs(struct mv88e6xxx_chip *chip, int port, void *_p)
406 if (!mv88e6352_port_has_serdes(chip, port))
409 for (i = 0 ; i < 32; i++) {
410 err = mv88e6352_serdes_read(chip, i, ®);
416 int mv88e6341_serdes_get_lane(struct mv88e6xxx_chip *chip, int port)
418 u8 cmode = chip->ports[port].cmode;
423 if (cmode == MV88E6XXX_PORT_STS_CMODE_1000BASEX ||
424 cmode == MV88E6XXX_PORT_STS_CMODE_SGMII ||
425 cmode == MV88E6XXX_PORT_STS_CMODE_2500BASEX)
426 lane = MV88E6341_PORT5_LANE;
433 int mv88e6185_serdes_power(struct mv88e6xxx_chip *chip, int port, int lane,
436 /* The serdes power can't be controlled on this switch chip but we need
437 * to supply this function to avoid returning -EOPNOTSUPP in
438 * mv88e6xxx_serdes_power_up/mv88e6xxx_serdes_power_down
443 int mv88e6185_serdes_get_lane(struct mv88e6xxx_chip *chip, int port)
445 /* There are no configurable serdes lanes on this switch chip but we
446 * need to return a non-negative lane number so that callers of
447 * mv88e6xxx_serdes_get_lane() know this is a serdes port.
449 switch (chip->ports[port].cmode) {
450 case MV88E6185_PORT_STS_CMODE_SERDES:
451 case MV88E6185_PORT_STS_CMODE_1000BASE_X:
458 int mv88e6185_serdes_pcs_get_state(struct mv88e6xxx_chip *chip, int port,
459 int lane, struct phylink_link_state *state)
464 err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_STS, &status);
468 state->link = !!(status & MV88E6XXX_PORT_STS_LINK);
471 state->duplex = status & MV88E6XXX_PORT_STS_DUPLEX ? DUPLEX_FULL : DUPLEX_HALF;
473 switch (status & MV88E6XXX_PORT_STS_SPEED_MASK) {
474 case MV88E6XXX_PORT_STS_SPEED_1000:
475 state->speed = SPEED_1000;
477 case MV88E6XXX_PORT_STS_SPEED_100:
478 state->speed = SPEED_100;
480 case MV88E6XXX_PORT_STS_SPEED_10:
481 state->speed = SPEED_10;
484 dev_err(chip->dev, "invalid PHY speed\n");
488 state->duplex = DUPLEX_UNKNOWN;
489 state->speed = SPEED_UNKNOWN;
495 int mv88e6097_serdes_irq_enable(struct mv88e6xxx_chip *chip, int port, int lane,
498 u8 cmode = chip->ports[port].cmode;
500 /* The serdes interrupts are enabled in the G2_INT_MASK register. We
501 * need to return 0 to avoid returning -EOPNOTSUPP in
502 * mv88e6xxx_serdes_irq_enable/mv88e6xxx_serdes_irq_disable
505 case MV88E6185_PORT_STS_CMODE_SERDES:
506 case MV88E6185_PORT_STS_CMODE_1000BASE_X:
513 static void mv88e6097_serdes_irq_link(struct mv88e6xxx_chip *chip, int port)
518 err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_STS, &status);
520 dev_err(chip->dev, "can't read port status: %d\n", err);
524 dsa_port_phylink_mac_change(chip->ds, port, !!(status & MV88E6XXX_PORT_STS_LINK));
527 irqreturn_t mv88e6097_serdes_irq_status(struct mv88e6xxx_chip *chip, int port,
530 u8 cmode = chip->ports[port].cmode;
533 case MV88E6185_PORT_STS_CMODE_SERDES:
534 case MV88E6185_PORT_STS_CMODE_1000BASE_X:
535 mv88e6097_serdes_irq_link(chip, port);
542 int mv88e6390_serdes_get_lane(struct mv88e6xxx_chip *chip, int port)
544 u8 cmode = chip->ports[port].cmode;
549 if (cmode == MV88E6XXX_PORT_STS_CMODE_1000BASEX ||
550 cmode == MV88E6XXX_PORT_STS_CMODE_SGMII ||
551 cmode == MV88E6XXX_PORT_STS_CMODE_2500BASEX)
552 lane = MV88E6390_PORT9_LANE0;
555 if (cmode == MV88E6XXX_PORT_STS_CMODE_1000BASEX ||
556 cmode == MV88E6XXX_PORT_STS_CMODE_SGMII ||
557 cmode == MV88E6XXX_PORT_STS_CMODE_2500BASEX)
558 lane = MV88E6390_PORT10_LANE0;
565 int mv88e6390x_serdes_get_lane(struct mv88e6xxx_chip *chip, int port)
567 u8 cmode_port = chip->ports[port].cmode;
568 u8 cmode_port10 = chip->ports[10].cmode;
569 u8 cmode_port9 = chip->ports[9].cmode;
574 if (cmode_port9 == MV88E6XXX_PORT_STS_CMODE_1000BASEX ||
575 cmode_port9 == MV88E6XXX_PORT_STS_CMODE_SGMII ||
576 cmode_port9 == MV88E6XXX_PORT_STS_CMODE_2500BASEX)
577 if (cmode_port == MV88E6XXX_PORT_STS_CMODE_1000BASEX)
578 lane = MV88E6390_PORT9_LANE1;
581 if (cmode_port9 == MV88E6XXX_PORT_STS_CMODE_1000BASEX ||
582 cmode_port9 == MV88E6XXX_PORT_STS_CMODE_SGMII ||
583 cmode_port9 == MV88E6XXX_PORT_STS_CMODE_2500BASEX ||
584 cmode_port9 == MV88E6XXX_PORT_STS_CMODE_RXAUI)
585 if (cmode_port == MV88E6XXX_PORT_STS_CMODE_1000BASEX)
586 lane = MV88E6390_PORT9_LANE2;
589 if (cmode_port9 == MV88E6XXX_PORT_STS_CMODE_1000BASEX ||
590 cmode_port9 == MV88E6XXX_PORT_STS_CMODE_SGMII ||
591 cmode_port9 == MV88E6XXX_PORT_STS_CMODE_2500BASEX ||
592 cmode_port9 == MV88E6XXX_PORT_STS_CMODE_RXAUI)
593 if (cmode_port == MV88E6XXX_PORT_STS_CMODE_1000BASEX)
594 lane = MV88E6390_PORT9_LANE3;
597 if (cmode_port10 == MV88E6XXX_PORT_STS_CMODE_1000BASEX ||
598 cmode_port10 == MV88E6XXX_PORT_STS_CMODE_SGMII ||
599 cmode_port10 == MV88E6XXX_PORT_STS_CMODE_2500BASEX)
600 if (cmode_port == MV88E6XXX_PORT_STS_CMODE_1000BASEX)
601 lane = MV88E6390_PORT10_LANE1;
604 if (cmode_port10 == MV88E6XXX_PORT_STS_CMODE_1000BASEX ||
605 cmode_port10 == MV88E6XXX_PORT_STS_CMODE_SGMII ||
606 cmode_port10 == MV88E6XXX_PORT_STS_CMODE_2500BASEX ||
607 cmode_port10 == MV88E6XXX_PORT_STS_CMODE_RXAUI)
608 if (cmode_port == MV88E6XXX_PORT_STS_CMODE_1000BASEX)
609 lane = MV88E6390_PORT10_LANE2;
612 if (cmode_port10 == MV88E6XXX_PORT_STS_CMODE_1000BASEX ||
613 cmode_port10 == MV88E6XXX_PORT_STS_CMODE_SGMII ||
614 cmode_port10 == MV88E6XXX_PORT_STS_CMODE_2500BASEX ||
615 cmode_port10 == MV88E6XXX_PORT_STS_CMODE_RXAUI)
616 if (cmode_port == MV88E6XXX_PORT_STS_CMODE_1000BASEX)
617 lane = MV88E6390_PORT10_LANE3;
620 if (cmode_port9 == MV88E6XXX_PORT_STS_CMODE_1000BASEX ||
621 cmode_port9 == MV88E6XXX_PORT_STS_CMODE_SGMII ||
622 cmode_port9 == MV88E6XXX_PORT_STS_CMODE_2500BASEX ||
623 cmode_port9 == MV88E6XXX_PORT_STS_CMODE_XAUI ||
624 cmode_port9 == MV88E6XXX_PORT_STS_CMODE_RXAUI)
625 lane = MV88E6390_PORT9_LANE0;
628 if (cmode_port10 == MV88E6XXX_PORT_STS_CMODE_1000BASEX ||
629 cmode_port10 == MV88E6XXX_PORT_STS_CMODE_SGMII ||
630 cmode_port10 == MV88E6XXX_PORT_STS_CMODE_2500BASEX ||
631 cmode_port10 == MV88E6XXX_PORT_STS_CMODE_XAUI ||
632 cmode_port10 == MV88E6XXX_PORT_STS_CMODE_RXAUI)
633 lane = MV88E6390_PORT10_LANE0;
640 /* Only Ports 0, 9 and 10 have SERDES lanes. Return the SERDES lane address
641 * a port is using else Returns -ENODEV.
643 int mv88e6393x_serdes_get_lane(struct mv88e6xxx_chip *chip, int port)
645 u8 cmode = chip->ports[port].cmode;
648 if (port != 0 && port != 9 && port != 10)
651 if (cmode == MV88E6XXX_PORT_STS_CMODE_1000BASEX ||
652 cmode == MV88E6XXX_PORT_STS_CMODE_SGMII ||
653 cmode == MV88E6XXX_PORT_STS_CMODE_2500BASEX ||
654 cmode == MV88E6393X_PORT_STS_CMODE_5GBASER ||
655 cmode == MV88E6393X_PORT_STS_CMODE_10GBASER)
661 /* Set power up/down for 10GBASE-R and 10GBASE-X4/X2 */
662 static int mv88e6390_serdes_power_10g(struct mv88e6xxx_chip *chip, int lane,
668 err = mv88e6390_serdes_read(chip, lane, MDIO_MMD_PHYXS,
669 MV88E6390_10G_CTRL1, &val);
675 new_val = val & ~(MDIO_CTRL1_RESET |
676 MDIO_PCS_CTRL1_LOOPBACK |
679 new_val = val | MDIO_CTRL1_LPOWER;
682 err = mv88e6390_serdes_write(chip, lane, MDIO_MMD_PHYXS,
683 MV88E6390_10G_CTRL1, new_val);
688 /* Set power up/down for SGMII and 1000Base-X */
689 static int mv88e6390_serdes_power_sgmii(struct mv88e6xxx_chip *chip, int lane,
695 err = mv88e6390_serdes_read(chip, lane, MDIO_MMD_PHYXS,
696 MV88E6390_SGMII_BMCR, &val);
701 new_val = val & ~(BMCR_RESET | BMCR_LOOPBACK | BMCR_PDOWN);
703 new_val = val | BMCR_PDOWN;
706 err = mv88e6390_serdes_write(chip, lane, MDIO_MMD_PHYXS,
707 MV88E6390_SGMII_BMCR, new_val);
712 struct mv88e6390_serdes_hw_stat {
713 char string[ETH_GSTRING_LEN];
717 static struct mv88e6390_serdes_hw_stat mv88e6390_serdes_hw_stats[] = {
718 { "serdes_rx_pkts", 0xf021 },
719 { "serdes_rx_bytes", 0xf024 },
720 { "serdes_rx_pkts_error", 0xf027 },
723 int mv88e6390_serdes_get_sset_count(struct mv88e6xxx_chip *chip, int port)
725 if (mv88e6xxx_serdes_get_lane(chip, port) < 0)
728 return ARRAY_SIZE(mv88e6390_serdes_hw_stats);
731 int mv88e6390_serdes_get_strings(struct mv88e6xxx_chip *chip,
732 int port, uint8_t *data)
734 struct mv88e6390_serdes_hw_stat *stat;
737 if (mv88e6xxx_serdes_get_lane(chip, port) < 0)
740 for (i = 0; i < ARRAY_SIZE(mv88e6390_serdes_hw_stats); i++) {
741 stat = &mv88e6390_serdes_hw_stats[i];
742 memcpy(data + i * ETH_GSTRING_LEN, stat->string,
745 return ARRAY_SIZE(mv88e6390_serdes_hw_stats);
748 static uint64_t mv88e6390_serdes_get_stat(struct mv88e6xxx_chip *chip, int lane,
749 struct mv88e6390_serdes_hw_stat *stat)
754 for (i = 0; i < 3; i++) {
755 err = mv88e6390_serdes_read(chip, lane, MDIO_MMD_PHYXS,
756 stat->reg + i, ®[i]);
758 dev_err(chip->dev, "failed to read statistic\n");
763 return reg[0] | ((u64)reg[1] << 16) | ((u64)reg[2] << 32);
766 int mv88e6390_serdes_get_stats(struct mv88e6xxx_chip *chip, int port,
769 struct mv88e6390_serdes_hw_stat *stat;
773 lane = mv88e6xxx_serdes_get_lane(chip, port);
777 for (i = 0; i < ARRAY_SIZE(mv88e6390_serdes_hw_stats); i++) {
778 stat = &mv88e6390_serdes_hw_stats[i];
779 data[i] = mv88e6390_serdes_get_stat(chip, lane, stat);
782 return ARRAY_SIZE(mv88e6390_serdes_hw_stats);
785 static int mv88e6390_serdes_enable_checker(struct mv88e6xxx_chip *chip, int lane)
790 err = mv88e6390_serdes_read(chip, lane, MDIO_MMD_PHYXS,
791 MV88E6390_PG_CONTROL, ®);
795 reg |= MV88E6390_PG_CONTROL_ENABLE_PC;
796 return mv88e6390_serdes_write(chip, lane, MDIO_MMD_PHYXS,
797 MV88E6390_PG_CONTROL, reg);
800 int mv88e6390_serdes_power(struct mv88e6xxx_chip *chip, int port, int lane,
803 u8 cmode = chip->ports[port].cmode;
807 case MV88E6XXX_PORT_STS_CMODE_SGMII:
808 case MV88E6XXX_PORT_STS_CMODE_1000BASEX:
809 case MV88E6XXX_PORT_STS_CMODE_2500BASEX:
810 err = mv88e6390_serdes_power_sgmii(chip, lane, up);
812 case MV88E6XXX_PORT_STS_CMODE_XAUI:
813 case MV88E6XXX_PORT_STS_CMODE_RXAUI:
814 err = mv88e6390_serdes_power_10g(chip, lane, up);
819 err = mv88e6390_serdes_enable_checker(chip, lane);
824 int mv88e6390_serdes_pcs_config(struct mv88e6xxx_chip *chip, int port,
825 int lane, unsigned int mode,
826 phy_interface_t interface,
827 const unsigned long *advertise)
834 case PHY_INTERFACE_MODE_SGMII:
838 case PHY_INTERFACE_MODE_1000BASEX:
839 adv = linkmode_adv_to_mii_adv_x(advertise,
840 ETHTOOL_LINK_MODE_1000baseX_Full_BIT);
843 case PHY_INTERFACE_MODE_2500BASEX:
844 adv = linkmode_adv_to_mii_adv_x(advertise,
845 ETHTOOL_LINK_MODE_2500baseX_Full_BIT);
852 err = mv88e6390_serdes_read(chip, lane, MDIO_MMD_PHYXS,
853 MV88E6390_SGMII_ADVERTISE, &val);
857 changed = val != adv;
859 err = mv88e6390_serdes_write(chip, lane, MDIO_MMD_PHYXS,
860 MV88E6390_SGMII_ADVERTISE, adv);
865 err = mv88e6390_serdes_read(chip, lane, MDIO_MMD_PHYXS,
866 MV88E6390_SGMII_BMCR, &val);
870 if (phylink_autoneg_inband(mode))
871 bmcr = val | BMCR_ANENABLE;
873 bmcr = val & ~BMCR_ANENABLE;
875 /* setting ANENABLE triggers a restart of negotiation */
879 return mv88e6390_serdes_write(chip, lane, MDIO_MMD_PHYXS,
880 MV88E6390_SGMII_BMCR, bmcr);
883 static int mv88e6390_serdes_pcs_get_state_sgmii(struct mv88e6xxx_chip *chip,
884 int port, int lane, struct phylink_link_state *state)
889 err = mv88e6390_serdes_read(chip, lane, MDIO_MMD_PHYXS,
890 MV88E6390_SGMII_PHY_STATUS, &status);
892 dev_err(chip->dev, "can't read Serdes PHY status: %d\n", err);
896 err = mv88e6390_serdes_read(chip, lane, MDIO_MMD_PHYXS,
897 MV88E6390_SGMII_LPA, &lpa);
899 dev_err(chip->dev, "can't read Serdes PHY LPA: %d\n", err);
903 return mv88e6xxx_serdes_pcs_get_state(chip, status, lpa, state);
906 static int mv88e6390_serdes_pcs_get_state_10g(struct mv88e6xxx_chip *chip,
907 int port, int lane, struct phylink_link_state *state)
912 err = mv88e6390_serdes_read(chip, lane, MDIO_MMD_PHYXS,
913 MV88E6390_10G_STAT1, &status);
917 state->link = !!(status & MDIO_STAT1_LSTATUS);
919 state->speed = SPEED_10000;
920 state->duplex = DUPLEX_FULL;
926 static int mv88e6393x_serdes_pcs_get_state_10g(struct mv88e6xxx_chip *chip,
928 struct phylink_link_state *state)
933 err = mv88e6390_serdes_read(chip, lane, MDIO_MMD_PHYXS,
934 MV88E6390_10G_STAT1, &status);
938 state->link = !!(status & MDIO_STAT1_LSTATUS);
940 if (state->interface == PHY_INTERFACE_MODE_5GBASER)
941 state->speed = SPEED_5000;
943 state->speed = SPEED_10000;
944 state->duplex = DUPLEX_FULL;
950 int mv88e6390_serdes_pcs_get_state(struct mv88e6xxx_chip *chip, int port,
951 int lane, struct phylink_link_state *state)
953 switch (state->interface) {
954 case PHY_INTERFACE_MODE_SGMII:
955 case PHY_INTERFACE_MODE_1000BASEX:
956 case PHY_INTERFACE_MODE_2500BASEX:
957 return mv88e6390_serdes_pcs_get_state_sgmii(chip, port, lane,
959 case PHY_INTERFACE_MODE_XAUI:
960 case PHY_INTERFACE_MODE_RXAUI:
961 return mv88e6390_serdes_pcs_get_state_10g(chip, port, lane,
969 int mv88e6393x_serdes_pcs_get_state(struct mv88e6xxx_chip *chip, int port,
970 int lane, struct phylink_link_state *state)
972 switch (state->interface) {
973 case PHY_INTERFACE_MODE_SGMII:
974 case PHY_INTERFACE_MODE_1000BASEX:
975 case PHY_INTERFACE_MODE_2500BASEX:
976 return mv88e6390_serdes_pcs_get_state_sgmii(chip, port, lane,
978 case PHY_INTERFACE_MODE_5GBASER:
979 case PHY_INTERFACE_MODE_10GBASER:
980 return mv88e6393x_serdes_pcs_get_state_10g(chip, port, lane,
988 int mv88e6390_serdes_pcs_an_restart(struct mv88e6xxx_chip *chip, int port,
994 err = mv88e6390_serdes_read(chip, lane, MDIO_MMD_PHYXS,
995 MV88E6390_SGMII_BMCR, &bmcr);
999 return mv88e6390_serdes_write(chip, lane, MDIO_MMD_PHYXS,
1000 MV88E6390_SGMII_BMCR,
1001 bmcr | BMCR_ANRESTART);
1004 int mv88e6390_serdes_pcs_link_up(struct mv88e6xxx_chip *chip, int port,
1005 int lane, int speed, int duplex)
1010 err = mv88e6390_serdes_read(chip, lane, MDIO_MMD_PHYXS,
1011 MV88E6390_SGMII_BMCR, &val);
1015 bmcr = val & ~(BMCR_SPEED100 | BMCR_FULLDPLX | BMCR_SPEED1000);
1019 bmcr |= BMCR_SPEED1000;
1022 bmcr |= BMCR_SPEED100;
1028 if (duplex == DUPLEX_FULL)
1029 bmcr |= BMCR_FULLDPLX;
1034 return mv88e6390_serdes_write(chip, lane, MDIO_MMD_PHYXS,
1035 MV88E6390_SGMII_BMCR, bmcr);
1038 static void mv88e6390_serdes_irq_link_sgmii(struct mv88e6xxx_chip *chip,
1044 /* If the link has dropped, we want to know about it. */
1045 err = mv88e6390_serdes_read(chip, lane, MDIO_MMD_PHYXS,
1046 MV88E6390_SGMII_BMSR, &bmsr);
1048 dev_err(chip->dev, "can't read Serdes BMSR: %d\n", err);
1052 dsa_port_phylink_mac_change(chip->ds, port, !!(bmsr & BMSR_LSTATUS));
1055 static void mv88e6393x_serdes_irq_link_10g(struct mv88e6xxx_chip *chip,
1061 /* If the link has dropped, we want to know about it. */
1062 err = mv88e6390_serdes_read(chip, lane, MDIO_MMD_PHYXS,
1063 MV88E6390_10G_STAT1, &status);
1065 dev_err(chip->dev, "can't read Serdes STAT1: %d\n", err);
1069 dsa_port_phylink_mac_change(chip->ds, port, !!(status & MDIO_STAT1_LSTATUS));
1072 static int mv88e6390_serdes_irq_enable_sgmii(struct mv88e6xxx_chip *chip,
1073 int lane, bool enable)
1078 val |= MV88E6390_SGMII_INT_LINK_DOWN |
1079 MV88E6390_SGMII_INT_LINK_UP;
1081 return mv88e6390_serdes_write(chip, lane, MDIO_MMD_PHYXS,
1082 MV88E6390_SGMII_INT_ENABLE, val);
1085 int mv88e6390_serdes_irq_enable(struct mv88e6xxx_chip *chip, int port, int lane,
1088 u8 cmode = chip->ports[port].cmode;
1091 case MV88E6XXX_PORT_STS_CMODE_SGMII:
1092 case MV88E6XXX_PORT_STS_CMODE_1000BASEX:
1093 case MV88E6XXX_PORT_STS_CMODE_2500BASEX:
1094 return mv88e6390_serdes_irq_enable_sgmii(chip, lane, enable);
1100 static int mv88e6390_serdes_irq_status_sgmii(struct mv88e6xxx_chip *chip,
1101 int lane, u16 *status)
1105 err = mv88e6390_serdes_read(chip, lane, MDIO_MMD_PHYXS,
1106 MV88E6390_SGMII_INT_STATUS, status);
1111 static int mv88e6393x_serdes_irq_enable_10g(struct mv88e6xxx_chip *chip,
1112 u8 lane, bool enable)
1117 val |= MV88E6393X_10G_INT_LINK_CHANGE;
1119 return mv88e6390_serdes_write(chip, lane, MDIO_MMD_PHYXS,
1120 MV88E6393X_10G_INT_ENABLE, val);
1123 int mv88e6393x_serdes_irq_enable(struct mv88e6xxx_chip *chip, int port,
1124 int lane, bool enable)
1126 u8 cmode = chip->ports[port].cmode;
1129 case MV88E6XXX_PORT_STS_CMODE_SGMII:
1130 case MV88E6XXX_PORT_STS_CMODE_1000BASEX:
1131 case MV88E6XXX_PORT_STS_CMODE_2500BASEX:
1132 return mv88e6390_serdes_irq_enable_sgmii(chip, lane, enable);
1133 case MV88E6393X_PORT_STS_CMODE_5GBASER:
1134 case MV88E6393X_PORT_STS_CMODE_10GBASER:
1135 return mv88e6393x_serdes_irq_enable_10g(chip, lane, enable);
1141 static int mv88e6393x_serdes_irq_status_10g(struct mv88e6xxx_chip *chip,
1142 u8 lane, u16 *status)
1146 err = mv88e6390_serdes_read(chip, lane, MDIO_MMD_PHYXS,
1147 MV88E6393X_10G_INT_STATUS, status);
1152 irqreturn_t mv88e6393x_serdes_irq_status(struct mv88e6xxx_chip *chip, int port,
1155 u8 cmode = chip->ports[port].cmode;
1156 irqreturn_t ret = IRQ_NONE;
1161 case MV88E6XXX_PORT_STS_CMODE_SGMII:
1162 case MV88E6XXX_PORT_STS_CMODE_1000BASEX:
1163 case MV88E6XXX_PORT_STS_CMODE_2500BASEX:
1164 err = mv88e6390_serdes_irq_status_sgmii(chip, lane, &status);
1167 if (status & (MV88E6390_SGMII_INT_LINK_DOWN |
1168 MV88E6390_SGMII_INT_LINK_UP)) {
1170 mv88e6390_serdes_irq_link_sgmii(chip, port, lane);
1173 case MV88E6393X_PORT_STS_CMODE_5GBASER:
1174 case MV88E6393X_PORT_STS_CMODE_10GBASER:
1175 err = mv88e6393x_serdes_irq_status_10g(chip, lane, &status);
1178 if (status & MV88E6393X_10G_INT_LINK_CHANGE) {
1180 mv88e6393x_serdes_irq_link_10g(chip, port, lane);
1188 irqreturn_t mv88e6390_serdes_irq_status(struct mv88e6xxx_chip *chip, int port,
1191 u8 cmode = chip->ports[port].cmode;
1192 irqreturn_t ret = IRQ_NONE;
1197 case MV88E6XXX_PORT_STS_CMODE_SGMII:
1198 case MV88E6XXX_PORT_STS_CMODE_1000BASEX:
1199 case MV88E6XXX_PORT_STS_CMODE_2500BASEX:
1200 err = mv88e6390_serdes_irq_status_sgmii(chip, lane, &status);
1203 if (status & (MV88E6390_SGMII_INT_LINK_DOWN |
1204 MV88E6390_SGMII_INT_LINK_UP)) {
1206 mv88e6390_serdes_irq_link_sgmii(chip, port, lane);
1213 unsigned int mv88e6390_serdes_irq_mapping(struct mv88e6xxx_chip *chip, int port)
1215 return irq_find_mapping(chip->g2_irq.domain, port);
1218 static const u16 mv88e6390_serdes_regs[] = {
1219 /* SERDES common registers */
1220 0xf00a, 0xf00b, 0xf00c,
1221 0xf010, 0xf011, 0xf012, 0xf013,
1222 0xf016, 0xf017, 0xf018,
1223 0xf01b, 0xf01c, 0xf01d, 0xf01e, 0xf01f,
1224 0xf020, 0xf021, 0xf022, 0xf023, 0xf024, 0xf025, 0xf026, 0xf027,
1226 0xf030, 0xf031, 0xf032, 0xf033, 0xf034, 0xf035, 0xf036, 0xf037,
1229 0x2000, 0x2001, 0x2002, 0x2003, 0x2004, 0x2005, 0x2006, 0x2007,
1232 0xa000, 0xa001, 0xa002, 0xa003,
1234 0x1000, 0x1001, 0x1002, 0x1003, 0x1004, 0x1005, 0x1006, 0x1007,
1238 0x9000, 0x9001, 0x9002, 0x9003, 0x9004,
1240 0x9010, 0x9011, 0x9012, 0x9013, 0x9014, 0x9015, 0x9016,
1242 0x1020, 0x1021, 0x1022, 0x1023, 0x1024, 0x1025, 0x1026, 0x1027,
1243 0x1028, 0x1029, 0x102a, 0x102b,
1246 int mv88e6390_serdes_get_regs_len(struct mv88e6xxx_chip *chip, int port)
1248 if (mv88e6xxx_serdes_get_lane(chip, port) < 0)
1251 return ARRAY_SIZE(mv88e6390_serdes_regs) * sizeof(u16);
1254 void mv88e6390_serdes_get_regs(struct mv88e6xxx_chip *chip, int port, void *_p)
1262 lane = mv88e6xxx_serdes_get_lane(chip, port);
1266 for (i = 0 ; i < ARRAY_SIZE(mv88e6390_serdes_regs); i++) {
1267 err = mv88e6390_serdes_read(chip, lane, MDIO_MMD_PHYXS,
1268 mv88e6390_serdes_regs[i], ®);
1274 static int mv88e6393x_serdes_port_errata(struct mv88e6xxx_chip *chip, int lane)
1279 /* mv88e6393x family errata 4.6:
1280 * Cannot clear PwrDn bit on SERDES if device is configured CPU_MGD
1281 * mode or P0_mode is configured for [x]MII.
1282 * Workaround: Set SERDES register 4.F002 bit 5=0 and bit 15=1.
1284 * It seems that after this workaround the SERDES is automatically
1285 * powered up (the bit is cleared), so power it down.
1287 if (lane == MV88E6393X_PORT0_LANE || lane == MV88E6393X_PORT9_LANE ||
1288 lane == MV88E6393X_PORT10_LANE) {
1289 err = mv88e6390_serdes_read(chip, lane,
1291 MV88E6393X_SERDES_POC, ®);
1295 reg &= ~MV88E6393X_SERDES_POC_PDOWN;
1296 reg |= MV88E6393X_SERDES_POC_RESET;
1298 err = mv88e6390_serdes_write(chip, lane, MDIO_MMD_PHYXS,
1299 MV88E6393X_SERDES_POC, reg);
1303 err = mv88e6390_serdes_power_sgmii(chip, lane, false);
1308 /* mv88e6393x family errata 4.8:
1309 * When a SERDES port is operating in 1000BASE-X or SGMII mode link may
1310 * not come up after hardware reset or software reset of SERDES core.
1311 * Workaround is to write SERDES register 4.F074.14=1 for only those
1312 * modes and 0 in all other modes.
1314 err = mv88e6390_serdes_read(chip, lane, MDIO_MMD_PHYXS,
1315 MV88E6393X_SERDES_POC, &pcs);
1319 pcs &= MV88E6393X_SERDES_POC_PCS_MASK;
1321 err = mv88e6390_serdes_read(chip, lane, MDIO_MMD_PHYXS,
1322 MV88E6393X_ERRATA_4_8_REG, ®);
1326 if (pcs == MV88E6393X_SERDES_POC_PCS_1000BASEX ||
1327 pcs == MV88E6393X_SERDES_POC_PCS_SGMII_PHY ||
1328 pcs == MV88E6393X_SERDES_POC_PCS_SGMII_MAC)
1329 reg |= MV88E6393X_ERRATA_4_8_BIT;
1331 reg &= ~MV88E6393X_ERRATA_4_8_BIT;
1333 return mv88e6390_serdes_write(chip, lane, MDIO_MMD_PHYXS,
1334 MV88E6393X_ERRATA_4_8_REG, reg);
1337 int mv88e6393x_serdes_setup_errata(struct mv88e6xxx_chip *chip)
1341 err = mv88e6393x_serdes_port_errata(chip, MV88E6393X_PORT0_LANE);
1345 err = mv88e6393x_serdes_port_errata(chip, MV88E6393X_PORT9_LANE);
1349 return mv88e6393x_serdes_port_errata(chip, MV88E6393X_PORT10_LANE);
1352 int mv88e6393x_serdes_power(struct mv88e6xxx_chip *chip, int port, int lane,
1355 u8 cmode = chip->ports[port].cmode;
1357 if (port != 0 && port != 9 && port != 10)
1361 case MV88E6XXX_PORT_STS_CMODE_SGMII:
1362 case MV88E6XXX_PORT_STS_CMODE_1000BASEX:
1363 case MV88E6XXX_PORT_STS_CMODE_2500BASEX:
1364 return mv88e6390_serdes_power_sgmii(chip, lane, on);
1365 case MV88E6393X_PORT_STS_CMODE_5GBASER:
1366 case MV88E6393X_PORT_STS_CMODE_10GBASER:
1367 return mv88e6390_serdes_power_10g(chip, lane, on);