1 /* SPDX-License-Identifier: GPL-2.0-or-later */
3 * Marvell 88E6xxx Ethernet switch single-chip definition
5 * Copyright (c) 2008 Marvell Semiconductor
8 #ifndef _MV88E6XXX_CHIP_H
9 #define _MV88E6XXX_CHIP_H
11 #include <linux/if_vlan.h>
12 #include <linux/irq.h>
13 #include <linux/gpio/consumer.h>
14 #include <linux/kthread.h>
15 #include <linux/phy.h>
16 #include <linux/ptp_clock_kernel.h>
17 #include <linux/timecounter.h>
20 #define MV88E6XXX_N_FID 4096
22 /* PVT limits for 4-bit port and 5-bit switch */
23 #define MV88E6XXX_MAX_PVT_SWITCHES 32
24 #define MV88E6XXX_MAX_PVT_PORTS 16
26 #define MV88E6XXX_MAX_GPIO 16
28 enum mv88e6xxx_egress_mode {
29 MV88E6XXX_EGRESS_MODE_UNMODIFIED,
30 MV88E6XXX_EGRESS_MODE_UNTAGGED,
31 MV88E6XXX_EGRESS_MODE_TAGGED,
32 MV88E6XXX_EGRESS_MODE_ETHERTYPE,
35 enum mv88e6xxx_frame_mode {
36 MV88E6XXX_FRAME_MODE_NORMAL,
37 MV88E6XXX_FRAME_MODE_DSA,
38 MV88E6XXX_FRAME_MODE_PROVIDER,
39 MV88E6XXX_FRAME_MODE_ETHERTYPE,
42 /* List of supported models */
43 enum mv88e6xxx_model {
73 enum mv88e6xxx_family {
74 MV88E6XXX_FAMILY_NONE,
75 MV88E6XXX_FAMILY_6065, /* 6031 6035 6061 6065 */
76 MV88E6XXX_FAMILY_6095, /* 6092 6095 */
77 MV88E6XXX_FAMILY_6097, /* 6046 6085 6096 6097 */
78 MV88E6XXX_FAMILY_6165, /* 6123 6161 6165 */
79 MV88E6XXX_FAMILY_6185, /* 6108 6121 6122 6131 6152 6155 6182 6185 */
80 MV88E6XXX_FAMILY_6250, /* 6250 */
81 MV88E6XXX_FAMILY_6320, /* 6320 6321 */
82 MV88E6XXX_FAMILY_6341, /* 6141 6341 */
83 MV88E6XXX_FAMILY_6351, /* 6171 6175 6350 6351 */
84 MV88E6XXX_FAMILY_6352, /* 6172 6176 6240 6352 */
85 MV88E6XXX_FAMILY_6390, /* 6190 6190X 6191 6290 6390 6390X */
90 struct mv88e6xxx_info {
91 enum mv88e6xxx_family family;
94 unsigned int num_databases;
95 unsigned int num_ports;
96 unsigned int num_internal_phys;
97 unsigned int num_gpio;
99 unsigned int port_base_addr;
100 unsigned int phy_base_addr;
101 unsigned int global1_addr;
102 unsigned int global2_addr;
103 unsigned int age_time_coeff;
104 unsigned int g1_irqs;
105 unsigned int g2_irqs;
108 /* Multi-chip Addressing Mode.
109 * Some chips respond to only 2 registers of its own SMI device address
110 * when it is non-zero, and use indirect access to internal registers.
113 /* Dual-chip Addressing Mode
114 * Some chips respond to only half of the 32 SMI addresses,
115 * allowing two to coexist on the same SMI interface.
119 enum dsa_tag_protocol tag_protocol;
121 /* Mask for FromPort and ToPort value of PortVec used in ATU Move
122 * operation. 0 means that the ATU Move operation is not supported.
124 u8 atu_move_port_mask;
125 const struct mv88e6xxx_ops *ops;
131 struct mv88e6xxx_atu_entry {
138 struct mv88e6xxx_vtu_entry {
143 u8 member[DSA_MAX_PORTS];
144 u8 state[DSA_MAX_PORTS];
147 struct mv88e6xxx_bus_ops;
148 struct mv88e6xxx_irq_ops;
149 struct mv88e6xxx_gpio_ops;
150 struct mv88e6xxx_avb_ops;
151 struct mv88e6xxx_ptp_ops;
153 struct mv88e6xxx_irq {
155 struct irq_chip chip;
156 struct irq_domain *domain;
160 /* state flags for mv88e6xxx_port_hwtstamp::state */
162 MV88E6XXX_HWTSTAMP_ENABLED,
163 MV88E6XXX_HWTSTAMP_TX_IN_PROGRESS,
166 struct mv88e6xxx_port_hwtstamp {
170 /* Timestamping state */
173 /* Resources for receive timestamping */
174 struct sk_buff_head rx_queue;
175 struct sk_buff_head rx_queue2;
177 /* Resources for transmit timestamping */
178 unsigned long tx_tstamp_start;
179 struct sk_buff *tx_skb;
182 /* Current timestamp configuration */
183 struct hwtstamp_config tstamp_config;
186 struct mv88e6xxx_port {
187 struct mv88e6xxx_chip *chip;
190 u64 atu_member_violation;
191 u64 atu_miss_violation;
192 u64 atu_full_violation;
193 u64 vtu_member_violation;
194 u64 vtu_miss_violation;
199 struct mv88e6xxx_chip {
200 const struct mv88e6xxx_info *info;
202 /* The dsa_switch this private structure is related to */
203 struct dsa_switch *ds;
205 /* The device this structure is associated to */
208 /* This mutex protects the access to the switch registers */
209 struct mutex reg_lock;
211 /* The MII bus and the address on the bus that is used to
212 * communication with the switch
214 const struct mv88e6xxx_bus_ops *smi_ops;
218 /* Handles automatic disabling and re-enabling of the PHY
221 const struct mv88e6xxx_bus_ops *phy_ops;
222 struct mutex ppu_mutex;
224 struct work_struct ppu_work;
225 struct timer_list ppu_timer;
227 /* This mutex serialises access to the statistics unit.
228 * Hold this mutex over snapshot + dump sequences.
230 struct mutex stats_mutex;
232 /* A switch may have a GPIO line tied to its reset pin. Parse
233 * this from the device tree, and use it before performing
236 struct gpio_desc *reset;
238 /* set to size of eeprom if supported by the switch */
241 /* List of mdio busses */
242 struct list_head mdios;
244 /* There can be two interrupt controllers, which are chained
245 * off a GPIO as interrupt source
247 struct mv88e6xxx_irq g1_irq;
248 struct mv88e6xxx_irq g2_irq;
255 struct kthread_worker *kworker;
256 struct kthread_delayed_work irq_poll_work;
261 /* This cyclecounter abstracts the switch PTP time.
262 * reg_lock must be held for any operation that read()s.
264 struct cyclecounter tstamp_cc;
265 struct timecounter tstamp_tc;
266 struct delayed_work overflow_work;
268 struct ptp_clock *ptp_clock;
269 struct ptp_clock_info ptp_clock_info;
270 struct delayed_work tai_event_work;
271 struct ptp_pin_desc pin_config[MV88E6XXX_MAX_GPIO];
276 /* Per-port timestamping resources. */
277 struct mv88e6xxx_port_hwtstamp port_hwtstamp[DSA_MAX_PORTS];
279 /* Array of port structures. */
280 struct mv88e6xxx_port ports[DSA_MAX_PORTS];
283 struct mv88e6xxx_bus_ops {
284 int (*read)(struct mv88e6xxx_chip *chip, int addr, int reg, u16 *val);
285 int (*write)(struct mv88e6xxx_chip *chip, int addr, int reg, u16 val);
288 struct mv88e6xxx_mdio_bus {
290 struct mv88e6xxx_chip *chip;
291 struct list_head list;
295 struct mv88e6xxx_ops {
296 /* Switch Setup Errata, called early in the switch setup to
297 * allow any errata actions to be performed
299 int (*setup_errata)(struct mv88e6xxx_chip *chip);
301 int (*ieee_pri_map)(struct mv88e6xxx_chip *chip);
302 int (*ip_pri_map)(struct mv88e6xxx_chip *chip);
304 /* Ingress Rate Limit unit (IRL) operations */
305 int (*irl_init_all)(struct mv88e6xxx_chip *chip, int port);
307 int (*get_eeprom)(struct mv88e6xxx_chip *chip,
308 struct ethtool_eeprom *eeprom, u8 *data);
309 int (*set_eeprom)(struct mv88e6xxx_chip *chip,
310 struct ethtool_eeprom *eeprom, u8 *data);
312 int (*set_switch_mac)(struct mv88e6xxx_chip *chip, u8 *addr);
314 int (*phy_read)(struct mv88e6xxx_chip *chip,
316 int addr, int reg, u16 *val);
317 int (*phy_write)(struct mv88e6xxx_chip *chip,
319 int addr, int reg, u16 val);
321 /* Priority Override Table operations */
322 int (*pot_clear)(struct mv88e6xxx_chip *chip);
324 /* PHY Polling Unit (PPU) operations */
325 int (*ppu_enable)(struct mv88e6xxx_chip *chip);
326 int (*ppu_disable)(struct mv88e6xxx_chip *chip);
328 /* Switch Software Reset */
329 int (*reset)(struct mv88e6xxx_chip *chip);
331 /* RGMII Receive/Transmit Timing Control
332 * Add delay on PHY_INTERFACE_MODE_RGMII_*ID, no delay otherwise.
334 int (*port_set_rgmii_delay)(struct mv88e6xxx_chip *chip, int port,
335 phy_interface_t mode);
337 #define LINK_FORCED_DOWN 0
338 #define LINK_FORCED_UP 1
339 #define LINK_UNFORCED -2
341 /* Port's MAC link state
342 * Use LINK_FORCED_UP or LINK_FORCED_DOWN to force link up or down,
343 * or LINK_UNFORCED for normal link detection.
345 int (*port_set_link)(struct mv88e6xxx_chip *chip, int port, int link);
347 #define DUPLEX_UNFORCED -2
349 /* Port's MAC duplex mode
351 * Use DUPLEX_HALF or DUPLEX_FULL to force half or full duplex,
352 * or DUPLEX_UNFORCED for normal duplex detection.
354 int (*port_set_duplex)(struct mv88e6xxx_chip *chip, int port, int dup);
359 /* Enable/disable sending Pause */
360 int (*port_set_pause)(struct mv88e6xxx_chip *chip, int port,
363 #define SPEED_MAX INT_MAX
364 #define SPEED_UNFORCED -2
366 /* Port's MAC speed (in Mbps)
368 * Depending on the chip, 10, 100, 200, 1000, 2500, 10000 are valid.
369 * Use SPEED_UNFORCED for normal detection, SPEED_MAX for max value.
371 int (*port_set_speed)(struct mv88e6xxx_chip *chip, int port, int speed);
373 /* What interface mode should be used for maximum speed? */
374 phy_interface_t (*port_max_speed_mode)(int port);
376 int (*port_tag_remap)(struct mv88e6xxx_chip *chip, int port);
378 int (*port_set_frame_mode)(struct mv88e6xxx_chip *chip, int port,
379 enum mv88e6xxx_frame_mode mode);
380 int (*port_set_egress_floods)(struct mv88e6xxx_chip *chip, int port,
381 bool unicast, bool multicast);
382 int (*port_set_ether_type)(struct mv88e6xxx_chip *chip, int port,
384 int (*port_set_jumbo_size)(struct mv88e6xxx_chip *chip, int port,
387 int (*port_egress_rate_limiting)(struct mv88e6xxx_chip *chip, int port);
388 int (*port_pause_limit)(struct mv88e6xxx_chip *chip, int port, u8 in,
390 int (*port_disable_learn_limit)(struct mv88e6xxx_chip *chip, int port);
391 int (*port_disable_pri_override)(struct mv88e6xxx_chip *chip, int port);
393 /* CMODE control what PHY mode the MAC will use, eg. SGMII, RGMII, etc.
394 * Some chips allow this to be configured on specific ports.
396 int (*port_set_cmode)(struct mv88e6xxx_chip *chip, int port,
397 phy_interface_t mode);
398 int (*port_get_cmode)(struct mv88e6xxx_chip *chip, int port, u8 *cmode);
400 /* Some devices have a per port register indicating what is
401 * the upstream port this port should forward to.
403 int (*port_set_upstream_port)(struct mv88e6xxx_chip *chip, int port,
405 /* Return the port link state, as required by phylink */
406 int (*port_link_state)(struct mv88e6xxx_chip *chip, int port,
407 struct phylink_link_state *state);
409 /* Snapshot the statistics for a port. The statistics can then
410 * be read back a leisure but still with a consistent view.
412 int (*stats_snapshot)(struct mv88e6xxx_chip *chip, int port);
414 /* Set the histogram mode for statistics, when the control registers
415 * are separated out of the STATS_OP register.
417 int (*stats_set_histogram)(struct mv88e6xxx_chip *chip);
419 /* Return the number of strings describing statistics */
420 int (*stats_get_sset_count)(struct mv88e6xxx_chip *chip);
421 int (*stats_get_strings)(struct mv88e6xxx_chip *chip, uint8_t *data);
422 int (*stats_get_stats)(struct mv88e6xxx_chip *chip, int port,
424 int (*set_cpu_port)(struct mv88e6xxx_chip *chip, int port);
425 int (*set_egress_port)(struct mv88e6xxx_chip *chip, int port);
427 #define MV88E6XXX_CASCADE_PORT_NONE 0xe
428 #define MV88E6XXX_CASCADE_PORT_MULTIPLE 0xf
430 int (*set_cascade_port)(struct mv88e6xxx_chip *chip, int port);
432 const struct mv88e6xxx_irq_ops *watchdog_ops;
434 int (*mgmt_rsvd2cpu)(struct mv88e6xxx_chip *chip);
436 /* Power on/off a SERDES interface */
437 int (*serdes_power)(struct mv88e6xxx_chip *chip, int port, bool on);
439 /* SERDES interrupt handling */
440 int (*serdes_irq_setup)(struct mv88e6xxx_chip *chip, int port);
441 void (*serdes_irq_free)(struct mv88e6xxx_chip *chip, int port);
443 /* Statistics from the SERDES interface */
444 int (*serdes_get_sset_count)(struct mv88e6xxx_chip *chip, int port);
445 int (*serdes_get_strings)(struct mv88e6xxx_chip *chip, int port,
447 int (*serdes_get_stats)(struct mv88e6xxx_chip *chip, int port,
450 /* VLAN Translation Unit operations */
451 int (*vtu_getnext)(struct mv88e6xxx_chip *chip,
452 struct mv88e6xxx_vtu_entry *entry);
453 int (*vtu_loadpurge)(struct mv88e6xxx_chip *chip,
454 struct mv88e6xxx_vtu_entry *entry);
456 /* GPIO operations */
457 const struct mv88e6xxx_gpio_ops *gpio_ops;
459 /* Interface to the AVB/PTP registers */
460 const struct mv88e6xxx_avb_ops *avb_ops;
462 /* Remote Management Unit operations */
463 int (*rmu_disable)(struct mv88e6xxx_chip *chip);
465 /* Precision Time Protocol operations */
466 const struct mv88e6xxx_ptp_ops *ptp_ops;
469 void (*phylink_validate)(struct mv88e6xxx_chip *chip, int port,
471 struct phylink_link_state *state);
474 struct mv88e6xxx_irq_ops {
475 /* Action to be performed when the interrupt happens */
476 int (*irq_action)(struct mv88e6xxx_chip *chip, int irq);
477 /* Setup the hardware to generate the interrupt */
478 int (*irq_setup)(struct mv88e6xxx_chip *chip);
479 /* Reset the hardware to stop generating the interrupt */
480 void (*irq_free)(struct mv88e6xxx_chip *chip);
483 struct mv88e6xxx_gpio_ops {
484 /* Get/set data on GPIO pin */
485 int (*get_data)(struct mv88e6xxx_chip *chip, unsigned int pin);
486 int (*set_data)(struct mv88e6xxx_chip *chip, unsigned int pin,
489 /* get/set GPIO direction */
490 int (*get_dir)(struct mv88e6xxx_chip *chip, unsigned int pin);
491 int (*set_dir)(struct mv88e6xxx_chip *chip, unsigned int pin,
494 /* get/set GPIO pin control */
495 int (*get_pctl)(struct mv88e6xxx_chip *chip, unsigned int pin,
497 int (*set_pctl)(struct mv88e6xxx_chip *chip, unsigned int pin,
501 struct mv88e6xxx_avb_ops {
502 /* Access port-scoped Precision Time Protocol registers */
503 int (*port_ptp_read)(struct mv88e6xxx_chip *chip, int port, int addr,
505 int (*port_ptp_write)(struct mv88e6xxx_chip *chip, int port, int addr,
508 /* Access global Precision Time Protocol registers */
509 int (*ptp_read)(struct mv88e6xxx_chip *chip, int addr, u16 *data,
511 int (*ptp_write)(struct mv88e6xxx_chip *chip, int addr, u16 data);
513 /* Access global Time Application Interface registers */
514 int (*tai_read)(struct mv88e6xxx_chip *chip, int addr, u16 *data,
516 int (*tai_write)(struct mv88e6xxx_chip *chip, int addr, u16 data);
519 struct mv88e6xxx_ptp_ops {
520 u64 (*clock_read)(const struct cyclecounter *cc);
521 int (*ptp_enable)(struct ptp_clock_info *ptp,
522 struct ptp_clock_request *rq, int on);
523 int (*ptp_verify)(struct ptp_clock_info *ptp, unsigned int pin,
524 enum ptp_pin_function func, unsigned int chan);
525 void (*event_work)(struct work_struct *ugly);
526 int (*port_enable)(struct mv88e6xxx_chip *chip, int port);
527 int (*port_disable)(struct mv88e6xxx_chip *chip, int port);
528 int (*global_enable)(struct mv88e6xxx_chip *chip);
529 int (*global_disable)(struct mv88e6xxx_chip *chip);
537 #define STATS_TYPE_PORT BIT(0)
538 #define STATS_TYPE_BANK0 BIT(1)
539 #define STATS_TYPE_BANK1 BIT(2)
541 struct mv88e6xxx_hw_stat {
542 char string[ETH_GSTRING_LEN];
548 static inline bool mv88e6xxx_has_pvt(struct mv88e6xxx_chip *chip)
550 return chip->info->pvt;
553 static inline unsigned int mv88e6xxx_num_databases(struct mv88e6xxx_chip *chip)
555 return chip->info->num_databases;
558 static inline unsigned int mv88e6xxx_num_ports(struct mv88e6xxx_chip *chip)
560 return chip->info->num_ports;
563 static inline u16 mv88e6xxx_port_mask(struct mv88e6xxx_chip *chip)
565 return GENMASK(mv88e6xxx_num_ports(chip) - 1, 0);
568 static inline unsigned int mv88e6xxx_num_gpio(struct mv88e6xxx_chip *chip)
570 return chip->info->num_gpio;
573 int mv88e6xxx_read(struct mv88e6xxx_chip *chip, int addr, int reg, u16 *val);
574 int mv88e6xxx_write(struct mv88e6xxx_chip *chip, int addr, int reg, u16 val);
575 int mv88e6xxx_update(struct mv88e6xxx_chip *chip, int addr, int reg,
577 int mv88e6xxx_wait(struct mv88e6xxx_chip *chip, int addr, int reg, u16 mask);
578 int mv88e6xxx_port_setup_mac(struct mv88e6xxx_chip *chip, int port, int link,
579 int speed, int duplex, int pause,
580 phy_interface_t mode);
581 struct mii_bus *mv88e6xxx_default_mdio_bus(struct mv88e6xxx_chip *chip);
583 static inline void mv88e6xxx_reg_lock(struct mv88e6xxx_chip *chip)
585 mutex_lock(&chip->reg_lock);
588 static inline void mv88e6xxx_reg_unlock(struct mv88e6xxx_chip *chip)
590 mutex_unlock(&chip->reg_lock);
593 #endif /* _MV88E6XXX_CHIP_H */