1 /* SPDX-License-Identifier: GPL-2.0-or-later */
3 * Marvell 88E6xxx Ethernet switch single-chip definition
5 * Copyright (c) 2008 Marvell Semiconductor
8 #ifndef _MV88E6XXX_CHIP_H
9 #define _MV88E6XXX_CHIP_H
11 #include <linux/if_vlan.h>
12 #include <linux/irq.h>
13 #include <linux/gpio/consumer.h>
14 #include <linux/kthread.h>
15 #include <linux/phy.h>
16 #include <linux/ptp_clock_kernel.h>
17 #include <linux/timecounter.h>
20 #define MV88E6XXX_N_FID 4096
22 /* PVT limits for 4-bit port and 5-bit switch */
23 #define MV88E6XXX_MAX_PVT_SWITCHES 32
24 #define MV88E6XXX_MAX_PVT_PORTS 16
26 #define MV88E6XXX_MAX_GPIO 16
28 enum mv88e6xxx_egress_mode {
29 MV88E6XXX_EGRESS_MODE_UNMODIFIED,
30 MV88E6XXX_EGRESS_MODE_UNTAGGED,
31 MV88E6XXX_EGRESS_MODE_TAGGED,
32 MV88E6XXX_EGRESS_MODE_ETHERTYPE,
35 enum mv88e6xxx_frame_mode {
36 MV88E6XXX_FRAME_MODE_NORMAL,
37 MV88E6XXX_FRAME_MODE_DSA,
38 MV88E6XXX_FRAME_MODE_PROVIDER,
39 MV88E6XXX_FRAME_MODE_ETHERTYPE,
42 /* List of supported models */
43 enum mv88e6xxx_model {
74 enum mv88e6xxx_family {
75 MV88E6XXX_FAMILY_NONE,
76 MV88E6XXX_FAMILY_6065, /* 6031 6035 6061 6065 */
77 MV88E6XXX_FAMILY_6095, /* 6092 6095 */
78 MV88E6XXX_FAMILY_6097, /* 6046 6085 6096 6097 */
79 MV88E6XXX_FAMILY_6165, /* 6123 6161 6165 */
80 MV88E6XXX_FAMILY_6185, /* 6108 6121 6122 6131 6152 6155 6182 6185 */
81 MV88E6XXX_FAMILY_6250, /* 6220 6250 */
82 MV88E6XXX_FAMILY_6320, /* 6320 6321 */
83 MV88E6XXX_FAMILY_6341, /* 6141 6341 */
84 MV88E6XXX_FAMILY_6351, /* 6171 6175 6350 6351 */
85 MV88E6XXX_FAMILY_6352, /* 6172 6176 6240 6352 */
86 MV88E6XXX_FAMILY_6390, /* 6190 6190X 6191 6290 6390 6390X */
91 struct mv88e6xxx_info {
92 enum mv88e6xxx_family family;
95 unsigned int num_databases;
96 unsigned int num_ports;
97 unsigned int num_internal_phys;
98 unsigned int num_gpio;
100 unsigned int port_base_addr;
101 unsigned int phy_base_addr;
102 unsigned int global1_addr;
103 unsigned int global2_addr;
104 unsigned int age_time_coeff;
105 unsigned int g1_irqs;
106 unsigned int g2_irqs;
109 /* Mark certain ports as invalid. This is required for example for the
110 * MV88E6220 (which is in general a MV88E6250 with 7 ports) but the
111 * ports 2-4 are not routet to pins.
113 unsigned int invalid_port_mask;
114 /* Multi-chip Addressing Mode.
115 * Some chips respond to only 2 registers of its own SMI device address
116 * when it is non-zero, and use indirect access to internal registers.
119 /* Dual-chip Addressing Mode
120 * Some chips respond to only half of the 32 SMI addresses,
121 * allowing two to coexist on the same SMI interface.
125 enum dsa_tag_protocol tag_protocol;
127 /* Mask for FromPort and ToPort value of PortVec used in ATU Move
128 * operation. 0 means that the ATU Move operation is not supported.
130 u8 atu_move_port_mask;
131 const struct mv88e6xxx_ops *ops;
137 struct mv88e6xxx_atu_entry {
144 struct mv88e6xxx_vtu_entry {
149 u8 member[DSA_MAX_PORTS];
150 u8 state[DSA_MAX_PORTS];
153 struct mv88e6xxx_bus_ops;
154 struct mv88e6xxx_irq_ops;
155 struct mv88e6xxx_gpio_ops;
156 struct mv88e6xxx_avb_ops;
157 struct mv88e6xxx_ptp_ops;
159 struct mv88e6xxx_irq {
161 struct irq_chip chip;
162 struct irq_domain *domain;
166 /* state flags for mv88e6xxx_port_hwtstamp::state */
168 MV88E6XXX_HWTSTAMP_ENABLED,
169 MV88E6XXX_HWTSTAMP_TX_IN_PROGRESS,
172 struct mv88e6xxx_port_hwtstamp {
176 /* Timestamping state */
179 /* Resources for receive timestamping */
180 struct sk_buff_head rx_queue;
181 struct sk_buff_head rx_queue2;
183 /* Resources for transmit timestamping */
184 unsigned long tx_tstamp_start;
185 struct sk_buff *tx_skb;
188 /* Current timestamp configuration */
189 struct hwtstamp_config tstamp_config;
192 struct mv88e6xxx_port {
193 struct mv88e6xxx_chip *chip;
196 u64 atu_member_violation;
197 u64 atu_miss_violation;
198 u64 atu_full_violation;
199 u64 vtu_member_violation;
200 u64 vtu_miss_violation;
202 unsigned int serdes_irq;
205 struct mv88e6xxx_chip {
206 const struct mv88e6xxx_info *info;
208 /* The dsa_switch this private structure is related to */
209 struct dsa_switch *ds;
211 /* The device this structure is associated to */
214 /* This mutex protects the access to the switch registers */
215 struct mutex reg_lock;
217 /* The MII bus and the address on the bus that is used to
218 * communication with the switch
220 const struct mv88e6xxx_bus_ops *smi_ops;
224 /* Handles automatic disabling and re-enabling of the PHY
227 const struct mv88e6xxx_bus_ops *phy_ops;
228 struct mutex ppu_mutex;
230 struct work_struct ppu_work;
231 struct timer_list ppu_timer;
233 /* This mutex serialises access to the statistics unit.
234 * Hold this mutex over snapshot + dump sequences.
236 struct mutex stats_mutex;
238 /* A switch may have a GPIO line tied to its reset pin. Parse
239 * this from the device tree, and use it before performing
242 struct gpio_desc *reset;
244 /* set to size of eeprom if supported by the switch */
247 /* List of mdio busses */
248 struct list_head mdios;
250 /* There can be two interrupt controllers, which are chained
251 * off a GPIO as interrupt source
253 struct mv88e6xxx_irq g1_irq;
254 struct mv88e6xxx_irq g2_irq;
261 struct kthread_worker *kworker;
262 struct kthread_delayed_work irq_poll_work;
267 /* This cyclecounter abstracts the switch PTP time.
268 * reg_lock must be held for any operation that read()s.
270 struct cyclecounter tstamp_cc;
271 struct timecounter tstamp_tc;
272 struct delayed_work overflow_work;
274 struct ptp_clock *ptp_clock;
275 struct ptp_clock_info ptp_clock_info;
276 struct delayed_work tai_event_work;
277 struct ptp_pin_desc pin_config[MV88E6XXX_MAX_GPIO];
282 /* Per-port timestamping resources. */
283 struct mv88e6xxx_port_hwtstamp port_hwtstamp[DSA_MAX_PORTS];
285 /* Array of port structures. */
286 struct mv88e6xxx_port ports[DSA_MAX_PORTS];
289 struct mv88e6xxx_bus_ops {
290 int (*read)(struct mv88e6xxx_chip *chip, int addr, int reg, u16 *val);
291 int (*write)(struct mv88e6xxx_chip *chip, int addr, int reg, u16 val);
294 struct mv88e6xxx_mdio_bus {
296 struct mv88e6xxx_chip *chip;
297 struct list_head list;
301 struct mv88e6xxx_ops {
302 /* Switch Setup Errata, called early in the switch setup to
303 * allow any errata actions to be performed
305 int (*setup_errata)(struct mv88e6xxx_chip *chip);
307 int (*ieee_pri_map)(struct mv88e6xxx_chip *chip);
308 int (*ip_pri_map)(struct mv88e6xxx_chip *chip);
310 /* Ingress Rate Limit unit (IRL) operations */
311 int (*irl_init_all)(struct mv88e6xxx_chip *chip, int port);
313 int (*get_eeprom)(struct mv88e6xxx_chip *chip,
314 struct ethtool_eeprom *eeprom, u8 *data);
315 int (*set_eeprom)(struct mv88e6xxx_chip *chip,
316 struct ethtool_eeprom *eeprom, u8 *data);
318 int (*set_switch_mac)(struct mv88e6xxx_chip *chip, u8 *addr);
320 int (*phy_read)(struct mv88e6xxx_chip *chip,
322 int addr, int reg, u16 *val);
323 int (*phy_write)(struct mv88e6xxx_chip *chip,
325 int addr, int reg, u16 val);
327 /* Priority Override Table operations */
328 int (*pot_clear)(struct mv88e6xxx_chip *chip);
330 /* PHY Polling Unit (PPU) operations */
331 int (*ppu_enable)(struct mv88e6xxx_chip *chip);
332 int (*ppu_disable)(struct mv88e6xxx_chip *chip);
334 /* Switch Software Reset */
335 int (*reset)(struct mv88e6xxx_chip *chip);
337 /* RGMII Receive/Transmit Timing Control
338 * Add delay on PHY_INTERFACE_MODE_RGMII_*ID, no delay otherwise.
340 int (*port_set_rgmii_delay)(struct mv88e6xxx_chip *chip, int port,
341 phy_interface_t mode);
343 #define LINK_FORCED_DOWN 0
344 #define LINK_FORCED_UP 1
345 #define LINK_UNFORCED -2
347 /* Port's MAC link state
348 * Use LINK_FORCED_UP or LINK_FORCED_DOWN to force link up or down,
349 * or LINK_UNFORCED for normal link detection.
351 int (*port_set_link)(struct mv88e6xxx_chip *chip, int port, int link);
353 #define DUPLEX_UNFORCED -2
355 /* Port's MAC duplex mode
357 * Use DUPLEX_HALF or DUPLEX_FULL to force half or full duplex,
358 * or DUPLEX_UNFORCED for normal duplex detection.
360 int (*port_set_duplex)(struct mv88e6xxx_chip *chip, int port, int dup);
365 /* Enable/disable sending Pause */
366 int (*port_set_pause)(struct mv88e6xxx_chip *chip, int port,
369 #define SPEED_MAX INT_MAX
370 #define SPEED_UNFORCED -2
372 /* Port's MAC speed (in Mbps)
374 * Depending on the chip, 10, 100, 200, 1000, 2500, 10000 are valid.
375 * Use SPEED_UNFORCED for normal detection, SPEED_MAX for max value.
377 int (*port_set_speed)(struct mv88e6xxx_chip *chip, int port, int speed);
379 /* What interface mode should be used for maximum speed? */
380 phy_interface_t (*port_max_speed_mode)(int port);
382 int (*port_tag_remap)(struct mv88e6xxx_chip *chip, int port);
384 int (*port_set_frame_mode)(struct mv88e6xxx_chip *chip, int port,
385 enum mv88e6xxx_frame_mode mode);
386 int (*port_set_egress_floods)(struct mv88e6xxx_chip *chip, int port,
387 bool unicast, bool multicast);
388 int (*port_set_ether_type)(struct mv88e6xxx_chip *chip, int port,
390 int (*port_set_jumbo_size)(struct mv88e6xxx_chip *chip, int port,
393 int (*port_egress_rate_limiting)(struct mv88e6xxx_chip *chip, int port);
394 int (*port_pause_limit)(struct mv88e6xxx_chip *chip, int port, u8 in,
396 int (*port_disable_learn_limit)(struct mv88e6xxx_chip *chip, int port);
397 int (*port_disable_pri_override)(struct mv88e6xxx_chip *chip, int port);
398 int (*port_setup_message_port)(struct mv88e6xxx_chip *chip, int port);
400 /* CMODE control what PHY mode the MAC will use, eg. SGMII, RGMII, etc.
401 * Some chips allow this to be configured on specific ports.
403 int (*port_set_cmode)(struct mv88e6xxx_chip *chip, int port,
404 phy_interface_t mode);
405 int (*port_get_cmode)(struct mv88e6xxx_chip *chip, int port, u8 *cmode);
407 /* Some devices have a per port register indicating what is
408 * the upstream port this port should forward to.
410 int (*port_set_upstream_port)(struct mv88e6xxx_chip *chip, int port,
412 /* Return the port link state, as required by phylink */
413 int (*port_link_state)(struct mv88e6xxx_chip *chip, int port,
414 struct phylink_link_state *state);
416 /* Snapshot the statistics for a port. The statistics can then
417 * be read back a leisure but still with a consistent view.
419 int (*stats_snapshot)(struct mv88e6xxx_chip *chip, int port);
421 /* Set the histogram mode for statistics, when the control registers
422 * are separated out of the STATS_OP register.
424 int (*stats_set_histogram)(struct mv88e6xxx_chip *chip);
426 /* Return the number of strings describing statistics */
427 int (*stats_get_sset_count)(struct mv88e6xxx_chip *chip);
428 int (*stats_get_strings)(struct mv88e6xxx_chip *chip, uint8_t *data);
429 int (*stats_get_stats)(struct mv88e6xxx_chip *chip, int port,
431 int (*set_cpu_port)(struct mv88e6xxx_chip *chip, int port);
432 int (*set_egress_port)(struct mv88e6xxx_chip *chip, int port);
434 #define MV88E6XXX_CASCADE_PORT_NONE 0xe
435 #define MV88E6XXX_CASCADE_PORT_MULTIPLE 0xf
437 int (*set_cascade_port)(struct mv88e6xxx_chip *chip, int port);
439 const struct mv88e6xxx_irq_ops *watchdog_ops;
441 int (*mgmt_rsvd2cpu)(struct mv88e6xxx_chip *chip);
443 /* Power on/off a SERDES interface */
444 int (*serdes_power)(struct mv88e6xxx_chip *chip, int port, u8 lane,
447 /* SERDES lane mapping */
448 u8 (*serdes_get_lane)(struct mv88e6xxx_chip *chip, int port);
450 /* SERDES interrupt handling */
451 unsigned int (*serdes_irq_mapping)(struct mv88e6xxx_chip *chip,
453 int (*serdes_irq_setup)(struct mv88e6xxx_chip *chip, int port);
454 void (*serdes_irq_free)(struct mv88e6xxx_chip *chip, int port);
455 int (*serdes_irq_enable)(struct mv88e6xxx_chip *chip, int port, u8 lane,
458 /* Statistics from the SERDES interface */
459 int (*serdes_get_sset_count)(struct mv88e6xxx_chip *chip, int port);
460 int (*serdes_get_strings)(struct mv88e6xxx_chip *chip, int port,
462 int (*serdes_get_stats)(struct mv88e6xxx_chip *chip, int port,
465 /* VLAN Translation Unit operations */
466 int (*vtu_getnext)(struct mv88e6xxx_chip *chip,
467 struct mv88e6xxx_vtu_entry *entry);
468 int (*vtu_loadpurge)(struct mv88e6xxx_chip *chip,
469 struct mv88e6xxx_vtu_entry *entry);
471 /* GPIO operations */
472 const struct mv88e6xxx_gpio_ops *gpio_ops;
474 /* Interface to the AVB/PTP registers */
475 const struct mv88e6xxx_avb_ops *avb_ops;
477 /* Remote Management Unit operations */
478 int (*rmu_disable)(struct mv88e6xxx_chip *chip);
480 /* Precision Time Protocol operations */
481 const struct mv88e6xxx_ptp_ops *ptp_ops;
484 void (*phylink_validate)(struct mv88e6xxx_chip *chip, int port,
486 struct phylink_link_state *state);
489 struct mv88e6xxx_irq_ops {
490 /* Action to be performed when the interrupt happens */
491 int (*irq_action)(struct mv88e6xxx_chip *chip, int irq);
492 /* Setup the hardware to generate the interrupt */
493 int (*irq_setup)(struct mv88e6xxx_chip *chip);
494 /* Reset the hardware to stop generating the interrupt */
495 void (*irq_free)(struct mv88e6xxx_chip *chip);
498 struct mv88e6xxx_gpio_ops {
499 /* Get/set data on GPIO pin */
500 int (*get_data)(struct mv88e6xxx_chip *chip, unsigned int pin);
501 int (*set_data)(struct mv88e6xxx_chip *chip, unsigned int pin,
504 /* get/set GPIO direction */
505 int (*get_dir)(struct mv88e6xxx_chip *chip, unsigned int pin);
506 int (*set_dir)(struct mv88e6xxx_chip *chip, unsigned int pin,
509 /* get/set GPIO pin control */
510 int (*get_pctl)(struct mv88e6xxx_chip *chip, unsigned int pin,
512 int (*set_pctl)(struct mv88e6xxx_chip *chip, unsigned int pin,
516 struct mv88e6xxx_avb_ops {
517 /* Access port-scoped Precision Time Protocol registers */
518 int (*port_ptp_read)(struct mv88e6xxx_chip *chip, int port, int addr,
520 int (*port_ptp_write)(struct mv88e6xxx_chip *chip, int port, int addr,
523 /* Access global Precision Time Protocol registers */
524 int (*ptp_read)(struct mv88e6xxx_chip *chip, int addr, u16 *data,
526 int (*ptp_write)(struct mv88e6xxx_chip *chip, int addr, u16 data);
528 /* Access global Time Application Interface registers */
529 int (*tai_read)(struct mv88e6xxx_chip *chip, int addr, u16 *data,
531 int (*tai_write)(struct mv88e6xxx_chip *chip, int addr, u16 data);
534 struct mv88e6xxx_ptp_ops {
535 u64 (*clock_read)(const struct cyclecounter *cc);
536 int (*ptp_enable)(struct ptp_clock_info *ptp,
537 struct ptp_clock_request *rq, int on);
538 int (*ptp_verify)(struct ptp_clock_info *ptp, unsigned int pin,
539 enum ptp_pin_function func, unsigned int chan);
540 void (*event_work)(struct work_struct *ugly);
541 int (*port_enable)(struct mv88e6xxx_chip *chip, int port);
542 int (*port_disable)(struct mv88e6xxx_chip *chip, int port);
543 int (*global_enable)(struct mv88e6xxx_chip *chip);
544 int (*global_disable)(struct mv88e6xxx_chip *chip);
556 #define STATS_TYPE_PORT BIT(0)
557 #define STATS_TYPE_BANK0 BIT(1)
558 #define STATS_TYPE_BANK1 BIT(2)
560 struct mv88e6xxx_hw_stat {
561 char string[ETH_GSTRING_LEN];
567 static inline bool mv88e6xxx_has_pvt(struct mv88e6xxx_chip *chip)
569 return chip->info->pvt;
572 static inline unsigned int mv88e6xxx_num_databases(struct mv88e6xxx_chip *chip)
574 return chip->info->num_databases;
577 static inline unsigned int mv88e6xxx_num_ports(struct mv88e6xxx_chip *chip)
579 return chip->info->num_ports;
582 static inline u16 mv88e6xxx_port_mask(struct mv88e6xxx_chip *chip)
584 return GENMASK(mv88e6xxx_num_ports(chip) - 1, 0);
587 static inline unsigned int mv88e6xxx_num_gpio(struct mv88e6xxx_chip *chip)
589 return chip->info->num_gpio;
592 static inline bool mv88e6xxx_is_invalid_port(struct mv88e6xxx_chip *chip, int port)
594 return (chip->info->invalid_port_mask & BIT(port)) != 0;
597 int mv88e6xxx_read(struct mv88e6xxx_chip *chip, int addr, int reg, u16 *val);
598 int mv88e6xxx_write(struct mv88e6xxx_chip *chip, int addr, int reg, u16 val);
599 int mv88e6xxx_wait_mask(struct mv88e6xxx_chip *chip, int addr, int reg,
601 int mv88e6xxx_wait_bit(struct mv88e6xxx_chip *chip, int addr, int reg,
603 int mv88e6xxx_port_setup_mac(struct mv88e6xxx_chip *chip, int port, int link,
604 int speed, int duplex, int pause,
605 phy_interface_t mode);
606 struct mii_bus *mv88e6xxx_default_mdio_bus(struct mv88e6xxx_chip *chip);
608 static inline void mv88e6xxx_reg_lock(struct mv88e6xxx_chip *chip)
610 mutex_lock(&chip->reg_lock);
613 static inline void mv88e6xxx_reg_unlock(struct mv88e6xxx_chip *chip)
615 mutex_unlock(&chip->reg_lock);
618 #endif /* _MV88E6XXX_CHIP_H */